| 1 | #ifdef GET_RISCVMaskedPseudosTable_DECL |
|---|---|
| 2 | const RISCVMaskedPseudoInfo *getMaskedPseudoInfo(unsigned MaskedPseudo); |
| 3 | const RISCVMaskedPseudoInfo *lookupMaskedIntrinsicByUnmasked(unsigned UnmaskedPseudo); |
| 4 | #endif |
| 5 | |
| 6 | #ifdef GET_RISCVMaskedPseudosTable_IMPL |
| 7 | constexpr RISCVMaskedPseudoInfo RISCVMaskedPseudosTable[] = { |
| 8 | { PseudoTHVdotVMAQASU_VV_M1_MASK, PseudoTHVdotVMAQASU_VV_M1, 0x3, false }, // 0 |
| 9 | { PseudoTHVdotVMAQASU_VV_M2_MASK, PseudoTHVdotVMAQASU_VV_M2, 0x3, false }, // 1 |
| 10 | { PseudoTHVdotVMAQASU_VV_M4_MASK, PseudoTHVdotVMAQASU_VV_M4, 0x3, false }, // 2 |
| 11 | { PseudoTHVdotVMAQASU_VV_M8_MASK, PseudoTHVdotVMAQASU_VV_M8, 0x3, false }, // 3 |
| 12 | { PseudoTHVdotVMAQASU_VV_MF2_MASK, PseudoTHVdotVMAQASU_VV_MF2, 0x3, false }, // 4 |
| 13 | { PseudoTHVdotVMAQASU_VX_M1_MASK, PseudoTHVdotVMAQASU_VX_M1, 0x3, false }, // 5 |
| 14 | { PseudoTHVdotVMAQASU_VX_M2_MASK, PseudoTHVdotVMAQASU_VX_M2, 0x3, false }, // 6 |
| 15 | { PseudoTHVdotVMAQASU_VX_M4_MASK, PseudoTHVdotVMAQASU_VX_M4, 0x3, false }, // 7 |
| 16 | { PseudoTHVdotVMAQASU_VX_M8_MASK, PseudoTHVdotVMAQASU_VX_M8, 0x3, false }, // 8 |
| 17 | { PseudoTHVdotVMAQASU_VX_MF2_MASK, PseudoTHVdotVMAQASU_VX_MF2, 0x3, false }, // 9 |
| 18 | { PseudoTHVdotVMAQAUS_VX_M1_MASK, PseudoTHVdotVMAQAUS_VX_M1, 0x3, false }, // 10 |
| 19 | { PseudoTHVdotVMAQAUS_VX_M2_MASK, PseudoTHVdotVMAQAUS_VX_M2, 0x3, false }, // 11 |
| 20 | { PseudoTHVdotVMAQAUS_VX_M4_MASK, PseudoTHVdotVMAQAUS_VX_M4, 0x3, false }, // 12 |
| 21 | { PseudoTHVdotVMAQAUS_VX_M8_MASK, PseudoTHVdotVMAQAUS_VX_M8, 0x3, false }, // 13 |
| 22 | { PseudoTHVdotVMAQAUS_VX_MF2_MASK, PseudoTHVdotVMAQAUS_VX_MF2, 0x3, false }, // 14 |
| 23 | { PseudoTHVdotVMAQAU_VV_M1_MASK, PseudoTHVdotVMAQAU_VV_M1, 0x3, false }, // 15 |
| 24 | { PseudoTHVdotVMAQAU_VV_M2_MASK, PseudoTHVdotVMAQAU_VV_M2, 0x3, false }, // 16 |
| 25 | { PseudoTHVdotVMAQAU_VV_M4_MASK, PseudoTHVdotVMAQAU_VV_M4, 0x3, false }, // 17 |
| 26 | { PseudoTHVdotVMAQAU_VV_M8_MASK, PseudoTHVdotVMAQAU_VV_M8, 0x3, false }, // 18 |
| 27 | { PseudoTHVdotVMAQAU_VV_MF2_MASK, PseudoTHVdotVMAQAU_VV_MF2, 0x3, false }, // 19 |
| 28 | { PseudoTHVdotVMAQAU_VX_M1_MASK, PseudoTHVdotVMAQAU_VX_M1, 0x3, false }, // 20 |
| 29 | { PseudoTHVdotVMAQAU_VX_M2_MASK, PseudoTHVdotVMAQAU_VX_M2, 0x3, false }, // 21 |
| 30 | { PseudoTHVdotVMAQAU_VX_M4_MASK, PseudoTHVdotVMAQAU_VX_M4, 0x3, false }, // 22 |
| 31 | { PseudoTHVdotVMAQAU_VX_M8_MASK, PseudoTHVdotVMAQAU_VX_M8, 0x3, false }, // 23 |
| 32 | { PseudoTHVdotVMAQAU_VX_MF2_MASK, PseudoTHVdotVMAQAU_VX_MF2, 0x3, false }, // 24 |
| 33 | { PseudoTHVdotVMAQA_VV_M1_MASK, PseudoTHVdotVMAQA_VV_M1, 0x3, false }, // 25 |
| 34 | { PseudoTHVdotVMAQA_VV_M2_MASK, PseudoTHVdotVMAQA_VV_M2, 0x3, false }, // 26 |
| 35 | { PseudoTHVdotVMAQA_VV_M4_MASK, PseudoTHVdotVMAQA_VV_M4, 0x3, false }, // 27 |
| 36 | { PseudoTHVdotVMAQA_VV_M8_MASK, PseudoTHVdotVMAQA_VV_M8, 0x3, false }, // 28 |
| 37 | { PseudoTHVdotVMAQA_VV_MF2_MASK, PseudoTHVdotVMAQA_VV_MF2, 0x3, false }, // 29 |
| 38 | { PseudoTHVdotVMAQA_VX_M1_MASK, PseudoTHVdotVMAQA_VX_M1, 0x3, false }, // 30 |
| 39 | { PseudoTHVdotVMAQA_VX_M2_MASK, PseudoTHVdotVMAQA_VX_M2, 0x3, false }, // 31 |
| 40 | { PseudoTHVdotVMAQA_VX_M4_MASK, PseudoTHVdotVMAQA_VX_M4, 0x3, false }, // 32 |
| 41 | { PseudoTHVdotVMAQA_VX_M8_MASK, PseudoTHVdotVMAQA_VX_M8, 0x3, false }, // 33 |
| 42 | { PseudoTHVdotVMAQA_VX_MF2_MASK, PseudoTHVdotVMAQA_VX_MF2, 0x3, false }, // 34 |
| 43 | { PseudoVAADDU_VV_M1_MASK, PseudoVAADDU_VV_M1, 0x3, false }, // 35 |
| 44 | { PseudoVAADDU_VV_M2_MASK, PseudoVAADDU_VV_M2, 0x3, false }, // 36 |
| 45 | { PseudoVAADDU_VV_M4_MASK, PseudoVAADDU_VV_M4, 0x3, false }, // 37 |
| 46 | { PseudoVAADDU_VV_M8_MASK, PseudoVAADDU_VV_M8, 0x3, false }, // 38 |
| 47 | { PseudoVAADDU_VV_MF2_MASK, PseudoVAADDU_VV_MF2, 0x3, false }, // 39 |
| 48 | { PseudoVAADDU_VV_MF4_MASK, PseudoVAADDU_VV_MF4, 0x3, false }, // 40 |
| 49 | { PseudoVAADDU_VV_MF8_MASK, PseudoVAADDU_VV_MF8, 0x3, false }, // 41 |
| 50 | { PseudoVAADDU_VX_M1_MASK, PseudoVAADDU_VX_M1, 0x3, false }, // 42 |
| 51 | { PseudoVAADDU_VX_M2_MASK, PseudoVAADDU_VX_M2, 0x3, false }, // 43 |
| 52 | { PseudoVAADDU_VX_M4_MASK, PseudoVAADDU_VX_M4, 0x3, false }, // 44 |
| 53 | { PseudoVAADDU_VX_M8_MASK, PseudoVAADDU_VX_M8, 0x3, false }, // 45 |
| 54 | { PseudoVAADDU_VX_MF2_MASK, PseudoVAADDU_VX_MF2, 0x3, false }, // 46 |
| 55 | { PseudoVAADDU_VX_MF4_MASK, PseudoVAADDU_VX_MF4, 0x3, false }, // 47 |
| 56 | { PseudoVAADDU_VX_MF8_MASK, PseudoVAADDU_VX_MF8, 0x3, false }, // 48 |
| 57 | { PseudoVAADD_VV_M1_MASK, PseudoVAADD_VV_M1, 0x3, false }, // 49 |
| 58 | { PseudoVAADD_VV_M2_MASK, PseudoVAADD_VV_M2, 0x3, false }, // 50 |
| 59 | { PseudoVAADD_VV_M4_MASK, PseudoVAADD_VV_M4, 0x3, false }, // 51 |
| 60 | { PseudoVAADD_VV_M8_MASK, PseudoVAADD_VV_M8, 0x3, false }, // 52 |
| 61 | { PseudoVAADD_VV_MF2_MASK, PseudoVAADD_VV_MF2, 0x3, false }, // 53 |
| 62 | { PseudoVAADD_VV_MF4_MASK, PseudoVAADD_VV_MF4, 0x3, false }, // 54 |
| 63 | { PseudoVAADD_VV_MF8_MASK, PseudoVAADD_VV_MF8, 0x3, false }, // 55 |
| 64 | { PseudoVAADD_VX_M1_MASK, PseudoVAADD_VX_M1, 0x3, false }, // 56 |
| 65 | { PseudoVAADD_VX_M2_MASK, PseudoVAADD_VX_M2, 0x3, false }, // 57 |
| 66 | { PseudoVAADD_VX_M4_MASK, PseudoVAADD_VX_M4, 0x3, false }, // 58 |
| 67 | { PseudoVAADD_VX_M8_MASK, PseudoVAADD_VX_M8, 0x3, false }, // 59 |
| 68 | { PseudoVAADD_VX_MF2_MASK, PseudoVAADD_VX_MF2, 0x3, false }, // 60 |
| 69 | { PseudoVAADD_VX_MF4_MASK, PseudoVAADD_VX_MF4, 0x3, false }, // 61 |
| 70 | { PseudoVAADD_VX_MF8_MASK, PseudoVAADD_VX_MF8, 0x3, false }, // 62 |
| 71 | { PseudoVADD_VI_M1_MASK, PseudoVADD_VI_M1, 0x3, false }, // 63 |
| 72 | { PseudoVADD_VI_M2_MASK, PseudoVADD_VI_M2, 0x3, false }, // 64 |
| 73 | { PseudoVADD_VI_M4_MASK, PseudoVADD_VI_M4, 0x3, false }, // 65 |
| 74 | { PseudoVADD_VI_M8_MASK, PseudoVADD_VI_M8, 0x3, false }, // 66 |
| 75 | { PseudoVADD_VI_MF2_MASK, PseudoVADD_VI_MF2, 0x3, false }, // 67 |
| 76 | { PseudoVADD_VI_MF4_MASK, PseudoVADD_VI_MF4, 0x3, false }, // 68 |
| 77 | { PseudoVADD_VI_MF8_MASK, PseudoVADD_VI_MF8, 0x3, false }, // 69 |
| 78 | { PseudoVADD_VV_M1_MASK, PseudoVADD_VV_M1, 0x3, false }, // 70 |
| 79 | { PseudoVADD_VV_M2_MASK, PseudoVADD_VV_M2, 0x3, false }, // 71 |
| 80 | { PseudoVADD_VV_M4_MASK, PseudoVADD_VV_M4, 0x3, false }, // 72 |
| 81 | { PseudoVADD_VV_M8_MASK, PseudoVADD_VV_M8, 0x3, false }, // 73 |
| 82 | { PseudoVADD_VV_MF2_MASK, PseudoVADD_VV_MF2, 0x3, false }, // 74 |
| 83 | { PseudoVADD_VV_MF4_MASK, PseudoVADD_VV_MF4, 0x3, false }, // 75 |
| 84 | { PseudoVADD_VV_MF8_MASK, PseudoVADD_VV_MF8, 0x3, false }, // 76 |
| 85 | { PseudoVADD_VX_M1_MASK, PseudoVADD_VX_M1, 0x3, false }, // 77 |
| 86 | { PseudoVADD_VX_M2_MASK, PseudoVADD_VX_M2, 0x3, false }, // 78 |
| 87 | { PseudoVADD_VX_M4_MASK, PseudoVADD_VX_M4, 0x3, false }, // 79 |
| 88 | { PseudoVADD_VX_M8_MASK, PseudoVADD_VX_M8, 0x3, false }, // 80 |
| 89 | { PseudoVADD_VX_MF2_MASK, PseudoVADD_VX_MF2, 0x3, false }, // 81 |
| 90 | { PseudoVADD_VX_MF4_MASK, PseudoVADD_VX_MF4, 0x3, false }, // 82 |
| 91 | { PseudoVADD_VX_MF8_MASK, PseudoVADD_VX_MF8, 0x3, false }, // 83 |
| 92 | { PseudoVANDN_VV_M1_MASK, PseudoVANDN_VV_M1, 0x3, false }, // 84 |
| 93 | { PseudoVANDN_VV_M2_MASK, PseudoVANDN_VV_M2, 0x3, false }, // 85 |
| 94 | { PseudoVANDN_VV_M4_MASK, PseudoVANDN_VV_M4, 0x3, false }, // 86 |
| 95 | { PseudoVANDN_VV_M8_MASK, PseudoVANDN_VV_M8, 0x3, false }, // 87 |
| 96 | { PseudoVANDN_VV_MF2_MASK, PseudoVANDN_VV_MF2, 0x3, false }, // 88 |
| 97 | { PseudoVANDN_VV_MF4_MASK, PseudoVANDN_VV_MF4, 0x3, false }, // 89 |
| 98 | { PseudoVANDN_VV_MF8_MASK, PseudoVANDN_VV_MF8, 0x3, false }, // 90 |
| 99 | { PseudoVANDN_VX_M1_MASK, PseudoVANDN_VX_M1, 0x3, false }, // 91 |
| 100 | { PseudoVANDN_VX_M2_MASK, PseudoVANDN_VX_M2, 0x3, false }, // 92 |
| 101 | { PseudoVANDN_VX_M4_MASK, PseudoVANDN_VX_M4, 0x3, false }, // 93 |
| 102 | { PseudoVANDN_VX_M8_MASK, PseudoVANDN_VX_M8, 0x3, false }, // 94 |
| 103 | { PseudoVANDN_VX_MF2_MASK, PseudoVANDN_VX_MF2, 0x3, false }, // 95 |
| 104 | { PseudoVANDN_VX_MF4_MASK, PseudoVANDN_VX_MF4, 0x3, false }, // 96 |
| 105 | { PseudoVANDN_VX_MF8_MASK, PseudoVANDN_VX_MF8, 0x3, false }, // 97 |
| 106 | { PseudoVAND_VI_M1_MASK, PseudoVAND_VI_M1, 0x3, false }, // 98 |
| 107 | { PseudoVAND_VI_M2_MASK, PseudoVAND_VI_M2, 0x3, false }, // 99 |
| 108 | { PseudoVAND_VI_M4_MASK, PseudoVAND_VI_M4, 0x3, false }, // 100 |
| 109 | { PseudoVAND_VI_M8_MASK, PseudoVAND_VI_M8, 0x3, false }, // 101 |
| 110 | { PseudoVAND_VI_MF2_MASK, PseudoVAND_VI_MF2, 0x3, false }, // 102 |
| 111 | { PseudoVAND_VI_MF4_MASK, PseudoVAND_VI_MF4, 0x3, false }, // 103 |
| 112 | { PseudoVAND_VI_MF8_MASK, PseudoVAND_VI_MF8, 0x3, false }, // 104 |
| 113 | { PseudoVAND_VV_M1_MASK, PseudoVAND_VV_M1, 0x3, false }, // 105 |
| 114 | { PseudoVAND_VV_M2_MASK, PseudoVAND_VV_M2, 0x3, false }, // 106 |
| 115 | { PseudoVAND_VV_M4_MASK, PseudoVAND_VV_M4, 0x3, false }, // 107 |
| 116 | { PseudoVAND_VV_M8_MASK, PseudoVAND_VV_M8, 0x3, false }, // 108 |
| 117 | { PseudoVAND_VV_MF2_MASK, PseudoVAND_VV_MF2, 0x3, false }, // 109 |
| 118 | { PseudoVAND_VV_MF4_MASK, PseudoVAND_VV_MF4, 0x3, false }, // 110 |
| 119 | { PseudoVAND_VV_MF8_MASK, PseudoVAND_VV_MF8, 0x3, false }, // 111 |
| 120 | { PseudoVAND_VX_M1_MASK, PseudoVAND_VX_M1, 0x3, false }, // 112 |
| 121 | { PseudoVAND_VX_M2_MASK, PseudoVAND_VX_M2, 0x3, false }, // 113 |
| 122 | { PseudoVAND_VX_M4_MASK, PseudoVAND_VX_M4, 0x3, false }, // 114 |
| 123 | { PseudoVAND_VX_M8_MASK, PseudoVAND_VX_M8, 0x3, false }, // 115 |
| 124 | { PseudoVAND_VX_MF2_MASK, PseudoVAND_VX_MF2, 0x3, false }, // 116 |
| 125 | { PseudoVAND_VX_MF4_MASK, PseudoVAND_VX_MF4, 0x3, false }, // 117 |
| 126 | { PseudoVAND_VX_MF8_MASK, PseudoVAND_VX_MF8, 0x3, false }, // 118 |
| 127 | { PseudoVASUBU_VV_M1_MASK, PseudoVASUBU_VV_M1, 0x3, false }, // 119 |
| 128 | { PseudoVASUBU_VV_M2_MASK, PseudoVASUBU_VV_M2, 0x3, false }, // 120 |
| 129 | { PseudoVASUBU_VV_M4_MASK, PseudoVASUBU_VV_M4, 0x3, false }, // 121 |
| 130 | { PseudoVASUBU_VV_M8_MASK, PseudoVASUBU_VV_M8, 0x3, false }, // 122 |
| 131 | { PseudoVASUBU_VV_MF2_MASK, PseudoVASUBU_VV_MF2, 0x3, false }, // 123 |
| 132 | { PseudoVASUBU_VV_MF4_MASK, PseudoVASUBU_VV_MF4, 0x3, false }, // 124 |
| 133 | { PseudoVASUBU_VV_MF8_MASK, PseudoVASUBU_VV_MF8, 0x3, false }, // 125 |
| 134 | { PseudoVASUBU_VX_M1_MASK, PseudoVASUBU_VX_M1, 0x3, false }, // 126 |
| 135 | { PseudoVASUBU_VX_M2_MASK, PseudoVASUBU_VX_M2, 0x3, false }, // 127 |
| 136 | { PseudoVASUBU_VX_M4_MASK, PseudoVASUBU_VX_M4, 0x3, false }, // 128 |
| 137 | { PseudoVASUBU_VX_M8_MASK, PseudoVASUBU_VX_M8, 0x3, false }, // 129 |
| 138 | { PseudoVASUBU_VX_MF2_MASK, PseudoVASUBU_VX_MF2, 0x3, false }, // 130 |
| 139 | { PseudoVASUBU_VX_MF4_MASK, PseudoVASUBU_VX_MF4, 0x3, false }, // 131 |
| 140 | { PseudoVASUBU_VX_MF8_MASK, PseudoVASUBU_VX_MF8, 0x3, false }, // 132 |
| 141 | { PseudoVASUB_VV_M1_MASK, PseudoVASUB_VV_M1, 0x3, false }, // 133 |
| 142 | { PseudoVASUB_VV_M2_MASK, PseudoVASUB_VV_M2, 0x3, false }, // 134 |
| 143 | { PseudoVASUB_VV_M4_MASK, PseudoVASUB_VV_M4, 0x3, false }, // 135 |
| 144 | { PseudoVASUB_VV_M8_MASK, PseudoVASUB_VV_M8, 0x3, false }, // 136 |
| 145 | { PseudoVASUB_VV_MF2_MASK, PseudoVASUB_VV_MF2, 0x3, false }, // 137 |
| 146 | { PseudoVASUB_VV_MF4_MASK, PseudoVASUB_VV_MF4, 0x3, false }, // 138 |
| 147 | { PseudoVASUB_VV_MF8_MASK, PseudoVASUB_VV_MF8, 0x3, false }, // 139 |
| 148 | { PseudoVASUB_VX_M1_MASK, PseudoVASUB_VX_M1, 0x3, false }, // 140 |
| 149 | { PseudoVASUB_VX_M2_MASK, PseudoVASUB_VX_M2, 0x3, false }, // 141 |
| 150 | { PseudoVASUB_VX_M4_MASK, PseudoVASUB_VX_M4, 0x3, false }, // 142 |
| 151 | { PseudoVASUB_VX_M8_MASK, PseudoVASUB_VX_M8, 0x3, false }, // 143 |
| 152 | { PseudoVASUB_VX_MF2_MASK, PseudoVASUB_VX_MF2, 0x3, false }, // 144 |
| 153 | { PseudoVASUB_VX_MF4_MASK, PseudoVASUB_VX_MF4, 0x3, false }, // 145 |
| 154 | { PseudoVASUB_VX_MF8_MASK, PseudoVASUB_VX_MF8, 0x3, false }, // 146 |
| 155 | { PseudoVBREV8_V_M1_MASK, PseudoVBREV8_V_M1, 0x2, false }, // 147 |
| 156 | { PseudoVBREV8_V_M2_MASK, PseudoVBREV8_V_M2, 0x2, false }, // 148 |
| 157 | { PseudoVBREV8_V_M4_MASK, PseudoVBREV8_V_M4, 0x2, false }, // 149 |
| 158 | { PseudoVBREV8_V_M8_MASK, PseudoVBREV8_V_M8, 0x2, false }, // 150 |
| 159 | { PseudoVBREV8_V_MF2_MASK, PseudoVBREV8_V_MF2, 0x2, false }, // 151 |
| 160 | { PseudoVBREV8_V_MF4_MASK, PseudoVBREV8_V_MF4, 0x2, false }, // 152 |
| 161 | { PseudoVBREV8_V_MF8_MASK, PseudoVBREV8_V_MF8, 0x2, false }, // 153 |
| 162 | { PseudoVBREV_V_M1_MASK, PseudoVBREV_V_M1, 0x2, false }, // 154 |
| 163 | { PseudoVBREV_V_M2_MASK, PseudoVBREV_V_M2, 0x2, false }, // 155 |
| 164 | { PseudoVBREV_V_M4_MASK, PseudoVBREV_V_M4, 0x2, false }, // 156 |
| 165 | { PseudoVBREV_V_M8_MASK, PseudoVBREV_V_M8, 0x2, false }, // 157 |
| 166 | { PseudoVBREV_V_MF2_MASK, PseudoVBREV_V_MF2, 0x2, false }, // 158 |
| 167 | { PseudoVBREV_V_MF4_MASK, PseudoVBREV_V_MF4, 0x2, false }, // 159 |
| 168 | { PseudoVBREV_V_MF8_MASK, PseudoVBREV_V_MF8, 0x2, false }, // 160 |
| 169 | { PseudoVCLMULH_VV_M1_MASK, PseudoVCLMULH_VV_M1, 0x3, false }, // 161 |
| 170 | { PseudoVCLMULH_VV_M2_MASK, PseudoVCLMULH_VV_M2, 0x3, false }, // 162 |
| 171 | { PseudoVCLMULH_VV_M4_MASK, PseudoVCLMULH_VV_M4, 0x3, false }, // 163 |
| 172 | { PseudoVCLMULH_VV_M8_MASK, PseudoVCLMULH_VV_M8, 0x3, false }, // 164 |
| 173 | { PseudoVCLMULH_VV_MF2_MASK, PseudoVCLMULH_VV_MF2, 0x3, false }, // 165 |
| 174 | { PseudoVCLMULH_VV_MF4_MASK, PseudoVCLMULH_VV_MF4, 0x3, false }, // 166 |
| 175 | { PseudoVCLMULH_VV_MF8_MASK, PseudoVCLMULH_VV_MF8, 0x3, false }, // 167 |
| 176 | { PseudoVCLMULH_VX_M1_MASK, PseudoVCLMULH_VX_M1, 0x3, false }, // 168 |
| 177 | { PseudoVCLMULH_VX_M2_MASK, PseudoVCLMULH_VX_M2, 0x3, false }, // 169 |
| 178 | { PseudoVCLMULH_VX_M4_MASK, PseudoVCLMULH_VX_M4, 0x3, false }, // 170 |
| 179 | { PseudoVCLMULH_VX_M8_MASK, PseudoVCLMULH_VX_M8, 0x3, false }, // 171 |
| 180 | { PseudoVCLMULH_VX_MF2_MASK, PseudoVCLMULH_VX_MF2, 0x3, false }, // 172 |
| 181 | { PseudoVCLMULH_VX_MF4_MASK, PseudoVCLMULH_VX_MF4, 0x3, false }, // 173 |
| 182 | { PseudoVCLMULH_VX_MF8_MASK, PseudoVCLMULH_VX_MF8, 0x3, false }, // 174 |
| 183 | { PseudoVCLMUL_VV_M1_MASK, PseudoVCLMUL_VV_M1, 0x3, false }, // 175 |
| 184 | { PseudoVCLMUL_VV_M2_MASK, PseudoVCLMUL_VV_M2, 0x3, false }, // 176 |
| 185 | { PseudoVCLMUL_VV_M4_MASK, PseudoVCLMUL_VV_M4, 0x3, false }, // 177 |
| 186 | { PseudoVCLMUL_VV_M8_MASK, PseudoVCLMUL_VV_M8, 0x3, false }, // 178 |
| 187 | { PseudoVCLMUL_VV_MF2_MASK, PseudoVCLMUL_VV_MF2, 0x3, false }, // 179 |
| 188 | { PseudoVCLMUL_VV_MF4_MASK, PseudoVCLMUL_VV_MF4, 0x3, false }, // 180 |
| 189 | { PseudoVCLMUL_VV_MF8_MASK, PseudoVCLMUL_VV_MF8, 0x3, false }, // 181 |
| 190 | { PseudoVCLMUL_VX_M1_MASK, PseudoVCLMUL_VX_M1, 0x3, false }, // 182 |
| 191 | { PseudoVCLMUL_VX_M2_MASK, PseudoVCLMUL_VX_M2, 0x3, false }, // 183 |
| 192 | { PseudoVCLMUL_VX_M4_MASK, PseudoVCLMUL_VX_M4, 0x3, false }, // 184 |
| 193 | { PseudoVCLMUL_VX_M8_MASK, PseudoVCLMUL_VX_M8, 0x3, false }, // 185 |
| 194 | { PseudoVCLMUL_VX_MF2_MASK, PseudoVCLMUL_VX_MF2, 0x3, false }, // 186 |
| 195 | { PseudoVCLMUL_VX_MF4_MASK, PseudoVCLMUL_VX_MF4, 0x3, false }, // 187 |
| 196 | { PseudoVCLMUL_VX_MF8_MASK, PseudoVCLMUL_VX_MF8, 0x3, false }, // 188 |
| 197 | { PseudoVCLZ_V_M1_MASK, PseudoVCLZ_V_M1, 0x2, false }, // 189 |
| 198 | { PseudoVCLZ_V_M2_MASK, PseudoVCLZ_V_M2, 0x2, false }, // 190 |
| 199 | { PseudoVCLZ_V_M4_MASK, PseudoVCLZ_V_M4, 0x2, false }, // 191 |
| 200 | { PseudoVCLZ_V_M8_MASK, PseudoVCLZ_V_M8, 0x2, false }, // 192 |
| 201 | { PseudoVCLZ_V_MF2_MASK, PseudoVCLZ_V_MF2, 0x2, false }, // 193 |
| 202 | { PseudoVCLZ_V_MF4_MASK, PseudoVCLZ_V_MF4, 0x2, false }, // 194 |
| 203 | { PseudoVCLZ_V_MF8_MASK, PseudoVCLZ_V_MF8, 0x2, false }, // 195 |
| 204 | { PseudoVCPOP_V_M1_MASK, PseudoVCPOP_V_M1, 0x2, false }, // 196 |
| 205 | { PseudoVCPOP_V_M2_MASK, PseudoVCPOP_V_M2, 0x2, false }, // 197 |
| 206 | { PseudoVCPOP_V_M4_MASK, PseudoVCPOP_V_M4, 0x2, false }, // 198 |
| 207 | { PseudoVCPOP_V_M8_MASK, PseudoVCPOP_V_M8, 0x2, false }, // 199 |
| 208 | { PseudoVCPOP_V_MF2_MASK, PseudoVCPOP_V_MF2, 0x2, false }, // 200 |
| 209 | { PseudoVCPOP_V_MF4_MASK, PseudoVCPOP_V_MF4, 0x2, false }, // 201 |
| 210 | { PseudoVCPOP_V_MF8_MASK, PseudoVCPOP_V_MF8, 0x2, false }, // 202 |
| 211 | { PseudoVCTZ_V_M1_MASK, PseudoVCTZ_V_M1, 0x2, false }, // 203 |
| 212 | { PseudoVCTZ_V_M2_MASK, PseudoVCTZ_V_M2, 0x2, false }, // 204 |
| 213 | { PseudoVCTZ_V_M4_MASK, PseudoVCTZ_V_M4, 0x2, false }, // 205 |
| 214 | { PseudoVCTZ_V_M8_MASK, PseudoVCTZ_V_M8, 0x2, false }, // 206 |
| 215 | { PseudoVCTZ_V_MF2_MASK, PseudoVCTZ_V_MF2, 0x2, false }, // 207 |
| 216 | { PseudoVCTZ_V_MF4_MASK, PseudoVCTZ_V_MF4, 0x2, false }, // 208 |
| 217 | { PseudoVCTZ_V_MF8_MASK, PseudoVCTZ_V_MF8, 0x2, false }, // 209 |
| 218 | { PseudoVDIVU_VV_M1_E16_MASK, PseudoVDIVU_VV_M1_E16, 0x3, false }, // 210 |
| 219 | { PseudoVDIVU_VV_M1_E32_MASK, PseudoVDIVU_VV_M1_E32, 0x3, false }, // 211 |
| 220 | { PseudoVDIVU_VV_M1_E64_MASK, PseudoVDIVU_VV_M1_E64, 0x3, false }, // 212 |
| 221 | { PseudoVDIVU_VV_M1_E8_MASK, PseudoVDIVU_VV_M1_E8, 0x3, false }, // 213 |
| 222 | { PseudoVDIVU_VV_M2_E16_MASK, PseudoVDIVU_VV_M2_E16, 0x3, false }, // 214 |
| 223 | { PseudoVDIVU_VV_M2_E32_MASK, PseudoVDIVU_VV_M2_E32, 0x3, false }, // 215 |
| 224 | { PseudoVDIVU_VV_M2_E64_MASK, PseudoVDIVU_VV_M2_E64, 0x3, false }, // 216 |
| 225 | { PseudoVDIVU_VV_M2_E8_MASK, PseudoVDIVU_VV_M2_E8, 0x3, false }, // 217 |
| 226 | { PseudoVDIVU_VV_M4_E16_MASK, PseudoVDIVU_VV_M4_E16, 0x3, false }, // 218 |
| 227 | { PseudoVDIVU_VV_M4_E32_MASK, PseudoVDIVU_VV_M4_E32, 0x3, false }, // 219 |
| 228 | { PseudoVDIVU_VV_M4_E64_MASK, PseudoVDIVU_VV_M4_E64, 0x3, false }, // 220 |
| 229 | { PseudoVDIVU_VV_M4_E8_MASK, PseudoVDIVU_VV_M4_E8, 0x3, false }, // 221 |
| 230 | { PseudoVDIVU_VV_M8_E16_MASK, PseudoVDIVU_VV_M8_E16, 0x3, false }, // 222 |
| 231 | { PseudoVDIVU_VV_M8_E32_MASK, PseudoVDIVU_VV_M8_E32, 0x3, false }, // 223 |
| 232 | { PseudoVDIVU_VV_M8_E64_MASK, PseudoVDIVU_VV_M8_E64, 0x3, false }, // 224 |
| 233 | { PseudoVDIVU_VV_M8_E8_MASK, PseudoVDIVU_VV_M8_E8, 0x3, false }, // 225 |
| 234 | { PseudoVDIVU_VV_MF2_E16_MASK, PseudoVDIVU_VV_MF2_E16, 0x3, false }, // 226 |
| 235 | { PseudoVDIVU_VV_MF2_E32_MASK, PseudoVDIVU_VV_MF2_E32, 0x3, false }, // 227 |
| 236 | { PseudoVDIVU_VV_MF2_E8_MASK, PseudoVDIVU_VV_MF2_E8, 0x3, false }, // 228 |
| 237 | { PseudoVDIVU_VV_MF4_E16_MASK, PseudoVDIVU_VV_MF4_E16, 0x3, false }, // 229 |
| 238 | { PseudoVDIVU_VV_MF4_E8_MASK, PseudoVDIVU_VV_MF4_E8, 0x3, false }, // 230 |
| 239 | { PseudoVDIVU_VV_MF8_E8_MASK, PseudoVDIVU_VV_MF8_E8, 0x3, false }, // 231 |
| 240 | { PseudoVDIVU_VX_M1_E16_MASK, PseudoVDIVU_VX_M1_E16, 0x3, false }, // 232 |
| 241 | { PseudoVDIVU_VX_M1_E32_MASK, PseudoVDIVU_VX_M1_E32, 0x3, false }, // 233 |
| 242 | { PseudoVDIVU_VX_M1_E64_MASK, PseudoVDIVU_VX_M1_E64, 0x3, false }, // 234 |
| 243 | { PseudoVDIVU_VX_M1_E8_MASK, PseudoVDIVU_VX_M1_E8, 0x3, false }, // 235 |
| 244 | { PseudoVDIVU_VX_M2_E16_MASK, PseudoVDIVU_VX_M2_E16, 0x3, false }, // 236 |
| 245 | { PseudoVDIVU_VX_M2_E32_MASK, PseudoVDIVU_VX_M2_E32, 0x3, false }, // 237 |
| 246 | { PseudoVDIVU_VX_M2_E64_MASK, PseudoVDIVU_VX_M2_E64, 0x3, false }, // 238 |
| 247 | { PseudoVDIVU_VX_M2_E8_MASK, PseudoVDIVU_VX_M2_E8, 0x3, false }, // 239 |
| 248 | { PseudoVDIVU_VX_M4_E16_MASK, PseudoVDIVU_VX_M4_E16, 0x3, false }, // 240 |
| 249 | { PseudoVDIVU_VX_M4_E32_MASK, PseudoVDIVU_VX_M4_E32, 0x3, false }, // 241 |
| 250 | { PseudoVDIVU_VX_M4_E64_MASK, PseudoVDIVU_VX_M4_E64, 0x3, false }, // 242 |
| 251 | { PseudoVDIVU_VX_M4_E8_MASK, PseudoVDIVU_VX_M4_E8, 0x3, false }, // 243 |
| 252 | { PseudoVDIVU_VX_M8_E16_MASK, PseudoVDIVU_VX_M8_E16, 0x3, false }, // 244 |
| 253 | { PseudoVDIVU_VX_M8_E32_MASK, PseudoVDIVU_VX_M8_E32, 0x3, false }, // 245 |
| 254 | { PseudoVDIVU_VX_M8_E64_MASK, PseudoVDIVU_VX_M8_E64, 0x3, false }, // 246 |
| 255 | { PseudoVDIVU_VX_M8_E8_MASK, PseudoVDIVU_VX_M8_E8, 0x3, false }, // 247 |
| 256 | { PseudoVDIVU_VX_MF2_E16_MASK, PseudoVDIVU_VX_MF2_E16, 0x3, false }, // 248 |
| 257 | { PseudoVDIVU_VX_MF2_E32_MASK, PseudoVDIVU_VX_MF2_E32, 0x3, false }, // 249 |
| 258 | { PseudoVDIVU_VX_MF2_E8_MASK, PseudoVDIVU_VX_MF2_E8, 0x3, false }, // 250 |
| 259 | { PseudoVDIVU_VX_MF4_E16_MASK, PseudoVDIVU_VX_MF4_E16, 0x3, false }, // 251 |
| 260 | { PseudoVDIVU_VX_MF4_E8_MASK, PseudoVDIVU_VX_MF4_E8, 0x3, false }, // 252 |
| 261 | { PseudoVDIVU_VX_MF8_E8_MASK, PseudoVDIVU_VX_MF8_E8, 0x3, false }, // 253 |
| 262 | { PseudoVDIV_VV_M1_E16_MASK, PseudoVDIV_VV_M1_E16, 0x3, false }, // 254 |
| 263 | { PseudoVDIV_VV_M1_E32_MASK, PseudoVDIV_VV_M1_E32, 0x3, false }, // 255 |
| 264 | { PseudoVDIV_VV_M1_E64_MASK, PseudoVDIV_VV_M1_E64, 0x3, false }, // 256 |
| 265 | { PseudoVDIV_VV_M1_E8_MASK, PseudoVDIV_VV_M1_E8, 0x3, false }, // 257 |
| 266 | { PseudoVDIV_VV_M2_E16_MASK, PseudoVDIV_VV_M2_E16, 0x3, false }, // 258 |
| 267 | { PseudoVDIV_VV_M2_E32_MASK, PseudoVDIV_VV_M2_E32, 0x3, false }, // 259 |
| 268 | { PseudoVDIV_VV_M2_E64_MASK, PseudoVDIV_VV_M2_E64, 0x3, false }, // 260 |
| 269 | { PseudoVDIV_VV_M2_E8_MASK, PseudoVDIV_VV_M2_E8, 0x3, false }, // 261 |
| 270 | { PseudoVDIV_VV_M4_E16_MASK, PseudoVDIV_VV_M4_E16, 0x3, false }, // 262 |
| 271 | { PseudoVDIV_VV_M4_E32_MASK, PseudoVDIV_VV_M4_E32, 0x3, false }, // 263 |
| 272 | { PseudoVDIV_VV_M4_E64_MASK, PseudoVDIV_VV_M4_E64, 0x3, false }, // 264 |
| 273 | { PseudoVDIV_VV_M4_E8_MASK, PseudoVDIV_VV_M4_E8, 0x3, false }, // 265 |
| 274 | { PseudoVDIV_VV_M8_E16_MASK, PseudoVDIV_VV_M8_E16, 0x3, false }, // 266 |
| 275 | { PseudoVDIV_VV_M8_E32_MASK, PseudoVDIV_VV_M8_E32, 0x3, false }, // 267 |
| 276 | { PseudoVDIV_VV_M8_E64_MASK, PseudoVDIV_VV_M8_E64, 0x3, false }, // 268 |
| 277 | { PseudoVDIV_VV_M8_E8_MASK, PseudoVDIV_VV_M8_E8, 0x3, false }, // 269 |
| 278 | { PseudoVDIV_VV_MF2_E16_MASK, PseudoVDIV_VV_MF2_E16, 0x3, false }, // 270 |
| 279 | { PseudoVDIV_VV_MF2_E32_MASK, PseudoVDIV_VV_MF2_E32, 0x3, false }, // 271 |
| 280 | { PseudoVDIV_VV_MF2_E8_MASK, PseudoVDIV_VV_MF2_E8, 0x3, false }, // 272 |
| 281 | { PseudoVDIV_VV_MF4_E16_MASK, PseudoVDIV_VV_MF4_E16, 0x3, false }, // 273 |
| 282 | { PseudoVDIV_VV_MF4_E8_MASK, PseudoVDIV_VV_MF4_E8, 0x3, false }, // 274 |
| 283 | { PseudoVDIV_VV_MF8_E8_MASK, PseudoVDIV_VV_MF8_E8, 0x3, false }, // 275 |
| 284 | { PseudoVDIV_VX_M1_E16_MASK, PseudoVDIV_VX_M1_E16, 0x3, false }, // 276 |
| 285 | { PseudoVDIV_VX_M1_E32_MASK, PseudoVDIV_VX_M1_E32, 0x3, false }, // 277 |
| 286 | { PseudoVDIV_VX_M1_E64_MASK, PseudoVDIV_VX_M1_E64, 0x3, false }, // 278 |
| 287 | { PseudoVDIV_VX_M1_E8_MASK, PseudoVDIV_VX_M1_E8, 0x3, false }, // 279 |
| 288 | { PseudoVDIV_VX_M2_E16_MASK, PseudoVDIV_VX_M2_E16, 0x3, false }, // 280 |
| 289 | { PseudoVDIV_VX_M2_E32_MASK, PseudoVDIV_VX_M2_E32, 0x3, false }, // 281 |
| 290 | { PseudoVDIV_VX_M2_E64_MASK, PseudoVDIV_VX_M2_E64, 0x3, false }, // 282 |
| 291 | { PseudoVDIV_VX_M2_E8_MASK, PseudoVDIV_VX_M2_E8, 0x3, false }, // 283 |
| 292 | { PseudoVDIV_VX_M4_E16_MASK, PseudoVDIV_VX_M4_E16, 0x3, false }, // 284 |
| 293 | { PseudoVDIV_VX_M4_E32_MASK, PseudoVDIV_VX_M4_E32, 0x3, false }, // 285 |
| 294 | { PseudoVDIV_VX_M4_E64_MASK, PseudoVDIV_VX_M4_E64, 0x3, false }, // 286 |
| 295 | { PseudoVDIV_VX_M4_E8_MASK, PseudoVDIV_VX_M4_E8, 0x3, false }, // 287 |
| 296 | { PseudoVDIV_VX_M8_E16_MASK, PseudoVDIV_VX_M8_E16, 0x3, false }, // 288 |
| 297 | { PseudoVDIV_VX_M8_E32_MASK, PseudoVDIV_VX_M8_E32, 0x3, false }, // 289 |
| 298 | { PseudoVDIV_VX_M8_E64_MASK, PseudoVDIV_VX_M8_E64, 0x3, false }, // 290 |
| 299 | { PseudoVDIV_VX_M8_E8_MASK, PseudoVDIV_VX_M8_E8, 0x3, false }, // 291 |
| 300 | { PseudoVDIV_VX_MF2_E16_MASK, PseudoVDIV_VX_MF2_E16, 0x3, false }, // 292 |
| 301 | { PseudoVDIV_VX_MF2_E32_MASK, PseudoVDIV_VX_MF2_E32, 0x3, false }, // 293 |
| 302 | { PseudoVDIV_VX_MF2_E8_MASK, PseudoVDIV_VX_MF2_E8, 0x3, false }, // 294 |
| 303 | { PseudoVDIV_VX_MF4_E16_MASK, PseudoVDIV_VX_MF4_E16, 0x3, false }, // 295 |
| 304 | { PseudoVDIV_VX_MF4_E8_MASK, PseudoVDIV_VX_MF4_E8, 0x3, false }, // 296 |
| 305 | { PseudoVDIV_VX_MF8_E8_MASK, PseudoVDIV_VX_MF8_E8, 0x3, false }, // 297 |
| 306 | { PseudoVFADD_VFPR16_M1_E16_MASK, PseudoVFADD_VFPR16_M1_E16, 0x3, false }, // 298 |
| 307 | { PseudoVFADD_VFPR16_M2_E16_MASK, PseudoVFADD_VFPR16_M2_E16, 0x3, false }, // 299 |
| 308 | { PseudoVFADD_VFPR16_M4_E16_MASK, PseudoVFADD_VFPR16_M4_E16, 0x3, false }, // 300 |
| 309 | { PseudoVFADD_VFPR16_M8_E16_MASK, PseudoVFADD_VFPR16_M8_E16, 0x3, false }, // 301 |
| 310 | { PseudoVFADD_VFPR16_MF2_E16_MASK, PseudoVFADD_VFPR16_MF2_E16, 0x3, false }, // 302 |
| 311 | { PseudoVFADD_VFPR16_MF4_E16_MASK, PseudoVFADD_VFPR16_MF4_E16, 0x3, false }, // 303 |
| 312 | { PseudoVFADD_VFPR32_M1_E32_MASK, PseudoVFADD_VFPR32_M1_E32, 0x3, false }, // 304 |
| 313 | { PseudoVFADD_VFPR32_M2_E32_MASK, PseudoVFADD_VFPR32_M2_E32, 0x3, false }, // 305 |
| 314 | { PseudoVFADD_VFPR32_M4_E32_MASK, PseudoVFADD_VFPR32_M4_E32, 0x3, false }, // 306 |
| 315 | { PseudoVFADD_VFPR32_M8_E32_MASK, PseudoVFADD_VFPR32_M8_E32, 0x3, false }, // 307 |
| 316 | { PseudoVFADD_VFPR32_MF2_E32_MASK, PseudoVFADD_VFPR32_MF2_E32, 0x3, false }, // 308 |
| 317 | { PseudoVFADD_VFPR64_M1_E64_MASK, PseudoVFADD_VFPR64_M1_E64, 0x3, false }, // 309 |
| 318 | { PseudoVFADD_VFPR64_M2_E64_MASK, PseudoVFADD_VFPR64_M2_E64, 0x3, false }, // 310 |
| 319 | { PseudoVFADD_VFPR64_M4_E64_MASK, PseudoVFADD_VFPR64_M4_E64, 0x3, false }, // 311 |
| 320 | { PseudoVFADD_VFPR64_M8_E64_MASK, PseudoVFADD_VFPR64_M8_E64, 0x3, false }, // 312 |
| 321 | { PseudoVFADD_VV_M1_E16_MASK, PseudoVFADD_VV_M1_E16, 0x3, false }, // 313 |
| 322 | { PseudoVFADD_VV_M1_E32_MASK, PseudoVFADD_VV_M1_E32, 0x3, false }, // 314 |
| 323 | { PseudoVFADD_VV_M1_E64_MASK, PseudoVFADD_VV_M1_E64, 0x3, false }, // 315 |
| 324 | { PseudoVFADD_VV_M2_E16_MASK, PseudoVFADD_VV_M2_E16, 0x3, false }, // 316 |
| 325 | { PseudoVFADD_VV_M2_E32_MASK, PseudoVFADD_VV_M2_E32, 0x3, false }, // 317 |
| 326 | { PseudoVFADD_VV_M2_E64_MASK, PseudoVFADD_VV_M2_E64, 0x3, false }, // 318 |
| 327 | { PseudoVFADD_VV_M4_E16_MASK, PseudoVFADD_VV_M4_E16, 0x3, false }, // 319 |
| 328 | { PseudoVFADD_VV_M4_E32_MASK, PseudoVFADD_VV_M4_E32, 0x3, false }, // 320 |
| 329 | { PseudoVFADD_VV_M4_E64_MASK, PseudoVFADD_VV_M4_E64, 0x3, false }, // 321 |
| 330 | { PseudoVFADD_VV_M8_E16_MASK, PseudoVFADD_VV_M8_E16, 0x3, false }, // 322 |
| 331 | { PseudoVFADD_VV_M8_E32_MASK, PseudoVFADD_VV_M8_E32, 0x3, false }, // 323 |
| 332 | { PseudoVFADD_VV_M8_E64_MASK, PseudoVFADD_VV_M8_E64, 0x3, false }, // 324 |
| 333 | { PseudoVFADD_VV_MF2_E16_MASK, PseudoVFADD_VV_MF2_E16, 0x3, false }, // 325 |
| 334 | { PseudoVFADD_VV_MF2_E32_MASK, PseudoVFADD_VV_MF2_E32, 0x3, false }, // 326 |
| 335 | { PseudoVFADD_VV_MF4_E16_MASK, PseudoVFADD_VV_MF4_E16, 0x3, false }, // 327 |
| 336 | { PseudoVFCLASS_V_M1_MASK, PseudoVFCLASS_V_M1, 0x2, false }, // 328 |
| 337 | { PseudoVFCLASS_V_M2_MASK, PseudoVFCLASS_V_M2, 0x2, false }, // 329 |
| 338 | { PseudoVFCLASS_V_M4_MASK, PseudoVFCLASS_V_M4, 0x2, false }, // 330 |
| 339 | { PseudoVFCLASS_V_M8_MASK, PseudoVFCLASS_V_M8, 0x2, false }, // 331 |
| 340 | { PseudoVFCLASS_V_MF2_MASK, PseudoVFCLASS_V_MF2, 0x2, false }, // 332 |
| 341 | { PseudoVFCLASS_V_MF4_MASK, PseudoVFCLASS_V_MF4, 0x2, false }, // 333 |
| 342 | { PseudoVFCVT_F_XU_V_M1_E16_MASK, PseudoVFCVT_F_XU_V_M1_E16, 0x2, false }, // 334 |
| 343 | { PseudoVFCVT_F_XU_V_M1_E32_MASK, PseudoVFCVT_F_XU_V_M1_E32, 0x2, false }, // 335 |
| 344 | { PseudoVFCVT_F_XU_V_M1_E64_MASK, PseudoVFCVT_F_XU_V_M1_E64, 0x2, false }, // 336 |
| 345 | { PseudoVFCVT_F_XU_V_M2_E16_MASK, PseudoVFCVT_F_XU_V_M2_E16, 0x2, false }, // 337 |
| 346 | { PseudoVFCVT_F_XU_V_M2_E32_MASK, PseudoVFCVT_F_XU_V_M2_E32, 0x2, false }, // 338 |
| 347 | { PseudoVFCVT_F_XU_V_M2_E64_MASK, PseudoVFCVT_F_XU_V_M2_E64, 0x2, false }, // 339 |
| 348 | { PseudoVFCVT_F_XU_V_M4_E16_MASK, PseudoVFCVT_F_XU_V_M4_E16, 0x2, false }, // 340 |
| 349 | { PseudoVFCVT_F_XU_V_M4_E32_MASK, PseudoVFCVT_F_XU_V_M4_E32, 0x2, false }, // 341 |
| 350 | { PseudoVFCVT_F_XU_V_M4_E64_MASK, PseudoVFCVT_F_XU_V_M4_E64, 0x2, false }, // 342 |
| 351 | { PseudoVFCVT_F_XU_V_M8_E16_MASK, PseudoVFCVT_F_XU_V_M8_E16, 0x2, false }, // 343 |
| 352 | { PseudoVFCVT_F_XU_V_M8_E32_MASK, PseudoVFCVT_F_XU_V_M8_E32, 0x2, false }, // 344 |
| 353 | { PseudoVFCVT_F_XU_V_M8_E64_MASK, PseudoVFCVT_F_XU_V_M8_E64, 0x2, false }, // 345 |
| 354 | { PseudoVFCVT_F_XU_V_MF2_E16_MASK, PseudoVFCVT_F_XU_V_MF2_E16, 0x2, false }, // 346 |
| 355 | { PseudoVFCVT_F_XU_V_MF2_E32_MASK, PseudoVFCVT_F_XU_V_MF2_E32, 0x2, false }, // 347 |
| 356 | { PseudoVFCVT_F_XU_V_MF4_E16_MASK, PseudoVFCVT_F_XU_V_MF4_E16, 0x2, false }, // 348 |
| 357 | { PseudoVFCVT_F_X_V_M1_E16_MASK, PseudoVFCVT_F_X_V_M1_E16, 0x2, false }, // 349 |
| 358 | { PseudoVFCVT_F_X_V_M1_E32_MASK, PseudoVFCVT_F_X_V_M1_E32, 0x2, false }, // 350 |
| 359 | { PseudoVFCVT_F_X_V_M1_E64_MASK, PseudoVFCVT_F_X_V_M1_E64, 0x2, false }, // 351 |
| 360 | { PseudoVFCVT_F_X_V_M2_E16_MASK, PseudoVFCVT_F_X_V_M2_E16, 0x2, false }, // 352 |
| 361 | { PseudoVFCVT_F_X_V_M2_E32_MASK, PseudoVFCVT_F_X_V_M2_E32, 0x2, false }, // 353 |
| 362 | { PseudoVFCVT_F_X_V_M2_E64_MASK, PseudoVFCVT_F_X_V_M2_E64, 0x2, false }, // 354 |
| 363 | { PseudoVFCVT_F_X_V_M4_E16_MASK, PseudoVFCVT_F_X_V_M4_E16, 0x2, false }, // 355 |
| 364 | { PseudoVFCVT_F_X_V_M4_E32_MASK, PseudoVFCVT_F_X_V_M4_E32, 0x2, false }, // 356 |
| 365 | { PseudoVFCVT_F_X_V_M4_E64_MASK, PseudoVFCVT_F_X_V_M4_E64, 0x2, false }, // 357 |
| 366 | { PseudoVFCVT_F_X_V_M8_E16_MASK, PseudoVFCVT_F_X_V_M8_E16, 0x2, false }, // 358 |
| 367 | { PseudoVFCVT_F_X_V_M8_E32_MASK, PseudoVFCVT_F_X_V_M8_E32, 0x2, false }, // 359 |
| 368 | { PseudoVFCVT_F_X_V_M8_E64_MASK, PseudoVFCVT_F_X_V_M8_E64, 0x2, false }, // 360 |
| 369 | { PseudoVFCVT_F_X_V_MF2_E16_MASK, PseudoVFCVT_F_X_V_MF2_E16, 0x2, false }, // 361 |
| 370 | { PseudoVFCVT_F_X_V_MF2_E32_MASK, PseudoVFCVT_F_X_V_MF2_E32, 0x2, false }, // 362 |
| 371 | { PseudoVFCVT_F_X_V_MF4_E16_MASK, PseudoVFCVT_F_X_V_MF4_E16, 0x2, false }, // 363 |
| 372 | { PseudoVFCVT_RM_F_XU_V_M1_E16_MASK, PseudoVFCVT_RM_F_XU_V_M1_E16, 0x2, false }, // 364 |
| 373 | { PseudoVFCVT_RM_F_XU_V_M1_E32_MASK, PseudoVFCVT_RM_F_XU_V_M1_E32, 0x2, false }, // 365 |
| 374 | { PseudoVFCVT_RM_F_XU_V_M1_E64_MASK, PseudoVFCVT_RM_F_XU_V_M1_E64, 0x2, false }, // 366 |
| 375 | { PseudoVFCVT_RM_F_XU_V_M2_E16_MASK, PseudoVFCVT_RM_F_XU_V_M2_E16, 0x2, false }, // 367 |
| 376 | { PseudoVFCVT_RM_F_XU_V_M2_E32_MASK, PseudoVFCVT_RM_F_XU_V_M2_E32, 0x2, false }, // 368 |
| 377 | { PseudoVFCVT_RM_F_XU_V_M2_E64_MASK, PseudoVFCVT_RM_F_XU_V_M2_E64, 0x2, false }, // 369 |
| 378 | { PseudoVFCVT_RM_F_XU_V_M4_E16_MASK, PseudoVFCVT_RM_F_XU_V_M4_E16, 0x2, false }, // 370 |
| 379 | { PseudoVFCVT_RM_F_XU_V_M4_E32_MASK, PseudoVFCVT_RM_F_XU_V_M4_E32, 0x2, false }, // 371 |
| 380 | { PseudoVFCVT_RM_F_XU_V_M4_E64_MASK, PseudoVFCVT_RM_F_XU_V_M4_E64, 0x2, false }, // 372 |
| 381 | { PseudoVFCVT_RM_F_XU_V_M8_E16_MASK, PseudoVFCVT_RM_F_XU_V_M8_E16, 0x2, false }, // 373 |
| 382 | { PseudoVFCVT_RM_F_XU_V_M8_E32_MASK, PseudoVFCVT_RM_F_XU_V_M8_E32, 0x2, false }, // 374 |
| 383 | { PseudoVFCVT_RM_F_XU_V_M8_E64_MASK, PseudoVFCVT_RM_F_XU_V_M8_E64, 0x2, false }, // 375 |
| 384 | { PseudoVFCVT_RM_F_XU_V_MF2_E16_MASK, PseudoVFCVT_RM_F_XU_V_MF2_E16, 0x2, false }, // 376 |
| 385 | { PseudoVFCVT_RM_F_XU_V_MF2_E32_MASK, PseudoVFCVT_RM_F_XU_V_MF2_E32, 0x2, false }, // 377 |
| 386 | { PseudoVFCVT_RM_F_XU_V_MF4_E16_MASK, PseudoVFCVT_RM_F_XU_V_MF4_E16, 0x2, false }, // 378 |
| 387 | { PseudoVFCVT_RM_F_X_V_M1_E16_MASK, PseudoVFCVT_RM_F_X_V_M1_E16, 0x2, false }, // 379 |
| 388 | { PseudoVFCVT_RM_F_X_V_M1_E32_MASK, PseudoVFCVT_RM_F_X_V_M1_E32, 0x2, false }, // 380 |
| 389 | { PseudoVFCVT_RM_F_X_V_M1_E64_MASK, PseudoVFCVT_RM_F_X_V_M1_E64, 0x2, false }, // 381 |
| 390 | { PseudoVFCVT_RM_F_X_V_M2_E16_MASK, PseudoVFCVT_RM_F_X_V_M2_E16, 0x2, false }, // 382 |
| 391 | { PseudoVFCVT_RM_F_X_V_M2_E32_MASK, PseudoVFCVT_RM_F_X_V_M2_E32, 0x2, false }, // 383 |
| 392 | { PseudoVFCVT_RM_F_X_V_M2_E64_MASK, PseudoVFCVT_RM_F_X_V_M2_E64, 0x2, false }, // 384 |
| 393 | { PseudoVFCVT_RM_F_X_V_M4_E16_MASK, PseudoVFCVT_RM_F_X_V_M4_E16, 0x2, false }, // 385 |
| 394 | { PseudoVFCVT_RM_F_X_V_M4_E32_MASK, PseudoVFCVT_RM_F_X_V_M4_E32, 0x2, false }, // 386 |
| 395 | { PseudoVFCVT_RM_F_X_V_M4_E64_MASK, PseudoVFCVT_RM_F_X_V_M4_E64, 0x2, false }, // 387 |
| 396 | { PseudoVFCVT_RM_F_X_V_M8_E16_MASK, PseudoVFCVT_RM_F_X_V_M8_E16, 0x2, false }, // 388 |
| 397 | { PseudoVFCVT_RM_F_X_V_M8_E32_MASK, PseudoVFCVT_RM_F_X_V_M8_E32, 0x2, false }, // 389 |
| 398 | { PseudoVFCVT_RM_F_X_V_M8_E64_MASK, PseudoVFCVT_RM_F_X_V_M8_E64, 0x2, false }, // 390 |
| 399 | { PseudoVFCVT_RM_F_X_V_MF2_E16_MASK, PseudoVFCVT_RM_F_X_V_MF2_E16, 0x2, false }, // 391 |
| 400 | { PseudoVFCVT_RM_F_X_V_MF2_E32_MASK, PseudoVFCVT_RM_F_X_V_MF2_E32, 0x2, false }, // 392 |
| 401 | { PseudoVFCVT_RM_F_X_V_MF4_E16_MASK, PseudoVFCVT_RM_F_X_V_MF4_E16, 0x2, false }, // 393 |
| 402 | { PseudoVFCVT_RM_XU_F_V_M1_MASK, PseudoVFCVT_RM_XU_F_V_M1, 0x2, false }, // 394 |
| 403 | { PseudoVFCVT_RM_XU_F_V_M2_MASK, PseudoVFCVT_RM_XU_F_V_M2, 0x2, false }, // 395 |
| 404 | { PseudoVFCVT_RM_XU_F_V_M4_MASK, PseudoVFCVT_RM_XU_F_V_M4, 0x2, false }, // 396 |
| 405 | { PseudoVFCVT_RM_XU_F_V_M8_MASK, PseudoVFCVT_RM_XU_F_V_M8, 0x2, false }, // 397 |
| 406 | { PseudoVFCVT_RM_XU_F_V_MF2_MASK, PseudoVFCVT_RM_XU_F_V_MF2, 0x2, false }, // 398 |
| 407 | { PseudoVFCVT_RM_XU_F_V_MF4_MASK, PseudoVFCVT_RM_XU_F_V_MF4, 0x2, false }, // 399 |
| 408 | { PseudoVFCVT_RM_X_F_V_M1_MASK, PseudoVFCVT_RM_X_F_V_M1, 0x2, false }, // 400 |
| 409 | { PseudoVFCVT_RM_X_F_V_M2_MASK, PseudoVFCVT_RM_X_F_V_M2, 0x2, false }, // 401 |
| 410 | { PseudoVFCVT_RM_X_F_V_M4_MASK, PseudoVFCVT_RM_X_F_V_M4, 0x2, false }, // 402 |
| 411 | { PseudoVFCVT_RM_X_F_V_M8_MASK, PseudoVFCVT_RM_X_F_V_M8, 0x2, false }, // 403 |
| 412 | { PseudoVFCVT_RM_X_F_V_MF2_MASK, PseudoVFCVT_RM_X_F_V_MF2, 0x2, false }, // 404 |
| 413 | { PseudoVFCVT_RM_X_F_V_MF4_MASK, PseudoVFCVT_RM_X_F_V_MF4, 0x2, false }, // 405 |
| 414 | { PseudoVFCVT_RTZ_XU_F_V_M1_MASK, PseudoVFCVT_RTZ_XU_F_V_M1, 0x2, false }, // 406 |
| 415 | { PseudoVFCVT_RTZ_XU_F_V_M2_MASK, PseudoVFCVT_RTZ_XU_F_V_M2, 0x2, false }, // 407 |
| 416 | { PseudoVFCVT_RTZ_XU_F_V_M4_MASK, PseudoVFCVT_RTZ_XU_F_V_M4, 0x2, false }, // 408 |
| 417 | { PseudoVFCVT_RTZ_XU_F_V_M8_MASK, PseudoVFCVT_RTZ_XU_F_V_M8, 0x2, false }, // 409 |
| 418 | { PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, PseudoVFCVT_RTZ_XU_F_V_MF2, 0x2, false }, // 410 |
| 419 | { PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, PseudoVFCVT_RTZ_XU_F_V_MF4, 0x2, false }, // 411 |
| 420 | { PseudoVFCVT_RTZ_X_F_V_M1_MASK, PseudoVFCVT_RTZ_X_F_V_M1, 0x2, false }, // 412 |
| 421 | { PseudoVFCVT_RTZ_X_F_V_M2_MASK, PseudoVFCVT_RTZ_X_F_V_M2, 0x2, false }, // 413 |
| 422 | { PseudoVFCVT_RTZ_X_F_V_M4_MASK, PseudoVFCVT_RTZ_X_F_V_M4, 0x2, false }, // 414 |
| 423 | { PseudoVFCVT_RTZ_X_F_V_M8_MASK, PseudoVFCVT_RTZ_X_F_V_M8, 0x2, false }, // 415 |
| 424 | { PseudoVFCVT_RTZ_X_F_V_MF2_MASK, PseudoVFCVT_RTZ_X_F_V_MF2, 0x2, false }, // 416 |
| 425 | { PseudoVFCVT_RTZ_X_F_V_MF4_MASK, PseudoVFCVT_RTZ_X_F_V_MF4, 0x2, false }, // 417 |
| 426 | { PseudoVFCVT_XU_F_V_M1_MASK, PseudoVFCVT_XU_F_V_M1, 0x2, false }, // 418 |
| 427 | { PseudoVFCVT_XU_F_V_M2_MASK, PseudoVFCVT_XU_F_V_M2, 0x2, false }, // 419 |
| 428 | { PseudoVFCVT_XU_F_V_M4_MASK, PseudoVFCVT_XU_F_V_M4, 0x2, false }, // 420 |
| 429 | { PseudoVFCVT_XU_F_V_M8_MASK, PseudoVFCVT_XU_F_V_M8, 0x2, false }, // 421 |
| 430 | { PseudoVFCVT_XU_F_V_MF2_MASK, PseudoVFCVT_XU_F_V_MF2, 0x2, false }, // 422 |
| 431 | { PseudoVFCVT_XU_F_V_MF4_MASK, PseudoVFCVT_XU_F_V_MF4, 0x2, false }, // 423 |
| 432 | { PseudoVFCVT_X_F_V_M1_MASK, PseudoVFCVT_X_F_V_M1, 0x2, false }, // 424 |
| 433 | { PseudoVFCVT_X_F_V_M2_MASK, PseudoVFCVT_X_F_V_M2, 0x2, false }, // 425 |
| 434 | { PseudoVFCVT_X_F_V_M4_MASK, PseudoVFCVT_X_F_V_M4, 0x2, false }, // 426 |
| 435 | { PseudoVFCVT_X_F_V_M8_MASK, PseudoVFCVT_X_F_V_M8, 0x2, false }, // 427 |
| 436 | { PseudoVFCVT_X_F_V_MF2_MASK, PseudoVFCVT_X_F_V_MF2, 0x2, false }, // 428 |
| 437 | { PseudoVFCVT_X_F_V_MF4_MASK, PseudoVFCVT_X_F_V_MF4, 0x2, false }, // 429 |
| 438 | { PseudoVFDIV_VFPR16_M1_E16_MASK, PseudoVFDIV_VFPR16_M1_E16, 0x3, false }, // 430 |
| 439 | { PseudoVFDIV_VFPR16_M2_E16_MASK, PseudoVFDIV_VFPR16_M2_E16, 0x3, false }, // 431 |
| 440 | { PseudoVFDIV_VFPR16_M4_E16_MASK, PseudoVFDIV_VFPR16_M4_E16, 0x3, false }, // 432 |
| 441 | { PseudoVFDIV_VFPR16_M8_E16_MASK, PseudoVFDIV_VFPR16_M8_E16, 0x3, false }, // 433 |
| 442 | { PseudoVFDIV_VFPR16_MF2_E16_MASK, PseudoVFDIV_VFPR16_MF2_E16, 0x3, false }, // 434 |
| 443 | { PseudoVFDIV_VFPR16_MF4_E16_MASK, PseudoVFDIV_VFPR16_MF4_E16, 0x3, false }, // 435 |
| 444 | { PseudoVFDIV_VFPR32_M1_E32_MASK, PseudoVFDIV_VFPR32_M1_E32, 0x3, false }, // 436 |
| 445 | { PseudoVFDIV_VFPR32_M2_E32_MASK, PseudoVFDIV_VFPR32_M2_E32, 0x3, false }, // 437 |
| 446 | { PseudoVFDIV_VFPR32_M4_E32_MASK, PseudoVFDIV_VFPR32_M4_E32, 0x3, false }, // 438 |
| 447 | { PseudoVFDIV_VFPR32_M8_E32_MASK, PseudoVFDIV_VFPR32_M8_E32, 0x3, false }, // 439 |
| 448 | { PseudoVFDIV_VFPR32_MF2_E32_MASK, PseudoVFDIV_VFPR32_MF2_E32, 0x3, false }, // 440 |
| 449 | { PseudoVFDIV_VFPR64_M1_E64_MASK, PseudoVFDIV_VFPR64_M1_E64, 0x3, false }, // 441 |
| 450 | { PseudoVFDIV_VFPR64_M2_E64_MASK, PseudoVFDIV_VFPR64_M2_E64, 0x3, false }, // 442 |
| 451 | { PseudoVFDIV_VFPR64_M4_E64_MASK, PseudoVFDIV_VFPR64_M4_E64, 0x3, false }, // 443 |
| 452 | { PseudoVFDIV_VFPR64_M8_E64_MASK, PseudoVFDIV_VFPR64_M8_E64, 0x3, false }, // 444 |
| 453 | { PseudoVFDIV_VV_M1_E16_MASK, PseudoVFDIV_VV_M1_E16, 0x3, false }, // 445 |
| 454 | { PseudoVFDIV_VV_M1_E32_MASK, PseudoVFDIV_VV_M1_E32, 0x3, false }, // 446 |
| 455 | { PseudoVFDIV_VV_M1_E64_MASK, PseudoVFDIV_VV_M1_E64, 0x3, false }, // 447 |
| 456 | { PseudoVFDIV_VV_M2_E16_MASK, PseudoVFDIV_VV_M2_E16, 0x3, false }, // 448 |
| 457 | { PseudoVFDIV_VV_M2_E32_MASK, PseudoVFDIV_VV_M2_E32, 0x3, false }, // 449 |
| 458 | { PseudoVFDIV_VV_M2_E64_MASK, PseudoVFDIV_VV_M2_E64, 0x3, false }, // 450 |
| 459 | { PseudoVFDIV_VV_M4_E16_MASK, PseudoVFDIV_VV_M4_E16, 0x3, false }, // 451 |
| 460 | { PseudoVFDIV_VV_M4_E32_MASK, PseudoVFDIV_VV_M4_E32, 0x3, false }, // 452 |
| 461 | { PseudoVFDIV_VV_M4_E64_MASK, PseudoVFDIV_VV_M4_E64, 0x3, false }, // 453 |
| 462 | { PseudoVFDIV_VV_M8_E16_MASK, PseudoVFDIV_VV_M8_E16, 0x3, false }, // 454 |
| 463 | { PseudoVFDIV_VV_M8_E32_MASK, PseudoVFDIV_VV_M8_E32, 0x3, false }, // 455 |
| 464 | { PseudoVFDIV_VV_M8_E64_MASK, PseudoVFDIV_VV_M8_E64, 0x3, false }, // 456 |
| 465 | { PseudoVFDIV_VV_MF2_E16_MASK, PseudoVFDIV_VV_MF2_E16, 0x3, false }, // 457 |
| 466 | { PseudoVFDIV_VV_MF2_E32_MASK, PseudoVFDIV_VV_MF2_E32, 0x3, false }, // 458 |
| 467 | { PseudoVFDIV_VV_MF4_E16_MASK, PseudoVFDIV_VV_MF4_E16, 0x3, false }, // 459 |
| 468 | { PseudoVFMACC_VFPR16_M1_E16_MASK, PseudoVFMACC_VFPR16_M1_E16, 0x3, false }, // 460 |
| 469 | { PseudoVFMACC_VFPR16_M2_E16_MASK, PseudoVFMACC_VFPR16_M2_E16, 0x3, false }, // 461 |
| 470 | { PseudoVFMACC_VFPR16_M4_E16_MASK, PseudoVFMACC_VFPR16_M4_E16, 0x3, false }, // 462 |
| 471 | { PseudoVFMACC_VFPR16_M8_E16_MASK, PseudoVFMACC_VFPR16_M8_E16, 0x3, false }, // 463 |
| 472 | { PseudoVFMACC_VFPR16_MF2_E16_MASK, PseudoVFMACC_VFPR16_MF2_E16, 0x3, false }, // 464 |
| 473 | { PseudoVFMACC_VFPR16_MF4_E16_MASK, PseudoVFMACC_VFPR16_MF4_E16, 0x3, false }, // 465 |
| 474 | { PseudoVFMACC_VFPR32_M1_E32_MASK, PseudoVFMACC_VFPR32_M1_E32, 0x3, false }, // 466 |
| 475 | { PseudoVFMACC_VFPR32_M2_E32_MASK, PseudoVFMACC_VFPR32_M2_E32, 0x3, false }, // 467 |
| 476 | { PseudoVFMACC_VFPR32_M4_E32_MASK, PseudoVFMACC_VFPR32_M4_E32, 0x3, false }, // 468 |
| 477 | { PseudoVFMACC_VFPR32_M8_E32_MASK, PseudoVFMACC_VFPR32_M8_E32, 0x3, false }, // 469 |
| 478 | { PseudoVFMACC_VFPR32_MF2_E32_MASK, PseudoVFMACC_VFPR32_MF2_E32, 0x3, false }, // 470 |
| 479 | { PseudoVFMACC_VFPR64_M1_E64_MASK, PseudoVFMACC_VFPR64_M1_E64, 0x3, false }, // 471 |
| 480 | { PseudoVFMACC_VFPR64_M2_E64_MASK, PseudoVFMACC_VFPR64_M2_E64, 0x3, false }, // 472 |
| 481 | { PseudoVFMACC_VFPR64_M4_E64_MASK, PseudoVFMACC_VFPR64_M4_E64, 0x3, false }, // 473 |
| 482 | { PseudoVFMACC_VFPR64_M8_E64_MASK, PseudoVFMACC_VFPR64_M8_E64, 0x3, false }, // 474 |
| 483 | { PseudoVFMACC_VV_M1_E16_MASK, PseudoVFMACC_VV_M1_E16, 0x3, false }, // 475 |
| 484 | { PseudoVFMACC_VV_M1_E32_MASK, PseudoVFMACC_VV_M1_E32, 0x3, false }, // 476 |
| 485 | { PseudoVFMACC_VV_M1_E64_MASK, PseudoVFMACC_VV_M1_E64, 0x3, false }, // 477 |
| 486 | { PseudoVFMACC_VV_M2_E16_MASK, PseudoVFMACC_VV_M2_E16, 0x3, false }, // 478 |
| 487 | { PseudoVFMACC_VV_M2_E32_MASK, PseudoVFMACC_VV_M2_E32, 0x3, false }, // 479 |
| 488 | { PseudoVFMACC_VV_M2_E64_MASK, PseudoVFMACC_VV_M2_E64, 0x3, false }, // 480 |
| 489 | { PseudoVFMACC_VV_M4_E16_MASK, PseudoVFMACC_VV_M4_E16, 0x3, false }, // 481 |
| 490 | { PseudoVFMACC_VV_M4_E32_MASK, PseudoVFMACC_VV_M4_E32, 0x3, false }, // 482 |
| 491 | { PseudoVFMACC_VV_M4_E64_MASK, PseudoVFMACC_VV_M4_E64, 0x3, false }, // 483 |
| 492 | { PseudoVFMACC_VV_M8_E16_MASK, PseudoVFMACC_VV_M8_E16, 0x3, false }, // 484 |
| 493 | { PseudoVFMACC_VV_M8_E32_MASK, PseudoVFMACC_VV_M8_E32, 0x3, false }, // 485 |
| 494 | { PseudoVFMACC_VV_M8_E64_MASK, PseudoVFMACC_VV_M8_E64, 0x3, false }, // 486 |
| 495 | { PseudoVFMACC_VV_MF2_E16_MASK, PseudoVFMACC_VV_MF2_E16, 0x3, false }, // 487 |
| 496 | { PseudoVFMACC_VV_MF2_E32_MASK, PseudoVFMACC_VV_MF2_E32, 0x3, false }, // 488 |
| 497 | { PseudoVFMACC_VV_MF4_E16_MASK, PseudoVFMACC_VV_MF4_E16, 0x3, false }, // 489 |
| 498 | { PseudoVFMADD_VFPR16_M1_E16_MASK, PseudoVFMADD_VFPR16_M1_E16, 0x3, false }, // 490 |
| 499 | { PseudoVFMADD_VFPR16_M2_E16_MASK, PseudoVFMADD_VFPR16_M2_E16, 0x3, false }, // 491 |
| 500 | { PseudoVFMADD_VFPR16_M4_E16_MASK, PseudoVFMADD_VFPR16_M4_E16, 0x3, false }, // 492 |
| 501 | { PseudoVFMADD_VFPR16_M8_E16_MASK, PseudoVFMADD_VFPR16_M8_E16, 0x3, false }, // 493 |
| 502 | { PseudoVFMADD_VFPR16_MF2_E16_MASK, PseudoVFMADD_VFPR16_MF2_E16, 0x3, false }, // 494 |
| 503 | { PseudoVFMADD_VFPR16_MF4_E16_MASK, PseudoVFMADD_VFPR16_MF4_E16, 0x3, false }, // 495 |
| 504 | { PseudoVFMADD_VFPR32_M1_E32_MASK, PseudoVFMADD_VFPR32_M1_E32, 0x3, false }, // 496 |
| 505 | { PseudoVFMADD_VFPR32_M2_E32_MASK, PseudoVFMADD_VFPR32_M2_E32, 0x3, false }, // 497 |
| 506 | { PseudoVFMADD_VFPR32_M4_E32_MASK, PseudoVFMADD_VFPR32_M4_E32, 0x3, false }, // 498 |
| 507 | { PseudoVFMADD_VFPR32_M8_E32_MASK, PseudoVFMADD_VFPR32_M8_E32, 0x3, false }, // 499 |
| 508 | { PseudoVFMADD_VFPR32_MF2_E32_MASK, PseudoVFMADD_VFPR32_MF2_E32, 0x3, false }, // 500 |
| 509 | { PseudoVFMADD_VFPR64_M1_E64_MASK, PseudoVFMADD_VFPR64_M1_E64, 0x3, false }, // 501 |
| 510 | { PseudoVFMADD_VFPR64_M2_E64_MASK, PseudoVFMADD_VFPR64_M2_E64, 0x3, false }, // 502 |
| 511 | { PseudoVFMADD_VFPR64_M4_E64_MASK, PseudoVFMADD_VFPR64_M4_E64, 0x3, false }, // 503 |
| 512 | { PseudoVFMADD_VFPR64_M8_E64_MASK, PseudoVFMADD_VFPR64_M8_E64, 0x3, false }, // 504 |
| 513 | { PseudoVFMADD_VV_M1_E16_MASK, PseudoVFMADD_VV_M1_E16, 0x3, false }, // 505 |
| 514 | { PseudoVFMADD_VV_M1_E32_MASK, PseudoVFMADD_VV_M1_E32, 0x3, false }, // 506 |
| 515 | { PseudoVFMADD_VV_M1_E64_MASK, PseudoVFMADD_VV_M1_E64, 0x3, false }, // 507 |
| 516 | { PseudoVFMADD_VV_M2_E16_MASK, PseudoVFMADD_VV_M2_E16, 0x3, false }, // 508 |
| 517 | { PseudoVFMADD_VV_M2_E32_MASK, PseudoVFMADD_VV_M2_E32, 0x3, false }, // 509 |
| 518 | { PseudoVFMADD_VV_M2_E64_MASK, PseudoVFMADD_VV_M2_E64, 0x3, false }, // 510 |
| 519 | { PseudoVFMADD_VV_M4_E16_MASK, PseudoVFMADD_VV_M4_E16, 0x3, false }, // 511 |
| 520 | { PseudoVFMADD_VV_M4_E32_MASK, PseudoVFMADD_VV_M4_E32, 0x3, false }, // 512 |
| 521 | { PseudoVFMADD_VV_M4_E64_MASK, PseudoVFMADD_VV_M4_E64, 0x3, false }, // 513 |
| 522 | { PseudoVFMADD_VV_M8_E16_MASK, PseudoVFMADD_VV_M8_E16, 0x3, false }, // 514 |
| 523 | { PseudoVFMADD_VV_M8_E32_MASK, PseudoVFMADD_VV_M8_E32, 0x3, false }, // 515 |
| 524 | { PseudoVFMADD_VV_M8_E64_MASK, PseudoVFMADD_VV_M8_E64, 0x3, false }, // 516 |
| 525 | { PseudoVFMADD_VV_MF2_E16_MASK, PseudoVFMADD_VV_MF2_E16, 0x3, false }, // 517 |
| 526 | { PseudoVFMADD_VV_MF2_E32_MASK, PseudoVFMADD_VV_MF2_E32, 0x3, false }, // 518 |
| 527 | { PseudoVFMADD_VV_MF4_E16_MASK, PseudoVFMADD_VV_MF4_E16, 0x3, false }, // 519 |
| 528 | { PseudoVFMAX_VFPR16_M1_E16_MASK, PseudoVFMAX_VFPR16_M1_E16, 0x3, false }, // 520 |
| 529 | { PseudoVFMAX_VFPR16_M2_E16_MASK, PseudoVFMAX_VFPR16_M2_E16, 0x3, false }, // 521 |
| 530 | { PseudoVFMAX_VFPR16_M4_E16_MASK, PseudoVFMAX_VFPR16_M4_E16, 0x3, false }, // 522 |
| 531 | { PseudoVFMAX_VFPR16_M8_E16_MASK, PseudoVFMAX_VFPR16_M8_E16, 0x3, false }, // 523 |
| 532 | { PseudoVFMAX_VFPR16_MF2_E16_MASK, PseudoVFMAX_VFPR16_MF2_E16, 0x3, false }, // 524 |
| 533 | { PseudoVFMAX_VFPR16_MF4_E16_MASK, PseudoVFMAX_VFPR16_MF4_E16, 0x3, false }, // 525 |
| 534 | { PseudoVFMAX_VFPR32_M1_E32_MASK, PseudoVFMAX_VFPR32_M1_E32, 0x3, false }, // 526 |
| 535 | { PseudoVFMAX_VFPR32_M2_E32_MASK, PseudoVFMAX_VFPR32_M2_E32, 0x3, false }, // 527 |
| 536 | { PseudoVFMAX_VFPR32_M4_E32_MASK, PseudoVFMAX_VFPR32_M4_E32, 0x3, false }, // 528 |
| 537 | { PseudoVFMAX_VFPR32_M8_E32_MASK, PseudoVFMAX_VFPR32_M8_E32, 0x3, false }, // 529 |
| 538 | { PseudoVFMAX_VFPR32_MF2_E32_MASK, PseudoVFMAX_VFPR32_MF2_E32, 0x3, false }, // 530 |
| 539 | { PseudoVFMAX_VFPR64_M1_E64_MASK, PseudoVFMAX_VFPR64_M1_E64, 0x3, false }, // 531 |
| 540 | { PseudoVFMAX_VFPR64_M2_E64_MASK, PseudoVFMAX_VFPR64_M2_E64, 0x3, false }, // 532 |
| 541 | { PseudoVFMAX_VFPR64_M4_E64_MASK, PseudoVFMAX_VFPR64_M4_E64, 0x3, false }, // 533 |
| 542 | { PseudoVFMAX_VFPR64_M8_E64_MASK, PseudoVFMAX_VFPR64_M8_E64, 0x3, false }, // 534 |
| 543 | { PseudoVFMAX_VV_M1_E16_MASK, PseudoVFMAX_VV_M1_E16, 0x3, false }, // 535 |
| 544 | { PseudoVFMAX_VV_M1_E32_MASK, PseudoVFMAX_VV_M1_E32, 0x3, false }, // 536 |
| 545 | { PseudoVFMAX_VV_M1_E64_MASK, PseudoVFMAX_VV_M1_E64, 0x3, false }, // 537 |
| 546 | { PseudoVFMAX_VV_M2_E16_MASK, PseudoVFMAX_VV_M2_E16, 0x3, false }, // 538 |
| 547 | { PseudoVFMAX_VV_M2_E32_MASK, PseudoVFMAX_VV_M2_E32, 0x3, false }, // 539 |
| 548 | { PseudoVFMAX_VV_M2_E64_MASK, PseudoVFMAX_VV_M2_E64, 0x3, false }, // 540 |
| 549 | { PseudoVFMAX_VV_M4_E16_MASK, PseudoVFMAX_VV_M4_E16, 0x3, false }, // 541 |
| 550 | { PseudoVFMAX_VV_M4_E32_MASK, PseudoVFMAX_VV_M4_E32, 0x3, false }, // 542 |
| 551 | { PseudoVFMAX_VV_M4_E64_MASK, PseudoVFMAX_VV_M4_E64, 0x3, false }, // 543 |
| 552 | { PseudoVFMAX_VV_M8_E16_MASK, PseudoVFMAX_VV_M8_E16, 0x3, false }, // 544 |
| 553 | { PseudoVFMAX_VV_M8_E32_MASK, PseudoVFMAX_VV_M8_E32, 0x3, false }, // 545 |
| 554 | { PseudoVFMAX_VV_M8_E64_MASK, PseudoVFMAX_VV_M8_E64, 0x3, false }, // 546 |
| 555 | { PseudoVFMAX_VV_MF2_E16_MASK, PseudoVFMAX_VV_MF2_E16, 0x3, false }, // 547 |
| 556 | { PseudoVFMAX_VV_MF2_E32_MASK, PseudoVFMAX_VV_MF2_E32, 0x3, false }, // 548 |
| 557 | { PseudoVFMAX_VV_MF4_E16_MASK, PseudoVFMAX_VV_MF4_E16, 0x3, false }, // 549 |
| 558 | { PseudoVFMIN_VFPR16_M1_E16_MASK, PseudoVFMIN_VFPR16_M1_E16, 0x3, false }, // 550 |
| 559 | { PseudoVFMIN_VFPR16_M2_E16_MASK, PseudoVFMIN_VFPR16_M2_E16, 0x3, false }, // 551 |
| 560 | { PseudoVFMIN_VFPR16_M4_E16_MASK, PseudoVFMIN_VFPR16_M4_E16, 0x3, false }, // 552 |
| 561 | { PseudoVFMIN_VFPR16_M8_E16_MASK, PseudoVFMIN_VFPR16_M8_E16, 0x3, false }, // 553 |
| 562 | { PseudoVFMIN_VFPR16_MF2_E16_MASK, PseudoVFMIN_VFPR16_MF2_E16, 0x3, false }, // 554 |
| 563 | { PseudoVFMIN_VFPR16_MF4_E16_MASK, PseudoVFMIN_VFPR16_MF4_E16, 0x3, false }, // 555 |
| 564 | { PseudoVFMIN_VFPR32_M1_E32_MASK, PseudoVFMIN_VFPR32_M1_E32, 0x3, false }, // 556 |
| 565 | { PseudoVFMIN_VFPR32_M2_E32_MASK, PseudoVFMIN_VFPR32_M2_E32, 0x3, false }, // 557 |
| 566 | { PseudoVFMIN_VFPR32_M4_E32_MASK, PseudoVFMIN_VFPR32_M4_E32, 0x3, false }, // 558 |
| 567 | { PseudoVFMIN_VFPR32_M8_E32_MASK, PseudoVFMIN_VFPR32_M8_E32, 0x3, false }, // 559 |
| 568 | { PseudoVFMIN_VFPR32_MF2_E32_MASK, PseudoVFMIN_VFPR32_MF2_E32, 0x3, false }, // 560 |
| 569 | { PseudoVFMIN_VFPR64_M1_E64_MASK, PseudoVFMIN_VFPR64_M1_E64, 0x3, false }, // 561 |
| 570 | { PseudoVFMIN_VFPR64_M2_E64_MASK, PseudoVFMIN_VFPR64_M2_E64, 0x3, false }, // 562 |
| 571 | { PseudoVFMIN_VFPR64_M4_E64_MASK, PseudoVFMIN_VFPR64_M4_E64, 0x3, false }, // 563 |
| 572 | { PseudoVFMIN_VFPR64_M8_E64_MASK, PseudoVFMIN_VFPR64_M8_E64, 0x3, false }, // 564 |
| 573 | { PseudoVFMIN_VV_M1_E16_MASK, PseudoVFMIN_VV_M1_E16, 0x3, false }, // 565 |
| 574 | { PseudoVFMIN_VV_M1_E32_MASK, PseudoVFMIN_VV_M1_E32, 0x3, false }, // 566 |
| 575 | { PseudoVFMIN_VV_M1_E64_MASK, PseudoVFMIN_VV_M1_E64, 0x3, false }, // 567 |
| 576 | { PseudoVFMIN_VV_M2_E16_MASK, PseudoVFMIN_VV_M2_E16, 0x3, false }, // 568 |
| 577 | { PseudoVFMIN_VV_M2_E32_MASK, PseudoVFMIN_VV_M2_E32, 0x3, false }, // 569 |
| 578 | { PseudoVFMIN_VV_M2_E64_MASK, PseudoVFMIN_VV_M2_E64, 0x3, false }, // 570 |
| 579 | { PseudoVFMIN_VV_M4_E16_MASK, PseudoVFMIN_VV_M4_E16, 0x3, false }, // 571 |
| 580 | { PseudoVFMIN_VV_M4_E32_MASK, PseudoVFMIN_VV_M4_E32, 0x3, false }, // 572 |
| 581 | { PseudoVFMIN_VV_M4_E64_MASK, PseudoVFMIN_VV_M4_E64, 0x3, false }, // 573 |
| 582 | { PseudoVFMIN_VV_M8_E16_MASK, PseudoVFMIN_VV_M8_E16, 0x3, false }, // 574 |
| 583 | { PseudoVFMIN_VV_M8_E32_MASK, PseudoVFMIN_VV_M8_E32, 0x3, false }, // 575 |
| 584 | { PseudoVFMIN_VV_M8_E64_MASK, PseudoVFMIN_VV_M8_E64, 0x3, false }, // 576 |
| 585 | { PseudoVFMIN_VV_MF2_E16_MASK, PseudoVFMIN_VV_MF2_E16, 0x3, false }, // 577 |
| 586 | { PseudoVFMIN_VV_MF2_E32_MASK, PseudoVFMIN_VV_MF2_E32, 0x3, false }, // 578 |
| 587 | { PseudoVFMIN_VV_MF4_E16_MASK, PseudoVFMIN_VV_MF4_E16, 0x3, false }, // 579 |
| 588 | { PseudoVFMSAC_VFPR16_M1_E16_MASK, PseudoVFMSAC_VFPR16_M1_E16, 0x3, false }, // 580 |
| 589 | { PseudoVFMSAC_VFPR16_M2_E16_MASK, PseudoVFMSAC_VFPR16_M2_E16, 0x3, false }, // 581 |
| 590 | { PseudoVFMSAC_VFPR16_M4_E16_MASK, PseudoVFMSAC_VFPR16_M4_E16, 0x3, false }, // 582 |
| 591 | { PseudoVFMSAC_VFPR16_M8_E16_MASK, PseudoVFMSAC_VFPR16_M8_E16, 0x3, false }, // 583 |
| 592 | { PseudoVFMSAC_VFPR16_MF2_E16_MASK, PseudoVFMSAC_VFPR16_MF2_E16, 0x3, false }, // 584 |
| 593 | { PseudoVFMSAC_VFPR16_MF4_E16_MASK, PseudoVFMSAC_VFPR16_MF4_E16, 0x3, false }, // 585 |
| 594 | { PseudoVFMSAC_VFPR32_M1_E32_MASK, PseudoVFMSAC_VFPR32_M1_E32, 0x3, false }, // 586 |
| 595 | { PseudoVFMSAC_VFPR32_M2_E32_MASK, PseudoVFMSAC_VFPR32_M2_E32, 0x3, false }, // 587 |
| 596 | { PseudoVFMSAC_VFPR32_M4_E32_MASK, PseudoVFMSAC_VFPR32_M4_E32, 0x3, false }, // 588 |
| 597 | { PseudoVFMSAC_VFPR32_M8_E32_MASK, PseudoVFMSAC_VFPR32_M8_E32, 0x3, false }, // 589 |
| 598 | { PseudoVFMSAC_VFPR32_MF2_E32_MASK, PseudoVFMSAC_VFPR32_MF2_E32, 0x3, false }, // 590 |
| 599 | { PseudoVFMSAC_VFPR64_M1_E64_MASK, PseudoVFMSAC_VFPR64_M1_E64, 0x3, false }, // 591 |
| 600 | { PseudoVFMSAC_VFPR64_M2_E64_MASK, PseudoVFMSAC_VFPR64_M2_E64, 0x3, false }, // 592 |
| 601 | { PseudoVFMSAC_VFPR64_M4_E64_MASK, PseudoVFMSAC_VFPR64_M4_E64, 0x3, false }, // 593 |
| 602 | { PseudoVFMSAC_VFPR64_M8_E64_MASK, PseudoVFMSAC_VFPR64_M8_E64, 0x3, false }, // 594 |
| 603 | { PseudoVFMSAC_VV_M1_E16_MASK, PseudoVFMSAC_VV_M1_E16, 0x3, false }, // 595 |
| 604 | { PseudoVFMSAC_VV_M1_E32_MASK, PseudoVFMSAC_VV_M1_E32, 0x3, false }, // 596 |
| 605 | { PseudoVFMSAC_VV_M1_E64_MASK, PseudoVFMSAC_VV_M1_E64, 0x3, false }, // 597 |
| 606 | { PseudoVFMSAC_VV_M2_E16_MASK, PseudoVFMSAC_VV_M2_E16, 0x3, false }, // 598 |
| 607 | { PseudoVFMSAC_VV_M2_E32_MASK, PseudoVFMSAC_VV_M2_E32, 0x3, false }, // 599 |
| 608 | { PseudoVFMSAC_VV_M2_E64_MASK, PseudoVFMSAC_VV_M2_E64, 0x3, false }, // 600 |
| 609 | { PseudoVFMSAC_VV_M4_E16_MASK, PseudoVFMSAC_VV_M4_E16, 0x3, false }, // 601 |
| 610 | { PseudoVFMSAC_VV_M4_E32_MASK, PseudoVFMSAC_VV_M4_E32, 0x3, false }, // 602 |
| 611 | { PseudoVFMSAC_VV_M4_E64_MASK, PseudoVFMSAC_VV_M4_E64, 0x3, false }, // 603 |
| 612 | { PseudoVFMSAC_VV_M8_E16_MASK, PseudoVFMSAC_VV_M8_E16, 0x3, false }, // 604 |
| 613 | { PseudoVFMSAC_VV_M8_E32_MASK, PseudoVFMSAC_VV_M8_E32, 0x3, false }, // 605 |
| 614 | { PseudoVFMSAC_VV_M8_E64_MASK, PseudoVFMSAC_VV_M8_E64, 0x3, false }, // 606 |
| 615 | { PseudoVFMSAC_VV_MF2_E16_MASK, PseudoVFMSAC_VV_MF2_E16, 0x3, false }, // 607 |
| 616 | { PseudoVFMSAC_VV_MF2_E32_MASK, PseudoVFMSAC_VV_MF2_E32, 0x3, false }, // 608 |
| 617 | { PseudoVFMSAC_VV_MF4_E16_MASK, PseudoVFMSAC_VV_MF4_E16, 0x3, false }, // 609 |
| 618 | { PseudoVFMSUB_VFPR16_M1_E16_MASK, PseudoVFMSUB_VFPR16_M1_E16, 0x3, false }, // 610 |
| 619 | { PseudoVFMSUB_VFPR16_M2_E16_MASK, PseudoVFMSUB_VFPR16_M2_E16, 0x3, false }, // 611 |
| 620 | { PseudoVFMSUB_VFPR16_M4_E16_MASK, PseudoVFMSUB_VFPR16_M4_E16, 0x3, false }, // 612 |
| 621 | { PseudoVFMSUB_VFPR16_M8_E16_MASK, PseudoVFMSUB_VFPR16_M8_E16, 0x3, false }, // 613 |
| 622 | { PseudoVFMSUB_VFPR16_MF2_E16_MASK, PseudoVFMSUB_VFPR16_MF2_E16, 0x3, false }, // 614 |
| 623 | { PseudoVFMSUB_VFPR16_MF4_E16_MASK, PseudoVFMSUB_VFPR16_MF4_E16, 0x3, false }, // 615 |
| 624 | { PseudoVFMSUB_VFPR32_M1_E32_MASK, PseudoVFMSUB_VFPR32_M1_E32, 0x3, false }, // 616 |
| 625 | { PseudoVFMSUB_VFPR32_M2_E32_MASK, PseudoVFMSUB_VFPR32_M2_E32, 0x3, false }, // 617 |
| 626 | { PseudoVFMSUB_VFPR32_M4_E32_MASK, PseudoVFMSUB_VFPR32_M4_E32, 0x3, false }, // 618 |
| 627 | { PseudoVFMSUB_VFPR32_M8_E32_MASK, PseudoVFMSUB_VFPR32_M8_E32, 0x3, false }, // 619 |
| 628 | { PseudoVFMSUB_VFPR32_MF2_E32_MASK, PseudoVFMSUB_VFPR32_MF2_E32, 0x3, false }, // 620 |
| 629 | { PseudoVFMSUB_VFPR64_M1_E64_MASK, PseudoVFMSUB_VFPR64_M1_E64, 0x3, false }, // 621 |
| 630 | { PseudoVFMSUB_VFPR64_M2_E64_MASK, PseudoVFMSUB_VFPR64_M2_E64, 0x3, false }, // 622 |
| 631 | { PseudoVFMSUB_VFPR64_M4_E64_MASK, PseudoVFMSUB_VFPR64_M4_E64, 0x3, false }, // 623 |
| 632 | { PseudoVFMSUB_VFPR64_M8_E64_MASK, PseudoVFMSUB_VFPR64_M8_E64, 0x3, false }, // 624 |
| 633 | { PseudoVFMSUB_VV_M1_E16_MASK, PseudoVFMSUB_VV_M1_E16, 0x3, false }, // 625 |
| 634 | { PseudoVFMSUB_VV_M1_E32_MASK, PseudoVFMSUB_VV_M1_E32, 0x3, false }, // 626 |
| 635 | { PseudoVFMSUB_VV_M1_E64_MASK, PseudoVFMSUB_VV_M1_E64, 0x3, false }, // 627 |
| 636 | { PseudoVFMSUB_VV_M2_E16_MASK, PseudoVFMSUB_VV_M2_E16, 0x3, false }, // 628 |
| 637 | { PseudoVFMSUB_VV_M2_E32_MASK, PseudoVFMSUB_VV_M2_E32, 0x3, false }, // 629 |
| 638 | { PseudoVFMSUB_VV_M2_E64_MASK, PseudoVFMSUB_VV_M2_E64, 0x3, false }, // 630 |
| 639 | { PseudoVFMSUB_VV_M4_E16_MASK, PseudoVFMSUB_VV_M4_E16, 0x3, false }, // 631 |
| 640 | { PseudoVFMSUB_VV_M4_E32_MASK, PseudoVFMSUB_VV_M4_E32, 0x3, false }, // 632 |
| 641 | { PseudoVFMSUB_VV_M4_E64_MASK, PseudoVFMSUB_VV_M4_E64, 0x3, false }, // 633 |
| 642 | { PseudoVFMSUB_VV_M8_E16_MASK, PseudoVFMSUB_VV_M8_E16, 0x3, false }, // 634 |
| 643 | { PseudoVFMSUB_VV_M8_E32_MASK, PseudoVFMSUB_VV_M8_E32, 0x3, false }, // 635 |
| 644 | { PseudoVFMSUB_VV_M8_E64_MASK, PseudoVFMSUB_VV_M8_E64, 0x3, false }, // 636 |
| 645 | { PseudoVFMSUB_VV_MF2_E16_MASK, PseudoVFMSUB_VV_MF2_E16, 0x3, false }, // 637 |
| 646 | { PseudoVFMSUB_VV_MF2_E32_MASK, PseudoVFMSUB_VV_MF2_E32, 0x3, false }, // 638 |
| 647 | { PseudoVFMSUB_VV_MF4_E16_MASK, PseudoVFMSUB_VV_MF4_E16, 0x3, false }, // 639 |
| 648 | { PseudoVFMUL_VFPR16_M1_E16_MASK, PseudoVFMUL_VFPR16_M1_E16, 0x3, false }, // 640 |
| 649 | { PseudoVFMUL_VFPR16_M2_E16_MASK, PseudoVFMUL_VFPR16_M2_E16, 0x3, false }, // 641 |
| 650 | { PseudoVFMUL_VFPR16_M4_E16_MASK, PseudoVFMUL_VFPR16_M4_E16, 0x3, false }, // 642 |
| 651 | { PseudoVFMUL_VFPR16_M8_E16_MASK, PseudoVFMUL_VFPR16_M8_E16, 0x3, false }, // 643 |
| 652 | { PseudoVFMUL_VFPR16_MF2_E16_MASK, PseudoVFMUL_VFPR16_MF2_E16, 0x3, false }, // 644 |
| 653 | { PseudoVFMUL_VFPR16_MF4_E16_MASK, PseudoVFMUL_VFPR16_MF4_E16, 0x3, false }, // 645 |
| 654 | { PseudoVFMUL_VFPR32_M1_E32_MASK, PseudoVFMUL_VFPR32_M1_E32, 0x3, false }, // 646 |
| 655 | { PseudoVFMUL_VFPR32_M2_E32_MASK, PseudoVFMUL_VFPR32_M2_E32, 0x3, false }, // 647 |
| 656 | { PseudoVFMUL_VFPR32_M4_E32_MASK, PseudoVFMUL_VFPR32_M4_E32, 0x3, false }, // 648 |
| 657 | { PseudoVFMUL_VFPR32_M8_E32_MASK, PseudoVFMUL_VFPR32_M8_E32, 0x3, false }, // 649 |
| 658 | { PseudoVFMUL_VFPR32_MF2_E32_MASK, PseudoVFMUL_VFPR32_MF2_E32, 0x3, false }, // 650 |
| 659 | { PseudoVFMUL_VFPR64_M1_E64_MASK, PseudoVFMUL_VFPR64_M1_E64, 0x3, false }, // 651 |
| 660 | { PseudoVFMUL_VFPR64_M2_E64_MASK, PseudoVFMUL_VFPR64_M2_E64, 0x3, false }, // 652 |
| 661 | { PseudoVFMUL_VFPR64_M4_E64_MASK, PseudoVFMUL_VFPR64_M4_E64, 0x3, false }, // 653 |
| 662 | { PseudoVFMUL_VFPR64_M8_E64_MASK, PseudoVFMUL_VFPR64_M8_E64, 0x3, false }, // 654 |
| 663 | { PseudoVFMUL_VV_M1_E16_MASK, PseudoVFMUL_VV_M1_E16, 0x3, false }, // 655 |
| 664 | { PseudoVFMUL_VV_M1_E32_MASK, PseudoVFMUL_VV_M1_E32, 0x3, false }, // 656 |
| 665 | { PseudoVFMUL_VV_M1_E64_MASK, PseudoVFMUL_VV_M1_E64, 0x3, false }, // 657 |
| 666 | { PseudoVFMUL_VV_M2_E16_MASK, PseudoVFMUL_VV_M2_E16, 0x3, false }, // 658 |
| 667 | { PseudoVFMUL_VV_M2_E32_MASK, PseudoVFMUL_VV_M2_E32, 0x3, false }, // 659 |
| 668 | { PseudoVFMUL_VV_M2_E64_MASK, PseudoVFMUL_VV_M2_E64, 0x3, false }, // 660 |
| 669 | { PseudoVFMUL_VV_M4_E16_MASK, PseudoVFMUL_VV_M4_E16, 0x3, false }, // 661 |
| 670 | { PseudoVFMUL_VV_M4_E32_MASK, PseudoVFMUL_VV_M4_E32, 0x3, false }, // 662 |
| 671 | { PseudoVFMUL_VV_M4_E64_MASK, PseudoVFMUL_VV_M4_E64, 0x3, false }, // 663 |
| 672 | { PseudoVFMUL_VV_M8_E16_MASK, PseudoVFMUL_VV_M8_E16, 0x3, false }, // 664 |
| 673 | { PseudoVFMUL_VV_M8_E32_MASK, PseudoVFMUL_VV_M8_E32, 0x3, false }, // 665 |
| 674 | { PseudoVFMUL_VV_M8_E64_MASK, PseudoVFMUL_VV_M8_E64, 0x3, false }, // 666 |
| 675 | { PseudoVFMUL_VV_MF2_E16_MASK, PseudoVFMUL_VV_MF2_E16, 0x3, false }, // 667 |
| 676 | { PseudoVFMUL_VV_MF2_E32_MASK, PseudoVFMUL_VV_MF2_E32, 0x3, false }, // 668 |
| 677 | { PseudoVFMUL_VV_MF4_E16_MASK, PseudoVFMUL_VV_MF4_E16, 0x3, false }, // 669 |
| 678 | { PseudoVFNCVTBF16_F_F_W_M1_E16_MASK, PseudoVFNCVTBF16_F_F_W_M1_E16, 0x2, false }, // 670 |
| 679 | { PseudoVFNCVTBF16_F_F_W_M1_E32_MASK, PseudoVFNCVTBF16_F_F_W_M1_E32, 0x2, false }, // 671 |
| 680 | { PseudoVFNCVTBF16_F_F_W_M2_E16_MASK, PseudoVFNCVTBF16_F_F_W_M2_E16, 0x2, false }, // 672 |
| 681 | { PseudoVFNCVTBF16_F_F_W_M2_E32_MASK, PseudoVFNCVTBF16_F_F_W_M2_E32, 0x2, false }, // 673 |
| 682 | { PseudoVFNCVTBF16_F_F_W_M4_E16_MASK, PseudoVFNCVTBF16_F_F_W_M4_E16, 0x2, false }, // 674 |
| 683 | { PseudoVFNCVTBF16_F_F_W_M4_E32_MASK, PseudoVFNCVTBF16_F_F_W_M4_E32, 0x2, false }, // 675 |
| 684 | { PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK, PseudoVFNCVTBF16_F_F_W_MF2_E16, 0x2, false }, // 676 |
| 685 | { PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK, PseudoVFNCVTBF16_F_F_W_MF2_E32, 0x2, false }, // 677 |
| 686 | { PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK, PseudoVFNCVTBF16_F_F_W_MF4_E16, 0x2, false }, // 678 |
| 687 | { PseudoVFNCVT_F_F_W_M1_E16_MASK, PseudoVFNCVT_F_F_W_M1_E16, 0x2, false }, // 679 |
| 688 | { PseudoVFNCVT_F_F_W_M1_E32_MASK, PseudoVFNCVT_F_F_W_M1_E32, 0x2, false }, // 680 |
| 689 | { PseudoVFNCVT_F_F_W_M2_E16_MASK, PseudoVFNCVT_F_F_W_M2_E16, 0x2, false }, // 681 |
| 690 | { PseudoVFNCVT_F_F_W_M2_E32_MASK, PseudoVFNCVT_F_F_W_M2_E32, 0x2, false }, // 682 |
| 691 | { PseudoVFNCVT_F_F_W_M4_E16_MASK, PseudoVFNCVT_F_F_W_M4_E16, 0x2, false }, // 683 |
| 692 | { PseudoVFNCVT_F_F_W_M4_E32_MASK, PseudoVFNCVT_F_F_W_M4_E32, 0x2, false }, // 684 |
| 693 | { PseudoVFNCVT_F_F_W_MF2_E16_MASK, PseudoVFNCVT_F_F_W_MF2_E16, 0x2, false }, // 685 |
| 694 | { PseudoVFNCVT_F_F_W_MF2_E32_MASK, PseudoVFNCVT_F_F_W_MF2_E32, 0x2, false }, // 686 |
| 695 | { PseudoVFNCVT_F_F_W_MF4_E16_MASK, PseudoVFNCVT_F_F_W_MF4_E16, 0x2, false }, // 687 |
| 696 | { PseudoVFNCVT_F_XU_W_M1_E16_MASK, PseudoVFNCVT_F_XU_W_M1_E16, 0x2, false }, // 688 |
| 697 | { PseudoVFNCVT_F_XU_W_M1_E32_MASK, PseudoVFNCVT_F_XU_W_M1_E32, 0x2, false }, // 689 |
| 698 | { PseudoVFNCVT_F_XU_W_M2_E16_MASK, PseudoVFNCVT_F_XU_W_M2_E16, 0x2, false }, // 690 |
| 699 | { PseudoVFNCVT_F_XU_W_M2_E32_MASK, PseudoVFNCVT_F_XU_W_M2_E32, 0x2, false }, // 691 |
| 700 | { PseudoVFNCVT_F_XU_W_M4_E16_MASK, PseudoVFNCVT_F_XU_W_M4_E16, 0x2, false }, // 692 |
| 701 | { PseudoVFNCVT_F_XU_W_M4_E32_MASK, PseudoVFNCVT_F_XU_W_M4_E32, 0x2, false }, // 693 |
| 702 | { PseudoVFNCVT_F_XU_W_MF2_E16_MASK, PseudoVFNCVT_F_XU_W_MF2_E16, 0x2, false }, // 694 |
| 703 | { PseudoVFNCVT_F_XU_W_MF2_E32_MASK, PseudoVFNCVT_F_XU_W_MF2_E32, 0x2, false }, // 695 |
| 704 | { PseudoVFNCVT_F_XU_W_MF4_E16_MASK, PseudoVFNCVT_F_XU_W_MF4_E16, 0x2, false }, // 696 |
| 705 | { PseudoVFNCVT_F_X_W_M1_E16_MASK, PseudoVFNCVT_F_X_W_M1_E16, 0x2, false }, // 697 |
| 706 | { PseudoVFNCVT_F_X_W_M1_E32_MASK, PseudoVFNCVT_F_X_W_M1_E32, 0x2, false }, // 698 |
| 707 | { PseudoVFNCVT_F_X_W_M2_E16_MASK, PseudoVFNCVT_F_X_W_M2_E16, 0x2, false }, // 699 |
| 708 | { PseudoVFNCVT_F_X_W_M2_E32_MASK, PseudoVFNCVT_F_X_W_M2_E32, 0x2, false }, // 700 |
| 709 | { PseudoVFNCVT_F_X_W_M4_E16_MASK, PseudoVFNCVT_F_X_W_M4_E16, 0x2, false }, // 701 |
| 710 | { PseudoVFNCVT_F_X_W_M4_E32_MASK, PseudoVFNCVT_F_X_W_M4_E32, 0x2, false }, // 702 |
| 711 | { PseudoVFNCVT_F_X_W_MF2_E16_MASK, PseudoVFNCVT_F_X_W_MF2_E16, 0x2, false }, // 703 |
| 712 | { PseudoVFNCVT_F_X_W_MF2_E32_MASK, PseudoVFNCVT_F_X_W_MF2_E32, 0x2, false }, // 704 |
| 713 | { PseudoVFNCVT_F_X_W_MF4_E16_MASK, PseudoVFNCVT_F_X_W_MF4_E16, 0x2, false }, // 705 |
| 714 | { PseudoVFNCVT_RM_F_XU_W_M1_E16_MASK, PseudoVFNCVT_RM_F_XU_W_M1_E16, 0x2, false }, // 706 |
| 715 | { PseudoVFNCVT_RM_F_XU_W_M1_E32_MASK, PseudoVFNCVT_RM_F_XU_W_M1_E32, 0x2, false }, // 707 |
| 716 | { PseudoVFNCVT_RM_F_XU_W_M2_E16_MASK, PseudoVFNCVT_RM_F_XU_W_M2_E16, 0x2, false }, // 708 |
| 717 | { PseudoVFNCVT_RM_F_XU_W_M2_E32_MASK, PseudoVFNCVT_RM_F_XU_W_M2_E32, 0x2, false }, // 709 |
| 718 | { PseudoVFNCVT_RM_F_XU_W_M4_E16_MASK, PseudoVFNCVT_RM_F_XU_W_M4_E16, 0x2, false }, // 710 |
| 719 | { PseudoVFNCVT_RM_F_XU_W_M4_E32_MASK, PseudoVFNCVT_RM_F_XU_W_M4_E32, 0x2, false }, // 711 |
| 720 | { PseudoVFNCVT_RM_F_XU_W_MF2_E16_MASK, PseudoVFNCVT_RM_F_XU_W_MF2_E16, 0x2, false }, // 712 |
| 721 | { PseudoVFNCVT_RM_F_XU_W_MF2_E32_MASK, PseudoVFNCVT_RM_F_XU_W_MF2_E32, 0x2, false }, // 713 |
| 722 | { PseudoVFNCVT_RM_F_XU_W_MF4_E16_MASK, PseudoVFNCVT_RM_F_XU_W_MF4_E16, 0x2, false }, // 714 |
| 723 | { PseudoVFNCVT_RM_F_X_W_M1_E16_MASK, PseudoVFNCVT_RM_F_X_W_M1_E16, 0x2, false }, // 715 |
| 724 | { PseudoVFNCVT_RM_F_X_W_M1_E32_MASK, PseudoVFNCVT_RM_F_X_W_M1_E32, 0x2, false }, // 716 |
| 725 | { PseudoVFNCVT_RM_F_X_W_M2_E16_MASK, PseudoVFNCVT_RM_F_X_W_M2_E16, 0x2, false }, // 717 |
| 726 | { PseudoVFNCVT_RM_F_X_W_M2_E32_MASK, PseudoVFNCVT_RM_F_X_W_M2_E32, 0x2, false }, // 718 |
| 727 | { PseudoVFNCVT_RM_F_X_W_M4_E16_MASK, PseudoVFNCVT_RM_F_X_W_M4_E16, 0x2, false }, // 719 |
| 728 | { PseudoVFNCVT_RM_F_X_W_M4_E32_MASK, PseudoVFNCVT_RM_F_X_W_M4_E32, 0x2, false }, // 720 |
| 729 | { PseudoVFNCVT_RM_F_X_W_MF2_E16_MASK, PseudoVFNCVT_RM_F_X_W_MF2_E16, 0x2, false }, // 721 |
| 730 | { PseudoVFNCVT_RM_F_X_W_MF2_E32_MASK, PseudoVFNCVT_RM_F_X_W_MF2_E32, 0x2, false }, // 722 |
| 731 | { PseudoVFNCVT_RM_F_X_W_MF4_E16_MASK, PseudoVFNCVT_RM_F_X_W_MF4_E16, 0x2, false }, // 723 |
| 732 | { PseudoVFNCVT_RM_XU_F_W_M1_MASK, PseudoVFNCVT_RM_XU_F_W_M1, 0x2, false }, // 724 |
| 733 | { PseudoVFNCVT_RM_XU_F_W_M2_MASK, PseudoVFNCVT_RM_XU_F_W_M2, 0x2, false }, // 725 |
| 734 | { PseudoVFNCVT_RM_XU_F_W_M4_MASK, PseudoVFNCVT_RM_XU_F_W_M4, 0x2, false }, // 726 |
| 735 | { PseudoVFNCVT_RM_XU_F_W_MF2_MASK, PseudoVFNCVT_RM_XU_F_W_MF2, 0x2, false }, // 727 |
| 736 | { PseudoVFNCVT_RM_XU_F_W_MF4_MASK, PseudoVFNCVT_RM_XU_F_W_MF4, 0x2, false }, // 728 |
| 737 | { PseudoVFNCVT_RM_XU_F_W_MF8_MASK, PseudoVFNCVT_RM_XU_F_W_MF8, 0x2, false }, // 729 |
| 738 | { PseudoVFNCVT_RM_X_F_W_M1_MASK, PseudoVFNCVT_RM_X_F_W_M1, 0x2, false }, // 730 |
| 739 | { PseudoVFNCVT_RM_X_F_W_M2_MASK, PseudoVFNCVT_RM_X_F_W_M2, 0x2, false }, // 731 |
| 740 | { PseudoVFNCVT_RM_X_F_W_M4_MASK, PseudoVFNCVT_RM_X_F_W_M4, 0x2, false }, // 732 |
| 741 | { PseudoVFNCVT_RM_X_F_W_MF2_MASK, PseudoVFNCVT_RM_X_F_W_MF2, 0x2, false }, // 733 |
| 742 | { PseudoVFNCVT_RM_X_F_W_MF4_MASK, PseudoVFNCVT_RM_X_F_W_MF4, 0x2, false }, // 734 |
| 743 | { PseudoVFNCVT_RM_X_F_W_MF8_MASK, PseudoVFNCVT_RM_X_F_W_MF8, 0x2, false }, // 735 |
| 744 | { PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK, PseudoVFNCVT_ROD_F_F_W_M1_E16, 0x2, false }, // 736 |
| 745 | { PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK, PseudoVFNCVT_ROD_F_F_W_M1_E32, 0x2, false }, // 737 |
| 746 | { PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK, PseudoVFNCVT_ROD_F_F_W_M2_E16, 0x2, false }, // 738 |
| 747 | { PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK, PseudoVFNCVT_ROD_F_F_W_M2_E32, 0x2, false }, // 739 |
| 748 | { PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK, PseudoVFNCVT_ROD_F_F_W_M4_E16, 0x2, false }, // 740 |
| 749 | { PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK, PseudoVFNCVT_ROD_F_F_W_M4_E32, 0x2, false }, // 741 |
| 750 | { PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK, PseudoVFNCVT_ROD_F_F_W_MF2_E16, 0x2, false }, // 742 |
| 751 | { PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK, PseudoVFNCVT_ROD_F_F_W_MF2_E32, 0x2, false }, // 743 |
| 752 | { PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK, PseudoVFNCVT_ROD_F_F_W_MF4_E16, 0x2, false }, // 744 |
| 753 | { PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, PseudoVFNCVT_RTZ_XU_F_W_M1, 0x2, false }, // 745 |
| 754 | { PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, PseudoVFNCVT_RTZ_XU_F_W_M2, 0x2, false }, // 746 |
| 755 | { PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, PseudoVFNCVT_RTZ_XU_F_W_M4, 0x2, false }, // 747 |
| 756 | { PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF2, 0x2, false }, // 748 |
| 757 | { PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF4, 0x2, false }, // 749 |
| 758 | { PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF8, 0x2, false }, // 750 |
| 759 | { PseudoVFNCVT_RTZ_X_F_W_M1_MASK, PseudoVFNCVT_RTZ_X_F_W_M1, 0x2, false }, // 751 |
| 760 | { PseudoVFNCVT_RTZ_X_F_W_M2_MASK, PseudoVFNCVT_RTZ_X_F_W_M2, 0x2, false }, // 752 |
| 761 | { PseudoVFNCVT_RTZ_X_F_W_M4_MASK, PseudoVFNCVT_RTZ_X_F_W_M4, 0x2, false }, // 753 |
| 762 | { PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, PseudoVFNCVT_RTZ_X_F_W_MF2, 0x2, false }, // 754 |
| 763 | { PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, PseudoVFNCVT_RTZ_X_F_W_MF4, 0x2, false }, // 755 |
| 764 | { PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, PseudoVFNCVT_RTZ_X_F_W_MF8, 0x2, false }, // 756 |
| 765 | { PseudoVFNCVT_XU_F_W_M1_MASK, PseudoVFNCVT_XU_F_W_M1, 0x2, false }, // 757 |
| 766 | { PseudoVFNCVT_XU_F_W_M2_MASK, PseudoVFNCVT_XU_F_W_M2, 0x2, false }, // 758 |
| 767 | { PseudoVFNCVT_XU_F_W_M4_MASK, PseudoVFNCVT_XU_F_W_M4, 0x2, false }, // 759 |
| 768 | { PseudoVFNCVT_XU_F_W_MF2_MASK, PseudoVFNCVT_XU_F_W_MF2, 0x2, false }, // 760 |
| 769 | { PseudoVFNCVT_XU_F_W_MF4_MASK, PseudoVFNCVT_XU_F_W_MF4, 0x2, false }, // 761 |
| 770 | { PseudoVFNCVT_XU_F_W_MF8_MASK, PseudoVFNCVT_XU_F_W_MF8, 0x2, false }, // 762 |
| 771 | { PseudoVFNCVT_X_F_W_M1_MASK, PseudoVFNCVT_X_F_W_M1, 0x2, false }, // 763 |
| 772 | { PseudoVFNCVT_X_F_W_M2_MASK, PseudoVFNCVT_X_F_W_M2, 0x2, false }, // 764 |
| 773 | { PseudoVFNCVT_X_F_W_M4_MASK, PseudoVFNCVT_X_F_W_M4, 0x2, false }, // 765 |
| 774 | { PseudoVFNCVT_X_F_W_MF2_MASK, PseudoVFNCVT_X_F_W_MF2, 0x2, false }, // 766 |
| 775 | { PseudoVFNCVT_X_F_W_MF4_MASK, PseudoVFNCVT_X_F_W_MF4, 0x2, false }, // 767 |
| 776 | { PseudoVFNCVT_X_F_W_MF8_MASK, PseudoVFNCVT_X_F_W_MF8, 0x2, false }, // 768 |
| 777 | { PseudoVFNMACC_VFPR16_M1_E16_MASK, PseudoVFNMACC_VFPR16_M1_E16, 0x3, false }, // 769 |
| 778 | { PseudoVFNMACC_VFPR16_M2_E16_MASK, PseudoVFNMACC_VFPR16_M2_E16, 0x3, false }, // 770 |
| 779 | { PseudoVFNMACC_VFPR16_M4_E16_MASK, PseudoVFNMACC_VFPR16_M4_E16, 0x3, false }, // 771 |
| 780 | { PseudoVFNMACC_VFPR16_M8_E16_MASK, PseudoVFNMACC_VFPR16_M8_E16, 0x3, false }, // 772 |
| 781 | { PseudoVFNMACC_VFPR16_MF2_E16_MASK, PseudoVFNMACC_VFPR16_MF2_E16, 0x3, false }, // 773 |
| 782 | { PseudoVFNMACC_VFPR16_MF4_E16_MASK, PseudoVFNMACC_VFPR16_MF4_E16, 0x3, false }, // 774 |
| 783 | { PseudoVFNMACC_VFPR32_M1_E32_MASK, PseudoVFNMACC_VFPR32_M1_E32, 0x3, false }, // 775 |
| 784 | { PseudoVFNMACC_VFPR32_M2_E32_MASK, PseudoVFNMACC_VFPR32_M2_E32, 0x3, false }, // 776 |
| 785 | { PseudoVFNMACC_VFPR32_M4_E32_MASK, PseudoVFNMACC_VFPR32_M4_E32, 0x3, false }, // 777 |
| 786 | { PseudoVFNMACC_VFPR32_M8_E32_MASK, PseudoVFNMACC_VFPR32_M8_E32, 0x3, false }, // 778 |
| 787 | { PseudoVFNMACC_VFPR32_MF2_E32_MASK, PseudoVFNMACC_VFPR32_MF2_E32, 0x3, false }, // 779 |
| 788 | { PseudoVFNMACC_VFPR64_M1_E64_MASK, PseudoVFNMACC_VFPR64_M1_E64, 0x3, false }, // 780 |
| 789 | { PseudoVFNMACC_VFPR64_M2_E64_MASK, PseudoVFNMACC_VFPR64_M2_E64, 0x3, false }, // 781 |
| 790 | { PseudoVFNMACC_VFPR64_M4_E64_MASK, PseudoVFNMACC_VFPR64_M4_E64, 0x3, false }, // 782 |
| 791 | { PseudoVFNMACC_VFPR64_M8_E64_MASK, PseudoVFNMACC_VFPR64_M8_E64, 0x3, false }, // 783 |
| 792 | { PseudoVFNMACC_VV_M1_E16_MASK, PseudoVFNMACC_VV_M1_E16, 0x3, false }, // 784 |
| 793 | { PseudoVFNMACC_VV_M1_E32_MASK, PseudoVFNMACC_VV_M1_E32, 0x3, false }, // 785 |
| 794 | { PseudoVFNMACC_VV_M1_E64_MASK, PseudoVFNMACC_VV_M1_E64, 0x3, false }, // 786 |
| 795 | { PseudoVFNMACC_VV_M2_E16_MASK, PseudoVFNMACC_VV_M2_E16, 0x3, false }, // 787 |
| 796 | { PseudoVFNMACC_VV_M2_E32_MASK, PseudoVFNMACC_VV_M2_E32, 0x3, false }, // 788 |
| 797 | { PseudoVFNMACC_VV_M2_E64_MASK, PseudoVFNMACC_VV_M2_E64, 0x3, false }, // 789 |
| 798 | { PseudoVFNMACC_VV_M4_E16_MASK, PseudoVFNMACC_VV_M4_E16, 0x3, false }, // 790 |
| 799 | { PseudoVFNMACC_VV_M4_E32_MASK, PseudoVFNMACC_VV_M4_E32, 0x3, false }, // 791 |
| 800 | { PseudoVFNMACC_VV_M4_E64_MASK, PseudoVFNMACC_VV_M4_E64, 0x3, false }, // 792 |
| 801 | { PseudoVFNMACC_VV_M8_E16_MASK, PseudoVFNMACC_VV_M8_E16, 0x3, false }, // 793 |
| 802 | { PseudoVFNMACC_VV_M8_E32_MASK, PseudoVFNMACC_VV_M8_E32, 0x3, false }, // 794 |
| 803 | { PseudoVFNMACC_VV_M8_E64_MASK, PseudoVFNMACC_VV_M8_E64, 0x3, false }, // 795 |
| 804 | { PseudoVFNMACC_VV_MF2_E16_MASK, PseudoVFNMACC_VV_MF2_E16, 0x3, false }, // 796 |
| 805 | { PseudoVFNMACC_VV_MF2_E32_MASK, PseudoVFNMACC_VV_MF2_E32, 0x3, false }, // 797 |
| 806 | { PseudoVFNMACC_VV_MF4_E16_MASK, PseudoVFNMACC_VV_MF4_E16, 0x3, false }, // 798 |
| 807 | { PseudoVFNMADD_VFPR16_M1_E16_MASK, PseudoVFNMADD_VFPR16_M1_E16, 0x3, false }, // 799 |
| 808 | { PseudoVFNMADD_VFPR16_M2_E16_MASK, PseudoVFNMADD_VFPR16_M2_E16, 0x3, false }, // 800 |
| 809 | { PseudoVFNMADD_VFPR16_M4_E16_MASK, PseudoVFNMADD_VFPR16_M4_E16, 0x3, false }, // 801 |
| 810 | { PseudoVFNMADD_VFPR16_M8_E16_MASK, PseudoVFNMADD_VFPR16_M8_E16, 0x3, false }, // 802 |
| 811 | { PseudoVFNMADD_VFPR16_MF2_E16_MASK, PseudoVFNMADD_VFPR16_MF2_E16, 0x3, false }, // 803 |
| 812 | { PseudoVFNMADD_VFPR16_MF4_E16_MASK, PseudoVFNMADD_VFPR16_MF4_E16, 0x3, false }, // 804 |
| 813 | { PseudoVFNMADD_VFPR32_M1_E32_MASK, PseudoVFNMADD_VFPR32_M1_E32, 0x3, false }, // 805 |
| 814 | { PseudoVFNMADD_VFPR32_M2_E32_MASK, PseudoVFNMADD_VFPR32_M2_E32, 0x3, false }, // 806 |
| 815 | { PseudoVFNMADD_VFPR32_M4_E32_MASK, PseudoVFNMADD_VFPR32_M4_E32, 0x3, false }, // 807 |
| 816 | { PseudoVFNMADD_VFPR32_M8_E32_MASK, PseudoVFNMADD_VFPR32_M8_E32, 0x3, false }, // 808 |
| 817 | { PseudoVFNMADD_VFPR32_MF2_E32_MASK, PseudoVFNMADD_VFPR32_MF2_E32, 0x3, false }, // 809 |
| 818 | { PseudoVFNMADD_VFPR64_M1_E64_MASK, PseudoVFNMADD_VFPR64_M1_E64, 0x3, false }, // 810 |
| 819 | { PseudoVFNMADD_VFPR64_M2_E64_MASK, PseudoVFNMADD_VFPR64_M2_E64, 0x3, false }, // 811 |
| 820 | { PseudoVFNMADD_VFPR64_M4_E64_MASK, PseudoVFNMADD_VFPR64_M4_E64, 0x3, false }, // 812 |
| 821 | { PseudoVFNMADD_VFPR64_M8_E64_MASK, PseudoVFNMADD_VFPR64_M8_E64, 0x3, false }, // 813 |
| 822 | { PseudoVFNMADD_VV_M1_E16_MASK, PseudoVFNMADD_VV_M1_E16, 0x3, false }, // 814 |
| 823 | { PseudoVFNMADD_VV_M1_E32_MASK, PseudoVFNMADD_VV_M1_E32, 0x3, false }, // 815 |
| 824 | { PseudoVFNMADD_VV_M1_E64_MASK, PseudoVFNMADD_VV_M1_E64, 0x3, false }, // 816 |
| 825 | { PseudoVFNMADD_VV_M2_E16_MASK, PseudoVFNMADD_VV_M2_E16, 0x3, false }, // 817 |
| 826 | { PseudoVFNMADD_VV_M2_E32_MASK, PseudoVFNMADD_VV_M2_E32, 0x3, false }, // 818 |
| 827 | { PseudoVFNMADD_VV_M2_E64_MASK, PseudoVFNMADD_VV_M2_E64, 0x3, false }, // 819 |
| 828 | { PseudoVFNMADD_VV_M4_E16_MASK, PseudoVFNMADD_VV_M4_E16, 0x3, false }, // 820 |
| 829 | { PseudoVFNMADD_VV_M4_E32_MASK, PseudoVFNMADD_VV_M4_E32, 0x3, false }, // 821 |
| 830 | { PseudoVFNMADD_VV_M4_E64_MASK, PseudoVFNMADD_VV_M4_E64, 0x3, false }, // 822 |
| 831 | { PseudoVFNMADD_VV_M8_E16_MASK, PseudoVFNMADD_VV_M8_E16, 0x3, false }, // 823 |
| 832 | { PseudoVFNMADD_VV_M8_E32_MASK, PseudoVFNMADD_VV_M8_E32, 0x3, false }, // 824 |
| 833 | { PseudoVFNMADD_VV_M8_E64_MASK, PseudoVFNMADD_VV_M8_E64, 0x3, false }, // 825 |
| 834 | { PseudoVFNMADD_VV_MF2_E16_MASK, PseudoVFNMADD_VV_MF2_E16, 0x3, false }, // 826 |
| 835 | { PseudoVFNMADD_VV_MF2_E32_MASK, PseudoVFNMADD_VV_MF2_E32, 0x3, false }, // 827 |
| 836 | { PseudoVFNMADD_VV_MF4_E16_MASK, PseudoVFNMADD_VV_MF4_E16, 0x3, false }, // 828 |
| 837 | { PseudoVFNMSAC_VFPR16_M1_E16_MASK, PseudoVFNMSAC_VFPR16_M1_E16, 0x3, false }, // 829 |
| 838 | { PseudoVFNMSAC_VFPR16_M2_E16_MASK, PseudoVFNMSAC_VFPR16_M2_E16, 0x3, false }, // 830 |
| 839 | { PseudoVFNMSAC_VFPR16_M4_E16_MASK, PseudoVFNMSAC_VFPR16_M4_E16, 0x3, false }, // 831 |
| 840 | { PseudoVFNMSAC_VFPR16_M8_E16_MASK, PseudoVFNMSAC_VFPR16_M8_E16, 0x3, false }, // 832 |
| 841 | { PseudoVFNMSAC_VFPR16_MF2_E16_MASK, PseudoVFNMSAC_VFPR16_MF2_E16, 0x3, false }, // 833 |
| 842 | { PseudoVFNMSAC_VFPR16_MF4_E16_MASK, PseudoVFNMSAC_VFPR16_MF4_E16, 0x3, false }, // 834 |
| 843 | { PseudoVFNMSAC_VFPR32_M1_E32_MASK, PseudoVFNMSAC_VFPR32_M1_E32, 0x3, false }, // 835 |
| 844 | { PseudoVFNMSAC_VFPR32_M2_E32_MASK, PseudoVFNMSAC_VFPR32_M2_E32, 0x3, false }, // 836 |
| 845 | { PseudoVFNMSAC_VFPR32_M4_E32_MASK, PseudoVFNMSAC_VFPR32_M4_E32, 0x3, false }, // 837 |
| 846 | { PseudoVFNMSAC_VFPR32_M8_E32_MASK, PseudoVFNMSAC_VFPR32_M8_E32, 0x3, false }, // 838 |
| 847 | { PseudoVFNMSAC_VFPR32_MF2_E32_MASK, PseudoVFNMSAC_VFPR32_MF2_E32, 0x3, false }, // 839 |
| 848 | { PseudoVFNMSAC_VFPR64_M1_E64_MASK, PseudoVFNMSAC_VFPR64_M1_E64, 0x3, false }, // 840 |
| 849 | { PseudoVFNMSAC_VFPR64_M2_E64_MASK, PseudoVFNMSAC_VFPR64_M2_E64, 0x3, false }, // 841 |
| 850 | { PseudoVFNMSAC_VFPR64_M4_E64_MASK, PseudoVFNMSAC_VFPR64_M4_E64, 0x3, false }, // 842 |
| 851 | { PseudoVFNMSAC_VFPR64_M8_E64_MASK, PseudoVFNMSAC_VFPR64_M8_E64, 0x3, false }, // 843 |
| 852 | { PseudoVFNMSAC_VV_M1_E16_MASK, PseudoVFNMSAC_VV_M1_E16, 0x3, false }, // 844 |
| 853 | { PseudoVFNMSAC_VV_M1_E32_MASK, PseudoVFNMSAC_VV_M1_E32, 0x3, false }, // 845 |
| 854 | { PseudoVFNMSAC_VV_M1_E64_MASK, PseudoVFNMSAC_VV_M1_E64, 0x3, false }, // 846 |
| 855 | { PseudoVFNMSAC_VV_M2_E16_MASK, PseudoVFNMSAC_VV_M2_E16, 0x3, false }, // 847 |
| 856 | { PseudoVFNMSAC_VV_M2_E32_MASK, PseudoVFNMSAC_VV_M2_E32, 0x3, false }, // 848 |
| 857 | { PseudoVFNMSAC_VV_M2_E64_MASK, PseudoVFNMSAC_VV_M2_E64, 0x3, false }, // 849 |
| 858 | { PseudoVFNMSAC_VV_M4_E16_MASK, PseudoVFNMSAC_VV_M4_E16, 0x3, false }, // 850 |
| 859 | { PseudoVFNMSAC_VV_M4_E32_MASK, PseudoVFNMSAC_VV_M4_E32, 0x3, false }, // 851 |
| 860 | { PseudoVFNMSAC_VV_M4_E64_MASK, PseudoVFNMSAC_VV_M4_E64, 0x3, false }, // 852 |
| 861 | { PseudoVFNMSAC_VV_M8_E16_MASK, PseudoVFNMSAC_VV_M8_E16, 0x3, false }, // 853 |
| 862 | { PseudoVFNMSAC_VV_M8_E32_MASK, PseudoVFNMSAC_VV_M8_E32, 0x3, false }, // 854 |
| 863 | { PseudoVFNMSAC_VV_M8_E64_MASK, PseudoVFNMSAC_VV_M8_E64, 0x3, false }, // 855 |
| 864 | { PseudoVFNMSAC_VV_MF2_E16_MASK, PseudoVFNMSAC_VV_MF2_E16, 0x3, false }, // 856 |
| 865 | { PseudoVFNMSAC_VV_MF2_E32_MASK, PseudoVFNMSAC_VV_MF2_E32, 0x3, false }, // 857 |
| 866 | { PseudoVFNMSAC_VV_MF4_E16_MASK, PseudoVFNMSAC_VV_MF4_E16, 0x3, false }, // 858 |
| 867 | { PseudoVFNMSUB_VFPR16_M1_E16_MASK, PseudoVFNMSUB_VFPR16_M1_E16, 0x3, false }, // 859 |
| 868 | { PseudoVFNMSUB_VFPR16_M2_E16_MASK, PseudoVFNMSUB_VFPR16_M2_E16, 0x3, false }, // 860 |
| 869 | { PseudoVFNMSUB_VFPR16_M4_E16_MASK, PseudoVFNMSUB_VFPR16_M4_E16, 0x3, false }, // 861 |
| 870 | { PseudoVFNMSUB_VFPR16_M8_E16_MASK, PseudoVFNMSUB_VFPR16_M8_E16, 0x3, false }, // 862 |
| 871 | { PseudoVFNMSUB_VFPR16_MF2_E16_MASK, PseudoVFNMSUB_VFPR16_MF2_E16, 0x3, false }, // 863 |
| 872 | { PseudoVFNMSUB_VFPR16_MF4_E16_MASK, PseudoVFNMSUB_VFPR16_MF4_E16, 0x3, false }, // 864 |
| 873 | { PseudoVFNMSUB_VFPR32_M1_E32_MASK, PseudoVFNMSUB_VFPR32_M1_E32, 0x3, false }, // 865 |
| 874 | { PseudoVFNMSUB_VFPR32_M2_E32_MASK, PseudoVFNMSUB_VFPR32_M2_E32, 0x3, false }, // 866 |
| 875 | { PseudoVFNMSUB_VFPR32_M4_E32_MASK, PseudoVFNMSUB_VFPR32_M4_E32, 0x3, false }, // 867 |
| 876 | { PseudoVFNMSUB_VFPR32_M8_E32_MASK, PseudoVFNMSUB_VFPR32_M8_E32, 0x3, false }, // 868 |
| 877 | { PseudoVFNMSUB_VFPR32_MF2_E32_MASK, PseudoVFNMSUB_VFPR32_MF2_E32, 0x3, false }, // 869 |
| 878 | { PseudoVFNMSUB_VFPR64_M1_E64_MASK, PseudoVFNMSUB_VFPR64_M1_E64, 0x3, false }, // 870 |
| 879 | { PseudoVFNMSUB_VFPR64_M2_E64_MASK, PseudoVFNMSUB_VFPR64_M2_E64, 0x3, false }, // 871 |
| 880 | { PseudoVFNMSUB_VFPR64_M4_E64_MASK, PseudoVFNMSUB_VFPR64_M4_E64, 0x3, false }, // 872 |
| 881 | { PseudoVFNMSUB_VFPR64_M8_E64_MASK, PseudoVFNMSUB_VFPR64_M8_E64, 0x3, false }, // 873 |
| 882 | { PseudoVFNMSUB_VV_M1_E16_MASK, PseudoVFNMSUB_VV_M1_E16, 0x3, false }, // 874 |
| 883 | { PseudoVFNMSUB_VV_M1_E32_MASK, PseudoVFNMSUB_VV_M1_E32, 0x3, false }, // 875 |
| 884 | { PseudoVFNMSUB_VV_M1_E64_MASK, PseudoVFNMSUB_VV_M1_E64, 0x3, false }, // 876 |
| 885 | { PseudoVFNMSUB_VV_M2_E16_MASK, PseudoVFNMSUB_VV_M2_E16, 0x3, false }, // 877 |
| 886 | { PseudoVFNMSUB_VV_M2_E32_MASK, PseudoVFNMSUB_VV_M2_E32, 0x3, false }, // 878 |
| 887 | { PseudoVFNMSUB_VV_M2_E64_MASK, PseudoVFNMSUB_VV_M2_E64, 0x3, false }, // 879 |
| 888 | { PseudoVFNMSUB_VV_M4_E16_MASK, PseudoVFNMSUB_VV_M4_E16, 0x3, false }, // 880 |
| 889 | { PseudoVFNMSUB_VV_M4_E32_MASK, PseudoVFNMSUB_VV_M4_E32, 0x3, false }, // 881 |
| 890 | { PseudoVFNMSUB_VV_M4_E64_MASK, PseudoVFNMSUB_VV_M4_E64, 0x3, false }, // 882 |
| 891 | { PseudoVFNMSUB_VV_M8_E16_MASK, PseudoVFNMSUB_VV_M8_E16, 0x3, false }, // 883 |
| 892 | { PseudoVFNMSUB_VV_M8_E32_MASK, PseudoVFNMSUB_VV_M8_E32, 0x3, false }, // 884 |
| 893 | { PseudoVFNMSUB_VV_M8_E64_MASK, PseudoVFNMSUB_VV_M8_E64, 0x3, false }, // 885 |
| 894 | { PseudoVFNMSUB_VV_MF2_E16_MASK, PseudoVFNMSUB_VV_MF2_E16, 0x3, false }, // 886 |
| 895 | { PseudoVFNMSUB_VV_MF2_E32_MASK, PseudoVFNMSUB_VV_MF2_E32, 0x3, false }, // 887 |
| 896 | { PseudoVFNMSUB_VV_MF4_E16_MASK, PseudoVFNMSUB_VV_MF4_E16, 0x3, false }, // 888 |
| 897 | { PseudoVFNRCLIP_XU_F_QF_M1_MASK, PseudoVFNRCLIP_XU_F_QF_M1, 0x3, false }, // 889 |
| 898 | { PseudoVFNRCLIP_XU_F_QF_M2_MASK, PseudoVFNRCLIP_XU_F_QF_M2, 0x3, false }, // 890 |
| 899 | { PseudoVFNRCLIP_XU_F_QF_MF2_MASK, PseudoVFNRCLIP_XU_F_QF_MF2, 0x3, false }, // 891 |
| 900 | { PseudoVFNRCLIP_XU_F_QF_MF4_MASK, PseudoVFNRCLIP_XU_F_QF_MF4, 0x3, false }, // 892 |
| 901 | { PseudoVFNRCLIP_XU_F_QF_MF8_MASK, PseudoVFNRCLIP_XU_F_QF_MF8, 0x3, false }, // 893 |
| 902 | { PseudoVFNRCLIP_X_F_QF_M1_MASK, PseudoVFNRCLIP_X_F_QF_M1, 0x3, false }, // 894 |
| 903 | { PseudoVFNRCLIP_X_F_QF_M2_MASK, PseudoVFNRCLIP_X_F_QF_M2, 0x3, false }, // 895 |
| 904 | { PseudoVFNRCLIP_X_F_QF_MF2_MASK, PseudoVFNRCLIP_X_F_QF_MF2, 0x3, false }, // 896 |
| 905 | { PseudoVFNRCLIP_X_F_QF_MF4_MASK, PseudoVFNRCLIP_X_F_QF_MF4, 0x3, false }, // 897 |
| 906 | { PseudoVFNRCLIP_X_F_QF_MF8_MASK, PseudoVFNRCLIP_X_F_QF_MF8, 0x3, false }, // 898 |
| 907 | { PseudoVFRDIV_VFPR16_M1_E16_MASK, PseudoVFRDIV_VFPR16_M1_E16, 0x3, false }, // 899 |
| 908 | { PseudoVFRDIV_VFPR16_M2_E16_MASK, PseudoVFRDIV_VFPR16_M2_E16, 0x3, false }, // 900 |
| 909 | { PseudoVFRDIV_VFPR16_M4_E16_MASK, PseudoVFRDIV_VFPR16_M4_E16, 0x3, false }, // 901 |
| 910 | { PseudoVFRDIV_VFPR16_M8_E16_MASK, PseudoVFRDIV_VFPR16_M8_E16, 0x3, false }, // 902 |
| 911 | { PseudoVFRDIV_VFPR16_MF2_E16_MASK, PseudoVFRDIV_VFPR16_MF2_E16, 0x3, false }, // 903 |
| 912 | { PseudoVFRDIV_VFPR16_MF4_E16_MASK, PseudoVFRDIV_VFPR16_MF4_E16, 0x3, false }, // 904 |
| 913 | { PseudoVFRDIV_VFPR32_M1_E32_MASK, PseudoVFRDIV_VFPR32_M1_E32, 0x3, false }, // 905 |
| 914 | { PseudoVFRDIV_VFPR32_M2_E32_MASK, PseudoVFRDIV_VFPR32_M2_E32, 0x3, false }, // 906 |
| 915 | { PseudoVFRDIV_VFPR32_M4_E32_MASK, PseudoVFRDIV_VFPR32_M4_E32, 0x3, false }, // 907 |
| 916 | { PseudoVFRDIV_VFPR32_M8_E32_MASK, PseudoVFRDIV_VFPR32_M8_E32, 0x3, false }, // 908 |
| 917 | { PseudoVFRDIV_VFPR32_MF2_E32_MASK, PseudoVFRDIV_VFPR32_MF2_E32, 0x3, false }, // 909 |
| 918 | { PseudoVFRDIV_VFPR64_M1_E64_MASK, PseudoVFRDIV_VFPR64_M1_E64, 0x3, false }, // 910 |
| 919 | { PseudoVFRDIV_VFPR64_M2_E64_MASK, PseudoVFRDIV_VFPR64_M2_E64, 0x3, false }, // 911 |
| 920 | { PseudoVFRDIV_VFPR64_M4_E64_MASK, PseudoVFRDIV_VFPR64_M4_E64, 0x3, false }, // 912 |
| 921 | { PseudoVFRDIV_VFPR64_M8_E64_MASK, PseudoVFRDIV_VFPR64_M8_E64, 0x3, false }, // 913 |
| 922 | { PseudoVFREC7_V_M1_E16_MASK, PseudoVFREC7_V_M1_E16, 0x2, false }, // 914 |
| 923 | { PseudoVFREC7_V_M1_E32_MASK, PseudoVFREC7_V_M1_E32, 0x2, false }, // 915 |
| 924 | { PseudoVFREC7_V_M1_E64_MASK, PseudoVFREC7_V_M1_E64, 0x2, false }, // 916 |
| 925 | { PseudoVFREC7_V_M2_E16_MASK, PseudoVFREC7_V_M2_E16, 0x2, false }, // 917 |
| 926 | { PseudoVFREC7_V_M2_E32_MASK, PseudoVFREC7_V_M2_E32, 0x2, false }, // 918 |
| 927 | { PseudoVFREC7_V_M2_E64_MASK, PseudoVFREC7_V_M2_E64, 0x2, false }, // 919 |
| 928 | { PseudoVFREC7_V_M4_E16_MASK, PseudoVFREC7_V_M4_E16, 0x2, false }, // 920 |
| 929 | { PseudoVFREC7_V_M4_E32_MASK, PseudoVFREC7_V_M4_E32, 0x2, false }, // 921 |
| 930 | { PseudoVFREC7_V_M4_E64_MASK, PseudoVFREC7_V_M4_E64, 0x2, false }, // 922 |
| 931 | { PseudoVFREC7_V_M8_E16_MASK, PseudoVFREC7_V_M8_E16, 0x2, false }, // 923 |
| 932 | { PseudoVFREC7_V_M8_E32_MASK, PseudoVFREC7_V_M8_E32, 0x2, false }, // 924 |
| 933 | { PseudoVFREC7_V_M8_E64_MASK, PseudoVFREC7_V_M8_E64, 0x2, false }, // 925 |
| 934 | { PseudoVFREC7_V_MF2_E16_MASK, PseudoVFREC7_V_MF2_E16, 0x2, false }, // 926 |
| 935 | { PseudoVFREC7_V_MF2_E32_MASK, PseudoVFREC7_V_MF2_E32, 0x2, false }, // 927 |
| 936 | { PseudoVFREC7_V_MF4_E16_MASK, PseudoVFREC7_V_MF4_E16, 0x2, false }, // 928 |
| 937 | { PseudoVFREDMAX_VS_M1_E16_MASK, PseudoVFREDMAX_VS_M1_E16, 0x3, true }, // 929 |
| 938 | { PseudoVFREDMAX_VS_M1_E32_MASK, PseudoVFREDMAX_VS_M1_E32, 0x3, true }, // 930 |
| 939 | { PseudoVFREDMAX_VS_M1_E64_MASK, PseudoVFREDMAX_VS_M1_E64, 0x3, true }, // 931 |
| 940 | { PseudoVFREDMAX_VS_M2_E16_MASK, PseudoVFREDMAX_VS_M2_E16, 0x3, true }, // 932 |
| 941 | { PseudoVFREDMAX_VS_M2_E32_MASK, PseudoVFREDMAX_VS_M2_E32, 0x3, true }, // 933 |
| 942 | { PseudoVFREDMAX_VS_M2_E64_MASK, PseudoVFREDMAX_VS_M2_E64, 0x3, true }, // 934 |
| 943 | { PseudoVFREDMAX_VS_M4_E16_MASK, PseudoVFREDMAX_VS_M4_E16, 0x3, true }, // 935 |
| 944 | { PseudoVFREDMAX_VS_M4_E32_MASK, PseudoVFREDMAX_VS_M4_E32, 0x3, true }, // 936 |
| 945 | { PseudoVFREDMAX_VS_M4_E64_MASK, PseudoVFREDMAX_VS_M4_E64, 0x3, true }, // 937 |
| 946 | { PseudoVFREDMAX_VS_M8_E16_MASK, PseudoVFREDMAX_VS_M8_E16, 0x3, true }, // 938 |
| 947 | { PseudoVFREDMAX_VS_M8_E32_MASK, PseudoVFREDMAX_VS_M8_E32, 0x3, true }, // 939 |
| 948 | { PseudoVFREDMAX_VS_M8_E64_MASK, PseudoVFREDMAX_VS_M8_E64, 0x3, true }, // 940 |
| 949 | { PseudoVFREDMAX_VS_MF2_E16_MASK, PseudoVFREDMAX_VS_MF2_E16, 0x3, true }, // 941 |
| 950 | { PseudoVFREDMAX_VS_MF2_E32_MASK, PseudoVFREDMAX_VS_MF2_E32, 0x3, true }, // 942 |
| 951 | { PseudoVFREDMAX_VS_MF4_E16_MASK, PseudoVFREDMAX_VS_MF4_E16, 0x3, true }, // 943 |
| 952 | { PseudoVFREDMIN_VS_M1_E16_MASK, PseudoVFREDMIN_VS_M1_E16, 0x3, true }, // 944 |
| 953 | { PseudoVFREDMIN_VS_M1_E32_MASK, PseudoVFREDMIN_VS_M1_E32, 0x3, true }, // 945 |
| 954 | { PseudoVFREDMIN_VS_M1_E64_MASK, PseudoVFREDMIN_VS_M1_E64, 0x3, true }, // 946 |
| 955 | { PseudoVFREDMIN_VS_M2_E16_MASK, PseudoVFREDMIN_VS_M2_E16, 0x3, true }, // 947 |
| 956 | { PseudoVFREDMIN_VS_M2_E32_MASK, PseudoVFREDMIN_VS_M2_E32, 0x3, true }, // 948 |
| 957 | { PseudoVFREDMIN_VS_M2_E64_MASK, PseudoVFREDMIN_VS_M2_E64, 0x3, true }, // 949 |
| 958 | { PseudoVFREDMIN_VS_M4_E16_MASK, PseudoVFREDMIN_VS_M4_E16, 0x3, true }, // 950 |
| 959 | { PseudoVFREDMIN_VS_M4_E32_MASK, PseudoVFREDMIN_VS_M4_E32, 0x3, true }, // 951 |
| 960 | { PseudoVFREDMIN_VS_M4_E64_MASK, PseudoVFREDMIN_VS_M4_E64, 0x3, true }, // 952 |
| 961 | { PseudoVFREDMIN_VS_M8_E16_MASK, PseudoVFREDMIN_VS_M8_E16, 0x3, true }, // 953 |
| 962 | { PseudoVFREDMIN_VS_M8_E32_MASK, PseudoVFREDMIN_VS_M8_E32, 0x3, true }, // 954 |
| 963 | { PseudoVFREDMIN_VS_M8_E64_MASK, PseudoVFREDMIN_VS_M8_E64, 0x3, true }, // 955 |
| 964 | { PseudoVFREDMIN_VS_MF2_E16_MASK, PseudoVFREDMIN_VS_MF2_E16, 0x3, true }, // 956 |
| 965 | { PseudoVFREDMIN_VS_MF2_E32_MASK, PseudoVFREDMIN_VS_MF2_E32, 0x3, true }, // 957 |
| 966 | { PseudoVFREDMIN_VS_MF4_E16_MASK, PseudoVFREDMIN_VS_MF4_E16, 0x3, true }, // 958 |
| 967 | { PseudoVFREDOSUM_VS_M1_E16_MASK, PseudoVFREDOSUM_VS_M1_E16, 0x3, true }, // 959 |
| 968 | { PseudoVFREDOSUM_VS_M1_E32_MASK, PseudoVFREDOSUM_VS_M1_E32, 0x3, true }, // 960 |
| 969 | { PseudoVFREDOSUM_VS_M1_E64_MASK, PseudoVFREDOSUM_VS_M1_E64, 0x3, true }, // 961 |
| 970 | { PseudoVFREDOSUM_VS_M2_E16_MASK, PseudoVFREDOSUM_VS_M2_E16, 0x3, true }, // 962 |
| 971 | { PseudoVFREDOSUM_VS_M2_E32_MASK, PseudoVFREDOSUM_VS_M2_E32, 0x3, true }, // 963 |
| 972 | { PseudoVFREDOSUM_VS_M2_E64_MASK, PseudoVFREDOSUM_VS_M2_E64, 0x3, true }, // 964 |
| 973 | { PseudoVFREDOSUM_VS_M4_E16_MASK, PseudoVFREDOSUM_VS_M4_E16, 0x3, true }, // 965 |
| 974 | { PseudoVFREDOSUM_VS_M4_E32_MASK, PseudoVFREDOSUM_VS_M4_E32, 0x3, true }, // 966 |
| 975 | { PseudoVFREDOSUM_VS_M4_E64_MASK, PseudoVFREDOSUM_VS_M4_E64, 0x3, true }, // 967 |
| 976 | { PseudoVFREDOSUM_VS_M8_E16_MASK, PseudoVFREDOSUM_VS_M8_E16, 0x3, true }, // 968 |
| 977 | { PseudoVFREDOSUM_VS_M8_E32_MASK, PseudoVFREDOSUM_VS_M8_E32, 0x3, true }, // 969 |
| 978 | { PseudoVFREDOSUM_VS_M8_E64_MASK, PseudoVFREDOSUM_VS_M8_E64, 0x3, true }, // 970 |
| 979 | { PseudoVFREDOSUM_VS_MF2_E16_MASK, PseudoVFREDOSUM_VS_MF2_E16, 0x3, true }, // 971 |
| 980 | { PseudoVFREDOSUM_VS_MF2_E32_MASK, PseudoVFREDOSUM_VS_MF2_E32, 0x3, true }, // 972 |
| 981 | { PseudoVFREDOSUM_VS_MF4_E16_MASK, PseudoVFREDOSUM_VS_MF4_E16, 0x3, true }, // 973 |
| 982 | { PseudoVFREDUSUM_VS_M1_E16_MASK, PseudoVFREDUSUM_VS_M1_E16, 0x3, true }, // 974 |
| 983 | { PseudoVFREDUSUM_VS_M1_E32_MASK, PseudoVFREDUSUM_VS_M1_E32, 0x3, true }, // 975 |
| 984 | { PseudoVFREDUSUM_VS_M1_E64_MASK, PseudoVFREDUSUM_VS_M1_E64, 0x3, true }, // 976 |
| 985 | { PseudoVFREDUSUM_VS_M2_E16_MASK, PseudoVFREDUSUM_VS_M2_E16, 0x3, true }, // 977 |
| 986 | { PseudoVFREDUSUM_VS_M2_E32_MASK, PseudoVFREDUSUM_VS_M2_E32, 0x3, true }, // 978 |
| 987 | { PseudoVFREDUSUM_VS_M2_E64_MASK, PseudoVFREDUSUM_VS_M2_E64, 0x3, true }, // 979 |
| 988 | { PseudoVFREDUSUM_VS_M4_E16_MASK, PseudoVFREDUSUM_VS_M4_E16, 0x3, true }, // 980 |
| 989 | { PseudoVFREDUSUM_VS_M4_E32_MASK, PseudoVFREDUSUM_VS_M4_E32, 0x3, true }, // 981 |
| 990 | { PseudoVFREDUSUM_VS_M4_E64_MASK, PseudoVFREDUSUM_VS_M4_E64, 0x3, true }, // 982 |
| 991 | { PseudoVFREDUSUM_VS_M8_E16_MASK, PseudoVFREDUSUM_VS_M8_E16, 0x3, true }, // 983 |
| 992 | { PseudoVFREDUSUM_VS_M8_E32_MASK, PseudoVFREDUSUM_VS_M8_E32, 0x3, true }, // 984 |
| 993 | { PseudoVFREDUSUM_VS_M8_E64_MASK, PseudoVFREDUSUM_VS_M8_E64, 0x3, true }, // 985 |
| 994 | { PseudoVFREDUSUM_VS_MF2_E16_MASK, PseudoVFREDUSUM_VS_MF2_E16, 0x3, true }, // 986 |
| 995 | { PseudoVFREDUSUM_VS_MF2_E32_MASK, PseudoVFREDUSUM_VS_MF2_E32, 0x3, true }, // 987 |
| 996 | { PseudoVFREDUSUM_VS_MF4_E16_MASK, PseudoVFREDUSUM_VS_MF4_E16, 0x3, true }, // 988 |
| 997 | { PseudoVFRSQRT7_V_M1_E16_MASK, PseudoVFRSQRT7_V_M1_E16, 0x2, false }, // 989 |
| 998 | { PseudoVFRSQRT7_V_M1_E32_MASK, PseudoVFRSQRT7_V_M1_E32, 0x2, false }, // 990 |
| 999 | { PseudoVFRSQRT7_V_M1_E64_MASK, PseudoVFRSQRT7_V_M1_E64, 0x2, false }, // 991 |
| 1000 | { PseudoVFRSQRT7_V_M2_E16_MASK, PseudoVFRSQRT7_V_M2_E16, 0x2, false }, // 992 |
| 1001 | { PseudoVFRSQRT7_V_M2_E32_MASK, PseudoVFRSQRT7_V_M2_E32, 0x2, false }, // 993 |
| 1002 | { PseudoVFRSQRT7_V_M2_E64_MASK, PseudoVFRSQRT7_V_M2_E64, 0x2, false }, // 994 |
| 1003 | { PseudoVFRSQRT7_V_M4_E16_MASK, PseudoVFRSQRT7_V_M4_E16, 0x2, false }, // 995 |
| 1004 | { PseudoVFRSQRT7_V_M4_E32_MASK, PseudoVFRSQRT7_V_M4_E32, 0x2, false }, // 996 |
| 1005 | { PseudoVFRSQRT7_V_M4_E64_MASK, PseudoVFRSQRT7_V_M4_E64, 0x2, false }, // 997 |
| 1006 | { PseudoVFRSQRT7_V_M8_E16_MASK, PseudoVFRSQRT7_V_M8_E16, 0x2, false }, // 998 |
| 1007 | { PseudoVFRSQRT7_V_M8_E32_MASK, PseudoVFRSQRT7_V_M8_E32, 0x2, false }, // 999 |
| 1008 | { PseudoVFRSQRT7_V_M8_E64_MASK, PseudoVFRSQRT7_V_M8_E64, 0x2, false }, // 1000 |
| 1009 | { PseudoVFRSQRT7_V_MF2_E16_MASK, PseudoVFRSQRT7_V_MF2_E16, 0x2, false }, // 1001 |
| 1010 | { PseudoVFRSQRT7_V_MF2_E32_MASK, PseudoVFRSQRT7_V_MF2_E32, 0x2, false }, // 1002 |
| 1011 | { PseudoVFRSQRT7_V_MF4_E16_MASK, PseudoVFRSQRT7_V_MF4_E16, 0x2, false }, // 1003 |
| 1012 | { PseudoVFRSUB_VFPR16_M1_E16_MASK, PseudoVFRSUB_VFPR16_M1_E16, 0x3, false }, // 1004 |
| 1013 | { PseudoVFRSUB_VFPR16_M2_E16_MASK, PseudoVFRSUB_VFPR16_M2_E16, 0x3, false }, // 1005 |
| 1014 | { PseudoVFRSUB_VFPR16_M4_E16_MASK, PseudoVFRSUB_VFPR16_M4_E16, 0x3, false }, // 1006 |
| 1015 | { PseudoVFRSUB_VFPR16_M8_E16_MASK, PseudoVFRSUB_VFPR16_M8_E16, 0x3, false }, // 1007 |
| 1016 | { PseudoVFRSUB_VFPR16_MF2_E16_MASK, PseudoVFRSUB_VFPR16_MF2_E16, 0x3, false }, // 1008 |
| 1017 | { PseudoVFRSUB_VFPR16_MF4_E16_MASK, PseudoVFRSUB_VFPR16_MF4_E16, 0x3, false }, // 1009 |
| 1018 | { PseudoVFRSUB_VFPR32_M1_E32_MASK, PseudoVFRSUB_VFPR32_M1_E32, 0x3, false }, // 1010 |
| 1019 | { PseudoVFRSUB_VFPR32_M2_E32_MASK, PseudoVFRSUB_VFPR32_M2_E32, 0x3, false }, // 1011 |
| 1020 | { PseudoVFRSUB_VFPR32_M4_E32_MASK, PseudoVFRSUB_VFPR32_M4_E32, 0x3, false }, // 1012 |
| 1021 | { PseudoVFRSUB_VFPR32_M8_E32_MASK, PseudoVFRSUB_VFPR32_M8_E32, 0x3, false }, // 1013 |
| 1022 | { PseudoVFRSUB_VFPR32_MF2_E32_MASK, PseudoVFRSUB_VFPR32_MF2_E32, 0x3, false }, // 1014 |
| 1023 | { PseudoVFRSUB_VFPR64_M1_E64_MASK, PseudoVFRSUB_VFPR64_M1_E64, 0x3, false }, // 1015 |
| 1024 | { PseudoVFRSUB_VFPR64_M2_E64_MASK, PseudoVFRSUB_VFPR64_M2_E64, 0x3, false }, // 1016 |
| 1025 | { PseudoVFRSUB_VFPR64_M4_E64_MASK, PseudoVFRSUB_VFPR64_M4_E64, 0x3, false }, // 1017 |
| 1026 | { PseudoVFRSUB_VFPR64_M8_E64_MASK, PseudoVFRSUB_VFPR64_M8_E64, 0x3, false }, // 1018 |
| 1027 | { PseudoVFSGNJN_VFPR16_M1_E16_MASK, PseudoVFSGNJN_VFPR16_M1_E16, 0x3, false }, // 1019 |
| 1028 | { PseudoVFSGNJN_VFPR16_M2_E16_MASK, PseudoVFSGNJN_VFPR16_M2_E16, 0x3, false }, // 1020 |
| 1029 | { PseudoVFSGNJN_VFPR16_M4_E16_MASK, PseudoVFSGNJN_VFPR16_M4_E16, 0x3, false }, // 1021 |
| 1030 | { PseudoVFSGNJN_VFPR16_M8_E16_MASK, PseudoVFSGNJN_VFPR16_M8_E16, 0x3, false }, // 1022 |
| 1031 | { PseudoVFSGNJN_VFPR16_MF2_E16_MASK, PseudoVFSGNJN_VFPR16_MF2_E16, 0x3, false }, // 1023 |
| 1032 | { PseudoVFSGNJN_VFPR16_MF4_E16_MASK, PseudoVFSGNJN_VFPR16_MF4_E16, 0x3, false }, // 1024 |
| 1033 | { PseudoVFSGNJN_VFPR32_M1_E32_MASK, PseudoVFSGNJN_VFPR32_M1_E32, 0x3, false }, // 1025 |
| 1034 | { PseudoVFSGNJN_VFPR32_M2_E32_MASK, PseudoVFSGNJN_VFPR32_M2_E32, 0x3, false }, // 1026 |
| 1035 | { PseudoVFSGNJN_VFPR32_M4_E32_MASK, PseudoVFSGNJN_VFPR32_M4_E32, 0x3, false }, // 1027 |
| 1036 | { PseudoVFSGNJN_VFPR32_M8_E32_MASK, PseudoVFSGNJN_VFPR32_M8_E32, 0x3, false }, // 1028 |
| 1037 | { PseudoVFSGNJN_VFPR32_MF2_E32_MASK, PseudoVFSGNJN_VFPR32_MF2_E32, 0x3, false }, // 1029 |
| 1038 | { PseudoVFSGNJN_VFPR64_M1_E64_MASK, PseudoVFSGNJN_VFPR64_M1_E64, 0x3, false }, // 1030 |
| 1039 | { PseudoVFSGNJN_VFPR64_M2_E64_MASK, PseudoVFSGNJN_VFPR64_M2_E64, 0x3, false }, // 1031 |
| 1040 | { PseudoVFSGNJN_VFPR64_M4_E64_MASK, PseudoVFSGNJN_VFPR64_M4_E64, 0x3, false }, // 1032 |
| 1041 | { PseudoVFSGNJN_VFPR64_M8_E64_MASK, PseudoVFSGNJN_VFPR64_M8_E64, 0x3, false }, // 1033 |
| 1042 | { PseudoVFSGNJN_VV_M1_E16_MASK, PseudoVFSGNJN_VV_M1_E16, 0x3, false }, // 1034 |
| 1043 | { PseudoVFSGNJN_VV_M1_E32_MASK, PseudoVFSGNJN_VV_M1_E32, 0x3, false }, // 1035 |
| 1044 | { PseudoVFSGNJN_VV_M1_E64_MASK, PseudoVFSGNJN_VV_M1_E64, 0x3, false }, // 1036 |
| 1045 | { PseudoVFSGNJN_VV_M2_E16_MASK, PseudoVFSGNJN_VV_M2_E16, 0x3, false }, // 1037 |
| 1046 | { PseudoVFSGNJN_VV_M2_E32_MASK, PseudoVFSGNJN_VV_M2_E32, 0x3, false }, // 1038 |
| 1047 | { PseudoVFSGNJN_VV_M2_E64_MASK, PseudoVFSGNJN_VV_M2_E64, 0x3, false }, // 1039 |
| 1048 | { PseudoVFSGNJN_VV_M4_E16_MASK, PseudoVFSGNJN_VV_M4_E16, 0x3, false }, // 1040 |
| 1049 | { PseudoVFSGNJN_VV_M4_E32_MASK, PseudoVFSGNJN_VV_M4_E32, 0x3, false }, // 1041 |
| 1050 | { PseudoVFSGNJN_VV_M4_E64_MASK, PseudoVFSGNJN_VV_M4_E64, 0x3, false }, // 1042 |
| 1051 | { PseudoVFSGNJN_VV_M8_E16_MASK, PseudoVFSGNJN_VV_M8_E16, 0x3, false }, // 1043 |
| 1052 | { PseudoVFSGNJN_VV_M8_E32_MASK, PseudoVFSGNJN_VV_M8_E32, 0x3, false }, // 1044 |
| 1053 | { PseudoVFSGNJN_VV_M8_E64_MASK, PseudoVFSGNJN_VV_M8_E64, 0x3, false }, // 1045 |
| 1054 | { PseudoVFSGNJN_VV_MF2_E16_MASK, PseudoVFSGNJN_VV_MF2_E16, 0x3, false }, // 1046 |
| 1055 | { PseudoVFSGNJN_VV_MF2_E32_MASK, PseudoVFSGNJN_VV_MF2_E32, 0x3, false }, // 1047 |
| 1056 | { PseudoVFSGNJN_VV_MF4_E16_MASK, PseudoVFSGNJN_VV_MF4_E16, 0x3, false }, // 1048 |
| 1057 | { PseudoVFSGNJX_VFPR16_M1_E16_MASK, PseudoVFSGNJX_VFPR16_M1_E16, 0x3, false }, // 1049 |
| 1058 | { PseudoVFSGNJX_VFPR16_M2_E16_MASK, PseudoVFSGNJX_VFPR16_M2_E16, 0x3, false }, // 1050 |
| 1059 | { PseudoVFSGNJX_VFPR16_M4_E16_MASK, PseudoVFSGNJX_VFPR16_M4_E16, 0x3, false }, // 1051 |
| 1060 | { PseudoVFSGNJX_VFPR16_M8_E16_MASK, PseudoVFSGNJX_VFPR16_M8_E16, 0x3, false }, // 1052 |
| 1061 | { PseudoVFSGNJX_VFPR16_MF2_E16_MASK, PseudoVFSGNJX_VFPR16_MF2_E16, 0x3, false }, // 1053 |
| 1062 | { PseudoVFSGNJX_VFPR16_MF4_E16_MASK, PseudoVFSGNJX_VFPR16_MF4_E16, 0x3, false }, // 1054 |
| 1063 | { PseudoVFSGNJX_VFPR32_M1_E32_MASK, PseudoVFSGNJX_VFPR32_M1_E32, 0x3, false }, // 1055 |
| 1064 | { PseudoVFSGNJX_VFPR32_M2_E32_MASK, PseudoVFSGNJX_VFPR32_M2_E32, 0x3, false }, // 1056 |
| 1065 | { PseudoVFSGNJX_VFPR32_M4_E32_MASK, PseudoVFSGNJX_VFPR32_M4_E32, 0x3, false }, // 1057 |
| 1066 | { PseudoVFSGNJX_VFPR32_M8_E32_MASK, PseudoVFSGNJX_VFPR32_M8_E32, 0x3, false }, // 1058 |
| 1067 | { PseudoVFSGNJX_VFPR32_MF2_E32_MASK, PseudoVFSGNJX_VFPR32_MF2_E32, 0x3, false }, // 1059 |
| 1068 | { PseudoVFSGNJX_VFPR64_M1_E64_MASK, PseudoVFSGNJX_VFPR64_M1_E64, 0x3, false }, // 1060 |
| 1069 | { PseudoVFSGNJX_VFPR64_M2_E64_MASK, PseudoVFSGNJX_VFPR64_M2_E64, 0x3, false }, // 1061 |
| 1070 | { PseudoVFSGNJX_VFPR64_M4_E64_MASK, PseudoVFSGNJX_VFPR64_M4_E64, 0x3, false }, // 1062 |
| 1071 | { PseudoVFSGNJX_VFPR64_M8_E64_MASK, PseudoVFSGNJX_VFPR64_M8_E64, 0x3, false }, // 1063 |
| 1072 | { PseudoVFSGNJX_VV_M1_E16_MASK, PseudoVFSGNJX_VV_M1_E16, 0x3, false }, // 1064 |
| 1073 | { PseudoVFSGNJX_VV_M1_E32_MASK, PseudoVFSGNJX_VV_M1_E32, 0x3, false }, // 1065 |
| 1074 | { PseudoVFSGNJX_VV_M1_E64_MASK, PseudoVFSGNJX_VV_M1_E64, 0x3, false }, // 1066 |
| 1075 | { PseudoVFSGNJX_VV_M2_E16_MASK, PseudoVFSGNJX_VV_M2_E16, 0x3, false }, // 1067 |
| 1076 | { PseudoVFSGNJX_VV_M2_E32_MASK, PseudoVFSGNJX_VV_M2_E32, 0x3, false }, // 1068 |
| 1077 | { PseudoVFSGNJX_VV_M2_E64_MASK, PseudoVFSGNJX_VV_M2_E64, 0x3, false }, // 1069 |
| 1078 | { PseudoVFSGNJX_VV_M4_E16_MASK, PseudoVFSGNJX_VV_M4_E16, 0x3, false }, // 1070 |
| 1079 | { PseudoVFSGNJX_VV_M4_E32_MASK, PseudoVFSGNJX_VV_M4_E32, 0x3, false }, // 1071 |
| 1080 | { PseudoVFSGNJX_VV_M4_E64_MASK, PseudoVFSGNJX_VV_M4_E64, 0x3, false }, // 1072 |
| 1081 | { PseudoVFSGNJX_VV_M8_E16_MASK, PseudoVFSGNJX_VV_M8_E16, 0x3, false }, // 1073 |
| 1082 | { PseudoVFSGNJX_VV_M8_E32_MASK, PseudoVFSGNJX_VV_M8_E32, 0x3, false }, // 1074 |
| 1083 | { PseudoVFSGNJX_VV_M8_E64_MASK, PseudoVFSGNJX_VV_M8_E64, 0x3, false }, // 1075 |
| 1084 | { PseudoVFSGNJX_VV_MF2_E16_MASK, PseudoVFSGNJX_VV_MF2_E16, 0x3, false }, // 1076 |
| 1085 | { PseudoVFSGNJX_VV_MF2_E32_MASK, PseudoVFSGNJX_VV_MF2_E32, 0x3, false }, // 1077 |
| 1086 | { PseudoVFSGNJX_VV_MF4_E16_MASK, PseudoVFSGNJX_VV_MF4_E16, 0x3, false }, // 1078 |
| 1087 | { PseudoVFSGNJ_VFPR16_M1_E16_MASK, PseudoVFSGNJ_VFPR16_M1_E16, 0x3, false }, // 1079 |
| 1088 | { PseudoVFSGNJ_VFPR16_M2_E16_MASK, PseudoVFSGNJ_VFPR16_M2_E16, 0x3, false }, // 1080 |
| 1089 | { PseudoVFSGNJ_VFPR16_M4_E16_MASK, PseudoVFSGNJ_VFPR16_M4_E16, 0x3, false }, // 1081 |
| 1090 | { PseudoVFSGNJ_VFPR16_M8_E16_MASK, PseudoVFSGNJ_VFPR16_M8_E16, 0x3, false }, // 1082 |
| 1091 | { PseudoVFSGNJ_VFPR16_MF2_E16_MASK, PseudoVFSGNJ_VFPR16_MF2_E16, 0x3, false }, // 1083 |
| 1092 | { PseudoVFSGNJ_VFPR16_MF4_E16_MASK, PseudoVFSGNJ_VFPR16_MF4_E16, 0x3, false }, // 1084 |
| 1093 | { PseudoVFSGNJ_VFPR32_M1_E32_MASK, PseudoVFSGNJ_VFPR32_M1_E32, 0x3, false }, // 1085 |
| 1094 | { PseudoVFSGNJ_VFPR32_M2_E32_MASK, PseudoVFSGNJ_VFPR32_M2_E32, 0x3, false }, // 1086 |
| 1095 | { PseudoVFSGNJ_VFPR32_M4_E32_MASK, PseudoVFSGNJ_VFPR32_M4_E32, 0x3, false }, // 1087 |
| 1096 | { PseudoVFSGNJ_VFPR32_M8_E32_MASK, PseudoVFSGNJ_VFPR32_M8_E32, 0x3, false }, // 1088 |
| 1097 | { PseudoVFSGNJ_VFPR32_MF2_E32_MASK, PseudoVFSGNJ_VFPR32_MF2_E32, 0x3, false }, // 1089 |
| 1098 | { PseudoVFSGNJ_VFPR64_M1_E64_MASK, PseudoVFSGNJ_VFPR64_M1_E64, 0x3, false }, // 1090 |
| 1099 | { PseudoVFSGNJ_VFPR64_M2_E64_MASK, PseudoVFSGNJ_VFPR64_M2_E64, 0x3, false }, // 1091 |
| 1100 | { PseudoVFSGNJ_VFPR64_M4_E64_MASK, PseudoVFSGNJ_VFPR64_M4_E64, 0x3, false }, // 1092 |
| 1101 | { PseudoVFSGNJ_VFPR64_M8_E64_MASK, PseudoVFSGNJ_VFPR64_M8_E64, 0x3, false }, // 1093 |
| 1102 | { PseudoVFSGNJ_VV_M1_E16_MASK, PseudoVFSGNJ_VV_M1_E16, 0x3, false }, // 1094 |
| 1103 | { PseudoVFSGNJ_VV_M1_E32_MASK, PseudoVFSGNJ_VV_M1_E32, 0x3, false }, // 1095 |
| 1104 | { PseudoVFSGNJ_VV_M1_E64_MASK, PseudoVFSGNJ_VV_M1_E64, 0x3, false }, // 1096 |
| 1105 | { PseudoVFSGNJ_VV_M2_E16_MASK, PseudoVFSGNJ_VV_M2_E16, 0x3, false }, // 1097 |
| 1106 | { PseudoVFSGNJ_VV_M2_E32_MASK, PseudoVFSGNJ_VV_M2_E32, 0x3, false }, // 1098 |
| 1107 | { PseudoVFSGNJ_VV_M2_E64_MASK, PseudoVFSGNJ_VV_M2_E64, 0x3, false }, // 1099 |
| 1108 | { PseudoVFSGNJ_VV_M4_E16_MASK, PseudoVFSGNJ_VV_M4_E16, 0x3, false }, // 1100 |
| 1109 | { PseudoVFSGNJ_VV_M4_E32_MASK, PseudoVFSGNJ_VV_M4_E32, 0x3, false }, // 1101 |
| 1110 | { PseudoVFSGNJ_VV_M4_E64_MASK, PseudoVFSGNJ_VV_M4_E64, 0x3, false }, // 1102 |
| 1111 | { PseudoVFSGNJ_VV_M8_E16_MASK, PseudoVFSGNJ_VV_M8_E16, 0x3, false }, // 1103 |
| 1112 | { PseudoVFSGNJ_VV_M8_E32_MASK, PseudoVFSGNJ_VV_M8_E32, 0x3, false }, // 1104 |
| 1113 | { PseudoVFSGNJ_VV_M8_E64_MASK, PseudoVFSGNJ_VV_M8_E64, 0x3, false }, // 1105 |
| 1114 | { PseudoVFSGNJ_VV_MF2_E16_MASK, PseudoVFSGNJ_VV_MF2_E16, 0x3, false }, // 1106 |
| 1115 | { PseudoVFSGNJ_VV_MF2_E32_MASK, PseudoVFSGNJ_VV_MF2_E32, 0x3, false }, // 1107 |
| 1116 | { PseudoVFSGNJ_VV_MF4_E16_MASK, PseudoVFSGNJ_VV_MF4_E16, 0x3, false }, // 1108 |
| 1117 | { PseudoVFSLIDE1DOWN_VFPR16_M1_MASK, PseudoVFSLIDE1DOWN_VFPR16_M1, 0x3, false }, // 1109 |
| 1118 | { PseudoVFSLIDE1DOWN_VFPR16_M2_MASK, PseudoVFSLIDE1DOWN_VFPR16_M2, 0x3, false }, // 1110 |
| 1119 | { PseudoVFSLIDE1DOWN_VFPR16_M4_MASK, PseudoVFSLIDE1DOWN_VFPR16_M4, 0x3, false }, // 1111 |
| 1120 | { PseudoVFSLIDE1DOWN_VFPR16_M8_MASK, PseudoVFSLIDE1DOWN_VFPR16_M8, 0x3, false }, // 1112 |
| 1121 | { PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK, PseudoVFSLIDE1DOWN_VFPR16_MF2, 0x3, false }, // 1113 |
| 1122 | { PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK, PseudoVFSLIDE1DOWN_VFPR16_MF4, 0x3, false }, // 1114 |
| 1123 | { PseudoVFSLIDE1DOWN_VFPR32_M1_MASK, PseudoVFSLIDE1DOWN_VFPR32_M1, 0x3, false }, // 1115 |
| 1124 | { PseudoVFSLIDE1DOWN_VFPR32_M2_MASK, PseudoVFSLIDE1DOWN_VFPR32_M2, 0x3, false }, // 1116 |
| 1125 | { PseudoVFSLIDE1DOWN_VFPR32_M4_MASK, PseudoVFSLIDE1DOWN_VFPR32_M4, 0x3, false }, // 1117 |
| 1126 | { PseudoVFSLIDE1DOWN_VFPR32_M8_MASK, PseudoVFSLIDE1DOWN_VFPR32_M8, 0x3, false }, // 1118 |
| 1127 | { PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK, PseudoVFSLIDE1DOWN_VFPR32_MF2, 0x3, false }, // 1119 |
| 1128 | { PseudoVFSLIDE1DOWN_VFPR64_M1_MASK, PseudoVFSLIDE1DOWN_VFPR64_M1, 0x3, false }, // 1120 |
| 1129 | { PseudoVFSLIDE1DOWN_VFPR64_M2_MASK, PseudoVFSLIDE1DOWN_VFPR64_M2, 0x3, false }, // 1121 |
| 1130 | { PseudoVFSLIDE1DOWN_VFPR64_M4_MASK, PseudoVFSLIDE1DOWN_VFPR64_M4, 0x3, false }, // 1122 |
| 1131 | { PseudoVFSLIDE1DOWN_VFPR64_M8_MASK, PseudoVFSLIDE1DOWN_VFPR64_M8, 0x3, false }, // 1123 |
| 1132 | { PseudoVFSLIDE1UP_VFPR16_M1_MASK, PseudoVFSLIDE1UP_VFPR16_M1, 0x3, false }, // 1124 |
| 1133 | { PseudoVFSLIDE1UP_VFPR16_M2_MASK, PseudoVFSLIDE1UP_VFPR16_M2, 0x3, false }, // 1125 |
| 1134 | { PseudoVFSLIDE1UP_VFPR16_M4_MASK, PseudoVFSLIDE1UP_VFPR16_M4, 0x3, false }, // 1126 |
| 1135 | { PseudoVFSLIDE1UP_VFPR16_M8_MASK, PseudoVFSLIDE1UP_VFPR16_M8, 0x3, false }, // 1127 |
| 1136 | { PseudoVFSLIDE1UP_VFPR16_MF2_MASK, PseudoVFSLIDE1UP_VFPR16_MF2, 0x3, false }, // 1128 |
| 1137 | { PseudoVFSLIDE1UP_VFPR16_MF4_MASK, PseudoVFSLIDE1UP_VFPR16_MF4, 0x3, false }, // 1129 |
| 1138 | { PseudoVFSLIDE1UP_VFPR32_M1_MASK, PseudoVFSLIDE1UP_VFPR32_M1, 0x3, false }, // 1130 |
| 1139 | { PseudoVFSLIDE1UP_VFPR32_M2_MASK, PseudoVFSLIDE1UP_VFPR32_M2, 0x3, false }, // 1131 |
| 1140 | { PseudoVFSLIDE1UP_VFPR32_M4_MASK, PseudoVFSLIDE1UP_VFPR32_M4, 0x3, false }, // 1132 |
| 1141 | { PseudoVFSLIDE1UP_VFPR32_M8_MASK, PseudoVFSLIDE1UP_VFPR32_M8, 0x3, false }, // 1133 |
| 1142 | { PseudoVFSLIDE1UP_VFPR32_MF2_MASK, PseudoVFSLIDE1UP_VFPR32_MF2, 0x3, false }, // 1134 |
| 1143 | { PseudoVFSLIDE1UP_VFPR64_M1_MASK, PseudoVFSLIDE1UP_VFPR64_M1, 0x3, false }, // 1135 |
| 1144 | { PseudoVFSLIDE1UP_VFPR64_M2_MASK, PseudoVFSLIDE1UP_VFPR64_M2, 0x3, false }, // 1136 |
| 1145 | { PseudoVFSLIDE1UP_VFPR64_M4_MASK, PseudoVFSLIDE1UP_VFPR64_M4, 0x3, false }, // 1137 |
| 1146 | { PseudoVFSLIDE1UP_VFPR64_M8_MASK, PseudoVFSLIDE1UP_VFPR64_M8, 0x3, false }, // 1138 |
| 1147 | { PseudoVFSQRT_V_M1_E16_MASK, PseudoVFSQRT_V_M1_E16, 0x2, false }, // 1139 |
| 1148 | { PseudoVFSQRT_V_M1_E32_MASK, PseudoVFSQRT_V_M1_E32, 0x2, false }, // 1140 |
| 1149 | { PseudoVFSQRT_V_M1_E64_MASK, PseudoVFSQRT_V_M1_E64, 0x2, false }, // 1141 |
| 1150 | { PseudoVFSQRT_V_M2_E16_MASK, PseudoVFSQRT_V_M2_E16, 0x2, false }, // 1142 |
| 1151 | { PseudoVFSQRT_V_M2_E32_MASK, PseudoVFSQRT_V_M2_E32, 0x2, false }, // 1143 |
| 1152 | { PseudoVFSQRT_V_M2_E64_MASK, PseudoVFSQRT_V_M2_E64, 0x2, false }, // 1144 |
| 1153 | { PseudoVFSQRT_V_M4_E16_MASK, PseudoVFSQRT_V_M4_E16, 0x2, false }, // 1145 |
| 1154 | { PseudoVFSQRT_V_M4_E32_MASK, PseudoVFSQRT_V_M4_E32, 0x2, false }, // 1146 |
| 1155 | { PseudoVFSQRT_V_M4_E64_MASK, PseudoVFSQRT_V_M4_E64, 0x2, false }, // 1147 |
| 1156 | { PseudoVFSQRT_V_M8_E16_MASK, PseudoVFSQRT_V_M8_E16, 0x2, false }, // 1148 |
| 1157 | { PseudoVFSQRT_V_M8_E32_MASK, PseudoVFSQRT_V_M8_E32, 0x2, false }, // 1149 |
| 1158 | { PseudoVFSQRT_V_M8_E64_MASK, PseudoVFSQRT_V_M8_E64, 0x2, false }, // 1150 |
| 1159 | { PseudoVFSQRT_V_MF2_E16_MASK, PseudoVFSQRT_V_MF2_E16, 0x2, false }, // 1151 |
| 1160 | { PseudoVFSQRT_V_MF2_E32_MASK, PseudoVFSQRT_V_MF2_E32, 0x2, false }, // 1152 |
| 1161 | { PseudoVFSQRT_V_MF4_E16_MASK, PseudoVFSQRT_V_MF4_E16, 0x2, false }, // 1153 |
| 1162 | { PseudoVFSUB_VFPR16_M1_E16_MASK, PseudoVFSUB_VFPR16_M1_E16, 0x3, false }, // 1154 |
| 1163 | { PseudoVFSUB_VFPR16_M2_E16_MASK, PseudoVFSUB_VFPR16_M2_E16, 0x3, false }, // 1155 |
| 1164 | { PseudoVFSUB_VFPR16_M4_E16_MASK, PseudoVFSUB_VFPR16_M4_E16, 0x3, false }, // 1156 |
| 1165 | { PseudoVFSUB_VFPR16_M8_E16_MASK, PseudoVFSUB_VFPR16_M8_E16, 0x3, false }, // 1157 |
| 1166 | { PseudoVFSUB_VFPR16_MF2_E16_MASK, PseudoVFSUB_VFPR16_MF2_E16, 0x3, false }, // 1158 |
| 1167 | { PseudoVFSUB_VFPR16_MF4_E16_MASK, PseudoVFSUB_VFPR16_MF4_E16, 0x3, false }, // 1159 |
| 1168 | { PseudoVFSUB_VFPR32_M1_E32_MASK, PseudoVFSUB_VFPR32_M1_E32, 0x3, false }, // 1160 |
| 1169 | { PseudoVFSUB_VFPR32_M2_E32_MASK, PseudoVFSUB_VFPR32_M2_E32, 0x3, false }, // 1161 |
| 1170 | { PseudoVFSUB_VFPR32_M4_E32_MASK, PseudoVFSUB_VFPR32_M4_E32, 0x3, false }, // 1162 |
| 1171 | { PseudoVFSUB_VFPR32_M8_E32_MASK, PseudoVFSUB_VFPR32_M8_E32, 0x3, false }, // 1163 |
| 1172 | { PseudoVFSUB_VFPR32_MF2_E32_MASK, PseudoVFSUB_VFPR32_MF2_E32, 0x3, false }, // 1164 |
| 1173 | { PseudoVFSUB_VFPR64_M1_E64_MASK, PseudoVFSUB_VFPR64_M1_E64, 0x3, false }, // 1165 |
| 1174 | { PseudoVFSUB_VFPR64_M2_E64_MASK, PseudoVFSUB_VFPR64_M2_E64, 0x3, false }, // 1166 |
| 1175 | { PseudoVFSUB_VFPR64_M4_E64_MASK, PseudoVFSUB_VFPR64_M4_E64, 0x3, false }, // 1167 |
| 1176 | { PseudoVFSUB_VFPR64_M8_E64_MASK, PseudoVFSUB_VFPR64_M8_E64, 0x3, false }, // 1168 |
| 1177 | { PseudoVFSUB_VV_M1_E16_MASK, PseudoVFSUB_VV_M1_E16, 0x3, false }, // 1169 |
| 1178 | { PseudoVFSUB_VV_M1_E32_MASK, PseudoVFSUB_VV_M1_E32, 0x3, false }, // 1170 |
| 1179 | { PseudoVFSUB_VV_M1_E64_MASK, PseudoVFSUB_VV_M1_E64, 0x3, false }, // 1171 |
| 1180 | { PseudoVFSUB_VV_M2_E16_MASK, PseudoVFSUB_VV_M2_E16, 0x3, false }, // 1172 |
| 1181 | { PseudoVFSUB_VV_M2_E32_MASK, PseudoVFSUB_VV_M2_E32, 0x3, false }, // 1173 |
| 1182 | { PseudoVFSUB_VV_M2_E64_MASK, PseudoVFSUB_VV_M2_E64, 0x3, false }, // 1174 |
| 1183 | { PseudoVFSUB_VV_M4_E16_MASK, PseudoVFSUB_VV_M4_E16, 0x3, false }, // 1175 |
| 1184 | { PseudoVFSUB_VV_M4_E32_MASK, PseudoVFSUB_VV_M4_E32, 0x3, false }, // 1176 |
| 1185 | { PseudoVFSUB_VV_M4_E64_MASK, PseudoVFSUB_VV_M4_E64, 0x3, false }, // 1177 |
| 1186 | { PseudoVFSUB_VV_M8_E16_MASK, PseudoVFSUB_VV_M8_E16, 0x3, false }, // 1178 |
| 1187 | { PseudoVFSUB_VV_M8_E32_MASK, PseudoVFSUB_VV_M8_E32, 0x3, false }, // 1179 |
| 1188 | { PseudoVFSUB_VV_M8_E64_MASK, PseudoVFSUB_VV_M8_E64, 0x3, false }, // 1180 |
| 1189 | { PseudoVFSUB_VV_MF2_E16_MASK, PseudoVFSUB_VV_MF2_E16, 0x3, false }, // 1181 |
| 1190 | { PseudoVFSUB_VV_MF2_E32_MASK, PseudoVFSUB_VV_MF2_E32, 0x3, false }, // 1182 |
| 1191 | { PseudoVFSUB_VV_MF4_E16_MASK, PseudoVFSUB_VV_MF4_E16, 0x3, false }, // 1183 |
| 1192 | { PseudoVFWADD_VFPR16_M1_E16_MASK, PseudoVFWADD_VFPR16_M1_E16, 0x3, false }, // 1184 |
| 1193 | { PseudoVFWADD_VFPR16_M2_E16_MASK, PseudoVFWADD_VFPR16_M2_E16, 0x3, false }, // 1185 |
| 1194 | { PseudoVFWADD_VFPR16_M4_E16_MASK, PseudoVFWADD_VFPR16_M4_E16, 0x3, false }, // 1186 |
| 1195 | { PseudoVFWADD_VFPR16_MF2_E16_MASK, PseudoVFWADD_VFPR16_MF2_E16, 0x3, false }, // 1187 |
| 1196 | { PseudoVFWADD_VFPR16_MF4_E16_MASK, PseudoVFWADD_VFPR16_MF4_E16, 0x3, false }, // 1188 |
| 1197 | { PseudoVFWADD_VFPR32_M1_E32_MASK, PseudoVFWADD_VFPR32_M1_E32, 0x3, false }, // 1189 |
| 1198 | { PseudoVFWADD_VFPR32_M2_E32_MASK, PseudoVFWADD_VFPR32_M2_E32, 0x3, false }, // 1190 |
| 1199 | { PseudoVFWADD_VFPR32_M4_E32_MASK, PseudoVFWADD_VFPR32_M4_E32, 0x3, false }, // 1191 |
| 1200 | { PseudoVFWADD_VFPR32_MF2_E32_MASK, PseudoVFWADD_VFPR32_MF2_E32, 0x3, false }, // 1192 |
| 1201 | { PseudoVFWADD_VV_M1_E16_MASK, PseudoVFWADD_VV_M1_E16, 0x3, false }, // 1193 |
| 1202 | { PseudoVFWADD_VV_M1_E32_MASK, PseudoVFWADD_VV_M1_E32, 0x3, false }, // 1194 |
| 1203 | { PseudoVFWADD_VV_M2_E16_MASK, PseudoVFWADD_VV_M2_E16, 0x3, false }, // 1195 |
| 1204 | { PseudoVFWADD_VV_M2_E32_MASK, PseudoVFWADD_VV_M2_E32, 0x3, false }, // 1196 |
| 1205 | { PseudoVFWADD_VV_M4_E16_MASK, PseudoVFWADD_VV_M4_E16, 0x3, false }, // 1197 |
| 1206 | { PseudoVFWADD_VV_M4_E32_MASK, PseudoVFWADD_VV_M4_E32, 0x3, false }, // 1198 |
| 1207 | { PseudoVFWADD_VV_MF2_E16_MASK, PseudoVFWADD_VV_MF2_E16, 0x3, false }, // 1199 |
| 1208 | { PseudoVFWADD_VV_MF2_E32_MASK, PseudoVFWADD_VV_MF2_E32, 0x3, false }, // 1200 |
| 1209 | { PseudoVFWADD_VV_MF4_E16_MASK, PseudoVFWADD_VV_MF4_E16, 0x3, false }, // 1201 |
| 1210 | { PseudoVFWADD_WFPR16_M1_E16_MASK, PseudoVFWADD_WFPR16_M1_E16, 0x3, false }, // 1202 |
| 1211 | { PseudoVFWADD_WFPR16_M2_E16_MASK, PseudoVFWADD_WFPR16_M2_E16, 0x3, false }, // 1203 |
| 1212 | { PseudoVFWADD_WFPR16_M4_E16_MASK, PseudoVFWADD_WFPR16_M4_E16, 0x3, false }, // 1204 |
| 1213 | { PseudoVFWADD_WFPR16_MF2_E16_MASK, PseudoVFWADD_WFPR16_MF2_E16, 0x3, false }, // 1205 |
| 1214 | { PseudoVFWADD_WFPR16_MF4_E16_MASK, PseudoVFWADD_WFPR16_MF4_E16, 0x3, false }, // 1206 |
| 1215 | { PseudoVFWADD_WFPR32_M1_E32_MASK, PseudoVFWADD_WFPR32_M1_E32, 0x3, false }, // 1207 |
| 1216 | { PseudoVFWADD_WFPR32_M2_E32_MASK, PseudoVFWADD_WFPR32_M2_E32, 0x3, false }, // 1208 |
| 1217 | { PseudoVFWADD_WFPR32_M4_E32_MASK, PseudoVFWADD_WFPR32_M4_E32, 0x3, false }, // 1209 |
| 1218 | { PseudoVFWADD_WFPR32_MF2_E32_MASK, PseudoVFWADD_WFPR32_MF2_E32, 0x3, false }, // 1210 |
| 1219 | { PseudoVFWADD_WV_M1_E16_MASK, PseudoVFWADD_WV_M1_E16, 0x3, false }, // 1211 |
| 1220 | { PseudoVFWADD_WV_M1_E16_MASK_TIED, PseudoVFWADD_WV_M1_E16_TIED, 0x2, false }, // 1212 |
| 1221 | { PseudoVFWADD_WV_M1_E32_MASK, PseudoVFWADD_WV_M1_E32, 0x3, false }, // 1213 |
| 1222 | { PseudoVFWADD_WV_M1_E32_MASK_TIED, PseudoVFWADD_WV_M1_E32_TIED, 0x2, false }, // 1214 |
| 1223 | { PseudoVFWADD_WV_M2_E16_MASK, PseudoVFWADD_WV_M2_E16, 0x3, false }, // 1215 |
| 1224 | { PseudoVFWADD_WV_M2_E16_MASK_TIED, PseudoVFWADD_WV_M2_E16_TIED, 0x2, false }, // 1216 |
| 1225 | { PseudoVFWADD_WV_M2_E32_MASK, PseudoVFWADD_WV_M2_E32, 0x3, false }, // 1217 |
| 1226 | { PseudoVFWADD_WV_M2_E32_MASK_TIED, PseudoVFWADD_WV_M2_E32_TIED, 0x2, false }, // 1218 |
| 1227 | { PseudoVFWADD_WV_M4_E16_MASK, PseudoVFWADD_WV_M4_E16, 0x3, false }, // 1219 |
| 1228 | { PseudoVFWADD_WV_M4_E16_MASK_TIED, PseudoVFWADD_WV_M4_E16_TIED, 0x2, false }, // 1220 |
| 1229 | { PseudoVFWADD_WV_M4_E32_MASK, PseudoVFWADD_WV_M4_E32, 0x3, false }, // 1221 |
| 1230 | { PseudoVFWADD_WV_M4_E32_MASK_TIED, PseudoVFWADD_WV_M4_E32_TIED, 0x2, false }, // 1222 |
| 1231 | { PseudoVFWADD_WV_MF2_E16_MASK, PseudoVFWADD_WV_MF2_E16, 0x3, false }, // 1223 |
| 1232 | { PseudoVFWADD_WV_MF2_E16_MASK_TIED, PseudoVFWADD_WV_MF2_E16_TIED, 0x2, false }, // 1224 |
| 1233 | { PseudoVFWADD_WV_MF2_E32_MASK, PseudoVFWADD_WV_MF2_E32, 0x3, false }, // 1225 |
| 1234 | { PseudoVFWADD_WV_MF2_E32_MASK_TIED, PseudoVFWADD_WV_MF2_E32_TIED, 0x2, false }, // 1226 |
| 1235 | { PseudoVFWADD_WV_MF4_E16_MASK, PseudoVFWADD_WV_MF4_E16, 0x3, false }, // 1227 |
| 1236 | { PseudoVFWADD_WV_MF4_E16_MASK_TIED, PseudoVFWADD_WV_MF4_E16_TIED, 0x2, false }, // 1228 |
| 1237 | { PseudoVFWCVTBF16_F_F_V_M1_E16_MASK, PseudoVFWCVTBF16_F_F_V_M1_E16, 0x2, false }, // 1229 |
| 1238 | { PseudoVFWCVTBF16_F_F_V_M1_E32_MASK, PseudoVFWCVTBF16_F_F_V_M1_E32, 0x2, false }, // 1230 |
| 1239 | { PseudoVFWCVTBF16_F_F_V_M2_E16_MASK, PseudoVFWCVTBF16_F_F_V_M2_E16, 0x2, false }, // 1231 |
| 1240 | { PseudoVFWCVTBF16_F_F_V_M2_E32_MASK, PseudoVFWCVTBF16_F_F_V_M2_E32, 0x2, false }, // 1232 |
| 1241 | { PseudoVFWCVTBF16_F_F_V_M4_E16_MASK, PseudoVFWCVTBF16_F_F_V_M4_E16, 0x2, false }, // 1233 |
| 1242 | { PseudoVFWCVTBF16_F_F_V_M4_E32_MASK, PseudoVFWCVTBF16_F_F_V_M4_E32, 0x2, false }, // 1234 |
| 1243 | { PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK, PseudoVFWCVTBF16_F_F_V_MF2_E16, 0x2, false }, // 1235 |
| 1244 | { PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK, PseudoVFWCVTBF16_F_F_V_MF2_E32, 0x2, false }, // 1236 |
| 1245 | { PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK, PseudoVFWCVTBF16_F_F_V_MF4_E16, 0x2, false }, // 1237 |
| 1246 | { PseudoVFWCVT_F_F_V_M1_E16_MASK, PseudoVFWCVT_F_F_V_M1_E16, 0x2, false }, // 1238 |
| 1247 | { PseudoVFWCVT_F_F_V_M1_E32_MASK, PseudoVFWCVT_F_F_V_M1_E32, 0x2, false }, // 1239 |
| 1248 | { PseudoVFWCVT_F_F_V_M2_E16_MASK, PseudoVFWCVT_F_F_V_M2_E16, 0x2, false }, // 1240 |
| 1249 | { PseudoVFWCVT_F_F_V_M2_E32_MASK, PseudoVFWCVT_F_F_V_M2_E32, 0x2, false }, // 1241 |
| 1250 | { PseudoVFWCVT_F_F_V_M4_E16_MASK, PseudoVFWCVT_F_F_V_M4_E16, 0x2, false }, // 1242 |
| 1251 | { PseudoVFWCVT_F_F_V_M4_E32_MASK, PseudoVFWCVT_F_F_V_M4_E32, 0x2, false }, // 1243 |
| 1252 | { PseudoVFWCVT_F_F_V_MF2_E16_MASK, PseudoVFWCVT_F_F_V_MF2_E16, 0x2, false }, // 1244 |
| 1253 | { PseudoVFWCVT_F_F_V_MF2_E32_MASK, PseudoVFWCVT_F_F_V_MF2_E32, 0x2, false }, // 1245 |
| 1254 | { PseudoVFWCVT_F_F_V_MF4_E16_MASK, PseudoVFWCVT_F_F_V_MF4_E16, 0x2, false }, // 1246 |
| 1255 | { PseudoVFWCVT_F_XU_V_M1_E16_MASK, PseudoVFWCVT_F_XU_V_M1_E16, 0x2, false }, // 1247 |
| 1256 | { PseudoVFWCVT_F_XU_V_M1_E32_MASK, PseudoVFWCVT_F_XU_V_M1_E32, 0x2, false }, // 1248 |
| 1257 | { PseudoVFWCVT_F_XU_V_M1_E8_MASK, PseudoVFWCVT_F_XU_V_M1_E8, 0x2, false }, // 1249 |
| 1258 | { PseudoVFWCVT_F_XU_V_M2_E16_MASK, PseudoVFWCVT_F_XU_V_M2_E16, 0x2, false }, // 1250 |
| 1259 | { PseudoVFWCVT_F_XU_V_M2_E32_MASK, PseudoVFWCVT_F_XU_V_M2_E32, 0x2, false }, // 1251 |
| 1260 | { PseudoVFWCVT_F_XU_V_M2_E8_MASK, PseudoVFWCVT_F_XU_V_M2_E8, 0x2, false }, // 1252 |
| 1261 | { PseudoVFWCVT_F_XU_V_M4_E16_MASK, PseudoVFWCVT_F_XU_V_M4_E16, 0x2, false }, // 1253 |
| 1262 | { PseudoVFWCVT_F_XU_V_M4_E32_MASK, PseudoVFWCVT_F_XU_V_M4_E32, 0x2, false }, // 1254 |
| 1263 | { PseudoVFWCVT_F_XU_V_M4_E8_MASK, PseudoVFWCVT_F_XU_V_M4_E8, 0x2, false }, // 1255 |
| 1264 | { PseudoVFWCVT_F_XU_V_MF2_E16_MASK, PseudoVFWCVT_F_XU_V_MF2_E16, 0x2, false }, // 1256 |
| 1265 | { PseudoVFWCVT_F_XU_V_MF2_E32_MASK, PseudoVFWCVT_F_XU_V_MF2_E32, 0x2, false }, // 1257 |
| 1266 | { PseudoVFWCVT_F_XU_V_MF2_E8_MASK, PseudoVFWCVT_F_XU_V_MF2_E8, 0x2, false }, // 1258 |
| 1267 | { PseudoVFWCVT_F_XU_V_MF4_E16_MASK, PseudoVFWCVT_F_XU_V_MF4_E16, 0x2, false }, // 1259 |
| 1268 | { PseudoVFWCVT_F_XU_V_MF4_E8_MASK, PseudoVFWCVT_F_XU_V_MF4_E8, 0x2, false }, // 1260 |
| 1269 | { PseudoVFWCVT_F_XU_V_MF8_E8_MASK, PseudoVFWCVT_F_XU_V_MF8_E8, 0x2, false }, // 1261 |
| 1270 | { PseudoVFWCVT_F_X_V_M1_E16_MASK, PseudoVFWCVT_F_X_V_M1_E16, 0x2, false }, // 1262 |
| 1271 | { PseudoVFWCVT_F_X_V_M1_E32_MASK, PseudoVFWCVT_F_X_V_M1_E32, 0x2, false }, // 1263 |
| 1272 | { PseudoVFWCVT_F_X_V_M1_E8_MASK, PseudoVFWCVT_F_X_V_M1_E8, 0x2, false }, // 1264 |
| 1273 | { PseudoVFWCVT_F_X_V_M2_E16_MASK, PseudoVFWCVT_F_X_V_M2_E16, 0x2, false }, // 1265 |
| 1274 | { PseudoVFWCVT_F_X_V_M2_E32_MASK, PseudoVFWCVT_F_X_V_M2_E32, 0x2, false }, // 1266 |
| 1275 | { PseudoVFWCVT_F_X_V_M2_E8_MASK, PseudoVFWCVT_F_X_V_M2_E8, 0x2, false }, // 1267 |
| 1276 | { PseudoVFWCVT_F_X_V_M4_E16_MASK, PseudoVFWCVT_F_X_V_M4_E16, 0x2, false }, // 1268 |
| 1277 | { PseudoVFWCVT_F_X_V_M4_E32_MASK, PseudoVFWCVT_F_X_V_M4_E32, 0x2, false }, // 1269 |
| 1278 | { PseudoVFWCVT_F_X_V_M4_E8_MASK, PseudoVFWCVT_F_X_V_M4_E8, 0x2, false }, // 1270 |
| 1279 | { PseudoVFWCVT_F_X_V_MF2_E16_MASK, PseudoVFWCVT_F_X_V_MF2_E16, 0x2, false }, // 1271 |
| 1280 | { PseudoVFWCVT_F_X_V_MF2_E32_MASK, PseudoVFWCVT_F_X_V_MF2_E32, 0x2, false }, // 1272 |
| 1281 | { PseudoVFWCVT_F_X_V_MF2_E8_MASK, PseudoVFWCVT_F_X_V_MF2_E8, 0x2, false }, // 1273 |
| 1282 | { PseudoVFWCVT_F_X_V_MF4_E16_MASK, PseudoVFWCVT_F_X_V_MF4_E16, 0x2, false }, // 1274 |
| 1283 | { PseudoVFWCVT_F_X_V_MF4_E8_MASK, PseudoVFWCVT_F_X_V_MF4_E8, 0x2, false }, // 1275 |
| 1284 | { PseudoVFWCVT_F_X_V_MF8_E8_MASK, PseudoVFWCVT_F_X_V_MF8_E8, 0x2, false }, // 1276 |
| 1285 | { PseudoVFWCVT_RM_XU_F_V_M1_MASK, PseudoVFWCVT_RM_XU_F_V_M1, 0x2, false }, // 1277 |
| 1286 | { PseudoVFWCVT_RM_XU_F_V_M2_MASK, PseudoVFWCVT_RM_XU_F_V_M2, 0x2, false }, // 1278 |
| 1287 | { PseudoVFWCVT_RM_XU_F_V_M4_MASK, PseudoVFWCVT_RM_XU_F_V_M4, 0x2, false }, // 1279 |
| 1288 | { PseudoVFWCVT_RM_XU_F_V_MF2_MASK, PseudoVFWCVT_RM_XU_F_V_MF2, 0x2, false }, // 1280 |
| 1289 | { PseudoVFWCVT_RM_XU_F_V_MF4_MASK, PseudoVFWCVT_RM_XU_F_V_MF4, 0x2, false }, // 1281 |
| 1290 | { PseudoVFWCVT_RM_X_F_V_M1_MASK, PseudoVFWCVT_RM_X_F_V_M1, 0x2, false }, // 1282 |
| 1291 | { PseudoVFWCVT_RM_X_F_V_M2_MASK, PseudoVFWCVT_RM_X_F_V_M2, 0x2, false }, // 1283 |
| 1292 | { PseudoVFWCVT_RM_X_F_V_M4_MASK, PseudoVFWCVT_RM_X_F_V_M4, 0x2, false }, // 1284 |
| 1293 | { PseudoVFWCVT_RM_X_F_V_MF2_MASK, PseudoVFWCVT_RM_X_F_V_MF2, 0x2, false }, // 1285 |
| 1294 | { PseudoVFWCVT_RM_X_F_V_MF4_MASK, PseudoVFWCVT_RM_X_F_V_MF4, 0x2, false }, // 1286 |
| 1295 | { PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, PseudoVFWCVT_RTZ_XU_F_V_M1, 0x2, false }, // 1287 |
| 1296 | { PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, PseudoVFWCVT_RTZ_XU_F_V_M2, 0x2, false }, // 1288 |
| 1297 | { PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, PseudoVFWCVT_RTZ_XU_F_V_M4, 0x2, false }, // 1289 |
| 1298 | { PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, PseudoVFWCVT_RTZ_XU_F_V_MF2, 0x2, false }, // 1290 |
| 1299 | { PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, PseudoVFWCVT_RTZ_XU_F_V_MF4, 0x2, false }, // 1291 |
| 1300 | { PseudoVFWCVT_RTZ_X_F_V_M1_MASK, PseudoVFWCVT_RTZ_X_F_V_M1, 0x2, false }, // 1292 |
| 1301 | { PseudoVFWCVT_RTZ_X_F_V_M2_MASK, PseudoVFWCVT_RTZ_X_F_V_M2, 0x2, false }, // 1293 |
| 1302 | { PseudoVFWCVT_RTZ_X_F_V_M4_MASK, PseudoVFWCVT_RTZ_X_F_V_M4, 0x2, false }, // 1294 |
| 1303 | { PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, PseudoVFWCVT_RTZ_X_F_V_MF2, 0x2, false }, // 1295 |
| 1304 | { PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, PseudoVFWCVT_RTZ_X_F_V_MF4, 0x2, false }, // 1296 |
| 1305 | { PseudoVFWCVT_XU_F_V_M1_MASK, PseudoVFWCVT_XU_F_V_M1, 0x2, false }, // 1297 |
| 1306 | { PseudoVFWCVT_XU_F_V_M2_MASK, PseudoVFWCVT_XU_F_V_M2, 0x2, false }, // 1298 |
| 1307 | { PseudoVFWCVT_XU_F_V_M4_MASK, PseudoVFWCVT_XU_F_V_M4, 0x2, false }, // 1299 |
| 1308 | { PseudoVFWCVT_XU_F_V_MF2_MASK, PseudoVFWCVT_XU_F_V_MF2, 0x2, false }, // 1300 |
| 1309 | { PseudoVFWCVT_XU_F_V_MF4_MASK, PseudoVFWCVT_XU_F_V_MF4, 0x2, false }, // 1301 |
| 1310 | { PseudoVFWCVT_X_F_V_M1_MASK, PseudoVFWCVT_X_F_V_M1, 0x2, false }, // 1302 |
| 1311 | { PseudoVFWCVT_X_F_V_M2_MASK, PseudoVFWCVT_X_F_V_M2, 0x2, false }, // 1303 |
| 1312 | { PseudoVFWCVT_X_F_V_M4_MASK, PseudoVFWCVT_X_F_V_M4, 0x2, false }, // 1304 |
| 1313 | { PseudoVFWCVT_X_F_V_MF2_MASK, PseudoVFWCVT_X_F_V_MF2, 0x2, false }, // 1305 |
| 1314 | { PseudoVFWCVT_X_F_V_MF4_MASK, PseudoVFWCVT_X_F_V_MF4, 0x2, false }, // 1306 |
| 1315 | { PseudoVFWMACCBF16_VFPR16_M1_E16_MASK, PseudoVFWMACCBF16_VFPR16_M1_E16, 0x3, false }, // 1307 |
| 1316 | { PseudoVFWMACCBF16_VFPR16_M2_E16_MASK, PseudoVFWMACCBF16_VFPR16_M2_E16, 0x3, false }, // 1308 |
| 1317 | { PseudoVFWMACCBF16_VFPR16_M4_E16_MASK, PseudoVFWMACCBF16_VFPR16_M4_E16, 0x3, false }, // 1309 |
| 1318 | { PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK, PseudoVFWMACCBF16_VFPR16_MF2_E16, 0x3, false }, // 1310 |
| 1319 | { PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK, PseudoVFWMACCBF16_VFPR16_MF4_E16, 0x3, false }, // 1311 |
| 1320 | { PseudoVFWMACCBF16_VV_M1_E16_MASK, PseudoVFWMACCBF16_VV_M1_E16, 0x3, false }, // 1312 |
| 1321 | { PseudoVFWMACCBF16_VV_M1_E32_MASK, PseudoVFWMACCBF16_VV_M1_E32, 0x3, false }, // 1313 |
| 1322 | { PseudoVFWMACCBF16_VV_M2_E16_MASK, PseudoVFWMACCBF16_VV_M2_E16, 0x3, false }, // 1314 |
| 1323 | { PseudoVFWMACCBF16_VV_M2_E32_MASK, PseudoVFWMACCBF16_VV_M2_E32, 0x3, false }, // 1315 |
| 1324 | { PseudoVFWMACCBF16_VV_M4_E16_MASK, PseudoVFWMACCBF16_VV_M4_E16, 0x3, false }, // 1316 |
| 1325 | { PseudoVFWMACCBF16_VV_M4_E32_MASK, PseudoVFWMACCBF16_VV_M4_E32, 0x3, false }, // 1317 |
| 1326 | { PseudoVFWMACCBF16_VV_MF2_E16_MASK, PseudoVFWMACCBF16_VV_MF2_E16, 0x3, false }, // 1318 |
| 1327 | { PseudoVFWMACCBF16_VV_MF2_E32_MASK, PseudoVFWMACCBF16_VV_MF2_E32, 0x3, false }, // 1319 |
| 1328 | { PseudoVFWMACCBF16_VV_MF4_E16_MASK, PseudoVFWMACCBF16_VV_MF4_E16, 0x3, false }, // 1320 |
| 1329 | { PseudoVFWMACC_VFPR16_M1_E16_MASK, PseudoVFWMACC_VFPR16_M1_E16, 0x3, false }, // 1321 |
| 1330 | { PseudoVFWMACC_VFPR16_M2_E16_MASK, PseudoVFWMACC_VFPR16_M2_E16, 0x3, false }, // 1322 |
| 1331 | { PseudoVFWMACC_VFPR16_M4_E16_MASK, PseudoVFWMACC_VFPR16_M4_E16, 0x3, false }, // 1323 |
| 1332 | { PseudoVFWMACC_VFPR16_MF2_E16_MASK, PseudoVFWMACC_VFPR16_MF2_E16, 0x3, false }, // 1324 |
| 1333 | { PseudoVFWMACC_VFPR16_MF4_E16_MASK, PseudoVFWMACC_VFPR16_MF4_E16, 0x3, false }, // 1325 |
| 1334 | { PseudoVFWMACC_VFPR32_M1_E32_MASK, PseudoVFWMACC_VFPR32_M1_E32, 0x3, false }, // 1326 |
| 1335 | { PseudoVFWMACC_VFPR32_M2_E32_MASK, PseudoVFWMACC_VFPR32_M2_E32, 0x3, false }, // 1327 |
| 1336 | { PseudoVFWMACC_VFPR32_M4_E32_MASK, PseudoVFWMACC_VFPR32_M4_E32, 0x3, false }, // 1328 |
| 1337 | { PseudoVFWMACC_VFPR32_MF2_E32_MASK, PseudoVFWMACC_VFPR32_MF2_E32, 0x3, false }, // 1329 |
| 1338 | { PseudoVFWMACC_VV_M1_E16_MASK, PseudoVFWMACC_VV_M1_E16, 0x3, false }, // 1330 |
| 1339 | { PseudoVFWMACC_VV_M1_E32_MASK, PseudoVFWMACC_VV_M1_E32, 0x3, false }, // 1331 |
| 1340 | { PseudoVFWMACC_VV_M2_E16_MASK, PseudoVFWMACC_VV_M2_E16, 0x3, false }, // 1332 |
| 1341 | { PseudoVFWMACC_VV_M2_E32_MASK, PseudoVFWMACC_VV_M2_E32, 0x3, false }, // 1333 |
| 1342 | { PseudoVFWMACC_VV_M4_E16_MASK, PseudoVFWMACC_VV_M4_E16, 0x3, false }, // 1334 |
| 1343 | { PseudoVFWMACC_VV_M4_E32_MASK, PseudoVFWMACC_VV_M4_E32, 0x3, false }, // 1335 |
| 1344 | { PseudoVFWMACC_VV_MF2_E16_MASK, PseudoVFWMACC_VV_MF2_E16, 0x3, false }, // 1336 |
| 1345 | { PseudoVFWMACC_VV_MF2_E32_MASK, PseudoVFWMACC_VV_MF2_E32, 0x3, false }, // 1337 |
| 1346 | { PseudoVFWMACC_VV_MF4_E16_MASK, PseudoVFWMACC_VV_MF4_E16, 0x3, false }, // 1338 |
| 1347 | { PseudoVFWMSAC_VFPR16_M1_E16_MASK, PseudoVFWMSAC_VFPR16_M1_E16, 0x3, false }, // 1339 |
| 1348 | { PseudoVFWMSAC_VFPR16_M2_E16_MASK, PseudoVFWMSAC_VFPR16_M2_E16, 0x3, false }, // 1340 |
| 1349 | { PseudoVFWMSAC_VFPR16_M4_E16_MASK, PseudoVFWMSAC_VFPR16_M4_E16, 0x3, false }, // 1341 |
| 1350 | { PseudoVFWMSAC_VFPR16_MF2_E16_MASK, PseudoVFWMSAC_VFPR16_MF2_E16, 0x3, false }, // 1342 |
| 1351 | { PseudoVFWMSAC_VFPR16_MF4_E16_MASK, PseudoVFWMSAC_VFPR16_MF4_E16, 0x3, false }, // 1343 |
| 1352 | { PseudoVFWMSAC_VFPR32_M1_E32_MASK, PseudoVFWMSAC_VFPR32_M1_E32, 0x3, false }, // 1344 |
| 1353 | { PseudoVFWMSAC_VFPR32_M2_E32_MASK, PseudoVFWMSAC_VFPR32_M2_E32, 0x3, false }, // 1345 |
| 1354 | { PseudoVFWMSAC_VFPR32_M4_E32_MASK, PseudoVFWMSAC_VFPR32_M4_E32, 0x3, false }, // 1346 |
| 1355 | { PseudoVFWMSAC_VFPR32_MF2_E32_MASK, PseudoVFWMSAC_VFPR32_MF2_E32, 0x3, false }, // 1347 |
| 1356 | { PseudoVFWMSAC_VV_M1_E16_MASK, PseudoVFWMSAC_VV_M1_E16, 0x3, false }, // 1348 |
| 1357 | { PseudoVFWMSAC_VV_M1_E32_MASK, PseudoVFWMSAC_VV_M1_E32, 0x3, false }, // 1349 |
| 1358 | { PseudoVFWMSAC_VV_M2_E16_MASK, PseudoVFWMSAC_VV_M2_E16, 0x3, false }, // 1350 |
| 1359 | { PseudoVFWMSAC_VV_M2_E32_MASK, PseudoVFWMSAC_VV_M2_E32, 0x3, false }, // 1351 |
| 1360 | { PseudoVFWMSAC_VV_M4_E16_MASK, PseudoVFWMSAC_VV_M4_E16, 0x3, false }, // 1352 |
| 1361 | { PseudoVFWMSAC_VV_M4_E32_MASK, PseudoVFWMSAC_VV_M4_E32, 0x3, false }, // 1353 |
| 1362 | { PseudoVFWMSAC_VV_MF2_E16_MASK, PseudoVFWMSAC_VV_MF2_E16, 0x3, false }, // 1354 |
| 1363 | { PseudoVFWMSAC_VV_MF2_E32_MASK, PseudoVFWMSAC_VV_MF2_E32, 0x3, false }, // 1355 |
| 1364 | { PseudoVFWMSAC_VV_MF4_E16_MASK, PseudoVFWMSAC_VV_MF4_E16, 0x3, false }, // 1356 |
| 1365 | { PseudoVFWMUL_VFPR16_M1_E16_MASK, PseudoVFWMUL_VFPR16_M1_E16, 0x3, false }, // 1357 |
| 1366 | { PseudoVFWMUL_VFPR16_M2_E16_MASK, PseudoVFWMUL_VFPR16_M2_E16, 0x3, false }, // 1358 |
| 1367 | { PseudoVFWMUL_VFPR16_M4_E16_MASK, PseudoVFWMUL_VFPR16_M4_E16, 0x3, false }, // 1359 |
| 1368 | { PseudoVFWMUL_VFPR16_MF2_E16_MASK, PseudoVFWMUL_VFPR16_MF2_E16, 0x3, false }, // 1360 |
| 1369 | { PseudoVFWMUL_VFPR16_MF4_E16_MASK, PseudoVFWMUL_VFPR16_MF4_E16, 0x3, false }, // 1361 |
| 1370 | { PseudoVFWMUL_VFPR32_M1_E32_MASK, PseudoVFWMUL_VFPR32_M1_E32, 0x3, false }, // 1362 |
| 1371 | { PseudoVFWMUL_VFPR32_M2_E32_MASK, PseudoVFWMUL_VFPR32_M2_E32, 0x3, false }, // 1363 |
| 1372 | { PseudoVFWMUL_VFPR32_M4_E32_MASK, PseudoVFWMUL_VFPR32_M4_E32, 0x3, false }, // 1364 |
| 1373 | { PseudoVFWMUL_VFPR32_MF2_E32_MASK, PseudoVFWMUL_VFPR32_MF2_E32, 0x3, false }, // 1365 |
| 1374 | { PseudoVFWMUL_VV_M1_E16_MASK, PseudoVFWMUL_VV_M1_E16, 0x3, false }, // 1366 |
| 1375 | { PseudoVFWMUL_VV_M1_E32_MASK, PseudoVFWMUL_VV_M1_E32, 0x3, false }, // 1367 |
| 1376 | { PseudoVFWMUL_VV_M2_E16_MASK, PseudoVFWMUL_VV_M2_E16, 0x3, false }, // 1368 |
| 1377 | { PseudoVFWMUL_VV_M2_E32_MASK, PseudoVFWMUL_VV_M2_E32, 0x3, false }, // 1369 |
| 1378 | { PseudoVFWMUL_VV_M4_E16_MASK, PseudoVFWMUL_VV_M4_E16, 0x3, false }, // 1370 |
| 1379 | { PseudoVFWMUL_VV_M4_E32_MASK, PseudoVFWMUL_VV_M4_E32, 0x3, false }, // 1371 |
| 1380 | { PseudoVFWMUL_VV_MF2_E16_MASK, PseudoVFWMUL_VV_MF2_E16, 0x3, false }, // 1372 |
| 1381 | { PseudoVFWMUL_VV_MF2_E32_MASK, PseudoVFWMUL_VV_MF2_E32, 0x3, false }, // 1373 |
| 1382 | { PseudoVFWMUL_VV_MF4_E16_MASK, PseudoVFWMUL_VV_MF4_E16, 0x3, false }, // 1374 |
| 1383 | { PseudoVFWNMACC_VFPR16_M1_E16_MASK, PseudoVFWNMACC_VFPR16_M1_E16, 0x3, false }, // 1375 |
| 1384 | { PseudoVFWNMACC_VFPR16_M2_E16_MASK, PseudoVFWNMACC_VFPR16_M2_E16, 0x3, false }, // 1376 |
| 1385 | { PseudoVFWNMACC_VFPR16_M4_E16_MASK, PseudoVFWNMACC_VFPR16_M4_E16, 0x3, false }, // 1377 |
| 1386 | { PseudoVFWNMACC_VFPR16_MF2_E16_MASK, PseudoVFWNMACC_VFPR16_MF2_E16, 0x3, false }, // 1378 |
| 1387 | { PseudoVFWNMACC_VFPR16_MF4_E16_MASK, PseudoVFWNMACC_VFPR16_MF4_E16, 0x3, false }, // 1379 |
| 1388 | { PseudoVFWNMACC_VFPR32_M1_E32_MASK, PseudoVFWNMACC_VFPR32_M1_E32, 0x3, false }, // 1380 |
| 1389 | { PseudoVFWNMACC_VFPR32_M2_E32_MASK, PseudoVFWNMACC_VFPR32_M2_E32, 0x3, false }, // 1381 |
| 1390 | { PseudoVFWNMACC_VFPR32_M4_E32_MASK, PseudoVFWNMACC_VFPR32_M4_E32, 0x3, false }, // 1382 |
| 1391 | { PseudoVFWNMACC_VFPR32_MF2_E32_MASK, PseudoVFWNMACC_VFPR32_MF2_E32, 0x3, false }, // 1383 |
| 1392 | { PseudoVFWNMACC_VV_M1_E16_MASK, PseudoVFWNMACC_VV_M1_E16, 0x3, false }, // 1384 |
| 1393 | { PseudoVFWNMACC_VV_M1_E32_MASK, PseudoVFWNMACC_VV_M1_E32, 0x3, false }, // 1385 |
| 1394 | { PseudoVFWNMACC_VV_M2_E16_MASK, PseudoVFWNMACC_VV_M2_E16, 0x3, false }, // 1386 |
| 1395 | { PseudoVFWNMACC_VV_M2_E32_MASK, PseudoVFWNMACC_VV_M2_E32, 0x3, false }, // 1387 |
| 1396 | { PseudoVFWNMACC_VV_M4_E16_MASK, PseudoVFWNMACC_VV_M4_E16, 0x3, false }, // 1388 |
| 1397 | { PseudoVFWNMACC_VV_M4_E32_MASK, PseudoVFWNMACC_VV_M4_E32, 0x3, false }, // 1389 |
| 1398 | { PseudoVFWNMACC_VV_MF2_E16_MASK, PseudoVFWNMACC_VV_MF2_E16, 0x3, false }, // 1390 |
| 1399 | { PseudoVFWNMACC_VV_MF2_E32_MASK, PseudoVFWNMACC_VV_MF2_E32, 0x3, false }, // 1391 |
| 1400 | { PseudoVFWNMACC_VV_MF4_E16_MASK, PseudoVFWNMACC_VV_MF4_E16, 0x3, false }, // 1392 |
| 1401 | { PseudoVFWNMSAC_VFPR16_M1_E16_MASK, PseudoVFWNMSAC_VFPR16_M1_E16, 0x3, false }, // 1393 |
| 1402 | { PseudoVFWNMSAC_VFPR16_M2_E16_MASK, PseudoVFWNMSAC_VFPR16_M2_E16, 0x3, false }, // 1394 |
| 1403 | { PseudoVFWNMSAC_VFPR16_M4_E16_MASK, PseudoVFWNMSAC_VFPR16_M4_E16, 0x3, false }, // 1395 |
| 1404 | { PseudoVFWNMSAC_VFPR16_MF2_E16_MASK, PseudoVFWNMSAC_VFPR16_MF2_E16, 0x3, false }, // 1396 |
| 1405 | { PseudoVFWNMSAC_VFPR16_MF4_E16_MASK, PseudoVFWNMSAC_VFPR16_MF4_E16, 0x3, false }, // 1397 |
| 1406 | { PseudoVFWNMSAC_VFPR32_M1_E32_MASK, PseudoVFWNMSAC_VFPR32_M1_E32, 0x3, false }, // 1398 |
| 1407 | { PseudoVFWNMSAC_VFPR32_M2_E32_MASK, PseudoVFWNMSAC_VFPR32_M2_E32, 0x3, false }, // 1399 |
| 1408 | { PseudoVFWNMSAC_VFPR32_M4_E32_MASK, PseudoVFWNMSAC_VFPR32_M4_E32, 0x3, false }, // 1400 |
| 1409 | { PseudoVFWNMSAC_VFPR32_MF2_E32_MASK, PseudoVFWNMSAC_VFPR32_MF2_E32, 0x3, false }, // 1401 |
| 1410 | { PseudoVFWNMSAC_VV_M1_E16_MASK, PseudoVFWNMSAC_VV_M1_E16, 0x3, false }, // 1402 |
| 1411 | { PseudoVFWNMSAC_VV_M1_E32_MASK, PseudoVFWNMSAC_VV_M1_E32, 0x3, false }, // 1403 |
| 1412 | { PseudoVFWNMSAC_VV_M2_E16_MASK, PseudoVFWNMSAC_VV_M2_E16, 0x3, false }, // 1404 |
| 1413 | { PseudoVFWNMSAC_VV_M2_E32_MASK, PseudoVFWNMSAC_VV_M2_E32, 0x3, false }, // 1405 |
| 1414 | { PseudoVFWNMSAC_VV_M4_E16_MASK, PseudoVFWNMSAC_VV_M4_E16, 0x3, false }, // 1406 |
| 1415 | { PseudoVFWNMSAC_VV_M4_E32_MASK, PseudoVFWNMSAC_VV_M4_E32, 0x3, false }, // 1407 |
| 1416 | { PseudoVFWNMSAC_VV_MF2_E16_MASK, PseudoVFWNMSAC_VV_MF2_E16, 0x3, false }, // 1408 |
| 1417 | { PseudoVFWNMSAC_VV_MF2_E32_MASK, PseudoVFWNMSAC_VV_MF2_E32, 0x3, false }, // 1409 |
| 1418 | { PseudoVFWNMSAC_VV_MF4_E16_MASK, PseudoVFWNMSAC_VV_MF4_E16, 0x3, false }, // 1410 |
| 1419 | { PseudoVFWREDOSUM_VS_M1_E16_MASK, PseudoVFWREDOSUM_VS_M1_E16, 0x3, true }, // 1411 |
| 1420 | { PseudoVFWREDOSUM_VS_M1_E32_MASK, PseudoVFWREDOSUM_VS_M1_E32, 0x3, true }, // 1412 |
| 1421 | { PseudoVFWREDOSUM_VS_M2_E16_MASK, PseudoVFWREDOSUM_VS_M2_E16, 0x3, true }, // 1413 |
| 1422 | { PseudoVFWREDOSUM_VS_M2_E32_MASK, PseudoVFWREDOSUM_VS_M2_E32, 0x3, true }, // 1414 |
| 1423 | { PseudoVFWREDOSUM_VS_M4_E16_MASK, PseudoVFWREDOSUM_VS_M4_E16, 0x3, true }, // 1415 |
| 1424 | { PseudoVFWREDOSUM_VS_M4_E32_MASK, PseudoVFWREDOSUM_VS_M4_E32, 0x3, true }, // 1416 |
| 1425 | { PseudoVFWREDOSUM_VS_M8_E16_MASK, PseudoVFWREDOSUM_VS_M8_E16, 0x3, true }, // 1417 |
| 1426 | { PseudoVFWREDOSUM_VS_M8_E32_MASK, PseudoVFWREDOSUM_VS_M8_E32, 0x3, true }, // 1418 |
| 1427 | { PseudoVFWREDOSUM_VS_MF2_E16_MASK, PseudoVFWREDOSUM_VS_MF2_E16, 0x3, true }, // 1419 |
| 1428 | { PseudoVFWREDOSUM_VS_MF2_E32_MASK, PseudoVFWREDOSUM_VS_MF2_E32, 0x3, true }, // 1420 |
| 1429 | { PseudoVFWREDOSUM_VS_MF4_E16_MASK, PseudoVFWREDOSUM_VS_MF4_E16, 0x3, true }, // 1421 |
| 1430 | { PseudoVFWREDUSUM_VS_M1_E16_MASK, PseudoVFWREDUSUM_VS_M1_E16, 0x3, true }, // 1422 |
| 1431 | { PseudoVFWREDUSUM_VS_M1_E32_MASK, PseudoVFWREDUSUM_VS_M1_E32, 0x3, true }, // 1423 |
| 1432 | { PseudoVFWREDUSUM_VS_M2_E16_MASK, PseudoVFWREDUSUM_VS_M2_E16, 0x3, true }, // 1424 |
| 1433 | { PseudoVFWREDUSUM_VS_M2_E32_MASK, PseudoVFWREDUSUM_VS_M2_E32, 0x3, true }, // 1425 |
| 1434 | { PseudoVFWREDUSUM_VS_M4_E16_MASK, PseudoVFWREDUSUM_VS_M4_E16, 0x3, true }, // 1426 |
| 1435 | { PseudoVFWREDUSUM_VS_M4_E32_MASK, PseudoVFWREDUSUM_VS_M4_E32, 0x3, true }, // 1427 |
| 1436 | { PseudoVFWREDUSUM_VS_M8_E16_MASK, PseudoVFWREDUSUM_VS_M8_E16, 0x3, true }, // 1428 |
| 1437 | { PseudoVFWREDUSUM_VS_M8_E32_MASK, PseudoVFWREDUSUM_VS_M8_E32, 0x3, true }, // 1429 |
| 1438 | { PseudoVFWREDUSUM_VS_MF2_E16_MASK, PseudoVFWREDUSUM_VS_MF2_E16, 0x3, true }, // 1430 |
| 1439 | { PseudoVFWREDUSUM_VS_MF2_E32_MASK, PseudoVFWREDUSUM_VS_MF2_E32, 0x3, true }, // 1431 |
| 1440 | { PseudoVFWREDUSUM_VS_MF4_E16_MASK, PseudoVFWREDUSUM_VS_MF4_E16, 0x3, true }, // 1432 |
| 1441 | { PseudoVFWSUB_VFPR16_M1_E16_MASK, PseudoVFWSUB_VFPR16_M1_E16, 0x3, false }, // 1433 |
| 1442 | { PseudoVFWSUB_VFPR16_M2_E16_MASK, PseudoVFWSUB_VFPR16_M2_E16, 0x3, false }, // 1434 |
| 1443 | { PseudoVFWSUB_VFPR16_M4_E16_MASK, PseudoVFWSUB_VFPR16_M4_E16, 0x3, false }, // 1435 |
| 1444 | { PseudoVFWSUB_VFPR16_MF2_E16_MASK, PseudoVFWSUB_VFPR16_MF2_E16, 0x3, false }, // 1436 |
| 1445 | { PseudoVFWSUB_VFPR16_MF4_E16_MASK, PseudoVFWSUB_VFPR16_MF4_E16, 0x3, false }, // 1437 |
| 1446 | { PseudoVFWSUB_VFPR32_M1_E32_MASK, PseudoVFWSUB_VFPR32_M1_E32, 0x3, false }, // 1438 |
| 1447 | { PseudoVFWSUB_VFPR32_M2_E32_MASK, PseudoVFWSUB_VFPR32_M2_E32, 0x3, false }, // 1439 |
| 1448 | { PseudoVFWSUB_VFPR32_M4_E32_MASK, PseudoVFWSUB_VFPR32_M4_E32, 0x3, false }, // 1440 |
| 1449 | { PseudoVFWSUB_VFPR32_MF2_E32_MASK, PseudoVFWSUB_VFPR32_MF2_E32, 0x3, false }, // 1441 |
| 1450 | { PseudoVFWSUB_VV_M1_E16_MASK, PseudoVFWSUB_VV_M1_E16, 0x3, false }, // 1442 |
| 1451 | { PseudoVFWSUB_VV_M1_E32_MASK, PseudoVFWSUB_VV_M1_E32, 0x3, false }, // 1443 |
| 1452 | { PseudoVFWSUB_VV_M2_E16_MASK, PseudoVFWSUB_VV_M2_E16, 0x3, false }, // 1444 |
| 1453 | { PseudoVFWSUB_VV_M2_E32_MASK, PseudoVFWSUB_VV_M2_E32, 0x3, false }, // 1445 |
| 1454 | { PseudoVFWSUB_VV_M4_E16_MASK, PseudoVFWSUB_VV_M4_E16, 0x3, false }, // 1446 |
| 1455 | { PseudoVFWSUB_VV_M4_E32_MASK, PseudoVFWSUB_VV_M4_E32, 0x3, false }, // 1447 |
| 1456 | { PseudoVFWSUB_VV_MF2_E16_MASK, PseudoVFWSUB_VV_MF2_E16, 0x3, false }, // 1448 |
| 1457 | { PseudoVFWSUB_VV_MF2_E32_MASK, PseudoVFWSUB_VV_MF2_E32, 0x3, false }, // 1449 |
| 1458 | { PseudoVFWSUB_VV_MF4_E16_MASK, PseudoVFWSUB_VV_MF4_E16, 0x3, false }, // 1450 |
| 1459 | { PseudoVFWSUB_WFPR16_M1_E16_MASK, PseudoVFWSUB_WFPR16_M1_E16, 0x3, false }, // 1451 |
| 1460 | { PseudoVFWSUB_WFPR16_M2_E16_MASK, PseudoVFWSUB_WFPR16_M2_E16, 0x3, false }, // 1452 |
| 1461 | { PseudoVFWSUB_WFPR16_M4_E16_MASK, PseudoVFWSUB_WFPR16_M4_E16, 0x3, false }, // 1453 |
| 1462 | { PseudoVFWSUB_WFPR16_MF2_E16_MASK, PseudoVFWSUB_WFPR16_MF2_E16, 0x3, false }, // 1454 |
| 1463 | { PseudoVFWSUB_WFPR16_MF4_E16_MASK, PseudoVFWSUB_WFPR16_MF4_E16, 0x3, false }, // 1455 |
| 1464 | { PseudoVFWSUB_WFPR32_M1_E32_MASK, PseudoVFWSUB_WFPR32_M1_E32, 0x3, false }, // 1456 |
| 1465 | { PseudoVFWSUB_WFPR32_M2_E32_MASK, PseudoVFWSUB_WFPR32_M2_E32, 0x3, false }, // 1457 |
| 1466 | { PseudoVFWSUB_WFPR32_M4_E32_MASK, PseudoVFWSUB_WFPR32_M4_E32, 0x3, false }, // 1458 |
| 1467 | { PseudoVFWSUB_WFPR32_MF2_E32_MASK, PseudoVFWSUB_WFPR32_MF2_E32, 0x3, false }, // 1459 |
| 1468 | { PseudoVFWSUB_WV_M1_E16_MASK, PseudoVFWSUB_WV_M1_E16, 0x3, false }, // 1460 |
| 1469 | { PseudoVFWSUB_WV_M1_E16_MASK_TIED, PseudoVFWSUB_WV_M1_E16_TIED, 0x2, false }, // 1461 |
| 1470 | { PseudoVFWSUB_WV_M1_E32_MASK, PseudoVFWSUB_WV_M1_E32, 0x3, false }, // 1462 |
| 1471 | { PseudoVFWSUB_WV_M1_E32_MASK_TIED, PseudoVFWSUB_WV_M1_E32_TIED, 0x2, false }, // 1463 |
| 1472 | { PseudoVFWSUB_WV_M2_E16_MASK, PseudoVFWSUB_WV_M2_E16, 0x3, false }, // 1464 |
| 1473 | { PseudoVFWSUB_WV_M2_E16_MASK_TIED, PseudoVFWSUB_WV_M2_E16_TIED, 0x2, false }, // 1465 |
| 1474 | { PseudoVFWSUB_WV_M2_E32_MASK, PseudoVFWSUB_WV_M2_E32, 0x3, false }, // 1466 |
| 1475 | { PseudoVFWSUB_WV_M2_E32_MASK_TIED, PseudoVFWSUB_WV_M2_E32_TIED, 0x2, false }, // 1467 |
| 1476 | { PseudoVFWSUB_WV_M4_E16_MASK, PseudoVFWSUB_WV_M4_E16, 0x3, false }, // 1468 |
| 1477 | { PseudoVFWSUB_WV_M4_E16_MASK_TIED, PseudoVFWSUB_WV_M4_E16_TIED, 0x2, false }, // 1469 |
| 1478 | { PseudoVFWSUB_WV_M4_E32_MASK, PseudoVFWSUB_WV_M4_E32, 0x3, false }, // 1470 |
| 1479 | { PseudoVFWSUB_WV_M4_E32_MASK_TIED, PseudoVFWSUB_WV_M4_E32_TIED, 0x2, false }, // 1471 |
| 1480 | { PseudoVFWSUB_WV_MF2_E16_MASK, PseudoVFWSUB_WV_MF2_E16, 0x3, false }, // 1472 |
| 1481 | { PseudoVFWSUB_WV_MF2_E16_MASK_TIED, PseudoVFWSUB_WV_MF2_E16_TIED, 0x2, false }, // 1473 |
| 1482 | { PseudoVFWSUB_WV_MF2_E32_MASK, PseudoVFWSUB_WV_MF2_E32, 0x3, false }, // 1474 |
| 1483 | { PseudoVFWSUB_WV_MF2_E32_MASK_TIED, PseudoVFWSUB_WV_MF2_E32_TIED, 0x2, false }, // 1475 |
| 1484 | { PseudoVFWSUB_WV_MF4_E16_MASK, PseudoVFWSUB_WV_MF4_E16, 0x3, false }, // 1476 |
| 1485 | { PseudoVFWSUB_WV_MF4_E16_MASK_TIED, PseudoVFWSUB_WV_MF4_E16_TIED, 0x2, false }, // 1477 |
| 1486 | { PseudoVID_V_M1_MASK, PseudoVID_V_M1, 0x1, false }, // 1478 |
| 1487 | { PseudoVID_V_M2_MASK, PseudoVID_V_M2, 0x1, false }, // 1479 |
| 1488 | { PseudoVID_V_M4_MASK, PseudoVID_V_M4, 0x1, false }, // 1480 |
| 1489 | { PseudoVID_V_M8_MASK, PseudoVID_V_M8, 0x1, false }, // 1481 |
| 1490 | { PseudoVID_V_MF2_MASK, PseudoVID_V_MF2, 0x1, false }, // 1482 |
| 1491 | { PseudoVID_V_MF4_MASK, PseudoVID_V_MF4, 0x1, false }, // 1483 |
| 1492 | { PseudoVID_V_MF8_MASK, PseudoVID_V_MF8, 0x1, false }, // 1484 |
| 1493 | { PseudoVIOTA_M_M1_MASK, PseudoVIOTA_M_M1, 0x2, true }, // 1485 |
| 1494 | { PseudoVIOTA_M_M2_MASK, PseudoVIOTA_M_M2, 0x2, true }, // 1486 |
| 1495 | { PseudoVIOTA_M_M4_MASK, PseudoVIOTA_M_M4, 0x2, true }, // 1487 |
| 1496 | { PseudoVIOTA_M_M8_MASK, PseudoVIOTA_M_M8, 0x2, true }, // 1488 |
| 1497 | { PseudoVIOTA_M_MF2_MASK, PseudoVIOTA_M_MF2, 0x2, true }, // 1489 |
| 1498 | { PseudoVIOTA_M_MF4_MASK, PseudoVIOTA_M_MF4, 0x2, true }, // 1490 |
| 1499 | { PseudoVIOTA_M_MF8_MASK, PseudoVIOTA_M_MF8, 0x2, true }, // 1491 |
| 1500 | { PseudoVLE16FF_V_M1_MASK, PseudoVLE16FF_V_M1, 0x2, false }, // 1492 |
| 1501 | { PseudoVLE16FF_V_M2_MASK, PseudoVLE16FF_V_M2, 0x2, false }, // 1493 |
| 1502 | { PseudoVLE16FF_V_M4_MASK, PseudoVLE16FF_V_M4, 0x2, false }, // 1494 |
| 1503 | { PseudoVLE16FF_V_M8_MASK, PseudoVLE16FF_V_M8, 0x2, false }, // 1495 |
| 1504 | { PseudoVLE16FF_V_MF2_MASK, PseudoVLE16FF_V_MF2, 0x2, false }, // 1496 |
| 1505 | { PseudoVLE16FF_V_MF4_MASK, PseudoVLE16FF_V_MF4, 0x2, false }, // 1497 |
| 1506 | { PseudoVLE16_V_M1_MASK, PseudoVLE16_V_M1, 0x2, false }, // 1498 |
| 1507 | { PseudoVLE16_V_M2_MASK, PseudoVLE16_V_M2, 0x2, false }, // 1499 |
| 1508 | { PseudoVLE16_V_M4_MASK, PseudoVLE16_V_M4, 0x2, false }, // 1500 |
| 1509 | { PseudoVLE16_V_M8_MASK, PseudoVLE16_V_M8, 0x2, false }, // 1501 |
| 1510 | { PseudoVLE16_V_MF2_MASK, PseudoVLE16_V_MF2, 0x2, false }, // 1502 |
| 1511 | { PseudoVLE16_V_MF4_MASK, PseudoVLE16_V_MF4, 0x2, false }, // 1503 |
| 1512 | { PseudoVLE32FF_V_M1_MASK, PseudoVLE32FF_V_M1, 0x2, false }, // 1504 |
| 1513 | { PseudoVLE32FF_V_M2_MASK, PseudoVLE32FF_V_M2, 0x2, false }, // 1505 |
| 1514 | { PseudoVLE32FF_V_M4_MASK, PseudoVLE32FF_V_M4, 0x2, false }, // 1506 |
| 1515 | { PseudoVLE32FF_V_M8_MASK, PseudoVLE32FF_V_M8, 0x2, false }, // 1507 |
| 1516 | { PseudoVLE32FF_V_MF2_MASK, PseudoVLE32FF_V_MF2, 0x2, false }, // 1508 |
| 1517 | { PseudoVLE32_V_M1_MASK, PseudoVLE32_V_M1, 0x2, false }, // 1509 |
| 1518 | { PseudoVLE32_V_M2_MASK, PseudoVLE32_V_M2, 0x2, false }, // 1510 |
| 1519 | { PseudoVLE32_V_M4_MASK, PseudoVLE32_V_M4, 0x2, false }, // 1511 |
| 1520 | { PseudoVLE32_V_M8_MASK, PseudoVLE32_V_M8, 0x2, false }, // 1512 |
| 1521 | { PseudoVLE32_V_MF2_MASK, PseudoVLE32_V_MF2, 0x2, false }, // 1513 |
| 1522 | { PseudoVLE64FF_V_M1_MASK, PseudoVLE64FF_V_M1, 0x2, false }, // 1514 |
| 1523 | { PseudoVLE64FF_V_M2_MASK, PseudoVLE64FF_V_M2, 0x2, false }, // 1515 |
| 1524 | { PseudoVLE64FF_V_M4_MASK, PseudoVLE64FF_V_M4, 0x2, false }, // 1516 |
| 1525 | { PseudoVLE64FF_V_M8_MASK, PseudoVLE64FF_V_M8, 0x2, false }, // 1517 |
| 1526 | { PseudoVLE64_V_M1_MASK, PseudoVLE64_V_M1, 0x2, false }, // 1518 |
| 1527 | { PseudoVLE64_V_M2_MASK, PseudoVLE64_V_M2, 0x2, false }, // 1519 |
| 1528 | { PseudoVLE64_V_M4_MASK, PseudoVLE64_V_M4, 0x2, false }, // 1520 |
| 1529 | { PseudoVLE64_V_M8_MASK, PseudoVLE64_V_M8, 0x2, false }, // 1521 |
| 1530 | { PseudoVLE8FF_V_M1_MASK, PseudoVLE8FF_V_M1, 0x2, false }, // 1522 |
| 1531 | { PseudoVLE8FF_V_M2_MASK, PseudoVLE8FF_V_M2, 0x2, false }, // 1523 |
| 1532 | { PseudoVLE8FF_V_M4_MASK, PseudoVLE8FF_V_M4, 0x2, false }, // 1524 |
| 1533 | { PseudoVLE8FF_V_M8_MASK, PseudoVLE8FF_V_M8, 0x2, false }, // 1525 |
| 1534 | { PseudoVLE8FF_V_MF2_MASK, PseudoVLE8FF_V_MF2, 0x2, false }, // 1526 |
| 1535 | { PseudoVLE8FF_V_MF4_MASK, PseudoVLE8FF_V_MF4, 0x2, false }, // 1527 |
| 1536 | { PseudoVLE8FF_V_MF8_MASK, PseudoVLE8FF_V_MF8, 0x2, false }, // 1528 |
| 1537 | { PseudoVLE8_V_M1_MASK, PseudoVLE8_V_M1, 0x2, false }, // 1529 |
| 1538 | { PseudoVLE8_V_M2_MASK, PseudoVLE8_V_M2, 0x2, false }, // 1530 |
| 1539 | { PseudoVLE8_V_M4_MASK, PseudoVLE8_V_M4, 0x2, false }, // 1531 |
| 1540 | { PseudoVLE8_V_M8_MASK, PseudoVLE8_V_M8, 0x2, false }, // 1532 |
| 1541 | { PseudoVLE8_V_MF2_MASK, PseudoVLE8_V_MF2, 0x2, false }, // 1533 |
| 1542 | { PseudoVLE8_V_MF4_MASK, PseudoVLE8_V_MF4, 0x2, false }, // 1534 |
| 1543 | { PseudoVLE8_V_MF8_MASK, PseudoVLE8_V_MF8, 0x2, false }, // 1535 |
| 1544 | { PseudoVLOXEI16_V_M1_M1_MASK, PseudoVLOXEI16_V_M1_M1, 0x3, false }, // 1536 |
| 1545 | { PseudoVLOXEI16_V_M1_M2_MASK, PseudoVLOXEI16_V_M1_M2, 0x3, false }, // 1537 |
| 1546 | { PseudoVLOXEI16_V_M1_M4_MASK, PseudoVLOXEI16_V_M1_M4, 0x3, false }, // 1538 |
| 1547 | { PseudoVLOXEI16_V_M1_MF2_MASK, PseudoVLOXEI16_V_M1_MF2, 0x3, false }, // 1539 |
| 1548 | { PseudoVLOXEI16_V_M2_M1_MASK, PseudoVLOXEI16_V_M2_M1, 0x3, false }, // 1540 |
| 1549 | { PseudoVLOXEI16_V_M2_M2_MASK, PseudoVLOXEI16_V_M2_M2, 0x3, false }, // 1541 |
| 1550 | { PseudoVLOXEI16_V_M2_M4_MASK, PseudoVLOXEI16_V_M2_M4, 0x3, false }, // 1542 |
| 1551 | { PseudoVLOXEI16_V_M2_M8_MASK, PseudoVLOXEI16_V_M2_M8, 0x3, false }, // 1543 |
| 1552 | { PseudoVLOXEI16_V_M4_M2_MASK, PseudoVLOXEI16_V_M4_M2, 0x3, false }, // 1544 |
| 1553 | { PseudoVLOXEI16_V_M4_M4_MASK, PseudoVLOXEI16_V_M4_M4, 0x3, false }, // 1545 |
| 1554 | { PseudoVLOXEI16_V_M4_M8_MASK, PseudoVLOXEI16_V_M4_M8, 0x3, false }, // 1546 |
| 1555 | { PseudoVLOXEI16_V_M8_M4_MASK, PseudoVLOXEI16_V_M8_M4, 0x3, false }, // 1547 |
| 1556 | { PseudoVLOXEI16_V_M8_M8_MASK, PseudoVLOXEI16_V_M8_M8, 0x3, false }, // 1548 |
| 1557 | { PseudoVLOXEI16_V_MF2_M1_MASK, PseudoVLOXEI16_V_MF2_M1, 0x3, false }, // 1549 |
| 1558 | { PseudoVLOXEI16_V_MF2_M2_MASK, PseudoVLOXEI16_V_MF2_M2, 0x3, false }, // 1550 |
| 1559 | { PseudoVLOXEI16_V_MF2_MF2_MASK, PseudoVLOXEI16_V_MF2_MF2, 0x3, false }, // 1551 |
| 1560 | { PseudoVLOXEI16_V_MF2_MF4_MASK, PseudoVLOXEI16_V_MF2_MF4, 0x3, false }, // 1552 |
| 1561 | { PseudoVLOXEI16_V_MF4_M1_MASK, PseudoVLOXEI16_V_MF4_M1, 0x3, false }, // 1553 |
| 1562 | { PseudoVLOXEI16_V_MF4_MF2_MASK, PseudoVLOXEI16_V_MF4_MF2, 0x3, false }, // 1554 |
| 1563 | { PseudoVLOXEI16_V_MF4_MF4_MASK, PseudoVLOXEI16_V_MF4_MF4, 0x3, false }, // 1555 |
| 1564 | { PseudoVLOXEI16_V_MF4_MF8_MASK, PseudoVLOXEI16_V_MF4_MF8, 0x3, false }, // 1556 |
| 1565 | { PseudoVLOXEI32_V_M1_M1_MASK, PseudoVLOXEI32_V_M1_M1, 0x3, false }, // 1557 |
| 1566 | { PseudoVLOXEI32_V_M1_M2_MASK, PseudoVLOXEI32_V_M1_M2, 0x3, false }, // 1558 |
| 1567 | { PseudoVLOXEI32_V_M1_MF2_MASK, PseudoVLOXEI32_V_M1_MF2, 0x3, false }, // 1559 |
| 1568 | { PseudoVLOXEI32_V_M1_MF4_MASK, PseudoVLOXEI32_V_M1_MF4, 0x3, false }, // 1560 |
| 1569 | { PseudoVLOXEI32_V_M2_M1_MASK, PseudoVLOXEI32_V_M2_M1, 0x3, false }, // 1561 |
| 1570 | { PseudoVLOXEI32_V_M2_M2_MASK, PseudoVLOXEI32_V_M2_M2, 0x3, false }, // 1562 |
| 1571 | { PseudoVLOXEI32_V_M2_M4_MASK, PseudoVLOXEI32_V_M2_M4, 0x3, false }, // 1563 |
| 1572 | { PseudoVLOXEI32_V_M2_MF2_MASK, PseudoVLOXEI32_V_M2_MF2, 0x3, false }, // 1564 |
| 1573 | { PseudoVLOXEI32_V_M4_M1_MASK, PseudoVLOXEI32_V_M4_M1, 0x3, false }, // 1565 |
| 1574 | { PseudoVLOXEI32_V_M4_M2_MASK, PseudoVLOXEI32_V_M4_M2, 0x3, false }, // 1566 |
| 1575 | { PseudoVLOXEI32_V_M4_M4_MASK, PseudoVLOXEI32_V_M4_M4, 0x3, false }, // 1567 |
| 1576 | { PseudoVLOXEI32_V_M4_M8_MASK, PseudoVLOXEI32_V_M4_M8, 0x3, false }, // 1568 |
| 1577 | { PseudoVLOXEI32_V_M8_M2_MASK, PseudoVLOXEI32_V_M8_M2, 0x3, false }, // 1569 |
| 1578 | { PseudoVLOXEI32_V_M8_M4_MASK, PseudoVLOXEI32_V_M8_M4, 0x3, false }, // 1570 |
| 1579 | { PseudoVLOXEI32_V_M8_M8_MASK, PseudoVLOXEI32_V_M8_M8, 0x3, false }, // 1571 |
| 1580 | { PseudoVLOXEI32_V_MF2_M1_MASK, PseudoVLOXEI32_V_MF2_M1, 0x3, false }, // 1572 |
| 1581 | { PseudoVLOXEI32_V_MF2_MF2_MASK, PseudoVLOXEI32_V_MF2_MF2, 0x3, false }, // 1573 |
| 1582 | { PseudoVLOXEI32_V_MF2_MF4_MASK, PseudoVLOXEI32_V_MF2_MF4, 0x3, false }, // 1574 |
| 1583 | { PseudoVLOXEI32_V_MF2_MF8_MASK, PseudoVLOXEI32_V_MF2_MF8, 0x3, false }, // 1575 |
| 1584 | { PseudoVLOXEI64_V_M1_M1_MASK, PseudoVLOXEI64_V_M1_M1, 0x3, false }, // 1576 |
| 1585 | { PseudoVLOXEI64_V_M1_MF2_MASK, PseudoVLOXEI64_V_M1_MF2, 0x3, false }, // 1577 |
| 1586 | { PseudoVLOXEI64_V_M1_MF4_MASK, PseudoVLOXEI64_V_M1_MF4, 0x3, false }, // 1578 |
| 1587 | { PseudoVLOXEI64_V_M1_MF8_MASK, PseudoVLOXEI64_V_M1_MF8, 0x3, false }, // 1579 |
| 1588 | { PseudoVLOXEI64_V_M2_M1_MASK, PseudoVLOXEI64_V_M2_M1, 0x3, false }, // 1580 |
| 1589 | { PseudoVLOXEI64_V_M2_M2_MASK, PseudoVLOXEI64_V_M2_M2, 0x3, false }, // 1581 |
| 1590 | { PseudoVLOXEI64_V_M2_MF2_MASK, PseudoVLOXEI64_V_M2_MF2, 0x3, false }, // 1582 |
| 1591 | { PseudoVLOXEI64_V_M2_MF4_MASK, PseudoVLOXEI64_V_M2_MF4, 0x3, false }, // 1583 |
| 1592 | { PseudoVLOXEI64_V_M4_M1_MASK, PseudoVLOXEI64_V_M4_M1, 0x3, false }, // 1584 |
| 1593 | { PseudoVLOXEI64_V_M4_M2_MASK, PseudoVLOXEI64_V_M4_M2, 0x3, false }, // 1585 |
| 1594 | { PseudoVLOXEI64_V_M4_M4_MASK, PseudoVLOXEI64_V_M4_M4, 0x3, false }, // 1586 |
| 1595 | { PseudoVLOXEI64_V_M4_MF2_MASK, PseudoVLOXEI64_V_M4_MF2, 0x3, false }, // 1587 |
| 1596 | { PseudoVLOXEI64_V_M8_M1_MASK, PseudoVLOXEI64_V_M8_M1, 0x3, false }, // 1588 |
| 1597 | { PseudoVLOXEI64_V_M8_M2_MASK, PseudoVLOXEI64_V_M8_M2, 0x3, false }, // 1589 |
| 1598 | { PseudoVLOXEI64_V_M8_M4_MASK, PseudoVLOXEI64_V_M8_M4, 0x3, false }, // 1590 |
| 1599 | { PseudoVLOXEI64_V_M8_M8_MASK, PseudoVLOXEI64_V_M8_M8, 0x3, false }, // 1591 |
| 1600 | { PseudoVLOXEI8_V_M1_M1_MASK, PseudoVLOXEI8_V_M1_M1, 0x3, false }, // 1592 |
| 1601 | { PseudoVLOXEI8_V_M1_M2_MASK, PseudoVLOXEI8_V_M1_M2, 0x3, false }, // 1593 |
| 1602 | { PseudoVLOXEI8_V_M1_M4_MASK, PseudoVLOXEI8_V_M1_M4, 0x3, false }, // 1594 |
| 1603 | { PseudoVLOXEI8_V_M1_M8_MASK, PseudoVLOXEI8_V_M1_M8, 0x3, false }, // 1595 |
| 1604 | { PseudoVLOXEI8_V_M2_M2_MASK, PseudoVLOXEI8_V_M2_M2, 0x3, false }, // 1596 |
| 1605 | { PseudoVLOXEI8_V_M2_M4_MASK, PseudoVLOXEI8_V_M2_M4, 0x3, false }, // 1597 |
| 1606 | { PseudoVLOXEI8_V_M2_M8_MASK, PseudoVLOXEI8_V_M2_M8, 0x3, false }, // 1598 |
| 1607 | { PseudoVLOXEI8_V_M4_M4_MASK, PseudoVLOXEI8_V_M4_M4, 0x3, false }, // 1599 |
| 1608 | { PseudoVLOXEI8_V_M4_M8_MASK, PseudoVLOXEI8_V_M4_M8, 0x3, false }, // 1600 |
| 1609 | { PseudoVLOXEI8_V_M8_M8_MASK, PseudoVLOXEI8_V_M8_M8, 0x3, false }, // 1601 |
| 1610 | { PseudoVLOXEI8_V_MF2_M1_MASK, PseudoVLOXEI8_V_MF2_M1, 0x3, false }, // 1602 |
| 1611 | { PseudoVLOXEI8_V_MF2_M2_MASK, PseudoVLOXEI8_V_MF2_M2, 0x3, false }, // 1603 |
| 1612 | { PseudoVLOXEI8_V_MF2_M4_MASK, PseudoVLOXEI8_V_MF2_M4, 0x3, false }, // 1604 |
| 1613 | { PseudoVLOXEI8_V_MF2_MF2_MASK, PseudoVLOXEI8_V_MF2_MF2, 0x3, false }, // 1605 |
| 1614 | { PseudoVLOXEI8_V_MF4_M1_MASK, PseudoVLOXEI8_V_MF4_M1, 0x3, false }, // 1606 |
| 1615 | { PseudoVLOXEI8_V_MF4_M2_MASK, PseudoVLOXEI8_V_MF4_M2, 0x3, false }, // 1607 |
| 1616 | { PseudoVLOXEI8_V_MF4_MF2_MASK, PseudoVLOXEI8_V_MF4_MF2, 0x3, false }, // 1608 |
| 1617 | { PseudoVLOXEI8_V_MF4_MF4_MASK, PseudoVLOXEI8_V_MF4_MF4, 0x3, false }, // 1609 |
| 1618 | { PseudoVLOXEI8_V_MF8_M1_MASK, PseudoVLOXEI8_V_MF8_M1, 0x3, false }, // 1610 |
| 1619 | { PseudoVLOXEI8_V_MF8_MF2_MASK, PseudoVLOXEI8_V_MF8_MF2, 0x3, false }, // 1611 |
| 1620 | { PseudoVLOXEI8_V_MF8_MF4_MASK, PseudoVLOXEI8_V_MF8_MF4, 0x3, false }, // 1612 |
| 1621 | { PseudoVLOXEI8_V_MF8_MF8_MASK, PseudoVLOXEI8_V_MF8_MF8, 0x3, false }, // 1613 |
| 1622 | { PseudoVLSE16_V_M1_MASK, PseudoVLSE16_V_M1, 0x3, false }, // 1614 |
| 1623 | { PseudoVLSE16_V_M2_MASK, PseudoVLSE16_V_M2, 0x3, false }, // 1615 |
| 1624 | { PseudoVLSE16_V_M4_MASK, PseudoVLSE16_V_M4, 0x3, false }, // 1616 |
| 1625 | { PseudoVLSE16_V_M8_MASK, PseudoVLSE16_V_M8, 0x3, false }, // 1617 |
| 1626 | { PseudoVLSE16_V_MF2_MASK, PseudoVLSE16_V_MF2, 0x3, false }, // 1618 |
| 1627 | { PseudoVLSE16_V_MF4_MASK, PseudoVLSE16_V_MF4, 0x3, false }, // 1619 |
| 1628 | { PseudoVLSE32_V_M1_MASK, PseudoVLSE32_V_M1, 0x3, false }, // 1620 |
| 1629 | { PseudoVLSE32_V_M2_MASK, PseudoVLSE32_V_M2, 0x3, false }, // 1621 |
| 1630 | { PseudoVLSE32_V_M4_MASK, PseudoVLSE32_V_M4, 0x3, false }, // 1622 |
| 1631 | { PseudoVLSE32_V_M8_MASK, PseudoVLSE32_V_M8, 0x3, false }, // 1623 |
| 1632 | { PseudoVLSE32_V_MF2_MASK, PseudoVLSE32_V_MF2, 0x3, false }, // 1624 |
| 1633 | { PseudoVLSE64_V_M1_MASK, PseudoVLSE64_V_M1, 0x3, false }, // 1625 |
| 1634 | { PseudoVLSE64_V_M2_MASK, PseudoVLSE64_V_M2, 0x3, false }, // 1626 |
| 1635 | { PseudoVLSE64_V_M4_MASK, PseudoVLSE64_V_M4, 0x3, false }, // 1627 |
| 1636 | { PseudoVLSE64_V_M8_MASK, PseudoVLSE64_V_M8, 0x3, false }, // 1628 |
| 1637 | { PseudoVLSE8_V_M1_MASK, PseudoVLSE8_V_M1, 0x3, false }, // 1629 |
| 1638 | { PseudoVLSE8_V_M2_MASK, PseudoVLSE8_V_M2, 0x3, false }, // 1630 |
| 1639 | { PseudoVLSE8_V_M4_MASK, PseudoVLSE8_V_M4, 0x3, false }, // 1631 |
| 1640 | { PseudoVLSE8_V_M8_MASK, PseudoVLSE8_V_M8, 0x3, false }, // 1632 |
| 1641 | { PseudoVLSE8_V_MF2_MASK, PseudoVLSE8_V_MF2, 0x3, false }, // 1633 |
| 1642 | { PseudoVLSE8_V_MF4_MASK, PseudoVLSE8_V_MF4, 0x3, false }, // 1634 |
| 1643 | { PseudoVLSE8_V_MF8_MASK, PseudoVLSE8_V_MF8, 0x3, false }, // 1635 |
| 1644 | { PseudoVLUXEI16_V_M1_M1_MASK, PseudoVLUXEI16_V_M1_M1, 0x3, false }, // 1636 |
| 1645 | { PseudoVLUXEI16_V_M1_M2_MASK, PseudoVLUXEI16_V_M1_M2, 0x3, false }, // 1637 |
| 1646 | { PseudoVLUXEI16_V_M1_M4_MASK, PseudoVLUXEI16_V_M1_M4, 0x3, false }, // 1638 |
| 1647 | { PseudoVLUXEI16_V_M1_MF2_MASK, PseudoVLUXEI16_V_M1_MF2, 0x3, false }, // 1639 |
| 1648 | { PseudoVLUXEI16_V_M2_M1_MASK, PseudoVLUXEI16_V_M2_M1, 0x3, false }, // 1640 |
| 1649 | { PseudoVLUXEI16_V_M2_M2_MASK, PseudoVLUXEI16_V_M2_M2, 0x3, false }, // 1641 |
| 1650 | { PseudoVLUXEI16_V_M2_M4_MASK, PseudoVLUXEI16_V_M2_M4, 0x3, false }, // 1642 |
| 1651 | { PseudoVLUXEI16_V_M2_M8_MASK, PseudoVLUXEI16_V_M2_M8, 0x3, false }, // 1643 |
| 1652 | { PseudoVLUXEI16_V_M4_M2_MASK, PseudoVLUXEI16_V_M4_M2, 0x3, false }, // 1644 |
| 1653 | { PseudoVLUXEI16_V_M4_M4_MASK, PseudoVLUXEI16_V_M4_M4, 0x3, false }, // 1645 |
| 1654 | { PseudoVLUXEI16_V_M4_M8_MASK, PseudoVLUXEI16_V_M4_M8, 0x3, false }, // 1646 |
| 1655 | { PseudoVLUXEI16_V_M8_M4_MASK, PseudoVLUXEI16_V_M8_M4, 0x3, false }, // 1647 |
| 1656 | { PseudoVLUXEI16_V_M8_M8_MASK, PseudoVLUXEI16_V_M8_M8, 0x3, false }, // 1648 |
| 1657 | { PseudoVLUXEI16_V_MF2_M1_MASK, PseudoVLUXEI16_V_MF2_M1, 0x3, false }, // 1649 |
| 1658 | { PseudoVLUXEI16_V_MF2_M2_MASK, PseudoVLUXEI16_V_MF2_M2, 0x3, false }, // 1650 |
| 1659 | { PseudoVLUXEI16_V_MF2_MF2_MASK, PseudoVLUXEI16_V_MF2_MF2, 0x3, false }, // 1651 |
| 1660 | { PseudoVLUXEI16_V_MF2_MF4_MASK, PseudoVLUXEI16_V_MF2_MF4, 0x3, false }, // 1652 |
| 1661 | { PseudoVLUXEI16_V_MF4_M1_MASK, PseudoVLUXEI16_V_MF4_M1, 0x3, false }, // 1653 |
| 1662 | { PseudoVLUXEI16_V_MF4_MF2_MASK, PseudoVLUXEI16_V_MF4_MF2, 0x3, false }, // 1654 |
| 1663 | { PseudoVLUXEI16_V_MF4_MF4_MASK, PseudoVLUXEI16_V_MF4_MF4, 0x3, false }, // 1655 |
| 1664 | { PseudoVLUXEI16_V_MF4_MF8_MASK, PseudoVLUXEI16_V_MF4_MF8, 0x3, false }, // 1656 |
| 1665 | { PseudoVLUXEI32_V_M1_M1_MASK, PseudoVLUXEI32_V_M1_M1, 0x3, false }, // 1657 |
| 1666 | { PseudoVLUXEI32_V_M1_M2_MASK, PseudoVLUXEI32_V_M1_M2, 0x3, false }, // 1658 |
| 1667 | { PseudoVLUXEI32_V_M1_MF2_MASK, PseudoVLUXEI32_V_M1_MF2, 0x3, false }, // 1659 |
| 1668 | { PseudoVLUXEI32_V_M1_MF4_MASK, PseudoVLUXEI32_V_M1_MF4, 0x3, false }, // 1660 |
| 1669 | { PseudoVLUXEI32_V_M2_M1_MASK, PseudoVLUXEI32_V_M2_M1, 0x3, false }, // 1661 |
| 1670 | { PseudoVLUXEI32_V_M2_M2_MASK, PseudoVLUXEI32_V_M2_M2, 0x3, false }, // 1662 |
| 1671 | { PseudoVLUXEI32_V_M2_M4_MASK, PseudoVLUXEI32_V_M2_M4, 0x3, false }, // 1663 |
| 1672 | { PseudoVLUXEI32_V_M2_MF2_MASK, PseudoVLUXEI32_V_M2_MF2, 0x3, false }, // 1664 |
| 1673 | { PseudoVLUXEI32_V_M4_M1_MASK, PseudoVLUXEI32_V_M4_M1, 0x3, false }, // 1665 |
| 1674 | { PseudoVLUXEI32_V_M4_M2_MASK, PseudoVLUXEI32_V_M4_M2, 0x3, false }, // 1666 |
| 1675 | { PseudoVLUXEI32_V_M4_M4_MASK, PseudoVLUXEI32_V_M4_M4, 0x3, false }, // 1667 |
| 1676 | { PseudoVLUXEI32_V_M4_M8_MASK, PseudoVLUXEI32_V_M4_M8, 0x3, false }, // 1668 |
| 1677 | { PseudoVLUXEI32_V_M8_M2_MASK, PseudoVLUXEI32_V_M8_M2, 0x3, false }, // 1669 |
| 1678 | { PseudoVLUXEI32_V_M8_M4_MASK, PseudoVLUXEI32_V_M8_M4, 0x3, false }, // 1670 |
| 1679 | { PseudoVLUXEI32_V_M8_M8_MASK, PseudoVLUXEI32_V_M8_M8, 0x3, false }, // 1671 |
| 1680 | { PseudoVLUXEI32_V_MF2_M1_MASK, PseudoVLUXEI32_V_MF2_M1, 0x3, false }, // 1672 |
| 1681 | { PseudoVLUXEI32_V_MF2_MF2_MASK, PseudoVLUXEI32_V_MF2_MF2, 0x3, false }, // 1673 |
| 1682 | { PseudoVLUXEI32_V_MF2_MF4_MASK, PseudoVLUXEI32_V_MF2_MF4, 0x3, false }, // 1674 |
| 1683 | { PseudoVLUXEI32_V_MF2_MF8_MASK, PseudoVLUXEI32_V_MF2_MF8, 0x3, false }, // 1675 |
| 1684 | { PseudoVLUXEI64_V_M1_M1_MASK, PseudoVLUXEI64_V_M1_M1, 0x3, false }, // 1676 |
| 1685 | { PseudoVLUXEI64_V_M1_MF2_MASK, PseudoVLUXEI64_V_M1_MF2, 0x3, false }, // 1677 |
| 1686 | { PseudoVLUXEI64_V_M1_MF4_MASK, PseudoVLUXEI64_V_M1_MF4, 0x3, false }, // 1678 |
| 1687 | { PseudoVLUXEI64_V_M1_MF8_MASK, PseudoVLUXEI64_V_M1_MF8, 0x3, false }, // 1679 |
| 1688 | { PseudoVLUXEI64_V_M2_M1_MASK, PseudoVLUXEI64_V_M2_M1, 0x3, false }, // 1680 |
| 1689 | { PseudoVLUXEI64_V_M2_M2_MASK, PseudoVLUXEI64_V_M2_M2, 0x3, false }, // 1681 |
| 1690 | { PseudoVLUXEI64_V_M2_MF2_MASK, PseudoVLUXEI64_V_M2_MF2, 0x3, false }, // 1682 |
| 1691 | { PseudoVLUXEI64_V_M2_MF4_MASK, PseudoVLUXEI64_V_M2_MF4, 0x3, false }, // 1683 |
| 1692 | { PseudoVLUXEI64_V_M4_M1_MASK, PseudoVLUXEI64_V_M4_M1, 0x3, false }, // 1684 |
| 1693 | { PseudoVLUXEI64_V_M4_M2_MASK, PseudoVLUXEI64_V_M4_M2, 0x3, false }, // 1685 |
| 1694 | { PseudoVLUXEI64_V_M4_M4_MASK, PseudoVLUXEI64_V_M4_M4, 0x3, false }, // 1686 |
| 1695 | { PseudoVLUXEI64_V_M4_MF2_MASK, PseudoVLUXEI64_V_M4_MF2, 0x3, false }, // 1687 |
| 1696 | { PseudoVLUXEI64_V_M8_M1_MASK, PseudoVLUXEI64_V_M8_M1, 0x3, false }, // 1688 |
| 1697 | { PseudoVLUXEI64_V_M8_M2_MASK, PseudoVLUXEI64_V_M8_M2, 0x3, false }, // 1689 |
| 1698 | { PseudoVLUXEI64_V_M8_M4_MASK, PseudoVLUXEI64_V_M8_M4, 0x3, false }, // 1690 |
| 1699 | { PseudoVLUXEI64_V_M8_M8_MASK, PseudoVLUXEI64_V_M8_M8, 0x3, false }, // 1691 |
| 1700 | { PseudoVLUXEI8_V_M1_M1_MASK, PseudoVLUXEI8_V_M1_M1, 0x3, false }, // 1692 |
| 1701 | { PseudoVLUXEI8_V_M1_M2_MASK, PseudoVLUXEI8_V_M1_M2, 0x3, false }, // 1693 |
| 1702 | { PseudoVLUXEI8_V_M1_M4_MASK, PseudoVLUXEI8_V_M1_M4, 0x3, false }, // 1694 |
| 1703 | { PseudoVLUXEI8_V_M1_M8_MASK, PseudoVLUXEI8_V_M1_M8, 0x3, false }, // 1695 |
| 1704 | { PseudoVLUXEI8_V_M2_M2_MASK, PseudoVLUXEI8_V_M2_M2, 0x3, false }, // 1696 |
| 1705 | { PseudoVLUXEI8_V_M2_M4_MASK, PseudoVLUXEI8_V_M2_M4, 0x3, false }, // 1697 |
| 1706 | { PseudoVLUXEI8_V_M2_M8_MASK, PseudoVLUXEI8_V_M2_M8, 0x3, false }, // 1698 |
| 1707 | { PseudoVLUXEI8_V_M4_M4_MASK, PseudoVLUXEI8_V_M4_M4, 0x3, false }, // 1699 |
| 1708 | { PseudoVLUXEI8_V_M4_M8_MASK, PseudoVLUXEI8_V_M4_M8, 0x3, false }, // 1700 |
| 1709 | { PseudoVLUXEI8_V_M8_M8_MASK, PseudoVLUXEI8_V_M8_M8, 0x3, false }, // 1701 |
| 1710 | { PseudoVLUXEI8_V_MF2_M1_MASK, PseudoVLUXEI8_V_MF2_M1, 0x3, false }, // 1702 |
| 1711 | { PseudoVLUXEI8_V_MF2_M2_MASK, PseudoVLUXEI8_V_MF2_M2, 0x3, false }, // 1703 |
| 1712 | { PseudoVLUXEI8_V_MF2_M4_MASK, PseudoVLUXEI8_V_MF2_M4, 0x3, false }, // 1704 |
| 1713 | { PseudoVLUXEI8_V_MF2_MF2_MASK, PseudoVLUXEI8_V_MF2_MF2, 0x3, false }, // 1705 |
| 1714 | { PseudoVLUXEI8_V_MF4_M1_MASK, PseudoVLUXEI8_V_MF4_M1, 0x3, false }, // 1706 |
| 1715 | { PseudoVLUXEI8_V_MF4_M2_MASK, PseudoVLUXEI8_V_MF4_M2, 0x3, false }, // 1707 |
| 1716 | { PseudoVLUXEI8_V_MF4_MF2_MASK, PseudoVLUXEI8_V_MF4_MF2, 0x3, false }, // 1708 |
| 1717 | { PseudoVLUXEI8_V_MF4_MF4_MASK, PseudoVLUXEI8_V_MF4_MF4, 0x3, false }, // 1709 |
| 1718 | { PseudoVLUXEI8_V_MF8_M1_MASK, PseudoVLUXEI8_V_MF8_M1, 0x3, false }, // 1710 |
| 1719 | { PseudoVLUXEI8_V_MF8_MF2_MASK, PseudoVLUXEI8_V_MF8_MF2, 0x3, false }, // 1711 |
| 1720 | { PseudoVLUXEI8_V_MF8_MF4_MASK, PseudoVLUXEI8_V_MF8_MF4, 0x3, false }, // 1712 |
| 1721 | { PseudoVLUXEI8_V_MF8_MF8_MASK, PseudoVLUXEI8_V_MF8_MF8, 0x3, false }, // 1713 |
| 1722 | { PseudoVMACC_VV_M1_MASK, PseudoVMACC_VV_M1, 0x3, false }, // 1714 |
| 1723 | { PseudoVMACC_VV_M2_MASK, PseudoVMACC_VV_M2, 0x3, false }, // 1715 |
| 1724 | { PseudoVMACC_VV_M4_MASK, PseudoVMACC_VV_M4, 0x3, false }, // 1716 |
| 1725 | { PseudoVMACC_VV_M8_MASK, PseudoVMACC_VV_M8, 0x3, false }, // 1717 |
| 1726 | { PseudoVMACC_VV_MF2_MASK, PseudoVMACC_VV_MF2, 0x3, false }, // 1718 |
| 1727 | { PseudoVMACC_VV_MF4_MASK, PseudoVMACC_VV_MF4, 0x3, false }, // 1719 |
| 1728 | { PseudoVMACC_VV_MF8_MASK, PseudoVMACC_VV_MF8, 0x3, false }, // 1720 |
| 1729 | { PseudoVMACC_VX_M1_MASK, PseudoVMACC_VX_M1, 0x3, false }, // 1721 |
| 1730 | { PseudoVMACC_VX_M2_MASK, PseudoVMACC_VX_M2, 0x3, false }, // 1722 |
| 1731 | { PseudoVMACC_VX_M4_MASK, PseudoVMACC_VX_M4, 0x3, false }, // 1723 |
| 1732 | { PseudoVMACC_VX_M8_MASK, PseudoVMACC_VX_M8, 0x3, false }, // 1724 |
| 1733 | { PseudoVMACC_VX_MF2_MASK, PseudoVMACC_VX_MF2, 0x3, false }, // 1725 |
| 1734 | { PseudoVMACC_VX_MF4_MASK, PseudoVMACC_VX_MF4, 0x3, false }, // 1726 |
| 1735 | { PseudoVMACC_VX_MF8_MASK, PseudoVMACC_VX_MF8, 0x3, false }, // 1727 |
| 1736 | { PseudoVMADD_VV_M1_MASK, PseudoVMADD_VV_M1, 0x3, false }, // 1728 |
| 1737 | { PseudoVMADD_VV_M2_MASK, PseudoVMADD_VV_M2, 0x3, false }, // 1729 |
| 1738 | { PseudoVMADD_VV_M4_MASK, PseudoVMADD_VV_M4, 0x3, false }, // 1730 |
| 1739 | { PseudoVMADD_VV_M8_MASK, PseudoVMADD_VV_M8, 0x3, false }, // 1731 |
| 1740 | { PseudoVMADD_VV_MF2_MASK, PseudoVMADD_VV_MF2, 0x3, false }, // 1732 |
| 1741 | { PseudoVMADD_VV_MF4_MASK, PseudoVMADD_VV_MF4, 0x3, false }, // 1733 |
| 1742 | { PseudoVMADD_VV_MF8_MASK, PseudoVMADD_VV_MF8, 0x3, false }, // 1734 |
| 1743 | { PseudoVMADD_VX_M1_MASK, PseudoVMADD_VX_M1, 0x3, false }, // 1735 |
| 1744 | { PseudoVMADD_VX_M2_MASK, PseudoVMADD_VX_M2, 0x3, false }, // 1736 |
| 1745 | { PseudoVMADD_VX_M4_MASK, PseudoVMADD_VX_M4, 0x3, false }, // 1737 |
| 1746 | { PseudoVMADD_VX_M8_MASK, PseudoVMADD_VX_M8, 0x3, false }, // 1738 |
| 1747 | { PseudoVMADD_VX_MF2_MASK, PseudoVMADD_VX_MF2, 0x3, false }, // 1739 |
| 1748 | { PseudoVMADD_VX_MF4_MASK, PseudoVMADD_VX_MF4, 0x3, false }, // 1740 |
| 1749 | { PseudoVMADD_VX_MF8_MASK, PseudoVMADD_VX_MF8, 0x3, false }, // 1741 |
| 1750 | { PseudoVMAXU_VV_M1_MASK, PseudoVMAXU_VV_M1, 0x3, false }, // 1742 |
| 1751 | { PseudoVMAXU_VV_M2_MASK, PseudoVMAXU_VV_M2, 0x3, false }, // 1743 |
| 1752 | { PseudoVMAXU_VV_M4_MASK, PseudoVMAXU_VV_M4, 0x3, false }, // 1744 |
| 1753 | { PseudoVMAXU_VV_M8_MASK, PseudoVMAXU_VV_M8, 0x3, false }, // 1745 |
| 1754 | { PseudoVMAXU_VV_MF2_MASK, PseudoVMAXU_VV_MF2, 0x3, false }, // 1746 |
| 1755 | { PseudoVMAXU_VV_MF4_MASK, PseudoVMAXU_VV_MF4, 0x3, false }, // 1747 |
| 1756 | { PseudoVMAXU_VV_MF8_MASK, PseudoVMAXU_VV_MF8, 0x3, false }, // 1748 |
| 1757 | { PseudoVMAXU_VX_M1_MASK, PseudoVMAXU_VX_M1, 0x3, false }, // 1749 |
| 1758 | { PseudoVMAXU_VX_M2_MASK, PseudoVMAXU_VX_M2, 0x3, false }, // 1750 |
| 1759 | { PseudoVMAXU_VX_M4_MASK, PseudoVMAXU_VX_M4, 0x3, false }, // 1751 |
| 1760 | { PseudoVMAXU_VX_M8_MASK, PseudoVMAXU_VX_M8, 0x3, false }, // 1752 |
| 1761 | { PseudoVMAXU_VX_MF2_MASK, PseudoVMAXU_VX_MF2, 0x3, false }, // 1753 |
| 1762 | { PseudoVMAXU_VX_MF4_MASK, PseudoVMAXU_VX_MF4, 0x3, false }, // 1754 |
| 1763 | { PseudoVMAXU_VX_MF8_MASK, PseudoVMAXU_VX_MF8, 0x3, false }, // 1755 |
| 1764 | { PseudoVMAX_VV_M1_MASK, PseudoVMAX_VV_M1, 0x3, false }, // 1756 |
| 1765 | { PseudoVMAX_VV_M2_MASK, PseudoVMAX_VV_M2, 0x3, false }, // 1757 |
| 1766 | { PseudoVMAX_VV_M4_MASK, PseudoVMAX_VV_M4, 0x3, false }, // 1758 |
| 1767 | { PseudoVMAX_VV_M8_MASK, PseudoVMAX_VV_M8, 0x3, false }, // 1759 |
| 1768 | { PseudoVMAX_VV_MF2_MASK, PseudoVMAX_VV_MF2, 0x3, false }, // 1760 |
| 1769 | { PseudoVMAX_VV_MF4_MASK, PseudoVMAX_VV_MF4, 0x3, false }, // 1761 |
| 1770 | { PseudoVMAX_VV_MF8_MASK, PseudoVMAX_VV_MF8, 0x3, false }, // 1762 |
| 1771 | { PseudoVMAX_VX_M1_MASK, PseudoVMAX_VX_M1, 0x3, false }, // 1763 |
| 1772 | { PseudoVMAX_VX_M2_MASK, PseudoVMAX_VX_M2, 0x3, false }, // 1764 |
| 1773 | { PseudoVMAX_VX_M4_MASK, PseudoVMAX_VX_M4, 0x3, false }, // 1765 |
| 1774 | { PseudoVMAX_VX_M8_MASK, PseudoVMAX_VX_M8, 0x3, false }, // 1766 |
| 1775 | { PseudoVMAX_VX_MF2_MASK, PseudoVMAX_VX_MF2, 0x3, false }, // 1767 |
| 1776 | { PseudoVMAX_VX_MF4_MASK, PseudoVMAX_VX_MF4, 0x3, false }, // 1768 |
| 1777 | { PseudoVMAX_VX_MF8_MASK, PseudoVMAX_VX_MF8, 0x3, false }, // 1769 |
| 1778 | { PseudoVMFEQ_VFPR16_M1_MASK, PseudoVMFEQ_VFPR16_M1, 0x3, false }, // 1770 |
| 1779 | { PseudoVMFEQ_VFPR16_M2_MASK, PseudoVMFEQ_VFPR16_M2, 0x3, false }, // 1771 |
| 1780 | { PseudoVMFEQ_VFPR16_M4_MASK, PseudoVMFEQ_VFPR16_M4, 0x3, false }, // 1772 |
| 1781 | { PseudoVMFEQ_VFPR16_M8_MASK, PseudoVMFEQ_VFPR16_M8, 0x3, false }, // 1773 |
| 1782 | { PseudoVMFEQ_VFPR16_MF2_MASK, PseudoVMFEQ_VFPR16_MF2, 0x3, false }, // 1774 |
| 1783 | { PseudoVMFEQ_VFPR16_MF4_MASK, PseudoVMFEQ_VFPR16_MF4, 0x3, false }, // 1775 |
| 1784 | { PseudoVMFEQ_VFPR32_M1_MASK, PseudoVMFEQ_VFPR32_M1, 0x3, false }, // 1776 |
| 1785 | { PseudoVMFEQ_VFPR32_M2_MASK, PseudoVMFEQ_VFPR32_M2, 0x3, false }, // 1777 |
| 1786 | { PseudoVMFEQ_VFPR32_M4_MASK, PseudoVMFEQ_VFPR32_M4, 0x3, false }, // 1778 |
| 1787 | { PseudoVMFEQ_VFPR32_M8_MASK, PseudoVMFEQ_VFPR32_M8, 0x3, false }, // 1779 |
| 1788 | { PseudoVMFEQ_VFPR32_MF2_MASK, PseudoVMFEQ_VFPR32_MF2, 0x3, false }, // 1780 |
| 1789 | { PseudoVMFEQ_VFPR64_M1_MASK, PseudoVMFEQ_VFPR64_M1, 0x3, false }, // 1781 |
| 1790 | { PseudoVMFEQ_VFPR64_M2_MASK, PseudoVMFEQ_VFPR64_M2, 0x3, false }, // 1782 |
| 1791 | { PseudoVMFEQ_VFPR64_M4_MASK, PseudoVMFEQ_VFPR64_M4, 0x3, false }, // 1783 |
| 1792 | { PseudoVMFEQ_VFPR64_M8_MASK, PseudoVMFEQ_VFPR64_M8, 0x3, false }, // 1784 |
| 1793 | { PseudoVMFEQ_VV_M1_MASK, PseudoVMFEQ_VV_M1, 0x3, false }, // 1785 |
| 1794 | { PseudoVMFEQ_VV_M2_MASK, PseudoVMFEQ_VV_M2, 0x3, false }, // 1786 |
| 1795 | { PseudoVMFEQ_VV_M4_MASK, PseudoVMFEQ_VV_M4, 0x3, false }, // 1787 |
| 1796 | { PseudoVMFEQ_VV_M8_MASK, PseudoVMFEQ_VV_M8, 0x3, false }, // 1788 |
| 1797 | { PseudoVMFEQ_VV_MF2_MASK, PseudoVMFEQ_VV_MF2, 0x3, false }, // 1789 |
| 1798 | { PseudoVMFEQ_VV_MF4_MASK, PseudoVMFEQ_VV_MF4, 0x3, false }, // 1790 |
| 1799 | { PseudoVMFGE_VFPR16_M1_MASK, PseudoVMFGE_VFPR16_M1, 0x3, false }, // 1791 |
| 1800 | { PseudoVMFGE_VFPR16_M2_MASK, PseudoVMFGE_VFPR16_M2, 0x3, false }, // 1792 |
| 1801 | { PseudoVMFGE_VFPR16_M4_MASK, PseudoVMFGE_VFPR16_M4, 0x3, false }, // 1793 |
| 1802 | { PseudoVMFGE_VFPR16_M8_MASK, PseudoVMFGE_VFPR16_M8, 0x3, false }, // 1794 |
| 1803 | { PseudoVMFGE_VFPR16_MF2_MASK, PseudoVMFGE_VFPR16_MF2, 0x3, false }, // 1795 |
| 1804 | { PseudoVMFGE_VFPR16_MF4_MASK, PseudoVMFGE_VFPR16_MF4, 0x3, false }, // 1796 |
| 1805 | { PseudoVMFGE_VFPR32_M1_MASK, PseudoVMFGE_VFPR32_M1, 0x3, false }, // 1797 |
| 1806 | { PseudoVMFGE_VFPR32_M2_MASK, PseudoVMFGE_VFPR32_M2, 0x3, false }, // 1798 |
| 1807 | { PseudoVMFGE_VFPR32_M4_MASK, PseudoVMFGE_VFPR32_M4, 0x3, false }, // 1799 |
| 1808 | { PseudoVMFGE_VFPR32_M8_MASK, PseudoVMFGE_VFPR32_M8, 0x3, false }, // 1800 |
| 1809 | { PseudoVMFGE_VFPR32_MF2_MASK, PseudoVMFGE_VFPR32_MF2, 0x3, false }, // 1801 |
| 1810 | { PseudoVMFGE_VFPR64_M1_MASK, PseudoVMFGE_VFPR64_M1, 0x3, false }, // 1802 |
| 1811 | { PseudoVMFGE_VFPR64_M2_MASK, PseudoVMFGE_VFPR64_M2, 0x3, false }, // 1803 |
| 1812 | { PseudoVMFGE_VFPR64_M4_MASK, PseudoVMFGE_VFPR64_M4, 0x3, false }, // 1804 |
| 1813 | { PseudoVMFGE_VFPR64_M8_MASK, PseudoVMFGE_VFPR64_M8, 0x3, false }, // 1805 |
| 1814 | { PseudoVMFGT_VFPR16_M1_MASK, PseudoVMFGT_VFPR16_M1, 0x3, false }, // 1806 |
| 1815 | { PseudoVMFGT_VFPR16_M2_MASK, PseudoVMFGT_VFPR16_M2, 0x3, false }, // 1807 |
| 1816 | { PseudoVMFGT_VFPR16_M4_MASK, PseudoVMFGT_VFPR16_M4, 0x3, false }, // 1808 |
| 1817 | { PseudoVMFGT_VFPR16_M8_MASK, PseudoVMFGT_VFPR16_M8, 0x3, false }, // 1809 |
| 1818 | { PseudoVMFGT_VFPR16_MF2_MASK, PseudoVMFGT_VFPR16_MF2, 0x3, false }, // 1810 |
| 1819 | { PseudoVMFGT_VFPR16_MF4_MASK, PseudoVMFGT_VFPR16_MF4, 0x3, false }, // 1811 |
| 1820 | { PseudoVMFGT_VFPR32_M1_MASK, PseudoVMFGT_VFPR32_M1, 0x3, false }, // 1812 |
| 1821 | { PseudoVMFGT_VFPR32_M2_MASK, PseudoVMFGT_VFPR32_M2, 0x3, false }, // 1813 |
| 1822 | { PseudoVMFGT_VFPR32_M4_MASK, PseudoVMFGT_VFPR32_M4, 0x3, false }, // 1814 |
| 1823 | { PseudoVMFGT_VFPR32_M8_MASK, PseudoVMFGT_VFPR32_M8, 0x3, false }, // 1815 |
| 1824 | { PseudoVMFGT_VFPR32_MF2_MASK, PseudoVMFGT_VFPR32_MF2, 0x3, false }, // 1816 |
| 1825 | { PseudoVMFGT_VFPR64_M1_MASK, PseudoVMFGT_VFPR64_M1, 0x3, false }, // 1817 |
| 1826 | { PseudoVMFGT_VFPR64_M2_MASK, PseudoVMFGT_VFPR64_M2, 0x3, false }, // 1818 |
| 1827 | { PseudoVMFGT_VFPR64_M4_MASK, PseudoVMFGT_VFPR64_M4, 0x3, false }, // 1819 |
| 1828 | { PseudoVMFGT_VFPR64_M8_MASK, PseudoVMFGT_VFPR64_M8, 0x3, false }, // 1820 |
| 1829 | { PseudoVMFLE_VFPR16_M1_MASK, PseudoVMFLE_VFPR16_M1, 0x3, false }, // 1821 |
| 1830 | { PseudoVMFLE_VFPR16_M2_MASK, PseudoVMFLE_VFPR16_M2, 0x3, false }, // 1822 |
| 1831 | { PseudoVMFLE_VFPR16_M4_MASK, PseudoVMFLE_VFPR16_M4, 0x3, false }, // 1823 |
| 1832 | { PseudoVMFLE_VFPR16_M8_MASK, PseudoVMFLE_VFPR16_M8, 0x3, false }, // 1824 |
| 1833 | { PseudoVMFLE_VFPR16_MF2_MASK, PseudoVMFLE_VFPR16_MF2, 0x3, false }, // 1825 |
| 1834 | { PseudoVMFLE_VFPR16_MF4_MASK, PseudoVMFLE_VFPR16_MF4, 0x3, false }, // 1826 |
| 1835 | { PseudoVMFLE_VFPR32_M1_MASK, PseudoVMFLE_VFPR32_M1, 0x3, false }, // 1827 |
| 1836 | { PseudoVMFLE_VFPR32_M2_MASK, PseudoVMFLE_VFPR32_M2, 0x3, false }, // 1828 |
| 1837 | { PseudoVMFLE_VFPR32_M4_MASK, PseudoVMFLE_VFPR32_M4, 0x3, false }, // 1829 |
| 1838 | { PseudoVMFLE_VFPR32_M8_MASK, PseudoVMFLE_VFPR32_M8, 0x3, false }, // 1830 |
| 1839 | { PseudoVMFLE_VFPR32_MF2_MASK, PseudoVMFLE_VFPR32_MF2, 0x3, false }, // 1831 |
| 1840 | { PseudoVMFLE_VFPR64_M1_MASK, PseudoVMFLE_VFPR64_M1, 0x3, false }, // 1832 |
| 1841 | { PseudoVMFLE_VFPR64_M2_MASK, PseudoVMFLE_VFPR64_M2, 0x3, false }, // 1833 |
| 1842 | { PseudoVMFLE_VFPR64_M4_MASK, PseudoVMFLE_VFPR64_M4, 0x3, false }, // 1834 |
| 1843 | { PseudoVMFLE_VFPR64_M8_MASK, PseudoVMFLE_VFPR64_M8, 0x3, false }, // 1835 |
| 1844 | { PseudoVMFLE_VV_M1_MASK, PseudoVMFLE_VV_M1, 0x3, false }, // 1836 |
| 1845 | { PseudoVMFLE_VV_M2_MASK, PseudoVMFLE_VV_M2, 0x3, false }, // 1837 |
| 1846 | { PseudoVMFLE_VV_M4_MASK, PseudoVMFLE_VV_M4, 0x3, false }, // 1838 |
| 1847 | { PseudoVMFLE_VV_M8_MASK, PseudoVMFLE_VV_M8, 0x3, false }, // 1839 |
| 1848 | { PseudoVMFLE_VV_MF2_MASK, PseudoVMFLE_VV_MF2, 0x3, false }, // 1840 |
| 1849 | { PseudoVMFLE_VV_MF4_MASK, PseudoVMFLE_VV_MF4, 0x3, false }, // 1841 |
| 1850 | { PseudoVMFLT_VFPR16_M1_MASK, PseudoVMFLT_VFPR16_M1, 0x3, false }, // 1842 |
| 1851 | { PseudoVMFLT_VFPR16_M2_MASK, PseudoVMFLT_VFPR16_M2, 0x3, false }, // 1843 |
| 1852 | { PseudoVMFLT_VFPR16_M4_MASK, PseudoVMFLT_VFPR16_M4, 0x3, false }, // 1844 |
| 1853 | { PseudoVMFLT_VFPR16_M8_MASK, PseudoVMFLT_VFPR16_M8, 0x3, false }, // 1845 |
| 1854 | { PseudoVMFLT_VFPR16_MF2_MASK, PseudoVMFLT_VFPR16_MF2, 0x3, false }, // 1846 |
| 1855 | { PseudoVMFLT_VFPR16_MF4_MASK, PseudoVMFLT_VFPR16_MF4, 0x3, false }, // 1847 |
| 1856 | { PseudoVMFLT_VFPR32_M1_MASK, PseudoVMFLT_VFPR32_M1, 0x3, false }, // 1848 |
| 1857 | { PseudoVMFLT_VFPR32_M2_MASK, PseudoVMFLT_VFPR32_M2, 0x3, false }, // 1849 |
| 1858 | { PseudoVMFLT_VFPR32_M4_MASK, PseudoVMFLT_VFPR32_M4, 0x3, false }, // 1850 |
| 1859 | { PseudoVMFLT_VFPR32_M8_MASK, PseudoVMFLT_VFPR32_M8, 0x3, false }, // 1851 |
| 1860 | { PseudoVMFLT_VFPR32_MF2_MASK, PseudoVMFLT_VFPR32_MF2, 0x3, false }, // 1852 |
| 1861 | { PseudoVMFLT_VFPR64_M1_MASK, PseudoVMFLT_VFPR64_M1, 0x3, false }, // 1853 |
| 1862 | { PseudoVMFLT_VFPR64_M2_MASK, PseudoVMFLT_VFPR64_M2, 0x3, false }, // 1854 |
| 1863 | { PseudoVMFLT_VFPR64_M4_MASK, PseudoVMFLT_VFPR64_M4, 0x3, false }, // 1855 |
| 1864 | { PseudoVMFLT_VFPR64_M8_MASK, PseudoVMFLT_VFPR64_M8, 0x3, false }, // 1856 |
| 1865 | { PseudoVMFLT_VV_M1_MASK, PseudoVMFLT_VV_M1, 0x3, false }, // 1857 |
| 1866 | { PseudoVMFLT_VV_M2_MASK, PseudoVMFLT_VV_M2, 0x3, false }, // 1858 |
| 1867 | { PseudoVMFLT_VV_M4_MASK, PseudoVMFLT_VV_M4, 0x3, false }, // 1859 |
| 1868 | { PseudoVMFLT_VV_M8_MASK, PseudoVMFLT_VV_M8, 0x3, false }, // 1860 |
| 1869 | { PseudoVMFLT_VV_MF2_MASK, PseudoVMFLT_VV_MF2, 0x3, false }, // 1861 |
| 1870 | { PseudoVMFLT_VV_MF4_MASK, PseudoVMFLT_VV_MF4, 0x3, false }, // 1862 |
| 1871 | { PseudoVMFNE_VFPR16_M1_MASK, PseudoVMFNE_VFPR16_M1, 0x3, false }, // 1863 |
| 1872 | { PseudoVMFNE_VFPR16_M2_MASK, PseudoVMFNE_VFPR16_M2, 0x3, false }, // 1864 |
| 1873 | { PseudoVMFNE_VFPR16_M4_MASK, PseudoVMFNE_VFPR16_M4, 0x3, false }, // 1865 |
| 1874 | { PseudoVMFNE_VFPR16_M8_MASK, PseudoVMFNE_VFPR16_M8, 0x3, false }, // 1866 |
| 1875 | { PseudoVMFNE_VFPR16_MF2_MASK, PseudoVMFNE_VFPR16_MF2, 0x3, false }, // 1867 |
| 1876 | { PseudoVMFNE_VFPR16_MF4_MASK, PseudoVMFNE_VFPR16_MF4, 0x3, false }, // 1868 |
| 1877 | { PseudoVMFNE_VFPR32_M1_MASK, PseudoVMFNE_VFPR32_M1, 0x3, false }, // 1869 |
| 1878 | { PseudoVMFNE_VFPR32_M2_MASK, PseudoVMFNE_VFPR32_M2, 0x3, false }, // 1870 |
| 1879 | { PseudoVMFNE_VFPR32_M4_MASK, PseudoVMFNE_VFPR32_M4, 0x3, false }, // 1871 |
| 1880 | { PseudoVMFNE_VFPR32_M8_MASK, PseudoVMFNE_VFPR32_M8, 0x3, false }, // 1872 |
| 1881 | { PseudoVMFNE_VFPR32_MF2_MASK, PseudoVMFNE_VFPR32_MF2, 0x3, false }, // 1873 |
| 1882 | { PseudoVMFNE_VFPR64_M1_MASK, PseudoVMFNE_VFPR64_M1, 0x3, false }, // 1874 |
| 1883 | { PseudoVMFNE_VFPR64_M2_MASK, PseudoVMFNE_VFPR64_M2, 0x3, false }, // 1875 |
| 1884 | { PseudoVMFNE_VFPR64_M4_MASK, PseudoVMFNE_VFPR64_M4, 0x3, false }, // 1876 |
| 1885 | { PseudoVMFNE_VFPR64_M8_MASK, PseudoVMFNE_VFPR64_M8, 0x3, false }, // 1877 |
| 1886 | { PseudoVMFNE_VV_M1_MASK, PseudoVMFNE_VV_M1, 0x3, false }, // 1878 |
| 1887 | { PseudoVMFNE_VV_M2_MASK, PseudoVMFNE_VV_M2, 0x3, false }, // 1879 |
| 1888 | { PseudoVMFNE_VV_M4_MASK, PseudoVMFNE_VV_M4, 0x3, false }, // 1880 |
| 1889 | { PseudoVMFNE_VV_M8_MASK, PseudoVMFNE_VV_M8, 0x3, false }, // 1881 |
| 1890 | { PseudoVMFNE_VV_MF2_MASK, PseudoVMFNE_VV_MF2, 0x3, false }, // 1882 |
| 1891 | { PseudoVMFNE_VV_MF4_MASK, PseudoVMFNE_VV_MF4, 0x3, false }, // 1883 |
| 1892 | { PseudoVMINU_VV_M1_MASK, PseudoVMINU_VV_M1, 0x3, false }, // 1884 |
| 1893 | { PseudoVMINU_VV_M2_MASK, PseudoVMINU_VV_M2, 0x3, false }, // 1885 |
| 1894 | { PseudoVMINU_VV_M4_MASK, PseudoVMINU_VV_M4, 0x3, false }, // 1886 |
| 1895 | { PseudoVMINU_VV_M8_MASK, PseudoVMINU_VV_M8, 0x3, false }, // 1887 |
| 1896 | { PseudoVMINU_VV_MF2_MASK, PseudoVMINU_VV_MF2, 0x3, false }, // 1888 |
| 1897 | { PseudoVMINU_VV_MF4_MASK, PseudoVMINU_VV_MF4, 0x3, false }, // 1889 |
| 1898 | { PseudoVMINU_VV_MF8_MASK, PseudoVMINU_VV_MF8, 0x3, false }, // 1890 |
| 1899 | { PseudoVMINU_VX_M1_MASK, PseudoVMINU_VX_M1, 0x3, false }, // 1891 |
| 1900 | { PseudoVMINU_VX_M2_MASK, PseudoVMINU_VX_M2, 0x3, false }, // 1892 |
| 1901 | { PseudoVMINU_VX_M4_MASK, PseudoVMINU_VX_M4, 0x3, false }, // 1893 |
| 1902 | { PseudoVMINU_VX_M8_MASK, PseudoVMINU_VX_M8, 0x3, false }, // 1894 |
| 1903 | { PseudoVMINU_VX_MF2_MASK, PseudoVMINU_VX_MF2, 0x3, false }, // 1895 |
| 1904 | { PseudoVMINU_VX_MF4_MASK, PseudoVMINU_VX_MF4, 0x3, false }, // 1896 |
| 1905 | { PseudoVMINU_VX_MF8_MASK, PseudoVMINU_VX_MF8, 0x3, false }, // 1897 |
| 1906 | { PseudoVMIN_VV_M1_MASK, PseudoVMIN_VV_M1, 0x3, false }, // 1898 |
| 1907 | { PseudoVMIN_VV_M2_MASK, PseudoVMIN_VV_M2, 0x3, false }, // 1899 |
| 1908 | { PseudoVMIN_VV_M4_MASK, PseudoVMIN_VV_M4, 0x3, false }, // 1900 |
| 1909 | { PseudoVMIN_VV_M8_MASK, PseudoVMIN_VV_M8, 0x3, false }, // 1901 |
| 1910 | { PseudoVMIN_VV_MF2_MASK, PseudoVMIN_VV_MF2, 0x3, false }, // 1902 |
| 1911 | { PseudoVMIN_VV_MF4_MASK, PseudoVMIN_VV_MF4, 0x3, false }, // 1903 |
| 1912 | { PseudoVMIN_VV_MF8_MASK, PseudoVMIN_VV_MF8, 0x3, false }, // 1904 |
| 1913 | { PseudoVMIN_VX_M1_MASK, PseudoVMIN_VX_M1, 0x3, false }, // 1905 |
| 1914 | { PseudoVMIN_VX_M2_MASK, PseudoVMIN_VX_M2, 0x3, false }, // 1906 |
| 1915 | { PseudoVMIN_VX_M4_MASK, PseudoVMIN_VX_M4, 0x3, false }, // 1907 |
| 1916 | { PseudoVMIN_VX_M8_MASK, PseudoVMIN_VX_M8, 0x3, false }, // 1908 |
| 1917 | { PseudoVMIN_VX_MF2_MASK, PseudoVMIN_VX_MF2, 0x3, false }, // 1909 |
| 1918 | { PseudoVMIN_VX_MF4_MASK, PseudoVMIN_VX_MF4, 0x3, false }, // 1910 |
| 1919 | { PseudoVMIN_VX_MF8_MASK, PseudoVMIN_VX_MF8, 0x3, false }, // 1911 |
| 1920 | { PseudoVMSEQ_VI_M1_MASK, PseudoVMSEQ_VI_M1, 0x3, false }, // 1912 |
| 1921 | { PseudoVMSEQ_VI_M2_MASK, PseudoVMSEQ_VI_M2, 0x3, false }, // 1913 |
| 1922 | { PseudoVMSEQ_VI_M4_MASK, PseudoVMSEQ_VI_M4, 0x3, false }, // 1914 |
| 1923 | { PseudoVMSEQ_VI_M8_MASK, PseudoVMSEQ_VI_M8, 0x3, false }, // 1915 |
| 1924 | { PseudoVMSEQ_VI_MF2_MASK, PseudoVMSEQ_VI_MF2, 0x3, false }, // 1916 |
| 1925 | { PseudoVMSEQ_VI_MF4_MASK, PseudoVMSEQ_VI_MF4, 0x3, false }, // 1917 |
| 1926 | { PseudoVMSEQ_VI_MF8_MASK, PseudoVMSEQ_VI_MF8, 0x3, false }, // 1918 |
| 1927 | { PseudoVMSEQ_VV_M1_MASK, PseudoVMSEQ_VV_M1, 0x3, false }, // 1919 |
| 1928 | { PseudoVMSEQ_VV_M2_MASK, PseudoVMSEQ_VV_M2, 0x3, false }, // 1920 |
| 1929 | { PseudoVMSEQ_VV_M4_MASK, PseudoVMSEQ_VV_M4, 0x3, false }, // 1921 |
| 1930 | { PseudoVMSEQ_VV_M8_MASK, PseudoVMSEQ_VV_M8, 0x3, false }, // 1922 |
| 1931 | { PseudoVMSEQ_VV_MF2_MASK, PseudoVMSEQ_VV_MF2, 0x3, false }, // 1923 |
| 1932 | { PseudoVMSEQ_VV_MF4_MASK, PseudoVMSEQ_VV_MF4, 0x3, false }, // 1924 |
| 1933 | { PseudoVMSEQ_VV_MF8_MASK, PseudoVMSEQ_VV_MF8, 0x3, false }, // 1925 |
| 1934 | { PseudoVMSEQ_VX_M1_MASK, PseudoVMSEQ_VX_M1, 0x3, false }, // 1926 |
| 1935 | { PseudoVMSEQ_VX_M2_MASK, PseudoVMSEQ_VX_M2, 0x3, false }, // 1927 |
| 1936 | { PseudoVMSEQ_VX_M4_MASK, PseudoVMSEQ_VX_M4, 0x3, false }, // 1928 |
| 1937 | { PseudoVMSEQ_VX_M8_MASK, PseudoVMSEQ_VX_M8, 0x3, false }, // 1929 |
| 1938 | { PseudoVMSEQ_VX_MF2_MASK, PseudoVMSEQ_VX_MF2, 0x3, false }, // 1930 |
| 1939 | { PseudoVMSEQ_VX_MF4_MASK, PseudoVMSEQ_VX_MF4, 0x3, false }, // 1931 |
| 1940 | { PseudoVMSEQ_VX_MF8_MASK, PseudoVMSEQ_VX_MF8, 0x3, false }, // 1932 |
| 1941 | { PseudoVMSGTU_VI_M1_MASK, PseudoVMSGTU_VI_M1, 0x3, false }, // 1933 |
| 1942 | { PseudoVMSGTU_VI_M2_MASK, PseudoVMSGTU_VI_M2, 0x3, false }, // 1934 |
| 1943 | { PseudoVMSGTU_VI_M4_MASK, PseudoVMSGTU_VI_M4, 0x3, false }, // 1935 |
| 1944 | { PseudoVMSGTU_VI_M8_MASK, PseudoVMSGTU_VI_M8, 0x3, false }, // 1936 |
| 1945 | { PseudoVMSGTU_VI_MF2_MASK, PseudoVMSGTU_VI_MF2, 0x3, false }, // 1937 |
| 1946 | { PseudoVMSGTU_VI_MF4_MASK, PseudoVMSGTU_VI_MF4, 0x3, false }, // 1938 |
| 1947 | { PseudoVMSGTU_VI_MF8_MASK, PseudoVMSGTU_VI_MF8, 0x3, false }, // 1939 |
| 1948 | { PseudoVMSGTU_VX_M1_MASK, PseudoVMSGTU_VX_M1, 0x3, false }, // 1940 |
| 1949 | { PseudoVMSGTU_VX_M2_MASK, PseudoVMSGTU_VX_M2, 0x3, false }, // 1941 |
| 1950 | { PseudoVMSGTU_VX_M4_MASK, PseudoVMSGTU_VX_M4, 0x3, false }, // 1942 |
| 1951 | { PseudoVMSGTU_VX_M8_MASK, PseudoVMSGTU_VX_M8, 0x3, false }, // 1943 |
| 1952 | { PseudoVMSGTU_VX_MF2_MASK, PseudoVMSGTU_VX_MF2, 0x3, false }, // 1944 |
| 1953 | { PseudoVMSGTU_VX_MF4_MASK, PseudoVMSGTU_VX_MF4, 0x3, false }, // 1945 |
| 1954 | { PseudoVMSGTU_VX_MF8_MASK, PseudoVMSGTU_VX_MF8, 0x3, false }, // 1946 |
| 1955 | { PseudoVMSGT_VI_M1_MASK, PseudoVMSGT_VI_M1, 0x3, false }, // 1947 |
| 1956 | { PseudoVMSGT_VI_M2_MASK, PseudoVMSGT_VI_M2, 0x3, false }, // 1948 |
| 1957 | { PseudoVMSGT_VI_M4_MASK, PseudoVMSGT_VI_M4, 0x3, false }, // 1949 |
| 1958 | { PseudoVMSGT_VI_M8_MASK, PseudoVMSGT_VI_M8, 0x3, false }, // 1950 |
| 1959 | { PseudoVMSGT_VI_MF2_MASK, PseudoVMSGT_VI_MF2, 0x3, false }, // 1951 |
| 1960 | { PseudoVMSGT_VI_MF4_MASK, PseudoVMSGT_VI_MF4, 0x3, false }, // 1952 |
| 1961 | { PseudoVMSGT_VI_MF8_MASK, PseudoVMSGT_VI_MF8, 0x3, false }, // 1953 |
| 1962 | { PseudoVMSGT_VX_M1_MASK, PseudoVMSGT_VX_M1, 0x3, false }, // 1954 |
| 1963 | { PseudoVMSGT_VX_M2_MASK, PseudoVMSGT_VX_M2, 0x3, false }, // 1955 |
| 1964 | { PseudoVMSGT_VX_M4_MASK, PseudoVMSGT_VX_M4, 0x3, false }, // 1956 |
| 1965 | { PseudoVMSGT_VX_M8_MASK, PseudoVMSGT_VX_M8, 0x3, false }, // 1957 |
| 1966 | { PseudoVMSGT_VX_MF2_MASK, PseudoVMSGT_VX_MF2, 0x3, false }, // 1958 |
| 1967 | { PseudoVMSGT_VX_MF4_MASK, PseudoVMSGT_VX_MF4, 0x3, false }, // 1959 |
| 1968 | { PseudoVMSGT_VX_MF8_MASK, PseudoVMSGT_VX_MF8, 0x3, false }, // 1960 |
| 1969 | { PseudoVMSLEU_VI_M1_MASK, PseudoVMSLEU_VI_M1, 0x3, false }, // 1961 |
| 1970 | { PseudoVMSLEU_VI_M2_MASK, PseudoVMSLEU_VI_M2, 0x3, false }, // 1962 |
| 1971 | { PseudoVMSLEU_VI_M4_MASK, PseudoVMSLEU_VI_M4, 0x3, false }, // 1963 |
| 1972 | { PseudoVMSLEU_VI_M8_MASK, PseudoVMSLEU_VI_M8, 0x3, false }, // 1964 |
| 1973 | { PseudoVMSLEU_VI_MF2_MASK, PseudoVMSLEU_VI_MF2, 0x3, false }, // 1965 |
| 1974 | { PseudoVMSLEU_VI_MF4_MASK, PseudoVMSLEU_VI_MF4, 0x3, false }, // 1966 |
| 1975 | { PseudoVMSLEU_VI_MF8_MASK, PseudoVMSLEU_VI_MF8, 0x3, false }, // 1967 |
| 1976 | { PseudoVMSLEU_VV_M1_MASK, PseudoVMSLEU_VV_M1, 0x3, false }, // 1968 |
| 1977 | { PseudoVMSLEU_VV_M2_MASK, PseudoVMSLEU_VV_M2, 0x3, false }, // 1969 |
| 1978 | { PseudoVMSLEU_VV_M4_MASK, PseudoVMSLEU_VV_M4, 0x3, false }, // 1970 |
| 1979 | { PseudoVMSLEU_VV_M8_MASK, PseudoVMSLEU_VV_M8, 0x3, false }, // 1971 |
| 1980 | { PseudoVMSLEU_VV_MF2_MASK, PseudoVMSLEU_VV_MF2, 0x3, false }, // 1972 |
| 1981 | { PseudoVMSLEU_VV_MF4_MASK, PseudoVMSLEU_VV_MF4, 0x3, false }, // 1973 |
| 1982 | { PseudoVMSLEU_VV_MF8_MASK, PseudoVMSLEU_VV_MF8, 0x3, false }, // 1974 |
| 1983 | { PseudoVMSLEU_VX_M1_MASK, PseudoVMSLEU_VX_M1, 0x3, false }, // 1975 |
| 1984 | { PseudoVMSLEU_VX_M2_MASK, PseudoVMSLEU_VX_M2, 0x3, false }, // 1976 |
| 1985 | { PseudoVMSLEU_VX_M4_MASK, PseudoVMSLEU_VX_M4, 0x3, false }, // 1977 |
| 1986 | { PseudoVMSLEU_VX_M8_MASK, PseudoVMSLEU_VX_M8, 0x3, false }, // 1978 |
| 1987 | { PseudoVMSLEU_VX_MF2_MASK, PseudoVMSLEU_VX_MF2, 0x3, false }, // 1979 |
| 1988 | { PseudoVMSLEU_VX_MF4_MASK, PseudoVMSLEU_VX_MF4, 0x3, false }, // 1980 |
| 1989 | { PseudoVMSLEU_VX_MF8_MASK, PseudoVMSLEU_VX_MF8, 0x3, false }, // 1981 |
| 1990 | { PseudoVMSLE_VI_M1_MASK, PseudoVMSLE_VI_M1, 0x3, false }, // 1982 |
| 1991 | { PseudoVMSLE_VI_M2_MASK, PseudoVMSLE_VI_M2, 0x3, false }, // 1983 |
| 1992 | { PseudoVMSLE_VI_M4_MASK, PseudoVMSLE_VI_M4, 0x3, false }, // 1984 |
| 1993 | { PseudoVMSLE_VI_M8_MASK, PseudoVMSLE_VI_M8, 0x3, false }, // 1985 |
| 1994 | { PseudoVMSLE_VI_MF2_MASK, PseudoVMSLE_VI_MF2, 0x3, false }, // 1986 |
| 1995 | { PseudoVMSLE_VI_MF4_MASK, PseudoVMSLE_VI_MF4, 0x3, false }, // 1987 |
| 1996 | { PseudoVMSLE_VI_MF8_MASK, PseudoVMSLE_VI_MF8, 0x3, false }, // 1988 |
| 1997 | { PseudoVMSLE_VV_M1_MASK, PseudoVMSLE_VV_M1, 0x3, false }, // 1989 |
| 1998 | { PseudoVMSLE_VV_M2_MASK, PseudoVMSLE_VV_M2, 0x3, false }, // 1990 |
| 1999 | { PseudoVMSLE_VV_M4_MASK, PseudoVMSLE_VV_M4, 0x3, false }, // 1991 |
| 2000 | { PseudoVMSLE_VV_M8_MASK, PseudoVMSLE_VV_M8, 0x3, false }, // 1992 |
| 2001 | { PseudoVMSLE_VV_MF2_MASK, PseudoVMSLE_VV_MF2, 0x3, false }, // 1993 |
| 2002 | { PseudoVMSLE_VV_MF4_MASK, PseudoVMSLE_VV_MF4, 0x3, false }, // 1994 |
| 2003 | { PseudoVMSLE_VV_MF8_MASK, PseudoVMSLE_VV_MF8, 0x3, false }, // 1995 |
| 2004 | { PseudoVMSLE_VX_M1_MASK, PseudoVMSLE_VX_M1, 0x3, false }, // 1996 |
| 2005 | { PseudoVMSLE_VX_M2_MASK, PseudoVMSLE_VX_M2, 0x3, false }, // 1997 |
| 2006 | { PseudoVMSLE_VX_M4_MASK, PseudoVMSLE_VX_M4, 0x3, false }, // 1998 |
| 2007 | { PseudoVMSLE_VX_M8_MASK, PseudoVMSLE_VX_M8, 0x3, false }, // 1999 |
| 2008 | { PseudoVMSLE_VX_MF2_MASK, PseudoVMSLE_VX_MF2, 0x3, false }, // 2000 |
| 2009 | { PseudoVMSLE_VX_MF4_MASK, PseudoVMSLE_VX_MF4, 0x3, false }, // 2001 |
| 2010 | { PseudoVMSLE_VX_MF8_MASK, PseudoVMSLE_VX_MF8, 0x3, false }, // 2002 |
| 2011 | { PseudoVMSLTU_VV_M1_MASK, PseudoVMSLTU_VV_M1, 0x3, false }, // 2003 |
| 2012 | { PseudoVMSLTU_VV_M2_MASK, PseudoVMSLTU_VV_M2, 0x3, false }, // 2004 |
| 2013 | { PseudoVMSLTU_VV_M4_MASK, PseudoVMSLTU_VV_M4, 0x3, false }, // 2005 |
| 2014 | { PseudoVMSLTU_VV_M8_MASK, PseudoVMSLTU_VV_M8, 0x3, false }, // 2006 |
| 2015 | { PseudoVMSLTU_VV_MF2_MASK, PseudoVMSLTU_VV_MF2, 0x3, false }, // 2007 |
| 2016 | { PseudoVMSLTU_VV_MF4_MASK, PseudoVMSLTU_VV_MF4, 0x3, false }, // 2008 |
| 2017 | { PseudoVMSLTU_VV_MF8_MASK, PseudoVMSLTU_VV_MF8, 0x3, false }, // 2009 |
| 2018 | { PseudoVMSLTU_VX_M1_MASK, PseudoVMSLTU_VX_M1, 0x3, false }, // 2010 |
| 2019 | { PseudoVMSLTU_VX_M2_MASK, PseudoVMSLTU_VX_M2, 0x3, false }, // 2011 |
| 2020 | { PseudoVMSLTU_VX_M4_MASK, PseudoVMSLTU_VX_M4, 0x3, false }, // 2012 |
| 2021 | { PseudoVMSLTU_VX_M8_MASK, PseudoVMSLTU_VX_M8, 0x3, false }, // 2013 |
| 2022 | { PseudoVMSLTU_VX_MF2_MASK, PseudoVMSLTU_VX_MF2, 0x3, false }, // 2014 |
| 2023 | { PseudoVMSLTU_VX_MF4_MASK, PseudoVMSLTU_VX_MF4, 0x3, false }, // 2015 |
| 2024 | { PseudoVMSLTU_VX_MF8_MASK, PseudoVMSLTU_VX_MF8, 0x3, false }, // 2016 |
| 2025 | { PseudoVMSLT_VV_M1_MASK, PseudoVMSLT_VV_M1, 0x3, false }, // 2017 |
| 2026 | { PseudoVMSLT_VV_M2_MASK, PseudoVMSLT_VV_M2, 0x3, false }, // 2018 |
| 2027 | { PseudoVMSLT_VV_M4_MASK, PseudoVMSLT_VV_M4, 0x3, false }, // 2019 |
| 2028 | { PseudoVMSLT_VV_M8_MASK, PseudoVMSLT_VV_M8, 0x3, false }, // 2020 |
| 2029 | { PseudoVMSLT_VV_MF2_MASK, PseudoVMSLT_VV_MF2, 0x3, false }, // 2021 |
| 2030 | { PseudoVMSLT_VV_MF4_MASK, PseudoVMSLT_VV_MF4, 0x3, false }, // 2022 |
| 2031 | { PseudoVMSLT_VV_MF8_MASK, PseudoVMSLT_VV_MF8, 0x3, false }, // 2023 |
| 2032 | { PseudoVMSLT_VX_M1_MASK, PseudoVMSLT_VX_M1, 0x3, false }, // 2024 |
| 2033 | { PseudoVMSLT_VX_M2_MASK, PseudoVMSLT_VX_M2, 0x3, false }, // 2025 |
| 2034 | { PseudoVMSLT_VX_M4_MASK, PseudoVMSLT_VX_M4, 0x3, false }, // 2026 |
| 2035 | { PseudoVMSLT_VX_M8_MASK, PseudoVMSLT_VX_M8, 0x3, false }, // 2027 |
| 2036 | { PseudoVMSLT_VX_MF2_MASK, PseudoVMSLT_VX_MF2, 0x3, false }, // 2028 |
| 2037 | { PseudoVMSLT_VX_MF4_MASK, PseudoVMSLT_VX_MF4, 0x3, false }, // 2029 |
| 2038 | { PseudoVMSLT_VX_MF8_MASK, PseudoVMSLT_VX_MF8, 0x3, false }, // 2030 |
| 2039 | { PseudoVMSNE_VI_M1_MASK, PseudoVMSNE_VI_M1, 0x3, false }, // 2031 |
| 2040 | { PseudoVMSNE_VI_M2_MASK, PseudoVMSNE_VI_M2, 0x3, false }, // 2032 |
| 2041 | { PseudoVMSNE_VI_M4_MASK, PseudoVMSNE_VI_M4, 0x3, false }, // 2033 |
| 2042 | { PseudoVMSNE_VI_M8_MASK, PseudoVMSNE_VI_M8, 0x3, false }, // 2034 |
| 2043 | { PseudoVMSNE_VI_MF2_MASK, PseudoVMSNE_VI_MF2, 0x3, false }, // 2035 |
| 2044 | { PseudoVMSNE_VI_MF4_MASK, PseudoVMSNE_VI_MF4, 0x3, false }, // 2036 |
| 2045 | { PseudoVMSNE_VI_MF8_MASK, PseudoVMSNE_VI_MF8, 0x3, false }, // 2037 |
| 2046 | { PseudoVMSNE_VV_M1_MASK, PseudoVMSNE_VV_M1, 0x3, false }, // 2038 |
| 2047 | { PseudoVMSNE_VV_M2_MASK, PseudoVMSNE_VV_M2, 0x3, false }, // 2039 |
| 2048 | { PseudoVMSNE_VV_M4_MASK, PseudoVMSNE_VV_M4, 0x3, false }, // 2040 |
| 2049 | { PseudoVMSNE_VV_M8_MASK, PseudoVMSNE_VV_M8, 0x3, false }, // 2041 |
| 2050 | { PseudoVMSNE_VV_MF2_MASK, PseudoVMSNE_VV_MF2, 0x3, false }, // 2042 |
| 2051 | { PseudoVMSNE_VV_MF4_MASK, PseudoVMSNE_VV_MF4, 0x3, false }, // 2043 |
| 2052 | { PseudoVMSNE_VV_MF8_MASK, PseudoVMSNE_VV_MF8, 0x3, false }, // 2044 |
| 2053 | { PseudoVMSNE_VX_M1_MASK, PseudoVMSNE_VX_M1, 0x3, false }, // 2045 |
| 2054 | { PseudoVMSNE_VX_M2_MASK, PseudoVMSNE_VX_M2, 0x3, false }, // 2046 |
| 2055 | { PseudoVMSNE_VX_M4_MASK, PseudoVMSNE_VX_M4, 0x3, false }, // 2047 |
| 2056 | { PseudoVMSNE_VX_M8_MASK, PseudoVMSNE_VX_M8, 0x3, false }, // 2048 |
| 2057 | { PseudoVMSNE_VX_MF2_MASK, PseudoVMSNE_VX_MF2, 0x3, false }, // 2049 |
| 2058 | { PseudoVMSNE_VX_MF4_MASK, PseudoVMSNE_VX_MF4, 0x3, false }, // 2050 |
| 2059 | { PseudoVMSNE_VX_MF8_MASK, PseudoVMSNE_VX_MF8, 0x3, false }, // 2051 |
| 2060 | { PseudoVMULHSU_VV_M1_MASK, PseudoVMULHSU_VV_M1, 0x3, false }, // 2052 |
| 2061 | { PseudoVMULHSU_VV_M2_MASK, PseudoVMULHSU_VV_M2, 0x3, false }, // 2053 |
| 2062 | { PseudoVMULHSU_VV_M4_MASK, PseudoVMULHSU_VV_M4, 0x3, false }, // 2054 |
| 2063 | { PseudoVMULHSU_VV_M8_MASK, PseudoVMULHSU_VV_M8, 0x3, false }, // 2055 |
| 2064 | { PseudoVMULHSU_VV_MF2_MASK, PseudoVMULHSU_VV_MF2, 0x3, false }, // 2056 |
| 2065 | { PseudoVMULHSU_VV_MF4_MASK, PseudoVMULHSU_VV_MF4, 0x3, false }, // 2057 |
| 2066 | { PseudoVMULHSU_VV_MF8_MASK, PseudoVMULHSU_VV_MF8, 0x3, false }, // 2058 |
| 2067 | { PseudoVMULHSU_VX_M1_MASK, PseudoVMULHSU_VX_M1, 0x3, false }, // 2059 |
| 2068 | { PseudoVMULHSU_VX_M2_MASK, PseudoVMULHSU_VX_M2, 0x3, false }, // 2060 |
| 2069 | { PseudoVMULHSU_VX_M4_MASK, PseudoVMULHSU_VX_M4, 0x3, false }, // 2061 |
| 2070 | { PseudoVMULHSU_VX_M8_MASK, PseudoVMULHSU_VX_M8, 0x3, false }, // 2062 |
| 2071 | { PseudoVMULHSU_VX_MF2_MASK, PseudoVMULHSU_VX_MF2, 0x3, false }, // 2063 |
| 2072 | { PseudoVMULHSU_VX_MF4_MASK, PseudoVMULHSU_VX_MF4, 0x3, false }, // 2064 |
| 2073 | { PseudoVMULHSU_VX_MF8_MASK, PseudoVMULHSU_VX_MF8, 0x3, false }, // 2065 |
| 2074 | { PseudoVMULHU_VV_M1_MASK, PseudoVMULHU_VV_M1, 0x3, false }, // 2066 |
| 2075 | { PseudoVMULHU_VV_M2_MASK, PseudoVMULHU_VV_M2, 0x3, false }, // 2067 |
| 2076 | { PseudoVMULHU_VV_M4_MASK, PseudoVMULHU_VV_M4, 0x3, false }, // 2068 |
| 2077 | { PseudoVMULHU_VV_M8_MASK, PseudoVMULHU_VV_M8, 0x3, false }, // 2069 |
| 2078 | { PseudoVMULHU_VV_MF2_MASK, PseudoVMULHU_VV_MF2, 0x3, false }, // 2070 |
| 2079 | { PseudoVMULHU_VV_MF4_MASK, PseudoVMULHU_VV_MF4, 0x3, false }, // 2071 |
| 2080 | { PseudoVMULHU_VV_MF8_MASK, PseudoVMULHU_VV_MF8, 0x3, false }, // 2072 |
| 2081 | { PseudoVMULHU_VX_M1_MASK, PseudoVMULHU_VX_M1, 0x3, false }, // 2073 |
| 2082 | { PseudoVMULHU_VX_M2_MASK, PseudoVMULHU_VX_M2, 0x3, false }, // 2074 |
| 2083 | { PseudoVMULHU_VX_M4_MASK, PseudoVMULHU_VX_M4, 0x3, false }, // 2075 |
| 2084 | { PseudoVMULHU_VX_M8_MASK, PseudoVMULHU_VX_M8, 0x3, false }, // 2076 |
| 2085 | { PseudoVMULHU_VX_MF2_MASK, PseudoVMULHU_VX_MF2, 0x3, false }, // 2077 |
| 2086 | { PseudoVMULHU_VX_MF4_MASK, PseudoVMULHU_VX_MF4, 0x3, false }, // 2078 |
| 2087 | { PseudoVMULHU_VX_MF8_MASK, PseudoVMULHU_VX_MF8, 0x3, false }, // 2079 |
| 2088 | { PseudoVMULH_VV_M1_MASK, PseudoVMULH_VV_M1, 0x3, false }, // 2080 |
| 2089 | { PseudoVMULH_VV_M2_MASK, PseudoVMULH_VV_M2, 0x3, false }, // 2081 |
| 2090 | { PseudoVMULH_VV_M4_MASK, PseudoVMULH_VV_M4, 0x3, false }, // 2082 |
| 2091 | { PseudoVMULH_VV_M8_MASK, PseudoVMULH_VV_M8, 0x3, false }, // 2083 |
| 2092 | { PseudoVMULH_VV_MF2_MASK, PseudoVMULH_VV_MF2, 0x3, false }, // 2084 |
| 2093 | { PseudoVMULH_VV_MF4_MASK, PseudoVMULH_VV_MF4, 0x3, false }, // 2085 |
| 2094 | { PseudoVMULH_VV_MF8_MASK, PseudoVMULH_VV_MF8, 0x3, false }, // 2086 |
| 2095 | { PseudoVMULH_VX_M1_MASK, PseudoVMULH_VX_M1, 0x3, false }, // 2087 |
| 2096 | { PseudoVMULH_VX_M2_MASK, PseudoVMULH_VX_M2, 0x3, false }, // 2088 |
| 2097 | { PseudoVMULH_VX_M4_MASK, PseudoVMULH_VX_M4, 0x3, false }, // 2089 |
| 2098 | { PseudoVMULH_VX_M8_MASK, PseudoVMULH_VX_M8, 0x3, false }, // 2090 |
| 2099 | { PseudoVMULH_VX_MF2_MASK, PseudoVMULH_VX_MF2, 0x3, false }, // 2091 |
| 2100 | { PseudoVMULH_VX_MF4_MASK, PseudoVMULH_VX_MF4, 0x3, false }, // 2092 |
| 2101 | { PseudoVMULH_VX_MF8_MASK, PseudoVMULH_VX_MF8, 0x3, false }, // 2093 |
| 2102 | { PseudoVMUL_VV_M1_MASK, PseudoVMUL_VV_M1, 0x3, false }, // 2094 |
| 2103 | { PseudoVMUL_VV_M2_MASK, PseudoVMUL_VV_M2, 0x3, false }, // 2095 |
| 2104 | { PseudoVMUL_VV_M4_MASK, PseudoVMUL_VV_M4, 0x3, false }, // 2096 |
| 2105 | { PseudoVMUL_VV_M8_MASK, PseudoVMUL_VV_M8, 0x3, false }, // 2097 |
| 2106 | { PseudoVMUL_VV_MF2_MASK, PseudoVMUL_VV_MF2, 0x3, false }, // 2098 |
| 2107 | { PseudoVMUL_VV_MF4_MASK, PseudoVMUL_VV_MF4, 0x3, false }, // 2099 |
| 2108 | { PseudoVMUL_VV_MF8_MASK, PseudoVMUL_VV_MF8, 0x3, false }, // 2100 |
| 2109 | { PseudoVMUL_VX_M1_MASK, PseudoVMUL_VX_M1, 0x3, false }, // 2101 |
| 2110 | { PseudoVMUL_VX_M2_MASK, PseudoVMUL_VX_M2, 0x3, false }, // 2102 |
| 2111 | { PseudoVMUL_VX_M4_MASK, PseudoVMUL_VX_M4, 0x3, false }, // 2103 |
| 2112 | { PseudoVMUL_VX_M8_MASK, PseudoVMUL_VX_M8, 0x3, false }, // 2104 |
| 2113 | { PseudoVMUL_VX_MF2_MASK, PseudoVMUL_VX_MF2, 0x3, false }, // 2105 |
| 2114 | { PseudoVMUL_VX_MF4_MASK, PseudoVMUL_VX_MF4, 0x3, false }, // 2106 |
| 2115 | { PseudoVMUL_VX_MF8_MASK, PseudoVMUL_VX_MF8, 0x3, false }, // 2107 |
| 2116 | { PseudoVNCLIPU_WI_M1_MASK, PseudoVNCLIPU_WI_M1, 0x3, false }, // 2108 |
| 2117 | { PseudoVNCLIPU_WI_M2_MASK, PseudoVNCLIPU_WI_M2, 0x3, false }, // 2109 |
| 2118 | { PseudoVNCLIPU_WI_M4_MASK, PseudoVNCLIPU_WI_M4, 0x3, false }, // 2110 |
| 2119 | { PseudoVNCLIPU_WI_MF2_MASK, PseudoVNCLIPU_WI_MF2, 0x3, false }, // 2111 |
| 2120 | { PseudoVNCLIPU_WI_MF4_MASK, PseudoVNCLIPU_WI_MF4, 0x3, false }, // 2112 |
| 2121 | { PseudoVNCLIPU_WI_MF8_MASK, PseudoVNCLIPU_WI_MF8, 0x3, false }, // 2113 |
| 2122 | { PseudoVNCLIPU_WV_M1_MASK, PseudoVNCLIPU_WV_M1, 0x3, false }, // 2114 |
| 2123 | { PseudoVNCLIPU_WV_M2_MASK, PseudoVNCLIPU_WV_M2, 0x3, false }, // 2115 |
| 2124 | { PseudoVNCLIPU_WV_M4_MASK, PseudoVNCLIPU_WV_M4, 0x3, false }, // 2116 |
| 2125 | { PseudoVNCLIPU_WV_MF2_MASK, PseudoVNCLIPU_WV_MF2, 0x3, false }, // 2117 |
| 2126 | { PseudoVNCLIPU_WV_MF4_MASK, PseudoVNCLIPU_WV_MF4, 0x3, false }, // 2118 |
| 2127 | { PseudoVNCLIPU_WV_MF8_MASK, PseudoVNCLIPU_WV_MF8, 0x3, false }, // 2119 |
| 2128 | { PseudoVNCLIPU_WX_M1_MASK, PseudoVNCLIPU_WX_M1, 0x3, false }, // 2120 |
| 2129 | { PseudoVNCLIPU_WX_M2_MASK, PseudoVNCLIPU_WX_M2, 0x3, false }, // 2121 |
| 2130 | { PseudoVNCLIPU_WX_M4_MASK, PseudoVNCLIPU_WX_M4, 0x3, false }, // 2122 |
| 2131 | { PseudoVNCLIPU_WX_MF2_MASK, PseudoVNCLIPU_WX_MF2, 0x3, false }, // 2123 |
| 2132 | { PseudoVNCLIPU_WX_MF4_MASK, PseudoVNCLIPU_WX_MF4, 0x3, false }, // 2124 |
| 2133 | { PseudoVNCLIPU_WX_MF8_MASK, PseudoVNCLIPU_WX_MF8, 0x3, false }, // 2125 |
| 2134 | { PseudoVNCLIP_WI_M1_MASK, PseudoVNCLIP_WI_M1, 0x3, false }, // 2126 |
| 2135 | { PseudoVNCLIP_WI_M2_MASK, PseudoVNCLIP_WI_M2, 0x3, false }, // 2127 |
| 2136 | { PseudoVNCLIP_WI_M4_MASK, PseudoVNCLIP_WI_M4, 0x3, false }, // 2128 |
| 2137 | { PseudoVNCLIP_WI_MF2_MASK, PseudoVNCLIP_WI_MF2, 0x3, false }, // 2129 |
| 2138 | { PseudoVNCLIP_WI_MF4_MASK, PseudoVNCLIP_WI_MF4, 0x3, false }, // 2130 |
| 2139 | { PseudoVNCLIP_WI_MF8_MASK, PseudoVNCLIP_WI_MF8, 0x3, false }, // 2131 |
| 2140 | { PseudoVNCLIP_WV_M1_MASK, PseudoVNCLIP_WV_M1, 0x3, false }, // 2132 |
| 2141 | { PseudoVNCLIP_WV_M2_MASK, PseudoVNCLIP_WV_M2, 0x3, false }, // 2133 |
| 2142 | { PseudoVNCLIP_WV_M4_MASK, PseudoVNCLIP_WV_M4, 0x3, false }, // 2134 |
| 2143 | { PseudoVNCLIP_WV_MF2_MASK, PseudoVNCLIP_WV_MF2, 0x3, false }, // 2135 |
| 2144 | { PseudoVNCLIP_WV_MF4_MASK, PseudoVNCLIP_WV_MF4, 0x3, false }, // 2136 |
| 2145 | { PseudoVNCLIP_WV_MF8_MASK, PseudoVNCLIP_WV_MF8, 0x3, false }, // 2137 |
| 2146 | { PseudoVNCLIP_WX_M1_MASK, PseudoVNCLIP_WX_M1, 0x3, false }, // 2138 |
| 2147 | { PseudoVNCLIP_WX_M2_MASK, PseudoVNCLIP_WX_M2, 0x3, false }, // 2139 |
| 2148 | { PseudoVNCLIP_WX_M4_MASK, PseudoVNCLIP_WX_M4, 0x3, false }, // 2140 |
| 2149 | { PseudoVNCLIP_WX_MF2_MASK, PseudoVNCLIP_WX_MF2, 0x3, false }, // 2141 |
| 2150 | { PseudoVNCLIP_WX_MF4_MASK, PseudoVNCLIP_WX_MF4, 0x3, false }, // 2142 |
| 2151 | { PseudoVNCLIP_WX_MF8_MASK, PseudoVNCLIP_WX_MF8, 0x3, false }, // 2143 |
| 2152 | { PseudoVNMSAC_VV_M1_MASK, PseudoVNMSAC_VV_M1, 0x3, false }, // 2144 |
| 2153 | { PseudoVNMSAC_VV_M2_MASK, PseudoVNMSAC_VV_M2, 0x3, false }, // 2145 |
| 2154 | { PseudoVNMSAC_VV_M4_MASK, PseudoVNMSAC_VV_M4, 0x3, false }, // 2146 |
| 2155 | { PseudoVNMSAC_VV_M8_MASK, PseudoVNMSAC_VV_M8, 0x3, false }, // 2147 |
| 2156 | { PseudoVNMSAC_VV_MF2_MASK, PseudoVNMSAC_VV_MF2, 0x3, false }, // 2148 |
| 2157 | { PseudoVNMSAC_VV_MF4_MASK, PseudoVNMSAC_VV_MF4, 0x3, false }, // 2149 |
| 2158 | { PseudoVNMSAC_VV_MF8_MASK, PseudoVNMSAC_VV_MF8, 0x3, false }, // 2150 |
| 2159 | { PseudoVNMSAC_VX_M1_MASK, PseudoVNMSAC_VX_M1, 0x3, false }, // 2151 |
| 2160 | { PseudoVNMSAC_VX_M2_MASK, PseudoVNMSAC_VX_M2, 0x3, false }, // 2152 |
| 2161 | { PseudoVNMSAC_VX_M4_MASK, PseudoVNMSAC_VX_M4, 0x3, false }, // 2153 |
| 2162 | { PseudoVNMSAC_VX_M8_MASK, PseudoVNMSAC_VX_M8, 0x3, false }, // 2154 |
| 2163 | { PseudoVNMSAC_VX_MF2_MASK, PseudoVNMSAC_VX_MF2, 0x3, false }, // 2155 |
| 2164 | { PseudoVNMSAC_VX_MF4_MASK, PseudoVNMSAC_VX_MF4, 0x3, false }, // 2156 |
| 2165 | { PseudoVNMSAC_VX_MF8_MASK, PseudoVNMSAC_VX_MF8, 0x3, false }, // 2157 |
| 2166 | { PseudoVNMSUB_VV_M1_MASK, PseudoVNMSUB_VV_M1, 0x3, false }, // 2158 |
| 2167 | { PseudoVNMSUB_VV_M2_MASK, PseudoVNMSUB_VV_M2, 0x3, false }, // 2159 |
| 2168 | { PseudoVNMSUB_VV_M4_MASK, PseudoVNMSUB_VV_M4, 0x3, false }, // 2160 |
| 2169 | { PseudoVNMSUB_VV_M8_MASK, PseudoVNMSUB_VV_M8, 0x3, false }, // 2161 |
| 2170 | { PseudoVNMSUB_VV_MF2_MASK, PseudoVNMSUB_VV_MF2, 0x3, false }, // 2162 |
| 2171 | { PseudoVNMSUB_VV_MF4_MASK, PseudoVNMSUB_VV_MF4, 0x3, false }, // 2163 |
| 2172 | { PseudoVNMSUB_VV_MF8_MASK, PseudoVNMSUB_VV_MF8, 0x3, false }, // 2164 |
| 2173 | { PseudoVNMSUB_VX_M1_MASK, PseudoVNMSUB_VX_M1, 0x3, false }, // 2165 |
| 2174 | { PseudoVNMSUB_VX_M2_MASK, PseudoVNMSUB_VX_M2, 0x3, false }, // 2166 |
| 2175 | { PseudoVNMSUB_VX_M4_MASK, PseudoVNMSUB_VX_M4, 0x3, false }, // 2167 |
| 2176 | { PseudoVNMSUB_VX_M8_MASK, PseudoVNMSUB_VX_M8, 0x3, false }, // 2168 |
| 2177 | { PseudoVNMSUB_VX_MF2_MASK, PseudoVNMSUB_VX_MF2, 0x3, false }, // 2169 |
| 2178 | { PseudoVNMSUB_VX_MF4_MASK, PseudoVNMSUB_VX_MF4, 0x3, false }, // 2170 |
| 2179 | { PseudoVNMSUB_VX_MF8_MASK, PseudoVNMSUB_VX_MF8, 0x3, false }, // 2171 |
| 2180 | { PseudoVNSRA_WI_M1_MASK, PseudoVNSRA_WI_M1, 0x3, false }, // 2172 |
| 2181 | { PseudoVNSRA_WI_M2_MASK, PseudoVNSRA_WI_M2, 0x3, false }, // 2173 |
| 2182 | { PseudoVNSRA_WI_M4_MASK, PseudoVNSRA_WI_M4, 0x3, false }, // 2174 |
| 2183 | { PseudoVNSRA_WI_MF2_MASK, PseudoVNSRA_WI_MF2, 0x3, false }, // 2175 |
| 2184 | { PseudoVNSRA_WI_MF4_MASK, PseudoVNSRA_WI_MF4, 0x3, false }, // 2176 |
| 2185 | { PseudoVNSRA_WI_MF8_MASK, PseudoVNSRA_WI_MF8, 0x3, false }, // 2177 |
| 2186 | { PseudoVNSRA_WV_M1_MASK, PseudoVNSRA_WV_M1, 0x3, false }, // 2178 |
| 2187 | { PseudoVNSRA_WV_M2_MASK, PseudoVNSRA_WV_M2, 0x3, false }, // 2179 |
| 2188 | { PseudoVNSRA_WV_M4_MASK, PseudoVNSRA_WV_M4, 0x3, false }, // 2180 |
| 2189 | { PseudoVNSRA_WV_MF2_MASK, PseudoVNSRA_WV_MF2, 0x3, false }, // 2181 |
| 2190 | { PseudoVNSRA_WV_MF4_MASK, PseudoVNSRA_WV_MF4, 0x3, false }, // 2182 |
| 2191 | { PseudoVNSRA_WV_MF8_MASK, PseudoVNSRA_WV_MF8, 0x3, false }, // 2183 |
| 2192 | { PseudoVNSRA_WX_M1_MASK, PseudoVNSRA_WX_M1, 0x3, false }, // 2184 |
| 2193 | { PseudoVNSRA_WX_M2_MASK, PseudoVNSRA_WX_M2, 0x3, false }, // 2185 |
| 2194 | { PseudoVNSRA_WX_M4_MASK, PseudoVNSRA_WX_M4, 0x3, false }, // 2186 |
| 2195 | { PseudoVNSRA_WX_MF2_MASK, PseudoVNSRA_WX_MF2, 0x3, false }, // 2187 |
| 2196 | { PseudoVNSRA_WX_MF4_MASK, PseudoVNSRA_WX_MF4, 0x3, false }, // 2188 |
| 2197 | { PseudoVNSRA_WX_MF8_MASK, PseudoVNSRA_WX_MF8, 0x3, false }, // 2189 |
| 2198 | { PseudoVNSRL_WI_M1_MASK, PseudoVNSRL_WI_M1, 0x3, false }, // 2190 |
| 2199 | { PseudoVNSRL_WI_M2_MASK, PseudoVNSRL_WI_M2, 0x3, false }, // 2191 |
| 2200 | { PseudoVNSRL_WI_M4_MASK, PseudoVNSRL_WI_M4, 0x3, false }, // 2192 |
| 2201 | { PseudoVNSRL_WI_MF2_MASK, PseudoVNSRL_WI_MF2, 0x3, false }, // 2193 |
| 2202 | { PseudoVNSRL_WI_MF4_MASK, PseudoVNSRL_WI_MF4, 0x3, false }, // 2194 |
| 2203 | { PseudoVNSRL_WI_MF8_MASK, PseudoVNSRL_WI_MF8, 0x3, false }, // 2195 |
| 2204 | { PseudoVNSRL_WV_M1_MASK, PseudoVNSRL_WV_M1, 0x3, false }, // 2196 |
| 2205 | { PseudoVNSRL_WV_M2_MASK, PseudoVNSRL_WV_M2, 0x3, false }, // 2197 |
| 2206 | { PseudoVNSRL_WV_M4_MASK, PseudoVNSRL_WV_M4, 0x3, false }, // 2198 |
| 2207 | { PseudoVNSRL_WV_MF2_MASK, PseudoVNSRL_WV_MF2, 0x3, false }, // 2199 |
| 2208 | { PseudoVNSRL_WV_MF4_MASK, PseudoVNSRL_WV_MF4, 0x3, false }, // 2200 |
| 2209 | { PseudoVNSRL_WV_MF8_MASK, PseudoVNSRL_WV_MF8, 0x3, false }, // 2201 |
| 2210 | { PseudoVNSRL_WX_M1_MASK, PseudoVNSRL_WX_M1, 0x3, false }, // 2202 |
| 2211 | { PseudoVNSRL_WX_M2_MASK, PseudoVNSRL_WX_M2, 0x3, false }, // 2203 |
| 2212 | { PseudoVNSRL_WX_M4_MASK, PseudoVNSRL_WX_M4, 0x3, false }, // 2204 |
| 2213 | { PseudoVNSRL_WX_MF2_MASK, PseudoVNSRL_WX_MF2, 0x3, false }, // 2205 |
| 2214 | { PseudoVNSRL_WX_MF4_MASK, PseudoVNSRL_WX_MF4, 0x3, false }, // 2206 |
| 2215 | { PseudoVNSRL_WX_MF8_MASK, PseudoVNSRL_WX_MF8, 0x3, false }, // 2207 |
| 2216 | { PseudoVOR_VI_M1_MASK, PseudoVOR_VI_M1, 0x3, false }, // 2208 |
| 2217 | { PseudoVOR_VI_M2_MASK, PseudoVOR_VI_M2, 0x3, false }, // 2209 |
| 2218 | { PseudoVOR_VI_M4_MASK, PseudoVOR_VI_M4, 0x3, false }, // 2210 |
| 2219 | { PseudoVOR_VI_M8_MASK, PseudoVOR_VI_M8, 0x3, false }, // 2211 |
| 2220 | { PseudoVOR_VI_MF2_MASK, PseudoVOR_VI_MF2, 0x3, false }, // 2212 |
| 2221 | { PseudoVOR_VI_MF4_MASK, PseudoVOR_VI_MF4, 0x3, false }, // 2213 |
| 2222 | { PseudoVOR_VI_MF8_MASK, PseudoVOR_VI_MF8, 0x3, false }, // 2214 |
| 2223 | { PseudoVOR_VV_M1_MASK, PseudoVOR_VV_M1, 0x3, false }, // 2215 |
| 2224 | { PseudoVOR_VV_M2_MASK, PseudoVOR_VV_M2, 0x3, false }, // 2216 |
| 2225 | { PseudoVOR_VV_M4_MASK, PseudoVOR_VV_M4, 0x3, false }, // 2217 |
| 2226 | { PseudoVOR_VV_M8_MASK, PseudoVOR_VV_M8, 0x3, false }, // 2218 |
| 2227 | { PseudoVOR_VV_MF2_MASK, PseudoVOR_VV_MF2, 0x3, false }, // 2219 |
| 2228 | { PseudoVOR_VV_MF4_MASK, PseudoVOR_VV_MF4, 0x3, false }, // 2220 |
| 2229 | { PseudoVOR_VV_MF8_MASK, PseudoVOR_VV_MF8, 0x3, false }, // 2221 |
| 2230 | { PseudoVOR_VX_M1_MASK, PseudoVOR_VX_M1, 0x3, false }, // 2222 |
| 2231 | { PseudoVOR_VX_M2_MASK, PseudoVOR_VX_M2, 0x3, false }, // 2223 |
| 2232 | { PseudoVOR_VX_M4_MASK, PseudoVOR_VX_M4, 0x3, false }, // 2224 |
| 2233 | { PseudoVOR_VX_M8_MASK, PseudoVOR_VX_M8, 0x3, false }, // 2225 |
| 2234 | { PseudoVOR_VX_MF2_MASK, PseudoVOR_VX_MF2, 0x3, false }, // 2226 |
| 2235 | { PseudoVOR_VX_MF4_MASK, PseudoVOR_VX_MF4, 0x3, false }, // 2227 |
| 2236 | { PseudoVOR_VX_MF8_MASK, PseudoVOR_VX_MF8, 0x3, false }, // 2228 |
| 2237 | { PseudoVREDAND_VS_M1_E16_MASK, PseudoVREDAND_VS_M1_E16, 0x3, true }, // 2229 |
| 2238 | { PseudoVREDAND_VS_M1_E32_MASK, PseudoVREDAND_VS_M1_E32, 0x3, true }, // 2230 |
| 2239 | { PseudoVREDAND_VS_M1_E64_MASK, PseudoVREDAND_VS_M1_E64, 0x3, true }, // 2231 |
| 2240 | { PseudoVREDAND_VS_M1_E8_MASK, PseudoVREDAND_VS_M1_E8, 0x3, true }, // 2232 |
| 2241 | { PseudoVREDAND_VS_M2_E16_MASK, PseudoVREDAND_VS_M2_E16, 0x3, true }, // 2233 |
| 2242 | { PseudoVREDAND_VS_M2_E32_MASK, PseudoVREDAND_VS_M2_E32, 0x3, true }, // 2234 |
| 2243 | { PseudoVREDAND_VS_M2_E64_MASK, PseudoVREDAND_VS_M2_E64, 0x3, true }, // 2235 |
| 2244 | { PseudoVREDAND_VS_M2_E8_MASK, PseudoVREDAND_VS_M2_E8, 0x3, true }, // 2236 |
| 2245 | { PseudoVREDAND_VS_M4_E16_MASK, PseudoVREDAND_VS_M4_E16, 0x3, true }, // 2237 |
| 2246 | { PseudoVREDAND_VS_M4_E32_MASK, PseudoVREDAND_VS_M4_E32, 0x3, true }, // 2238 |
| 2247 | { PseudoVREDAND_VS_M4_E64_MASK, PseudoVREDAND_VS_M4_E64, 0x3, true }, // 2239 |
| 2248 | { PseudoVREDAND_VS_M4_E8_MASK, PseudoVREDAND_VS_M4_E8, 0x3, true }, // 2240 |
| 2249 | { PseudoVREDAND_VS_M8_E16_MASK, PseudoVREDAND_VS_M8_E16, 0x3, true }, // 2241 |
| 2250 | { PseudoVREDAND_VS_M8_E32_MASK, PseudoVREDAND_VS_M8_E32, 0x3, true }, // 2242 |
| 2251 | { PseudoVREDAND_VS_M8_E64_MASK, PseudoVREDAND_VS_M8_E64, 0x3, true }, // 2243 |
| 2252 | { PseudoVREDAND_VS_M8_E8_MASK, PseudoVREDAND_VS_M8_E8, 0x3, true }, // 2244 |
| 2253 | { PseudoVREDAND_VS_MF2_E16_MASK, PseudoVREDAND_VS_MF2_E16, 0x3, true }, // 2245 |
| 2254 | { PseudoVREDAND_VS_MF2_E32_MASK, PseudoVREDAND_VS_MF2_E32, 0x3, true }, // 2246 |
| 2255 | { PseudoVREDAND_VS_MF2_E8_MASK, PseudoVREDAND_VS_MF2_E8, 0x3, true }, // 2247 |
| 2256 | { PseudoVREDAND_VS_MF4_E16_MASK, PseudoVREDAND_VS_MF4_E16, 0x3, true }, // 2248 |
| 2257 | { PseudoVREDAND_VS_MF4_E8_MASK, PseudoVREDAND_VS_MF4_E8, 0x3, true }, // 2249 |
| 2258 | { PseudoVREDAND_VS_MF8_E8_MASK, PseudoVREDAND_VS_MF8_E8, 0x3, true }, // 2250 |
| 2259 | { PseudoVREDMAXU_VS_M1_E16_MASK, PseudoVREDMAXU_VS_M1_E16, 0x3, true }, // 2251 |
| 2260 | { PseudoVREDMAXU_VS_M1_E32_MASK, PseudoVREDMAXU_VS_M1_E32, 0x3, true }, // 2252 |
| 2261 | { PseudoVREDMAXU_VS_M1_E64_MASK, PseudoVREDMAXU_VS_M1_E64, 0x3, true }, // 2253 |
| 2262 | { PseudoVREDMAXU_VS_M1_E8_MASK, PseudoVREDMAXU_VS_M1_E8, 0x3, true }, // 2254 |
| 2263 | { PseudoVREDMAXU_VS_M2_E16_MASK, PseudoVREDMAXU_VS_M2_E16, 0x3, true }, // 2255 |
| 2264 | { PseudoVREDMAXU_VS_M2_E32_MASK, PseudoVREDMAXU_VS_M2_E32, 0x3, true }, // 2256 |
| 2265 | { PseudoVREDMAXU_VS_M2_E64_MASK, PseudoVREDMAXU_VS_M2_E64, 0x3, true }, // 2257 |
| 2266 | { PseudoVREDMAXU_VS_M2_E8_MASK, PseudoVREDMAXU_VS_M2_E8, 0x3, true }, // 2258 |
| 2267 | { PseudoVREDMAXU_VS_M4_E16_MASK, PseudoVREDMAXU_VS_M4_E16, 0x3, true }, // 2259 |
| 2268 | { PseudoVREDMAXU_VS_M4_E32_MASK, PseudoVREDMAXU_VS_M4_E32, 0x3, true }, // 2260 |
| 2269 | { PseudoVREDMAXU_VS_M4_E64_MASK, PseudoVREDMAXU_VS_M4_E64, 0x3, true }, // 2261 |
| 2270 | { PseudoVREDMAXU_VS_M4_E8_MASK, PseudoVREDMAXU_VS_M4_E8, 0x3, true }, // 2262 |
| 2271 | { PseudoVREDMAXU_VS_M8_E16_MASK, PseudoVREDMAXU_VS_M8_E16, 0x3, true }, // 2263 |
| 2272 | { PseudoVREDMAXU_VS_M8_E32_MASK, PseudoVREDMAXU_VS_M8_E32, 0x3, true }, // 2264 |
| 2273 | { PseudoVREDMAXU_VS_M8_E64_MASK, PseudoVREDMAXU_VS_M8_E64, 0x3, true }, // 2265 |
| 2274 | { PseudoVREDMAXU_VS_M8_E8_MASK, PseudoVREDMAXU_VS_M8_E8, 0x3, true }, // 2266 |
| 2275 | { PseudoVREDMAXU_VS_MF2_E16_MASK, PseudoVREDMAXU_VS_MF2_E16, 0x3, true }, // 2267 |
| 2276 | { PseudoVREDMAXU_VS_MF2_E32_MASK, PseudoVREDMAXU_VS_MF2_E32, 0x3, true }, // 2268 |
| 2277 | { PseudoVREDMAXU_VS_MF2_E8_MASK, PseudoVREDMAXU_VS_MF2_E8, 0x3, true }, // 2269 |
| 2278 | { PseudoVREDMAXU_VS_MF4_E16_MASK, PseudoVREDMAXU_VS_MF4_E16, 0x3, true }, // 2270 |
| 2279 | { PseudoVREDMAXU_VS_MF4_E8_MASK, PseudoVREDMAXU_VS_MF4_E8, 0x3, true }, // 2271 |
| 2280 | { PseudoVREDMAXU_VS_MF8_E8_MASK, PseudoVREDMAXU_VS_MF8_E8, 0x3, true }, // 2272 |
| 2281 | { PseudoVREDMAX_VS_M1_E16_MASK, PseudoVREDMAX_VS_M1_E16, 0x3, true }, // 2273 |
| 2282 | { PseudoVREDMAX_VS_M1_E32_MASK, PseudoVREDMAX_VS_M1_E32, 0x3, true }, // 2274 |
| 2283 | { PseudoVREDMAX_VS_M1_E64_MASK, PseudoVREDMAX_VS_M1_E64, 0x3, true }, // 2275 |
| 2284 | { PseudoVREDMAX_VS_M1_E8_MASK, PseudoVREDMAX_VS_M1_E8, 0x3, true }, // 2276 |
| 2285 | { PseudoVREDMAX_VS_M2_E16_MASK, PseudoVREDMAX_VS_M2_E16, 0x3, true }, // 2277 |
| 2286 | { PseudoVREDMAX_VS_M2_E32_MASK, PseudoVREDMAX_VS_M2_E32, 0x3, true }, // 2278 |
| 2287 | { PseudoVREDMAX_VS_M2_E64_MASK, PseudoVREDMAX_VS_M2_E64, 0x3, true }, // 2279 |
| 2288 | { PseudoVREDMAX_VS_M2_E8_MASK, PseudoVREDMAX_VS_M2_E8, 0x3, true }, // 2280 |
| 2289 | { PseudoVREDMAX_VS_M4_E16_MASK, PseudoVREDMAX_VS_M4_E16, 0x3, true }, // 2281 |
| 2290 | { PseudoVREDMAX_VS_M4_E32_MASK, PseudoVREDMAX_VS_M4_E32, 0x3, true }, // 2282 |
| 2291 | { PseudoVREDMAX_VS_M4_E64_MASK, PseudoVREDMAX_VS_M4_E64, 0x3, true }, // 2283 |
| 2292 | { PseudoVREDMAX_VS_M4_E8_MASK, PseudoVREDMAX_VS_M4_E8, 0x3, true }, // 2284 |
| 2293 | { PseudoVREDMAX_VS_M8_E16_MASK, PseudoVREDMAX_VS_M8_E16, 0x3, true }, // 2285 |
| 2294 | { PseudoVREDMAX_VS_M8_E32_MASK, PseudoVREDMAX_VS_M8_E32, 0x3, true }, // 2286 |
| 2295 | { PseudoVREDMAX_VS_M8_E64_MASK, PseudoVREDMAX_VS_M8_E64, 0x3, true }, // 2287 |
| 2296 | { PseudoVREDMAX_VS_M8_E8_MASK, PseudoVREDMAX_VS_M8_E8, 0x3, true }, // 2288 |
| 2297 | { PseudoVREDMAX_VS_MF2_E16_MASK, PseudoVREDMAX_VS_MF2_E16, 0x3, true }, // 2289 |
| 2298 | { PseudoVREDMAX_VS_MF2_E32_MASK, PseudoVREDMAX_VS_MF2_E32, 0x3, true }, // 2290 |
| 2299 | { PseudoVREDMAX_VS_MF2_E8_MASK, PseudoVREDMAX_VS_MF2_E8, 0x3, true }, // 2291 |
| 2300 | { PseudoVREDMAX_VS_MF4_E16_MASK, PseudoVREDMAX_VS_MF4_E16, 0x3, true }, // 2292 |
| 2301 | { PseudoVREDMAX_VS_MF4_E8_MASK, PseudoVREDMAX_VS_MF4_E8, 0x3, true }, // 2293 |
| 2302 | { PseudoVREDMAX_VS_MF8_E8_MASK, PseudoVREDMAX_VS_MF8_E8, 0x3, true }, // 2294 |
| 2303 | { PseudoVREDMINU_VS_M1_E16_MASK, PseudoVREDMINU_VS_M1_E16, 0x3, true }, // 2295 |
| 2304 | { PseudoVREDMINU_VS_M1_E32_MASK, PseudoVREDMINU_VS_M1_E32, 0x3, true }, // 2296 |
| 2305 | { PseudoVREDMINU_VS_M1_E64_MASK, PseudoVREDMINU_VS_M1_E64, 0x3, true }, // 2297 |
| 2306 | { PseudoVREDMINU_VS_M1_E8_MASK, PseudoVREDMINU_VS_M1_E8, 0x3, true }, // 2298 |
| 2307 | { PseudoVREDMINU_VS_M2_E16_MASK, PseudoVREDMINU_VS_M2_E16, 0x3, true }, // 2299 |
| 2308 | { PseudoVREDMINU_VS_M2_E32_MASK, PseudoVREDMINU_VS_M2_E32, 0x3, true }, // 2300 |
| 2309 | { PseudoVREDMINU_VS_M2_E64_MASK, PseudoVREDMINU_VS_M2_E64, 0x3, true }, // 2301 |
| 2310 | { PseudoVREDMINU_VS_M2_E8_MASK, PseudoVREDMINU_VS_M2_E8, 0x3, true }, // 2302 |
| 2311 | { PseudoVREDMINU_VS_M4_E16_MASK, PseudoVREDMINU_VS_M4_E16, 0x3, true }, // 2303 |
| 2312 | { PseudoVREDMINU_VS_M4_E32_MASK, PseudoVREDMINU_VS_M4_E32, 0x3, true }, // 2304 |
| 2313 | { PseudoVREDMINU_VS_M4_E64_MASK, PseudoVREDMINU_VS_M4_E64, 0x3, true }, // 2305 |
| 2314 | { PseudoVREDMINU_VS_M4_E8_MASK, PseudoVREDMINU_VS_M4_E8, 0x3, true }, // 2306 |
| 2315 | { PseudoVREDMINU_VS_M8_E16_MASK, PseudoVREDMINU_VS_M8_E16, 0x3, true }, // 2307 |
| 2316 | { PseudoVREDMINU_VS_M8_E32_MASK, PseudoVREDMINU_VS_M8_E32, 0x3, true }, // 2308 |
| 2317 | { PseudoVREDMINU_VS_M8_E64_MASK, PseudoVREDMINU_VS_M8_E64, 0x3, true }, // 2309 |
| 2318 | { PseudoVREDMINU_VS_M8_E8_MASK, PseudoVREDMINU_VS_M8_E8, 0x3, true }, // 2310 |
| 2319 | { PseudoVREDMINU_VS_MF2_E16_MASK, PseudoVREDMINU_VS_MF2_E16, 0x3, true }, // 2311 |
| 2320 | { PseudoVREDMINU_VS_MF2_E32_MASK, PseudoVREDMINU_VS_MF2_E32, 0x3, true }, // 2312 |
| 2321 | { PseudoVREDMINU_VS_MF2_E8_MASK, PseudoVREDMINU_VS_MF2_E8, 0x3, true }, // 2313 |
| 2322 | { PseudoVREDMINU_VS_MF4_E16_MASK, PseudoVREDMINU_VS_MF4_E16, 0x3, true }, // 2314 |
| 2323 | { PseudoVREDMINU_VS_MF4_E8_MASK, PseudoVREDMINU_VS_MF4_E8, 0x3, true }, // 2315 |
| 2324 | { PseudoVREDMINU_VS_MF8_E8_MASK, PseudoVREDMINU_VS_MF8_E8, 0x3, true }, // 2316 |
| 2325 | { PseudoVREDMIN_VS_M1_E16_MASK, PseudoVREDMIN_VS_M1_E16, 0x3, true }, // 2317 |
| 2326 | { PseudoVREDMIN_VS_M1_E32_MASK, PseudoVREDMIN_VS_M1_E32, 0x3, true }, // 2318 |
| 2327 | { PseudoVREDMIN_VS_M1_E64_MASK, PseudoVREDMIN_VS_M1_E64, 0x3, true }, // 2319 |
| 2328 | { PseudoVREDMIN_VS_M1_E8_MASK, PseudoVREDMIN_VS_M1_E8, 0x3, true }, // 2320 |
| 2329 | { PseudoVREDMIN_VS_M2_E16_MASK, PseudoVREDMIN_VS_M2_E16, 0x3, true }, // 2321 |
| 2330 | { PseudoVREDMIN_VS_M2_E32_MASK, PseudoVREDMIN_VS_M2_E32, 0x3, true }, // 2322 |
| 2331 | { PseudoVREDMIN_VS_M2_E64_MASK, PseudoVREDMIN_VS_M2_E64, 0x3, true }, // 2323 |
| 2332 | { PseudoVREDMIN_VS_M2_E8_MASK, PseudoVREDMIN_VS_M2_E8, 0x3, true }, // 2324 |
| 2333 | { PseudoVREDMIN_VS_M4_E16_MASK, PseudoVREDMIN_VS_M4_E16, 0x3, true }, // 2325 |
| 2334 | { PseudoVREDMIN_VS_M4_E32_MASK, PseudoVREDMIN_VS_M4_E32, 0x3, true }, // 2326 |
| 2335 | { PseudoVREDMIN_VS_M4_E64_MASK, PseudoVREDMIN_VS_M4_E64, 0x3, true }, // 2327 |
| 2336 | { PseudoVREDMIN_VS_M4_E8_MASK, PseudoVREDMIN_VS_M4_E8, 0x3, true }, // 2328 |
| 2337 | { PseudoVREDMIN_VS_M8_E16_MASK, PseudoVREDMIN_VS_M8_E16, 0x3, true }, // 2329 |
| 2338 | { PseudoVREDMIN_VS_M8_E32_MASK, PseudoVREDMIN_VS_M8_E32, 0x3, true }, // 2330 |
| 2339 | { PseudoVREDMIN_VS_M8_E64_MASK, PseudoVREDMIN_VS_M8_E64, 0x3, true }, // 2331 |
| 2340 | { PseudoVREDMIN_VS_M8_E8_MASK, PseudoVREDMIN_VS_M8_E8, 0x3, true }, // 2332 |
| 2341 | { PseudoVREDMIN_VS_MF2_E16_MASK, PseudoVREDMIN_VS_MF2_E16, 0x3, true }, // 2333 |
| 2342 | { PseudoVREDMIN_VS_MF2_E32_MASK, PseudoVREDMIN_VS_MF2_E32, 0x3, true }, // 2334 |
| 2343 | { PseudoVREDMIN_VS_MF2_E8_MASK, PseudoVREDMIN_VS_MF2_E8, 0x3, true }, // 2335 |
| 2344 | { PseudoVREDMIN_VS_MF4_E16_MASK, PseudoVREDMIN_VS_MF4_E16, 0x3, true }, // 2336 |
| 2345 | { PseudoVREDMIN_VS_MF4_E8_MASK, PseudoVREDMIN_VS_MF4_E8, 0x3, true }, // 2337 |
| 2346 | { PseudoVREDMIN_VS_MF8_E8_MASK, PseudoVREDMIN_VS_MF8_E8, 0x3, true }, // 2338 |
| 2347 | { PseudoVREDOR_VS_M1_E16_MASK, PseudoVREDOR_VS_M1_E16, 0x3, true }, // 2339 |
| 2348 | { PseudoVREDOR_VS_M1_E32_MASK, PseudoVREDOR_VS_M1_E32, 0x3, true }, // 2340 |
| 2349 | { PseudoVREDOR_VS_M1_E64_MASK, PseudoVREDOR_VS_M1_E64, 0x3, true }, // 2341 |
| 2350 | { PseudoVREDOR_VS_M1_E8_MASK, PseudoVREDOR_VS_M1_E8, 0x3, true }, // 2342 |
| 2351 | { PseudoVREDOR_VS_M2_E16_MASK, PseudoVREDOR_VS_M2_E16, 0x3, true }, // 2343 |
| 2352 | { PseudoVREDOR_VS_M2_E32_MASK, PseudoVREDOR_VS_M2_E32, 0x3, true }, // 2344 |
| 2353 | { PseudoVREDOR_VS_M2_E64_MASK, PseudoVREDOR_VS_M2_E64, 0x3, true }, // 2345 |
| 2354 | { PseudoVREDOR_VS_M2_E8_MASK, PseudoVREDOR_VS_M2_E8, 0x3, true }, // 2346 |
| 2355 | { PseudoVREDOR_VS_M4_E16_MASK, PseudoVREDOR_VS_M4_E16, 0x3, true }, // 2347 |
| 2356 | { PseudoVREDOR_VS_M4_E32_MASK, PseudoVREDOR_VS_M4_E32, 0x3, true }, // 2348 |
| 2357 | { PseudoVREDOR_VS_M4_E64_MASK, PseudoVREDOR_VS_M4_E64, 0x3, true }, // 2349 |
| 2358 | { PseudoVREDOR_VS_M4_E8_MASK, PseudoVREDOR_VS_M4_E8, 0x3, true }, // 2350 |
| 2359 | { PseudoVREDOR_VS_M8_E16_MASK, PseudoVREDOR_VS_M8_E16, 0x3, true }, // 2351 |
| 2360 | { PseudoVREDOR_VS_M8_E32_MASK, PseudoVREDOR_VS_M8_E32, 0x3, true }, // 2352 |
| 2361 | { PseudoVREDOR_VS_M8_E64_MASK, PseudoVREDOR_VS_M8_E64, 0x3, true }, // 2353 |
| 2362 | { PseudoVREDOR_VS_M8_E8_MASK, PseudoVREDOR_VS_M8_E8, 0x3, true }, // 2354 |
| 2363 | { PseudoVREDOR_VS_MF2_E16_MASK, PseudoVREDOR_VS_MF2_E16, 0x3, true }, // 2355 |
| 2364 | { PseudoVREDOR_VS_MF2_E32_MASK, PseudoVREDOR_VS_MF2_E32, 0x3, true }, // 2356 |
| 2365 | { PseudoVREDOR_VS_MF2_E8_MASK, PseudoVREDOR_VS_MF2_E8, 0x3, true }, // 2357 |
| 2366 | { PseudoVREDOR_VS_MF4_E16_MASK, PseudoVREDOR_VS_MF4_E16, 0x3, true }, // 2358 |
| 2367 | { PseudoVREDOR_VS_MF4_E8_MASK, PseudoVREDOR_VS_MF4_E8, 0x3, true }, // 2359 |
| 2368 | { PseudoVREDOR_VS_MF8_E8_MASK, PseudoVREDOR_VS_MF8_E8, 0x3, true }, // 2360 |
| 2369 | { PseudoVREDSUM_VS_M1_E16_MASK, PseudoVREDSUM_VS_M1_E16, 0x3, true }, // 2361 |
| 2370 | { PseudoVREDSUM_VS_M1_E32_MASK, PseudoVREDSUM_VS_M1_E32, 0x3, true }, // 2362 |
| 2371 | { PseudoVREDSUM_VS_M1_E64_MASK, PseudoVREDSUM_VS_M1_E64, 0x3, true }, // 2363 |
| 2372 | { PseudoVREDSUM_VS_M1_E8_MASK, PseudoVREDSUM_VS_M1_E8, 0x3, true }, // 2364 |
| 2373 | { PseudoVREDSUM_VS_M2_E16_MASK, PseudoVREDSUM_VS_M2_E16, 0x3, true }, // 2365 |
| 2374 | { PseudoVREDSUM_VS_M2_E32_MASK, PseudoVREDSUM_VS_M2_E32, 0x3, true }, // 2366 |
| 2375 | { PseudoVREDSUM_VS_M2_E64_MASK, PseudoVREDSUM_VS_M2_E64, 0x3, true }, // 2367 |
| 2376 | { PseudoVREDSUM_VS_M2_E8_MASK, PseudoVREDSUM_VS_M2_E8, 0x3, true }, // 2368 |
| 2377 | { PseudoVREDSUM_VS_M4_E16_MASK, PseudoVREDSUM_VS_M4_E16, 0x3, true }, // 2369 |
| 2378 | { PseudoVREDSUM_VS_M4_E32_MASK, PseudoVREDSUM_VS_M4_E32, 0x3, true }, // 2370 |
| 2379 | { PseudoVREDSUM_VS_M4_E64_MASK, PseudoVREDSUM_VS_M4_E64, 0x3, true }, // 2371 |
| 2380 | { PseudoVREDSUM_VS_M4_E8_MASK, PseudoVREDSUM_VS_M4_E8, 0x3, true }, // 2372 |
| 2381 | { PseudoVREDSUM_VS_M8_E16_MASK, PseudoVREDSUM_VS_M8_E16, 0x3, true }, // 2373 |
| 2382 | { PseudoVREDSUM_VS_M8_E32_MASK, PseudoVREDSUM_VS_M8_E32, 0x3, true }, // 2374 |
| 2383 | { PseudoVREDSUM_VS_M8_E64_MASK, PseudoVREDSUM_VS_M8_E64, 0x3, true }, // 2375 |
| 2384 | { PseudoVREDSUM_VS_M8_E8_MASK, PseudoVREDSUM_VS_M8_E8, 0x3, true }, // 2376 |
| 2385 | { PseudoVREDSUM_VS_MF2_E16_MASK, PseudoVREDSUM_VS_MF2_E16, 0x3, true }, // 2377 |
| 2386 | { PseudoVREDSUM_VS_MF2_E32_MASK, PseudoVREDSUM_VS_MF2_E32, 0x3, true }, // 2378 |
| 2387 | { PseudoVREDSUM_VS_MF2_E8_MASK, PseudoVREDSUM_VS_MF2_E8, 0x3, true }, // 2379 |
| 2388 | { PseudoVREDSUM_VS_MF4_E16_MASK, PseudoVREDSUM_VS_MF4_E16, 0x3, true }, // 2380 |
| 2389 | { PseudoVREDSUM_VS_MF4_E8_MASK, PseudoVREDSUM_VS_MF4_E8, 0x3, true }, // 2381 |
| 2390 | { PseudoVREDSUM_VS_MF8_E8_MASK, PseudoVREDSUM_VS_MF8_E8, 0x3, true }, // 2382 |
| 2391 | { PseudoVREDXOR_VS_M1_E16_MASK, PseudoVREDXOR_VS_M1_E16, 0x3, true }, // 2383 |
| 2392 | { PseudoVREDXOR_VS_M1_E32_MASK, PseudoVREDXOR_VS_M1_E32, 0x3, true }, // 2384 |
| 2393 | { PseudoVREDXOR_VS_M1_E64_MASK, PseudoVREDXOR_VS_M1_E64, 0x3, true }, // 2385 |
| 2394 | { PseudoVREDXOR_VS_M1_E8_MASK, PseudoVREDXOR_VS_M1_E8, 0x3, true }, // 2386 |
| 2395 | { PseudoVREDXOR_VS_M2_E16_MASK, PseudoVREDXOR_VS_M2_E16, 0x3, true }, // 2387 |
| 2396 | { PseudoVREDXOR_VS_M2_E32_MASK, PseudoVREDXOR_VS_M2_E32, 0x3, true }, // 2388 |
| 2397 | { PseudoVREDXOR_VS_M2_E64_MASK, PseudoVREDXOR_VS_M2_E64, 0x3, true }, // 2389 |
| 2398 | { PseudoVREDXOR_VS_M2_E8_MASK, PseudoVREDXOR_VS_M2_E8, 0x3, true }, // 2390 |
| 2399 | { PseudoVREDXOR_VS_M4_E16_MASK, PseudoVREDXOR_VS_M4_E16, 0x3, true }, // 2391 |
| 2400 | { PseudoVREDXOR_VS_M4_E32_MASK, PseudoVREDXOR_VS_M4_E32, 0x3, true }, // 2392 |
| 2401 | { PseudoVREDXOR_VS_M4_E64_MASK, PseudoVREDXOR_VS_M4_E64, 0x3, true }, // 2393 |
| 2402 | { PseudoVREDXOR_VS_M4_E8_MASK, PseudoVREDXOR_VS_M4_E8, 0x3, true }, // 2394 |
| 2403 | { PseudoVREDXOR_VS_M8_E16_MASK, PseudoVREDXOR_VS_M8_E16, 0x3, true }, // 2395 |
| 2404 | { PseudoVREDXOR_VS_M8_E32_MASK, PseudoVREDXOR_VS_M8_E32, 0x3, true }, // 2396 |
| 2405 | { PseudoVREDXOR_VS_M8_E64_MASK, PseudoVREDXOR_VS_M8_E64, 0x3, true }, // 2397 |
| 2406 | { PseudoVREDXOR_VS_M8_E8_MASK, PseudoVREDXOR_VS_M8_E8, 0x3, true }, // 2398 |
| 2407 | { PseudoVREDXOR_VS_MF2_E16_MASK, PseudoVREDXOR_VS_MF2_E16, 0x3, true }, // 2399 |
| 2408 | { PseudoVREDXOR_VS_MF2_E32_MASK, PseudoVREDXOR_VS_MF2_E32, 0x3, true }, // 2400 |
| 2409 | { PseudoVREDXOR_VS_MF2_E8_MASK, PseudoVREDXOR_VS_MF2_E8, 0x3, true }, // 2401 |
| 2410 | { PseudoVREDXOR_VS_MF4_E16_MASK, PseudoVREDXOR_VS_MF4_E16, 0x3, true }, // 2402 |
| 2411 | { PseudoVREDXOR_VS_MF4_E8_MASK, PseudoVREDXOR_VS_MF4_E8, 0x3, true }, // 2403 |
| 2412 | { PseudoVREDXOR_VS_MF8_E8_MASK, PseudoVREDXOR_VS_MF8_E8, 0x3, true }, // 2404 |
| 2413 | { PseudoVREMU_VV_M1_E16_MASK, PseudoVREMU_VV_M1_E16, 0x3, false }, // 2405 |
| 2414 | { PseudoVREMU_VV_M1_E32_MASK, PseudoVREMU_VV_M1_E32, 0x3, false }, // 2406 |
| 2415 | { PseudoVREMU_VV_M1_E64_MASK, PseudoVREMU_VV_M1_E64, 0x3, false }, // 2407 |
| 2416 | { PseudoVREMU_VV_M1_E8_MASK, PseudoVREMU_VV_M1_E8, 0x3, false }, // 2408 |
| 2417 | { PseudoVREMU_VV_M2_E16_MASK, PseudoVREMU_VV_M2_E16, 0x3, false }, // 2409 |
| 2418 | { PseudoVREMU_VV_M2_E32_MASK, PseudoVREMU_VV_M2_E32, 0x3, false }, // 2410 |
| 2419 | { PseudoVREMU_VV_M2_E64_MASK, PseudoVREMU_VV_M2_E64, 0x3, false }, // 2411 |
| 2420 | { PseudoVREMU_VV_M2_E8_MASK, PseudoVREMU_VV_M2_E8, 0x3, false }, // 2412 |
| 2421 | { PseudoVREMU_VV_M4_E16_MASK, PseudoVREMU_VV_M4_E16, 0x3, false }, // 2413 |
| 2422 | { PseudoVREMU_VV_M4_E32_MASK, PseudoVREMU_VV_M4_E32, 0x3, false }, // 2414 |
| 2423 | { PseudoVREMU_VV_M4_E64_MASK, PseudoVREMU_VV_M4_E64, 0x3, false }, // 2415 |
| 2424 | { PseudoVREMU_VV_M4_E8_MASK, PseudoVREMU_VV_M4_E8, 0x3, false }, // 2416 |
| 2425 | { PseudoVREMU_VV_M8_E16_MASK, PseudoVREMU_VV_M8_E16, 0x3, false }, // 2417 |
| 2426 | { PseudoVREMU_VV_M8_E32_MASK, PseudoVREMU_VV_M8_E32, 0x3, false }, // 2418 |
| 2427 | { PseudoVREMU_VV_M8_E64_MASK, PseudoVREMU_VV_M8_E64, 0x3, false }, // 2419 |
| 2428 | { PseudoVREMU_VV_M8_E8_MASK, PseudoVREMU_VV_M8_E8, 0x3, false }, // 2420 |
| 2429 | { PseudoVREMU_VV_MF2_E16_MASK, PseudoVREMU_VV_MF2_E16, 0x3, false }, // 2421 |
| 2430 | { PseudoVREMU_VV_MF2_E32_MASK, PseudoVREMU_VV_MF2_E32, 0x3, false }, // 2422 |
| 2431 | { PseudoVREMU_VV_MF2_E8_MASK, PseudoVREMU_VV_MF2_E8, 0x3, false }, // 2423 |
| 2432 | { PseudoVREMU_VV_MF4_E16_MASK, PseudoVREMU_VV_MF4_E16, 0x3, false }, // 2424 |
| 2433 | { PseudoVREMU_VV_MF4_E8_MASK, PseudoVREMU_VV_MF4_E8, 0x3, false }, // 2425 |
| 2434 | { PseudoVREMU_VV_MF8_E8_MASK, PseudoVREMU_VV_MF8_E8, 0x3, false }, // 2426 |
| 2435 | { PseudoVREMU_VX_M1_E16_MASK, PseudoVREMU_VX_M1_E16, 0x3, false }, // 2427 |
| 2436 | { PseudoVREMU_VX_M1_E32_MASK, PseudoVREMU_VX_M1_E32, 0x3, false }, // 2428 |
| 2437 | { PseudoVREMU_VX_M1_E64_MASK, PseudoVREMU_VX_M1_E64, 0x3, false }, // 2429 |
| 2438 | { PseudoVREMU_VX_M1_E8_MASK, PseudoVREMU_VX_M1_E8, 0x3, false }, // 2430 |
| 2439 | { PseudoVREMU_VX_M2_E16_MASK, PseudoVREMU_VX_M2_E16, 0x3, false }, // 2431 |
| 2440 | { PseudoVREMU_VX_M2_E32_MASK, PseudoVREMU_VX_M2_E32, 0x3, false }, // 2432 |
| 2441 | { PseudoVREMU_VX_M2_E64_MASK, PseudoVREMU_VX_M2_E64, 0x3, false }, // 2433 |
| 2442 | { PseudoVREMU_VX_M2_E8_MASK, PseudoVREMU_VX_M2_E8, 0x3, false }, // 2434 |
| 2443 | { PseudoVREMU_VX_M4_E16_MASK, PseudoVREMU_VX_M4_E16, 0x3, false }, // 2435 |
| 2444 | { PseudoVREMU_VX_M4_E32_MASK, PseudoVREMU_VX_M4_E32, 0x3, false }, // 2436 |
| 2445 | { PseudoVREMU_VX_M4_E64_MASK, PseudoVREMU_VX_M4_E64, 0x3, false }, // 2437 |
| 2446 | { PseudoVREMU_VX_M4_E8_MASK, PseudoVREMU_VX_M4_E8, 0x3, false }, // 2438 |
| 2447 | { PseudoVREMU_VX_M8_E16_MASK, PseudoVREMU_VX_M8_E16, 0x3, false }, // 2439 |
| 2448 | { PseudoVREMU_VX_M8_E32_MASK, PseudoVREMU_VX_M8_E32, 0x3, false }, // 2440 |
| 2449 | { PseudoVREMU_VX_M8_E64_MASK, PseudoVREMU_VX_M8_E64, 0x3, false }, // 2441 |
| 2450 | { PseudoVREMU_VX_M8_E8_MASK, PseudoVREMU_VX_M8_E8, 0x3, false }, // 2442 |
| 2451 | { PseudoVREMU_VX_MF2_E16_MASK, PseudoVREMU_VX_MF2_E16, 0x3, false }, // 2443 |
| 2452 | { PseudoVREMU_VX_MF2_E32_MASK, PseudoVREMU_VX_MF2_E32, 0x3, false }, // 2444 |
| 2453 | { PseudoVREMU_VX_MF2_E8_MASK, PseudoVREMU_VX_MF2_E8, 0x3, false }, // 2445 |
| 2454 | { PseudoVREMU_VX_MF4_E16_MASK, PseudoVREMU_VX_MF4_E16, 0x3, false }, // 2446 |
| 2455 | { PseudoVREMU_VX_MF4_E8_MASK, PseudoVREMU_VX_MF4_E8, 0x3, false }, // 2447 |
| 2456 | { PseudoVREMU_VX_MF8_E8_MASK, PseudoVREMU_VX_MF8_E8, 0x3, false }, // 2448 |
| 2457 | { PseudoVREM_VV_M1_E16_MASK, PseudoVREM_VV_M1_E16, 0x3, false }, // 2449 |
| 2458 | { PseudoVREM_VV_M1_E32_MASK, PseudoVREM_VV_M1_E32, 0x3, false }, // 2450 |
| 2459 | { PseudoVREM_VV_M1_E64_MASK, PseudoVREM_VV_M1_E64, 0x3, false }, // 2451 |
| 2460 | { PseudoVREM_VV_M1_E8_MASK, PseudoVREM_VV_M1_E8, 0x3, false }, // 2452 |
| 2461 | { PseudoVREM_VV_M2_E16_MASK, PseudoVREM_VV_M2_E16, 0x3, false }, // 2453 |
| 2462 | { PseudoVREM_VV_M2_E32_MASK, PseudoVREM_VV_M2_E32, 0x3, false }, // 2454 |
| 2463 | { PseudoVREM_VV_M2_E64_MASK, PseudoVREM_VV_M2_E64, 0x3, false }, // 2455 |
| 2464 | { PseudoVREM_VV_M2_E8_MASK, PseudoVREM_VV_M2_E8, 0x3, false }, // 2456 |
| 2465 | { PseudoVREM_VV_M4_E16_MASK, PseudoVREM_VV_M4_E16, 0x3, false }, // 2457 |
| 2466 | { PseudoVREM_VV_M4_E32_MASK, PseudoVREM_VV_M4_E32, 0x3, false }, // 2458 |
| 2467 | { PseudoVREM_VV_M4_E64_MASK, PseudoVREM_VV_M4_E64, 0x3, false }, // 2459 |
| 2468 | { PseudoVREM_VV_M4_E8_MASK, PseudoVREM_VV_M4_E8, 0x3, false }, // 2460 |
| 2469 | { PseudoVREM_VV_M8_E16_MASK, PseudoVREM_VV_M8_E16, 0x3, false }, // 2461 |
| 2470 | { PseudoVREM_VV_M8_E32_MASK, PseudoVREM_VV_M8_E32, 0x3, false }, // 2462 |
| 2471 | { PseudoVREM_VV_M8_E64_MASK, PseudoVREM_VV_M8_E64, 0x3, false }, // 2463 |
| 2472 | { PseudoVREM_VV_M8_E8_MASK, PseudoVREM_VV_M8_E8, 0x3, false }, // 2464 |
| 2473 | { PseudoVREM_VV_MF2_E16_MASK, PseudoVREM_VV_MF2_E16, 0x3, false }, // 2465 |
| 2474 | { PseudoVREM_VV_MF2_E32_MASK, PseudoVREM_VV_MF2_E32, 0x3, false }, // 2466 |
| 2475 | { PseudoVREM_VV_MF2_E8_MASK, PseudoVREM_VV_MF2_E8, 0x3, false }, // 2467 |
| 2476 | { PseudoVREM_VV_MF4_E16_MASK, PseudoVREM_VV_MF4_E16, 0x3, false }, // 2468 |
| 2477 | { PseudoVREM_VV_MF4_E8_MASK, PseudoVREM_VV_MF4_E8, 0x3, false }, // 2469 |
| 2478 | { PseudoVREM_VV_MF8_E8_MASK, PseudoVREM_VV_MF8_E8, 0x3, false }, // 2470 |
| 2479 | { PseudoVREM_VX_M1_E16_MASK, PseudoVREM_VX_M1_E16, 0x3, false }, // 2471 |
| 2480 | { PseudoVREM_VX_M1_E32_MASK, PseudoVREM_VX_M1_E32, 0x3, false }, // 2472 |
| 2481 | { PseudoVREM_VX_M1_E64_MASK, PseudoVREM_VX_M1_E64, 0x3, false }, // 2473 |
| 2482 | { PseudoVREM_VX_M1_E8_MASK, PseudoVREM_VX_M1_E8, 0x3, false }, // 2474 |
| 2483 | { PseudoVREM_VX_M2_E16_MASK, PseudoVREM_VX_M2_E16, 0x3, false }, // 2475 |
| 2484 | { PseudoVREM_VX_M2_E32_MASK, PseudoVREM_VX_M2_E32, 0x3, false }, // 2476 |
| 2485 | { PseudoVREM_VX_M2_E64_MASK, PseudoVREM_VX_M2_E64, 0x3, false }, // 2477 |
| 2486 | { PseudoVREM_VX_M2_E8_MASK, PseudoVREM_VX_M2_E8, 0x3, false }, // 2478 |
| 2487 | { PseudoVREM_VX_M4_E16_MASK, PseudoVREM_VX_M4_E16, 0x3, false }, // 2479 |
| 2488 | { PseudoVREM_VX_M4_E32_MASK, PseudoVREM_VX_M4_E32, 0x3, false }, // 2480 |
| 2489 | { PseudoVREM_VX_M4_E64_MASK, PseudoVREM_VX_M4_E64, 0x3, false }, // 2481 |
| 2490 | { PseudoVREM_VX_M4_E8_MASK, PseudoVREM_VX_M4_E8, 0x3, false }, // 2482 |
| 2491 | { PseudoVREM_VX_M8_E16_MASK, PseudoVREM_VX_M8_E16, 0x3, false }, // 2483 |
| 2492 | { PseudoVREM_VX_M8_E32_MASK, PseudoVREM_VX_M8_E32, 0x3, false }, // 2484 |
| 2493 | { PseudoVREM_VX_M8_E64_MASK, PseudoVREM_VX_M8_E64, 0x3, false }, // 2485 |
| 2494 | { PseudoVREM_VX_M8_E8_MASK, PseudoVREM_VX_M8_E8, 0x3, false }, // 2486 |
| 2495 | { PseudoVREM_VX_MF2_E16_MASK, PseudoVREM_VX_MF2_E16, 0x3, false }, // 2487 |
| 2496 | { PseudoVREM_VX_MF2_E32_MASK, PseudoVREM_VX_MF2_E32, 0x3, false }, // 2488 |
| 2497 | { PseudoVREM_VX_MF2_E8_MASK, PseudoVREM_VX_MF2_E8, 0x3, false }, // 2489 |
| 2498 | { PseudoVREM_VX_MF4_E16_MASK, PseudoVREM_VX_MF4_E16, 0x3, false }, // 2490 |
| 2499 | { PseudoVREM_VX_MF4_E8_MASK, PseudoVREM_VX_MF4_E8, 0x3, false }, // 2491 |
| 2500 | { PseudoVREM_VX_MF8_E8_MASK, PseudoVREM_VX_MF8_E8, 0x3, false }, // 2492 |
| 2501 | { PseudoVREV8_V_M1_MASK, PseudoVREV8_V_M1, 0x2, false }, // 2493 |
| 2502 | { PseudoVREV8_V_M2_MASK, PseudoVREV8_V_M2, 0x2, false }, // 2494 |
| 2503 | { PseudoVREV8_V_M4_MASK, PseudoVREV8_V_M4, 0x2, false }, // 2495 |
| 2504 | { PseudoVREV8_V_M8_MASK, PseudoVREV8_V_M8, 0x2, false }, // 2496 |
| 2505 | { PseudoVREV8_V_MF2_MASK, PseudoVREV8_V_MF2, 0x2, false }, // 2497 |
| 2506 | { PseudoVREV8_V_MF4_MASK, PseudoVREV8_V_MF4, 0x2, false }, // 2498 |
| 2507 | { PseudoVREV8_V_MF8_MASK, PseudoVREV8_V_MF8, 0x2, false }, // 2499 |
| 2508 | { PseudoVRGATHEREI16_VV_M1_E16_M1_MASK, PseudoVRGATHEREI16_VV_M1_E16_M1, 0x3, false }, // 2500 |
| 2509 | { PseudoVRGATHEREI16_VV_M1_E16_M2_MASK, PseudoVRGATHEREI16_VV_M1_E16_M2, 0x3, false }, // 2501 |
| 2510 | { PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E16_MF2, 0x3, false }, // 2502 |
| 2511 | { PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E16_MF4, 0x3, false }, // 2503 |
| 2512 | { PseudoVRGATHEREI16_VV_M1_E32_M1_MASK, PseudoVRGATHEREI16_VV_M1_E32_M1, 0x3, false }, // 2504 |
| 2513 | { PseudoVRGATHEREI16_VV_M1_E32_M2_MASK, PseudoVRGATHEREI16_VV_M1_E32_M2, 0x3, false }, // 2505 |
| 2514 | { PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E32_MF2, 0x3, false }, // 2506 |
| 2515 | { PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E32_MF4, 0x3, false }, // 2507 |
| 2516 | { PseudoVRGATHEREI16_VV_M1_E64_M1_MASK, PseudoVRGATHEREI16_VV_M1_E64_M1, 0x3, false }, // 2508 |
| 2517 | { PseudoVRGATHEREI16_VV_M1_E64_M2_MASK, PseudoVRGATHEREI16_VV_M1_E64_M2, 0x3, false }, // 2509 |
| 2518 | { PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E64_MF2, 0x3, false }, // 2510 |
| 2519 | { PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E64_MF4, 0x3, false }, // 2511 |
| 2520 | { PseudoVRGATHEREI16_VV_M1_E8_M1_MASK, PseudoVRGATHEREI16_VV_M1_E8_M1, 0x3, false }, // 2512 |
| 2521 | { PseudoVRGATHEREI16_VV_M1_E8_M2_MASK, PseudoVRGATHEREI16_VV_M1_E8_M2, 0x3, false }, // 2513 |
| 2522 | { PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E8_MF2, 0x3, false }, // 2514 |
| 2523 | { PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E8_MF4, 0x3, false }, // 2515 |
| 2524 | { PseudoVRGATHEREI16_VV_M2_E16_M1_MASK, PseudoVRGATHEREI16_VV_M2_E16_M1, 0x3, false }, // 2516 |
| 2525 | { PseudoVRGATHEREI16_VV_M2_E16_M2_MASK, PseudoVRGATHEREI16_VV_M2_E16_M2, 0x3, false }, // 2517 |
| 2526 | { PseudoVRGATHEREI16_VV_M2_E16_M4_MASK, PseudoVRGATHEREI16_VV_M2_E16_M4, 0x3, false }, // 2518 |
| 2527 | { PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E16_MF2, 0x3, false }, // 2519 |
| 2528 | { PseudoVRGATHEREI16_VV_M2_E32_M1_MASK, PseudoVRGATHEREI16_VV_M2_E32_M1, 0x3, false }, // 2520 |
| 2529 | { PseudoVRGATHEREI16_VV_M2_E32_M2_MASK, PseudoVRGATHEREI16_VV_M2_E32_M2, 0x3, false }, // 2521 |
| 2530 | { PseudoVRGATHEREI16_VV_M2_E32_M4_MASK, PseudoVRGATHEREI16_VV_M2_E32_M4, 0x3, false }, // 2522 |
| 2531 | { PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E32_MF2, 0x3, false }, // 2523 |
| 2532 | { PseudoVRGATHEREI16_VV_M2_E64_M1_MASK, PseudoVRGATHEREI16_VV_M2_E64_M1, 0x3, false }, // 2524 |
| 2533 | { PseudoVRGATHEREI16_VV_M2_E64_M2_MASK, PseudoVRGATHEREI16_VV_M2_E64_M2, 0x3, false }, // 2525 |
| 2534 | { PseudoVRGATHEREI16_VV_M2_E64_M4_MASK, PseudoVRGATHEREI16_VV_M2_E64_M4, 0x3, false }, // 2526 |
| 2535 | { PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E64_MF2, 0x3, false }, // 2527 |
| 2536 | { PseudoVRGATHEREI16_VV_M2_E8_M1_MASK, PseudoVRGATHEREI16_VV_M2_E8_M1, 0x3, false }, // 2528 |
| 2537 | { PseudoVRGATHEREI16_VV_M2_E8_M2_MASK, PseudoVRGATHEREI16_VV_M2_E8_M2, 0x3, false }, // 2529 |
| 2538 | { PseudoVRGATHEREI16_VV_M2_E8_M4_MASK, PseudoVRGATHEREI16_VV_M2_E8_M4, 0x3, false }, // 2530 |
| 2539 | { PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E8_MF2, 0x3, false }, // 2531 |
| 2540 | { PseudoVRGATHEREI16_VV_M4_E16_M1_MASK, PseudoVRGATHEREI16_VV_M4_E16_M1, 0x3, false }, // 2532 |
| 2541 | { PseudoVRGATHEREI16_VV_M4_E16_M2_MASK, PseudoVRGATHEREI16_VV_M4_E16_M2, 0x3, false }, // 2533 |
| 2542 | { PseudoVRGATHEREI16_VV_M4_E16_M4_MASK, PseudoVRGATHEREI16_VV_M4_E16_M4, 0x3, false }, // 2534 |
| 2543 | { PseudoVRGATHEREI16_VV_M4_E16_M8_MASK, PseudoVRGATHEREI16_VV_M4_E16_M8, 0x3, false }, // 2535 |
| 2544 | { PseudoVRGATHEREI16_VV_M4_E32_M1_MASK, PseudoVRGATHEREI16_VV_M4_E32_M1, 0x3, false }, // 2536 |
| 2545 | { PseudoVRGATHEREI16_VV_M4_E32_M2_MASK, PseudoVRGATHEREI16_VV_M4_E32_M2, 0x3, false }, // 2537 |
| 2546 | { PseudoVRGATHEREI16_VV_M4_E32_M4_MASK, PseudoVRGATHEREI16_VV_M4_E32_M4, 0x3, false }, // 2538 |
| 2547 | { PseudoVRGATHEREI16_VV_M4_E32_M8_MASK, PseudoVRGATHEREI16_VV_M4_E32_M8, 0x3, false }, // 2539 |
| 2548 | { PseudoVRGATHEREI16_VV_M4_E64_M1_MASK, PseudoVRGATHEREI16_VV_M4_E64_M1, 0x3, false }, // 2540 |
| 2549 | { PseudoVRGATHEREI16_VV_M4_E64_M2_MASK, PseudoVRGATHEREI16_VV_M4_E64_M2, 0x3, false }, // 2541 |
| 2550 | { PseudoVRGATHEREI16_VV_M4_E64_M4_MASK, PseudoVRGATHEREI16_VV_M4_E64_M4, 0x3, false }, // 2542 |
| 2551 | { PseudoVRGATHEREI16_VV_M4_E64_M8_MASK, PseudoVRGATHEREI16_VV_M4_E64_M8, 0x3, false }, // 2543 |
| 2552 | { PseudoVRGATHEREI16_VV_M4_E8_M1_MASK, PseudoVRGATHEREI16_VV_M4_E8_M1, 0x3, false }, // 2544 |
| 2553 | { PseudoVRGATHEREI16_VV_M4_E8_M2_MASK, PseudoVRGATHEREI16_VV_M4_E8_M2, 0x3, false }, // 2545 |
| 2554 | { PseudoVRGATHEREI16_VV_M4_E8_M4_MASK, PseudoVRGATHEREI16_VV_M4_E8_M4, 0x3, false }, // 2546 |
| 2555 | { PseudoVRGATHEREI16_VV_M4_E8_M8_MASK, PseudoVRGATHEREI16_VV_M4_E8_M8, 0x3, false }, // 2547 |
| 2556 | { PseudoVRGATHEREI16_VV_M8_E16_M2_MASK, PseudoVRGATHEREI16_VV_M8_E16_M2, 0x3, false }, // 2548 |
| 2557 | { PseudoVRGATHEREI16_VV_M8_E16_M4_MASK, PseudoVRGATHEREI16_VV_M8_E16_M4, 0x3, false }, // 2549 |
| 2558 | { PseudoVRGATHEREI16_VV_M8_E16_M8_MASK, PseudoVRGATHEREI16_VV_M8_E16_M8, 0x3, false }, // 2550 |
| 2559 | { PseudoVRGATHEREI16_VV_M8_E32_M2_MASK, PseudoVRGATHEREI16_VV_M8_E32_M2, 0x3, false }, // 2551 |
| 2560 | { PseudoVRGATHEREI16_VV_M8_E32_M4_MASK, PseudoVRGATHEREI16_VV_M8_E32_M4, 0x3, false }, // 2552 |
| 2561 | { PseudoVRGATHEREI16_VV_M8_E32_M8_MASK, PseudoVRGATHEREI16_VV_M8_E32_M8, 0x3, false }, // 2553 |
| 2562 | { PseudoVRGATHEREI16_VV_M8_E64_M2_MASK, PseudoVRGATHEREI16_VV_M8_E64_M2, 0x3, false }, // 2554 |
| 2563 | { PseudoVRGATHEREI16_VV_M8_E64_M4_MASK, PseudoVRGATHEREI16_VV_M8_E64_M4, 0x3, false }, // 2555 |
| 2564 | { PseudoVRGATHEREI16_VV_M8_E64_M8_MASK, PseudoVRGATHEREI16_VV_M8_E64_M8, 0x3, false }, // 2556 |
| 2565 | { PseudoVRGATHEREI16_VV_M8_E8_M2_MASK, PseudoVRGATHEREI16_VV_M8_E8_M2, 0x3, false }, // 2557 |
| 2566 | { PseudoVRGATHEREI16_VV_M8_E8_M4_MASK, PseudoVRGATHEREI16_VV_M8_E8_M4, 0x3, false }, // 2558 |
| 2567 | { PseudoVRGATHEREI16_VV_M8_E8_M8_MASK, PseudoVRGATHEREI16_VV_M8_E8_M8, 0x3, false }, // 2559 |
| 2568 | { PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK, PseudoVRGATHEREI16_VV_MF2_E16_M1, 0x3, false }, // 2560 |
| 2569 | { PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK, PseudoVRGATHEREI16_VV_MF2_E16_MF2, 0x3, false }, // 2561 |
| 2570 | { PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK, PseudoVRGATHEREI16_VV_MF2_E16_MF4, 0x3, false }, // 2562 |
| 2571 | { PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK, PseudoVRGATHEREI16_VV_MF2_E16_MF8, 0x3, false }, // 2563 |
| 2572 | { PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK, PseudoVRGATHEREI16_VV_MF2_E32_M1, 0x3, false }, // 2564 |
| 2573 | { PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK, PseudoVRGATHEREI16_VV_MF2_E32_MF2, 0x3, false }, // 2565 |
| 2574 | { PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK, PseudoVRGATHEREI16_VV_MF2_E32_MF4, 0x3, false }, // 2566 |
| 2575 | { PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK, PseudoVRGATHEREI16_VV_MF2_E32_MF8, 0x3, false }, // 2567 |
| 2576 | { PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK, PseudoVRGATHEREI16_VV_MF2_E8_M1, 0x3, false }, // 2568 |
| 2577 | { PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK, PseudoVRGATHEREI16_VV_MF2_E8_MF2, 0x3, false }, // 2569 |
| 2578 | { PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK, PseudoVRGATHEREI16_VV_MF2_E8_MF4, 0x3, false }, // 2570 |
| 2579 | { PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK, PseudoVRGATHEREI16_VV_MF2_E8_MF8, 0x3, false }, // 2571 |
| 2580 | { PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK, PseudoVRGATHEREI16_VV_MF4_E16_MF2, 0x3, false }, // 2572 |
| 2581 | { PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK, PseudoVRGATHEREI16_VV_MF4_E16_MF4, 0x3, false }, // 2573 |
| 2582 | { PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK, PseudoVRGATHEREI16_VV_MF4_E16_MF8, 0x3, false }, // 2574 |
| 2583 | { PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK, PseudoVRGATHEREI16_VV_MF4_E8_MF2, 0x3, false }, // 2575 |
| 2584 | { PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK, PseudoVRGATHEREI16_VV_MF4_E8_MF4, 0x3, false }, // 2576 |
| 2585 | { PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK, PseudoVRGATHEREI16_VV_MF4_E8_MF8, 0x3, false }, // 2577 |
| 2586 | { PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK, PseudoVRGATHEREI16_VV_MF8_E8_MF4, 0x3, false }, // 2578 |
| 2587 | { PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK, PseudoVRGATHEREI16_VV_MF8_E8_MF8, 0x3, false }, // 2579 |
| 2588 | { PseudoVRGATHER_VI_M1_MASK, PseudoVRGATHER_VI_M1, 0x3, false }, // 2580 |
| 2589 | { PseudoVRGATHER_VI_M2_MASK, PseudoVRGATHER_VI_M2, 0x3, false }, // 2581 |
| 2590 | { PseudoVRGATHER_VI_M4_MASK, PseudoVRGATHER_VI_M4, 0x3, false }, // 2582 |
| 2591 | { PseudoVRGATHER_VI_M8_MASK, PseudoVRGATHER_VI_M8, 0x3, false }, // 2583 |
| 2592 | { PseudoVRGATHER_VI_MF2_MASK, PseudoVRGATHER_VI_MF2, 0x3, false }, // 2584 |
| 2593 | { PseudoVRGATHER_VI_MF4_MASK, PseudoVRGATHER_VI_MF4, 0x3, false }, // 2585 |
| 2594 | { PseudoVRGATHER_VI_MF8_MASK, PseudoVRGATHER_VI_MF8, 0x3, false }, // 2586 |
| 2595 | { PseudoVRGATHER_VV_M1_E16_MASK, PseudoVRGATHER_VV_M1_E16, 0x3, false }, // 2587 |
| 2596 | { PseudoVRGATHER_VV_M1_E32_MASK, PseudoVRGATHER_VV_M1_E32, 0x3, false }, // 2588 |
| 2597 | { PseudoVRGATHER_VV_M1_E64_MASK, PseudoVRGATHER_VV_M1_E64, 0x3, false }, // 2589 |
| 2598 | { PseudoVRGATHER_VV_M1_E8_MASK, PseudoVRGATHER_VV_M1_E8, 0x3, false }, // 2590 |
| 2599 | { PseudoVRGATHER_VV_M2_E16_MASK, PseudoVRGATHER_VV_M2_E16, 0x3, false }, // 2591 |
| 2600 | { PseudoVRGATHER_VV_M2_E32_MASK, PseudoVRGATHER_VV_M2_E32, 0x3, false }, // 2592 |
| 2601 | { PseudoVRGATHER_VV_M2_E64_MASK, PseudoVRGATHER_VV_M2_E64, 0x3, false }, // 2593 |
| 2602 | { PseudoVRGATHER_VV_M2_E8_MASK, PseudoVRGATHER_VV_M2_E8, 0x3, false }, // 2594 |
| 2603 | { PseudoVRGATHER_VV_M4_E16_MASK, PseudoVRGATHER_VV_M4_E16, 0x3, false }, // 2595 |
| 2604 | { PseudoVRGATHER_VV_M4_E32_MASK, PseudoVRGATHER_VV_M4_E32, 0x3, false }, // 2596 |
| 2605 | { PseudoVRGATHER_VV_M4_E64_MASK, PseudoVRGATHER_VV_M4_E64, 0x3, false }, // 2597 |
| 2606 | { PseudoVRGATHER_VV_M4_E8_MASK, PseudoVRGATHER_VV_M4_E8, 0x3, false }, // 2598 |
| 2607 | { PseudoVRGATHER_VV_M8_E16_MASK, PseudoVRGATHER_VV_M8_E16, 0x3, false }, // 2599 |
| 2608 | { PseudoVRGATHER_VV_M8_E32_MASK, PseudoVRGATHER_VV_M8_E32, 0x3, false }, // 2600 |
| 2609 | { PseudoVRGATHER_VV_M8_E64_MASK, PseudoVRGATHER_VV_M8_E64, 0x3, false }, // 2601 |
| 2610 | { PseudoVRGATHER_VV_M8_E8_MASK, PseudoVRGATHER_VV_M8_E8, 0x3, false }, // 2602 |
| 2611 | { PseudoVRGATHER_VV_MF2_E16_MASK, PseudoVRGATHER_VV_MF2_E16, 0x3, false }, // 2603 |
| 2612 | { PseudoVRGATHER_VV_MF2_E32_MASK, PseudoVRGATHER_VV_MF2_E32, 0x3, false }, // 2604 |
| 2613 | { PseudoVRGATHER_VV_MF2_E8_MASK, PseudoVRGATHER_VV_MF2_E8, 0x3, false }, // 2605 |
| 2614 | { PseudoVRGATHER_VV_MF4_E16_MASK, PseudoVRGATHER_VV_MF4_E16, 0x3, false }, // 2606 |
| 2615 | { PseudoVRGATHER_VV_MF4_E8_MASK, PseudoVRGATHER_VV_MF4_E8, 0x3, false }, // 2607 |
| 2616 | { PseudoVRGATHER_VV_MF8_E8_MASK, PseudoVRGATHER_VV_MF8_E8, 0x3, false }, // 2608 |
| 2617 | { PseudoVRGATHER_VX_M1_MASK, PseudoVRGATHER_VX_M1, 0x3, false }, // 2609 |
| 2618 | { PseudoVRGATHER_VX_M2_MASK, PseudoVRGATHER_VX_M2, 0x3, false }, // 2610 |
| 2619 | { PseudoVRGATHER_VX_M4_MASK, PseudoVRGATHER_VX_M4, 0x3, false }, // 2611 |
| 2620 | { PseudoVRGATHER_VX_M8_MASK, PseudoVRGATHER_VX_M8, 0x3, false }, // 2612 |
| 2621 | { PseudoVRGATHER_VX_MF2_MASK, PseudoVRGATHER_VX_MF2, 0x3, false }, // 2613 |
| 2622 | { PseudoVRGATHER_VX_MF4_MASK, PseudoVRGATHER_VX_MF4, 0x3, false }, // 2614 |
| 2623 | { PseudoVRGATHER_VX_MF8_MASK, PseudoVRGATHER_VX_MF8, 0x3, false }, // 2615 |
| 2624 | { PseudoVROL_VV_M1_MASK, PseudoVROL_VV_M1, 0x3, false }, // 2616 |
| 2625 | { PseudoVROL_VV_M2_MASK, PseudoVROL_VV_M2, 0x3, false }, // 2617 |
| 2626 | { PseudoVROL_VV_M4_MASK, PseudoVROL_VV_M4, 0x3, false }, // 2618 |
| 2627 | { PseudoVROL_VV_M8_MASK, PseudoVROL_VV_M8, 0x3, false }, // 2619 |
| 2628 | { PseudoVROL_VV_MF2_MASK, PseudoVROL_VV_MF2, 0x3, false }, // 2620 |
| 2629 | { PseudoVROL_VV_MF4_MASK, PseudoVROL_VV_MF4, 0x3, false }, // 2621 |
| 2630 | { PseudoVROL_VV_MF8_MASK, PseudoVROL_VV_MF8, 0x3, false }, // 2622 |
| 2631 | { PseudoVROL_VX_M1_MASK, PseudoVROL_VX_M1, 0x3, false }, // 2623 |
| 2632 | { PseudoVROL_VX_M2_MASK, PseudoVROL_VX_M2, 0x3, false }, // 2624 |
| 2633 | { PseudoVROL_VX_M4_MASK, PseudoVROL_VX_M4, 0x3, false }, // 2625 |
| 2634 | { PseudoVROL_VX_M8_MASK, PseudoVROL_VX_M8, 0x3, false }, // 2626 |
| 2635 | { PseudoVROL_VX_MF2_MASK, PseudoVROL_VX_MF2, 0x3, false }, // 2627 |
| 2636 | { PseudoVROL_VX_MF4_MASK, PseudoVROL_VX_MF4, 0x3, false }, // 2628 |
| 2637 | { PseudoVROL_VX_MF8_MASK, PseudoVROL_VX_MF8, 0x3, false }, // 2629 |
| 2638 | { PseudoVROR_VI_M1_MASK, PseudoVROR_VI_M1, 0x3, false }, // 2630 |
| 2639 | { PseudoVROR_VI_M2_MASK, PseudoVROR_VI_M2, 0x3, false }, // 2631 |
| 2640 | { PseudoVROR_VI_M4_MASK, PseudoVROR_VI_M4, 0x3, false }, // 2632 |
| 2641 | { PseudoVROR_VI_M8_MASK, PseudoVROR_VI_M8, 0x3, false }, // 2633 |
| 2642 | { PseudoVROR_VI_MF2_MASK, PseudoVROR_VI_MF2, 0x3, false }, // 2634 |
| 2643 | { PseudoVROR_VI_MF4_MASK, PseudoVROR_VI_MF4, 0x3, false }, // 2635 |
| 2644 | { PseudoVROR_VI_MF8_MASK, PseudoVROR_VI_MF8, 0x3, false }, // 2636 |
| 2645 | { PseudoVROR_VV_M1_MASK, PseudoVROR_VV_M1, 0x3, false }, // 2637 |
| 2646 | { PseudoVROR_VV_M2_MASK, PseudoVROR_VV_M2, 0x3, false }, // 2638 |
| 2647 | { PseudoVROR_VV_M4_MASK, PseudoVROR_VV_M4, 0x3, false }, // 2639 |
| 2648 | { PseudoVROR_VV_M8_MASK, PseudoVROR_VV_M8, 0x3, false }, // 2640 |
| 2649 | { PseudoVROR_VV_MF2_MASK, PseudoVROR_VV_MF2, 0x3, false }, // 2641 |
| 2650 | { PseudoVROR_VV_MF4_MASK, PseudoVROR_VV_MF4, 0x3, false }, // 2642 |
| 2651 | { PseudoVROR_VV_MF8_MASK, PseudoVROR_VV_MF8, 0x3, false }, // 2643 |
| 2652 | { PseudoVROR_VX_M1_MASK, PseudoVROR_VX_M1, 0x3, false }, // 2644 |
| 2653 | { PseudoVROR_VX_M2_MASK, PseudoVROR_VX_M2, 0x3, false }, // 2645 |
| 2654 | { PseudoVROR_VX_M4_MASK, PseudoVROR_VX_M4, 0x3, false }, // 2646 |
| 2655 | { PseudoVROR_VX_M8_MASK, PseudoVROR_VX_M8, 0x3, false }, // 2647 |
| 2656 | { PseudoVROR_VX_MF2_MASK, PseudoVROR_VX_MF2, 0x3, false }, // 2648 |
| 2657 | { PseudoVROR_VX_MF4_MASK, PseudoVROR_VX_MF4, 0x3, false }, // 2649 |
| 2658 | { PseudoVROR_VX_MF8_MASK, PseudoVROR_VX_MF8, 0x3, false }, // 2650 |
| 2659 | { PseudoVRSUB_VI_M1_MASK, PseudoVRSUB_VI_M1, 0x3, false }, // 2651 |
| 2660 | { PseudoVRSUB_VI_M2_MASK, PseudoVRSUB_VI_M2, 0x3, false }, // 2652 |
| 2661 | { PseudoVRSUB_VI_M4_MASK, PseudoVRSUB_VI_M4, 0x3, false }, // 2653 |
| 2662 | { PseudoVRSUB_VI_M8_MASK, PseudoVRSUB_VI_M8, 0x3, false }, // 2654 |
| 2663 | { PseudoVRSUB_VI_MF2_MASK, PseudoVRSUB_VI_MF2, 0x3, false }, // 2655 |
| 2664 | { PseudoVRSUB_VI_MF4_MASK, PseudoVRSUB_VI_MF4, 0x3, false }, // 2656 |
| 2665 | { PseudoVRSUB_VI_MF8_MASK, PseudoVRSUB_VI_MF8, 0x3, false }, // 2657 |
| 2666 | { PseudoVRSUB_VX_M1_MASK, PseudoVRSUB_VX_M1, 0x3, false }, // 2658 |
| 2667 | { PseudoVRSUB_VX_M2_MASK, PseudoVRSUB_VX_M2, 0x3, false }, // 2659 |
| 2668 | { PseudoVRSUB_VX_M4_MASK, PseudoVRSUB_VX_M4, 0x3, false }, // 2660 |
| 2669 | { PseudoVRSUB_VX_M8_MASK, PseudoVRSUB_VX_M8, 0x3, false }, // 2661 |
| 2670 | { PseudoVRSUB_VX_MF2_MASK, PseudoVRSUB_VX_MF2, 0x3, false }, // 2662 |
| 2671 | { PseudoVRSUB_VX_MF4_MASK, PseudoVRSUB_VX_MF4, 0x3, false }, // 2663 |
| 2672 | { PseudoVRSUB_VX_MF8_MASK, PseudoVRSUB_VX_MF8, 0x3, false }, // 2664 |
| 2673 | { PseudoVSADDU_VI_M1_MASK, PseudoVSADDU_VI_M1, 0x3, false }, // 2665 |
| 2674 | { PseudoVSADDU_VI_M2_MASK, PseudoVSADDU_VI_M2, 0x3, false }, // 2666 |
| 2675 | { PseudoVSADDU_VI_M4_MASK, PseudoVSADDU_VI_M4, 0x3, false }, // 2667 |
| 2676 | { PseudoVSADDU_VI_M8_MASK, PseudoVSADDU_VI_M8, 0x3, false }, // 2668 |
| 2677 | { PseudoVSADDU_VI_MF2_MASK, PseudoVSADDU_VI_MF2, 0x3, false }, // 2669 |
| 2678 | { PseudoVSADDU_VI_MF4_MASK, PseudoVSADDU_VI_MF4, 0x3, false }, // 2670 |
| 2679 | { PseudoVSADDU_VI_MF8_MASK, PseudoVSADDU_VI_MF8, 0x3, false }, // 2671 |
| 2680 | { PseudoVSADDU_VV_M1_MASK, PseudoVSADDU_VV_M1, 0x3, false }, // 2672 |
| 2681 | { PseudoVSADDU_VV_M2_MASK, PseudoVSADDU_VV_M2, 0x3, false }, // 2673 |
| 2682 | { PseudoVSADDU_VV_M4_MASK, PseudoVSADDU_VV_M4, 0x3, false }, // 2674 |
| 2683 | { PseudoVSADDU_VV_M8_MASK, PseudoVSADDU_VV_M8, 0x3, false }, // 2675 |
| 2684 | { PseudoVSADDU_VV_MF2_MASK, PseudoVSADDU_VV_MF2, 0x3, false }, // 2676 |
| 2685 | { PseudoVSADDU_VV_MF4_MASK, PseudoVSADDU_VV_MF4, 0x3, false }, // 2677 |
| 2686 | { PseudoVSADDU_VV_MF8_MASK, PseudoVSADDU_VV_MF8, 0x3, false }, // 2678 |
| 2687 | { PseudoVSADDU_VX_M1_MASK, PseudoVSADDU_VX_M1, 0x3, false }, // 2679 |
| 2688 | { PseudoVSADDU_VX_M2_MASK, PseudoVSADDU_VX_M2, 0x3, false }, // 2680 |
| 2689 | { PseudoVSADDU_VX_M4_MASK, PseudoVSADDU_VX_M4, 0x3, false }, // 2681 |
| 2690 | { PseudoVSADDU_VX_M8_MASK, PseudoVSADDU_VX_M8, 0x3, false }, // 2682 |
| 2691 | { PseudoVSADDU_VX_MF2_MASK, PseudoVSADDU_VX_MF2, 0x3, false }, // 2683 |
| 2692 | { PseudoVSADDU_VX_MF4_MASK, PseudoVSADDU_VX_MF4, 0x3, false }, // 2684 |
| 2693 | { PseudoVSADDU_VX_MF8_MASK, PseudoVSADDU_VX_MF8, 0x3, false }, // 2685 |
| 2694 | { PseudoVSADD_VI_M1_MASK, PseudoVSADD_VI_M1, 0x3, false }, // 2686 |
| 2695 | { PseudoVSADD_VI_M2_MASK, PseudoVSADD_VI_M2, 0x3, false }, // 2687 |
| 2696 | { PseudoVSADD_VI_M4_MASK, PseudoVSADD_VI_M4, 0x3, false }, // 2688 |
| 2697 | { PseudoVSADD_VI_M8_MASK, PseudoVSADD_VI_M8, 0x3, false }, // 2689 |
| 2698 | { PseudoVSADD_VI_MF2_MASK, PseudoVSADD_VI_MF2, 0x3, false }, // 2690 |
| 2699 | { PseudoVSADD_VI_MF4_MASK, PseudoVSADD_VI_MF4, 0x3, false }, // 2691 |
| 2700 | { PseudoVSADD_VI_MF8_MASK, PseudoVSADD_VI_MF8, 0x3, false }, // 2692 |
| 2701 | { PseudoVSADD_VV_M1_MASK, PseudoVSADD_VV_M1, 0x3, false }, // 2693 |
| 2702 | { PseudoVSADD_VV_M2_MASK, PseudoVSADD_VV_M2, 0x3, false }, // 2694 |
| 2703 | { PseudoVSADD_VV_M4_MASK, PseudoVSADD_VV_M4, 0x3, false }, // 2695 |
| 2704 | { PseudoVSADD_VV_M8_MASK, PseudoVSADD_VV_M8, 0x3, false }, // 2696 |
| 2705 | { PseudoVSADD_VV_MF2_MASK, PseudoVSADD_VV_MF2, 0x3, false }, // 2697 |
| 2706 | { PseudoVSADD_VV_MF4_MASK, PseudoVSADD_VV_MF4, 0x3, false }, // 2698 |
| 2707 | { PseudoVSADD_VV_MF8_MASK, PseudoVSADD_VV_MF8, 0x3, false }, // 2699 |
| 2708 | { PseudoVSADD_VX_M1_MASK, PseudoVSADD_VX_M1, 0x3, false }, // 2700 |
| 2709 | { PseudoVSADD_VX_M2_MASK, PseudoVSADD_VX_M2, 0x3, false }, // 2701 |
| 2710 | { PseudoVSADD_VX_M4_MASK, PseudoVSADD_VX_M4, 0x3, false }, // 2702 |
| 2711 | { PseudoVSADD_VX_M8_MASK, PseudoVSADD_VX_M8, 0x3, false }, // 2703 |
| 2712 | { PseudoVSADD_VX_MF2_MASK, PseudoVSADD_VX_MF2, 0x3, false }, // 2704 |
| 2713 | { PseudoVSADD_VX_MF4_MASK, PseudoVSADD_VX_MF4, 0x3, false }, // 2705 |
| 2714 | { PseudoVSADD_VX_MF8_MASK, PseudoVSADD_VX_MF8, 0x3, false }, // 2706 |
| 2715 | { PseudoVSEXT_VF2_M1_MASK, PseudoVSEXT_VF2_M1, 0x2, false }, // 2707 |
| 2716 | { PseudoVSEXT_VF2_M2_MASK, PseudoVSEXT_VF2_M2, 0x2, false }, // 2708 |
| 2717 | { PseudoVSEXT_VF2_M4_MASK, PseudoVSEXT_VF2_M4, 0x2, false }, // 2709 |
| 2718 | { PseudoVSEXT_VF2_M8_MASK, PseudoVSEXT_VF2_M8, 0x2, false }, // 2710 |
| 2719 | { PseudoVSEXT_VF2_MF2_MASK, PseudoVSEXT_VF2_MF2, 0x2, false }, // 2711 |
| 2720 | { PseudoVSEXT_VF2_MF4_MASK, PseudoVSEXT_VF2_MF4, 0x2, false }, // 2712 |
| 2721 | { PseudoVSEXT_VF4_M1_MASK, PseudoVSEXT_VF4_M1, 0x2, false }, // 2713 |
| 2722 | { PseudoVSEXT_VF4_M2_MASK, PseudoVSEXT_VF4_M2, 0x2, false }, // 2714 |
| 2723 | { PseudoVSEXT_VF4_M4_MASK, PseudoVSEXT_VF4_M4, 0x2, false }, // 2715 |
| 2724 | { PseudoVSEXT_VF4_M8_MASK, PseudoVSEXT_VF4_M8, 0x2, false }, // 2716 |
| 2725 | { PseudoVSEXT_VF4_MF2_MASK, PseudoVSEXT_VF4_MF2, 0x2, false }, // 2717 |
| 2726 | { PseudoVSEXT_VF8_M1_MASK, PseudoVSEXT_VF8_M1, 0x2, false }, // 2718 |
| 2727 | { PseudoVSEXT_VF8_M2_MASK, PseudoVSEXT_VF8_M2, 0x2, false }, // 2719 |
| 2728 | { PseudoVSEXT_VF8_M4_MASK, PseudoVSEXT_VF8_M4, 0x2, false }, // 2720 |
| 2729 | { PseudoVSEXT_VF8_M8_MASK, PseudoVSEXT_VF8_M8, 0x2, false }, // 2721 |
| 2730 | { PseudoVSLIDE1DOWN_VX_M1_MASK, PseudoVSLIDE1DOWN_VX_M1, 0x3, false }, // 2722 |
| 2731 | { PseudoVSLIDE1DOWN_VX_M2_MASK, PseudoVSLIDE1DOWN_VX_M2, 0x3, false }, // 2723 |
| 2732 | { PseudoVSLIDE1DOWN_VX_M4_MASK, PseudoVSLIDE1DOWN_VX_M4, 0x3, false }, // 2724 |
| 2733 | { PseudoVSLIDE1DOWN_VX_M8_MASK, PseudoVSLIDE1DOWN_VX_M8, 0x3, false }, // 2725 |
| 2734 | { PseudoVSLIDE1DOWN_VX_MF2_MASK, PseudoVSLIDE1DOWN_VX_MF2, 0x3, false }, // 2726 |
| 2735 | { PseudoVSLIDE1DOWN_VX_MF4_MASK, PseudoVSLIDE1DOWN_VX_MF4, 0x3, false }, // 2727 |
| 2736 | { PseudoVSLIDE1DOWN_VX_MF8_MASK, PseudoVSLIDE1DOWN_VX_MF8, 0x3, false }, // 2728 |
| 2737 | { PseudoVSLIDE1UP_VX_M1_MASK, PseudoVSLIDE1UP_VX_M1, 0x3, false }, // 2729 |
| 2738 | { PseudoVSLIDE1UP_VX_M2_MASK, PseudoVSLIDE1UP_VX_M2, 0x3, false }, // 2730 |
| 2739 | { PseudoVSLIDE1UP_VX_M4_MASK, PseudoVSLIDE1UP_VX_M4, 0x3, false }, // 2731 |
| 2740 | { PseudoVSLIDE1UP_VX_M8_MASK, PseudoVSLIDE1UP_VX_M8, 0x3, false }, // 2732 |
| 2741 | { PseudoVSLIDE1UP_VX_MF2_MASK, PseudoVSLIDE1UP_VX_MF2, 0x3, false }, // 2733 |
| 2742 | { PseudoVSLIDE1UP_VX_MF4_MASK, PseudoVSLIDE1UP_VX_MF4, 0x3, false }, // 2734 |
| 2743 | { PseudoVSLIDE1UP_VX_MF8_MASK, PseudoVSLIDE1UP_VX_MF8, 0x3, false }, // 2735 |
| 2744 | { PseudoVSLIDEDOWN_VI_M1_MASK, PseudoVSLIDEDOWN_VI_M1, 0x3, false }, // 2736 |
| 2745 | { PseudoVSLIDEDOWN_VI_M2_MASK, PseudoVSLIDEDOWN_VI_M2, 0x3, false }, // 2737 |
| 2746 | { PseudoVSLIDEDOWN_VI_M4_MASK, PseudoVSLIDEDOWN_VI_M4, 0x3, false }, // 2738 |
| 2747 | { PseudoVSLIDEDOWN_VI_M8_MASK, PseudoVSLIDEDOWN_VI_M8, 0x3, false }, // 2739 |
| 2748 | { PseudoVSLIDEDOWN_VI_MF2_MASK, PseudoVSLIDEDOWN_VI_MF2, 0x3, false }, // 2740 |
| 2749 | { PseudoVSLIDEDOWN_VI_MF4_MASK, PseudoVSLIDEDOWN_VI_MF4, 0x3, false }, // 2741 |
| 2750 | { PseudoVSLIDEDOWN_VI_MF8_MASK, PseudoVSLIDEDOWN_VI_MF8, 0x3, false }, // 2742 |
| 2751 | { PseudoVSLIDEDOWN_VX_M1_MASK, PseudoVSLIDEDOWN_VX_M1, 0x3, false }, // 2743 |
| 2752 | { PseudoVSLIDEDOWN_VX_M2_MASK, PseudoVSLIDEDOWN_VX_M2, 0x3, false }, // 2744 |
| 2753 | { PseudoVSLIDEDOWN_VX_M4_MASK, PseudoVSLIDEDOWN_VX_M4, 0x3, false }, // 2745 |
| 2754 | { PseudoVSLIDEDOWN_VX_M8_MASK, PseudoVSLIDEDOWN_VX_M8, 0x3, false }, // 2746 |
| 2755 | { PseudoVSLIDEDOWN_VX_MF2_MASK, PseudoVSLIDEDOWN_VX_MF2, 0x3, false }, // 2747 |
| 2756 | { PseudoVSLIDEDOWN_VX_MF4_MASK, PseudoVSLIDEDOWN_VX_MF4, 0x3, false }, // 2748 |
| 2757 | { PseudoVSLIDEDOWN_VX_MF8_MASK, PseudoVSLIDEDOWN_VX_MF8, 0x3, false }, // 2749 |
| 2758 | { PseudoVSLIDEUP_VI_M1_MASK, PseudoVSLIDEUP_VI_M1, 0x3, false }, // 2750 |
| 2759 | { PseudoVSLIDEUP_VI_M2_MASK, PseudoVSLIDEUP_VI_M2, 0x3, false }, // 2751 |
| 2760 | { PseudoVSLIDEUP_VI_M4_MASK, PseudoVSLIDEUP_VI_M4, 0x3, false }, // 2752 |
| 2761 | { PseudoVSLIDEUP_VI_M8_MASK, PseudoVSLIDEUP_VI_M8, 0x3, false }, // 2753 |
| 2762 | { PseudoVSLIDEUP_VI_MF2_MASK, PseudoVSLIDEUP_VI_MF2, 0x3, false }, // 2754 |
| 2763 | { PseudoVSLIDEUP_VI_MF4_MASK, PseudoVSLIDEUP_VI_MF4, 0x3, false }, // 2755 |
| 2764 | { PseudoVSLIDEUP_VI_MF8_MASK, PseudoVSLIDEUP_VI_MF8, 0x3, false }, // 2756 |
| 2765 | { PseudoVSLIDEUP_VX_M1_MASK, PseudoVSLIDEUP_VX_M1, 0x3, false }, // 2757 |
| 2766 | { PseudoVSLIDEUP_VX_M2_MASK, PseudoVSLIDEUP_VX_M2, 0x3, false }, // 2758 |
| 2767 | { PseudoVSLIDEUP_VX_M4_MASK, PseudoVSLIDEUP_VX_M4, 0x3, false }, // 2759 |
| 2768 | { PseudoVSLIDEUP_VX_M8_MASK, PseudoVSLIDEUP_VX_M8, 0x3, false }, // 2760 |
| 2769 | { PseudoVSLIDEUP_VX_MF2_MASK, PseudoVSLIDEUP_VX_MF2, 0x3, false }, // 2761 |
| 2770 | { PseudoVSLIDEUP_VX_MF4_MASK, PseudoVSLIDEUP_VX_MF4, 0x3, false }, // 2762 |
| 2771 | { PseudoVSLIDEUP_VX_MF8_MASK, PseudoVSLIDEUP_VX_MF8, 0x3, false }, // 2763 |
| 2772 | { PseudoVSLL_VI_M1_MASK, PseudoVSLL_VI_M1, 0x3, false }, // 2764 |
| 2773 | { PseudoVSLL_VI_M2_MASK, PseudoVSLL_VI_M2, 0x3, false }, // 2765 |
| 2774 | { PseudoVSLL_VI_M4_MASK, PseudoVSLL_VI_M4, 0x3, false }, // 2766 |
| 2775 | { PseudoVSLL_VI_M8_MASK, PseudoVSLL_VI_M8, 0x3, false }, // 2767 |
| 2776 | { PseudoVSLL_VI_MF2_MASK, PseudoVSLL_VI_MF2, 0x3, false }, // 2768 |
| 2777 | { PseudoVSLL_VI_MF4_MASK, PseudoVSLL_VI_MF4, 0x3, false }, // 2769 |
| 2778 | { PseudoVSLL_VI_MF8_MASK, PseudoVSLL_VI_MF8, 0x3, false }, // 2770 |
| 2779 | { PseudoVSLL_VV_M1_MASK, PseudoVSLL_VV_M1, 0x3, false }, // 2771 |
| 2780 | { PseudoVSLL_VV_M2_MASK, PseudoVSLL_VV_M2, 0x3, false }, // 2772 |
| 2781 | { PseudoVSLL_VV_M4_MASK, PseudoVSLL_VV_M4, 0x3, false }, // 2773 |
| 2782 | { PseudoVSLL_VV_M8_MASK, PseudoVSLL_VV_M8, 0x3, false }, // 2774 |
| 2783 | { PseudoVSLL_VV_MF2_MASK, PseudoVSLL_VV_MF2, 0x3, false }, // 2775 |
| 2784 | { PseudoVSLL_VV_MF4_MASK, PseudoVSLL_VV_MF4, 0x3, false }, // 2776 |
| 2785 | { PseudoVSLL_VV_MF8_MASK, PseudoVSLL_VV_MF8, 0x3, false }, // 2777 |
| 2786 | { PseudoVSLL_VX_M1_MASK, PseudoVSLL_VX_M1, 0x3, false }, // 2778 |
| 2787 | { PseudoVSLL_VX_M2_MASK, PseudoVSLL_VX_M2, 0x3, false }, // 2779 |
| 2788 | { PseudoVSLL_VX_M4_MASK, PseudoVSLL_VX_M4, 0x3, false }, // 2780 |
| 2789 | { PseudoVSLL_VX_M8_MASK, PseudoVSLL_VX_M8, 0x3, false }, // 2781 |
| 2790 | { PseudoVSLL_VX_MF2_MASK, PseudoVSLL_VX_MF2, 0x3, false }, // 2782 |
| 2791 | { PseudoVSLL_VX_MF4_MASK, PseudoVSLL_VX_MF4, 0x3, false }, // 2783 |
| 2792 | { PseudoVSLL_VX_MF8_MASK, PseudoVSLL_VX_MF8, 0x3, false }, // 2784 |
| 2793 | { PseudoVSMUL_VV_M1_MASK, PseudoVSMUL_VV_M1, 0x3, false }, // 2785 |
| 2794 | { PseudoVSMUL_VV_M2_MASK, PseudoVSMUL_VV_M2, 0x3, false }, // 2786 |
| 2795 | { PseudoVSMUL_VV_M4_MASK, PseudoVSMUL_VV_M4, 0x3, false }, // 2787 |
| 2796 | { PseudoVSMUL_VV_M8_MASK, PseudoVSMUL_VV_M8, 0x3, false }, // 2788 |
| 2797 | { PseudoVSMUL_VV_MF2_MASK, PseudoVSMUL_VV_MF2, 0x3, false }, // 2789 |
| 2798 | { PseudoVSMUL_VV_MF4_MASK, PseudoVSMUL_VV_MF4, 0x3, false }, // 2790 |
| 2799 | { PseudoVSMUL_VV_MF8_MASK, PseudoVSMUL_VV_MF8, 0x3, false }, // 2791 |
| 2800 | { PseudoVSMUL_VX_M1_MASK, PseudoVSMUL_VX_M1, 0x3, false }, // 2792 |
| 2801 | { PseudoVSMUL_VX_M2_MASK, PseudoVSMUL_VX_M2, 0x3, false }, // 2793 |
| 2802 | { PseudoVSMUL_VX_M4_MASK, PseudoVSMUL_VX_M4, 0x3, false }, // 2794 |
| 2803 | { PseudoVSMUL_VX_M8_MASK, PseudoVSMUL_VX_M8, 0x3, false }, // 2795 |
| 2804 | { PseudoVSMUL_VX_MF2_MASK, PseudoVSMUL_VX_MF2, 0x3, false }, // 2796 |
| 2805 | { PseudoVSMUL_VX_MF4_MASK, PseudoVSMUL_VX_MF4, 0x3, false }, // 2797 |
| 2806 | { PseudoVSMUL_VX_MF8_MASK, PseudoVSMUL_VX_MF8, 0x3, false }, // 2798 |
| 2807 | { PseudoVSRA_VI_M1_MASK, PseudoVSRA_VI_M1, 0x3, false }, // 2799 |
| 2808 | { PseudoVSRA_VI_M2_MASK, PseudoVSRA_VI_M2, 0x3, false }, // 2800 |
| 2809 | { PseudoVSRA_VI_M4_MASK, PseudoVSRA_VI_M4, 0x3, false }, // 2801 |
| 2810 | { PseudoVSRA_VI_M8_MASK, PseudoVSRA_VI_M8, 0x3, false }, // 2802 |
| 2811 | { PseudoVSRA_VI_MF2_MASK, PseudoVSRA_VI_MF2, 0x3, false }, // 2803 |
| 2812 | { PseudoVSRA_VI_MF4_MASK, PseudoVSRA_VI_MF4, 0x3, false }, // 2804 |
| 2813 | { PseudoVSRA_VI_MF8_MASK, PseudoVSRA_VI_MF8, 0x3, false }, // 2805 |
| 2814 | { PseudoVSRA_VV_M1_MASK, PseudoVSRA_VV_M1, 0x3, false }, // 2806 |
| 2815 | { PseudoVSRA_VV_M2_MASK, PseudoVSRA_VV_M2, 0x3, false }, // 2807 |
| 2816 | { PseudoVSRA_VV_M4_MASK, PseudoVSRA_VV_M4, 0x3, false }, // 2808 |
| 2817 | { PseudoVSRA_VV_M8_MASK, PseudoVSRA_VV_M8, 0x3, false }, // 2809 |
| 2818 | { PseudoVSRA_VV_MF2_MASK, PseudoVSRA_VV_MF2, 0x3, false }, // 2810 |
| 2819 | { PseudoVSRA_VV_MF4_MASK, PseudoVSRA_VV_MF4, 0x3, false }, // 2811 |
| 2820 | { PseudoVSRA_VV_MF8_MASK, PseudoVSRA_VV_MF8, 0x3, false }, // 2812 |
| 2821 | { PseudoVSRA_VX_M1_MASK, PseudoVSRA_VX_M1, 0x3, false }, // 2813 |
| 2822 | { PseudoVSRA_VX_M2_MASK, PseudoVSRA_VX_M2, 0x3, false }, // 2814 |
| 2823 | { PseudoVSRA_VX_M4_MASK, PseudoVSRA_VX_M4, 0x3, false }, // 2815 |
| 2824 | { PseudoVSRA_VX_M8_MASK, PseudoVSRA_VX_M8, 0x3, false }, // 2816 |
| 2825 | { PseudoVSRA_VX_MF2_MASK, PseudoVSRA_VX_MF2, 0x3, false }, // 2817 |
| 2826 | { PseudoVSRA_VX_MF4_MASK, PseudoVSRA_VX_MF4, 0x3, false }, // 2818 |
| 2827 | { PseudoVSRA_VX_MF8_MASK, PseudoVSRA_VX_MF8, 0x3, false }, // 2819 |
| 2828 | { PseudoVSRL_VI_M1_MASK, PseudoVSRL_VI_M1, 0x3, false }, // 2820 |
| 2829 | { PseudoVSRL_VI_M2_MASK, PseudoVSRL_VI_M2, 0x3, false }, // 2821 |
| 2830 | { PseudoVSRL_VI_M4_MASK, PseudoVSRL_VI_M4, 0x3, false }, // 2822 |
| 2831 | { PseudoVSRL_VI_M8_MASK, PseudoVSRL_VI_M8, 0x3, false }, // 2823 |
| 2832 | { PseudoVSRL_VI_MF2_MASK, PseudoVSRL_VI_MF2, 0x3, false }, // 2824 |
| 2833 | { PseudoVSRL_VI_MF4_MASK, PseudoVSRL_VI_MF4, 0x3, false }, // 2825 |
| 2834 | { PseudoVSRL_VI_MF8_MASK, PseudoVSRL_VI_MF8, 0x3, false }, // 2826 |
| 2835 | { PseudoVSRL_VV_M1_MASK, PseudoVSRL_VV_M1, 0x3, false }, // 2827 |
| 2836 | { PseudoVSRL_VV_M2_MASK, PseudoVSRL_VV_M2, 0x3, false }, // 2828 |
| 2837 | { PseudoVSRL_VV_M4_MASK, PseudoVSRL_VV_M4, 0x3, false }, // 2829 |
| 2838 | { PseudoVSRL_VV_M8_MASK, PseudoVSRL_VV_M8, 0x3, false }, // 2830 |
| 2839 | { PseudoVSRL_VV_MF2_MASK, PseudoVSRL_VV_MF2, 0x3, false }, // 2831 |
| 2840 | { PseudoVSRL_VV_MF4_MASK, PseudoVSRL_VV_MF4, 0x3, false }, // 2832 |
| 2841 | { PseudoVSRL_VV_MF8_MASK, PseudoVSRL_VV_MF8, 0x3, false }, // 2833 |
| 2842 | { PseudoVSRL_VX_M1_MASK, PseudoVSRL_VX_M1, 0x3, false }, // 2834 |
| 2843 | { PseudoVSRL_VX_M2_MASK, PseudoVSRL_VX_M2, 0x3, false }, // 2835 |
| 2844 | { PseudoVSRL_VX_M4_MASK, PseudoVSRL_VX_M4, 0x3, false }, // 2836 |
| 2845 | { PseudoVSRL_VX_M8_MASK, PseudoVSRL_VX_M8, 0x3, false }, // 2837 |
| 2846 | { PseudoVSRL_VX_MF2_MASK, PseudoVSRL_VX_MF2, 0x3, false }, // 2838 |
| 2847 | { PseudoVSRL_VX_MF4_MASK, PseudoVSRL_VX_MF4, 0x3, false }, // 2839 |
| 2848 | { PseudoVSRL_VX_MF8_MASK, PseudoVSRL_VX_MF8, 0x3, false }, // 2840 |
| 2849 | { PseudoVSSRA_VI_M1_MASK, PseudoVSSRA_VI_M1, 0x3, false }, // 2841 |
| 2850 | { PseudoVSSRA_VI_M2_MASK, PseudoVSSRA_VI_M2, 0x3, false }, // 2842 |
| 2851 | { PseudoVSSRA_VI_M4_MASK, PseudoVSSRA_VI_M4, 0x3, false }, // 2843 |
| 2852 | { PseudoVSSRA_VI_M8_MASK, PseudoVSSRA_VI_M8, 0x3, false }, // 2844 |
| 2853 | { PseudoVSSRA_VI_MF2_MASK, PseudoVSSRA_VI_MF2, 0x3, false }, // 2845 |
| 2854 | { PseudoVSSRA_VI_MF4_MASK, PseudoVSSRA_VI_MF4, 0x3, false }, // 2846 |
| 2855 | { PseudoVSSRA_VI_MF8_MASK, PseudoVSSRA_VI_MF8, 0x3, false }, // 2847 |
| 2856 | { PseudoVSSRA_VV_M1_MASK, PseudoVSSRA_VV_M1, 0x3, false }, // 2848 |
| 2857 | { PseudoVSSRA_VV_M2_MASK, PseudoVSSRA_VV_M2, 0x3, false }, // 2849 |
| 2858 | { PseudoVSSRA_VV_M4_MASK, PseudoVSSRA_VV_M4, 0x3, false }, // 2850 |
| 2859 | { PseudoVSSRA_VV_M8_MASK, PseudoVSSRA_VV_M8, 0x3, false }, // 2851 |
| 2860 | { PseudoVSSRA_VV_MF2_MASK, PseudoVSSRA_VV_MF2, 0x3, false }, // 2852 |
| 2861 | { PseudoVSSRA_VV_MF4_MASK, PseudoVSSRA_VV_MF4, 0x3, false }, // 2853 |
| 2862 | { PseudoVSSRA_VV_MF8_MASK, PseudoVSSRA_VV_MF8, 0x3, false }, // 2854 |
| 2863 | { PseudoVSSRA_VX_M1_MASK, PseudoVSSRA_VX_M1, 0x3, false }, // 2855 |
| 2864 | { PseudoVSSRA_VX_M2_MASK, PseudoVSSRA_VX_M2, 0x3, false }, // 2856 |
| 2865 | { PseudoVSSRA_VX_M4_MASK, PseudoVSSRA_VX_M4, 0x3, false }, // 2857 |
| 2866 | { PseudoVSSRA_VX_M8_MASK, PseudoVSSRA_VX_M8, 0x3, false }, // 2858 |
| 2867 | { PseudoVSSRA_VX_MF2_MASK, PseudoVSSRA_VX_MF2, 0x3, false }, // 2859 |
| 2868 | { PseudoVSSRA_VX_MF4_MASK, PseudoVSSRA_VX_MF4, 0x3, false }, // 2860 |
| 2869 | { PseudoVSSRA_VX_MF8_MASK, PseudoVSSRA_VX_MF8, 0x3, false }, // 2861 |
| 2870 | { PseudoVSSRL_VI_M1_MASK, PseudoVSSRL_VI_M1, 0x3, false }, // 2862 |
| 2871 | { PseudoVSSRL_VI_M2_MASK, PseudoVSSRL_VI_M2, 0x3, false }, // 2863 |
| 2872 | { PseudoVSSRL_VI_M4_MASK, PseudoVSSRL_VI_M4, 0x3, false }, // 2864 |
| 2873 | { PseudoVSSRL_VI_M8_MASK, PseudoVSSRL_VI_M8, 0x3, false }, // 2865 |
| 2874 | { PseudoVSSRL_VI_MF2_MASK, PseudoVSSRL_VI_MF2, 0x3, false }, // 2866 |
| 2875 | { PseudoVSSRL_VI_MF4_MASK, PseudoVSSRL_VI_MF4, 0x3, false }, // 2867 |
| 2876 | { PseudoVSSRL_VI_MF8_MASK, PseudoVSSRL_VI_MF8, 0x3, false }, // 2868 |
| 2877 | { PseudoVSSRL_VV_M1_MASK, PseudoVSSRL_VV_M1, 0x3, false }, // 2869 |
| 2878 | { PseudoVSSRL_VV_M2_MASK, PseudoVSSRL_VV_M2, 0x3, false }, // 2870 |
| 2879 | { PseudoVSSRL_VV_M4_MASK, PseudoVSSRL_VV_M4, 0x3, false }, // 2871 |
| 2880 | { PseudoVSSRL_VV_M8_MASK, PseudoVSSRL_VV_M8, 0x3, false }, // 2872 |
| 2881 | { PseudoVSSRL_VV_MF2_MASK, PseudoVSSRL_VV_MF2, 0x3, false }, // 2873 |
| 2882 | { PseudoVSSRL_VV_MF4_MASK, PseudoVSSRL_VV_MF4, 0x3, false }, // 2874 |
| 2883 | { PseudoVSSRL_VV_MF8_MASK, PseudoVSSRL_VV_MF8, 0x3, false }, // 2875 |
| 2884 | { PseudoVSSRL_VX_M1_MASK, PseudoVSSRL_VX_M1, 0x3, false }, // 2876 |
| 2885 | { PseudoVSSRL_VX_M2_MASK, PseudoVSSRL_VX_M2, 0x3, false }, // 2877 |
| 2886 | { PseudoVSSRL_VX_M4_MASK, PseudoVSSRL_VX_M4, 0x3, false }, // 2878 |
| 2887 | { PseudoVSSRL_VX_M8_MASK, PseudoVSSRL_VX_M8, 0x3, false }, // 2879 |
| 2888 | { PseudoVSSRL_VX_MF2_MASK, PseudoVSSRL_VX_MF2, 0x3, false }, // 2880 |
| 2889 | { PseudoVSSRL_VX_MF4_MASK, PseudoVSSRL_VX_MF4, 0x3, false }, // 2881 |
| 2890 | { PseudoVSSRL_VX_MF8_MASK, PseudoVSSRL_VX_MF8, 0x3, false }, // 2882 |
| 2891 | { PseudoVSSUBU_VV_M1_MASK, PseudoVSSUBU_VV_M1, 0x3, false }, // 2883 |
| 2892 | { PseudoVSSUBU_VV_M2_MASK, PseudoVSSUBU_VV_M2, 0x3, false }, // 2884 |
| 2893 | { PseudoVSSUBU_VV_M4_MASK, PseudoVSSUBU_VV_M4, 0x3, false }, // 2885 |
| 2894 | { PseudoVSSUBU_VV_M8_MASK, PseudoVSSUBU_VV_M8, 0x3, false }, // 2886 |
| 2895 | { PseudoVSSUBU_VV_MF2_MASK, PseudoVSSUBU_VV_MF2, 0x3, false }, // 2887 |
| 2896 | { PseudoVSSUBU_VV_MF4_MASK, PseudoVSSUBU_VV_MF4, 0x3, false }, // 2888 |
| 2897 | { PseudoVSSUBU_VV_MF8_MASK, PseudoVSSUBU_VV_MF8, 0x3, false }, // 2889 |
| 2898 | { PseudoVSSUBU_VX_M1_MASK, PseudoVSSUBU_VX_M1, 0x3, false }, // 2890 |
| 2899 | { PseudoVSSUBU_VX_M2_MASK, PseudoVSSUBU_VX_M2, 0x3, false }, // 2891 |
| 2900 | { PseudoVSSUBU_VX_M4_MASK, PseudoVSSUBU_VX_M4, 0x3, false }, // 2892 |
| 2901 | { PseudoVSSUBU_VX_M8_MASK, PseudoVSSUBU_VX_M8, 0x3, false }, // 2893 |
| 2902 | { PseudoVSSUBU_VX_MF2_MASK, PseudoVSSUBU_VX_MF2, 0x3, false }, // 2894 |
| 2903 | { PseudoVSSUBU_VX_MF4_MASK, PseudoVSSUBU_VX_MF4, 0x3, false }, // 2895 |
| 2904 | { PseudoVSSUBU_VX_MF8_MASK, PseudoVSSUBU_VX_MF8, 0x3, false }, // 2896 |
| 2905 | { PseudoVSSUB_VV_M1_MASK, PseudoVSSUB_VV_M1, 0x3, false }, // 2897 |
| 2906 | { PseudoVSSUB_VV_M2_MASK, PseudoVSSUB_VV_M2, 0x3, false }, // 2898 |
| 2907 | { PseudoVSSUB_VV_M4_MASK, PseudoVSSUB_VV_M4, 0x3, false }, // 2899 |
| 2908 | { PseudoVSSUB_VV_M8_MASK, PseudoVSSUB_VV_M8, 0x3, false }, // 2900 |
| 2909 | { PseudoVSSUB_VV_MF2_MASK, PseudoVSSUB_VV_MF2, 0x3, false }, // 2901 |
| 2910 | { PseudoVSSUB_VV_MF4_MASK, PseudoVSSUB_VV_MF4, 0x3, false }, // 2902 |
| 2911 | { PseudoVSSUB_VV_MF8_MASK, PseudoVSSUB_VV_MF8, 0x3, false }, // 2903 |
| 2912 | { PseudoVSSUB_VX_M1_MASK, PseudoVSSUB_VX_M1, 0x3, false }, // 2904 |
| 2913 | { PseudoVSSUB_VX_M2_MASK, PseudoVSSUB_VX_M2, 0x3, false }, // 2905 |
| 2914 | { PseudoVSSUB_VX_M4_MASK, PseudoVSSUB_VX_M4, 0x3, false }, // 2906 |
| 2915 | { PseudoVSSUB_VX_M8_MASK, PseudoVSSUB_VX_M8, 0x3, false }, // 2907 |
| 2916 | { PseudoVSSUB_VX_MF2_MASK, PseudoVSSUB_VX_MF2, 0x3, false }, // 2908 |
| 2917 | { PseudoVSSUB_VX_MF4_MASK, PseudoVSSUB_VX_MF4, 0x3, false }, // 2909 |
| 2918 | { PseudoVSSUB_VX_MF8_MASK, PseudoVSSUB_VX_MF8, 0x3, false }, // 2910 |
| 2919 | { PseudoVSUB_VV_M1_MASK, PseudoVSUB_VV_M1, 0x3, false }, // 2911 |
| 2920 | { PseudoVSUB_VV_M2_MASK, PseudoVSUB_VV_M2, 0x3, false }, // 2912 |
| 2921 | { PseudoVSUB_VV_M4_MASK, PseudoVSUB_VV_M4, 0x3, false }, // 2913 |
| 2922 | { PseudoVSUB_VV_M8_MASK, PseudoVSUB_VV_M8, 0x3, false }, // 2914 |
| 2923 | { PseudoVSUB_VV_MF2_MASK, PseudoVSUB_VV_MF2, 0x3, false }, // 2915 |
| 2924 | { PseudoVSUB_VV_MF4_MASK, PseudoVSUB_VV_MF4, 0x3, false }, // 2916 |
| 2925 | { PseudoVSUB_VV_MF8_MASK, PseudoVSUB_VV_MF8, 0x3, false }, // 2917 |
| 2926 | { PseudoVSUB_VX_M1_MASK, PseudoVSUB_VX_M1, 0x3, false }, // 2918 |
| 2927 | { PseudoVSUB_VX_M2_MASK, PseudoVSUB_VX_M2, 0x3, false }, // 2919 |
| 2928 | { PseudoVSUB_VX_M4_MASK, PseudoVSUB_VX_M4, 0x3, false }, // 2920 |
| 2929 | { PseudoVSUB_VX_M8_MASK, PseudoVSUB_VX_M8, 0x3, false }, // 2921 |
| 2930 | { PseudoVSUB_VX_MF2_MASK, PseudoVSUB_VX_MF2, 0x3, false }, // 2922 |
| 2931 | { PseudoVSUB_VX_MF4_MASK, PseudoVSUB_VX_MF4, 0x3, false }, // 2923 |
| 2932 | { PseudoVSUB_VX_MF8_MASK, PseudoVSUB_VX_MF8, 0x3, false }, // 2924 |
| 2933 | { PseudoVWADDU_VV_M1_MASK, PseudoVWADDU_VV_M1, 0x3, false }, // 2925 |
| 2934 | { PseudoVWADDU_VV_M2_MASK, PseudoVWADDU_VV_M2, 0x3, false }, // 2926 |
| 2935 | { PseudoVWADDU_VV_M4_MASK, PseudoVWADDU_VV_M4, 0x3, false }, // 2927 |
| 2936 | { PseudoVWADDU_VV_MF2_MASK, PseudoVWADDU_VV_MF2, 0x3, false }, // 2928 |
| 2937 | { PseudoVWADDU_VV_MF4_MASK, PseudoVWADDU_VV_MF4, 0x3, false }, // 2929 |
| 2938 | { PseudoVWADDU_VV_MF8_MASK, PseudoVWADDU_VV_MF8, 0x3, false }, // 2930 |
| 2939 | { PseudoVWADDU_VX_M1_MASK, PseudoVWADDU_VX_M1, 0x3, false }, // 2931 |
| 2940 | { PseudoVWADDU_VX_M2_MASK, PseudoVWADDU_VX_M2, 0x3, false }, // 2932 |
| 2941 | { PseudoVWADDU_VX_M4_MASK, PseudoVWADDU_VX_M4, 0x3, false }, // 2933 |
| 2942 | { PseudoVWADDU_VX_MF2_MASK, PseudoVWADDU_VX_MF2, 0x3, false }, // 2934 |
| 2943 | { PseudoVWADDU_VX_MF4_MASK, PseudoVWADDU_VX_MF4, 0x3, false }, // 2935 |
| 2944 | { PseudoVWADDU_VX_MF8_MASK, PseudoVWADDU_VX_MF8, 0x3, false }, // 2936 |
| 2945 | { PseudoVWADDU_WV_M1_MASK, PseudoVWADDU_WV_M1, 0x3, false }, // 2937 |
| 2946 | { PseudoVWADDU_WV_M1_MASK_TIED, PseudoVWADDU_WV_M1_TIED, 0x2, false }, // 2938 |
| 2947 | { PseudoVWADDU_WV_M2_MASK, PseudoVWADDU_WV_M2, 0x3, false }, // 2939 |
| 2948 | { PseudoVWADDU_WV_M2_MASK_TIED, PseudoVWADDU_WV_M2_TIED, 0x2, false }, // 2940 |
| 2949 | { PseudoVWADDU_WV_M4_MASK, PseudoVWADDU_WV_M4, 0x3, false }, // 2941 |
| 2950 | { PseudoVWADDU_WV_M4_MASK_TIED, PseudoVWADDU_WV_M4_TIED, 0x2, false }, // 2942 |
| 2951 | { PseudoVWADDU_WV_MF2_MASK, PseudoVWADDU_WV_MF2, 0x3, false }, // 2943 |
| 2952 | { PseudoVWADDU_WV_MF2_MASK_TIED, PseudoVWADDU_WV_MF2_TIED, 0x2, false }, // 2944 |
| 2953 | { PseudoVWADDU_WV_MF4_MASK, PseudoVWADDU_WV_MF4, 0x3, false }, // 2945 |
| 2954 | { PseudoVWADDU_WV_MF4_MASK_TIED, PseudoVWADDU_WV_MF4_TIED, 0x2, false }, // 2946 |
| 2955 | { PseudoVWADDU_WV_MF8_MASK, PseudoVWADDU_WV_MF8, 0x3, false }, // 2947 |
| 2956 | { PseudoVWADDU_WV_MF8_MASK_TIED, PseudoVWADDU_WV_MF8_TIED, 0x2, false }, // 2948 |
| 2957 | { PseudoVWADDU_WX_M1_MASK, PseudoVWADDU_WX_M1, 0x3, false }, // 2949 |
| 2958 | { PseudoVWADDU_WX_M2_MASK, PseudoVWADDU_WX_M2, 0x3, false }, // 2950 |
| 2959 | { PseudoVWADDU_WX_M4_MASK, PseudoVWADDU_WX_M4, 0x3, false }, // 2951 |
| 2960 | { PseudoVWADDU_WX_MF2_MASK, PseudoVWADDU_WX_MF2, 0x3, false }, // 2952 |
| 2961 | { PseudoVWADDU_WX_MF4_MASK, PseudoVWADDU_WX_MF4, 0x3, false }, // 2953 |
| 2962 | { PseudoVWADDU_WX_MF8_MASK, PseudoVWADDU_WX_MF8, 0x3, false }, // 2954 |
| 2963 | { PseudoVWADD_VV_M1_MASK, PseudoVWADD_VV_M1, 0x3, false }, // 2955 |
| 2964 | { PseudoVWADD_VV_M2_MASK, PseudoVWADD_VV_M2, 0x3, false }, // 2956 |
| 2965 | { PseudoVWADD_VV_M4_MASK, PseudoVWADD_VV_M4, 0x3, false }, // 2957 |
| 2966 | { PseudoVWADD_VV_MF2_MASK, PseudoVWADD_VV_MF2, 0x3, false }, // 2958 |
| 2967 | { PseudoVWADD_VV_MF4_MASK, PseudoVWADD_VV_MF4, 0x3, false }, // 2959 |
| 2968 | { PseudoVWADD_VV_MF8_MASK, PseudoVWADD_VV_MF8, 0x3, false }, // 2960 |
| 2969 | { PseudoVWADD_VX_M1_MASK, PseudoVWADD_VX_M1, 0x3, false }, // 2961 |
| 2970 | { PseudoVWADD_VX_M2_MASK, PseudoVWADD_VX_M2, 0x3, false }, // 2962 |
| 2971 | { PseudoVWADD_VX_M4_MASK, PseudoVWADD_VX_M4, 0x3, false }, // 2963 |
| 2972 | { PseudoVWADD_VX_MF2_MASK, PseudoVWADD_VX_MF2, 0x3, false }, // 2964 |
| 2973 | { PseudoVWADD_VX_MF4_MASK, PseudoVWADD_VX_MF4, 0x3, false }, // 2965 |
| 2974 | { PseudoVWADD_VX_MF8_MASK, PseudoVWADD_VX_MF8, 0x3, false }, // 2966 |
| 2975 | { PseudoVWADD_WV_M1_MASK, PseudoVWADD_WV_M1, 0x3, false }, // 2967 |
| 2976 | { PseudoVWADD_WV_M1_MASK_TIED, PseudoVWADD_WV_M1_TIED, 0x2, false }, // 2968 |
| 2977 | { PseudoVWADD_WV_M2_MASK, PseudoVWADD_WV_M2, 0x3, false }, // 2969 |
| 2978 | { PseudoVWADD_WV_M2_MASK_TIED, PseudoVWADD_WV_M2_TIED, 0x2, false }, // 2970 |
| 2979 | { PseudoVWADD_WV_M4_MASK, PseudoVWADD_WV_M4, 0x3, false }, // 2971 |
| 2980 | { PseudoVWADD_WV_M4_MASK_TIED, PseudoVWADD_WV_M4_TIED, 0x2, false }, // 2972 |
| 2981 | { PseudoVWADD_WV_MF2_MASK, PseudoVWADD_WV_MF2, 0x3, false }, // 2973 |
| 2982 | { PseudoVWADD_WV_MF2_MASK_TIED, PseudoVWADD_WV_MF2_TIED, 0x2, false }, // 2974 |
| 2983 | { PseudoVWADD_WV_MF4_MASK, PseudoVWADD_WV_MF4, 0x3, false }, // 2975 |
| 2984 | { PseudoVWADD_WV_MF4_MASK_TIED, PseudoVWADD_WV_MF4_TIED, 0x2, false }, // 2976 |
| 2985 | { PseudoVWADD_WV_MF8_MASK, PseudoVWADD_WV_MF8, 0x3, false }, // 2977 |
| 2986 | { PseudoVWADD_WV_MF8_MASK_TIED, PseudoVWADD_WV_MF8_TIED, 0x2, false }, // 2978 |
| 2987 | { PseudoVWADD_WX_M1_MASK, PseudoVWADD_WX_M1, 0x3, false }, // 2979 |
| 2988 | { PseudoVWADD_WX_M2_MASK, PseudoVWADD_WX_M2, 0x3, false }, // 2980 |
| 2989 | { PseudoVWADD_WX_M4_MASK, PseudoVWADD_WX_M4, 0x3, false }, // 2981 |
| 2990 | { PseudoVWADD_WX_MF2_MASK, PseudoVWADD_WX_MF2, 0x3, false }, // 2982 |
| 2991 | { PseudoVWADD_WX_MF4_MASK, PseudoVWADD_WX_MF4, 0x3, false }, // 2983 |
| 2992 | { PseudoVWADD_WX_MF8_MASK, PseudoVWADD_WX_MF8, 0x3, false }, // 2984 |
| 2993 | { PseudoVWMACCSU_VV_M1_MASK, PseudoVWMACCSU_VV_M1, 0x3, false }, // 2985 |
| 2994 | { PseudoVWMACCSU_VV_M2_MASK, PseudoVWMACCSU_VV_M2, 0x3, false }, // 2986 |
| 2995 | { PseudoVWMACCSU_VV_M4_MASK, PseudoVWMACCSU_VV_M4, 0x3, false }, // 2987 |
| 2996 | { PseudoVWMACCSU_VV_MF2_MASK, PseudoVWMACCSU_VV_MF2, 0x3, false }, // 2988 |
| 2997 | { PseudoVWMACCSU_VV_MF4_MASK, PseudoVWMACCSU_VV_MF4, 0x3, false }, // 2989 |
| 2998 | { PseudoVWMACCSU_VV_MF8_MASK, PseudoVWMACCSU_VV_MF8, 0x3, false }, // 2990 |
| 2999 | { PseudoVWMACCSU_VX_M1_MASK, PseudoVWMACCSU_VX_M1, 0x3, false }, // 2991 |
| 3000 | { PseudoVWMACCSU_VX_M2_MASK, PseudoVWMACCSU_VX_M2, 0x3, false }, // 2992 |
| 3001 | { PseudoVWMACCSU_VX_M4_MASK, PseudoVWMACCSU_VX_M4, 0x3, false }, // 2993 |
| 3002 | { PseudoVWMACCSU_VX_MF2_MASK, PseudoVWMACCSU_VX_MF2, 0x3, false }, // 2994 |
| 3003 | { PseudoVWMACCSU_VX_MF4_MASK, PseudoVWMACCSU_VX_MF4, 0x3, false }, // 2995 |
| 3004 | { PseudoVWMACCSU_VX_MF8_MASK, PseudoVWMACCSU_VX_MF8, 0x3, false }, // 2996 |
| 3005 | { PseudoVWMACCUS_VX_M1_MASK, PseudoVWMACCUS_VX_M1, 0x3, false }, // 2997 |
| 3006 | { PseudoVWMACCUS_VX_M2_MASK, PseudoVWMACCUS_VX_M2, 0x3, false }, // 2998 |
| 3007 | { PseudoVWMACCUS_VX_M4_MASK, PseudoVWMACCUS_VX_M4, 0x3, false }, // 2999 |
| 3008 | { PseudoVWMACCUS_VX_MF2_MASK, PseudoVWMACCUS_VX_MF2, 0x3, false }, // 3000 |
| 3009 | { PseudoVWMACCUS_VX_MF4_MASK, PseudoVWMACCUS_VX_MF4, 0x3, false }, // 3001 |
| 3010 | { PseudoVWMACCUS_VX_MF8_MASK, PseudoVWMACCUS_VX_MF8, 0x3, false }, // 3002 |
| 3011 | { PseudoVWMACCU_VV_M1_MASK, PseudoVWMACCU_VV_M1, 0x3, false }, // 3003 |
| 3012 | { PseudoVWMACCU_VV_M2_MASK, PseudoVWMACCU_VV_M2, 0x3, false }, // 3004 |
| 3013 | { PseudoVWMACCU_VV_M4_MASK, PseudoVWMACCU_VV_M4, 0x3, false }, // 3005 |
| 3014 | { PseudoVWMACCU_VV_MF2_MASK, PseudoVWMACCU_VV_MF2, 0x3, false }, // 3006 |
| 3015 | { PseudoVWMACCU_VV_MF4_MASK, PseudoVWMACCU_VV_MF4, 0x3, false }, // 3007 |
| 3016 | { PseudoVWMACCU_VV_MF8_MASK, PseudoVWMACCU_VV_MF8, 0x3, false }, // 3008 |
| 3017 | { PseudoVWMACCU_VX_M1_MASK, PseudoVWMACCU_VX_M1, 0x3, false }, // 3009 |
| 3018 | { PseudoVWMACCU_VX_M2_MASK, PseudoVWMACCU_VX_M2, 0x3, false }, // 3010 |
| 3019 | { PseudoVWMACCU_VX_M4_MASK, PseudoVWMACCU_VX_M4, 0x3, false }, // 3011 |
| 3020 | { PseudoVWMACCU_VX_MF2_MASK, PseudoVWMACCU_VX_MF2, 0x3, false }, // 3012 |
| 3021 | { PseudoVWMACCU_VX_MF4_MASK, PseudoVWMACCU_VX_MF4, 0x3, false }, // 3013 |
| 3022 | { PseudoVWMACCU_VX_MF8_MASK, PseudoVWMACCU_VX_MF8, 0x3, false }, // 3014 |
| 3023 | { PseudoVWMACC_VV_M1_MASK, PseudoVWMACC_VV_M1, 0x3, false }, // 3015 |
| 3024 | { PseudoVWMACC_VV_M2_MASK, PseudoVWMACC_VV_M2, 0x3, false }, // 3016 |
| 3025 | { PseudoVWMACC_VV_M4_MASK, PseudoVWMACC_VV_M4, 0x3, false }, // 3017 |
| 3026 | { PseudoVWMACC_VV_MF2_MASK, PseudoVWMACC_VV_MF2, 0x3, false }, // 3018 |
| 3027 | { PseudoVWMACC_VV_MF4_MASK, PseudoVWMACC_VV_MF4, 0x3, false }, // 3019 |
| 3028 | { PseudoVWMACC_VV_MF8_MASK, PseudoVWMACC_VV_MF8, 0x3, false }, // 3020 |
| 3029 | { PseudoVWMACC_VX_M1_MASK, PseudoVWMACC_VX_M1, 0x3, false }, // 3021 |
| 3030 | { PseudoVWMACC_VX_M2_MASK, PseudoVWMACC_VX_M2, 0x3, false }, // 3022 |
| 3031 | { PseudoVWMACC_VX_M4_MASK, PseudoVWMACC_VX_M4, 0x3, false }, // 3023 |
| 3032 | { PseudoVWMACC_VX_MF2_MASK, PseudoVWMACC_VX_MF2, 0x3, false }, // 3024 |
| 3033 | { PseudoVWMACC_VX_MF4_MASK, PseudoVWMACC_VX_MF4, 0x3, false }, // 3025 |
| 3034 | { PseudoVWMACC_VX_MF8_MASK, PseudoVWMACC_VX_MF8, 0x3, false }, // 3026 |
| 3035 | { PseudoVWMULSU_VV_M1_MASK, PseudoVWMULSU_VV_M1, 0x3, false }, // 3027 |
| 3036 | { PseudoVWMULSU_VV_M2_MASK, PseudoVWMULSU_VV_M2, 0x3, false }, // 3028 |
| 3037 | { PseudoVWMULSU_VV_M4_MASK, PseudoVWMULSU_VV_M4, 0x3, false }, // 3029 |
| 3038 | { PseudoVWMULSU_VV_MF2_MASK, PseudoVWMULSU_VV_MF2, 0x3, false }, // 3030 |
| 3039 | { PseudoVWMULSU_VV_MF4_MASK, PseudoVWMULSU_VV_MF4, 0x3, false }, // 3031 |
| 3040 | { PseudoVWMULSU_VV_MF8_MASK, PseudoVWMULSU_VV_MF8, 0x3, false }, // 3032 |
| 3041 | { PseudoVWMULSU_VX_M1_MASK, PseudoVWMULSU_VX_M1, 0x3, false }, // 3033 |
| 3042 | { PseudoVWMULSU_VX_M2_MASK, PseudoVWMULSU_VX_M2, 0x3, false }, // 3034 |
| 3043 | { PseudoVWMULSU_VX_M4_MASK, PseudoVWMULSU_VX_M4, 0x3, false }, // 3035 |
| 3044 | { PseudoVWMULSU_VX_MF2_MASK, PseudoVWMULSU_VX_MF2, 0x3, false }, // 3036 |
| 3045 | { PseudoVWMULSU_VX_MF4_MASK, PseudoVWMULSU_VX_MF4, 0x3, false }, // 3037 |
| 3046 | { PseudoVWMULSU_VX_MF8_MASK, PseudoVWMULSU_VX_MF8, 0x3, false }, // 3038 |
| 3047 | { PseudoVWMULU_VV_M1_MASK, PseudoVWMULU_VV_M1, 0x3, false }, // 3039 |
| 3048 | { PseudoVWMULU_VV_M2_MASK, PseudoVWMULU_VV_M2, 0x3, false }, // 3040 |
| 3049 | { PseudoVWMULU_VV_M4_MASK, PseudoVWMULU_VV_M4, 0x3, false }, // 3041 |
| 3050 | { PseudoVWMULU_VV_MF2_MASK, PseudoVWMULU_VV_MF2, 0x3, false }, // 3042 |
| 3051 | { PseudoVWMULU_VV_MF4_MASK, PseudoVWMULU_VV_MF4, 0x3, false }, // 3043 |
| 3052 | { PseudoVWMULU_VV_MF8_MASK, PseudoVWMULU_VV_MF8, 0x3, false }, // 3044 |
| 3053 | { PseudoVWMULU_VX_M1_MASK, PseudoVWMULU_VX_M1, 0x3, false }, // 3045 |
| 3054 | { PseudoVWMULU_VX_M2_MASK, PseudoVWMULU_VX_M2, 0x3, false }, // 3046 |
| 3055 | { PseudoVWMULU_VX_M4_MASK, PseudoVWMULU_VX_M4, 0x3, false }, // 3047 |
| 3056 | { PseudoVWMULU_VX_MF2_MASK, PseudoVWMULU_VX_MF2, 0x3, false }, // 3048 |
| 3057 | { PseudoVWMULU_VX_MF4_MASK, PseudoVWMULU_VX_MF4, 0x3, false }, // 3049 |
| 3058 | { PseudoVWMULU_VX_MF8_MASK, PseudoVWMULU_VX_MF8, 0x3, false }, // 3050 |
| 3059 | { PseudoVWMUL_VV_M1_MASK, PseudoVWMUL_VV_M1, 0x3, false }, // 3051 |
| 3060 | { PseudoVWMUL_VV_M2_MASK, PseudoVWMUL_VV_M2, 0x3, false }, // 3052 |
| 3061 | { PseudoVWMUL_VV_M4_MASK, PseudoVWMUL_VV_M4, 0x3, false }, // 3053 |
| 3062 | { PseudoVWMUL_VV_MF2_MASK, PseudoVWMUL_VV_MF2, 0x3, false }, // 3054 |
| 3063 | { PseudoVWMUL_VV_MF4_MASK, PseudoVWMUL_VV_MF4, 0x3, false }, // 3055 |
| 3064 | { PseudoVWMUL_VV_MF8_MASK, PseudoVWMUL_VV_MF8, 0x3, false }, // 3056 |
| 3065 | { PseudoVWMUL_VX_M1_MASK, PseudoVWMUL_VX_M1, 0x3, false }, // 3057 |
| 3066 | { PseudoVWMUL_VX_M2_MASK, PseudoVWMUL_VX_M2, 0x3, false }, // 3058 |
| 3067 | { PseudoVWMUL_VX_M4_MASK, PseudoVWMUL_VX_M4, 0x3, false }, // 3059 |
| 3068 | { PseudoVWMUL_VX_MF2_MASK, PseudoVWMUL_VX_MF2, 0x3, false }, // 3060 |
| 3069 | { PseudoVWMUL_VX_MF4_MASK, PseudoVWMUL_VX_MF4, 0x3, false }, // 3061 |
| 3070 | { PseudoVWMUL_VX_MF8_MASK, PseudoVWMUL_VX_MF8, 0x3, false }, // 3062 |
| 3071 | { PseudoVWREDSUMU_VS_M1_E16_MASK, PseudoVWREDSUMU_VS_M1_E16, 0x3, true }, // 3063 |
| 3072 | { PseudoVWREDSUMU_VS_M1_E32_MASK, PseudoVWREDSUMU_VS_M1_E32, 0x3, true }, // 3064 |
| 3073 | { PseudoVWREDSUMU_VS_M1_E8_MASK, PseudoVWREDSUMU_VS_M1_E8, 0x3, true }, // 3065 |
| 3074 | { PseudoVWREDSUMU_VS_M2_E16_MASK, PseudoVWREDSUMU_VS_M2_E16, 0x3, true }, // 3066 |
| 3075 | { PseudoVWREDSUMU_VS_M2_E32_MASK, PseudoVWREDSUMU_VS_M2_E32, 0x3, true }, // 3067 |
| 3076 | { PseudoVWREDSUMU_VS_M2_E8_MASK, PseudoVWREDSUMU_VS_M2_E8, 0x3, true }, // 3068 |
| 3077 | { PseudoVWREDSUMU_VS_M4_E16_MASK, PseudoVWREDSUMU_VS_M4_E16, 0x3, true }, // 3069 |
| 3078 | { PseudoVWREDSUMU_VS_M4_E32_MASK, PseudoVWREDSUMU_VS_M4_E32, 0x3, true }, // 3070 |
| 3079 | { PseudoVWREDSUMU_VS_M4_E8_MASK, PseudoVWREDSUMU_VS_M4_E8, 0x3, true }, // 3071 |
| 3080 | { PseudoVWREDSUMU_VS_M8_E16_MASK, PseudoVWREDSUMU_VS_M8_E16, 0x3, true }, // 3072 |
| 3081 | { PseudoVWREDSUMU_VS_M8_E32_MASK, PseudoVWREDSUMU_VS_M8_E32, 0x3, true }, // 3073 |
| 3082 | { PseudoVWREDSUMU_VS_M8_E8_MASK, PseudoVWREDSUMU_VS_M8_E8, 0x3, true }, // 3074 |
| 3083 | { PseudoVWREDSUMU_VS_MF2_E16_MASK, PseudoVWREDSUMU_VS_MF2_E16, 0x3, true }, // 3075 |
| 3084 | { PseudoVWREDSUMU_VS_MF2_E32_MASK, PseudoVWREDSUMU_VS_MF2_E32, 0x3, true }, // 3076 |
| 3085 | { PseudoVWREDSUMU_VS_MF2_E8_MASK, PseudoVWREDSUMU_VS_MF2_E8, 0x3, true }, // 3077 |
| 3086 | { PseudoVWREDSUMU_VS_MF4_E16_MASK, PseudoVWREDSUMU_VS_MF4_E16, 0x3, true }, // 3078 |
| 3087 | { PseudoVWREDSUMU_VS_MF4_E8_MASK, PseudoVWREDSUMU_VS_MF4_E8, 0x3, true }, // 3079 |
| 3088 | { PseudoVWREDSUMU_VS_MF8_E8_MASK, PseudoVWREDSUMU_VS_MF8_E8, 0x3, true }, // 3080 |
| 3089 | { PseudoVWREDSUM_VS_M1_E16_MASK, PseudoVWREDSUM_VS_M1_E16, 0x3, true }, // 3081 |
| 3090 | { PseudoVWREDSUM_VS_M1_E32_MASK, PseudoVWREDSUM_VS_M1_E32, 0x3, true }, // 3082 |
| 3091 | { PseudoVWREDSUM_VS_M1_E8_MASK, PseudoVWREDSUM_VS_M1_E8, 0x3, true }, // 3083 |
| 3092 | { PseudoVWREDSUM_VS_M2_E16_MASK, PseudoVWREDSUM_VS_M2_E16, 0x3, true }, // 3084 |
| 3093 | { PseudoVWREDSUM_VS_M2_E32_MASK, PseudoVWREDSUM_VS_M2_E32, 0x3, true }, // 3085 |
| 3094 | { PseudoVWREDSUM_VS_M2_E8_MASK, PseudoVWREDSUM_VS_M2_E8, 0x3, true }, // 3086 |
| 3095 | { PseudoVWREDSUM_VS_M4_E16_MASK, PseudoVWREDSUM_VS_M4_E16, 0x3, true }, // 3087 |
| 3096 | { PseudoVWREDSUM_VS_M4_E32_MASK, PseudoVWREDSUM_VS_M4_E32, 0x3, true }, // 3088 |
| 3097 | { PseudoVWREDSUM_VS_M4_E8_MASK, PseudoVWREDSUM_VS_M4_E8, 0x3, true }, // 3089 |
| 3098 | { PseudoVWREDSUM_VS_M8_E16_MASK, PseudoVWREDSUM_VS_M8_E16, 0x3, true }, // 3090 |
| 3099 | { PseudoVWREDSUM_VS_M8_E32_MASK, PseudoVWREDSUM_VS_M8_E32, 0x3, true }, // 3091 |
| 3100 | { PseudoVWREDSUM_VS_M8_E8_MASK, PseudoVWREDSUM_VS_M8_E8, 0x3, true }, // 3092 |
| 3101 | { PseudoVWREDSUM_VS_MF2_E16_MASK, PseudoVWREDSUM_VS_MF2_E16, 0x3, true }, // 3093 |
| 3102 | { PseudoVWREDSUM_VS_MF2_E32_MASK, PseudoVWREDSUM_VS_MF2_E32, 0x3, true }, // 3094 |
| 3103 | { PseudoVWREDSUM_VS_MF2_E8_MASK, PseudoVWREDSUM_VS_MF2_E8, 0x3, true }, // 3095 |
| 3104 | { PseudoVWREDSUM_VS_MF4_E16_MASK, PseudoVWREDSUM_VS_MF4_E16, 0x3, true }, // 3096 |
| 3105 | { PseudoVWREDSUM_VS_MF4_E8_MASK, PseudoVWREDSUM_VS_MF4_E8, 0x3, true }, // 3097 |
| 3106 | { PseudoVWREDSUM_VS_MF8_E8_MASK, PseudoVWREDSUM_VS_MF8_E8, 0x3, true }, // 3098 |
| 3107 | { PseudoVWSLL_VI_M1_MASK, PseudoVWSLL_VI_M1, 0x3, false }, // 3099 |
| 3108 | { PseudoVWSLL_VI_M2_MASK, PseudoVWSLL_VI_M2, 0x3, false }, // 3100 |
| 3109 | { PseudoVWSLL_VI_M4_MASK, PseudoVWSLL_VI_M4, 0x3, false }, // 3101 |
| 3110 | { PseudoVWSLL_VI_MF2_MASK, PseudoVWSLL_VI_MF2, 0x3, false }, // 3102 |
| 3111 | { PseudoVWSLL_VI_MF4_MASK, PseudoVWSLL_VI_MF4, 0x3, false }, // 3103 |
| 3112 | { PseudoVWSLL_VI_MF8_MASK, PseudoVWSLL_VI_MF8, 0x3, false }, // 3104 |
| 3113 | { PseudoVWSLL_VV_M1_MASK, PseudoVWSLL_VV_M1, 0x3, false }, // 3105 |
| 3114 | { PseudoVWSLL_VV_M2_MASK, PseudoVWSLL_VV_M2, 0x3, false }, // 3106 |
| 3115 | { PseudoVWSLL_VV_M4_MASK, PseudoVWSLL_VV_M4, 0x3, false }, // 3107 |
| 3116 | { PseudoVWSLL_VV_MF2_MASK, PseudoVWSLL_VV_MF2, 0x3, false }, // 3108 |
| 3117 | { PseudoVWSLL_VV_MF4_MASK, PseudoVWSLL_VV_MF4, 0x3, false }, // 3109 |
| 3118 | { PseudoVWSLL_VV_MF8_MASK, PseudoVWSLL_VV_MF8, 0x3, false }, // 3110 |
| 3119 | { PseudoVWSLL_VX_M1_MASK, PseudoVWSLL_VX_M1, 0x3, false }, // 3111 |
| 3120 | { PseudoVWSLL_VX_M2_MASK, PseudoVWSLL_VX_M2, 0x3, false }, // 3112 |
| 3121 | { PseudoVWSLL_VX_M4_MASK, PseudoVWSLL_VX_M4, 0x3, false }, // 3113 |
| 3122 | { PseudoVWSLL_VX_MF2_MASK, PseudoVWSLL_VX_MF2, 0x3, false }, // 3114 |
| 3123 | { PseudoVWSLL_VX_MF4_MASK, PseudoVWSLL_VX_MF4, 0x3, false }, // 3115 |
| 3124 | { PseudoVWSLL_VX_MF8_MASK, PseudoVWSLL_VX_MF8, 0x3, false }, // 3116 |
| 3125 | { PseudoVWSUBU_VV_M1_MASK, PseudoVWSUBU_VV_M1, 0x3, false }, // 3117 |
| 3126 | { PseudoVWSUBU_VV_M2_MASK, PseudoVWSUBU_VV_M2, 0x3, false }, // 3118 |
| 3127 | { PseudoVWSUBU_VV_M4_MASK, PseudoVWSUBU_VV_M4, 0x3, false }, // 3119 |
| 3128 | { PseudoVWSUBU_VV_MF2_MASK, PseudoVWSUBU_VV_MF2, 0x3, false }, // 3120 |
| 3129 | { PseudoVWSUBU_VV_MF4_MASK, PseudoVWSUBU_VV_MF4, 0x3, false }, // 3121 |
| 3130 | { PseudoVWSUBU_VV_MF8_MASK, PseudoVWSUBU_VV_MF8, 0x3, false }, // 3122 |
| 3131 | { PseudoVWSUBU_VX_M1_MASK, PseudoVWSUBU_VX_M1, 0x3, false }, // 3123 |
| 3132 | { PseudoVWSUBU_VX_M2_MASK, PseudoVWSUBU_VX_M2, 0x3, false }, // 3124 |
| 3133 | { PseudoVWSUBU_VX_M4_MASK, PseudoVWSUBU_VX_M4, 0x3, false }, // 3125 |
| 3134 | { PseudoVWSUBU_VX_MF2_MASK, PseudoVWSUBU_VX_MF2, 0x3, false }, // 3126 |
| 3135 | { PseudoVWSUBU_VX_MF4_MASK, PseudoVWSUBU_VX_MF4, 0x3, false }, // 3127 |
| 3136 | { PseudoVWSUBU_VX_MF8_MASK, PseudoVWSUBU_VX_MF8, 0x3, false }, // 3128 |
| 3137 | { PseudoVWSUBU_WV_M1_MASK, PseudoVWSUBU_WV_M1, 0x3, false }, // 3129 |
| 3138 | { PseudoVWSUBU_WV_M1_MASK_TIED, PseudoVWSUBU_WV_M1_TIED, 0x2, false }, // 3130 |
| 3139 | { PseudoVWSUBU_WV_M2_MASK, PseudoVWSUBU_WV_M2, 0x3, false }, // 3131 |
| 3140 | { PseudoVWSUBU_WV_M2_MASK_TIED, PseudoVWSUBU_WV_M2_TIED, 0x2, false }, // 3132 |
| 3141 | { PseudoVWSUBU_WV_M4_MASK, PseudoVWSUBU_WV_M4, 0x3, false }, // 3133 |
| 3142 | { PseudoVWSUBU_WV_M4_MASK_TIED, PseudoVWSUBU_WV_M4_TIED, 0x2, false }, // 3134 |
| 3143 | { PseudoVWSUBU_WV_MF2_MASK, PseudoVWSUBU_WV_MF2, 0x3, false }, // 3135 |
| 3144 | { PseudoVWSUBU_WV_MF2_MASK_TIED, PseudoVWSUBU_WV_MF2_TIED, 0x2, false }, // 3136 |
| 3145 | { PseudoVWSUBU_WV_MF4_MASK, PseudoVWSUBU_WV_MF4, 0x3, false }, // 3137 |
| 3146 | { PseudoVWSUBU_WV_MF4_MASK_TIED, PseudoVWSUBU_WV_MF4_TIED, 0x2, false }, // 3138 |
| 3147 | { PseudoVWSUBU_WV_MF8_MASK, PseudoVWSUBU_WV_MF8, 0x3, false }, // 3139 |
| 3148 | { PseudoVWSUBU_WV_MF8_MASK_TIED, PseudoVWSUBU_WV_MF8_TIED, 0x2, false }, // 3140 |
| 3149 | { PseudoVWSUBU_WX_M1_MASK, PseudoVWSUBU_WX_M1, 0x3, false }, // 3141 |
| 3150 | { PseudoVWSUBU_WX_M2_MASK, PseudoVWSUBU_WX_M2, 0x3, false }, // 3142 |
| 3151 | { PseudoVWSUBU_WX_M4_MASK, PseudoVWSUBU_WX_M4, 0x3, false }, // 3143 |
| 3152 | { PseudoVWSUBU_WX_MF2_MASK, PseudoVWSUBU_WX_MF2, 0x3, false }, // 3144 |
| 3153 | { PseudoVWSUBU_WX_MF4_MASK, PseudoVWSUBU_WX_MF4, 0x3, false }, // 3145 |
| 3154 | { PseudoVWSUBU_WX_MF8_MASK, PseudoVWSUBU_WX_MF8, 0x3, false }, // 3146 |
| 3155 | { PseudoVWSUB_VV_M1_MASK, PseudoVWSUB_VV_M1, 0x3, false }, // 3147 |
| 3156 | { PseudoVWSUB_VV_M2_MASK, PseudoVWSUB_VV_M2, 0x3, false }, // 3148 |
| 3157 | { PseudoVWSUB_VV_M4_MASK, PseudoVWSUB_VV_M4, 0x3, false }, // 3149 |
| 3158 | { PseudoVWSUB_VV_MF2_MASK, PseudoVWSUB_VV_MF2, 0x3, false }, // 3150 |
| 3159 | { PseudoVWSUB_VV_MF4_MASK, PseudoVWSUB_VV_MF4, 0x3, false }, // 3151 |
| 3160 | { PseudoVWSUB_VV_MF8_MASK, PseudoVWSUB_VV_MF8, 0x3, false }, // 3152 |
| 3161 | { PseudoVWSUB_VX_M1_MASK, PseudoVWSUB_VX_M1, 0x3, false }, // 3153 |
| 3162 | { PseudoVWSUB_VX_M2_MASK, PseudoVWSUB_VX_M2, 0x3, false }, // 3154 |
| 3163 | { PseudoVWSUB_VX_M4_MASK, PseudoVWSUB_VX_M4, 0x3, false }, // 3155 |
| 3164 | { PseudoVWSUB_VX_MF2_MASK, PseudoVWSUB_VX_MF2, 0x3, false }, // 3156 |
| 3165 | { PseudoVWSUB_VX_MF4_MASK, PseudoVWSUB_VX_MF4, 0x3, false }, // 3157 |
| 3166 | { PseudoVWSUB_VX_MF8_MASK, PseudoVWSUB_VX_MF8, 0x3, false }, // 3158 |
| 3167 | { PseudoVWSUB_WV_M1_MASK, PseudoVWSUB_WV_M1, 0x3, false }, // 3159 |
| 3168 | { PseudoVWSUB_WV_M1_MASK_TIED, PseudoVWSUB_WV_M1_TIED, 0x2, false }, // 3160 |
| 3169 | { PseudoVWSUB_WV_M2_MASK, PseudoVWSUB_WV_M2, 0x3, false }, // 3161 |
| 3170 | { PseudoVWSUB_WV_M2_MASK_TIED, PseudoVWSUB_WV_M2_TIED, 0x2, false }, // 3162 |
| 3171 | { PseudoVWSUB_WV_M4_MASK, PseudoVWSUB_WV_M4, 0x3, false }, // 3163 |
| 3172 | { PseudoVWSUB_WV_M4_MASK_TIED, PseudoVWSUB_WV_M4_TIED, 0x2, false }, // 3164 |
| 3173 | { PseudoVWSUB_WV_MF2_MASK, PseudoVWSUB_WV_MF2, 0x3, false }, // 3165 |
| 3174 | { PseudoVWSUB_WV_MF2_MASK_TIED, PseudoVWSUB_WV_MF2_TIED, 0x2, false }, // 3166 |
| 3175 | { PseudoVWSUB_WV_MF4_MASK, PseudoVWSUB_WV_MF4, 0x3, false }, // 3167 |
| 3176 | { PseudoVWSUB_WV_MF4_MASK_TIED, PseudoVWSUB_WV_MF4_TIED, 0x2, false }, // 3168 |
| 3177 | { PseudoVWSUB_WV_MF8_MASK, PseudoVWSUB_WV_MF8, 0x3, false }, // 3169 |
| 3178 | { PseudoVWSUB_WV_MF8_MASK_TIED, PseudoVWSUB_WV_MF8_TIED, 0x2, false }, // 3170 |
| 3179 | { PseudoVWSUB_WX_M1_MASK, PseudoVWSUB_WX_M1, 0x3, false }, // 3171 |
| 3180 | { PseudoVWSUB_WX_M2_MASK, PseudoVWSUB_WX_M2, 0x3, false }, // 3172 |
| 3181 | { PseudoVWSUB_WX_M4_MASK, PseudoVWSUB_WX_M4, 0x3, false }, // 3173 |
| 3182 | { PseudoVWSUB_WX_MF2_MASK, PseudoVWSUB_WX_MF2, 0x3, false }, // 3174 |
| 3183 | { PseudoVWSUB_WX_MF4_MASK, PseudoVWSUB_WX_MF4, 0x3, false }, // 3175 |
| 3184 | { PseudoVWSUB_WX_MF8_MASK, PseudoVWSUB_WX_MF8, 0x3, false }, // 3176 |
| 3185 | { PseudoVXOR_VI_M1_MASK, PseudoVXOR_VI_M1, 0x3, false }, // 3177 |
| 3186 | { PseudoVXOR_VI_M2_MASK, PseudoVXOR_VI_M2, 0x3, false }, // 3178 |
| 3187 | { PseudoVXOR_VI_M4_MASK, PseudoVXOR_VI_M4, 0x3, false }, // 3179 |
| 3188 | { PseudoVXOR_VI_M8_MASK, PseudoVXOR_VI_M8, 0x3, false }, // 3180 |
| 3189 | { PseudoVXOR_VI_MF2_MASK, PseudoVXOR_VI_MF2, 0x3, false }, // 3181 |
| 3190 | { PseudoVXOR_VI_MF4_MASK, PseudoVXOR_VI_MF4, 0x3, false }, // 3182 |
| 3191 | { PseudoVXOR_VI_MF8_MASK, PseudoVXOR_VI_MF8, 0x3, false }, // 3183 |
| 3192 | { PseudoVXOR_VV_M1_MASK, PseudoVXOR_VV_M1, 0x3, false }, // 3184 |
| 3193 | { PseudoVXOR_VV_M2_MASK, PseudoVXOR_VV_M2, 0x3, false }, // 3185 |
| 3194 | { PseudoVXOR_VV_M4_MASK, PseudoVXOR_VV_M4, 0x3, false }, // 3186 |
| 3195 | { PseudoVXOR_VV_M8_MASK, PseudoVXOR_VV_M8, 0x3, false }, // 3187 |
| 3196 | { PseudoVXOR_VV_MF2_MASK, PseudoVXOR_VV_MF2, 0x3, false }, // 3188 |
| 3197 | { PseudoVXOR_VV_MF4_MASK, PseudoVXOR_VV_MF4, 0x3, false }, // 3189 |
| 3198 | { PseudoVXOR_VV_MF8_MASK, PseudoVXOR_VV_MF8, 0x3, false }, // 3190 |
| 3199 | { PseudoVXOR_VX_M1_MASK, PseudoVXOR_VX_M1, 0x3, false }, // 3191 |
| 3200 | { PseudoVXOR_VX_M2_MASK, PseudoVXOR_VX_M2, 0x3, false }, // 3192 |
| 3201 | { PseudoVXOR_VX_M4_MASK, PseudoVXOR_VX_M4, 0x3, false }, // 3193 |
| 3202 | { PseudoVXOR_VX_M8_MASK, PseudoVXOR_VX_M8, 0x3, false }, // 3194 |
| 3203 | { PseudoVXOR_VX_MF2_MASK, PseudoVXOR_VX_MF2, 0x3, false }, // 3195 |
| 3204 | { PseudoVXOR_VX_MF4_MASK, PseudoVXOR_VX_MF4, 0x3, false }, // 3196 |
| 3205 | { PseudoVXOR_VX_MF8_MASK, PseudoVXOR_VX_MF8, 0x3, false }, // 3197 |
| 3206 | { PseudoVZEXT_VF2_M1_MASK, PseudoVZEXT_VF2_M1, 0x2, false }, // 3198 |
| 3207 | { PseudoVZEXT_VF2_M2_MASK, PseudoVZEXT_VF2_M2, 0x2, false }, // 3199 |
| 3208 | { PseudoVZEXT_VF2_M4_MASK, PseudoVZEXT_VF2_M4, 0x2, false }, // 3200 |
| 3209 | { PseudoVZEXT_VF2_M8_MASK, PseudoVZEXT_VF2_M8, 0x2, false }, // 3201 |
| 3210 | { PseudoVZEXT_VF2_MF2_MASK, PseudoVZEXT_VF2_MF2, 0x2, false }, // 3202 |
| 3211 | { PseudoVZEXT_VF2_MF4_MASK, PseudoVZEXT_VF2_MF4, 0x2, false }, // 3203 |
| 3212 | { PseudoVZEXT_VF4_M1_MASK, PseudoVZEXT_VF4_M1, 0x2, false }, // 3204 |
| 3213 | { PseudoVZEXT_VF4_M2_MASK, PseudoVZEXT_VF4_M2, 0x2, false }, // 3205 |
| 3214 | { PseudoVZEXT_VF4_M4_MASK, PseudoVZEXT_VF4_M4, 0x2, false }, // 3206 |
| 3215 | { PseudoVZEXT_VF4_M8_MASK, PseudoVZEXT_VF4_M8, 0x2, false }, // 3207 |
| 3216 | { PseudoVZEXT_VF4_MF2_MASK, PseudoVZEXT_VF4_MF2, 0x2, false }, // 3208 |
| 3217 | { PseudoVZEXT_VF8_M1_MASK, PseudoVZEXT_VF8_M1, 0x2, false }, // 3209 |
| 3218 | { PseudoVZEXT_VF8_M2_MASK, PseudoVZEXT_VF8_M2, 0x2, false }, // 3210 |
| 3219 | { PseudoVZEXT_VF8_M4_MASK, PseudoVZEXT_VF8_M4, 0x2, false }, // 3211 |
| 3220 | { PseudoVZEXT_VF8_M8_MASK, PseudoVZEXT_VF8_M8, 0x2, false }, // 3212 |
| 3221 | }; |
| 3222 | |
| 3223 | const RISCVMaskedPseudoInfo *getMaskedPseudoInfo(unsigned MaskedPseudo) { |
| 3224 | struct KeyType { |
| 3225 | unsigned MaskedPseudo; |
| 3226 | }; |
| 3227 | KeyType Key = {MaskedPseudo}; |
| 3228 | struct Comp { |
| 3229 | bool operator()(const RISCVMaskedPseudoInfo &LHS, const KeyType &RHS) const { |
| 3230 | if (LHS.MaskedPseudo < RHS.MaskedPseudo) |
| 3231 | return true; |
| 3232 | if (LHS.MaskedPseudo > RHS.MaskedPseudo) |
| 3233 | return false; |
| 3234 | return false; |
| 3235 | } |
| 3236 | }; |
| 3237 | auto Table = ArrayRef(RISCVMaskedPseudosTable); |
| 3238 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 3239 | if (Idx == Table.end() || |
| 3240 | Key.MaskedPseudo != Idx->MaskedPseudo) |
| 3241 | return nullptr; |
| 3242 | |
| 3243 | return &*Idx; |
| 3244 | } |
| 3245 | |
| 3246 | const RISCVMaskedPseudoInfo *lookupMaskedIntrinsicByUnmasked(unsigned UnmaskedPseudo) { |
| 3247 | struct IndexType { |
| 3248 | unsigned UnmaskedPseudo; |
| 3249 | unsigned _index; |
| 3250 | }; |
| 3251 | static const struct IndexType Index[] = { |
| 3252 | { PseudoTHVdotVMAQASU_VV_M1, 0 }, |
| 3253 | { PseudoTHVdotVMAQASU_VV_M2, 1 }, |
| 3254 | { PseudoTHVdotVMAQASU_VV_M4, 2 }, |
| 3255 | { PseudoTHVdotVMAQASU_VV_M8, 3 }, |
| 3256 | { PseudoTHVdotVMAQASU_VV_MF2, 4 }, |
| 3257 | { PseudoTHVdotVMAQASU_VX_M1, 5 }, |
| 3258 | { PseudoTHVdotVMAQASU_VX_M2, 6 }, |
| 3259 | { PseudoTHVdotVMAQASU_VX_M4, 7 }, |
| 3260 | { PseudoTHVdotVMAQASU_VX_M8, 8 }, |
| 3261 | { PseudoTHVdotVMAQASU_VX_MF2, 9 }, |
| 3262 | { PseudoTHVdotVMAQAUS_VX_M1, 10 }, |
| 3263 | { PseudoTHVdotVMAQAUS_VX_M2, 11 }, |
| 3264 | { PseudoTHVdotVMAQAUS_VX_M4, 12 }, |
| 3265 | { PseudoTHVdotVMAQAUS_VX_M8, 13 }, |
| 3266 | { PseudoTHVdotVMAQAUS_VX_MF2, 14 }, |
| 3267 | { PseudoTHVdotVMAQAU_VV_M1, 15 }, |
| 3268 | { PseudoTHVdotVMAQAU_VV_M2, 16 }, |
| 3269 | { PseudoTHVdotVMAQAU_VV_M4, 17 }, |
| 3270 | { PseudoTHVdotVMAQAU_VV_M8, 18 }, |
| 3271 | { PseudoTHVdotVMAQAU_VV_MF2, 19 }, |
| 3272 | { PseudoTHVdotVMAQAU_VX_M1, 20 }, |
| 3273 | { PseudoTHVdotVMAQAU_VX_M2, 21 }, |
| 3274 | { PseudoTHVdotVMAQAU_VX_M4, 22 }, |
| 3275 | { PseudoTHVdotVMAQAU_VX_M8, 23 }, |
| 3276 | { PseudoTHVdotVMAQAU_VX_MF2, 24 }, |
| 3277 | { PseudoTHVdotVMAQA_VV_M1, 25 }, |
| 3278 | { PseudoTHVdotVMAQA_VV_M2, 26 }, |
| 3279 | { PseudoTHVdotVMAQA_VV_M4, 27 }, |
| 3280 | { PseudoTHVdotVMAQA_VV_M8, 28 }, |
| 3281 | { PseudoTHVdotVMAQA_VV_MF2, 29 }, |
| 3282 | { PseudoTHVdotVMAQA_VX_M1, 30 }, |
| 3283 | { PseudoTHVdotVMAQA_VX_M2, 31 }, |
| 3284 | { PseudoTHVdotVMAQA_VX_M4, 32 }, |
| 3285 | { PseudoTHVdotVMAQA_VX_M8, 33 }, |
| 3286 | { PseudoTHVdotVMAQA_VX_MF2, 34 }, |
| 3287 | { PseudoVAADDU_VV_M1, 35 }, |
| 3288 | { PseudoVAADDU_VV_M2, 36 }, |
| 3289 | { PseudoVAADDU_VV_M4, 37 }, |
| 3290 | { PseudoVAADDU_VV_M8, 38 }, |
| 3291 | { PseudoVAADDU_VV_MF2, 39 }, |
| 3292 | { PseudoVAADDU_VV_MF4, 40 }, |
| 3293 | { PseudoVAADDU_VV_MF8, 41 }, |
| 3294 | { PseudoVAADDU_VX_M1, 42 }, |
| 3295 | { PseudoVAADDU_VX_M2, 43 }, |
| 3296 | { PseudoVAADDU_VX_M4, 44 }, |
| 3297 | { PseudoVAADDU_VX_M8, 45 }, |
| 3298 | { PseudoVAADDU_VX_MF2, 46 }, |
| 3299 | { PseudoVAADDU_VX_MF4, 47 }, |
| 3300 | { PseudoVAADDU_VX_MF8, 48 }, |
| 3301 | { PseudoVAADD_VV_M1, 49 }, |
| 3302 | { PseudoVAADD_VV_M2, 50 }, |
| 3303 | { PseudoVAADD_VV_M4, 51 }, |
| 3304 | { PseudoVAADD_VV_M8, 52 }, |
| 3305 | { PseudoVAADD_VV_MF2, 53 }, |
| 3306 | { PseudoVAADD_VV_MF4, 54 }, |
| 3307 | { PseudoVAADD_VV_MF8, 55 }, |
| 3308 | { PseudoVAADD_VX_M1, 56 }, |
| 3309 | { PseudoVAADD_VX_M2, 57 }, |
| 3310 | { PseudoVAADD_VX_M4, 58 }, |
| 3311 | { PseudoVAADD_VX_M8, 59 }, |
| 3312 | { PseudoVAADD_VX_MF2, 60 }, |
| 3313 | { PseudoVAADD_VX_MF4, 61 }, |
| 3314 | { PseudoVAADD_VX_MF8, 62 }, |
| 3315 | { PseudoVADD_VI_M1, 63 }, |
| 3316 | { PseudoVADD_VI_M2, 64 }, |
| 3317 | { PseudoVADD_VI_M4, 65 }, |
| 3318 | { PseudoVADD_VI_M8, 66 }, |
| 3319 | { PseudoVADD_VI_MF2, 67 }, |
| 3320 | { PseudoVADD_VI_MF4, 68 }, |
| 3321 | { PseudoVADD_VI_MF8, 69 }, |
| 3322 | { PseudoVADD_VV_M1, 70 }, |
| 3323 | { PseudoVADD_VV_M2, 71 }, |
| 3324 | { PseudoVADD_VV_M4, 72 }, |
| 3325 | { PseudoVADD_VV_M8, 73 }, |
| 3326 | { PseudoVADD_VV_MF2, 74 }, |
| 3327 | { PseudoVADD_VV_MF4, 75 }, |
| 3328 | { PseudoVADD_VV_MF8, 76 }, |
| 3329 | { PseudoVADD_VX_M1, 77 }, |
| 3330 | { PseudoVADD_VX_M2, 78 }, |
| 3331 | { PseudoVADD_VX_M4, 79 }, |
| 3332 | { PseudoVADD_VX_M8, 80 }, |
| 3333 | { PseudoVADD_VX_MF2, 81 }, |
| 3334 | { PseudoVADD_VX_MF4, 82 }, |
| 3335 | { PseudoVADD_VX_MF8, 83 }, |
| 3336 | { PseudoVANDN_VV_M1, 84 }, |
| 3337 | { PseudoVANDN_VV_M2, 85 }, |
| 3338 | { PseudoVANDN_VV_M4, 86 }, |
| 3339 | { PseudoVANDN_VV_M8, 87 }, |
| 3340 | { PseudoVANDN_VV_MF2, 88 }, |
| 3341 | { PseudoVANDN_VV_MF4, 89 }, |
| 3342 | { PseudoVANDN_VV_MF8, 90 }, |
| 3343 | { PseudoVANDN_VX_M1, 91 }, |
| 3344 | { PseudoVANDN_VX_M2, 92 }, |
| 3345 | { PseudoVANDN_VX_M4, 93 }, |
| 3346 | { PseudoVANDN_VX_M8, 94 }, |
| 3347 | { PseudoVANDN_VX_MF2, 95 }, |
| 3348 | { PseudoVANDN_VX_MF4, 96 }, |
| 3349 | { PseudoVANDN_VX_MF8, 97 }, |
| 3350 | { PseudoVAND_VI_M1, 98 }, |
| 3351 | { PseudoVAND_VI_M2, 99 }, |
| 3352 | { PseudoVAND_VI_M4, 100 }, |
| 3353 | { PseudoVAND_VI_M8, 101 }, |
| 3354 | { PseudoVAND_VI_MF2, 102 }, |
| 3355 | { PseudoVAND_VI_MF4, 103 }, |
| 3356 | { PseudoVAND_VI_MF8, 104 }, |
| 3357 | { PseudoVAND_VV_M1, 105 }, |
| 3358 | { PseudoVAND_VV_M2, 106 }, |
| 3359 | { PseudoVAND_VV_M4, 107 }, |
| 3360 | { PseudoVAND_VV_M8, 108 }, |
| 3361 | { PseudoVAND_VV_MF2, 109 }, |
| 3362 | { PseudoVAND_VV_MF4, 110 }, |
| 3363 | { PseudoVAND_VV_MF8, 111 }, |
| 3364 | { PseudoVAND_VX_M1, 112 }, |
| 3365 | { PseudoVAND_VX_M2, 113 }, |
| 3366 | { PseudoVAND_VX_M4, 114 }, |
| 3367 | { PseudoVAND_VX_M8, 115 }, |
| 3368 | { PseudoVAND_VX_MF2, 116 }, |
| 3369 | { PseudoVAND_VX_MF4, 117 }, |
| 3370 | { PseudoVAND_VX_MF8, 118 }, |
| 3371 | { PseudoVASUBU_VV_M1, 119 }, |
| 3372 | { PseudoVASUBU_VV_M2, 120 }, |
| 3373 | { PseudoVASUBU_VV_M4, 121 }, |
| 3374 | { PseudoVASUBU_VV_M8, 122 }, |
| 3375 | { PseudoVASUBU_VV_MF2, 123 }, |
| 3376 | { PseudoVASUBU_VV_MF4, 124 }, |
| 3377 | { PseudoVASUBU_VV_MF8, 125 }, |
| 3378 | { PseudoVASUBU_VX_M1, 126 }, |
| 3379 | { PseudoVASUBU_VX_M2, 127 }, |
| 3380 | { PseudoVASUBU_VX_M4, 128 }, |
| 3381 | { PseudoVASUBU_VX_M8, 129 }, |
| 3382 | { PseudoVASUBU_VX_MF2, 130 }, |
| 3383 | { PseudoVASUBU_VX_MF4, 131 }, |
| 3384 | { PseudoVASUBU_VX_MF8, 132 }, |
| 3385 | { PseudoVASUB_VV_M1, 133 }, |
| 3386 | { PseudoVASUB_VV_M2, 134 }, |
| 3387 | { PseudoVASUB_VV_M4, 135 }, |
| 3388 | { PseudoVASUB_VV_M8, 136 }, |
| 3389 | { PseudoVASUB_VV_MF2, 137 }, |
| 3390 | { PseudoVASUB_VV_MF4, 138 }, |
| 3391 | { PseudoVASUB_VV_MF8, 139 }, |
| 3392 | { PseudoVASUB_VX_M1, 140 }, |
| 3393 | { PseudoVASUB_VX_M2, 141 }, |
| 3394 | { PseudoVASUB_VX_M4, 142 }, |
| 3395 | { PseudoVASUB_VX_M8, 143 }, |
| 3396 | { PseudoVASUB_VX_MF2, 144 }, |
| 3397 | { PseudoVASUB_VX_MF4, 145 }, |
| 3398 | { PseudoVASUB_VX_MF8, 146 }, |
| 3399 | { PseudoVBREV8_V_M1, 147 }, |
| 3400 | { PseudoVBREV8_V_M2, 148 }, |
| 3401 | { PseudoVBREV8_V_M4, 149 }, |
| 3402 | { PseudoVBREV8_V_M8, 150 }, |
| 3403 | { PseudoVBREV8_V_MF2, 151 }, |
| 3404 | { PseudoVBREV8_V_MF4, 152 }, |
| 3405 | { PseudoVBREV8_V_MF8, 153 }, |
| 3406 | { PseudoVBREV_V_M1, 154 }, |
| 3407 | { PseudoVBREV_V_M2, 155 }, |
| 3408 | { PseudoVBREV_V_M4, 156 }, |
| 3409 | { PseudoVBREV_V_M8, 157 }, |
| 3410 | { PseudoVBREV_V_MF2, 158 }, |
| 3411 | { PseudoVBREV_V_MF4, 159 }, |
| 3412 | { PseudoVBREV_V_MF8, 160 }, |
| 3413 | { PseudoVCLMULH_VV_M1, 161 }, |
| 3414 | { PseudoVCLMULH_VV_M2, 162 }, |
| 3415 | { PseudoVCLMULH_VV_M4, 163 }, |
| 3416 | { PseudoVCLMULH_VV_M8, 164 }, |
| 3417 | { PseudoVCLMULH_VV_MF2, 165 }, |
| 3418 | { PseudoVCLMULH_VV_MF4, 166 }, |
| 3419 | { PseudoVCLMULH_VV_MF8, 167 }, |
| 3420 | { PseudoVCLMULH_VX_M1, 168 }, |
| 3421 | { PseudoVCLMULH_VX_M2, 169 }, |
| 3422 | { PseudoVCLMULH_VX_M4, 170 }, |
| 3423 | { PseudoVCLMULH_VX_M8, 171 }, |
| 3424 | { PseudoVCLMULH_VX_MF2, 172 }, |
| 3425 | { PseudoVCLMULH_VX_MF4, 173 }, |
| 3426 | { PseudoVCLMULH_VX_MF8, 174 }, |
| 3427 | { PseudoVCLMUL_VV_M1, 175 }, |
| 3428 | { PseudoVCLMUL_VV_M2, 176 }, |
| 3429 | { PseudoVCLMUL_VV_M4, 177 }, |
| 3430 | { PseudoVCLMUL_VV_M8, 178 }, |
| 3431 | { PseudoVCLMUL_VV_MF2, 179 }, |
| 3432 | { PseudoVCLMUL_VV_MF4, 180 }, |
| 3433 | { PseudoVCLMUL_VV_MF8, 181 }, |
| 3434 | { PseudoVCLMUL_VX_M1, 182 }, |
| 3435 | { PseudoVCLMUL_VX_M2, 183 }, |
| 3436 | { PseudoVCLMUL_VX_M4, 184 }, |
| 3437 | { PseudoVCLMUL_VX_M8, 185 }, |
| 3438 | { PseudoVCLMUL_VX_MF2, 186 }, |
| 3439 | { PseudoVCLMUL_VX_MF4, 187 }, |
| 3440 | { PseudoVCLMUL_VX_MF8, 188 }, |
| 3441 | { PseudoVCLZ_V_M1, 189 }, |
| 3442 | { PseudoVCLZ_V_M2, 190 }, |
| 3443 | { PseudoVCLZ_V_M4, 191 }, |
| 3444 | { PseudoVCLZ_V_M8, 192 }, |
| 3445 | { PseudoVCLZ_V_MF2, 193 }, |
| 3446 | { PseudoVCLZ_V_MF4, 194 }, |
| 3447 | { PseudoVCLZ_V_MF8, 195 }, |
| 3448 | { PseudoVCPOP_V_M1, 196 }, |
| 3449 | { PseudoVCPOP_V_M2, 197 }, |
| 3450 | { PseudoVCPOP_V_M4, 198 }, |
| 3451 | { PseudoVCPOP_V_M8, 199 }, |
| 3452 | { PseudoVCPOP_V_MF2, 200 }, |
| 3453 | { PseudoVCPOP_V_MF4, 201 }, |
| 3454 | { PseudoVCPOP_V_MF8, 202 }, |
| 3455 | { PseudoVCTZ_V_M1, 203 }, |
| 3456 | { PseudoVCTZ_V_M2, 204 }, |
| 3457 | { PseudoVCTZ_V_M4, 205 }, |
| 3458 | { PseudoVCTZ_V_M8, 206 }, |
| 3459 | { PseudoVCTZ_V_MF2, 207 }, |
| 3460 | { PseudoVCTZ_V_MF4, 208 }, |
| 3461 | { PseudoVCTZ_V_MF8, 209 }, |
| 3462 | { PseudoVDIVU_VV_M1_E16, 210 }, |
| 3463 | { PseudoVDIVU_VV_M1_E32, 211 }, |
| 3464 | { PseudoVDIVU_VV_M1_E64, 212 }, |
| 3465 | { PseudoVDIVU_VV_M1_E8, 213 }, |
| 3466 | { PseudoVDIVU_VV_M2_E16, 214 }, |
| 3467 | { PseudoVDIVU_VV_M2_E32, 215 }, |
| 3468 | { PseudoVDIVU_VV_M2_E64, 216 }, |
| 3469 | { PseudoVDIVU_VV_M2_E8, 217 }, |
| 3470 | { PseudoVDIVU_VV_M4_E16, 218 }, |
| 3471 | { PseudoVDIVU_VV_M4_E32, 219 }, |
| 3472 | { PseudoVDIVU_VV_M4_E64, 220 }, |
| 3473 | { PseudoVDIVU_VV_M4_E8, 221 }, |
| 3474 | { PseudoVDIVU_VV_M8_E16, 222 }, |
| 3475 | { PseudoVDIVU_VV_M8_E32, 223 }, |
| 3476 | { PseudoVDIVU_VV_M8_E64, 224 }, |
| 3477 | { PseudoVDIVU_VV_M8_E8, 225 }, |
| 3478 | { PseudoVDIVU_VV_MF2_E16, 226 }, |
| 3479 | { PseudoVDIVU_VV_MF2_E32, 227 }, |
| 3480 | { PseudoVDIVU_VV_MF2_E8, 228 }, |
| 3481 | { PseudoVDIVU_VV_MF4_E16, 229 }, |
| 3482 | { PseudoVDIVU_VV_MF4_E8, 230 }, |
| 3483 | { PseudoVDIVU_VV_MF8_E8, 231 }, |
| 3484 | { PseudoVDIVU_VX_M1_E16, 232 }, |
| 3485 | { PseudoVDIVU_VX_M1_E32, 233 }, |
| 3486 | { PseudoVDIVU_VX_M1_E64, 234 }, |
| 3487 | { PseudoVDIVU_VX_M1_E8, 235 }, |
| 3488 | { PseudoVDIVU_VX_M2_E16, 236 }, |
| 3489 | { PseudoVDIVU_VX_M2_E32, 237 }, |
| 3490 | { PseudoVDIVU_VX_M2_E64, 238 }, |
| 3491 | { PseudoVDIVU_VX_M2_E8, 239 }, |
| 3492 | { PseudoVDIVU_VX_M4_E16, 240 }, |
| 3493 | { PseudoVDIVU_VX_M4_E32, 241 }, |
| 3494 | { PseudoVDIVU_VX_M4_E64, 242 }, |
| 3495 | { PseudoVDIVU_VX_M4_E8, 243 }, |
| 3496 | { PseudoVDIVU_VX_M8_E16, 244 }, |
| 3497 | { PseudoVDIVU_VX_M8_E32, 245 }, |
| 3498 | { PseudoVDIVU_VX_M8_E64, 246 }, |
| 3499 | { PseudoVDIVU_VX_M8_E8, 247 }, |
| 3500 | { PseudoVDIVU_VX_MF2_E16, 248 }, |
| 3501 | { PseudoVDIVU_VX_MF2_E32, 249 }, |
| 3502 | { PseudoVDIVU_VX_MF2_E8, 250 }, |
| 3503 | { PseudoVDIVU_VX_MF4_E16, 251 }, |
| 3504 | { PseudoVDIVU_VX_MF4_E8, 252 }, |
| 3505 | { PseudoVDIVU_VX_MF8_E8, 253 }, |
| 3506 | { PseudoVDIV_VV_M1_E16, 254 }, |
| 3507 | { PseudoVDIV_VV_M1_E32, 255 }, |
| 3508 | { PseudoVDIV_VV_M1_E64, 256 }, |
| 3509 | { PseudoVDIV_VV_M1_E8, 257 }, |
| 3510 | { PseudoVDIV_VV_M2_E16, 258 }, |
| 3511 | { PseudoVDIV_VV_M2_E32, 259 }, |
| 3512 | { PseudoVDIV_VV_M2_E64, 260 }, |
| 3513 | { PseudoVDIV_VV_M2_E8, 261 }, |
| 3514 | { PseudoVDIV_VV_M4_E16, 262 }, |
| 3515 | { PseudoVDIV_VV_M4_E32, 263 }, |
| 3516 | { PseudoVDIV_VV_M4_E64, 264 }, |
| 3517 | { PseudoVDIV_VV_M4_E8, 265 }, |
| 3518 | { PseudoVDIV_VV_M8_E16, 266 }, |
| 3519 | { PseudoVDIV_VV_M8_E32, 267 }, |
| 3520 | { PseudoVDIV_VV_M8_E64, 268 }, |
| 3521 | { PseudoVDIV_VV_M8_E8, 269 }, |
| 3522 | { PseudoVDIV_VV_MF2_E16, 270 }, |
| 3523 | { PseudoVDIV_VV_MF2_E32, 271 }, |
| 3524 | { PseudoVDIV_VV_MF2_E8, 272 }, |
| 3525 | { PseudoVDIV_VV_MF4_E16, 273 }, |
| 3526 | { PseudoVDIV_VV_MF4_E8, 274 }, |
| 3527 | { PseudoVDIV_VV_MF8_E8, 275 }, |
| 3528 | { PseudoVDIV_VX_M1_E16, 276 }, |
| 3529 | { PseudoVDIV_VX_M1_E32, 277 }, |
| 3530 | { PseudoVDIV_VX_M1_E64, 278 }, |
| 3531 | { PseudoVDIV_VX_M1_E8, 279 }, |
| 3532 | { PseudoVDIV_VX_M2_E16, 280 }, |
| 3533 | { PseudoVDIV_VX_M2_E32, 281 }, |
| 3534 | { PseudoVDIV_VX_M2_E64, 282 }, |
| 3535 | { PseudoVDIV_VX_M2_E8, 283 }, |
| 3536 | { PseudoVDIV_VX_M4_E16, 284 }, |
| 3537 | { PseudoVDIV_VX_M4_E32, 285 }, |
| 3538 | { PseudoVDIV_VX_M4_E64, 286 }, |
| 3539 | { PseudoVDIV_VX_M4_E8, 287 }, |
| 3540 | { PseudoVDIV_VX_M8_E16, 288 }, |
| 3541 | { PseudoVDIV_VX_M8_E32, 289 }, |
| 3542 | { PseudoVDIV_VX_M8_E64, 290 }, |
| 3543 | { PseudoVDIV_VX_M8_E8, 291 }, |
| 3544 | { PseudoVDIV_VX_MF2_E16, 292 }, |
| 3545 | { PseudoVDIV_VX_MF2_E32, 293 }, |
| 3546 | { PseudoVDIV_VX_MF2_E8, 294 }, |
| 3547 | { PseudoVDIV_VX_MF4_E16, 295 }, |
| 3548 | { PseudoVDIV_VX_MF4_E8, 296 }, |
| 3549 | { PseudoVDIV_VX_MF8_E8, 297 }, |
| 3550 | { PseudoVFADD_VFPR16_M1_E16, 298 }, |
| 3551 | { PseudoVFADD_VFPR16_M2_E16, 299 }, |
| 3552 | { PseudoVFADD_VFPR16_M4_E16, 300 }, |
| 3553 | { PseudoVFADD_VFPR16_M8_E16, 301 }, |
| 3554 | { PseudoVFADD_VFPR16_MF2_E16, 302 }, |
| 3555 | { PseudoVFADD_VFPR16_MF4_E16, 303 }, |
| 3556 | { PseudoVFADD_VFPR32_M1_E32, 304 }, |
| 3557 | { PseudoVFADD_VFPR32_M2_E32, 305 }, |
| 3558 | { PseudoVFADD_VFPR32_M4_E32, 306 }, |
| 3559 | { PseudoVFADD_VFPR32_M8_E32, 307 }, |
| 3560 | { PseudoVFADD_VFPR32_MF2_E32, 308 }, |
| 3561 | { PseudoVFADD_VFPR64_M1_E64, 309 }, |
| 3562 | { PseudoVFADD_VFPR64_M2_E64, 310 }, |
| 3563 | { PseudoVFADD_VFPR64_M4_E64, 311 }, |
| 3564 | { PseudoVFADD_VFPR64_M8_E64, 312 }, |
| 3565 | { PseudoVFADD_VV_M1_E16, 313 }, |
| 3566 | { PseudoVFADD_VV_M1_E32, 314 }, |
| 3567 | { PseudoVFADD_VV_M1_E64, 315 }, |
| 3568 | { PseudoVFADD_VV_M2_E16, 316 }, |
| 3569 | { PseudoVFADD_VV_M2_E32, 317 }, |
| 3570 | { PseudoVFADD_VV_M2_E64, 318 }, |
| 3571 | { PseudoVFADD_VV_M4_E16, 319 }, |
| 3572 | { PseudoVFADD_VV_M4_E32, 320 }, |
| 3573 | { PseudoVFADD_VV_M4_E64, 321 }, |
| 3574 | { PseudoVFADD_VV_M8_E16, 322 }, |
| 3575 | { PseudoVFADD_VV_M8_E32, 323 }, |
| 3576 | { PseudoVFADD_VV_M8_E64, 324 }, |
| 3577 | { PseudoVFADD_VV_MF2_E16, 325 }, |
| 3578 | { PseudoVFADD_VV_MF2_E32, 326 }, |
| 3579 | { PseudoVFADD_VV_MF4_E16, 327 }, |
| 3580 | { PseudoVFCLASS_V_M1, 328 }, |
| 3581 | { PseudoVFCLASS_V_M2, 329 }, |
| 3582 | { PseudoVFCLASS_V_M4, 330 }, |
| 3583 | { PseudoVFCLASS_V_M8, 331 }, |
| 3584 | { PseudoVFCLASS_V_MF2, 332 }, |
| 3585 | { PseudoVFCLASS_V_MF4, 333 }, |
| 3586 | { PseudoVFCVT_F_XU_V_M1_E16, 334 }, |
| 3587 | { PseudoVFCVT_F_XU_V_M1_E32, 335 }, |
| 3588 | { PseudoVFCVT_F_XU_V_M1_E64, 336 }, |
| 3589 | { PseudoVFCVT_F_XU_V_M2_E16, 337 }, |
| 3590 | { PseudoVFCVT_F_XU_V_M2_E32, 338 }, |
| 3591 | { PseudoVFCVT_F_XU_V_M2_E64, 339 }, |
| 3592 | { PseudoVFCVT_F_XU_V_M4_E16, 340 }, |
| 3593 | { PseudoVFCVT_F_XU_V_M4_E32, 341 }, |
| 3594 | { PseudoVFCVT_F_XU_V_M4_E64, 342 }, |
| 3595 | { PseudoVFCVT_F_XU_V_M8_E16, 343 }, |
| 3596 | { PseudoVFCVT_F_XU_V_M8_E32, 344 }, |
| 3597 | { PseudoVFCVT_F_XU_V_M8_E64, 345 }, |
| 3598 | { PseudoVFCVT_F_XU_V_MF2_E16, 346 }, |
| 3599 | { PseudoVFCVT_F_XU_V_MF2_E32, 347 }, |
| 3600 | { PseudoVFCVT_F_XU_V_MF4_E16, 348 }, |
| 3601 | { PseudoVFCVT_F_X_V_M1_E16, 349 }, |
| 3602 | { PseudoVFCVT_F_X_V_M1_E32, 350 }, |
| 3603 | { PseudoVFCVT_F_X_V_M1_E64, 351 }, |
| 3604 | { PseudoVFCVT_F_X_V_M2_E16, 352 }, |
| 3605 | { PseudoVFCVT_F_X_V_M2_E32, 353 }, |
| 3606 | { PseudoVFCVT_F_X_V_M2_E64, 354 }, |
| 3607 | { PseudoVFCVT_F_X_V_M4_E16, 355 }, |
| 3608 | { PseudoVFCVT_F_X_V_M4_E32, 356 }, |
| 3609 | { PseudoVFCVT_F_X_V_M4_E64, 357 }, |
| 3610 | { PseudoVFCVT_F_X_V_M8_E16, 358 }, |
| 3611 | { PseudoVFCVT_F_X_V_M8_E32, 359 }, |
| 3612 | { PseudoVFCVT_F_X_V_M8_E64, 360 }, |
| 3613 | { PseudoVFCVT_F_X_V_MF2_E16, 361 }, |
| 3614 | { PseudoVFCVT_F_X_V_MF2_E32, 362 }, |
| 3615 | { PseudoVFCVT_F_X_V_MF4_E16, 363 }, |
| 3616 | { PseudoVFCVT_RM_F_XU_V_M1_E16, 364 }, |
| 3617 | { PseudoVFCVT_RM_F_XU_V_M1_E32, 365 }, |
| 3618 | { PseudoVFCVT_RM_F_XU_V_M1_E64, 366 }, |
| 3619 | { PseudoVFCVT_RM_F_XU_V_M2_E16, 367 }, |
| 3620 | { PseudoVFCVT_RM_F_XU_V_M2_E32, 368 }, |
| 3621 | { PseudoVFCVT_RM_F_XU_V_M2_E64, 369 }, |
| 3622 | { PseudoVFCVT_RM_F_XU_V_M4_E16, 370 }, |
| 3623 | { PseudoVFCVT_RM_F_XU_V_M4_E32, 371 }, |
| 3624 | { PseudoVFCVT_RM_F_XU_V_M4_E64, 372 }, |
| 3625 | { PseudoVFCVT_RM_F_XU_V_M8_E16, 373 }, |
| 3626 | { PseudoVFCVT_RM_F_XU_V_M8_E32, 374 }, |
| 3627 | { PseudoVFCVT_RM_F_XU_V_M8_E64, 375 }, |
| 3628 | { PseudoVFCVT_RM_F_XU_V_MF2_E16, 376 }, |
| 3629 | { PseudoVFCVT_RM_F_XU_V_MF2_E32, 377 }, |
| 3630 | { PseudoVFCVT_RM_F_XU_V_MF4_E16, 378 }, |
| 3631 | { PseudoVFCVT_RM_F_X_V_M1_E16, 379 }, |
| 3632 | { PseudoVFCVT_RM_F_X_V_M1_E32, 380 }, |
| 3633 | { PseudoVFCVT_RM_F_X_V_M1_E64, 381 }, |
| 3634 | { PseudoVFCVT_RM_F_X_V_M2_E16, 382 }, |
| 3635 | { PseudoVFCVT_RM_F_X_V_M2_E32, 383 }, |
| 3636 | { PseudoVFCVT_RM_F_X_V_M2_E64, 384 }, |
| 3637 | { PseudoVFCVT_RM_F_X_V_M4_E16, 385 }, |
| 3638 | { PseudoVFCVT_RM_F_X_V_M4_E32, 386 }, |
| 3639 | { PseudoVFCVT_RM_F_X_V_M4_E64, 387 }, |
| 3640 | { PseudoVFCVT_RM_F_X_V_M8_E16, 388 }, |
| 3641 | { PseudoVFCVT_RM_F_X_V_M8_E32, 389 }, |
| 3642 | { PseudoVFCVT_RM_F_X_V_M8_E64, 390 }, |
| 3643 | { PseudoVFCVT_RM_F_X_V_MF2_E16, 391 }, |
| 3644 | { PseudoVFCVT_RM_F_X_V_MF2_E32, 392 }, |
| 3645 | { PseudoVFCVT_RM_F_X_V_MF4_E16, 393 }, |
| 3646 | { PseudoVFCVT_RM_XU_F_V_M1, 394 }, |
| 3647 | { PseudoVFCVT_RM_XU_F_V_M2, 395 }, |
| 3648 | { PseudoVFCVT_RM_XU_F_V_M4, 396 }, |
| 3649 | { PseudoVFCVT_RM_XU_F_V_M8, 397 }, |
| 3650 | { PseudoVFCVT_RM_XU_F_V_MF2, 398 }, |
| 3651 | { PseudoVFCVT_RM_XU_F_V_MF4, 399 }, |
| 3652 | { PseudoVFCVT_RM_X_F_V_M1, 400 }, |
| 3653 | { PseudoVFCVT_RM_X_F_V_M2, 401 }, |
| 3654 | { PseudoVFCVT_RM_X_F_V_M4, 402 }, |
| 3655 | { PseudoVFCVT_RM_X_F_V_M8, 403 }, |
| 3656 | { PseudoVFCVT_RM_X_F_V_MF2, 404 }, |
| 3657 | { PseudoVFCVT_RM_X_F_V_MF4, 405 }, |
| 3658 | { PseudoVFCVT_RTZ_XU_F_V_M1, 406 }, |
| 3659 | { PseudoVFCVT_RTZ_XU_F_V_M2, 407 }, |
| 3660 | { PseudoVFCVT_RTZ_XU_F_V_M4, 408 }, |
| 3661 | { PseudoVFCVT_RTZ_XU_F_V_M8, 409 }, |
| 3662 | { PseudoVFCVT_RTZ_XU_F_V_MF2, 410 }, |
| 3663 | { PseudoVFCVT_RTZ_XU_F_V_MF4, 411 }, |
| 3664 | { PseudoVFCVT_RTZ_X_F_V_M1, 412 }, |
| 3665 | { PseudoVFCVT_RTZ_X_F_V_M2, 413 }, |
| 3666 | { PseudoVFCVT_RTZ_X_F_V_M4, 414 }, |
| 3667 | { PseudoVFCVT_RTZ_X_F_V_M8, 415 }, |
| 3668 | { PseudoVFCVT_RTZ_X_F_V_MF2, 416 }, |
| 3669 | { PseudoVFCVT_RTZ_X_F_V_MF4, 417 }, |
| 3670 | { PseudoVFCVT_XU_F_V_M1, 418 }, |
| 3671 | { PseudoVFCVT_XU_F_V_M2, 419 }, |
| 3672 | { PseudoVFCVT_XU_F_V_M4, 420 }, |
| 3673 | { PseudoVFCVT_XU_F_V_M8, 421 }, |
| 3674 | { PseudoVFCVT_XU_F_V_MF2, 422 }, |
| 3675 | { PseudoVFCVT_XU_F_V_MF4, 423 }, |
| 3676 | { PseudoVFCVT_X_F_V_M1, 424 }, |
| 3677 | { PseudoVFCVT_X_F_V_M2, 425 }, |
| 3678 | { PseudoVFCVT_X_F_V_M4, 426 }, |
| 3679 | { PseudoVFCVT_X_F_V_M8, 427 }, |
| 3680 | { PseudoVFCVT_X_F_V_MF2, 428 }, |
| 3681 | { PseudoVFCVT_X_F_V_MF4, 429 }, |
| 3682 | { PseudoVFDIV_VFPR16_M1_E16, 430 }, |
| 3683 | { PseudoVFDIV_VFPR16_M2_E16, 431 }, |
| 3684 | { PseudoVFDIV_VFPR16_M4_E16, 432 }, |
| 3685 | { PseudoVFDIV_VFPR16_M8_E16, 433 }, |
| 3686 | { PseudoVFDIV_VFPR16_MF2_E16, 434 }, |
| 3687 | { PseudoVFDIV_VFPR16_MF4_E16, 435 }, |
| 3688 | { PseudoVFDIV_VFPR32_M1_E32, 436 }, |
| 3689 | { PseudoVFDIV_VFPR32_M2_E32, 437 }, |
| 3690 | { PseudoVFDIV_VFPR32_M4_E32, 438 }, |
| 3691 | { PseudoVFDIV_VFPR32_M8_E32, 439 }, |
| 3692 | { PseudoVFDIV_VFPR32_MF2_E32, 440 }, |
| 3693 | { PseudoVFDIV_VFPR64_M1_E64, 441 }, |
| 3694 | { PseudoVFDIV_VFPR64_M2_E64, 442 }, |
| 3695 | { PseudoVFDIV_VFPR64_M4_E64, 443 }, |
| 3696 | { PseudoVFDIV_VFPR64_M8_E64, 444 }, |
| 3697 | { PseudoVFDIV_VV_M1_E16, 445 }, |
| 3698 | { PseudoVFDIV_VV_M1_E32, 446 }, |
| 3699 | { PseudoVFDIV_VV_M1_E64, 447 }, |
| 3700 | { PseudoVFDIV_VV_M2_E16, 448 }, |
| 3701 | { PseudoVFDIV_VV_M2_E32, 449 }, |
| 3702 | { PseudoVFDIV_VV_M2_E64, 450 }, |
| 3703 | { PseudoVFDIV_VV_M4_E16, 451 }, |
| 3704 | { PseudoVFDIV_VV_M4_E32, 452 }, |
| 3705 | { PseudoVFDIV_VV_M4_E64, 453 }, |
| 3706 | { PseudoVFDIV_VV_M8_E16, 454 }, |
| 3707 | { PseudoVFDIV_VV_M8_E32, 455 }, |
| 3708 | { PseudoVFDIV_VV_M8_E64, 456 }, |
| 3709 | { PseudoVFDIV_VV_MF2_E16, 457 }, |
| 3710 | { PseudoVFDIV_VV_MF2_E32, 458 }, |
| 3711 | { PseudoVFDIV_VV_MF4_E16, 459 }, |
| 3712 | { PseudoVFMACC_VFPR16_M1_E16, 460 }, |
| 3713 | { PseudoVFMACC_VFPR16_M2_E16, 461 }, |
| 3714 | { PseudoVFMACC_VFPR16_M4_E16, 462 }, |
| 3715 | { PseudoVFMACC_VFPR16_M8_E16, 463 }, |
| 3716 | { PseudoVFMACC_VFPR16_MF2_E16, 464 }, |
| 3717 | { PseudoVFMACC_VFPR16_MF4_E16, 465 }, |
| 3718 | { PseudoVFMACC_VFPR32_M1_E32, 466 }, |
| 3719 | { PseudoVFMACC_VFPR32_M2_E32, 467 }, |
| 3720 | { PseudoVFMACC_VFPR32_M4_E32, 468 }, |
| 3721 | { PseudoVFMACC_VFPR32_M8_E32, 469 }, |
| 3722 | { PseudoVFMACC_VFPR32_MF2_E32, 470 }, |
| 3723 | { PseudoVFMACC_VFPR64_M1_E64, 471 }, |
| 3724 | { PseudoVFMACC_VFPR64_M2_E64, 472 }, |
| 3725 | { PseudoVFMACC_VFPR64_M4_E64, 473 }, |
| 3726 | { PseudoVFMACC_VFPR64_M8_E64, 474 }, |
| 3727 | { PseudoVFMACC_VV_M1_E16, 475 }, |
| 3728 | { PseudoVFMACC_VV_M1_E32, 476 }, |
| 3729 | { PseudoVFMACC_VV_M1_E64, 477 }, |
| 3730 | { PseudoVFMACC_VV_M2_E16, 478 }, |
| 3731 | { PseudoVFMACC_VV_M2_E32, 479 }, |
| 3732 | { PseudoVFMACC_VV_M2_E64, 480 }, |
| 3733 | { PseudoVFMACC_VV_M4_E16, 481 }, |
| 3734 | { PseudoVFMACC_VV_M4_E32, 482 }, |
| 3735 | { PseudoVFMACC_VV_M4_E64, 483 }, |
| 3736 | { PseudoVFMACC_VV_M8_E16, 484 }, |
| 3737 | { PseudoVFMACC_VV_M8_E32, 485 }, |
| 3738 | { PseudoVFMACC_VV_M8_E64, 486 }, |
| 3739 | { PseudoVFMACC_VV_MF2_E16, 487 }, |
| 3740 | { PseudoVFMACC_VV_MF2_E32, 488 }, |
| 3741 | { PseudoVFMACC_VV_MF4_E16, 489 }, |
| 3742 | { PseudoVFMADD_VFPR16_M1_E16, 490 }, |
| 3743 | { PseudoVFMADD_VFPR16_M2_E16, 491 }, |
| 3744 | { PseudoVFMADD_VFPR16_M4_E16, 492 }, |
| 3745 | { PseudoVFMADD_VFPR16_M8_E16, 493 }, |
| 3746 | { PseudoVFMADD_VFPR16_MF2_E16, 494 }, |
| 3747 | { PseudoVFMADD_VFPR16_MF4_E16, 495 }, |
| 3748 | { PseudoVFMADD_VFPR32_M1_E32, 496 }, |
| 3749 | { PseudoVFMADD_VFPR32_M2_E32, 497 }, |
| 3750 | { PseudoVFMADD_VFPR32_M4_E32, 498 }, |
| 3751 | { PseudoVFMADD_VFPR32_M8_E32, 499 }, |
| 3752 | { PseudoVFMADD_VFPR32_MF2_E32, 500 }, |
| 3753 | { PseudoVFMADD_VFPR64_M1_E64, 501 }, |
| 3754 | { PseudoVFMADD_VFPR64_M2_E64, 502 }, |
| 3755 | { PseudoVFMADD_VFPR64_M4_E64, 503 }, |
| 3756 | { PseudoVFMADD_VFPR64_M8_E64, 504 }, |
| 3757 | { PseudoVFMADD_VV_M1_E16, 505 }, |
| 3758 | { PseudoVFMADD_VV_M1_E32, 506 }, |
| 3759 | { PseudoVFMADD_VV_M1_E64, 507 }, |
| 3760 | { PseudoVFMADD_VV_M2_E16, 508 }, |
| 3761 | { PseudoVFMADD_VV_M2_E32, 509 }, |
| 3762 | { PseudoVFMADD_VV_M2_E64, 510 }, |
| 3763 | { PseudoVFMADD_VV_M4_E16, 511 }, |
| 3764 | { PseudoVFMADD_VV_M4_E32, 512 }, |
| 3765 | { PseudoVFMADD_VV_M4_E64, 513 }, |
| 3766 | { PseudoVFMADD_VV_M8_E16, 514 }, |
| 3767 | { PseudoVFMADD_VV_M8_E32, 515 }, |
| 3768 | { PseudoVFMADD_VV_M8_E64, 516 }, |
| 3769 | { PseudoVFMADD_VV_MF2_E16, 517 }, |
| 3770 | { PseudoVFMADD_VV_MF2_E32, 518 }, |
| 3771 | { PseudoVFMADD_VV_MF4_E16, 519 }, |
| 3772 | { PseudoVFMAX_VFPR16_M1_E16, 520 }, |
| 3773 | { PseudoVFMAX_VFPR16_M2_E16, 521 }, |
| 3774 | { PseudoVFMAX_VFPR16_M4_E16, 522 }, |
| 3775 | { PseudoVFMAX_VFPR16_M8_E16, 523 }, |
| 3776 | { PseudoVFMAX_VFPR16_MF2_E16, 524 }, |
| 3777 | { PseudoVFMAX_VFPR16_MF4_E16, 525 }, |
| 3778 | { PseudoVFMAX_VFPR32_M1_E32, 526 }, |
| 3779 | { PseudoVFMAX_VFPR32_M2_E32, 527 }, |
| 3780 | { PseudoVFMAX_VFPR32_M4_E32, 528 }, |
| 3781 | { PseudoVFMAX_VFPR32_M8_E32, 529 }, |
| 3782 | { PseudoVFMAX_VFPR32_MF2_E32, 530 }, |
| 3783 | { PseudoVFMAX_VFPR64_M1_E64, 531 }, |
| 3784 | { PseudoVFMAX_VFPR64_M2_E64, 532 }, |
| 3785 | { PseudoVFMAX_VFPR64_M4_E64, 533 }, |
| 3786 | { PseudoVFMAX_VFPR64_M8_E64, 534 }, |
| 3787 | { PseudoVFMAX_VV_M1_E16, 535 }, |
| 3788 | { PseudoVFMAX_VV_M1_E32, 536 }, |
| 3789 | { PseudoVFMAX_VV_M1_E64, 537 }, |
| 3790 | { PseudoVFMAX_VV_M2_E16, 538 }, |
| 3791 | { PseudoVFMAX_VV_M2_E32, 539 }, |
| 3792 | { PseudoVFMAX_VV_M2_E64, 540 }, |
| 3793 | { PseudoVFMAX_VV_M4_E16, 541 }, |
| 3794 | { PseudoVFMAX_VV_M4_E32, 542 }, |
| 3795 | { PseudoVFMAX_VV_M4_E64, 543 }, |
| 3796 | { PseudoVFMAX_VV_M8_E16, 544 }, |
| 3797 | { PseudoVFMAX_VV_M8_E32, 545 }, |
| 3798 | { PseudoVFMAX_VV_M8_E64, 546 }, |
| 3799 | { PseudoVFMAX_VV_MF2_E16, 547 }, |
| 3800 | { PseudoVFMAX_VV_MF2_E32, 548 }, |
| 3801 | { PseudoVFMAX_VV_MF4_E16, 549 }, |
| 3802 | { PseudoVFMIN_VFPR16_M1_E16, 550 }, |
| 3803 | { PseudoVFMIN_VFPR16_M2_E16, 551 }, |
| 3804 | { PseudoVFMIN_VFPR16_M4_E16, 552 }, |
| 3805 | { PseudoVFMIN_VFPR16_M8_E16, 553 }, |
| 3806 | { PseudoVFMIN_VFPR16_MF2_E16, 554 }, |
| 3807 | { PseudoVFMIN_VFPR16_MF4_E16, 555 }, |
| 3808 | { PseudoVFMIN_VFPR32_M1_E32, 556 }, |
| 3809 | { PseudoVFMIN_VFPR32_M2_E32, 557 }, |
| 3810 | { PseudoVFMIN_VFPR32_M4_E32, 558 }, |
| 3811 | { PseudoVFMIN_VFPR32_M8_E32, 559 }, |
| 3812 | { PseudoVFMIN_VFPR32_MF2_E32, 560 }, |
| 3813 | { PseudoVFMIN_VFPR64_M1_E64, 561 }, |
| 3814 | { PseudoVFMIN_VFPR64_M2_E64, 562 }, |
| 3815 | { PseudoVFMIN_VFPR64_M4_E64, 563 }, |
| 3816 | { PseudoVFMIN_VFPR64_M8_E64, 564 }, |
| 3817 | { PseudoVFMIN_VV_M1_E16, 565 }, |
| 3818 | { PseudoVFMIN_VV_M1_E32, 566 }, |
| 3819 | { PseudoVFMIN_VV_M1_E64, 567 }, |
| 3820 | { PseudoVFMIN_VV_M2_E16, 568 }, |
| 3821 | { PseudoVFMIN_VV_M2_E32, 569 }, |
| 3822 | { PseudoVFMIN_VV_M2_E64, 570 }, |
| 3823 | { PseudoVFMIN_VV_M4_E16, 571 }, |
| 3824 | { PseudoVFMIN_VV_M4_E32, 572 }, |
| 3825 | { PseudoVFMIN_VV_M4_E64, 573 }, |
| 3826 | { PseudoVFMIN_VV_M8_E16, 574 }, |
| 3827 | { PseudoVFMIN_VV_M8_E32, 575 }, |
| 3828 | { PseudoVFMIN_VV_M8_E64, 576 }, |
| 3829 | { PseudoVFMIN_VV_MF2_E16, 577 }, |
| 3830 | { PseudoVFMIN_VV_MF2_E32, 578 }, |
| 3831 | { PseudoVFMIN_VV_MF4_E16, 579 }, |
| 3832 | { PseudoVFMSAC_VFPR16_M1_E16, 580 }, |
| 3833 | { PseudoVFMSAC_VFPR16_M2_E16, 581 }, |
| 3834 | { PseudoVFMSAC_VFPR16_M4_E16, 582 }, |
| 3835 | { PseudoVFMSAC_VFPR16_M8_E16, 583 }, |
| 3836 | { PseudoVFMSAC_VFPR16_MF2_E16, 584 }, |
| 3837 | { PseudoVFMSAC_VFPR16_MF4_E16, 585 }, |
| 3838 | { PseudoVFMSAC_VFPR32_M1_E32, 586 }, |
| 3839 | { PseudoVFMSAC_VFPR32_M2_E32, 587 }, |
| 3840 | { PseudoVFMSAC_VFPR32_M4_E32, 588 }, |
| 3841 | { PseudoVFMSAC_VFPR32_M8_E32, 589 }, |
| 3842 | { PseudoVFMSAC_VFPR32_MF2_E32, 590 }, |
| 3843 | { PseudoVFMSAC_VFPR64_M1_E64, 591 }, |
| 3844 | { PseudoVFMSAC_VFPR64_M2_E64, 592 }, |
| 3845 | { PseudoVFMSAC_VFPR64_M4_E64, 593 }, |
| 3846 | { PseudoVFMSAC_VFPR64_M8_E64, 594 }, |
| 3847 | { PseudoVFMSAC_VV_M1_E16, 595 }, |
| 3848 | { PseudoVFMSAC_VV_M1_E32, 596 }, |
| 3849 | { PseudoVFMSAC_VV_M1_E64, 597 }, |
| 3850 | { PseudoVFMSAC_VV_M2_E16, 598 }, |
| 3851 | { PseudoVFMSAC_VV_M2_E32, 599 }, |
| 3852 | { PseudoVFMSAC_VV_M2_E64, 600 }, |
| 3853 | { PseudoVFMSAC_VV_M4_E16, 601 }, |
| 3854 | { PseudoVFMSAC_VV_M4_E32, 602 }, |
| 3855 | { PseudoVFMSAC_VV_M4_E64, 603 }, |
| 3856 | { PseudoVFMSAC_VV_M8_E16, 604 }, |
| 3857 | { PseudoVFMSAC_VV_M8_E32, 605 }, |
| 3858 | { PseudoVFMSAC_VV_M8_E64, 606 }, |
| 3859 | { PseudoVFMSAC_VV_MF2_E16, 607 }, |
| 3860 | { PseudoVFMSAC_VV_MF2_E32, 608 }, |
| 3861 | { PseudoVFMSAC_VV_MF4_E16, 609 }, |
| 3862 | { PseudoVFMSUB_VFPR16_M1_E16, 610 }, |
| 3863 | { PseudoVFMSUB_VFPR16_M2_E16, 611 }, |
| 3864 | { PseudoVFMSUB_VFPR16_M4_E16, 612 }, |
| 3865 | { PseudoVFMSUB_VFPR16_M8_E16, 613 }, |
| 3866 | { PseudoVFMSUB_VFPR16_MF2_E16, 614 }, |
| 3867 | { PseudoVFMSUB_VFPR16_MF4_E16, 615 }, |
| 3868 | { PseudoVFMSUB_VFPR32_M1_E32, 616 }, |
| 3869 | { PseudoVFMSUB_VFPR32_M2_E32, 617 }, |
| 3870 | { PseudoVFMSUB_VFPR32_M4_E32, 618 }, |
| 3871 | { PseudoVFMSUB_VFPR32_M8_E32, 619 }, |
| 3872 | { PseudoVFMSUB_VFPR32_MF2_E32, 620 }, |
| 3873 | { PseudoVFMSUB_VFPR64_M1_E64, 621 }, |
| 3874 | { PseudoVFMSUB_VFPR64_M2_E64, 622 }, |
| 3875 | { PseudoVFMSUB_VFPR64_M4_E64, 623 }, |
| 3876 | { PseudoVFMSUB_VFPR64_M8_E64, 624 }, |
| 3877 | { PseudoVFMSUB_VV_M1_E16, 625 }, |
| 3878 | { PseudoVFMSUB_VV_M1_E32, 626 }, |
| 3879 | { PseudoVFMSUB_VV_M1_E64, 627 }, |
| 3880 | { PseudoVFMSUB_VV_M2_E16, 628 }, |
| 3881 | { PseudoVFMSUB_VV_M2_E32, 629 }, |
| 3882 | { PseudoVFMSUB_VV_M2_E64, 630 }, |
| 3883 | { PseudoVFMSUB_VV_M4_E16, 631 }, |
| 3884 | { PseudoVFMSUB_VV_M4_E32, 632 }, |
| 3885 | { PseudoVFMSUB_VV_M4_E64, 633 }, |
| 3886 | { PseudoVFMSUB_VV_M8_E16, 634 }, |
| 3887 | { PseudoVFMSUB_VV_M8_E32, 635 }, |
| 3888 | { PseudoVFMSUB_VV_M8_E64, 636 }, |
| 3889 | { PseudoVFMSUB_VV_MF2_E16, 637 }, |
| 3890 | { PseudoVFMSUB_VV_MF2_E32, 638 }, |
| 3891 | { PseudoVFMSUB_VV_MF4_E16, 639 }, |
| 3892 | { PseudoVFMUL_VFPR16_M1_E16, 640 }, |
| 3893 | { PseudoVFMUL_VFPR16_M2_E16, 641 }, |
| 3894 | { PseudoVFMUL_VFPR16_M4_E16, 642 }, |
| 3895 | { PseudoVFMUL_VFPR16_M8_E16, 643 }, |
| 3896 | { PseudoVFMUL_VFPR16_MF2_E16, 644 }, |
| 3897 | { PseudoVFMUL_VFPR16_MF4_E16, 645 }, |
| 3898 | { PseudoVFMUL_VFPR32_M1_E32, 646 }, |
| 3899 | { PseudoVFMUL_VFPR32_M2_E32, 647 }, |
| 3900 | { PseudoVFMUL_VFPR32_M4_E32, 648 }, |
| 3901 | { PseudoVFMUL_VFPR32_M8_E32, 649 }, |
| 3902 | { PseudoVFMUL_VFPR32_MF2_E32, 650 }, |
| 3903 | { PseudoVFMUL_VFPR64_M1_E64, 651 }, |
| 3904 | { PseudoVFMUL_VFPR64_M2_E64, 652 }, |
| 3905 | { PseudoVFMUL_VFPR64_M4_E64, 653 }, |
| 3906 | { PseudoVFMUL_VFPR64_M8_E64, 654 }, |
| 3907 | { PseudoVFMUL_VV_M1_E16, 655 }, |
| 3908 | { PseudoVFMUL_VV_M1_E32, 656 }, |
| 3909 | { PseudoVFMUL_VV_M1_E64, 657 }, |
| 3910 | { PseudoVFMUL_VV_M2_E16, 658 }, |
| 3911 | { PseudoVFMUL_VV_M2_E32, 659 }, |
| 3912 | { PseudoVFMUL_VV_M2_E64, 660 }, |
| 3913 | { PseudoVFMUL_VV_M4_E16, 661 }, |
| 3914 | { PseudoVFMUL_VV_M4_E32, 662 }, |
| 3915 | { PseudoVFMUL_VV_M4_E64, 663 }, |
| 3916 | { PseudoVFMUL_VV_M8_E16, 664 }, |
| 3917 | { PseudoVFMUL_VV_M8_E32, 665 }, |
| 3918 | { PseudoVFMUL_VV_M8_E64, 666 }, |
| 3919 | { PseudoVFMUL_VV_MF2_E16, 667 }, |
| 3920 | { PseudoVFMUL_VV_MF2_E32, 668 }, |
| 3921 | { PseudoVFMUL_VV_MF4_E16, 669 }, |
| 3922 | { PseudoVFNCVTBF16_F_F_W_M1_E16, 670 }, |
| 3923 | { PseudoVFNCVTBF16_F_F_W_M1_E32, 671 }, |
| 3924 | { PseudoVFNCVTBF16_F_F_W_M2_E16, 672 }, |
| 3925 | { PseudoVFNCVTBF16_F_F_W_M2_E32, 673 }, |
| 3926 | { PseudoVFNCVTBF16_F_F_W_M4_E16, 674 }, |
| 3927 | { PseudoVFNCVTBF16_F_F_W_M4_E32, 675 }, |
| 3928 | { PseudoVFNCVTBF16_F_F_W_MF2_E16, 676 }, |
| 3929 | { PseudoVFNCVTBF16_F_F_W_MF2_E32, 677 }, |
| 3930 | { PseudoVFNCVTBF16_F_F_W_MF4_E16, 678 }, |
| 3931 | { PseudoVFNCVT_F_F_W_M1_E16, 679 }, |
| 3932 | { PseudoVFNCVT_F_F_W_M1_E32, 680 }, |
| 3933 | { PseudoVFNCVT_F_F_W_M2_E16, 681 }, |
| 3934 | { PseudoVFNCVT_F_F_W_M2_E32, 682 }, |
| 3935 | { PseudoVFNCVT_F_F_W_M4_E16, 683 }, |
| 3936 | { PseudoVFNCVT_F_F_W_M4_E32, 684 }, |
| 3937 | { PseudoVFNCVT_F_F_W_MF2_E16, 685 }, |
| 3938 | { PseudoVFNCVT_F_F_W_MF2_E32, 686 }, |
| 3939 | { PseudoVFNCVT_F_F_W_MF4_E16, 687 }, |
| 3940 | { PseudoVFNCVT_F_XU_W_M1_E16, 688 }, |
| 3941 | { PseudoVFNCVT_F_XU_W_M1_E32, 689 }, |
| 3942 | { PseudoVFNCVT_F_XU_W_M2_E16, 690 }, |
| 3943 | { PseudoVFNCVT_F_XU_W_M2_E32, 691 }, |
| 3944 | { PseudoVFNCVT_F_XU_W_M4_E16, 692 }, |
| 3945 | { PseudoVFNCVT_F_XU_W_M4_E32, 693 }, |
| 3946 | { PseudoVFNCVT_F_XU_W_MF2_E16, 694 }, |
| 3947 | { PseudoVFNCVT_F_XU_W_MF2_E32, 695 }, |
| 3948 | { PseudoVFNCVT_F_XU_W_MF4_E16, 696 }, |
| 3949 | { PseudoVFNCVT_F_X_W_M1_E16, 697 }, |
| 3950 | { PseudoVFNCVT_F_X_W_M1_E32, 698 }, |
| 3951 | { PseudoVFNCVT_F_X_W_M2_E16, 699 }, |
| 3952 | { PseudoVFNCVT_F_X_W_M2_E32, 700 }, |
| 3953 | { PseudoVFNCVT_F_X_W_M4_E16, 701 }, |
| 3954 | { PseudoVFNCVT_F_X_W_M4_E32, 702 }, |
| 3955 | { PseudoVFNCVT_F_X_W_MF2_E16, 703 }, |
| 3956 | { PseudoVFNCVT_F_X_W_MF2_E32, 704 }, |
| 3957 | { PseudoVFNCVT_F_X_W_MF4_E16, 705 }, |
| 3958 | { PseudoVFNCVT_RM_F_XU_W_M1_E16, 706 }, |
| 3959 | { PseudoVFNCVT_RM_F_XU_W_M1_E32, 707 }, |
| 3960 | { PseudoVFNCVT_RM_F_XU_W_M2_E16, 708 }, |
| 3961 | { PseudoVFNCVT_RM_F_XU_W_M2_E32, 709 }, |
| 3962 | { PseudoVFNCVT_RM_F_XU_W_M4_E16, 710 }, |
| 3963 | { PseudoVFNCVT_RM_F_XU_W_M4_E32, 711 }, |
| 3964 | { PseudoVFNCVT_RM_F_XU_W_MF2_E16, 712 }, |
| 3965 | { PseudoVFNCVT_RM_F_XU_W_MF2_E32, 713 }, |
| 3966 | { PseudoVFNCVT_RM_F_XU_W_MF4_E16, 714 }, |
| 3967 | { PseudoVFNCVT_RM_F_X_W_M1_E16, 715 }, |
| 3968 | { PseudoVFNCVT_RM_F_X_W_M1_E32, 716 }, |
| 3969 | { PseudoVFNCVT_RM_F_X_W_M2_E16, 717 }, |
| 3970 | { PseudoVFNCVT_RM_F_X_W_M2_E32, 718 }, |
| 3971 | { PseudoVFNCVT_RM_F_X_W_M4_E16, 719 }, |
| 3972 | { PseudoVFNCVT_RM_F_X_W_M4_E32, 720 }, |
| 3973 | { PseudoVFNCVT_RM_F_X_W_MF2_E16, 721 }, |
| 3974 | { PseudoVFNCVT_RM_F_X_W_MF2_E32, 722 }, |
| 3975 | { PseudoVFNCVT_RM_F_X_W_MF4_E16, 723 }, |
| 3976 | { PseudoVFNCVT_RM_XU_F_W_M1, 724 }, |
| 3977 | { PseudoVFNCVT_RM_XU_F_W_M2, 725 }, |
| 3978 | { PseudoVFNCVT_RM_XU_F_W_M4, 726 }, |
| 3979 | { PseudoVFNCVT_RM_XU_F_W_MF2, 727 }, |
| 3980 | { PseudoVFNCVT_RM_XU_F_W_MF4, 728 }, |
| 3981 | { PseudoVFNCVT_RM_XU_F_W_MF8, 729 }, |
| 3982 | { PseudoVFNCVT_RM_X_F_W_M1, 730 }, |
| 3983 | { PseudoVFNCVT_RM_X_F_W_M2, 731 }, |
| 3984 | { PseudoVFNCVT_RM_X_F_W_M4, 732 }, |
| 3985 | { PseudoVFNCVT_RM_X_F_W_MF2, 733 }, |
| 3986 | { PseudoVFNCVT_RM_X_F_W_MF4, 734 }, |
| 3987 | { PseudoVFNCVT_RM_X_F_W_MF8, 735 }, |
| 3988 | { PseudoVFNCVT_ROD_F_F_W_M1_E16, 736 }, |
| 3989 | { PseudoVFNCVT_ROD_F_F_W_M1_E32, 737 }, |
| 3990 | { PseudoVFNCVT_ROD_F_F_W_M2_E16, 738 }, |
| 3991 | { PseudoVFNCVT_ROD_F_F_W_M2_E32, 739 }, |
| 3992 | { PseudoVFNCVT_ROD_F_F_W_M4_E16, 740 }, |
| 3993 | { PseudoVFNCVT_ROD_F_F_W_M4_E32, 741 }, |
| 3994 | { PseudoVFNCVT_ROD_F_F_W_MF2_E16, 742 }, |
| 3995 | { PseudoVFNCVT_ROD_F_F_W_MF2_E32, 743 }, |
| 3996 | { PseudoVFNCVT_ROD_F_F_W_MF4_E16, 744 }, |
| 3997 | { PseudoVFNCVT_RTZ_XU_F_W_M1, 745 }, |
| 3998 | { PseudoVFNCVT_RTZ_XU_F_W_M2, 746 }, |
| 3999 | { PseudoVFNCVT_RTZ_XU_F_W_M4, 747 }, |
| 4000 | { PseudoVFNCVT_RTZ_XU_F_W_MF2, 748 }, |
| 4001 | { PseudoVFNCVT_RTZ_XU_F_W_MF4, 749 }, |
| 4002 | { PseudoVFNCVT_RTZ_XU_F_W_MF8, 750 }, |
| 4003 | { PseudoVFNCVT_RTZ_X_F_W_M1, 751 }, |
| 4004 | { PseudoVFNCVT_RTZ_X_F_W_M2, 752 }, |
| 4005 | { PseudoVFNCVT_RTZ_X_F_W_M4, 753 }, |
| 4006 | { PseudoVFNCVT_RTZ_X_F_W_MF2, 754 }, |
| 4007 | { PseudoVFNCVT_RTZ_X_F_W_MF4, 755 }, |
| 4008 | { PseudoVFNCVT_RTZ_X_F_W_MF8, 756 }, |
| 4009 | { PseudoVFNCVT_XU_F_W_M1, 757 }, |
| 4010 | { PseudoVFNCVT_XU_F_W_M2, 758 }, |
| 4011 | { PseudoVFNCVT_XU_F_W_M4, 759 }, |
| 4012 | { PseudoVFNCVT_XU_F_W_MF2, 760 }, |
| 4013 | { PseudoVFNCVT_XU_F_W_MF4, 761 }, |
| 4014 | { PseudoVFNCVT_XU_F_W_MF8, 762 }, |
| 4015 | { PseudoVFNCVT_X_F_W_M1, 763 }, |
| 4016 | { PseudoVFNCVT_X_F_W_M2, 764 }, |
| 4017 | { PseudoVFNCVT_X_F_W_M4, 765 }, |
| 4018 | { PseudoVFNCVT_X_F_W_MF2, 766 }, |
| 4019 | { PseudoVFNCVT_X_F_W_MF4, 767 }, |
| 4020 | { PseudoVFNCVT_X_F_W_MF8, 768 }, |
| 4021 | { PseudoVFNMACC_VFPR16_M1_E16, 769 }, |
| 4022 | { PseudoVFNMACC_VFPR16_M2_E16, 770 }, |
| 4023 | { PseudoVFNMACC_VFPR16_M4_E16, 771 }, |
| 4024 | { PseudoVFNMACC_VFPR16_M8_E16, 772 }, |
| 4025 | { PseudoVFNMACC_VFPR16_MF2_E16, 773 }, |
| 4026 | { PseudoVFNMACC_VFPR16_MF4_E16, 774 }, |
| 4027 | { PseudoVFNMACC_VFPR32_M1_E32, 775 }, |
| 4028 | { PseudoVFNMACC_VFPR32_M2_E32, 776 }, |
| 4029 | { PseudoVFNMACC_VFPR32_M4_E32, 777 }, |
| 4030 | { PseudoVFNMACC_VFPR32_M8_E32, 778 }, |
| 4031 | { PseudoVFNMACC_VFPR32_MF2_E32, 779 }, |
| 4032 | { PseudoVFNMACC_VFPR64_M1_E64, 780 }, |
| 4033 | { PseudoVFNMACC_VFPR64_M2_E64, 781 }, |
| 4034 | { PseudoVFNMACC_VFPR64_M4_E64, 782 }, |
| 4035 | { PseudoVFNMACC_VFPR64_M8_E64, 783 }, |
| 4036 | { PseudoVFNMACC_VV_M1_E16, 784 }, |
| 4037 | { PseudoVFNMACC_VV_M1_E32, 785 }, |
| 4038 | { PseudoVFNMACC_VV_M1_E64, 786 }, |
| 4039 | { PseudoVFNMACC_VV_M2_E16, 787 }, |
| 4040 | { PseudoVFNMACC_VV_M2_E32, 788 }, |
| 4041 | { PseudoVFNMACC_VV_M2_E64, 789 }, |
| 4042 | { PseudoVFNMACC_VV_M4_E16, 790 }, |
| 4043 | { PseudoVFNMACC_VV_M4_E32, 791 }, |
| 4044 | { PseudoVFNMACC_VV_M4_E64, 792 }, |
| 4045 | { PseudoVFNMACC_VV_M8_E16, 793 }, |
| 4046 | { PseudoVFNMACC_VV_M8_E32, 794 }, |
| 4047 | { PseudoVFNMACC_VV_M8_E64, 795 }, |
| 4048 | { PseudoVFNMACC_VV_MF2_E16, 796 }, |
| 4049 | { PseudoVFNMACC_VV_MF2_E32, 797 }, |
| 4050 | { PseudoVFNMACC_VV_MF4_E16, 798 }, |
| 4051 | { PseudoVFNMADD_VFPR16_M1_E16, 799 }, |
| 4052 | { PseudoVFNMADD_VFPR16_M2_E16, 800 }, |
| 4053 | { PseudoVFNMADD_VFPR16_M4_E16, 801 }, |
| 4054 | { PseudoVFNMADD_VFPR16_M8_E16, 802 }, |
| 4055 | { PseudoVFNMADD_VFPR16_MF2_E16, 803 }, |
| 4056 | { PseudoVFNMADD_VFPR16_MF4_E16, 804 }, |
| 4057 | { PseudoVFNMADD_VFPR32_M1_E32, 805 }, |
| 4058 | { PseudoVFNMADD_VFPR32_M2_E32, 806 }, |
| 4059 | { PseudoVFNMADD_VFPR32_M4_E32, 807 }, |
| 4060 | { PseudoVFNMADD_VFPR32_M8_E32, 808 }, |
| 4061 | { PseudoVFNMADD_VFPR32_MF2_E32, 809 }, |
| 4062 | { PseudoVFNMADD_VFPR64_M1_E64, 810 }, |
| 4063 | { PseudoVFNMADD_VFPR64_M2_E64, 811 }, |
| 4064 | { PseudoVFNMADD_VFPR64_M4_E64, 812 }, |
| 4065 | { PseudoVFNMADD_VFPR64_M8_E64, 813 }, |
| 4066 | { PseudoVFNMADD_VV_M1_E16, 814 }, |
| 4067 | { PseudoVFNMADD_VV_M1_E32, 815 }, |
| 4068 | { PseudoVFNMADD_VV_M1_E64, 816 }, |
| 4069 | { PseudoVFNMADD_VV_M2_E16, 817 }, |
| 4070 | { PseudoVFNMADD_VV_M2_E32, 818 }, |
| 4071 | { PseudoVFNMADD_VV_M2_E64, 819 }, |
| 4072 | { PseudoVFNMADD_VV_M4_E16, 820 }, |
| 4073 | { PseudoVFNMADD_VV_M4_E32, 821 }, |
| 4074 | { PseudoVFNMADD_VV_M4_E64, 822 }, |
| 4075 | { PseudoVFNMADD_VV_M8_E16, 823 }, |
| 4076 | { PseudoVFNMADD_VV_M8_E32, 824 }, |
| 4077 | { PseudoVFNMADD_VV_M8_E64, 825 }, |
| 4078 | { PseudoVFNMADD_VV_MF2_E16, 826 }, |
| 4079 | { PseudoVFNMADD_VV_MF2_E32, 827 }, |
| 4080 | { PseudoVFNMADD_VV_MF4_E16, 828 }, |
| 4081 | { PseudoVFNMSAC_VFPR16_M1_E16, 829 }, |
| 4082 | { PseudoVFNMSAC_VFPR16_M2_E16, 830 }, |
| 4083 | { PseudoVFNMSAC_VFPR16_M4_E16, 831 }, |
| 4084 | { PseudoVFNMSAC_VFPR16_M8_E16, 832 }, |
| 4085 | { PseudoVFNMSAC_VFPR16_MF2_E16, 833 }, |
| 4086 | { PseudoVFNMSAC_VFPR16_MF4_E16, 834 }, |
| 4087 | { PseudoVFNMSAC_VFPR32_M1_E32, 835 }, |
| 4088 | { PseudoVFNMSAC_VFPR32_M2_E32, 836 }, |
| 4089 | { PseudoVFNMSAC_VFPR32_M4_E32, 837 }, |
| 4090 | { PseudoVFNMSAC_VFPR32_M8_E32, 838 }, |
| 4091 | { PseudoVFNMSAC_VFPR32_MF2_E32, 839 }, |
| 4092 | { PseudoVFNMSAC_VFPR64_M1_E64, 840 }, |
| 4093 | { PseudoVFNMSAC_VFPR64_M2_E64, 841 }, |
| 4094 | { PseudoVFNMSAC_VFPR64_M4_E64, 842 }, |
| 4095 | { PseudoVFNMSAC_VFPR64_M8_E64, 843 }, |
| 4096 | { PseudoVFNMSAC_VV_M1_E16, 844 }, |
| 4097 | { PseudoVFNMSAC_VV_M1_E32, 845 }, |
| 4098 | { PseudoVFNMSAC_VV_M1_E64, 846 }, |
| 4099 | { PseudoVFNMSAC_VV_M2_E16, 847 }, |
| 4100 | { PseudoVFNMSAC_VV_M2_E32, 848 }, |
| 4101 | { PseudoVFNMSAC_VV_M2_E64, 849 }, |
| 4102 | { PseudoVFNMSAC_VV_M4_E16, 850 }, |
| 4103 | { PseudoVFNMSAC_VV_M4_E32, 851 }, |
| 4104 | { PseudoVFNMSAC_VV_M4_E64, 852 }, |
| 4105 | { PseudoVFNMSAC_VV_M8_E16, 853 }, |
| 4106 | { PseudoVFNMSAC_VV_M8_E32, 854 }, |
| 4107 | { PseudoVFNMSAC_VV_M8_E64, 855 }, |
| 4108 | { PseudoVFNMSAC_VV_MF2_E16, 856 }, |
| 4109 | { PseudoVFNMSAC_VV_MF2_E32, 857 }, |
| 4110 | { PseudoVFNMSAC_VV_MF4_E16, 858 }, |
| 4111 | { PseudoVFNMSUB_VFPR16_M1_E16, 859 }, |
| 4112 | { PseudoVFNMSUB_VFPR16_M2_E16, 860 }, |
| 4113 | { PseudoVFNMSUB_VFPR16_M4_E16, 861 }, |
| 4114 | { PseudoVFNMSUB_VFPR16_M8_E16, 862 }, |
| 4115 | { PseudoVFNMSUB_VFPR16_MF2_E16, 863 }, |
| 4116 | { PseudoVFNMSUB_VFPR16_MF4_E16, 864 }, |
| 4117 | { PseudoVFNMSUB_VFPR32_M1_E32, 865 }, |
| 4118 | { PseudoVFNMSUB_VFPR32_M2_E32, 866 }, |
| 4119 | { PseudoVFNMSUB_VFPR32_M4_E32, 867 }, |
| 4120 | { PseudoVFNMSUB_VFPR32_M8_E32, 868 }, |
| 4121 | { PseudoVFNMSUB_VFPR32_MF2_E32, 869 }, |
| 4122 | { PseudoVFNMSUB_VFPR64_M1_E64, 870 }, |
| 4123 | { PseudoVFNMSUB_VFPR64_M2_E64, 871 }, |
| 4124 | { PseudoVFNMSUB_VFPR64_M4_E64, 872 }, |
| 4125 | { PseudoVFNMSUB_VFPR64_M8_E64, 873 }, |
| 4126 | { PseudoVFNMSUB_VV_M1_E16, 874 }, |
| 4127 | { PseudoVFNMSUB_VV_M1_E32, 875 }, |
| 4128 | { PseudoVFNMSUB_VV_M1_E64, 876 }, |
| 4129 | { PseudoVFNMSUB_VV_M2_E16, 877 }, |
| 4130 | { PseudoVFNMSUB_VV_M2_E32, 878 }, |
| 4131 | { PseudoVFNMSUB_VV_M2_E64, 879 }, |
| 4132 | { PseudoVFNMSUB_VV_M4_E16, 880 }, |
| 4133 | { PseudoVFNMSUB_VV_M4_E32, 881 }, |
| 4134 | { PseudoVFNMSUB_VV_M4_E64, 882 }, |
| 4135 | { PseudoVFNMSUB_VV_M8_E16, 883 }, |
| 4136 | { PseudoVFNMSUB_VV_M8_E32, 884 }, |
| 4137 | { PseudoVFNMSUB_VV_M8_E64, 885 }, |
| 4138 | { PseudoVFNMSUB_VV_MF2_E16, 886 }, |
| 4139 | { PseudoVFNMSUB_VV_MF2_E32, 887 }, |
| 4140 | { PseudoVFNMSUB_VV_MF4_E16, 888 }, |
| 4141 | { PseudoVFNRCLIP_XU_F_QF_M1, 889 }, |
| 4142 | { PseudoVFNRCLIP_XU_F_QF_M2, 890 }, |
| 4143 | { PseudoVFNRCLIP_XU_F_QF_MF2, 891 }, |
| 4144 | { PseudoVFNRCLIP_XU_F_QF_MF4, 892 }, |
| 4145 | { PseudoVFNRCLIP_XU_F_QF_MF8, 893 }, |
| 4146 | { PseudoVFNRCLIP_X_F_QF_M1, 894 }, |
| 4147 | { PseudoVFNRCLIP_X_F_QF_M2, 895 }, |
| 4148 | { PseudoVFNRCLIP_X_F_QF_MF2, 896 }, |
| 4149 | { PseudoVFNRCLIP_X_F_QF_MF4, 897 }, |
| 4150 | { PseudoVFNRCLIP_X_F_QF_MF8, 898 }, |
| 4151 | { PseudoVFRDIV_VFPR16_M1_E16, 899 }, |
| 4152 | { PseudoVFRDIV_VFPR16_M2_E16, 900 }, |
| 4153 | { PseudoVFRDIV_VFPR16_M4_E16, 901 }, |
| 4154 | { PseudoVFRDIV_VFPR16_M8_E16, 902 }, |
| 4155 | { PseudoVFRDIV_VFPR16_MF2_E16, 903 }, |
| 4156 | { PseudoVFRDIV_VFPR16_MF4_E16, 904 }, |
| 4157 | { PseudoVFRDIV_VFPR32_M1_E32, 905 }, |
| 4158 | { PseudoVFRDIV_VFPR32_M2_E32, 906 }, |
| 4159 | { PseudoVFRDIV_VFPR32_M4_E32, 907 }, |
| 4160 | { PseudoVFRDIV_VFPR32_M8_E32, 908 }, |
| 4161 | { PseudoVFRDIV_VFPR32_MF2_E32, 909 }, |
| 4162 | { PseudoVFRDIV_VFPR64_M1_E64, 910 }, |
| 4163 | { PseudoVFRDIV_VFPR64_M2_E64, 911 }, |
| 4164 | { PseudoVFRDIV_VFPR64_M4_E64, 912 }, |
| 4165 | { PseudoVFRDIV_VFPR64_M8_E64, 913 }, |
| 4166 | { PseudoVFREC7_V_M1_E16, 914 }, |
| 4167 | { PseudoVFREC7_V_M1_E32, 915 }, |
| 4168 | { PseudoVFREC7_V_M1_E64, 916 }, |
| 4169 | { PseudoVFREC7_V_M2_E16, 917 }, |
| 4170 | { PseudoVFREC7_V_M2_E32, 918 }, |
| 4171 | { PseudoVFREC7_V_M2_E64, 919 }, |
| 4172 | { PseudoVFREC7_V_M4_E16, 920 }, |
| 4173 | { PseudoVFREC7_V_M4_E32, 921 }, |
| 4174 | { PseudoVFREC7_V_M4_E64, 922 }, |
| 4175 | { PseudoVFREC7_V_M8_E16, 923 }, |
| 4176 | { PseudoVFREC7_V_M8_E32, 924 }, |
| 4177 | { PseudoVFREC7_V_M8_E64, 925 }, |
| 4178 | { PseudoVFREC7_V_MF2_E16, 926 }, |
| 4179 | { PseudoVFREC7_V_MF2_E32, 927 }, |
| 4180 | { PseudoVFREC7_V_MF4_E16, 928 }, |
| 4181 | { PseudoVFREDMAX_VS_M1_E16, 929 }, |
| 4182 | { PseudoVFREDMAX_VS_M1_E32, 930 }, |
| 4183 | { PseudoVFREDMAX_VS_M1_E64, 931 }, |
| 4184 | { PseudoVFREDMAX_VS_M2_E16, 932 }, |
| 4185 | { PseudoVFREDMAX_VS_M2_E32, 933 }, |
| 4186 | { PseudoVFREDMAX_VS_M2_E64, 934 }, |
| 4187 | { PseudoVFREDMAX_VS_M4_E16, 935 }, |
| 4188 | { PseudoVFREDMAX_VS_M4_E32, 936 }, |
| 4189 | { PseudoVFREDMAX_VS_M4_E64, 937 }, |
| 4190 | { PseudoVFREDMAX_VS_M8_E16, 938 }, |
| 4191 | { PseudoVFREDMAX_VS_M8_E32, 939 }, |
| 4192 | { PseudoVFREDMAX_VS_M8_E64, 940 }, |
| 4193 | { PseudoVFREDMAX_VS_MF2_E16, 941 }, |
| 4194 | { PseudoVFREDMAX_VS_MF2_E32, 942 }, |
| 4195 | { PseudoVFREDMAX_VS_MF4_E16, 943 }, |
| 4196 | { PseudoVFREDMIN_VS_M1_E16, 944 }, |
| 4197 | { PseudoVFREDMIN_VS_M1_E32, 945 }, |
| 4198 | { PseudoVFREDMIN_VS_M1_E64, 946 }, |
| 4199 | { PseudoVFREDMIN_VS_M2_E16, 947 }, |
| 4200 | { PseudoVFREDMIN_VS_M2_E32, 948 }, |
| 4201 | { PseudoVFREDMIN_VS_M2_E64, 949 }, |
| 4202 | { PseudoVFREDMIN_VS_M4_E16, 950 }, |
| 4203 | { PseudoVFREDMIN_VS_M4_E32, 951 }, |
| 4204 | { PseudoVFREDMIN_VS_M4_E64, 952 }, |
| 4205 | { PseudoVFREDMIN_VS_M8_E16, 953 }, |
| 4206 | { PseudoVFREDMIN_VS_M8_E32, 954 }, |
| 4207 | { PseudoVFREDMIN_VS_M8_E64, 955 }, |
| 4208 | { PseudoVFREDMIN_VS_MF2_E16, 956 }, |
| 4209 | { PseudoVFREDMIN_VS_MF2_E32, 957 }, |
| 4210 | { PseudoVFREDMIN_VS_MF4_E16, 958 }, |
| 4211 | { PseudoVFREDOSUM_VS_M1_E16, 959 }, |
| 4212 | { PseudoVFREDOSUM_VS_M1_E32, 960 }, |
| 4213 | { PseudoVFREDOSUM_VS_M1_E64, 961 }, |
| 4214 | { PseudoVFREDOSUM_VS_M2_E16, 962 }, |
| 4215 | { PseudoVFREDOSUM_VS_M2_E32, 963 }, |
| 4216 | { PseudoVFREDOSUM_VS_M2_E64, 964 }, |
| 4217 | { PseudoVFREDOSUM_VS_M4_E16, 965 }, |
| 4218 | { PseudoVFREDOSUM_VS_M4_E32, 966 }, |
| 4219 | { PseudoVFREDOSUM_VS_M4_E64, 967 }, |
| 4220 | { PseudoVFREDOSUM_VS_M8_E16, 968 }, |
| 4221 | { PseudoVFREDOSUM_VS_M8_E32, 969 }, |
| 4222 | { PseudoVFREDOSUM_VS_M8_E64, 970 }, |
| 4223 | { PseudoVFREDOSUM_VS_MF2_E16, 971 }, |
| 4224 | { PseudoVFREDOSUM_VS_MF2_E32, 972 }, |
| 4225 | { PseudoVFREDOSUM_VS_MF4_E16, 973 }, |
| 4226 | { PseudoVFREDUSUM_VS_M1_E16, 974 }, |
| 4227 | { PseudoVFREDUSUM_VS_M1_E32, 975 }, |
| 4228 | { PseudoVFREDUSUM_VS_M1_E64, 976 }, |
| 4229 | { PseudoVFREDUSUM_VS_M2_E16, 977 }, |
| 4230 | { PseudoVFREDUSUM_VS_M2_E32, 978 }, |
| 4231 | { PseudoVFREDUSUM_VS_M2_E64, 979 }, |
| 4232 | { PseudoVFREDUSUM_VS_M4_E16, 980 }, |
| 4233 | { PseudoVFREDUSUM_VS_M4_E32, 981 }, |
| 4234 | { PseudoVFREDUSUM_VS_M4_E64, 982 }, |
| 4235 | { PseudoVFREDUSUM_VS_M8_E16, 983 }, |
| 4236 | { PseudoVFREDUSUM_VS_M8_E32, 984 }, |
| 4237 | { PseudoVFREDUSUM_VS_M8_E64, 985 }, |
| 4238 | { PseudoVFREDUSUM_VS_MF2_E16, 986 }, |
| 4239 | { PseudoVFREDUSUM_VS_MF2_E32, 987 }, |
| 4240 | { PseudoVFREDUSUM_VS_MF4_E16, 988 }, |
| 4241 | { PseudoVFRSQRT7_V_M1_E16, 989 }, |
| 4242 | { PseudoVFRSQRT7_V_M1_E32, 990 }, |
| 4243 | { PseudoVFRSQRT7_V_M1_E64, 991 }, |
| 4244 | { PseudoVFRSQRT7_V_M2_E16, 992 }, |
| 4245 | { PseudoVFRSQRT7_V_M2_E32, 993 }, |
| 4246 | { PseudoVFRSQRT7_V_M2_E64, 994 }, |
| 4247 | { PseudoVFRSQRT7_V_M4_E16, 995 }, |
| 4248 | { PseudoVFRSQRT7_V_M4_E32, 996 }, |
| 4249 | { PseudoVFRSQRT7_V_M4_E64, 997 }, |
| 4250 | { PseudoVFRSQRT7_V_M8_E16, 998 }, |
| 4251 | { PseudoVFRSQRT7_V_M8_E32, 999 }, |
| 4252 | { PseudoVFRSQRT7_V_M8_E64, 1000 }, |
| 4253 | { PseudoVFRSQRT7_V_MF2_E16, 1001 }, |
| 4254 | { PseudoVFRSQRT7_V_MF2_E32, 1002 }, |
| 4255 | { PseudoVFRSQRT7_V_MF4_E16, 1003 }, |
| 4256 | { PseudoVFRSUB_VFPR16_M1_E16, 1004 }, |
| 4257 | { PseudoVFRSUB_VFPR16_M2_E16, 1005 }, |
| 4258 | { PseudoVFRSUB_VFPR16_M4_E16, 1006 }, |
| 4259 | { PseudoVFRSUB_VFPR16_M8_E16, 1007 }, |
| 4260 | { PseudoVFRSUB_VFPR16_MF2_E16, 1008 }, |
| 4261 | { PseudoVFRSUB_VFPR16_MF4_E16, 1009 }, |
| 4262 | { PseudoVFRSUB_VFPR32_M1_E32, 1010 }, |
| 4263 | { PseudoVFRSUB_VFPR32_M2_E32, 1011 }, |
| 4264 | { PseudoVFRSUB_VFPR32_M4_E32, 1012 }, |
| 4265 | { PseudoVFRSUB_VFPR32_M8_E32, 1013 }, |
| 4266 | { PseudoVFRSUB_VFPR32_MF2_E32, 1014 }, |
| 4267 | { PseudoVFRSUB_VFPR64_M1_E64, 1015 }, |
| 4268 | { PseudoVFRSUB_VFPR64_M2_E64, 1016 }, |
| 4269 | { PseudoVFRSUB_VFPR64_M4_E64, 1017 }, |
| 4270 | { PseudoVFRSUB_VFPR64_M8_E64, 1018 }, |
| 4271 | { PseudoVFSGNJN_VFPR16_M1_E16, 1019 }, |
| 4272 | { PseudoVFSGNJN_VFPR16_M2_E16, 1020 }, |
| 4273 | { PseudoVFSGNJN_VFPR16_M4_E16, 1021 }, |
| 4274 | { PseudoVFSGNJN_VFPR16_M8_E16, 1022 }, |
| 4275 | { PseudoVFSGNJN_VFPR16_MF2_E16, 1023 }, |
| 4276 | { PseudoVFSGNJN_VFPR16_MF4_E16, 1024 }, |
| 4277 | { PseudoVFSGNJN_VFPR32_M1_E32, 1025 }, |
| 4278 | { PseudoVFSGNJN_VFPR32_M2_E32, 1026 }, |
| 4279 | { PseudoVFSGNJN_VFPR32_M4_E32, 1027 }, |
| 4280 | { PseudoVFSGNJN_VFPR32_M8_E32, 1028 }, |
| 4281 | { PseudoVFSGNJN_VFPR32_MF2_E32, 1029 }, |
| 4282 | { PseudoVFSGNJN_VFPR64_M1_E64, 1030 }, |
| 4283 | { PseudoVFSGNJN_VFPR64_M2_E64, 1031 }, |
| 4284 | { PseudoVFSGNJN_VFPR64_M4_E64, 1032 }, |
| 4285 | { PseudoVFSGNJN_VFPR64_M8_E64, 1033 }, |
| 4286 | { PseudoVFSGNJN_VV_M1_E16, 1034 }, |
| 4287 | { PseudoVFSGNJN_VV_M1_E32, 1035 }, |
| 4288 | { PseudoVFSGNJN_VV_M1_E64, 1036 }, |
| 4289 | { PseudoVFSGNJN_VV_M2_E16, 1037 }, |
| 4290 | { PseudoVFSGNJN_VV_M2_E32, 1038 }, |
| 4291 | { PseudoVFSGNJN_VV_M2_E64, 1039 }, |
| 4292 | { PseudoVFSGNJN_VV_M4_E16, 1040 }, |
| 4293 | { PseudoVFSGNJN_VV_M4_E32, 1041 }, |
| 4294 | { PseudoVFSGNJN_VV_M4_E64, 1042 }, |
| 4295 | { PseudoVFSGNJN_VV_M8_E16, 1043 }, |
| 4296 | { PseudoVFSGNJN_VV_M8_E32, 1044 }, |
| 4297 | { PseudoVFSGNJN_VV_M8_E64, 1045 }, |
| 4298 | { PseudoVFSGNJN_VV_MF2_E16, 1046 }, |
| 4299 | { PseudoVFSGNJN_VV_MF2_E32, 1047 }, |
| 4300 | { PseudoVFSGNJN_VV_MF4_E16, 1048 }, |
| 4301 | { PseudoVFSGNJX_VFPR16_M1_E16, 1049 }, |
| 4302 | { PseudoVFSGNJX_VFPR16_M2_E16, 1050 }, |
| 4303 | { PseudoVFSGNJX_VFPR16_M4_E16, 1051 }, |
| 4304 | { PseudoVFSGNJX_VFPR16_M8_E16, 1052 }, |
| 4305 | { PseudoVFSGNJX_VFPR16_MF2_E16, 1053 }, |
| 4306 | { PseudoVFSGNJX_VFPR16_MF4_E16, 1054 }, |
| 4307 | { PseudoVFSGNJX_VFPR32_M1_E32, 1055 }, |
| 4308 | { PseudoVFSGNJX_VFPR32_M2_E32, 1056 }, |
| 4309 | { PseudoVFSGNJX_VFPR32_M4_E32, 1057 }, |
| 4310 | { PseudoVFSGNJX_VFPR32_M8_E32, 1058 }, |
| 4311 | { PseudoVFSGNJX_VFPR32_MF2_E32, 1059 }, |
| 4312 | { PseudoVFSGNJX_VFPR64_M1_E64, 1060 }, |
| 4313 | { PseudoVFSGNJX_VFPR64_M2_E64, 1061 }, |
| 4314 | { PseudoVFSGNJX_VFPR64_M4_E64, 1062 }, |
| 4315 | { PseudoVFSGNJX_VFPR64_M8_E64, 1063 }, |
| 4316 | { PseudoVFSGNJX_VV_M1_E16, 1064 }, |
| 4317 | { PseudoVFSGNJX_VV_M1_E32, 1065 }, |
| 4318 | { PseudoVFSGNJX_VV_M1_E64, 1066 }, |
| 4319 | { PseudoVFSGNJX_VV_M2_E16, 1067 }, |
| 4320 | { PseudoVFSGNJX_VV_M2_E32, 1068 }, |
| 4321 | { PseudoVFSGNJX_VV_M2_E64, 1069 }, |
| 4322 | { PseudoVFSGNJX_VV_M4_E16, 1070 }, |
| 4323 | { PseudoVFSGNJX_VV_M4_E32, 1071 }, |
| 4324 | { PseudoVFSGNJX_VV_M4_E64, 1072 }, |
| 4325 | { PseudoVFSGNJX_VV_M8_E16, 1073 }, |
| 4326 | { PseudoVFSGNJX_VV_M8_E32, 1074 }, |
| 4327 | { PseudoVFSGNJX_VV_M8_E64, 1075 }, |
| 4328 | { PseudoVFSGNJX_VV_MF2_E16, 1076 }, |
| 4329 | { PseudoVFSGNJX_VV_MF2_E32, 1077 }, |
| 4330 | { PseudoVFSGNJX_VV_MF4_E16, 1078 }, |
| 4331 | { PseudoVFSGNJ_VFPR16_M1_E16, 1079 }, |
| 4332 | { PseudoVFSGNJ_VFPR16_M2_E16, 1080 }, |
| 4333 | { PseudoVFSGNJ_VFPR16_M4_E16, 1081 }, |
| 4334 | { PseudoVFSGNJ_VFPR16_M8_E16, 1082 }, |
| 4335 | { PseudoVFSGNJ_VFPR16_MF2_E16, 1083 }, |
| 4336 | { PseudoVFSGNJ_VFPR16_MF4_E16, 1084 }, |
| 4337 | { PseudoVFSGNJ_VFPR32_M1_E32, 1085 }, |
| 4338 | { PseudoVFSGNJ_VFPR32_M2_E32, 1086 }, |
| 4339 | { PseudoVFSGNJ_VFPR32_M4_E32, 1087 }, |
| 4340 | { PseudoVFSGNJ_VFPR32_M8_E32, 1088 }, |
| 4341 | { PseudoVFSGNJ_VFPR32_MF2_E32, 1089 }, |
| 4342 | { PseudoVFSGNJ_VFPR64_M1_E64, 1090 }, |
| 4343 | { PseudoVFSGNJ_VFPR64_M2_E64, 1091 }, |
| 4344 | { PseudoVFSGNJ_VFPR64_M4_E64, 1092 }, |
| 4345 | { PseudoVFSGNJ_VFPR64_M8_E64, 1093 }, |
| 4346 | { PseudoVFSGNJ_VV_M1_E16, 1094 }, |
| 4347 | { PseudoVFSGNJ_VV_M1_E32, 1095 }, |
| 4348 | { PseudoVFSGNJ_VV_M1_E64, 1096 }, |
| 4349 | { PseudoVFSGNJ_VV_M2_E16, 1097 }, |
| 4350 | { PseudoVFSGNJ_VV_M2_E32, 1098 }, |
| 4351 | { PseudoVFSGNJ_VV_M2_E64, 1099 }, |
| 4352 | { PseudoVFSGNJ_VV_M4_E16, 1100 }, |
| 4353 | { PseudoVFSGNJ_VV_M4_E32, 1101 }, |
| 4354 | { PseudoVFSGNJ_VV_M4_E64, 1102 }, |
| 4355 | { PseudoVFSGNJ_VV_M8_E16, 1103 }, |
| 4356 | { PseudoVFSGNJ_VV_M8_E32, 1104 }, |
| 4357 | { PseudoVFSGNJ_VV_M8_E64, 1105 }, |
| 4358 | { PseudoVFSGNJ_VV_MF2_E16, 1106 }, |
| 4359 | { PseudoVFSGNJ_VV_MF2_E32, 1107 }, |
| 4360 | { PseudoVFSGNJ_VV_MF4_E16, 1108 }, |
| 4361 | { PseudoVFSLIDE1DOWN_VFPR16_M1, 1109 }, |
| 4362 | { PseudoVFSLIDE1DOWN_VFPR16_M2, 1110 }, |
| 4363 | { PseudoVFSLIDE1DOWN_VFPR16_M4, 1111 }, |
| 4364 | { PseudoVFSLIDE1DOWN_VFPR16_M8, 1112 }, |
| 4365 | { PseudoVFSLIDE1DOWN_VFPR16_MF2, 1113 }, |
| 4366 | { PseudoVFSLIDE1DOWN_VFPR16_MF4, 1114 }, |
| 4367 | { PseudoVFSLIDE1DOWN_VFPR32_M1, 1115 }, |
| 4368 | { PseudoVFSLIDE1DOWN_VFPR32_M2, 1116 }, |
| 4369 | { PseudoVFSLIDE1DOWN_VFPR32_M4, 1117 }, |
| 4370 | { PseudoVFSLIDE1DOWN_VFPR32_M8, 1118 }, |
| 4371 | { PseudoVFSLIDE1DOWN_VFPR32_MF2, 1119 }, |
| 4372 | { PseudoVFSLIDE1DOWN_VFPR64_M1, 1120 }, |
| 4373 | { PseudoVFSLIDE1DOWN_VFPR64_M2, 1121 }, |
| 4374 | { PseudoVFSLIDE1DOWN_VFPR64_M4, 1122 }, |
| 4375 | { PseudoVFSLIDE1DOWN_VFPR64_M8, 1123 }, |
| 4376 | { PseudoVFSLIDE1UP_VFPR16_M1, 1124 }, |
| 4377 | { PseudoVFSLIDE1UP_VFPR16_M2, 1125 }, |
| 4378 | { PseudoVFSLIDE1UP_VFPR16_M4, 1126 }, |
| 4379 | { PseudoVFSLIDE1UP_VFPR16_M8, 1127 }, |
| 4380 | { PseudoVFSLIDE1UP_VFPR16_MF2, 1128 }, |
| 4381 | { PseudoVFSLIDE1UP_VFPR16_MF4, 1129 }, |
| 4382 | { PseudoVFSLIDE1UP_VFPR32_M1, 1130 }, |
| 4383 | { PseudoVFSLIDE1UP_VFPR32_M2, 1131 }, |
| 4384 | { PseudoVFSLIDE1UP_VFPR32_M4, 1132 }, |
| 4385 | { PseudoVFSLIDE1UP_VFPR32_M8, 1133 }, |
| 4386 | { PseudoVFSLIDE1UP_VFPR32_MF2, 1134 }, |
| 4387 | { PseudoVFSLIDE1UP_VFPR64_M1, 1135 }, |
| 4388 | { PseudoVFSLIDE1UP_VFPR64_M2, 1136 }, |
| 4389 | { PseudoVFSLIDE1UP_VFPR64_M4, 1137 }, |
| 4390 | { PseudoVFSLIDE1UP_VFPR64_M8, 1138 }, |
| 4391 | { PseudoVFSQRT_V_M1_E16, 1139 }, |
| 4392 | { PseudoVFSQRT_V_M1_E32, 1140 }, |
| 4393 | { PseudoVFSQRT_V_M1_E64, 1141 }, |
| 4394 | { PseudoVFSQRT_V_M2_E16, 1142 }, |
| 4395 | { PseudoVFSQRT_V_M2_E32, 1143 }, |
| 4396 | { PseudoVFSQRT_V_M2_E64, 1144 }, |
| 4397 | { PseudoVFSQRT_V_M4_E16, 1145 }, |
| 4398 | { PseudoVFSQRT_V_M4_E32, 1146 }, |
| 4399 | { PseudoVFSQRT_V_M4_E64, 1147 }, |
| 4400 | { PseudoVFSQRT_V_M8_E16, 1148 }, |
| 4401 | { PseudoVFSQRT_V_M8_E32, 1149 }, |
| 4402 | { PseudoVFSQRT_V_M8_E64, 1150 }, |
| 4403 | { PseudoVFSQRT_V_MF2_E16, 1151 }, |
| 4404 | { PseudoVFSQRT_V_MF2_E32, 1152 }, |
| 4405 | { PseudoVFSQRT_V_MF4_E16, 1153 }, |
| 4406 | { PseudoVFSUB_VFPR16_M1_E16, 1154 }, |
| 4407 | { PseudoVFSUB_VFPR16_M2_E16, 1155 }, |
| 4408 | { PseudoVFSUB_VFPR16_M4_E16, 1156 }, |
| 4409 | { PseudoVFSUB_VFPR16_M8_E16, 1157 }, |
| 4410 | { PseudoVFSUB_VFPR16_MF2_E16, 1158 }, |
| 4411 | { PseudoVFSUB_VFPR16_MF4_E16, 1159 }, |
| 4412 | { PseudoVFSUB_VFPR32_M1_E32, 1160 }, |
| 4413 | { PseudoVFSUB_VFPR32_M2_E32, 1161 }, |
| 4414 | { PseudoVFSUB_VFPR32_M4_E32, 1162 }, |
| 4415 | { PseudoVFSUB_VFPR32_M8_E32, 1163 }, |
| 4416 | { PseudoVFSUB_VFPR32_MF2_E32, 1164 }, |
| 4417 | { PseudoVFSUB_VFPR64_M1_E64, 1165 }, |
| 4418 | { PseudoVFSUB_VFPR64_M2_E64, 1166 }, |
| 4419 | { PseudoVFSUB_VFPR64_M4_E64, 1167 }, |
| 4420 | { PseudoVFSUB_VFPR64_M8_E64, 1168 }, |
| 4421 | { PseudoVFSUB_VV_M1_E16, 1169 }, |
| 4422 | { PseudoVFSUB_VV_M1_E32, 1170 }, |
| 4423 | { PseudoVFSUB_VV_M1_E64, 1171 }, |
| 4424 | { PseudoVFSUB_VV_M2_E16, 1172 }, |
| 4425 | { PseudoVFSUB_VV_M2_E32, 1173 }, |
| 4426 | { PseudoVFSUB_VV_M2_E64, 1174 }, |
| 4427 | { PseudoVFSUB_VV_M4_E16, 1175 }, |
| 4428 | { PseudoVFSUB_VV_M4_E32, 1176 }, |
| 4429 | { PseudoVFSUB_VV_M4_E64, 1177 }, |
| 4430 | { PseudoVFSUB_VV_M8_E16, 1178 }, |
| 4431 | { PseudoVFSUB_VV_M8_E32, 1179 }, |
| 4432 | { PseudoVFSUB_VV_M8_E64, 1180 }, |
| 4433 | { PseudoVFSUB_VV_MF2_E16, 1181 }, |
| 4434 | { PseudoVFSUB_VV_MF2_E32, 1182 }, |
| 4435 | { PseudoVFSUB_VV_MF4_E16, 1183 }, |
| 4436 | { PseudoVFWADD_VFPR16_M1_E16, 1184 }, |
| 4437 | { PseudoVFWADD_VFPR16_M2_E16, 1185 }, |
| 4438 | { PseudoVFWADD_VFPR16_M4_E16, 1186 }, |
| 4439 | { PseudoVFWADD_VFPR16_MF2_E16, 1187 }, |
| 4440 | { PseudoVFWADD_VFPR16_MF4_E16, 1188 }, |
| 4441 | { PseudoVFWADD_VFPR32_M1_E32, 1189 }, |
| 4442 | { PseudoVFWADD_VFPR32_M2_E32, 1190 }, |
| 4443 | { PseudoVFWADD_VFPR32_M4_E32, 1191 }, |
| 4444 | { PseudoVFWADD_VFPR32_MF2_E32, 1192 }, |
| 4445 | { PseudoVFWADD_VV_M1_E16, 1193 }, |
| 4446 | { PseudoVFWADD_VV_M1_E32, 1194 }, |
| 4447 | { PseudoVFWADD_VV_M2_E16, 1195 }, |
| 4448 | { PseudoVFWADD_VV_M2_E32, 1196 }, |
| 4449 | { PseudoVFWADD_VV_M4_E16, 1197 }, |
| 4450 | { PseudoVFWADD_VV_M4_E32, 1198 }, |
| 4451 | { PseudoVFWADD_VV_MF2_E16, 1199 }, |
| 4452 | { PseudoVFWADD_VV_MF2_E32, 1200 }, |
| 4453 | { PseudoVFWADD_VV_MF4_E16, 1201 }, |
| 4454 | { PseudoVFWADD_WFPR16_M1_E16, 1202 }, |
| 4455 | { PseudoVFWADD_WFPR16_M2_E16, 1203 }, |
| 4456 | { PseudoVFWADD_WFPR16_M4_E16, 1204 }, |
| 4457 | { PseudoVFWADD_WFPR16_MF2_E16, 1205 }, |
| 4458 | { PseudoVFWADD_WFPR16_MF4_E16, 1206 }, |
| 4459 | { PseudoVFWADD_WFPR32_M1_E32, 1207 }, |
| 4460 | { PseudoVFWADD_WFPR32_M2_E32, 1208 }, |
| 4461 | { PseudoVFWADD_WFPR32_M4_E32, 1209 }, |
| 4462 | { PseudoVFWADD_WFPR32_MF2_E32, 1210 }, |
| 4463 | { PseudoVFWADD_WV_M1_E16, 1211 }, |
| 4464 | { PseudoVFWADD_WV_M1_E16_TIED, 1212 }, |
| 4465 | { PseudoVFWADD_WV_M1_E32, 1213 }, |
| 4466 | { PseudoVFWADD_WV_M1_E32_TIED, 1214 }, |
| 4467 | { PseudoVFWADD_WV_M2_E16, 1215 }, |
| 4468 | { PseudoVFWADD_WV_M2_E16_TIED, 1216 }, |
| 4469 | { PseudoVFWADD_WV_M2_E32, 1217 }, |
| 4470 | { PseudoVFWADD_WV_M2_E32_TIED, 1218 }, |
| 4471 | { PseudoVFWADD_WV_M4_E16, 1219 }, |
| 4472 | { PseudoVFWADD_WV_M4_E16_TIED, 1220 }, |
| 4473 | { PseudoVFWADD_WV_M4_E32, 1221 }, |
| 4474 | { PseudoVFWADD_WV_M4_E32_TIED, 1222 }, |
| 4475 | { PseudoVFWADD_WV_MF2_E16, 1223 }, |
| 4476 | { PseudoVFWADD_WV_MF2_E16_TIED, 1224 }, |
| 4477 | { PseudoVFWADD_WV_MF2_E32, 1225 }, |
| 4478 | { PseudoVFWADD_WV_MF2_E32_TIED, 1226 }, |
| 4479 | { PseudoVFWADD_WV_MF4_E16, 1227 }, |
| 4480 | { PseudoVFWADD_WV_MF4_E16_TIED, 1228 }, |
| 4481 | { PseudoVFWCVTBF16_F_F_V_M1_E16, 1229 }, |
| 4482 | { PseudoVFWCVTBF16_F_F_V_M1_E32, 1230 }, |
| 4483 | { PseudoVFWCVTBF16_F_F_V_M2_E16, 1231 }, |
| 4484 | { PseudoVFWCVTBF16_F_F_V_M2_E32, 1232 }, |
| 4485 | { PseudoVFWCVTBF16_F_F_V_M4_E16, 1233 }, |
| 4486 | { PseudoVFWCVTBF16_F_F_V_M4_E32, 1234 }, |
| 4487 | { PseudoVFWCVTBF16_F_F_V_MF2_E16, 1235 }, |
| 4488 | { PseudoVFWCVTBF16_F_F_V_MF2_E32, 1236 }, |
| 4489 | { PseudoVFWCVTBF16_F_F_V_MF4_E16, 1237 }, |
| 4490 | { PseudoVFWCVT_F_F_V_M1_E16, 1238 }, |
| 4491 | { PseudoVFWCVT_F_F_V_M1_E32, 1239 }, |
| 4492 | { PseudoVFWCVT_F_F_V_M2_E16, 1240 }, |
| 4493 | { PseudoVFWCVT_F_F_V_M2_E32, 1241 }, |
| 4494 | { PseudoVFWCVT_F_F_V_M4_E16, 1242 }, |
| 4495 | { PseudoVFWCVT_F_F_V_M4_E32, 1243 }, |
| 4496 | { PseudoVFWCVT_F_F_V_MF2_E16, 1244 }, |
| 4497 | { PseudoVFWCVT_F_F_V_MF2_E32, 1245 }, |
| 4498 | { PseudoVFWCVT_F_F_V_MF4_E16, 1246 }, |
| 4499 | { PseudoVFWCVT_F_XU_V_M1_E16, 1247 }, |
| 4500 | { PseudoVFWCVT_F_XU_V_M1_E32, 1248 }, |
| 4501 | { PseudoVFWCVT_F_XU_V_M1_E8, 1249 }, |
| 4502 | { PseudoVFWCVT_F_XU_V_M2_E16, 1250 }, |
| 4503 | { PseudoVFWCVT_F_XU_V_M2_E32, 1251 }, |
| 4504 | { PseudoVFWCVT_F_XU_V_M2_E8, 1252 }, |
| 4505 | { PseudoVFWCVT_F_XU_V_M4_E16, 1253 }, |
| 4506 | { PseudoVFWCVT_F_XU_V_M4_E32, 1254 }, |
| 4507 | { PseudoVFWCVT_F_XU_V_M4_E8, 1255 }, |
| 4508 | { PseudoVFWCVT_F_XU_V_MF2_E16, 1256 }, |
| 4509 | { PseudoVFWCVT_F_XU_V_MF2_E32, 1257 }, |
| 4510 | { PseudoVFWCVT_F_XU_V_MF2_E8, 1258 }, |
| 4511 | { PseudoVFWCVT_F_XU_V_MF4_E16, 1259 }, |
| 4512 | { PseudoVFWCVT_F_XU_V_MF4_E8, 1260 }, |
| 4513 | { PseudoVFWCVT_F_XU_V_MF8_E8, 1261 }, |
| 4514 | { PseudoVFWCVT_F_X_V_M1_E16, 1262 }, |
| 4515 | { PseudoVFWCVT_F_X_V_M1_E32, 1263 }, |
| 4516 | { PseudoVFWCVT_F_X_V_M1_E8, 1264 }, |
| 4517 | { PseudoVFWCVT_F_X_V_M2_E16, 1265 }, |
| 4518 | { PseudoVFWCVT_F_X_V_M2_E32, 1266 }, |
| 4519 | { PseudoVFWCVT_F_X_V_M2_E8, 1267 }, |
| 4520 | { PseudoVFWCVT_F_X_V_M4_E16, 1268 }, |
| 4521 | { PseudoVFWCVT_F_X_V_M4_E32, 1269 }, |
| 4522 | { PseudoVFWCVT_F_X_V_M4_E8, 1270 }, |
| 4523 | { PseudoVFWCVT_F_X_V_MF2_E16, 1271 }, |
| 4524 | { PseudoVFWCVT_F_X_V_MF2_E32, 1272 }, |
| 4525 | { PseudoVFWCVT_F_X_V_MF2_E8, 1273 }, |
| 4526 | { PseudoVFWCVT_F_X_V_MF4_E16, 1274 }, |
| 4527 | { PseudoVFWCVT_F_X_V_MF4_E8, 1275 }, |
| 4528 | { PseudoVFWCVT_F_X_V_MF8_E8, 1276 }, |
| 4529 | { PseudoVFWCVT_RM_XU_F_V_M1, 1277 }, |
| 4530 | { PseudoVFWCVT_RM_XU_F_V_M2, 1278 }, |
| 4531 | { PseudoVFWCVT_RM_XU_F_V_M4, 1279 }, |
| 4532 | { PseudoVFWCVT_RM_XU_F_V_MF2, 1280 }, |
| 4533 | { PseudoVFWCVT_RM_XU_F_V_MF4, 1281 }, |
| 4534 | { PseudoVFWCVT_RM_X_F_V_M1, 1282 }, |
| 4535 | { PseudoVFWCVT_RM_X_F_V_M2, 1283 }, |
| 4536 | { PseudoVFWCVT_RM_X_F_V_M4, 1284 }, |
| 4537 | { PseudoVFWCVT_RM_X_F_V_MF2, 1285 }, |
| 4538 | { PseudoVFWCVT_RM_X_F_V_MF4, 1286 }, |
| 4539 | { PseudoVFWCVT_RTZ_XU_F_V_M1, 1287 }, |
| 4540 | { PseudoVFWCVT_RTZ_XU_F_V_M2, 1288 }, |
| 4541 | { PseudoVFWCVT_RTZ_XU_F_V_M4, 1289 }, |
| 4542 | { PseudoVFWCVT_RTZ_XU_F_V_MF2, 1290 }, |
| 4543 | { PseudoVFWCVT_RTZ_XU_F_V_MF4, 1291 }, |
| 4544 | { PseudoVFWCVT_RTZ_X_F_V_M1, 1292 }, |
| 4545 | { PseudoVFWCVT_RTZ_X_F_V_M2, 1293 }, |
| 4546 | { PseudoVFWCVT_RTZ_X_F_V_M4, 1294 }, |
| 4547 | { PseudoVFWCVT_RTZ_X_F_V_MF2, 1295 }, |
| 4548 | { PseudoVFWCVT_RTZ_X_F_V_MF4, 1296 }, |
| 4549 | { PseudoVFWCVT_XU_F_V_M1, 1297 }, |
| 4550 | { PseudoVFWCVT_XU_F_V_M2, 1298 }, |
| 4551 | { PseudoVFWCVT_XU_F_V_M4, 1299 }, |
| 4552 | { PseudoVFWCVT_XU_F_V_MF2, 1300 }, |
| 4553 | { PseudoVFWCVT_XU_F_V_MF4, 1301 }, |
| 4554 | { PseudoVFWCVT_X_F_V_M1, 1302 }, |
| 4555 | { PseudoVFWCVT_X_F_V_M2, 1303 }, |
| 4556 | { PseudoVFWCVT_X_F_V_M4, 1304 }, |
| 4557 | { PseudoVFWCVT_X_F_V_MF2, 1305 }, |
| 4558 | { PseudoVFWCVT_X_F_V_MF4, 1306 }, |
| 4559 | { PseudoVFWMACCBF16_VFPR16_M1_E16, 1307 }, |
| 4560 | { PseudoVFWMACCBF16_VFPR16_M2_E16, 1308 }, |
| 4561 | { PseudoVFWMACCBF16_VFPR16_M4_E16, 1309 }, |
| 4562 | { PseudoVFWMACCBF16_VFPR16_MF2_E16, 1310 }, |
| 4563 | { PseudoVFWMACCBF16_VFPR16_MF4_E16, 1311 }, |
| 4564 | { PseudoVFWMACCBF16_VV_M1_E16, 1312 }, |
| 4565 | { PseudoVFWMACCBF16_VV_M1_E32, 1313 }, |
| 4566 | { PseudoVFWMACCBF16_VV_M2_E16, 1314 }, |
| 4567 | { PseudoVFWMACCBF16_VV_M2_E32, 1315 }, |
| 4568 | { PseudoVFWMACCBF16_VV_M4_E16, 1316 }, |
| 4569 | { PseudoVFWMACCBF16_VV_M4_E32, 1317 }, |
| 4570 | { PseudoVFWMACCBF16_VV_MF2_E16, 1318 }, |
| 4571 | { PseudoVFWMACCBF16_VV_MF2_E32, 1319 }, |
| 4572 | { PseudoVFWMACCBF16_VV_MF4_E16, 1320 }, |
| 4573 | { PseudoVFWMACC_VFPR16_M1_E16, 1321 }, |
| 4574 | { PseudoVFWMACC_VFPR16_M2_E16, 1322 }, |
| 4575 | { PseudoVFWMACC_VFPR16_M4_E16, 1323 }, |
| 4576 | { PseudoVFWMACC_VFPR16_MF2_E16, 1324 }, |
| 4577 | { PseudoVFWMACC_VFPR16_MF4_E16, 1325 }, |
| 4578 | { PseudoVFWMACC_VFPR32_M1_E32, 1326 }, |
| 4579 | { PseudoVFWMACC_VFPR32_M2_E32, 1327 }, |
| 4580 | { PseudoVFWMACC_VFPR32_M4_E32, 1328 }, |
| 4581 | { PseudoVFWMACC_VFPR32_MF2_E32, 1329 }, |
| 4582 | { PseudoVFWMACC_VV_M1_E16, 1330 }, |
| 4583 | { PseudoVFWMACC_VV_M1_E32, 1331 }, |
| 4584 | { PseudoVFWMACC_VV_M2_E16, 1332 }, |
| 4585 | { PseudoVFWMACC_VV_M2_E32, 1333 }, |
| 4586 | { PseudoVFWMACC_VV_M4_E16, 1334 }, |
| 4587 | { PseudoVFWMACC_VV_M4_E32, 1335 }, |
| 4588 | { PseudoVFWMACC_VV_MF2_E16, 1336 }, |
| 4589 | { PseudoVFWMACC_VV_MF2_E32, 1337 }, |
| 4590 | { PseudoVFWMACC_VV_MF4_E16, 1338 }, |
| 4591 | { PseudoVFWMSAC_VFPR16_M1_E16, 1339 }, |
| 4592 | { PseudoVFWMSAC_VFPR16_M2_E16, 1340 }, |
| 4593 | { PseudoVFWMSAC_VFPR16_M4_E16, 1341 }, |
| 4594 | { PseudoVFWMSAC_VFPR16_MF2_E16, 1342 }, |
| 4595 | { PseudoVFWMSAC_VFPR16_MF4_E16, 1343 }, |
| 4596 | { PseudoVFWMSAC_VFPR32_M1_E32, 1344 }, |
| 4597 | { PseudoVFWMSAC_VFPR32_M2_E32, 1345 }, |
| 4598 | { PseudoVFWMSAC_VFPR32_M4_E32, 1346 }, |
| 4599 | { PseudoVFWMSAC_VFPR32_MF2_E32, 1347 }, |
| 4600 | { PseudoVFWMSAC_VV_M1_E16, 1348 }, |
| 4601 | { PseudoVFWMSAC_VV_M1_E32, 1349 }, |
| 4602 | { PseudoVFWMSAC_VV_M2_E16, 1350 }, |
| 4603 | { PseudoVFWMSAC_VV_M2_E32, 1351 }, |
| 4604 | { PseudoVFWMSAC_VV_M4_E16, 1352 }, |
| 4605 | { PseudoVFWMSAC_VV_M4_E32, 1353 }, |
| 4606 | { PseudoVFWMSAC_VV_MF2_E16, 1354 }, |
| 4607 | { PseudoVFWMSAC_VV_MF2_E32, 1355 }, |
| 4608 | { PseudoVFWMSAC_VV_MF4_E16, 1356 }, |
| 4609 | { PseudoVFWMUL_VFPR16_M1_E16, 1357 }, |
| 4610 | { PseudoVFWMUL_VFPR16_M2_E16, 1358 }, |
| 4611 | { PseudoVFWMUL_VFPR16_M4_E16, 1359 }, |
| 4612 | { PseudoVFWMUL_VFPR16_MF2_E16, 1360 }, |
| 4613 | { PseudoVFWMUL_VFPR16_MF4_E16, 1361 }, |
| 4614 | { PseudoVFWMUL_VFPR32_M1_E32, 1362 }, |
| 4615 | { PseudoVFWMUL_VFPR32_M2_E32, 1363 }, |
| 4616 | { PseudoVFWMUL_VFPR32_M4_E32, 1364 }, |
| 4617 | { PseudoVFWMUL_VFPR32_MF2_E32, 1365 }, |
| 4618 | { PseudoVFWMUL_VV_M1_E16, 1366 }, |
| 4619 | { PseudoVFWMUL_VV_M1_E32, 1367 }, |
| 4620 | { PseudoVFWMUL_VV_M2_E16, 1368 }, |
| 4621 | { PseudoVFWMUL_VV_M2_E32, 1369 }, |
| 4622 | { PseudoVFWMUL_VV_M4_E16, 1370 }, |
| 4623 | { PseudoVFWMUL_VV_M4_E32, 1371 }, |
| 4624 | { PseudoVFWMUL_VV_MF2_E16, 1372 }, |
| 4625 | { PseudoVFWMUL_VV_MF2_E32, 1373 }, |
| 4626 | { PseudoVFWMUL_VV_MF4_E16, 1374 }, |
| 4627 | { PseudoVFWNMACC_VFPR16_M1_E16, 1375 }, |
| 4628 | { PseudoVFWNMACC_VFPR16_M2_E16, 1376 }, |
| 4629 | { PseudoVFWNMACC_VFPR16_M4_E16, 1377 }, |
| 4630 | { PseudoVFWNMACC_VFPR16_MF2_E16, 1378 }, |
| 4631 | { PseudoVFWNMACC_VFPR16_MF4_E16, 1379 }, |
| 4632 | { PseudoVFWNMACC_VFPR32_M1_E32, 1380 }, |
| 4633 | { PseudoVFWNMACC_VFPR32_M2_E32, 1381 }, |
| 4634 | { PseudoVFWNMACC_VFPR32_M4_E32, 1382 }, |
| 4635 | { PseudoVFWNMACC_VFPR32_MF2_E32, 1383 }, |
| 4636 | { PseudoVFWNMACC_VV_M1_E16, 1384 }, |
| 4637 | { PseudoVFWNMACC_VV_M1_E32, 1385 }, |
| 4638 | { PseudoVFWNMACC_VV_M2_E16, 1386 }, |
| 4639 | { PseudoVFWNMACC_VV_M2_E32, 1387 }, |
| 4640 | { PseudoVFWNMACC_VV_M4_E16, 1388 }, |
| 4641 | { PseudoVFWNMACC_VV_M4_E32, 1389 }, |
| 4642 | { PseudoVFWNMACC_VV_MF2_E16, 1390 }, |
| 4643 | { PseudoVFWNMACC_VV_MF2_E32, 1391 }, |
| 4644 | { PseudoVFWNMACC_VV_MF4_E16, 1392 }, |
| 4645 | { PseudoVFWNMSAC_VFPR16_M1_E16, 1393 }, |
| 4646 | { PseudoVFWNMSAC_VFPR16_M2_E16, 1394 }, |
| 4647 | { PseudoVFWNMSAC_VFPR16_M4_E16, 1395 }, |
| 4648 | { PseudoVFWNMSAC_VFPR16_MF2_E16, 1396 }, |
| 4649 | { PseudoVFWNMSAC_VFPR16_MF4_E16, 1397 }, |
| 4650 | { PseudoVFWNMSAC_VFPR32_M1_E32, 1398 }, |
| 4651 | { PseudoVFWNMSAC_VFPR32_M2_E32, 1399 }, |
| 4652 | { PseudoVFWNMSAC_VFPR32_M4_E32, 1400 }, |
| 4653 | { PseudoVFWNMSAC_VFPR32_MF2_E32, 1401 }, |
| 4654 | { PseudoVFWNMSAC_VV_M1_E16, 1402 }, |
| 4655 | { PseudoVFWNMSAC_VV_M1_E32, 1403 }, |
| 4656 | { PseudoVFWNMSAC_VV_M2_E16, 1404 }, |
| 4657 | { PseudoVFWNMSAC_VV_M2_E32, 1405 }, |
| 4658 | { PseudoVFWNMSAC_VV_M4_E16, 1406 }, |
| 4659 | { PseudoVFWNMSAC_VV_M4_E32, 1407 }, |
| 4660 | { PseudoVFWNMSAC_VV_MF2_E16, 1408 }, |
| 4661 | { PseudoVFWNMSAC_VV_MF2_E32, 1409 }, |
| 4662 | { PseudoVFWNMSAC_VV_MF4_E16, 1410 }, |
| 4663 | { PseudoVFWREDOSUM_VS_M1_E16, 1411 }, |
| 4664 | { PseudoVFWREDOSUM_VS_M1_E32, 1412 }, |
| 4665 | { PseudoVFWREDOSUM_VS_M2_E16, 1413 }, |
| 4666 | { PseudoVFWREDOSUM_VS_M2_E32, 1414 }, |
| 4667 | { PseudoVFWREDOSUM_VS_M4_E16, 1415 }, |
| 4668 | { PseudoVFWREDOSUM_VS_M4_E32, 1416 }, |
| 4669 | { PseudoVFWREDOSUM_VS_M8_E16, 1417 }, |
| 4670 | { PseudoVFWREDOSUM_VS_M8_E32, 1418 }, |
| 4671 | { PseudoVFWREDOSUM_VS_MF2_E16, 1419 }, |
| 4672 | { PseudoVFWREDOSUM_VS_MF2_E32, 1420 }, |
| 4673 | { PseudoVFWREDOSUM_VS_MF4_E16, 1421 }, |
| 4674 | { PseudoVFWREDUSUM_VS_M1_E16, 1422 }, |
| 4675 | { PseudoVFWREDUSUM_VS_M1_E32, 1423 }, |
| 4676 | { PseudoVFWREDUSUM_VS_M2_E16, 1424 }, |
| 4677 | { PseudoVFWREDUSUM_VS_M2_E32, 1425 }, |
| 4678 | { PseudoVFWREDUSUM_VS_M4_E16, 1426 }, |
| 4679 | { PseudoVFWREDUSUM_VS_M4_E32, 1427 }, |
| 4680 | { PseudoVFWREDUSUM_VS_M8_E16, 1428 }, |
| 4681 | { PseudoVFWREDUSUM_VS_M8_E32, 1429 }, |
| 4682 | { PseudoVFWREDUSUM_VS_MF2_E16, 1430 }, |
| 4683 | { PseudoVFWREDUSUM_VS_MF2_E32, 1431 }, |
| 4684 | { PseudoVFWREDUSUM_VS_MF4_E16, 1432 }, |
| 4685 | { PseudoVFWSUB_VFPR16_M1_E16, 1433 }, |
| 4686 | { PseudoVFWSUB_VFPR16_M2_E16, 1434 }, |
| 4687 | { PseudoVFWSUB_VFPR16_M4_E16, 1435 }, |
| 4688 | { PseudoVFWSUB_VFPR16_MF2_E16, 1436 }, |
| 4689 | { PseudoVFWSUB_VFPR16_MF4_E16, 1437 }, |
| 4690 | { PseudoVFWSUB_VFPR32_M1_E32, 1438 }, |
| 4691 | { PseudoVFWSUB_VFPR32_M2_E32, 1439 }, |
| 4692 | { PseudoVFWSUB_VFPR32_M4_E32, 1440 }, |
| 4693 | { PseudoVFWSUB_VFPR32_MF2_E32, 1441 }, |
| 4694 | { PseudoVFWSUB_VV_M1_E16, 1442 }, |
| 4695 | { PseudoVFWSUB_VV_M1_E32, 1443 }, |
| 4696 | { PseudoVFWSUB_VV_M2_E16, 1444 }, |
| 4697 | { PseudoVFWSUB_VV_M2_E32, 1445 }, |
| 4698 | { PseudoVFWSUB_VV_M4_E16, 1446 }, |
| 4699 | { PseudoVFWSUB_VV_M4_E32, 1447 }, |
| 4700 | { PseudoVFWSUB_VV_MF2_E16, 1448 }, |
| 4701 | { PseudoVFWSUB_VV_MF2_E32, 1449 }, |
| 4702 | { PseudoVFWSUB_VV_MF4_E16, 1450 }, |
| 4703 | { PseudoVFWSUB_WFPR16_M1_E16, 1451 }, |
| 4704 | { PseudoVFWSUB_WFPR16_M2_E16, 1452 }, |
| 4705 | { PseudoVFWSUB_WFPR16_M4_E16, 1453 }, |
| 4706 | { PseudoVFWSUB_WFPR16_MF2_E16, 1454 }, |
| 4707 | { PseudoVFWSUB_WFPR16_MF4_E16, 1455 }, |
| 4708 | { PseudoVFWSUB_WFPR32_M1_E32, 1456 }, |
| 4709 | { PseudoVFWSUB_WFPR32_M2_E32, 1457 }, |
| 4710 | { PseudoVFWSUB_WFPR32_M4_E32, 1458 }, |
| 4711 | { PseudoVFWSUB_WFPR32_MF2_E32, 1459 }, |
| 4712 | { PseudoVFWSUB_WV_M1_E16, 1460 }, |
| 4713 | { PseudoVFWSUB_WV_M1_E16_TIED, 1461 }, |
| 4714 | { PseudoVFWSUB_WV_M1_E32, 1462 }, |
| 4715 | { PseudoVFWSUB_WV_M1_E32_TIED, 1463 }, |
| 4716 | { PseudoVFWSUB_WV_M2_E16, 1464 }, |
| 4717 | { PseudoVFWSUB_WV_M2_E16_TIED, 1465 }, |
| 4718 | { PseudoVFWSUB_WV_M2_E32, 1466 }, |
| 4719 | { PseudoVFWSUB_WV_M2_E32_TIED, 1467 }, |
| 4720 | { PseudoVFWSUB_WV_M4_E16, 1468 }, |
| 4721 | { PseudoVFWSUB_WV_M4_E16_TIED, 1469 }, |
| 4722 | { PseudoVFWSUB_WV_M4_E32, 1470 }, |
| 4723 | { PseudoVFWSUB_WV_M4_E32_TIED, 1471 }, |
| 4724 | { PseudoVFWSUB_WV_MF2_E16, 1472 }, |
| 4725 | { PseudoVFWSUB_WV_MF2_E16_TIED, 1473 }, |
| 4726 | { PseudoVFWSUB_WV_MF2_E32, 1474 }, |
| 4727 | { PseudoVFWSUB_WV_MF2_E32_TIED, 1475 }, |
| 4728 | { PseudoVFWSUB_WV_MF4_E16, 1476 }, |
| 4729 | { PseudoVFWSUB_WV_MF4_E16_TIED, 1477 }, |
| 4730 | { PseudoVID_V_M1, 1478 }, |
| 4731 | { PseudoVID_V_M2, 1479 }, |
| 4732 | { PseudoVID_V_M4, 1480 }, |
| 4733 | { PseudoVID_V_M8, 1481 }, |
| 4734 | { PseudoVID_V_MF2, 1482 }, |
| 4735 | { PseudoVID_V_MF4, 1483 }, |
| 4736 | { PseudoVID_V_MF8, 1484 }, |
| 4737 | { PseudoVIOTA_M_M1, 1485 }, |
| 4738 | { PseudoVIOTA_M_M2, 1486 }, |
| 4739 | { PseudoVIOTA_M_M4, 1487 }, |
| 4740 | { PseudoVIOTA_M_M8, 1488 }, |
| 4741 | { PseudoVIOTA_M_MF2, 1489 }, |
| 4742 | { PseudoVIOTA_M_MF4, 1490 }, |
| 4743 | { PseudoVIOTA_M_MF8, 1491 }, |
| 4744 | { PseudoVLE16FF_V_M1, 1492 }, |
| 4745 | { PseudoVLE16FF_V_M2, 1493 }, |
| 4746 | { PseudoVLE16FF_V_M4, 1494 }, |
| 4747 | { PseudoVLE16FF_V_M8, 1495 }, |
| 4748 | { PseudoVLE16FF_V_MF2, 1496 }, |
| 4749 | { PseudoVLE16FF_V_MF4, 1497 }, |
| 4750 | { PseudoVLE16_V_M1, 1498 }, |
| 4751 | { PseudoVLE16_V_M2, 1499 }, |
| 4752 | { PseudoVLE16_V_M4, 1500 }, |
| 4753 | { PseudoVLE16_V_M8, 1501 }, |
| 4754 | { PseudoVLE16_V_MF2, 1502 }, |
| 4755 | { PseudoVLE16_V_MF4, 1503 }, |
| 4756 | { PseudoVLE32FF_V_M1, 1504 }, |
| 4757 | { PseudoVLE32FF_V_M2, 1505 }, |
| 4758 | { PseudoVLE32FF_V_M4, 1506 }, |
| 4759 | { PseudoVLE32FF_V_M8, 1507 }, |
| 4760 | { PseudoVLE32FF_V_MF2, 1508 }, |
| 4761 | { PseudoVLE32_V_M1, 1509 }, |
| 4762 | { PseudoVLE32_V_M2, 1510 }, |
| 4763 | { PseudoVLE32_V_M4, 1511 }, |
| 4764 | { PseudoVLE32_V_M8, 1512 }, |
| 4765 | { PseudoVLE32_V_MF2, 1513 }, |
| 4766 | { PseudoVLE64FF_V_M1, 1514 }, |
| 4767 | { PseudoVLE64FF_V_M2, 1515 }, |
| 4768 | { PseudoVLE64FF_V_M4, 1516 }, |
| 4769 | { PseudoVLE64FF_V_M8, 1517 }, |
| 4770 | { PseudoVLE64_V_M1, 1518 }, |
| 4771 | { PseudoVLE64_V_M2, 1519 }, |
| 4772 | { PseudoVLE64_V_M4, 1520 }, |
| 4773 | { PseudoVLE64_V_M8, 1521 }, |
| 4774 | { PseudoVLE8FF_V_M1, 1522 }, |
| 4775 | { PseudoVLE8FF_V_M2, 1523 }, |
| 4776 | { PseudoVLE8FF_V_M4, 1524 }, |
| 4777 | { PseudoVLE8FF_V_M8, 1525 }, |
| 4778 | { PseudoVLE8FF_V_MF2, 1526 }, |
| 4779 | { PseudoVLE8FF_V_MF4, 1527 }, |
| 4780 | { PseudoVLE8FF_V_MF8, 1528 }, |
| 4781 | { PseudoVLE8_V_M1, 1529 }, |
| 4782 | { PseudoVLE8_V_M2, 1530 }, |
| 4783 | { PseudoVLE8_V_M4, 1531 }, |
| 4784 | { PseudoVLE8_V_M8, 1532 }, |
| 4785 | { PseudoVLE8_V_MF2, 1533 }, |
| 4786 | { PseudoVLE8_V_MF4, 1534 }, |
| 4787 | { PseudoVLE8_V_MF8, 1535 }, |
| 4788 | { PseudoVLOXEI16_V_M1_M1, 1536 }, |
| 4789 | { PseudoVLOXEI16_V_M1_M2, 1537 }, |
| 4790 | { PseudoVLOXEI16_V_M1_M4, 1538 }, |
| 4791 | { PseudoVLOXEI16_V_M1_MF2, 1539 }, |
| 4792 | { PseudoVLOXEI16_V_M2_M1, 1540 }, |
| 4793 | { PseudoVLOXEI16_V_M2_M2, 1541 }, |
| 4794 | { PseudoVLOXEI16_V_M2_M4, 1542 }, |
| 4795 | { PseudoVLOXEI16_V_M2_M8, 1543 }, |
| 4796 | { PseudoVLOXEI16_V_M4_M2, 1544 }, |
| 4797 | { PseudoVLOXEI16_V_M4_M4, 1545 }, |
| 4798 | { PseudoVLOXEI16_V_M4_M8, 1546 }, |
| 4799 | { PseudoVLOXEI16_V_M8_M4, 1547 }, |
| 4800 | { PseudoVLOXEI16_V_M8_M8, 1548 }, |
| 4801 | { PseudoVLOXEI16_V_MF2_M1, 1549 }, |
| 4802 | { PseudoVLOXEI16_V_MF2_M2, 1550 }, |
| 4803 | { PseudoVLOXEI16_V_MF2_MF2, 1551 }, |
| 4804 | { PseudoVLOXEI16_V_MF2_MF4, 1552 }, |
| 4805 | { PseudoVLOXEI16_V_MF4_M1, 1553 }, |
| 4806 | { PseudoVLOXEI16_V_MF4_MF2, 1554 }, |
| 4807 | { PseudoVLOXEI16_V_MF4_MF4, 1555 }, |
| 4808 | { PseudoVLOXEI16_V_MF4_MF8, 1556 }, |
| 4809 | { PseudoVLOXEI32_V_M1_M1, 1557 }, |
| 4810 | { PseudoVLOXEI32_V_M1_M2, 1558 }, |
| 4811 | { PseudoVLOXEI32_V_M1_MF2, 1559 }, |
| 4812 | { PseudoVLOXEI32_V_M1_MF4, 1560 }, |
| 4813 | { PseudoVLOXEI32_V_M2_M1, 1561 }, |
| 4814 | { PseudoVLOXEI32_V_M2_M2, 1562 }, |
| 4815 | { PseudoVLOXEI32_V_M2_M4, 1563 }, |
| 4816 | { PseudoVLOXEI32_V_M2_MF2, 1564 }, |
| 4817 | { PseudoVLOXEI32_V_M4_M1, 1565 }, |
| 4818 | { PseudoVLOXEI32_V_M4_M2, 1566 }, |
| 4819 | { PseudoVLOXEI32_V_M4_M4, 1567 }, |
| 4820 | { PseudoVLOXEI32_V_M4_M8, 1568 }, |
| 4821 | { PseudoVLOXEI32_V_M8_M2, 1569 }, |
| 4822 | { PseudoVLOXEI32_V_M8_M4, 1570 }, |
| 4823 | { PseudoVLOXEI32_V_M8_M8, 1571 }, |
| 4824 | { PseudoVLOXEI32_V_MF2_M1, 1572 }, |
| 4825 | { PseudoVLOXEI32_V_MF2_MF2, 1573 }, |
| 4826 | { PseudoVLOXEI32_V_MF2_MF4, 1574 }, |
| 4827 | { PseudoVLOXEI32_V_MF2_MF8, 1575 }, |
| 4828 | { PseudoVLOXEI64_V_M1_M1, 1576 }, |
| 4829 | { PseudoVLOXEI64_V_M1_MF2, 1577 }, |
| 4830 | { PseudoVLOXEI64_V_M1_MF4, 1578 }, |
| 4831 | { PseudoVLOXEI64_V_M1_MF8, 1579 }, |
| 4832 | { PseudoVLOXEI64_V_M2_M1, 1580 }, |
| 4833 | { PseudoVLOXEI64_V_M2_M2, 1581 }, |
| 4834 | { PseudoVLOXEI64_V_M2_MF2, 1582 }, |
| 4835 | { PseudoVLOXEI64_V_M2_MF4, 1583 }, |
| 4836 | { PseudoVLOXEI64_V_M4_M1, 1584 }, |
| 4837 | { PseudoVLOXEI64_V_M4_M2, 1585 }, |
| 4838 | { PseudoVLOXEI64_V_M4_M4, 1586 }, |
| 4839 | { PseudoVLOXEI64_V_M4_MF2, 1587 }, |
| 4840 | { PseudoVLOXEI64_V_M8_M1, 1588 }, |
| 4841 | { PseudoVLOXEI64_V_M8_M2, 1589 }, |
| 4842 | { PseudoVLOXEI64_V_M8_M4, 1590 }, |
| 4843 | { PseudoVLOXEI64_V_M8_M8, 1591 }, |
| 4844 | { PseudoVLOXEI8_V_M1_M1, 1592 }, |
| 4845 | { PseudoVLOXEI8_V_M1_M2, 1593 }, |
| 4846 | { PseudoVLOXEI8_V_M1_M4, 1594 }, |
| 4847 | { PseudoVLOXEI8_V_M1_M8, 1595 }, |
| 4848 | { PseudoVLOXEI8_V_M2_M2, 1596 }, |
| 4849 | { PseudoVLOXEI8_V_M2_M4, 1597 }, |
| 4850 | { PseudoVLOXEI8_V_M2_M8, 1598 }, |
| 4851 | { PseudoVLOXEI8_V_M4_M4, 1599 }, |
| 4852 | { PseudoVLOXEI8_V_M4_M8, 1600 }, |
| 4853 | { PseudoVLOXEI8_V_M8_M8, 1601 }, |
| 4854 | { PseudoVLOXEI8_V_MF2_M1, 1602 }, |
| 4855 | { PseudoVLOXEI8_V_MF2_M2, 1603 }, |
| 4856 | { PseudoVLOXEI8_V_MF2_M4, 1604 }, |
| 4857 | { PseudoVLOXEI8_V_MF2_MF2, 1605 }, |
| 4858 | { PseudoVLOXEI8_V_MF4_M1, 1606 }, |
| 4859 | { PseudoVLOXEI8_V_MF4_M2, 1607 }, |
| 4860 | { PseudoVLOXEI8_V_MF4_MF2, 1608 }, |
| 4861 | { PseudoVLOXEI8_V_MF4_MF4, 1609 }, |
| 4862 | { PseudoVLOXEI8_V_MF8_M1, 1610 }, |
| 4863 | { PseudoVLOXEI8_V_MF8_MF2, 1611 }, |
| 4864 | { PseudoVLOXEI8_V_MF8_MF4, 1612 }, |
| 4865 | { PseudoVLOXEI8_V_MF8_MF8, 1613 }, |
| 4866 | { PseudoVLSE16_V_M1, 1614 }, |
| 4867 | { PseudoVLSE16_V_M2, 1615 }, |
| 4868 | { PseudoVLSE16_V_M4, 1616 }, |
| 4869 | { PseudoVLSE16_V_M8, 1617 }, |
| 4870 | { PseudoVLSE16_V_MF2, 1618 }, |
| 4871 | { PseudoVLSE16_V_MF4, 1619 }, |
| 4872 | { PseudoVLSE32_V_M1, 1620 }, |
| 4873 | { PseudoVLSE32_V_M2, 1621 }, |
| 4874 | { PseudoVLSE32_V_M4, 1622 }, |
| 4875 | { PseudoVLSE32_V_M8, 1623 }, |
| 4876 | { PseudoVLSE32_V_MF2, 1624 }, |
| 4877 | { PseudoVLSE64_V_M1, 1625 }, |
| 4878 | { PseudoVLSE64_V_M2, 1626 }, |
| 4879 | { PseudoVLSE64_V_M4, 1627 }, |
| 4880 | { PseudoVLSE64_V_M8, 1628 }, |
| 4881 | { PseudoVLSE8_V_M1, 1629 }, |
| 4882 | { PseudoVLSE8_V_M2, 1630 }, |
| 4883 | { PseudoVLSE8_V_M4, 1631 }, |
| 4884 | { PseudoVLSE8_V_M8, 1632 }, |
| 4885 | { PseudoVLSE8_V_MF2, 1633 }, |
| 4886 | { PseudoVLSE8_V_MF4, 1634 }, |
| 4887 | { PseudoVLSE8_V_MF8, 1635 }, |
| 4888 | { PseudoVLUXEI16_V_M1_M1, 1636 }, |
| 4889 | { PseudoVLUXEI16_V_M1_M2, 1637 }, |
| 4890 | { PseudoVLUXEI16_V_M1_M4, 1638 }, |
| 4891 | { PseudoVLUXEI16_V_M1_MF2, 1639 }, |
| 4892 | { PseudoVLUXEI16_V_M2_M1, 1640 }, |
| 4893 | { PseudoVLUXEI16_V_M2_M2, 1641 }, |
| 4894 | { PseudoVLUXEI16_V_M2_M4, 1642 }, |
| 4895 | { PseudoVLUXEI16_V_M2_M8, 1643 }, |
| 4896 | { PseudoVLUXEI16_V_M4_M2, 1644 }, |
| 4897 | { PseudoVLUXEI16_V_M4_M4, 1645 }, |
| 4898 | { PseudoVLUXEI16_V_M4_M8, 1646 }, |
| 4899 | { PseudoVLUXEI16_V_M8_M4, 1647 }, |
| 4900 | { PseudoVLUXEI16_V_M8_M8, 1648 }, |
| 4901 | { PseudoVLUXEI16_V_MF2_M1, 1649 }, |
| 4902 | { PseudoVLUXEI16_V_MF2_M2, 1650 }, |
| 4903 | { PseudoVLUXEI16_V_MF2_MF2, 1651 }, |
| 4904 | { PseudoVLUXEI16_V_MF2_MF4, 1652 }, |
| 4905 | { PseudoVLUXEI16_V_MF4_M1, 1653 }, |
| 4906 | { PseudoVLUXEI16_V_MF4_MF2, 1654 }, |
| 4907 | { PseudoVLUXEI16_V_MF4_MF4, 1655 }, |
| 4908 | { PseudoVLUXEI16_V_MF4_MF8, 1656 }, |
| 4909 | { PseudoVLUXEI32_V_M1_M1, 1657 }, |
| 4910 | { PseudoVLUXEI32_V_M1_M2, 1658 }, |
| 4911 | { PseudoVLUXEI32_V_M1_MF2, 1659 }, |
| 4912 | { PseudoVLUXEI32_V_M1_MF4, 1660 }, |
| 4913 | { PseudoVLUXEI32_V_M2_M1, 1661 }, |
| 4914 | { PseudoVLUXEI32_V_M2_M2, 1662 }, |
| 4915 | { PseudoVLUXEI32_V_M2_M4, 1663 }, |
| 4916 | { PseudoVLUXEI32_V_M2_MF2, 1664 }, |
| 4917 | { PseudoVLUXEI32_V_M4_M1, 1665 }, |
| 4918 | { PseudoVLUXEI32_V_M4_M2, 1666 }, |
| 4919 | { PseudoVLUXEI32_V_M4_M4, 1667 }, |
| 4920 | { PseudoVLUXEI32_V_M4_M8, 1668 }, |
| 4921 | { PseudoVLUXEI32_V_M8_M2, 1669 }, |
| 4922 | { PseudoVLUXEI32_V_M8_M4, 1670 }, |
| 4923 | { PseudoVLUXEI32_V_M8_M8, 1671 }, |
| 4924 | { PseudoVLUXEI32_V_MF2_M1, 1672 }, |
| 4925 | { PseudoVLUXEI32_V_MF2_MF2, 1673 }, |
| 4926 | { PseudoVLUXEI32_V_MF2_MF4, 1674 }, |
| 4927 | { PseudoVLUXEI32_V_MF2_MF8, 1675 }, |
| 4928 | { PseudoVLUXEI64_V_M1_M1, 1676 }, |
| 4929 | { PseudoVLUXEI64_V_M1_MF2, 1677 }, |
| 4930 | { PseudoVLUXEI64_V_M1_MF4, 1678 }, |
| 4931 | { PseudoVLUXEI64_V_M1_MF8, 1679 }, |
| 4932 | { PseudoVLUXEI64_V_M2_M1, 1680 }, |
| 4933 | { PseudoVLUXEI64_V_M2_M2, 1681 }, |
| 4934 | { PseudoVLUXEI64_V_M2_MF2, 1682 }, |
| 4935 | { PseudoVLUXEI64_V_M2_MF4, 1683 }, |
| 4936 | { PseudoVLUXEI64_V_M4_M1, 1684 }, |
| 4937 | { PseudoVLUXEI64_V_M4_M2, 1685 }, |
| 4938 | { PseudoVLUXEI64_V_M4_M4, 1686 }, |
| 4939 | { PseudoVLUXEI64_V_M4_MF2, 1687 }, |
| 4940 | { PseudoVLUXEI64_V_M8_M1, 1688 }, |
| 4941 | { PseudoVLUXEI64_V_M8_M2, 1689 }, |
| 4942 | { PseudoVLUXEI64_V_M8_M4, 1690 }, |
| 4943 | { PseudoVLUXEI64_V_M8_M8, 1691 }, |
| 4944 | { PseudoVLUXEI8_V_M1_M1, 1692 }, |
| 4945 | { PseudoVLUXEI8_V_M1_M2, 1693 }, |
| 4946 | { PseudoVLUXEI8_V_M1_M4, 1694 }, |
| 4947 | { PseudoVLUXEI8_V_M1_M8, 1695 }, |
| 4948 | { PseudoVLUXEI8_V_M2_M2, 1696 }, |
| 4949 | { PseudoVLUXEI8_V_M2_M4, 1697 }, |
| 4950 | { PseudoVLUXEI8_V_M2_M8, 1698 }, |
| 4951 | { PseudoVLUXEI8_V_M4_M4, 1699 }, |
| 4952 | { PseudoVLUXEI8_V_M4_M8, 1700 }, |
| 4953 | { PseudoVLUXEI8_V_M8_M8, 1701 }, |
| 4954 | { PseudoVLUXEI8_V_MF2_M1, 1702 }, |
| 4955 | { PseudoVLUXEI8_V_MF2_M2, 1703 }, |
| 4956 | { PseudoVLUXEI8_V_MF2_M4, 1704 }, |
| 4957 | { PseudoVLUXEI8_V_MF2_MF2, 1705 }, |
| 4958 | { PseudoVLUXEI8_V_MF4_M1, 1706 }, |
| 4959 | { PseudoVLUXEI8_V_MF4_M2, 1707 }, |
| 4960 | { PseudoVLUXEI8_V_MF4_MF2, 1708 }, |
| 4961 | { PseudoVLUXEI8_V_MF4_MF4, 1709 }, |
| 4962 | { PseudoVLUXEI8_V_MF8_M1, 1710 }, |
| 4963 | { PseudoVLUXEI8_V_MF8_MF2, 1711 }, |
| 4964 | { PseudoVLUXEI8_V_MF8_MF4, 1712 }, |
| 4965 | { PseudoVLUXEI8_V_MF8_MF8, 1713 }, |
| 4966 | { PseudoVMACC_VV_M1, 1714 }, |
| 4967 | { PseudoVMACC_VV_M2, 1715 }, |
| 4968 | { PseudoVMACC_VV_M4, 1716 }, |
| 4969 | { PseudoVMACC_VV_M8, 1717 }, |
| 4970 | { PseudoVMACC_VV_MF2, 1718 }, |
| 4971 | { PseudoVMACC_VV_MF4, 1719 }, |
| 4972 | { PseudoVMACC_VV_MF8, 1720 }, |
| 4973 | { PseudoVMACC_VX_M1, 1721 }, |
| 4974 | { PseudoVMACC_VX_M2, 1722 }, |
| 4975 | { PseudoVMACC_VX_M4, 1723 }, |
| 4976 | { PseudoVMACC_VX_M8, 1724 }, |
| 4977 | { PseudoVMACC_VX_MF2, 1725 }, |
| 4978 | { PseudoVMACC_VX_MF4, 1726 }, |
| 4979 | { PseudoVMACC_VX_MF8, 1727 }, |
| 4980 | { PseudoVMADD_VV_M1, 1728 }, |
| 4981 | { PseudoVMADD_VV_M2, 1729 }, |
| 4982 | { PseudoVMADD_VV_M4, 1730 }, |
| 4983 | { PseudoVMADD_VV_M8, 1731 }, |
| 4984 | { PseudoVMADD_VV_MF2, 1732 }, |
| 4985 | { PseudoVMADD_VV_MF4, 1733 }, |
| 4986 | { PseudoVMADD_VV_MF8, 1734 }, |
| 4987 | { PseudoVMADD_VX_M1, 1735 }, |
| 4988 | { PseudoVMADD_VX_M2, 1736 }, |
| 4989 | { PseudoVMADD_VX_M4, 1737 }, |
| 4990 | { PseudoVMADD_VX_M8, 1738 }, |
| 4991 | { PseudoVMADD_VX_MF2, 1739 }, |
| 4992 | { PseudoVMADD_VX_MF4, 1740 }, |
| 4993 | { PseudoVMADD_VX_MF8, 1741 }, |
| 4994 | { PseudoVMAXU_VV_M1, 1742 }, |
| 4995 | { PseudoVMAXU_VV_M2, 1743 }, |
| 4996 | { PseudoVMAXU_VV_M4, 1744 }, |
| 4997 | { PseudoVMAXU_VV_M8, 1745 }, |
| 4998 | { PseudoVMAXU_VV_MF2, 1746 }, |
| 4999 | { PseudoVMAXU_VV_MF4, 1747 }, |
| 5000 | { PseudoVMAXU_VV_MF8, 1748 }, |
| 5001 | { PseudoVMAXU_VX_M1, 1749 }, |
| 5002 | { PseudoVMAXU_VX_M2, 1750 }, |
| 5003 | { PseudoVMAXU_VX_M4, 1751 }, |
| 5004 | { PseudoVMAXU_VX_M8, 1752 }, |
| 5005 | { PseudoVMAXU_VX_MF2, 1753 }, |
| 5006 | { PseudoVMAXU_VX_MF4, 1754 }, |
| 5007 | { PseudoVMAXU_VX_MF8, 1755 }, |
| 5008 | { PseudoVMAX_VV_M1, 1756 }, |
| 5009 | { PseudoVMAX_VV_M2, 1757 }, |
| 5010 | { PseudoVMAX_VV_M4, 1758 }, |
| 5011 | { PseudoVMAX_VV_M8, 1759 }, |
| 5012 | { PseudoVMAX_VV_MF2, 1760 }, |
| 5013 | { PseudoVMAX_VV_MF4, 1761 }, |
| 5014 | { PseudoVMAX_VV_MF8, 1762 }, |
| 5015 | { PseudoVMAX_VX_M1, 1763 }, |
| 5016 | { PseudoVMAX_VX_M2, 1764 }, |
| 5017 | { PseudoVMAX_VX_M4, 1765 }, |
| 5018 | { PseudoVMAX_VX_M8, 1766 }, |
| 5019 | { PseudoVMAX_VX_MF2, 1767 }, |
| 5020 | { PseudoVMAX_VX_MF4, 1768 }, |
| 5021 | { PseudoVMAX_VX_MF8, 1769 }, |
| 5022 | { PseudoVMFEQ_VFPR16_M1, 1770 }, |
| 5023 | { PseudoVMFEQ_VFPR16_M2, 1771 }, |
| 5024 | { PseudoVMFEQ_VFPR16_M4, 1772 }, |
| 5025 | { PseudoVMFEQ_VFPR16_M8, 1773 }, |
| 5026 | { PseudoVMFEQ_VFPR16_MF2, 1774 }, |
| 5027 | { PseudoVMFEQ_VFPR16_MF4, 1775 }, |
| 5028 | { PseudoVMFEQ_VFPR32_M1, 1776 }, |
| 5029 | { PseudoVMFEQ_VFPR32_M2, 1777 }, |
| 5030 | { PseudoVMFEQ_VFPR32_M4, 1778 }, |
| 5031 | { PseudoVMFEQ_VFPR32_M8, 1779 }, |
| 5032 | { PseudoVMFEQ_VFPR32_MF2, 1780 }, |
| 5033 | { PseudoVMFEQ_VFPR64_M1, 1781 }, |
| 5034 | { PseudoVMFEQ_VFPR64_M2, 1782 }, |
| 5035 | { PseudoVMFEQ_VFPR64_M4, 1783 }, |
| 5036 | { PseudoVMFEQ_VFPR64_M8, 1784 }, |
| 5037 | { PseudoVMFEQ_VV_M1, 1785 }, |
| 5038 | { PseudoVMFEQ_VV_M2, 1786 }, |
| 5039 | { PseudoVMFEQ_VV_M4, 1787 }, |
| 5040 | { PseudoVMFEQ_VV_M8, 1788 }, |
| 5041 | { PseudoVMFEQ_VV_MF2, 1789 }, |
| 5042 | { PseudoVMFEQ_VV_MF4, 1790 }, |
| 5043 | { PseudoVMFGE_VFPR16_M1, 1791 }, |
| 5044 | { PseudoVMFGE_VFPR16_M2, 1792 }, |
| 5045 | { PseudoVMFGE_VFPR16_M4, 1793 }, |
| 5046 | { PseudoVMFGE_VFPR16_M8, 1794 }, |
| 5047 | { PseudoVMFGE_VFPR16_MF2, 1795 }, |
| 5048 | { PseudoVMFGE_VFPR16_MF4, 1796 }, |
| 5049 | { PseudoVMFGE_VFPR32_M1, 1797 }, |
| 5050 | { PseudoVMFGE_VFPR32_M2, 1798 }, |
| 5051 | { PseudoVMFGE_VFPR32_M4, 1799 }, |
| 5052 | { PseudoVMFGE_VFPR32_M8, 1800 }, |
| 5053 | { PseudoVMFGE_VFPR32_MF2, 1801 }, |
| 5054 | { PseudoVMFGE_VFPR64_M1, 1802 }, |
| 5055 | { PseudoVMFGE_VFPR64_M2, 1803 }, |
| 5056 | { PseudoVMFGE_VFPR64_M4, 1804 }, |
| 5057 | { PseudoVMFGE_VFPR64_M8, 1805 }, |
| 5058 | { PseudoVMFGT_VFPR16_M1, 1806 }, |
| 5059 | { PseudoVMFGT_VFPR16_M2, 1807 }, |
| 5060 | { PseudoVMFGT_VFPR16_M4, 1808 }, |
| 5061 | { PseudoVMFGT_VFPR16_M8, 1809 }, |
| 5062 | { PseudoVMFGT_VFPR16_MF2, 1810 }, |
| 5063 | { PseudoVMFGT_VFPR16_MF4, 1811 }, |
| 5064 | { PseudoVMFGT_VFPR32_M1, 1812 }, |
| 5065 | { PseudoVMFGT_VFPR32_M2, 1813 }, |
| 5066 | { PseudoVMFGT_VFPR32_M4, 1814 }, |
| 5067 | { PseudoVMFGT_VFPR32_M8, 1815 }, |
| 5068 | { PseudoVMFGT_VFPR32_MF2, 1816 }, |
| 5069 | { PseudoVMFGT_VFPR64_M1, 1817 }, |
| 5070 | { PseudoVMFGT_VFPR64_M2, 1818 }, |
| 5071 | { PseudoVMFGT_VFPR64_M4, 1819 }, |
| 5072 | { PseudoVMFGT_VFPR64_M8, 1820 }, |
| 5073 | { PseudoVMFLE_VFPR16_M1, 1821 }, |
| 5074 | { PseudoVMFLE_VFPR16_M2, 1822 }, |
| 5075 | { PseudoVMFLE_VFPR16_M4, 1823 }, |
| 5076 | { PseudoVMFLE_VFPR16_M8, 1824 }, |
| 5077 | { PseudoVMFLE_VFPR16_MF2, 1825 }, |
| 5078 | { PseudoVMFLE_VFPR16_MF4, 1826 }, |
| 5079 | { PseudoVMFLE_VFPR32_M1, 1827 }, |
| 5080 | { PseudoVMFLE_VFPR32_M2, 1828 }, |
| 5081 | { PseudoVMFLE_VFPR32_M4, 1829 }, |
| 5082 | { PseudoVMFLE_VFPR32_M8, 1830 }, |
| 5083 | { PseudoVMFLE_VFPR32_MF2, 1831 }, |
| 5084 | { PseudoVMFLE_VFPR64_M1, 1832 }, |
| 5085 | { PseudoVMFLE_VFPR64_M2, 1833 }, |
| 5086 | { PseudoVMFLE_VFPR64_M4, 1834 }, |
| 5087 | { PseudoVMFLE_VFPR64_M8, 1835 }, |
| 5088 | { PseudoVMFLE_VV_M1, 1836 }, |
| 5089 | { PseudoVMFLE_VV_M2, 1837 }, |
| 5090 | { PseudoVMFLE_VV_M4, 1838 }, |
| 5091 | { PseudoVMFLE_VV_M8, 1839 }, |
| 5092 | { PseudoVMFLE_VV_MF2, 1840 }, |
| 5093 | { PseudoVMFLE_VV_MF4, 1841 }, |
| 5094 | { PseudoVMFLT_VFPR16_M1, 1842 }, |
| 5095 | { PseudoVMFLT_VFPR16_M2, 1843 }, |
| 5096 | { PseudoVMFLT_VFPR16_M4, 1844 }, |
| 5097 | { PseudoVMFLT_VFPR16_M8, 1845 }, |
| 5098 | { PseudoVMFLT_VFPR16_MF2, 1846 }, |
| 5099 | { PseudoVMFLT_VFPR16_MF4, 1847 }, |
| 5100 | { PseudoVMFLT_VFPR32_M1, 1848 }, |
| 5101 | { PseudoVMFLT_VFPR32_M2, 1849 }, |
| 5102 | { PseudoVMFLT_VFPR32_M4, 1850 }, |
| 5103 | { PseudoVMFLT_VFPR32_M8, 1851 }, |
| 5104 | { PseudoVMFLT_VFPR32_MF2, 1852 }, |
| 5105 | { PseudoVMFLT_VFPR64_M1, 1853 }, |
| 5106 | { PseudoVMFLT_VFPR64_M2, 1854 }, |
| 5107 | { PseudoVMFLT_VFPR64_M4, 1855 }, |
| 5108 | { PseudoVMFLT_VFPR64_M8, 1856 }, |
| 5109 | { PseudoVMFLT_VV_M1, 1857 }, |
| 5110 | { PseudoVMFLT_VV_M2, 1858 }, |
| 5111 | { PseudoVMFLT_VV_M4, 1859 }, |
| 5112 | { PseudoVMFLT_VV_M8, 1860 }, |
| 5113 | { PseudoVMFLT_VV_MF2, 1861 }, |
| 5114 | { PseudoVMFLT_VV_MF4, 1862 }, |
| 5115 | { PseudoVMFNE_VFPR16_M1, 1863 }, |
| 5116 | { PseudoVMFNE_VFPR16_M2, 1864 }, |
| 5117 | { PseudoVMFNE_VFPR16_M4, 1865 }, |
| 5118 | { PseudoVMFNE_VFPR16_M8, 1866 }, |
| 5119 | { PseudoVMFNE_VFPR16_MF2, 1867 }, |
| 5120 | { PseudoVMFNE_VFPR16_MF4, 1868 }, |
| 5121 | { PseudoVMFNE_VFPR32_M1, 1869 }, |
| 5122 | { PseudoVMFNE_VFPR32_M2, 1870 }, |
| 5123 | { PseudoVMFNE_VFPR32_M4, 1871 }, |
| 5124 | { PseudoVMFNE_VFPR32_M8, 1872 }, |
| 5125 | { PseudoVMFNE_VFPR32_MF2, 1873 }, |
| 5126 | { PseudoVMFNE_VFPR64_M1, 1874 }, |
| 5127 | { PseudoVMFNE_VFPR64_M2, 1875 }, |
| 5128 | { PseudoVMFNE_VFPR64_M4, 1876 }, |
| 5129 | { PseudoVMFNE_VFPR64_M8, 1877 }, |
| 5130 | { PseudoVMFNE_VV_M1, 1878 }, |
| 5131 | { PseudoVMFNE_VV_M2, 1879 }, |
| 5132 | { PseudoVMFNE_VV_M4, 1880 }, |
| 5133 | { PseudoVMFNE_VV_M8, 1881 }, |
| 5134 | { PseudoVMFNE_VV_MF2, 1882 }, |
| 5135 | { PseudoVMFNE_VV_MF4, 1883 }, |
| 5136 | { PseudoVMINU_VV_M1, 1884 }, |
| 5137 | { PseudoVMINU_VV_M2, 1885 }, |
| 5138 | { PseudoVMINU_VV_M4, 1886 }, |
| 5139 | { PseudoVMINU_VV_M8, 1887 }, |
| 5140 | { PseudoVMINU_VV_MF2, 1888 }, |
| 5141 | { PseudoVMINU_VV_MF4, 1889 }, |
| 5142 | { PseudoVMINU_VV_MF8, 1890 }, |
| 5143 | { PseudoVMINU_VX_M1, 1891 }, |
| 5144 | { PseudoVMINU_VX_M2, 1892 }, |
| 5145 | { PseudoVMINU_VX_M4, 1893 }, |
| 5146 | { PseudoVMINU_VX_M8, 1894 }, |
| 5147 | { PseudoVMINU_VX_MF2, 1895 }, |
| 5148 | { PseudoVMINU_VX_MF4, 1896 }, |
| 5149 | { PseudoVMINU_VX_MF8, 1897 }, |
| 5150 | { PseudoVMIN_VV_M1, 1898 }, |
| 5151 | { PseudoVMIN_VV_M2, 1899 }, |
| 5152 | { PseudoVMIN_VV_M4, 1900 }, |
| 5153 | { PseudoVMIN_VV_M8, 1901 }, |
| 5154 | { PseudoVMIN_VV_MF2, 1902 }, |
| 5155 | { PseudoVMIN_VV_MF4, 1903 }, |
| 5156 | { PseudoVMIN_VV_MF8, 1904 }, |
| 5157 | { PseudoVMIN_VX_M1, 1905 }, |
| 5158 | { PseudoVMIN_VX_M2, 1906 }, |
| 5159 | { PseudoVMIN_VX_M4, 1907 }, |
| 5160 | { PseudoVMIN_VX_M8, 1908 }, |
| 5161 | { PseudoVMIN_VX_MF2, 1909 }, |
| 5162 | { PseudoVMIN_VX_MF4, 1910 }, |
| 5163 | { PseudoVMIN_VX_MF8, 1911 }, |
| 5164 | { PseudoVMSEQ_VI_M1, 1912 }, |
| 5165 | { PseudoVMSEQ_VI_M2, 1913 }, |
| 5166 | { PseudoVMSEQ_VI_M4, 1914 }, |
| 5167 | { PseudoVMSEQ_VI_M8, 1915 }, |
| 5168 | { PseudoVMSEQ_VI_MF2, 1916 }, |
| 5169 | { PseudoVMSEQ_VI_MF4, 1917 }, |
| 5170 | { PseudoVMSEQ_VI_MF8, 1918 }, |
| 5171 | { PseudoVMSEQ_VV_M1, 1919 }, |
| 5172 | { PseudoVMSEQ_VV_M2, 1920 }, |
| 5173 | { PseudoVMSEQ_VV_M4, 1921 }, |
| 5174 | { PseudoVMSEQ_VV_M8, 1922 }, |
| 5175 | { PseudoVMSEQ_VV_MF2, 1923 }, |
| 5176 | { PseudoVMSEQ_VV_MF4, 1924 }, |
| 5177 | { PseudoVMSEQ_VV_MF8, 1925 }, |
| 5178 | { PseudoVMSEQ_VX_M1, 1926 }, |
| 5179 | { PseudoVMSEQ_VX_M2, 1927 }, |
| 5180 | { PseudoVMSEQ_VX_M4, 1928 }, |
| 5181 | { PseudoVMSEQ_VX_M8, 1929 }, |
| 5182 | { PseudoVMSEQ_VX_MF2, 1930 }, |
| 5183 | { PseudoVMSEQ_VX_MF4, 1931 }, |
| 5184 | { PseudoVMSEQ_VX_MF8, 1932 }, |
| 5185 | { PseudoVMSGTU_VI_M1, 1933 }, |
| 5186 | { PseudoVMSGTU_VI_M2, 1934 }, |
| 5187 | { PseudoVMSGTU_VI_M4, 1935 }, |
| 5188 | { PseudoVMSGTU_VI_M8, 1936 }, |
| 5189 | { PseudoVMSGTU_VI_MF2, 1937 }, |
| 5190 | { PseudoVMSGTU_VI_MF4, 1938 }, |
| 5191 | { PseudoVMSGTU_VI_MF8, 1939 }, |
| 5192 | { PseudoVMSGTU_VX_M1, 1940 }, |
| 5193 | { PseudoVMSGTU_VX_M2, 1941 }, |
| 5194 | { PseudoVMSGTU_VX_M4, 1942 }, |
| 5195 | { PseudoVMSGTU_VX_M8, 1943 }, |
| 5196 | { PseudoVMSGTU_VX_MF2, 1944 }, |
| 5197 | { PseudoVMSGTU_VX_MF4, 1945 }, |
| 5198 | { PseudoVMSGTU_VX_MF8, 1946 }, |
| 5199 | { PseudoVMSGT_VI_M1, 1947 }, |
| 5200 | { PseudoVMSGT_VI_M2, 1948 }, |
| 5201 | { PseudoVMSGT_VI_M4, 1949 }, |
| 5202 | { PseudoVMSGT_VI_M8, 1950 }, |
| 5203 | { PseudoVMSGT_VI_MF2, 1951 }, |
| 5204 | { PseudoVMSGT_VI_MF4, 1952 }, |
| 5205 | { PseudoVMSGT_VI_MF8, 1953 }, |
| 5206 | { PseudoVMSGT_VX_M1, 1954 }, |
| 5207 | { PseudoVMSGT_VX_M2, 1955 }, |
| 5208 | { PseudoVMSGT_VX_M4, 1956 }, |
| 5209 | { PseudoVMSGT_VX_M8, 1957 }, |
| 5210 | { PseudoVMSGT_VX_MF2, 1958 }, |
| 5211 | { PseudoVMSGT_VX_MF4, 1959 }, |
| 5212 | { PseudoVMSGT_VX_MF8, 1960 }, |
| 5213 | { PseudoVMSLEU_VI_M1, 1961 }, |
| 5214 | { PseudoVMSLEU_VI_M2, 1962 }, |
| 5215 | { PseudoVMSLEU_VI_M4, 1963 }, |
| 5216 | { PseudoVMSLEU_VI_M8, 1964 }, |
| 5217 | { PseudoVMSLEU_VI_MF2, 1965 }, |
| 5218 | { PseudoVMSLEU_VI_MF4, 1966 }, |
| 5219 | { PseudoVMSLEU_VI_MF8, 1967 }, |
| 5220 | { PseudoVMSLEU_VV_M1, 1968 }, |
| 5221 | { PseudoVMSLEU_VV_M2, 1969 }, |
| 5222 | { PseudoVMSLEU_VV_M4, 1970 }, |
| 5223 | { PseudoVMSLEU_VV_M8, 1971 }, |
| 5224 | { PseudoVMSLEU_VV_MF2, 1972 }, |
| 5225 | { PseudoVMSLEU_VV_MF4, 1973 }, |
| 5226 | { PseudoVMSLEU_VV_MF8, 1974 }, |
| 5227 | { PseudoVMSLEU_VX_M1, 1975 }, |
| 5228 | { PseudoVMSLEU_VX_M2, 1976 }, |
| 5229 | { PseudoVMSLEU_VX_M4, 1977 }, |
| 5230 | { PseudoVMSLEU_VX_M8, 1978 }, |
| 5231 | { PseudoVMSLEU_VX_MF2, 1979 }, |
| 5232 | { PseudoVMSLEU_VX_MF4, 1980 }, |
| 5233 | { PseudoVMSLEU_VX_MF8, 1981 }, |
| 5234 | { PseudoVMSLE_VI_M1, 1982 }, |
| 5235 | { PseudoVMSLE_VI_M2, 1983 }, |
| 5236 | { PseudoVMSLE_VI_M4, 1984 }, |
| 5237 | { PseudoVMSLE_VI_M8, 1985 }, |
| 5238 | { PseudoVMSLE_VI_MF2, 1986 }, |
| 5239 | { PseudoVMSLE_VI_MF4, 1987 }, |
| 5240 | { PseudoVMSLE_VI_MF8, 1988 }, |
| 5241 | { PseudoVMSLE_VV_M1, 1989 }, |
| 5242 | { PseudoVMSLE_VV_M2, 1990 }, |
| 5243 | { PseudoVMSLE_VV_M4, 1991 }, |
| 5244 | { PseudoVMSLE_VV_M8, 1992 }, |
| 5245 | { PseudoVMSLE_VV_MF2, 1993 }, |
| 5246 | { PseudoVMSLE_VV_MF4, 1994 }, |
| 5247 | { PseudoVMSLE_VV_MF8, 1995 }, |
| 5248 | { PseudoVMSLE_VX_M1, 1996 }, |
| 5249 | { PseudoVMSLE_VX_M2, 1997 }, |
| 5250 | { PseudoVMSLE_VX_M4, 1998 }, |
| 5251 | { PseudoVMSLE_VX_M8, 1999 }, |
| 5252 | { PseudoVMSLE_VX_MF2, 2000 }, |
| 5253 | { PseudoVMSLE_VX_MF4, 2001 }, |
| 5254 | { PseudoVMSLE_VX_MF8, 2002 }, |
| 5255 | { PseudoVMSLTU_VV_M1, 2003 }, |
| 5256 | { PseudoVMSLTU_VV_M2, 2004 }, |
| 5257 | { PseudoVMSLTU_VV_M4, 2005 }, |
| 5258 | { PseudoVMSLTU_VV_M8, 2006 }, |
| 5259 | { PseudoVMSLTU_VV_MF2, 2007 }, |
| 5260 | { PseudoVMSLTU_VV_MF4, 2008 }, |
| 5261 | { PseudoVMSLTU_VV_MF8, 2009 }, |
| 5262 | { PseudoVMSLTU_VX_M1, 2010 }, |
| 5263 | { PseudoVMSLTU_VX_M2, 2011 }, |
| 5264 | { PseudoVMSLTU_VX_M4, 2012 }, |
| 5265 | { PseudoVMSLTU_VX_M8, 2013 }, |
| 5266 | { PseudoVMSLTU_VX_MF2, 2014 }, |
| 5267 | { PseudoVMSLTU_VX_MF4, 2015 }, |
| 5268 | { PseudoVMSLTU_VX_MF8, 2016 }, |
| 5269 | { PseudoVMSLT_VV_M1, 2017 }, |
| 5270 | { PseudoVMSLT_VV_M2, 2018 }, |
| 5271 | { PseudoVMSLT_VV_M4, 2019 }, |
| 5272 | { PseudoVMSLT_VV_M8, 2020 }, |
| 5273 | { PseudoVMSLT_VV_MF2, 2021 }, |
| 5274 | { PseudoVMSLT_VV_MF4, 2022 }, |
| 5275 | { PseudoVMSLT_VV_MF8, 2023 }, |
| 5276 | { PseudoVMSLT_VX_M1, 2024 }, |
| 5277 | { PseudoVMSLT_VX_M2, 2025 }, |
| 5278 | { PseudoVMSLT_VX_M4, 2026 }, |
| 5279 | { PseudoVMSLT_VX_M8, 2027 }, |
| 5280 | { PseudoVMSLT_VX_MF2, 2028 }, |
| 5281 | { PseudoVMSLT_VX_MF4, 2029 }, |
| 5282 | { PseudoVMSLT_VX_MF8, 2030 }, |
| 5283 | { PseudoVMSNE_VI_M1, 2031 }, |
| 5284 | { PseudoVMSNE_VI_M2, 2032 }, |
| 5285 | { PseudoVMSNE_VI_M4, 2033 }, |
| 5286 | { PseudoVMSNE_VI_M8, 2034 }, |
| 5287 | { PseudoVMSNE_VI_MF2, 2035 }, |
| 5288 | { PseudoVMSNE_VI_MF4, 2036 }, |
| 5289 | { PseudoVMSNE_VI_MF8, 2037 }, |
| 5290 | { PseudoVMSNE_VV_M1, 2038 }, |
| 5291 | { PseudoVMSNE_VV_M2, 2039 }, |
| 5292 | { PseudoVMSNE_VV_M4, 2040 }, |
| 5293 | { PseudoVMSNE_VV_M8, 2041 }, |
| 5294 | { PseudoVMSNE_VV_MF2, 2042 }, |
| 5295 | { PseudoVMSNE_VV_MF4, 2043 }, |
| 5296 | { PseudoVMSNE_VV_MF8, 2044 }, |
| 5297 | { PseudoVMSNE_VX_M1, 2045 }, |
| 5298 | { PseudoVMSNE_VX_M2, 2046 }, |
| 5299 | { PseudoVMSNE_VX_M4, 2047 }, |
| 5300 | { PseudoVMSNE_VX_M8, 2048 }, |
| 5301 | { PseudoVMSNE_VX_MF2, 2049 }, |
| 5302 | { PseudoVMSNE_VX_MF4, 2050 }, |
| 5303 | { PseudoVMSNE_VX_MF8, 2051 }, |
| 5304 | { PseudoVMULHSU_VV_M1, 2052 }, |
| 5305 | { PseudoVMULHSU_VV_M2, 2053 }, |
| 5306 | { PseudoVMULHSU_VV_M4, 2054 }, |
| 5307 | { PseudoVMULHSU_VV_M8, 2055 }, |
| 5308 | { PseudoVMULHSU_VV_MF2, 2056 }, |
| 5309 | { PseudoVMULHSU_VV_MF4, 2057 }, |
| 5310 | { PseudoVMULHSU_VV_MF8, 2058 }, |
| 5311 | { PseudoVMULHSU_VX_M1, 2059 }, |
| 5312 | { PseudoVMULHSU_VX_M2, 2060 }, |
| 5313 | { PseudoVMULHSU_VX_M4, 2061 }, |
| 5314 | { PseudoVMULHSU_VX_M8, 2062 }, |
| 5315 | { PseudoVMULHSU_VX_MF2, 2063 }, |
| 5316 | { PseudoVMULHSU_VX_MF4, 2064 }, |
| 5317 | { PseudoVMULHSU_VX_MF8, 2065 }, |
| 5318 | { PseudoVMULHU_VV_M1, 2066 }, |
| 5319 | { PseudoVMULHU_VV_M2, 2067 }, |
| 5320 | { PseudoVMULHU_VV_M4, 2068 }, |
| 5321 | { PseudoVMULHU_VV_M8, 2069 }, |
| 5322 | { PseudoVMULHU_VV_MF2, 2070 }, |
| 5323 | { PseudoVMULHU_VV_MF4, 2071 }, |
| 5324 | { PseudoVMULHU_VV_MF8, 2072 }, |
| 5325 | { PseudoVMULHU_VX_M1, 2073 }, |
| 5326 | { PseudoVMULHU_VX_M2, 2074 }, |
| 5327 | { PseudoVMULHU_VX_M4, 2075 }, |
| 5328 | { PseudoVMULHU_VX_M8, 2076 }, |
| 5329 | { PseudoVMULHU_VX_MF2, 2077 }, |
| 5330 | { PseudoVMULHU_VX_MF4, 2078 }, |
| 5331 | { PseudoVMULHU_VX_MF8, 2079 }, |
| 5332 | { PseudoVMULH_VV_M1, 2080 }, |
| 5333 | { PseudoVMULH_VV_M2, 2081 }, |
| 5334 | { PseudoVMULH_VV_M4, 2082 }, |
| 5335 | { PseudoVMULH_VV_M8, 2083 }, |
| 5336 | { PseudoVMULH_VV_MF2, 2084 }, |
| 5337 | { PseudoVMULH_VV_MF4, 2085 }, |
| 5338 | { PseudoVMULH_VV_MF8, 2086 }, |
| 5339 | { PseudoVMULH_VX_M1, 2087 }, |
| 5340 | { PseudoVMULH_VX_M2, 2088 }, |
| 5341 | { PseudoVMULH_VX_M4, 2089 }, |
| 5342 | { PseudoVMULH_VX_M8, 2090 }, |
| 5343 | { PseudoVMULH_VX_MF2, 2091 }, |
| 5344 | { PseudoVMULH_VX_MF4, 2092 }, |
| 5345 | { PseudoVMULH_VX_MF8, 2093 }, |
| 5346 | { PseudoVMUL_VV_M1, 2094 }, |
| 5347 | { PseudoVMUL_VV_M2, 2095 }, |
| 5348 | { PseudoVMUL_VV_M4, 2096 }, |
| 5349 | { PseudoVMUL_VV_M8, 2097 }, |
| 5350 | { PseudoVMUL_VV_MF2, 2098 }, |
| 5351 | { PseudoVMUL_VV_MF4, 2099 }, |
| 5352 | { PseudoVMUL_VV_MF8, 2100 }, |
| 5353 | { PseudoVMUL_VX_M1, 2101 }, |
| 5354 | { PseudoVMUL_VX_M2, 2102 }, |
| 5355 | { PseudoVMUL_VX_M4, 2103 }, |
| 5356 | { PseudoVMUL_VX_M8, 2104 }, |
| 5357 | { PseudoVMUL_VX_MF2, 2105 }, |
| 5358 | { PseudoVMUL_VX_MF4, 2106 }, |
| 5359 | { PseudoVMUL_VX_MF8, 2107 }, |
| 5360 | { PseudoVNCLIPU_WI_M1, 2108 }, |
| 5361 | { PseudoVNCLIPU_WI_M2, 2109 }, |
| 5362 | { PseudoVNCLIPU_WI_M4, 2110 }, |
| 5363 | { PseudoVNCLIPU_WI_MF2, 2111 }, |
| 5364 | { PseudoVNCLIPU_WI_MF4, 2112 }, |
| 5365 | { PseudoVNCLIPU_WI_MF8, 2113 }, |
| 5366 | { PseudoVNCLIPU_WV_M1, 2114 }, |
| 5367 | { PseudoVNCLIPU_WV_M2, 2115 }, |
| 5368 | { PseudoVNCLIPU_WV_M4, 2116 }, |
| 5369 | { PseudoVNCLIPU_WV_MF2, 2117 }, |
| 5370 | { PseudoVNCLIPU_WV_MF4, 2118 }, |
| 5371 | { PseudoVNCLIPU_WV_MF8, 2119 }, |
| 5372 | { PseudoVNCLIPU_WX_M1, 2120 }, |
| 5373 | { PseudoVNCLIPU_WX_M2, 2121 }, |
| 5374 | { PseudoVNCLIPU_WX_M4, 2122 }, |
| 5375 | { PseudoVNCLIPU_WX_MF2, 2123 }, |
| 5376 | { PseudoVNCLIPU_WX_MF4, 2124 }, |
| 5377 | { PseudoVNCLIPU_WX_MF8, 2125 }, |
| 5378 | { PseudoVNCLIP_WI_M1, 2126 }, |
| 5379 | { PseudoVNCLIP_WI_M2, 2127 }, |
| 5380 | { PseudoVNCLIP_WI_M4, 2128 }, |
| 5381 | { PseudoVNCLIP_WI_MF2, 2129 }, |
| 5382 | { PseudoVNCLIP_WI_MF4, 2130 }, |
| 5383 | { PseudoVNCLIP_WI_MF8, 2131 }, |
| 5384 | { PseudoVNCLIP_WV_M1, 2132 }, |
| 5385 | { PseudoVNCLIP_WV_M2, 2133 }, |
| 5386 | { PseudoVNCLIP_WV_M4, 2134 }, |
| 5387 | { PseudoVNCLIP_WV_MF2, 2135 }, |
| 5388 | { PseudoVNCLIP_WV_MF4, 2136 }, |
| 5389 | { PseudoVNCLIP_WV_MF8, 2137 }, |
| 5390 | { PseudoVNCLIP_WX_M1, 2138 }, |
| 5391 | { PseudoVNCLIP_WX_M2, 2139 }, |
| 5392 | { PseudoVNCLIP_WX_M4, 2140 }, |
| 5393 | { PseudoVNCLIP_WX_MF2, 2141 }, |
| 5394 | { PseudoVNCLIP_WX_MF4, 2142 }, |
| 5395 | { PseudoVNCLIP_WX_MF8, 2143 }, |
| 5396 | { PseudoVNMSAC_VV_M1, 2144 }, |
| 5397 | { PseudoVNMSAC_VV_M2, 2145 }, |
| 5398 | { PseudoVNMSAC_VV_M4, 2146 }, |
| 5399 | { PseudoVNMSAC_VV_M8, 2147 }, |
| 5400 | { PseudoVNMSAC_VV_MF2, 2148 }, |
| 5401 | { PseudoVNMSAC_VV_MF4, 2149 }, |
| 5402 | { PseudoVNMSAC_VV_MF8, 2150 }, |
| 5403 | { PseudoVNMSAC_VX_M1, 2151 }, |
| 5404 | { PseudoVNMSAC_VX_M2, 2152 }, |
| 5405 | { PseudoVNMSAC_VX_M4, 2153 }, |
| 5406 | { PseudoVNMSAC_VX_M8, 2154 }, |
| 5407 | { PseudoVNMSAC_VX_MF2, 2155 }, |
| 5408 | { PseudoVNMSAC_VX_MF4, 2156 }, |
| 5409 | { PseudoVNMSAC_VX_MF8, 2157 }, |
| 5410 | { PseudoVNMSUB_VV_M1, 2158 }, |
| 5411 | { PseudoVNMSUB_VV_M2, 2159 }, |
| 5412 | { PseudoVNMSUB_VV_M4, 2160 }, |
| 5413 | { PseudoVNMSUB_VV_M8, 2161 }, |
| 5414 | { PseudoVNMSUB_VV_MF2, 2162 }, |
| 5415 | { PseudoVNMSUB_VV_MF4, 2163 }, |
| 5416 | { PseudoVNMSUB_VV_MF8, 2164 }, |
| 5417 | { PseudoVNMSUB_VX_M1, 2165 }, |
| 5418 | { PseudoVNMSUB_VX_M2, 2166 }, |
| 5419 | { PseudoVNMSUB_VX_M4, 2167 }, |
| 5420 | { PseudoVNMSUB_VX_M8, 2168 }, |
| 5421 | { PseudoVNMSUB_VX_MF2, 2169 }, |
| 5422 | { PseudoVNMSUB_VX_MF4, 2170 }, |
| 5423 | { PseudoVNMSUB_VX_MF8, 2171 }, |
| 5424 | { PseudoVNSRA_WI_M1, 2172 }, |
| 5425 | { PseudoVNSRA_WI_M2, 2173 }, |
| 5426 | { PseudoVNSRA_WI_M4, 2174 }, |
| 5427 | { PseudoVNSRA_WI_MF2, 2175 }, |
| 5428 | { PseudoVNSRA_WI_MF4, 2176 }, |
| 5429 | { PseudoVNSRA_WI_MF8, 2177 }, |
| 5430 | { PseudoVNSRA_WV_M1, 2178 }, |
| 5431 | { PseudoVNSRA_WV_M2, 2179 }, |
| 5432 | { PseudoVNSRA_WV_M4, 2180 }, |
| 5433 | { PseudoVNSRA_WV_MF2, 2181 }, |
| 5434 | { PseudoVNSRA_WV_MF4, 2182 }, |
| 5435 | { PseudoVNSRA_WV_MF8, 2183 }, |
| 5436 | { PseudoVNSRA_WX_M1, 2184 }, |
| 5437 | { PseudoVNSRA_WX_M2, 2185 }, |
| 5438 | { PseudoVNSRA_WX_M4, 2186 }, |
| 5439 | { PseudoVNSRA_WX_MF2, 2187 }, |
| 5440 | { PseudoVNSRA_WX_MF4, 2188 }, |
| 5441 | { PseudoVNSRA_WX_MF8, 2189 }, |
| 5442 | { PseudoVNSRL_WI_M1, 2190 }, |
| 5443 | { PseudoVNSRL_WI_M2, 2191 }, |
| 5444 | { PseudoVNSRL_WI_M4, 2192 }, |
| 5445 | { PseudoVNSRL_WI_MF2, 2193 }, |
| 5446 | { PseudoVNSRL_WI_MF4, 2194 }, |
| 5447 | { PseudoVNSRL_WI_MF8, 2195 }, |
| 5448 | { PseudoVNSRL_WV_M1, 2196 }, |
| 5449 | { PseudoVNSRL_WV_M2, 2197 }, |
| 5450 | { PseudoVNSRL_WV_M4, 2198 }, |
| 5451 | { PseudoVNSRL_WV_MF2, 2199 }, |
| 5452 | { PseudoVNSRL_WV_MF4, 2200 }, |
| 5453 | { PseudoVNSRL_WV_MF8, 2201 }, |
| 5454 | { PseudoVNSRL_WX_M1, 2202 }, |
| 5455 | { PseudoVNSRL_WX_M2, 2203 }, |
| 5456 | { PseudoVNSRL_WX_M4, 2204 }, |
| 5457 | { PseudoVNSRL_WX_MF2, 2205 }, |
| 5458 | { PseudoVNSRL_WX_MF4, 2206 }, |
| 5459 | { PseudoVNSRL_WX_MF8, 2207 }, |
| 5460 | { PseudoVOR_VI_M1, 2208 }, |
| 5461 | { PseudoVOR_VI_M2, 2209 }, |
| 5462 | { PseudoVOR_VI_M4, 2210 }, |
| 5463 | { PseudoVOR_VI_M8, 2211 }, |
| 5464 | { PseudoVOR_VI_MF2, 2212 }, |
| 5465 | { PseudoVOR_VI_MF4, 2213 }, |
| 5466 | { PseudoVOR_VI_MF8, 2214 }, |
| 5467 | { PseudoVOR_VV_M1, 2215 }, |
| 5468 | { PseudoVOR_VV_M2, 2216 }, |
| 5469 | { PseudoVOR_VV_M4, 2217 }, |
| 5470 | { PseudoVOR_VV_M8, 2218 }, |
| 5471 | { PseudoVOR_VV_MF2, 2219 }, |
| 5472 | { PseudoVOR_VV_MF4, 2220 }, |
| 5473 | { PseudoVOR_VV_MF8, 2221 }, |
| 5474 | { PseudoVOR_VX_M1, 2222 }, |
| 5475 | { PseudoVOR_VX_M2, 2223 }, |
| 5476 | { PseudoVOR_VX_M4, 2224 }, |
| 5477 | { PseudoVOR_VX_M8, 2225 }, |
| 5478 | { PseudoVOR_VX_MF2, 2226 }, |
| 5479 | { PseudoVOR_VX_MF4, 2227 }, |
| 5480 | { PseudoVOR_VX_MF8, 2228 }, |
| 5481 | { PseudoVREDAND_VS_M1_E16, 2229 }, |
| 5482 | { PseudoVREDAND_VS_M1_E32, 2230 }, |
| 5483 | { PseudoVREDAND_VS_M1_E64, 2231 }, |
| 5484 | { PseudoVREDAND_VS_M1_E8, 2232 }, |
| 5485 | { PseudoVREDAND_VS_M2_E16, 2233 }, |
| 5486 | { PseudoVREDAND_VS_M2_E32, 2234 }, |
| 5487 | { PseudoVREDAND_VS_M2_E64, 2235 }, |
| 5488 | { PseudoVREDAND_VS_M2_E8, 2236 }, |
| 5489 | { PseudoVREDAND_VS_M4_E16, 2237 }, |
| 5490 | { PseudoVREDAND_VS_M4_E32, 2238 }, |
| 5491 | { PseudoVREDAND_VS_M4_E64, 2239 }, |
| 5492 | { PseudoVREDAND_VS_M4_E8, 2240 }, |
| 5493 | { PseudoVREDAND_VS_M8_E16, 2241 }, |
| 5494 | { PseudoVREDAND_VS_M8_E32, 2242 }, |
| 5495 | { PseudoVREDAND_VS_M8_E64, 2243 }, |
| 5496 | { PseudoVREDAND_VS_M8_E8, 2244 }, |
| 5497 | { PseudoVREDAND_VS_MF2_E16, 2245 }, |
| 5498 | { PseudoVREDAND_VS_MF2_E32, 2246 }, |
| 5499 | { PseudoVREDAND_VS_MF2_E8, 2247 }, |
| 5500 | { PseudoVREDAND_VS_MF4_E16, 2248 }, |
| 5501 | { PseudoVREDAND_VS_MF4_E8, 2249 }, |
| 5502 | { PseudoVREDAND_VS_MF8_E8, 2250 }, |
| 5503 | { PseudoVREDMAXU_VS_M1_E16, 2251 }, |
| 5504 | { PseudoVREDMAXU_VS_M1_E32, 2252 }, |
| 5505 | { PseudoVREDMAXU_VS_M1_E64, 2253 }, |
| 5506 | { PseudoVREDMAXU_VS_M1_E8, 2254 }, |
| 5507 | { PseudoVREDMAXU_VS_M2_E16, 2255 }, |
| 5508 | { PseudoVREDMAXU_VS_M2_E32, 2256 }, |
| 5509 | { PseudoVREDMAXU_VS_M2_E64, 2257 }, |
| 5510 | { PseudoVREDMAXU_VS_M2_E8, 2258 }, |
| 5511 | { PseudoVREDMAXU_VS_M4_E16, 2259 }, |
| 5512 | { PseudoVREDMAXU_VS_M4_E32, 2260 }, |
| 5513 | { PseudoVREDMAXU_VS_M4_E64, 2261 }, |
| 5514 | { PseudoVREDMAXU_VS_M4_E8, 2262 }, |
| 5515 | { PseudoVREDMAXU_VS_M8_E16, 2263 }, |
| 5516 | { PseudoVREDMAXU_VS_M8_E32, 2264 }, |
| 5517 | { PseudoVREDMAXU_VS_M8_E64, 2265 }, |
| 5518 | { PseudoVREDMAXU_VS_M8_E8, 2266 }, |
| 5519 | { PseudoVREDMAXU_VS_MF2_E16, 2267 }, |
| 5520 | { PseudoVREDMAXU_VS_MF2_E32, 2268 }, |
| 5521 | { PseudoVREDMAXU_VS_MF2_E8, 2269 }, |
| 5522 | { PseudoVREDMAXU_VS_MF4_E16, 2270 }, |
| 5523 | { PseudoVREDMAXU_VS_MF4_E8, 2271 }, |
| 5524 | { PseudoVREDMAXU_VS_MF8_E8, 2272 }, |
| 5525 | { PseudoVREDMAX_VS_M1_E16, 2273 }, |
| 5526 | { PseudoVREDMAX_VS_M1_E32, 2274 }, |
| 5527 | { PseudoVREDMAX_VS_M1_E64, 2275 }, |
| 5528 | { PseudoVREDMAX_VS_M1_E8, 2276 }, |
| 5529 | { PseudoVREDMAX_VS_M2_E16, 2277 }, |
| 5530 | { PseudoVREDMAX_VS_M2_E32, 2278 }, |
| 5531 | { PseudoVREDMAX_VS_M2_E64, 2279 }, |
| 5532 | { PseudoVREDMAX_VS_M2_E8, 2280 }, |
| 5533 | { PseudoVREDMAX_VS_M4_E16, 2281 }, |
| 5534 | { PseudoVREDMAX_VS_M4_E32, 2282 }, |
| 5535 | { PseudoVREDMAX_VS_M4_E64, 2283 }, |
| 5536 | { PseudoVREDMAX_VS_M4_E8, 2284 }, |
| 5537 | { PseudoVREDMAX_VS_M8_E16, 2285 }, |
| 5538 | { PseudoVREDMAX_VS_M8_E32, 2286 }, |
| 5539 | { PseudoVREDMAX_VS_M8_E64, 2287 }, |
| 5540 | { PseudoVREDMAX_VS_M8_E8, 2288 }, |
| 5541 | { PseudoVREDMAX_VS_MF2_E16, 2289 }, |
| 5542 | { PseudoVREDMAX_VS_MF2_E32, 2290 }, |
| 5543 | { PseudoVREDMAX_VS_MF2_E8, 2291 }, |
| 5544 | { PseudoVREDMAX_VS_MF4_E16, 2292 }, |
| 5545 | { PseudoVREDMAX_VS_MF4_E8, 2293 }, |
| 5546 | { PseudoVREDMAX_VS_MF8_E8, 2294 }, |
| 5547 | { PseudoVREDMINU_VS_M1_E16, 2295 }, |
| 5548 | { PseudoVREDMINU_VS_M1_E32, 2296 }, |
| 5549 | { PseudoVREDMINU_VS_M1_E64, 2297 }, |
| 5550 | { PseudoVREDMINU_VS_M1_E8, 2298 }, |
| 5551 | { PseudoVREDMINU_VS_M2_E16, 2299 }, |
| 5552 | { PseudoVREDMINU_VS_M2_E32, 2300 }, |
| 5553 | { PseudoVREDMINU_VS_M2_E64, 2301 }, |
| 5554 | { PseudoVREDMINU_VS_M2_E8, 2302 }, |
| 5555 | { PseudoVREDMINU_VS_M4_E16, 2303 }, |
| 5556 | { PseudoVREDMINU_VS_M4_E32, 2304 }, |
| 5557 | { PseudoVREDMINU_VS_M4_E64, 2305 }, |
| 5558 | { PseudoVREDMINU_VS_M4_E8, 2306 }, |
| 5559 | { PseudoVREDMINU_VS_M8_E16, 2307 }, |
| 5560 | { PseudoVREDMINU_VS_M8_E32, 2308 }, |
| 5561 | { PseudoVREDMINU_VS_M8_E64, 2309 }, |
| 5562 | { PseudoVREDMINU_VS_M8_E8, 2310 }, |
| 5563 | { PseudoVREDMINU_VS_MF2_E16, 2311 }, |
| 5564 | { PseudoVREDMINU_VS_MF2_E32, 2312 }, |
| 5565 | { PseudoVREDMINU_VS_MF2_E8, 2313 }, |
| 5566 | { PseudoVREDMINU_VS_MF4_E16, 2314 }, |
| 5567 | { PseudoVREDMINU_VS_MF4_E8, 2315 }, |
| 5568 | { PseudoVREDMINU_VS_MF8_E8, 2316 }, |
| 5569 | { PseudoVREDMIN_VS_M1_E16, 2317 }, |
| 5570 | { PseudoVREDMIN_VS_M1_E32, 2318 }, |
| 5571 | { PseudoVREDMIN_VS_M1_E64, 2319 }, |
| 5572 | { PseudoVREDMIN_VS_M1_E8, 2320 }, |
| 5573 | { PseudoVREDMIN_VS_M2_E16, 2321 }, |
| 5574 | { PseudoVREDMIN_VS_M2_E32, 2322 }, |
| 5575 | { PseudoVREDMIN_VS_M2_E64, 2323 }, |
| 5576 | { PseudoVREDMIN_VS_M2_E8, 2324 }, |
| 5577 | { PseudoVREDMIN_VS_M4_E16, 2325 }, |
| 5578 | { PseudoVREDMIN_VS_M4_E32, 2326 }, |
| 5579 | { PseudoVREDMIN_VS_M4_E64, 2327 }, |
| 5580 | { PseudoVREDMIN_VS_M4_E8, 2328 }, |
| 5581 | { PseudoVREDMIN_VS_M8_E16, 2329 }, |
| 5582 | { PseudoVREDMIN_VS_M8_E32, 2330 }, |
| 5583 | { PseudoVREDMIN_VS_M8_E64, 2331 }, |
| 5584 | { PseudoVREDMIN_VS_M8_E8, 2332 }, |
| 5585 | { PseudoVREDMIN_VS_MF2_E16, 2333 }, |
| 5586 | { PseudoVREDMIN_VS_MF2_E32, 2334 }, |
| 5587 | { PseudoVREDMIN_VS_MF2_E8, 2335 }, |
| 5588 | { PseudoVREDMIN_VS_MF4_E16, 2336 }, |
| 5589 | { PseudoVREDMIN_VS_MF4_E8, 2337 }, |
| 5590 | { PseudoVREDMIN_VS_MF8_E8, 2338 }, |
| 5591 | { PseudoVREDOR_VS_M1_E16, 2339 }, |
| 5592 | { PseudoVREDOR_VS_M1_E32, 2340 }, |
| 5593 | { PseudoVREDOR_VS_M1_E64, 2341 }, |
| 5594 | { PseudoVREDOR_VS_M1_E8, 2342 }, |
| 5595 | { PseudoVREDOR_VS_M2_E16, 2343 }, |
| 5596 | { PseudoVREDOR_VS_M2_E32, 2344 }, |
| 5597 | { PseudoVREDOR_VS_M2_E64, 2345 }, |
| 5598 | { PseudoVREDOR_VS_M2_E8, 2346 }, |
| 5599 | { PseudoVREDOR_VS_M4_E16, 2347 }, |
| 5600 | { PseudoVREDOR_VS_M4_E32, 2348 }, |
| 5601 | { PseudoVREDOR_VS_M4_E64, 2349 }, |
| 5602 | { PseudoVREDOR_VS_M4_E8, 2350 }, |
| 5603 | { PseudoVREDOR_VS_M8_E16, 2351 }, |
| 5604 | { PseudoVREDOR_VS_M8_E32, 2352 }, |
| 5605 | { PseudoVREDOR_VS_M8_E64, 2353 }, |
| 5606 | { PseudoVREDOR_VS_M8_E8, 2354 }, |
| 5607 | { PseudoVREDOR_VS_MF2_E16, 2355 }, |
| 5608 | { PseudoVREDOR_VS_MF2_E32, 2356 }, |
| 5609 | { PseudoVREDOR_VS_MF2_E8, 2357 }, |
| 5610 | { PseudoVREDOR_VS_MF4_E16, 2358 }, |
| 5611 | { PseudoVREDOR_VS_MF4_E8, 2359 }, |
| 5612 | { PseudoVREDOR_VS_MF8_E8, 2360 }, |
| 5613 | { PseudoVREDSUM_VS_M1_E16, 2361 }, |
| 5614 | { PseudoVREDSUM_VS_M1_E32, 2362 }, |
| 5615 | { PseudoVREDSUM_VS_M1_E64, 2363 }, |
| 5616 | { PseudoVREDSUM_VS_M1_E8, 2364 }, |
| 5617 | { PseudoVREDSUM_VS_M2_E16, 2365 }, |
| 5618 | { PseudoVREDSUM_VS_M2_E32, 2366 }, |
| 5619 | { PseudoVREDSUM_VS_M2_E64, 2367 }, |
| 5620 | { PseudoVREDSUM_VS_M2_E8, 2368 }, |
| 5621 | { PseudoVREDSUM_VS_M4_E16, 2369 }, |
| 5622 | { PseudoVREDSUM_VS_M4_E32, 2370 }, |
| 5623 | { PseudoVREDSUM_VS_M4_E64, 2371 }, |
| 5624 | { PseudoVREDSUM_VS_M4_E8, 2372 }, |
| 5625 | { PseudoVREDSUM_VS_M8_E16, 2373 }, |
| 5626 | { PseudoVREDSUM_VS_M8_E32, 2374 }, |
| 5627 | { PseudoVREDSUM_VS_M8_E64, 2375 }, |
| 5628 | { PseudoVREDSUM_VS_M8_E8, 2376 }, |
| 5629 | { PseudoVREDSUM_VS_MF2_E16, 2377 }, |
| 5630 | { PseudoVREDSUM_VS_MF2_E32, 2378 }, |
| 5631 | { PseudoVREDSUM_VS_MF2_E8, 2379 }, |
| 5632 | { PseudoVREDSUM_VS_MF4_E16, 2380 }, |
| 5633 | { PseudoVREDSUM_VS_MF4_E8, 2381 }, |
| 5634 | { PseudoVREDSUM_VS_MF8_E8, 2382 }, |
| 5635 | { PseudoVREDXOR_VS_M1_E16, 2383 }, |
| 5636 | { PseudoVREDXOR_VS_M1_E32, 2384 }, |
| 5637 | { PseudoVREDXOR_VS_M1_E64, 2385 }, |
| 5638 | { PseudoVREDXOR_VS_M1_E8, 2386 }, |
| 5639 | { PseudoVREDXOR_VS_M2_E16, 2387 }, |
| 5640 | { PseudoVREDXOR_VS_M2_E32, 2388 }, |
| 5641 | { PseudoVREDXOR_VS_M2_E64, 2389 }, |
| 5642 | { PseudoVREDXOR_VS_M2_E8, 2390 }, |
| 5643 | { PseudoVREDXOR_VS_M4_E16, 2391 }, |
| 5644 | { PseudoVREDXOR_VS_M4_E32, 2392 }, |
| 5645 | { PseudoVREDXOR_VS_M4_E64, 2393 }, |
| 5646 | { PseudoVREDXOR_VS_M4_E8, 2394 }, |
| 5647 | { PseudoVREDXOR_VS_M8_E16, 2395 }, |
| 5648 | { PseudoVREDXOR_VS_M8_E32, 2396 }, |
| 5649 | { PseudoVREDXOR_VS_M8_E64, 2397 }, |
| 5650 | { PseudoVREDXOR_VS_M8_E8, 2398 }, |
| 5651 | { PseudoVREDXOR_VS_MF2_E16, 2399 }, |
| 5652 | { PseudoVREDXOR_VS_MF2_E32, 2400 }, |
| 5653 | { PseudoVREDXOR_VS_MF2_E8, 2401 }, |
| 5654 | { PseudoVREDXOR_VS_MF4_E16, 2402 }, |
| 5655 | { PseudoVREDXOR_VS_MF4_E8, 2403 }, |
| 5656 | { PseudoVREDXOR_VS_MF8_E8, 2404 }, |
| 5657 | { PseudoVREMU_VV_M1_E16, 2405 }, |
| 5658 | { PseudoVREMU_VV_M1_E32, 2406 }, |
| 5659 | { PseudoVREMU_VV_M1_E64, 2407 }, |
| 5660 | { PseudoVREMU_VV_M1_E8, 2408 }, |
| 5661 | { PseudoVREMU_VV_M2_E16, 2409 }, |
| 5662 | { PseudoVREMU_VV_M2_E32, 2410 }, |
| 5663 | { PseudoVREMU_VV_M2_E64, 2411 }, |
| 5664 | { PseudoVREMU_VV_M2_E8, 2412 }, |
| 5665 | { PseudoVREMU_VV_M4_E16, 2413 }, |
| 5666 | { PseudoVREMU_VV_M4_E32, 2414 }, |
| 5667 | { PseudoVREMU_VV_M4_E64, 2415 }, |
| 5668 | { PseudoVREMU_VV_M4_E8, 2416 }, |
| 5669 | { PseudoVREMU_VV_M8_E16, 2417 }, |
| 5670 | { PseudoVREMU_VV_M8_E32, 2418 }, |
| 5671 | { PseudoVREMU_VV_M8_E64, 2419 }, |
| 5672 | { PseudoVREMU_VV_M8_E8, 2420 }, |
| 5673 | { PseudoVREMU_VV_MF2_E16, 2421 }, |
| 5674 | { PseudoVREMU_VV_MF2_E32, 2422 }, |
| 5675 | { PseudoVREMU_VV_MF2_E8, 2423 }, |
| 5676 | { PseudoVREMU_VV_MF4_E16, 2424 }, |
| 5677 | { PseudoVREMU_VV_MF4_E8, 2425 }, |
| 5678 | { PseudoVREMU_VV_MF8_E8, 2426 }, |
| 5679 | { PseudoVREMU_VX_M1_E16, 2427 }, |
| 5680 | { PseudoVREMU_VX_M1_E32, 2428 }, |
| 5681 | { PseudoVREMU_VX_M1_E64, 2429 }, |
| 5682 | { PseudoVREMU_VX_M1_E8, 2430 }, |
| 5683 | { PseudoVREMU_VX_M2_E16, 2431 }, |
| 5684 | { PseudoVREMU_VX_M2_E32, 2432 }, |
| 5685 | { PseudoVREMU_VX_M2_E64, 2433 }, |
| 5686 | { PseudoVREMU_VX_M2_E8, 2434 }, |
| 5687 | { PseudoVREMU_VX_M4_E16, 2435 }, |
| 5688 | { PseudoVREMU_VX_M4_E32, 2436 }, |
| 5689 | { PseudoVREMU_VX_M4_E64, 2437 }, |
| 5690 | { PseudoVREMU_VX_M4_E8, 2438 }, |
| 5691 | { PseudoVREMU_VX_M8_E16, 2439 }, |
| 5692 | { PseudoVREMU_VX_M8_E32, 2440 }, |
| 5693 | { PseudoVREMU_VX_M8_E64, 2441 }, |
| 5694 | { PseudoVREMU_VX_M8_E8, 2442 }, |
| 5695 | { PseudoVREMU_VX_MF2_E16, 2443 }, |
| 5696 | { PseudoVREMU_VX_MF2_E32, 2444 }, |
| 5697 | { PseudoVREMU_VX_MF2_E8, 2445 }, |
| 5698 | { PseudoVREMU_VX_MF4_E16, 2446 }, |
| 5699 | { PseudoVREMU_VX_MF4_E8, 2447 }, |
| 5700 | { PseudoVREMU_VX_MF8_E8, 2448 }, |
| 5701 | { PseudoVREM_VV_M1_E16, 2449 }, |
| 5702 | { PseudoVREM_VV_M1_E32, 2450 }, |
| 5703 | { PseudoVREM_VV_M1_E64, 2451 }, |
| 5704 | { PseudoVREM_VV_M1_E8, 2452 }, |
| 5705 | { PseudoVREM_VV_M2_E16, 2453 }, |
| 5706 | { PseudoVREM_VV_M2_E32, 2454 }, |
| 5707 | { PseudoVREM_VV_M2_E64, 2455 }, |
| 5708 | { PseudoVREM_VV_M2_E8, 2456 }, |
| 5709 | { PseudoVREM_VV_M4_E16, 2457 }, |
| 5710 | { PseudoVREM_VV_M4_E32, 2458 }, |
| 5711 | { PseudoVREM_VV_M4_E64, 2459 }, |
| 5712 | { PseudoVREM_VV_M4_E8, 2460 }, |
| 5713 | { PseudoVREM_VV_M8_E16, 2461 }, |
| 5714 | { PseudoVREM_VV_M8_E32, 2462 }, |
| 5715 | { PseudoVREM_VV_M8_E64, 2463 }, |
| 5716 | { PseudoVREM_VV_M8_E8, 2464 }, |
| 5717 | { PseudoVREM_VV_MF2_E16, 2465 }, |
| 5718 | { PseudoVREM_VV_MF2_E32, 2466 }, |
| 5719 | { PseudoVREM_VV_MF2_E8, 2467 }, |
| 5720 | { PseudoVREM_VV_MF4_E16, 2468 }, |
| 5721 | { PseudoVREM_VV_MF4_E8, 2469 }, |
| 5722 | { PseudoVREM_VV_MF8_E8, 2470 }, |
| 5723 | { PseudoVREM_VX_M1_E16, 2471 }, |
| 5724 | { PseudoVREM_VX_M1_E32, 2472 }, |
| 5725 | { PseudoVREM_VX_M1_E64, 2473 }, |
| 5726 | { PseudoVREM_VX_M1_E8, 2474 }, |
| 5727 | { PseudoVREM_VX_M2_E16, 2475 }, |
| 5728 | { PseudoVREM_VX_M2_E32, 2476 }, |
| 5729 | { PseudoVREM_VX_M2_E64, 2477 }, |
| 5730 | { PseudoVREM_VX_M2_E8, 2478 }, |
| 5731 | { PseudoVREM_VX_M4_E16, 2479 }, |
| 5732 | { PseudoVREM_VX_M4_E32, 2480 }, |
| 5733 | { PseudoVREM_VX_M4_E64, 2481 }, |
| 5734 | { PseudoVREM_VX_M4_E8, 2482 }, |
| 5735 | { PseudoVREM_VX_M8_E16, 2483 }, |
| 5736 | { PseudoVREM_VX_M8_E32, 2484 }, |
| 5737 | { PseudoVREM_VX_M8_E64, 2485 }, |
| 5738 | { PseudoVREM_VX_M8_E8, 2486 }, |
| 5739 | { PseudoVREM_VX_MF2_E16, 2487 }, |
| 5740 | { PseudoVREM_VX_MF2_E32, 2488 }, |
| 5741 | { PseudoVREM_VX_MF2_E8, 2489 }, |
| 5742 | { PseudoVREM_VX_MF4_E16, 2490 }, |
| 5743 | { PseudoVREM_VX_MF4_E8, 2491 }, |
| 5744 | { PseudoVREM_VX_MF8_E8, 2492 }, |
| 5745 | { PseudoVREV8_V_M1, 2493 }, |
| 5746 | { PseudoVREV8_V_M2, 2494 }, |
| 5747 | { PseudoVREV8_V_M4, 2495 }, |
| 5748 | { PseudoVREV8_V_M8, 2496 }, |
| 5749 | { PseudoVREV8_V_MF2, 2497 }, |
| 5750 | { PseudoVREV8_V_MF4, 2498 }, |
| 5751 | { PseudoVREV8_V_MF8, 2499 }, |
| 5752 | { PseudoVRGATHEREI16_VV_M1_E16_M1, 2500 }, |
| 5753 | { PseudoVRGATHEREI16_VV_M1_E16_M2, 2501 }, |
| 5754 | { PseudoVRGATHEREI16_VV_M1_E16_MF2, 2502 }, |
| 5755 | { PseudoVRGATHEREI16_VV_M1_E16_MF4, 2503 }, |
| 5756 | { PseudoVRGATHEREI16_VV_M1_E32_M1, 2504 }, |
| 5757 | { PseudoVRGATHEREI16_VV_M1_E32_M2, 2505 }, |
| 5758 | { PseudoVRGATHEREI16_VV_M1_E32_MF2, 2506 }, |
| 5759 | { PseudoVRGATHEREI16_VV_M1_E32_MF4, 2507 }, |
| 5760 | { PseudoVRGATHEREI16_VV_M1_E64_M1, 2508 }, |
| 5761 | { PseudoVRGATHEREI16_VV_M1_E64_M2, 2509 }, |
| 5762 | { PseudoVRGATHEREI16_VV_M1_E64_MF2, 2510 }, |
| 5763 | { PseudoVRGATHEREI16_VV_M1_E64_MF4, 2511 }, |
| 5764 | { PseudoVRGATHEREI16_VV_M1_E8_M1, 2512 }, |
| 5765 | { PseudoVRGATHEREI16_VV_M1_E8_M2, 2513 }, |
| 5766 | { PseudoVRGATHEREI16_VV_M1_E8_MF2, 2514 }, |
| 5767 | { PseudoVRGATHEREI16_VV_M1_E8_MF4, 2515 }, |
| 5768 | { PseudoVRGATHEREI16_VV_M2_E16_M1, 2516 }, |
| 5769 | { PseudoVRGATHEREI16_VV_M2_E16_M2, 2517 }, |
| 5770 | { PseudoVRGATHEREI16_VV_M2_E16_M4, 2518 }, |
| 5771 | { PseudoVRGATHEREI16_VV_M2_E16_MF2, 2519 }, |
| 5772 | { PseudoVRGATHEREI16_VV_M2_E32_M1, 2520 }, |
| 5773 | { PseudoVRGATHEREI16_VV_M2_E32_M2, 2521 }, |
| 5774 | { PseudoVRGATHEREI16_VV_M2_E32_M4, 2522 }, |
| 5775 | { PseudoVRGATHEREI16_VV_M2_E32_MF2, 2523 }, |
| 5776 | { PseudoVRGATHEREI16_VV_M2_E64_M1, 2524 }, |
| 5777 | { PseudoVRGATHEREI16_VV_M2_E64_M2, 2525 }, |
| 5778 | { PseudoVRGATHEREI16_VV_M2_E64_M4, 2526 }, |
| 5779 | { PseudoVRGATHEREI16_VV_M2_E64_MF2, 2527 }, |
| 5780 | { PseudoVRGATHEREI16_VV_M2_E8_M1, 2528 }, |
| 5781 | { PseudoVRGATHEREI16_VV_M2_E8_M2, 2529 }, |
| 5782 | { PseudoVRGATHEREI16_VV_M2_E8_M4, 2530 }, |
| 5783 | { PseudoVRGATHEREI16_VV_M2_E8_MF2, 2531 }, |
| 5784 | { PseudoVRGATHEREI16_VV_M4_E16_M1, 2532 }, |
| 5785 | { PseudoVRGATHEREI16_VV_M4_E16_M2, 2533 }, |
| 5786 | { PseudoVRGATHEREI16_VV_M4_E16_M4, 2534 }, |
| 5787 | { PseudoVRGATHEREI16_VV_M4_E16_M8, 2535 }, |
| 5788 | { PseudoVRGATHEREI16_VV_M4_E32_M1, 2536 }, |
| 5789 | { PseudoVRGATHEREI16_VV_M4_E32_M2, 2537 }, |
| 5790 | { PseudoVRGATHEREI16_VV_M4_E32_M4, 2538 }, |
| 5791 | { PseudoVRGATHEREI16_VV_M4_E32_M8, 2539 }, |
| 5792 | { PseudoVRGATHEREI16_VV_M4_E64_M1, 2540 }, |
| 5793 | { PseudoVRGATHEREI16_VV_M4_E64_M2, 2541 }, |
| 5794 | { PseudoVRGATHEREI16_VV_M4_E64_M4, 2542 }, |
| 5795 | { PseudoVRGATHEREI16_VV_M4_E64_M8, 2543 }, |
| 5796 | { PseudoVRGATHEREI16_VV_M4_E8_M1, 2544 }, |
| 5797 | { PseudoVRGATHEREI16_VV_M4_E8_M2, 2545 }, |
| 5798 | { PseudoVRGATHEREI16_VV_M4_E8_M4, 2546 }, |
| 5799 | { PseudoVRGATHEREI16_VV_M4_E8_M8, 2547 }, |
| 5800 | { PseudoVRGATHEREI16_VV_M8_E16_M2, 2548 }, |
| 5801 | { PseudoVRGATHEREI16_VV_M8_E16_M4, 2549 }, |
| 5802 | { PseudoVRGATHEREI16_VV_M8_E16_M8, 2550 }, |
| 5803 | { PseudoVRGATHEREI16_VV_M8_E32_M2, 2551 }, |
| 5804 | { PseudoVRGATHEREI16_VV_M8_E32_M4, 2552 }, |
| 5805 | { PseudoVRGATHEREI16_VV_M8_E32_M8, 2553 }, |
| 5806 | { PseudoVRGATHEREI16_VV_M8_E64_M2, 2554 }, |
| 5807 | { PseudoVRGATHEREI16_VV_M8_E64_M4, 2555 }, |
| 5808 | { PseudoVRGATHEREI16_VV_M8_E64_M8, 2556 }, |
| 5809 | { PseudoVRGATHEREI16_VV_M8_E8_M2, 2557 }, |
| 5810 | { PseudoVRGATHEREI16_VV_M8_E8_M4, 2558 }, |
| 5811 | { PseudoVRGATHEREI16_VV_M8_E8_M8, 2559 }, |
| 5812 | { PseudoVRGATHEREI16_VV_MF2_E16_M1, 2560 }, |
| 5813 | { PseudoVRGATHEREI16_VV_MF2_E16_MF2, 2561 }, |
| 5814 | { PseudoVRGATHEREI16_VV_MF2_E16_MF4, 2562 }, |
| 5815 | { PseudoVRGATHEREI16_VV_MF2_E16_MF8, 2563 }, |
| 5816 | { PseudoVRGATHEREI16_VV_MF2_E32_M1, 2564 }, |
| 5817 | { PseudoVRGATHEREI16_VV_MF2_E32_MF2, 2565 }, |
| 5818 | { PseudoVRGATHEREI16_VV_MF2_E32_MF4, 2566 }, |
| 5819 | { PseudoVRGATHEREI16_VV_MF2_E32_MF8, 2567 }, |
| 5820 | { PseudoVRGATHEREI16_VV_MF2_E8_M1, 2568 }, |
| 5821 | { PseudoVRGATHEREI16_VV_MF2_E8_MF2, 2569 }, |
| 5822 | { PseudoVRGATHEREI16_VV_MF2_E8_MF4, 2570 }, |
| 5823 | { PseudoVRGATHEREI16_VV_MF2_E8_MF8, 2571 }, |
| 5824 | { PseudoVRGATHEREI16_VV_MF4_E16_MF2, 2572 }, |
| 5825 | { PseudoVRGATHEREI16_VV_MF4_E16_MF4, 2573 }, |
| 5826 | { PseudoVRGATHEREI16_VV_MF4_E16_MF8, 2574 }, |
| 5827 | { PseudoVRGATHEREI16_VV_MF4_E8_MF2, 2575 }, |
| 5828 | { PseudoVRGATHEREI16_VV_MF4_E8_MF4, 2576 }, |
| 5829 | { PseudoVRGATHEREI16_VV_MF4_E8_MF8, 2577 }, |
| 5830 | { PseudoVRGATHEREI16_VV_MF8_E8_MF4, 2578 }, |
| 5831 | { PseudoVRGATHEREI16_VV_MF8_E8_MF8, 2579 }, |
| 5832 | { PseudoVRGATHER_VI_M1, 2580 }, |
| 5833 | { PseudoVRGATHER_VI_M2, 2581 }, |
| 5834 | { PseudoVRGATHER_VI_M4, 2582 }, |
| 5835 | { PseudoVRGATHER_VI_M8, 2583 }, |
| 5836 | { PseudoVRGATHER_VI_MF2, 2584 }, |
| 5837 | { PseudoVRGATHER_VI_MF4, 2585 }, |
| 5838 | { PseudoVRGATHER_VI_MF8, 2586 }, |
| 5839 | { PseudoVRGATHER_VV_M1_E16, 2587 }, |
| 5840 | { PseudoVRGATHER_VV_M1_E32, 2588 }, |
| 5841 | { PseudoVRGATHER_VV_M1_E64, 2589 }, |
| 5842 | { PseudoVRGATHER_VV_M1_E8, 2590 }, |
| 5843 | { PseudoVRGATHER_VV_M2_E16, 2591 }, |
| 5844 | { PseudoVRGATHER_VV_M2_E32, 2592 }, |
| 5845 | { PseudoVRGATHER_VV_M2_E64, 2593 }, |
| 5846 | { PseudoVRGATHER_VV_M2_E8, 2594 }, |
| 5847 | { PseudoVRGATHER_VV_M4_E16, 2595 }, |
| 5848 | { PseudoVRGATHER_VV_M4_E32, 2596 }, |
| 5849 | { PseudoVRGATHER_VV_M4_E64, 2597 }, |
| 5850 | { PseudoVRGATHER_VV_M4_E8, 2598 }, |
| 5851 | { PseudoVRGATHER_VV_M8_E16, 2599 }, |
| 5852 | { PseudoVRGATHER_VV_M8_E32, 2600 }, |
| 5853 | { PseudoVRGATHER_VV_M8_E64, 2601 }, |
| 5854 | { PseudoVRGATHER_VV_M8_E8, 2602 }, |
| 5855 | { PseudoVRGATHER_VV_MF2_E16, 2603 }, |
| 5856 | { PseudoVRGATHER_VV_MF2_E32, 2604 }, |
| 5857 | { PseudoVRGATHER_VV_MF2_E8, 2605 }, |
| 5858 | { PseudoVRGATHER_VV_MF4_E16, 2606 }, |
| 5859 | { PseudoVRGATHER_VV_MF4_E8, 2607 }, |
| 5860 | { PseudoVRGATHER_VV_MF8_E8, 2608 }, |
| 5861 | { PseudoVRGATHER_VX_M1, 2609 }, |
| 5862 | { PseudoVRGATHER_VX_M2, 2610 }, |
| 5863 | { PseudoVRGATHER_VX_M4, 2611 }, |
| 5864 | { PseudoVRGATHER_VX_M8, 2612 }, |
| 5865 | { PseudoVRGATHER_VX_MF2, 2613 }, |
| 5866 | { PseudoVRGATHER_VX_MF4, 2614 }, |
| 5867 | { PseudoVRGATHER_VX_MF8, 2615 }, |
| 5868 | { PseudoVROL_VV_M1, 2616 }, |
| 5869 | { PseudoVROL_VV_M2, 2617 }, |
| 5870 | { PseudoVROL_VV_M4, 2618 }, |
| 5871 | { PseudoVROL_VV_M8, 2619 }, |
| 5872 | { PseudoVROL_VV_MF2, 2620 }, |
| 5873 | { PseudoVROL_VV_MF4, 2621 }, |
| 5874 | { PseudoVROL_VV_MF8, 2622 }, |
| 5875 | { PseudoVROL_VX_M1, 2623 }, |
| 5876 | { PseudoVROL_VX_M2, 2624 }, |
| 5877 | { PseudoVROL_VX_M4, 2625 }, |
| 5878 | { PseudoVROL_VX_M8, 2626 }, |
| 5879 | { PseudoVROL_VX_MF2, 2627 }, |
| 5880 | { PseudoVROL_VX_MF4, 2628 }, |
| 5881 | { PseudoVROL_VX_MF8, 2629 }, |
| 5882 | { PseudoVROR_VI_M1, 2630 }, |
| 5883 | { PseudoVROR_VI_M2, 2631 }, |
| 5884 | { PseudoVROR_VI_M4, 2632 }, |
| 5885 | { PseudoVROR_VI_M8, 2633 }, |
| 5886 | { PseudoVROR_VI_MF2, 2634 }, |
| 5887 | { PseudoVROR_VI_MF4, 2635 }, |
| 5888 | { PseudoVROR_VI_MF8, 2636 }, |
| 5889 | { PseudoVROR_VV_M1, 2637 }, |
| 5890 | { PseudoVROR_VV_M2, 2638 }, |
| 5891 | { PseudoVROR_VV_M4, 2639 }, |
| 5892 | { PseudoVROR_VV_M8, 2640 }, |
| 5893 | { PseudoVROR_VV_MF2, 2641 }, |
| 5894 | { PseudoVROR_VV_MF4, 2642 }, |
| 5895 | { PseudoVROR_VV_MF8, 2643 }, |
| 5896 | { PseudoVROR_VX_M1, 2644 }, |
| 5897 | { PseudoVROR_VX_M2, 2645 }, |
| 5898 | { PseudoVROR_VX_M4, 2646 }, |
| 5899 | { PseudoVROR_VX_M8, 2647 }, |
| 5900 | { PseudoVROR_VX_MF2, 2648 }, |
| 5901 | { PseudoVROR_VX_MF4, 2649 }, |
| 5902 | { PseudoVROR_VX_MF8, 2650 }, |
| 5903 | { PseudoVRSUB_VI_M1, 2651 }, |
| 5904 | { PseudoVRSUB_VI_M2, 2652 }, |
| 5905 | { PseudoVRSUB_VI_M4, 2653 }, |
| 5906 | { PseudoVRSUB_VI_M8, 2654 }, |
| 5907 | { PseudoVRSUB_VI_MF2, 2655 }, |
| 5908 | { PseudoVRSUB_VI_MF4, 2656 }, |
| 5909 | { PseudoVRSUB_VI_MF8, 2657 }, |
| 5910 | { PseudoVRSUB_VX_M1, 2658 }, |
| 5911 | { PseudoVRSUB_VX_M2, 2659 }, |
| 5912 | { PseudoVRSUB_VX_M4, 2660 }, |
| 5913 | { PseudoVRSUB_VX_M8, 2661 }, |
| 5914 | { PseudoVRSUB_VX_MF2, 2662 }, |
| 5915 | { PseudoVRSUB_VX_MF4, 2663 }, |
| 5916 | { PseudoVRSUB_VX_MF8, 2664 }, |
| 5917 | { PseudoVSADDU_VI_M1, 2665 }, |
| 5918 | { PseudoVSADDU_VI_M2, 2666 }, |
| 5919 | { PseudoVSADDU_VI_M4, 2667 }, |
| 5920 | { PseudoVSADDU_VI_M8, 2668 }, |
| 5921 | { PseudoVSADDU_VI_MF2, 2669 }, |
| 5922 | { PseudoVSADDU_VI_MF4, 2670 }, |
| 5923 | { PseudoVSADDU_VI_MF8, 2671 }, |
| 5924 | { PseudoVSADDU_VV_M1, 2672 }, |
| 5925 | { PseudoVSADDU_VV_M2, 2673 }, |
| 5926 | { PseudoVSADDU_VV_M4, 2674 }, |
| 5927 | { PseudoVSADDU_VV_M8, 2675 }, |
| 5928 | { PseudoVSADDU_VV_MF2, 2676 }, |
| 5929 | { PseudoVSADDU_VV_MF4, 2677 }, |
| 5930 | { PseudoVSADDU_VV_MF8, 2678 }, |
| 5931 | { PseudoVSADDU_VX_M1, 2679 }, |
| 5932 | { PseudoVSADDU_VX_M2, 2680 }, |
| 5933 | { PseudoVSADDU_VX_M4, 2681 }, |
| 5934 | { PseudoVSADDU_VX_M8, 2682 }, |
| 5935 | { PseudoVSADDU_VX_MF2, 2683 }, |
| 5936 | { PseudoVSADDU_VX_MF4, 2684 }, |
| 5937 | { PseudoVSADDU_VX_MF8, 2685 }, |
| 5938 | { PseudoVSADD_VI_M1, 2686 }, |
| 5939 | { PseudoVSADD_VI_M2, 2687 }, |
| 5940 | { PseudoVSADD_VI_M4, 2688 }, |
| 5941 | { PseudoVSADD_VI_M8, 2689 }, |
| 5942 | { PseudoVSADD_VI_MF2, 2690 }, |
| 5943 | { PseudoVSADD_VI_MF4, 2691 }, |
| 5944 | { PseudoVSADD_VI_MF8, 2692 }, |
| 5945 | { PseudoVSADD_VV_M1, 2693 }, |
| 5946 | { PseudoVSADD_VV_M2, 2694 }, |
| 5947 | { PseudoVSADD_VV_M4, 2695 }, |
| 5948 | { PseudoVSADD_VV_M8, 2696 }, |
| 5949 | { PseudoVSADD_VV_MF2, 2697 }, |
| 5950 | { PseudoVSADD_VV_MF4, 2698 }, |
| 5951 | { PseudoVSADD_VV_MF8, 2699 }, |
| 5952 | { PseudoVSADD_VX_M1, 2700 }, |
| 5953 | { PseudoVSADD_VX_M2, 2701 }, |
| 5954 | { PseudoVSADD_VX_M4, 2702 }, |
| 5955 | { PseudoVSADD_VX_M8, 2703 }, |
| 5956 | { PseudoVSADD_VX_MF2, 2704 }, |
| 5957 | { PseudoVSADD_VX_MF4, 2705 }, |
| 5958 | { PseudoVSADD_VX_MF8, 2706 }, |
| 5959 | { PseudoVSEXT_VF2_M1, 2707 }, |
| 5960 | { PseudoVSEXT_VF2_M2, 2708 }, |
| 5961 | { PseudoVSEXT_VF2_M4, 2709 }, |
| 5962 | { PseudoVSEXT_VF2_M8, 2710 }, |
| 5963 | { PseudoVSEXT_VF2_MF2, 2711 }, |
| 5964 | { PseudoVSEXT_VF2_MF4, 2712 }, |
| 5965 | { PseudoVSEXT_VF4_M1, 2713 }, |
| 5966 | { PseudoVSEXT_VF4_M2, 2714 }, |
| 5967 | { PseudoVSEXT_VF4_M4, 2715 }, |
| 5968 | { PseudoVSEXT_VF4_M8, 2716 }, |
| 5969 | { PseudoVSEXT_VF4_MF2, 2717 }, |
| 5970 | { PseudoVSEXT_VF8_M1, 2718 }, |
| 5971 | { PseudoVSEXT_VF8_M2, 2719 }, |
| 5972 | { PseudoVSEXT_VF8_M4, 2720 }, |
| 5973 | { PseudoVSEXT_VF8_M8, 2721 }, |
| 5974 | { PseudoVSLIDE1DOWN_VX_M1, 2722 }, |
| 5975 | { PseudoVSLIDE1DOWN_VX_M2, 2723 }, |
| 5976 | { PseudoVSLIDE1DOWN_VX_M4, 2724 }, |
| 5977 | { PseudoVSLIDE1DOWN_VX_M8, 2725 }, |
| 5978 | { PseudoVSLIDE1DOWN_VX_MF2, 2726 }, |
| 5979 | { PseudoVSLIDE1DOWN_VX_MF4, 2727 }, |
| 5980 | { PseudoVSLIDE1DOWN_VX_MF8, 2728 }, |
| 5981 | { PseudoVSLIDE1UP_VX_M1, 2729 }, |
| 5982 | { PseudoVSLIDE1UP_VX_M2, 2730 }, |
| 5983 | { PseudoVSLIDE1UP_VX_M4, 2731 }, |
| 5984 | { PseudoVSLIDE1UP_VX_M8, 2732 }, |
| 5985 | { PseudoVSLIDE1UP_VX_MF2, 2733 }, |
| 5986 | { PseudoVSLIDE1UP_VX_MF4, 2734 }, |
| 5987 | { PseudoVSLIDE1UP_VX_MF8, 2735 }, |
| 5988 | { PseudoVSLIDEDOWN_VI_M1, 2736 }, |
| 5989 | { PseudoVSLIDEDOWN_VI_M2, 2737 }, |
| 5990 | { PseudoVSLIDEDOWN_VI_M4, 2738 }, |
| 5991 | { PseudoVSLIDEDOWN_VI_M8, 2739 }, |
| 5992 | { PseudoVSLIDEDOWN_VI_MF2, 2740 }, |
| 5993 | { PseudoVSLIDEDOWN_VI_MF4, 2741 }, |
| 5994 | { PseudoVSLIDEDOWN_VI_MF8, 2742 }, |
| 5995 | { PseudoVSLIDEDOWN_VX_M1, 2743 }, |
| 5996 | { PseudoVSLIDEDOWN_VX_M2, 2744 }, |
| 5997 | { PseudoVSLIDEDOWN_VX_M4, 2745 }, |
| 5998 | { PseudoVSLIDEDOWN_VX_M8, 2746 }, |
| 5999 | { PseudoVSLIDEDOWN_VX_MF2, 2747 }, |
| 6000 | { PseudoVSLIDEDOWN_VX_MF4, 2748 }, |
| 6001 | { PseudoVSLIDEDOWN_VX_MF8, 2749 }, |
| 6002 | { PseudoVSLIDEUP_VI_M1, 2750 }, |
| 6003 | { PseudoVSLIDEUP_VI_M2, 2751 }, |
| 6004 | { PseudoVSLIDEUP_VI_M4, 2752 }, |
| 6005 | { PseudoVSLIDEUP_VI_M8, 2753 }, |
| 6006 | { PseudoVSLIDEUP_VI_MF2, 2754 }, |
| 6007 | { PseudoVSLIDEUP_VI_MF4, 2755 }, |
| 6008 | { PseudoVSLIDEUP_VI_MF8, 2756 }, |
| 6009 | { PseudoVSLIDEUP_VX_M1, 2757 }, |
| 6010 | { PseudoVSLIDEUP_VX_M2, 2758 }, |
| 6011 | { PseudoVSLIDEUP_VX_M4, 2759 }, |
| 6012 | { PseudoVSLIDEUP_VX_M8, 2760 }, |
| 6013 | { PseudoVSLIDEUP_VX_MF2, 2761 }, |
| 6014 | { PseudoVSLIDEUP_VX_MF4, 2762 }, |
| 6015 | { PseudoVSLIDEUP_VX_MF8, 2763 }, |
| 6016 | { PseudoVSLL_VI_M1, 2764 }, |
| 6017 | { PseudoVSLL_VI_M2, 2765 }, |
| 6018 | { PseudoVSLL_VI_M4, 2766 }, |
| 6019 | { PseudoVSLL_VI_M8, 2767 }, |
| 6020 | { PseudoVSLL_VI_MF2, 2768 }, |
| 6021 | { PseudoVSLL_VI_MF4, 2769 }, |
| 6022 | { PseudoVSLL_VI_MF8, 2770 }, |
| 6023 | { PseudoVSLL_VV_M1, 2771 }, |
| 6024 | { PseudoVSLL_VV_M2, 2772 }, |
| 6025 | { PseudoVSLL_VV_M4, 2773 }, |
| 6026 | { PseudoVSLL_VV_M8, 2774 }, |
| 6027 | { PseudoVSLL_VV_MF2, 2775 }, |
| 6028 | { PseudoVSLL_VV_MF4, 2776 }, |
| 6029 | { PseudoVSLL_VV_MF8, 2777 }, |
| 6030 | { PseudoVSLL_VX_M1, 2778 }, |
| 6031 | { PseudoVSLL_VX_M2, 2779 }, |
| 6032 | { PseudoVSLL_VX_M4, 2780 }, |
| 6033 | { PseudoVSLL_VX_M8, 2781 }, |
| 6034 | { PseudoVSLL_VX_MF2, 2782 }, |
| 6035 | { PseudoVSLL_VX_MF4, 2783 }, |
| 6036 | { PseudoVSLL_VX_MF8, 2784 }, |
| 6037 | { PseudoVSMUL_VV_M1, 2785 }, |
| 6038 | { PseudoVSMUL_VV_M2, 2786 }, |
| 6039 | { PseudoVSMUL_VV_M4, 2787 }, |
| 6040 | { PseudoVSMUL_VV_M8, 2788 }, |
| 6041 | { PseudoVSMUL_VV_MF2, 2789 }, |
| 6042 | { PseudoVSMUL_VV_MF4, 2790 }, |
| 6043 | { PseudoVSMUL_VV_MF8, 2791 }, |
| 6044 | { PseudoVSMUL_VX_M1, 2792 }, |
| 6045 | { PseudoVSMUL_VX_M2, 2793 }, |
| 6046 | { PseudoVSMUL_VX_M4, 2794 }, |
| 6047 | { PseudoVSMUL_VX_M8, 2795 }, |
| 6048 | { PseudoVSMUL_VX_MF2, 2796 }, |
| 6049 | { PseudoVSMUL_VX_MF4, 2797 }, |
| 6050 | { PseudoVSMUL_VX_MF8, 2798 }, |
| 6051 | { PseudoVSRA_VI_M1, 2799 }, |
| 6052 | { PseudoVSRA_VI_M2, 2800 }, |
| 6053 | { PseudoVSRA_VI_M4, 2801 }, |
| 6054 | { PseudoVSRA_VI_M8, 2802 }, |
| 6055 | { PseudoVSRA_VI_MF2, 2803 }, |
| 6056 | { PseudoVSRA_VI_MF4, 2804 }, |
| 6057 | { PseudoVSRA_VI_MF8, 2805 }, |
| 6058 | { PseudoVSRA_VV_M1, 2806 }, |
| 6059 | { PseudoVSRA_VV_M2, 2807 }, |
| 6060 | { PseudoVSRA_VV_M4, 2808 }, |
| 6061 | { PseudoVSRA_VV_M8, 2809 }, |
| 6062 | { PseudoVSRA_VV_MF2, 2810 }, |
| 6063 | { PseudoVSRA_VV_MF4, 2811 }, |
| 6064 | { PseudoVSRA_VV_MF8, 2812 }, |
| 6065 | { PseudoVSRA_VX_M1, 2813 }, |
| 6066 | { PseudoVSRA_VX_M2, 2814 }, |
| 6067 | { PseudoVSRA_VX_M4, 2815 }, |
| 6068 | { PseudoVSRA_VX_M8, 2816 }, |
| 6069 | { PseudoVSRA_VX_MF2, 2817 }, |
| 6070 | { PseudoVSRA_VX_MF4, 2818 }, |
| 6071 | { PseudoVSRA_VX_MF8, 2819 }, |
| 6072 | { PseudoVSRL_VI_M1, 2820 }, |
| 6073 | { PseudoVSRL_VI_M2, 2821 }, |
| 6074 | { PseudoVSRL_VI_M4, 2822 }, |
| 6075 | { PseudoVSRL_VI_M8, 2823 }, |
| 6076 | { PseudoVSRL_VI_MF2, 2824 }, |
| 6077 | { PseudoVSRL_VI_MF4, 2825 }, |
| 6078 | { PseudoVSRL_VI_MF8, 2826 }, |
| 6079 | { PseudoVSRL_VV_M1, 2827 }, |
| 6080 | { PseudoVSRL_VV_M2, 2828 }, |
| 6081 | { PseudoVSRL_VV_M4, 2829 }, |
| 6082 | { PseudoVSRL_VV_M8, 2830 }, |
| 6083 | { PseudoVSRL_VV_MF2, 2831 }, |
| 6084 | { PseudoVSRL_VV_MF4, 2832 }, |
| 6085 | { PseudoVSRL_VV_MF8, 2833 }, |
| 6086 | { PseudoVSRL_VX_M1, 2834 }, |
| 6087 | { PseudoVSRL_VX_M2, 2835 }, |
| 6088 | { PseudoVSRL_VX_M4, 2836 }, |
| 6089 | { PseudoVSRL_VX_M8, 2837 }, |
| 6090 | { PseudoVSRL_VX_MF2, 2838 }, |
| 6091 | { PseudoVSRL_VX_MF4, 2839 }, |
| 6092 | { PseudoVSRL_VX_MF8, 2840 }, |
| 6093 | { PseudoVSSRA_VI_M1, 2841 }, |
| 6094 | { PseudoVSSRA_VI_M2, 2842 }, |
| 6095 | { PseudoVSSRA_VI_M4, 2843 }, |
| 6096 | { PseudoVSSRA_VI_M8, 2844 }, |
| 6097 | { PseudoVSSRA_VI_MF2, 2845 }, |
| 6098 | { PseudoVSSRA_VI_MF4, 2846 }, |
| 6099 | { PseudoVSSRA_VI_MF8, 2847 }, |
| 6100 | { PseudoVSSRA_VV_M1, 2848 }, |
| 6101 | { PseudoVSSRA_VV_M2, 2849 }, |
| 6102 | { PseudoVSSRA_VV_M4, 2850 }, |
| 6103 | { PseudoVSSRA_VV_M8, 2851 }, |
| 6104 | { PseudoVSSRA_VV_MF2, 2852 }, |
| 6105 | { PseudoVSSRA_VV_MF4, 2853 }, |
| 6106 | { PseudoVSSRA_VV_MF8, 2854 }, |
| 6107 | { PseudoVSSRA_VX_M1, 2855 }, |
| 6108 | { PseudoVSSRA_VX_M2, 2856 }, |
| 6109 | { PseudoVSSRA_VX_M4, 2857 }, |
| 6110 | { PseudoVSSRA_VX_M8, 2858 }, |
| 6111 | { PseudoVSSRA_VX_MF2, 2859 }, |
| 6112 | { PseudoVSSRA_VX_MF4, 2860 }, |
| 6113 | { PseudoVSSRA_VX_MF8, 2861 }, |
| 6114 | { PseudoVSSRL_VI_M1, 2862 }, |
| 6115 | { PseudoVSSRL_VI_M2, 2863 }, |
| 6116 | { PseudoVSSRL_VI_M4, 2864 }, |
| 6117 | { PseudoVSSRL_VI_M8, 2865 }, |
| 6118 | { PseudoVSSRL_VI_MF2, 2866 }, |
| 6119 | { PseudoVSSRL_VI_MF4, 2867 }, |
| 6120 | { PseudoVSSRL_VI_MF8, 2868 }, |
| 6121 | { PseudoVSSRL_VV_M1, 2869 }, |
| 6122 | { PseudoVSSRL_VV_M2, 2870 }, |
| 6123 | { PseudoVSSRL_VV_M4, 2871 }, |
| 6124 | { PseudoVSSRL_VV_M8, 2872 }, |
| 6125 | { PseudoVSSRL_VV_MF2, 2873 }, |
| 6126 | { PseudoVSSRL_VV_MF4, 2874 }, |
| 6127 | { PseudoVSSRL_VV_MF8, 2875 }, |
| 6128 | { PseudoVSSRL_VX_M1, 2876 }, |
| 6129 | { PseudoVSSRL_VX_M2, 2877 }, |
| 6130 | { PseudoVSSRL_VX_M4, 2878 }, |
| 6131 | { PseudoVSSRL_VX_M8, 2879 }, |
| 6132 | { PseudoVSSRL_VX_MF2, 2880 }, |
| 6133 | { PseudoVSSRL_VX_MF4, 2881 }, |
| 6134 | { PseudoVSSRL_VX_MF8, 2882 }, |
| 6135 | { PseudoVSSUBU_VV_M1, 2883 }, |
| 6136 | { PseudoVSSUBU_VV_M2, 2884 }, |
| 6137 | { PseudoVSSUBU_VV_M4, 2885 }, |
| 6138 | { PseudoVSSUBU_VV_M8, 2886 }, |
| 6139 | { PseudoVSSUBU_VV_MF2, 2887 }, |
| 6140 | { PseudoVSSUBU_VV_MF4, 2888 }, |
| 6141 | { PseudoVSSUBU_VV_MF8, 2889 }, |
| 6142 | { PseudoVSSUBU_VX_M1, 2890 }, |
| 6143 | { PseudoVSSUBU_VX_M2, 2891 }, |
| 6144 | { PseudoVSSUBU_VX_M4, 2892 }, |
| 6145 | { PseudoVSSUBU_VX_M8, 2893 }, |
| 6146 | { PseudoVSSUBU_VX_MF2, 2894 }, |
| 6147 | { PseudoVSSUBU_VX_MF4, 2895 }, |
| 6148 | { PseudoVSSUBU_VX_MF8, 2896 }, |
| 6149 | { PseudoVSSUB_VV_M1, 2897 }, |
| 6150 | { PseudoVSSUB_VV_M2, 2898 }, |
| 6151 | { PseudoVSSUB_VV_M4, 2899 }, |
| 6152 | { PseudoVSSUB_VV_M8, 2900 }, |
| 6153 | { PseudoVSSUB_VV_MF2, 2901 }, |
| 6154 | { PseudoVSSUB_VV_MF4, 2902 }, |
| 6155 | { PseudoVSSUB_VV_MF8, 2903 }, |
| 6156 | { PseudoVSSUB_VX_M1, 2904 }, |
| 6157 | { PseudoVSSUB_VX_M2, 2905 }, |
| 6158 | { PseudoVSSUB_VX_M4, 2906 }, |
| 6159 | { PseudoVSSUB_VX_M8, 2907 }, |
| 6160 | { PseudoVSSUB_VX_MF2, 2908 }, |
| 6161 | { PseudoVSSUB_VX_MF4, 2909 }, |
| 6162 | { PseudoVSSUB_VX_MF8, 2910 }, |
| 6163 | { PseudoVSUB_VV_M1, 2911 }, |
| 6164 | { PseudoVSUB_VV_M2, 2912 }, |
| 6165 | { PseudoVSUB_VV_M4, 2913 }, |
| 6166 | { PseudoVSUB_VV_M8, 2914 }, |
| 6167 | { PseudoVSUB_VV_MF2, 2915 }, |
| 6168 | { PseudoVSUB_VV_MF4, 2916 }, |
| 6169 | { PseudoVSUB_VV_MF8, 2917 }, |
| 6170 | { PseudoVSUB_VX_M1, 2918 }, |
| 6171 | { PseudoVSUB_VX_M2, 2919 }, |
| 6172 | { PseudoVSUB_VX_M4, 2920 }, |
| 6173 | { PseudoVSUB_VX_M8, 2921 }, |
| 6174 | { PseudoVSUB_VX_MF2, 2922 }, |
| 6175 | { PseudoVSUB_VX_MF4, 2923 }, |
| 6176 | { PseudoVSUB_VX_MF8, 2924 }, |
| 6177 | { PseudoVWADDU_VV_M1, 2925 }, |
| 6178 | { PseudoVWADDU_VV_M2, 2926 }, |
| 6179 | { PseudoVWADDU_VV_M4, 2927 }, |
| 6180 | { PseudoVWADDU_VV_MF2, 2928 }, |
| 6181 | { PseudoVWADDU_VV_MF4, 2929 }, |
| 6182 | { PseudoVWADDU_VV_MF8, 2930 }, |
| 6183 | { PseudoVWADDU_VX_M1, 2931 }, |
| 6184 | { PseudoVWADDU_VX_M2, 2932 }, |
| 6185 | { PseudoVWADDU_VX_M4, 2933 }, |
| 6186 | { PseudoVWADDU_VX_MF2, 2934 }, |
| 6187 | { PseudoVWADDU_VX_MF4, 2935 }, |
| 6188 | { PseudoVWADDU_VX_MF8, 2936 }, |
| 6189 | { PseudoVWADDU_WV_M1, 2937 }, |
| 6190 | { PseudoVWADDU_WV_M1_TIED, 2938 }, |
| 6191 | { PseudoVWADDU_WV_M2, 2939 }, |
| 6192 | { PseudoVWADDU_WV_M2_TIED, 2940 }, |
| 6193 | { PseudoVWADDU_WV_M4, 2941 }, |
| 6194 | { PseudoVWADDU_WV_M4_TIED, 2942 }, |
| 6195 | { PseudoVWADDU_WV_MF2, 2943 }, |
| 6196 | { PseudoVWADDU_WV_MF2_TIED, 2944 }, |
| 6197 | { PseudoVWADDU_WV_MF4, 2945 }, |
| 6198 | { PseudoVWADDU_WV_MF4_TIED, 2946 }, |
| 6199 | { PseudoVWADDU_WV_MF8, 2947 }, |
| 6200 | { PseudoVWADDU_WV_MF8_TIED, 2948 }, |
| 6201 | { PseudoVWADDU_WX_M1, 2949 }, |
| 6202 | { PseudoVWADDU_WX_M2, 2950 }, |
| 6203 | { PseudoVWADDU_WX_M4, 2951 }, |
| 6204 | { PseudoVWADDU_WX_MF2, 2952 }, |
| 6205 | { PseudoVWADDU_WX_MF4, 2953 }, |
| 6206 | { PseudoVWADDU_WX_MF8, 2954 }, |
| 6207 | { PseudoVWADD_VV_M1, 2955 }, |
| 6208 | { PseudoVWADD_VV_M2, 2956 }, |
| 6209 | { PseudoVWADD_VV_M4, 2957 }, |
| 6210 | { PseudoVWADD_VV_MF2, 2958 }, |
| 6211 | { PseudoVWADD_VV_MF4, 2959 }, |
| 6212 | { PseudoVWADD_VV_MF8, 2960 }, |
| 6213 | { PseudoVWADD_VX_M1, 2961 }, |
| 6214 | { PseudoVWADD_VX_M2, 2962 }, |
| 6215 | { PseudoVWADD_VX_M4, 2963 }, |
| 6216 | { PseudoVWADD_VX_MF2, 2964 }, |
| 6217 | { PseudoVWADD_VX_MF4, 2965 }, |
| 6218 | { PseudoVWADD_VX_MF8, 2966 }, |
| 6219 | { PseudoVWADD_WV_M1, 2967 }, |
| 6220 | { PseudoVWADD_WV_M1_TIED, 2968 }, |
| 6221 | { PseudoVWADD_WV_M2, 2969 }, |
| 6222 | { PseudoVWADD_WV_M2_TIED, 2970 }, |
| 6223 | { PseudoVWADD_WV_M4, 2971 }, |
| 6224 | { PseudoVWADD_WV_M4_TIED, 2972 }, |
| 6225 | { PseudoVWADD_WV_MF2, 2973 }, |
| 6226 | { PseudoVWADD_WV_MF2_TIED, 2974 }, |
| 6227 | { PseudoVWADD_WV_MF4, 2975 }, |
| 6228 | { PseudoVWADD_WV_MF4_TIED, 2976 }, |
| 6229 | { PseudoVWADD_WV_MF8, 2977 }, |
| 6230 | { PseudoVWADD_WV_MF8_TIED, 2978 }, |
| 6231 | { PseudoVWADD_WX_M1, 2979 }, |
| 6232 | { PseudoVWADD_WX_M2, 2980 }, |
| 6233 | { PseudoVWADD_WX_M4, 2981 }, |
| 6234 | { PseudoVWADD_WX_MF2, 2982 }, |
| 6235 | { PseudoVWADD_WX_MF4, 2983 }, |
| 6236 | { PseudoVWADD_WX_MF8, 2984 }, |
| 6237 | { PseudoVWMACCSU_VV_M1, 2985 }, |
| 6238 | { PseudoVWMACCSU_VV_M2, 2986 }, |
| 6239 | { PseudoVWMACCSU_VV_M4, 2987 }, |
| 6240 | { PseudoVWMACCSU_VV_MF2, 2988 }, |
| 6241 | { PseudoVWMACCSU_VV_MF4, 2989 }, |
| 6242 | { PseudoVWMACCSU_VV_MF8, 2990 }, |
| 6243 | { PseudoVWMACCSU_VX_M1, 2991 }, |
| 6244 | { PseudoVWMACCSU_VX_M2, 2992 }, |
| 6245 | { PseudoVWMACCSU_VX_M4, 2993 }, |
| 6246 | { PseudoVWMACCSU_VX_MF2, 2994 }, |
| 6247 | { PseudoVWMACCSU_VX_MF4, 2995 }, |
| 6248 | { PseudoVWMACCSU_VX_MF8, 2996 }, |
| 6249 | { PseudoVWMACCUS_VX_M1, 2997 }, |
| 6250 | { PseudoVWMACCUS_VX_M2, 2998 }, |
| 6251 | { PseudoVWMACCUS_VX_M4, 2999 }, |
| 6252 | { PseudoVWMACCUS_VX_MF2, 3000 }, |
| 6253 | { PseudoVWMACCUS_VX_MF4, 3001 }, |
| 6254 | { PseudoVWMACCUS_VX_MF8, 3002 }, |
| 6255 | { PseudoVWMACCU_VV_M1, 3003 }, |
| 6256 | { PseudoVWMACCU_VV_M2, 3004 }, |
| 6257 | { PseudoVWMACCU_VV_M4, 3005 }, |
| 6258 | { PseudoVWMACCU_VV_MF2, 3006 }, |
| 6259 | { PseudoVWMACCU_VV_MF4, 3007 }, |
| 6260 | { PseudoVWMACCU_VV_MF8, 3008 }, |
| 6261 | { PseudoVWMACCU_VX_M1, 3009 }, |
| 6262 | { PseudoVWMACCU_VX_M2, 3010 }, |
| 6263 | { PseudoVWMACCU_VX_M4, 3011 }, |
| 6264 | { PseudoVWMACCU_VX_MF2, 3012 }, |
| 6265 | { PseudoVWMACCU_VX_MF4, 3013 }, |
| 6266 | { PseudoVWMACCU_VX_MF8, 3014 }, |
| 6267 | { PseudoVWMACC_VV_M1, 3015 }, |
| 6268 | { PseudoVWMACC_VV_M2, 3016 }, |
| 6269 | { PseudoVWMACC_VV_M4, 3017 }, |
| 6270 | { PseudoVWMACC_VV_MF2, 3018 }, |
| 6271 | { PseudoVWMACC_VV_MF4, 3019 }, |
| 6272 | { PseudoVWMACC_VV_MF8, 3020 }, |
| 6273 | { PseudoVWMACC_VX_M1, 3021 }, |
| 6274 | { PseudoVWMACC_VX_M2, 3022 }, |
| 6275 | { PseudoVWMACC_VX_M4, 3023 }, |
| 6276 | { PseudoVWMACC_VX_MF2, 3024 }, |
| 6277 | { PseudoVWMACC_VX_MF4, 3025 }, |
| 6278 | { PseudoVWMACC_VX_MF8, 3026 }, |
| 6279 | { PseudoVWMULSU_VV_M1, 3027 }, |
| 6280 | { PseudoVWMULSU_VV_M2, 3028 }, |
| 6281 | { PseudoVWMULSU_VV_M4, 3029 }, |
| 6282 | { PseudoVWMULSU_VV_MF2, 3030 }, |
| 6283 | { PseudoVWMULSU_VV_MF4, 3031 }, |
| 6284 | { PseudoVWMULSU_VV_MF8, 3032 }, |
| 6285 | { PseudoVWMULSU_VX_M1, 3033 }, |
| 6286 | { PseudoVWMULSU_VX_M2, 3034 }, |
| 6287 | { PseudoVWMULSU_VX_M4, 3035 }, |
| 6288 | { PseudoVWMULSU_VX_MF2, 3036 }, |
| 6289 | { PseudoVWMULSU_VX_MF4, 3037 }, |
| 6290 | { PseudoVWMULSU_VX_MF8, 3038 }, |
| 6291 | { PseudoVWMULU_VV_M1, 3039 }, |
| 6292 | { PseudoVWMULU_VV_M2, 3040 }, |
| 6293 | { PseudoVWMULU_VV_M4, 3041 }, |
| 6294 | { PseudoVWMULU_VV_MF2, 3042 }, |
| 6295 | { PseudoVWMULU_VV_MF4, 3043 }, |
| 6296 | { PseudoVWMULU_VV_MF8, 3044 }, |
| 6297 | { PseudoVWMULU_VX_M1, 3045 }, |
| 6298 | { PseudoVWMULU_VX_M2, 3046 }, |
| 6299 | { PseudoVWMULU_VX_M4, 3047 }, |
| 6300 | { PseudoVWMULU_VX_MF2, 3048 }, |
| 6301 | { PseudoVWMULU_VX_MF4, 3049 }, |
| 6302 | { PseudoVWMULU_VX_MF8, 3050 }, |
| 6303 | { PseudoVWMUL_VV_M1, 3051 }, |
| 6304 | { PseudoVWMUL_VV_M2, 3052 }, |
| 6305 | { PseudoVWMUL_VV_M4, 3053 }, |
| 6306 | { PseudoVWMUL_VV_MF2, 3054 }, |
| 6307 | { PseudoVWMUL_VV_MF4, 3055 }, |
| 6308 | { PseudoVWMUL_VV_MF8, 3056 }, |
| 6309 | { PseudoVWMUL_VX_M1, 3057 }, |
| 6310 | { PseudoVWMUL_VX_M2, 3058 }, |
| 6311 | { PseudoVWMUL_VX_M4, 3059 }, |
| 6312 | { PseudoVWMUL_VX_MF2, 3060 }, |
| 6313 | { PseudoVWMUL_VX_MF4, 3061 }, |
| 6314 | { PseudoVWMUL_VX_MF8, 3062 }, |
| 6315 | { PseudoVWREDSUMU_VS_M1_E16, 3063 }, |
| 6316 | { PseudoVWREDSUMU_VS_M1_E32, 3064 }, |
| 6317 | { PseudoVWREDSUMU_VS_M1_E8, 3065 }, |
| 6318 | { PseudoVWREDSUMU_VS_M2_E16, 3066 }, |
| 6319 | { PseudoVWREDSUMU_VS_M2_E32, 3067 }, |
| 6320 | { PseudoVWREDSUMU_VS_M2_E8, 3068 }, |
| 6321 | { PseudoVWREDSUMU_VS_M4_E16, 3069 }, |
| 6322 | { PseudoVWREDSUMU_VS_M4_E32, 3070 }, |
| 6323 | { PseudoVWREDSUMU_VS_M4_E8, 3071 }, |
| 6324 | { PseudoVWREDSUMU_VS_M8_E16, 3072 }, |
| 6325 | { PseudoVWREDSUMU_VS_M8_E32, 3073 }, |
| 6326 | { PseudoVWREDSUMU_VS_M8_E8, 3074 }, |
| 6327 | { PseudoVWREDSUMU_VS_MF2_E16, 3075 }, |
| 6328 | { PseudoVWREDSUMU_VS_MF2_E32, 3076 }, |
| 6329 | { PseudoVWREDSUMU_VS_MF2_E8, 3077 }, |
| 6330 | { PseudoVWREDSUMU_VS_MF4_E16, 3078 }, |
| 6331 | { PseudoVWREDSUMU_VS_MF4_E8, 3079 }, |
| 6332 | { PseudoVWREDSUMU_VS_MF8_E8, 3080 }, |
| 6333 | { PseudoVWREDSUM_VS_M1_E16, 3081 }, |
| 6334 | { PseudoVWREDSUM_VS_M1_E32, 3082 }, |
| 6335 | { PseudoVWREDSUM_VS_M1_E8, 3083 }, |
| 6336 | { PseudoVWREDSUM_VS_M2_E16, 3084 }, |
| 6337 | { PseudoVWREDSUM_VS_M2_E32, 3085 }, |
| 6338 | { PseudoVWREDSUM_VS_M2_E8, 3086 }, |
| 6339 | { PseudoVWREDSUM_VS_M4_E16, 3087 }, |
| 6340 | { PseudoVWREDSUM_VS_M4_E32, 3088 }, |
| 6341 | { PseudoVWREDSUM_VS_M4_E8, 3089 }, |
| 6342 | { PseudoVWREDSUM_VS_M8_E16, 3090 }, |
| 6343 | { PseudoVWREDSUM_VS_M8_E32, 3091 }, |
| 6344 | { PseudoVWREDSUM_VS_M8_E8, 3092 }, |
| 6345 | { PseudoVWREDSUM_VS_MF2_E16, 3093 }, |
| 6346 | { PseudoVWREDSUM_VS_MF2_E32, 3094 }, |
| 6347 | { PseudoVWREDSUM_VS_MF2_E8, 3095 }, |
| 6348 | { PseudoVWREDSUM_VS_MF4_E16, 3096 }, |
| 6349 | { PseudoVWREDSUM_VS_MF4_E8, 3097 }, |
| 6350 | { PseudoVWREDSUM_VS_MF8_E8, 3098 }, |
| 6351 | { PseudoVWSLL_VI_M1, 3099 }, |
| 6352 | { PseudoVWSLL_VI_M2, 3100 }, |
| 6353 | { PseudoVWSLL_VI_M4, 3101 }, |
| 6354 | { PseudoVWSLL_VI_MF2, 3102 }, |
| 6355 | { PseudoVWSLL_VI_MF4, 3103 }, |
| 6356 | { PseudoVWSLL_VI_MF8, 3104 }, |
| 6357 | { PseudoVWSLL_VV_M1, 3105 }, |
| 6358 | { PseudoVWSLL_VV_M2, 3106 }, |
| 6359 | { PseudoVWSLL_VV_M4, 3107 }, |
| 6360 | { PseudoVWSLL_VV_MF2, 3108 }, |
| 6361 | { PseudoVWSLL_VV_MF4, 3109 }, |
| 6362 | { PseudoVWSLL_VV_MF8, 3110 }, |
| 6363 | { PseudoVWSLL_VX_M1, 3111 }, |
| 6364 | { PseudoVWSLL_VX_M2, 3112 }, |
| 6365 | { PseudoVWSLL_VX_M4, 3113 }, |
| 6366 | { PseudoVWSLL_VX_MF2, 3114 }, |
| 6367 | { PseudoVWSLL_VX_MF4, 3115 }, |
| 6368 | { PseudoVWSLL_VX_MF8, 3116 }, |
| 6369 | { PseudoVWSUBU_VV_M1, 3117 }, |
| 6370 | { PseudoVWSUBU_VV_M2, 3118 }, |
| 6371 | { PseudoVWSUBU_VV_M4, 3119 }, |
| 6372 | { PseudoVWSUBU_VV_MF2, 3120 }, |
| 6373 | { PseudoVWSUBU_VV_MF4, 3121 }, |
| 6374 | { PseudoVWSUBU_VV_MF8, 3122 }, |
| 6375 | { PseudoVWSUBU_VX_M1, 3123 }, |
| 6376 | { PseudoVWSUBU_VX_M2, 3124 }, |
| 6377 | { PseudoVWSUBU_VX_M4, 3125 }, |
| 6378 | { PseudoVWSUBU_VX_MF2, 3126 }, |
| 6379 | { PseudoVWSUBU_VX_MF4, 3127 }, |
| 6380 | { PseudoVWSUBU_VX_MF8, 3128 }, |
| 6381 | { PseudoVWSUBU_WV_M1, 3129 }, |
| 6382 | { PseudoVWSUBU_WV_M1_TIED, 3130 }, |
| 6383 | { PseudoVWSUBU_WV_M2, 3131 }, |
| 6384 | { PseudoVWSUBU_WV_M2_TIED, 3132 }, |
| 6385 | { PseudoVWSUBU_WV_M4, 3133 }, |
| 6386 | { PseudoVWSUBU_WV_M4_TIED, 3134 }, |
| 6387 | { PseudoVWSUBU_WV_MF2, 3135 }, |
| 6388 | { PseudoVWSUBU_WV_MF2_TIED, 3136 }, |
| 6389 | { PseudoVWSUBU_WV_MF4, 3137 }, |
| 6390 | { PseudoVWSUBU_WV_MF4_TIED, 3138 }, |
| 6391 | { PseudoVWSUBU_WV_MF8, 3139 }, |
| 6392 | { PseudoVWSUBU_WV_MF8_TIED, 3140 }, |
| 6393 | { PseudoVWSUBU_WX_M1, 3141 }, |
| 6394 | { PseudoVWSUBU_WX_M2, 3142 }, |
| 6395 | { PseudoVWSUBU_WX_M4, 3143 }, |
| 6396 | { PseudoVWSUBU_WX_MF2, 3144 }, |
| 6397 | { PseudoVWSUBU_WX_MF4, 3145 }, |
| 6398 | { PseudoVWSUBU_WX_MF8, 3146 }, |
| 6399 | { PseudoVWSUB_VV_M1, 3147 }, |
| 6400 | { PseudoVWSUB_VV_M2, 3148 }, |
| 6401 | { PseudoVWSUB_VV_M4, 3149 }, |
| 6402 | { PseudoVWSUB_VV_MF2, 3150 }, |
| 6403 | { PseudoVWSUB_VV_MF4, 3151 }, |
| 6404 | { PseudoVWSUB_VV_MF8, 3152 }, |
| 6405 | { PseudoVWSUB_VX_M1, 3153 }, |
| 6406 | { PseudoVWSUB_VX_M2, 3154 }, |
| 6407 | { PseudoVWSUB_VX_M4, 3155 }, |
| 6408 | { PseudoVWSUB_VX_MF2, 3156 }, |
| 6409 | { PseudoVWSUB_VX_MF4, 3157 }, |
| 6410 | { PseudoVWSUB_VX_MF8, 3158 }, |
| 6411 | { PseudoVWSUB_WV_M1, 3159 }, |
| 6412 | { PseudoVWSUB_WV_M1_TIED, 3160 }, |
| 6413 | { PseudoVWSUB_WV_M2, 3161 }, |
| 6414 | { PseudoVWSUB_WV_M2_TIED, 3162 }, |
| 6415 | { PseudoVWSUB_WV_M4, 3163 }, |
| 6416 | { PseudoVWSUB_WV_M4_TIED, 3164 }, |
| 6417 | { PseudoVWSUB_WV_MF2, 3165 }, |
| 6418 | { PseudoVWSUB_WV_MF2_TIED, 3166 }, |
| 6419 | { PseudoVWSUB_WV_MF4, 3167 }, |
| 6420 | { PseudoVWSUB_WV_MF4_TIED, 3168 }, |
| 6421 | { PseudoVWSUB_WV_MF8, 3169 }, |
| 6422 | { PseudoVWSUB_WV_MF8_TIED, 3170 }, |
| 6423 | { PseudoVWSUB_WX_M1, 3171 }, |
| 6424 | { PseudoVWSUB_WX_M2, 3172 }, |
| 6425 | { PseudoVWSUB_WX_M4, 3173 }, |
| 6426 | { PseudoVWSUB_WX_MF2, 3174 }, |
| 6427 | { PseudoVWSUB_WX_MF4, 3175 }, |
| 6428 | { PseudoVWSUB_WX_MF8, 3176 }, |
| 6429 | { PseudoVXOR_VI_M1, 3177 }, |
| 6430 | { PseudoVXOR_VI_M2, 3178 }, |
| 6431 | { PseudoVXOR_VI_M4, 3179 }, |
| 6432 | { PseudoVXOR_VI_M8, 3180 }, |
| 6433 | { PseudoVXOR_VI_MF2, 3181 }, |
| 6434 | { PseudoVXOR_VI_MF4, 3182 }, |
| 6435 | { PseudoVXOR_VI_MF8, 3183 }, |
| 6436 | { PseudoVXOR_VV_M1, 3184 }, |
| 6437 | { PseudoVXOR_VV_M2, 3185 }, |
| 6438 | { PseudoVXOR_VV_M4, 3186 }, |
| 6439 | { PseudoVXOR_VV_M8, 3187 }, |
| 6440 | { PseudoVXOR_VV_MF2, 3188 }, |
| 6441 | { PseudoVXOR_VV_MF4, 3189 }, |
| 6442 | { PseudoVXOR_VV_MF8, 3190 }, |
| 6443 | { PseudoVXOR_VX_M1, 3191 }, |
| 6444 | { PseudoVXOR_VX_M2, 3192 }, |
| 6445 | { PseudoVXOR_VX_M4, 3193 }, |
| 6446 | { PseudoVXOR_VX_M8, 3194 }, |
| 6447 | { PseudoVXOR_VX_MF2, 3195 }, |
| 6448 | { PseudoVXOR_VX_MF4, 3196 }, |
| 6449 | { PseudoVXOR_VX_MF8, 3197 }, |
| 6450 | { PseudoVZEXT_VF2_M1, 3198 }, |
| 6451 | { PseudoVZEXT_VF2_M2, 3199 }, |
| 6452 | { PseudoVZEXT_VF2_M4, 3200 }, |
| 6453 | { PseudoVZEXT_VF2_M8, 3201 }, |
| 6454 | { PseudoVZEXT_VF2_MF2, 3202 }, |
| 6455 | { PseudoVZEXT_VF2_MF4, 3203 }, |
| 6456 | { PseudoVZEXT_VF4_M1, 3204 }, |
| 6457 | { PseudoVZEXT_VF4_M2, 3205 }, |
| 6458 | { PseudoVZEXT_VF4_M4, 3206 }, |
| 6459 | { PseudoVZEXT_VF4_M8, 3207 }, |
| 6460 | { PseudoVZEXT_VF4_MF2, 3208 }, |
| 6461 | { PseudoVZEXT_VF8_M1, 3209 }, |
| 6462 | { PseudoVZEXT_VF8_M2, 3210 }, |
| 6463 | { PseudoVZEXT_VF8_M4, 3211 }, |
| 6464 | { PseudoVZEXT_VF8_M8, 3212 }, |
| 6465 | }; |
| 6466 | |
| 6467 | struct KeyType { |
| 6468 | unsigned UnmaskedPseudo; |
| 6469 | }; |
| 6470 | KeyType Key = {UnmaskedPseudo}; |
| 6471 | struct Comp { |
| 6472 | bool operator()(const IndexType &LHS, const KeyType &RHS) const { |
| 6473 | if (LHS.UnmaskedPseudo < RHS.UnmaskedPseudo) |
| 6474 | return true; |
| 6475 | if (LHS.UnmaskedPseudo > RHS.UnmaskedPseudo) |
| 6476 | return false; |
| 6477 | return false; |
| 6478 | } |
| 6479 | }; |
| 6480 | auto Table = ArrayRef(Index); |
| 6481 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 6482 | if (Idx == Table.end() || |
| 6483 | Key.UnmaskedPseudo != Idx->UnmaskedPseudo) |
| 6484 | return nullptr; |
| 6485 | |
| 6486 | return &RISCVMaskedPseudosTable[Idx->_index]; |
| 6487 | } |
| 6488 | #endif |
| 6489 | |
| 6490 | #ifdef GET_RISCVOpcodesList_DECL |
| 6491 | const RISCVOpcode *lookupRISCVOpcodeByValue(uint8_t Value); |
| 6492 | const RISCVOpcode *lookupRISCVOpcodeByName(StringRef Name); |
| 6493 | #endif |
| 6494 | |
| 6495 | #ifdef GET_RISCVOpcodesList_IMPL |
| 6496 | constexpr RISCVOpcode RISCVOpcodesList[] = { |
| 6497 | { "LOAD", 0x3 }, // 0 |
| 6498 | { "LOAD_FP", 0x7 }, // 1 |
| 6499 | { "CUSTOM_0", 0xB }, // 2 |
| 6500 | { "MISC_MEM", 0xF }, // 3 |
| 6501 | { "OP_IMM", 0x13 }, // 4 |
| 6502 | { "AUIPC", 0x17 }, // 5 |
| 6503 | { "OP_IMM_32", 0x1B }, // 6 |
| 6504 | { "STORE", 0x23 }, // 7 |
| 6505 | { "STORE_FP", 0x27 }, // 8 |
| 6506 | { "CUSTOM_1", 0x2B }, // 9 |
| 6507 | { "AMO", 0x2F }, // 10 |
| 6508 | { "OP", 0x33 }, // 11 |
| 6509 | { "LUI", 0x37 }, // 12 |
| 6510 | { "OP_32", 0x3B }, // 13 |
| 6511 | { "MADD", 0x43 }, // 14 |
| 6512 | { "MSUB", 0x47 }, // 15 |
| 6513 | { "NMSUB", 0x4B }, // 16 |
| 6514 | { "NMADD", 0x4F }, // 17 |
| 6515 | { "OP_FP", 0x53 }, // 18 |
| 6516 | { "OP_V", 0x57 }, // 19 |
| 6517 | { "CUSTOM_2", 0x5B }, // 20 |
| 6518 | { "BRANCH", 0x63 }, // 21 |
| 6519 | { "JALR", 0x67 }, // 22 |
| 6520 | { "JAL", 0x6F }, // 23 |
| 6521 | { "SYSTEM", 0x73 }, // 24 |
| 6522 | { "OP_VE", 0x77 }, // 25 |
| 6523 | { "CUSTOM_3", 0x7B }, // 26 |
| 6524 | }; |
| 6525 | |
| 6526 | const RISCVOpcode *lookupRISCVOpcodeByValue(uint8_t Value) { |
| 6527 | struct KeyType { |
| 6528 | uint8_t Value; |
| 6529 | }; |
| 6530 | KeyType Key = {Value}; |
| 6531 | struct Comp { |
| 6532 | bool operator()(const RISCVOpcode &LHS, const KeyType &RHS) const { |
| 6533 | if (LHS.Value < RHS.Value) |
| 6534 | return true; |
| 6535 | if (LHS.Value > RHS.Value) |
| 6536 | return false; |
| 6537 | return false; |
| 6538 | } |
| 6539 | }; |
| 6540 | auto Table = ArrayRef(RISCVOpcodesList); |
| 6541 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 6542 | if (Idx == Table.end() || |
| 6543 | Key.Value != Idx->Value) |
| 6544 | return nullptr; |
| 6545 | |
| 6546 | return &*Idx; |
| 6547 | } |
| 6548 | |
| 6549 | const RISCVOpcode *lookupRISCVOpcodeByName(StringRef Name) { |
| 6550 | struct IndexType { |
| 6551 | const char * Name; |
| 6552 | unsigned _index; |
| 6553 | }; |
| 6554 | static const struct IndexType Index[] = { |
| 6555 | { "AMO", 10 }, |
| 6556 | { "AUIPC", 5 }, |
| 6557 | { "BRANCH", 21 }, |
| 6558 | { "CUSTOM_0", 2 }, |
| 6559 | { "CUSTOM_1", 9 }, |
| 6560 | { "CUSTOM_2", 20 }, |
| 6561 | { "CUSTOM_3", 26 }, |
| 6562 | { "JAL", 23 }, |
| 6563 | { "JALR", 22 }, |
| 6564 | { "LOAD", 0 }, |
| 6565 | { "LOAD_FP", 1 }, |
| 6566 | { "LUI", 12 }, |
| 6567 | { "MADD", 14 }, |
| 6568 | { "MISC_MEM", 3 }, |
| 6569 | { "MSUB", 15 }, |
| 6570 | { "NMADD", 17 }, |
| 6571 | { "NMSUB", 16 }, |
| 6572 | { "OP", 11 }, |
| 6573 | { "OP_32", 13 }, |
| 6574 | { "OP_FP", 18 }, |
| 6575 | { "OP_IMM", 4 }, |
| 6576 | { "OP_IMM_32", 6 }, |
| 6577 | { "OP_V", 19 }, |
| 6578 | { "OP_VE", 25 }, |
| 6579 | { "STORE", 7 }, |
| 6580 | { "STORE_FP", 8 }, |
| 6581 | { "SYSTEM", 24 }, |
| 6582 | }; |
| 6583 | |
| 6584 | struct KeyType { |
| 6585 | std::string Name; |
| 6586 | }; |
| 6587 | KeyType Key = {Name.upper()}; |
| 6588 | struct Comp { |
| 6589 | bool operator()(const IndexType &LHS, const KeyType &RHS) const { |
| 6590 | int CmpName = StringRef(LHS.Name).compare(RHS.Name); |
| 6591 | if (CmpName < 0) return true; |
| 6592 | if (CmpName > 0) return false; |
| 6593 | return false; |
| 6594 | } |
| 6595 | }; |
| 6596 | auto Table = ArrayRef(Index); |
| 6597 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 6598 | if (Idx == Table.end() || |
| 6599 | Key.Name != Idx->Name) |
| 6600 | return nullptr; |
| 6601 | |
| 6602 | return &RISCVOpcodesList[Idx->_index]; |
| 6603 | } |
| 6604 | #endif |
| 6605 | |
| 6606 | #ifdef GET_RISCVTuneInfoTable_DECL |
| 6607 | const RISCVTuneInfo *getRISCVTuneInfo(StringRef Name); |
| 6608 | #endif |
| 6609 | |
| 6610 | #ifdef GET_RISCVTuneInfoTable_IMPL |
| 6611 | constexpr RISCVTuneInfo RISCVTuneInfoTable[] = { |
| 6612 | { "generic", 0x1, 0x1, 0x0, 0x0, 0x1, 0xFFFFFFFF, 0x5 }, // 0 |
| 6613 | { "generic-rv32", 0x1, 0x1, 0x0, 0x0, 0x1, 0xFFFFFFFF, 0x5 }, // 1 |
| 6614 | { "generic-rv64", 0x1, 0x1, 0x0, 0x0, 0x1, 0xFFFFFFFF, 0x5 }, // 2 |
| 6615 | }; |
| 6616 | |
| 6617 | const RISCVTuneInfo *getRISCVTuneInfo(StringRef Name) { |
| 6618 | struct IndexType { |
| 6619 | const char * Name; |
| 6620 | unsigned _index; |
| 6621 | }; |
| 6622 | static const struct IndexType Index[] = { |
| 6623 | { "GENERIC", 0 }, |
| 6624 | { "GENERIC-RV32", 1 }, |
| 6625 | { "GENERIC-RV64", 2 }, |
| 6626 | }; |
| 6627 | |
| 6628 | struct KeyType { |
| 6629 | std::string Name; |
| 6630 | }; |
| 6631 | KeyType Key = {Name.upper()}; |
| 6632 | struct Comp { |
| 6633 | bool operator()(const IndexType &LHS, const KeyType &RHS) const { |
| 6634 | int CmpName = StringRef(LHS.Name).compare(RHS.Name); |
| 6635 | if (CmpName < 0) return true; |
| 6636 | if (CmpName > 0) return false; |
| 6637 | return false; |
| 6638 | } |
| 6639 | }; |
| 6640 | auto Table = ArrayRef(Index); |
| 6641 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 6642 | if (Idx == Table.end() || |
| 6643 | Key.Name != Idx->Name) |
| 6644 | return nullptr; |
| 6645 | |
| 6646 | return &RISCVTuneInfoTable[Idx->_index]; |
| 6647 | } |
| 6648 | #endif |
| 6649 | |
| 6650 | #ifdef GET_RISCVVIntrinsicsTable_DECL |
| 6651 | const RISCVVIntrinsicInfo *getRISCVVIntrinsicInfo(unsigned IntrinsicID); |
| 6652 | #endif |
| 6653 | |
| 6654 | #ifdef GET_RISCVVIntrinsicsTable_IMPL |
| 6655 | constexpr RISCVVIntrinsicInfo RISCVVIntrinsicsTable[] = { |
| 6656 | { Intrinsic::riscv_sf_vc_fv_se, 0x3, 0x4 }, // 0 |
| 6657 | { Intrinsic::riscv_sf_vc_fvv_se, 0x3, 0x4 }, // 1 |
| 6658 | { Intrinsic::riscv_sf_vc_fvw_se, 0x3, 0x4 }, // 2 |
| 6659 | { Intrinsic::riscv_sf_vc_i_se, 0xF, 0x6 }, // 3 |
| 6660 | { Intrinsic::riscv_sf_vc_iv_se, 0xF, 0x4 }, // 4 |
| 6661 | { Intrinsic::riscv_sf_vc_ivv_se, 0xF, 0x4 }, // 5 |
| 6662 | { Intrinsic::riscv_sf_vc_ivw_se, 0xF, 0x4 }, // 6 |
| 6663 | { Intrinsic::riscv_sf_vc_v_fv, 0x2, 0x3 }, // 7 |
| 6664 | { Intrinsic::riscv_sf_vc_v_fv_se, 0x2, 0x3 }, // 8 |
| 6665 | { Intrinsic::riscv_sf_vc_v_fvv, 0x3, 0x4 }, // 9 |
| 6666 | { Intrinsic::riscv_sf_vc_v_fvv_se, 0x3, 0x4 }, // 10 |
| 6667 | { Intrinsic::riscv_sf_vc_v_fvw, 0x3, 0x4 }, // 11 |
| 6668 | { Intrinsic::riscv_sf_vc_v_fvw_se, 0x3, 0x4 }, // 12 |
| 6669 | { Intrinsic::riscv_sf_vc_v_i, 0xF, 0x3 }, // 13 |
| 6670 | { Intrinsic::riscv_sf_vc_v_i_se, 0xF, 0x3 }, // 14 |
| 6671 | { Intrinsic::riscv_sf_vc_v_iv, 0xF, 0x3 }, // 15 |
| 6672 | { Intrinsic::riscv_sf_vc_v_iv_se, 0xF, 0x3 }, // 16 |
| 6673 | { Intrinsic::riscv_sf_vc_v_ivv, 0xF, 0x4 }, // 17 |
| 6674 | { Intrinsic::riscv_sf_vc_v_ivv_se, 0xF, 0x4 }, // 18 |
| 6675 | { Intrinsic::riscv_sf_vc_v_ivw, 0xF, 0x4 }, // 19 |
| 6676 | { Intrinsic::riscv_sf_vc_v_ivw_se, 0xF, 0x4 }, // 20 |
| 6677 | { Intrinsic::riscv_sf_vc_v_vv, 0x2, 0x3 }, // 21 |
| 6678 | { Intrinsic::riscv_sf_vc_v_vv_se, 0x2, 0x3 }, // 22 |
| 6679 | { Intrinsic::riscv_sf_vc_v_vvv, 0x3, 0x4 }, // 23 |
| 6680 | { Intrinsic::riscv_sf_vc_v_vvv_se, 0x3, 0x4 }, // 24 |
| 6681 | { Intrinsic::riscv_sf_vc_v_vvw, 0x3, 0x4 }, // 25 |
| 6682 | { Intrinsic::riscv_sf_vc_v_vvw_se, 0x3, 0x4 }, // 26 |
| 6683 | { Intrinsic::riscv_sf_vc_v_x, 0x2, 0x3 }, // 27 |
| 6684 | { Intrinsic::riscv_sf_vc_v_x_se, 0x2, 0x3 }, // 28 |
| 6685 | { Intrinsic::riscv_sf_vc_v_xv, 0x2, 0x3 }, // 29 |
| 6686 | { Intrinsic::riscv_sf_vc_v_xv_se, 0x2, 0x3 }, // 30 |
| 6687 | { Intrinsic::riscv_sf_vc_v_xvv, 0x3, 0x4 }, // 31 |
| 6688 | { Intrinsic::riscv_sf_vc_v_xvv_se, 0x3, 0x4 }, // 32 |
| 6689 | { Intrinsic::riscv_sf_vc_v_xvw, 0x3, 0x4 }, // 33 |
| 6690 | { Intrinsic::riscv_sf_vc_v_xvw_se, 0x3, 0x4 }, // 34 |
| 6691 | { Intrinsic::riscv_sf_vc_vv_se, 0x3, 0x4 }, // 35 |
| 6692 | { Intrinsic::riscv_sf_vc_vvv_se, 0x3, 0x4 }, // 36 |
| 6693 | { Intrinsic::riscv_sf_vc_vvw_se, 0x3, 0x4 }, // 37 |
| 6694 | { Intrinsic::riscv_sf_vc_x_se, 0x3, 0x6 }, // 38 |
| 6695 | { Intrinsic::riscv_sf_vc_xv_se, 0x3, 0x4 }, // 39 |
| 6696 | { Intrinsic::riscv_sf_vc_xvv_se, 0x3, 0x4 }, // 40 |
| 6697 | { Intrinsic::riscv_sf_vc_xvw_se, 0x3, 0x4 }, // 41 |
| 6698 | { Intrinsic::riscv_sf_vfnrclip_x_f_qf, 0xF, 0x4 }, // 42 |
| 6699 | { Intrinsic::riscv_sf_vfnrclip_x_f_qf_mask, 0xF, 0x5 }, // 43 |
| 6700 | { Intrinsic::riscv_sf_vfnrclip_xu_f_qf, 0xF, 0x4 }, // 44 |
| 6701 | { Intrinsic::riscv_sf_vfnrclip_xu_f_qf_mask, 0xF, 0x5 }, // 45 |
| 6702 | { Intrinsic::riscv_sf_vfwmacc_4x4x4, 0xF, 0x3 }, // 46 |
| 6703 | { Intrinsic::riscv_sf_vqmacc_2x8x2, 0xF, 0x3 }, // 47 |
| 6704 | { Intrinsic::riscv_sf_vqmacc_4x8x4, 0xF, 0x3 }, // 48 |
| 6705 | { Intrinsic::riscv_sf_vqmaccsu_2x8x2, 0xF, 0x3 }, // 49 |
| 6706 | { Intrinsic::riscv_sf_vqmaccsu_4x8x4, 0xF, 0x3 }, // 50 |
| 6707 | { Intrinsic::riscv_sf_vqmaccu_2x8x2, 0xF, 0x3 }, // 51 |
| 6708 | { Intrinsic::riscv_sf_vqmaccu_4x8x4, 0xF, 0x3 }, // 52 |
| 6709 | { Intrinsic::riscv_sf_vqmaccus_2x8x2, 0xF, 0x3 }, // 53 |
| 6710 | { Intrinsic::riscv_sf_vqmaccus_4x8x4, 0xF, 0x3 }, // 54 |
| 6711 | { Intrinsic::riscv_th_vmaqa, 0x1, 0x3 }, // 55 |
| 6712 | { Intrinsic::riscv_th_vmaqa_mask, 0x1, 0x4 }, // 56 |
| 6713 | { Intrinsic::riscv_th_vmaqasu, 0x1, 0x3 }, // 57 |
| 6714 | { Intrinsic::riscv_th_vmaqasu_mask, 0x1, 0x4 }, // 58 |
| 6715 | { Intrinsic::riscv_th_vmaqau, 0x1, 0x3 }, // 59 |
| 6716 | { Intrinsic::riscv_th_vmaqau_mask, 0x1, 0x4 }, // 60 |
| 6717 | { Intrinsic::riscv_th_vmaqaus, 0x1, 0x3 }, // 61 |
| 6718 | { Intrinsic::riscv_th_vmaqaus_mask, 0x1, 0x4 }, // 62 |
| 6719 | { Intrinsic::riscv_vaadd, 0x2, 0x4 }, // 63 |
| 6720 | { Intrinsic::riscv_vaadd_mask, 0x2, 0x5 }, // 64 |
| 6721 | { Intrinsic::riscv_vaaddu, 0x2, 0x4 }, // 65 |
| 6722 | { Intrinsic::riscv_vaaddu_mask, 0x2, 0x5 }, // 66 |
| 6723 | { Intrinsic::riscv_vadc, 0x2, 0x4 }, // 67 |
| 6724 | { Intrinsic::riscv_vadd, 0x2, 0x3 }, // 68 |
| 6725 | { Intrinsic::riscv_vadd_mask, 0x2, 0x4 }, // 69 |
| 6726 | { Intrinsic::riscv_vaesdf_vs, 0xF, 0x2 }, // 70 |
| 6727 | { Intrinsic::riscv_vaesdf_vv, 0xF, 0x2 }, // 71 |
| 6728 | { Intrinsic::riscv_vaesdm_vs, 0xF, 0x2 }, // 72 |
| 6729 | { Intrinsic::riscv_vaesdm_vv, 0xF, 0x2 }, // 73 |
| 6730 | { Intrinsic::riscv_vaesef_vs, 0xF, 0x2 }, // 74 |
| 6731 | { Intrinsic::riscv_vaesef_vv, 0xF, 0x2 }, // 75 |
| 6732 | { Intrinsic::riscv_vaesem_vs, 0xF, 0x2 }, // 76 |
| 6733 | { Intrinsic::riscv_vaesem_vv, 0xF, 0x2 }, // 77 |
| 6734 | { Intrinsic::riscv_vaeskf1, 0x2, 0x3 }, // 78 |
| 6735 | { Intrinsic::riscv_vaeskf2, 0x2, 0x3 }, // 79 |
| 6736 | { Intrinsic::riscv_vaesz_vs, 0xF, 0x2 }, // 80 |
| 6737 | { Intrinsic::riscv_vand, 0x2, 0x3 }, // 81 |
| 6738 | { Intrinsic::riscv_vand_mask, 0x2, 0x4 }, // 82 |
| 6739 | { Intrinsic::riscv_vandn, 0x2, 0x3 }, // 83 |
| 6740 | { Intrinsic::riscv_vandn_mask, 0x2, 0x4 }, // 84 |
| 6741 | { Intrinsic::riscv_vasub, 0x2, 0x4 }, // 85 |
| 6742 | { Intrinsic::riscv_vasub_mask, 0x2, 0x5 }, // 86 |
| 6743 | { Intrinsic::riscv_vasubu, 0x2, 0x4 }, // 87 |
| 6744 | { Intrinsic::riscv_vasubu_mask, 0x2, 0x5 }, // 88 |
| 6745 | { Intrinsic::riscv_vbrev, 0xF, 0x2 }, // 89 |
| 6746 | { Intrinsic::riscv_vbrev_mask, 0xF, 0x3 }, // 90 |
| 6747 | { Intrinsic::riscv_vbrev8, 0xF, 0x2 }, // 91 |
| 6748 | { Intrinsic::riscv_vbrev8_mask, 0xF, 0x3 }, // 92 |
| 6749 | { Intrinsic::riscv_vclmul, 0x2, 0x3 }, // 93 |
| 6750 | { Intrinsic::riscv_vclmul_mask, 0x2, 0x4 }, // 94 |
| 6751 | { Intrinsic::riscv_vclmulh, 0x2, 0x3 }, // 95 |
| 6752 | { Intrinsic::riscv_vclmulh_mask, 0x2, 0x4 }, // 96 |
| 6753 | { Intrinsic::riscv_vclz, 0xF, 0x2 }, // 97 |
| 6754 | { Intrinsic::riscv_vclz_mask, 0xF, 0x3 }, // 98 |
| 6755 | { Intrinsic::riscv_vcompress, 0xF, 0x3 }, // 99 |
| 6756 | { Intrinsic::riscv_vcpop, 0xF, 0x1 }, // 100 |
| 6757 | { Intrinsic::riscv_vcpop_mask, 0xF, 0x2 }, // 101 |
| 6758 | { Intrinsic::riscv_vcpopv, 0xF, 0x2 }, // 102 |
| 6759 | { Intrinsic::riscv_vcpopv_mask, 0xF, 0x3 }, // 103 |
| 6760 | { Intrinsic::riscv_vctz, 0xF, 0x2 }, // 104 |
| 6761 | { Intrinsic::riscv_vctz_mask, 0xF, 0x3 }, // 105 |
| 6762 | { Intrinsic::riscv_vdiv, 0x2, 0x3 }, // 106 |
| 6763 | { Intrinsic::riscv_vdiv_mask, 0x2, 0x4 }, // 107 |
| 6764 | { Intrinsic::riscv_vdivu, 0x2, 0x3 }, // 108 |
| 6765 | { Intrinsic::riscv_vdivu_mask, 0x2, 0x4 }, // 109 |
| 6766 | { Intrinsic::riscv_vfadd, 0x2, 0x4 }, // 110 |
| 6767 | { Intrinsic::riscv_vfadd_mask, 0x2, 0x5 }, // 111 |
| 6768 | { Intrinsic::riscv_vfclass, 0xF, 0x1 }, // 112 |
| 6769 | { Intrinsic::riscv_vfclass_mask, 0xF, 0x3 }, // 113 |
| 6770 | { Intrinsic::riscv_vfcvt_f_x_v, 0xF, 0x3 }, // 114 |
| 6771 | { Intrinsic::riscv_vfcvt_f_x_v_mask, 0xF, 0x4 }, // 115 |
| 6772 | { Intrinsic::riscv_vfcvt_f_xu_v, 0xF, 0x3 }, // 116 |
| 6773 | { Intrinsic::riscv_vfcvt_f_xu_v_mask, 0xF, 0x4 }, // 117 |
| 6774 | { Intrinsic::riscv_vfcvt_rtz_x_f_v, 0xF, 0x2 }, // 118 |
| 6775 | { Intrinsic::riscv_vfcvt_rtz_x_f_v_mask, 0xF, 0x3 }, // 119 |
| 6776 | { Intrinsic::riscv_vfcvt_rtz_xu_f_v, 0xF, 0x2 }, // 120 |
| 6777 | { Intrinsic::riscv_vfcvt_rtz_xu_f_v_mask, 0xF, 0x3 }, // 121 |
| 6778 | { Intrinsic::riscv_vfcvt_x_f_v, 0xF, 0x3 }, // 122 |
| 6779 | { Intrinsic::riscv_vfcvt_x_f_v_mask, 0xF, 0x4 }, // 123 |
| 6780 | { Intrinsic::riscv_vfcvt_xu_f_v, 0xF, 0x3 }, // 124 |
| 6781 | { Intrinsic::riscv_vfcvt_xu_f_v_mask, 0xF, 0x4 }, // 125 |
| 6782 | { Intrinsic::riscv_vfdiv, 0x2, 0x4 }, // 126 |
| 6783 | { Intrinsic::riscv_vfdiv_mask, 0x2, 0x5 }, // 127 |
| 6784 | { Intrinsic::riscv_vfirst, 0xF, 0x1 }, // 128 |
| 6785 | { Intrinsic::riscv_vfirst_mask, 0xF, 0x2 }, // 129 |
| 6786 | { Intrinsic::riscv_vfmacc, 0x1, 0x4 }, // 130 |
| 6787 | { Intrinsic::riscv_vfmacc_mask, 0x1, 0x5 }, // 131 |
| 6788 | { Intrinsic::riscv_vfmadd, 0x1, 0x4 }, // 132 |
| 6789 | { Intrinsic::riscv_vfmadd_mask, 0x1, 0x5 }, // 133 |
| 6790 | { Intrinsic::riscv_vfmax, 0x2, 0x3 }, // 134 |
| 6791 | { Intrinsic::riscv_vfmax_mask, 0x2, 0x4 }, // 135 |
| 6792 | { Intrinsic::riscv_vfmerge, 0x2, 0x4 }, // 136 |
| 6793 | { Intrinsic::riscv_vfmin, 0x2, 0x3 }, // 137 |
| 6794 | { Intrinsic::riscv_vfmin_mask, 0x2, 0x4 }, // 138 |
| 6795 | { Intrinsic::riscv_vfmsac, 0x1, 0x4 }, // 139 |
| 6796 | { Intrinsic::riscv_vfmsac_mask, 0x1, 0x5 }, // 140 |
| 6797 | { Intrinsic::riscv_vfmsub, 0x1, 0x4 }, // 141 |
| 6798 | { Intrinsic::riscv_vfmsub_mask, 0x1, 0x5 }, // 142 |
| 6799 | { Intrinsic::riscv_vfmul, 0x2, 0x4 }, // 143 |
| 6800 | { Intrinsic::riscv_vfmul_mask, 0x2, 0x5 }, // 144 |
| 6801 | { Intrinsic::riscv_vfmv_f_s, 0xF, 0x1F }, // 145 |
| 6802 | { Intrinsic::riscv_vfmv_s_f, 0xF, 0x2 }, // 146 |
| 6803 | { Intrinsic::riscv_vfmv_v_f, 0xF, 0x2 }, // 147 |
| 6804 | { Intrinsic::riscv_vfncvt_f_f_w, 0xF, 0x3 }, // 148 |
| 6805 | { Intrinsic::riscv_vfncvt_f_f_w_mask, 0xF, 0x4 }, // 149 |
| 6806 | { Intrinsic::riscv_vfncvt_f_x_w, 0xF, 0x3 }, // 150 |
| 6807 | { Intrinsic::riscv_vfncvt_f_x_w_mask, 0xF, 0x4 }, // 151 |
| 6808 | { Intrinsic::riscv_vfncvt_f_xu_w, 0xF, 0x3 }, // 152 |
| 6809 | { Intrinsic::riscv_vfncvt_f_xu_w_mask, 0xF, 0x4 }, // 153 |
| 6810 | { Intrinsic::riscv_vfncvt_rod_f_f_w, 0xF, 0x2 }, // 154 |
| 6811 | { Intrinsic::riscv_vfncvt_rod_f_f_w_mask, 0xF, 0x3 }, // 155 |
| 6812 | { Intrinsic::riscv_vfncvt_rtz_x_f_w, 0xF, 0x2 }, // 156 |
| 6813 | { Intrinsic::riscv_vfncvt_rtz_x_f_w_mask, 0xF, 0x3 }, // 157 |
| 6814 | { Intrinsic::riscv_vfncvt_rtz_xu_f_w, 0xF, 0x2 }, // 158 |
| 6815 | { Intrinsic::riscv_vfncvt_rtz_xu_f_w_mask, 0xF, 0x3 }, // 159 |
| 6816 | { Intrinsic::riscv_vfncvt_x_f_w, 0xF, 0x3 }, // 160 |
| 6817 | { Intrinsic::riscv_vfncvt_x_f_w_mask, 0xF, 0x4 }, // 161 |
| 6818 | { Intrinsic::riscv_vfncvt_xu_f_w, 0xF, 0x3 }, // 162 |
| 6819 | { Intrinsic::riscv_vfncvt_xu_f_w_mask, 0xF, 0x4 }, // 163 |
| 6820 | { Intrinsic::riscv_vfncvtbf16_f_f_w, 0xF, 0x3 }, // 164 |
| 6821 | { Intrinsic::riscv_vfncvtbf16_f_f_w_mask, 0xF, 0x4 }, // 165 |
| 6822 | { Intrinsic::riscv_vfnmacc, 0x1, 0x4 }, // 166 |
| 6823 | { Intrinsic::riscv_vfnmacc_mask, 0x1, 0x5 }, // 167 |
| 6824 | { Intrinsic::riscv_vfnmadd, 0x1, 0x4 }, // 168 |
| 6825 | { Intrinsic::riscv_vfnmadd_mask, 0x1, 0x5 }, // 169 |
| 6826 | { Intrinsic::riscv_vfnmsac, 0x1, 0x4 }, // 170 |
| 6827 | { Intrinsic::riscv_vfnmsac_mask, 0x1, 0x5 }, // 171 |
| 6828 | { Intrinsic::riscv_vfnmsub, 0x1, 0x4 }, // 172 |
| 6829 | { Intrinsic::riscv_vfnmsub_mask, 0x1, 0x5 }, // 173 |
| 6830 | { Intrinsic::riscv_vfrdiv, 0x2, 0x4 }, // 174 |
| 6831 | { Intrinsic::riscv_vfrdiv_mask, 0x2, 0x5 }, // 175 |
| 6832 | { Intrinsic::riscv_vfrec7, 0xF, 0x3 }, // 176 |
| 6833 | { Intrinsic::riscv_vfrec7_mask, 0xF, 0x4 }, // 177 |
| 6834 | { Intrinsic::riscv_vfredmax, 0xF, 0x3 }, // 178 |
| 6835 | { Intrinsic::riscv_vfredmax_mask, 0xF, 0x4 }, // 179 |
| 6836 | { Intrinsic::riscv_vfredmin, 0xF, 0x3 }, // 180 |
| 6837 | { Intrinsic::riscv_vfredmin_mask, 0xF, 0x4 }, // 181 |
| 6838 | { Intrinsic::riscv_vfredosum, 0xF, 0x4 }, // 182 |
| 6839 | { Intrinsic::riscv_vfredosum_mask, 0xF, 0x5 }, // 183 |
| 6840 | { Intrinsic::riscv_vfredusum, 0xF, 0x4 }, // 184 |
| 6841 | { Intrinsic::riscv_vfredusum_mask, 0xF, 0x5 }, // 185 |
| 6842 | { Intrinsic::riscv_vfrsqrt7, 0xF, 0x2 }, // 186 |
| 6843 | { Intrinsic::riscv_vfrsqrt7_mask, 0xF, 0x3 }, // 187 |
| 6844 | { Intrinsic::riscv_vfrsub, 0x2, 0x4 }, // 188 |
| 6845 | { Intrinsic::riscv_vfrsub_mask, 0x2, 0x5 }, // 189 |
| 6846 | { Intrinsic::riscv_vfsgnj, 0x2, 0x3 }, // 190 |
| 6847 | { Intrinsic::riscv_vfsgnj_mask, 0x2, 0x4 }, // 191 |
| 6848 | { Intrinsic::riscv_vfsgnjn, 0x2, 0x3 }, // 192 |
| 6849 | { Intrinsic::riscv_vfsgnjn_mask, 0x2, 0x4 }, // 193 |
| 6850 | { Intrinsic::riscv_vfsgnjx, 0x2, 0x3 }, // 194 |
| 6851 | { Intrinsic::riscv_vfsgnjx_mask, 0x2, 0x4 }, // 195 |
| 6852 | { Intrinsic::riscv_vfslide1down, 0x2, 0x3 }, // 196 |
| 6853 | { Intrinsic::riscv_vfslide1down_mask, 0x2, 0x4 }, // 197 |
| 6854 | { Intrinsic::riscv_vfslide1up, 0x2, 0x3 }, // 198 |
| 6855 | { Intrinsic::riscv_vfslide1up_mask, 0x2, 0x4 }, // 199 |
| 6856 | { Intrinsic::riscv_vfsqrt, 0xF, 0x3 }, // 200 |
| 6857 | { Intrinsic::riscv_vfsqrt_mask, 0xF, 0x4 }, // 201 |
| 6858 | { Intrinsic::riscv_vfsub, 0x2, 0x4 }, // 202 |
| 6859 | { Intrinsic::riscv_vfsub_mask, 0x2, 0x5 }, // 203 |
| 6860 | { Intrinsic::riscv_vfwadd, 0x2, 0x4 }, // 204 |
| 6861 | { Intrinsic::riscv_vfwadd_mask, 0x2, 0x5 }, // 205 |
| 6862 | { Intrinsic::riscv_vfwadd_w, 0x2, 0x4 }, // 206 |
| 6863 | { Intrinsic::riscv_vfwadd_w_mask, 0x2, 0x5 }, // 207 |
| 6864 | { Intrinsic::riscv_vfwcvt_f_f_v, 0xF, 0x2 }, // 208 |
| 6865 | { Intrinsic::riscv_vfwcvt_f_f_v_mask, 0xF, 0x3 }, // 209 |
| 6866 | { Intrinsic::riscv_vfwcvt_f_x_v, 0xF, 0x2 }, // 210 |
| 6867 | { Intrinsic::riscv_vfwcvt_f_x_v_mask, 0xF, 0x3 }, // 211 |
| 6868 | { Intrinsic::riscv_vfwcvt_f_xu_v, 0xF, 0x2 }, // 212 |
| 6869 | { Intrinsic::riscv_vfwcvt_f_xu_v_mask, 0xF, 0x3 }, // 213 |
| 6870 | { Intrinsic::riscv_vfwcvt_rtz_x_f_v, 0xF, 0x2 }, // 214 |
| 6871 | { Intrinsic::riscv_vfwcvt_rtz_x_f_v_mask, 0xF, 0x3 }, // 215 |
| 6872 | { Intrinsic::riscv_vfwcvt_rtz_xu_f_v, 0xF, 0x2 }, // 216 |
| 6873 | { Intrinsic::riscv_vfwcvt_rtz_xu_f_v_mask, 0xF, 0x3 }, // 217 |
| 6874 | { Intrinsic::riscv_vfwcvt_x_f_v, 0xF, 0x3 }, // 218 |
| 6875 | { Intrinsic::riscv_vfwcvt_x_f_v_mask, 0xF, 0x4 }, // 219 |
| 6876 | { Intrinsic::riscv_vfwcvt_xu_f_v, 0xF, 0x3 }, // 220 |
| 6877 | { Intrinsic::riscv_vfwcvt_xu_f_v_mask, 0xF, 0x4 }, // 221 |
| 6878 | { Intrinsic::riscv_vfwcvtbf16_f_f_v, 0xF, 0x2 }, // 222 |
| 6879 | { Intrinsic::riscv_vfwcvtbf16_f_f_v_mask, 0xF, 0x3 }, // 223 |
| 6880 | { Intrinsic::riscv_vfwmacc, 0x1, 0x4 }, // 224 |
| 6881 | { Intrinsic::riscv_vfwmacc_mask, 0x1, 0x5 }, // 225 |
| 6882 | { Intrinsic::riscv_vfwmaccbf16, 0x1, 0x4 }, // 226 |
| 6883 | { Intrinsic::riscv_vfwmaccbf16_mask, 0x1, 0x5 }, // 227 |
| 6884 | { Intrinsic::riscv_vfwmsac, 0x1, 0x4 }, // 228 |
| 6885 | { Intrinsic::riscv_vfwmsac_mask, 0x1, 0x5 }, // 229 |
| 6886 | { Intrinsic::riscv_vfwmul, 0x2, 0x4 }, // 230 |
| 6887 | { Intrinsic::riscv_vfwmul_mask, 0x2, 0x5 }, // 231 |
| 6888 | { Intrinsic::riscv_vfwnmacc, 0x1, 0x4 }, // 232 |
| 6889 | { Intrinsic::riscv_vfwnmacc_mask, 0x1, 0x5 }, // 233 |
| 6890 | { Intrinsic::riscv_vfwnmsac, 0x1, 0x4 }, // 234 |
| 6891 | { Intrinsic::riscv_vfwnmsac_mask, 0x1, 0x5 }, // 235 |
| 6892 | { Intrinsic::riscv_vfwredosum, 0xF, 0x4 }, // 236 |
| 6893 | { Intrinsic::riscv_vfwredosum_mask, 0xF, 0x5 }, // 237 |
| 6894 | { Intrinsic::riscv_vfwredusum, 0xF, 0x4 }, // 238 |
| 6895 | { Intrinsic::riscv_vfwredusum_mask, 0xF, 0x5 }, // 239 |
| 6896 | { Intrinsic::riscv_vfwsub, 0x2, 0x4 }, // 240 |
| 6897 | { Intrinsic::riscv_vfwsub_mask, 0x2, 0x5 }, // 241 |
| 6898 | { Intrinsic::riscv_vfwsub_w, 0x2, 0x4 }, // 242 |
| 6899 | { Intrinsic::riscv_vfwsub_w_mask, 0x2, 0x5 }, // 243 |
| 6900 | { Intrinsic::riscv_vghsh, 0x2, 0x3 }, // 244 |
| 6901 | { Intrinsic::riscv_vgmul_vv, 0xF, 0x2 }, // 245 |
| 6902 | { Intrinsic::riscv_vid, 0xF, 0x1 }, // 246 |
| 6903 | { Intrinsic::riscv_vid_mask, 0xF, 0x2 }, // 247 |
| 6904 | { Intrinsic::riscv_viota, 0xF, 0x2 }, // 248 |
| 6905 | { Intrinsic::riscv_viota_mask, 0xF, 0x3 }, // 249 |
| 6906 | { Intrinsic::riscv_vle, 0xF, 0x2 }, // 250 |
| 6907 | { Intrinsic::riscv_vle_mask, 0xF, 0x3 }, // 251 |
| 6908 | { Intrinsic::riscv_vleff, 0xF, 0x2 }, // 252 |
| 6909 | { Intrinsic::riscv_vleff_mask, 0xF, 0x3 }, // 253 |
| 6910 | { Intrinsic::riscv_vlm, 0xF, 0x1 }, // 254 |
| 6911 | { Intrinsic::riscv_vloxei, 0xF, 0x3 }, // 255 |
| 6912 | { Intrinsic::riscv_vloxei_mask, 0xF, 0x4 }, // 256 |
| 6913 | { Intrinsic::riscv_vloxseg2, 0xF, 0x4 }, // 257 |
| 6914 | { Intrinsic::riscv_vloxseg2_mask, 0xF, 0x5 }, // 258 |
| 6915 | { Intrinsic::riscv_vloxseg3, 0xF, 0x5 }, // 259 |
| 6916 | { Intrinsic::riscv_vloxseg3_mask, 0xF, 0x6 }, // 260 |
| 6917 | { Intrinsic::riscv_vloxseg4, 0xF, 0x6 }, // 261 |
| 6918 | { Intrinsic::riscv_vloxseg4_mask, 0xF, 0x7 }, // 262 |
| 6919 | { Intrinsic::riscv_vloxseg5, 0xF, 0x7 }, // 263 |
| 6920 | { Intrinsic::riscv_vloxseg5_mask, 0xF, 0x8 }, // 264 |
| 6921 | { Intrinsic::riscv_vloxseg6, 0xF, 0x8 }, // 265 |
| 6922 | { Intrinsic::riscv_vloxseg6_mask, 0xF, 0x9 }, // 266 |
| 6923 | { Intrinsic::riscv_vloxseg7, 0xF, 0x9 }, // 267 |
| 6924 | { Intrinsic::riscv_vloxseg7_mask, 0xF, 0xA }, // 268 |
| 6925 | { Intrinsic::riscv_vloxseg8, 0xF, 0xA }, // 269 |
| 6926 | { Intrinsic::riscv_vloxseg8_mask, 0xF, 0xB }, // 270 |
| 6927 | { Intrinsic::riscv_vlse, 0xF, 0x3 }, // 271 |
| 6928 | { Intrinsic::riscv_vlse_mask, 0xF, 0x4 }, // 272 |
| 6929 | { Intrinsic::riscv_vlseg2, 0xF, 0x3 }, // 273 |
| 6930 | { Intrinsic::riscv_vlseg2_mask, 0xF, 0x4 }, // 274 |
| 6931 | { Intrinsic::riscv_vlseg2ff, 0xF, 0x3 }, // 275 |
| 6932 | { Intrinsic::riscv_vlseg2ff_mask, 0xF, 0x4 }, // 276 |
| 6933 | { Intrinsic::riscv_vlseg3, 0xF, 0x4 }, // 277 |
| 6934 | { Intrinsic::riscv_vlseg3_mask, 0xF, 0x5 }, // 278 |
| 6935 | { Intrinsic::riscv_vlseg3ff, 0xF, 0x4 }, // 279 |
| 6936 | { Intrinsic::riscv_vlseg3ff_mask, 0xF, 0x5 }, // 280 |
| 6937 | { Intrinsic::riscv_vlseg4, 0xF, 0x5 }, // 281 |
| 6938 | { Intrinsic::riscv_vlseg4_mask, 0xF, 0x6 }, // 282 |
| 6939 | { Intrinsic::riscv_vlseg4ff, 0xF, 0x5 }, // 283 |
| 6940 | { Intrinsic::riscv_vlseg4ff_mask, 0xF, 0x6 }, // 284 |
| 6941 | { Intrinsic::riscv_vlseg5, 0xF, 0x6 }, // 285 |
| 6942 | { Intrinsic::riscv_vlseg5_mask, 0xF, 0x7 }, // 286 |
| 6943 | { Intrinsic::riscv_vlseg5ff, 0xF, 0x6 }, // 287 |
| 6944 | { Intrinsic::riscv_vlseg5ff_mask, 0xF, 0x7 }, // 288 |
| 6945 | { Intrinsic::riscv_vlseg6, 0xF, 0x7 }, // 289 |
| 6946 | { Intrinsic::riscv_vlseg6_mask, 0xF, 0x8 }, // 290 |
| 6947 | { Intrinsic::riscv_vlseg6ff, 0xF, 0x7 }, // 291 |
| 6948 | { Intrinsic::riscv_vlseg6ff_mask, 0xF, 0x8 }, // 292 |
| 6949 | { Intrinsic::riscv_vlseg7, 0xF, 0x8 }, // 293 |
| 6950 | { Intrinsic::riscv_vlseg7_mask, 0xF, 0x9 }, // 294 |
| 6951 | { Intrinsic::riscv_vlseg7ff, 0xF, 0x8 }, // 295 |
| 6952 | { Intrinsic::riscv_vlseg7ff_mask, 0xF, 0x9 }, // 296 |
| 6953 | { Intrinsic::riscv_vlseg8, 0xF, 0x9 }, // 297 |
| 6954 | { Intrinsic::riscv_vlseg8_mask, 0xF, 0xA }, // 298 |
| 6955 | { Intrinsic::riscv_vlseg8ff, 0xF, 0x9 }, // 299 |
| 6956 | { Intrinsic::riscv_vlseg8ff_mask, 0xF, 0xA }, // 300 |
| 6957 | { Intrinsic::riscv_vlsseg2, 0xF, 0x4 }, // 301 |
| 6958 | { Intrinsic::riscv_vlsseg2_mask, 0xF, 0x5 }, // 302 |
| 6959 | { Intrinsic::riscv_vlsseg3, 0xF, 0x5 }, // 303 |
| 6960 | { Intrinsic::riscv_vlsseg3_mask, 0xF, 0x6 }, // 304 |
| 6961 | { Intrinsic::riscv_vlsseg4, 0xF, 0x6 }, // 305 |
| 6962 | { Intrinsic::riscv_vlsseg4_mask, 0xF, 0x7 }, // 306 |
| 6963 | { Intrinsic::riscv_vlsseg5, 0xF, 0x7 }, // 307 |
| 6964 | { Intrinsic::riscv_vlsseg5_mask, 0xF, 0x8 }, // 308 |
| 6965 | { Intrinsic::riscv_vlsseg6, 0xF, 0x8 }, // 309 |
| 6966 | { Intrinsic::riscv_vlsseg6_mask, 0xF, 0x9 }, // 310 |
| 6967 | { Intrinsic::riscv_vlsseg7, 0xF, 0x9 }, // 311 |
| 6968 | { Intrinsic::riscv_vlsseg7_mask, 0xF, 0xA }, // 312 |
| 6969 | { Intrinsic::riscv_vlsseg8, 0xF, 0xA }, // 313 |
| 6970 | { Intrinsic::riscv_vlsseg8_mask, 0xF, 0xB }, // 314 |
| 6971 | { Intrinsic::riscv_vluxei, 0xF, 0x3 }, // 315 |
| 6972 | { Intrinsic::riscv_vluxei_mask, 0xF, 0x4 }, // 316 |
| 6973 | { Intrinsic::riscv_vluxseg2, 0xF, 0x4 }, // 317 |
| 6974 | { Intrinsic::riscv_vluxseg2_mask, 0xF, 0x5 }, // 318 |
| 6975 | { Intrinsic::riscv_vluxseg3, 0xF, 0x5 }, // 319 |
| 6976 | { Intrinsic::riscv_vluxseg3_mask, 0xF, 0x6 }, // 320 |
| 6977 | { Intrinsic::riscv_vluxseg4, 0xF, 0x6 }, // 321 |
| 6978 | { Intrinsic::riscv_vluxseg4_mask, 0xF, 0x7 }, // 322 |
| 6979 | { Intrinsic::riscv_vluxseg5, 0xF, 0x7 }, // 323 |
| 6980 | { Intrinsic::riscv_vluxseg5_mask, 0xF, 0x8 }, // 324 |
| 6981 | { Intrinsic::riscv_vluxseg6, 0xF, 0x8 }, // 325 |
| 6982 | { Intrinsic::riscv_vluxseg6_mask, 0xF, 0x9 }, // 326 |
| 6983 | { Intrinsic::riscv_vluxseg7, 0xF, 0x9 }, // 327 |
| 6984 | { Intrinsic::riscv_vluxseg7_mask, 0xF, 0xA }, // 328 |
| 6985 | { Intrinsic::riscv_vluxseg8, 0xF, 0xA }, // 329 |
| 6986 | { Intrinsic::riscv_vluxseg8_mask, 0xF, 0xB }, // 330 |
| 6987 | { Intrinsic::riscv_vmacc, 0x1, 0x3 }, // 331 |
| 6988 | { Intrinsic::riscv_vmacc_mask, 0x1, 0x4 }, // 332 |
| 6989 | { Intrinsic::riscv_vmadc, 0x1, 0x2 }, // 333 |
| 6990 | { Intrinsic::riscv_vmadc_carry_in, 0x1, 0x3 }, // 334 |
| 6991 | { Intrinsic::riscv_vmadd, 0x1, 0x3 }, // 335 |
| 6992 | { Intrinsic::riscv_vmadd_mask, 0x1, 0x4 }, // 336 |
| 6993 | { Intrinsic::riscv_vmand, 0xF, 0x2 }, // 337 |
| 6994 | { Intrinsic::riscv_vmandn, 0xF, 0x2 }, // 338 |
| 6995 | { Intrinsic::riscv_vmax, 0x2, 0x3 }, // 339 |
| 6996 | { Intrinsic::riscv_vmax_mask, 0x2, 0x4 }, // 340 |
| 6997 | { Intrinsic::riscv_vmaxu, 0x2, 0x3 }, // 341 |
| 6998 | { Intrinsic::riscv_vmaxu_mask, 0x2, 0x4 }, // 342 |
| 6999 | { Intrinsic::riscv_vmclr, 0xF, 0x1 }, // 343 |
| 7000 | { Intrinsic::riscv_vmerge, 0x2, 0x4 }, // 344 |
| 7001 | { Intrinsic::riscv_vmfeq, 0x1, 0x2 }, // 345 |
| 7002 | { Intrinsic::riscv_vmfeq_mask, 0x2, 0x4 }, // 346 |
| 7003 | { Intrinsic::riscv_vmfge, 0x1, 0x2 }, // 347 |
| 7004 | { Intrinsic::riscv_vmfge_mask, 0x2, 0x4 }, // 348 |
| 7005 | { Intrinsic::riscv_vmfgt, 0x1, 0x2 }, // 349 |
| 7006 | { Intrinsic::riscv_vmfgt_mask, 0x2, 0x4 }, // 350 |
| 7007 | { Intrinsic::riscv_vmfle, 0x1, 0x2 }, // 351 |
| 7008 | { Intrinsic::riscv_vmfle_mask, 0x2, 0x4 }, // 352 |
| 7009 | { Intrinsic::riscv_vmflt, 0x1, 0x2 }, // 353 |
| 7010 | { Intrinsic::riscv_vmflt_mask, 0x2, 0x4 }, // 354 |
| 7011 | { Intrinsic::riscv_vmfne, 0x1, 0x2 }, // 355 |
| 7012 | { Intrinsic::riscv_vmfne_mask, 0x2, 0x4 }, // 356 |
| 7013 | { Intrinsic::riscv_vmin, 0x2, 0x3 }, // 357 |
| 7014 | { Intrinsic::riscv_vmin_mask, 0x2, 0x4 }, // 358 |
| 7015 | { Intrinsic::riscv_vminu, 0x2, 0x3 }, // 359 |
| 7016 | { Intrinsic::riscv_vminu_mask, 0x2, 0x4 }, // 360 |
| 7017 | { Intrinsic::riscv_vmnand, 0xF, 0x2 }, // 361 |
| 7018 | { Intrinsic::riscv_vmnor, 0xF, 0x2 }, // 362 |
| 7019 | { Intrinsic::riscv_vmor, 0xF, 0x2 }, // 363 |
| 7020 | { Intrinsic::riscv_vmorn, 0xF, 0x2 }, // 364 |
| 7021 | { Intrinsic::riscv_vmsbc, 0x1, 0x2 }, // 365 |
| 7022 | { Intrinsic::riscv_vmsbc_borrow_in, 0x1, 0x3 }, // 366 |
| 7023 | { Intrinsic::riscv_vmsbf, 0xF, 0x1 }, // 367 |
| 7024 | { Intrinsic::riscv_vmsbf_mask, 0xF, 0x3 }, // 368 |
| 7025 | { Intrinsic::riscv_vmseq, 0x1, 0x2 }, // 369 |
| 7026 | { Intrinsic::riscv_vmseq_mask, 0x2, 0x4 }, // 370 |
| 7027 | { Intrinsic::riscv_vmset, 0xF, 0x1 }, // 371 |
| 7028 | { Intrinsic::riscv_vmsge, 0x1, 0x2 }, // 372 |
| 7029 | { Intrinsic::riscv_vmsge_mask, 0x2, 0x4 }, // 373 |
| 7030 | { Intrinsic::riscv_vmsgeu, 0x1, 0x2 }, // 374 |
| 7031 | { Intrinsic::riscv_vmsgeu_mask, 0x2, 0x4 }, // 375 |
| 7032 | { Intrinsic::riscv_vmsgt, 0x1, 0x2 }, // 376 |
| 7033 | { Intrinsic::riscv_vmsgt_mask, 0x2, 0x4 }, // 377 |
| 7034 | { Intrinsic::riscv_vmsgtu, 0x1, 0x2 }, // 378 |
| 7035 | { Intrinsic::riscv_vmsgtu_mask, 0x2, 0x4 }, // 379 |
| 7036 | { Intrinsic::riscv_vmsif, 0xF, 0x1 }, // 380 |
| 7037 | { Intrinsic::riscv_vmsif_mask, 0xF, 0x3 }, // 381 |
| 7038 | { Intrinsic::riscv_vmsle, 0x1, 0x2 }, // 382 |
| 7039 | { Intrinsic::riscv_vmsle_mask, 0x2, 0x4 }, // 383 |
| 7040 | { Intrinsic::riscv_vmsleu, 0x1, 0x2 }, // 384 |
| 7041 | { Intrinsic::riscv_vmsleu_mask, 0x2, 0x4 }, // 385 |
| 7042 | { Intrinsic::riscv_vmslt, 0x1, 0x2 }, // 386 |
| 7043 | { Intrinsic::riscv_vmslt_mask, 0x2, 0x4 }, // 387 |
| 7044 | { Intrinsic::riscv_vmsltu, 0x1, 0x2 }, // 388 |
| 7045 | { Intrinsic::riscv_vmsltu_mask, 0x2, 0x4 }, // 389 |
| 7046 | { Intrinsic::riscv_vmsne, 0x1, 0x2 }, // 390 |
| 7047 | { Intrinsic::riscv_vmsne_mask, 0x2, 0x4 }, // 391 |
| 7048 | { Intrinsic::riscv_vmsof, 0xF, 0x1 }, // 392 |
| 7049 | { Intrinsic::riscv_vmsof_mask, 0xF, 0x3 }, // 393 |
| 7050 | { Intrinsic::riscv_vmul, 0x2, 0x3 }, // 394 |
| 7051 | { Intrinsic::riscv_vmul_mask, 0x2, 0x4 }, // 395 |
| 7052 | { Intrinsic::riscv_vmulh, 0x2, 0x3 }, // 396 |
| 7053 | { Intrinsic::riscv_vmulh_mask, 0x2, 0x4 }, // 397 |
| 7054 | { Intrinsic::riscv_vmulhsu, 0x2, 0x3 }, // 398 |
| 7055 | { Intrinsic::riscv_vmulhsu_mask, 0x2, 0x4 }, // 399 |
| 7056 | { Intrinsic::riscv_vmulhu, 0x2, 0x3 }, // 400 |
| 7057 | { Intrinsic::riscv_vmulhu_mask, 0x2, 0x4 }, // 401 |
| 7058 | { Intrinsic::riscv_vmv_s_x, 0xF, 0x2 }, // 402 |
| 7059 | { Intrinsic::riscv_vmv_v_v, 0xF, 0x2 }, // 403 |
| 7060 | { Intrinsic::riscv_vmv_v_x, 0xF, 0x2 }, // 404 |
| 7061 | { Intrinsic::riscv_vmv_x_s, 0xF, 0x1F }, // 405 |
| 7062 | { Intrinsic::riscv_vmxnor, 0xF, 0x2 }, // 406 |
| 7063 | { Intrinsic::riscv_vmxor, 0xF, 0x2 }, // 407 |
| 7064 | { Intrinsic::riscv_vnclip, 0xF, 0x4 }, // 408 |
| 7065 | { Intrinsic::riscv_vnclip_mask, 0xF, 0x5 }, // 409 |
| 7066 | { Intrinsic::riscv_vnclipu, 0xF, 0x4 }, // 410 |
| 7067 | { Intrinsic::riscv_vnclipu_mask, 0xF, 0x5 }, // 411 |
| 7068 | { Intrinsic::riscv_vnmsac, 0x1, 0x3 }, // 412 |
| 7069 | { Intrinsic::riscv_vnmsac_mask, 0x1, 0x4 }, // 413 |
| 7070 | { Intrinsic::riscv_vnmsub, 0x1, 0x3 }, // 414 |
| 7071 | { Intrinsic::riscv_vnmsub_mask, 0x1, 0x4 }, // 415 |
| 7072 | { Intrinsic::riscv_vnsra, 0xF, 0x3 }, // 416 |
| 7073 | { Intrinsic::riscv_vnsra_mask, 0xF, 0x4 }, // 417 |
| 7074 | { Intrinsic::riscv_vnsrl, 0xF, 0x3 }, // 418 |
| 7075 | { Intrinsic::riscv_vnsrl_mask, 0xF, 0x4 }, // 419 |
| 7076 | { Intrinsic::riscv_vor, 0x2, 0x3 }, // 420 |
| 7077 | { Intrinsic::riscv_vor_mask, 0x2, 0x4 }, // 421 |
| 7078 | { Intrinsic::riscv_vredand, 0xF, 0x3 }, // 422 |
| 7079 | { Intrinsic::riscv_vredand_mask, 0xF, 0x4 }, // 423 |
| 7080 | { Intrinsic::riscv_vredmax, 0xF, 0x3 }, // 424 |
| 7081 | { Intrinsic::riscv_vredmax_mask, 0xF, 0x4 }, // 425 |
| 7082 | { Intrinsic::riscv_vredmaxu, 0xF, 0x3 }, // 426 |
| 7083 | { Intrinsic::riscv_vredmaxu_mask, 0xF, 0x4 }, // 427 |
| 7084 | { Intrinsic::riscv_vredmin, 0xF, 0x3 }, // 428 |
| 7085 | { Intrinsic::riscv_vredmin_mask, 0xF, 0x4 }, // 429 |
| 7086 | { Intrinsic::riscv_vredminu, 0xF, 0x3 }, // 430 |
| 7087 | { Intrinsic::riscv_vredminu_mask, 0xF, 0x4 }, // 431 |
| 7088 | { Intrinsic::riscv_vredor, 0xF, 0x3 }, // 432 |
| 7089 | { Intrinsic::riscv_vredor_mask, 0xF, 0x4 }, // 433 |
| 7090 | { Intrinsic::riscv_vredsum, 0xF, 0x3 }, // 434 |
| 7091 | { Intrinsic::riscv_vredsum_mask, 0xF, 0x4 }, // 435 |
| 7092 | { Intrinsic::riscv_vredxor, 0xF, 0x3 }, // 436 |
| 7093 | { Intrinsic::riscv_vredxor_mask, 0xF, 0x4 }, // 437 |
| 7094 | { Intrinsic::riscv_vrem, 0x2, 0x3 }, // 438 |
| 7095 | { Intrinsic::riscv_vrem_mask, 0x2, 0x4 }, // 439 |
| 7096 | { Intrinsic::riscv_vremu, 0x2, 0x3 }, // 440 |
| 7097 | { Intrinsic::riscv_vremu_mask, 0x2, 0x4 }, // 441 |
| 7098 | { Intrinsic::riscv_vrev8, 0xF, 0x2 }, // 442 |
| 7099 | { Intrinsic::riscv_vrev8_mask, 0xF, 0x3 }, // 443 |
| 7100 | { Intrinsic::riscv_vrgather_vv, 0xF, 0x3 }, // 444 |
| 7101 | { Intrinsic::riscv_vrgather_vv_mask, 0xF, 0x4 }, // 445 |
| 7102 | { Intrinsic::riscv_vrgather_vx, 0xF, 0x3 }, // 446 |
| 7103 | { Intrinsic::riscv_vrgather_vx_mask, 0xF, 0x4 }, // 447 |
| 7104 | { Intrinsic::riscv_vrgatherei16_vv, 0xF, 0x3 }, // 448 |
| 7105 | { Intrinsic::riscv_vrgatherei16_vv_mask, 0xF, 0x4 }, // 449 |
| 7106 | { Intrinsic::riscv_vrol, 0x2, 0x3 }, // 450 |
| 7107 | { Intrinsic::riscv_vrol_mask, 0x2, 0x4 }, // 451 |
| 7108 | { Intrinsic::riscv_vror, 0x2, 0x3 }, // 452 |
| 7109 | { Intrinsic::riscv_vror_mask, 0x2, 0x4 }, // 453 |
| 7110 | { Intrinsic::riscv_vrsub, 0x2, 0x3 }, // 454 |
| 7111 | { Intrinsic::riscv_vrsub_mask, 0x2, 0x4 }, // 455 |
| 7112 | { Intrinsic::riscv_vsadd, 0x2, 0x3 }, // 456 |
| 7113 | { Intrinsic::riscv_vsadd_mask, 0x2, 0x4 }, // 457 |
| 7114 | { Intrinsic::riscv_vsaddu, 0x2, 0x3 }, // 458 |
| 7115 | { Intrinsic::riscv_vsaddu_mask, 0x2, 0x4 }, // 459 |
| 7116 | { Intrinsic::riscv_vsbc, 0x2, 0x4 }, // 460 |
| 7117 | { Intrinsic::riscv_vse, 0xF, 0x2 }, // 461 |
| 7118 | { Intrinsic::riscv_vse_mask, 0xF, 0x3 }, // 462 |
| 7119 | { Intrinsic::riscv_vsext, 0xF, 0x2 }, // 463 |
| 7120 | { Intrinsic::riscv_vsext_mask, 0xF, 0x3 }, // 464 |
| 7121 | { Intrinsic::riscv_vsha2ch, 0x2, 0x3 }, // 465 |
| 7122 | { Intrinsic::riscv_vsha2cl, 0x2, 0x3 }, // 466 |
| 7123 | { Intrinsic::riscv_vsha2ms, 0x2, 0x3 }, // 467 |
| 7124 | { Intrinsic::riscv_vslide1down, 0x2, 0x3 }, // 468 |
| 7125 | { Intrinsic::riscv_vslide1down_mask, 0x2, 0x4 }, // 469 |
| 7126 | { Intrinsic::riscv_vslide1up, 0x2, 0x3 }, // 470 |
| 7127 | { Intrinsic::riscv_vslide1up_mask, 0x2, 0x4 }, // 471 |
| 7128 | { Intrinsic::riscv_vslidedown, 0xF, 0x3 }, // 472 |
| 7129 | { Intrinsic::riscv_vslidedown_mask, 0xF, 0x4 }, // 473 |
| 7130 | { Intrinsic::riscv_vslideup, 0xF, 0x3 }, // 474 |
| 7131 | { Intrinsic::riscv_vslideup_mask, 0xF, 0x4 }, // 475 |
| 7132 | { Intrinsic::riscv_vsll, 0xF, 0x3 }, // 476 |
| 7133 | { Intrinsic::riscv_vsll_mask, 0xF, 0x4 }, // 477 |
| 7134 | { Intrinsic::riscv_vsm, 0xF, 0x2 }, // 478 |
| 7135 | { Intrinsic::riscv_vsm3c, 0x2, 0x3 }, // 479 |
| 7136 | { Intrinsic::riscv_vsm3me, 0x2, 0x3 }, // 480 |
| 7137 | { Intrinsic::riscv_vsm4k, 0x2, 0x3 }, // 481 |
| 7138 | { Intrinsic::riscv_vsm4r_vs, 0xF, 0x2 }, // 482 |
| 7139 | { Intrinsic::riscv_vsm4r_vv, 0xF, 0x2 }, // 483 |
| 7140 | { Intrinsic::riscv_vsmul, 0x2, 0x4 }, // 484 |
| 7141 | { Intrinsic::riscv_vsmul_mask, 0x2, 0x5 }, // 485 |
| 7142 | { Intrinsic::riscv_vsoxei, 0xF, 0x3 }, // 486 |
| 7143 | { Intrinsic::riscv_vsoxei_mask, 0xF, 0x4 }, // 487 |
| 7144 | { Intrinsic::riscv_vsoxseg2, 0xF, 0x4 }, // 488 |
| 7145 | { Intrinsic::riscv_vsoxseg2_mask, 0xF, 0x5 }, // 489 |
| 7146 | { Intrinsic::riscv_vsoxseg3, 0xF, 0x5 }, // 490 |
| 7147 | { Intrinsic::riscv_vsoxseg3_mask, 0xF, 0x6 }, // 491 |
| 7148 | { Intrinsic::riscv_vsoxseg4, 0xF, 0x6 }, // 492 |
| 7149 | { Intrinsic::riscv_vsoxseg4_mask, 0xF, 0x7 }, // 493 |
| 7150 | { Intrinsic::riscv_vsoxseg5, 0xF, 0x7 }, // 494 |
| 7151 | { Intrinsic::riscv_vsoxseg5_mask, 0xF, 0x8 }, // 495 |
| 7152 | { Intrinsic::riscv_vsoxseg6, 0xF, 0x8 }, // 496 |
| 7153 | { Intrinsic::riscv_vsoxseg6_mask, 0xF, 0x9 }, // 497 |
| 7154 | { Intrinsic::riscv_vsoxseg7, 0xF, 0x9 }, // 498 |
| 7155 | { Intrinsic::riscv_vsoxseg7_mask, 0xF, 0xA }, // 499 |
| 7156 | { Intrinsic::riscv_vsoxseg8, 0xF, 0xA }, // 500 |
| 7157 | { Intrinsic::riscv_vsoxseg8_mask, 0xF, 0xB }, // 501 |
| 7158 | { Intrinsic::riscv_vsra, 0xF, 0x3 }, // 502 |
| 7159 | { Intrinsic::riscv_vsra_mask, 0xF, 0x4 }, // 503 |
| 7160 | { Intrinsic::riscv_vsrl, 0xF, 0x3 }, // 504 |
| 7161 | { Intrinsic::riscv_vsrl_mask, 0xF, 0x4 }, // 505 |
| 7162 | { Intrinsic::riscv_vsse, 0xF, 0x3 }, // 506 |
| 7163 | { Intrinsic::riscv_vsse_mask, 0xF, 0x4 }, // 507 |
| 7164 | { Intrinsic::riscv_vsseg2, 0xF, 0x3 }, // 508 |
| 7165 | { Intrinsic::riscv_vsseg2_mask, 0xF, 0x4 }, // 509 |
| 7166 | { Intrinsic::riscv_vsseg3, 0xF, 0x4 }, // 510 |
| 7167 | { Intrinsic::riscv_vsseg3_mask, 0xF, 0x5 }, // 511 |
| 7168 | { Intrinsic::riscv_vsseg4, 0xF, 0x5 }, // 512 |
| 7169 | { Intrinsic::riscv_vsseg4_mask, 0xF, 0x6 }, // 513 |
| 7170 | { Intrinsic::riscv_vsseg5, 0xF, 0x6 }, // 514 |
| 7171 | { Intrinsic::riscv_vsseg5_mask, 0xF, 0x7 }, // 515 |
| 7172 | { Intrinsic::riscv_vsseg6, 0xF, 0x7 }, // 516 |
| 7173 | { Intrinsic::riscv_vsseg6_mask, 0xF, 0x8 }, // 517 |
| 7174 | { Intrinsic::riscv_vsseg7, 0xF, 0x8 }, // 518 |
| 7175 | { Intrinsic::riscv_vsseg7_mask, 0xF, 0x9 }, // 519 |
| 7176 | { Intrinsic::riscv_vsseg8, 0xF, 0x9 }, // 520 |
| 7177 | { Intrinsic::riscv_vsseg8_mask, 0xF, 0xA }, // 521 |
| 7178 | { Intrinsic::riscv_vssra, 0xF, 0x4 }, // 522 |
| 7179 | { Intrinsic::riscv_vssra_mask, 0xF, 0x5 }, // 523 |
| 7180 | { Intrinsic::riscv_vssrl, 0xF, 0x4 }, // 524 |
| 7181 | { Intrinsic::riscv_vssrl_mask, 0xF, 0x5 }, // 525 |
| 7182 | { Intrinsic::riscv_vssseg2, 0xF, 0x4 }, // 526 |
| 7183 | { Intrinsic::riscv_vssseg2_mask, 0xF, 0x5 }, // 527 |
| 7184 | { Intrinsic::riscv_vssseg3, 0xF, 0x5 }, // 528 |
| 7185 | { Intrinsic::riscv_vssseg3_mask, 0xF, 0x6 }, // 529 |
| 7186 | { Intrinsic::riscv_vssseg4, 0xF, 0x6 }, // 530 |
| 7187 | { Intrinsic::riscv_vssseg4_mask, 0xF, 0x7 }, // 531 |
| 7188 | { Intrinsic::riscv_vssseg5, 0xF, 0x7 }, // 532 |
| 7189 | { Intrinsic::riscv_vssseg5_mask, 0xF, 0x8 }, // 533 |
| 7190 | { Intrinsic::riscv_vssseg6, 0xF, 0x8 }, // 534 |
| 7191 | { Intrinsic::riscv_vssseg6_mask, 0xF, 0x9 }, // 535 |
| 7192 | { Intrinsic::riscv_vssseg7, 0xF, 0x9 }, // 536 |
| 7193 | { Intrinsic::riscv_vssseg7_mask, 0xF, 0xA }, // 537 |
| 7194 | { Intrinsic::riscv_vssseg8, 0xF, 0xA }, // 538 |
| 7195 | { Intrinsic::riscv_vssseg8_mask, 0xF, 0xB }, // 539 |
| 7196 | { Intrinsic::riscv_vssub, 0x2, 0x3 }, // 540 |
| 7197 | { Intrinsic::riscv_vssub_mask, 0x2, 0x4 }, // 541 |
| 7198 | { Intrinsic::riscv_vssubu, 0x2, 0x3 }, // 542 |
| 7199 | { Intrinsic::riscv_vssubu_mask, 0x2, 0x4 }, // 543 |
| 7200 | { Intrinsic::riscv_vsub, 0x2, 0x3 }, // 544 |
| 7201 | { Intrinsic::riscv_vsub_mask, 0x2, 0x4 }, // 545 |
| 7202 | { Intrinsic::riscv_vsuxei, 0xF, 0x3 }, // 546 |
| 7203 | { Intrinsic::riscv_vsuxei_mask, 0xF, 0x4 }, // 547 |
| 7204 | { Intrinsic::riscv_vsuxseg2, 0xF, 0x4 }, // 548 |
| 7205 | { Intrinsic::riscv_vsuxseg2_mask, 0xF, 0x5 }, // 549 |
| 7206 | { Intrinsic::riscv_vsuxseg3, 0xF, 0x5 }, // 550 |
| 7207 | { Intrinsic::riscv_vsuxseg3_mask, 0xF, 0x6 }, // 551 |
| 7208 | { Intrinsic::riscv_vsuxseg4, 0xF, 0x6 }, // 552 |
| 7209 | { Intrinsic::riscv_vsuxseg4_mask, 0xF, 0x7 }, // 553 |
| 7210 | { Intrinsic::riscv_vsuxseg5, 0xF, 0x7 }, // 554 |
| 7211 | { Intrinsic::riscv_vsuxseg5_mask, 0xF, 0x8 }, // 555 |
| 7212 | { Intrinsic::riscv_vsuxseg6, 0xF, 0x8 }, // 556 |
| 7213 | { Intrinsic::riscv_vsuxseg6_mask, 0xF, 0x9 }, // 557 |
| 7214 | { Intrinsic::riscv_vsuxseg7, 0xF, 0x9 }, // 558 |
| 7215 | { Intrinsic::riscv_vsuxseg7_mask, 0xF, 0xA }, // 559 |
| 7216 | { Intrinsic::riscv_vsuxseg8, 0xF, 0xA }, // 560 |
| 7217 | { Intrinsic::riscv_vsuxseg8_mask, 0xF, 0xB }, // 561 |
| 7218 | { Intrinsic::riscv_vwadd, 0x2, 0x3 }, // 562 |
| 7219 | { Intrinsic::riscv_vwadd_mask, 0x2, 0x4 }, // 563 |
| 7220 | { Intrinsic::riscv_vwadd_w, 0x2, 0x3 }, // 564 |
| 7221 | { Intrinsic::riscv_vwadd_w_mask, 0x2, 0x4 }, // 565 |
| 7222 | { Intrinsic::riscv_vwaddu, 0x2, 0x3 }, // 566 |
| 7223 | { Intrinsic::riscv_vwaddu_mask, 0x2, 0x4 }, // 567 |
| 7224 | { Intrinsic::riscv_vwaddu_w, 0x2, 0x3 }, // 568 |
| 7225 | { Intrinsic::riscv_vwaddu_w_mask, 0x2, 0x4 }, // 569 |
| 7226 | { Intrinsic::riscv_vwmacc, 0x1, 0x3 }, // 570 |
| 7227 | { Intrinsic::riscv_vwmacc_mask, 0x1, 0x4 }, // 571 |
| 7228 | { Intrinsic::riscv_vwmaccsu, 0x1, 0x3 }, // 572 |
| 7229 | { Intrinsic::riscv_vwmaccsu_mask, 0x1, 0x4 }, // 573 |
| 7230 | { Intrinsic::riscv_vwmaccu, 0x1, 0x3 }, // 574 |
| 7231 | { Intrinsic::riscv_vwmaccu_mask, 0x1, 0x4 }, // 575 |
| 7232 | { Intrinsic::riscv_vwmaccus, 0x1, 0x3 }, // 576 |
| 7233 | { Intrinsic::riscv_vwmaccus_mask, 0x1, 0x4 }, // 577 |
| 7234 | { Intrinsic::riscv_vwmul, 0x2, 0x3 }, // 578 |
| 7235 | { Intrinsic::riscv_vwmul_mask, 0x2, 0x4 }, // 579 |
| 7236 | { Intrinsic::riscv_vwmulsu, 0x2, 0x3 }, // 580 |
| 7237 | { Intrinsic::riscv_vwmulsu_mask, 0x2, 0x4 }, // 581 |
| 7238 | { Intrinsic::riscv_vwmulu, 0x2, 0x3 }, // 582 |
| 7239 | { Intrinsic::riscv_vwmulu_mask, 0x2, 0x4 }, // 583 |
| 7240 | { Intrinsic::riscv_vwredsum, 0xF, 0x3 }, // 584 |
| 7241 | { Intrinsic::riscv_vwredsum_mask, 0xF, 0x4 }, // 585 |
| 7242 | { Intrinsic::riscv_vwredsumu, 0xF, 0x3 }, // 586 |
| 7243 | { Intrinsic::riscv_vwredsumu_mask, 0xF, 0x4 }, // 587 |
| 7244 | { Intrinsic::riscv_vwsll, 0x2, 0x3 }, // 588 |
| 7245 | { Intrinsic::riscv_vwsll_mask, 0x2, 0x4 }, // 589 |
| 7246 | { Intrinsic::riscv_vwsub, 0x2, 0x3 }, // 590 |
| 7247 | { Intrinsic::riscv_vwsub_mask, 0x2, 0x4 }, // 591 |
| 7248 | { Intrinsic::riscv_vwsub_w, 0x2, 0x3 }, // 592 |
| 7249 | { Intrinsic::riscv_vwsub_w_mask, 0x2, 0x4 }, // 593 |
| 7250 | { Intrinsic::riscv_vwsubu, 0x2, 0x3 }, // 594 |
| 7251 | { Intrinsic::riscv_vwsubu_mask, 0x2, 0x4 }, // 595 |
| 7252 | { Intrinsic::riscv_vwsubu_w, 0x2, 0x3 }, // 596 |
| 7253 | { Intrinsic::riscv_vwsubu_w_mask, 0x2, 0x4 }, // 597 |
| 7254 | { Intrinsic::riscv_vxor, 0x2, 0x3 }, // 598 |
| 7255 | { Intrinsic::riscv_vxor_mask, 0x2, 0x4 }, // 599 |
| 7256 | { Intrinsic::riscv_vzext, 0xF, 0x2 }, // 600 |
| 7257 | { Intrinsic::riscv_vzext_mask, 0xF, 0x3 }, // 601 |
| 7258 | }; |
| 7259 | |
| 7260 | const RISCVVIntrinsicInfo *getRISCVVIntrinsicInfo(unsigned IntrinsicID) { |
| 7261 | struct KeyType { |
| 7262 | unsigned IntrinsicID; |
| 7263 | }; |
| 7264 | KeyType Key = {IntrinsicID}; |
| 7265 | struct Comp { |
| 7266 | bool operator()(const RISCVVIntrinsicInfo &LHS, const KeyType &RHS) const { |
| 7267 | if (LHS.IntrinsicID < RHS.IntrinsicID) |
| 7268 | return true; |
| 7269 | if (LHS.IntrinsicID > RHS.IntrinsicID) |
| 7270 | return false; |
| 7271 | return false; |
| 7272 | } |
| 7273 | }; |
| 7274 | auto Table = ArrayRef(RISCVVIntrinsicsTable); |
| 7275 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 7276 | if (Idx == Table.end() || |
| 7277 | Key.IntrinsicID != Idx->IntrinsicID) |
| 7278 | return nullptr; |
| 7279 | |
| 7280 | return &*Idx; |
| 7281 | } |
| 7282 | #endif |
| 7283 | |
| 7284 | #ifdef GET_RISCVVInversePseudosTable_DECL |
| 7285 | const PseudoInfo *getBaseInfo(unsigned BaseInstr, uint8_t VLMul, uint8_t SEW); |
| 7286 | #endif |
| 7287 | |
| 7288 | #ifdef GET_RISCVVInversePseudosTable_IMPL |
| 7289 | constexpr PseudoInfo RISCVVInversePseudosTable[] = { |
| 7290 | { PseudoTHVdotVMAQASU_VV_M1, THVdotVMAQASU_VV, 0x0, 0x0 }, // 0 |
| 7291 | { PseudoTHVdotVMAQASU_VV_M1_MASK, THVdotVMAQASU_VV, 0x0, 0x0 }, // 1 |
| 7292 | { PseudoTHVdotVMAQASU_VV_M2, THVdotVMAQASU_VV, 0x1, 0x0 }, // 2 |
| 7293 | { PseudoTHVdotVMAQASU_VV_M2_MASK, THVdotVMAQASU_VV, 0x1, 0x0 }, // 3 |
| 7294 | { PseudoTHVdotVMAQASU_VV_M4, THVdotVMAQASU_VV, 0x2, 0x0 }, // 4 |
| 7295 | { PseudoTHVdotVMAQASU_VV_M4_MASK, THVdotVMAQASU_VV, 0x2, 0x0 }, // 5 |
| 7296 | { PseudoTHVdotVMAQASU_VV_M8, THVdotVMAQASU_VV, 0x3, 0x0 }, // 6 |
| 7297 | { PseudoTHVdotVMAQASU_VV_M8_MASK, THVdotVMAQASU_VV, 0x3, 0x0 }, // 7 |
| 7298 | { PseudoTHVdotVMAQASU_VV_MF2, THVdotVMAQASU_VV, 0x7, 0x0 }, // 8 |
| 7299 | { PseudoTHVdotVMAQASU_VV_MF2_MASK, THVdotVMAQASU_VV, 0x7, 0x0 }, // 9 |
| 7300 | { PseudoTHVdotVMAQASU_VX_M1, THVdotVMAQASU_VX, 0x0, 0x0 }, // 10 |
| 7301 | { PseudoTHVdotVMAQASU_VX_M1_MASK, THVdotVMAQASU_VX, 0x0, 0x0 }, // 11 |
| 7302 | { PseudoTHVdotVMAQASU_VX_M2, THVdotVMAQASU_VX, 0x1, 0x0 }, // 12 |
| 7303 | { PseudoTHVdotVMAQASU_VX_M2_MASK, THVdotVMAQASU_VX, 0x1, 0x0 }, // 13 |
| 7304 | { PseudoTHVdotVMAQASU_VX_M4, THVdotVMAQASU_VX, 0x2, 0x0 }, // 14 |
| 7305 | { PseudoTHVdotVMAQASU_VX_M4_MASK, THVdotVMAQASU_VX, 0x2, 0x0 }, // 15 |
| 7306 | { PseudoTHVdotVMAQASU_VX_M8, THVdotVMAQASU_VX, 0x3, 0x0 }, // 16 |
| 7307 | { PseudoTHVdotVMAQASU_VX_M8_MASK, THVdotVMAQASU_VX, 0x3, 0x0 }, // 17 |
| 7308 | { PseudoTHVdotVMAQASU_VX_MF2, THVdotVMAQASU_VX, 0x7, 0x0 }, // 18 |
| 7309 | { PseudoTHVdotVMAQASU_VX_MF2_MASK, THVdotVMAQASU_VX, 0x7, 0x0 }, // 19 |
| 7310 | { PseudoTHVdotVMAQAUS_VX_M1, THVdotVMAQAUS_VX, 0x0, 0x0 }, // 20 |
| 7311 | { PseudoTHVdotVMAQAUS_VX_M1_MASK, THVdotVMAQAUS_VX, 0x0, 0x0 }, // 21 |
| 7312 | { PseudoTHVdotVMAQAUS_VX_M2, THVdotVMAQAUS_VX, 0x1, 0x0 }, // 22 |
| 7313 | { PseudoTHVdotVMAQAUS_VX_M2_MASK, THVdotVMAQAUS_VX, 0x1, 0x0 }, // 23 |
| 7314 | { PseudoTHVdotVMAQAUS_VX_M4, THVdotVMAQAUS_VX, 0x2, 0x0 }, // 24 |
| 7315 | { PseudoTHVdotVMAQAUS_VX_M4_MASK, THVdotVMAQAUS_VX, 0x2, 0x0 }, // 25 |
| 7316 | { PseudoTHVdotVMAQAUS_VX_M8, THVdotVMAQAUS_VX, 0x3, 0x0 }, // 26 |
| 7317 | { PseudoTHVdotVMAQAUS_VX_M8_MASK, THVdotVMAQAUS_VX, 0x3, 0x0 }, // 27 |
| 7318 | { PseudoTHVdotVMAQAUS_VX_MF2, THVdotVMAQAUS_VX, 0x7, 0x0 }, // 28 |
| 7319 | { PseudoTHVdotVMAQAUS_VX_MF2_MASK, THVdotVMAQAUS_VX, 0x7, 0x0 }, // 29 |
| 7320 | { PseudoTHVdotVMAQAU_VV_M1, THVdotVMAQAU_VV, 0x0, 0x0 }, // 30 |
| 7321 | { PseudoTHVdotVMAQAU_VV_M1_MASK, THVdotVMAQAU_VV, 0x0, 0x0 }, // 31 |
| 7322 | { PseudoTHVdotVMAQAU_VV_M2, THVdotVMAQAU_VV, 0x1, 0x0 }, // 32 |
| 7323 | { PseudoTHVdotVMAQAU_VV_M2_MASK, THVdotVMAQAU_VV, 0x1, 0x0 }, // 33 |
| 7324 | { PseudoTHVdotVMAQAU_VV_M4, THVdotVMAQAU_VV, 0x2, 0x0 }, // 34 |
| 7325 | { PseudoTHVdotVMAQAU_VV_M4_MASK, THVdotVMAQAU_VV, 0x2, 0x0 }, // 35 |
| 7326 | { PseudoTHVdotVMAQAU_VV_M8, THVdotVMAQAU_VV, 0x3, 0x0 }, // 36 |
| 7327 | { PseudoTHVdotVMAQAU_VV_M8_MASK, THVdotVMAQAU_VV, 0x3, 0x0 }, // 37 |
| 7328 | { PseudoTHVdotVMAQAU_VV_MF2, THVdotVMAQAU_VV, 0x7, 0x0 }, // 38 |
| 7329 | { PseudoTHVdotVMAQAU_VV_MF2_MASK, THVdotVMAQAU_VV, 0x7, 0x0 }, // 39 |
| 7330 | { PseudoTHVdotVMAQAU_VX_M1, THVdotVMAQAU_VX, 0x0, 0x0 }, // 40 |
| 7331 | { PseudoTHVdotVMAQAU_VX_M1_MASK, THVdotVMAQAU_VX, 0x0, 0x0 }, // 41 |
| 7332 | { PseudoTHVdotVMAQAU_VX_M2, THVdotVMAQAU_VX, 0x1, 0x0 }, // 42 |
| 7333 | { PseudoTHVdotVMAQAU_VX_M2_MASK, THVdotVMAQAU_VX, 0x1, 0x0 }, // 43 |
| 7334 | { PseudoTHVdotVMAQAU_VX_M4, THVdotVMAQAU_VX, 0x2, 0x0 }, // 44 |
| 7335 | { PseudoTHVdotVMAQAU_VX_M4_MASK, THVdotVMAQAU_VX, 0x2, 0x0 }, // 45 |
| 7336 | { PseudoTHVdotVMAQAU_VX_M8, THVdotVMAQAU_VX, 0x3, 0x0 }, // 46 |
| 7337 | { PseudoTHVdotVMAQAU_VX_M8_MASK, THVdotVMAQAU_VX, 0x3, 0x0 }, // 47 |
| 7338 | { PseudoTHVdotVMAQAU_VX_MF2, THVdotVMAQAU_VX, 0x7, 0x0 }, // 48 |
| 7339 | { PseudoTHVdotVMAQAU_VX_MF2_MASK, THVdotVMAQAU_VX, 0x7, 0x0 }, // 49 |
| 7340 | { PseudoTHVdotVMAQA_VV_M1, THVdotVMAQA_VV, 0x0, 0x0 }, // 50 |
| 7341 | { PseudoTHVdotVMAQA_VV_M1_MASK, THVdotVMAQA_VV, 0x0, 0x0 }, // 51 |
| 7342 | { PseudoTHVdotVMAQA_VV_M2, THVdotVMAQA_VV, 0x1, 0x0 }, // 52 |
| 7343 | { PseudoTHVdotVMAQA_VV_M2_MASK, THVdotVMAQA_VV, 0x1, 0x0 }, // 53 |
| 7344 | { PseudoTHVdotVMAQA_VV_M4, THVdotVMAQA_VV, 0x2, 0x0 }, // 54 |
| 7345 | { PseudoTHVdotVMAQA_VV_M4_MASK, THVdotVMAQA_VV, 0x2, 0x0 }, // 55 |
| 7346 | { PseudoTHVdotVMAQA_VV_M8, THVdotVMAQA_VV, 0x3, 0x0 }, // 56 |
| 7347 | { PseudoTHVdotVMAQA_VV_M8_MASK, THVdotVMAQA_VV, 0x3, 0x0 }, // 57 |
| 7348 | { PseudoTHVdotVMAQA_VV_MF2, THVdotVMAQA_VV, 0x7, 0x0 }, // 58 |
| 7349 | { PseudoTHVdotVMAQA_VV_MF2_MASK, THVdotVMAQA_VV, 0x7, 0x0 }, // 59 |
| 7350 | { PseudoTHVdotVMAQA_VX_M1, THVdotVMAQA_VX, 0x0, 0x0 }, // 60 |
| 7351 | { PseudoTHVdotVMAQA_VX_M1_MASK, THVdotVMAQA_VX, 0x0, 0x0 }, // 61 |
| 7352 | { PseudoTHVdotVMAQA_VX_M2, THVdotVMAQA_VX, 0x1, 0x0 }, // 62 |
| 7353 | { PseudoTHVdotVMAQA_VX_M2_MASK, THVdotVMAQA_VX, 0x1, 0x0 }, // 63 |
| 7354 | { PseudoTHVdotVMAQA_VX_M4, THVdotVMAQA_VX, 0x2, 0x0 }, // 64 |
| 7355 | { PseudoTHVdotVMAQA_VX_M4_MASK, THVdotVMAQA_VX, 0x2, 0x0 }, // 65 |
| 7356 | { PseudoTHVdotVMAQA_VX_M8, THVdotVMAQA_VX, 0x3, 0x0 }, // 66 |
| 7357 | { PseudoTHVdotVMAQA_VX_M8_MASK, THVdotVMAQA_VX, 0x3, 0x0 }, // 67 |
| 7358 | { PseudoTHVdotVMAQA_VX_MF2, THVdotVMAQA_VX, 0x7, 0x0 }, // 68 |
| 7359 | { PseudoTHVdotVMAQA_VX_MF2_MASK, THVdotVMAQA_VX, 0x7, 0x0 }, // 69 |
| 7360 | { PseudoVAADDU_VV_M1, VAADDU_VV, 0x0, 0x0 }, // 70 |
| 7361 | { PseudoVAADDU_VV_M1_MASK, VAADDU_VV, 0x0, 0x0 }, // 71 |
| 7362 | { PseudoVAADDU_VV_M2, VAADDU_VV, 0x1, 0x0 }, // 72 |
| 7363 | { PseudoVAADDU_VV_M2_MASK, VAADDU_VV, 0x1, 0x0 }, // 73 |
| 7364 | { PseudoVAADDU_VV_M4, VAADDU_VV, 0x2, 0x0 }, // 74 |
| 7365 | { PseudoVAADDU_VV_M4_MASK, VAADDU_VV, 0x2, 0x0 }, // 75 |
| 7366 | { PseudoVAADDU_VV_M8, VAADDU_VV, 0x3, 0x0 }, // 76 |
| 7367 | { PseudoVAADDU_VV_M8_MASK, VAADDU_VV, 0x3, 0x0 }, // 77 |
| 7368 | { PseudoVAADDU_VV_MF8, VAADDU_VV, 0x5, 0x0 }, // 78 |
| 7369 | { PseudoVAADDU_VV_MF8_MASK, VAADDU_VV, 0x5, 0x0 }, // 79 |
| 7370 | { PseudoVAADDU_VV_MF4, VAADDU_VV, 0x6, 0x0 }, // 80 |
| 7371 | { PseudoVAADDU_VV_MF4_MASK, VAADDU_VV, 0x6, 0x0 }, // 81 |
| 7372 | { PseudoVAADDU_VV_MF2, VAADDU_VV, 0x7, 0x0 }, // 82 |
| 7373 | { PseudoVAADDU_VV_MF2_MASK, VAADDU_VV, 0x7, 0x0 }, // 83 |
| 7374 | { PseudoVAADDU_VX_M1, VAADDU_VX, 0x0, 0x0 }, // 84 |
| 7375 | { PseudoVAADDU_VX_M1_MASK, VAADDU_VX, 0x0, 0x0 }, // 85 |
| 7376 | { PseudoVAADDU_VX_M2, VAADDU_VX, 0x1, 0x0 }, // 86 |
| 7377 | { PseudoVAADDU_VX_M2_MASK, VAADDU_VX, 0x1, 0x0 }, // 87 |
| 7378 | { PseudoVAADDU_VX_M4, VAADDU_VX, 0x2, 0x0 }, // 88 |
| 7379 | { PseudoVAADDU_VX_M4_MASK, VAADDU_VX, 0x2, 0x0 }, // 89 |
| 7380 | { PseudoVAADDU_VX_M8, VAADDU_VX, 0x3, 0x0 }, // 90 |
| 7381 | { PseudoVAADDU_VX_M8_MASK, VAADDU_VX, 0x3, 0x0 }, // 91 |
| 7382 | { PseudoVAADDU_VX_MF8, VAADDU_VX, 0x5, 0x0 }, // 92 |
| 7383 | { PseudoVAADDU_VX_MF8_MASK, VAADDU_VX, 0x5, 0x0 }, // 93 |
| 7384 | { PseudoVAADDU_VX_MF4, VAADDU_VX, 0x6, 0x0 }, // 94 |
| 7385 | { PseudoVAADDU_VX_MF4_MASK, VAADDU_VX, 0x6, 0x0 }, // 95 |
| 7386 | { PseudoVAADDU_VX_MF2, VAADDU_VX, 0x7, 0x0 }, // 96 |
| 7387 | { PseudoVAADDU_VX_MF2_MASK, VAADDU_VX, 0x7, 0x0 }, // 97 |
| 7388 | { PseudoVAADD_VV_M1, VAADD_VV, 0x0, 0x0 }, // 98 |
| 7389 | { PseudoVAADD_VV_M1_MASK, VAADD_VV, 0x0, 0x0 }, // 99 |
| 7390 | { PseudoVAADD_VV_M2, VAADD_VV, 0x1, 0x0 }, // 100 |
| 7391 | { PseudoVAADD_VV_M2_MASK, VAADD_VV, 0x1, 0x0 }, // 101 |
| 7392 | { PseudoVAADD_VV_M4, VAADD_VV, 0x2, 0x0 }, // 102 |
| 7393 | { PseudoVAADD_VV_M4_MASK, VAADD_VV, 0x2, 0x0 }, // 103 |
| 7394 | { PseudoVAADD_VV_M8, VAADD_VV, 0x3, 0x0 }, // 104 |
| 7395 | { PseudoVAADD_VV_M8_MASK, VAADD_VV, 0x3, 0x0 }, // 105 |
| 7396 | { PseudoVAADD_VV_MF8, VAADD_VV, 0x5, 0x0 }, // 106 |
| 7397 | { PseudoVAADD_VV_MF8_MASK, VAADD_VV, 0x5, 0x0 }, // 107 |
| 7398 | { PseudoVAADD_VV_MF4, VAADD_VV, 0x6, 0x0 }, // 108 |
| 7399 | { PseudoVAADD_VV_MF4_MASK, VAADD_VV, 0x6, 0x0 }, // 109 |
| 7400 | { PseudoVAADD_VV_MF2, VAADD_VV, 0x7, 0x0 }, // 110 |
| 7401 | { PseudoVAADD_VV_MF2_MASK, VAADD_VV, 0x7, 0x0 }, // 111 |
| 7402 | { PseudoVAADD_VX_M1, VAADD_VX, 0x0, 0x0 }, // 112 |
| 7403 | { PseudoVAADD_VX_M1_MASK, VAADD_VX, 0x0, 0x0 }, // 113 |
| 7404 | { PseudoVAADD_VX_M2, VAADD_VX, 0x1, 0x0 }, // 114 |
| 7405 | { PseudoVAADD_VX_M2_MASK, VAADD_VX, 0x1, 0x0 }, // 115 |
| 7406 | { PseudoVAADD_VX_M4, VAADD_VX, 0x2, 0x0 }, // 116 |
| 7407 | { PseudoVAADD_VX_M4_MASK, VAADD_VX, 0x2, 0x0 }, // 117 |
| 7408 | { PseudoVAADD_VX_M8, VAADD_VX, 0x3, 0x0 }, // 118 |
| 7409 | { PseudoVAADD_VX_M8_MASK, VAADD_VX, 0x3, 0x0 }, // 119 |
| 7410 | { PseudoVAADD_VX_MF8, VAADD_VX, 0x5, 0x0 }, // 120 |
| 7411 | { PseudoVAADD_VX_MF8_MASK, VAADD_VX, 0x5, 0x0 }, // 121 |
| 7412 | { PseudoVAADD_VX_MF4, VAADD_VX, 0x6, 0x0 }, // 122 |
| 7413 | { PseudoVAADD_VX_MF4_MASK, VAADD_VX, 0x6, 0x0 }, // 123 |
| 7414 | { PseudoVAADD_VX_MF2, VAADD_VX, 0x7, 0x0 }, // 124 |
| 7415 | { PseudoVAADD_VX_MF2_MASK, VAADD_VX, 0x7, 0x0 }, // 125 |
| 7416 | { PseudoVADC_VIM_M1, VADC_VIM, 0x0, 0x0 }, // 126 |
| 7417 | { PseudoVADC_VIM_M2, VADC_VIM, 0x1, 0x0 }, // 127 |
| 7418 | { PseudoVADC_VIM_M4, VADC_VIM, 0x2, 0x0 }, // 128 |
| 7419 | { PseudoVADC_VIM_M8, VADC_VIM, 0x3, 0x0 }, // 129 |
| 7420 | { PseudoVADC_VIM_MF8, VADC_VIM, 0x5, 0x0 }, // 130 |
| 7421 | { PseudoVADC_VIM_MF4, VADC_VIM, 0x6, 0x0 }, // 131 |
| 7422 | { PseudoVADC_VIM_MF2, VADC_VIM, 0x7, 0x0 }, // 132 |
| 7423 | { PseudoVADC_VVM_M1, VADC_VVM, 0x0, 0x0 }, // 133 |
| 7424 | { PseudoVADC_VVM_M2, VADC_VVM, 0x1, 0x0 }, // 134 |
| 7425 | { PseudoVADC_VVM_M4, VADC_VVM, 0x2, 0x0 }, // 135 |
| 7426 | { PseudoVADC_VVM_M8, VADC_VVM, 0x3, 0x0 }, // 136 |
| 7427 | { PseudoVADC_VVM_MF8, VADC_VVM, 0x5, 0x0 }, // 137 |
| 7428 | { PseudoVADC_VVM_MF4, VADC_VVM, 0x6, 0x0 }, // 138 |
| 7429 | { PseudoVADC_VVM_MF2, VADC_VVM, 0x7, 0x0 }, // 139 |
| 7430 | { PseudoVADC_VXM_M1, VADC_VXM, 0x0, 0x0 }, // 140 |
| 7431 | { PseudoVADC_VXM_M2, VADC_VXM, 0x1, 0x0 }, // 141 |
| 7432 | { PseudoVADC_VXM_M4, VADC_VXM, 0x2, 0x0 }, // 142 |
| 7433 | { PseudoVADC_VXM_M8, VADC_VXM, 0x3, 0x0 }, // 143 |
| 7434 | { PseudoVADC_VXM_MF8, VADC_VXM, 0x5, 0x0 }, // 144 |
| 7435 | { PseudoVADC_VXM_MF4, VADC_VXM, 0x6, 0x0 }, // 145 |
| 7436 | { PseudoVADC_VXM_MF2, VADC_VXM, 0x7, 0x0 }, // 146 |
| 7437 | { PseudoVADD_VI_M1, VADD_VI, 0x0, 0x0 }, // 147 |
| 7438 | { PseudoVADD_VI_M1_MASK, VADD_VI, 0x0, 0x0 }, // 148 |
| 7439 | { PseudoVADD_VI_M2, VADD_VI, 0x1, 0x0 }, // 149 |
| 7440 | { PseudoVADD_VI_M2_MASK, VADD_VI, 0x1, 0x0 }, // 150 |
| 7441 | { PseudoVADD_VI_M4, VADD_VI, 0x2, 0x0 }, // 151 |
| 7442 | { PseudoVADD_VI_M4_MASK, VADD_VI, 0x2, 0x0 }, // 152 |
| 7443 | { PseudoVADD_VI_M8, VADD_VI, 0x3, 0x0 }, // 153 |
| 7444 | { PseudoVADD_VI_M8_MASK, VADD_VI, 0x3, 0x0 }, // 154 |
| 7445 | { PseudoVADD_VI_MF8, VADD_VI, 0x5, 0x0 }, // 155 |
| 7446 | { PseudoVADD_VI_MF8_MASK, VADD_VI, 0x5, 0x0 }, // 156 |
| 7447 | { PseudoVADD_VI_MF4, VADD_VI, 0x6, 0x0 }, // 157 |
| 7448 | { PseudoVADD_VI_MF4_MASK, VADD_VI, 0x6, 0x0 }, // 158 |
| 7449 | { PseudoVADD_VI_MF2, VADD_VI, 0x7, 0x0 }, // 159 |
| 7450 | { PseudoVADD_VI_MF2_MASK, VADD_VI, 0x7, 0x0 }, // 160 |
| 7451 | { PseudoVADD_VV_M1, VADD_VV, 0x0, 0x0 }, // 161 |
| 7452 | { PseudoVADD_VV_M1_MASK, VADD_VV, 0x0, 0x0 }, // 162 |
| 7453 | { PseudoVADD_VV_M2, VADD_VV, 0x1, 0x0 }, // 163 |
| 7454 | { PseudoVADD_VV_M2_MASK, VADD_VV, 0x1, 0x0 }, // 164 |
| 7455 | { PseudoVADD_VV_M4, VADD_VV, 0x2, 0x0 }, // 165 |
| 7456 | { PseudoVADD_VV_M4_MASK, VADD_VV, 0x2, 0x0 }, // 166 |
| 7457 | { PseudoVADD_VV_M8, VADD_VV, 0x3, 0x0 }, // 167 |
| 7458 | { PseudoVADD_VV_M8_MASK, VADD_VV, 0x3, 0x0 }, // 168 |
| 7459 | { PseudoVADD_VV_MF8, VADD_VV, 0x5, 0x0 }, // 169 |
| 7460 | { PseudoVADD_VV_MF8_MASK, VADD_VV, 0x5, 0x0 }, // 170 |
| 7461 | { PseudoVADD_VV_MF4, VADD_VV, 0x6, 0x0 }, // 171 |
| 7462 | { PseudoVADD_VV_MF4_MASK, VADD_VV, 0x6, 0x0 }, // 172 |
| 7463 | { PseudoVADD_VV_MF2, VADD_VV, 0x7, 0x0 }, // 173 |
| 7464 | { PseudoVADD_VV_MF2_MASK, VADD_VV, 0x7, 0x0 }, // 174 |
| 7465 | { PseudoVADD_VX_M1, VADD_VX, 0x0, 0x0 }, // 175 |
| 7466 | { PseudoVADD_VX_M1_MASK, VADD_VX, 0x0, 0x0 }, // 176 |
| 7467 | { PseudoVADD_VX_M2, VADD_VX, 0x1, 0x0 }, // 177 |
| 7468 | { PseudoVADD_VX_M2_MASK, VADD_VX, 0x1, 0x0 }, // 178 |
| 7469 | { PseudoVADD_VX_M4, VADD_VX, 0x2, 0x0 }, // 179 |
| 7470 | { PseudoVADD_VX_M4_MASK, VADD_VX, 0x2, 0x0 }, // 180 |
| 7471 | { PseudoVADD_VX_M8, VADD_VX, 0x3, 0x0 }, // 181 |
| 7472 | { PseudoVADD_VX_M8_MASK, VADD_VX, 0x3, 0x0 }, // 182 |
| 7473 | { PseudoVADD_VX_MF8, VADD_VX, 0x5, 0x0 }, // 183 |
| 7474 | { PseudoVADD_VX_MF8_MASK, VADD_VX, 0x5, 0x0 }, // 184 |
| 7475 | { PseudoVADD_VX_MF4, VADD_VX, 0x6, 0x0 }, // 185 |
| 7476 | { PseudoVADD_VX_MF4_MASK, VADD_VX, 0x6, 0x0 }, // 186 |
| 7477 | { PseudoVADD_VX_MF2, VADD_VX, 0x7, 0x0 }, // 187 |
| 7478 | { PseudoVADD_VX_MF2_MASK, VADD_VX, 0x7, 0x0 }, // 188 |
| 7479 | { PseudoVAESDF_VS_M1_M1, VAESDF_VS, 0x0, 0x0 }, // 189 |
| 7480 | { PseudoVAESDF_VS_M1_MF2, VAESDF_VS, 0x0, 0x0 }, // 190 |
| 7481 | { PseudoVAESDF_VS_M1_MF4, VAESDF_VS, 0x0, 0x0 }, // 191 |
| 7482 | { PseudoVAESDF_VS_M1_MF8, VAESDF_VS, 0x0, 0x0 }, // 192 |
| 7483 | { PseudoVAESDF_VS_M2_M1, VAESDF_VS, 0x1, 0x0 }, // 193 |
| 7484 | { PseudoVAESDF_VS_M2_M2, VAESDF_VS, 0x1, 0x0 }, // 194 |
| 7485 | { PseudoVAESDF_VS_M2_MF2, VAESDF_VS, 0x1, 0x0 }, // 195 |
| 7486 | { PseudoVAESDF_VS_M2_MF4, VAESDF_VS, 0x1, 0x0 }, // 196 |
| 7487 | { PseudoVAESDF_VS_M2_MF8, VAESDF_VS, 0x1, 0x0 }, // 197 |
| 7488 | { PseudoVAESDF_VS_M4_M1, VAESDF_VS, 0x2, 0x0 }, // 198 |
| 7489 | { PseudoVAESDF_VS_M4_M2, VAESDF_VS, 0x2, 0x0 }, // 199 |
| 7490 | { PseudoVAESDF_VS_M4_M4, VAESDF_VS, 0x2, 0x0 }, // 200 |
| 7491 | { PseudoVAESDF_VS_M4_MF2, VAESDF_VS, 0x2, 0x0 }, // 201 |
| 7492 | { PseudoVAESDF_VS_M4_MF4, VAESDF_VS, 0x2, 0x0 }, // 202 |
| 7493 | { PseudoVAESDF_VS_M4_MF8, VAESDF_VS, 0x2, 0x0 }, // 203 |
| 7494 | { PseudoVAESDF_VS_M8_M1, VAESDF_VS, 0x3, 0x0 }, // 204 |
| 7495 | { PseudoVAESDF_VS_M8_M2, VAESDF_VS, 0x3, 0x0 }, // 205 |
| 7496 | { PseudoVAESDF_VS_M8_M4, VAESDF_VS, 0x3, 0x0 }, // 206 |
| 7497 | { PseudoVAESDF_VS_M8_MF2, VAESDF_VS, 0x3, 0x0 }, // 207 |
| 7498 | { PseudoVAESDF_VS_M8_MF4, VAESDF_VS, 0x3, 0x0 }, // 208 |
| 7499 | { PseudoVAESDF_VS_M8_MF8, VAESDF_VS, 0x3, 0x0 }, // 209 |
| 7500 | { PseudoVAESDF_VS_MF2_MF2, VAESDF_VS, 0x7, 0x0 }, // 210 |
| 7501 | { PseudoVAESDF_VS_MF2_MF4, VAESDF_VS, 0x7, 0x0 }, // 211 |
| 7502 | { PseudoVAESDF_VS_MF2_MF8, VAESDF_VS, 0x7, 0x0 }, // 212 |
| 7503 | { PseudoVAESDF_VV_M1, VAESDF_VV, 0x0, 0x0 }, // 213 |
| 7504 | { PseudoVAESDF_VV_M2, VAESDF_VV, 0x1, 0x0 }, // 214 |
| 7505 | { PseudoVAESDF_VV_M4, VAESDF_VV, 0x2, 0x0 }, // 215 |
| 7506 | { PseudoVAESDF_VV_M8, VAESDF_VV, 0x3, 0x0 }, // 216 |
| 7507 | { PseudoVAESDF_VV_MF2, VAESDF_VV, 0x7, 0x0 }, // 217 |
| 7508 | { PseudoVAESDM_VS_M1_M1, VAESDM_VS, 0x0, 0x0 }, // 218 |
| 7509 | { PseudoVAESDM_VS_M1_MF2, VAESDM_VS, 0x0, 0x0 }, // 219 |
| 7510 | { PseudoVAESDM_VS_M1_MF4, VAESDM_VS, 0x0, 0x0 }, // 220 |
| 7511 | { PseudoVAESDM_VS_M1_MF8, VAESDM_VS, 0x0, 0x0 }, // 221 |
| 7512 | { PseudoVAESDM_VS_M2_M1, VAESDM_VS, 0x1, 0x0 }, // 222 |
| 7513 | { PseudoVAESDM_VS_M2_M2, VAESDM_VS, 0x1, 0x0 }, // 223 |
| 7514 | { PseudoVAESDM_VS_M2_MF2, VAESDM_VS, 0x1, 0x0 }, // 224 |
| 7515 | { PseudoVAESDM_VS_M2_MF4, VAESDM_VS, 0x1, 0x0 }, // 225 |
| 7516 | { PseudoVAESDM_VS_M2_MF8, VAESDM_VS, 0x1, 0x0 }, // 226 |
| 7517 | { PseudoVAESDM_VS_M4_M1, VAESDM_VS, 0x2, 0x0 }, // 227 |
| 7518 | { PseudoVAESDM_VS_M4_M2, VAESDM_VS, 0x2, 0x0 }, // 228 |
| 7519 | { PseudoVAESDM_VS_M4_M4, VAESDM_VS, 0x2, 0x0 }, // 229 |
| 7520 | { PseudoVAESDM_VS_M4_MF2, VAESDM_VS, 0x2, 0x0 }, // 230 |
| 7521 | { PseudoVAESDM_VS_M4_MF4, VAESDM_VS, 0x2, 0x0 }, // 231 |
| 7522 | { PseudoVAESDM_VS_M4_MF8, VAESDM_VS, 0x2, 0x0 }, // 232 |
| 7523 | { PseudoVAESDM_VS_M8_M1, VAESDM_VS, 0x3, 0x0 }, // 233 |
| 7524 | { PseudoVAESDM_VS_M8_M2, VAESDM_VS, 0x3, 0x0 }, // 234 |
| 7525 | { PseudoVAESDM_VS_M8_M4, VAESDM_VS, 0x3, 0x0 }, // 235 |
| 7526 | { PseudoVAESDM_VS_M8_MF2, VAESDM_VS, 0x3, 0x0 }, // 236 |
| 7527 | { PseudoVAESDM_VS_M8_MF4, VAESDM_VS, 0x3, 0x0 }, // 237 |
| 7528 | { PseudoVAESDM_VS_M8_MF8, VAESDM_VS, 0x3, 0x0 }, // 238 |
| 7529 | { PseudoVAESDM_VS_MF2_MF2, VAESDM_VS, 0x7, 0x0 }, // 239 |
| 7530 | { PseudoVAESDM_VS_MF2_MF4, VAESDM_VS, 0x7, 0x0 }, // 240 |
| 7531 | { PseudoVAESDM_VS_MF2_MF8, VAESDM_VS, 0x7, 0x0 }, // 241 |
| 7532 | { PseudoVAESDM_VV_M1, VAESDM_VV, 0x0, 0x0 }, // 242 |
| 7533 | { PseudoVAESDM_VV_M2, VAESDM_VV, 0x1, 0x0 }, // 243 |
| 7534 | { PseudoVAESDM_VV_M4, VAESDM_VV, 0x2, 0x0 }, // 244 |
| 7535 | { PseudoVAESDM_VV_M8, VAESDM_VV, 0x3, 0x0 }, // 245 |
| 7536 | { PseudoVAESDM_VV_MF2, VAESDM_VV, 0x7, 0x0 }, // 246 |
| 7537 | { PseudoVAESEF_VS_M1_M1, VAESEF_VS, 0x0, 0x0 }, // 247 |
| 7538 | { PseudoVAESEF_VS_M1_MF2, VAESEF_VS, 0x0, 0x0 }, // 248 |
| 7539 | { PseudoVAESEF_VS_M1_MF4, VAESEF_VS, 0x0, 0x0 }, // 249 |
| 7540 | { PseudoVAESEF_VS_M1_MF8, VAESEF_VS, 0x0, 0x0 }, // 250 |
| 7541 | { PseudoVAESEF_VS_M2_M1, VAESEF_VS, 0x1, 0x0 }, // 251 |
| 7542 | { PseudoVAESEF_VS_M2_M2, VAESEF_VS, 0x1, 0x0 }, // 252 |
| 7543 | { PseudoVAESEF_VS_M2_MF2, VAESEF_VS, 0x1, 0x0 }, // 253 |
| 7544 | { PseudoVAESEF_VS_M2_MF4, VAESEF_VS, 0x1, 0x0 }, // 254 |
| 7545 | { PseudoVAESEF_VS_M2_MF8, VAESEF_VS, 0x1, 0x0 }, // 255 |
| 7546 | { PseudoVAESEF_VS_M4_M1, VAESEF_VS, 0x2, 0x0 }, // 256 |
| 7547 | { PseudoVAESEF_VS_M4_M2, VAESEF_VS, 0x2, 0x0 }, // 257 |
| 7548 | { PseudoVAESEF_VS_M4_M4, VAESEF_VS, 0x2, 0x0 }, // 258 |
| 7549 | { PseudoVAESEF_VS_M4_MF2, VAESEF_VS, 0x2, 0x0 }, // 259 |
| 7550 | { PseudoVAESEF_VS_M4_MF4, VAESEF_VS, 0x2, 0x0 }, // 260 |
| 7551 | { PseudoVAESEF_VS_M4_MF8, VAESEF_VS, 0x2, 0x0 }, // 261 |
| 7552 | { PseudoVAESEF_VS_M8_M1, VAESEF_VS, 0x3, 0x0 }, // 262 |
| 7553 | { PseudoVAESEF_VS_M8_M2, VAESEF_VS, 0x3, 0x0 }, // 263 |
| 7554 | { PseudoVAESEF_VS_M8_M4, VAESEF_VS, 0x3, 0x0 }, // 264 |
| 7555 | { PseudoVAESEF_VS_M8_MF2, VAESEF_VS, 0x3, 0x0 }, // 265 |
| 7556 | { PseudoVAESEF_VS_M8_MF4, VAESEF_VS, 0x3, 0x0 }, // 266 |
| 7557 | { PseudoVAESEF_VS_M8_MF8, VAESEF_VS, 0x3, 0x0 }, // 267 |
| 7558 | { PseudoVAESEF_VS_MF2_MF2, VAESEF_VS, 0x7, 0x0 }, // 268 |
| 7559 | { PseudoVAESEF_VS_MF2_MF4, VAESEF_VS, 0x7, 0x0 }, // 269 |
| 7560 | { PseudoVAESEF_VS_MF2_MF8, VAESEF_VS, 0x7, 0x0 }, // 270 |
| 7561 | { PseudoVAESEF_VV_M1, VAESEF_VV, 0x0, 0x0 }, // 271 |
| 7562 | { PseudoVAESEF_VV_M2, VAESEF_VV, 0x1, 0x0 }, // 272 |
| 7563 | { PseudoVAESEF_VV_M4, VAESEF_VV, 0x2, 0x0 }, // 273 |
| 7564 | { PseudoVAESEF_VV_M8, VAESEF_VV, 0x3, 0x0 }, // 274 |
| 7565 | { PseudoVAESEF_VV_MF2, VAESEF_VV, 0x7, 0x0 }, // 275 |
| 7566 | { PseudoVAESEM_VS_M1_M1, VAESEM_VS, 0x0, 0x0 }, // 276 |
| 7567 | { PseudoVAESEM_VS_M1_MF2, VAESEM_VS, 0x0, 0x0 }, // 277 |
| 7568 | { PseudoVAESEM_VS_M1_MF4, VAESEM_VS, 0x0, 0x0 }, // 278 |
| 7569 | { PseudoVAESEM_VS_M1_MF8, VAESEM_VS, 0x0, 0x0 }, // 279 |
| 7570 | { PseudoVAESEM_VS_M2_M1, VAESEM_VS, 0x1, 0x0 }, // 280 |
| 7571 | { PseudoVAESEM_VS_M2_M2, VAESEM_VS, 0x1, 0x0 }, // 281 |
| 7572 | { PseudoVAESEM_VS_M2_MF2, VAESEM_VS, 0x1, 0x0 }, // 282 |
| 7573 | { PseudoVAESEM_VS_M2_MF4, VAESEM_VS, 0x1, 0x0 }, // 283 |
| 7574 | { PseudoVAESEM_VS_M2_MF8, VAESEM_VS, 0x1, 0x0 }, // 284 |
| 7575 | { PseudoVAESEM_VS_M4_M1, VAESEM_VS, 0x2, 0x0 }, // 285 |
| 7576 | { PseudoVAESEM_VS_M4_M2, VAESEM_VS, 0x2, 0x0 }, // 286 |
| 7577 | { PseudoVAESEM_VS_M4_M4, VAESEM_VS, 0x2, 0x0 }, // 287 |
| 7578 | { PseudoVAESEM_VS_M4_MF2, VAESEM_VS, 0x2, 0x0 }, // 288 |
| 7579 | { PseudoVAESEM_VS_M4_MF4, VAESEM_VS, 0x2, 0x0 }, // 289 |
| 7580 | { PseudoVAESEM_VS_M4_MF8, VAESEM_VS, 0x2, 0x0 }, // 290 |
| 7581 | { PseudoVAESEM_VS_M8_M1, VAESEM_VS, 0x3, 0x0 }, // 291 |
| 7582 | { PseudoVAESEM_VS_M8_M2, VAESEM_VS, 0x3, 0x0 }, // 292 |
| 7583 | { PseudoVAESEM_VS_M8_M4, VAESEM_VS, 0x3, 0x0 }, // 293 |
| 7584 | { PseudoVAESEM_VS_M8_MF2, VAESEM_VS, 0x3, 0x0 }, // 294 |
| 7585 | { PseudoVAESEM_VS_M8_MF4, VAESEM_VS, 0x3, 0x0 }, // 295 |
| 7586 | { PseudoVAESEM_VS_M8_MF8, VAESEM_VS, 0x3, 0x0 }, // 296 |
| 7587 | { PseudoVAESEM_VS_MF2_MF2, VAESEM_VS, 0x7, 0x0 }, // 297 |
| 7588 | { PseudoVAESEM_VS_MF2_MF4, VAESEM_VS, 0x7, 0x0 }, // 298 |
| 7589 | { PseudoVAESEM_VS_MF2_MF8, VAESEM_VS, 0x7, 0x0 }, // 299 |
| 7590 | { PseudoVAESEM_VV_M1, VAESEM_VV, 0x0, 0x0 }, // 300 |
| 7591 | { PseudoVAESEM_VV_M2, VAESEM_VV, 0x1, 0x0 }, // 301 |
| 7592 | { PseudoVAESEM_VV_M4, VAESEM_VV, 0x2, 0x0 }, // 302 |
| 7593 | { PseudoVAESEM_VV_M8, VAESEM_VV, 0x3, 0x0 }, // 303 |
| 7594 | { PseudoVAESEM_VV_MF2, VAESEM_VV, 0x7, 0x0 }, // 304 |
| 7595 | { PseudoVAESKF1_VI_M1, VAESKF1_VI, 0x0, 0x0 }, // 305 |
| 7596 | { PseudoVAESKF1_VI_M2, VAESKF1_VI, 0x1, 0x0 }, // 306 |
| 7597 | { PseudoVAESKF1_VI_M4, VAESKF1_VI, 0x2, 0x0 }, // 307 |
| 7598 | { PseudoVAESKF1_VI_M8, VAESKF1_VI, 0x3, 0x0 }, // 308 |
| 7599 | { PseudoVAESKF1_VI_MF2, VAESKF1_VI, 0x7, 0x0 }, // 309 |
| 7600 | { PseudoVAESKF2_VI_M1, VAESKF2_VI, 0x0, 0x0 }, // 310 |
| 7601 | { PseudoVAESKF2_VI_M2, VAESKF2_VI, 0x1, 0x0 }, // 311 |
| 7602 | { PseudoVAESKF2_VI_M4, VAESKF2_VI, 0x2, 0x0 }, // 312 |
| 7603 | { PseudoVAESKF2_VI_M8, VAESKF2_VI, 0x3, 0x0 }, // 313 |
| 7604 | { PseudoVAESKF2_VI_MF2, VAESKF2_VI, 0x7, 0x0 }, // 314 |
| 7605 | { PseudoVAESZ_VS_M1_M1, VAESZ_VS, 0x0, 0x0 }, // 315 |
| 7606 | { PseudoVAESZ_VS_M1_MF2, VAESZ_VS, 0x0, 0x0 }, // 316 |
| 7607 | { PseudoVAESZ_VS_M1_MF4, VAESZ_VS, 0x0, 0x0 }, // 317 |
| 7608 | { PseudoVAESZ_VS_M1_MF8, VAESZ_VS, 0x0, 0x0 }, // 318 |
| 7609 | { PseudoVAESZ_VS_M2_M1, VAESZ_VS, 0x1, 0x0 }, // 319 |
| 7610 | { PseudoVAESZ_VS_M2_M2, VAESZ_VS, 0x1, 0x0 }, // 320 |
| 7611 | { PseudoVAESZ_VS_M2_MF2, VAESZ_VS, 0x1, 0x0 }, // 321 |
| 7612 | { PseudoVAESZ_VS_M2_MF4, VAESZ_VS, 0x1, 0x0 }, // 322 |
| 7613 | { PseudoVAESZ_VS_M2_MF8, VAESZ_VS, 0x1, 0x0 }, // 323 |
| 7614 | { PseudoVAESZ_VS_M4_M1, VAESZ_VS, 0x2, 0x0 }, // 324 |
| 7615 | { PseudoVAESZ_VS_M4_M2, VAESZ_VS, 0x2, 0x0 }, // 325 |
| 7616 | { PseudoVAESZ_VS_M4_M4, VAESZ_VS, 0x2, 0x0 }, // 326 |
| 7617 | { PseudoVAESZ_VS_M4_MF2, VAESZ_VS, 0x2, 0x0 }, // 327 |
| 7618 | { PseudoVAESZ_VS_M4_MF4, VAESZ_VS, 0x2, 0x0 }, // 328 |
| 7619 | { PseudoVAESZ_VS_M4_MF8, VAESZ_VS, 0x2, 0x0 }, // 329 |
| 7620 | { PseudoVAESZ_VS_M8_M1, VAESZ_VS, 0x3, 0x0 }, // 330 |
| 7621 | { PseudoVAESZ_VS_M8_M2, VAESZ_VS, 0x3, 0x0 }, // 331 |
| 7622 | { PseudoVAESZ_VS_M8_M4, VAESZ_VS, 0x3, 0x0 }, // 332 |
| 7623 | { PseudoVAESZ_VS_M8_MF2, VAESZ_VS, 0x3, 0x0 }, // 333 |
| 7624 | { PseudoVAESZ_VS_M8_MF4, VAESZ_VS, 0x3, 0x0 }, // 334 |
| 7625 | { PseudoVAESZ_VS_M8_MF8, VAESZ_VS, 0x3, 0x0 }, // 335 |
| 7626 | { PseudoVAESZ_VS_MF2_MF2, VAESZ_VS, 0x7, 0x0 }, // 336 |
| 7627 | { PseudoVAESZ_VS_MF2_MF4, VAESZ_VS, 0x7, 0x0 }, // 337 |
| 7628 | { PseudoVAESZ_VS_MF2_MF8, VAESZ_VS, 0x7, 0x0 }, // 338 |
| 7629 | { PseudoVANDN_VV_M1, VANDN_VV, 0x0, 0x0 }, // 339 |
| 7630 | { PseudoVANDN_VV_M1_MASK, VANDN_VV, 0x0, 0x0 }, // 340 |
| 7631 | { PseudoVANDN_VV_M2, VANDN_VV, 0x1, 0x0 }, // 341 |
| 7632 | { PseudoVANDN_VV_M2_MASK, VANDN_VV, 0x1, 0x0 }, // 342 |
| 7633 | { PseudoVANDN_VV_M4, VANDN_VV, 0x2, 0x0 }, // 343 |
| 7634 | { PseudoVANDN_VV_M4_MASK, VANDN_VV, 0x2, 0x0 }, // 344 |
| 7635 | { PseudoVANDN_VV_M8, VANDN_VV, 0x3, 0x0 }, // 345 |
| 7636 | { PseudoVANDN_VV_M8_MASK, VANDN_VV, 0x3, 0x0 }, // 346 |
| 7637 | { PseudoVANDN_VV_MF8, VANDN_VV, 0x5, 0x0 }, // 347 |
| 7638 | { PseudoVANDN_VV_MF8_MASK, VANDN_VV, 0x5, 0x0 }, // 348 |
| 7639 | { PseudoVANDN_VV_MF4, VANDN_VV, 0x6, 0x0 }, // 349 |
| 7640 | { PseudoVANDN_VV_MF4_MASK, VANDN_VV, 0x6, 0x0 }, // 350 |
| 7641 | { PseudoVANDN_VV_MF2, VANDN_VV, 0x7, 0x0 }, // 351 |
| 7642 | { PseudoVANDN_VV_MF2_MASK, VANDN_VV, 0x7, 0x0 }, // 352 |
| 7643 | { PseudoVANDN_VX_M1, VANDN_VX, 0x0, 0x0 }, // 353 |
| 7644 | { PseudoVANDN_VX_M1_MASK, VANDN_VX, 0x0, 0x0 }, // 354 |
| 7645 | { PseudoVANDN_VX_M2, VANDN_VX, 0x1, 0x0 }, // 355 |
| 7646 | { PseudoVANDN_VX_M2_MASK, VANDN_VX, 0x1, 0x0 }, // 356 |
| 7647 | { PseudoVANDN_VX_M4, VANDN_VX, 0x2, 0x0 }, // 357 |
| 7648 | { PseudoVANDN_VX_M4_MASK, VANDN_VX, 0x2, 0x0 }, // 358 |
| 7649 | { PseudoVANDN_VX_M8, VANDN_VX, 0x3, 0x0 }, // 359 |
| 7650 | { PseudoVANDN_VX_M8_MASK, VANDN_VX, 0x3, 0x0 }, // 360 |
| 7651 | { PseudoVANDN_VX_MF8, VANDN_VX, 0x5, 0x0 }, // 361 |
| 7652 | { PseudoVANDN_VX_MF8_MASK, VANDN_VX, 0x5, 0x0 }, // 362 |
| 7653 | { PseudoVANDN_VX_MF4, VANDN_VX, 0x6, 0x0 }, // 363 |
| 7654 | { PseudoVANDN_VX_MF4_MASK, VANDN_VX, 0x6, 0x0 }, // 364 |
| 7655 | { PseudoVANDN_VX_MF2, VANDN_VX, 0x7, 0x0 }, // 365 |
| 7656 | { PseudoVANDN_VX_MF2_MASK, VANDN_VX, 0x7, 0x0 }, // 366 |
| 7657 | { PseudoVAND_VI_M1, VAND_VI, 0x0, 0x0 }, // 367 |
| 7658 | { PseudoVAND_VI_M1_MASK, VAND_VI, 0x0, 0x0 }, // 368 |
| 7659 | { PseudoVAND_VI_M2, VAND_VI, 0x1, 0x0 }, // 369 |
| 7660 | { PseudoVAND_VI_M2_MASK, VAND_VI, 0x1, 0x0 }, // 370 |
| 7661 | { PseudoVAND_VI_M4, VAND_VI, 0x2, 0x0 }, // 371 |
| 7662 | { PseudoVAND_VI_M4_MASK, VAND_VI, 0x2, 0x0 }, // 372 |
| 7663 | { PseudoVAND_VI_M8, VAND_VI, 0x3, 0x0 }, // 373 |
| 7664 | { PseudoVAND_VI_M8_MASK, VAND_VI, 0x3, 0x0 }, // 374 |
| 7665 | { PseudoVAND_VI_MF8, VAND_VI, 0x5, 0x0 }, // 375 |
| 7666 | { PseudoVAND_VI_MF8_MASK, VAND_VI, 0x5, 0x0 }, // 376 |
| 7667 | { PseudoVAND_VI_MF4, VAND_VI, 0x6, 0x0 }, // 377 |
| 7668 | { PseudoVAND_VI_MF4_MASK, VAND_VI, 0x6, 0x0 }, // 378 |
| 7669 | { PseudoVAND_VI_MF2, VAND_VI, 0x7, 0x0 }, // 379 |
| 7670 | { PseudoVAND_VI_MF2_MASK, VAND_VI, 0x7, 0x0 }, // 380 |
| 7671 | { PseudoVAND_VV_M1, VAND_VV, 0x0, 0x0 }, // 381 |
| 7672 | { PseudoVAND_VV_M1_MASK, VAND_VV, 0x0, 0x0 }, // 382 |
| 7673 | { PseudoVAND_VV_M2, VAND_VV, 0x1, 0x0 }, // 383 |
| 7674 | { PseudoVAND_VV_M2_MASK, VAND_VV, 0x1, 0x0 }, // 384 |
| 7675 | { PseudoVAND_VV_M4, VAND_VV, 0x2, 0x0 }, // 385 |
| 7676 | { PseudoVAND_VV_M4_MASK, VAND_VV, 0x2, 0x0 }, // 386 |
| 7677 | { PseudoVAND_VV_M8, VAND_VV, 0x3, 0x0 }, // 387 |
| 7678 | { PseudoVAND_VV_M8_MASK, VAND_VV, 0x3, 0x0 }, // 388 |
| 7679 | { PseudoVAND_VV_MF8, VAND_VV, 0x5, 0x0 }, // 389 |
| 7680 | { PseudoVAND_VV_MF8_MASK, VAND_VV, 0x5, 0x0 }, // 390 |
| 7681 | { PseudoVAND_VV_MF4, VAND_VV, 0x6, 0x0 }, // 391 |
| 7682 | { PseudoVAND_VV_MF4_MASK, VAND_VV, 0x6, 0x0 }, // 392 |
| 7683 | { PseudoVAND_VV_MF2, VAND_VV, 0x7, 0x0 }, // 393 |
| 7684 | { PseudoVAND_VV_MF2_MASK, VAND_VV, 0x7, 0x0 }, // 394 |
| 7685 | { PseudoVAND_VX_M1, VAND_VX, 0x0, 0x0 }, // 395 |
| 7686 | { PseudoVAND_VX_M1_MASK, VAND_VX, 0x0, 0x0 }, // 396 |
| 7687 | { PseudoVAND_VX_M2, VAND_VX, 0x1, 0x0 }, // 397 |
| 7688 | { PseudoVAND_VX_M2_MASK, VAND_VX, 0x1, 0x0 }, // 398 |
| 7689 | { PseudoVAND_VX_M4, VAND_VX, 0x2, 0x0 }, // 399 |
| 7690 | { PseudoVAND_VX_M4_MASK, VAND_VX, 0x2, 0x0 }, // 400 |
| 7691 | { PseudoVAND_VX_M8, VAND_VX, 0x3, 0x0 }, // 401 |
| 7692 | { PseudoVAND_VX_M8_MASK, VAND_VX, 0x3, 0x0 }, // 402 |
| 7693 | { PseudoVAND_VX_MF8, VAND_VX, 0x5, 0x0 }, // 403 |
| 7694 | { PseudoVAND_VX_MF8_MASK, VAND_VX, 0x5, 0x0 }, // 404 |
| 7695 | { PseudoVAND_VX_MF4, VAND_VX, 0x6, 0x0 }, // 405 |
| 7696 | { PseudoVAND_VX_MF4_MASK, VAND_VX, 0x6, 0x0 }, // 406 |
| 7697 | { PseudoVAND_VX_MF2, VAND_VX, 0x7, 0x0 }, // 407 |
| 7698 | { PseudoVAND_VX_MF2_MASK, VAND_VX, 0x7, 0x0 }, // 408 |
| 7699 | { PseudoVASUBU_VV_M1, VASUBU_VV, 0x0, 0x0 }, // 409 |
| 7700 | { PseudoVASUBU_VV_M1_MASK, VASUBU_VV, 0x0, 0x0 }, // 410 |
| 7701 | { PseudoVASUBU_VV_M2, VASUBU_VV, 0x1, 0x0 }, // 411 |
| 7702 | { PseudoVASUBU_VV_M2_MASK, VASUBU_VV, 0x1, 0x0 }, // 412 |
| 7703 | { PseudoVASUBU_VV_M4, VASUBU_VV, 0x2, 0x0 }, // 413 |
| 7704 | { PseudoVASUBU_VV_M4_MASK, VASUBU_VV, 0x2, 0x0 }, // 414 |
| 7705 | { PseudoVASUBU_VV_M8, VASUBU_VV, 0x3, 0x0 }, // 415 |
| 7706 | { PseudoVASUBU_VV_M8_MASK, VASUBU_VV, 0x3, 0x0 }, // 416 |
| 7707 | { PseudoVASUBU_VV_MF8, VASUBU_VV, 0x5, 0x0 }, // 417 |
| 7708 | { PseudoVASUBU_VV_MF8_MASK, VASUBU_VV, 0x5, 0x0 }, // 418 |
| 7709 | { PseudoVASUBU_VV_MF4, VASUBU_VV, 0x6, 0x0 }, // 419 |
| 7710 | { PseudoVASUBU_VV_MF4_MASK, VASUBU_VV, 0x6, 0x0 }, // 420 |
| 7711 | { PseudoVASUBU_VV_MF2, VASUBU_VV, 0x7, 0x0 }, // 421 |
| 7712 | { PseudoVASUBU_VV_MF2_MASK, VASUBU_VV, 0x7, 0x0 }, // 422 |
| 7713 | { PseudoVASUBU_VX_M1, VASUBU_VX, 0x0, 0x0 }, // 423 |
| 7714 | { PseudoVASUBU_VX_M1_MASK, VASUBU_VX, 0x0, 0x0 }, // 424 |
| 7715 | { PseudoVASUBU_VX_M2, VASUBU_VX, 0x1, 0x0 }, // 425 |
| 7716 | { PseudoVASUBU_VX_M2_MASK, VASUBU_VX, 0x1, 0x0 }, // 426 |
| 7717 | { PseudoVASUBU_VX_M4, VASUBU_VX, 0x2, 0x0 }, // 427 |
| 7718 | { PseudoVASUBU_VX_M4_MASK, VASUBU_VX, 0x2, 0x0 }, // 428 |
| 7719 | { PseudoVASUBU_VX_M8, VASUBU_VX, 0x3, 0x0 }, // 429 |
| 7720 | { PseudoVASUBU_VX_M8_MASK, VASUBU_VX, 0x3, 0x0 }, // 430 |
| 7721 | { PseudoVASUBU_VX_MF8, VASUBU_VX, 0x5, 0x0 }, // 431 |
| 7722 | { PseudoVASUBU_VX_MF8_MASK, VASUBU_VX, 0x5, 0x0 }, // 432 |
| 7723 | { PseudoVASUBU_VX_MF4, VASUBU_VX, 0x6, 0x0 }, // 433 |
| 7724 | { PseudoVASUBU_VX_MF4_MASK, VASUBU_VX, 0x6, 0x0 }, // 434 |
| 7725 | { PseudoVASUBU_VX_MF2, VASUBU_VX, 0x7, 0x0 }, // 435 |
| 7726 | { PseudoVASUBU_VX_MF2_MASK, VASUBU_VX, 0x7, 0x0 }, // 436 |
| 7727 | { PseudoVASUB_VV_M1, VASUB_VV, 0x0, 0x0 }, // 437 |
| 7728 | { PseudoVASUB_VV_M1_MASK, VASUB_VV, 0x0, 0x0 }, // 438 |
| 7729 | { PseudoVASUB_VV_M2, VASUB_VV, 0x1, 0x0 }, // 439 |
| 7730 | { PseudoVASUB_VV_M2_MASK, VASUB_VV, 0x1, 0x0 }, // 440 |
| 7731 | { PseudoVASUB_VV_M4, VASUB_VV, 0x2, 0x0 }, // 441 |
| 7732 | { PseudoVASUB_VV_M4_MASK, VASUB_VV, 0x2, 0x0 }, // 442 |
| 7733 | { PseudoVASUB_VV_M8, VASUB_VV, 0x3, 0x0 }, // 443 |
| 7734 | { PseudoVASUB_VV_M8_MASK, VASUB_VV, 0x3, 0x0 }, // 444 |
| 7735 | { PseudoVASUB_VV_MF8, VASUB_VV, 0x5, 0x0 }, // 445 |
| 7736 | { PseudoVASUB_VV_MF8_MASK, VASUB_VV, 0x5, 0x0 }, // 446 |
| 7737 | { PseudoVASUB_VV_MF4, VASUB_VV, 0x6, 0x0 }, // 447 |
| 7738 | { PseudoVASUB_VV_MF4_MASK, VASUB_VV, 0x6, 0x0 }, // 448 |
| 7739 | { PseudoVASUB_VV_MF2, VASUB_VV, 0x7, 0x0 }, // 449 |
| 7740 | { PseudoVASUB_VV_MF2_MASK, VASUB_VV, 0x7, 0x0 }, // 450 |
| 7741 | { PseudoVASUB_VX_M1, VASUB_VX, 0x0, 0x0 }, // 451 |
| 7742 | { PseudoVASUB_VX_M1_MASK, VASUB_VX, 0x0, 0x0 }, // 452 |
| 7743 | { PseudoVASUB_VX_M2, VASUB_VX, 0x1, 0x0 }, // 453 |
| 7744 | { PseudoVASUB_VX_M2_MASK, VASUB_VX, 0x1, 0x0 }, // 454 |
| 7745 | { PseudoVASUB_VX_M4, VASUB_VX, 0x2, 0x0 }, // 455 |
| 7746 | { PseudoVASUB_VX_M4_MASK, VASUB_VX, 0x2, 0x0 }, // 456 |
| 7747 | { PseudoVASUB_VX_M8, VASUB_VX, 0x3, 0x0 }, // 457 |
| 7748 | { PseudoVASUB_VX_M8_MASK, VASUB_VX, 0x3, 0x0 }, // 458 |
| 7749 | { PseudoVASUB_VX_MF8, VASUB_VX, 0x5, 0x0 }, // 459 |
| 7750 | { PseudoVASUB_VX_MF8_MASK, VASUB_VX, 0x5, 0x0 }, // 460 |
| 7751 | { PseudoVASUB_VX_MF4, VASUB_VX, 0x6, 0x0 }, // 461 |
| 7752 | { PseudoVASUB_VX_MF4_MASK, VASUB_VX, 0x6, 0x0 }, // 462 |
| 7753 | { PseudoVASUB_VX_MF2, VASUB_VX, 0x7, 0x0 }, // 463 |
| 7754 | { PseudoVASUB_VX_MF2_MASK, VASUB_VX, 0x7, 0x0 }, // 464 |
| 7755 | { PseudoVBREV8_V_M1, VBREV8_V, 0x0, 0x0 }, // 465 |
| 7756 | { PseudoVBREV8_V_M1_MASK, VBREV8_V, 0x0, 0x0 }, // 466 |
| 7757 | { PseudoVBREV8_V_M2, VBREV8_V, 0x1, 0x0 }, // 467 |
| 7758 | { PseudoVBREV8_V_M2_MASK, VBREV8_V, 0x1, 0x0 }, // 468 |
| 7759 | { PseudoVBREV8_V_M4, VBREV8_V, 0x2, 0x0 }, // 469 |
| 7760 | { PseudoVBREV8_V_M4_MASK, VBREV8_V, 0x2, 0x0 }, // 470 |
| 7761 | { PseudoVBREV8_V_M8, VBREV8_V, 0x3, 0x0 }, // 471 |
| 7762 | { PseudoVBREV8_V_M8_MASK, VBREV8_V, 0x3, 0x0 }, // 472 |
| 7763 | { PseudoVBREV8_V_MF8, VBREV8_V, 0x5, 0x0 }, // 473 |
| 7764 | { PseudoVBREV8_V_MF8_MASK, VBREV8_V, 0x5, 0x0 }, // 474 |
| 7765 | { PseudoVBREV8_V_MF4, VBREV8_V, 0x6, 0x0 }, // 475 |
| 7766 | { PseudoVBREV8_V_MF4_MASK, VBREV8_V, 0x6, 0x0 }, // 476 |
| 7767 | { PseudoVBREV8_V_MF2, VBREV8_V, 0x7, 0x0 }, // 477 |
| 7768 | { PseudoVBREV8_V_MF2_MASK, VBREV8_V, 0x7, 0x0 }, // 478 |
| 7769 | { PseudoVBREV_V_M1, VBREV_V, 0x0, 0x0 }, // 479 |
| 7770 | { PseudoVBREV_V_M1_MASK, VBREV_V, 0x0, 0x0 }, // 480 |
| 7771 | { PseudoVBREV_V_M2, VBREV_V, 0x1, 0x0 }, // 481 |
| 7772 | { PseudoVBREV_V_M2_MASK, VBREV_V, 0x1, 0x0 }, // 482 |
| 7773 | { PseudoVBREV_V_M4, VBREV_V, 0x2, 0x0 }, // 483 |
| 7774 | { PseudoVBREV_V_M4_MASK, VBREV_V, 0x2, 0x0 }, // 484 |
| 7775 | { PseudoVBREV_V_M8, VBREV_V, 0x3, 0x0 }, // 485 |
| 7776 | { PseudoVBREV_V_M8_MASK, VBREV_V, 0x3, 0x0 }, // 486 |
| 7777 | { PseudoVBREV_V_MF8, VBREV_V, 0x5, 0x0 }, // 487 |
| 7778 | { PseudoVBREV_V_MF8_MASK, VBREV_V, 0x5, 0x0 }, // 488 |
| 7779 | { PseudoVBREV_V_MF4, VBREV_V, 0x6, 0x0 }, // 489 |
| 7780 | { PseudoVBREV_V_MF4_MASK, VBREV_V, 0x6, 0x0 }, // 490 |
| 7781 | { PseudoVBREV_V_MF2, VBREV_V, 0x7, 0x0 }, // 491 |
| 7782 | { PseudoVBREV_V_MF2_MASK, VBREV_V, 0x7, 0x0 }, // 492 |
| 7783 | { PseudoVCLMULH_VV_M1, VCLMULH_VV, 0x0, 0x0 }, // 493 |
| 7784 | { PseudoVCLMULH_VV_M1_MASK, VCLMULH_VV, 0x0, 0x0 }, // 494 |
| 7785 | { PseudoVCLMULH_VV_M2, VCLMULH_VV, 0x1, 0x0 }, // 495 |
| 7786 | { PseudoVCLMULH_VV_M2_MASK, VCLMULH_VV, 0x1, 0x0 }, // 496 |
| 7787 | { PseudoVCLMULH_VV_M4, VCLMULH_VV, 0x2, 0x0 }, // 497 |
| 7788 | { PseudoVCLMULH_VV_M4_MASK, VCLMULH_VV, 0x2, 0x0 }, // 498 |
| 7789 | { PseudoVCLMULH_VV_M8, VCLMULH_VV, 0x3, 0x0 }, // 499 |
| 7790 | { PseudoVCLMULH_VV_M8_MASK, VCLMULH_VV, 0x3, 0x0 }, // 500 |
| 7791 | { PseudoVCLMULH_VV_MF8, VCLMULH_VV, 0x5, 0x0 }, // 501 |
| 7792 | { PseudoVCLMULH_VV_MF8_MASK, VCLMULH_VV, 0x5, 0x0 }, // 502 |
| 7793 | { PseudoVCLMULH_VV_MF4, VCLMULH_VV, 0x6, 0x0 }, // 503 |
| 7794 | { PseudoVCLMULH_VV_MF4_MASK, VCLMULH_VV, 0x6, 0x0 }, // 504 |
| 7795 | { PseudoVCLMULH_VV_MF2, VCLMULH_VV, 0x7, 0x0 }, // 505 |
| 7796 | { PseudoVCLMULH_VV_MF2_MASK, VCLMULH_VV, 0x7, 0x0 }, // 506 |
| 7797 | { PseudoVCLMULH_VX_M1, VCLMULH_VX, 0x0, 0x0 }, // 507 |
| 7798 | { PseudoVCLMULH_VX_M1_MASK, VCLMULH_VX, 0x0, 0x0 }, // 508 |
| 7799 | { PseudoVCLMULH_VX_M2, VCLMULH_VX, 0x1, 0x0 }, // 509 |
| 7800 | { PseudoVCLMULH_VX_M2_MASK, VCLMULH_VX, 0x1, 0x0 }, // 510 |
| 7801 | { PseudoVCLMULH_VX_M4, VCLMULH_VX, 0x2, 0x0 }, // 511 |
| 7802 | { PseudoVCLMULH_VX_M4_MASK, VCLMULH_VX, 0x2, 0x0 }, // 512 |
| 7803 | { PseudoVCLMULH_VX_M8, VCLMULH_VX, 0x3, 0x0 }, // 513 |
| 7804 | { PseudoVCLMULH_VX_M8_MASK, VCLMULH_VX, 0x3, 0x0 }, // 514 |
| 7805 | { PseudoVCLMULH_VX_MF8, VCLMULH_VX, 0x5, 0x0 }, // 515 |
| 7806 | { PseudoVCLMULH_VX_MF8_MASK, VCLMULH_VX, 0x5, 0x0 }, // 516 |
| 7807 | { PseudoVCLMULH_VX_MF4, VCLMULH_VX, 0x6, 0x0 }, // 517 |
| 7808 | { PseudoVCLMULH_VX_MF4_MASK, VCLMULH_VX, 0x6, 0x0 }, // 518 |
| 7809 | { PseudoVCLMULH_VX_MF2, VCLMULH_VX, 0x7, 0x0 }, // 519 |
| 7810 | { PseudoVCLMULH_VX_MF2_MASK, VCLMULH_VX, 0x7, 0x0 }, // 520 |
| 7811 | { PseudoVCLMUL_VV_M1, VCLMUL_VV, 0x0, 0x0 }, // 521 |
| 7812 | { PseudoVCLMUL_VV_M1_MASK, VCLMUL_VV, 0x0, 0x0 }, // 522 |
| 7813 | { PseudoVCLMUL_VV_M2, VCLMUL_VV, 0x1, 0x0 }, // 523 |
| 7814 | { PseudoVCLMUL_VV_M2_MASK, VCLMUL_VV, 0x1, 0x0 }, // 524 |
| 7815 | { PseudoVCLMUL_VV_M4, VCLMUL_VV, 0x2, 0x0 }, // 525 |
| 7816 | { PseudoVCLMUL_VV_M4_MASK, VCLMUL_VV, 0x2, 0x0 }, // 526 |
| 7817 | { PseudoVCLMUL_VV_M8, VCLMUL_VV, 0x3, 0x0 }, // 527 |
| 7818 | { PseudoVCLMUL_VV_M8_MASK, VCLMUL_VV, 0x3, 0x0 }, // 528 |
| 7819 | { PseudoVCLMUL_VV_MF8, VCLMUL_VV, 0x5, 0x0 }, // 529 |
| 7820 | { PseudoVCLMUL_VV_MF8_MASK, VCLMUL_VV, 0x5, 0x0 }, // 530 |
| 7821 | { PseudoVCLMUL_VV_MF4, VCLMUL_VV, 0x6, 0x0 }, // 531 |
| 7822 | { PseudoVCLMUL_VV_MF4_MASK, VCLMUL_VV, 0x6, 0x0 }, // 532 |
| 7823 | { PseudoVCLMUL_VV_MF2, VCLMUL_VV, 0x7, 0x0 }, // 533 |
| 7824 | { PseudoVCLMUL_VV_MF2_MASK, VCLMUL_VV, 0x7, 0x0 }, // 534 |
| 7825 | { PseudoVCLMUL_VX_M1, VCLMUL_VX, 0x0, 0x0 }, // 535 |
| 7826 | { PseudoVCLMUL_VX_M1_MASK, VCLMUL_VX, 0x0, 0x0 }, // 536 |
| 7827 | { PseudoVCLMUL_VX_M2, VCLMUL_VX, 0x1, 0x0 }, // 537 |
| 7828 | { PseudoVCLMUL_VX_M2_MASK, VCLMUL_VX, 0x1, 0x0 }, // 538 |
| 7829 | { PseudoVCLMUL_VX_M4, VCLMUL_VX, 0x2, 0x0 }, // 539 |
| 7830 | { PseudoVCLMUL_VX_M4_MASK, VCLMUL_VX, 0x2, 0x0 }, // 540 |
| 7831 | { PseudoVCLMUL_VX_M8, VCLMUL_VX, 0x3, 0x0 }, // 541 |
| 7832 | { PseudoVCLMUL_VX_M8_MASK, VCLMUL_VX, 0x3, 0x0 }, // 542 |
| 7833 | { PseudoVCLMUL_VX_MF8, VCLMUL_VX, 0x5, 0x0 }, // 543 |
| 7834 | { PseudoVCLMUL_VX_MF8_MASK, VCLMUL_VX, 0x5, 0x0 }, // 544 |
| 7835 | { PseudoVCLMUL_VX_MF4, VCLMUL_VX, 0x6, 0x0 }, // 545 |
| 7836 | { PseudoVCLMUL_VX_MF4_MASK, VCLMUL_VX, 0x6, 0x0 }, // 546 |
| 7837 | { PseudoVCLMUL_VX_MF2, VCLMUL_VX, 0x7, 0x0 }, // 547 |
| 7838 | { PseudoVCLMUL_VX_MF2_MASK, VCLMUL_VX, 0x7, 0x0 }, // 548 |
| 7839 | { PseudoVCLZ_V_M1, VCLZ_V, 0x0, 0x0 }, // 549 |
| 7840 | { PseudoVCLZ_V_M1_MASK, VCLZ_V, 0x0, 0x0 }, // 550 |
| 7841 | { PseudoVCLZ_V_M2, VCLZ_V, 0x1, 0x0 }, // 551 |
| 7842 | { PseudoVCLZ_V_M2_MASK, VCLZ_V, 0x1, 0x0 }, // 552 |
| 7843 | { PseudoVCLZ_V_M4, VCLZ_V, 0x2, 0x0 }, // 553 |
| 7844 | { PseudoVCLZ_V_M4_MASK, VCLZ_V, 0x2, 0x0 }, // 554 |
| 7845 | { PseudoVCLZ_V_M8, VCLZ_V, 0x3, 0x0 }, // 555 |
| 7846 | { PseudoVCLZ_V_M8_MASK, VCLZ_V, 0x3, 0x0 }, // 556 |
| 7847 | { PseudoVCLZ_V_MF8, VCLZ_V, 0x5, 0x0 }, // 557 |
| 7848 | { PseudoVCLZ_V_MF8_MASK, VCLZ_V, 0x5, 0x0 }, // 558 |
| 7849 | { PseudoVCLZ_V_MF4, VCLZ_V, 0x6, 0x0 }, // 559 |
| 7850 | { PseudoVCLZ_V_MF4_MASK, VCLZ_V, 0x6, 0x0 }, // 560 |
| 7851 | { PseudoVCLZ_V_MF2, VCLZ_V, 0x7, 0x0 }, // 561 |
| 7852 | { PseudoVCLZ_V_MF2_MASK, VCLZ_V, 0x7, 0x0 }, // 562 |
| 7853 | { PseudoVCOMPRESS_VM_M1_E8, VCOMPRESS_VM, 0x0, 0x8 }, // 563 |
| 7854 | { PseudoVCOMPRESS_VM_M1_E16, VCOMPRESS_VM, 0x0, 0x10 }, // 564 |
| 7855 | { PseudoVCOMPRESS_VM_M1_E32, VCOMPRESS_VM, 0x0, 0x20 }, // 565 |
| 7856 | { PseudoVCOMPRESS_VM_M1_E64, VCOMPRESS_VM, 0x0, 0x40 }, // 566 |
| 7857 | { PseudoVCOMPRESS_VM_M2_E8, VCOMPRESS_VM, 0x1, 0x8 }, // 567 |
| 7858 | { PseudoVCOMPRESS_VM_M2_E16, VCOMPRESS_VM, 0x1, 0x10 }, // 568 |
| 7859 | { PseudoVCOMPRESS_VM_M2_E32, VCOMPRESS_VM, 0x1, 0x20 }, // 569 |
| 7860 | { PseudoVCOMPRESS_VM_M2_E64, VCOMPRESS_VM, 0x1, 0x40 }, // 570 |
| 7861 | { PseudoVCOMPRESS_VM_M4_E8, VCOMPRESS_VM, 0x2, 0x8 }, // 571 |
| 7862 | { PseudoVCOMPRESS_VM_M4_E16, VCOMPRESS_VM, 0x2, 0x10 }, // 572 |
| 7863 | { PseudoVCOMPRESS_VM_M4_E32, VCOMPRESS_VM, 0x2, 0x20 }, // 573 |
| 7864 | { PseudoVCOMPRESS_VM_M4_E64, VCOMPRESS_VM, 0x2, 0x40 }, // 574 |
| 7865 | { PseudoVCOMPRESS_VM_M8_E8, VCOMPRESS_VM, 0x3, 0x8 }, // 575 |
| 7866 | { PseudoVCOMPRESS_VM_M8_E16, VCOMPRESS_VM, 0x3, 0x10 }, // 576 |
| 7867 | { PseudoVCOMPRESS_VM_M8_E32, VCOMPRESS_VM, 0x3, 0x20 }, // 577 |
| 7868 | { PseudoVCOMPRESS_VM_M8_E64, VCOMPRESS_VM, 0x3, 0x40 }, // 578 |
| 7869 | { PseudoVCOMPRESS_VM_MF8_E8, VCOMPRESS_VM, 0x5, 0x8 }, // 579 |
| 7870 | { PseudoVCOMPRESS_VM_MF4_E8, VCOMPRESS_VM, 0x6, 0x8 }, // 580 |
| 7871 | { PseudoVCOMPRESS_VM_MF4_E16, VCOMPRESS_VM, 0x6, 0x10 }, // 581 |
| 7872 | { PseudoVCOMPRESS_VM_MF2_E8, VCOMPRESS_VM, 0x7, 0x8 }, // 582 |
| 7873 | { PseudoVCOMPRESS_VM_MF2_E16, VCOMPRESS_VM, 0x7, 0x10 }, // 583 |
| 7874 | { PseudoVCOMPRESS_VM_MF2_E32, VCOMPRESS_VM, 0x7, 0x20 }, // 584 |
| 7875 | { PseudoVCPOP_M_B8, VCPOP_M, 0x0, 0x0 }, // 585 |
| 7876 | { PseudoVCPOP_M_B8_MASK, VCPOP_M, 0x0, 0x0 }, // 586 |
| 7877 | { PseudoVCPOP_M_B16, VCPOP_M, 0x1, 0x0 }, // 587 |
| 7878 | { PseudoVCPOP_M_B16_MASK, VCPOP_M, 0x1, 0x0 }, // 588 |
| 7879 | { PseudoVCPOP_M_B32, VCPOP_M, 0x2, 0x0 }, // 589 |
| 7880 | { PseudoVCPOP_M_B32_MASK, VCPOP_M, 0x2, 0x0 }, // 590 |
| 7881 | { PseudoVCPOP_M_B64, VCPOP_M, 0x3, 0x0 }, // 591 |
| 7882 | { PseudoVCPOP_M_B64_MASK, VCPOP_M, 0x3, 0x0 }, // 592 |
| 7883 | { PseudoVCPOP_M_B1, VCPOP_M, 0x5, 0x0 }, // 593 |
| 7884 | { PseudoVCPOP_M_B1_MASK, VCPOP_M, 0x5, 0x0 }, // 594 |
| 7885 | { PseudoVCPOP_M_B2, VCPOP_M, 0x6, 0x0 }, // 595 |
| 7886 | { PseudoVCPOP_M_B2_MASK, VCPOP_M, 0x6, 0x0 }, // 596 |
| 7887 | { PseudoVCPOP_M_B4, VCPOP_M, 0x7, 0x0 }, // 597 |
| 7888 | { PseudoVCPOP_M_B4_MASK, VCPOP_M, 0x7, 0x0 }, // 598 |
| 7889 | { PseudoVCPOP_V_M1, VCPOP_V, 0x0, 0x0 }, // 599 |
| 7890 | { PseudoVCPOP_V_M1_MASK, VCPOP_V, 0x0, 0x0 }, // 600 |
| 7891 | { PseudoVCPOP_V_M2, VCPOP_V, 0x1, 0x0 }, // 601 |
| 7892 | { PseudoVCPOP_V_M2_MASK, VCPOP_V, 0x1, 0x0 }, // 602 |
| 7893 | { PseudoVCPOP_V_M4, VCPOP_V, 0x2, 0x0 }, // 603 |
| 7894 | { PseudoVCPOP_V_M4_MASK, VCPOP_V, 0x2, 0x0 }, // 604 |
| 7895 | { PseudoVCPOP_V_M8, VCPOP_V, 0x3, 0x0 }, // 605 |
| 7896 | { PseudoVCPOP_V_M8_MASK, VCPOP_V, 0x3, 0x0 }, // 606 |
| 7897 | { PseudoVCPOP_V_MF8, VCPOP_V, 0x5, 0x0 }, // 607 |
| 7898 | { PseudoVCPOP_V_MF8_MASK, VCPOP_V, 0x5, 0x0 }, // 608 |
| 7899 | { PseudoVCPOP_V_MF4, VCPOP_V, 0x6, 0x0 }, // 609 |
| 7900 | { PseudoVCPOP_V_MF4_MASK, VCPOP_V, 0x6, 0x0 }, // 610 |
| 7901 | { PseudoVCPOP_V_MF2, VCPOP_V, 0x7, 0x0 }, // 611 |
| 7902 | { PseudoVCPOP_V_MF2_MASK, VCPOP_V, 0x7, 0x0 }, // 612 |
| 7903 | { PseudoVCTZ_V_M1, VCTZ_V, 0x0, 0x0 }, // 613 |
| 7904 | { PseudoVCTZ_V_M1_MASK, VCTZ_V, 0x0, 0x0 }, // 614 |
| 7905 | { PseudoVCTZ_V_M2, VCTZ_V, 0x1, 0x0 }, // 615 |
| 7906 | { PseudoVCTZ_V_M2_MASK, VCTZ_V, 0x1, 0x0 }, // 616 |
| 7907 | { PseudoVCTZ_V_M4, VCTZ_V, 0x2, 0x0 }, // 617 |
| 7908 | { PseudoVCTZ_V_M4_MASK, VCTZ_V, 0x2, 0x0 }, // 618 |
| 7909 | { PseudoVCTZ_V_M8, VCTZ_V, 0x3, 0x0 }, // 619 |
| 7910 | { PseudoVCTZ_V_M8_MASK, VCTZ_V, 0x3, 0x0 }, // 620 |
| 7911 | { PseudoVCTZ_V_MF8, VCTZ_V, 0x5, 0x0 }, // 621 |
| 7912 | { PseudoVCTZ_V_MF8_MASK, VCTZ_V, 0x5, 0x0 }, // 622 |
| 7913 | { PseudoVCTZ_V_MF4, VCTZ_V, 0x6, 0x0 }, // 623 |
| 7914 | { PseudoVCTZ_V_MF4_MASK, VCTZ_V, 0x6, 0x0 }, // 624 |
| 7915 | { PseudoVCTZ_V_MF2, VCTZ_V, 0x7, 0x0 }, // 625 |
| 7916 | { PseudoVCTZ_V_MF2_MASK, VCTZ_V, 0x7, 0x0 }, // 626 |
| 7917 | { PseudoVC_FPR16V_SE_M1, VC_FV, 0x0, 0x0 }, // 627 |
| 7918 | { PseudoVC_FPR32V_SE_M1, VC_FV, 0x0, 0x0 }, // 628 |
| 7919 | { PseudoVC_FPR64V_SE_M1, VC_FV, 0x0, 0x0 }, // 629 |
| 7920 | { PseudoVC_FPR16V_SE_M2, VC_FV, 0x1, 0x0 }, // 630 |
| 7921 | { PseudoVC_FPR32V_SE_M2, VC_FV, 0x1, 0x0 }, // 631 |
| 7922 | { PseudoVC_FPR64V_SE_M2, VC_FV, 0x1, 0x0 }, // 632 |
| 7923 | { PseudoVC_FPR16V_SE_M4, VC_FV, 0x2, 0x0 }, // 633 |
| 7924 | { PseudoVC_FPR32V_SE_M4, VC_FV, 0x2, 0x0 }, // 634 |
| 7925 | { PseudoVC_FPR64V_SE_M4, VC_FV, 0x2, 0x0 }, // 635 |
| 7926 | { PseudoVC_FPR16V_SE_M8, VC_FV, 0x3, 0x0 }, // 636 |
| 7927 | { PseudoVC_FPR32V_SE_M8, VC_FV, 0x3, 0x0 }, // 637 |
| 7928 | { PseudoVC_FPR64V_SE_M8, VC_FV, 0x3, 0x0 }, // 638 |
| 7929 | { PseudoVC_FPR16V_SE_MF4, VC_FV, 0x6, 0x0 }, // 639 |
| 7930 | { PseudoVC_FPR16V_SE_MF2, VC_FV, 0x7, 0x0 }, // 640 |
| 7931 | { PseudoVC_FPR32V_SE_MF2, VC_FV, 0x7, 0x0 }, // 641 |
| 7932 | { PseudoVC_FPR16VV_SE_M1, VC_FVV, 0x0, 0x0 }, // 642 |
| 7933 | { PseudoVC_FPR32VV_SE_M1, VC_FVV, 0x0, 0x0 }, // 643 |
| 7934 | { PseudoVC_FPR64VV_SE_M1, VC_FVV, 0x0, 0x0 }, // 644 |
| 7935 | { PseudoVC_FPR16VV_SE_M2, VC_FVV, 0x1, 0x0 }, // 645 |
| 7936 | { PseudoVC_FPR32VV_SE_M2, VC_FVV, 0x1, 0x0 }, // 646 |
| 7937 | { PseudoVC_FPR64VV_SE_M2, VC_FVV, 0x1, 0x0 }, // 647 |
| 7938 | { PseudoVC_FPR16VV_SE_M4, VC_FVV, 0x2, 0x0 }, // 648 |
| 7939 | { PseudoVC_FPR32VV_SE_M4, VC_FVV, 0x2, 0x0 }, // 649 |
| 7940 | { PseudoVC_FPR64VV_SE_M4, VC_FVV, 0x2, 0x0 }, // 650 |
| 7941 | { PseudoVC_FPR16VV_SE_M8, VC_FVV, 0x3, 0x0 }, // 651 |
| 7942 | { PseudoVC_FPR32VV_SE_M8, VC_FVV, 0x3, 0x0 }, // 652 |
| 7943 | { PseudoVC_FPR64VV_SE_M8, VC_FVV, 0x3, 0x0 }, // 653 |
| 7944 | { PseudoVC_FPR16VV_SE_MF4, VC_FVV, 0x6, 0x0 }, // 654 |
| 7945 | { PseudoVC_FPR16VV_SE_MF2, VC_FVV, 0x7, 0x0 }, // 655 |
| 7946 | { PseudoVC_FPR32VV_SE_MF2, VC_FVV, 0x7, 0x0 }, // 656 |
| 7947 | { PseudoVC_FPR16VW_SE_M1, VC_FVW, 0x0, 0x0 }, // 657 |
| 7948 | { PseudoVC_FPR32VW_SE_M1, VC_FVW, 0x0, 0x0 }, // 658 |
| 7949 | { PseudoVC_FPR16VW_SE_M2, VC_FVW, 0x1, 0x0 }, // 659 |
| 7950 | { PseudoVC_FPR32VW_SE_M2, VC_FVW, 0x1, 0x0 }, // 660 |
| 7951 | { PseudoVC_FPR16VW_SE_M4, VC_FVW, 0x2, 0x0 }, // 661 |
| 7952 | { PseudoVC_FPR32VW_SE_M4, VC_FVW, 0x2, 0x0 }, // 662 |
| 7953 | { PseudoVC_FPR16VW_SE_M8, VC_FVW, 0x3, 0x0 }, // 663 |
| 7954 | { PseudoVC_FPR32VW_SE_M8, VC_FVW, 0x3, 0x0 }, // 664 |
| 7955 | { PseudoVC_FPR16VW_SE_MF4, VC_FVW, 0x6, 0x0 }, // 665 |
| 7956 | { PseudoVC_FPR16VW_SE_MF2, VC_FVW, 0x7, 0x0 }, // 666 |
| 7957 | { PseudoVC_FPR32VW_SE_MF2, VC_FVW, 0x7, 0x0 }, // 667 |
| 7958 | { PseudoVC_I_SE_M1, VC_I, 0x0, 0x0 }, // 668 |
| 7959 | { PseudoVC_I_SE_M2, VC_I, 0x1, 0x0 }, // 669 |
| 7960 | { PseudoVC_I_SE_M4, VC_I, 0x2, 0x0 }, // 670 |
| 7961 | { PseudoVC_I_SE_M8, VC_I, 0x3, 0x0 }, // 671 |
| 7962 | { PseudoVC_I_SE_MF8, VC_I, 0x5, 0x0 }, // 672 |
| 7963 | { PseudoVC_I_SE_MF4, VC_I, 0x6, 0x0 }, // 673 |
| 7964 | { PseudoVC_I_SE_MF2, VC_I, 0x7, 0x0 }, // 674 |
| 7965 | { PseudoVC_IV_SE_M1, VC_IV, 0x0, 0x0 }, // 675 |
| 7966 | { PseudoVC_IV_SE_M2, VC_IV, 0x1, 0x0 }, // 676 |
| 7967 | { PseudoVC_IV_SE_M4, VC_IV, 0x2, 0x0 }, // 677 |
| 7968 | { PseudoVC_IV_SE_M8, VC_IV, 0x3, 0x0 }, // 678 |
| 7969 | { PseudoVC_IV_SE_MF8, VC_IV, 0x5, 0x0 }, // 679 |
| 7970 | { PseudoVC_IV_SE_MF4, VC_IV, 0x6, 0x0 }, // 680 |
| 7971 | { PseudoVC_IV_SE_MF2, VC_IV, 0x7, 0x0 }, // 681 |
| 7972 | { PseudoVC_IVV_SE_M1, VC_IVV, 0x0, 0x0 }, // 682 |
| 7973 | { PseudoVC_IVV_SE_M2, VC_IVV, 0x1, 0x0 }, // 683 |
| 7974 | { PseudoVC_IVV_SE_M4, VC_IVV, 0x2, 0x0 }, // 684 |
| 7975 | { PseudoVC_IVV_SE_M8, VC_IVV, 0x3, 0x0 }, // 685 |
| 7976 | { PseudoVC_IVV_SE_MF8, VC_IVV, 0x5, 0x0 }, // 686 |
| 7977 | { PseudoVC_IVV_SE_MF4, VC_IVV, 0x6, 0x0 }, // 687 |
| 7978 | { PseudoVC_IVV_SE_MF2, VC_IVV, 0x7, 0x0 }, // 688 |
| 7979 | { PseudoVC_IVW_SE_M1, VC_IVW, 0x0, 0x0 }, // 689 |
| 7980 | { PseudoVC_IVW_SE_M2, VC_IVW, 0x1, 0x0 }, // 690 |
| 7981 | { PseudoVC_IVW_SE_M4, VC_IVW, 0x2, 0x0 }, // 691 |
| 7982 | { PseudoVC_IVW_SE_MF8, VC_IVW, 0x5, 0x0 }, // 692 |
| 7983 | { PseudoVC_IVW_SE_MF4, VC_IVW, 0x6, 0x0 }, // 693 |
| 7984 | { PseudoVC_IVW_SE_MF2, VC_IVW, 0x7, 0x0 }, // 694 |
| 7985 | { PseudoVC_VV_SE_M1, VC_VV, 0x0, 0x0 }, // 695 |
| 7986 | { PseudoVC_VV_SE_M2, VC_VV, 0x1, 0x0 }, // 696 |
| 7987 | { PseudoVC_VV_SE_M4, VC_VV, 0x2, 0x0 }, // 697 |
| 7988 | { PseudoVC_VV_SE_M8, VC_VV, 0x3, 0x0 }, // 698 |
| 7989 | { PseudoVC_VV_SE_MF8, VC_VV, 0x5, 0x0 }, // 699 |
| 7990 | { PseudoVC_VV_SE_MF4, VC_VV, 0x6, 0x0 }, // 700 |
| 7991 | { PseudoVC_VV_SE_MF2, VC_VV, 0x7, 0x0 }, // 701 |
| 7992 | { PseudoVC_VVV_SE_M1, VC_VVV, 0x0, 0x0 }, // 702 |
| 7993 | { PseudoVC_VVV_SE_M2, VC_VVV, 0x1, 0x0 }, // 703 |
| 7994 | { PseudoVC_VVV_SE_M4, VC_VVV, 0x2, 0x0 }, // 704 |
| 7995 | { PseudoVC_VVV_SE_M8, VC_VVV, 0x3, 0x0 }, // 705 |
| 7996 | { PseudoVC_VVV_SE_MF8, VC_VVV, 0x5, 0x0 }, // 706 |
| 7997 | { PseudoVC_VVV_SE_MF4, VC_VVV, 0x6, 0x0 }, // 707 |
| 7998 | { PseudoVC_VVV_SE_MF2, VC_VVV, 0x7, 0x0 }, // 708 |
| 7999 | { PseudoVC_VVW_SE_M1, VC_VVW, 0x0, 0x0 }, // 709 |
| 8000 | { PseudoVC_VVW_SE_M2, VC_VVW, 0x1, 0x0 }, // 710 |
| 8001 | { PseudoVC_VVW_SE_M4, VC_VVW, 0x2, 0x0 }, // 711 |
| 8002 | { PseudoVC_VVW_SE_MF8, VC_VVW, 0x5, 0x0 }, // 712 |
| 8003 | { PseudoVC_VVW_SE_MF4, VC_VVW, 0x6, 0x0 }, // 713 |
| 8004 | { PseudoVC_VVW_SE_MF2, VC_VVW, 0x7, 0x0 }, // 714 |
| 8005 | { PseudoVC_V_FPR16V_M1, VC_V_FV, 0x0, 0x0 }, // 715 |
| 8006 | { PseudoVC_V_FPR16V_SE_M1, VC_V_FV, 0x0, 0x0 }, // 716 |
| 8007 | { PseudoVC_V_FPR32V_M1, VC_V_FV, 0x0, 0x0 }, // 717 |
| 8008 | { PseudoVC_V_FPR32V_SE_M1, VC_V_FV, 0x0, 0x0 }, // 718 |
| 8009 | { PseudoVC_V_FPR64V_M1, VC_V_FV, 0x0, 0x0 }, // 719 |
| 8010 | { PseudoVC_V_FPR64V_SE_M1, VC_V_FV, 0x0, 0x0 }, // 720 |
| 8011 | { PseudoVC_V_FPR16V_M2, VC_V_FV, 0x1, 0x0 }, // 721 |
| 8012 | { PseudoVC_V_FPR16V_SE_M2, VC_V_FV, 0x1, 0x0 }, // 722 |
| 8013 | { PseudoVC_V_FPR32V_M2, VC_V_FV, 0x1, 0x0 }, // 723 |
| 8014 | { PseudoVC_V_FPR32V_SE_M2, VC_V_FV, 0x1, 0x0 }, // 724 |
| 8015 | { PseudoVC_V_FPR64V_M2, VC_V_FV, 0x1, 0x0 }, // 725 |
| 8016 | { PseudoVC_V_FPR64V_SE_M2, VC_V_FV, 0x1, 0x0 }, // 726 |
| 8017 | { PseudoVC_V_FPR16V_M4, VC_V_FV, 0x2, 0x0 }, // 727 |
| 8018 | { PseudoVC_V_FPR16V_SE_M4, VC_V_FV, 0x2, 0x0 }, // 728 |
| 8019 | { PseudoVC_V_FPR32V_M4, VC_V_FV, 0x2, 0x0 }, // 729 |
| 8020 | { PseudoVC_V_FPR32V_SE_M4, VC_V_FV, 0x2, 0x0 }, // 730 |
| 8021 | { PseudoVC_V_FPR64V_M4, VC_V_FV, 0x2, 0x0 }, // 731 |
| 8022 | { PseudoVC_V_FPR64V_SE_M4, VC_V_FV, 0x2, 0x0 }, // 732 |
| 8023 | { PseudoVC_V_FPR16V_M8, VC_V_FV, 0x3, 0x0 }, // 733 |
| 8024 | { PseudoVC_V_FPR16V_SE_M8, VC_V_FV, 0x3, 0x0 }, // 734 |
| 8025 | { PseudoVC_V_FPR32V_M8, VC_V_FV, 0x3, 0x0 }, // 735 |
| 8026 | { PseudoVC_V_FPR32V_SE_M8, VC_V_FV, 0x3, 0x0 }, // 736 |
| 8027 | { PseudoVC_V_FPR64V_M8, VC_V_FV, 0x3, 0x0 }, // 737 |
| 8028 | { PseudoVC_V_FPR64V_SE_M8, VC_V_FV, 0x3, 0x0 }, // 738 |
| 8029 | { PseudoVC_V_FPR16V_MF4, VC_V_FV, 0x6, 0x0 }, // 739 |
| 8030 | { PseudoVC_V_FPR16V_SE_MF4, VC_V_FV, 0x6, 0x0 }, // 740 |
| 8031 | { PseudoVC_V_FPR16V_MF2, VC_V_FV, 0x7, 0x0 }, // 741 |
| 8032 | { PseudoVC_V_FPR16V_SE_MF2, VC_V_FV, 0x7, 0x0 }, // 742 |
| 8033 | { PseudoVC_V_FPR32V_MF2, VC_V_FV, 0x7, 0x0 }, // 743 |
| 8034 | { PseudoVC_V_FPR32V_SE_MF2, VC_V_FV, 0x7, 0x0 }, // 744 |
| 8035 | { PseudoVC_V_FPR16VV_M1, VC_V_FVV, 0x0, 0x0 }, // 745 |
| 8036 | { PseudoVC_V_FPR16VV_SE_M1, VC_V_FVV, 0x0, 0x0 }, // 746 |
| 8037 | { PseudoVC_V_FPR32VV_M1, VC_V_FVV, 0x0, 0x0 }, // 747 |
| 8038 | { PseudoVC_V_FPR32VV_SE_M1, VC_V_FVV, 0x0, 0x0 }, // 748 |
| 8039 | { PseudoVC_V_FPR64VV_M1, VC_V_FVV, 0x0, 0x0 }, // 749 |
| 8040 | { PseudoVC_V_FPR64VV_SE_M1, VC_V_FVV, 0x0, 0x0 }, // 750 |
| 8041 | { PseudoVC_V_FPR16VV_M2, VC_V_FVV, 0x1, 0x0 }, // 751 |
| 8042 | { PseudoVC_V_FPR16VV_SE_M2, VC_V_FVV, 0x1, 0x0 }, // 752 |
| 8043 | { PseudoVC_V_FPR32VV_M2, VC_V_FVV, 0x1, 0x0 }, // 753 |
| 8044 | { PseudoVC_V_FPR32VV_SE_M2, VC_V_FVV, 0x1, 0x0 }, // 754 |
| 8045 | { PseudoVC_V_FPR64VV_M2, VC_V_FVV, 0x1, 0x0 }, // 755 |
| 8046 | { PseudoVC_V_FPR64VV_SE_M2, VC_V_FVV, 0x1, 0x0 }, // 756 |
| 8047 | { PseudoVC_V_FPR16VV_M4, VC_V_FVV, 0x2, 0x0 }, // 757 |
| 8048 | { PseudoVC_V_FPR16VV_SE_M4, VC_V_FVV, 0x2, 0x0 }, // 758 |
| 8049 | { PseudoVC_V_FPR32VV_M4, VC_V_FVV, 0x2, 0x0 }, // 759 |
| 8050 | { PseudoVC_V_FPR32VV_SE_M4, VC_V_FVV, 0x2, 0x0 }, // 760 |
| 8051 | { PseudoVC_V_FPR64VV_M4, VC_V_FVV, 0x2, 0x0 }, // 761 |
| 8052 | { PseudoVC_V_FPR64VV_SE_M4, VC_V_FVV, 0x2, 0x0 }, // 762 |
| 8053 | { PseudoVC_V_FPR16VV_M8, VC_V_FVV, 0x3, 0x0 }, // 763 |
| 8054 | { PseudoVC_V_FPR16VV_SE_M8, VC_V_FVV, 0x3, 0x0 }, // 764 |
| 8055 | { PseudoVC_V_FPR32VV_M8, VC_V_FVV, 0x3, 0x0 }, // 765 |
| 8056 | { PseudoVC_V_FPR32VV_SE_M8, VC_V_FVV, 0x3, 0x0 }, // 766 |
| 8057 | { PseudoVC_V_FPR64VV_M8, VC_V_FVV, 0x3, 0x0 }, // 767 |
| 8058 | { PseudoVC_V_FPR64VV_SE_M8, VC_V_FVV, 0x3, 0x0 }, // 768 |
| 8059 | { PseudoVC_V_FPR16VV_MF4, VC_V_FVV, 0x6, 0x0 }, // 769 |
| 8060 | { PseudoVC_V_FPR16VV_SE_MF4, VC_V_FVV, 0x6, 0x0 }, // 770 |
| 8061 | { PseudoVC_V_FPR16VV_MF2, VC_V_FVV, 0x7, 0x0 }, // 771 |
| 8062 | { PseudoVC_V_FPR16VV_SE_MF2, VC_V_FVV, 0x7, 0x0 }, // 772 |
| 8063 | { PseudoVC_V_FPR32VV_MF2, VC_V_FVV, 0x7, 0x0 }, // 773 |
| 8064 | { PseudoVC_V_FPR32VV_SE_MF2, VC_V_FVV, 0x7, 0x0 }, // 774 |
| 8065 | { PseudoVC_V_FPR16VW_M1, VC_V_FVW, 0x0, 0x0 }, // 775 |
| 8066 | { PseudoVC_V_FPR16VW_SE_M1, VC_V_FVW, 0x0, 0x0 }, // 776 |
| 8067 | { PseudoVC_V_FPR32VW_M1, VC_V_FVW, 0x0, 0x0 }, // 777 |
| 8068 | { PseudoVC_V_FPR32VW_SE_M1, VC_V_FVW, 0x0, 0x0 }, // 778 |
| 8069 | { PseudoVC_V_FPR16VW_M2, VC_V_FVW, 0x1, 0x0 }, // 779 |
| 8070 | { PseudoVC_V_FPR16VW_SE_M2, VC_V_FVW, 0x1, 0x0 }, // 780 |
| 8071 | { PseudoVC_V_FPR32VW_M2, VC_V_FVW, 0x1, 0x0 }, // 781 |
| 8072 | { PseudoVC_V_FPR32VW_SE_M2, VC_V_FVW, 0x1, 0x0 }, // 782 |
| 8073 | { PseudoVC_V_FPR16VW_M4, VC_V_FVW, 0x2, 0x0 }, // 783 |
| 8074 | { PseudoVC_V_FPR16VW_SE_M4, VC_V_FVW, 0x2, 0x0 }, // 784 |
| 8075 | { PseudoVC_V_FPR32VW_M4, VC_V_FVW, 0x2, 0x0 }, // 785 |
| 8076 | { PseudoVC_V_FPR32VW_SE_M4, VC_V_FVW, 0x2, 0x0 }, // 786 |
| 8077 | { PseudoVC_V_FPR16VW_M8, VC_V_FVW, 0x3, 0x0 }, // 787 |
| 8078 | { PseudoVC_V_FPR16VW_SE_M8, VC_V_FVW, 0x3, 0x0 }, // 788 |
| 8079 | { PseudoVC_V_FPR32VW_M8, VC_V_FVW, 0x3, 0x0 }, // 789 |
| 8080 | { PseudoVC_V_FPR32VW_SE_M8, VC_V_FVW, 0x3, 0x0 }, // 790 |
| 8081 | { PseudoVC_V_FPR16VW_MF4, VC_V_FVW, 0x6, 0x0 }, // 791 |
| 8082 | { PseudoVC_V_FPR16VW_SE_MF4, VC_V_FVW, 0x6, 0x0 }, // 792 |
| 8083 | { PseudoVC_V_FPR16VW_MF2, VC_V_FVW, 0x7, 0x0 }, // 793 |
| 8084 | { PseudoVC_V_FPR16VW_SE_MF2, VC_V_FVW, 0x7, 0x0 }, // 794 |
| 8085 | { PseudoVC_V_FPR32VW_MF2, VC_V_FVW, 0x7, 0x0 }, // 795 |
| 8086 | { PseudoVC_V_FPR32VW_SE_MF2, VC_V_FVW, 0x7, 0x0 }, // 796 |
| 8087 | { PseudoVC_V_I_M1, VC_V_I, 0x0, 0x0 }, // 797 |
| 8088 | { PseudoVC_V_I_SE_M1, VC_V_I, 0x0, 0x0 }, // 798 |
| 8089 | { PseudoVC_V_I_M2, VC_V_I, 0x1, 0x0 }, // 799 |
| 8090 | { PseudoVC_V_I_SE_M2, VC_V_I, 0x1, 0x0 }, // 800 |
| 8091 | { PseudoVC_V_I_M4, VC_V_I, 0x2, 0x0 }, // 801 |
| 8092 | { PseudoVC_V_I_SE_M4, VC_V_I, 0x2, 0x0 }, // 802 |
| 8093 | { PseudoVC_V_I_M8, VC_V_I, 0x3, 0x0 }, // 803 |
| 8094 | { PseudoVC_V_I_SE_M8, VC_V_I, 0x3, 0x0 }, // 804 |
| 8095 | { PseudoVC_V_I_MF8, VC_V_I, 0x5, 0x0 }, // 805 |
| 8096 | { PseudoVC_V_I_SE_MF8, VC_V_I, 0x5, 0x0 }, // 806 |
| 8097 | { PseudoVC_V_I_MF4, VC_V_I, 0x6, 0x0 }, // 807 |
| 8098 | { PseudoVC_V_I_SE_MF4, VC_V_I, 0x6, 0x0 }, // 808 |
| 8099 | { PseudoVC_V_I_MF2, VC_V_I, 0x7, 0x0 }, // 809 |
| 8100 | { PseudoVC_V_I_SE_MF2, VC_V_I, 0x7, 0x0 }, // 810 |
| 8101 | { PseudoVC_V_IV_M1, VC_V_IV, 0x0, 0x0 }, // 811 |
| 8102 | { PseudoVC_V_IV_SE_M1, VC_V_IV, 0x0, 0x0 }, // 812 |
| 8103 | { PseudoVC_V_IV_M2, VC_V_IV, 0x1, 0x0 }, // 813 |
| 8104 | { PseudoVC_V_IV_SE_M2, VC_V_IV, 0x1, 0x0 }, // 814 |
| 8105 | { PseudoVC_V_IV_M4, VC_V_IV, 0x2, 0x0 }, // 815 |
| 8106 | { PseudoVC_V_IV_SE_M4, VC_V_IV, 0x2, 0x0 }, // 816 |
| 8107 | { PseudoVC_V_IV_M8, VC_V_IV, 0x3, 0x0 }, // 817 |
| 8108 | { PseudoVC_V_IV_SE_M8, VC_V_IV, 0x3, 0x0 }, // 818 |
| 8109 | { PseudoVC_V_IV_MF8, VC_V_IV, 0x5, 0x0 }, // 819 |
| 8110 | { PseudoVC_V_IV_SE_MF8, VC_V_IV, 0x5, 0x0 }, // 820 |
| 8111 | { PseudoVC_V_IV_MF4, VC_V_IV, 0x6, 0x0 }, // 821 |
| 8112 | { PseudoVC_V_IV_SE_MF4, VC_V_IV, 0x6, 0x0 }, // 822 |
| 8113 | { PseudoVC_V_IV_MF2, VC_V_IV, 0x7, 0x0 }, // 823 |
| 8114 | { PseudoVC_V_IV_SE_MF2, VC_V_IV, 0x7, 0x0 }, // 824 |
| 8115 | { PseudoVC_V_IVV_M1, VC_V_IVV, 0x0, 0x0 }, // 825 |
| 8116 | { PseudoVC_V_IVV_SE_M1, VC_V_IVV, 0x0, 0x0 }, // 826 |
| 8117 | { PseudoVC_V_IVV_M2, VC_V_IVV, 0x1, 0x0 }, // 827 |
| 8118 | { PseudoVC_V_IVV_SE_M2, VC_V_IVV, 0x1, 0x0 }, // 828 |
| 8119 | { PseudoVC_V_IVV_M4, VC_V_IVV, 0x2, 0x0 }, // 829 |
| 8120 | { PseudoVC_V_IVV_SE_M4, VC_V_IVV, 0x2, 0x0 }, // 830 |
| 8121 | { PseudoVC_V_IVV_M8, VC_V_IVV, 0x3, 0x0 }, // 831 |
| 8122 | { PseudoVC_V_IVV_SE_M8, VC_V_IVV, 0x3, 0x0 }, // 832 |
| 8123 | { PseudoVC_V_IVV_MF8, VC_V_IVV, 0x5, 0x0 }, // 833 |
| 8124 | { PseudoVC_V_IVV_SE_MF8, VC_V_IVV, 0x5, 0x0 }, // 834 |
| 8125 | { PseudoVC_V_IVV_MF4, VC_V_IVV, 0x6, 0x0 }, // 835 |
| 8126 | { PseudoVC_V_IVV_SE_MF4, VC_V_IVV, 0x6, 0x0 }, // 836 |
| 8127 | { PseudoVC_V_IVV_MF2, VC_V_IVV, 0x7, 0x0 }, // 837 |
| 8128 | { PseudoVC_V_IVV_SE_MF2, VC_V_IVV, 0x7, 0x0 }, // 838 |
| 8129 | { PseudoVC_V_IVW_M1, VC_V_IVW, 0x0, 0x0 }, // 839 |
| 8130 | { PseudoVC_V_IVW_SE_M1, VC_V_IVW, 0x0, 0x0 }, // 840 |
| 8131 | { PseudoVC_V_IVW_M2, VC_V_IVW, 0x1, 0x0 }, // 841 |
| 8132 | { PseudoVC_V_IVW_SE_M2, VC_V_IVW, 0x1, 0x0 }, // 842 |
| 8133 | { PseudoVC_V_IVW_M4, VC_V_IVW, 0x2, 0x0 }, // 843 |
| 8134 | { PseudoVC_V_IVW_SE_M4, VC_V_IVW, 0x2, 0x0 }, // 844 |
| 8135 | { PseudoVC_V_IVW_MF8, VC_V_IVW, 0x5, 0x0 }, // 845 |
| 8136 | { PseudoVC_V_IVW_SE_MF8, VC_V_IVW, 0x5, 0x0 }, // 846 |
| 8137 | { PseudoVC_V_IVW_MF4, VC_V_IVW, 0x6, 0x0 }, // 847 |
| 8138 | { PseudoVC_V_IVW_SE_MF4, VC_V_IVW, 0x6, 0x0 }, // 848 |
| 8139 | { PseudoVC_V_IVW_MF2, VC_V_IVW, 0x7, 0x0 }, // 849 |
| 8140 | { PseudoVC_V_IVW_SE_MF2, VC_V_IVW, 0x7, 0x0 }, // 850 |
| 8141 | { PseudoVC_V_VV_M1, VC_V_VV, 0x0, 0x0 }, // 851 |
| 8142 | { PseudoVC_V_VV_SE_M1, VC_V_VV, 0x0, 0x0 }, // 852 |
| 8143 | { PseudoVC_V_VV_M2, VC_V_VV, 0x1, 0x0 }, // 853 |
| 8144 | { PseudoVC_V_VV_SE_M2, VC_V_VV, 0x1, 0x0 }, // 854 |
| 8145 | { PseudoVC_V_VV_M4, VC_V_VV, 0x2, 0x0 }, // 855 |
| 8146 | { PseudoVC_V_VV_SE_M4, VC_V_VV, 0x2, 0x0 }, // 856 |
| 8147 | { PseudoVC_V_VV_M8, VC_V_VV, 0x3, 0x0 }, // 857 |
| 8148 | { PseudoVC_V_VV_SE_M8, VC_V_VV, 0x3, 0x0 }, // 858 |
| 8149 | { PseudoVC_V_VV_MF8, VC_V_VV, 0x5, 0x0 }, // 859 |
| 8150 | { PseudoVC_V_VV_SE_MF8, VC_V_VV, 0x5, 0x0 }, // 860 |
| 8151 | { PseudoVC_V_VV_MF4, VC_V_VV, 0x6, 0x0 }, // 861 |
| 8152 | { PseudoVC_V_VV_SE_MF4, VC_V_VV, 0x6, 0x0 }, // 862 |
| 8153 | { PseudoVC_V_VV_MF2, VC_V_VV, 0x7, 0x0 }, // 863 |
| 8154 | { PseudoVC_V_VV_SE_MF2, VC_V_VV, 0x7, 0x0 }, // 864 |
| 8155 | { PseudoVC_V_VVV_M1, VC_V_VVV, 0x0, 0x0 }, // 865 |
| 8156 | { PseudoVC_V_VVV_SE_M1, VC_V_VVV, 0x0, 0x0 }, // 866 |
| 8157 | { PseudoVC_V_VVV_M2, VC_V_VVV, 0x1, 0x0 }, // 867 |
| 8158 | { PseudoVC_V_VVV_SE_M2, VC_V_VVV, 0x1, 0x0 }, // 868 |
| 8159 | { PseudoVC_V_VVV_M4, VC_V_VVV, 0x2, 0x0 }, // 869 |
| 8160 | { PseudoVC_V_VVV_SE_M4, VC_V_VVV, 0x2, 0x0 }, // 870 |
| 8161 | { PseudoVC_V_VVV_M8, VC_V_VVV, 0x3, 0x0 }, // 871 |
| 8162 | { PseudoVC_V_VVV_SE_M8, VC_V_VVV, 0x3, 0x0 }, // 872 |
| 8163 | { PseudoVC_V_VVV_MF8, VC_V_VVV, 0x5, 0x0 }, // 873 |
| 8164 | { PseudoVC_V_VVV_SE_MF8, VC_V_VVV, 0x5, 0x0 }, // 874 |
| 8165 | { PseudoVC_V_VVV_MF4, VC_V_VVV, 0x6, 0x0 }, // 875 |
| 8166 | { PseudoVC_V_VVV_SE_MF4, VC_V_VVV, 0x6, 0x0 }, // 876 |
| 8167 | { PseudoVC_V_VVV_MF2, VC_V_VVV, 0x7, 0x0 }, // 877 |
| 8168 | { PseudoVC_V_VVV_SE_MF2, VC_V_VVV, 0x7, 0x0 }, // 878 |
| 8169 | { PseudoVC_V_VVW_M1, VC_V_VVW, 0x0, 0x0 }, // 879 |
| 8170 | { PseudoVC_V_VVW_SE_M1, VC_V_VVW, 0x0, 0x0 }, // 880 |
| 8171 | { PseudoVC_V_VVW_M2, VC_V_VVW, 0x1, 0x0 }, // 881 |
| 8172 | { PseudoVC_V_VVW_SE_M2, VC_V_VVW, 0x1, 0x0 }, // 882 |
| 8173 | { PseudoVC_V_VVW_M4, VC_V_VVW, 0x2, 0x0 }, // 883 |
| 8174 | { PseudoVC_V_VVW_SE_M4, VC_V_VVW, 0x2, 0x0 }, // 884 |
| 8175 | { PseudoVC_V_VVW_MF8, VC_V_VVW, 0x5, 0x0 }, // 885 |
| 8176 | { PseudoVC_V_VVW_SE_MF8, VC_V_VVW, 0x5, 0x0 }, // 886 |
| 8177 | { PseudoVC_V_VVW_MF4, VC_V_VVW, 0x6, 0x0 }, // 887 |
| 8178 | { PseudoVC_V_VVW_SE_MF4, VC_V_VVW, 0x6, 0x0 }, // 888 |
| 8179 | { PseudoVC_V_VVW_MF2, VC_V_VVW, 0x7, 0x0 }, // 889 |
| 8180 | { PseudoVC_V_VVW_SE_MF2, VC_V_VVW, 0x7, 0x0 }, // 890 |
| 8181 | { PseudoVC_V_X_M1, VC_V_X, 0x0, 0x0 }, // 891 |
| 8182 | { PseudoVC_V_X_SE_M1, VC_V_X, 0x0, 0x0 }, // 892 |
| 8183 | { PseudoVC_V_X_M2, VC_V_X, 0x1, 0x0 }, // 893 |
| 8184 | { PseudoVC_V_X_SE_M2, VC_V_X, 0x1, 0x0 }, // 894 |
| 8185 | { PseudoVC_V_X_M4, VC_V_X, 0x2, 0x0 }, // 895 |
| 8186 | { PseudoVC_V_X_SE_M4, VC_V_X, 0x2, 0x0 }, // 896 |
| 8187 | { PseudoVC_V_X_M8, VC_V_X, 0x3, 0x0 }, // 897 |
| 8188 | { PseudoVC_V_X_SE_M8, VC_V_X, 0x3, 0x0 }, // 898 |
| 8189 | { PseudoVC_V_X_MF8, VC_V_X, 0x5, 0x0 }, // 899 |
| 8190 | { PseudoVC_V_X_SE_MF8, VC_V_X, 0x5, 0x0 }, // 900 |
| 8191 | { PseudoVC_V_X_MF4, VC_V_X, 0x6, 0x0 }, // 901 |
| 8192 | { PseudoVC_V_X_SE_MF4, VC_V_X, 0x6, 0x0 }, // 902 |
| 8193 | { PseudoVC_V_X_MF2, VC_V_X, 0x7, 0x0 }, // 903 |
| 8194 | { PseudoVC_V_X_SE_MF2, VC_V_X, 0x7, 0x0 }, // 904 |
| 8195 | { PseudoVC_V_XV_M1, VC_V_XV, 0x0, 0x0 }, // 905 |
| 8196 | { PseudoVC_V_XV_SE_M1, VC_V_XV, 0x0, 0x0 }, // 906 |
| 8197 | { PseudoVC_V_XV_M2, VC_V_XV, 0x1, 0x0 }, // 907 |
| 8198 | { PseudoVC_V_XV_SE_M2, VC_V_XV, 0x1, 0x0 }, // 908 |
| 8199 | { PseudoVC_V_XV_M4, VC_V_XV, 0x2, 0x0 }, // 909 |
| 8200 | { PseudoVC_V_XV_SE_M4, VC_V_XV, 0x2, 0x0 }, // 910 |
| 8201 | { PseudoVC_V_XV_M8, VC_V_XV, 0x3, 0x0 }, // 911 |
| 8202 | { PseudoVC_V_XV_SE_M8, VC_V_XV, 0x3, 0x0 }, // 912 |
| 8203 | { PseudoVC_V_XV_MF8, VC_V_XV, 0x5, 0x0 }, // 913 |
| 8204 | { PseudoVC_V_XV_SE_MF8, VC_V_XV, 0x5, 0x0 }, // 914 |
| 8205 | { PseudoVC_V_XV_MF4, VC_V_XV, 0x6, 0x0 }, // 915 |
| 8206 | { PseudoVC_V_XV_SE_MF4, VC_V_XV, 0x6, 0x0 }, // 916 |
| 8207 | { PseudoVC_V_XV_MF2, VC_V_XV, 0x7, 0x0 }, // 917 |
| 8208 | { PseudoVC_V_XV_SE_MF2, VC_V_XV, 0x7, 0x0 }, // 918 |
| 8209 | { PseudoVC_V_XVV_M1, VC_V_XVV, 0x0, 0x0 }, // 919 |
| 8210 | { PseudoVC_V_XVV_SE_M1, VC_V_XVV, 0x0, 0x0 }, // 920 |
| 8211 | { PseudoVC_V_XVV_M2, VC_V_XVV, 0x1, 0x0 }, // 921 |
| 8212 | { PseudoVC_V_XVV_SE_M2, VC_V_XVV, 0x1, 0x0 }, // 922 |
| 8213 | { PseudoVC_V_XVV_M4, VC_V_XVV, 0x2, 0x0 }, // 923 |
| 8214 | { PseudoVC_V_XVV_SE_M4, VC_V_XVV, 0x2, 0x0 }, // 924 |
| 8215 | { PseudoVC_V_XVV_M8, VC_V_XVV, 0x3, 0x0 }, // 925 |
| 8216 | { PseudoVC_V_XVV_SE_M8, VC_V_XVV, 0x3, 0x0 }, // 926 |
| 8217 | { PseudoVC_V_XVV_MF8, VC_V_XVV, 0x5, 0x0 }, // 927 |
| 8218 | { PseudoVC_V_XVV_SE_MF8, VC_V_XVV, 0x5, 0x0 }, // 928 |
| 8219 | { PseudoVC_V_XVV_MF4, VC_V_XVV, 0x6, 0x0 }, // 929 |
| 8220 | { PseudoVC_V_XVV_SE_MF4, VC_V_XVV, 0x6, 0x0 }, // 930 |
| 8221 | { PseudoVC_V_XVV_MF2, VC_V_XVV, 0x7, 0x0 }, // 931 |
| 8222 | { PseudoVC_V_XVV_SE_MF2, VC_V_XVV, 0x7, 0x0 }, // 932 |
| 8223 | { PseudoVC_V_XVW_M1, VC_V_XVW, 0x0, 0x0 }, // 933 |
| 8224 | { PseudoVC_V_XVW_SE_M1, VC_V_XVW, 0x0, 0x0 }, // 934 |
| 8225 | { PseudoVC_V_XVW_M2, VC_V_XVW, 0x1, 0x0 }, // 935 |
| 8226 | { PseudoVC_V_XVW_SE_M2, VC_V_XVW, 0x1, 0x0 }, // 936 |
| 8227 | { PseudoVC_V_XVW_M4, VC_V_XVW, 0x2, 0x0 }, // 937 |
| 8228 | { PseudoVC_V_XVW_SE_M4, VC_V_XVW, 0x2, 0x0 }, // 938 |
| 8229 | { PseudoVC_V_XVW_MF8, VC_V_XVW, 0x5, 0x0 }, // 939 |
| 8230 | { PseudoVC_V_XVW_SE_MF8, VC_V_XVW, 0x5, 0x0 }, // 940 |
| 8231 | { PseudoVC_V_XVW_MF4, VC_V_XVW, 0x6, 0x0 }, // 941 |
| 8232 | { PseudoVC_V_XVW_SE_MF4, VC_V_XVW, 0x6, 0x0 }, // 942 |
| 8233 | { PseudoVC_V_XVW_MF2, VC_V_XVW, 0x7, 0x0 }, // 943 |
| 8234 | { PseudoVC_V_XVW_SE_MF2, VC_V_XVW, 0x7, 0x0 }, // 944 |
| 8235 | { PseudoVC_X_SE_M1, VC_X, 0x0, 0x0 }, // 945 |
| 8236 | { PseudoVC_X_SE_M2, VC_X, 0x1, 0x0 }, // 946 |
| 8237 | { PseudoVC_X_SE_M4, VC_X, 0x2, 0x0 }, // 947 |
| 8238 | { PseudoVC_X_SE_M8, VC_X, 0x3, 0x0 }, // 948 |
| 8239 | { PseudoVC_X_SE_MF8, VC_X, 0x5, 0x0 }, // 949 |
| 8240 | { PseudoVC_X_SE_MF4, VC_X, 0x6, 0x0 }, // 950 |
| 8241 | { PseudoVC_X_SE_MF2, VC_X, 0x7, 0x0 }, // 951 |
| 8242 | { PseudoVC_XV_SE_M1, VC_XV, 0x0, 0x0 }, // 952 |
| 8243 | { PseudoVC_XV_SE_M2, VC_XV, 0x1, 0x0 }, // 953 |
| 8244 | { PseudoVC_XV_SE_M4, VC_XV, 0x2, 0x0 }, // 954 |
| 8245 | { PseudoVC_XV_SE_M8, VC_XV, 0x3, 0x0 }, // 955 |
| 8246 | { PseudoVC_XV_SE_MF8, VC_XV, 0x5, 0x0 }, // 956 |
| 8247 | { PseudoVC_XV_SE_MF4, VC_XV, 0x6, 0x0 }, // 957 |
| 8248 | { PseudoVC_XV_SE_MF2, VC_XV, 0x7, 0x0 }, // 958 |
| 8249 | { PseudoVC_XVV_SE_M1, VC_XVV, 0x0, 0x0 }, // 959 |
| 8250 | { PseudoVC_XVV_SE_M2, VC_XVV, 0x1, 0x0 }, // 960 |
| 8251 | { PseudoVC_XVV_SE_M4, VC_XVV, 0x2, 0x0 }, // 961 |
| 8252 | { PseudoVC_XVV_SE_M8, VC_XVV, 0x3, 0x0 }, // 962 |
| 8253 | { PseudoVC_XVV_SE_MF8, VC_XVV, 0x5, 0x0 }, // 963 |
| 8254 | { PseudoVC_XVV_SE_MF4, VC_XVV, 0x6, 0x0 }, // 964 |
| 8255 | { PseudoVC_XVV_SE_MF2, VC_XVV, 0x7, 0x0 }, // 965 |
| 8256 | { PseudoVC_XVW_SE_M1, VC_XVW, 0x0, 0x0 }, // 966 |
| 8257 | { PseudoVC_XVW_SE_M2, VC_XVW, 0x1, 0x0 }, // 967 |
| 8258 | { PseudoVC_XVW_SE_M4, VC_XVW, 0x2, 0x0 }, // 968 |
| 8259 | { PseudoVC_XVW_SE_MF8, VC_XVW, 0x5, 0x0 }, // 969 |
| 8260 | { PseudoVC_XVW_SE_MF4, VC_XVW, 0x6, 0x0 }, // 970 |
| 8261 | { PseudoVC_XVW_SE_MF2, VC_XVW, 0x7, 0x0 }, // 971 |
| 8262 | { PseudoVDIVU_VV_M1_E8, VDIVU_VV, 0x0, 0x8 }, // 972 |
| 8263 | { PseudoVDIVU_VV_M1_E8_MASK, VDIVU_VV, 0x0, 0x8 }, // 973 |
| 8264 | { PseudoVDIVU_VV_M1_E16, VDIVU_VV, 0x0, 0x10 }, // 974 |
| 8265 | { PseudoVDIVU_VV_M1_E16_MASK, VDIVU_VV, 0x0, 0x10 }, // 975 |
| 8266 | { PseudoVDIVU_VV_M1_E32, VDIVU_VV, 0x0, 0x20 }, // 976 |
| 8267 | { PseudoVDIVU_VV_M1_E32_MASK, VDIVU_VV, 0x0, 0x20 }, // 977 |
| 8268 | { PseudoVDIVU_VV_M1_E64, VDIVU_VV, 0x0, 0x40 }, // 978 |
| 8269 | { PseudoVDIVU_VV_M1_E64_MASK, VDIVU_VV, 0x0, 0x40 }, // 979 |
| 8270 | { PseudoVDIVU_VV_M2_E8, VDIVU_VV, 0x1, 0x8 }, // 980 |
| 8271 | { PseudoVDIVU_VV_M2_E8_MASK, VDIVU_VV, 0x1, 0x8 }, // 981 |
| 8272 | { PseudoVDIVU_VV_M2_E16, VDIVU_VV, 0x1, 0x10 }, // 982 |
| 8273 | { PseudoVDIVU_VV_M2_E16_MASK, VDIVU_VV, 0x1, 0x10 }, // 983 |
| 8274 | { PseudoVDIVU_VV_M2_E32, VDIVU_VV, 0x1, 0x20 }, // 984 |
| 8275 | { PseudoVDIVU_VV_M2_E32_MASK, VDIVU_VV, 0x1, 0x20 }, // 985 |
| 8276 | { PseudoVDIVU_VV_M2_E64, VDIVU_VV, 0x1, 0x40 }, // 986 |
| 8277 | { PseudoVDIVU_VV_M2_E64_MASK, VDIVU_VV, 0x1, 0x40 }, // 987 |
| 8278 | { PseudoVDIVU_VV_M4_E8, VDIVU_VV, 0x2, 0x8 }, // 988 |
| 8279 | { PseudoVDIVU_VV_M4_E8_MASK, VDIVU_VV, 0x2, 0x8 }, // 989 |
| 8280 | { PseudoVDIVU_VV_M4_E16, VDIVU_VV, 0x2, 0x10 }, // 990 |
| 8281 | { PseudoVDIVU_VV_M4_E16_MASK, VDIVU_VV, 0x2, 0x10 }, // 991 |
| 8282 | { PseudoVDIVU_VV_M4_E32, VDIVU_VV, 0x2, 0x20 }, // 992 |
| 8283 | { PseudoVDIVU_VV_M4_E32_MASK, VDIVU_VV, 0x2, 0x20 }, // 993 |
| 8284 | { PseudoVDIVU_VV_M4_E64, VDIVU_VV, 0x2, 0x40 }, // 994 |
| 8285 | { PseudoVDIVU_VV_M4_E64_MASK, VDIVU_VV, 0x2, 0x40 }, // 995 |
| 8286 | { PseudoVDIVU_VV_M8_E8, VDIVU_VV, 0x3, 0x8 }, // 996 |
| 8287 | { PseudoVDIVU_VV_M8_E8_MASK, VDIVU_VV, 0x3, 0x8 }, // 997 |
| 8288 | { PseudoVDIVU_VV_M8_E16, VDIVU_VV, 0x3, 0x10 }, // 998 |
| 8289 | { PseudoVDIVU_VV_M8_E16_MASK, VDIVU_VV, 0x3, 0x10 }, // 999 |
| 8290 | { PseudoVDIVU_VV_M8_E32, VDIVU_VV, 0x3, 0x20 }, // 1000 |
| 8291 | { PseudoVDIVU_VV_M8_E32_MASK, VDIVU_VV, 0x3, 0x20 }, // 1001 |
| 8292 | { PseudoVDIVU_VV_M8_E64, VDIVU_VV, 0x3, 0x40 }, // 1002 |
| 8293 | { PseudoVDIVU_VV_M8_E64_MASK, VDIVU_VV, 0x3, 0x40 }, // 1003 |
| 8294 | { PseudoVDIVU_VV_MF8_E8, VDIVU_VV, 0x5, 0x8 }, // 1004 |
| 8295 | { PseudoVDIVU_VV_MF8_E8_MASK, VDIVU_VV, 0x5, 0x8 }, // 1005 |
| 8296 | { PseudoVDIVU_VV_MF4_E8, VDIVU_VV, 0x6, 0x8 }, // 1006 |
| 8297 | { PseudoVDIVU_VV_MF4_E8_MASK, VDIVU_VV, 0x6, 0x8 }, // 1007 |
| 8298 | { PseudoVDIVU_VV_MF4_E16, VDIVU_VV, 0x6, 0x10 }, // 1008 |
| 8299 | { PseudoVDIVU_VV_MF4_E16_MASK, VDIVU_VV, 0x6, 0x10 }, // 1009 |
| 8300 | { PseudoVDIVU_VV_MF2_E8, VDIVU_VV, 0x7, 0x8 }, // 1010 |
| 8301 | { PseudoVDIVU_VV_MF2_E8_MASK, VDIVU_VV, 0x7, 0x8 }, // 1011 |
| 8302 | { PseudoVDIVU_VV_MF2_E16, VDIVU_VV, 0x7, 0x10 }, // 1012 |
| 8303 | { PseudoVDIVU_VV_MF2_E16_MASK, VDIVU_VV, 0x7, 0x10 }, // 1013 |
| 8304 | { PseudoVDIVU_VV_MF2_E32, VDIVU_VV, 0x7, 0x20 }, // 1014 |
| 8305 | { PseudoVDIVU_VV_MF2_E32_MASK, VDIVU_VV, 0x7, 0x20 }, // 1015 |
| 8306 | { PseudoVDIVU_VX_M1_E8, VDIVU_VX, 0x0, 0x8 }, // 1016 |
| 8307 | { PseudoVDIVU_VX_M1_E8_MASK, VDIVU_VX, 0x0, 0x8 }, // 1017 |
| 8308 | { PseudoVDIVU_VX_M1_E16, VDIVU_VX, 0x0, 0x10 }, // 1018 |
| 8309 | { PseudoVDIVU_VX_M1_E16_MASK, VDIVU_VX, 0x0, 0x10 }, // 1019 |
| 8310 | { PseudoVDIVU_VX_M1_E32, VDIVU_VX, 0x0, 0x20 }, // 1020 |
| 8311 | { PseudoVDIVU_VX_M1_E32_MASK, VDIVU_VX, 0x0, 0x20 }, // 1021 |
| 8312 | { PseudoVDIVU_VX_M1_E64, VDIVU_VX, 0x0, 0x40 }, // 1022 |
| 8313 | { PseudoVDIVU_VX_M1_E64_MASK, VDIVU_VX, 0x0, 0x40 }, // 1023 |
| 8314 | { PseudoVDIVU_VX_M2_E8, VDIVU_VX, 0x1, 0x8 }, // 1024 |
| 8315 | { PseudoVDIVU_VX_M2_E8_MASK, VDIVU_VX, 0x1, 0x8 }, // 1025 |
| 8316 | { PseudoVDIVU_VX_M2_E16, VDIVU_VX, 0x1, 0x10 }, // 1026 |
| 8317 | { PseudoVDIVU_VX_M2_E16_MASK, VDIVU_VX, 0x1, 0x10 }, // 1027 |
| 8318 | { PseudoVDIVU_VX_M2_E32, VDIVU_VX, 0x1, 0x20 }, // 1028 |
| 8319 | { PseudoVDIVU_VX_M2_E32_MASK, VDIVU_VX, 0x1, 0x20 }, // 1029 |
| 8320 | { PseudoVDIVU_VX_M2_E64, VDIVU_VX, 0x1, 0x40 }, // 1030 |
| 8321 | { PseudoVDIVU_VX_M2_E64_MASK, VDIVU_VX, 0x1, 0x40 }, // 1031 |
| 8322 | { PseudoVDIVU_VX_M4_E8, VDIVU_VX, 0x2, 0x8 }, // 1032 |
| 8323 | { PseudoVDIVU_VX_M4_E8_MASK, VDIVU_VX, 0x2, 0x8 }, // 1033 |
| 8324 | { PseudoVDIVU_VX_M4_E16, VDIVU_VX, 0x2, 0x10 }, // 1034 |
| 8325 | { PseudoVDIVU_VX_M4_E16_MASK, VDIVU_VX, 0x2, 0x10 }, // 1035 |
| 8326 | { PseudoVDIVU_VX_M4_E32, VDIVU_VX, 0x2, 0x20 }, // 1036 |
| 8327 | { PseudoVDIVU_VX_M4_E32_MASK, VDIVU_VX, 0x2, 0x20 }, // 1037 |
| 8328 | { PseudoVDIVU_VX_M4_E64, VDIVU_VX, 0x2, 0x40 }, // 1038 |
| 8329 | { PseudoVDIVU_VX_M4_E64_MASK, VDIVU_VX, 0x2, 0x40 }, // 1039 |
| 8330 | { PseudoVDIVU_VX_M8_E8, VDIVU_VX, 0x3, 0x8 }, // 1040 |
| 8331 | { PseudoVDIVU_VX_M8_E8_MASK, VDIVU_VX, 0x3, 0x8 }, // 1041 |
| 8332 | { PseudoVDIVU_VX_M8_E16, VDIVU_VX, 0x3, 0x10 }, // 1042 |
| 8333 | { PseudoVDIVU_VX_M8_E16_MASK, VDIVU_VX, 0x3, 0x10 }, // 1043 |
| 8334 | { PseudoVDIVU_VX_M8_E32, VDIVU_VX, 0x3, 0x20 }, // 1044 |
| 8335 | { PseudoVDIVU_VX_M8_E32_MASK, VDIVU_VX, 0x3, 0x20 }, // 1045 |
| 8336 | { PseudoVDIVU_VX_M8_E64, VDIVU_VX, 0x3, 0x40 }, // 1046 |
| 8337 | { PseudoVDIVU_VX_M8_E64_MASK, VDIVU_VX, 0x3, 0x40 }, // 1047 |
| 8338 | { PseudoVDIVU_VX_MF8_E8, VDIVU_VX, 0x5, 0x8 }, // 1048 |
| 8339 | { PseudoVDIVU_VX_MF8_E8_MASK, VDIVU_VX, 0x5, 0x8 }, // 1049 |
| 8340 | { PseudoVDIVU_VX_MF4_E8, VDIVU_VX, 0x6, 0x8 }, // 1050 |
| 8341 | { PseudoVDIVU_VX_MF4_E8_MASK, VDIVU_VX, 0x6, 0x8 }, // 1051 |
| 8342 | { PseudoVDIVU_VX_MF4_E16, VDIVU_VX, 0x6, 0x10 }, // 1052 |
| 8343 | { PseudoVDIVU_VX_MF4_E16_MASK, VDIVU_VX, 0x6, 0x10 }, // 1053 |
| 8344 | { PseudoVDIVU_VX_MF2_E8, VDIVU_VX, 0x7, 0x8 }, // 1054 |
| 8345 | { PseudoVDIVU_VX_MF2_E8_MASK, VDIVU_VX, 0x7, 0x8 }, // 1055 |
| 8346 | { PseudoVDIVU_VX_MF2_E16, VDIVU_VX, 0x7, 0x10 }, // 1056 |
| 8347 | { PseudoVDIVU_VX_MF2_E16_MASK, VDIVU_VX, 0x7, 0x10 }, // 1057 |
| 8348 | { PseudoVDIVU_VX_MF2_E32, VDIVU_VX, 0x7, 0x20 }, // 1058 |
| 8349 | { PseudoVDIVU_VX_MF2_E32_MASK, VDIVU_VX, 0x7, 0x20 }, // 1059 |
| 8350 | { PseudoVDIV_VV_M1_E8, VDIV_VV, 0x0, 0x8 }, // 1060 |
| 8351 | { PseudoVDIV_VV_M1_E8_MASK, VDIV_VV, 0x0, 0x8 }, // 1061 |
| 8352 | { PseudoVDIV_VV_M1_E16, VDIV_VV, 0x0, 0x10 }, // 1062 |
| 8353 | { PseudoVDIV_VV_M1_E16_MASK, VDIV_VV, 0x0, 0x10 }, // 1063 |
| 8354 | { PseudoVDIV_VV_M1_E32, VDIV_VV, 0x0, 0x20 }, // 1064 |
| 8355 | { PseudoVDIV_VV_M1_E32_MASK, VDIV_VV, 0x0, 0x20 }, // 1065 |
| 8356 | { PseudoVDIV_VV_M1_E64, VDIV_VV, 0x0, 0x40 }, // 1066 |
| 8357 | { PseudoVDIV_VV_M1_E64_MASK, VDIV_VV, 0x0, 0x40 }, // 1067 |
| 8358 | { PseudoVDIV_VV_M2_E8, VDIV_VV, 0x1, 0x8 }, // 1068 |
| 8359 | { PseudoVDIV_VV_M2_E8_MASK, VDIV_VV, 0x1, 0x8 }, // 1069 |
| 8360 | { PseudoVDIV_VV_M2_E16, VDIV_VV, 0x1, 0x10 }, // 1070 |
| 8361 | { PseudoVDIV_VV_M2_E16_MASK, VDIV_VV, 0x1, 0x10 }, // 1071 |
| 8362 | { PseudoVDIV_VV_M2_E32, VDIV_VV, 0x1, 0x20 }, // 1072 |
| 8363 | { PseudoVDIV_VV_M2_E32_MASK, VDIV_VV, 0x1, 0x20 }, // 1073 |
| 8364 | { PseudoVDIV_VV_M2_E64, VDIV_VV, 0x1, 0x40 }, // 1074 |
| 8365 | { PseudoVDIV_VV_M2_E64_MASK, VDIV_VV, 0x1, 0x40 }, // 1075 |
| 8366 | { PseudoVDIV_VV_M4_E8, VDIV_VV, 0x2, 0x8 }, // 1076 |
| 8367 | { PseudoVDIV_VV_M4_E8_MASK, VDIV_VV, 0x2, 0x8 }, // 1077 |
| 8368 | { PseudoVDIV_VV_M4_E16, VDIV_VV, 0x2, 0x10 }, // 1078 |
| 8369 | { PseudoVDIV_VV_M4_E16_MASK, VDIV_VV, 0x2, 0x10 }, // 1079 |
| 8370 | { PseudoVDIV_VV_M4_E32, VDIV_VV, 0x2, 0x20 }, // 1080 |
| 8371 | { PseudoVDIV_VV_M4_E32_MASK, VDIV_VV, 0x2, 0x20 }, // 1081 |
| 8372 | { PseudoVDIV_VV_M4_E64, VDIV_VV, 0x2, 0x40 }, // 1082 |
| 8373 | { PseudoVDIV_VV_M4_E64_MASK, VDIV_VV, 0x2, 0x40 }, // 1083 |
| 8374 | { PseudoVDIV_VV_M8_E8, VDIV_VV, 0x3, 0x8 }, // 1084 |
| 8375 | { PseudoVDIV_VV_M8_E8_MASK, VDIV_VV, 0x3, 0x8 }, // 1085 |
| 8376 | { PseudoVDIV_VV_M8_E16, VDIV_VV, 0x3, 0x10 }, // 1086 |
| 8377 | { PseudoVDIV_VV_M8_E16_MASK, VDIV_VV, 0x3, 0x10 }, // 1087 |
| 8378 | { PseudoVDIV_VV_M8_E32, VDIV_VV, 0x3, 0x20 }, // 1088 |
| 8379 | { PseudoVDIV_VV_M8_E32_MASK, VDIV_VV, 0x3, 0x20 }, // 1089 |
| 8380 | { PseudoVDIV_VV_M8_E64, VDIV_VV, 0x3, 0x40 }, // 1090 |
| 8381 | { PseudoVDIV_VV_M8_E64_MASK, VDIV_VV, 0x3, 0x40 }, // 1091 |
| 8382 | { PseudoVDIV_VV_MF8_E8, VDIV_VV, 0x5, 0x8 }, // 1092 |
| 8383 | { PseudoVDIV_VV_MF8_E8_MASK, VDIV_VV, 0x5, 0x8 }, // 1093 |
| 8384 | { PseudoVDIV_VV_MF4_E8, VDIV_VV, 0x6, 0x8 }, // 1094 |
| 8385 | { PseudoVDIV_VV_MF4_E8_MASK, VDIV_VV, 0x6, 0x8 }, // 1095 |
| 8386 | { PseudoVDIV_VV_MF4_E16, VDIV_VV, 0x6, 0x10 }, // 1096 |
| 8387 | { PseudoVDIV_VV_MF4_E16_MASK, VDIV_VV, 0x6, 0x10 }, // 1097 |
| 8388 | { PseudoVDIV_VV_MF2_E8, VDIV_VV, 0x7, 0x8 }, // 1098 |
| 8389 | { PseudoVDIV_VV_MF2_E8_MASK, VDIV_VV, 0x7, 0x8 }, // 1099 |
| 8390 | { PseudoVDIV_VV_MF2_E16, VDIV_VV, 0x7, 0x10 }, // 1100 |
| 8391 | { PseudoVDIV_VV_MF2_E16_MASK, VDIV_VV, 0x7, 0x10 }, // 1101 |
| 8392 | { PseudoVDIV_VV_MF2_E32, VDIV_VV, 0x7, 0x20 }, // 1102 |
| 8393 | { PseudoVDIV_VV_MF2_E32_MASK, VDIV_VV, 0x7, 0x20 }, // 1103 |
| 8394 | { PseudoVDIV_VX_M1_E8, VDIV_VX, 0x0, 0x8 }, // 1104 |
| 8395 | { PseudoVDIV_VX_M1_E8_MASK, VDIV_VX, 0x0, 0x8 }, // 1105 |
| 8396 | { PseudoVDIV_VX_M1_E16, VDIV_VX, 0x0, 0x10 }, // 1106 |
| 8397 | { PseudoVDIV_VX_M1_E16_MASK, VDIV_VX, 0x0, 0x10 }, // 1107 |
| 8398 | { PseudoVDIV_VX_M1_E32, VDIV_VX, 0x0, 0x20 }, // 1108 |
| 8399 | { PseudoVDIV_VX_M1_E32_MASK, VDIV_VX, 0x0, 0x20 }, // 1109 |
| 8400 | { PseudoVDIV_VX_M1_E64, VDIV_VX, 0x0, 0x40 }, // 1110 |
| 8401 | { PseudoVDIV_VX_M1_E64_MASK, VDIV_VX, 0x0, 0x40 }, // 1111 |
| 8402 | { PseudoVDIV_VX_M2_E8, VDIV_VX, 0x1, 0x8 }, // 1112 |
| 8403 | { PseudoVDIV_VX_M2_E8_MASK, VDIV_VX, 0x1, 0x8 }, // 1113 |
| 8404 | { PseudoVDIV_VX_M2_E16, VDIV_VX, 0x1, 0x10 }, // 1114 |
| 8405 | { PseudoVDIV_VX_M2_E16_MASK, VDIV_VX, 0x1, 0x10 }, // 1115 |
| 8406 | { PseudoVDIV_VX_M2_E32, VDIV_VX, 0x1, 0x20 }, // 1116 |
| 8407 | { PseudoVDIV_VX_M2_E32_MASK, VDIV_VX, 0x1, 0x20 }, // 1117 |
| 8408 | { PseudoVDIV_VX_M2_E64, VDIV_VX, 0x1, 0x40 }, // 1118 |
| 8409 | { PseudoVDIV_VX_M2_E64_MASK, VDIV_VX, 0x1, 0x40 }, // 1119 |
| 8410 | { PseudoVDIV_VX_M4_E8, VDIV_VX, 0x2, 0x8 }, // 1120 |
| 8411 | { PseudoVDIV_VX_M4_E8_MASK, VDIV_VX, 0x2, 0x8 }, // 1121 |
| 8412 | { PseudoVDIV_VX_M4_E16, VDIV_VX, 0x2, 0x10 }, // 1122 |
| 8413 | { PseudoVDIV_VX_M4_E16_MASK, VDIV_VX, 0x2, 0x10 }, // 1123 |
| 8414 | { PseudoVDIV_VX_M4_E32, VDIV_VX, 0x2, 0x20 }, // 1124 |
| 8415 | { PseudoVDIV_VX_M4_E32_MASK, VDIV_VX, 0x2, 0x20 }, // 1125 |
| 8416 | { PseudoVDIV_VX_M4_E64, VDIV_VX, 0x2, 0x40 }, // 1126 |
| 8417 | { PseudoVDIV_VX_M4_E64_MASK, VDIV_VX, 0x2, 0x40 }, // 1127 |
| 8418 | { PseudoVDIV_VX_M8_E8, VDIV_VX, 0x3, 0x8 }, // 1128 |
| 8419 | { PseudoVDIV_VX_M8_E8_MASK, VDIV_VX, 0x3, 0x8 }, // 1129 |
| 8420 | { PseudoVDIV_VX_M8_E16, VDIV_VX, 0x3, 0x10 }, // 1130 |
| 8421 | { PseudoVDIV_VX_M8_E16_MASK, VDIV_VX, 0x3, 0x10 }, // 1131 |
| 8422 | { PseudoVDIV_VX_M8_E32, VDIV_VX, 0x3, 0x20 }, // 1132 |
| 8423 | { PseudoVDIV_VX_M8_E32_MASK, VDIV_VX, 0x3, 0x20 }, // 1133 |
| 8424 | { PseudoVDIV_VX_M8_E64, VDIV_VX, 0x3, 0x40 }, // 1134 |
| 8425 | { PseudoVDIV_VX_M8_E64_MASK, VDIV_VX, 0x3, 0x40 }, // 1135 |
| 8426 | { PseudoVDIV_VX_MF8_E8, VDIV_VX, 0x5, 0x8 }, // 1136 |
| 8427 | { PseudoVDIV_VX_MF8_E8_MASK, VDIV_VX, 0x5, 0x8 }, // 1137 |
| 8428 | { PseudoVDIV_VX_MF4_E8, VDIV_VX, 0x6, 0x8 }, // 1138 |
| 8429 | { PseudoVDIV_VX_MF4_E8_MASK, VDIV_VX, 0x6, 0x8 }, // 1139 |
| 8430 | { PseudoVDIV_VX_MF4_E16, VDIV_VX, 0x6, 0x10 }, // 1140 |
| 8431 | { PseudoVDIV_VX_MF4_E16_MASK, VDIV_VX, 0x6, 0x10 }, // 1141 |
| 8432 | { PseudoVDIV_VX_MF2_E8, VDIV_VX, 0x7, 0x8 }, // 1142 |
| 8433 | { PseudoVDIV_VX_MF2_E8_MASK, VDIV_VX, 0x7, 0x8 }, // 1143 |
| 8434 | { PseudoVDIV_VX_MF2_E16, VDIV_VX, 0x7, 0x10 }, // 1144 |
| 8435 | { PseudoVDIV_VX_MF2_E16_MASK, VDIV_VX, 0x7, 0x10 }, // 1145 |
| 8436 | { PseudoVDIV_VX_MF2_E32, VDIV_VX, 0x7, 0x20 }, // 1146 |
| 8437 | { PseudoVDIV_VX_MF2_E32_MASK, VDIV_VX, 0x7, 0x20 }, // 1147 |
| 8438 | { PseudoVFADD_VFPR16_M1_E16, VFADD_VF, 0x0, 0x10 }, // 1148 |
| 8439 | { PseudoVFADD_VFPR16_M1_E16_MASK, VFADD_VF, 0x0, 0x10 }, // 1149 |
| 8440 | { PseudoVFADD_VFPR32_M1_E32, VFADD_VF, 0x0, 0x20 }, // 1150 |
| 8441 | { PseudoVFADD_VFPR32_M1_E32_MASK, VFADD_VF, 0x0, 0x20 }, // 1151 |
| 8442 | { PseudoVFADD_VFPR64_M1_E64, VFADD_VF, 0x0, 0x40 }, // 1152 |
| 8443 | { PseudoVFADD_VFPR64_M1_E64_MASK, VFADD_VF, 0x0, 0x40 }, // 1153 |
| 8444 | { PseudoVFADD_VFPR16_M2_E16, VFADD_VF, 0x1, 0x10 }, // 1154 |
| 8445 | { PseudoVFADD_VFPR16_M2_E16_MASK, VFADD_VF, 0x1, 0x10 }, // 1155 |
| 8446 | { PseudoVFADD_VFPR32_M2_E32, VFADD_VF, 0x1, 0x20 }, // 1156 |
| 8447 | { PseudoVFADD_VFPR32_M2_E32_MASK, VFADD_VF, 0x1, 0x20 }, // 1157 |
| 8448 | { PseudoVFADD_VFPR64_M2_E64, VFADD_VF, 0x1, 0x40 }, // 1158 |
| 8449 | { PseudoVFADD_VFPR64_M2_E64_MASK, VFADD_VF, 0x1, 0x40 }, // 1159 |
| 8450 | { PseudoVFADD_VFPR16_M4_E16, VFADD_VF, 0x2, 0x10 }, // 1160 |
| 8451 | { PseudoVFADD_VFPR16_M4_E16_MASK, VFADD_VF, 0x2, 0x10 }, // 1161 |
| 8452 | { PseudoVFADD_VFPR32_M4_E32, VFADD_VF, 0x2, 0x20 }, // 1162 |
| 8453 | { PseudoVFADD_VFPR32_M4_E32_MASK, VFADD_VF, 0x2, 0x20 }, // 1163 |
| 8454 | { PseudoVFADD_VFPR64_M4_E64, VFADD_VF, 0x2, 0x40 }, // 1164 |
| 8455 | { PseudoVFADD_VFPR64_M4_E64_MASK, VFADD_VF, 0x2, 0x40 }, // 1165 |
| 8456 | { PseudoVFADD_VFPR16_M8_E16, VFADD_VF, 0x3, 0x10 }, // 1166 |
| 8457 | { PseudoVFADD_VFPR16_M8_E16_MASK, VFADD_VF, 0x3, 0x10 }, // 1167 |
| 8458 | { PseudoVFADD_VFPR32_M8_E32, VFADD_VF, 0x3, 0x20 }, // 1168 |
| 8459 | { PseudoVFADD_VFPR32_M8_E32_MASK, VFADD_VF, 0x3, 0x20 }, // 1169 |
| 8460 | { PseudoVFADD_VFPR64_M8_E64, VFADD_VF, 0x3, 0x40 }, // 1170 |
| 8461 | { PseudoVFADD_VFPR64_M8_E64_MASK, VFADD_VF, 0x3, 0x40 }, // 1171 |
| 8462 | { PseudoVFADD_VFPR16_MF4_E16, VFADD_VF, 0x6, 0x10 }, // 1172 |
| 8463 | { PseudoVFADD_VFPR16_MF4_E16_MASK, VFADD_VF, 0x6, 0x10 }, // 1173 |
| 8464 | { PseudoVFADD_VFPR16_MF2_E16, VFADD_VF, 0x7, 0x10 }, // 1174 |
| 8465 | { PseudoVFADD_VFPR16_MF2_E16_MASK, VFADD_VF, 0x7, 0x10 }, // 1175 |
| 8466 | { PseudoVFADD_VFPR32_MF2_E32, VFADD_VF, 0x7, 0x20 }, // 1176 |
| 8467 | { PseudoVFADD_VFPR32_MF2_E32_MASK, VFADD_VF, 0x7, 0x20 }, // 1177 |
| 8468 | { PseudoVFADD_VV_M1_E16, VFADD_VV, 0x0, 0x10 }, // 1178 |
| 8469 | { PseudoVFADD_VV_M1_E16_MASK, VFADD_VV, 0x0, 0x10 }, // 1179 |
| 8470 | { PseudoVFADD_VV_M1_E32, VFADD_VV, 0x0, 0x20 }, // 1180 |
| 8471 | { PseudoVFADD_VV_M1_E32_MASK, VFADD_VV, 0x0, 0x20 }, // 1181 |
| 8472 | { PseudoVFADD_VV_M1_E64, VFADD_VV, 0x0, 0x40 }, // 1182 |
| 8473 | { PseudoVFADD_VV_M1_E64_MASK, VFADD_VV, 0x0, 0x40 }, // 1183 |
| 8474 | { PseudoVFADD_VV_M2_E16, VFADD_VV, 0x1, 0x10 }, // 1184 |
| 8475 | { PseudoVFADD_VV_M2_E16_MASK, VFADD_VV, 0x1, 0x10 }, // 1185 |
| 8476 | { PseudoVFADD_VV_M2_E32, VFADD_VV, 0x1, 0x20 }, // 1186 |
| 8477 | { PseudoVFADD_VV_M2_E32_MASK, VFADD_VV, 0x1, 0x20 }, // 1187 |
| 8478 | { PseudoVFADD_VV_M2_E64, VFADD_VV, 0x1, 0x40 }, // 1188 |
| 8479 | { PseudoVFADD_VV_M2_E64_MASK, VFADD_VV, 0x1, 0x40 }, // 1189 |
| 8480 | { PseudoVFADD_VV_M4_E16, VFADD_VV, 0x2, 0x10 }, // 1190 |
| 8481 | { PseudoVFADD_VV_M4_E16_MASK, VFADD_VV, 0x2, 0x10 }, // 1191 |
| 8482 | { PseudoVFADD_VV_M4_E32, VFADD_VV, 0x2, 0x20 }, // 1192 |
| 8483 | { PseudoVFADD_VV_M4_E32_MASK, VFADD_VV, 0x2, 0x20 }, // 1193 |
| 8484 | { PseudoVFADD_VV_M4_E64, VFADD_VV, 0x2, 0x40 }, // 1194 |
| 8485 | { PseudoVFADD_VV_M4_E64_MASK, VFADD_VV, 0x2, 0x40 }, // 1195 |
| 8486 | { PseudoVFADD_VV_M8_E16, VFADD_VV, 0x3, 0x10 }, // 1196 |
| 8487 | { PseudoVFADD_VV_M8_E16_MASK, VFADD_VV, 0x3, 0x10 }, // 1197 |
| 8488 | { PseudoVFADD_VV_M8_E32, VFADD_VV, 0x3, 0x20 }, // 1198 |
| 8489 | { PseudoVFADD_VV_M8_E32_MASK, VFADD_VV, 0x3, 0x20 }, // 1199 |
| 8490 | { PseudoVFADD_VV_M8_E64, VFADD_VV, 0x3, 0x40 }, // 1200 |
| 8491 | { PseudoVFADD_VV_M8_E64_MASK, VFADD_VV, 0x3, 0x40 }, // 1201 |
| 8492 | { PseudoVFADD_VV_MF4_E16, VFADD_VV, 0x6, 0x10 }, // 1202 |
| 8493 | { PseudoVFADD_VV_MF4_E16_MASK, VFADD_VV, 0x6, 0x10 }, // 1203 |
| 8494 | { PseudoVFADD_VV_MF2_E16, VFADD_VV, 0x7, 0x10 }, // 1204 |
| 8495 | { PseudoVFADD_VV_MF2_E16_MASK, VFADD_VV, 0x7, 0x10 }, // 1205 |
| 8496 | { PseudoVFADD_VV_MF2_E32, VFADD_VV, 0x7, 0x20 }, // 1206 |
| 8497 | { PseudoVFADD_VV_MF2_E32_MASK, VFADD_VV, 0x7, 0x20 }, // 1207 |
| 8498 | { PseudoVFCLASS_V_M1, VFCLASS_V, 0x0, 0x0 }, // 1208 |
| 8499 | { PseudoVFCLASS_V_M1_MASK, VFCLASS_V, 0x0, 0x0 }, // 1209 |
| 8500 | { PseudoVFCLASS_V_M2, VFCLASS_V, 0x1, 0x0 }, // 1210 |
| 8501 | { PseudoVFCLASS_V_M2_MASK, VFCLASS_V, 0x1, 0x0 }, // 1211 |
| 8502 | { PseudoVFCLASS_V_M4, VFCLASS_V, 0x2, 0x0 }, // 1212 |
| 8503 | { PseudoVFCLASS_V_M4_MASK, VFCLASS_V, 0x2, 0x0 }, // 1213 |
| 8504 | { PseudoVFCLASS_V_M8, VFCLASS_V, 0x3, 0x0 }, // 1214 |
| 8505 | { PseudoVFCLASS_V_M8_MASK, VFCLASS_V, 0x3, 0x0 }, // 1215 |
| 8506 | { PseudoVFCLASS_V_MF4, VFCLASS_V, 0x6, 0x0 }, // 1216 |
| 8507 | { PseudoVFCLASS_V_MF4_MASK, VFCLASS_V, 0x6, 0x0 }, // 1217 |
| 8508 | { PseudoVFCLASS_V_MF2, VFCLASS_V, 0x7, 0x0 }, // 1218 |
| 8509 | { PseudoVFCLASS_V_MF2_MASK, VFCLASS_V, 0x7, 0x0 }, // 1219 |
| 8510 | { PseudoVFCVT_F_XU_V_M1_E16, VFCVT_F_XU_V, 0x0, 0x10 }, // 1220 |
| 8511 | { PseudoVFCVT_F_XU_V_M1_E16_MASK, VFCVT_F_XU_V, 0x0, 0x10 }, // 1221 |
| 8512 | { PseudoVFCVT_RM_F_XU_V_M1_E16, VFCVT_F_XU_V, 0x0, 0x10 }, // 1222 |
| 8513 | { PseudoVFCVT_RM_F_XU_V_M1_E16_MASK, VFCVT_F_XU_V, 0x0, 0x10 }, // 1223 |
| 8514 | { PseudoVFCVT_F_XU_V_M1_E32, VFCVT_F_XU_V, 0x0, 0x20 }, // 1224 |
| 8515 | { PseudoVFCVT_F_XU_V_M1_E32_MASK, VFCVT_F_XU_V, 0x0, 0x20 }, // 1225 |
| 8516 | { PseudoVFCVT_RM_F_XU_V_M1_E32, VFCVT_F_XU_V, 0x0, 0x20 }, // 1226 |
| 8517 | { PseudoVFCVT_RM_F_XU_V_M1_E32_MASK, VFCVT_F_XU_V, 0x0, 0x20 }, // 1227 |
| 8518 | { PseudoVFCVT_F_XU_V_M1_E64, VFCVT_F_XU_V, 0x0, 0x40 }, // 1228 |
| 8519 | { PseudoVFCVT_F_XU_V_M1_E64_MASK, VFCVT_F_XU_V, 0x0, 0x40 }, // 1229 |
| 8520 | { PseudoVFCVT_RM_F_XU_V_M1_E64, VFCVT_F_XU_V, 0x0, 0x40 }, // 1230 |
| 8521 | { PseudoVFCVT_RM_F_XU_V_M1_E64_MASK, VFCVT_F_XU_V, 0x0, 0x40 }, // 1231 |
| 8522 | { PseudoVFCVT_F_XU_V_M2_E16, VFCVT_F_XU_V, 0x1, 0x10 }, // 1232 |
| 8523 | { PseudoVFCVT_F_XU_V_M2_E16_MASK, VFCVT_F_XU_V, 0x1, 0x10 }, // 1233 |
| 8524 | { PseudoVFCVT_RM_F_XU_V_M2_E16, VFCVT_F_XU_V, 0x1, 0x10 }, // 1234 |
| 8525 | { PseudoVFCVT_RM_F_XU_V_M2_E16_MASK, VFCVT_F_XU_V, 0x1, 0x10 }, // 1235 |
| 8526 | { PseudoVFCVT_F_XU_V_M2_E32, VFCVT_F_XU_V, 0x1, 0x20 }, // 1236 |
| 8527 | { PseudoVFCVT_F_XU_V_M2_E32_MASK, VFCVT_F_XU_V, 0x1, 0x20 }, // 1237 |
| 8528 | { PseudoVFCVT_RM_F_XU_V_M2_E32, VFCVT_F_XU_V, 0x1, 0x20 }, // 1238 |
| 8529 | { PseudoVFCVT_RM_F_XU_V_M2_E32_MASK, VFCVT_F_XU_V, 0x1, 0x20 }, // 1239 |
| 8530 | { PseudoVFCVT_F_XU_V_M2_E64, VFCVT_F_XU_V, 0x1, 0x40 }, // 1240 |
| 8531 | { PseudoVFCVT_F_XU_V_M2_E64_MASK, VFCVT_F_XU_V, 0x1, 0x40 }, // 1241 |
| 8532 | { PseudoVFCVT_RM_F_XU_V_M2_E64, VFCVT_F_XU_V, 0x1, 0x40 }, // 1242 |
| 8533 | { PseudoVFCVT_RM_F_XU_V_M2_E64_MASK, VFCVT_F_XU_V, 0x1, 0x40 }, // 1243 |
| 8534 | { PseudoVFCVT_F_XU_V_M4_E16, VFCVT_F_XU_V, 0x2, 0x10 }, // 1244 |
| 8535 | { PseudoVFCVT_F_XU_V_M4_E16_MASK, VFCVT_F_XU_V, 0x2, 0x10 }, // 1245 |
| 8536 | { PseudoVFCVT_RM_F_XU_V_M4_E16, VFCVT_F_XU_V, 0x2, 0x10 }, // 1246 |
| 8537 | { PseudoVFCVT_RM_F_XU_V_M4_E16_MASK, VFCVT_F_XU_V, 0x2, 0x10 }, // 1247 |
| 8538 | { PseudoVFCVT_F_XU_V_M4_E32, VFCVT_F_XU_V, 0x2, 0x20 }, // 1248 |
| 8539 | { PseudoVFCVT_F_XU_V_M4_E32_MASK, VFCVT_F_XU_V, 0x2, 0x20 }, // 1249 |
| 8540 | { PseudoVFCVT_RM_F_XU_V_M4_E32, VFCVT_F_XU_V, 0x2, 0x20 }, // 1250 |
| 8541 | { PseudoVFCVT_RM_F_XU_V_M4_E32_MASK, VFCVT_F_XU_V, 0x2, 0x20 }, // 1251 |
| 8542 | { PseudoVFCVT_F_XU_V_M4_E64, VFCVT_F_XU_V, 0x2, 0x40 }, // 1252 |
| 8543 | { PseudoVFCVT_F_XU_V_M4_E64_MASK, VFCVT_F_XU_V, 0x2, 0x40 }, // 1253 |
| 8544 | { PseudoVFCVT_RM_F_XU_V_M4_E64, VFCVT_F_XU_V, 0x2, 0x40 }, // 1254 |
| 8545 | { PseudoVFCVT_RM_F_XU_V_M4_E64_MASK, VFCVT_F_XU_V, 0x2, 0x40 }, // 1255 |
| 8546 | { PseudoVFCVT_F_XU_V_M8_E16, VFCVT_F_XU_V, 0x3, 0x10 }, // 1256 |
| 8547 | { PseudoVFCVT_F_XU_V_M8_E16_MASK, VFCVT_F_XU_V, 0x3, 0x10 }, // 1257 |
| 8548 | { PseudoVFCVT_RM_F_XU_V_M8_E16, VFCVT_F_XU_V, 0x3, 0x10 }, // 1258 |
| 8549 | { PseudoVFCVT_RM_F_XU_V_M8_E16_MASK, VFCVT_F_XU_V, 0x3, 0x10 }, // 1259 |
| 8550 | { PseudoVFCVT_F_XU_V_M8_E32, VFCVT_F_XU_V, 0x3, 0x20 }, // 1260 |
| 8551 | { PseudoVFCVT_F_XU_V_M8_E32_MASK, VFCVT_F_XU_V, 0x3, 0x20 }, // 1261 |
| 8552 | { PseudoVFCVT_RM_F_XU_V_M8_E32, VFCVT_F_XU_V, 0x3, 0x20 }, // 1262 |
| 8553 | { PseudoVFCVT_RM_F_XU_V_M8_E32_MASK, VFCVT_F_XU_V, 0x3, 0x20 }, // 1263 |
| 8554 | { PseudoVFCVT_F_XU_V_M8_E64, VFCVT_F_XU_V, 0x3, 0x40 }, // 1264 |
| 8555 | { PseudoVFCVT_F_XU_V_M8_E64_MASK, VFCVT_F_XU_V, 0x3, 0x40 }, // 1265 |
| 8556 | { PseudoVFCVT_RM_F_XU_V_M8_E64, VFCVT_F_XU_V, 0x3, 0x40 }, // 1266 |
| 8557 | { PseudoVFCVT_RM_F_XU_V_M8_E64_MASK, VFCVT_F_XU_V, 0x3, 0x40 }, // 1267 |
| 8558 | { PseudoVFCVT_F_XU_V_MF4_E16, VFCVT_F_XU_V, 0x6, 0x10 }, // 1268 |
| 8559 | { PseudoVFCVT_F_XU_V_MF4_E16_MASK, VFCVT_F_XU_V, 0x6, 0x10 }, // 1269 |
| 8560 | { PseudoVFCVT_RM_F_XU_V_MF4_E16, VFCVT_F_XU_V, 0x6, 0x10 }, // 1270 |
| 8561 | { PseudoVFCVT_RM_F_XU_V_MF4_E16_MASK, VFCVT_F_XU_V, 0x6, 0x10 }, // 1271 |
| 8562 | { PseudoVFCVT_F_XU_V_MF2_E16, VFCVT_F_XU_V, 0x7, 0x10 }, // 1272 |
| 8563 | { PseudoVFCVT_F_XU_V_MF2_E16_MASK, VFCVT_F_XU_V, 0x7, 0x10 }, // 1273 |
| 8564 | { PseudoVFCVT_RM_F_XU_V_MF2_E16, VFCVT_F_XU_V, 0x7, 0x10 }, // 1274 |
| 8565 | { PseudoVFCVT_RM_F_XU_V_MF2_E16_MASK, VFCVT_F_XU_V, 0x7, 0x10 }, // 1275 |
| 8566 | { PseudoVFCVT_F_XU_V_MF2_E32, VFCVT_F_XU_V, 0x7, 0x20 }, // 1276 |
| 8567 | { PseudoVFCVT_F_XU_V_MF2_E32_MASK, VFCVT_F_XU_V, 0x7, 0x20 }, // 1277 |
| 8568 | { PseudoVFCVT_RM_F_XU_V_MF2_E32, VFCVT_F_XU_V, 0x7, 0x20 }, // 1278 |
| 8569 | { PseudoVFCVT_RM_F_XU_V_MF2_E32_MASK, VFCVT_F_XU_V, 0x7, 0x20 }, // 1279 |
| 8570 | { PseudoVFCVT_F_X_V_M1_E16, VFCVT_F_X_V, 0x0, 0x10 }, // 1280 |
| 8571 | { PseudoVFCVT_F_X_V_M1_E16_MASK, VFCVT_F_X_V, 0x0, 0x10 }, // 1281 |
| 8572 | { PseudoVFCVT_RM_F_X_V_M1_E16, VFCVT_F_X_V, 0x0, 0x10 }, // 1282 |
| 8573 | { PseudoVFCVT_RM_F_X_V_M1_E16_MASK, VFCVT_F_X_V, 0x0, 0x10 }, // 1283 |
| 8574 | { PseudoVFCVT_F_X_V_M1_E32, VFCVT_F_X_V, 0x0, 0x20 }, // 1284 |
| 8575 | { PseudoVFCVT_F_X_V_M1_E32_MASK, VFCVT_F_X_V, 0x0, 0x20 }, // 1285 |
| 8576 | { PseudoVFCVT_RM_F_X_V_M1_E32, VFCVT_F_X_V, 0x0, 0x20 }, // 1286 |
| 8577 | { PseudoVFCVT_RM_F_X_V_M1_E32_MASK, VFCVT_F_X_V, 0x0, 0x20 }, // 1287 |
| 8578 | { PseudoVFCVT_F_X_V_M1_E64, VFCVT_F_X_V, 0x0, 0x40 }, // 1288 |
| 8579 | { PseudoVFCVT_F_X_V_M1_E64_MASK, VFCVT_F_X_V, 0x0, 0x40 }, // 1289 |
| 8580 | { PseudoVFCVT_RM_F_X_V_M1_E64, VFCVT_F_X_V, 0x0, 0x40 }, // 1290 |
| 8581 | { PseudoVFCVT_RM_F_X_V_M1_E64_MASK, VFCVT_F_X_V, 0x0, 0x40 }, // 1291 |
| 8582 | { PseudoVFCVT_F_X_V_M2_E16, VFCVT_F_X_V, 0x1, 0x10 }, // 1292 |
| 8583 | { PseudoVFCVT_F_X_V_M2_E16_MASK, VFCVT_F_X_V, 0x1, 0x10 }, // 1293 |
| 8584 | { PseudoVFCVT_RM_F_X_V_M2_E16, VFCVT_F_X_V, 0x1, 0x10 }, // 1294 |
| 8585 | { PseudoVFCVT_RM_F_X_V_M2_E16_MASK, VFCVT_F_X_V, 0x1, 0x10 }, // 1295 |
| 8586 | { PseudoVFCVT_F_X_V_M2_E32, VFCVT_F_X_V, 0x1, 0x20 }, // 1296 |
| 8587 | { PseudoVFCVT_F_X_V_M2_E32_MASK, VFCVT_F_X_V, 0x1, 0x20 }, // 1297 |
| 8588 | { PseudoVFCVT_RM_F_X_V_M2_E32, VFCVT_F_X_V, 0x1, 0x20 }, // 1298 |
| 8589 | { PseudoVFCVT_RM_F_X_V_M2_E32_MASK, VFCVT_F_X_V, 0x1, 0x20 }, // 1299 |
| 8590 | { PseudoVFCVT_F_X_V_M2_E64, VFCVT_F_X_V, 0x1, 0x40 }, // 1300 |
| 8591 | { PseudoVFCVT_F_X_V_M2_E64_MASK, VFCVT_F_X_V, 0x1, 0x40 }, // 1301 |
| 8592 | { PseudoVFCVT_RM_F_X_V_M2_E64, VFCVT_F_X_V, 0x1, 0x40 }, // 1302 |
| 8593 | { PseudoVFCVT_RM_F_X_V_M2_E64_MASK, VFCVT_F_X_V, 0x1, 0x40 }, // 1303 |
| 8594 | { PseudoVFCVT_F_X_V_M4_E16, VFCVT_F_X_V, 0x2, 0x10 }, // 1304 |
| 8595 | { PseudoVFCVT_F_X_V_M4_E16_MASK, VFCVT_F_X_V, 0x2, 0x10 }, // 1305 |
| 8596 | { PseudoVFCVT_RM_F_X_V_M4_E16, VFCVT_F_X_V, 0x2, 0x10 }, // 1306 |
| 8597 | { PseudoVFCVT_RM_F_X_V_M4_E16_MASK, VFCVT_F_X_V, 0x2, 0x10 }, // 1307 |
| 8598 | { PseudoVFCVT_F_X_V_M4_E32, VFCVT_F_X_V, 0x2, 0x20 }, // 1308 |
| 8599 | { PseudoVFCVT_F_X_V_M4_E32_MASK, VFCVT_F_X_V, 0x2, 0x20 }, // 1309 |
| 8600 | { PseudoVFCVT_RM_F_X_V_M4_E32, VFCVT_F_X_V, 0x2, 0x20 }, // 1310 |
| 8601 | { PseudoVFCVT_RM_F_X_V_M4_E32_MASK, VFCVT_F_X_V, 0x2, 0x20 }, // 1311 |
| 8602 | { PseudoVFCVT_F_X_V_M4_E64, VFCVT_F_X_V, 0x2, 0x40 }, // 1312 |
| 8603 | { PseudoVFCVT_F_X_V_M4_E64_MASK, VFCVT_F_X_V, 0x2, 0x40 }, // 1313 |
| 8604 | { PseudoVFCVT_RM_F_X_V_M4_E64, VFCVT_F_X_V, 0x2, 0x40 }, // 1314 |
| 8605 | { PseudoVFCVT_RM_F_X_V_M4_E64_MASK, VFCVT_F_X_V, 0x2, 0x40 }, // 1315 |
| 8606 | { PseudoVFCVT_F_X_V_M8_E16, VFCVT_F_X_V, 0x3, 0x10 }, // 1316 |
| 8607 | { PseudoVFCVT_F_X_V_M8_E16_MASK, VFCVT_F_X_V, 0x3, 0x10 }, // 1317 |
| 8608 | { PseudoVFCVT_RM_F_X_V_M8_E16, VFCVT_F_X_V, 0x3, 0x10 }, // 1318 |
| 8609 | { PseudoVFCVT_RM_F_X_V_M8_E16_MASK, VFCVT_F_X_V, 0x3, 0x10 }, // 1319 |
| 8610 | { PseudoVFCVT_F_X_V_M8_E32, VFCVT_F_X_V, 0x3, 0x20 }, // 1320 |
| 8611 | { PseudoVFCVT_F_X_V_M8_E32_MASK, VFCVT_F_X_V, 0x3, 0x20 }, // 1321 |
| 8612 | { PseudoVFCVT_RM_F_X_V_M8_E32, VFCVT_F_X_V, 0x3, 0x20 }, // 1322 |
| 8613 | { PseudoVFCVT_RM_F_X_V_M8_E32_MASK, VFCVT_F_X_V, 0x3, 0x20 }, // 1323 |
| 8614 | { PseudoVFCVT_F_X_V_M8_E64, VFCVT_F_X_V, 0x3, 0x40 }, // 1324 |
| 8615 | { PseudoVFCVT_F_X_V_M8_E64_MASK, VFCVT_F_X_V, 0x3, 0x40 }, // 1325 |
| 8616 | { PseudoVFCVT_RM_F_X_V_M8_E64, VFCVT_F_X_V, 0x3, 0x40 }, // 1326 |
| 8617 | { PseudoVFCVT_RM_F_X_V_M8_E64_MASK, VFCVT_F_X_V, 0x3, 0x40 }, // 1327 |
| 8618 | { PseudoVFCVT_F_X_V_MF4_E16, VFCVT_F_X_V, 0x6, 0x10 }, // 1328 |
| 8619 | { PseudoVFCVT_F_X_V_MF4_E16_MASK, VFCVT_F_X_V, 0x6, 0x10 }, // 1329 |
| 8620 | { PseudoVFCVT_RM_F_X_V_MF4_E16, VFCVT_F_X_V, 0x6, 0x10 }, // 1330 |
| 8621 | { PseudoVFCVT_RM_F_X_V_MF4_E16_MASK, VFCVT_F_X_V, 0x6, 0x10 }, // 1331 |
| 8622 | { PseudoVFCVT_F_X_V_MF2_E16, VFCVT_F_X_V, 0x7, 0x10 }, // 1332 |
| 8623 | { PseudoVFCVT_F_X_V_MF2_E16_MASK, VFCVT_F_X_V, 0x7, 0x10 }, // 1333 |
| 8624 | { PseudoVFCVT_RM_F_X_V_MF2_E16, VFCVT_F_X_V, 0x7, 0x10 }, // 1334 |
| 8625 | { PseudoVFCVT_RM_F_X_V_MF2_E16_MASK, VFCVT_F_X_V, 0x7, 0x10 }, // 1335 |
| 8626 | { PseudoVFCVT_F_X_V_MF2_E32, VFCVT_F_X_V, 0x7, 0x20 }, // 1336 |
| 8627 | { PseudoVFCVT_F_X_V_MF2_E32_MASK, VFCVT_F_X_V, 0x7, 0x20 }, // 1337 |
| 8628 | { PseudoVFCVT_RM_F_X_V_MF2_E32, VFCVT_F_X_V, 0x7, 0x20 }, // 1338 |
| 8629 | { PseudoVFCVT_RM_F_X_V_MF2_E32_MASK, VFCVT_F_X_V, 0x7, 0x20 }, // 1339 |
| 8630 | { PseudoVFCVT_RTZ_XU_F_V_M1, VFCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 1340 |
| 8631 | { PseudoVFCVT_RTZ_XU_F_V_M1_MASK, VFCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 1341 |
| 8632 | { PseudoVFCVT_RTZ_XU_F_V_M2, VFCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 1342 |
| 8633 | { PseudoVFCVT_RTZ_XU_F_V_M2_MASK, VFCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 1343 |
| 8634 | { PseudoVFCVT_RTZ_XU_F_V_M4, VFCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 1344 |
| 8635 | { PseudoVFCVT_RTZ_XU_F_V_M4_MASK, VFCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 1345 |
| 8636 | { PseudoVFCVT_RTZ_XU_F_V_M8, VFCVT_RTZ_XU_F_V, 0x3, 0x0 }, // 1346 |
| 8637 | { PseudoVFCVT_RTZ_XU_F_V_M8_MASK, VFCVT_RTZ_XU_F_V, 0x3, 0x0 }, // 1347 |
| 8638 | { PseudoVFCVT_RTZ_XU_F_V_MF4, VFCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 1348 |
| 8639 | { PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, VFCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 1349 |
| 8640 | { PseudoVFCVT_RTZ_XU_F_V_MF2, VFCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 1350 |
| 8641 | { PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, VFCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 1351 |
| 8642 | { PseudoVFCVT_RTZ_X_F_V_M1, VFCVT_RTZ_X_F_V, 0x0, 0x0 }, // 1352 |
| 8643 | { PseudoVFCVT_RTZ_X_F_V_M1_MASK, VFCVT_RTZ_X_F_V, 0x0, 0x0 }, // 1353 |
| 8644 | { PseudoVFCVT_RTZ_X_F_V_M2, VFCVT_RTZ_X_F_V, 0x1, 0x0 }, // 1354 |
| 8645 | { PseudoVFCVT_RTZ_X_F_V_M2_MASK, VFCVT_RTZ_X_F_V, 0x1, 0x0 }, // 1355 |
| 8646 | { PseudoVFCVT_RTZ_X_F_V_M4, VFCVT_RTZ_X_F_V, 0x2, 0x0 }, // 1356 |
| 8647 | { PseudoVFCVT_RTZ_X_F_V_M4_MASK, VFCVT_RTZ_X_F_V, 0x2, 0x0 }, // 1357 |
| 8648 | { PseudoVFCVT_RTZ_X_F_V_M8, VFCVT_RTZ_X_F_V, 0x3, 0x0 }, // 1358 |
| 8649 | { PseudoVFCVT_RTZ_X_F_V_M8_MASK, VFCVT_RTZ_X_F_V, 0x3, 0x0 }, // 1359 |
| 8650 | { PseudoVFCVT_RTZ_X_F_V_MF4, VFCVT_RTZ_X_F_V, 0x6, 0x0 }, // 1360 |
| 8651 | { PseudoVFCVT_RTZ_X_F_V_MF4_MASK, VFCVT_RTZ_X_F_V, 0x6, 0x0 }, // 1361 |
| 8652 | { PseudoVFCVT_RTZ_X_F_V_MF2, VFCVT_RTZ_X_F_V, 0x7, 0x0 }, // 1362 |
| 8653 | { PseudoVFCVT_RTZ_X_F_V_MF2_MASK, VFCVT_RTZ_X_F_V, 0x7, 0x0 }, // 1363 |
| 8654 | { PseudoVFCVT_RM_XU_F_V_M1, VFCVT_XU_F_V, 0x0, 0x0 }, // 1364 |
| 8655 | { PseudoVFCVT_RM_XU_F_V_M1_MASK, VFCVT_XU_F_V, 0x0, 0x0 }, // 1365 |
| 8656 | { PseudoVFCVT_XU_F_V_M1, VFCVT_XU_F_V, 0x0, 0x0 }, // 1366 |
| 8657 | { PseudoVFCVT_XU_F_V_M1_MASK, VFCVT_XU_F_V, 0x0, 0x0 }, // 1367 |
| 8658 | { PseudoVFCVT_RM_XU_F_V_M2, VFCVT_XU_F_V, 0x1, 0x0 }, // 1368 |
| 8659 | { PseudoVFCVT_RM_XU_F_V_M2_MASK, VFCVT_XU_F_V, 0x1, 0x0 }, // 1369 |
| 8660 | { PseudoVFCVT_XU_F_V_M2, VFCVT_XU_F_V, 0x1, 0x0 }, // 1370 |
| 8661 | { PseudoVFCVT_XU_F_V_M2_MASK, VFCVT_XU_F_V, 0x1, 0x0 }, // 1371 |
| 8662 | { PseudoVFCVT_RM_XU_F_V_M4, VFCVT_XU_F_V, 0x2, 0x0 }, // 1372 |
| 8663 | { PseudoVFCVT_RM_XU_F_V_M4_MASK, VFCVT_XU_F_V, 0x2, 0x0 }, // 1373 |
| 8664 | { PseudoVFCVT_XU_F_V_M4, VFCVT_XU_F_V, 0x2, 0x0 }, // 1374 |
| 8665 | { PseudoVFCVT_XU_F_V_M4_MASK, VFCVT_XU_F_V, 0x2, 0x0 }, // 1375 |
| 8666 | { PseudoVFCVT_RM_XU_F_V_M8, VFCVT_XU_F_V, 0x3, 0x0 }, // 1376 |
| 8667 | { PseudoVFCVT_RM_XU_F_V_M8_MASK, VFCVT_XU_F_V, 0x3, 0x0 }, // 1377 |
| 8668 | { PseudoVFCVT_XU_F_V_M8, VFCVT_XU_F_V, 0x3, 0x0 }, // 1378 |
| 8669 | { PseudoVFCVT_XU_F_V_M8_MASK, VFCVT_XU_F_V, 0x3, 0x0 }, // 1379 |
| 8670 | { PseudoVFCVT_RM_XU_F_V_MF4, VFCVT_XU_F_V, 0x6, 0x0 }, // 1380 |
| 8671 | { PseudoVFCVT_RM_XU_F_V_MF4_MASK, VFCVT_XU_F_V, 0x6, 0x0 }, // 1381 |
| 8672 | { PseudoVFCVT_XU_F_V_MF4, VFCVT_XU_F_V, 0x6, 0x0 }, // 1382 |
| 8673 | { PseudoVFCVT_XU_F_V_MF4_MASK, VFCVT_XU_F_V, 0x6, 0x0 }, // 1383 |
| 8674 | { PseudoVFCVT_RM_XU_F_V_MF2, VFCVT_XU_F_V, 0x7, 0x0 }, // 1384 |
| 8675 | { PseudoVFCVT_RM_XU_F_V_MF2_MASK, VFCVT_XU_F_V, 0x7, 0x0 }, // 1385 |
| 8676 | { PseudoVFCVT_XU_F_V_MF2, VFCVT_XU_F_V, 0x7, 0x0 }, // 1386 |
| 8677 | { PseudoVFCVT_XU_F_V_MF2_MASK, VFCVT_XU_F_V, 0x7, 0x0 }, // 1387 |
| 8678 | { PseudoVFCVT_RM_X_F_V_M1, VFCVT_X_F_V, 0x0, 0x0 }, // 1388 |
| 8679 | { PseudoVFCVT_RM_X_F_V_M1_MASK, VFCVT_X_F_V, 0x0, 0x0 }, // 1389 |
| 8680 | { PseudoVFCVT_X_F_V_M1, VFCVT_X_F_V, 0x0, 0x0 }, // 1390 |
| 8681 | { PseudoVFCVT_X_F_V_M1_MASK, VFCVT_X_F_V, 0x0, 0x0 }, // 1391 |
| 8682 | { PseudoVFCVT_RM_X_F_V_M2, VFCVT_X_F_V, 0x1, 0x0 }, // 1392 |
| 8683 | { PseudoVFCVT_RM_X_F_V_M2_MASK, VFCVT_X_F_V, 0x1, 0x0 }, // 1393 |
| 8684 | { PseudoVFCVT_X_F_V_M2, VFCVT_X_F_V, 0x1, 0x0 }, // 1394 |
| 8685 | { PseudoVFCVT_X_F_V_M2_MASK, VFCVT_X_F_V, 0x1, 0x0 }, // 1395 |
| 8686 | { PseudoVFCVT_RM_X_F_V_M4, VFCVT_X_F_V, 0x2, 0x0 }, // 1396 |
| 8687 | { PseudoVFCVT_RM_X_F_V_M4_MASK, VFCVT_X_F_V, 0x2, 0x0 }, // 1397 |
| 8688 | { PseudoVFCVT_X_F_V_M4, VFCVT_X_F_V, 0x2, 0x0 }, // 1398 |
| 8689 | { PseudoVFCVT_X_F_V_M4_MASK, VFCVT_X_F_V, 0x2, 0x0 }, // 1399 |
| 8690 | { PseudoVFCVT_RM_X_F_V_M8, VFCVT_X_F_V, 0x3, 0x0 }, // 1400 |
| 8691 | { PseudoVFCVT_RM_X_F_V_M8_MASK, VFCVT_X_F_V, 0x3, 0x0 }, // 1401 |
| 8692 | { PseudoVFCVT_X_F_V_M8, VFCVT_X_F_V, 0x3, 0x0 }, // 1402 |
| 8693 | { PseudoVFCVT_X_F_V_M8_MASK, VFCVT_X_F_V, 0x3, 0x0 }, // 1403 |
| 8694 | { PseudoVFCVT_RM_X_F_V_MF4, VFCVT_X_F_V, 0x6, 0x0 }, // 1404 |
| 8695 | { PseudoVFCVT_RM_X_F_V_MF4_MASK, VFCVT_X_F_V, 0x6, 0x0 }, // 1405 |
| 8696 | { PseudoVFCVT_X_F_V_MF4, VFCVT_X_F_V, 0x6, 0x0 }, // 1406 |
| 8697 | { PseudoVFCVT_X_F_V_MF4_MASK, VFCVT_X_F_V, 0x6, 0x0 }, // 1407 |
| 8698 | { PseudoVFCVT_RM_X_F_V_MF2, VFCVT_X_F_V, 0x7, 0x0 }, // 1408 |
| 8699 | { PseudoVFCVT_RM_X_F_V_MF2_MASK, VFCVT_X_F_V, 0x7, 0x0 }, // 1409 |
| 8700 | { PseudoVFCVT_X_F_V_MF2, VFCVT_X_F_V, 0x7, 0x0 }, // 1410 |
| 8701 | { PseudoVFCVT_X_F_V_MF2_MASK, VFCVT_X_F_V, 0x7, 0x0 }, // 1411 |
| 8702 | { PseudoVFDIV_VFPR16_M1_E16, VFDIV_VF, 0x0, 0x10 }, // 1412 |
| 8703 | { PseudoVFDIV_VFPR16_M1_E16_MASK, VFDIV_VF, 0x0, 0x10 }, // 1413 |
| 8704 | { PseudoVFDIV_VFPR32_M1_E32, VFDIV_VF, 0x0, 0x20 }, // 1414 |
| 8705 | { PseudoVFDIV_VFPR32_M1_E32_MASK, VFDIV_VF, 0x0, 0x20 }, // 1415 |
| 8706 | { PseudoVFDIV_VFPR64_M1_E64, VFDIV_VF, 0x0, 0x40 }, // 1416 |
| 8707 | { PseudoVFDIV_VFPR64_M1_E64_MASK, VFDIV_VF, 0x0, 0x40 }, // 1417 |
| 8708 | { PseudoVFDIV_VFPR16_M2_E16, VFDIV_VF, 0x1, 0x10 }, // 1418 |
| 8709 | { PseudoVFDIV_VFPR16_M2_E16_MASK, VFDIV_VF, 0x1, 0x10 }, // 1419 |
| 8710 | { PseudoVFDIV_VFPR32_M2_E32, VFDIV_VF, 0x1, 0x20 }, // 1420 |
| 8711 | { PseudoVFDIV_VFPR32_M2_E32_MASK, VFDIV_VF, 0x1, 0x20 }, // 1421 |
| 8712 | { PseudoVFDIV_VFPR64_M2_E64, VFDIV_VF, 0x1, 0x40 }, // 1422 |
| 8713 | { PseudoVFDIV_VFPR64_M2_E64_MASK, VFDIV_VF, 0x1, 0x40 }, // 1423 |
| 8714 | { PseudoVFDIV_VFPR16_M4_E16, VFDIV_VF, 0x2, 0x10 }, // 1424 |
| 8715 | { PseudoVFDIV_VFPR16_M4_E16_MASK, VFDIV_VF, 0x2, 0x10 }, // 1425 |
| 8716 | { PseudoVFDIV_VFPR32_M4_E32, VFDIV_VF, 0x2, 0x20 }, // 1426 |
| 8717 | { PseudoVFDIV_VFPR32_M4_E32_MASK, VFDIV_VF, 0x2, 0x20 }, // 1427 |
| 8718 | { PseudoVFDIV_VFPR64_M4_E64, VFDIV_VF, 0x2, 0x40 }, // 1428 |
| 8719 | { PseudoVFDIV_VFPR64_M4_E64_MASK, VFDIV_VF, 0x2, 0x40 }, // 1429 |
| 8720 | { PseudoVFDIV_VFPR16_M8_E16, VFDIV_VF, 0x3, 0x10 }, // 1430 |
| 8721 | { PseudoVFDIV_VFPR16_M8_E16_MASK, VFDIV_VF, 0x3, 0x10 }, // 1431 |
| 8722 | { PseudoVFDIV_VFPR32_M8_E32, VFDIV_VF, 0x3, 0x20 }, // 1432 |
| 8723 | { PseudoVFDIV_VFPR32_M8_E32_MASK, VFDIV_VF, 0x3, 0x20 }, // 1433 |
| 8724 | { PseudoVFDIV_VFPR64_M8_E64, VFDIV_VF, 0x3, 0x40 }, // 1434 |
| 8725 | { PseudoVFDIV_VFPR64_M8_E64_MASK, VFDIV_VF, 0x3, 0x40 }, // 1435 |
| 8726 | { PseudoVFDIV_VFPR16_MF4_E16, VFDIV_VF, 0x6, 0x10 }, // 1436 |
| 8727 | { PseudoVFDIV_VFPR16_MF4_E16_MASK, VFDIV_VF, 0x6, 0x10 }, // 1437 |
| 8728 | { PseudoVFDIV_VFPR16_MF2_E16, VFDIV_VF, 0x7, 0x10 }, // 1438 |
| 8729 | { PseudoVFDIV_VFPR16_MF2_E16_MASK, VFDIV_VF, 0x7, 0x10 }, // 1439 |
| 8730 | { PseudoVFDIV_VFPR32_MF2_E32, VFDIV_VF, 0x7, 0x20 }, // 1440 |
| 8731 | { PseudoVFDIV_VFPR32_MF2_E32_MASK, VFDIV_VF, 0x7, 0x20 }, // 1441 |
| 8732 | { PseudoVFDIV_VV_M1_E16, VFDIV_VV, 0x0, 0x10 }, // 1442 |
| 8733 | { PseudoVFDIV_VV_M1_E16_MASK, VFDIV_VV, 0x0, 0x10 }, // 1443 |
| 8734 | { PseudoVFDIV_VV_M1_E32, VFDIV_VV, 0x0, 0x20 }, // 1444 |
| 8735 | { PseudoVFDIV_VV_M1_E32_MASK, VFDIV_VV, 0x0, 0x20 }, // 1445 |
| 8736 | { PseudoVFDIV_VV_M1_E64, VFDIV_VV, 0x0, 0x40 }, // 1446 |
| 8737 | { PseudoVFDIV_VV_M1_E64_MASK, VFDIV_VV, 0x0, 0x40 }, // 1447 |
| 8738 | { PseudoVFDIV_VV_M2_E16, VFDIV_VV, 0x1, 0x10 }, // 1448 |
| 8739 | { PseudoVFDIV_VV_M2_E16_MASK, VFDIV_VV, 0x1, 0x10 }, // 1449 |
| 8740 | { PseudoVFDIV_VV_M2_E32, VFDIV_VV, 0x1, 0x20 }, // 1450 |
| 8741 | { PseudoVFDIV_VV_M2_E32_MASK, VFDIV_VV, 0x1, 0x20 }, // 1451 |
| 8742 | { PseudoVFDIV_VV_M2_E64, VFDIV_VV, 0x1, 0x40 }, // 1452 |
| 8743 | { PseudoVFDIV_VV_M2_E64_MASK, VFDIV_VV, 0x1, 0x40 }, // 1453 |
| 8744 | { PseudoVFDIV_VV_M4_E16, VFDIV_VV, 0x2, 0x10 }, // 1454 |
| 8745 | { PseudoVFDIV_VV_M4_E16_MASK, VFDIV_VV, 0x2, 0x10 }, // 1455 |
| 8746 | { PseudoVFDIV_VV_M4_E32, VFDIV_VV, 0x2, 0x20 }, // 1456 |
| 8747 | { PseudoVFDIV_VV_M4_E32_MASK, VFDIV_VV, 0x2, 0x20 }, // 1457 |
| 8748 | { PseudoVFDIV_VV_M4_E64, VFDIV_VV, 0x2, 0x40 }, // 1458 |
| 8749 | { PseudoVFDIV_VV_M4_E64_MASK, VFDIV_VV, 0x2, 0x40 }, // 1459 |
| 8750 | { PseudoVFDIV_VV_M8_E16, VFDIV_VV, 0x3, 0x10 }, // 1460 |
| 8751 | { PseudoVFDIV_VV_M8_E16_MASK, VFDIV_VV, 0x3, 0x10 }, // 1461 |
| 8752 | { PseudoVFDIV_VV_M8_E32, VFDIV_VV, 0x3, 0x20 }, // 1462 |
| 8753 | { PseudoVFDIV_VV_M8_E32_MASK, VFDIV_VV, 0x3, 0x20 }, // 1463 |
| 8754 | { PseudoVFDIV_VV_M8_E64, VFDIV_VV, 0x3, 0x40 }, // 1464 |
| 8755 | { PseudoVFDIV_VV_M8_E64_MASK, VFDIV_VV, 0x3, 0x40 }, // 1465 |
| 8756 | { PseudoVFDIV_VV_MF4_E16, VFDIV_VV, 0x6, 0x10 }, // 1466 |
| 8757 | { PseudoVFDIV_VV_MF4_E16_MASK, VFDIV_VV, 0x6, 0x10 }, // 1467 |
| 8758 | { PseudoVFDIV_VV_MF2_E16, VFDIV_VV, 0x7, 0x10 }, // 1468 |
| 8759 | { PseudoVFDIV_VV_MF2_E16_MASK, VFDIV_VV, 0x7, 0x10 }, // 1469 |
| 8760 | { PseudoVFDIV_VV_MF2_E32, VFDIV_VV, 0x7, 0x20 }, // 1470 |
| 8761 | { PseudoVFDIV_VV_MF2_E32_MASK, VFDIV_VV, 0x7, 0x20 }, // 1471 |
| 8762 | { PseudoVFIRST_M_B8, VFIRST_M, 0x0, 0x0 }, // 1472 |
| 8763 | { PseudoVFIRST_M_B8_MASK, VFIRST_M, 0x0, 0x0 }, // 1473 |
| 8764 | { PseudoVFIRST_M_B16, VFIRST_M, 0x1, 0x0 }, // 1474 |
| 8765 | { PseudoVFIRST_M_B16_MASK, VFIRST_M, 0x1, 0x0 }, // 1475 |
| 8766 | { PseudoVFIRST_M_B32, VFIRST_M, 0x2, 0x0 }, // 1476 |
| 8767 | { PseudoVFIRST_M_B32_MASK, VFIRST_M, 0x2, 0x0 }, // 1477 |
| 8768 | { PseudoVFIRST_M_B64, VFIRST_M, 0x3, 0x0 }, // 1478 |
| 8769 | { PseudoVFIRST_M_B64_MASK, VFIRST_M, 0x3, 0x0 }, // 1479 |
| 8770 | { PseudoVFIRST_M_B1, VFIRST_M, 0x5, 0x0 }, // 1480 |
| 8771 | { PseudoVFIRST_M_B1_MASK, VFIRST_M, 0x5, 0x0 }, // 1481 |
| 8772 | { PseudoVFIRST_M_B2, VFIRST_M, 0x6, 0x0 }, // 1482 |
| 8773 | { PseudoVFIRST_M_B2_MASK, VFIRST_M, 0x6, 0x0 }, // 1483 |
| 8774 | { PseudoVFIRST_M_B4, VFIRST_M, 0x7, 0x0 }, // 1484 |
| 8775 | { PseudoVFIRST_M_B4_MASK, VFIRST_M, 0x7, 0x0 }, // 1485 |
| 8776 | { PseudoVFMACC_VFPR16_M1_E16, VFMACC_VF, 0x0, 0x0 }, // 1486 |
| 8777 | { PseudoVFMACC_VFPR16_M1_E16_MASK, VFMACC_VF, 0x0, 0x0 }, // 1487 |
| 8778 | { PseudoVFMACC_VFPR32_M1_E32, VFMACC_VF, 0x0, 0x0 }, // 1488 |
| 8779 | { PseudoVFMACC_VFPR32_M1_E32_MASK, VFMACC_VF, 0x0, 0x0 }, // 1489 |
| 8780 | { PseudoVFMACC_VFPR64_M1_E64, VFMACC_VF, 0x0, 0x0 }, // 1490 |
| 8781 | { PseudoVFMACC_VFPR64_M1_E64_MASK, VFMACC_VF, 0x0, 0x0 }, // 1491 |
| 8782 | { PseudoVFMACC_VFPR16_M2_E16, VFMACC_VF, 0x1, 0x0 }, // 1492 |
| 8783 | { PseudoVFMACC_VFPR16_M2_E16_MASK, VFMACC_VF, 0x1, 0x0 }, // 1493 |
| 8784 | { PseudoVFMACC_VFPR32_M2_E32, VFMACC_VF, 0x1, 0x0 }, // 1494 |
| 8785 | { PseudoVFMACC_VFPR32_M2_E32_MASK, VFMACC_VF, 0x1, 0x0 }, // 1495 |
| 8786 | { PseudoVFMACC_VFPR64_M2_E64, VFMACC_VF, 0x1, 0x0 }, // 1496 |
| 8787 | { PseudoVFMACC_VFPR64_M2_E64_MASK, VFMACC_VF, 0x1, 0x0 }, // 1497 |
| 8788 | { PseudoVFMACC_VFPR16_M4_E16, VFMACC_VF, 0x2, 0x0 }, // 1498 |
| 8789 | { PseudoVFMACC_VFPR16_M4_E16_MASK, VFMACC_VF, 0x2, 0x0 }, // 1499 |
| 8790 | { PseudoVFMACC_VFPR32_M4_E32, VFMACC_VF, 0x2, 0x0 }, // 1500 |
| 8791 | { PseudoVFMACC_VFPR32_M4_E32_MASK, VFMACC_VF, 0x2, 0x0 }, // 1501 |
| 8792 | { PseudoVFMACC_VFPR64_M4_E64, VFMACC_VF, 0x2, 0x0 }, // 1502 |
| 8793 | { PseudoVFMACC_VFPR64_M4_E64_MASK, VFMACC_VF, 0x2, 0x0 }, // 1503 |
| 8794 | { PseudoVFMACC_VFPR16_M8_E16, VFMACC_VF, 0x3, 0x0 }, // 1504 |
| 8795 | { PseudoVFMACC_VFPR16_M8_E16_MASK, VFMACC_VF, 0x3, 0x0 }, // 1505 |
| 8796 | { PseudoVFMACC_VFPR32_M8_E32, VFMACC_VF, 0x3, 0x0 }, // 1506 |
| 8797 | { PseudoVFMACC_VFPR32_M8_E32_MASK, VFMACC_VF, 0x3, 0x0 }, // 1507 |
| 8798 | { PseudoVFMACC_VFPR64_M8_E64, VFMACC_VF, 0x3, 0x0 }, // 1508 |
| 8799 | { PseudoVFMACC_VFPR64_M8_E64_MASK, VFMACC_VF, 0x3, 0x0 }, // 1509 |
| 8800 | { PseudoVFMACC_VFPR16_MF4_E16, VFMACC_VF, 0x6, 0x0 }, // 1510 |
| 8801 | { PseudoVFMACC_VFPR16_MF4_E16_MASK, VFMACC_VF, 0x6, 0x0 }, // 1511 |
| 8802 | { PseudoVFMACC_VFPR16_MF2_E16, VFMACC_VF, 0x7, 0x0 }, // 1512 |
| 8803 | { PseudoVFMACC_VFPR16_MF2_E16_MASK, VFMACC_VF, 0x7, 0x0 }, // 1513 |
| 8804 | { PseudoVFMACC_VFPR32_MF2_E32, VFMACC_VF, 0x7, 0x0 }, // 1514 |
| 8805 | { PseudoVFMACC_VFPR32_MF2_E32_MASK, VFMACC_VF, 0x7, 0x0 }, // 1515 |
| 8806 | { PseudoVFMACC_VV_M1_E16, VFMACC_VV, 0x0, 0x0 }, // 1516 |
| 8807 | { PseudoVFMACC_VV_M1_E16_MASK, VFMACC_VV, 0x0, 0x0 }, // 1517 |
| 8808 | { PseudoVFMACC_VV_M1_E32, VFMACC_VV, 0x0, 0x0 }, // 1518 |
| 8809 | { PseudoVFMACC_VV_M1_E32_MASK, VFMACC_VV, 0x0, 0x0 }, // 1519 |
| 8810 | { PseudoVFMACC_VV_M1_E64, VFMACC_VV, 0x0, 0x0 }, // 1520 |
| 8811 | { PseudoVFMACC_VV_M1_E64_MASK, VFMACC_VV, 0x0, 0x0 }, // 1521 |
| 8812 | { PseudoVFMACC_VV_M2_E16, VFMACC_VV, 0x1, 0x0 }, // 1522 |
| 8813 | { PseudoVFMACC_VV_M2_E16_MASK, VFMACC_VV, 0x1, 0x0 }, // 1523 |
| 8814 | { PseudoVFMACC_VV_M2_E32, VFMACC_VV, 0x1, 0x0 }, // 1524 |
| 8815 | { PseudoVFMACC_VV_M2_E32_MASK, VFMACC_VV, 0x1, 0x0 }, // 1525 |
| 8816 | { PseudoVFMACC_VV_M2_E64, VFMACC_VV, 0x1, 0x0 }, // 1526 |
| 8817 | { PseudoVFMACC_VV_M2_E64_MASK, VFMACC_VV, 0x1, 0x0 }, // 1527 |
| 8818 | { PseudoVFMACC_VV_M4_E16, VFMACC_VV, 0x2, 0x0 }, // 1528 |
| 8819 | { PseudoVFMACC_VV_M4_E16_MASK, VFMACC_VV, 0x2, 0x0 }, // 1529 |
| 8820 | { PseudoVFMACC_VV_M4_E32, VFMACC_VV, 0x2, 0x0 }, // 1530 |
| 8821 | { PseudoVFMACC_VV_M4_E32_MASK, VFMACC_VV, 0x2, 0x0 }, // 1531 |
| 8822 | { PseudoVFMACC_VV_M4_E64, VFMACC_VV, 0x2, 0x0 }, // 1532 |
| 8823 | { PseudoVFMACC_VV_M4_E64_MASK, VFMACC_VV, 0x2, 0x0 }, // 1533 |
| 8824 | { PseudoVFMACC_VV_M8_E16, VFMACC_VV, 0x3, 0x0 }, // 1534 |
| 8825 | { PseudoVFMACC_VV_M8_E16_MASK, VFMACC_VV, 0x3, 0x0 }, // 1535 |
| 8826 | { PseudoVFMACC_VV_M8_E32, VFMACC_VV, 0x3, 0x0 }, // 1536 |
| 8827 | { PseudoVFMACC_VV_M8_E32_MASK, VFMACC_VV, 0x3, 0x0 }, // 1537 |
| 8828 | { PseudoVFMACC_VV_M8_E64, VFMACC_VV, 0x3, 0x0 }, // 1538 |
| 8829 | { PseudoVFMACC_VV_M8_E64_MASK, VFMACC_VV, 0x3, 0x0 }, // 1539 |
| 8830 | { PseudoVFMACC_VV_MF4_E16, VFMACC_VV, 0x6, 0x0 }, // 1540 |
| 8831 | { PseudoVFMACC_VV_MF4_E16_MASK, VFMACC_VV, 0x6, 0x0 }, // 1541 |
| 8832 | { PseudoVFMACC_VV_MF2_E16, VFMACC_VV, 0x7, 0x0 }, // 1542 |
| 8833 | { PseudoVFMACC_VV_MF2_E16_MASK, VFMACC_VV, 0x7, 0x0 }, // 1543 |
| 8834 | { PseudoVFMACC_VV_MF2_E32, VFMACC_VV, 0x7, 0x0 }, // 1544 |
| 8835 | { PseudoVFMACC_VV_MF2_E32_MASK, VFMACC_VV, 0x7, 0x0 }, // 1545 |
| 8836 | { PseudoVFMADD_VFPR16_M1_E16, VFMADD_VF, 0x0, 0x0 }, // 1546 |
| 8837 | { PseudoVFMADD_VFPR16_M1_E16_MASK, VFMADD_VF, 0x0, 0x0 }, // 1547 |
| 8838 | { PseudoVFMADD_VFPR32_M1_E32, VFMADD_VF, 0x0, 0x0 }, // 1548 |
| 8839 | { PseudoVFMADD_VFPR32_M1_E32_MASK, VFMADD_VF, 0x0, 0x0 }, // 1549 |
| 8840 | { PseudoVFMADD_VFPR64_M1_E64, VFMADD_VF, 0x0, 0x0 }, // 1550 |
| 8841 | { PseudoVFMADD_VFPR64_M1_E64_MASK, VFMADD_VF, 0x0, 0x0 }, // 1551 |
| 8842 | { PseudoVFMADD_VFPR16_M2_E16, VFMADD_VF, 0x1, 0x0 }, // 1552 |
| 8843 | { PseudoVFMADD_VFPR16_M2_E16_MASK, VFMADD_VF, 0x1, 0x0 }, // 1553 |
| 8844 | { PseudoVFMADD_VFPR32_M2_E32, VFMADD_VF, 0x1, 0x0 }, // 1554 |
| 8845 | { PseudoVFMADD_VFPR32_M2_E32_MASK, VFMADD_VF, 0x1, 0x0 }, // 1555 |
| 8846 | { PseudoVFMADD_VFPR64_M2_E64, VFMADD_VF, 0x1, 0x0 }, // 1556 |
| 8847 | { PseudoVFMADD_VFPR64_M2_E64_MASK, VFMADD_VF, 0x1, 0x0 }, // 1557 |
| 8848 | { PseudoVFMADD_VFPR16_M4_E16, VFMADD_VF, 0x2, 0x0 }, // 1558 |
| 8849 | { PseudoVFMADD_VFPR16_M4_E16_MASK, VFMADD_VF, 0x2, 0x0 }, // 1559 |
| 8850 | { PseudoVFMADD_VFPR32_M4_E32, VFMADD_VF, 0x2, 0x0 }, // 1560 |
| 8851 | { PseudoVFMADD_VFPR32_M4_E32_MASK, VFMADD_VF, 0x2, 0x0 }, // 1561 |
| 8852 | { PseudoVFMADD_VFPR64_M4_E64, VFMADD_VF, 0x2, 0x0 }, // 1562 |
| 8853 | { PseudoVFMADD_VFPR64_M4_E64_MASK, VFMADD_VF, 0x2, 0x0 }, // 1563 |
| 8854 | { PseudoVFMADD_VFPR16_M8_E16, VFMADD_VF, 0x3, 0x0 }, // 1564 |
| 8855 | { PseudoVFMADD_VFPR16_M8_E16_MASK, VFMADD_VF, 0x3, 0x0 }, // 1565 |
| 8856 | { PseudoVFMADD_VFPR32_M8_E32, VFMADD_VF, 0x3, 0x0 }, // 1566 |
| 8857 | { PseudoVFMADD_VFPR32_M8_E32_MASK, VFMADD_VF, 0x3, 0x0 }, // 1567 |
| 8858 | { PseudoVFMADD_VFPR64_M8_E64, VFMADD_VF, 0x3, 0x0 }, // 1568 |
| 8859 | { PseudoVFMADD_VFPR64_M8_E64_MASK, VFMADD_VF, 0x3, 0x0 }, // 1569 |
| 8860 | { PseudoVFMADD_VFPR16_MF4_E16, VFMADD_VF, 0x6, 0x0 }, // 1570 |
| 8861 | { PseudoVFMADD_VFPR16_MF4_E16_MASK, VFMADD_VF, 0x6, 0x0 }, // 1571 |
| 8862 | { PseudoVFMADD_VFPR16_MF2_E16, VFMADD_VF, 0x7, 0x0 }, // 1572 |
| 8863 | { PseudoVFMADD_VFPR16_MF2_E16_MASK, VFMADD_VF, 0x7, 0x0 }, // 1573 |
| 8864 | { PseudoVFMADD_VFPR32_MF2_E32, VFMADD_VF, 0x7, 0x0 }, // 1574 |
| 8865 | { PseudoVFMADD_VFPR32_MF2_E32_MASK, VFMADD_VF, 0x7, 0x0 }, // 1575 |
| 8866 | { PseudoVFMADD_VV_M1_E16, VFMADD_VV, 0x0, 0x0 }, // 1576 |
| 8867 | { PseudoVFMADD_VV_M1_E16_MASK, VFMADD_VV, 0x0, 0x0 }, // 1577 |
| 8868 | { PseudoVFMADD_VV_M1_E32, VFMADD_VV, 0x0, 0x0 }, // 1578 |
| 8869 | { PseudoVFMADD_VV_M1_E32_MASK, VFMADD_VV, 0x0, 0x0 }, // 1579 |
| 8870 | { PseudoVFMADD_VV_M1_E64, VFMADD_VV, 0x0, 0x0 }, // 1580 |
| 8871 | { PseudoVFMADD_VV_M1_E64_MASK, VFMADD_VV, 0x0, 0x0 }, // 1581 |
| 8872 | { PseudoVFMADD_VV_M2_E16, VFMADD_VV, 0x1, 0x0 }, // 1582 |
| 8873 | { PseudoVFMADD_VV_M2_E16_MASK, VFMADD_VV, 0x1, 0x0 }, // 1583 |
| 8874 | { PseudoVFMADD_VV_M2_E32, VFMADD_VV, 0x1, 0x0 }, // 1584 |
| 8875 | { PseudoVFMADD_VV_M2_E32_MASK, VFMADD_VV, 0x1, 0x0 }, // 1585 |
| 8876 | { PseudoVFMADD_VV_M2_E64, VFMADD_VV, 0x1, 0x0 }, // 1586 |
| 8877 | { PseudoVFMADD_VV_M2_E64_MASK, VFMADD_VV, 0x1, 0x0 }, // 1587 |
| 8878 | { PseudoVFMADD_VV_M4_E16, VFMADD_VV, 0x2, 0x0 }, // 1588 |
| 8879 | { PseudoVFMADD_VV_M4_E16_MASK, VFMADD_VV, 0x2, 0x0 }, // 1589 |
| 8880 | { PseudoVFMADD_VV_M4_E32, VFMADD_VV, 0x2, 0x0 }, // 1590 |
| 8881 | { PseudoVFMADD_VV_M4_E32_MASK, VFMADD_VV, 0x2, 0x0 }, // 1591 |
| 8882 | { PseudoVFMADD_VV_M4_E64, VFMADD_VV, 0x2, 0x0 }, // 1592 |
| 8883 | { PseudoVFMADD_VV_M4_E64_MASK, VFMADD_VV, 0x2, 0x0 }, // 1593 |
| 8884 | { PseudoVFMADD_VV_M8_E16, VFMADD_VV, 0x3, 0x0 }, // 1594 |
| 8885 | { PseudoVFMADD_VV_M8_E16_MASK, VFMADD_VV, 0x3, 0x0 }, // 1595 |
| 8886 | { PseudoVFMADD_VV_M8_E32, VFMADD_VV, 0x3, 0x0 }, // 1596 |
| 8887 | { PseudoVFMADD_VV_M8_E32_MASK, VFMADD_VV, 0x3, 0x0 }, // 1597 |
| 8888 | { PseudoVFMADD_VV_M8_E64, VFMADD_VV, 0x3, 0x0 }, // 1598 |
| 8889 | { PseudoVFMADD_VV_M8_E64_MASK, VFMADD_VV, 0x3, 0x0 }, // 1599 |
| 8890 | { PseudoVFMADD_VV_MF4_E16, VFMADD_VV, 0x6, 0x0 }, // 1600 |
| 8891 | { PseudoVFMADD_VV_MF4_E16_MASK, VFMADD_VV, 0x6, 0x0 }, // 1601 |
| 8892 | { PseudoVFMADD_VV_MF2_E16, VFMADD_VV, 0x7, 0x0 }, // 1602 |
| 8893 | { PseudoVFMADD_VV_MF2_E16_MASK, VFMADD_VV, 0x7, 0x0 }, // 1603 |
| 8894 | { PseudoVFMADD_VV_MF2_E32, VFMADD_VV, 0x7, 0x0 }, // 1604 |
| 8895 | { PseudoVFMADD_VV_MF2_E32_MASK, VFMADD_VV, 0x7, 0x0 }, // 1605 |
| 8896 | { PseudoVFMAX_VFPR16_M1_E16, VFMAX_VF, 0x0, 0x10 }, // 1606 |
| 8897 | { PseudoVFMAX_VFPR16_M1_E16_MASK, VFMAX_VF, 0x0, 0x10 }, // 1607 |
| 8898 | { PseudoVFMAX_VFPR32_M1_E32, VFMAX_VF, 0x0, 0x20 }, // 1608 |
| 8899 | { PseudoVFMAX_VFPR32_M1_E32_MASK, VFMAX_VF, 0x0, 0x20 }, // 1609 |
| 8900 | { PseudoVFMAX_VFPR64_M1_E64, VFMAX_VF, 0x0, 0x40 }, // 1610 |
| 8901 | { PseudoVFMAX_VFPR64_M1_E64_MASK, VFMAX_VF, 0x0, 0x40 }, // 1611 |
| 8902 | { PseudoVFMAX_VFPR16_M2_E16, VFMAX_VF, 0x1, 0x10 }, // 1612 |
| 8903 | { PseudoVFMAX_VFPR16_M2_E16_MASK, VFMAX_VF, 0x1, 0x10 }, // 1613 |
| 8904 | { PseudoVFMAX_VFPR32_M2_E32, VFMAX_VF, 0x1, 0x20 }, // 1614 |
| 8905 | { PseudoVFMAX_VFPR32_M2_E32_MASK, VFMAX_VF, 0x1, 0x20 }, // 1615 |
| 8906 | { PseudoVFMAX_VFPR64_M2_E64, VFMAX_VF, 0x1, 0x40 }, // 1616 |
| 8907 | { PseudoVFMAX_VFPR64_M2_E64_MASK, VFMAX_VF, 0x1, 0x40 }, // 1617 |
| 8908 | { PseudoVFMAX_VFPR16_M4_E16, VFMAX_VF, 0x2, 0x10 }, // 1618 |
| 8909 | { PseudoVFMAX_VFPR16_M4_E16_MASK, VFMAX_VF, 0x2, 0x10 }, // 1619 |
| 8910 | { PseudoVFMAX_VFPR32_M4_E32, VFMAX_VF, 0x2, 0x20 }, // 1620 |
| 8911 | { PseudoVFMAX_VFPR32_M4_E32_MASK, VFMAX_VF, 0x2, 0x20 }, // 1621 |
| 8912 | { PseudoVFMAX_VFPR64_M4_E64, VFMAX_VF, 0x2, 0x40 }, // 1622 |
| 8913 | { PseudoVFMAX_VFPR64_M4_E64_MASK, VFMAX_VF, 0x2, 0x40 }, // 1623 |
| 8914 | { PseudoVFMAX_VFPR16_M8_E16, VFMAX_VF, 0x3, 0x10 }, // 1624 |
| 8915 | { PseudoVFMAX_VFPR16_M8_E16_MASK, VFMAX_VF, 0x3, 0x10 }, // 1625 |
| 8916 | { PseudoVFMAX_VFPR32_M8_E32, VFMAX_VF, 0x3, 0x20 }, // 1626 |
| 8917 | { PseudoVFMAX_VFPR32_M8_E32_MASK, VFMAX_VF, 0x3, 0x20 }, // 1627 |
| 8918 | { PseudoVFMAX_VFPR64_M8_E64, VFMAX_VF, 0x3, 0x40 }, // 1628 |
| 8919 | { PseudoVFMAX_VFPR64_M8_E64_MASK, VFMAX_VF, 0x3, 0x40 }, // 1629 |
| 8920 | { PseudoVFMAX_VFPR16_MF4_E16, VFMAX_VF, 0x6, 0x10 }, // 1630 |
| 8921 | { PseudoVFMAX_VFPR16_MF4_E16_MASK, VFMAX_VF, 0x6, 0x10 }, // 1631 |
| 8922 | { PseudoVFMAX_VFPR16_MF2_E16, VFMAX_VF, 0x7, 0x10 }, // 1632 |
| 8923 | { PseudoVFMAX_VFPR16_MF2_E16_MASK, VFMAX_VF, 0x7, 0x10 }, // 1633 |
| 8924 | { PseudoVFMAX_VFPR32_MF2_E32, VFMAX_VF, 0x7, 0x20 }, // 1634 |
| 8925 | { PseudoVFMAX_VFPR32_MF2_E32_MASK, VFMAX_VF, 0x7, 0x20 }, // 1635 |
| 8926 | { PseudoVFMAX_VV_M1_E16, VFMAX_VV, 0x0, 0x10 }, // 1636 |
| 8927 | { PseudoVFMAX_VV_M1_E16_MASK, VFMAX_VV, 0x0, 0x10 }, // 1637 |
| 8928 | { PseudoVFMAX_VV_M1_E32, VFMAX_VV, 0x0, 0x20 }, // 1638 |
| 8929 | { PseudoVFMAX_VV_M1_E32_MASK, VFMAX_VV, 0x0, 0x20 }, // 1639 |
| 8930 | { PseudoVFMAX_VV_M1_E64, VFMAX_VV, 0x0, 0x40 }, // 1640 |
| 8931 | { PseudoVFMAX_VV_M1_E64_MASK, VFMAX_VV, 0x0, 0x40 }, // 1641 |
| 8932 | { PseudoVFMAX_VV_M2_E16, VFMAX_VV, 0x1, 0x10 }, // 1642 |
| 8933 | { PseudoVFMAX_VV_M2_E16_MASK, VFMAX_VV, 0x1, 0x10 }, // 1643 |
| 8934 | { PseudoVFMAX_VV_M2_E32, VFMAX_VV, 0x1, 0x20 }, // 1644 |
| 8935 | { PseudoVFMAX_VV_M2_E32_MASK, VFMAX_VV, 0x1, 0x20 }, // 1645 |
| 8936 | { PseudoVFMAX_VV_M2_E64, VFMAX_VV, 0x1, 0x40 }, // 1646 |
| 8937 | { PseudoVFMAX_VV_M2_E64_MASK, VFMAX_VV, 0x1, 0x40 }, // 1647 |
| 8938 | { PseudoVFMAX_VV_M4_E16, VFMAX_VV, 0x2, 0x10 }, // 1648 |
| 8939 | { PseudoVFMAX_VV_M4_E16_MASK, VFMAX_VV, 0x2, 0x10 }, // 1649 |
| 8940 | { PseudoVFMAX_VV_M4_E32, VFMAX_VV, 0x2, 0x20 }, // 1650 |
| 8941 | { PseudoVFMAX_VV_M4_E32_MASK, VFMAX_VV, 0x2, 0x20 }, // 1651 |
| 8942 | { PseudoVFMAX_VV_M4_E64, VFMAX_VV, 0x2, 0x40 }, // 1652 |
| 8943 | { PseudoVFMAX_VV_M4_E64_MASK, VFMAX_VV, 0x2, 0x40 }, // 1653 |
| 8944 | { PseudoVFMAX_VV_M8_E16, VFMAX_VV, 0x3, 0x10 }, // 1654 |
| 8945 | { PseudoVFMAX_VV_M8_E16_MASK, VFMAX_VV, 0x3, 0x10 }, // 1655 |
| 8946 | { PseudoVFMAX_VV_M8_E32, VFMAX_VV, 0x3, 0x20 }, // 1656 |
| 8947 | { PseudoVFMAX_VV_M8_E32_MASK, VFMAX_VV, 0x3, 0x20 }, // 1657 |
| 8948 | { PseudoVFMAX_VV_M8_E64, VFMAX_VV, 0x3, 0x40 }, // 1658 |
| 8949 | { PseudoVFMAX_VV_M8_E64_MASK, VFMAX_VV, 0x3, 0x40 }, // 1659 |
| 8950 | { PseudoVFMAX_VV_MF4_E16, VFMAX_VV, 0x6, 0x10 }, // 1660 |
| 8951 | { PseudoVFMAX_VV_MF4_E16_MASK, VFMAX_VV, 0x6, 0x10 }, // 1661 |
| 8952 | { PseudoVFMAX_VV_MF2_E16, VFMAX_VV, 0x7, 0x10 }, // 1662 |
| 8953 | { PseudoVFMAX_VV_MF2_E16_MASK, VFMAX_VV, 0x7, 0x10 }, // 1663 |
| 8954 | { PseudoVFMAX_VV_MF2_E32, VFMAX_VV, 0x7, 0x20 }, // 1664 |
| 8955 | { PseudoVFMAX_VV_MF2_E32_MASK, VFMAX_VV, 0x7, 0x20 }, // 1665 |
| 8956 | { PseudoVFMERGE_VFPR16M_M1, VFMERGE_VFM, 0x0, 0x0 }, // 1666 |
| 8957 | { PseudoVFMERGE_VFPR32M_M1, VFMERGE_VFM, 0x0, 0x0 }, // 1667 |
| 8958 | { PseudoVFMERGE_VFPR64M_M1, VFMERGE_VFM, 0x0, 0x0 }, // 1668 |
| 8959 | { PseudoVFMERGE_VFPR16M_M2, VFMERGE_VFM, 0x1, 0x0 }, // 1669 |
| 8960 | { PseudoVFMERGE_VFPR32M_M2, VFMERGE_VFM, 0x1, 0x0 }, // 1670 |
| 8961 | { PseudoVFMERGE_VFPR64M_M2, VFMERGE_VFM, 0x1, 0x0 }, // 1671 |
| 8962 | { PseudoVFMERGE_VFPR16M_M4, VFMERGE_VFM, 0x2, 0x0 }, // 1672 |
| 8963 | { PseudoVFMERGE_VFPR32M_M4, VFMERGE_VFM, 0x2, 0x0 }, // 1673 |
| 8964 | { PseudoVFMERGE_VFPR64M_M4, VFMERGE_VFM, 0x2, 0x0 }, // 1674 |
| 8965 | { PseudoVFMERGE_VFPR16M_M8, VFMERGE_VFM, 0x3, 0x0 }, // 1675 |
| 8966 | { PseudoVFMERGE_VFPR32M_M8, VFMERGE_VFM, 0x3, 0x0 }, // 1676 |
| 8967 | { PseudoVFMERGE_VFPR64M_M8, VFMERGE_VFM, 0x3, 0x0 }, // 1677 |
| 8968 | { PseudoVFMERGE_VFPR16M_MF4, VFMERGE_VFM, 0x6, 0x0 }, // 1678 |
| 8969 | { PseudoVFMERGE_VFPR16M_MF2, VFMERGE_VFM, 0x7, 0x0 }, // 1679 |
| 8970 | { PseudoVFMERGE_VFPR32M_MF2, VFMERGE_VFM, 0x7, 0x0 }, // 1680 |
| 8971 | { PseudoVFMIN_VFPR16_M1_E16, VFMIN_VF, 0x0, 0x10 }, // 1681 |
| 8972 | { PseudoVFMIN_VFPR16_M1_E16_MASK, VFMIN_VF, 0x0, 0x10 }, // 1682 |
| 8973 | { PseudoVFMIN_VFPR32_M1_E32, VFMIN_VF, 0x0, 0x20 }, // 1683 |
| 8974 | { PseudoVFMIN_VFPR32_M1_E32_MASK, VFMIN_VF, 0x0, 0x20 }, // 1684 |
| 8975 | { PseudoVFMIN_VFPR64_M1_E64, VFMIN_VF, 0x0, 0x40 }, // 1685 |
| 8976 | { PseudoVFMIN_VFPR64_M1_E64_MASK, VFMIN_VF, 0x0, 0x40 }, // 1686 |
| 8977 | { PseudoVFMIN_VFPR16_M2_E16, VFMIN_VF, 0x1, 0x10 }, // 1687 |
| 8978 | { PseudoVFMIN_VFPR16_M2_E16_MASK, VFMIN_VF, 0x1, 0x10 }, // 1688 |
| 8979 | { PseudoVFMIN_VFPR32_M2_E32, VFMIN_VF, 0x1, 0x20 }, // 1689 |
| 8980 | { PseudoVFMIN_VFPR32_M2_E32_MASK, VFMIN_VF, 0x1, 0x20 }, // 1690 |
| 8981 | { PseudoVFMIN_VFPR64_M2_E64, VFMIN_VF, 0x1, 0x40 }, // 1691 |
| 8982 | { PseudoVFMIN_VFPR64_M2_E64_MASK, VFMIN_VF, 0x1, 0x40 }, // 1692 |
| 8983 | { PseudoVFMIN_VFPR16_M4_E16, VFMIN_VF, 0x2, 0x10 }, // 1693 |
| 8984 | { PseudoVFMIN_VFPR16_M4_E16_MASK, VFMIN_VF, 0x2, 0x10 }, // 1694 |
| 8985 | { PseudoVFMIN_VFPR32_M4_E32, VFMIN_VF, 0x2, 0x20 }, // 1695 |
| 8986 | { PseudoVFMIN_VFPR32_M4_E32_MASK, VFMIN_VF, 0x2, 0x20 }, // 1696 |
| 8987 | { PseudoVFMIN_VFPR64_M4_E64, VFMIN_VF, 0x2, 0x40 }, // 1697 |
| 8988 | { PseudoVFMIN_VFPR64_M4_E64_MASK, VFMIN_VF, 0x2, 0x40 }, // 1698 |
| 8989 | { PseudoVFMIN_VFPR16_M8_E16, VFMIN_VF, 0x3, 0x10 }, // 1699 |
| 8990 | { PseudoVFMIN_VFPR16_M8_E16_MASK, VFMIN_VF, 0x3, 0x10 }, // 1700 |
| 8991 | { PseudoVFMIN_VFPR32_M8_E32, VFMIN_VF, 0x3, 0x20 }, // 1701 |
| 8992 | { PseudoVFMIN_VFPR32_M8_E32_MASK, VFMIN_VF, 0x3, 0x20 }, // 1702 |
| 8993 | { PseudoVFMIN_VFPR64_M8_E64, VFMIN_VF, 0x3, 0x40 }, // 1703 |
| 8994 | { PseudoVFMIN_VFPR64_M8_E64_MASK, VFMIN_VF, 0x3, 0x40 }, // 1704 |
| 8995 | { PseudoVFMIN_VFPR16_MF4_E16, VFMIN_VF, 0x6, 0x10 }, // 1705 |
| 8996 | { PseudoVFMIN_VFPR16_MF4_E16_MASK, VFMIN_VF, 0x6, 0x10 }, // 1706 |
| 8997 | { PseudoVFMIN_VFPR16_MF2_E16, VFMIN_VF, 0x7, 0x10 }, // 1707 |
| 8998 | { PseudoVFMIN_VFPR16_MF2_E16_MASK, VFMIN_VF, 0x7, 0x10 }, // 1708 |
| 8999 | { PseudoVFMIN_VFPR32_MF2_E32, VFMIN_VF, 0x7, 0x20 }, // 1709 |
| 9000 | { PseudoVFMIN_VFPR32_MF2_E32_MASK, VFMIN_VF, 0x7, 0x20 }, // 1710 |
| 9001 | { PseudoVFMIN_VV_M1_E16, VFMIN_VV, 0x0, 0x10 }, // 1711 |
| 9002 | { PseudoVFMIN_VV_M1_E16_MASK, VFMIN_VV, 0x0, 0x10 }, // 1712 |
| 9003 | { PseudoVFMIN_VV_M1_E32, VFMIN_VV, 0x0, 0x20 }, // 1713 |
| 9004 | { PseudoVFMIN_VV_M1_E32_MASK, VFMIN_VV, 0x0, 0x20 }, // 1714 |
| 9005 | { PseudoVFMIN_VV_M1_E64, VFMIN_VV, 0x0, 0x40 }, // 1715 |
| 9006 | { PseudoVFMIN_VV_M1_E64_MASK, VFMIN_VV, 0x0, 0x40 }, // 1716 |
| 9007 | { PseudoVFMIN_VV_M2_E16, VFMIN_VV, 0x1, 0x10 }, // 1717 |
| 9008 | { PseudoVFMIN_VV_M2_E16_MASK, VFMIN_VV, 0x1, 0x10 }, // 1718 |
| 9009 | { PseudoVFMIN_VV_M2_E32, VFMIN_VV, 0x1, 0x20 }, // 1719 |
| 9010 | { PseudoVFMIN_VV_M2_E32_MASK, VFMIN_VV, 0x1, 0x20 }, // 1720 |
| 9011 | { PseudoVFMIN_VV_M2_E64, VFMIN_VV, 0x1, 0x40 }, // 1721 |
| 9012 | { PseudoVFMIN_VV_M2_E64_MASK, VFMIN_VV, 0x1, 0x40 }, // 1722 |
| 9013 | { PseudoVFMIN_VV_M4_E16, VFMIN_VV, 0x2, 0x10 }, // 1723 |
| 9014 | { PseudoVFMIN_VV_M4_E16_MASK, VFMIN_VV, 0x2, 0x10 }, // 1724 |
| 9015 | { PseudoVFMIN_VV_M4_E32, VFMIN_VV, 0x2, 0x20 }, // 1725 |
| 9016 | { PseudoVFMIN_VV_M4_E32_MASK, VFMIN_VV, 0x2, 0x20 }, // 1726 |
| 9017 | { PseudoVFMIN_VV_M4_E64, VFMIN_VV, 0x2, 0x40 }, // 1727 |
| 9018 | { PseudoVFMIN_VV_M4_E64_MASK, VFMIN_VV, 0x2, 0x40 }, // 1728 |
| 9019 | { PseudoVFMIN_VV_M8_E16, VFMIN_VV, 0x3, 0x10 }, // 1729 |
| 9020 | { PseudoVFMIN_VV_M8_E16_MASK, VFMIN_VV, 0x3, 0x10 }, // 1730 |
| 9021 | { PseudoVFMIN_VV_M8_E32, VFMIN_VV, 0x3, 0x20 }, // 1731 |
| 9022 | { PseudoVFMIN_VV_M8_E32_MASK, VFMIN_VV, 0x3, 0x20 }, // 1732 |
| 9023 | { PseudoVFMIN_VV_M8_E64, VFMIN_VV, 0x3, 0x40 }, // 1733 |
| 9024 | { PseudoVFMIN_VV_M8_E64_MASK, VFMIN_VV, 0x3, 0x40 }, // 1734 |
| 9025 | { PseudoVFMIN_VV_MF4_E16, VFMIN_VV, 0x6, 0x10 }, // 1735 |
| 9026 | { PseudoVFMIN_VV_MF4_E16_MASK, VFMIN_VV, 0x6, 0x10 }, // 1736 |
| 9027 | { PseudoVFMIN_VV_MF2_E16, VFMIN_VV, 0x7, 0x10 }, // 1737 |
| 9028 | { PseudoVFMIN_VV_MF2_E16_MASK, VFMIN_VV, 0x7, 0x10 }, // 1738 |
| 9029 | { PseudoVFMIN_VV_MF2_E32, VFMIN_VV, 0x7, 0x20 }, // 1739 |
| 9030 | { PseudoVFMIN_VV_MF2_E32_MASK, VFMIN_VV, 0x7, 0x20 }, // 1740 |
| 9031 | { PseudoVFMSAC_VFPR16_M1_E16, VFMSAC_VF, 0x0, 0x0 }, // 1741 |
| 9032 | { PseudoVFMSAC_VFPR16_M1_E16_MASK, VFMSAC_VF, 0x0, 0x0 }, // 1742 |
| 9033 | { PseudoVFMSAC_VFPR32_M1_E32, VFMSAC_VF, 0x0, 0x0 }, // 1743 |
| 9034 | { PseudoVFMSAC_VFPR32_M1_E32_MASK, VFMSAC_VF, 0x0, 0x0 }, // 1744 |
| 9035 | { PseudoVFMSAC_VFPR64_M1_E64, VFMSAC_VF, 0x0, 0x0 }, // 1745 |
| 9036 | { PseudoVFMSAC_VFPR64_M1_E64_MASK, VFMSAC_VF, 0x0, 0x0 }, // 1746 |
| 9037 | { PseudoVFMSAC_VFPR16_M2_E16, VFMSAC_VF, 0x1, 0x0 }, // 1747 |
| 9038 | { PseudoVFMSAC_VFPR16_M2_E16_MASK, VFMSAC_VF, 0x1, 0x0 }, // 1748 |
| 9039 | { PseudoVFMSAC_VFPR32_M2_E32, VFMSAC_VF, 0x1, 0x0 }, // 1749 |
| 9040 | { PseudoVFMSAC_VFPR32_M2_E32_MASK, VFMSAC_VF, 0x1, 0x0 }, // 1750 |
| 9041 | { PseudoVFMSAC_VFPR64_M2_E64, VFMSAC_VF, 0x1, 0x0 }, // 1751 |
| 9042 | { PseudoVFMSAC_VFPR64_M2_E64_MASK, VFMSAC_VF, 0x1, 0x0 }, // 1752 |
| 9043 | { PseudoVFMSAC_VFPR16_M4_E16, VFMSAC_VF, 0x2, 0x0 }, // 1753 |
| 9044 | { PseudoVFMSAC_VFPR16_M4_E16_MASK, VFMSAC_VF, 0x2, 0x0 }, // 1754 |
| 9045 | { PseudoVFMSAC_VFPR32_M4_E32, VFMSAC_VF, 0x2, 0x0 }, // 1755 |
| 9046 | { PseudoVFMSAC_VFPR32_M4_E32_MASK, VFMSAC_VF, 0x2, 0x0 }, // 1756 |
| 9047 | { PseudoVFMSAC_VFPR64_M4_E64, VFMSAC_VF, 0x2, 0x0 }, // 1757 |
| 9048 | { PseudoVFMSAC_VFPR64_M4_E64_MASK, VFMSAC_VF, 0x2, 0x0 }, // 1758 |
| 9049 | { PseudoVFMSAC_VFPR16_M8_E16, VFMSAC_VF, 0x3, 0x0 }, // 1759 |
| 9050 | { PseudoVFMSAC_VFPR16_M8_E16_MASK, VFMSAC_VF, 0x3, 0x0 }, // 1760 |
| 9051 | { PseudoVFMSAC_VFPR32_M8_E32, VFMSAC_VF, 0x3, 0x0 }, // 1761 |
| 9052 | { PseudoVFMSAC_VFPR32_M8_E32_MASK, VFMSAC_VF, 0x3, 0x0 }, // 1762 |
| 9053 | { PseudoVFMSAC_VFPR64_M8_E64, VFMSAC_VF, 0x3, 0x0 }, // 1763 |
| 9054 | { PseudoVFMSAC_VFPR64_M8_E64_MASK, VFMSAC_VF, 0x3, 0x0 }, // 1764 |
| 9055 | { PseudoVFMSAC_VFPR16_MF4_E16, VFMSAC_VF, 0x6, 0x0 }, // 1765 |
| 9056 | { PseudoVFMSAC_VFPR16_MF4_E16_MASK, VFMSAC_VF, 0x6, 0x0 }, // 1766 |
| 9057 | { PseudoVFMSAC_VFPR16_MF2_E16, VFMSAC_VF, 0x7, 0x0 }, // 1767 |
| 9058 | { PseudoVFMSAC_VFPR16_MF2_E16_MASK, VFMSAC_VF, 0x7, 0x0 }, // 1768 |
| 9059 | { PseudoVFMSAC_VFPR32_MF2_E32, VFMSAC_VF, 0x7, 0x0 }, // 1769 |
| 9060 | { PseudoVFMSAC_VFPR32_MF2_E32_MASK, VFMSAC_VF, 0x7, 0x0 }, // 1770 |
| 9061 | { PseudoVFMSAC_VV_M1_E16, VFMSAC_VV, 0x0, 0x0 }, // 1771 |
| 9062 | { PseudoVFMSAC_VV_M1_E16_MASK, VFMSAC_VV, 0x0, 0x0 }, // 1772 |
| 9063 | { PseudoVFMSAC_VV_M1_E32, VFMSAC_VV, 0x0, 0x0 }, // 1773 |
| 9064 | { PseudoVFMSAC_VV_M1_E32_MASK, VFMSAC_VV, 0x0, 0x0 }, // 1774 |
| 9065 | { PseudoVFMSAC_VV_M1_E64, VFMSAC_VV, 0x0, 0x0 }, // 1775 |
| 9066 | { PseudoVFMSAC_VV_M1_E64_MASK, VFMSAC_VV, 0x0, 0x0 }, // 1776 |
| 9067 | { PseudoVFMSAC_VV_M2_E16, VFMSAC_VV, 0x1, 0x0 }, // 1777 |
| 9068 | { PseudoVFMSAC_VV_M2_E16_MASK, VFMSAC_VV, 0x1, 0x0 }, // 1778 |
| 9069 | { PseudoVFMSAC_VV_M2_E32, VFMSAC_VV, 0x1, 0x0 }, // 1779 |
| 9070 | { PseudoVFMSAC_VV_M2_E32_MASK, VFMSAC_VV, 0x1, 0x0 }, // 1780 |
| 9071 | { PseudoVFMSAC_VV_M2_E64, VFMSAC_VV, 0x1, 0x0 }, // 1781 |
| 9072 | { PseudoVFMSAC_VV_M2_E64_MASK, VFMSAC_VV, 0x1, 0x0 }, // 1782 |
| 9073 | { PseudoVFMSAC_VV_M4_E16, VFMSAC_VV, 0x2, 0x0 }, // 1783 |
| 9074 | { PseudoVFMSAC_VV_M4_E16_MASK, VFMSAC_VV, 0x2, 0x0 }, // 1784 |
| 9075 | { PseudoVFMSAC_VV_M4_E32, VFMSAC_VV, 0x2, 0x0 }, // 1785 |
| 9076 | { PseudoVFMSAC_VV_M4_E32_MASK, VFMSAC_VV, 0x2, 0x0 }, // 1786 |
| 9077 | { PseudoVFMSAC_VV_M4_E64, VFMSAC_VV, 0x2, 0x0 }, // 1787 |
| 9078 | { PseudoVFMSAC_VV_M4_E64_MASK, VFMSAC_VV, 0x2, 0x0 }, // 1788 |
| 9079 | { PseudoVFMSAC_VV_M8_E16, VFMSAC_VV, 0x3, 0x0 }, // 1789 |
| 9080 | { PseudoVFMSAC_VV_M8_E16_MASK, VFMSAC_VV, 0x3, 0x0 }, // 1790 |
| 9081 | { PseudoVFMSAC_VV_M8_E32, VFMSAC_VV, 0x3, 0x0 }, // 1791 |
| 9082 | { PseudoVFMSAC_VV_M8_E32_MASK, VFMSAC_VV, 0x3, 0x0 }, // 1792 |
| 9083 | { PseudoVFMSAC_VV_M8_E64, VFMSAC_VV, 0x3, 0x0 }, // 1793 |
| 9084 | { PseudoVFMSAC_VV_M8_E64_MASK, VFMSAC_VV, 0x3, 0x0 }, // 1794 |
| 9085 | { PseudoVFMSAC_VV_MF4_E16, VFMSAC_VV, 0x6, 0x0 }, // 1795 |
| 9086 | { PseudoVFMSAC_VV_MF4_E16_MASK, VFMSAC_VV, 0x6, 0x0 }, // 1796 |
| 9087 | { PseudoVFMSAC_VV_MF2_E16, VFMSAC_VV, 0x7, 0x0 }, // 1797 |
| 9088 | { PseudoVFMSAC_VV_MF2_E16_MASK, VFMSAC_VV, 0x7, 0x0 }, // 1798 |
| 9089 | { PseudoVFMSAC_VV_MF2_E32, VFMSAC_VV, 0x7, 0x0 }, // 1799 |
| 9090 | { PseudoVFMSAC_VV_MF2_E32_MASK, VFMSAC_VV, 0x7, 0x0 }, // 1800 |
| 9091 | { PseudoVFMSUB_VFPR16_M1_E16, VFMSUB_VF, 0x0, 0x0 }, // 1801 |
| 9092 | { PseudoVFMSUB_VFPR16_M1_E16_MASK, VFMSUB_VF, 0x0, 0x0 }, // 1802 |
| 9093 | { PseudoVFMSUB_VFPR32_M1_E32, VFMSUB_VF, 0x0, 0x0 }, // 1803 |
| 9094 | { PseudoVFMSUB_VFPR32_M1_E32_MASK, VFMSUB_VF, 0x0, 0x0 }, // 1804 |
| 9095 | { PseudoVFMSUB_VFPR64_M1_E64, VFMSUB_VF, 0x0, 0x0 }, // 1805 |
| 9096 | { PseudoVFMSUB_VFPR64_M1_E64_MASK, VFMSUB_VF, 0x0, 0x0 }, // 1806 |
| 9097 | { PseudoVFMSUB_VFPR16_M2_E16, VFMSUB_VF, 0x1, 0x0 }, // 1807 |
| 9098 | { PseudoVFMSUB_VFPR16_M2_E16_MASK, VFMSUB_VF, 0x1, 0x0 }, // 1808 |
| 9099 | { PseudoVFMSUB_VFPR32_M2_E32, VFMSUB_VF, 0x1, 0x0 }, // 1809 |
| 9100 | { PseudoVFMSUB_VFPR32_M2_E32_MASK, VFMSUB_VF, 0x1, 0x0 }, // 1810 |
| 9101 | { PseudoVFMSUB_VFPR64_M2_E64, VFMSUB_VF, 0x1, 0x0 }, // 1811 |
| 9102 | { PseudoVFMSUB_VFPR64_M2_E64_MASK, VFMSUB_VF, 0x1, 0x0 }, // 1812 |
| 9103 | { PseudoVFMSUB_VFPR16_M4_E16, VFMSUB_VF, 0x2, 0x0 }, // 1813 |
| 9104 | { PseudoVFMSUB_VFPR16_M4_E16_MASK, VFMSUB_VF, 0x2, 0x0 }, // 1814 |
| 9105 | { PseudoVFMSUB_VFPR32_M4_E32, VFMSUB_VF, 0x2, 0x0 }, // 1815 |
| 9106 | { PseudoVFMSUB_VFPR32_M4_E32_MASK, VFMSUB_VF, 0x2, 0x0 }, // 1816 |
| 9107 | { PseudoVFMSUB_VFPR64_M4_E64, VFMSUB_VF, 0x2, 0x0 }, // 1817 |
| 9108 | { PseudoVFMSUB_VFPR64_M4_E64_MASK, VFMSUB_VF, 0x2, 0x0 }, // 1818 |
| 9109 | { PseudoVFMSUB_VFPR16_M8_E16, VFMSUB_VF, 0x3, 0x0 }, // 1819 |
| 9110 | { PseudoVFMSUB_VFPR16_M8_E16_MASK, VFMSUB_VF, 0x3, 0x0 }, // 1820 |
| 9111 | { PseudoVFMSUB_VFPR32_M8_E32, VFMSUB_VF, 0x3, 0x0 }, // 1821 |
| 9112 | { PseudoVFMSUB_VFPR32_M8_E32_MASK, VFMSUB_VF, 0x3, 0x0 }, // 1822 |
| 9113 | { PseudoVFMSUB_VFPR64_M8_E64, VFMSUB_VF, 0x3, 0x0 }, // 1823 |
| 9114 | { PseudoVFMSUB_VFPR64_M8_E64_MASK, VFMSUB_VF, 0x3, 0x0 }, // 1824 |
| 9115 | { PseudoVFMSUB_VFPR16_MF4_E16, VFMSUB_VF, 0x6, 0x0 }, // 1825 |
| 9116 | { PseudoVFMSUB_VFPR16_MF4_E16_MASK, VFMSUB_VF, 0x6, 0x0 }, // 1826 |
| 9117 | { PseudoVFMSUB_VFPR16_MF2_E16, VFMSUB_VF, 0x7, 0x0 }, // 1827 |
| 9118 | { PseudoVFMSUB_VFPR16_MF2_E16_MASK, VFMSUB_VF, 0x7, 0x0 }, // 1828 |
| 9119 | { PseudoVFMSUB_VFPR32_MF2_E32, VFMSUB_VF, 0x7, 0x0 }, // 1829 |
| 9120 | { PseudoVFMSUB_VFPR32_MF2_E32_MASK, VFMSUB_VF, 0x7, 0x0 }, // 1830 |
| 9121 | { PseudoVFMSUB_VV_M1_E16, VFMSUB_VV, 0x0, 0x0 }, // 1831 |
| 9122 | { PseudoVFMSUB_VV_M1_E16_MASK, VFMSUB_VV, 0x0, 0x0 }, // 1832 |
| 9123 | { PseudoVFMSUB_VV_M1_E32, VFMSUB_VV, 0x0, 0x0 }, // 1833 |
| 9124 | { PseudoVFMSUB_VV_M1_E32_MASK, VFMSUB_VV, 0x0, 0x0 }, // 1834 |
| 9125 | { PseudoVFMSUB_VV_M1_E64, VFMSUB_VV, 0x0, 0x0 }, // 1835 |
| 9126 | { PseudoVFMSUB_VV_M1_E64_MASK, VFMSUB_VV, 0x0, 0x0 }, // 1836 |
| 9127 | { PseudoVFMSUB_VV_M2_E16, VFMSUB_VV, 0x1, 0x0 }, // 1837 |
| 9128 | { PseudoVFMSUB_VV_M2_E16_MASK, VFMSUB_VV, 0x1, 0x0 }, // 1838 |
| 9129 | { PseudoVFMSUB_VV_M2_E32, VFMSUB_VV, 0x1, 0x0 }, // 1839 |
| 9130 | { PseudoVFMSUB_VV_M2_E32_MASK, VFMSUB_VV, 0x1, 0x0 }, // 1840 |
| 9131 | { PseudoVFMSUB_VV_M2_E64, VFMSUB_VV, 0x1, 0x0 }, // 1841 |
| 9132 | { PseudoVFMSUB_VV_M2_E64_MASK, VFMSUB_VV, 0x1, 0x0 }, // 1842 |
| 9133 | { PseudoVFMSUB_VV_M4_E16, VFMSUB_VV, 0x2, 0x0 }, // 1843 |
| 9134 | { PseudoVFMSUB_VV_M4_E16_MASK, VFMSUB_VV, 0x2, 0x0 }, // 1844 |
| 9135 | { PseudoVFMSUB_VV_M4_E32, VFMSUB_VV, 0x2, 0x0 }, // 1845 |
| 9136 | { PseudoVFMSUB_VV_M4_E32_MASK, VFMSUB_VV, 0x2, 0x0 }, // 1846 |
| 9137 | { PseudoVFMSUB_VV_M4_E64, VFMSUB_VV, 0x2, 0x0 }, // 1847 |
| 9138 | { PseudoVFMSUB_VV_M4_E64_MASK, VFMSUB_VV, 0x2, 0x0 }, // 1848 |
| 9139 | { PseudoVFMSUB_VV_M8_E16, VFMSUB_VV, 0x3, 0x0 }, // 1849 |
| 9140 | { PseudoVFMSUB_VV_M8_E16_MASK, VFMSUB_VV, 0x3, 0x0 }, // 1850 |
| 9141 | { PseudoVFMSUB_VV_M8_E32, VFMSUB_VV, 0x3, 0x0 }, // 1851 |
| 9142 | { PseudoVFMSUB_VV_M8_E32_MASK, VFMSUB_VV, 0x3, 0x0 }, // 1852 |
| 9143 | { PseudoVFMSUB_VV_M8_E64, VFMSUB_VV, 0x3, 0x0 }, // 1853 |
| 9144 | { PseudoVFMSUB_VV_M8_E64_MASK, VFMSUB_VV, 0x3, 0x0 }, // 1854 |
| 9145 | { PseudoVFMSUB_VV_MF4_E16, VFMSUB_VV, 0x6, 0x0 }, // 1855 |
| 9146 | { PseudoVFMSUB_VV_MF4_E16_MASK, VFMSUB_VV, 0x6, 0x0 }, // 1856 |
| 9147 | { PseudoVFMSUB_VV_MF2_E16, VFMSUB_VV, 0x7, 0x0 }, // 1857 |
| 9148 | { PseudoVFMSUB_VV_MF2_E16_MASK, VFMSUB_VV, 0x7, 0x0 }, // 1858 |
| 9149 | { PseudoVFMSUB_VV_MF2_E32, VFMSUB_VV, 0x7, 0x0 }, // 1859 |
| 9150 | { PseudoVFMSUB_VV_MF2_E32_MASK, VFMSUB_VV, 0x7, 0x0 }, // 1860 |
| 9151 | { PseudoVFMUL_VFPR16_M1_E16, VFMUL_VF, 0x0, 0x10 }, // 1861 |
| 9152 | { PseudoVFMUL_VFPR16_M1_E16_MASK, VFMUL_VF, 0x0, 0x10 }, // 1862 |
| 9153 | { PseudoVFMUL_VFPR32_M1_E32, VFMUL_VF, 0x0, 0x20 }, // 1863 |
| 9154 | { PseudoVFMUL_VFPR32_M1_E32_MASK, VFMUL_VF, 0x0, 0x20 }, // 1864 |
| 9155 | { PseudoVFMUL_VFPR64_M1_E64, VFMUL_VF, 0x0, 0x40 }, // 1865 |
| 9156 | { PseudoVFMUL_VFPR64_M1_E64_MASK, VFMUL_VF, 0x0, 0x40 }, // 1866 |
| 9157 | { PseudoVFMUL_VFPR16_M2_E16, VFMUL_VF, 0x1, 0x10 }, // 1867 |
| 9158 | { PseudoVFMUL_VFPR16_M2_E16_MASK, VFMUL_VF, 0x1, 0x10 }, // 1868 |
| 9159 | { PseudoVFMUL_VFPR32_M2_E32, VFMUL_VF, 0x1, 0x20 }, // 1869 |
| 9160 | { PseudoVFMUL_VFPR32_M2_E32_MASK, VFMUL_VF, 0x1, 0x20 }, // 1870 |
| 9161 | { PseudoVFMUL_VFPR64_M2_E64, VFMUL_VF, 0x1, 0x40 }, // 1871 |
| 9162 | { PseudoVFMUL_VFPR64_M2_E64_MASK, VFMUL_VF, 0x1, 0x40 }, // 1872 |
| 9163 | { PseudoVFMUL_VFPR16_M4_E16, VFMUL_VF, 0x2, 0x10 }, // 1873 |
| 9164 | { PseudoVFMUL_VFPR16_M4_E16_MASK, VFMUL_VF, 0x2, 0x10 }, // 1874 |
| 9165 | { PseudoVFMUL_VFPR32_M4_E32, VFMUL_VF, 0x2, 0x20 }, // 1875 |
| 9166 | { PseudoVFMUL_VFPR32_M4_E32_MASK, VFMUL_VF, 0x2, 0x20 }, // 1876 |
| 9167 | { PseudoVFMUL_VFPR64_M4_E64, VFMUL_VF, 0x2, 0x40 }, // 1877 |
| 9168 | { PseudoVFMUL_VFPR64_M4_E64_MASK, VFMUL_VF, 0x2, 0x40 }, // 1878 |
| 9169 | { PseudoVFMUL_VFPR16_M8_E16, VFMUL_VF, 0x3, 0x10 }, // 1879 |
| 9170 | { PseudoVFMUL_VFPR16_M8_E16_MASK, VFMUL_VF, 0x3, 0x10 }, // 1880 |
| 9171 | { PseudoVFMUL_VFPR32_M8_E32, VFMUL_VF, 0x3, 0x20 }, // 1881 |
| 9172 | { PseudoVFMUL_VFPR32_M8_E32_MASK, VFMUL_VF, 0x3, 0x20 }, // 1882 |
| 9173 | { PseudoVFMUL_VFPR64_M8_E64, VFMUL_VF, 0x3, 0x40 }, // 1883 |
| 9174 | { PseudoVFMUL_VFPR64_M8_E64_MASK, VFMUL_VF, 0x3, 0x40 }, // 1884 |
| 9175 | { PseudoVFMUL_VFPR16_MF4_E16, VFMUL_VF, 0x6, 0x10 }, // 1885 |
| 9176 | { PseudoVFMUL_VFPR16_MF4_E16_MASK, VFMUL_VF, 0x6, 0x10 }, // 1886 |
| 9177 | { PseudoVFMUL_VFPR16_MF2_E16, VFMUL_VF, 0x7, 0x10 }, // 1887 |
| 9178 | { PseudoVFMUL_VFPR16_MF2_E16_MASK, VFMUL_VF, 0x7, 0x10 }, // 1888 |
| 9179 | { PseudoVFMUL_VFPR32_MF2_E32, VFMUL_VF, 0x7, 0x20 }, // 1889 |
| 9180 | { PseudoVFMUL_VFPR32_MF2_E32_MASK, VFMUL_VF, 0x7, 0x20 }, // 1890 |
| 9181 | { PseudoVFMUL_VV_M1_E16, VFMUL_VV, 0x0, 0x10 }, // 1891 |
| 9182 | { PseudoVFMUL_VV_M1_E16_MASK, VFMUL_VV, 0x0, 0x10 }, // 1892 |
| 9183 | { PseudoVFMUL_VV_M1_E32, VFMUL_VV, 0x0, 0x20 }, // 1893 |
| 9184 | { PseudoVFMUL_VV_M1_E32_MASK, VFMUL_VV, 0x0, 0x20 }, // 1894 |
| 9185 | { PseudoVFMUL_VV_M1_E64, VFMUL_VV, 0x0, 0x40 }, // 1895 |
| 9186 | { PseudoVFMUL_VV_M1_E64_MASK, VFMUL_VV, 0x0, 0x40 }, // 1896 |
| 9187 | { PseudoVFMUL_VV_M2_E16, VFMUL_VV, 0x1, 0x10 }, // 1897 |
| 9188 | { PseudoVFMUL_VV_M2_E16_MASK, VFMUL_VV, 0x1, 0x10 }, // 1898 |
| 9189 | { PseudoVFMUL_VV_M2_E32, VFMUL_VV, 0x1, 0x20 }, // 1899 |
| 9190 | { PseudoVFMUL_VV_M2_E32_MASK, VFMUL_VV, 0x1, 0x20 }, // 1900 |
| 9191 | { PseudoVFMUL_VV_M2_E64, VFMUL_VV, 0x1, 0x40 }, // 1901 |
| 9192 | { PseudoVFMUL_VV_M2_E64_MASK, VFMUL_VV, 0x1, 0x40 }, // 1902 |
| 9193 | { PseudoVFMUL_VV_M4_E16, VFMUL_VV, 0x2, 0x10 }, // 1903 |
| 9194 | { PseudoVFMUL_VV_M4_E16_MASK, VFMUL_VV, 0x2, 0x10 }, // 1904 |
| 9195 | { PseudoVFMUL_VV_M4_E32, VFMUL_VV, 0x2, 0x20 }, // 1905 |
| 9196 | { PseudoVFMUL_VV_M4_E32_MASK, VFMUL_VV, 0x2, 0x20 }, // 1906 |
| 9197 | { PseudoVFMUL_VV_M4_E64, VFMUL_VV, 0x2, 0x40 }, // 1907 |
| 9198 | { PseudoVFMUL_VV_M4_E64_MASK, VFMUL_VV, 0x2, 0x40 }, // 1908 |
| 9199 | { PseudoVFMUL_VV_M8_E16, VFMUL_VV, 0x3, 0x10 }, // 1909 |
| 9200 | { PseudoVFMUL_VV_M8_E16_MASK, VFMUL_VV, 0x3, 0x10 }, // 1910 |
| 9201 | { PseudoVFMUL_VV_M8_E32, VFMUL_VV, 0x3, 0x20 }, // 1911 |
| 9202 | { PseudoVFMUL_VV_M8_E32_MASK, VFMUL_VV, 0x3, 0x20 }, // 1912 |
| 9203 | { PseudoVFMUL_VV_M8_E64, VFMUL_VV, 0x3, 0x40 }, // 1913 |
| 9204 | { PseudoVFMUL_VV_M8_E64_MASK, VFMUL_VV, 0x3, 0x40 }, // 1914 |
| 9205 | { PseudoVFMUL_VV_MF4_E16, VFMUL_VV, 0x6, 0x10 }, // 1915 |
| 9206 | { PseudoVFMUL_VV_MF4_E16_MASK, VFMUL_VV, 0x6, 0x10 }, // 1916 |
| 9207 | { PseudoVFMUL_VV_MF2_E16, VFMUL_VV, 0x7, 0x10 }, // 1917 |
| 9208 | { PseudoVFMUL_VV_MF2_E16_MASK, VFMUL_VV, 0x7, 0x10 }, // 1918 |
| 9209 | { PseudoVFMUL_VV_MF2_E32, VFMUL_VV, 0x7, 0x20 }, // 1919 |
| 9210 | { PseudoVFMUL_VV_MF2_E32_MASK, VFMUL_VV, 0x7, 0x20 }, // 1920 |
| 9211 | { PseudoVFMV_FPR16_S_M1, VFMV_F_S, 0x0, 0x0 }, // 1921 |
| 9212 | { PseudoVFMV_FPR32_S_M1, VFMV_F_S, 0x0, 0x0 }, // 1922 |
| 9213 | { PseudoVFMV_FPR64_S_M1, VFMV_F_S, 0x0, 0x0 }, // 1923 |
| 9214 | { PseudoVFMV_FPR16_S_M2, VFMV_F_S, 0x1, 0x0 }, // 1924 |
| 9215 | { PseudoVFMV_FPR32_S_M2, VFMV_F_S, 0x1, 0x0 }, // 1925 |
| 9216 | { PseudoVFMV_FPR64_S_M2, VFMV_F_S, 0x1, 0x0 }, // 1926 |
| 9217 | { PseudoVFMV_FPR16_S_M4, VFMV_F_S, 0x2, 0x0 }, // 1927 |
| 9218 | { PseudoVFMV_FPR32_S_M4, VFMV_F_S, 0x2, 0x0 }, // 1928 |
| 9219 | { PseudoVFMV_FPR64_S_M4, VFMV_F_S, 0x2, 0x0 }, // 1929 |
| 9220 | { PseudoVFMV_FPR16_S_M8, VFMV_F_S, 0x3, 0x0 }, // 1930 |
| 9221 | { PseudoVFMV_FPR32_S_M8, VFMV_F_S, 0x3, 0x0 }, // 1931 |
| 9222 | { PseudoVFMV_FPR64_S_M8, VFMV_F_S, 0x3, 0x0 }, // 1932 |
| 9223 | { PseudoVFMV_FPR16_S_MF4, VFMV_F_S, 0x6, 0x0 }, // 1933 |
| 9224 | { PseudoVFMV_FPR16_S_MF2, VFMV_F_S, 0x7, 0x0 }, // 1934 |
| 9225 | { PseudoVFMV_FPR32_S_MF2, VFMV_F_S, 0x7, 0x0 }, // 1935 |
| 9226 | { PseudoVFMV_S_FPR16_M1, VFMV_S_F, 0x0, 0x0 }, // 1936 |
| 9227 | { PseudoVFMV_S_FPR32_M1, VFMV_S_F, 0x0, 0x0 }, // 1937 |
| 9228 | { PseudoVFMV_S_FPR64_M1, VFMV_S_F, 0x0, 0x0 }, // 1938 |
| 9229 | { PseudoVFMV_S_FPR16_M2, VFMV_S_F, 0x1, 0x0 }, // 1939 |
| 9230 | { PseudoVFMV_S_FPR32_M2, VFMV_S_F, 0x1, 0x0 }, // 1940 |
| 9231 | { PseudoVFMV_S_FPR64_M2, VFMV_S_F, 0x1, 0x0 }, // 1941 |
| 9232 | { PseudoVFMV_S_FPR16_M4, VFMV_S_F, 0x2, 0x0 }, // 1942 |
| 9233 | { PseudoVFMV_S_FPR32_M4, VFMV_S_F, 0x2, 0x0 }, // 1943 |
| 9234 | { PseudoVFMV_S_FPR64_M4, VFMV_S_F, 0x2, 0x0 }, // 1944 |
| 9235 | { PseudoVFMV_S_FPR16_M8, VFMV_S_F, 0x3, 0x0 }, // 1945 |
| 9236 | { PseudoVFMV_S_FPR32_M8, VFMV_S_F, 0x3, 0x0 }, // 1946 |
| 9237 | { PseudoVFMV_S_FPR64_M8, VFMV_S_F, 0x3, 0x0 }, // 1947 |
| 9238 | { PseudoVFMV_S_FPR16_MF4, VFMV_S_F, 0x6, 0x0 }, // 1948 |
| 9239 | { PseudoVFMV_S_FPR16_MF2, VFMV_S_F, 0x7, 0x0 }, // 1949 |
| 9240 | { PseudoVFMV_S_FPR32_MF2, VFMV_S_F, 0x7, 0x0 }, // 1950 |
| 9241 | { PseudoVFMV_V_FPR16_M1, VFMV_V_F, 0x0, 0x0 }, // 1951 |
| 9242 | { PseudoVFMV_V_FPR32_M1, VFMV_V_F, 0x0, 0x0 }, // 1952 |
| 9243 | { PseudoVFMV_V_FPR64_M1, VFMV_V_F, 0x0, 0x0 }, // 1953 |
| 9244 | { PseudoVFMV_V_FPR16_M2, VFMV_V_F, 0x1, 0x0 }, // 1954 |
| 9245 | { PseudoVFMV_V_FPR32_M2, VFMV_V_F, 0x1, 0x0 }, // 1955 |
| 9246 | { PseudoVFMV_V_FPR64_M2, VFMV_V_F, 0x1, 0x0 }, // 1956 |
| 9247 | { PseudoVFMV_V_FPR16_M4, VFMV_V_F, 0x2, 0x0 }, // 1957 |
| 9248 | { PseudoVFMV_V_FPR32_M4, VFMV_V_F, 0x2, 0x0 }, // 1958 |
| 9249 | { PseudoVFMV_V_FPR64_M4, VFMV_V_F, 0x2, 0x0 }, // 1959 |
| 9250 | { PseudoVFMV_V_FPR16_M8, VFMV_V_F, 0x3, 0x0 }, // 1960 |
| 9251 | { PseudoVFMV_V_FPR32_M8, VFMV_V_F, 0x3, 0x0 }, // 1961 |
| 9252 | { PseudoVFMV_V_FPR64_M8, VFMV_V_F, 0x3, 0x0 }, // 1962 |
| 9253 | { PseudoVFMV_V_FPR16_MF4, VFMV_V_F, 0x6, 0x0 }, // 1963 |
| 9254 | { PseudoVFMV_V_FPR16_MF2, VFMV_V_F, 0x7, 0x0 }, // 1964 |
| 9255 | { PseudoVFMV_V_FPR32_MF2, VFMV_V_F, 0x7, 0x0 }, // 1965 |
| 9256 | { PseudoVFNCVTBF16_F_F_W_M1_E16, VFNCVTBF16_F_F_W, 0x0, 0x10 }, // 1966 |
| 9257 | { PseudoVFNCVTBF16_F_F_W_M1_E16_MASK, VFNCVTBF16_F_F_W, 0x0, 0x10 }, // 1967 |
| 9258 | { PseudoVFNCVTBF16_F_F_W_M1_E32, VFNCVTBF16_F_F_W, 0x0, 0x20 }, // 1968 |
| 9259 | { PseudoVFNCVTBF16_F_F_W_M1_E32_MASK, VFNCVTBF16_F_F_W, 0x0, 0x20 }, // 1969 |
| 9260 | { PseudoVFNCVTBF16_F_F_W_M2_E16, VFNCVTBF16_F_F_W, 0x1, 0x10 }, // 1970 |
| 9261 | { PseudoVFNCVTBF16_F_F_W_M2_E16_MASK, VFNCVTBF16_F_F_W, 0x1, 0x10 }, // 1971 |
| 9262 | { PseudoVFNCVTBF16_F_F_W_M2_E32, VFNCVTBF16_F_F_W, 0x1, 0x20 }, // 1972 |
| 9263 | { PseudoVFNCVTBF16_F_F_W_M2_E32_MASK, VFNCVTBF16_F_F_W, 0x1, 0x20 }, // 1973 |
| 9264 | { PseudoVFNCVTBF16_F_F_W_M4_E16, VFNCVTBF16_F_F_W, 0x2, 0x10 }, // 1974 |
| 9265 | { PseudoVFNCVTBF16_F_F_W_M4_E16_MASK, VFNCVTBF16_F_F_W, 0x2, 0x10 }, // 1975 |
| 9266 | { PseudoVFNCVTBF16_F_F_W_M4_E32, VFNCVTBF16_F_F_W, 0x2, 0x20 }, // 1976 |
| 9267 | { PseudoVFNCVTBF16_F_F_W_M4_E32_MASK, VFNCVTBF16_F_F_W, 0x2, 0x20 }, // 1977 |
| 9268 | { PseudoVFNCVTBF16_F_F_W_MF4_E16, VFNCVTBF16_F_F_W, 0x6, 0x10 }, // 1978 |
| 9269 | { PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK, VFNCVTBF16_F_F_W, 0x6, 0x10 }, // 1979 |
| 9270 | { PseudoVFNCVTBF16_F_F_W_MF2_E16, VFNCVTBF16_F_F_W, 0x7, 0x10 }, // 1980 |
| 9271 | { PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK, VFNCVTBF16_F_F_W, 0x7, 0x10 }, // 1981 |
| 9272 | { PseudoVFNCVTBF16_F_F_W_MF2_E32, VFNCVTBF16_F_F_W, 0x7, 0x20 }, // 1982 |
| 9273 | { PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK, VFNCVTBF16_F_F_W, 0x7, 0x20 }, // 1983 |
| 9274 | { PseudoVFNCVT_F_F_W_M1_E16, VFNCVT_F_F_W, 0x0, 0x10 }, // 1984 |
| 9275 | { PseudoVFNCVT_F_F_W_M1_E16_MASK, VFNCVT_F_F_W, 0x0, 0x10 }, // 1985 |
| 9276 | { PseudoVFNCVT_F_F_W_M1_E32, VFNCVT_F_F_W, 0x0, 0x20 }, // 1986 |
| 9277 | { PseudoVFNCVT_F_F_W_M1_E32_MASK, VFNCVT_F_F_W, 0x0, 0x20 }, // 1987 |
| 9278 | { PseudoVFNCVT_F_F_W_M2_E16, VFNCVT_F_F_W, 0x1, 0x10 }, // 1988 |
| 9279 | { PseudoVFNCVT_F_F_W_M2_E16_MASK, VFNCVT_F_F_W, 0x1, 0x10 }, // 1989 |
| 9280 | { PseudoVFNCVT_F_F_W_M2_E32, VFNCVT_F_F_W, 0x1, 0x20 }, // 1990 |
| 9281 | { PseudoVFNCVT_F_F_W_M2_E32_MASK, VFNCVT_F_F_W, 0x1, 0x20 }, // 1991 |
| 9282 | { PseudoVFNCVT_F_F_W_M4_E16, VFNCVT_F_F_W, 0x2, 0x10 }, // 1992 |
| 9283 | { PseudoVFNCVT_F_F_W_M4_E16_MASK, VFNCVT_F_F_W, 0x2, 0x10 }, // 1993 |
| 9284 | { PseudoVFNCVT_F_F_W_M4_E32, VFNCVT_F_F_W, 0x2, 0x20 }, // 1994 |
| 9285 | { PseudoVFNCVT_F_F_W_M4_E32_MASK, VFNCVT_F_F_W, 0x2, 0x20 }, // 1995 |
| 9286 | { PseudoVFNCVT_F_F_W_MF4_E16, VFNCVT_F_F_W, 0x6, 0x10 }, // 1996 |
| 9287 | { PseudoVFNCVT_F_F_W_MF4_E16_MASK, VFNCVT_F_F_W, 0x6, 0x10 }, // 1997 |
| 9288 | { PseudoVFNCVT_F_F_W_MF2_E16, VFNCVT_F_F_W, 0x7, 0x10 }, // 1998 |
| 9289 | { PseudoVFNCVT_F_F_W_MF2_E16_MASK, VFNCVT_F_F_W, 0x7, 0x10 }, // 1999 |
| 9290 | { PseudoVFNCVT_F_F_W_MF2_E32, VFNCVT_F_F_W, 0x7, 0x20 }, // 2000 |
| 9291 | { PseudoVFNCVT_F_F_W_MF2_E32_MASK, VFNCVT_F_F_W, 0x7, 0x20 }, // 2001 |
| 9292 | { PseudoVFNCVT_F_XU_W_M1_E16, VFNCVT_F_XU_W, 0x0, 0x10 }, // 2002 |
| 9293 | { PseudoVFNCVT_F_XU_W_M1_E16_MASK, VFNCVT_F_XU_W, 0x0, 0x10 }, // 2003 |
| 9294 | { PseudoVFNCVT_RM_F_XU_W_M1_E16, VFNCVT_F_XU_W, 0x0, 0x10 }, // 2004 |
| 9295 | { PseudoVFNCVT_RM_F_XU_W_M1_E16_MASK, VFNCVT_F_XU_W, 0x0, 0x10 }, // 2005 |
| 9296 | { PseudoVFNCVT_F_XU_W_M1_E32, VFNCVT_F_XU_W, 0x0, 0x20 }, // 2006 |
| 9297 | { PseudoVFNCVT_F_XU_W_M1_E32_MASK, VFNCVT_F_XU_W, 0x0, 0x20 }, // 2007 |
| 9298 | { PseudoVFNCVT_RM_F_XU_W_M1_E32, VFNCVT_F_XU_W, 0x0, 0x20 }, // 2008 |
| 9299 | { PseudoVFNCVT_RM_F_XU_W_M1_E32_MASK, VFNCVT_F_XU_W, 0x0, 0x20 }, // 2009 |
| 9300 | { PseudoVFNCVT_F_XU_W_M2_E16, VFNCVT_F_XU_W, 0x1, 0x10 }, // 2010 |
| 9301 | { PseudoVFNCVT_F_XU_W_M2_E16_MASK, VFNCVT_F_XU_W, 0x1, 0x10 }, // 2011 |
| 9302 | { PseudoVFNCVT_RM_F_XU_W_M2_E16, VFNCVT_F_XU_W, 0x1, 0x10 }, // 2012 |
| 9303 | { PseudoVFNCVT_RM_F_XU_W_M2_E16_MASK, VFNCVT_F_XU_W, 0x1, 0x10 }, // 2013 |
| 9304 | { PseudoVFNCVT_F_XU_W_M2_E32, VFNCVT_F_XU_W, 0x1, 0x20 }, // 2014 |
| 9305 | { PseudoVFNCVT_F_XU_W_M2_E32_MASK, VFNCVT_F_XU_W, 0x1, 0x20 }, // 2015 |
| 9306 | { PseudoVFNCVT_RM_F_XU_W_M2_E32, VFNCVT_F_XU_W, 0x1, 0x20 }, // 2016 |
| 9307 | { PseudoVFNCVT_RM_F_XU_W_M2_E32_MASK, VFNCVT_F_XU_W, 0x1, 0x20 }, // 2017 |
| 9308 | { PseudoVFNCVT_F_XU_W_M4_E16, VFNCVT_F_XU_W, 0x2, 0x10 }, // 2018 |
| 9309 | { PseudoVFNCVT_F_XU_W_M4_E16_MASK, VFNCVT_F_XU_W, 0x2, 0x10 }, // 2019 |
| 9310 | { PseudoVFNCVT_RM_F_XU_W_M4_E16, VFNCVT_F_XU_W, 0x2, 0x10 }, // 2020 |
| 9311 | { PseudoVFNCVT_RM_F_XU_W_M4_E16_MASK, VFNCVT_F_XU_W, 0x2, 0x10 }, // 2021 |
| 9312 | { PseudoVFNCVT_F_XU_W_M4_E32, VFNCVT_F_XU_W, 0x2, 0x20 }, // 2022 |
| 9313 | { PseudoVFNCVT_F_XU_W_M4_E32_MASK, VFNCVT_F_XU_W, 0x2, 0x20 }, // 2023 |
| 9314 | { PseudoVFNCVT_RM_F_XU_W_M4_E32, VFNCVT_F_XU_W, 0x2, 0x20 }, // 2024 |
| 9315 | { PseudoVFNCVT_RM_F_XU_W_M4_E32_MASK, VFNCVT_F_XU_W, 0x2, 0x20 }, // 2025 |
| 9316 | { PseudoVFNCVT_F_XU_W_MF4_E16, VFNCVT_F_XU_W, 0x6, 0x10 }, // 2026 |
| 9317 | { PseudoVFNCVT_F_XU_W_MF4_E16_MASK, VFNCVT_F_XU_W, 0x6, 0x10 }, // 2027 |
| 9318 | { PseudoVFNCVT_RM_F_XU_W_MF4_E16, VFNCVT_F_XU_W, 0x6, 0x10 }, // 2028 |
| 9319 | { PseudoVFNCVT_RM_F_XU_W_MF4_E16_MASK, VFNCVT_F_XU_W, 0x6, 0x10 }, // 2029 |
| 9320 | { PseudoVFNCVT_F_XU_W_MF2_E16, VFNCVT_F_XU_W, 0x7, 0x10 }, // 2030 |
| 9321 | { PseudoVFNCVT_F_XU_W_MF2_E16_MASK, VFNCVT_F_XU_W, 0x7, 0x10 }, // 2031 |
| 9322 | { PseudoVFNCVT_RM_F_XU_W_MF2_E16, VFNCVT_F_XU_W, 0x7, 0x10 }, // 2032 |
| 9323 | { PseudoVFNCVT_RM_F_XU_W_MF2_E16_MASK, VFNCVT_F_XU_W, 0x7, 0x10 }, // 2033 |
| 9324 | { PseudoVFNCVT_F_XU_W_MF2_E32, VFNCVT_F_XU_W, 0x7, 0x20 }, // 2034 |
| 9325 | { PseudoVFNCVT_F_XU_W_MF2_E32_MASK, VFNCVT_F_XU_W, 0x7, 0x20 }, // 2035 |
| 9326 | { PseudoVFNCVT_RM_F_XU_W_MF2_E32, VFNCVT_F_XU_W, 0x7, 0x20 }, // 2036 |
| 9327 | { PseudoVFNCVT_RM_F_XU_W_MF2_E32_MASK, VFNCVT_F_XU_W, 0x7, 0x20 }, // 2037 |
| 9328 | { PseudoVFNCVT_F_X_W_M1_E16, VFNCVT_F_X_W, 0x0, 0x10 }, // 2038 |
| 9329 | { PseudoVFNCVT_F_X_W_M1_E16_MASK, VFNCVT_F_X_W, 0x0, 0x10 }, // 2039 |
| 9330 | { PseudoVFNCVT_RM_F_X_W_M1_E16, VFNCVT_F_X_W, 0x0, 0x10 }, // 2040 |
| 9331 | { PseudoVFNCVT_RM_F_X_W_M1_E16_MASK, VFNCVT_F_X_W, 0x0, 0x10 }, // 2041 |
| 9332 | { PseudoVFNCVT_F_X_W_M1_E32, VFNCVT_F_X_W, 0x0, 0x20 }, // 2042 |
| 9333 | { PseudoVFNCVT_F_X_W_M1_E32_MASK, VFNCVT_F_X_W, 0x0, 0x20 }, // 2043 |
| 9334 | { PseudoVFNCVT_RM_F_X_W_M1_E32, VFNCVT_F_X_W, 0x0, 0x20 }, // 2044 |
| 9335 | { PseudoVFNCVT_RM_F_X_W_M1_E32_MASK, VFNCVT_F_X_W, 0x0, 0x20 }, // 2045 |
| 9336 | { PseudoVFNCVT_F_X_W_M2_E16, VFNCVT_F_X_W, 0x1, 0x10 }, // 2046 |
| 9337 | { PseudoVFNCVT_F_X_W_M2_E16_MASK, VFNCVT_F_X_W, 0x1, 0x10 }, // 2047 |
| 9338 | { PseudoVFNCVT_RM_F_X_W_M2_E16, VFNCVT_F_X_W, 0x1, 0x10 }, // 2048 |
| 9339 | { PseudoVFNCVT_RM_F_X_W_M2_E16_MASK, VFNCVT_F_X_W, 0x1, 0x10 }, // 2049 |
| 9340 | { PseudoVFNCVT_F_X_W_M2_E32, VFNCVT_F_X_W, 0x1, 0x20 }, // 2050 |
| 9341 | { PseudoVFNCVT_F_X_W_M2_E32_MASK, VFNCVT_F_X_W, 0x1, 0x20 }, // 2051 |
| 9342 | { PseudoVFNCVT_RM_F_X_W_M2_E32, VFNCVT_F_X_W, 0x1, 0x20 }, // 2052 |
| 9343 | { PseudoVFNCVT_RM_F_X_W_M2_E32_MASK, VFNCVT_F_X_W, 0x1, 0x20 }, // 2053 |
| 9344 | { PseudoVFNCVT_F_X_W_M4_E16, VFNCVT_F_X_W, 0x2, 0x10 }, // 2054 |
| 9345 | { PseudoVFNCVT_F_X_W_M4_E16_MASK, VFNCVT_F_X_W, 0x2, 0x10 }, // 2055 |
| 9346 | { PseudoVFNCVT_RM_F_X_W_M4_E16, VFNCVT_F_X_W, 0x2, 0x10 }, // 2056 |
| 9347 | { PseudoVFNCVT_RM_F_X_W_M4_E16_MASK, VFNCVT_F_X_W, 0x2, 0x10 }, // 2057 |
| 9348 | { PseudoVFNCVT_F_X_W_M4_E32, VFNCVT_F_X_W, 0x2, 0x20 }, // 2058 |
| 9349 | { PseudoVFNCVT_F_X_W_M4_E32_MASK, VFNCVT_F_X_W, 0x2, 0x20 }, // 2059 |
| 9350 | { PseudoVFNCVT_RM_F_X_W_M4_E32, VFNCVT_F_X_W, 0x2, 0x20 }, // 2060 |
| 9351 | { PseudoVFNCVT_RM_F_X_W_M4_E32_MASK, VFNCVT_F_X_W, 0x2, 0x20 }, // 2061 |
| 9352 | { PseudoVFNCVT_F_X_W_MF4_E16, VFNCVT_F_X_W, 0x6, 0x10 }, // 2062 |
| 9353 | { PseudoVFNCVT_F_X_W_MF4_E16_MASK, VFNCVT_F_X_W, 0x6, 0x10 }, // 2063 |
| 9354 | { PseudoVFNCVT_RM_F_X_W_MF4_E16, VFNCVT_F_X_W, 0x6, 0x10 }, // 2064 |
| 9355 | { PseudoVFNCVT_RM_F_X_W_MF4_E16_MASK, VFNCVT_F_X_W, 0x6, 0x10 }, // 2065 |
| 9356 | { PseudoVFNCVT_F_X_W_MF2_E16, VFNCVT_F_X_W, 0x7, 0x10 }, // 2066 |
| 9357 | { PseudoVFNCVT_F_X_W_MF2_E16_MASK, VFNCVT_F_X_W, 0x7, 0x10 }, // 2067 |
| 9358 | { PseudoVFNCVT_RM_F_X_W_MF2_E16, VFNCVT_F_X_W, 0x7, 0x10 }, // 2068 |
| 9359 | { PseudoVFNCVT_RM_F_X_W_MF2_E16_MASK, VFNCVT_F_X_W, 0x7, 0x10 }, // 2069 |
| 9360 | { PseudoVFNCVT_F_X_W_MF2_E32, VFNCVT_F_X_W, 0x7, 0x20 }, // 2070 |
| 9361 | { PseudoVFNCVT_F_X_W_MF2_E32_MASK, VFNCVT_F_X_W, 0x7, 0x20 }, // 2071 |
| 9362 | { PseudoVFNCVT_RM_F_X_W_MF2_E32, VFNCVT_F_X_W, 0x7, 0x20 }, // 2072 |
| 9363 | { PseudoVFNCVT_RM_F_X_W_MF2_E32_MASK, VFNCVT_F_X_W, 0x7, 0x20 }, // 2073 |
| 9364 | { PseudoVFNCVT_ROD_F_F_W_M1_E16, VFNCVT_ROD_F_F_W, 0x0, 0x10 }, // 2074 |
| 9365 | { PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK, VFNCVT_ROD_F_F_W, 0x0, 0x10 }, // 2075 |
| 9366 | { PseudoVFNCVT_ROD_F_F_W_M1_E32, VFNCVT_ROD_F_F_W, 0x0, 0x20 }, // 2076 |
| 9367 | { PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK, VFNCVT_ROD_F_F_W, 0x0, 0x20 }, // 2077 |
| 9368 | { PseudoVFNCVT_ROD_F_F_W_M2_E16, VFNCVT_ROD_F_F_W, 0x1, 0x10 }, // 2078 |
| 9369 | { PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK, VFNCVT_ROD_F_F_W, 0x1, 0x10 }, // 2079 |
| 9370 | { PseudoVFNCVT_ROD_F_F_W_M2_E32, VFNCVT_ROD_F_F_W, 0x1, 0x20 }, // 2080 |
| 9371 | { PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK, VFNCVT_ROD_F_F_W, 0x1, 0x20 }, // 2081 |
| 9372 | { PseudoVFNCVT_ROD_F_F_W_M4_E16, VFNCVT_ROD_F_F_W, 0x2, 0x10 }, // 2082 |
| 9373 | { PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK, VFNCVT_ROD_F_F_W, 0x2, 0x10 }, // 2083 |
| 9374 | { PseudoVFNCVT_ROD_F_F_W_M4_E32, VFNCVT_ROD_F_F_W, 0x2, 0x20 }, // 2084 |
| 9375 | { PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK, VFNCVT_ROD_F_F_W, 0x2, 0x20 }, // 2085 |
| 9376 | { PseudoVFNCVT_ROD_F_F_W_MF4_E16, VFNCVT_ROD_F_F_W, 0x6, 0x10 }, // 2086 |
| 9377 | { PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK, VFNCVT_ROD_F_F_W, 0x6, 0x10 }, // 2087 |
| 9378 | { PseudoVFNCVT_ROD_F_F_W_MF2_E16, VFNCVT_ROD_F_F_W, 0x7, 0x10 }, // 2088 |
| 9379 | { PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK, VFNCVT_ROD_F_F_W, 0x7, 0x10 }, // 2089 |
| 9380 | { PseudoVFNCVT_ROD_F_F_W_MF2_E32, VFNCVT_ROD_F_F_W, 0x7, 0x20 }, // 2090 |
| 9381 | { PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK, VFNCVT_ROD_F_F_W, 0x7, 0x20 }, // 2091 |
| 9382 | { PseudoVFNCVT_RTZ_XU_F_W_M1, VFNCVT_RTZ_XU_F_W, 0x0, 0x0 }, // 2092 |
| 9383 | { PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, VFNCVT_RTZ_XU_F_W, 0x0, 0x0 }, // 2093 |
| 9384 | { PseudoVFNCVT_RTZ_XU_F_W_M2, VFNCVT_RTZ_XU_F_W, 0x1, 0x0 }, // 2094 |
| 9385 | { PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, VFNCVT_RTZ_XU_F_W, 0x1, 0x0 }, // 2095 |
| 9386 | { PseudoVFNCVT_RTZ_XU_F_W_M4, VFNCVT_RTZ_XU_F_W, 0x2, 0x0 }, // 2096 |
| 9387 | { PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, VFNCVT_RTZ_XU_F_W, 0x2, 0x0 }, // 2097 |
| 9388 | { PseudoVFNCVT_RTZ_XU_F_W_MF8, VFNCVT_RTZ_XU_F_W, 0x5, 0x0 }, // 2098 |
| 9389 | { PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, VFNCVT_RTZ_XU_F_W, 0x5, 0x0 }, // 2099 |
| 9390 | { PseudoVFNCVT_RTZ_XU_F_W_MF4, VFNCVT_RTZ_XU_F_W, 0x6, 0x0 }, // 2100 |
| 9391 | { PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, VFNCVT_RTZ_XU_F_W, 0x6, 0x0 }, // 2101 |
| 9392 | { PseudoVFNCVT_RTZ_XU_F_W_MF2, VFNCVT_RTZ_XU_F_W, 0x7, 0x0 }, // 2102 |
| 9393 | { PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, VFNCVT_RTZ_XU_F_W, 0x7, 0x0 }, // 2103 |
| 9394 | { PseudoVFNCVT_RTZ_X_F_W_M1, VFNCVT_RTZ_X_F_W, 0x0, 0x0 }, // 2104 |
| 9395 | { PseudoVFNCVT_RTZ_X_F_W_M1_MASK, VFNCVT_RTZ_X_F_W, 0x0, 0x0 }, // 2105 |
| 9396 | { PseudoVFNCVT_RTZ_X_F_W_M2, VFNCVT_RTZ_X_F_W, 0x1, 0x0 }, // 2106 |
| 9397 | { PseudoVFNCVT_RTZ_X_F_W_M2_MASK, VFNCVT_RTZ_X_F_W, 0x1, 0x0 }, // 2107 |
| 9398 | { PseudoVFNCVT_RTZ_X_F_W_M4, VFNCVT_RTZ_X_F_W, 0x2, 0x0 }, // 2108 |
| 9399 | { PseudoVFNCVT_RTZ_X_F_W_M4_MASK, VFNCVT_RTZ_X_F_W, 0x2, 0x0 }, // 2109 |
| 9400 | { PseudoVFNCVT_RTZ_X_F_W_MF8, VFNCVT_RTZ_X_F_W, 0x5, 0x0 }, // 2110 |
| 9401 | { PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, VFNCVT_RTZ_X_F_W, 0x5, 0x0 }, // 2111 |
| 9402 | { PseudoVFNCVT_RTZ_X_F_W_MF4, VFNCVT_RTZ_X_F_W, 0x6, 0x0 }, // 2112 |
| 9403 | { PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, VFNCVT_RTZ_X_F_W, 0x6, 0x0 }, // 2113 |
| 9404 | { PseudoVFNCVT_RTZ_X_F_W_MF2, VFNCVT_RTZ_X_F_W, 0x7, 0x0 }, // 2114 |
| 9405 | { PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, VFNCVT_RTZ_X_F_W, 0x7, 0x0 }, // 2115 |
| 9406 | { PseudoVFNCVT_RM_XU_F_W_M1, VFNCVT_XU_F_W, 0x0, 0x0 }, // 2116 |
| 9407 | { PseudoVFNCVT_RM_XU_F_W_M1_MASK, VFNCVT_XU_F_W, 0x0, 0x0 }, // 2117 |
| 9408 | { PseudoVFNCVT_XU_F_W_M1, VFNCVT_XU_F_W, 0x0, 0x0 }, // 2118 |
| 9409 | { PseudoVFNCVT_XU_F_W_M1_MASK, VFNCVT_XU_F_W, 0x0, 0x0 }, // 2119 |
| 9410 | { PseudoVFNCVT_RM_XU_F_W_M2, VFNCVT_XU_F_W, 0x1, 0x0 }, // 2120 |
| 9411 | { PseudoVFNCVT_RM_XU_F_W_M2_MASK, VFNCVT_XU_F_W, 0x1, 0x0 }, // 2121 |
| 9412 | { PseudoVFNCVT_XU_F_W_M2, VFNCVT_XU_F_W, 0x1, 0x0 }, // 2122 |
| 9413 | { PseudoVFNCVT_XU_F_W_M2_MASK, VFNCVT_XU_F_W, 0x1, 0x0 }, // 2123 |
| 9414 | { PseudoVFNCVT_RM_XU_F_W_M4, VFNCVT_XU_F_W, 0x2, 0x0 }, // 2124 |
| 9415 | { PseudoVFNCVT_RM_XU_F_W_M4_MASK, VFNCVT_XU_F_W, 0x2, 0x0 }, // 2125 |
| 9416 | { PseudoVFNCVT_XU_F_W_M4, VFNCVT_XU_F_W, 0x2, 0x0 }, // 2126 |
| 9417 | { PseudoVFNCVT_XU_F_W_M4_MASK, VFNCVT_XU_F_W, 0x2, 0x0 }, // 2127 |
| 9418 | { PseudoVFNCVT_RM_XU_F_W_MF8, VFNCVT_XU_F_W, 0x5, 0x0 }, // 2128 |
| 9419 | { PseudoVFNCVT_RM_XU_F_W_MF8_MASK, VFNCVT_XU_F_W, 0x5, 0x0 }, // 2129 |
| 9420 | { PseudoVFNCVT_XU_F_W_MF8, VFNCVT_XU_F_W, 0x5, 0x0 }, // 2130 |
| 9421 | { PseudoVFNCVT_XU_F_W_MF8_MASK, VFNCVT_XU_F_W, 0x5, 0x0 }, // 2131 |
| 9422 | { PseudoVFNCVT_RM_XU_F_W_MF4, VFNCVT_XU_F_W, 0x6, 0x0 }, // 2132 |
| 9423 | { PseudoVFNCVT_RM_XU_F_W_MF4_MASK, VFNCVT_XU_F_W, 0x6, 0x0 }, // 2133 |
| 9424 | { PseudoVFNCVT_XU_F_W_MF4, VFNCVT_XU_F_W, 0x6, 0x0 }, // 2134 |
| 9425 | { PseudoVFNCVT_XU_F_W_MF4_MASK, VFNCVT_XU_F_W, 0x6, 0x0 }, // 2135 |
| 9426 | { PseudoVFNCVT_RM_XU_F_W_MF2, VFNCVT_XU_F_W, 0x7, 0x0 }, // 2136 |
| 9427 | { PseudoVFNCVT_RM_XU_F_W_MF2_MASK, VFNCVT_XU_F_W, 0x7, 0x0 }, // 2137 |
| 9428 | { PseudoVFNCVT_XU_F_W_MF2, VFNCVT_XU_F_W, 0x7, 0x0 }, // 2138 |
| 9429 | { PseudoVFNCVT_XU_F_W_MF2_MASK, VFNCVT_XU_F_W, 0x7, 0x0 }, // 2139 |
| 9430 | { PseudoVFNCVT_RM_X_F_W_M1, VFNCVT_X_F_W, 0x0, 0x0 }, // 2140 |
| 9431 | { PseudoVFNCVT_RM_X_F_W_M1_MASK, VFNCVT_X_F_W, 0x0, 0x0 }, // 2141 |
| 9432 | { PseudoVFNCVT_X_F_W_M1, VFNCVT_X_F_W, 0x0, 0x0 }, // 2142 |
| 9433 | { PseudoVFNCVT_X_F_W_M1_MASK, VFNCVT_X_F_W, 0x0, 0x0 }, // 2143 |
| 9434 | { PseudoVFNCVT_RM_X_F_W_M2, VFNCVT_X_F_W, 0x1, 0x0 }, // 2144 |
| 9435 | { PseudoVFNCVT_RM_X_F_W_M2_MASK, VFNCVT_X_F_W, 0x1, 0x0 }, // 2145 |
| 9436 | { PseudoVFNCVT_X_F_W_M2, VFNCVT_X_F_W, 0x1, 0x0 }, // 2146 |
| 9437 | { PseudoVFNCVT_X_F_W_M2_MASK, VFNCVT_X_F_W, 0x1, 0x0 }, // 2147 |
| 9438 | { PseudoVFNCVT_RM_X_F_W_M4, VFNCVT_X_F_W, 0x2, 0x0 }, // 2148 |
| 9439 | { PseudoVFNCVT_RM_X_F_W_M4_MASK, VFNCVT_X_F_W, 0x2, 0x0 }, // 2149 |
| 9440 | { PseudoVFNCVT_X_F_W_M4, VFNCVT_X_F_W, 0x2, 0x0 }, // 2150 |
| 9441 | { PseudoVFNCVT_X_F_W_M4_MASK, VFNCVT_X_F_W, 0x2, 0x0 }, // 2151 |
| 9442 | { PseudoVFNCVT_RM_X_F_W_MF8, VFNCVT_X_F_W, 0x5, 0x0 }, // 2152 |
| 9443 | { PseudoVFNCVT_RM_X_F_W_MF8_MASK, VFNCVT_X_F_W, 0x5, 0x0 }, // 2153 |
| 9444 | { PseudoVFNCVT_X_F_W_MF8, VFNCVT_X_F_W, 0x5, 0x0 }, // 2154 |
| 9445 | { PseudoVFNCVT_X_F_W_MF8_MASK, VFNCVT_X_F_W, 0x5, 0x0 }, // 2155 |
| 9446 | { PseudoVFNCVT_RM_X_F_W_MF4, VFNCVT_X_F_W, 0x6, 0x0 }, // 2156 |
| 9447 | { PseudoVFNCVT_RM_X_F_W_MF4_MASK, VFNCVT_X_F_W, 0x6, 0x0 }, // 2157 |
| 9448 | { PseudoVFNCVT_X_F_W_MF4, VFNCVT_X_F_W, 0x6, 0x0 }, // 2158 |
| 9449 | { PseudoVFNCVT_X_F_W_MF4_MASK, VFNCVT_X_F_W, 0x6, 0x0 }, // 2159 |
| 9450 | { PseudoVFNCVT_RM_X_F_W_MF2, VFNCVT_X_F_W, 0x7, 0x0 }, // 2160 |
| 9451 | { PseudoVFNCVT_RM_X_F_W_MF2_MASK, VFNCVT_X_F_W, 0x7, 0x0 }, // 2161 |
| 9452 | { PseudoVFNCVT_X_F_W_MF2, VFNCVT_X_F_W, 0x7, 0x0 }, // 2162 |
| 9453 | { PseudoVFNCVT_X_F_W_MF2_MASK, VFNCVT_X_F_W, 0x7, 0x0 }, // 2163 |
| 9454 | { PseudoVFNMACC_VFPR16_M1_E16, VFNMACC_VF, 0x0, 0x0 }, // 2164 |
| 9455 | { PseudoVFNMACC_VFPR16_M1_E16_MASK, VFNMACC_VF, 0x0, 0x0 }, // 2165 |
| 9456 | { PseudoVFNMACC_VFPR32_M1_E32, VFNMACC_VF, 0x0, 0x0 }, // 2166 |
| 9457 | { PseudoVFNMACC_VFPR32_M1_E32_MASK, VFNMACC_VF, 0x0, 0x0 }, // 2167 |
| 9458 | { PseudoVFNMACC_VFPR64_M1_E64, VFNMACC_VF, 0x0, 0x0 }, // 2168 |
| 9459 | { PseudoVFNMACC_VFPR64_M1_E64_MASK, VFNMACC_VF, 0x0, 0x0 }, // 2169 |
| 9460 | { PseudoVFNMACC_VFPR16_M2_E16, VFNMACC_VF, 0x1, 0x0 }, // 2170 |
| 9461 | { PseudoVFNMACC_VFPR16_M2_E16_MASK, VFNMACC_VF, 0x1, 0x0 }, // 2171 |
| 9462 | { PseudoVFNMACC_VFPR32_M2_E32, VFNMACC_VF, 0x1, 0x0 }, // 2172 |
| 9463 | { PseudoVFNMACC_VFPR32_M2_E32_MASK, VFNMACC_VF, 0x1, 0x0 }, // 2173 |
| 9464 | { PseudoVFNMACC_VFPR64_M2_E64, VFNMACC_VF, 0x1, 0x0 }, // 2174 |
| 9465 | { PseudoVFNMACC_VFPR64_M2_E64_MASK, VFNMACC_VF, 0x1, 0x0 }, // 2175 |
| 9466 | { PseudoVFNMACC_VFPR16_M4_E16, VFNMACC_VF, 0x2, 0x0 }, // 2176 |
| 9467 | { PseudoVFNMACC_VFPR16_M4_E16_MASK, VFNMACC_VF, 0x2, 0x0 }, // 2177 |
| 9468 | { PseudoVFNMACC_VFPR32_M4_E32, VFNMACC_VF, 0x2, 0x0 }, // 2178 |
| 9469 | { PseudoVFNMACC_VFPR32_M4_E32_MASK, VFNMACC_VF, 0x2, 0x0 }, // 2179 |
| 9470 | { PseudoVFNMACC_VFPR64_M4_E64, VFNMACC_VF, 0x2, 0x0 }, // 2180 |
| 9471 | { PseudoVFNMACC_VFPR64_M4_E64_MASK, VFNMACC_VF, 0x2, 0x0 }, // 2181 |
| 9472 | { PseudoVFNMACC_VFPR16_M8_E16, VFNMACC_VF, 0x3, 0x0 }, // 2182 |
| 9473 | { PseudoVFNMACC_VFPR16_M8_E16_MASK, VFNMACC_VF, 0x3, 0x0 }, // 2183 |
| 9474 | { PseudoVFNMACC_VFPR32_M8_E32, VFNMACC_VF, 0x3, 0x0 }, // 2184 |
| 9475 | { PseudoVFNMACC_VFPR32_M8_E32_MASK, VFNMACC_VF, 0x3, 0x0 }, // 2185 |
| 9476 | { PseudoVFNMACC_VFPR64_M8_E64, VFNMACC_VF, 0x3, 0x0 }, // 2186 |
| 9477 | { PseudoVFNMACC_VFPR64_M8_E64_MASK, VFNMACC_VF, 0x3, 0x0 }, // 2187 |
| 9478 | { PseudoVFNMACC_VFPR16_MF4_E16, VFNMACC_VF, 0x6, 0x0 }, // 2188 |
| 9479 | { PseudoVFNMACC_VFPR16_MF4_E16_MASK, VFNMACC_VF, 0x6, 0x0 }, // 2189 |
| 9480 | { PseudoVFNMACC_VFPR16_MF2_E16, VFNMACC_VF, 0x7, 0x0 }, // 2190 |
| 9481 | { PseudoVFNMACC_VFPR16_MF2_E16_MASK, VFNMACC_VF, 0x7, 0x0 }, // 2191 |
| 9482 | { PseudoVFNMACC_VFPR32_MF2_E32, VFNMACC_VF, 0x7, 0x0 }, // 2192 |
| 9483 | { PseudoVFNMACC_VFPR32_MF2_E32_MASK, VFNMACC_VF, 0x7, 0x0 }, // 2193 |
| 9484 | { PseudoVFNMACC_VV_M1_E16, VFNMACC_VV, 0x0, 0x0 }, // 2194 |
| 9485 | { PseudoVFNMACC_VV_M1_E16_MASK, VFNMACC_VV, 0x0, 0x0 }, // 2195 |
| 9486 | { PseudoVFNMACC_VV_M1_E32, VFNMACC_VV, 0x0, 0x0 }, // 2196 |
| 9487 | { PseudoVFNMACC_VV_M1_E32_MASK, VFNMACC_VV, 0x0, 0x0 }, // 2197 |
| 9488 | { PseudoVFNMACC_VV_M1_E64, VFNMACC_VV, 0x0, 0x0 }, // 2198 |
| 9489 | { PseudoVFNMACC_VV_M1_E64_MASK, VFNMACC_VV, 0x0, 0x0 }, // 2199 |
| 9490 | { PseudoVFNMACC_VV_M2_E16, VFNMACC_VV, 0x1, 0x0 }, // 2200 |
| 9491 | { PseudoVFNMACC_VV_M2_E16_MASK, VFNMACC_VV, 0x1, 0x0 }, // 2201 |
| 9492 | { PseudoVFNMACC_VV_M2_E32, VFNMACC_VV, 0x1, 0x0 }, // 2202 |
| 9493 | { PseudoVFNMACC_VV_M2_E32_MASK, VFNMACC_VV, 0x1, 0x0 }, // 2203 |
| 9494 | { PseudoVFNMACC_VV_M2_E64, VFNMACC_VV, 0x1, 0x0 }, // 2204 |
| 9495 | { PseudoVFNMACC_VV_M2_E64_MASK, VFNMACC_VV, 0x1, 0x0 }, // 2205 |
| 9496 | { PseudoVFNMACC_VV_M4_E16, VFNMACC_VV, 0x2, 0x0 }, // 2206 |
| 9497 | { PseudoVFNMACC_VV_M4_E16_MASK, VFNMACC_VV, 0x2, 0x0 }, // 2207 |
| 9498 | { PseudoVFNMACC_VV_M4_E32, VFNMACC_VV, 0x2, 0x0 }, // 2208 |
| 9499 | { PseudoVFNMACC_VV_M4_E32_MASK, VFNMACC_VV, 0x2, 0x0 }, // 2209 |
| 9500 | { PseudoVFNMACC_VV_M4_E64, VFNMACC_VV, 0x2, 0x0 }, // 2210 |
| 9501 | { PseudoVFNMACC_VV_M4_E64_MASK, VFNMACC_VV, 0x2, 0x0 }, // 2211 |
| 9502 | { PseudoVFNMACC_VV_M8_E16, VFNMACC_VV, 0x3, 0x0 }, // 2212 |
| 9503 | { PseudoVFNMACC_VV_M8_E16_MASK, VFNMACC_VV, 0x3, 0x0 }, // 2213 |
| 9504 | { PseudoVFNMACC_VV_M8_E32, VFNMACC_VV, 0x3, 0x0 }, // 2214 |
| 9505 | { PseudoVFNMACC_VV_M8_E32_MASK, VFNMACC_VV, 0x3, 0x0 }, // 2215 |
| 9506 | { PseudoVFNMACC_VV_M8_E64, VFNMACC_VV, 0x3, 0x0 }, // 2216 |
| 9507 | { PseudoVFNMACC_VV_M8_E64_MASK, VFNMACC_VV, 0x3, 0x0 }, // 2217 |
| 9508 | { PseudoVFNMACC_VV_MF4_E16, VFNMACC_VV, 0x6, 0x0 }, // 2218 |
| 9509 | { PseudoVFNMACC_VV_MF4_E16_MASK, VFNMACC_VV, 0x6, 0x0 }, // 2219 |
| 9510 | { PseudoVFNMACC_VV_MF2_E16, VFNMACC_VV, 0x7, 0x0 }, // 2220 |
| 9511 | { PseudoVFNMACC_VV_MF2_E16_MASK, VFNMACC_VV, 0x7, 0x0 }, // 2221 |
| 9512 | { PseudoVFNMACC_VV_MF2_E32, VFNMACC_VV, 0x7, 0x0 }, // 2222 |
| 9513 | { PseudoVFNMACC_VV_MF2_E32_MASK, VFNMACC_VV, 0x7, 0x0 }, // 2223 |
| 9514 | { PseudoVFNMADD_VFPR16_M1_E16, VFNMADD_VF, 0x0, 0x0 }, // 2224 |
| 9515 | { PseudoVFNMADD_VFPR16_M1_E16_MASK, VFNMADD_VF, 0x0, 0x0 }, // 2225 |
| 9516 | { PseudoVFNMADD_VFPR32_M1_E32, VFNMADD_VF, 0x0, 0x0 }, // 2226 |
| 9517 | { PseudoVFNMADD_VFPR32_M1_E32_MASK, VFNMADD_VF, 0x0, 0x0 }, // 2227 |
| 9518 | { PseudoVFNMADD_VFPR64_M1_E64, VFNMADD_VF, 0x0, 0x0 }, // 2228 |
| 9519 | { PseudoVFNMADD_VFPR64_M1_E64_MASK, VFNMADD_VF, 0x0, 0x0 }, // 2229 |
| 9520 | { PseudoVFNMADD_VFPR16_M2_E16, VFNMADD_VF, 0x1, 0x0 }, // 2230 |
| 9521 | { PseudoVFNMADD_VFPR16_M2_E16_MASK, VFNMADD_VF, 0x1, 0x0 }, // 2231 |
| 9522 | { PseudoVFNMADD_VFPR32_M2_E32, VFNMADD_VF, 0x1, 0x0 }, // 2232 |
| 9523 | { PseudoVFNMADD_VFPR32_M2_E32_MASK, VFNMADD_VF, 0x1, 0x0 }, // 2233 |
| 9524 | { PseudoVFNMADD_VFPR64_M2_E64, VFNMADD_VF, 0x1, 0x0 }, // 2234 |
| 9525 | { PseudoVFNMADD_VFPR64_M2_E64_MASK, VFNMADD_VF, 0x1, 0x0 }, // 2235 |
| 9526 | { PseudoVFNMADD_VFPR16_M4_E16, VFNMADD_VF, 0x2, 0x0 }, // 2236 |
| 9527 | { PseudoVFNMADD_VFPR16_M4_E16_MASK, VFNMADD_VF, 0x2, 0x0 }, // 2237 |
| 9528 | { PseudoVFNMADD_VFPR32_M4_E32, VFNMADD_VF, 0x2, 0x0 }, // 2238 |
| 9529 | { PseudoVFNMADD_VFPR32_M4_E32_MASK, VFNMADD_VF, 0x2, 0x0 }, // 2239 |
| 9530 | { PseudoVFNMADD_VFPR64_M4_E64, VFNMADD_VF, 0x2, 0x0 }, // 2240 |
| 9531 | { PseudoVFNMADD_VFPR64_M4_E64_MASK, VFNMADD_VF, 0x2, 0x0 }, // 2241 |
| 9532 | { PseudoVFNMADD_VFPR16_M8_E16, VFNMADD_VF, 0x3, 0x0 }, // 2242 |
| 9533 | { PseudoVFNMADD_VFPR16_M8_E16_MASK, VFNMADD_VF, 0x3, 0x0 }, // 2243 |
| 9534 | { PseudoVFNMADD_VFPR32_M8_E32, VFNMADD_VF, 0x3, 0x0 }, // 2244 |
| 9535 | { PseudoVFNMADD_VFPR32_M8_E32_MASK, VFNMADD_VF, 0x3, 0x0 }, // 2245 |
| 9536 | { PseudoVFNMADD_VFPR64_M8_E64, VFNMADD_VF, 0x3, 0x0 }, // 2246 |
| 9537 | { PseudoVFNMADD_VFPR64_M8_E64_MASK, VFNMADD_VF, 0x3, 0x0 }, // 2247 |
| 9538 | { PseudoVFNMADD_VFPR16_MF4_E16, VFNMADD_VF, 0x6, 0x0 }, // 2248 |
| 9539 | { PseudoVFNMADD_VFPR16_MF4_E16_MASK, VFNMADD_VF, 0x6, 0x0 }, // 2249 |
| 9540 | { PseudoVFNMADD_VFPR16_MF2_E16, VFNMADD_VF, 0x7, 0x0 }, // 2250 |
| 9541 | { PseudoVFNMADD_VFPR16_MF2_E16_MASK, VFNMADD_VF, 0x7, 0x0 }, // 2251 |
| 9542 | { PseudoVFNMADD_VFPR32_MF2_E32, VFNMADD_VF, 0x7, 0x0 }, // 2252 |
| 9543 | { PseudoVFNMADD_VFPR32_MF2_E32_MASK, VFNMADD_VF, 0x7, 0x0 }, // 2253 |
| 9544 | { PseudoVFNMADD_VV_M1_E16, VFNMADD_VV, 0x0, 0x0 }, // 2254 |
| 9545 | { PseudoVFNMADD_VV_M1_E16_MASK, VFNMADD_VV, 0x0, 0x0 }, // 2255 |
| 9546 | { PseudoVFNMADD_VV_M1_E32, VFNMADD_VV, 0x0, 0x0 }, // 2256 |
| 9547 | { PseudoVFNMADD_VV_M1_E32_MASK, VFNMADD_VV, 0x0, 0x0 }, // 2257 |
| 9548 | { PseudoVFNMADD_VV_M1_E64, VFNMADD_VV, 0x0, 0x0 }, // 2258 |
| 9549 | { PseudoVFNMADD_VV_M1_E64_MASK, VFNMADD_VV, 0x0, 0x0 }, // 2259 |
| 9550 | { PseudoVFNMADD_VV_M2_E16, VFNMADD_VV, 0x1, 0x0 }, // 2260 |
| 9551 | { PseudoVFNMADD_VV_M2_E16_MASK, VFNMADD_VV, 0x1, 0x0 }, // 2261 |
| 9552 | { PseudoVFNMADD_VV_M2_E32, VFNMADD_VV, 0x1, 0x0 }, // 2262 |
| 9553 | { PseudoVFNMADD_VV_M2_E32_MASK, VFNMADD_VV, 0x1, 0x0 }, // 2263 |
| 9554 | { PseudoVFNMADD_VV_M2_E64, VFNMADD_VV, 0x1, 0x0 }, // 2264 |
| 9555 | { PseudoVFNMADD_VV_M2_E64_MASK, VFNMADD_VV, 0x1, 0x0 }, // 2265 |
| 9556 | { PseudoVFNMADD_VV_M4_E16, VFNMADD_VV, 0x2, 0x0 }, // 2266 |
| 9557 | { PseudoVFNMADD_VV_M4_E16_MASK, VFNMADD_VV, 0x2, 0x0 }, // 2267 |
| 9558 | { PseudoVFNMADD_VV_M4_E32, VFNMADD_VV, 0x2, 0x0 }, // 2268 |
| 9559 | { PseudoVFNMADD_VV_M4_E32_MASK, VFNMADD_VV, 0x2, 0x0 }, // 2269 |
| 9560 | { PseudoVFNMADD_VV_M4_E64, VFNMADD_VV, 0x2, 0x0 }, // 2270 |
| 9561 | { PseudoVFNMADD_VV_M4_E64_MASK, VFNMADD_VV, 0x2, 0x0 }, // 2271 |
| 9562 | { PseudoVFNMADD_VV_M8_E16, VFNMADD_VV, 0x3, 0x0 }, // 2272 |
| 9563 | { PseudoVFNMADD_VV_M8_E16_MASK, VFNMADD_VV, 0x3, 0x0 }, // 2273 |
| 9564 | { PseudoVFNMADD_VV_M8_E32, VFNMADD_VV, 0x3, 0x0 }, // 2274 |
| 9565 | { PseudoVFNMADD_VV_M8_E32_MASK, VFNMADD_VV, 0x3, 0x0 }, // 2275 |
| 9566 | { PseudoVFNMADD_VV_M8_E64, VFNMADD_VV, 0x3, 0x0 }, // 2276 |
| 9567 | { PseudoVFNMADD_VV_M8_E64_MASK, VFNMADD_VV, 0x3, 0x0 }, // 2277 |
| 9568 | { PseudoVFNMADD_VV_MF4_E16, VFNMADD_VV, 0x6, 0x0 }, // 2278 |
| 9569 | { PseudoVFNMADD_VV_MF4_E16_MASK, VFNMADD_VV, 0x6, 0x0 }, // 2279 |
| 9570 | { PseudoVFNMADD_VV_MF2_E16, VFNMADD_VV, 0x7, 0x0 }, // 2280 |
| 9571 | { PseudoVFNMADD_VV_MF2_E16_MASK, VFNMADD_VV, 0x7, 0x0 }, // 2281 |
| 9572 | { PseudoVFNMADD_VV_MF2_E32, VFNMADD_VV, 0x7, 0x0 }, // 2282 |
| 9573 | { PseudoVFNMADD_VV_MF2_E32_MASK, VFNMADD_VV, 0x7, 0x0 }, // 2283 |
| 9574 | { PseudoVFNMSAC_VFPR16_M1_E16, VFNMSAC_VF, 0x0, 0x0 }, // 2284 |
| 9575 | { PseudoVFNMSAC_VFPR16_M1_E16_MASK, VFNMSAC_VF, 0x0, 0x0 }, // 2285 |
| 9576 | { PseudoVFNMSAC_VFPR32_M1_E32, VFNMSAC_VF, 0x0, 0x0 }, // 2286 |
| 9577 | { PseudoVFNMSAC_VFPR32_M1_E32_MASK, VFNMSAC_VF, 0x0, 0x0 }, // 2287 |
| 9578 | { PseudoVFNMSAC_VFPR64_M1_E64, VFNMSAC_VF, 0x0, 0x0 }, // 2288 |
| 9579 | { PseudoVFNMSAC_VFPR64_M1_E64_MASK, VFNMSAC_VF, 0x0, 0x0 }, // 2289 |
| 9580 | { PseudoVFNMSAC_VFPR16_M2_E16, VFNMSAC_VF, 0x1, 0x0 }, // 2290 |
| 9581 | { PseudoVFNMSAC_VFPR16_M2_E16_MASK, VFNMSAC_VF, 0x1, 0x0 }, // 2291 |
| 9582 | { PseudoVFNMSAC_VFPR32_M2_E32, VFNMSAC_VF, 0x1, 0x0 }, // 2292 |
| 9583 | { PseudoVFNMSAC_VFPR32_M2_E32_MASK, VFNMSAC_VF, 0x1, 0x0 }, // 2293 |
| 9584 | { PseudoVFNMSAC_VFPR64_M2_E64, VFNMSAC_VF, 0x1, 0x0 }, // 2294 |
| 9585 | { PseudoVFNMSAC_VFPR64_M2_E64_MASK, VFNMSAC_VF, 0x1, 0x0 }, // 2295 |
| 9586 | { PseudoVFNMSAC_VFPR16_M4_E16, VFNMSAC_VF, 0x2, 0x0 }, // 2296 |
| 9587 | { PseudoVFNMSAC_VFPR16_M4_E16_MASK, VFNMSAC_VF, 0x2, 0x0 }, // 2297 |
| 9588 | { PseudoVFNMSAC_VFPR32_M4_E32, VFNMSAC_VF, 0x2, 0x0 }, // 2298 |
| 9589 | { PseudoVFNMSAC_VFPR32_M4_E32_MASK, VFNMSAC_VF, 0x2, 0x0 }, // 2299 |
| 9590 | { PseudoVFNMSAC_VFPR64_M4_E64, VFNMSAC_VF, 0x2, 0x0 }, // 2300 |
| 9591 | { PseudoVFNMSAC_VFPR64_M4_E64_MASK, VFNMSAC_VF, 0x2, 0x0 }, // 2301 |
| 9592 | { PseudoVFNMSAC_VFPR16_M8_E16, VFNMSAC_VF, 0x3, 0x0 }, // 2302 |
| 9593 | { PseudoVFNMSAC_VFPR16_M8_E16_MASK, VFNMSAC_VF, 0x3, 0x0 }, // 2303 |
| 9594 | { PseudoVFNMSAC_VFPR32_M8_E32, VFNMSAC_VF, 0x3, 0x0 }, // 2304 |
| 9595 | { PseudoVFNMSAC_VFPR32_M8_E32_MASK, VFNMSAC_VF, 0x3, 0x0 }, // 2305 |
| 9596 | { PseudoVFNMSAC_VFPR64_M8_E64, VFNMSAC_VF, 0x3, 0x0 }, // 2306 |
| 9597 | { PseudoVFNMSAC_VFPR64_M8_E64_MASK, VFNMSAC_VF, 0x3, 0x0 }, // 2307 |
| 9598 | { PseudoVFNMSAC_VFPR16_MF4_E16, VFNMSAC_VF, 0x6, 0x0 }, // 2308 |
| 9599 | { PseudoVFNMSAC_VFPR16_MF4_E16_MASK, VFNMSAC_VF, 0x6, 0x0 }, // 2309 |
| 9600 | { PseudoVFNMSAC_VFPR16_MF2_E16, VFNMSAC_VF, 0x7, 0x0 }, // 2310 |
| 9601 | { PseudoVFNMSAC_VFPR16_MF2_E16_MASK, VFNMSAC_VF, 0x7, 0x0 }, // 2311 |
| 9602 | { PseudoVFNMSAC_VFPR32_MF2_E32, VFNMSAC_VF, 0x7, 0x0 }, // 2312 |
| 9603 | { PseudoVFNMSAC_VFPR32_MF2_E32_MASK, VFNMSAC_VF, 0x7, 0x0 }, // 2313 |
| 9604 | { PseudoVFNMSAC_VV_M1_E16, VFNMSAC_VV, 0x0, 0x0 }, // 2314 |
| 9605 | { PseudoVFNMSAC_VV_M1_E16_MASK, VFNMSAC_VV, 0x0, 0x0 }, // 2315 |
| 9606 | { PseudoVFNMSAC_VV_M1_E32, VFNMSAC_VV, 0x0, 0x0 }, // 2316 |
| 9607 | { PseudoVFNMSAC_VV_M1_E32_MASK, VFNMSAC_VV, 0x0, 0x0 }, // 2317 |
| 9608 | { PseudoVFNMSAC_VV_M1_E64, VFNMSAC_VV, 0x0, 0x0 }, // 2318 |
| 9609 | { PseudoVFNMSAC_VV_M1_E64_MASK, VFNMSAC_VV, 0x0, 0x0 }, // 2319 |
| 9610 | { PseudoVFNMSAC_VV_M2_E16, VFNMSAC_VV, 0x1, 0x0 }, // 2320 |
| 9611 | { PseudoVFNMSAC_VV_M2_E16_MASK, VFNMSAC_VV, 0x1, 0x0 }, // 2321 |
| 9612 | { PseudoVFNMSAC_VV_M2_E32, VFNMSAC_VV, 0x1, 0x0 }, // 2322 |
| 9613 | { PseudoVFNMSAC_VV_M2_E32_MASK, VFNMSAC_VV, 0x1, 0x0 }, // 2323 |
| 9614 | { PseudoVFNMSAC_VV_M2_E64, VFNMSAC_VV, 0x1, 0x0 }, // 2324 |
| 9615 | { PseudoVFNMSAC_VV_M2_E64_MASK, VFNMSAC_VV, 0x1, 0x0 }, // 2325 |
| 9616 | { PseudoVFNMSAC_VV_M4_E16, VFNMSAC_VV, 0x2, 0x0 }, // 2326 |
| 9617 | { PseudoVFNMSAC_VV_M4_E16_MASK, VFNMSAC_VV, 0x2, 0x0 }, // 2327 |
| 9618 | { PseudoVFNMSAC_VV_M4_E32, VFNMSAC_VV, 0x2, 0x0 }, // 2328 |
| 9619 | { PseudoVFNMSAC_VV_M4_E32_MASK, VFNMSAC_VV, 0x2, 0x0 }, // 2329 |
| 9620 | { PseudoVFNMSAC_VV_M4_E64, VFNMSAC_VV, 0x2, 0x0 }, // 2330 |
| 9621 | { PseudoVFNMSAC_VV_M4_E64_MASK, VFNMSAC_VV, 0x2, 0x0 }, // 2331 |
| 9622 | { PseudoVFNMSAC_VV_M8_E16, VFNMSAC_VV, 0x3, 0x0 }, // 2332 |
| 9623 | { PseudoVFNMSAC_VV_M8_E16_MASK, VFNMSAC_VV, 0x3, 0x0 }, // 2333 |
| 9624 | { PseudoVFNMSAC_VV_M8_E32, VFNMSAC_VV, 0x3, 0x0 }, // 2334 |
| 9625 | { PseudoVFNMSAC_VV_M8_E32_MASK, VFNMSAC_VV, 0x3, 0x0 }, // 2335 |
| 9626 | { PseudoVFNMSAC_VV_M8_E64, VFNMSAC_VV, 0x3, 0x0 }, // 2336 |
| 9627 | { PseudoVFNMSAC_VV_M8_E64_MASK, VFNMSAC_VV, 0x3, 0x0 }, // 2337 |
| 9628 | { PseudoVFNMSAC_VV_MF4_E16, VFNMSAC_VV, 0x6, 0x0 }, // 2338 |
| 9629 | { PseudoVFNMSAC_VV_MF4_E16_MASK, VFNMSAC_VV, 0x6, 0x0 }, // 2339 |
| 9630 | { PseudoVFNMSAC_VV_MF2_E16, VFNMSAC_VV, 0x7, 0x0 }, // 2340 |
| 9631 | { PseudoVFNMSAC_VV_MF2_E16_MASK, VFNMSAC_VV, 0x7, 0x0 }, // 2341 |
| 9632 | { PseudoVFNMSAC_VV_MF2_E32, VFNMSAC_VV, 0x7, 0x0 }, // 2342 |
| 9633 | { PseudoVFNMSAC_VV_MF2_E32_MASK, VFNMSAC_VV, 0x7, 0x0 }, // 2343 |
| 9634 | { PseudoVFNMSUB_VFPR16_M1_E16, VFNMSUB_VF, 0x0, 0x0 }, // 2344 |
| 9635 | { PseudoVFNMSUB_VFPR16_M1_E16_MASK, VFNMSUB_VF, 0x0, 0x0 }, // 2345 |
| 9636 | { PseudoVFNMSUB_VFPR32_M1_E32, VFNMSUB_VF, 0x0, 0x0 }, // 2346 |
| 9637 | { PseudoVFNMSUB_VFPR32_M1_E32_MASK, VFNMSUB_VF, 0x0, 0x0 }, // 2347 |
| 9638 | { PseudoVFNMSUB_VFPR64_M1_E64, VFNMSUB_VF, 0x0, 0x0 }, // 2348 |
| 9639 | { PseudoVFNMSUB_VFPR64_M1_E64_MASK, VFNMSUB_VF, 0x0, 0x0 }, // 2349 |
| 9640 | { PseudoVFNMSUB_VFPR16_M2_E16, VFNMSUB_VF, 0x1, 0x0 }, // 2350 |
| 9641 | { PseudoVFNMSUB_VFPR16_M2_E16_MASK, VFNMSUB_VF, 0x1, 0x0 }, // 2351 |
| 9642 | { PseudoVFNMSUB_VFPR32_M2_E32, VFNMSUB_VF, 0x1, 0x0 }, // 2352 |
| 9643 | { PseudoVFNMSUB_VFPR32_M2_E32_MASK, VFNMSUB_VF, 0x1, 0x0 }, // 2353 |
| 9644 | { PseudoVFNMSUB_VFPR64_M2_E64, VFNMSUB_VF, 0x1, 0x0 }, // 2354 |
| 9645 | { PseudoVFNMSUB_VFPR64_M2_E64_MASK, VFNMSUB_VF, 0x1, 0x0 }, // 2355 |
| 9646 | { PseudoVFNMSUB_VFPR16_M4_E16, VFNMSUB_VF, 0x2, 0x0 }, // 2356 |
| 9647 | { PseudoVFNMSUB_VFPR16_M4_E16_MASK, VFNMSUB_VF, 0x2, 0x0 }, // 2357 |
| 9648 | { PseudoVFNMSUB_VFPR32_M4_E32, VFNMSUB_VF, 0x2, 0x0 }, // 2358 |
| 9649 | { PseudoVFNMSUB_VFPR32_M4_E32_MASK, VFNMSUB_VF, 0x2, 0x0 }, // 2359 |
| 9650 | { PseudoVFNMSUB_VFPR64_M4_E64, VFNMSUB_VF, 0x2, 0x0 }, // 2360 |
| 9651 | { PseudoVFNMSUB_VFPR64_M4_E64_MASK, VFNMSUB_VF, 0x2, 0x0 }, // 2361 |
| 9652 | { PseudoVFNMSUB_VFPR16_M8_E16, VFNMSUB_VF, 0x3, 0x0 }, // 2362 |
| 9653 | { PseudoVFNMSUB_VFPR16_M8_E16_MASK, VFNMSUB_VF, 0x3, 0x0 }, // 2363 |
| 9654 | { PseudoVFNMSUB_VFPR32_M8_E32, VFNMSUB_VF, 0x3, 0x0 }, // 2364 |
| 9655 | { PseudoVFNMSUB_VFPR32_M8_E32_MASK, VFNMSUB_VF, 0x3, 0x0 }, // 2365 |
| 9656 | { PseudoVFNMSUB_VFPR64_M8_E64, VFNMSUB_VF, 0x3, 0x0 }, // 2366 |
| 9657 | { PseudoVFNMSUB_VFPR64_M8_E64_MASK, VFNMSUB_VF, 0x3, 0x0 }, // 2367 |
| 9658 | { PseudoVFNMSUB_VFPR16_MF4_E16, VFNMSUB_VF, 0x6, 0x0 }, // 2368 |
| 9659 | { PseudoVFNMSUB_VFPR16_MF4_E16_MASK, VFNMSUB_VF, 0x6, 0x0 }, // 2369 |
| 9660 | { PseudoVFNMSUB_VFPR16_MF2_E16, VFNMSUB_VF, 0x7, 0x0 }, // 2370 |
| 9661 | { PseudoVFNMSUB_VFPR16_MF2_E16_MASK, VFNMSUB_VF, 0x7, 0x0 }, // 2371 |
| 9662 | { PseudoVFNMSUB_VFPR32_MF2_E32, VFNMSUB_VF, 0x7, 0x0 }, // 2372 |
| 9663 | { PseudoVFNMSUB_VFPR32_MF2_E32_MASK, VFNMSUB_VF, 0x7, 0x0 }, // 2373 |
| 9664 | { PseudoVFNMSUB_VV_M1_E16, VFNMSUB_VV, 0x0, 0x0 }, // 2374 |
| 9665 | { PseudoVFNMSUB_VV_M1_E16_MASK, VFNMSUB_VV, 0x0, 0x0 }, // 2375 |
| 9666 | { PseudoVFNMSUB_VV_M1_E32, VFNMSUB_VV, 0x0, 0x0 }, // 2376 |
| 9667 | { PseudoVFNMSUB_VV_M1_E32_MASK, VFNMSUB_VV, 0x0, 0x0 }, // 2377 |
| 9668 | { PseudoVFNMSUB_VV_M1_E64, VFNMSUB_VV, 0x0, 0x0 }, // 2378 |
| 9669 | { PseudoVFNMSUB_VV_M1_E64_MASK, VFNMSUB_VV, 0x0, 0x0 }, // 2379 |
| 9670 | { PseudoVFNMSUB_VV_M2_E16, VFNMSUB_VV, 0x1, 0x0 }, // 2380 |
| 9671 | { PseudoVFNMSUB_VV_M2_E16_MASK, VFNMSUB_VV, 0x1, 0x0 }, // 2381 |
| 9672 | { PseudoVFNMSUB_VV_M2_E32, VFNMSUB_VV, 0x1, 0x0 }, // 2382 |
| 9673 | { PseudoVFNMSUB_VV_M2_E32_MASK, VFNMSUB_VV, 0x1, 0x0 }, // 2383 |
| 9674 | { PseudoVFNMSUB_VV_M2_E64, VFNMSUB_VV, 0x1, 0x0 }, // 2384 |
| 9675 | { PseudoVFNMSUB_VV_M2_E64_MASK, VFNMSUB_VV, 0x1, 0x0 }, // 2385 |
| 9676 | { PseudoVFNMSUB_VV_M4_E16, VFNMSUB_VV, 0x2, 0x0 }, // 2386 |
| 9677 | { PseudoVFNMSUB_VV_M4_E16_MASK, VFNMSUB_VV, 0x2, 0x0 }, // 2387 |
| 9678 | { PseudoVFNMSUB_VV_M4_E32, VFNMSUB_VV, 0x2, 0x0 }, // 2388 |
| 9679 | { PseudoVFNMSUB_VV_M4_E32_MASK, VFNMSUB_VV, 0x2, 0x0 }, // 2389 |
| 9680 | { PseudoVFNMSUB_VV_M4_E64, VFNMSUB_VV, 0x2, 0x0 }, // 2390 |
| 9681 | { PseudoVFNMSUB_VV_M4_E64_MASK, VFNMSUB_VV, 0x2, 0x0 }, // 2391 |
| 9682 | { PseudoVFNMSUB_VV_M8_E16, VFNMSUB_VV, 0x3, 0x0 }, // 2392 |
| 9683 | { PseudoVFNMSUB_VV_M8_E16_MASK, VFNMSUB_VV, 0x3, 0x0 }, // 2393 |
| 9684 | { PseudoVFNMSUB_VV_M8_E32, VFNMSUB_VV, 0x3, 0x0 }, // 2394 |
| 9685 | { PseudoVFNMSUB_VV_M8_E32_MASK, VFNMSUB_VV, 0x3, 0x0 }, // 2395 |
| 9686 | { PseudoVFNMSUB_VV_M8_E64, VFNMSUB_VV, 0x3, 0x0 }, // 2396 |
| 9687 | { PseudoVFNMSUB_VV_M8_E64_MASK, VFNMSUB_VV, 0x3, 0x0 }, // 2397 |
| 9688 | { PseudoVFNMSUB_VV_MF4_E16, VFNMSUB_VV, 0x6, 0x0 }, // 2398 |
| 9689 | { PseudoVFNMSUB_VV_MF4_E16_MASK, VFNMSUB_VV, 0x6, 0x0 }, // 2399 |
| 9690 | { PseudoVFNMSUB_VV_MF2_E16, VFNMSUB_VV, 0x7, 0x0 }, // 2400 |
| 9691 | { PseudoVFNMSUB_VV_MF2_E16_MASK, VFNMSUB_VV, 0x7, 0x0 }, // 2401 |
| 9692 | { PseudoVFNMSUB_VV_MF2_E32, VFNMSUB_VV, 0x7, 0x0 }, // 2402 |
| 9693 | { PseudoVFNMSUB_VV_MF2_E32_MASK, VFNMSUB_VV, 0x7, 0x0 }, // 2403 |
| 9694 | { PseudoVFNRCLIP_XU_F_QF_M1, VFNRCLIP_XU_F_QF, 0x0, 0x0 }, // 2404 |
| 9695 | { PseudoVFNRCLIP_XU_F_QF_M1_MASK, VFNRCLIP_XU_F_QF, 0x0, 0x0 }, // 2405 |
| 9696 | { PseudoVFNRCLIP_XU_F_QF_M2, VFNRCLIP_XU_F_QF, 0x1, 0x0 }, // 2406 |
| 9697 | { PseudoVFNRCLIP_XU_F_QF_M2_MASK, VFNRCLIP_XU_F_QF, 0x1, 0x0 }, // 2407 |
| 9698 | { PseudoVFNRCLIP_XU_F_QF_MF8, VFNRCLIP_XU_F_QF, 0x5, 0x0 }, // 2408 |
| 9699 | { PseudoVFNRCLIP_XU_F_QF_MF8_MASK, VFNRCLIP_XU_F_QF, 0x5, 0x0 }, // 2409 |
| 9700 | { PseudoVFNRCLIP_XU_F_QF_MF4, VFNRCLIP_XU_F_QF, 0x6, 0x0 }, // 2410 |
| 9701 | { PseudoVFNRCLIP_XU_F_QF_MF4_MASK, VFNRCLIP_XU_F_QF, 0x6, 0x0 }, // 2411 |
| 9702 | { PseudoVFNRCLIP_XU_F_QF_MF2, VFNRCLIP_XU_F_QF, 0x7, 0x0 }, // 2412 |
| 9703 | { PseudoVFNRCLIP_XU_F_QF_MF2_MASK, VFNRCLIP_XU_F_QF, 0x7, 0x0 }, // 2413 |
| 9704 | { PseudoVFNRCLIP_X_F_QF_M1, VFNRCLIP_X_F_QF, 0x0, 0x0 }, // 2414 |
| 9705 | { PseudoVFNRCLIP_X_F_QF_M1_MASK, VFNRCLIP_X_F_QF, 0x0, 0x0 }, // 2415 |
| 9706 | { PseudoVFNRCLIP_X_F_QF_M2, VFNRCLIP_X_F_QF, 0x1, 0x0 }, // 2416 |
| 9707 | { PseudoVFNRCLIP_X_F_QF_M2_MASK, VFNRCLIP_X_F_QF, 0x1, 0x0 }, // 2417 |
| 9708 | { PseudoVFNRCLIP_X_F_QF_MF8, VFNRCLIP_X_F_QF, 0x5, 0x0 }, // 2418 |
| 9709 | { PseudoVFNRCLIP_X_F_QF_MF8_MASK, VFNRCLIP_X_F_QF, 0x5, 0x0 }, // 2419 |
| 9710 | { PseudoVFNRCLIP_X_F_QF_MF4, VFNRCLIP_X_F_QF, 0x6, 0x0 }, // 2420 |
| 9711 | { PseudoVFNRCLIP_X_F_QF_MF4_MASK, VFNRCLIP_X_F_QF, 0x6, 0x0 }, // 2421 |
| 9712 | { PseudoVFNRCLIP_X_F_QF_MF2, VFNRCLIP_X_F_QF, 0x7, 0x0 }, // 2422 |
| 9713 | { PseudoVFNRCLIP_X_F_QF_MF2_MASK, VFNRCLIP_X_F_QF, 0x7, 0x0 }, // 2423 |
| 9714 | { PseudoVFRDIV_VFPR16_M1_E16, VFRDIV_VF, 0x0, 0x10 }, // 2424 |
| 9715 | { PseudoVFRDIV_VFPR16_M1_E16_MASK, VFRDIV_VF, 0x0, 0x10 }, // 2425 |
| 9716 | { PseudoVFRDIV_VFPR32_M1_E32, VFRDIV_VF, 0x0, 0x20 }, // 2426 |
| 9717 | { PseudoVFRDIV_VFPR32_M1_E32_MASK, VFRDIV_VF, 0x0, 0x20 }, // 2427 |
| 9718 | { PseudoVFRDIV_VFPR64_M1_E64, VFRDIV_VF, 0x0, 0x40 }, // 2428 |
| 9719 | { PseudoVFRDIV_VFPR64_M1_E64_MASK, VFRDIV_VF, 0x0, 0x40 }, // 2429 |
| 9720 | { PseudoVFRDIV_VFPR16_M2_E16, VFRDIV_VF, 0x1, 0x10 }, // 2430 |
| 9721 | { PseudoVFRDIV_VFPR16_M2_E16_MASK, VFRDIV_VF, 0x1, 0x10 }, // 2431 |
| 9722 | { PseudoVFRDIV_VFPR32_M2_E32, VFRDIV_VF, 0x1, 0x20 }, // 2432 |
| 9723 | { PseudoVFRDIV_VFPR32_M2_E32_MASK, VFRDIV_VF, 0x1, 0x20 }, // 2433 |
| 9724 | { PseudoVFRDIV_VFPR64_M2_E64, VFRDIV_VF, 0x1, 0x40 }, // 2434 |
| 9725 | { PseudoVFRDIV_VFPR64_M2_E64_MASK, VFRDIV_VF, 0x1, 0x40 }, // 2435 |
| 9726 | { PseudoVFRDIV_VFPR16_M4_E16, VFRDIV_VF, 0x2, 0x10 }, // 2436 |
| 9727 | { PseudoVFRDIV_VFPR16_M4_E16_MASK, VFRDIV_VF, 0x2, 0x10 }, // 2437 |
| 9728 | { PseudoVFRDIV_VFPR32_M4_E32, VFRDIV_VF, 0x2, 0x20 }, // 2438 |
| 9729 | { PseudoVFRDIV_VFPR32_M4_E32_MASK, VFRDIV_VF, 0x2, 0x20 }, // 2439 |
| 9730 | { PseudoVFRDIV_VFPR64_M4_E64, VFRDIV_VF, 0x2, 0x40 }, // 2440 |
| 9731 | { PseudoVFRDIV_VFPR64_M4_E64_MASK, VFRDIV_VF, 0x2, 0x40 }, // 2441 |
| 9732 | { PseudoVFRDIV_VFPR16_M8_E16, VFRDIV_VF, 0x3, 0x10 }, // 2442 |
| 9733 | { PseudoVFRDIV_VFPR16_M8_E16_MASK, VFRDIV_VF, 0x3, 0x10 }, // 2443 |
| 9734 | { PseudoVFRDIV_VFPR32_M8_E32, VFRDIV_VF, 0x3, 0x20 }, // 2444 |
| 9735 | { PseudoVFRDIV_VFPR32_M8_E32_MASK, VFRDIV_VF, 0x3, 0x20 }, // 2445 |
| 9736 | { PseudoVFRDIV_VFPR64_M8_E64, VFRDIV_VF, 0x3, 0x40 }, // 2446 |
| 9737 | { PseudoVFRDIV_VFPR64_M8_E64_MASK, VFRDIV_VF, 0x3, 0x40 }, // 2447 |
| 9738 | { PseudoVFRDIV_VFPR16_MF4_E16, VFRDIV_VF, 0x6, 0x10 }, // 2448 |
| 9739 | { PseudoVFRDIV_VFPR16_MF4_E16_MASK, VFRDIV_VF, 0x6, 0x10 }, // 2449 |
| 9740 | { PseudoVFRDIV_VFPR16_MF2_E16, VFRDIV_VF, 0x7, 0x10 }, // 2450 |
| 9741 | { PseudoVFRDIV_VFPR16_MF2_E16_MASK, VFRDIV_VF, 0x7, 0x10 }, // 2451 |
| 9742 | { PseudoVFRDIV_VFPR32_MF2_E32, VFRDIV_VF, 0x7, 0x20 }, // 2452 |
| 9743 | { PseudoVFRDIV_VFPR32_MF2_E32_MASK, VFRDIV_VF, 0x7, 0x20 }, // 2453 |
| 9744 | { PseudoVFREC7_V_M1_E16, VFREC7_V, 0x0, 0x0 }, // 2454 |
| 9745 | { PseudoVFREC7_V_M1_E16_MASK, VFREC7_V, 0x0, 0x0 }, // 2455 |
| 9746 | { PseudoVFREC7_V_M1_E32, VFREC7_V, 0x0, 0x0 }, // 2456 |
| 9747 | { PseudoVFREC7_V_M1_E32_MASK, VFREC7_V, 0x0, 0x0 }, // 2457 |
| 9748 | { PseudoVFREC7_V_M1_E64, VFREC7_V, 0x0, 0x0 }, // 2458 |
| 9749 | { PseudoVFREC7_V_M1_E64_MASK, VFREC7_V, 0x0, 0x0 }, // 2459 |
| 9750 | { PseudoVFREC7_V_M2_E16, VFREC7_V, 0x1, 0x0 }, // 2460 |
| 9751 | { PseudoVFREC7_V_M2_E16_MASK, VFREC7_V, 0x1, 0x0 }, // 2461 |
| 9752 | { PseudoVFREC7_V_M2_E32, VFREC7_V, 0x1, 0x0 }, // 2462 |
| 9753 | { PseudoVFREC7_V_M2_E32_MASK, VFREC7_V, 0x1, 0x0 }, // 2463 |
| 9754 | { PseudoVFREC7_V_M2_E64, VFREC7_V, 0x1, 0x0 }, // 2464 |
| 9755 | { PseudoVFREC7_V_M2_E64_MASK, VFREC7_V, 0x1, 0x0 }, // 2465 |
| 9756 | { PseudoVFREC7_V_M4_E16, VFREC7_V, 0x2, 0x0 }, // 2466 |
| 9757 | { PseudoVFREC7_V_M4_E16_MASK, VFREC7_V, 0x2, 0x0 }, // 2467 |
| 9758 | { PseudoVFREC7_V_M4_E32, VFREC7_V, 0x2, 0x0 }, // 2468 |
| 9759 | { PseudoVFREC7_V_M4_E32_MASK, VFREC7_V, 0x2, 0x0 }, // 2469 |
| 9760 | { PseudoVFREC7_V_M4_E64, VFREC7_V, 0x2, 0x0 }, // 2470 |
| 9761 | { PseudoVFREC7_V_M4_E64_MASK, VFREC7_V, 0x2, 0x0 }, // 2471 |
| 9762 | { PseudoVFREC7_V_M8_E16, VFREC7_V, 0x3, 0x0 }, // 2472 |
| 9763 | { PseudoVFREC7_V_M8_E16_MASK, VFREC7_V, 0x3, 0x0 }, // 2473 |
| 9764 | { PseudoVFREC7_V_M8_E32, VFREC7_V, 0x3, 0x0 }, // 2474 |
| 9765 | { PseudoVFREC7_V_M8_E32_MASK, VFREC7_V, 0x3, 0x0 }, // 2475 |
| 9766 | { PseudoVFREC7_V_M8_E64, VFREC7_V, 0x3, 0x0 }, // 2476 |
| 9767 | { PseudoVFREC7_V_M8_E64_MASK, VFREC7_V, 0x3, 0x0 }, // 2477 |
| 9768 | { PseudoVFREC7_V_MF4_E16, VFREC7_V, 0x6, 0x0 }, // 2478 |
| 9769 | { PseudoVFREC7_V_MF4_E16_MASK, VFREC7_V, 0x6, 0x0 }, // 2479 |
| 9770 | { PseudoVFREC7_V_MF2_E16, VFREC7_V, 0x7, 0x0 }, // 2480 |
| 9771 | { PseudoVFREC7_V_MF2_E16_MASK, VFREC7_V, 0x7, 0x0 }, // 2481 |
| 9772 | { PseudoVFREC7_V_MF2_E32, VFREC7_V, 0x7, 0x0 }, // 2482 |
| 9773 | { PseudoVFREC7_V_MF2_E32_MASK, VFREC7_V, 0x7, 0x0 }, // 2483 |
| 9774 | { PseudoVFREDMAX_VS_M1_E16, VFREDMAX_VS, 0x0, 0x10 }, // 2484 |
| 9775 | { PseudoVFREDMAX_VS_M1_E16_MASK, VFREDMAX_VS, 0x0, 0x10 }, // 2485 |
| 9776 | { PseudoVFREDMAX_VS_M1_E32, VFREDMAX_VS, 0x0, 0x20 }, // 2486 |
| 9777 | { PseudoVFREDMAX_VS_M1_E32_MASK, VFREDMAX_VS, 0x0, 0x20 }, // 2487 |
| 9778 | { PseudoVFREDMAX_VS_M1_E64, VFREDMAX_VS, 0x0, 0x40 }, // 2488 |
| 9779 | { PseudoVFREDMAX_VS_M1_E64_MASK, VFREDMAX_VS, 0x0, 0x40 }, // 2489 |
| 9780 | { PseudoVFREDMAX_VS_M2_E16, VFREDMAX_VS, 0x1, 0x10 }, // 2490 |
| 9781 | { PseudoVFREDMAX_VS_M2_E16_MASK, VFREDMAX_VS, 0x1, 0x10 }, // 2491 |
| 9782 | { PseudoVFREDMAX_VS_M2_E32, VFREDMAX_VS, 0x1, 0x20 }, // 2492 |
| 9783 | { PseudoVFREDMAX_VS_M2_E32_MASK, VFREDMAX_VS, 0x1, 0x20 }, // 2493 |
| 9784 | { PseudoVFREDMAX_VS_M2_E64, VFREDMAX_VS, 0x1, 0x40 }, // 2494 |
| 9785 | { PseudoVFREDMAX_VS_M2_E64_MASK, VFREDMAX_VS, 0x1, 0x40 }, // 2495 |
| 9786 | { PseudoVFREDMAX_VS_M4_E16, VFREDMAX_VS, 0x2, 0x10 }, // 2496 |
| 9787 | { PseudoVFREDMAX_VS_M4_E16_MASK, VFREDMAX_VS, 0x2, 0x10 }, // 2497 |
| 9788 | { PseudoVFREDMAX_VS_M4_E32, VFREDMAX_VS, 0x2, 0x20 }, // 2498 |
| 9789 | { PseudoVFREDMAX_VS_M4_E32_MASK, VFREDMAX_VS, 0x2, 0x20 }, // 2499 |
| 9790 | { PseudoVFREDMAX_VS_M4_E64, VFREDMAX_VS, 0x2, 0x40 }, // 2500 |
| 9791 | { PseudoVFREDMAX_VS_M4_E64_MASK, VFREDMAX_VS, 0x2, 0x40 }, // 2501 |
| 9792 | { PseudoVFREDMAX_VS_M8_E16, VFREDMAX_VS, 0x3, 0x10 }, // 2502 |
| 9793 | { PseudoVFREDMAX_VS_M8_E16_MASK, VFREDMAX_VS, 0x3, 0x10 }, // 2503 |
| 9794 | { PseudoVFREDMAX_VS_M8_E32, VFREDMAX_VS, 0x3, 0x20 }, // 2504 |
| 9795 | { PseudoVFREDMAX_VS_M8_E32_MASK, VFREDMAX_VS, 0x3, 0x20 }, // 2505 |
| 9796 | { PseudoVFREDMAX_VS_M8_E64, VFREDMAX_VS, 0x3, 0x40 }, // 2506 |
| 9797 | { PseudoVFREDMAX_VS_M8_E64_MASK, VFREDMAX_VS, 0x3, 0x40 }, // 2507 |
| 9798 | { PseudoVFREDMAX_VS_MF4_E16, VFREDMAX_VS, 0x6, 0x10 }, // 2508 |
| 9799 | { PseudoVFREDMAX_VS_MF4_E16_MASK, VFREDMAX_VS, 0x6, 0x10 }, // 2509 |
| 9800 | { PseudoVFREDMAX_VS_MF2_E16, VFREDMAX_VS, 0x7, 0x10 }, // 2510 |
| 9801 | { PseudoVFREDMAX_VS_MF2_E16_MASK, VFREDMAX_VS, 0x7, 0x10 }, // 2511 |
| 9802 | { PseudoVFREDMAX_VS_MF2_E32, VFREDMAX_VS, 0x7, 0x20 }, // 2512 |
| 9803 | { PseudoVFREDMAX_VS_MF2_E32_MASK, VFREDMAX_VS, 0x7, 0x20 }, // 2513 |
| 9804 | { PseudoVFREDMIN_VS_M1_E16, VFREDMIN_VS, 0x0, 0x10 }, // 2514 |
| 9805 | { PseudoVFREDMIN_VS_M1_E16_MASK, VFREDMIN_VS, 0x0, 0x10 }, // 2515 |
| 9806 | { PseudoVFREDMIN_VS_M1_E32, VFREDMIN_VS, 0x0, 0x20 }, // 2516 |
| 9807 | { PseudoVFREDMIN_VS_M1_E32_MASK, VFREDMIN_VS, 0x0, 0x20 }, // 2517 |
| 9808 | { PseudoVFREDMIN_VS_M1_E64, VFREDMIN_VS, 0x0, 0x40 }, // 2518 |
| 9809 | { PseudoVFREDMIN_VS_M1_E64_MASK, VFREDMIN_VS, 0x0, 0x40 }, // 2519 |
| 9810 | { PseudoVFREDMIN_VS_M2_E16, VFREDMIN_VS, 0x1, 0x10 }, // 2520 |
| 9811 | { PseudoVFREDMIN_VS_M2_E16_MASK, VFREDMIN_VS, 0x1, 0x10 }, // 2521 |
| 9812 | { PseudoVFREDMIN_VS_M2_E32, VFREDMIN_VS, 0x1, 0x20 }, // 2522 |
| 9813 | { PseudoVFREDMIN_VS_M2_E32_MASK, VFREDMIN_VS, 0x1, 0x20 }, // 2523 |
| 9814 | { PseudoVFREDMIN_VS_M2_E64, VFREDMIN_VS, 0x1, 0x40 }, // 2524 |
| 9815 | { PseudoVFREDMIN_VS_M2_E64_MASK, VFREDMIN_VS, 0x1, 0x40 }, // 2525 |
| 9816 | { PseudoVFREDMIN_VS_M4_E16, VFREDMIN_VS, 0x2, 0x10 }, // 2526 |
| 9817 | { PseudoVFREDMIN_VS_M4_E16_MASK, VFREDMIN_VS, 0x2, 0x10 }, // 2527 |
| 9818 | { PseudoVFREDMIN_VS_M4_E32, VFREDMIN_VS, 0x2, 0x20 }, // 2528 |
| 9819 | { PseudoVFREDMIN_VS_M4_E32_MASK, VFREDMIN_VS, 0x2, 0x20 }, // 2529 |
| 9820 | { PseudoVFREDMIN_VS_M4_E64, VFREDMIN_VS, 0x2, 0x40 }, // 2530 |
| 9821 | { PseudoVFREDMIN_VS_M4_E64_MASK, VFREDMIN_VS, 0x2, 0x40 }, // 2531 |
| 9822 | { PseudoVFREDMIN_VS_M8_E16, VFREDMIN_VS, 0x3, 0x10 }, // 2532 |
| 9823 | { PseudoVFREDMIN_VS_M8_E16_MASK, VFREDMIN_VS, 0x3, 0x10 }, // 2533 |
| 9824 | { PseudoVFREDMIN_VS_M8_E32, VFREDMIN_VS, 0x3, 0x20 }, // 2534 |
| 9825 | { PseudoVFREDMIN_VS_M8_E32_MASK, VFREDMIN_VS, 0x3, 0x20 }, // 2535 |
| 9826 | { PseudoVFREDMIN_VS_M8_E64, VFREDMIN_VS, 0x3, 0x40 }, // 2536 |
| 9827 | { PseudoVFREDMIN_VS_M8_E64_MASK, VFREDMIN_VS, 0x3, 0x40 }, // 2537 |
| 9828 | { PseudoVFREDMIN_VS_MF4_E16, VFREDMIN_VS, 0x6, 0x10 }, // 2538 |
| 9829 | { PseudoVFREDMIN_VS_MF4_E16_MASK, VFREDMIN_VS, 0x6, 0x10 }, // 2539 |
| 9830 | { PseudoVFREDMIN_VS_MF2_E16, VFREDMIN_VS, 0x7, 0x10 }, // 2540 |
| 9831 | { PseudoVFREDMIN_VS_MF2_E16_MASK, VFREDMIN_VS, 0x7, 0x10 }, // 2541 |
| 9832 | { PseudoVFREDMIN_VS_MF2_E32, VFREDMIN_VS, 0x7, 0x20 }, // 2542 |
| 9833 | { PseudoVFREDMIN_VS_MF2_E32_MASK, VFREDMIN_VS, 0x7, 0x20 }, // 2543 |
| 9834 | { PseudoVFREDOSUM_VS_M1_E16, VFREDOSUM_VS, 0x0, 0x10 }, // 2544 |
| 9835 | { PseudoVFREDOSUM_VS_M1_E16_MASK, VFREDOSUM_VS, 0x0, 0x10 }, // 2545 |
| 9836 | { PseudoVFREDOSUM_VS_M1_E32, VFREDOSUM_VS, 0x0, 0x20 }, // 2546 |
| 9837 | { PseudoVFREDOSUM_VS_M1_E32_MASK, VFREDOSUM_VS, 0x0, 0x20 }, // 2547 |
| 9838 | { PseudoVFREDOSUM_VS_M1_E64, VFREDOSUM_VS, 0x0, 0x40 }, // 2548 |
| 9839 | { PseudoVFREDOSUM_VS_M1_E64_MASK, VFREDOSUM_VS, 0x0, 0x40 }, // 2549 |
| 9840 | { PseudoVFREDOSUM_VS_M2_E16, VFREDOSUM_VS, 0x1, 0x10 }, // 2550 |
| 9841 | { PseudoVFREDOSUM_VS_M2_E16_MASK, VFREDOSUM_VS, 0x1, 0x10 }, // 2551 |
| 9842 | { PseudoVFREDOSUM_VS_M2_E32, VFREDOSUM_VS, 0x1, 0x20 }, // 2552 |
| 9843 | { PseudoVFREDOSUM_VS_M2_E32_MASK, VFREDOSUM_VS, 0x1, 0x20 }, // 2553 |
| 9844 | { PseudoVFREDOSUM_VS_M2_E64, VFREDOSUM_VS, 0x1, 0x40 }, // 2554 |
| 9845 | { PseudoVFREDOSUM_VS_M2_E64_MASK, VFREDOSUM_VS, 0x1, 0x40 }, // 2555 |
| 9846 | { PseudoVFREDOSUM_VS_M4_E16, VFREDOSUM_VS, 0x2, 0x10 }, // 2556 |
| 9847 | { PseudoVFREDOSUM_VS_M4_E16_MASK, VFREDOSUM_VS, 0x2, 0x10 }, // 2557 |
| 9848 | { PseudoVFREDOSUM_VS_M4_E32, VFREDOSUM_VS, 0x2, 0x20 }, // 2558 |
| 9849 | { PseudoVFREDOSUM_VS_M4_E32_MASK, VFREDOSUM_VS, 0x2, 0x20 }, // 2559 |
| 9850 | { PseudoVFREDOSUM_VS_M4_E64, VFREDOSUM_VS, 0x2, 0x40 }, // 2560 |
| 9851 | { PseudoVFREDOSUM_VS_M4_E64_MASK, VFREDOSUM_VS, 0x2, 0x40 }, // 2561 |
| 9852 | { PseudoVFREDOSUM_VS_M8_E16, VFREDOSUM_VS, 0x3, 0x10 }, // 2562 |
| 9853 | { PseudoVFREDOSUM_VS_M8_E16_MASK, VFREDOSUM_VS, 0x3, 0x10 }, // 2563 |
| 9854 | { PseudoVFREDOSUM_VS_M8_E32, VFREDOSUM_VS, 0x3, 0x20 }, // 2564 |
| 9855 | { PseudoVFREDOSUM_VS_M8_E32_MASK, VFREDOSUM_VS, 0x3, 0x20 }, // 2565 |
| 9856 | { PseudoVFREDOSUM_VS_M8_E64, VFREDOSUM_VS, 0x3, 0x40 }, // 2566 |
| 9857 | { PseudoVFREDOSUM_VS_M8_E64_MASK, VFREDOSUM_VS, 0x3, 0x40 }, // 2567 |
| 9858 | { PseudoVFREDOSUM_VS_MF4_E16, VFREDOSUM_VS, 0x6, 0x10 }, // 2568 |
| 9859 | { PseudoVFREDOSUM_VS_MF4_E16_MASK, VFREDOSUM_VS, 0x6, 0x10 }, // 2569 |
| 9860 | { PseudoVFREDOSUM_VS_MF2_E16, VFREDOSUM_VS, 0x7, 0x10 }, // 2570 |
| 9861 | { PseudoVFREDOSUM_VS_MF2_E16_MASK, VFREDOSUM_VS, 0x7, 0x10 }, // 2571 |
| 9862 | { PseudoVFREDOSUM_VS_MF2_E32, VFREDOSUM_VS, 0x7, 0x20 }, // 2572 |
| 9863 | { PseudoVFREDOSUM_VS_MF2_E32_MASK, VFREDOSUM_VS, 0x7, 0x20 }, // 2573 |
| 9864 | { PseudoVFREDUSUM_VS_M1_E16, VFREDUSUM_VS, 0x0, 0x10 }, // 2574 |
| 9865 | { PseudoVFREDUSUM_VS_M1_E16_MASK, VFREDUSUM_VS, 0x0, 0x10 }, // 2575 |
| 9866 | { PseudoVFREDUSUM_VS_M1_E32, VFREDUSUM_VS, 0x0, 0x20 }, // 2576 |
| 9867 | { PseudoVFREDUSUM_VS_M1_E32_MASK, VFREDUSUM_VS, 0x0, 0x20 }, // 2577 |
| 9868 | { PseudoVFREDUSUM_VS_M1_E64, VFREDUSUM_VS, 0x0, 0x40 }, // 2578 |
| 9869 | { PseudoVFREDUSUM_VS_M1_E64_MASK, VFREDUSUM_VS, 0x0, 0x40 }, // 2579 |
| 9870 | { PseudoVFREDUSUM_VS_M2_E16, VFREDUSUM_VS, 0x1, 0x10 }, // 2580 |
| 9871 | { PseudoVFREDUSUM_VS_M2_E16_MASK, VFREDUSUM_VS, 0x1, 0x10 }, // 2581 |
| 9872 | { PseudoVFREDUSUM_VS_M2_E32, VFREDUSUM_VS, 0x1, 0x20 }, // 2582 |
| 9873 | { PseudoVFREDUSUM_VS_M2_E32_MASK, VFREDUSUM_VS, 0x1, 0x20 }, // 2583 |
| 9874 | { PseudoVFREDUSUM_VS_M2_E64, VFREDUSUM_VS, 0x1, 0x40 }, // 2584 |
| 9875 | { PseudoVFREDUSUM_VS_M2_E64_MASK, VFREDUSUM_VS, 0x1, 0x40 }, // 2585 |
| 9876 | { PseudoVFREDUSUM_VS_M4_E16, VFREDUSUM_VS, 0x2, 0x10 }, // 2586 |
| 9877 | { PseudoVFREDUSUM_VS_M4_E16_MASK, VFREDUSUM_VS, 0x2, 0x10 }, // 2587 |
| 9878 | { PseudoVFREDUSUM_VS_M4_E32, VFREDUSUM_VS, 0x2, 0x20 }, // 2588 |
| 9879 | { PseudoVFREDUSUM_VS_M4_E32_MASK, VFREDUSUM_VS, 0x2, 0x20 }, // 2589 |
| 9880 | { PseudoVFREDUSUM_VS_M4_E64, VFREDUSUM_VS, 0x2, 0x40 }, // 2590 |
| 9881 | { PseudoVFREDUSUM_VS_M4_E64_MASK, VFREDUSUM_VS, 0x2, 0x40 }, // 2591 |
| 9882 | { PseudoVFREDUSUM_VS_M8_E16, VFREDUSUM_VS, 0x3, 0x10 }, // 2592 |
| 9883 | { PseudoVFREDUSUM_VS_M8_E16_MASK, VFREDUSUM_VS, 0x3, 0x10 }, // 2593 |
| 9884 | { PseudoVFREDUSUM_VS_M8_E32, VFREDUSUM_VS, 0x3, 0x20 }, // 2594 |
| 9885 | { PseudoVFREDUSUM_VS_M8_E32_MASK, VFREDUSUM_VS, 0x3, 0x20 }, // 2595 |
| 9886 | { PseudoVFREDUSUM_VS_M8_E64, VFREDUSUM_VS, 0x3, 0x40 }, // 2596 |
| 9887 | { PseudoVFREDUSUM_VS_M8_E64_MASK, VFREDUSUM_VS, 0x3, 0x40 }, // 2597 |
| 9888 | { PseudoVFREDUSUM_VS_MF4_E16, VFREDUSUM_VS, 0x6, 0x10 }, // 2598 |
| 9889 | { PseudoVFREDUSUM_VS_MF4_E16_MASK, VFREDUSUM_VS, 0x6, 0x10 }, // 2599 |
| 9890 | { PseudoVFREDUSUM_VS_MF2_E16, VFREDUSUM_VS, 0x7, 0x10 }, // 2600 |
| 9891 | { PseudoVFREDUSUM_VS_MF2_E16_MASK, VFREDUSUM_VS, 0x7, 0x10 }, // 2601 |
| 9892 | { PseudoVFREDUSUM_VS_MF2_E32, VFREDUSUM_VS, 0x7, 0x20 }, // 2602 |
| 9893 | { PseudoVFREDUSUM_VS_MF2_E32_MASK, VFREDUSUM_VS, 0x7, 0x20 }, // 2603 |
| 9894 | { PseudoVFRSQRT7_V_M1_E16, VFRSQRT7_V, 0x0, 0x0 }, // 2604 |
| 9895 | { PseudoVFRSQRT7_V_M1_E16_MASK, VFRSQRT7_V, 0x0, 0x0 }, // 2605 |
| 9896 | { PseudoVFRSQRT7_V_M1_E32, VFRSQRT7_V, 0x0, 0x0 }, // 2606 |
| 9897 | { PseudoVFRSQRT7_V_M1_E32_MASK, VFRSQRT7_V, 0x0, 0x0 }, // 2607 |
| 9898 | { PseudoVFRSQRT7_V_M1_E64, VFRSQRT7_V, 0x0, 0x0 }, // 2608 |
| 9899 | { PseudoVFRSQRT7_V_M1_E64_MASK, VFRSQRT7_V, 0x0, 0x0 }, // 2609 |
| 9900 | { PseudoVFRSQRT7_V_M2_E16, VFRSQRT7_V, 0x1, 0x0 }, // 2610 |
| 9901 | { PseudoVFRSQRT7_V_M2_E16_MASK, VFRSQRT7_V, 0x1, 0x0 }, // 2611 |
| 9902 | { PseudoVFRSQRT7_V_M2_E32, VFRSQRT7_V, 0x1, 0x0 }, // 2612 |
| 9903 | { PseudoVFRSQRT7_V_M2_E32_MASK, VFRSQRT7_V, 0x1, 0x0 }, // 2613 |
| 9904 | { PseudoVFRSQRT7_V_M2_E64, VFRSQRT7_V, 0x1, 0x0 }, // 2614 |
| 9905 | { PseudoVFRSQRT7_V_M2_E64_MASK, VFRSQRT7_V, 0x1, 0x0 }, // 2615 |
| 9906 | { PseudoVFRSQRT7_V_M4_E16, VFRSQRT7_V, 0x2, 0x0 }, // 2616 |
| 9907 | { PseudoVFRSQRT7_V_M4_E16_MASK, VFRSQRT7_V, 0x2, 0x0 }, // 2617 |
| 9908 | { PseudoVFRSQRT7_V_M4_E32, VFRSQRT7_V, 0x2, 0x0 }, // 2618 |
| 9909 | { PseudoVFRSQRT7_V_M4_E32_MASK, VFRSQRT7_V, 0x2, 0x0 }, // 2619 |
| 9910 | { PseudoVFRSQRT7_V_M4_E64, VFRSQRT7_V, 0x2, 0x0 }, // 2620 |
| 9911 | { PseudoVFRSQRT7_V_M4_E64_MASK, VFRSQRT7_V, 0x2, 0x0 }, // 2621 |
| 9912 | { PseudoVFRSQRT7_V_M8_E16, VFRSQRT7_V, 0x3, 0x0 }, // 2622 |
| 9913 | { PseudoVFRSQRT7_V_M8_E16_MASK, VFRSQRT7_V, 0x3, 0x0 }, // 2623 |
| 9914 | { PseudoVFRSQRT7_V_M8_E32, VFRSQRT7_V, 0x3, 0x0 }, // 2624 |
| 9915 | { PseudoVFRSQRT7_V_M8_E32_MASK, VFRSQRT7_V, 0x3, 0x0 }, // 2625 |
| 9916 | { PseudoVFRSQRT7_V_M8_E64, VFRSQRT7_V, 0x3, 0x0 }, // 2626 |
| 9917 | { PseudoVFRSQRT7_V_M8_E64_MASK, VFRSQRT7_V, 0x3, 0x0 }, // 2627 |
| 9918 | { PseudoVFRSQRT7_V_MF4_E16, VFRSQRT7_V, 0x6, 0x0 }, // 2628 |
| 9919 | { PseudoVFRSQRT7_V_MF4_E16_MASK, VFRSQRT7_V, 0x6, 0x0 }, // 2629 |
| 9920 | { PseudoVFRSQRT7_V_MF2_E16, VFRSQRT7_V, 0x7, 0x0 }, // 2630 |
| 9921 | { PseudoVFRSQRT7_V_MF2_E16_MASK, VFRSQRT7_V, 0x7, 0x0 }, // 2631 |
| 9922 | { PseudoVFRSQRT7_V_MF2_E32, VFRSQRT7_V, 0x7, 0x0 }, // 2632 |
| 9923 | { PseudoVFRSQRT7_V_MF2_E32_MASK, VFRSQRT7_V, 0x7, 0x0 }, // 2633 |
| 9924 | { PseudoVFRSUB_VFPR16_M1_E16, VFRSUB_VF, 0x0, 0x10 }, // 2634 |
| 9925 | { PseudoVFRSUB_VFPR16_M1_E16_MASK, VFRSUB_VF, 0x0, 0x10 }, // 2635 |
| 9926 | { PseudoVFRSUB_VFPR32_M1_E32, VFRSUB_VF, 0x0, 0x20 }, // 2636 |
| 9927 | { PseudoVFRSUB_VFPR32_M1_E32_MASK, VFRSUB_VF, 0x0, 0x20 }, // 2637 |
| 9928 | { PseudoVFRSUB_VFPR64_M1_E64, VFRSUB_VF, 0x0, 0x40 }, // 2638 |
| 9929 | { PseudoVFRSUB_VFPR64_M1_E64_MASK, VFRSUB_VF, 0x0, 0x40 }, // 2639 |
| 9930 | { PseudoVFRSUB_VFPR16_M2_E16, VFRSUB_VF, 0x1, 0x10 }, // 2640 |
| 9931 | { PseudoVFRSUB_VFPR16_M2_E16_MASK, VFRSUB_VF, 0x1, 0x10 }, // 2641 |
| 9932 | { PseudoVFRSUB_VFPR32_M2_E32, VFRSUB_VF, 0x1, 0x20 }, // 2642 |
| 9933 | { PseudoVFRSUB_VFPR32_M2_E32_MASK, VFRSUB_VF, 0x1, 0x20 }, // 2643 |
| 9934 | { PseudoVFRSUB_VFPR64_M2_E64, VFRSUB_VF, 0x1, 0x40 }, // 2644 |
| 9935 | { PseudoVFRSUB_VFPR64_M2_E64_MASK, VFRSUB_VF, 0x1, 0x40 }, // 2645 |
| 9936 | { PseudoVFRSUB_VFPR16_M4_E16, VFRSUB_VF, 0x2, 0x10 }, // 2646 |
| 9937 | { PseudoVFRSUB_VFPR16_M4_E16_MASK, VFRSUB_VF, 0x2, 0x10 }, // 2647 |
| 9938 | { PseudoVFRSUB_VFPR32_M4_E32, VFRSUB_VF, 0x2, 0x20 }, // 2648 |
| 9939 | { PseudoVFRSUB_VFPR32_M4_E32_MASK, VFRSUB_VF, 0x2, 0x20 }, // 2649 |
| 9940 | { PseudoVFRSUB_VFPR64_M4_E64, VFRSUB_VF, 0x2, 0x40 }, // 2650 |
| 9941 | { PseudoVFRSUB_VFPR64_M4_E64_MASK, VFRSUB_VF, 0x2, 0x40 }, // 2651 |
| 9942 | { PseudoVFRSUB_VFPR16_M8_E16, VFRSUB_VF, 0x3, 0x10 }, // 2652 |
| 9943 | { PseudoVFRSUB_VFPR16_M8_E16_MASK, VFRSUB_VF, 0x3, 0x10 }, // 2653 |
| 9944 | { PseudoVFRSUB_VFPR32_M8_E32, VFRSUB_VF, 0x3, 0x20 }, // 2654 |
| 9945 | { PseudoVFRSUB_VFPR32_M8_E32_MASK, VFRSUB_VF, 0x3, 0x20 }, // 2655 |
| 9946 | { PseudoVFRSUB_VFPR64_M8_E64, VFRSUB_VF, 0x3, 0x40 }, // 2656 |
| 9947 | { PseudoVFRSUB_VFPR64_M8_E64_MASK, VFRSUB_VF, 0x3, 0x40 }, // 2657 |
| 9948 | { PseudoVFRSUB_VFPR16_MF4_E16, VFRSUB_VF, 0x6, 0x10 }, // 2658 |
| 9949 | { PseudoVFRSUB_VFPR16_MF4_E16_MASK, VFRSUB_VF, 0x6, 0x10 }, // 2659 |
| 9950 | { PseudoVFRSUB_VFPR16_MF2_E16, VFRSUB_VF, 0x7, 0x10 }, // 2660 |
| 9951 | { PseudoVFRSUB_VFPR16_MF2_E16_MASK, VFRSUB_VF, 0x7, 0x10 }, // 2661 |
| 9952 | { PseudoVFRSUB_VFPR32_MF2_E32, VFRSUB_VF, 0x7, 0x20 }, // 2662 |
| 9953 | { PseudoVFRSUB_VFPR32_MF2_E32_MASK, VFRSUB_VF, 0x7, 0x20 }, // 2663 |
| 9954 | { PseudoVFSGNJN_VFPR16_M1_E16, VFSGNJN_VF, 0x0, 0x10 }, // 2664 |
| 9955 | { PseudoVFSGNJN_VFPR16_M1_E16_MASK, VFSGNJN_VF, 0x0, 0x10 }, // 2665 |
| 9956 | { PseudoVFSGNJN_VFPR32_M1_E32, VFSGNJN_VF, 0x0, 0x20 }, // 2666 |
| 9957 | { PseudoVFSGNJN_VFPR32_M1_E32_MASK, VFSGNJN_VF, 0x0, 0x20 }, // 2667 |
| 9958 | { PseudoVFSGNJN_VFPR64_M1_E64, VFSGNJN_VF, 0x0, 0x40 }, // 2668 |
| 9959 | { PseudoVFSGNJN_VFPR64_M1_E64_MASK, VFSGNJN_VF, 0x0, 0x40 }, // 2669 |
| 9960 | { PseudoVFSGNJN_VFPR16_M2_E16, VFSGNJN_VF, 0x1, 0x10 }, // 2670 |
| 9961 | { PseudoVFSGNJN_VFPR16_M2_E16_MASK, VFSGNJN_VF, 0x1, 0x10 }, // 2671 |
| 9962 | { PseudoVFSGNJN_VFPR32_M2_E32, VFSGNJN_VF, 0x1, 0x20 }, // 2672 |
| 9963 | { PseudoVFSGNJN_VFPR32_M2_E32_MASK, VFSGNJN_VF, 0x1, 0x20 }, // 2673 |
| 9964 | { PseudoVFSGNJN_VFPR64_M2_E64, VFSGNJN_VF, 0x1, 0x40 }, // 2674 |
| 9965 | { PseudoVFSGNJN_VFPR64_M2_E64_MASK, VFSGNJN_VF, 0x1, 0x40 }, // 2675 |
| 9966 | { PseudoVFSGNJN_VFPR16_M4_E16, VFSGNJN_VF, 0x2, 0x10 }, // 2676 |
| 9967 | { PseudoVFSGNJN_VFPR16_M4_E16_MASK, VFSGNJN_VF, 0x2, 0x10 }, // 2677 |
| 9968 | { PseudoVFSGNJN_VFPR32_M4_E32, VFSGNJN_VF, 0x2, 0x20 }, // 2678 |
| 9969 | { PseudoVFSGNJN_VFPR32_M4_E32_MASK, VFSGNJN_VF, 0x2, 0x20 }, // 2679 |
| 9970 | { PseudoVFSGNJN_VFPR64_M4_E64, VFSGNJN_VF, 0x2, 0x40 }, // 2680 |
| 9971 | { PseudoVFSGNJN_VFPR64_M4_E64_MASK, VFSGNJN_VF, 0x2, 0x40 }, // 2681 |
| 9972 | { PseudoVFSGNJN_VFPR16_M8_E16, VFSGNJN_VF, 0x3, 0x10 }, // 2682 |
| 9973 | { PseudoVFSGNJN_VFPR16_M8_E16_MASK, VFSGNJN_VF, 0x3, 0x10 }, // 2683 |
| 9974 | { PseudoVFSGNJN_VFPR32_M8_E32, VFSGNJN_VF, 0x3, 0x20 }, // 2684 |
| 9975 | { PseudoVFSGNJN_VFPR32_M8_E32_MASK, VFSGNJN_VF, 0x3, 0x20 }, // 2685 |
| 9976 | { PseudoVFSGNJN_VFPR64_M8_E64, VFSGNJN_VF, 0x3, 0x40 }, // 2686 |
| 9977 | { PseudoVFSGNJN_VFPR64_M8_E64_MASK, VFSGNJN_VF, 0x3, 0x40 }, // 2687 |
| 9978 | { PseudoVFSGNJN_VFPR16_MF4_E16, VFSGNJN_VF, 0x6, 0x10 }, // 2688 |
| 9979 | { PseudoVFSGNJN_VFPR16_MF4_E16_MASK, VFSGNJN_VF, 0x6, 0x10 }, // 2689 |
| 9980 | { PseudoVFSGNJN_VFPR16_MF2_E16, VFSGNJN_VF, 0x7, 0x10 }, // 2690 |
| 9981 | { PseudoVFSGNJN_VFPR16_MF2_E16_MASK, VFSGNJN_VF, 0x7, 0x10 }, // 2691 |
| 9982 | { PseudoVFSGNJN_VFPR32_MF2_E32, VFSGNJN_VF, 0x7, 0x20 }, // 2692 |
| 9983 | { PseudoVFSGNJN_VFPR32_MF2_E32_MASK, VFSGNJN_VF, 0x7, 0x20 }, // 2693 |
| 9984 | { PseudoVFSGNJN_VV_M1_E16, VFSGNJN_VV, 0x0, 0x10 }, // 2694 |
| 9985 | { PseudoVFSGNJN_VV_M1_E16_MASK, VFSGNJN_VV, 0x0, 0x10 }, // 2695 |
| 9986 | { PseudoVFSGNJN_VV_M1_E32, VFSGNJN_VV, 0x0, 0x20 }, // 2696 |
| 9987 | { PseudoVFSGNJN_VV_M1_E32_MASK, VFSGNJN_VV, 0x0, 0x20 }, // 2697 |
| 9988 | { PseudoVFSGNJN_VV_M1_E64, VFSGNJN_VV, 0x0, 0x40 }, // 2698 |
| 9989 | { PseudoVFSGNJN_VV_M1_E64_MASK, VFSGNJN_VV, 0x0, 0x40 }, // 2699 |
| 9990 | { PseudoVFSGNJN_VV_M2_E16, VFSGNJN_VV, 0x1, 0x10 }, // 2700 |
| 9991 | { PseudoVFSGNJN_VV_M2_E16_MASK, VFSGNJN_VV, 0x1, 0x10 }, // 2701 |
| 9992 | { PseudoVFSGNJN_VV_M2_E32, VFSGNJN_VV, 0x1, 0x20 }, // 2702 |
| 9993 | { PseudoVFSGNJN_VV_M2_E32_MASK, VFSGNJN_VV, 0x1, 0x20 }, // 2703 |
| 9994 | { PseudoVFSGNJN_VV_M2_E64, VFSGNJN_VV, 0x1, 0x40 }, // 2704 |
| 9995 | { PseudoVFSGNJN_VV_M2_E64_MASK, VFSGNJN_VV, 0x1, 0x40 }, // 2705 |
| 9996 | { PseudoVFSGNJN_VV_M4_E16, VFSGNJN_VV, 0x2, 0x10 }, // 2706 |
| 9997 | { PseudoVFSGNJN_VV_M4_E16_MASK, VFSGNJN_VV, 0x2, 0x10 }, // 2707 |
| 9998 | { PseudoVFSGNJN_VV_M4_E32, VFSGNJN_VV, 0x2, 0x20 }, // 2708 |
| 9999 | { PseudoVFSGNJN_VV_M4_E32_MASK, VFSGNJN_VV, 0x2, 0x20 }, // 2709 |
| 10000 | { PseudoVFSGNJN_VV_M4_E64, VFSGNJN_VV, 0x2, 0x40 }, // 2710 |
| 10001 | { PseudoVFSGNJN_VV_M4_E64_MASK, VFSGNJN_VV, 0x2, 0x40 }, // 2711 |
| 10002 | { PseudoVFSGNJN_VV_M8_E16, VFSGNJN_VV, 0x3, 0x10 }, // 2712 |
| 10003 | { PseudoVFSGNJN_VV_M8_E16_MASK, VFSGNJN_VV, 0x3, 0x10 }, // 2713 |
| 10004 | { PseudoVFSGNJN_VV_M8_E32, VFSGNJN_VV, 0x3, 0x20 }, // 2714 |
| 10005 | { PseudoVFSGNJN_VV_M8_E32_MASK, VFSGNJN_VV, 0x3, 0x20 }, // 2715 |
| 10006 | { PseudoVFSGNJN_VV_M8_E64, VFSGNJN_VV, 0x3, 0x40 }, // 2716 |
| 10007 | { PseudoVFSGNJN_VV_M8_E64_MASK, VFSGNJN_VV, 0x3, 0x40 }, // 2717 |
| 10008 | { PseudoVFSGNJN_VV_MF4_E16, VFSGNJN_VV, 0x6, 0x10 }, // 2718 |
| 10009 | { PseudoVFSGNJN_VV_MF4_E16_MASK, VFSGNJN_VV, 0x6, 0x10 }, // 2719 |
| 10010 | { PseudoVFSGNJN_VV_MF2_E16, VFSGNJN_VV, 0x7, 0x10 }, // 2720 |
| 10011 | { PseudoVFSGNJN_VV_MF2_E16_MASK, VFSGNJN_VV, 0x7, 0x10 }, // 2721 |
| 10012 | { PseudoVFSGNJN_VV_MF2_E32, VFSGNJN_VV, 0x7, 0x20 }, // 2722 |
| 10013 | { PseudoVFSGNJN_VV_MF2_E32_MASK, VFSGNJN_VV, 0x7, 0x20 }, // 2723 |
| 10014 | { PseudoVFSGNJX_VFPR16_M1_E16, VFSGNJX_VF, 0x0, 0x10 }, // 2724 |
| 10015 | { PseudoVFSGNJX_VFPR16_M1_E16_MASK, VFSGNJX_VF, 0x0, 0x10 }, // 2725 |
| 10016 | { PseudoVFSGNJX_VFPR32_M1_E32, VFSGNJX_VF, 0x0, 0x20 }, // 2726 |
| 10017 | { PseudoVFSGNJX_VFPR32_M1_E32_MASK, VFSGNJX_VF, 0x0, 0x20 }, // 2727 |
| 10018 | { PseudoVFSGNJX_VFPR64_M1_E64, VFSGNJX_VF, 0x0, 0x40 }, // 2728 |
| 10019 | { PseudoVFSGNJX_VFPR64_M1_E64_MASK, VFSGNJX_VF, 0x0, 0x40 }, // 2729 |
| 10020 | { PseudoVFSGNJX_VFPR16_M2_E16, VFSGNJX_VF, 0x1, 0x10 }, // 2730 |
| 10021 | { PseudoVFSGNJX_VFPR16_M2_E16_MASK, VFSGNJX_VF, 0x1, 0x10 }, // 2731 |
| 10022 | { PseudoVFSGNJX_VFPR32_M2_E32, VFSGNJX_VF, 0x1, 0x20 }, // 2732 |
| 10023 | { PseudoVFSGNJX_VFPR32_M2_E32_MASK, VFSGNJX_VF, 0x1, 0x20 }, // 2733 |
| 10024 | { PseudoVFSGNJX_VFPR64_M2_E64, VFSGNJX_VF, 0x1, 0x40 }, // 2734 |
| 10025 | { PseudoVFSGNJX_VFPR64_M2_E64_MASK, VFSGNJX_VF, 0x1, 0x40 }, // 2735 |
| 10026 | { PseudoVFSGNJX_VFPR16_M4_E16, VFSGNJX_VF, 0x2, 0x10 }, // 2736 |
| 10027 | { PseudoVFSGNJX_VFPR16_M4_E16_MASK, VFSGNJX_VF, 0x2, 0x10 }, // 2737 |
| 10028 | { PseudoVFSGNJX_VFPR32_M4_E32, VFSGNJX_VF, 0x2, 0x20 }, // 2738 |
| 10029 | { PseudoVFSGNJX_VFPR32_M4_E32_MASK, VFSGNJX_VF, 0x2, 0x20 }, // 2739 |
| 10030 | { PseudoVFSGNJX_VFPR64_M4_E64, VFSGNJX_VF, 0x2, 0x40 }, // 2740 |
| 10031 | { PseudoVFSGNJX_VFPR64_M4_E64_MASK, VFSGNJX_VF, 0x2, 0x40 }, // 2741 |
| 10032 | { PseudoVFSGNJX_VFPR16_M8_E16, VFSGNJX_VF, 0x3, 0x10 }, // 2742 |
| 10033 | { PseudoVFSGNJX_VFPR16_M8_E16_MASK, VFSGNJX_VF, 0x3, 0x10 }, // 2743 |
| 10034 | { PseudoVFSGNJX_VFPR32_M8_E32, VFSGNJX_VF, 0x3, 0x20 }, // 2744 |
| 10035 | { PseudoVFSGNJX_VFPR32_M8_E32_MASK, VFSGNJX_VF, 0x3, 0x20 }, // 2745 |
| 10036 | { PseudoVFSGNJX_VFPR64_M8_E64, VFSGNJX_VF, 0x3, 0x40 }, // 2746 |
| 10037 | { PseudoVFSGNJX_VFPR64_M8_E64_MASK, VFSGNJX_VF, 0x3, 0x40 }, // 2747 |
| 10038 | { PseudoVFSGNJX_VFPR16_MF4_E16, VFSGNJX_VF, 0x6, 0x10 }, // 2748 |
| 10039 | { PseudoVFSGNJX_VFPR16_MF4_E16_MASK, VFSGNJX_VF, 0x6, 0x10 }, // 2749 |
| 10040 | { PseudoVFSGNJX_VFPR16_MF2_E16, VFSGNJX_VF, 0x7, 0x10 }, // 2750 |
| 10041 | { PseudoVFSGNJX_VFPR16_MF2_E16_MASK, VFSGNJX_VF, 0x7, 0x10 }, // 2751 |
| 10042 | { PseudoVFSGNJX_VFPR32_MF2_E32, VFSGNJX_VF, 0x7, 0x20 }, // 2752 |
| 10043 | { PseudoVFSGNJX_VFPR32_MF2_E32_MASK, VFSGNJX_VF, 0x7, 0x20 }, // 2753 |
| 10044 | { PseudoVFSGNJX_VV_M1_E16, VFSGNJX_VV, 0x0, 0x10 }, // 2754 |
| 10045 | { PseudoVFSGNJX_VV_M1_E16_MASK, VFSGNJX_VV, 0x0, 0x10 }, // 2755 |
| 10046 | { PseudoVFSGNJX_VV_M1_E32, VFSGNJX_VV, 0x0, 0x20 }, // 2756 |
| 10047 | { PseudoVFSGNJX_VV_M1_E32_MASK, VFSGNJX_VV, 0x0, 0x20 }, // 2757 |
| 10048 | { PseudoVFSGNJX_VV_M1_E64, VFSGNJX_VV, 0x0, 0x40 }, // 2758 |
| 10049 | { PseudoVFSGNJX_VV_M1_E64_MASK, VFSGNJX_VV, 0x0, 0x40 }, // 2759 |
| 10050 | { PseudoVFSGNJX_VV_M2_E16, VFSGNJX_VV, 0x1, 0x10 }, // 2760 |
| 10051 | { PseudoVFSGNJX_VV_M2_E16_MASK, VFSGNJX_VV, 0x1, 0x10 }, // 2761 |
| 10052 | { PseudoVFSGNJX_VV_M2_E32, VFSGNJX_VV, 0x1, 0x20 }, // 2762 |
| 10053 | { PseudoVFSGNJX_VV_M2_E32_MASK, VFSGNJX_VV, 0x1, 0x20 }, // 2763 |
| 10054 | { PseudoVFSGNJX_VV_M2_E64, VFSGNJX_VV, 0x1, 0x40 }, // 2764 |
| 10055 | { PseudoVFSGNJX_VV_M2_E64_MASK, VFSGNJX_VV, 0x1, 0x40 }, // 2765 |
| 10056 | { PseudoVFSGNJX_VV_M4_E16, VFSGNJX_VV, 0x2, 0x10 }, // 2766 |
| 10057 | { PseudoVFSGNJX_VV_M4_E16_MASK, VFSGNJX_VV, 0x2, 0x10 }, // 2767 |
| 10058 | { PseudoVFSGNJX_VV_M4_E32, VFSGNJX_VV, 0x2, 0x20 }, // 2768 |
| 10059 | { PseudoVFSGNJX_VV_M4_E32_MASK, VFSGNJX_VV, 0x2, 0x20 }, // 2769 |
| 10060 | { PseudoVFSGNJX_VV_M4_E64, VFSGNJX_VV, 0x2, 0x40 }, // 2770 |
| 10061 | { PseudoVFSGNJX_VV_M4_E64_MASK, VFSGNJX_VV, 0x2, 0x40 }, // 2771 |
| 10062 | { PseudoVFSGNJX_VV_M8_E16, VFSGNJX_VV, 0x3, 0x10 }, // 2772 |
| 10063 | { PseudoVFSGNJX_VV_M8_E16_MASK, VFSGNJX_VV, 0x3, 0x10 }, // 2773 |
| 10064 | { PseudoVFSGNJX_VV_M8_E32, VFSGNJX_VV, 0x3, 0x20 }, // 2774 |
| 10065 | { PseudoVFSGNJX_VV_M8_E32_MASK, VFSGNJX_VV, 0x3, 0x20 }, // 2775 |
| 10066 | { PseudoVFSGNJX_VV_M8_E64, VFSGNJX_VV, 0x3, 0x40 }, // 2776 |
| 10067 | { PseudoVFSGNJX_VV_M8_E64_MASK, VFSGNJX_VV, 0x3, 0x40 }, // 2777 |
| 10068 | { PseudoVFSGNJX_VV_MF4_E16, VFSGNJX_VV, 0x6, 0x10 }, // 2778 |
| 10069 | { PseudoVFSGNJX_VV_MF4_E16_MASK, VFSGNJX_VV, 0x6, 0x10 }, // 2779 |
| 10070 | { PseudoVFSGNJX_VV_MF2_E16, VFSGNJX_VV, 0x7, 0x10 }, // 2780 |
| 10071 | { PseudoVFSGNJX_VV_MF2_E16_MASK, VFSGNJX_VV, 0x7, 0x10 }, // 2781 |
| 10072 | { PseudoVFSGNJX_VV_MF2_E32, VFSGNJX_VV, 0x7, 0x20 }, // 2782 |
| 10073 | { PseudoVFSGNJX_VV_MF2_E32_MASK, VFSGNJX_VV, 0x7, 0x20 }, // 2783 |
| 10074 | { PseudoVFSGNJ_VFPR16_M1_E16, VFSGNJ_VF, 0x0, 0x10 }, // 2784 |
| 10075 | { PseudoVFSGNJ_VFPR16_M1_E16_MASK, VFSGNJ_VF, 0x0, 0x10 }, // 2785 |
| 10076 | { PseudoVFSGNJ_VFPR32_M1_E32, VFSGNJ_VF, 0x0, 0x20 }, // 2786 |
| 10077 | { PseudoVFSGNJ_VFPR32_M1_E32_MASK, VFSGNJ_VF, 0x0, 0x20 }, // 2787 |
| 10078 | { PseudoVFSGNJ_VFPR64_M1_E64, VFSGNJ_VF, 0x0, 0x40 }, // 2788 |
| 10079 | { PseudoVFSGNJ_VFPR64_M1_E64_MASK, VFSGNJ_VF, 0x0, 0x40 }, // 2789 |
| 10080 | { PseudoVFSGNJ_VFPR16_M2_E16, VFSGNJ_VF, 0x1, 0x10 }, // 2790 |
| 10081 | { PseudoVFSGNJ_VFPR16_M2_E16_MASK, VFSGNJ_VF, 0x1, 0x10 }, // 2791 |
| 10082 | { PseudoVFSGNJ_VFPR32_M2_E32, VFSGNJ_VF, 0x1, 0x20 }, // 2792 |
| 10083 | { PseudoVFSGNJ_VFPR32_M2_E32_MASK, VFSGNJ_VF, 0x1, 0x20 }, // 2793 |
| 10084 | { PseudoVFSGNJ_VFPR64_M2_E64, VFSGNJ_VF, 0x1, 0x40 }, // 2794 |
| 10085 | { PseudoVFSGNJ_VFPR64_M2_E64_MASK, VFSGNJ_VF, 0x1, 0x40 }, // 2795 |
| 10086 | { PseudoVFSGNJ_VFPR16_M4_E16, VFSGNJ_VF, 0x2, 0x10 }, // 2796 |
| 10087 | { PseudoVFSGNJ_VFPR16_M4_E16_MASK, VFSGNJ_VF, 0x2, 0x10 }, // 2797 |
| 10088 | { PseudoVFSGNJ_VFPR32_M4_E32, VFSGNJ_VF, 0x2, 0x20 }, // 2798 |
| 10089 | { PseudoVFSGNJ_VFPR32_M4_E32_MASK, VFSGNJ_VF, 0x2, 0x20 }, // 2799 |
| 10090 | { PseudoVFSGNJ_VFPR64_M4_E64, VFSGNJ_VF, 0x2, 0x40 }, // 2800 |
| 10091 | { PseudoVFSGNJ_VFPR64_M4_E64_MASK, VFSGNJ_VF, 0x2, 0x40 }, // 2801 |
| 10092 | { PseudoVFSGNJ_VFPR16_M8_E16, VFSGNJ_VF, 0x3, 0x10 }, // 2802 |
| 10093 | { PseudoVFSGNJ_VFPR16_M8_E16_MASK, VFSGNJ_VF, 0x3, 0x10 }, // 2803 |
| 10094 | { PseudoVFSGNJ_VFPR32_M8_E32, VFSGNJ_VF, 0x3, 0x20 }, // 2804 |
| 10095 | { PseudoVFSGNJ_VFPR32_M8_E32_MASK, VFSGNJ_VF, 0x3, 0x20 }, // 2805 |
| 10096 | { PseudoVFSGNJ_VFPR64_M8_E64, VFSGNJ_VF, 0x3, 0x40 }, // 2806 |
| 10097 | { PseudoVFSGNJ_VFPR64_M8_E64_MASK, VFSGNJ_VF, 0x3, 0x40 }, // 2807 |
| 10098 | { PseudoVFSGNJ_VFPR16_MF4_E16, VFSGNJ_VF, 0x6, 0x10 }, // 2808 |
| 10099 | { PseudoVFSGNJ_VFPR16_MF4_E16_MASK, VFSGNJ_VF, 0x6, 0x10 }, // 2809 |
| 10100 | { PseudoVFSGNJ_VFPR16_MF2_E16, VFSGNJ_VF, 0x7, 0x10 }, // 2810 |
| 10101 | { PseudoVFSGNJ_VFPR16_MF2_E16_MASK, VFSGNJ_VF, 0x7, 0x10 }, // 2811 |
| 10102 | { PseudoVFSGNJ_VFPR32_MF2_E32, VFSGNJ_VF, 0x7, 0x20 }, // 2812 |
| 10103 | { PseudoVFSGNJ_VFPR32_MF2_E32_MASK, VFSGNJ_VF, 0x7, 0x20 }, // 2813 |
| 10104 | { PseudoVFSGNJ_VV_M1_E16, VFSGNJ_VV, 0x0, 0x10 }, // 2814 |
| 10105 | { PseudoVFSGNJ_VV_M1_E16_MASK, VFSGNJ_VV, 0x0, 0x10 }, // 2815 |
| 10106 | { PseudoVFSGNJ_VV_M1_E32, VFSGNJ_VV, 0x0, 0x20 }, // 2816 |
| 10107 | { PseudoVFSGNJ_VV_M1_E32_MASK, VFSGNJ_VV, 0x0, 0x20 }, // 2817 |
| 10108 | { PseudoVFSGNJ_VV_M1_E64, VFSGNJ_VV, 0x0, 0x40 }, // 2818 |
| 10109 | { PseudoVFSGNJ_VV_M1_E64_MASK, VFSGNJ_VV, 0x0, 0x40 }, // 2819 |
| 10110 | { PseudoVFSGNJ_VV_M2_E16, VFSGNJ_VV, 0x1, 0x10 }, // 2820 |
| 10111 | { PseudoVFSGNJ_VV_M2_E16_MASK, VFSGNJ_VV, 0x1, 0x10 }, // 2821 |
| 10112 | { PseudoVFSGNJ_VV_M2_E32, VFSGNJ_VV, 0x1, 0x20 }, // 2822 |
| 10113 | { PseudoVFSGNJ_VV_M2_E32_MASK, VFSGNJ_VV, 0x1, 0x20 }, // 2823 |
| 10114 | { PseudoVFSGNJ_VV_M2_E64, VFSGNJ_VV, 0x1, 0x40 }, // 2824 |
| 10115 | { PseudoVFSGNJ_VV_M2_E64_MASK, VFSGNJ_VV, 0x1, 0x40 }, // 2825 |
| 10116 | { PseudoVFSGNJ_VV_M4_E16, VFSGNJ_VV, 0x2, 0x10 }, // 2826 |
| 10117 | { PseudoVFSGNJ_VV_M4_E16_MASK, VFSGNJ_VV, 0x2, 0x10 }, // 2827 |
| 10118 | { PseudoVFSGNJ_VV_M4_E32, VFSGNJ_VV, 0x2, 0x20 }, // 2828 |
| 10119 | { PseudoVFSGNJ_VV_M4_E32_MASK, VFSGNJ_VV, 0x2, 0x20 }, // 2829 |
| 10120 | { PseudoVFSGNJ_VV_M4_E64, VFSGNJ_VV, 0x2, 0x40 }, // 2830 |
| 10121 | { PseudoVFSGNJ_VV_M4_E64_MASK, VFSGNJ_VV, 0x2, 0x40 }, // 2831 |
| 10122 | { PseudoVFSGNJ_VV_M8_E16, VFSGNJ_VV, 0x3, 0x10 }, // 2832 |
| 10123 | { PseudoVFSGNJ_VV_M8_E16_MASK, VFSGNJ_VV, 0x3, 0x10 }, // 2833 |
| 10124 | { PseudoVFSGNJ_VV_M8_E32, VFSGNJ_VV, 0x3, 0x20 }, // 2834 |
| 10125 | { PseudoVFSGNJ_VV_M8_E32_MASK, VFSGNJ_VV, 0x3, 0x20 }, // 2835 |
| 10126 | { PseudoVFSGNJ_VV_M8_E64, VFSGNJ_VV, 0x3, 0x40 }, // 2836 |
| 10127 | { PseudoVFSGNJ_VV_M8_E64_MASK, VFSGNJ_VV, 0x3, 0x40 }, // 2837 |
| 10128 | { PseudoVFSGNJ_VV_MF4_E16, VFSGNJ_VV, 0x6, 0x10 }, // 2838 |
| 10129 | { PseudoVFSGNJ_VV_MF4_E16_MASK, VFSGNJ_VV, 0x6, 0x10 }, // 2839 |
| 10130 | { PseudoVFSGNJ_VV_MF2_E16, VFSGNJ_VV, 0x7, 0x10 }, // 2840 |
| 10131 | { PseudoVFSGNJ_VV_MF2_E16_MASK, VFSGNJ_VV, 0x7, 0x10 }, // 2841 |
| 10132 | { PseudoVFSGNJ_VV_MF2_E32, VFSGNJ_VV, 0x7, 0x20 }, // 2842 |
| 10133 | { PseudoVFSGNJ_VV_MF2_E32_MASK, VFSGNJ_VV, 0x7, 0x20 }, // 2843 |
| 10134 | { PseudoVFSLIDE1DOWN_VFPR16_M1, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2844 |
| 10135 | { PseudoVFSLIDE1DOWN_VFPR16_M1_MASK, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2845 |
| 10136 | { PseudoVFSLIDE1DOWN_VFPR32_M1, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2846 |
| 10137 | { PseudoVFSLIDE1DOWN_VFPR32_M1_MASK, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2847 |
| 10138 | { PseudoVFSLIDE1DOWN_VFPR64_M1, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2848 |
| 10139 | { PseudoVFSLIDE1DOWN_VFPR64_M1_MASK, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2849 |
| 10140 | { PseudoVFSLIDE1DOWN_VFPR16_M2, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2850 |
| 10141 | { PseudoVFSLIDE1DOWN_VFPR16_M2_MASK, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2851 |
| 10142 | { PseudoVFSLIDE1DOWN_VFPR32_M2, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2852 |
| 10143 | { PseudoVFSLIDE1DOWN_VFPR32_M2_MASK, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2853 |
| 10144 | { PseudoVFSLIDE1DOWN_VFPR64_M2, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2854 |
| 10145 | { PseudoVFSLIDE1DOWN_VFPR64_M2_MASK, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2855 |
| 10146 | { PseudoVFSLIDE1DOWN_VFPR16_M4, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2856 |
| 10147 | { PseudoVFSLIDE1DOWN_VFPR16_M4_MASK, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2857 |
| 10148 | { PseudoVFSLIDE1DOWN_VFPR32_M4, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2858 |
| 10149 | { PseudoVFSLIDE1DOWN_VFPR32_M4_MASK, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2859 |
| 10150 | { PseudoVFSLIDE1DOWN_VFPR64_M4, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2860 |
| 10151 | { PseudoVFSLIDE1DOWN_VFPR64_M4_MASK, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2861 |
| 10152 | { PseudoVFSLIDE1DOWN_VFPR16_M8, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2862 |
| 10153 | { PseudoVFSLIDE1DOWN_VFPR16_M8_MASK, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2863 |
| 10154 | { PseudoVFSLIDE1DOWN_VFPR32_M8, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2864 |
| 10155 | { PseudoVFSLIDE1DOWN_VFPR32_M8_MASK, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2865 |
| 10156 | { PseudoVFSLIDE1DOWN_VFPR64_M8, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2866 |
| 10157 | { PseudoVFSLIDE1DOWN_VFPR64_M8_MASK, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2867 |
| 10158 | { PseudoVFSLIDE1DOWN_VFPR16_MF4, VFSLIDE1DOWN_VF, 0x6, 0x0 }, // 2868 |
| 10159 | { PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK, VFSLIDE1DOWN_VF, 0x6, 0x0 }, // 2869 |
| 10160 | { PseudoVFSLIDE1DOWN_VFPR16_MF2, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2870 |
| 10161 | { PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2871 |
| 10162 | { PseudoVFSLIDE1DOWN_VFPR32_MF2, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2872 |
| 10163 | { PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2873 |
| 10164 | { PseudoVFSLIDE1UP_VFPR16_M1, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2874 |
| 10165 | { PseudoVFSLIDE1UP_VFPR16_M1_MASK, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2875 |
| 10166 | { PseudoVFSLIDE1UP_VFPR32_M1, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2876 |
| 10167 | { PseudoVFSLIDE1UP_VFPR32_M1_MASK, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2877 |
| 10168 | { PseudoVFSLIDE1UP_VFPR64_M1, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2878 |
| 10169 | { PseudoVFSLIDE1UP_VFPR64_M1_MASK, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2879 |
| 10170 | { PseudoVFSLIDE1UP_VFPR16_M2, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2880 |
| 10171 | { PseudoVFSLIDE1UP_VFPR16_M2_MASK, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2881 |
| 10172 | { PseudoVFSLIDE1UP_VFPR32_M2, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2882 |
| 10173 | { PseudoVFSLIDE1UP_VFPR32_M2_MASK, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2883 |
| 10174 | { PseudoVFSLIDE1UP_VFPR64_M2, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2884 |
| 10175 | { PseudoVFSLIDE1UP_VFPR64_M2_MASK, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2885 |
| 10176 | { PseudoVFSLIDE1UP_VFPR16_M4, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2886 |
| 10177 | { PseudoVFSLIDE1UP_VFPR16_M4_MASK, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2887 |
| 10178 | { PseudoVFSLIDE1UP_VFPR32_M4, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2888 |
| 10179 | { PseudoVFSLIDE1UP_VFPR32_M4_MASK, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2889 |
| 10180 | { PseudoVFSLIDE1UP_VFPR64_M4, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2890 |
| 10181 | { PseudoVFSLIDE1UP_VFPR64_M4_MASK, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2891 |
| 10182 | { PseudoVFSLIDE1UP_VFPR16_M8, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2892 |
| 10183 | { PseudoVFSLIDE1UP_VFPR16_M8_MASK, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2893 |
| 10184 | { PseudoVFSLIDE1UP_VFPR32_M8, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2894 |
| 10185 | { PseudoVFSLIDE1UP_VFPR32_M8_MASK, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2895 |
| 10186 | { PseudoVFSLIDE1UP_VFPR64_M8, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2896 |
| 10187 | { PseudoVFSLIDE1UP_VFPR64_M8_MASK, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2897 |
| 10188 | { PseudoVFSLIDE1UP_VFPR16_MF4, VFSLIDE1UP_VF, 0x6, 0x0 }, // 2898 |
| 10189 | { PseudoVFSLIDE1UP_VFPR16_MF4_MASK, VFSLIDE1UP_VF, 0x6, 0x0 }, // 2899 |
| 10190 | { PseudoVFSLIDE1UP_VFPR16_MF2, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2900 |
| 10191 | { PseudoVFSLIDE1UP_VFPR16_MF2_MASK, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2901 |
| 10192 | { PseudoVFSLIDE1UP_VFPR32_MF2, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2902 |
| 10193 | { PseudoVFSLIDE1UP_VFPR32_MF2_MASK, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2903 |
| 10194 | { PseudoVFSQRT_V_M1_E16, VFSQRT_V, 0x0, 0x10 }, // 2904 |
| 10195 | { PseudoVFSQRT_V_M1_E16_MASK, VFSQRT_V, 0x0, 0x10 }, // 2905 |
| 10196 | { PseudoVFSQRT_V_M1_E32, VFSQRT_V, 0x0, 0x20 }, // 2906 |
| 10197 | { PseudoVFSQRT_V_M1_E32_MASK, VFSQRT_V, 0x0, 0x20 }, // 2907 |
| 10198 | { PseudoVFSQRT_V_M1_E64, VFSQRT_V, 0x0, 0x40 }, // 2908 |
| 10199 | { PseudoVFSQRT_V_M1_E64_MASK, VFSQRT_V, 0x0, 0x40 }, // 2909 |
| 10200 | { PseudoVFSQRT_V_M2_E16, VFSQRT_V, 0x1, 0x10 }, // 2910 |
| 10201 | { PseudoVFSQRT_V_M2_E16_MASK, VFSQRT_V, 0x1, 0x10 }, // 2911 |
| 10202 | { PseudoVFSQRT_V_M2_E32, VFSQRT_V, 0x1, 0x20 }, // 2912 |
| 10203 | { PseudoVFSQRT_V_M2_E32_MASK, VFSQRT_V, 0x1, 0x20 }, // 2913 |
| 10204 | { PseudoVFSQRT_V_M2_E64, VFSQRT_V, 0x1, 0x40 }, // 2914 |
| 10205 | { PseudoVFSQRT_V_M2_E64_MASK, VFSQRT_V, 0x1, 0x40 }, // 2915 |
| 10206 | { PseudoVFSQRT_V_M4_E16, VFSQRT_V, 0x2, 0x10 }, // 2916 |
| 10207 | { PseudoVFSQRT_V_M4_E16_MASK, VFSQRT_V, 0x2, 0x10 }, // 2917 |
| 10208 | { PseudoVFSQRT_V_M4_E32, VFSQRT_V, 0x2, 0x20 }, // 2918 |
| 10209 | { PseudoVFSQRT_V_M4_E32_MASK, VFSQRT_V, 0x2, 0x20 }, // 2919 |
| 10210 | { PseudoVFSQRT_V_M4_E64, VFSQRT_V, 0x2, 0x40 }, // 2920 |
| 10211 | { PseudoVFSQRT_V_M4_E64_MASK, VFSQRT_V, 0x2, 0x40 }, // 2921 |
| 10212 | { PseudoVFSQRT_V_M8_E16, VFSQRT_V, 0x3, 0x10 }, // 2922 |
| 10213 | { PseudoVFSQRT_V_M8_E16_MASK, VFSQRT_V, 0x3, 0x10 }, // 2923 |
| 10214 | { PseudoVFSQRT_V_M8_E32, VFSQRT_V, 0x3, 0x20 }, // 2924 |
| 10215 | { PseudoVFSQRT_V_M8_E32_MASK, VFSQRT_V, 0x3, 0x20 }, // 2925 |
| 10216 | { PseudoVFSQRT_V_M8_E64, VFSQRT_V, 0x3, 0x40 }, // 2926 |
| 10217 | { PseudoVFSQRT_V_M8_E64_MASK, VFSQRT_V, 0x3, 0x40 }, // 2927 |
| 10218 | { PseudoVFSQRT_V_MF4_E16, VFSQRT_V, 0x6, 0x10 }, // 2928 |
| 10219 | { PseudoVFSQRT_V_MF4_E16_MASK, VFSQRT_V, 0x6, 0x10 }, // 2929 |
| 10220 | { PseudoVFSQRT_V_MF2_E16, VFSQRT_V, 0x7, 0x10 }, // 2930 |
| 10221 | { PseudoVFSQRT_V_MF2_E16_MASK, VFSQRT_V, 0x7, 0x10 }, // 2931 |
| 10222 | { PseudoVFSQRT_V_MF2_E32, VFSQRT_V, 0x7, 0x20 }, // 2932 |
| 10223 | { PseudoVFSQRT_V_MF2_E32_MASK, VFSQRT_V, 0x7, 0x20 }, // 2933 |
| 10224 | { PseudoVFSUB_VFPR16_M1_E16, VFSUB_VF, 0x0, 0x10 }, // 2934 |
| 10225 | { PseudoVFSUB_VFPR16_M1_E16_MASK, VFSUB_VF, 0x0, 0x10 }, // 2935 |
| 10226 | { PseudoVFSUB_VFPR32_M1_E32, VFSUB_VF, 0x0, 0x20 }, // 2936 |
| 10227 | { PseudoVFSUB_VFPR32_M1_E32_MASK, VFSUB_VF, 0x0, 0x20 }, // 2937 |
| 10228 | { PseudoVFSUB_VFPR64_M1_E64, VFSUB_VF, 0x0, 0x40 }, // 2938 |
| 10229 | { PseudoVFSUB_VFPR64_M1_E64_MASK, VFSUB_VF, 0x0, 0x40 }, // 2939 |
| 10230 | { PseudoVFSUB_VFPR16_M2_E16, VFSUB_VF, 0x1, 0x10 }, // 2940 |
| 10231 | { PseudoVFSUB_VFPR16_M2_E16_MASK, VFSUB_VF, 0x1, 0x10 }, // 2941 |
| 10232 | { PseudoVFSUB_VFPR32_M2_E32, VFSUB_VF, 0x1, 0x20 }, // 2942 |
| 10233 | { PseudoVFSUB_VFPR32_M2_E32_MASK, VFSUB_VF, 0x1, 0x20 }, // 2943 |
| 10234 | { PseudoVFSUB_VFPR64_M2_E64, VFSUB_VF, 0x1, 0x40 }, // 2944 |
| 10235 | { PseudoVFSUB_VFPR64_M2_E64_MASK, VFSUB_VF, 0x1, 0x40 }, // 2945 |
| 10236 | { PseudoVFSUB_VFPR16_M4_E16, VFSUB_VF, 0x2, 0x10 }, // 2946 |
| 10237 | { PseudoVFSUB_VFPR16_M4_E16_MASK, VFSUB_VF, 0x2, 0x10 }, // 2947 |
| 10238 | { PseudoVFSUB_VFPR32_M4_E32, VFSUB_VF, 0x2, 0x20 }, // 2948 |
| 10239 | { PseudoVFSUB_VFPR32_M4_E32_MASK, VFSUB_VF, 0x2, 0x20 }, // 2949 |
| 10240 | { PseudoVFSUB_VFPR64_M4_E64, VFSUB_VF, 0x2, 0x40 }, // 2950 |
| 10241 | { PseudoVFSUB_VFPR64_M4_E64_MASK, VFSUB_VF, 0x2, 0x40 }, // 2951 |
| 10242 | { PseudoVFSUB_VFPR16_M8_E16, VFSUB_VF, 0x3, 0x10 }, // 2952 |
| 10243 | { PseudoVFSUB_VFPR16_M8_E16_MASK, VFSUB_VF, 0x3, 0x10 }, // 2953 |
| 10244 | { PseudoVFSUB_VFPR32_M8_E32, VFSUB_VF, 0x3, 0x20 }, // 2954 |
| 10245 | { PseudoVFSUB_VFPR32_M8_E32_MASK, VFSUB_VF, 0x3, 0x20 }, // 2955 |
| 10246 | { PseudoVFSUB_VFPR64_M8_E64, VFSUB_VF, 0x3, 0x40 }, // 2956 |
| 10247 | { PseudoVFSUB_VFPR64_M8_E64_MASK, VFSUB_VF, 0x3, 0x40 }, // 2957 |
| 10248 | { PseudoVFSUB_VFPR16_MF4_E16, VFSUB_VF, 0x6, 0x10 }, // 2958 |
| 10249 | { PseudoVFSUB_VFPR16_MF4_E16_MASK, VFSUB_VF, 0x6, 0x10 }, // 2959 |
| 10250 | { PseudoVFSUB_VFPR16_MF2_E16, VFSUB_VF, 0x7, 0x10 }, // 2960 |
| 10251 | { PseudoVFSUB_VFPR16_MF2_E16_MASK, VFSUB_VF, 0x7, 0x10 }, // 2961 |
| 10252 | { PseudoVFSUB_VFPR32_MF2_E32, VFSUB_VF, 0x7, 0x20 }, // 2962 |
| 10253 | { PseudoVFSUB_VFPR32_MF2_E32_MASK, VFSUB_VF, 0x7, 0x20 }, // 2963 |
| 10254 | { PseudoVFSUB_VV_M1_E16, VFSUB_VV, 0x0, 0x10 }, // 2964 |
| 10255 | { PseudoVFSUB_VV_M1_E16_MASK, VFSUB_VV, 0x0, 0x10 }, // 2965 |
| 10256 | { PseudoVFSUB_VV_M1_E32, VFSUB_VV, 0x0, 0x20 }, // 2966 |
| 10257 | { PseudoVFSUB_VV_M1_E32_MASK, VFSUB_VV, 0x0, 0x20 }, // 2967 |
| 10258 | { PseudoVFSUB_VV_M1_E64, VFSUB_VV, 0x0, 0x40 }, // 2968 |
| 10259 | { PseudoVFSUB_VV_M1_E64_MASK, VFSUB_VV, 0x0, 0x40 }, // 2969 |
| 10260 | { PseudoVFSUB_VV_M2_E16, VFSUB_VV, 0x1, 0x10 }, // 2970 |
| 10261 | { PseudoVFSUB_VV_M2_E16_MASK, VFSUB_VV, 0x1, 0x10 }, // 2971 |
| 10262 | { PseudoVFSUB_VV_M2_E32, VFSUB_VV, 0x1, 0x20 }, // 2972 |
| 10263 | { PseudoVFSUB_VV_M2_E32_MASK, VFSUB_VV, 0x1, 0x20 }, // 2973 |
| 10264 | { PseudoVFSUB_VV_M2_E64, VFSUB_VV, 0x1, 0x40 }, // 2974 |
| 10265 | { PseudoVFSUB_VV_M2_E64_MASK, VFSUB_VV, 0x1, 0x40 }, // 2975 |
| 10266 | { PseudoVFSUB_VV_M4_E16, VFSUB_VV, 0x2, 0x10 }, // 2976 |
| 10267 | { PseudoVFSUB_VV_M4_E16_MASK, VFSUB_VV, 0x2, 0x10 }, // 2977 |
| 10268 | { PseudoVFSUB_VV_M4_E32, VFSUB_VV, 0x2, 0x20 }, // 2978 |
| 10269 | { PseudoVFSUB_VV_M4_E32_MASK, VFSUB_VV, 0x2, 0x20 }, // 2979 |
| 10270 | { PseudoVFSUB_VV_M4_E64, VFSUB_VV, 0x2, 0x40 }, // 2980 |
| 10271 | { PseudoVFSUB_VV_M4_E64_MASK, VFSUB_VV, 0x2, 0x40 }, // 2981 |
| 10272 | { PseudoVFSUB_VV_M8_E16, VFSUB_VV, 0x3, 0x10 }, // 2982 |
| 10273 | { PseudoVFSUB_VV_M8_E16_MASK, VFSUB_VV, 0x3, 0x10 }, // 2983 |
| 10274 | { PseudoVFSUB_VV_M8_E32, VFSUB_VV, 0x3, 0x20 }, // 2984 |
| 10275 | { PseudoVFSUB_VV_M8_E32_MASK, VFSUB_VV, 0x3, 0x20 }, // 2985 |
| 10276 | { PseudoVFSUB_VV_M8_E64, VFSUB_VV, 0x3, 0x40 }, // 2986 |
| 10277 | { PseudoVFSUB_VV_M8_E64_MASK, VFSUB_VV, 0x3, 0x40 }, // 2987 |
| 10278 | { PseudoVFSUB_VV_MF4_E16, VFSUB_VV, 0x6, 0x10 }, // 2988 |
| 10279 | { PseudoVFSUB_VV_MF4_E16_MASK, VFSUB_VV, 0x6, 0x10 }, // 2989 |
| 10280 | { PseudoVFSUB_VV_MF2_E16, VFSUB_VV, 0x7, 0x10 }, // 2990 |
| 10281 | { PseudoVFSUB_VV_MF2_E16_MASK, VFSUB_VV, 0x7, 0x10 }, // 2991 |
| 10282 | { PseudoVFSUB_VV_MF2_E32, VFSUB_VV, 0x7, 0x20 }, // 2992 |
| 10283 | { PseudoVFSUB_VV_MF2_E32_MASK, VFSUB_VV, 0x7, 0x20 }, // 2993 |
| 10284 | { PseudoVFWADD_VFPR16_M1_E16, VFWADD_VF, 0x0, 0x10 }, // 2994 |
| 10285 | { PseudoVFWADD_VFPR16_M1_E16_MASK, VFWADD_VF, 0x0, 0x10 }, // 2995 |
| 10286 | { PseudoVFWADD_VFPR32_M1_E32, VFWADD_VF, 0x0, 0x20 }, // 2996 |
| 10287 | { PseudoVFWADD_VFPR32_M1_E32_MASK, VFWADD_VF, 0x0, 0x20 }, // 2997 |
| 10288 | { PseudoVFWADD_VFPR16_M2_E16, VFWADD_VF, 0x1, 0x10 }, // 2998 |
| 10289 | { PseudoVFWADD_VFPR16_M2_E16_MASK, VFWADD_VF, 0x1, 0x10 }, // 2999 |
| 10290 | { PseudoVFWADD_VFPR32_M2_E32, VFWADD_VF, 0x1, 0x20 }, // 3000 |
| 10291 | { PseudoVFWADD_VFPR32_M2_E32_MASK, VFWADD_VF, 0x1, 0x20 }, // 3001 |
| 10292 | { PseudoVFWADD_VFPR16_M4_E16, VFWADD_VF, 0x2, 0x10 }, // 3002 |
| 10293 | { PseudoVFWADD_VFPR16_M4_E16_MASK, VFWADD_VF, 0x2, 0x10 }, // 3003 |
| 10294 | { PseudoVFWADD_VFPR32_M4_E32, VFWADD_VF, 0x2, 0x20 }, // 3004 |
| 10295 | { PseudoVFWADD_VFPR32_M4_E32_MASK, VFWADD_VF, 0x2, 0x20 }, // 3005 |
| 10296 | { PseudoVFWADD_VFPR16_MF4_E16, VFWADD_VF, 0x6, 0x10 }, // 3006 |
| 10297 | { PseudoVFWADD_VFPR16_MF4_E16_MASK, VFWADD_VF, 0x6, 0x10 }, // 3007 |
| 10298 | { PseudoVFWADD_VFPR16_MF2_E16, VFWADD_VF, 0x7, 0x10 }, // 3008 |
| 10299 | { PseudoVFWADD_VFPR16_MF2_E16_MASK, VFWADD_VF, 0x7, 0x10 }, // 3009 |
| 10300 | { PseudoVFWADD_VFPR32_MF2_E32, VFWADD_VF, 0x7, 0x20 }, // 3010 |
| 10301 | { PseudoVFWADD_VFPR32_MF2_E32_MASK, VFWADD_VF, 0x7, 0x20 }, // 3011 |
| 10302 | { PseudoVFWADD_VV_M1_E16, VFWADD_VV, 0x0, 0x10 }, // 3012 |
| 10303 | { PseudoVFWADD_VV_M1_E16_MASK, VFWADD_VV, 0x0, 0x10 }, // 3013 |
| 10304 | { PseudoVFWADD_VV_M1_E32, VFWADD_VV, 0x0, 0x20 }, // 3014 |
| 10305 | { PseudoVFWADD_VV_M1_E32_MASK, VFWADD_VV, 0x0, 0x20 }, // 3015 |
| 10306 | { PseudoVFWADD_VV_M2_E16, VFWADD_VV, 0x1, 0x10 }, // 3016 |
| 10307 | { PseudoVFWADD_VV_M2_E16_MASK, VFWADD_VV, 0x1, 0x10 }, // 3017 |
| 10308 | { PseudoVFWADD_VV_M2_E32, VFWADD_VV, 0x1, 0x20 }, // 3018 |
| 10309 | { PseudoVFWADD_VV_M2_E32_MASK, VFWADD_VV, 0x1, 0x20 }, // 3019 |
| 10310 | { PseudoVFWADD_VV_M4_E16, VFWADD_VV, 0x2, 0x10 }, // 3020 |
| 10311 | { PseudoVFWADD_VV_M4_E16_MASK, VFWADD_VV, 0x2, 0x10 }, // 3021 |
| 10312 | { PseudoVFWADD_VV_M4_E32, VFWADD_VV, 0x2, 0x20 }, // 3022 |
| 10313 | { PseudoVFWADD_VV_M4_E32_MASK, VFWADD_VV, 0x2, 0x20 }, // 3023 |
| 10314 | { PseudoVFWADD_VV_MF4_E16, VFWADD_VV, 0x6, 0x10 }, // 3024 |
| 10315 | { PseudoVFWADD_VV_MF4_E16_MASK, VFWADD_VV, 0x6, 0x10 }, // 3025 |
| 10316 | { PseudoVFWADD_VV_MF2_E16, VFWADD_VV, 0x7, 0x10 }, // 3026 |
| 10317 | { PseudoVFWADD_VV_MF2_E16_MASK, VFWADD_VV, 0x7, 0x10 }, // 3027 |
| 10318 | { PseudoVFWADD_VV_MF2_E32, VFWADD_VV, 0x7, 0x20 }, // 3028 |
| 10319 | { PseudoVFWADD_VV_MF2_E32_MASK, VFWADD_VV, 0x7, 0x20 }, // 3029 |
| 10320 | { PseudoVFWADD_WFPR16_M1_E16, VFWADD_WF, 0x0, 0x10 }, // 3030 |
| 10321 | { PseudoVFWADD_WFPR16_M1_E16_MASK, VFWADD_WF, 0x0, 0x10 }, // 3031 |
| 10322 | { PseudoVFWADD_WFPR32_M1_E32, VFWADD_WF, 0x0, 0x20 }, // 3032 |
| 10323 | { PseudoVFWADD_WFPR32_M1_E32_MASK, VFWADD_WF, 0x0, 0x20 }, // 3033 |
| 10324 | { PseudoVFWADD_WFPR16_M2_E16, VFWADD_WF, 0x1, 0x10 }, // 3034 |
| 10325 | { PseudoVFWADD_WFPR16_M2_E16_MASK, VFWADD_WF, 0x1, 0x10 }, // 3035 |
| 10326 | { PseudoVFWADD_WFPR32_M2_E32, VFWADD_WF, 0x1, 0x20 }, // 3036 |
| 10327 | { PseudoVFWADD_WFPR32_M2_E32_MASK, VFWADD_WF, 0x1, 0x20 }, // 3037 |
| 10328 | { PseudoVFWADD_WFPR16_M4_E16, VFWADD_WF, 0x2, 0x10 }, // 3038 |
| 10329 | { PseudoVFWADD_WFPR16_M4_E16_MASK, VFWADD_WF, 0x2, 0x10 }, // 3039 |
| 10330 | { PseudoVFWADD_WFPR32_M4_E32, VFWADD_WF, 0x2, 0x20 }, // 3040 |
| 10331 | { PseudoVFWADD_WFPR32_M4_E32_MASK, VFWADD_WF, 0x2, 0x20 }, // 3041 |
| 10332 | { PseudoVFWADD_WFPR16_MF4_E16, VFWADD_WF, 0x6, 0x10 }, // 3042 |
| 10333 | { PseudoVFWADD_WFPR16_MF4_E16_MASK, VFWADD_WF, 0x6, 0x10 }, // 3043 |
| 10334 | { PseudoVFWADD_WFPR16_MF2_E16, VFWADD_WF, 0x7, 0x10 }, // 3044 |
| 10335 | { PseudoVFWADD_WFPR16_MF2_E16_MASK, VFWADD_WF, 0x7, 0x10 }, // 3045 |
| 10336 | { PseudoVFWADD_WFPR32_MF2_E32, VFWADD_WF, 0x7, 0x20 }, // 3046 |
| 10337 | { PseudoVFWADD_WFPR32_MF2_E32_MASK, VFWADD_WF, 0x7, 0x20 }, // 3047 |
| 10338 | { PseudoVFWADD_WV_M1_E16_MASK_TIED, VFWADD_WV, 0x0, 0x0 }, // 3048 |
| 10339 | { PseudoVFWADD_WV_M1_E16_TIED, VFWADD_WV, 0x0, 0x0 }, // 3049 |
| 10340 | { PseudoVFWADD_WV_M1_E32_MASK_TIED, VFWADD_WV, 0x0, 0x0 }, // 3050 |
| 10341 | { PseudoVFWADD_WV_M1_E32_TIED, VFWADD_WV, 0x0, 0x0 }, // 3051 |
| 10342 | { PseudoVFWADD_WV_M1_E16, VFWADD_WV, 0x0, 0x10 }, // 3052 |
| 10343 | { PseudoVFWADD_WV_M1_E16_MASK, VFWADD_WV, 0x0, 0x10 }, // 3053 |
| 10344 | { PseudoVFWADD_WV_M1_E32, VFWADD_WV, 0x0, 0x20 }, // 3054 |
| 10345 | { PseudoVFWADD_WV_M1_E32_MASK, VFWADD_WV, 0x0, 0x20 }, // 3055 |
| 10346 | { PseudoVFWADD_WV_M2_E16_MASK_TIED, VFWADD_WV, 0x1, 0x0 }, // 3056 |
| 10347 | { PseudoVFWADD_WV_M2_E16_TIED, VFWADD_WV, 0x1, 0x0 }, // 3057 |
| 10348 | { PseudoVFWADD_WV_M2_E32_MASK_TIED, VFWADD_WV, 0x1, 0x0 }, // 3058 |
| 10349 | { PseudoVFWADD_WV_M2_E32_TIED, VFWADD_WV, 0x1, 0x0 }, // 3059 |
| 10350 | { PseudoVFWADD_WV_M2_E16, VFWADD_WV, 0x1, 0x10 }, // 3060 |
| 10351 | { PseudoVFWADD_WV_M2_E16_MASK, VFWADD_WV, 0x1, 0x10 }, // 3061 |
| 10352 | { PseudoVFWADD_WV_M2_E32, VFWADD_WV, 0x1, 0x20 }, // 3062 |
| 10353 | { PseudoVFWADD_WV_M2_E32_MASK, VFWADD_WV, 0x1, 0x20 }, // 3063 |
| 10354 | { PseudoVFWADD_WV_M4_E16_MASK_TIED, VFWADD_WV, 0x2, 0x0 }, // 3064 |
| 10355 | { PseudoVFWADD_WV_M4_E16_TIED, VFWADD_WV, 0x2, 0x0 }, // 3065 |
| 10356 | { PseudoVFWADD_WV_M4_E32_MASK_TIED, VFWADD_WV, 0x2, 0x0 }, // 3066 |
| 10357 | { PseudoVFWADD_WV_M4_E32_TIED, VFWADD_WV, 0x2, 0x0 }, // 3067 |
| 10358 | { PseudoVFWADD_WV_M4_E16, VFWADD_WV, 0x2, 0x10 }, // 3068 |
| 10359 | { PseudoVFWADD_WV_M4_E16_MASK, VFWADD_WV, 0x2, 0x10 }, // 3069 |
| 10360 | { PseudoVFWADD_WV_M4_E32, VFWADD_WV, 0x2, 0x20 }, // 3070 |
| 10361 | { PseudoVFWADD_WV_M4_E32_MASK, VFWADD_WV, 0x2, 0x20 }, // 3071 |
| 10362 | { PseudoVFWADD_WV_MF4_E16_MASK_TIED, VFWADD_WV, 0x6, 0x0 }, // 3072 |
| 10363 | { PseudoVFWADD_WV_MF4_E16_TIED, VFWADD_WV, 0x6, 0x0 }, // 3073 |
| 10364 | { PseudoVFWADD_WV_MF4_E16, VFWADD_WV, 0x6, 0x10 }, // 3074 |
| 10365 | { PseudoVFWADD_WV_MF4_E16_MASK, VFWADD_WV, 0x6, 0x10 }, // 3075 |
| 10366 | { PseudoVFWADD_WV_MF2_E16_MASK_TIED, VFWADD_WV, 0x7, 0x0 }, // 3076 |
| 10367 | { PseudoVFWADD_WV_MF2_E16_TIED, VFWADD_WV, 0x7, 0x0 }, // 3077 |
| 10368 | { PseudoVFWADD_WV_MF2_E32_MASK_TIED, VFWADD_WV, 0x7, 0x0 }, // 3078 |
| 10369 | { PseudoVFWADD_WV_MF2_E32_TIED, VFWADD_WV, 0x7, 0x0 }, // 3079 |
| 10370 | { PseudoVFWADD_WV_MF2_E16, VFWADD_WV, 0x7, 0x10 }, // 3080 |
| 10371 | { PseudoVFWADD_WV_MF2_E16_MASK, VFWADD_WV, 0x7, 0x10 }, // 3081 |
| 10372 | { PseudoVFWADD_WV_MF2_E32, VFWADD_WV, 0x7, 0x20 }, // 3082 |
| 10373 | { PseudoVFWADD_WV_MF2_E32_MASK, VFWADD_WV, 0x7, 0x20 }, // 3083 |
| 10374 | { PseudoVFWCVTBF16_F_F_V_M1_E16, VFWCVTBF16_F_F_V, 0x0, 0x10 }, // 3084 |
| 10375 | { PseudoVFWCVTBF16_F_F_V_M1_E16_MASK, VFWCVTBF16_F_F_V, 0x0, 0x10 }, // 3085 |
| 10376 | { PseudoVFWCVTBF16_F_F_V_M1_E32, VFWCVTBF16_F_F_V, 0x0, 0x20 }, // 3086 |
| 10377 | { PseudoVFWCVTBF16_F_F_V_M1_E32_MASK, VFWCVTBF16_F_F_V, 0x0, 0x20 }, // 3087 |
| 10378 | { PseudoVFWCVTBF16_F_F_V_M2_E16, VFWCVTBF16_F_F_V, 0x1, 0x10 }, // 3088 |
| 10379 | { PseudoVFWCVTBF16_F_F_V_M2_E16_MASK, VFWCVTBF16_F_F_V, 0x1, 0x10 }, // 3089 |
| 10380 | { PseudoVFWCVTBF16_F_F_V_M2_E32, VFWCVTBF16_F_F_V, 0x1, 0x20 }, // 3090 |
| 10381 | { PseudoVFWCVTBF16_F_F_V_M2_E32_MASK, VFWCVTBF16_F_F_V, 0x1, 0x20 }, // 3091 |
| 10382 | { PseudoVFWCVTBF16_F_F_V_M4_E16, VFWCVTBF16_F_F_V, 0x2, 0x10 }, // 3092 |
| 10383 | { PseudoVFWCVTBF16_F_F_V_M4_E16_MASK, VFWCVTBF16_F_F_V, 0x2, 0x10 }, // 3093 |
| 10384 | { PseudoVFWCVTBF16_F_F_V_M4_E32, VFWCVTBF16_F_F_V, 0x2, 0x20 }, // 3094 |
| 10385 | { PseudoVFWCVTBF16_F_F_V_M4_E32_MASK, VFWCVTBF16_F_F_V, 0x2, 0x20 }, // 3095 |
| 10386 | { PseudoVFWCVTBF16_F_F_V_MF4_E16, VFWCVTBF16_F_F_V, 0x6, 0x10 }, // 3096 |
| 10387 | { PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK, VFWCVTBF16_F_F_V, 0x6, 0x10 }, // 3097 |
| 10388 | { PseudoVFWCVTBF16_F_F_V_MF2_E16, VFWCVTBF16_F_F_V, 0x7, 0x10 }, // 3098 |
| 10389 | { PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK, VFWCVTBF16_F_F_V, 0x7, 0x10 }, // 3099 |
| 10390 | { PseudoVFWCVTBF16_F_F_V_MF2_E32, VFWCVTBF16_F_F_V, 0x7, 0x20 }, // 3100 |
| 10391 | { PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK, VFWCVTBF16_F_F_V, 0x7, 0x20 }, // 3101 |
| 10392 | { PseudoVFWCVT_F_F_V_M1_E16, VFWCVT_F_F_V, 0x0, 0x10 }, // 3102 |
| 10393 | { PseudoVFWCVT_F_F_V_M1_E16_MASK, VFWCVT_F_F_V, 0x0, 0x10 }, // 3103 |
| 10394 | { PseudoVFWCVT_F_F_V_M1_E32, VFWCVT_F_F_V, 0x0, 0x20 }, // 3104 |
| 10395 | { PseudoVFWCVT_F_F_V_M1_E32_MASK, VFWCVT_F_F_V, 0x0, 0x20 }, // 3105 |
| 10396 | { PseudoVFWCVT_F_F_V_M2_E16, VFWCVT_F_F_V, 0x1, 0x10 }, // 3106 |
| 10397 | { PseudoVFWCVT_F_F_V_M2_E16_MASK, VFWCVT_F_F_V, 0x1, 0x10 }, // 3107 |
| 10398 | { PseudoVFWCVT_F_F_V_M2_E32, VFWCVT_F_F_V, 0x1, 0x20 }, // 3108 |
| 10399 | { PseudoVFWCVT_F_F_V_M2_E32_MASK, VFWCVT_F_F_V, 0x1, 0x20 }, // 3109 |
| 10400 | { PseudoVFWCVT_F_F_V_M4_E16, VFWCVT_F_F_V, 0x2, 0x10 }, // 3110 |
| 10401 | { PseudoVFWCVT_F_F_V_M4_E16_MASK, VFWCVT_F_F_V, 0x2, 0x10 }, // 3111 |
| 10402 | { PseudoVFWCVT_F_F_V_M4_E32, VFWCVT_F_F_V, 0x2, 0x20 }, // 3112 |
| 10403 | { PseudoVFWCVT_F_F_V_M4_E32_MASK, VFWCVT_F_F_V, 0x2, 0x20 }, // 3113 |
| 10404 | { PseudoVFWCVT_F_F_V_MF4_E16, VFWCVT_F_F_V, 0x6, 0x10 }, // 3114 |
| 10405 | { PseudoVFWCVT_F_F_V_MF4_E16_MASK, VFWCVT_F_F_V, 0x6, 0x10 }, // 3115 |
| 10406 | { PseudoVFWCVT_F_F_V_MF2_E16, VFWCVT_F_F_V, 0x7, 0x10 }, // 3116 |
| 10407 | { PseudoVFWCVT_F_F_V_MF2_E16_MASK, VFWCVT_F_F_V, 0x7, 0x10 }, // 3117 |
| 10408 | { PseudoVFWCVT_F_F_V_MF2_E32, VFWCVT_F_F_V, 0x7, 0x20 }, // 3118 |
| 10409 | { PseudoVFWCVT_F_F_V_MF2_E32_MASK, VFWCVT_F_F_V, 0x7, 0x20 }, // 3119 |
| 10410 | { PseudoVFWCVT_F_XU_V_M1_E8, VFWCVT_F_XU_V, 0x0, 0x8 }, // 3120 |
| 10411 | { PseudoVFWCVT_F_XU_V_M1_E8_MASK, VFWCVT_F_XU_V, 0x0, 0x8 }, // 3121 |
| 10412 | { PseudoVFWCVT_F_XU_V_M1_E16, VFWCVT_F_XU_V, 0x0, 0x10 }, // 3122 |
| 10413 | { PseudoVFWCVT_F_XU_V_M1_E16_MASK, VFWCVT_F_XU_V, 0x0, 0x10 }, // 3123 |
| 10414 | { PseudoVFWCVT_F_XU_V_M1_E32, VFWCVT_F_XU_V, 0x0, 0x20 }, // 3124 |
| 10415 | { PseudoVFWCVT_F_XU_V_M1_E32_MASK, VFWCVT_F_XU_V, 0x0, 0x20 }, // 3125 |
| 10416 | { PseudoVFWCVT_F_XU_V_M2_E8, VFWCVT_F_XU_V, 0x1, 0x8 }, // 3126 |
| 10417 | { PseudoVFWCVT_F_XU_V_M2_E8_MASK, VFWCVT_F_XU_V, 0x1, 0x8 }, // 3127 |
| 10418 | { PseudoVFWCVT_F_XU_V_M2_E16, VFWCVT_F_XU_V, 0x1, 0x10 }, // 3128 |
| 10419 | { PseudoVFWCVT_F_XU_V_M2_E16_MASK, VFWCVT_F_XU_V, 0x1, 0x10 }, // 3129 |
| 10420 | { PseudoVFWCVT_F_XU_V_M2_E32, VFWCVT_F_XU_V, 0x1, 0x20 }, // 3130 |
| 10421 | { PseudoVFWCVT_F_XU_V_M2_E32_MASK, VFWCVT_F_XU_V, 0x1, 0x20 }, // 3131 |
| 10422 | { PseudoVFWCVT_F_XU_V_M4_E8, VFWCVT_F_XU_V, 0x2, 0x8 }, // 3132 |
| 10423 | { PseudoVFWCVT_F_XU_V_M4_E8_MASK, VFWCVT_F_XU_V, 0x2, 0x8 }, // 3133 |
| 10424 | { PseudoVFWCVT_F_XU_V_M4_E16, VFWCVT_F_XU_V, 0x2, 0x10 }, // 3134 |
| 10425 | { PseudoVFWCVT_F_XU_V_M4_E16_MASK, VFWCVT_F_XU_V, 0x2, 0x10 }, // 3135 |
| 10426 | { PseudoVFWCVT_F_XU_V_M4_E32, VFWCVT_F_XU_V, 0x2, 0x20 }, // 3136 |
| 10427 | { PseudoVFWCVT_F_XU_V_M4_E32_MASK, VFWCVT_F_XU_V, 0x2, 0x20 }, // 3137 |
| 10428 | { PseudoVFWCVT_F_XU_V_MF8_E8, VFWCVT_F_XU_V, 0x5, 0x8 }, // 3138 |
| 10429 | { PseudoVFWCVT_F_XU_V_MF8_E8_MASK, VFWCVT_F_XU_V, 0x5, 0x8 }, // 3139 |
| 10430 | { PseudoVFWCVT_F_XU_V_MF4_E8, VFWCVT_F_XU_V, 0x6, 0x8 }, // 3140 |
| 10431 | { PseudoVFWCVT_F_XU_V_MF4_E8_MASK, VFWCVT_F_XU_V, 0x6, 0x8 }, // 3141 |
| 10432 | { PseudoVFWCVT_F_XU_V_MF4_E16, VFWCVT_F_XU_V, 0x6, 0x10 }, // 3142 |
| 10433 | { PseudoVFWCVT_F_XU_V_MF4_E16_MASK, VFWCVT_F_XU_V, 0x6, 0x10 }, // 3143 |
| 10434 | { PseudoVFWCVT_F_XU_V_MF2_E8, VFWCVT_F_XU_V, 0x7, 0x8 }, // 3144 |
| 10435 | { PseudoVFWCVT_F_XU_V_MF2_E8_MASK, VFWCVT_F_XU_V, 0x7, 0x8 }, // 3145 |
| 10436 | { PseudoVFWCVT_F_XU_V_MF2_E16, VFWCVT_F_XU_V, 0x7, 0x10 }, // 3146 |
| 10437 | { PseudoVFWCVT_F_XU_V_MF2_E16_MASK, VFWCVT_F_XU_V, 0x7, 0x10 }, // 3147 |
| 10438 | { PseudoVFWCVT_F_XU_V_MF2_E32, VFWCVT_F_XU_V, 0x7, 0x20 }, // 3148 |
| 10439 | { PseudoVFWCVT_F_XU_V_MF2_E32_MASK, VFWCVT_F_XU_V, 0x7, 0x20 }, // 3149 |
| 10440 | { PseudoVFWCVT_F_X_V_M1_E8, VFWCVT_F_X_V, 0x0, 0x8 }, // 3150 |
| 10441 | { PseudoVFWCVT_F_X_V_M1_E8_MASK, VFWCVT_F_X_V, 0x0, 0x8 }, // 3151 |
| 10442 | { PseudoVFWCVT_F_X_V_M1_E16, VFWCVT_F_X_V, 0x0, 0x10 }, // 3152 |
| 10443 | { PseudoVFWCVT_F_X_V_M1_E16_MASK, VFWCVT_F_X_V, 0x0, 0x10 }, // 3153 |
| 10444 | { PseudoVFWCVT_F_X_V_M1_E32, VFWCVT_F_X_V, 0x0, 0x20 }, // 3154 |
| 10445 | { PseudoVFWCVT_F_X_V_M1_E32_MASK, VFWCVT_F_X_V, 0x0, 0x20 }, // 3155 |
| 10446 | { PseudoVFWCVT_F_X_V_M2_E8, VFWCVT_F_X_V, 0x1, 0x8 }, // 3156 |
| 10447 | { PseudoVFWCVT_F_X_V_M2_E8_MASK, VFWCVT_F_X_V, 0x1, 0x8 }, // 3157 |
| 10448 | { PseudoVFWCVT_F_X_V_M2_E16, VFWCVT_F_X_V, 0x1, 0x10 }, // 3158 |
| 10449 | { PseudoVFWCVT_F_X_V_M2_E16_MASK, VFWCVT_F_X_V, 0x1, 0x10 }, // 3159 |
| 10450 | { PseudoVFWCVT_F_X_V_M2_E32, VFWCVT_F_X_V, 0x1, 0x20 }, // 3160 |
| 10451 | { PseudoVFWCVT_F_X_V_M2_E32_MASK, VFWCVT_F_X_V, 0x1, 0x20 }, // 3161 |
| 10452 | { PseudoVFWCVT_F_X_V_M4_E8, VFWCVT_F_X_V, 0x2, 0x8 }, // 3162 |
| 10453 | { PseudoVFWCVT_F_X_V_M4_E8_MASK, VFWCVT_F_X_V, 0x2, 0x8 }, // 3163 |
| 10454 | { PseudoVFWCVT_F_X_V_M4_E16, VFWCVT_F_X_V, 0x2, 0x10 }, // 3164 |
| 10455 | { PseudoVFWCVT_F_X_V_M4_E16_MASK, VFWCVT_F_X_V, 0x2, 0x10 }, // 3165 |
| 10456 | { PseudoVFWCVT_F_X_V_M4_E32, VFWCVT_F_X_V, 0x2, 0x20 }, // 3166 |
| 10457 | { PseudoVFWCVT_F_X_V_M4_E32_MASK, VFWCVT_F_X_V, 0x2, 0x20 }, // 3167 |
| 10458 | { PseudoVFWCVT_F_X_V_MF8_E8, VFWCVT_F_X_V, 0x5, 0x8 }, // 3168 |
| 10459 | { PseudoVFWCVT_F_X_V_MF8_E8_MASK, VFWCVT_F_X_V, 0x5, 0x8 }, // 3169 |
| 10460 | { PseudoVFWCVT_F_X_V_MF4_E8, VFWCVT_F_X_V, 0x6, 0x8 }, // 3170 |
| 10461 | { PseudoVFWCVT_F_X_V_MF4_E8_MASK, VFWCVT_F_X_V, 0x6, 0x8 }, // 3171 |
| 10462 | { PseudoVFWCVT_F_X_V_MF4_E16, VFWCVT_F_X_V, 0x6, 0x10 }, // 3172 |
| 10463 | { PseudoVFWCVT_F_X_V_MF4_E16_MASK, VFWCVT_F_X_V, 0x6, 0x10 }, // 3173 |
| 10464 | { PseudoVFWCVT_F_X_V_MF2_E8, VFWCVT_F_X_V, 0x7, 0x8 }, // 3174 |
| 10465 | { PseudoVFWCVT_F_X_V_MF2_E8_MASK, VFWCVT_F_X_V, 0x7, 0x8 }, // 3175 |
| 10466 | { PseudoVFWCVT_F_X_V_MF2_E16, VFWCVT_F_X_V, 0x7, 0x10 }, // 3176 |
| 10467 | { PseudoVFWCVT_F_X_V_MF2_E16_MASK, VFWCVT_F_X_V, 0x7, 0x10 }, // 3177 |
| 10468 | { PseudoVFWCVT_F_X_V_MF2_E32, VFWCVT_F_X_V, 0x7, 0x20 }, // 3178 |
| 10469 | { PseudoVFWCVT_F_X_V_MF2_E32_MASK, VFWCVT_F_X_V, 0x7, 0x20 }, // 3179 |
| 10470 | { PseudoVFWCVT_RTZ_XU_F_V_M1, VFWCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 3180 |
| 10471 | { PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, VFWCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 3181 |
| 10472 | { PseudoVFWCVT_RTZ_XU_F_V_M2, VFWCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 3182 |
| 10473 | { PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, VFWCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 3183 |
| 10474 | { PseudoVFWCVT_RTZ_XU_F_V_M4, VFWCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 3184 |
| 10475 | { PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, VFWCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 3185 |
| 10476 | { PseudoVFWCVT_RTZ_XU_F_V_MF4, VFWCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 3186 |
| 10477 | { PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, VFWCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 3187 |
| 10478 | { PseudoVFWCVT_RTZ_XU_F_V_MF2, VFWCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 3188 |
| 10479 | { PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, VFWCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 3189 |
| 10480 | { PseudoVFWCVT_RTZ_X_F_V_M1, VFWCVT_RTZ_X_F_V, 0x0, 0x0 }, // 3190 |
| 10481 | { PseudoVFWCVT_RTZ_X_F_V_M1_MASK, VFWCVT_RTZ_X_F_V, 0x0, 0x0 }, // 3191 |
| 10482 | { PseudoVFWCVT_RTZ_X_F_V_M2, VFWCVT_RTZ_X_F_V, 0x1, 0x0 }, // 3192 |
| 10483 | { PseudoVFWCVT_RTZ_X_F_V_M2_MASK, VFWCVT_RTZ_X_F_V, 0x1, 0x0 }, // 3193 |
| 10484 | { PseudoVFWCVT_RTZ_X_F_V_M4, VFWCVT_RTZ_X_F_V, 0x2, 0x0 }, // 3194 |
| 10485 | { PseudoVFWCVT_RTZ_X_F_V_M4_MASK, VFWCVT_RTZ_X_F_V, 0x2, 0x0 }, // 3195 |
| 10486 | { PseudoVFWCVT_RTZ_X_F_V_MF4, VFWCVT_RTZ_X_F_V, 0x6, 0x0 }, // 3196 |
| 10487 | { PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, VFWCVT_RTZ_X_F_V, 0x6, 0x0 }, // 3197 |
| 10488 | { PseudoVFWCVT_RTZ_X_F_V_MF2, VFWCVT_RTZ_X_F_V, 0x7, 0x0 }, // 3198 |
| 10489 | { PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, VFWCVT_RTZ_X_F_V, 0x7, 0x0 }, // 3199 |
| 10490 | { PseudoVFWCVT_RM_XU_F_V_M1, VFWCVT_XU_F_V, 0x0, 0x0 }, // 3200 |
| 10491 | { PseudoVFWCVT_RM_XU_F_V_M1_MASK, VFWCVT_XU_F_V, 0x0, 0x0 }, // 3201 |
| 10492 | { PseudoVFWCVT_XU_F_V_M1, VFWCVT_XU_F_V, 0x0, 0x0 }, // 3202 |
| 10493 | { PseudoVFWCVT_XU_F_V_M1_MASK, VFWCVT_XU_F_V, 0x0, 0x0 }, // 3203 |
| 10494 | { PseudoVFWCVT_RM_XU_F_V_M2, VFWCVT_XU_F_V, 0x1, 0x0 }, // 3204 |
| 10495 | { PseudoVFWCVT_RM_XU_F_V_M2_MASK, VFWCVT_XU_F_V, 0x1, 0x0 }, // 3205 |
| 10496 | { PseudoVFWCVT_XU_F_V_M2, VFWCVT_XU_F_V, 0x1, 0x0 }, // 3206 |
| 10497 | { PseudoVFWCVT_XU_F_V_M2_MASK, VFWCVT_XU_F_V, 0x1, 0x0 }, // 3207 |
| 10498 | { PseudoVFWCVT_RM_XU_F_V_M4, VFWCVT_XU_F_V, 0x2, 0x0 }, // 3208 |
| 10499 | { PseudoVFWCVT_RM_XU_F_V_M4_MASK, VFWCVT_XU_F_V, 0x2, 0x0 }, // 3209 |
| 10500 | { PseudoVFWCVT_XU_F_V_M4, VFWCVT_XU_F_V, 0x2, 0x0 }, // 3210 |
| 10501 | { PseudoVFWCVT_XU_F_V_M4_MASK, VFWCVT_XU_F_V, 0x2, 0x0 }, // 3211 |
| 10502 | { PseudoVFWCVT_RM_XU_F_V_MF4, VFWCVT_XU_F_V, 0x6, 0x0 }, // 3212 |
| 10503 | { PseudoVFWCVT_RM_XU_F_V_MF4_MASK, VFWCVT_XU_F_V, 0x6, 0x0 }, // 3213 |
| 10504 | { PseudoVFWCVT_XU_F_V_MF4, VFWCVT_XU_F_V, 0x6, 0x0 }, // 3214 |
| 10505 | { PseudoVFWCVT_XU_F_V_MF4_MASK, VFWCVT_XU_F_V, 0x6, 0x0 }, // 3215 |
| 10506 | { PseudoVFWCVT_RM_XU_F_V_MF2, VFWCVT_XU_F_V, 0x7, 0x0 }, // 3216 |
| 10507 | { PseudoVFWCVT_RM_XU_F_V_MF2_MASK, VFWCVT_XU_F_V, 0x7, 0x0 }, // 3217 |
| 10508 | { PseudoVFWCVT_XU_F_V_MF2, VFWCVT_XU_F_V, 0x7, 0x0 }, // 3218 |
| 10509 | { PseudoVFWCVT_XU_F_V_MF2_MASK, VFWCVT_XU_F_V, 0x7, 0x0 }, // 3219 |
| 10510 | { PseudoVFWCVT_RM_X_F_V_M1, VFWCVT_X_F_V, 0x0, 0x0 }, // 3220 |
| 10511 | { PseudoVFWCVT_RM_X_F_V_M1_MASK, VFWCVT_X_F_V, 0x0, 0x0 }, // 3221 |
| 10512 | { PseudoVFWCVT_X_F_V_M1, VFWCVT_X_F_V, 0x0, 0x0 }, // 3222 |
| 10513 | { PseudoVFWCVT_X_F_V_M1_MASK, VFWCVT_X_F_V, 0x0, 0x0 }, // 3223 |
| 10514 | { PseudoVFWCVT_RM_X_F_V_M2, VFWCVT_X_F_V, 0x1, 0x0 }, // 3224 |
| 10515 | { PseudoVFWCVT_RM_X_F_V_M2_MASK, VFWCVT_X_F_V, 0x1, 0x0 }, // 3225 |
| 10516 | { PseudoVFWCVT_X_F_V_M2, VFWCVT_X_F_V, 0x1, 0x0 }, // 3226 |
| 10517 | { PseudoVFWCVT_X_F_V_M2_MASK, VFWCVT_X_F_V, 0x1, 0x0 }, // 3227 |
| 10518 | { PseudoVFWCVT_RM_X_F_V_M4, VFWCVT_X_F_V, 0x2, 0x0 }, // 3228 |
| 10519 | { PseudoVFWCVT_RM_X_F_V_M4_MASK, VFWCVT_X_F_V, 0x2, 0x0 }, // 3229 |
| 10520 | { PseudoVFWCVT_X_F_V_M4, VFWCVT_X_F_V, 0x2, 0x0 }, // 3230 |
| 10521 | { PseudoVFWCVT_X_F_V_M4_MASK, VFWCVT_X_F_V, 0x2, 0x0 }, // 3231 |
| 10522 | { PseudoVFWCVT_RM_X_F_V_MF4, VFWCVT_X_F_V, 0x6, 0x0 }, // 3232 |
| 10523 | { PseudoVFWCVT_RM_X_F_V_MF4_MASK, VFWCVT_X_F_V, 0x6, 0x0 }, // 3233 |
| 10524 | { PseudoVFWCVT_X_F_V_MF4, VFWCVT_X_F_V, 0x6, 0x0 }, // 3234 |
| 10525 | { PseudoVFWCVT_X_F_V_MF4_MASK, VFWCVT_X_F_V, 0x6, 0x0 }, // 3235 |
| 10526 | { PseudoVFWCVT_RM_X_F_V_MF2, VFWCVT_X_F_V, 0x7, 0x0 }, // 3236 |
| 10527 | { PseudoVFWCVT_RM_X_F_V_MF2_MASK, VFWCVT_X_F_V, 0x7, 0x0 }, // 3237 |
| 10528 | { PseudoVFWCVT_X_F_V_MF2, VFWCVT_X_F_V, 0x7, 0x0 }, // 3238 |
| 10529 | { PseudoVFWCVT_X_F_V_MF2_MASK, VFWCVT_X_F_V, 0x7, 0x0 }, // 3239 |
| 10530 | { PseudoVFWMACCBF16_VFPR16_M1_E16, VFWMACCBF16_VF, 0x0, 0x0 }, // 3240 |
| 10531 | { PseudoVFWMACCBF16_VFPR16_M1_E16_MASK, VFWMACCBF16_VF, 0x0, 0x0 }, // 3241 |
| 10532 | { PseudoVFWMACCBF16_VFPR16_M2_E16, VFWMACCBF16_VF, 0x1, 0x0 }, // 3242 |
| 10533 | { PseudoVFWMACCBF16_VFPR16_M2_E16_MASK, VFWMACCBF16_VF, 0x1, 0x0 }, // 3243 |
| 10534 | { PseudoVFWMACCBF16_VFPR16_M4_E16, VFWMACCBF16_VF, 0x2, 0x0 }, // 3244 |
| 10535 | { PseudoVFWMACCBF16_VFPR16_M4_E16_MASK, VFWMACCBF16_VF, 0x2, 0x0 }, // 3245 |
| 10536 | { PseudoVFWMACCBF16_VFPR16_MF4_E16, VFWMACCBF16_VF, 0x6, 0x0 }, // 3246 |
| 10537 | { PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK, VFWMACCBF16_VF, 0x6, 0x0 }, // 3247 |
| 10538 | { PseudoVFWMACCBF16_VFPR16_MF2_E16, VFWMACCBF16_VF, 0x7, 0x0 }, // 3248 |
| 10539 | { PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK, VFWMACCBF16_VF, 0x7, 0x0 }, // 3249 |
| 10540 | { PseudoVFWMACCBF16_VV_M1_E16, VFWMACCBF16_VV, 0x0, 0x0 }, // 3250 |
| 10541 | { PseudoVFWMACCBF16_VV_M1_E16_MASK, VFWMACCBF16_VV, 0x0, 0x0 }, // 3251 |
| 10542 | { PseudoVFWMACCBF16_VV_M1_E32, VFWMACCBF16_VV, 0x0, 0x0 }, // 3252 |
| 10543 | { PseudoVFWMACCBF16_VV_M1_E32_MASK, VFWMACCBF16_VV, 0x0, 0x0 }, // 3253 |
| 10544 | { PseudoVFWMACCBF16_VV_M2_E16, VFWMACCBF16_VV, 0x1, 0x0 }, // 3254 |
| 10545 | { PseudoVFWMACCBF16_VV_M2_E16_MASK, VFWMACCBF16_VV, 0x1, 0x0 }, // 3255 |
| 10546 | { PseudoVFWMACCBF16_VV_M2_E32, VFWMACCBF16_VV, 0x1, 0x0 }, // 3256 |
| 10547 | { PseudoVFWMACCBF16_VV_M2_E32_MASK, VFWMACCBF16_VV, 0x1, 0x0 }, // 3257 |
| 10548 | { PseudoVFWMACCBF16_VV_M4_E16, VFWMACCBF16_VV, 0x2, 0x0 }, // 3258 |
| 10549 | { PseudoVFWMACCBF16_VV_M4_E16_MASK, VFWMACCBF16_VV, 0x2, 0x0 }, // 3259 |
| 10550 | { PseudoVFWMACCBF16_VV_M4_E32, VFWMACCBF16_VV, 0x2, 0x0 }, // 3260 |
| 10551 | { PseudoVFWMACCBF16_VV_M4_E32_MASK, VFWMACCBF16_VV, 0x2, 0x0 }, // 3261 |
| 10552 | { PseudoVFWMACCBF16_VV_MF4_E16, VFWMACCBF16_VV, 0x6, 0x0 }, // 3262 |
| 10553 | { PseudoVFWMACCBF16_VV_MF4_E16_MASK, VFWMACCBF16_VV, 0x6, 0x0 }, // 3263 |
| 10554 | { PseudoVFWMACCBF16_VV_MF2_E16, VFWMACCBF16_VV, 0x7, 0x0 }, // 3264 |
| 10555 | { PseudoVFWMACCBF16_VV_MF2_E16_MASK, VFWMACCBF16_VV, 0x7, 0x0 }, // 3265 |
| 10556 | { PseudoVFWMACCBF16_VV_MF2_E32, VFWMACCBF16_VV, 0x7, 0x0 }, // 3266 |
| 10557 | { PseudoVFWMACCBF16_VV_MF2_E32_MASK, VFWMACCBF16_VV, 0x7, 0x0 }, // 3267 |
| 10558 | { PseudoVFWMACC_4x4x4_M1, VFWMACC_4x4x4, 0x0, 0x0 }, // 3268 |
| 10559 | { PseudoVFWMACC_4x4x4_M2, VFWMACC_4x4x4, 0x1, 0x0 }, // 3269 |
| 10560 | { PseudoVFWMACC_4x4x4_M4, VFWMACC_4x4x4, 0x2, 0x0 }, // 3270 |
| 10561 | { PseudoVFWMACC_4x4x4_M8, VFWMACC_4x4x4, 0x3, 0x0 }, // 3271 |
| 10562 | { PseudoVFWMACC_4x4x4_MF4, VFWMACC_4x4x4, 0x6, 0x0 }, // 3272 |
| 10563 | { PseudoVFWMACC_4x4x4_MF2, VFWMACC_4x4x4, 0x7, 0x0 }, // 3273 |
| 10564 | { PseudoVFWMACC_VFPR16_M1_E16, VFWMACC_VF, 0x0, 0x0 }, // 3274 |
| 10565 | { PseudoVFWMACC_VFPR16_M1_E16_MASK, VFWMACC_VF, 0x0, 0x0 }, // 3275 |
| 10566 | { PseudoVFWMACC_VFPR32_M1_E32, VFWMACC_VF, 0x0, 0x0 }, // 3276 |
| 10567 | { PseudoVFWMACC_VFPR32_M1_E32_MASK, VFWMACC_VF, 0x0, 0x0 }, // 3277 |
| 10568 | { PseudoVFWMACC_VFPR16_M2_E16, VFWMACC_VF, 0x1, 0x0 }, // 3278 |
| 10569 | { PseudoVFWMACC_VFPR16_M2_E16_MASK, VFWMACC_VF, 0x1, 0x0 }, // 3279 |
| 10570 | { PseudoVFWMACC_VFPR32_M2_E32, VFWMACC_VF, 0x1, 0x0 }, // 3280 |
| 10571 | { PseudoVFWMACC_VFPR32_M2_E32_MASK, VFWMACC_VF, 0x1, 0x0 }, // 3281 |
| 10572 | { PseudoVFWMACC_VFPR16_M4_E16, VFWMACC_VF, 0x2, 0x0 }, // 3282 |
| 10573 | { PseudoVFWMACC_VFPR16_M4_E16_MASK, VFWMACC_VF, 0x2, 0x0 }, // 3283 |
| 10574 | { PseudoVFWMACC_VFPR32_M4_E32, VFWMACC_VF, 0x2, 0x0 }, // 3284 |
| 10575 | { PseudoVFWMACC_VFPR32_M4_E32_MASK, VFWMACC_VF, 0x2, 0x0 }, // 3285 |
| 10576 | { PseudoVFWMACC_VFPR16_MF4_E16, VFWMACC_VF, 0x6, 0x0 }, // 3286 |
| 10577 | { PseudoVFWMACC_VFPR16_MF4_E16_MASK, VFWMACC_VF, 0x6, 0x0 }, // 3287 |
| 10578 | { PseudoVFWMACC_VFPR16_MF2_E16, VFWMACC_VF, 0x7, 0x0 }, // 3288 |
| 10579 | { PseudoVFWMACC_VFPR16_MF2_E16_MASK, VFWMACC_VF, 0x7, 0x0 }, // 3289 |
| 10580 | { PseudoVFWMACC_VFPR32_MF2_E32, VFWMACC_VF, 0x7, 0x0 }, // 3290 |
| 10581 | { PseudoVFWMACC_VFPR32_MF2_E32_MASK, VFWMACC_VF, 0x7, 0x0 }, // 3291 |
| 10582 | { PseudoVFWMACC_VV_M1_E16, VFWMACC_VV, 0x0, 0x0 }, // 3292 |
| 10583 | { PseudoVFWMACC_VV_M1_E16_MASK, VFWMACC_VV, 0x0, 0x0 }, // 3293 |
| 10584 | { PseudoVFWMACC_VV_M1_E32, VFWMACC_VV, 0x0, 0x0 }, // 3294 |
| 10585 | { PseudoVFWMACC_VV_M1_E32_MASK, VFWMACC_VV, 0x0, 0x0 }, // 3295 |
| 10586 | { PseudoVFWMACC_VV_M2_E16, VFWMACC_VV, 0x1, 0x0 }, // 3296 |
| 10587 | { PseudoVFWMACC_VV_M2_E16_MASK, VFWMACC_VV, 0x1, 0x0 }, // 3297 |
| 10588 | { PseudoVFWMACC_VV_M2_E32, VFWMACC_VV, 0x1, 0x0 }, // 3298 |
| 10589 | { PseudoVFWMACC_VV_M2_E32_MASK, VFWMACC_VV, 0x1, 0x0 }, // 3299 |
| 10590 | { PseudoVFWMACC_VV_M4_E16, VFWMACC_VV, 0x2, 0x0 }, // 3300 |
| 10591 | { PseudoVFWMACC_VV_M4_E16_MASK, VFWMACC_VV, 0x2, 0x0 }, // 3301 |
| 10592 | { PseudoVFWMACC_VV_M4_E32, VFWMACC_VV, 0x2, 0x0 }, // 3302 |
| 10593 | { PseudoVFWMACC_VV_M4_E32_MASK, VFWMACC_VV, 0x2, 0x0 }, // 3303 |
| 10594 | { PseudoVFWMACC_VV_MF4_E16, VFWMACC_VV, 0x6, 0x0 }, // 3304 |
| 10595 | { PseudoVFWMACC_VV_MF4_E16_MASK, VFWMACC_VV, 0x6, 0x0 }, // 3305 |
| 10596 | { PseudoVFWMACC_VV_MF2_E16, VFWMACC_VV, 0x7, 0x0 }, // 3306 |
| 10597 | { PseudoVFWMACC_VV_MF2_E16_MASK, VFWMACC_VV, 0x7, 0x0 }, // 3307 |
| 10598 | { PseudoVFWMACC_VV_MF2_E32, VFWMACC_VV, 0x7, 0x0 }, // 3308 |
| 10599 | { PseudoVFWMACC_VV_MF2_E32_MASK, VFWMACC_VV, 0x7, 0x0 }, // 3309 |
| 10600 | { PseudoVFWMSAC_VFPR16_M1_E16, VFWMSAC_VF, 0x0, 0x0 }, // 3310 |
| 10601 | { PseudoVFWMSAC_VFPR16_M1_E16_MASK, VFWMSAC_VF, 0x0, 0x0 }, // 3311 |
| 10602 | { PseudoVFWMSAC_VFPR32_M1_E32, VFWMSAC_VF, 0x0, 0x0 }, // 3312 |
| 10603 | { PseudoVFWMSAC_VFPR32_M1_E32_MASK, VFWMSAC_VF, 0x0, 0x0 }, // 3313 |
| 10604 | { PseudoVFWMSAC_VFPR16_M2_E16, VFWMSAC_VF, 0x1, 0x0 }, // 3314 |
| 10605 | { PseudoVFWMSAC_VFPR16_M2_E16_MASK, VFWMSAC_VF, 0x1, 0x0 }, // 3315 |
| 10606 | { PseudoVFWMSAC_VFPR32_M2_E32, VFWMSAC_VF, 0x1, 0x0 }, // 3316 |
| 10607 | { PseudoVFWMSAC_VFPR32_M2_E32_MASK, VFWMSAC_VF, 0x1, 0x0 }, // 3317 |
| 10608 | { PseudoVFWMSAC_VFPR16_M4_E16, VFWMSAC_VF, 0x2, 0x0 }, // 3318 |
| 10609 | { PseudoVFWMSAC_VFPR16_M4_E16_MASK, VFWMSAC_VF, 0x2, 0x0 }, // 3319 |
| 10610 | { PseudoVFWMSAC_VFPR32_M4_E32, VFWMSAC_VF, 0x2, 0x0 }, // 3320 |
| 10611 | { PseudoVFWMSAC_VFPR32_M4_E32_MASK, VFWMSAC_VF, 0x2, 0x0 }, // 3321 |
| 10612 | { PseudoVFWMSAC_VFPR16_MF4_E16, VFWMSAC_VF, 0x6, 0x0 }, // 3322 |
| 10613 | { PseudoVFWMSAC_VFPR16_MF4_E16_MASK, VFWMSAC_VF, 0x6, 0x0 }, // 3323 |
| 10614 | { PseudoVFWMSAC_VFPR16_MF2_E16, VFWMSAC_VF, 0x7, 0x0 }, // 3324 |
| 10615 | { PseudoVFWMSAC_VFPR16_MF2_E16_MASK, VFWMSAC_VF, 0x7, 0x0 }, // 3325 |
| 10616 | { PseudoVFWMSAC_VFPR32_MF2_E32, VFWMSAC_VF, 0x7, 0x0 }, // 3326 |
| 10617 | { PseudoVFWMSAC_VFPR32_MF2_E32_MASK, VFWMSAC_VF, 0x7, 0x0 }, // 3327 |
| 10618 | { PseudoVFWMSAC_VV_M1_E16, VFWMSAC_VV, 0x0, 0x0 }, // 3328 |
| 10619 | { PseudoVFWMSAC_VV_M1_E16_MASK, VFWMSAC_VV, 0x0, 0x0 }, // 3329 |
| 10620 | { PseudoVFWMSAC_VV_M1_E32, VFWMSAC_VV, 0x0, 0x0 }, // 3330 |
| 10621 | { PseudoVFWMSAC_VV_M1_E32_MASK, VFWMSAC_VV, 0x0, 0x0 }, // 3331 |
| 10622 | { PseudoVFWMSAC_VV_M2_E16, VFWMSAC_VV, 0x1, 0x0 }, // 3332 |
| 10623 | { PseudoVFWMSAC_VV_M2_E16_MASK, VFWMSAC_VV, 0x1, 0x0 }, // 3333 |
| 10624 | { PseudoVFWMSAC_VV_M2_E32, VFWMSAC_VV, 0x1, 0x0 }, // 3334 |
| 10625 | { PseudoVFWMSAC_VV_M2_E32_MASK, VFWMSAC_VV, 0x1, 0x0 }, // 3335 |
| 10626 | { PseudoVFWMSAC_VV_M4_E16, VFWMSAC_VV, 0x2, 0x0 }, // 3336 |
| 10627 | { PseudoVFWMSAC_VV_M4_E16_MASK, VFWMSAC_VV, 0x2, 0x0 }, // 3337 |
| 10628 | { PseudoVFWMSAC_VV_M4_E32, VFWMSAC_VV, 0x2, 0x0 }, // 3338 |
| 10629 | { PseudoVFWMSAC_VV_M4_E32_MASK, VFWMSAC_VV, 0x2, 0x0 }, // 3339 |
| 10630 | { PseudoVFWMSAC_VV_MF4_E16, VFWMSAC_VV, 0x6, 0x0 }, // 3340 |
| 10631 | { PseudoVFWMSAC_VV_MF4_E16_MASK, VFWMSAC_VV, 0x6, 0x0 }, // 3341 |
| 10632 | { PseudoVFWMSAC_VV_MF2_E16, VFWMSAC_VV, 0x7, 0x0 }, // 3342 |
| 10633 | { PseudoVFWMSAC_VV_MF2_E16_MASK, VFWMSAC_VV, 0x7, 0x0 }, // 3343 |
| 10634 | { PseudoVFWMSAC_VV_MF2_E32, VFWMSAC_VV, 0x7, 0x0 }, // 3344 |
| 10635 | { PseudoVFWMSAC_VV_MF2_E32_MASK, VFWMSAC_VV, 0x7, 0x0 }, // 3345 |
| 10636 | { PseudoVFWMUL_VFPR16_M1_E16, VFWMUL_VF, 0x0, 0x10 }, // 3346 |
| 10637 | { PseudoVFWMUL_VFPR16_M1_E16_MASK, VFWMUL_VF, 0x0, 0x10 }, // 3347 |
| 10638 | { PseudoVFWMUL_VFPR32_M1_E32, VFWMUL_VF, 0x0, 0x20 }, // 3348 |
| 10639 | { PseudoVFWMUL_VFPR32_M1_E32_MASK, VFWMUL_VF, 0x0, 0x20 }, // 3349 |
| 10640 | { PseudoVFWMUL_VFPR16_M2_E16, VFWMUL_VF, 0x1, 0x10 }, // 3350 |
| 10641 | { PseudoVFWMUL_VFPR16_M2_E16_MASK, VFWMUL_VF, 0x1, 0x10 }, // 3351 |
| 10642 | { PseudoVFWMUL_VFPR32_M2_E32, VFWMUL_VF, 0x1, 0x20 }, // 3352 |
| 10643 | { PseudoVFWMUL_VFPR32_M2_E32_MASK, VFWMUL_VF, 0x1, 0x20 }, // 3353 |
| 10644 | { PseudoVFWMUL_VFPR16_M4_E16, VFWMUL_VF, 0x2, 0x10 }, // 3354 |
| 10645 | { PseudoVFWMUL_VFPR16_M4_E16_MASK, VFWMUL_VF, 0x2, 0x10 }, // 3355 |
| 10646 | { PseudoVFWMUL_VFPR32_M4_E32, VFWMUL_VF, 0x2, 0x20 }, // 3356 |
| 10647 | { PseudoVFWMUL_VFPR32_M4_E32_MASK, VFWMUL_VF, 0x2, 0x20 }, // 3357 |
| 10648 | { PseudoVFWMUL_VFPR16_MF4_E16, VFWMUL_VF, 0x6, 0x10 }, // 3358 |
| 10649 | { PseudoVFWMUL_VFPR16_MF4_E16_MASK, VFWMUL_VF, 0x6, 0x10 }, // 3359 |
| 10650 | { PseudoVFWMUL_VFPR16_MF2_E16, VFWMUL_VF, 0x7, 0x10 }, // 3360 |
| 10651 | { PseudoVFWMUL_VFPR16_MF2_E16_MASK, VFWMUL_VF, 0x7, 0x10 }, // 3361 |
| 10652 | { PseudoVFWMUL_VFPR32_MF2_E32, VFWMUL_VF, 0x7, 0x20 }, // 3362 |
| 10653 | { PseudoVFWMUL_VFPR32_MF2_E32_MASK, VFWMUL_VF, 0x7, 0x20 }, // 3363 |
| 10654 | { PseudoVFWMUL_VV_M1_E16, VFWMUL_VV, 0x0, 0x10 }, // 3364 |
| 10655 | { PseudoVFWMUL_VV_M1_E16_MASK, VFWMUL_VV, 0x0, 0x10 }, // 3365 |
| 10656 | { PseudoVFWMUL_VV_M1_E32, VFWMUL_VV, 0x0, 0x20 }, // 3366 |
| 10657 | { PseudoVFWMUL_VV_M1_E32_MASK, VFWMUL_VV, 0x0, 0x20 }, // 3367 |
| 10658 | { PseudoVFWMUL_VV_M2_E16, VFWMUL_VV, 0x1, 0x10 }, // 3368 |
| 10659 | { PseudoVFWMUL_VV_M2_E16_MASK, VFWMUL_VV, 0x1, 0x10 }, // 3369 |
| 10660 | { PseudoVFWMUL_VV_M2_E32, VFWMUL_VV, 0x1, 0x20 }, // 3370 |
| 10661 | { PseudoVFWMUL_VV_M2_E32_MASK, VFWMUL_VV, 0x1, 0x20 }, // 3371 |
| 10662 | { PseudoVFWMUL_VV_M4_E16, VFWMUL_VV, 0x2, 0x10 }, // 3372 |
| 10663 | { PseudoVFWMUL_VV_M4_E16_MASK, VFWMUL_VV, 0x2, 0x10 }, // 3373 |
| 10664 | { PseudoVFWMUL_VV_M4_E32, VFWMUL_VV, 0x2, 0x20 }, // 3374 |
| 10665 | { PseudoVFWMUL_VV_M4_E32_MASK, VFWMUL_VV, 0x2, 0x20 }, // 3375 |
| 10666 | { PseudoVFWMUL_VV_MF4_E16, VFWMUL_VV, 0x6, 0x10 }, // 3376 |
| 10667 | { PseudoVFWMUL_VV_MF4_E16_MASK, VFWMUL_VV, 0x6, 0x10 }, // 3377 |
| 10668 | { PseudoVFWMUL_VV_MF2_E16, VFWMUL_VV, 0x7, 0x10 }, // 3378 |
| 10669 | { PseudoVFWMUL_VV_MF2_E16_MASK, VFWMUL_VV, 0x7, 0x10 }, // 3379 |
| 10670 | { PseudoVFWMUL_VV_MF2_E32, VFWMUL_VV, 0x7, 0x20 }, // 3380 |
| 10671 | { PseudoVFWMUL_VV_MF2_E32_MASK, VFWMUL_VV, 0x7, 0x20 }, // 3381 |
| 10672 | { PseudoVFWNMACC_VFPR16_M1_E16, VFWNMACC_VF, 0x0, 0x0 }, // 3382 |
| 10673 | { PseudoVFWNMACC_VFPR16_M1_E16_MASK, VFWNMACC_VF, 0x0, 0x0 }, // 3383 |
| 10674 | { PseudoVFWNMACC_VFPR32_M1_E32, VFWNMACC_VF, 0x0, 0x0 }, // 3384 |
| 10675 | { PseudoVFWNMACC_VFPR32_M1_E32_MASK, VFWNMACC_VF, 0x0, 0x0 }, // 3385 |
| 10676 | { PseudoVFWNMACC_VFPR16_M2_E16, VFWNMACC_VF, 0x1, 0x0 }, // 3386 |
| 10677 | { PseudoVFWNMACC_VFPR16_M2_E16_MASK, VFWNMACC_VF, 0x1, 0x0 }, // 3387 |
| 10678 | { PseudoVFWNMACC_VFPR32_M2_E32, VFWNMACC_VF, 0x1, 0x0 }, // 3388 |
| 10679 | { PseudoVFWNMACC_VFPR32_M2_E32_MASK, VFWNMACC_VF, 0x1, 0x0 }, // 3389 |
| 10680 | { PseudoVFWNMACC_VFPR16_M4_E16, VFWNMACC_VF, 0x2, 0x0 }, // 3390 |
| 10681 | { PseudoVFWNMACC_VFPR16_M4_E16_MASK, VFWNMACC_VF, 0x2, 0x0 }, // 3391 |
| 10682 | { PseudoVFWNMACC_VFPR32_M4_E32, VFWNMACC_VF, 0x2, 0x0 }, // 3392 |
| 10683 | { PseudoVFWNMACC_VFPR32_M4_E32_MASK, VFWNMACC_VF, 0x2, 0x0 }, // 3393 |
| 10684 | { PseudoVFWNMACC_VFPR16_MF4_E16, VFWNMACC_VF, 0x6, 0x0 }, // 3394 |
| 10685 | { PseudoVFWNMACC_VFPR16_MF4_E16_MASK, VFWNMACC_VF, 0x6, 0x0 }, // 3395 |
| 10686 | { PseudoVFWNMACC_VFPR16_MF2_E16, VFWNMACC_VF, 0x7, 0x0 }, // 3396 |
| 10687 | { PseudoVFWNMACC_VFPR16_MF2_E16_MASK, VFWNMACC_VF, 0x7, 0x0 }, // 3397 |
| 10688 | { PseudoVFWNMACC_VFPR32_MF2_E32, VFWNMACC_VF, 0x7, 0x0 }, // 3398 |
| 10689 | { PseudoVFWNMACC_VFPR32_MF2_E32_MASK, VFWNMACC_VF, 0x7, 0x0 }, // 3399 |
| 10690 | { PseudoVFWNMACC_VV_M1_E16, VFWNMACC_VV, 0x0, 0x0 }, // 3400 |
| 10691 | { PseudoVFWNMACC_VV_M1_E16_MASK, VFWNMACC_VV, 0x0, 0x0 }, // 3401 |
| 10692 | { PseudoVFWNMACC_VV_M1_E32, VFWNMACC_VV, 0x0, 0x0 }, // 3402 |
| 10693 | { PseudoVFWNMACC_VV_M1_E32_MASK, VFWNMACC_VV, 0x0, 0x0 }, // 3403 |
| 10694 | { PseudoVFWNMACC_VV_M2_E16, VFWNMACC_VV, 0x1, 0x0 }, // 3404 |
| 10695 | { PseudoVFWNMACC_VV_M2_E16_MASK, VFWNMACC_VV, 0x1, 0x0 }, // 3405 |
| 10696 | { PseudoVFWNMACC_VV_M2_E32, VFWNMACC_VV, 0x1, 0x0 }, // 3406 |
| 10697 | { PseudoVFWNMACC_VV_M2_E32_MASK, VFWNMACC_VV, 0x1, 0x0 }, // 3407 |
| 10698 | { PseudoVFWNMACC_VV_M4_E16, VFWNMACC_VV, 0x2, 0x0 }, // 3408 |
| 10699 | { PseudoVFWNMACC_VV_M4_E16_MASK, VFWNMACC_VV, 0x2, 0x0 }, // 3409 |
| 10700 | { PseudoVFWNMACC_VV_M4_E32, VFWNMACC_VV, 0x2, 0x0 }, // 3410 |
| 10701 | { PseudoVFWNMACC_VV_M4_E32_MASK, VFWNMACC_VV, 0x2, 0x0 }, // 3411 |
| 10702 | { PseudoVFWNMACC_VV_MF4_E16, VFWNMACC_VV, 0x6, 0x0 }, // 3412 |
| 10703 | { PseudoVFWNMACC_VV_MF4_E16_MASK, VFWNMACC_VV, 0x6, 0x0 }, // 3413 |
| 10704 | { PseudoVFWNMACC_VV_MF2_E16, VFWNMACC_VV, 0x7, 0x0 }, // 3414 |
| 10705 | { PseudoVFWNMACC_VV_MF2_E16_MASK, VFWNMACC_VV, 0x7, 0x0 }, // 3415 |
| 10706 | { PseudoVFWNMACC_VV_MF2_E32, VFWNMACC_VV, 0x7, 0x0 }, // 3416 |
| 10707 | { PseudoVFWNMACC_VV_MF2_E32_MASK, VFWNMACC_VV, 0x7, 0x0 }, // 3417 |
| 10708 | { PseudoVFWNMSAC_VFPR16_M1_E16, VFWNMSAC_VF, 0x0, 0x0 }, // 3418 |
| 10709 | { PseudoVFWNMSAC_VFPR16_M1_E16_MASK, VFWNMSAC_VF, 0x0, 0x0 }, // 3419 |
| 10710 | { PseudoVFWNMSAC_VFPR32_M1_E32, VFWNMSAC_VF, 0x0, 0x0 }, // 3420 |
| 10711 | { PseudoVFWNMSAC_VFPR32_M1_E32_MASK, VFWNMSAC_VF, 0x0, 0x0 }, // 3421 |
| 10712 | { PseudoVFWNMSAC_VFPR16_M2_E16, VFWNMSAC_VF, 0x1, 0x0 }, // 3422 |
| 10713 | { PseudoVFWNMSAC_VFPR16_M2_E16_MASK, VFWNMSAC_VF, 0x1, 0x0 }, // 3423 |
| 10714 | { PseudoVFWNMSAC_VFPR32_M2_E32, VFWNMSAC_VF, 0x1, 0x0 }, // 3424 |
| 10715 | { PseudoVFWNMSAC_VFPR32_M2_E32_MASK, VFWNMSAC_VF, 0x1, 0x0 }, // 3425 |
| 10716 | { PseudoVFWNMSAC_VFPR16_M4_E16, VFWNMSAC_VF, 0x2, 0x0 }, // 3426 |
| 10717 | { PseudoVFWNMSAC_VFPR16_M4_E16_MASK, VFWNMSAC_VF, 0x2, 0x0 }, // 3427 |
| 10718 | { PseudoVFWNMSAC_VFPR32_M4_E32, VFWNMSAC_VF, 0x2, 0x0 }, // 3428 |
| 10719 | { PseudoVFWNMSAC_VFPR32_M4_E32_MASK, VFWNMSAC_VF, 0x2, 0x0 }, // 3429 |
| 10720 | { PseudoVFWNMSAC_VFPR16_MF4_E16, VFWNMSAC_VF, 0x6, 0x0 }, // 3430 |
| 10721 | { PseudoVFWNMSAC_VFPR16_MF4_E16_MASK, VFWNMSAC_VF, 0x6, 0x0 }, // 3431 |
| 10722 | { PseudoVFWNMSAC_VFPR16_MF2_E16, VFWNMSAC_VF, 0x7, 0x0 }, // 3432 |
| 10723 | { PseudoVFWNMSAC_VFPR16_MF2_E16_MASK, VFWNMSAC_VF, 0x7, 0x0 }, // 3433 |
| 10724 | { PseudoVFWNMSAC_VFPR32_MF2_E32, VFWNMSAC_VF, 0x7, 0x0 }, // 3434 |
| 10725 | { PseudoVFWNMSAC_VFPR32_MF2_E32_MASK, VFWNMSAC_VF, 0x7, 0x0 }, // 3435 |
| 10726 | { PseudoVFWNMSAC_VV_M1_E16, VFWNMSAC_VV, 0x0, 0x0 }, // 3436 |
| 10727 | { PseudoVFWNMSAC_VV_M1_E16_MASK, VFWNMSAC_VV, 0x0, 0x0 }, // 3437 |
| 10728 | { PseudoVFWNMSAC_VV_M1_E32, VFWNMSAC_VV, 0x0, 0x0 }, // 3438 |
| 10729 | { PseudoVFWNMSAC_VV_M1_E32_MASK, VFWNMSAC_VV, 0x0, 0x0 }, // 3439 |
| 10730 | { PseudoVFWNMSAC_VV_M2_E16, VFWNMSAC_VV, 0x1, 0x0 }, // 3440 |
| 10731 | { PseudoVFWNMSAC_VV_M2_E16_MASK, VFWNMSAC_VV, 0x1, 0x0 }, // 3441 |
| 10732 | { PseudoVFWNMSAC_VV_M2_E32, VFWNMSAC_VV, 0x1, 0x0 }, // 3442 |
| 10733 | { PseudoVFWNMSAC_VV_M2_E32_MASK, VFWNMSAC_VV, 0x1, 0x0 }, // 3443 |
| 10734 | { PseudoVFWNMSAC_VV_M4_E16, VFWNMSAC_VV, 0x2, 0x0 }, // 3444 |
| 10735 | { PseudoVFWNMSAC_VV_M4_E16_MASK, VFWNMSAC_VV, 0x2, 0x0 }, // 3445 |
| 10736 | { PseudoVFWNMSAC_VV_M4_E32, VFWNMSAC_VV, 0x2, 0x0 }, // 3446 |
| 10737 | { PseudoVFWNMSAC_VV_M4_E32_MASK, VFWNMSAC_VV, 0x2, 0x0 }, // 3447 |
| 10738 | { PseudoVFWNMSAC_VV_MF4_E16, VFWNMSAC_VV, 0x6, 0x0 }, // 3448 |
| 10739 | { PseudoVFWNMSAC_VV_MF4_E16_MASK, VFWNMSAC_VV, 0x6, 0x0 }, // 3449 |
| 10740 | { PseudoVFWNMSAC_VV_MF2_E16, VFWNMSAC_VV, 0x7, 0x0 }, // 3450 |
| 10741 | { PseudoVFWNMSAC_VV_MF2_E16_MASK, VFWNMSAC_VV, 0x7, 0x0 }, // 3451 |
| 10742 | { PseudoVFWNMSAC_VV_MF2_E32, VFWNMSAC_VV, 0x7, 0x0 }, // 3452 |
| 10743 | { PseudoVFWNMSAC_VV_MF2_E32_MASK, VFWNMSAC_VV, 0x7, 0x0 }, // 3453 |
| 10744 | { PseudoVFWREDOSUM_VS_M1_E16, VFWREDOSUM_VS, 0x0, 0x10 }, // 3454 |
| 10745 | { PseudoVFWREDOSUM_VS_M1_E16_MASK, VFWREDOSUM_VS, 0x0, 0x10 }, // 3455 |
| 10746 | { PseudoVFWREDOSUM_VS_M1_E32, VFWREDOSUM_VS, 0x0, 0x20 }, // 3456 |
| 10747 | { PseudoVFWREDOSUM_VS_M1_E32_MASK, VFWREDOSUM_VS, 0x0, 0x20 }, // 3457 |
| 10748 | { PseudoVFWREDOSUM_VS_M2_E16, VFWREDOSUM_VS, 0x1, 0x10 }, // 3458 |
| 10749 | { PseudoVFWREDOSUM_VS_M2_E16_MASK, VFWREDOSUM_VS, 0x1, 0x10 }, // 3459 |
| 10750 | { PseudoVFWREDOSUM_VS_M2_E32, VFWREDOSUM_VS, 0x1, 0x20 }, // 3460 |
| 10751 | { PseudoVFWREDOSUM_VS_M2_E32_MASK, VFWREDOSUM_VS, 0x1, 0x20 }, // 3461 |
| 10752 | { PseudoVFWREDOSUM_VS_M4_E16, VFWREDOSUM_VS, 0x2, 0x10 }, // 3462 |
| 10753 | { PseudoVFWREDOSUM_VS_M4_E16_MASK, VFWREDOSUM_VS, 0x2, 0x10 }, // 3463 |
| 10754 | { PseudoVFWREDOSUM_VS_M4_E32, VFWREDOSUM_VS, 0x2, 0x20 }, // 3464 |
| 10755 | { PseudoVFWREDOSUM_VS_M4_E32_MASK, VFWREDOSUM_VS, 0x2, 0x20 }, // 3465 |
| 10756 | { PseudoVFWREDOSUM_VS_M8_E16, VFWREDOSUM_VS, 0x3, 0x10 }, // 3466 |
| 10757 | { PseudoVFWREDOSUM_VS_M8_E16_MASK, VFWREDOSUM_VS, 0x3, 0x10 }, // 3467 |
| 10758 | { PseudoVFWREDOSUM_VS_M8_E32, VFWREDOSUM_VS, 0x3, 0x20 }, // 3468 |
| 10759 | { PseudoVFWREDOSUM_VS_M8_E32_MASK, VFWREDOSUM_VS, 0x3, 0x20 }, // 3469 |
| 10760 | { PseudoVFWREDOSUM_VS_MF4_E16, VFWREDOSUM_VS, 0x6, 0x10 }, // 3470 |
| 10761 | { PseudoVFWREDOSUM_VS_MF4_E16_MASK, VFWREDOSUM_VS, 0x6, 0x10 }, // 3471 |
| 10762 | { PseudoVFWREDOSUM_VS_MF2_E16, VFWREDOSUM_VS, 0x7, 0x10 }, // 3472 |
| 10763 | { PseudoVFWREDOSUM_VS_MF2_E16_MASK, VFWREDOSUM_VS, 0x7, 0x10 }, // 3473 |
| 10764 | { PseudoVFWREDOSUM_VS_MF2_E32, VFWREDOSUM_VS, 0x7, 0x20 }, // 3474 |
| 10765 | { PseudoVFWREDOSUM_VS_MF2_E32_MASK, VFWREDOSUM_VS, 0x7, 0x20 }, // 3475 |
| 10766 | { PseudoVFWREDUSUM_VS_M1_E16, VFWREDUSUM_VS, 0x0, 0x10 }, // 3476 |
| 10767 | { PseudoVFWREDUSUM_VS_M1_E16_MASK, VFWREDUSUM_VS, 0x0, 0x10 }, // 3477 |
| 10768 | { PseudoVFWREDUSUM_VS_M1_E32, VFWREDUSUM_VS, 0x0, 0x20 }, // 3478 |
| 10769 | { PseudoVFWREDUSUM_VS_M1_E32_MASK, VFWREDUSUM_VS, 0x0, 0x20 }, // 3479 |
| 10770 | { PseudoVFWREDUSUM_VS_M2_E16, VFWREDUSUM_VS, 0x1, 0x10 }, // 3480 |
| 10771 | { PseudoVFWREDUSUM_VS_M2_E16_MASK, VFWREDUSUM_VS, 0x1, 0x10 }, // 3481 |
| 10772 | { PseudoVFWREDUSUM_VS_M2_E32, VFWREDUSUM_VS, 0x1, 0x20 }, // 3482 |
| 10773 | { PseudoVFWREDUSUM_VS_M2_E32_MASK, VFWREDUSUM_VS, 0x1, 0x20 }, // 3483 |
| 10774 | { PseudoVFWREDUSUM_VS_M4_E16, VFWREDUSUM_VS, 0x2, 0x10 }, // 3484 |
| 10775 | { PseudoVFWREDUSUM_VS_M4_E16_MASK, VFWREDUSUM_VS, 0x2, 0x10 }, // 3485 |
| 10776 | { PseudoVFWREDUSUM_VS_M4_E32, VFWREDUSUM_VS, 0x2, 0x20 }, // 3486 |
| 10777 | { PseudoVFWREDUSUM_VS_M4_E32_MASK, VFWREDUSUM_VS, 0x2, 0x20 }, // 3487 |
| 10778 | { PseudoVFWREDUSUM_VS_M8_E16, VFWREDUSUM_VS, 0x3, 0x10 }, // 3488 |
| 10779 | { PseudoVFWREDUSUM_VS_M8_E16_MASK, VFWREDUSUM_VS, 0x3, 0x10 }, // 3489 |
| 10780 | { PseudoVFWREDUSUM_VS_M8_E32, VFWREDUSUM_VS, 0x3, 0x20 }, // 3490 |
| 10781 | { PseudoVFWREDUSUM_VS_M8_E32_MASK, VFWREDUSUM_VS, 0x3, 0x20 }, // 3491 |
| 10782 | { PseudoVFWREDUSUM_VS_MF4_E16, VFWREDUSUM_VS, 0x6, 0x10 }, // 3492 |
| 10783 | { PseudoVFWREDUSUM_VS_MF4_E16_MASK, VFWREDUSUM_VS, 0x6, 0x10 }, // 3493 |
| 10784 | { PseudoVFWREDUSUM_VS_MF2_E16, VFWREDUSUM_VS, 0x7, 0x10 }, // 3494 |
| 10785 | { PseudoVFWREDUSUM_VS_MF2_E16_MASK, VFWREDUSUM_VS, 0x7, 0x10 }, // 3495 |
| 10786 | { PseudoVFWREDUSUM_VS_MF2_E32, VFWREDUSUM_VS, 0x7, 0x20 }, // 3496 |
| 10787 | { PseudoVFWREDUSUM_VS_MF2_E32_MASK, VFWREDUSUM_VS, 0x7, 0x20 }, // 3497 |
| 10788 | { PseudoVFWSUB_VFPR16_M1_E16, VFWSUB_VF, 0x0, 0x10 }, // 3498 |
| 10789 | { PseudoVFWSUB_VFPR16_M1_E16_MASK, VFWSUB_VF, 0x0, 0x10 }, // 3499 |
| 10790 | { PseudoVFWSUB_VFPR32_M1_E32, VFWSUB_VF, 0x0, 0x20 }, // 3500 |
| 10791 | { PseudoVFWSUB_VFPR32_M1_E32_MASK, VFWSUB_VF, 0x0, 0x20 }, // 3501 |
| 10792 | { PseudoVFWSUB_VFPR16_M2_E16, VFWSUB_VF, 0x1, 0x10 }, // 3502 |
| 10793 | { PseudoVFWSUB_VFPR16_M2_E16_MASK, VFWSUB_VF, 0x1, 0x10 }, // 3503 |
| 10794 | { PseudoVFWSUB_VFPR32_M2_E32, VFWSUB_VF, 0x1, 0x20 }, // 3504 |
| 10795 | { PseudoVFWSUB_VFPR32_M2_E32_MASK, VFWSUB_VF, 0x1, 0x20 }, // 3505 |
| 10796 | { PseudoVFWSUB_VFPR16_M4_E16, VFWSUB_VF, 0x2, 0x10 }, // 3506 |
| 10797 | { PseudoVFWSUB_VFPR16_M4_E16_MASK, VFWSUB_VF, 0x2, 0x10 }, // 3507 |
| 10798 | { PseudoVFWSUB_VFPR32_M4_E32, VFWSUB_VF, 0x2, 0x20 }, // 3508 |
| 10799 | { PseudoVFWSUB_VFPR32_M4_E32_MASK, VFWSUB_VF, 0x2, 0x20 }, // 3509 |
| 10800 | { PseudoVFWSUB_VFPR16_MF4_E16, VFWSUB_VF, 0x6, 0x10 }, // 3510 |
| 10801 | { PseudoVFWSUB_VFPR16_MF4_E16_MASK, VFWSUB_VF, 0x6, 0x10 }, // 3511 |
| 10802 | { PseudoVFWSUB_VFPR16_MF2_E16, VFWSUB_VF, 0x7, 0x10 }, // 3512 |
| 10803 | { PseudoVFWSUB_VFPR16_MF2_E16_MASK, VFWSUB_VF, 0x7, 0x10 }, // 3513 |
| 10804 | { PseudoVFWSUB_VFPR32_MF2_E32, VFWSUB_VF, 0x7, 0x20 }, // 3514 |
| 10805 | { PseudoVFWSUB_VFPR32_MF2_E32_MASK, VFWSUB_VF, 0x7, 0x20 }, // 3515 |
| 10806 | { PseudoVFWSUB_VV_M1_E16, VFWSUB_VV, 0x0, 0x10 }, // 3516 |
| 10807 | { PseudoVFWSUB_VV_M1_E16_MASK, VFWSUB_VV, 0x0, 0x10 }, // 3517 |
| 10808 | { PseudoVFWSUB_VV_M1_E32, VFWSUB_VV, 0x0, 0x20 }, // 3518 |
| 10809 | { PseudoVFWSUB_VV_M1_E32_MASK, VFWSUB_VV, 0x0, 0x20 }, // 3519 |
| 10810 | { PseudoVFWSUB_VV_M2_E16, VFWSUB_VV, 0x1, 0x10 }, // 3520 |
| 10811 | { PseudoVFWSUB_VV_M2_E16_MASK, VFWSUB_VV, 0x1, 0x10 }, // 3521 |
| 10812 | { PseudoVFWSUB_VV_M2_E32, VFWSUB_VV, 0x1, 0x20 }, // 3522 |
| 10813 | { PseudoVFWSUB_VV_M2_E32_MASK, VFWSUB_VV, 0x1, 0x20 }, // 3523 |
| 10814 | { PseudoVFWSUB_VV_M4_E16, VFWSUB_VV, 0x2, 0x10 }, // 3524 |
| 10815 | { PseudoVFWSUB_VV_M4_E16_MASK, VFWSUB_VV, 0x2, 0x10 }, // 3525 |
| 10816 | { PseudoVFWSUB_VV_M4_E32, VFWSUB_VV, 0x2, 0x20 }, // 3526 |
| 10817 | { PseudoVFWSUB_VV_M4_E32_MASK, VFWSUB_VV, 0x2, 0x20 }, // 3527 |
| 10818 | { PseudoVFWSUB_VV_MF4_E16, VFWSUB_VV, 0x6, 0x10 }, // 3528 |
| 10819 | { PseudoVFWSUB_VV_MF4_E16_MASK, VFWSUB_VV, 0x6, 0x10 }, // 3529 |
| 10820 | { PseudoVFWSUB_VV_MF2_E16, VFWSUB_VV, 0x7, 0x10 }, // 3530 |
| 10821 | { PseudoVFWSUB_VV_MF2_E16_MASK, VFWSUB_VV, 0x7, 0x10 }, // 3531 |
| 10822 | { PseudoVFWSUB_VV_MF2_E32, VFWSUB_VV, 0x7, 0x20 }, // 3532 |
| 10823 | { PseudoVFWSUB_VV_MF2_E32_MASK, VFWSUB_VV, 0x7, 0x20 }, // 3533 |
| 10824 | { PseudoVFWSUB_WFPR16_M1_E16, VFWSUB_WF, 0x0, 0x10 }, // 3534 |
| 10825 | { PseudoVFWSUB_WFPR16_M1_E16_MASK, VFWSUB_WF, 0x0, 0x10 }, // 3535 |
| 10826 | { PseudoVFWSUB_WFPR32_M1_E32, VFWSUB_WF, 0x0, 0x20 }, // 3536 |
| 10827 | { PseudoVFWSUB_WFPR32_M1_E32_MASK, VFWSUB_WF, 0x0, 0x20 }, // 3537 |
| 10828 | { PseudoVFWSUB_WFPR16_M2_E16, VFWSUB_WF, 0x1, 0x10 }, // 3538 |
| 10829 | { PseudoVFWSUB_WFPR16_M2_E16_MASK, VFWSUB_WF, 0x1, 0x10 }, // 3539 |
| 10830 | { PseudoVFWSUB_WFPR32_M2_E32, VFWSUB_WF, 0x1, 0x20 }, // 3540 |
| 10831 | { PseudoVFWSUB_WFPR32_M2_E32_MASK, VFWSUB_WF, 0x1, 0x20 }, // 3541 |
| 10832 | { PseudoVFWSUB_WFPR16_M4_E16, VFWSUB_WF, 0x2, 0x10 }, // 3542 |
| 10833 | { PseudoVFWSUB_WFPR16_M4_E16_MASK, VFWSUB_WF, 0x2, 0x10 }, // 3543 |
| 10834 | { PseudoVFWSUB_WFPR32_M4_E32, VFWSUB_WF, 0x2, 0x20 }, // 3544 |
| 10835 | { PseudoVFWSUB_WFPR32_M4_E32_MASK, VFWSUB_WF, 0x2, 0x20 }, // 3545 |
| 10836 | { PseudoVFWSUB_WFPR16_MF4_E16, VFWSUB_WF, 0x6, 0x10 }, // 3546 |
| 10837 | { PseudoVFWSUB_WFPR16_MF4_E16_MASK, VFWSUB_WF, 0x6, 0x10 }, // 3547 |
| 10838 | { PseudoVFWSUB_WFPR16_MF2_E16, VFWSUB_WF, 0x7, 0x10 }, // 3548 |
| 10839 | { PseudoVFWSUB_WFPR16_MF2_E16_MASK, VFWSUB_WF, 0x7, 0x10 }, // 3549 |
| 10840 | { PseudoVFWSUB_WFPR32_MF2_E32, VFWSUB_WF, 0x7, 0x20 }, // 3550 |
| 10841 | { PseudoVFWSUB_WFPR32_MF2_E32_MASK, VFWSUB_WF, 0x7, 0x20 }, // 3551 |
| 10842 | { PseudoVFWSUB_WV_M1_E16_MASK_TIED, VFWSUB_WV, 0x0, 0x0 }, // 3552 |
| 10843 | { PseudoVFWSUB_WV_M1_E16_TIED, VFWSUB_WV, 0x0, 0x0 }, // 3553 |
| 10844 | { PseudoVFWSUB_WV_M1_E32_MASK_TIED, VFWSUB_WV, 0x0, 0x0 }, // 3554 |
| 10845 | { PseudoVFWSUB_WV_M1_E32_TIED, VFWSUB_WV, 0x0, 0x0 }, // 3555 |
| 10846 | { PseudoVFWSUB_WV_M1_E16, VFWSUB_WV, 0x0, 0x10 }, // 3556 |
| 10847 | { PseudoVFWSUB_WV_M1_E16_MASK, VFWSUB_WV, 0x0, 0x10 }, // 3557 |
| 10848 | { PseudoVFWSUB_WV_M1_E32, VFWSUB_WV, 0x0, 0x20 }, // 3558 |
| 10849 | { PseudoVFWSUB_WV_M1_E32_MASK, VFWSUB_WV, 0x0, 0x20 }, // 3559 |
| 10850 | { PseudoVFWSUB_WV_M2_E16_MASK_TIED, VFWSUB_WV, 0x1, 0x0 }, // 3560 |
| 10851 | { PseudoVFWSUB_WV_M2_E16_TIED, VFWSUB_WV, 0x1, 0x0 }, // 3561 |
| 10852 | { PseudoVFWSUB_WV_M2_E32_MASK_TIED, VFWSUB_WV, 0x1, 0x0 }, // 3562 |
| 10853 | { PseudoVFWSUB_WV_M2_E32_TIED, VFWSUB_WV, 0x1, 0x0 }, // 3563 |
| 10854 | { PseudoVFWSUB_WV_M2_E16, VFWSUB_WV, 0x1, 0x10 }, // 3564 |
| 10855 | { PseudoVFWSUB_WV_M2_E16_MASK, VFWSUB_WV, 0x1, 0x10 }, // 3565 |
| 10856 | { PseudoVFWSUB_WV_M2_E32, VFWSUB_WV, 0x1, 0x20 }, // 3566 |
| 10857 | { PseudoVFWSUB_WV_M2_E32_MASK, VFWSUB_WV, 0x1, 0x20 }, // 3567 |
| 10858 | { PseudoVFWSUB_WV_M4_E16_MASK_TIED, VFWSUB_WV, 0x2, 0x0 }, // 3568 |
| 10859 | { PseudoVFWSUB_WV_M4_E16_TIED, VFWSUB_WV, 0x2, 0x0 }, // 3569 |
| 10860 | { PseudoVFWSUB_WV_M4_E32_MASK_TIED, VFWSUB_WV, 0x2, 0x0 }, // 3570 |
| 10861 | { PseudoVFWSUB_WV_M4_E32_TIED, VFWSUB_WV, 0x2, 0x0 }, // 3571 |
| 10862 | { PseudoVFWSUB_WV_M4_E16, VFWSUB_WV, 0x2, 0x10 }, // 3572 |
| 10863 | { PseudoVFWSUB_WV_M4_E16_MASK, VFWSUB_WV, 0x2, 0x10 }, // 3573 |
| 10864 | { PseudoVFWSUB_WV_M4_E32, VFWSUB_WV, 0x2, 0x20 }, // 3574 |
| 10865 | { PseudoVFWSUB_WV_M4_E32_MASK, VFWSUB_WV, 0x2, 0x20 }, // 3575 |
| 10866 | { PseudoVFWSUB_WV_MF4_E16_MASK_TIED, VFWSUB_WV, 0x6, 0x0 }, // 3576 |
| 10867 | { PseudoVFWSUB_WV_MF4_E16_TIED, VFWSUB_WV, 0x6, 0x0 }, // 3577 |
| 10868 | { PseudoVFWSUB_WV_MF4_E16, VFWSUB_WV, 0x6, 0x10 }, // 3578 |
| 10869 | { PseudoVFWSUB_WV_MF4_E16_MASK, VFWSUB_WV, 0x6, 0x10 }, // 3579 |
| 10870 | { PseudoVFWSUB_WV_MF2_E16_MASK_TIED, VFWSUB_WV, 0x7, 0x0 }, // 3580 |
| 10871 | { PseudoVFWSUB_WV_MF2_E16_TIED, VFWSUB_WV, 0x7, 0x0 }, // 3581 |
| 10872 | { PseudoVFWSUB_WV_MF2_E32_MASK_TIED, VFWSUB_WV, 0x7, 0x0 }, // 3582 |
| 10873 | { PseudoVFWSUB_WV_MF2_E32_TIED, VFWSUB_WV, 0x7, 0x0 }, // 3583 |
| 10874 | { PseudoVFWSUB_WV_MF2_E16, VFWSUB_WV, 0x7, 0x10 }, // 3584 |
| 10875 | { PseudoVFWSUB_WV_MF2_E16_MASK, VFWSUB_WV, 0x7, 0x10 }, // 3585 |
| 10876 | { PseudoVFWSUB_WV_MF2_E32, VFWSUB_WV, 0x7, 0x20 }, // 3586 |
| 10877 | { PseudoVFWSUB_WV_MF2_E32_MASK, VFWSUB_WV, 0x7, 0x20 }, // 3587 |
| 10878 | { PseudoVGHSH_VV_M1, VGHSH_VV, 0x0, 0x0 }, // 3588 |
| 10879 | { PseudoVGHSH_VV_M2, VGHSH_VV, 0x1, 0x0 }, // 3589 |
| 10880 | { PseudoVGHSH_VV_M4, VGHSH_VV, 0x2, 0x0 }, // 3590 |
| 10881 | { PseudoVGHSH_VV_M8, VGHSH_VV, 0x3, 0x0 }, // 3591 |
| 10882 | { PseudoVGHSH_VV_MF2, VGHSH_VV, 0x7, 0x0 }, // 3592 |
| 10883 | { PseudoVGMUL_VV_M1, VGMUL_VV, 0x0, 0x0 }, // 3593 |
| 10884 | { PseudoVGMUL_VV_M2, VGMUL_VV, 0x1, 0x0 }, // 3594 |
| 10885 | { PseudoVGMUL_VV_M4, VGMUL_VV, 0x2, 0x0 }, // 3595 |
| 10886 | { PseudoVGMUL_VV_M8, VGMUL_VV, 0x3, 0x0 }, // 3596 |
| 10887 | { PseudoVGMUL_VV_MF2, VGMUL_VV, 0x7, 0x0 }, // 3597 |
| 10888 | { PseudoVID_V_M1, VID_V, 0x0, 0x0 }, // 3598 |
| 10889 | { PseudoVID_V_M1_MASK, VID_V, 0x0, 0x0 }, // 3599 |
| 10890 | { PseudoVID_V_M2, VID_V, 0x1, 0x0 }, // 3600 |
| 10891 | { PseudoVID_V_M2_MASK, VID_V, 0x1, 0x0 }, // 3601 |
| 10892 | { PseudoVID_V_M4, VID_V, 0x2, 0x0 }, // 3602 |
| 10893 | { PseudoVID_V_M4_MASK, VID_V, 0x2, 0x0 }, // 3603 |
| 10894 | { PseudoVID_V_M8, VID_V, 0x3, 0x0 }, // 3604 |
| 10895 | { PseudoVID_V_M8_MASK, VID_V, 0x3, 0x0 }, // 3605 |
| 10896 | { PseudoVID_V_MF8, VID_V, 0x5, 0x0 }, // 3606 |
| 10897 | { PseudoVID_V_MF8_MASK, VID_V, 0x5, 0x0 }, // 3607 |
| 10898 | { PseudoVID_V_MF4, VID_V, 0x6, 0x0 }, // 3608 |
| 10899 | { PseudoVID_V_MF4_MASK, VID_V, 0x6, 0x0 }, // 3609 |
| 10900 | { PseudoVID_V_MF2, VID_V, 0x7, 0x0 }, // 3610 |
| 10901 | { PseudoVID_V_MF2_MASK, VID_V, 0x7, 0x0 }, // 3611 |
| 10902 | { PseudoVIOTA_M_M1, VIOTA_M, 0x0, 0x0 }, // 3612 |
| 10903 | { PseudoVIOTA_M_M1_MASK, VIOTA_M, 0x0, 0x0 }, // 3613 |
| 10904 | { PseudoVIOTA_M_M2, VIOTA_M, 0x1, 0x0 }, // 3614 |
| 10905 | { PseudoVIOTA_M_M2_MASK, VIOTA_M, 0x1, 0x0 }, // 3615 |
| 10906 | { PseudoVIOTA_M_M4, VIOTA_M, 0x2, 0x0 }, // 3616 |
| 10907 | { PseudoVIOTA_M_M4_MASK, VIOTA_M, 0x2, 0x0 }, // 3617 |
| 10908 | { PseudoVIOTA_M_M8, VIOTA_M, 0x3, 0x0 }, // 3618 |
| 10909 | { PseudoVIOTA_M_M8_MASK, VIOTA_M, 0x3, 0x0 }, // 3619 |
| 10910 | { PseudoVIOTA_M_MF8, VIOTA_M, 0x5, 0x0 }, // 3620 |
| 10911 | { PseudoVIOTA_M_MF8_MASK, VIOTA_M, 0x5, 0x0 }, // 3621 |
| 10912 | { PseudoVIOTA_M_MF4, VIOTA_M, 0x6, 0x0 }, // 3622 |
| 10913 | { PseudoVIOTA_M_MF4_MASK, VIOTA_M, 0x6, 0x0 }, // 3623 |
| 10914 | { PseudoVIOTA_M_MF2, VIOTA_M, 0x7, 0x0 }, // 3624 |
| 10915 | { PseudoVIOTA_M_MF2_MASK, VIOTA_M, 0x7, 0x0 }, // 3625 |
| 10916 | { PseudoVLE16FF_V_M1, VLE16FF_V, 0x0, 0x10 }, // 3626 |
| 10917 | { PseudoVLE16FF_V_M1_MASK, VLE16FF_V, 0x0, 0x10 }, // 3627 |
| 10918 | { PseudoVLE16FF_V_M2, VLE16FF_V, 0x1, 0x10 }, // 3628 |
| 10919 | { PseudoVLE16FF_V_M2_MASK, VLE16FF_V, 0x1, 0x10 }, // 3629 |
| 10920 | { PseudoVLE16FF_V_M4, VLE16FF_V, 0x2, 0x10 }, // 3630 |
| 10921 | { PseudoVLE16FF_V_M4_MASK, VLE16FF_V, 0x2, 0x10 }, // 3631 |
| 10922 | { PseudoVLE16FF_V_M8, VLE16FF_V, 0x3, 0x10 }, // 3632 |
| 10923 | { PseudoVLE16FF_V_M8_MASK, VLE16FF_V, 0x3, 0x10 }, // 3633 |
| 10924 | { PseudoVLE16FF_V_MF4, VLE16FF_V, 0x6, 0x10 }, // 3634 |
| 10925 | { PseudoVLE16FF_V_MF4_MASK, VLE16FF_V, 0x6, 0x10 }, // 3635 |
| 10926 | { PseudoVLE16FF_V_MF2, VLE16FF_V, 0x7, 0x10 }, // 3636 |
| 10927 | { PseudoVLE16FF_V_MF2_MASK, VLE16FF_V, 0x7, 0x10 }, // 3637 |
| 10928 | { PseudoVLE16_V_M1, VLE16_V, 0x0, 0x10 }, // 3638 |
| 10929 | { PseudoVLE16_V_M1_MASK, VLE16_V, 0x0, 0x10 }, // 3639 |
| 10930 | { PseudoVLE16_V_M2, VLE16_V, 0x1, 0x10 }, // 3640 |
| 10931 | { PseudoVLE16_V_M2_MASK, VLE16_V, 0x1, 0x10 }, // 3641 |
| 10932 | { PseudoVLE16_V_M4, VLE16_V, 0x2, 0x10 }, // 3642 |
| 10933 | { PseudoVLE16_V_M4_MASK, VLE16_V, 0x2, 0x10 }, // 3643 |
| 10934 | { PseudoVLE16_V_M8, VLE16_V, 0x3, 0x10 }, // 3644 |
| 10935 | { PseudoVLE16_V_M8_MASK, VLE16_V, 0x3, 0x10 }, // 3645 |
| 10936 | { PseudoVLE16_V_MF4, VLE16_V, 0x6, 0x10 }, // 3646 |
| 10937 | { PseudoVLE16_V_MF4_MASK, VLE16_V, 0x6, 0x10 }, // 3647 |
| 10938 | { PseudoVLE16_V_MF2, VLE16_V, 0x7, 0x10 }, // 3648 |
| 10939 | { PseudoVLE16_V_MF2_MASK, VLE16_V, 0x7, 0x10 }, // 3649 |
| 10940 | { PseudoVLE32FF_V_M1, VLE32FF_V, 0x0, 0x20 }, // 3650 |
| 10941 | { PseudoVLE32FF_V_M1_MASK, VLE32FF_V, 0x0, 0x20 }, // 3651 |
| 10942 | { PseudoVLE32FF_V_M2, VLE32FF_V, 0x1, 0x20 }, // 3652 |
| 10943 | { PseudoVLE32FF_V_M2_MASK, VLE32FF_V, 0x1, 0x20 }, // 3653 |
| 10944 | { PseudoVLE32FF_V_M4, VLE32FF_V, 0x2, 0x20 }, // 3654 |
| 10945 | { PseudoVLE32FF_V_M4_MASK, VLE32FF_V, 0x2, 0x20 }, // 3655 |
| 10946 | { PseudoVLE32FF_V_M8, VLE32FF_V, 0x3, 0x20 }, // 3656 |
| 10947 | { PseudoVLE32FF_V_M8_MASK, VLE32FF_V, 0x3, 0x20 }, // 3657 |
| 10948 | { PseudoVLE32FF_V_MF2, VLE32FF_V, 0x7, 0x20 }, // 3658 |
| 10949 | { PseudoVLE32FF_V_MF2_MASK, VLE32FF_V, 0x7, 0x20 }, // 3659 |
| 10950 | { PseudoVLE32_V_M1, VLE32_V, 0x0, 0x20 }, // 3660 |
| 10951 | { PseudoVLE32_V_M1_MASK, VLE32_V, 0x0, 0x20 }, // 3661 |
| 10952 | { PseudoVLE32_V_M2, VLE32_V, 0x1, 0x20 }, // 3662 |
| 10953 | { PseudoVLE32_V_M2_MASK, VLE32_V, 0x1, 0x20 }, // 3663 |
| 10954 | { PseudoVLE32_V_M4, VLE32_V, 0x2, 0x20 }, // 3664 |
| 10955 | { PseudoVLE32_V_M4_MASK, VLE32_V, 0x2, 0x20 }, // 3665 |
| 10956 | { PseudoVLE32_V_M8, VLE32_V, 0x3, 0x20 }, // 3666 |
| 10957 | { PseudoVLE32_V_M8_MASK, VLE32_V, 0x3, 0x20 }, // 3667 |
| 10958 | { PseudoVLE32_V_MF2, VLE32_V, 0x7, 0x20 }, // 3668 |
| 10959 | { PseudoVLE32_V_MF2_MASK, VLE32_V, 0x7, 0x20 }, // 3669 |
| 10960 | { PseudoVLE64FF_V_M1, VLE64FF_V, 0x0, 0x40 }, // 3670 |
| 10961 | { PseudoVLE64FF_V_M1_MASK, VLE64FF_V, 0x0, 0x40 }, // 3671 |
| 10962 | { PseudoVLE64FF_V_M2, VLE64FF_V, 0x1, 0x40 }, // 3672 |
| 10963 | { PseudoVLE64FF_V_M2_MASK, VLE64FF_V, 0x1, 0x40 }, // 3673 |
| 10964 | { PseudoVLE64FF_V_M4, VLE64FF_V, 0x2, 0x40 }, // 3674 |
| 10965 | { PseudoVLE64FF_V_M4_MASK, VLE64FF_V, 0x2, 0x40 }, // 3675 |
| 10966 | { PseudoVLE64FF_V_M8, VLE64FF_V, 0x3, 0x40 }, // 3676 |
| 10967 | { PseudoVLE64FF_V_M8_MASK, VLE64FF_V, 0x3, 0x40 }, // 3677 |
| 10968 | { PseudoVLE64_V_M1, VLE64_V, 0x0, 0x40 }, // 3678 |
| 10969 | { PseudoVLE64_V_M1_MASK, VLE64_V, 0x0, 0x40 }, // 3679 |
| 10970 | { PseudoVLE64_V_M2, VLE64_V, 0x1, 0x40 }, // 3680 |
| 10971 | { PseudoVLE64_V_M2_MASK, VLE64_V, 0x1, 0x40 }, // 3681 |
| 10972 | { PseudoVLE64_V_M4, VLE64_V, 0x2, 0x40 }, // 3682 |
| 10973 | { PseudoVLE64_V_M4_MASK, VLE64_V, 0x2, 0x40 }, // 3683 |
| 10974 | { PseudoVLE64_V_M8, VLE64_V, 0x3, 0x40 }, // 3684 |
| 10975 | { PseudoVLE64_V_M8_MASK, VLE64_V, 0x3, 0x40 }, // 3685 |
| 10976 | { PseudoVLE8FF_V_M1, VLE8FF_V, 0x0, 0x8 }, // 3686 |
| 10977 | { PseudoVLE8FF_V_M1_MASK, VLE8FF_V, 0x0, 0x8 }, // 3687 |
| 10978 | { PseudoVLE8FF_V_M2, VLE8FF_V, 0x1, 0x8 }, // 3688 |
| 10979 | { PseudoVLE8FF_V_M2_MASK, VLE8FF_V, 0x1, 0x8 }, // 3689 |
| 10980 | { PseudoVLE8FF_V_M4, VLE8FF_V, 0x2, 0x8 }, // 3690 |
| 10981 | { PseudoVLE8FF_V_M4_MASK, VLE8FF_V, 0x2, 0x8 }, // 3691 |
| 10982 | { PseudoVLE8FF_V_M8, VLE8FF_V, 0x3, 0x8 }, // 3692 |
| 10983 | { PseudoVLE8FF_V_M8_MASK, VLE8FF_V, 0x3, 0x8 }, // 3693 |
| 10984 | { PseudoVLE8FF_V_MF8, VLE8FF_V, 0x5, 0x8 }, // 3694 |
| 10985 | { PseudoVLE8FF_V_MF8_MASK, VLE8FF_V, 0x5, 0x8 }, // 3695 |
| 10986 | { PseudoVLE8FF_V_MF4, VLE8FF_V, 0x6, 0x8 }, // 3696 |
| 10987 | { PseudoVLE8FF_V_MF4_MASK, VLE8FF_V, 0x6, 0x8 }, // 3697 |
| 10988 | { PseudoVLE8FF_V_MF2, VLE8FF_V, 0x7, 0x8 }, // 3698 |
| 10989 | { PseudoVLE8FF_V_MF2_MASK, VLE8FF_V, 0x7, 0x8 }, // 3699 |
| 10990 | { PseudoVLE8_V_M1, VLE8_V, 0x0, 0x8 }, // 3700 |
| 10991 | { PseudoVLE8_V_M1_MASK, VLE8_V, 0x0, 0x8 }, // 3701 |
| 10992 | { PseudoVLE8_V_M2, VLE8_V, 0x1, 0x8 }, // 3702 |
| 10993 | { PseudoVLE8_V_M2_MASK, VLE8_V, 0x1, 0x8 }, // 3703 |
| 10994 | { PseudoVLE8_V_M4, VLE8_V, 0x2, 0x8 }, // 3704 |
| 10995 | { PseudoVLE8_V_M4_MASK, VLE8_V, 0x2, 0x8 }, // 3705 |
| 10996 | { PseudoVLE8_V_M8, VLE8_V, 0x3, 0x8 }, // 3706 |
| 10997 | { PseudoVLE8_V_M8_MASK, VLE8_V, 0x3, 0x8 }, // 3707 |
| 10998 | { PseudoVLE8_V_MF8, VLE8_V, 0x5, 0x8 }, // 3708 |
| 10999 | { PseudoVLE8_V_MF8_MASK, VLE8_V, 0x5, 0x8 }, // 3709 |
| 11000 | { PseudoVLE8_V_MF4, VLE8_V, 0x6, 0x8 }, // 3710 |
| 11001 | { PseudoVLE8_V_MF4_MASK, VLE8_V, 0x6, 0x8 }, // 3711 |
| 11002 | { PseudoVLE8_V_MF2, VLE8_V, 0x7, 0x8 }, // 3712 |
| 11003 | { PseudoVLE8_V_MF2_MASK, VLE8_V, 0x7, 0x8 }, // 3713 |
| 11004 | { PseudoVLM_V_B8, VLM_V, 0x0, 0x0 }, // 3714 |
| 11005 | { PseudoVLM_V_B16, VLM_V, 0x1, 0x0 }, // 3715 |
| 11006 | { PseudoVLM_V_B32, VLM_V, 0x2, 0x0 }, // 3716 |
| 11007 | { PseudoVLM_V_B64, VLM_V, 0x3, 0x0 }, // 3717 |
| 11008 | { PseudoVLM_V_B1, VLM_V, 0x5, 0x0 }, // 3718 |
| 11009 | { PseudoVLM_V_B2, VLM_V, 0x6, 0x0 }, // 3719 |
| 11010 | { PseudoVLM_V_B4, VLM_V, 0x7, 0x0 }, // 3720 |
| 11011 | { PseudoVLOXEI16_V_M1_M1, VLOXEI16_V, 0x0, 0x0 }, // 3721 |
| 11012 | { PseudoVLOXEI16_V_M1_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3722 |
| 11013 | { PseudoVLOXEI16_V_M2_M1, VLOXEI16_V, 0x0, 0x0 }, // 3723 |
| 11014 | { PseudoVLOXEI16_V_M2_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3724 |
| 11015 | { PseudoVLOXEI16_V_MF2_M1, VLOXEI16_V, 0x0, 0x0 }, // 3725 |
| 11016 | { PseudoVLOXEI16_V_MF2_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3726 |
| 11017 | { PseudoVLOXEI16_V_MF4_M1, VLOXEI16_V, 0x0, 0x0 }, // 3727 |
| 11018 | { PseudoVLOXEI16_V_MF4_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3728 |
| 11019 | { PseudoVLOXEI16_V_M1_M2, VLOXEI16_V, 0x1, 0x0 }, // 3729 |
| 11020 | { PseudoVLOXEI16_V_M1_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3730 |
| 11021 | { PseudoVLOXEI16_V_M2_M2, VLOXEI16_V, 0x1, 0x0 }, // 3731 |
| 11022 | { PseudoVLOXEI16_V_M2_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3732 |
| 11023 | { PseudoVLOXEI16_V_M4_M2, VLOXEI16_V, 0x1, 0x0 }, // 3733 |
| 11024 | { PseudoVLOXEI16_V_M4_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3734 |
| 11025 | { PseudoVLOXEI16_V_MF2_M2, VLOXEI16_V, 0x1, 0x0 }, // 3735 |
| 11026 | { PseudoVLOXEI16_V_MF2_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3736 |
| 11027 | { PseudoVLOXEI16_V_M1_M4, VLOXEI16_V, 0x2, 0x0 }, // 3737 |
| 11028 | { PseudoVLOXEI16_V_M1_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3738 |
| 11029 | { PseudoVLOXEI16_V_M2_M4, VLOXEI16_V, 0x2, 0x0 }, // 3739 |
| 11030 | { PseudoVLOXEI16_V_M2_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3740 |
| 11031 | { PseudoVLOXEI16_V_M4_M4, VLOXEI16_V, 0x2, 0x0 }, // 3741 |
| 11032 | { PseudoVLOXEI16_V_M4_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3742 |
| 11033 | { PseudoVLOXEI16_V_M8_M4, VLOXEI16_V, 0x2, 0x0 }, // 3743 |
| 11034 | { PseudoVLOXEI16_V_M8_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3744 |
| 11035 | { PseudoVLOXEI16_V_M2_M8, VLOXEI16_V, 0x3, 0x0 }, // 3745 |
| 11036 | { PseudoVLOXEI16_V_M2_M8_MASK, VLOXEI16_V, 0x3, 0x0 }, // 3746 |
| 11037 | { PseudoVLOXEI16_V_M4_M8, VLOXEI16_V, 0x3, 0x0 }, // 3747 |
| 11038 | { PseudoVLOXEI16_V_M4_M8_MASK, VLOXEI16_V, 0x3, 0x0 }, // 3748 |
| 11039 | { PseudoVLOXEI16_V_M8_M8, VLOXEI16_V, 0x3, 0x0 }, // 3749 |
| 11040 | { PseudoVLOXEI16_V_M8_M8_MASK, VLOXEI16_V, 0x3, 0x0 }, // 3750 |
| 11041 | { PseudoVLOXEI16_V_MF4_MF8, VLOXEI16_V, 0x5, 0x0 }, // 3751 |
| 11042 | { PseudoVLOXEI16_V_MF4_MF8_MASK, VLOXEI16_V, 0x5, 0x0 }, // 3752 |
| 11043 | { PseudoVLOXEI16_V_MF2_MF4, VLOXEI16_V, 0x6, 0x0 }, // 3753 |
| 11044 | { PseudoVLOXEI16_V_MF2_MF4_MASK, VLOXEI16_V, 0x6, 0x0 }, // 3754 |
| 11045 | { PseudoVLOXEI16_V_MF4_MF4, VLOXEI16_V, 0x6, 0x0 }, // 3755 |
| 11046 | { PseudoVLOXEI16_V_MF4_MF4_MASK, VLOXEI16_V, 0x6, 0x0 }, // 3756 |
| 11047 | { PseudoVLOXEI16_V_M1_MF2, VLOXEI16_V, 0x7, 0x0 }, // 3757 |
| 11048 | { PseudoVLOXEI16_V_M1_MF2_MASK, VLOXEI16_V, 0x7, 0x0 }, // 3758 |
| 11049 | { PseudoVLOXEI16_V_MF2_MF2, VLOXEI16_V, 0x7, 0x0 }, // 3759 |
| 11050 | { PseudoVLOXEI16_V_MF2_MF2_MASK, VLOXEI16_V, 0x7, 0x0 }, // 3760 |
| 11051 | { PseudoVLOXEI16_V_MF4_MF2, VLOXEI16_V, 0x7, 0x0 }, // 3761 |
| 11052 | { PseudoVLOXEI16_V_MF4_MF2_MASK, VLOXEI16_V, 0x7, 0x0 }, // 3762 |
| 11053 | { PseudoVLOXEI32_V_M1_M1, VLOXEI32_V, 0x0, 0x0 }, // 3763 |
| 11054 | { PseudoVLOXEI32_V_M1_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3764 |
| 11055 | { PseudoVLOXEI32_V_M2_M1, VLOXEI32_V, 0x0, 0x0 }, // 3765 |
| 11056 | { PseudoVLOXEI32_V_M2_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3766 |
| 11057 | { PseudoVLOXEI32_V_M4_M1, VLOXEI32_V, 0x0, 0x0 }, // 3767 |
| 11058 | { PseudoVLOXEI32_V_M4_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3768 |
| 11059 | { PseudoVLOXEI32_V_MF2_M1, VLOXEI32_V, 0x0, 0x0 }, // 3769 |
| 11060 | { PseudoVLOXEI32_V_MF2_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3770 |
| 11061 | { PseudoVLOXEI32_V_M1_M2, VLOXEI32_V, 0x1, 0x0 }, // 3771 |
| 11062 | { PseudoVLOXEI32_V_M1_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3772 |
| 11063 | { PseudoVLOXEI32_V_M2_M2, VLOXEI32_V, 0x1, 0x0 }, // 3773 |
| 11064 | { PseudoVLOXEI32_V_M2_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3774 |
| 11065 | { PseudoVLOXEI32_V_M4_M2, VLOXEI32_V, 0x1, 0x0 }, // 3775 |
| 11066 | { PseudoVLOXEI32_V_M4_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3776 |
| 11067 | { PseudoVLOXEI32_V_M8_M2, VLOXEI32_V, 0x1, 0x0 }, // 3777 |
| 11068 | { PseudoVLOXEI32_V_M8_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3778 |
| 11069 | { PseudoVLOXEI32_V_M2_M4, VLOXEI32_V, 0x2, 0x0 }, // 3779 |
| 11070 | { PseudoVLOXEI32_V_M2_M4_MASK, VLOXEI32_V, 0x2, 0x0 }, // 3780 |
| 11071 | { PseudoVLOXEI32_V_M4_M4, VLOXEI32_V, 0x2, 0x0 }, // 3781 |
| 11072 | { PseudoVLOXEI32_V_M4_M4_MASK, VLOXEI32_V, 0x2, 0x0 }, // 3782 |
| 11073 | { PseudoVLOXEI32_V_M8_M4, VLOXEI32_V, 0x2, 0x0 }, // 3783 |
| 11074 | { PseudoVLOXEI32_V_M8_M4_MASK, VLOXEI32_V, 0x2, 0x0 }, // 3784 |
| 11075 | { PseudoVLOXEI32_V_M4_M8, VLOXEI32_V, 0x3, 0x0 }, // 3785 |
| 11076 | { PseudoVLOXEI32_V_M4_M8_MASK, VLOXEI32_V, 0x3, 0x0 }, // 3786 |
| 11077 | { PseudoVLOXEI32_V_M8_M8, VLOXEI32_V, 0x3, 0x0 }, // 3787 |
| 11078 | { PseudoVLOXEI32_V_M8_M8_MASK, VLOXEI32_V, 0x3, 0x0 }, // 3788 |
| 11079 | { PseudoVLOXEI32_V_MF2_MF8, VLOXEI32_V, 0x5, 0x0 }, // 3789 |
| 11080 | { PseudoVLOXEI32_V_MF2_MF8_MASK, VLOXEI32_V, 0x5, 0x0 }, // 3790 |
| 11081 | { PseudoVLOXEI32_V_M1_MF4, VLOXEI32_V, 0x6, 0x0 }, // 3791 |
| 11082 | { PseudoVLOXEI32_V_M1_MF4_MASK, VLOXEI32_V, 0x6, 0x0 }, // 3792 |
| 11083 | { PseudoVLOXEI32_V_MF2_MF4, VLOXEI32_V, 0x6, 0x0 }, // 3793 |
| 11084 | { PseudoVLOXEI32_V_MF2_MF4_MASK, VLOXEI32_V, 0x6, 0x0 }, // 3794 |
| 11085 | { PseudoVLOXEI32_V_M1_MF2, VLOXEI32_V, 0x7, 0x0 }, // 3795 |
| 11086 | { PseudoVLOXEI32_V_M1_MF2_MASK, VLOXEI32_V, 0x7, 0x0 }, // 3796 |
| 11087 | { PseudoVLOXEI32_V_M2_MF2, VLOXEI32_V, 0x7, 0x0 }, // 3797 |
| 11088 | { PseudoVLOXEI32_V_M2_MF2_MASK, VLOXEI32_V, 0x7, 0x0 }, // 3798 |
| 11089 | { PseudoVLOXEI32_V_MF2_MF2, VLOXEI32_V, 0x7, 0x0 }, // 3799 |
| 11090 | { PseudoVLOXEI32_V_MF2_MF2_MASK, VLOXEI32_V, 0x7, 0x0 }, // 3800 |
| 11091 | { PseudoVLOXEI64_V_M1_M1, VLOXEI64_V, 0x0, 0x0 }, // 3801 |
| 11092 | { PseudoVLOXEI64_V_M1_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3802 |
| 11093 | { PseudoVLOXEI64_V_M2_M1, VLOXEI64_V, 0x0, 0x0 }, // 3803 |
| 11094 | { PseudoVLOXEI64_V_M2_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3804 |
| 11095 | { PseudoVLOXEI64_V_M4_M1, VLOXEI64_V, 0x0, 0x0 }, // 3805 |
| 11096 | { PseudoVLOXEI64_V_M4_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3806 |
| 11097 | { PseudoVLOXEI64_V_M8_M1, VLOXEI64_V, 0x0, 0x0 }, // 3807 |
| 11098 | { PseudoVLOXEI64_V_M8_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3808 |
| 11099 | { PseudoVLOXEI64_V_M2_M2, VLOXEI64_V, 0x1, 0x0 }, // 3809 |
| 11100 | { PseudoVLOXEI64_V_M2_M2_MASK, VLOXEI64_V, 0x1, 0x0 }, // 3810 |
| 11101 | { PseudoVLOXEI64_V_M4_M2, VLOXEI64_V, 0x1, 0x0 }, // 3811 |
| 11102 | { PseudoVLOXEI64_V_M4_M2_MASK, VLOXEI64_V, 0x1, 0x0 }, // 3812 |
| 11103 | { PseudoVLOXEI64_V_M8_M2, VLOXEI64_V, 0x1, 0x0 }, // 3813 |
| 11104 | { PseudoVLOXEI64_V_M8_M2_MASK, VLOXEI64_V, 0x1, 0x0 }, // 3814 |
| 11105 | { PseudoVLOXEI64_V_M4_M4, VLOXEI64_V, 0x2, 0x0 }, // 3815 |
| 11106 | { PseudoVLOXEI64_V_M4_M4_MASK, VLOXEI64_V, 0x2, 0x0 }, // 3816 |
| 11107 | { PseudoVLOXEI64_V_M8_M4, VLOXEI64_V, 0x2, 0x0 }, // 3817 |
| 11108 | { PseudoVLOXEI64_V_M8_M4_MASK, VLOXEI64_V, 0x2, 0x0 }, // 3818 |
| 11109 | { PseudoVLOXEI64_V_M8_M8, VLOXEI64_V, 0x3, 0x0 }, // 3819 |
| 11110 | { PseudoVLOXEI64_V_M8_M8_MASK, VLOXEI64_V, 0x3, 0x0 }, // 3820 |
| 11111 | { PseudoVLOXEI64_V_M1_MF8, VLOXEI64_V, 0x5, 0x0 }, // 3821 |
| 11112 | { PseudoVLOXEI64_V_M1_MF8_MASK, VLOXEI64_V, 0x5, 0x0 }, // 3822 |
| 11113 | { PseudoVLOXEI64_V_M1_MF4, VLOXEI64_V, 0x6, 0x0 }, // 3823 |
| 11114 | { PseudoVLOXEI64_V_M1_MF4_MASK, VLOXEI64_V, 0x6, 0x0 }, // 3824 |
| 11115 | { PseudoVLOXEI64_V_M2_MF4, VLOXEI64_V, 0x6, 0x0 }, // 3825 |
| 11116 | { PseudoVLOXEI64_V_M2_MF4_MASK, VLOXEI64_V, 0x6, 0x0 }, // 3826 |
| 11117 | { PseudoVLOXEI64_V_M1_MF2, VLOXEI64_V, 0x7, 0x0 }, // 3827 |
| 11118 | { PseudoVLOXEI64_V_M1_MF2_MASK, VLOXEI64_V, 0x7, 0x0 }, // 3828 |
| 11119 | { PseudoVLOXEI64_V_M2_MF2, VLOXEI64_V, 0x7, 0x0 }, // 3829 |
| 11120 | { PseudoVLOXEI64_V_M2_MF2_MASK, VLOXEI64_V, 0x7, 0x0 }, // 3830 |
| 11121 | { PseudoVLOXEI64_V_M4_MF2, VLOXEI64_V, 0x7, 0x0 }, // 3831 |
| 11122 | { PseudoVLOXEI64_V_M4_MF2_MASK, VLOXEI64_V, 0x7, 0x0 }, // 3832 |
| 11123 | { PseudoVLOXEI8_V_M1_M1, VLOXEI8_V, 0x0, 0x0 }, // 3833 |
| 11124 | { PseudoVLOXEI8_V_M1_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3834 |
| 11125 | { PseudoVLOXEI8_V_MF2_M1, VLOXEI8_V, 0x0, 0x0 }, // 3835 |
| 11126 | { PseudoVLOXEI8_V_MF2_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3836 |
| 11127 | { PseudoVLOXEI8_V_MF4_M1, VLOXEI8_V, 0x0, 0x0 }, // 3837 |
| 11128 | { PseudoVLOXEI8_V_MF4_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3838 |
| 11129 | { PseudoVLOXEI8_V_MF8_M1, VLOXEI8_V, 0x0, 0x0 }, // 3839 |
| 11130 | { PseudoVLOXEI8_V_MF8_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3840 |
| 11131 | { PseudoVLOXEI8_V_M1_M2, VLOXEI8_V, 0x1, 0x0 }, // 3841 |
| 11132 | { PseudoVLOXEI8_V_M1_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3842 |
| 11133 | { PseudoVLOXEI8_V_M2_M2, VLOXEI8_V, 0x1, 0x0 }, // 3843 |
| 11134 | { PseudoVLOXEI8_V_M2_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3844 |
| 11135 | { PseudoVLOXEI8_V_MF2_M2, VLOXEI8_V, 0x1, 0x0 }, // 3845 |
| 11136 | { PseudoVLOXEI8_V_MF2_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3846 |
| 11137 | { PseudoVLOXEI8_V_MF4_M2, VLOXEI8_V, 0x1, 0x0 }, // 3847 |
| 11138 | { PseudoVLOXEI8_V_MF4_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3848 |
| 11139 | { PseudoVLOXEI8_V_M1_M4, VLOXEI8_V, 0x2, 0x0 }, // 3849 |
| 11140 | { PseudoVLOXEI8_V_M1_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3850 |
| 11141 | { PseudoVLOXEI8_V_M2_M4, VLOXEI8_V, 0x2, 0x0 }, // 3851 |
| 11142 | { PseudoVLOXEI8_V_M2_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3852 |
| 11143 | { PseudoVLOXEI8_V_M4_M4, VLOXEI8_V, 0x2, 0x0 }, // 3853 |
| 11144 | { PseudoVLOXEI8_V_M4_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3854 |
| 11145 | { PseudoVLOXEI8_V_MF2_M4, VLOXEI8_V, 0x2, 0x0 }, // 3855 |
| 11146 | { PseudoVLOXEI8_V_MF2_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3856 |
| 11147 | { PseudoVLOXEI8_V_M1_M8, VLOXEI8_V, 0x3, 0x0 }, // 3857 |
| 11148 | { PseudoVLOXEI8_V_M1_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3858 |
| 11149 | { PseudoVLOXEI8_V_M2_M8, VLOXEI8_V, 0x3, 0x0 }, // 3859 |
| 11150 | { PseudoVLOXEI8_V_M2_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3860 |
| 11151 | { PseudoVLOXEI8_V_M4_M8, VLOXEI8_V, 0x3, 0x0 }, // 3861 |
| 11152 | { PseudoVLOXEI8_V_M4_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3862 |
| 11153 | { PseudoVLOXEI8_V_M8_M8, VLOXEI8_V, 0x3, 0x0 }, // 3863 |
| 11154 | { PseudoVLOXEI8_V_M8_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3864 |
| 11155 | { PseudoVLOXEI8_V_MF8_MF8, VLOXEI8_V, 0x5, 0x0 }, // 3865 |
| 11156 | { PseudoVLOXEI8_V_MF8_MF8_MASK, VLOXEI8_V, 0x5, 0x0 }, // 3866 |
| 11157 | { PseudoVLOXEI8_V_MF4_MF4, VLOXEI8_V, 0x6, 0x0 }, // 3867 |
| 11158 | { PseudoVLOXEI8_V_MF4_MF4_MASK, VLOXEI8_V, 0x6, 0x0 }, // 3868 |
| 11159 | { PseudoVLOXEI8_V_MF8_MF4, VLOXEI8_V, 0x6, 0x0 }, // 3869 |
| 11160 | { PseudoVLOXEI8_V_MF8_MF4_MASK, VLOXEI8_V, 0x6, 0x0 }, // 3870 |
| 11161 | { PseudoVLOXEI8_V_MF2_MF2, VLOXEI8_V, 0x7, 0x0 }, // 3871 |
| 11162 | { PseudoVLOXEI8_V_MF2_MF2_MASK, VLOXEI8_V, 0x7, 0x0 }, // 3872 |
| 11163 | { PseudoVLOXEI8_V_MF4_MF2, VLOXEI8_V, 0x7, 0x0 }, // 3873 |
| 11164 | { PseudoVLOXEI8_V_MF4_MF2_MASK, VLOXEI8_V, 0x7, 0x0 }, // 3874 |
| 11165 | { PseudoVLOXEI8_V_MF8_MF2, VLOXEI8_V, 0x7, 0x0 }, // 3875 |
| 11166 | { PseudoVLOXEI8_V_MF8_MF2_MASK, VLOXEI8_V, 0x7, 0x0 }, // 3876 |
| 11167 | { PseudoVLOXSEG2EI16_V_M1_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3877 |
| 11168 | { PseudoVLOXSEG2EI16_V_M1_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3878 |
| 11169 | { PseudoVLOXSEG2EI16_V_M2_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3879 |
| 11170 | { PseudoVLOXSEG2EI16_V_M2_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3880 |
| 11171 | { PseudoVLOXSEG2EI16_V_MF2_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3881 |
| 11172 | { PseudoVLOXSEG2EI16_V_MF2_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3882 |
| 11173 | { PseudoVLOXSEG2EI16_V_MF4_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3883 |
| 11174 | { PseudoVLOXSEG2EI16_V_MF4_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3884 |
| 11175 | { PseudoVLOXSEG2EI16_V_M1_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3885 |
| 11176 | { PseudoVLOXSEG2EI16_V_M1_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3886 |
| 11177 | { PseudoVLOXSEG2EI16_V_M2_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3887 |
| 11178 | { PseudoVLOXSEG2EI16_V_M2_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3888 |
| 11179 | { PseudoVLOXSEG2EI16_V_M4_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3889 |
| 11180 | { PseudoVLOXSEG2EI16_V_M4_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3890 |
| 11181 | { PseudoVLOXSEG2EI16_V_MF2_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3891 |
| 11182 | { PseudoVLOXSEG2EI16_V_MF2_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3892 |
| 11183 | { PseudoVLOXSEG2EI16_V_M1_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3893 |
| 11184 | { PseudoVLOXSEG2EI16_V_M1_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3894 |
| 11185 | { PseudoVLOXSEG2EI16_V_M2_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3895 |
| 11186 | { PseudoVLOXSEG2EI16_V_M2_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3896 |
| 11187 | { PseudoVLOXSEG2EI16_V_M4_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3897 |
| 11188 | { PseudoVLOXSEG2EI16_V_M4_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3898 |
| 11189 | { PseudoVLOXSEG2EI16_V_M8_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3899 |
| 11190 | { PseudoVLOXSEG2EI16_V_M8_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3900 |
| 11191 | { PseudoVLOXSEG2EI16_V_MF4_MF8, VLOXSEG2EI16_V, 0x5, 0x0 }, // 3901 |
| 11192 | { PseudoVLOXSEG2EI16_V_MF4_MF8_MASK, VLOXSEG2EI16_V, 0x5, 0x0 }, // 3902 |
| 11193 | { PseudoVLOXSEG2EI16_V_MF2_MF4, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3903 |
| 11194 | { PseudoVLOXSEG2EI16_V_MF2_MF4_MASK, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3904 |
| 11195 | { PseudoVLOXSEG2EI16_V_MF4_MF4, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3905 |
| 11196 | { PseudoVLOXSEG2EI16_V_MF4_MF4_MASK, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3906 |
| 11197 | { PseudoVLOXSEG2EI16_V_M1_MF2, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3907 |
| 11198 | { PseudoVLOXSEG2EI16_V_M1_MF2_MASK, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3908 |
| 11199 | { PseudoVLOXSEG2EI16_V_MF2_MF2, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3909 |
| 11200 | { PseudoVLOXSEG2EI16_V_MF2_MF2_MASK, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3910 |
| 11201 | { PseudoVLOXSEG2EI16_V_MF4_MF2, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3911 |
| 11202 | { PseudoVLOXSEG2EI16_V_MF4_MF2_MASK, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3912 |
| 11203 | { PseudoVLOXSEG2EI32_V_M1_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3913 |
| 11204 | { PseudoVLOXSEG2EI32_V_M1_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3914 |
| 11205 | { PseudoVLOXSEG2EI32_V_M2_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3915 |
| 11206 | { PseudoVLOXSEG2EI32_V_M2_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3916 |
| 11207 | { PseudoVLOXSEG2EI32_V_M4_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3917 |
| 11208 | { PseudoVLOXSEG2EI32_V_M4_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3918 |
| 11209 | { PseudoVLOXSEG2EI32_V_MF2_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3919 |
| 11210 | { PseudoVLOXSEG2EI32_V_MF2_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3920 |
| 11211 | { PseudoVLOXSEG2EI32_V_M1_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3921 |
| 11212 | { PseudoVLOXSEG2EI32_V_M1_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3922 |
| 11213 | { PseudoVLOXSEG2EI32_V_M2_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3923 |
| 11214 | { PseudoVLOXSEG2EI32_V_M2_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3924 |
| 11215 | { PseudoVLOXSEG2EI32_V_M4_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3925 |
| 11216 | { PseudoVLOXSEG2EI32_V_M4_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3926 |
| 11217 | { PseudoVLOXSEG2EI32_V_M8_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3927 |
| 11218 | { PseudoVLOXSEG2EI32_V_M8_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3928 |
| 11219 | { PseudoVLOXSEG2EI32_V_M2_M4, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3929 |
| 11220 | { PseudoVLOXSEG2EI32_V_M2_M4_MASK, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3930 |
| 11221 | { PseudoVLOXSEG2EI32_V_M4_M4, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3931 |
| 11222 | { PseudoVLOXSEG2EI32_V_M4_M4_MASK, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3932 |
| 11223 | { PseudoVLOXSEG2EI32_V_M8_M4, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3933 |
| 11224 | { PseudoVLOXSEG2EI32_V_M8_M4_MASK, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3934 |
| 11225 | { PseudoVLOXSEG2EI32_V_MF2_MF8, VLOXSEG2EI32_V, 0x5, 0x0 }, // 3935 |
| 11226 | { PseudoVLOXSEG2EI32_V_MF2_MF8_MASK, VLOXSEG2EI32_V, 0x5, 0x0 }, // 3936 |
| 11227 | { PseudoVLOXSEG2EI32_V_M1_MF4, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3937 |
| 11228 | { PseudoVLOXSEG2EI32_V_M1_MF4_MASK, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3938 |
| 11229 | { PseudoVLOXSEG2EI32_V_MF2_MF4, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3939 |
| 11230 | { PseudoVLOXSEG2EI32_V_MF2_MF4_MASK, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3940 |
| 11231 | { PseudoVLOXSEG2EI32_V_M1_MF2, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3941 |
| 11232 | { PseudoVLOXSEG2EI32_V_M1_MF2_MASK, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3942 |
| 11233 | { PseudoVLOXSEG2EI32_V_M2_MF2, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3943 |
| 11234 | { PseudoVLOXSEG2EI32_V_M2_MF2_MASK, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3944 |
| 11235 | { PseudoVLOXSEG2EI32_V_MF2_MF2, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3945 |
| 11236 | { PseudoVLOXSEG2EI32_V_MF2_MF2_MASK, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3946 |
| 11237 | { PseudoVLOXSEG2EI64_V_M1_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3947 |
| 11238 | { PseudoVLOXSEG2EI64_V_M1_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3948 |
| 11239 | { PseudoVLOXSEG2EI64_V_M2_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3949 |
| 11240 | { PseudoVLOXSEG2EI64_V_M2_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3950 |
| 11241 | { PseudoVLOXSEG2EI64_V_M4_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3951 |
| 11242 | { PseudoVLOXSEG2EI64_V_M4_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3952 |
| 11243 | { PseudoVLOXSEG2EI64_V_M8_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3953 |
| 11244 | { PseudoVLOXSEG2EI64_V_M8_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3954 |
| 11245 | { PseudoVLOXSEG2EI64_V_M2_M2, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3955 |
| 11246 | { PseudoVLOXSEG2EI64_V_M2_M2_MASK, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3956 |
| 11247 | { PseudoVLOXSEG2EI64_V_M4_M2, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3957 |
| 11248 | { PseudoVLOXSEG2EI64_V_M4_M2_MASK, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3958 |
| 11249 | { PseudoVLOXSEG2EI64_V_M8_M2, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3959 |
| 11250 | { PseudoVLOXSEG2EI64_V_M8_M2_MASK, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3960 |
| 11251 | { PseudoVLOXSEG2EI64_V_M4_M4, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3961 |
| 11252 | { PseudoVLOXSEG2EI64_V_M4_M4_MASK, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3962 |
| 11253 | { PseudoVLOXSEG2EI64_V_M8_M4, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3963 |
| 11254 | { PseudoVLOXSEG2EI64_V_M8_M4_MASK, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3964 |
| 11255 | { PseudoVLOXSEG2EI64_V_M1_MF8, VLOXSEG2EI64_V, 0x5, 0x0 }, // 3965 |
| 11256 | { PseudoVLOXSEG2EI64_V_M1_MF8_MASK, VLOXSEG2EI64_V, 0x5, 0x0 }, // 3966 |
| 11257 | { PseudoVLOXSEG2EI64_V_M1_MF4, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3967 |
| 11258 | { PseudoVLOXSEG2EI64_V_M1_MF4_MASK, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3968 |
| 11259 | { PseudoVLOXSEG2EI64_V_M2_MF4, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3969 |
| 11260 | { PseudoVLOXSEG2EI64_V_M2_MF4_MASK, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3970 |
| 11261 | { PseudoVLOXSEG2EI64_V_M1_MF2, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3971 |
| 11262 | { PseudoVLOXSEG2EI64_V_M1_MF2_MASK, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3972 |
| 11263 | { PseudoVLOXSEG2EI64_V_M2_MF2, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3973 |
| 11264 | { PseudoVLOXSEG2EI64_V_M2_MF2_MASK, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3974 |
| 11265 | { PseudoVLOXSEG2EI64_V_M4_MF2, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3975 |
| 11266 | { PseudoVLOXSEG2EI64_V_M4_MF2_MASK, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3976 |
| 11267 | { PseudoVLOXSEG2EI8_V_M1_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3977 |
| 11268 | { PseudoVLOXSEG2EI8_V_M1_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3978 |
| 11269 | { PseudoVLOXSEG2EI8_V_MF2_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3979 |
| 11270 | { PseudoVLOXSEG2EI8_V_MF2_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3980 |
| 11271 | { PseudoVLOXSEG2EI8_V_MF4_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3981 |
| 11272 | { PseudoVLOXSEG2EI8_V_MF4_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3982 |
| 11273 | { PseudoVLOXSEG2EI8_V_MF8_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3983 |
| 11274 | { PseudoVLOXSEG2EI8_V_MF8_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3984 |
| 11275 | { PseudoVLOXSEG2EI8_V_M1_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3985 |
| 11276 | { PseudoVLOXSEG2EI8_V_M1_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3986 |
| 11277 | { PseudoVLOXSEG2EI8_V_M2_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3987 |
| 11278 | { PseudoVLOXSEG2EI8_V_M2_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3988 |
| 11279 | { PseudoVLOXSEG2EI8_V_MF2_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3989 |
| 11280 | { PseudoVLOXSEG2EI8_V_MF2_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3990 |
| 11281 | { PseudoVLOXSEG2EI8_V_MF4_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3991 |
| 11282 | { PseudoVLOXSEG2EI8_V_MF4_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3992 |
| 11283 | { PseudoVLOXSEG2EI8_V_M1_M4, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3993 |
| 11284 | { PseudoVLOXSEG2EI8_V_M1_M4_MASK, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3994 |
| 11285 | { PseudoVLOXSEG2EI8_V_M2_M4, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3995 |
| 11286 | { PseudoVLOXSEG2EI8_V_M2_M4_MASK, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3996 |
| 11287 | { PseudoVLOXSEG2EI8_V_M4_M4, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3997 |
| 11288 | { PseudoVLOXSEG2EI8_V_M4_M4_MASK, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3998 |
| 11289 | { PseudoVLOXSEG2EI8_V_MF2_M4, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3999 |
| 11290 | { PseudoVLOXSEG2EI8_V_MF2_M4_MASK, VLOXSEG2EI8_V, 0x2, 0x0 }, // 4000 |
| 11291 | { PseudoVLOXSEG2EI8_V_MF8_MF8, VLOXSEG2EI8_V, 0x5, 0x0 }, // 4001 |
| 11292 | { PseudoVLOXSEG2EI8_V_MF8_MF8_MASK, VLOXSEG2EI8_V, 0x5, 0x0 }, // 4002 |
| 11293 | { PseudoVLOXSEG2EI8_V_MF4_MF4, VLOXSEG2EI8_V, 0x6, 0x0 }, // 4003 |
| 11294 | { PseudoVLOXSEG2EI8_V_MF4_MF4_MASK, VLOXSEG2EI8_V, 0x6, 0x0 }, // 4004 |
| 11295 | { PseudoVLOXSEG2EI8_V_MF8_MF4, VLOXSEG2EI8_V, 0x6, 0x0 }, // 4005 |
| 11296 | { PseudoVLOXSEG2EI8_V_MF8_MF4_MASK, VLOXSEG2EI8_V, 0x6, 0x0 }, // 4006 |
| 11297 | { PseudoVLOXSEG2EI8_V_MF2_MF2, VLOXSEG2EI8_V, 0x7, 0x0 }, // 4007 |
| 11298 | { PseudoVLOXSEG2EI8_V_MF2_MF2_MASK, VLOXSEG2EI8_V, 0x7, 0x0 }, // 4008 |
| 11299 | { PseudoVLOXSEG2EI8_V_MF4_MF2, VLOXSEG2EI8_V, 0x7, 0x0 }, // 4009 |
| 11300 | { PseudoVLOXSEG2EI8_V_MF4_MF2_MASK, VLOXSEG2EI8_V, 0x7, 0x0 }, // 4010 |
| 11301 | { PseudoVLOXSEG2EI8_V_MF8_MF2, VLOXSEG2EI8_V, 0x7, 0x0 }, // 4011 |
| 11302 | { PseudoVLOXSEG2EI8_V_MF8_MF2_MASK, VLOXSEG2EI8_V, 0x7, 0x0 }, // 4012 |
| 11303 | { PseudoVLOXSEG3EI16_V_M1_M1, VLOXSEG3EI16_V, 0x0, 0x0 }, // 4013 |
| 11304 | { PseudoVLOXSEG3EI16_V_M1_M1_MASK, VLOXSEG3EI16_V, 0x0, 0x0 }, // 4014 |
| 11305 | { PseudoVLOXSEG3EI16_V_M2_M1, VLOXSEG3EI16_V, 0x0, 0x0 }, // 4015 |
| 11306 | { PseudoVLOXSEG3EI16_V_M2_M1_MASK, VLOXSEG3EI16_V, 0x0, 0x0 }, // 4016 |
| 11307 | { PseudoVLOXSEG3EI16_V_MF2_M1, VLOXSEG3EI16_V, 0x0, 0x0 }, // 4017 |
| 11308 | { PseudoVLOXSEG3EI16_V_MF2_M1_MASK, VLOXSEG3EI16_V, 0x0, 0x0 }, // 4018 |
| 11309 | { PseudoVLOXSEG3EI16_V_MF4_M1, VLOXSEG3EI16_V, 0x0, 0x0 }, // 4019 |
| 11310 | { PseudoVLOXSEG3EI16_V_MF4_M1_MASK, VLOXSEG3EI16_V, 0x0, 0x0 }, // 4020 |
| 11311 | { PseudoVLOXSEG3EI16_V_M1_M2, VLOXSEG3EI16_V, 0x1, 0x0 }, // 4021 |
| 11312 | { PseudoVLOXSEG3EI16_V_M1_M2_MASK, VLOXSEG3EI16_V, 0x1, 0x0 }, // 4022 |
| 11313 | { PseudoVLOXSEG3EI16_V_M2_M2, VLOXSEG3EI16_V, 0x1, 0x0 }, // 4023 |
| 11314 | { PseudoVLOXSEG3EI16_V_M2_M2_MASK, VLOXSEG3EI16_V, 0x1, 0x0 }, // 4024 |
| 11315 | { PseudoVLOXSEG3EI16_V_M4_M2, VLOXSEG3EI16_V, 0x1, 0x0 }, // 4025 |
| 11316 | { PseudoVLOXSEG3EI16_V_M4_M2_MASK, VLOXSEG3EI16_V, 0x1, 0x0 }, // 4026 |
| 11317 | { PseudoVLOXSEG3EI16_V_MF2_M2, VLOXSEG3EI16_V, 0x1, 0x0 }, // 4027 |
| 11318 | { PseudoVLOXSEG3EI16_V_MF2_M2_MASK, VLOXSEG3EI16_V, 0x1, 0x0 }, // 4028 |
| 11319 | { PseudoVLOXSEG3EI16_V_MF4_MF8, VLOXSEG3EI16_V, 0x5, 0x0 }, // 4029 |
| 11320 | { PseudoVLOXSEG3EI16_V_MF4_MF8_MASK, VLOXSEG3EI16_V, 0x5, 0x0 }, // 4030 |
| 11321 | { PseudoVLOXSEG3EI16_V_MF2_MF4, VLOXSEG3EI16_V, 0x6, 0x0 }, // 4031 |
| 11322 | { PseudoVLOXSEG3EI16_V_MF2_MF4_MASK, VLOXSEG3EI16_V, 0x6, 0x0 }, // 4032 |
| 11323 | { PseudoVLOXSEG3EI16_V_MF4_MF4, VLOXSEG3EI16_V, 0x6, 0x0 }, // 4033 |
| 11324 | { PseudoVLOXSEG3EI16_V_MF4_MF4_MASK, VLOXSEG3EI16_V, 0x6, 0x0 }, // 4034 |
| 11325 | { PseudoVLOXSEG3EI16_V_M1_MF2, VLOXSEG3EI16_V, 0x7, 0x0 }, // 4035 |
| 11326 | { PseudoVLOXSEG3EI16_V_M1_MF2_MASK, VLOXSEG3EI16_V, 0x7, 0x0 }, // 4036 |
| 11327 | { PseudoVLOXSEG3EI16_V_MF2_MF2, VLOXSEG3EI16_V, 0x7, 0x0 }, // 4037 |
| 11328 | { PseudoVLOXSEG3EI16_V_MF2_MF2_MASK, VLOXSEG3EI16_V, 0x7, 0x0 }, // 4038 |
| 11329 | { PseudoVLOXSEG3EI16_V_MF4_MF2, VLOXSEG3EI16_V, 0x7, 0x0 }, // 4039 |
| 11330 | { PseudoVLOXSEG3EI16_V_MF4_MF2_MASK, VLOXSEG3EI16_V, 0x7, 0x0 }, // 4040 |
| 11331 | { PseudoVLOXSEG3EI32_V_M1_M1, VLOXSEG3EI32_V, 0x0, 0x0 }, // 4041 |
| 11332 | { PseudoVLOXSEG3EI32_V_M1_M1_MASK, VLOXSEG3EI32_V, 0x0, 0x0 }, // 4042 |
| 11333 | { PseudoVLOXSEG3EI32_V_M2_M1, VLOXSEG3EI32_V, 0x0, 0x0 }, // 4043 |
| 11334 | { PseudoVLOXSEG3EI32_V_M2_M1_MASK, VLOXSEG3EI32_V, 0x0, 0x0 }, // 4044 |
| 11335 | { PseudoVLOXSEG3EI32_V_M4_M1, VLOXSEG3EI32_V, 0x0, 0x0 }, // 4045 |
| 11336 | { PseudoVLOXSEG3EI32_V_M4_M1_MASK, VLOXSEG3EI32_V, 0x0, 0x0 }, // 4046 |
| 11337 | { PseudoVLOXSEG3EI32_V_MF2_M1, VLOXSEG3EI32_V, 0x0, 0x0 }, // 4047 |
| 11338 | { PseudoVLOXSEG3EI32_V_MF2_M1_MASK, VLOXSEG3EI32_V, 0x0, 0x0 }, // 4048 |
| 11339 | { PseudoVLOXSEG3EI32_V_M1_M2, VLOXSEG3EI32_V, 0x1, 0x0 }, // 4049 |
| 11340 | { PseudoVLOXSEG3EI32_V_M1_M2_MASK, VLOXSEG3EI32_V, 0x1, 0x0 }, // 4050 |
| 11341 | { PseudoVLOXSEG3EI32_V_M2_M2, VLOXSEG3EI32_V, 0x1, 0x0 }, // 4051 |
| 11342 | { PseudoVLOXSEG3EI32_V_M2_M2_MASK, VLOXSEG3EI32_V, 0x1, 0x0 }, // 4052 |
| 11343 | { PseudoVLOXSEG3EI32_V_M4_M2, VLOXSEG3EI32_V, 0x1, 0x0 }, // 4053 |
| 11344 | { PseudoVLOXSEG3EI32_V_M4_M2_MASK, VLOXSEG3EI32_V, 0x1, 0x0 }, // 4054 |
| 11345 | { PseudoVLOXSEG3EI32_V_M8_M2, VLOXSEG3EI32_V, 0x1, 0x0 }, // 4055 |
| 11346 | { PseudoVLOXSEG3EI32_V_M8_M2_MASK, VLOXSEG3EI32_V, 0x1, 0x0 }, // 4056 |
| 11347 | { PseudoVLOXSEG3EI32_V_MF2_MF8, VLOXSEG3EI32_V, 0x5, 0x0 }, // 4057 |
| 11348 | { PseudoVLOXSEG3EI32_V_MF2_MF8_MASK, VLOXSEG3EI32_V, 0x5, 0x0 }, // 4058 |
| 11349 | { PseudoVLOXSEG3EI32_V_M1_MF4, VLOXSEG3EI32_V, 0x6, 0x0 }, // 4059 |
| 11350 | { PseudoVLOXSEG3EI32_V_M1_MF4_MASK, VLOXSEG3EI32_V, 0x6, 0x0 }, // 4060 |
| 11351 | { PseudoVLOXSEG3EI32_V_MF2_MF4, VLOXSEG3EI32_V, 0x6, 0x0 }, // 4061 |
| 11352 | { PseudoVLOXSEG3EI32_V_MF2_MF4_MASK, VLOXSEG3EI32_V, 0x6, 0x0 }, // 4062 |
| 11353 | { PseudoVLOXSEG3EI32_V_M1_MF2, VLOXSEG3EI32_V, 0x7, 0x0 }, // 4063 |
| 11354 | { PseudoVLOXSEG3EI32_V_M1_MF2_MASK, VLOXSEG3EI32_V, 0x7, 0x0 }, // 4064 |
| 11355 | { PseudoVLOXSEG3EI32_V_M2_MF2, VLOXSEG3EI32_V, 0x7, 0x0 }, // 4065 |
| 11356 | { PseudoVLOXSEG3EI32_V_M2_MF2_MASK, VLOXSEG3EI32_V, 0x7, 0x0 }, // 4066 |
| 11357 | { PseudoVLOXSEG3EI32_V_MF2_MF2, VLOXSEG3EI32_V, 0x7, 0x0 }, // 4067 |
| 11358 | { PseudoVLOXSEG3EI32_V_MF2_MF2_MASK, VLOXSEG3EI32_V, 0x7, 0x0 }, // 4068 |
| 11359 | { PseudoVLOXSEG3EI64_V_M1_M1, VLOXSEG3EI64_V, 0x0, 0x0 }, // 4069 |
| 11360 | { PseudoVLOXSEG3EI64_V_M1_M1_MASK, VLOXSEG3EI64_V, 0x0, 0x0 }, // 4070 |
| 11361 | { PseudoVLOXSEG3EI64_V_M2_M1, VLOXSEG3EI64_V, 0x0, 0x0 }, // 4071 |
| 11362 | { PseudoVLOXSEG3EI64_V_M2_M1_MASK, VLOXSEG3EI64_V, 0x0, 0x0 }, // 4072 |
| 11363 | { PseudoVLOXSEG3EI64_V_M4_M1, VLOXSEG3EI64_V, 0x0, 0x0 }, // 4073 |
| 11364 | { PseudoVLOXSEG3EI64_V_M4_M1_MASK, VLOXSEG3EI64_V, 0x0, 0x0 }, // 4074 |
| 11365 | { PseudoVLOXSEG3EI64_V_M8_M1, VLOXSEG3EI64_V, 0x0, 0x0 }, // 4075 |
| 11366 | { PseudoVLOXSEG3EI64_V_M8_M1_MASK, VLOXSEG3EI64_V, 0x0, 0x0 }, // 4076 |
| 11367 | { PseudoVLOXSEG3EI64_V_M2_M2, VLOXSEG3EI64_V, 0x1, 0x0 }, // 4077 |
| 11368 | { PseudoVLOXSEG3EI64_V_M2_M2_MASK, VLOXSEG3EI64_V, 0x1, 0x0 }, // 4078 |
| 11369 | { PseudoVLOXSEG3EI64_V_M4_M2, VLOXSEG3EI64_V, 0x1, 0x0 }, // 4079 |
| 11370 | { PseudoVLOXSEG3EI64_V_M4_M2_MASK, VLOXSEG3EI64_V, 0x1, 0x0 }, // 4080 |
| 11371 | { PseudoVLOXSEG3EI64_V_M8_M2, VLOXSEG3EI64_V, 0x1, 0x0 }, // 4081 |
| 11372 | { PseudoVLOXSEG3EI64_V_M8_M2_MASK, VLOXSEG3EI64_V, 0x1, 0x0 }, // 4082 |
| 11373 | { PseudoVLOXSEG3EI64_V_M1_MF8, VLOXSEG3EI64_V, 0x5, 0x0 }, // 4083 |
| 11374 | { PseudoVLOXSEG3EI64_V_M1_MF8_MASK, VLOXSEG3EI64_V, 0x5, 0x0 }, // 4084 |
| 11375 | { PseudoVLOXSEG3EI64_V_M1_MF4, VLOXSEG3EI64_V, 0x6, 0x0 }, // 4085 |
| 11376 | { PseudoVLOXSEG3EI64_V_M1_MF4_MASK, VLOXSEG3EI64_V, 0x6, 0x0 }, // 4086 |
| 11377 | { PseudoVLOXSEG3EI64_V_M2_MF4, VLOXSEG3EI64_V, 0x6, 0x0 }, // 4087 |
| 11378 | { PseudoVLOXSEG3EI64_V_M2_MF4_MASK, VLOXSEG3EI64_V, 0x6, 0x0 }, // 4088 |
| 11379 | { PseudoVLOXSEG3EI64_V_M1_MF2, VLOXSEG3EI64_V, 0x7, 0x0 }, // 4089 |
| 11380 | { PseudoVLOXSEG3EI64_V_M1_MF2_MASK, VLOXSEG3EI64_V, 0x7, 0x0 }, // 4090 |
| 11381 | { PseudoVLOXSEG3EI64_V_M2_MF2, VLOXSEG3EI64_V, 0x7, 0x0 }, // 4091 |
| 11382 | { PseudoVLOXSEG3EI64_V_M2_MF2_MASK, VLOXSEG3EI64_V, 0x7, 0x0 }, // 4092 |
| 11383 | { PseudoVLOXSEG3EI64_V_M4_MF2, VLOXSEG3EI64_V, 0x7, 0x0 }, // 4093 |
| 11384 | { PseudoVLOXSEG3EI64_V_M4_MF2_MASK, VLOXSEG3EI64_V, 0x7, 0x0 }, // 4094 |
| 11385 | { PseudoVLOXSEG3EI8_V_M1_M1, VLOXSEG3EI8_V, 0x0, 0x0 }, // 4095 |
| 11386 | { PseudoVLOXSEG3EI8_V_M1_M1_MASK, VLOXSEG3EI8_V, 0x0, 0x0 }, // 4096 |
| 11387 | { PseudoVLOXSEG3EI8_V_MF2_M1, VLOXSEG3EI8_V, 0x0, 0x0 }, // 4097 |
| 11388 | { PseudoVLOXSEG3EI8_V_MF2_M1_MASK, VLOXSEG3EI8_V, 0x0, 0x0 }, // 4098 |
| 11389 | { PseudoVLOXSEG3EI8_V_MF4_M1, VLOXSEG3EI8_V, 0x0, 0x0 }, // 4099 |
| 11390 | { PseudoVLOXSEG3EI8_V_MF4_M1_MASK, VLOXSEG3EI8_V, 0x0, 0x0 }, // 4100 |
| 11391 | { PseudoVLOXSEG3EI8_V_MF8_M1, VLOXSEG3EI8_V, 0x0, 0x0 }, // 4101 |
| 11392 | { PseudoVLOXSEG3EI8_V_MF8_M1_MASK, VLOXSEG3EI8_V, 0x0, 0x0 }, // 4102 |
| 11393 | { PseudoVLOXSEG3EI8_V_M1_M2, VLOXSEG3EI8_V, 0x1, 0x0 }, // 4103 |
| 11394 | { PseudoVLOXSEG3EI8_V_M1_M2_MASK, VLOXSEG3EI8_V, 0x1, 0x0 }, // 4104 |
| 11395 | { PseudoVLOXSEG3EI8_V_M2_M2, VLOXSEG3EI8_V, 0x1, 0x0 }, // 4105 |
| 11396 | { PseudoVLOXSEG3EI8_V_M2_M2_MASK, VLOXSEG3EI8_V, 0x1, 0x0 }, // 4106 |
| 11397 | { PseudoVLOXSEG3EI8_V_MF2_M2, VLOXSEG3EI8_V, 0x1, 0x0 }, // 4107 |
| 11398 | { PseudoVLOXSEG3EI8_V_MF2_M2_MASK, VLOXSEG3EI8_V, 0x1, 0x0 }, // 4108 |
| 11399 | { PseudoVLOXSEG3EI8_V_MF4_M2, VLOXSEG3EI8_V, 0x1, 0x0 }, // 4109 |
| 11400 | { PseudoVLOXSEG3EI8_V_MF4_M2_MASK, VLOXSEG3EI8_V, 0x1, 0x0 }, // 4110 |
| 11401 | { PseudoVLOXSEG3EI8_V_MF8_MF8, VLOXSEG3EI8_V, 0x5, 0x0 }, // 4111 |
| 11402 | { PseudoVLOXSEG3EI8_V_MF8_MF8_MASK, VLOXSEG3EI8_V, 0x5, 0x0 }, // 4112 |
| 11403 | { PseudoVLOXSEG3EI8_V_MF4_MF4, VLOXSEG3EI8_V, 0x6, 0x0 }, // 4113 |
| 11404 | { PseudoVLOXSEG3EI8_V_MF4_MF4_MASK, VLOXSEG3EI8_V, 0x6, 0x0 }, // 4114 |
| 11405 | { PseudoVLOXSEG3EI8_V_MF8_MF4, VLOXSEG3EI8_V, 0x6, 0x0 }, // 4115 |
| 11406 | { PseudoVLOXSEG3EI8_V_MF8_MF4_MASK, VLOXSEG3EI8_V, 0x6, 0x0 }, // 4116 |
| 11407 | { PseudoVLOXSEG3EI8_V_MF2_MF2, VLOXSEG3EI8_V, 0x7, 0x0 }, // 4117 |
| 11408 | { PseudoVLOXSEG3EI8_V_MF2_MF2_MASK, VLOXSEG3EI8_V, 0x7, 0x0 }, // 4118 |
| 11409 | { PseudoVLOXSEG3EI8_V_MF4_MF2, VLOXSEG3EI8_V, 0x7, 0x0 }, // 4119 |
| 11410 | { PseudoVLOXSEG3EI8_V_MF4_MF2_MASK, VLOXSEG3EI8_V, 0x7, 0x0 }, // 4120 |
| 11411 | { PseudoVLOXSEG3EI8_V_MF8_MF2, VLOXSEG3EI8_V, 0x7, 0x0 }, // 4121 |
| 11412 | { PseudoVLOXSEG3EI8_V_MF8_MF2_MASK, VLOXSEG3EI8_V, 0x7, 0x0 }, // 4122 |
| 11413 | { PseudoVLOXSEG4EI16_V_M1_M1, VLOXSEG4EI16_V, 0x0, 0x0 }, // 4123 |
| 11414 | { PseudoVLOXSEG4EI16_V_M1_M1_MASK, VLOXSEG4EI16_V, 0x0, 0x0 }, // 4124 |
| 11415 | { PseudoVLOXSEG4EI16_V_M2_M1, VLOXSEG4EI16_V, 0x0, 0x0 }, // 4125 |
| 11416 | { PseudoVLOXSEG4EI16_V_M2_M1_MASK, VLOXSEG4EI16_V, 0x0, 0x0 }, // 4126 |
| 11417 | { PseudoVLOXSEG4EI16_V_MF2_M1, VLOXSEG4EI16_V, 0x0, 0x0 }, // 4127 |
| 11418 | { PseudoVLOXSEG4EI16_V_MF2_M1_MASK, VLOXSEG4EI16_V, 0x0, 0x0 }, // 4128 |
| 11419 | { PseudoVLOXSEG4EI16_V_MF4_M1, VLOXSEG4EI16_V, 0x0, 0x0 }, // 4129 |
| 11420 | { PseudoVLOXSEG4EI16_V_MF4_M1_MASK, VLOXSEG4EI16_V, 0x0, 0x0 }, // 4130 |
| 11421 | { PseudoVLOXSEG4EI16_V_M1_M2, VLOXSEG4EI16_V, 0x1, 0x0 }, // 4131 |
| 11422 | { PseudoVLOXSEG4EI16_V_M1_M2_MASK, VLOXSEG4EI16_V, 0x1, 0x0 }, // 4132 |
| 11423 | { PseudoVLOXSEG4EI16_V_M2_M2, VLOXSEG4EI16_V, 0x1, 0x0 }, // 4133 |
| 11424 | { PseudoVLOXSEG4EI16_V_M2_M2_MASK, VLOXSEG4EI16_V, 0x1, 0x0 }, // 4134 |
| 11425 | { PseudoVLOXSEG4EI16_V_M4_M2, VLOXSEG4EI16_V, 0x1, 0x0 }, // 4135 |
| 11426 | { PseudoVLOXSEG4EI16_V_M4_M2_MASK, VLOXSEG4EI16_V, 0x1, 0x0 }, // 4136 |
| 11427 | { PseudoVLOXSEG4EI16_V_MF2_M2, VLOXSEG4EI16_V, 0x1, 0x0 }, // 4137 |
| 11428 | { PseudoVLOXSEG4EI16_V_MF2_M2_MASK, VLOXSEG4EI16_V, 0x1, 0x0 }, // 4138 |
| 11429 | { PseudoVLOXSEG4EI16_V_MF4_MF8, VLOXSEG4EI16_V, 0x5, 0x0 }, // 4139 |
| 11430 | { PseudoVLOXSEG4EI16_V_MF4_MF8_MASK, VLOXSEG4EI16_V, 0x5, 0x0 }, // 4140 |
| 11431 | { PseudoVLOXSEG4EI16_V_MF2_MF4, VLOXSEG4EI16_V, 0x6, 0x0 }, // 4141 |
| 11432 | { PseudoVLOXSEG4EI16_V_MF2_MF4_MASK, VLOXSEG4EI16_V, 0x6, 0x0 }, // 4142 |
| 11433 | { PseudoVLOXSEG4EI16_V_MF4_MF4, VLOXSEG4EI16_V, 0x6, 0x0 }, // 4143 |
| 11434 | { PseudoVLOXSEG4EI16_V_MF4_MF4_MASK, VLOXSEG4EI16_V, 0x6, 0x0 }, // 4144 |
| 11435 | { PseudoVLOXSEG4EI16_V_M1_MF2, VLOXSEG4EI16_V, 0x7, 0x0 }, // 4145 |
| 11436 | { PseudoVLOXSEG4EI16_V_M1_MF2_MASK, VLOXSEG4EI16_V, 0x7, 0x0 }, // 4146 |
| 11437 | { PseudoVLOXSEG4EI16_V_MF2_MF2, VLOXSEG4EI16_V, 0x7, 0x0 }, // 4147 |
| 11438 | { PseudoVLOXSEG4EI16_V_MF2_MF2_MASK, VLOXSEG4EI16_V, 0x7, 0x0 }, // 4148 |
| 11439 | { PseudoVLOXSEG4EI16_V_MF4_MF2, VLOXSEG4EI16_V, 0x7, 0x0 }, // 4149 |
| 11440 | { PseudoVLOXSEG4EI16_V_MF4_MF2_MASK, VLOXSEG4EI16_V, 0x7, 0x0 }, // 4150 |
| 11441 | { PseudoVLOXSEG4EI32_V_M1_M1, VLOXSEG4EI32_V, 0x0, 0x0 }, // 4151 |
| 11442 | { PseudoVLOXSEG4EI32_V_M1_M1_MASK, VLOXSEG4EI32_V, 0x0, 0x0 }, // 4152 |
| 11443 | { PseudoVLOXSEG4EI32_V_M2_M1, VLOXSEG4EI32_V, 0x0, 0x0 }, // 4153 |
| 11444 | { PseudoVLOXSEG4EI32_V_M2_M1_MASK, VLOXSEG4EI32_V, 0x0, 0x0 }, // 4154 |
| 11445 | { PseudoVLOXSEG4EI32_V_M4_M1, VLOXSEG4EI32_V, 0x0, 0x0 }, // 4155 |
| 11446 | { PseudoVLOXSEG4EI32_V_M4_M1_MASK, VLOXSEG4EI32_V, 0x0, 0x0 }, // 4156 |
| 11447 | { PseudoVLOXSEG4EI32_V_MF2_M1, VLOXSEG4EI32_V, 0x0, 0x0 }, // 4157 |
| 11448 | { PseudoVLOXSEG4EI32_V_MF2_M1_MASK, VLOXSEG4EI32_V, 0x0, 0x0 }, // 4158 |
| 11449 | { PseudoVLOXSEG4EI32_V_M1_M2, VLOXSEG4EI32_V, 0x1, 0x0 }, // 4159 |
| 11450 | { PseudoVLOXSEG4EI32_V_M1_M2_MASK, VLOXSEG4EI32_V, 0x1, 0x0 }, // 4160 |
| 11451 | { PseudoVLOXSEG4EI32_V_M2_M2, VLOXSEG4EI32_V, 0x1, 0x0 }, // 4161 |
| 11452 | { PseudoVLOXSEG4EI32_V_M2_M2_MASK, VLOXSEG4EI32_V, 0x1, 0x0 }, // 4162 |
| 11453 | { PseudoVLOXSEG4EI32_V_M4_M2, VLOXSEG4EI32_V, 0x1, 0x0 }, // 4163 |
| 11454 | { PseudoVLOXSEG4EI32_V_M4_M2_MASK, VLOXSEG4EI32_V, 0x1, 0x0 }, // 4164 |
| 11455 | { PseudoVLOXSEG4EI32_V_M8_M2, VLOXSEG4EI32_V, 0x1, 0x0 }, // 4165 |
| 11456 | { PseudoVLOXSEG4EI32_V_M8_M2_MASK, VLOXSEG4EI32_V, 0x1, 0x0 }, // 4166 |
| 11457 | { PseudoVLOXSEG4EI32_V_MF2_MF8, VLOXSEG4EI32_V, 0x5, 0x0 }, // 4167 |
| 11458 | { PseudoVLOXSEG4EI32_V_MF2_MF8_MASK, VLOXSEG4EI32_V, 0x5, 0x0 }, // 4168 |
| 11459 | { PseudoVLOXSEG4EI32_V_M1_MF4, VLOXSEG4EI32_V, 0x6, 0x0 }, // 4169 |
| 11460 | { PseudoVLOXSEG4EI32_V_M1_MF4_MASK, VLOXSEG4EI32_V, 0x6, 0x0 }, // 4170 |
| 11461 | { PseudoVLOXSEG4EI32_V_MF2_MF4, VLOXSEG4EI32_V, 0x6, 0x0 }, // 4171 |
| 11462 | { PseudoVLOXSEG4EI32_V_MF2_MF4_MASK, VLOXSEG4EI32_V, 0x6, 0x0 }, // 4172 |
| 11463 | { PseudoVLOXSEG4EI32_V_M1_MF2, VLOXSEG4EI32_V, 0x7, 0x0 }, // 4173 |
| 11464 | { PseudoVLOXSEG4EI32_V_M1_MF2_MASK, VLOXSEG4EI32_V, 0x7, 0x0 }, // 4174 |
| 11465 | { PseudoVLOXSEG4EI32_V_M2_MF2, VLOXSEG4EI32_V, 0x7, 0x0 }, // 4175 |
| 11466 | { PseudoVLOXSEG4EI32_V_M2_MF2_MASK, VLOXSEG4EI32_V, 0x7, 0x0 }, // 4176 |
| 11467 | { PseudoVLOXSEG4EI32_V_MF2_MF2, VLOXSEG4EI32_V, 0x7, 0x0 }, // 4177 |
| 11468 | { PseudoVLOXSEG4EI32_V_MF2_MF2_MASK, VLOXSEG4EI32_V, 0x7, 0x0 }, // 4178 |
| 11469 | { PseudoVLOXSEG4EI64_V_M1_M1, VLOXSEG4EI64_V, 0x0, 0x0 }, // 4179 |
| 11470 | { PseudoVLOXSEG4EI64_V_M1_M1_MASK, VLOXSEG4EI64_V, 0x0, 0x0 }, // 4180 |
| 11471 | { PseudoVLOXSEG4EI64_V_M2_M1, VLOXSEG4EI64_V, 0x0, 0x0 }, // 4181 |
| 11472 | { PseudoVLOXSEG4EI64_V_M2_M1_MASK, VLOXSEG4EI64_V, 0x0, 0x0 }, // 4182 |
| 11473 | { PseudoVLOXSEG4EI64_V_M4_M1, VLOXSEG4EI64_V, 0x0, 0x0 }, // 4183 |
| 11474 | { PseudoVLOXSEG4EI64_V_M4_M1_MASK, VLOXSEG4EI64_V, 0x0, 0x0 }, // 4184 |
| 11475 | { PseudoVLOXSEG4EI64_V_M8_M1, VLOXSEG4EI64_V, 0x0, 0x0 }, // 4185 |
| 11476 | { PseudoVLOXSEG4EI64_V_M8_M1_MASK, VLOXSEG4EI64_V, 0x0, 0x0 }, // 4186 |
| 11477 | { PseudoVLOXSEG4EI64_V_M2_M2, VLOXSEG4EI64_V, 0x1, 0x0 }, // 4187 |
| 11478 | { PseudoVLOXSEG4EI64_V_M2_M2_MASK, VLOXSEG4EI64_V, 0x1, 0x0 }, // 4188 |
| 11479 | { PseudoVLOXSEG4EI64_V_M4_M2, VLOXSEG4EI64_V, 0x1, 0x0 }, // 4189 |
| 11480 | { PseudoVLOXSEG4EI64_V_M4_M2_MASK, VLOXSEG4EI64_V, 0x1, 0x0 }, // 4190 |
| 11481 | { PseudoVLOXSEG4EI64_V_M8_M2, VLOXSEG4EI64_V, 0x1, 0x0 }, // 4191 |
| 11482 | { PseudoVLOXSEG4EI64_V_M8_M2_MASK, VLOXSEG4EI64_V, 0x1, 0x0 }, // 4192 |
| 11483 | { PseudoVLOXSEG4EI64_V_M1_MF8, VLOXSEG4EI64_V, 0x5, 0x0 }, // 4193 |
| 11484 | { PseudoVLOXSEG4EI64_V_M1_MF8_MASK, VLOXSEG4EI64_V, 0x5, 0x0 }, // 4194 |
| 11485 | { PseudoVLOXSEG4EI64_V_M1_MF4, VLOXSEG4EI64_V, 0x6, 0x0 }, // 4195 |
| 11486 | { PseudoVLOXSEG4EI64_V_M1_MF4_MASK, VLOXSEG4EI64_V, 0x6, 0x0 }, // 4196 |
| 11487 | { PseudoVLOXSEG4EI64_V_M2_MF4, VLOXSEG4EI64_V, 0x6, 0x0 }, // 4197 |
| 11488 | { PseudoVLOXSEG4EI64_V_M2_MF4_MASK, VLOXSEG4EI64_V, 0x6, 0x0 }, // 4198 |
| 11489 | { PseudoVLOXSEG4EI64_V_M1_MF2, VLOXSEG4EI64_V, 0x7, 0x0 }, // 4199 |
| 11490 | { PseudoVLOXSEG4EI64_V_M1_MF2_MASK, VLOXSEG4EI64_V, 0x7, 0x0 }, // 4200 |
| 11491 | { PseudoVLOXSEG4EI64_V_M2_MF2, VLOXSEG4EI64_V, 0x7, 0x0 }, // 4201 |
| 11492 | { PseudoVLOXSEG4EI64_V_M2_MF2_MASK, VLOXSEG4EI64_V, 0x7, 0x0 }, // 4202 |
| 11493 | { PseudoVLOXSEG4EI64_V_M4_MF2, VLOXSEG4EI64_V, 0x7, 0x0 }, // 4203 |
| 11494 | { PseudoVLOXSEG4EI64_V_M4_MF2_MASK, VLOXSEG4EI64_V, 0x7, 0x0 }, // 4204 |
| 11495 | { PseudoVLOXSEG4EI8_V_M1_M1, VLOXSEG4EI8_V, 0x0, 0x0 }, // 4205 |
| 11496 | { PseudoVLOXSEG4EI8_V_M1_M1_MASK, VLOXSEG4EI8_V, 0x0, 0x0 }, // 4206 |
| 11497 | { PseudoVLOXSEG4EI8_V_MF2_M1, VLOXSEG4EI8_V, 0x0, 0x0 }, // 4207 |
| 11498 | { PseudoVLOXSEG4EI8_V_MF2_M1_MASK, VLOXSEG4EI8_V, 0x0, 0x0 }, // 4208 |
| 11499 | { PseudoVLOXSEG4EI8_V_MF4_M1, VLOXSEG4EI8_V, 0x0, 0x0 }, // 4209 |
| 11500 | { PseudoVLOXSEG4EI8_V_MF4_M1_MASK, VLOXSEG4EI8_V, 0x0, 0x0 }, // 4210 |
| 11501 | { PseudoVLOXSEG4EI8_V_MF8_M1, VLOXSEG4EI8_V, 0x0, 0x0 }, // 4211 |
| 11502 | { PseudoVLOXSEG4EI8_V_MF8_M1_MASK, VLOXSEG4EI8_V, 0x0, 0x0 }, // 4212 |
| 11503 | { PseudoVLOXSEG4EI8_V_M1_M2, VLOXSEG4EI8_V, 0x1, 0x0 }, // 4213 |
| 11504 | { PseudoVLOXSEG4EI8_V_M1_M2_MASK, VLOXSEG4EI8_V, 0x1, 0x0 }, // 4214 |
| 11505 | { PseudoVLOXSEG4EI8_V_M2_M2, VLOXSEG4EI8_V, 0x1, 0x0 }, // 4215 |
| 11506 | { PseudoVLOXSEG4EI8_V_M2_M2_MASK, VLOXSEG4EI8_V, 0x1, 0x0 }, // 4216 |
| 11507 | { PseudoVLOXSEG4EI8_V_MF2_M2, VLOXSEG4EI8_V, 0x1, 0x0 }, // 4217 |
| 11508 | { PseudoVLOXSEG4EI8_V_MF2_M2_MASK, VLOXSEG4EI8_V, 0x1, 0x0 }, // 4218 |
| 11509 | { PseudoVLOXSEG4EI8_V_MF4_M2, VLOXSEG4EI8_V, 0x1, 0x0 }, // 4219 |
| 11510 | { PseudoVLOXSEG4EI8_V_MF4_M2_MASK, VLOXSEG4EI8_V, 0x1, 0x0 }, // 4220 |
| 11511 | { PseudoVLOXSEG4EI8_V_MF8_MF8, VLOXSEG4EI8_V, 0x5, 0x0 }, // 4221 |
| 11512 | { PseudoVLOXSEG4EI8_V_MF8_MF8_MASK, VLOXSEG4EI8_V, 0x5, 0x0 }, // 4222 |
| 11513 | { PseudoVLOXSEG4EI8_V_MF4_MF4, VLOXSEG4EI8_V, 0x6, 0x0 }, // 4223 |
| 11514 | { PseudoVLOXSEG4EI8_V_MF4_MF4_MASK, VLOXSEG4EI8_V, 0x6, 0x0 }, // 4224 |
| 11515 | { PseudoVLOXSEG4EI8_V_MF8_MF4, VLOXSEG4EI8_V, 0x6, 0x0 }, // 4225 |
| 11516 | { PseudoVLOXSEG4EI8_V_MF8_MF4_MASK, VLOXSEG4EI8_V, 0x6, 0x0 }, // 4226 |
| 11517 | { PseudoVLOXSEG4EI8_V_MF2_MF2, VLOXSEG4EI8_V, 0x7, 0x0 }, // 4227 |
| 11518 | { PseudoVLOXSEG4EI8_V_MF2_MF2_MASK, VLOXSEG4EI8_V, 0x7, 0x0 }, // 4228 |
| 11519 | { PseudoVLOXSEG4EI8_V_MF4_MF2, VLOXSEG4EI8_V, 0x7, 0x0 }, // 4229 |
| 11520 | { PseudoVLOXSEG4EI8_V_MF4_MF2_MASK, VLOXSEG4EI8_V, 0x7, 0x0 }, // 4230 |
| 11521 | { PseudoVLOXSEG4EI8_V_MF8_MF2, VLOXSEG4EI8_V, 0x7, 0x0 }, // 4231 |
| 11522 | { PseudoVLOXSEG4EI8_V_MF8_MF2_MASK, VLOXSEG4EI8_V, 0x7, 0x0 }, // 4232 |
| 11523 | { PseudoVLOXSEG5EI16_V_M1_M1, VLOXSEG5EI16_V, 0x0, 0x0 }, // 4233 |
| 11524 | { PseudoVLOXSEG5EI16_V_M1_M1_MASK, VLOXSEG5EI16_V, 0x0, 0x0 }, // 4234 |
| 11525 | { PseudoVLOXSEG5EI16_V_M2_M1, VLOXSEG5EI16_V, 0x0, 0x0 }, // 4235 |
| 11526 | { PseudoVLOXSEG5EI16_V_M2_M1_MASK, VLOXSEG5EI16_V, 0x0, 0x0 }, // 4236 |
| 11527 | { PseudoVLOXSEG5EI16_V_MF2_M1, VLOXSEG5EI16_V, 0x0, 0x0 }, // 4237 |
| 11528 | { PseudoVLOXSEG5EI16_V_MF2_M1_MASK, VLOXSEG5EI16_V, 0x0, 0x0 }, // 4238 |
| 11529 | { PseudoVLOXSEG5EI16_V_MF4_M1, VLOXSEG5EI16_V, 0x0, 0x0 }, // 4239 |
| 11530 | { PseudoVLOXSEG5EI16_V_MF4_M1_MASK, VLOXSEG5EI16_V, 0x0, 0x0 }, // 4240 |
| 11531 | { PseudoVLOXSEG5EI16_V_MF4_MF8, VLOXSEG5EI16_V, 0x5, 0x0 }, // 4241 |
| 11532 | { PseudoVLOXSEG5EI16_V_MF4_MF8_MASK, VLOXSEG5EI16_V, 0x5, 0x0 }, // 4242 |
| 11533 | { PseudoVLOXSEG5EI16_V_MF2_MF4, VLOXSEG5EI16_V, 0x6, 0x0 }, // 4243 |
| 11534 | { PseudoVLOXSEG5EI16_V_MF2_MF4_MASK, VLOXSEG5EI16_V, 0x6, 0x0 }, // 4244 |
| 11535 | { PseudoVLOXSEG5EI16_V_MF4_MF4, VLOXSEG5EI16_V, 0x6, 0x0 }, // 4245 |
| 11536 | { PseudoVLOXSEG5EI16_V_MF4_MF4_MASK, VLOXSEG5EI16_V, 0x6, 0x0 }, // 4246 |
| 11537 | { PseudoVLOXSEG5EI16_V_M1_MF2, VLOXSEG5EI16_V, 0x7, 0x0 }, // 4247 |
| 11538 | { PseudoVLOXSEG5EI16_V_M1_MF2_MASK, VLOXSEG5EI16_V, 0x7, 0x0 }, // 4248 |
| 11539 | { PseudoVLOXSEG5EI16_V_MF2_MF2, VLOXSEG5EI16_V, 0x7, 0x0 }, // 4249 |
| 11540 | { PseudoVLOXSEG5EI16_V_MF2_MF2_MASK, VLOXSEG5EI16_V, 0x7, 0x0 }, // 4250 |
| 11541 | { PseudoVLOXSEG5EI16_V_MF4_MF2, VLOXSEG5EI16_V, 0x7, 0x0 }, // 4251 |
| 11542 | { PseudoVLOXSEG5EI16_V_MF4_MF2_MASK, VLOXSEG5EI16_V, 0x7, 0x0 }, // 4252 |
| 11543 | { PseudoVLOXSEG5EI32_V_M1_M1, VLOXSEG5EI32_V, 0x0, 0x0 }, // 4253 |
| 11544 | { PseudoVLOXSEG5EI32_V_M1_M1_MASK, VLOXSEG5EI32_V, 0x0, 0x0 }, // 4254 |
| 11545 | { PseudoVLOXSEG5EI32_V_M2_M1, VLOXSEG5EI32_V, 0x0, 0x0 }, // 4255 |
| 11546 | { PseudoVLOXSEG5EI32_V_M2_M1_MASK, VLOXSEG5EI32_V, 0x0, 0x0 }, // 4256 |
| 11547 | { PseudoVLOXSEG5EI32_V_M4_M1, VLOXSEG5EI32_V, 0x0, 0x0 }, // 4257 |
| 11548 | { PseudoVLOXSEG5EI32_V_M4_M1_MASK, VLOXSEG5EI32_V, 0x0, 0x0 }, // 4258 |
| 11549 | { PseudoVLOXSEG5EI32_V_MF2_M1, VLOXSEG5EI32_V, 0x0, 0x0 }, // 4259 |
| 11550 | { PseudoVLOXSEG5EI32_V_MF2_M1_MASK, VLOXSEG5EI32_V, 0x0, 0x0 }, // 4260 |
| 11551 | { PseudoVLOXSEG5EI32_V_MF2_MF8, VLOXSEG5EI32_V, 0x5, 0x0 }, // 4261 |
| 11552 | { PseudoVLOXSEG5EI32_V_MF2_MF8_MASK, VLOXSEG5EI32_V, 0x5, 0x0 }, // 4262 |
| 11553 | { PseudoVLOXSEG5EI32_V_M1_MF4, VLOXSEG5EI32_V, 0x6, 0x0 }, // 4263 |
| 11554 | { PseudoVLOXSEG5EI32_V_M1_MF4_MASK, VLOXSEG5EI32_V, 0x6, 0x0 }, // 4264 |
| 11555 | { PseudoVLOXSEG5EI32_V_MF2_MF4, VLOXSEG5EI32_V, 0x6, 0x0 }, // 4265 |
| 11556 | { PseudoVLOXSEG5EI32_V_MF2_MF4_MASK, VLOXSEG5EI32_V, 0x6, 0x0 }, // 4266 |
| 11557 | { PseudoVLOXSEG5EI32_V_M1_MF2, VLOXSEG5EI32_V, 0x7, 0x0 }, // 4267 |
| 11558 | { PseudoVLOXSEG5EI32_V_M1_MF2_MASK, VLOXSEG5EI32_V, 0x7, 0x0 }, // 4268 |
| 11559 | { PseudoVLOXSEG5EI32_V_M2_MF2, VLOXSEG5EI32_V, 0x7, 0x0 }, // 4269 |
| 11560 | { PseudoVLOXSEG5EI32_V_M2_MF2_MASK, VLOXSEG5EI32_V, 0x7, 0x0 }, // 4270 |
| 11561 | { PseudoVLOXSEG5EI32_V_MF2_MF2, VLOXSEG5EI32_V, 0x7, 0x0 }, // 4271 |
| 11562 | { PseudoVLOXSEG5EI32_V_MF2_MF2_MASK, VLOXSEG5EI32_V, 0x7, 0x0 }, // 4272 |
| 11563 | { PseudoVLOXSEG5EI64_V_M1_M1, VLOXSEG5EI64_V, 0x0, 0x0 }, // 4273 |
| 11564 | { PseudoVLOXSEG5EI64_V_M1_M1_MASK, VLOXSEG5EI64_V, 0x0, 0x0 }, // 4274 |
| 11565 | { PseudoVLOXSEG5EI64_V_M2_M1, VLOXSEG5EI64_V, 0x0, 0x0 }, // 4275 |
| 11566 | { PseudoVLOXSEG5EI64_V_M2_M1_MASK, VLOXSEG5EI64_V, 0x0, 0x0 }, // 4276 |
| 11567 | { PseudoVLOXSEG5EI64_V_M4_M1, VLOXSEG5EI64_V, 0x0, 0x0 }, // 4277 |
| 11568 | { PseudoVLOXSEG5EI64_V_M4_M1_MASK, VLOXSEG5EI64_V, 0x0, 0x0 }, // 4278 |
| 11569 | { PseudoVLOXSEG5EI64_V_M8_M1, VLOXSEG5EI64_V, 0x0, 0x0 }, // 4279 |
| 11570 | { PseudoVLOXSEG5EI64_V_M8_M1_MASK, VLOXSEG5EI64_V, 0x0, 0x0 }, // 4280 |
| 11571 | { PseudoVLOXSEG5EI64_V_M1_MF8, VLOXSEG5EI64_V, 0x5, 0x0 }, // 4281 |
| 11572 | { PseudoVLOXSEG5EI64_V_M1_MF8_MASK, VLOXSEG5EI64_V, 0x5, 0x0 }, // 4282 |
| 11573 | { PseudoVLOXSEG5EI64_V_M1_MF4, VLOXSEG5EI64_V, 0x6, 0x0 }, // 4283 |
| 11574 | { PseudoVLOXSEG5EI64_V_M1_MF4_MASK, VLOXSEG5EI64_V, 0x6, 0x0 }, // 4284 |
| 11575 | { PseudoVLOXSEG5EI64_V_M2_MF4, VLOXSEG5EI64_V, 0x6, 0x0 }, // 4285 |
| 11576 | { PseudoVLOXSEG5EI64_V_M2_MF4_MASK, VLOXSEG5EI64_V, 0x6, 0x0 }, // 4286 |
| 11577 | { PseudoVLOXSEG5EI64_V_M1_MF2, VLOXSEG5EI64_V, 0x7, 0x0 }, // 4287 |
| 11578 | { PseudoVLOXSEG5EI64_V_M1_MF2_MASK, VLOXSEG5EI64_V, 0x7, 0x0 }, // 4288 |
| 11579 | { PseudoVLOXSEG5EI64_V_M2_MF2, VLOXSEG5EI64_V, 0x7, 0x0 }, // 4289 |
| 11580 | { PseudoVLOXSEG5EI64_V_M2_MF2_MASK, VLOXSEG5EI64_V, 0x7, 0x0 }, // 4290 |
| 11581 | { PseudoVLOXSEG5EI64_V_M4_MF2, VLOXSEG5EI64_V, 0x7, 0x0 }, // 4291 |
| 11582 | { PseudoVLOXSEG5EI64_V_M4_MF2_MASK, VLOXSEG5EI64_V, 0x7, 0x0 }, // 4292 |
| 11583 | { PseudoVLOXSEG5EI8_V_M1_M1, VLOXSEG5EI8_V, 0x0, 0x0 }, // 4293 |
| 11584 | { PseudoVLOXSEG5EI8_V_M1_M1_MASK, VLOXSEG5EI8_V, 0x0, 0x0 }, // 4294 |
| 11585 | { PseudoVLOXSEG5EI8_V_MF2_M1, VLOXSEG5EI8_V, 0x0, 0x0 }, // 4295 |
| 11586 | { PseudoVLOXSEG5EI8_V_MF2_M1_MASK, VLOXSEG5EI8_V, 0x0, 0x0 }, // 4296 |
| 11587 | { PseudoVLOXSEG5EI8_V_MF4_M1, VLOXSEG5EI8_V, 0x0, 0x0 }, // 4297 |
| 11588 | { PseudoVLOXSEG5EI8_V_MF4_M1_MASK, VLOXSEG5EI8_V, 0x0, 0x0 }, // 4298 |
| 11589 | { PseudoVLOXSEG5EI8_V_MF8_M1, VLOXSEG5EI8_V, 0x0, 0x0 }, // 4299 |
| 11590 | { PseudoVLOXSEG5EI8_V_MF8_M1_MASK, VLOXSEG5EI8_V, 0x0, 0x0 }, // 4300 |
| 11591 | { PseudoVLOXSEG5EI8_V_MF8_MF8, VLOXSEG5EI8_V, 0x5, 0x0 }, // 4301 |
| 11592 | { PseudoVLOXSEG5EI8_V_MF8_MF8_MASK, VLOXSEG5EI8_V, 0x5, 0x0 }, // 4302 |
| 11593 | { PseudoVLOXSEG5EI8_V_MF4_MF4, VLOXSEG5EI8_V, 0x6, 0x0 }, // 4303 |
| 11594 | { PseudoVLOXSEG5EI8_V_MF4_MF4_MASK, VLOXSEG5EI8_V, 0x6, 0x0 }, // 4304 |
| 11595 | { PseudoVLOXSEG5EI8_V_MF8_MF4, VLOXSEG5EI8_V, 0x6, 0x0 }, // 4305 |
| 11596 | { PseudoVLOXSEG5EI8_V_MF8_MF4_MASK, VLOXSEG5EI8_V, 0x6, 0x0 }, // 4306 |
| 11597 | { PseudoVLOXSEG5EI8_V_MF2_MF2, VLOXSEG5EI8_V, 0x7, 0x0 }, // 4307 |
| 11598 | { PseudoVLOXSEG5EI8_V_MF2_MF2_MASK, VLOXSEG5EI8_V, 0x7, 0x0 }, // 4308 |
| 11599 | { PseudoVLOXSEG5EI8_V_MF4_MF2, VLOXSEG5EI8_V, 0x7, 0x0 }, // 4309 |
| 11600 | { PseudoVLOXSEG5EI8_V_MF4_MF2_MASK, VLOXSEG5EI8_V, 0x7, 0x0 }, // 4310 |
| 11601 | { PseudoVLOXSEG5EI8_V_MF8_MF2, VLOXSEG5EI8_V, 0x7, 0x0 }, // 4311 |
| 11602 | { PseudoVLOXSEG5EI8_V_MF8_MF2_MASK, VLOXSEG5EI8_V, 0x7, 0x0 }, // 4312 |
| 11603 | { PseudoVLOXSEG6EI16_V_M1_M1, VLOXSEG6EI16_V, 0x0, 0x0 }, // 4313 |
| 11604 | { PseudoVLOXSEG6EI16_V_M1_M1_MASK, VLOXSEG6EI16_V, 0x0, 0x0 }, // 4314 |
| 11605 | { PseudoVLOXSEG6EI16_V_M2_M1, VLOXSEG6EI16_V, 0x0, 0x0 }, // 4315 |
| 11606 | { PseudoVLOXSEG6EI16_V_M2_M1_MASK, VLOXSEG6EI16_V, 0x0, 0x0 }, // 4316 |
| 11607 | { PseudoVLOXSEG6EI16_V_MF2_M1, VLOXSEG6EI16_V, 0x0, 0x0 }, // 4317 |
| 11608 | { PseudoVLOXSEG6EI16_V_MF2_M1_MASK, VLOXSEG6EI16_V, 0x0, 0x0 }, // 4318 |
| 11609 | { PseudoVLOXSEG6EI16_V_MF4_M1, VLOXSEG6EI16_V, 0x0, 0x0 }, // 4319 |
| 11610 | { PseudoVLOXSEG6EI16_V_MF4_M1_MASK, VLOXSEG6EI16_V, 0x0, 0x0 }, // 4320 |
| 11611 | { PseudoVLOXSEG6EI16_V_MF4_MF8, VLOXSEG6EI16_V, 0x5, 0x0 }, // 4321 |
| 11612 | { PseudoVLOXSEG6EI16_V_MF4_MF8_MASK, VLOXSEG6EI16_V, 0x5, 0x0 }, // 4322 |
| 11613 | { PseudoVLOXSEG6EI16_V_MF2_MF4, VLOXSEG6EI16_V, 0x6, 0x0 }, // 4323 |
| 11614 | { PseudoVLOXSEG6EI16_V_MF2_MF4_MASK, VLOXSEG6EI16_V, 0x6, 0x0 }, // 4324 |
| 11615 | { PseudoVLOXSEG6EI16_V_MF4_MF4, VLOXSEG6EI16_V, 0x6, 0x0 }, // 4325 |
| 11616 | { PseudoVLOXSEG6EI16_V_MF4_MF4_MASK, VLOXSEG6EI16_V, 0x6, 0x0 }, // 4326 |
| 11617 | { PseudoVLOXSEG6EI16_V_M1_MF2, VLOXSEG6EI16_V, 0x7, 0x0 }, // 4327 |
| 11618 | { PseudoVLOXSEG6EI16_V_M1_MF2_MASK, VLOXSEG6EI16_V, 0x7, 0x0 }, // 4328 |
| 11619 | { PseudoVLOXSEG6EI16_V_MF2_MF2, VLOXSEG6EI16_V, 0x7, 0x0 }, // 4329 |
| 11620 | { PseudoVLOXSEG6EI16_V_MF2_MF2_MASK, VLOXSEG6EI16_V, 0x7, 0x0 }, // 4330 |
| 11621 | { PseudoVLOXSEG6EI16_V_MF4_MF2, VLOXSEG6EI16_V, 0x7, 0x0 }, // 4331 |
| 11622 | { PseudoVLOXSEG6EI16_V_MF4_MF2_MASK, VLOXSEG6EI16_V, 0x7, 0x0 }, // 4332 |
| 11623 | { PseudoVLOXSEG6EI32_V_M1_M1, VLOXSEG6EI32_V, 0x0, 0x0 }, // 4333 |
| 11624 | { PseudoVLOXSEG6EI32_V_M1_M1_MASK, VLOXSEG6EI32_V, 0x0, 0x0 }, // 4334 |
| 11625 | { PseudoVLOXSEG6EI32_V_M2_M1, VLOXSEG6EI32_V, 0x0, 0x0 }, // 4335 |
| 11626 | { PseudoVLOXSEG6EI32_V_M2_M1_MASK, VLOXSEG6EI32_V, 0x0, 0x0 }, // 4336 |
| 11627 | { PseudoVLOXSEG6EI32_V_M4_M1, VLOXSEG6EI32_V, 0x0, 0x0 }, // 4337 |
| 11628 | { PseudoVLOXSEG6EI32_V_M4_M1_MASK, VLOXSEG6EI32_V, 0x0, 0x0 }, // 4338 |
| 11629 | { PseudoVLOXSEG6EI32_V_MF2_M1, VLOXSEG6EI32_V, 0x0, 0x0 }, // 4339 |
| 11630 | { PseudoVLOXSEG6EI32_V_MF2_M1_MASK, VLOXSEG6EI32_V, 0x0, 0x0 }, // 4340 |
| 11631 | { PseudoVLOXSEG6EI32_V_MF2_MF8, VLOXSEG6EI32_V, 0x5, 0x0 }, // 4341 |
| 11632 | { PseudoVLOXSEG6EI32_V_MF2_MF8_MASK, VLOXSEG6EI32_V, 0x5, 0x0 }, // 4342 |
| 11633 | { PseudoVLOXSEG6EI32_V_M1_MF4, VLOXSEG6EI32_V, 0x6, 0x0 }, // 4343 |
| 11634 | { PseudoVLOXSEG6EI32_V_M1_MF4_MASK, VLOXSEG6EI32_V, 0x6, 0x0 }, // 4344 |
| 11635 | { PseudoVLOXSEG6EI32_V_MF2_MF4, VLOXSEG6EI32_V, 0x6, 0x0 }, // 4345 |
| 11636 | { PseudoVLOXSEG6EI32_V_MF2_MF4_MASK, VLOXSEG6EI32_V, 0x6, 0x0 }, // 4346 |
| 11637 | { PseudoVLOXSEG6EI32_V_M1_MF2, VLOXSEG6EI32_V, 0x7, 0x0 }, // 4347 |
| 11638 | { PseudoVLOXSEG6EI32_V_M1_MF2_MASK, VLOXSEG6EI32_V, 0x7, 0x0 }, // 4348 |
| 11639 | { PseudoVLOXSEG6EI32_V_M2_MF2, VLOXSEG6EI32_V, 0x7, 0x0 }, // 4349 |
| 11640 | { PseudoVLOXSEG6EI32_V_M2_MF2_MASK, VLOXSEG6EI32_V, 0x7, 0x0 }, // 4350 |
| 11641 | { PseudoVLOXSEG6EI32_V_MF2_MF2, VLOXSEG6EI32_V, 0x7, 0x0 }, // 4351 |
| 11642 | { PseudoVLOXSEG6EI32_V_MF2_MF2_MASK, VLOXSEG6EI32_V, 0x7, 0x0 }, // 4352 |
| 11643 | { PseudoVLOXSEG6EI64_V_M1_M1, VLOXSEG6EI64_V, 0x0, 0x0 }, // 4353 |
| 11644 | { PseudoVLOXSEG6EI64_V_M1_M1_MASK, VLOXSEG6EI64_V, 0x0, 0x0 }, // 4354 |
| 11645 | { PseudoVLOXSEG6EI64_V_M2_M1, VLOXSEG6EI64_V, 0x0, 0x0 }, // 4355 |
| 11646 | { PseudoVLOXSEG6EI64_V_M2_M1_MASK, VLOXSEG6EI64_V, 0x0, 0x0 }, // 4356 |
| 11647 | { PseudoVLOXSEG6EI64_V_M4_M1, VLOXSEG6EI64_V, 0x0, 0x0 }, // 4357 |
| 11648 | { PseudoVLOXSEG6EI64_V_M4_M1_MASK, VLOXSEG6EI64_V, 0x0, 0x0 }, // 4358 |
| 11649 | { PseudoVLOXSEG6EI64_V_M8_M1, VLOXSEG6EI64_V, 0x0, 0x0 }, // 4359 |
| 11650 | { PseudoVLOXSEG6EI64_V_M8_M1_MASK, VLOXSEG6EI64_V, 0x0, 0x0 }, // 4360 |
| 11651 | { PseudoVLOXSEG6EI64_V_M1_MF8, VLOXSEG6EI64_V, 0x5, 0x0 }, // 4361 |
| 11652 | { PseudoVLOXSEG6EI64_V_M1_MF8_MASK, VLOXSEG6EI64_V, 0x5, 0x0 }, // 4362 |
| 11653 | { PseudoVLOXSEG6EI64_V_M1_MF4, VLOXSEG6EI64_V, 0x6, 0x0 }, // 4363 |
| 11654 | { PseudoVLOXSEG6EI64_V_M1_MF4_MASK, VLOXSEG6EI64_V, 0x6, 0x0 }, // 4364 |
| 11655 | { PseudoVLOXSEG6EI64_V_M2_MF4, VLOXSEG6EI64_V, 0x6, 0x0 }, // 4365 |
| 11656 | { PseudoVLOXSEG6EI64_V_M2_MF4_MASK, VLOXSEG6EI64_V, 0x6, 0x0 }, // 4366 |
| 11657 | { PseudoVLOXSEG6EI64_V_M1_MF2, VLOXSEG6EI64_V, 0x7, 0x0 }, // 4367 |
| 11658 | { PseudoVLOXSEG6EI64_V_M1_MF2_MASK, VLOXSEG6EI64_V, 0x7, 0x0 }, // 4368 |
| 11659 | { PseudoVLOXSEG6EI64_V_M2_MF2, VLOXSEG6EI64_V, 0x7, 0x0 }, // 4369 |
| 11660 | { PseudoVLOXSEG6EI64_V_M2_MF2_MASK, VLOXSEG6EI64_V, 0x7, 0x0 }, // 4370 |
| 11661 | { PseudoVLOXSEG6EI64_V_M4_MF2, VLOXSEG6EI64_V, 0x7, 0x0 }, // 4371 |
| 11662 | { PseudoVLOXSEG6EI64_V_M4_MF2_MASK, VLOXSEG6EI64_V, 0x7, 0x0 }, // 4372 |
| 11663 | { PseudoVLOXSEG6EI8_V_M1_M1, VLOXSEG6EI8_V, 0x0, 0x0 }, // 4373 |
| 11664 | { PseudoVLOXSEG6EI8_V_M1_M1_MASK, VLOXSEG6EI8_V, 0x0, 0x0 }, // 4374 |
| 11665 | { PseudoVLOXSEG6EI8_V_MF2_M1, VLOXSEG6EI8_V, 0x0, 0x0 }, // 4375 |
| 11666 | { PseudoVLOXSEG6EI8_V_MF2_M1_MASK, VLOXSEG6EI8_V, 0x0, 0x0 }, // 4376 |
| 11667 | { PseudoVLOXSEG6EI8_V_MF4_M1, VLOXSEG6EI8_V, 0x0, 0x0 }, // 4377 |
| 11668 | { PseudoVLOXSEG6EI8_V_MF4_M1_MASK, VLOXSEG6EI8_V, 0x0, 0x0 }, // 4378 |
| 11669 | { PseudoVLOXSEG6EI8_V_MF8_M1, VLOXSEG6EI8_V, 0x0, 0x0 }, // 4379 |
| 11670 | { PseudoVLOXSEG6EI8_V_MF8_M1_MASK, VLOXSEG6EI8_V, 0x0, 0x0 }, // 4380 |
| 11671 | { PseudoVLOXSEG6EI8_V_MF8_MF8, VLOXSEG6EI8_V, 0x5, 0x0 }, // 4381 |
| 11672 | { PseudoVLOXSEG6EI8_V_MF8_MF8_MASK, VLOXSEG6EI8_V, 0x5, 0x0 }, // 4382 |
| 11673 | { PseudoVLOXSEG6EI8_V_MF4_MF4, VLOXSEG6EI8_V, 0x6, 0x0 }, // 4383 |
| 11674 | { PseudoVLOXSEG6EI8_V_MF4_MF4_MASK, VLOXSEG6EI8_V, 0x6, 0x0 }, // 4384 |
| 11675 | { PseudoVLOXSEG6EI8_V_MF8_MF4, VLOXSEG6EI8_V, 0x6, 0x0 }, // 4385 |
| 11676 | { PseudoVLOXSEG6EI8_V_MF8_MF4_MASK, VLOXSEG6EI8_V, 0x6, 0x0 }, // 4386 |
| 11677 | { PseudoVLOXSEG6EI8_V_MF2_MF2, VLOXSEG6EI8_V, 0x7, 0x0 }, // 4387 |
| 11678 | { PseudoVLOXSEG6EI8_V_MF2_MF2_MASK, VLOXSEG6EI8_V, 0x7, 0x0 }, // 4388 |
| 11679 | { PseudoVLOXSEG6EI8_V_MF4_MF2, VLOXSEG6EI8_V, 0x7, 0x0 }, // 4389 |
| 11680 | { PseudoVLOXSEG6EI8_V_MF4_MF2_MASK, VLOXSEG6EI8_V, 0x7, 0x0 }, // 4390 |
| 11681 | { PseudoVLOXSEG6EI8_V_MF8_MF2, VLOXSEG6EI8_V, 0x7, 0x0 }, // 4391 |
| 11682 | { PseudoVLOXSEG6EI8_V_MF8_MF2_MASK, VLOXSEG6EI8_V, 0x7, 0x0 }, // 4392 |
| 11683 | { PseudoVLOXSEG7EI16_V_M1_M1, VLOXSEG7EI16_V, 0x0, 0x0 }, // 4393 |
| 11684 | { PseudoVLOXSEG7EI16_V_M1_M1_MASK, VLOXSEG7EI16_V, 0x0, 0x0 }, // 4394 |
| 11685 | { PseudoVLOXSEG7EI16_V_M2_M1, VLOXSEG7EI16_V, 0x0, 0x0 }, // 4395 |
| 11686 | { PseudoVLOXSEG7EI16_V_M2_M1_MASK, VLOXSEG7EI16_V, 0x0, 0x0 }, // 4396 |
| 11687 | { PseudoVLOXSEG7EI16_V_MF2_M1, VLOXSEG7EI16_V, 0x0, 0x0 }, // 4397 |
| 11688 | { PseudoVLOXSEG7EI16_V_MF2_M1_MASK, VLOXSEG7EI16_V, 0x0, 0x0 }, // 4398 |
| 11689 | { PseudoVLOXSEG7EI16_V_MF4_M1, VLOXSEG7EI16_V, 0x0, 0x0 }, // 4399 |
| 11690 | { PseudoVLOXSEG7EI16_V_MF4_M1_MASK, VLOXSEG7EI16_V, 0x0, 0x0 }, // 4400 |
| 11691 | { PseudoVLOXSEG7EI16_V_MF4_MF8, VLOXSEG7EI16_V, 0x5, 0x0 }, // 4401 |
| 11692 | { PseudoVLOXSEG7EI16_V_MF4_MF8_MASK, VLOXSEG7EI16_V, 0x5, 0x0 }, // 4402 |
| 11693 | { PseudoVLOXSEG7EI16_V_MF2_MF4, VLOXSEG7EI16_V, 0x6, 0x0 }, // 4403 |
| 11694 | { PseudoVLOXSEG7EI16_V_MF2_MF4_MASK, VLOXSEG7EI16_V, 0x6, 0x0 }, // 4404 |
| 11695 | { PseudoVLOXSEG7EI16_V_MF4_MF4, VLOXSEG7EI16_V, 0x6, 0x0 }, // 4405 |
| 11696 | { PseudoVLOXSEG7EI16_V_MF4_MF4_MASK, VLOXSEG7EI16_V, 0x6, 0x0 }, // 4406 |
| 11697 | { PseudoVLOXSEG7EI16_V_M1_MF2, VLOXSEG7EI16_V, 0x7, 0x0 }, // 4407 |
| 11698 | { PseudoVLOXSEG7EI16_V_M1_MF2_MASK, VLOXSEG7EI16_V, 0x7, 0x0 }, // 4408 |
| 11699 | { PseudoVLOXSEG7EI16_V_MF2_MF2, VLOXSEG7EI16_V, 0x7, 0x0 }, // 4409 |
| 11700 | { PseudoVLOXSEG7EI16_V_MF2_MF2_MASK, VLOXSEG7EI16_V, 0x7, 0x0 }, // 4410 |
| 11701 | { PseudoVLOXSEG7EI16_V_MF4_MF2, VLOXSEG7EI16_V, 0x7, 0x0 }, // 4411 |
| 11702 | { PseudoVLOXSEG7EI16_V_MF4_MF2_MASK, VLOXSEG7EI16_V, 0x7, 0x0 }, // 4412 |
| 11703 | { PseudoVLOXSEG7EI32_V_M1_M1, VLOXSEG7EI32_V, 0x0, 0x0 }, // 4413 |
| 11704 | { PseudoVLOXSEG7EI32_V_M1_M1_MASK, VLOXSEG7EI32_V, 0x0, 0x0 }, // 4414 |
| 11705 | { PseudoVLOXSEG7EI32_V_M2_M1, VLOXSEG7EI32_V, 0x0, 0x0 }, // 4415 |
| 11706 | { PseudoVLOXSEG7EI32_V_M2_M1_MASK, VLOXSEG7EI32_V, 0x0, 0x0 }, // 4416 |
| 11707 | { PseudoVLOXSEG7EI32_V_M4_M1, VLOXSEG7EI32_V, 0x0, 0x0 }, // 4417 |
| 11708 | { PseudoVLOXSEG7EI32_V_M4_M1_MASK, VLOXSEG7EI32_V, 0x0, 0x0 }, // 4418 |
| 11709 | { PseudoVLOXSEG7EI32_V_MF2_M1, VLOXSEG7EI32_V, 0x0, 0x0 }, // 4419 |
| 11710 | { PseudoVLOXSEG7EI32_V_MF2_M1_MASK, VLOXSEG7EI32_V, 0x0, 0x0 }, // 4420 |
| 11711 | { PseudoVLOXSEG7EI32_V_MF2_MF8, VLOXSEG7EI32_V, 0x5, 0x0 }, // 4421 |
| 11712 | { PseudoVLOXSEG7EI32_V_MF2_MF8_MASK, VLOXSEG7EI32_V, 0x5, 0x0 }, // 4422 |
| 11713 | { PseudoVLOXSEG7EI32_V_M1_MF4, VLOXSEG7EI32_V, 0x6, 0x0 }, // 4423 |
| 11714 | { PseudoVLOXSEG7EI32_V_M1_MF4_MASK, VLOXSEG7EI32_V, 0x6, 0x0 }, // 4424 |
| 11715 | { PseudoVLOXSEG7EI32_V_MF2_MF4, VLOXSEG7EI32_V, 0x6, 0x0 }, // 4425 |
| 11716 | { PseudoVLOXSEG7EI32_V_MF2_MF4_MASK, VLOXSEG7EI32_V, 0x6, 0x0 }, // 4426 |
| 11717 | { PseudoVLOXSEG7EI32_V_M1_MF2, VLOXSEG7EI32_V, 0x7, 0x0 }, // 4427 |
| 11718 | { PseudoVLOXSEG7EI32_V_M1_MF2_MASK, VLOXSEG7EI32_V, 0x7, 0x0 }, // 4428 |
| 11719 | { PseudoVLOXSEG7EI32_V_M2_MF2, VLOXSEG7EI32_V, 0x7, 0x0 }, // 4429 |
| 11720 | { PseudoVLOXSEG7EI32_V_M2_MF2_MASK, VLOXSEG7EI32_V, 0x7, 0x0 }, // 4430 |
| 11721 | { PseudoVLOXSEG7EI32_V_MF2_MF2, VLOXSEG7EI32_V, 0x7, 0x0 }, // 4431 |
| 11722 | { PseudoVLOXSEG7EI32_V_MF2_MF2_MASK, VLOXSEG7EI32_V, 0x7, 0x0 }, // 4432 |
| 11723 | { PseudoVLOXSEG7EI64_V_M1_M1, VLOXSEG7EI64_V, 0x0, 0x0 }, // 4433 |
| 11724 | { PseudoVLOXSEG7EI64_V_M1_M1_MASK, VLOXSEG7EI64_V, 0x0, 0x0 }, // 4434 |
| 11725 | { PseudoVLOXSEG7EI64_V_M2_M1, VLOXSEG7EI64_V, 0x0, 0x0 }, // 4435 |
| 11726 | { PseudoVLOXSEG7EI64_V_M2_M1_MASK, VLOXSEG7EI64_V, 0x0, 0x0 }, // 4436 |
| 11727 | { PseudoVLOXSEG7EI64_V_M4_M1, VLOXSEG7EI64_V, 0x0, 0x0 }, // 4437 |
| 11728 | { PseudoVLOXSEG7EI64_V_M4_M1_MASK, VLOXSEG7EI64_V, 0x0, 0x0 }, // 4438 |
| 11729 | { PseudoVLOXSEG7EI64_V_M8_M1, VLOXSEG7EI64_V, 0x0, 0x0 }, // 4439 |
| 11730 | { PseudoVLOXSEG7EI64_V_M8_M1_MASK, VLOXSEG7EI64_V, 0x0, 0x0 }, // 4440 |
| 11731 | { PseudoVLOXSEG7EI64_V_M1_MF8, VLOXSEG7EI64_V, 0x5, 0x0 }, // 4441 |
| 11732 | { PseudoVLOXSEG7EI64_V_M1_MF8_MASK, VLOXSEG7EI64_V, 0x5, 0x0 }, // 4442 |
| 11733 | { PseudoVLOXSEG7EI64_V_M1_MF4, VLOXSEG7EI64_V, 0x6, 0x0 }, // 4443 |
| 11734 | { PseudoVLOXSEG7EI64_V_M1_MF4_MASK, VLOXSEG7EI64_V, 0x6, 0x0 }, // 4444 |
| 11735 | { PseudoVLOXSEG7EI64_V_M2_MF4, VLOXSEG7EI64_V, 0x6, 0x0 }, // 4445 |
| 11736 | { PseudoVLOXSEG7EI64_V_M2_MF4_MASK, VLOXSEG7EI64_V, 0x6, 0x0 }, // 4446 |
| 11737 | { PseudoVLOXSEG7EI64_V_M1_MF2, VLOXSEG7EI64_V, 0x7, 0x0 }, // 4447 |
| 11738 | { PseudoVLOXSEG7EI64_V_M1_MF2_MASK, VLOXSEG7EI64_V, 0x7, 0x0 }, // 4448 |
| 11739 | { PseudoVLOXSEG7EI64_V_M2_MF2, VLOXSEG7EI64_V, 0x7, 0x0 }, // 4449 |
| 11740 | { PseudoVLOXSEG7EI64_V_M2_MF2_MASK, VLOXSEG7EI64_V, 0x7, 0x0 }, // 4450 |
| 11741 | { PseudoVLOXSEG7EI64_V_M4_MF2, VLOXSEG7EI64_V, 0x7, 0x0 }, // 4451 |
| 11742 | { PseudoVLOXSEG7EI64_V_M4_MF2_MASK, VLOXSEG7EI64_V, 0x7, 0x0 }, // 4452 |
| 11743 | { PseudoVLOXSEG7EI8_V_M1_M1, VLOXSEG7EI8_V, 0x0, 0x0 }, // 4453 |
| 11744 | { PseudoVLOXSEG7EI8_V_M1_M1_MASK, VLOXSEG7EI8_V, 0x0, 0x0 }, // 4454 |
| 11745 | { PseudoVLOXSEG7EI8_V_MF2_M1, VLOXSEG7EI8_V, 0x0, 0x0 }, // 4455 |
| 11746 | { PseudoVLOXSEG7EI8_V_MF2_M1_MASK, VLOXSEG7EI8_V, 0x0, 0x0 }, // 4456 |
| 11747 | { PseudoVLOXSEG7EI8_V_MF4_M1, VLOXSEG7EI8_V, 0x0, 0x0 }, // 4457 |
| 11748 | { PseudoVLOXSEG7EI8_V_MF4_M1_MASK, VLOXSEG7EI8_V, 0x0, 0x0 }, // 4458 |
| 11749 | { PseudoVLOXSEG7EI8_V_MF8_M1, VLOXSEG7EI8_V, 0x0, 0x0 }, // 4459 |
| 11750 | { PseudoVLOXSEG7EI8_V_MF8_M1_MASK, VLOXSEG7EI8_V, 0x0, 0x0 }, // 4460 |
| 11751 | { PseudoVLOXSEG7EI8_V_MF8_MF8, VLOXSEG7EI8_V, 0x5, 0x0 }, // 4461 |
| 11752 | { PseudoVLOXSEG7EI8_V_MF8_MF8_MASK, VLOXSEG7EI8_V, 0x5, 0x0 }, // 4462 |
| 11753 | { PseudoVLOXSEG7EI8_V_MF4_MF4, VLOXSEG7EI8_V, 0x6, 0x0 }, // 4463 |
| 11754 | { PseudoVLOXSEG7EI8_V_MF4_MF4_MASK, VLOXSEG7EI8_V, 0x6, 0x0 }, // 4464 |
| 11755 | { PseudoVLOXSEG7EI8_V_MF8_MF4, VLOXSEG7EI8_V, 0x6, 0x0 }, // 4465 |
| 11756 | { PseudoVLOXSEG7EI8_V_MF8_MF4_MASK, VLOXSEG7EI8_V, 0x6, 0x0 }, // 4466 |
| 11757 | { PseudoVLOXSEG7EI8_V_MF2_MF2, VLOXSEG7EI8_V, 0x7, 0x0 }, // 4467 |
| 11758 | { PseudoVLOXSEG7EI8_V_MF2_MF2_MASK, VLOXSEG7EI8_V, 0x7, 0x0 }, // 4468 |
| 11759 | { PseudoVLOXSEG7EI8_V_MF4_MF2, VLOXSEG7EI8_V, 0x7, 0x0 }, // 4469 |
| 11760 | { PseudoVLOXSEG7EI8_V_MF4_MF2_MASK, VLOXSEG7EI8_V, 0x7, 0x0 }, // 4470 |
| 11761 | { PseudoVLOXSEG7EI8_V_MF8_MF2, VLOXSEG7EI8_V, 0x7, 0x0 }, // 4471 |
| 11762 | { PseudoVLOXSEG7EI8_V_MF8_MF2_MASK, VLOXSEG7EI8_V, 0x7, 0x0 }, // 4472 |
| 11763 | { PseudoVLOXSEG8EI16_V_M1_M1, VLOXSEG8EI16_V, 0x0, 0x0 }, // 4473 |
| 11764 | { PseudoVLOXSEG8EI16_V_M1_M1_MASK, VLOXSEG8EI16_V, 0x0, 0x0 }, // 4474 |
| 11765 | { PseudoVLOXSEG8EI16_V_M2_M1, VLOXSEG8EI16_V, 0x0, 0x0 }, // 4475 |
| 11766 | { PseudoVLOXSEG8EI16_V_M2_M1_MASK, VLOXSEG8EI16_V, 0x0, 0x0 }, // 4476 |
| 11767 | { PseudoVLOXSEG8EI16_V_MF2_M1, VLOXSEG8EI16_V, 0x0, 0x0 }, // 4477 |
| 11768 | { PseudoVLOXSEG8EI16_V_MF2_M1_MASK, VLOXSEG8EI16_V, 0x0, 0x0 }, // 4478 |
| 11769 | { PseudoVLOXSEG8EI16_V_MF4_M1, VLOXSEG8EI16_V, 0x0, 0x0 }, // 4479 |
| 11770 | { PseudoVLOXSEG8EI16_V_MF4_M1_MASK, VLOXSEG8EI16_V, 0x0, 0x0 }, // 4480 |
| 11771 | { PseudoVLOXSEG8EI16_V_MF4_MF8, VLOXSEG8EI16_V, 0x5, 0x0 }, // 4481 |
| 11772 | { PseudoVLOXSEG8EI16_V_MF4_MF8_MASK, VLOXSEG8EI16_V, 0x5, 0x0 }, // 4482 |
| 11773 | { PseudoVLOXSEG8EI16_V_MF2_MF4, VLOXSEG8EI16_V, 0x6, 0x0 }, // 4483 |
| 11774 | { PseudoVLOXSEG8EI16_V_MF2_MF4_MASK, VLOXSEG8EI16_V, 0x6, 0x0 }, // 4484 |
| 11775 | { PseudoVLOXSEG8EI16_V_MF4_MF4, VLOXSEG8EI16_V, 0x6, 0x0 }, // 4485 |
| 11776 | { PseudoVLOXSEG8EI16_V_MF4_MF4_MASK, VLOXSEG8EI16_V, 0x6, 0x0 }, // 4486 |
| 11777 | { PseudoVLOXSEG8EI16_V_M1_MF2, VLOXSEG8EI16_V, 0x7, 0x0 }, // 4487 |
| 11778 | { PseudoVLOXSEG8EI16_V_M1_MF2_MASK, VLOXSEG8EI16_V, 0x7, 0x0 }, // 4488 |
| 11779 | { PseudoVLOXSEG8EI16_V_MF2_MF2, VLOXSEG8EI16_V, 0x7, 0x0 }, // 4489 |
| 11780 | { PseudoVLOXSEG8EI16_V_MF2_MF2_MASK, VLOXSEG8EI16_V, 0x7, 0x0 }, // 4490 |
| 11781 | { PseudoVLOXSEG8EI16_V_MF4_MF2, VLOXSEG8EI16_V, 0x7, 0x0 }, // 4491 |
| 11782 | { PseudoVLOXSEG8EI16_V_MF4_MF2_MASK, VLOXSEG8EI16_V, 0x7, 0x0 }, // 4492 |
| 11783 | { PseudoVLOXSEG8EI32_V_M1_M1, VLOXSEG8EI32_V, 0x0, 0x0 }, // 4493 |
| 11784 | { PseudoVLOXSEG8EI32_V_M1_M1_MASK, VLOXSEG8EI32_V, 0x0, 0x0 }, // 4494 |
| 11785 | { PseudoVLOXSEG8EI32_V_M2_M1, VLOXSEG8EI32_V, 0x0, 0x0 }, // 4495 |
| 11786 | { PseudoVLOXSEG8EI32_V_M2_M1_MASK, VLOXSEG8EI32_V, 0x0, 0x0 }, // 4496 |
| 11787 | { PseudoVLOXSEG8EI32_V_M4_M1, VLOXSEG8EI32_V, 0x0, 0x0 }, // 4497 |
| 11788 | { PseudoVLOXSEG8EI32_V_M4_M1_MASK, VLOXSEG8EI32_V, 0x0, 0x0 }, // 4498 |
| 11789 | { PseudoVLOXSEG8EI32_V_MF2_M1, VLOXSEG8EI32_V, 0x0, 0x0 }, // 4499 |
| 11790 | { PseudoVLOXSEG8EI32_V_MF2_M1_MASK, VLOXSEG8EI32_V, 0x0, 0x0 }, // 4500 |
| 11791 | { PseudoVLOXSEG8EI32_V_MF2_MF8, VLOXSEG8EI32_V, 0x5, 0x0 }, // 4501 |
| 11792 | { PseudoVLOXSEG8EI32_V_MF2_MF8_MASK, VLOXSEG8EI32_V, 0x5, 0x0 }, // 4502 |
| 11793 | { PseudoVLOXSEG8EI32_V_M1_MF4, VLOXSEG8EI32_V, 0x6, 0x0 }, // 4503 |
| 11794 | { PseudoVLOXSEG8EI32_V_M1_MF4_MASK, VLOXSEG8EI32_V, 0x6, 0x0 }, // 4504 |
| 11795 | { PseudoVLOXSEG8EI32_V_MF2_MF4, VLOXSEG8EI32_V, 0x6, 0x0 }, // 4505 |
| 11796 | { PseudoVLOXSEG8EI32_V_MF2_MF4_MASK, VLOXSEG8EI32_V, 0x6, 0x0 }, // 4506 |
| 11797 | { PseudoVLOXSEG8EI32_V_M1_MF2, VLOXSEG8EI32_V, 0x7, 0x0 }, // 4507 |
| 11798 | { PseudoVLOXSEG8EI32_V_M1_MF2_MASK, VLOXSEG8EI32_V, 0x7, 0x0 }, // 4508 |
| 11799 | { PseudoVLOXSEG8EI32_V_M2_MF2, VLOXSEG8EI32_V, 0x7, 0x0 }, // 4509 |
| 11800 | { PseudoVLOXSEG8EI32_V_M2_MF2_MASK, VLOXSEG8EI32_V, 0x7, 0x0 }, // 4510 |
| 11801 | { PseudoVLOXSEG8EI32_V_MF2_MF2, VLOXSEG8EI32_V, 0x7, 0x0 }, // 4511 |
| 11802 | { PseudoVLOXSEG8EI32_V_MF2_MF2_MASK, VLOXSEG8EI32_V, 0x7, 0x0 }, // 4512 |
| 11803 | { PseudoVLOXSEG8EI64_V_M1_M1, VLOXSEG8EI64_V, 0x0, 0x0 }, // 4513 |
| 11804 | { PseudoVLOXSEG8EI64_V_M1_M1_MASK, VLOXSEG8EI64_V, 0x0, 0x0 }, // 4514 |
| 11805 | { PseudoVLOXSEG8EI64_V_M2_M1, VLOXSEG8EI64_V, 0x0, 0x0 }, // 4515 |
| 11806 | { PseudoVLOXSEG8EI64_V_M2_M1_MASK, VLOXSEG8EI64_V, 0x0, 0x0 }, // 4516 |
| 11807 | { PseudoVLOXSEG8EI64_V_M4_M1, VLOXSEG8EI64_V, 0x0, 0x0 }, // 4517 |
| 11808 | { PseudoVLOXSEG8EI64_V_M4_M1_MASK, VLOXSEG8EI64_V, 0x0, 0x0 }, // 4518 |
| 11809 | { PseudoVLOXSEG8EI64_V_M8_M1, VLOXSEG8EI64_V, 0x0, 0x0 }, // 4519 |
| 11810 | { PseudoVLOXSEG8EI64_V_M8_M1_MASK, VLOXSEG8EI64_V, 0x0, 0x0 }, // 4520 |
| 11811 | { PseudoVLOXSEG8EI64_V_M1_MF8, VLOXSEG8EI64_V, 0x5, 0x0 }, // 4521 |
| 11812 | { PseudoVLOXSEG8EI64_V_M1_MF8_MASK, VLOXSEG8EI64_V, 0x5, 0x0 }, // 4522 |
| 11813 | { PseudoVLOXSEG8EI64_V_M1_MF4, VLOXSEG8EI64_V, 0x6, 0x0 }, // 4523 |
| 11814 | { PseudoVLOXSEG8EI64_V_M1_MF4_MASK, VLOXSEG8EI64_V, 0x6, 0x0 }, // 4524 |
| 11815 | { PseudoVLOXSEG8EI64_V_M2_MF4, VLOXSEG8EI64_V, 0x6, 0x0 }, // 4525 |
| 11816 | { PseudoVLOXSEG8EI64_V_M2_MF4_MASK, VLOXSEG8EI64_V, 0x6, 0x0 }, // 4526 |
| 11817 | { PseudoVLOXSEG8EI64_V_M1_MF2, VLOXSEG8EI64_V, 0x7, 0x0 }, // 4527 |
| 11818 | { PseudoVLOXSEG8EI64_V_M1_MF2_MASK, VLOXSEG8EI64_V, 0x7, 0x0 }, // 4528 |
| 11819 | { PseudoVLOXSEG8EI64_V_M2_MF2, VLOXSEG8EI64_V, 0x7, 0x0 }, // 4529 |
| 11820 | { PseudoVLOXSEG8EI64_V_M2_MF2_MASK, VLOXSEG8EI64_V, 0x7, 0x0 }, // 4530 |
| 11821 | { PseudoVLOXSEG8EI64_V_M4_MF2, VLOXSEG8EI64_V, 0x7, 0x0 }, // 4531 |
| 11822 | { PseudoVLOXSEG8EI64_V_M4_MF2_MASK, VLOXSEG8EI64_V, 0x7, 0x0 }, // 4532 |
| 11823 | { PseudoVLOXSEG8EI8_V_M1_M1, VLOXSEG8EI8_V, 0x0, 0x0 }, // 4533 |
| 11824 | { PseudoVLOXSEG8EI8_V_M1_M1_MASK, VLOXSEG8EI8_V, 0x0, 0x0 }, // 4534 |
| 11825 | { PseudoVLOXSEG8EI8_V_MF2_M1, VLOXSEG8EI8_V, 0x0, 0x0 }, // 4535 |
| 11826 | { PseudoVLOXSEG8EI8_V_MF2_M1_MASK, VLOXSEG8EI8_V, 0x0, 0x0 }, // 4536 |
| 11827 | { PseudoVLOXSEG8EI8_V_MF4_M1, VLOXSEG8EI8_V, 0x0, 0x0 }, // 4537 |
| 11828 | { PseudoVLOXSEG8EI8_V_MF4_M1_MASK, VLOXSEG8EI8_V, 0x0, 0x0 }, // 4538 |
| 11829 | { PseudoVLOXSEG8EI8_V_MF8_M1, VLOXSEG8EI8_V, 0x0, 0x0 }, // 4539 |
| 11830 | { PseudoVLOXSEG8EI8_V_MF8_M1_MASK, VLOXSEG8EI8_V, 0x0, 0x0 }, // 4540 |
| 11831 | { PseudoVLOXSEG8EI8_V_MF8_MF8, VLOXSEG8EI8_V, 0x5, 0x0 }, // 4541 |
| 11832 | { PseudoVLOXSEG8EI8_V_MF8_MF8_MASK, VLOXSEG8EI8_V, 0x5, 0x0 }, // 4542 |
| 11833 | { PseudoVLOXSEG8EI8_V_MF4_MF4, VLOXSEG8EI8_V, 0x6, 0x0 }, // 4543 |
| 11834 | { PseudoVLOXSEG8EI8_V_MF4_MF4_MASK, VLOXSEG8EI8_V, 0x6, 0x0 }, // 4544 |
| 11835 | { PseudoVLOXSEG8EI8_V_MF8_MF4, VLOXSEG8EI8_V, 0x6, 0x0 }, // 4545 |
| 11836 | { PseudoVLOXSEG8EI8_V_MF8_MF4_MASK, VLOXSEG8EI8_V, 0x6, 0x0 }, // 4546 |
| 11837 | { PseudoVLOXSEG8EI8_V_MF2_MF2, VLOXSEG8EI8_V, 0x7, 0x0 }, // 4547 |
| 11838 | { PseudoVLOXSEG8EI8_V_MF2_MF2_MASK, VLOXSEG8EI8_V, 0x7, 0x0 }, // 4548 |
| 11839 | { PseudoVLOXSEG8EI8_V_MF4_MF2, VLOXSEG8EI8_V, 0x7, 0x0 }, // 4549 |
| 11840 | { PseudoVLOXSEG8EI8_V_MF4_MF2_MASK, VLOXSEG8EI8_V, 0x7, 0x0 }, // 4550 |
| 11841 | { PseudoVLOXSEG8EI8_V_MF8_MF2, VLOXSEG8EI8_V, 0x7, 0x0 }, // 4551 |
| 11842 | { PseudoVLOXSEG8EI8_V_MF8_MF2_MASK, VLOXSEG8EI8_V, 0x7, 0x0 }, // 4552 |
| 11843 | { PseudoVLSE16_V_M1, VLSE16_V, 0x0, 0x10 }, // 4553 |
| 11844 | { PseudoVLSE16_V_M1_MASK, VLSE16_V, 0x0, 0x10 }, // 4554 |
| 11845 | { PseudoVLSE16_V_M2, VLSE16_V, 0x1, 0x10 }, // 4555 |
| 11846 | { PseudoVLSE16_V_M2_MASK, VLSE16_V, 0x1, 0x10 }, // 4556 |
| 11847 | { PseudoVLSE16_V_M4, VLSE16_V, 0x2, 0x10 }, // 4557 |
| 11848 | { PseudoVLSE16_V_M4_MASK, VLSE16_V, 0x2, 0x10 }, // 4558 |
| 11849 | { PseudoVLSE16_V_M8, VLSE16_V, 0x3, 0x10 }, // 4559 |
| 11850 | { PseudoVLSE16_V_M8_MASK, VLSE16_V, 0x3, 0x10 }, // 4560 |
| 11851 | { PseudoVLSE16_V_MF4, VLSE16_V, 0x6, 0x10 }, // 4561 |
| 11852 | { PseudoVLSE16_V_MF4_MASK, VLSE16_V, 0x6, 0x10 }, // 4562 |
| 11853 | { PseudoVLSE16_V_MF2, VLSE16_V, 0x7, 0x10 }, // 4563 |
| 11854 | { PseudoVLSE16_V_MF2_MASK, VLSE16_V, 0x7, 0x10 }, // 4564 |
| 11855 | { PseudoVLSE32_V_M1, VLSE32_V, 0x0, 0x20 }, // 4565 |
| 11856 | { PseudoVLSE32_V_M1_MASK, VLSE32_V, 0x0, 0x20 }, // 4566 |
| 11857 | { PseudoVLSE32_V_M2, VLSE32_V, 0x1, 0x20 }, // 4567 |
| 11858 | { PseudoVLSE32_V_M2_MASK, VLSE32_V, 0x1, 0x20 }, // 4568 |
| 11859 | { PseudoVLSE32_V_M4, VLSE32_V, 0x2, 0x20 }, // 4569 |
| 11860 | { PseudoVLSE32_V_M4_MASK, VLSE32_V, 0x2, 0x20 }, // 4570 |
| 11861 | { PseudoVLSE32_V_M8, VLSE32_V, 0x3, 0x20 }, // 4571 |
| 11862 | { PseudoVLSE32_V_M8_MASK, VLSE32_V, 0x3, 0x20 }, // 4572 |
| 11863 | { PseudoVLSE32_V_MF2, VLSE32_V, 0x7, 0x20 }, // 4573 |
| 11864 | { PseudoVLSE32_V_MF2_MASK, VLSE32_V, 0x7, 0x20 }, // 4574 |
| 11865 | { PseudoVLSE64_V_M1, VLSE64_V, 0x0, 0x40 }, // 4575 |
| 11866 | { PseudoVLSE64_V_M1_MASK, VLSE64_V, 0x0, 0x40 }, // 4576 |
| 11867 | { PseudoVLSE64_V_M2, VLSE64_V, 0x1, 0x40 }, // 4577 |
| 11868 | { PseudoVLSE64_V_M2_MASK, VLSE64_V, 0x1, 0x40 }, // 4578 |
| 11869 | { PseudoVLSE64_V_M4, VLSE64_V, 0x2, 0x40 }, // 4579 |
| 11870 | { PseudoVLSE64_V_M4_MASK, VLSE64_V, 0x2, 0x40 }, // 4580 |
| 11871 | { PseudoVLSE64_V_M8, VLSE64_V, 0x3, 0x40 }, // 4581 |
| 11872 | { PseudoVLSE64_V_M8_MASK, VLSE64_V, 0x3, 0x40 }, // 4582 |
| 11873 | { PseudoVLSE8_V_M1, VLSE8_V, 0x0, 0x8 }, // 4583 |
| 11874 | { PseudoVLSE8_V_M1_MASK, VLSE8_V, 0x0, 0x8 }, // 4584 |
| 11875 | { PseudoVLSE8_V_M2, VLSE8_V, 0x1, 0x8 }, // 4585 |
| 11876 | { PseudoVLSE8_V_M2_MASK, VLSE8_V, 0x1, 0x8 }, // 4586 |
| 11877 | { PseudoVLSE8_V_M4, VLSE8_V, 0x2, 0x8 }, // 4587 |
| 11878 | { PseudoVLSE8_V_M4_MASK, VLSE8_V, 0x2, 0x8 }, // 4588 |
| 11879 | { PseudoVLSE8_V_M8, VLSE8_V, 0x3, 0x8 }, // 4589 |
| 11880 | { PseudoVLSE8_V_M8_MASK, VLSE8_V, 0x3, 0x8 }, // 4590 |
| 11881 | { PseudoVLSE8_V_MF8, VLSE8_V, 0x5, 0x8 }, // 4591 |
| 11882 | { PseudoVLSE8_V_MF8_MASK, VLSE8_V, 0x5, 0x8 }, // 4592 |
| 11883 | { PseudoVLSE8_V_MF4, VLSE8_V, 0x6, 0x8 }, // 4593 |
| 11884 | { PseudoVLSE8_V_MF4_MASK, VLSE8_V, 0x6, 0x8 }, // 4594 |
| 11885 | { PseudoVLSE8_V_MF2, VLSE8_V, 0x7, 0x8 }, // 4595 |
| 11886 | { PseudoVLSE8_V_MF2_MASK, VLSE8_V, 0x7, 0x8 }, // 4596 |
| 11887 | { PseudoVLSEG2E16FF_V_M1, VLSEG2E16FF_V, 0x0, 0x10 }, // 4597 |
| 11888 | { PseudoVLSEG2E16FF_V_M1_MASK, VLSEG2E16FF_V, 0x0, 0x10 }, // 4598 |
| 11889 | { PseudoVLSEG2E16FF_V_M2, VLSEG2E16FF_V, 0x1, 0x10 }, // 4599 |
| 11890 | { PseudoVLSEG2E16FF_V_M2_MASK, VLSEG2E16FF_V, 0x1, 0x10 }, // 4600 |
| 11891 | { PseudoVLSEG2E16FF_V_M4, VLSEG2E16FF_V, 0x2, 0x10 }, // 4601 |
| 11892 | { PseudoVLSEG2E16FF_V_M4_MASK, VLSEG2E16FF_V, 0x2, 0x10 }, // 4602 |
| 11893 | { PseudoVLSEG2E16FF_V_MF4, VLSEG2E16FF_V, 0x6, 0x10 }, // 4603 |
| 11894 | { PseudoVLSEG2E16FF_V_MF4_MASK, VLSEG2E16FF_V, 0x6, 0x10 }, // 4604 |
| 11895 | { PseudoVLSEG2E16FF_V_MF2, VLSEG2E16FF_V, 0x7, 0x10 }, // 4605 |
| 11896 | { PseudoVLSEG2E16FF_V_MF2_MASK, VLSEG2E16FF_V, 0x7, 0x10 }, // 4606 |
| 11897 | { PseudoVLSEG2E16_V_M1, VLSEG2E16_V, 0x0, 0x10 }, // 4607 |
| 11898 | { PseudoVLSEG2E16_V_M1_MASK, VLSEG2E16_V, 0x0, 0x10 }, // 4608 |
| 11899 | { PseudoVLSEG2E16_V_M2, VLSEG2E16_V, 0x1, 0x10 }, // 4609 |
| 11900 | { PseudoVLSEG2E16_V_M2_MASK, VLSEG2E16_V, 0x1, 0x10 }, // 4610 |
| 11901 | { PseudoVLSEG2E16_V_M4, VLSEG2E16_V, 0x2, 0x10 }, // 4611 |
| 11902 | { PseudoVLSEG2E16_V_M4_MASK, VLSEG2E16_V, 0x2, 0x10 }, // 4612 |
| 11903 | { PseudoVLSEG2E16_V_MF4, VLSEG2E16_V, 0x6, 0x10 }, // 4613 |
| 11904 | { PseudoVLSEG2E16_V_MF4_MASK, VLSEG2E16_V, 0x6, 0x10 }, // 4614 |
| 11905 | { PseudoVLSEG2E16_V_MF2, VLSEG2E16_V, 0x7, 0x10 }, // 4615 |
| 11906 | { PseudoVLSEG2E16_V_MF2_MASK, VLSEG2E16_V, 0x7, 0x10 }, // 4616 |
| 11907 | { PseudoVLSEG2E32FF_V_M1, VLSEG2E32FF_V, 0x0, 0x20 }, // 4617 |
| 11908 | { PseudoVLSEG2E32FF_V_M1_MASK, VLSEG2E32FF_V, 0x0, 0x20 }, // 4618 |
| 11909 | { PseudoVLSEG2E32FF_V_M2, VLSEG2E32FF_V, 0x1, 0x20 }, // 4619 |
| 11910 | { PseudoVLSEG2E32FF_V_M2_MASK, VLSEG2E32FF_V, 0x1, 0x20 }, // 4620 |
| 11911 | { PseudoVLSEG2E32FF_V_M4, VLSEG2E32FF_V, 0x2, 0x20 }, // 4621 |
| 11912 | { PseudoVLSEG2E32FF_V_M4_MASK, VLSEG2E32FF_V, 0x2, 0x20 }, // 4622 |
| 11913 | { PseudoVLSEG2E32FF_V_MF2, VLSEG2E32FF_V, 0x7, 0x20 }, // 4623 |
| 11914 | { PseudoVLSEG2E32FF_V_MF2_MASK, VLSEG2E32FF_V, 0x7, 0x20 }, // 4624 |
| 11915 | { PseudoVLSEG2E32_V_M1, VLSEG2E32_V, 0x0, 0x20 }, // 4625 |
| 11916 | { PseudoVLSEG2E32_V_M1_MASK, VLSEG2E32_V, 0x0, 0x20 }, // 4626 |
| 11917 | { PseudoVLSEG2E32_V_M2, VLSEG2E32_V, 0x1, 0x20 }, // 4627 |
| 11918 | { PseudoVLSEG2E32_V_M2_MASK, VLSEG2E32_V, 0x1, 0x20 }, // 4628 |
| 11919 | { PseudoVLSEG2E32_V_M4, VLSEG2E32_V, 0x2, 0x20 }, // 4629 |
| 11920 | { PseudoVLSEG2E32_V_M4_MASK, VLSEG2E32_V, 0x2, 0x20 }, // 4630 |
| 11921 | { PseudoVLSEG2E32_V_MF2, VLSEG2E32_V, 0x7, 0x20 }, // 4631 |
| 11922 | { PseudoVLSEG2E32_V_MF2_MASK, VLSEG2E32_V, 0x7, 0x20 }, // 4632 |
| 11923 | { PseudoVLSEG2E64FF_V_M1, VLSEG2E64FF_V, 0x0, 0x40 }, // 4633 |
| 11924 | { PseudoVLSEG2E64FF_V_M1_MASK, VLSEG2E64FF_V, 0x0, 0x40 }, // 4634 |
| 11925 | { PseudoVLSEG2E64FF_V_M2, VLSEG2E64FF_V, 0x1, 0x40 }, // 4635 |
| 11926 | { PseudoVLSEG2E64FF_V_M2_MASK, VLSEG2E64FF_V, 0x1, 0x40 }, // 4636 |
| 11927 | { PseudoVLSEG2E64FF_V_M4, VLSEG2E64FF_V, 0x2, 0x40 }, // 4637 |
| 11928 | { PseudoVLSEG2E64FF_V_M4_MASK, VLSEG2E64FF_V, 0x2, 0x40 }, // 4638 |
| 11929 | { PseudoVLSEG2E64_V_M1, VLSEG2E64_V, 0x0, 0x40 }, // 4639 |
| 11930 | { PseudoVLSEG2E64_V_M1_MASK, VLSEG2E64_V, 0x0, 0x40 }, // 4640 |
| 11931 | { PseudoVLSEG2E64_V_M2, VLSEG2E64_V, 0x1, 0x40 }, // 4641 |
| 11932 | { PseudoVLSEG2E64_V_M2_MASK, VLSEG2E64_V, 0x1, 0x40 }, // 4642 |
| 11933 | { PseudoVLSEG2E64_V_M4, VLSEG2E64_V, 0x2, 0x40 }, // 4643 |
| 11934 | { PseudoVLSEG2E64_V_M4_MASK, VLSEG2E64_V, 0x2, 0x40 }, // 4644 |
| 11935 | { PseudoVLSEG2E8FF_V_M1, VLSEG2E8FF_V, 0x0, 0x8 }, // 4645 |
| 11936 | { PseudoVLSEG2E8FF_V_M1_MASK, VLSEG2E8FF_V, 0x0, 0x8 }, // 4646 |
| 11937 | { PseudoVLSEG2E8FF_V_M2, VLSEG2E8FF_V, 0x1, 0x8 }, // 4647 |
| 11938 | { PseudoVLSEG2E8FF_V_M2_MASK, VLSEG2E8FF_V, 0x1, 0x8 }, // 4648 |
| 11939 | { PseudoVLSEG2E8FF_V_M4, VLSEG2E8FF_V, 0x2, 0x8 }, // 4649 |
| 11940 | { PseudoVLSEG2E8FF_V_M4_MASK, VLSEG2E8FF_V, 0x2, 0x8 }, // 4650 |
| 11941 | { PseudoVLSEG2E8FF_V_MF8, VLSEG2E8FF_V, 0x5, 0x8 }, // 4651 |
| 11942 | { PseudoVLSEG2E8FF_V_MF8_MASK, VLSEG2E8FF_V, 0x5, 0x8 }, // 4652 |
| 11943 | { PseudoVLSEG2E8FF_V_MF4, VLSEG2E8FF_V, 0x6, 0x8 }, // 4653 |
| 11944 | { PseudoVLSEG2E8FF_V_MF4_MASK, VLSEG2E8FF_V, 0x6, 0x8 }, // 4654 |
| 11945 | { PseudoVLSEG2E8FF_V_MF2, VLSEG2E8FF_V, 0x7, 0x8 }, // 4655 |
| 11946 | { PseudoVLSEG2E8FF_V_MF2_MASK, VLSEG2E8FF_V, 0x7, 0x8 }, // 4656 |
| 11947 | { PseudoVLSEG2E8_V_M1, VLSEG2E8_V, 0x0, 0x8 }, // 4657 |
| 11948 | { PseudoVLSEG2E8_V_M1_MASK, VLSEG2E8_V, 0x0, 0x8 }, // 4658 |
| 11949 | { PseudoVLSEG2E8_V_M2, VLSEG2E8_V, 0x1, 0x8 }, // 4659 |
| 11950 | { PseudoVLSEG2E8_V_M2_MASK, VLSEG2E8_V, 0x1, 0x8 }, // 4660 |
| 11951 | { PseudoVLSEG2E8_V_M4, VLSEG2E8_V, 0x2, 0x8 }, // 4661 |
| 11952 | { PseudoVLSEG2E8_V_M4_MASK, VLSEG2E8_V, 0x2, 0x8 }, // 4662 |
| 11953 | { PseudoVLSEG2E8_V_MF8, VLSEG2E8_V, 0x5, 0x8 }, // 4663 |
| 11954 | { PseudoVLSEG2E8_V_MF8_MASK, VLSEG2E8_V, 0x5, 0x8 }, // 4664 |
| 11955 | { PseudoVLSEG2E8_V_MF4, VLSEG2E8_V, 0x6, 0x8 }, // 4665 |
| 11956 | { PseudoVLSEG2E8_V_MF4_MASK, VLSEG2E8_V, 0x6, 0x8 }, // 4666 |
| 11957 | { PseudoVLSEG2E8_V_MF2, VLSEG2E8_V, 0x7, 0x8 }, // 4667 |
| 11958 | { PseudoVLSEG2E8_V_MF2_MASK, VLSEG2E8_V, 0x7, 0x8 }, // 4668 |
| 11959 | { PseudoVLSEG3E16FF_V_M1, VLSEG3E16FF_V, 0x0, 0x10 }, // 4669 |
| 11960 | { PseudoVLSEG3E16FF_V_M1_MASK, VLSEG3E16FF_V, 0x0, 0x10 }, // 4670 |
| 11961 | { PseudoVLSEG3E16FF_V_M2, VLSEG3E16FF_V, 0x1, 0x10 }, // 4671 |
| 11962 | { PseudoVLSEG3E16FF_V_M2_MASK, VLSEG3E16FF_V, 0x1, 0x10 }, // 4672 |
| 11963 | { PseudoVLSEG3E16FF_V_MF4, VLSEG3E16FF_V, 0x6, 0x10 }, // 4673 |
| 11964 | { PseudoVLSEG3E16FF_V_MF4_MASK, VLSEG3E16FF_V, 0x6, 0x10 }, // 4674 |
| 11965 | { PseudoVLSEG3E16FF_V_MF2, VLSEG3E16FF_V, 0x7, 0x10 }, // 4675 |
| 11966 | { PseudoVLSEG3E16FF_V_MF2_MASK, VLSEG3E16FF_V, 0x7, 0x10 }, // 4676 |
| 11967 | { PseudoVLSEG3E16_V_M1, VLSEG3E16_V, 0x0, 0x10 }, // 4677 |
| 11968 | { PseudoVLSEG3E16_V_M1_MASK, VLSEG3E16_V, 0x0, 0x10 }, // 4678 |
| 11969 | { PseudoVLSEG3E16_V_M2, VLSEG3E16_V, 0x1, 0x10 }, // 4679 |
| 11970 | { PseudoVLSEG3E16_V_M2_MASK, VLSEG3E16_V, 0x1, 0x10 }, // 4680 |
| 11971 | { PseudoVLSEG3E16_V_MF4, VLSEG3E16_V, 0x6, 0x10 }, // 4681 |
| 11972 | { PseudoVLSEG3E16_V_MF4_MASK, VLSEG3E16_V, 0x6, 0x10 }, // 4682 |
| 11973 | { PseudoVLSEG3E16_V_MF2, VLSEG3E16_V, 0x7, 0x10 }, // 4683 |
| 11974 | { PseudoVLSEG3E16_V_MF2_MASK, VLSEG3E16_V, 0x7, 0x10 }, // 4684 |
| 11975 | { PseudoVLSEG3E32FF_V_M1, VLSEG3E32FF_V, 0x0, 0x20 }, // 4685 |
| 11976 | { PseudoVLSEG3E32FF_V_M1_MASK, VLSEG3E32FF_V, 0x0, 0x20 }, // 4686 |
| 11977 | { PseudoVLSEG3E32FF_V_M2, VLSEG3E32FF_V, 0x1, 0x20 }, // 4687 |
| 11978 | { PseudoVLSEG3E32FF_V_M2_MASK, VLSEG3E32FF_V, 0x1, 0x20 }, // 4688 |
| 11979 | { PseudoVLSEG3E32FF_V_MF2, VLSEG3E32FF_V, 0x7, 0x20 }, // 4689 |
| 11980 | { PseudoVLSEG3E32FF_V_MF2_MASK, VLSEG3E32FF_V, 0x7, 0x20 }, // 4690 |
| 11981 | { PseudoVLSEG3E32_V_M1, VLSEG3E32_V, 0x0, 0x20 }, // 4691 |
| 11982 | { PseudoVLSEG3E32_V_M1_MASK, VLSEG3E32_V, 0x0, 0x20 }, // 4692 |
| 11983 | { PseudoVLSEG3E32_V_M2, VLSEG3E32_V, 0x1, 0x20 }, // 4693 |
| 11984 | { PseudoVLSEG3E32_V_M2_MASK, VLSEG3E32_V, 0x1, 0x20 }, // 4694 |
| 11985 | { PseudoVLSEG3E32_V_MF2, VLSEG3E32_V, 0x7, 0x20 }, // 4695 |
| 11986 | { PseudoVLSEG3E32_V_MF2_MASK, VLSEG3E32_V, 0x7, 0x20 }, // 4696 |
| 11987 | { PseudoVLSEG3E64FF_V_M1, VLSEG3E64FF_V, 0x0, 0x40 }, // 4697 |
| 11988 | { PseudoVLSEG3E64FF_V_M1_MASK, VLSEG3E64FF_V, 0x0, 0x40 }, // 4698 |
| 11989 | { PseudoVLSEG3E64FF_V_M2, VLSEG3E64FF_V, 0x1, 0x40 }, // 4699 |
| 11990 | { PseudoVLSEG3E64FF_V_M2_MASK, VLSEG3E64FF_V, 0x1, 0x40 }, // 4700 |
| 11991 | { PseudoVLSEG3E64_V_M1, VLSEG3E64_V, 0x0, 0x40 }, // 4701 |
| 11992 | { PseudoVLSEG3E64_V_M1_MASK, VLSEG3E64_V, 0x0, 0x40 }, // 4702 |
| 11993 | { PseudoVLSEG3E64_V_M2, VLSEG3E64_V, 0x1, 0x40 }, // 4703 |
| 11994 | { PseudoVLSEG3E64_V_M2_MASK, VLSEG3E64_V, 0x1, 0x40 }, // 4704 |
| 11995 | { PseudoVLSEG3E8FF_V_M1, VLSEG3E8FF_V, 0x0, 0x8 }, // 4705 |
| 11996 | { PseudoVLSEG3E8FF_V_M1_MASK, VLSEG3E8FF_V, 0x0, 0x8 }, // 4706 |
| 11997 | { PseudoVLSEG3E8FF_V_M2, VLSEG3E8FF_V, 0x1, 0x8 }, // 4707 |
| 11998 | { PseudoVLSEG3E8FF_V_M2_MASK, VLSEG3E8FF_V, 0x1, 0x8 }, // 4708 |
| 11999 | { PseudoVLSEG3E8FF_V_MF8, VLSEG3E8FF_V, 0x5, 0x8 }, // 4709 |
| 12000 | { PseudoVLSEG3E8FF_V_MF8_MASK, VLSEG3E8FF_V, 0x5, 0x8 }, // 4710 |
| 12001 | { PseudoVLSEG3E8FF_V_MF4, VLSEG3E8FF_V, 0x6, 0x8 }, // 4711 |
| 12002 | { PseudoVLSEG3E8FF_V_MF4_MASK, VLSEG3E8FF_V, 0x6, 0x8 }, // 4712 |
| 12003 | { PseudoVLSEG3E8FF_V_MF2, VLSEG3E8FF_V, 0x7, 0x8 }, // 4713 |
| 12004 | { PseudoVLSEG3E8FF_V_MF2_MASK, VLSEG3E8FF_V, 0x7, 0x8 }, // 4714 |
| 12005 | { PseudoVLSEG3E8_V_M1, VLSEG3E8_V, 0x0, 0x8 }, // 4715 |
| 12006 | { PseudoVLSEG3E8_V_M1_MASK, VLSEG3E8_V, 0x0, 0x8 }, // 4716 |
| 12007 | { PseudoVLSEG3E8_V_M2, VLSEG3E8_V, 0x1, 0x8 }, // 4717 |
| 12008 | { PseudoVLSEG3E8_V_M2_MASK, VLSEG3E8_V, 0x1, 0x8 }, // 4718 |
| 12009 | { PseudoVLSEG3E8_V_MF8, VLSEG3E8_V, 0x5, 0x8 }, // 4719 |
| 12010 | { PseudoVLSEG3E8_V_MF8_MASK, VLSEG3E8_V, 0x5, 0x8 }, // 4720 |
| 12011 | { PseudoVLSEG3E8_V_MF4, VLSEG3E8_V, 0x6, 0x8 }, // 4721 |
| 12012 | { PseudoVLSEG3E8_V_MF4_MASK, VLSEG3E8_V, 0x6, 0x8 }, // 4722 |
| 12013 | { PseudoVLSEG3E8_V_MF2, VLSEG3E8_V, 0x7, 0x8 }, // 4723 |
| 12014 | { PseudoVLSEG3E8_V_MF2_MASK, VLSEG3E8_V, 0x7, 0x8 }, // 4724 |
| 12015 | { PseudoVLSEG4E16FF_V_M1, VLSEG4E16FF_V, 0x0, 0x10 }, // 4725 |
| 12016 | { PseudoVLSEG4E16FF_V_M1_MASK, VLSEG4E16FF_V, 0x0, 0x10 }, // 4726 |
| 12017 | { PseudoVLSEG4E16FF_V_M2, VLSEG4E16FF_V, 0x1, 0x10 }, // 4727 |
| 12018 | { PseudoVLSEG4E16FF_V_M2_MASK, VLSEG4E16FF_V, 0x1, 0x10 }, // 4728 |
| 12019 | { PseudoVLSEG4E16FF_V_MF4, VLSEG4E16FF_V, 0x6, 0x10 }, // 4729 |
| 12020 | { PseudoVLSEG4E16FF_V_MF4_MASK, VLSEG4E16FF_V, 0x6, 0x10 }, // 4730 |
| 12021 | { PseudoVLSEG4E16FF_V_MF2, VLSEG4E16FF_V, 0x7, 0x10 }, // 4731 |
| 12022 | { PseudoVLSEG4E16FF_V_MF2_MASK, VLSEG4E16FF_V, 0x7, 0x10 }, // 4732 |
| 12023 | { PseudoVLSEG4E16_V_M1, VLSEG4E16_V, 0x0, 0x10 }, // 4733 |
| 12024 | { PseudoVLSEG4E16_V_M1_MASK, VLSEG4E16_V, 0x0, 0x10 }, // 4734 |
| 12025 | { PseudoVLSEG4E16_V_M2, VLSEG4E16_V, 0x1, 0x10 }, // 4735 |
| 12026 | { PseudoVLSEG4E16_V_M2_MASK, VLSEG4E16_V, 0x1, 0x10 }, // 4736 |
| 12027 | { PseudoVLSEG4E16_V_MF4, VLSEG4E16_V, 0x6, 0x10 }, // 4737 |
| 12028 | { PseudoVLSEG4E16_V_MF4_MASK, VLSEG4E16_V, 0x6, 0x10 }, // 4738 |
| 12029 | { PseudoVLSEG4E16_V_MF2, VLSEG4E16_V, 0x7, 0x10 }, // 4739 |
| 12030 | { PseudoVLSEG4E16_V_MF2_MASK, VLSEG4E16_V, 0x7, 0x10 }, // 4740 |
| 12031 | { PseudoVLSEG4E32FF_V_M1, VLSEG4E32FF_V, 0x0, 0x20 }, // 4741 |
| 12032 | { PseudoVLSEG4E32FF_V_M1_MASK, VLSEG4E32FF_V, 0x0, 0x20 }, // 4742 |
| 12033 | { PseudoVLSEG4E32FF_V_M2, VLSEG4E32FF_V, 0x1, 0x20 }, // 4743 |
| 12034 | { PseudoVLSEG4E32FF_V_M2_MASK, VLSEG4E32FF_V, 0x1, 0x20 }, // 4744 |
| 12035 | { PseudoVLSEG4E32FF_V_MF2, VLSEG4E32FF_V, 0x7, 0x20 }, // 4745 |
| 12036 | { PseudoVLSEG4E32FF_V_MF2_MASK, VLSEG4E32FF_V, 0x7, 0x20 }, // 4746 |
| 12037 | { PseudoVLSEG4E32_V_M1, VLSEG4E32_V, 0x0, 0x20 }, // 4747 |
| 12038 | { PseudoVLSEG4E32_V_M1_MASK, VLSEG4E32_V, 0x0, 0x20 }, // 4748 |
| 12039 | { PseudoVLSEG4E32_V_M2, VLSEG4E32_V, 0x1, 0x20 }, // 4749 |
| 12040 | { PseudoVLSEG4E32_V_M2_MASK, VLSEG4E32_V, 0x1, 0x20 }, // 4750 |
| 12041 | { PseudoVLSEG4E32_V_MF2, VLSEG4E32_V, 0x7, 0x20 }, // 4751 |
| 12042 | { PseudoVLSEG4E32_V_MF2_MASK, VLSEG4E32_V, 0x7, 0x20 }, // 4752 |
| 12043 | { PseudoVLSEG4E64FF_V_M1, VLSEG4E64FF_V, 0x0, 0x40 }, // 4753 |
| 12044 | { PseudoVLSEG4E64FF_V_M1_MASK, VLSEG4E64FF_V, 0x0, 0x40 }, // 4754 |
| 12045 | { PseudoVLSEG4E64FF_V_M2, VLSEG4E64FF_V, 0x1, 0x40 }, // 4755 |
| 12046 | { PseudoVLSEG4E64FF_V_M2_MASK, VLSEG4E64FF_V, 0x1, 0x40 }, // 4756 |
| 12047 | { PseudoVLSEG4E64_V_M1, VLSEG4E64_V, 0x0, 0x40 }, // 4757 |
| 12048 | { PseudoVLSEG4E64_V_M1_MASK, VLSEG4E64_V, 0x0, 0x40 }, // 4758 |
| 12049 | { PseudoVLSEG4E64_V_M2, VLSEG4E64_V, 0x1, 0x40 }, // 4759 |
| 12050 | { PseudoVLSEG4E64_V_M2_MASK, VLSEG4E64_V, 0x1, 0x40 }, // 4760 |
| 12051 | { PseudoVLSEG4E8FF_V_M1, VLSEG4E8FF_V, 0x0, 0x8 }, // 4761 |
| 12052 | { PseudoVLSEG4E8FF_V_M1_MASK, VLSEG4E8FF_V, 0x0, 0x8 }, // 4762 |
| 12053 | { PseudoVLSEG4E8FF_V_M2, VLSEG4E8FF_V, 0x1, 0x8 }, // 4763 |
| 12054 | { PseudoVLSEG4E8FF_V_M2_MASK, VLSEG4E8FF_V, 0x1, 0x8 }, // 4764 |
| 12055 | { PseudoVLSEG4E8FF_V_MF8, VLSEG4E8FF_V, 0x5, 0x8 }, // 4765 |
| 12056 | { PseudoVLSEG4E8FF_V_MF8_MASK, VLSEG4E8FF_V, 0x5, 0x8 }, // 4766 |
| 12057 | { PseudoVLSEG4E8FF_V_MF4, VLSEG4E8FF_V, 0x6, 0x8 }, // 4767 |
| 12058 | { PseudoVLSEG4E8FF_V_MF4_MASK, VLSEG4E8FF_V, 0x6, 0x8 }, // 4768 |
| 12059 | { PseudoVLSEG4E8FF_V_MF2, VLSEG4E8FF_V, 0x7, 0x8 }, // 4769 |
| 12060 | { PseudoVLSEG4E8FF_V_MF2_MASK, VLSEG4E8FF_V, 0x7, 0x8 }, // 4770 |
| 12061 | { PseudoVLSEG4E8_V_M1, VLSEG4E8_V, 0x0, 0x8 }, // 4771 |
| 12062 | { PseudoVLSEG4E8_V_M1_MASK, VLSEG4E8_V, 0x0, 0x8 }, // 4772 |
| 12063 | { PseudoVLSEG4E8_V_M2, VLSEG4E8_V, 0x1, 0x8 }, // 4773 |
| 12064 | { PseudoVLSEG4E8_V_M2_MASK, VLSEG4E8_V, 0x1, 0x8 }, // 4774 |
| 12065 | { PseudoVLSEG4E8_V_MF8, VLSEG4E8_V, 0x5, 0x8 }, // 4775 |
| 12066 | { PseudoVLSEG4E8_V_MF8_MASK, VLSEG4E8_V, 0x5, 0x8 }, // 4776 |
| 12067 | { PseudoVLSEG4E8_V_MF4, VLSEG4E8_V, 0x6, 0x8 }, // 4777 |
| 12068 | { PseudoVLSEG4E8_V_MF4_MASK, VLSEG4E8_V, 0x6, 0x8 }, // 4778 |
| 12069 | { PseudoVLSEG4E8_V_MF2, VLSEG4E8_V, 0x7, 0x8 }, // 4779 |
| 12070 | { PseudoVLSEG4E8_V_MF2_MASK, VLSEG4E8_V, 0x7, 0x8 }, // 4780 |
| 12071 | { PseudoVLSEG5E16FF_V_M1, VLSEG5E16FF_V, 0x0, 0x10 }, // 4781 |
| 12072 | { PseudoVLSEG5E16FF_V_M1_MASK, VLSEG5E16FF_V, 0x0, 0x10 }, // 4782 |
| 12073 | { PseudoVLSEG5E16FF_V_MF4, VLSEG5E16FF_V, 0x6, 0x10 }, // 4783 |
| 12074 | { PseudoVLSEG5E16FF_V_MF4_MASK, VLSEG5E16FF_V, 0x6, 0x10 }, // 4784 |
| 12075 | { PseudoVLSEG5E16FF_V_MF2, VLSEG5E16FF_V, 0x7, 0x10 }, // 4785 |
| 12076 | { PseudoVLSEG5E16FF_V_MF2_MASK, VLSEG5E16FF_V, 0x7, 0x10 }, // 4786 |
| 12077 | { PseudoVLSEG5E16_V_M1, VLSEG5E16_V, 0x0, 0x10 }, // 4787 |
| 12078 | { PseudoVLSEG5E16_V_M1_MASK, VLSEG5E16_V, 0x0, 0x10 }, // 4788 |
| 12079 | { PseudoVLSEG5E16_V_MF4, VLSEG5E16_V, 0x6, 0x10 }, // 4789 |
| 12080 | { PseudoVLSEG5E16_V_MF4_MASK, VLSEG5E16_V, 0x6, 0x10 }, // 4790 |
| 12081 | { PseudoVLSEG5E16_V_MF2, VLSEG5E16_V, 0x7, 0x10 }, // 4791 |
| 12082 | { PseudoVLSEG5E16_V_MF2_MASK, VLSEG5E16_V, 0x7, 0x10 }, // 4792 |
| 12083 | { PseudoVLSEG5E32FF_V_M1, VLSEG5E32FF_V, 0x0, 0x20 }, // 4793 |
| 12084 | { PseudoVLSEG5E32FF_V_M1_MASK, VLSEG5E32FF_V, 0x0, 0x20 }, // 4794 |
| 12085 | { PseudoVLSEG5E32FF_V_MF2, VLSEG5E32FF_V, 0x7, 0x20 }, // 4795 |
| 12086 | { PseudoVLSEG5E32FF_V_MF2_MASK, VLSEG5E32FF_V, 0x7, 0x20 }, // 4796 |
| 12087 | { PseudoVLSEG5E32_V_M1, VLSEG5E32_V, 0x0, 0x20 }, // 4797 |
| 12088 | { PseudoVLSEG5E32_V_M1_MASK, VLSEG5E32_V, 0x0, 0x20 }, // 4798 |
| 12089 | { PseudoVLSEG5E32_V_MF2, VLSEG5E32_V, 0x7, 0x20 }, // 4799 |
| 12090 | { PseudoVLSEG5E32_V_MF2_MASK, VLSEG5E32_V, 0x7, 0x20 }, // 4800 |
| 12091 | { PseudoVLSEG5E64FF_V_M1, VLSEG5E64FF_V, 0x0, 0x40 }, // 4801 |
| 12092 | { PseudoVLSEG5E64FF_V_M1_MASK, VLSEG5E64FF_V, 0x0, 0x40 }, // 4802 |
| 12093 | { PseudoVLSEG5E64_V_M1, VLSEG5E64_V, 0x0, 0x40 }, // 4803 |
| 12094 | { PseudoVLSEG5E64_V_M1_MASK, VLSEG5E64_V, 0x0, 0x40 }, // 4804 |
| 12095 | { PseudoVLSEG5E8FF_V_M1, VLSEG5E8FF_V, 0x0, 0x8 }, // 4805 |
| 12096 | { PseudoVLSEG5E8FF_V_M1_MASK, VLSEG5E8FF_V, 0x0, 0x8 }, // 4806 |
| 12097 | { PseudoVLSEG5E8FF_V_MF8, VLSEG5E8FF_V, 0x5, 0x8 }, // 4807 |
| 12098 | { PseudoVLSEG5E8FF_V_MF8_MASK, VLSEG5E8FF_V, 0x5, 0x8 }, // 4808 |
| 12099 | { PseudoVLSEG5E8FF_V_MF4, VLSEG5E8FF_V, 0x6, 0x8 }, // 4809 |
| 12100 | { PseudoVLSEG5E8FF_V_MF4_MASK, VLSEG5E8FF_V, 0x6, 0x8 }, // 4810 |
| 12101 | { PseudoVLSEG5E8FF_V_MF2, VLSEG5E8FF_V, 0x7, 0x8 }, // 4811 |
| 12102 | { PseudoVLSEG5E8FF_V_MF2_MASK, VLSEG5E8FF_V, 0x7, 0x8 }, // 4812 |
| 12103 | { PseudoVLSEG5E8_V_M1, VLSEG5E8_V, 0x0, 0x8 }, // 4813 |
| 12104 | { PseudoVLSEG5E8_V_M1_MASK, VLSEG5E8_V, 0x0, 0x8 }, // 4814 |
| 12105 | { PseudoVLSEG5E8_V_MF8, VLSEG5E8_V, 0x5, 0x8 }, // 4815 |
| 12106 | { PseudoVLSEG5E8_V_MF8_MASK, VLSEG5E8_V, 0x5, 0x8 }, // 4816 |
| 12107 | { PseudoVLSEG5E8_V_MF4, VLSEG5E8_V, 0x6, 0x8 }, // 4817 |
| 12108 | { PseudoVLSEG5E8_V_MF4_MASK, VLSEG5E8_V, 0x6, 0x8 }, // 4818 |
| 12109 | { PseudoVLSEG5E8_V_MF2, VLSEG5E8_V, 0x7, 0x8 }, // 4819 |
| 12110 | { PseudoVLSEG5E8_V_MF2_MASK, VLSEG5E8_V, 0x7, 0x8 }, // 4820 |
| 12111 | { PseudoVLSEG6E16FF_V_M1, VLSEG6E16FF_V, 0x0, 0x10 }, // 4821 |
| 12112 | { PseudoVLSEG6E16FF_V_M1_MASK, VLSEG6E16FF_V, 0x0, 0x10 }, // 4822 |
| 12113 | { PseudoVLSEG6E16FF_V_MF4, VLSEG6E16FF_V, 0x6, 0x10 }, // 4823 |
| 12114 | { PseudoVLSEG6E16FF_V_MF4_MASK, VLSEG6E16FF_V, 0x6, 0x10 }, // 4824 |
| 12115 | { PseudoVLSEG6E16FF_V_MF2, VLSEG6E16FF_V, 0x7, 0x10 }, // 4825 |
| 12116 | { PseudoVLSEG6E16FF_V_MF2_MASK, VLSEG6E16FF_V, 0x7, 0x10 }, // 4826 |
| 12117 | { PseudoVLSEG6E16_V_M1, VLSEG6E16_V, 0x0, 0x10 }, // 4827 |
| 12118 | { PseudoVLSEG6E16_V_M1_MASK, VLSEG6E16_V, 0x0, 0x10 }, // 4828 |
| 12119 | { PseudoVLSEG6E16_V_MF4, VLSEG6E16_V, 0x6, 0x10 }, // 4829 |
| 12120 | { PseudoVLSEG6E16_V_MF4_MASK, VLSEG6E16_V, 0x6, 0x10 }, // 4830 |
| 12121 | { PseudoVLSEG6E16_V_MF2, VLSEG6E16_V, 0x7, 0x10 }, // 4831 |
| 12122 | { PseudoVLSEG6E16_V_MF2_MASK, VLSEG6E16_V, 0x7, 0x10 }, // 4832 |
| 12123 | { PseudoVLSEG6E32FF_V_M1, VLSEG6E32FF_V, 0x0, 0x20 }, // 4833 |
| 12124 | { PseudoVLSEG6E32FF_V_M1_MASK, VLSEG6E32FF_V, 0x0, 0x20 }, // 4834 |
| 12125 | { PseudoVLSEG6E32FF_V_MF2, VLSEG6E32FF_V, 0x7, 0x20 }, // 4835 |
| 12126 | { PseudoVLSEG6E32FF_V_MF2_MASK, VLSEG6E32FF_V, 0x7, 0x20 }, // 4836 |
| 12127 | { PseudoVLSEG6E32_V_M1, VLSEG6E32_V, 0x0, 0x20 }, // 4837 |
| 12128 | { PseudoVLSEG6E32_V_M1_MASK, VLSEG6E32_V, 0x0, 0x20 }, // 4838 |
| 12129 | { PseudoVLSEG6E32_V_MF2, VLSEG6E32_V, 0x7, 0x20 }, // 4839 |
| 12130 | { PseudoVLSEG6E32_V_MF2_MASK, VLSEG6E32_V, 0x7, 0x20 }, // 4840 |
| 12131 | { PseudoVLSEG6E64FF_V_M1, VLSEG6E64FF_V, 0x0, 0x40 }, // 4841 |
| 12132 | { PseudoVLSEG6E64FF_V_M1_MASK, VLSEG6E64FF_V, 0x0, 0x40 }, // 4842 |
| 12133 | { PseudoVLSEG6E64_V_M1, VLSEG6E64_V, 0x0, 0x40 }, // 4843 |
| 12134 | { PseudoVLSEG6E64_V_M1_MASK, VLSEG6E64_V, 0x0, 0x40 }, // 4844 |
| 12135 | { PseudoVLSEG6E8FF_V_M1, VLSEG6E8FF_V, 0x0, 0x8 }, // 4845 |
| 12136 | { PseudoVLSEG6E8FF_V_M1_MASK, VLSEG6E8FF_V, 0x0, 0x8 }, // 4846 |
| 12137 | { PseudoVLSEG6E8FF_V_MF8, VLSEG6E8FF_V, 0x5, 0x8 }, // 4847 |
| 12138 | { PseudoVLSEG6E8FF_V_MF8_MASK, VLSEG6E8FF_V, 0x5, 0x8 }, // 4848 |
| 12139 | { PseudoVLSEG6E8FF_V_MF4, VLSEG6E8FF_V, 0x6, 0x8 }, // 4849 |
| 12140 | { PseudoVLSEG6E8FF_V_MF4_MASK, VLSEG6E8FF_V, 0x6, 0x8 }, // 4850 |
| 12141 | { PseudoVLSEG6E8FF_V_MF2, VLSEG6E8FF_V, 0x7, 0x8 }, // 4851 |
| 12142 | { PseudoVLSEG6E8FF_V_MF2_MASK, VLSEG6E8FF_V, 0x7, 0x8 }, // 4852 |
| 12143 | { PseudoVLSEG6E8_V_M1, VLSEG6E8_V, 0x0, 0x8 }, // 4853 |
| 12144 | { PseudoVLSEG6E8_V_M1_MASK, VLSEG6E8_V, 0x0, 0x8 }, // 4854 |
| 12145 | { PseudoVLSEG6E8_V_MF8, VLSEG6E8_V, 0x5, 0x8 }, // 4855 |
| 12146 | { PseudoVLSEG6E8_V_MF8_MASK, VLSEG6E8_V, 0x5, 0x8 }, // 4856 |
| 12147 | { PseudoVLSEG6E8_V_MF4, VLSEG6E8_V, 0x6, 0x8 }, // 4857 |
| 12148 | { PseudoVLSEG6E8_V_MF4_MASK, VLSEG6E8_V, 0x6, 0x8 }, // 4858 |
| 12149 | { PseudoVLSEG6E8_V_MF2, VLSEG6E8_V, 0x7, 0x8 }, // 4859 |
| 12150 | { PseudoVLSEG6E8_V_MF2_MASK, VLSEG6E8_V, 0x7, 0x8 }, // 4860 |
| 12151 | { PseudoVLSEG7E16FF_V_M1, VLSEG7E16FF_V, 0x0, 0x10 }, // 4861 |
| 12152 | { PseudoVLSEG7E16FF_V_M1_MASK, VLSEG7E16FF_V, 0x0, 0x10 }, // 4862 |
| 12153 | { PseudoVLSEG7E16FF_V_MF4, VLSEG7E16FF_V, 0x6, 0x10 }, // 4863 |
| 12154 | { PseudoVLSEG7E16FF_V_MF4_MASK, VLSEG7E16FF_V, 0x6, 0x10 }, // 4864 |
| 12155 | { PseudoVLSEG7E16FF_V_MF2, VLSEG7E16FF_V, 0x7, 0x10 }, // 4865 |
| 12156 | { PseudoVLSEG7E16FF_V_MF2_MASK, VLSEG7E16FF_V, 0x7, 0x10 }, // 4866 |
| 12157 | { PseudoVLSEG7E16_V_M1, VLSEG7E16_V, 0x0, 0x10 }, // 4867 |
| 12158 | { PseudoVLSEG7E16_V_M1_MASK, VLSEG7E16_V, 0x0, 0x10 }, // 4868 |
| 12159 | { PseudoVLSEG7E16_V_MF4, VLSEG7E16_V, 0x6, 0x10 }, // 4869 |
| 12160 | { PseudoVLSEG7E16_V_MF4_MASK, VLSEG7E16_V, 0x6, 0x10 }, // 4870 |
| 12161 | { PseudoVLSEG7E16_V_MF2, VLSEG7E16_V, 0x7, 0x10 }, // 4871 |
| 12162 | { PseudoVLSEG7E16_V_MF2_MASK, VLSEG7E16_V, 0x7, 0x10 }, // 4872 |
| 12163 | { PseudoVLSEG7E32FF_V_M1, VLSEG7E32FF_V, 0x0, 0x20 }, // 4873 |
| 12164 | { PseudoVLSEG7E32FF_V_M1_MASK, VLSEG7E32FF_V, 0x0, 0x20 }, // 4874 |
| 12165 | { PseudoVLSEG7E32FF_V_MF2, VLSEG7E32FF_V, 0x7, 0x20 }, // 4875 |
| 12166 | { PseudoVLSEG7E32FF_V_MF2_MASK, VLSEG7E32FF_V, 0x7, 0x20 }, // 4876 |
| 12167 | { PseudoVLSEG7E32_V_M1, VLSEG7E32_V, 0x0, 0x20 }, // 4877 |
| 12168 | { PseudoVLSEG7E32_V_M1_MASK, VLSEG7E32_V, 0x0, 0x20 }, // 4878 |
| 12169 | { PseudoVLSEG7E32_V_MF2, VLSEG7E32_V, 0x7, 0x20 }, // 4879 |
| 12170 | { PseudoVLSEG7E32_V_MF2_MASK, VLSEG7E32_V, 0x7, 0x20 }, // 4880 |
| 12171 | { PseudoVLSEG7E64FF_V_M1, VLSEG7E64FF_V, 0x0, 0x40 }, // 4881 |
| 12172 | { PseudoVLSEG7E64FF_V_M1_MASK, VLSEG7E64FF_V, 0x0, 0x40 }, // 4882 |
| 12173 | { PseudoVLSEG7E64_V_M1, VLSEG7E64_V, 0x0, 0x40 }, // 4883 |
| 12174 | { PseudoVLSEG7E64_V_M1_MASK, VLSEG7E64_V, 0x0, 0x40 }, // 4884 |
| 12175 | { PseudoVLSEG7E8FF_V_M1, VLSEG7E8FF_V, 0x0, 0x8 }, // 4885 |
| 12176 | { PseudoVLSEG7E8FF_V_M1_MASK, VLSEG7E8FF_V, 0x0, 0x8 }, // 4886 |
| 12177 | { PseudoVLSEG7E8FF_V_MF8, VLSEG7E8FF_V, 0x5, 0x8 }, // 4887 |
| 12178 | { PseudoVLSEG7E8FF_V_MF8_MASK, VLSEG7E8FF_V, 0x5, 0x8 }, // 4888 |
| 12179 | { PseudoVLSEG7E8FF_V_MF4, VLSEG7E8FF_V, 0x6, 0x8 }, // 4889 |
| 12180 | { PseudoVLSEG7E8FF_V_MF4_MASK, VLSEG7E8FF_V, 0x6, 0x8 }, // 4890 |
| 12181 | { PseudoVLSEG7E8FF_V_MF2, VLSEG7E8FF_V, 0x7, 0x8 }, // 4891 |
| 12182 | { PseudoVLSEG7E8FF_V_MF2_MASK, VLSEG7E8FF_V, 0x7, 0x8 }, // 4892 |
| 12183 | { PseudoVLSEG7E8_V_M1, VLSEG7E8_V, 0x0, 0x8 }, // 4893 |
| 12184 | { PseudoVLSEG7E8_V_M1_MASK, VLSEG7E8_V, 0x0, 0x8 }, // 4894 |
| 12185 | { PseudoVLSEG7E8_V_MF8, VLSEG7E8_V, 0x5, 0x8 }, // 4895 |
| 12186 | { PseudoVLSEG7E8_V_MF8_MASK, VLSEG7E8_V, 0x5, 0x8 }, // 4896 |
| 12187 | { PseudoVLSEG7E8_V_MF4, VLSEG7E8_V, 0x6, 0x8 }, // 4897 |
| 12188 | { PseudoVLSEG7E8_V_MF4_MASK, VLSEG7E8_V, 0x6, 0x8 }, // 4898 |
| 12189 | { PseudoVLSEG7E8_V_MF2, VLSEG7E8_V, 0x7, 0x8 }, // 4899 |
| 12190 | { PseudoVLSEG7E8_V_MF2_MASK, VLSEG7E8_V, 0x7, 0x8 }, // 4900 |
| 12191 | { PseudoVLSEG8E16FF_V_M1, VLSEG8E16FF_V, 0x0, 0x10 }, // 4901 |
| 12192 | { PseudoVLSEG8E16FF_V_M1_MASK, VLSEG8E16FF_V, 0x0, 0x10 }, // 4902 |
| 12193 | { PseudoVLSEG8E16FF_V_MF4, VLSEG8E16FF_V, 0x6, 0x10 }, // 4903 |
| 12194 | { PseudoVLSEG8E16FF_V_MF4_MASK, VLSEG8E16FF_V, 0x6, 0x10 }, // 4904 |
| 12195 | { PseudoVLSEG8E16FF_V_MF2, VLSEG8E16FF_V, 0x7, 0x10 }, // 4905 |
| 12196 | { PseudoVLSEG8E16FF_V_MF2_MASK, VLSEG8E16FF_V, 0x7, 0x10 }, // 4906 |
| 12197 | { PseudoVLSEG8E16_V_M1, VLSEG8E16_V, 0x0, 0x10 }, // 4907 |
| 12198 | { PseudoVLSEG8E16_V_M1_MASK, VLSEG8E16_V, 0x0, 0x10 }, // 4908 |
| 12199 | { PseudoVLSEG8E16_V_MF4, VLSEG8E16_V, 0x6, 0x10 }, // 4909 |
| 12200 | { PseudoVLSEG8E16_V_MF4_MASK, VLSEG8E16_V, 0x6, 0x10 }, // 4910 |
| 12201 | { PseudoVLSEG8E16_V_MF2, VLSEG8E16_V, 0x7, 0x10 }, // 4911 |
| 12202 | { PseudoVLSEG8E16_V_MF2_MASK, VLSEG8E16_V, 0x7, 0x10 }, // 4912 |
| 12203 | { PseudoVLSEG8E32FF_V_M1, VLSEG8E32FF_V, 0x0, 0x20 }, // 4913 |
| 12204 | { PseudoVLSEG8E32FF_V_M1_MASK, VLSEG8E32FF_V, 0x0, 0x20 }, // 4914 |
| 12205 | { PseudoVLSEG8E32FF_V_MF2, VLSEG8E32FF_V, 0x7, 0x20 }, // 4915 |
| 12206 | { PseudoVLSEG8E32FF_V_MF2_MASK, VLSEG8E32FF_V, 0x7, 0x20 }, // 4916 |
| 12207 | { PseudoVLSEG8E32_V_M1, VLSEG8E32_V, 0x0, 0x20 }, // 4917 |
| 12208 | { PseudoVLSEG8E32_V_M1_MASK, VLSEG8E32_V, 0x0, 0x20 }, // 4918 |
| 12209 | { PseudoVLSEG8E32_V_MF2, VLSEG8E32_V, 0x7, 0x20 }, // 4919 |
| 12210 | { PseudoVLSEG8E32_V_MF2_MASK, VLSEG8E32_V, 0x7, 0x20 }, // 4920 |
| 12211 | { PseudoVLSEG8E64FF_V_M1, VLSEG8E64FF_V, 0x0, 0x40 }, // 4921 |
| 12212 | { PseudoVLSEG8E64FF_V_M1_MASK, VLSEG8E64FF_V, 0x0, 0x40 }, // 4922 |
| 12213 | { PseudoVLSEG8E64_V_M1, VLSEG8E64_V, 0x0, 0x40 }, // 4923 |
| 12214 | { PseudoVLSEG8E64_V_M1_MASK, VLSEG8E64_V, 0x0, 0x40 }, // 4924 |
| 12215 | { PseudoVLSEG8E8FF_V_M1, VLSEG8E8FF_V, 0x0, 0x8 }, // 4925 |
| 12216 | { PseudoVLSEG8E8FF_V_M1_MASK, VLSEG8E8FF_V, 0x0, 0x8 }, // 4926 |
| 12217 | { PseudoVLSEG8E8FF_V_MF8, VLSEG8E8FF_V, 0x5, 0x8 }, // 4927 |
| 12218 | { PseudoVLSEG8E8FF_V_MF8_MASK, VLSEG8E8FF_V, 0x5, 0x8 }, // 4928 |
| 12219 | { PseudoVLSEG8E8FF_V_MF4, VLSEG8E8FF_V, 0x6, 0x8 }, // 4929 |
| 12220 | { PseudoVLSEG8E8FF_V_MF4_MASK, VLSEG8E8FF_V, 0x6, 0x8 }, // 4930 |
| 12221 | { PseudoVLSEG8E8FF_V_MF2, VLSEG8E8FF_V, 0x7, 0x8 }, // 4931 |
| 12222 | { PseudoVLSEG8E8FF_V_MF2_MASK, VLSEG8E8FF_V, 0x7, 0x8 }, // 4932 |
| 12223 | { PseudoVLSEG8E8_V_M1, VLSEG8E8_V, 0x0, 0x8 }, // 4933 |
| 12224 | { PseudoVLSEG8E8_V_M1_MASK, VLSEG8E8_V, 0x0, 0x8 }, // 4934 |
| 12225 | { PseudoVLSEG8E8_V_MF8, VLSEG8E8_V, 0x5, 0x8 }, // 4935 |
| 12226 | { PseudoVLSEG8E8_V_MF8_MASK, VLSEG8E8_V, 0x5, 0x8 }, // 4936 |
| 12227 | { PseudoVLSEG8E8_V_MF4, VLSEG8E8_V, 0x6, 0x8 }, // 4937 |
| 12228 | { PseudoVLSEG8E8_V_MF4_MASK, VLSEG8E8_V, 0x6, 0x8 }, // 4938 |
| 12229 | { PseudoVLSEG8E8_V_MF2, VLSEG8E8_V, 0x7, 0x8 }, // 4939 |
| 12230 | { PseudoVLSEG8E8_V_MF2_MASK, VLSEG8E8_V, 0x7, 0x8 }, // 4940 |
| 12231 | { PseudoVLSSEG2E16_V_M1, VLSSEG2E16_V, 0x0, 0x10 }, // 4941 |
| 12232 | { PseudoVLSSEG2E16_V_M1_MASK, VLSSEG2E16_V, 0x0, 0x10 }, // 4942 |
| 12233 | { PseudoVLSSEG2E16_V_M2, VLSSEG2E16_V, 0x1, 0x10 }, // 4943 |
| 12234 | { PseudoVLSSEG2E16_V_M2_MASK, VLSSEG2E16_V, 0x1, 0x10 }, // 4944 |
| 12235 | { PseudoVLSSEG2E16_V_M4, VLSSEG2E16_V, 0x2, 0x10 }, // 4945 |
| 12236 | { PseudoVLSSEG2E16_V_M4_MASK, VLSSEG2E16_V, 0x2, 0x10 }, // 4946 |
| 12237 | { PseudoVLSSEG2E16_V_MF4, VLSSEG2E16_V, 0x6, 0x10 }, // 4947 |
| 12238 | { PseudoVLSSEG2E16_V_MF4_MASK, VLSSEG2E16_V, 0x6, 0x10 }, // 4948 |
| 12239 | { PseudoVLSSEG2E16_V_MF2, VLSSEG2E16_V, 0x7, 0x10 }, // 4949 |
| 12240 | { PseudoVLSSEG2E16_V_MF2_MASK, VLSSEG2E16_V, 0x7, 0x10 }, // 4950 |
| 12241 | { PseudoVLSSEG2E32_V_M1, VLSSEG2E32_V, 0x0, 0x20 }, // 4951 |
| 12242 | { PseudoVLSSEG2E32_V_M1_MASK, VLSSEG2E32_V, 0x0, 0x20 }, // 4952 |
| 12243 | { PseudoVLSSEG2E32_V_M2, VLSSEG2E32_V, 0x1, 0x20 }, // 4953 |
| 12244 | { PseudoVLSSEG2E32_V_M2_MASK, VLSSEG2E32_V, 0x1, 0x20 }, // 4954 |
| 12245 | { PseudoVLSSEG2E32_V_M4, VLSSEG2E32_V, 0x2, 0x20 }, // 4955 |
| 12246 | { PseudoVLSSEG2E32_V_M4_MASK, VLSSEG2E32_V, 0x2, 0x20 }, // 4956 |
| 12247 | { PseudoVLSSEG2E32_V_MF2, VLSSEG2E32_V, 0x7, 0x20 }, // 4957 |
| 12248 | { PseudoVLSSEG2E32_V_MF2_MASK, VLSSEG2E32_V, 0x7, 0x20 }, // 4958 |
| 12249 | { PseudoVLSSEG2E64_V_M1, VLSSEG2E64_V, 0x0, 0x40 }, // 4959 |
| 12250 | { PseudoVLSSEG2E64_V_M1_MASK, VLSSEG2E64_V, 0x0, 0x40 }, // 4960 |
| 12251 | { PseudoVLSSEG2E64_V_M2, VLSSEG2E64_V, 0x1, 0x40 }, // 4961 |
| 12252 | { PseudoVLSSEG2E64_V_M2_MASK, VLSSEG2E64_V, 0x1, 0x40 }, // 4962 |
| 12253 | { PseudoVLSSEG2E64_V_M4, VLSSEG2E64_V, 0x2, 0x40 }, // 4963 |
| 12254 | { PseudoVLSSEG2E64_V_M4_MASK, VLSSEG2E64_V, 0x2, 0x40 }, // 4964 |
| 12255 | { PseudoVLSSEG2E8_V_M1, VLSSEG2E8_V, 0x0, 0x8 }, // 4965 |
| 12256 | { PseudoVLSSEG2E8_V_M1_MASK, VLSSEG2E8_V, 0x0, 0x8 }, // 4966 |
| 12257 | { PseudoVLSSEG2E8_V_M2, VLSSEG2E8_V, 0x1, 0x8 }, // 4967 |
| 12258 | { PseudoVLSSEG2E8_V_M2_MASK, VLSSEG2E8_V, 0x1, 0x8 }, // 4968 |
| 12259 | { PseudoVLSSEG2E8_V_M4, VLSSEG2E8_V, 0x2, 0x8 }, // 4969 |
| 12260 | { PseudoVLSSEG2E8_V_M4_MASK, VLSSEG2E8_V, 0x2, 0x8 }, // 4970 |
| 12261 | { PseudoVLSSEG2E8_V_MF8, VLSSEG2E8_V, 0x5, 0x8 }, // 4971 |
| 12262 | { PseudoVLSSEG2E8_V_MF8_MASK, VLSSEG2E8_V, 0x5, 0x8 }, // 4972 |
| 12263 | { PseudoVLSSEG2E8_V_MF4, VLSSEG2E8_V, 0x6, 0x8 }, // 4973 |
| 12264 | { PseudoVLSSEG2E8_V_MF4_MASK, VLSSEG2E8_V, 0x6, 0x8 }, // 4974 |
| 12265 | { PseudoVLSSEG2E8_V_MF2, VLSSEG2E8_V, 0x7, 0x8 }, // 4975 |
| 12266 | { PseudoVLSSEG2E8_V_MF2_MASK, VLSSEG2E8_V, 0x7, 0x8 }, // 4976 |
| 12267 | { PseudoVLSSEG3E16_V_M1, VLSSEG3E16_V, 0x0, 0x10 }, // 4977 |
| 12268 | { PseudoVLSSEG3E16_V_M1_MASK, VLSSEG3E16_V, 0x0, 0x10 }, // 4978 |
| 12269 | { PseudoVLSSEG3E16_V_M2, VLSSEG3E16_V, 0x1, 0x10 }, // 4979 |
| 12270 | { PseudoVLSSEG3E16_V_M2_MASK, VLSSEG3E16_V, 0x1, 0x10 }, // 4980 |
| 12271 | { PseudoVLSSEG3E16_V_MF4, VLSSEG3E16_V, 0x6, 0x10 }, // 4981 |
| 12272 | { PseudoVLSSEG3E16_V_MF4_MASK, VLSSEG3E16_V, 0x6, 0x10 }, // 4982 |
| 12273 | { PseudoVLSSEG3E16_V_MF2, VLSSEG3E16_V, 0x7, 0x10 }, // 4983 |
| 12274 | { PseudoVLSSEG3E16_V_MF2_MASK, VLSSEG3E16_V, 0x7, 0x10 }, // 4984 |
| 12275 | { PseudoVLSSEG3E32_V_M1, VLSSEG3E32_V, 0x0, 0x20 }, // 4985 |
| 12276 | { PseudoVLSSEG3E32_V_M1_MASK, VLSSEG3E32_V, 0x0, 0x20 }, // 4986 |
| 12277 | { PseudoVLSSEG3E32_V_M2, VLSSEG3E32_V, 0x1, 0x20 }, // 4987 |
| 12278 | { PseudoVLSSEG3E32_V_M2_MASK, VLSSEG3E32_V, 0x1, 0x20 }, // 4988 |
| 12279 | { PseudoVLSSEG3E32_V_MF2, VLSSEG3E32_V, 0x7, 0x20 }, // 4989 |
| 12280 | { PseudoVLSSEG3E32_V_MF2_MASK, VLSSEG3E32_V, 0x7, 0x20 }, // 4990 |
| 12281 | { PseudoVLSSEG3E64_V_M1, VLSSEG3E64_V, 0x0, 0x40 }, // 4991 |
| 12282 | { PseudoVLSSEG3E64_V_M1_MASK, VLSSEG3E64_V, 0x0, 0x40 }, // 4992 |
| 12283 | { PseudoVLSSEG3E64_V_M2, VLSSEG3E64_V, 0x1, 0x40 }, // 4993 |
| 12284 | { PseudoVLSSEG3E64_V_M2_MASK, VLSSEG3E64_V, 0x1, 0x40 }, // 4994 |
| 12285 | { PseudoVLSSEG3E8_V_M1, VLSSEG3E8_V, 0x0, 0x8 }, // 4995 |
| 12286 | { PseudoVLSSEG3E8_V_M1_MASK, VLSSEG3E8_V, 0x0, 0x8 }, // 4996 |
| 12287 | { PseudoVLSSEG3E8_V_M2, VLSSEG3E8_V, 0x1, 0x8 }, // 4997 |
| 12288 | { PseudoVLSSEG3E8_V_M2_MASK, VLSSEG3E8_V, 0x1, 0x8 }, // 4998 |
| 12289 | { PseudoVLSSEG3E8_V_MF8, VLSSEG3E8_V, 0x5, 0x8 }, // 4999 |
| 12290 | { PseudoVLSSEG3E8_V_MF8_MASK, VLSSEG3E8_V, 0x5, 0x8 }, // 5000 |
| 12291 | { PseudoVLSSEG3E8_V_MF4, VLSSEG3E8_V, 0x6, 0x8 }, // 5001 |
| 12292 | { PseudoVLSSEG3E8_V_MF4_MASK, VLSSEG3E8_V, 0x6, 0x8 }, // 5002 |
| 12293 | { PseudoVLSSEG3E8_V_MF2, VLSSEG3E8_V, 0x7, 0x8 }, // 5003 |
| 12294 | { PseudoVLSSEG3E8_V_MF2_MASK, VLSSEG3E8_V, 0x7, 0x8 }, // 5004 |
| 12295 | { PseudoVLSSEG4E16_V_M1, VLSSEG4E16_V, 0x0, 0x10 }, // 5005 |
| 12296 | { PseudoVLSSEG4E16_V_M1_MASK, VLSSEG4E16_V, 0x0, 0x10 }, // 5006 |
| 12297 | { PseudoVLSSEG4E16_V_M2, VLSSEG4E16_V, 0x1, 0x10 }, // 5007 |
| 12298 | { PseudoVLSSEG4E16_V_M2_MASK, VLSSEG4E16_V, 0x1, 0x10 }, // 5008 |
| 12299 | { PseudoVLSSEG4E16_V_MF4, VLSSEG4E16_V, 0x6, 0x10 }, // 5009 |
| 12300 | { PseudoVLSSEG4E16_V_MF4_MASK, VLSSEG4E16_V, 0x6, 0x10 }, // 5010 |
| 12301 | { PseudoVLSSEG4E16_V_MF2, VLSSEG4E16_V, 0x7, 0x10 }, // 5011 |
| 12302 | { PseudoVLSSEG4E16_V_MF2_MASK, VLSSEG4E16_V, 0x7, 0x10 }, // 5012 |
| 12303 | { PseudoVLSSEG4E32_V_M1, VLSSEG4E32_V, 0x0, 0x20 }, // 5013 |
| 12304 | { PseudoVLSSEG4E32_V_M1_MASK, VLSSEG4E32_V, 0x0, 0x20 }, // 5014 |
| 12305 | { PseudoVLSSEG4E32_V_M2, VLSSEG4E32_V, 0x1, 0x20 }, // 5015 |
| 12306 | { PseudoVLSSEG4E32_V_M2_MASK, VLSSEG4E32_V, 0x1, 0x20 }, // 5016 |
| 12307 | { PseudoVLSSEG4E32_V_MF2, VLSSEG4E32_V, 0x7, 0x20 }, // 5017 |
| 12308 | { PseudoVLSSEG4E32_V_MF2_MASK, VLSSEG4E32_V, 0x7, 0x20 }, // 5018 |
| 12309 | { PseudoVLSSEG4E64_V_M1, VLSSEG4E64_V, 0x0, 0x40 }, // 5019 |
| 12310 | { PseudoVLSSEG4E64_V_M1_MASK, VLSSEG4E64_V, 0x0, 0x40 }, // 5020 |
| 12311 | { PseudoVLSSEG4E64_V_M2, VLSSEG4E64_V, 0x1, 0x40 }, // 5021 |
| 12312 | { PseudoVLSSEG4E64_V_M2_MASK, VLSSEG4E64_V, 0x1, 0x40 }, // 5022 |
| 12313 | { PseudoVLSSEG4E8_V_M1, VLSSEG4E8_V, 0x0, 0x8 }, // 5023 |
| 12314 | { PseudoVLSSEG4E8_V_M1_MASK, VLSSEG4E8_V, 0x0, 0x8 }, // 5024 |
| 12315 | { PseudoVLSSEG4E8_V_M2, VLSSEG4E8_V, 0x1, 0x8 }, // 5025 |
| 12316 | { PseudoVLSSEG4E8_V_M2_MASK, VLSSEG4E8_V, 0x1, 0x8 }, // 5026 |
| 12317 | { PseudoVLSSEG4E8_V_MF8, VLSSEG4E8_V, 0x5, 0x8 }, // 5027 |
| 12318 | { PseudoVLSSEG4E8_V_MF8_MASK, VLSSEG4E8_V, 0x5, 0x8 }, // 5028 |
| 12319 | { PseudoVLSSEG4E8_V_MF4, VLSSEG4E8_V, 0x6, 0x8 }, // 5029 |
| 12320 | { PseudoVLSSEG4E8_V_MF4_MASK, VLSSEG4E8_V, 0x6, 0x8 }, // 5030 |
| 12321 | { PseudoVLSSEG4E8_V_MF2, VLSSEG4E8_V, 0x7, 0x8 }, // 5031 |
| 12322 | { PseudoVLSSEG4E8_V_MF2_MASK, VLSSEG4E8_V, 0x7, 0x8 }, // 5032 |
| 12323 | { PseudoVLSSEG5E16_V_M1, VLSSEG5E16_V, 0x0, 0x10 }, // 5033 |
| 12324 | { PseudoVLSSEG5E16_V_M1_MASK, VLSSEG5E16_V, 0x0, 0x10 }, // 5034 |
| 12325 | { PseudoVLSSEG5E16_V_MF4, VLSSEG5E16_V, 0x6, 0x10 }, // 5035 |
| 12326 | { PseudoVLSSEG5E16_V_MF4_MASK, VLSSEG5E16_V, 0x6, 0x10 }, // 5036 |
| 12327 | { PseudoVLSSEG5E16_V_MF2, VLSSEG5E16_V, 0x7, 0x10 }, // 5037 |
| 12328 | { PseudoVLSSEG5E16_V_MF2_MASK, VLSSEG5E16_V, 0x7, 0x10 }, // 5038 |
| 12329 | { PseudoVLSSEG5E32_V_M1, VLSSEG5E32_V, 0x0, 0x20 }, // 5039 |
| 12330 | { PseudoVLSSEG5E32_V_M1_MASK, VLSSEG5E32_V, 0x0, 0x20 }, // 5040 |
| 12331 | { PseudoVLSSEG5E32_V_MF2, VLSSEG5E32_V, 0x7, 0x20 }, // 5041 |
| 12332 | { PseudoVLSSEG5E32_V_MF2_MASK, VLSSEG5E32_V, 0x7, 0x20 }, // 5042 |
| 12333 | { PseudoVLSSEG5E64_V_M1, VLSSEG5E64_V, 0x0, 0x40 }, // 5043 |
| 12334 | { PseudoVLSSEG5E64_V_M1_MASK, VLSSEG5E64_V, 0x0, 0x40 }, // 5044 |
| 12335 | { PseudoVLSSEG5E8_V_M1, VLSSEG5E8_V, 0x0, 0x8 }, // 5045 |
| 12336 | { PseudoVLSSEG5E8_V_M1_MASK, VLSSEG5E8_V, 0x0, 0x8 }, // 5046 |
| 12337 | { PseudoVLSSEG5E8_V_MF8, VLSSEG5E8_V, 0x5, 0x8 }, // 5047 |
| 12338 | { PseudoVLSSEG5E8_V_MF8_MASK, VLSSEG5E8_V, 0x5, 0x8 }, // 5048 |
| 12339 | { PseudoVLSSEG5E8_V_MF4, VLSSEG5E8_V, 0x6, 0x8 }, // 5049 |
| 12340 | { PseudoVLSSEG5E8_V_MF4_MASK, VLSSEG5E8_V, 0x6, 0x8 }, // 5050 |
| 12341 | { PseudoVLSSEG5E8_V_MF2, VLSSEG5E8_V, 0x7, 0x8 }, // 5051 |
| 12342 | { PseudoVLSSEG5E8_V_MF2_MASK, VLSSEG5E8_V, 0x7, 0x8 }, // 5052 |
| 12343 | { PseudoVLSSEG6E16_V_M1, VLSSEG6E16_V, 0x0, 0x10 }, // 5053 |
| 12344 | { PseudoVLSSEG6E16_V_M1_MASK, VLSSEG6E16_V, 0x0, 0x10 }, // 5054 |
| 12345 | { PseudoVLSSEG6E16_V_MF4, VLSSEG6E16_V, 0x6, 0x10 }, // 5055 |
| 12346 | { PseudoVLSSEG6E16_V_MF4_MASK, VLSSEG6E16_V, 0x6, 0x10 }, // 5056 |
| 12347 | { PseudoVLSSEG6E16_V_MF2, VLSSEG6E16_V, 0x7, 0x10 }, // 5057 |
| 12348 | { PseudoVLSSEG6E16_V_MF2_MASK, VLSSEG6E16_V, 0x7, 0x10 }, // 5058 |
| 12349 | { PseudoVLSSEG6E32_V_M1, VLSSEG6E32_V, 0x0, 0x20 }, // 5059 |
| 12350 | { PseudoVLSSEG6E32_V_M1_MASK, VLSSEG6E32_V, 0x0, 0x20 }, // 5060 |
| 12351 | { PseudoVLSSEG6E32_V_MF2, VLSSEG6E32_V, 0x7, 0x20 }, // 5061 |
| 12352 | { PseudoVLSSEG6E32_V_MF2_MASK, VLSSEG6E32_V, 0x7, 0x20 }, // 5062 |
| 12353 | { PseudoVLSSEG6E64_V_M1, VLSSEG6E64_V, 0x0, 0x40 }, // 5063 |
| 12354 | { PseudoVLSSEG6E64_V_M1_MASK, VLSSEG6E64_V, 0x0, 0x40 }, // 5064 |
| 12355 | { PseudoVLSSEG6E8_V_M1, VLSSEG6E8_V, 0x0, 0x8 }, // 5065 |
| 12356 | { PseudoVLSSEG6E8_V_M1_MASK, VLSSEG6E8_V, 0x0, 0x8 }, // 5066 |
| 12357 | { PseudoVLSSEG6E8_V_MF8, VLSSEG6E8_V, 0x5, 0x8 }, // 5067 |
| 12358 | { PseudoVLSSEG6E8_V_MF8_MASK, VLSSEG6E8_V, 0x5, 0x8 }, // 5068 |
| 12359 | { PseudoVLSSEG6E8_V_MF4, VLSSEG6E8_V, 0x6, 0x8 }, // 5069 |
| 12360 | { PseudoVLSSEG6E8_V_MF4_MASK, VLSSEG6E8_V, 0x6, 0x8 }, // 5070 |
| 12361 | { PseudoVLSSEG6E8_V_MF2, VLSSEG6E8_V, 0x7, 0x8 }, // 5071 |
| 12362 | { PseudoVLSSEG6E8_V_MF2_MASK, VLSSEG6E8_V, 0x7, 0x8 }, // 5072 |
| 12363 | { PseudoVLSSEG7E16_V_M1, VLSSEG7E16_V, 0x0, 0x10 }, // 5073 |
| 12364 | { PseudoVLSSEG7E16_V_M1_MASK, VLSSEG7E16_V, 0x0, 0x10 }, // 5074 |
| 12365 | { PseudoVLSSEG7E16_V_MF4, VLSSEG7E16_V, 0x6, 0x10 }, // 5075 |
| 12366 | { PseudoVLSSEG7E16_V_MF4_MASK, VLSSEG7E16_V, 0x6, 0x10 }, // 5076 |
| 12367 | { PseudoVLSSEG7E16_V_MF2, VLSSEG7E16_V, 0x7, 0x10 }, // 5077 |
| 12368 | { PseudoVLSSEG7E16_V_MF2_MASK, VLSSEG7E16_V, 0x7, 0x10 }, // 5078 |
| 12369 | { PseudoVLSSEG7E32_V_M1, VLSSEG7E32_V, 0x0, 0x20 }, // 5079 |
| 12370 | { PseudoVLSSEG7E32_V_M1_MASK, VLSSEG7E32_V, 0x0, 0x20 }, // 5080 |
| 12371 | { PseudoVLSSEG7E32_V_MF2, VLSSEG7E32_V, 0x7, 0x20 }, // 5081 |
| 12372 | { PseudoVLSSEG7E32_V_MF2_MASK, VLSSEG7E32_V, 0x7, 0x20 }, // 5082 |
| 12373 | { PseudoVLSSEG7E64_V_M1, VLSSEG7E64_V, 0x0, 0x40 }, // 5083 |
| 12374 | { PseudoVLSSEG7E64_V_M1_MASK, VLSSEG7E64_V, 0x0, 0x40 }, // 5084 |
| 12375 | { PseudoVLSSEG7E8_V_M1, VLSSEG7E8_V, 0x0, 0x8 }, // 5085 |
| 12376 | { PseudoVLSSEG7E8_V_M1_MASK, VLSSEG7E8_V, 0x0, 0x8 }, // 5086 |
| 12377 | { PseudoVLSSEG7E8_V_MF8, VLSSEG7E8_V, 0x5, 0x8 }, // 5087 |
| 12378 | { PseudoVLSSEG7E8_V_MF8_MASK, VLSSEG7E8_V, 0x5, 0x8 }, // 5088 |
| 12379 | { PseudoVLSSEG7E8_V_MF4, VLSSEG7E8_V, 0x6, 0x8 }, // 5089 |
| 12380 | { PseudoVLSSEG7E8_V_MF4_MASK, VLSSEG7E8_V, 0x6, 0x8 }, // 5090 |
| 12381 | { PseudoVLSSEG7E8_V_MF2, VLSSEG7E8_V, 0x7, 0x8 }, // 5091 |
| 12382 | { PseudoVLSSEG7E8_V_MF2_MASK, VLSSEG7E8_V, 0x7, 0x8 }, // 5092 |
| 12383 | { PseudoVLSSEG8E16_V_M1, VLSSEG8E16_V, 0x0, 0x10 }, // 5093 |
| 12384 | { PseudoVLSSEG8E16_V_M1_MASK, VLSSEG8E16_V, 0x0, 0x10 }, // 5094 |
| 12385 | { PseudoVLSSEG8E16_V_MF4, VLSSEG8E16_V, 0x6, 0x10 }, // 5095 |
| 12386 | { PseudoVLSSEG8E16_V_MF4_MASK, VLSSEG8E16_V, 0x6, 0x10 }, // 5096 |
| 12387 | { PseudoVLSSEG8E16_V_MF2, VLSSEG8E16_V, 0x7, 0x10 }, // 5097 |
| 12388 | { PseudoVLSSEG8E16_V_MF2_MASK, VLSSEG8E16_V, 0x7, 0x10 }, // 5098 |
| 12389 | { PseudoVLSSEG8E32_V_M1, VLSSEG8E32_V, 0x0, 0x20 }, // 5099 |
| 12390 | { PseudoVLSSEG8E32_V_M1_MASK, VLSSEG8E32_V, 0x0, 0x20 }, // 5100 |
| 12391 | { PseudoVLSSEG8E32_V_MF2, VLSSEG8E32_V, 0x7, 0x20 }, // 5101 |
| 12392 | { PseudoVLSSEG8E32_V_MF2_MASK, VLSSEG8E32_V, 0x7, 0x20 }, // 5102 |
| 12393 | { PseudoVLSSEG8E64_V_M1, VLSSEG8E64_V, 0x0, 0x40 }, // 5103 |
| 12394 | { PseudoVLSSEG8E64_V_M1_MASK, VLSSEG8E64_V, 0x0, 0x40 }, // 5104 |
| 12395 | { PseudoVLSSEG8E8_V_M1, VLSSEG8E8_V, 0x0, 0x8 }, // 5105 |
| 12396 | { PseudoVLSSEG8E8_V_M1_MASK, VLSSEG8E8_V, 0x0, 0x8 }, // 5106 |
| 12397 | { PseudoVLSSEG8E8_V_MF8, VLSSEG8E8_V, 0x5, 0x8 }, // 5107 |
| 12398 | { PseudoVLSSEG8E8_V_MF8_MASK, VLSSEG8E8_V, 0x5, 0x8 }, // 5108 |
| 12399 | { PseudoVLSSEG8E8_V_MF4, VLSSEG8E8_V, 0x6, 0x8 }, // 5109 |
| 12400 | { PseudoVLSSEG8E8_V_MF4_MASK, VLSSEG8E8_V, 0x6, 0x8 }, // 5110 |
| 12401 | { PseudoVLSSEG8E8_V_MF2, VLSSEG8E8_V, 0x7, 0x8 }, // 5111 |
| 12402 | { PseudoVLSSEG8E8_V_MF2_MASK, VLSSEG8E8_V, 0x7, 0x8 }, // 5112 |
| 12403 | { PseudoVLUXEI16_V_M1_M1, VLUXEI16_V, 0x0, 0x0 }, // 5113 |
| 12404 | { PseudoVLUXEI16_V_M1_M1_MASK, VLUXEI16_V, 0x0, 0x0 }, // 5114 |
| 12405 | { PseudoVLUXEI16_V_M2_M1, VLUXEI16_V, 0x0, 0x0 }, // 5115 |
| 12406 | { PseudoVLUXEI16_V_M2_M1_MASK, VLUXEI16_V, 0x0, 0x0 }, // 5116 |
| 12407 | { PseudoVLUXEI16_V_MF2_M1, VLUXEI16_V, 0x0, 0x0 }, // 5117 |
| 12408 | { PseudoVLUXEI16_V_MF2_M1_MASK, VLUXEI16_V, 0x0, 0x0 }, // 5118 |
| 12409 | { PseudoVLUXEI16_V_MF4_M1, VLUXEI16_V, 0x0, 0x0 }, // 5119 |
| 12410 | { PseudoVLUXEI16_V_MF4_M1_MASK, VLUXEI16_V, 0x0, 0x0 }, // 5120 |
| 12411 | { PseudoVLUXEI16_V_M1_M2, VLUXEI16_V, 0x1, 0x0 }, // 5121 |
| 12412 | { PseudoVLUXEI16_V_M1_M2_MASK, VLUXEI16_V, 0x1, 0x0 }, // 5122 |
| 12413 | { PseudoVLUXEI16_V_M2_M2, VLUXEI16_V, 0x1, 0x0 }, // 5123 |
| 12414 | { PseudoVLUXEI16_V_M2_M2_MASK, VLUXEI16_V, 0x1, 0x0 }, // 5124 |
| 12415 | { PseudoVLUXEI16_V_M4_M2, VLUXEI16_V, 0x1, 0x0 }, // 5125 |
| 12416 | { PseudoVLUXEI16_V_M4_M2_MASK, VLUXEI16_V, 0x1, 0x0 }, // 5126 |
| 12417 | { PseudoVLUXEI16_V_MF2_M2, VLUXEI16_V, 0x1, 0x0 }, // 5127 |
| 12418 | { PseudoVLUXEI16_V_MF2_M2_MASK, VLUXEI16_V, 0x1, 0x0 }, // 5128 |
| 12419 | { PseudoVLUXEI16_V_M1_M4, VLUXEI16_V, 0x2, 0x0 }, // 5129 |
| 12420 | { PseudoVLUXEI16_V_M1_M4_MASK, VLUXEI16_V, 0x2, 0x0 }, // 5130 |
| 12421 | { PseudoVLUXEI16_V_M2_M4, VLUXEI16_V, 0x2, 0x0 }, // 5131 |
| 12422 | { PseudoVLUXEI16_V_M2_M4_MASK, VLUXEI16_V, 0x2, 0x0 }, // 5132 |
| 12423 | { PseudoVLUXEI16_V_M4_M4, VLUXEI16_V, 0x2, 0x0 }, // 5133 |
| 12424 | { PseudoVLUXEI16_V_M4_M4_MASK, VLUXEI16_V, 0x2, 0x0 }, // 5134 |
| 12425 | { PseudoVLUXEI16_V_M8_M4, VLUXEI16_V, 0x2, 0x0 }, // 5135 |
| 12426 | { PseudoVLUXEI16_V_M8_M4_MASK, VLUXEI16_V, 0x2, 0x0 }, // 5136 |
| 12427 | { PseudoVLUXEI16_V_M2_M8, VLUXEI16_V, 0x3, 0x0 }, // 5137 |
| 12428 | { PseudoVLUXEI16_V_M2_M8_MASK, VLUXEI16_V, 0x3, 0x0 }, // 5138 |
| 12429 | { PseudoVLUXEI16_V_M4_M8, VLUXEI16_V, 0x3, 0x0 }, // 5139 |
| 12430 | { PseudoVLUXEI16_V_M4_M8_MASK, VLUXEI16_V, 0x3, 0x0 }, // 5140 |
| 12431 | { PseudoVLUXEI16_V_M8_M8, VLUXEI16_V, 0x3, 0x0 }, // 5141 |
| 12432 | { PseudoVLUXEI16_V_M8_M8_MASK, VLUXEI16_V, 0x3, 0x0 }, // 5142 |
| 12433 | { PseudoVLUXEI16_V_MF4_MF8, VLUXEI16_V, 0x5, 0x0 }, // 5143 |
| 12434 | { PseudoVLUXEI16_V_MF4_MF8_MASK, VLUXEI16_V, 0x5, 0x0 }, // 5144 |
| 12435 | { PseudoVLUXEI16_V_MF2_MF4, VLUXEI16_V, 0x6, 0x0 }, // 5145 |
| 12436 | { PseudoVLUXEI16_V_MF2_MF4_MASK, VLUXEI16_V, 0x6, 0x0 }, // 5146 |
| 12437 | { PseudoVLUXEI16_V_MF4_MF4, VLUXEI16_V, 0x6, 0x0 }, // 5147 |
| 12438 | { PseudoVLUXEI16_V_MF4_MF4_MASK, VLUXEI16_V, 0x6, 0x0 }, // 5148 |
| 12439 | { PseudoVLUXEI16_V_M1_MF2, VLUXEI16_V, 0x7, 0x0 }, // 5149 |
| 12440 | { PseudoVLUXEI16_V_M1_MF2_MASK, VLUXEI16_V, 0x7, 0x0 }, // 5150 |
| 12441 | { PseudoVLUXEI16_V_MF2_MF2, VLUXEI16_V, 0x7, 0x0 }, // 5151 |
| 12442 | { PseudoVLUXEI16_V_MF2_MF2_MASK, VLUXEI16_V, 0x7, 0x0 }, // 5152 |
| 12443 | { PseudoVLUXEI16_V_MF4_MF2, VLUXEI16_V, 0x7, 0x0 }, // 5153 |
| 12444 | { PseudoVLUXEI16_V_MF4_MF2_MASK, VLUXEI16_V, 0x7, 0x0 }, // 5154 |
| 12445 | { PseudoVLUXEI32_V_M1_M1, VLUXEI32_V, 0x0, 0x0 }, // 5155 |
| 12446 | { PseudoVLUXEI32_V_M1_M1_MASK, VLUXEI32_V, 0x0, 0x0 }, // 5156 |
| 12447 | { PseudoVLUXEI32_V_M2_M1, VLUXEI32_V, 0x0, 0x0 }, // 5157 |
| 12448 | { PseudoVLUXEI32_V_M2_M1_MASK, VLUXEI32_V, 0x0, 0x0 }, // 5158 |
| 12449 | { PseudoVLUXEI32_V_M4_M1, VLUXEI32_V, 0x0, 0x0 }, // 5159 |
| 12450 | { PseudoVLUXEI32_V_M4_M1_MASK, VLUXEI32_V, 0x0, 0x0 }, // 5160 |
| 12451 | { PseudoVLUXEI32_V_MF2_M1, VLUXEI32_V, 0x0, 0x0 }, // 5161 |
| 12452 | { PseudoVLUXEI32_V_MF2_M1_MASK, VLUXEI32_V, 0x0, 0x0 }, // 5162 |
| 12453 | { PseudoVLUXEI32_V_M1_M2, VLUXEI32_V, 0x1, 0x0 }, // 5163 |
| 12454 | { PseudoVLUXEI32_V_M1_M2_MASK, VLUXEI32_V, 0x1, 0x0 }, // 5164 |
| 12455 | { PseudoVLUXEI32_V_M2_M2, VLUXEI32_V, 0x1, 0x0 }, // 5165 |
| 12456 | { PseudoVLUXEI32_V_M2_M2_MASK, VLUXEI32_V, 0x1, 0x0 }, // 5166 |
| 12457 | { PseudoVLUXEI32_V_M4_M2, VLUXEI32_V, 0x1, 0x0 }, // 5167 |
| 12458 | { PseudoVLUXEI32_V_M4_M2_MASK, VLUXEI32_V, 0x1, 0x0 }, // 5168 |
| 12459 | { PseudoVLUXEI32_V_M8_M2, VLUXEI32_V, 0x1, 0x0 }, // 5169 |
| 12460 | { PseudoVLUXEI32_V_M8_M2_MASK, VLUXEI32_V, 0x1, 0x0 }, // 5170 |
| 12461 | { PseudoVLUXEI32_V_M2_M4, VLUXEI32_V, 0x2, 0x0 }, // 5171 |
| 12462 | { PseudoVLUXEI32_V_M2_M4_MASK, VLUXEI32_V, 0x2, 0x0 }, // 5172 |
| 12463 | { PseudoVLUXEI32_V_M4_M4, VLUXEI32_V, 0x2, 0x0 }, // 5173 |
| 12464 | { PseudoVLUXEI32_V_M4_M4_MASK, VLUXEI32_V, 0x2, 0x0 }, // 5174 |
| 12465 | { PseudoVLUXEI32_V_M8_M4, VLUXEI32_V, 0x2, 0x0 }, // 5175 |
| 12466 | { PseudoVLUXEI32_V_M8_M4_MASK, VLUXEI32_V, 0x2, 0x0 }, // 5176 |
| 12467 | { PseudoVLUXEI32_V_M4_M8, VLUXEI32_V, 0x3, 0x0 }, // 5177 |
| 12468 | { PseudoVLUXEI32_V_M4_M8_MASK, VLUXEI32_V, 0x3, 0x0 }, // 5178 |
| 12469 | { PseudoVLUXEI32_V_M8_M8, VLUXEI32_V, 0x3, 0x0 }, // 5179 |
| 12470 | { PseudoVLUXEI32_V_M8_M8_MASK, VLUXEI32_V, 0x3, 0x0 }, // 5180 |
| 12471 | { PseudoVLUXEI32_V_MF2_MF8, VLUXEI32_V, 0x5, 0x0 }, // 5181 |
| 12472 | { PseudoVLUXEI32_V_MF2_MF8_MASK, VLUXEI32_V, 0x5, 0x0 }, // 5182 |
| 12473 | { PseudoVLUXEI32_V_M1_MF4, VLUXEI32_V, 0x6, 0x0 }, // 5183 |
| 12474 | { PseudoVLUXEI32_V_M1_MF4_MASK, VLUXEI32_V, 0x6, 0x0 }, // 5184 |
| 12475 | { PseudoVLUXEI32_V_MF2_MF4, VLUXEI32_V, 0x6, 0x0 }, // 5185 |
| 12476 | { PseudoVLUXEI32_V_MF2_MF4_MASK, VLUXEI32_V, 0x6, 0x0 }, // 5186 |
| 12477 | { PseudoVLUXEI32_V_M1_MF2, VLUXEI32_V, 0x7, 0x0 }, // 5187 |
| 12478 | { PseudoVLUXEI32_V_M1_MF2_MASK, VLUXEI32_V, 0x7, 0x0 }, // 5188 |
| 12479 | { PseudoVLUXEI32_V_M2_MF2, VLUXEI32_V, 0x7, 0x0 }, // 5189 |
| 12480 | { PseudoVLUXEI32_V_M2_MF2_MASK, VLUXEI32_V, 0x7, 0x0 }, // 5190 |
| 12481 | { PseudoVLUXEI32_V_MF2_MF2, VLUXEI32_V, 0x7, 0x0 }, // 5191 |
| 12482 | { PseudoVLUXEI32_V_MF2_MF2_MASK, VLUXEI32_V, 0x7, 0x0 }, // 5192 |
| 12483 | { PseudoVLUXEI64_V_M1_M1, VLUXEI64_V, 0x0, 0x0 }, // 5193 |
| 12484 | { PseudoVLUXEI64_V_M1_M1_MASK, VLUXEI64_V, 0x0, 0x0 }, // 5194 |
| 12485 | { PseudoVLUXEI64_V_M2_M1, VLUXEI64_V, 0x0, 0x0 }, // 5195 |
| 12486 | { PseudoVLUXEI64_V_M2_M1_MASK, VLUXEI64_V, 0x0, 0x0 }, // 5196 |
| 12487 | { PseudoVLUXEI64_V_M4_M1, VLUXEI64_V, 0x0, 0x0 }, // 5197 |
| 12488 | { PseudoVLUXEI64_V_M4_M1_MASK, VLUXEI64_V, 0x0, 0x0 }, // 5198 |
| 12489 | { PseudoVLUXEI64_V_M8_M1, VLUXEI64_V, 0x0, 0x0 }, // 5199 |
| 12490 | { PseudoVLUXEI64_V_M8_M1_MASK, VLUXEI64_V, 0x0, 0x0 }, // 5200 |
| 12491 | { PseudoVLUXEI64_V_M2_M2, VLUXEI64_V, 0x1, 0x0 }, // 5201 |
| 12492 | { PseudoVLUXEI64_V_M2_M2_MASK, VLUXEI64_V, 0x1, 0x0 }, // 5202 |
| 12493 | { PseudoVLUXEI64_V_M4_M2, VLUXEI64_V, 0x1, 0x0 }, // 5203 |
| 12494 | { PseudoVLUXEI64_V_M4_M2_MASK, VLUXEI64_V, 0x1, 0x0 }, // 5204 |
| 12495 | { PseudoVLUXEI64_V_M8_M2, VLUXEI64_V, 0x1, 0x0 }, // 5205 |
| 12496 | { PseudoVLUXEI64_V_M8_M2_MASK, VLUXEI64_V, 0x1, 0x0 }, // 5206 |
| 12497 | { PseudoVLUXEI64_V_M4_M4, VLUXEI64_V, 0x2, 0x0 }, // 5207 |
| 12498 | { PseudoVLUXEI64_V_M4_M4_MASK, VLUXEI64_V, 0x2, 0x0 }, // 5208 |
| 12499 | { PseudoVLUXEI64_V_M8_M4, VLUXEI64_V, 0x2, 0x0 }, // 5209 |
| 12500 | { PseudoVLUXEI64_V_M8_M4_MASK, VLUXEI64_V, 0x2, 0x0 }, // 5210 |
| 12501 | { PseudoVLUXEI64_V_M8_M8, VLUXEI64_V, 0x3, 0x0 }, // 5211 |
| 12502 | { PseudoVLUXEI64_V_M8_M8_MASK, VLUXEI64_V, 0x3, 0x0 }, // 5212 |
| 12503 | { PseudoVLUXEI64_V_M1_MF8, VLUXEI64_V, 0x5, 0x0 }, // 5213 |
| 12504 | { PseudoVLUXEI64_V_M1_MF8_MASK, VLUXEI64_V, 0x5, 0x0 }, // 5214 |
| 12505 | { PseudoVLUXEI64_V_M1_MF4, VLUXEI64_V, 0x6, 0x0 }, // 5215 |
| 12506 | { PseudoVLUXEI64_V_M1_MF4_MASK, VLUXEI64_V, 0x6, 0x0 }, // 5216 |
| 12507 | { PseudoVLUXEI64_V_M2_MF4, VLUXEI64_V, 0x6, 0x0 }, // 5217 |
| 12508 | { PseudoVLUXEI64_V_M2_MF4_MASK, VLUXEI64_V, 0x6, 0x0 }, // 5218 |
| 12509 | { PseudoVLUXEI64_V_M1_MF2, VLUXEI64_V, 0x7, 0x0 }, // 5219 |
| 12510 | { PseudoVLUXEI64_V_M1_MF2_MASK, VLUXEI64_V, 0x7, 0x0 }, // 5220 |
| 12511 | { PseudoVLUXEI64_V_M2_MF2, VLUXEI64_V, 0x7, 0x0 }, // 5221 |
| 12512 | { PseudoVLUXEI64_V_M2_MF2_MASK, VLUXEI64_V, 0x7, 0x0 }, // 5222 |
| 12513 | { PseudoVLUXEI64_V_M4_MF2, VLUXEI64_V, 0x7, 0x0 }, // 5223 |
| 12514 | { PseudoVLUXEI64_V_M4_MF2_MASK, VLUXEI64_V, 0x7, 0x0 }, // 5224 |
| 12515 | { PseudoVLUXEI8_V_M1_M1, VLUXEI8_V, 0x0, 0x0 }, // 5225 |
| 12516 | { PseudoVLUXEI8_V_M1_M1_MASK, VLUXEI8_V, 0x0, 0x0 }, // 5226 |
| 12517 | { PseudoVLUXEI8_V_MF2_M1, VLUXEI8_V, 0x0, 0x0 }, // 5227 |
| 12518 | { PseudoVLUXEI8_V_MF2_M1_MASK, VLUXEI8_V, 0x0, 0x0 }, // 5228 |
| 12519 | { PseudoVLUXEI8_V_MF4_M1, VLUXEI8_V, 0x0, 0x0 }, // 5229 |
| 12520 | { PseudoVLUXEI8_V_MF4_M1_MASK, VLUXEI8_V, 0x0, 0x0 }, // 5230 |
| 12521 | { PseudoVLUXEI8_V_MF8_M1, VLUXEI8_V, 0x0, 0x0 }, // 5231 |
| 12522 | { PseudoVLUXEI8_V_MF8_M1_MASK, VLUXEI8_V, 0x0, 0x0 }, // 5232 |
| 12523 | { PseudoVLUXEI8_V_M1_M2, VLUXEI8_V, 0x1, 0x0 }, // 5233 |
| 12524 | { PseudoVLUXEI8_V_M1_M2_MASK, VLUXEI8_V, 0x1, 0x0 }, // 5234 |
| 12525 | { PseudoVLUXEI8_V_M2_M2, VLUXEI8_V, 0x1, 0x0 }, // 5235 |
| 12526 | { PseudoVLUXEI8_V_M2_M2_MASK, VLUXEI8_V, 0x1, 0x0 }, // 5236 |
| 12527 | { PseudoVLUXEI8_V_MF2_M2, VLUXEI8_V, 0x1, 0x0 }, // 5237 |
| 12528 | { PseudoVLUXEI8_V_MF2_M2_MASK, VLUXEI8_V, 0x1, 0x0 }, // 5238 |
| 12529 | { PseudoVLUXEI8_V_MF4_M2, VLUXEI8_V, 0x1, 0x0 }, // 5239 |
| 12530 | { PseudoVLUXEI8_V_MF4_M2_MASK, VLUXEI8_V, 0x1, 0x0 }, // 5240 |
| 12531 | { PseudoVLUXEI8_V_M1_M4, VLUXEI8_V, 0x2, 0x0 }, // 5241 |
| 12532 | { PseudoVLUXEI8_V_M1_M4_MASK, VLUXEI8_V, 0x2, 0x0 }, // 5242 |
| 12533 | { PseudoVLUXEI8_V_M2_M4, VLUXEI8_V, 0x2, 0x0 }, // 5243 |
| 12534 | { PseudoVLUXEI8_V_M2_M4_MASK, VLUXEI8_V, 0x2, 0x0 }, // 5244 |
| 12535 | { PseudoVLUXEI8_V_M4_M4, VLUXEI8_V, 0x2, 0x0 }, // 5245 |
| 12536 | { PseudoVLUXEI8_V_M4_M4_MASK, VLUXEI8_V, 0x2, 0x0 }, // 5246 |
| 12537 | { PseudoVLUXEI8_V_MF2_M4, VLUXEI8_V, 0x2, 0x0 }, // 5247 |
| 12538 | { PseudoVLUXEI8_V_MF2_M4_MASK, VLUXEI8_V, 0x2, 0x0 }, // 5248 |
| 12539 | { PseudoVLUXEI8_V_M1_M8, VLUXEI8_V, 0x3, 0x0 }, // 5249 |
| 12540 | { PseudoVLUXEI8_V_M1_M8_MASK, VLUXEI8_V, 0x3, 0x0 }, // 5250 |
| 12541 | { PseudoVLUXEI8_V_M2_M8, VLUXEI8_V, 0x3, 0x0 }, // 5251 |
| 12542 | { PseudoVLUXEI8_V_M2_M8_MASK, VLUXEI8_V, 0x3, 0x0 }, // 5252 |
| 12543 | { PseudoVLUXEI8_V_M4_M8, VLUXEI8_V, 0x3, 0x0 }, // 5253 |
| 12544 | { PseudoVLUXEI8_V_M4_M8_MASK, VLUXEI8_V, 0x3, 0x0 }, // 5254 |
| 12545 | { PseudoVLUXEI8_V_M8_M8, VLUXEI8_V, 0x3, 0x0 }, // 5255 |
| 12546 | { PseudoVLUXEI8_V_M8_M8_MASK, VLUXEI8_V, 0x3, 0x0 }, // 5256 |
| 12547 | { PseudoVLUXEI8_V_MF8_MF8, VLUXEI8_V, 0x5, 0x0 }, // 5257 |
| 12548 | { PseudoVLUXEI8_V_MF8_MF8_MASK, VLUXEI8_V, 0x5, 0x0 }, // 5258 |
| 12549 | { PseudoVLUXEI8_V_MF4_MF4, VLUXEI8_V, 0x6, 0x0 }, // 5259 |
| 12550 | { PseudoVLUXEI8_V_MF4_MF4_MASK, VLUXEI8_V, 0x6, 0x0 }, // 5260 |
| 12551 | { PseudoVLUXEI8_V_MF8_MF4, VLUXEI8_V, 0x6, 0x0 }, // 5261 |
| 12552 | { PseudoVLUXEI8_V_MF8_MF4_MASK, VLUXEI8_V, 0x6, 0x0 }, // 5262 |
| 12553 | { PseudoVLUXEI8_V_MF2_MF2, VLUXEI8_V, 0x7, 0x0 }, // 5263 |
| 12554 | { PseudoVLUXEI8_V_MF2_MF2_MASK, VLUXEI8_V, 0x7, 0x0 }, // 5264 |
| 12555 | { PseudoVLUXEI8_V_MF4_MF2, VLUXEI8_V, 0x7, 0x0 }, // 5265 |
| 12556 | { PseudoVLUXEI8_V_MF4_MF2_MASK, VLUXEI8_V, 0x7, 0x0 }, // 5266 |
| 12557 | { PseudoVLUXEI8_V_MF8_MF2, VLUXEI8_V, 0x7, 0x0 }, // 5267 |
| 12558 | { PseudoVLUXEI8_V_MF8_MF2_MASK, VLUXEI8_V, 0x7, 0x0 }, // 5268 |
| 12559 | { PseudoVLUXSEG2EI16_V_M1_M1, VLUXSEG2EI16_V, 0x0, 0x0 }, // 5269 |
| 12560 | { PseudoVLUXSEG2EI16_V_M1_M1_MASK, VLUXSEG2EI16_V, 0x0, 0x0 }, // 5270 |
| 12561 | { PseudoVLUXSEG2EI16_V_M2_M1, VLUXSEG2EI16_V, 0x0, 0x0 }, // 5271 |
| 12562 | { PseudoVLUXSEG2EI16_V_M2_M1_MASK, VLUXSEG2EI16_V, 0x0, 0x0 }, // 5272 |
| 12563 | { PseudoVLUXSEG2EI16_V_MF2_M1, VLUXSEG2EI16_V, 0x0, 0x0 }, // 5273 |
| 12564 | { PseudoVLUXSEG2EI16_V_MF2_M1_MASK, VLUXSEG2EI16_V, 0x0, 0x0 }, // 5274 |
| 12565 | { PseudoVLUXSEG2EI16_V_MF4_M1, VLUXSEG2EI16_V, 0x0, 0x0 }, // 5275 |
| 12566 | { PseudoVLUXSEG2EI16_V_MF4_M1_MASK, VLUXSEG2EI16_V, 0x0, 0x0 }, // 5276 |
| 12567 | { PseudoVLUXSEG2EI16_V_M1_M2, VLUXSEG2EI16_V, 0x1, 0x0 }, // 5277 |
| 12568 | { PseudoVLUXSEG2EI16_V_M1_M2_MASK, VLUXSEG2EI16_V, 0x1, 0x0 }, // 5278 |
| 12569 | { PseudoVLUXSEG2EI16_V_M2_M2, VLUXSEG2EI16_V, 0x1, 0x0 }, // 5279 |
| 12570 | { PseudoVLUXSEG2EI16_V_M2_M2_MASK, VLUXSEG2EI16_V, 0x1, 0x0 }, // 5280 |
| 12571 | { PseudoVLUXSEG2EI16_V_M4_M2, VLUXSEG2EI16_V, 0x1, 0x0 }, // 5281 |
| 12572 | { PseudoVLUXSEG2EI16_V_M4_M2_MASK, VLUXSEG2EI16_V, 0x1, 0x0 }, // 5282 |
| 12573 | { PseudoVLUXSEG2EI16_V_MF2_M2, VLUXSEG2EI16_V, 0x1, 0x0 }, // 5283 |
| 12574 | { PseudoVLUXSEG2EI16_V_MF2_M2_MASK, VLUXSEG2EI16_V, 0x1, 0x0 }, // 5284 |
| 12575 | { PseudoVLUXSEG2EI16_V_M1_M4, VLUXSEG2EI16_V, 0x2, 0x0 }, // 5285 |
| 12576 | { PseudoVLUXSEG2EI16_V_M1_M4_MASK, VLUXSEG2EI16_V, 0x2, 0x0 }, // 5286 |
| 12577 | { PseudoVLUXSEG2EI16_V_M2_M4, VLUXSEG2EI16_V, 0x2, 0x0 }, // 5287 |
| 12578 | { PseudoVLUXSEG2EI16_V_M2_M4_MASK, VLUXSEG2EI16_V, 0x2, 0x0 }, // 5288 |
| 12579 | { PseudoVLUXSEG2EI16_V_M4_M4, VLUXSEG2EI16_V, 0x2, 0x0 }, // 5289 |
| 12580 | { PseudoVLUXSEG2EI16_V_M4_M4_MASK, VLUXSEG2EI16_V, 0x2, 0x0 }, // 5290 |
| 12581 | { PseudoVLUXSEG2EI16_V_M8_M4, VLUXSEG2EI16_V, 0x2, 0x0 }, // 5291 |
| 12582 | { PseudoVLUXSEG2EI16_V_M8_M4_MASK, VLUXSEG2EI16_V, 0x2, 0x0 }, // 5292 |
| 12583 | { PseudoVLUXSEG2EI16_V_MF4_MF8, VLUXSEG2EI16_V, 0x5, 0x0 }, // 5293 |
| 12584 | { PseudoVLUXSEG2EI16_V_MF4_MF8_MASK, VLUXSEG2EI16_V, 0x5, 0x0 }, // 5294 |
| 12585 | { PseudoVLUXSEG2EI16_V_MF2_MF4, VLUXSEG2EI16_V, 0x6, 0x0 }, // 5295 |
| 12586 | { PseudoVLUXSEG2EI16_V_MF2_MF4_MASK, VLUXSEG2EI16_V, 0x6, 0x0 }, // 5296 |
| 12587 | { PseudoVLUXSEG2EI16_V_MF4_MF4, VLUXSEG2EI16_V, 0x6, 0x0 }, // 5297 |
| 12588 | { PseudoVLUXSEG2EI16_V_MF4_MF4_MASK, VLUXSEG2EI16_V, 0x6, 0x0 }, // 5298 |
| 12589 | { PseudoVLUXSEG2EI16_V_M1_MF2, VLUXSEG2EI16_V, 0x7, 0x0 }, // 5299 |
| 12590 | { PseudoVLUXSEG2EI16_V_M1_MF2_MASK, VLUXSEG2EI16_V, 0x7, 0x0 }, // 5300 |
| 12591 | { PseudoVLUXSEG2EI16_V_MF2_MF2, VLUXSEG2EI16_V, 0x7, 0x0 }, // 5301 |
| 12592 | { PseudoVLUXSEG2EI16_V_MF2_MF2_MASK, VLUXSEG2EI16_V, 0x7, 0x0 }, // 5302 |
| 12593 | { PseudoVLUXSEG2EI16_V_MF4_MF2, VLUXSEG2EI16_V, 0x7, 0x0 }, // 5303 |
| 12594 | { PseudoVLUXSEG2EI16_V_MF4_MF2_MASK, VLUXSEG2EI16_V, 0x7, 0x0 }, // 5304 |
| 12595 | { PseudoVLUXSEG2EI32_V_M1_M1, VLUXSEG2EI32_V, 0x0, 0x0 }, // 5305 |
| 12596 | { PseudoVLUXSEG2EI32_V_M1_M1_MASK, VLUXSEG2EI32_V, 0x0, 0x0 }, // 5306 |
| 12597 | { PseudoVLUXSEG2EI32_V_M2_M1, VLUXSEG2EI32_V, 0x0, 0x0 }, // 5307 |
| 12598 | { PseudoVLUXSEG2EI32_V_M2_M1_MASK, VLUXSEG2EI32_V, 0x0, 0x0 }, // 5308 |
| 12599 | { PseudoVLUXSEG2EI32_V_M4_M1, VLUXSEG2EI32_V, 0x0, 0x0 }, // 5309 |
| 12600 | { PseudoVLUXSEG2EI32_V_M4_M1_MASK, VLUXSEG2EI32_V, 0x0, 0x0 }, // 5310 |
| 12601 | { PseudoVLUXSEG2EI32_V_MF2_M1, VLUXSEG2EI32_V, 0x0, 0x0 }, // 5311 |
| 12602 | { PseudoVLUXSEG2EI32_V_MF2_M1_MASK, VLUXSEG2EI32_V, 0x0, 0x0 }, // 5312 |
| 12603 | { PseudoVLUXSEG2EI32_V_M1_M2, VLUXSEG2EI32_V, 0x1, 0x0 }, // 5313 |
| 12604 | { PseudoVLUXSEG2EI32_V_M1_M2_MASK, VLUXSEG2EI32_V, 0x1, 0x0 }, // 5314 |
| 12605 | { PseudoVLUXSEG2EI32_V_M2_M2, VLUXSEG2EI32_V, 0x1, 0x0 }, // 5315 |
| 12606 | { PseudoVLUXSEG2EI32_V_M2_M2_MASK, VLUXSEG2EI32_V, 0x1, 0x0 }, // 5316 |
| 12607 | { PseudoVLUXSEG2EI32_V_M4_M2, VLUXSEG2EI32_V, 0x1, 0x0 }, // 5317 |
| 12608 | { PseudoVLUXSEG2EI32_V_M4_M2_MASK, VLUXSEG2EI32_V, 0x1, 0x0 }, // 5318 |
| 12609 | { PseudoVLUXSEG2EI32_V_M8_M2, VLUXSEG2EI32_V, 0x1, 0x0 }, // 5319 |
| 12610 | { PseudoVLUXSEG2EI32_V_M8_M2_MASK, VLUXSEG2EI32_V, 0x1, 0x0 }, // 5320 |
| 12611 | { PseudoVLUXSEG2EI32_V_M2_M4, VLUXSEG2EI32_V, 0x2, 0x0 }, // 5321 |
| 12612 | { PseudoVLUXSEG2EI32_V_M2_M4_MASK, VLUXSEG2EI32_V, 0x2, 0x0 }, // 5322 |
| 12613 | { PseudoVLUXSEG2EI32_V_M4_M4, VLUXSEG2EI32_V, 0x2, 0x0 }, // 5323 |
| 12614 | { PseudoVLUXSEG2EI32_V_M4_M4_MASK, VLUXSEG2EI32_V, 0x2, 0x0 }, // 5324 |
| 12615 | { PseudoVLUXSEG2EI32_V_M8_M4, VLUXSEG2EI32_V, 0x2, 0x0 }, // 5325 |
| 12616 | { PseudoVLUXSEG2EI32_V_M8_M4_MASK, VLUXSEG2EI32_V, 0x2, 0x0 }, // 5326 |
| 12617 | { PseudoVLUXSEG2EI32_V_MF2_MF8, VLUXSEG2EI32_V, 0x5, 0x0 }, // 5327 |
| 12618 | { PseudoVLUXSEG2EI32_V_MF2_MF8_MASK, VLUXSEG2EI32_V, 0x5, 0x0 }, // 5328 |
| 12619 | { PseudoVLUXSEG2EI32_V_M1_MF4, VLUXSEG2EI32_V, 0x6, 0x0 }, // 5329 |
| 12620 | { PseudoVLUXSEG2EI32_V_M1_MF4_MASK, VLUXSEG2EI32_V, 0x6, 0x0 }, // 5330 |
| 12621 | { PseudoVLUXSEG2EI32_V_MF2_MF4, VLUXSEG2EI32_V, 0x6, 0x0 }, // 5331 |
| 12622 | { PseudoVLUXSEG2EI32_V_MF2_MF4_MASK, VLUXSEG2EI32_V, 0x6, 0x0 }, // 5332 |
| 12623 | { PseudoVLUXSEG2EI32_V_M1_MF2, VLUXSEG2EI32_V, 0x7, 0x0 }, // 5333 |
| 12624 | { PseudoVLUXSEG2EI32_V_M1_MF2_MASK, VLUXSEG2EI32_V, 0x7, 0x0 }, // 5334 |
| 12625 | { PseudoVLUXSEG2EI32_V_M2_MF2, VLUXSEG2EI32_V, 0x7, 0x0 }, // 5335 |
| 12626 | { PseudoVLUXSEG2EI32_V_M2_MF2_MASK, VLUXSEG2EI32_V, 0x7, 0x0 }, // 5336 |
| 12627 | { PseudoVLUXSEG2EI32_V_MF2_MF2, VLUXSEG2EI32_V, 0x7, 0x0 }, // 5337 |
| 12628 | { PseudoVLUXSEG2EI32_V_MF2_MF2_MASK, VLUXSEG2EI32_V, 0x7, 0x0 }, // 5338 |
| 12629 | { PseudoVLUXSEG2EI64_V_M1_M1, VLUXSEG2EI64_V, 0x0, 0x0 }, // 5339 |
| 12630 | { PseudoVLUXSEG2EI64_V_M1_M1_MASK, VLUXSEG2EI64_V, 0x0, 0x0 }, // 5340 |
| 12631 | { PseudoVLUXSEG2EI64_V_M2_M1, VLUXSEG2EI64_V, 0x0, 0x0 }, // 5341 |
| 12632 | { PseudoVLUXSEG2EI64_V_M2_M1_MASK, VLUXSEG2EI64_V, 0x0, 0x0 }, // 5342 |
| 12633 | { PseudoVLUXSEG2EI64_V_M4_M1, VLUXSEG2EI64_V, 0x0, 0x0 }, // 5343 |
| 12634 | { PseudoVLUXSEG2EI64_V_M4_M1_MASK, VLUXSEG2EI64_V, 0x0, 0x0 }, // 5344 |
| 12635 | { PseudoVLUXSEG2EI64_V_M8_M1, VLUXSEG2EI64_V, 0x0, 0x0 }, // 5345 |
| 12636 | { PseudoVLUXSEG2EI64_V_M8_M1_MASK, VLUXSEG2EI64_V, 0x0, 0x0 }, // 5346 |
| 12637 | { PseudoVLUXSEG2EI64_V_M2_M2, VLUXSEG2EI64_V, 0x1, 0x0 }, // 5347 |
| 12638 | { PseudoVLUXSEG2EI64_V_M2_M2_MASK, VLUXSEG2EI64_V, 0x1, 0x0 }, // 5348 |
| 12639 | { PseudoVLUXSEG2EI64_V_M4_M2, VLUXSEG2EI64_V, 0x1, 0x0 }, // 5349 |
| 12640 | { PseudoVLUXSEG2EI64_V_M4_M2_MASK, VLUXSEG2EI64_V, 0x1, 0x0 }, // 5350 |
| 12641 | { PseudoVLUXSEG2EI64_V_M8_M2, VLUXSEG2EI64_V, 0x1, 0x0 }, // 5351 |
| 12642 | { PseudoVLUXSEG2EI64_V_M8_M2_MASK, VLUXSEG2EI64_V, 0x1, 0x0 }, // 5352 |
| 12643 | { PseudoVLUXSEG2EI64_V_M4_M4, VLUXSEG2EI64_V, 0x2, 0x0 }, // 5353 |
| 12644 | { PseudoVLUXSEG2EI64_V_M4_M4_MASK, VLUXSEG2EI64_V, 0x2, 0x0 }, // 5354 |
| 12645 | { PseudoVLUXSEG2EI64_V_M8_M4, VLUXSEG2EI64_V, 0x2, 0x0 }, // 5355 |
| 12646 | { PseudoVLUXSEG2EI64_V_M8_M4_MASK, VLUXSEG2EI64_V, 0x2, 0x0 }, // 5356 |
| 12647 | { PseudoVLUXSEG2EI64_V_M1_MF8, VLUXSEG2EI64_V, 0x5, 0x0 }, // 5357 |
| 12648 | { PseudoVLUXSEG2EI64_V_M1_MF8_MASK, VLUXSEG2EI64_V, 0x5, 0x0 }, // 5358 |
| 12649 | { PseudoVLUXSEG2EI64_V_M1_MF4, VLUXSEG2EI64_V, 0x6, 0x0 }, // 5359 |
| 12650 | { PseudoVLUXSEG2EI64_V_M1_MF4_MASK, VLUXSEG2EI64_V, 0x6, 0x0 }, // 5360 |
| 12651 | { PseudoVLUXSEG2EI64_V_M2_MF4, VLUXSEG2EI64_V, 0x6, 0x0 }, // 5361 |
| 12652 | { PseudoVLUXSEG2EI64_V_M2_MF4_MASK, VLUXSEG2EI64_V, 0x6, 0x0 }, // 5362 |
| 12653 | { PseudoVLUXSEG2EI64_V_M1_MF2, VLUXSEG2EI64_V, 0x7, 0x0 }, // 5363 |
| 12654 | { PseudoVLUXSEG2EI64_V_M1_MF2_MASK, VLUXSEG2EI64_V, 0x7, 0x0 }, // 5364 |
| 12655 | { PseudoVLUXSEG2EI64_V_M2_MF2, VLUXSEG2EI64_V, 0x7, 0x0 }, // 5365 |
| 12656 | { PseudoVLUXSEG2EI64_V_M2_MF2_MASK, VLUXSEG2EI64_V, 0x7, 0x0 }, // 5366 |
| 12657 | { PseudoVLUXSEG2EI64_V_M4_MF2, VLUXSEG2EI64_V, 0x7, 0x0 }, // 5367 |
| 12658 | { PseudoVLUXSEG2EI64_V_M4_MF2_MASK, VLUXSEG2EI64_V, 0x7, 0x0 }, // 5368 |
| 12659 | { PseudoVLUXSEG2EI8_V_M1_M1, VLUXSEG2EI8_V, 0x0, 0x0 }, // 5369 |
| 12660 | { PseudoVLUXSEG2EI8_V_M1_M1_MASK, VLUXSEG2EI8_V, 0x0, 0x0 }, // 5370 |
| 12661 | { PseudoVLUXSEG2EI8_V_MF2_M1, VLUXSEG2EI8_V, 0x0, 0x0 }, // 5371 |
| 12662 | { PseudoVLUXSEG2EI8_V_MF2_M1_MASK, VLUXSEG2EI8_V, 0x0, 0x0 }, // 5372 |
| 12663 | { PseudoVLUXSEG2EI8_V_MF4_M1, VLUXSEG2EI8_V, 0x0, 0x0 }, // 5373 |
| 12664 | { PseudoVLUXSEG2EI8_V_MF4_M1_MASK, VLUXSEG2EI8_V, 0x0, 0x0 }, // 5374 |
| 12665 | { PseudoVLUXSEG2EI8_V_MF8_M1, VLUXSEG2EI8_V, 0x0, 0x0 }, // 5375 |
| 12666 | { PseudoVLUXSEG2EI8_V_MF8_M1_MASK, VLUXSEG2EI8_V, 0x0, 0x0 }, // 5376 |
| 12667 | { PseudoVLUXSEG2EI8_V_M1_M2, VLUXSEG2EI8_V, 0x1, 0x0 }, // 5377 |
| 12668 | { PseudoVLUXSEG2EI8_V_M1_M2_MASK, VLUXSEG2EI8_V, 0x1, 0x0 }, // 5378 |
| 12669 | { PseudoVLUXSEG2EI8_V_M2_M2, VLUXSEG2EI8_V, 0x1, 0x0 }, // 5379 |
| 12670 | { PseudoVLUXSEG2EI8_V_M2_M2_MASK, VLUXSEG2EI8_V, 0x1, 0x0 }, // 5380 |
| 12671 | { PseudoVLUXSEG2EI8_V_MF2_M2, VLUXSEG2EI8_V, 0x1, 0x0 }, // 5381 |
| 12672 | { PseudoVLUXSEG2EI8_V_MF2_M2_MASK, VLUXSEG2EI8_V, 0x1, 0x0 }, // 5382 |
| 12673 | { PseudoVLUXSEG2EI8_V_MF4_M2, VLUXSEG2EI8_V, 0x1, 0x0 }, // 5383 |
| 12674 | { PseudoVLUXSEG2EI8_V_MF4_M2_MASK, VLUXSEG2EI8_V, 0x1, 0x0 }, // 5384 |
| 12675 | { PseudoVLUXSEG2EI8_V_M1_M4, VLUXSEG2EI8_V, 0x2, 0x0 }, // 5385 |
| 12676 | { PseudoVLUXSEG2EI8_V_M1_M4_MASK, VLUXSEG2EI8_V, 0x2, 0x0 }, // 5386 |
| 12677 | { PseudoVLUXSEG2EI8_V_M2_M4, VLUXSEG2EI8_V, 0x2, 0x0 }, // 5387 |
| 12678 | { PseudoVLUXSEG2EI8_V_M2_M4_MASK, VLUXSEG2EI8_V, 0x2, 0x0 }, // 5388 |
| 12679 | { PseudoVLUXSEG2EI8_V_M4_M4, VLUXSEG2EI8_V, 0x2, 0x0 }, // 5389 |
| 12680 | { PseudoVLUXSEG2EI8_V_M4_M4_MASK, VLUXSEG2EI8_V, 0x2, 0x0 }, // 5390 |
| 12681 | { PseudoVLUXSEG2EI8_V_MF2_M4, VLUXSEG2EI8_V, 0x2, 0x0 }, // 5391 |
| 12682 | { PseudoVLUXSEG2EI8_V_MF2_M4_MASK, VLUXSEG2EI8_V, 0x2, 0x0 }, // 5392 |
| 12683 | { PseudoVLUXSEG2EI8_V_MF8_MF8, VLUXSEG2EI8_V, 0x5, 0x0 }, // 5393 |
| 12684 | { PseudoVLUXSEG2EI8_V_MF8_MF8_MASK, VLUXSEG2EI8_V, 0x5, 0x0 }, // 5394 |
| 12685 | { PseudoVLUXSEG2EI8_V_MF4_MF4, VLUXSEG2EI8_V, 0x6, 0x0 }, // 5395 |
| 12686 | { PseudoVLUXSEG2EI8_V_MF4_MF4_MASK, VLUXSEG2EI8_V, 0x6, 0x0 }, // 5396 |
| 12687 | { PseudoVLUXSEG2EI8_V_MF8_MF4, VLUXSEG2EI8_V, 0x6, 0x0 }, // 5397 |
| 12688 | { PseudoVLUXSEG2EI8_V_MF8_MF4_MASK, VLUXSEG2EI8_V, 0x6, 0x0 }, // 5398 |
| 12689 | { PseudoVLUXSEG2EI8_V_MF2_MF2, VLUXSEG2EI8_V, 0x7, 0x0 }, // 5399 |
| 12690 | { PseudoVLUXSEG2EI8_V_MF2_MF2_MASK, VLUXSEG2EI8_V, 0x7, 0x0 }, // 5400 |
| 12691 | { PseudoVLUXSEG2EI8_V_MF4_MF2, VLUXSEG2EI8_V, 0x7, 0x0 }, // 5401 |
| 12692 | { PseudoVLUXSEG2EI8_V_MF4_MF2_MASK, VLUXSEG2EI8_V, 0x7, 0x0 }, // 5402 |
| 12693 | { PseudoVLUXSEG2EI8_V_MF8_MF2, VLUXSEG2EI8_V, 0x7, 0x0 }, // 5403 |
| 12694 | { PseudoVLUXSEG2EI8_V_MF8_MF2_MASK, VLUXSEG2EI8_V, 0x7, 0x0 }, // 5404 |
| 12695 | { PseudoVLUXSEG3EI16_V_M1_M1, VLUXSEG3EI16_V, 0x0, 0x0 }, // 5405 |
| 12696 | { PseudoVLUXSEG3EI16_V_M1_M1_MASK, VLUXSEG3EI16_V, 0x0, 0x0 }, // 5406 |
| 12697 | { PseudoVLUXSEG3EI16_V_M2_M1, VLUXSEG3EI16_V, 0x0, 0x0 }, // 5407 |
| 12698 | { PseudoVLUXSEG3EI16_V_M2_M1_MASK, VLUXSEG3EI16_V, 0x0, 0x0 }, // 5408 |
| 12699 | { PseudoVLUXSEG3EI16_V_MF2_M1, VLUXSEG3EI16_V, 0x0, 0x0 }, // 5409 |
| 12700 | { PseudoVLUXSEG3EI16_V_MF2_M1_MASK, VLUXSEG3EI16_V, 0x0, 0x0 }, // 5410 |
| 12701 | { PseudoVLUXSEG3EI16_V_MF4_M1, VLUXSEG3EI16_V, 0x0, 0x0 }, // 5411 |
| 12702 | { PseudoVLUXSEG3EI16_V_MF4_M1_MASK, VLUXSEG3EI16_V, 0x0, 0x0 }, // 5412 |
| 12703 | { PseudoVLUXSEG3EI16_V_M1_M2, VLUXSEG3EI16_V, 0x1, 0x0 }, // 5413 |
| 12704 | { PseudoVLUXSEG3EI16_V_M1_M2_MASK, VLUXSEG3EI16_V, 0x1, 0x0 }, // 5414 |
| 12705 | { PseudoVLUXSEG3EI16_V_M2_M2, VLUXSEG3EI16_V, 0x1, 0x0 }, // 5415 |
| 12706 | { PseudoVLUXSEG3EI16_V_M2_M2_MASK, VLUXSEG3EI16_V, 0x1, 0x0 }, // 5416 |
| 12707 | { PseudoVLUXSEG3EI16_V_M4_M2, VLUXSEG3EI16_V, 0x1, 0x0 }, // 5417 |
| 12708 | { PseudoVLUXSEG3EI16_V_M4_M2_MASK, VLUXSEG3EI16_V, 0x1, 0x0 }, // 5418 |
| 12709 | { PseudoVLUXSEG3EI16_V_MF2_M2, VLUXSEG3EI16_V, 0x1, 0x0 }, // 5419 |
| 12710 | { PseudoVLUXSEG3EI16_V_MF2_M2_MASK, VLUXSEG3EI16_V, 0x1, 0x0 }, // 5420 |
| 12711 | { PseudoVLUXSEG3EI16_V_MF4_MF8, VLUXSEG3EI16_V, 0x5, 0x0 }, // 5421 |
| 12712 | { PseudoVLUXSEG3EI16_V_MF4_MF8_MASK, VLUXSEG3EI16_V, 0x5, 0x0 }, // 5422 |
| 12713 | { PseudoVLUXSEG3EI16_V_MF2_MF4, VLUXSEG3EI16_V, 0x6, 0x0 }, // 5423 |
| 12714 | { PseudoVLUXSEG3EI16_V_MF2_MF4_MASK, VLUXSEG3EI16_V, 0x6, 0x0 }, // 5424 |
| 12715 | { PseudoVLUXSEG3EI16_V_MF4_MF4, VLUXSEG3EI16_V, 0x6, 0x0 }, // 5425 |
| 12716 | { PseudoVLUXSEG3EI16_V_MF4_MF4_MASK, VLUXSEG3EI16_V, 0x6, 0x0 }, // 5426 |
| 12717 | { PseudoVLUXSEG3EI16_V_M1_MF2, VLUXSEG3EI16_V, 0x7, 0x0 }, // 5427 |
| 12718 | { PseudoVLUXSEG3EI16_V_M1_MF2_MASK, VLUXSEG3EI16_V, 0x7, 0x0 }, // 5428 |
| 12719 | { PseudoVLUXSEG3EI16_V_MF2_MF2, VLUXSEG3EI16_V, 0x7, 0x0 }, // 5429 |
| 12720 | { PseudoVLUXSEG3EI16_V_MF2_MF2_MASK, VLUXSEG3EI16_V, 0x7, 0x0 }, // 5430 |
| 12721 | { PseudoVLUXSEG3EI16_V_MF4_MF2, VLUXSEG3EI16_V, 0x7, 0x0 }, // 5431 |
| 12722 | { PseudoVLUXSEG3EI16_V_MF4_MF2_MASK, VLUXSEG3EI16_V, 0x7, 0x0 }, // 5432 |
| 12723 | { PseudoVLUXSEG3EI32_V_M1_M1, VLUXSEG3EI32_V, 0x0, 0x0 }, // 5433 |
| 12724 | { PseudoVLUXSEG3EI32_V_M1_M1_MASK, VLUXSEG3EI32_V, 0x0, 0x0 }, // 5434 |
| 12725 | { PseudoVLUXSEG3EI32_V_M2_M1, VLUXSEG3EI32_V, 0x0, 0x0 }, // 5435 |
| 12726 | { PseudoVLUXSEG3EI32_V_M2_M1_MASK, VLUXSEG3EI32_V, 0x0, 0x0 }, // 5436 |
| 12727 | { PseudoVLUXSEG3EI32_V_M4_M1, VLUXSEG3EI32_V, 0x0, 0x0 }, // 5437 |
| 12728 | { PseudoVLUXSEG3EI32_V_M4_M1_MASK, VLUXSEG3EI32_V, 0x0, 0x0 }, // 5438 |
| 12729 | { PseudoVLUXSEG3EI32_V_MF2_M1, VLUXSEG3EI32_V, 0x0, 0x0 }, // 5439 |
| 12730 | { PseudoVLUXSEG3EI32_V_MF2_M1_MASK, VLUXSEG3EI32_V, 0x0, 0x0 }, // 5440 |
| 12731 | { PseudoVLUXSEG3EI32_V_M1_M2, VLUXSEG3EI32_V, 0x1, 0x0 }, // 5441 |
| 12732 | { PseudoVLUXSEG3EI32_V_M1_M2_MASK, VLUXSEG3EI32_V, 0x1, 0x0 }, // 5442 |
| 12733 | { PseudoVLUXSEG3EI32_V_M2_M2, VLUXSEG3EI32_V, 0x1, 0x0 }, // 5443 |
| 12734 | { PseudoVLUXSEG3EI32_V_M2_M2_MASK, VLUXSEG3EI32_V, 0x1, 0x0 }, // 5444 |
| 12735 | { PseudoVLUXSEG3EI32_V_M4_M2, VLUXSEG3EI32_V, 0x1, 0x0 }, // 5445 |
| 12736 | { PseudoVLUXSEG3EI32_V_M4_M2_MASK, VLUXSEG3EI32_V, 0x1, 0x0 }, // 5446 |
| 12737 | { PseudoVLUXSEG3EI32_V_M8_M2, VLUXSEG3EI32_V, 0x1, 0x0 }, // 5447 |
| 12738 | { PseudoVLUXSEG3EI32_V_M8_M2_MASK, VLUXSEG3EI32_V, 0x1, 0x0 }, // 5448 |
| 12739 | { PseudoVLUXSEG3EI32_V_MF2_MF8, VLUXSEG3EI32_V, 0x5, 0x0 }, // 5449 |
| 12740 | { PseudoVLUXSEG3EI32_V_MF2_MF8_MASK, VLUXSEG3EI32_V, 0x5, 0x0 }, // 5450 |
| 12741 | { PseudoVLUXSEG3EI32_V_M1_MF4, VLUXSEG3EI32_V, 0x6, 0x0 }, // 5451 |
| 12742 | { PseudoVLUXSEG3EI32_V_M1_MF4_MASK, VLUXSEG3EI32_V, 0x6, 0x0 }, // 5452 |
| 12743 | { PseudoVLUXSEG3EI32_V_MF2_MF4, VLUXSEG3EI32_V, 0x6, 0x0 }, // 5453 |
| 12744 | { PseudoVLUXSEG3EI32_V_MF2_MF4_MASK, VLUXSEG3EI32_V, 0x6, 0x0 }, // 5454 |
| 12745 | { PseudoVLUXSEG3EI32_V_M1_MF2, VLUXSEG3EI32_V, 0x7, 0x0 }, // 5455 |
| 12746 | { PseudoVLUXSEG3EI32_V_M1_MF2_MASK, VLUXSEG3EI32_V, 0x7, 0x0 }, // 5456 |
| 12747 | { PseudoVLUXSEG3EI32_V_M2_MF2, VLUXSEG3EI32_V, 0x7, 0x0 }, // 5457 |
| 12748 | { PseudoVLUXSEG3EI32_V_M2_MF2_MASK, VLUXSEG3EI32_V, 0x7, 0x0 }, // 5458 |
| 12749 | { PseudoVLUXSEG3EI32_V_MF2_MF2, VLUXSEG3EI32_V, 0x7, 0x0 }, // 5459 |
| 12750 | { PseudoVLUXSEG3EI32_V_MF2_MF2_MASK, VLUXSEG3EI32_V, 0x7, 0x0 }, // 5460 |
| 12751 | { PseudoVLUXSEG3EI64_V_M1_M1, VLUXSEG3EI64_V, 0x0, 0x0 }, // 5461 |
| 12752 | { PseudoVLUXSEG3EI64_V_M1_M1_MASK, VLUXSEG3EI64_V, 0x0, 0x0 }, // 5462 |
| 12753 | { PseudoVLUXSEG3EI64_V_M2_M1, VLUXSEG3EI64_V, 0x0, 0x0 }, // 5463 |
| 12754 | { PseudoVLUXSEG3EI64_V_M2_M1_MASK, VLUXSEG3EI64_V, 0x0, 0x0 }, // 5464 |
| 12755 | { PseudoVLUXSEG3EI64_V_M4_M1, VLUXSEG3EI64_V, 0x0, 0x0 }, // 5465 |
| 12756 | { PseudoVLUXSEG3EI64_V_M4_M1_MASK, VLUXSEG3EI64_V, 0x0, 0x0 }, // 5466 |
| 12757 | { PseudoVLUXSEG3EI64_V_M8_M1, VLUXSEG3EI64_V, 0x0, 0x0 }, // 5467 |
| 12758 | { PseudoVLUXSEG3EI64_V_M8_M1_MASK, VLUXSEG3EI64_V, 0x0, 0x0 }, // 5468 |
| 12759 | { PseudoVLUXSEG3EI64_V_M2_M2, VLUXSEG3EI64_V, 0x1, 0x0 }, // 5469 |
| 12760 | { PseudoVLUXSEG3EI64_V_M2_M2_MASK, VLUXSEG3EI64_V, 0x1, 0x0 }, // 5470 |
| 12761 | { PseudoVLUXSEG3EI64_V_M4_M2, VLUXSEG3EI64_V, 0x1, 0x0 }, // 5471 |
| 12762 | { PseudoVLUXSEG3EI64_V_M4_M2_MASK, VLUXSEG3EI64_V, 0x1, 0x0 }, // 5472 |
| 12763 | { PseudoVLUXSEG3EI64_V_M8_M2, VLUXSEG3EI64_V, 0x1, 0x0 }, // 5473 |
| 12764 | { PseudoVLUXSEG3EI64_V_M8_M2_MASK, VLUXSEG3EI64_V, 0x1, 0x0 }, // 5474 |
| 12765 | { PseudoVLUXSEG3EI64_V_M1_MF8, VLUXSEG3EI64_V, 0x5, 0x0 }, // 5475 |
| 12766 | { PseudoVLUXSEG3EI64_V_M1_MF8_MASK, VLUXSEG3EI64_V, 0x5, 0x0 }, // 5476 |
| 12767 | { PseudoVLUXSEG3EI64_V_M1_MF4, VLUXSEG3EI64_V, 0x6, 0x0 }, // 5477 |
| 12768 | { PseudoVLUXSEG3EI64_V_M1_MF4_MASK, VLUXSEG3EI64_V, 0x6, 0x0 }, // 5478 |
| 12769 | { PseudoVLUXSEG3EI64_V_M2_MF4, VLUXSEG3EI64_V, 0x6, 0x0 }, // 5479 |
| 12770 | { PseudoVLUXSEG3EI64_V_M2_MF4_MASK, VLUXSEG3EI64_V, 0x6, 0x0 }, // 5480 |
| 12771 | { PseudoVLUXSEG3EI64_V_M1_MF2, VLUXSEG3EI64_V, 0x7, 0x0 }, // 5481 |
| 12772 | { PseudoVLUXSEG3EI64_V_M1_MF2_MASK, VLUXSEG3EI64_V, 0x7, 0x0 }, // 5482 |
| 12773 | { PseudoVLUXSEG3EI64_V_M2_MF2, VLUXSEG3EI64_V, 0x7, 0x0 }, // 5483 |
| 12774 | { PseudoVLUXSEG3EI64_V_M2_MF2_MASK, VLUXSEG3EI64_V, 0x7, 0x0 }, // 5484 |
| 12775 | { PseudoVLUXSEG3EI64_V_M4_MF2, VLUXSEG3EI64_V, 0x7, 0x0 }, // 5485 |
| 12776 | { PseudoVLUXSEG3EI64_V_M4_MF2_MASK, VLUXSEG3EI64_V, 0x7, 0x0 }, // 5486 |
| 12777 | { PseudoVLUXSEG3EI8_V_M1_M1, VLUXSEG3EI8_V, 0x0, 0x0 }, // 5487 |
| 12778 | { PseudoVLUXSEG3EI8_V_M1_M1_MASK, VLUXSEG3EI8_V, 0x0, 0x0 }, // 5488 |
| 12779 | { PseudoVLUXSEG3EI8_V_MF2_M1, VLUXSEG3EI8_V, 0x0, 0x0 }, // 5489 |
| 12780 | { PseudoVLUXSEG3EI8_V_MF2_M1_MASK, VLUXSEG3EI8_V, 0x0, 0x0 }, // 5490 |
| 12781 | { PseudoVLUXSEG3EI8_V_MF4_M1, VLUXSEG3EI8_V, 0x0, 0x0 }, // 5491 |
| 12782 | { PseudoVLUXSEG3EI8_V_MF4_M1_MASK, VLUXSEG3EI8_V, 0x0, 0x0 }, // 5492 |
| 12783 | { PseudoVLUXSEG3EI8_V_MF8_M1, VLUXSEG3EI8_V, 0x0, 0x0 }, // 5493 |
| 12784 | { PseudoVLUXSEG3EI8_V_MF8_M1_MASK, VLUXSEG3EI8_V, 0x0, 0x0 }, // 5494 |
| 12785 | { PseudoVLUXSEG3EI8_V_M1_M2, VLUXSEG3EI8_V, 0x1, 0x0 }, // 5495 |
| 12786 | { PseudoVLUXSEG3EI8_V_M1_M2_MASK, VLUXSEG3EI8_V, 0x1, 0x0 }, // 5496 |
| 12787 | { PseudoVLUXSEG3EI8_V_M2_M2, VLUXSEG3EI8_V, 0x1, 0x0 }, // 5497 |
| 12788 | { PseudoVLUXSEG3EI8_V_M2_M2_MASK, VLUXSEG3EI8_V, 0x1, 0x0 }, // 5498 |
| 12789 | { PseudoVLUXSEG3EI8_V_MF2_M2, VLUXSEG3EI8_V, 0x1, 0x0 }, // 5499 |
| 12790 | { PseudoVLUXSEG3EI8_V_MF2_M2_MASK, VLUXSEG3EI8_V, 0x1, 0x0 }, // 5500 |
| 12791 | { PseudoVLUXSEG3EI8_V_MF4_M2, VLUXSEG3EI8_V, 0x1, 0x0 }, // 5501 |
| 12792 | { PseudoVLUXSEG3EI8_V_MF4_M2_MASK, VLUXSEG3EI8_V, 0x1, 0x0 }, // 5502 |
| 12793 | { PseudoVLUXSEG3EI8_V_MF8_MF8, VLUXSEG3EI8_V, 0x5, 0x0 }, // 5503 |
| 12794 | { PseudoVLUXSEG3EI8_V_MF8_MF8_MASK, VLUXSEG3EI8_V, 0x5, 0x0 }, // 5504 |
| 12795 | { PseudoVLUXSEG3EI8_V_MF4_MF4, VLUXSEG3EI8_V, 0x6, 0x0 }, // 5505 |
| 12796 | { PseudoVLUXSEG3EI8_V_MF4_MF4_MASK, VLUXSEG3EI8_V, 0x6, 0x0 }, // 5506 |
| 12797 | { PseudoVLUXSEG3EI8_V_MF8_MF4, VLUXSEG3EI8_V, 0x6, 0x0 }, // 5507 |
| 12798 | { PseudoVLUXSEG3EI8_V_MF8_MF4_MASK, VLUXSEG3EI8_V, 0x6, 0x0 }, // 5508 |
| 12799 | { PseudoVLUXSEG3EI8_V_MF2_MF2, VLUXSEG3EI8_V, 0x7, 0x0 }, // 5509 |
| 12800 | { PseudoVLUXSEG3EI8_V_MF2_MF2_MASK, VLUXSEG3EI8_V, 0x7, 0x0 }, // 5510 |
| 12801 | { PseudoVLUXSEG3EI8_V_MF4_MF2, VLUXSEG3EI8_V, 0x7, 0x0 }, // 5511 |
| 12802 | { PseudoVLUXSEG3EI8_V_MF4_MF2_MASK, VLUXSEG3EI8_V, 0x7, 0x0 }, // 5512 |
| 12803 | { PseudoVLUXSEG3EI8_V_MF8_MF2, VLUXSEG3EI8_V, 0x7, 0x0 }, // 5513 |
| 12804 | { PseudoVLUXSEG3EI8_V_MF8_MF2_MASK, VLUXSEG3EI8_V, 0x7, 0x0 }, // 5514 |
| 12805 | { PseudoVLUXSEG4EI16_V_M1_M1, VLUXSEG4EI16_V, 0x0, 0x0 }, // 5515 |
| 12806 | { PseudoVLUXSEG4EI16_V_M1_M1_MASK, VLUXSEG4EI16_V, 0x0, 0x0 }, // 5516 |
| 12807 | { PseudoVLUXSEG4EI16_V_M2_M1, VLUXSEG4EI16_V, 0x0, 0x0 }, // 5517 |
| 12808 | { PseudoVLUXSEG4EI16_V_M2_M1_MASK, VLUXSEG4EI16_V, 0x0, 0x0 }, // 5518 |
| 12809 | { PseudoVLUXSEG4EI16_V_MF2_M1, VLUXSEG4EI16_V, 0x0, 0x0 }, // 5519 |
| 12810 | { PseudoVLUXSEG4EI16_V_MF2_M1_MASK, VLUXSEG4EI16_V, 0x0, 0x0 }, // 5520 |
| 12811 | { PseudoVLUXSEG4EI16_V_MF4_M1, VLUXSEG4EI16_V, 0x0, 0x0 }, // 5521 |
| 12812 | { PseudoVLUXSEG4EI16_V_MF4_M1_MASK, VLUXSEG4EI16_V, 0x0, 0x0 }, // 5522 |
| 12813 | { PseudoVLUXSEG4EI16_V_M1_M2, VLUXSEG4EI16_V, 0x1, 0x0 }, // 5523 |
| 12814 | { PseudoVLUXSEG4EI16_V_M1_M2_MASK, VLUXSEG4EI16_V, 0x1, 0x0 }, // 5524 |
| 12815 | { PseudoVLUXSEG4EI16_V_M2_M2, VLUXSEG4EI16_V, 0x1, 0x0 }, // 5525 |
| 12816 | { PseudoVLUXSEG4EI16_V_M2_M2_MASK, VLUXSEG4EI16_V, 0x1, 0x0 }, // 5526 |
| 12817 | { PseudoVLUXSEG4EI16_V_M4_M2, VLUXSEG4EI16_V, 0x1, 0x0 }, // 5527 |
| 12818 | { PseudoVLUXSEG4EI16_V_M4_M2_MASK, VLUXSEG4EI16_V, 0x1, 0x0 }, // 5528 |
| 12819 | { PseudoVLUXSEG4EI16_V_MF2_M2, VLUXSEG4EI16_V, 0x1, 0x0 }, // 5529 |
| 12820 | { PseudoVLUXSEG4EI16_V_MF2_M2_MASK, VLUXSEG4EI16_V, 0x1, 0x0 }, // 5530 |
| 12821 | { PseudoVLUXSEG4EI16_V_MF4_MF8, VLUXSEG4EI16_V, 0x5, 0x0 }, // 5531 |
| 12822 | { PseudoVLUXSEG4EI16_V_MF4_MF8_MASK, VLUXSEG4EI16_V, 0x5, 0x0 }, // 5532 |
| 12823 | { PseudoVLUXSEG4EI16_V_MF2_MF4, VLUXSEG4EI16_V, 0x6, 0x0 }, // 5533 |
| 12824 | { PseudoVLUXSEG4EI16_V_MF2_MF4_MASK, VLUXSEG4EI16_V, 0x6, 0x0 }, // 5534 |
| 12825 | { PseudoVLUXSEG4EI16_V_MF4_MF4, VLUXSEG4EI16_V, 0x6, 0x0 }, // 5535 |
| 12826 | { PseudoVLUXSEG4EI16_V_MF4_MF4_MASK, VLUXSEG4EI16_V, 0x6, 0x0 }, // 5536 |
| 12827 | { PseudoVLUXSEG4EI16_V_M1_MF2, VLUXSEG4EI16_V, 0x7, 0x0 }, // 5537 |
| 12828 | { PseudoVLUXSEG4EI16_V_M1_MF2_MASK, VLUXSEG4EI16_V, 0x7, 0x0 }, // 5538 |
| 12829 | { PseudoVLUXSEG4EI16_V_MF2_MF2, VLUXSEG4EI16_V, 0x7, 0x0 }, // 5539 |
| 12830 | { PseudoVLUXSEG4EI16_V_MF2_MF2_MASK, VLUXSEG4EI16_V, 0x7, 0x0 }, // 5540 |
| 12831 | { PseudoVLUXSEG4EI16_V_MF4_MF2, VLUXSEG4EI16_V, 0x7, 0x0 }, // 5541 |
| 12832 | { PseudoVLUXSEG4EI16_V_MF4_MF2_MASK, VLUXSEG4EI16_V, 0x7, 0x0 }, // 5542 |
| 12833 | { PseudoVLUXSEG4EI32_V_M1_M1, VLUXSEG4EI32_V, 0x0, 0x0 }, // 5543 |
| 12834 | { PseudoVLUXSEG4EI32_V_M1_M1_MASK, VLUXSEG4EI32_V, 0x0, 0x0 }, // 5544 |
| 12835 | { PseudoVLUXSEG4EI32_V_M2_M1, VLUXSEG4EI32_V, 0x0, 0x0 }, // 5545 |
| 12836 | { PseudoVLUXSEG4EI32_V_M2_M1_MASK, VLUXSEG4EI32_V, 0x0, 0x0 }, // 5546 |
| 12837 | { PseudoVLUXSEG4EI32_V_M4_M1, VLUXSEG4EI32_V, 0x0, 0x0 }, // 5547 |
| 12838 | { PseudoVLUXSEG4EI32_V_M4_M1_MASK, VLUXSEG4EI32_V, 0x0, 0x0 }, // 5548 |
| 12839 | { PseudoVLUXSEG4EI32_V_MF2_M1, VLUXSEG4EI32_V, 0x0, 0x0 }, // 5549 |
| 12840 | { PseudoVLUXSEG4EI32_V_MF2_M1_MASK, VLUXSEG4EI32_V, 0x0, 0x0 }, // 5550 |
| 12841 | { PseudoVLUXSEG4EI32_V_M1_M2, VLUXSEG4EI32_V, 0x1, 0x0 }, // 5551 |
| 12842 | { PseudoVLUXSEG4EI32_V_M1_M2_MASK, VLUXSEG4EI32_V, 0x1, 0x0 }, // 5552 |
| 12843 | { PseudoVLUXSEG4EI32_V_M2_M2, VLUXSEG4EI32_V, 0x1, 0x0 }, // 5553 |
| 12844 | { PseudoVLUXSEG4EI32_V_M2_M2_MASK, VLUXSEG4EI32_V, 0x1, 0x0 }, // 5554 |
| 12845 | { PseudoVLUXSEG4EI32_V_M4_M2, VLUXSEG4EI32_V, 0x1, 0x0 }, // 5555 |
| 12846 | { PseudoVLUXSEG4EI32_V_M4_M2_MASK, VLUXSEG4EI32_V, 0x1, 0x0 }, // 5556 |
| 12847 | { PseudoVLUXSEG4EI32_V_M8_M2, VLUXSEG4EI32_V, 0x1, 0x0 }, // 5557 |
| 12848 | { PseudoVLUXSEG4EI32_V_M8_M2_MASK, VLUXSEG4EI32_V, 0x1, 0x0 }, // 5558 |
| 12849 | { PseudoVLUXSEG4EI32_V_MF2_MF8, VLUXSEG4EI32_V, 0x5, 0x0 }, // 5559 |
| 12850 | { PseudoVLUXSEG4EI32_V_MF2_MF8_MASK, VLUXSEG4EI32_V, 0x5, 0x0 }, // 5560 |
| 12851 | { PseudoVLUXSEG4EI32_V_M1_MF4, VLUXSEG4EI32_V, 0x6, 0x0 }, // 5561 |
| 12852 | { PseudoVLUXSEG4EI32_V_M1_MF4_MASK, VLUXSEG4EI32_V, 0x6, 0x0 }, // 5562 |
| 12853 | { PseudoVLUXSEG4EI32_V_MF2_MF4, VLUXSEG4EI32_V, 0x6, 0x0 }, // 5563 |
| 12854 | { PseudoVLUXSEG4EI32_V_MF2_MF4_MASK, VLUXSEG4EI32_V, 0x6, 0x0 }, // 5564 |
| 12855 | { PseudoVLUXSEG4EI32_V_M1_MF2, VLUXSEG4EI32_V, 0x7, 0x0 }, // 5565 |
| 12856 | { PseudoVLUXSEG4EI32_V_M1_MF2_MASK, VLUXSEG4EI32_V, 0x7, 0x0 }, // 5566 |
| 12857 | { PseudoVLUXSEG4EI32_V_M2_MF2, VLUXSEG4EI32_V, 0x7, 0x0 }, // 5567 |
| 12858 | { PseudoVLUXSEG4EI32_V_M2_MF2_MASK, VLUXSEG4EI32_V, 0x7, 0x0 }, // 5568 |
| 12859 | { PseudoVLUXSEG4EI32_V_MF2_MF2, VLUXSEG4EI32_V, 0x7, 0x0 }, // 5569 |
| 12860 | { PseudoVLUXSEG4EI32_V_MF2_MF2_MASK, VLUXSEG4EI32_V, 0x7, 0x0 }, // 5570 |
| 12861 | { PseudoVLUXSEG4EI64_V_M1_M1, VLUXSEG4EI64_V, 0x0, 0x0 }, // 5571 |
| 12862 | { PseudoVLUXSEG4EI64_V_M1_M1_MASK, VLUXSEG4EI64_V, 0x0, 0x0 }, // 5572 |
| 12863 | { PseudoVLUXSEG4EI64_V_M2_M1, VLUXSEG4EI64_V, 0x0, 0x0 }, // 5573 |
| 12864 | { PseudoVLUXSEG4EI64_V_M2_M1_MASK, VLUXSEG4EI64_V, 0x0, 0x0 }, // 5574 |
| 12865 | { PseudoVLUXSEG4EI64_V_M4_M1, VLUXSEG4EI64_V, 0x0, 0x0 }, // 5575 |
| 12866 | { PseudoVLUXSEG4EI64_V_M4_M1_MASK, VLUXSEG4EI64_V, 0x0, 0x0 }, // 5576 |
| 12867 | { PseudoVLUXSEG4EI64_V_M8_M1, VLUXSEG4EI64_V, 0x0, 0x0 }, // 5577 |
| 12868 | { PseudoVLUXSEG4EI64_V_M8_M1_MASK, VLUXSEG4EI64_V, 0x0, 0x0 }, // 5578 |
| 12869 | { PseudoVLUXSEG4EI64_V_M2_M2, VLUXSEG4EI64_V, 0x1, 0x0 }, // 5579 |
| 12870 | { PseudoVLUXSEG4EI64_V_M2_M2_MASK, VLUXSEG4EI64_V, 0x1, 0x0 }, // 5580 |
| 12871 | { PseudoVLUXSEG4EI64_V_M4_M2, VLUXSEG4EI64_V, 0x1, 0x0 }, // 5581 |
| 12872 | { PseudoVLUXSEG4EI64_V_M4_M2_MASK, VLUXSEG4EI64_V, 0x1, 0x0 }, // 5582 |
| 12873 | { PseudoVLUXSEG4EI64_V_M8_M2, VLUXSEG4EI64_V, 0x1, 0x0 }, // 5583 |
| 12874 | { PseudoVLUXSEG4EI64_V_M8_M2_MASK, VLUXSEG4EI64_V, 0x1, 0x0 }, // 5584 |
| 12875 | { PseudoVLUXSEG4EI64_V_M1_MF8, VLUXSEG4EI64_V, 0x5, 0x0 }, // 5585 |
| 12876 | { PseudoVLUXSEG4EI64_V_M1_MF8_MASK, VLUXSEG4EI64_V, 0x5, 0x0 }, // 5586 |
| 12877 | { PseudoVLUXSEG4EI64_V_M1_MF4, VLUXSEG4EI64_V, 0x6, 0x0 }, // 5587 |
| 12878 | { PseudoVLUXSEG4EI64_V_M1_MF4_MASK, VLUXSEG4EI64_V, 0x6, 0x0 }, // 5588 |
| 12879 | { PseudoVLUXSEG4EI64_V_M2_MF4, VLUXSEG4EI64_V, 0x6, 0x0 }, // 5589 |
| 12880 | { PseudoVLUXSEG4EI64_V_M2_MF4_MASK, VLUXSEG4EI64_V, 0x6, 0x0 }, // 5590 |
| 12881 | { PseudoVLUXSEG4EI64_V_M1_MF2, VLUXSEG4EI64_V, 0x7, 0x0 }, // 5591 |
| 12882 | { PseudoVLUXSEG4EI64_V_M1_MF2_MASK, VLUXSEG4EI64_V, 0x7, 0x0 }, // 5592 |
| 12883 | { PseudoVLUXSEG4EI64_V_M2_MF2, VLUXSEG4EI64_V, 0x7, 0x0 }, // 5593 |
| 12884 | { PseudoVLUXSEG4EI64_V_M2_MF2_MASK, VLUXSEG4EI64_V, 0x7, 0x0 }, // 5594 |
| 12885 | { PseudoVLUXSEG4EI64_V_M4_MF2, VLUXSEG4EI64_V, 0x7, 0x0 }, // 5595 |
| 12886 | { PseudoVLUXSEG4EI64_V_M4_MF2_MASK, VLUXSEG4EI64_V, 0x7, 0x0 }, // 5596 |
| 12887 | { PseudoVLUXSEG4EI8_V_M1_M1, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5597 |
| 12888 | { PseudoVLUXSEG4EI8_V_M1_M1_MASK, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5598 |
| 12889 | { PseudoVLUXSEG4EI8_V_MF2_M1, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5599 |
| 12890 | { PseudoVLUXSEG4EI8_V_MF2_M1_MASK, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5600 |
| 12891 | { PseudoVLUXSEG4EI8_V_MF4_M1, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5601 |
| 12892 | { PseudoVLUXSEG4EI8_V_MF4_M1_MASK, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5602 |
| 12893 | { PseudoVLUXSEG4EI8_V_MF8_M1, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5603 |
| 12894 | { PseudoVLUXSEG4EI8_V_MF8_M1_MASK, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5604 |
| 12895 | { PseudoVLUXSEG4EI8_V_M1_M2, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5605 |
| 12896 | { PseudoVLUXSEG4EI8_V_M1_M2_MASK, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5606 |
| 12897 | { PseudoVLUXSEG4EI8_V_M2_M2, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5607 |
| 12898 | { PseudoVLUXSEG4EI8_V_M2_M2_MASK, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5608 |
| 12899 | { PseudoVLUXSEG4EI8_V_MF2_M2, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5609 |
| 12900 | { PseudoVLUXSEG4EI8_V_MF2_M2_MASK, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5610 |
| 12901 | { PseudoVLUXSEG4EI8_V_MF4_M2, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5611 |
| 12902 | { PseudoVLUXSEG4EI8_V_MF4_M2_MASK, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5612 |
| 12903 | { PseudoVLUXSEG4EI8_V_MF8_MF8, VLUXSEG4EI8_V, 0x5, 0x0 }, // 5613 |
| 12904 | { PseudoVLUXSEG4EI8_V_MF8_MF8_MASK, VLUXSEG4EI8_V, 0x5, 0x0 }, // 5614 |
| 12905 | { PseudoVLUXSEG4EI8_V_MF4_MF4, VLUXSEG4EI8_V, 0x6, 0x0 }, // 5615 |
| 12906 | { PseudoVLUXSEG4EI8_V_MF4_MF4_MASK, VLUXSEG4EI8_V, 0x6, 0x0 }, // 5616 |
| 12907 | { PseudoVLUXSEG4EI8_V_MF8_MF4, VLUXSEG4EI8_V, 0x6, 0x0 }, // 5617 |
| 12908 | { PseudoVLUXSEG4EI8_V_MF8_MF4_MASK, VLUXSEG4EI8_V, 0x6, 0x0 }, // 5618 |
| 12909 | { PseudoVLUXSEG4EI8_V_MF2_MF2, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5619 |
| 12910 | { PseudoVLUXSEG4EI8_V_MF2_MF2_MASK, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5620 |
| 12911 | { PseudoVLUXSEG4EI8_V_MF4_MF2, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5621 |
| 12912 | { PseudoVLUXSEG4EI8_V_MF4_MF2_MASK, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5622 |
| 12913 | { PseudoVLUXSEG4EI8_V_MF8_MF2, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5623 |
| 12914 | { PseudoVLUXSEG4EI8_V_MF8_MF2_MASK, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5624 |
| 12915 | { PseudoVLUXSEG5EI16_V_M1_M1, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5625 |
| 12916 | { PseudoVLUXSEG5EI16_V_M1_M1_MASK, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5626 |
| 12917 | { PseudoVLUXSEG5EI16_V_M2_M1, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5627 |
| 12918 | { PseudoVLUXSEG5EI16_V_M2_M1_MASK, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5628 |
| 12919 | { PseudoVLUXSEG5EI16_V_MF2_M1, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5629 |
| 12920 | { PseudoVLUXSEG5EI16_V_MF2_M1_MASK, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5630 |
| 12921 | { PseudoVLUXSEG5EI16_V_MF4_M1, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5631 |
| 12922 | { PseudoVLUXSEG5EI16_V_MF4_M1_MASK, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5632 |
| 12923 | { PseudoVLUXSEG5EI16_V_MF4_MF8, VLUXSEG5EI16_V, 0x5, 0x0 }, // 5633 |
| 12924 | { PseudoVLUXSEG5EI16_V_MF4_MF8_MASK, VLUXSEG5EI16_V, 0x5, 0x0 }, // 5634 |
| 12925 | { PseudoVLUXSEG5EI16_V_MF2_MF4, VLUXSEG5EI16_V, 0x6, 0x0 }, // 5635 |
| 12926 | { PseudoVLUXSEG5EI16_V_MF2_MF4_MASK, VLUXSEG5EI16_V, 0x6, 0x0 }, // 5636 |
| 12927 | { PseudoVLUXSEG5EI16_V_MF4_MF4, VLUXSEG5EI16_V, 0x6, 0x0 }, // 5637 |
| 12928 | { PseudoVLUXSEG5EI16_V_MF4_MF4_MASK, VLUXSEG5EI16_V, 0x6, 0x0 }, // 5638 |
| 12929 | { PseudoVLUXSEG5EI16_V_M1_MF2, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5639 |
| 12930 | { PseudoVLUXSEG5EI16_V_M1_MF2_MASK, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5640 |
| 12931 | { PseudoVLUXSEG5EI16_V_MF2_MF2, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5641 |
| 12932 | { PseudoVLUXSEG5EI16_V_MF2_MF2_MASK, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5642 |
| 12933 | { PseudoVLUXSEG5EI16_V_MF4_MF2, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5643 |
| 12934 | { PseudoVLUXSEG5EI16_V_MF4_MF2_MASK, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5644 |
| 12935 | { PseudoVLUXSEG5EI32_V_M1_M1, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5645 |
| 12936 | { PseudoVLUXSEG5EI32_V_M1_M1_MASK, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5646 |
| 12937 | { PseudoVLUXSEG5EI32_V_M2_M1, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5647 |
| 12938 | { PseudoVLUXSEG5EI32_V_M2_M1_MASK, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5648 |
| 12939 | { PseudoVLUXSEG5EI32_V_M4_M1, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5649 |
| 12940 | { PseudoVLUXSEG5EI32_V_M4_M1_MASK, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5650 |
| 12941 | { PseudoVLUXSEG5EI32_V_MF2_M1, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5651 |
| 12942 | { PseudoVLUXSEG5EI32_V_MF2_M1_MASK, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5652 |
| 12943 | { PseudoVLUXSEG5EI32_V_MF2_MF8, VLUXSEG5EI32_V, 0x5, 0x0 }, // 5653 |
| 12944 | { PseudoVLUXSEG5EI32_V_MF2_MF8_MASK, VLUXSEG5EI32_V, 0x5, 0x0 }, // 5654 |
| 12945 | { PseudoVLUXSEG5EI32_V_M1_MF4, VLUXSEG5EI32_V, 0x6, 0x0 }, // 5655 |
| 12946 | { PseudoVLUXSEG5EI32_V_M1_MF4_MASK, VLUXSEG5EI32_V, 0x6, 0x0 }, // 5656 |
| 12947 | { PseudoVLUXSEG5EI32_V_MF2_MF4, VLUXSEG5EI32_V, 0x6, 0x0 }, // 5657 |
| 12948 | { PseudoVLUXSEG5EI32_V_MF2_MF4_MASK, VLUXSEG5EI32_V, 0x6, 0x0 }, // 5658 |
| 12949 | { PseudoVLUXSEG5EI32_V_M1_MF2, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5659 |
| 12950 | { PseudoVLUXSEG5EI32_V_M1_MF2_MASK, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5660 |
| 12951 | { PseudoVLUXSEG5EI32_V_M2_MF2, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5661 |
| 12952 | { PseudoVLUXSEG5EI32_V_M2_MF2_MASK, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5662 |
| 12953 | { PseudoVLUXSEG5EI32_V_MF2_MF2, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5663 |
| 12954 | { PseudoVLUXSEG5EI32_V_MF2_MF2_MASK, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5664 |
| 12955 | { PseudoVLUXSEG5EI64_V_M1_M1, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5665 |
| 12956 | { PseudoVLUXSEG5EI64_V_M1_M1_MASK, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5666 |
| 12957 | { PseudoVLUXSEG5EI64_V_M2_M1, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5667 |
| 12958 | { PseudoVLUXSEG5EI64_V_M2_M1_MASK, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5668 |
| 12959 | { PseudoVLUXSEG5EI64_V_M4_M1, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5669 |
| 12960 | { PseudoVLUXSEG5EI64_V_M4_M1_MASK, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5670 |
| 12961 | { PseudoVLUXSEG5EI64_V_M8_M1, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5671 |
| 12962 | { PseudoVLUXSEG5EI64_V_M8_M1_MASK, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5672 |
| 12963 | { PseudoVLUXSEG5EI64_V_M1_MF8, VLUXSEG5EI64_V, 0x5, 0x0 }, // 5673 |
| 12964 | { PseudoVLUXSEG5EI64_V_M1_MF8_MASK, VLUXSEG5EI64_V, 0x5, 0x0 }, // 5674 |
| 12965 | { PseudoVLUXSEG5EI64_V_M1_MF4, VLUXSEG5EI64_V, 0x6, 0x0 }, // 5675 |
| 12966 | { PseudoVLUXSEG5EI64_V_M1_MF4_MASK, VLUXSEG5EI64_V, 0x6, 0x0 }, // 5676 |
| 12967 | { PseudoVLUXSEG5EI64_V_M2_MF4, VLUXSEG5EI64_V, 0x6, 0x0 }, // 5677 |
| 12968 | { PseudoVLUXSEG5EI64_V_M2_MF4_MASK, VLUXSEG5EI64_V, 0x6, 0x0 }, // 5678 |
| 12969 | { PseudoVLUXSEG5EI64_V_M1_MF2, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5679 |
| 12970 | { PseudoVLUXSEG5EI64_V_M1_MF2_MASK, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5680 |
| 12971 | { PseudoVLUXSEG5EI64_V_M2_MF2, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5681 |
| 12972 | { PseudoVLUXSEG5EI64_V_M2_MF2_MASK, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5682 |
| 12973 | { PseudoVLUXSEG5EI64_V_M4_MF2, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5683 |
| 12974 | { PseudoVLUXSEG5EI64_V_M4_MF2_MASK, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5684 |
| 12975 | { PseudoVLUXSEG5EI8_V_M1_M1, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5685 |
| 12976 | { PseudoVLUXSEG5EI8_V_M1_M1_MASK, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5686 |
| 12977 | { PseudoVLUXSEG5EI8_V_MF2_M1, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5687 |
| 12978 | { PseudoVLUXSEG5EI8_V_MF2_M1_MASK, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5688 |
| 12979 | { PseudoVLUXSEG5EI8_V_MF4_M1, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5689 |
| 12980 | { PseudoVLUXSEG5EI8_V_MF4_M1_MASK, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5690 |
| 12981 | { PseudoVLUXSEG5EI8_V_MF8_M1, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5691 |
| 12982 | { PseudoVLUXSEG5EI8_V_MF8_M1_MASK, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5692 |
| 12983 | { PseudoVLUXSEG5EI8_V_MF8_MF8, VLUXSEG5EI8_V, 0x5, 0x0 }, // 5693 |
| 12984 | { PseudoVLUXSEG5EI8_V_MF8_MF8_MASK, VLUXSEG5EI8_V, 0x5, 0x0 }, // 5694 |
| 12985 | { PseudoVLUXSEG5EI8_V_MF4_MF4, VLUXSEG5EI8_V, 0x6, 0x0 }, // 5695 |
| 12986 | { PseudoVLUXSEG5EI8_V_MF4_MF4_MASK, VLUXSEG5EI8_V, 0x6, 0x0 }, // 5696 |
| 12987 | { PseudoVLUXSEG5EI8_V_MF8_MF4, VLUXSEG5EI8_V, 0x6, 0x0 }, // 5697 |
| 12988 | { PseudoVLUXSEG5EI8_V_MF8_MF4_MASK, VLUXSEG5EI8_V, 0x6, 0x0 }, // 5698 |
| 12989 | { PseudoVLUXSEG5EI8_V_MF2_MF2, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5699 |
| 12990 | { PseudoVLUXSEG5EI8_V_MF2_MF2_MASK, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5700 |
| 12991 | { PseudoVLUXSEG5EI8_V_MF4_MF2, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5701 |
| 12992 | { PseudoVLUXSEG5EI8_V_MF4_MF2_MASK, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5702 |
| 12993 | { PseudoVLUXSEG5EI8_V_MF8_MF2, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5703 |
| 12994 | { PseudoVLUXSEG5EI8_V_MF8_MF2_MASK, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5704 |
| 12995 | { PseudoVLUXSEG6EI16_V_M1_M1, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5705 |
| 12996 | { PseudoVLUXSEG6EI16_V_M1_M1_MASK, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5706 |
| 12997 | { PseudoVLUXSEG6EI16_V_M2_M1, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5707 |
| 12998 | { PseudoVLUXSEG6EI16_V_M2_M1_MASK, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5708 |
| 12999 | { PseudoVLUXSEG6EI16_V_MF2_M1, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5709 |
| 13000 | { PseudoVLUXSEG6EI16_V_MF2_M1_MASK, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5710 |
| 13001 | { PseudoVLUXSEG6EI16_V_MF4_M1, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5711 |
| 13002 | { PseudoVLUXSEG6EI16_V_MF4_M1_MASK, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5712 |
| 13003 | { PseudoVLUXSEG6EI16_V_MF4_MF8, VLUXSEG6EI16_V, 0x5, 0x0 }, // 5713 |
| 13004 | { PseudoVLUXSEG6EI16_V_MF4_MF8_MASK, VLUXSEG6EI16_V, 0x5, 0x0 }, // 5714 |
| 13005 | { PseudoVLUXSEG6EI16_V_MF2_MF4, VLUXSEG6EI16_V, 0x6, 0x0 }, // 5715 |
| 13006 | { PseudoVLUXSEG6EI16_V_MF2_MF4_MASK, VLUXSEG6EI16_V, 0x6, 0x0 }, // 5716 |
| 13007 | { PseudoVLUXSEG6EI16_V_MF4_MF4, VLUXSEG6EI16_V, 0x6, 0x0 }, // 5717 |
| 13008 | { PseudoVLUXSEG6EI16_V_MF4_MF4_MASK, VLUXSEG6EI16_V, 0x6, 0x0 }, // 5718 |
| 13009 | { PseudoVLUXSEG6EI16_V_M1_MF2, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5719 |
| 13010 | { PseudoVLUXSEG6EI16_V_M1_MF2_MASK, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5720 |
| 13011 | { PseudoVLUXSEG6EI16_V_MF2_MF2, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5721 |
| 13012 | { PseudoVLUXSEG6EI16_V_MF2_MF2_MASK, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5722 |
| 13013 | { PseudoVLUXSEG6EI16_V_MF4_MF2, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5723 |
| 13014 | { PseudoVLUXSEG6EI16_V_MF4_MF2_MASK, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5724 |
| 13015 | { PseudoVLUXSEG6EI32_V_M1_M1, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5725 |
| 13016 | { PseudoVLUXSEG6EI32_V_M1_M1_MASK, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5726 |
| 13017 | { PseudoVLUXSEG6EI32_V_M2_M1, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5727 |
| 13018 | { PseudoVLUXSEG6EI32_V_M2_M1_MASK, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5728 |
| 13019 | { PseudoVLUXSEG6EI32_V_M4_M1, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5729 |
| 13020 | { PseudoVLUXSEG6EI32_V_M4_M1_MASK, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5730 |
| 13021 | { PseudoVLUXSEG6EI32_V_MF2_M1, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5731 |
| 13022 | { PseudoVLUXSEG6EI32_V_MF2_M1_MASK, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5732 |
| 13023 | { PseudoVLUXSEG6EI32_V_MF2_MF8, VLUXSEG6EI32_V, 0x5, 0x0 }, // 5733 |
| 13024 | { PseudoVLUXSEG6EI32_V_MF2_MF8_MASK, VLUXSEG6EI32_V, 0x5, 0x0 }, // 5734 |
| 13025 | { PseudoVLUXSEG6EI32_V_M1_MF4, VLUXSEG6EI32_V, 0x6, 0x0 }, // 5735 |
| 13026 | { PseudoVLUXSEG6EI32_V_M1_MF4_MASK, VLUXSEG6EI32_V, 0x6, 0x0 }, // 5736 |
| 13027 | { PseudoVLUXSEG6EI32_V_MF2_MF4, VLUXSEG6EI32_V, 0x6, 0x0 }, // 5737 |
| 13028 | { PseudoVLUXSEG6EI32_V_MF2_MF4_MASK, VLUXSEG6EI32_V, 0x6, 0x0 }, // 5738 |
| 13029 | { PseudoVLUXSEG6EI32_V_M1_MF2, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5739 |
| 13030 | { PseudoVLUXSEG6EI32_V_M1_MF2_MASK, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5740 |
| 13031 | { PseudoVLUXSEG6EI32_V_M2_MF2, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5741 |
| 13032 | { PseudoVLUXSEG6EI32_V_M2_MF2_MASK, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5742 |
| 13033 | { PseudoVLUXSEG6EI32_V_MF2_MF2, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5743 |
| 13034 | { PseudoVLUXSEG6EI32_V_MF2_MF2_MASK, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5744 |
| 13035 | { PseudoVLUXSEG6EI64_V_M1_M1, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5745 |
| 13036 | { PseudoVLUXSEG6EI64_V_M1_M1_MASK, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5746 |
| 13037 | { PseudoVLUXSEG6EI64_V_M2_M1, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5747 |
| 13038 | { PseudoVLUXSEG6EI64_V_M2_M1_MASK, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5748 |
| 13039 | { PseudoVLUXSEG6EI64_V_M4_M1, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5749 |
| 13040 | { PseudoVLUXSEG6EI64_V_M4_M1_MASK, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5750 |
| 13041 | { PseudoVLUXSEG6EI64_V_M8_M1, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5751 |
| 13042 | { PseudoVLUXSEG6EI64_V_M8_M1_MASK, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5752 |
| 13043 | { PseudoVLUXSEG6EI64_V_M1_MF8, VLUXSEG6EI64_V, 0x5, 0x0 }, // 5753 |
| 13044 | { PseudoVLUXSEG6EI64_V_M1_MF8_MASK, VLUXSEG6EI64_V, 0x5, 0x0 }, // 5754 |
| 13045 | { PseudoVLUXSEG6EI64_V_M1_MF4, VLUXSEG6EI64_V, 0x6, 0x0 }, // 5755 |
| 13046 | { PseudoVLUXSEG6EI64_V_M1_MF4_MASK, VLUXSEG6EI64_V, 0x6, 0x0 }, // 5756 |
| 13047 | { PseudoVLUXSEG6EI64_V_M2_MF4, VLUXSEG6EI64_V, 0x6, 0x0 }, // 5757 |
| 13048 | { PseudoVLUXSEG6EI64_V_M2_MF4_MASK, VLUXSEG6EI64_V, 0x6, 0x0 }, // 5758 |
| 13049 | { PseudoVLUXSEG6EI64_V_M1_MF2, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5759 |
| 13050 | { PseudoVLUXSEG6EI64_V_M1_MF2_MASK, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5760 |
| 13051 | { PseudoVLUXSEG6EI64_V_M2_MF2, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5761 |
| 13052 | { PseudoVLUXSEG6EI64_V_M2_MF2_MASK, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5762 |
| 13053 | { PseudoVLUXSEG6EI64_V_M4_MF2, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5763 |
| 13054 | { PseudoVLUXSEG6EI64_V_M4_MF2_MASK, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5764 |
| 13055 | { PseudoVLUXSEG6EI8_V_M1_M1, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5765 |
| 13056 | { PseudoVLUXSEG6EI8_V_M1_M1_MASK, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5766 |
| 13057 | { PseudoVLUXSEG6EI8_V_MF2_M1, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5767 |
| 13058 | { PseudoVLUXSEG6EI8_V_MF2_M1_MASK, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5768 |
| 13059 | { PseudoVLUXSEG6EI8_V_MF4_M1, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5769 |
| 13060 | { PseudoVLUXSEG6EI8_V_MF4_M1_MASK, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5770 |
| 13061 | { PseudoVLUXSEG6EI8_V_MF8_M1, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5771 |
| 13062 | { PseudoVLUXSEG6EI8_V_MF8_M1_MASK, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5772 |
| 13063 | { PseudoVLUXSEG6EI8_V_MF8_MF8, VLUXSEG6EI8_V, 0x5, 0x0 }, // 5773 |
| 13064 | { PseudoVLUXSEG6EI8_V_MF8_MF8_MASK, VLUXSEG6EI8_V, 0x5, 0x0 }, // 5774 |
| 13065 | { PseudoVLUXSEG6EI8_V_MF4_MF4, VLUXSEG6EI8_V, 0x6, 0x0 }, // 5775 |
| 13066 | { PseudoVLUXSEG6EI8_V_MF4_MF4_MASK, VLUXSEG6EI8_V, 0x6, 0x0 }, // 5776 |
| 13067 | { PseudoVLUXSEG6EI8_V_MF8_MF4, VLUXSEG6EI8_V, 0x6, 0x0 }, // 5777 |
| 13068 | { PseudoVLUXSEG6EI8_V_MF8_MF4_MASK, VLUXSEG6EI8_V, 0x6, 0x0 }, // 5778 |
| 13069 | { PseudoVLUXSEG6EI8_V_MF2_MF2, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5779 |
| 13070 | { PseudoVLUXSEG6EI8_V_MF2_MF2_MASK, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5780 |
| 13071 | { PseudoVLUXSEG6EI8_V_MF4_MF2, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5781 |
| 13072 | { PseudoVLUXSEG6EI8_V_MF4_MF2_MASK, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5782 |
| 13073 | { PseudoVLUXSEG6EI8_V_MF8_MF2, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5783 |
| 13074 | { PseudoVLUXSEG6EI8_V_MF8_MF2_MASK, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5784 |
| 13075 | { PseudoVLUXSEG7EI16_V_M1_M1, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5785 |
| 13076 | { PseudoVLUXSEG7EI16_V_M1_M1_MASK, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5786 |
| 13077 | { PseudoVLUXSEG7EI16_V_M2_M1, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5787 |
| 13078 | { PseudoVLUXSEG7EI16_V_M2_M1_MASK, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5788 |
| 13079 | { PseudoVLUXSEG7EI16_V_MF2_M1, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5789 |
| 13080 | { PseudoVLUXSEG7EI16_V_MF2_M1_MASK, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5790 |
| 13081 | { PseudoVLUXSEG7EI16_V_MF4_M1, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5791 |
| 13082 | { PseudoVLUXSEG7EI16_V_MF4_M1_MASK, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5792 |
| 13083 | { PseudoVLUXSEG7EI16_V_MF4_MF8, VLUXSEG7EI16_V, 0x5, 0x0 }, // 5793 |
| 13084 | { PseudoVLUXSEG7EI16_V_MF4_MF8_MASK, VLUXSEG7EI16_V, 0x5, 0x0 }, // 5794 |
| 13085 | { PseudoVLUXSEG7EI16_V_MF2_MF4, VLUXSEG7EI16_V, 0x6, 0x0 }, // 5795 |
| 13086 | { PseudoVLUXSEG7EI16_V_MF2_MF4_MASK, VLUXSEG7EI16_V, 0x6, 0x0 }, // 5796 |
| 13087 | { PseudoVLUXSEG7EI16_V_MF4_MF4, VLUXSEG7EI16_V, 0x6, 0x0 }, // 5797 |
| 13088 | { PseudoVLUXSEG7EI16_V_MF4_MF4_MASK, VLUXSEG7EI16_V, 0x6, 0x0 }, // 5798 |
| 13089 | { PseudoVLUXSEG7EI16_V_M1_MF2, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5799 |
| 13090 | { PseudoVLUXSEG7EI16_V_M1_MF2_MASK, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5800 |
| 13091 | { PseudoVLUXSEG7EI16_V_MF2_MF2, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5801 |
| 13092 | { PseudoVLUXSEG7EI16_V_MF2_MF2_MASK, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5802 |
| 13093 | { PseudoVLUXSEG7EI16_V_MF4_MF2, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5803 |
| 13094 | { PseudoVLUXSEG7EI16_V_MF4_MF2_MASK, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5804 |
| 13095 | { PseudoVLUXSEG7EI32_V_M1_M1, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5805 |
| 13096 | { PseudoVLUXSEG7EI32_V_M1_M1_MASK, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5806 |
| 13097 | { PseudoVLUXSEG7EI32_V_M2_M1, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5807 |
| 13098 | { PseudoVLUXSEG7EI32_V_M2_M1_MASK, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5808 |
| 13099 | { PseudoVLUXSEG7EI32_V_M4_M1, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5809 |
| 13100 | { PseudoVLUXSEG7EI32_V_M4_M1_MASK, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5810 |
| 13101 | { PseudoVLUXSEG7EI32_V_MF2_M1, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5811 |
| 13102 | { PseudoVLUXSEG7EI32_V_MF2_M1_MASK, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5812 |
| 13103 | { PseudoVLUXSEG7EI32_V_MF2_MF8, VLUXSEG7EI32_V, 0x5, 0x0 }, // 5813 |
| 13104 | { PseudoVLUXSEG7EI32_V_MF2_MF8_MASK, VLUXSEG7EI32_V, 0x5, 0x0 }, // 5814 |
| 13105 | { PseudoVLUXSEG7EI32_V_M1_MF4, VLUXSEG7EI32_V, 0x6, 0x0 }, // 5815 |
| 13106 | { PseudoVLUXSEG7EI32_V_M1_MF4_MASK, VLUXSEG7EI32_V, 0x6, 0x0 }, // 5816 |
| 13107 | { PseudoVLUXSEG7EI32_V_MF2_MF4, VLUXSEG7EI32_V, 0x6, 0x0 }, // 5817 |
| 13108 | { PseudoVLUXSEG7EI32_V_MF2_MF4_MASK, VLUXSEG7EI32_V, 0x6, 0x0 }, // 5818 |
| 13109 | { PseudoVLUXSEG7EI32_V_M1_MF2, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5819 |
| 13110 | { PseudoVLUXSEG7EI32_V_M1_MF2_MASK, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5820 |
| 13111 | { PseudoVLUXSEG7EI32_V_M2_MF2, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5821 |
| 13112 | { PseudoVLUXSEG7EI32_V_M2_MF2_MASK, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5822 |
| 13113 | { PseudoVLUXSEG7EI32_V_MF2_MF2, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5823 |
| 13114 | { PseudoVLUXSEG7EI32_V_MF2_MF2_MASK, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5824 |
| 13115 | { PseudoVLUXSEG7EI64_V_M1_M1, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5825 |
| 13116 | { PseudoVLUXSEG7EI64_V_M1_M1_MASK, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5826 |
| 13117 | { PseudoVLUXSEG7EI64_V_M2_M1, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5827 |
| 13118 | { PseudoVLUXSEG7EI64_V_M2_M1_MASK, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5828 |
| 13119 | { PseudoVLUXSEG7EI64_V_M4_M1, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5829 |
| 13120 | { PseudoVLUXSEG7EI64_V_M4_M1_MASK, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5830 |
| 13121 | { PseudoVLUXSEG7EI64_V_M8_M1, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5831 |
| 13122 | { PseudoVLUXSEG7EI64_V_M8_M1_MASK, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5832 |
| 13123 | { PseudoVLUXSEG7EI64_V_M1_MF8, VLUXSEG7EI64_V, 0x5, 0x0 }, // 5833 |
| 13124 | { PseudoVLUXSEG7EI64_V_M1_MF8_MASK, VLUXSEG7EI64_V, 0x5, 0x0 }, // 5834 |
| 13125 | { PseudoVLUXSEG7EI64_V_M1_MF4, VLUXSEG7EI64_V, 0x6, 0x0 }, // 5835 |
| 13126 | { PseudoVLUXSEG7EI64_V_M1_MF4_MASK, VLUXSEG7EI64_V, 0x6, 0x0 }, // 5836 |
| 13127 | { PseudoVLUXSEG7EI64_V_M2_MF4, VLUXSEG7EI64_V, 0x6, 0x0 }, // 5837 |
| 13128 | { PseudoVLUXSEG7EI64_V_M2_MF4_MASK, VLUXSEG7EI64_V, 0x6, 0x0 }, // 5838 |
| 13129 | { PseudoVLUXSEG7EI64_V_M1_MF2, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5839 |
| 13130 | { PseudoVLUXSEG7EI64_V_M1_MF2_MASK, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5840 |
| 13131 | { PseudoVLUXSEG7EI64_V_M2_MF2, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5841 |
| 13132 | { PseudoVLUXSEG7EI64_V_M2_MF2_MASK, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5842 |
| 13133 | { PseudoVLUXSEG7EI64_V_M4_MF2, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5843 |
| 13134 | { PseudoVLUXSEG7EI64_V_M4_MF2_MASK, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5844 |
| 13135 | { PseudoVLUXSEG7EI8_V_M1_M1, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5845 |
| 13136 | { PseudoVLUXSEG7EI8_V_M1_M1_MASK, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5846 |
| 13137 | { PseudoVLUXSEG7EI8_V_MF2_M1, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5847 |
| 13138 | { PseudoVLUXSEG7EI8_V_MF2_M1_MASK, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5848 |
| 13139 | { PseudoVLUXSEG7EI8_V_MF4_M1, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5849 |
| 13140 | { PseudoVLUXSEG7EI8_V_MF4_M1_MASK, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5850 |
| 13141 | { PseudoVLUXSEG7EI8_V_MF8_M1, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5851 |
| 13142 | { PseudoVLUXSEG7EI8_V_MF8_M1_MASK, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5852 |
| 13143 | { PseudoVLUXSEG7EI8_V_MF8_MF8, VLUXSEG7EI8_V, 0x5, 0x0 }, // 5853 |
| 13144 | { PseudoVLUXSEG7EI8_V_MF8_MF8_MASK, VLUXSEG7EI8_V, 0x5, 0x0 }, // 5854 |
| 13145 | { PseudoVLUXSEG7EI8_V_MF4_MF4, VLUXSEG7EI8_V, 0x6, 0x0 }, // 5855 |
| 13146 | { PseudoVLUXSEG7EI8_V_MF4_MF4_MASK, VLUXSEG7EI8_V, 0x6, 0x0 }, // 5856 |
| 13147 | { PseudoVLUXSEG7EI8_V_MF8_MF4, VLUXSEG7EI8_V, 0x6, 0x0 }, // 5857 |
| 13148 | { PseudoVLUXSEG7EI8_V_MF8_MF4_MASK, VLUXSEG7EI8_V, 0x6, 0x0 }, // 5858 |
| 13149 | { PseudoVLUXSEG7EI8_V_MF2_MF2, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5859 |
| 13150 | { PseudoVLUXSEG7EI8_V_MF2_MF2_MASK, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5860 |
| 13151 | { PseudoVLUXSEG7EI8_V_MF4_MF2, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5861 |
| 13152 | { PseudoVLUXSEG7EI8_V_MF4_MF2_MASK, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5862 |
| 13153 | { PseudoVLUXSEG7EI8_V_MF8_MF2, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5863 |
| 13154 | { PseudoVLUXSEG7EI8_V_MF8_MF2_MASK, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5864 |
| 13155 | { PseudoVLUXSEG8EI16_V_M1_M1, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5865 |
| 13156 | { PseudoVLUXSEG8EI16_V_M1_M1_MASK, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5866 |
| 13157 | { PseudoVLUXSEG8EI16_V_M2_M1, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5867 |
| 13158 | { PseudoVLUXSEG8EI16_V_M2_M1_MASK, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5868 |
| 13159 | { PseudoVLUXSEG8EI16_V_MF2_M1, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5869 |
| 13160 | { PseudoVLUXSEG8EI16_V_MF2_M1_MASK, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5870 |
| 13161 | { PseudoVLUXSEG8EI16_V_MF4_M1, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5871 |
| 13162 | { PseudoVLUXSEG8EI16_V_MF4_M1_MASK, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5872 |
| 13163 | { PseudoVLUXSEG8EI16_V_MF4_MF8, VLUXSEG8EI16_V, 0x5, 0x0 }, // 5873 |
| 13164 | { PseudoVLUXSEG8EI16_V_MF4_MF8_MASK, VLUXSEG8EI16_V, 0x5, 0x0 }, // 5874 |
| 13165 | { PseudoVLUXSEG8EI16_V_MF2_MF4, VLUXSEG8EI16_V, 0x6, 0x0 }, // 5875 |
| 13166 | { PseudoVLUXSEG8EI16_V_MF2_MF4_MASK, VLUXSEG8EI16_V, 0x6, 0x0 }, // 5876 |
| 13167 | { PseudoVLUXSEG8EI16_V_MF4_MF4, VLUXSEG8EI16_V, 0x6, 0x0 }, // 5877 |
| 13168 | { PseudoVLUXSEG8EI16_V_MF4_MF4_MASK, VLUXSEG8EI16_V, 0x6, 0x0 }, // 5878 |
| 13169 | { PseudoVLUXSEG8EI16_V_M1_MF2, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5879 |
| 13170 | { PseudoVLUXSEG8EI16_V_M1_MF2_MASK, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5880 |
| 13171 | { PseudoVLUXSEG8EI16_V_MF2_MF2, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5881 |
| 13172 | { PseudoVLUXSEG8EI16_V_MF2_MF2_MASK, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5882 |
| 13173 | { PseudoVLUXSEG8EI16_V_MF4_MF2, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5883 |
| 13174 | { PseudoVLUXSEG8EI16_V_MF4_MF2_MASK, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5884 |
| 13175 | { PseudoVLUXSEG8EI32_V_M1_M1, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5885 |
| 13176 | { PseudoVLUXSEG8EI32_V_M1_M1_MASK, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5886 |
| 13177 | { PseudoVLUXSEG8EI32_V_M2_M1, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5887 |
| 13178 | { PseudoVLUXSEG8EI32_V_M2_M1_MASK, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5888 |
| 13179 | { PseudoVLUXSEG8EI32_V_M4_M1, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5889 |
| 13180 | { PseudoVLUXSEG8EI32_V_M4_M1_MASK, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5890 |
| 13181 | { PseudoVLUXSEG8EI32_V_MF2_M1, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5891 |
| 13182 | { PseudoVLUXSEG8EI32_V_MF2_M1_MASK, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5892 |
| 13183 | { PseudoVLUXSEG8EI32_V_MF2_MF8, VLUXSEG8EI32_V, 0x5, 0x0 }, // 5893 |
| 13184 | { PseudoVLUXSEG8EI32_V_MF2_MF8_MASK, VLUXSEG8EI32_V, 0x5, 0x0 }, // 5894 |
| 13185 | { PseudoVLUXSEG8EI32_V_M1_MF4, VLUXSEG8EI32_V, 0x6, 0x0 }, // 5895 |
| 13186 | { PseudoVLUXSEG8EI32_V_M1_MF4_MASK, VLUXSEG8EI32_V, 0x6, 0x0 }, // 5896 |
| 13187 | { PseudoVLUXSEG8EI32_V_MF2_MF4, VLUXSEG8EI32_V, 0x6, 0x0 }, // 5897 |
| 13188 | { PseudoVLUXSEG8EI32_V_MF2_MF4_MASK, VLUXSEG8EI32_V, 0x6, 0x0 }, // 5898 |
| 13189 | { PseudoVLUXSEG8EI32_V_M1_MF2, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5899 |
| 13190 | { PseudoVLUXSEG8EI32_V_M1_MF2_MASK, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5900 |
| 13191 | { PseudoVLUXSEG8EI32_V_M2_MF2, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5901 |
| 13192 | { PseudoVLUXSEG8EI32_V_M2_MF2_MASK, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5902 |
| 13193 | { PseudoVLUXSEG8EI32_V_MF2_MF2, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5903 |
| 13194 | { PseudoVLUXSEG8EI32_V_MF2_MF2_MASK, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5904 |
| 13195 | { PseudoVLUXSEG8EI64_V_M1_M1, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5905 |
| 13196 | { PseudoVLUXSEG8EI64_V_M1_M1_MASK, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5906 |
| 13197 | { PseudoVLUXSEG8EI64_V_M2_M1, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5907 |
| 13198 | { PseudoVLUXSEG8EI64_V_M2_M1_MASK, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5908 |
| 13199 | { PseudoVLUXSEG8EI64_V_M4_M1, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5909 |
| 13200 | { PseudoVLUXSEG8EI64_V_M4_M1_MASK, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5910 |
| 13201 | { PseudoVLUXSEG8EI64_V_M8_M1, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5911 |
| 13202 | { PseudoVLUXSEG8EI64_V_M8_M1_MASK, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5912 |
| 13203 | { PseudoVLUXSEG8EI64_V_M1_MF8, VLUXSEG8EI64_V, 0x5, 0x0 }, // 5913 |
| 13204 | { PseudoVLUXSEG8EI64_V_M1_MF8_MASK, VLUXSEG8EI64_V, 0x5, 0x0 }, // 5914 |
| 13205 | { PseudoVLUXSEG8EI64_V_M1_MF4, VLUXSEG8EI64_V, 0x6, 0x0 }, // 5915 |
| 13206 | { PseudoVLUXSEG8EI64_V_M1_MF4_MASK, VLUXSEG8EI64_V, 0x6, 0x0 }, // 5916 |
| 13207 | { PseudoVLUXSEG8EI64_V_M2_MF4, VLUXSEG8EI64_V, 0x6, 0x0 }, // 5917 |
| 13208 | { PseudoVLUXSEG8EI64_V_M2_MF4_MASK, VLUXSEG8EI64_V, 0x6, 0x0 }, // 5918 |
| 13209 | { PseudoVLUXSEG8EI64_V_M1_MF2, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5919 |
| 13210 | { PseudoVLUXSEG8EI64_V_M1_MF2_MASK, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5920 |
| 13211 | { PseudoVLUXSEG8EI64_V_M2_MF2, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5921 |
| 13212 | { PseudoVLUXSEG8EI64_V_M2_MF2_MASK, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5922 |
| 13213 | { PseudoVLUXSEG8EI64_V_M4_MF2, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5923 |
| 13214 | { PseudoVLUXSEG8EI64_V_M4_MF2_MASK, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5924 |
| 13215 | { PseudoVLUXSEG8EI8_V_M1_M1, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5925 |
| 13216 | { PseudoVLUXSEG8EI8_V_M1_M1_MASK, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5926 |
| 13217 | { PseudoVLUXSEG8EI8_V_MF2_M1, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5927 |
| 13218 | { PseudoVLUXSEG8EI8_V_MF2_M1_MASK, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5928 |
| 13219 | { PseudoVLUXSEG8EI8_V_MF4_M1, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5929 |
| 13220 | { PseudoVLUXSEG8EI8_V_MF4_M1_MASK, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5930 |
| 13221 | { PseudoVLUXSEG8EI8_V_MF8_M1, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5931 |
| 13222 | { PseudoVLUXSEG8EI8_V_MF8_M1_MASK, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5932 |
| 13223 | { PseudoVLUXSEG8EI8_V_MF8_MF8, VLUXSEG8EI8_V, 0x5, 0x0 }, // 5933 |
| 13224 | { PseudoVLUXSEG8EI8_V_MF8_MF8_MASK, VLUXSEG8EI8_V, 0x5, 0x0 }, // 5934 |
| 13225 | { PseudoVLUXSEG8EI8_V_MF4_MF4, VLUXSEG8EI8_V, 0x6, 0x0 }, // 5935 |
| 13226 | { PseudoVLUXSEG8EI8_V_MF4_MF4_MASK, VLUXSEG8EI8_V, 0x6, 0x0 }, // 5936 |
| 13227 | { PseudoVLUXSEG8EI8_V_MF8_MF4, VLUXSEG8EI8_V, 0x6, 0x0 }, // 5937 |
| 13228 | { PseudoVLUXSEG8EI8_V_MF8_MF4_MASK, VLUXSEG8EI8_V, 0x6, 0x0 }, // 5938 |
| 13229 | { PseudoVLUXSEG8EI8_V_MF2_MF2, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5939 |
| 13230 | { PseudoVLUXSEG8EI8_V_MF2_MF2_MASK, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5940 |
| 13231 | { PseudoVLUXSEG8EI8_V_MF4_MF2, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5941 |
| 13232 | { PseudoVLUXSEG8EI8_V_MF4_MF2_MASK, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5942 |
| 13233 | { PseudoVLUXSEG8EI8_V_MF8_MF2, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5943 |
| 13234 | { PseudoVLUXSEG8EI8_V_MF8_MF2_MASK, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5944 |
| 13235 | { PseudoVMACC_VV_M1, VMACC_VV, 0x0, 0x0 }, // 5945 |
| 13236 | { PseudoVMACC_VV_M1_MASK, VMACC_VV, 0x0, 0x0 }, // 5946 |
| 13237 | { PseudoVMACC_VV_M2, VMACC_VV, 0x1, 0x0 }, // 5947 |
| 13238 | { PseudoVMACC_VV_M2_MASK, VMACC_VV, 0x1, 0x0 }, // 5948 |
| 13239 | { PseudoVMACC_VV_M4, VMACC_VV, 0x2, 0x0 }, // 5949 |
| 13240 | { PseudoVMACC_VV_M4_MASK, VMACC_VV, 0x2, 0x0 }, // 5950 |
| 13241 | { PseudoVMACC_VV_M8, VMACC_VV, 0x3, 0x0 }, // 5951 |
| 13242 | { PseudoVMACC_VV_M8_MASK, VMACC_VV, 0x3, 0x0 }, // 5952 |
| 13243 | { PseudoVMACC_VV_MF8, VMACC_VV, 0x5, 0x0 }, // 5953 |
| 13244 | { PseudoVMACC_VV_MF8_MASK, VMACC_VV, 0x5, 0x0 }, // 5954 |
| 13245 | { PseudoVMACC_VV_MF4, VMACC_VV, 0x6, 0x0 }, // 5955 |
| 13246 | { PseudoVMACC_VV_MF4_MASK, VMACC_VV, 0x6, 0x0 }, // 5956 |
| 13247 | { PseudoVMACC_VV_MF2, VMACC_VV, 0x7, 0x0 }, // 5957 |
| 13248 | { PseudoVMACC_VV_MF2_MASK, VMACC_VV, 0x7, 0x0 }, // 5958 |
| 13249 | { PseudoVMACC_VX_M1, VMACC_VX, 0x0, 0x0 }, // 5959 |
| 13250 | { PseudoVMACC_VX_M1_MASK, VMACC_VX, 0x0, 0x0 }, // 5960 |
| 13251 | { PseudoVMACC_VX_M2, VMACC_VX, 0x1, 0x0 }, // 5961 |
| 13252 | { PseudoVMACC_VX_M2_MASK, VMACC_VX, 0x1, 0x0 }, // 5962 |
| 13253 | { PseudoVMACC_VX_M4, VMACC_VX, 0x2, 0x0 }, // 5963 |
| 13254 | { PseudoVMACC_VX_M4_MASK, VMACC_VX, 0x2, 0x0 }, // 5964 |
| 13255 | { PseudoVMACC_VX_M8, VMACC_VX, 0x3, 0x0 }, // 5965 |
| 13256 | { PseudoVMACC_VX_M8_MASK, VMACC_VX, 0x3, 0x0 }, // 5966 |
| 13257 | { PseudoVMACC_VX_MF8, VMACC_VX, 0x5, 0x0 }, // 5967 |
| 13258 | { PseudoVMACC_VX_MF8_MASK, VMACC_VX, 0x5, 0x0 }, // 5968 |
| 13259 | { PseudoVMACC_VX_MF4, VMACC_VX, 0x6, 0x0 }, // 5969 |
| 13260 | { PseudoVMACC_VX_MF4_MASK, VMACC_VX, 0x6, 0x0 }, // 5970 |
| 13261 | { PseudoVMACC_VX_MF2, VMACC_VX, 0x7, 0x0 }, // 5971 |
| 13262 | { PseudoVMACC_VX_MF2_MASK, VMACC_VX, 0x7, 0x0 }, // 5972 |
| 13263 | { PseudoVMADC_VI_M1, VMADC_VI, 0x0, 0x0 }, // 5973 |
| 13264 | { PseudoVMADC_VI_M2, VMADC_VI, 0x1, 0x0 }, // 5974 |
| 13265 | { PseudoVMADC_VI_M4, VMADC_VI, 0x2, 0x0 }, // 5975 |
| 13266 | { PseudoVMADC_VI_M8, VMADC_VI, 0x3, 0x0 }, // 5976 |
| 13267 | { PseudoVMADC_VI_MF8, VMADC_VI, 0x5, 0x0 }, // 5977 |
| 13268 | { PseudoVMADC_VI_MF4, VMADC_VI, 0x6, 0x0 }, // 5978 |
| 13269 | { PseudoVMADC_VI_MF2, VMADC_VI, 0x7, 0x0 }, // 5979 |
| 13270 | { PseudoVMADC_VIM_M1, VMADC_VIM, 0x0, 0x0 }, // 5980 |
| 13271 | { PseudoVMADC_VIM_M2, VMADC_VIM, 0x1, 0x0 }, // 5981 |
| 13272 | { PseudoVMADC_VIM_M4, VMADC_VIM, 0x2, 0x0 }, // 5982 |
| 13273 | { PseudoVMADC_VIM_M8, VMADC_VIM, 0x3, 0x0 }, // 5983 |
| 13274 | { PseudoVMADC_VIM_MF8, VMADC_VIM, 0x5, 0x0 }, // 5984 |
| 13275 | { PseudoVMADC_VIM_MF4, VMADC_VIM, 0x6, 0x0 }, // 5985 |
| 13276 | { PseudoVMADC_VIM_MF2, VMADC_VIM, 0x7, 0x0 }, // 5986 |
| 13277 | { PseudoVMADC_VV_M1, VMADC_VV, 0x0, 0x0 }, // 5987 |
| 13278 | { PseudoVMADC_VV_M2, VMADC_VV, 0x1, 0x0 }, // 5988 |
| 13279 | { PseudoVMADC_VV_M4, VMADC_VV, 0x2, 0x0 }, // 5989 |
| 13280 | { PseudoVMADC_VV_M8, VMADC_VV, 0x3, 0x0 }, // 5990 |
| 13281 | { PseudoVMADC_VV_MF8, VMADC_VV, 0x5, 0x0 }, // 5991 |
| 13282 | { PseudoVMADC_VV_MF4, VMADC_VV, 0x6, 0x0 }, // 5992 |
| 13283 | { PseudoVMADC_VV_MF2, VMADC_VV, 0x7, 0x0 }, // 5993 |
| 13284 | { PseudoVMADC_VVM_M1, VMADC_VVM, 0x0, 0x0 }, // 5994 |
| 13285 | { PseudoVMADC_VVM_M2, VMADC_VVM, 0x1, 0x0 }, // 5995 |
| 13286 | { PseudoVMADC_VVM_M4, VMADC_VVM, 0x2, 0x0 }, // 5996 |
| 13287 | { PseudoVMADC_VVM_M8, VMADC_VVM, 0x3, 0x0 }, // 5997 |
| 13288 | { PseudoVMADC_VVM_MF8, VMADC_VVM, 0x5, 0x0 }, // 5998 |
| 13289 | { PseudoVMADC_VVM_MF4, VMADC_VVM, 0x6, 0x0 }, // 5999 |
| 13290 | { PseudoVMADC_VVM_MF2, VMADC_VVM, 0x7, 0x0 }, // 6000 |
| 13291 | { PseudoVMADC_VX_M1, VMADC_VX, 0x0, 0x0 }, // 6001 |
| 13292 | { PseudoVMADC_VX_M2, VMADC_VX, 0x1, 0x0 }, // 6002 |
| 13293 | { PseudoVMADC_VX_M4, VMADC_VX, 0x2, 0x0 }, // 6003 |
| 13294 | { PseudoVMADC_VX_M8, VMADC_VX, 0x3, 0x0 }, // 6004 |
| 13295 | { PseudoVMADC_VX_MF8, VMADC_VX, 0x5, 0x0 }, // 6005 |
| 13296 | { PseudoVMADC_VX_MF4, VMADC_VX, 0x6, 0x0 }, // 6006 |
| 13297 | { PseudoVMADC_VX_MF2, VMADC_VX, 0x7, 0x0 }, // 6007 |
| 13298 | { PseudoVMADC_VXM_M1, VMADC_VXM, 0x0, 0x0 }, // 6008 |
| 13299 | { PseudoVMADC_VXM_M2, VMADC_VXM, 0x1, 0x0 }, // 6009 |
| 13300 | { PseudoVMADC_VXM_M4, VMADC_VXM, 0x2, 0x0 }, // 6010 |
| 13301 | { PseudoVMADC_VXM_M8, VMADC_VXM, 0x3, 0x0 }, // 6011 |
| 13302 | { PseudoVMADC_VXM_MF8, VMADC_VXM, 0x5, 0x0 }, // 6012 |
| 13303 | { PseudoVMADC_VXM_MF4, VMADC_VXM, 0x6, 0x0 }, // 6013 |
| 13304 | { PseudoVMADC_VXM_MF2, VMADC_VXM, 0x7, 0x0 }, // 6014 |
| 13305 | { PseudoVMADD_VV_M1, VMADD_VV, 0x0, 0x0 }, // 6015 |
| 13306 | { PseudoVMADD_VV_M1_MASK, VMADD_VV, 0x0, 0x0 }, // 6016 |
| 13307 | { PseudoVMADD_VV_M2, VMADD_VV, 0x1, 0x0 }, // 6017 |
| 13308 | { PseudoVMADD_VV_M2_MASK, VMADD_VV, 0x1, 0x0 }, // 6018 |
| 13309 | { PseudoVMADD_VV_M4, VMADD_VV, 0x2, 0x0 }, // 6019 |
| 13310 | { PseudoVMADD_VV_M4_MASK, VMADD_VV, 0x2, 0x0 }, // 6020 |
| 13311 | { PseudoVMADD_VV_M8, VMADD_VV, 0x3, 0x0 }, // 6021 |
| 13312 | { PseudoVMADD_VV_M8_MASK, VMADD_VV, 0x3, 0x0 }, // 6022 |
| 13313 | { PseudoVMADD_VV_MF8, VMADD_VV, 0x5, 0x0 }, // 6023 |
| 13314 | { PseudoVMADD_VV_MF8_MASK, VMADD_VV, 0x5, 0x0 }, // 6024 |
| 13315 | { PseudoVMADD_VV_MF4, VMADD_VV, 0x6, 0x0 }, // 6025 |
| 13316 | { PseudoVMADD_VV_MF4_MASK, VMADD_VV, 0x6, 0x0 }, // 6026 |
| 13317 | { PseudoVMADD_VV_MF2, VMADD_VV, 0x7, 0x0 }, // 6027 |
| 13318 | { PseudoVMADD_VV_MF2_MASK, VMADD_VV, 0x7, 0x0 }, // 6028 |
| 13319 | { PseudoVMADD_VX_M1, VMADD_VX, 0x0, 0x0 }, // 6029 |
| 13320 | { PseudoVMADD_VX_M1_MASK, VMADD_VX, 0x0, 0x0 }, // 6030 |
| 13321 | { PseudoVMADD_VX_M2, VMADD_VX, 0x1, 0x0 }, // 6031 |
| 13322 | { PseudoVMADD_VX_M2_MASK, VMADD_VX, 0x1, 0x0 }, // 6032 |
| 13323 | { PseudoVMADD_VX_M4, VMADD_VX, 0x2, 0x0 }, // 6033 |
| 13324 | { PseudoVMADD_VX_M4_MASK, VMADD_VX, 0x2, 0x0 }, // 6034 |
| 13325 | { PseudoVMADD_VX_M8, VMADD_VX, 0x3, 0x0 }, // 6035 |
| 13326 | { PseudoVMADD_VX_M8_MASK, VMADD_VX, 0x3, 0x0 }, // 6036 |
| 13327 | { PseudoVMADD_VX_MF8, VMADD_VX, 0x5, 0x0 }, // 6037 |
| 13328 | { PseudoVMADD_VX_MF8_MASK, VMADD_VX, 0x5, 0x0 }, // 6038 |
| 13329 | { PseudoVMADD_VX_MF4, VMADD_VX, 0x6, 0x0 }, // 6039 |
| 13330 | { PseudoVMADD_VX_MF4_MASK, VMADD_VX, 0x6, 0x0 }, // 6040 |
| 13331 | { PseudoVMADD_VX_MF2, VMADD_VX, 0x7, 0x0 }, // 6041 |
| 13332 | { PseudoVMADD_VX_MF2_MASK, VMADD_VX, 0x7, 0x0 }, // 6042 |
| 13333 | { PseudoVMANDN_MM_M1, VMANDN_MM, 0x0, 0x0 }, // 6043 |
| 13334 | { PseudoVMANDN_MM_M2, VMANDN_MM, 0x1, 0x0 }, // 6044 |
| 13335 | { PseudoVMANDN_MM_M4, VMANDN_MM, 0x2, 0x0 }, // 6045 |
| 13336 | { PseudoVMANDN_MM_M8, VMANDN_MM, 0x3, 0x0 }, // 6046 |
| 13337 | { PseudoVMANDN_MM_MF8, VMANDN_MM, 0x5, 0x0 }, // 6047 |
| 13338 | { PseudoVMANDN_MM_MF4, VMANDN_MM, 0x6, 0x0 }, // 6048 |
| 13339 | { PseudoVMANDN_MM_MF2, VMANDN_MM, 0x7, 0x0 }, // 6049 |
| 13340 | { PseudoVMAND_MM_M1, VMAND_MM, 0x0, 0x0 }, // 6050 |
| 13341 | { PseudoVMAND_MM_M2, VMAND_MM, 0x1, 0x0 }, // 6051 |
| 13342 | { PseudoVMAND_MM_M4, VMAND_MM, 0x2, 0x0 }, // 6052 |
| 13343 | { PseudoVMAND_MM_M8, VMAND_MM, 0x3, 0x0 }, // 6053 |
| 13344 | { PseudoVMAND_MM_MF8, VMAND_MM, 0x5, 0x0 }, // 6054 |
| 13345 | { PseudoVMAND_MM_MF4, VMAND_MM, 0x6, 0x0 }, // 6055 |
| 13346 | { PseudoVMAND_MM_MF2, VMAND_MM, 0x7, 0x0 }, // 6056 |
| 13347 | { PseudoVMAXU_VV_M1, VMAXU_VV, 0x0, 0x0 }, // 6057 |
| 13348 | { PseudoVMAXU_VV_M1_MASK, VMAXU_VV, 0x0, 0x0 }, // 6058 |
| 13349 | { PseudoVMAXU_VV_M2, VMAXU_VV, 0x1, 0x0 }, // 6059 |
| 13350 | { PseudoVMAXU_VV_M2_MASK, VMAXU_VV, 0x1, 0x0 }, // 6060 |
| 13351 | { PseudoVMAXU_VV_M4, VMAXU_VV, 0x2, 0x0 }, // 6061 |
| 13352 | { PseudoVMAXU_VV_M4_MASK, VMAXU_VV, 0x2, 0x0 }, // 6062 |
| 13353 | { PseudoVMAXU_VV_M8, VMAXU_VV, 0x3, 0x0 }, // 6063 |
| 13354 | { PseudoVMAXU_VV_M8_MASK, VMAXU_VV, 0x3, 0x0 }, // 6064 |
| 13355 | { PseudoVMAXU_VV_MF8, VMAXU_VV, 0x5, 0x0 }, // 6065 |
| 13356 | { PseudoVMAXU_VV_MF8_MASK, VMAXU_VV, 0x5, 0x0 }, // 6066 |
| 13357 | { PseudoVMAXU_VV_MF4, VMAXU_VV, 0x6, 0x0 }, // 6067 |
| 13358 | { PseudoVMAXU_VV_MF4_MASK, VMAXU_VV, 0x6, 0x0 }, // 6068 |
| 13359 | { PseudoVMAXU_VV_MF2, VMAXU_VV, 0x7, 0x0 }, // 6069 |
| 13360 | { PseudoVMAXU_VV_MF2_MASK, VMAXU_VV, 0x7, 0x0 }, // 6070 |
| 13361 | { PseudoVMAXU_VX_M1, VMAXU_VX, 0x0, 0x0 }, // 6071 |
| 13362 | { PseudoVMAXU_VX_M1_MASK, VMAXU_VX, 0x0, 0x0 }, // 6072 |
| 13363 | { PseudoVMAXU_VX_M2, VMAXU_VX, 0x1, 0x0 }, // 6073 |
| 13364 | { PseudoVMAXU_VX_M2_MASK, VMAXU_VX, 0x1, 0x0 }, // 6074 |
| 13365 | { PseudoVMAXU_VX_M4, VMAXU_VX, 0x2, 0x0 }, // 6075 |
| 13366 | { PseudoVMAXU_VX_M4_MASK, VMAXU_VX, 0x2, 0x0 }, // 6076 |
| 13367 | { PseudoVMAXU_VX_M8, VMAXU_VX, 0x3, 0x0 }, // 6077 |
| 13368 | { PseudoVMAXU_VX_M8_MASK, VMAXU_VX, 0x3, 0x0 }, // 6078 |
| 13369 | { PseudoVMAXU_VX_MF8, VMAXU_VX, 0x5, 0x0 }, // 6079 |
| 13370 | { PseudoVMAXU_VX_MF8_MASK, VMAXU_VX, 0x5, 0x0 }, // 6080 |
| 13371 | { PseudoVMAXU_VX_MF4, VMAXU_VX, 0x6, 0x0 }, // 6081 |
| 13372 | { PseudoVMAXU_VX_MF4_MASK, VMAXU_VX, 0x6, 0x0 }, // 6082 |
| 13373 | { PseudoVMAXU_VX_MF2, VMAXU_VX, 0x7, 0x0 }, // 6083 |
| 13374 | { PseudoVMAXU_VX_MF2_MASK, VMAXU_VX, 0x7, 0x0 }, // 6084 |
| 13375 | { PseudoVMAX_VV_M1, VMAX_VV, 0x0, 0x0 }, // 6085 |
| 13376 | { PseudoVMAX_VV_M1_MASK, VMAX_VV, 0x0, 0x0 }, // 6086 |
| 13377 | { PseudoVMAX_VV_M2, VMAX_VV, 0x1, 0x0 }, // 6087 |
| 13378 | { PseudoVMAX_VV_M2_MASK, VMAX_VV, 0x1, 0x0 }, // 6088 |
| 13379 | { PseudoVMAX_VV_M4, VMAX_VV, 0x2, 0x0 }, // 6089 |
| 13380 | { PseudoVMAX_VV_M4_MASK, VMAX_VV, 0x2, 0x0 }, // 6090 |
| 13381 | { PseudoVMAX_VV_M8, VMAX_VV, 0x3, 0x0 }, // 6091 |
| 13382 | { PseudoVMAX_VV_M8_MASK, VMAX_VV, 0x3, 0x0 }, // 6092 |
| 13383 | { PseudoVMAX_VV_MF8, VMAX_VV, 0x5, 0x0 }, // 6093 |
| 13384 | { PseudoVMAX_VV_MF8_MASK, VMAX_VV, 0x5, 0x0 }, // 6094 |
| 13385 | { PseudoVMAX_VV_MF4, VMAX_VV, 0x6, 0x0 }, // 6095 |
| 13386 | { PseudoVMAX_VV_MF4_MASK, VMAX_VV, 0x6, 0x0 }, // 6096 |
| 13387 | { PseudoVMAX_VV_MF2, VMAX_VV, 0x7, 0x0 }, // 6097 |
| 13388 | { PseudoVMAX_VV_MF2_MASK, VMAX_VV, 0x7, 0x0 }, // 6098 |
| 13389 | { PseudoVMAX_VX_M1, VMAX_VX, 0x0, 0x0 }, // 6099 |
| 13390 | { PseudoVMAX_VX_M1_MASK, VMAX_VX, 0x0, 0x0 }, // 6100 |
| 13391 | { PseudoVMAX_VX_M2, VMAX_VX, 0x1, 0x0 }, // 6101 |
| 13392 | { PseudoVMAX_VX_M2_MASK, VMAX_VX, 0x1, 0x0 }, // 6102 |
| 13393 | { PseudoVMAX_VX_M4, VMAX_VX, 0x2, 0x0 }, // 6103 |
| 13394 | { PseudoVMAX_VX_M4_MASK, VMAX_VX, 0x2, 0x0 }, // 6104 |
| 13395 | { PseudoVMAX_VX_M8, VMAX_VX, 0x3, 0x0 }, // 6105 |
| 13396 | { PseudoVMAX_VX_M8_MASK, VMAX_VX, 0x3, 0x0 }, // 6106 |
| 13397 | { PseudoVMAX_VX_MF8, VMAX_VX, 0x5, 0x0 }, // 6107 |
| 13398 | { PseudoVMAX_VX_MF8_MASK, VMAX_VX, 0x5, 0x0 }, // 6108 |
| 13399 | { PseudoVMAX_VX_MF4, VMAX_VX, 0x6, 0x0 }, // 6109 |
| 13400 | { PseudoVMAX_VX_MF4_MASK, VMAX_VX, 0x6, 0x0 }, // 6110 |
| 13401 | { PseudoVMAX_VX_MF2, VMAX_VX, 0x7, 0x0 }, // 6111 |
| 13402 | { PseudoVMAX_VX_MF2_MASK, VMAX_VX, 0x7, 0x0 }, // 6112 |
| 13403 | { PseudoVMERGE_VIM_M1, VMERGE_VIM, 0x0, 0x0 }, // 6113 |
| 13404 | { PseudoVMERGE_VIM_M2, VMERGE_VIM, 0x1, 0x0 }, // 6114 |
| 13405 | { PseudoVMERGE_VIM_M4, VMERGE_VIM, 0x2, 0x0 }, // 6115 |
| 13406 | { PseudoVMERGE_VIM_M8, VMERGE_VIM, 0x3, 0x0 }, // 6116 |
| 13407 | { PseudoVMERGE_VIM_MF8, VMERGE_VIM, 0x5, 0x0 }, // 6117 |
| 13408 | { PseudoVMERGE_VIM_MF4, VMERGE_VIM, 0x6, 0x0 }, // 6118 |
| 13409 | { PseudoVMERGE_VIM_MF2, VMERGE_VIM, 0x7, 0x0 }, // 6119 |
| 13410 | { PseudoVMERGE_VVM_M1, VMERGE_VVM, 0x0, 0x0 }, // 6120 |
| 13411 | { PseudoVMERGE_VVM_M2, VMERGE_VVM, 0x1, 0x0 }, // 6121 |
| 13412 | { PseudoVMERGE_VVM_M4, VMERGE_VVM, 0x2, 0x0 }, // 6122 |
| 13413 | { PseudoVMERGE_VVM_M8, VMERGE_VVM, 0x3, 0x0 }, // 6123 |
| 13414 | { PseudoVMERGE_VVM_MF8, VMERGE_VVM, 0x5, 0x0 }, // 6124 |
| 13415 | { PseudoVMERGE_VVM_MF4, VMERGE_VVM, 0x6, 0x0 }, // 6125 |
| 13416 | { PseudoVMERGE_VVM_MF2, VMERGE_VVM, 0x7, 0x0 }, // 6126 |
| 13417 | { PseudoVMERGE_VXM_M1, VMERGE_VXM, 0x0, 0x0 }, // 6127 |
| 13418 | { PseudoVMERGE_VXM_M2, VMERGE_VXM, 0x1, 0x0 }, // 6128 |
| 13419 | { PseudoVMERGE_VXM_M4, VMERGE_VXM, 0x2, 0x0 }, // 6129 |
| 13420 | { PseudoVMERGE_VXM_M8, VMERGE_VXM, 0x3, 0x0 }, // 6130 |
| 13421 | { PseudoVMERGE_VXM_MF8, VMERGE_VXM, 0x5, 0x0 }, // 6131 |
| 13422 | { PseudoVMERGE_VXM_MF4, VMERGE_VXM, 0x6, 0x0 }, // 6132 |
| 13423 | { PseudoVMERGE_VXM_MF2, VMERGE_VXM, 0x7, 0x0 }, // 6133 |
| 13424 | { PseudoVMFEQ_VFPR16_M1, VMFEQ_VF, 0x0, 0x0 }, // 6134 |
| 13425 | { PseudoVMFEQ_VFPR16_M1_MASK, VMFEQ_VF, 0x0, 0x0 }, // 6135 |
| 13426 | { PseudoVMFEQ_VFPR32_M1, VMFEQ_VF, 0x0, 0x0 }, // 6136 |
| 13427 | { PseudoVMFEQ_VFPR32_M1_MASK, VMFEQ_VF, 0x0, 0x0 }, // 6137 |
| 13428 | { PseudoVMFEQ_VFPR64_M1, VMFEQ_VF, 0x0, 0x0 }, // 6138 |
| 13429 | { PseudoVMFEQ_VFPR64_M1_MASK, VMFEQ_VF, 0x0, 0x0 }, // 6139 |
| 13430 | { PseudoVMFEQ_VFPR16_M2, VMFEQ_VF, 0x1, 0x0 }, // 6140 |
| 13431 | { PseudoVMFEQ_VFPR16_M2_MASK, VMFEQ_VF, 0x1, 0x0 }, // 6141 |
| 13432 | { PseudoVMFEQ_VFPR32_M2, VMFEQ_VF, 0x1, 0x0 }, // 6142 |
| 13433 | { PseudoVMFEQ_VFPR32_M2_MASK, VMFEQ_VF, 0x1, 0x0 }, // 6143 |
| 13434 | { PseudoVMFEQ_VFPR64_M2, VMFEQ_VF, 0x1, 0x0 }, // 6144 |
| 13435 | { PseudoVMFEQ_VFPR64_M2_MASK, VMFEQ_VF, 0x1, 0x0 }, // 6145 |
| 13436 | { PseudoVMFEQ_VFPR16_M4, VMFEQ_VF, 0x2, 0x0 }, // 6146 |
| 13437 | { PseudoVMFEQ_VFPR16_M4_MASK, VMFEQ_VF, 0x2, 0x0 }, // 6147 |
| 13438 | { PseudoVMFEQ_VFPR32_M4, VMFEQ_VF, 0x2, 0x0 }, // 6148 |
| 13439 | { PseudoVMFEQ_VFPR32_M4_MASK, VMFEQ_VF, 0x2, 0x0 }, // 6149 |
| 13440 | { PseudoVMFEQ_VFPR64_M4, VMFEQ_VF, 0x2, 0x0 }, // 6150 |
| 13441 | { PseudoVMFEQ_VFPR64_M4_MASK, VMFEQ_VF, 0x2, 0x0 }, // 6151 |
| 13442 | { PseudoVMFEQ_VFPR16_M8, VMFEQ_VF, 0x3, 0x0 }, // 6152 |
| 13443 | { PseudoVMFEQ_VFPR16_M8_MASK, VMFEQ_VF, 0x3, 0x0 }, // 6153 |
| 13444 | { PseudoVMFEQ_VFPR32_M8, VMFEQ_VF, 0x3, 0x0 }, // 6154 |
| 13445 | { PseudoVMFEQ_VFPR32_M8_MASK, VMFEQ_VF, 0x3, 0x0 }, // 6155 |
| 13446 | { PseudoVMFEQ_VFPR64_M8, VMFEQ_VF, 0x3, 0x0 }, // 6156 |
| 13447 | { PseudoVMFEQ_VFPR64_M8_MASK, VMFEQ_VF, 0x3, 0x0 }, // 6157 |
| 13448 | { PseudoVMFEQ_VFPR16_MF4, VMFEQ_VF, 0x6, 0x0 }, // 6158 |
| 13449 | { PseudoVMFEQ_VFPR16_MF4_MASK, VMFEQ_VF, 0x6, 0x0 }, // 6159 |
| 13450 | { PseudoVMFEQ_VFPR16_MF2, VMFEQ_VF, 0x7, 0x0 }, // 6160 |
| 13451 | { PseudoVMFEQ_VFPR16_MF2_MASK, VMFEQ_VF, 0x7, 0x0 }, // 6161 |
| 13452 | { PseudoVMFEQ_VFPR32_MF2, VMFEQ_VF, 0x7, 0x0 }, // 6162 |
| 13453 | { PseudoVMFEQ_VFPR32_MF2_MASK, VMFEQ_VF, 0x7, 0x0 }, // 6163 |
| 13454 | { PseudoVMFEQ_VV_M1, VMFEQ_VV, 0x0, 0x0 }, // 6164 |
| 13455 | { PseudoVMFEQ_VV_M1_MASK, VMFEQ_VV, 0x0, 0x0 }, // 6165 |
| 13456 | { PseudoVMFEQ_VV_M2, VMFEQ_VV, 0x1, 0x0 }, // 6166 |
| 13457 | { PseudoVMFEQ_VV_M2_MASK, VMFEQ_VV, 0x1, 0x0 }, // 6167 |
| 13458 | { PseudoVMFEQ_VV_M4, VMFEQ_VV, 0x2, 0x0 }, // 6168 |
| 13459 | { PseudoVMFEQ_VV_M4_MASK, VMFEQ_VV, 0x2, 0x0 }, // 6169 |
| 13460 | { PseudoVMFEQ_VV_M8, VMFEQ_VV, 0x3, 0x0 }, // 6170 |
| 13461 | { PseudoVMFEQ_VV_M8_MASK, VMFEQ_VV, 0x3, 0x0 }, // 6171 |
| 13462 | { PseudoVMFEQ_VV_MF4, VMFEQ_VV, 0x6, 0x0 }, // 6172 |
| 13463 | { PseudoVMFEQ_VV_MF4_MASK, VMFEQ_VV, 0x6, 0x0 }, // 6173 |
| 13464 | { PseudoVMFEQ_VV_MF2, VMFEQ_VV, 0x7, 0x0 }, // 6174 |
| 13465 | { PseudoVMFEQ_VV_MF2_MASK, VMFEQ_VV, 0x7, 0x0 }, // 6175 |
| 13466 | { PseudoVMFGE_VFPR16_M1, VMFGE_VF, 0x0, 0x0 }, // 6176 |
| 13467 | { PseudoVMFGE_VFPR16_M1_MASK, VMFGE_VF, 0x0, 0x0 }, // 6177 |
| 13468 | { PseudoVMFGE_VFPR32_M1, VMFGE_VF, 0x0, 0x0 }, // 6178 |
| 13469 | { PseudoVMFGE_VFPR32_M1_MASK, VMFGE_VF, 0x0, 0x0 }, // 6179 |
| 13470 | { PseudoVMFGE_VFPR64_M1, VMFGE_VF, 0x0, 0x0 }, // 6180 |
| 13471 | { PseudoVMFGE_VFPR64_M1_MASK, VMFGE_VF, 0x0, 0x0 }, // 6181 |
| 13472 | { PseudoVMFGE_VFPR16_M2, VMFGE_VF, 0x1, 0x0 }, // 6182 |
| 13473 | { PseudoVMFGE_VFPR16_M2_MASK, VMFGE_VF, 0x1, 0x0 }, // 6183 |
| 13474 | { PseudoVMFGE_VFPR32_M2, VMFGE_VF, 0x1, 0x0 }, // 6184 |
| 13475 | { PseudoVMFGE_VFPR32_M2_MASK, VMFGE_VF, 0x1, 0x0 }, // 6185 |
| 13476 | { PseudoVMFGE_VFPR64_M2, VMFGE_VF, 0x1, 0x0 }, // 6186 |
| 13477 | { PseudoVMFGE_VFPR64_M2_MASK, VMFGE_VF, 0x1, 0x0 }, // 6187 |
| 13478 | { PseudoVMFGE_VFPR16_M4, VMFGE_VF, 0x2, 0x0 }, // 6188 |
| 13479 | { PseudoVMFGE_VFPR16_M4_MASK, VMFGE_VF, 0x2, 0x0 }, // 6189 |
| 13480 | { PseudoVMFGE_VFPR32_M4, VMFGE_VF, 0x2, 0x0 }, // 6190 |
| 13481 | { PseudoVMFGE_VFPR32_M4_MASK, VMFGE_VF, 0x2, 0x0 }, // 6191 |
| 13482 | { PseudoVMFGE_VFPR64_M4, VMFGE_VF, 0x2, 0x0 }, // 6192 |
| 13483 | { PseudoVMFGE_VFPR64_M4_MASK, VMFGE_VF, 0x2, 0x0 }, // 6193 |
| 13484 | { PseudoVMFGE_VFPR16_M8, VMFGE_VF, 0x3, 0x0 }, // 6194 |
| 13485 | { PseudoVMFGE_VFPR16_M8_MASK, VMFGE_VF, 0x3, 0x0 }, // 6195 |
| 13486 | { PseudoVMFGE_VFPR32_M8, VMFGE_VF, 0x3, 0x0 }, // 6196 |
| 13487 | { PseudoVMFGE_VFPR32_M8_MASK, VMFGE_VF, 0x3, 0x0 }, // 6197 |
| 13488 | { PseudoVMFGE_VFPR64_M8, VMFGE_VF, 0x3, 0x0 }, // 6198 |
| 13489 | { PseudoVMFGE_VFPR64_M8_MASK, VMFGE_VF, 0x3, 0x0 }, // 6199 |
| 13490 | { PseudoVMFGE_VFPR16_MF4, VMFGE_VF, 0x6, 0x0 }, // 6200 |
| 13491 | { PseudoVMFGE_VFPR16_MF4_MASK, VMFGE_VF, 0x6, 0x0 }, // 6201 |
| 13492 | { PseudoVMFGE_VFPR16_MF2, VMFGE_VF, 0x7, 0x0 }, // 6202 |
| 13493 | { PseudoVMFGE_VFPR16_MF2_MASK, VMFGE_VF, 0x7, 0x0 }, // 6203 |
| 13494 | { PseudoVMFGE_VFPR32_MF2, VMFGE_VF, 0x7, 0x0 }, // 6204 |
| 13495 | { PseudoVMFGE_VFPR32_MF2_MASK, VMFGE_VF, 0x7, 0x0 }, // 6205 |
| 13496 | { PseudoVMFGT_VFPR16_M1, VMFGT_VF, 0x0, 0x0 }, // 6206 |
| 13497 | { PseudoVMFGT_VFPR16_M1_MASK, VMFGT_VF, 0x0, 0x0 }, // 6207 |
| 13498 | { PseudoVMFGT_VFPR32_M1, VMFGT_VF, 0x0, 0x0 }, // 6208 |
| 13499 | { PseudoVMFGT_VFPR32_M1_MASK, VMFGT_VF, 0x0, 0x0 }, // 6209 |
| 13500 | { PseudoVMFGT_VFPR64_M1, VMFGT_VF, 0x0, 0x0 }, // 6210 |
| 13501 | { PseudoVMFGT_VFPR64_M1_MASK, VMFGT_VF, 0x0, 0x0 }, // 6211 |
| 13502 | { PseudoVMFGT_VFPR16_M2, VMFGT_VF, 0x1, 0x0 }, // 6212 |
| 13503 | { PseudoVMFGT_VFPR16_M2_MASK, VMFGT_VF, 0x1, 0x0 }, // 6213 |
| 13504 | { PseudoVMFGT_VFPR32_M2, VMFGT_VF, 0x1, 0x0 }, // 6214 |
| 13505 | { PseudoVMFGT_VFPR32_M2_MASK, VMFGT_VF, 0x1, 0x0 }, // 6215 |
| 13506 | { PseudoVMFGT_VFPR64_M2, VMFGT_VF, 0x1, 0x0 }, // 6216 |
| 13507 | { PseudoVMFGT_VFPR64_M2_MASK, VMFGT_VF, 0x1, 0x0 }, // 6217 |
| 13508 | { PseudoVMFGT_VFPR16_M4, VMFGT_VF, 0x2, 0x0 }, // 6218 |
| 13509 | { PseudoVMFGT_VFPR16_M4_MASK, VMFGT_VF, 0x2, 0x0 }, // 6219 |
| 13510 | { PseudoVMFGT_VFPR32_M4, VMFGT_VF, 0x2, 0x0 }, // 6220 |
| 13511 | { PseudoVMFGT_VFPR32_M4_MASK, VMFGT_VF, 0x2, 0x0 }, // 6221 |
| 13512 | { PseudoVMFGT_VFPR64_M4, VMFGT_VF, 0x2, 0x0 }, // 6222 |
| 13513 | { PseudoVMFGT_VFPR64_M4_MASK, VMFGT_VF, 0x2, 0x0 }, // 6223 |
| 13514 | { PseudoVMFGT_VFPR16_M8, VMFGT_VF, 0x3, 0x0 }, // 6224 |
| 13515 | { PseudoVMFGT_VFPR16_M8_MASK, VMFGT_VF, 0x3, 0x0 }, // 6225 |
| 13516 | { PseudoVMFGT_VFPR32_M8, VMFGT_VF, 0x3, 0x0 }, // 6226 |
| 13517 | { PseudoVMFGT_VFPR32_M8_MASK, VMFGT_VF, 0x3, 0x0 }, // 6227 |
| 13518 | { PseudoVMFGT_VFPR64_M8, VMFGT_VF, 0x3, 0x0 }, // 6228 |
| 13519 | { PseudoVMFGT_VFPR64_M8_MASK, VMFGT_VF, 0x3, 0x0 }, // 6229 |
| 13520 | { PseudoVMFGT_VFPR16_MF4, VMFGT_VF, 0x6, 0x0 }, // 6230 |
| 13521 | { PseudoVMFGT_VFPR16_MF4_MASK, VMFGT_VF, 0x6, 0x0 }, // 6231 |
| 13522 | { PseudoVMFGT_VFPR16_MF2, VMFGT_VF, 0x7, 0x0 }, // 6232 |
| 13523 | { PseudoVMFGT_VFPR16_MF2_MASK, VMFGT_VF, 0x7, 0x0 }, // 6233 |
| 13524 | { PseudoVMFGT_VFPR32_MF2, VMFGT_VF, 0x7, 0x0 }, // 6234 |
| 13525 | { PseudoVMFGT_VFPR32_MF2_MASK, VMFGT_VF, 0x7, 0x0 }, // 6235 |
| 13526 | { PseudoVMFLE_VFPR16_M1, VMFLE_VF, 0x0, 0x0 }, // 6236 |
| 13527 | { PseudoVMFLE_VFPR16_M1_MASK, VMFLE_VF, 0x0, 0x0 }, // 6237 |
| 13528 | { PseudoVMFLE_VFPR32_M1, VMFLE_VF, 0x0, 0x0 }, // 6238 |
| 13529 | { PseudoVMFLE_VFPR32_M1_MASK, VMFLE_VF, 0x0, 0x0 }, // 6239 |
| 13530 | { PseudoVMFLE_VFPR64_M1, VMFLE_VF, 0x0, 0x0 }, // 6240 |
| 13531 | { PseudoVMFLE_VFPR64_M1_MASK, VMFLE_VF, 0x0, 0x0 }, // 6241 |
| 13532 | { PseudoVMFLE_VFPR16_M2, VMFLE_VF, 0x1, 0x0 }, // 6242 |
| 13533 | { PseudoVMFLE_VFPR16_M2_MASK, VMFLE_VF, 0x1, 0x0 }, // 6243 |
| 13534 | { PseudoVMFLE_VFPR32_M2, VMFLE_VF, 0x1, 0x0 }, // 6244 |
| 13535 | { PseudoVMFLE_VFPR32_M2_MASK, VMFLE_VF, 0x1, 0x0 }, // 6245 |
| 13536 | { PseudoVMFLE_VFPR64_M2, VMFLE_VF, 0x1, 0x0 }, // 6246 |
| 13537 | { PseudoVMFLE_VFPR64_M2_MASK, VMFLE_VF, 0x1, 0x0 }, // 6247 |
| 13538 | { PseudoVMFLE_VFPR16_M4, VMFLE_VF, 0x2, 0x0 }, // 6248 |
| 13539 | { PseudoVMFLE_VFPR16_M4_MASK, VMFLE_VF, 0x2, 0x0 }, // 6249 |
| 13540 | { PseudoVMFLE_VFPR32_M4, VMFLE_VF, 0x2, 0x0 }, // 6250 |
| 13541 | { PseudoVMFLE_VFPR32_M4_MASK, VMFLE_VF, 0x2, 0x0 }, // 6251 |
| 13542 | { PseudoVMFLE_VFPR64_M4, VMFLE_VF, 0x2, 0x0 }, // 6252 |
| 13543 | { PseudoVMFLE_VFPR64_M4_MASK, VMFLE_VF, 0x2, 0x0 }, // 6253 |
| 13544 | { PseudoVMFLE_VFPR16_M8, VMFLE_VF, 0x3, 0x0 }, // 6254 |
| 13545 | { PseudoVMFLE_VFPR16_M8_MASK, VMFLE_VF, 0x3, 0x0 }, // 6255 |
| 13546 | { PseudoVMFLE_VFPR32_M8, VMFLE_VF, 0x3, 0x0 }, // 6256 |
| 13547 | { PseudoVMFLE_VFPR32_M8_MASK, VMFLE_VF, 0x3, 0x0 }, // 6257 |
| 13548 | { PseudoVMFLE_VFPR64_M8, VMFLE_VF, 0x3, 0x0 }, // 6258 |
| 13549 | { PseudoVMFLE_VFPR64_M8_MASK, VMFLE_VF, 0x3, 0x0 }, // 6259 |
| 13550 | { PseudoVMFLE_VFPR16_MF4, VMFLE_VF, 0x6, 0x0 }, // 6260 |
| 13551 | { PseudoVMFLE_VFPR16_MF4_MASK, VMFLE_VF, 0x6, 0x0 }, // 6261 |
| 13552 | { PseudoVMFLE_VFPR16_MF2, VMFLE_VF, 0x7, 0x0 }, // 6262 |
| 13553 | { PseudoVMFLE_VFPR16_MF2_MASK, VMFLE_VF, 0x7, 0x0 }, // 6263 |
| 13554 | { PseudoVMFLE_VFPR32_MF2, VMFLE_VF, 0x7, 0x0 }, // 6264 |
| 13555 | { PseudoVMFLE_VFPR32_MF2_MASK, VMFLE_VF, 0x7, 0x0 }, // 6265 |
| 13556 | { PseudoVMFLE_VV_M1, VMFLE_VV, 0x0, 0x0 }, // 6266 |
| 13557 | { PseudoVMFLE_VV_M1_MASK, VMFLE_VV, 0x0, 0x0 }, // 6267 |
| 13558 | { PseudoVMFLE_VV_M2, VMFLE_VV, 0x1, 0x0 }, // 6268 |
| 13559 | { PseudoVMFLE_VV_M2_MASK, VMFLE_VV, 0x1, 0x0 }, // 6269 |
| 13560 | { PseudoVMFLE_VV_M4, VMFLE_VV, 0x2, 0x0 }, // 6270 |
| 13561 | { PseudoVMFLE_VV_M4_MASK, VMFLE_VV, 0x2, 0x0 }, // 6271 |
| 13562 | { PseudoVMFLE_VV_M8, VMFLE_VV, 0x3, 0x0 }, // 6272 |
| 13563 | { PseudoVMFLE_VV_M8_MASK, VMFLE_VV, 0x3, 0x0 }, // 6273 |
| 13564 | { PseudoVMFLE_VV_MF4, VMFLE_VV, 0x6, 0x0 }, // 6274 |
| 13565 | { PseudoVMFLE_VV_MF4_MASK, VMFLE_VV, 0x6, 0x0 }, // 6275 |
| 13566 | { PseudoVMFLE_VV_MF2, VMFLE_VV, 0x7, 0x0 }, // 6276 |
| 13567 | { PseudoVMFLE_VV_MF2_MASK, VMFLE_VV, 0x7, 0x0 }, // 6277 |
| 13568 | { PseudoVMFLT_VFPR16_M1, VMFLT_VF, 0x0, 0x0 }, // 6278 |
| 13569 | { PseudoVMFLT_VFPR16_M1_MASK, VMFLT_VF, 0x0, 0x0 }, // 6279 |
| 13570 | { PseudoVMFLT_VFPR32_M1, VMFLT_VF, 0x0, 0x0 }, // 6280 |
| 13571 | { PseudoVMFLT_VFPR32_M1_MASK, VMFLT_VF, 0x0, 0x0 }, // 6281 |
| 13572 | { PseudoVMFLT_VFPR64_M1, VMFLT_VF, 0x0, 0x0 }, // 6282 |
| 13573 | { PseudoVMFLT_VFPR64_M1_MASK, VMFLT_VF, 0x0, 0x0 }, // 6283 |
| 13574 | { PseudoVMFLT_VFPR16_M2, VMFLT_VF, 0x1, 0x0 }, // 6284 |
| 13575 | { PseudoVMFLT_VFPR16_M2_MASK, VMFLT_VF, 0x1, 0x0 }, // 6285 |
| 13576 | { PseudoVMFLT_VFPR32_M2, VMFLT_VF, 0x1, 0x0 }, // 6286 |
| 13577 | { PseudoVMFLT_VFPR32_M2_MASK, VMFLT_VF, 0x1, 0x0 }, // 6287 |
| 13578 | { PseudoVMFLT_VFPR64_M2, VMFLT_VF, 0x1, 0x0 }, // 6288 |
| 13579 | { PseudoVMFLT_VFPR64_M2_MASK, VMFLT_VF, 0x1, 0x0 }, // 6289 |
| 13580 | { PseudoVMFLT_VFPR16_M4, VMFLT_VF, 0x2, 0x0 }, // 6290 |
| 13581 | { PseudoVMFLT_VFPR16_M4_MASK, VMFLT_VF, 0x2, 0x0 }, // 6291 |
| 13582 | { PseudoVMFLT_VFPR32_M4, VMFLT_VF, 0x2, 0x0 }, // 6292 |
| 13583 | { PseudoVMFLT_VFPR32_M4_MASK, VMFLT_VF, 0x2, 0x0 }, // 6293 |
| 13584 | { PseudoVMFLT_VFPR64_M4, VMFLT_VF, 0x2, 0x0 }, // 6294 |
| 13585 | { PseudoVMFLT_VFPR64_M4_MASK, VMFLT_VF, 0x2, 0x0 }, // 6295 |
| 13586 | { PseudoVMFLT_VFPR16_M8, VMFLT_VF, 0x3, 0x0 }, // 6296 |
| 13587 | { PseudoVMFLT_VFPR16_M8_MASK, VMFLT_VF, 0x3, 0x0 }, // 6297 |
| 13588 | { PseudoVMFLT_VFPR32_M8, VMFLT_VF, 0x3, 0x0 }, // 6298 |
| 13589 | { PseudoVMFLT_VFPR32_M8_MASK, VMFLT_VF, 0x3, 0x0 }, // 6299 |
| 13590 | { PseudoVMFLT_VFPR64_M8, VMFLT_VF, 0x3, 0x0 }, // 6300 |
| 13591 | { PseudoVMFLT_VFPR64_M8_MASK, VMFLT_VF, 0x3, 0x0 }, // 6301 |
| 13592 | { PseudoVMFLT_VFPR16_MF4, VMFLT_VF, 0x6, 0x0 }, // 6302 |
| 13593 | { PseudoVMFLT_VFPR16_MF4_MASK, VMFLT_VF, 0x6, 0x0 }, // 6303 |
| 13594 | { PseudoVMFLT_VFPR16_MF2, VMFLT_VF, 0x7, 0x0 }, // 6304 |
| 13595 | { PseudoVMFLT_VFPR16_MF2_MASK, VMFLT_VF, 0x7, 0x0 }, // 6305 |
| 13596 | { PseudoVMFLT_VFPR32_MF2, VMFLT_VF, 0x7, 0x0 }, // 6306 |
| 13597 | { PseudoVMFLT_VFPR32_MF2_MASK, VMFLT_VF, 0x7, 0x0 }, // 6307 |
| 13598 | { PseudoVMFLT_VV_M1, VMFLT_VV, 0x0, 0x0 }, // 6308 |
| 13599 | { PseudoVMFLT_VV_M1_MASK, VMFLT_VV, 0x0, 0x0 }, // 6309 |
| 13600 | { PseudoVMFLT_VV_M2, VMFLT_VV, 0x1, 0x0 }, // 6310 |
| 13601 | { PseudoVMFLT_VV_M2_MASK, VMFLT_VV, 0x1, 0x0 }, // 6311 |
| 13602 | { PseudoVMFLT_VV_M4, VMFLT_VV, 0x2, 0x0 }, // 6312 |
| 13603 | { PseudoVMFLT_VV_M4_MASK, VMFLT_VV, 0x2, 0x0 }, // 6313 |
| 13604 | { PseudoVMFLT_VV_M8, VMFLT_VV, 0x3, 0x0 }, // 6314 |
| 13605 | { PseudoVMFLT_VV_M8_MASK, VMFLT_VV, 0x3, 0x0 }, // 6315 |
| 13606 | { PseudoVMFLT_VV_MF4, VMFLT_VV, 0x6, 0x0 }, // 6316 |
| 13607 | { PseudoVMFLT_VV_MF4_MASK, VMFLT_VV, 0x6, 0x0 }, // 6317 |
| 13608 | { PseudoVMFLT_VV_MF2, VMFLT_VV, 0x7, 0x0 }, // 6318 |
| 13609 | { PseudoVMFLT_VV_MF2_MASK, VMFLT_VV, 0x7, 0x0 }, // 6319 |
| 13610 | { PseudoVMFNE_VFPR16_M1, VMFNE_VF, 0x0, 0x0 }, // 6320 |
| 13611 | { PseudoVMFNE_VFPR16_M1_MASK, VMFNE_VF, 0x0, 0x0 }, // 6321 |
| 13612 | { PseudoVMFNE_VFPR32_M1, VMFNE_VF, 0x0, 0x0 }, // 6322 |
| 13613 | { PseudoVMFNE_VFPR32_M1_MASK, VMFNE_VF, 0x0, 0x0 }, // 6323 |
| 13614 | { PseudoVMFNE_VFPR64_M1, VMFNE_VF, 0x0, 0x0 }, // 6324 |
| 13615 | { PseudoVMFNE_VFPR64_M1_MASK, VMFNE_VF, 0x0, 0x0 }, // 6325 |
| 13616 | { PseudoVMFNE_VFPR16_M2, VMFNE_VF, 0x1, 0x0 }, // 6326 |
| 13617 | { PseudoVMFNE_VFPR16_M2_MASK, VMFNE_VF, 0x1, 0x0 }, // 6327 |
| 13618 | { PseudoVMFNE_VFPR32_M2, VMFNE_VF, 0x1, 0x0 }, // 6328 |
| 13619 | { PseudoVMFNE_VFPR32_M2_MASK, VMFNE_VF, 0x1, 0x0 }, // 6329 |
| 13620 | { PseudoVMFNE_VFPR64_M2, VMFNE_VF, 0x1, 0x0 }, // 6330 |
| 13621 | { PseudoVMFNE_VFPR64_M2_MASK, VMFNE_VF, 0x1, 0x0 }, // 6331 |
| 13622 | { PseudoVMFNE_VFPR16_M4, VMFNE_VF, 0x2, 0x0 }, // 6332 |
| 13623 | { PseudoVMFNE_VFPR16_M4_MASK, VMFNE_VF, 0x2, 0x0 }, // 6333 |
| 13624 | { PseudoVMFNE_VFPR32_M4, VMFNE_VF, 0x2, 0x0 }, // 6334 |
| 13625 | { PseudoVMFNE_VFPR32_M4_MASK, VMFNE_VF, 0x2, 0x0 }, // 6335 |
| 13626 | { PseudoVMFNE_VFPR64_M4, VMFNE_VF, 0x2, 0x0 }, // 6336 |
| 13627 | { PseudoVMFNE_VFPR64_M4_MASK, VMFNE_VF, 0x2, 0x0 }, // 6337 |
| 13628 | { PseudoVMFNE_VFPR16_M8, VMFNE_VF, 0x3, 0x0 }, // 6338 |
| 13629 | { PseudoVMFNE_VFPR16_M8_MASK, VMFNE_VF, 0x3, 0x0 }, // 6339 |
| 13630 | { PseudoVMFNE_VFPR32_M8, VMFNE_VF, 0x3, 0x0 }, // 6340 |
| 13631 | { PseudoVMFNE_VFPR32_M8_MASK, VMFNE_VF, 0x3, 0x0 }, // 6341 |
| 13632 | { PseudoVMFNE_VFPR64_M8, VMFNE_VF, 0x3, 0x0 }, // 6342 |
| 13633 | { PseudoVMFNE_VFPR64_M8_MASK, VMFNE_VF, 0x3, 0x0 }, // 6343 |
| 13634 | { PseudoVMFNE_VFPR16_MF4, VMFNE_VF, 0x6, 0x0 }, // 6344 |
| 13635 | { PseudoVMFNE_VFPR16_MF4_MASK, VMFNE_VF, 0x6, 0x0 }, // 6345 |
| 13636 | { PseudoVMFNE_VFPR16_MF2, VMFNE_VF, 0x7, 0x0 }, // 6346 |
| 13637 | { PseudoVMFNE_VFPR16_MF2_MASK, VMFNE_VF, 0x7, 0x0 }, // 6347 |
| 13638 | { PseudoVMFNE_VFPR32_MF2, VMFNE_VF, 0x7, 0x0 }, // 6348 |
| 13639 | { PseudoVMFNE_VFPR32_MF2_MASK, VMFNE_VF, 0x7, 0x0 }, // 6349 |
| 13640 | { PseudoVMFNE_VV_M1, VMFNE_VV, 0x0, 0x0 }, // 6350 |
| 13641 | { PseudoVMFNE_VV_M1_MASK, VMFNE_VV, 0x0, 0x0 }, // 6351 |
| 13642 | { PseudoVMFNE_VV_M2, VMFNE_VV, 0x1, 0x0 }, // 6352 |
| 13643 | { PseudoVMFNE_VV_M2_MASK, VMFNE_VV, 0x1, 0x0 }, // 6353 |
| 13644 | { PseudoVMFNE_VV_M4, VMFNE_VV, 0x2, 0x0 }, // 6354 |
| 13645 | { PseudoVMFNE_VV_M4_MASK, VMFNE_VV, 0x2, 0x0 }, // 6355 |
| 13646 | { PseudoVMFNE_VV_M8, VMFNE_VV, 0x3, 0x0 }, // 6356 |
| 13647 | { PseudoVMFNE_VV_M8_MASK, VMFNE_VV, 0x3, 0x0 }, // 6357 |
| 13648 | { PseudoVMFNE_VV_MF4, VMFNE_VV, 0x6, 0x0 }, // 6358 |
| 13649 | { PseudoVMFNE_VV_MF4_MASK, VMFNE_VV, 0x6, 0x0 }, // 6359 |
| 13650 | { PseudoVMFNE_VV_MF2, VMFNE_VV, 0x7, 0x0 }, // 6360 |
| 13651 | { PseudoVMFNE_VV_MF2_MASK, VMFNE_VV, 0x7, 0x0 }, // 6361 |
| 13652 | { PseudoVMINU_VV_M1, VMINU_VV, 0x0, 0x0 }, // 6362 |
| 13653 | { PseudoVMINU_VV_M1_MASK, VMINU_VV, 0x0, 0x0 }, // 6363 |
| 13654 | { PseudoVMINU_VV_M2, VMINU_VV, 0x1, 0x0 }, // 6364 |
| 13655 | { PseudoVMINU_VV_M2_MASK, VMINU_VV, 0x1, 0x0 }, // 6365 |
| 13656 | { PseudoVMINU_VV_M4, VMINU_VV, 0x2, 0x0 }, // 6366 |
| 13657 | { PseudoVMINU_VV_M4_MASK, VMINU_VV, 0x2, 0x0 }, // 6367 |
| 13658 | { PseudoVMINU_VV_M8, VMINU_VV, 0x3, 0x0 }, // 6368 |
| 13659 | { PseudoVMINU_VV_M8_MASK, VMINU_VV, 0x3, 0x0 }, // 6369 |
| 13660 | { PseudoVMINU_VV_MF8, VMINU_VV, 0x5, 0x0 }, // 6370 |
| 13661 | { PseudoVMINU_VV_MF8_MASK, VMINU_VV, 0x5, 0x0 }, // 6371 |
| 13662 | { PseudoVMINU_VV_MF4, VMINU_VV, 0x6, 0x0 }, // 6372 |
| 13663 | { PseudoVMINU_VV_MF4_MASK, VMINU_VV, 0x6, 0x0 }, // 6373 |
| 13664 | { PseudoVMINU_VV_MF2, VMINU_VV, 0x7, 0x0 }, // 6374 |
| 13665 | { PseudoVMINU_VV_MF2_MASK, VMINU_VV, 0x7, 0x0 }, // 6375 |
| 13666 | { PseudoVMINU_VX_M1, VMINU_VX, 0x0, 0x0 }, // 6376 |
| 13667 | { PseudoVMINU_VX_M1_MASK, VMINU_VX, 0x0, 0x0 }, // 6377 |
| 13668 | { PseudoVMINU_VX_M2, VMINU_VX, 0x1, 0x0 }, // 6378 |
| 13669 | { PseudoVMINU_VX_M2_MASK, VMINU_VX, 0x1, 0x0 }, // 6379 |
| 13670 | { PseudoVMINU_VX_M4, VMINU_VX, 0x2, 0x0 }, // 6380 |
| 13671 | { PseudoVMINU_VX_M4_MASK, VMINU_VX, 0x2, 0x0 }, // 6381 |
| 13672 | { PseudoVMINU_VX_M8, VMINU_VX, 0x3, 0x0 }, // 6382 |
| 13673 | { PseudoVMINU_VX_M8_MASK, VMINU_VX, 0x3, 0x0 }, // 6383 |
| 13674 | { PseudoVMINU_VX_MF8, VMINU_VX, 0x5, 0x0 }, // 6384 |
| 13675 | { PseudoVMINU_VX_MF8_MASK, VMINU_VX, 0x5, 0x0 }, // 6385 |
| 13676 | { PseudoVMINU_VX_MF4, VMINU_VX, 0x6, 0x0 }, // 6386 |
| 13677 | { PseudoVMINU_VX_MF4_MASK, VMINU_VX, 0x6, 0x0 }, // 6387 |
| 13678 | { PseudoVMINU_VX_MF2, VMINU_VX, 0x7, 0x0 }, // 6388 |
| 13679 | { PseudoVMINU_VX_MF2_MASK, VMINU_VX, 0x7, 0x0 }, // 6389 |
| 13680 | { PseudoVMIN_VV_M1, VMIN_VV, 0x0, 0x0 }, // 6390 |
| 13681 | { PseudoVMIN_VV_M1_MASK, VMIN_VV, 0x0, 0x0 }, // 6391 |
| 13682 | { PseudoVMIN_VV_M2, VMIN_VV, 0x1, 0x0 }, // 6392 |
| 13683 | { PseudoVMIN_VV_M2_MASK, VMIN_VV, 0x1, 0x0 }, // 6393 |
| 13684 | { PseudoVMIN_VV_M4, VMIN_VV, 0x2, 0x0 }, // 6394 |
| 13685 | { PseudoVMIN_VV_M4_MASK, VMIN_VV, 0x2, 0x0 }, // 6395 |
| 13686 | { PseudoVMIN_VV_M8, VMIN_VV, 0x3, 0x0 }, // 6396 |
| 13687 | { PseudoVMIN_VV_M8_MASK, VMIN_VV, 0x3, 0x0 }, // 6397 |
| 13688 | { PseudoVMIN_VV_MF8, VMIN_VV, 0x5, 0x0 }, // 6398 |
| 13689 | { PseudoVMIN_VV_MF8_MASK, VMIN_VV, 0x5, 0x0 }, // 6399 |
| 13690 | { PseudoVMIN_VV_MF4, VMIN_VV, 0x6, 0x0 }, // 6400 |
| 13691 | { PseudoVMIN_VV_MF4_MASK, VMIN_VV, 0x6, 0x0 }, // 6401 |
| 13692 | { PseudoVMIN_VV_MF2, VMIN_VV, 0x7, 0x0 }, // 6402 |
| 13693 | { PseudoVMIN_VV_MF2_MASK, VMIN_VV, 0x7, 0x0 }, // 6403 |
| 13694 | { PseudoVMIN_VX_M1, VMIN_VX, 0x0, 0x0 }, // 6404 |
| 13695 | { PseudoVMIN_VX_M1_MASK, VMIN_VX, 0x0, 0x0 }, // 6405 |
| 13696 | { PseudoVMIN_VX_M2, VMIN_VX, 0x1, 0x0 }, // 6406 |
| 13697 | { PseudoVMIN_VX_M2_MASK, VMIN_VX, 0x1, 0x0 }, // 6407 |
| 13698 | { PseudoVMIN_VX_M4, VMIN_VX, 0x2, 0x0 }, // 6408 |
| 13699 | { PseudoVMIN_VX_M4_MASK, VMIN_VX, 0x2, 0x0 }, // 6409 |
| 13700 | { PseudoVMIN_VX_M8, VMIN_VX, 0x3, 0x0 }, // 6410 |
| 13701 | { PseudoVMIN_VX_M8_MASK, VMIN_VX, 0x3, 0x0 }, // 6411 |
| 13702 | { PseudoVMIN_VX_MF8, VMIN_VX, 0x5, 0x0 }, // 6412 |
| 13703 | { PseudoVMIN_VX_MF8_MASK, VMIN_VX, 0x5, 0x0 }, // 6413 |
| 13704 | { PseudoVMIN_VX_MF4, VMIN_VX, 0x6, 0x0 }, // 6414 |
| 13705 | { PseudoVMIN_VX_MF4_MASK, VMIN_VX, 0x6, 0x0 }, // 6415 |
| 13706 | { PseudoVMIN_VX_MF2, VMIN_VX, 0x7, 0x0 }, // 6416 |
| 13707 | { PseudoVMIN_VX_MF2_MASK, VMIN_VX, 0x7, 0x0 }, // 6417 |
| 13708 | { PseudoVMNAND_MM_M1, VMNAND_MM, 0x0, 0x0 }, // 6418 |
| 13709 | { PseudoVMNAND_MM_M2, VMNAND_MM, 0x1, 0x0 }, // 6419 |
| 13710 | { PseudoVMNAND_MM_M4, VMNAND_MM, 0x2, 0x0 }, // 6420 |
| 13711 | { PseudoVMNAND_MM_M8, VMNAND_MM, 0x3, 0x0 }, // 6421 |
| 13712 | { PseudoVMNAND_MM_MF8, VMNAND_MM, 0x5, 0x0 }, // 6422 |
| 13713 | { PseudoVMNAND_MM_MF4, VMNAND_MM, 0x6, 0x0 }, // 6423 |
| 13714 | { PseudoVMNAND_MM_MF2, VMNAND_MM, 0x7, 0x0 }, // 6424 |
| 13715 | { PseudoVMNOR_MM_M1, VMNOR_MM, 0x0, 0x0 }, // 6425 |
| 13716 | { PseudoVMNOR_MM_M2, VMNOR_MM, 0x1, 0x0 }, // 6426 |
| 13717 | { PseudoVMNOR_MM_M4, VMNOR_MM, 0x2, 0x0 }, // 6427 |
| 13718 | { PseudoVMNOR_MM_M8, VMNOR_MM, 0x3, 0x0 }, // 6428 |
| 13719 | { PseudoVMNOR_MM_MF8, VMNOR_MM, 0x5, 0x0 }, // 6429 |
| 13720 | { PseudoVMNOR_MM_MF4, VMNOR_MM, 0x6, 0x0 }, // 6430 |
| 13721 | { PseudoVMNOR_MM_MF2, VMNOR_MM, 0x7, 0x0 }, // 6431 |
| 13722 | { PseudoVMORN_MM_M1, VMORN_MM, 0x0, 0x0 }, // 6432 |
| 13723 | { PseudoVMORN_MM_M2, VMORN_MM, 0x1, 0x0 }, // 6433 |
| 13724 | { PseudoVMORN_MM_M4, VMORN_MM, 0x2, 0x0 }, // 6434 |
| 13725 | { PseudoVMORN_MM_M8, VMORN_MM, 0x3, 0x0 }, // 6435 |
| 13726 | { PseudoVMORN_MM_MF8, VMORN_MM, 0x5, 0x0 }, // 6436 |
| 13727 | { PseudoVMORN_MM_MF4, VMORN_MM, 0x6, 0x0 }, // 6437 |
| 13728 | { PseudoVMORN_MM_MF2, VMORN_MM, 0x7, 0x0 }, // 6438 |
| 13729 | { PseudoVMOR_MM_M1, VMOR_MM, 0x0, 0x0 }, // 6439 |
| 13730 | { PseudoVMOR_MM_M2, VMOR_MM, 0x1, 0x0 }, // 6440 |
| 13731 | { PseudoVMOR_MM_M4, VMOR_MM, 0x2, 0x0 }, // 6441 |
| 13732 | { PseudoVMOR_MM_M8, VMOR_MM, 0x3, 0x0 }, // 6442 |
| 13733 | { PseudoVMOR_MM_MF8, VMOR_MM, 0x5, 0x0 }, // 6443 |
| 13734 | { PseudoVMOR_MM_MF4, VMOR_MM, 0x6, 0x0 }, // 6444 |
| 13735 | { PseudoVMOR_MM_MF2, VMOR_MM, 0x7, 0x0 }, // 6445 |
| 13736 | { PseudoVMSBC_VV_M1, VMSBC_VV, 0x0, 0x0 }, // 6446 |
| 13737 | { PseudoVMSBC_VV_M2, VMSBC_VV, 0x1, 0x0 }, // 6447 |
| 13738 | { PseudoVMSBC_VV_M4, VMSBC_VV, 0x2, 0x0 }, // 6448 |
| 13739 | { PseudoVMSBC_VV_M8, VMSBC_VV, 0x3, 0x0 }, // 6449 |
| 13740 | { PseudoVMSBC_VV_MF8, VMSBC_VV, 0x5, 0x0 }, // 6450 |
| 13741 | { PseudoVMSBC_VV_MF4, VMSBC_VV, 0x6, 0x0 }, // 6451 |
| 13742 | { PseudoVMSBC_VV_MF2, VMSBC_VV, 0x7, 0x0 }, // 6452 |
| 13743 | { PseudoVMSBC_VVM_M1, VMSBC_VVM, 0x0, 0x0 }, // 6453 |
| 13744 | { PseudoVMSBC_VVM_M2, VMSBC_VVM, 0x1, 0x0 }, // 6454 |
| 13745 | { PseudoVMSBC_VVM_M4, VMSBC_VVM, 0x2, 0x0 }, // 6455 |
| 13746 | { PseudoVMSBC_VVM_M8, VMSBC_VVM, 0x3, 0x0 }, // 6456 |
| 13747 | { PseudoVMSBC_VVM_MF8, VMSBC_VVM, 0x5, 0x0 }, // 6457 |
| 13748 | { PseudoVMSBC_VVM_MF4, VMSBC_VVM, 0x6, 0x0 }, // 6458 |
| 13749 | { PseudoVMSBC_VVM_MF2, VMSBC_VVM, 0x7, 0x0 }, // 6459 |
| 13750 | { PseudoVMSBC_VX_M1, VMSBC_VX, 0x0, 0x0 }, // 6460 |
| 13751 | { PseudoVMSBC_VX_M2, VMSBC_VX, 0x1, 0x0 }, // 6461 |
| 13752 | { PseudoVMSBC_VX_M4, VMSBC_VX, 0x2, 0x0 }, // 6462 |
| 13753 | { PseudoVMSBC_VX_M8, VMSBC_VX, 0x3, 0x0 }, // 6463 |
| 13754 | { PseudoVMSBC_VX_MF8, VMSBC_VX, 0x5, 0x0 }, // 6464 |
| 13755 | { PseudoVMSBC_VX_MF4, VMSBC_VX, 0x6, 0x0 }, // 6465 |
| 13756 | { PseudoVMSBC_VX_MF2, VMSBC_VX, 0x7, 0x0 }, // 6466 |
| 13757 | { PseudoVMSBC_VXM_M1, VMSBC_VXM, 0x0, 0x0 }, // 6467 |
| 13758 | { PseudoVMSBC_VXM_M2, VMSBC_VXM, 0x1, 0x0 }, // 6468 |
| 13759 | { PseudoVMSBC_VXM_M4, VMSBC_VXM, 0x2, 0x0 }, // 6469 |
| 13760 | { PseudoVMSBC_VXM_M8, VMSBC_VXM, 0x3, 0x0 }, // 6470 |
| 13761 | { PseudoVMSBC_VXM_MF8, VMSBC_VXM, 0x5, 0x0 }, // 6471 |
| 13762 | { PseudoVMSBC_VXM_MF4, VMSBC_VXM, 0x6, 0x0 }, // 6472 |
| 13763 | { PseudoVMSBC_VXM_MF2, VMSBC_VXM, 0x7, 0x0 }, // 6473 |
| 13764 | { PseudoVMSBF_M_B8, VMSBF_M, 0x0, 0x0 }, // 6474 |
| 13765 | { PseudoVMSBF_M_B8_MASK, VMSBF_M, 0x0, 0x0 }, // 6475 |
| 13766 | { PseudoVMSBF_M_B16, VMSBF_M, 0x1, 0x0 }, // 6476 |
| 13767 | { PseudoVMSBF_M_B16_MASK, VMSBF_M, 0x1, 0x0 }, // 6477 |
| 13768 | { PseudoVMSBF_M_B32, VMSBF_M, 0x2, 0x0 }, // 6478 |
| 13769 | { PseudoVMSBF_M_B32_MASK, VMSBF_M, 0x2, 0x0 }, // 6479 |
| 13770 | { PseudoVMSBF_M_B64, VMSBF_M, 0x3, 0x0 }, // 6480 |
| 13771 | { PseudoVMSBF_M_B64_MASK, VMSBF_M, 0x3, 0x0 }, // 6481 |
| 13772 | { PseudoVMSBF_M_B1, VMSBF_M, 0x5, 0x0 }, // 6482 |
| 13773 | { PseudoVMSBF_M_B1_MASK, VMSBF_M, 0x5, 0x0 }, // 6483 |
| 13774 | { PseudoVMSBF_M_B2, VMSBF_M, 0x6, 0x0 }, // 6484 |
| 13775 | { PseudoVMSBF_M_B2_MASK, VMSBF_M, 0x6, 0x0 }, // 6485 |
| 13776 | { PseudoVMSBF_M_B4, VMSBF_M, 0x7, 0x0 }, // 6486 |
| 13777 | { PseudoVMSBF_M_B4_MASK, VMSBF_M, 0x7, 0x0 }, // 6487 |
| 13778 | { PseudoVMSEQ_VI_M1, VMSEQ_VI, 0x0, 0x0 }, // 6488 |
| 13779 | { PseudoVMSEQ_VI_M1_MASK, VMSEQ_VI, 0x0, 0x0 }, // 6489 |
| 13780 | { PseudoVMSEQ_VI_M2, VMSEQ_VI, 0x1, 0x0 }, // 6490 |
| 13781 | { PseudoVMSEQ_VI_M2_MASK, VMSEQ_VI, 0x1, 0x0 }, // 6491 |
| 13782 | { PseudoVMSEQ_VI_M4, VMSEQ_VI, 0x2, 0x0 }, // 6492 |
| 13783 | { PseudoVMSEQ_VI_M4_MASK, VMSEQ_VI, 0x2, 0x0 }, // 6493 |
| 13784 | { PseudoVMSEQ_VI_M8, VMSEQ_VI, 0x3, 0x0 }, // 6494 |
| 13785 | { PseudoVMSEQ_VI_M8_MASK, VMSEQ_VI, 0x3, 0x0 }, // 6495 |
| 13786 | { PseudoVMSEQ_VI_MF8, VMSEQ_VI, 0x5, 0x0 }, // 6496 |
| 13787 | { PseudoVMSEQ_VI_MF8_MASK, VMSEQ_VI, 0x5, 0x0 }, // 6497 |
| 13788 | { PseudoVMSEQ_VI_MF4, VMSEQ_VI, 0x6, 0x0 }, // 6498 |
| 13789 | { PseudoVMSEQ_VI_MF4_MASK, VMSEQ_VI, 0x6, 0x0 }, // 6499 |
| 13790 | { PseudoVMSEQ_VI_MF2, VMSEQ_VI, 0x7, 0x0 }, // 6500 |
| 13791 | { PseudoVMSEQ_VI_MF2_MASK, VMSEQ_VI, 0x7, 0x0 }, // 6501 |
| 13792 | { PseudoVMSEQ_VV_M1, VMSEQ_VV, 0x0, 0x0 }, // 6502 |
| 13793 | { PseudoVMSEQ_VV_M1_MASK, VMSEQ_VV, 0x0, 0x0 }, // 6503 |
| 13794 | { PseudoVMSEQ_VV_M2, VMSEQ_VV, 0x1, 0x0 }, // 6504 |
| 13795 | { PseudoVMSEQ_VV_M2_MASK, VMSEQ_VV, 0x1, 0x0 }, // 6505 |
| 13796 | { PseudoVMSEQ_VV_M4, VMSEQ_VV, 0x2, 0x0 }, // 6506 |
| 13797 | { PseudoVMSEQ_VV_M4_MASK, VMSEQ_VV, 0x2, 0x0 }, // 6507 |
| 13798 | { PseudoVMSEQ_VV_M8, VMSEQ_VV, 0x3, 0x0 }, // 6508 |
| 13799 | { PseudoVMSEQ_VV_M8_MASK, VMSEQ_VV, 0x3, 0x0 }, // 6509 |
| 13800 | { PseudoVMSEQ_VV_MF8, VMSEQ_VV, 0x5, 0x0 }, // 6510 |
| 13801 | { PseudoVMSEQ_VV_MF8_MASK, VMSEQ_VV, 0x5, 0x0 }, // 6511 |
| 13802 | { PseudoVMSEQ_VV_MF4, VMSEQ_VV, 0x6, 0x0 }, // 6512 |
| 13803 | { PseudoVMSEQ_VV_MF4_MASK, VMSEQ_VV, 0x6, 0x0 }, // 6513 |
| 13804 | { PseudoVMSEQ_VV_MF2, VMSEQ_VV, 0x7, 0x0 }, // 6514 |
| 13805 | { PseudoVMSEQ_VV_MF2_MASK, VMSEQ_VV, 0x7, 0x0 }, // 6515 |
| 13806 | { PseudoVMSEQ_VX_M1, VMSEQ_VX, 0x0, 0x0 }, // 6516 |
| 13807 | { PseudoVMSEQ_VX_M1_MASK, VMSEQ_VX, 0x0, 0x0 }, // 6517 |
| 13808 | { PseudoVMSEQ_VX_M2, VMSEQ_VX, 0x1, 0x0 }, // 6518 |
| 13809 | { PseudoVMSEQ_VX_M2_MASK, VMSEQ_VX, 0x1, 0x0 }, // 6519 |
| 13810 | { PseudoVMSEQ_VX_M4, VMSEQ_VX, 0x2, 0x0 }, // 6520 |
| 13811 | { PseudoVMSEQ_VX_M4_MASK, VMSEQ_VX, 0x2, 0x0 }, // 6521 |
| 13812 | { PseudoVMSEQ_VX_M8, VMSEQ_VX, 0x3, 0x0 }, // 6522 |
| 13813 | { PseudoVMSEQ_VX_M8_MASK, VMSEQ_VX, 0x3, 0x0 }, // 6523 |
| 13814 | { PseudoVMSEQ_VX_MF8, VMSEQ_VX, 0x5, 0x0 }, // 6524 |
| 13815 | { PseudoVMSEQ_VX_MF8_MASK, VMSEQ_VX, 0x5, 0x0 }, // 6525 |
| 13816 | { PseudoVMSEQ_VX_MF4, VMSEQ_VX, 0x6, 0x0 }, // 6526 |
| 13817 | { PseudoVMSEQ_VX_MF4_MASK, VMSEQ_VX, 0x6, 0x0 }, // 6527 |
| 13818 | { PseudoVMSEQ_VX_MF2, VMSEQ_VX, 0x7, 0x0 }, // 6528 |
| 13819 | { PseudoVMSEQ_VX_MF2_MASK, VMSEQ_VX, 0x7, 0x0 }, // 6529 |
| 13820 | { PseudoVMSGTU_VI_M1, VMSGTU_VI, 0x0, 0x0 }, // 6530 |
| 13821 | { PseudoVMSGTU_VI_M1_MASK, VMSGTU_VI, 0x0, 0x0 }, // 6531 |
| 13822 | { PseudoVMSGTU_VI_M2, VMSGTU_VI, 0x1, 0x0 }, // 6532 |
| 13823 | { PseudoVMSGTU_VI_M2_MASK, VMSGTU_VI, 0x1, 0x0 }, // 6533 |
| 13824 | { PseudoVMSGTU_VI_M4, VMSGTU_VI, 0x2, 0x0 }, // 6534 |
| 13825 | { PseudoVMSGTU_VI_M4_MASK, VMSGTU_VI, 0x2, 0x0 }, // 6535 |
| 13826 | { PseudoVMSGTU_VI_M8, VMSGTU_VI, 0x3, 0x0 }, // 6536 |
| 13827 | { PseudoVMSGTU_VI_M8_MASK, VMSGTU_VI, 0x3, 0x0 }, // 6537 |
| 13828 | { PseudoVMSGTU_VI_MF8, VMSGTU_VI, 0x5, 0x0 }, // 6538 |
| 13829 | { PseudoVMSGTU_VI_MF8_MASK, VMSGTU_VI, 0x5, 0x0 }, // 6539 |
| 13830 | { PseudoVMSGTU_VI_MF4, VMSGTU_VI, 0x6, 0x0 }, // 6540 |
| 13831 | { PseudoVMSGTU_VI_MF4_MASK, VMSGTU_VI, 0x6, 0x0 }, // 6541 |
| 13832 | { PseudoVMSGTU_VI_MF2, VMSGTU_VI, 0x7, 0x0 }, // 6542 |
| 13833 | { PseudoVMSGTU_VI_MF2_MASK, VMSGTU_VI, 0x7, 0x0 }, // 6543 |
| 13834 | { PseudoVMSGTU_VX_M1, VMSGTU_VX, 0x0, 0x0 }, // 6544 |
| 13835 | { PseudoVMSGTU_VX_M1_MASK, VMSGTU_VX, 0x0, 0x0 }, // 6545 |
| 13836 | { PseudoVMSGTU_VX_M2, VMSGTU_VX, 0x1, 0x0 }, // 6546 |
| 13837 | { PseudoVMSGTU_VX_M2_MASK, VMSGTU_VX, 0x1, 0x0 }, // 6547 |
| 13838 | { PseudoVMSGTU_VX_M4, VMSGTU_VX, 0x2, 0x0 }, // 6548 |
| 13839 | { PseudoVMSGTU_VX_M4_MASK, VMSGTU_VX, 0x2, 0x0 }, // 6549 |
| 13840 | { PseudoVMSGTU_VX_M8, VMSGTU_VX, 0x3, 0x0 }, // 6550 |
| 13841 | { PseudoVMSGTU_VX_M8_MASK, VMSGTU_VX, 0x3, 0x0 }, // 6551 |
| 13842 | { PseudoVMSGTU_VX_MF8, VMSGTU_VX, 0x5, 0x0 }, // 6552 |
| 13843 | { PseudoVMSGTU_VX_MF8_MASK, VMSGTU_VX, 0x5, 0x0 }, // 6553 |
| 13844 | { PseudoVMSGTU_VX_MF4, VMSGTU_VX, 0x6, 0x0 }, // 6554 |
| 13845 | { PseudoVMSGTU_VX_MF4_MASK, VMSGTU_VX, 0x6, 0x0 }, // 6555 |
| 13846 | { PseudoVMSGTU_VX_MF2, VMSGTU_VX, 0x7, 0x0 }, // 6556 |
| 13847 | { PseudoVMSGTU_VX_MF2_MASK, VMSGTU_VX, 0x7, 0x0 }, // 6557 |
| 13848 | { PseudoVMSGT_VI_M1, VMSGT_VI, 0x0, 0x0 }, // 6558 |
| 13849 | { PseudoVMSGT_VI_M1_MASK, VMSGT_VI, 0x0, 0x0 }, // 6559 |
| 13850 | { PseudoVMSGT_VI_M2, VMSGT_VI, 0x1, 0x0 }, // 6560 |
| 13851 | { PseudoVMSGT_VI_M2_MASK, VMSGT_VI, 0x1, 0x0 }, // 6561 |
| 13852 | { PseudoVMSGT_VI_M4, VMSGT_VI, 0x2, 0x0 }, // 6562 |
| 13853 | { PseudoVMSGT_VI_M4_MASK, VMSGT_VI, 0x2, 0x0 }, // 6563 |
| 13854 | { PseudoVMSGT_VI_M8, VMSGT_VI, 0x3, 0x0 }, // 6564 |
| 13855 | { PseudoVMSGT_VI_M8_MASK, VMSGT_VI, 0x3, 0x0 }, // 6565 |
| 13856 | { PseudoVMSGT_VI_MF8, VMSGT_VI, 0x5, 0x0 }, // 6566 |
| 13857 | { PseudoVMSGT_VI_MF8_MASK, VMSGT_VI, 0x5, 0x0 }, // 6567 |
| 13858 | { PseudoVMSGT_VI_MF4, VMSGT_VI, 0x6, 0x0 }, // 6568 |
| 13859 | { PseudoVMSGT_VI_MF4_MASK, VMSGT_VI, 0x6, 0x0 }, // 6569 |
| 13860 | { PseudoVMSGT_VI_MF2, VMSGT_VI, 0x7, 0x0 }, // 6570 |
| 13861 | { PseudoVMSGT_VI_MF2_MASK, VMSGT_VI, 0x7, 0x0 }, // 6571 |
| 13862 | { PseudoVMSGT_VX_M1, VMSGT_VX, 0x0, 0x0 }, // 6572 |
| 13863 | { PseudoVMSGT_VX_M1_MASK, VMSGT_VX, 0x0, 0x0 }, // 6573 |
| 13864 | { PseudoVMSGT_VX_M2, VMSGT_VX, 0x1, 0x0 }, // 6574 |
| 13865 | { PseudoVMSGT_VX_M2_MASK, VMSGT_VX, 0x1, 0x0 }, // 6575 |
| 13866 | { PseudoVMSGT_VX_M4, VMSGT_VX, 0x2, 0x0 }, // 6576 |
| 13867 | { PseudoVMSGT_VX_M4_MASK, VMSGT_VX, 0x2, 0x0 }, // 6577 |
| 13868 | { PseudoVMSGT_VX_M8, VMSGT_VX, 0x3, 0x0 }, // 6578 |
| 13869 | { PseudoVMSGT_VX_M8_MASK, VMSGT_VX, 0x3, 0x0 }, // 6579 |
| 13870 | { PseudoVMSGT_VX_MF8, VMSGT_VX, 0x5, 0x0 }, // 6580 |
| 13871 | { PseudoVMSGT_VX_MF8_MASK, VMSGT_VX, 0x5, 0x0 }, // 6581 |
| 13872 | { PseudoVMSGT_VX_MF4, VMSGT_VX, 0x6, 0x0 }, // 6582 |
| 13873 | { PseudoVMSGT_VX_MF4_MASK, VMSGT_VX, 0x6, 0x0 }, // 6583 |
| 13874 | { PseudoVMSGT_VX_MF2, VMSGT_VX, 0x7, 0x0 }, // 6584 |
| 13875 | { PseudoVMSGT_VX_MF2_MASK, VMSGT_VX, 0x7, 0x0 }, // 6585 |
| 13876 | { PseudoVMSIF_M_B8, VMSIF_M, 0x0, 0x0 }, // 6586 |
| 13877 | { PseudoVMSIF_M_B8_MASK, VMSIF_M, 0x0, 0x0 }, // 6587 |
| 13878 | { PseudoVMSIF_M_B16, VMSIF_M, 0x1, 0x0 }, // 6588 |
| 13879 | { PseudoVMSIF_M_B16_MASK, VMSIF_M, 0x1, 0x0 }, // 6589 |
| 13880 | { PseudoVMSIF_M_B32, VMSIF_M, 0x2, 0x0 }, // 6590 |
| 13881 | { PseudoVMSIF_M_B32_MASK, VMSIF_M, 0x2, 0x0 }, // 6591 |
| 13882 | { PseudoVMSIF_M_B64, VMSIF_M, 0x3, 0x0 }, // 6592 |
| 13883 | { PseudoVMSIF_M_B64_MASK, VMSIF_M, 0x3, 0x0 }, // 6593 |
| 13884 | { PseudoVMSIF_M_B1, VMSIF_M, 0x5, 0x0 }, // 6594 |
| 13885 | { PseudoVMSIF_M_B1_MASK, VMSIF_M, 0x5, 0x0 }, // 6595 |
| 13886 | { PseudoVMSIF_M_B2, VMSIF_M, 0x6, 0x0 }, // 6596 |
| 13887 | { PseudoVMSIF_M_B2_MASK, VMSIF_M, 0x6, 0x0 }, // 6597 |
| 13888 | { PseudoVMSIF_M_B4, VMSIF_M, 0x7, 0x0 }, // 6598 |
| 13889 | { PseudoVMSIF_M_B4_MASK, VMSIF_M, 0x7, 0x0 }, // 6599 |
| 13890 | { PseudoVMSLEU_VI_M1, VMSLEU_VI, 0x0, 0x0 }, // 6600 |
| 13891 | { PseudoVMSLEU_VI_M1_MASK, VMSLEU_VI, 0x0, 0x0 }, // 6601 |
| 13892 | { PseudoVMSLEU_VI_M2, VMSLEU_VI, 0x1, 0x0 }, // 6602 |
| 13893 | { PseudoVMSLEU_VI_M2_MASK, VMSLEU_VI, 0x1, 0x0 }, // 6603 |
| 13894 | { PseudoVMSLEU_VI_M4, VMSLEU_VI, 0x2, 0x0 }, // 6604 |
| 13895 | { PseudoVMSLEU_VI_M4_MASK, VMSLEU_VI, 0x2, 0x0 }, // 6605 |
| 13896 | { PseudoVMSLEU_VI_M8, VMSLEU_VI, 0x3, 0x0 }, // 6606 |
| 13897 | { PseudoVMSLEU_VI_M8_MASK, VMSLEU_VI, 0x3, 0x0 }, // 6607 |
| 13898 | { PseudoVMSLEU_VI_MF8, VMSLEU_VI, 0x5, 0x0 }, // 6608 |
| 13899 | { PseudoVMSLEU_VI_MF8_MASK, VMSLEU_VI, 0x5, 0x0 }, // 6609 |
| 13900 | { PseudoVMSLEU_VI_MF4, VMSLEU_VI, 0x6, 0x0 }, // 6610 |
| 13901 | { PseudoVMSLEU_VI_MF4_MASK, VMSLEU_VI, 0x6, 0x0 }, // 6611 |
| 13902 | { PseudoVMSLEU_VI_MF2, VMSLEU_VI, 0x7, 0x0 }, // 6612 |
| 13903 | { PseudoVMSLEU_VI_MF2_MASK, VMSLEU_VI, 0x7, 0x0 }, // 6613 |
| 13904 | { PseudoVMSLEU_VV_M1, VMSLEU_VV, 0x0, 0x0 }, // 6614 |
| 13905 | { PseudoVMSLEU_VV_M1_MASK, VMSLEU_VV, 0x0, 0x0 }, // 6615 |
| 13906 | { PseudoVMSLEU_VV_M2, VMSLEU_VV, 0x1, 0x0 }, // 6616 |
| 13907 | { PseudoVMSLEU_VV_M2_MASK, VMSLEU_VV, 0x1, 0x0 }, // 6617 |
| 13908 | { PseudoVMSLEU_VV_M4, VMSLEU_VV, 0x2, 0x0 }, // 6618 |
| 13909 | { PseudoVMSLEU_VV_M4_MASK, VMSLEU_VV, 0x2, 0x0 }, // 6619 |
| 13910 | { PseudoVMSLEU_VV_M8, VMSLEU_VV, 0x3, 0x0 }, // 6620 |
| 13911 | { PseudoVMSLEU_VV_M8_MASK, VMSLEU_VV, 0x3, 0x0 }, // 6621 |
| 13912 | { PseudoVMSLEU_VV_MF8, VMSLEU_VV, 0x5, 0x0 }, // 6622 |
| 13913 | { PseudoVMSLEU_VV_MF8_MASK, VMSLEU_VV, 0x5, 0x0 }, // 6623 |
| 13914 | { PseudoVMSLEU_VV_MF4, VMSLEU_VV, 0x6, 0x0 }, // 6624 |
| 13915 | { PseudoVMSLEU_VV_MF4_MASK, VMSLEU_VV, 0x6, 0x0 }, // 6625 |
| 13916 | { PseudoVMSLEU_VV_MF2, VMSLEU_VV, 0x7, 0x0 }, // 6626 |
| 13917 | { PseudoVMSLEU_VV_MF2_MASK, VMSLEU_VV, 0x7, 0x0 }, // 6627 |
| 13918 | { PseudoVMSLEU_VX_M1, VMSLEU_VX, 0x0, 0x0 }, // 6628 |
| 13919 | { PseudoVMSLEU_VX_M1_MASK, VMSLEU_VX, 0x0, 0x0 }, // 6629 |
| 13920 | { PseudoVMSLEU_VX_M2, VMSLEU_VX, 0x1, 0x0 }, // 6630 |
| 13921 | { PseudoVMSLEU_VX_M2_MASK, VMSLEU_VX, 0x1, 0x0 }, // 6631 |
| 13922 | { PseudoVMSLEU_VX_M4, VMSLEU_VX, 0x2, 0x0 }, // 6632 |
| 13923 | { PseudoVMSLEU_VX_M4_MASK, VMSLEU_VX, 0x2, 0x0 }, // 6633 |
| 13924 | { PseudoVMSLEU_VX_M8, VMSLEU_VX, 0x3, 0x0 }, // 6634 |
| 13925 | { PseudoVMSLEU_VX_M8_MASK, VMSLEU_VX, 0x3, 0x0 }, // 6635 |
| 13926 | { PseudoVMSLEU_VX_MF8, VMSLEU_VX, 0x5, 0x0 }, // 6636 |
| 13927 | { PseudoVMSLEU_VX_MF8_MASK, VMSLEU_VX, 0x5, 0x0 }, // 6637 |
| 13928 | { PseudoVMSLEU_VX_MF4, VMSLEU_VX, 0x6, 0x0 }, // 6638 |
| 13929 | { PseudoVMSLEU_VX_MF4_MASK, VMSLEU_VX, 0x6, 0x0 }, // 6639 |
| 13930 | { PseudoVMSLEU_VX_MF2, VMSLEU_VX, 0x7, 0x0 }, // 6640 |
| 13931 | { PseudoVMSLEU_VX_MF2_MASK, VMSLEU_VX, 0x7, 0x0 }, // 6641 |
| 13932 | { PseudoVMSLE_VI_M1, VMSLE_VI, 0x0, 0x0 }, // 6642 |
| 13933 | { PseudoVMSLE_VI_M1_MASK, VMSLE_VI, 0x0, 0x0 }, // 6643 |
| 13934 | { PseudoVMSLE_VI_M2, VMSLE_VI, 0x1, 0x0 }, // 6644 |
| 13935 | { PseudoVMSLE_VI_M2_MASK, VMSLE_VI, 0x1, 0x0 }, // 6645 |
| 13936 | { PseudoVMSLE_VI_M4, VMSLE_VI, 0x2, 0x0 }, // 6646 |
| 13937 | { PseudoVMSLE_VI_M4_MASK, VMSLE_VI, 0x2, 0x0 }, // 6647 |
| 13938 | { PseudoVMSLE_VI_M8, VMSLE_VI, 0x3, 0x0 }, // 6648 |
| 13939 | { PseudoVMSLE_VI_M8_MASK, VMSLE_VI, 0x3, 0x0 }, // 6649 |
| 13940 | { PseudoVMSLE_VI_MF8, VMSLE_VI, 0x5, 0x0 }, // 6650 |
| 13941 | { PseudoVMSLE_VI_MF8_MASK, VMSLE_VI, 0x5, 0x0 }, // 6651 |
| 13942 | { PseudoVMSLE_VI_MF4, VMSLE_VI, 0x6, 0x0 }, // 6652 |
| 13943 | { PseudoVMSLE_VI_MF4_MASK, VMSLE_VI, 0x6, 0x0 }, // 6653 |
| 13944 | { PseudoVMSLE_VI_MF2, VMSLE_VI, 0x7, 0x0 }, // 6654 |
| 13945 | { PseudoVMSLE_VI_MF2_MASK, VMSLE_VI, 0x7, 0x0 }, // 6655 |
| 13946 | { PseudoVMSLE_VV_M1, VMSLE_VV, 0x0, 0x0 }, // 6656 |
| 13947 | { PseudoVMSLE_VV_M1_MASK, VMSLE_VV, 0x0, 0x0 }, // 6657 |
| 13948 | { PseudoVMSLE_VV_M2, VMSLE_VV, 0x1, 0x0 }, // 6658 |
| 13949 | { PseudoVMSLE_VV_M2_MASK, VMSLE_VV, 0x1, 0x0 }, // 6659 |
| 13950 | { PseudoVMSLE_VV_M4, VMSLE_VV, 0x2, 0x0 }, // 6660 |
| 13951 | { PseudoVMSLE_VV_M4_MASK, VMSLE_VV, 0x2, 0x0 }, // 6661 |
| 13952 | { PseudoVMSLE_VV_M8, VMSLE_VV, 0x3, 0x0 }, // 6662 |
| 13953 | { PseudoVMSLE_VV_M8_MASK, VMSLE_VV, 0x3, 0x0 }, // 6663 |
| 13954 | { PseudoVMSLE_VV_MF8, VMSLE_VV, 0x5, 0x0 }, // 6664 |
| 13955 | { PseudoVMSLE_VV_MF8_MASK, VMSLE_VV, 0x5, 0x0 }, // 6665 |
| 13956 | { PseudoVMSLE_VV_MF4, VMSLE_VV, 0x6, 0x0 }, // 6666 |
| 13957 | { PseudoVMSLE_VV_MF4_MASK, VMSLE_VV, 0x6, 0x0 }, // 6667 |
| 13958 | { PseudoVMSLE_VV_MF2, VMSLE_VV, 0x7, 0x0 }, // 6668 |
| 13959 | { PseudoVMSLE_VV_MF2_MASK, VMSLE_VV, 0x7, 0x0 }, // 6669 |
| 13960 | { PseudoVMSLE_VX_M1, VMSLE_VX, 0x0, 0x0 }, // 6670 |
| 13961 | { PseudoVMSLE_VX_M1_MASK, VMSLE_VX, 0x0, 0x0 }, // 6671 |
| 13962 | { PseudoVMSLE_VX_M2, VMSLE_VX, 0x1, 0x0 }, // 6672 |
| 13963 | { PseudoVMSLE_VX_M2_MASK, VMSLE_VX, 0x1, 0x0 }, // 6673 |
| 13964 | { PseudoVMSLE_VX_M4, VMSLE_VX, 0x2, 0x0 }, // 6674 |
| 13965 | { PseudoVMSLE_VX_M4_MASK, VMSLE_VX, 0x2, 0x0 }, // 6675 |
| 13966 | { PseudoVMSLE_VX_M8, VMSLE_VX, 0x3, 0x0 }, // 6676 |
| 13967 | { PseudoVMSLE_VX_M8_MASK, VMSLE_VX, 0x3, 0x0 }, // 6677 |
| 13968 | { PseudoVMSLE_VX_MF8, VMSLE_VX, 0x5, 0x0 }, // 6678 |
| 13969 | { PseudoVMSLE_VX_MF8_MASK, VMSLE_VX, 0x5, 0x0 }, // 6679 |
| 13970 | { PseudoVMSLE_VX_MF4, VMSLE_VX, 0x6, 0x0 }, // 6680 |
| 13971 | { PseudoVMSLE_VX_MF4_MASK, VMSLE_VX, 0x6, 0x0 }, // 6681 |
| 13972 | { PseudoVMSLE_VX_MF2, VMSLE_VX, 0x7, 0x0 }, // 6682 |
| 13973 | { PseudoVMSLE_VX_MF2_MASK, VMSLE_VX, 0x7, 0x0 }, // 6683 |
| 13974 | { PseudoVMSLTU_VV_M1, VMSLTU_VV, 0x0, 0x0 }, // 6684 |
| 13975 | { PseudoVMSLTU_VV_M1_MASK, VMSLTU_VV, 0x0, 0x0 }, // 6685 |
| 13976 | { PseudoVMSLTU_VV_M2, VMSLTU_VV, 0x1, 0x0 }, // 6686 |
| 13977 | { PseudoVMSLTU_VV_M2_MASK, VMSLTU_VV, 0x1, 0x0 }, // 6687 |
| 13978 | { PseudoVMSLTU_VV_M4, VMSLTU_VV, 0x2, 0x0 }, // 6688 |
| 13979 | { PseudoVMSLTU_VV_M4_MASK, VMSLTU_VV, 0x2, 0x0 }, // 6689 |
| 13980 | { PseudoVMSLTU_VV_M8, VMSLTU_VV, 0x3, 0x0 }, // 6690 |
| 13981 | { PseudoVMSLTU_VV_M8_MASK, VMSLTU_VV, 0x3, 0x0 }, // 6691 |
| 13982 | { PseudoVMSLTU_VV_MF8, VMSLTU_VV, 0x5, 0x0 }, // 6692 |
| 13983 | { PseudoVMSLTU_VV_MF8_MASK, VMSLTU_VV, 0x5, 0x0 }, // 6693 |
| 13984 | { PseudoVMSLTU_VV_MF4, VMSLTU_VV, 0x6, 0x0 }, // 6694 |
| 13985 | { PseudoVMSLTU_VV_MF4_MASK, VMSLTU_VV, 0x6, 0x0 }, // 6695 |
| 13986 | { PseudoVMSLTU_VV_MF2, VMSLTU_VV, 0x7, 0x0 }, // 6696 |
| 13987 | { PseudoVMSLTU_VV_MF2_MASK, VMSLTU_VV, 0x7, 0x0 }, // 6697 |
| 13988 | { PseudoVMSLTU_VX_M1, VMSLTU_VX, 0x0, 0x0 }, // 6698 |
| 13989 | { PseudoVMSLTU_VX_M1_MASK, VMSLTU_VX, 0x0, 0x0 }, // 6699 |
| 13990 | { PseudoVMSLTU_VX_M2, VMSLTU_VX, 0x1, 0x0 }, // 6700 |
| 13991 | { PseudoVMSLTU_VX_M2_MASK, VMSLTU_VX, 0x1, 0x0 }, // 6701 |
| 13992 | { PseudoVMSLTU_VX_M4, VMSLTU_VX, 0x2, 0x0 }, // 6702 |
| 13993 | { PseudoVMSLTU_VX_M4_MASK, VMSLTU_VX, 0x2, 0x0 }, // 6703 |
| 13994 | { PseudoVMSLTU_VX_M8, VMSLTU_VX, 0x3, 0x0 }, // 6704 |
| 13995 | { PseudoVMSLTU_VX_M8_MASK, VMSLTU_VX, 0x3, 0x0 }, // 6705 |
| 13996 | { PseudoVMSLTU_VX_MF8, VMSLTU_VX, 0x5, 0x0 }, // 6706 |
| 13997 | { PseudoVMSLTU_VX_MF8_MASK, VMSLTU_VX, 0x5, 0x0 }, // 6707 |
| 13998 | { PseudoVMSLTU_VX_MF4, VMSLTU_VX, 0x6, 0x0 }, // 6708 |
| 13999 | { PseudoVMSLTU_VX_MF4_MASK, VMSLTU_VX, 0x6, 0x0 }, // 6709 |
| 14000 | { PseudoVMSLTU_VX_MF2, VMSLTU_VX, 0x7, 0x0 }, // 6710 |
| 14001 | { PseudoVMSLTU_VX_MF2_MASK, VMSLTU_VX, 0x7, 0x0 }, // 6711 |
| 14002 | { PseudoVMSLT_VV_M1, VMSLT_VV, 0x0, 0x0 }, // 6712 |
| 14003 | { PseudoVMSLT_VV_M1_MASK, VMSLT_VV, 0x0, 0x0 }, // 6713 |
| 14004 | { PseudoVMSLT_VV_M2, VMSLT_VV, 0x1, 0x0 }, // 6714 |
| 14005 | { PseudoVMSLT_VV_M2_MASK, VMSLT_VV, 0x1, 0x0 }, // 6715 |
| 14006 | { PseudoVMSLT_VV_M4, VMSLT_VV, 0x2, 0x0 }, // 6716 |
| 14007 | { PseudoVMSLT_VV_M4_MASK, VMSLT_VV, 0x2, 0x0 }, // 6717 |
| 14008 | { PseudoVMSLT_VV_M8, VMSLT_VV, 0x3, 0x0 }, // 6718 |
| 14009 | { PseudoVMSLT_VV_M8_MASK, VMSLT_VV, 0x3, 0x0 }, // 6719 |
| 14010 | { PseudoVMSLT_VV_MF8, VMSLT_VV, 0x5, 0x0 }, // 6720 |
| 14011 | { PseudoVMSLT_VV_MF8_MASK, VMSLT_VV, 0x5, 0x0 }, // 6721 |
| 14012 | { PseudoVMSLT_VV_MF4, VMSLT_VV, 0x6, 0x0 }, // 6722 |
| 14013 | { PseudoVMSLT_VV_MF4_MASK, VMSLT_VV, 0x6, 0x0 }, // 6723 |
| 14014 | { PseudoVMSLT_VV_MF2, VMSLT_VV, 0x7, 0x0 }, // 6724 |
| 14015 | { PseudoVMSLT_VV_MF2_MASK, VMSLT_VV, 0x7, 0x0 }, // 6725 |
| 14016 | { PseudoVMSLT_VX_M1, VMSLT_VX, 0x0, 0x0 }, // 6726 |
| 14017 | { PseudoVMSLT_VX_M1_MASK, VMSLT_VX, 0x0, 0x0 }, // 6727 |
| 14018 | { PseudoVMSLT_VX_M2, VMSLT_VX, 0x1, 0x0 }, // 6728 |
| 14019 | { PseudoVMSLT_VX_M2_MASK, VMSLT_VX, 0x1, 0x0 }, // 6729 |
| 14020 | { PseudoVMSLT_VX_M4, VMSLT_VX, 0x2, 0x0 }, // 6730 |
| 14021 | { PseudoVMSLT_VX_M4_MASK, VMSLT_VX, 0x2, 0x0 }, // 6731 |
| 14022 | { PseudoVMSLT_VX_M8, VMSLT_VX, 0x3, 0x0 }, // 6732 |
| 14023 | { PseudoVMSLT_VX_M8_MASK, VMSLT_VX, 0x3, 0x0 }, // 6733 |
| 14024 | { PseudoVMSLT_VX_MF8, VMSLT_VX, 0x5, 0x0 }, // 6734 |
| 14025 | { PseudoVMSLT_VX_MF8_MASK, VMSLT_VX, 0x5, 0x0 }, // 6735 |
| 14026 | { PseudoVMSLT_VX_MF4, VMSLT_VX, 0x6, 0x0 }, // 6736 |
| 14027 | { PseudoVMSLT_VX_MF4_MASK, VMSLT_VX, 0x6, 0x0 }, // 6737 |
| 14028 | { PseudoVMSLT_VX_MF2, VMSLT_VX, 0x7, 0x0 }, // 6738 |
| 14029 | { PseudoVMSLT_VX_MF2_MASK, VMSLT_VX, 0x7, 0x0 }, // 6739 |
| 14030 | { PseudoVMSNE_VI_M1, VMSNE_VI, 0x0, 0x0 }, // 6740 |
| 14031 | { PseudoVMSNE_VI_M1_MASK, VMSNE_VI, 0x0, 0x0 }, // 6741 |
| 14032 | { PseudoVMSNE_VI_M2, VMSNE_VI, 0x1, 0x0 }, // 6742 |
| 14033 | { PseudoVMSNE_VI_M2_MASK, VMSNE_VI, 0x1, 0x0 }, // 6743 |
| 14034 | { PseudoVMSNE_VI_M4, VMSNE_VI, 0x2, 0x0 }, // 6744 |
| 14035 | { PseudoVMSNE_VI_M4_MASK, VMSNE_VI, 0x2, 0x0 }, // 6745 |
| 14036 | { PseudoVMSNE_VI_M8, VMSNE_VI, 0x3, 0x0 }, // 6746 |
| 14037 | { PseudoVMSNE_VI_M8_MASK, VMSNE_VI, 0x3, 0x0 }, // 6747 |
| 14038 | { PseudoVMSNE_VI_MF8, VMSNE_VI, 0x5, 0x0 }, // 6748 |
| 14039 | { PseudoVMSNE_VI_MF8_MASK, VMSNE_VI, 0x5, 0x0 }, // 6749 |
| 14040 | { PseudoVMSNE_VI_MF4, VMSNE_VI, 0x6, 0x0 }, // 6750 |
| 14041 | { PseudoVMSNE_VI_MF4_MASK, VMSNE_VI, 0x6, 0x0 }, // 6751 |
| 14042 | { PseudoVMSNE_VI_MF2, VMSNE_VI, 0x7, 0x0 }, // 6752 |
| 14043 | { PseudoVMSNE_VI_MF2_MASK, VMSNE_VI, 0x7, 0x0 }, // 6753 |
| 14044 | { PseudoVMSNE_VV_M1, VMSNE_VV, 0x0, 0x0 }, // 6754 |
| 14045 | { PseudoVMSNE_VV_M1_MASK, VMSNE_VV, 0x0, 0x0 }, // 6755 |
| 14046 | { PseudoVMSNE_VV_M2, VMSNE_VV, 0x1, 0x0 }, // 6756 |
| 14047 | { PseudoVMSNE_VV_M2_MASK, VMSNE_VV, 0x1, 0x0 }, // 6757 |
| 14048 | { PseudoVMSNE_VV_M4, VMSNE_VV, 0x2, 0x0 }, // 6758 |
| 14049 | { PseudoVMSNE_VV_M4_MASK, VMSNE_VV, 0x2, 0x0 }, // 6759 |
| 14050 | { PseudoVMSNE_VV_M8, VMSNE_VV, 0x3, 0x0 }, // 6760 |
| 14051 | { PseudoVMSNE_VV_M8_MASK, VMSNE_VV, 0x3, 0x0 }, // 6761 |
| 14052 | { PseudoVMSNE_VV_MF8, VMSNE_VV, 0x5, 0x0 }, // 6762 |
| 14053 | { PseudoVMSNE_VV_MF8_MASK, VMSNE_VV, 0x5, 0x0 }, // 6763 |
| 14054 | { PseudoVMSNE_VV_MF4, VMSNE_VV, 0x6, 0x0 }, // 6764 |
| 14055 | { PseudoVMSNE_VV_MF4_MASK, VMSNE_VV, 0x6, 0x0 }, // 6765 |
| 14056 | { PseudoVMSNE_VV_MF2, VMSNE_VV, 0x7, 0x0 }, // 6766 |
| 14057 | { PseudoVMSNE_VV_MF2_MASK, VMSNE_VV, 0x7, 0x0 }, // 6767 |
| 14058 | { PseudoVMSNE_VX_M1, VMSNE_VX, 0x0, 0x0 }, // 6768 |
| 14059 | { PseudoVMSNE_VX_M1_MASK, VMSNE_VX, 0x0, 0x0 }, // 6769 |
| 14060 | { PseudoVMSNE_VX_M2, VMSNE_VX, 0x1, 0x0 }, // 6770 |
| 14061 | { PseudoVMSNE_VX_M2_MASK, VMSNE_VX, 0x1, 0x0 }, // 6771 |
| 14062 | { PseudoVMSNE_VX_M4, VMSNE_VX, 0x2, 0x0 }, // 6772 |
| 14063 | { PseudoVMSNE_VX_M4_MASK, VMSNE_VX, 0x2, 0x0 }, // 6773 |
| 14064 | { PseudoVMSNE_VX_M8, VMSNE_VX, 0x3, 0x0 }, // 6774 |
| 14065 | { PseudoVMSNE_VX_M8_MASK, VMSNE_VX, 0x3, 0x0 }, // 6775 |
| 14066 | { PseudoVMSNE_VX_MF8, VMSNE_VX, 0x5, 0x0 }, // 6776 |
| 14067 | { PseudoVMSNE_VX_MF8_MASK, VMSNE_VX, 0x5, 0x0 }, // 6777 |
| 14068 | { PseudoVMSNE_VX_MF4, VMSNE_VX, 0x6, 0x0 }, // 6778 |
| 14069 | { PseudoVMSNE_VX_MF4_MASK, VMSNE_VX, 0x6, 0x0 }, // 6779 |
| 14070 | { PseudoVMSNE_VX_MF2, VMSNE_VX, 0x7, 0x0 }, // 6780 |
| 14071 | { PseudoVMSNE_VX_MF2_MASK, VMSNE_VX, 0x7, 0x0 }, // 6781 |
| 14072 | { PseudoVMSOF_M_B8, VMSOF_M, 0x0, 0x0 }, // 6782 |
| 14073 | { PseudoVMSOF_M_B8_MASK, VMSOF_M, 0x0, 0x0 }, // 6783 |
| 14074 | { PseudoVMSOF_M_B16, VMSOF_M, 0x1, 0x0 }, // 6784 |
| 14075 | { PseudoVMSOF_M_B16_MASK, VMSOF_M, 0x1, 0x0 }, // 6785 |
| 14076 | { PseudoVMSOF_M_B32, VMSOF_M, 0x2, 0x0 }, // 6786 |
| 14077 | { PseudoVMSOF_M_B32_MASK, VMSOF_M, 0x2, 0x0 }, // 6787 |
| 14078 | { PseudoVMSOF_M_B64, VMSOF_M, 0x3, 0x0 }, // 6788 |
| 14079 | { PseudoVMSOF_M_B64_MASK, VMSOF_M, 0x3, 0x0 }, // 6789 |
| 14080 | { PseudoVMSOF_M_B1, VMSOF_M, 0x5, 0x0 }, // 6790 |
| 14081 | { PseudoVMSOF_M_B1_MASK, VMSOF_M, 0x5, 0x0 }, // 6791 |
| 14082 | { PseudoVMSOF_M_B2, VMSOF_M, 0x6, 0x0 }, // 6792 |
| 14083 | { PseudoVMSOF_M_B2_MASK, VMSOF_M, 0x6, 0x0 }, // 6793 |
| 14084 | { PseudoVMSOF_M_B4, VMSOF_M, 0x7, 0x0 }, // 6794 |
| 14085 | { PseudoVMSOF_M_B4_MASK, VMSOF_M, 0x7, 0x0 }, // 6795 |
| 14086 | { PseudoVMULHSU_VV_M1, VMULHSU_VV, 0x0, 0x0 }, // 6796 |
| 14087 | { PseudoVMULHSU_VV_M1_MASK, VMULHSU_VV, 0x0, 0x0 }, // 6797 |
| 14088 | { PseudoVMULHSU_VV_M2, VMULHSU_VV, 0x1, 0x0 }, // 6798 |
| 14089 | { PseudoVMULHSU_VV_M2_MASK, VMULHSU_VV, 0x1, 0x0 }, // 6799 |
| 14090 | { PseudoVMULHSU_VV_M4, VMULHSU_VV, 0x2, 0x0 }, // 6800 |
| 14091 | { PseudoVMULHSU_VV_M4_MASK, VMULHSU_VV, 0x2, 0x0 }, // 6801 |
| 14092 | { PseudoVMULHSU_VV_M8, VMULHSU_VV, 0x3, 0x0 }, // 6802 |
| 14093 | { PseudoVMULHSU_VV_M8_MASK, VMULHSU_VV, 0x3, 0x0 }, // 6803 |
| 14094 | { PseudoVMULHSU_VV_MF8, VMULHSU_VV, 0x5, 0x0 }, // 6804 |
| 14095 | { PseudoVMULHSU_VV_MF8_MASK, VMULHSU_VV, 0x5, 0x0 }, // 6805 |
| 14096 | { PseudoVMULHSU_VV_MF4, VMULHSU_VV, 0x6, 0x0 }, // 6806 |
| 14097 | { PseudoVMULHSU_VV_MF4_MASK, VMULHSU_VV, 0x6, 0x0 }, // 6807 |
| 14098 | { PseudoVMULHSU_VV_MF2, VMULHSU_VV, 0x7, 0x0 }, // 6808 |
| 14099 | { PseudoVMULHSU_VV_MF2_MASK, VMULHSU_VV, 0x7, 0x0 }, // 6809 |
| 14100 | { PseudoVMULHSU_VX_M1, VMULHSU_VX, 0x0, 0x0 }, // 6810 |
| 14101 | { PseudoVMULHSU_VX_M1_MASK, VMULHSU_VX, 0x0, 0x0 }, // 6811 |
| 14102 | { PseudoVMULHSU_VX_M2, VMULHSU_VX, 0x1, 0x0 }, // 6812 |
| 14103 | { PseudoVMULHSU_VX_M2_MASK, VMULHSU_VX, 0x1, 0x0 }, // 6813 |
| 14104 | { PseudoVMULHSU_VX_M4, VMULHSU_VX, 0x2, 0x0 }, // 6814 |
| 14105 | { PseudoVMULHSU_VX_M4_MASK, VMULHSU_VX, 0x2, 0x0 }, // 6815 |
| 14106 | { PseudoVMULHSU_VX_M8, VMULHSU_VX, 0x3, 0x0 }, // 6816 |
| 14107 | { PseudoVMULHSU_VX_M8_MASK, VMULHSU_VX, 0x3, 0x0 }, // 6817 |
| 14108 | { PseudoVMULHSU_VX_MF8, VMULHSU_VX, 0x5, 0x0 }, // 6818 |
| 14109 | { PseudoVMULHSU_VX_MF8_MASK, VMULHSU_VX, 0x5, 0x0 }, // 6819 |
| 14110 | { PseudoVMULHSU_VX_MF4, VMULHSU_VX, 0x6, 0x0 }, // 6820 |
| 14111 | { PseudoVMULHSU_VX_MF4_MASK, VMULHSU_VX, 0x6, 0x0 }, // 6821 |
| 14112 | { PseudoVMULHSU_VX_MF2, VMULHSU_VX, 0x7, 0x0 }, // 6822 |
| 14113 | { PseudoVMULHSU_VX_MF2_MASK, VMULHSU_VX, 0x7, 0x0 }, // 6823 |
| 14114 | { PseudoVMULHU_VV_M1, VMULHU_VV, 0x0, 0x0 }, // 6824 |
| 14115 | { PseudoVMULHU_VV_M1_MASK, VMULHU_VV, 0x0, 0x0 }, // 6825 |
| 14116 | { PseudoVMULHU_VV_M2, VMULHU_VV, 0x1, 0x0 }, // 6826 |
| 14117 | { PseudoVMULHU_VV_M2_MASK, VMULHU_VV, 0x1, 0x0 }, // 6827 |
| 14118 | { PseudoVMULHU_VV_M4, VMULHU_VV, 0x2, 0x0 }, // 6828 |
| 14119 | { PseudoVMULHU_VV_M4_MASK, VMULHU_VV, 0x2, 0x0 }, // 6829 |
| 14120 | { PseudoVMULHU_VV_M8, VMULHU_VV, 0x3, 0x0 }, // 6830 |
| 14121 | { PseudoVMULHU_VV_M8_MASK, VMULHU_VV, 0x3, 0x0 }, // 6831 |
| 14122 | { PseudoVMULHU_VV_MF8, VMULHU_VV, 0x5, 0x0 }, // 6832 |
| 14123 | { PseudoVMULHU_VV_MF8_MASK, VMULHU_VV, 0x5, 0x0 }, // 6833 |
| 14124 | { PseudoVMULHU_VV_MF4, VMULHU_VV, 0x6, 0x0 }, // 6834 |
| 14125 | { PseudoVMULHU_VV_MF4_MASK, VMULHU_VV, 0x6, 0x0 }, // 6835 |
| 14126 | { PseudoVMULHU_VV_MF2, VMULHU_VV, 0x7, 0x0 }, // 6836 |
| 14127 | { PseudoVMULHU_VV_MF2_MASK, VMULHU_VV, 0x7, 0x0 }, // 6837 |
| 14128 | { PseudoVMULHU_VX_M1, VMULHU_VX, 0x0, 0x0 }, // 6838 |
| 14129 | { PseudoVMULHU_VX_M1_MASK, VMULHU_VX, 0x0, 0x0 }, // 6839 |
| 14130 | { PseudoVMULHU_VX_M2, VMULHU_VX, 0x1, 0x0 }, // 6840 |
| 14131 | { PseudoVMULHU_VX_M2_MASK, VMULHU_VX, 0x1, 0x0 }, // 6841 |
| 14132 | { PseudoVMULHU_VX_M4, VMULHU_VX, 0x2, 0x0 }, // 6842 |
| 14133 | { PseudoVMULHU_VX_M4_MASK, VMULHU_VX, 0x2, 0x0 }, // 6843 |
| 14134 | { PseudoVMULHU_VX_M8, VMULHU_VX, 0x3, 0x0 }, // 6844 |
| 14135 | { PseudoVMULHU_VX_M8_MASK, VMULHU_VX, 0x3, 0x0 }, // 6845 |
| 14136 | { PseudoVMULHU_VX_MF8, VMULHU_VX, 0x5, 0x0 }, // 6846 |
| 14137 | { PseudoVMULHU_VX_MF8_MASK, VMULHU_VX, 0x5, 0x0 }, // 6847 |
| 14138 | { PseudoVMULHU_VX_MF4, VMULHU_VX, 0x6, 0x0 }, // 6848 |
| 14139 | { PseudoVMULHU_VX_MF4_MASK, VMULHU_VX, 0x6, 0x0 }, // 6849 |
| 14140 | { PseudoVMULHU_VX_MF2, VMULHU_VX, 0x7, 0x0 }, // 6850 |
| 14141 | { PseudoVMULHU_VX_MF2_MASK, VMULHU_VX, 0x7, 0x0 }, // 6851 |
| 14142 | { PseudoVMULH_VV_M1, VMULH_VV, 0x0, 0x0 }, // 6852 |
| 14143 | { PseudoVMULH_VV_M1_MASK, VMULH_VV, 0x0, 0x0 }, // 6853 |
| 14144 | { PseudoVMULH_VV_M2, VMULH_VV, 0x1, 0x0 }, // 6854 |
| 14145 | { PseudoVMULH_VV_M2_MASK, VMULH_VV, 0x1, 0x0 }, // 6855 |
| 14146 | { PseudoVMULH_VV_M4, VMULH_VV, 0x2, 0x0 }, // 6856 |
| 14147 | { PseudoVMULH_VV_M4_MASK, VMULH_VV, 0x2, 0x0 }, // 6857 |
| 14148 | { PseudoVMULH_VV_M8, VMULH_VV, 0x3, 0x0 }, // 6858 |
| 14149 | { PseudoVMULH_VV_M8_MASK, VMULH_VV, 0x3, 0x0 }, // 6859 |
| 14150 | { PseudoVMULH_VV_MF8, VMULH_VV, 0x5, 0x0 }, // 6860 |
| 14151 | { PseudoVMULH_VV_MF8_MASK, VMULH_VV, 0x5, 0x0 }, // 6861 |
| 14152 | { PseudoVMULH_VV_MF4, VMULH_VV, 0x6, 0x0 }, // 6862 |
| 14153 | { PseudoVMULH_VV_MF4_MASK, VMULH_VV, 0x6, 0x0 }, // 6863 |
| 14154 | { PseudoVMULH_VV_MF2, VMULH_VV, 0x7, 0x0 }, // 6864 |
| 14155 | { PseudoVMULH_VV_MF2_MASK, VMULH_VV, 0x7, 0x0 }, // 6865 |
| 14156 | { PseudoVMULH_VX_M1, VMULH_VX, 0x0, 0x0 }, // 6866 |
| 14157 | { PseudoVMULH_VX_M1_MASK, VMULH_VX, 0x0, 0x0 }, // 6867 |
| 14158 | { PseudoVMULH_VX_M2, VMULH_VX, 0x1, 0x0 }, // 6868 |
| 14159 | { PseudoVMULH_VX_M2_MASK, VMULH_VX, 0x1, 0x0 }, // 6869 |
| 14160 | { PseudoVMULH_VX_M4, VMULH_VX, 0x2, 0x0 }, // 6870 |
| 14161 | { PseudoVMULH_VX_M4_MASK, VMULH_VX, 0x2, 0x0 }, // 6871 |
| 14162 | { PseudoVMULH_VX_M8, VMULH_VX, 0x3, 0x0 }, // 6872 |
| 14163 | { PseudoVMULH_VX_M8_MASK, VMULH_VX, 0x3, 0x0 }, // 6873 |
| 14164 | { PseudoVMULH_VX_MF8, VMULH_VX, 0x5, 0x0 }, // 6874 |
| 14165 | { PseudoVMULH_VX_MF8_MASK, VMULH_VX, 0x5, 0x0 }, // 6875 |
| 14166 | { PseudoVMULH_VX_MF4, VMULH_VX, 0x6, 0x0 }, // 6876 |
| 14167 | { PseudoVMULH_VX_MF4_MASK, VMULH_VX, 0x6, 0x0 }, // 6877 |
| 14168 | { PseudoVMULH_VX_MF2, VMULH_VX, 0x7, 0x0 }, // 6878 |
| 14169 | { PseudoVMULH_VX_MF2_MASK, VMULH_VX, 0x7, 0x0 }, // 6879 |
| 14170 | { PseudoVMUL_VV_M1, VMUL_VV, 0x0, 0x0 }, // 6880 |
| 14171 | { PseudoVMUL_VV_M1_MASK, VMUL_VV, 0x0, 0x0 }, // 6881 |
| 14172 | { PseudoVMUL_VV_M2, VMUL_VV, 0x1, 0x0 }, // 6882 |
| 14173 | { PseudoVMUL_VV_M2_MASK, VMUL_VV, 0x1, 0x0 }, // 6883 |
| 14174 | { PseudoVMUL_VV_M4, VMUL_VV, 0x2, 0x0 }, // 6884 |
| 14175 | { PseudoVMUL_VV_M4_MASK, VMUL_VV, 0x2, 0x0 }, // 6885 |
| 14176 | { PseudoVMUL_VV_M8, VMUL_VV, 0x3, 0x0 }, // 6886 |
| 14177 | { PseudoVMUL_VV_M8_MASK, VMUL_VV, 0x3, 0x0 }, // 6887 |
| 14178 | { PseudoVMUL_VV_MF8, VMUL_VV, 0x5, 0x0 }, // 6888 |
| 14179 | { PseudoVMUL_VV_MF8_MASK, VMUL_VV, 0x5, 0x0 }, // 6889 |
| 14180 | { PseudoVMUL_VV_MF4, VMUL_VV, 0x6, 0x0 }, // 6890 |
| 14181 | { PseudoVMUL_VV_MF4_MASK, VMUL_VV, 0x6, 0x0 }, // 6891 |
| 14182 | { PseudoVMUL_VV_MF2, VMUL_VV, 0x7, 0x0 }, // 6892 |
| 14183 | { PseudoVMUL_VV_MF2_MASK, VMUL_VV, 0x7, 0x0 }, // 6893 |
| 14184 | { PseudoVMUL_VX_M1, VMUL_VX, 0x0, 0x0 }, // 6894 |
| 14185 | { PseudoVMUL_VX_M1_MASK, VMUL_VX, 0x0, 0x0 }, // 6895 |
| 14186 | { PseudoVMUL_VX_M2, VMUL_VX, 0x1, 0x0 }, // 6896 |
| 14187 | { PseudoVMUL_VX_M2_MASK, VMUL_VX, 0x1, 0x0 }, // 6897 |
| 14188 | { PseudoVMUL_VX_M4, VMUL_VX, 0x2, 0x0 }, // 6898 |
| 14189 | { PseudoVMUL_VX_M4_MASK, VMUL_VX, 0x2, 0x0 }, // 6899 |
| 14190 | { PseudoVMUL_VX_M8, VMUL_VX, 0x3, 0x0 }, // 6900 |
| 14191 | { PseudoVMUL_VX_M8_MASK, VMUL_VX, 0x3, 0x0 }, // 6901 |
| 14192 | { PseudoVMUL_VX_MF8, VMUL_VX, 0x5, 0x0 }, // 6902 |
| 14193 | { PseudoVMUL_VX_MF8_MASK, VMUL_VX, 0x5, 0x0 }, // 6903 |
| 14194 | { PseudoVMUL_VX_MF4, VMUL_VX, 0x6, 0x0 }, // 6904 |
| 14195 | { PseudoVMUL_VX_MF4_MASK, VMUL_VX, 0x6, 0x0 }, // 6905 |
| 14196 | { PseudoVMUL_VX_MF2, VMUL_VX, 0x7, 0x0 }, // 6906 |
| 14197 | { PseudoVMUL_VX_MF2_MASK, VMUL_VX, 0x7, 0x0 }, // 6907 |
| 14198 | { PseudoVMV_S_X, VMV_S_X, 0x0, 0x0 }, // 6908 |
| 14199 | { PseudoVMV_V_I_M1, VMV_V_I, 0x0, 0x0 }, // 6909 |
| 14200 | { PseudoVMV_V_I_M2, VMV_V_I, 0x1, 0x0 }, // 6910 |
| 14201 | { PseudoVMV_V_I_M4, VMV_V_I, 0x2, 0x0 }, // 6911 |
| 14202 | { PseudoVMV_V_I_M8, VMV_V_I, 0x3, 0x0 }, // 6912 |
| 14203 | { PseudoVMV_V_I_MF8, VMV_V_I, 0x5, 0x0 }, // 6913 |
| 14204 | { PseudoVMV_V_I_MF4, VMV_V_I, 0x6, 0x0 }, // 6914 |
| 14205 | { PseudoVMV_V_I_MF2, VMV_V_I, 0x7, 0x0 }, // 6915 |
| 14206 | { PseudoVMV_V_V_M1, VMV_V_V, 0x0, 0x0 }, // 6916 |
| 14207 | { PseudoVMV_V_V_M2, VMV_V_V, 0x1, 0x0 }, // 6917 |
| 14208 | { PseudoVMV_V_V_M4, VMV_V_V, 0x2, 0x0 }, // 6918 |
| 14209 | { PseudoVMV_V_V_M8, VMV_V_V, 0x3, 0x0 }, // 6919 |
| 14210 | { PseudoVMV_V_V_MF8, VMV_V_V, 0x5, 0x0 }, // 6920 |
| 14211 | { PseudoVMV_V_V_MF4, VMV_V_V, 0x6, 0x0 }, // 6921 |
| 14212 | { PseudoVMV_V_V_MF2, VMV_V_V, 0x7, 0x0 }, // 6922 |
| 14213 | { PseudoVMV_V_X_M1, VMV_V_X, 0x0, 0x0 }, // 6923 |
| 14214 | { PseudoVMV_V_X_M2, VMV_V_X, 0x1, 0x0 }, // 6924 |
| 14215 | { PseudoVMV_V_X_M4, VMV_V_X, 0x2, 0x0 }, // 6925 |
| 14216 | { PseudoVMV_V_X_M8, VMV_V_X, 0x3, 0x0 }, // 6926 |
| 14217 | { PseudoVMV_V_X_MF8, VMV_V_X, 0x5, 0x0 }, // 6927 |
| 14218 | { PseudoVMV_V_X_MF4, VMV_V_X, 0x6, 0x0 }, // 6928 |
| 14219 | { PseudoVMV_V_X_MF2, VMV_V_X, 0x7, 0x0 }, // 6929 |
| 14220 | { PseudoVMV_X_S, VMV_X_S, 0x0, 0x0 }, // 6930 |
| 14221 | { PseudoVMSET_M_B8, VMXNOR_MM, 0x0, 0x0 }, // 6931 |
| 14222 | { PseudoVMXNOR_MM_M1, VMXNOR_MM, 0x0, 0x0 }, // 6932 |
| 14223 | { PseudoVMSET_M_B16, VMXNOR_MM, 0x1, 0x0 }, // 6933 |
| 14224 | { PseudoVMXNOR_MM_M2, VMXNOR_MM, 0x1, 0x0 }, // 6934 |
| 14225 | { PseudoVMSET_M_B32, VMXNOR_MM, 0x2, 0x0 }, // 6935 |
| 14226 | { PseudoVMXNOR_MM_M4, VMXNOR_MM, 0x2, 0x0 }, // 6936 |
| 14227 | { PseudoVMSET_M_B64, VMXNOR_MM, 0x3, 0x0 }, // 6937 |
| 14228 | { PseudoVMXNOR_MM_M8, VMXNOR_MM, 0x3, 0x0 }, // 6938 |
| 14229 | { PseudoVMSET_M_B1, VMXNOR_MM, 0x5, 0x0 }, // 6939 |
| 14230 | { PseudoVMXNOR_MM_MF8, VMXNOR_MM, 0x5, 0x0 }, // 6940 |
| 14231 | { PseudoVMSET_M_B2, VMXNOR_MM, 0x6, 0x0 }, // 6941 |
| 14232 | { PseudoVMXNOR_MM_MF4, VMXNOR_MM, 0x6, 0x0 }, // 6942 |
| 14233 | { PseudoVMSET_M_B4, VMXNOR_MM, 0x7, 0x0 }, // 6943 |
| 14234 | { PseudoVMXNOR_MM_MF2, VMXNOR_MM, 0x7, 0x0 }, // 6944 |
| 14235 | { PseudoVMCLR_M_B8, VMXOR_MM, 0x0, 0x0 }, // 6945 |
| 14236 | { PseudoVMXOR_MM_M1, VMXOR_MM, 0x0, 0x0 }, // 6946 |
| 14237 | { PseudoVMCLR_M_B16, VMXOR_MM, 0x1, 0x0 }, // 6947 |
| 14238 | { PseudoVMXOR_MM_M2, VMXOR_MM, 0x1, 0x0 }, // 6948 |
| 14239 | { PseudoVMCLR_M_B32, VMXOR_MM, 0x2, 0x0 }, // 6949 |
| 14240 | { PseudoVMXOR_MM_M4, VMXOR_MM, 0x2, 0x0 }, // 6950 |
| 14241 | { PseudoVMCLR_M_B64, VMXOR_MM, 0x3, 0x0 }, // 6951 |
| 14242 | { PseudoVMXOR_MM_M8, VMXOR_MM, 0x3, 0x0 }, // 6952 |
| 14243 | { PseudoVMCLR_M_B1, VMXOR_MM, 0x5, 0x0 }, // 6953 |
| 14244 | { PseudoVMXOR_MM_MF8, VMXOR_MM, 0x5, 0x0 }, // 6954 |
| 14245 | { PseudoVMCLR_M_B2, VMXOR_MM, 0x6, 0x0 }, // 6955 |
| 14246 | { PseudoVMXOR_MM_MF4, VMXOR_MM, 0x6, 0x0 }, // 6956 |
| 14247 | { PseudoVMCLR_M_B4, VMXOR_MM, 0x7, 0x0 }, // 6957 |
| 14248 | { PseudoVMXOR_MM_MF2, VMXOR_MM, 0x7, 0x0 }, // 6958 |
| 14249 | { PseudoVNCLIPU_WI_M1, VNCLIPU_WI, 0x0, 0x0 }, // 6959 |
| 14250 | { PseudoVNCLIPU_WI_M1_MASK, VNCLIPU_WI, 0x0, 0x0 }, // 6960 |
| 14251 | { PseudoVNCLIPU_WI_M2, VNCLIPU_WI, 0x1, 0x0 }, // 6961 |
| 14252 | { PseudoVNCLIPU_WI_M2_MASK, VNCLIPU_WI, 0x1, 0x0 }, // 6962 |
| 14253 | { PseudoVNCLIPU_WI_M4, VNCLIPU_WI, 0x2, 0x0 }, // 6963 |
| 14254 | { PseudoVNCLIPU_WI_M4_MASK, VNCLIPU_WI, 0x2, 0x0 }, // 6964 |
| 14255 | { PseudoVNCLIPU_WI_MF8, VNCLIPU_WI, 0x5, 0x0 }, // 6965 |
| 14256 | { PseudoVNCLIPU_WI_MF8_MASK, VNCLIPU_WI, 0x5, 0x0 }, // 6966 |
| 14257 | { PseudoVNCLIPU_WI_MF4, VNCLIPU_WI, 0x6, 0x0 }, // 6967 |
| 14258 | { PseudoVNCLIPU_WI_MF4_MASK, VNCLIPU_WI, 0x6, 0x0 }, // 6968 |
| 14259 | { PseudoVNCLIPU_WI_MF2, VNCLIPU_WI, 0x7, 0x0 }, // 6969 |
| 14260 | { PseudoVNCLIPU_WI_MF2_MASK, VNCLIPU_WI, 0x7, 0x0 }, // 6970 |
| 14261 | { PseudoVNCLIPU_WV_M1, VNCLIPU_WV, 0x0, 0x0 }, // 6971 |
| 14262 | { PseudoVNCLIPU_WV_M1_MASK, VNCLIPU_WV, 0x0, 0x0 }, // 6972 |
| 14263 | { PseudoVNCLIPU_WV_M2, VNCLIPU_WV, 0x1, 0x0 }, // 6973 |
| 14264 | { PseudoVNCLIPU_WV_M2_MASK, VNCLIPU_WV, 0x1, 0x0 }, // 6974 |
| 14265 | { PseudoVNCLIPU_WV_M4, VNCLIPU_WV, 0x2, 0x0 }, // 6975 |
| 14266 | { PseudoVNCLIPU_WV_M4_MASK, VNCLIPU_WV, 0x2, 0x0 }, // 6976 |
| 14267 | { PseudoVNCLIPU_WV_MF8, VNCLIPU_WV, 0x5, 0x0 }, // 6977 |
| 14268 | { PseudoVNCLIPU_WV_MF8_MASK, VNCLIPU_WV, 0x5, 0x0 }, // 6978 |
| 14269 | { PseudoVNCLIPU_WV_MF4, VNCLIPU_WV, 0x6, 0x0 }, // 6979 |
| 14270 | { PseudoVNCLIPU_WV_MF4_MASK, VNCLIPU_WV, 0x6, 0x0 }, // 6980 |
| 14271 | { PseudoVNCLIPU_WV_MF2, VNCLIPU_WV, 0x7, 0x0 }, // 6981 |
| 14272 | { PseudoVNCLIPU_WV_MF2_MASK, VNCLIPU_WV, 0x7, 0x0 }, // 6982 |
| 14273 | { PseudoVNCLIPU_WX_M1, VNCLIPU_WX, 0x0, 0x0 }, // 6983 |
| 14274 | { PseudoVNCLIPU_WX_M1_MASK, VNCLIPU_WX, 0x0, 0x0 }, // 6984 |
| 14275 | { PseudoVNCLIPU_WX_M2, VNCLIPU_WX, 0x1, 0x0 }, // 6985 |
| 14276 | { PseudoVNCLIPU_WX_M2_MASK, VNCLIPU_WX, 0x1, 0x0 }, // 6986 |
| 14277 | { PseudoVNCLIPU_WX_M4, VNCLIPU_WX, 0x2, 0x0 }, // 6987 |
| 14278 | { PseudoVNCLIPU_WX_M4_MASK, VNCLIPU_WX, 0x2, 0x0 }, // 6988 |
| 14279 | { PseudoVNCLIPU_WX_MF8, VNCLIPU_WX, 0x5, 0x0 }, // 6989 |
| 14280 | { PseudoVNCLIPU_WX_MF8_MASK, VNCLIPU_WX, 0x5, 0x0 }, // 6990 |
| 14281 | { PseudoVNCLIPU_WX_MF4, VNCLIPU_WX, 0x6, 0x0 }, // 6991 |
| 14282 | { PseudoVNCLIPU_WX_MF4_MASK, VNCLIPU_WX, 0x6, 0x0 }, // 6992 |
| 14283 | { PseudoVNCLIPU_WX_MF2, VNCLIPU_WX, 0x7, 0x0 }, // 6993 |
| 14284 | { PseudoVNCLIPU_WX_MF2_MASK, VNCLIPU_WX, 0x7, 0x0 }, // 6994 |
| 14285 | { PseudoVNCLIP_WI_M1, VNCLIP_WI, 0x0, 0x0 }, // 6995 |
| 14286 | { PseudoVNCLIP_WI_M1_MASK, VNCLIP_WI, 0x0, 0x0 }, // 6996 |
| 14287 | { PseudoVNCLIP_WI_M2, VNCLIP_WI, 0x1, 0x0 }, // 6997 |
| 14288 | { PseudoVNCLIP_WI_M2_MASK, VNCLIP_WI, 0x1, 0x0 }, // 6998 |
| 14289 | { PseudoVNCLIP_WI_M4, VNCLIP_WI, 0x2, 0x0 }, // 6999 |
| 14290 | { PseudoVNCLIP_WI_M4_MASK, VNCLIP_WI, 0x2, 0x0 }, // 7000 |
| 14291 | { PseudoVNCLIP_WI_MF8, VNCLIP_WI, 0x5, 0x0 }, // 7001 |
| 14292 | { PseudoVNCLIP_WI_MF8_MASK, VNCLIP_WI, 0x5, 0x0 }, // 7002 |
| 14293 | { PseudoVNCLIP_WI_MF4, VNCLIP_WI, 0x6, 0x0 }, // 7003 |
| 14294 | { PseudoVNCLIP_WI_MF4_MASK, VNCLIP_WI, 0x6, 0x0 }, // 7004 |
| 14295 | { PseudoVNCLIP_WI_MF2, VNCLIP_WI, 0x7, 0x0 }, // 7005 |
| 14296 | { PseudoVNCLIP_WI_MF2_MASK, VNCLIP_WI, 0x7, 0x0 }, // 7006 |
| 14297 | { PseudoVNCLIP_WV_M1, VNCLIP_WV, 0x0, 0x0 }, // 7007 |
| 14298 | { PseudoVNCLIP_WV_M1_MASK, VNCLIP_WV, 0x0, 0x0 }, // 7008 |
| 14299 | { PseudoVNCLIP_WV_M2, VNCLIP_WV, 0x1, 0x0 }, // 7009 |
| 14300 | { PseudoVNCLIP_WV_M2_MASK, VNCLIP_WV, 0x1, 0x0 }, // 7010 |
| 14301 | { PseudoVNCLIP_WV_M4, VNCLIP_WV, 0x2, 0x0 }, // 7011 |
| 14302 | { PseudoVNCLIP_WV_M4_MASK, VNCLIP_WV, 0x2, 0x0 }, // 7012 |
| 14303 | { PseudoVNCLIP_WV_MF8, VNCLIP_WV, 0x5, 0x0 }, // 7013 |
| 14304 | { PseudoVNCLIP_WV_MF8_MASK, VNCLIP_WV, 0x5, 0x0 }, // 7014 |
| 14305 | { PseudoVNCLIP_WV_MF4, VNCLIP_WV, 0x6, 0x0 }, // 7015 |
| 14306 | { PseudoVNCLIP_WV_MF4_MASK, VNCLIP_WV, 0x6, 0x0 }, // 7016 |
| 14307 | { PseudoVNCLIP_WV_MF2, VNCLIP_WV, 0x7, 0x0 }, // 7017 |
| 14308 | { PseudoVNCLIP_WV_MF2_MASK, VNCLIP_WV, 0x7, 0x0 }, // 7018 |
| 14309 | { PseudoVNCLIP_WX_M1, VNCLIP_WX, 0x0, 0x0 }, // 7019 |
| 14310 | { PseudoVNCLIP_WX_M1_MASK, VNCLIP_WX, 0x0, 0x0 }, // 7020 |
| 14311 | { PseudoVNCLIP_WX_M2, VNCLIP_WX, 0x1, 0x0 }, // 7021 |
| 14312 | { PseudoVNCLIP_WX_M2_MASK, VNCLIP_WX, 0x1, 0x0 }, // 7022 |
| 14313 | { PseudoVNCLIP_WX_M4, VNCLIP_WX, 0x2, 0x0 }, // 7023 |
| 14314 | { PseudoVNCLIP_WX_M4_MASK, VNCLIP_WX, 0x2, 0x0 }, // 7024 |
| 14315 | { PseudoVNCLIP_WX_MF8, VNCLIP_WX, 0x5, 0x0 }, // 7025 |
| 14316 | { PseudoVNCLIP_WX_MF8_MASK, VNCLIP_WX, 0x5, 0x0 }, // 7026 |
| 14317 | { PseudoVNCLIP_WX_MF4, VNCLIP_WX, 0x6, 0x0 }, // 7027 |
| 14318 | { PseudoVNCLIP_WX_MF4_MASK, VNCLIP_WX, 0x6, 0x0 }, // 7028 |
| 14319 | { PseudoVNCLIP_WX_MF2, VNCLIP_WX, 0x7, 0x0 }, // 7029 |
| 14320 | { PseudoVNCLIP_WX_MF2_MASK, VNCLIP_WX, 0x7, 0x0 }, // 7030 |
| 14321 | { PseudoVNMSAC_VV_M1, VNMSAC_VV, 0x0, 0x0 }, // 7031 |
| 14322 | { PseudoVNMSAC_VV_M1_MASK, VNMSAC_VV, 0x0, 0x0 }, // 7032 |
| 14323 | { PseudoVNMSAC_VV_M2, VNMSAC_VV, 0x1, 0x0 }, // 7033 |
| 14324 | { PseudoVNMSAC_VV_M2_MASK, VNMSAC_VV, 0x1, 0x0 }, // 7034 |
| 14325 | { PseudoVNMSAC_VV_M4, VNMSAC_VV, 0x2, 0x0 }, // 7035 |
| 14326 | { PseudoVNMSAC_VV_M4_MASK, VNMSAC_VV, 0x2, 0x0 }, // 7036 |
| 14327 | { PseudoVNMSAC_VV_M8, VNMSAC_VV, 0x3, 0x0 }, // 7037 |
| 14328 | { PseudoVNMSAC_VV_M8_MASK, VNMSAC_VV, 0x3, 0x0 }, // 7038 |
| 14329 | { PseudoVNMSAC_VV_MF8, VNMSAC_VV, 0x5, 0x0 }, // 7039 |
| 14330 | { PseudoVNMSAC_VV_MF8_MASK, VNMSAC_VV, 0x5, 0x0 }, // 7040 |
| 14331 | { PseudoVNMSAC_VV_MF4, VNMSAC_VV, 0x6, 0x0 }, // 7041 |
| 14332 | { PseudoVNMSAC_VV_MF4_MASK, VNMSAC_VV, 0x6, 0x0 }, // 7042 |
| 14333 | { PseudoVNMSAC_VV_MF2, VNMSAC_VV, 0x7, 0x0 }, // 7043 |
| 14334 | { PseudoVNMSAC_VV_MF2_MASK, VNMSAC_VV, 0x7, 0x0 }, // 7044 |
| 14335 | { PseudoVNMSAC_VX_M1, VNMSAC_VX, 0x0, 0x0 }, // 7045 |
| 14336 | { PseudoVNMSAC_VX_M1_MASK, VNMSAC_VX, 0x0, 0x0 }, // 7046 |
| 14337 | { PseudoVNMSAC_VX_M2, VNMSAC_VX, 0x1, 0x0 }, // 7047 |
| 14338 | { PseudoVNMSAC_VX_M2_MASK, VNMSAC_VX, 0x1, 0x0 }, // 7048 |
| 14339 | { PseudoVNMSAC_VX_M4, VNMSAC_VX, 0x2, 0x0 }, // 7049 |
| 14340 | { PseudoVNMSAC_VX_M4_MASK, VNMSAC_VX, 0x2, 0x0 }, // 7050 |
| 14341 | { PseudoVNMSAC_VX_M8, VNMSAC_VX, 0x3, 0x0 }, // 7051 |
| 14342 | { PseudoVNMSAC_VX_M8_MASK, VNMSAC_VX, 0x3, 0x0 }, // 7052 |
| 14343 | { PseudoVNMSAC_VX_MF8, VNMSAC_VX, 0x5, 0x0 }, // 7053 |
| 14344 | { PseudoVNMSAC_VX_MF8_MASK, VNMSAC_VX, 0x5, 0x0 }, // 7054 |
| 14345 | { PseudoVNMSAC_VX_MF4, VNMSAC_VX, 0x6, 0x0 }, // 7055 |
| 14346 | { PseudoVNMSAC_VX_MF4_MASK, VNMSAC_VX, 0x6, 0x0 }, // 7056 |
| 14347 | { PseudoVNMSAC_VX_MF2, VNMSAC_VX, 0x7, 0x0 }, // 7057 |
| 14348 | { PseudoVNMSAC_VX_MF2_MASK, VNMSAC_VX, 0x7, 0x0 }, // 7058 |
| 14349 | { PseudoVNMSUB_VV_M1, VNMSUB_VV, 0x0, 0x0 }, // 7059 |
| 14350 | { PseudoVNMSUB_VV_M1_MASK, VNMSUB_VV, 0x0, 0x0 }, // 7060 |
| 14351 | { PseudoVNMSUB_VV_M2, VNMSUB_VV, 0x1, 0x0 }, // 7061 |
| 14352 | { PseudoVNMSUB_VV_M2_MASK, VNMSUB_VV, 0x1, 0x0 }, // 7062 |
| 14353 | { PseudoVNMSUB_VV_M4, VNMSUB_VV, 0x2, 0x0 }, // 7063 |
| 14354 | { PseudoVNMSUB_VV_M4_MASK, VNMSUB_VV, 0x2, 0x0 }, // 7064 |
| 14355 | { PseudoVNMSUB_VV_M8, VNMSUB_VV, 0x3, 0x0 }, // 7065 |
| 14356 | { PseudoVNMSUB_VV_M8_MASK, VNMSUB_VV, 0x3, 0x0 }, // 7066 |
| 14357 | { PseudoVNMSUB_VV_MF8, VNMSUB_VV, 0x5, 0x0 }, // 7067 |
| 14358 | { PseudoVNMSUB_VV_MF8_MASK, VNMSUB_VV, 0x5, 0x0 }, // 7068 |
| 14359 | { PseudoVNMSUB_VV_MF4, VNMSUB_VV, 0x6, 0x0 }, // 7069 |
| 14360 | { PseudoVNMSUB_VV_MF4_MASK, VNMSUB_VV, 0x6, 0x0 }, // 7070 |
| 14361 | { PseudoVNMSUB_VV_MF2, VNMSUB_VV, 0x7, 0x0 }, // 7071 |
| 14362 | { PseudoVNMSUB_VV_MF2_MASK, VNMSUB_VV, 0x7, 0x0 }, // 7072 |
| 14363 | { PseudoVNMSUB_VX_M1, VNMSUB_VX, 0x0, 0x0 }, // 7073 |
| 14364 | { PseudoVNMSUB_VX_M1_MASK, VNMSUB_VX, 0x0, 0x0 }, // 7074 |
| 14365 | { PseudoVNMSUB_VX_M2, VNMSUB_VX, 0x1, 0x0 }, // 7075 |
| 14366 | { PseudoVNMSUB_VX_M2_MASK, VNMSUB_VX, 0x1, 0x0 }, // 7076 |
| 14367 | { PseudoVNMSUB_VX_M4, VNMSUB_VX, 0x2, 0x0 }, // 7077 |
| 14368 | { PseudoVNMSUB_VX_M4_MASK, VNMSUB_VX, 0x2, 0x0 }, // 7078 |
| 14369 | { PseudoVNMSUB_VX_M8, VNMSUB_VX, 0x3, 0x0 }, // 7079 |
| 14370 | { PseudoVNMSUB_VX_M8_MASK, VNMSUB_VX, 0x3, 0x0 }, // 7080 |
| 14371 | { PseudoVNMSUB_VX_MF8, VNMSUB_VX, 0x5, 0x0 }, // 7081 |
| 14372 | { PseudoVNMSUB_VX_MF8_MASK, VNMSUB_VX, 0x5, 0x0 }, // 7082 |
| 14373 | { PseudoVNMSUB_VX_MF4, VNMSUB_VX, 0x6, 0x0 }, // 7083 |
| 14374 | { PseudoVNMSUB_VX_MF4_MASK, VNMSUB_VX, 0x6, 0x0 }, // 7084 |
| 14375 | { PseudoVNMSUB_VX_MF2, VNMSUB_VX, 0x7, 0x0 }, // 7085 |
| 14376 | { PseudoVNMSUB_VX_MF2_MASK, VNMSUB_VX, 0x7, 0x0 }, // 7086 |
| 14377 | { PseudoVNSRA_WI_M1, VNSRA_WI, 0x0, 0x0 }, // 7087 |
| 14378 | { PseudoVNSRA_WI_M1_MASK, VNSRA_WI, 0x0, 0x0 }, // 7088 |
| 14379 | { PseudoVNSRA_WI_M2, VNSRA_WI, 0x1, 0x0 }, // 7089 |
| 14380 | { PseudoVNSRA_WI_M2_MASK, VNSRA_WI, 0x1, 0x0 }, // 7090 |
| 14381 | { PseudoVNSRA_WI_M4, VNSRA_WI, 0x2, 0x0 }, // 7091 |
| 14382 | { PseudoVNSRA_WI_M4_MASK, VNSRA_WI, 0x2, 0x0 }, // 7092 |
| 14383 | { PseudoVNSRA_WI_MF8, VNSRA_WI, 0x5, 0x0 }, // 7093 |
| 14384 | { PseudoVNSRA_WI_MF8_MASK, VNSRA_WI, 0x5, 0x0 }, // 7094 |
| 14385 | { PseudoVNSRA_WI_MF4, VNSRA_WI, 0x6, 0x0 }, // 7095 |
| 14386 | { PseudoVNSRA_WI_MF4_MASK, VNSRA_WI, 0x6, 0x0 }, // 7096 |
| 14387 | { PseudoVNSRA_WI_MF2, VNSRA_WI, 0x7, 0x0 }, // 7097 |
| 14388 | { PseudoVNSRA_WI_MF2_MASK, VNSRA_WI, 0x7, 0x0 }, // 7098 |
| 14389 | { PseudoVNSRA_WV_M1, VNSRA_WV, 0x0, 0x0 }, // 7099 |
| 14390 | { PseudoVNSRA_WV_M1_MASK, VNSRA_WV, 0x0, 0x0 }, // 7100 |
| 14391 | { PseudoVNSRA_WV_M2, VNSRA_WV, 0x1, 0x0 }, // 7101 |
| 14392 | { PseudoVNSRA_WV_M2_MASK, VNSRA_WV, 0x1, 0x0 }, // 7102 |
| 14393 | { PseudoVNSRA_WV_M4, VNSRA_WV, 0x2, 0x0 }, // 7103 |
| 14394 | { PseudoVNSRA_WV_M4_MASK, VNSRA_WV, 0x2, 0x0 }, // 7104 |
| 14395 | { PseudoVNSRA_WV_MF8, VNSRA_WV, 0x5, 0x0 }, // 7105 |
| 14396 | { PseudoVNSRA_WV_MF8_MASK, VNSRA_WV, 0x5, 0x0 }, // 7106 |
| 14397 | { PseudoVNSRA_WV_MF4, VNSRA_WV, 0x6, 0x0 }, // 7107 |
| 14398 | { PseudoVNSRA_WV_MF4_MASK, VNSRA_WV, 0x6, 0x0 }, // 7108 |
| 14399 | { PseudoVNSRA_WV_MF2, VNSRA_WV, 0x7, 0x0 }, // 7109 |
| 14400 | { PseudoVNSRA_WV_MF2_MASK, VNSRA_WV, 0x7, 0x0 }, // 7110 |
| 14401 | { PseudoVNSRA_WX_M1, VNSRA_WX, 0x0, 0x0 }, // 7111 |
| 14402 | { PseudoVNSRA_WX_M1_MASK, VNSRA_WX, 0x0, 0x0 }, // 7112 |
| 14403 | { PseudoVNSRA_WX_M2, VNSRA_WX, 0x1, 0x0 }, // 7113 |
| 14404 | { PseudoVNSRA_WX_M2_MASK, VNSRA_WX, 0x1, 0x0 }, // 7114 |
| 14405 | { PseudoVNSRA_WX_M4, VNSRA_WX, 0x2, 0x0 }, // 7115 |
| 14406 | { PseudoVNSRA_WX_M4_MASK, VNSRA_WX, 0x2, 0x0 }, // 7116 |
| 14407 | { PseudoVNSRA_WX_MF8, VNSRA_WX, 0x5, 0x0 }, // 7117 |
| 14408 | { PseudoVNSRA_WX_MF8_MASK, VNSRA_WX, 0x5, 0x0 }, // 7118 |
| 14409 | { PseudoVNSRA_WX_MF4, VNSRA_WX, 0x6, 0x0 }, // 7119 |
| 14410 | { PseudoVNSRA_WX_MF4_MASK, VNSRA_WX, 0x6, 0x0 }, // 7120 |
| 14411 | { PseudoVNSRA_WX_MF2, VNSRA_WX, 0x7, 0x0 }, // 7121 |
| 14412 | { PseudoVNSRA_WX_MF2_MASK, VNSRA_WX, 0x7, 0x0 }, // 7122 |
| 14413 | { PseudoVNSRL_WI_M1, VNSRL_WI, 0x0, 0x0 }, // 7123 |
| 14414 | { PseudoVNSRL_WI_M1_MASK, VNSRL_WI, 0x0, 0x0 }, // 7124 |
| 14415 | { PseudoVNSRL_WI_M2, VNSRL_WI, 0x1, 0x0 }, // 7125 |
| 14416 | { PseudoVNSRL_WI_M2_MASK, VNSRL_WI, 0x1, 0x0 }, // 7126 |
| 14417 | { PseudoVNSRL_WI_M4, VNSRL_WI, 0x2, 0x0 }, // 7127 |
| 14418 | { PseudoVNSRL_WI_M4_MASK, VNSRL_WI, 0x2, 0x0 }, // 7128 |
| 14419 | { PseudoVNSRL_WI_MF8, VNSRL_WI, 0x5, 0x0 }, // 7129 |
| 14420 | { PseudoVNSRL_WI_MF8_MASK, VNSRL_WI, 0x5, 0x0 }, // 7130 |
| 14421 | { PseudoVNSRL_WI_MF4, VNSRL_WI, 0x6, 0x0 }, // 7131 |
| 14422 | { PseudoVNSRL_WI_MF4_MASK, VNSRL_WI, 0x6, 0x0 }, // 7132 |
| 14423 | { PseudoVNSRL_WI_MF2, VNSRL_WI, 0x7, 0x0 }, // 7133 |
| 14424 | { PseudoVNSRL_WI_MF2_MASK, VNSRL_WI, 0x7, 0x0 }, // 7134 |
| 14425 | { PseudoVNSRL_WV_M1, VNSRL_WV, 0x0, 0x0 }, // 7135 |
| 14426 | { PseudoVNSRL_WV_M1_MASK, VNSRL_WV, 0x0, 0x0 }, // 7136 |
| 14427 | { PseudoVNSRL_WV_M2, VNSRL_WV, 0x1, 0x0 }, // 7137 |
| 14428 | { PseudoVNSRL_WV_M2_MASK, VNSRL_WV, 0x1, 0x0 }, // 7138 |
| 14429 | { PseudoVNSRL_WV_M4, VNSRL_WV, 0x2, 0x0 }, // 7139 |
| 14430 | { PseudoVNSRL_WV_M4_MASK, VNSRL_WV, 0x2, 0x0 }, // 7140 |
| 14431 | { PseudoVNSRL_WV_MF8, VNSRL_WV, 0x5, 0x0 }, // 7141 |
| 14432 | { PseudoVNSRL_WV_MF8_MASK, VNSRL_WV, 0x5, 0x0 }, // 7142 |
| 14433 | { PseudoVNSRL_WV_MF4, VNSRL_WV, 0x6, 0x0 }, // 7143 |
| 14434 | { PseudoVNSRL_WV_MF4_MASK, VNSRL_WV, 0x6, 0x0 }, // 7144 |
| 14435 | { PseudoVNSRL_WV_MF2, VNSRL_WV, 0x7, 0x0 }, // 7145 |
| 14436 | { PseudoVNSRL_WV_MF2_MASK, VNSRL_WV, 0x7, 0x0 }, // 7146 |
| 14437 | { PseudoVNSRL_WX_M1, VNSRL_WX, 0x0, 0x0 }, // 7147 |
| 14438 | { PseudoVNSRL_WX_M1_MASK, VNSRL_WX, 0x0, 0x0 }, // 7148 |
| 14439 | { PseudoVNSRL_WX_M2, VNSRL_WX, 0x1, 0x0 }, // 7149 |
| 14440 | { PseudoVNSRL_WX_M2_MASK, VNSRL_WX, 0x1, 0x0 }, // 7150 |
| 14441 | { PseudoVNSRL_WX_M4, VNSRL_WX, 0x2, 0x0 }, // 7151 |
| 14442 | { PseudoVNSRL_WX_M4_MASK, VNSRL_WX, 0x2, 0x0 }, // 7152 |
| 14443 | { PseudoVNSRL_WX_MF8, VNSRL_WX, 0x5, 0x0 }, // 7153 |
| 14444 | { PseudoVNSRL_WX_MF8_MASK, VNSRL_WX, 0x5, 0x0 }, // 7154 |
| 14445 | { PseudoVNSRL_WX_MF4, VNSRL_WX, 0x6, 0x0 }, // 7155 |
| 14446 | { PseudoVNSRL_WX_MF4_MASK, VNSRL_WX, 0x6, 0x0 }, // 7156 |
| 14447 | { PseudoVNSRL_WX_MF2, VNSRL_WX, 0x7, 0x0 }, // 7157 |
| 14448 | { PseudoVNSRL_WX_MF2_MASK, VNSRL_WX, 0x7, 0x0 }, // 7158 |
| 14449 | { PseudoVOR_VI_M1, VOR_VI, 0x0, 0x0 }, // 7159 |
| 14450 | { PseudoVOR_VI_M1_MASK, VOR_VI, 0x0, 0x0 }, // 7160 |
| 14451 | { PseudoVOR_VI_M2, VOR_VI, 0x1, 0x0 }, // 7161 |
| 14452 | { PseudoVOR_VI_M2_MASK, VOR_VI, 0x1, 0x0 }, // 7162 |
| 14453 | { PseudoVOR_VI_M4, VOR_VI, 0x2, 0x0 }, // 7163 |
| 14454 | { PseudoVOR_VI_M4_MASK, VOR_VI, 0x2, 0x0 }, // 7164 |
| 14455 | { PseudoVOR_VI_M8, VOR_VI, 0x3, 0x0 }, // 7165 |
| 14456 | { PseudoVOR_VI_M8_MASK, VOR_VI, 0x3, 0x0 }, // 7166 |
| 14457 | { PseudoVOR_VI_MF8, VOR_VI, 0x5, 0x0 }, // 7167 |
| 14458 | { PseudoVOR_VI_MF8_MASK, VOR_VI, 0x5, 0x0 }, // 7168 |
| 14459 | { PseudoVOR_VI_MF4, VOR_VI, 0x6, 0x0 }, // 7169 |
| 14460 | { PseudoVOR_VI_MF4_MASK, VOR_VI, 0x6, 0x0 }, // 7170 |
| 14461 | { PseudoVOR_VI_MF2, VOR_VI, 0x7, 0x0 }, // 7171 |
| 14462 | { PseudoVOR_VI_MF2_MASK, VOR_VI, 0x7, 0x0 }, // 7172 |
| 14463 | { PseudoVOR_VV_M1, VOR_VV, 0x0, 0x0 }, // 7173 |
| 14464 | { PseudoVOR_VV_M1_MASK, VOR_VV, 0x0, 0x0 }, // 7174 |
| 14465 | { PseudoVOR_VV_M2, VOR_VV, 0x1, 0x0 }, // 7175 |
| 14466 | { PseudoVOR_VV_M2_MASK, VOR_VV, 0x1, 0x0 }, // 7176 |
| 14467 | { PseudoVOR_VV_M4, VOR_VV, 0x2, 0x0 }, // 7177 |
| 14468 | { PseudoVOR_VV_M4_MASK, VOR_VV, 0x2, 0x0 }, // 7178 |
| 14469 | { PseudoVOR_VV_M8, VOR_VV, 0x3, 0x0 }, // 7179 |
| 14470 | { PseudoVOR_VV_M8_MASK, VOR_VV, 0x3, 0x0 }, // 7180 |
| 14471 | { PseudoVOR_VV_MF8, VOR_VV, 0x5, 0x0 }, // 7181 |
| 14472 | { PseudoVOR_VV_MF8_MASK, VOR_VV, 0x5, 0x0 }, // 7182 |
| 14473 | { PseudoVOR_VV_MF4, VOR_VV, 0x6, 0x0 }, // 7183 |
| 14474 | { PseudoVOR_VV_MF4_MASK, VOR_VV, 0x6, 0x0 }, // 7184 |
| 14475 | { PseudoVOR_VV_MF2, VOR_VV, 0x7, 0x0 }, // 7185 |
| 14476 | { PseudoVOR_VV_MF2_MASK, VOR_VV, 0x7, 0x0 }, // 7186 |
| 14477 | { PseudoVOR_VX_M1, VOR_VX, 0x0, 0x0 }, // 7187 |
| 14478 | { PseudoVOR_VX_M1_MASK, VOR_VX, 0x0, 0x0 }, // 7188 |
| 14479 | { PseudoVOR_VX_M2, VOR_VX, 0x1, 0x0 }, // 7189 |
| 14480 | { PseudoVOR_VX_M2_MASK, VOR_VX, 0x1, 0x0 }, // 7190 |
| 14481 | { PseudoVOR_VX_M4, VOR_VX, 0x2, 0x0 }, // 7191 |
| 14482 | { PseudoVOR_VX_M4_MASK, VOR_VX, 0x2, 0x0 }, // 7192 |
| 14483 | { PseudoVOR_VX_M8, VOR_VX, 0x3, 0x0 }, // 7193 |
| 14484 | { PseudoVOR_VX_M8_MASK, VOR_VX, 0x3, 0x0 }, // 7194 |
| 14485 | { PseudoVOR_VX_MF8, VOR_VX, 0x5, 0x0 }, // 7195 |
| 14486 | { PseudoVOR_VX_MF8_MASK, VOR_VX, 0x5, 0x0 }, // 7196 |
| 14487 | { PseudoVOR_VX_MF4, VOR_VX, 0x6, 0x0 }, // 7197 |
| 14488 | { PseudoVOR_VX_MF4_MASK, VOR_VX, 0x6, 0x0 }, // 7198 |
| 14489 | { PseudoVOR_VX_MF2, VOR_VX, 0x7, 0x0 }, // 7199 |
| 14490 | { PseudoVOR_VX_MF2_MASK, VOR_VX, 0x7, 0x0 }, // 7200 |
| 14491 | { PseudoVQMACCSU_2x8x2_M1, VQMACCSU_2x8x2, 0x0, 0x0 }, // 7201 |
| 14492 | { PseudoVQMACCSU_2x8x2_M2, VQMACCSU_2x8x2, 0x1, 0x0 }, // 7202 |
| 14493 | { PseudoVQMACCSU_2x8x2_M4, VQMACCSU_2x8x2, 0x2, 0x0 }, // 7203 |
| 14494 | { PseudoVQMACCSU_2x8x2_M8, VQMACCSU_2x8x2, 0x3, 0x0 }, // 7204 |
| 14495 | { PseudoVQMACCSU_4x8x4_M1, VQMACCSU_4x8x4, 0x0, 0x0 }, // 7205 |
| 14496 | { PseudoVQMACCSU_4x8x4_M2, VQMACCSU_4x8x4, 0x1, 0x0 }, // 7206 |
| 14497 | { PseudoVQMACCSU_4x8x4_M4, VQMACCSU_4x8x4, 0x2, 0x0 }, // 7207 |
| 14498 | { PseudoVQMACCSU_4x8x4_MF2, VQMACCSU_4x8x4, 0x7, 0x0 }, // 7208 |
| 14499 | { PseudoVQMACCUS_2x8x2_M1, VQMACCUS_2x8x2, 0x0, 0x0 }, // 7209 |
| 14500 | { PseudoVQMACCUS_2x8x2_M2, VQMACCUS_2x8x2, 0x1, 0x0 }, // 7210 |
| 14501 | { PseudoVQMACCUS_2x8x2_M4, VQMACCUS_2x8x2, 0x2, 0x0 }, // 7211 |
| 14502 | { PseudoVQMACCUS_2x8x2_M8, VQMACCUS_2x8x2, 0x3, 0x0 }, // 7212 |
| 14503 | { PseudoVQMACCUS_4x8x4_M1, VQMACCUS_4x8x4, 0x0, 0x0 }, // 7213 |
| 14504 | { PseudoVQMACCUS_4x8x4_M2, VQMACCUS_4x8x4, 0x1, 0x0 }, // 7214 |
| 14505 | { PseudoVQMACCUS_4x8x4_M4, VQMACCUS_4x8x4, 0x2, 0x0 }, // 7215 |
| 14506 | { PseudoVQMACCUS_4x8x4_MF2, VQMACCUS_4x8x4, 0x7, 0x0 }, // 7216 |
| 14507 | { PseudoVQMACCU_2x8x2_M1, VQMACCU_2x8x2, 0x0, 0x0 }, // 7217 |
| 14508 | { PseudoVQMACCU_2x8x2_M2, VQMACCU_2x8x2, 0x1, 0x0 }, // 7218 |
| 14509 | { PseudoVQMACCU_2x8x2_M4, VQMACCU_2x8x2, 0x2, 0x0 }, // 7219 |
| 14510 | { PseudoVQMACCU_2x8x2_M8, VQMACCU_2x8x2, 0x3, 0x0 }, // 7220 |
| 14511 | { PseudoVQMACCU_4x8x4_M1, VQMACCU_4x8x4, 0x0, 0x0 }, // 7221 |
| 14512 | { PseudoVQMACCU_4x8x4_M2, VQMACCU_4x8x4, 0x1, 0x0 }, // 7222 |
| 14513 | { PseudoVQMACCU_4x8x4_M4, VQMACCU_4x8x4, 0x2, 0x0 }, // 7223 |
| 14514 | { PseudoVQMACCU_4x8x4_MF2, VQMACCU_4x8x4, 0x7, 0x0 }, // 7224 |
| 14515 | { PseudoVQMACC_2x8x2_M1, VQMACC_2x8x2, 0x0, 0x0 }, // 7225 |
| 14516 | { PseudoVQMACC_2x8x2_M2, VQMACC_2x8x2, 0x1, 0x0 }, // 7226 |
| 14517 | { PseudoVQMACC_2x8x2_M4, VQMACC_2x8x2, 0x2, 0x0 }, // 7227 |
| 14518 | { PseudoVQMACC_2x8x2_M8, VQMACC_2x8x2, 0x3, 0x0 }, // 7228 |
| 14519 | { PseudoVQMACC_4x8x4_M1, VQMACC_4x8x4, 0x0, 0x0 }, // 7229 |
| 14520 | { PseudoVQMACC_4x8x4_M2, VQMACC_4x8x4, 0x1, 0x0 }, // 7230 |
| 14521 | { PseudoVQMACC_4x8x4_M4, VQMACC_4x8x4, 0x2, 0x0 }, // 7231 |
| 14522 | { PseudoVQMACC_4x8x4_MF2, VQMACC_4x8x4, 0x7, 0x0 }, // 7232 |
| 14523 | { PseudoVREDAND_VS_M1_E8, VREDAND_VS, 0x0, 0x8 }, // 7233 |
| 14524 | { PseudoVREDAND_VS_M1_E8_MASK, VREDAND_VS, 0x0, 0x8 }, // 7234 |
| 14525 | { PseudoVREDAND_VS_M1_E16, VREDAND_VS, 0x0, 0x10 }, // 7235 |
| 14526 | { PseudoVREDAND_VS_M1_E16_MASK, VREDAND_VS, 0x0, 0x10 }, // 7236 |
| 14527 | { PseudoVREDAND_VS_M1_E32, VREDAND_VS, 0x0, 0x20 }, // 7237 |
| 14528 | { PseudoVREDAND_VS_M1_E32_MASK, VREDAND_VS, 0x0, 0x20 }, // 7238 |
| 14529 | { PseudoVREDAND_VS_M1_E64, VREDAND_VS, 0x0, 0x40 }, // 7239 |
| 14530 | { PseudoVREDAND_VS_M1_E64_MASK, VREDAND_VS, 0x0, 0x40 }, // 7240 |
| 14531 | { PseudoVREDAND_VS_M2_E8, VREDAND_VS, 0x1, 0x8 }, // 7241 |
| 14532 | { PseudoVREDAND_VS_M2_E8_MASK, VREDAND_VS, 0x1, 0x8 }, // 7242 |
| 14533 | { PseudoVREDAND_VS_M2_E16, VREDAND_VS, 0x1, 0x10 }, // 7243 |
| 14534 | { PseudoVREDAND_VS_M2_E16_MASK, VREDAND_VS, 0x1, 0x10 }, // 7244 |
| 14535 | { PseudoVREDAND_VS_M2_E32, VREDAND_VS, 0x1, 0x20 }, // 7245 |
| 14536 | { PseudoVREDAND_VS_M2_E32_MASK, VREDAND_VS, 0x1, 0x20 }, // 7246 |
| 14537 | { PseudoVREDAND_VS_M2_E64, VREDAND_VS, 0x1, 0x40 }, // 7247 |
| 14538 | { PseudoVREDAND_VS_M2_E64_MASK, VREDAND_VS, 0x1, 0x40 }, // 7248 |
| 14539 | { PseudoVREDAND_VS_M4_E8, VREDAND_VS, 0x2, 0x8 }, // 7249 |
| 14540 | { PseudoVREDAND_VS_M4_E8_MASK, VREDAND_VS, 0x2, 0x8 }, // 7250 |
| 14541 | { PseudoVREDAND_VS_M4_E16, VREDAND_VS, 0x2, 0x10 }, // 7251 |
| 14542 | { PseudoVREDAND_VS_M4_E16_MASK, VREDAND_VS, 0x2, 0x10 }, // 7252 |
| 14543 | { PseudoVREDAND_VS_M4_E32, VREDAND_VS, 0x2, 0x20 }, // 7253 |
| 14544 | { PseudoVREDAND_VS_M4_E32_MASK, VREDAND_VS, 0x2, 0x20 }, // 7254 |
| 14545 | { PseudoVREDAND_VS_M4_E64, VREDAND_VS, 0x2, 0x40 }, // 7255 |
| 14546 | { PseudoVREDAND_VS_M4_E64_MASK, VREDAND_VS, 0x2, 0x40 }, // 7256 |
| 14547 | { PseudoVREDAND_VS_M8_E8, VREDAND_VS, 0x3, 0x8 }, // 7257 |
| 14548 | { PseudoVREDAND_VS_M8_E8_MASK, VREDAND_VS, 0x3, 0x8 }, // 7258 |
| 14549 | { PseudoVREDAND_VS_M8_E16, VREDAND_VS, 0x3, 0x10 }, // 7259 |
| 14550 | { PseudoVREDAND_VS_M8_E16_MASK, VREDAND_VS, 0x3, 0x10 }, // 7260 |
| 14551 | { PseudoVREDAND_VS_M8_E32, VREDAND_VS, 0x3, 0x20 }, // 7261 |
| 14552 | { PseudoVREDAND_VS_M8_E32_MASK, VREDAND_VS, 0x3, 0x20 }, // 7262 |
| 14553 | { PseudoVREDAND_VS_M8_E64, VREDAND_VS, 0x3, 0x40 }, // 7263 |
| 14554 | { PseudoVREDAND_VS_M8_E64_MASK, VREDAND_VS, 0x3, 0x40 }, // 7264 |
| 14555 | { PseudoVREDAND_VS_MF8_E8, VREDAND_VS, 0x5, 0x8 }, // 7265 |
| 14556 | { PseudoVREDAND_VS_MF8_E8_MASK, VREDAND_VS, 0x5, 0x8 }, // 7266 |
| 14557 | { PseudoVREDAND_VS_MF4_E8, VREDAND_VS, 0x6, 0x8 }, // 7267 |
| 14558 | { PseudoVREDAND_VS_MF4_E8_MASK, VREDAND_VS, 0x6, 0x8 }, // 7268 |
| 14559 | { PseudoVREDAND_VS_MF4_E16, VREDAND_VS, 0x6, 0x10 }, // 7269 |
| 14560 | { PseudoVREDAND_VS_MF4_E16_MASK, VREDAND_VS, 0x6, 0x10 }, // 7270 |
| 14561 | { PseudoVREDAND_VS_MF2_E8, VREDAND_VS, 0x7, 0x8 }, // 7271 |
| 14562 | { PseudoVREDAND_VS_MF2_E8_MASK, VREDAND_VS, 0x7, 0x8 }, // 7272 |
| 14563 | { PseudoVREDAND_VS_MF2_E16, VREDAND_VS, 0x7, 0x10 }, // 7273 |
| 14564 | { PseudoVREDAND_VS_MF2_E16_MASK, VREDAND_VS, 0x7, 0x10 }, // 7274 |
| 14565 | { PseudoVREDAND_VS_MF2_E32, VREDAND_VS, 0x7, 0x20 }, // 7275 |
| 14566 | { PseudoVREDAND_VS_MF2_E32_MASK, VREDAND_VS, 0x7, 0x20 }, // 7276 |
| 14567 | { PseudoVREDMAXU_VS_M1_E8, VREDMAXU_VS, 0x0, 0x8 }, // 7277 |
| 14568 | { PseudoVREDMAXU_VS_M1_E8_MASK, VREDMAXU_VS, 0x0, 0x8 }, // 7278 |
| 14569 | { PseudoVREDMAXU_VS_M1_E16, VREDMAXU_VS, 0x0, 0x10 }, // 7279 |
| 14570 | { PseudoVREDMAXU_VS_M1_E16_MASK, VREDMAXU_VS, 0x0, 0x10 }, // 7280 |
| 14571 | { PseudoVREDMAXU_VS_M1_E32, VREDMAXU_VS, 0x0, 0x20 }, // 7281 |
| 14572 | { PseudoVREDMAXU_VS_M1_E32_MASK, VREDMAXU_VS, 0x0, 0x20 }, // 7282 |
| 14573 | { PseudoVREDMAXU_VS_M1_E64, VREDMAXU_VS, 0x0, 0x40 }, // 7283 |
| 14574 | { PseudoVREDMAXU_VS_M1_E64_MASK, VREDMAXU_VS, 0x0, 0x40 }, // 7284 |
| 14575 | { PseudoVREDMAXU_VS_M2_E8, VREDMAXU_VS, 0x1, 0x8 }, // 7285 |
| 14576 | { PseudoVREDMAXU_VS_M2_E8_MASK, VREDMAXU_VS, 0x1, 0x8 }, // 7286 |
| 14577 | { PseudoVREDMAXU_VS_M2_E16, VREDMAXU_VS, 0x1, 0x10 }, // 7287 |
| 14578 | { PseudoVREDMAXU_VS_M2_E16_MASK, VREDMAXU_VS, 0x1, 0x10 }, // 7288 |
| 14579 | { PseudoVREDMAXU_VS_M2_E32, VREDMAXU_VS, 0x1, 0x20 }, // 7289 |
| 14580 | { PseudoVREDMAXU_VS_M2_E32_MASK, VREDMAXU_VS, 0x1, 0x20 }, // 7290 |
| 14581 | { PseudoVREDMAXU_VS_M2_E64, VREDMAXU_VS, 0x1, 0x40 }, // 7291 |
| 14582 | { PseudoVREDMAXU_VS_M2_E64_MASK, VREDMAXU_VS, 0x1, 0x40 }, // 7292 |
| 14583 | { PseudoVREDMAXU_VS_M4_E8, VREDMAXU_VS, 0x2, 0x8 }, // 7293 |
| 14584 | { PseudoVREDMAXU_VS_M4_E8_MASK, VREDMAXU_VS, 0x2, 0x8 }, // 7294 |
| 14585 | { PseudoVREDMAXU_VS_M4_E16, VREDMAXU_VS, 0x2, 0x10 }, // 7295 |
| 14586 | { PseudoVREDMAXU_VS_M4_E16_MASK, VREDMAXU_VS, 0x2, 0x10 }, // 7296 |
| 14587 | { PseudoVREDMAXU_VS_M4_E32, VREDMAXU_VS, 0x2, 0x20 }, // 7297 |
| 14588 | { PseudoVREDMAXU_VS_M4_E32_MASK, VREDMAXU_VS, 0x2, 0x20 }, // 7298 |
| 14589 | { PseudoVREDMAXU_VS_M4_E64, VREDMAXU_VS, 0x2, 0x40 }, // 7299 |
| 14590 | { PseudoVREDMAXU_VS_M4_E64_MASK, VREDMAXU_VS, 0x2, 0x40 }, // 7300 |
| 14591 | { PseudoVREDMAXU_VS_M8_E8, VREDMAXU_VS, 0x3, 0x8 }, // 7301 |
| 14592 | { PseudoVREDMAXU_VS_M8_E8_MASK, VREDMAXU_VS, 0x3, 0x8 }, // 7302 |
| 14593 | { PseudoVREDMAXU_VS_M8_E16, VREDMAXU_VS, 0x3, 0x10 }, // 7303 |
| 14594 | { PseudoVREDMAXU_VS_M8_E16_MASK, VREDMAXU_VS, 0x3, 0x10 }, // 7304 |
| 14595 | { PseudoVREDMAXU_VS_M8_E32, VREDMAXU_VS, 0x3, 0x20 }, // 7305 |
| 14596 | { PseudoVREDMAXU_VS_M8_E32_MASK, VREDMAXU_VS, 0x3, 0x20 }, // 7306 |
| 14597 | { PseudoVREDMAXU_VS_M8_E64, VREDMAXU_VS, 0x3, 0x40 }, // 7307 |
| 14598 | { PseudoVREDMAXU_VS_M8_E64_MASK, VREDMAXU_VS, 0x3, 0x40 }, // 7308 |
| 14599 | { PseudoVREDMAXU_VS_MF8_E8, VREDMAXU_VS, 0x5, 0x8 }, // 7309 |
| 14600 | { PseudoVREDMAXU_VS_MF8_E8_MASK, VREDMAXU_VS, 0x5, 0x8 }, // 7310 |
| 14601 | { PseudoVREDMAXU_VS_MF4_E8, VREDMAXU_VS, 0x6, 0x8 }, // 7311 |
| 14602 | { PseudoVREDMAXU_VS_MF4_E8_MASK, VREDMAXU_VS, 0x6, 0x8 }, // 7312 |
| 14603 | { PseudoVREDMAXU_VS_MF4_E16, VREDMAXU_VS, 0x6, 0x10 }, // 7313 |
| 14604 | { PseudoVREDMAXU_VS_MF4_E16_MASK, VREDMAXU_VS, 0x6, 0x10 }, // 7314 |
| 14605 | { PseudoVREDMAXU_VS_MF2_E8, VREDMAXU_VS, 0x7, 0x8 }, // 7315 |
| 14606 | { PseudoVREDMAXU_VS_MF2_E8_MASK, VREDMAXU_VS, 0x7, 0x8 }, // 7316 |
| 14607 | { PseudoVREDMAXU_VS_MF2_E16, VREDMAXU_VS, 0x7, 0x10 }, // 7317 |
| 14608 | { PseudoVREDMAXU_VS_MF2_E16_MASK, VREDMAXU_VS, 0x7, 0x10 }, // 7318 |
| 14609 | { PseudoVREDMAXU_VS_MF2_E32, VREDMAXU_VS, 0x7, 0x20 }, // 7319 |
| 14610 | { PseudoVREDMAXU_VS_MF2_E32_MASK, VREDMAXU_VS, 0x7, 0x20 }, // 7320 |
| 14611 | { PseudoVREDMAX_VS_M1_E8, VREDMAX_VS, 0x0, 0x8 }, // 7321 |
| 14612 | { PseudoVREDMAX_VS_M1_E8_MASK, VREDMAX_VS, 0x0, 0x8 }, // 7322 |
| 14613 | { PseudoVREDMAX_VS_M1_E16, VREDMAX_VS, 0x0, 0x10 }, // 7323 |
| 14614 | { PseudoVREDMAX_VS_M1_E16_MASK, VREDMAX_VS, 0x0, 0x10 }, // 7324 |
| 14615 | { PseudoVREDMAX_VS_M1_E32, VREDMAX_VS, 0x0, 0x20 }, // 7325 |
| 14616 | { PseudoVREDMAX_VS_M1_E32_MASK, VREDMAX_VS, 0x0, 0x20 }, // 7326 |
| 14617 | { PseudoVREDMAX_VS_M1_E64, VREDMAX_VS, 0x0, 0x40 }, // 7327 |
| 14618 | { PseudoVREDMAX_VS_M1_E64_MASK, VREDMAX_VS, 0x0, 0x40 }, // 7328 |
| 14619 | { PseudoVREDMAX_VS_M2_E8, VREDMAX_VS, 0x1, 0x8 }, // 7329 |
| 14620 | { PseudoVREDMAX_VS_M2_E8_MASK, VREDMAX_VS, 0x1, 0x8 }, // 7330 |
| 14621 | { PseudoVREDMAX_VS_M2_E16, VREDMAX_VS, 0x1, 0x10 }, // 7331 |
| 14622 | { PseudoVREDMAX_VS_M2_E16_MASK, VREDMAX_VS, 0x1, 0x10 }, // 7332 |
| 14623 | { PseudoVREDMAX_VS_M2_E32, VREDMAX_VS, 0x1, 0x20 }, // 7333 |
| 14624 | { PseudoVREDMAX_VS_M2_E32_MASK, VREDMAX_VS, 0x1, 0x20 }, // 7334 |
| 14625 | { PseudoVREDMAX_VS_M2_E64, VREDMAX_VS, 0x1, 0x40 }, // 7335 |
| 14626 | { PseudoVREDMAX_VS_M2_E64_MASK, VREDMAX_VS, 0x1, 0x40 }, // 7336 |
| 14627 | { PseudoVREDMAX_VS_M4_E8, VREDMAX_VS, 0x2, 0x8 }, // 7337 |
| 14628 | { PseudoVREDMAX_VS_M4_E8_MASK, VREDMAX_VS, 0x2, 0x8 }, // 7338 |
| 14629 | { PseudoVREDMAX_VS_M4_E16, VREDMAX_VS, 0x2, 0x10 }, // 7339 |
| 14630 | { PseudoVREDMAX_VS_M4_E16_MASK, VREDMAX_VS, 0x2, 0x10 }, // 7340 |
| 14631 | { PseudoVREDMAX_VS_M4_E32, VREDMAX_VS, 0x2, 0x20 }, // 7341 |
| 14632 | { PseudoVREDMAX_VS_M4_E32_MASK, VREDMAX_VS, 0x2, 0x20 }, // 7342 |
| 14633 | { PseudoVREDMAX_VS_M4_E64, VREDMAX_VS, 0x2, 0x40 }, // 7343 |
| 14634 | { PseudoVREDMAX_VS_M4_E64_MASK, VREDMAX_VS, 0x2, 0x40 }, // 7344 |
| 14635 | { PseudoVREDMAX_VS_M8_E8, VREDMAX_VS, 0x3, 0x8 }, // 7345 |
| 14636 | { PseudoVREDMAX_VS_M8_E8_MASK, VREDMAX_VS, 0x3, 0x8 }, // 7346 |
| 14637 | { PseudoVREDMAX_VS_M8_E16, VREDMAX_VS, 0x3, 0x10 }, // 7347 |
| 14638 | { PseudoVREDMAX_VS_M8_E16_MASK, VREDMAX_VS, 0x3, 0x10 }, // 7348 |
| 14639 | { PseudoVREDMAX_VS_M8_E32, VREDMAX_VS, 0x3, 0x20 }, // 7349 |
| 14640 | { PseudoVREDMAX_VS_M8_E32_MASK, VREDMAX_VS, 0x3, 0x20 }, // 7350 |
| 14641 | { PseudoVREDMAX_VS_M8_E64, VREDMAX_VS, 0x3, 0x40 }, // 7351 |
| 14642 | { PseudoVREDMAX_VS_M8_E64_MASK, VREDMAX_VS, 0x3, 0x40 }, // 7352 |
| 14643 | { PseudoVREDMAX_VS_MF8_E8, VREDMAX_VS, 0x5, 0x8 }, // 7353 |
| 14644 | { PseudoVREDMAX_VS_MF8_E8_MASK, VREDMAX_VS, 0x5, 0x8 }, // 7354 |
| 14645 | { PseudoVREDMAX_VS_MF4_E8, VREDMAX_VS, 0x6, 0x8 }, // 7355 |
| 14646 | { PseudoVREDMAX_VS_MF4_E8_MASK, VREDMAX_VS, 0x6, 0x8 }, // 7356 |
| 14647 | { PseudoVREDMAX_VS_MF4_E16, VREDMAX_VS, 0x6, 0x10 }, // 7357 |
| 14648 | { PseudoVREDMAX_VS_MF4_E16_MASK, VREDMAX_VS, 0x6, 0x10 }, // 7358 |
| 14649 | { PseudoVREDMAX_VS_MF2_E8, VREDMAX_VS, 0x7, 0x8 }, // 7359 |
| 14650 | { PseudoVREDMAX_VS_MF2_E8_MASK, VREDMAX_VS, 0x7, 0x8 }, // 7360 |
| 14651 | { PseudoVREDMAX_VS_MF2_E16, VREDMAX_VS, 0x7, 0x10 }, // 7361 |
| 14652 | { PseudoVREDMAX_VS_MF2_E16_MASK, VREDMAX_VS, 0x7, 0x10 }, // 7362 |
| 14653 | { PseudoVREDMAX_VS_MF2_E32, VREDMAX_VS, 0x7, 0x20 }, // 7363 |
| 14654 | { PseudoVREDMAX_VS_MF2_E32_MASK, VREDMAX_VS, 0x7, 0x20 }, // 7364 |
| 14655 | { PseudoVREDMINU_VS_M1_E8, VREDMINU_VS, 0x0, 0x8 }, // 7365 |
| 14656 | { PseudoVREDMINU_VS_M1_E8_MASK, VREDMINU_VS, 0x0, 0x8 }, // 7366 |
| 14657 | { PseudoVREDMINU_VS_M1_E16, VREDMINU_VS, 0x0, 0x10 }, // 7367 |
| 14658 | { PseudoVREDMINU_VS_M1_E16_MASK, VREDMINU_VS, 0x0, 0x10 }, // 7368 |
| 14659 | { PseudoVREDMINU_VS_M1_E32, VREDMINU_VS, 0x0, 0x20 }, // 7369 |
| 14660 | { PseudoVREDMINU_VS_M1_E32_MASK, VREDMINU_VS, 0x0, 0x20 }, // 7370 |
| 14661 | { PseudoVREDMINU_VS_M1_E64, VREDMINU_VS, 0x0, 0x40 }, // 7371 |
| 14662 | { PseudoVREDMINU_VS_M1_E64_MASK, VREDMINU_VS, 0x0, 0x40 }, // 7372 |
| 14663 | { PseudoVREDMINU_VS_M2_E8, VREDMINU_VS, 0x1, 0x8 }, // 7373 |
| 14664 | { PseudoVREDMINU_VS_M2_E8_MASK, VREDMINU_VS, 0x1, 0x8 }, // 7374 |
| 14665 | { PseudoVREDMINU_VS_M2_E16, VREDMINU_VS, 0x1, 0x10 }, // 7375 |
| 14666 | { PseudoVREDMINU_VS_M2_E16_MASK, VREDMINU_VS, 0x1, 0x10 }, // 7376 |
| 14667 | { PseudoVREDMINU_VS_M2_E32, VREDMINU_VS, 0x1, 0x20 }, // 7377 |
| 14668 | { PseudoVREDMINU_VS_M2_E32_MASK, VREDMINU_VS, 0x1, 0x20 }, // 7378 |
| 14669 | { PseudoVREDMINU_VS_M2_E64, VREDMINU_VS, 0x1, 0x40 }, // 7379 |
| 14670 | { PseudoVREDMINU_VS_M2_E64_MASK, VREDMINU_VS, 0x1, 0x40 }, // 7380 |
| 14671 | { PseudoVREDMINU_VS_M4_E8, VREDMINU_VS, 0x2, 0x8 }, // 7381 |
| 14672 | { PseudoVREDMINU_VS_M4_E8_MASK, VREDMINU_VS, 0x2, 0x8 }, // 7382 |
| 14673 | { PseudoVREDMINU_VS_M4_E16, VREDMINU_VS, 0x2, 0x10 }, // 7383 |
| 14674 | { PseudoVREDMINU_VS_M4_E16_MASK, VREDMINU_VS, 0x2, 0x10 }, // 7384 |
| 14675 | { PseudoVREDMINU_VS_M4_E32, VREDMINU_VS, 0x2, 0x20 }, // 7385 |
| 14676 | { PseudoVREDMINU_VS_M4_E32_MASK, VREDMINU_VS, 0x2, 0x20 }, // 7386 |
| 14677 | { PseudoVREDMINU_VS_M4_E64, VREDMINU_VS, 0x2, 0x40 }, // 7387 |
| 14678 | { PseudoVREDMINU_VS_M4_E64_MASK, VREDMINU_VS, 0x2, 0x40 }, // 7388 |
| 14679 | { PseudoVREDMINU_VS_M8_E8, VREDMINU_VS, 0x3, 0x8 }, // 7389 |
| 14680 | { PseudoVREDMINU_VS_M8_E8_MASK, VREDMINU_VS, 0x3, 0x8 }, // 7390 |
| 14681 | { PseudoVREDMINU_VS_M8_E16, VREDMINU_VS, 0x3, 0x10 }, // 7391 |
| 14682 | { PseudoVREDMINU_VS_M8_E16_MASK, VREDMINU_VS, 0x3, 0x10 }, // 7392 |
| 14683 | { PseudoVREDMINU_VS_M8_E32, VREDMINU_VS, 0x3, 0x20 }, // 7393 |
| 14684 | { PseudoVREDMINU_VS_M8_E32_MASK, VREDMINU_VS, 0x3, 0x20 }, // 7394 |
| 14685 | { PseudoVREDMINU_VS_M8_E64, VREDMINU_VS, 0x3, 0x40 }, // 7395 |
| 14686 | { PseudoVREDMINU_VS_M8_E64_MASK, VREDMINU_VS, 0x3, 0x40 }, // 7396 |
| 14687 | { PseudoVREDMINU_VS_MF8_E8, VREDMINU_VS, 0x5, 0x8 }, // 7397 |
| 14688 | { PseudoVREDMINU_VS_MF8_E8_MASK, VREDMINU_VS, 0x5, 0x8 }, // 7398 |
| 14689 | { PseudoVREDMINU_VS_MF4_E8, VREDMINU_VS, 0x6, 0x8 }, // 7399 |
| 14690 | { PseudoVREDMINU_VS_MF4_E8_MASK, VREDMINU_VS, 0x6, 0x8 }, // 7400 |
| 14691 | { PseudoVREDMINU_VS_MF4_E16, VREDMINU_VS, 0x6, 0x10 }, // 7401 |
| 14692 | { PseudoVREDMINU_VS_MF4_E16_MASK, VREDMINU_VS, 0x6, 0x10 }, // 7402 |
| 14693 | { PseudoVREDMINU_VS_MF2_E8, VREDMINU_VS, 0x7, 0x8 }, // 7403 |
| 14694 | { PseudoVREDMINU_VS_MF2_E8_MASK, VREDMINU_VS, 0x7, 0x8 }, // 7404 |
| 14695 | { PseudoVREDMINU_VS_MF2_E16, VREDMINU_VS, 0x7, 0x10 }, // 7405 |
| 14696 | { PseudoVREDMINU_VS_MF2_E16_MASK, VREDMINU_VS, 0x7, 0x10 }, // 7406 |
| 14697 | { PseudoVREDMINU_VS_MF2_E32, VREDMINU_VS, 0x7, 0x20 }, // 7407 |
| 14698 | { PseudoVREDMINU_VS_MF2_E32_MASK, VREDMINU_VS, 0x7, 0x20 }, // 7408 |
| 14699 | { PseudoVREDMIN_VS_M1_E8, VREDMIN_VS, 0x0, 0x8 }, // 7409 |
| 14700 | { PseudoVREDMIN_VS_M1_E8_MASK, VREDMIN_VS, 0x0, 0x8 }, // 7410 |
| 14701 | { PseudoVREDMIN_VS_M1_E16, VREDMIN_VS, 0x0, 0x10 }, // 7411 |
| 14702 | { PseudoVREDMIN_VS_M1_E16_MASK, VREDMIN_VS, 0x0, 0x10 }, // 7412 |
| 14703 | { PseudoVREDMIN_VS_M1_E32, VREDMIN_VS, 0x0, 0x20 }, // 7413 |
| 14704 | { PseudoVREDMIN_VS_M1_E32_MASK, VREDMIN_VS, 0x0, 0x20 }, // 7414 |
| 14705 | { PseudoVREDMIN_VS_M1_E64, VREDMIN_VS, 0x0, 0x40 }, // 7415 |
| 14706 | { PseudoVREDMIN_VS_M1_E64_MASK, VREDMIN_VS, 0x0, 0x40 }, // 7416 |
| 14707 | { PseudoVREDMIN_VS_M2_E8, VREDMIN_VS, 0x1, 0x8 }, // 7417 |
| 14708 | { PseudoVREDMIN_VS_M2_E8_MASK, VREDMIN_VS, 0x1, 0x8 }, // 7418 |
| 14709 | { PseudoVREDMIN_VS_M2_E16, VREDMIN_VS, 0x1, 0x10 }, // 7419 |
| 14710 | { PseudoVREDMIN_VS_M2_E16_MASK, VREDMIN_VS, 0x1, 0x10 }, // 7420 |
| 14711 | { PseudoVREDMIN_VS_M2_E32, VREDMIN_VS, 0x1, 0x20 }, // 7421 |
| 14712 | { PseudoVREDMIN_VS_M2_E32_MASK, VREDMIN_VS, 0x1, 0x20 }, // 7422 |
| 14713 | { PseudoVREDMIN_VS_M2_E64, VREDMIN_VS, 0x1, 0x40 }, // 7423 |
| 14714 | { PseudoVREDMIN_VS_M2_E64_MASK, VREDMIN_VS, 0x1, 0x40 }, // 7424 |
| 14715 | { PseudoVREDMIN_VS_M4_E8, VREDMIN_VS, 0x2, 0x8 }, // 7425 |
| 14716 | { PseudoVREDMIN_VS_M4_E8_MASK, VREDMIN_VS, 0x2, 0x8 }, // 7426 |
| 14717 | { PseudoVREDMIN_VS_M4_E16, VREDMIN_VS, 0x2, 0x10 }, // 7427 |
| 14718 | { PseudoVREDMIN_VS_M4_E16_MASK, VREDMIN_VS, 0x2, 0x10 }, // 7428 |
| 14719 | { PseudoVREDMIN_VS_M4_E32, VREDMIN_VS, 0x2, 0x20 }, // 7429 |
| 14720 | { PseudoVREDMIN_VS_M4_E32_MASK, VREDMIN_VS, 0x2, 0x20 }, // 7430 |
| 14721 | { PseudoVREDMIN_VS_M4_E64, VREDMIN_VS, 0x2, 0x40 }, // 7431 |
| 14722 | { PseudoVREDMIN_VS_M4_E64_MASK, VREDMIN_VS, 0x2, 0x40 }, // 7432 |
| 14723 | { PseudoVREDMIN_VS_M8_E8, VREDMIN_VS, 0x3, 0x8 }, // 7433 |
| 14724 | { PseudoVREDMIN_VS_M8_E8_MASK, VREDMIN_VS, 0x3, 0x8 }, // 7434 |
| 14725 | { PseudoVREDMIN_VS_M8_E16, VREDMIN_VS, 0x3, 0x10 }, // 7435 |
| 14726 | { PseudoVREDMIN_VS_M8_E16_MASK, VREDMIN_VS, 0x3, 0x10 }, // 7436 |
| 14727 | { PseudoVREDMIN_VS_M8_E32, VREDMIN_VS, 0x3, 0x20 }, // 7437 |
| 14728 | { PseudoVREDMIN_VS_M8_E32_MASK, VREDMIN_VS, 0x3, 0x20 }, // 7438 |
| 14729 | { PseudoVREDMIN_VS_M8_E64, VREDMIN_VS, 0x3, 0x40 }, // 7439 |
| 14730 | { PseudoVREDMIN_VS_M8_E64_MASK, VREDMIN_VS, 0x3, 0x40 }, // 7440 |
| 14731 | { PseudoVREDMIN_VS_MF8_E8, VREDMIN_VS, 0x5, 0x8 }, // 7441 |
| 14732 | { PseudoVREDMIN_VS_MF8_E8_MASK, VREDMIN_VS, 0x5, 0x8 }, // 7442 |
| 14733 | { PseudoVREDMIN_VS_MF4_E8, VREDMIN_VS, 0x6, 0x8 }, // 7443 |
| 14734 | { PseudoVREDMIN_VS_MF4_E8_MASK, VREDMIN_VS, 0x6, 0x8 }, // 7444 |
| 14735 | { PseudoVREDMIN_VS_MF4_E16, VREDMIN_VS, 0x6, 0x10 }, // 7445 |
| 14736 | { PseudoVREDMIN_VS_MF4_E16_MASK, VREDMIN_VS, 0x6, 0x10 }, // 7446 |
| 14737 | { PseudoVREDMIN_VS_MF2_E8, VREDMIN_VS, 0x7, 0x8 }, // 7447 |
| 14738 | { PseudoVREDMIN_VS_MF2_E8_MASK, VREDMIN_VS, 0x7, 0x8 }, // 7448 |
| 14739 | { PseudoVREDMIN_VS_MF2_E16, VREDMIN_VS, 0x7, 0x10 }, // 7449 |
| 14740 | { PseudoVREDMIN_VS_MF2_E16_MASK, VREDMIN_VS, 0x7, 0x10 }, // 7450 |
| 14741 | { PseudoVREDMIN_VS_MF2_E32, VREDMIN_VS, 0x7, 0x20 }, // 7451 |
| 14742 | { PseudoVREDMIN_VS_MF2_E32_MASK, VREDMIN_VS, 0x7, 0x20 }, // 7452 |
| 14743 | { PseudoVREDOR_VS_M1_E8, VREDOR_VS, 0x0, 0x8 }, // 7453 |
| 14744 | { PseudoVREDOR_VS_M1_E8_MASK, VREDOR_VS, 0x0, 0x8 }, // 7454 |
| 14745 | { PseudoVREDOR_VS_M1_E16, VREDOR_VS, 0x0, 0x10 }, // 7455 |
| 14746 | { PseudoVREDOR_VS_M1_E16_MASK, VREDOR_VS, 0x0, 0x10 }, // 7456 |
| 14747 | { PseudoVREDOR_VS_M1_E32, VREDOR_VS, 0x0, 0x20 }, // 7457 |
| 14748 | { PseudoVREDOR_VS_M1_E32_MASK, VREDOR_VS, 0x0, 0x20 }, // 7458 |
| 14749 | { PseudoVREDOR_VS_M1_E64, VREDOR_VS, 0x0, 0x40 }, // 7459 |
| 14750 | { PseudoVREDOR_VS_M1_E64_MASK, VREDOR_VS, 0x0, 0x40 }, // 7460 |
| 14751 | { PseudoVREDOR_VS_M2_E8, VREDOR_VS, 0x1, 0x8 }, // 7461 |
| 14752 | { PseudoVREDOR_VS_M2_E8_MASK, VREDOR_VS, 0x1, 0x8 }, // 7462 |
| 14753 | { PseudoVREDOR_VS_M2_E16, VREDOR_VS, 0x1, 0x10 }, // 7463 |
| 14754 | { PseudoVREDOR_VS_M2_E16_MASK, VREDOR_VS, 0x1, 0x10 }, // 7464 |
| 14755 | { PseudoVREDOR_VS_M2_E32, VREDOR_VS, 0x1, 0x20 }, // 7465 |
| 14756 | { PseudoVREDOR_VS_M2_E32_MASK, VREDOR_VS, 0x1, 0x20 }, // 7466 |
| 14757 | { PseudoVREDOR_VS_M2_E64, VREDOR_VS, 0x1, 0x40 }, // 7467 |
| 14758 | { PseudoVREDOR_VS_M2_E64_MASK, VREDOR_VS, 0x1, 0x40 }, // 7468 |
| 14759 | { PseudoVREDOR_VS_M4_E8, VREDOR_VS, 0x2, 0x8 }, // 7469 |
| 14760 | { PseudoVREDOR_VS_M4_E8_MASK, VREDOR_VS, 0x2, 0x8 }, // 7470 |
| 14761 | { PseudoVREDOR_VS_M4_E16, VREDOR_VS, 0x2, 0x10 }, // 7471 |
| 14762 | { PseudoVREDOR_VS_M4_E16_MASK, VREDOR_VS, 0x2, 0x10 }, // 7472 |
| 14763 | { PseudoVREDOR_VS_M4_E32, VREDOR_VS, 0x2, 0x20 }, // 7473 |
| 14764 | { PseudoVREDOR_VS_M4_E32_MASK, VREDOR_VS, 0x2, 0x20 }, // 7474 |
| 14765 | { PseudoVREDOR_VS_M4_E64, VREDOR_VS, 0x2, 0x40 }, // 7475 |
| 14766 | { PseudoVREDOR_VS_M4_E64_MASK, VREDOR_VS, 0x2, 0x40 }, // 7476 |
| 14767 | { PseudoVREDOR_VS_M8_E8, VREDOR_VS, 0x3, 0x8 }, // 7477 |
| 14768 | { PseudoVREDOR_VS_M8_E8_MASK, VREDOR_VS, 0x3, 0x8 }, // 7478 |
| 14769 | { PseudoVREDOR_VS_M8_E16, VREDOR_VS, 0x3, 0x10 }, // 7479 |
| 14770 | { PseudoVREDOR_VS_M8_E16_MASK, VREDOR_VS, 0x3, 0x10 }, // 7480 |
| 14771 | { PseudoVREDOR_VS_M8_E32, VREDOR_VS, 0x3, 0x20 }, // 7481 |
| 14772 | { PseudoVREDOR_VS_M8_E32_MASK, VREDOR_VS, 0x3, 0x20 }, // 7482 |
| 14773 | { PseudoVREDOR_VS_M8_E64, VREDOR_VS, 0x3, 0x40 }, // 7483 |
| 14774 | { PseudoVREDOR_VS_M8_E64_MASK, VREDOR_VS, 0x3, 0x40 }, // 7484 |
| 14775 | { PseudoVREDOR_VS_MF8_E8, VREDOR_VS, 0x5, 0x8 }, // 7485 |
| 14776 | { PseudoVREDOR_VS_MF8_E8_MASK, VREDOR_VS, 0x5, 0x8 }, // 7486 |
| 14777 | { PseudoVREDOR_VS_MF4_E8, VREDOR_VS, 0x6, 0x8 }, // 7487 |
| 14778 | { PseudoVREDOR_VS_MF4_E8_MASK, VREDOR_VS, 0x6, 0x8 }, // 7488 |
| 14779 | { PseudoVREDOR_VS_MF4_E16, VREDOR_VS, 0x6, 0x10 }, // 7489 |
| 14780 | { PseudoVREDOR_VS_MF4_E16_MASK, VREDOR_VS, 0x6, 0x10 }, // 7490 |
| 14781 | { PseudoVREDOR_VS_MF2_E8, VREDOR_VS, 0x7, 0x8 }, // 7491 |
| 14782 | { PseudoVREDOR_VS_MF2_E8_MASK, VREDOR_VS, 0x7, 0x8 }, // 7492 |
| 14783 | { PseudoVREDOR_VS_MF2_E16, VREDOR_VS, 0x7, 0x10 }, // 7493 |
| 14784 | { PseudoVREDOR_VS_MF2_E16_MASK, VREDOR_VS, 0x7, 0x10 }, // 7494 |
| 14785 | { PseudoVREDOR_VS_MF2_E32, VREDOR_VS, 0x7, 0x20 }, // 7495 |
| 14786 | { PseudoVREDOR_VS_MF2_E32_MASK, VREDOR_VS, 0x7, 0x20 }, // 7496 |
| 14787 | { PseudoVREDSUM_VS_M1_E8, VREDSUM_VS, 0x0, 0x8 }, // 7497 |
| 14788 | { PseudoVREDSUM_VS_M1_E8_MASK, VREDSUM_VS, 0x0, 0x8 }, // 7498 |
| 14789 | { PseudoVREDSUM_VS_M1_E16, VREDSUM_VS, 0x0, 0x10 }, // 7499 |
| 14790 | { PseudoVREDSUM_VS_M1_E16_MASK, VREDSUM_VS, 0x0, 0x10 }, // 7500 |
| 14791 | { PseudoVREDSUM_VS_M1_E32, VREDSUM_VS, 0x0, 0x20 }, // 7501 |
| 14792 | { PseudoVREDSUM_VS_M1_E32_MASK, VREDSUM_VS, 0x0, 0x20 }, // 7502 |
| 14793 | { PseudoVREDSUM_VS_M1_E64, VREDSUM_VS, 0x0, 0x40 }, // 7503 |
| 14794 | { PseudoVREDSUM_VS_M1_E64_MASK, VREDSUM_VS, 0x0, 0x40 }, // 7504 |
| 14795 | { PseudoVREDSUM_VS_M2_E8, VREDSUM_VS, 0x1, 0x8 }, // 7505 |
| 14796 | { PseudoVREDSUM_VS_M2_E8_MASK, VREDSUM_VS, 0x1, 0x8 }, // 7506 |
| 14797 | { PseudoVREDSUM_VS_M2_E16, VREDSUM_VS, 0x1, 0x10 }, // 7507 |
| 14798 | { PseudoVREDSUM_VS_M2_E16_MASK, VREDSUM_VS, 0x1, 0x10 }, // 7508 |
| 14799 | { PseudoVREDSUM_VS_M2_E32, VREDSUM_VS, 0x1, 0x20 }, // 7509 |
| 14800 | { PseudoVREDSUM_VS_M2_E32_MASK, VREDSUM_VS, 0x1, 0x20 }, // 7510 |
| 14801 | { PseudoVREDSUM_VS_M2_E64, VREDSUM_VS, 0x1, 0x40 }, // 7511 |
| 14802 | { PseudoVREDSUM_VS_M2_E64_MASK, VREDSUM_VS, 0x1, 0x40 }, // 7512 |
| 14803 | { PseudoVREDSUM_VS_M4_E8, VREDSUM_VS, 0x2, 0x8 }, // 7513 |
| 14804 | { PseudoVREDSUM_VS_M4_E8_MASK, VREDSUM_VS, 0x2, 0x8 }, // 7514 |
| 14805 | { PseudoVREDSUM_VS_M4_E16, VREDSUM_VS, 0x2, 0x10 }, // 7515 |
| 14806 | { PseudoVREDSUM_VS_M4_E16_MASK, VREDSUM_VS, 0x2, 0x10 }, // 7516 |
| 14807 | { PseudoVREDSUM_VS_M4_E32, VREDSUM_VS, 0x2, 0x20 }, // 7517 |
| 14808 | { PseudoVREDSUM_VS_M4_E32_MASK, VREDSUM_VS, 0x2, 0x20 }, // 7518 |
| 14809 | { PseudoVREDSUM_VS_M4_E64, VREDSUM_VS, 0x2, 0x40 }, // 7519 |
| 14810 | { PseudoVREDSUM_VS_M4_E64_MASK, VREDSUM_VS, 0x2, 0x40 }, // 7520 |
| 14811 | { PseudoVREDSUM_VS_M8_E8, VREDSUM_VS, 0x3, 0x8 }, // 7521 |
| 14812 | { PseudoVREDSUM_VS_M8_E8_MASK, VREDSUM_VS, 0x3, 0x8 }, // 7522 |
| 14813 | { PseudoVREDSUM_VS_M8_E16, VREDSUM_VS, 0x3, 0x10 }, // 7523 |
| 14814 | { PseudoVREDSUM_VS_M8_E16_MASK, VREDSUM_VS, 0x3, 0x10 }, // 7524 |
| 14815 | { PseudoVREDSUM_VS_M8_E32, VREDSUM_VS, 0x3, 0x20 }, // 7525 |
| 14816 | { PseudoVREDSUM_VS_M8_E32_MASK, VREDSUM_VS, 0x3, 0x20 }, // 7526 |
| 14817 | { PseudoVREDSUM_VS_M8_E64, VREDSUM_VS, 0x3, 0x40 }, // 7527 |
| 14818 | { PseudoVREDSUM_VS_M8_E64_MASK, VREDSUM_VS, 0x3, 0x40 }, // 7528 |
| 14819 | { PseudoVREDSUM_VS_MF8_E8, VREDSUM_VS, 0x5, 0x8 }, // 7529 |
| 14820 | { PseudoVREDSUM_VS_MF8_E8_MASK, VREDSUM_VS, 0x5, 0x8 }, // 7530 |
| 14821 | { PseudoVREDSUM_VS_MF4_E8, VREDSUM_VS, 0x6, 0x8 }, // 7531 |
| 14822 | { PseudoVREDSUM_VS_MF4_E8_MASK, VREDSUM_VS, 0x6, 0x8 }, // 7532 |
| 14823 | { PseudoVREDSUM_VS_MF4_E16, VREDSUM_VS, 0x6, 0x10 }, // 7533 |
| 14824 | { PseudoVREDSUM_VS_MF4_E16_MASK, VREDSUM_VS, 0x6, 0x10 }, // 7534 |
| 14825 | { PseudoVREDSUM_VS_MF2_E8, VREDSUM_VS, 0x7, 0x8 }, // 7535 |
| 14826 | { PseudoVREDSUM_VS_MF2_E8_MASK, VREDSUM_VS, 0x7, 0x8 }, // 7536 |
| 14827 | { PseudoVREDSUM_VS_MF2_E16, VREDSUM_VS, 0x7, 0x10 }, // 7537 |
| 14828 | { PseudoVREDSUM_VS_MF2_E16_MASK, VREDSUM_VS, 0x7, 0x10 }, // 7538 |
| 14829 | { PseudoVREDSUM_VS_MF2_E32, VREDSUM_VS, 0x7, 0x20 }, // 7539 |
| 14830 | { PseudoVREDSUM_VS_MF2_E32_MASK, VREDSUM_VS, 0x7, 0x20 }, // 7540 |
| 14831 | { PseudoVREDXOR_VS_M1_E8, VREDXOR_VS, 0x0, 0x8 }, // 7541 |
| 14832 | { PseudoVREDXOR_VS_M1_E8_MASK, VREDXOR_VS, 0x0, 0x8 }, // 7542 |
| 14833 | { PseudoVREDXOR_VS_M1_E16, VREDXOR_VS, 0x0, 0x10 }, // 7543 |
| 14834 | { PseudoVREDXOR_VS_M1_E16_MASK, VREDXOR_VS, 0x0, 0x10 }, // 7544 |
| 14835 | { PseudoVREDXOR_VS_M1_E32, VREDXOR_VS, 0x0, 0x20 }, // 7545 |
| 14836 | { PseudoVREDXOR_VS_M1_E32_MASK, VREDXOR_VS, 0x0, 0x20 }, // 7546 |
| 14837 | { PseudoVREDXOR_VS_M1_E64, VREDXOR_VS, 0x0, 0x40 }, // 7547 |
| 14838 | { PseudoVREDXOR_VS_M1_E64_MASK, VREDXOR_VS, 0x0, 0x40 }, // 7548 |
| 14839 | { PseudoVREDXOR_VS_M2_E8, VREDXOR_VS, 0x1, 0x8 }, // 7549 |
| 14840 | { PseudoVREDXOR_VS_M2_E8_MASK, VREDXOR_VS, 0x1, 0x8 }, // 7550 |
| 14841 | { PseudoVREDXOR_VS_M2_E16, VREDXOR_VS, 0x1, 0x10 }, // 7551 |
| 14842 | { PseudoVREDXOR_VS_M2_E16_MASK, VREDXOR_VS, 0x1, 0x10 }, // 7552 |
| 14843 | { PseudoVREDXOR_VS_M2_E32, VREDXOR_VS, 0x1, 0x20 }, // 7553 |
| 14844 | { PseudoVREDXOR_VS_M2_E32_MASK, VREDXOR_VS, 0x1, 0x20 }, // 7554 |
| 14845 | { PseudoVREDXOR_VS_M2_E64, VREDXOR_VS, 0x1, 0x40 }, // 7555 |
| 14846 | { PseudoVREDXOR_VS_M2_E64_MASK, VREDXOR_VS, 0x1, 0x40 }, // 7556 |
| 14847 | { PseudoVREDXOR_VS_M4_E8, VREDXOR_VS, 0x2, 0x8 }, // 7557 |
| 14848 | { PseudoVREDXOR_VS_M4_E8_MASK, VREDXOR_VS, 0x2, 0x8 }, // 7558 |
| 14849 | { PseudoVREDXOR_VS_M4_E16, VREDXOR_VS, 0x2, 0x10 }, // 7559 |
| 14850 | { PseudoVREDXOR_VS_M4_E16_MASK, VREDXOR_VS, 0x2, 0x10 }, // 7560 |
| 14851 | { PseudoVREDXOR_VS_M4_E32, VREDXOR_VS, 0x2, 0x20 }, // 7561 |
| 14852 | { PseudoVREDXOR_VS_M4_E32_MASK, VREDXOR_VS, 0x2, 0x20 }, // 7562 |
| 14853 | { PseudoVREDXOR_VS_M4_E64, VREDXOR_VS, 0x2, 0x40 }, // 7563 |
| 14854 | { PseudoVREDXOR_VS_M4_E64_MASK, VREDXOR_VS, 0x2, 0x40 }, // 7564 |
| 14855 | { PseudoVREDXOR_VS_M8_E8, VREDXOR_VS, 0x3, 0x8 }, // 7565 |
| 14856 | { PseudoVREDXOR_VS_M8_E8_MASK, VREDXOR_VS, 0x3, 0x8 }, // 7566 |
| 14857 | { PseudoVREDXOR_VS_M8_E16, VREDXOR_VS, 0x3, 0x10 }, // 7567 |
| 14858 | { PseudoVREDXOR_VS_M8_E16_MASK, VREDXOR_VS, 0x3, 0x10 }, // 7568 |
| 14859 | { PseudoVREDXOR_VS_M8_E32, VREDXOR_VS, 0x3, 0x20 }, // 7569 |
| 14860 | { PseudoVREDXOR_VS_M8_E32_MASK, VREDXOR_VS, 0x3, 0x20 }, // 7570 |
| 14861 | { PseudoVREDXOR_VS_M8_E64, VREDXOR_VS, 0x3, 0x40 }, // 7571 |
| 14862 | { PseudoVREDXOR_VS_M8_E64_MASK, VREDXOR_VS, 0x3, 0x40 }, // 7572 |
| 14863 | { PseudoVREDXOR_VS_MF8_E8, VREDXOR_VS, 0x5, 0x8 }, // 7573 |
| 14864 | { PseudoVREDXOR_VS_MF8_E8_MASK, VREDXOR_VS, 0x5, 0x8 }, // 7574 |
| 14865 | { PseudoVREDXOR_VS_MF4_E8, VREDXOR_VS, 0x6, 0x8 }, // 7575 |
| 14866 | { PseudoVREDXOR_VS_MF4_E8_MASK, VREDXOR_VS, 0x6, 0x8 }, // 7576 |
| 14867 | { PseudoVREDXOR_VS_MF4_E16, VREDXOR_VS, 0x6, 0x10 }, // 7577 |
| 14868 | { PseudoVREDXOR_VS_MF4_E16_MASK, VREDXOR_VS, 0x6, 0x10 }, // 7578 |
| 14869 | { PseudoVREDXOR_VS_MF2_E8, VREDXOR_VS, 0x7, 0x8 }, // 7579 |
| 14870 | { PseudoVREDXOR_VS_MF2_E8_MASK, VREDXOR_VS, 0x7, 0x8 }, // 7580 |
| 14871 | { PseudoVREDXOR_VS_MF2_E16, VREDXOR_VS, 0x7, 0x10 }, // 7581 |
| 14872 | { PseudoVREDXOR_VS_MF2_E16_MASK, VREDXOR_VS, 0x7, 0x10 }, // 7582 |
| 14873 | { PseudoVREDXOR_VS_MF2_E32, VREDXOR_VS, 0x7, 0x20 }, // 7583 |
| 14874 | { PseudoVREDXOR_VS_MF2_E32_MASK, VREDXOR_VS, 0x7, 0x20 }, // 7584 |
| 14875 | { PseudoVREMU_VV_M1_E8, VREMU_VV, 0x0, 0x8 }, // 7585 |
| 14876 | { PseudoVREMU_VV_M1_E8_MASK, VREMU_VV, 0x0, 0x8 }, // 7586 |
| 14877 | { PseudoVREMU_VV_M1_E16, VREMU_VV, 0x0, 0x10 }, // 7587 |
| 14878 | { PseudoVREMU_VV_M1_E16_MASK, VREMU_VV, 0x0, 0x10 }, // 7588 |
| 14879 | { PseudoVREMU_VV_M1_E32, VREMU_VV, 0x0, 0x20 }, // 7589 |
| 14880 | { PseudoVREMU_VV_M1_E32_MASK, VREMU_VV, 0x0, 0x20 }, // 7590 |
| 14881 | { PseudoVREMU_VV_M1_E64, VREMU_VV, 0x0, 0x40 }, // 7591 |
| 14882 | { PseudoVREMU_VV_M1_E64_MASK, VREMU_VV, 0x0, 0x40 }, // 7592 |
| 14883 | { PseudoVREMU_VV_M2_E8, VREMU_VV, 0x1, 0x8 }, // 7593 |
| 14884 | { PseudoVREMU_VV_M2_E8_MASK, VREMU_VV, 0x1, 0x8 }, // 7594 |
| 14885 | { PseudoVREMU_VV_M2_E16, VREMU_VV, 0x1, 0x10 }, // 7595 |
| 14886 | { PseudoVREMU_VV_M2_E16_MASK, VREMU_VV, 0x1, 0x10 }, // 7596 |
| 14887 | { PseudoVREMU_VV_M2_E32, VREMU_VV, 0x1, 0x20 }, // 7597 |
| 14888 | { PseudoVREMU_VV_M2_E32_MASK, VREMU_VV, 0x1, 0x20 }, // 7598 |
| 14889 | { PseudoVREMU_VV_M2_E64, VREMU_VV, 0x1, 0x40 }, // 7599 |
| 14890 | { PseudoVREMU_VV_M2_E64_MASK, VREMU_VV, 0x1, 0x40 }, // 7600 |
| 14891 | { PseudoVREMU_VV_M4_E8, VREMU_VV, 0x2, 0x8 }, // 7601 |
| 14892 | { PseudoVREMU_VV_M4_E8_MASK, VREMU_VV, 0x2, 0x8 }, // 7602 |
| 14893 | { PseudoVREMU_VV_M4_E16, VREMU_VV, 0x2, 0x10 }, // 7603 |
| 14894 | { PseudoVREMU_VV_M4_E16_MASK, VREMU_VV, 0x2, 0x10 }, // 7604 |
| 14895 | { PseudoVREMU_VV_M4_E32, VREMU_VV, 0x2, 0x20 }, // 7605 |
| 14896 | { PseudoVREMU_VV_M4_E32_MASK, VREMU_VV, 0x2, 0x20 }, // 7606 |
| 14897 | { PseudoVREMU_VV_M4_E64, VREMU_VV, 0x2, 0x40 }, // 7607 |
| 14898 | { PseudoVREMU_VV_M4_E64_MASK, VREMU_VV, 0x2, 0x40 }, // 7608 |
| 14899 | { PseudoVREMU_VV_M8_E8, VREMU_VV, 0x3, 0x8 }, // 7609 |
| 14900 | { PseudoVREMU_VV_M8_E8_MASK, VREMU_VV, 0x3, 0x8 }, // 7610 |
| 14901 | { PseudoVREMU_VV_M8_E16, VREMU_VV, 0x3, 0x10 }, // 7611 |
| 14902 | { PseudoVREMU_VV_M8_E16_MASK, VREMU_VV, 0x3, 0x10 }, // 7612 |
| 14903 | { PseudoVREMU_VV_M8_E32, VREMU_VV, 0x3, 0x20 }, // 7613 |
| 14904 | { PseudoVREMU_VV_M8_E32_MASK, VREMU_VV, 0x3, 0x20 }, // 7614 |
| 14905 | { PseudoVREMU_VV_M8_E64, VREMU_VV, 0x3, 0x40 }, // 7615 |
| 14906 | { PseudoVREMU_VV_M8_E64_MASK, VREMU_VV, 0x3, 0x40 }, // 7616 |
| 14907 | { PseudoVREMU_VV_MF8_E8, VREMU_VV, 0x5, 0x8 }, // 7617 |
| 14908 | { PseudoVREMU_VV_MF8_E8_MASK, VREMU_VV, 0x5, 0x8 }, // 7618 |
| 14909 | { PseudoVREMU_VV_MF4_E8, VREMU_VV, 0x6, 0x8 }, // 7619 |
| 14910 | { PseudoVREMU_VV_MF4_E8_MASK, VREMU_VV, 0x6, 0x8 }, // 7620 |
| 14911 | { PseudoVREMU_VV_MF4_E16, VREMU_VV, 0x6, 0x10 }, // 7621 |
| 14912 | { PseudoVREMU_VV_MF4_E16_MASK, VREMU_VV, 0x6, 0x10 }, // 7622 |
| 14913 | { PseudoVREMU_VV_MF2_E8, VREMU_VV, 0x7, 0x8 }, // 7623 |
| 14914 | { PseudoVREMU_VV_MF2_E8_MASK, VREMU_VV, 0x7, 0x8 }, // 7624 |
| 14915 | { PseudoVREMU_VV_MF2_E16, VREMU_VV, 0x7, 0x10 }, // 7625 |
| 14916 | { PseudoVREMU_VV_MF2_E16_MASK, VREMU_VV, 0x7, 0x10 }, // 7626 |
| 14917 | { PseudoVREMU_VV_MF2_E32, VREMU_VV, 0x7, 0x20 }, // 7627 |
| 14918 | { PseudoVREMU_VV_MF2_E32_MASK, VREMU_VV, 0x7, 0x20 }, // 7628 |
| 14919 | { PseudoVREMU_VX_M1_E8, VREMU_VX, 0x0, 0x8 }, // 7629 |
| 14920 | { PseudoVREMU_VX_M1_E8_MASK, VREMU_VX, 0x0, 0x8 }, // 7630 |
| 14921 | { PseudoVREMU_VX_M1_E16, VREMU_VX, 0x0, 0x10 }, // 7631 |
| 14922 | { PseudoVREMU_VX_M1_E16_MASK, VREMU_VX, 0x0, 0x10 }, // 7632 |
| 14923 | { PseudoVREMU_VX_M1_E32, VREMU_VX, 0x0, 0x20 }, // 7633 |
| 14924 | { PseudoVREMU_VX_M1_E32_MASK, VREMU_VX, 0x0, 0x20 }, // 7634 |
| 14925 | { PseudoVREMU_VX_M1_E64, VREMU_VX, 0x0, 0x40 }, // 7635 |
| 14926 | { PseudoVREMU_VX_M1_E64_MASK, VREMU_VX, 0x0, 0x40 }, // 7636 |
| 14927 | { PseudoVREMU_VX_M2_E8, VREMU_VX, 0x1, 0x8 }, // 7637 |
| 14928 | { PseudoVREMU_VX_M2_E8_MASK, VREMU_VX, 0x1, 0x8 }, // 7638 |
| 14929 | { PseudoVREMU_VX_M2_E16, VREMU_VX, 0x1, 0x10 }, // 7639 |
| 14930 | { PseudoVREMU_VX_M2_E16_MASK, VREMU_VX, 0x1, 0x10 }, // 7640 |
| 14931 | { PseudoVREMU_VX_M2_E32, VREMU_VX, 0x1, 0x20 }, // 7641 |
| 14932 | { PseudoVREMU_VX_M2_E32_MASK, VREMU_VX, 0x1, 0x20 }, // 7642 |
| 14933 | { PseudoVREMU_VX_M2_E64, VREMU_VX, 0x1, 0x40 }, // 7643 |
| 14934 | { PseudoVREMU_VX_M2_E64_MASK, VREMU_VX, 0x1, 0x40 }, // 7644 |
| 14935 | { PseudoVREMU_VX_M4_E8, VREMU_VX, 0x2, 0x8 }, // 7645 |
| 14936 | { PseudoVREMU_VX_M4_E8_MASK, VREMU_VX, 0x2, 0x8 }, // 7646 |
| 14937 | { PseudoVREMU_VX_M4_E16, VREMU_VX, 0x2, 0x10 }, // 7647 |
| 14938 | { PseudoVREMU_VX_M4_E16_MASK, VREMU_VX, 0x2, 0x10 }, // 7648 |
| 14939 | { PseudoVREMU_VX_M4_E32, VREMU_VX, 0x2, 0x20 }, // 7649 |
| 14940 | { PseudoVREMU_VX_M4_E32_MASK, VREMU_VX, 0x2, 0x20 }, // 7650 |
| 14941 | { PseudoVREMU_VX_M4_E64, VREMU_VX, 0x2, 0x40 }, // 7651 |
| 14942 | { PseudoVREMU_VX_M4_E64_MASK, VREMU_VX, 0x2, 0x40 }, // 7652 |
| 14943 | { PseudoVREMU_VX_M8_E8, VREMU_VX, 0x3, 0x8 }, // 7653 |
| 14944 | { PseudoVREMU_VX_M8_E8_MASK, VREMU_VX, 0x3, 0x8 }, // 7654 |
| 14945 | { PseudoVREMU_VX_M8_E16, VREMU_VX, 0x3, 0x10 }, // 7655 |
| 14946 | { PseudoVREMU_VX_M8_E16_MASK, VREMU_VX, 0x3, 0x10 }, // 7656 |
| 14947 | { PseudoVREMU_VX_M8_E32, VREMU_VX, 0x3, 0x20 }, // 7657 |
| 14948 | { PseudoVREMU_VX_M8_E32_MASK, VREMU_VX, 0x3, 0x20 }, // 7658 |
| 14949 | { PseudoVREMU_VX_M8_E64, VREMU_VX, 0x3, 0x40 }, // 7659 |
| 14950 | { PseudoVREMU_VX_M8_E64_MASK, VREMU_VX, 0x3, 0x40 }, // 7660 |
| 14951 | { PseudoVREMU_VX_MF8_E8, VREMU_VX, 0x5, 0x8 }, // 7661 |
| 14952 | { PseudoVREMU_VX_MF8_E8_MASK, VREMU_VX, 0x5, 0x8 }, // 7662 |
| 14953 | { PseudoVREMU_VX_MF4_E8, VREMU_VX, 0x6, 0x8 }, // 7663 |
| 14954 | { PseudoVREMU_VX_MF4_E8_MASK, VREMU_VX, 0x6, 0x8 }, // 7664 |
| 14955 | { PseudoVREMU_VX_MF4_E16, VREMU_VX, 0x6, 0x10 }, // 7665 |
| 14956 | { PseudoVREMU_VX_MF4_E16_MASK, VREMU_VX, 0x6, 0x10 }, // 7666 |
| 14957 | { PseudoVREMU_VX_MF2_E8, VREMU_VX, 0x7, 0x8 }, // 7667 |
| 14958 | { PseudoVREMU_VX_MF2_E8_MASK, VREMU_VX, 0x7, 0x8 }, // 7668 |
| 14959 | { PseudoVREMU_VX_MF2_E16, VREMU_VX, 0x7, 0x10 }, // 7669 |
| 14960 | { PseudoVREMU_VX_MF2_E16_MASK, VREMU_VX, 0x7, 0x10 }, // 7670 |
| 14961 | { PseudoVREMU_VX_MF2_E32, VREMU_VX, 0x7, 0x20 }, // 7671 |
| 14962 | { PseudoVREMU_VX_MF2_E32_MASK, VREMU_VX, 0x7, 0x20 }, // 7672 |
| 14963 | { PseudoVREM_VV_M1_E8, VREM_VV, 0x0, 0x8 }, // 7673 |
| 14964 | { PseudoVREM_VV_M1_E8_MASK, VREM_VV, 0x0, 0x8 }, // 7674 |
| 14965 | { PseudoVREM_VV_M1_E16, VREM_VV, 0x0, 0x10 }, // 7675 |
| 14966 | { PseudoVREM_VV_M1_E16_MASK, VREM_VV, 0x0, 0x10 }, // 7676 |
| 14967 | { PseudoVREM_VV_M1_E32, VREM_VV, 0x0, 0x20 }, // 7677 |
| 14968 | { PseudoVREM_VV_M1_E32_MASK, VREM_VV, 0x0, 0x20 }, // 7678 |
| 14969 | { PseudoVREM_VV_M1_E64, VREM_VV, 0x0, 0x40 }, // 7679 |
| 14970 | { PseudoVREM_VV_M1_E64_MASK, VREM_VV, 0x0, 0x40 }, // 7680 |
| 14971 | { PseudoVREM_VV_M2_E8, VREM_VV, 0x1, 0x8 }, // 7681 |
| 14972 | { PseudoVREM_VV_M2_E8_MASK, VREM_VV, 0x1, 0x8 }, // 7682 |
| 14973 | { PseudoVREM_VV_M2_E16, VREM_VV, 0x1, 0x10 }, // 7683 |
| 14974 | { PseudoVREM_VV_M2_E16_MASK, VREM_VV, 0x1, 0x10 }, // 7684 |
| 14975 | { PseudoVREM_VV_M2_E32, VREM_VV, 0x1, 0x20 }, // 7685 |
| 14976 | { PseudoVREM_VV_M2_E32_MASK, VREM_VV, 0x1, 0x20 }, // 7686 |
| 14977 | { PseudoVREM_VV_M2_E64, VREM_VV, 0x1, 0x40 }, // 7687 |
| 14978 | { PseudoVREM_VV_M2_E64_MASK, VREM_VV, 0x1, 0x40 }, // 7688 |
| 14979 | { PseudoVREM_VV_M4_E8, VREM_VV, 0x2, 0x8 }, // 7689 |
| 14980 | { PseudoVREM_VV_M4_E8_MASK, VREM_VV, 0x2, 0x8 }, // 7690 |
| 14981 | { PseudoVREM_VV_M4_E16, VREM_VV, 0x2, 0x10 }, // 7691 |
| 14982 | { PseudoVREM_VV_M4_E16_MASK, VREM_VV, 0x2, 0x10 }, // 7692 |
| 14983 | { PseudoVREM_VV_M4_E32, VREM_VV, 0x2, 0x20 }, // 7693 |
| 14984 | { PseudoVREM_VV_M4_E32_MASK, VREM_VV, 0x2, 0x20 }, // 7694 |
| 14985 | { PseudoVREM_VV_M4_E64, VREM_VV, 0x2, 0x40 }, // 7695 |
| 14986 | { PseudoVREM_VV_M4_E64_MASK, VREM_VV, 0x2, 0x40 }, // 7696 |
| 14987 | { PseudoVREM_VV_M8_E8, VREM_VV, 0x3, 0x8 }, // 7697 |
| 14988 | { PseudoVREM_VV_M8_E8_MASK, VREM_VV, 0x3, 0x8 }, // 7698 |
| 14989 | { PseudoVREM_VV_M8_E16, VREM_VV, 0x3, 0x10 }, // 7699 |
| 14990 | { PseudoVREM_VV_M8_E16_MASK, VREM_VV, 0x3, 0x10 }, // 7700 |
| 14991 | { PseudoVREM_VV_M8_E32, VREM_VV, 0x3, 0x20 }, // 7701 |
| 14992 | { PseudoVREM_VV_M8_E32_MASK, VREM_VV, 0x3, 0x20 }, // 7702 |
| 14993 | { PseudoVREM_VV_M8_E64, VREM_VV, 0x3, 0x40 }, // 7703 |
| 14994 | { PseudoVREM_VV_M8_E64_MASK, VREM_VV, 0x3, 0x40 }, // 7704 |
| 14995 | { PseudoVREM_VV_MF8_E8, VREM_VV, 0x5, 0x8 }, // 7705 |
| 14996 | { PseudoVREM_VV_MF8_E8_MASK, VREM_VV, 0x5, 0x8 }, // 7706 |
| 14997 | { PseudoVREM_VV_MF4_E8, VREM_VV, 0x6, 0x8 }, // 7707 |
| 14998 | { PseudoVREM_VV_MF4_E8_MASK, VREM_VV, 0x6, 0x8 }, // 7708 |
| 14999 | { PseudoVREM_VV_MF4_E16, VREM_VV, 0x6, 0x10 }, // 7709 |
| 15000 | { PseudoVREM_VV_MF4_E16_MASK, VREM_VV, 0x6, 0x10 }, // 7710 |
| 15001 | { PseudoVREM_VV_MF2_E8, VREM_VV, 0x7, 0x8 }, // 7711 |
| 15002 | { PseudoVREM_VV_MF2_E8_MASK, VREM_VV, 0x7, 0x8 }, // 7712 |
| 15003 | { PseudoVREM_VV_MF2_E16, VREM_VV, 0x7, 0x10 }, // 7713 |
| 15004 | { PseudoVREM_VV_MF2_E16_MASK, VREM_VV, 0x7, 0x10 }, // 7714 |
| 15005 | { PseudoVREM_VV_MF2_E32, VREM_VV, 0x7, 0x20 }, // 7715 |
| 15006 | { PseudoVREM_VV_MF2_E32_MASK, VREM_VV, 0x7, 0x20 }, // 7716 |
| 15007 | { PseudoVREM_VX_M1_E8, VREM_VX, 0x0, 0x8 }, // 7717 |
| 15008 | { PseudoVREM_VX_M1_E8_MASK, VREM_VX, 0x0, 0x8 }, // 7718 |
| 15009 | { PseudoVREM_VX_M1_E16, VREM_VX, 0x0, 0x10 }, // 7719 |
| 15010 | { PseudoVREM_VX_M1_E16_MASK, VREM_VX, 0x0, 0x10 }, // 7720 |
| 15011 | { PseudoVREM_VX_M1_E32, VREM_VX, 0x0, 0x20 }, // 7721 |
| 15012 | { PseudoVREM_VX_M1_E32_MASK, VREM_VX, 0x0, 0x20 }, // 7722 |
| 15013 | { PseudoVREM_VX_M1_E64, VREM_VX, 0x0, 0x40 }, // 7723 |
| 15014 | { PseudoVREM_VX_M1_E64_MASK, VREM_VX, 0x0, 0x40 }, // 7724 |
| 15015 | { PseudoVREM_VX_M2_E8, VREM_VX, 0x1, 0x8 }, // 7725 |
| 15016 | { PseudoVREM_VX_M2_E8_MASK, VREM_VX, 0x1, 0x8 }, // 7726 |
| 15017 | { PseudoVREM_VX_M2_E16, VREM_VX, 0x1, 0x10 }, // 7727 |
| 15018 | { PseudoVREM_VX_M2_E16_MASK, VREM_VX, 0x1, 0x10 }, // 7728 |
| 15019 | { PseudoVREM_VX_M2_E32, VREM_VX, 0x1, 0x20 }, // 7729 |
| 15020 | { PseudoVREM_VX_M2_E32_MASK, VREM_VX, 0x1, 0x20 }, // 7730 |
| 15021 | { PseudoVREM_VX_M2_E64, VREM_VX, 0x1, 0x40 }, // 7731 |
| 15022 | { PseudoVREM_VX_M2_E64_MASK, VREM_VX, 0x1, 0x40 }, // 7732 |
| 15023 | { PseudoVREM_VX_M4_E8, VREM_VX, 0x2, 0x8 }, // 7733 |
| 15024 | { PseudoVREM_VX_M4_E8_MASK, VREM_VX, 0x2, 0x8 }, // 7734 |
| 15025 | { PseudoVREM_VX_M4_E16, VREM_VX, 0x2, 0x10 }, // 7735 |
| 15026 | { PseudoVREM_VX_M4_E16_MASK, VREM_VX, 0x2, 0x10 }, // 7736 |
| 15027 | { PseudoVREM_VX_M4_E32, VREM_VX, 0x2, 0x20 }, // 7737 |
| 15028 | { PseudoVREM_VX_M4_E32_MASK, VREM_VX, 0x2, 0x20 }, // 7738 |
| 15029 | { PseudoVREM_VX_M4_E64, VREM_VX, 0x2, 0x40 }, // 7739 |
| 15030 | { PseudoVREM_VX_M4_E64_MASK, VREM_VX, 0x2, 0x40 }, // 7740 |
| 15031 | { PseudoVREM_VX_M8_E8, VREM_VX, 0x3, 0x8 }, // 7741 |
| 15032 | { PseudoVREM_VX_M8_E8_MASK, VREM_VX, 0x3, 0x8 }, // 7742 |
| 15033 | { PseudoVREM_VX_M8_E16, VREM_VX, 0x3, 0x10 }, // 7743 |
| 15034 | { PseudoVREM_VX_M8_E16_MASK, VREM_VX, 0x3, 0x10 }, // 7744 |
| 15035 | { PseudoVREM_VX_M8_E32, VREM_VX, 0x3, 0x20 }, // 7745 |
| 15036 | { PseudoVREM_VX_M8_E32_MASK, VREM_VX, 0x3, 0x20 }, // 7746 |
| 15037 | { PseudoVREM_VX_M8_E64, VREM_VX, 0x3, 0x40 }, // 7747 |
| 15038 | { PseudoVREM_VX_M8_E64_MASK, VREM_VX, 0x3, 0x40 }, // 7748 |
| 15039 | { PseudoVREM_VX_MF8_E8, VREM_VX, 0x5, 0x8 }, // 7749 |
| 15040 | { PseudoVREM_VX_MF8_E8_MASK, VREM_VX, 0x5, 0x8 }, // 7750 |
| 15041 | { PseudoVREM_VX_MF4_E8, VREM_VX, 0x6, 0x8 }, // 7751 |
| 15042 | { PseudoVREM_VX_MF4_E8_MASK, VREM_VX, 0x6, 0x8 }, // 7752 |
| 15043 | { PseudoVREM_VX_MF4_E16, VREM_VX, 0x6, 0x10 }, // 7753 |
| 15044 | { PseudoVREM_VX_MF4_E16_MASK, VREM_VX, 0x6, 0x10 }, // 7754 |
| 15045 | { PseudoVREM_VX_MF2_E8, VREM_VX, 0x7, 0x8 }, // 7755 |
| 15046 | { PseudoVREM_VX_MF2_E8_MASK, VREM_VX, 0x7, 0x8 }, // 7756 |
| 15047 | { PseudoVREM_VX_MF2_E16, VREM_VX, 0x7, 0x10 }, // 7757 |
| 15048 | { PseudoVREM_VX_MF2_E16_MASK, VREM_VX, 0x7, 0x10 }, // 7758 |
| 15049 | { PseudoVREM_VX_MF2_E32, VREM_VX, 0x7, 0x20 }, // 7759 |
| 15050 | { PseudoVREM_VX_MF2_E32_MASK, VREM_VX, 0x7, 0x20 }, // 7760 |
| 15051 | { PseudoVREV8_V_M1, VREV8_V, 0x0, 0x0 }, // 7761 |
| 15052 | { PseudoVREV8_V_M1_MASK, VREV8_V, 0x0, 0x0 }, // 7762 |
| 15053 | { PseudoVREV8_V_M2, VREV8_V, 0x1, 0x0 }, // 7763 |
| 15054 | { PseudoVREV8_V_M2_MASK, VREV8_V, 0x1, 0x0 }, // 7764 |
| 15055 | { PseudoVREV8_V_M4, VREV8_V, 0x2, 0x0 }, // 7765 |
| 15056 | { PseudoVREV8_V_M4_MASK, VREV8_V, 0x2, 0x0 }, // 7766 |
| 15057 | { PseudoVREV8_V_M8, VREV8_V, 0x3, 0x0 }, // 7767 |
| 15058 | { PseudoVREV8_V_M8_MASK, VREV8_V, 0x3, 0x0 }, // 7768 |
| 15059 | { PseudoVREV8_V_MF8, VREV8_V, 0x5, 0x0 }, // 7769 |
| 15060 | { PseudoVREV8_V_MF8_MASK, VREV8_V, 0x5, 0x0 }, // 7770 |
| 15061 | { PseudoVREV8_V_MF4, VREV8_V, 0x6, 0x0 }, // 7771 |
| 15062 | { PseudoVREV8_V_MF4_MASK, VREV8_V, 0x6, 0x0 }, // 7772 |
| 15063 | { PseudoVREV8_V_MF2, VREV8_V, 0x7, 0x0 }, // 7773 |
| 15064 | { PseudoVREV8_V_MF2_MASK, VREV8_V, 0x7, 0x0 }, // 7774 |
| 15065 | { PseudoVRGATHEREI16_VV_M1_E8_M1, VRGATHEREI16_VV, 0x0, 0x8 }, // 7775 |
| 15066 | { PseudoVRGATHEREI16_VV_M1_E8_M1_MASK, VRGATHEREI16_VV, 0x0, 0x8 }, // 7776 |
| 15067 | { PseudoVRGATHEREI16_VV_M1_E8_M2, VRGATHEREI16_VV, 0x0, 0x8 }, // 7777 |
| 15068 | { PseudoVRGATHEREI16_VV_M1_E8_M2_MASK, VRGATHEREI16_VV, 0x0, 0x8 }, // 7778 |
| 15069 | { PseudoVRGATHEREI16_VV_M1_E8_MF2, VRGATHEREI16_VV, 0x0, 0x8 }, // 7779 |
| 15070 | { PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK, VRGATHEREI16_VV, 0x0, 0x8 }, // 7780 |
| 15071 | { PseudoVRGATHEREI16_VV_M1_E8_MF4, VRGATHEREI16_VV, 0x0, 0x8 }, // 7781 |
| 15072 | { PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK, VRGATHEREI16_VV, 0x0, 0x8 }, // 7782 |
| 15073 | { PseudoVRGATHEREI16_VV_M1_E16_M1, VRGATHEREI16_VV, 0x0, 0x10 }, // 7783 |
| 15074 | { PseudoVRGATHEREI16_VV_M1_E16_M1_MASK, VRGATHEREI16_VV, 0x0, 0x10 }, // 7784 |
| 15075 | { PseudoVRGATHEREI16_VV_M1_E16_M2, VRGATHEREI16_VV, 0x0, 0x10 }, // 7785 |
| 15076 | { PseudoVRGATHEREI16_VV_M1_E16_M2_MASK, VRGATHEREI16_VV, 0x0, 0x10 }, // 7786 |
| 15077 | { PseudoVRGATHEREI16_VV_M1_E16_MF2, VRGATHEREI16_VV, 0x0, 0x10 }, // 7787 |
| 15078 | { PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK, VRGATHEREI16_VV, 0x0, 0x10 }, // 7788 |
| 15079 | { PseudoVRGATHEREI16_VV_M1_E16_MF4, VRGATHEREI16_VV, 0x0, 0x10 }, // 7789 |
| 15080 | { PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK, VRGATHEREI16_VV, 0x0, 0x10 }, // 7790 |
| 15081 | { PseudoVRGATHEREI16_VV_M1_E32_M1, VRGATHEREI16_VV, 0x0, 0x20 }, // 7791 |
| 15082 | { PseudoVRGATHEREI16_VV_M1_E32_M1_MASK, VRGATHEREI16_VV, 0x0, 0x20 }, // 7792 |
| 15083 | { PseudoVRGATHEREI16_VV_M1_E32_M2, VRGATHEREI16_VV, 0x0, 0x20 }, // 7793 |
| 15084 | { PseudoVRGATHEREI16_VV_M1_E32_M2_MASK, VRGATHEREI16_VV, 0x0, 0x20 }, // 7794 |
| 15085 | { PseudoVRGATHEREI16_VV_M1_E32_MF2, VRGATHEREI16_VV, 0x0, 0x20 }, // 7795 |
| 15086 | { PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK, VRGATHEREI16_VV, 0x0, 0x20 }, // 7796 |
| 15087 | { PseudoVRGATHEREI16_VV_M1_E32_MF4, VRGATHEREI16_VV, 0x0, 0x20 }, // 7797 |
| 15088 | { PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK, VRGATHEREI16_VV, 0x0, 0x20 }, // 7798 |
| 15089 | { PseudoVRGATHEREI16_VV_M1_E64_M1, VRGATHEREI16_VV, 0x0, 0x40 }, // 7799 |
| 15090 | { PseudoVRGATHEREI16_VV_M1_E64_M1_MASK, VRGATHEREI16_VV, 0x0, 0x40 }, // 7800 |
| 15091 | { PseudoVRGATHEREI16_VV_M1_E64_M2, VRGATHEREI16_VV, 0x0, 0x40 }, // 7801 |
| 15092 | { PseudoVRGATHEREI16_VV_M1_E64_M2_MASK, VRGATHEREI16_VV, 0x0, 0x40 }, // 7802 |
| 15093 | { PseudoVRGATHEREI16_VV_M1_E64_MF2, VRGATHEREI16_VV, 0x0, 0x40 }, // 7803 |
| 15094 | { PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK, VRGATHEREI16_VV, 0x0, 0x40 }, // 7804 |
| 15095 | { PseudoVRGATHEREI16_VV_M1_E64_MF4, VRGATHEREI16_VV, 0x0, 0x40 }, // 7805 |
| 15096 | { PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK, VRGATHEREI16_VV, 0x0, 0x40 }, // 7806 |
| 15097 | { PseudoVRGATHEREI16_VV_M2_E8_M1, VRGATHEREI16_VV, 0x1, 0x8 }, // 7807 |
| 15098 | { PseudoVRGATHEREI16_VV_M2_E8_M1_MASK, VRGATHEREI16_VV, 0x1, 0x8 }, // 7808 |
| 15099 | { PseudoVRGATHEREI16_VV_M2_E8_M2, VRGATHEREI16_VV, 0x1, 0x8 }, // 7809 |
| 15100 | { PseudoVRGATHEREI16_VV_M2_E8_M2_MASK, VRGATHEREI16_VV, 0x1, 0x8 }, // 7810 |
| 15101 | { PseudoVRGATHEREI16_VV_M2_E8_M4, VRGATHEREI16_VV, 0x1, 0x8 }, // 7811 |
| 15102 | { PseudoVRGATHEREI16_VV_M2_E8_M4_MASK, VRGATHEREI16_VV, 0x1, 0x8 }, // 7812 |
| 15103 | { PseudoVRGATHEREI16_VV_M2_E8_MF2, VRGATHEREI16_VV, 0x1, 0x8 }, // 7813 |
| 15104 | { PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK, VRGATHEREI16_VV, 0x1, 0x8 }, // 7814 |
| 15105 | { PseudoVRGATHEREI16_VV_M2_E16_M1, VRGATHEREI16_VV, 0x1, 0x10 }, // 7815 |
| 15106 | { PseudoVRGATHEREI16_VV_M2_E16_M1_MASK, VRGATHEREI16_VV, 0x1, 0x10 }, // 7816 |
| 15107 | { PseudoVRGATHEREI16_VV_M2_E16_M2, VRGATHEREI16_VV, 0x1, 0x10 }, // 7817 |
| 15108 | { PseudoVRGATHEREI16_VV_M2_E16_M2_MASK, VRGATHEREI16_VV, 0x1, 0x10 }, // 7818 |
| 15109 | { PseudoVRGATHEREI16_VV_M2_E16_M4, VRGATHEREI16_VV, 0x1, 0x10 }, // 7819 |
| 15110 | { PseudoVRGATHEREI16_VV_M2_E16_M4_MASK, VRGATHEREI16_VV, 0x1, 0x10 }, // 7820 |
| 15111 | { PseudoVRGATHEREI16_VV_M2_E16_MF2, VRGATHEREI16_VV, 0x1, 0x10 }, // 7821 |
| 15112 | { PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK, VRGATHEREI16_VV, 0x1, 0x10 }, // 7822 |
| 15113 | { PseudoVRGATHEREI16_VV_M2_E32_M1, VRGATHEREI16_VV, 0x1, 0x20 }, // 7823 |
| 15114 | { PseudoVRGATHEREI16_VV_M2_E32_M1_MASK, VRGATHEREI16_VV, 0x1, 0x20 }, // 7824 |
| 15115 | { PseudoVRGATHEREI16_VV_M2_E32_M2, VRGATHEREI16_VV, 0x1, 0x20 }, // 7825 |
| 15116 | { PseudoVRGATHEREI16_VV_M2_E32_M2_MASK, VRGATHEREI16_VV, 0x1, 0x20 }, // 7826 |
| 15117 | { PseudoVRGATHEREI16_VV_M2_E32_M4, VRGATHEREI16_VV, 0x1, 0x20 }, // 7827 |
| 15118 | { PseudoVRGATHEREI16_VV_M2_E32_M4_MASK, VRGATHEREI16_VV, 0x1, 0x20 }, // 7828 |
| 15119 | { PseudoVRGATHEREI16_VV_M2_E32_MF2, VRGATHEREI16_VV, 0x1, 0x20 }, // 7829 |
| 15120 | { PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK, VRGATHEREI16_VV, 0x1, 0x20 }, // 7830 |
| 15121 | { PseudoVRGATHEREI16_VV_M2_E64_M1, VRGATHEREI16_VV, 0x1, 0x40 }, // 7831 |
| 15122 | { PseudoVRGATHEREI16_VV_M2_E64_M1_MASK, VRGATHEREI16_VV, 0x1, 0x40 }, // 7832 |
| 15123 | { PseudoVRGATHEREI16_VV_M2_E64_M2, VRGATHEREI16_VV, 0x1, 0x40 }, // 7833 |
| 15124 | { PseudoVRGATHEREI16_VV_M2_E64_M2_MASK, VRGATHEREI16_VV, 0x1, 0x40 }, // 7834 |
| 15125 | { PseudoVRGATHEREI16_VV_M2_E64_M4, VRGATHEREI16_VV, 0x1, 0x40 }, // 7835 |
| 15126 | { PseudoVRGATHEREI16_VV_M2_E64_M4_MASK, VRGATHEREI16_VV, 0x1, 0x40 }, // 7836 |
| 15127 | { PseudoVRGATHEREI16_VV_M2_E64_MF2, VRGATHEREI16_VV, 0x1, 0x40 }, // 7837 |
| 15128 | { PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK, VRGATHEREI16_VV, 0x1, 0x40 }, // 7838 |
| 15129 | { PseudoVRGATHEREI16_VV_M4_E8_M1, VRGATHEREI16_VV, 0x2, 0x8 }, // 7839 |
| 15130 | { PseudoVRGATHEREI16_VV_M4_E8_M1_MASK, VRGATHEREI16_VV, 0x2, 0x8 }, // 7840 |
| 15131 | { PseudoVRGATHEREI16_VV_M4_E8_M2, VRGATHEREI16_VV, 0x2, 0x8 }, // 7841 |
| 15132 | { PseudoVRGATHEREI16_VV_M4_E8_M2_MASK, VRGATHEREI16_VV, 0x2, 0x8 }, // 7842 |
| 15133 | { PseudoVRGATHEREI16_VV_M4_E8_M4, VRGATHEREI16_VV, 0x2, 0x8 }, // 7843 |
| 15134 | { PseudoVRGATHEREI16_VV_M4_E8_M4_MASK, VRGATHEREI16_VV, 0x2, 0x8 }, // 7844 |
| 15135 | { PseudoVRGATHEREI16_VV_M4_E8_M8, VRGATHEREI16_VV, 0x2, 0x8 }, // 7845 |
| 15136 | { PseudoVRGATHEREI16_VV_M4_E8_M8_MASK, VRGATHEREI16_VV, 0x2, 0x8 }, // 7846 |
| 15137 | { PseudoVRGATHEREI16_VV_M4_E16_M1, VRGATHEREI16_VV, 0x2, 0x10 }, // 7847 |
| 15138 | { PseudoVRGATHEREI16_VV_M4_E16_M1_MASK, VRGATHEREI16_VV, 0x2, 0x10 }, // 7848 |
| 15139 | { PseudoVRGATHEREI16_VV_M4_E16_M2, VRGATHEREI16_VV, 0x2, 0x10 }, // 7849 |
| 15140 | { PseudoVRGATHEREI16_VV_M4_E16_M2_MASK, VRGATHEREI16_VV, 0x2, 0x10 }, // 7850 |
| 15141 | { PseudoVRGATHEREI16_VV_M4_E16_M4, VRGATHEREI16_VV, 0x2, 0x10 }, // 7851 |
| 15142 | { PseudoVRGATHEREI16_VV_M4_E16_M4_MASK, VRGATHEREI16_VV, 0x2, 0x10 }, // 7852 |
| 15143 | { PseudoVRGATHEREI16_VV_M4_E16_M8, VRGATHEREI16_VV, 0x2, 0x10 }, // 7853 |
| 15144 | { PseudoVRGATHEREI16_VV_M4_E16_M8_MASK, VRGATHEREI16_VV, 0x2, 0x10 }, // 7854 |
| 15145 | { PseudoVRGATHEREI16_VV_M4_E32_M1, VRGATHEREI16_VV, 0x2, 0x20 }, // 7855 |
| 15146 | { PseudoVRGATHEREI16_VV_M4_E32_M1_MASK, VRGATHEREI16_VV, 0x2, 0x20 }, // 7856 |
| 15147 | { PseudoVRGATHEREI16_VV_M4_E32_M2, VRGATHEREI16_VV, 0x2, 0x20 }, // 7857 |
| 15148 | { PseudoVRGATHEREI16_VV_M4_E32_M2_MASK, VRGATHEREI16_VV, 0x2, 0x20 }, // 7858 |
| 15149 | { PseudoVRGATHEREI16_VV_M4_E32_M4, VRGATHEREI16_VV, 0x2, 0x20 }, // 7859 |
| 15150 | { PseudoVRGATHEREI16_VV_M4_E32_M4_MASK, VRGATHEREI16_VV, 0x2, 0x20 }, // 7860 |
| 15151 | { PseudoVRGATHEREI16_VV_M4_E32_M8, VRGATHEREI16_VV, 0x2, 0x20 }, // 7861 |
| 15152 | { PseudoVRGATHEREI16_VV_M4_E32_M8_MASK, VRGATHEREI16_VV, 0x2, 0x20 }, // 7862 |
| 15153 | { PseudoVRGATHEREI16_VV_M4_E64_M1, VRGATHEREI16_VV, 0x2, 0x40 }, // 7863 |
| 15154 | { PseudoVRGATHEREI16_VV_M4_E64_M1_MASK, VRGATHEREI16_VV, 0x2, 0x40 }, // 7864 |
| 15155 | { PseudoVRGATHEREI16_VV_M4_E64_M2, VRGATHEREI16_VV, 0x2, 0x40 }, // 7865 |
| 15156 | { PseudoVRGATHEREI16_VV_M4_E64_M2_MASK, VRGATHEREI16_VV, 0x2, 0x40 }, // 7866 |
| 15157 | { PseudoVRGATHEREI16_VV_M4_E64_M4, VRGATHEREI16_VV, 0x2, 0x40 }, // 7867 |
| 15158 | { PseudoVRGATHEREI16_VV_M4_E64_M4_MASK, VRGATHEREI16_VV, 0x2, 0x40 }, // 7868 |
| 15159 | { PseudoVRGATHEREI16_VV_M4_E64_M8, VRGATHEREI16_VV, 0x2, 0x40 }, // 7869 |
| 15160 | { PseudoVRGATHEREI16_VV_M4_E64_M8_MASK, VRGATHEREI16_VV, 0x2, 0x40 }, // 7870 |
| 15161 | { PseudoVRGATHEREI16_VV_M8_E8_M2, VRGATHEREI16_VV, 0x3, 0x8 }, // 7871 |
| 15162 | { PseudoVRGATHEREI16_VV_M8_E8_M2_MASK, VRGATHEREI16_VV, 0x3, 0x8 }, // 7872 |
| 15163 | { PseudoVRGATHEREI16_VV_M8_E8_M4, VRGATHEREI16_VV, 0x3, 0x8 }, // 7873 |
| 15164 | { PseudoVRGATHEREI16_VV_M8_E8_M4_MASK, VRGATHEREI16_VV, 0x3, 0x8 }, // 7874 |
| 15165 | { PseudoVRGATHEREI16_VV_M8_E8_M8, VRGATHEREI16_VV, 0x3, 0x8 }, // 7875 |
| 15166 | { PseudoVRGATHEREI16_VV_M8_E8_M8_MASK, VRGATHEREI16_VV, 0x3, 0x8 }, // 7876 |
| 15167 | { PseudoVRGATHEREI16_VV_M8_E16_M2, VRGATHEREI16_VV, 0x3, 0x10 }, // 7877 |
| 15168 | { PseudoVRGATHEREI16_VV_M8_E16_M2_MASK, VRGATHEREI16_VV, 0x3, 0x10 }, // 7878 |
| 15169 | { PseudoVRGATHEREI16_VV_M8_E16_M4, VRGATHEREI16_VV, 0x3, 0x10 }, // 7879 |
| 15170 | { PseudoVRGATHEREI16_VV_M8_E16_M4_MASK, VRGATHEREI16_VV, 0x3, 0x10 }, // 7880 |
| 15171 | { PseudoVRGATHEREI16_VV_M8_E16_M8, VRGATHEREI16_VV, 0x3, 0x10 }, // 7881 |
| 15172 | { PseudoVRGATHEREI16_VV_M8_E16_M8_MASK, VRGATHEREI16_VV, 0x3, 0x10 }, // 7882 |
| 15173 | { PseudoVRGATHEREI16_VV_M8_E32_M2, VRGATHEREI16_VV, 0x3, 0x20 }, // 7883 |
| 15174 | { PseudoVRGATHEREI16_VV_M8_E32_M2_MASK, VRGATHEREI16_VV, 0x3, 0x20 }, // 7884 |
| 15175 | { PseudoVRGATHEREI16_VV_M8_E32_M4, VRGATHEREI16_VV, 0x3, 0x20 }, // 7885 |
| 15176 | { PseudoVRGATHEREI16_VV_M8_E32_M4_MASK, VRGATHEREI16_VV, 0x3, 0x20 }, // 7886 |
| 15177 | { PseudoVRGATHEREI16_VV_M8_E32_M8, VRGATHEREI16_VV, 0x3, 0x20 }, // 7887 |
| 15178 | { PseudoVRGATHEREI16_VV_M8_E32_M8_MASK, VRGATHEREI16_VV, 0x3, 0x20 }, // 7888 |
| 15179 | { PseudoVRGATHEREI16_VV_M8_E64_M2, VRGATHEREI16_VV, 0x3, 0x40 }, // 7889 |
| 15180 | { PseudoVRGATHEREI16_VV_M8_E64_M2_MASK, VRGATHEREI16_VV, 0x3, 0x40 }, // 7890 |
| 15181 | { PseudoVRGATHEREI16_VV_M8_E64_M4, VRGATHEREI16_VV, 0x3, 0x40 }, // 7891 |
| 15182 | { PseudoVRGATHEREI16_VV_M8_E64_M4_MASK, VRGATHEREI16_VV, 0x3, 0x40 }, // 7892 |
| 15183 | { PseudoVRGATHEREI16_VV_M8_E64_M8, VRGATHEREI16_VV, 0x3, 0x40 }, // 7893 |
| 15184 | { PseudoVRGATHEREI16_VV_M8_E64_M8_MASK, VRGATHEREI16_VV, 0x3, 0x40 }, // 7894 |
| 15185 | { PseudoVRGATHEREI16_VV_MF8_E8_MF4, VRGATHEREI16_VV, 0x5, 0x8 }, // 7895 |
| 15186 | { PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK, VRGATHEREI16_VV, 0x5, 0x8 }, // 7896 |
| 15187 | { PseudoVRGATHEREI16_VV_MF8_E8_MF8, VRGATHEREI16_VV, 0x5, 0x8 }, // 7897 |
| 15188 | { PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK, VRGATHEREI16_VV, 0x5, 0x8 }, // 7898 |
| 15189 | { PseudoVRGATHEREI16_VV_MF4_E8_MF2, VRGATHEREI16_VV, 0x6, 0x8 }, // 7899 |
| 15190 | { PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK, VRGATHEREI16_VV, 0x6, 0x8 }, // 7900 |
| 15191 | { PseudoVRGATHEREI16_VV_MF4_E8_MF4, VRGATHEREI16_VV, 0x6, 0x8 }, // 7901 |
| 15192 | { PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK, VRGATHEREI16_VV, 0x6, 0x8 }, // 7902 |
| 15193 | { PseudoVRGATHEREI16_VV_MF4_E8_MF8, VRGATHEREI16_VV, 0x6, 0x8 }, // 7903 |
| 15194 | { PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK, VRGATHEREI16_VV, 0x6, 0x8 }, // 7904 |
| 15195 | { PseudoVRGATHEREI16_VV_MF4_E16_MF2, VRGATHEREI16_VV, 0x6, 0x10 }, // 7905 |
| 15196 | { PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK, VRGATHEREI16_VV, 0x6, 0x10 }, // 7906 |
| 15197 | { PseudoVRGATHEREI16_VV_MF4_E16_MF4, VRGATHEREI16_VV, 0x6, 0x10 }, // 7907 |
| 15198 | { PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK, VRGATHEREI16_VV, 0x6, 0x10 }, // 7908 |
| 15199 | { PseudoVRGATHEREI16_VV_MF4_E16_MF8, VRGATHEREI16_VV, 0x6, 0x10 }, // 7909 |
| 15200 | { PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK, VRGATHEREI16_VV, 0x6, 0x10 }, // 7910 |
| 15201 | { PseudoVRGATHEREI16_VV_MF2_E8_M1, VRGATHEREI16_VV, 0x7, 0x8 }, // 7911 |
| 15202 | { PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK, VRGATHEREI16_VV, 0x7, 0x8 }, // 7912 |
| 15203 | { PseudoVRGATHEREI16_VV_MF2_E8_MF2, VRGATHEREI16_VV, 0x7, 0x8 }, // 7913 |
| 15204 | { PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK, VRGATHEREI16_VV, 0x7, 0x8 }, // 7914 |
| 15205 | { PseudoVRGATHEREI16_VV_MF2_E8_MF4, VRGATHEREI16_VV, 0x7, 0x8 }, // 7915 |
| 15206 | { PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK, VRGATHEREI16_VV, 0x7, 0x8 }, // 7916 |
| 15207 | { PseudoVRGATHEREI16_VV_MF2_E8_MF8, VRGATHEREI16_VV, 0x7, 0x8 }, // 7917 |
| 15208 | { PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK, VRGATHEREI16_VV, 0x7, 0x8 }, // 7918 |
| 15209 | { PseudoVRGATHEREI16_VV_MF2_E16_M1, VRGATHEREI16_VV, 0x7, 0x10 }, // 7919 |
| 15210 | { PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK, VRGATHEREI16_VV, 0x7, 0x10 }, // 7920 |
| 15211 | { PseudoVRGATHEREI16_VV_MF2_E16_MF2, VRGATHEREI16_VV, 0x7, 0x10 }, // 7921 |
| 15212 | { PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK, VRGATHEREI16_VV, 0x7, 0x10 }, // 7922 |
| 15213 | { PseudoVRGATHEREI16_VV_MF2_E16_MF4, VRGATHEREI16_VV, 0x7, 0x10 }, // 7923 |
| 15214 | { PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK, VRGATHEREI16_VV, 0x7, 0x10 }, // 7924 |
| 15215 | { PseudoVRGATHEREI16_VV_MF2_E16_MF8, VRGATHEREI16_VV, 0x7, 0x10 }, // 7925 |
| 15216 | { PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK, VRGATHEREI16_VV, 0x7, 0x10 }, // 7926 |
| 15217 | { PseudoVRGATHEREI16_VV_MF2_E32_M1, VRGATHEREI16_VV, 0x7, 0x20 }, // 7927 |
| 15218 | { PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK, VRGATHEREI16_VV, 0x7, 0x20 }, // 7928 |
| 15219 | { PseudoVRGATHEREI16_VV_MF2_E32_MF2, VRGATHEREI16_VV, 0x7, 0x20 }, // 7929 |
| 15220 | { PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK, VRGATHEREI16_VV, 0x7, 0x20 }, // 7930 |
| 15221 | { PseudoVRGATHEREI16_VV_MF2_E32_MF4, VRGATHEREI16_VV, 0x7, 0x20 }, // 7931 |
| 15222 | { PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK, VRGATHEREI16_VV, 0x7, 0x20 }, // 7932 |
| 15223 | { PseudoVRGATHEREI16_VV_MF2_E32_MF8, VRGATHEREI16_VV, 0x7, 0x20 }, // 7933 |
| 15224 | { PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK, VRGATHEREI16_VV, 0x7, 0x20 }, // 7934 |
| 15225 | { PseudoVRGATHER_VI_M1, VRGATHER_VI, 0x0, 0x0 }, // 7935 |
| 15226 | { PseudoVRGATHER_VI_M1_MASK, VRGATHER_VI, 0x0, 0x0 }, // 7936 |
| 15227 | { PseudoVRGATHER_VI_M2, VRGATHER_VI, 0x1, 0x0 }, // 7937 |
| 15228 | { PseudoVRGATHER_VI_M2_MASK, VRGATHER_VI, 0x1, 0x0 }, // 7938 |
| 15229 | { PseudoVRGATHER_VI_M4, VRGATHER_VI, 0x2, 0x0 }, // 7939 |
| 15230 | { PseudoVRGATHER_VI_M4_MASK, VRGATHER_VI, 0x2, 0x0 }, // 7940 |
| 15231 | { PseudoVRGATHER_VI_M8, VRGATHER_VI, 0x3, 0x0 }, // 7941 |
| 15232 | { PseudoVRGATHER_VI_M8_MASK, VRGATHER_VI, 0x3, 0x0 }, // 7942 |
| 15233 | { PseudoVRGATHER_VI_MF8, VRGATHER_VI, 0x5, 0x0 }, // 7943 |
| 15234 | { PseudoVRGATHER_VI_MF8_MASK, VRGATHER_VI, 0x5, 0x0 }, // 7944 |
| 15235 | { PseudoVRGATHER_VI_MF4, VRGATHER_VI, 0x6, 0x0 }, // 7945 |
| 15236 | { PseudoVRGATHER_VI_MF4_MASK, VRGATHER_VI, 0x6, 0x0 }, // 7946 |
| 15237 | { PseudoVRGATHER_VI_MF2, VRGATHER_VI, 0x7, 0x0 }, // 7947 |
| 15238 | { PseudoVRGATHER_VI_MF2_MASK, VRGATHER_VI, 0x7, 0x0 }, // 7948 |
| 15239 | { PseudoVRGATHER_VV_M1_E8, VRGATHER_VV, 0x0, 0x8 }, // 7949 |
| 15240 | { PseudoVRGATHER_VV_M1_E8_MASK, VRGATHER_VV, 0x0, 0x8 }, // 7950 |
| 15241 | { PseudoVRGATHER_VV_M1_E16, VRGATHER_VV, 0x0, 0x10 }, // 7951 |
| 15242 | { PseudoVRGATHER_VV_M1_E16_MASK, VRGATHER_VV, 0x0, 0x10 }, // 7952 |
| 15243 | { PseudoVRGATHER_VV_M1_E32, VRGATHER_VV, 0x0, 0x20 }, // 7953 |
| 15244 | { PseudoVRGATHER_VV_M1_E32_MASK, VRGATHER_VV, 0x0, 0x20 }, // 7954 |
| 15245 | { PseudoVRGATHER_VV_M1_E64, VRGATHER_VV, 0x0, 0x40 }, // 7955 |
| 15246 | { PseudoVRGATHER_VV_M1_E64_MASK, VRGATHER_VV, 0x0, 0x40 }, // 7956 |
| 15247 | { PseudoVRGATHER_VV_M2_E8, VRGATHER_VV, 0x1, 0x8 }, // 7957 |
| 15248 | { PseudoVRGATHER_VV_M2_E8_MASK, VRGATHER_VV, 0x1, 0x8 }, // 7958 |
| 15249 | { PseudoVRGATHER_VV_M2_E16, VRGATHER_VV, 0x1, 0x10 }, // 7959 |
| 15250 | { PseudoVRGATHER_VV_M2_E16_MASK, VRGATHER_VV, 0x1, 0x10 }, // 7960 |
| 15251 | { PseudoVRGATHER_VV_M2_E32, VRGATHER_VV, 0x1, 0x20 }, // 7961 |
| 15252 | { PseudoVRGATHER_VV_M2_E32_MASK, VRGATHER_VV, 0x1, 0x20 }, // 7962 |
| 15253 | { PseudoVRGATHER_VV_M2_E64, VRGATHER_VV, 0x1, 0x40 }, // 7963 |
| 15254 | { PseudoVRGATHER_VV_M2_E64_MASK, VRGATHER_VV, 0x1, 0x40 }, // 7964 |
| 15255 | { PseudoVRGATHER_VV_M4_E8, VRGATHER_VV, 0x2, 0x8 }, // 7965 |
| 15256 | { PseudoVRGATHER_VV_M4_E8_MASK, VRGATHER_VV, 0x2, 0x8 }, // 7966 |
| 15257 | { PseudoVRGATHER_VV_M4_E16, VRGATHER_VV, 0x2, 0x10 }, // 7967 |
| 15258 | { PseudoVRGATHER_VV_M4_E16_MASK, VRGATHER_VV, 0x2, 0x10 }, // 7968 |
| 15259 | { PseudoVRGATHER_VV_M4_E32, VRGATHER_VV, 0x2, 0x20 }, // 7969 |
| 15260 | { PseudoVRGATHER_VV_M4_E32_MASK, VRGATHER_VV, 0x2, 0x20 }, // 7970 |
| 15261 | { PseudoVRGATHER_VV_M4_E64, VRGATHER_VV, 0x2, 0x40 }, // 7971 |
| 15262 | { PseudoVRGATHER_VV_M4_E64_MASK, VRGATHER_VV, 0x2, 0x40 }, // 7972 |
| 15263 | { PseudoVRGATHER_VV_M8_E8, VRGATHER_VV, 0x3, 0x8 }, // 7973 |
| 15264 | { PseudoVRGATHER_VV_M8_E8_MASK, VRGATHER_VV, 0x3, 0x8 }, // 7974 |
| 15265 | { PseudoVRGATHER_VV_M8_E16, VRGATHER_VV, 0x3, 0x10 }, // 7975 |
| 15266 | { PseudoVRGATHER_VV_M8_E16_MASK, VRGATHER_VV, 0x3, 0x10 }, // 7976 |
| 15267 | { PseudoVRGATHER_VV_M8_E32, VRGATHER_VV, 0x3, 0x20 }, // 7977 |
| 15268 | { PseudoVRGATHER_VV_M8_E32_MASK, VRGATHER_VV, 0x3, 0x20 }, // 7978 |
| 15269 | { PseudoVRGATHER_VV_M8_E64, VRGATHER_VV, 0x3, 0x40 }, // 7979 |
| 15270 | { PseudoVRGATHER_VV_M8_E64_MASK, VRGATHER_VV, 0x3, 0x40 }, // 7980 |
| 15271 | { PseudoVRGATHER_VV_MF8_E8, VRGATHER_VV, 0x5, 0x8 }, // 7981 |
| 15272 | { PseudoVRGATHER_VV_MF8_E8_MASK, VRGATHER_VV, 0x5, 0x8 }, // 7982 |
| 15273 | { PseudoVRGATHER_VV_MF4_E8, VRGATHER_VV, 0x6, 0x8 }, // 7983 |
| 15274 | { PseudoVRGATHER_VV_MF4_E8_MASK, VRGATHER_VV, 0x6, 0x8 }, // 7984 |
| 15275 | { PseudoVRGATHER_VV_MF4_E16, VRGATHER_VV, 0x6, 0x10 }, // 7985 |
| 15276 | { PseudoVRGATHER_VV_MF4_E16_MASK, VRGATHER_VV, 0x6, 0x10 }, // 7986 |
| 15277 | { PseudoVRGATHER_VV_MF2_E8, VRGATHER_VV, 0x7, 0x8 }, // 7987 |
| 15278 | { PseudoVRGATHER_VV_MF2_E8_MASK, VRGATHER_VV, 0x7, 0x8 }, // 7988 |
| 15279 | { PseudoVRGATHER_VV_MF2_E16, VRGATHER_VV, 0x7, 0x10 }, // 7989 |
| 15280 | { PseudoVRGATHER_VV_MF2_E16_MASK, VRGATHER_VV, 0x7, 0x10 }, // 7990 |
| 15281 | { PseudoVRGATHER_VV_MF2_E32, VRGATHER_VV, 0x7, 0x20 }, // 7991 |
| 15282 | { PseudoVRGATHER_VV_MF2_E32_MASK, VRGATHER_VV, 0x7, 0x20 }, // 7992 |
| 15283 | { PseudoVRGATHER_VX_M1, VRGATHER_VX, 0x0, 0x0 }, // 7993 |
| 15284 | { PseudoVRGATHER_VX_M1_MASK, VRGATHER_VX, 0x0, 0x0 }, // 7994 |
| 15285 | { PseudoVRGATHER_VX_M2, VRGATHER_VX, 0x1, 0x0 }, // 7995 |
| 15286 | { PseudoVRGATHER_VX_M2_MASK, VRGATHER_VX, 0x1, 0x0 }, // 7996 |
| 15287 | { PseudoVRGATHER_VX_M4, VRGATHER_VX, 0x2, 0x0 }, // 7997 |
| 15288 | { PseudoVRGATHER_VX_M4_MASK, VRGATHER_VX, 0x2, 0x0 }, // 7998 |
| 15289 | { PseudoVRGATHER_VX_M8, VRGATHER_VX, 0x3, 0x0 }, // 7999 |
| 15290 | { PseudoVRGATHER_VX_M8_MASK, VRGATHER_VX, 0x3, 0x0 }, // 8000 |
| 15291 | { PseudoVRGATHER_VX_MF8, VRGATHER_VX, 0x5, 0x0 }, // 8001 |
| 15292 | { PseudoVRGATHER_VX_MF8_MASK, VRGATHER_VX, 0x5, 0x0 }, // 8002 |
| 15293 | { PseudoVRGATHER_VX_MF4, VRGATHER_VX, 0x6, 0x0 }, // 8003 |
| 15294 | { PseudoVRGATHER_VX_MF4_MASK, VRGATHER_VX, 0x6, 0x0 }, // 8004 |
| 15295 | { PseudoVRGATHER_VX_MF2, VRGATHER_VX, 0x7, 0x0 }, // 8005 |
| 15296 | { PseudoVRGATHER_VX_MF2_MASK, VRGATHER_VX, 0x7, 0x0 }, // 8006 |
| 15297 | { PseudoVROL_VV_M1, VROL_VV, 0x0, 0x0 }, // 8007 |
| 15298 | { PseudoVROL_VV_M1_MASK, VROL_VV, 0x0, 0x0 }, // 8008 |
| 15299 | { PseudoVROL_VV_M2, VROL_VV, 0x1, 0x0 }, // 8009 |
| 15300 | { PseudoVROL_VV_M2_MASK, VROL_VV, 0x1, 0x0 }, // 8010 |
| 15301 | { PseudoVROL_VV_M4, VROL_VV, 0x2, 0x0 }, // 8011 |
| 15302 | { PseudoVROL_VV_M4_MASK, VROL_VV, 0x2, 0x0 }, // 8012 |
| 15303 | { PseudoVROL_VV_M8, VROL_VV, 0x3, 0x0 }, // 8013 |
| 15304 | { PseudoVROL_VV_M8_MASK, VROL_VV, 0x3, 0x0 }, // 8014 |
| 15305 | { PseudoVROL_VV_MF8, VROL_VV, 0x5, 0x0 }, // 8015 |
| 15306 | { PseudoVROL_VV_MF8_MASK, VROL_VV, 0x5, 0x0 }, // 8016 |
| 15307 | { PseudoVROL_VV_MF4, VROL_VV, 0x6, 0x0 }, // 8017 |
| 15308 | { PseudoVROL_VV_MF4_MASK, VROL_VV, 0x6, 0x0 }, // 8018 |
| 15309 | { PseudoVROL_VV_MF2, VROL_VV, 0x7, 0x0 }, // 8019 |
| 15310 | { PseudoVROL_VV_MF2_MASK, VROL_VV, 0x7, 0x0 }, // 8020 |
| 15311 | { PseudoVROL_VX_M1, VROL_VX, 0x0, 0x0 }, // 8021 |
| 15312 | { PseudoVROL_VX_M1_MASK, VROL_VX, 0x0, 0x0 }, // 8022 |
| 15313 | { PseudoVROL_VX_M2, VROL_VX, 0x1, 0x0 }, // 8023 |
| 15314 | { PseudoVROL_VX_M2_MASK, VROL_VX, 0x1, 0x0 }, // 8024 |
| 15315 | { PseudoVROL_VX_M4, VROL_VX, 0x2, 0x0 }, // 8025 |
| 15316 | { PseudoVROL_VX_M4_MASK, VROL_VX, 0x2, 0x0 }, // 8026 |
| 15317 | { PseudoVROL_VX_M8, VROL_VX, 0x3, 0x0 }, // 8027 |
| 15318 | { PseudoVROL_VX_M8_MASK, VROL_VX, 0x3, 0x0 }, // 8028 |
| 15319 | { PseudoVROL_VX_MF8, VROL_VX, 0x5, 0x0 }, // 8029 |
| 15320 | { PseudoVROL_VX_MF8_MASK, VROL_VX, 0x5, 0x0 }, // 8030 |
| 15321 | { PseudoVROL_VX_MF4, VROL_VX, 0x6, 0x0 }, // 8031 |
| 15322 | { PseudoVROL_VX_MF4_MASK, VROL_VX, 0x6, 0x0 }, // 8032 |
| 15323 | { PseudoVROL_VX_MF2, VROL_VX, 0x7, 0x0 }, // 8033 |
| 15324 | { PseudoVROL_VX_MF2_MASK, VROL_VX, 0x7, 0x0 }, // 8034 |
| 15325 | { PseudoVROR_VI_M1, VROR_VI, 0x0, 0x0 }, // 8035 |
| 15326 | { PseudoVROR_VI_M1_MASK, VROR_VI, 0x0, 0x0 }, // 8036 |
| 15327 | { PseudoVROR_VI_M2, VROR_VI, 0x1, 0x0 }, // 8037 |
| 15328 | { PseudoVROR_VI_M2_MASK, VROR_VI, 0x1, 0x0 }, // 8038 |
| 15329 | { PseudoVROR_VI_M4, VROR_VI, 0x2, 0x0 }, // 8039 |
| 15330 | { PseudoVROR_VI_M4_MASK, VROR_VI, 0x2, 0x0 }, // 8040 |
| 15331 | { PseudoVROR_VI_M8, VROR_VI, 0x3, 0x0 }, // 8041 |
| 15332 | { PseudoVROR_VI_M8_MASK, VROR_VI, 0x3, 0x0 }, // 8042 |
| 15333 | { PseudoVROR_VI_MF8, VROR_VI, 0x5, 0x0 }, // 8043 |
| 15334 | { PseudoVROR_VI_MF8_MASK, VROR_VI, 0x5, 0x0 }, // 8044 |
| 15335 | { PseudoVROR_VI_MF4, VROR_VI, 0x6, 0x0 }, // 8045 |
| 15336 | { PseudoVROR_VI_MF4_MASK, VROR_VI, 0x6, 0x0 }, // 8046 |
| 15337 | { PseudoVROR_VI_MF2, VROR_VI, 0x7, 0x0 }, // 8047 |
| 15338 | { PseudoVROR_VI_MF2_MASK, VROR_VI, 0x7, 0x0 }, // 8048 |
| 15339 | { PseudoVROR_VV_M1, VROR_VV, 0x0, 0x0 }, // 8049 |
| 15340 | { PseudoVROR_VV_M1_MASK, VROR_VV, 0x0, 0x0 }, // 8050 |
| 15341 | { PseudoVROR_VV_M2, VROR_VV, 0x1, 0x0 }, // 8051 |
| 15342 | { PseudoVROR_VV_M2_MASK, VROR_VV, 0x1, 0x0 }, // 8052 |
| 15343 | { PseudoVROR_VV_M4, VROR_VV, 0x2, 0x0 }, // 8053 |
| 15344 | { PseudoVROR_VV_M4_MASK, VROR_VV, 0x2, 0x0 }, // 8054 |
| 15345 | { PseudoVROR_VV_M8, VROR_VV, 0x3, 0x0 }, // 8055 |
| 15346 | { PseudoVROR_VV_M8_MASK, VROR_VV, 0x3, 0x0 }, // 8056 |
| 15347 | { PseudoVROR_VV_MF8, VROR_VV, 0x5, 0x0 }, // 8057 |
| 15348 | { PseudoVROR_VV_MF8_MASK, VROR_VV, 0x5, 0x0 }, // 8058 |
| 15349 | { PseudoVROR_VV_MF4, VROR_VV, 0x6, 0x0 }, // 8059 |
| 15350 | { PseudoVROR_VV_MF4_MASK, VROR_VV, 0x6, 0x0 }, // 8060 |
| 15351 | { PseudoVROR_VV_MF2, VROR_VV, 0x7, 0x0 }, // 8061 |
| 15352 | { PseudoVROR_VV_MF2_MASK, VROR_VV, 0x7, 0x0 }, // 8062 |
| 15353 | { PseudoVROR_VX_M1, VROR_VX, 0x0, 0x0 }, // 8063 |
| 15354 | { PseudoVROR_VX_M1_MASK, VROR_VX, 0x0, 0x0 }, // 8064 |
| 15355 | { PseudoVROR_VX_M2, VROR_VX, 0x1, 0x0 }, // 8065 |
| 15356 | { PseudoVROR_VX_M2_MASK, VROR_VX, 0x1, 0x0 }, // 8066 |
| 15357 | { PseudoVROR_VX_M4, VROR_VX, 0x2, 0x0 }, // 8067 |
| 15358 | { PseudoVROR_VX_M4_MASK, VROR_VX, 0x2, 0x0 }, // 8068 |
| 15359 | { PseudoVROR_VX_M8, VROR_VX, 0x3, 0x0 }, // 8069 |
| 15360 | { PseudoVROR_VX_M8_MASK, VROR_VX, 0x3, 0x0 }, // 8070 |
| 15361 | { PseudoVROR_VX_MF8, VROR_VX, 0x5, 0x0 }, // 8071 |
| 15362 | { PseudoVROR_VX_MF8_MASK, VROR_VX, 0x5, 0x0 }, // 8072 |
| 15363 | { PseudoVROR_VX_MF4, VROR_VX, 0x6, 0x0 }, // 8073 |
| 15364 | { PseudoVROR_VX_MF4_MASK, VROR_VX, 0x6, 0x0 }, // 8074 |
| 15365 | { PseudoVROR_VX_MF2, VROR_VX, 0x7, 0x0 }, // 8075 |
| 15366 | { PseudoVROR_VX_MF2_MASK, VROR_VX, 0x7, 0x0 }, // 8076 |
| 15367 | { PseudoVRSUB_VI_M1, VRSUB_VI, 0x0, 0x0 }, // 8077 |
| 15368 | { PseudoVRSUB_VI_M1_MASK, VRSUB_VI, 0x0, 0x0 }, // 8078 |
| 15369 | { PseudoVRSUB_VI_M2, VRSUB_VI, 0x1, 0x0 }, // 8079 |
| 15370 | { PseudoVRSUB_VI_M2_MASK, VRSUB_VI, 0x1, 0x0 }, // 8080 |
| 15371 | { PseudoVRSUB_VI_M4, VRSUB_VI, 0x2, 0x0 }, // 8081 |
| 15372 | { PseudoVRSUB_VI_M4_MASK, VRSUB_VI, 0x2, 0x0 }, // 8082 |
| 15373 | { PseudoVRSUB_VI_M8, VRSUB_VI, 0x3, 0x0 }, // 8083 |
| 15374 | { PseudoVRSUB_VI_M8_MASK, VRSUB_VI, 0x3, 0x0 }, // 8084 |
| 15375 | { PseudoVRSUB_VI_MF8, VRSUB_VI, 0x5, 0x0 }, // 8085 |
| 15376 | { PseudoVRSUB_VI_MF8_MASK, VRSUB_VI, 0x5, 0x0 }, // 8086 |
| 15377 | { PseudoVRSUB_VI_MF4, VRSUB_VI, 0x6, 0x0 }, // 8087 |
| 15378 | { PseudoVRSUB_VI_MF4_MASK, VRSUB_VI, 0x6, 0x0 }, // 8088 |
| 15379 | { PseudoVRSUB_VI_MF2, VRSUB_VI, 0x7, 0x0 }, // 8089 |
| 15380 | { PseudoVRSUB_VI_MF2_MASK, VRSUB_VI, 0x7, 0x0 }, // 8090 |
| 15381 | { PseudoVRSUB_VX_M1, VRSUB_VX, 0x0, 0x0 }, // 8091 |
| 15382 | { PseudoVRSUB_VX_M1_MASK, VRSUB_VX, 0x0, 0x0 }, // 8092 |
| 15383 | { PseudoVRSUB_VX_M2, VRSUB_VX, 0x1, 0x0 }, // 8093 |
| 15384 | { PseudoVRSUB_VX_M2_MASK, VRSUB_VX, 0x1, 0x0 }, // 8094 |
| 15385 | { PseudoVRSUB_VX_M4, VRSUB_VX, 0x2, 0x0 }, // 8095 |
| 15386 | { PseudoVRSUB_VX_M4_MASK, VRSUB_VX, 0x2, 0x0 }, // 8096 |
| 15387 | { PseudoVRSUB_VX_M8, VRSUB_VX, 0x3, 0x0 }, // 8097 |
| 15388 | { PseudoVRSUB_VX_M8_MASK, VRSUB_VX, 0x3, 0x0 }, // 8098 |
| 15389 | { PseudoVRSUB_VX_MF8, VRSUB_VX, 0x5, 0x0 }, // 8099 |
| 15390 | { PseudoVRSUB_VX_MF8_MASK, VRSUB_VX, 0x5, 0x0 }, // 8100 |
| 15391 | { PseudoVRSUB_VX_MF4, VRSUB_VX, 0x6, 0x0 }, // 8101 |
| 15392 | { PseudoVRSUB_VX_MF4_MASK, VRSUB_VX, 0x6, 0x0 }, // 8102 |
| 15393 | { PseudoVRSUB_VX_MF2, VRSUB_VX, 0x7, 0x0 }, // 8103 |
| 15394 | { PseudoVRSUB_VX_MF2_MASK, VRSUB_VX, 0x7, 0x0 }, // 8104 |
| 15395 | { PseudoVSADDU_VI_M1, VSADDU_VI, 0x0, 0x0 }, // 8105 |
| 15396 | { PseudoVSADDU_VI_M1_MASK, VSADDU_VI, 0x0, 0x0 }, // 8106 |
| 15397 | { PseudoVSADDU_VI_M2, VSADDU_VI, 0x1, 0x0 }, // 8107 |
| 15398 | { PseudoVSADDU_VI_M2_MASK, VSADDU_VI, 0x1, 0x0 }, // 8108 |
| 15399 | { PseudoVSADDU_VI_M4, VSADDU_VI, 0x2, 0x0 }, // 8109 |
| 15400 | { PseudoVSADDU_VI_M4_MASK, VSADDU_VI, 0x2, 0x0 }, // 8110 |
| 15401 | { PseudoVSADDU_VI_M8, VSADDU_VI, 0x3, 0x0 }, // 8111 |
| 15402 | { PseudoVSADDU_VI_M8_MASK, VSADDU_VI, 0x3, 0x0 }, // 8112 |
| 15403 | { PseudoVSADDU_VI_MF8, VSADDU_VI, 0x5, 0x0 }, // 8113 |
| 15404 | { PseudoVSADDU_VI_MF8_MASK, VSADDU_VI, 0x5, 0x0 }, // 8114 |
| 15405 | { PseudoVSADDU_VI_MF4, VSADDU_VI, 0x6, 0x0 }, // 8115 |
| 15406 | { PseudoVSADDU_VI_MF4_MASK, VSADDU_VI, 0x6, 0x0 }, // 8116 |
| 15407 | { PseudoVSADDU_VI_MF2, VSADDU_VI, 0x7, 0x0 }, // 8117 |
| 15408 | { PseudoVSADDU_VI_MF2_MASK, VSADDU_VI, 0x7, 0x0 }, // 8118 |
| 15409 | { PseudoVSADDU_VV_M1, VSADDU_VV, 0x0, 0x0 }, // 8119 |
| 15410 | { PseudoVSADDU_VV_M1_MASK, VSADDU_VV, 0x0, 0x0 }, // 8120 |
| 15411 | { PseudoVSADDU_VV_M2, VSADDU_VV, 0x1, 0x0 }, // 8121 |
| 15412 | { PseudoVSADDU_VV_M2_MASK, VSADDU_VV, 0x1, 0x0 }, // 8122 |
| 15413 | { PseudoVSADDU_VV_M4, VSADDU_VV, 0x2, 0x0 }, // 8123 |
| 15414 | { PseudoVSADDU_VV_M4_MASK, VSADDU_VV, 0x2, 0x0 }, // 8124 |
| 15415 | { PseudoVSADDU_VV_M8, VSADDU_VV, 0x3, 0x0 }, // 8125 |
| 15416 | { PseudoVSADDU_VV_M8_MASK, VSADDU_VV, 0x3, 0x0 }, // 8126 |
| 15417 | { PseudoVSADDU_VV_MF8, VSADDU_VV, 0x5, 0x0 }, // 8127 |
| 15418 | { PseudoVSADDU_VV_MF8_MASK, VSADDU_VV, 0x5, 0x0 }, // 8128 |
| 15419 | { PseudoVSADDU_VV_MF4, VSADDU_VV, 0x6, 0x0 }, // 8129 |
| 15420 | { PseudoVSADDU_VV_MF4_MASK, VSADDU_VV, 0x6, 0x0 }, // 8130 |
| 15421 | { PseudoVSADDU_VV_MF2, VSADDU_VV, 0x7, 0x0 }, // 8131 |
| 15422 | { PseudoVSADDU_VV_MF2_MASK, VSADDU_VV, 0x7, 0x0 }, // 8132 |
| 15423 | { PseudoVSADDU_VX_M1, VSADDU_VX, 0x0, 0x0 }, // 8133 |
| 15424 | { PseudoVSADDU_VX_M1_MASK, VSADDU_VX, 0x0, 0x0 }, // 8134 |
| 15425 | { PseudoVSADDU_VX_M2, VSADDU_VX, 0x1, 0x0 }, // 8135 |
| 15426 | { PseudoVSADDU_VX_M2_MASK, VSADDU_VX, 0x1, 0x0 }, // 8136 |
| 15427 | { PseudoVSADDU_VX_M4, VSADDU_VX, 0x2, 0x0 }, // 8137 |
| 15428 | { PseudoVSADDU_VX_M4_MASK, VSADDU_VX, 0x2, 0x0 }, // 8138 |
| 15429 | { PseudoVSADDU_VX_M8, VSADDU_VX, 0x3, 0x0 }, // 8139 |
| 15430 | { PseudoVSADDU_VX_M8_MASK, VSADDU_VX, 0x3, 0x0 }, // 8140 |
| 15431 | { PseudoVSADDU_VX_MF8, VSADDU_VX, 0x5, 0x0 }, // 8141 |
| 15432 | { PseudoVSADDU_VX_MF8_MASK, VSADDU_VX, 0x5, 0x0 }, // 8142 |
| 15433 | { PseudoVSADDU_VX_MF4, VSADDU_VX, 0x6, 0x0 }, // 8143 |
| 15434 | { PseudoVSADDU_VX_MF4_MASK, VSADDU_VX, 0x6, 0x0 }, // 8144 |
| 15435 | { PseudoVSADDU_VX_MF2, VSADDU_VX, 0x7, 0x0 }, // 8145 |
| 15436 | { PseudoVSADDU_VX_MF2_MASK, VSADDU_VX, 0x7, 0x0 }, // 8146 |
| 15437 | { PseudoVSADD_VI_M1, VSADD_VI, 0x0, 0x0 }, // 8147 |
| 15438 | { PseudoVSADD_VI_M1_MASK, VSADD_VI, 0x0, 0x0 }, // 8148 |
| 15439 | { PseudoVSADD_VI_M2, VSADD_VI, 0x1, 0x0 }, // 8149 |
| 15440 | { PseudoVSADD_VI_M2_MASK, VSADD_VI, 0x1, 0x0 }, // 8150 |
| 15441 | { PseudoVSADD_VI_M4, VSADD_VI, 0x2, 0x0 }, // 8151 |
| 15442 | { PseudoVSADD_VI_M4_MASK, VSADD_VI, 0x2, 0x0 }, // 8152 |
| 15443 | { PseudoVSADD_VI_M8, VSADD_VI, 0x3, 0x0 }, // 8153 |
| 15444 | { PseudoVSADD_VI_M8_MASK, VSADD_VI, 0x3, 0x0 }, // 8154 |
| 15445 | { PseudoVSADD_VI_MF8, VSADD_VI, 0x5, 0x0 }, // 8155 |
| 15446 | { PseudoVSADD_VI_MF8_MASK, VSADD_VI, 0x5, 0x0 }, // 8156 |
| 15447 | { PseudoVSADD_VI_MF4, VSADD_VI, 0x6, 0x0 }, // 8157 |
| 15448 | { PseudoVSADD_VI_MF4_MASK, VSADD_VI, 0x6, 0x0 }, // 8158 |
| 15449 | { PseudoVSADD_VI_MF2, VSADD_VI, 0x7, 0x0 }, // 8159 |
| 15450 | { PseudoVSADD_VI_MF2_MASK, VSADD_VI, 0x7, 0x0 }, // 8160 |
| 15451 | { PseudoVSADD_VV_M1, VSADD_VV, 0x0, 0x0 }, // 8161 |
| 15452 | { PseudoVSADD_VV_M1_MASK, VSADD_VV, 0x0, 0x0 }, // 8162 |
| 15453 | { PseudoVSADD_VV_M2, VSADD_VV, 0x1, 0x0 }, // 8163 |
| 15454 | { PseudoVSADD_VV_M2_MASK, VSADD_VV, 0x1, 0x0 }, // 8164 |
| 15455 | { PseudoVSADD_VV_M4, VSADD_VV, 0x2, 0x0 }, // 8165 |
| 15456 | { PseudoVSADD_VV_M4_MASK, VSADD_VV, 0x2, 0x0 }, // 8166 |
| 15457 | { PseudoVSADD_VV_M8, VSADD_VV, 0x3, 0x0 }, // 8167 |
| 15458 | { PseudoVSADD_VV_M8_MASK, VSADD_VV, 0x3, 0x0 }, // 8168 |
| 15459 | { PseudoVSADD_VV_MF8, VSADD_VV, 0x5, 0x0 }, // 8169 |
| 15460 | { PseudoVSADD_VV_MF8_MASK, VSADD_VV, 0x5, 0x0 }, // 8170 |
| 15461 | { PseudoVSADD_VV_MF4, VSADD_VV, 0x6, 0x0 }, // 8171 |
| 15462 | { PseudoVSADD_VV_MF4_MASK, VSADD_VV, 0x6, 0x0 }, // 8172 |
| 15463 | { PseudoVSADD_VV_MF2, VSADD_VV, 0x7, 0x0 }, // 8173 |
| 15464 | { PseudoVSADD_VV_MF2_MASK, VSADD_VV, 0x7, 0x0 }, // 8174 |
| 15465 | { PseudoVSADD_VX_M1, VSADD_VX, 0x0, 0x0 }, // 8175 |
| 15466 | { PseudoVSADD_VX_M1_MASK, VSADD_VX, 0x0, 0x0 }, // 8176 |
| 15467 | { PseudoVSADD_VX_M2, VSADD_VX, 0x1, 0x0 }, // 8177 |
| 15468 | { PseudoVSADD_VX_M2_MASK, VSADD_VX, 0x1, 0x0 }, // 8178 |
| 15469 | { PseudoVSADD_VX_M4, VSADD_VX, 0x2, 0x0 }, // 8179 |
| 15470 | { PseudoVSADD_VX_M4_MASK, VSADD_VX, 0x2, 0x0 }, // 8180 |
| 15471 | { PseudoVSADD_VX_M8, VSADD_VX, 0x3, 0x0 }, // 8181 |
| 15472 | { PseudoVSADD_VX_M8_MASK, VSADD_VX, 0x3, 0x0 }, // 8182 |
| 15473 | { PseudoVSADD_VX_MF8, VSADD_VX, 0x5, 0x0 }, // 8183 |
| 15474 | { PseudoVSADD_VX_MF8_MASK, VSADD_VX, 0x5, 0x0 }, // 8184 |
| 15475 | { PseudoVSADD_VX_MF4, VSADD_VX, 0x6, 0x0 }, // 8185 |
| 15476 | { PseudoVSADD_VX_MF4_MASK, VSADD_VX, 0x6, 0x0 }, // 8186 |
| 15477 | { PseudoVSADD_VX_MF2, VSADD_VX, 0x7, 0x0 }, // 8187 |
| 15478 | { PseudoVSADD_VX_MF2_MASK, VSADD_VX, 0x7, 0x0 }, // 8188 |
| 15479 | { PseudoVSBC_VVM_M1, VSBC_VVM, 0x0, 0x0 }, // 8189 |
| 15480 | { PseudoVSBC_VVM_M2, VSBC_VVM, 0x1, 0x0 }, // 8190 |
| 15481 | { PseudoVSBC_VVM_M4, VSBC_VVM, 0x2, 0x0 }, // 8191 |
| 15482 | { PseudoVSBC_VVM_M8, VSBC_VVM, 0x3, 0x0 }, // 8192 |
| 15483 | { PseudoVSBC_VVM_MF8, VSBC_VVM, 0x5, 0x0 }, // 8193 |
| 15484 | { PseudoVSBC_VVM_MF4, VSBC_VVM, 0x6, 0x0 }, // 8194 |
| 15485 | { PseudoVSBC_VVM_MF2, VSBC_VVM, 0x7, 0x0 }, // 8195 |
| 15486 | { PseudoVSBC_VXM_M1, VSBC_VXM, 0x0, 0x0 }, // 8196 |
| 15487 | { PseudoVSBC_VXM_M2, VSBC_VXM, 0x1, 0x0 }, // 8197 |
| 15488 | { PseudoVSBC_VXM_M4, VSBC_VXM, 0x2, 0x0 }, // 8198 |
| 15489 | { PseudoVSBC_VXM_M8, VSBC_VXM, 0x3, 0x0 }, // 8199 |
| 15490 | { PseudoVSBC_VXM_MF8, VSBC_VXM, 0x5, 0x0 }, // 8200 |
| 15491 | { PseudoVSBC_VXM_MF4, VSBC_VXM, 0x6, 0x0 }, // 8201 |
| 15492 | { PseudoVSBC_VXM_MF2, VSBC_VXM, 0x7, 0x0 }, // 8202 |
| 15493 | { PseudoVSE16_V_M1, VSE16_V, 0x0, 0x10 }, // 8203 |
| 15494 | { PseudoVSE16_V_M1_MASK, VSE16_V, 0x0, 0x10 }, // 8204 |
| 15495 | { PseudoVSE16_V_M2, VSE16_V, 0x1, 0x10 }, // 8205 |
| 15496 | { PseudoVSE16_V_M2_MASK, VSE16_V, 0x1, 0x10 }, // 8206 |
| 15497 | { PseudoVSE16_V_M4, VSE16_V, 0x2, 0x10 }, // 8207 |
| 15498 | { PseudoVSE16_V_M4_MASK, VSE16_V, 0x2, 0x10 }, // 8208 |
| 15499 | { PseudoVSE16_V_M8, VSE16_V, 0x3, 0x10 }, // 8209 |
| 15500 | { PseudoVSE16_V_M8_MASK, VSE16_V, 0x3, 0x10 }, // 8210 |
| 15501 | { PseudoVSE16_V_MF4, VSE16_V, 0x6, 0x10 }, // 8211 |
| 15502 | { PseudoVSE16_V_MF4_MASK, VSE16_V, 0x6, 0x10 }, // 8212 |
| 15503 | { PseudoVSE16_V_MF2, VSE16_V, 0x7, 0x10 }, // 8213 |
| 15504 | { PseudoVSE16_V_MF2_MASK, VSE16_V, 0x7, 0x10 }, // 8214 |
| 15505 | { PseudoVSE32_V_M1, VSE32_V, 0x0, 0x20 }, // 8215 |
| 15506 | { PseudoVSE32_V_M1_MASK, VSE32_V, 0x0, 0x20 }, // 8216 |
| 15507 | { PseudoVSE32_V_M2, VSE32_V, 0x1, 0x20 }, // 8217 |
| 15508 | { PseudoVSE32_V_M2_MASK, VSE32_V, 0x1, 0x20 }, // 8218 |
| 15509 | { PseudoVSE32_V_M4, VSE32_V, 0x2, 0x20 }, // 8219 |
| 15510 | { PseudoVSE32_V_M4_MASK, VSE32_V, 0x2, 0x20 }, // 8220 |
| 15511 | { PseudoVSE32_V_M8, VSE32_V, 0x3, 0x20 }, // 8221 |
| 15512 | { PseudoVSE32_V_M8_MASK, VSE32_V, 0x3, 0x20 }, // 8222 |
| 15513 | { PseudoVSE32_V_MF2, VSE32_V, 0x7, 0x20 }, // 8223 |
| 15514 | { PseudoVSE32_V_MF2_MASK, VSE32_V, 0x7, 0x20 }, // 8224 |
| 15515 | { PseudoVSE64_V_M1, VSE64_V, 0x0, 0x40 }, // 8225 |
| 15516 | { PseudoVSE64_V_M1_MASK, VSE64_V, 0x0, 0x40 }, // 8226 |
| 15517 | { PseudoVSE64_V_M2, VSE64_V, 0x1, 0x40 }, // 8227 |
| 15518 | { PseudoVSE64_V_M2_MASK, VSE64_V, 0x1, 0x40 }, // 8228 |
| 15519 | { PseudoVSE64_V_M4, VSE64_V, 0x2, 0x40 }, // 8229 |
| 15520 | { PseudoVSE64_V_M4_MASK, VSE64_V, 0x2, 0x40 }, // 8230 |
| 15521 | { PseudoVSE64_V_M8, VSE64_V, 0x3, 0x40 }, // 8231 |
| 15522 | { PseudoVSE64_V_M8_MASK, VSE64_V, 0x3, 0x40 }, // 8232 |
| 15523 | { PseudoVSE8_V_M1, VSE8_V, 0x0, 0x8 }, // 8233 |
| 15524 | { PseudoVSE8_V_M1_MASK, VSE8_V, 0x0, 0x8 }, // 8234 |
| 15525 | { PseudoVSE8_V_M2, VSE8_V, 0x1, 0x8 }, // 8235 |
| 15526 | { PseudoVSE8_V_M2_MASK, VSE8_V, 0x1, 0x8 }, // 8236 |
| 15527 | { PseudoVSE8_V_M4, VSE8_V, 0x2, 0x8 }, // 8237 |
| 15528 | { PseudoVSE8_V_M4_MASK, VSE8_V, 0x2, 0x8 }, // 8238 |
| 15529 | { PseudoVSE8_V_M8, VSE8_V, 0x3, 0x8 }, // 8239 |
| 15530 | { PseudoVSE8_V_M8_MASK, VSE8_V, 0x3, 0x8 }, // 8240 |
| 15531 | { PseudoVSE8_V_MF8, VSE8_V, 0x5, 0x8 }, // 8241 |
| 15532 | { PseudoVSE8_V_MF8_MASK, VSE8_V, 0x5, 0x8 }, // 8242 |
| 15533 | { PseudoVSE8_V_MF4, VSE8_V, 0x6, 0x8 }, // 8243 |
| 15534 | { PseudoVSE8_V_MF4_MASK, VSE8_V, 0x6, 0x8 }, // 8244 |
| 15535 | { PseudoVSE8_V_MF2, VSE8_V, 0x7, 0x8 }, // 8245 |
| 15536 | { PseudoVSE8_V_MF2_MASK, VSE8_V, 0x7, 0x8 }, // 8246 |
| 15537 | { PseudoVSEXT_VF2_M1, VSEXT_VF2, 0x0, 0x0 }, // 8247 |
| 15538 | { PseudoVSEXT_VF2_M1_MASK, VSEXT_VF2, 0x0, 0x0 }, // 8248 |
| 15539 | { PseudoVSEXT_VF2_M2, VSEXT_VF2, 0x1, 0x0 }, // 8249 |
| 15540 | { PseudoVSEXT_VF2_M2_MASK, VSEXT_VF2, 0x1, 0x0 }, // 8250 |
| 15541 | { PseudoVSEXT_VF2_M4, VSEXT_VF2, 0x2, 0x0 }, // 8251 |
| 15542 | { PseudoVSEXT_VF2_M4_MASK, VSEXT_VF2, 0x2, 0x0 }, // 8252 |
| 15543 | { PseudoVSEXT_VF2_M8, VSEXT_VF2, 0x3, 0x0 }, // 8253 |
| 15544 | { PseudoVSEXT_VF2_M8_MASK, VSEXT_VF2, 0x3, 0x0 }, // 8254 |
| 15545 | { PseudoVSEXT_VF2_MF4, VSEXT_VF2, 0x6, 0x0 }, // 8255 |
| 15546 | { PseudoVSEXT_VF2_MF4_MASK, VSEXT_VF2, 0x6, 0x0 }, // 8256 |
| 15547 | { PseudoVSEXT_VF2_MF2, VSEXT_VF2, 0x7, 0x0 }, // 8257 |
| 15548 | { PseudoVSEXT_VF2_MF2_MASK, VSEXT_VF2, 0x7, 0x0 }, // 8258 |
| 15549 | { PseudoVSEXT_VF4_M1, VSEXT_VF4, 0x0, 0x0 }, // 8259 |
| 15550 | { PseudoVSEXT_VF4_M1_MASK, VSEXT_VF4, 0x0, 0x0 }, // 8260 |
| 15551 | { PseudoVSEXT_VF4_M2, VSEXT_VF4, 0x1, 0x0 }, // 8261 |
| 15552 | { PseudoVSEXT_VF4_M2_MASK, VSEXT_VF4, 0x1, 0x0 }, // 8262 |
| 15553 | { PseudoVSEXT_VF4_M4, VSEXT_VF4, 0x2, 0x0 }, // 8263 |
| 15554 | { PseudoVSEXT_VF4_M4_MASK, VSEXT_VF4, 0x2, 0x0 }, // 8264 |
| 15555 | { PseudoVSEXT_VF4_M8, VSEXT_VF4, 0x3, 0x0 }, // 8265 |
| 15556 | { PseudoVSEXT_VF4_M8_MASK, VSEXT_VF4, 0x3, 0x0 }, // 8266 |
| 15557 | { PseudoVSEXT_VF4_MF2, VSEXT_VF4, 0x7, 0x0 }, // 8267 |
| 15558 | { PseudoVSEXT_VF4_MF2_MASK, VSEXT_VF4, 0x7, 0x0 }, // 8268 |
| 15559 | { PseudoVSEXT_VF8_M1, VSEXT_VF8, 0x0, 0x0 }, // 8269 |
| 15560 | { PseudoVSEXT_VF8_M1_MASK, VSEXT_VF8, 0x0, 0x0 }, // 8270 |
| 15561 | { PseudoVSEXT_VF8_M2, VSEXT_VF8, 0x1, 0x0 }, // 8271 |
| 15562 | { PseudoVSEXT_VF8_M2_MASK, VSEXT_VF8, 0x1, 0x0 }, // 8272 |
| 15563 | { PseudoVSEXT_VF8_M4, VSEXT_VF8, 0x2, 0x0 }, // 8273 |
| 15564 | { PseudoVSEXT_VF8_M4_MASK, VSEXT_VF8, 0x2, 0x0 }, // 8274 |
| 15565 | { PseudoVSEXT_VF8_M8, VSEXT_VF8, 0x3, 0x0 }, // 8275 |
| 15566 | { PseudoVSEXT_VF8_M8_MASK, VSEXT_VF8, 0x3, 0x0 }, // 8276 |
| 15567 | { PseudoVSHA2CH_VV_M1, VSHA2CH_VV, 0x0, 0x0 }, // 8277 |
| 15568 | { PseudoVSHA2CH_VV_M2, VSHA2CH_VV, 0x1, 0x0 }, // 8278 |
| 15569 | { PseudoVSHA2CH_VV_M4, VSHA2CH_VV, 0x2, 0x0 }, // 8279 |
| 15570 | { PseudoVSHA2CH_VV_M8, VSHA2CH_VV, 0x3, 0x0 }, // 8280 |
| 15571 | { PseudoVSHA2CH_VV_MF2, VSHA2CH_VV, 0x7, 0x0 }, // 8281 |
| 15572 | { PseudoVSHA2CL_VV_M1, VSHA2CL_VV, 0x0, 0x0 }, // 8282 |
| 15573 | { PseudoVSHA2CL_VV_M2, VSHA2CL_VV, 0x1, 0x0 }, // 8283 |
| 15574 | { PseudoVSHA2CL_VV_M4, VSHA2CL_VV, 0x2, 0x0 }, // 8284 |
| 15575 | { PseudoVSHA2CL_VV_M8, VSHA2CL_VV, 0x3, 0x0 }, // 8285 |
| 15576 | { PseudoVSHA2CL_VV_MF2, VSHA2CL_VV, 0x7, 0x0 }, // 8286 |
| 15577 | { PseudoVSHA2MS_VV_M1, VSHA2MS_VV, 0x0, 0x0 }, // 8287 |
| 15578 | { PseudoVSHA2MS_VV_M2, VSHA2MS_VV, 0x1, 0x0 }, // 8288 |
| 15579 | { PseudoVSHA2MS_VV_M4, VSHA2MS_VV, 0x2, 0x0 }, // 8289 |
| 15580 | { PseudoVSHA2MS_VV_M8, VSHA2MS_VV, 0x3, 0x0 }, // 8290 |
| 15581 | { PseudoVSHA2MS_VV_MF2, VSHA2MS_VV, 0x7, 0x0 }, // 8291 |
| 15582 | { PseudoVSLIDE1DOWN_VX_M1, VSLIDE1DOWN_VX, 0x0, 0x0 }, // 8292 |
| 15583 | { PseudoVSLIDE1DOWN_VX_M1_MASK, VSLIDE1DOWN_VX, 0x0, 0x0 }, // 8293 |
| 15584 | { PseudoVSLIDE1DOWN_VX_M2, VSLIDE1DOWN_VX, 0x1, 0x0 }, // 8294 |
| 15585 | { PseudoVSLIDE1DOWN_VX_M2_MASK, VSLIDE1DOWN_VX, 0x1, 0x0 }, // 8295 |
| 15586 | { PseudoVSLIDE1DOWN_VX_M4, VSLIDE1DOWN_VX, 0x2, 0x0 }, // 8296 |
| 15587 | { PseudoVSLIDE1DOWN_VX_M4_MASK, VSLIDE1DOWN_VX, 0x2, 0x0 }, // 8297 |
| 15588 | { PseudoVSLIDE1DOWN_VX_M8, VSLIDE1DOWN_VX, 0x3, 0x0 }, // 8298 |
| 15589 | { PseudoVSLIDE1DOWN_VX_M8_MASK, VSLIDE1DOWN_VX, 0x3, 0x0 }, // 8299 |
| 15590 | { PseudoVSLIDE1DOWN_VX_MF8, VSLIDE1DOWN_VX, 0x5, 0x0 }, // 8300 |
| 15591 | { PseudoVSLIDE1DOWN_VX_MF8_MASK, VSLIDE1DOWN_VX, 0x5, 0x0 }, // 8301 |
| 15592 | { PseudoVSLIDE1DOWN_VX_MF4, VSLIDE1DOWN_VX, 0x6, 0x0 }, // 8302 |
| 15593 | { PseudoVSLIDE1DOWN_VX_MF4_MASK, VSLIDE1DOWN_VX, 0x6, 0x0 }, // 8303 |
| 15594 | { PseudoVSLIDE1DOWN_VX_MF2, VSLIDE1DOWN_VX, 0x7, 0x0 }, // 8304 |
| 15595 | { PseudoVSLIDE1DOWN_VX_MF2_MASK, VSLIDE1DOWN_VX, 0x7, 0x0 }, // 8305 |
| 15596 | { PseudoVSLIDE1UP_VX_M1, VSLIDE1UP_VX, 0x0, 0x0 }, // 8306 |
| 15597 | { PseudoVSLIDE1UP_VX_M1_MASK, VSLIDE1UP_VX, 0x0, 0x0 }, // 8307 |
| 15598 | { PseudoVSLIDE1UP_VX_M2, VSLIDE1UP_VX, 0x1, 0x0 }, // 8308 |
| 15599 | { PseudoVSLIDE1UP_VX_M2_MASK, VSLIDE1UP_VX, 0x1, 0x0 }, // 8309 |
| 15600 | { PseudoVSLIDE1UP_VX_M4, VSLIDE1UP_VX, 0x2, 0x0 }, // 8310 |
| 15601 | { PseudoVSLIDE1UP_VX_M4_MASK, VSLIDE1UP_VX, 0x2, 0x0 }, // 8311 |
| 15602 | { PseudoVSLIDE1UP_VX_M8, VSLIDE1UP_VX, 0x3, 0x0 }, // 8312 |
| 15603 | { PseudoVSLIDE1UP_VX_M8_MASK, VSLIDE1UP_VX, 0x3, 0x0 }, // 8313 |
| 15604 | { PseudoVSLIDE1UP_VX_MF8, VSLIDE1UP_VX, 0x5, 0x0 }, // 8314 |
| 15605 | { PseudoVSLIDE1UP_VX_MF8_MASK, VSLIDE1UP_VX, 0x5, 0x0 }, // 8315 |
| 15606 | { PseudoVSLIDE1UP_VX_MF4, VSLIDE1UP_VX, 0x6, 0x0 }, // 8316 |
| 15607 | { PseudoVSLIDE1UP_VX_MF4_MASK, VSLIDE1UP_VX, 0x6, 0x0 }, // 8317 |
| 15608 | { PseudoVSLIDE1UP_VX_MF2, VSLIDE1UP_VX, 0x7, 0x0 }, // 8318 |
| 15609 | { PseudoVSLIDE1UP_VX_MF2_MASK, VSLIDE1UP_VX, 0x7, 0x0 }, // 8319 |
| 15610 | { PseudoVSLIDEDOWN_VI_M1, VSLIDEDOWN_VI, 0x0, 0x0 }, // 8320 |
| 15611 | { PseudoVSLIDEDOWN_VI_M1_MASK, VSLIDEDOWN_VI, 0x0, 0x0 }, // 8321 |
| 15612 | { PseudoVSLIDEDOWN_VI_M2, VSLIDEDOWN_VI, 0x1, 0x0 }, // 8322 |
| 15613 | { PseudoVSLIDEDOWN_VI_M2_MASK, VSLIDEDOWN_VI, 0x1, 0x0 }, // 8323 |
| 15614 | { PseudoVSLIDEDOWN_VI_M4, VSLIDEDOWN_VI, 0x2, 0x0 }, // 8324 |
| 15615 | { PseudoVSLIDEDOWN_VI_M4_MASK, VSLIDEDOWN_VI, 0x2, 0x0 }, // 8325 |
| 15616 | { PseudoVSLIDEDOWN_VI_M8, VSLIDEDOWN_VI, 0x3, 0x0 }, // 8326 |
| 15617 | { PseudoVSLIDEDOWN_VI_M8_MASK, VSLIDEDOWN_VI, 0x3, 0x0 }, // 8327 |
| 15618 | { PseudoVSLIDEDOWN_VI_MF8, VSLIDEDOWN_VI, 0x5, 0x0 }, // 8328 |
| 15619 | { PseudoVSLIDEDOWN_VI_MF8_MASK, VSLIDEDOWN_VI, 0x5, 0x0 }, // 8329 |
| 15620 | { PseudoVSLIDEDOWN_VI_MF4, VSLIDEDOWN_VI, 0x6, 0x0 }, // 8330 |
| 15621 | { PseudoVSLIDEDOWN_VI_MF4_MASK, VSLIDEDOWN_VI, 0x6, 0x0 }, // 8331 |
| 15622 | { PseudoVSLIDEDOWN_VI_MF2, VSLIDEDOWN_VI, 0x7, 0x0 }, // 8332 |
| 15623 | { PseudoVSLIDEDOWN_VI_MF2_MASK, VSLIDEDOWN_VI, 0x7, 0x0 }, // 8333 |
| 15624 | { PseudoVSLIDEDOWN_VX_M1, VSLIDEDOWN_VX, 0x0, 0x0 }, // 8334 |
| 15625 | { PseudoVSLIDEDOWN_VX_M1_MASK, VSLIDEDOWN_VX, 0x0, 0x0 }, // 8335 |
| 15626 | { PseudoVSLIDEDOWN_VX_M2, VSLIDEDOWN_VX, 0x1, 0x0 }, // 8336 |
| 15627 | { PseudoVSLIDEDOWN_VX_M2_MASK, VSLIDEDOWN_VX, 0x1, 0x0 }, // 8337 |
| 15628 | { PseudoVSLIDEDOWN_VX_M4, VSLIDEDOWN_VX, 0x2, 0x0 }, // 8338 |
| 15629 | { PseudoVSLIDEDOWN_VX_M4_MASK, VSLIDEDOWN_VX, 0x2, 0x0 }, // 8339 |
| 15630 | { PseudoVSLIDEDOWN_VX_M8, VSLIDEDOWN_VX, 0x3, 0x0 }, // 8340 |
| 15631 | { PseudoVSLIDEDOWN_VX_M8_MASK, VSLIDEDOWN_VX, 0x3, 0x0 }, // 8341 |
| 15632 | { PseudoVSLIDEDOWN_VX_MF8, VSLIDEDOWN_VX, 0x5, 0x0 }, // 8342 |
| 15633 | { PseudoVSLIDEDOWN_VX_MF8_MASK, VSLIDEDOWN_VX, 0x5, 0x0 }, // 8343 |
| 15634 | { PseudoVSLIDEDOWN_VX_MF4, VSLIDEDOWN_VX, 0x6, 0x0 }, // 8344 |
| 15635 | { PseudoVSLIDEDOWN_VX_MF4_MASK, VSLIDEDOWN_VX, 0x6, 0x0 }, // 8345 |
| 15636 | { PseudoVSLIDEDOWN_VX_MF2, VSLIDEDOWN_VX, 0x7, 0x0 }, // 8346 |
| 15637 | { PseudoVSLIDEDOWN_VX_MF2_MASK, VSLIDEDOWN_VX, 0x7, 0x0 }, // 8347 |
| 15638 | { PseudoVSLIDEUP_VI_M1, VSLIDEUP_VI, 0x0, 0x0 }, // 8348 |
| 15639 | { PseudoVSLIDEUP_VI_M1_MASK, VSLIDEUP_VI, 0x0, 0x0 }, // 8349 |
| 15640 | { PseudoVSLIDEUP_VI_M2, VSLIDEUP_VI, 0x1, 0x0 }, // 8350 |
| 15641 | { PseudoVSLIDEUP_VI_M2_MASK, VSLIDEUP_VI, 0x1, 0x0 }, // 8351 |
| 15642 | { PseudoVSLIDEUP_VI_M4, VSLIDEUP_VI, 0x2, 0x0 }, // 8352 |
| 15643 | { PseudoVSLIDEUP_VI_M4_MASK, VSLIDEUP_VI, 0x2, 0x0 }, // 8353 |
| 15644 | { PseudoVSLIDEUP_VI_M8, VSLIDEUP_VI, 0x3, 0x0 }, // 8354 |
| 15645 | { PseudoVSLIDEUP_VI_M8_MASK, VSLIDEUP_VI, 0x3, 0x0 }, // 8355 |
| 15646 | { PseudoVSLIDEUP_VI_MF8, VSLIDEUP_VI, 0x5, 0x0 }, // 8356 |
| 15647 | { PseudoVSLIDEUP_VI_MF8_MASK, VSLIDEUP_VI, 0x5, 0x0 }, // 8357 |
| 15648 | { PseudoVSLIDEUP_VI_MF4, VSLIDEUP_VI, 0x6, 0x0 }, // 8358 |
| 15649 | { PseudoVSLIDEUP_VI_MF4_MASK, VSLIDEUP_VI, 0x6, 0x0 }, // 8359 |
| 15650 | { PseudoVSLIDEUP_VI_MF2, VSLIDEUP_VI, 0x7, 0x0 }, // 8360 |
| 15651 | { PseudoVSLIDEUP_VI_MF2_MASK, VSLIDEUP_VI, 0x7, 0x0 }, // 8361 |
| 15652 | { PseudoVSLIDEUP_VX_M1, VSLIDEUP_VX, 0x0, 0x0 }, // 8362 |
| 15653 | { PseudoVSLIDEUP_VX_M1_MASK, VSLIDEUP_VX, 0x0, 0x0 }, // 8363 |
| 15654 | { PseudoVSLIDEUP_VX_M2, VSLIDEUP_VX, 0x1, 0x0 }, // 8364 |
| 15655 | { PseudoVSLIDEUP_VX_M2_MASK, VSLIDEUP_VX, 0x1, 0x0 }, // 8365 |
| 15656 | { PseudoVSLIDEUP_VX_M4, VSLIDEUP_VX, 0x2, 0x0 }, // 8366 |
| 15657 | { PseudoVSLIDEUP_VX_M4_MASK, VSLIDEUP_VX, 0x2, 0x0 }, // 8367 |
| 15658 | { PseudoVSLIDEUP_VX_M8, VSLIDEUP_VX, 0x3, 0x0 }, // 8368 |
| 15659 | { PseudoVSLIDEUP_VX_M8_MASK, VSLIDEUP_VX, 0x3, 0x0 }, // 8369 |
| 15660 | { PseudoVSLIDEUP_VX_MF8, VSLIDEUP_VX, 0x5, 0x0 }, // 8370 |
| 15661 | { PseudoVSLIDEUP_VX_MF8_MASK, VSLIDEUP_VX, 0x5, 0x0 }, // 8371 |
| 15662 | { PseudoVSLIDEUP_VX_MF4, VSLIDEUP_VX, 0x6, 0x0 }, // 8372 |
| 15663 | { PseudoVSLIDEUP_VX_MF4_MASK, VSLIDEUP_VX, 0x6, 0x0 }, // 8373 |
| 15664 | { PseudoVSLIDEUP_VX_MF2, VSLIDEUP_VX, 0x7, 0x0 }, // 8374 |
| 15665 | { PseudoVSLIDEUP_VX_MF2_MASK, VSLIDEUP_VX, 0x7, 0x0 }, // 8375 |
| 15666 | { PseudoVSLL_VI_M1, VSLL_VI, 0x0, 0x0 }, // 8376 |
| 15667 | { PseudoVSLL_VI_M1_MASK, VSLL_VI, 0x0, 0x0 }, // 8377 |
| 15668 | { PseudoVSLL_VI_M2, VSLL_VI, 0x1, 0x0 }, // 8378 |
| 15669 | { PseudoVSLL_VI_M2_MASK, VSLL_VI, 0x1, 0x0 }, // 8379 |
| 15670 | { PseudoVSLL_VI_M4, VSLL_VI, 0x2, 0x0 }, // 8380 |
| 15671 | { PseudoVSLL_VI_M4_MASK, VSLL_VI, 0x2, 0x0 }, // 8381 |
| 15672 | { PseudoVSLL_VI_M8, VSLL_VI, 0x3, 0x0 }, // 8382 |
| 15673 | { PseudoVSLL_VI_M8_MASK, VSLL_VI, 0x3, 0x0 }, // 8383 |
| 15674 | { PseudoVSLL_VI_MF8, VSLL_VI, 0x5, 0x0 }, // 8384 |
| 15675 | { PseudoVSLL_VI_MF8_MASK, VSLL_VI, 0x5, 0x0 }, // 8385 |
| 15676 | { PseudoVSLL_VI_MF4, VSLL_VI, 0x6, 0x0 }, // 8386 |
| 15677 | { PseudoVSLL_VI_MF4_MASK, VSLL_VI, 0x6, 0x0 }, // 8387 |
| 15678 | { PseudoVSLL_VI_MF2, VSLL_VI, 0x7, 0x0 }, // 8388 |
| 15679 | { PseudoVSLL_VI_MF2_MASK, VSLL_VI, 0x7, 0x0 }, // 8389 |
| 15680 | { PseudoVSLL_VV_M1, VSLL_VV, 0x0, 0x0 }, // 8390 |
| 15681 | { PseudoVSLL_VV_M1_MASK, VSLL_VV, 0x0, 0x0 }, // 8391 |
| 15682 | { PseudoVSLL_VV_M2, VSLL_VV, 0x1, 0x0 }, // 8392 |
| 15683 | { PseudoVSLL_VV_M2_MASK, VSLL_VV, 0x1, 0x0 }, // 8393 |
| 15684 | { PseudoVSLL_VV_M4, VSLL_VV, 0x2, 0x0 }, // 8394 |
| 15685 | { PseudoVSLL_VV_M4_MASK, VSLL_VV, 0x2, 0x0 }, // 8395 |
| 15686 | { PseudoVSLL_VV_M8, VSLL_VV, 0x3, 0x0 }, // 8396 |
| 15687 | { PseudoVSLL_VV_M8_MASK, VSLL_VV, 0x3, 0x0 }, // 8397 |
| 15688 | { PseudoVSLL_VV_MF8, VSLL_VV, 0x5, 0x0 }, // 8398 |
| 15689 | { PseudoVSLL_VV_MF8_MASK, VSLL_VV, 0x5, 0x0 }, // 8399 |
| 15690 | { PseudoVSLL_VV_MF4, VSLL_VV, 0x6, 0x0 }, // 8400 |
| 15691 | { PseudoVSLL_VV_MF4_MASK, VSLL_VV, 0x6, 0x0 }, // 8401 |
| 15692 | { PseudoVSLL_VV_MF2, VSLL_VV, 0x7, 0x0 }, // 8402 |
| 15693 | { PseudoVSLL_VV_MF2_MASK, VSLL_VV, 0x7, 0x0 }, // 8403 |
| 15694 | { PseudoVSLL_VX_M1, VSLL_VX, 0x0, 0x0 }, // 8404 |
| 15695 | { PseudoVSLL_VX_M1_MASK, VSLL_VX, 0x0, 0x0 }, // 8405 |
| 15696 | { PseudoVSLL_VX_M2, VSLL_VX, 0x1, 0x0 }, // 8406 |
| 15697 | { PseudoVSLL_VX_M2_MASK, VSLL_VX, 0x1, 0x0 }, // 8407 |
| 15698 | { PseudoVSLL_VX_M4, VSLL_VX, 0x2, 0x0 }, // 8408 |
| 15699 | { PseudoVSLL_VX_M4_MASK, VSLL_VX, 0x2, 0x0 }, // 8409 |
| 15700 | { PseudoVSLL_VX_M8, VSLL_VX, 0x3, 0x0 }, // 8410 |
| 15701 | { PseudoVSLL_VX_M8_MASK, VSLL_VX, 0x3, 0x0 }, // 8411 |
| 15702 | { PseudoVSLL_VX_MF8, VSLL_VX, 0x5, 0x0 }, // 8412 |
| 15703 | { PseudoVSLL_VX_MF8_MASK, VSLL_VX, 0x5, 0x0 }, // 8413 |
| 15704 | { PseudoVSLL_VX_MF4, VSLL_VX, 0x6, 0x0 }, // 8414 |
| 15705 | { PseudoVSLL_VX_MF4_MASK, VSLL_VX, 0x6, 0x0 }, // 8415 |
| 15706 | { PseudoVSLL_VX_MF2, VSLL_VX, 0x7, 0x0 }, // 8416 |
| 15707 | { PseudoVSLL_VX_MF2_MASK, VSLL_VX, 0x7, 0x0 }, // 8417 |
| 15708 | { PseudoVSM3C_VI_M1, VSM3C_VI, 0x0, 0x0 }, // 8418 |
| 15709 | { PseudoVSM3C_VI_M2, VSM3C_VI, 0x1, 0x0 }, // 8419 |
| 15710 | { PseudoVSM3C_VI_M4, VSM3C_VI, 0x2, 0x0 }, // 8420 |
| 15711 | { PseudoVSM3C_VI_M8, VSM3C_VI, 0x3, 0x0 }, // 8421 |
| 15712 | { PseudoVSM3C_VI_MF2, VSM3C_VI, 0x7, 0x0 }, // 8422 |
| 15713 | { PseudoVSM3ME_VV_M1, VSM3ME_VV, 0x0, 0x0 }, // 8423 |
| 15714 | { PseudoVSM3ME_VV_M2, VSM3ME_VV, 0x1, 0x0 }, // 8424 |
| 15715 | { PseudoVSM3ME_VV_M4, VSM3ME_VV, 0x2, 0x0 }, // 8425 |
| 15716 | { PseudoVSM3ME_VV_M8, VSM3ME_VV, 0x3, 0x0 }, // 8426 |
| 15717 | { PseudoVSM3ME_VV_MF2, VSM3ME_VV, 0x7, 0x0 }, // 8427 |
| 15718 | { PseudoVSM4K_VI_M1, VSM4K_VI, 0x0, 0x0 }, // 8428 |
| 15719 | { PseudoVSM4K_VI_M2, VSM4K_VI, 0x1, 0x0 }, // 8429 |
| 15720 | { PseudoVSM4K_VI_M4, VSM4K_VI, 0x2, 0x0 }, // 8430 |
| 15721 | { PseudoVSM4K_VI_M8, VSM4K_VI, 0x3, 0x0 }, // 8431 |
| 15722 | { PseudoVSM4K_VI_MF2, VSM4K_VI, 0x7, 0x0 }, // 8432 |
| 15723 | { PseudoVSM4R_VS_M1_M1, VSM4R_VS, 0x0, 0x0 }, // 8433 |
| 15724 | { PseudoVSM4R_VS_M1_MF2, VSM4R_VS, 0x0, 0x0 }, // 8434 |
| 15725 | { PseudoVSM4R_VS_M1_MF4, VSM4R_VS, 0x0, 0x0 }, // 8435 |
| 15726 | { PseudoVSM4R_VS_M1_MF8, VSM4R_VS, 0x0, 0x0 }, // 8436 |
| 15727 | { PseudoVSM4R_VS_M2_M1, VSM4R_VS, 0x1, 0x0 }, // 8437 |
| 15728 | { PseudoVSM4R_VS_M2_M2, VSM4R_VS, 0x1, 0x0 }, // 8438 |
| 15729 | { PseudoVSM4R_VS_M2_MF2, VSM4R_VS, 0x1, 0x0 }, // 8439 |
| 15730 | { PseudoVSM4R_VS_M2_MF4, VSM4R_VS, 0x1, 0x0 }, // 8440 |
| 15731 | { PseudoVSM4R_VS_M2_MF8, VSM4R_VS, 0x1, 0x0 }, // 8441 |
| 15732 | { PseudoVSM4R_VS_M4_M1, VSM4R_VS, 0x2, 0x0 }, // 8442 |
| 15733 | { PseudoVSM4R_VS_M4_M2, VSM4R_VS, 0x2, 0x0 }, // 8443 |
| 15734 | { PseudoVSM4R_VS_M4_M4, VSM4R_VS, 0x2, 0x0 }, // 8444 |
| 15735 | { PseudoVSM4R_VS_M4_MF2, VSM4R_VS, 0x2, 0x0 }, // 8445 |
| 15736 | { PseudoVSM4R_VS_M4_MF4, VSM4R_VS, 0x2, 0x0 }, // 8446 |
| 15737 | { PseudoVSM4R_VS_M4_MF8, VSM4R_VS, 0x2, 0x0 }, // 8447 |
| 15738 | { PseudoVSM4R_VS_M8_M1, VSM4R_VS, 0x3, 0x0 }, // 8448 |
| 15739 | { PseudoVSM4R_VS_M8_M2, VSM4R_VS, 0x3, 0x0 }, // 8449 |
| 15740 | { PseudoVSM4R_VS_M8_M4, VSM4R_VS, 0x3, 0x0 }, // 8450 |
| 15741 | { PseudoVSM4R_VS_M8_MF2, VSM4R_VS, 0x3, 0x0 }, // 8451 |
| 15742 | { PseudoVSM4R_VS_M8_MF4, VSM4R_VS, 0x3, 0x0 }, // 8452 |
| 15743 | { PseudoVSM4R_VS_M8_MF8, VSM4R_VS, 0x3, 0x0 }, // 8453 |
| 15744 | { PseudoVSM4R_VS_MF2_MF2, VSM4R_VS, 0x7, 0x0 }, // 8454 |
| 15745 | { PseudoVSM4R_VS_MF2_MF4, VSM4R_VS, 0x7, 0x0 }, // 8455 |
| 15746 | { PseudoVSM4R_VS_MF2_MF8, VSM4R_VS, 0x7, 0x0 }, // 8456 |
| 15747 | { PseudoVSM4R_VV_M1, VSM4R_VV, 0x0, 0x0 }, // 8457 |
| 15748 | { PseudoVSM4R_VV_M2, VSM4R_VV, 0x1, 0x0 }, // 8458 |
| 15749 | { PseudoVSM4R_VV_M4, VSM4R_VV, 0x2, 0x0 }, // 8459 |
| 15750 | { PseudoVSM4R_VV_M8, VSM4R_VV, 0x3, 0x0 }, // 8460 |
| 15751 | { PseudoVSM4R_VV_MF2, VSM4R_VV, 0x7, 0x0 }, // 8461 |
| 15752 | { PseudoVSMUL_VV_M1, VSMUL_VV, 0x0, 0x0 }, // 8462 |
| 15753 | { PseudoVSMUL_VV_M1_MASK, VSMUL_VV, 0x0, 0x0 }, // 8463 |
| 15754 | { PseudoVSMUL_VV_M2, VSMUL_VV, 0x1, 0x0 }, // 8464 |
| 15755 | { PseudoVSMUL_VV_M2_MASK, VSMUL_VV, 0x1, 0x0 }, // 8465 |
| 15756 | { PseudoVSMUL_VV_M4, VSMUL_VV, 0x2, 0x0 }, // 8466 |
| 15757 | { PseudoVSMUL_VV_M4_MASK, VSMUL_VV, 0x2, 0x0 }, // 8467 |
| 15758 | { PseudoVSMUL_VV_M8, VSMUL_VV, 0x3, 0x0 }, // 8468 |
| 15759 | { PseudoVSMUL_VV_M8_MASK, VSMUL_VV, 0x3, 0x0 }, // 8469 |
| 15760 | { PseudoVSMUL_VV_MF8, VSMUL_VV, 0x5, 0x0 }, // 8470 |
| 15761 | { PseudoVSMUL_VV_MF8_MASK, VSMUL_VV, 0x5, 0x0 }, // 8471 |
| 15762 | { PseudoVSMUL_VV_MF4, VSMUL_VV, 0x6, 0x0 }, // 8472 |
| 15763 | { PseudoVSMUL_VV_MF4_MASK, VSMUL_VV, 0x6, 0x0 }, // 8473 |
| 15764 | { PseudoVSMUL_VV_MF2, VSMUL_VV, 0x7, 0x0 }, // 8474 |
| 15765 | { PseudoVSMUL_VV_MF2_MASK, VSMUL_VV, 0x7, 0x0 }, // 8475 |
| 15766 | { PseudoVSMUL_VX_M1, VSMUL_VX, 0x0, 0x0 }, // 8476 |
| 15767 | { PseudoVSMUL_VX_M1_MASK, VSMUL_VX, 0x0, 0x0 }, // 8477 |
| 15768 | { PseudoVSMUL_VX_M2, VSMUL_VX, 0x1, 0x0 }, // 8478 |
| 15769 | { PseudoVSMUL_VX_M2_MASK, VSMUL_VX, 0x1, 0x0 }, // 8479 |
| 15770 | { PseudoVSMUL_VX_M4, VSMUL_VX, 0x2, 0x0 }, // 8480 |
| 15771 | { PseudoVSMUL_VX_M4_MASK, VSMUL_VX, 0x2, 0x0 }, // 8481 |
| 15772 | { PseudoVSMUL_VX_M8, VSMUL_VX, 0x3, 0x0 }, // 8482 |
| 15773 | { PseudoVSMUL_VX_M8_MASK, VSMUL_VX, 0x3, 0x0 }, // 8483 |
| 15774 | { PseudoVSMUL_VX_MF8, VSMUL_VX, 0x5, 0x0 }, // 8484 |
| 15775 | { PseudoVSMUL_VX_MF8_MASK, VSMUL_VX, 0x5, 0x0 }, // 8485 |
| 15776 | { PseudoVSMUL_VX_MF4, VSMUL_VX, 0x6, 0x0 }, // 8486 |
| 15777 | { PseudoVSMUL_VX_MF4_MASK, VSMUL_VX, 0x6, 0x0 }, // 8487 |
| 15778 | { PseudoVSMUL_VX_MF2, VSMUL_VX, 0x7, 0x0 }, // 8488 |
| 15779 | { PseudoVSMUL_VX_MF2_MASK, VSMUL_VX, 0x7, 0x0 }, // 8489 |
| 15780 | { PseudoVSM_V_B8, VSM_V, 0x0, 0x0 }, // 8490 |
| 15781 | { PseudoVSM_V_B16, VSM_V, 0x1, 0x0 }, // 8491 |
| 15782 | { PseudoVSM_V_B32, VSM_V, 0x2, 0x0 }, // 8492 |
| 15783 | { PseudoVSM_V_B64, VSM_V, 0x3, 0x0 }, // 8493 |
| 15784 | { PseudoVSM_V_B1, VSM_V, 0x5, 0x0 }, // 8494 |
| 15785 | { PseudoVSM_V_B2, VSM_V, 0x6, 0x0 }, // 8495 |
| 15786 | { PseudoVSM_V_B4, VSM_V, 0x7, 0x0 }, // 8496 |
| 15787 | { PseudoVSOXEI16_V_M1_M1, VSOXEI16_V, 0x0, 0x0 }, // 8497 |
| 15788 | { PseudoVSOXEI16_V_M1_M1_MASK, VSOXEI16_V, 0x0, 0x0 }, // 8498 |
| 15789 | { PseudoVSOXEI16_V_M2_M1, VSOXEI16_V, 0x0, 0x0 }, // 8499 |
| 15790 | { PseudoVSOXEI16_V_M2_M1_MASK, VSOXEI16_V, 0x0, 0x0 }, // 8500 |
| 15791 | { PseudoVSOXEI16_V_MF2_M1, VSOXEI16_V, 0x0, 0x0 }, // 8501 |
| 15792 | { PseudoVSOXEI16_V_MF2_M1_MASK, VSOXEI16_V, 0x0, 0x0 }, // 8502 |
| 15793 | { PseudoVSOXEI16_V_MF4_M1, VSOXEI16_V, 0x0, 0x0 }, // 8503 |
| 15794 | { PseudoVSOXEI16_V_MF4_M1_MASK, VSOXEI16_V, 0x0, 0x0 }, // 8504 |
| 15795 | { PseudoVSOXEI16_V_M1_M2, VSOXEI16_V, 0x1, 0x0 }, // 8505 |
| 15796 | { PseudoVSOXEI16_V_M1_M2_MASK, VSOXEI16_V, 0x1, 0x0 }, // 8506 |
| 15797 | { PseudoVSOXEI16_V_M2_M2, VSOXEI16_V, 0x1, 0x0 }, // 8507 |
| 15798 | { PseudoVSOXEI16_V_M2_M2_MASK, VSOXEI16_V, 0x1, 0x0 }, // 8508 |
| 15799 | { PseudoVSOXEI16_V_M4_M2, VSOXEI16_V, 0x1, 0x0 }, // 8509 |
| 15800 | { PseudoVSOXEI16_V_M4_M2_MASK, VSOXEI16_V, 0x1, 0x0 }, // 8510 |
| 15801 | { PseudoVSOXEI16_V_MF2_M2, VSOXEI16_V, 0x1, 0x0 }, // 8511 |
| 15802 | { PseudoVSOXEI16_V_MF2_M2_MASK, VSOXEI16_V, 0x1, 0x0 }, // 8512 |
| 15803 | { PseudoVSOXEI16_V_M1_M4, VSOXEI16_V, 0x2, 0x0 }, // 8513 |
| 15804 | { PseudoVSOXEI16_V_M1_M4_MASK, VSOXEI16_V, 0x2, 0x0 }, // 8514 |
| 15805 | { PseudoVSOXEI16_V_M2_M4, VSOXEI16_V, 0x2, 0x0 }, // 8515 |
| 15806 | { PseudoVSOXEI16_V_M2_M4_MASK, VSOXEI16_V, 0x2, 0x0 }, // 8516 |
| 15807 | { PseudoVSOXEI16_V_M4_M4, VSOXEI16_V, 0x2, 0x0 }, // 8517 |
| 15808 | { PseudoVSOXEI16_V_M4_M4_MASK, VSOXEI16_V, 0x2, 0x0 }, // 8518 |
| 15809 | { PseudoVSOXEI16_V_M8_M4, VSOXEI16_V, 0x2, 0x0 }, // 8519 |
| 15810 | { PseudoVSOXEI16_V_M8_M4_MASK, VSOXEI16_V, 0x2, 0x0 }, // 8520 |
| 15811 | { PseudoVSOXEI16_V_M2_M8, VSOXEI16_V, 0x3, 0x0 }, // 8521 |
| 15812 | { PseudoVSOXEI16_V_M2_M8_MASK, VSOXEI16_V, 0x3, 0x0 }, // 8522 |
| 15813 | { PseudoVSOXEI16_V_M4_M8, VSOXEI16_V, 0x3, 0x0 }, // 8523 |
| 15814 | { PseudoVSOXEI16_V_M4_M8_MASK, VSOXEI16_V, 0x3, 0x0 }, // 8524 |
| 15815 | { PseudoVSOXEI16_V_M8_M8, VSOXEI16_V, 0x3, 0x0 }, // 8525 |
| 15816 | { PseudoVSOXEI16_V_M8_M8_MASK, VSOXEI16_V, 0x3, 0x0 }, // 8526 |
| 15817 | { PseudoVSOXEI16_V_MF4_MF8, VSOXEI16_V, 0x5, 0x0 }, // 8527 |
| 15818 | { PseudoVSOXEI16_V_MF4_MF8_MASK, VSOXEI16_V, 0x5, 0x0 }, // 8528 |
| 15819 | { PseudoVSOXEI16_V_MF2_MF4, VSOXEI16_V, 0x6, 0x0 }, // 8529 |
| 15820 | { PseudoVSOXEI16_V_MF2_MF4_MASK, VSOXEI16_V, 0x6, 0x0 }, // 8530 |
| 15821 | { PseudoVSOXEI16_V_MF4_MF4, VSOXEI16_V, 0x6, 0x0 }, // 8531 |
| 15822 | { PseudoVSOXEI16_V_MF4_MF4_MASK, VSOXEI16_V, 0x6, 0x0 }, // 8532 |
| 15823 | { PseudoVSOXEI16_V_M1_MF2, VSOXEI16_V, 0x7, 0x0 }, // 8533 |
| 15824 | { PseudoVSOXEI16_V_M1_MF2_MASK, VSOXEI16_V, 0x7, 0x0 }, // 8534 |
| 15825 | { PseudoVSOXEI16_V_MF2_MF2, VSOXEI16_V, 0x7, 0x0 }, // 8535 |
| 15826 | { PseudoVSOXEI16_V_MF2_MF2_MASK, VSOXEI16_V, 0x7, 0x0 }, // 8536 |
| 15827 | { PseudoVSOXEI16_V_MF4_MF2, VSOXEI16_V, 0x7, 0x0 }, // 8537 |
| 15828 | { PseudoVSOXEI16_V_MF4_MF2_MASK, VSOXEI16_V, 0x7, 0x0 }, // 8538 |
| 15829 | { PseudoVSOXEI32_V_M1_M1, VSOXEI32_V, 0x0, 0x0 }, // 8539 |
| 15830 | { PseudoVSOXEI32_V_M1_M1_MASK, VSOXEI32_V, 0x0, 0x0 }, // 8540 |
| 15831 | { PseudoVSOXEI32_V_M2_M1, VSOXEI32_V, 0x0, 0x0 }, // 8541 |
| 15832 | { PseudoVSOXEI32_V_M2_M1_MASK, VSOXEI32_V, 0x0, 0x0 }, // 8542 |
| 15833 | { PseudoVSOXEI32_V_M4_M1, VSOXEI32_V, 0x0, 0x0 }, // 8543 |
| 15834 | { PseudoVSOXEI32_V_M4_M1_MASK, VSOXEI32_V, 0x0, 0x0 }, // 8544 |
| 15835 | { PseudoVSOXEI32_V_MF2_M1, VSOXEI32_V, 0x0, 0x0 }, // 8545 |
| 15836 | { PseudoVSOXEI32_V_MF2_M1_MASK, VSOXEI32_V, 0x0, 0x0 }, // 8546 |
| 15837 | { PseudoVSOXEI32_V_M1_M2, VSOXEI32_V, 0x1, 0x0 }, // 8547 |
| 15838 | { PseudoVSOXEI32_V_M1_M2_MASK, VSOXEI32_V, 0x1, 0x0 }, // 8548 |
| 15839 | { PseudoVSOXEI32_V_M2_M2, VSOXEI32_V, 0x1, 0x0 }, // 8549 |
| 15840 | { PseudoVSOXEI32_V_M2_M2_MASK, VSOXEI32_V, 0x1, 0x0 }, // 8550 |
| 15841 | { PseudoVSOXEI32_V_M4_M2, VSOXEI32_V, 0x1, 0x0 }, // 8551 |
| 15842 | { PseudoVSOXEI32_V_M4_M2_MASK, VSOXEI32_V, 0x1, 0x0 }, // 8552 |
| 15843 | { PseudoVSOXEI32_V_M8_M2, VSOXEI32_V, 0x1, 0x0 }, // 8553 |
| 15844 | { PseudoVSOXEI32_V_M8_M2_MASK, VSOXEI32_V, 0x1, 0x0 }, // 8554 |
| 15845 | { PseudoVSOXEI32_V_M2_M4, VSOXEI32_V, 0x2, 0x0 }, // 8555 |
| 15846 | { PseudoVSOXEI32_V_M2_M4_MASK, VSOXEI32_V, 0x2, 0x0 }, // 8556 |
| 15847 | { PseudoVSOXEI32_V_M4_M4, VSOXEI32_V, 0x2, 0x0 }, // 8557 |
| 15848 | { PseudoVSOXEI32_V_M4_M4_MASK, VSOXEI32_V, 0x2, 0x0 }, // 8558 |
| 15849 | { PseudoVSOXEI32_V_M8_M4, VSOXEI32_V, 0x2, 0x0 }, // 8559 |
| 15850 | { PseudoVSOXEI32_V_M8_M4_MASK, VSOXEI32_V, 0x2, 0x0 }, // 8560 |
| 15851 | { PseudoVSOXEI32_V_M4_M8, VSOXEI32_V, 0x3, 0x0 }, // 8561 |
| 15852 | { PseudoVSOXEI32_V_M4_M8_MASK, VSOXEI32_V, 0x3, 0x0 }, // 8562 |
| 15853 | { PseudoVSOXEI32_V_M8_M8, VSOXEI32_V, 0x3, 0x0 }, // 8563 |
| 15854 | { PseudoVSOXEI32_V_M8_M8_MASK, VSOXEI32_V, 0x3, 0x0 }, // 8564 |
| 15855 | { PseudoVSOXEI32_V_MF2_MF8, VSOXEI32_V, 0x5, 0x0 }, // 8565 |
| 15856 | { PseudoVSOXEI32_V_MF2_MF8_MASK, VSOXEI32_V, 0x5, 0x0 }, // 8566 |
| 15857 | { PseudoVSOXEI32_V_M1_MF4, VSOXEI32_V, 0x6, 0x0 }, // 8567 |
| 15858 | { PseudoVSOXEI32_V_M1_MF4_MASK, VSOXEI32_V, 0x6, 0x0 }, // 8568 |
| 15859 | { PseudoVSOXEI32_V_MF2_MF4, VSOXEI32_V, 0x6, 0x0 }, // 8569 |
| 15860 | { PseudoVSOXEI32_V_MF2_MF4_MASK, VSOXEI32_V, 0x6, 0x0 }, // 8570 |
| 15861 | { PseudoVSOXEI32_V_M1_MF2, VSOXEI32_V, 0x7, 0x0 }, // 8571 |
| 15862 | { PseudoVSOXEI32_V_M1_MF2_MASK, VSOXEI32_V, 0x7, 0x0 }, // 8572 |
| 15863 | { PseudoVSOXEI32_V_M2_MF2, VSOXEI32_V, 0x7, 0x0 }, // 8573 |
| 15864 | { PseudoVSOXEI32_V_M2_MF2_MASK, VSOXEI32_V, 0x7, 0x0 }, // 8574 |
| 15865 | { PseudoVSOXEI32_V_MF2_MF2, VSOXEI32_V, 0x7, 0x0 }, // 8575 |
| 15866 | { PseudoVSOXEI32_V_MF2_MF2_MASK, VSOXEI32_V, 0x7, 0x0 }, // 8576 |
| 15867 | { PseudoVSOXEI64_V_M1_M1, VSOXEI64_V, 0x0, 0x0 }, // 8577 |
| 15868 | { PseudoVSOXEI64_V_M1_M1_MASK, VSOXEI64_V, 0x0, 0x0 }, // 8578 |
| 15869 | { PseudoVSOXEI64_V_M2_M1, VSOXEI64_V, 0x0, 0x0 }, // 8579 |
| 15870 | { PseudoVSOXEI64_V_M2_M1_MASK, VSOXEI64_V, 0x0, 0x0 }, // 8580 |
| 15871 | { PseudoVSOXEI64_V_M4_M1, VSOXEI64_V, 0x0, 0x0 }, // 8581 |
| 15872 | { PseudoVSOXEI64_V_M4_M1_MASK, VSOXEI64_V, 0x0, 0x0 }, // 8582 |
| 15873 | { PseudoVSOXEI64_V_M8_M1, VSOXEI64_V, 0x0, 0x0 }, // 8583 |
| 15874 | { PseudoVSOXEI64_V_M8_M1_MASK, VSOXEI64_V, 0x0, 0x0 }, // 8584 |
| 15875 | { PseudoVSOXEI64_V_M2_M2, VSOXEI64_V, 0x1, 0x0 }, // 8585 |
| 15876 | { PseudoVSOXEI64_V_M2_M2_MASK, VSOXEI64_V, 0x1, 0x0 }, // 8586 |
| 15877 | { PseudoVSOXEI64_V_M4_M2, VSOXEI64_V, 0x1, 0x0 }, // 8587 |
| 15878 | { PseudoVSOXEI64_V_M4_M2_MASK, VSOXEI64_V, 0x1, 0x0 }, // 8588 |
| 15879 | { PseudoVSOXEI64_V_M8_M2, VSOXEI64_V, 0x1, 0x0 }, // 8589 |
| 15880 | { PseudoVSOXEI64_V_M8_M2_MASK, VSOXEI64_V, 0x1, 0x0 }, // 8590 |
| 15881 | { PseudoVSOXEI64_V_M4_M4, VSOXEI64_V, 0x2, 0x0 }, // 8591 |
| 15882 | { PseudoVSOXEI64_V_M4_M4_MASK, VSOXEI64_V, 0x2, 0x0 }, // 8592 |
| 15883 | { PseudoVSOXEI64_V_M8_M4, VSOXEI64_V, 0x2, 0x0 }, // 8593 |
| 15884 | { PseudoVSOXEI64_V_M8_M4_MASK, VSOXEI64_V, 0x2, 0x0 }, // 8594 |
| 15885 | { PseudoVSOXEI64_V_M8_M8, VSOXEI64_V, 0x3, 0x0 }, // 8595 |
| 15886 | { PseudoVSOXEI64_V_M8_M8_MASK, VSOXEI64_V, 0x3, 0x0 }, // 8596 |
| 15887 | { PseudoVSOXEI64_V_M1_MF8, VSOXEI64_V, 0x5, 0x0 }, // 8597 |
| 15888 | { PseudoVSOXEI64_V_M1_MF8_MASK, VSOXEI64_V, 0x5, 0x0 }, // 8598 |
| 15889 | { PseudoVSOXEI64_V_M1_MF4, VSOXEI64_V, 0x6, 0x0 }, // 8599 |
| 15890 | { PseudoVSOXEI64_V_M1_MF4_MASK, VSOXEI64_V, 0x6, 0x0 }, // 8600 |
| 15891 | { PseudoVSOXEI64_V_M2_MF4, VSOXEI64_V, 0x6, 0x0 }, // 8601 |
| 15892 | { PseudoVSOXEI64_V_M2_MF4_MASK, VSOXEI64_V, 0x6, 0x0 }, // 8602 |
| 15893 | { PseudoVSOXEI64_V_M1_MF2, VSOXEI64_V, 0x7, 0x0 }, // 8603 |
| 15894 | { PseudoVSOXEI64_V_M1_MF2_MASK, VSOXEI64_V, 0x7, 0x0 }, // 8604 |
| 15895 | { PseudoVSOXEI64_V_M2_MF2, VSOXEI64_V, 0x7, 0x0 }, // 8605 |
| 15896 | { PseudoVSOXEI64_V_M2_MF2_MASK, VSOXEI64_V, 0x7, 0x0 }, // 8606 |
| 15897 | { PseudoVSOXEI64_V_M4_MF2, VSOXEI64_V, 0x7, 0x0 }, // 8607 |
| 15898 | { PseudoVSOXEI64_V_M4_MF2_MASK, VSOXEI64_V, 0x7, 0x0 }, // 8608 |
| 15899 | { PseudoVSOXEI8_V_M1_M1, VSOXEI8_V, 0x0, 0x0 }, // 8609 |
| 15900 | { PseudoVSOXEI8_V_M1_M1_MASK, VSOXEI8_V, 0x0, 0x0 }, // 8610 |
| 15901 | { PseudoVSOXEI8_V_MF2_M1, VSOXEI8_V, 0x0, 0x0 }, // 8611 |
| 15902 | { PseudoVSOXEI8_V_MF2_M1_MASK, VSOXEI8_V, 0x0, 0x0 }, // 8612 |
| 15903 | { PseudoVSOXEI8_V_MF4_M1, VSOXEI8_V, 0x0, 0x0 }, // 8613 |
| 15904 | { PseudoVSOXEI8_V_MF4_M1_MASK, VSOXEI8_V, 0x0, 0x0 }, // 8614 |
| 15905 | { PseudoVSOXEI8_V_MF8_M1, VSOXEI8_V, 0x0, 0x0 }, // 8615 |
| 15906 | { PseudoVSOXEI8_V_MF8_M1_MASK, VSOXEI8_V, 0x0, 0x0 }, // 8616 |
| 15907 | { PseudoVSOXEI8_V_M1_M2, VSOXEI8_V, 0x1, 0x0 }, // 8617 |
| 15908 | { PseudoVSOXEI8_V_M1_M2_MASK, VSOXEI8_V, 0x1, 0x0 }, // 8618 |
| 15909 | { PseudoVSOXEI8_V_M2_M2, VSOXEI8_V, 0x1, 0x0 }, // 8619 |
| 15910 | { PseudoVSOXEI8_V_M2_M2_MASK, VSOXEI8_V, 0x1, 0x0 }, // 8620 |
| 15911 | { PseudoVSOXEI8_V_MF2_M2, VSOXEI8_V, 0x1, 0x0 }, // 8621 |
| 15912 | { PseudoVSOXEI8_V_MF2_M2_MASK, VSOXEI8_V, 0x1, 0x0 }, // 8622 |
| 15913 | { PseudoVSOXEI8_V_MF4_M2, VSOXEI8_V, 0x1, 0x0 }, // 8623 |
| 15914 | { PseudoVSOXEI8_V_MF4_M2_MASK, VSOXEI8_V, 0x1, 0x0 }, // 8624 |
| 15915 | { PseudoVSOXEI8_V_M1_M4, VSOXEI8_V, 0x2, 0x0 }, // 8625 |
| 15916 | { PseudoVSOXEI8_V_M1_M4_MASK, VSOXEI8_V, 0x2, 0x0 }, // 8626 |
| 15917 | { PseudoVSOXEI8_V_M2_M4, VSOXEI8_V, 0x2, 0x0 }, // 8627 |
| 15918 | { PseudoVSOXEI8_V_M2_M4_MASK, VSOXEI8_V, 0x2, 0x0 }, // 8628 |
| 15919 | { PseudoVSOXEI8_V_M4_M4, VSOXEI8_V, 0x2, 0x0 }, // 8629 |
| 15920 | { PseudoVSOXEI8_V_M4_M4_MASK, VSOXEI8_V, 0x2, 0x0 }, // 8630 |
| 15921 | { PseudoVSOXEI8_V_MF2_M4, VSOXEI8_V, 0x2, 0x0 }, // 8631 |
| 15922 | { PseudoVSOXEI8_V_MF2_M4_MASK, VSOXEI8_V, 0x2, 0x0 }, // 8632 |
| 15923 | { PseudoVSOXEI8_V_M1_M8, VSOXEI8_V, 0x3, 0x0 }, // 8633 |
| 15924 | { PseudoVSOXEI8_V_M1_M8_MASK, VSOXEI8_V, 0x3, 0x0 }, // 8634 |
| 15925 | { PseudoVSOXEI8_V_M2_M8, VSOXEI8_V, 0x3, 0x0 }, // 8635 |
| 15926 | { PseudoVSOXEI8_V_M2_M8_MASK, VSOXEI8_V, 0x3, 0x0 }, // 8636 |
| 15927 | { PseudoVSOXEI8_V_M4_M8, VSOXEI8_V, 0x3, 0x0 }, // 8637 |
| 15928 | { PseudoVSOXEI8_V_M4_M8_MASK, VSOXEI8_V, 0x3, 0x0 }, // 8638 |
| 15929 | { PseudoVSOXEI8_V_M8_M8, VSOXEI8_V, 0x3, 0x0 }, // 8639 |
| 15930 | { PseudoVSOXEI8_V_M8_M8_MASK, VSOXEI8_V, 0x3, 0x0 }, // 8640 |
| 15931 | { PseudoVSOXEI8_V_MF8_MF8, VSOXEI8_V, 0x5, 0x0 }, // 8641 |
| 15932 | { PseudoVSOXEI8_V_MF8_MF8_MASK, VSOXEI8_V, 0x5, 0x0 }, // 8642 |
| 15933 | { PseudoVSOXEI8_V_MF4_MF4, VSOXEI8_V, 0x6, 0x0 }, // 8643 |
| 15934 | { PseudoVSOXEI8_V_MF4_MF4_MASK, VSOXEI8_V, 0x6, 0x0 }, // 8644 |
| 15935 | { PseudoVSOXEI8_V_MF8_MF4, VSOXEI8_V, 0x6, 0x0 }, // 8645 |
| 15936 | { PseudoVSOXEI8_V_MF8_MF4_MASK, VSOXEI8_V, 0x6, 0x0 }, // 8646 |
| 15937 | { PseudoVSOXEI8_V_MF2_MF2, VSOXEI8_V, 0x7, 0x0 }, // 8647 |
| 15938 | { PseudoVSOXEI8_V_MF2_MF2_MASK, VSOXEI8_V, 0x7, 0x0 }, // 8648 |
| 15939 | { PseudoVSOXEI8_V_MF4_MF2, VSOXEI8_V, 0x7, 0x0 }, // 8649 |
| 15940 | { PseudoVSOXEI8_V_MF4_MF2_MASK, VSOXEI8_V, 0x7, 0x0 }, // 8650 |
| 15941 | { PseudoVSOXEI8_V_MF8_MF2, VSOXEI8_V, 0x7, 0x0 }, // 8651 |
| 15942 | { PseudoVSOXEI8_V_MF8_MF2_MASK, VSOXEI8_V, 0x7, 0x0 }, // 8652 |
| 15943 | { PseudoVSOXSEG2EI16_V_M1_M1, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8653 |
| 15944 | { PseudoVSOXSEG2EI16_V_M1_M1_MASK, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8654 |
| 15945 | { PseudoVSOXSEG2EI16_V_M2_M1, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8655 |
| 15946 | { PseudoVSOXSEG2EI16_V_M2_M1_MASK, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8656 |
| 15947 | { PseudoVSOXSEG2EI16_V_MF2_M1, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8657 |
| 15948 | { PseudoVSOXSEG2EI16_V_MF2_M1_MASK, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8658 |
| 15949 | { PseudoVSOXSEG2EI16_V_MF4_M1, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8659 |
| 15950 | { PseudoVSOXSEG2EI16_V_MF4_M1_MASK, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8660 |
| 15951 | { PseudoVSOXSEG2EI16_V_M1_M2, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8661 |
| 15952 | { PseudoVSOXSEG2EI16_V_M1_M2_MASK, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8662 |
| 15953 | { PseudoVSOXSEG2EI16_V_M2_M2, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8663 |
| 15954 | { PseudoVSOXSEG2EI16_V_M2_M2_MASK, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8664 |
| 15955 | { PseudoVSOXSEG2EI16_V_M4_M2, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8665 |
| 15956 | { PseudoVSOXSEG2EI16_V_M4_M2_MASK, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8666 |
| 15957 | { PseudoVSOXSEG2EI16_V_MF2_M2, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8667 |
| 15958 | { PseudoVSOXSEG2EI16_V_MF2_M2_MASK, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8668 |
| 15959 | { PseudoVSOXSEG2EI16_V_M1_M4, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8669 |
| 15960 | { PseudoVSOXSEG2EI16_V_M1_M4_MASK, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8670 |
| 15961 | { PseudoVSOXSEG2EI16_V_M2_M4, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8671 |
| 15962 | { PseudoVSOXSEG2EI16_V_M2_M4_MASK, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8672 |
| 15963 | { PseudoVSOXSEG2EI16_V_M4_M4, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8673 |
| 15964 | { PseudoVSOXSEG2EI16_V_M4_M4_MASK, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8674 |
| 15965 | { PseudoVSOXSEG2EI16_V_M8_M4, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8675 |
| 15966 | { PseudoVSOXSEG2EI16_V_M8_M4_MASK, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8676 |
| 15967 | { PseudoVSOXSEG2EI16_V_MF4_MF8, VSOXSEG2EI16_V, 0x5, 0x0 }, // 8677 |
| 15968 | { PseudoVSOXSEG2EI16_V_MF4_MF8_MASK, VSOXSEG2EI16_V, 0x5, 0x0 }, // 8678 |
| 15969 | { PseudoVSOXSEG2EI16_V_MF2_MF4, VSOXSEG2EI16_V, 0x6, 0x0 }, // 8679 |
| 15970 | { PseudoVSOXSEG2EI16_V_MF2_MF4_MASK, VSOXSEG2EI16_V, 0x6, 0x0 }, // 8680 |
| 15971 | { PseudoVSOXSEG2EI16_V_MF4_MF4, VSOXSEG2EI16_V, 0x6, 0x0 }, // 8681 |
| 15972 | { PseudoVSOXSEG2EI16_V_MF4_MF4_MASK, VSOXSEG2EI16_V, 0x6, 0x0 }, // 8682 |
| 15973 | { PseudoVSOXSEG2EI16_V_M1_MF2, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8683 |
| 15974 | { PseudoVSOXSEG2EI16_V_M1_MF2_MASK, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8684 |
| 15975 | { PseudoVSOXSEG2EI16_V_MF2_MF2, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8685 |
| 15976 | { PseudoVSOXSEG2EI16_V_MF2_MF2_MASK, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8686 |
| 15977 | { PseudoVSOXSEG2EI16_V_MF4_MF2, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8687 |
| 15978 | { PseudoVSOXSEG2EI16_V_MF4_MF2_MASK, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8688 |
| 15979 | { PseudoVSOXSEG2EI32_V_M1_M1, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8689 |
| 15980 | { PseudoVSOXSEG2EI32_V_M1_M1_MASK, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8690 |
| 15981 | { PseudoVSOXSEG2EI32_V_M2_M1, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8691 |
| 15982 | { PseudoVSOXSEG2EI32_V_M2_M1_MASK, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8692 |
| 15983 | { PseudoVSOXSEG2EI32_V_M4_M1, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8693 |
| 15984 | { PseudoVSOXSEG2EI32_V_M4_M1_MASK, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8694 |
| 15985 | { PseudoVSOXSEG2EI32_V_MF2_M1, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8695 |
| 15986 | { PseudoVSOXSEG2EI32_V_MF2_M1_MASK, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8696 |
| 15987 | { PseudoVSOXSEG2EI32_V_M1_M2, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8697 |
| 15988 | { PseudoVSOXSEG2EI32_V_M1_M2_MASK, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8698 |
| 15989 | { PseudoVSOXSEG2EI32_V_M2_M2, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8699 |
| 15990 | { PseudoVSOXSEG2EI32_V_M2_M2_MASK, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8700 |
| 15991 | { PseudoVSOXSEG2EI32_V_M4_M2, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8701 |
| 15992 | { PseudoVSOXSEG2EI32_V_M4_M2_MASK, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8702 |
| 15993 | { PseudoVSOXSEG2EI32_V_M8_M2, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8703 |
| 15994 | { PseudoVSOXSEG2EI32_V_M8_M2_MASK, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8704 |
| 15995 | { PseudoVSOXSEG2EI32_V_M2_M4, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8705 |
| 15996 | { PseudoVSOXSEG2EI32_V_M2_M4_MASK, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8706 |
| 15997 | { PseudoVSOXSEG2EI32_V_M4_M4, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8707 |
| 15998 | { PseudoVSOXSEG2EI32_V_M4_M4_MASK, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8708 |
| 15999 | { PseudoVSOXSEG2EI32_V_M8_M4, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8709 |
| 16000 | { PseudoVSOXSEG2EI32_V_M8_M4_MASK, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8710 |
| 16001 | { PseudoVSOXSEG2EI32_V_MF2_MF8, VSOXSEG2EI32_V, 0x5, 0x0 }, // 8711 |
| 16002 | { PseudoVSOXSEG2EI32_V_MF2_MF8_MASK, VSOXSEG2EI32_V, 0x5, 0x0 }, // 8712 |
| 16003 | { PseudoVSOXSEG2EI32_V_M1_MF4, VSOXSEG2EI32_V, 0x6, 0x0 }, // 8713 |
| 16004 | { PseudoVSOXSEG2EI32_V_M1_MF4_MASK, VSOXSEG2EI32_V, 0x6, 0x0 }, // 8714 |
| 16005 | { PseudoVSOXSEG2EI32_V_MF2_MF4, VSOXSEG2EI32_V, 0x6, 0x0 }, // 8715 |
| 16006 | { PseudoVSOXSEG2EI32_V_MF2_MF4_MASK, VSOXSEG2EI32_V, 0x6, 0x0 }, // 8716 |
| 16007 | { PseudoVSOXSEG2EI32_V_M1_MF2, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8717 |
| 16008 | { PseudoVSOXSEG2EI32_V_M1_MF2_MASK, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8718 |
| 16009 | { PseudoVSOXSEG2EI32_V_M2_MF2, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8719 |
| 16010 | { PseudoVSOXSEG2EI32_V_M2_MF2_MASK, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8720 |
| 16011 | { PseudoVSOXSEG2EI32_V_MF2_MF2, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8721 |
| 16012 | { PseudoVSOXSEG2EI32_V_MF2_MF2_MASK, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8722 |
| 16013 | { PseudoVSOXSEG2EI64_V_M1_M1, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8723 |
| 16014 | { PseudoVSOXSEG2EI64_V_M1_M1_MASK, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8724 |
| 16015 | { PseudoVSOXSEG2EI64_V_M2_M1, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8725 |
| 16016 | { PseudoVSOXSEG2EI64_V_M2_M1_MASK, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8726 |
| 16017 | { PseudoVSOXSEG2EI64_V_M4_M1, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8727 |
| 16018 | { PseudoVSOXSEG2EI64_V_M4_M1_MASK, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8728 |
| 16019 | { PseudoVSOXSEG2EI64_V_M8_M1, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8729 |
| 16020 | { PseudoVSOXSEG2EI64_V_M8_M1_MASK, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8730 |
| 16021 | { PseudoVSOXSEG2EI64_V_M2_M2, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8731 |
| 16022 | { PseudoVSOXSEG2EI64_V_M2_M2_MASK, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8732 |
| 16023 | { PseudoVSOXSEG2EI64_V_M4_M2, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8733 |
| 16024 | { PseudoVSOXSEG2EI64_V_M4_M2_MASK, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8734 |
| 16025 | { PseudoVSOXSEG2EI64_V_M8_M2, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8735 |
| 16026 | { PseudoVSOXSEG2EI64_V_M8_M2_MASK, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8736 |
| 16027 | { PseudoVSOXSEG2EI64_V_M4_M4, VSOXSEG2EI64_V, 0x2, 0x0 }, // 8737 |
| 16028 | { PseudoVSOXSEG2EI64_V_M4_M4_MASK, VSOXSEG2EI64_V, 0x2, 0x0 }, // 8738 |
| 16029 | { PseudoVSOXSEG2EI64_V_M8_M4, VSOXSEG2EI64_V, 0x2, 0x0 }, // 8739 |
| 16030 | { PseudoVSOXSEG2EI64_V_M8_M4_MASK, VSOXSEG2EI64_V, 0x2, 0x0 }, // 8740 |
| 16031 | { PseudoVSOXSEG2EI64_V_M1_MF8, VSOXSEG2EI64_V, 0x5, 0x0 }, // 8741 |
| 16032 | { PseudoVSOXSEG2EI64_V_M1_MF8_MASK, VSOXSEG2EI64_V, 0x5, 0x0 }, // 8742 |
| 16033 | { PseudoVSOXSEG2EI64_V_M1_MF4, VSOXSEG2EI64_V, 0x6, 0x0 }, // 8743 |
| 16034 | { PseudoVSOXSEG2EI64_V_M1_MF4_MASK, VSOXSEG2EI64_V, 0x6, 0x0 }, // 8744 |
| 16035 | { PseudoVSOXSEG2EI64_V_M2_MF4, VSOXSEG2EI64_V, 0x6, 0x0 }, // 8745 |
| 16036 | { PseudoVSOXSEG2EI64_V_M2_MF4_MASK, VSOXSEG2EI64_V, 0x6, 0x0 }, // 8746 |
| 16037 | { PseudoVSOXSEG2EI64_V_M1_MF2, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8747 |
| 16038 | { PseudoVSOXSEG2EI64_V_M1_MF2_MASK, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8748 |
| 16039 | { PseudoVSOXSEG2EI64_V_M2_MF2, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8749 |
| 16040 | { PseudoVSOXSEG2EI64_V_M2_MF2_MASK, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8750 |
| 16041 | { PseudoVSOXSEG2EI64_V_M4_MF2, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8751 |
| 16042 | { PseudoVSOXSEG2EI64_V_M4_MF2_MASK, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8752 |
| 16043 | { PseudoVSOXSEG2EI8_V_M1_M1, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8753 |
| 16044 | { PseudoVSOXSEG2EI8_V_M1_M1_MASK, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8754 |
| 16045 | { PseudoVSOXSEG2EI8_V_MF2_M1, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8755 |
| 16046 | { PseudoVSOXSEG2EI8_V_MF2_M1_MASK, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8756 |
| 16047 | { PseudoVSOXSEG2EI8_V_MF4_M1, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8757 |
| 16048 | { PseudoVSOXSEG2EI8_V_MF4_M1_MASK, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8758 |
| 16049 | { PseudoVSOXSEG2EI8_V_MF8_M1, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8759 |
| 16050 | { PseudoVSOXSEG2EI8_V_MF8_M1_MASK, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8760 |
| 16051 | { PseudoVSOXSEG2EI8_V_M1_M2, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8761 |
| 16052 | { PseudoVSOXSEG2EI8_V_M1_M2_MASK, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8762 |
| 16053 | { PseudoVSOXSEG2EI8_V_M2_M2, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8763 |
| 16054 | { PseudoVSOXSEG2EI8_V_M2_M2_MASK, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8764 |
| 16055 | { PseudoVSOXSEG2EI8_V_MF2_M2, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8765 |
| 16056 | { PseudoVSOXSEG2EI8_V_MF2_M2_MASK, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8766 |
| 16057 | { PseudoVSOXSEG2EI8_V_MF4_M2, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8767 |
| 16058 | { PseudoVSOXSEG2EI8_V_MF4_M2_MASK, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8768 |
| 16059 | { PseudoVSOXSEG2EI8_V_M1_M4, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8769 |
| 16060 | { PseudoVSOXSEG2EI8_V_M1_M4_MASK, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8770 |
| 16061 | { PseudoVSOXSEG2EI8_V_M2_M4, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8771 |
| 16062 | { PseudoVSOXSEG2EI8_V_M2_M4_MASK, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8772 |
| 16063 | { PseudoVSOXSEG2EI8_V_M4_M4, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8773 |
| 16064 | { PseudoVSOXSEG2EI8_V_M4_M4_MASK, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8774 |
| 16065 | { PseudoVSOXSEG2EI8_V_MF2_M4, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8775 |
| 16066 | { PseudoVSOXSEG2EI8_V_MF2_M4_MASK, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8776 |
| 16067 | { PseudoVSOXSEG2EI8_V_MF8_MF8, VSOXSEG2EI8_V, 0x5, 0x0 }, // 8777 |
| 16068 | { PseudoVSOXSEG2EI8_V_MF8_MF8_MASK, VSOXSEG2EI8_V, 0x5, 0x0 }, // 8778 |
| 16069 | { PseudoVSOXSEG2EI8_V_MF4_MF4, VSOXSEG2EI8_V, 0x6, 0x0 }, // 8779 |
| 16070 | { PseudoVSOXSEG2EI8_V_MF4_MF4_MASK, VSOXSEG2EI8_V, 0x6, 0x0 }, // 8780 |
| 16071 | { PseudoVSOXSEG2EI8_V_MF8_MF4, VSOXSEG2EI8_V, 0x6, 0x0 }, // 8781 |
| 16072 | { PseudoVSOXSEG2EI8_V_MF8_MF4_MASK, VSOXSEG2EI8_V, 0x6, 0x0 }, // 8782 |
| 16073 | { PseudoVSOXSEG2EI8_V_MF2_MF2, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8783 |
| 16074 | { PseudoVSOXSEG2EI8_V_MF2_MF2_MASK, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8784 |
| 16075 | { PseudoVSOXSEG2EI8_V_MF4_MF2, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8785 |
| 16076 | { PseudoVSOXSEG2EI8_V_MF4_MF2_MASK, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8786 |
| 16077 | { PseudoVSOXSEG2EI8_V_MF8_MF2, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8787 |
| 16078 | { PseudoVSOXSEG2EI8_V_MF8_MF2_MASK, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8788 |
| 16079 | { PseudoVSOXSEG3EI16_V_M1_M1, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8789 |
| 16080 | { PseudoVSOXSEG3EI16_V_M1_M1_MASK, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8790 |
| 16081 | { PseudoVSOXSEG3EI16_V_M2_M1, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8791 |
| 16082 | { PseudoVSOXSEG3EI16_V_M2_M1_MASK, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8792 |
| 16083 | { PseudoVSOXSEG3EI16_V_MF2_M1, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8793 |
| 16084 | { PseudoVSOXSEG3EI16_V_MF2_M1_MASK, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8794 |
| 16085 | { PseudoVSOXSEG3EI16_V_MF4_M1, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8795 |
| 16086 | { PseudoVSOXSEG3EI16_V_MF4_M1_MASK, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8796 |
| 16087 | { PseudoVSOXSEG3EI16_V_M1_M2, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8797 |
| 16088 | { PseudoVSOXSEG3EI16_V_M1_M2_MASK, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8798 |
| 16089 | { PseudoVSOXSEG3EI16_V_M2_M2, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8799 |
| 16090 | { PseudoVSOXSEG3EI16_V_M2_M2_MASK, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8800 |
| 16091 | { PseudoVSOXSEG3EI16_V_M4_M2, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8801 |
| 16092 | { PseudoVSOXSEG3EI16_V_M4_M2_MASK, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8802 |
| 16093 | { PseudoVSOXSEG3EI16_V_MF2_M2, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8803 |
| 16094 | { PseudoVSOXSEG3EI16_V_MF2_M2_MASK, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8804 |
| 16095 | { PseudoVSOXSEG3EI16_V_MF4_MF8, VSOXSEG3EI16_V, 0x5, 0x0 }, // 8805 |
| 16096 | { PseudoVSOXSEG3EI16_V_MF4_MF8_MASK, VSOXSEG3EI16_V, 0x5, 0x0 }, // 8806 |
| 16097 | { PseudoVSOXSEG3EI16_V_MF2_MF4, VSOXSEG3EI16_V, 0x6, 0x0 }, // 8807 |
| 16098 | { PseudoVSOXSEG3EI16_V_MF2_MF4_MASK, VSOXSEG3EI16_V, 0x6, 0x0 }, // 8808 |
| 16099 | { PseudoVSOXSEG3EI16_V_MF4_MF4, VSOXSEG3EI16_V, 0x6, 0x0 }, // 8809 |
| 16100 | { PseudoVSOXSEG3EI16_V_MF4_MF4_MASK, VSOXSEG3EI16_V, 0x6, 0x0 }, // 8810 |
| 16101 | { PseudoVSOXSEG3EI16_V_M1_MF2, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8811 |
| 16102 | { PseudoVSOXSEG3EI16_V_M1_MF2_MASK, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8812 |
| 16103 | { PseudoVSOXSEG3EI16_V_MF2_MF2, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8813 |
| 16104 | { PseudoVSOXSEG3EI16_V_MF2_MF2_MASK, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8814 |
| 16105 | { PseudoVSOXSEG3EI16_V_MF4_MF2, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8815 |
| 16106 | { PseudoVSOXSEG3EI16_V_MF4_MF2_MASK, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8816 |
| 16107 | { PseudoVSOXSEG3EI32_V_M1_M1, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8817 |
| 16108 | { PseudoVSOXSEG3EI32_V_M1_M1_MASK, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8818 |
| 16109 | { PseudoVSOXSEG3EI32_V_M2_M1, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8819 |
| 16110 | { PseudoVSOXSEG3EI32_V_M2_M1_MASK, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8820 |
| 16111 | { PseudoVSOXSEG3EI32_V_M4_M1, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8821 |
| 16112 | { PseudoVSOXSEG3EI32_V_M4_M1_MASK, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8822 |
| 16113 | { PseudoVSOXSEG3EI32_V_MF2_M1, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8823 |
| 16114 | { PseudoVSOXSEG3EI32_V_MF2_M1_MASK, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8824 |
| 16115 | { PseudoVSOXSEG3EI32_V_M1_M2, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8825 |
| 16116 | { PseudoVSOXSEG3EI32_V_M1_M2_MASK, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8826 |
| 16117 | { PseudoVSOXSEG3EI32_V_M2_M2, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8827 |
| 16118 | { PseudoVSOXSEG3EI32_V_M2_M2_MASK, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8828 |
| 16119 | { PseudoVSOXSEG3EI32_V_M4_M2, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8829 |
| 16120 | { PseudoVSOXSEG3EI32_V_M4_M2_MASK, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8830 |
| 16121 | { PseudoVSOXSEG3EI32_V_M8_M2, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8831 |
| 16122 | { PseudoVSOXSEG3EI32_V_M8_M2_MASK, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8832 |
| 16123 | { PseudoVSOXSEG3EI32_V_MF2_MF8, VSOXSEG3EI32_V, 0x5, 0x0 }, // 8833 |
| 16124 | { PseudoVSOXSEG3EI32_V_MF2_MF8_MASK, VSOXSEG3EI32_V, 0x5, 0x0 }, // 8834 |
| 16125 | { PseudoVSOXSEG3EI32_V_M1_MF4, VSOXSEG3EI32_V, 0x6, 0x0 }, // 8835 |
| 16126 | { PseudoVSOXSEG3EI32_V_M1_MF4_MASK, VSOXSEG3EI32_V, 0x6, 0x0 }, // 8836 |
| 16127 | { PseudoVSOXSEG3EI32_V_MF2_MF4, VSOXSEG3EI32_V, 0x6, 0x0 }, // 8837 |
| 16128 | { PseudoVSOXSEG3EI32_V_MF2_MF4_MASK, VSOXSEG3EI32_V, 0x6, 0x0 }, // 8838 |
| 16129 | { PseudoVSOXSEG3EI32_V_M1_MF2, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8839 |
| 16130 | { PseudoVSOXSEG3EI32_V_M1_MF2_MASK, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8840 |
| 16131 | { PseudoVSOXSEG3EI32_V_M2_MF2, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8841 |
| 16132 | { PseudoVSOXSEG3EI32_V_M2_MF2_MASK, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8842 |
| 16133 | { PseudoVSOXSEG3EI32_V_MF2_MF2, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8843 |
| 16134 | { PseudoVSOXSEG3EI32_V_MF2_MF2_MASK, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8844 |
| 16135 | { PseudoVSOXSEG3EI64_V_M1_M1, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8845 |
| 16136 | { PseudoVSOXSEG3EI64_V_M1_M1_MASK, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8846 |
| 16137 | { PseudoVSOXSEG3EI64_V_M2_M1, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8847 |
| 16138 | { PseudoVSOXSEG3EI64_V_M2_M1_MASK, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8848 |
| 16139 | { PseudoVSOXSEG3EI64_V_M4_M1, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8849 |
| 16140 | { PseudoVSOXSEG3EI64_V_M4_M1_MASK, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8850 |
| 16141 | { PseudoVSOXSEG3EI64_V_M8_M1, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8851 |
| 16142 | { PseudoVSOXSEG3EI64_V_M8_M1_MASK, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8852 |
| 16143 | { PseudoVSOXSEG3EI64_V_M2_M2, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8853 |
| 16144 | { PseudoVSOXSEG3EI64_V_M2_M2_MASK, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8854 |
| 16145 | { PseudoVSOXSEG3EI64_V_M4_M2, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8855 |
| 16146 | { PseudoVSOXSEG3EI64_V_M4_M2_MASK, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8856 |
| 16147 | { PseudoVSOXSEG3EI64_V_M8_M2, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8857 |
| 16148 | { PseudoVSOXSEG3EI64_V_M8_M2_MASK, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8858 |
| 16149 | { PseudoVSOXSEG3EI64_V_M1_MF8, VSOXSEG3EI64_V, 0x5, 0x0 }, // 8859 |
| 16150 | { PseudoVSOXSEG3EI64_V_M1_MF8_MASK, VSOXSEG3EI64_V, 0x5, 0x0 }, // 8860 |
| 16151 | { PseudoVSOXSEG3EI64_V_M1_MF4, VSOXSEG3EI64_V, 0x6, 0x0 }, // 8861 |
| 16152 | { PseudoVSOXSEG3EI64_V_M1_MF4_MASK, VSOXSEG3EI64_V, 0x6, 0x0 }, // 8862 |
| 16153 | { PseudoVSOXSEG3EI64_V_M2_MF4, VSOXSEG3EI64_V, 0x6, 0x0 }, // 8863 |
| 16154 | { PseudoVSOXSEG3EI64_V_M2_MF4_MASK, VSOXSEG3EI64_V, 0x6, 0x0 }, // 8864 |
| 16155 | { PseudoVSOXSEG3EI64_V_M1_MF2, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8865 |
| 16156 | { PseudoVSOXSEG3EI64_V_M1_MF2_MASK, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8866 |
| 16157 | { PseudoVSOXSEG3EI64_V_M2_MF2, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8867 |
| 16158 | { PseudoVSOXSEG3EI64_V_M2_MF2_MASK, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8868 |
| 16159 | { PseudoVSOXSEG3EI64_V_M4_MF2, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8869 |
| 16160 | { PseudoVSOXSEG3EI64_V_M4_MF2_MASK, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8870 |
| 16161 | { PseudoVSOXSEG3EI8_V_M1_M1, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8871 |
| 16162 | { PseudoVSOXSEG3EI8_V_M1_M1_MASK, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8872 |
| 16163 | { PseudoVSOXSEG3EI8_V_MF2_M1, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8873 |
| 16164 | { PseudoVSOXSEG3EI8_V_MF2_M1_MASK, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8874 |
| 16165 | { PseudoVSOXSEG3EI8_V_MF4_M1, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8875 |
| 16166 | { PseudoVSOXSEG3EI8_V_MF4_M1_MASK, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8876 |
| 16167 | { PseudoVSOXSEG3EI8_V_MF8_M1, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8877 |
| 16168 | { PseudoVSOXSEG3EI8_V_MF8_M1_MASK, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8878 |
| 16169 | { PseudoVSOXSEG3EI8_V_M1_M2, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8879 |
| 16170 | { PseudoVSOXSEG3EI8_V_M1_M2_MASK, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8880 |
| 16171 | { PseudoVSOXSEG3EI8_V_M2_M2, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8881 |
| 16172 | { PseudoVSOXSEG3EI8_V_M2_M2_MASK, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8882 |
| 16173 | { PseudoVSOXSEG3EI8_V_MF2_M2, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8883 |
| 16174 | { PseudoVSOXSEG3EI8_V_MF2_M2_MASK, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8884 |
| 16175 | { PseudoVSOXSEG3EI8_V_MF4_M2, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8885 |
| 16176 | { PseudoVSOXSEG3EI8_V_MF4_M2_MASK, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8886 |
| 16177 | { PseudoVSOXSEG3EI8_V_MF8_MF8, VSOXSEG3EI8_V, 0x5, 0x0 }, // 8887 |
| 16178 | { PseudoVSOXSEG3EI8_V_MF8_MF8_MASK, VSOXSEG3EI8_V, 0x5, 0x0 }, // 8888 |
| 16179 | { PseudoVSOXSEG3EI8_V_MF4_MF4, VSOXSEG3EI8_V, 0x6, 0x0 }, // 8889 |
| 16180 | { PseudoVSOXSEG3EI8_V_MF4_MF4_MASK, VSOXSEG3EI8_V, 0x6, 0x0 }, // 8890 |
| 16181 | { PseudoVSOXSEG3EI8_V_MF8_MF4, VSOXSEG3EI8_V, 0x6, 0x0 }, // 8891 |
| 16182 | { PseudoVSOXSEG3EI8_V_MF8_MF4_MASK, VSOXSEG3EI8_V, 0x6, 0x0 }, // 8892 |
| 16183 | { PseudoVSOXSEG3EI8_V_MF2_MF2, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8893 |
| 16184 | { PseudoVSOXSEG3EI8_V_MF2_MF2_MASK, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8894 |
| 16185 | { PseudoVSOXSEG3EI8_V_MF4_MF2, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8895 |
| 16186 | { PseudoVSOXSEG3EI8_V_MF4_MF2_MASK, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8896 |
| 16187 | { PseudoVSOXSEG3EI8_V_MF8_MF2, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8897 |
| 16188 | { PseudoVSOXSEG3EI8_V_MF8_MF2_MASK, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8898 |
| 16189 | { PseudoVSOXSEG4EI16_V_M1_M1, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8899 |
| 16190 | { PseudoVSOXSEG4EI16_V_M1_M1_MASK, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8900 |
| 16191 | { PseudoVSOXSEG4EI16_V_M2_M1, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8901 |
| 16192 | { PseudoVSOXSEG4EI16_V_M2_M1_MASK, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8902 |
| 16193 | { PseudoVSOXSEG4EI16_V_MF2_M1, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8903 |
| 16194 | { PseudoVSOXSEG4EI16_V_MF2_M1_MASK, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8904 |
| 16195 | { PseudoVSOXSEG4EI16_V_MF4_M1, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8905 |
| 16196 | { PseudoVSOXSEG4EI16_V_MF4_M1_MASK, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8906 |
| 16197 | { PseudoVSOXSEG4EI16_V_M1_M2, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8907 |
| 16198 | { PseudoVSOXSEG4EI16_V_M1_M2_MASK, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8908 |
| 16199 | { PseudoVSOXSEG4EI16_V_M2_M2, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8909 |
| 16200 | { PseudoVSOXSEG4EI16_V_M2_M2_MASK, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8910 |
| 16201 | { PseudoVSOXSEG4EI16_V_M4_M2, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8911 |
| 16202 | { PseudoVSOXSEG4EI16_V_M4_M2_MASK, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8912 |
| 16203 | { PseudoVSOXSEG4EI16_V_MF2_M2, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8913 |
| 16204 | { PseudoVSOXSEG4EI16_V_MF2_M2_MASK, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8914 |
| 16205 | { PseudoVSOXSEG4EI16_V_MF4_MF8, VSOXSEG4EI16_V, 0x5, 0x0 }, // 8915 |
| 16206 | { PseudoVSOXSEG4EI16_V_MF4_MF8_MASK, VSOXSEG4EI16_V, 0x5, 0x0 }, // 8916 |
| 16207 | { PseudoVSOXSEG4EI16_V_MF2_MF4, VSOXSEG4EI16_V, 0x6, 0x0 }, // 8917 |
| 16208 | { PseudoVSOXSEG4EI16_V_MF2_MF4_MASK, VSOXSEG4EI16_V, 0x6, 0x0 }, // 8918 |
| 16209 | { PseudoVSOXSEG4EI16_V_MF4_MF4, VSOXSEG4EI16_V, 0x6, 0x0 }, // 8919 |
| 16210 | { PseudoVSOXSEG4EI16_V_MF4_MF4_MASK, VSOXSEG4EI16_V, 0x6, 0x0 }, // 8920 |
| 16211 | { PseudoVSOXSEG4EI16_V_M1_MF2, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8921 |
| 16212 | { PseudoVSOXSEG4EI16_V_M1_MF2_MASK, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8922 |
| 16213 | { PseudoVSOXSEG4EI16_V_MF2_MF2, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8923 |
| 16214 | { PseudoVSOXSEG4EI16_V_MF2_MF2_MASK, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8924 |
| 16215 | { PseudoVSOXSEG4EI16_V_MF4_MF2, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8925 |
| 16216 | { PseudoVSOXSEG4EI16_V_MF4_MF2_MASK, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8926 |
| 16217 | { PseudoVSOXSEG4EI32_V_M1_M1, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8927 |
| 16218 | { PseudoVSOXSEG4EI32_V_M1_M1_MASK, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8928 |
| 16219 | { PseudoVSOXSEG4EI32_V_M2_M1, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8929 |
| 16220 | { PseudoVSOXSEG4EI32_V_M2_M1_MASK, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8930 |
| 16221 | { PseudoVSOXSEG4EI32_V_M4_M1, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8931 |
| 16222 | { PseudoVSOXSEG4EI32_V_M4_M1_MASK, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8932 |
| 16223 | { PseudoVSOXSEG4EI32_V_MF2_M1, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8933 |
| 16224 | { PseudoVSOXSEG4EI32_V_MF2_M1_MASK, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8934 |
| 16225 | { PseudoVSOXSEG4EI32_V_M1_M2, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8935 |
| 16226 | { PseudoVSOXSEG4EI32_V_M1_M2_MASK, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8936 |
| 16227 | { PseudoVSOXSEG4EI32_V_M2_M2, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8937 |
| 16228 | { PseudoVSOXSEG4EI32_V_M2_M2_MASK, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8938 |
| 16229 | { PseudoVSOXSEG4EI32_V_M4_M2, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8939 |
| 16230 | { PseudoVSOXSEG4EI32_V_M4_M2_MASK, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8940 |
| 16231 | { PseudoVSOXSEG4EI32_V_M8_M2, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8941 |
| 16232 | { PseudoVSOXSEG4EI32_V_M8_M2_MASK, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8942 |
| 16233 | { PseudoVSOXSEG4EI32_V_MF2_MF8, VSOXSEG4EI32_V, 0x5, 0x0 }, // 8943 |
| 16234 | { PseudoVSOXSEG4EI32_V_MF2_MF8_MASK, VSOXSEG4EI32_V, 0x5, 0x0 }, // 8944 |
| 16235 | { PseudoVSOXSEG4EI32_V_M1_MF4, VSOXSEG4EI32_V, 0x6, 0x0 }, // 8945 |
| 16236 | { PseudoVSOXSEG4EI32_V_M1_MF4_MASK, VSOXSEG4EI32_V, 0x6, 0x0 }, // 8946 |
| 16237 | { PseudoVSOXSEG4EI32_V_MF2_MF4, VSOXSEG4EI32_V, 0x6, 0x0 }, // 8947 |
| 16238 | { PseudoVSOXSEG4EI32_V_MF2_MF4_MASK, VSOXSEG4EI32_V, 0x6, 0x0 }, // 8948 |
| 16239 | { PseudoVSOXSEG4EI32_V_M1_MF2, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8949 |
| 16240 | { PseudoVSOXSEG4EI32_V_M1_MF2_MASK, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8950 |
| 16241 | { PseudoVSOXSEG4EI32_V_M2_MF2, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8951 |
| 16242 | { PseudoVSOXSEG4EI32_V_M2_MF2_MASK, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8952 |
| 16243 | { PseudoVSOXSEG4EI32_V_MF2_MF2, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8953 |
| 16244 | { PseudoVSOXSEG4EI32_V_MF2_MF2_MASK, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8954 |
| 16245 | { PseudoVSOXSEG4EI64_V_M1_M1, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8955 |
| 16246 | { PseudoVSOXSEG4EI64_V_M1_M1_MASK, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8956 |
| 16247 | { PseudoVSOXSEG4EI64_V_M2_M1, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8957 |
| 16248 | { PseudoVSOXSEG4EI64_V_M2_M1_MASK, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8958 |
| 16249 | { PseudoVSOXSEG4EI64_V_M4_M1, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8959 |
| 16250 | { PseudoVSOXSEG4EI64_V_M4_M1_MASK, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8960 |
| 16251 | { PseudoVSOXSEG4EI64_V_M8_M1, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8961 |
| 16252 | { PseudoVSOXSEG4EI64_V_M8_M1_MASK, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8962 |
| 16253 | { PseudoVSOXSEG4EI64_V_M2_M2, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8963 |
| 16254 | { PseudoVSOXSEG4EI64_V_M2_M2_MASK, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8964 |
| 16255 | { PseudoVSOXSEG4EI64_V_M4_M2, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8965 |
| 16256 | { PseudoVSOXSEG4EI64_V_M4_M2_MASK, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8966 |
| 16257 | { PseudoVSOXSEG4EI64_V_M8_M2, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8967 |
| 16258 | { PseudoVSOXSEG4EI64_V_M8_M2_MASK, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8968 |
| 16259 | { PseudoVSOXSEG4EI64_V_M1_MF8, VSOXSEG4EI64_V, 0x5, 0x0 }, // 8969 |
| 16260 | { PseudoVSOXSEG4EI64_V_M1_MF8_MASK, VSOXSEG4EI64_V, 0x5, 0x0 }, // 8970 |
| 16261 | { PseudoVSOXSEG4EI64_V_M1_MF4, VSOXSEG4EI64_V, 0x6, 0x0 }, // 8971 |
| 16262 | { PseudoVSOXSEG4EI64_V_M1_MF4_MASK, VSOXSEG4EI64_V, 0x6, 0x0 }, // 8972 |
| 16263 | { PseudoVSOXSEG4EI64_V_M2_MF4, VSOXSEG4EI64_V, 0x6, 0x0 }, // 8973 |
| 16264 | { PseudoVSOXSEG4EI64_V_M2_MF4_MASK, VSOXSEG4EI64_V, 0x6, 0x0 }, // 8974 |
| 16265 | { PseudoVSOXSEG4EI64_V_M1_MF2, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8975 |
| 16266 | { PseudoVSOXSEG4EI64_V_M1_MF2_MASK, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8976 |
| 16267 | { PseudoVSOXSEG4EI64_V_M2_MF2, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8977 |
| 16268 | { PseudoVSOXSEG4EI64_V_M2_MF2_MASK, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8978 |
| 16269 | { PseudoVSOXSEG4EI64_V_M4_MF2, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8979 |
| 16270 | { PseudoVSOXSEG4EI64_V_M4_MF2_MASK, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8980 |
| 16271 | { PseudoVSOXSEG4EI8_V_M1_M1, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8981 |
| 16272 | { PseudoVSOXSEG4EI8_V_M1_M1_MASK, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8982 |
| 16273 | { PseudoVSOXSEG4EI8_V_MF2_M1, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8983 |
| 16274 | { PseudoVSOXSEG4EI8_V_MF2_M1_MASK, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8984 |
| 16275 | { PseudoVSOXSEG4EI8_V_MF4_M1, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8985 |
| 16276 | { PseudoVSOXSEG4EI8_V_MF4_M1_MASK, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8986 |
| 16277 | { PseudoVSOXSEG4EI8_V_MF8_M1, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8987 |
| 16278 | { PseudoVSOXSEG4EI8_V_MF8_M1_MASK, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8988 |
| 16279 | { PseudoVSOXSEG4EI8_V_M1_M2, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8989 |
| 16280 | { PseudoVSOXSEG4EI8_V_M1_M2_MASK, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8990 |
| 16281 | { PseudoVSOXSEG4EI8_V_M2_M2, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8991 |
| 16282 | { PseudoVSOXSEG4EI8_V_M2_M2_MASK, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8992 |
| 16283 | { PseudoVSOXSEG4EI8_V_MF2_M2, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8993 |
| 16284 | { PseudoVSOXSEG4EI8_V_MF2_M2_MASK, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8994 |
| 16285 | { PseudoVSOXSEG4EI8_V_MF4_M2, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8995 |
| 16286 | { PseudoVSOXSEG4EI8_V_MF4_M2_MASK, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8996 |
| 16287 | { PseudoVSOXSEG4EI8_V_MF8_MF8, VSOXSEG4EI8_V, 0x5, 0x0 }, // 8997 |
| 16288 | { PseudoVSOXSEG4EI8_V_MF8_MF8_MASK, VSOXSEG4EI8_V, 0x5, 0x0 }, // 8998 |
| 16289 | { PseudoVSOXSEG4EI8_V_MF4_MF4, VSOXSEG4EI8_V, 0x6, 0x0 }, // 8999 |
| 16290 | { PseudoVSOXSEG4EI8_V_MF4_MF4_MASK, VSOXSEG4EI8_V, 0x6, 0x0 }, // 9000 |
| 16291 | { PseudoVSOXSEG4EI8_V_MF8_MF4, VSOXSEG4EI8_V, 0x6, 0x0 }, // 9001 |
| 16292 | { PseudoVSOXSEG4EI8_V_MF8_MF4_MASK, VSOXSEG4EI8_V, 0x6, 0x0 }, // 9002 |
| 16293 | { PseudoVSOXSEG4EI8_V_MF2_MF2, VSOXSEG4EI8_V, 0x7, 0x0 }, // 9003 |
| 16294 | { PseudoVSOXSEG4EI8_V_MF2_MF2_MASK, VSOXSEG4EI8_V, 0x7, 0x0 }, // 9004 |
| 16295 | { PseudoVSOXSEG4EI8_V_MF4_MF2, VSOXSEG4EI8_V, 0x7, 0x0 }, // 9005 |
| 16296 | { PseudoVSOXSEG4EI8_V_MF4_MF2_MASK, VSOXSEG4EI8_V, 0x7, 0x0 }, // 9006 |
| 16297 | { PseudoVSOXSEG4EI8_V_MF8_MF2, VSOXSEG4EI8_V, 0x7, 0x0 }, // 9007 |
| 16298 | { PseudoVSOXSEG4EI8_V_MF8_MF2_MASK, VSOXSEG4EI8_V, 0x7, 0x0 }, // 9008 |
| 16299 | { PseudoVSOXSEG5EI16_V_M1_M1, VSOXSEG5EI16_V, 0x0, 0x0 }, // 9009 |
| 16300 | { PseudoVSOXSEG5EI16_V_M1_M1_MASK, VSOXSEG5EI16_V, 0x0, 0x0 }, // 9010 |
| 16301 | { PseudoVSOXSEG5EI16_V_M2_M1, VSOXSEG5EI16_V, 0x0, 0x0 }, // 9011 |
| 16302 | { PseudoVSOXSEG5EI16_V_M2_M1_MASK, VSOXSEG5EI16_V, 0x0, 0x0 }, // 9012 |
| 16303 | { PseudoVSOXSEG5EI16_V_MF2_M1, VSOXSEG5EI16_V, 0x0, 0x0 }, // 9013 |
| 16304 | { PseudoVSOXSEG5EI16_V_MF2_M1_MASK, VSOXSEG5EI16_V, 0x0, 0x0 }, // 9014 |
| 16305 | { PseudoVSOXSEG5EI16_V_MF4_M1, VSOXSEG5EI16_V, 0x0, 0x0 }, // 9015 |
| 16306 | { PseudoVSOXSEG5EI16_V_MF4_M1_MASK, VSOXSEG5EI16_V, 0x0, 0x0 }, // 9016 |
| 16307 | { PseudoVSOXSEG5EI16_V_MF4_MF8, VSOXSEG5EI16_V, 0x5, 0x0 }, // 9017 |
| 16308 | { PseudoVSOXSEG5EI16_V_MF4_MF8_MASK, VSOXSEG5EI16_V, 0x5, 0x0 }, // 9018 |
| 16309 | { PseudoVSOXSEG5EI16_V_MF2_MF4, VSOXSEG5EI16_V, 0x6, 0x0 }, // 9019 |
| 16310 | { PseudoVSOXSEG5EI16_V_MF2_MF4_MASK, VSOXSEG5EI16_V, 0x6, 0x0 }, // 9020 |
| 16311 | { PseudoVSOXSEG5EI16_V_MF4_MF4, VSOXSEG5EI16_V, 0x6, 0x0 }, // 9021 |
| 16312 | { PseudoVSOXSEG5EI16_V_MF4_MF4_MASK, VSOXSEG5EI16_V, 0x6, 0x0 }, // 9022 |
| 16313 | { PseudoVSOXSEG5EI16_V_M1_MF2, VSOXSEG5EI16_V, 0x7, 0x0 }, // 9023 |
| 16314 | { PseudoVSOXSEG5EI16_V_M1_MF2_MASK, VSOXSEG5EI16_V, 0x7, 0x0 }, // 9024 |
| 16315 | { PseudoVSOXSEG5EI16_V_MF2_MF2, VSOXSEG5EI16_V, 0x7, 0x0 }, // 9025 |
| 16316 | { PseudoVSOXSEG5EI16_V_MF2_MF2_MASK, VSOXSEG5EI16_V, 0x7, 0x0 }, // 9026 |
| 16317 | { PseudoVSOXSEG5EI16_V_MF4_MF2, VSOXSEG5EI16_V, 0x7, 0x0 }, // 9027 |
| 16318 | { PseudoVSOXSEG5EI16_V_MF4_MF2_MASK, VSOXSEG5EI16_V, 0x7, 0x0 }, // 9028 |
| 16319 | { PseudoVSOXSEG5EI32_V_M1_M1, VSOXSEG5EI32_V, 0x0, 0x0 }, // 9029 |
| 16320 | { PseudoVSOXSEG5EI32_V_M1_M1_MASK, VSOXSEG5EI32_V, 0x0, 0x0 }, // 9030 |
| 16321 | { PseudoVSOXSEG5EI32_V_M2_M1, VSOXSEG5EI32_V, 0x0, 0x0 }, // 9031 |
| 16322 | { PseudoVSOXSEG5EI32_V_M2_M1_MASK, VSOXSEG5EI32_V, 0x0, 0x0 }, // 9032 |
| 16323 | { PseudoVSOXSEG5EI32_V_M4_M1, VSOXSEG5EI32_V, 0x0, 0x0 }, // 9033 |
| 16324 | { PseudoVSOXSEG5EI32_V_M4_M1_MASK, VSOXSEG5EI32_V, 0x0, 0x0 }, // 9034 |
| 16325 | { PseudoVSOXSEG5EI32_V_MF2_M1, VSOXSEG5EI32_V, 0x0, 0x0 }, // 9035 |
| 16326 | { PseudoVSOXSEG5EI32_V_MF2_M1_MASK, VSOXSEG5EI32_V, 0x0, 0x0 }, // 9036 |
| 16327 | { PseudoVSOXSEG5EI32_V_MF2_MF8, VSOXSEG5EI32_V, 0x5, 0x0 }, // 9037 |
| 16328 | { PseudoVSOXSEG5EI32_V_MF2_MF8_MASK, VSOXSEG5EI32_V, 0x5, 0x0 }, // 9038 |
| 16329 | { PseudoVSOXSEG5EI32_V_M1_MF4, VSOXSEG5EI32_V, 0x6, 0x0 }, // 9039 |
| 16330 | { PseudoVSOXSEG5EI32_V_M1_MF4_MASK, VSOXSEG5EI32_V, 0x6, 0x0 }, // 9040 |
| 16331 | { PseudoVSOXSEG5EI32_V_MF2_MF4, VSOXSEG5EI32_V, 0x6, 0x0 }, // 9041 |
| 16332 | { PseudoVSOXSEG5EI32_V_MF2_MF4_MASK, VSOXSEG5EI32_V, 0x6, 0x0 }, // 9042 |
| 16333 | { PseudoVSOXSEG5EI32_V_M1_MF2, VSOXSEG5EI32_V, 0x7, 0x0 }, // 9043 |
| 16334 | { PseudoVSOXSEG5EI32_V_M1_MF2_MASK, VSOXSEG5EI32_V, 0x7, 0x0 }, // 9044 |
| 16335 | { PseudoVSOXSEG5EI32_V_M2_MF2, VSOXSEG5EI32_V, 0x7, 0x0 }, // 9045 |
| 16336 | { PseudoVSOXSEG5EI32_V_M2_MF2_MASK, VSOXSEG5EI32_V, 0x7, 0x0 }, // 9046 |
| 16337 | { PseudoVSOXSEG5EI32_V_MF2_MF2, VSOXSEG5EI32_V, 0x7, 0x0 }, // 9047 |
| 16338 | { PseudoVSOXSEG5EI32_V_MF2_MF2_MASK, VSOXSEG5EI32_V, 0x7, 0x0 }, // 9048 |
| 16339 | { PseudoVSOXSEG5EI64_V_M1_M1, VSOXSEG5EI64_V, 0x0, 0x0 }, // 9049 |
| 16340 | { PseudoVSOXSEG5EI64_V_M1_M1_MASK, VSOXSEG5EI64_V, 0x0, 0x0 }, // 9050 |
| 16341 | { PseudoVSOXSEG5EI64_V_M2_M1, VSOXSEG5EI64_V, 0x0, 0x0 }, // 9051 |
| 16342 | { PseudoVSOXSEG5EI64_V_M2_M1_MASK, VSOXSEG5EI64_V, 0x0, 0x0 }, // 9052 |
| 16343 | { PseudoVSOXSEG5EI64_V_M4_M1, VSOXSEG5EI64_V, 0x0, 0x0 }, // 9053 |
| 16344 | { PseudoVSOXSEG5EI64_V_M4_M1_MASK, VSOXSEG5EI64_V, 0x0, 0x0 }, // 9054 |
| 16345 | { PseudoVSOXSEG5EI64_V_M8_M1, VSOXSEG5EI64_V, 0x0, 0x0 }, // 9055 |
| 16346 | { PseudoVSOXSEG5EI64_V_M8_M1_MASK, VSOXSEG5EI64_V, 0x0, 0x0 }, // 9056 |
| 16347 | { PseudoVSOXSEG5EI64_V_M1_MF8, VSOXSEG5EI64_V, 0x5, 0x0 }, // 9057 |
| 16348 | { PseudoVSOXSEG5EI64_V_M1_MF8_MASK, VSOXSEG5EI64_V, 0x5, 0x0 }, // 9058 |
| 16349 | { PseudoVSOXSEG5EI64_V_M1_MF4, VSOXSEG5EI64_V, 0x6, 0x0 }, // 9059 |
| 16350 | { PseudoVSOXSEG5EI64_V_M1_MF4_MASK, VSOXSEG5EI64_V, 0x6, 0x0 }, // 9060 |
| 16351 | { PseudoVSOXSEG5EI64_V_M2_MF4, VSOXSEG5EI64_V, 0x6, 0x0 }, // 9061 |
| 16352 | { PseudoVSOXSEG5EI64_V_M2_MF4_MASK, VSOXSEG5EI64_V, 0x6, 0x0 }, // 9062 |
| 16353 | { PseudoVSOXSEG5EI64_V_M1_MF2, VSOXSEG5EI64_V, 0x7, 0x0 }, // 9063 |
| 16354 | { PseudoVSOXSEG5EI64_V_M1_MF2_MASK, VSOXSEG5EI64_V, 0x7, 0x0 }, // 9064 |
| 16355 | { PseudoVSOXSEG5EI64_V_M2_MF2, VSOXSEG5EI64_V, 0x7, 0x0 }, // 9065 |
| 16356 | { PseudoVSOXSEG5EI64_V_M2_MF2_MASK, VSOXSEG5EI64_V, 0x7, 0x0 }, // 9066 |
| 16357 | { PseudoVSOXSEG5EI64_V_M4_MF2, VSOXSEG5EI64_V, 0x7, 0x0 }, // 9067 |
| 16358 | { PseudoVSOXSEG5EI64_V_M4_MF2_MASK, VSOXSEG5EI64_V, 0x7, 0x0 }, // 9068 |
| 16359 | { PseudoVSOXSEG5EI8_V_M1_M1, VSOXSEG5EI8_V, 0x0, 0x0 }, // 9069 |
| 16360 | { PseudoVSOXSEG5EI8_V_M1_M1_MASK, VSOXSEG5EI8_V, 0x0, 0x0 }, // 9070 |
| 16361 | { PseudoVSOXSEG5EI8_V_MF2_M1, VSOXSEG5EI8_V, 0x0, 0x0 }, // 9071 |
| 16362 | { PseudoVSOXSEG5EI8_V_MF2_M1_MASK, VSOXSEG5EI8_V, 0x0, 0x0 }, // 9072 |
| 16363 | { PseudoVSOXSEG5EI8_V_MF4_M1, VSOXSEG5EI8_V, 0x0, 0x0 }, // 9073 |
| 16364 | { PseudoVSOXSEG5EI8_V_MF4_M1_MASK, VSOXSEG5EI8_V, 0x0, 0x0 }, // 9074 |
| 16365 | { PseudoVSOXSEG5EI8_V_MF8_M1, VSOXSEG5EI8_V, 0x0, 0x0 }, // 9075 |
| 16366 | { PseudoVSOXSEG5EI8_V_MF8_M1_MASK, VSOXSEG5EI8_V, 0x0, 0x0 }, // 9076 |
| 16367 | { PseudoVSOXSEG5EI8_V_MF8_MF8, VSOXSEG5EI8_V, 0x5, 0x0 }, // 9077 |
| 16368 | { PseudoVSOXSEG5EI8_V_MF8_MF8_MASK, VSOXSEG5EI8_V, 0x5, 0x0 }, // 9078 |
| 16369 | { PseudoVSOXSEG5EI8_V_MF4_MF4, VSOXSEG5EI8_V, 0x6, 0x0 }, // 9079 |
| 16370 | { PseudoVSOXSEG5EI8_V_MF4_MF4_MASK, VSOXSEG5EI8_V, 0x6, 0x0 }, // 9080 |
| 16371 | { PseudoVSOXSEG5EI8_V_MF8_MF4, VSOXSEG5EI8_V, 0x6, 0x0 }, // 9081 |
| 16372 | { PseudoVSOXSEG5EI8_V_MF8_MF4_MASK, VSOXSEG5EI8_V, 0x6, 0x0 }, // 9082 |
| 16373 | { PseudoVSOXSEG5EI8_V_MF2_MF2, VSOXSEG5EI8_V, 0x7, 0x0 }, // 9083 |
| 16374 | { PseudoVSOXSEG5EI8_V_MF2_MF2_MASK, VSOXSEG5EI8_V, 0x7, 0x0 }, // 9084 |
| 16375 | { PseudoVSOXSEG5EI8_V_MF4_MF2, VSOXSEG5EI8_V, 0x7, 0x0 }, // 9085 |
| 16376 | { PseudoVSOXSEG5EI8_V_MF4_MF2_MASK, VSOXSEG5EI8_V, 0x7, 0x0 }, // 9086 |
| 16377 | { PseudoVSOXSEG5EI8_V_MF8_MF2, VSOXSEG5EI8_V, 0x7, 0x0 }, // 9087 |
| 16378 | { PseudoVSOXSEG5EI8_V_MF8_MF2_MASK, VSOXSEG5EI8_V, 0x7, 0x0 }, // 9088 |
| 16379 | { PseudoVSOXSEG6EI16_V_M1_M1, VSOXSEG6EI16_V, 0x0, 0x0 }, // 9089 |
| 16380 | { PseudoVSOXSEG6EI16_V_M1_M1_MASK, VSOXSEG6EI16_V, 0x0, 0x0 }, // 9090 |
| 16381 | { PseudoVSOXSEG6EI16_V_M2_M1, VSOXSEG6EI16_V, 0x0, 0x0 }, // 9091 |
| 16382 | { PseudoVSOXSEG6EI16_V_M2_M1_MASK, VSOXSEG6EI16_V, 0x0, 0x0 }, // 9092 |
| 16383 | { PseudoVSOXSEG6EI16_V_MF2_M1, VSOXSEG6EI16_V, 0x0, 0x0 }, // 9093 |
| 16384 | { PseudoVSOXSEG6EI16_V_MF2_M1_MASK, VSOXSEG6EI16_V, 0x0, 0x0 }, // 9094 |
| 16385 | { PseudoVSOXSEG6EI16_V_MF4_M1, VSOXSEG6EI16_V, 0x0, 0x0 }, // 9095 |
| 16386 | { PseudoVSOXSEG6EI16_V_MF4_M1_MASK, VSOXSEG6EI16_V, 0x0, 0x0 }, // 9096 |
| 16387 | { PseudoVSOXSEG6EI16_V_MF4_MF8, VSOXSEG6EI16_V, 0x5, 0x0 }, // 9097 |
| 16388 | { PseudoVSOXSEG6EI16_V_MF4_MF8_MASK, VSOXSEG6EI16_V, 0x5, 0x0 }, // 9098 |
| 16389 | { PseudoVSOXSEG6EI16_V_MF2_MF4, VSOXSEG6EI16_V, 0x6, 0x0 }, // 9099 |
| 16390 | { PseudoVSOXSEG6EI16_V_MF2_MF4_MASK, VSOXSEG6EI16_V, 0x6, 0x0 }, // 9100 |
| 16391 | { PseudoVSOXSEG6EI16_V_MF4_MF4, VSOXSEG6EI16_V, 0x6, 0x0 }, // 9101 |
| 16392 | { PseudoVSOXSEG6EI16_V_MF4_MF4_MASK, VSOXSEG6EI16_V, 0x6, 0x0 }, // 9102 |
| 16393 | { PseudoVSOXSEG6EI16_V_M1_MF2, VSOXSEG6EI16_V, 0x7, 0x0 }, // 9103 |
| 16394 | { PseudoVSOXSEG6EI16_V_M1_MF2_MASK, VSOXSEG6EI16_V, 0x7, 0x0 }, // 9104 |
| 16395 | { PseudoVSOXSEG6EI16_V_MF2_MF2, VSOXSEG6EI16_V, 0x7, 0x0 }, // 9105 |
| 16396 | { PseudoVSOXSEG6EI16_V_MF2_MF2_MASK, VSOXSEG6EI16_V, 0x7, 0x0 }, // 9106 |
| 16397 | { PseudoVSOXSEG6EI16_V_MF4_MF2, VSOXSEG6EI16_V, 0x7, 0x0 }, // 9107 |
| 16398 | { PseudoVSOXSEG6EI16_V_MF4_MF2_MASK, VSOXSEG6EI16_V, 0x7, 0x0 }, // 9108 |
| 16399 | { PseudoVSOXSEG6EI32_V_M1_M1, VSOXSEG6EI32_V, 0x0, 0x0 }, // 9109 |
| 16400 | { PseudoVSOXSEG6EI32_V_M1_M1_MASK, VSOXSEG6EI32_V, 0x0, 0x0 }, // 9110 |
| 16401 | { PseudoVSOXSEG6EI32_V_M2_M1, VSOXSEG6EI32_V, 0x0, 0x0 }, // 9111 |
| 16402 | { PseudoVSOXSEG6EI32_V_M2_M1_MASK, VSOXSEG6EI32_V, 0x0, 0x0 }, // 9112 |
| 16403 | { PseudoVSOXSEG6EI32_V_M4_M1, VSOXSEG6EI32_V, 0x0, 0x0 }, // 9113 |
| 16404 | { PseudoVSOXSEG6EI32_V_M4_M1_MASK, VSOXSEG6EI32_V, 0x0, 0x0 }, // 9114 |
| 16405 | { PseudoVSOXSEG6EI32_V_MF2_M1, VSOXSEG6EI32_V, 0x0, 0x0 }, // 9115 |
| 16406 | { PseudoVSOXSEG6EI32_V_MF2_M1_MASK, VSOXSEG6EI32_V, 0x0, 0x0 }, // 9116 |
| 16407 | { PseudoVSOXSEG6EI32_V_MF2_MF8, VSOXSEG6EI32_V, 0x5, 0x0 }, // 9117 |
| 16408 | { PseudoVSOXSEG6EI32_V_MF2_MF8_MASK, VSOXSEG6EI32_V, 0x5, 0x0 }, // 9118 |
| 16409 | { PseudoVSOXSEG6EI32_V_M1_MF4, VSOXSEG6EI32_V, 0x6, 0x0 }, // 9119 |
| 16410 | { PseudoVSOXSEG6EI32_V_M1_MF4_MASK, VSOXSEG6EI32_V, 0x6, 0x0 }, // 9120 |
| 16411 | { PseudoVSOXSEG6EI32_V_MF2_MF4, VSOXSEG6EI32_V, 0x6, 0x0 }, // 9121 |
| 16412 | { PseudoVSOXSEG6EI32_V_MF2_MF4_MASK, VSOXSEG6EI32_V, 0x6, 0x0 }, // 9122 |
| 16413 | { PseudoVSOXSEG6EI32_V_M1_MF2, VSOXSEG6EI32_V, 0x7, 0x0 }, // 9123 |
| 16414 | { PseudoVSOXSEG6EI32_V_M1_MF2_MASK, VSOXSEG6EI32_V, 0x7, 0x0 }, // 9124 |
| 16415 | { PseudoVSOXSEG6EI32_V_M2_MF2, VSOXSEG6EI32_V, 0x7, 0x0 }, // 9125 |
| 16416 | { PseudoVSOXSEG6EI32_V_M2_MF2_MASK, VSOXSEG6EI32_V, 0x7, 0x0 }, // 9126 |
| 16417 | { PseudoVSOXSEG6EI32_V_MF2_MF2, VSOXSEG6EI32_V, 0x7, 0x0 }, // 9127 |
| 16418 | { PseudoVSOXSEG6EI32_V_MF2_MF2_MASK, VSOXSEG6EI32_V, 0x7, 0x0 }, // 9128 |
| 16419 | { PseudoVSOXSEG6EI64_V_M1_M1, VSOXSEG6EI64_V, 0x0, 0x0 }, // 9129 |
| 16420 | { PseudoVSOXSEG6EI64_V_M1_M1_MASK, VSOXSEG6EI64_V, 0x0, 0x0 }, // 9130 |
| 16421 | { PseudoVSOXSEG6EI64_V_M2_M1, VSOXSEG6EI64_V, 0x0, 0x0 }, // 9131 |
| 16422 | { PseudoVSOXSEG6EI64_V_M2_M1_MASK, VSOXSEG6EI64_V, 0x0, 0x0 }, // 9132 |
| 16423 | { PseudoVSOXSEG6EI64_V_M4_M1, VSOXSEG6EI64_V, 0x0, 0x0 }, // 9133 |
| 16424 | { PseudoVSOXSEG6EI64_V_M4_M1_MASK, VSOXSEG6EI64_V, 0x0, 0x0 }, // 9134 |
| 16425 | { PseudoVSOXSEG6EI64_V_M8_M1, VSOXSEG6EI64_V, 0x0, 0x0 }, // 9135 |
| 16426 | { PseudoVSOXSEG6EI64_V_M8_M1_MASK, VSOXSEG6EI64_V, 0x0, 0x0 }, // 9136 |
| 16427 | { PseudoVSOXSEG6EI64_V_M1_MF8, VSOXSEG6EI64_V, 0x5, 0x0 }, // 9137 |
| 16428 | { PseudoVSOXSEG6EI64_V_M1_MF8_MASK, VSOXSEG6EI64_V, 0x5, 0x0 }, // 9138 |
| 16429 | { PseudoVSOXSEG6EI64_V_M1_MF4, VSOXSEG6EI64_V, 0x6, 0x0 }, // 9139 |
| 16430 | { PseudoVSOXSEG6EI64_V_M1_MF4_MASK, VSOXSEG6EI64_V, 0x6, 0x0 }, // 9140 |
| 16431 | { PseudoVSOXSEG6EI64_V_M2_MF4, VSOXSEG6EI64_V, 0x6, 0x0 }, // 9141 |
| 16432 | { PseudoVSOXSEG6EI64_V_M2_MF4_MASK, VSOXSEG6EI64_V, 0x6, 0x0 }, // 9142 |
| 16433 | { PseudoVSOXSEG6EI64_V_M1_MF2, VSOXSEG6EI64_V, 0x7, 0x0 }, // 9143 |
| 16434 | { PseudoVSOXSEG6EI64_V_M1_MF2_MASK, VSOXSEG6EI64_V, 0x7, 0x0 }, // 9144 |
| 16435 | { PseudoVSOXSEG6EI64_V_M2_MF2, VSOXSEG6EI64_V, 0x7, 0x0 }, // 9145 |
| 16436 | { PseudoVSOXSEG6EI64_V_M2_MF2_MASK, VSOXSEG6EI64_V, 0x7, 0x0 }, // 9146 |
| 16437 | { PseudoVSOXSEG6EI64_V_M4_MF2, VSOXSEG6EI64_V, 0x7, 0x0 }, // 9147 |
| 16438 | { PseudoVSOXSEG6EI64_V_M4_MF2_MASK, VSOXSEG6EI64_V, 0x7, 0x0 }, // 9148 |
| 16439 | { PseudoVSOXSEG6EI8_V_M1_M1, VSOXSEG6EI8_V, 0x0, 0x0 }, // 9149 |
| 16440 | { PseudoVSOXSEG6EI8_V_M1_M1_MASK, VSOXSEG6EI8_V, 0x0, 0x0 }, // 9150 |
| 16441 | { PseudoVSOXSEG6EI8_V_MF2_M1, VSOXSEG6EI8_V, 0x0, 0x0 }, // 9151 |
| 16442 | { PseudoVSOXSEG6EI8_V_MF2_M1_MASK, VSOXSEG6EI8_V, 0x0, 0x0 }, // 9152 |
| 16443 | { PseudoVSOXSEG6EI8_V_MF4_M1, VSOXSEG6EI8_V, 0x0, 0x0 }, // 9153 |
| 16444 | { PseudoVSOXSEG6EI8_V_MF4_M1_MASK, VSOXSEG6EI8_V, 0x0, 0x0 }, // 9154 |
| 16445 | { PseudoVSOXSEG6EI8_V_MF8_M1, VSOXSEG6EI8_V, 0x0, 0x0 }, // 9155 |
| 16446 | { PseudoVSOXSEG6EI8_V_MF8_M1_MASK, VSOXSEG6EI8_V, 0x0, 0x0 }, // 9156 |
| 16447 | { PseudoVSOXSEG6EI8_V_MF8_MF8, VSOXSEG6EI8_V, 0x5, 0x0 }, // 9157 |
| 16448 | { PseudoVSOXSEG6EI8_V_MF8_MF8_MASK, VSOXSEG6EI8_V, 0x5, 0x0 }, // 9158 |
| 16449 | { PseudoVSOXSEG6EI8_V_MF4_MF4, VSOXSEG6EI8_V, 0x6, 0x0 }, // 9159 |
| 16450 | { PseudoVSOXSEG6EI8_V_MF4_MF4_MASK, VSOXSEG6EI8_V, 0x6, 0x0 }, // 9160 |
| 16451 | { PseudoVSOXSEG6EI8_V_MF8_MF4, VSOXSEG6EI8_V, 0x6, 0x0 }, // 9161 |
| 16452 | { PseudoVSOXSEG6EI8_V_MF8_MF4_MASK, VSOXSEG6EI8_V, 0x6, 0x0 }, // 9162 |
| 16453 | { PseudoVSOXSEG6EI8_V_MF2_MF2, VSOXSEG6EI8_V, 0x7, 0x0 }, // 9163 |
| 16454 | { PseudoVSOXSEG6EI8_V_MF2_MF2_MASK, VSOXSEG6EI8_V, 0x7, 0x0 }, // 9164 |
| 16455 | { PseudoVSOXSEG6EI8_V_MF4_MF2, VSOXSEG6EI8_V, 0x7, 0x0 }, // 9165 |
| 16456 | { PseudoVSOXSEG6EI8_V_MF4_MF2_MASK, VSOXSEG6EI8_V, 0x7, 0x0 }, // 9166 |
| 16457 | { PseudoVSOXSEG6EI8_V_MF8_MF2, VSOXSEG6EI8_V, 0x7, 0x0 }, // 9167 |
| 16458 | { PseudoVSOXSEG6EI8_V_MF8_MF2_MASK, VSOXSEG6EI8_V, 0x7, 0x0 }, // 9168 |
| 16459 | { PseudoVSOXSEG7EI16_V_M1_M1, VSOXSEG7EI16_V, 0x0, 0x0 }, // 9169 |
| 16460 | { PseudoVSOXSEG7EI16_V_M1_M1_MASK, VSOXSEG7EI16_V, 0x0, 0x0 }, // 9170 |
| 16461 | { PseudoVSOXSEG7EI16_V_M2_M1, VSOXSEG7EI16_V, 0x0, 0x0 }, // 9171 |
| 16462 | { PseudoVSOXSEG7EI16_V_M2_M1_MASK, VSOXSEG7EI16_V, 0x0, 0x0 }, // 9172 |
| 16463 | { PseudoVSOXSEG7EI16_V_MF2_M1, VSOXSEG7EI16_V, 0x0, 0x0 }, // 9173 |
| 16464 | { PseudoVSOXSEG7EI16_V_MF2_M1_MASK, VSOXSEG7EI16_V, 0x0, 0x0 }, // 9174 |
| 16465 | { PseudoVSOXSEG7EI16_V_MF4_M1, VSOXSEG7EI16_V, 0x0, 0x0 }, // 9175 |
| 16466 | { PseudoVSOXSEG7EI16_V_MF4_M1_MASK, VSOXSEG7EI16_V, 0x0, 0x0 }, // 9176 |
| 16467 | { PseudoVSOXSEG7EI16_V_MF4_MF8, VSOXSEG7EI16_V, 0x5, 0x0 }, // 9177 |
| 16468 | { PseudoVSOXSEG7EI16_V_MF4_MF8_MASK, VSOXSEG7EI16_V, 0x5, 0x0 }, // 9178 |
| 16469 | { PseudoVSOXSEG7EI16_V_MF2_MF4, VSOXSEG7EI16_V, 0x6, 0x0 }, // 9179 |
| 16470 | { PseudoVSOXSEG7EI16_V_MF2_MF4_MASK, VSOXSEG7EI16_V, 0x6, 0x0 }, // 9180 |
| 16471 | { PseudoVSOXSEG7EI16_V_MF4_MF4, VSOXSEG7EI16_V, 0x6, 0x0 }, // 9181 |
| 16472 | { PseudoVSOXSEG7EI16_V_MF4_MF4_MASK, VSOXSEG7EI16_V, 0x6, 0x0 }, // 9182 |
| 16473 | { PseudoVSOXSEG7EI16_V_M1_MF2, VSOXSEG7EI16_V, 0x7, 0x0 }, // 9183 |
| 16474 | { PseudoVSOXSEG7EI16_V_M1_MF2_MASK, VSOXSEG7EI16_V, 0x7, 0x0 }, // 9184 |
| 16475 | { PseudoVSOXSEG7EI16_V_MF2_MF2, VSOXSEG7EI16_V, 0x7, 0x0 }, // 9185 |
| 16476 | { PseudoVSOXSEG7EI16_V_MF2_MF2_MASK, VSOXSEG7EI16_V, 0x7, 0x0 }, // 9186 |
| 16477 | { PseudoVSOXSEG7EI16_V_MF4_MF2, VSOXSEG7EI16_V, 0x7, 0x0 }, // 9187 |
| 16478 | { PseudoVSOXSEG7EI16_V_MF4_MF2_MASK, VSOXSEG7EI16_V, 0x7, 0x0 }, // 9188 |
| 16479 | { PseudoVSOXSEG7EI32_V_M1_M1, VSOXSEG7EI32_V, 0x0, 0x0 }, // 9189 |
| 16480 | { PseudoVSOXSEG7EI32_V_M1_M1_MASK, VSOXSEG7EI32_V, 0x0, 0x0 }, // 9190 |
| 16481 | { PseudoVSOXSEG7EI32_V_M2_M1, VSOXSEG7EI32_V, 0x0, 0x0 }, // 9191 |
| 16482 | { PseudoVSOXSEG7EI32_V_M2_M1_MASK, VSOXSEG7EI32_V, 0x0, 0x0 }, // 9192 |
| 16483 | { PseudoVSOXSEG7EI32_V_M4_M1, VSOXSEG7EI32_V, 0x0, 0x0 }, // 9193 |
| 16484 | { PseudoVSOXSEG7EI32_V_M4_M1_MASK, VSOXSEG7EI32_V, 0x0, 0x0 }, // 9194 |
| 16485 | { PseudoVSOXSEG7EI32_V_MF2_M1, VSOXSEG7EI32_V, 0x0, 0x0 }, // 9195 |
| 16486 | { PseudoVSOXSEG7EI32_V_MF2_M1_MASK, VSOXSEG7EI32_V, 0x0, 0x0 }, // 9196 |
| 16487 | { PseudoVSOXSEG7EI32_V_MF2_MF8, VSOXSEG7EI32_V, 0x5, 0x0 }, // 9197 |
| 16488 | { PseudoVSOXSEG7EI32_V_MF2_MF8_MASK, VSOXSEG7EI32_V, 0x5, 0x0 }, // 9198 |
| 16489 | { PseudoVSOXSEG7EI32_V_M1_MF4, VSOXSEG7EI32_V, 0x6, 0x0 }, // 9199 |
| 16490 | { PseudoVSOXSEG7EI32_V_M1_MF4_MASK, VSOXSEG7EI32_V, 0x6, 0x0 }, // 9200 |
| 16491 | { PseudoVSOXSEG7EI32_V_MF2_MF4, VSOXSEG7EI32_V, 0x6, 0x0 }, // 9201 |
| 16492 | { PseudoVSOXSEG7EI32_V_MF2_MF4_MASK, VSOXSEG7EI32_V, 0x6, 0x0 }, // 9202 |
| 16493 | { PseudoVSOXSEG7EI32_V_M1_MF2, VSOXSEG7EI32_V, 0x7, 0x0 }, // 9203 |
| 16494 | { PseudoVSOXSEG7EI32_V_M1_MF2_MASK, VSOXSEG7EI32_V, 0x7, 0x0 }, // 9204 |
| 16495 | { PseudoVSOXSEG7EI32_V_M2_MF2, VSOXSEG7EI32_V, 0x7, 0x0 }, // 9205 |
| 16496 | { PseudoVSOXSEG7EI32_V_M2_MF2_MASK, VSOXSEG7EI32_V, 0x7, 0x0 }, // 9206 |
| 16497 | { PseudoVSOXSEG7EI32_V_MF2_MF2, VSOXSEG7EI32_V, 0x7, 0x0 }, // 9207 |
| 16498 | { PseudoVSOXSEG7EI32_V_MF2_MF2_MASK, VSOXSEG7EI32_V, 0x7, 0x0 }, // 9208 |
| 16499 | { PseudoVSOXSEG7EI64_V_M1_M1, VSOXSEG7EI64_V, 0x0, 0x0 }, // 9209 |
| 16500 | { PseudoVSOXSEG7EI64_V_M1_M1_MASK, VSOXSEG7EI64_V, 0x0, 0x0 }, // 9210 |
| 16501 | { PseudoVSOXSEG7EI64_V_M2_M1, VSOXSEG7EI64_V, 0x0, 0x0 }, // 9211 |
| 16502 | { PseudoVSOXSEG7EI64_V_M2_M1_MASK, VSOXSEG7EI64_V, 0x0, 0x0 }, // 9212 |
| 16503 | { PseudoVSOXSEG7EI64_V_M4_M1, VSOXSEG7EI64_V, 0x0, 0x0 }, // 9213 |
| 16504 | { PseudoVSOXSEG7EI64_V_M4_M1_MASK, VSOXSEG7EI64_V, 0x0, 0x0 }, // 9214 |
| 16505 | { PseudoVSOXSEG7EI64_V_M8_M1, VSOXSEG7EI64_V, 0x0, 0x0 }, // 9215 |
| 16506 | { PseudoVSOXSEG7EI64_V_M8_M1_MASK, VSOXSEG7EI64_V, 0x0, 0x0 }, // 9216 |
| 16507 | { PseudoVSOXSEG7EI64_V_M1_MF8, VSOXSEG7EI64_V, 0x5, 0x0 }, // 9217 |
| 16508 | { PseudoVSOXSEG7EI64_V_M1_MF8_MASK, VSOXSEG7EI64_V, 0x5, 0x0 }, // 9218 |
| 16509 | { PseudoVSOXSEG7EI64_V_M1_MF4, VSOXSEG7EI64_V, 0x6, 0x0 }, // 9219 |
| 16510 | { PseudoVSOXSEG7EI64_V_M1_MF4_MASK, VSOXSEG7EI64_V, 0x6, 0x0 }, // 9220 |
| 16511 | { PseudoVSOXSEG7EI64_V_M2_MF4, VSOXSEG7EI64_V, 0x6, 0x0 }, // 9221 |
| 16512 | { PseudoVSOXSEG7EI64_V_M2_MF4_MASK, VSOXSEG7EI64_V, 0x6, 0x0 }, // 9222 |
| 16513 | { PseudoVSOXSEG7EI64_V_M1_MF2, VSOXSEG7EI64_V, 0x7, 0x0 }, // 9223 |
| 16514 | { PseudoVSOXSEG7EI64_V_M1_MF2_MASK, VSOXSEG7EI64_V, 0x7, 0x0 }, // 9224 |
| 16515 | { PseudoVSOXSEG7EI64_V_M2_MF2, VSOXSEG7EI64_V, 0x7, 0x0 }, // 9225 |
| 16516 | { PseudoVSOXSEG7EI64_V_M2_MF2_MASK, VSOXSEG7EI64_V, 0x7, 0x0 }, // 9226 |
| 16517 | { PseudoVSOXSEG7EI64_V_M4_MF2, VSOXSEG7EI64_V, 0x7, 0x0 }, // 9227 |
| 16518 | { PseudoVSOXSEG7EI64_V_M4_MF2_MASK, VSOXSEG7EI64_V, 0x7, 0x0 }, // 9228 |
| 16519 | { PseudoVSOXSEG7EI8_V_M1_M1, VSOXSEG7EI8_V, 0x0, 0x0 }, // 9229 |
| 16520 | { PseudoVSOXSEG7EI8_V_M1_M1_MASK, VSOXSEG7EI8_V, 0x0, 0x0 }, // 9230 |
| 16521 | { PseudoVSOXSEG7EI8_V_MF2_M1, VSOXSEG7EI8_V, 0x0, 0x0 }, // 9231 |
| 16522 | { PseudoVSOXSEG7EI8_V_MF2_M1_MASK, VSOXSEG7EI8_V, 0x0, 0x0 }, // 9232 |
| 16523 | { PseudoVSOXSEG7EI8_V_MF4_M1, VSOXSEG7EI8_V, 0x0, 0x0 }, // 9233 |
| 16524 | { PseudoVSOXSEG7EI8_V_MF4_M1_MASK, VSOXSEG7EI8_V, 0x0, 0x0 }, // 9234 |
| 16525 | { PseudoVSOXSEG7EI8_V_MF8_M1, VSOXSEG7EI8_V, 0x0, 0x0 }, // 9235 |
| 16526 | { PseudoVSOXSEG7EI8_V_MF8_M1_MASK, VSOXSEG7EI8_V, 0x0, 0x0 }, // 9236 |
| 16527 | { PseudoVSOXSEG7EI8_V_MF8_MF8, VSOXSEG7EI8_V, 0x5, 0x0 }, // 9237 |
| 16528 | { PseudoVSOXSEG7EI8_V_MF8_MF8_MASK, VSOXSEG7EI8_V, 0x5, 0x0 }, // 9238 |
| 16529 | { PseudoVSOXSEG7EI8_V_MF4_MF4, VSOXSEG7EI8_V, 0x6, 0x0 }, // 9239 |
| 16530 | { PseudoVSOXSEG7EI8_V_MF4_MF4_MASK, VSOXSEG7EI8_V, 0x6, 0x0 }, // 9240 |
| 16531 | { PseudoVSOXSEG7EI8_V_MF8_MF4, VSOXSEG7EI8_V, 0x6, 0x0 }, // 9241 |
| 16532 | { PseudoVSOXSEG7EI8_V_MF8_MF4_MASK, VSOXSEG7EI8_V, 0x6, 0x0 }, // 9242 |
| 16533 | { PseudoVSOXSEG7EI8_V_MF2_MF2, VSOXSEG7EI8_V, 0x7, 0x0 }, // 9243 |
| 16534 | { PseudoVSOXSEG7EI8_V_MF2_MF2_MASK, VSOXSEG7EI8_V, 0x7, 0x0 }, // 9244 |
| 16535 | { PseudoVSOXSEG7EI8_V_MF4_MF2, VSOXSEG7EI8_V, 0x7, 0x0 }, // 9245 |
| 16536 | { PseudoVSOXSEG7EI8_V_MF4_MF2_MASK, VSOXSEG7EI8_V, 0x7, 0x0 }, // 9246 |
| 16537 | { PseudoVSOXSEG7EI8_V_MF8_MF2, VSOXSEG7EI8_V, 0x7, 0x0 }, // 9247 |
| 16538 | { PseudoVSOXSEG7EI8_V_MF8_MF2_MASK, VSOXSEG7EI8_V, 0x7, 0x0 }, // 9248 |
| 16539 | { PseudoVSOXSEG8EI16_V_M1_M1, VSOXSEG8EI16_V, 0x0, 0x0 }, // 9249 |
| 16540 | { PseudoVSOXSEG8EI16_V_M1_M1_MASK, VSOXSEG8EI16_V, 0x0, 0x0 }, // 9250 |
| 16541 | { PseudoVSOXSEG8EI16_V_M2_M1, VSOXSEG8EI16_V, 0x0, 0x0 }, // 9251 |
| 16542 | { PseudoVSOXSEG8EI16_V_M2_M1_MASK, VSOXSEG8EI16_V, 0x0, 0x0 }, // 9252 |
| 16543 | { PseudoVSOXSEG8EI16_V_MF2_M1, VSOXSEG8EI16_V, 0x0, 0x0 }, // 9253 |
| 16544 | { PseudoVSOXSEG8EI16_V_MF2_M1_MASK, VSOXSEG8EI16_V, 0x0, 0x0 }, // 9254 |
| 16545 | { PseudoVSOXSEG8EI16_V_MF4_M1, VSOXSEG8EI16_V, 0x0, 0x0 }, // 9255 |
| 16546 | { PseudoVSOXSEG8EI16_V_MF4_M1_MASK, VSOXSEG8EI16_V, 0x0, 0x0 }, // 9256 |
| 16547 | { PseudoVSOXSEG8EI16_V_MF4_MF8, VSOXSEG8EI16_V, 0x5, 0x0 }, // 9257 |
| 16548 | { PseudoVSOXSEG8EI16_V_MF4_MF8_MASK, VSOXSEG8EI16_V, 0x5, 0x0 }, // 9258 |
| 16549 | { PseudoVSOXSEG8EI16_V_MF2_MF4, VSOXSEG8EI16_V, 0x6, 0x0 }, // 9259 |
| 16550 | { PseudoVSOXSEG8EI16_V_MF2_MF4_MASK, VSOXSEG8EI16_V, 0x6, 0x0 }, // 9260 |
| 16551 | { PseudoVSOXSEG8EI16_V_MF4_MF4, VSOXSEG8EI16_V, 0x6, 0x0 }, // 9261 |
| 16552 | { PseudoVSOXSEG8EI16_V_MF4_MF4_MASK, VSOXSEG8EI16_V, 0x6, 0x0 }, // 9262 |
| 16553 | { PseudoVSOXSEG8EI16_V_M1_MF2, VSOXSEG8EI16_V, 0x7, 0x0 }, // 9263 |
| 16554 | { PseudoVSOXSEG8EI16_V_M1_MF2_MASK, VSOXSEG8EI16_V, 0x7, 0x0 }, // 9264 |
| 16555 | { PseudoVSOXSEG8EI16_V_MF2_MF2, VSOXSEG8EI16_V, 0x7, 0x0 }, // 9265 |
| 16556 | { PseudoVSOXSEG8EI16_V_MF2_MF2_MASK, VSOXSEG8EI16_V, 0x7, 0x0 }, // 9266 |
| 16557 | { PseudoVSOXSEG8EI16_V_MF4_MF2, VSOXSEG8EI16_V, 0x7, 0x0 }, // 9267 |
| 16558 | { PseudoVSOXSEG8EI16_V_MF4_MF2_MASK, VSOXSEG8EI16_V, 0x7, 0x0 }, // 9268 |
| 16559 | { PseudoVSOXSEG8EI32_V_M1_M1, VSOXSEG8EI32_V, 0x0, 0x0 }, // 9269 |
| 16560 | { PseudoVSOXSEG8EI32_V_M1_M1_MASK, VSOXSEG8EI32_V, 0x0, 0x0 }, // 9270 |
| 16561 | { PseudoVSOXSEG8EI32_V_M2_M1, VSOXSEG8EI32_V, 0x0, 0x0 }, // 9271 |
| 16562 | { PseudoVSOXSEG8EI32_V_M2_M1_MASK, VSOXSEG8EI32_V, 0x0, 0x0 }, // 9272 |
| 16563 | { PseudoVSOXSEG8EI32_V_M4_M1, VSOXSEG8EI32_V, 0x0, 0x0 }, // 9273 |
| 16564 | { PseudoVSOXSEG8EI32_V_M4_M1_MASK, VSOXSEG8EI32_V, 0x0, 0x0 }, // 9274 |
| 16565 | { PseudoVSOXSEG8EI32_V_MF2_M1, VSOXSEG8EI32_V, 0x0, 0x0 }, // 9275 |
| 16566 | { PseudoVSOXSEG8EI32_V_MF2_M1_MASK, VSOXSEG8EI32_V, 0x0, 0x0 }, // 9276 |
| 16567 | { PseudoVSOXSEG8EI32_V_MF2_MF8, VSOXSEG8EI32_V, 0x5, 0x0 }, // 9277 |
| 16568 | { PseudoVSOXSEG8EI32_V_MF2_MF8_MASK, VSOXSEG8EI32_V, 0x5, 0x0 }, // 9278 |
| 16569 | { PseudoVSOXSEG8EI32_V_M1_MF4, VSOXSEG8EI32_V, 0x6, 0x0 }, // 9279 |
| 16570 | { PseudoVSOXSEG8EI32_V_M1_MF4_MASK, VSOXSEG8EI32_V, 0x6, 0x0 }, // 9280 |
| 16571 | { PseudoVSOXSEG8EI32_V_MF2_MF4, VSOXSEG8EI32_V, 0x6, 0x0 }, // 9281 |
| 16572 | { PseudoVSOXSEG8EI32_V_MF2_MF4_MASK, VSOXSEG8EI32_V, 0x6, 0x0 }, // 9282 |
| 16573 | { PseudoVSOXSEG8EI32_V_M1_MF2, VSOXSEG8EI32_V, 0x7, 0x0 }, // 9283 |
| 16574 | { PseudoVSOXSEG8EI32_V_M1_MF2_MASK, VSOXSEG8EI32_V, 0x7, 0x0 }, // 9284 |
| 16575 | { PseudoVSOXSEG8EI32_V_M2_MF2, VSOXSEG8EI32_V, 0x7, 0x0 }, // 9285 |
| 16576 | { PseudoVSOXSEG8EI32_V_M2_MF2_MASK, VSOXSEG8EI32_V, 0x7, 0x0 }, // 9286 |
| 16577 | { PseudoVSOXSEG8EI32_V_MF2_MF2, VSOXSEG8EI32_V, 0x7, 0x0 }, // 9287 |
| 16578 | { PseudoVSOXSEG8EI32_V_MF2_MF2_MASK, VSOXSEG8EI32_V, 0x7, 0x0 }, // 9288 |
| 16579 | { PseudoVSOXSEG8EI64_V_M1_M1, VSOXSEG8EI64_V, 0x0, 0x0 }, // 9289 |
| 16580 | { PseudoVSOXSEG8EI64_V_M1_M1_MASK, VSOXSEG8EI64_V, 0x0, 0x0 }, // 9290 |
| 16581 | { PseudoVSOXSEG8EI64_V_M2_M1, VSOXSEG8EI64_V, 0x0, 0x0 }, // 9291 |
| 16582 | { PseudoVSOXSEG8EI64_V_M2_M1_MASK, VSOXSEG8EI64_V, 0x0, 0x0 }, // 9292 |
| 16583 | { PseudoVSOXSEG8EI64_V_M4_M1, VSOXSEG8EI64_V, 0x0, 0x0 }, // 9293 |
| 16584 | { PseudoVSOXSEG8EI64_V_M4_M1_MASK, VSOXSEG8EI64_V, 0x0, 0x0 }, // 9294 |
| 16585 | { PseudoVSOXSEG8EI64_V_M8_M1, VSOXSEG8EI64_V, 0x0, 0x0 }, // 9295 |
| 16586 | { PseudoVSOXSEG8EI64_V_M8_M1_MASK, VSOXSEG8EI64_V, 0x0, 0x0 }, // 9296 |
| 16587 | { PseudoVSOXSEG8EI64_V_M1_MF8, VSOXSEG8EI64_V, 0x5, 0x0 }, // 9297 |
| 16588 | { PseudoVSOXSEG8EI64_V_M1_MF8_MASK, VSOXSEG8EI64_V, 0x5, 0x0 }, // 9298 |
| 16589 | { PseudoVSOXSEG8EI64_V_M1_MF4, VSOXSEG8EI64_V, 0x6, 0x0 }, // 9299 |
| 16590 | { PseudoVSOXSEG8EI64_V_M1_MF4_MASK, VSOXSEG8EI64_V, 0x6, 0x0 }, // 9300 |
| 16591 | { PseudoVSOXSEG8EI64_V_M2_MF4, VSOXSEG8EI64_V, 0x6, 0x0 }, // 9301 |
| 16592 | { PseudoVSOXSEG8EI64_V_M2_MF4_MASK, VSOXSEG8EI64_V, 0x6, 0x0 }, // 9302 |
| 16593 | { PseudoVSOXSEG8EI64_V_M1_MF2, VSOXSEG8EI64_V, 0x7, 0x0 }, // 9303 |
| 16594 | { PseudoVSOXSEG8EI64_V_M1_MF2_MASK, VSOXSEG8EI64_V, 0x7, 0x0 }, // 9304 |
| 16595 | { PseudoVSOXSEG8EI64_V_M2_MF2, VSOXSEG8EI64_V, 0x7, 0x0 }, // 9305 |
| 16596 | { PseudoVSOXSEG8EI64_V_M2_MF2_MASK, VSOXSEG8EI64_V, 0x7, 0x0 }, // 9306 |
| 16597 | { PseudoVSOXSEG8EI64_V_M4_MF2, VSOXSEG8EI64_V, 0x7, 0x0 }, // 9307 |
| 16598 | { PseudoVSOXSEG8EI64_V_M4_MF2_MASK, VSOXSEG8EI64_V, 0x7, 0x0 }, // 9308 |
| 16599 | { PseudoVSOXSEG8EI8_V_M1_M1, VSOXSEG8EI8_V, 0x0, 0x0 }, // 9309 |
| 16600 | { PseudoVSOXSEG8EI8_V_M1_M1_MASK, VSOXSEG8EI8_V, 0x0, 0x0 }, // 9310 |
| 16601 | { PseudoVSOXSEG8EI8_V_MF2_M1, VSOXSEG8EI8_V, 0x0, 0x0 }, // 9311 |
| 16602 | { PseudoVSOXSEG8EI8_V_MF2_M1_MASK, VSOXSEG8EI8_V, 0x0, 0x0 }, // 9312 |
| 16603 | { PseudoVSOXSEG8EI8_V_MF4_M1, VSOXSEG8EI8_V, 0x0, 0x0 }, // 9313 |
| 16604 | { PseudoVSOXSEG8EI8_V_MF4_M1_MASK, VSOXSEG8EI8_V, 0x0, 0x0 }, // 9314 |
| 16605 | { PseudoVSOXSEG8EI8_V_MF8_M1, VSOXSEG8EI8_V, 0x0, 0x0 }, // 9315 |
| 16606 | { PseudoVSOXSEG8EI8_V_MF8_M1_MASK, VSOXSEG8EI8_V, 0x0, 0x0 }, // 9316 |
| 16607 | { PseudoVSOXSEG8EI8_V_MF8_MF8, VSOXSEG8EI8_V, 0x5, 0x0 }, // 9317 |
| 16608 | { PseudoVSOXSEG8EI8_V_MF8_MF8_MASK, VSOXSEG8EI8_V, 0x5, 0x0 }, // 9318 |
| 16609 | { PseudoVSOXSEG8EI8_V_MF4_MF4, VSOXSEG8EI8_V, 0x6, 0x0 }, // 9319 |
| 16610 | { PseudoVSOXSEG8EI8_V_MF4_MF4_MASK, VSOXSEG8EI8_V, 0x6, 0x0 }, // 9320 |
| 16611 | { PseudoVSOXSEG8EI8_V_MF8_MF4, VSOXSEG8EI8_V, 0x6, 0x0 }, // 9321 |
| 16612 | { PseudoVSOXSEG8EI8_V_MF8_MF4_MASK, VSOXSEG8EI8_V, 0x6, 0x0 }, // 9322 |
| 16613 | { PseudoVSOXSEG8EI8_V_MF2_MF2, VSOXSEG8EI8_V, 0x7, 0x0 }, // 9323 |
| 16614 | { PseudoVSOXSEG8EI8_V_MF2_MF2_MASK, VSOXSEG8EI8_V, 0x7, 0x0 }, // 9324 |
| 16615 | { PseudoVSOXSEG8EI8_V_MF4_MF2, VSOXSEG8EI8_V, 0x7, 0x0 }, // 9325 |
| 16616 | { PseudoVSOXSEG8EI8_V_MF4_MF2_MASK, VSOXSEG8EI8_V, 0x7, 0x0 }, // 9326 |
| 16617 | { PseudoVSOXSEG8EI8_V_MF8_MF2, VSOXSEG8EI8_V, 0x7, 0x0 }, // 9327 |
| 16618 | { PseudoVSOXSEG8EI8_V_MF8_MF2_MASK, VSOXSEG8EI8_V, 0x7, 0x0 }, // 9328 |
| 16619 | { PseudoVSRA_VI_M1, VSRA_VI, 0x0, 0x0 }, // 9329 |
| 16620 | { PseudoVSRA_VI_M1_MASK, VSRA_VI, 0x0, 0x0 }, // 9330 |
| 16621 | { PseudoVSRA_VI_M2, VSRA_VI, 0x1, 0x0 }, // 9331 |
| 16622 | { PseudoVSRA_VI_M2_MASK, VSRA_VI, 0x1, 0x0 }, // 9332 |
| 16623 | { PseudoVSRA_VI_M4, VSRA_VI, 0x2, 0x0 }, // 9333 |
| 16624 | { PseudoVSRA_VI_M4_MASK, VSRA_VI, 0x2, 0x0 }, // 9334 |
| 16625 | { PseudoVSRA_VI_M8, VSRA_VI, 0x3, 0x0 }, // 9335 |
| 16626 | { PseudoVSRA_VI_M8_MASK, VSRA_VI, 0x3, 0x0 }, // 9336 |
| 16627 | { PseudoVSRA_VI_MF8, VSRA_VI, 0x5, 0x0 }, // 9337 |
| 16628 | { PseudoVSRA_VI_MF8_MASK, VSRA_VI, 0x5, 0x0 }, // 9338 |
| 16629 | { PseudoVSRA_VI_MF4, VSRA_VI, 0x6, 0x0 }, // 9339 |
| 16630 | { PseudoVSRA_VI_MF4_MASK, VSRA_VI, 0x6, 0x0 }, // 9340 |
| 16631 | { PseudoVSRA_VI_MF2, VSRA_VI, 0x7, 0x0 }, // 9341 |
| 16632 | { PseudoVSRA_VI_MF2_MASK, VSRA_VI, 0x7, 0x0 }, // 9342 |
| 16633 | { PseudoVSRA_VV_M1, VSRA_VV, 0x0, 0x0 }, // 9343 |
| 16634 | { PseudoVSRA_VV_M1_MASK, VSRA_VV, 0x0, 0x0 }, // 9344 |
| 16635 | { PseudoVSRA_VV_M2, VSRA_VV, 0x1, 0x0 }, // 9345 |
| 16636 | { PseudoVSRA_VV_M2_MASK, VSRA_VV, 0x1, 0x0 }, // 9346 |
| 16637 | { PseudoVSRA_VV_M4, VSRA_VV, 0x2, 0x0 }, // 9347 |
| 16638 | { PseudoVSRA_VV_M4_MASK, VSRA_VV, 0x2, 0x0 }, // 9348 |
| 16639 | { PseudoVSRA_VV_M8, VSRA_VV, 0x3, 0x0 }, // 9349 |
| 16640 | { PseudoVSRA_VV_M8_MASK, VSRA_VV, 0x3, 0x0 }, // 9350 |
| 16641 | { PseudoVSRA_VV_MF8, VSRA_VV, 0x5, 0x0 }, // 9351 |
| 16642 | { PseudoVSRA_VV_MF8_MASK, VSRA_VV, 0x5, 0x0 }, // 9352 |
| 16643 | { PseudoVSRA_VV_MF4, VSRA_VV, 0x6, 0x0 }, // 9353 |
| 16644 | { PseudoVSRA_VV_MF4_MASK, VSRA_VV, 0x6, 0x0 }, // 9354 |
| 16645 | { PseudoVSRA_VV_MF2, VSRA_VV, 0x7, 0x0 }, // 9355 |
| 16646 | { PseudoVSRA_VV_MF2_MASK, VSRA_VV, 0x7, 0x0 }, // 9356 |
| 16647 | { PseudoVSRA_VX_M1, VSRA_VX, 0x0, 0x0 }, // 9357 |
| 16648 | { PseudoVSRA_VX_M1_MASK, VSRA_VX, 0x0, 0x0 }, // 9358 |
| 16649 | { PseudoVSRA_VX_M2, VSRA_VX, 0x1, 0x0 }, // 9359 |
| 16650 | { PseudoVSRA_VX_M2_MASK, VSRA_VX, 0x1, 0x0 }, // 9360 |
| 16651 | { PseudoVSRA_VX_M4, VSRA_VX, 0x2, 0x0 }, // 9361 |
| 16652 | { PseudoVSRA_VX_M4_MASK, VSRA_VX, 0x2, 0x0 }, // 9362 |
| 16653 | { PseudoVSRA_VX_M8, VSRA_VX, 0x3, 0x0 }, // 9363 |
| 16654 | { PseudoVSRA_VX_M8_MASK, VSRA_VX, 0x3, 0x0 }, // 9364 |
| 16655 | { PseudoVSRA_VX_MF8, VSRA_VX, 0x5, 0x0 }, // 9365 |
| 16656 | { PseudoVSRA_VX_MF8_MASK, VSRA_VX, 0x5, 0x0 }, // 9366 |
| 16657 | { PseudoVSRA_VX_MF4, VSRA_VX, 0x6, 0x0 }, // 9367 |
| 16658 | { PseudoVSRA_VX_MF4_MASK, VSRA_VX, 0x6, 0x0 }, // 9368 |
| 16659 | { PseudoVSRA_VX_MF2, VSRA_VX, 0x7, 0x0 }, // 9369 |
| 16660 | { PseudoVSRA_VX_MF2_MASK, VSRA_VX, 0x7, 0x0 }, // 9370 |
| 16661 | { PseudoVSRL_VI_M1, VSRL_VI, 0x0, 0x0 }, // 9371 |
| 16662 | { PseudoVSRL_VI_M1_MASK, VSRL_VI, 0x0, 0x0 }, // 9372 |
| 16663 | { PseudoVSRL_VI_M2, VSRL_VI, 0x1, 0x0 }, // 9373 |
| 16664 | { PseudoVSRL_VI_M2_MASK, VSRL_VI, 0x1, 0x0 }, // 9374 |
| 16665 | { PseudoVSRL_VI_M4, VSRL_VI, 0x2, 0x0 }, // 9375 |
| 16666 | { PseudoVSRL_VI_M4_MASK, VSRL_VI, 0x2, 0x0 }, // 9376 |
| 16667 | { PseudoVSRL_VI_M8, VSRL_VI, 0x3, 0x0 }, // 9377 |
| 16668 | { PseudoVSRL_VI_M8_MASK, VSRL_VI, 0x3, 0x0 }, // 9378 |
| 16669 | { PseudoVSRL_VI_MF8, VSRL_VI, 0x5, 0x0 }, // 9379 |
| 16670 | { PseudoVSRL_VI_MF8_MASK, VSRL_VI, 0x5, 0x0 }, // 9380 |
| 16671 | { PseudoVSRL_VI_MF4, VSRL_VI, 0x6, 0x0 }, // 9381 |
| 16672 | { PseudoVSRL_VI_MF4_MASK, VSRL_VI, 0x6, 0x0 }, // 9382 |
| 16673 | { PseudoVSRL_VI_MF2, VSRL_VI, 0x7, 0x0 }, // 9383 |
| 16674 | { PseudoVSRL_VI_MF2_MASK, VSRL_VI, 0x7, 0x0 }, // 9384 |
| 16675 | { PseudoVSRL_VV_M1, VSRL_VV, 0x0, 0x0 }, // 9385 |
| 16676 | { PseudoVSRL_VV_M1_MASK, VSRL_VV, 0x0, 0x0 }, // 9386 |
| 16677 | { PseudoVSRL_VV_M2, VSRL_VV, 0x1, 0x0 }, // 9387 |
| 16678 | { PseudoVSRL_VV_M2_MASK, VSRL_VV, 0x1, 0x0 }, // 9388 |
| 16679 | { PseudoVSRL_VV_M4, VSRL_VV, 0x2, 0x0 }, // 9389 |
| 16680 | { PseudoVSRL_VV_M4_MASK, VSRL_VV, 0x2, 0x0 }, // 9390 |
| 16681 | { PseudoVSRL_VV_M8, VSRL_VV, 0x3, 0x0 }, // 9391 |
| 16682 | { PseudoVSRL_VV_M8_MASK, VSRL_VV, 0x3, 0x0 }, // 9392 |
| 16683 | { PseudoVSRL_VV_MF8, VSRL_VV, 0x5, 0x0 }, // 9393 |
| 16684 | { PseudoVSRL_VV_MF8_MASK, VSRL_VV, 0x5, 0x0 }, // 9394 |
| 16685 | { PseudoVSRL_VV_MF4, VSRL_VV, 0x6, 0x0 }, // 9395 |
| 16686 | { PseudoVSRL_VV_MF4_MASK, VSRL_VV, 0x6, 0x0 }, // 9396 |
| 16687 | { PseudoVSRL_VV_MF2, VSRL_VV, 0x7, 0x0 }, // 9397 |
| 16688 | { PseudoVSRL_VV_MF2_MASK, VSRL_VV, 0x7, 0x0 }, // 9398 |
| 16689 | { PseudoVSRL_VX_M1, VSRL_VX, 0x0, 0x0 }, // 9399 |
| 16690 | { PseudoVSRL_VX_M1_MASK, VSRL_VX, 0x0, 0x0 }, // 9400 |
| 16691 | { PseudoVSRL_VX_M2, VSRL_VX, 0x1, 0x0 }, // 9401 |
| 16692 | { PseudoVSRL_VX_M2_MASK, VSRL_VX, 0x1, 0x0 }, // 9402 |
| 16693 | { PseudoVSRL_VX_M4, VSRL_VX, 0x2, 0x0 }, // 9403 |
| 16694 | { PseudoVSRL_VX_M4_MASK, VSRL_VX, 0x2, 0x0 }, // 9404 |
| 16695 | { PseudoVSRL_VX_M8, VSRL_VX, 0x3, 0x0 }, // 9405 |
| 16696 | { PseudoVSRL_VX_M8_MASK, VSRL_VX, 0x3, 0x0 }, // 9406 |
| 16697 | { PseudoVSRL_VX_MF8, VSRL_VX, 0x5, 0x0 }, // 9407 |
| 16698 | { PseudoVSRL_VX_MF8_MASK, VSRL_VX, 0x5, 0x0 }, // 9408 |
| 16699 | { PseudoVSRL_VX_MF4, VSRL_VX, 0x6, 0x0 }, // 9409 |
| 16700 | { PseudoVSRL_VX_MF4_MASK, VSRL_VX, 0x6, 0x0 }, // 9410 |
| 16701 | { PseudoVSRL_VX_MF2, VSRL_VX, 0x7, 0x0 }, // 9411 |
| 16702 | { PseudoVSRL_VX_MF2_MASK, VSRL_VX, 0x7, 0x0 }, // 9412 |
| 16703 | { PseudoVSSE16_V_M1, VSSE16_V, 0x0, 0x10 }, // 9413 |
| 16704 | { PseudoVSSE16_V_M1_MASK, VSSE16_V, 0x0, 0x10 }, // 9414 |
| 16705 | { PseudoVSSE16_V_M2, VSSE16_V, 0x1, 0x10 }, // 9415 |
| 16706 | { PseudoVSSE16_V_M2_MASK, VSSE16_V, 0x1, 0x10 }, // 9416 |
| 16707 | { PseudoVSSE16_V_M4, VSSE16_V, 0x2, 0x10 }, // 9417 |
| 16708 | { PseudoVSSE16_V_M4_MASK, VSSE16_V, 0x2, 0x10 }, // 9418 |
| 16709 | { PseudoVSSE16_V_M8, VSSE16_V, 0x3, 0x10 }, // 9419 |
| 16710 | { PseudoVSSE16_V_M8_MASK, VSSE16_V, 0x3, 0x10 }, // 9420 |
| 16711 | { PseudoVSSE16_V_MF4, VSSE16_V, 0x6, 0x10 }, // 9421 |
| 16712 | { PseudoVSSE16_V_MF4_MASK, VSSE16_V, 0x6, 0x10 }, // 9422 |
| 16713 | { PseudoVSSE16_V_MF2, VSSE16_V, 0x7, 0x10 }, // 9423 |
| 16714 | { PseudoVSSE16_V_MF2_MASK, VSSE16_V, 0x7, 0x10 }, // 9424 |
| 16715 | { PseudoVSSE32_V_M1, VSSE32_V, 0x0, 0x20 }, // 9425 |
| 16716 | { PseudoVSSE32_V_M1_MASK, VSSE32_V, 0x0, 0x20 }, // 9426 |
| 16717 | { PseudoVSSE32_V_M2, VSSE32_V, 0x1, 0x20 }, // 9427 |
| 16718 | { PseudoVSSE32_V_M2_MASK, VSSE32_V, 0x1, 0x20 }, // 9428 |
| 16719 | { PseudoVSSE32_V_M4, VSSE32_V, 0x2, 0x20 }, // 9429 |
| 16720 | { PseudoVSSE32_V_M4_MASK, VSSE32_V, 0x2, 0x20 }, // 9430 |
| 16721 | { PseudoVSSE32_V_M8, VSSE32_V, 0x3, 0x20 }, // 9431 |
| 16722 | { PseudoVSSE32_V_M8_MASK, VSSE32_V, 0x3, 0x20 }, // 9432 |
| 16723 | { PseudoVSSE32_V_MF2, VSSE32_V, 0x7, 0x20 }, // 9433 |
| 16724 | { PseudoVSSE32_V_MF2_MASK, VSSE32_V, 0x7, 0x20 }, // 9434 |
| 16725 | { PseudoVSSE64_V_M1, VSSE64_V, 0x0, 0x40 }, // 9435 |
| 16726 | { PseudoVSSE64_V_M1_MASK, VSSE64_V, 0x0, 0x40 }, // 9436 |
| 16727 | { PseudoVSSE64_V_M2, VSSE64_V, 0x1, 0x40 }, // 9437 |
| 16728 | { PseudoVSSE64_V_M2_MASK, VSSE64_V, 0x1, 0x40 }, // 9438 |
| 16729 | { PseudoVSSE64_V_M4, VSSE64_V, 0x2, 0x40 }, // 9439 |
| 16730 | { PseudoVSSE64_V_M4_MASK, VSSE64_V, 0x2, 0x40 }, // 9440 |
| 16731 | { PseudoVSSE64_V_M8, VSSE64_V, 0x3, 0x40 }, // 9441 |
| 16732 | { PseudoVSSE64_V_M8_MASK, VSSE64_V, 0x3, 0x40 }, // 9442 |
| 16733 | { PseudoVSSE8_V_M1, VSSE8_V, 0x0, 0x8 }, // 9443 |
| 16734 | { PseudoVSSE8_V_M1_MASK, VSSE8_V, 0x0, 0x8 }, // 9444 |
| 16735 | { PseudoVSSE8_V_M2, VSSE8_V, 0x1, 0x8 }, // 9445 |
| 16736 | { PseudoVSSE8_V_M2_MASK, VSSE8_V, 0x1, 0x8 }, // 9446 |
| 16737 | { PseudoVSSE8_V_M4, VSSE8_V, 0x2, 0x8 }, // 9447 |
| 16738 | { PseudoVSSE8_V_M4_MASK, VSSE8_V, 0x2, 0x8 }, // 9448 |
| 16739 | { PseudoVSSE8_V_M8, VSSE8_V, 0x3, 0x8 }, // 9449 |
| 16740 | { PseudoVSSE8_V_M8_MASK, VSSE8_V, 0x3, 0x8 }, // 9450 |
| 16741 | { PseudoVSSE8_V_MF8, VSSE8_V, 0x5, 0x8 }, // 9451 |
| 16742 | { PseudoVSSE8_V_MF8_MASK, VSSE8_V, 0x5, 0x8 }, // 9452 |
| 16743 | { PseudoVSSE8_V_MF4, VSSE8_V, 0x6, 0x8 }, // 9453 |
| 16744 | { PseudoVSSE8_V_MF4_MASK, VSSE8_V, 0x6, 0x8 }, // 9454 |
| 16745 | { PseudoVSSE8_V_MF2, VSSE8_V, 0x7, 0x8 }, // 9455 |
| 16746 | { PseudoVSSE8_V_MF2_MASK, VSSE8_V, 0x7, 0x8 }, // 9456 |
| 16747 | { PseudoVSSEG2E16_V_M1, VSSEG2E16_V, 0x0, 0x10 }, // 9457 |
| 16748 | { PseudoVSSEG2E16_V_M1_MASK, VSSEG2E16_V, 0x0, 0x10 }, // 9458 |
| 16749 | { PseudoVSSEG2E16_V_M2, VSSEG2E16_V, 0x1, 0x10 }, // 9459 |
| 16750 | { PseudoVSSEG2E16_V_M2_MASK, VSSEG2E16_V, 0x1, 0x10 }, // 9460 |
| 16751 | { PseudoVSSEG2E16_V_M4, VSSEG2E16_V, 0x2, 0x10 }, // 9461 |
| 16752 | { PseudoVSSEG2E16_V_M4_MASK, VSSEG2E16_V, 0x2, 0x10 }, // 9462 |
| 16753 | { PseudoVSSEG2E16_V_MF4, VSSEG2E16_V, 0x6, 0x10 }, // 9463 |
| 16754 | { PseudoVSSEG2E16_V_MF4_MASK, VSSEG2E16_V, 0x6, 0x10 }, // 9464 |
| 16755 | { PseudoVSSEG2E16_V_MF2, VSSEG2E16_V, 0x7, 0x10 }, // 9465 |
| 16756 | { PseudoVSSEG2E16_V_MF2_MASK, VSSEG2E16_V, 0x7, 0x10 }, // 9466 |
| 16757 | { PseudoVSSEG2E32_V_M1, VSSEG2E32_V, 0x0, 0x20 }, // 9467 |
| 16758 | { PseudoVSSEG2E32_V_M1_MASK, VSSEG2E32_V, 0x0, 0x20 }, // 9468 |
| 16759 | { PseudoVSSEG2E32_V_M2, VSSEG2E32_V, 0x1, 0x20 }, // 9469 |
| 16760 | { PseudoVSSEG2E32_V_M2_MASK, VSSEG2E32_V, 0x1, 0x20 }, // 9470 |
| 16761 | { PseudoVSSEG2E32_V_M4, VSSEG2E32_V, 0x2, 0x20 }, // 9471 |
| 16762 | { PseudoVSSEG2E32_V_M4_MASK, VSSEG2E32_V, 0x2, 0x20 }, // 9472 |
| 16763 | { PseudoVSSEG2E32_V_MF2, VSSEG2E32_V, 0x7, 0x20 }, // 9473 |
| 16764 | { PseudoVSSEG2E32_V_MF2_MASK, VSSEG2E32_V, 0x7, 0x20 }, // 9474 |
| 16765 | { PseudoVSSEG2E64_V_M1, VSSEG2E64_V, 0x0, 0x40 }, // 9475 |
| 16766 | { PseudoVSSEG2E64_V_M1_MASK, VSSEG2E64_V, 0x0, 0x40 }, // 9476 |
| 16767 | { PseudoVSSEG2E64_V_M2, VSSEG2E64_V, 0x1, 0x40 }, // 9477 |
| 16768 | { PseudoVSSEG2E64_V_M2_MASK, VSSEG2E64_V, 0x1, 0x40 }, // 9478 |
| 16769 | { PseudoVSSEG2E64_V_M4, VSSEG2E64_V, 0x2, 0x40 }, // 9479 |
| 16770 | { PseudoVSSEG2E64_V_M4_MASK, VSSEG2E64_V, 0x2, 0x40 }, // 9480 |
| 16771 | { PseudoVSSEG2E8_V_M1, VSSEG2E8_V, 0x0, 0x8 }, // 9481 |
| 16772 | { PseudoVSSEG2E8_V_M1_MASK, VSSEG2E8_V, 0x0, 0x8 }, // 9482 |
| 16773 | { PseudoVSSEG2E8_V_M2, VSSEG2E8_V, 0x1, 0x8 }, // 9483 |
| 16774 | { PseudoVSSEG2E8_V_M2_MASK, VSSEG2E8_V, 0x1, 0x8 }, // 9484 |
| 16775 | { PseudoVSSEG2E8_V_M4, VSSEG2E8_V, 0x2, 0x8 }, // 9485 |
| 16776 | { PseudoVSSEG2E8_V_M4_MASK, VSSEG2E8_V, 0x2, 0x8 }, // 9486 |
| 16777 | { PseudoVSSEG2E8_V_MF8, VSSEG2E8_V, 0x5, 0x8 }, // 9487 |
| 16778 | { PseudoVSSEG2E8_V_MF8_MASK, VSSEG2E8_V, 0x5, 0x8 }, // 9488 |
| 16779 | { PseudoVSSEG2E8_V_MF4, VSSEG2E8_V, 0x6, 0x8 }, // 9489 |
| 16780 | { PseudoVSSEG2E8_V_MF4_MASK, VSSEG2E8_V, 0x6, 0x8 }, // 9490 |
| 16781 | { PseudoVSSEG2E8_V_MF2, VSSEG2E8_V, 0x7, 0x8 }, // 9491 |
| 16782 | { PseudoVSSEG2E8_V_MF2_MASK, VSSEG2E8_V, 0x7, 0x8 }, // 9492 |
| 16783 | { PseudoVSSEG3E16_V_M1, VSSEG3E16_V, 0x0, 0x10 }, // 9493 |
| 16784 | { PseudoVSSEG3E16_V_M1_MASK, VSSEG3E16_V, 0x0, 0x10 }, // 9494 |
| 16785 | { PseudoVSSEG3E16_V_M2, VSSEG3E16_V, 0x1, 0x10 }, // 9495 |
| 16786 | { PseudoVSSEG3E16_V_M2_MASK, VSSEG3E16_V, 0x1, 0x10 }, // 9496 |
| 16787 | { PseudoVSSEG3E16_V_MF4, VSSEG3E16_V, 0x6, 0x10 }, // 9497 |
| 16788 | { PseudoVSSEG3E16_V_MF4_MASK, VSSEG3E16_V, 0x6, 0x10 }, // 9498 |
| 16789 | { PseudoVSSEG3E16_V_MF2, VSSEG3E16_V, 0x7, 0x10 }, // 9499 |
| 16790 | { PseudoVSSEG3E16_V_MF2_MASK, VSSEG3E16_V, 0x7, 0x10 }, // 9500 |
| 16791 | { PseudoVSSEG3E32_V_M1, VSSEG3E32_V, 0x0, 0x20 }, // 9501 |
| 16792 | { PseudoVSSEG3E32_V_M1_MASK, VSSEG3E32_V, 0x0, 0x20 }, // 9502 |
| 16793 | { PseudoVSSEG3E32_V_M2, VSSEG3E32_V, 0x1, 0x20 }, // 9503 |
| 16794 | { PseudoVSSEG3E32_V_M2_MASK, VSSEG3E32_V, 0x1, 0x20 }, // 9504 |
| 16795 | { PseudoVSSEG3E32_V_MF2, VSSEG3E32_V, 0x7, 0x20 }, // 9505 |
| 16796 | { PseudoVSSEG3E32_V_MF2_MASK, VSSEG3E32_V, 0x7, 0x20 }, // 9506 |
| 16797 | { PseudoVSSEG3E64_V_M1, VSSEG3E64_V, 0x0, 0x40 }, // 9507 |
| 16798 | { PseudoVSSEG3E64_V_M1_MASK, VSSEG3E64_V, 0x0, 0x40 }, // 9508 |
| 16799 | { PseudoVSSEG3E64_V_M2, VSSEG3E64_V, 0x1, 0x40 }, // 9509 |
| 16800 | { PseudoVSSEG3E64_V_M2_MASK, VSSEG3E64_V, 0x1, 0x40 }, // 9510 |
| 16801 | { PseudoVSSEG3E8_V_M1, VSSEG3E8_V, 0x0, 0x8 }, // 9511 |
| 16802 | { PseudoVSSEG3E8_V_M1_MASK, VSSEG3E8_V, 0x0, 0x8 }, // 9512 |
| 16803 | { PseudoVSSEG3E8_V_M2, VSSEG3E8_V, 0x1, 0x8 }, // 9513 |
| 16804 | { PseudoVSSEG3E8_V_M2_MASK, VSSEG3E8_V, 0x1, 0x8 }, // 9514 |
| 16805 | { PseudoVSSEG3E8_V_MF8, VSSEG3E8_V, 0x5, 0x8 }, // 9515 |
| 16806 | { PseudoVSSEG3E8_V_MF8_MASK, VSSEG3E8_V, 0x5, 0x8 }, // 9516 |
| 16807 | { PseudoVSSEG3E8_V_MF4, VSSEG3E8_V, 0x6, 0x8 }, // 9517 |
| 16808 | { PseudoVSSEG3E8_V_MF4_MASK, VSSEG3E8_V, 0x6, 0x8 }, // 9518 |
| 16809 | { PseudoVSSEG3E8_V_MF2, VSSEG3E8_V, 0x7, 0x8 }, // 9519 |
| 16810 | { PseudoVSSEG3E8_V_MF2_MASK, VSSEG3E8_V, 0x7, 0x8 }, // 9520 |
| 16811 | { PseudoVSSEG4E16_V_M1, VSSEG4E16_V, 0x0, 0x10 }, // 9521 |
| 16812 | { PseudoVSSEG4E16_V_M1_MASK, VSSEG4E16_V, 0x0, 0x10 }, // 9522 |
| 16813 | { PseudoVSSEG4E16_V_M2, VSSEG4E16_V, 0x1, 0x10 }, // 9523 |
| 16814 | { PseudoVSSEG4E16_V_M2_MASK, VSSEG4E16_V, 0x1, 0x10 }, // 9524 |
| 16815 | { PseudoVSSEG4E16_V_MF4, VSSEG4E16_V, 0x6, 0x10 }, // 9525 |
| 16816 | { PseudoVSSEG4E16_V_MF4_MASK, VSSEG4E16_V, 0x6, 0x10 }, // 9526 |
| 16817 | { PseudoVSSEG4E16_V_MF2, VSSEG4E16_V, 0x7, 0x10 }, // 9527 |
| 16818 | { PseudoVSSEG4E16_V_MF2_MASK, VSSEG4E16_V, 0x7, 0x10 }, // 9528 |
| 16819 | { PseudoVSSEG4E32_V_M1, VSSEG4E32_V, 0x0, 0x20 }, // 9529 |
| 16820 | { PseudoVSSEG4E32_V_M1_MASK, VSSEG4E32_V, 0x0, 0x20 }, // 9530 |
| 16821 | { PseudoVSSEG4E32_V_M2, VSSEG4E32_V, 0x1, 0x20 }, // 9531 |
| 16822 | { PseudoVSSEG4E32_V_M2_MASK, VSSEG4E32_V, 0x1, 0x20 }, // 9532 |
| 16823 | { PseudoVSSEG4E32_V_MF2, VSSEG4E32_V, 0x7, 0x20 }, // 9533 |
| 16824 | { PseudoVSSEG4E32_V_MF2_MASK, VSSEG4E32_V, 0x7, 0x20 }, // 9534 |
| 16825 | { PseudoVSSEG4E64_V_M1, VSSEG4E64_V, 0x0, 0x40 }, // 9535 |
| 16826 | { PseudoVSSEG4E64_V_M1_MASK, VSSEG4E64_V, 0x0, 0x40 }, // 9536 |
| 16827 | { PseudoVSSEG4E64_V_M2, VSSEG4E64_V, 0x1, 0x40 }, // 9537 |
| 16828 | { PseudoVSSEG4E64_V_M2_MASK, VSSEG4E64_V, 0x1, 0x40 }, // 9538 |
| 16829 | { PseudoVSSEG4E8_V_M1, VSSEG4E8_V, 0x0, 0x8 }, // 9539 |
| 16830 | { PseudoVSSEG4E8_V_M1_MASK, VSSEG4E8_V, 0x0, 0x8 }, // 9540 |
| 16831 | { PseudoVSSEG4E8_V_M2, VSSEG4E8_V, 0x1, 0x8 }, // 9541 |
| 16832 | { PseudoVSSEG4E8_V_M2_MASK, VSSEG4E8_V, 0x1, 0x8 }, // 9542 |
| 16833 | { PseudoVSSEG4E8_V_MF8, VSSEG4E8_V, 0x5, 0x8 }, // 9543 |
| 16834 | { PseudoVSSEG4E8_V_MF8_MASK, VSSEG4E8_V, 0x5, 0x8 }, // 9544 |
| 16835 | { PseudoVSSEG4E8_V_MF4, VSSEG4E8_V, 0x6, 0x8 }, // 9545 |
| 16836 | { PseudoVSSEG4E8_V_MF4_MASK, VSSEG4E8_V, 0x6, 0x8 }, // 9546 |
| 16837 | { PseudoVSSEG4E8_V_MF2, VSSEG4E8_V, 0x7, 0x8 }, // 9547 |
| 16838 | { PseudoVSSEG4E8_V_MF2_MASK, VSSEG4E8_V, 0x7, 0x8 }, // 9548 |
| 16839 | { PseudoVSSEG5E16_V_M1, VSSEG5E16_V, 0x0, 0x10 }, // 9549 |
| 16840 | { PseudoVSSEG5E16_V_M1_MASK, VSSEG5E16_V, 0x0, 0x10 }, // 9550 |
| 16841 | { PseudoVSSEG5E16_V_MF4, VSSEG5E16_V, 0x6, 0x10 }, // 9551 |
| 16842 | { PseudoVSSEG5E16_V_MF4_MASK, VSSEG5E16_V, 0x6, 0x10 }, // 9552 |
| 16843 | { PseudoVSSEG5E16_V_MF2, VSSEG5E16_V, 0x7, 0x10 }, // 9553 |
| 16844 | { PseudoVSSEG5E16_V_MF2_MASK, VSSEG5E16_V, 0x7, 0x10 }, // 9554 |
| 16845 | { PseudoVSSEG5E32_V_M1, VSSEG5E32_V, 0x0, 0x20 }, // 9555 |
| 16846 | { PseudoVSSEG5E32_V_M1_MASK, VSSEG5E32_V, 0x0, 0x20 }, // 9556 |
| 16847 | { PseudoVSSEG5E32_V_MF2, VSSEG5E32_V, 0x7, 0x20 }, // 9557 |
| 16848 | { PseudoVSSEG5E32_V_MF2_MASK, VSSEG5E32_V, 0x7, 0x20 }, // 9558 |
| 16849 | { PseudoVSSEG5E64_V_M1, VSSEG5E64_V, 0x0, 0x40 }, // 9559 |
| 16850 | { PseudoVSSEG5E64_V_M1_MASK, VSSEG5E64_V, 0x0, 0x40 }, // 9560 |
| 16851 | { PseudoVSSEG5E8_V_M1, VSSEG5E8_V, 0x0, 0x8 }, // 9561 |
| 16852 | { PseudoVSSEG5E8_V_M1_MASK, VSSEG5E8_V, 0x0, 0x8 }, // 9562 |
| 16853 | { PseudoVSSEG5E8_V_MF8, VSSEG5E8_V, 0x5, 0x8 }, // 9563 |
| 16854 | { PseudoVSSEG5E8_V_MF8_MASK, VSSEG5E8_V, 0x5, 0x8 }, // 9564 |
| 16855 | { PseudoVSSEG5E8_V_MF4, VSSEG5E8_V, 0x6, 0x8 }, // 9565 |
| 16856 | { PseudoVSSEG5E8_V_MF4_MASK, VSSEG5E8_V, 0x6, 0x8 }, // 9566 |
| 16857 | { PseudoVSSEG5E8_V_MF2, VSSEG5E8_V, 0x7, 0x8 }, // 9567 |
| 16858 | { PseudoVSSEG5E8_V_MF2_MASK, VSSEG5E8_V, 0x7, 0x8 }, // 9568 |
| 16859 | { PseudoVSSEG6E16_V_M1, VSSEG6E16_V, 0x0, 0x10 }, // 9569 |
| 16860 | { PseudoVSSEG6E16_V_M1_MASK, VSSEG6E16_V, 0x0, 0x10 }, // 9570 |
| 16861 | { PseudoVSSEG6E16_V_MF4, VSSEG6E16_V, 0x6, 0x10 }, // 9571 |
| 16862 | { PseudoVSSEG6E16_V_MF4_MASK, VSSEG6E16_V, 0x6, 0x10 }, // 9572 |
| 16863 | { PseudoVSSEG6E16_V_MF2, VSSEG6E16_V, 0x7, 0x10 }, // 9573 |
| 16864 | { PseudoVSSEG6E16_V_MF2_MASK, VSSEG6E16_V, 0x7, 0x10 }, // 9574 |
| 16865 | { PseudoVSSEG6E32_V_M1, VSSEG6E32_V, 0x0, 0x20 }, // 9575 |
| 16866 | { PseudoVSSEG6E32_V_M1_MASK, VSSEG6E32_V, 0x0, 0x20 }, // 9576 |
| 16867 | { PseudoVSSEG6E32_V_MF2, VSSEG6E32_V, 0x7, 0x20 }, // 9577 |
| 16868 | { PseudoVSSEG6E32_V_MF2_MASK, VSSEG6E32_V, 0x7, 0x20 }, // 9578 |
| 16869 | { PseudoVSSEG6E64_V_M1, VSSEG6E64_V, 0x0, 0x40 }, // 9579 |
| 16870 | { PseudoVSSEG6E64_V_M1_MASK, VSSEG6E64_V, 0x0, 0x40 }, // 9580 |
| 16871 | { PseudoVSSEG6E8_V_M1, VSSEG6E8_V, 0x0, 0x8 }, // 9581 |
| 16872 | { PseudoVSSEG6E8_V_M1_MASK, VSSEG6E8_V, 0x0, 0x8 }, // 9582 |
| 16873 | { PseudoVSSEG6E8_V_MF8, VSSEG6E8_V, 0x5, 0x8 }, // 9583 |
| 16874 | { PseudoVSSEG6E8_V_MF8_MASK, VSSEG6E8_V, 0x5, 0x8 }, // 9584 |
| 16875 | { PseudoVSSEG6E8_V_MF4, VSSEG6E8_V, 0x6, 0x8 }, // 9585 |
| 16876 | { PseudoVSSEG6E8_V_MF4_MASK, VSSEG6E8_V, 0x6, 0x8 }, // 9586 |
| 16877 | { PseudoVSSEG6E8_V_MF2, VSSEG6E8_V, 0x7, 0x8 }, // 9587 |
| 16878 | { PseudoVSSEG6E8_V_MF2_MASK, VSSEG6E8_V, 0x7, 0x8 }, // 9588 |
| 16879 | { PseudoVSSEG7E16_V_M1, VSSEG7E16_V, 0x0, 0x10 }, // 9589 |
| 16880 | { PseudoVSSEG7E16_V_M1_MASK, VSSEG7E16_V, 0x0, 0x10 }, // 9590 |
| 16881 | { PseudoVSSEG7E16_V_MF4, VSSEG7E16_V, 0x6, 0x10 }, // 9591 |
| 16882 | { PseudoVSSEG7E16_V_MF4_MASK, VSSEG7E16_V, 0x6, 0x10 }, // 9592 |
| 16883 | { PseudoVSSEG7E16_V_MF2, VSSEG7E16_V, 0x7, 0x10 }, // 9593 |
| 16884 | { PseudoVSSEG7E16_V_MF2_MASK, VSSEG7E16_V, 0x7, 0x10 }, // 9594 |
| 16885 | { PseudoVSSEG7E32_V_M1, VSSEG7E32_V, 0x0, 0x20 }, // 9595 |
| 16886 | { PseudoVSSEG7E32_V_M1_MASK, VSSEG7E32_V, 0x0, 0x20 }, // 9596 |
| 16887 | { PseudoVSSEG7E32_V_MF2, VSSEG7E32_V, 0x7, 0x20 }, // 9597 |
| 16888 | { PseudoVSSEG7E32_V_MF2_MASK, VSSEG7E32_V, 0x7, 0x20 }, // 9598 |
| 16889 | { PseudoVSSEG7E64_V_M1, VSSEG7E64_V, 0x0, 0x40 }, // 9599 |
| 16890 | { PseudoVSSEG7E64_V_M1_MASK, VSSEG7E64_V, 0x0, 0x40 }, // 9600 |
| 16891 | { PseudoVSSEG7E8_V_M1, VSSEG7E8_V, 0x0, 0x8 }, // 9601 |
| 16892 | { PseudoVSSEG7E8_V_M1_MASK, VSSEG7E8_V, 0x0, 0x8 }, // 9602 |
| 16893 | { PseudoVSSEG7E8_V_MF8, VSSEG7E8_V, 0x5, 0x8 }, // 9603 |
| 16894 | { PseudoVSSEG7E8_V_MF8_MASK, VSSEG7E8_V, 0x5, 0x8 }, // 9604 |
| 16895 | { PseudoVSSEG7E8_V_MF4, VSSEG7E8_V, 0x6, 0x8 }, // 9605 |
| 16896 | { PseudoVSSEG7E8_V_MF4_MASK, VSSEG7E8_V, 0x6, 0x8 }, // 9606 |
| 16897 | { PseudoVSSEG7E8_V_MF2, VSSEG7E8_V, 0x7, 0x8 }, // 9607 |
| 16898 | { PseudoVSSEG7E8_V_MF2_MASK, VSSEG7E8_V, 0x7, 0x8 }, // 9608 |
| 16899 | { PseudoVSSEG8E16_V_M1, VSSEG8E16_V, 0x0, 0x10 }, // 9609 |
| 16900 | { PseudoVSSEG8E16_V_M1_MASK, VSSEG8E16_V, 0x0, 0x10 }, // 9610 |
| 16901 | { PseudoVSSEG8E16_V_MF4, VSSEG8E16_V, 0x6, 0x10 }, // 9611 |
| 16902 | { PseudoVSSEG8E16_V_MF4_MASK, VSSEG8E16_V, 0x6, 0x10 }, // 9612 |
| 16903 | { PseudoVSSEG8E16_V_MF2, VSSEG8E16_V, 0x7, 0x10 }, // 9613 |
| 16904 | { PseudoVSSEG8E16_V_MF2_MASK, VSSEG8E16_V, 0x7, 0x10 }, // 9614 |
| 16905 | { PseudoVSSEG8E32_V_M1, VSSEG8E32_V, 0x0, 0x20 }, // 9615 |
| 16906 | { PseudoVSSEG8E32_V_M1_MASK, VSSEG8E32_V, 0x0, 0x20 }, // 9616 |
| 16907 | { PseudoVSSEG8E32_V_MF2, VSSEG8E32_V, 0x7, 0x20 }, // 9617 |
| 16908 | { PseudoVSSEG8E32_V_MF2_MASK, VSSEG8E32_V, 0x7, 0x20 }, // 9618 |
| 16909 | { PseudoVSSEG8E64_V_M1, VSSEG8E64_V, 0x0, 0x40 }, // 9619 |
| 16910 | { PseudoVSSEG8E64_V_M1_MASK, VSSEG8E64_V, 0x0, 0x40 }, // 9620 |
| 16911 | { PseudoVSSEG8E8_V_M1, VSSEG8E8_V, 0x0, 0x8 }, // 9621 |
| 16912 | { PseudoVSSEG8E8_V_M1_MASK, VSSEG8E8_V, 0x0, 0x8 }, // 9622 |
| 16913 | { PseudoVSSEG8E8_V_MF8, VSSEG8E8_V, 0x5, 0x8 }, // 9623 |
| 16914 | { PseudoVSSEG8E8_V_MF8_MASK, VSSEG8E8_V, 0x5, 0x8 }, // 9624 |
| 16915 | { PseudoVSSEG8E8_V_MF4, VSSEG8E8_V, 0x6, 0x8 }, // 9625 |
| 16916 | { PseudoVSSEG8E8_V_MF4_MASK, VSSEG8E8_V, 0x6, 0x8 }, // 9626 |
| 16917 | { PseudoVSSEG8E8_V_MF2, VSSEG8E8_V, 0x7, 0x8 }, // 9627 |
| 16918 | { PseudoVSSEG8E8_V_MF2_MASK, VSSEG8E8_V, 0x7, 0x8 }, // 9628 |
| 16919 | { PseudoVSSRA_VI_M1, VSSRA_VI, 0x0, 0x0 }, // 9629 |
| 16920 | { PseudoVSSRA_VI_M1_MASK, VSSRA_VI, 0x0, 0x0 }, // 9630 |
| 16921 | { PseudoVSSRA_VI_M2, VSSRA_VI, 0x1, 0x0 }, // 9631 |
| 16922 | { PseudoVSSRA_VI_M2_MASK, VSSRA_VI, 0x1, 0x0 }, // 9632 |
| 16923 | { PseudoVSSRA_VI_M4, VSSRA_VI, 0x2, 0x0 }, // 9633 |
| 16924 | { PseudoVSSRA_VI_M4_MASK, VSSRA_VI, 0x2, 0x0 }, // 9634 |
| 16925 | { PseudoVSSRA_VI_M8, VSSRA_VI, 0x3, 0x0 }, // 9635 |
| 16926 | { PseudoVSSRA_VI_M8_MASK, VSSRA_VI, 0x3, 0x0 }, // 9636 |
| 16927 | { PseudoVSSRA_VI_MF8, VSSRA_VI, 0x5, 0x0 }, // 9637 |
| 16928 | { PseudoVSSRA_VI_MF8_MASK, VSSRA_VI, 0x5, 0x0 }, // 9638 |
| 16929 | { PseudoVSSRA_VI_MF4, VSSRA_VI, 0x6, 0x0 }, // 9639 |
| 16930 | { PseudoVSSRA_VI_MF4_MASK, VSSRA_VI, 0x6, 0x0 }, // 9640 |
| 16931 | { PseudoVSSRA_VI_MF2, VSSRA_VI, 0x7, 0x0 }, // 9641 |
| 16932 | { PseudoVSSRA_VI_MF2_MASK, VSSRA_VI, 0x7, 0x0 }, // 9642 |
| 16933 | { PseudoVSSRA_VV_M1, VSSRA_VV, 0x0, 0x0 }, // 9643 |
| 16934 | { PseudoVSSRA_VV_M1_MASK, VSSRA_VV, 0x0, 0x0 }, // 9644 |
| 16935 | { PseudoVSSRA_VV_M2, VSSRA_VV, 0x1, 0x0 }, // 9645 |
| 16936 | { PseudoVSSRA_VV_M2_MASK, VSSRA_VV, 0x1, 0x0 }, // 9646 |
| 16937 | { PseudoVSSRA_VV_M4, VSSRA_VV, 0x2, 0x0 }, // 9647 |
| 16938 | { PseudoVSSRA_VV_M4_MASK, VSSRA_VV, 0x2, 0x0 }, // 9648 |
| 16939 | { PseudoVSSRA_VV_M8, VSSRA_VV, 0x3, 0x0 }, // 9649 |
| 16940 | { PseudoVSSRA_VV_M8_MASK, VSSRA_VV, 0x3, 0x0 }, // 9650 |
| 16941 | { PseudoVSSRA_VV_MF8, VSSRA_VV, 0x5, 0x0 }, // 9651 |
| 16942 | { PseudoVSSRA_VV_MF8_MASK, VSSRA_VV, 0x5, 0x0 }, // 9652 |
| 16943 | { PseudoVSSRA_VV_MF4, VSSRA_VV, 0x6, 0x0 }, // 9653 |
| 16944 | { PseudoVSSRA_VV_MF4_MASK, VSSRA_VV, 0x6, 0x0 }, // 9654 |
| 16945 | { PseudoVSSRA_VV_MF2, VSSRA_VV, 0x7, 0x0 }, // 9655 |
| 16946 | { PseudoVSSRA_VV_MF2_MASK, VSSRA_VV, 0x7, 0x0 }, // 9656 |
| 16947 | { PseudoVSSRA_VX_M1, VSSRA_VX, 0x0, 0x0 }, // 9657 |
| 16948 | { PseudoVSSRA_VX_M1_MASK, VSSRA_VX, 0x0, 0x0 }, // 9658 |
| 16949 | { PseudoVSSRA_VX_M2, VSSRA_VX, 0x1, 0x0 }, // 9659 |
| 16950 | { PseudoVSSRA_VX_M2_MASK, VSSRA_VX, 0x1, 0x0 }, // 9660 |
| 16951 | { PseudoVSSRA_VX_M4, VSSRA_VX, 0x2, 0x0 }, // 9661 |
| 16952 | { PseudoVSSRA_VX_M4_MASK, VSSRA_VX, 0x2, 0x0 }, // 9662 |
| 16953 | { PseudoVSSRA_VX_M8, VSSRA_VX, 0x3, 0x0 }, // 9663 |
| 16954 | { PseudoVSSRA_VX_M8_MASK, VSSRA_VX, 0x3, 0x0 }, // 9664 |
| 16955 | { PseudoVSSRA_VX_MF8, VSSRA_VX, 0x5, 0x0 }, // 9665 |
| 16956 | { PseudoVSSRA_VX_MF8_MASK, VSSRA_VX, 0x5, 0x0 }, // 9666 |
| 16957 | { PseudoVSSRA_VX_MF4, VSSRA_VX, 0x6, 0x0 }, // 9667 |
| 16958 | { PseudoVSSRA_VX_MF4_MASK, VSSRA_VX, 0x6, 0x0 }, // 9668 |
| 16959 | { PseudoVSSRA_VX_MF2, VSSRA_VX, 0x7, 0x0 }, // 9669 |
| 16960 | { PseudoVSSRA_VX_MF2_MASK, VSSRA_VX, 0x7, 0x0 }, // 9670 |
| 16961 | { PseudoVSSRL_VI_M1, VSSRL_VI, 0x0, 0x0 }, // 9671 |
| 16962 | { PseudoVSSRL_VI_M1_MASK, VSSRL_VI, 0x0, 0x0 }, // 9672 |
| 16963 | { PseudoVSSRL_VI_M2, VSSRL_VI, 0x1, 0x0 }, // 9673 |
| 16964 | { PseudoVSSRL_VI_M2_MASK, VSSRL_VI, 0x1, 0x0 }, // 9674 |
| 16965 | { PseudoVSSRL_VI_M4, VSSRL_VI, 0x2, 0x0 }, // 9675 |
| 16966 | { PseudoVSSRL_VI_M4_MASK, VSSRL_VI, 0x2, 0x0 }, // 9676 |
| 16967 | { PseudoVSSRL_VI_M8, VSSRL_VI, 0x3, 0x0 }, // 9677 |
| 16968 | { PseudoVSSRL_VI_M8_MASK, VSSRL_VI, 0x3, 0x0 }, // 9678 |
| 16969 | { PseudoVSSRL_VI_MF8, VSSRL_VI, 0x5, 0x0 }, // 9679 |
| 16970 | { PseudoVSSRL_VI_MF8_MASK, VSSRL_VI, 0x5, 0x0 }, // 9680 |
| 16971 | { PseudoVSSRL_VI_MF4, VSSRL_VI, 0x6, 0x0 }, // 9681 |
| 16972 | { PseudoVSSRL_VI_MF4_MASK, VSSRL_VI, 0x6, 0x0 }, // 9682 |
| 16973 | { PseudoVSSRL_VI_MF2, VSSRL_VI, 0x7, 0x0 }, // 9683 |
| 16974 | { PseudoVSSRL_VI_MF2_MASK, VSSRL_VI, 0x7, 0x0 }, // 9684 |
| 16975 | { PseudoVSSRL_VV_M1, VSSRL_VV, 0x0, 0x0 }, // 9685 |
| 16976 | { PseudoVSSRL_VV_M1_MASK, VSSRL_VV, 0x0, 0x0 }, // 9686 |
| 16977 | { PseudoVSSRL_VV_M2, VSSRL_VV, 0x1, 0x0 }, // 9687 |
| 16978 | { PseudoVSSRL_VV_M2_MASK, VSSRL_VV, 0x1, 0x0 }, // 9688 |
| 16979 | { PseudoVSSRL_VV_M4, VSSRL_VV, 0x2, 0x0 }, // 9689 |
| 16980 | { PseudoVSSRL_VV_M4_MASK, VSSRL_VV, 0x2, 0x0 }, // 9690 |
| 16981 | { PseudoVSSRL_VV_M8, VSSRL_VV, 0x3, 0x0 }, // 9691 |
| 16982 | { PseudoVSSRL_VV_M8_MASK, VSSRL_VV, 0x3, 0x0 }, // 9692 |
| 16983 | { PseudoVSSRL_VV_MF8, VSSRL_VV, 0x5, 0x0 }, // 9693 |
| 16984 | { PseudoVSSRL_VV_MF8_MASK, VSSRL_VV, 0x5, 0x0 }, // 9694 |
| 16985 | { PseudoVSSRL_VV_MF4, VSSRL_VV, 0x6, 0x0 }, // 9695 |
| 16986 | { PseudoVSSRL_VV_MF4_MASK, VSSRL_VV, 0x6, 0x0 }, // 9696 |
| 16987 | { PseudoVSSRL_VV_MF2, VSSRL_VV, 0x7, 0x0 }, // 9697 |
| 16988 | { PseudoVSSRL_VV_MF2_MASK, VSSRL_VV, 0x7, 0x0 }, // 9698 |
| 16989 | { PseudoVSSRL_VX_M1, VSSRL_VX, 0x0, 0x0 }, // 9699 |
| 16990 | { PseudoVSSRL_VX_M1_MASK, VSSRL_VX, 0x0, 0x0 }, // 9700 |
| 16991 | { PseudoVSSRL_VX_M2, VSSRL_VX, 0x1, 0x0 }, // 9701 |
| 16992 | { PseudoVSSRL_VX_M2_MASK, VSSRL_VX, 0x1, 0x0 }, // 9702 |
| 16993 | { PseudoVSSRL_VX_M4, VSSRL_VX, 0x2, 0x0 }, // 9703 |
| 16994 | { PseudoVSSRL_VX_M4_MASK, VSSRL_VX, 0x2, 0x0 }, // 9704 |
| 16995 | { PseudoVSSRL_VX_M8, VSSRL_VX, 0x3, 0x0 }, // 9705 |
| 16996 | { PseudoVSSRL_VX_M8_MASK, VSSRL_VX, 0x3, 0x0 }, // 9706 |
| 16997 | { PseudoVSSRL_VX_MF8, VSSRL_VX, 0x5, 0x0 }, // 9707 |
| 16998 | { PseudoVSSRL_VX_MF8_MASK, VSSRL_VX, 0x5, 0x0 }, // 9708 |
| 16999 | { PseudoVSSRL_VX_MF4, VSSRL_VX, 0x6, 0x0 }, // 9709 |
| 17000 | { PseudoVSSRL_VX_MF4_MASK, VSSRL_VX, 0x6, 0x0 }, // 9710 |
| 17001 | { PseudoVSSRL_VX_MF2, VSSRL_VX, 0x7, 0x0 }, // 9711 |
| 17002 | { PseudoVSSRL_VX_MF2_MASK, VSSRL_VX, 0x7, 0x0 }, // 9712 |
| 17003 | { PseudoVSSSEG2E16_V_M1, VSSSEG2E16_V, 0x0, 0x10 }, // 9713 |
| 17004 | { PseudoVSSSEG2E16_V_M1_MASK, VSSSEG2E16_V, 0x0, 0x10 }, // 9714 |
| 17005 | { PseudoVSSSEG2E16_V_M2, VSSSEG2E16_V, 0x1, 0x10 }, // 9715 |
| 17006 | { PseudoVSSSEG2E16_V_M2_MASK, VSSSEG2E16_V, 0x1, 0x10 }, // 9716 |
| 17007 | { PseudoVSSSEG2E16_V_M4, VSSSEG2E16_V, 0x2, 0x10 }, // 9717 |
| 17008 | { PseudoVSSSEG2E16_V_M4_MASK, VSSSEG2E16_V, 0x2, 0x10 }, // 9718 |
| 17009 | { PseudoVSSSEG2E16_V_MF4, VSSSEG2E16_V, 0x6, 0x10 }, // 9719 |
| 17010 | { PseudoVSSSEG2E16_V_MF4_MASK, VSSSEG2E16_V, 0x6, 0x10 }, // 9720 |
| 17011 | { PseudoVSSSEG2E16_V_MF2, VSSSEG2E16_V, 0x7, 0x10 }, // 9721 |
| 17012 | { PseudoVSSSEG2E16_V_MF2_MASK, VSSSEG2E16_V, 0x7, 0x10 }, // 9722 |
| 17013 | { PseudoVSSSEG2E32_V_M1, VSSSEG2E32_V, 0x0, 0x20 }, // 9723 |
| 17014 | { PseudoVSSSEG2E32_V_M1_MASK, VSSSEG2E32_V, 0x0, 0x20 }, // 9724 |
| 17015 | { PseudoVSSSEG2E32_V_M2, VSSSEG2E32_V, 0x1, 0x20 }, // 9725 |
| 17016 | { PseudoVSSSEG2E32_V_M2_MASK, VSSSEG2E32_V, 0x1, 0x20 }, // 9726 |
| 17017 | { PseudoVSSSEG2E32_V_M4, VSSSEG2E32_V, 0x2, 0x20 }, // 9727 |
| 17018 | { PseudoVSSSEG2E32_V_M4_MASK, VSSSEG2E32_V, 0x2, 0x20 }, // 9728 |
| 17019 | { PseudoVSSSEG2E32_V_MF2, VSSSEG2E32_V, 0x7, 0x20 }, // 9729 |
| 17020 | { PseudoVSSSEG2E32_V_MF2_MASK, VSSSEG2E32_V, 0x7, 0x20 }, // 9730 |
| 17021 | { PseudoVSSSEG2E64_V_M1, VSSSEG2E64_V, 0x0, 0x40 }, // 9731 |
| 17022 | { PseudoVSSSEG2E64_V_M1_MASK, VSSSEG2E64_V, 0x0, 0x40 }, // 9732 |
| 17023 | { PseudoVSSSEG2E64_V_M2, VSSSEG2E64_V, 0x1, 0x40 }, // 9733 |
| 17024 | { PseudoVSSSEG2E64_V_M2_MASK, VSSSEG2E64_V, 0x1, 0x40 }, // 9734 |
| 17025 | { PseudoVSSSEG2E64_V_M4, VSSSEG2E64_V, 0x2, 0x40 }, // 9735 |
| 17026 | { PseudoVSSSEG2E64_V_M4_MASK, VSSSEG2E64_V, 0x2, 0x40 }, // 9736 |
| 17027 | { PseudoVSSSEG2E8_V_M1, VSSSEG2E8_V, 0x0, 0x8 }, // 9737 |
| 17028 | { PseudoVSSSEG2E8_V_M1_MASK, VSSSEG2E8_V, 0x0, 0x8 }, // 9738 |
| 17029 | { PseudoVSSSEG2E8_V_M2, VSSSEG2E8_V, 0x1, 0x8 }, // 9739 |
| 17030 | { PseudoVSSSEG2E8_V_M2_MASK, VSSSEG2E8_V, 0x1, 0x8 }, // 9740 |
| 17031 | { PseudoVSSSEG2E8_V_M4, VSSSEG2E8_V, 0x2, 0x8 }, // 9741 |
| 17032 | { PseudoVSSSEG2E8_V_M4_MASK, VSSSEG2E8_V, 0x2, 0x8 }, // 9742 |
| 17033 | { PseudoVSSSEG2E8_V_MF8, VSSSEG2E8_V, 0x5, 0x8 }, // 9743 |
| 17034 | { PseudoVSSSEG2E8_V_MF8_MASK, VSSSEG2E8_V, 0x5, 0x8 }, // 9744 |
| 17035 | { PseudoVSSSEG2E8_V_MF4, VSSSEG2E8_V, 0x6, 0x8 }, // 9745 |
| 17036 | { PseudoVSSSEG2E8_V_MF4_MASK, VSSSEG2E8_V, 0x6, 0x8 }, // 9746 |
| 17037 | { PseudoVSSSEG2E8_V_MF2, VSSSEG2E8_V, 0x7, 0x8 }, // 9747 |
| 17038 | { PseudoVSSSEG2E8_V_MF2_MASK, VSSSEG2E8_V, 0x7, 0x8 }, // 9748 |
| 17039 | { PseudoVSSSEG3E16_V_M1, VSSSEG3E16_V, 0x0, 0x10 }, // 9749 |
| 17040 | { PseudoVSSSEG3E16_V_M1_MASK, VSSSEG3E16_V, 0x0, 0x10 }, // 9750 |
| 17041 | { PseudoVSSSEG3E16_V_M2, VSSSEG3E16_V, 0x1, 0x10 }, // 9751 |
| 17042 | { PseudoVSSSEG3E16_V_M2_MASK, VSSSEG3E16_V, 0x1, 0x10 }, // 9752 |
| 17043 | { PseudoVSSSEG3E16_V_MF4, VSSSEG3E16_V, 0x6, 0x10 }, // 9753 |
| 17044 | { PseudoVSSSEG3E16_V_MF4_MASK, VSSSEG3E16_V, 0x6, 0x10 }, // 9754 |
| 17045 | { PseudoVSSSEG3E16_V_MF2, VSSSEG3E16_V, 0x7, 0x10 }, // 9755 |
| 17046 | { PseudoVSSSEG3E16_V_MF2_MASK, VSSSEG3E16_V, 0x7, 0x10 }, // 9756 |
| 17047 | { PseudoVSSSEG3E32_V_M1, VSSSEG3E32_V, 0x0, 0x20 }, // 9757 |
| 17048 | { PseudoVSSSEG3E32_V_M1_MASK, VSSSEG3E32_V, 0x0, 0x20 }, // 9758 |
| 17049 | { PseudoVSSSEG3E32_V_M2, VSSSEG3E32_V, 0x1, 0x20 }, // 9759 |
| 17050 | { PseudoVSSSEG3E32_V_M2_MASK, VSSSEG3E32_V, 0x1, 0x20 }, // 9760 |
| 17051 | { PseudoVSSSEG3E32_V_MF2, VSSSEG3E32_V, 0x7, 0x20 }, // 9761 |
| 17052 | { PseudoVSSSEG3E32_V_MF2_MASK, VSSSEG3E32_V, 0x7, 0x20 }, // 9762 |
| 17053 | { PseudoVSSSEG3E64_V_M1, VSSSEG3E64_V, 0x0, 0x40 }, // 9763 |
| 17054 | { PseudoVSSSEG3E64_V_M1_MASK, VSSSEG3E64_V, 0x0, 0x40 }, // 9764 |
| 17055 | { PseudoVSSSEG3E64_V_M2, VSSSEG3E64_V, 0x1, 0x40 }, // 9765 |
| 17056 | { PseudoVSSSEG3E64_V_M2_MASK, VSSSEG3E64_V, 0x1, 0x40 }, // 9766 |
| 17057 | { PseudoVSSSEG3E8_V_M1, VSSSEG3E8_V, 0x0, 0x8 }, // 9767 |
| 17058 | { PseudoVSSSEG3E8_V_M1_MASK, VSSSEG3E8_V, 0x0, 0x8 }, // 9768 |
| 17059 | { PseudoVSSSEG3E8_V_M2, VSSSEG3E8_V, 0x1, 0x8 }, // 9769 |
| 17060 | { PseudoVSSSEG3E8_V_M2_MASK, VSSSEG3E8_V, 0x1, 0x8 }, // 9770 |
| 17061 | { PseudoVSSSEG3E8_V_MF8, VSSSEG3E8_V, 0x5, 0x8 }, // 9771 |
| 17062 | { PseudoVSSSEG3E8_V_MF8_MASK, VSSSEG3E8_V, 0x5, 0x8 }, // 9772 |
| 17063 | { PseudoVSSSEG3E8_V_MF4, VSSSEG3E8_V, 0x6, 0x8 }, // 9773 |
| 17064 | { PseudoVSSSEG3E8_V_MF4_MASK, VSSSEG3E8_V, 0x6, 0x8 }, // 9774 |
| 17065 | { PseudoVSSSEG3E8_V_MF2, VSSSEG3E8_V, 0x7, 0x8 }, // 9775 |
| 17066 | { PseudoVSSSEG3E8_V_MF2_MASK, VSSSEG3E8_V, 0x7, 0x8 }, // 9776 |
| 17067 | { PseudoVSSSEG4E16_V_M1, VSSSEG4E16_V, 0x0, 0x10 }, // 9777 |
| 17068 | { PseudoVSSSEG4E16_V_M1_MASK, VSSSEG4E16_V, 0x0, 0x10 }, // 9778 |
| 17069 | { PseudoVSSSEG4E16_V_M2, VSSSEG4E16_V, 0x1, 0x10 }, // 9779 |
| 17070 | { PseudoVSSSEG4E16_V_M2_MASK, VSSSEG4E16_V, 0x1, 0x10 }, // 9780 |
| 17071 | { PseudoVSSSEG4E16_V_MF4, VSSSEG4E16_V, 0x6, 0x10 }, // 9781 |
| 17072 | { PseudoVSSSEG4E16_V_MF4_MASK, VSSSEG4E16_V, 0x6, 0x10 }, // 9782 |
| 17073 | { PseudoVSSSEG4E16_V_MF2, VSSSEG4E16_V, 0x7, 0x10 }, // 9783 |
| 17074 | { PseudoVSSSEG4E16_V_MF2_MASK, VSSSEG4E16_V, 0x7, 0x10 }, // 9784 |
| 17075 | { PseudoVSSSEG4E32_V_M1, VSSSEG4E32_V, 0x0, 0x20 }, // 9785 |
| 17076 | { PseudoVSSSEG4E32_V_M1_MASK, VSSSEG4E32_V, 0x0, 0x20 }, // 9786 |
| 17077 | { PseudoVSSSEG4E32_V_M2, VSSSEG4E32_V, 0x1, 0x20 }, // 9787 |
| 17078 | { PseudoVSSSEG4E32_V_M2_MASK, VSSSEG4E32_V, 0x1, 0x20 }, // 9788 |
| 17079 | { PseudoVSSSEG4E32_V_MF2, VSSSEG4E32_V, 0x7, 0x20 }, // 9789 |
| 17080 | { PseudoVSSSEG4E32_V_MF2_MASK, VSSSEG4E32_V, 0x7, 0x20 }, // 9790 |
| 17081 | { PseudoVSSSEG4E64_V_M1, VSSSEG4E64_V, 0x0, 0x40 }, // 9791 |
| 17082 | { PseudoVSSSEG4E64_V_M1_MASK, VSSSEG4E64_V, 0x0, 0x40 }, // 9792 |
| 17083 | { PseudoVSSSEG4E64_V_M2, VSSSEG4E64_V, 0x1, 0x40 }, // 9793 |
| 17084 | { PseudoVSSSEG4E64_V_M2_MASK, VSSSEG4E64_V, 0x1, 0x40 }, // 9794 |
| 17085 | { PseudoVSSSEG4E8_V_M1, VSSSEG4E8_V, 0x0, 0x8 }, // 9795 |
| 17086 | { PseudoVSSSEG4E8_V_M1_MASK, VSSSEG4E8_V, 0x0, 0x8 }, // 9796 |
| 17087 | { PseudoVSSSEG4E8_V_M2, VSSSEG4E8_V, 0x1, 0x8 }, // 9797 |
| 17088 | { PseudoVSSSEG4E8_V_M2_MASK, VSSSEG4E8_V, 0x1, 0x8 }, // 9798 |
| 17089 | { PseudoVSSSEG4E8_V_MF8, VSSSEG4E8_V, 0x5, 0x8 }, // 9799 |
| 17090 | { PseudoVSSSEG4E8_V_MF8_MASK, VSSSEG4E8_V, 0x5, 0x8 }, // 9800 |
| 17091 | { PseudoVSSSEG4E8_V_MF4, VSSSEG4E8_V, 0x6, 0x8 }, // 9801 |
| 17092 | { PseudoVSSSEG4E8_V_MF4_MASK, VSSSEG4E8_V, 0x6, 0x8 }, // 9802 |
| 17093 | { PseudoVSSSEG4E8_V_MF2, VSSSEG4E8_V, 0x7, 0x8 }, // 9803 |
| 17094 | { PseudoVSSSEG4E8_V_MF2_MASK, VSSSEG4E8_V, 0x7, 0x8 }, // 9804 |
| 17095 | { PseudoVSSSEG5E16_V_M1, VSSSEG5E16_V, 0x0, 0x10 }, // 9805 |
| 17096 | { PseudoVSSSEG5E16_V_M1_MASK, VSSSEG5E16_V, 0x0, 0x10 }, // 9806 |
| 17097 | { PseudoVSSSEG5E16_V_MF4, VSSSEG5E16_V, 0x6, 0x10 }, // 9807 |
| 17098 | { PseudoVSSSEG5E16_V_MF4_MASK, VSSSEG5E16_V, 0x6, 0x10 }, // 9808 |
| 17099 | { PseudoVSSSEG5E16_V_MF2, VSSSEG5E16_V, 0x7, 0x10 }, // 9809 |
| 17100 | { PseudoVSSSEG5E16_V_MF2_MASK, VSSSEG5E16_V, 0x7, 0x10 }, // 9810 |
| 17101 | { PseudoVSSSEG5E32_V_M1, VSSSEG5E32_V, 0x0, 0x20 }, // 9811 |
| 17102 | { PseudoVSSSEG5E32_V_M1_MASK, VSSSEG5E32_V, 0x0, 0x20 }, // 9812 |
| 17103 | { PseudoVSSSEG5E32_V_MF2, VSSSEG5E32_V, 0x7, 0x20 }, // 9813 |
| 17104 | { PseudoVSSSEG5E32_V_MF2_MASK, VSSSEG5E32_V, 0x7, 0x20 }, // 9814 |
| 17105 | { PseudoVSSSEG5E64_V_M1, VSSSEG5E64_V, 0x0, 0x40 }, // 9815 |
| 17106 | { PseudoVSSSEG5E64_V_M1_MASK, VSSSEG5E64_V, 0x0, 0x40 }, // 9816 |
| 17107 | { PseudoVSSSEG5E8_V_M1, VSSSEG5E8_V, 0x0, 0x8 }, // 9817 |
| 17108 | { PseudoVSSSEG5E8_V_M1_MASK, VSSSEG5E8_V, 0x0, 0x8 }, // 9818 |
| 17109 | { PseudoVSSSEG5E8_V_MF8, VSSSEG5E8_V, 0x5, 0x8 }, // 9819 |
| 17110 | { PseudoVSSSEG5E8_V_MF8_MASK, VSSSEG5E8_V, 0x5, 0x8 }, // 9820 |
| 17111 | { PseudoVSSSEG5E8_V_MF4, VSSSEG5E8_V, 0x6, 0x8 }, // 9821 |
| 17112 | { PseudoVSSSEG5E8_V_MF4_MASK, VSSSEG5E8_V, 0x6, 0x8 }, // 9822 |
| 17113 | { PseudoVSSSEG5E8_V_MF2, VSSSEG5E8_V, 0x7, 0x8 }, // 9823 |
| 17114 | { PseudoVSSSEG5E8_V_MF2_MASK, VSSSEG5E8_V, 0x7, 0x8 }, // 9824 |
| 17115 | { PseudoVSSSEG6E16_V_M1, VSSSEG6E16_V, 0x0, 0x10 }, // 9825 |
| 17116 | { PseudoVSSSEG6E16_V_M1_MASK, VSSSEG6E16_V, 0x0, 0x10 }, // 9826 |
| 17117 | { PseudoVSSSEG6E16_V_MF4, VSSSEG6E16_V, 0x6, 0x10 }, // 9827 |
| 17118 | { PseudoVSSSEG6E16_V_MF4_MASK, VSSSEG6E16_V, 0x6, 0x10 }, // 9828 |
| 17119 | { PseudoVSSSEG6E16_V_MF2, VSSSEG6E16_V, 0x7, 0x10 }, // 9829 |
| 17120 | { PseudoVSSSEG6E16_V_MF2_MASK, VSSSEG6E16_V, 0x7, 0x10 }, // 9830 |
| 17121 | { PseudoVSSSEG6E32_V_M1, VSSSEG6E32_V, 0x0, 0x20 }, // 9831 |
| 17122 | { PseudoVSSSEG6E32_V_M1_MASK, VSSSEG6E32_V, 0x0, 0x20 }, // 9832 |
| 17123 | { PseudoVSSSEG6E32_V_MF2, VSSSEG6E32_V, 0x7, 0x20 }, // 9833 |
| 17124 | { PseudoVSSSEG6E32_V_MF2_MASK, VSSSEG6E32_V, 0x7, 0x20 }, // 9834 |
| 17125 | { PseudoVSSSEG6E64_V_M1, VSSSEG6E64_V, 0x0, 0x40 }, // 9835 |
| 17126 | { PseudoVSSSEG6E64_V_M1_MASK, VSSSEG6E64_V, 0x0, 0x40 }, // 9836 |
| 17127 | { PseudoVSSSEG6E8_V_M1, VSSSEG6E8_V, 0x0, 0x8 }, // 9837 |
| 17128 | { PseudoVSSSEG6E8_V_M1_MASK, VSSSEG6E8_V, 0x0, 0x8 }, // 9838 |
| 17129 | { PseudoVSSSEG6E8_V_MF8, VSSSEG6E8_V, 0x5, 0x8 }, // 9839 |
| 17130 | { PseudoVSSSEG6E8_V_MF8_MASK, VSSSEG6E8_V, 0x5, 0x8 }, // 9840 |
| 17131 | { PseudoVSSSEG6E8_V_MF4, VSSSEG6E8_V, 0x6, 0x8 }, // 9841 |
| 17132 | { PseudoVSSSEG6E8_V_MF4_MASK, VSSSEG6E8_V, 0x6, 0x8 }, // 9842 |
| 17133 | { PseudoVSSSEG6E8_V_MF2, VSSSEG6E8_V, 0x7, 0x8 }, // 9843 |
| 17134 | { PseudoVSSSEG6E8_V_MF2_MASK, VSSSEG6E8_V, 0x7, 0x8 }, // 9844 |
| 17135 | { PseudoVSSSEG7E16_V_M1, VSSSEG7E16_V, 0x0, 0x10 }, // 9845 |
| 17136 | { PseudoVSSSEG7E16_V_M1_MASK, VSSSEG7E16_V, 0x0, 0x10 }, // 9846 |
| 17137 | { PseudoVSSSEG7E16_V_MF4, VSSSEG7E16_V, 0x6, 0x10 }, // 9847 |
| 17138 | { PseudoVSSSEG7E16_V_MF4_MASK, VSSSEG7E16_V, 0x6, 0x10 }, // 9848 |
| 17139 | { PseudoVSSSEG7E16_V_MF2, VSSSEG7E16_V, 0x7, 0x10 }, // 9849 |
| 17140 | { PseudoVSSSEG7E16_V_MF2_MASK, VSSSEG7E16_V, 0x7, 0x10 }, // 9850 |
| 17141 | { PseudoVSSSEG7E32_V_M1, VSSSEG7E32_V, 0x0, 0x20 }, // 9851 |
| 17142 | { PseudoVSSSEG7E32_V_M1_MASK, VSSSEG7E32_V, 0x0, 0x20 }, // 9852 |
| 17143 | { PseudoVSSSEG7E32_V_MF2, VSSSEG7E32_V, 0x7, 0x20 }, // 9853 |
| 17144 | { PseudoVSSSEG7E32_V_MF2_MASK, VSSSEG7E32_V, 0x7, 0x20 }, // 9854 |
| 17145 | { PseudoVSSSEG7E64_V_M1, VSSSEG7E64_V, 0x0, 0x40 }, // 9855 |
| 17146 | { PseudoVSSSEG7E64_V_M1_MASK, VSSSEG7E64_V, 0x0, 0x40 }, // 9856 |
| 17147 | { PseudoVSSSEG7E8_V_M1, VSSSEG7E8_V, 0x0, 0x8 }, // 9857 |
| 17148 | { PseudoVSSSEG7E8_V_M1_MASK, VSSSEG7E8_V, 0x0, 0x8 }, // 9858 |
| 17149 | { PseudoVSSSEG7E8_V_MF8, VSSSEG7E8_V, 0x5, 0x8 }, // 9859 |
| 17150 | { PseudoVSSSEG7E8_V_MF8_MASK, VSSSEG7E8_V, 0x5, 0x8 }, // 9860 |
| 17151 | { PseudoVSSSEG7E8_V_MF4, VSSSEG7E8_V, 0x6, 0x8 }, // 9861 |
| 17152 | { PseudoVSSSEG7E8_V_MF4_MASK, VSSSEG7E8_V, 0x6, 0x8 }, // 9862 |
| 17153 | { PseudoVSSSEG7E8_V_MF2, VSSSEG7E8_V, 0x7, 0x8 }, // 9863 |
| 17154 | { PseudoVSSSEG7E8_V_MF2_MASK, VSSSEG7E8_V, 0x7, 0x8 }, // 9864 |
| 17155 | { PseudoVSSSEG8E16_V_M1, VSSSEG8E16_V, 0x0, 0x10 }, // 9865 |
| 17156 | { PseudoVSSSEG8E16_V_M1_MASK, VSSSEG8E16_V, 0x0, 0x10 }, // 9866 |
| 17157 | { PseudoVSSSEG8E16_V_MF4, VSSSEG8E16_V, 0x6, 0x10 }, // 9867 |
| 17158 | { PseudoVSSSEG8E16_V_MF4_MASK, VSSSEG8E16_V, 0x6, 0x10 }, // 9868 |
| 17159 | { PseudoVSSSEG8E16_V_MF2, VSSSEG8E16_V, 0x7, 0x10 }, // 9869 |
| 17160 | { PseudoVSSSEG8E16_V_MF2_MASK, VSSSEG8E16_V, 0x7, 0x10 }, // 9870 |
| 17161 | { PseudoVSSSEG8E32_V_M1, VSSSEG8E32_V, 0x0, 0x20 }, // 9871 |
| 17162 | { PseudoVSSSEG8E32_V_M1_MASK, VSSSEG8E32_V, 0x0, 0x20 }, // 9872 |
| 17163 | { PseudoVSSSEG8E32_V_MF2, VSSSEG8E32_V, 0x7, 0x20 }, // 9873 |
| 17164 | { PseudoVSSSEG8E32_V_MF2_MASK, VSSSEG8E32_V, 0x7, 0x20 }, // 9874 |
| 17165 | { PseudoVSSSEG8E64_V_M1, VSSSEG8E64_V, 0x0, 0x40 }, // 9875 |
| 17166 | { PseudoVSSSEG8E64_V_M1_MASK, VSSSEG8E64_V, 0x0, 0x40 }, // 9876 |
| 17167 | { PseudoVSSSEG8E8_V_M1, VSSSEG8E8_V, 0x0, 0x8 }, // 9877 |
| 17168 | { PseudoVSSSEG8E8_V_M1_MASK, VSSSEG8E8_V, 0x0, 0x8 }, // 9878 |
| 17169 | { PseudoVSSSEG8E8_V_MF8, VSSSEG8E8_V, 0x5, 0x8 }, // 9879 |
| 17170 | { PseudoVSSSEG8E8_V_MF8_MASK, VSSSEG8E8_V, 0x5, 0x8 }, // 9880 |
| 17171 | { PseudoVSSSEG8E8_V_MF4, VSSSEG8E8_V, 0x6, 0x8 }, // 9881 |
| 17172 | { PseudoVSSSEG8E8_V_MF4_MASK, VSSSEG8E8_V, 0x6, 0x8 }, // 9882 |
| 17173 | { PseudoVSSSEG8E8_V_MF2, VSSSEG8E8_V, 0x7, 0x8 }, // 9883 |
| 17174 | { PseudoVSSSEG8E8_V_MF2_MASK, VSSSEG8E8_V, 0x7, 0x8 }, // 9884 |
| 17175 | { PseudoVSSUBU_VV_M1, VSSUBU_VV, 0x0, 0x0 }, // 9885 |
| 17176 | { PseudoVSSUBU_VV_M1_MASK, VSSUBU_VV, 0x0, 0x0 }, // 9886 |
| 17177 | { PseudoVSSUBU_VV_M2, VSSUBU_VV, 0x1, 0x0 }, // 9887 |
| 17178 | { PseudoVSSUBU_VV_M2_MASK, VSSUBU_VV, 0x1, 0x0 }, // 9888 |
| 17179 | { PseudoVSSUBU_VV_M4, VSSUBU_VV, 0x2, 0x0 }, // 9889 |
| 17180 | { PseudoVSSUBU_VV_M4_MASK, VSSUBU_VV, 0x2, 0x0 }, // 9890 |
| 17181 | { PseudoVSSUBU_VV_M8, VSSUBU_VV, 0x3, 0x0 }, // 9891 |
| 17182 | { PseudoVSSUBU_VV_M8_MASK, VSSUBU_VV, 0x3, 0x0 }, // 9892 |
| 17183 | { PseudoVSSUBU_VV_MF8, VSSUBU_VV, 0x5, 0x0 }, // 9893 |
| 17184 | { PseudoVSSUBU_VV_MF8_MASK, VSSUBU_VV, 0x5, 0x0 }, // 9894 |
| 17185 | { PseudoVSSUBU_VV_MF4, VSSUBU_VV, 0x6, 0x0 }, // 9895 |
| 17186 | { PseudoVSSUBU_VV_MF4_MASK, VSSUBU_VV, 0x6, 0x0 }, // 9896 |
| 17187 | { PseudoVSSUBU_VV_MF2, VSSUBU_VV, 0x7, 0x0 }, // 9897 |
| 17188 | { PseudoVSSUBU_VV_MF2_MASK, VSSUBU_VV, 0x7, 0x0 }, // 9898 |
| 17189 | { PseudoVSSUBU_VX_M1, VSSUBU_VX, 0x0, 0x0 }, // 9899 |
| 17190 | { PseudoVSSUBU_VX_M1_MASK, VSSUBU_VX, 0x0, 0x0 }, // 9900 |
| 17191 | { PseudoVSSUBU_VX_M2, VSSUBU_VX, 0x1, 0x0 }, // 9901 |
| 17192 | { PseudoVSSUBU_VX_M2_MASK, VSSUBU_VX, 0x1, 0x0 }, // 9902 |
| 17193 | { PseudoVSSUBU_VX_M4, VSSUBU_VX, 0x2, 0x0 }, // 9903 |
| 17194 | { PseudoVSSUBU_VX_M4_MASK, VSSUBU_VX, 0x2, 0x0 }, // 9904 |
| 17195 | { PseudoVSSUBU_VX_M8, VSSUBU_VX, 0x3, 0x0 }, // 9905 |
| 17196 | { PseudoVSSUBU_VX_M8_MASK, VSSUBU_VX, 0x3, 0x0 }, // 9906 |
| 17197 | { PseudoVSSUBU_VX_MF8, VSSUBU_VX, 0x5, 0x0 }, // 9907 |
| 17198 | { PseudoVSSUBU_VX_MF8_MASK, VSSUBU_VX, 0x5, 0x0 }, // 9908 |
| 17199 | { PseudoVSSUBU_VX_MF4, VSSUBU_VX, 0x6, 0x0 }, // 9909 |
| 17200 | { PseudoVSSUBU_VX_MF4_MASK, VSSUBU_VX, 0x6, 0x0 }, // 9910 |
| 17201 | { PseudoVSSUBU_VX_MF2, VSSUBU_VX, 0x7, 0x0 }, // 9911 |
| 17202 | { PseudoVSSUBU_VX_MF2_MASK, VSSUBU_VX, 0x7, 0x0 }, // 9912 |
| 17203 | { PseudoVSSUB_VV_M1, VSSUB_VV, 0x0, 0x0 }, // 9913 |
| 17204 | { PseudoVSSUB_VV_M1_MASK, VSSUB_VV, 0x0, 0x0 }, // 9914 |
| 17205 | { PseudoVSSUB_VV_M2, VSSUB_VV, 0x1, 0x0 }, // 9915 |
| 17206 | { PseudoVSSUB_VV_M2_MASK, VSSUB_VV, 0x1, 0x0 }, // 9916 |
| 17207 | { PseudoVSSUB_VV_M4, VSSUB_VV, 0x2, 0x0 }, // 9917 |
| 17208 | { PseudoVSSUB_VV_M4_MASK, VSSUB_VV, 0x2, 0x0 }, // 9918 |
| 17209 | { PseudoVSSUB_VV_M8, VSSUB_VV, 0x3, 0x0 }, // 9919 |
| 17210 | { PseudoVSSUB_VV_M8_MASK, VSSUB_VV, 0x3, 0x0 }, // 9920 |
| 17211 | { PseudoVSSUB_VV_MF8, VSSUB_VV, 0x5, 0x0 }, // 9921 |
| 17212 | { PseudoVSSUB_VV_MF8_MASK, VSSUB_VV, 0x5, 0x0 }, // 9922 |
| 17213 | { PseudoVSSUB_VV_MF4, VSSUB_VV, 0x6, 0x0 }, // 9923 |
| 17214 | { PseudoVSSUB_VV_MF4_MASK, VSSUB_VV, 0x6, 0x0 }, // 9924 |
| 17215 | { PseudoVSSUB_VV_MF2, VSSUB_VV, 0x7, 0x0 }, // 9925 |
| 17216 | { PseudoVSSUB_VV_MF2_MASK, VSSUB_VV, 0x7, 0x0 }, // 9926 |
| 17217 | { PseudoVSSUB_VX_M1, VSSUB_VX, 0x0, 0x0 }, // 9927 |
| 17218 | { PseudoVSSUB_VX_M1_MASK, VSSUB_VX, 0x0, 0x0 }, // 9928 |
| 17219 | { PseudoVSSUB_VX_M2, VSSUB_VX, 0x1, 0x0 }, // 9929 |
| 17220 | { PseudoVSSUB_VX_M2_MASK, VSSUB_VX, 0x1, 0x0 }, // 9930 |
| 17221 | { PseudoVSSUB_VX_M4, VSSUB_VX, 0x2, 0x0 }, // 9931 |
| 17222 | { PseudoVSSUB_VX_M4_MASK, VSSUB_VX, 0x2, 0x0 }, // 9932 |
| 17223 | { PseudoVSSUB_VX_M8, VSSUB_VX, 0x3, 0x0 }, // 9933 |
| 17224 | { PseudoVSSUB_VX_M8_MASK, VSSUB_VX, 0x3, 0x0 }, // 9934 |
| 17225 | { PseudoVSSUB_VX_MF8, VSSUB_VX, 0x5, 0x0 }, // 9935 |
| 17226 | { PseudoVSSUB_VX_MF8_MASK, VSSUB_VX, 0x5, 0x0 }, // 9936 |
| 17227 | { PseudoVSSUB_VX_MF4, VSSUB_VX, 0x6, 0x0 }, // 9937 |
| 17228 | { PseudoVSSUB_VX_MF4_MASK, VSSUB_VX, 0x6, 0x0 }, // 9938 |
| 17229 | { PseudoVSSUB_VX_MF2, VSSUB_VX, 0x7, 0x0 }, // 9939 |
| 17230 | { PseudoVSSUB_VX_MF2_MASK, VSSUB_VX, 0x7, 0x0 }, // 9940 |
| 17231 | { PseudoVSUB_VV_M1, VSUB_VV, 0x0, 0x0 }, // 9941 |
| 17232 | { PseudoVSUB_VV_M1_MASK, VSUB_VV, 0x0, 0x0 }, // 9942 |
| 17233 | { PseudoVSUB_VV_M2, VSUB_VV, 0x1, 0x0 }, // 9943 |
| 17234 | { PseudoVSUB_VV_M2_MASK, VSUB_VV, 0x1, 0x0 }, // 9944 |
| 17235 | { PseudoVSUB_VV_M4, VSUB_VV, 0x2, 0x0 }, // 9945 |
| 17236 | { PseudoVSUB_VV_M4_MASK, VSUB_VV, 0x2, 0x0 }, // 9946 |
| 17237 | { PseudoVSUB_VV_M8, VSUB_VV, 0x3, 0x0 }, // 9947 |
| 17238 | { PseudoVSUB_VV_M8_MASK, VSUB_VV, 0x3, 0x0 }, // 9948 |
| 17239 | { PseudoVSUB_VV_MF8, VSUB_VV, 0x5, 0x0 }, // 9949 |
| 17240 | { PseudoVSUB_VV_MF8_MASK, VSUB_VV, 0x5, 0x0 }, // 9950 |
| 17241 | { PseudoVSUB_VV_MF4, VSUB_VV, 0x6, 0x0 }, // 9951 |
| 17242 | { PseudoVSUB_VV_MF4_MASK, VSUB_VV, 0x6, 0x0 }, // 9952 |
| 17243 | { PseudoVSUB_VV_MF2, VSUB_VV, 0x7, 0x0 }, // 9953 |
| 17244 | { PseudoVSUB_VV_MF2_MASK, VSUB_VV, 0x7, 0x0 }, // 9954 |
| 17245 | { PseudoVSUB_VX_M1, VSUB_VX, 0x0, 0x0 }, // 9955 |
| 17246 | { PseudoVSUB_VX_M1_MASK, VSUB_VX, 0x0, 0x0 }, // 9956 |
| 17247 | { PseudoVSUB_VX_M2, VSUB_VX, 0x1, 0x0 }, // 9957 |
| 17248 | { PseudoVSUB_VX_M2_MASK, VSUB_VX, 0x1, 0x0 }, // 9958 |
| 17249 | { PseudoVSUB_VX_M4, VSUB_VX, 0x2, 0x0 }, // 9959 |
| 17250 | { PseudoVSUB_VX_M4_MASK, VSUB_VX, 0x2, 0x0 }, // 9960 |
| 17251 | { PseudoVSUB_VX_M8, VSUB_VX, 0x3, 0x0 }, // 9961 |
| 17252 | { PseudoVSUB_VX_M8_MASK, VSUB_VX, 0x3, 0x0 }, // 9962 |
| 17253 | { PseudoVSUB_VX_MF8, VSUB_VX, 0x5, 0x0 }, // 9963 |
| 17254 | { PseudoVSUB_VX_MF8_MASK, VSUB_VX, 0x5, 0x0 }, // 9964 |
| 17255 | { PseudoVSUB_VX_MF4, VSUB_VX, 0x6, 0x0 }, // 9965 |
| 17256 | { PseudoVSUB_VX_MF4_MASK, VSUB_VX, 0x6, 0x0 }, // 9966 |
| 17257 | { PseudoVSUB_VX_MF2, VSUB_VX, 0x7, 0x0 }, // 9967 |
| 17258 | { PseudoVSUB_VX_MF2_MASK, VSUB_VX, 0x7, 0x0 }, // 9968 |
| 17259 | { PseudoVSUXEI16_V_M1_M1, VSUXEI16_V, 0x0, 0x0 }, // 9969 |
| 17260 | { PseudoVSUXEI16_V_M1_M1_MASK, VSUXEI16_V, 0x0, 0x0 }, // 9970 |
| 17261 | { PseudoVSUXEI16_V_M2_M1, VSUXEI16_V, 0x0, 0x0 }, // 9971 |
| 17262 | { PseudoVSUXEI16_V_M2_M1_MASK, VSUXEI16_V, 0x0, 0x0 }, // 9972 |
| 17263 | { PseudoVSUXEI16_V_MF2_M1, VSUXEI16_V, 0x0, 0x0 }, // 9973 |
| 17264 | { PseudoVSUXEI16_V_MF2_M1_MASK, VSUXEI16_V, 0x0, 0x0 }, // 9974 |
| 17265 | { PseudoVSUXEI16_V_MF4_M1, VSUXEI16_V, 0x0, 0x0 }, // 9975 |
| 17266 | { PseudoVSUXEI16_V_MF4_M1_MASK, VSUXEI16_V, 0x0, 0x0 }, // 9976 |
| 17267 | { PseudoVSUXEI16_V_M1_M2, VSUXEI16_V, 0x1, 0x0 }, // 9977 |
| 17268 | { PseudoVSUXEI16_V_M1_M2_MASK, VSUXEI16_V, 0x1, 0x0 }, // 9978 |
| 17269 | { PseudoVSUXEI16_V_M2_M2, VSUXEI16_V, 0x1, 0x0 }, // 9979 |
| 17270 | { PseudoVSUXEI16_V_M2_M2_MASK, VSUXEI16_V, 0x1, 0x0 }, // 9980 |
| 17271 | { PseudoVSUXEI16_V_M4_M2, VSUXEI16_V, 0x1, 0x0 }, // 9981 |
| 17272 | { PseudoVSUXEI16_V_M4_M2_MASK, VSUXEI16_V, 0x1, 0x0 }, // 9982 |
| 17273 | { PseudoVSUXEI16_V_MF2_M2, VSUXEI16_V, 0x1, 0x0 }, // 9983 |
| 17274 | { PseudoVSUXEI16_V_MF2_M2_MASK, VSUXEI16_V, 0x1, 0x0 }, // 9984 |
| 17275 | { PseudoVSUXEI16_V_M1_M4, VSUXEI16_V, 0x2, 0x0 }, // 9985 |
| 17276 | { PseudoVSUXEI16_V_M1_M4_MASK, VSUXEI16_V, 0x2, 0x0 }, // 9986 |
| 17277 | { PseudoVSUXEI16_V_M2_M4, VSUXEI16_V, 0x2, 0x0 }, // 9987 |
| 17278 | { PseudoVSUXEI16_V_M2_M4_MASK, VSUXEI16_V, 0x2, 0x0 }, // 9988 |
| 17279 | { PseudoVSUXEI16_V_M4_M4, VSUXEI16_V, 0x2, 0x0 }, // 9989 |
| 17280 | { PseudoVSUXEI16_V_M4_M4_MASK, VSUXEI16_V, 0x2, 0x0 }, // 9990 |
| 17281 | { PseudoVSUXEI16_V_M8_M4, VSUXEI16_V, 0x2, 0x0 }, // 9991 |
| 17282 | { PseudoVSUXEI16_V_M8_M4_MASK, VSUXEI16_V, 0x2, 0x0 }, // 9992 |
| 17283 | { PseudoVSUXEI16_V_M2_M8, VSUXEI16_V, 0x3, 0x0 }, // 9993 |
| 17284 | { PseudoVSUXEI16_V_M2_M8_MASK, VSUXEI16_V, 0x3, 0x0 }, // 9994 |
| 17285 | { PseudoVSUXEI16_V_M4_M8, VSUXEI16_V, 0x3, 0x0 }, // 9995 |
| 17286 | { PseudoVSUXEI16_V_M4_M8_MASK, VSUXEI16_V, 0x3, 0x0 }, // 9996 |
| 17287 | { PseudoVSUXEI16_V_M8_M8, VSUXEI16_V, 0x3, 0x0 }, // 9997 |
| 17288 | { PseudoVSUXEI16_V_M8_M8_MASK, VSUXEI16_V, 0x3, 0x0 }, // 9998 |
| 17289 | { PseudoVSUXEI16_V_MF4_MF8, VSUXEI16_V, 0x5, 0x0 }, // 9999 |
| 17290 | { PseudoVSUXEI16_V_MF4_MF8_MASK, VSUXEI16_V, 0x5, 0x0 }, // 10000 |
| 17291 | { PseudoVSUXEI16_V_MF2_MF4, VSUXEI16_V, 0x6, 0x0 }, // 10001 |
| 17292 | { PseudoVSUXEI16_V_MF2_MF4_MASK, VSUXEI16_V, 0x6, 0x0 }, // 10002 |
| 17293 | { PseudoVSUXEI16_V_MF4_MF4, VSUXEI16_V, 0x6, 0x0 }, // 10003 |
| 17294 | { PseudoVSUXEI16_V_MF4_MF4_MASK, VSUXEI16_V, 0x6, 0x0 }, // 10004 |
| 17295 | { PseudoVSUXEI16_V_M1_MF2, VSUXEI16_V, 0x7, 0x0 }, // 10005 |
| 17296 | { PseudoVSUXEI16_V_M1_MF2_MASK, VSUXEI16_V, 0x7, 0x0 }, // 10006 |
| 17297 | { PseudoVSUXEI16_V_MF2_MF2, VSUXEI16_V, 0x7, 0x0 }, // 10007 |
| 17298 | { PseudoVSUXEI16_V_MF2_MF2_MASK, VSUXEI16_V, 0x7, 0x0 }, // 10008 |
| 17299 | { PseudoVSUXEI16_V_MF4_MF2, VSUXEI16_V, 0x7, 0x0 }, // 10009 |
| 17300 | { PseudoVSUXEI16_V_MF4_MF2_MASK, VSUXEI16_V, 0x7, 0x0 }, // 10010 |
| 17301 | { PseudoVSUXEI32_V_M1_M1, VSUXEI32_V, 0x0, 0x0 }, // 10011 |
| 17302 | { PseudoVSUXEI32_V_M1_M1_MASK, VSUXEI32_V, 0x0, 0x0 }, // 10012 |
| 17303 | { PseudoVSUXEI32_V_M2_M1, VSUXEI32_V, 0x0, 0x0 }, // 10013 |
| 17304 | { PseudoVSUXEI32_V_M2_M1_MASK, VSUXEI32_V, 0x0, 0x0 }, // 10014 |
| 17305 | { PseudoVSUXEI32_V_M4_M1, VSUXEI32_V, 0x0, 0x0 }, // 10015 |
| 17306 | { PseudoVSUXEI32_V_M4_M1_MASK, VSUXEI32_V, 0x0, 0x0 }, // 10016 |
| 17307 | { PseudoVSUXEI32_V_MF2_M1, VSUXEI32_V, 0x0, 0x0 }, // 10017 |
| 17308 | { PseudoVSUXEI32_V_MF2_M1_MASK, VSUXEI32_V, 0x0, 0x0 }, // 10018 |
| 17309 | { PseudoVSUXEI32_V_M1_M2, VSUXEI32_V, 0x1, 0x0 }, // 10019 |
| 17310 | { PseudoVSUXEI32_V_M1_M2_MASK, VSUXEI32_V, 0x1, 0x0 }, // 10020 |
| 17311 | { PseudoVSUXEI32_V_M2_M2, VSUXEI32_V, 0x1, 0x0 }, // 10021 |
| 17312 | { PseudoVSUXEI32_V_M2_M2_MASK, VSUXEI32_V, 0x1, 0x0 }, // 10022 |
| 17313 | { PseudoVSUXEI32_V_M4_M2, VSUXEI32_V, 0x1, 0x0 }, // 10023 |
| 17314 | { PseudoVSUXEI32_V_M4_M2_MASK, VSUXEI32_V, 0x1, 0x0 }, // 10024 |
| 17315 | { PseudoVSUXEI32_V_M8_M2, VSUXEI32_V, 0x1, 0x0 }, // 10025 |
| 17316 | { PseudoVSUXEI32_V_M8_M2_MASK, VSUXEI32_V, 0x1, 0x0 }, // 10026 |
| 17317 | { PseudoVSUXEI32_V_M2_M4, VSUXEI32_V, 0x2, 0x0 }, // 10027 |
| 17318 | { PseudoVSUXEI32_V_M2_M4_MASK, VSUXEI32_V, 0x2, 0x0 }, // 10028 |
| 17319 | { PseudoVSUXEI32_V_M4_M4, VSUXEI32_V, 0x2, 0x0 }, // 10029 |
| 17320 | { PseudoVSUXEI32_V_M4_M4_MASK, VSUXEI32_V, 0x2, 0x0 }, // 10030 |
| 17321 | { PseudoVSUXEI32_V_M8_M4, VSUXEI32_V, 0x2, 0x0 }, // 10031 |
| 17322 | { PseudoVSUXEI32_V_M8_M4_MASK, VSUXEI32_V, 0x2, 0x0 }, // 10032 |
| 17323 | { PseudoVSUXEI32_V_M4_M8, VSUXEI32_V, 0x3, 0x0 }, // 10033 |
| 17324 | { PseudoVSUXEI32_V_M4_M8_MASK, VSUXEI32_V, 0x3, 0x0 }, // 10034 |
| 17325 | { PseudoVSUXEI32_V_M8_M8, VSUXEI32_V, 0x3, 0x0 }, // 10035 |
| 17326 | { PseudoVSUXEI32_V_M8_M8_MASK, VSUXEI32_V, 0x3, 0x0 }, // 10036 |
| 17327 | { PseudoVSUXEI32_V_MF2_MF8, VSUXEI32_V, 0x5, 0x0 }, // 10037 |
| 17328 | { PseudoVSUXEI32_V_MF2_MF8_MASK, VSUXEI32_V, 0x5, 0x0 }, // 10038 |
| 17329 | { PseudoVSUXEI32_V_M1_MF4, VSUXEI32_V, 0x6, 0x0 }, // 10039 |
| 17330 | { PseudoVSUXEI32_V_M1_MF4_MASK, VSUXEI32_V, 0x6, 0x0 }, // 10040 |
| 17331 | { PseudoVSUXEI32_V_MF2_MF4, VSUXEI32_V, 0x6, 0x0 }, // 10041 |
| 17332 | { PseudoVSUXEI32_V_MF2_MF4_MASK, VSUXEI32_V, 0x6, 0x0 }, // 10042 |
| 17333 | { PseudoVSUXEI32_V_M1_MF2, VSUXEI32_V, 0x7, 0x0 }, // 10043 |
| 17334 | { PseudoVSUXEI32_V_M1_MF2_MASK, VSUXEI32_V, 0x7, 0x0 }, // 10044 |
| 17335 | { PseudoVSUXEI32_V_M2_MF2, VSUXEI32_V, 0x7, 0x0 }, // 10045 |
| 17336 | { PseudoVSUXEI32_V_M2_MF2_MASK, VSUXEI32_V, 0x7, 0x0 }, // 10046 |
| 17337 | { PseudoVSUXEI32_V_MF2_MF2, VSUXEI32_V, 0x7, 0x0 }, // 10047 |
| 17338 | { PseudoVSUXEI32_V_MF2_MF2_MASK, VSUXEI32_V, 0x7, 0x0 }, // 10048 |
| 17339 | { PseudoVSUXEI64_V_M1_M1, VSUXEI64_V, 0x0, 0x0 }, // 10049 |
| 17340 | { PseudoVSUXEI64_V_M1_M1_MASK, VSUXEI64_V, 0x0, 0x0 }, // 10050 |
| 17341 | { PseudoVSUXEI64_V_M2_M1, VSUXEI64_V, 0x0, 0x0 }, // 10051 |
| 17342 | { PseudoVSUXEI64_V_M2_M1_MASK, VSUXEI64_V, 0x0, 0x0 }, // 10052 |
| 17343 | { PseudoVSUXEI64_V_M4_M1, VSUXEI64_V, 0x0, 0x0 }, // 10053 |
| 17344 | { PseudoVSUXEI64_V_M4_M1_MASK, VSUXEI64_V, 0x0, 0x0 }, // 10054 |
| 17345 | { PseudoVSUXEI64_V_M8_M1, VSUXEI64_V, 0x0, 0x0 }, // 10055 |
| 17346 | { PseudoVSUXEI64_V_M8_M1_MASK, VSUXEI64_V, 0x0, 0x0 }, // 10056 |
| 17347 | { PseudoVSUXEI64_V_M2_M2, VSUXEI64_V, 0x1, 0x0 }, // 10057 |
| 17348 | { PseudoVSUXEI64_V_M2_M2_MASK, VSUXEI64_V, 0x1, 0x0 }, // 10058 |
| 17349 | { PseudoVSUXEI64_V_M4_M2, VSUXEI64_V, 0x1, 0x0 }, // 10059 |
| 17350 | { PseudoVSUXEI64_V_M4_M2_MASK, VSUXEI64_V, 0x1, 0x0 }, // 10060 |
| 17351 | { PseudoVSUXEI64_V_M8_M2, VSUXEI64_V, 0x1, 0x0 }, // 10061 |
| 17352 | { PseudoVSUXEI64_V_M8_M2_MASK, VSUXEI64_V, 0x1, 0x0 }, // 10062 |
| 17353 | { PseudoVSUXEI64_V_M4_M4, VSUXEI64_V, 0x2, 0x0 }, // 10063 |
| 17354 | { PseudoVSUXEI64_V_M4_M4_MASK, VSUXEI64_V, 0x2, 0x0 }, // 10064 |
| 17355 | { PseudoVSUXEI64_V_M8_M4, VSUXEI64_V, 0x2, 0x0 }, // 10065 |
| 17356 | { PseudoVSUXEI64_V_M8_M4_MASK, VSUXEI64_V, 0x2, 0x0 }, // 10066 |
| 17357 | { PseudoVSUXEI64_V_M8_M8, VSUXEI64_V, 0x3, 0x0 }, // 10067 |
| 17358 | { PseudoVSUXEI64_V_M8_M8_MASK, VSUXEI64_V, 0x3, 0x0 }, // 10068 |
| 17359 | { PseudoVSUXEI64_V_M1_MF8, VSUXEI64_V, 0x5, 0x0 }, // 10069 |
| 17360 | { PseudoVSUXEI64_V_M1_MF8_MASK, VSUXEI64_V, 0x5, 0x0 }, // 10070 |
| 17361 | { PseudoVSUXEI64_V_M1_MF4, VSUXEI64_V, 0x6, 0x0 }, // 10071 |
| 17362 | { PseudoVSUXEI64_V_M1_MF4_MASK, VSUXEI64_V, 0x6, 0x0 }, // 10072 |
| 17363 | { PseudoVSUXEI64_V_M2_MF4, VSUXEI64_V, 0x6, 0x0 }, // 10073 |
| 17364 | { PseudoVSUXEI64_V_M2_MF4_MASK, VSUXEI64_V, 0x6, 0x0 }, // 10074 |
| 17365 | { PseudoVSUXEI64_V_M1_MF2, VSUXEI64_V, 0x7, 0x0 }, // 10075 |
| 17366 | { PseudoVSUXEI64_V_M1_MF2_MASK, VSUXEI64_V, 0x7, 0x0 }, // 10076 |
| 17367 | { PseudoVSUXEI64_V_M2_MF2, VSUXEI64_V, 0x7, 0x0 }, // 10077 |
| 17368 | { PseudoVSUXEI64_V_M2_MF2_MASK, VSUXEI64_V, 0x7, 0x0 }, // 10078 |
| 17369 | { PseudoVSUXEI64_V_M4_MF2, VSUXEI64_V, 0x7, 0x0 }, // 10079 |
| 17370 | { PseudoVSUXEI64_V_M4_MF2_MASK, VSUXEI64_V, 0x7, 0x0 }, // 10080 |
| 17371 | { PseudoVSUXEI8_V_M1_M1, VSUXEI8_V, 0x0, 0x0 }, // 10081 |
| 17372 | { PseudoVSUXEI8_V_M1_M1_MASK, VSUXEI8_V, 0x0, 0x0 }, // 10082 |
| 17373 | { PseudoVSUXEI8_V_MF2_M1, VSUXEI8_V, 0x0, 0x0 }, // 10083 |
| 17374 | { PseudoVSUXEI8_V_MF2_M1_MASK, VSUXEI8_V, 0x0, 0x0 }, // 10084 |
| 17375 | { PseudoVSUXEI8_V_MF4_M1, VSUXEI8_V, 0x0, 0x0 }, // 10085 |
| 17376 | { PseudoVSUXEI8_V_MF4_M1_MASK, VSUXEI8_V, 0x0, 0x0 }, // 10086 |
| 17377 | { PseudoVSUXEI8_V_MF8_M1, VSUXEI8_V, 0x0, 0x0 }, // 10087 |
| 17378 | { PseudoVSUXEI8_V_MF8_M1_MASK, VSUXEI8_V, 0x0, 0x0 }, // 10088 |
| 17379 | { PseudoVSUXEI8_V_M1_M2, VSUXEI8_V, 0x1, 0x0 }, // 10089 |
| 17380 | { PseudoVSUXEI8_V_M1_M2_MASK, VSUXEI8_V, 0x1, 0x0 }, // 10090 |
| 17381 | { PseudoVSUXEI8_V_M2_M2, VSUXEI8_V, 0x1, 0x0 }, // 10091 |
| 17382 | { PseudoVSUXEI8_V_M2_M2_MASK, VSUXEI8_V, 0x1, 0x0 }, // 10092 |
| 17383 | { PseudoVSUXEI8_V_MF2_M2, VSUXEI8_V, 0x1, 0x0 }, // 10093 |
| 17384 | { PseudoVSUXEI8_V_MF2_M2_MASK, VSUXEI8_V, 0x1, 0x0 }, // 10094 |
| 17385 | { PseudoVSUXEI8_V_MF4_M2, VSUXEI8_V, 0x1, 0x0 }, // 10095 |
| 17386 | { PseudoVSUXEI8_V_MF4_M2_MASK, VSUXEI8_V, 0x1, 0x0 }, // 10096 |
| 17387 | { PseudoVSUXEI8_V_M1_M4, VSUXEI8_V, 0x2, 0x0 }, // 10097 |
| 17388 | { PseudoVSUXEI8_V_M1_M4_MASK, VSUXEI8_V, 0x2, 0x0 }, // 10098 |
| 17389 | { PseudoVSUXEI8_V_M2_M4, VSUXEI8_V, 0x2, 0x0 }, // 10099 |
| 17390 | { PseudoVSUXEI8_V_M2_M4_MASK, VSUXEI8_V, 0x2, 0x0 }, // 10100 |
| 17391 | { PseudoVSUXEI8_V_M4_M4, VSUXEI8_V, 0x2, 0x0 }, // 10101 |
| 17392 | { PseudoVSUXEI8_V_M4_M4_MASK, VSUXEI8_V, 0x2, 0x0 }, // 10102 |
| 17393 | { PseudoVSUXEI8_V_MF2_M4, VSUXEI8_V, 0x2, 0x0 }, // 10103 |
| 17394 | { PseudoVSUXEI8_V_MF2_M4_MASK, VSUXEI8_V, 0x2, 0x0 }, // 10104 |
| 17395 | { PseudoVSUXEI8_V_M1_M8, VSUXEI8_V, 0x3, 0x0 }, // 10105 |
| 17396 | { PseudoVSUXEI8_V_M1_M8_MASK, VSUXEI8_V, 0x3, 0x0 }, // 10106 |
| 17397 | { PseudoVSUXEI8_V_M2_M8, VSUXEI8_V, 0x3, 0x0 }, // 10107 |
| 17398 | { PseudoVSUXEI8_V_M2_M8_MASK, VSUXEI8_V, 0x3, 0x0 }, // 10108 |
| 17399 | { PseudoVSUXEI8_V_M4_M8, VSUXEI8_V, 0x3, 0x0 }, // 10109 |
| 17400 | { PseudoVSUXEI8_V_M4_M8_MASK, VSUXEI8_V, 0x3, 0x0 }, // 10110 |
| 17401 | { PseudoVSUXEI8_V_M8_M8, VSUXEI8_V, 0x3, 0x0 }, // 10111 |
| 17402 | { PseudoVSUXEI8_V_M8_M8_MASK, VSUXEI8_V, 0x3, 0x0 }, // 10112 |
| 17403 | { PseudoVSUXEI8_V_MF8_MF8, VSUXEI8_V, 0x5, 0x0 }, // 10113 |
| 17404 | { PseudoVSUXEI8_V_MF8_MF8_MASK, VSUXEI8_V, 0x5, 0x0 }, // 10114 |
| 17405 | { PseudoVSUXEI8_V_MF4_MF4, VSUXEI8_V, 0x6, 0x0 }, // 10115 |
| 17406 | { PseudoVSUXEI8_V_MF4_MF4_MASK, VSUXEI8_V, 0x6, 0x0 }, // 10116 |
| 17407 | { PseudoVSUXEI8_V_MF8_MF4, VSUXEI8_V, 0x6, 0x0 }, // 10117 |
| 17408 | { PseudoVSUXEI8_V_MF8_MF4_MASK, VSUXEI8_V, 0x6, 0x0 }, // 10118 |
| 17409 | { PseudoVSUXEI8_V_MF2_MF2, VSUXEI8_V, 0x7, 0x0 }, // 10119 |
| 17410 | { PseudoVSUXEI8_V_MF2_MF2_MASK, VSUXEI8_V, 0x7, 0x0 }, // 10120 |
| 17411 | { PseudoVSUXEI8_V_MF4_MF2, VSUXEI8_V, 0x7, 0x0 }, // 10121 |
| 17412 | { PseudoVSUXEI8_V_MF4_MF2_MASK, VSUXEI8_V, 0x7, 0x0 }, // 10122 |
| 17413 | { PseudoVSUXEI8_V_MF8_MF2, VSUXEI8_V, 0x7, 0x0 }, // 10123 |
| 17414 | { PseudoVSUXEI8_V_MF8_MF2_MASK, VSUXEI8_V, 0x7, 0x0 }, // 10124 |
| 17415 | { PseudoVSUXSEG2EI16_V_M1_M1, VSUXSEG2EI16_V, 0x0, 0x0 }, // 10125 |
| 17416 | { PseudoVSUXSEG2EI16_V_M1_M1_MASK, VSUXSEG2EI16_V, 0x0, 0x0 }, // 10126 |
| 17417 | { PseudoVSUXSEG2EI16_V_M2_M1, VSUXSEG2EI16_V, 0x0, 0x0 }, // 10127 |
| 17418 | { PseudoVSUXSEG2EI16_V_M2_M1_MASK, VSUXSEG2EI16_V, 0x0, 0x0 }, // 10128 |
| 17419 | { PseudoVSUXSEG2EI16_V_MF2_M1, VSUXSEG2EI16_V, 0x0, 0x0 }, // 10129 |
| 17420 | { PseudoVSUXSEG2EI16_V_MF2_M1_MASK, VSUXSEG2EI16_V, 0x0, 0x0 }, // 10130 |
| 17421 | { PseudoVSUXSEG2EI16_V_MF4_M1, VSUXSEG2EI16_V, 0x0, 0x0 }, // 10131 |
| 17422 | { PseudoVSUXSEG2EI16_V_MF4_M1_MASK, VSUXSEG2EI16_V, 0x0, 0x0 }, // 10132 |
| 17423 | { PseudoVSUXSEG2EI16_V_M1_M2, VSUXSEG2EI16_V, 0x1, 0x0 }, // 10133 |
| 17424 | { PseudoVSUXSEG2EI16_V_M1_M2_MASK, VSUXSEG2EI16_V, 0x1, 0x0 }, // 10134 |
| 17425 | { PseudoVSUXSEG2EI16_V_M2_M2, VSUXSEG2EI16_V, 0x1, 0x0 }, // 10135 |
| 17426 | { PseudoVSUXSEG2EI16_V_M2_M2_MASK, VSUXSEG2EI16_V, 0x1, 0x0 }, // 10136 |
| 17427 | { PseudoVSUXSEG2EI16_V_M4_M2, VSUXSEG2EI16_V, 0x1, 0x0 }, // 10137 |
| 17428 | { PseudoVSUXSEG2EI16_V_M4_M2_MASK, VSUXSEG2EI16_V, 0x1, 0x0 }, // 10138 |
| 17429 | { PseudoVSUXSEG2EI16_V_MF2_M2, VSUXSEG2EI16_V, 0x1, 0x0 }, // 10139 |
| 17430 | { PseudoVSUXSEG2EI16_V_MF2_M2_MASK, VSUXSEG2EI16_V, 0x1, 0x0 }, // 10140 |
| 17431 | { PseudoVSUXSEG2EI16_V_M1_M4, VSUXSEG2EI16_V, 0x2, 0x0 }, // 10141 |
| 17432 | { PseudoVSUXSEG2EI16_V_M1_M4_MASK, VSUXSEG2EI16_V, 0x2, 0x0 }, // 10142 |
| 17433 | { PseudoVSUXSEG2EI16_V_M2_M4, VSUXSEG2EI16_V, 0x2, 0x0 }, // 10143 |
| 17434 | { PseudoVSUXSEG2EI16_V_M2_M4_MASK, VSUXSEG2EI16_V, 0x2, 0x0 }, // 10144 |
| 17435 | { PseudoVSUXSEG2EI16_V_M4_M4, VSUXSEG2EI16_V, 0x2, 0x0 }, // 10145 |
| 17436 | { PseudoVSUXSEG2EI16_V_M4_M4_MASK, VSUXSEG2EI16_V, 0x2, 0x0 }, // 10146 |
| 17437 | { PseudoVSUXSEG2EI16_V_M8_M4, VSUXSEG2EI16_V, 0x2, 0x0 }, // 10147 |
| 17438 | { PseudoVSUXSEG2EI16_V_M8_M4_MASK, VSUXSEG2EI16_V, 0x2, 0x0 }, // 10148 |
| 17439 | { PseudoVSUXSEG2EI16_V_MF4_MF8, VSUXSEG2EI16_V, 0x5, 0x0 }, // 10149 |
| 17440 | { PseudoVSUXSEG2EI16_V_MF4_MF8_MASK, VSUXSEG2EI16_V, 0x5, 0x0 }, // 10150 |
| 17441 | { PseudoVSUXSEG2EI16_V_MF2_MF4, VSUXSEG2EI16_V, 0x6, 0x0 }, // 10151 |
| 17442 | { PseudoVSUXSEG2EI16_V_MF2_MF4_MASK, VSUXSEG2EI16_V, 0x6, 0x0 }, // 10152 |
| 17443 | { PseudoVSUXSEG2EI16_V_MF4_MF4, VSUXSEG2EI16_V, 0x6, 0x0 }, // 10153 |
| 17444 | { PseudoVSUXSEG2EI16_V_MF4_MF4_MASK, VSUXSEG2EI16_V, 0x6, 0x0 }, // 10154 |
| 17445 | { PseudoVSUXSEG2EI16_V_M1_MF2, VSUXSEG2EI16_V, 0x7, 0x0 }, // 10155 |
| 17446 | { PseudoVSUXSEG2EI16_V_M1_MF2_MASK, VSUXSEG2EI16_V, 0x7, 0x0 }, // 10156 |
| 17447 | { PseudoVSUXSEG2EI16_V_MF2_MF2, VSUXSEG2EI16_V, 0x7, 0x0 }, // 10157 |
| 17448 | { PseudoVSUXSEG2EI16_V_MF2_MF2_MASK, VSUXSEG2EI16_V, 0x7, 0x0 }, // 10158 |
| 17449 | { PseudoVSUXSEG2EI16_V_MF4_MF2, VSUXSEG2EI16_V, 0x7, 0x0 }, // 10159 |
| 17450 | { PseudoVSUXSEG2EI16_V_MF4_MF2_MASK, VSUXSEG2EI16_V, 0x7, 0x0 }, // 10160 |
| 17451 | { PseudoVSUXSEG2EI32_V_M1_M1, VSUXSEG2EI32_V, 0x0, 0x0 }, // 10161 |
| 17452 | { PseudoVSUXSEG2EI32_V_M1_M1_MASK, VSUXSEG2EI32_V, 0x0, 0x0 }, // 10162 |
| 17453 | { PseudoVSUXSEG2EI32_V_M2_M1, VSUXSEG2EI32_V, 0x0, 0x0 }, // 10163 |
| 17454 | { PseudoVSUXSEG2EI32_V_M2_M1_MASK, VSUXSEG2EI32_V, 0x0, 0x0 }, // 10164 |
| 17455 | { PseudoVSUXSEG2EI32_V_M4_M1, VSUXSEG2EI32_V, 0x0, 0x0 }, // 10165 |
| 17456 | { PseudoVSUXSEG2EI32_V_M4_M1_MASK, VSUXSEG2EI32_V, 0x0, 0x0 }, // 10166 |
| 17457 | { PseudoVSUXSEG2EI32_V_MF2_M1, VSUXSEG2EI32_V, 0x0, 0x0 }, // 10167 |
| 17458 | { PseudoVSUXSEG2EI32_V_MF2_M1_MASK, VSUXSEG2EI32_V, 0x0, 0x0 }, // 10168 |
| 17459 | { PseudoVSUXSEG2EI32_V_M1_M2, VSUXSEG2EI32_V, 0x1, 0x0 }, // 10169 |
| 17460 | { PseudoVSUXSEG2EI32_V_M1_M2_MASK, VSUXSEG2EI32_V, 0x1, 0x0 }, // 10170 |
| 17461 | { PseudoVSUXSEG2EI32_V_M2_M2, VSUXSEG2EI32_V, 0x1, 0x0 }, // 10171 |
| 17462 | { PseudoVSUXSEG2EI32_V_M2_M2_MASK, VSUXSEG2EI32_V, 0x1, 0x0 }, // 10172 |
| 17463 | { PseudoVSUXSEG2EI32_V_M4_M2, VSUXSEG2EI32_V, 0x1, 0x0 }, // 10173 |
| 17464 | { PseudoVSUXSEG2EI32_V_M4_M2_MASK, VSUXSEG2EI32_V, 0x1, 0x0 }, // 10174 |
| 17465 | { PseudoVSUXSEG2EI32_V_M8_M2, VSUXSEG2EI32_V, 0x1, 0x0 }, // 10175 |
| 17466 | { PseudoVSUXSEG2EI32_V_M8_M2_MASK, VSUXSEG2EI32_V, 0x1, 0x0 }, // 10176 |
| 17467 | { PseudoVSUXSEG2EI32_V_M2_M4, VSUXSEG2EI32_V, 0x2, 0x0 }, // 10177 |
| 17468 | { PseudoVSUXSEG2EI32_V_M2_M4_MASK, VSUXSEG2EI32_V, 0x2, 0x0 }, // 10178 |
| 17469 | { PseudoVSUXSEG2EI32_V_M4_M4, VSUXSEG2EI32_V, 0x2, 0x0 }, // 10179 |
| 17470 | { PseudoVSUXSEG2EI32_V_M4_M4_MASK, VSUXSEG2EI32_V, 0x2, 0x0 }, // 10180 |
| 17471 | { PseudoVSUXSEG2EI32_V_M8_M4, VSUXSEG2EI32_V, 0x2, 0x0 }, // 10181 |
| 17472 | { PseudoVSUXSEG2EI32_V_M8_M4_MASK, VSUXSEG2EI32_V, 0x2, 0x0 }, // 10182 |
| 17473 | { PseudoVSUXSEG2EI32_V_MF2_MF8, VSUXSEG2EI32_V, 0x5, 0x0 }, // 10183 |
| 17474 | { PseudoVSUXSEG2EI32_V_MF2_MF8_MASK, VSUXSEG2EI32_V, 0x5, 0x0 }, // 10184 |
| 17475 | { PseudoVSUXSEG2EI32_V_M1_MF4, VSUXSEG2EI32_V, 0x6, 0x0 }, // 10185 |
| 17476 | { PseudoVSUXSEG2EI32_V_M1_MF4_MASK, VSUXSEG2EI32_V, 0x6, 0x0 }, // 10186 |
| 17477 | { PseudoVSUXSEG2EI32_V_MF2_MF4, VSUXSEG2EI32_V, 0x6, 0x0 }, // 10187 |
| 17478 | { PseudoVSUXSEG2EI32_V_MF2_MF4_MASK, VSUXSEG2EI32_V, 0x6, 0x0 }, // 10188 |
| 17479 | { PseudoVSUXSEG2EI32_V_M1_MF2, VSUXSEG2EI32_V, 0x7, 0x0 }, // 10189 |
| 17480 | { PseudoVSUXSEG2EI32_V_M1_MF2_MASK, VSUXSEG2EI32_V, 0x7, 0x0 }, // 10190 |
| 17481 | { PseudoVSUXSEG2EI32_V_M2_MF2, VSUXSEG2EI32_V, 0x7, 0x0 }, // 10191 |
| 17482 | { PseudoVSUXSEG2EI32_V_M2_MF2_MASK, VSUXSEG2EI32_V, 0x7, 0x0 }, // 10192 |
| 17483 | { PseudoVSUXSEG2EI32_V_MF2_MF2, VSUXSEG2EI32_V, 0x7, 0x0 }, // 10193 |
| 17484 | { PseudoVSUXSEG2EI32_V_MF2_MF2_MASK, VSUXSEG2EI32_V, 0x7, 0x0 }, // 10194 |
| 17485 | { PseudoVSUXSEG2EI64_V_M1_M1, VSUXSEG2EI64_V, 0x0, 0x0 }, // 10195 |
| 17486 | { PseudoVSUXSEG2EI64_V_M1_M1_MASK, VSUXSEG2EI64_V, 0x0, 0x0 }, // 10196 |
| 17487 | { PseudoVSUXSEG2EI64_V_M2_M1, VSUXSEG2EI64_V, 0x0, 0x0 }, // 10197 |
| 17488 | { PseudoVSUXSEG2EI64_V_M2_M1_MASK, VSUXSEG2EI64_V, 0x0, 0x0 }, // 10198 |
| 17489 | { PseudoVSUXSEG2EI64_V_M4_M1, VSUXSEG2EI64_V, 0x0, 0x0 }, // 10199 |
| 17490 | { PseudoVSUXSEG2EI64_V_M4_M1_MASK, VSUXSEG2EI64_V, 0x0, 0x0 }, // 10200 |
| 17491 | { PseudoVSUXSEG2EI64_V_M8_M1, VSUXSEG2EI64_V, 0x0, 0x0 }, // 10201 |
| 17492 | { PseudoVSUXSEG2EI64_V_M8_M1_MASK, VSUXSEG2EI64_V, 0x0, 0x0 }, // 10202 |
| 17493 | { PseudoVSUXSEG2EI64_V_M2_M2, VSUXSEG2EI64_V, 0x1, 0x0 }, // 10203 |
| 17494 | { PseudoVSUXSEG2EI64_V_M2_M2_MASK, VSUXSEG2EI64_V, 0x1, 0x0 }, // 10204 |
| 17495 | { PseudoVSUXSEG2EI64_V_M4_M2, VSUXSEG2EI64_V, 0x1, 0x0 }, // 10205 |
| 17496 | { PseudoVSUXSEG2EI64_V_M4_M2_MASK, VSUXSEG2EI64_V, 0x1, 0x0 }, // 10206 |
| 17497 | { PseudoVSUXSEG2EI64_V_M8_M2, VSUXSEG2EI64_V, 0x1, 0x0 }, // 10207 |
| 17498 | { PseudoVSUXSEG2EI64_V_M8_M2_MASK, VSUXSEG2EI64_V, 0x1, 0x0 }, // 10208 |
| 17499 | { PseudoVSUXSEG2EI64_V_M4_M4, VSUXSEG2EI64_V, 0x2, 0x0 }, // 10209 |
| 17500 | { PseudoVSUXSEG2EI64_V_M4_M4_MASK, VSUXSEG2EI64_V, 0x2, 0x0 }, // 10210 |
| 17501 | { PseudoVSUXSEG2EI64_V_M8_M4, VSUXSEG2EI64_V, 0x2, 0x0 }, // 10211 |
| 17502 | { PseudoVSUXSEG2EI64_V_M8_M4_MASK, VSUXSEG2EI64_V, 0x2, 0x0 }, // 10212 |
| 17503 | { PseudoVSUXSEG2EI64_V_M1_MF8, VSUXSEG2EI64_V, 0x5, 0x0 }, // 10213 |
| 17504 | { PseudoVSUXSEG2EI64_V_M1_MF8_MASK, VSUXSEG2EI64_V, 0x5, 0x0 }, // 10214 |
| 17505 | { PseudoVSUXSEG2EI64_V_M1_MF4, VSUXSEG2EI64_V, 0x6, 0x0 }, // 10215 |
| 17506 | { PseudoVSUXSEG2EI64_V_M1_MF4_MASK, VSUXSEG2EI64_V, 0x6, 0x0 }, // 10216 |
| 17507 | { PseudoVSUXSEG2EI64_V_M2_MF4, VSUXSEG2EI64_V, 0x6, 0x0 }, // 10217 |
| 17508 | { PseudoVSUXSEG2EI64_V_M2_MF4_MASK, VSUXSEG2EI64_V, 0x6, 0x0 }, // 10218 |
| 17509 | { PseudoVSUXSEG2EI64_V_M1_MF2, VSUXSEG2EI64_V, 0x7, 0x0 }, // 10219 |
| 17510 | { PseudoVSUXSEG2EI64_V_M1_MF2_MASK, VSUXSEG2EI64_V, 0x7, 0x0 }, // 10220 |
| 17511 | { PseudoVSUXSEG2EI64_V_M2_MF2, VSUXSEG2EI64_V, 0x7, 0x0 }, // 10221 |
| 17512 | { PseudoVSUXSEG2EI64_V_M2_MF2_MASK, VSUXSEG2EI64_V, 0x7, 0x0 }, // 10222 |
| 17513 | { PseudoVSUXSEG2EI64_V_M4_MF2, VSUXSEG2EI64_V, 0x7, 0x0 }, // 10223 |
| 17514 | { PseudoVSUXSEG2EI64_V_M4_MF2_MASK, VSUXSEG2EI64_V, 0x7, 0x0 }, // 10224 |
| 17515 | { PseudoVSUXSEG2EI8_V_M1_M1, VSUXSEG2EI8_V, 0x0, 0x0 }, // 10225 |
| 17516 | { PseudoVSUXSEG2EI8_V_M1_M1_MASK, VSUXSEG2EI8_V, 0x0, 0x0 }, // 10226 |
| 17517 | { PseudoVSUXSEG2EI8_V_MF2_M1, VSUXSEG2EI8_V, 0x0, 0x0 }, // 10227 |
| 17518 | { PseudoVSUXSEG2EI8_V_MF2_M1_MASK, VSUXSEG2EI8_V, 0x0, 0x0 }, // 10228 |
| 17519 | { PseudoVSUXSEG2EI8_V_MF4_M1, VSUXSEG2EI8_V, 0x0, 0x0 }, // 10229 |
| 17520 | { PseudoVSUXSEG2EI8_V_MF4_M1_MASK, VSUXSEG2EI8_V, 0x0, 0x0 }, // 10230 |
| 17521 | { PseudoVSUXSEG2EI8_V_MF8_M1, VSUXSEG2EI8_V, 0x0, 0x0 }, // 10231 |
| 17522 | { PseudoVSUXSEG2EI8_V_MF8_M1_MASK, VSUXSEG2EI8_V, 0x0, 0x0 }, // 10232 |
| 17523 | { PseudoVSUXSEG2EI8_V_M1_M2, VSUXSEG2EI8_V, 0x1, 0x0 }, // 10233 |
| 17524 | { PseudoVSUXSEG2EI8_V_M1_M2_MASK, VSUXSEG2EI8_V, 0x1, 0x0 }, // 10234 |
| 17525 | { PseudoVSUXSEG2EI8_V_M2_M2, VSUXSEG2EI8_V, 0x1, 0x0 }, // 10235 |
| 17526 | { PseudoVSUXSEG2EI8_V_M2_M2_MASK, VSUXSEG2EI8_V, 0x1, 0x0 }, // 10236 |
| 17527 | { PseudoVSUXSEG2EI8_V_MF2_M2, VSUXSEG2EI8_V, 0x1, 0x0 }, // 10237 |
| 17528 | { PseudoVSUXSEG2EI8_V_MF2_M2_MASK, VSUXSEG2EI8_V, 0x1, 0x0 }, // 10238 |
| 17529 | { PseudoVSUXSEG2EI8_V_MF4_M2, VSUXSEG2EI8_V, 0x1, 0x0 }, // 10239 |
| 17530 | { PseudoVSUXSEG2EI8_V_MF4_M2_MASK, VSUXSEG2EI8_V, 0x1, 0x0 }, // 10240 |
| 17531 | { PseudoVSUXSEG2EI8_V_M1_M4, VSUXSEG2EI8_V, 0x2, 0x0 }, // 10241 |
| 17532 | { PseudoVSUXSEG2EI8_V_M1_M4_MASK, VSUXSEG2EI8_V, 0x2, 0x0 }, // 10242 |
| 17533 | { PseudoVSUXSEG2EI8_V_M2_M4, VSUXSEG2EI8_V, 0x2, 0x0 }, // 10243 |
| 17534 | { PseudoVSUXSEG2EI8_V_M2_M4_MASK, VSUXSEG2EI8_V, 0x2, 0x0 }, // 10244 |
| 17535 | { PseudoVSUXSEG2EI8_V_M4_M4, VSUXSEG2EI8_V, 0x2, 0x0 }, // 10245 |
| 17536 | { PseudoVSUXSEG2EI8_V_M4_M4_MASK, VSUXSEG2EI8_V, 0x2, 0x0 }, // 10246 |
| 17537 | { PseudoVSUXSEG2EI8_V_MF2_M4, VSUXSEG2EI8_V, 0x2, 0x0 }, // 10247 |
| 17538 | { PseudoVSUXSEG2EI8_V_MF2_M4_MASK, VSUXSEG2EI8_V, 0x2, 0x0 }, // 10248 |
| 17539 | { PseudoVSUXSEG2EI8_V_MF8_MF8, VSUXSEG2EI8_V, 0x5, 0x0 }, // 10249 |
| 17540 | { PseudoVSUXSEG2EI8_V_MF8_MF8_MASK, VSUXSEG2EI8_V, 0x5, 0x0 }, // 10250 |
| 17541 | { PseudoVSUXSEG2EI8_V_MF4_MF4, VSUXSEG2EI8_V, 0x6, 0x0 }, // 10251 |
| 17542 | { PseudoVSUXSEG2EI8_V_MF4_MF4_MASK, VSUXSEG2EI8_V, 0x6, 0x0 }, // 10252 |
| 17543 | { PseudoVSUXSEG2EI8_V_MF8_MF4, VSUXSEG2EI8_V, 0x6, 0x0 }, // 10253 |
| 17544 | { PseudoVSUXSEG2EI8_V_MF8_MF4_MASK, VSUXSEG2EI8_V, 0x6, 0x0 }, // 10254 |
| 17545 | { PseudoVSUXSEG2EI8_V_MF2_MF2, VSUXSEG2EI8_V, 0x7, 0x0 }, // 10255 |
| 17546 | { PseudoVSUXSEG2EI8_V_MF2_MF2_MASK, VSUXSEG2EI8_V, 0x7, 0x0 }, // 10256 |
| 17547 | { PseudoVSUXSEG2EI8_V_MF4_MF2, VSUXSEG2EI8_V, 0x7, 0x0 }, // 10257 |
| 17548 | { PseudoVSUXSEG2EI8_V_MF4_MF2_MASK, VSUXSEG2EI8_V, 0x7, 0x0 }, // 10258 |
| 17549 | { PseudoVSUXSEG2EI8_V_MF8_MF2, VSUXSEG2EI8_V, 0x7, 0x0 }, // 10259 |
| 17550 | { PseudoVSUXSEG2EI8_V_MF8_MF2_MASK, VSUXSEG2EI8_V, 0x7, 0x0 }, // 10260 |
| 17551 | { PseudoVSUXSEG3EI16_V_M1_M1, VSUXSEG3EI16_V, 0x0, 0x0 }, // 10261 |
| 17552 | { PseudoVSUXSEG3EI16_V_M1_M1_MASK, VSUXSEG3EI16_V, 0x0, 0x0 }, // 10262 |
| 17553 | { PseudoVSUXSEG3EI16_V_M2_M1, VSUXSEG3EI16_V, 0x0, 0x0 }, // 10263 |
| 17554 | { PseudoVSUXSEG3EI16_V_M2_M1_MASK, VSUXSEG3EI16_V, 0x0, 0x0 }, // 10264 |
| 17555 | { PseudoVSUXSEG3EI16_V_MF2_M1, VSUXSEG3EI16_V, 0x0, 0x0 }, // 10265 |
| 17556 | { PseudoVSUXSEG3EI16_V_MF2_M1_MASK, VSUXSEG3EI16_V, 0x0, 0x0 }, // 10266 |
| 17557 | { PseudoVSUXSEG3EI16_V_MF4_M1, VSUXSEG3EI16_V, 0x0, 0x0 }, // 10267 |
| 17558 | { PseudoVSUXSEG3EI16_V_MF4_M1_MASK, VSUXSEG3EI16_V, 0x0, 0x0 }, // 10268 |
| 17559 | { PseudoVSUXSEG3EI16_V_M1_M2, VSUXSEG3EI16_V, 0x1, 0x0 }, // 10269 |
| 17560 | { PseudoVSUXSEG3EI16_V_M1_M2_MASK, VSUXSEG3EI16_V, 0x1, 0x0 }, // 10270 |
| 17561 | { PseudoVSUXSEG3EI16_V_M2_M2, VSUXSEG3EI16_V, 0x1, 0x0 }, // 10271 |
| 17562 | { PseudoVSUXSEG3EI16_V_M2_M2_MASK, VSUXSEG3EI16_V, 0x1, 0x0 }, // 10272 |
| 17563 | { PseudoVSUXSEG3EI16_V_M4_M2, VSUXSEG3EI16_V, 0x1, 0x0 }, // 10273 |
| 17564 | { PseudoVSUXSEG3EI16_V_M4_M2_MASK, VSUXSEG3EI16_V, 0x1, 0x0 }, // 10274 |
| 17565 | { PseudoVSUXSEG3EI16_V_MF2_M2, VSUXSEG3EI16_V, 0x1, 0x0 }, // 10275 |
| 17566 | { PseudoVSUXSEG3EI16_V_MF2_M2_MASK, VSUXSEG3EI16_V, 0x1, 0x0 }, // 10276 |
| 17567 | { PseudoVSUXSEG3EI16_V_MF4_MF8, VSUXSEG3EI16_V, 0x5, 0x0 }, // 10277 |
| 17568 | { PseudoVSUXSEG3EI16_V_MF4_MF8_MASK, VSUXSEG3EI16_V, 0x5, 0x0 }, // 10278 |
| 17569 | { PseudoVSUXSEG3EI16_V_MF2_MF4, VSUXSEG3EI16_V, 0x6, 0x0 }, // 10279 |
| 17570 | { PseudoVSUXSEG3EI16_V_MF2_MF4_MASK, VSUXSEG3EI16_V, 0x6, 0x0 }, // 10280 |
| 17571 | { PseudoVSUXSEG3EI16_V_MF4_MF4, VSUXSEG3EI16_V, 0x6, 0x0 }, // 10281 |
| 17572 | { PseudoVSUXSEG3EI16_V_MF4_MF4_MASK, VSUXSEG3EI16_V, 0x6, 0x0 }, // 10282 |
| 17573 | { PseudoVSUXSEG3EI16_V_M1_MF2, VSUXSEG3EI16_V, 0x7, 0x0 }, // 10283 |
| 17574 | { PseudoVSUXSEG3EI16_V_M1_MF2_MASK, VSUXSEG3EI16_V, 0x7, 0x0 }, // 10284 |
| 17575 | { PseudoVSUXSEG3EI16_V_MF2_MF2, VSUXSEG3EI16_V, 0x7, 0x0 }, // 10285 |
| 17576 | { PseudoVSUXSEG3EI16_V_MF2_MF2_MASK, VSUXSEG3EI16_V, 0x7, 0x0 }, // 10286 |
| 17577 | { PseudoVSUXSEG3EI16_V_MF4_MF2, VSUXSEG3EI16_V, 0x7, 0x0 }, // 10287 |
| 17578 | { PseudoVSUXSEG3EI16_V_MF4_MF2_MASK, VSUXSEG3EI16_V, 0x7, 0x0 }, // 10288 |
| 17579 | { PseudoVSUXSEG3EI32_V_M1_M1, VSUXSEG3EI32_V, 0x0, 0x0 }, // 10289 |
| 17580 | { PseudoVSUXSEG3EI32_V_M1_M1_MASK, VSUXSEG3EI32_V, 0x0, 0x0 }, // 10290 |
| 17581 | { PseudoVSUXSEG3EI32_V_M2_M1, VSUXSEG3EI32_V, 0x0, 0x0 }, // 10291 |
| 17582 | { PseudoVSUXSEG3EI32_V_M2_M1_MASK, VSUXSEG3EI32_V, 0x0, 0x0 }, // 10292 |
| 17583 | { PseudoVSUXSEG3EI32_V_M4_M1, VSUXSEG3EI32_V, 0x0, 0x0 }, // 10293 |
| 17584 | { PseudoVSUXSEG3EI32_V_M4_M1_MASK, VSUXSEG3EI32_V, 0x0, 0x0 }, // 10294 |
| 17585 | { PseudoVSUXSEG3EI32_V_MF2_M1, VSUXSEG3EI32_V, 0x0, 0x0 }, // 10295 |
| 17586 | { PseudoVSUXSEG3EI32_V_MF2_M1_MASK, VSUXSEG3EI32_V, 0x0, 0x0 }, // 10296 |
| 17587 | { PseudoVSUXSEG3EI32_V_M1_M2, VSUXSEG3EI32_V, 0x1, 0x0 }, // 10297 |
| 17588 | { PseudoVSUXSEG3EI32_V_M1_M2_MASK, VSUXSEG3EI32_V, 0x1, 0x0 }, // 10298 |
| 17589 | { PseudoVSUXSEG3EI32_V_M2_M2, VSUXSEG3EI32_V, 0x1, 0x0 }, // 10299 |
| 17590 | { PseudoVSUXSEG3EI32_V_M2_M2_MASK, VSUXSEG3EI32_V, 0x1, 0x0 }, // 10300 |
| 17591 | { PseudoVSUXSEG3EI32_V_M4_M2, VSUXSEG3EI32_V, 0x1, 0x0 }, // 10301 |
| 17592 | { PseudoVSUXSEG3EI32_V_M4_M2_MASK, VSUXSEG3EI32_V, 0x1, 0x0 }, // 10302 |
| 17593 | { PseudoVSUXSEG3EI32_V_M8_M2, VSUXSEG3EI32_V, 0x1, 0x0 }, // 10303 |
| 17594 | { PseudoVSUXSEG3EI32_V_M8_M2_MASK, VSUXSEG3EI32_V, 0x1, 0x0 }, // 10304 |
| 17595 | { PseudoVSUXSEG3EI32_V_MF2_MF8, VSUXSEG3EI32_V, 0x5, 0x0 }, // 10305 |
| 17596 | { PseudoVSUXSEG3EI32_V_MF2_MF8_MASK, VSUXSEG3EI32_V, 0x5, 0x0 }, // 10306 |
| 17597 | { PseudoVSUXSEG3EI32_V_M1_MF4, VSUXSEG3EI32_V, 0x6, 0x0 }, // 10307 |
| 17598 | { PseudoVSUXSEG3EI32_V_M1_MF4_MASK, VSUXSEG3EI32_V, 0x6, 0x0 }, // 10308 |
| 17599 | { PseudoVSUXSEG3EI32_V_MF2_MF4, VSUXSEG3EI32_V, 0x6, 0x0 }, // 10309 |
| 17600 | { PseudoVSUXSEG3EI32_V_MF2_MF4_MASK, VSUXSEG3EI32_V, 0x6, 0x0 }, // 10310 |
| 17601 | { PseudoVSUXSEG3EI32_V_M1_MF2, VSUXSEG3EI32_V, 0x7, 0x0 }, // 10311 |
| 17602 | { PseudoVSUXSEG3EI32_V_M1_MF2_MASK, VSUXSEG3EI32_V, 0x7, 0x0 }, // 10312 |
| 17603 | { PseudoVSUXSEG3EI32_V_M2_MF2, VSUXSEG3EI32_V, 0x7, 0x0 }, // 10313 |
| 17604 | { PseudoVSUXSEG3EI32_V_M2_MF2_MASK, VSUXSEG3EI32_V, 0x7, 0x0 }, // 10314 |
| 17605 | { PseudoVSUXSEG3EI32_V_MF2_MF2, VSUXSEG3EI32_V, 0x7, 0x0 }, // 10315 |
| 17606 | { PseudoVSUXSEG3EI32_V_MF2_MF2_MASK, VSUXSEG3EI32_V, 0x7, 0x0 }, // 10316 |
| 17607 | { PseudoVSUXSEG3EI64_V_M1_M1, VSUXSEG3EI64_V, 0x0, 0x0 }, // 10317 |
| 17608 | { PseudoVSUXSEG3EI64_V_M1_M1_MASK, VSUXSEG3EI64_V, 0x0, 0x0 }, // 10318 |
| 17609 | { PseudoVSUXSEG3EI64_V_M2_M1, VSUXSEG3EI64_V, 0x0, 0x0 }, // 10319 |
| 17610 | { PseudoVSUXSEG3EI64_V_M2_M1_MASK, VSUXSEG3EI64_V, 0x0, 0x0 }, // 10320 |
| 17611 | { PseudoVSUXSEG3EI64_V_M4_M1, VSUXSEG3EI64_V, 0x0, 0x0 }, // 10321 |
| 17612 | { PseudoVSUXSEG3EI64_V_M4_M1_MASK, VSUXSEG3EI64_V, 0x0, 0x0 }, // 10322 |
| 17613 | { PseudoVSUXSEG3EI64_V_M8_M1, VSUXSEG3EI64_V, 0x0, 0x0 }, // 10323 |
| 17614 | { PseudoVSUXSEG3EI64_V_M8_M1_MASK, VSUXSEG3EI64_V, 0x0, 0x0 }, // 10324 |
| 17615 | { PseudoVSUXSEG3EI64_V_M2_M2, VSUXSEG3EI64_V, 0x1, 0x0 }, // 10325 |
| 17616 | { PseudoVSUXSEG3EI64_V_M2_M2_MASK, VSUXSEG3EI64_V, 0x1, 0x0 }, // 10326 |
| 17617 | { PseudoVSUXSEG3EI64_V_M4_M2, VSUXSEG3EI64_V, 0x1, 0x0 }, // 10327 |
| 17618 | { PseudoVSUXSEG3EI64_V_M4_M2_MASK, VSUXSEG3EI64_V, 0x1, 0x0 }, // 10328 |
| 17619 | { PseudoVSUXSEG3EI64_V_M8_M2, VSUXSEG3EI64_V, 0x1, 0x0 }, // 10329 |
| 17620 | { PseudoVSUXSEG3EI64_V_M8_M2_MASK, VSUXSEG3EI64_V, 0x1, 0x0 }, // 10330 |
| 17621 | { PseudoVSUXSEG3EI64_V_M1_MF8, VSUXSEG3EI64_V, 0x5, 0x0 }, // 10331 |
| 17622 | { PseudoVSUXSEG3EI64_V_M1_MF8_MASK, VSUXSEG3EI64_V, 0x5, 0x0 }, // 10332 |
| 17623 | { PseudoVSUXSEG3EI64_V_M1_MF4, VSUXSEG3EI64_V, 0x6, 0x0 }, // 10333 |
| 17624 | { PseudoVSUXSEG3EI64_V_M1_MF4_MASK, VSUXSEG3EI64_V, 0x6, 0x0 }, // 10334 |
| 17625 | { PseudoVSUXSEG3EI64_V_M2_MF4, VSUXSEG3EI64_V, 0x6, 0x0 }, // 10335 |
| 17626 | { PseudoVSUXSEG3EI64_V_M2_MF4_MASK, VSUXSEG3EI64_V, 0x6, 0x0 }, // 10336 |
| 17627 | { PseudoVSUXSEG3EI64_V_M1_MF2, VSUXSEG3EI64_V, 0x7, 0x0 }, // 10337 |
| 17628 | { PseudoVSUXSEG3EI64_V_M1_MF2_MASK, VSUXSEG3EI64_V, 0x7, 0x0 }, // 10338 |
| 17629 | { PseudoVSUXSEG3EI64_V_M2_MF2, VSUXSEG3EI64_V, 0x7, 0x0 }, // 10339 |
| 17630 | { PseudoVSUXSEG3EI64_V_M2_MF2_MASK, VSUXSEG3EI64_V, 0x7, 0x0 }, // 10340 |
| 17631 | { PseudoVSUXSEG3EI64_V_M4_MF2, VSUXSEG3EI64_V, 0x7, 0x0 }, // 10341 |
| 17632 | { PseudoVSUXSEG3EI64_V_M4_MF2_MASK, VSUXSEG3EI64_V, 0x7, 0x0 }, // 10342 |
| 17633 | { PseudoVSUXSEG3EI8_V_M1_M1, VSUXSEG3EI8_V, 0x0, 0x0 }, // 10343 |
| 17634 | { PseudoVSUXSEG3EI8_V_M1_M1_MASK, VSUXSEG3EI8_V, 0x0, 0x0 }, // 10344 |
| 17635 | { PseudoVSUXSEG3EI8_V_MF2_M1, VSUXSEG3EI8_V, 0x0, 0x0 }, // 10345 |
| 17636 | { PseudoVSUXSEG3EI8_V_MF2_M1_MASK, VSUXSEG3EI8_V, 0x0, 0x0 }, // 10346 |
| 17637 | { PseudoVSUXSEG3EI8_V_MF4_M1, VSUXSEG3EI8_V, 0x0, 0x0 }, // 10347 |
| 17638 | { PseudoVSUXSEG3EI8_V_MF4_M1_MASK, VSUXSEG3EI8_V, 0x0, 0x0 }, // 10348 |
| 17639 | { PseudoVSUXSEG3EI8_V_MF8_M1, VSUXSEG3EI8_V, 0x0, 0x0 }, // 10349 |
| 17640 | { PseudoVSUXSEG3EI8_V_MF8_M1_MASK, VSUXSEG3EI8_V, 0x0, 0x0 }, // 10350 |
| 17641 | { PseudoVSUXSEG3EI8_V_M1_M2, VSUXSEG3EI8_V, 0x1, 0x0 }, // 10351 |
| 17642 | { PseudoVSUXSEG3EI8_V_M1_M2_MASK, VSUXSEG3EI8_V, 0x1, 0x0 }, // 10352 |
| 17643 | { PseudoVSUXSEG3EI8_V_M2_M2, VSUXSEG3EI8_V, 0x1, 0x0 }, // 10353 |
| 17644 | { PseudoVSUXSEG3EI8_V_M2_M2_MASK, VSUXSEG3EI8_V, 0x1, 0x0 }, // 10354 |
| 17645 | { PseudoVSUXSEG3EI8_V_MF2_M2, VSUXSEG3EI8_V, 0x1, 0x0 }, // 10355 |
| 17646 | { PseudoVSUXSEG3EI8_V_MF2_M2_MASK, VSUXSEG3EI8_V, 0x1, 0x0 }, // 10356 |
| 17647 | { PseudoVSUXSEG3EI8_V_MF4_M2, VSUXSEG3EI8_V, 0x1, 0x0 }, // 10357 |
| 17648 | { PseudoVSUXSEG3EI8_V_MF4_M2_MASK, VSUXSEG3EI8_V, 0x1, 0x0 }, // 10358 |
| 17649 | { PseudoVSUXSEG3EI8_V_MF8_MF8, VSUXSEG3EI8_V, 0x5, 0x0 }, // 10359 |
| 17650 | { PseudoVSUXSEG3EI8_V_MF8_MF8_MASK, VSUXSEG3EI8_V, 0x5, 0x0 }, // 10360 |
| 17651 | { PseudoVSUXSEG3EI8_V_MF4_MF4, VSUXSEG3EI8_V, 0x6, 0x0 }, // 10361 |
| 17652 | { PseudoVSUXSEG3EI8_V_MF4_MF4_MASK, VSUXSEG3EI8_V, 0x6, 0x0 }, // 10362 |
| 17653 | { PseudoVSUXSEG3EI8_V_MF8_MF4, VSUXSEG3EI8_V, 0x6, 0x0 }, // 10363 |
| 17654 | { PseudoVSUXSEG3EI8_V_MF8_MF4_MASK, VSUXSEG3EI8_V, 0x6, 0x0 }, // 10364 |
| 17655 | { PseudoVSUXSEG3EI8_V_MF2_MF2, VSUXSEG3EI8_V, 0x7, 0x0 }, // 10365 |
| 17656 | { PseudoVSUXSEG3EI8_V_MF2_MF2_MASK, VSUXSEG3EI8_V, 0x7, 0x0 }, // 10366 |
| 17657 | { PseudoVSUXSEG3EI8_V_MF4_MF2, VSUXSEG3EI8_V, 0x7, 0x0 }, // 10367 |
| 17658 | { PseudoVSUXSEG3EI8_V_MF4_MF2_MASK, VSUXSEG3EI8_V, 0x7, 0x0 }, // 10368 |
| 17659 | { PseudoVSUXSEG3EI8_V_MF8_MF2, VSUXSEG3EI8_V, 0x7, 0x0 }, // 10369 |
| 17660 | { PseudoVSUXSEG3EI8_V_MF8_MF2_MASK, VSUXSEG3EI8_V, 0x7, 0x0 }, // 10370 |
| 17661 | { PseudoVSUXSEG4EI16_V_M1_M1, VSUXSEG4EI16_V, 0x0, 0x0 }, // 10371 |
| 17662 | { PseudoVSUXSEG4EI16_V_M1_M1_MASK, VSUXSEG4EI16_V, 0x0, 0x0 }, // 10372 |
| 17663 | { PseudoVSUXSEG4EI16_V_M2_M1, VSUXSEG4EI16_V, 0x0, 0x0 }, // 10373 |
| 17664 | { PseudoVSUXSEG4EI16_V_M2_M1_MASK, VSUXSEG4EI16_V, 0x0, 0x0 }, // 10374 |
| 17665 | { PseudoVSUXSEG4EI16_V_MF2_M1, VSUXSEG4EI16_V, 0x0, 0x0 }, // 10375 |
| 17666 | { PseudoVSUXSEG4EI16_V_MF2_M1_MASK, VSUXSEG4EI16_V, 0x0, 0x0 }, // 10376 |
| 17667 | { PseudoVSUXSEG4EI16_V_MF4_M1, VSUXSEG4EI16_V, 0x0, 0x0 }, // 10377 |
| 17668 | { PseudoVSUXSEG4EI16_V_MF4_M1_MASK, VSUXSEG4EI16_V, 0x0, 0x0 }, // 10378 |
| 17669 | { PseudoVSUXSEG4EI16_V_M1_M2, VSUXSEG4EI16_V, 0x1, 0x0 }, // 10379 |
| 17670 | { PseudoVSUXSEG4EI16_V_M1_M2_MASK, VSUXSEG4EI16_V, 0x1, 0x0 }, // 10380 |
| 17671 | { PseudoVSUXSEG4EI16_V_M2_M2, VSUXSEG4EI16_V, 0x1, 0x0 }, // 10381 |
| 17672 | { PseudoVSUXSEG4EI16_V_M2_M2_MASK, VSUXSEG4EI16_V, 0x1, 0x0 }, // 10382 |
| 17673 | { PseudoVSUXSEG4EI16_V_M4_M2, VSUXSEG4EI16_V, 0x1, 0x0 }, // 10383 |
| 17674 | { PseudoVSUXSEG4EI16_V_M4_M2_MASK, VSUXSEG4EI16_V, 0x1, 0x0 }, // 10384 |
| 17675 | { PseudoVSUXSEG4EI16_V_MF2_M2, VSUXSEG4EI16_V, 0x1, 0x0 }, // 10385 |
| 17676 | { PseudoVSUXSEG4EI16_V_MF2_M2_MASK, VSUXSEG4EI16_V, 0x1, 0x0 }, // 10386 |
| 17677 | { PseudoVSUXSEG4EI16_V_MF4_MF8, VSUXSEG4EI16_V, 0x5, 0x0 }, // 10387 |
| 17678 | { PseudoVSUXSEG4EI16_V_MF4_MF8_MASK, VSUXSEG4EI16_V, 0x5, 0x0 }, // 10388 |
| 17679 | { PseudoVSUXSEG4EI16_V_MF2_MF4, VSUXSEG4EI16_V, 0x6, 0x0 }, // 10389 |
| 17680 | { PseudoVSUXSEG4EI16_V_MF2_MF4_MASK, VSUXSEG4EI16_V, 0x6, 0x0 }, // 10390 |
| 17681 | { PseudoVSUXSEG4EI16_V_MF4_MF4, VSUXSEG4EI16_V, 0x6, 0x0 }, // 10391 |
| 17682 | { PseudoVSUXSEG4EI16_V_MF4_MF4_MASK, VSUXSEG4EI16_V, 0x6, 0x0 }, // 10392 |
| 17683 | { PseudoVSUXSEG4EI16_V_M1_MF2, VSUXSEG4EI16_V, 0x7, 0x0 }, // 10393 |
| 17684 | { PseudoVSUXSEG4EI16_V_M1_MF2_MASK, VSUXSEG4EI16_V, 0x7, 0x0 }, // 10394 |
| 17685 | { PseudoVSUXSEG4EI16_V_MF2_MF2, VSUXSEG4EI16_V, 0x7, 0x0 }, // 10395 |
| 17686 | { PseudoVSUXSEG4EI16_V_MF2_MF2_MASK, VSUXSEG4EI16_V, 0x7, 0x0 }, // 10396 |
| 17687 | { PseudoVSUXSEG4EI16_V_MF4_MF2, VSUXSEG4EI16_V, 0x7, 0x0 }, // 10397 |
| 17688 | { PseudoVSUXSEG4EI16_V_MF4_MF2_MASK, VSUXSEG4EI16_V, 0x7, 0x0 }, // 10398 |
| 17689 | { PseudoVSUXSEG4EI32_V_M1_M1, VSUXSEG4EI32_V, 0x0, 0x0 }, // 10399 |
| 17690 | { PseudoVSUXSEG4EI32_V_M1_M1_MASK, VSUXSEG4EI32_V, 0x0, 0x0 }, // 10400 |
| 17691 | { PseudoVSUXSEG4EI32_V_M2_M1, VSUXSEG4EI32_V, 0x0, 0x0 }, // 10401 |
| 17692 | { PseudoVSUXSEG4EI32_V_M2_M1_MASK, VSUXSEG4EI32_V, 0x0, 0x0 }, // 10402 |
| 17693 | { PseudoVSUXSEG4EI32_V_M4_M1, VSUXSEG4EI32_V, 0x0, 0x0 }, // 10403 |
| 17694 | { PseudoVSUXSEG4EI32_V_M4_M1_MASK, VSUXSEG4EI32_V, 0x0, 0x0 }, // 10404 |
| 17695 | { PseudoVSUXSEG4EI32_V_MF2_M1, VSUXSEG4EI32_V, 0x0, 0x0 }, // 10405 |
| 17696 | { PseudoVSUXSEG4EI32_V_MF2_M1_MASK, VSUXSEG4EI32_V, 0x0, 0x0 }, // 10406 |
| 17697 | { PseudoVSUXSEG4EI32_V_M1_M2, VSUXSEG4EI32_V, 0x1, 0x0 }, // 10407 |
| 17698 | { PseudoVSUXSEG4EI32_V_M1_M2_MASK, VSUXSEG4EI32_V, 0x1, 0x0 }, // 10408 |
| 17699 | { PseudoVSUXSEG4EI32_V_M2_M2, VSUXSEG4EI32_V, 0x1, 0x0 }, // 10409 |
| 17700 | { PseudoVSUXSEG4EI32_V_M2_M2_MASK, VSUXSEG4EI32_V, 0x1, 0x0 }, // 10410 |
| 17701 | { PseudoVSUXSEG4EI32_V_M4_M2, VSUXSEG4EI32_V, 0x1, 0x0 }, // 10411 |
| 17702 | { PseudoVSUXSEG4EI32_V_M4_M2_MASK, VSUXSEG4EI32_V, 0x1, 0x0 }, // 10412 |
| 17703 | { PseudoVSUXSEG4EI32_V_M8_M2, VSUXSEG4EI32_V, 0x1, 0x0 }, // 10413 |
| 17704 | { PseudoVSUXSEG4EI32_V_M8_M2_MASK, VSUXSEG4EI32_V, 0x1, 0x0 }, // 10414 |
| 17705 | { PseudoVSUXSEG4EI32_V_MF2_MF8, VSUXSEG4EI32_V, 0x5, 0x0 }, // 10415 |
| 17706 | { PseudoVSUXSEG4EI32_V_MF2_MF8_MASK, VSUXSEG4EI32_V, 0x5, 0x0 }, // 10416 |
| 17707 | { PseudoVSUXSEG4EI32_V_M1_MF4, VSUXSEG4EI32_V, 0x6, 0x0 }, // 10417 |
| 17708 | { PseudoVSUXSEG4EI32_V_M1_MF4_MASK, VSUXSEG4EI32_V, 0x6, 0x0 }, // 10418 |
| 17709 | { PseudoVSUXSEG4EI32_V_MF2_MF4, VSUXSEG4EI32_V, 0x6, 0x0 }, // 10419 |
| 17710 | { PseudoVSUXSEG4EI32_V_MF2_MF4_MASK, VSUXSEG4EI32_V, 0x6, 0x0 }, // 10420 |
| 17711 | { PseudoVSUXSEG4EI32_V_M1_MF2, VSUXSEG4EI32_V, 0x7, 0x0 }, // 10421 |
| 17712 | { PseudoVSUXSEG4EI32_V_M1_MF2_MASK, VSUXSEG4EI32_V, 0x7, 0x0 }, // 10422 |
| 17713 | { PseudoVSUXSEG4EI32_V_M2_MF2, VSUXSEG4EI32_V, 0x7, 0x0 }, // 10423 |
| 17714 | { PseudoVSUXSEG4EI32_V_M2_MF2_MASK, VSUXSEG4EI32_V, 0x7, 0x0 }, // 10424 |
| 17715 | { PseudoVSUXSEG4EI32_V_MF2_MF2, VSUXSEG4EI32_V, 0x7, 0x0 }, // 10425 |
| 17716 | { PseudoVSUXSEG4EI32_V_MF2_MF2_MASK, VSUXSEG4EI32_V, 0x7, 0x0 }, // 10426 |
| 17717 | { PseudoVSUXSEG4EI64_V_M1_M1, VSUXSEG4EI64_V, 0x0, 0x0 }, // 10427 |
| 17718 | { PseudoVSUXSEG4EI64_V_M1_M1_MASK, VSUXSEG4EI64_V, 0x0, 0x0 }, // 10428 |
| 17719 | { PseudoVSUXSEG4EI64_V_M2_M1, VSUXSEG4EI64_V, 0x0, 0x0 }, // 10429 |
| 17720 | { PseudoVSUXSEG4EI64_V_M2_M1_MASK, VSUXSEG4EI64_V, 0x0, 0x0 }, // 10430 |
| 17721 | { PseudoVSUXSEG4EI64_V_M4_M1, VSUXSEG4EI64_V, 0x0, 0x0 }, // 10431 |
| 17722 | { PseudoVSUXSEG4EI64_V_M4_M1_MASK, VSUXSEG4EI64_V, 0x0, 0x0 }, // 10432 |
| 17723 | { PseudoVSUXSEG4EI64_V_M8_M1, VSUXSEG4EI64_V, 0x0, 0x0 }, // 10433 |
| 17724 | { PseudoVSUXSEG4EI64_V_M8_M1_MASK, VSUXSEG4EI64_V, 0x0, 0x0 }, // 10434 |
| 17725 | { PseudoVSUXSEG4EI64_V_M2_M2, VSUXSEG4EI64_V, 0x1, 0x0 }, // 10435 |
| 17726 | { PseudoVSUXSEG4EI64_V_M2_M2_MASK, VSUXSEG4EI64_V, 0x1, 0x0 }, // 10436 |
| 17727 | { PseudoVSUXSEG4EI64_V_M4_M2, VSUXSEG4EI64_V, 0x1, 0x0 }, // 10437 |
| 17728 | { PseudoVSUXSEG4EI64_V_M4_M2_MASK, VSUXSEG4EI64_V, 0x1, 0x0 }, // 10438 |
| 17729 | { PseudoVSUXSEG4EI64_V_M8_M2, VSUXSEG4EI64_V, 0x1, 0x0 }, // 10439 |
| 17730 | { PseudoVSUXSEG4EI64_V_M8_M2_MASK, VSUXSEG4EI64_V, 0x1, 0x0 }, // 10440 |
| 17731 | { PseudoVSUXSEG4EI64_V_M1_MF8, VSUXSEG4EI64_V, 0x5, 0x0 }, // 10441 |
| 17732 | { PseudoVSUXSEG4EI64_V_M1_MF8_MASK, VSUXSEG4EI64_V, 0x5, 0x0 }, // 10442 |
| 17733 | { PseudoVSUXSEG4EI64_V_M1_MF4, VSUXSEG4EI64_V, 0x6, 0x0 }, // 10443 |
| 17734 | { PseudoVSUXSEG4EI64_V_M1_MF4_MASK, VSUXSEG4EI64_V, 0x6, 0x0 }, // 10444 |
| 17735 | { PseudoVSUXSEG4EI64_V_M2_MF4, VSUXSEG4EI64_V, 0x6, 0x0 }, // 10445 |
| 17736 | { PseudoVSUXSEG4EI64_V_M2_MF4_MASK, VSUXSEG4EI64_V, 0x6, 0x0 }, // 10446 |
| 17737 | { PseudoVSUXSEG4EI64_V_M1_MF2, VSUXSEG4EI64_V, 0x7, 0x0 }, // 10447 |
| 17738 | { PseudoVSUXSEG4EI64_V_M1_MF2_MASK, VSUXSEG4EI64_V, 0x7, 0x0 }, // 10448 |
| 17739 | { PseudoVSUXSEG4EI64_V_M2_MF2, VSUXSEG4EI64_V, 0x7, 0x0 }, // 10449 |
| 17740 | { PseudoVSUXSEG4EI64_V_M2_MF2_MASK, VSUXSEG4EI64_V, 0x7, 0x0 }, // 10450 |
| 17741 | { PseudoVSUXSEG4EI64_V_M4_MF2, VSUXSEG4EI64_V, 0x7, 0x0 }, // 10451 |
| 17742 | { PseudoVSUXSEG4EI64_V_M4_MF2_MASK, VSUXSEG4EI64_V, 0x7, 0x0 }, // 10452 |
| 17743 | { PseudoVSUXSEG4EI8_V_M1_M1, VSUXSEG4EI8_V, 0x0, 0x0 }, // 10453 |
| 17744 | { PseudoVSUXSEG4EI8_V_M1_M1_MASK, VSUXSEG4EI8_V, 0x0, 0x0 }, // 10454 |
| 17745 | { PseudoVSUXSEG4EI8_V_MF2_M1, VSUXSEG4EI8_V, 0x0, 0x0 }, // 10455 |
| 17746 | { PseudoVSUXSEG4EI8_V_MF2_M1_MASK, VSUXSEG4EI8_V, 0x0, 0x0 }, // 10456 |
| 17747 | { PseudoVSUXSEG4EI8_V_MF4_M1, VSUXSEG4EI8_V, 0x0, 0x0 }, // 10457 |
| 17748 | { PseudoVSUXSEG4EI8_V_MF4_M1_MASK, VSUXSEG4EI8_V, 0x0, 0x0 }, // 10458 |
| 17749 | { PseudoVSUXSEG4EI8_V_MF8_M1, VSUXSEG4EI8_V, 0x0, 0x0 }, // 10459 |
| 17750 | { PseudoVSUXSEG4EI8_V_MF8_M1_MASK, VSUXSEG4EI8_V, 0x0, 0x0 }, // 10460 |
| 17751 | { PseudoVSUXSEG4EI8_V_M1_M2, VSUXSEG4EI8_V, 0x1, 0x0 }, // 10461 |
| 17752 | { PseudoVSUXSEG4EI8_V_M1_M2_MASK, VSUXSEG4EI8_V, 0x1, 0x0 }, // 10462 |
| 17753 | { PseudoVSUXSEG4EI8_V_M2_M2, VSUXSEG4EI8_V, 0x1, 0x0 }, // 10463 |
| 17754 | { PseudoVSUXSEG4EI8_V_M2_M2_MASK, VSUXSEG4EI8_V, 0x1, 0x0 }, // 10464 |
| 17755 | { PseudoVSUXSEG4EI8_V_MF2_M2, VSUXSEG4EI8_V, 0x1, 0x0 }, // 10465 |
| 17756 | { PseudoVSUXSEG4EI8_V_MF2_M2_MASK, VSUXSEG4EI8_V, 0x1, 0x0 }, // 10466 |
| 17757 | { PseudoVSUXSEG4EI8_V_MF4_M2, VSUXSEG4EI8_V, 0x1, 0x0 }, // 10467 |
| 17758 | { PseudoVSUXSEG4EI8_V_MF4_M2_MASK, VSUXSEG4EI8_V, 0x1, 0x0 }, // 10468 |
| 17759 | { PseudoVSUXSEG4EI8_V_MF8_MF8, VSUXSEG4EI8_V, 0x5, 0x0 }, // 10469 |
| 17760 | { PseudoVSUXSEG4EI8_V_MF8_MF8_MASK, VSUXSEG4EI8_V, 0x5, 0x0 }, // 10470 |
| 17761 | { PseudoVSUXSEG4EI8_V_MF4_MF4, VSUXSEG4EI8_V, 0x6, 0x0 }, // 10471 |
| 17762 | { PseudoVSUXSEG4EI8_V_MF4_MF4_MASK, VSUXSEG4EI8_V, 0x6, 0x0 }, // 10472 |
| 17763 | { PseudoVSUXSEG4EI8_V_MF8_MF4, VSUXSEG4EI8_V, 0x6, 0x0 }, // 10473 |
| 17764 | { PseudoVSUXSEG4EI8_V_MF8_MF4_MASK, VSUXSEG4EI8_V, 0x6, 0x0 }, // 10474 |
| 17765 | { PseudoVSUXSEG4EI8_V_MF2_MF2, VSUXSEG4EI8_V, 0x7, 0x0 }, // 10475 |
| 17766 | { PseudoVSUXSEG4EI8_V_MF2_MF2_MASK, VSUXSEG4EI8_V, 0x7, 0x0 }, // 10476 |
| 17767 | { PseudoVSUXSEG4EI8_V_MF4_MF2, VSUXSEG4EI8_V, 0x7, 0x0 }, // 10477 |
| 17768 | { PseudoVSUXSEG4EI8_V_MF4_MF2_MASK, VSUXSEG4EI8_V, 0x7, 0x0 }, // 10478 |
| 17769 | { PseudoVSUXSEG4EI8_V_MF8_MF2, VSUXSEG4EI8_V, 0x7, 0x0 }, // 10479 |
| 17770 | { PseudoVSUXSEG4EI8_V_MF8_MF2_MASK, VSUXSEG4EI8_V, 0x7, 0x0 }, // 10480 |
| 17771 | { PseudoVSUXSEG5EI16_V_M1_M1, VSUXSEG5EI16_V, 0x0, 0x0 }, // 10481 |
| 17772 | { PseudoVSUXSEG5EI16_V_M1_M1_MASK, VSUXSEG5EI16_V, 0x0, 0x0 }, // 10482 |
| 17773 | { PseudoVSUXSEG5EI16_V_M2_M1, VSUXSEG5EI16_V, 0x0, 0x0 }, // 10483 |
| 17774 | { PseudoVSUXSEG5EI16_V_M2_M1_MASK, VSUXSEG5EI16_V, 0x0, 0x0 }, // 10484 |
| 17775 | { PseudoVSUXSEG5EI16_V_MF2_M1, VSUXSEG5EI16_V, 0x0, 0x0 }, // 10485 |
| 17776 | { PseudoVSUXSEG5EI16_V_MF2_M1_MASK, VSUXSEG5EI16_V, 0x0, 0x0 }, // 10486 |
| 17777 | { PseudoVSUXSEG5EI16_V_MF4_M1, VSUXSEG5EI16_V, 0x0, 0x0 }, // 10487 |
| 17778 | { PseudoVSUXSEG5EI16_V_MF4_M1_MASK, VSUXSEG5EI16_V, 0x0, 0x0 }, // 10488 |
| 17779 | { PseudoVSUXSEG5EI16_V_MF4_MF8, VSUXSEG5EI16_V, 0x5, 0x0 }, // 10489 |
| 17780 | { PseudoVSUXSEG5EI16_V_MF4_MF8_MASK, VSUXSEG5EI16_V, 0x5, 0x0 }, // 10490 |
| 17781 | { PseudoVSUXSEG5EI16_V_MF2_MF4, VSUXSEG5EI16_V, 0x6, 0x0 }, // 10491 |
| 17782 | { PseudoVSUXSEG5EI16_V_MF2_MF4_MASK, VSUXSEG5EI16_V, 0x6, 0x0 }, // 10492 |
| 17783 | { PseudoVSUXSEG5EI16_V_MF4_MF4, VSUXSEG5EI16_V, 0x6, 0x0 }, // 10493 |
| 17784 | { PseudoVSUXSEG5EI16_V_MF4_MF4_MASK, VSUXSEG5EI16_V, 0x6, 0x0 }, // 10494 |
| 17785 | { PseudoVSUXSEG5EI16_V_M1_MF2, VSUXSEG5EI16_V, 0x7, 0x0 }, // 10495 |
| 17786 | { PseudoVSUXSEG5EI16_V_M1_MF2_MASK, VSUXSEG5EI16_V, 0x7, 0x0 }, // 10496 |
| 17787 | { PseudoVSUXSEG5EI16_V_MF2_MF2, VSUXSEG5EI16_V, 0x7, 0x0 }, // 10497 |
| 17788 | { PseudoVSUXSEG5EI16_V_MF2_MF2_MASK, VSUXSEG5EI16_V, 0x7, 0x0 }, // 10498 |
| 17789 | { PseudoVSUXSEG5EI16_V_MF4_MF2, VSUXSEG5EI16_V, 0x7, 0x0 }, // 10499 |
| 17790 | { PseudoVSUXSEG5EI16_V_MF4_MF2_MASK, VSUXSEG5EI16_V, 0x7, 0x0 }, // 10500 |
| 17791 | { PseudoVSUXSEG5EI32_V_M1_M1, VSUXSEG5EI32_V, 0x0, 0x0 }, // 10501 |
| 17792 | { PseudoVSUXSEG5EI32_V_M1_M1_MASK, VSUXSEG5EI32_V, 0x0, 0x0 }, // 10502 |
| 17793 | { PseudoVSUXSEG5EI32_V_M2_M1, VSUXSEG5EI32_V, 0x0, 0x0 }, // 10503 |
| 17794 | { PseudoVSUXSEG5EI32_V_M2_M1_MASK, VSUXSEG5EI32_V, 0x0, 0x0 }, // 10504 |
| 17795 | { PseudoVSUXSEG5EI32_V_M4_M1, VSUXSEG5EI32_V, 0x0, 0x0 }, // 10505 |
| 17796 | { PseudoVSUXSEG5EI32_V_M4_M1_MASK, VSUXSEG5EI32_V, 0x0, 0x0 }, // 10506 |
| 17797 | { PseudoVSUXSEG5EI32_V_MF2_M1, VSUXSEG5EI32_V, 0x0, 0x0 }, // 10507 |
| 17798 | { PseudoVSUXSEG5EI32_V_MF2_M1_MASK, VSUXSEG5EI32_V, 0x0, 0x0 }, // 10508 |
| 17799 | { PseudoVSUXSEG5EI32_V_MF2_MF8, VSUXSEG5EI32_V, 0x5, 0x0 }, // 10509 |
| 17800 | { PseudoVSUXSEG5EI32_V_MF2_MF8_MASK, VSUXSEG5EI32_V, 0x5, 0x0 }, // 10510 |
| 17801 | { PseudoVSUXSEG5EI32_V_M1_MF4, VSUXSEG5EI32_V, 0x6, 0x0 }, // 10511 |
| 17802 | { PseudoVSUXSEG5EI32_V_M1_MF4_MASK, VSUXSEG5EI32_V, 0x6, 0x0 }, // 10512 |
| 17803 | { PseudoVSUXSEG5EI32_V_MF2_MF4, VSUXSEG5EI32_V, 0x6, 0x0 }, // 10513 |
| 17804 | { PseudoVSUXSEG5EI32_V_MF2_MF4_MASK, VSUXSEG5EI32_V, 0x6, 0x0 }, // 10514 |
| 17805 | { PseudoVSUXSEG5EI32_V_M1_MF2, VSUXSEG5EI32_V, 0x7, 0x0 }, // 10515 |
| 17806 | { PseudoVSUXSEG5EI32_V_M1_MF2_MASK, VSUXSEG5EI32_V, 0x7, 0x0 }, // 10516 |
| 17807 | { PseudoVSUXSEG5EI32_V_M2_MF2, VSUXSEG5EI32_V, 0x7, 0x0 }, // 10517 |
| 17808 | { PseudoVSUXSEG5EI32_V_M2_MF2_MASK, VSUXSEG5EI32_V, 0x7, 0x0 }, // 10518 |
| 17809 | { PseudoVSUXSEG5EI32_V_MF2_MF2, VSUXSEG5EI32_V, 0x7, 0x0 }, // 10519 |
| 17810 | { PseudoVSUXSEG5EI32_V_MF2_MF2_MASK, VSUXSEG5EI32_V, 0x7, 0x0 }, // 10520 |
| 17811 | { PseudoVSUXSEG5EI64_V_M1_M1, VSUXSEG5EI64_V, 0x0, 0x0 }, // 10521 |
| 17812 | { PseudoVSUXSEG5EI64_V_M1_M1_MASK, VSUXSEG5EI64_V, 0x0, 0x0 }, // 10522 |
| 17813 | { PseudoVSUXSEG5EI64_V_M2_M1, VSUXSEG5EI64_V, 0x0, 0x0 }, // 10523 |
| 17814 | { PseudoVSUXSEG5EI64_V_M2_M1_MASK, VSUXSEG5EI64_V, 0x0, 0x0 }, // 10524 |
| 17815 | { PseudoVSUXSEG5EI64_V_M4_M1, VSUXSEG5EI64_V, 0x0, 0x0 }, // 10525 |
| 17816 | { PseudoVSUXSEG5EI64_V_M4_M1_MASK, VSUXSEG5EI64_V, 0x0, 0x0 }, // 10526 |
| 17817 | { PseudoVSUXSEG5EI64_V_M8_M1, VSUXSEG5EI64_V, 0x0, 0x0 }, // 10527 |
| 17818 | { PseudoVSUXSEG5EI64_V_M8_M1_MASK, VSUXSEG5EI64_V, 0x0, 0x0 }, // 10528 |
| 17819 | { PseudoVSUXSEG5EI64_V_M1_MF8, VSUXSEG5EI64_V, 0x5, 0x0 }, // 10529 |
| 17820 | { PseudoVSUXSEG5EI64_V_M1_MF8_MASK, VSUXSEG5EI64_V, 0x5, 0x0 }, // 10530 |
| 17821 | { PseudoVSUXSEG5EI64_V_M1_MF4, VSUXSEG5EI64_V, 0x6, 0x0 }, // 10531 |
| 17822 | { PseudoVSUXSEG5EI64_V_M1_MF4_MASK, VSUXSEG5EI64_V, 0x6, 0x0 }, // 10532 |
| 17823 | { PseudoVSUXSEG5EI64_V_M2_MF4, VSUXSEG5EI64_V, 0x6, 0x0 }, // 10533 |
| 17824 | { PseudoVSUXSEG5EI64_V_M2_MF4_MASK, VSUXSEG5EI64_V, 0x6, 0x0 }, // 10534 |
| 17825 | { PseudoVSUXSEG5EI64_V_M1_MF2, VSUXSEG5EI64_V, 0x7, 0x0 }, // 10535 |
| 17826 | { PseudoVSUXSEG5EI64_V_M1_MF2_MASK, VSUXSEG5EI64_V, 0x7, 0x0 }, // 10536 |
| 17827 | { PseudoVSUXSEG5EI64_V_M2_MF2, VSUXSEG5EI64_V, 0x7, 0x0 }, // 10537 |
| 17828 | { PseudoVSUXSEG5EI64_V_M2_MF2_MASK, VSUXSEG5EI64_V, 0x7, 0x0 }, // 10538 |
| 17829 | { PseudoVSUXSEG5EI64_V_M4_MF2, VSUXSEG5EI64_V, 0x7, 0x0 }, // 10539 |
| 17830 | { PseudoVSUXSEG5EI64_V_M4_MF2_MASK, VSUXSEG5EI64_V, 0x7, 0x0 }, // 10540 |
| 17831 | { PseudoVSUXSEG5EI8_V_M1_M1, VSUXSEG5EI8_V, 0x0, 0x0 }, // 10541 |
| 17832 | { PseudoVSUXSEG5EI8_V_M1_M1_MASK, VSUXSEG5EI8_V, 0x0, 0x0 }, // 10542 |
| 17833 | { PseudoVSUXSEG5EI8_V_MF2_M1, VSUXSEG5EI8_V, 0x0, 0x0 }, // 10543 |
| 17834 | { PseudoVSUXSEG5EI8_V_MF2_M1_MASK, VSUXSEG5EI8_V, 0x0, 0x0 }, // 10544 |
| 17835 | { PseudoVSUXSEG5EI8_V_MF4_M1, VSUXSEG5EI8_V, 0x0, 0x0 }, // 10545 |
| 17836 | { PseudoVSUXSEG5EI8_V_MF4_M1_MASK, VSUXSEG5EI8_V, 0x0, 0x0 }, // 10546 |
| 17837 | { PseudoVSUXSEG5EI8_V_MF8_M1, VSUXSEG5EI8_V, 0x0, 0x0 }, // 10547 |
| 17838 | { PseudoVSUXSEG5EI8_V_MF8_M1_MASK, VSUXSEG5EI8_V, 0x0, 0x0 }, // 10548 |
| 17839 | { PseudoVSUXSEG5EI8_V_MF8_MF8, VSUXSEG5EI8_V, 0x5, 0x0 }, // 10549 |
| 17840 | { PseudoVSUXSEG5EI8_V_MF8_MF8_MASK, VSUXSEG5EI8_V, 0x5, 0x0 }, // 10550 |
| 17841 | { PseudoVSUXSEG5EI8_V_MF4_MF4, VSUXSEG5EI8_V, 0x6, 0x0 }, // 10551 |
| 17842 | { PseudoVSUXSEG5EI8_V_MF4_MF4_MASK, VSUXSEG5EI8_V, 0x6, 0x0 }, // 10552 |
| 17843 | { PseudoVSUXSEG5EI8_V_MF8_MF4, VSUXSEG5EI8_V, 0x6, 0x0 }, // 10553 |
| 17844 | { PseudoVSUXSEG5EI8_V_MF8_MF4_MASK, VSUXSEG5EI8_V, 0x6, 0x0 }, // 10554 |
| 17845 | { PseudoVSUXSEG5EI8_V_MF2_MF2, VSUXSEG5EI8_V, 0x7, 0x0 }, // 10555 |
| 17846 | { PseudoVSUXSEG5EI8_V_MF2_MF2_MASK, VSUXSEG5EI8_V, 0x7, 0x0 }, // 10556 |
| 17847 | { PseudoVSUXSEG5EI8_V_MF4_MF2, VSUXSEG5EI8_V, 0x7, 0x0 }, // 10557 |
| 17848 | { PseudoVSUXSEG5EI8_V_MF4_MF2_MASK, VSUXSEG5EI8_V, 0x7, 0x0 }, // 10558 |
| 17849 | { PseudoVSUXSEG5EI8_V_MF8_MF2, VSUXSEG5EI8_V, 0x7, 0x0 }, // 10559 |
| 17850 | { PseudoVSUXSEG5EI8_V_MF8_MF2_MASK, VSUXSEG5EI8_V, 0x7, 0x0 }, // 10560 |
| 17851 | { PseudoVSUXSEG6EI16_V_M1_M1, VSUXSEG6EI16_V, 0x0, 0x0 }, // 10561 |
| 17852 | { PseudoVSUXSEG6EI16_V_M1_M1_MASK, VSUXSEG6EI16_V, 0x0, 0x0 }, // 10562 |
| 17853 | { PseudoVSUXSEG6EI16_V_M2_M1, VSUXSEG6EI16_V, 0x0, 0x0 }, // 10563 |
| 17854 | { PseudoVSUXSEG6EI16_V_M2_M1_MASK, VSUXSEG6EI16_V, 0x0, 0x0 }, // 10564 |
| 17855 | { PseudoVSUXSEG6EI16_V_MF2_M1, VSUXSEG6EI16_V, 0x0, 0x0 }, // 10565 |
| 17856 | { PseudoVSUXSEG6EI16_V_MF2_M1_MASK, VSUXSEG6EI16_V, 0x0, 0x0 }, // 10566 |
| 17857 | { PseudoVSUXSEG6EI16_V_MF4_M1, VSUXSEG6EI16_V, 0x0, 0x0 }, // 10567 |
| 17858 | { PseudoVSUXSEG6EI16_V_MF4_M1_MASK, VSUXSEG6EI16_V, 0x0, 0x0 }, // 10568 |
| 17859 | { PseudoVSUXSEG6EI16_V_MF4_MF8, VSUXSEG6EI16_V, 0x5, 0x0 }, // 10569 |
| 17860 | { PseudoVSUXSEG6EI16_V_MF4_MF8_MASK, VSUXSEG6EI16_V, 0x5, 0x0 }, // 10570 |
| 17861 | { PseudoVSUXSEG6EI16_V_MF2_MF4, VSUXSEG6EI16_V, 0x6, 0x0 }, // 10571 |
| 17862 | { PseudoVSUXSEG6EI16_V_MF2_MF4_MASK, VSUXSEG6EI16_V, 0x6, 0x0 }, // 10572 |
| 17863 | { PseudoVSUXSEG6EI16_V_MF4_MF4, VSUXSEG6EI16_V, 0x6, 0x0 }, // 10573 |
| 17864 | { PseudoVSUXSEG6EI16_V_MF4_MF4_MASK, VSUXSEG6EI16_V, 0x6, 0x0 }, // 10574 |
| 17865 | { PseudoVSUXSEG6EI16_V_M1_MF2, VSUXSEG6EI16_V, 0x7, 0x0 }, // 10575 |
| 17866 | { PseudoVSUXSEG6EI16_V_M1_MF2_MASK, VSUXSEG6EI16_V, 0x7, 0x0 }, // 10576 |
| 17867 | { PseudoVSUXSEG6EI16_V_MF2_MF2, VSUXSEG6EI16_V, 0x7, 0x0 }, // 10577 |
| 17868 | { PseudoVSUXSEG6EI16_V_MF2_MF2_MASK, VSUXSEG6EI16_V, 0x7, 0x0 }, // 10578 |
| 17869 | { PseudoVSUXSEG6EI16_V_MF4_MF2, VSUXSEG6EI16_V, 0x7, 0x0 }, // 10579 |
| 17870 | { PseudoVSUXSEG6EI16_V_MF4_MF2_MASK, VSUXSEG6EI16_V, 0x7, 0x0 }, // 10580 |
| 17871 | { PseudoVSUXSEG6EI32_V_M1_M1, VSUXSEG6EI32_V, 0x0, 0x0 }, // 10581 |
| 17872 | { PseudoVSUXSEG6EI32_V_M1_M1_MASK, VSUXSEG6EI32_V, 0x0, 0x0 }, // 10582 |
| 17873 | { PseudoVSUXSEG6EI32_V_M2_M1, VSUXSEG6EI32_V, 0x0, 0x0 }, // 10583 |
| 17874 | { PseudoVSUXSEG6EI32_V_M2_M1_MASK, VSUXSEG6EI32_V, 0x0, 0x0 }, // 10584 |
| 17875 | { PseudoVSUXSEG6EI32_V_M4_M1, VSUXSEG6EI32_V, 0x0, 0x0 }, // 10585 |
| 17876 | { PseudoVSUXSEG6EI32_V_M4_M1_MASK, VSUXSEG6EI32_V, 0x0, 0x0 }, // 10586 |
| 17877 | { PseudoVSUXSEG6EI32_V_MF2_M1, VSUXSEG6EI32_V, 0x0, 0x0 }, // 10587 |
| 17878 | { PseudoVSUXSEG6EI32_V_MF2_M1_MASK, VSUXSEG6EI32_V, 0x0, 0x0 }, // 10588 |
| 17879 | { PseudoVSUXSEG6EI32_V_MF2_MF8, VSUXSEG6EI32_V, 0x5, 0x0 }, // 10589 |
| 17880 | { PseudoVSUXSEG6EI32_V_MF2_MF8_MASK, VSUXSEG6EI32_V, 0x5, 0x0 }, // 10590 |
| 17881 | { PseudoVSUXSEG6EI32_V_M1_MF4, VSUXSEG6EI32_V, 0x6, 0x0 }, // 10591 |
| 17882 | { PseudoVSUXSEG6EI32_V_M1_MF4_MASK, VSUXSEG6EI32_V, 0x6, 0x0 }, // 10592 |
| 17883 | { PseudoVSUXSEG6EI32_V_MF2_MF4, VSUXSEG6EI32_V, 0x6, 0x0 }, // 10593 |
| 17884 | { PseudoVSUXSEG6EI32_V_MF2_MF4_MASK, VSUXSEG6EI32_V, 0x6, 0x0 }, // 10594 |
| 17885 | { PseudoVSUXSEG6EI32_V_M1_MF2, VSUXSEG6EI32_V, 0x7, 0x0 }, // 10595 |
| 17886 | { PseudoVSUXSEG6EI32_V_M1_MF2_MASK, VSUXSEG6EI32_V, 0x7, 0x0 }, // 10596 |
| 17887 | { PseudoVSUXSEG6EI32_V_M2_MF2, VSUXSEG6EI32_V, 0x7, 0x0 }, // 10597 |
| 17888 | { PseudoVSUXSEG6EI32_V_M2_MF2_MASK, VSUXSEG6EI32_V, 0x7, 0x0 }, // 10598 |
| 17889 | { PseudoVSUXSEG6EI32_V_MF2_MF2, VSUXSEG6EI32_V, 0x7, 0x0 }, // 10599 |
| 17890 | { PseudoVSUXSEG6EI32_V_MF2_MF2_MASK, VSUXSEG6EI32_V, 0x7, 0x0 }, // 10600 |
| 17891 | { PseudoVSUXSEG6EI64_V_M1_M1, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10601 |
| 17892 | { PseudoVSUXSEG6EI64_V_M1_M1_MASK, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10602 |
| 17893 | { PseudoVSUXSEG6EI64_V_M2_M1, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10603 |
| 17894 | { PseudoVSUXSEG6EI64_V_M2_M1_MASK, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10604 |
| 17895 | { PseudoVSUXSEG6EI64_V_M4_M1, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10605 |
| 17896 | { PseudoVSUXSEG6EI64_V_M4_M1_MASK, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10606 |
| 17897 | { PseudoVSUXSEG6EI64_V_M8_M1, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10607 |
| 17898 | { PseudoVSUXSEG6EI64_V_M8_M1_MASK, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10608 |
| 17899 | { PseudoVSUXSEG6EI64_V_M1_MF8, VSUXSEG6EI64_V, 0x5, 0x0 }, // 10609 |
| 17900 | { PseudoVSUXSEG6EI64_V_M1_MF8_MASK, VSUXSEG6EI64_V, 0x5, 0x0 }, // 10610 |
| 17901 | { PseudoVSUXSEG6EI64_V_M1_MF4, VSUXSEG6EI64_V, 0x6, 0x0 }, // 10611 |
| 17902 | { PseudoVSUXSEG6EI64_V_M1_MF4_MASK, VSUXSEG6EI64_V, 0x6, 0x0 }, // 10612 |
| 17903 | { PseudoVSUXSEG6EI64_V_M2_MF4, VSUXSEG6EI64_V, 0x6, 0x0 }, // 10613 |
| 17904 | { PseudoVSUXSEG6EI64_V_M2_MF4_MASK, VSUXSEG6EI64_V, 0x6, 0x0 }, // 10614 |
| 17905 | { PseudoVSUXSEG6EI64_V_M1_MF2, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10615 |
| 17906 | { PseudoVSUXSEG6EI64_V_M1_MF2_MASK, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10616 |
| 17907 | { PseudoVSUXSEG6EI64_V_M2_MF2, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10617 |
| 17908 | { PseudoVSUXSEG6EI64_V_M2_MF2_MASK, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10618 |
| 17909 | { PseudoVSUXSEG6EI64_V_M4_MF2, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10619 |
| 17910 | { PseudoVSUXSEG6EI64_V_M4_MF2_MASK, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10620 |
| 17911 | { PseudoVSUXSEG6EI8_V_M1_M1, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10621 |
| 17912 | { PseudoVSUXSEG6EI8_V_M1_M1_MASK, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10622 |
| 17913 | { PseudoVSUXSEG6EI8_V_MF2_M1, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10623 |
| 17914 | { PseudoVSUXSEG6EI8_V_MF2_M1_MASK, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10624 |
| 17915 | { PseudoVSUXSEG6EI8_V_MF4_M1, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10625 |
| 17916 | { PseudoVSUXSEG6EI8_V_MF4_M1_MASK, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10626 |
| 17917 | { PseudoVSUXSEG6EI8_V_MF8_M1, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10627 |
| 17918 | { PseudoVSUXSEG6EI8_V_MF8_M1_MASK, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10628 |
| 17919 | { PseudoVSUXSEG6EI8_V_MF8_MF8, VSUXSEG6EI8_V, 0x5, 0x0 }, // 10629 |
| 17920 | { PseudoVSUXSEG6EI8_V_MF8_MF8_MASK, VSUXSEG6EI8_V, 0x5, 0x0 }, // 10630 |
| 17921 | { PseudoVSUXSEG6EI8_V_MF4_MF4, VSUXSEG6EI8_V, 0x6, 0x0 }, // 10631 |
| 17922 | { PseudoVSUXSEG6EI8_V_MF4_MF4_MASK, VSUXSEG6EI8_V, 0x6, 0x0 }, // 10632 |
| 17923 | { PseudoVSUXSEG6EI8_V_MF8_MF4, VSUXSEG6EI8_V, 0x6, 0x0 }, // 10633 |
| 17924 | { PseudoVSUXSEG6EI8_V_MF8_MF4_MASK, VSUXSEG6EI8_V, 0x6, 0x0 }, // 10634 |
| 17925 | { PseudoVSUXSEG6EI8_V_MF2_MF2, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10635 |
| 17926 | { PseudoVSUXSEG6EI8_V_MF2_MF2_MASK, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10636 |
| 17927 | { PseudoVSUXSEG6EI8_V_MF4_MF2, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10637 |
| 17928 | { PseudoVSUXSEG6EI8_V_MF4_MF2_MASK, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10638 |
| 17929 | { PseudoVSUXSEG6EI8_V_MF8_MF2, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10639 |
| 17930 | { PseudoVSUXSEG6EI8_V_MF8_MF2_MASK, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10640 |
| 17931 | { PseudoVSUXSEG7EI16_V_M1_M1, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10641 |
| 17932 | { PseudoVSUXSEG7EI16_V_M1_M1_MASK, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10642 |
| 17933 | { PseudoVSUXSEG7EI16_V_M2_M1, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10643 |
| 17934 | { PseudoVSUXSEG7EI16_V_M2_M1_MASK, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10644 |
| 17935 | { PseudoVSUXSEG7EI16_V_MF2_M1, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10645 |
| 17936 | { PseudoVSUXSEG7EI16_V_MF2_M1_MASK, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10646 |
| 17937 | { PseudoVSUXSEG7EI16_V_MF4_M1, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10647 |
| 17938 | { PseudoVSUXSEG7EI16_V_MF4_M1_MASK, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10648 |
| 17939 | { PseudoVSUXSEG7EI16_V_MF4_MF8, VSUXSEG7EI16_V, 0x5, 0x0 }, // 10649 |
| 17940 | { PseudoVSUXSEG7EI16_V_MF4_MF8_MASK, VSUXSEG7EI16_V, 0x5, 0x0 }, // 10650 |
| 17941 | { PseudoVSUXSEG7EI16_V_MF2_MF4, VSUXSEG7EI16_V, 0x6, 0x0 }, // 10651 |
| 17942 | { PseudoVSUXSEG7EI16_V_MF2_MF4_MASK, VSUXSEG7EI16_V, 0x6, 0x0 }, // 10652 |
| 17943 | { PseudoVSUXSEG7EI16_V_MF4_MF4, VSUXSEG7EI16_V, 0x6, 0x0 }, // 10653 |
| 17944 | { PseudoVSUXSEG7EI16_V_MF4_MF4_MASK, VSUXSEG7EI16_V, 0x6, 0x0 }, // 10654 |
| 17945 | { PseudoVSUXSEG7EI16_V_M1_MF2, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10655 |
| 17946 | { PseudoVSUXSEG7EI16_V_M1_MF2_MASK, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10656 |
| 17947 | { PseudoVSUXSEG7EI16_V_MF2_MF2, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10657 |
| 17948 | { PseudoVSUXSEG7EI16_V_MF2_MF2_MASK, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10658 |
| 17949 | { PseudoVSUXSEG7EI16_V_MF4_MF2, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10659 |
| 17950 | { PseudoVSUXSEG7EI16_V_MF4_MF2_MASK, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10660 |
| 17951 | { PseudoVSUXSEG7EI32_V_M1_M1, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10661 |
| 17952 | { PseudoVSUXSEG7EI32_V_M1_M1_MASK, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10662 |
| 17953 | { PseudoVSUXSEG7EI32_V_M2_M1, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10663 |
| 17954 | { PseudoVSUXSEG7EI32_V_M2_M1_MASK, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10664 |
| 17955 | { PseudoVSUXSEG7EI32_V_M4_M1, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10665 |
| 17956 | { PseudoVSUXSEG7EI32_V_M4_M1_MASK, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10666 |
| 17957 | { PseudoVSUXSEG7EI32_V_MF2_M1, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10667 |
| 17958 | { PseudoVSUXSEG7EI32_V_MF2_M1_MASK, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10668 |
| 17959 | { PseudoVSUXSEG7EI32_V_MF2_MF8, VSUXSEG7EI32_V, 0x5, 0x0 }, // 10669 |
| 17960 | { PseudoVSUXSEG7EI32_V_MF2_MF8_MASK, VSUXSEG7EI32_V, 0x5, 0x0 }, // 10670 |
| 17961 | { PseudoVSUXSEG7EI32_V_M1_MF4, VSUXSEG7EI32_V, 0x6, 0x0 }, // 10671 |
| 17962 | { PseudoVSUXSEG7EI32_V_M1_MF4_MASK, VSUXSEG7EI32_V, 0x6, 0x0 }, // 10672 |
| 17963 | { PseudoVSUXSEG7EI32_V_MF2_MF4, VSUXSEG7EI32_V, 0x6, 0x0 }, // 10673 |
| 17964 | { PseudoVSUXSEG7EI32_V_MF2_MF4_MASK, VSUXSEG7EI32_V, 0x6, 0x0 }, // 10674 |
| 17965 | { PseudoVSUXSEG7EI32_V_M1_MF2, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10675 |
| 17966 | { PseudoVSUXSEG7EI32_V_M1_MF2_MASK, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10676 |
| 17967 | { PseudoVSUXSEG7EI32_V_M2_MF2, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10677 |
| 17968 | { PseudoVSUXSEG7EI32_V_M2_MF2_MASK, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10678 |
| 17969 | { PseudoVSUXSEG7EI32_V_MF2_MF2, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10679 |
| 17970 | { PseudoVSUXSEG7EI32_V_MF2_MF2_MASK, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10680 |
| 17971 | { PseudoVSUXSEG7EI64_V_M1_M1, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10681 |
| 17972 | { PseudoVSUXSEG7EI64_V_M1_M1_MASK, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10682 |
| 17973 | { PseudoVSUXSEG7EI64_V_M2_M1, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10683 |
| 17974 | { PseudoVSUXSEG7EI64_V_M2_M1_MASK, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10684 |
| 17975 | { PseudoVSUXSEG7EI64_V_M4_M1, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10685 |
| 17976 | { PseudoVSUXSEG7EI64_V_M4_M1_MASK, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10686 |
| 17977 | { PseudoVSUXSEG7EI64_V_M8_M1, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10687 |
| 17978 | { PseudoVSUXSEG7EI64_V_M8_M1_MASK, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10688 |
| 17979 | { PseudoVSUXSEG7EI64_V_M1_MF8, VSUXSEG7EI64_V, 0x5, 0x0 }, // 10689 |
| 17980 | { PseudoVSUXSEG7EI64_V_M1_MF8_MASK, VSUXSEG7EI64_V, 0x5, 0x0 }, // 10690 |
| 17981 | { PseudoVSUXSEG7EI64_V_M1_MF4, VSUXSEG7EI64_V, 0x6, 0x0 }, // 10691 |
| 17982 | { PseudoVSUXSEG7EI64_V_M1_MF4_MASK, VSUXSEG7EI64_V, 0x6, 0x0 }, // 10692 |
| 17983 | { PseudoVSUXSEG7EI64_V_M2_MF4, VSUXSEG7EI64_V, 0x6, 0x0 }, // 10693 |
| 17984 | { PseudoVSUXSEG7EI64_V_M2_MF4_MASK, VSUXSEG7EI64_V, 0x6, 0x0 }, // 10694 |
| 17985 | { PseudoVSUXSEG7EI64_V_M1_MF2, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10695 |
| 17986 | { PseudoVSUXSEG7EI64_V_M1_MF2_MASK, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10696 |
| 17987 | { PseudoVSUXSEG7EI64_V_M2_MF2, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10697 |
| 17988 | { PseudoVSUXSEG7EI64_V_M2_MF2_MASK, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10698 |
| 17989 | { PseudoVSUXSEG7EI64_V_M4_MF2, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10699 |
| 17990 | { PseudoVSUXSEG7EI64_V_M4_MF2_MASK, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10700 |
| 17991 | { PseudoVSUXSEG7EI8_V_M1_M1, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10701 |
| 17992 | { PseudoVSUXSEG7EI8_V_M1_M1_MASK, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10702 |
| 17993 | { PseudoVSUXSEG7EI8_V_MF2_M1, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10703 |
| 17994 | { PseudoVSUXSEG7EI8_V_MF2_M1_MASK, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10704 |
| 17995 | { PseudoVSUXSEG7EI8_V_MF4_M1, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10705 |
| 17996 | { PseudoVSUXSEG7EI8_V_MF4_M1_MASK, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10706 |
| 17997 | { PseudoVSUXSEG7EI8_V_MF8_M1, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10707 |
| 17998 | { PseudoVSUXSEG7EI8_V_MF8_M1_MASK, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10708 |
| 17999 | { PseudoVSUXSEG7EI8_V_MF8_MF8, VSUXSEG7EI8_V, 0x5, 0x0 }, // 10709 |
| 18000 | { PseudoVSUXSEG7EI8_V_MF8_MF8_MASK, VSUXSEG7EI8_V, 0x5, 0x0 }, // 10710 |
| 18001 | { PseudoVSUXSEG7EI8_V_MF4_MF4, VSUXSEG7EI8_V, 0x6, 0x0 }, // 10711 |
| 18002 | { PseudoVSUXSEG7EI8_V_MF4_MF4_MASK, VSUXSEG7EI8_V, 0x6, 0x0 }, // 10712 |
| 18003 | { PseudoVSUXSEG7EI8_V_MF8_MF4, VSUXSEG7EI8_V, 0x6, 0x0 }, // 10713 |
| 18004 | { PseudoVSUXSEG7EI8_V_MF8_MF4_MASK, VSUXSEG7EI8_V, 0x6, 0x0 }, // 10714 |
| 18005 | { PseudoVSUXSEG7EI8_V_MF2_MF2, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10715 |
| 18006 | { PseudoVSUXSEG7EI8_V_MF2_MF2_MASK, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10716 |
| 18007 | { PseudoVSUXSEG7EI8_V_MF4_MF2, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10717 |
| 18008 | { PseudoVSUXSEG7EI8_V_MF4_MF2_MASK, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10718 |
| 18009 | { PseudoVSUXSEG7EI8_V_MF8_MF2, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10719 |
| 18010 | { PseudoVSUXSEG7EI8_V_MF8_MF2_MASK, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10720 |
| 18011 | { PseudoVSUXSEG8EI16_V_M1_M1, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10721 |
| 18012 | { PseudoVSUXSEG8EI16_V_M1_M1_MASK, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10722 |
| 18013 | { PseudoVSUXSEG8EI16_V_M2_M1, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10723 |
| 18014 | { PseudoVSUXSEG8EI16_V_M2_M1_MASK, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10724 |
| 18015 | { PseudoVSUXSEG8EI16_V_MF2_M1, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10725 |
| 18016 | { PseudoVSUXSEG8EI16_V_MF2_M1_MASK, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10726 |
| 18017 | { PseudoVSUXSEG8EI16_V_MF4_M1, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10727 |
| 18018 | { PseudoVSUXSEG8EI16_V_MF4_M1_MASK, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10728 |
| 18019 | { PseudoVSUXSEG8EI16_V_MF4_MF8, VSUXSEG8EI16_V, 0x5, 0x0 }, // 10729 |
| 18020 | { PseudoVSUXSEG8EI16_V_MF4_MF8_MASK, VSUXSEG8EI16_V, 0x5, 0x0 }, // 10730 |
| 18021 | { PseudoVSUXSEG8EI16_V_MF2_MF4, VSUXSEG8EI16_V, 0x6, 0x0 }, // 10731 |
| 18022 | { PseudoVSUXSEG8EI16_V_MF2_MF4_MASK, VSUXSEG8EI16_V, 0x6, 0x0 }, // 10732 |
| 18023 | { PseudoVSUXSEG8EI16_V_MF4_MF4, VSUXSEG8EI16_V, 0x6, 0x0 }, // 10733 |
| 18024 | { PseudoVSUXSEG8EI16_V_MF4_MF4_MASK, VSUXSEG8EI16_V, 0x6, 0x0 }, // 10734 |
| 18025 | { PseudoVSUXSEG8EI16_V_M1_MF2, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10735 |
| 18026 | { PseudoVSUXSEG8EI16_V_M1_MF2_MASK, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10736 |
| 18027 | { PseudoVSUXSEG8EI16_V_MF2_MF2, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10737 |
| 18028 | { PseudoVSUXSEG8EI16_V_MF2_MF2_MASK, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10738 |
| 18029 | { PseudoVSUXSEG8EI16_V_MF4_MF2, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10739 |
| 18030 | { PseudoVSUXSEG8EI16_V_MF4_MF2_MASK, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10740 |
| 18031 | { PseudoVSUXSEG8EI32_V_M1_M1, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10741 |
| 18032 | { PseudoVSUXSEG8EI32_V_M1_M1_MASK, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10742 |
| 18033 | { PseudoVSUXSEG8EI32_V_M2_M1, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10743 |
| 18034 | { PseudoVSUXSEG8EI32_V_M2_M1_MASK, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10744 |
| 18035 | { PseudoVSUXSEG8EI32_V_M4_M1, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10745 |
| 18036 | { PseudoVSUXSEG8EI32_V_M4_M1_MASK, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10746 |
| 18037 | { PseudoVSUXSEG8EI32_V_MF2_M1, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10747 |
| 18038 | { PseudoVSUXSEG8EI32_V_MF2_M1_MASK, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10748 |
| 18039 | { PseudoVSUXSEG8EI32_V_MF2_MF8, VSUXSEG8EI32_V, 0x5, 0x0 }, // 10749 |
| 18040 | { PseudoVSUXSEG8EI32_V_MF2_MF8_MASK, VSUXSEG8EI32_V, 0x5, 0x0 }, // 10750 |
| 18041 | { PseudoVSUXSEG8EI32_V_M1_MF4, VSUXSEG8EI32_V, 0x6, 0x0 }, // 10751 |
| 18042 | { PseudoVSUXSEG8EI32_V_M1_MF4_MASK, VSUXSEG8EI32_V, 0x6, 0x0 }, // 10752 |
| 18043 | { PseudoVSUXSEG8EI32_V_MF2_MF4, VSUXSEG8EI32_V, 0x6, 0x0 }, // 10753 |
| 18044 | { PseudoVSUXSEG8EI32_V_MF2_MF4_MASK, VSUXSEG8EI32_V, 0x6, 0x0 }, // 10754 |
| 18045 | { PseudoVSUXSEG8EI32_V_M1_MF2, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10755 |
| 18046 | { PseudoVSUXSEG8EI32_V_M1_MF2_MASK, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10756 |
| 18047 | { PseudoVSUXSEG8EI32_V_M2_MF2, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10757 |
| 18048 | { PseudoVSUXSEG8EI32_V_M2_MF2_MASK, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10758 |
| 18049 | { PseudoVSUXSEG8EI32_V_MF2_MF2, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10759 |
| 18050 | { PseudoVSUXSEG8EI32_V_MF2_MF2_MASK, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10760 |
| 18051 | { PseudoVSUXSEG8EI64_V_M1_M1, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10761 |
| 18052 | { PseudoVSUXSEG8EI64_V_M1_M1_MASK, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10762 |
| 18053 | { PseudoVSUXSEG8EI64_V_M2_M1, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10763 |
| 18054 | { PseudoVSUXSEG8EI64_V_M2_M1_MASK, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10764 |
| 18055 | { PseudoVSUXSEG8EI64_V_M4_M1, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10765 |
| 18056 | { PseudoVSUXSEG8EI64_V_M4_M1_MASK, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10766 |
| 18057 | { PseudoVSUXSEG8EI64_V_M8_M1, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10767 |
| 18058 | { PseudoVSUXSEG8EI64_V_M8_M1_MASK, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10768 |
| 18059 | { PseudoVSUXSEG8EI64_V_M1_MF8, VSUXSEG8EI64_V, 0x5, 0x0 }, // 10769 |
| 18060 | { PseudoVSUXSEG8EI64_V_M1_MF8_MASK, VSUXSEG8EI64_V, 0x5, 0x0 }, // 10770 |
| 18061 | { PseudoVSUXSEG8EI64_V_M1_MF4, VSUXSEG8EI64_V, 0x6, 0x0 }, // 10771 |
| 18062 | { PseudoVSUXSEG8EI64_V_M1_MF4_MASK, VSUXSEG8EI64_V, 0x6, 0x0 }, // 10772 |
| 18063 | { PseudoVSUXSEG8EI64_V_M2_MF4, VSUXSEG8EI64_V, 0x6, 0x0 }, // 10773 |
| 18064 | { PseudoVSUXSEG8EI64_V_M2_MF4_MASK, VSUXSEG8EI64_V, 0x6, 0x0 }, // 10774 |
| 18065 | { PseudoVSUXSEG8EI64_V_M1_MF2, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10775 |
| 18066 | { PseudoVSUXSEG8EI64_V_M1_MF2_MASK, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10776 |
| 18067 | { PseudoVSUXSEG8EI64_V_M2_MF2, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10777 |
| 18068 | { PseudoVSUXSEG8EI64_V_M2_MF2_MASK, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10778 |
| 18069 | { PseudoVSUXSEG8EI64_V_M4_MF2, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10779 |
| 18070 | { PseudoVSUXSEG8EI64_V_M4_MF2_MASK, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10780 |
| 18071 | { PseudoVSUXSEG8EI8_V_M1_M1, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10781 |
| 18072 | { PseudoVSUXSEG8EI8_V_M1_M1_MASK, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10782 |
| 18073 | { PseudoVSUXSEG8EI8_V_MF2_M1, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10783 |
| 18074 | { PseudoVSUXSEG8EI8_V_MF2_M1_MASK, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10784 |
| 18075 | { PseudoVSUXSEG8EI8_V_MF4_M1, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10785 |
| 18076 | { PseudoVSUXSEG8EI8_V_MF4_M1_MASK, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10786 |
| 18077 | { PseudoVSUXSEG8EI8_V_MF8_M1, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10787 |
| 18078 | { PseudoVSUXSEG8EI8_V_MF8_M1_MASK, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10788 |
| 18079 | { PseudoVSUXSEG8EI8_V_MF8_MF8, VSUXSEG8EI8_V, 0x5, 0x0 }, // 10789 |
| 18080 | { PseudoVSUXSEG8EI8_V_MF8_MF8_MASK, VSUXSEG8EI8_V, 0x5, 0x0 }, // 10790 |
| 18081 | { PseudoVSUXSEG8EI8_V_MF4_MF4, VSUXSEG8EI8_V, 0x6, 0x0 }, // 10791 |
| 18082 | { PseudoVSUXSEG8EI8_V_MF4_MF4_MASK, VSUXSEG8EI8_V, 0x6, 0x0 }, // 10792 |
| 18083 | { PseudoVSUXSEG8EI8_V_MF8_MF4, VSUXSEG8EI8_V, 0x6, 0x0 }, // 10793 |
| 18084 | { PseudoVSUXSEG8EI8_V_MF8_MF4_MASK, VSUXSEG8EI8_V, 0x6, 0x0 }, // 10794 |
| 18085 | { PseudoVSUXSEG8EI8_V_MF2_MF2, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10795 |
| 18086 | { PseudoVSUXSEG8EI8_V_MF2_MF2_MASK, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10796 |
| 18087 | { PseudoVSUXSEG8EI8_V_MF4_MF2, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10797 |
| 18088 | { PseudoVSUXSEG8EI8_V_MF4_MF2_MASK, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10798 |
| 18089 | { PseudoVSUXSEG8EI8_V_MF8_MF2, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10799 |
| 18090 | { PseudoVSUXSEG8EI8_V_MF8_MF2_MASK, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10800 |
| 18091 | { PseudoVWADDU_VV_M1, VWADDU_VV, 0x0, 0x0 }, // 10801 |
| 18092 | { PseudoVWADDU_VV_M1_MASK, VWADDU_VV, 0x0, 0x0 }, // 10802 |
| 18093 | { PseudoVWADDU_VV_M2, VWADDU_VV, 0x1, 0x0 }, // 10803 |
| 18094 | { PseudoVWADDU_VV_M2_MASK, VWADDU_VV, 0x1, 0x0 }, // 10804 |
| 18095 | { PseudoVWADDU_VV_M4, VWADDU_VV, 0x2, 0x0 }, // 10805 |
| 18096 | { PseudoVWADDU_VV_M4_MASK, VWADDU_VV, 0x2, 0x0 }, // 10806 |
| 18097 | { PseudoVWADDU_VV_MF8, VWADDU_VV, 0x5, 0x0 }, // 10807 |
| 18098 | { PseudoVWADDU_VV_MF8_MASK, VWADDU_VV, 0x5, 0x0 }, // 10808 |
| 18099 | { PseudoVWADDU_VV_MF4, VWADDU_VV, 0x6, 0x0 }, // 10809 |
| 18100 | { PseudoVWADDU_VV_MF4_MASK, VWADDU_VV, 0x6, 0x0 }, // 10810 |
| 18101 | { PseudoVWADDU_VV_MF2, VWADDU_VV, 0x7, 0x0 }, // 10811 |
| 18102 | { PseudoVWADDU_VV_MF2_MASK, VWADDU_VV, 0x7, 0x0 }, // 10812 |
| 18103 | { PseudoVWADDU_VX_M1, VWADDU_VX, 0x0, 0x0 }, // 10813 |
| 18104 | { PseudoVWADDU_VX_M1_MASK, VWADDU_VX, 0x0, 0x0 }, // 10814 |
| 18105 | { PseudoVWADDU_VX_M2, VWADDU_VX, 0x1, 0x0 }, // 10815 |
| 18106 | { PseudoVWADDU_VX_M2_MASK, VWADDU_VX, 0x1, 0x0 }, // 10816 |
| 18107 | { PseudoVWADDU_VX_M4, VWADDU_VX, 0x2, 0x0 }, // 10817 |
| 18108 | { PseudoVWADDU_VX_M4_MASK, VWADDU_VX, 0x2, 0x0 }, // 10818 |
| 18109 | { PseudoVWADDU_VX_MF8, VWADDU_VX, 0x5, 0x0 }, // 10819 |
| 18110 | { PseudoVWADDU_VX_MF8_MASK, VWADDU_VX, 0x5, 0x0 }, // 10820 |
| 18111 | { PseudoVWADDU_VX_MF4, VWADDU_VX, 0x6, 0x0 }, // 10821 |
| 18112 | { PseudoVWADDU_VX_MF4_MASK, VWADDU_VX, 0x6, 0x0 }, // 10822 |
| 18113 | { PseudoVWADDU_VX_MF2, VWADDU_VX, 0x7, 0x0 }, // 10823 |
| 18114 | { PseudoVWADDU_VX_MF2_MASK, VWADDU_VX, 0x7, 0x0 }, // 10824 |
| 18115 | { PseudoVWADDU_WV_M1, VWADDU_WV, 0x0, 0x0 }, // 10825 |
| 18116 | { PseudoVWADDU_WV_M1_MASK, VWADDU_WV, 0x0, 0x0 }, // 10826 |
| 18117 | { PseudoVWADDU_WV_M1_MASK_TIED, VWADDU_WV, 0x0, 0x0 }, // 10827 |
| 18118 | { PseudoVWADDU_WV_M1_TIED, VWADDU_WV, 0x0, 0x0 }, // 10828 |
| 18119 | { PseudoVWADDU_WV_M2, VWADDU_WV, 0x1, 0x0 }, // 10829 |
| 18120 | { PseudoVWADDU_WV_M2_MASK, VWADDU_WV, 0x1, 0x0 }, // 10830 |
| 18121 | { PseudoVWADDU_WV_M2_MASK_TIED, VWADDU_WV, 0x1, 0x0 }, // 10831 |
| 18122 | { PseudoVWADDU_WV_M2_TIED, VWADDU_WV, 0x1, 0x0 }, // 10832 |
| 18123 | { PseudoVWADDU_WV_M4, VWADDU_WV, 0x2, 0x0 }, // 10833 |
| 18124 | { PseudoVWADDU_WV_M4_MASK, VWADDU_WV, 0x2, 0x0 }, // 10834 |
| 18125 | { PseudoVWADDU_WV_M4_MASK_TIED, VWADDU_WV, 0x2, 0x0 }, // 10835 |
| 18126 | { PseudoVWADDU_WV_M4_TIED, VWADDU_WV, 0x2, 0x0 }, // 10836 |
| 18127 | { PseudoVWADDU_WV_MF8, VWADDU_WV, 0x5, 0x0 }, // 10837 |
| 18128 | { PseudoVWADDU_WV_MF8_MASK, VWADDU_WV, 0x5, 0x0 }, // 10838 |
| 18129 | { PseudoVWADDU_WV_MF8_MASK_TIED, VWADDU_WV, 0x5, 0x0 }, // 10839 |
| 18130 | { PseudoVWADDU_WV_MF8_TIED, VWADDU_WV, 0x5, 0x0 }, // 10840 |
| 18131 | { PseudoVWADDU_WV_MF4, VWADDU_WV, 0x6, 0x0 }, // 10841 |
| 18132 | { PseudoVWADDU_WV_MF4_MASK, VWADDU_WV, 0x6, 0x0 }, // 10842 |
| 18133 | { PseudoVWADDU_WV_MF4_MASK_TIED, VWADDU_WV, 0x6, 0x0 }, // 10843 |
| 18134 | { PseudoVWADDU_WV_MF4_TIED, VWADDU_WV, 0x6, 0x0 }, // 10844 |
| 18135 | { PseudoVWADDU_WV_MF2, VWADDU_WV, 0x7, 0x0 }, // 10845 |
| 18136 | { PseudoVWADDU_WV_MF2_MASK, VWADDU_WV, 0x7, 0x0 }, // 10846 |
| 18137 | { PseudoVWADDU_WV_MF2_MASK_TIED, VWADDU_WV, 0x7, 0x0 }, // 10847 |
| 18138 | { PseudoVWADDU_WV_MF2_TIED, VWADDU_WV, 0x7, 0x0 }, // 10848 |
| 18139 | { PseudoVWADDU_WX_M1, VWADDU_WX, 0x0, 0x0 }, // 10849 |
| 18140 | { PseudoVWADDU_WX_M1_MASK, VWADDU_WX, 0x0, 0x0 }, // 10850 |
| 18141 | { PseudoVWADDU_WX_M2, VWADDU_WX, 0x1, 0x0 }, // 10851 |
| 18142 | { PseudoVWADDU_WX_M2_MASK, VWADDU_WX, 0x1, 0x0 }, // 10852 |
| 18143 | { PseudoVWADDU_WX_M4, VWADDU_WX, 0x2, 0x0 }, // 10853 |
| 18144 | { PseudoVWADDU_WX_M4_MASK, VWADDU_WX, 0x2, 0x0 }, // 10854 |
| 18145 | { PseudoVWADDU_WX_MF8, VWADDU_WX, 0x5, 0x0 }, // 10855 |
| 18146 | { PseudoVWADDU_WX_MF8_MASK, VWADDU_WX, 0x5, 0x0 }, // 10856 |
| 18147 | { PseudoVWADDU_WX_MF4, VWADDU_WX, 0x6, 0x0 }, // 10857 |
| 18148 | { PseudoVWADDU_WX_MF4_MASK, VWADDU_WX, 0x6, 0x0 }, // 10858 |
| 18149 | { PseudoVWADDU_WX_MF2, VWADDU_WX, 0x7, 0x0 }, // 10859 |
| 18150 | { PseudoVWADDU_WX_MF2_MASK, VWADDU_WX, 0x7, 0x0 }, // 10860 |
| 18151 | { PseudoVWADD_VV_M1, VWADD_VV, 0x0, 0x0 }, // 10861 |
| 18152 | { PseudoVWADD_VV_M1_MASK, VWADD_VV, 0x0, 0x0 }, // 10862 |
| 18153 | { PseudoVWADD_VV_M2, VWADD_VV, 0x1, 0x0 }, // 10863 |
| 18154 | { PseudoVWADD_VV_M2_MASK, VWADD_VV, 0x1, 0x0 }, // 10864 |
| 18155 | { PseudoVWADD_VV_M4, VWADD_VV, 0x2, 0x0 }, // 10865 |
| 18156 | { PseudoVWADD_VV_M4_MASK, VWADD_VV, 0x2, 0x0 }, // 10866 |
| 18157 | { PseudoVWADD_VV_MF8, VWADD_VV, 0x5, 0x0 }, // 10867 |
| 18158 | { PseudoVWADD_VV_MF8_MASK, VWADD_VV, 0x5, 0x0 }, // 10868 |
| 18159 | { PseudoVWADD_VV_MF4, VWADD_VV, 0x6, 0x0 }, // 10869 |
| 18160 | { PseudoVWADD_VV_MF4_MASK, VWADD_VV, 0x6, 0x0 }, // 10870 |
| 18161 | { PseudoVWADD_VV_MF2, VWADD_VV, 0x7, 0x0 }, // 10871 |
| 18162 | { PseudoVWADD_VV_MF2_MASK, VWADD_VV, 0x7, 0x0 }, // 10872 |
| 18163 | { PseudoVWADD_VX_M1, VWADD_VX, 0x0, 0x0 }, // 10873 |
| 18164 | { PseudoVWADD_VX_M1_MASK, VWADD_VX, 0x0, 0x0 }, // 10874 |
| 18165 | { PseudoVWADD_VX_M2, VWADD_VX, 0x1, 0x0 }, // 10875 |
| 18166 | { PseudoVWADD_VX_M2_MASK, VWADD_VX, 0x1, 0x0 }, // 10876 |
| 18167 | { PseudoVWADD_VX_M4, VWADD_VX, 0x2, 0x0 }, // 10877 |
| 18168 | { PseudoVWADD_VX_M4_MASK, VWADD_VX, 0x2, 0x0 }, // 10878 |
| 18169 | { PseudoVWADD_VX_MF8, VWADD_VX, 0x5, 0x0 }, // 10879 |
| 18170 | { PseudoVWADD_VX_MF8_MASK, VWADD_VX, 0x5, 0x0 }, // 10880 |
| 18171 | { PseudoVWADD_VX_MF4, VWADD_VX, 0x6, 0x0 }, // 10881 |
| 18172 | { PseudoVWADD_VX_MF4_MASK, VWADD_VX, 0x6, 0x0 }, // 10882 |
| 18173 | { PseudoVWADD_VX_MF2, VWADD_VX, 0x7, 0x0 }, // 10883 |
| 18174 | { PseudoVWADD_VX_MF2_MASK, VWADD_VX, 0x7, 0x0 }, // 10884 |
| 18175 | { PseudoVWADD_WV_M1, VWADD_WV, 0x0, 0x0 }, // 10885 |
| 18176 | { PseudoVWADD_WV_M1_MASK, VWADD_WV, 0x0, 0x0 }, // 10886 |
| 18177 | { PseudoVWADD_WV_M1_MASK_TIED, VWADD_WV, 0x0, 0x0 }, // 10887 |
| 18178 | { PseudoVWADD_WV_M1_TIED, VWADD_WV, 0x0, 0x0 }, // 10888 |
| 18179 | { PseudoVWADD_WV_M2, VWADD_WV, 0x1, 0x0 }, // 10889 |
| 18180 | { PseudoVWADD_WV_M2_MASK, VWADD_WV, 0x1, 0x0 }, // 10890 |
| 18181 | { PseudoVWADD_WV_M2_MASK_TIED, VWADD_WV, 0x1, 0x0 }, // 10891 |
| 18182 | { PseudoVWADD_WV_M2_TIED, VWADD_WV, 0x1, 0x0 }, // 10892 |
| 18183 | { PseudoVWADD_WV_M4, VWADD_WV, 0x2, 0x0 }, // 10893 |
| 18184 | { PseudoVWADD_WV_M4_MASK, VWADD_WV, 0x2, 0x0 }, // 10894 |
| 18185 | { PseudoVWADD_WV_M4_MASK_TIED, VWADD_WV, 0x2, 0x0 }, // 10895 |
| 18186 | { PseudoVWADD_WV_M4_TIED, VWADD_WV, 0x2, 0x0 }, // 10896 |
| 18187 | { PseudoVWADD_WV_MF8, VWADD_WV, 0x5, 0x0 }, // 10897 |
| 18188 | { PseudoVWADD_WV_MF8_MASK, VWADD_WV, 0x5, 0x0 }, // 10898 |
| 18189 | { PseudoVWADD_WV_MF8_MASK_TIED, VWADD_WV, 0x5, 0x0 }, // 10899 |
| 18190 | { PseudoVWADD_WV_MF8_TIED, VWADD_WV, 0x5, 0x0 }, // 10900 |
| 18191 | { PseudoVWADD_WV_MF4, VWADD_WV, 0x6, 0x0 }, // 10901 |
| 18192 | { PseudoVWADD_WV_MF4_MASK, VWADD_WV, 0x6, 0x0 }, // 10902 |
| 18193 | { PseudoVWADD_WV_MF4_MASK_TIED, VWADD_WV, 0x6, 0x0 }, // 10903 |
| 18194 | { PseudoVWADD_WV_MF4_TIED, VWADD_WV, 0x6, 0x0 }, // 10904 |
| 18195 | { PseudoVWADD_WV_MF2, VWADD_WV, 0x7, 0x0 }, // 10905 |
| 18196 | { PseudoVWADD_WV_MF2_MASK, VWADD_WV, 0x7, 0x0 }, // 10906 |
| 18197 | { PseudoVWADD_WV_MF2_MASK_TIED, VWADD_WV, 0x7, 0x0 }, // 10907 |
| 18198 | { PseudoVWADD_WV_MF2_TIED, VWADD_WV, 0x7, 0x0 }, // 10908 |
| 18199 | { PseudoVWADD_WX_M1, VWADD_WX, 0x0, 0x0 }, // 10909 |
| 18200 | { PseudoVWADD_WX_M1_MASK, VWADD_WX, 0x0, 0x0 }, // 10910 |
| 18201 | { PseudoVWADD_WX_M2, VWADD_WX, 0x1, 0x0 }, // 10911 |
| 18202 | { PseudoVWADD_WX_M2_MASK, VWADD_WX, 0x1, 0x0 }, // 10912 |
| 18203 | { PseudoVWADD_WX_M4, VWADD_WX, 0x2, 0x0 }, // 10913 |
| 18204 | { PseudoVWADD_WX_M4_MASK, VWADD_WX, 0x2, 0x0 }, // 10914 |
| 18205 | { PseudoVWADD_WX_MF8, VWADD_WX, 0x5, 0x0 }, // 10915 |
| 18206 | { PseudoVWADD_WX_MF8_MASK, VWADD_WX, 0x5, 0x0 }, // 10916 |
| 18207 | { PseudoVWADD_WX_MF4, VWADD_WX, 0x6, 0x0 }, // 10917 |
| 18208 | { PseudoVWADD_WX_MF4_MASK, VWADD_WX, 0x6, 0x0 }, // 10918 |
| 18209 | { PseudoVWADD_WX_MF2, VWADD_WX, 0x7, 0x0 }, // 10919 |
| 18210 | { PseudoVWADD_WX_MF2_MASK, VWADD_WX, 0x7, 0x0 }, // 10920 |
| 18211 | { PseudoVWMACCSU_VV_M1, VWMACCSU_VV, 0x0, 0x0 }, // 10921 |
| 18212 | { PseudoVWMACCSU_VV_M1_MASK, VWMACCSU_VV, 0x0, 0x0 }, // 10922 |
| 18213 | { PseudoVWMACCSU_VV_M2, VWMACCSU_VV, 0x1, 0x0 }, // 10923 |
| 18214 | { PseudoVWMACCSU_VV_M2_MASK, VWMACCSU_VV, 0x1, 0x0 }, // 10924 |
| 18215 | { PseudoVWMACCSU_VV_M4, VWMACCSU_VV, 0x2, 0x0 }, // 10925 |
| 18216 | { PseudoVWMACCSU_VV_M4_MASK, VWMACCSU_VV, 0x2, 0x0 }, // 10926 |
| 18217 | { PseudoVWMACCSU_VV_MF8, VWMACCSU_VV, 0x5, 0x0 }, // 10927 |
| 18218 | { PseudoVWMACCSU_VV_MF8_MASK, VWMACCSU_VV, 0x5, 0x0 }, // 10928 |
| 18219 | { PseudoVWMACCSU_VV_MF4, VWMACCSU_VV, 0x6, 0x0 }, // 10929 |
| 18220 | { PseudoVWMACCSU_VV_MF4_MASK, VWMACCSU_VV, 0x6, 0x0 }, // 10930 |
| 18221 | { PseudoVWMACCSU_VV_MF2, VWMACCSU_VV, 0x7, 0x0 }, // 10931 |
| 18222 | { PseudoVWMACCSU_VV_MF2_MASK, VWMACCSU_VV, 0x7, 0x0 }, // 10932 |
| 18223 | { PseudoVWMACCSU_VX_M1, VWMACCSU_VX, 0x0, 0x0 }, // 10933 |
| 18224 | { PseudoVWMACCSU_VX_M1_MASK, VWMACCSU_VX, 0x0, 0x0 }, // 10934 |
| 18225 | { PseudoVWMACCSU_VX_M2, VWMACCSU_VX, 0x1, 0x0 }, // 10935 |
| 18226 | { PseudoVWMACCSU_VX_M2_MASK, VWMACCSU_VX, 0x1, 0x0 }, // 10936 |
| 18227 | { PseudoVWMACCSU_VX_M4, VWMACCSU_VX, 0x2, 0x0 }, // 10937 |
| 18228 | { PseudoVWMACCSU_VX_M4_MASK, VWMACCSU_VX, 0x2, 0x0 }, // 10938 |
| 18229 | { PseudoVWMACCSU_VX_MF8, VWMACCSU_VX, 0x5, 0x0 }, // 10939 |
| 18230 | { PseudoVWMACCSU_VX_MF8_MASK, VWMACCSU_VX, 0x5, 0x0 }, // 10940 |
| 18231 | { PseudoVWMACCSU_VX_MF4, VWMACCSU_VX, 0x6, 0x0 }, // 10941 |
| 18232 | { PseudoVWMACCSU_VX_MF4_MASK, VWMACCSU_VX, 0x6, 0x0 }, // 10942 |
| 18233 | { PseudoVWMACCSU_VX_MF2, VWMACCSU_VX, 0x7, 0x0 }, // 10943 |
| 18234 | { PseudoVWMACCSU_VX_MF2_MASK, VWMACCSU_VX, 0x7, 0x0 }, // 10944 |
| 18235 | { PseudoVWMACCUS_VX_M1, VWMACCUS_VX, 0x0, 0x0 }, // 10945 |
| 18236 | { PseudoVWMACCUS_VX_M1_MASK, VWMACCUS_VX, 0x0, 0x0 }, // 10946 |
| 18237 | { PseudoVWMACCUS_VX_M2, VWMACCUS_VX, 0x1, 0x0 }, // 10947 |
| 18238 | { PseudoVWMACCUS_VX_M2_MASK, VWMACCUS_VX, 0x1, 0x0 }, // 10948 |
| 18239 | { PseudoVWMACCUS_VX_M4, VWMACCUS_VX, 0x2, 0x0 }, // 10949 |
| 18240 | { PseudoVWMACCUS_VX_M4_MASK, VWMACCUS_VX, 0x2, 0x0 }, // 10950 |
| 18241 | { PseudoVWMACCUS_VX_MF8, VWMACCUS_VX, 0x5, 0x0 }, // 10951 |
| 18242 | { PseudoVWMACCUS_VX_MF8_MASK, VWMACCUS_VX, 0x5, 0x0 }, // 10952 |
| 18243 | { PseudoVWMACCUS_VX_MF4, VWMACCUS_VX, 0x6, 0x0 }, // 10953 |
| 18244 | { PseudoVWMACCUS_VX_MF4_MASK, VWMACCUS_VX, 0x6, 0x0 }, // 10954 |
| 18245 | { PseudoVWMACCUS_VX_MF2, VWMACCUS_VX, 0x7, 0x0 }, // 10955 |
| 18246 | { PseudoVWMACCUS_VX_MF2_MASK, VWMACCUS_VX, 0x7, 0x0 }, // 10956 |
| 18247 | { PseudoVWMACCU_VV_M1, VWMACCU_VV, 0x0, 0x0 }, // 10957 |
| 18248 | { PseudoVWMACCU_VV_M1_MASK, VWMACCU_VV, 0x0, 0x0 }, // 10958 |
| 18249 | { PseudoVWMACCU_VV_M2, VWMACCU_VV, 0x1, 0x0 }, // 10959 |
| 18250 | { PseudoVWMACCU_VV_M2_MASK, VWMACCU_VV, 0x1, 0x0 }, // 10960 |
| 18251 | { PseudoVWMACCU_VV_M4, VWMACCU_VV, 0x2, 0x0 }, // 10961 |
| 18252 | { PseudoVWMACCU_VV_M4_MASK, VWMACCU_VV, 0x2, 0x0 }, // 10962 |
| 18253 | { PseudoVWMACCU_VV_MF8, VWMACCU_VV, 0x5, 0x0 }, // 10963 |
| 18254 | { PseudoVWMACCU_VV_MF8_MASK, VWMACCU_VV, 0x5, 0x0 }, // 10964 |
| 18255 | { PseudoVWMACCU_VV_MF4, VWMACCU_VV, 0x6, 0x0 }, // 10965 |
| 18256 | { PseudoVWMACCU_VV_MF4_MASK, VWMACCU_VV, 0x6, 0x0 }, // 10966 |
| 18257 | { PseudoVWMACCU_VV_MF2, VWMACCU_VV, 0x7, 0x0 }, // 10967 |
| 18258 | { PseudoVWMACCU_VV_MF2_MASK, VWMACCU_VV, 0x7, 0x0 }, // 10968 |
| 18259 | { PseudoVWMACCU_VX_M1, VWMACCU_VX, 0x0, 0x0 }, // 10969 |
| 18260 | { PseudoVWMACCU_VX_M1_MASK, VWMACCU_VX, 0x0, 0x0 }, // 10970 |
| 18261 | { PseudoVWMACCU_VX_M2, VWMACCU_VX, 0x1, 0x0 }, // 10971 |
| 18262 | { PseudoVWMACCU_VX_M2_MASK, VWMACCU_VX, 0x1, 0x0 }, // 10972 |
| 18263 | { PseudoVWMACCU_VX_M4, VWMACCU_VX, 0x2, 0x0 }, // 10973 |
| 18264 | { PseudoVWMACCU_VX_M4_MASK, VWMACCU_VX, 0x2, 0x0 }, // 10974 |
| 18265 | { PseudoVWMACCU_VX_MF8, VWMACCU_VX, 0x5, 0x0 }, // 10975 |
| 18266 | { PseudoVWMACCU_VX_MF8_MASK, VWMACCU_VX, 0x5, 0x0 }, // 10976 |
| 18267 | { PseudoVWMACCU_VX_MF4, VWMACCU_VX, 0x6, 0x0 }, // 10977 |
| 18268 | { PseudoVWMACCU_VX_MF4_MASK, VWMACCU_VX, 0x6, 0x0 }, // 10978 |
| 18269 | { PseudoVWMACCU_VX_MF2, VWMACCU_VX, 0x7, 0x0 }, // 10979 |
| 18270 | { PseudoVWMACCU_VX_MF2_MASK, VWMACCU_VX, 0x7, 0x0 }, // 10980 |
| 18271 | { PseudoVWMACC_VV_M1, VWMACC_VV, 0x0, 0x0 }, // 10981 |
| 18272 | { PseudoVWMACC_VV_M1_MASK, VWMACC_VV, 0x0, 0x0 }, // 10982 |
| 18273 | { PseudoVWMACC_VV_M2, VWMACC_VV, 0x1, 0x0 }, // 10983 |
| 18274 | { PseudoVWMACC_VV_M2_MASK, VWMACC_VV, 0x1, 0x0 }, // 10984 |
| 18275 | { PseudoVWMACC_VV_M4, VWMACC_VV, 0x2, 0x0 }, // 10985 |
| 18276 | { PseudoVWMACC_VV_M4_MASK, VWMACC_VV, 0x2, 0x0 }, // 10986 |
| 18277 | { PseudoVWMACC_VV_MF8, VWMACC_VV, 0x5, 0x0 }, // 10987 |
| 18278 | { PseudoVWMACC_VV_MF8_MASK, VWMACC_VV, 0x5, 0x0 }, // 10988 |
| 18279 | { PseudoVWMACC_VV_MF4, VWMACC_VV, 0x6, 0x0 }, // 10989 |
| 18280 | { PseudoVWMACC_VV_MF4_MASK, VWMACC_VV, 0x6, 0x0 }, // 10990 |
| 18281 | { PseudoVWMACC_VV_MF2, VWMACC_VV, 0x7, 0x0 }, // 10991 |
| 18282 | { PseudoVWMACC_VV_MF2_MASK, VWMACC_VV, 0x7, 0x0 }, // 10992 |
| 18283 | { PseudoVWMACC_VX_M1, VWMACC_VX, 0x0, 0x0 }, // 10993 |
| 18284 | { PseudoVWMACC_VX_M1_MASK, VWMACC_VX, 0x0, 0x0 }, // 10994 |
| 18285 | { PseudoVWMACC_VX_M2, VWMACC_VX, 0x1, 0x0 }, // 10995 |
| 18286 | { PseudoVWMACC_VX_M2_MASK, VWMACC_VX, 0x1, 0x0 }, // 10996 |
| 18287 | { PseudoVWMACC_VX_M4, VWMACC_VX, 0x2, 0x0 }, // 10997 |
| 18288 | { PseudoVWMACC_VX_M4_MASK, VWMACC_VX, 0x2, 0x0 }, // 10998 |
| 18289 | { PseudoVWMACC_VX_MF8, VWMACC_VX, 0x5, 0x0 }, // 10999 |
| 18290 | { PseudoVWMACC_VX_MF8_MASK, VWMACC_VX, 0x5, 0x0 }, // 11000 |
| 18291 | { PseudoVWMACC_VX_MF4, VWMACC_VX, 0x6, 0x0 }, // 11001 |
| 18292 | { PseudoVWMACC_VX_MF4_MASK, VWMACC_VX, 0x6, 0x0 }, // 11002 |
| 18293 | { PseudoVWMACC_VX_MF2, VWMACC_VX, 0x7, 0x0 }, // 11003 |
| 18294 | { PseudoVWMACC_VX_MF2_MASK, VWMACC_VX, 0x7, 0x0 }, // 11004 |
| 18295 | { PseudoVWMULSU_VV_M1, VWMULSU_VV, 0x0, 0x0 }, // 11005 |
| 18296 | { PseudoVWMULSU_VV_M1_MASK, VWMULSU_VV, 0x0, 0x0 }, // 11006 |
| 18297 | { PseudoVWMULSU_VV_M2, VWMULSU_VV, 0x1, 0x0 }, // 11007 |
| 18298 | { PseudoVWMULSU_VV_M2_MASK, VWMULSU_VV, 0x1, 0x0 }, // 11008 |
| 18299 | { PseudoVWMULSU_VV_M4, VWMULSU_VV, 0x2, 0x0 }, // 11009 |
| 18300 | { PseudoVWMULSU_VV_M4_MASK, VWMULSU_VV, 0x2, 0x0 }, // 11010 |
| 18301 | { PseudoVWMULSU_VV_MF8, VWMULSU_VV, 0x5, 0x0 }, // 11011 |
| 18302 | { PseudoVWMULSU_VV_MF8_MASK, VWMULSU_VV, 0x5, 0x0 }, // 11012 |
| 18303 | { PseudoVWMULSU_VV_MF4, VWMULSU_VV, 0x6, 0x0 }, // 11013 |
| 18304 | { PseudoVWMULSU_VV_MF4_MASK, VWMULSU_VV, 0x6, 0x0 }, // 11014 |
| 18305 | { PseudoVWMULSU_VV_MF2, VWMULSU_VV, 0x7, 0x0 }, // 11015 |
| 18306 | { PseudoVWMULSU_VV_MF2_MASK, VWMULSU_VV, 0x7, 0x0 }, // 11016 |
| 18307 | { PseudoVWMULSU_VX_M1, VWMULSU_VX, 0x0, 0x0 }, // 11017 |
| 18308 | { PseudoVWMULSU_VX_M1_MASK, VWMULSU_VX, 0x0, 0x0 }, // 11018 |
| 18309 | { PseudoVWMULSU_VX_M2, VWMULSU_VX, 0x1, 0x0 }, // 11019 |
| 18310 | { PseudoVWMULSU_VX_M2_MASK, VWMULSU_VX, 0x1, 0x0 }, // 11020 |
| 18311 | { PseudoVWMULSU_VX_M4, VWMULSU_VX, 0x2, 0x0 }, // 11021 |
| 18312 | { PseudoVWMULSU_VX_M4_MASK, VWMULSU_VX, 0x2, 0x0 }, // 11022 |
| 18313 | { PseudoVWMULSU_VX_MF8, VWMULSU_VX, 0x5, 0x0 }, // 11023 |
| 18314 | { PseudoVWMULSU_VX_MF8_MASK, VWMULSU_VX, 0x5, 0x0 }, // 11024 |
| 18315 | { PseudoVWMULSU_VX_MF4, VWMULSU_VX, 0x6, 0x0 }, // 11025 |
| 18316 | { PseudoVWMULSU_VX_MF4_MASK, VWMULSU_VX, 0x6, 0x0 }, // 11026 |
| 18317 | { PseudoVWMULSU_VX_MF2, VWMULSU_VX, 0x7, 0x0 }, // 11027 |
| 18318 | { PseudoVWMULSU_VX_MF2_MASK, VWMULSU_VX, 0x7, 0x0 }, // 11028 |
| 18319 | { PseudoVWMULU_VV_M1, VWMULU_VV, 0x0, 0x0 }, // 11029 |
| 18320 | { PseudoVWMULU_VV_M1_MASK, VWMULU_VV, 0x0, 0x0 }, // 11030 |
| 18321 | { PseudoVWMULU_VV_M2, VWMULU_VV, 0x1, 0x0 }, // 11031 |
| 18322 | { PseudoVWMULU_VV_M2_MASK, VWMULU_VV, 0x1, 0x0 }, // 11032 |
| 18323 | { PseudoVWMULU_VV_M4, VWMULU_VV, 0x2, 0x0 }, // 11033 |
| 18324 | { PseudoVWMULU_VV_M4_MASK, VWMULU_VV, 0x2, 0x0 }, // 11034 |
| 18325 | { PseudoVWMULU_VV_MF8, VWMULU_VV, 0x5, 0x0 }, // 11035 |
| 18326 | { PseudoVWMULU_VV_MF8_MASK, VWMULU_VV, 0x5, 0x0 }, // 11036 |
| 18327 | { PseudoVWMULU_VV_MF4, VWMULU_VV, 0x6, 0x0 }, // 11037 |
| 18328 | { PseudoVWMULU_VV_MF4_MASK, VWMULU_VV, 0x6, 0x0 }, // 11038 |
| 18329 | { PseudoVWMULU_VV_MF2, VWMULU_VV, 0x7, 0x0 }, // 11039 |
| 18330 | { PseudoVWMULU_VV_MF2_MASK, VWMULU_VV, 0x7, 0x0 }, // 11040 |
| 18331 | { PseudoVWMULU_VX_M1, VWMULU_VX, 0x0, 0x0 }, // 11041 |
| 18332 | { PseudoVWMULU_VX_M1_MASK, VWMULU_VX, 0x0, 0x0 }, // 11042 |
| 18333 | { PseudoVWMULU_VX_M2, VWMULU_VX, 0x1, 0x0 }, // 11043 |
| 18334 | { PseudoVWMULU_VX_M2_MASK, VWMULU_VX, 0x1, 0x0 }, // 11044 |
| 18335 | { PseudoVWMULU_VX_M4, VWMULU_VX, 0x2, 0x0 }, // 11045 |
| 18336 | { PseudoVWMULU_VX_M4_MASK, VWMULU_VX, 0x2, 0x0 }, // 11046 |
| 18337 | { PseudoVWMULU_VX_MF8, VWMULU_VX, 0x5, 0x0 }, // 11047 |
| 18338 | { PseudoVWMULU_VX_MF8_MASK, VWMULU_VX, 0x5, 0x0 }, // 11048 |
| 18339 | { PseudoVWMULU_VX_MF4, VWMULU_VX, 0x6, 0x0 }, // 11049 |
| 18340 | { PseudoVWMULU_VX_MF4_MASK, VWMULU_VX, 0x6, 0x0 }, // 11050 |
| 18341 | { PseudoVWMULU_VX_MF2, VWMULU_VX, 0x7, 0x0 }, // 11051 |
| 18342 | { PseudoVWMULU_VX_MF2_MASK, VWMULU_VX, 0x7, 0x0 }, // 11052 |
| 18343 | { PseudoVWMUL_VV_M1, VWMUL_VV, 0x0, 0x0 }, // 11053 |
| 18344 | { PseudoVWMUL_VV_M1_MASK, VWMUL_VV, 0x0, 0x0 }, // 11054 |
| 18345 | { PseudoVWMUL_VV_M2, VWMUL_VV, 0x1, 0x0 }, // 11055 |
| 18346 | { PseudoVWMUL_VV_M2_MASK, VWMUL_VV, 0x1, 0x0 }, // 11056 |
| 18347 | { PseudoVWMUL_VV_M4, VWMUL_VV, 0x2, 0x0 }, // 11057 |
| 18348 | { PseudoVWMUL_VV_M4_MASK, VWMUL_VV, 0x2, 0x0 }, // 11058 |
| 18349 | { PseudoVWMUL_VV_MF8, VWMUL_VV, 0x5, 0x0 }, // 11059 |
| 18350 | { PseudoVWMUL_VV_MF8_MASK, VWMUL_VV, 0x5, 0x0 }, // 11060 |
| 18351 | { PseudoVWMUL_VV_MF4, VWMUL_VV, 0x6, 0x0 }, // 11061 |
| 18352 | { PseudoVWMUL_VV_MF4_MASK, VWMUL_VV, 0x6, 0x0 }, // 11062 |
| 18353 | { PseudoVWMUL_VV_MF2, VWMUL_VV, 0x7, 0x0 }, // 11063 |
| 18354 | { PseudoVWMUL_VV_MF2_MASK, VWMUL_VV, 0x7, 0x0 }, // 11064 |
| 18355 | { PseudoVWMUL_VX_M1, VWMUL_VX, 0x0, 0x0 }, // 11065 |
| 18356 | { PseudoVWMUL_VX_M1_MASK, VWMUL_VX, 0x0, 0x0 }, // 11066 |
| 18357 | { PseudoVWMUL_VX_M2, VWMUL_VX, 0x1, 0x0 }, // 11067 |
| 18358 | { PseudoVWMUL_VX_M2_MASK, VWMUL_VX, 0x1, 0x0 }, // 11068 |
| 18359 | { PseudoVWMUL_VX_M4, VWMUL_VX, 0x2, 0x0 }, // 11069 |
| 18360 | { PseudoVWMUL_VX_M4_MASK, VWMUL_VX, 0x2, 0x0 }, // 11070 |
| 18361 | { PseudoVWMUL_VX_MF8, VWMUL_VX, 0x5, 0x0 }, // 11071 |
| 18362 | { PseudoVWMUL_VX_MF8_MASK, VWMUL_VX, 0x5, 0x0 }, // 11072 |
| 18363 | { PseudoVWMUL_VX_MF4, VWMUL_VX, 0x6, 0x0 }, // 11073 |
| 18364 | { PseudoVWMUL_VX_MF4_MASK, VWMUL_VX, 0x6, 0x0 }, // 11074 |
| 18365 | { PseudoVWMUL_VX_MF2, VWMUL_VX, 0x7, 0x0 }, // 11075 |
| 18366 | { PseudoVWMUL_VX_MF2_MASK, VWMUL_VX, 0x7, 0x0 }, // 11076 |
| 18367 | { PseudoVWREDSUMU_VS_M1_E8, VWREDSUMU_VS, 0x0, 0x8 }, // 11077 |
| 18368 | { PseudoVWREDSUMU_VS_M1_E8_MASK, VWREDSUMU_VS, 0x0, 0x8 }, // 11078 |
| 18369 | { PseudoVWREDSUMU_VS_M1_E16, VWREDSUMU_VS, 0x0, 0x10 }, // 11079 |
| 18370 | { PseudoVWREDSUMU_VS_M1_E16_MASK, VWREDSUMU_VS, 0x0, 0x10 }, // 11080 |
| 18371 | { PseudoVWREDSUMU_VS_M1_E32, VWREDSUMU_VS, 0x0, 0x20 }, // 11081 |
| 18372 | { PseudoVWREDSUMU_VS_M1_E32_MASK, VWREDSUMU_VS, 0x0, 0x20 }, // 11082 |
| 18373 | { PseudoVWREDSUMU_VS_M2_E8, VWREDSUMU_VS, 0x1, 0x8 }, // 11083 |
| 18374 | { PseudoVWREDSUMU_VS_M2_E8_MASK, VWREDSUMU_VS, 0x1, 0x8 }, // 11084 |
| 18375 | { PseudoVWREDSUMU_VS_M2_E16, VWREDSUMU_VS, 0x1, 0x10 }, // 11085 |
| 18376 | { PseudoVWREDSUMU_VS_M2_E16_MASK, VWREDSUMU_VS, 0x1, 0x10 }, // 11086 |
| 18377 | { PseudoVWREDSUMU_VS_M2_E32, VWREDSUMU_VS, 0x1, 0x20 }, // 11087 |
| 18378 | { PseudoVWREDSUMU_VS_M2_E32_MASK, VWREDSUMU_VS, 0x1, 0x20 }, // 11088 |
| 18379 | { PseudoVWREDSUMU_VS_M4_E8, VWREDSUMU_VS, 0x2, 0x8 }, // 11089 |
| 18380 | { PseudoVWREDSUMU_VS_M4_E8_MASK, VWREDSUMU_VS, 0x2, 0x8 }, // 11090 |
| 18381 | { PseudoVWREDSUMU_VS_M4_E16, VWREDSUMU_VS, 0x2, 0x10 }, // 11091 |
| 18382 | { PseudoVWREDSUMU_VS_M4_E16_MASK, VWREDSUMU_VS, 0x2, 0x10 }, // 11092 |
| 18383 | { PseudoVWREDSUMU_VS_M4_E32, VWREDSUMU_VS, 0x2, 0x20 }, // 11093 |
| 18384 | { PseudoVWREDSUMU_VS_M4_E32_MASK, VWREDSUMU_VS, 0x2, 0x20 }, // 11094 |
| 18385 | { PseudoVWREDSUMU_VS_M8_E8, VWREDSUMU_VS, 0x3, 0x8 }, // 11095 |
| 18386 | { PseudoVWREDSUMU_VS_M8_E8_MASK, VWREDSUMU_VS, 0x3, 0x8 }, // 11096 |
| 18387 | { PseudoVWREDSUMU_VS_M8_E16, VWREDSUMU_VS, 0x3, 0x10 }, // 11097 |
| 18388 | { PseudoVWREDSUMU_VS_M8_E16_MASK, VWREDSUMU_VS, 0x3, 0x10 }, // 11098 |
| 18389 | { PseudoVWREDSUMU_VS_M8_E32, VWREDSUMU_VS, 0x3, 0x20 }, // 11099 |
| 18390 | { PseudoVWREDSUMU_VS_M8_E32_MASK, VWREDSUMU_VS, 0x3, 0x20 }, // 11100 |
| 18391 | { PseudoVWREDSUMU_VS_MF8_E8, VWREDSUMU_VS, 0x5, 0x8 }, // 11101 |
| 18392 | { PseudoVWREDSUMU_VS_MF8_E8_MASK, VWREDSUMU_VS, 0x5, 0x8 }, // 11102 |
| 18393 | { PseudoVWREDSUMU_VS_MF4_E8, VWREDSUMU_VS, 0x6, 0x8 }, // 11103 |
| 18394 | { PseudoVWREDSUMU_VS_MF4_E8_MASK, VWREDSUMU_VS, 0x6, 0x8 }, // 11104 |
| 18395 | { PseudoVWREDSUMU_VS_MF4_E16, VWREDSUMU_VS, 0x6, 0x10 }, // 11105 |
| 18396 | { PseudoVWREDSUMU_VS_MF4_E16_MASK, VWREDSUMU_VS, 0x6, 0x10 }, // 11106 |
| 18397 | { PseudoVWREDSUMU_VS_MF2_E8, VWREDSUMU_VS, 0x7, 0x8 }, // 11107 |
| 18398 | { PseudoVWREDSUMU_VS_MF2_E8_MASK, VWREDSUMU_VS, 0x7, 0x8 }, // 11108 |
| 18399 | { PseudoVWREDSUMU_VS_MF2_E16, VWREDSUMU_VS, 0x7, 0x10 }, // 11109 |
| 18400 | { PseudoVWREDSUMU_VS_MF2_E16_MASK, VWREDSUMU_VS, 0x7, 0x10 }, // 11110 |
| 18401 | { PseudoVWREDSUMU_VS_MF2_E32, VWREDSUMU_VS, 0x7, 0x20 }, // 11111 |
| 18402 | { PseudoVWREDSUMU_VS_MF2_E32_MASK, VWREDSUMU_VS, 0x7, 0x20 }, // 11112 |
| 18403 | { PseudoVWREDSUM_VS_M1_E8, VWREDSUM_VS, 0x0, 0x8 }, // 11113 |
| 18404 | { PseudoVWREDSUM_VS_M1_E8_MASK, VWREDSUM_VS, 0x0, 0x8 }, // 11114 |
| 18405 | { PseudoVWREDSUM_VS_M1_E16, VWREDSUM_VS, 0x0, 0x10 }, // 11115 |
| 18406 | { PseudoVWREDSUM_VS_M1_E16_MASK, VWREDSUM_VS, 0x0, 0x10 }, // 11116 |
| 18407 | { PseudoVWREDSUM_VS_M1_E32, VWREDSUM_VS, 0x0, 0x20 }, // 11117 |
| 18408 | { PseudoVWREDSUM_VS_M1_E32_MASK, VWREDSUM_VS, 0x0, 0x20 }, // 11118 |
| 18409 | { PseudoVWREDSUM_VS_M2_E8, VWREDSUM_VS, 0x1, 0x8 }, // 11119 |
| 18410 | { PseudoVWREDSUM_VS_M2_E8_MASK, VWREDSUM_VS, 0x1, 0x8 }, // 11120 |
| 18411 | { PseudoVWREDSUM_VS_M2_E16, VWREDSUM_VS, 0x1, 0x10 }, // 11121 |
| 18412 | { PseudoVWREDSUM_VS_M2_E16_MASK, VWREDSUM_VS, 0x1, 0x10 }, // 11122 |
| 18413 | { PseudoVWREDSUM_VS_M2_E32, VWREDSUM_VS, 0x1, 0x20 }, // 11123 |
| 18414 | { PseudoVWREDSUM_VS_M2_E32_MASK, VWREDSUM_VS, 0x1, 0x20 }, // 11124 |
| 18415 | { PseudoVWREDSUM_VS_M4_E8, VWREDSUM_VS, 0x2, 0x8 }, // 11125 |
| 18416 | { PseudoVWREDSUM_VS_M4_E8_MASK, VWREDSUM_VS, 0x2, 0x8 }, // 11126 |
| 18417 | { PseudoVWREDSUM_VS_M4_E16, VWREDSUM_VS, 0x2, 0x10 }, // 11127 |
| 18418 | { PseudoVWREDSUM_VS_M4_E16_MASK, VWREDSUM_VS, 0x2, 0x10 }, // 11128 |
| 18419 | { PseudoVWREDSUM_VS_M4_E32, VWREDSUM_VS, 0x2, 0x20 }, // 11129 |
| 18420 | { PseudoVWREDSUM_VS_M4_E32_MASK, VWREDSUM_VS, 0x2, 0x20 }, // 11130 |
| 18421 | { PseudoVWREDSUM_VS_M8_E8, VWREDSUM_VS, 0x3, 0x8 }, // 11131 |
| 18422 | { PseudoVWREDSUM_VS_M8_E8_MASK, VWREDSUM_VS, 0x3, 0x8 }, // 11132 |
| 18423 | { PseudoVWREDSUM_VS_M8_E16, VWREDSUM_VS, 0x3, 0x10 }, // 11133 |
| 18424 | { PseudoVWREDSUM_VS_M8_E16_MASK, VWREDSUM_VS, 0x3, 0x10 }, // 11134 |
| 18425 | { PseudoVWREDSUM_VS_M8_E32, VWREDSUM_VS, 0x3, 0x20 }, // 11135 |
| 18426 | { PseudoVWREDSUM_VS_M8_E32_MASK, VWREDSUM_VS, 0x3, 0x20 }, // 11136 |
| 18427 | { PseudoVWREDSUM_VS_MF8_E8, VWREDSUM_VS, 0x5, 0x8 }, // 11137 |
| 18428 | { PseudoVWREDSUM_VS_MF8_E8_MASK, VWREDSUM_VS, 0x5, 0x8 }, // 11138 |
| 18429 | { PseudoVWREDSUM_VS_MF4_E8, VWREDSUM_VS, 0x6, 0x8 }, // 11139 |
| 18430 | { PseudoVWREDSUM_VS_MF4_E8_MASK, VWREDSUM_VS, 0x6, 0x8 }, // 11140 |
| 18431 | { PseudoVWREDSUM_VS_MF4_E16, VWREDSUM_VS, 0x6, 0x10 }, // 11141 |
| 18432 | { PseudoVWREDSUM_VS_MF4_E16_MASK, VWREDSUM_VS, 0x6, 0x10 }, // 11142 |
| 18433 | { PseudoVWREDSUM_VS_MF2_E8, VWREDSUM_VS, 0x7, 0x8 }, // 11143 |
| 18434 | { PseudoVWREDSUM_VS_MF2_E8_MASK, VWREDSUM_VS, 0x7, 0x8 }, // 11144 |
| 18435 | { PseudoVWREDSUM_VS_MF2_E16, VWREDSUM_VS, 0x7, 0x10 }, // 11145 |
| 18436 | { PseudoVWREDSUM_VS_MF2_E16_MASK, VWREDSUM_VS, 0x7, 0x10 }, // 11146 |
| 18437 | { PseudoVWREDSUM_VS_MF2_E32, VWREDSUM_VS, 0x7, 0x20 }, // 11147 |
| 18438 | { PseudoVWREDSUM_VS_MF2_E32_MASK, VWREDSUM_VS, 0x7, 0x20 }, // 11148 |
| 18439 | { PseudoVWSLL_VI_M1, VWSLL_VI, 0x0, 0x0 }, // 11149 |
| 18440 | { PseudoVWSLL_VI_M1_MASK, VWSLL_VI, 0x0, 0x0 }, // 11150 |
| 18441 | { PseudoVWSLL_VI_M2, VWSLL_VI, 0x1, 0x0 }, // 11151 |
| 18442 | { PseudoVWSLL_VI_M2_MASK, VWSLL_VI, 0x1, 0x0 }, // 11152 |
| 18443 | { PseudoVWSLL_VI_M4, VWSLL_VI, 0x2, 0x0 }, // 11153 |
| 18444 | { PseudoVWSLL_VI_M4_MASK, VWSLL_VI, 0x2, 0x0 }, // 11154 |
| 18445 | { PseudoVWSLL_VI_MF8, VWSLL_VI, 0x5, 0x0 }, // 11155 |
| 18446 | { PseudoVWSLL_VI_MF8_MASK, VWSLL_VI, 0x5, 0x0 }, // 11156 |
| 18447 | { PseudoVWSLL_VI_MF4, VWSLL_VI, 0x6, 0x0 }, // 11157 |
| 18448 | { PseudoVWSLL_VI_MF4_MASK, VWSLL_VI, 0x6, 0x0 }, // 11158 |
| 18449 | { PseudoVWSLL_VI_MF2, VWSLL_VI, 0x7, 0x0 }, // 11159 |
| 18450 | { PseudoVWSLL_VI_MF2_MASK, VWSLL_VI, 0x7, 0x0 }, // 11160 |
| 18451 | { PseudoVWSLL_VV_M1, VWSLL_VV, 0x0, 0x0 }, // 11161 |
| 18452 | { PseudoVWSLL_VV_M1_MASK, VWSLL_VV, 0x0, 0x0 }, // 11162 |
| 18453 | { PseudoVWSLL_VV_M2, VWSLL_VV, 0x1, 0x0 }, // 11163 |
| 18454 | { PseudoVWSLL_VV_M2_MASK, VWSLL_VV, 0x1, 0x0 }, // 11164 |
| 18455 | { PseudoVWSLL_VV_M4, VWSLL_VV, 0x2, 0x0 }, // 11165 |
| 18456 | { PseudoVWSLL_VV_M4_MASK, VWSLL_VV, 0x2, 0x0 }, // 11166 |
| 18457 | { PseudoVWSLL_VV_MF8, VWSLL_VV, 0x5, 0x0 }, // 11167 |
| 18458 | { PseudoVWSLL_VV_MF8_MASK, VWSLL_VV, 0x5, 0x0 }, // 11168 |
| 18459 | { PseudoVWSLL_VV_MF4, VWSLL_VV, 0x6, 0x0 }, // 11169 |
| 18460 | { PseudoVWSLL_VV_MF4_MASK, VWSLL_VV, 0x6, 0x0 }, // 11170 |
| 18461 | { PseudoVWSLL_VV_MF2, VWSLL_VV, 0x7, 0x0 }, // 11171 |
| 18462 | { PseudoVWSLL_VV_MF2_MASK, VWSLL_VV, 0x7, 0x0 }, // 11172 |
| 18463 | { PseudoVWSLL_VX_M1, VWSLL_VX, 0x0, 0x0 }, // 11173 |
| 18464 | { PseudoVWSLL_VX_M1_MASK, VWSLL_VX, 0x0, 0x0 }, // 11174 |
| 18465 | { PseudoVWSLL_VX_M2, VWSLL_VX, 0x1, 0x0 }, // 11175 |
| 18466 | { PseudoVWSLL_VX_M2_MASK, VWSLL_VX, 0x1, 0x0 }, // 11176 |
| 18467 | { PseudoVWSLL_VX_M4, VWSLL_VX, 0x2, 0x0 }, // 11177 |
| 18468 | { PseudoVWSLL_VX_M4_MASK, VWSLL_VX, 0x2, 0x0 }, // 11178 |
| 18469 | { PseudoVWSLL_VX_MF8, VWSLL_VX, 0x5, 0x0 }, // 11179 |
| 18470 | { PseudoVWSLL_VX_MF8_MASK, VWSLL_VX, 0x5, 0x0 }, // 11180 |
| 18471 | { PseudoVWSLL_VX_MF4, VWSLL_VX, 0x6, 0x0 }, // 11181 |
| 18472 | { PseudoVWSLL_VX_MF4_MASK, VWSLL_VX, 0x6, 0x0 }, // 11182 |
| 18473 | { PseudoVWSLL_VX_MF2, VWSLL_VX, 0x7, 0x0 }, // 11183 |
| 18474 | { PseudoVWSLL_VX_MF2_MASK, VWSLL_VX, 0x7, 0x0 }, // 11184 |
| 18475 | { PseudoVWSUBU_VV_M1, VWSUBU_VV, 0x0, 0x0 }, // 11185 |
| 18476 | { PseudoVWSUBU_VV_M1_MASK, VWSUBU_VV, 0x0, 0x0 }, // 11186 |
| 18477 | { PseudoVWSUBU_VV_M2, VWSUBU_VV, 0x1, 0x0 }, // 11187 |
| 18478 | { PseudoVWSUBU_VV_M2_MASK, VWSUBU_VV, 0x1, 0x0 }, // 11188 |
| 18479 | { PseudoVWSUBU_VV_M4, VWSUBU_VV, 0x2, 0x0 }, // 11189 |
| 18480 | { PseudoVWSUBU_VV_M4_MASK, VWSUBU_VV, 0x2, 0x0 }, // 11190 |
| 18481 | { PseudoVWSUBU_VV_MF8, VWSUBU_VV, 0x5, 0x0 }, // 11191 |
| 18482 | { PseudoVWSUBU_VV_MF8_MASK, VWSUBU_VV, 0x5, 0x0 }, // 11192 |
| 18483 | { PseudoVWSUBU_VV_MF4, VWSUBU_VV, 0x6, 0x0 }, // 11193 |
| 18484 | { PseudoVWSUBU_VV_MF4_MASK, VWSUBU_VV, 0x6, 0x0 }, // 11194 |
| 18485 | { PseudoVWSUBU_VV_MF2, VWSUBU_VV, 0x7, 0x0 }, // 11195 |
| 18486 | { PseudoVWSUBU_VV_MF2_MASK, VWSUBU_VV, 0x7, 0x0 }, // 11196 |
| 18487 | { PseudoVWSUBU_VX_M1, VWSUBU_VX, 0x0, 0x0 }, // 11197 |
| 18488 | { PseudoVWSUBU_VX_M1_MASK, VWSUBU_VX, 0x0, 0x0 }, // 11198 |
| 18489 | { PseudoVWSUBU_VX_M2, VWSUBU_VX, 0x1, 0x0 }, // 11199 |
| 18490 | { PseudoVWSUBU_VX_M2_MASK, VWSUBU_VX, 0x1, 0x0 }, // 11200 |
| 18491 | { PseudoVWSUBU_VX_M4, VWSUBU_VX, 0x2, 0x0 }, // 11201 |
| 18492 | { PseudoVWSUBU_VX_M4_MASK, VWSUBU_VX, 0x2, 0x0 }, // 11202 |
| 18493 | { PseudoVWSUBU_VX_MF8, VWSUBU_VX, 0x5, 0x0 }, // 11203 |
| 18494 | { PseudoVWSUBU_VX_MF8_MASK, VWSUBU_VX, 0x5, 0x0 }, // 11204 |
| 18495 | { PseudoVWSUBU_VX_MF4, VWSUBU_VX, 0x6, 0x0 }, // 11205 |
| 18496 | { PseudoVWSUBU_VX_MF4_MASK, VWSUBU_VX, 0x6, 0x0 }, // 11206 |
| 18497 | { PseudoVWSUBU_VX_MF2, VWSUBU_VX, 0x7, 0x0 }, // 11207 |
| 18498 | { PseudoVWSUBU_VX_MF2_MASK, VWSUBU_VX, 0x7, 0x0 }, // 11208 |
| 18499 | { PseudoVWSUBU_WV_M1, VWSUBU_WV, 0x0, 0x0 }, // 11209 |
| 18500 | { PseudoVWSUBU_WV_M1_MASK, VWSUBU_WV, 0x0, 0x0 }, // 11210 |
| 18501 | { PseudoVWSUBU_WV_M1_MASK_TIED, VWSUBU_WV, 0x0, 0x0 }, // 11211 |
| 18502 | { PseudoVWSUBU_WV_M1_TIED, VWSUBU_WV, 0x0, 0x0 }, // 11212 |
| 18503 | { PseudoVWSUBU_WV_M2, VWSUBU_WV, 0x1, 0x0 }, // 11213 |
| 18504 | { PseudoVWSUBU_WV_M2_MASK, VWSUBU_WV, 0x1, 0x0 }, // 11214 |
| 18505 | { PseudoVWSUBU_WV_M2_MASK_TIED, VWSUBU_WV, 0x1, 0x0 }, // 11215 |
| 18506 | { PseudoVWSUBU_WV_M2_TIED, VWSUBU_WV, 0x1, 0x0 }, // 11216 |
| 18507 | { PseudoVWSUBU_WV_M4, VWSUBU_WV, 0x2, 0x0 }, // 11217 |
| 18508 | { PseudoVWSUBU_WV_M4_MASK, VWSUBU_WV, 0x2, 0x0 }, // 11218 |
| 18509 | { PseudoVWSUBU_WV_M4_MASK_TIED, VWSUBU_WV, 0x2, 0x0 }, // 11219 |
| 18510 | { PseudoVWSUBU_WV_M4_TIED, VWSUBU_WV, 0x2, 0x0 }, // 11220 |
| 18511 | { PseudoVWSUBU_WV_MF8, VWSUBU_WV, 0x5, 0x0 }, // 11221 |
| 18512 | { PseudoVWSUBU_WV_MF8_MASK, VWSUBU_WV, 0x5, 0x0 }, // 11222 |
| 18513 | { PseudoVWSUBU_WV_MF8_MASK_TIED, VWSUBU_WV, 0x5, 0x0 }, // 11223 |
| 18514 | { PseudoVWSUBU_WV_MF8_TIED, VWSUBU_WV, 0x5, 0x0 }, // 11224 |
| 18515 | { PseudoVWSUBU_WV_MF4, VWSUBU_WV, 0x6, 0x0 }, // 11225 |
| 18516 | { PseudoVWSUBU_WV_MF4_MASK, VWSUBU_WV, 0x6, 0x0 }, // 11226 |
| 18517 | { PseudoVWSUBU_WV_MF4_MASK_TIED, VWSUBU_WV, 0x6, 0x0 }, // 11227 |
| 18518 | { PseudoVWSUBU_WV_MF4_TIED, VWSUBU_WV, 0x6, 0x0 }, // 11228 |
| 18519 | { PseudoVWSUBU_WV_MF2, VWSUBU_WV, 0x7, 0x0 }, // 11229 |
| 18520 | { PseudoVWSUBU_WV_MF2_MASK, VWSUBU_WV, 0x7, 0x0 }, // 11230 |
| 18521 | { PseudoVWSUBU_WV_MF2_MASK_TIED, VWSUBU_WV, 0x7, 0x0 }, // 11231 |
| 18522 | { PseudoVWSUBU_WV_MF2_TIED, VWSUBU_WV, 0x7, 0x0 }, // 11232 |
| 18523 | { PseudoVWSUBU_WX_M1, VWSUBU_WX, 0x0, 0x0 }, // 11233 |
| 18524 | { PseudoVWSUBU_WX_M1_MASK, VWSUBU_WX, 0x0, 0x0 }, // 11234 |
| 18525 | { PseudoVWSUBU_WX_M2, VWSUBU_WX, 0x1, 0x0 }, // 11235 |
| 18526 | { PseudoVWSUBU_WX_M2_MASK, VWSUBU_WX, 0x1, 0x0 }, // 11236 |
| 18527 | { PseudoVWSUBU_WX_M4, VWSUBU_WX, 0x2, 0x0 }, // 11237 |
| 18528 | { PseudoVWSUBU_WX_M4_MASK, VWSUBU_WX, 0x2, 0x0 }, // 11238 |
| 18529 | { PseudoVWSUBU_WX_MF8, VWSUBU_WX, 0x5, 0x0 }, // 11239 |
| 18530 | { PseudoVWSUBU_WX_MF8_MASK, VWSUBU_WX, 0x5, 0x0 }, // 11240 |
| 18531 | { PseudoVWSUBU_WX_MF4, VWSUBU_WX, 0x6, 0x0 }, // 11241 |
| 18532 | { PseudoVWSUBU_WX_MF4_MASK, VWSUBU_WX, 0x6, 0x0 }, // 11242 |
| 18533 | { PseudoVWSUBU_WX_MF2, VWSUBU_WX, 0x7, 0x0 }, // 11243 |
| 18534 | { PseudoVWSUBU_WX_MF2_MASK, VWSUBU_WX, 0x7, 0x0 }, // 11244 |
| 18535 | { PseudoVWSUB_VV_M1, VWSUB_VV, 0x0, 0x0 }, // 11245 |
| 18536 | { PseudoVWSUB_VV_M1_MASK, VWSUB_VV, 0x0, 0x0 }, // 11246 |
| 18537 | { PseudoVWSUB_VV_M2, VWSUB_VV, 0x1, 0x0 }, // 11247 |
| 18538 | { PseudoVWSUB_VV_M2_MASK, VWSUB_VV, 0x1, 0x0 }, // 11248 |
| 18539 | { PseudoVWSUB_VV_M4, VWSUB_VV, 0x2, 0x0 }, // 11249 |
| 18540 | { PseudoVWSUB_VV_M4_MASK, VWSUB_VV, 0x2, 0x0 }, // 11250 |
| 18541 | { PseudoVWSUB_VV_MF8, VWSUB_VV, 0x5, 0x0 }, // 11251 |
| 18542 | { PseudoVWSUB_VV_MF8_MASK, VWSUB_VV, 0x5, 0x0 }, // 11252 |
| 18543 | { PseudoVWSUB_VV_MF4, VWSUB_VV, 0x6, 0x0 }, // 11253 |
| 18544 | { PseudoVWSUB_VV_MF4_MASK, VWSUB_VV, 0x6, 0x0 }, // 11254 |
| 18545 | { PseudoVWSUB_VV_MF2, VWSUB_VV, 0x7, 0x0 }, // 11255 |
| 18546 | { PseudoVWSUB_VV_MF2_MASK, VWSUB_VV, 0x7, 0x0 }, // 11256 |
| 18547 | { PseudoVWSUB_VX_M1, VWSUB_VX, 0x0, 0x0 }, // 11257 |
| 18548 | { PseudoVWSUB_VX_M1_MASK, VWSUB_VX, 0x0, 0x0 }, // 11258 |
| 18549 | { PseudoVWSUB_VX_M2, VWSUB_VX, 0x1, 0x0 }, // 11259 |
| 18550 | { PseudoVWSUB_VX_M2_MASK, VWSUB_VX, 0x1, 0x0 }, // 11260 |
| 18551 | { PseudoVWSUB_VX_M4, VWSUB_VX, 0x2, 0x0 }, // 11261 |
| 18552 | { PseudoVWSUB_VX_M4_MASK, VWSUB_VX, 0x2, 0x0 }, // 11262 |
| 18553 | { PseudoVWSUB_VX_MF8, VWSUB_VX, 0x5, 0x0 }, // 11263 |
| 18554 | { PseudoVWSUB_VX_MF8_MASK, VWSUB_VX, 0x5, 0x0 }, // 11264 |
| 18555 | { PseudoVWSUB_VX_MF4, VWSUB_VX, 0x6, 0x0 }, // 11265 |
| 18556 | { PseudoVWSUB_VX_MF4_MASK, VWSUB_VX, 0x6, 0x0 }, // 11266 |
| 18557 | { PseudoVWSUB_VX_MF2, VWSUB_VX, 0x7, 0x0 }, // 11267 |
| 18558 | { PseudoVWSUB_VX_MF2_MASK, VWSUB_VX, 0x7, 0x0 }, // 11268 |
| 18559 | { PseudoVWSUB_WV_M1, VWSUB_WV, 0x0, 0x0 }, // 11269 |
| 18560 | { PseudoVWSUB_WV_M1_MASK, VWSUB_WV, 0x0, 0x0 }, // 11270 |
| 18561 | { PseudoVWSUB_WV_M1_MASK_TIED, VWSUB_WV, 0x0, 0x0 }, // 11271 |
| 18562 | { PseudoVWSUB_WV_M1_TIED, VWSUB_WV, 0x0, 0x0 }, // 11272 |
| 18563 | { PseudoVWSUB_WV_M2, VWSUB_WV, 0x1, 0x0 }, // 11273 |
| 18564 | { PseudoVWSUB_WV_M2_MASK, VWSUB_WV, 0x1, 0x0 }, // 11274 |
| 18565 | { PseudoVWSUB_WV_M2_MASK_TIED, VWSUB_WV, 0x1, 0x0 }, // 11275 |
| 18566 | { PseudoVWSUB_WV_M2_TIED, VWSUB_WV, 0x1, 0x0 }, // 11276 |
| 18567 | { PseudoVWSUB_WV_M4, VWSUB_WV, 0x2, 0x0 }, // 11277 |
| 18568 | { PseudoVWSUB_WV_M4_MASK, VWSUB_WV, 0x2, 0x0 }, // 11278 |
| 18569 | { PseudoVWSUB_WV_M4_MASK_TIED, VWSUB_WV, 0x2, 0x0 }, // 11279 |
| 18570 | { PseudoVWSUB_WV_M4_TIED, VWSUB_WV, 0x2, 0x0 }, // 11280 |
| 18571 | { PseudoVWSUB_WV_MF8, VWSUB_WV, 0x5, 0x0 }, // 11281 |
| 18572 | { PseudoVWSUB_WV_MF8_MASK, VWSUB_WV, 0x5, 0x0 }, // 11282 |
| 18573 | { PseudoVWSUB_WV_MF8_MASK_TIED, VWSUB_WV, 0x5, 0x0 }, // 11283 |
| 18574 | { PseudoVWSUB_WV_MF8_TIED, VWSUB_WV, 0x5, 0x0 }, // 11284 |
| 18575 | { PseudoVWSUB_WV_MF4, VWSUB_WV, 0x6, 0x0 }, // 11285 |
| 18576 | { PseudoVWSUB_WV_MF4_MASK, VWSUB_WV, 0x6, 0x0 }, // 11286 |
| 18577 | { PseudoVWSUB_WV_MF4_MASK_TIED, VWSUB_WV, 0x6, 0x0 }, // 11287 |
| 18578 | { PseudoVWSUB_WV_MF4_TIED, VWSUB_WV, 0x6, 0x0 }, // 11288 |
| 18579 | { PseudoVWSUB_WV_MF2, VWSUB_WV, 0x7, 0x0 }, // 11289 |
| 18580 | { PseudoVWSUB_WV_MF2_MASK, VWSUB_WV, 0x7, 0x0 }, // 11290 |
| 18581 | { PseudoVWSUB_WV_MF2_MASK_TIED, VWSUB_WV, 0x7, 0x0 }, // 11291 |
| 18582 | { PseudoVWSUB_WV_MF2_TIED, VWSUB_WV, 0x7, 0x0 }, // 11292 |
| 18583 | { PseudoVWSUB_WX_M1, VWSUB_WX, 0x0, 0x0 }, // 11293 |
| 18584 | { PseudoVWSUB_WX_M1_MASK, VWSUB_WX, 0x0, 0x0 }, // 11294 |
| 18585 | { PseudoVWSUB_WX_M2, VWSUB_WX, 0x1, 0x0 }, // 11295 |
| 18586 | { PseudoVWSUB_WX_M2_MASK, VWSUB_WX, 0x1, 0x0 }, // 11296 |
| 18587 | { PseudoVWSUB_WX_M4, VWSUB_WX, 0x2, 0x0 }, // 11297 |
| 18588 | { PseudoVWSUB_WX_M4_MASK, VWSUB_WX, 0x2, 0x0 }, // 11298 |
| 18589 | { PseudoVWSUB_WX_MF8, VWSUB_WX, 0x5, 0x0 }, // 11299 |
| 18590 | { PseudoVWSUB_WX_MF8_MASK, VWSUB_WX, 0x5, 0x0 }, // 11300 |
| 18591 | { PseudoVWSUB_WX_MF4, VWSUB_WX, 0x6, 0x0 }, // 11301 |
| 18592 | { PseudoVWSUB_WX_MF4_MASK, VWSUB_WX, 0x6, 0x0 }, // 11302 |
| 18593 | { PseudoVWSUB_WX_MF2, VWSUB_WX, 0x7, 0x0 }, // 11303 |
| 18594 | { PseudoVWSUB_WX_MF2_MASK, VWSUB_WX, 0x7, 0x0 }, // 11304 |
| 18595 | { PseudoVXOR_VI_M1, VXOR_VI, 0x0, 0x0 }, // 11305 |
| 18596 | { PseudoVXOR_VI_M1_MASK, VXOR_VI, 0x0, 0x0 }, // 11306 |
| 18597 | { PseudoVXOR_VI_M2, VXOR_VI, 0x1, 0x0 }, // 11307 |
| 18598 | { PseudoVXOR_VI_M2_MASK, VXOR_VI, 0x1, 0x0 }, // 11308 |
| 18599 | { PseudoVXOR_VI_M4, VXOR_VI, 0x2, 0x0 }, // 11309 |
| 18600 | { PseudoVXOR_VI_M4_MASK, VXOR_VI, 0x2, 0x0 }, // 11310 |
| 18601 | { PseudoVXOR_VI_M8, VXOR_VI, 0x3, 0x0 }, // 11311 |
| 18602 | { PseudoVXOR_VI_M8_MASK, VXOR_VI, 0x3, 0x0 }, // 11312 |
| 18603 | { PseudoVXOR_VI_MF8, VXOR_VI, 0x5, 0x0 }, // 11313 |
| 18604 | { PseudoVXOR_VI_MF8_MASK, VXOR_VI, 0x5, 0x0 }, // 11314 |
| 18605 | { PseudoVXOR_VI_MF4, VXOR_VI, 0x6, 0x0 }, // 11315 |
| 18606 | { PseudoVXOR_VI_MF4_MASK, VXOR_VI, 0x6, 0x0 }, // 11316 |
| 18607 | { PseudoVXOR_VI_MF2, VXOR_VI, 0x7, 0x0 }, // 11317 |
| 18608 | { PseudoVXOR_VI_MF2_MASK, VXOR_VI, 0x7, 0x0 }, // 11318 |
| 18609 | { PseudoVXOR_VV_M1, VXOR_VV, 0x0, 0x0 }, // 11319 |
| 18610 | { PseudoVXOR_VV_M1_MASK, VXOR_VV, 0x0, 0x0 }, // 11320 |
| 18611 | { PseudoVXOR_VV_M2, VXOR_VV, 0x1, 0x0 }, // 11321 |
| 18612 | { PseudoVXOR_VV_M2_MASK, VXOR_VV, 0x1, 0x0 }, // 11322 |
| 18613 | { PseudoVXOR_VV_M4, VXOR_VV, 0x2, 0x0 }, // 11323 |
| 18614 | { PseudoVXOR_VV_M4_MASK, VXOR_VV, 0x2, 0x0 }, // 11324 |
| 18615 | { PseudoVXOR_VV_M8, VXOR_VV, 0x3, 0x0 }, // 11325 |
| 18616 | { PseudoVXOR_VV_M8_MASK, VXOR_VV, 0x3, 0x0 }, // 11326 |
| 18617 | { PseudoVXOR_VV_MF8, VXOR_VV, 0x5, 0x0 }, // 11327 |
| 18618 | { PseudoVXOR_VV_MF8_MASK, VXOR_VV, 0x5, 0x0 }, // 11328 |
| 18619 | { PseudoVXOR_VV_MF4, VXOR_VV, 0x6, 0x0 }, // 11329 |
| 18620 | { PseudoVXOR_VV_MF4_MASK, VXOR_VV, 0x6, 0x0 }, // 11330 |
| 18621 | { PseudoVXOR_VV_MF2, VXOR_VV, 0x7, 0x0 }, // 11331 |
| 18622 | { PseudoVXOR_VV_MF2_MASK, VXOR_VV, 0x7, 0x0 }, // 11332 |
| 18623 | { PseudoVXOR_VX_M1, VXOR_VX, 0x0, 0x0 }, // 11333 |
| 18624 | { PseudoVXOR_VX_M1_MASK, VXOR_VX, 0x0, 0x0 }, // 11334 |
| 18625 | { PseudoVXOR_VX_M2, VXOR_VX, 0x1, 0x0 }, // 11335 |
| 18626 | { PseudoVXOR_VX_M2_MASK, VXOR_VX, 0x1, 0x0 }, // 11336 |
| 18627 | { PseudoVXOR_VX_M4, VXOR_VX, 0x2, 0x0 }, // 11337 |
| 18628 | { PseudoVXOR_VX_M4_MASK, VXOR_VX, 0x2, 0x0 }, // 11338 |
| 18629 | { PseudoVXOR_VX_M8, VXOR_VX, 0x3, 0x0 }, // 11339 |
| 18630 | { PseudoVXOR_VX_M8_MASK, VXOR_VX, 0x3, 0x0 }, // 11340 |
| 18631 | { PseudoVXOR_VX_MF8, VXOR_VX, 0x5, 0x0 }, // 11341 |
| 18632 | { PseudoVXOR_VX_MF8_MASK, VXOR_VX, 0x5, 0x0 }, // 11342 |
| 18633 | { PseudoVXOR_VX_MF4, VXOR_VX, 0x6, 0x0 }, // 11343 |
| 18634 | { PseudoVXOR_VX_MF4_MASK, VXOR_VX, 0x6, 0x0 }, // 11344 |
| 18635 | { PseudoVXOR_VX_MF2, VXOR_VX, 0x7, 0x0 }, // 11345 |
| 18636 | { PseudoVXOR_VX_MF2_MASK, VXOR_VX, 0x7, 0x0 }, // 11346 |
| 18637 | { PseudoVZEXT_VF2_M1, VZEXT_VF2, 0x0, 0x0 }, // 11347 |
| 18638 | { PseudoVZEXT_VF2_M1_MASK, VZEXT_VF2, 0x0, 0x0 }, // 11348 |
| 18639 | { PseudoVZEXT_VF2_M2, VZEXT_VF2, 0x1, 0x0 }, // 11349 |
| 18640 | { PseudoVZEXT_VF2_M2_MASK, VZEXT_VF2, 0x1, 0x0 }, // 11350 |
| 18641 | { PseudoVZEXT_VF2_M4, VZEXT_VF2, 0x2, 0x0 }, // 11351 |
| 18642 | { PseudoVZEXT_VF2_M4_MASK, VZEXT_VF2, 0x2, 0x0 }, // 11352 |
| 18643 | { PseudoVZEXT_VF2_M8, VZEXT_VF2, 0x3, 0x0 }, // 11353 |
| 18644 | { PseudoVZEXT_VF2_M8_MASK, VZEXT_VF2, 0x3, 0x0 }, // 11354 |
| 18645 | { PseudoVZEXT_VF2_MF4, VZEXT_VF2, 0x6, 0x0 }, // 11355 |
| 18646 | { PseudoVZEXT_VF2_MF4_MASK, VZEXT_VF2, 0x6, 0x0 }, // 11356 |
| 18647 | { PseudoVZEXT_VF2_MF2, VZEXT_VF2, 0x7, 0x0 }, // 11357 |
| 18648 | { PseudoVZEXT_VF2_MF2_MASK, VZEXT_VF2, 0x7, 0x0 }, // 11358 |
| 18649 | { PseudoVZEXT_VF4_M1, VZEXT_VF4, 0x0, 0x0 }, // 11359 |
| 18650 | { PseudoVZEXT_VF4_M1_MASK, VZEXT_VF4, 0x0, 0x0 }, // 11360 |
| 18651 | { PseudoVZEXT_VF4_M2, VZEXT_VF4, 0x1, 0x0 }, // 11361 |
| 18652 | { PseudoVZEXT_VF4_M2_MASK, VZEXT_VF4, 0x1, 0x0 }, // 11362 |
| 18653 | { PseudoVZEXT_VF4_M4, VZEXT_VF4, 0x2, 0x0 }, // 11363 |
| 18654 | { PseudoVZEXT_VF4_M4_MASK, VZEXT_VF4, 0x2, 0x0 }, // 11364 |
| 18655 | { PseudoVZEXT_VF4_M8, VZEXT_VF4, 0x3, 0x0 }, // 11365 |
| 18656 | { PseudoVZEXT_VF4_M8_MASK, VZEXT_VF4, 0x3, 0x0 }, // 11366 |
| 18657 | { PseudoVZEXT_VF4_MF2, VZEXT_VF4, 0x7, 0x0 }, // 11367 |
| 18658 | { PseudoVZEXT_VF4_MF2_MASK, VZEXT_VF4, 0x7, 0x0 }, // 11368 |
| 18659 | { PseudoVZEXT_VF8_M1, VZEXT_VF8, 0x0, 0x0 }, // 11369 |
| 18660 | { PseudoVZEXT_VF8_M1_MASK, VZEXT_VF8, 0x0, 0x0 }, // 11370 |
| 18661 | { PseudoVZEXT_VF8_M2, VZEXT_VF8, 0x1, 0x0 }, // 11371 |
| 18662 | { PseudoVZEXT_VF8_M2_MASK, VZEXT_VF8, 0x1, 0x0 }, // 11372 |
| 18663 | { PseudoVZEXT_VF8_M4, VZEXT_VF8, 0x2, 0x0 }, // 11373 |
| 18664 | { PseudoVZEXT_VF8_M4_MASK, VZEXT_VF8, 0x2, 0x0 }, // 11374 |
| 18665 | { PseudoVZEXT_VF8_M8, VZEXT_VF8, 0x3, 0x0 }, // 11375 |
| 18666 | { PseudoVZEXT_VF8_M8_MASK, VZEXT_VF8, 0x3, 0x0 }, // 11376 |
| 18667 | }; |
| 18668 | |
| 18669 | const PseudoInfo *getBaseInfo(unsigned BaseInstr, uint8_t VLMul, uint8_t SEW) { |
| 18670 | if ((BaseInstr < THVdotVMAQASU_VV) || |
| 18671 | (BaseInstr > VZEXT_VF8)) |
| 18672 | return nullptr; |
| 18673 | |
| 18674 | struct KeyType { |
| 18675 | unsigned BaseInstr; |
| 18676 | uint8_t VLMul; |
| 18677 | uint8_t SEW; |
| 18678 | }; |
| 18679 | KeyType Key = {BaseInstr, VLMul, SEW}; |
| 18680 | struct Comp { |
| 18681 | bool operator()(const PseudoInfo &LHS, const KeyType &RHS) const { |
| 18682 | if (LHS.BaseInstr < RHS.BaseInstr) |
| 18683 | return true; |
| 18684 | if (LHS.BaseInstr > RHS.BaseInstr) |
| 18685 | return false; |
| 18686 | if (LHS.VLMul < RHS.VLMul) |
| 18687 | return true; |
| 18688 | if (LHS.VLMul > RHS.VLMul) |
| 18689 | return false; |
| 18690 | if (LHS.SEW < RHS.SEW) |
| 18691 | return true; |
| 18692 | if (LHS.SEW > RHS.SEW) |
| 18693 | return false; |
| 18694 | return false; |
| 18695 | } |
| 18696 | }; |
| 18697 | auto Table = ArrayRef(RISCVVInversePseudosTable); |
| 18698 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 18699 | if (Idx == Table.end() || |
| 18700 | Key.BaseInstr != Idx->BaseInstr || |
| 18701 | Key.VLMul != Idx->VLMul || |
| 18702 | Key.SEW != Idx->SEW) |
| 18703 | return nullptr; |
| 18704 | |
| 18705 | return &*Idx; |
| 18706 | } |
| 18707 | #endif |
| 18708 | |
| 18709 | #ifdef GET_RISCVVLETable_DECL |
| 18710 | const VLEPseudo *getVLEPseudo(uint8_t Masked, uint8_t Strided, uint8_t FF, uint8_t Log2SEW, uint8_t LMUL); |
| 18711 | #endif |
| 18712 | |
| 18713 | #ifdef GET_RISCVVLETable_IMPL |
| 18714 | constexpr VLEPseudo RISCVVLETable[] = { |
| 18715 | { 0x0, 0x0, 0x0, 0x0, 0x0, PseudoVLM_V_B8 }, // 0 |
| 18716 | { 0x0, 0x0, 0x0, 0x0, 0x1, PseudoVLM_V_B16 }, // 1 |
| 18717 | { 0x0, 0x0, 0x0, 0x0, 0x2, PseudoVLM_V_B32 }, // 2 |
| 18718 | { 0x0, 0x0, 0x0, 0x0, 0x3, PseudoVLM_V_B64 }, // 3 |
| 18719 | { 0x0, 0x0, 0x0, 0x0, 0x5, PseudoVLM_V_B1 }, // 4 |
| 18720 | { 0x0, 0x0, 0x0, 0x0, 0x6, PseudoVLM_V_B2 }, // 5 |
| 18721 | { 0x0, 0x0, 0x0, 0x0, 0x7, PseudoVLM_V_B4 }, // 6 |
| 18722 | { 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLE8_V_M1 }, // 7 |
| 18723 | { 0x0, 0x0, 0x0, 0x3, 0x1, PseudoVLE8_V_M2 }, // 8 |
| 18724 | { 0x0, 0x0, 0x0, 0x3, 0x2, PseudoVLE8_V_M4 }, // 9 |
| 18725 | { 0x0, 0x0, 0x0, 0x3, 0x3, PseudoVLE8_V_M8 }, // 10 |
| 18726 | { 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLE8_V_MF8 }, // 11 |
| 18727 | { 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLE8_V_MF4 }, // 12 |
| 18728 | { 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLE8_V_MF2 }, // 13 |
| 18729 | { 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLE16_V_M1 }, // 14 |
| 18730 | { 0x0, 0x0, 0x0, 0x4, 0x1, PseudoVLE16_V_M2 }, // 15 |
| 18731 | { 0x0, 0x0, 0x0, 0x4, 0x2, PseudoVLE16_V_M4 }, // 16 |
| 18732 | { 0x0, 0x0, 0x0, 0x4, 0x3, PseudoVLE16_V_M8 }, // 17 |
| 18733 | { 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLE16_V_MF4 }, // 18 |
| 18734 | { 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLE16_V_MF2 }, // 19 |
| 18735 | { 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLE32_V_M1 }, // 20 |
| 18736 | { 0x0, 0x0, 0x0, 0x5, 0x1, PseudoVLE32_V_M2 }, // 21 |
| 18737 | { 0x0, 0x0, 0x0, 0x5, 0x2, PseudoVLE32_V_M4 }, // 22 |
| 18738 | { 0x0, 0x0, 0x0, 0x5, 0x3, PseudoVLE32_V_M8 }, // 23 |
| 18739 | { 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLE32_V_MF2 }, // 24 |
| 18740 | { 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLE64_V_M1 }, // 25 |
| 18741 | { 0x0, 0x0, 0x0, 0x6, 0x1, PseudoVLE64_V_M2 }, // 26 |
| 18742 | { 0x0, 0x0, 0x0, 0x6, 0x2, PseudoVLE64_V_M4 }, // 27 |
| 18743 | { 0x0, 0x0, 0x0, 0x6, 0x3, PseudoVLE64_V_M8 }, // 28 |
| 18744 | { 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLE8FF_V_M1 }, // 29 |
| 18745 | { 0x0, 0x0, 0x1, 0x3, 0x1, PseudoVLE8FF_V_M2 }, // 30 |
| 18746 | { 0x0, 0x0, 0x1, 0x3, 0x2, PseudoVLE8FF_V_M4 }, // 31 |
| 18747 | { 0x0, 0x0, 0x1, 0x3, 0x3, PseudoVLE8FF_V_M8 }, // 32 |
| 18748 | { 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLE8FF_V_MF8 }, // 33 |
| 18749 | { 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLE8FF_V_MF4 }, // 34 |
| 18750 | { 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLE8FF_V_MF2 }, // 35 |
| 18751 | { 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLE16FF_V_M1 }, // 36 |
| 18752 | { 0x0, 0x0, 0x1, 0x4, 0x1, PseudoVLE16FF_V_M2 }, // 37 |
| 18753 | { 0x0, 0x0, 0x1, 0x4, 0x2, PseudoVLE16FF_V_M4 }, // 38 |
| 18754 | { 0x0, 0x0, 0x1, 0x4, 0x3, PseudoVLE16FF_V_M8 }, // 39 |
| 18755 | { 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLE16FF_V_MF4 }, // 40 |
| 18756 | { 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLE16FF_V_MF2 }, // 41 |
| 18757 | { 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLE32FF_V_M1 }, // 42 |
| 18758 | { 0x0, 0x0, 0x1, 0x5, 0x1, PseudoVLE32FF_V_M2 }, // 43 |
| 18759 | { 0x0, 0x0, 0x1, 0x5, 0x2, PseudoVLE32FF_V_M4 }, // 44 |
| 18760 | { 0x0, 0x0, 0x1, 0x5, 0x3, PseudoVLE32FF_V_M8 }, // 45 |
| 18761 | { 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLE32FF_V_MF2 }, // 46 |
| 18762 | { 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLE64FF_V_M1 }, // 47 |
| 18763 | { 0x0, 0x0, 0x1, 0x6, 0x1, PseudoVLE64FF_V_M2 }, // 48 |
| 18764 | { 0x0, 0x0, 0x1, 0x6, 0x2, PseudoVLE64FF_V_M4 }, // 49 |
| 18765 | { 0x0, 0x0, 0x1, 0x6, 0x3, PseudoVLE64FF_V_M8 }, // 50 |
| 18766 | { 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSE8_V_M1 }, // 51 |
| 18767 | { 0x0, 0x1, 0x0, 0x3, 0x1, PseudoVLSE8_V_M2 }, // 52 |
| 18768 | { 0x0, 0x1, 0x0, 0x3, 0x2, PseudoVLSE8_V_M4 }, // 53 |
| 18769 | { 0x0, 0x1, 0x0, 0x3, 0x3, PseudoVLSE8_V_M8 }, // 54 |
| 18770 | { 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSE8_V_MF8 }, // 55 |
| 18771 | { 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSE8_V_MF4 }, // 56 |
| 18772 | { 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSE8_V_MF2 }, // 57 |
| 18773 | { 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSE16_V_M1 }, // 58 |
| 18774 | { 0x0, 0x1, 0x0, 0x4, 0x1, PseudoVLSE16_V_M2 }, // 59 |
| 18775 | { 0x0, 0x1, 0x0, 0x4, 0x2, PseudoVLSE16_V_M4 }, // 60 |
| 18776 | { 0x0, 0x1, 0x0, 0x4, 0x3, PseudoVLSE16_V_M8 }, // 61 |
| 18777 | { 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSE16_V_MF4 }, // 62 |
| 18778 | { 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSE16_V_MF2 }, // 63 |
| 18779 | { 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSE32_V_M1 }, // 64 |
| 18780 | { 0x0, 0x1, 0x0, 0x5, 0x1, PseudoVLSE32_V_M2 }, // 65 |
| 18781 | { 0x0, 0x1, 0x0, 0x5, 0x2, PseudoVLSE32_V_M4 }, // 66 |
| 18782 | { 0x0, 0x1, 0x0, 0x5, 0x3, PseudoVLSE32_V_M8 }, // 67 |
| 18783 | { 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSE32_V_MF2 }, // 68 |
| 18784 | { 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSE64_V_M1 }, // 69 |
| 18785 | { 0x0, 0x1, 0x0, 0x6, 0x1, PseudoVLSE64_V_M2 }, // 70 |
| 18786 | { 0x0, 0x1, 0x0, 0x6, 0x2, PseudoVLSE64_V_M4 }, // 71 |
| 18787 | { 0x0, 0x1, 0x0, 0x6, 0x3, PseudoVLSE64_V_M8 }, // 72 |
| 18788 | { 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLE8_V_M1_MASK }, // 73 |
| 18789 | { 0x1, 0x0, 0x0, 0x3, 0x1, PseudoVLE8_V_M2_MASK }, // 74 |
| 18790 | { 0x1, 0x0, 0x0, 0x3, 0x2, PseudoVLE8_V_M4_MASK }, // 75 |
| 18791 | { 0x1, 0x0, 0x0, 0x3, 0x3, PseudoVLE8_V_M8_MASK }, // 76 |
| 18792 | { 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLE8_V_MF8_MASK }, // 77 |
| 18793 | { 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLE8_V_MF4_MASK }, // 78 |
| 18794 | { 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLE8_V_MF2_MASK }, // 79 |
| 18795 | { 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLE16_V_M1_MASK }, // 80 |
| 18796 | { 0x1, 0x0, 0x0, 0x4, 0x1, PseudoVLE16_V_M2_MASK }, // 81 |
| 18797 | { 0x1, 0x0, 0x0, 0x4, 0x2, PseudoVLE16_V_M4_MASK }, // 82 |
| 18798 | { 0x1, 0x0, 0x0, 0x4, 0x3, PseudoVLE16_V_M8_MASK }, // 83 |
| 18799 | { 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLE16_V_MF4_MASK }, // 84 |
| 18800 | { 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLE16_V_MF2_MASK }, // 85 |
| 18801 | { 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLE32_V_M1_MASK }, // 86 |
| 18802 | { 0x1, 0x0, 0x0, 0x5, 0x1, PseudoVLE32_V_M2_MASK }, // 87 |
| 18803 | { 0x1, 0x0, 0x0, 0x5, 0x2, PseudoVLE32_V_M4_MASK }, // 88 |
| 18804 | { 0x1, 0x0, 0x0, 0x5, 0x3, PseudoVLE32_V_M8_MASK }, // 89 |
| 18805 | { 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLE32_V_MF2_MASK }, // 90 |
| 18806 | { 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLE64_V_M1_MASK }, // 91 |
| 18807 | { 0x1, 0x0, 0x0, 0x6, 0x1, PseudoVLE64_V_M2_MASK }, // 92 |
| 18808 | { 0x1, 0x0, 0x0, 0x6, 0x2, PseudoVLE64_V_M4_MASK }, // 93 |
| 18809 | { 0x1, 0x0, 0x0, 0x6, 0x3, PseudoVLE64_V_M8_MASK }, // 94 |
| 18810 | { 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLE8FF_V_M1_MASK }, // 95 |
| 18811 | { 0x1, 0x0, 0x1, 0x3, 0x1, PseudoVLE8FF_V_M2_MASK }, // 96 |
| 18812 | { 0x1, 0x0, 0x1, 0x3, 0x2, PseudoVLE8FF_V_M4_MASK }, // 97 |
| 18813 | { 0x1, 0x0, 0x1, 0x3, 0x3, PseudoVLE8FF_V_M8_MASK }, // 98 |
| 18814 | { 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLE8FF_V_MF8_MASK }, // 99 |
| 18815 | { 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLE8FF_V_MF4_MASK }, // 100 |
| 18816 | { 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLE8FF_V_MF2_MASK }, // 101 |
| 18817 | { 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLE16FF_V_M1_MASK }, // 102 |
| 18818 | { 0x1, 0x0, 0x1, 0x4, 0x1, PseudoVLE16FF_V_M2_MASK }, // 103 |
| 18819 | { 0x1, 0x0, 0x1, 0x4, 0x2, PseudoVLE16FF_V_M4_MASK }, // 104 |
| 18820 | { 0x1, 0x0, 0x1, 0x4, 0x3, PseudoVLE16FF_V_M8_MASK }, // 105 |
| 18821 | { 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLE16FF_V_MF4_MASK }, // 106 |
| 18822 | { 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLE16FF_V_MF2_MASK }, // 107 |
| 18823 | { 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLE32FF_V_M1_MASK }, // 108 |
| 18824 | { 0x1, 0x0, 0x1, 0x5, 0x1, PseudoVLE32FF_V_M2_MASK }, // 109 |
| 18825 | { 0x1, 0x0, 0x1, 0x5, 0x2, PseudoVLE32FF_V_M4_MASK }, // 110 |
| 18826 | { 0x1, 0x0, 0x1, 0x5, 0x3, PseudoVLE32FF_V_M8_MASK }, // 111 |
| 18827 | { 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLE32FF_V_MF2_MASK }, // 112 |
| 18828 | { 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLE64FF_V_M1_MASK }, // 113 |
| 18829 | { 0x1, 0x0, 0x1, 0x6, 0x1, PseudoVLE64FF_V_M2_MASK }, // 114 |
| 18830 | { 0x1, 0x0, 0x1, 0x6, 0x2, PseudoVLE64FF_V_M4_MASK }, // 115 |
| 18831 | { 0x1, 0x0, 0x1, 0x6, 0x3, PseudoVLE64FF_V_M8_MASK }, // 116 |
| 18832 | { 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSE8_V_M1_MASK }, // 117 |
| 18833 | { 0x1, 0x1, 0x0, 0x3, 0x1, PseudoVLSE8_V_M2_MASK }, // 118 |
| 18834 | { 0x1, 0x1, 0x0, 0x3, 0x2, PseudoVLSE8_V_M4_MASK }, // 119 |
| 18835 | { 0x1, 0x1, 0x0, 0x3, 0x3, PseudoVLSE8_V_M8_MASK }, // 120 |
| 18836 | { 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSE8_V_MF8_MASK }, // 121 |
| 18837 | { 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSE8_V_MF4_MASK }, // 122 |
| 18838 | { 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSE8_V_MF2_MASK }, // 123 |
| 18839 | { 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSE16_V_M1_MASK }, // 124 |
| 18840 | { 0x1, 0x1, 0x0, 0x4, 0x1, PseudoVLSE16_V_M2_MASK }, // 125 |
| 18841 | { 0x1, 0x1, 0x0, 0x4, 0x2, PseudoVLSE16_V_M4_MASK }, // 126 |
| 18842 | { 0x1, 0x1, 0x0, 0x4, 0x3, PseudoVLSE16_V_M8_MASK }, // 127 |
| 18843 | { 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSE16_V_MF4_MASK }, // 128 |
| 18844 | { 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSE16_V_MF2_MASK }, // 129 |
| 18845 | { 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSE32_V_M1_MASK }, // 130 |
| 18846 | { 0x1, 0x1, 0x0, 0x5, 0x1, PseudoVLSE32_V_M2_MASK }, // 131 |
| 18847 | { 0x1, 0x1, 0x0, 0x5, 0x2, PseudoVLSE32_V_M4_MASK }, // 132 |
| 18848 | { 0x1, 0x1, 0x0, 0x5, 0x3, PseudoVLSE32_V_M8_MASK }, // 133 |
| 18849 | { 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSE32_V_MF2_MASK }, // 134 |
| 18850 | { 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSE64_V_M1_MASK }, // 135 |
| 18851 | { 0x1, 0x1, 0x0, 0x6, 0x1, PseudoVLSE64_V_M2_MASK }, // 136 |
| 18852 | { 0x1, 0x1, 0x0, 0x6, 0x2, PseudoVLSE64_V_M4_MASK }, // 137 |
| 18853 | { 0x1, 0x1, 0x0, 0x6, 0x3, PseudoVLSE64_V_M8_MASK }, // 138 |
| 18854 | }; |
| 18855 | |
| 18856 | const VLEPseudo *getVLEPseudo(uint8_t Masked, uint8_t Strided, uint8_t FF, uint8_t Log2SEW, uint8_t LMUL) { |
| 18857 | struct KeyType { |
| 18858 | uint8_t Masked; |
| 18859 | uint8_t Strided; |
| 18860 | uint8_t FF; |
| 18861 | uint8_t Log2SEW; |
| 18862 | uint8_t LMUL; |
| 18863 | }; |
| 18864 | KeyType Key = {Masked, Strided, FF, Log2SEW, LMUL}; |
| 18865 | struct Comp { |
| 18866 | bool operator()(const VLEPseudo &LHS, const KeyType &RHS) const { |
| 18867 | if (LHS.Masked < RHS.Masked) |
| 18868 | return true; |
| 18869 | if (LHS.Masked > RHS.Masked) |
| 18870 | return false; |
| 18871 | if (LHS.Strided < RHS.Strided) |
| 18872 | return true; |
| 18873 | if (LHS.Strided > RHS.Strided) |
| 18874 | return false; |
| 18875 | if (LHS.FF < RHS.FF) |
| 18876 | return true; |
| 18877 | if (LHS.FF > RHS.FF) |
| 18878 | return false; |
| 18879 | if (LHS.Log2SEW < RHS.Log2SEW) |
| 18880 | return true; |
| 18881 | if (LHS.Log2SEW > RHS.Log2SEW) |
| 18882 | return false; |
| 18883 | if (LHS.LMUL < RHS.LMUL) |
| 18884 | return true; |
| 18885 | if (LHS.LMUL > RHS.LMUL) |
| 18886 | return false; |
| 18887 | return false; |
| 18888 | } |
| 18889 | }; |
| 18890 | auto Table = ArrayRef(RISCVVLETable); |
| 18891 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 18892 | if (Idx == Table.end() || |
| 18893 | Key.Masked != Idx->Masked || |
| 18894 | Key.Strided != Idx->Strided || |
| 18895 | Key.FF != Idx->FF || |
| 18896 | Key.Log2SEW != Idx->Log2SEW || |
| 18897 | Key.LMUL != Idx->LMUL) |
| 18898 | return nullptr; |
| 18899 | |
| 18900 | return &*Idx; |
| 18901 | } |
| 18902 | #endif |
| 18903 | |
| 18904 | #ifdef GET_RISCVVLSEGTable_DECL |
| 18905 | const VLSEGPseudo *getVLSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Strided, uint8_t FF, uint8_t Log2SEW, uint8_t LMUL); |
| 18906 | #endif |
| 18907 | |
| 18908 | #ifdef GET_RISCVVLSEGTable_IMPL |
| 18909 | constexpr VLSEGPseudo RISCVVLSEGTable[] = { |
| 18910 | { 0x2, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG2E8_V_M1 }, // 0 |
| 18911 | { 0x2, 0x0, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG2E8_V_M2 }, // 1 |
| 18912 | { 0x2, 0x0, 0x0, 0x0, 0x3, 0x2, PseudoVLSEG2E8_V_M4 }, // 2 |
| 18913 | { 0x2, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG2E8_V_MF8 }, // 3 |
| 18914 | { 0x2, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG2E8_V_MF4 }, // 4 |
| 18915 | { 0x2, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG2E8_V_MF2 }, // 5 |
| 18916 | { 0x2, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG2E16_V_M1 }, // 6 |
| 18917 | { 0x2, 0x0, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG2E16_V_M2 }, // 7 |
| 18918 | { 0x2, 0x0, 0x0, 0x0, 0x4, 0x2, PseudoVLSEG2E16_V_M4 }, // 8 |
| 18919 | { 0x2, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG2E16_V_MF4 }, // 9 |
| 18920 | { 0x2, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG2E16_V_MF2 }, // 10 |
| 18921 | { 0x2, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG2E32_V_M1 }, // 11 |
| 18922 | { 0x2, 0x0, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG2E32_V_M2 }, // 12 |
| 18923 | { 0x2, 0x0, 0x0, 0x0, 0x5, 0x2, PseudoVLSEG2E32_V_M4 }, // 13 |
| 18924 | { 0x2, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG2E32_V_MF2 }, // 14 |
| 18925 | { 0x2, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG2E64_V_M1 }, // 15 |
| 18926 | { 0x2, 0x0, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG2E64_V_M2 }, // 16 |
| 18927 | { 0x2, 0x0, 0x0, 0x0, 0x6, 0x2, PseudoVLSEG2E64_V_M4 }, // 17 |
| 18928 | { 0x2, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG2E8FF_V_M1 }, // 18 |
| 18929 | { 0x2, 0x0, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG2E8FF_V_M2 }, // 19 |
| 18930 | { 0x2, 0x0, 0x0, 0x1, 0x3, 0x2, PseudoVLSEG2E8FF_V_M4 }, // 20 |
| 18931 | { 0x2, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG2E8FF_V_MF8 }, // 21 |
| 18932 | { 0x2, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG2E8FF_V_MF4 }, // 22 |
| 18933 | { 0x2, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG2E8FF_V_MF2 }, // 23 |
| 18934 | { 0x2, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG2E16FF_V_M1 }, // 24 |
| 18935 | { 0x2, 0x0, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG2E16FF_V_M2 }, // 25 |
| 18936 | { 0x2, 0x0, 0x0, 0x1, 0x4, 0x2, PseudoVLSEG2E16FF_V_M4 }, // 26 |
| 18937 | { 0x2, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG2E16FF_V_MF4 }, // 27 |
| 18938 | { 0x2, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG2E16FF_V_MF2 }, // 28 |
| 18939 | { 0x2, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG2E32FF_V_M1 }, // 29 |
| 18940 | { 0x2, 0x0, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG2E32FF_V_M2 }, // 30 |
| 18941 | { 0x2, 0x0, 0x0, 0x1, 0x5, 0x2, PseudoVLSEG2E32FF_V_M4 }, // 31 |
| 18942 | { 0x2, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG2E32FF_V_MF2 }, // 32 |
| 18943 | { 0x2, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG2E64FF_V_M1 }, // 33 |
| 18944 | { 0x2, 0x0, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG2E64FF_V_M2 }, // 34 |
| 18945 | { 0x2, 0x0, 0x0, 0x1, 0x6, 0x2, PseudoVLSEG2E64FF_V_M4 }, // 35 |
| 18946 | { 0x2, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG2E8_V_M1 }, // 36 |
| 18947 | { 0x2, 0x0, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG2E8_V_M2 }, // 37 |
| 18948 | { 0x2, 0x0, 0x1, 0x0, 0x3, 0x2, PseudoVLSSEG2E8_V_M4 }, // 38 |
| 18949 | { 0x2, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG2E8_V_MF8 }, // 39 |
| 18950 | { 0x2, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG2E8_V_MF4 }, // 40 |
| 18951 | { 0x2, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG2E8_V_MF2 }, // 41 |
| 18952 | { 0x2, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG2E16_V_M1 }, // 42 |
| 18953 | { 0x2, 0x0, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG2E16_V_M2 }, // 43 |
| 18954 | { 0x2, 0x0, 0x1, 0x0, 0x4, 0x2, PseudoVLSSEG2E16_V_M4 }, // 44 |
| 18955 | { 0x2, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG2E16_V_MF4 }, // 45 |
| 18956 | { 0x2, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG2E16_V_MF2 }, // 46 |
| 18957 | { 0x2, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG2E32_V_M1 }, // 47 |
| 18958 | { 0x2, 0x0, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG2E32_V_M2 }, // 48 |
| 18959 | { 0x2, 0x0, 0x1, 0x0, 0x5, 0x2, PseudoVLSSEG2E32_V_M4 }, // 49 |
| 18960 | { 0x2, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG2E32_V_MF2 }, // 50 |
| 18961 | { 0x2, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG2E64_V_M1 }, // 51 |
| 18962 | { 0x2, 0x0, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG2E64_V_M2 }, // 52 |
| 18963 | { 0x2, 0x0, 0x1, 0x0, 0x6, 0x2, PseudoVLSSEG2E64_V_M4 }, // 53 |
| 18964 | { 0x2, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG2E8_V_M1_MASK }, // 54 |
| 18965 | { 0x2, 0x1, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG2E8_V_M2_MASK }, // 55 |
| 18966 | { 0x2, 0x1, 0x0, 0x0, 0x3, 0x2, PseudoVLSEG2E8_V_M4_MASK }, // 56 |
| 18967 | { 0x2, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG2E8_V_MF8_MASK }, // 57 |
| 18968 | { 0x2, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG2E8_V_MF4_MASK }, // 58 |
| 18969 | { 0x2, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG2E8_V_MF2_MASK }, // 59 |
| 18970 | { 0x2, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG2E16_V_M1_MASK }, // 60 |
| 18971 | { 0x2, 0x1, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG2E16_V_M2_MASK }, // 61 |
| 18972 | { 0x2, 0x1, 0x0, 0x0, 0x4, 0x2, PseudoVLSEG2E16_V_M4_MASK }, // 62 |
| 18973 | { 0x2, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG2E16_V_MF4_MASK }, // 63 |
| 18974 | { 0x2, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG2E16_V_MF2_MASK }, // 64 |
| 18975 | { 0x2, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG2E32_V_M1_MASK }, // 65 |
| 18976 | { 0x2, 0x1, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG2E32_V_M2_MASK }, // 66 |
| 18977 | { 0x2, 0x1, 0x0, 0x0, 0x5, 0x2, PseudoVLSEG2E32_V_M4_MASK }, // 67 |
| 18978 | { 0x2, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG2E32_V_MF2_MASK }, // 68 |
| 18979 | { 0x2, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG2E64_V_M1_MASK }, // 69 |
| 18980 | { 0x2, 0x1, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG2E64_V_M2_MASK }, // 70 |
| 18981 | { 0x2, 0x1, 0x0, 0x0, 0x6, 0x2, PseudoVLSEG2E64_V_M4_MASK }, // 71 |
| 18982 | { 0x2, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG2E8FF_V_M1_MASK }, // 72 |
| 18983 | { 0x2, 0x1, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG2E8FF_V_M2_MASK }, // 73 |
| 18984 | { 0x2, 0x1, 0x0, 0x1, 0x3, 0x2, PseudoVLSEG2E8FF_V_M4_MASK }, // 74 |
| 18985 | { 0x2, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG2E8FF_V_MF8_MASK }, // 75 |
| 18986 | { 0x2, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG2E8FF_V_MF4_MASK }, // 76 |
| 18987 | { 0x2, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG2E8FF_V_MF2_MASK }, // 77 |
| 18988 | { 0x2, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG2E16FF_V_M1_MASK }, // 78 |
| 18989 | { 0x2, 0x1, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG2E16FF_V_M2_MASK }, // 79 |
| 18990 | { 0x2, 0x1, 0x0, 0x1, 0x4, 0x2, PseudoVLSEG2E16FF_V_M4_MASK }, // 80 |
| 18991 | { 0x2, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG2E16FF_V_MF4_MASK }, // 81 |
| 18992 | { 0x2, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG2E16FF_V_MF2_MASK }, // 82 |
| 18993 | { 0x2, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG2E32FF_V_M1_MASK }, // 83 |
| 18994 | { 0x2, 0x1, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG2E32FF_V_M2_MASK }, // 84 |
| 18995 | { 0x2, 0x1, 0x0, 0x1, 0x5, 0x2, PseudoVLSEG2E32FF_V_M4_MASK }, // 85 |
| 18996 | { 0x2, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG2E32FF_V_MF2_MASK }, // 86 |
| 18997 | { 0x2, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG2E64FF_V_M1_MASK }, // 87 |
| 18998 | { 0x2, 0x1, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG2E64FF_V_M2_MASK }, // 88 |
| 18999 | { 0x2, 0x1, 0x0, 0x1, 0x6, 0x2, PseudoVLSEG2E64FF_V_M4_MASK }, // 89 |
| 19000 | { 0x2, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG2E8_V_M1_MASK }, // 90 |
| 19001 | { 0x2, 0x1, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG2E8_V_M2_MASK }, // 91 |
| 19002 | { 0x2, 0x1, 0x1, 0x0, 0x3, 0x2, PseudoVLSSEG2E8_V_M4_MASK }, // 92 |
| 19003 | { 0x2, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG2E8_V_MF8_MASK }, // 93 |
| 19004 | { 0x2, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG2E8_V_MF4_MASK }, // 94 |
| 19005 | { 0x2, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG2E8_V_MF2_MASK }, // 95 |
| 19006 | { 0x2, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG2E16_V_M1_MASK }, // 96 |
| 19007 | { 0x2, 0x1, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG2E16_V_M2_MASK }, // 97 |
| 19008 | { 0x2, 0x1, 0x1, 0x0, 0x4, 0x2, PseudoVLSSEG2E16_V_M4_MASK }, // 98 |
| 19009 | { 0x2, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG2E16_V_MF4_MASK }, // 99 |
| 19010 | { 0x2, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG2E16_V_MF2_MASK }, // 100 |
| 19011 | { 0x2, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG2E32_V_M1_MASK }, // 101 |
| 19012 | { 0x2, 0x1, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG2E32_V_M2_MASK }, // 102 |
| 19013 | { 0x2, 0x1, 0x1, 0x0, 0x5, 0x2, PseudoVLSSEG2E32_V_M4_MASK }, // 103 |
| 19014 | { 0x2, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG2E32_V_MF2_MASK }, // 104 |
| 19015 | { 0x2, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG2E64_V_M1_MASK }, // 105 |
| 19016 | { 0x2, 0x1, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG2E64_V_M2_MASK }, // 106 |
| 19017 | { 0x2, 0x1, 0x1, 0x0, 0x6, 0x2, PseudoVLSSEG2E64_V_M4_MASK }, // 107 |
| 19018 | { 0x3, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG3E8_V_M1 }, // 108 |
| 19019 | { 0x3, 0x0, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG3E8_V_M2 }, // 109 |
| 19020 | { 0x3, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG3E8_V_MF8 }, // 110 |
| 19021 | { 0x3, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG3E8_V_MF4 }, // 111 |
| 19022 | { 0x3, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG3E8_V_MF2 }, // 112 |
| 19023 | { 0x3, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG3E16_V_M1 }, // 113 |
| 19024 | { 0x3, 0x0, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG3E16_V_M2 }, // 114 |
| 19025 | { 0x3, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG3E16_V_MF4 }, // 115 |
| 19026 | { 0x3, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG3E16_V_MF2 }, // 116 |
| 19027 | { 0x3, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG3E32_V_M1 }, // 117 |
| 19028 | { 0x3, 0x0, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG3E32_V_M2 }, // 118 |
| 19029 | { 0x3, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG3E32_V_MF2 }, // 119 |
| 19030 | { 0x3, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG3E64_V_M1 }, // 120 |
| 19031 | { 0x3, 0x0, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG3E64_V_M2 }, // 121 |
| 19032 | { 0x3, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG3E8FF_V_M1 }, // 122 |
| 19033 | { 0x3, 0x0, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG3E8FF_V_M2 }, // 123 |
| 19034 | { 0x3, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG3E8FF_V_MF8 }, // 124 |
| 19035 | { 0x3, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG3E8FF_V_MF4 }, // 125 |
| 19036 | { 0x3, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG3E8FF_V_MF2 }, // 126 |
| 19037 | { 0x3, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG3E16FF_V_M1 }, // 127 |
| 19038 | { 0x3, 0x0, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG3E16FF_V_M2 }, // 128 |
| 19039 | { 0x3, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG3E16FF_V_MF4 }, // 129 |
| 19040 | { 0x3, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG3E16FF_V_MF2 }, // 130 |
| 19041 | { 0x3, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG3E32FF_V_M1 }, // 131 |
| 19042 | { 0x3, 0x0, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG3E32FF_V_M2 }, // 132 |
| 19043 | { 0x3, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG3E32FF_V_MF2 }, // 133 |
| 19044 | { 0x3, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG3E64FF_V_M1 }, // 134 |
| 19045 | { 0x3, 0x0, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG3E64FF_V_M2 }, // 135 |
| 19046 | { 0x3, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG3E8_V_M1 }, // 136 |
| 19047 | { 0x3, 0x0, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG3E8_V_M2 }, // 137 |
| 19048 | { 0x3, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG3E8_V_MF8 }, // 138 |
| 19049 | { 0x3, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG3E8_V_MF4 }, // 139 |
| 19050 | { 0x3, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG3E8_V_MF2 }, // 140 |
| 19051 | { 0x3, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG3E16_V_M1 }, // 141 |
| 19052 | { 0x3, 0x0, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG3E16_V_M2 }, // 142 |
| 19053 | { 0x3, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG3E16_V_MF4 }, // 143 |
| 19054 | { 0x3, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG3E16_V_MF2 }, // 144 |
| 19055 | { 0x3, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG3E32_V_M1 }, // 145 |
| 19056 | { 0x3, 0x0, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG3E32_V_M2 }, // 146 |
| 19057 | { 0x3, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG3E32_V_MF2 }, // 147 |
| 19058 | { 0x3, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG3E64_V_M1 }, // 148 |
| 19059 | { 0x3, 0x0, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG3E64_V_M2 }, // 149 |
| 19060 | { 0x3, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG3E8_V_M1_MASK }, // 150 |
| 19061 | { 0x3, 0x1, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG3E8_V_M2_MASK }, // 151 |
| 19062 | { 0x3, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG3E8_V_MF8_MASK }, // 152 |
| 19063 | { 0x3, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG3E8_V_MF4_MASK }, // 153 |
| 19064 | { 0x3, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG3E8_V_MF2_MASK }, // 154 |
| 19065 | { 0x3, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG3E16_V_M1_MASK }, // 155 |
| 19066 | { 0x3, 0x1, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG3E16_V_M2_MASK }, // 156 |
| 19067 | { 0x3, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG3E16_V_MF4_MASK }, // 157 |
| 19068 | { 0x3, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG3E16_V_MF2_MASK }, // 158 |
| 19069 | { 0x3, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG3E32_V_M1_MASK }, // 159 |
| 19070 | { 0x3, 0x1, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG3E32_V_M2_MASK }, // 160 |
| 19071 | { 0x3, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG3E32_V_MF2_MASK }, // 161 |
| 19072 | { 0x3, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG3E64_V_M1_MASK }, // 162 |
| 19073 | { 0x3, 0x1, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG3E64_V_M2_MASK }, // 163 |
| 19074 | { 0x3, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG3E8FF_V_M1_MASK }, // 164 |
| 19075 | { 0x3, 0x1, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG3E8FF_V_M2_MASK }, // 165 |
| 19076 | { 0x3, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG3E8FF_V_MF8_MASK }, // 166 |
| 19077 | { 0x3, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG3E8FF_V_MF4_MASK }, // 167 |
| 19078 | { 0x3, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG3E8FF_V_MF2_MASK }, // 168 |
| 19079 | { 0x3, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG3E16FF_V_M1_MASK }, // 169 |
| 19080 | { 0x3, 0x1, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG3E16FF_V_M2_MASK }, // 170 |
| 19081 | { 0x3, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG3E16FF_V_MF4_MASK }, // 171 |
| 19082 | { 0x3, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG3E16FF_V_MF2_MASK }, // 172 |
| 19083 | { 0x3, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG3E32FF_V_M1_MASK }, // 173 |
| 19084 | { 0x3, 0x1, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG3E32FF_V_M2_MASK }, // 174 |
| 19085 | { 0x3, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG3E32FF_V_MF2_MASK }, // 175 |
| 19086 | { 0x3, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG3E64FF_V_M1_MASK }, // 176 |
| 19087 | { 0x3, 0x1, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG3E64FF_V_M2_MASK }, // 177 |
| 19088 | { 0x3, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG3E8_V_M1_MASK }, // 178 |
| 19089 | { 0x3, 0x1, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG3E8_V_M2_MASK }, // 179 |
| 19090 | { 0x3, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG3E8_V_MF8_MASK }, // 180 |
| 19091 | { 0x3, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG3E8_V_MF4_MASK }, // 181 |
| 19092 | { 0x3, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG3E8_V_MF2_MASK }, // 182 |
| 19093 | { 0x3, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG3E16_V_M1_MASK }, // 183 |
| 19094 | { 0x3, 0x1, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG3E16_V_M2_MASK }, // 184 |
| 19095 | { 0x3, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG3E16_V_MF4_MASK }, // 185 |
| 19096 | { 0x3, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG3E16_V_MF2_MASK }, // 186 |
| 19097 | { 0x3, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG3E32_V_M1_MASK }, // 187 |
| 19098 | { 0x3, 0x1, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG3E32_V_M2_MASK }, // 188 |
| 19099 | { 0x3, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG3E32_V_MF2_MASK }, // 189 |
| 19100 | { 0x3, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG3E64_V_M1_MASK }, // 190 |
| 19101 | { 0x3, 0x1, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG3E64_V_M2_MASK }, // 191 |
| 19102 | { 0x4, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG4E8_V_M1 }, // 192 |
| 19103 | { 0x4, 0x0, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG4E8_V_M2 }, // 193 |
| 19104 | { 0x4, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG4E8_V_MF8 }, // 194 |
| 19105 | { 0x4, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG4E8_V_MF4 }, // 195 |
| 19106 | { 0x4, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG4E8_V_MF2 }, // 196 |
| 19107 | { 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG4E16_V_M1 }, // 197 |
| 19108 | { 0x4, 0x0, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG4E16_V_M2 }, // 198 |
| 19109 | { 0x4, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG4E16_V_MF4 }, // 199 |
| 19110 | { 0x4, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG4E16_V_MF2 }, // 200 |
| 19111 | { 0x4, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG4E32_V_M1 }, // 201 |
| 19112 | { 0x4, 0x0, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG4E32_V_M2 }, // 202 |
| 19113 | { 0x4, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG4E32_V_MF2 }, // 203 |
| 19114 | { 0x4, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG4E64_V_M1 }, // 204 |
| 19115 | { 0x4, 0x0, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG4E64_V_M2 }, // 205 |
| 19116 | { 0x4, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG4E8FF_V_M1 }, // 206 |
| 19117 | { 0x4, 0x0, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG4E8FF_V_M2 }, // 207 |
| 19118 | { 0x4, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG4E8FF_V_MF8 }, // 208 |
| 19119 | { 0x4, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG4E8FF_V_MF4 }, // 209 |
| 19120 | { 0x4, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG4E8FF_V_MF2 }, // 210 |
| 19121 | { 0x4, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG4E16FF_V_M1 }, // 211 |
| 19122 | { 0x4, 0x0, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG4E16FF_V_M2 }, // 212 |
| 19123 | { 0x4, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG4E16FF_V_MF4 }, // 213 |
| 19124 | { 0x4, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG4E16FF_V_MF2 }, // 214 |
| 19125 | { 0x4, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG4E32FF_V_M1 }, // 215 |
| 19126 | { 0x4, 0x0, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG4E32FF_V_M2 }, // 216 |
| 19127 | { 0x4, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG4E32FF_V_MF2 }, // 217 |
| 19128 | { 0x4, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG4E64FF_V_M1 }, // 218 |
| 19129 | { 0x4, 0x0, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG4E64FF_V_M2 }, // 219 |
| 19130 | { 0x4, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG4E8_V_M1 }, // 220 |
| 19131 | { 0x4, 0x0, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG4E8_V_M2 }, // 221 |
| 19132 | { 0x4, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG4E8_V_MF8 }, // 222 |
| 19133 | { 0x4, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG4E8_V_MF4 }, // 223 |
| 19134 | { 0x4, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG4E8_V_MF2 }, // 224 |
| 19135 | { 0x4, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG4E16_V_M1 }, // 225 |
| 19136 | { 0x4, 0x0, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG4E16_V_M2 }, // 226 |
| 19137 | { 0x4, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG4E16_V_MF4 }, // 227 |
| 19138 | { 0x4, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG4E16_V_MF2 }, // 228 |
| 19139 | { 0x4, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG4E32_V_M1 }, // 229 |
| 19140 | { 0x4, 0x0, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG4E32_V_M2 }, // 230 |
| 19141 | { 0x4, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG4E32_V_MF2 }, // 231 |
| 19142 | { 0x4, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG4E64_V_M1 }, // 232 |
| 19143 | { 0x4, 0x0, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG4E64_V_M2 }, // 233 |
| 19144 | { 0x4, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG4E8_V_M1_MASK }, // 234 |
| 19145 | { 0x4, 0x1, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG4E8_V_M2_MASK }, // 235 |
| 19146 | { 0x4, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG4E8_V_MF8_MASK }, // 236 |
| 19147 | { 0x4, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG4E8_V_MF4_MASK }, // 237 |
| 19148 | { 0x4, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG4E8_V_MF2_MASK }, // 238 |
| 19149 | { 0x4, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG4E16_V_M1_MASK }, // 239 |
| 19150 | { 0x4, 0x1, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG4E16_V_M2_MASK }, // 240 |
| 19151 | { 0x4, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG4E16_V_MF4_MASK }, // 241 |
| 19152 | { 0x4, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG4E16_V_MF2_MASK }, // 242 |
| 19153 | { 0x4, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG4E32_V_M1_MASK }, // 243 |
| 19154 | { 0x4, 0x1, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG4E32_V_M2_MASK }, // 244 |
| 19155 | { 0x4, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG4E32_V_MF2_MASK }, // 245 |
| 19156 | { 0x4, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG4E64_V_M1_MASK }, // 246 |
| 19157 | { 0x4, 0x1, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG4E64_V_M2_MASK }, // 247 |
| 19158 | { 0x4, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG4E8FF_V_M1_MASK }, // 248 |
| 19159 | { 0x4, 0x1, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG4E8FF_V_M2_MASK }, // 249 |
| 19160 | { 0x4, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG4E8FF_V_MF8_MASK }, // 250 |
| 19161 | { 0x4, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG4E8FF_V_MF4_MASK }, // 251 |
| 19162 | { 0x4, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG4E8FF_V_MF2_MASK }, // 252 |
| 19163 | { 0x4, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG4E16FF_V_M1_MASK }, // 253 |
| 19164 | { 0x4, 0x1, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG4E16FF_V_M2_MASK }, // 254 |
| 19165 | { 0x4, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG4E16FF_V_MF4_MASK }, // 255 |
| 19166 | { 0x4, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG4E16FF_V_MF2_MASK }, // 256 |
| 19167 | { 0x4, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG4E32FF_V_M1_MASK }, // 257 |
| 19168 | { 0x4, 0x1, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG4E32FF_V_M2_MASK }, // 258 |
| 19169 | { 0x4, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG4E32FF_V_MF2_MASK }, // 259 |
| 19170 | { 0x4, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG4E64FF_V_M1_MASK }, // 260 |
| 19171 | { 0x4, 0x1, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG4E64FF_V_M2_MASK }, // 261 |
| 19172 | { 0x4, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG4E8_V_M1_MASK }, // 262 |
| 19173 | { 0x4, 0x1, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG4E8_V_M2_MASK }, // 263 |
| 19174 | { 0x4, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG4E8_V_MF8_MASK }, // 264 |
| 19175 | { 0x4, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG4E8_V_MF4_MASK }, // 265 |
| 19176 | { 0x4, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG4E8_V_MF2_MASK }, // 266 |
| 19177 | { 0x4, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG4E16_V_M1_MASK }, // 267 |
| 19178 | { 0x4, 0x1, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG4E16_V_M2_MASK }, // 268 |
| 19179 | { 0x4, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG4E16_V_MF4_MASK }, // 269 |
| 19180 | { 0x4, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG4E16_V_MF2_MASK }, // 270 |
| 19181 | { 0x4, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG4E32_V_M1_MASK }, // 271 |
| 19182 | { 0x4, 0x1, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG4E32_V_M2_MASK }, // 272 |
| 19183 | { 0x4, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG4E32_V_MF2_MASK }, // 273 |
| 19184 | { 0x4, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG4E64_V_M1_MASK }, // 274 |
| 19185 | { 0x4, 0x1, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG4E64_V_M2_MASK }, // 275 |
| 19186 | { 0x5, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG5E8_V_M1 }, // 276 |
| 19187 | { 0x5, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG5E8_V_MF8 }, // 277 |
| 19188 | { 0x5, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG5E8_V_MF4 }, // 278 |
| 19189 | { 0x5, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG5E8_V_MF2 }, // 279 |
| 19190 | { 0x5, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG5E16_V_M1 }, // 280 |
| 19191 | { 0x5, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG5E16_V_MF4 }, // 281 |
| 19192 | { 0x5, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG5E16_V_MF2 }, // 282 |
| 19193 | { 0x5, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG5E32_V_M1 }, // 283 |
| 19194 | { 0x5, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG5E32_V_MF2 }, // 284 |
| 19195 | { 0x5, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG5E64_V_M1 }, // 285 |
| 19196 | { 0x5, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG5E8FF_V_M1 }, // 286 |
| 19197 | { 0x5, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG5E8FF_V_MF8 }, // 287 |
| 19198 | { 0x5, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG5E8FF_V_MF4 }, // 288 |
| 19199 | { 0x5, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG5E8FF_V_MF2 }, // 289 |
| 19200 | { 0x5, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG5E16FF_V_M1 }, // 290 |
| 19201 | { 0x5, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG5E16FF_V_MF4 }, // 291 |
| 19202 | { 0x5, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG5E16FF_V_MF2 }, // 292 |
| 19203 | { 0x5, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG5E32FF_V_M1 }, // 293 |
| 19204 | { 0x5, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG5E32FF_V_MF2 }, // 294 |
| 19205 | { 0x5, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG5E64FF_V_M1 }, // 295 |
| 19206 | { 0x5, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG5E8_V_M1 }, // 296 |
| 19207 | { 0x5, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG5E8_V_MF8 }, // 297 |
| 19208 | { 0x5, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG5E8_V_MF4 }, // 298 |
| 19209 | { 0x5, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG5E8_V_MF2 }, // 299 |
| 19210 | { 0x5, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG5E16_V_M1 }, // 300 |
| 19211 | { 0x5, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG5E16_V_MF4 }, // 301 |
| 19212 | { 0x5, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG5E16_V_MF2 }, // 302 |
| 19213 | { 0x5, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG5E32_V_M1 }, // 303 |
| 19214 | { 0x5, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG5E32_V_MF2 }, // 304 |
| 19215 | { 0x5, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG5E64_V_M1 }, // 305 |
| 19216 | { 0x5, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG5E8_V_M1_MASK }, // 306 |
| 19217 | { 0x5, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG5E8_V_MF8_MASK }, // 307 |
| 19218 | { 0x5, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG5E8_V_MF4_MASK }, // 308 |
| 19219 | { 0x5, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG5E8_V_MF2_MASK }, // 309 |
| 19220 | { 0x5, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG5E16_V_M1_MASK }, // 310 |
| 19221 | { 0x5, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG5E16_V_MF4_MASK }, // 311 |
| 19222 | { 0x5, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG5E16_V_MF2_MASK }, // 312 |
| 19223 | { 0x5, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG5E32_V_M1_MASK }, // 313 |
| 19224 | { 0x5, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG5E32_V_MF2_MASK }, // 314 |
| 19225 | { 0x5, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG5E64_V_M1_MASK }, // 315 |
| 19226 | { 0x5, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG5E8FF_V_M1_MASK }, // 316 |
| 19227 | { 0x5, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG5E8FF_V_MF8_MASK }, // 317 |
| 19228 | { 0x5, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG5E8FF_V_MF4_MASK }, // 318 |
| 19229 | { 0x5, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG5E8FF_V_MF2_MASK }, // 319 |
| 19230 | { 0x5, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG5E16FF_V_M1_MASK }, // 320 |
| 19231 | { 0x5, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG5E16FF_V_MF4_MASK }, // 321 |
| 19232 | { 0x5, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG5E16FF_V_MF2_MASK }, // 322 |
| 19233 | { 0x5, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG5E32FF_V_M1_MASK }, // 323 |
| 19234 | { 0x5, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG5E32FF_V_MF2_MASK }, // 324 |
| 19235 | { 0x5, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG5E64FF_V_M1_MASK }, // 325 |
| 19236 | { 0x5, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG5E8_V_M1_MASK }, // 326 |
| 19237 | { 0x5, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG5E8_V_MF8_MASK }, // 327 |
| 19238 | { 0x5, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG5E8_V_MF4_MASK }, // 328 |
| 19239 | { 0x5, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG5E8_V_MF2_MASK }, // 329 |
| 19240 | { 0x5, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG5E16_V_M1_MASK }, // 330 |
| 19241 | { 0x5, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG5E16_V_MF4_MASK }, // 331 |
| 19242 | { 0x5, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG5E16_V_MF2_MASK }, // 332 |
| 19243 | { 0x5, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG5E32_V_M1_MASK }, // 333 |
| 19244 | { 0x5, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG5E32_V_MF2_MASK }, // 334 |
| 19245 | { 0x5, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG5E64_V_M1_MASK }, // 335 |
| 19246 | { 0x6, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG6E8_V_M1 }, // 336 |
| 19247 | { 0x6, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG6E8_V_MF8 }, // 337 |
| 19248 | { 0x6, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG6E8_V_MF4 }, // 338 |
| 19249 | { 0x6, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG6E8_V_MF2 }, // 339 |
| 19250 | { 0x6, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG6E16_V_M1 }, // 340 |
| 19251 | { 0x6, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG6E16_V_MF4 }, // 341 |
| 19252 | { 0x6, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG6E16_V_MF2 }, // 342 |
| 19253 | { 0x6, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG6E32_V_M1 }, // 343 |
| 19254 | { 0x6, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG6E32_V_MF2 }, // 344 |
| 19255 | { 0x6, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG6E64_V_M1 }, // 345 |
| 19256 | { 0x6, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG6E8FF_V_M1 }, // 346 |
| 19257 | { 0x6, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG6E8FF_V_MF8 }, // 347 |
| 19258 | { 0x6, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG6E8FF_V_MF4 }, // 348 |
| 19259 | { 0x6, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG6E8FF_V_MF2 }, // 349 |
| 19260 | { 0x6, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG6E16FF_V_M1 }, // 350 |
| 19261 | { 0x6, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG6E16FF_V_MF4 }, // 351 |
| 19262 | { 0x6, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG6E16FF_V_MF2 }, // 352 |
| 19263 | { 0x6, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG6E32FF_V_M1 }, // 353 |
| 19264 | { 0x6, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG6E32FF_V_MF2 }, // 354 |
| 19265 | { 0x6, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG6E64FF_V_M1 }, // 355 |
| 19266 | { 0x6, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG6E8_V_M1 }, // 356 |
| 19267 | { 0x6, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG6E8_V_MF8 }, // 357 |
| 19268 | { 0x6, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG6E8_V_MF4 }, // 358 |
| 19269 | { 0x6, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG6E8_V_MF2 }, // 359 |
| 19270 | { 0x6, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG6E16_V_M1 }, // 360 |
| 19271 | { 0x6, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG6E16_V_MF4 }, // 361 |
| 19272 | { 0x6, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG6E16_V_MF2 }, // 362 |
| 19273 | { 0x6, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG6E32_V_M1 }, // 363 |
| 19274 | { 0x6, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG6E32_V_MF2 }, // 364 |
| 19275 | { 0x6, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG6E64_V_M1 }, // 365 |
| 19276 | { 0x6, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG6E8_V_M1_MASK }, // 366 |
| 19277 | { 0x6, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG6E8_V_MF8_MASK }, // 367 |
| 19278 | { 0x6, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG6E8_V_MF4_MASK }, // 368 |
| 19279 | { 0x6, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG6E8_V_MF2_MASK }, // 369 |
| 19280 | { 0x6, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG6E16_V_M1_MASK }, // 370 |
| 19281 | { 0x6, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG6E16_V_MF4_MASK }, // 371 |
| 19282 | { 0x6, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG6E16_V_MF2_MASK }, // 372 |
| 19283 | { 0x6, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG6E32_V_M1_MASK }, // 373 |
| 19284 | { 0x6, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG6E32_V_MF2_MASK }, // 374 |
| 19285 | { 0x6, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG6E64_V_M1_MASK }, // 375 |
| 19286 | { 0x6, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG6E8FF_V_M1_MASK }, // 376 |
| 19287 | { 0x6, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG6E8FF_V_MF8_MASK }, // 377 |
| 19288 | { 0x6, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG6E8FF_V_MF4_MASK }, // 378 |
| 19289 | { 0x6, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG6E8FF_V_MF2_MASK }, // 379 |
| 19290 | { 0x6, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG6E16FF_V_M1_MASK }, // 380 |
| 19291 | { 0x6, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG6E16FF_V_MF4_MASK }, // 381 |
| 19292 | { 0x6, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG6E16FF_V_MF2_MASK }, // 382 |
| 19293 | { 0x6, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG6E32FF_V_M1_MASK }, // 383 |
| 19294 | { 0x6, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG6E32FF_V_MF2_MASK }, // 384 |
| 19295 | { 0x6, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG6E64FF_V_M1_MASK }, // 385 |
| 19296 | { 0x6, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG6E8_V_M1_MASK }, // 386 |
| 19297 | { 0x6, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG6E8_V_MF8_MASK }, // 387 |
| 19298 | { 0x6, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG6E8_V_MF4_MASK }, // 388 |
| 19299 | { 0x6, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG6E8_V_MF2_MASK }, // 389 |
| 19300 | { 0x6, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG6E16_V_M1_MASK }, // 390 |
| 19301 | { 0x6, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG6E16_V_MF4_MASK }, // 391 |
| 19302 | { 0x6, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG6E16_V_MF2_MASK }, // 392 |
| 19303 | { 0x6, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG6E32_V_M1_MASK }, // 393 |
| 19304 | { 0x6, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG6E32_V_MF2_MASK }, // 394 |
| 19305 | { 0x6, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG6E64_V_M1_MASK }, // 395 |
| 19306 | { 0x7, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG7E8_V_M1 }, // 396 |
| 19307 | { 0x7, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG7E8_V_MF8 }, // 397 |
| 19308 | { 0x7, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG7E8_V_MF4 }, // 398 |
| 19309 | { 0x7, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG7E8_V_MF2 }, // 399 |
| 19310 | { 0x7, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG7E16_V_M1 }, // 400 |
| 19311 | { 0x7, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG7E16_V_MF4 }, // 401 |
| 19312 | { 0x7, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG7E16_V_MF2 }, // 402 |
| 19313 | { 0x7, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG7E32_V_M1 }, // 403 |
| 19314 | { 0x7, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG7E32_V_MF2 }, // 404 |
| 19315 | { 0x7, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG7E64_V_M1 }, // 405 |
| 19316 | { 0x7, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG7E8FF_V_M1 }, // 406 |
| 19317 | { 0x7, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG7E8FF_V_MF8 }, // 407 |
| 19318 | { 0x7, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG7E8FF_V_MF4 }, // 408 |
| 19319 | { 0x7, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG7E8FF_V_MF2 }, // 409 |
| 19320 | { 0x7, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG7E16FF_V_M1 }, // 410 |
| 19321 | { 0x7, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG7E16FF_V_MF4 }, // 411 |
| 19322 | { 0x7, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG7E16FF_V_MF2 }, // 412 |
| 19323 | { 0x7, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG7E32FF_V_M1 }, // 413 |
| 19324 | { 0x7, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG7E32FF_V_MF2 }, // 414 |
| 19325 | { 0x7, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG7E64FF_V_M1 }, // 415 |
| 19326 | { 0x7, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG7E8_V_M1 }, // 416 |
| 19327 | { 0x7, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG7E8_V_MF8 }, // 417 |
| 19328 | { 0x7, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG7E8_V_MF4 }, // 418 |
| 19329 | { 0x7, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG7E8_V_MF2 }, // 419 |
| 19330 | { 0x7, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG7E16_V_M1 }, // 420 |
| 19331 | { 0x7, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG7E16_V_MF4 }, // 421 |
| 19332 | { 0x7, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG7E16_V_MF2 }, // 422 |
| 19333 | { 0x7, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG7E32_V_M1 }, // 423 |
| 19334 | { 0x7, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG7E32_V_MF2 }, // 424 |
| 19335 | { 0x7, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG7E64_V_M1 }, // 425 |
| 19336 | { 0x7, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG7E8_V_M1_MASK }, // 426 |
| 19337 | { 0x7, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG7E8_V_MF8_MASK }, // 427 |
| 19338 | { 0x7, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG7E8_V_MF4_MASK }, // 428 |
| 19339 | { 0x7, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG7E8_V_MF2_MASK }, // 429 |
| 19340 | { 0x7, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG7E16_V_M1_MASK }, // 430 |
| 19341 | { 0x7, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG7E16_V_MF4_MASK }, // 431 |
| 19342 | { 0x7, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG7E16_V_MF2_MASK }, // 432 |
| 19343 | { 0x7, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG7E32_V_M1_MASK }, // 433 |
| 19344 | { 0x7, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG7E32_V_MF2_MASK }, // 434 |
| 19345 | { 0x7, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG7E64_V_M1_MASK }, // 435 |
| 19346 | { 0x7, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG7E8FF_V_M1_MASK }, // 436 |
| 19347 | { 0x7, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG7E8FF_V_MF8_MASK }, // 437 |
| 19348 | { 0x7, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG7E8FF_V_MF4_MASK }, // 438 |
| 19349 | { 0x7, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG7E8FF_V_MF2_MASK }, // 439 |
| 19350 | { 0x7, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG7E16FF_V_M1_MASK }, // 440 |
| 19351 | { 0x7, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG7E16FF_V_MF4_MASK }, // 441 |
| 19352 | { 0x7, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG7E16FF_V_MF2_MASK }, // 442 |
| 19353 | { 0x7, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG7E32FF_V_M1_MASK }, // 443 |
| 19354 | { 0x7, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG7E32FF_V_MF2_MASK }, // 444 |
| 19355 | { 0x7, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG7E64FF_V_M1_MASK }, // 445 |
| 19356 | { 0x7, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG7E8_V_M1_MASK }, // 446 |
| 19357 | { 0x7, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG7E8_V_MF8_MASK }, // 447 |
| 19358 | { 0x7, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG7E8_V_MF4_MASK }, // 448 |
| 19359 | { 0x7, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG7E8_V_MF2_MASK }, // 449 |
| 19360 | { 0x7, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG7E16_V_M1_MASK }, // 450 |
| 19361 | { 0x7, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG7E16_V_MF4_MASK }, // 451 |
| 19362 | { 0x7, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG7E16_V_MF2_MASK }, // 452 |
| 19363 | { 0x7, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG7E32_V_M1_MASK }, // 453 |
| 19364 | { 0x7, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG7E32_V_MF2_MASK }, // 454 |
| 19365 | { 0x7, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG7E64_V_M1_MASK }, // 455 |
| 19366 | { 0x8, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG8E8_V_M1 }, // 456 |
| 19367 | { 0x8, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG8E8_V_MF8 }, // 457 |
| 19368 | { 0x8, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG8E8_V_MF4 }, // 458 |
| 19369 | { 0x8, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG8E8_V_MF2 }, // 459 |
| 19370 | { 0x8, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG8E16_V_M1 }, // 460 |
| 19371 | { 0x8, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG8E16_V_MF4 }, // 461 |
| 19372 | { 0x8, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG8E16_V_MF2 }, // 462 |
| 19373 | { 0x8, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG8E32_V_M1 }, // 463 |
| 19374 | { 0x8, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG8E32_V_MF2 }, // 464 |
| 19375 | { 0x8, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG8E64_V_M1 }, // 465 |
| 19376 | { 0x8, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG8E8FF_V_M1 }, // 466 |
| 19377 | { 0x8, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG8E8FF_V_MF8 }, // 467 |
| 19378 | { 0x8, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG8E8FF_V_MF4 }, // 468 |
| 19379 | { 0x8, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG8E8FF_V_MF2 }, // 469 |
| 19380 | { 0x8, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG8E16FF_V_M1 }, // 470 |
| 19381 | { 0x8, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG8E16FF_V_MF4 }, // 471 |
| 19382 | { 0x8, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG8E16FF_V_MF2 }, // 472 |
| 19383 | { 0x8, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG8E32FF_V_M1 }, // 473 |
| 19384 | { 0x8, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG8E32FF_V_MF2 }, // 474 |
| 19385 | { 0x8, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG8E64FF_V_M1 }, // 475 |
| 19386 | { 0x8, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG8E8_V_M1 }, // 476 |
| 19387 | { 0x8, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG8E8_V_MF8 }, // 477 |
| 19388 | { 0x8, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG8E8_V_MF4 }, // 478 |
| 19389 | { 0x8, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG8E8_V_MF2 }, // 479 |
| 19390 | { 0x8, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG8E16_V_M1 }, // 480 |
| 19391 | { 0x8, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG8E16_V_MF4 }, // 481 |
| 19392 | { 0x8, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG8E16_V_MF2 }, // 482 |
| 19393 | { 0x8, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG8E32_V_M1 }, // 483 |
| 19394 | { 0x8, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG8E32_V_MF2 }, // 484 |
| 19395 | { 0x8, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG8E64_V_M1 }, // 485 |
| 19396 | { 0x8, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG8E8_V_M1_MASK }, // 486 |
| 19397 | { 0x8, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG8E8_V_MF8_MASK }, // 487 |
| 19398 | { 0x8, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG8E8_V_MF4_MASK }, // 488 |
| 19399 | { 0x8, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG8E8_V_MF2_MASK }, // 489 |
| 19400 | { 0x8, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG8E16_V_M1_MASK }, // 490 |
| 19401 | { 0x8, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG8E16_V_MF4_MASK }, // 491 |
| 19402 | { 0x8, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG8E16_V_MF2_MASK }, // 492 |
| 19403 | { 0x8, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG8E32_V_M1_MASK }, // 493 |
| 19404 | { 0x8, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG8E32_V_MF2_MASK }, // 494 |
| 19405 | { 0x8, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG8E64_V_M1_MASK }, // 495 |
| 19406 | { 0x8, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG8E8FF_V_M1_MASK }, // 496 |
| 19407 | { 0x8, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG8E8FF_V_MF8_MASK }, // 497 |
| 19408 | { 0x8, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG8E8FF_V_MF4_MASK }, // 498 |
| 19409 | { 0x8, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG8E8FF_V_MF2_MASK }, // 499 |
| 19410 | { 0x8, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG8E16FF_V_M1_MASK }, // 500 |
| 19411 | { 0x8, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG8E16FF_V_MF4_MASK }, // 501 |
| 19412 | { 0x8, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG8E16FF_V_MF2_MASK }, // 502 |
| 19413 | { 0x8, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG8E32FF_V_M1_MASK }, // 503 |
| 19414 | { 0x8, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG8E32FF_V_MF2_MASK }, // 504 |
| 19415 | { 0x8, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG8E64FF_V_M1_MASK }, // 505 |
| 19416 | { 0x8, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG8E8_V_M1_MASK }, // 506 |
| 19417 | { 0x8, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG8E8_V_MF8_MASK }, // 507 |
| 19418 | { 0x8, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG8E8_V_MF4_MASK }, // 508 |
| 19419 | { 0x8, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG8E8_V_MF2_MASK }, // 509 |
| 19420 | { 0x8, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG8E16_V_M1_MASK }, // 510 |
| 19421 | { 0x8, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG8E16_V_MF4_MASK }, // 511 |
| 19422 | { 0x8, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG8E16_V_MF2_MASK }, // 512 |
| 19423 | { 0x8, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG8E32_V_M1_MASK }, // 513 |
| 19424 | { 0x8, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG8E32_V_MF2_MASK }, // 514 |
| 19425 | { 0x8, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG8E64_V_M1_MASK }, // 515 |
| 19426 | }; |
| 19427 | |
| 19428 | const VLSEGPseudo *getVLSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Strided, uint8_t FF, uint8_t Log2SEW, uint8_t LMUL) { |
| 19429 | struct KeyType { |
| 19430 | uint8_t NF; |
| 19431 | uint8_t Masked; |
| 19432 | uint8_t Strided; |
| 19433 | uint8_t FF; |
| 19434 | uint8_t Log2SEW; |
| 19435 | uint8_t LMUL; |
| 19436 | }; |
| 19437 | KeyType Key = {NF, Masked, Strided, FF, Log2SEW, LMUL}; |
| 19438 | struct Comp { |
| 19439 | bool operator()(const VLSEGPseudo &LHS, const KeyType &RHS) const { |
| 19440 | if (LHS.NF < RHS.NF) |
| 19441 | return true; |
| 19442 | if (LHS.NF > RHS.NF) |
| 19443 | return false; |
| 19444 | if (LHS.Masked < RHS.Masked) |
| 19445 | return true; |
| 19446 | if (LHS.Masked > RHS.Masked) |
| 19447 | return false; |
| 19448 | if (LHS.Strided < RHS.Strided) |
| 19449 | return true; |
| 19450 | if (LHS.Strided > RHS.Strided) |
| 19451 | return false; |
| 19452 | if (LHS.FF < RHS.FF) |
| 19453 | return true; |
| 19454 | if (LHS.FF > RHS.FF) |
| 19455 | return false; |
| 19456 | if (LHS.Log2SEW < RHS.Log2SEW) |
| 19457 | return true; |
| 19458 | if (LHS.Log2SEW > RHS.Log2SEW) |
| 19459 | return false; |
| 19460 | if (LHS.LMUL < RHS.LMUL) |
| 19461 | return true; |
| 19462 | if (LHS.LMUL > RHS.LMUL) |
| 19463 | return false; |
| 19464 | return false; |
| 19465 | } |
| 19466 | }; |
| 19467 | auto Table = ArrayRef(RISCVVLSEGTable); |
| 19468 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 19469 | if (Idx == Table.end() || |
| 19470 | Key.NF != Idx->NF || |
| 19471 | Key.Masked != Idx->Masked || |
| 19472 | Key.Strided != Idx->Strided || |
| 19473 | Key.FF != Idx->FF || |
| 19474 | Key.Log2SEW != Idx->Log2SEW || |
| 19475 | Key.LMUL != Idx->LMUL) |
| 19476 | return nullptr; |
| 19477 | |
| 19478 | return &*Idx; |
| 19479 | } |
| 19480 | #endif |
| 19481 | |
| 19482 | #ifdef GET_RISCVVLXSEGTable_DECL |
| 19483 | const VLXSEGPseudo *getVLXSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL); |
| 19484 | #endif |
| 19485 | |
| 19486 | #ifdef GET_RISCVVLXSEGTable_IMPL |
| 19487 | constexpr VLXSEGPseudo RISCVVLXSEGTable[] = { |
| 19488 | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG2EI8_V_M1_M1 }, // 0 |
| 19489 | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG2EI8_V_MF8_M1 }, // 1 |
| 19490 | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG2EI8_V_MF4_M1 }, // 2 |
| 19491 | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG2EI8_V_MF2_M1 }, // 3 |
| 19492 | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG2EI8_V_M1_M2 }, // 4 |
| 19493 | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG2EI8_V_M2_M2 }, // 5 |
| 19494 | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG2EI8_V_MF4_M2 }, // 6 |
| 19495 | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG2EI8_V_MF2_M2 }, // 7 |
| 19496 | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x0, PseudoVLUXSEG2EI8_V_M1_M4 }, // 8 |
| 19497 | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x1, PseudoVLUXSEG2EI8_V_M2_M4 }, // 9 |
| 19498 | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x2, PseudoVLUXSEG2EI8_V_M4_M4 }, // 10 |
| 19499 | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x7, PseudoVLUXSEG2EI8_V_MF2_M4 }, // 11 |
| 19500 | { 0x2, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF8 }, // 12 |
| 19501 | { 0x2, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF4 }, // 13 |
| 19502 | { 0x2, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG2EI8_V_MF4_MF4 }, // 14 |
| 19503 | { 0x2, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF2 }, // 15 |
| 19504 | { 0x2, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG2EI8_V_MF4_MF2 }, // 16 |
| 19505 | { 0x2, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG2EI8_V_MF2_MF2 }, // 17 |
| 19506 | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG2EI16_V_M1_M1 }, // 18 |
| 19507 | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG2EI16_V_M2_M1 }, // 19 |
| 19508 | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG2EI16_V_MF4_M1 }, // 20 |
| 19509 | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG2EI16_V_MF2_M1 }, // 21 |
| 19510 | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG2EI16_V_M1_M2 }, // 22 |
| 19511 | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG2EI16_V_M2_M2 }, // 23 |
| 19512 | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG2EI16_V_M4_M2 }, // 24 |
| 19513 | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG2EI16_V_MF2_M2 }, // 25 |
| 19514 | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x0, PseudoVLUXSEG2EI16_V_M1_M4 }, // 26 |
| 19515 | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x1, PseudoVLUXSEG2EI16_V_M2_M4 }, // 27 |
| 19516 | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x2, PseudoVLUXSEG2EI16_V_M4_M4 }, // 28 |
| 19517 | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x3, PseudoVLUXSEG2EI16_V_M8_M4 }, // 29 |
| 19518 | { 0x2, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF8 }, // 30 |
| 19519 | { 0x2, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF4 }, // 31 |
| 19520 | { 0x2, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG2EI16_V_MF2_MF4 }, // 32 |
| 19521 | { 0x2, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG2EI16_V_M1_MF2 }, // 33 |
| 19522 | { 0x2, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF2 }, // 34 |
| 19523 | { 0x2, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG2EI16_V_MF2_MF2 }, // 35 |
| 19524 | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG2EI32_V_M1_M1 }, // 36 |
| 19525 | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG2EI32_V_M2_M1 }, // 37 |
| 19526 | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG2EI32_V_M4_M1 }, // 38 |
| 19527 | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG2EI32_V_MF2_M1 }, // 39 |
| 19528 | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG2EI32_V_M1_M2 }, // 40 |
| 19529 | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG2EI32_V_M2_M2 }, // 41 |
| 19530 | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG2EI32_V_M4_M2 }, // 42 |
| 19531 | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG2EI32_V_M8_M2 }, // 43 |
| 19532 | { 0x2, 0x0, 0x0, 0x5, 0x2, 0x1, PseudoVLUXSEG2EI32_V_M2_M4 }, // 44 |
| 19533 | { 0x2, 0x0, 0x0, 0x5, 0x2, 0x2, PseudoVLUXSEG2EI32_V_M4_M4 }, // 45 |
| 19534 | { 0x2, 0x0, 0x0, 0x5, 0x2, 0x3, PseudoVLUXSEG2EI32_V_M8_M4 }, // 46 |
| 19535 | { 0x2, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF8 }, // 47 |
| 19536 | { 0x2, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG2EI32_V_M1_MF4 }, // 48 |
| 19537 | { 0x2, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF4 }, // 49 |
| 19538 | { 0x2, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG2EI32_V_M1_MF2 }, // 50 |
| 19539 | { 0x2, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG2EI32_V_M2_MF2 }, // 51 |
| 19540 | { 0x2, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF2 }, // 52 |
| 19541 | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG2EI64_V_M1_M1 }, // 53 |
| 19542 | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG2EI64_V_M2_M1 }, // 54 |
| 19543 | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG2EI64_V_M4_M1 }, // 55 |
| 19544 | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG2EI64_V_M8_M1 }, // 56 |
| 19545 | { 0x2, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG2EI64_V_M2_M2 }, // 57 |
| 19546 | { 0x2, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG2EI64_V_M4_M2 }, // 58 |
| 19547 | { 0x2, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG2EI64_V_M8_M2 }, // 59 |
| 19548 | { 0x2, 0x0, 0x0, 0x6, 0x2, 0x2, PseudoVLUXSEG2EI64_V_M4_M4 }, // 60 |
| 19549 | { 0x2, 0x0, 0x0, 0x6, 0x2, 0x3, PseudoVLUXSEG2EI64_V_M8_M4 }, // 61 |
| 19550 | { 0x2, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG2EI64_V_M1_MF8 }, // 62 |
| 19551 | { 0x2, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG2EI64_V_M1_MF4 }, // 63 |
| 19552 | { 0x2, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG2EI64_V_M2_MF4 }, // 64 |
| 19553 | { 0x2, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG2EI64_V_M1_MF2 }, // 65 |
| 19554 | { 0x2, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG2EI64_V_M2_MF2 }, // 66 |
| 19555 | { 0x2, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG2EI64_V_M4_MF2 }, // 67 |
| 19556 | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG2EI8_V_M1_M1 }, // 68 |
| 19557 | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG2EI8_V_MF8_M1 }, // 69 |
| 19558 | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG2EI8_V_MF4_M1 }, // 70 |
| 19559 | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG2EI8_V_MF2_M1 }, // 71 |
| 19560 | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG2EI8_V_M1_M2 }, // 72 |
| 19561 | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG2EI8_V_M2_M2 }, // 73 |
| 19562 | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG2EI8_V_MF4_M2 }, // 74 |
| 19563 | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG2EI8_V_MF2_M2 }, // 75 |
| 19564 | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x0, PseudoVLOXSEG2EI8_V_M1_M4 }, // 76 |
| 19565 | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x1, PseudoVLOXSEG2EI8_V_M2_M4 }, // 77 |
| 19566 | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x2, PseudoVLOXSEG2EI8_V_M4_M4 }, // 78 |
| 19567 | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x7, PseudoVLOXSEG2EI8_V_MF2_M4 }, // 79 |
| 19568 | { 0x2, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF8 }, // 80 |
| 19569 | { 0x2, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF4 }, // 81 |
| 19570 | { 0x2, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG2EI8_V_MF4_MF4 }, // 82 |
| 19571 | { 0x2, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF2 }, // 83 |
| 19572 | { 0x2, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG2EI8_V_MF4_MF2 }, // 84 |
| 19573 | { 0x2, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG2EI8_V_MF2_MF2 }, // 85 |
| 19574 | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG2EI16_V_M1_M1 }, // 86 |
| 19575 | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG2EI16_V_M2_M1 }, // 87 |
| 19576 | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG2EI16_V_MF4_M1 }, // 88 |
| 19577 | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG2EI16_V_MF2_M1 }, // 89 |
| 19578 | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG2EI16_V_M1_M2 }, // 90 |
| 19579 | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG2EI16_V_M2_M2 }, // 91 |
| 19580 | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG2EI16_V_M4_M2 }, // 92 |
| 19581 | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG2EI16_V_MF2_M2 }, // 93 |
| 19582 | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x0, PseudoVLOXSEG2EI16_V_M1_M4 }, // 94 |
| 19583 | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x1, PseudoVLOXSEG2EI16_V_M2_M4 }, // 95 |
| 19584 | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x2, PseudoVLOXSEG2EI16_V_M4_M4 }, // 96 |
| 19585 | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x3, PseudoVLOXSEG2EI16_V_M8_M4 }, // 97 |
| 19586 | { 0x2, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF8 }, // 98 |
| 19587 | { 0x2, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF4 }, // 99 |
| 19588 | { 0x2, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG2EI16_V_MF2_MF4 }, // 100 |
| 19589 | { 0x2, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG2EI16_V_M1_MF2 }, // 101 |
| 19590 | { 0x2, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF2 }, // 102 |
| 19591 | { 0x2, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG2EI16_V_MF2_MF2 }, // 103 |
| 19592 | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG2EI32_V_M1_M1 }, // 104 |
| 19593 | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG2EI32_V_M2_M1 }, // 105 |
| 19594 | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG2EI32_V_M4_M1 }, // 106 |
| 19595 | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG2EI32_V_MF2_M1 }, // 107 |
| 19596 | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG2EI32_V_M1_M2 }, // 108 |
| 19597 | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG2EI32_V_M2_M2 }, // 109 |
| 19598 | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG2EI32_V_M4_M2 }, // 110 |
| 19599 | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG2EI32_V_M8_M2 }, // 111 |
| 19600 | { 0x2, 0x0, 0x1, 0x5, 0x2, 0x1, PseudoVLOXSEG2EI32_V_M2_M4 }, // 112 |
| 19601 | { 0x2, 0x0, 0x1, 0x5, 0x2, 0x2, PseudoVLOXSEG2EI32_V_M4_M4 }, // 113 |
| 19602 | { 0x2, 0x0, 0x1, 0x5, 0x2, 0x3, PseudoVLOXSEG2EI32_V_M8_M4 }, // 114 |
| 19603 | { 0x2, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF8 }, // 115 |
| 19604 | { 0x2, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG2EI32_V_M1_MF4 }, // 116 |
| 19605 | { 0x2, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF4 }, // 117 |
| 19606 | { 0x2, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG2EI32_V_M1_MF2 }, // 118 |
| 19607 | { 0x2, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG2EI32_V_M2_MF2 }, // 119 |
| 19608 | { 0x2, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF2 }, // 120 |
| 19609 | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG2EI64_V_M1_M1 }, // 121 |
| 19610 | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG2EI64_V_M2_M1 }, // 122 |
| 19611 | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG2EI64_V_M4_M1 }, // 123 |
| 19612 | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG2EI64_V_M8_M1 }, // 124 |
| 19613 | { 0x2, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG2EI64_V_M2_M2 }, // 125 |
| 19614 | { 0x2, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG2EI64_V_M4_M2 }, // 126 |
| 19615 | { 0x2, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG2EI64_V_M8_M2 }, // 127 |
| 19616 | { 0x2, 0x0, 0x1, 0x6, 0x2, 0x2, PseudoVLOXSEG2EI64_V_M4_M4 }, // 128 |
| 19617 | { 0x2, 0x0, 0x1, 0x6, 0x2, 0x3, PseudoVLOXSEG2EI64_V_M8_M4 }, // 129 |
| 19618 | { 0x2, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG2EI64_V_M1_MF8 }, // 130 |
| 19619 | { 0x2, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG2EI64_V_M1_MF4 }, // 131 |
| 19620 | { 0x2, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG2EI64_V_M2_MF4 }, // 132 |
| 19621 | { 0x2, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG2EI64_V_M1_MF2 }, // 133 |
| 19622 | { 0x2, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG2EI64_V_M2_MF2 }, // 134 |
| 19623 | { 0x2, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG2EI64_V_M4_MF2 }, // 135 |
| 19624 | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG2EI8_V_M1_M1_MASK }, // 136 |
| 19625 | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG2EI8_V_MF8_M1_MASK }, // 137 |
| 19626 | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG2EI8_V_MF4_M1_MASK }, // 138 |
| 19627 | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG2EI8_V_MF2_M1_MASK }, // 139 |
| 19628 | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG2EI8_V_M1_M2_MASK }, // 140 |
| 19629 | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG2EI8_V_M2_M2_MASK }, // 141 |
| 19630 | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG2EI8_V_MF4_M2_MASK }, // 142 |
| 19631 | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG2EI8_V_MF2_M2_MASK }, // 143 |
| 19632 | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x0, PseudoVLUXSEG2EI8_V_M1_M4_MASK }, // 144 |
| 19633 | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x1, PseudoVLUXSEG2EI8_V_M2_M4_MASK }, // 145 |
| 19634 | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x2, PseudoVLUXSEG2EI8_V_M4_M4_MASK }, // 146 |
| 19635 | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x7, PseudoVLUXSEG2EI8_V_MF2_M4_MASK }, // 147 |
| 19636 | { 0x2, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF8_MASK }, // 148 |
| 19637 | { 0x2, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF4_MASK }, // 149 |
| 19638 | { 0x2, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG2EI8_V_MF4_MF4_MASK }, // 150 |
| 19639 | { 0x2, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF2_MASK }, // 151 |
| 19640 | { 0x2, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG2EI8_V_MF4_MF2_MASK }, // 152 |
| 19641 | { 0x2, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG2EI8_V_MF2_MF2_MASK }, // 153 |
| 19642 | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG2EI16_V_M1_M1_MASK }, // 154 |
| 19643 | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG2EI16_V_M2_M1_MASK }, // 155 |
| 19644 | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG2EI16_V_MF4_M1_MASK }, // 156 |
| 19645 | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG2EI16_V_MF2_M1_MASK }, // 157 |
| 19646 | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG2EI16_V_M1_M2_MASK }, // 158 |
| 19647 | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG2EI16_V_M2_M2_MASK }, // 159 |
| 19648 | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG2EI16_V_M4_M2_MASK }, // 160 |
| 19649 | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG2EI16_V_MF2_M2_MASK }, // 161 |
| 19650 | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x0, PseudoVLUXSEG2EI16_V_M1_M4_MASK }, // 162 |
| 19651 | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x1, PseudoVLUXSEG2EI16_V_M2_M4_MASK }, // 163 |
| 19652 | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x2, PseudoVLUXSEG2EI16_V_M4_M4_MASK }, // 164 |
| 19653 | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x3, PseudoVLUXSEG2EI16_V_M8_M4_MASK }, // 165 |
| 19654 | { 0x2, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF8_MASK }, // 166 |
| 19655 | { 0x2, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF4_MASK }, // 167 |
| 19656 | { 0x2, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG2EI16_V_MF2_MF4_MASK }, // 168 |
| 19657 | { 0x2, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG2EI16_V_M1_MF2_MASK }, // 169 |
| 19658 | { 0x2, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF2_MASK }, // 170 |
| 19659 | { 0x2, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG2EI16_V_MF2_MF2_MASK }, // 171 |
| 19660 | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG2EI32_V_M1_M1_MASK }, // 172 |
| 19661 | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG2EI32_V_M2_M1_MASK }, // 173 |
| 19662 | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG2EI32_V_M4_M1_MASK }, // 174 |
| 19663 | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG2EI32_V_MF2_M1_MASK }, // 175 |
| 19664 | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG2EI32_V_M1_M2_MASK }, // 176 |
| 19665 | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG2EI32_V_M2_M2_MASK }, // 177 |
| 19666 | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG2EI32_V_M4_M2_MASK }, // 178 |
| 19667 | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG2EI32_V_M8_M2_MASK }, // 179 |
| 19668 | { 0x2, 0x1, 0x0, 0x5, 0x2, 0x1, PseudoVLUXSEG2EI32_V_M2_M4_MASK }, // 180 |
| 19669 | { 0x2, 0x1, 0x0, 0x5, 0x2, 0x2, PseudoVLUXSEG2EI32_V_M4_M4_MASK }, // 181 |
| 19670 | { 0x2, 0x1, 0x0, 0x5, 0x2, 0x3, PseudoVLUXSEG2EI32_V_M8_M4_MASK }, // 182 |
| 19671 | { 0x2, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF8_MASK }, // 183 |
| 19672 | { 0x2, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG2EI32_V_M1_MF4_MASK }, // 184 |
| 19673 | { 0x2, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF4_MASK }, // 185 |
| 19674 | { 0x2, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG2EI32_V_M1_MF2_MASK }, // 186 |
| 19675 | { 0x2, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG2EI32_V_M2_MF2_MASK }, // 187 |
| 19676 | { 0x2, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF2_MASK }, // 188 |
| 19677 | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG2EI64_V_M1_M1_MASK }, // 189 |
| 19678 | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG2EI64_V_M2_M1_MASK }, // 190 |
| 19679 | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG2EI64_V_M4_M1_MASK }, // 191 |
| 19680 | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG2EI64_V_M8_M1_MASK }, // 192 |
| 19681 | { 0x2, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG2EI64_V_M2_M2_MASK }, // 193 |
| 19682 | { 0x2, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG2EI64_V_M4_M2_MASK }, // 194 |
| 19683 | { 0x2, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG2EI64_V_M8_M2_MASK }, // 195 |
| 19684 | { 0x2, 0x1, 0x0, 0x6, 0x2, 0x2, PseudoVLUXSEG2EI64_V_M4_M4_MASK }, // 196 |
| 19685 | { 0x2, 0x1, 0x0, 0x6, 0x2, 0x3, PseudoVLUXSEG2EI64_V_M8_M4_MASK }, // 197 |
| 19686 | { 0x2, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG2EI64_V_M1_MF8_MASK }, // 198 |
| 19687 | { 0x2, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG2EI64_V_M1_MF4_MASK }, // 199 |
| 19688 | { 0x2, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG2EI64_V_M2_MF4_MASK }, // 200 |
| 19689 | { 0x2, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG2EI64_V_M1_MF2_MASK }, // 201 |
| 19690 | { 0x2, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG2EI64_V_M2_MF2_MASK }, // 202 |
| 19691 | { 0x2, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG2EI64_V_M4_MF2_MASK }, // 203 |
| 19692 | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG2EI8_V_M1_M1_MASK }, // 204 |
| 19693 | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG2EI8_V_MF8_M1_MASK }, // 205 |
| 19694 | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG2EI8_V_MF4_M1_MASK }, // 206 |
| 19695 | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG2EI8_V_MF2_M1_MASK }, // 207 |
| 19696 | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG2EI8_V_M1_M2_MASK }, // 208 |
| 19697 | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG2EI8_V_M2_M2_MASK }, // 209 |
| 19698 | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG2EI8_V_MF4_M2_MASK }, // 210 |
| 19699 | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG2EI8_V_MF2_M2_MASK }, // 211 |
| 19700 | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x0, PseudoVLOXSEG2EI8_V_M1_M4_MASK }, // 212 |
| 19701 | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x1, PseudoVLOXSEG2EI8_V_M2_M4_MASK }, // 213 |
| 19702 | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x2, PseudoVLOXSEG2EI8_V_M4_M4_MASK }, // 214 |
| 19703 | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x7, PseudoVLOXSEG2EI8_V_MF2_M4_MASK }, // 215 |
| 19704 | { 0x2, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF8_MASK }, // 216 |
| 19705 | { 0x2, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF4_MASK }, // 217 |
| 19706 | { 0x2, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG2EI8_V_MF4_MF4_MASK }, // 218 |
| 19707 | { 0x2, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF2_MASK }, // 219 |
| 19708 | { 0x2, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG2EI8_V_MF4_MF2_MASK }, // 220 |
| 19709 | { 0x2, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG2EI8_V_MF2_MF2_MASK }, // 221 |
| 19710 | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG2EI16_V_M1_M1_MASK }, // 222 |
| 19711 | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG2EI16_V_M2_M1_MASK }, // 223 |
| 19712 | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG2EI16_V_MF4_M1_MASK }, // 224 |
| 19713 | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG2EI16_V_MF2_M1_MASK }, // 225 |
| 19714 | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG2EI16_V_M1_M2_MASK }, // 226 |
| 19715 | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG2EI16_V_M2_M2_MASK }, // 227 |
| 19716 | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG2EI16_V_M4_M2_MASK }, // 228 |
| 19717 | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG2EI16_V_MF2_M2_MASK }, // 229 |
| 19718 | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x0, PseudoVLOXSEG2EI16_V_M1_M4_MASK }, // 230 |
| 19719 | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x1, PseudoVLOXSEG2EI16_V_M2_M4_MASK }, // 231 |
| 19720 | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x2, PseudoVLOXSEG2EI16_V_M4_M4_MASK }, // 232 |
| 19721 | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x3, PseudoVLOXSEG2EI16_V_M8_M4_MASK }, // 233 |
| 19722 | { 0x2, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF8_MASK }, // 234 |
| 19723 | { 0x2, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF4_MASK }, // 235 |
| 19724 | { 0x2, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG2EI16_V_MF2_MF4_MASK }, // 236 |
| 19725 | { 0x2, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG2EI16_V_M1_MF2_MASK }, // 237 |
| 19726 | { 0x2, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF2_MASK }, // 238 |
| 19727 | { 0x2, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG2EI16_V_MF2_MF2_MASK }, // 239 |
| 19728 | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG2EI32_V_M1_M1_MASK }, // 240 |
| 19729 | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG2EI32_V_M2_M1_MASK }, // 241 |
| 19730 | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG2EI32_V_M4_M1_MASK }, // 242 |
| 19731 | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG2EI32_V_MF2_M1_MASK }, // 243 |
| 19732 | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG2EI32_V_M1_M2_MASK }, // 244 |
| 19733 | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG2EI32_V_M2_M2_MASK }, // 245 |
| 19734 | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG2EI32_V_M4_M2_MASK }, // 246 |
| 19735 | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG2EI32_V_M8_M2_MASK }, // 247 |
| 19736 | { 0x2, 0x1, 0x1, 0x5, 0x2, 0x1, PseudoVLOXSEG2EI32_V_M2_M4_MASK }, // 248 |
| 19737 | { 0x2, 0x1, 0x1, 0x5, 0x2, 0x2, PseudoVLOXSEG2EI32_V_M4_M4_MASK }, // 249 |
| 19738 | { 0x2, 0x1, 0x1, 0x5, 0x2, 0x3, PseudoVLOXSEG2EI32_V_M8_M4_MASK }, // 250 |
| 19739 | { 0x2, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF8_MASK }, // 251 |
| 19740 | { 0x2, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG2EI32_V_M1_MF4_MASK }, // 252 |
| 19741 | { 0x2, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF4_MASK }, // 253 |
| 19742 | { 0x2, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG2EI32_V_M1_MF2_MASK }, // 254 |
| 19743 | { 0x2, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG2EI32_V_M2_MF2_MASK }, // 255 |
| 19744 | { 0x2, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF2_MASK }, // 256 |
| 19745 | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG2EI64_V_M1_M1_MASK }, // 257 |
| 19746 | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG2EI64_V_M2_M1_MASK }, // 258 |
| 19747 | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG2EI64_V_M4_M1_MASK }, // 259 |
| 19748 | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG2EI64_V_M8_M1_MASK }, // 260 |
| 19749 | { 0x2, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG2EI64_V_M2_M2_MASK }, // 261 |
| 19750 | { 0x2, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG2EI64_V_M4_M2_MASK }, // 262 |
| 19751 | { 0x2, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG2EI64_V_M8_M2_MASK }, // 263 |
| 19752 | { 0x2, 0x1, 0x1, 0x6, 0x2, 0x2, PseudoVLOXSEG2EI64_V_M4_M4_MASK }, // 264 |
| 19753 | { 0x2, 0x1, 0x1, 0x6, 0x2, 0x3, PseudoVLOXSEG2EI64_V_M8_M4_MASK }, // 265 |
| 19754 | { 0x2, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG2EI64_V_M1_MF8_MASK }, // 266 |
| 19755 | { 0x2, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG2EI64_V_M1_MF4_MASK }, // 267 |
| 19756 | { 0x2, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG2EI64_V_M2_MF4_MASK }, // 268 |
| 19757 | { 0x2, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG2EI64_V_M1_MF2_MASK }, // 269 |
| 19758 | { 0x2, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG2EI64_V_M2_MF2_MASK }, // 270 |
| 19759 | { 0x2, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG2EI64_V_M4_MF2_MASK }, // 271 |
| 19760 | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG3EI8_V_M1_M1 }, // 272 |
| 19761 | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG3EI8_V_MF8_M1 }, // 273 |
| 19762 | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG3EI8_V_MF4_M1 }, // 274 |
| 19763 | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG3EI8_V_MF2_M1 }, // 275 |
| 19764 | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG3EI8_V_M1_M2 }, // 276 |
| 19765 | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG3EI8_V_M2_M2 }, // 277 |
| 19766 | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG3EI8_V_MF4_M2 }, // 278 |
| 19767 | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG3EI8_V_MF2_M2 }, // 279 |
| 19768 | { 0x3, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF8 }, // 280 |
| 19769 | { 0x3, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF4 }, // 281 |
| 19770 | { 0x3, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG3EI8_V_MF4_MF4 }, // 282 |
| 19771 | { 0x3, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF2 }, // 283 |
| 19772 | { 0x3, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG3EI8_V_MF4_MF2 }, // 284 |
| 19773 | { 0x3, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG3EI8_V_MF2_MF2 }, // 285 |
| 19774 | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG3EI16_V_M1_M1 }, // 286 |
| 19775 | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG3EI16_V_M2_M1 }, // 287 |
| 19776 | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG3EI16_V_MF4_M1 }, // 288 |
| 19777 | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG3EI16_V_MF2_M1 }, // 289 |
| 19778 | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG3EI16_V_M1_M2 }, // 290 |
| 19779 | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG3EI16_V_M2_M2 }, // 291 |
| 19780 | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG3EI16_V_M4_M2 }, // 292 |
| 19781 | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG3EI16_V_MF2_M2 }, // 293 |
| 19782 | { 0x3, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF8 }, // 294 |
| 19783 | { 0x3, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF4 }, // 295 |
| 19784 | { 0x3, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG3EI16_V_MF2_MF4 }, // 296 |
| 19785 | { 0x3, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG3EI16_V_M1_MF2 }, // 297 |
| 19786 | { 0x3, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF2 }, // 298 |
| 19787 | { 0x3, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG3EI16_V_MF2_MF2 }, // 299 |
| 19788 | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG3EI32_V_M1_M1 }, // 300 |
| 19789 | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG3EI32_V_M2_M1 }, // 301 |
| 19790 | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG3EI32_V_M4_M1 }, // 302 |
| 19791 | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG3EI32_V_MF2_M1 }, // 303 |
| 19792 | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG3EI32_V_M1_M2 }, // 304 |
| 19793 | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG3EI32_V_M2_M2 }, // 305 |
| 19794 | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG3EI32_V_M4_M2 }, // 306 |
| 19795 | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG3EI32_V_M8_M2 }, // 307 |
| 19796 | { 0x3, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF8 }, // 308 |
| 19797 | { 0x3, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG3EI32_V_M1_MF4 }, // 309 |
| 19798 | { 0x3, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF4 }, // 310 |
| 19799 | { 0x3, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG3EI32_V_M1_MF2 }, // 311 |
| 19800 | { 0x3, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG3EI32_V_M2_MF2 }, // 312 |
| 19801 | { 0x3, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF2 }, // 313 |
| 19802 | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG3EI64_V_M1_M1 }, // 314 |
| 19803 | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG3EI64_V_M2_M1 }, // 315 |
| 19804 | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG3EI64_V_M4_M1 }, // 316 |
| 19805 | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG3EI64_V_M8_M1 }, // 317 |
| 19806 | { 0x3, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG3EI64_V_M2_M2 }, // 318 |
| 19807 | { 0x3, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG3EI64_V_M4_M2 }, // 319 |
| 19808 | { 0x3, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG3EI64_V_M8_M2 }, // 320 |
| 19809 | { 0x3, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG3EI64_V_M1_MF8 }, // 321 |
| 19810 | { 0x3, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG3EI64_V_M1_MF4 }, // 322 |
| 19811 | { 0x3, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG3EI64_V_M2_MF4 }, // 323 |
| 19812 | { 0x3, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG3EI64_V_M1_MF2 }, // 324 |
| 19813 | { 0x3, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG3EI64_V_M2_MF2 }, // 325 |
| 19814 | { 0x3, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG3EI64_V_M4_MF2 }, // 326 |
| 19815 | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG3EI8_V_M1_M1 }, // 327 |
| 19816 | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG3EI8_V_MF8_M1 }, // 328 |
| 19817 | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG3EI8_V_MF4_M1 }, // 329 |
| 19818 | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG3EI8_V_MF2_M1 }, // 330 |
| 19819 | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG3EI8_V_M1_M2 }, // 331 |
| 19820 | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG3EI8_V_M2_M2 }, // 332 |
| 19821 | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG3EI8_V_MF4_M2 }, // 333 |
| 19822 | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG3EI8_V_MF2_M2 }, // 334 |
| 19823 | { 0x3, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF8 }, // 335 |
| 19824 | { 0x3, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF4 }, // 336 |
| 19825 | { 0x3, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG3EI8_V_MF4_MF4 }, // 337 |
| 19826 | { 0x3, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF2 }, // 338 |
| 19827 | { 0x3, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG3EI8_V_MF4_MF2 }, // 339 |
| 19828 | { 0x3, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG3EI8_V_MF2_MF2 }, // 340 |
| 19829 | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG3EI16_V_M1_M1 }, // 341 |
| 19830 | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG3EI16_V_M2_M1 }, // 342 |
| 19831 | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG3EI16_V_MF4_M1 }, // 343 |
| 19832 | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG3EI16_V_MF2_M1 }, // 344 |
| 19833 | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG3EI16_V_M1_M2 }, // 345 |
| 19834 | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG3EI16_V_M2_M2 }, // 346 |
| 19835 | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG3EI16_V_M4_M2 }, // 347 |
| 19836 | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG3EI16_V_MF2_M2 }, // 348 |
| 19837 | { 0x3, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF8 }, // 349 |
| 19838 | { 0x3, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF4 }, // 350 |
| 19839 | { 0x3, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG3EI16_V_MF2_MF4 }, // 351 |
| 19840 | { 0x3, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG3EI16_V_M1_MF2 }, // 352 |
| 19841 | { 0x3, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF2 }, // 353 |
| 19842 | { 0x3, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG3EI16_V_MF2_MF2 }, // 354 |
| 19843 | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG3EI32_V_M1_M1 }, // 355 |
| 19844 | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG3EI32_V_M2_M1 }, // 356 |
| 19845 | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG3EI32_V_M4_M1 }, // 357 |
| 19846 | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG3EI32_V_MF2_M1 }, // 358 |
| 19847 | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG3EI32_V_M1_M2 }, // 359 |
| 19848 | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG3EI32_V_M2_M2 }, // 360 |
| 19849 | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG3EI32_V_M4_M2 }, // 361 |
| 19850 | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG3EI32_V_M8_M2 }, // 362 |
| 19851 | { 0x3, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF8 }, // 363 |
| 19852 | { 0x3, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG3EI32_V_M1_MF4 }, // 364 |
| 19853 | { 0x3, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF4 }, // 365 |
| 19854 | { 0x3, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG3EI32_V_M1_MF2 }, // 366 |
| 19855 | { 0x3, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG3EI32_V_M2_MF2 }, // 367 |
| 19856 | { 0x3, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF2 }, // 368 |
| 19857 | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG3EI64_V_M1_M1 }, // 369 |
| 19858 | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG3EI64_V_M2_M1 }, // 370 |
| 19859 | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG3EI64_V_M4_M1 }, // 371 |
| 19860 | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG3EI64_V_M8_M1 }, // 372 |
| 19861 | { 0x3, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG3EI64_V_M2_M2 }, // 373 |
| 19862 | { 0x3, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG3EI64_V_M4_M2 }, // 374 |
| 19863 | { 0x3, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG3EI64_V_M8_M2 }, // 375 |
| 19864 | { 0x3, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG3EI64_V_M1_MF8 }, // 376 |
| 19865 | { 0x3, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG3EI64_V_M1_MF4 }, // 377 |
| 19866 | { 0x3, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG3EI64_V_M2_MF4 }, // 378 |
| 19867 | { 0x3, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG3EI64_V_M1_MF2 }, // 379 |
| 19868 | { 0x3, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG3EI64_V_M2_MF2 }, // 380 |
| 19869 | { 0x3, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG3EI64_V_M4_MF2 }, // 381 |
| 19870 | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG3EI8_V_M1_M1_MASK }, // 382 |
| 19871 | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG3EI8_V_MF8_M1_MASK }, // 383 |
| 19872 | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG3EI8_V_MF4_M1_MASK }, // 384 |
| 19873 | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG3EI8_V_MF2_M1_MASK }, // 385 |
| 19874 | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG3EI8_V_M1_M2_MASK }, // 386 |
| 19875 | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG3EI8_V_M2_M2_MASK }, // 387 |
| 19876 | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG3EI8_V_MF4_M2_MASK }, // 388 |
| 19877 | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG3EI8_V_MF2_M2_MASK }, // 389 |
| 19878 | { 0x3, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF8_MASK }, // 390 |
| 19879 | { 0x3, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF4_MASK }, // 391 |
| 19880 | { 0x3, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG3EI8_V_MF4_MF4_MASK }, // 392 |
| 19881 | { 0x3, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF2_MASK }, // 393 |
| 19882 | { 0x3, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG3EI8_V_MF4_MF2_MASK }, // 394 |
| 19883 | { 0x3, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG3EI8_V_MF2_MF2_MASK }, // 395 |
| 19884 | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG3EI16_V_M1_M1_MASK }, // 396 |
| 19885 | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG3EI16_V_M2_M1_MASK }, // 397 |
| 19886 | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG3EI16_V_MF4_M1_MASK }, // 398 |
| 19887 | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG3EI16_V_MF2_M1_MASK }, // 399 |
| 19888 | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG3EI16_V_M1_M2_MASK }, // 400 |
| 19889 | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG3EI16_V_M2_M2_MASK }, // 401 |
| 19890 | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG3EI16_V_M4_M2_MASK }, // 402 |
| 19891 | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG3EI16_V_MF2_M2_MASK }, // 403 |
| 19892 | { 0x3, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF8_MASK }, // 404 |
| 19893 | { 0x3, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF4_MASK }, // 405 |
| 19894 | { 0x3, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG3EI16_V_MF2_MF4_MASK }, // 406 |
| 19895 | { 0x3, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG3EI16_V_M1_MF2_MASK }, // 407 |
| 19896 | { 0x3, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF2_MASK }, // 408 |
| 19897 | { 0x3, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG3EI16_V_MF2_MF2_MASK }, // 409 |
| 19898 | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG3EI32_V_M1_M1_MASK }, // 410 |
| 19899 | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG3EI32_V_M2_M1_MASK }, // 411 |
| 19900 | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG3EI32_V_M4_M1_MASK }, // 412 |
| 19901 | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG3EI32_V_MF2_M1_MASK }, // 413 |
| 19902 | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG3EI32_V_M1_M2_MASK }, // 414 |
| 19903 | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG3EI32_V_M2_M2_MASK }, // 415 |
| 19904 | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG3EI32_V_M4_M2_MASK }, // 416 |
| 19905 | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG3EI32_V_M8_M2_MASK }, // 417 |
| 19906 | { 0x3, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF8_MASK }, // 418 |
| 19907 | { 0x3, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG3EI32_V_M1_MF4_MASK }, // 419 |
| 19908 | { 0x3, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF4_MASK }, // 420 |
| 19909 | { 0x3, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG3EI32_V_M1_MF2_MASK }, // 421 |
| 19910 | { 0x3, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG3EI32_V_M2_MF2_MASK }, // 422 |
| 19911 | { 0x3, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF2_MASK }, // 423 |
| 19912 | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG3EI64_V_M1_M1_MASK }, // 424 |
| 19913 | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG3EI64_V_M2_M1_MASK }, // 425 |
| 19914 | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG3EI64_V_M4_M1_MASK }, // 426 |
| 19915 | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG3EI64_V_M8_M1_MASK }, // 427 |
| 19916 | { 0x3, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG3EI64_V_M2_M2_MASK }, // 428 |
| 19917 | { 0x3, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG3EI64_V_M4_M2_MASK }, // 429 |
| 19918 | { 0x3, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG3EI64_V_M8_M2_MASK }, // 430 |
| 19919 | { 0x3, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG3EI64_V_M1_MF8_MASK }, // 431 |
| 19920 | { 0x3, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG3EI64_V_M1_MF4_MASK }, // 432 |
| 19921 | { 0x3, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG3EI64_V_M2_MF4_MASK }, // 433 |
| 19922 | { 0x3, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG3EI64_V_M1_MF2_MASK }, // 434 |
| 19923 | { 0x3, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG3EI64_V_M2_MF2_MASK }, // 435 |
| 19924 | { 0x3, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG3EI64_V_M4_MF2_MASK }, // 436 |
| 19925 | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG3EI8_V_M1_M1_MASK }, // 437 |
| 19926 | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG3EI8_V_MF8_M1_MASK }, // 438 |
| 19927 | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG3EI8_V_MF4_M1_MASK }, // 439 |
| 19928 | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG3EI8_V_MF2_M1_MASK }, // 440 |
| 19929 | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG3EI8_V_M1_M2_MASK }, // 441 |
| 19930 | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG3EI8_V_M2_M2_MASK }, // 442 |
| 19931 | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG3EI8_V_MF4_M2_MASK }, // 443 |
| 19932 | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG3EI8_V_MF2_M2_MASK }, // 444 |
| 19933 | { 0x3, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF8_MASK }, // 445 |
| 19934 | { 0x3, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF4_MASK }, // 446 |
| 19935 | { 0x3, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG3EI8_V_MF4_MF4_MASK }, // 447 |
| 19936 | { 0x3, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF2_MASK }, // 448 |
| 19937 | { 0x3, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG3EI8_V_MF4_MF2_MASK }, // 449 |
| 19938 | { 0x3, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG3EI8_V_MF2_MF2_MASK }, // 450 |
| 19939 | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG3EI16_V_M1_M1_MASK }, // 451 |
| 19940 | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG3EI16_V_M2_M1_MASK }, // 452 |
| 19941 | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG3EI16_V_MF4_M1_MASK }, // 453 |
| 19942 | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG3EI16_V_MF2_M1_MASK }, // 454 |
| 19943 | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG3EI16_V_M1_M2_MASK }, // 455 |
| 19944 | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG3EI16_V_M2_M2_MASK }, // 456 |
| 19945 | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG3EI16_V_M4_M2_MASK }, // 457 |
| 19946 | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG3EI16_V_MF2_M2_MASK }, // 458 |
| 19947 | { 0x3, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF8_MASK }, // 459 |
| 19948 | { 0x3, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF4_MASK }, // 460 |
| 19949 | { 0x3, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG3EI16_V_MF2_MF4_MASK }, // 461 |
| 19950 | { 0x3, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG3EI16_V_M1_MF2_MASK }, // 462 |
| 19951 | { 0x3, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF2_MASK }, // 463 |
| 19952 | { 0x3, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG3EI16_V_MF2_MF2_MASK }, // 464 |
| 19953 | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG3EI32_V_M1_M1_MASK }, // 465 |
| 19954 | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG3EI32_V_M2_M1_MASK }, // 466 |
| 19955 | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG3EI32_V_M4_M1_MASK }, // 467 |
| 19956 | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG3EI32_V_MF2_M1_MASK }, // 468 |
| 19957 | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG3EI32_V_M1_M2_MASK }, // 469 |
| 19958 | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG3EI32_V_M2_M2_MASK }, // 470 |
| 19959 | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG3EI32_V_M4_M2_MASK }, // 471 |
| 19960 | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG3EI32_V_M8_M2_MASK }, // 472 |
| 19961 | { 0x3, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF8_MASK }, // 473 |
| 19962 | { 0x3, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG3EI32_V_M1_MF4_MASK }, // 474 |
| 19963 | { 0x3, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF4_MASK }, // 475 |
| 19964 | { 0x3, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG3EI32_V_M1_MF2_MASK }, // 476 |
| 19965 | { 0x3, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG3EI32_V_M2_MF2_MASK }, // 477 |
| 19966 | { 0x3, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF2_MASK }, // 478 |
| 19967 | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG3EI64_V_M1_M1_MASK }, // 479 |
| 19968 | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG3EI64_V_M2_M1_MASK }, // 480 |
| 19969 | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG3EI64_V_M4_M1_MASK }, // 481 |
| 19970 | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG3EI64_V_M8_M1_MASK }, // 482 |
| 19971 | { 0x3, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG3EI64_V_M2_M2_MASK }, // 483 |
| 19972 | { 0x3, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG3EI64_V_M4_M2_MASK }, // 484 |
| 19973 | { 0x3, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG3EI64_V_M8_M2_MASK }, // 485 |
| 19974 | { 0x3, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG3EI64_V_M1_MF8_MASK }, // 486 |
| 19975 | { 0x3, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG3EI64_V_M1_MF4_MASK }, // 487 |
| 19976 | { 0x3, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG3EI64_V_M2_MF4_MASK }, // 488 |
| 19977 | { 0x3, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG3EI64_V_M1_MF2_MASK }, // 489 |
| 19978 | { 0x3, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG3EI64_V_M2_MF2_MASK }, // 490 |
| 19979 | { 0x3, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG3EI64_V_M4_MF2_MASK }, // 491 |
| 19980 | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG4EI8_V_M1_M1 }, // 492 |
| 19981 | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG4EI8_V_MF8_M1 }, // 493 |
| 19982 | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG4EI8_V_MF4_M1 }, // 494 |
| 19983 | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG4EI8_V_MF2_M1 }, // 495 |
| 19984 | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG4EI8_V_M1_M2 }, // 496 |
| 19985 | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG4EI8_V_M2_M2 }, // 497 |
| 19986 | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG4EI8_V_MF4_M2 }, // 498 |
| 19987 | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG4EI8_V_MF2_M2 }, // 499 |
| 19988 | { 0x4, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF8 }, // 500 |
| 19989 | { 0x4, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF4 }, // 501 |
| 19990 | { 0x4, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG4EI8_V_MF4_MF4 }, // 502 |
| 19991 | { 0x4, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF2 }, // 503 |
| 19992 | { 0x4, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG4EI8_V_MF4_MF2 }, // 504 |
| 19993 | { 0x4, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG4EI8_V_MF2_MF2 }, // 505 |
| 19994 | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG4EI16_V_M1_M1 }, // 506 |
| 19995 | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG4EI16_V_M2_M1 }, // 507 |
| 19996 | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG4EI16_V_MF4_M1 }, // 508 |
| 19997 | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG4EI16_V_MF2_M1 }, // 509 |
| 19998 | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG4EI16_V_M1_M2 }, // 510 |
| 19999 | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG4EI16_V_M2_M2 }, // 511 |
| 20000 | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG4EI16_V_M4_M2 }, // 512 |
| 20001 | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG4EI16_V_MF2_M2 }, // 513 |
| 20002 | { 0x4, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF8 }, // 514 |
| 20003 | { 0x4, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF4 }, // 515 |
| 20004 | { 0x4, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG4EI16_V_MF2_MF4 }, // 516 |
| 20005 | { 0x4, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG4EI16_V_M1_MF2 }, // 517 |
| 20006 | { 0x4, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF2 }, // 518 |
| 20007 | { 0x4, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG4EI16_V_MF2_MF2 }, // 519 |
| 20008 | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG4EI32_V_M1_M1 }, // 520 |
| 20009 | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG4EI32_V_M2_M1 }, // 521 |
| 20010 | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG4EI32_V_M4_M1 }, // 522 |
| 20011 | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG4EI32_V_MF2_M1 }, // 523 |
| 20012 | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG4EI32_V_M1_M2 }, // 524 |
| 20013 | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG4EI32_V_M2_M2 }, // 525 |
| 20014 | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG4EI32_V_M4_M2 }, // 526 |
| 20015 | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG4EI32_V_M8_M2 }, // 527 |
| 20016 | { 0x4, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF8 }, // 528 |
| 20017 | { 0x4, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG4EI32_V_M1_MF4 }, // 529 |
| 20018 | { 0x4, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF4 }, // 530 |
| 20019 | { 0x4, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG4EI32_V_M1_MF2 }, // 531 |
| 20020 | { 0x4, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG4EI32_V_M2_MF2 }, // 532 |
| 20021 | { 0x4, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF2 }, // 533 |
| 20022 | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG4EI64_V_M1_M1 }, // 534 |
| 20023 | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG4EI64_V_M2_M1 }, // 535 |
| 20024 | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG4EI64_V_M4_M1 }, // 536 |
| 20025 | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG4EI64_V_M8_M1 }, // 537 |
| 20026 | { 0x4, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG4EI64_V_M2_M2 }, // 538 |
| 20027 | { 0x4, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG4EI64_V_M4_M2 }, // 539 |
| 20028 | { 0x4, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG4EI64_V_M8_M2 }, // 540 |
| 20029 | { 0x4, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG4EI64_V_M1_MF8 }, // 541 |
| 20030 | { 0x4, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG4EI64_V_M1_MF4 }, // 542 |
| 20031 | { 0x4, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG4EI64_V_M2_MF4 }, // 543 |
| 20032 | { 0x4, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG4EI64_V_M1_MF2 }, // 544 |
| 20033 | { 0x4, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG4EI64_V_M2_MF2 }, // 545 |
| 20034 | { 0x4, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG4EI64_V_M4_MF2 }, // 546 |
| 20035 | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG4EI8_V_M1_M1 }, // 547 |
| 20036 | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG4EI8_V_MF8_M1 }, // 548 |
| 20037 | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG4EI8_V_MF4_M1 }, // 549 |
| 20038 | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG4EI8_V_MF2_M1 }, // 550 |
| 20039 | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG4EI8_V_M1_M2 }, // 551 |
| 20040 | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG4EI8_V_M2_M2 }, // 552 |
| 20041 | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG4EI8_V_MF4_M2 }, // 553 |
| 20042 | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG4EI8_V_MF2_M2 }, // 554 |
| 20043 | { 0x4, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF8 }, // 555 |
| 20044 | { 0x4, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF4 }, // 556 |
| 20045 | { 0x4, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG4EI8_V_MF4_MF4 }, // 557 |
| 20046 | { 0x4, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF2 }, // 558 |
| 20047 | { 0x4, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG4EI8_V_MF4_MF2 }, // 559 |
| 20048 | { 0x4, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG4EI8_V_MF2_MF2 }, // 560 |
| 20049 | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG4EI16_V_M1_M1 }, // 561 |
| 20050 | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG4EI16_V_M2_M1 }, // 562 |
| 20051 | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG4EI16_V_MF4_M1 }, // 563 |
| 20052 | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG4EI16_V_MF2_M1 }, // 564 |
| 20053 | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG4EI16_V_M1_M2 }, // 565 |
| 20054 | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG4EI16_V_M2_M2 }, // 566 |
| 20055 | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG4EI16_V_M4_M2 }, // 567 |
| 20056 | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG4EI16_V_MF2_M2 }, // 568 |
| 20057 | { 0x4, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF8 }, // 569 |
| 20058 | { 0x4, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF4 }, // 570 |
| 20059 | { 0x4, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG4EI16_V_MF2_MF4 }, // 571 |
| 20060 | { 0x4, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG4EI16_V_M1_MF2 }, // 572 |
| 20061 | { 0x4, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF2 }, // 573 |
| 20062 | { 0x4, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG4EI16_V_MF2_MF2 }, // 574 |
| 20063 | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG4EI32_V_M1_M1 }, // 575 |
| 20064 | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG4EI32_V_M2_M1 }, // 576 |
| 20065 | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG4EI32_V_M4_M1 }, // 577 |
| 20066 | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG4EI32_V_MF2_M1 }, // 578 |
| 20067 | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG4EI32_V_M1_M2 }, // 579 |
| 20068 | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG4EI32_V_M2_M2 }, // 580 |
| 20069 | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG4EI32_V_M4_M2 }, // 581 |
| 20070 | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG4EI32_V_M8_M2 }, // 582 |
| 20071 | { 0x4, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF8 }, // 583 |
| 20072 | { 0x4, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG4EI32_V_M1_MF4 }, // 584 |
| 20073 | { 0x4, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF4 }, // 585 |
| 20074 | { 0x4, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG4EI32_V_M1_MF2 }, // 586 |
| 20075 | { 0x4, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG4EI32_V_M2_MF2 }, // 587 |
| 20076 | { 0x4, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF2 }, // 588 |
| 20077 | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG4EI64_V_M1_M1 }, // 589 |
| 20078 | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG4EI64_V_M2_M1 }, // 590 |
| 20079 | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG4EI64_V_M4_M1 }, // 591 |
| 20080 | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG4EI64_V_M8_M1 }, // 592 |
| 20081 | { 0x4, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG4EI64_V_M2_M2 }, // 593 |
| 20082 | { 0x4, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG4EI64_V_M4_M2 }, // 594 |
| 20083 | { 0x4, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG4EI64_V_M8_M2 }, // 595 |
| 20084 | { 0x4, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG4EI64_V_M1_MF8 }, // 596 |
| 20085 | { 0x4, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG4EI64_V_M1_MF4 }, // 597 |
| 20086 | { 0x4, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG4EI64_V_M2_MF4 }, // 598 |
| 20087 | { 0x4, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG4EI64_V_M1_MF2 }, // 599 |
| 20088 | { 0x4, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG4EI64_V_M2_MF2 }, // 600 |
| 20089 | { 0x4, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG4EI64_V_M4_MF2 }, // 601 |
| 20090 | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG4EI8_V_M1_M1_MASK }, // 602 |
| 20091 | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG4EI8_V_MF8_M1_MASK }, // 603 |
| 20092 | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG4EI8_V_MF4_M1_MASK }, // 604 |
| 20093 | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG4EI8_V_MF2_M1_MASK }, // 605 |
| 20094 | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG4EI8_V_M1_M2_MASK }, // 606 |
| 20095 | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG4EI8_V_M2_M2_MASK }, // 607 |
| 20096 | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG4EI8_V_MF4_M2_MASK }, // 608 |
| 20097 | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG4EI8_V_MF2_M2_MASK }, // 609 |
| 20098 | { 0x4, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF8_MASK }, // 610 |
| 20099 | { 0x4, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF4_MASK }, // 611 |
| 20100 | { 0x4, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG4EI8_V_MF4_MF4_MASK }, // 612 |
| 20101 | { 0x4, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF2_MASK }, // 613 |
| 20102 | { 0x4, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG4EI8_V_MF4_MF2_MASK }, // 614 |
| 20103 | { 0x4, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG4EI8_V_MF2_MF2_MASK }, // 615 |
| 20104 | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG4EI16_V_M1_M1_MASK }, // 616 |
| 20105 | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG4EI16_V_M2_M1_MASK }, // 617 |
| 20106 | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG4EI16_V_MF4_M1_MASK }, // 618 |
| 20107 | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG4EI16_V_MF2_M1_MASK }, // 619 |
| 20108 | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG4EI16_V_M1_M2_MASK }, // 620 |
| 20109 | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG4EI16_V_M2_M2_MASK }, // 621 |
| 20110 | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG4EI16_V_M4_M2_MASK }, // 622 |
| 20111 | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG4EI16_V_MF2_M2_MASK }, // 623 |
| 20112 | { 0x4, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF8_MASK }, // 624 |
| 20113 | { 0x4, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF4_MASK }, // 625 |
| 20114 | { 0x4, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG4EI16_V_MF2_MF4_MASK }, // 626 |
| 20115 | { 0x4, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG4EI16_V_M1_MF2_MASK }, // 627 |
| 20116 | { 0x4, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF2_MASK }, // 628 |
| 20117 | { 0x4, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG4EI16_V_MF2_MF2_MASK }, // 629 |
| 20118 | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG4EI32_V_M1_M1_MASK }, // 630 |
| 20119 | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG4EI32_V_M2_M1_MASK }, // 631 |
| 20120 | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG4EI32_V_M4_M1_MASK }, // 632 |
| 20121 | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG4EI32_V_MF2_M1_MASK }, // 633 |
| 20122 | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG4EI32_V_M1_M2_MASK }, // 634 |
| 20123 | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG4EI32_V_M2_M2_MASK }, // 635 |
| 20124 | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG4EI32_V_M4_M2_MASK }, // 636 |
| 20125 | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG4EI32_V_M8_M2_MASK }, // 637 |
| 20126 | { 0x4, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF8_MASK }, // 638 |
| 20127 | { 0x4, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG4EI32_V_M1_MF4_MASK }, // 639 |
| 20128 | { 0x4, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF4_MASK }, // 640 |
| 20129 | { 0x4, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG4EI32_V_M1_MF2_MASK }, // 641 |
| 20130 | { 0x4, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG4EI32_V_M2_MF2_MASK }, // 642 |
| 20131 | { 0x4, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF2_MASK }, // 643 |
| 20132 | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG4EI64_V_M1_M1_MASK }, // 644 |
| 20133 | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG4EI64_V_M2_M1_MASK }, // 645 |
| 20134 | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG4EI64_V_M4_M1_MASK }, // 646 |
| 20135 | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG4EI64_V_M8_M1_MASK }, // 647 |
| 20136 | { 0x4, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG4EI64_V_M2_M2_MASK }, // 648 |
| 20137 | { 0x4, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG4EI64_V_M4_M2_MASK }, // 649 |
| 20138 | { 0x4, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG4EI64_V_M8_M2_MASK }, // 650 |
| 20139 | { 0x4, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG4EI64_V_M1_MF8_MASK }, // 651 |
| 20140 | { 0x4, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG4EI64_V_M1_MF4_MASK }, // 652 |
| 20141 | { 0x4, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG4EI64_V_M2_MF4_MASK }, // 653 |
| 20142 | { 0x4, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG4EI64_V_M1_MF2_MASK }, // 654 |
| 20143 | { 0x4, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG4EI64_V_M2_MF2_MASK }, // 655 |
| 20144 | { 0x4, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG4EI64_V_M4_MF2_MASK }, // 656 |
| 20145 | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG4EI8_V_M1_M1_MASK }, // 657 |
| 20146 | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG4EI8_V_MF8_M1_MASK }, // 658 |
| 20147 | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG4EI8_V_MF4_M1_MASK }, // 659 |
| 20148 | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG4EI8_V_MF2_M1_MASK }, // 660 |
| 20149 | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG4EI8_V_M1_M2_MASK }, // 661 |
| 20150 | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG4EI8_V_M2_M2_MASK }, // 662 |
| 20151 | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG4EI8_V_MF4_M2_MASK }, // 663 |
| 20152 | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG4EI8_V_MF2_M2_MASK }, // 664 |
| 20153 | { 0x4, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF8_MASK }, // 665 |
| 20154 | { 0x4, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF4_MASK }, // 666 |
| 20155 | { 0x4, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG4EI8_V_MF4_MF4_MASK }, // 667 |
| 20156 | { 0x4, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF2_MASK }, // 668 |
| 20157 | { 0x4, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG4EI8_V_MF4_MF2_MASK }, // 669 |
| 20158 | { 0x4, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG4EI8_V_MF2_MF2_MASK }, // 670 |
| 20159 | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG4EI16_V_M1_M1_MASK }, // 671 |
| 20160 | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG4EI16_V_M2_M1_MASK }, // 672 |
| 20161 | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG4EI16_V_MF4_M1_MASK }, // 673 |
| 20162 | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG4EI16_V_MF2_M1_MASK }, // 674 |
| 20163 | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG4EI16_V_M1_M2_MASK }, // 675 |
| 20164 | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG4EI16_V_M2_M2_MASK }, // 676 |
| 20165 | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG4EI16_V_M4_M2_MASK }, // 677 |
| 20166 | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG4EI16_V_MF2_M2_MASK }, // 678 |
| 20167 | { 0x4, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF8_MASK }, // 679 |
| 20168 | { 0x4, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF4_MASK }, // 680 |
| 20169 | { 0x4, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG4EI16_V_MF2_MF4_MASK }, // 681 |
| 20170 | { 0x4, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG4EI16_V_M1_MF2_MASK }, // 682 |
| 20171 | { 0x4, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF2_MASK }, // 683 |
| 20172 | { 0x4, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG4EI16_V_MF2_MF2_MASK }, // 684 |
| 20173 | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG4EI32_V_M1_M1_MASK }, // 685 |
| 20174 | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG4EI32_V_M2_M1_MASK }, // 686 |
| 20175 | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG4EI32_V_M4_M1_MASK }, // 687 |
| 20176 | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG4EI32_V_MF2_M1_MASK }, // 688 |
| 20177 | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG4EI32_V_M1_M2_MASK }, // 689 |
| 20178 | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG4EI32_V_M2_M2_MASK }, // 690 |
| 20179 | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG4EI32_V_M4_M2_MASK }, // 691 |
| 20180 | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG4EI32_V_M8_M2_MASK }, // 692 |
| 20181 | { 0x4, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF8_MASK }, // 693 |
| 20182 | { 0x4, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG4EI32_V_M1_MF4_MASK }, // 694 |
| 20183 | { 0x4, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF4_MASK }, // 695 |
| 20184 | { 0x4, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG4EI32_V_M1_MF2_MASK }, // 696 |
| 20185 | { 0x4, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG4EI32_V_M2_MF2_MASK }, // 697 |
| 20186 | { 0x4, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF2_MASK }, // 698 |
| 20187 | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG4EI64_V_M1_M1_MASK }, // 699 |
| 20188 | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG4EI64_V_M2_M1_MASK }, // 700 |
| 20189 | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG4EI64_V_M4_M1_MASK }, // 701 |
| 20190 | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG4EI64_V_M8_M1_MASK }, // 702 |
| 20191 | { 0x4, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG4EI64_V_M2_M2_MASK }, // 703 |
| 20192 | { 0x4, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG4EI64_V_M4_M2_MASK }, // 704 |
| 20193 | { 0x4, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG4EI64_V_M8_M2_MASK }, // 705 |
| 20194 | { 0x4, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG4EI64_V_M1_MF8_MASK }, // 706 |
| 20195 | { 0x4, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG4EI64_V_M1_MF4_MASK }, // 707 |
| 20196 | { 0x4, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG4EI64_V_M2_MF4_MASK }, // 708 |
| 20197 | { 0x4, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG4EI64_V_M1_MF2_MASK }, // 709 |
| 20198 | { 0x4, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG4EI64_V_M2_MF2_MASK }, // 710 |
| 20199 | { 0x4, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG4EI64_V_M4_MF2_MASK }, // 711 |
| 20200 | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG5EI8_V_M1_M1 }, // 712 |
| 20201 | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG5EI8_V_MF8_M1 }, // 713 |
| 20202 | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG5EI8_V_MF4_M1 }, // 714 |
| 20203 | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG5EI8_V_MF2_M1 }, // 715 |
| 20204 | { 0x5, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF8 }, // 716 |
| 20205 | { 0x5, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF4 }, // 717 |
| 20206 | { 0x5, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG5EI8_V_MF4_MF4 }, // 718 |
| 20207 | { 0x5, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF2 }, // 719 |
| 20208 | { 0x5, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG5EI8_V_MF4_MF2 }, // 720 |
| 20209 | { 0x5, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG5EI8_V_MF2_MF2 }, // 721 |
| 20210 | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG5EI16_V_M1_M1 }, // 722 |
| 20211 | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG5EI16_V_M2_M1 }, // 723 |
| 20212 | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG5EI16_V_MF4_M1 }, // 724 |
| 20213 | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG5EI16_V_MF2_M1 }, // 725 |
| 20214 | { 0x5, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF8 }, // 726 |
| 20215 | { 0x5, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF4 }, // 727 |
| 20216 | { 0x5, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG5EI16_V_MF2_MF4 }, // 728 |
| 20217 | { 0x5, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG5EI16_V_M1_MF2 }, // 729 |
| 20218 | { 0x5, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF2 }, // 730 |
| 20219 | { 0x5, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG5EI16_V_MF2_MF2 }, // 731 |
| 20220 | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG5EI32_V_M1_M1 }, // 732 |
| 20221 | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG5EI32_V_M2_M1 }, // 733 |
| 20222 | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG5EI32_V_M4_M1 }, // 734 |
| 20223 | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG5EI32_V_MF2_M1 }, // 735 |
| 20224 | { 0x5, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF8 }, // 736 |
| 20225 | { 0x5, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG5EI32_V_M1_MF4 }, // 737 |
| 20226 | { 0x5, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF4 }, // 738 |
| 20227 | { 0x5, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG5EI32_V_M1_MF2 }, // 739 |
| 20228 | { 0x5, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG5EI32_V_M2_MF2 }, // 740 |
| 20229 | { 0x5, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF2 }, // 741 |
| 20230 | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG5EI64_V_M1_M1 }, // 742 |
| 20231 | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG5EI64_V_M2_M1 }, // 743 |
| 20232 | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG5EI64_V_M4_M1 }, // 744 |
| 20233 | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG5EI64_V_M8_M1 }, // 745 |
| 20234 | { 0x5, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG5EI64_V_M1_MF8 }, // 746 |
| 20235 | { 0x5, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG5EI64_V_M1_MF4 }, // 747 |
| 20236 | { 0x5, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG5EI64_V_M2_MF4 }, // 748 |
| 20237 | { 0x5, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG5EI64_V_M1_MF2 }, // 749 |
| 20238 | { 0x5, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG5EI64_V_M2_MF2 }, // 750 |
| 20239 | { 0x5, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG5EI64_V_M4_MF2 }, // 751 |
| 20240 | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG5EI8_V_M1_M1 }, // 752 |
| 20241 | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG5EI8_V_MF8_M1 }, // 753 |
| 20242 | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG5EI8_V_MF4_M1 }, // 754 |
| 20243 | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG5EI8_V_MF2_M1 }, // 755 |
| 20244 | { 0x5, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF8 }, // 756 |
| 20245 | { 0x5, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF4 }, // 757 |
| 20246 | { 0x5, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG5EI8_V_MF4_MF4 }, // 758 |
| 20247 | { 0x5, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF2 }, // 759 |
| 20248 | { 0x5, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG5EI8_V_MF4_MF2 }, // 760 |
| 20249 | { 0x5, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG5EI8_V_MF2_MF2 }, // 761 |
| 20250 | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG5EI16_V_M1_M1 }, // 762 |
| 20251 | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG5EI16_V_M2_M1 }, // 763 |
| 20252 | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG5EI16_V_MF4_M1 }, // 764 |
| 20253 | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG5EI16_V_MF2_M1 }, // 765 |
| 20254 | { 0x5, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF8 }, // 766 |
| 20255 | { 0x5, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF4 }, // 767 |
| 20256 | { 0x5, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG5EI16_V_MF2_MF4 }, // 768 |
| 20257 | { 0x5, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG5EI16_V_M1_MF2 }, // 769 |
| 20258 | { 0x5, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF2 }, // 770 |
| 20259 | { 0x5, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG5EI16_V_MF2_MF2 }, // 771 |
| 20260 | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG5EI32_V_M1_M1 }, // 772 |
| 20261 | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG5EI32_V_M2_M1 }, // 773 |
| 20262 | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG5EI32_V_M4_M1 }, // 774 |
| 20263 | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG5EI32_V_MF2_M1 }, // 775 |
| 20264 | { 0x5, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF8 }, // 776 |
| 20265 | { 0x5, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG5EI32_V_M1_MF4 }, // 777 |
| 20266 | { 0x5, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF4 }, // 778 |
| 20267 | { 0x5, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG5EI32_V_M1_MF2 }, // 779 |
| 20268 | { 0x5, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG5EI32_V_M2_MF2 }, // 780 |
| 20269 | { 0x5, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF2 }, // 781 |
| 20270 | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG5EI64_V_M1_M1 }, // 782 |
| 20271 | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG5EI64_V_M2_M1 }, // 783 |
| 20272 | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG5EI64_V_M4_M1 }, // 784 |
| 20273 | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG5EI64_V_M8_M1 }, // 785 |
| 20274 | { 0x5, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG5EI64_V_M1_MF8 }, // 786 |
| 20275 | { 0x5, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG5EI64_V_M1_MF4 }, // 787 |
| 20276 | { 0x5, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG5EI64_V_M2_MF4 }, // 788 |
| 20277 | { 0x5, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG5EI64_V_M1_MF2 }, // 789 |
| 20278 | { 0x5, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG5EI64_V_M2_MF2 }, // 790 |
| 20279 | { 0x5, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG5EI64_V_M4_MF2 }, // 791 |
| 20280 | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG5EI8_V_M1_M1_MASK }, // 792 |
| 20281 | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG5EI8_V_MF8_M1_MASK }, // 793 |
| 20282 | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG5EI8_V_MF4_M1_MASK }, // 794 |
| 20283 | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG5EI8_V_MF2_M1_MASK }, // 795 |
| 20284 | { 0x5, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF8_MASK }, // 796 |
| 20285 | { 0x5, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF4_MASK }, // 797 |
| 20286 | { 0x5, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG5EI8_V_MF4_MF4_MASK }, // 798 |
| 20287 | { 0x5, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF2_MASK }, // 799 |
| 20288 | { 0x5, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG5EI8_V_MF4_MF2_MASK }, // 800 |
| 20289 | { 0x5, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG5EI8_V_MF2_MF2_MASK }, // 801 |
| 20290 | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG5EI16_V_M1_M1_MASK }, // 802 |
| 20291 | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG5EI16_V_M2_M1_MASK }, // 803 |
| 20292 | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG5EI16_V_MF4_M1_MASK }, // 804 |
| 20293 | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG5EI16_V_MF2_M1_MASK }, // 805 |
| 20294 | { 0x5, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF8_MASK }, // 806 |
| 20295 | { 0x5, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF4_MASK }, // 807 |
| 20296 | { 0x5, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG5EI16_V_MF2_MF4_MASK }, // 808 |
| 20297 | { 0x5, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG5EI16_V_M1_MF2_MASK }, // 809 |
| 20298 | { 0x5, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF2_MASK }, // 810 |
| 20299 | { 0x5, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG5EI16_V_MF2_MF2_MASK }, // 811 |
| 20300 | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG5EI32_V_M1_M1_MASK }, // 812 |
| 20301 | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG5EI32_V_M2_M1_MASK }, // 813 |
| 20302 | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG5EI32_V_M4_M1_MASK }, // 814 |
| 20303 | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG5EI32_V_MF2_M1_MASK }, // 815 |
| 20304 | { 0x5, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF8_MASK }, // 816 |
| 20305 | { 0x5, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG5EI32_V_M1_MF4_MASK }, // 817 |
| 20306 | { 0x5, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF4_MASK }, // 818 |
| 20307 | { 0x5, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG5EI32_V_M1_MF2_MASK }, // 819 |
| 20308 | { 0x5, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG5EI32_V_M2_MF2_MASK }, // 820 |
| 20309 | { 0x5, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF2_MASK }, // 821 |
| 20310 | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG5EI64_V_M1_M1_MASK }, // 822 |
| 20311 | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG5EI64_V_M2_M1_MASK }, // 823 |
| 20312 | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG5EI64_V_M4_M1_MASK }, // 824 |
| 20313 | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG5EI64_V_M8_M1_MASK }, // 825 |
| 20314 | { 0x5, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG5EI64_V_M1_MF8_MASK }, // 826 |
| 20315 | { 0x5, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG5EI64_V_M1_MF4_MASK }, // 827 |
| 20316 | { 0x5, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG5EI64_V_M2_MF4_MASK }, // 828 |
| 20317 | { 0x5, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG5EI64_V_M1_MF2_MASK }, // 829 |
| 20318 | { 0x5, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG5EI64_V_M2_MF2_MASK }, // 830 |
| 20319 | { 0x5, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG5EI64_V_M4_MF2_MASK }, // 831 |
| 20320 | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG5EI8_V_M1_M1_MASK }, // 832 |
| 20321 | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG5EI8_V_MF8_M1_MASK }, // 833 |
| 20322 | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG5EI8_V_MF4_M1_MASK }, // 834 |
| 20323 | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG5EI8_V_MF2_M1_MASK }, // 835 |
| 20324 | { 0x5, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF8_MASK }, // 836 |
| 20325 | { 0x5, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF4_MASK }, // 837 |
| 20326 | { 0x5, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG5EI8_V_MF4_MF4_MASK }, // 838 |
| 20327 | { 0x5, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF2_MASK }, // 839 |
| 20328 | { 0x5, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG5EI8_V_MF4_MF2_MASK }, // 840 |
| 20329 | { 0x5, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG5EI8_V_MF2_MF2_MASK }, // 841 |
| 20330 | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG5EI16_V_M1_M1_MASK }, // 842 |
| 20331 | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG5EI16_V_M2_M1_MASK }, // 843 |
| 20332 | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG5EI16_V_MF4_M1_MASK }, // 844 |
| 20333 | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG5EI16_V_MF2_M1_MASK }, // 845 |
| 20334 | { 0x5, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF8_MASK }, // 846 |
| 20335 | { 0x5, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF4_MASK }, // 847 |
| 20336 | { 0x5, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG5EI16_V_MF2_MF4_MASK }, // 848 |
| 20337 | { 0x5, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG5EI16_V_M1_MF2_MASK }, // 849 |
| 20338 | { 0x5, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF2_MASK }, // 850 |
| 20339 | { 0x5, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG5EI16_V_MF2_MF2_MASK }, // 851 |
| 20340 | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG5EI32_V_M1_M1_MASK }, // 852 |
| 20341 | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG5EI32_V_M2_M1_MASK }, // 853 |
| 20342 | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG5EI32_V_M4_M1_MASK }, // 854 |
| 20343 | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG5EI32_V_MF2_M1_MASK }, // 855 |
| 20344 | { 0x5, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF8_MASK }, // 856 |
| 20345 | { 0x5, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG5EI32_V_M1_MF4_MASK }, // 857 |
| 20346 | { 0x5, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF4_MASK }, // 858 |
| 20347 | { 0x5, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG5EI32_V_M1_MF2_MASK }, // 859 |
| 20348 | { 0x5, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG5EI32_V_M2_MF2_MASK }, // 860 |
| 20349 | { 0x5, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF2_MASK }, // 861 |
| 20350 | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG5EI64_V_M1_M1_MASK }, // 862 |
| 20351 | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG5EI64_V_M2_M1_MASK }, // 863 |
| 20352 | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG5EI64_V_M4_M1_MASK }, // 864 |
| 20353 | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG5EI64_V_M8_M1_MASK }, // 865 |
| 20354 | { 0x5, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG5EI64_V_M1_MF8_MASK }, // 866 |
| 20355 | { 0x5, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG5EI64_V_M1_MF4_MASK }, // 867 |
| 20356 | { 0x5, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG5EI64_V_M2_MF4_MASK }, // 868 |
| 20357 | { 0x5, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG5EI64_V_M1_MF2_MASK }, // 869 |
| 20358 | { 0x5, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG5EI64_V_M2_MF2_MASK }, // 870 |
| 20359 | { 0x5, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG5EI64_V_M4_MF2_MASK }, // 871 |
| 20360 | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG6EI8_V_M1_M1 }, // 872 |
| 20361 | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG6EI8_V_MF8_M1 }, // 873 |
| 20362 | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG6EI8_V_MF4_M1 }, // 874 |
| 20363 | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG6EI8_V_MF2_M1 }, // 875 |
| 20364 | { 0x6, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF8 }, // 876 |
| 20365 | { 0x6, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF4 }, // 877 |
| 20366 | { 0x6, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG6EI8_V_MF4_MF4 }, // 878 |
| 20367 | { 0x6, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF2 }, // 879 |
| 20368 | { 0x6, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG6EI8_V_MF4_MF2 }, // 880 |
| 20369 | { 0x6, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG6EI8_V_MF2_MF2 }, // 881 |
| 20370 | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG6EI16_V_M1_M1 }, // 882 |
| 20371 | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG6EI16_V_M2_M1 }, // 883 |
| 20372 | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG6EI16_V_MF4_M1 }, // 884 |
| 20373 | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG6EI16_V_MF2_M1 }, // 885 |
| 20374 | { 0x6, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF8 }, // 886 |
| 20375 | { 0x6, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF4 }, // 887 |
| 20376 | { 0x6, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG6EI16_V_MF2_MF4 }, // 888 |
| 20377 | { 0x6, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG6EI16_V_M1_MF2 }, // 889 |
| 20378 | { 0x6, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF2 }, // 890 |
| 20379 | { 0x6, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG6EI16_V_MF2_MF2 }, // 891 |
| 20380 | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG6EI32_V_M1_M1 }, // 892 |
| 20381 | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG6EI32_V_M2_M1 }, // 893 |
| 20382 | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG6EI32_V_M4_M1 }, // 894 |
| 20383 | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG6EI32_V_MF2_M1 }, // 895 |
| 20384 | { 0x6, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF8 }, // 896 |
| 20385 | { 0x6, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG6EI32_V_M1_MF4 }, // 897 |
| 20386 | { 0x6, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF4 }, // 898 |
| 20387 | { 0x6, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG6EI32_V_M1_MF2 }, // 899 |
| 20388 | { 0x6, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG6EI32_V_M2_MF2 }, // 900 |
| 20389 | { 0x6, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF2 }, // 901 |
| 20390 | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG6EI64_V_M1_M1 }, // 902 |
| 20391 | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG6EI64_V_M2_M1 }, // 903 |
| 20392 | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG6EI64_V_M4_M1 }, // 904 |
| 20393 | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG6EI64_V_M8_M1 }, // 905 |
| 20394 | { 0x6, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG6EI64_V_M1_MF8 }, // 906 |
| 20395 | { 0x6, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG6EI64_V_M1_MF4 }, // 907 |
| 20396 | { 0x6, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG6EI64_V_M2_MF4 }, // 908 |
| 20397 | { 0x6, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG6EI64_V_M1_MF2 }, // 909 |
| 20398 | { 0x6, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG6EI64_V_M2_MF2 }, // 910 |
| 20399 | { 0x6, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG6EI64_V_M4_MF2 }, // 911 |
| 20400 | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG6EI8_V_M1_M1 }, // 912 |
| 20401 | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG6EI8_V_MF8_M1 }, // 913 |
| 20402 | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG6EI8_V_MF4_M1 }, // 914 |
| 20403 | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG6EI8_V_MF2_M1 }, // 915 |
| 20404 | { 0x6, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF8 }, // 916 |
| 20405 | { 0x6, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF4 }, // 917 |
| 20406 | { 0x6, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG6EI8_V_MF4_MF4 }, // 918 |
| 20407 | { 0x6, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF2 }, // 919 |
| 20408 | { 0x6, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG6EI8_V_MF4_MF2 }, // 920 |
| 20409 | { 0x6, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG6EI8_V_MF2_MF2 }, // 921 |
| 20410 | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG6EI16_V_M1_M1 }, // 922 |
| 20411 | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG6EI16_V_M2_M1 }, // 923 |
| 20412 | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG6EI16_V_MF4_M1 }, // 924 |
| 20413 | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG6EI16_V_MF2_M1 }, // 925 |
| 20414 | { 0x6, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF8 }, // 926 |
| 20415 | { 0x6, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF4 }, // 927 |
| 20416 | { 0x6, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG6EI16_V_MF2_MF4 }, // 928 |
| 20417 | { 0x6, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG6EI16_V_M1_MF2 }, // 929 |
| 20418 | { 0x6, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF2 }, // 930 |
| 20419 | { 0x6, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG6EI16_V_MF2_MF2 }, // 931 |
| 20420 | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG6EI32_V_M1_M1 }, // 932 |
| 20421 | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG6EI32_V_M2_M1 }, // 933 |
| 20422 | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG6EI32_V_M4_M1 }, // 934 |
| 20423 | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG6EI32_V_MF2_M1 }, // 935 |
| 20424 | { 0x6, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF8 }, // 936 |
| 20425 | { 0x6, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG6EI32_V_M1_MF4 }, // 937 |
| 20426 | { 0x6, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF4 }, // 938 |
| 20427 | { 0x6, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG6EI32_V_M1_MF2 }, // 939 |
| 20428 | { 0x6, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG6EI32_V_M2_MF2 }, // 940 |
| 20429 | { 0x6, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF2 }, // 941 |
| 20430 | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG6EI64_V_M1_M1 }, // 942 |
| 20431 | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG6EI64_V_M2_M1 }, // 943 |
| 20432 | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG6EI64_V_M4_M1 }, // 944 |
| 20433 | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG6EI64_V_M8_M1 }, // 945 |
| 20434 | { 0x6, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG6EI64_V_M1_MF8 }, // 946 |
| 20435 | { 0x6, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG6EI64_V_M1_MF4 }, // 947 |
| 20436 | { 0x6, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG6EI64_V_M2_MF4 }, // 948 |
| 20437 | { 0x6, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG6EI64_V_M1_MF2 }, // 949 |
| 20438 | { 0x6, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG6EI64_V_M2_MF2 }, // 950 |
| 20439 | { 0x6, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG6EI64_V_M4_MF2 }, // 951 |
| 20440 | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG6EI8_V_M1_M1_MASK }, // 952 |
| 20441 | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG6EI8_V_MF8_M1_MASK }, // 953 |
| 20442 | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG6EI8_V_MF4_M1_MASK }, // 954 |
| 20443 | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG6EI8_V_MF2_M1_MASK }, // 955 |
| 20444 | { 0x6, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF8_MASK }, // 956 |
| 20445 | { 0x6, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF4_MASK }, // 957 |
| 20446 | { 0x6, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG6EI8_V_MF4_MF4_MASK }, // 958 |
| 20447 | { 0x6, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF2_MASK }, // 959 |
| 20448 | { 0x6, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG6EI8_V_MF4_MF2_MASK }, // 960 |
| 20449 | { 0x6, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG6EI8_V_MF2_MF2_MASK }, // 961 |
| 20450 | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG6EI16_V_M1_M1_MASK }, // 962 |
| 20451 | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG6EI16_V_M2_M1_MASK }, // 963 |
| 20452 | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG6EI16_V_MF4_M1_MASK }, // 964 |
| 20453 | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG6EI16_V_MF2_M1_MASK }, // 965 |
| 20454 | { 0x6, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF8_MASK }, // 966 |
| 20455 | { 0x6, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF4_MASK }, // 967 |
| 20456 | { 0x6, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG6EI16_V_MF2_MF4_MASK }, // 968 |
| 20457 | { 0x6, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG6EI16_V_M1_MF2_MASK }, // 969 |
| 20458 | { 0x6, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF2_MASK }, // 970 |
| 20459 | { 0x6, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG6EI16_V_MF2_MF2_MASK }, // 971 |
| 20460 | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG6EI32_V_M1_M1_MASK }, // 972 |
| 20461 | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG6EI32_V_M2_M1_MASK }, // 973 |
| 20462 | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG6EI32_V_M4_M1_MASK }, // 974 |
| 20463 | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG6EI32_V_MF2_M1_MASK }, // 975 |
| 20464 | { 0x6, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF8_MASK }, // 976 |
| 20465 | { 0x6, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG6EI32_V_M1_MF4_MASK }, // 977 |
| 20466 | { 0x6, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF4_MASK }, // 978 |
| 20467 | { 0x6, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG6EI32_V_M1_MF2_MASK }, // 979 |
| 20468 | { 0x6, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG6EI32_V_M2_MF2_MASK }, // 980 |
| 20469 | { 0x6, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF2_MASK }, // 981 |
| 20470 | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG6EI64_V_M1_M1_MASK }, // 982 |
| 20471 | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG6EI64_V_M2_M1_MASK }, // 983 |
| 20472 | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG6EI64_V_M4_M1_MASK }, // 984 |
| 20473 | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG6EI64_V_M8_M1_MASK }, // 985 |
| 20474 | { 0x6, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG6EI64_V_M1_MF8_MASK }, // 986 |
| 20475 | { 0x6, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG6EI64_V_M1_MF4_MASK }, // 987 |
| 20476 | { 0x6, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG6EI64_V_M2_MF4_MASK }, // 988 |
| 20477 | { 0x6, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG6EI64_V_M1_MF2_MASK }, // 989 |
| 20478 | { 0x6, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG6EI64_V_M2_MF2_MASK }, // 990 |
| 20479 | { 0x6, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG6EI64_V_M4_MF2_MASK }, // 991 |
| 20480 | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG6EI8_V_M1_M1_MASK }, // 992 |
| 20481 | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG6EI8_V_MF8_M1_MASK }, // 993 |
| 20482 | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG6EI8_V_MF4_M1_MASK }, // 994 |
| 20483 | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG6EI8_V_MF2_M1_MASK }, // 995 |
| 20484 | { 0x6, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF8_MASK }, // 996 |
| 20485 | { 0x6, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF4_MASK }, // 997 |
| 20486 | { 0x6, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG6EI8_V_MF4_MF4_MASK }, // 998 |
| 20487 | { 0x6, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF2_MASK }, // 999 |
| 20488 | { 0x6, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG6EI8_V_MF4_MF2_MASK }, // 1000 |
| 20489 | { 0x6, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG6EI8_V_MF2_MF2_MASK }, // 1001 |
| 20490 | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG6EI16_V_M1_M1_MASK }, // 1002 |
| 20491 | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG6EI16_V_M2_M1_MASK }, // 1003 |
| 20492 | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG6EI16_V_MF4_M1_MASK }, // 1004 |
| 20493 | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG6EI16_V_MF2_M1_MASK }, // 1005 |
| 20494 | { 0x6, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF8_MASK }, // 1006 |
| 20495 | { 0x6, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF4_MASK }, // 1007 |
| 20496 | { 0x6, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG6EI16_V_MF2_MF4_MASK }, // 1008 |
| 20497 | { 0x6, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG6EI16_V_M1_MF2_MASK }, // 1009 |
| 20498 | { 0x6, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF2_MASK }, // 1010 |
| 20499 | { 0x6, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG6EI16_V_MF2_MF2_MASK }, // 1011 |
| 20500 | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG6EI32_V_M1_M1_MASK }, // 1012 |
| 20501 | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG6EI32_V_M2_M1_MASK }, // 1013 |
| 20502 | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG6EI32_V_M4_M1_MASK }, // 1014 |
| 20503 | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG6EI32_V_MF2_M1_MASK }, // 1015 |
| 20504 | { 0x6, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF8_MASK }, // 1016 |
| 20505 | { 0x6, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG6EI32_V_M1_MF4_MASK }, // 1017 |
| 20506 | { 0x6, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF4_MASK }, // 1018 |
| 20507 | { 0x6, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG6EI32_V_M1_MF2_MASK }, // 1019 |
| 20508 | { 0x6, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG6EI32_V_M2_MF2_MASK }, // 1020 |
| 20509 | { 0x6, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF2_MASK }, // 1021 |
| 20510 | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG6EI64_V_M1_M1_MASK }, // 1022 |
| 20511 | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG6EI64_V_M2_M1_MASK }, // 1023 |
| 20512 | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG6EI64_V_M4_M1_MASK }, // 1024 |
| 20513 | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG6EI64_V_M8_M1_MASK }, // 1025 |
| 20514 | { 0x6, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG6EI64_V_M1_MF8_MASK }, // 1026 |
| 20515 | { 0x6, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG6EI64_V_M1_MF4_MASK }, // 1027 |
| 20516 | { 0x6, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG6EI64_V_M2_MF4_MASK }, // 1028 |
| 20517 | { 0x6, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG6EI64_V_M1_MF2_MASK }, // 1029 |
| 20518 | { 0x6, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG6EI64_V_M2_MF2_MASK }, // 1030 |
| 20519 | { 0x6, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG6EI64_V_M4_MF2_MASK }, // 1031 |
| 20520 | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG7EI8_V_M1_M1 }, // 1032 |
| 20521 | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG7EI8_V_MF8_M1 }, // 1033 |
| 20522 | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG7EI8_V_MF4_M1 }, // 1034 |
| 20523 | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG7EI8_V_MF2_M1 }, // 1035 |
| 20524 | { 0x7, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF8 }, // 1036 |
| 20525 | { 0x7, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF4 }, // 1037 |
| 20526 | { 0x7, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG7EI8_V_MF4_MF4 }, // 1038 |
| 20527 | { 0x7, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF2 }, // 1039 |
| 20528 | { 0x7, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG7EI8_V_MF4_MF2 }, // 1040 |
| 20529 | { 0x7, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG7EI8_V_MF2_MF2 }, // 1041 |
| 20530 | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG7EI16_V_M1_M1 }, // 1042 |
| 20531 | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG7EI16_V_M2_M1 }, // 1043 |
| 20532 | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG7EI16_V_MF4_M1 }, // 1044 |
| 20533 | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG7EI16_V_MF2_M1 }, // 1045 |
| 20534 | { 0x7, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF8 }, // 1046 |
| 20535 | { 0x7, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF4 }, // 1047 |
| 20536 | { 0x7, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG7EI16_V_MF2_MF4 }, // 1048 |
| 20537 | { 0x7, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG7EI16_V_M1_MF2 }, // 1049 |
| 20538 | { 0x7, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF2 }, // 1050 |
| 20539 | { 0x7, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG7EI16_V_MF2_MF2 }, // 1051 |
| 20540 | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG7EI32_V_M1_M1 }, // 1052 |
| 20541 | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG7EI32_V_M2_M1 }, // 1053 |
| 20542 | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG7EI32_V_M4_M1 }, // 1054 |
| 20543 | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG7EI32_V_MF2_M1 }, // 1055 |
| 20544 | { 0x7, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF8 }, // 1056 |
| 20545 | { 0x7, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG7EI32_V_M1_MF4 }, // 1057 |
| 20546 | { 0x7, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF4 }, // 1058 |
| 20547 | { 0x7, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG7EI32_V_M1_MF2 }, // 1059 |
| 20548 | { 0x7, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG7EI32_V_M2_MF2 }, // 1060 |
| 20549 | { 0x7, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF2 }, // 1061 |
| 20550 | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG7EI64_V_M1_M1 }, // 1062 |
| 20551 | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG7EI64_V_M2_M1 }, // 1063 |
| 20552 | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG7EI64_V_M4_M1 }, // 1064 |
| 20553 | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG7EI64_V_M8_M1 }, // 1065 |
| 20554 | { 0x7, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG7EI64_V_M1_MF8 }, // 1066 |
| 20555 | { 0x7, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG7EI64_V_M1_MF4 }, // 1067 |
| 20556 | { 0x7, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG7EI64_V_M2_MF4 }, // 1068 |
| 20557 | { 0x7, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG7EI64_V_M1_MF2 }, // 1069 |
| 20558 | { 0x7, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG7EI64_V_M2_MF2 }, // 1070 |
| 20559 | { 0x7, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG7EI64_V_M4_MF2 }, // 1071 |
| 20560 | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG7EI8_V_M1_M1 }, // 1072 |
| 20561 | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG7EI8_V_MF8_M1 }, // 1073 |
| 20562 | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG7EI8_V_MF4_M1 }, // 1074 |
| 20563 | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG7EI8_V_MF2_M1 }, // 1075 |
| 20564 | { 0x7, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF8 }, // 1076 |
| 20565 | { 0x7, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF4 }, // 1077 |
| 20566 | { 0x7, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG7EI8_V_MF4_MF4 }, // 1078 |
| 20567 | { 0x7, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF2 }, // 1079 |
| 20568 | { 0x7, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG7EI8_V_MF4_MF2 }, // 1080 |
| 20569 | { 0x7, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG7EI8_V_MF2_MF2 }, // 1081 |
| 20570 | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG7EI16_V_M1_M1 }, // 1082 |
| 20571 | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG7EI16_V_M2_M1 }, // 1083 |
| 20572 | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG7EI16_V_MF4_M1 }, // 1084 |
| 20573 | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG7EI16_V_MF2_M1 }, // 1085 |
| 20574 | { 0x7, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF8 }, // 1086 |
| 20575 | { 0x7, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF4 }, // 1087 |
| 20576 | { 0x7, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG7EI16_V_MF2_MF4 }, // 1088 |
| 20577 | { 0x7, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG7EI16_V_M1_MF2 }, // 1089 |
| 20578 | { 0x7, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF2 }, // 1090 |
| 20579 | { 0x7, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG7EI16_V_MF2_MF2 }, // 1091 |
| 20580 | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG7EI32_V_M1_M1 }, // 1092 |
| 20581 | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG7EI32_V_M2_M1 }, // 1093 |
| 20582 | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG7EI32_V_M4_M1 }, // 1094 |
| 20583 | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG7EI32_V_MF2_M1 }, // 1095 |
| 20584 | { 0x7, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF8 }, // 1096 |
| 20585 | { 0x7, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG7EI32_V_M1_MF4 }, // 1097 |
| 20586 | { 0x7, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF4 }, // 1098 |
| 20587 | { 0x7, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG7EI32_V_M1_MF2 }, // 1099 |
| 20588 | { 0x7, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG7EI32_V_M2_MF2 }, // 1100 |
| 20589 | { 0x7, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF2 }, // 1101 |
| 20590 | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG7EI64_V_M1_M1 }, // 1102 |
| 20591 | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG7EI64_V_M2_M1 }, // 1103 |
| 20592 | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG7EI64_V_M4_M1 }, // 1104 |
| 20593 | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG7EI64_V_M8_M1 }, // 1105 |
| 20594 | { 0x7, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG7EI64_V_M1_MF8 }, // 1106 |
| 20595 | { 0x7, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG7EI64_V_M1_MF4 }, // 1107 |
| 20596 | { 0x7, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG7EI64_V_M2_MF4 }, // 1108 |
| 20597 | { 0x7, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG7EI64_V_M1_MF2 }, // 1109 |
| 20598 | { 0x7, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG7EI64_V_M2_MF2 }, // 1110 |
| 20599 | { 0x7, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG7EI64_V_M4_MF2 }, // 1111 |
| 20600 | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG7EI8_V_M1_M1_MASK }, // 1112 |
| 20601 | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG7EI8_V_MF8_M1_MASK }, // 1113 |
| 20602 | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG7EI8_V_MF4_M1_MASK }, // 1114 |
| 20603 | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG7EI8_V_MF2_M1_MASK }, // 1115 |
| 20604 | { 0x7, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF8_MASK }, // 1116 |
| 20605 | { 0x7, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF4_MASK }, // 1117 |
| 20606 | { 0x7, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG7EI8_V_MF4_MF4_MASK }, // 1118 |
| 20607 | { 0x7, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF2_MASK }, // 1119 |
| 20608 | { 0x7, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG7EI8_V_MF4_MF2_MASK }, // 1120 |
| 20609 | { 0x7, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG7EI8_V_MF2_MF2_MASK }, // 1121 |
| 20610 | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG7EI16_V_M1_M1_MASK }, // 1122 |
| 20611 | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG7EI16_V_M2_M1_MASK }, // 1123 |
| 20612 | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG7EI16_V_MF4_M1_MASK }, // 1124 |
| 20613 | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG7EI16_V_MF2_M1_MASK }, // 1125 |
| 20614 | { 0x7, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF8_MASK }, // 1126 |
| 20615 | { 0x7, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF4_MASK }, // 1127 |
| 20616 | { 0x7, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG7EI16_V_MF2_MF4_MASK }, // 1128 |
| 20617 | { 0x7, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG7EI16_V_M1_MF2_MASK }, // 1129 |
| 20618 | { 0x7, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF2_MASK }, // 1130 |
| 20619 | { 0x7, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG7EI16_V_MF2_MF2_MASK }, // 1131 |
| 20620 | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG7EI32_V_M1_M1_MASK }, // 1132 |
| 20621 | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG7EI32_V_M2_M1_MASK }, // 1133 |
| 20622 | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG7EI32_V_M4_M1_MASK }, // 1134 |
| 20623 | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG7EI32_V_MF2_M1_MASK }, // 1135 |
| 20624 | { 0x7, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF8_MASK }, // 1136 |
| 20625 | { 0x7, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG7EI32_V_M1_MF4_MASK }, // 1137 |
| 20626 | { 0x7, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF4_MASK }, // 1138 |
| 20627 | { 0x7, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG7EI32_V_M1_MF2_MASK }, // 1139 |
| 20628 | { 0x7, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG7EI32_V_M2_MF2_MASK }, // 1140 |
| 20629 | { 0x7, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF2_MASK }, // 1141 |
| 20630 | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG7EI64_V_M1_M1_MASK }, // 1142 |
| 20631 | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG7EI64_V_M2_M1_MASK }, // 1143 |
| 20632 | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG7EI64_V_M4_M1_MASK }, // 1144 |
| 20633 | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG7EI64_V_M8_M1_MASK }, // 1145 |
| 20634 | { 0x7, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG7EI64_V_M1_MF8_MASK }, // 1146 |
| 20635 | { 0x7, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG7EI64_V_M1_MF4_MASK }, // 1147 |
| 20636 | { 0x7, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG7EI64_V_M2_MF4_MASK }, // 1148 |
| 20637 | { 0x7, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG7EI64_V_M1_MF2_MASK }, // 1149 |
| 20638 | { 0x7, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG7EI64_V_M2_MF2_MASK }, // 1150 |
| 20639 | { 0x7, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG7EI64_V_M4_MF2_MASK }, // 1151 |
| 20640 | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG7EI8_V_M1_M1_MASK }, // 1152 |
| 20641 | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG7EI8_V_MF8_M1_MASK }, // 1153 |
| 20642 | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG7EI8_V_MF4_M1_MASK }, // 1154 |
| 20643 | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG7EI8_V_MF2_M1_MASK }, // 1155 |
| 20644 | { 0x7, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF8_MASK }, // 1156 |
| 20645 | { 0x7, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF4_MASK }, // 1157 |
| 20646 | { 0x7, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG7EI8_V_MF4_MF4_MASK }, // 1158 |
| 20647 | { 0x7, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF2_MASK }, // 1159 |
| 20648 | { 0x7, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG7EI8_V_MF4_MF2_MASK }, // 1160 |
| 20649 | { 0x7, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG7EI8_V_MF2_MF2_MASK }, // 1161 |
| 20650 | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG7EI16_V_M1_M1_MASK }, // 1162 |
| 20651 | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG7EI16_V_M2_M1_MASK }, // 1163 |
| 20652 | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG7EI16_V_MF4_M1_MASK }, // 1164 |
| 20653 | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG7EI16_V_MF2_M1_MASK }, // 1165 |
| 20654 | { 0x7, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF8_MASK }, // 1166 |
| 20655 | { 0x7, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF4_MASK }, // 1167 |
| 20656 | { 0x7, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG7EI16_V_MF2_MF4_MASK }, // 1168 |
| 20657 | { 0x7, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG7EI16_V_M1_MF2_MASK }, // 1169 |
| 20658 | { 0x7, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF2_MASK }, // 1170 |
| 20659 | { 0x7, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG7EI16_V_MF2_MF2_MASK }, // 1171 |
| 20660 | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG7EI32_V_M1_M1_MASK }, // 1172 |
| 20661 | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG7EI32_V_M2_M1_MASK }, // 1173 |
| 20662 | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG7EI32_V_M4_M1_MASK }, // 1174 |
| 20663 | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG7EI32_V_MF2_M1_MASK }, // 1175 |
| 20664 | { 0x7, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF8_MASK }, // 1176 |
| 20665 | { 0x7, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG7EI32_V_M1_MF4_MASK }, // 1177 |
| 20666 | { 0x7, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF4_MASK }, // 1178 |
| 20667 | { 0x7, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG7EI32_V_M1_MF2_MASK }, // 1179 |
| 20668 | { 0x7, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG7EI32_V_M2_MF2_MASK }, // 1180 |
| 20669 | { 0x7, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF2_MASK }, // 1181 |
| 20670 | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG7EI64_V_M1_M1_MASK }, // 1182 |
| 20671 | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG7EI64_V_M2_M1_MASK }, // 1183 |
| 20672 | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG7EI64_V_M4_M1_MASK }, // 1184 |
| 20673 | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG7EI64_V_M8_M1_MASK }, // 1185 |
| 20674 | { 0x7, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG7EI64_V_M1_MF8_MASK }, // 1186 |
| 20675 | { 0x7, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG7EI64_V_M1_MF4_MASK }, // 1187 |
| 20676 | { 0x7, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG7EI64_V_M2_MF4_MASK }, // 1188 |
| 20677 | { 0x7, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG7EI64_V_M1_MF2_MASK }, // 1189 |
| 20678 | { 0x7, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG7EI64_V_M2_MF2_MASK }, // 1190 |
| 20679 | { 0x7, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG7EI64_V_M4_MF2_MASK }, // 1191 |
| 20680 | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG8EI8_V_M1_M1 }, // 1192 |
| 20681 | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG8EI8_V_MF8_M1 }, // 1193 |
| 20682 | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG8EI8_V_MF4_M1 }, // 1194 |
| 20683 | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG8EI8_V_MF2_M1 }, // 1195 |
| 20684 | { 0x8, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF8 }, // 1196 |
| 20685 | { 0x8, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF4 }, // 1197 |
| 20686 | { 0x8, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG8EI8_V_MF4_MF4 }, // 1198 |
| 20687 | { 0x8, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF2 }, // 1199 |
| 20688 | { 0x8, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG8EI8_V_MF4_MF2 }, // 1200 |
| 20689 | { 0x8, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG8EI8_V_MF2_MF2 }, // 1201 |
| 20690 | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG8EI16_V_M1_M1 }, // 1202 |
| 20691 | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG8EI16_V_M2_M1 }, // 1203 |
| 20692 | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG8EI16_V_MF4_M1 }, // 1204 |
| 20693 | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG8EI16_V_MF2_M1 }, // 1205 |
| 20694 | { 0x8, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF8 }, // 1206 |
| 20695 | { 0x8, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF4 }, // 1207 |
| 20696 | { 0x8, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG8EI16_V_MF2_MF4 }, // 1208 |
| 20697 | { 0x8, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG8EI16_V_M1_MF2 }, // 1209 |
| 20698 | { 0x8, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF2 }, // 1210 |
| 20699 | { 0x8, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG8EI16_V_MF2_MF2 }, // 1211 |
| 20700 | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG8EI32_V_M1_M1 }, // 1212 |
| 20701 | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG8EI32_V_M2_M1 }, // 1213 |
| 20702 | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG8EI32_V_M4_M1 }, // 1214 |
| 20703 | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG8EI32_V_MF2_M1 }, // 1215 |
| 20704 | { 0x8, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF8 }, // 1216 |
| 20705 | { 0x8, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG8EI32_V_M1_MF4 }, // 1217 |
| 20706 | { 0x8, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF4 }, // 1218 |
| 20707 | { 0x8, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG8EI32_V_M1_MF2 }, // 1219 |
| 20708 | { 0x8, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG8EI32_V_M2_MF2 }, // 1220 |
| 20709 | { 0x8, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF2 }, // 1221 |
| 20710 | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG8EI64_V_M1_M1 }, // 1222 |
| 20711 | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG8EI64_V_M2_M1 }, // 1223 |
| 20712 | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG8EI64_V_M4_M1 }, // 1224 |
| 20713 | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG8EI64_V_M8_M1 }, // 1225 |
| 20714 | { 0x8, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG8EI64_V_M1_MF8 }, // 1226 |
| 20715 | { 0x8, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG8EI64_V_M1_MF4 }, // 1227 |
| 20716 | { 0x8, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG8EI64_V_M2_MF4 }, // 1228 |
| 20717 | { 0x8, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG8EI64_V_M1_MF2 }, // 1229 |
| 20718 | { 0x8, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG8EI64_V_M2_MF2 }, // 1230 |
| 20719 | { 0x8, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG8EI64_V_M4_MF2 }, // 1231 |
| 20720 | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG8EI8_V_M1_M1 }, // 1232 |
| 20721 | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG8EI8_V_MF8_M1 }, // 1233 |
| 20722 | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG8EI8_V_MF4_M1 }, // 1234 |
| 20723 | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG8EI8_V_MF2_M1 }, // 1235 |
| 20724 | { 0x8, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF8 }, // 1236 |
| 20725 | { 0x8, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF4 }, // 1237 |
| 20726 | { 0x8, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG8EI8_V_MF4_MF4 }, // 1238 |
| 20727 | { 0x8, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF2 }, // 1239 |
| 20728 | { 0x8, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG8EI8_V_MF4_MF2 }, // 1240 |
| 20729 | { 0x8, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG8EI8_V_MF2_MF2 }, // 1241 |
| 20730 | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG8EI16_V_M1_M1 }, // 1242 |
| 20731 | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG8EI16_V_M2_M1 }, // 1243 |
| 20732 | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG8EI16_V_MF4_M1 }, // 1244 |
| 20733 | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG8EI16_V_MF2_M1 }, // 1245 |
| 20734 | { 0x8, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF8 }, // 1246 |
| 20735 | { 0x8, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF4 }, // 1247 |
| 20736 | { 0x8, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG8EI16_V_MF2_MF4 }, // 1248 |
| 20737 | { 0x8, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG8EI16_V_M1_MF2 }, // 1249 |
| 20738 | { 0x8, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF2 }, // 1250 |
| 20739 | { 0x8, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG8EI16_V_MF2_MF2 }, // 1251 |
| 20740 | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG8EI32_V_M1_M1 }, // 1252 |
| 20741 | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG8EI32_V_M2_M1 }, // 1253 |
| 20742 | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG8EI32_V_M4_M1 }, // 1254 |
| 20743 | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG8EI32_V_MF2_M1 }, // 1255 |
| 20744 | { 0x8, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF8 }, // 1256 |
| 20745 | { 0x8, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG8EI32_V_M1_MF4 }, // 1257 |
| 20746 | { 0x8, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF4 }, // 1258 |
| 20747 | { 0x8, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG8EI32_V_M1_MF2 }, // 1259 |
| 20748 | { 0x8, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG8EI32_V_M2_MF2 }, // 1260 |
| 20749 | { 0x8, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF2 }, // 1261 |
| 20750 | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG8EI64_V_M1_M1 }, // 1262 |
| 20751 | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG8EI64_V_M2_M1 }, // 1263 |
| 20752 | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG8EI64_V_M4_M1 }, // 1264 |
| 20753 | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG8EI64_V_M8_M1 }, // 1265 |
| 20754 | { 0x8, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG8EI64_V_M1_MF8 }, // 1266 |
| 20755 | { 0x8, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG8EI64_V_M1_MF4 }, // 1267 |
| 20756 | { 0x8, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG8EI64_V_M2_MF4 }, // 1268 |
| 20757 | { 0x8, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG8EI64_V_M1_MF2 }, // 1269 |
| 20758 | { 0x8, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG8EI64_V_M2_MF2 }, // 1270 |
| 20759 | { 0x8, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG8EI64_V_M4_MF2 }, // 1271 |
| 20760 | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG8EI8_V_M1_M1_MASK }, // 1272 |
| 20761 | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG8EI8_V_MF8_M1_MASK }, // 1273 |
| 20762 | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG8EI8_V_MF4_M1_MASK }, // 1274 |
| 20763 | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG8EI8_V_MF2_M1_MASK }, // 1275 |
| 20764 | { 0x8, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF8_MASK }, // 1276 |
| 20765 | { 0x8, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF4_MASK }, // 1277 |
| 20766 | { 0x8, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG8EI8_V_MF4_MF4_MASK }, // 1278 |
| 20767 | { 0x8, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF2_MASK }, // 1279 |
| 20768 | { 0x8, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG8EI8_V_MF4_MF2_MASK }, // 1280 |
| 20769 | { 0x8, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG8EI8_V_MF2_MF2_MASK }, // 1281 |
| 20770 | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG8EI16_V_M1_M1_MASK }, // 1282 |
| 20771 | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG8EI16_V_M2_M1_MASK }, // 1283 |
| 20772 | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG8EI16_V_MF4_M1_MASK }, // 1284 |
| 20773 | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG8EI16_V_MF2_M1_MASK }, // 1285 |
| 20774 | { 0x8, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF8_MASK }, // 1286 |
| 20775 | { 0x8, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF4_MASK }, // 1287 |
| 20776 | { 0x8, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG8EI16_V_MF2_MF4_MASK }, // 1288 |
| 20777 | { 0x8, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG8EI16_V_M1_MF2_MASK }, // 1289 |
| 20778 | { 0x8, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF2_MASK }, // 1290 |
| 20779 | { 0x8, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG8EI16_V_MF2_MF2_MASK }, // 1291 |
| 20780 | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG8EI32_V_M1_M1_MASK }, // 1292 |
| 20781 | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG8EI32_V_M2_M1_MASK }, // 1293 |
| 20782 | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG8EI32_V_M4_M1_MASK }, // 1294 |
| 20783 | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG8EI32_V_MF2_M1_MASK }, // 1295 |
| 20784 | { 0x8, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF8_MASK }, // 1296 |
| 20785 | { 0x8, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG8EI32_V_M1_MF4_MASK }, // 1297 |
| 20786 | { 0x8, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF4_MASK }, // 1298 |
| 20787 | { 0x8, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG8EI32_V_M1_MF2_MASK }, // 1299 |
| 20788 | { 0x8, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG8EI32_V_M2_MF2_MASK }, // 1300 |
| 20789 | { 0x8, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF2_MASK }, // 1301 |
| 20790 | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG8EI64_V_M1_M1_MASK }, // 1302 |
| 20791 | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG8EI64_V_M2_M1_MASK }, // 1303 |
| 20792 | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG8EI64_V_M4_M1_MASK }, // 1304 |
| 20793 | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG8EI64_V_M8_M1_MASK }, // 1305 |
| 20794 | { 0x8, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG8EI64_V_M1_MF8_MASK }, // 1306 |
| 20795 | { 0x8, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG8EI64_V_M1_MF4_MASK }, // 1307 |
| 20796 | { 0x8, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG8EI64_V_M2_MF4_MASK }, // 1308 |
| 20797 | { 0x8, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG8EI64_V_M1_MF2_MASK }, // 1309 |
| 20798 | { 0x8, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG8EI64_V_M2_MF2_MASK }, // 1310 |
| 20799 | { 0x8, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG8EI64_V_M4_MF2_MASK }, // 1311 |
| 20800 | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG8EI8_V_M1_M1_MASK }, // 1312 |
| 20801 | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG8EI8_V_MF8_M1_MASK }, // 1313 |
| 20802 | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG8EI8_V_MF4_M1_MASK }, // 1314 |
| 20803 | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG8EI8_V_MF2_M1_MASK }, // 1315 |
| 20804 | { 0x8, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF8_MASK }, // 1316 |
| 20805 | { 0x8, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF4_MASK }, // 1317 |
| 20806 | { 0x8, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG8EI8_V_MF4_MF4_MASK }, // 1318 |
| 20807 | { 0x8, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF2_MASK }, // 1319 |
| 20808 | { 0x8, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG8EI8_V_MF4_MF2_MASK }, // 1320 |
| 20809 | { 0x8, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG8EI8_V_MF2_MF2_MASK }, // 1321 |
| 20810 | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG8EI16_V_M1_M1_MASK }, // 1322 |
| 20811 | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG8EI16_V_M2_M1_MASK }, // 1323 |
| 20812 | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG8EI16_V_MF4_M1_MASK }, // 1324 |
| 20813 | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG8EI16_V_MF2_M1_MASK }, // 1325 |
| 20814 | { 0x8, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF8_MASK }, // 1326 |
| 20815 | { 0x8, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF4_MASK }, // 1327 |
| 20816 | { 0x8, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG8EI16_V_MF2_MF4_MASK }, // 1328 |
| 20817 | { 0x8, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG8EI16_V_M1_MF2_MASK }, // 1329 |
| 20818 | { 0x8, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF2_MASK }, // 1330 |
| 20819 | { 0x8, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG8EI16_V_MF2_MF2_MASK }, // 1331 |
| 20820 | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG8EI32_V_M1_M1_MASK }, // 1332 |
| 20821 | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG8EI32_V_M2_M1_MASK }, // 1333 |
| 20822 | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG8EI32_V_M4_M1_MASK }, // 1334 |
| 20823 | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG8EI32_V_MF2_M1_MASK }, // 1335 |
| 20824 | { 0x8, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF8_MASK }, // 1336 |
| 20825 | { 0x8, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG8EI32_V_M1_MF4_MASK }, // 1337 |
| 20826 | { 0x8, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF4_MASK }, // 1338 |
| 20827 | { 0x8, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG8EI32_V_M1_MF2_MASK }, // 1339 |
| 20828 | { 0x8, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG8EI32_V_M2_MF2_MASK }, // 1340 |
| 20829 | { 0x8, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF2_MASK }, // 1341 |
| 20830 | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG8EI64_V_M1_M1_MASK }, // 1342 |
| 20831 | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG8EI64_V_M2_M1_MASK }, // 1343 |
| 20832 | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG8EI64_V_M4_M1_MASK }, // 1344 |
| 20833 | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG8EI64_V_M8_M1_MASK }, // 1345 |
| 20834 | { 0x8, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG8EI64_V_M1_MF8_MASK }, // 1346 |
| 20835 | { 0x8, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG8EI64_V_M1_MF4_MASK }, // 1347 |
| 20836 | { 0x8, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG8EI64_V_M2_MF4_MASK }, // 1348 |
| 20837 | { 0x8, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG8EI64_V_M1_MF2_MASK }, // 1349 |
| 20838 | { 0x8, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG8EI64_V_M2_MF2_MASK }, // 1350 |
| 20839 | { 0x8, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG8EI64_V_M4_MF2_MASK }, // 1351 |
| 20840 | }; |
| 20841 | |
| 20842 | const VLXSEGPseudo *getVLXSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL) { |
| 20843 | struct KeyType { |
| 20844 | uint8_t NF; |
| 20845 | uint8_t Masked; |
| 20846 | uint8_t Ordered; |
| 20847 | uint8_t Log2SEW; |
| 20848 | uint8_t LMUL; |
| 20849 | uint8_t IndexLMUL; |
| 20850 | }; |
| 20851 | KeyType Key = {NF, Masked, Ordered, Log2SEW, LMUL, IndexLMUL}; |
| 20852 | struct Comp { |
| 20853 | bool operator()(const VLXSEGPseudo &LHS, const KeyType &RHS) const { |
| 20854 | if (LHS.NF < RHS.NF) |
| 20855 | return true; |
| 20856 | if (LHS.NF > RHS.NF) |
| 20857 | return false; |
| 20858 | if (LHS.Masked < RHS.Masked) |
| 20859 | return true; |
| 20860 | if (LHS.Masked > RHS.Masked) |
| 20861 | return false; |
| 20862 | if (LHS.Ordered < RHS.Ordered) |
| 20863 | return true; |
| 20864 | if (LHS.Ordered > RHS.Ordered) |
| 20865 | return false; |
| 20866 | if (LHS.Log2SEW < RHS.Log2SEW) |
| 20867 | return true; |
| 20868 | if (LHS.Log2SEW > RHS.Log2SEW) |
| 20869 | return false; |
| 20870 | if (LHS.LMUL < RHS.LMUL) |
| 20871 | return true; |
| 20872 | if (LHS.LMUL > RHS.LMUL) |
| 20873 | return false; |
| 20874 | if (LHS.IndexLMUL < RHS.IndexLMUL) |
| 20875 | return true; |
| 20876 | if (LHS.IndexLMUL > RHS.IndexLMUL) |
| 20877 | return false; |
| 20878 | return false; |
| 20879 | } |
| 20880 | }; |
| 20881 | auto Table = ArrayRef(RISCVVLXSEGTable); |
| 20882 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 20883 | if (Idx == Table.end() || |
| 20884 | Key.NF != Idx->NF || |
| 20885 | Key.Masked != Idx->Masked || |
| 20886 | Key.Ordered != Idx->Ordered || |
| 20887 | Key.Log2SEW != Idx->Log2SEW || |
| 20888 | Key.LMUL != Idx->LMUL || |
| 20889 | Key.IndexLMUL != Idx->IndexLMUL) |
| 20890 | return nullptr; |
| 20891 | |
| 20892 | return &*Idx; |
| 20893 | } |
| 20894 | #endif |
| 20895 | |
| 20896 | #ifdef GET_RISCVVLXTable_DECL |
| 20897 | const VLX_VSXPseudo *getVLXPseudo(uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL); |
| 20898 | #endif |
| 20899 | |
| 20900 | #ifdef GET_RISCVVLXTable_IMPL |
| 20901 | constexpr VLX_VSXPseudo RISCVVLXTable[] = { |
| 20902 | { 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXEI8_V_M1_M1 }, // 0 |
| 20903 | { 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXEI8_V_MF8_M1 }, // 1 |
| 20904 | { 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXEI8_V_MF4_M1 }, // 2 |
| 20905 | { 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXEI8_V_MF2_M1 }, // 3 |
| 20906 | { 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVLUXEI8_V_M1_M2 }, // 4 |
| 20907 | { 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVLUXEI8_V_M2_M2 }, // 5 |
| 20908 | { 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVLUXEI8_V_MF4_M2 }, // 6 |
| 20909 | { 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVLUXEI8_V_MF2_M2 }, // 7 |
| 20910 | { 0x0, 0x0, 0x3, 0x2, 0x0, PseudoVLUXEI8_V_M1_M4 }, // 8 |
| 20911 | { 0x0, 0x0, 0x3, 0x2, 0x1, PseudoVLUXEI8_V_M2_M4 }, // 9 |
| 20912 | { 0x0, 0x0, 0x3, 0x2, 0x2, PseudoVLUXEI8_V_M4_M4 }, // 10 |
| 20913 | { 0x0, 0x0, 0x3, 0x2, 0x7, PseudoVLUXEI8_V_MF2_M4 }, // 11 |
| 20914 | { 0x0, 0x0, 0x3, 0x3, 0x0, PseudoVLUXEI8_V_M1_M8 }, // 12 |
| 20915 | { 0x0, 0x0, 0x3, 0x3, 0x1, PseudoVLUXEI8_V_M2_M8 }, // 13 |
| 20916 | { 0x0, 0x0, 0x3, 0x3, 0x2, PseudoVLUXEI8_V_M4_M8 }, // 14 |
| 20917 | { 0x0, 0x0, 0x3, 0x3, 0x3, PseudoVLUXEI8_V_M8_M8 }, // 15 |
| 20918 | { 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXEI8_V_MF8_MF8 }, // 16 |
| 20919 | { 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXEI8_V_MF8_MF4 }, // 17 |
| 20920 | { 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXEI8_V_MF4_MF4 }, // 18 |
| 20921 | { 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXEI8_V_MF8_MF2 }, // 19 |
| 20922 | { 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXEI8_V_MF4_MF2 }, // 20 |
| 20923 | { 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXEI8_V_MF2_MF2 }, // 21 |
| 20924 | { 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXEI16_V_M1_M1 }, // 22 |
| 20925 | { 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXEI16_V_M2_M1 }, // 23 |
| 20926 | { 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXEI16_V_MF4_M1 }, // 24 |
| 20927 | { 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXEI16_V_MF2_M1 }, // 25 |
| 20928 | { 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVLUXEI16_V_M1_M2 }, // 26 |
| 20929 | { 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVLUXEI16_V_M2_M2 }, // 27 |
| 20930 | { 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVLUXEI16_V_M4_M2 }, // 28 |
| 20931 | { 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVLUXEI16_V_MF2_M2 }, // 29 |
| 20932 | { 0x0, 0x0, 0x4, 0x2, 0x0, PseudoVLUXEI16_V_M1_M4 }, // 30 |
| 20933 | { 0x0, 0x0, 0x4, 0x2, 0x1, PseudoVLUXEI16_V_M2_M4 }, // 31 |
| 20934 | { 0x0, 0x0, 0x4, 0x2, 0x2, PseudoVLUXEI16_V_M4_M4 }, // 32 |
| 20935 | { 0x0, 0x0, 0x4, 0x2, 0x3, PseudoVLUXEI16_V_M8_M4 }, // 33 |
| 20936 | { 0x0, 0x0, 0x4, 0x3, 0x1, PseudoVLUXEI16_V_M2_M8 }, // 34 |
| 20937 | { 0x0, 0x0, 0x4, 0x3, 0x2, PseudoVLUXEI16_V_M4_M8 }, // 35 |
| 20938 | { 0x0, 0x0, 0x4, 0x3, 0x3, PseudoVLUXEI16_V_M8_M8 }, // 36 |
| 20939 | { 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXEI16_V_MF4_MF8 }, // 37 |
| 20940 | { 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXEI16_V_MF4_MF4 }, // 38 |
| 20941 | { 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXEI16_V_MF2_MF4 }, // 39 |
| 20942 | { 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXEI16_V_M1_MF2 }, // 40 |
| 20943 | { 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXEI16_V_MF4_MF2 }, // 41 |
| 20944 | { 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXEI16_V_MF2_MF2 }, // 42 |
| 20945 | { 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXEI32_V_M1_M1 }, // 43 |
| 20946 | { 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXEI32_V_M2_M1 }, // 44 |
| 20947 | { 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXEI32_V_M4_M1 }, // 45 |
| 20948 | { 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXEI32_V_MF2_M1 }, // 46 |
| 20949 | { 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVLUXEI32_V_M1_M2 }, // 47 |
| 20950 | { 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVLUXEI32_V_M2_M2 }, // 48 |
| 20951 | { 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVLUXEI32_V_M4_M2 }, // 49 |
| 20952 | { 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVLUXEI32_V_M8_M2 }, // 50 |
| 20953 | { 0x0, 0x0, 0x5, 0x2, 0x1, PseudoVLUXEI32_V_M2_M4 }, // 51 |
| 20954 | { 0x0, 0x0, 0x5, 0x2, 0x2, PseudoVLUXEI32_V_M4_M4 }, // 52 |
| 20955 | { 0x0, 0x0, 0x5, 0x2, 0x3, PseudoVLUXEI32_V_M8_M4 }, // 53 |
| 20956 | { 0x0, 0x0, 0x5, 0x3, 0x2, PseudoVLUXEI32_V_M4_M8 }, // 54 |
| 20957 | { 0x0, 0x0, 0x5, 0x3, 0x3, PseudoVLUXEI32_V_M8_M8 }, // 55 |
| 20958 | { 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXEI32_V_MF2_MF8 }, // 56 |
| 20959 | { 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXEI32_V_M1_MF4 }, // 57 |
| 20960 | { 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXEI32_V_MF2_MF4 }, // 58 |
| 20961 | { 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXEI32_V_M1_MF2 }, // 59 |
| 20962 | { 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXEI32_V_M2_MF2 }, // 60 |
| 20963 | { 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXEI32_V_MF2_MF2 }, // 61 |
| 20964 | { 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXEI64_V_M1_M1 }, // 62 |
| 20965 | { 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXEI64_V_M2_M1 }, // 63 |
| 20966 | { 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXEI64_V_M4_M1 }, // 64 |
| 20967 | { 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXEI64_V_M8_M1 }, // 65 |
| 20968 | { 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVLUXEI64_V_M2_M2 }, // 66 |
| 20969 | { 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVLUXEI64_V_M4_M2 }, // 67 |
| 20970 | { 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVLUXEI64_V_M8_M2 }, // 68 |
| 20971 | { 0x0, 0x0, 0x6, 0x2, 0x2, PseudoVLUXEI64_V_M4_M4 }, // 69 |
| 20972 | { 0x0, 0x0, 0x6, 0x2, 0x3, PseudoVLUXEI64_V_M8_M4 }, // 70 |
| 20973 | { 0x0, 0x0, 0x6, 0x3, 0x3, PseudoVLUXEI64_V_M8_M8 }, // 71 |
| 20974 | { 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXEI64_V_M1_MF8 }, // 72 |
| 20975 | { 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXEI64_V_M1_MF4 }, // 73 |
| 20976 | { 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXEI64_V_M2_MF4 }, // 74 |
| 20977 | { 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXEI64_V_M1_MF2 }, // 75 |
| 20978 | { 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXEI64_V_M2_MF2 }, // 76 |
| 20979 | { 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXEI64_V_M4_MF2 }, // 77 |
| 20980 | { 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXEI8_V_M1_M1 }, // 78 |
| 20981 | { 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXEI8_V_MF8_M1 }, // 79 |
| 20982 | { 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXEI8_V_MF4_M1 }, // 80 |
| 20983 | { 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXEI8_V_MF2_M1 }, // 81 |
| 20984 | { 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVLOXEI8_V_M1_M2 }, // 82 |
| 20985 | { 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVLOXEI8_V_M2_M2 }, // 83 |
| 20986 | { 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVLOXEI8_V_MF4_M2 }, // 84 |
| 20987 | { 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVLOXEI8_V_MF2_M2 }, // 85 |
| 20988 | { 0x0, 0x1, 0x3, 0x2, 0x0, PseudoVLOXEI8_V_M1_M4 }, // 86 |
| 20989 | { 0x0, 0x1, 0x3, 0x2, 0x1, PseudoVLOXEI8_V_M2_M4 }, // 87 |
| 20990 | { 0x0, 0x1, 0x3, 0x2, 0x2, PseudoVLOXEI8_V_M4_M4 }, // 88 |
| 20991 | { 0x0, 0x1, 0x3, 0x2, 0x7, PseudoVLOXEI8_V_MF2_M4 }, // 89 |
| 20992 | { 0x0, 0x1, 0x3, 0x3, 0x0, PseudoVLOXEI8_V_M1_M8 }, // 90 |
| 20993 | { 0x0, 0x1, 0x3, 0x3, 0x1, PseudoVLOXEI8_V_M2_M8 }, // 91 |
| 20994 | { 0x0, 0x1, 0x3, 0x3, 0x2, PseudoVLOXEI8_V_M4_M8 }, // 92 |
| 20995 | { 0x0, 0x1, 0x3, 0x3, 0x3, PseudoVLOXEI8_V_M8_M8 }, // 93 |
| 20996 | { 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXEI8_V_MF8_MF8 }, // 94 |
| 20997 | { 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXEI8_V_MF8_MF4 }, // 95 |
| 20998 | { 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXEI8_V_MF4_MF4 }, // 96 |
| 20999 | { 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXEI8_V_MF8_MF2 }, // 97 |
| 21000 | { 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXEI8_V_MF4_MF2 }, // 98 |
| 21001 | { 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXEI8_V_MF2_MF2 }, // 99 |
| 21002 | { 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXEI16_V_M1_M1 }, // 100 |
| 21003 | { 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXEI16_V_M2_M1 }, // 101 |
| 21004 | { 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXEI16_V_MF4_M1 }, // 102 |
| 21005 | { 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXEI16_V_MF2_M1 }, // 103 |
| 21006 | { 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVLOXEI16_V_M1_M2 }, // 104 |
| 21007 | { 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVLOXEI16_V_M2_M2 }, // 105 |
| 21008 | { 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVLOXEI16_V_M4_M2 }, // 106 |
| 21009 | { 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVLOXEI16_V_MF2_M2 }, // 107 |
| 21010 | { 0x0, 0x1, 0x4, 0x2, 0x0, PseudoVLOXEI16_V_M1_M4 }, // 108 |
| 21011 | { 0x0, 0x1, 0x4, 0x2, 0x1, PseudoVLOXEI16_V_M2_M4 }, // 109 |
| 21012 | { 0x0, 0x1, 0x4, 0x2, 0x2, PseudoVLOXEI16_V_M4_M4 }, // 110 |
| 21013 | { 0x0, 0x1, 0x4, 0x2, 0x3, PseudoVLOXEI16_V_M8_M4 }, // 111 |
| 21014 | { 0x0, 0x1, 0x4, 0x3, 0x1, PseudoVLOXEI16_V_M2_M8 }, // 112 |
| 21015 | { 0x0, 0x1, 0x4, 0x3, 0x2, PseudoVLOXEI16_V_M4_M8 }, // 113 |
| 21016 | { 0x0, 0x1, 0x4, 0x3, 0x3, PseudoVLOXEI16_V_M8_M8 }, // 114 |
| 21017 | { 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXEI16_V_MF4_MF8 }, // 115 |
| 21018 | { 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXEI16_V_MF4_MF4 }, // 116 |
| 21019 | { 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXEI16_V_MF2_MF4 }, // 117 |
| 21020 | { 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXEI16_V_M1_MF2 }, // 118 |
| 21021 | { 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXEI16_V_MF4_MF2 }, // 119 |
| 21022 | { 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXEI16_V_MF2_MF2 }, // 120 |
| 21023 | { 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXEI32_V_M1_M1 }, // 121 |
| 21024 | { 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXEI32_V_M2_M1 }, // 122 |
| 21025 | { 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXEI32_V_M4_M1 }, // 123 |
| 21026 | { 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXEI32_V_MF2_M1 }, // 124 |
| 21027 | { 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVLOXEI32_V_M1_M2 }, // 125 |
| 21028 | { 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVLOXEI32_V_M2_M2 }, // 126 |
| 21029 | { 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVLOXEI32_V_M4_M2 }, // 127 |
| 21030 | { 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVLOXEI32_V_M8_M2 }, // 128 |
| 21031 | { 0x0, 0x1, 0x5, 0x2, 0x1, PseudoVLOXEI32_V_M2_M4 }, // 129 |
| 21032 | { 0x0, 0x1, 0x5, 0x2, 0x2, PseudoVLOXEI32_V_M4_M4 }, // 130 |
| 21033 | { 0x0, 0x1, 0x5, 0x2, 0x3, PseudoVLOXEI32_V_M8_M4 }, // 131 |
| 21034 | { 0x0, 0x1, 0x5, 0x3, 0x2, PseudoVLOXEI32_V_M4_M8 }, // 132 |
| 21035 | { 0x0, 0x1, 0x5, 0x3, 0x3, PseudoVLOXEI32_V_M8_M8 }, // 133 |
| 21036 | { 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXEI32_V_MF2_MF8 }, // 134 |
| 21037 | { 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXEI32_V_M1_MF4 }, // 135 |
| 21038 | { 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXEI32_V_MF2_MF4 }, // 136 |
| 21039 | { 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXEI32_V_M1_MF2 }, // 137 |
| 21040 | { 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXEI32_V_M2_MF2 }, // 138 |
| 21041 | { 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXEI32_V_MF2_MF2 }, // 139 |
| 21042 | { 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXEI64_V_M1_M1 }, // 140 |
| 21043 | { 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXEI64_V_M2_M1 }, // 141 |
| 21044 | { 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXEI64_V_M4_M1 }, // 142 |
| 21045 | { 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXEI64_V_M8_M1 }, // 143 |
| 21046 | { 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVLOXEI64_V_M2_M2 }, // 144 |
| 21047 | { 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVLOXEI64_V_M4_M2 }, // 145 |
| 21048 | { 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVLOXEI64_V_M8_M2 }, // 146 |
| 21049 | { 0x0, 0x1, 0x6, 0x2, 0x2, PseudoVLOXEI64_V_M4_M4 }, // 147 |
| 21050 | { 0x0, 0x1, 0x6, 0x2, 0x3, PseudoVLOXEI64_V_M8_M4 }, // 148 |
| 21051 | { 0x0, 0x1, 0x6, 0x3, 0x3, PseudoVLOXEI64_V_M8_M8 }, // 149 |
| 21052 | { 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXEI64_V_M1_MF8 }, // 150 |
| 21053 | { 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXEI64_V_M1_MF4 }, // 151 |
| 21054 | { 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXEI64_V_M2_MF4 }, // 152 |
| 21055 | { 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXEI64_V_M1_MF2 }, // 153 |
| 21056 | { 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXEI64_V_M2_MF2 }, // 154 |
| 21057 | { 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXEI64_V_M4_MF2 }, // 155 |
| 21058 | { 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXEI8_V_M1_M1_MASK }, // 156 |
| 21059 | { 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXEI8_V_MF8_M1_MASK }, // 157 |
| 21060 | { 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXEI8_V_MF4_M1_MASK }, // 158 |
| 21061 | { 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXEI8_V_MF2_M1_MASK }, // 159 |
| 21062 | { 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVLUXEI8_V_M1_M2_MASK }, // 160 |
| 21063 | { 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVLUXEI8_V_M2_M2_MASK }, // 161 |
| 21064 | { 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVLUXEI8_V_MF4_M2_MASK }, // 162 |
| 21065 | { 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVLUXEI8_V_MF2_M2_MASK }, // 163 |
| 21066 | { 0x1, 0x0, 0x3, 0x2, 0x0, PseudoVLUXEI8_V_M1_M4_MASK }, // 164 |
| 21067 | { 0x1, 0x0, 0x3, 0x2, 0x1, PseudoVLUXEI8_V_M2_M4_MASK }, // 165 |
| 21068 | { 0x1, 0x0, 0x3, 0x2, 0x2, PseudoVLUXEI8_V_M4_M4_MASK }, // 166 |
| 21069 | { 0x1, 0x0, 0x3, 0x2, 0x7, PseudoVLUXEI8_V_MF2_M4_MASK }, // 167 |
| 21070 | { 0x1, 0x0, 0x3, 0x3, 0x0, PseudoVLUXEI8_V_M1_M8_MASK }, // 168 |
| 21071 | { 0x1, 0x0, 0x3, 0x3, 0x1, PseudoVLUXEI8_V_M2_M8_MASK }, // 169 |
| 21072 | { 0x1, 0x0, 0x3, 0x3, 0x2, PseudoVLUXEI8_V_M4_M8_MASK }, // 170 |
| 21073 | { 0x1, 0x0, 0x3, 0x3, 0x3, PseudoVLUXEI8_V_M8_M8_MASK }, // 171 |
| 21074 | { 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXEI8_V_MF8_MF8_MASK }, // 172 |
| 21075 | { 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXEI8_V_MF8_MF4_MASK }, // 173 |
| 21076 | { 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXEI8_V_MF4_MF4_MASK }, // 174 |
| 21077 | { 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXEI8_V_MF8_MF2_MASK }, // 175 |
| 21078 | { 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXEI8_V_MF4_MF2_MASK }, // 176 |
| 21079 | { 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXEI8_V_MF2_MF2_MASK }, // 177 |
| 21080 | { 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXEI16_V_M1_M1_MASK }, // 178 |
| 21081 | { 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXEI16_V_M2_M1_MASK }, // 179 |
| 21082 | { 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXEI16_V_MF4_M1_MASK }, // 180 |
| 21083 | { 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXEI16_V_MF2_M1_MASK }, // 181 |
| 21084 | { 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVLUXEI16_V_M1_M2_MASK }, // 182 |
| 21085 | { 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVLUXEI16_V_M2_M2_MASK }, // 183 |
| 21086 | { 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVLUXEI16_V_M4_M2_MASK }, // 184 |
| 21087 | { 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVLUXEI16_V_MF2_M2_MASK }, // 185 |
| 21088 | { 0x1, 0x0, 0x4, 0x2, 0x0, PseudoVLUXEI16_V_M1_M4_MASK }, // 186 |
| 21089 | { 0x1, 0x0, 0x4, 0x2, 0x1, PseudoVLUXEI16_V_M2_M4_MASK }, // 187 |
| 21090 | { 0x1, 0x0, 0x4, 0x2, 0x2, PseudoVLUXEI16_V_M4_M4_MASK }, // 188 |
| 21091 | { 0x1, 0x0, 0x4, 0x2, 0x3, PseudoVLUXEI16_V_M8_M4_MASK }, // 189 |
| 21092 | { 0x1, 0x0, 0x4, 0x3, 0x1, PseudoVLUXEI16_V_M2_M8_MASK }, // 190 |
| 21093 | { 0x1, 0x0, 0x4, 0x3, 0x2, PseudoVLUXEI16_V_M4_M8_MASK }, // 191 |
| 21094 | { 0x1, 0x0, 0x4, 0x3, 0x3, PseudoVLUXEI16_V_M8_M8_MASK }, // 192 |
| 21095 | { 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXEI16_V_MF4_MF8_MASK }, // 193 |
| 21096 | { 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXEI16_V_MF4_MF4_MASK }, // 194 |
| 21097 | { 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXEI16_V_MF2_MF4_MASK }, // 195 |
| 21098 | { 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXEI16_V_M1_MF2_MASK }, // 196 |
| 21099 | { 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXEI16_V_MF4_MF2_MASK }, // 197 |
| 21100 | { 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXEI16_V_MF2_MF2_MASK }, // 198 |
| 21101 | { 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXEI32_V_M1_M1_MASK }, // 199 |
| 21102 | { 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXEI32_V_M2_M1_MASK }, // 200 |
| 21103 | { 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXEI32_V_M4_M1_MASK }, // 201 |
| 21104 | { 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXEI32_V_MF2_M1_MASK }, // 202 |
| 21105 | { 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVLUXEI32_V_M1_M2_MASK }, // 203 |
| 21106 | { 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVLUXEI32_V_M2_M2_MASK }, // 204 |
| 21107 | { 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVLUXEI32_V_M4_M2_MASK }, // 205 |
| 21108 | { 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVLUXEI32_V_M8_M2_MASK }, // 206 |
| 21109 | { 0x1, 0x0, 0x5, 0x2, 0x1, PseudoVLUXEI32_V_M2_M4_MASK }, // 207 |
| 21110 | { 0x1, 0x0, 0x5, 0x2, 0x2, PseudoVLUXEI32_V_M4_M4_MASK }, // 208 |
| 21111 | { 0x1, 0x0, 0x5, 0x2, 0x3, PseudoVLUXEI32_V_M8_M4_MASK }, // 209 |
| 21112 | { 0x1, 0x0, 0x5, 0x3, 0x2, PseudoVLUXEI32_V_M4_M8_MASK }, // 210 |
| 21113 | { 0x1, 0x0, 0x5, 0x3, 0x3, PseudoVLUXEI32_V_M8_M8_MASK }, // 211 |
| 21114 | { 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXEI32_V_MF2_MF8_MASK }, // 212 |
| 21115 | { 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXEI32_V_M1_MF4_MASK }, // 213 |
| 21116 | { 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXEI32_V_MF2_MF4_MASK }, // 214 |
| 21117 | { 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXEI32_V_M1_MF2_MASK }, // 215 |
| 21118 | { 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXEI32_V_M2_MF2_MASK }, // 216 |
| 21119 | { 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXEI32_V_MF2_MF2_MASK }, // 217 |
| 21120 | { 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXEI64_V_M1_M1_MASK }, // 218 |
| 21121 | { 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXEI64_V_M2_M1_MASK }, // 219 |
| 21122 | { 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXEI64_V_M4_M1_MASK }, // 220 |
| 21123 | { 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXEI64_V_M8_M1_MASK }, // 221 |
| 21124 | { 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVLUXEI64_V_M2_M2_MASK }, // 222 |
| 21125 | { 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVLUXEI64_V_M4_M2_MASK }, // 223 |
| 21126 | { 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVLUXEI64_V_M8_M2_MASK }, // 224 |
| 21127 | { 0x1, 0x0, 0x6, 0x2, 0x2, PseudoVLUXEI64_V_M4_M4_MASK }, // 225 |
| 21128 | { 0x1, 0x0, 0x6, 0x2, 0x3, PseudoVLUXEI64_V_M8_M4_MASK }, // 226 |
| 21129 | { 0x1, 0x0, 0x6, 0x3, 0x3, PseudoVLUXEI64_V_M8_M8_MASK }, // 227 |
| 21130 | { 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXEI64_V_M1_MF8_MASK }, // 228 |
| 21131 | { 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXEI64_V_M1_MF4_MASK }, // 229 |
| 21132 | { 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXEI64_V_M2_MF4_MASK }, // 230 |
| 21133 | { 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXEI64_V_M1_MF2_MASK }, // 231 |
| 21134 | { 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXEI64_V_M2_MF2_MASK }, // 232 |
| 21135 | { 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXEI64_V_M4_MF2_MASK }, // 233 |
| 21136 | { 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXEI8_V_M1_M1_MASK }, // 234 |
| 21137 | { 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXEI8_V_MF8_M1_MASK }, // 235 |
| 21138 | { 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXEI8_V_MF4_M1_MASK }, // 236 |
| 21139 | { 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXEI8_V_MF2_M1_MASK }, // 237 |
| 21140 | { 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVLOXEI8_V_M1_M2_MASK }, // 238 |
| 21141 | { 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVLOXEI8_V_M2_M2_MASK }, // 239 |
| 21142 | { 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVLOXEI8_V_MF4_M2_MASK }, // 240 |
| 21143 | { 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVLOXEI8_V_MF2_M2_MASK }, // 241 |
| 21144 | { 0x1, 0x1, 0x3, 0x2, 0x0, PseudoVLOXEI8_V_M1_M4_MASK }, // 242 |
| 21145 | { 0x1, 0x1, 0x3, 0x2, 0x1, PseudoVLOXEI8_V_M2_M4_MASK }, // 243 |
| 21146 | { 0x1, 0x1, 0x3, 0x2, 0x2, PseudoVLOXEI8_V_M4_M4_MASK }, // 244 |
| 21147 | { 0x1, 0x1, 0x3, 0x2, 0x7, PseudoVLOXEI8_V_MF2_M4_MASK }, // 245 |
| 21148 | { 0x1, 0x1, 0x3, 0x3, 0x0, PseudoVLOXEI8_V_M1_M8_MASK }, // 246 |
| 21149 | { 0x1, 0x1, 0x3, 0x3, 0x1, PseudoVLOXEI8_V_M2_M8_MASK }, // 247 |
| 21150 | { 0x1, 0x1, 0x3, 0x3, 0x2, PseudoVLOXEI8_V_M4_M8_MASK }, // 248 |
| 21151 | { 0x1, 0x1, 0x3, 0x3, 0x3, PseudoVLOXEI8_V_M8_M8_MASK }, // 249 |
| 21152 | { 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXEI8_V_MF8_MF8_MASK }, // 250 |
| 21153 | { 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXEI8_V_MF8_MF4_MASK }, // 251 |
| 21154 | { 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXEI8_V_MF4_MF4_MASK }, // 252 |
| 21155 | { 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXEI8_V_MF8_MF2_MASK }, // 253 |
| 21156 | { 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXEI8_V_MF4_MF2_MASK }, // 254 |
| 21157 | { 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXEI8_V_MF2_MF2_MASK }, // 255 |
| 21158 | { 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXEI16_V_M1_M1_MASK }, // 256 |
| 21159 | { 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXEI16_V_M2_M1_MASK }, // 257 |
| 21160 | { 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXEI16_V_MF4_M1_MASK }, // 258 |
| 21161 | { 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXEI16_V_MF2_M1_MASK }, // 259 |
| 21162 | { 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVLOXEI16_V_M1_M2_MASK }, // 260 |
| 21163 | { 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVLOXEI16_V_M2_M2_MASK }, // 261 |
| 21164 | { 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVLOXEI16_V_M4_M2_MASK }, // 262 |
| 21165 | { 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVLOXEI16_V_MF2_M2_MASK }, // 263 |
| 21166 | { 0x1, 0x1, 0x4, 0x2, 0x0, PseudoVLOXEI16_V_M1_M4_MASK }, // 264 |
| 21167 | { 0x1, 0x1, 0x4, 0x2, 0x1, PseudoVLOXEI16_V_M2_M4_MASK }, // 265 |
| 21168 | { 0x1, 0x1, 0x4, 0x2, 0x2, PseudoVLOXEI16_V_M4_M4_MASK }, // 266 |
| 21169 | { 0x1, 0x1, 0x4, 0x2, 0x3, PseudoVLOXEI16_V_M8_M4_MASK }, // 267 |
| 21170 | { 0x1, 0x1, 0x4, 0x3, 0x1, PseudoVLOXEI16_V_M2_M8_MASK }, // 268 |
| 21171 | { 0x1, 0x1, 0x4, 0x3, 0x2, PseudoVLOXEI16_V_M4_M8_MASK }, // 269 |
| 21172 | { 0x1, 0x1, 0x4, 0x3, 0x3, PseudoVLOXEI16_V_M8_M8_MASK }, // 270 |
| 21173 | { 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXEI16_V_MF4_MF8_MASK }, // 271 |
| 21174 | { 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXEI16_V_MF4_MF4_MASK }, // 272 |
| 21175 | { 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXEI16_V_MF2_MF4_MASK }, // 273 |
| 21176 | { 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXEI16_V_M1_MF2_MASK }, // 274 |
| 21177 | { 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXEI16_V_MF4_MF2_MASK }, // 275 |
| 21178 | { 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXEI16_V_MF2_MF2_MASK }, // 276 |
| 21179 | { 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXEI32_V_M1_M1_MASK }, // 277 |
| 21180 | { 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXEI32_V_M2_M1_MASK }, // 278 |
| 21181 | { 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXEI32_V_M4_M1_MASK }, // 279 |
| 21182 | { 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXEI32_V_MF2_M1_MASK }, // 280 |
| 21183 | { 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVLOXEI32_V_M1_M2_MASK }, // 281 |
| 21184 | { 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVLOXEI32_V_M2_M2_MASK }, // 282 |
| 21185 | { 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVLOXEI32_V_M4_M2_MASK }, // 283 |
| 21186 | { 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVLOXEI32_V_M8_M2_MASK }, // 284 |
| 21187 | { 0x1, 0x1, 0x5, 0x2, 0x1, PseudoVLOXEI32_V_M2_M4_MASK }, // 285 |
| 21188 | { 0x1, 0x1, 0x5, 0x2, 0x2, PseudoVLOXEI32_V_M4_M4_MASK }, // 286 |
| 21189 | { 0x1, 0x1, 0x5, 0x2, 0x3, PseudoVLOXEI32_V_M8_M4_MASK }, // 287 |
| 21190 | { 0x1, 0x1, 0x5, 0x3, 0x2, PseudoVLOXEI32_V_M4_M8_MASK }, // 288 |
| 21191 | { 0x1, 0x1, 0x5, 0x3, 0x3, PseudoVLOXEI32_V_M8_M8_MASK }, // 289 |
| 21192 | { 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXEI32_V_MF2_MF8_MASK }, // 290 |
| 21193 | { 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXEI32_V_M1_MF4_MASK }, // 291 |
| 21194 | { 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXEI32_V_MF2_MF4_MASK }, // 292 |
| 21195 | { 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXEI32_V_M1_MF2_MASK }, // 293 |
| 21196 | { 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXEI32_V_M2_MF2_MASK }, // 294 |
| 21197 | { 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXEI32_V_MF2_MF2_MASK }, // 295 |
| 21198 | { 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXEI64_V_M1_M1_MASK }, // 296 |
| 21199 | { 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXEI64_V_M2_M1_MASK }, // 297 |
| 21200 | { 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXEI64_V_M4_M1_MASK }, // 298 |
| 21201 | { 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXEI64_V_M8_M1_MASK }, // 299 |
| 21202 | { 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVLOXEI64_V_M2_M2_MASK }, // 300 |
| 21203 | { 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVLOXEI64_V_M4_M2_MASK }, // 301 |
| 21204 | { 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVLOXEI64_V_M8_M2_MASK }, // 302 |
| 21205 | { 0x1, 0x1, 0x6, 0x2, 0x2, PseudoVLOXEI64_V_M4_M4_MASK }, // 303 |
| 21206 | { 0x1, 0x1, 0x6, 0x2, 0x3, PseudoVLOXEI64_V_M8_M4_MASK }, // 304 |
| 21207 | { 0x1, 0x1, 0x6, 0x3, 0x3, PseudoVLOXEI64_V_M8_M8_MASK }, // 305 |
| 21208 | { 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXEI64_V_M1_MF8_MASK }, // 306 |
| 21209 | { 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXEI64_V_M1_MF4_MASK }, // 307 |
| 21210 | { 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXEI64_V_M2_MF4_MASK }, // 308 |
| 21211 | { 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXEI64_V_M1_MF2_MASK }, // 309 |
| 21212 | { 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXEI64_V_M2_MF2_MASK }, // 310 |
| 21213 | { 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXEI64_V_M4_MF2_MASK }, // 311 |
| 21214 | }; |
| 21215 | |
| 21216 | const VLX_VSXPseudo *getVLXPseudo(uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL) { |
| 21217 | struct KeyType { |
| 21218 | uint8_t Masked; |
| 21219 | uint8_t Ordered; |
| 21220 | uint8_t Log2SEW; |
| 21221 | uint8_t LMUL; |
| 21222 | uint8_t IndexLMUL; |
| 21223 | }; |
| 21224 | KeyType Key = {Masked, Ordered, Log2SEW, LMUL, IndexLMUL}; |
| 21225 | struct Comp { |
| 21226 | bool operator()(const VLX_VSXPseudo &LHS, const KeyType &RHS) const { |
| 21227 | if (LHS.Masked < RHS.Masked) |
| 21228 | return true; |
| 21229 | if (LHS.Masked > RHS.Masked) |
| 21230 | return false; |
| 21231 | if (LHS.Ordered < RHS.Ordered) |
| 21232 | return true; |
| 21233 | if (LHS.Ordered > RHS.Ordered) |
| 21234 | return false; |
| 21235 | if (LHS.Log2SEW < RHS.Log2SEW) |
| 21236 | return true; |
| 21237 | if (LHS.Log2SEW > RHS.Log2SEW) |
| 21238 | return false; |
| 21239 | if (LHS.LMUL < RHS.LMUL) |
| 21240 | return true; |
| 21241 | if (LHS.LMUL > RHS.LMUL) |
| 21242 | return false; |
| 21243 | if (LHS.IndexLMUL < RHS.IndexLMUL) |
| 21244 | return true; |
| 21245 | if (LHS.IndexLMUL > RHS.IndexLMUL) |
| 21246 | return false; |
| 21247 | return false; |
| 21248 | } |
| 21249 | }; |
| 21250 | auto Table = ArrayRef(RISCVVLXTable); |
| 21251 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 21252 | if (Idx == Table.end() || |
| 21253 | Key.Masked != Idx->Masked || |
| 21254 | Key.Ordered != Idx->Ordered || |
| 21255 | Key.Log2SEW != Idx->Log2SEW || |
| 21256 | Key.LMUL != Idx->LMUL || |
| 21257 | Key.IndexLMUL != Idx->IndexLMUL) |
| 21258 | return nullptr; |
| 21259 | |
| 21260 | return &*Idx; |
| 21261 | } |
| 21262 | #endif |
| 21263 | |
| 21264 | #ifdef GET_RISCVVPseudosTable_DECL |
| 21265 | const PseudoInfo *getPseudoInfo(unsigned Pseudo); |
| 21266 | #endif |
| 21267 | |
| 21268 | #ifdef GET_RISCVVPseudosTable_IMPL |
| 21269 | constexpr PseudoInfo RISCVVPseudosTable[] = { |
| 21270 | { PseudoTHVdotVMAQASU_VV_M1, THVdotVMAQASU_VV }, // 0 |
| 21271 | { PseudoTHVdotVMAQASU_VV_M1_MASK, THVdotVMAQASU_VV }, // 1 |
| 21272 | { PseudoTHVdotVMAQASU_VV_M2, THVdotVMAQASU_VV }, // 2 |
| 21273 | { PseudoTHVdotVMAQASU_VV_M2_MASK, THVdotVMAQASU_VV }, // 3 |
| 21274 | { PseudoTHVdotVMAQASU_VV_M4, THVdotVMAQASU_VV }, // 4 |
| 21275 | { PseudoTHVdotVMAQASU_VV_M4_MASK, THVdotVMAQASU_VV }, // 5 |
| 21276 | { PseudoTHVdotVMAQASU_VV_M8, THVdotVMAQASU_VV }, // 6 |
| 21277 | { PseudoTHVdotVMAQASU_VV_M8_MASK, THVdotVMAQASU_VV }, // 7 |
| 21278 | { PseudoTHVdotVMAQASU_VV_MF2, THVdotVMAQASU_VV }, // 8 |
| 21279 | { PseudoTHVdotVMAQASU_VV_MF2_MASK, THVdotVMAQASU_VV }, // 9 |
| 21280 | { PseudoTHVdotVMAQASU_VX_M1, THVdotVMAQASU_VX }, // 10 |
| 21281 | { PseudoTHVdotVMAQASU_VX_M1_MASK, THVdotVMAQASU_VX }, // 11 |
| 21282 | { PseudoTHVdotVMAQASU_VX_M2, THVdotVMAQASU_VX }, // 12 |
| 21283 | { PseudoTHVdotVMAQASU_VX_M2_MASK, THVdotVMAQASU_VX }, // 13 |
| 21284 | { PseudoTHVdotVMAQASU_VX_M4, THVdotVMAQASU_VX }, // 14 |
| 21285 | { PseudoTHVdotVMAQASU_VX_M4_MASK, THVdotVMAQASU_VX }, // 15 |
| 21286 | { PseudoTHVdotVMAQASU_VX_M8, THVdotVMAQASU_VX }, // 16 |
| 21287 | { PseudoTHVdotVMAQASU_VX_M8_MASK, THVdotVMAQASU_VX }, // 17 |
| 21288 | { PseudoTHVdotVMAQASU_VX_MF2, THVdotVMAQASU_VX }, // 18 |
| 21289 | { PseudoTHVdotVMAQASU_VX_MF2_MASK, THVdotVMAQASU_VX }, // 19 |
| 21290 | { PseudoTHVdotVMAQAUS_VX_M1, THVdotVMAQAUS_VX }, // 20 |
| 21291 | { PseudoTHVdotVMAQAUS_VX_M1_MASK, THVdotVMAQAUS_VX }, // 21 |
| 21292 | { PseudoTHVdotVMAQAUS_VX_M2, THVdotVMAQAUS_VX }, // 22 |
| 21293 | { PseudoTHVdotVMAQAUS_VX_M2_MASK, THVdotVMAQAUS_VX }, // 23 |
| 21294 | { PseudoTHVdotVMAQAUS_VX_M4, THVdotVMAQAUS_VX }, // 24 |
| 21295 | { PseudoTHVdotVMAQAUS_VX_M4_MASK, THVdotVMAQAUS_VX }, // 25 |
| 21296 | { PseudoTHVdotVMAQAUS_VX_M8, THVdotVMAQAUS_VX }, // 26 |
| 21297 | { PseudoTHVdotVMAQAUS_VX_M8_MASK, THVdotVMAQAUS_VX }, // 27 |
| 21298 | { PseudoTHVdotVMAQAUS_VX_MF2, THVdotVMAQAUS_VX }, // 28 |
| 21299 | { PseudoTHVdotVMAQAUS_VX_MF2_MASK, THVdotVMAQAUS_VX }, // 29 |
| 21300 | { PseudoTHVdotVMAQAU_VV_M1, THVdotVMAQAU_VV }, // 30 |
| 21301 | { PseudoTHVdotVMAQAU_VV_M1_MASK, THVdotVMAQAU_VV }, // 31 |
| 21302 | { PseudoTHVdotVMAQAU_VV_M2, THVdotVMAQAU_VV }, // 32 |
| 21303 | { PseudoTHVdotVMAQAU_VV_M2_MASK, THVdotVMAQAU_VV }, // 33 |
| 21304 | { PseudoTHVdotVMAQAU_VV_M4, THVdotVMAQAU_VV }, // 34 |
| 21305 | { PseudoTHVdotVMAQAU_VV_M4_MASK, THVdotVMAQAU_VV }, // 35 |
| 21306 | { PseudoTHVdotVMAQAU_VV_M8, THVdotVMAQAU_VV }, // 36 |
| 21307 | { PseudoTHVdotVMAQAU_VV_M8_MASK, THVdotVMAQAU_VV }, // 37 |
| 21308 | { PseudoTHVdotVMAQAU_VV_MF2, THVdotVMAQAU_VV }, // 38 |
| 21309 | { PseudoTHVdotVMAQAU_VV_MF2_MASK, THVdotVMAQAU_VV }, // 39 |
| 21310 | { PseudoTHVdotVMAQAU_VX_M1, THVdotVMAQAU_VX }, // 40 |
| 21311 | { PseudoTHVdotVMAQAU_VX_M1_MASK, THVdotVMAQAU_VX }, // 41 |
| 21312 | { PseudoTHVdotVMAQAU_VX_M2, THVdotVMAQAU_VX }, // 42 |
| 21313 | { PseudoTHVdotVMAQAU_VX_M2_MASK, THVdotVMAQAU_VX }, // 43 |
| 21314 | { PseudoTHVdotVMAQAU_VX_M4, THVdotVMAQAU_VX }, // 44 |
| 21315 | { PseudoTHVdotVMAQAU_VX_M4_MASK, THVdotVMAQAU_VX }, // 45 |
| 21316 | { PseudoTHVdotVMAQAU_VX_M8, THVdotVMAQAU_VX }, // 46 |
| 21317 | { PseudoTHVdotVMAQAU_VX_M8_MASK, THVdotVMAQAU_VX }, // 47 |
| 21318 | { PseudoTHVdotVMAQAU_VX_MF2, THVdotVMAQAU_VX }, // 48 |
| 21319 | { PseudoTHVdotVMAQAU_VX_MF2_MASK, THVdotVMAQAU_VX }, // 49 |
| 21320 | { PseudoTHVdotVMAQA_VV_M1, THVdotVMAQA_VV }, // 50 |
| 21321 | { PseudoTHVdotVMAQA_VV_M1_MASK, THVdotVMAQA_VV }, // 51 |
| 21322 | { PseudoTHVdotVMAQA_VV_M2, THVdotVMAQA_VV }, // 52 |
| 21323 | { PseudoTHVdotVMAQA_VV_M2_MASK, THVdotVMAQA_VV }, // 53 |
| 21324 | { PseudoTHVdotVMAQA_VV_M4, THVdotVMAQA_VV }, // 54 |
| 21325 | { PseudoTHVdotVMAQA_VV_M4_MASK, THVdotVMAQA_VV }, // 55 |
| 21326 | { PseudoTHVdotVMAQA_VV_M8, THVdotVMAQA_VV }, // 56 |
| 21327 | { PseudoTHVdotVMAQA_VV_M8_MASK, THVdotVMAQA_VV }, // 57 |
| 21328 | { PseudoTHVdotVMAQA_VV_MF2, THVdotVMAQA_VV }, // 58 |
| 21329 | { PseudoTHVdotVMAQA_VV_MF2_MASK, THVdotVMAQA_VV }, // 59 |
| 21330 | { PseudoTHVdotVMAQA_VX_M1, THVdotVMAQA_VX }, // 60 |
| 21331 | { PseudoTHVdotVMAQA_VX_M1_MASK, THVdotVMAQA_VX }, // 61 |
| 21332 | { PseudoTHVdotVMAQA_VX_M2, THVdotVMAQA_VX }, // 62 |
| 21333 | { PseudoTHVdotVMAQA_VX_M2_MASK, THVdotVMAQA_VX }, // 63 |
| 21334 | { PseudoTHVdotVMAQA_VX_M4, THVdotVMAQA_VX }, // 64 |
| 21335 | { PseudoTHVdotVMAQA_VX_M4_MASK, THVdotVMAQA_VX }, // 65 |
| 21336 | { PseudoTHVdotVMAQA_VX_M8, THVdotVMAQA_VX }, // 66 |
| 21337 | { PseudoTHVdotVMAQA_VX_M8_MASK, THVdotVMAQA_VX }, // 67 |
| 21338 | { PseudoTHVdotVMAQA_VX_MF2, THVdotVMAQA_VX }, // 68 |
| 21339 | { PseudoTHVdotVMAQA_VX_MF2_MASK, THVdotVMAQA_VX }, // 69 |
| 21340 | { PseudoVAADDU_VV_M1, VAADDU_VV }, // 70 |
| 21341 | { PseudoVAADDU_VV_M1_MASK, VAADDU_VV }, // 71 |
| 21342 | { PseudoVAADDU_VV_M2, VAADDU_VV }, // 72 |
| 21343 | { PseudoVAADDU_VV_M2_MASK, VAADDU_VV }, // 73 |
| 21344 | { PseudoVAADDU_VV_M4, VAADDU_VV }, // 74 |
| 21345 | { PseudoVAADDU_VV_M4_MASK, VAADDU_VV }, // 75 |
| 21346 | { PseudoVAADDU_VV_M8, VAADDU_VV }, // 76 |
| 21347 | { PseudoVAADDU_VV_M8_MASK, VAADDU_VV }, // 77 |
| 21348 | { PseudoVAADDU_VV_MF2, VAADDU_VV }, // 78 |
| 21349 | { PseudoVAADDU_VV_MF2_MASK, VAADDU_VV }, // 79 |
| 21350 | { PseudoVAADDU_VV_MF4, VAADDU_VV }, // 80 |
| 21351 | { PseudoVAADDU_VV_MF4_MASK, VAADDU_VV }, // 81 |
| 21352 | { PseudoVAADDU_VV_MF8, VAADDU_VV }, // 82 |
| 21353 | { PseudoVAADDU_VV_MF8_MASK, VAADDU_VV }, // 83 |
| 21354 | { PseudoVAADDU_VX_M1, VAADDU_VX }, // 84 |
| 21355 | { PseudoVAADDU_VX_M1_MASK, VAADDU_VX }, // 85 |
| 21356 | { PseudoVAADDU_VX_M2, VAADDU_VX }, // 86 |
| 21357 | { PseudoVAADDU_VX_M2_MASK, VAADDU_VX }, // 87 |
| 21358 | { PseudoVAADDU_VX_M4, VAADDU_VX }, // 88 |
| 21359 | { PseudoVAADDU_VX_M4_MASK, VAADDU_VX }, // 89 |
| 21360 | { PseudoVAADDU_VX_M8, VAADDU_VX }, // 90 |
| 21361 | { PseudoVAADDU_VX_M8_MASK, VAADDU_VX }, // 91 |
| 21362 | { PseudoVAADDU_VX_MF2, VAADDU_VX }, // 92 |
| 21363 | { PseudoVAADDU_VX_MF2_MASK, VAADDU_VX }, // 93 |
| 21364 | { PseudoVAADDU_VX_MF4, VAADDU_VX }, // 94 |
| 21365 | { PseudoVAADDU_VX_MF4_MASK, VAADDU_VX }, // 95 |
| 21366 | { PseudoVAADDU_VX_MF8, VAADDU_VX }, // 96 |
| 21367 | { PseudoVAADDU_VX_MF8_MASK, VAADDU_VX }, // 97 |
| 21368 | { PseudoVAADD_VV_M1, VAADD_VV }, // 98 |
| 21369 | { PseudoVAADD_VV_M1_MASK, VAADD_VV }, // 99 |
| 21370 | { PseudoVAADD_VV_M2, VAADD_VV }, // 100 |
| 21371 | { PseudoVAADD_VV_M2_MASK, VAADD_VV }, // 101 |
| 21372 | { PseudoVAADD_VV_M4, VAADD_VV }, // 102 |
| 21373 | { PseudoVAADD_VV_M4_MASK, VAADD_VV }, // 103 |
| 21374 | { PseudoVAADD_VV_M8, VAADD_VV }, // 104 |
| 21375 | { PseudoVAADD_VV_M8_MASK, VAADD_VV }, // 105 |
| 21376 | { PseudoVAADD_VV_MF2, VAADD_VV }, // 106 |
| 21377 | { PseudoVAADD_VV_MF2_MASK, VAADD_VV }, // 107 |
| 21378 | { PseudoVAADD_VV_MF4, VAADD_VV }, // 108 |
| 21379 | { PseudoVAADD_VV_MF4_MASK, VAADD_VV }, // 109 |
| 21380 | { PseudoVAADD_VV_MF8, VAADD_VV }, // 110 |
| 21381 | { PseudoVAADD_VV_MF8_MASK, VAADD_VV }, // 111 |
| 21382 | { PseudoVAADD_VX_M1, VAADD_VX }, // 112 |
| 21383 | { PseudoVAADD_VX_M1_MASK, VAADD_VX }, // 113 |
| 21384 | { PseudoVAADD_VX_M2, VAADD_VX }, // 114 |
| 21385 | { PseudoVAADD_VX_M2_MASK, VAADD_VX }, // 115 |
| 21386 | { PseudoVAADD_VX_M4, VAADD_VX }, // 116 |
| 21387 | { PseudoVAADD_VX_M4_MASK, VAADD_VX }, // 117 |
| 21388 | { PseudoVAADD_VX_M8, VAADD_VX }, // 118 |
| 21389 | { PseudoVAADD_VX_M8_MASK, VAADD_VX }, // 119 |
| 21390 | { PseudoVAADD_VX_MF2, VAADD_VX }, // 120 |
| 21391 | { PseudoVAADD_VX_MF2_MASK, VAADD_VX }, // 121 |
| 21392 | { PseudoVAADD_VX_MF4, VAADD_VX }, // 122 |
| 21393 | { PseudoVAADD_VX_MF4_MASK, VAADD_VX }, // 123 |
| 21394 | { PseudoVAADD_VX_MF8, VAADD_VX }, // 124 |
| 21395 | { PseudoVAADD_VX_MF8_MASK, VAADD_VX }, // 125 |
| 21396 | { PseudoVADC_VIM_M1, VADC_VIM }, // 126 |
| 21397 | { PseudoVADC_VIM_M2, VADC_VIM }, // 127 |
| 21398 | { PseudoVADC_VIM_M4, VADC_VIM }, // 128 |
| 21399 | { PseudoVADC_VIM_M8, VADC_VIM }, // 129 |
| 21400 | { PseudoVADC_VIM_MF2, VADC_VIM }, // 130 |
| 21401 | { PseudoVADC_VIM_MF4, VADC_VIM }, // 131 |
| 21402 | { PseudoVADC_VIM_MF8, VADC_VIM }, // 132 |
| 21403 | { PseudoVADC_VVM_M1, VADC_VVM }, // 133 |
| 21404 | { PseudoVADC_VVM_M2, VADC_VVM }, // 134 |
| 21405 | { PseudoVADC_VVM_M4, VADC_VVM }, // 135 |
| 21406 | { PseudoVADC_VVM_M8, VADC_VVM }, // 136 |
| 21407 | { PseudoVADC_VVM_MF2, VADC_VVM }, // 137 |
| 21408 | { PseudoVADC_VVM_MF4, VADC_VVM }, // 138 |
| 21409 | { PseudoVADC_VVM_MF8, VADC_VVM }, // 139 |
| 21410 | { PseudoVADC_VXM_M1, VADC_VXM }, // 140 |
| 21411 | { PseudoVADC_VXM_M2, VADC_VXM }, // 141 |
| 21412 | { PseudoVADC_VXM_M4, VADC_VXM }, // 142 |
| 21413 | { PseudoVADC_VXM_M8, VADC_VXM }, // 143 |
| 21414 | { PseudoVADC_VXM_MF2, VADC_VXM }, // 144 |
| 21415 | { PseudoVADC_VXM_MF4, VADC_VXM }, // 145 |
| 21416 | { PseudoVADC_VXM_MF8, VADC_VXM }, // 146 |
| 21417 | { PseudoVADD_VI_M1, VADD_VI }, // 147 |
| 21418 | { PseudoVADD_VI_M1_MASK, VADD_VI }, // 148 |
| 21419 | { PseudoVADD_VI_M2, VADD_VI }, // 149 |
| 21420 | { PseudoVADD_VI_M2_MASK, VADD_VI }, // 150 |
| 21421 | { PseudoVADD_VI_M4, VADD_VI }, // 151 |
| 21422 | { PseudoVADD_VI_M4_MASK, VADD_VI }, // 152 |
| 21423 | { PseudoVADD_VI_M8, VADD_VI }, // 153 |
| 21424 | { PseudoVADD_VI_M8_MASK, VADD_VI }, // 154 |
| 21425 | { PseudoVADD_VI_MF2, VADD_VI }, // 155 |
| 21426 | { PseudoVADD_VI_MF2_MASK, VADD_VI }, // 156 |
| 21427 | { PseudoVADD_VI_MF4, VADD_VI }, // 157 |
| 21428 | { PseudoVADD_VI_MF4_MASK, VADD_VI }, // 158 |
| 21429 | { PseudoVADD_VI_MF8, VADD_VI }, // 159 |
| 21430 | { PseudoVADD_VI_MF8_MASK, VADD_VI }, // 160 |
| 21431 | { PseudoVADD_VV_M1, VADD_VV }, // 161 |
| 21432 | { PseudoVADD_VV_M1_MASK, VADD_VV }, // 162 |
| 21433 | { PseudoVADD_VV_M2, VADD_VV }, // 163 |
| 21434 | { PseudoVADD_VV_M2_MASK, VADD_VV }, // 164 |
| 21435 | { PseudoVADD_VV_M4, VADD_VV }, // 165 |
| 21436 | { PseudoVADD_VV_M4_MASK, VADD_VV }, // 166 |
| 21437 | { PseudoVADD_VV_M8, VADD_VV }, // 167 |
| 21438 | { PseudoVADD_VV_M8_MASK, VADD_VV }, // 168 |
| 21439 | { PseudoVADD_VV_MF2, VADD_VV }, // 169 |
| 21440 | { PseudoVADD_VV_MF2_MASK, VADD_VV }, // 170 |
| 21441 | { PseudoVADD_VV_MF4, VADD_VV }, // 171 |
| 21442 | { PseudoVADD_VV_MF4_MASK, VADD_VV }, // 172 |
| 21443 | { PseudoVADD_VV_MF8, VADD_VV }, // 173 |
| 21444 | { PseudoVADD_VV_MF8_MASK, VADD_VV }, // 174 |
| 21445 | { PseudoVADD_VX_M1, VADD_VX }, // 175 |
| 21446 | { PseudoVADD_VX_M1_MASK, VADD_VX }, // 176 |
| 21447 | { PseudoVADD_VX_M2, VADD_VX }, // 177 |
| 21448 | { PseudoVADD_VX_M2_MASK, VADD_VX }, // 178 |
| 21449 | { PseudoVADD_VX_M4, VADD_VX }, // 179 |
| 21450 | { PseudoVADD_VX_M4_MASK, VADD_VX }, // 180 |
| 21451 | { PseudoVADD_VX_M8, VADD_VX }, // 181 |
| 21452 | { PseudoVADD_VX_M8_MASK, VADD_VX }, // 182 |
| 21453 | { PseudoVADD_VX_MF2, VADD_VX }, // 183 |
| 21454 | { PseudoVADD_VX_MF2_MASK, VADD_VX }, // 184 |
| 21455 | { PseudoVADD_VX_MF4, VADD_VX }, // 185 |
| 21456 | { PseudoVADD_VX_MF4_MASK, VADD_VX }, // 186 |
| 21457 | { PseudoVADD_VX_MF8, VADD_VX }, // 187 |
| 21458 | { PseudoVADD_VX_MF8_MASK, VADD_VX }, // 188 |
| 21459 | { PseudoVAESDF_VS_M1_M1, VAESDF_VS }, // 189 |
| 21460 | { PseudoVAESDF_VS_M1_MF2, VAESDF_VS }, // 190 |
| 21461 | { PseudoVAESDF_VS_M1_MF4, VAESDF_VS }, // 191 |
| 21462 | { PseudoVAESDF_VS_M1_MF8, VAESDF_VS }, // 192 |
| 21463 | { PseudoVAESDF_VS_M2_M1, VAESDF_VS }, // 193 |
| 21464 | { PseudoVAESDF_VS_M2_M2, VAESDF_VS }, // 194 |
| 21465 | { PseudoVAESDF_VS_M2_MF2, VAESDF_VS }, // 195 |
| 21466 | { PseudoVAESDF_VS_M2_MF4, VAESDF_VS }, // 196 |
| 21467 | { PseudoVAESDF_VS_M2_MF8, VAESDF_VS }, // 197 |
| 21468 | { PseudoVAESDF_VS_M4_M1, VAESDF_VS }, // 198 |
| 21469 | { PseudoVAESDF_VS_M4_M2, VAESDF_VS }, // 199 |
| 21470 | { PseudoVAESDF_VS_M4_M4, VAESDF_VS }, // 200 |
| 21471 | { PseudoVAESDF_VS_M4_MF2, VAESDF_VS }, // 201 |
| 21472 | { PseudoVAESDF_VS_M4_MF4, VAESDF_VS }, // 202 |
| 21473 | { PseudoVAESDF_VS_M4_MF8, VAESDF_VS }, // 203 |
| 21474 | { PseudoVAESDF_VS_M8_M1, VAESDF_VS }, // 204 |
| 21475 | { PseudoVAESDF_VS_M8_M2, VAESDF_VS }, // 205 |
| 21476 | { PseudoVAESDF_VS_M8_M4, VAESDF_VS }, // 206 |
| 21477 | { PseudoVAESDF_VS_M8_MF2, VAESDF_VS }, // 207 |
| 21478 | { PseudoVAESDF_VS_M8_MF4, VAESDF_VS }, // 208 |
| 21479 | { PseudoVAESDF_VS_M8_MF8, VAESDF_VS }, // 209 |
| 21480 | { PseudoVAESDF_VS_MF2_MF2, VAESDF_VS }, // 210 |
| 21481 | { PseudoVAESDF_VS_MF2_MF4, VAESDF_VS }, // 211 |
| 21482 | { PseudoVAESDF_VS_MF2_MF8, VAESDF_VS }, // 212 |
| 21483 | { PseudoVAESDF_VV_M1, VAESDF_VV }, // 213 |
| 21484 | { PseudoVAESDF_VV_M2, VAESDF_VV }, // 214 |
| 21485 | { PseudoVAESDF_VV_M4, VAESDF_VV }, // 215 |
| 21486 | { PseudoVAESDF_VV_M8, VAESDF_VV }, // 216 |
| 21487 | { PseudoVAESDF_VV_MF2, VAESDF_VV }, // 217 |
| 21488 | { PseudoVAESDM_VS_M1_M1, VAESDM_VS }, // 218 |
| 21489 | { PseudoVAESDM_VS_M1_MF2, VAESDM_VS }, // 219 |
| 21490 | { PseudoVAESDM_VS_M1_MF4, VAESDM_VS }, // 220 |
| 21491 | { PseudoVAESDM_VS_M1_MF8, VAESDM_VS }, // 221 |
| 21492 | { PseudoVAESDM_VS_M2_M1, VAESDM_VS }, // 222 |
| 21493 | { PseudoVAESDM_VS_M2_M2, VAESDM_VS }, // 223 |
| 21494 | { PseudoVAESDM_VS_M2_MF2, VAESDM_VS }, // 224 |
| 21495 | { PseudoVAESDM_VS_M2_MF4, VAESDM_VS }, // 225 |
| 21496 | { PseudoVAESDM_VS_M2_MF8, VAESDM_VS }, // 226 |
| 21497 | { PseudoVAESDM_VS_M4_M1, VAESDM_VS }, // 227 |
| 21498 | { PseudoVAESDM_VS_M4_M2, VAESDM_VS }, // 228 |
| 21499 | { PseudoVAESDM_VS_M4_M4, VAESDM_VS }, // 229 |
| 21500 | { PseudoVAESDM_VS_M4_MF2, VAESDM_VS }, // 230 |
| 21501 | { PseudoVAESDM_VS_M4_MF4, VAESDM_VS }, // 231 |
| 21502 | { PseudoVAESDM_VS_M4_MF8, VAESDM_VS }, // 232 |
| 21503 | { PseudoVAESDM_VS_M8_M1, VAESDM_VS }, // 233 |
| 21504 | { PseudoVAESDM_VS_M8_M2, VAESDM_VS }, // 234 |
| 21505 | { PseudoVAESDM_VS_M8_M4, VAESDM_VS }, // 235 |
| 21506 | { PseudoVAESDM_VS_M8_MF2, VAESDM_VS }, // 236 |
| 21507 | { PseudoVAESDM_VS_M8_MF4, VAESDM_VS }, // 237 |
| 21508 | { PseudoVAESDM_VS_M8_MF8, VAESDM_VS }, // 238 |
| 21509 | { PseudoVAESDM_VS_MF2_MF2, VAESDM_VS }, // 239 |
| 21510 | { PseudoVAESDM_VS_MF2_MF4, VAESDM_VS }, // 240 |
| 21511 | { PseudoVAESDM_VS_MF2_MF8, VAESDM_VS }, // 241 |
| 21512 | { PseudoVAESDM_VV_M1, VAESDM_VV }, // 242 |
| 21513 | { PseudoVAESDM_VV_M2, VAESDM_VV }, // 243 |
| 21514 | { PseudoVAESDM_VV_M4, VAESDM_VV }, // 244 |
| 21515 | { PseudoVAESDM_VV_M8, VAESDM_VV }, // 245 |
| 21516 | { PseudoVAESDM_VV_MF2, VAESDM_VV }, // 246 |
| 21517 | { PseudoVAESEF_VS_M1_M1, VAESEF_VS }, // 247 |
| 21518 | { PseudoVAESEF_VS_M1_MF2, VAESEF_VS }, // 248 |
| 21519 | { PseudoVAESEF_VS_M1_MF4, VAESEF_VS }, // 249 |
| 21520 | { PseudoVAESEF_VS_M1_MF8, VAESEF_VS }, // 250 |
| 21521 | { PseudoVAESEF_VS_M2_M1, VAESEF_VS }, // 251 |
| 21522 | { PseudoVAESEF_VS_M2_M2, VAESEF_VS }, // 252 |
| 21523 | { PseudoVAESEF_VS_M2_MF2, VAESEF_VS }, // 253 |
| 21524 | { PseudoVAESEF_VS_M2_MF4, VAESEF_VS }, // 254 |
| 21525 | { PseudoVAESEF_VS_M2_MF8, VAESEF_VS }, // 255 |
| 21526 | { PseudoVAESEF_VS_M4_M1, VAESEF_VS }, // 256 |
| 21527 | { PseudoVAESEF_VS_M4_M2, VAESEF_VS }, // 257 |
| 21528 | { PseudoVAESEF_VS_M4_M4, VAESEF_VS }, // 258 |
| 21529 | { PseudoVAESEF_VS_M4_MF2, VAESEF_VS }, // 259 |
| 21530 | { PseudoVAESEF_VS_M4_MF4, VAESEF_VS }, // 260 |
| 21531 | { PseudoVAESEF_VS_M4_MF8, VAESEF_VS }, // 261 |
| 21532 | { PseudoVAESEF_VS_M8_M1, VAESEF_VS }, // 262 |
| 21533 | { PseudoVAESEF_VS_M8_M2, VAESEF_VS }, // 263 |
| 21534 | { PseudoVAESEF_VS_M8_M4, VAESEF_VS }, // 264 |
| 21535 | { PseudoVAESEF_VS_M8_MF2, VAESEF_VS }, // 265 |
| 21536 | { PseudoVAESEF_VS_M8_MF4, VAESEF_VS }, // 266 |
| 21537 | { PseudoVAESEF_VS_M8_MF8, VAESEF_VS }, // 267 |
| 21538 | { PseudoVAESEF_VS_MF2_MF2, VAESEF_VS }, // 268 |
| 21539 | { PseudoVAESEF_VS_MF2_MF4, VAESEF_VS }, // 269 |
| 21540 | { PseudoVAESEF_VS_MF2_MF8, VAESEF_VS }, // 270 |
| 21541 | { PseudoVAESEF_VV_M1, VAESEF_VV }, // 271 |
| 21542 | { PseudoVAESEF_VV_M2, VAESEF_VV }, // 272 |
| 21543 | { PseudoVAESEF_VV_M4, VAESEF_VV }, // 273 |
| 21544 | { PseudoVAESEF_VV_M8, VAESEF_VV }, // 274 |
| 21545 | { PseudoVAESEF_VV_MF2, VAESEF_VV }, // 275 |
| 21546 | { PseudoVAESEM_VS_M1_M1, VAESEM_VS }, // 276 |
| 21547 | { PseudoVAESEM_VS_M1_MF2, VAESEM_VS }, // 277 |
| 21548 | { PseudoVAESEM_VS_M1_MF4, VAESEM_VS }, // 278 |
| 21549 | { PseudoVAESEM_VS_M1_MF8, VAESEM_VS }, // 279 |
| 21550 | { PseudoVAESEM_VS_M2_M1, VAESEM_VS }, // 280 |
| 21551 | { PseudoVAESEM_VS_M2_M2, VAESEM_VS }, // 281 |
| 21552 | { PseudoVAESEM_VS_M2_MF2, VAESEM_VS }, // 282 |
| 21553 | { PseudoVAESEM_VS_M2_MF4, VAESEM_VS }, // 283 |
| 21554 | { PseudoVAESEM_VS_M2_MF8, VAESEM_VS }, // 284 |
| 21555 | { PseudoVAESEM_VS_M4_M1, VAESEM_VS }, // 285 |
| 21556 | { PseudoVAESEM_VS_M4_M2, VAESEM_VS }, // 286 |
| 21557 | { PseudoVAESEM_VS_M4_M4, VAESEM_VS }, // 287 |
| 21558 | { PseudoVAESEM_VS_M4_MF2, VAESEM_VS }, // 288 |
| 21559 | { PseudoVAESEM_VS_M4_MF4, VAESEM_VS }, // 289 |
| 21560 | { PseudoVAESEM_VS_M4_MF8, VAESEM_VS }, // 290 |
| 21561 | { PseudoVAESEM_VS_M8_M1, VAESEM_VS }, // 291 |
| 21562 | { PseudoVAESEM_VS_M8_M2, VAESEM_VS }, // 292 |
| 21563 | { PseudoVAESEM_VS_M8_M4, VAESEM_VS }, // 293 |
| 21564 | { PseudoVAESEM_VS_M8_MF2, VAESEM_VS }, // 294 |
| 21565 | { PseudoVAESEM_VS_M8_MF4, VAESEM_VS }, // 295 |
| 21566 | { PseudoVAESEM_VS_M8_MF8, VAESEM_VS }, // 296 |
| 21567 | { PseudoVAESEM_VS_MF2_MF2, VAESEM_VS }, // 297 |
| 21568 | { PseudoVAESEM_VS_MF2_MF4, VAESEM_VS }, // 298 |
| 21569 | { PseudoVAESEM_VS_MF2_MF8, VAESEM_VS }, // 299 |
| 21570 | { PseudoVAESEM_VV_M1, VAESEM_VV }, // 300 |
| 21571 | { PseudoVAESEM_VV_M2, VAESEM_VV }, // 301 |
| 21572 | { PseudoVAESEM_VV_M4, VAESEM_VV }, // 302 |
| 21573 | { PseudoVAESEM_VV_M8, VAESEM_VV }, // 303 |
| 21574 | { PseudoVAESEM_VV_MF2, VAESEM_VV }, // 304 |
| 21575 | { PseudoVAESKF1_VI_M1, VAESKF1_VI }, // 305 |
| 21576 | { PseudoVAESKF1_VI_M2, VAESKF1_VI }, // 306 |
| 21577 | { PseudoVAESKF1_VI_M4, VAESKF1_VI }, // 307 |
| 21578 | { PseudoVAESKF1_VI_M8, VAESKF1_VI }, // 308 |
| 21579 | { PseudoVAESKF1_VI_MF2, VAESKF1_VI }, // 309 |
| 21580 | { PseudoVAESKF2_VI_M1, VAESKF2_VI }, // 310 |
| 21581 | { PseudoVAESKF2_VI_M2, VAESKF2_VI }, // 311 |
| 21582 | { PseudoVAESKF2_VI_M4, VAESKF2_VI }, // 312 |
| 21583 | { PseudoVAESKF2_VI_M8, VAESKF2_VI }, // 313 |
| 21584 | { PseudoVAESKF2_VI_MF2, VAESKF2_VI }, // 314 |
| 21585 | { PseudoVAESZ_VS_M1_M1, VAESZ_VS }, // 315 |
| 21586 | { PseudoVAESZ_VS_M1_MF2, VAESZ_VS }, // 316 |
| 21587 | { PseudoVAESZ_VS_M1_MF4, VAESZ_VS }, // 317 |
| 21588 | { PseudoVAESZ_VS_M1_MF8, VAESZ_VS }, // 318 |
| 21589 | { PseudoVAESZ_VS_M2_M1, VAESZ_VS }, // 319 |
| 21590 | { PseudoVAESZ_VS_M2_M2, VAESZ_VS }, // 320 |
| 21591 | { PseudoVAESZ_VS_M2_MF2, VAESZ_VS }, // 321 |
| 21592 | { PseudoVAESZ_VS_M2_MF4, VAESZ_VS }, // 322 |
| 21593 | { PseudoVAESZ_VS_M2_MF8, VAESZ_VS }, // 323 |
| 21594 | { PseudoVAESZ_VS_M4_M1, VAESZ_VS }, // 324 |
| 21595 | { PseudoVAESZ_VS_M4_M2, VAESZ_VS }, // 325 |
| 21596 | { PseudoVAESZ_VS_M4_M4, VAESZ_VS }, // 326 |
| 21597 | { PseudoVAESZ_VS_M4_MF2, VAESZ_VS }, // 327 |
| 21598 | { PseudoVAESZ_VS_M4_MF4, VAESZ_VS }, // 328 |
| 21599 | { PseudoVAESZ_VS_M4_MF8, VAESZ_VS }, // 329 |
| 21600 | { PseudoVAESZ_VS_M8_M1, VAESZ_VS }, // 330 |
| 21601 | { PseudoVAESZ_VS_M8_M2, VAESZ_VS }, // 331 |
| 21602 | { PseudoVAESZ_VS_M8_M4, VAESZ_VS }, // 332 |
| 21603 | { PseudoVAESZ_VS_M8_MF2, VAESZ_VS }, // 333 |
| 21604 | { PseudoVAESZ_VS_M8_MF4, VAESZ_VS }, // 334 |
| 21605 | { PseudoVAESZ_VS_M8_MF8, VAESZ_VS }, // 335 |
| 21606 | { PseudoVAESZ_VS_MF2_MF2, VAESZ_VS }, // 336 |
| 21607 | { PseudoVAESZ_VS_MF2_MF4, VAESZ_VS }, // 337 |
| 21608 | { PseudoVAESZ_VS_MF2_MF8, VAESZ_VS }, // 338 |
| 21609 | { PseudoVANDN_VV_M1, VANDN_VV }, // 339 |
| 21610 | { PseudoVANDN_VV_M1_MASK, VANDN_VV }, // 340 |
| 21611 | { PseudoVANDN_VV_M2, VANDN_VV }, // 341 |
| 21612 | { PseudoVANDN_VV_M2_MASK, VANDN_VV }, // 342 |
| 21613 | { PseudoVANDN_VV_M4, VANDN_VV }, // 343 |
| 21614 | { PseudoVANDN_VV_M4_MASK, VANDN_VV }, // 344 |
| 21615 | { PseudoVANDN_VV_M8, VANDN_VV }, // 345 |
| 21616 | { PseudoVANDN_VV_M8_MASK, VANDN_VV }, // 346 |
| 21617 | { PseudoVANDN_VV_MF2, VANDN_VV }, // 347 |
| 21618 | { PseudoVANDN_VV_MF2_MASK, VANDN_VV }, // 348 |
| 21619 | { PseudoVANDN_VV_MF4, VANDN_VV }, // 349 |
| 21620 | { PseudoVANDN_VV_MF4_MASK, VANDN_VV }, // 350 |
| 21621 | { PseudoVANDN_VV_MF8, VANDN_VV }, // 351 |
| 21622 | { PseudoVANDN_VV_MF8_MASK, VANDN_VV }, // 352 |
| 21623 | { PseudoVANDN_VX_M1, VANDN_VX }, // 353 |
| 21624 | { PseudoVANDN_VX_M1_MASK, VANDN_VX }, // 354 |
| 21625 | { PseudoVANDN_VX_M2, VANDN_VX }, // 355 |
| 21626 | { PseudoVANDN_VX_M2_MASK, VANDN_VX }, // 356 |
| 21627 | { PseudoVANDN_VX_M4, VANDN_VX }, // 357 |
| 21628 | { PseudoVANDN_VX_M4_MASK, VANDN_VX }, // 358 |
| 21629 | { PseudoVANDN_VX_M8, VANDN_VX }, // 359 |
| 21630 | { PseudoVANDN_VX_M8_MASK, VANDN_VX }, // 360 |
| 21631 | { PseudoVANDN_VX_MF2, VANDN_VX }, // 361 |
| 21632 | { PseudoVANDN_VX_MF2_MASK, VANDN_VX }, // 362 |
| 21633 | { PseudoVANDN_VX_MF4, VANDN_VX }, // 363 |
| 21634 | { PseudoVANDN_VX_MF4_MASK, VANDN_VX }, // 364 |
| 21635 | { PseudoVANDN_VX_MF8, VANDN_VX }, // 365 |
| 21636 | { PseudoVANDN_VX_MF8_MASK, VANDN_VX }, // 366 |
| 21637 | { PseudoVAND_VI_M1, VAND_VI }, // 367 |
| 21638 | { PseudoVAND_VI_M1_MASK, VAND_VI }, // 368 |
| 21639 | { PseudoVAND_VI_M2, VAND_VI }, // 369 |
| 21640 | { PseudoVAND_VI_M2_MASK, VAND_VI }, // 370 |
| 21641 | { PseudoVAND_VI_M4, VAND_VI }, // 371 |
| 21642 | { PseudoVAND_VI_M4_MASK, VAND_VI }, // 372 |
| 21643 | { PseudoVAND_VI_M8, VAND_VI }, // 373 |
| 21644 | { PseudoVAND_VI_M8_MASK, VAND_VI }, // 374 |
| 21645 | { PseudoVAND_VI_MF2, VAND_VI }, // 375 |
| 21646 | { PseudoVAND_VI_MF2_MASK, VAND_VI }, // 376 |
| 21647 | { PseudoVAND_VI_MF4, VAND_VI }, // 377 |
| 21648 | { PseudoVAND_VI_MF4_MASK, VAND_VI }, // 378 |
| 21649 | { PseudoVAND_VI_MF8, VAND_VI }, // 379 |
| 21650 | { PseudoVAND_VI_MF8_MASK, VAND_VI }, // 380 |
| 21651 | { PseudoVAND_VV_M1, VAND_VV }, // 381 |
| 21652 | { PseudoVAND_VV_M1_MASK, VAND_VV }, // 382 |
| 21653 | { PseudoVAND_VV_M2, VAND_VV }, // 383 |
| 21654 | { PseudoVAND_VV_M2_MASK, VAND_VV }, // 384 |
| 21655 | { PseudoVAND_VV_M4, VAND_VV }, // 385 |
| 21656 | { PseudoVAND_VV_M4_MASK, VAND_VV }, // 386 |
| 21657 | { PseudoVAND_VV_M8, VAND_VV }, // 387 |
| 21658 | { PseudoVAND_VV_M8_MASK, VAND_VV }, // 388 |
| 21659 | { PseudoVAND_VV_MF2, VAND_VV }, // 389 |
| 21660 | { PseudoVAND_VV_MF2_MASK, VAND_VV }, // 390 |
| 21661 | { PseudoVAND_VV_MF4, VAND_VV }, // 391 |
| 21662 | { PseudoVAND_VV_MF4_MASK, VAND_VV }, // 392 |
| 21663 | { PseudoVAND_VV_MF8, VAND_VV }, // 393 |
| 21664 | { PseudoVAND_VV_MF8_MASK, VAND_VV }, // 394 |
| 21665 | { PseudoVAND_VX_M1, VAND_VX }, // 395 |
| 21666 | { PseudoVAND_VX_M1_MASK, VAND_VX }, // 396 |
| 21667 | { PseudoVAND_VX_M2, VAND_VX }, // 397 |
| 21668 | { PseudoVAND_VX_M2_MASK, VAND_VX }, // 398 |
| 21669 | { PseudoVAND_VX_M4, VAND_VX }, // 399 |
| 21670 | { PseudoVAND_VX_M4_MASK, VAND_VX }, // 400 |
| 21671 | { PseudoVAND_VX_M8, VAND_VX }, // 401 |
| 21672 | { PseudoVAND_VX_M8_MASK, VAND_VX }, // 402 |
| 21673 | { PseudoVAND_VX_MF2, VAND_VX }, // 403 |
| 21674 | { PseudoVAND_VX_MF2_MASK, VAND_VX }, // 404 |
| 21675 | { PseudoVAND_VX_MF4, VAND_VX }, // 405 |
| 21676 | { PseudoVAND_VX_MF4_MASK, VAND_VX }, // 406 |
| 21677 | { PseudoVAND_VX_MF8, VAND_VX }, // 407 |
| 21678 | { PseudoVAND_VX_MF8_MASK, VAND_VX }, // 408 |
| 21679 | { PseudoVASUBU_VV_M1, VASUBU_VV }, // 409 |
| 21680 | { PseudoVASUBU_VV_M1_MASK, VASUBU_VV }, // 410 |
| 21681 | { PseudoVASUBU_VV_M2, VASUBU_VV }, // 411 |
| 21682 | { PseudoVASUBU_VV_M2_MASK, VASUBU_VV }, // 412 |
| 21683 | { PseudoVASUBU_VV_M4, VASUBU_VV }, // 413 |
| 21684 | { PseudoVASUBU_VV_M4_MASK, VASUBU_VV }, // 414 |
| 21685 | { PseudoVASUBU_VV_M8, VASUBU_VV }, // 415 |
| 21686 | { PseudoVASUBU_VV_M8_MASK, VASUBU_VV }, // 416 |
| 21687 | { PseudoVASUBU_VV_MF2, VASUBU_VV }, // 417 |
| 21688 | { PseudoVASUBU_VV_MF2_MASK, VASUBU_VV }, // 418 |
| 21689 | { PseudoVASUBU_VV_MF4, VASUBU_VV }, // 419 |
| 21690 | { PseudoVASUBU_VV_MF4_MASK, VASUBU_VV }, // 420 |
| 21691 | { PseudoVASUBU_VV_MF8, VASUBU_VV }, // 421 |
| 21692 | { PseudoVASUBU_VV_MF8_MASK, VASUBU_VV }, // 422 |
| 21693 | { PseudoVASUBU_VX_M1, VASUBU_VX }, // 423 |
| 21694 | { PseudoVASUBU_VX_M1_MASK, VASUBU_VX }, // 424 |
| 21695 | { PseudoVASUBU_VX_M2, VASUBU_VX }, // 425 |
| 21696 | { PseudoVASUBU_VX_M2_MASK, VASUBU_VX }, // 426 |
| 21697 | { PseudoVASUBU_VX_M4, VASUBU_VX }, // 427 |
| 21698 | { PseudoVASUBU_VX_M4_MASK, VASUBU_VX }, // 428 |
| 21699 | { PseudoVASUBU_VX_M8, VASUBU_VX }, // 429 |
| 21700 | { PseudoVASUBU_VX_M8_MASK, VASUBU_VX }, // 430 |
| 21701 | { PseudoVASUBU_VX_MF2, VASUBU_VX }, // 431 |
| 21702 | { PseudoVASUBU_VX_MF2_MASK, VASUBU_VX }, // 432 |
| 21703 | { PseudoVASUBU_VX_MF4, VASUBU_VX }, // 433 |
| 21704 | { PseudoVASUBU_VX_MF4_MASK, VASUBU_VX }, // 434 |
| 21705 | { PseudoVASUBU_VX_MF8, VASUBU_VX }, // 435 |
| 21706 | { PseudoVASUBU_VX_MF8_MASK, VASUBU_VX }, // 436 |
| 21707 | { PseudoVASUB_VV_M1, VASUB_VV }, // 437 |
| 21708 | { PseudoVASUB_VV_M1_MASK, VASUB_VV }, // 438 |
| 21709 | { PseudoVASUB_VV_M2, VASUB_VV }, // 439 |
| 21710 | { PseudoVASUB_VV_M2_MASK, VASUB_VV }, // 440 |
| 21711 | { PseudoVASUB_VV_M4, VASUB_VV }, // 441 |
| 21712 | { PseudoVASUB_VV_M4_MASK, VASUB_VV }, // 442 |
| 21713 | { PseudoVASUB_VV_M8, VASUB_VV }, // 443 |
| 21714 | { PseudoVASUB_VV_M8_MASK, VASUB_VV }, // 444 |
| 21715 | { PseudoVASUB_VV_MF2, VASUB_VV }, // 445 |
| 21716 | { PseudoVASUB_VV_MF2_MASK, VASUB_VV }, // 446 |
| 21717 | { PseudoVASUB_VV_MF4, VASUB_VV }, // 447 |
| 21718 | { PseudoVASUB_VV_MF4_MASK, VASUB_VV }, // 448 |
| 21719 | { PseudoVASUB_VV_MF8, VASUB_VV }, // 449 |
| 21720 | { PseudoVASUB_VV_MF8_MASK, VASUB_VV }, // 450 |
| 21721 | { PseudoVASUB_VX_M1, VASUB_VX }, // 451 |
| 21722 | { PseudoVASUB_VX_M1_MASK, VASUB_VX }, // 452 |
| 21723 | { PseudoVASUB_VX_M2, VASUB_VX }, // 453 |
| 21724 | { PseudoVASUB_VX_M2_MASK, VASUB_VX }, // 454 |
| 21725 | { PseudoVASUB_VX_M4, VASUB_VX }, // 455 |
| 21726 | { PseudoVASUB_VX_M4_MASK, VASUB_VX }, // 456 |
| 21727 | { PseudoVASUB_VX_M8, VASUB_VX }, // 457 |
| 21728 | { PseudoVASUB_VX_M8_MASK, VASUB_VX }, // 458 |
| 21729 | { PseudoVASUB_VX_MF2, VASUB_VX }, // 459 |
| 21730 | { PseudoVASUB_VX_MF2_MASK, VASUB_VX }, // 460 |
| 21731 | { PseudoVASUB_VX_MF4, VASUB_VX }, // 461 |
| 21732 | { PseudoVASUB_VX_MF4_MASK, VASUB_VX }, // 462 |
| 21733 | { PseudoVASUB_VX_MF8, VASUB_VX }, // 463 |
| 21734 | { PseudoVASUB_VX_MF8_MASK, VASUB_VX }, // 464 |
| 21735 | { PseudoVBREV8_V_M1, VBREV8_V }, // 465 |
| 21736 | { PseudoVBREV8_V_M1_MASK, VBREV8_V }, // 466 |
| 21737 | { PseudoVBREV8_V_M2, VBREV8_V }, // 467 |
| 21738 | { PseudoVBREV8_V_M2_MASK, VBREV8_V }, // 468 |
| 21739 | { PseudoVBREV8_V_M4, VBREV8_V }, // 469 |
| 21740 | { PseudoVBREV8_V_M4_MASK, VBREV8_V }, // 470 |
| 21741 | { PseudoVBREV8_V_M8, VBREV8_V }, // 471 |
| 21742 | { PseudoVBREV8_V_M8_MASK, VBREV8_V }, // 472 |
| 21743 | { PseudoVBREV8_V_MF2, VBREV8_V }, // 473 |
| 21744 | { PseudoVBREV8_V_MF2_MASK, VBREV8_V }, // 474 |
| 21745 | { PseudoVBREV8_V_MF4, VBREV8_V }, // 475 |
| 21746 | { PseudoVBREV8_V_MF4_MASK, VBREV8_V }, // 476 |
| 21747 | { PseudoVBREV8_V_MF8, VBREV8_V }, // 477 |
| 21748 | { PseudoVBREV8_V_MF8_MASK, VBREV8_V }, // 478 |
| 21749 | { PseudoVBREV_V_M1, VBREV_V }, // 479 |
| 21750 | { PseudoVBREV_V_M1_MASK, VBREV_V }, // 480 |
| 21751 | { PseudoVBREV_V_M2, VBREV_V }, // 481 |
| 21752 | { PseudoVBREV_V_M2_MASK, VBREV_V }, // 482 |
| 21753 | { PseudoVBREV_V_M4, VBREV_V }, // 483 |
| 21754 | { PseudoVBREV_V_M4_MASK, VBREV_V }, // 484 |
| 21755 | { PseudoVBREV_V_M8, VBREV_V }, // 485 |
| 21756 | { PseudoVBREV_V_M8_MASK, VBREV_V }, // 486 |
| 21757 | { PseudoVBREV_V_MF2, VBREV_V }, // 487 |
| 21758 | { PseudoVBREV_V_MF2_MASK, VBREV_V }, // 488 |
| 21759 | { PseudoVBREV_V_MF4, VBREV_V }, // 489 |
| 21760 | { PseudoVBREV_V_MF4_MASK, VBREV_V }, // 490 |
| 21761 | { PseudoVBREV_V_MF8, VBREV_V }, // 491 |
| 21762 | { PseudoVBREV_V_MF8_MASK, VBREV_V }, // 492 |
| 21763 | { PseudoVCLMULH_VV_M1, VCLMULH_VV }, // 493 |
| 21764 | { PseudoVCLMULH_VV_M1_MASK, VCLMULH_VV }, // 494 |
| 21765 | { PseudoVCLMULH_VV_M2, VCLMULH_VV }, // 495 |
| 21766 | { PseudoVCLMULH_VV_M2_MASK, VCLMULH_VV }, // 496 |
| 21767 | { PseudoVCLMULH_VV_M4, VCLMULH_VV }, // 497 |
| 21768 | { PseudoVCLMULH_VV_M4_MASK, VCLMULH_VV }, // 498 |
| 21769 | { PseudoVCLMULH_VV_M8, VCLMULH_VV }, // 499 |
| 21770 | { PseudoVCLMULH_VV_M8_MASK, VCLMULH_VV }, // 500 |
| 21771 | { PseudoVCLMULH_VV_MF2, VCLMULH_VV }, // 501 |
| 21772 | { PseudoVCLMULH_VV_MF2_MASK, VCLMULH_VV }, // 502 |
| 21773 | { PseudoVCLMULH_VV_MF4, VCLMULH_VV }, // 503 |
| 21774 | { PseudoVCLMULH_VV_MF4_MASK, VCLMULH_VV }, // 504 |
| 21775 | { PseudoVCLMULH_VV_MF8, VCLMULH_VV }, // 505 |
| 21776 | { PseudoVCLMULH_VV_MF8_MASK, VCLMULH_VV }, // 506 |
| 21777 | { PseudoVCLMULH_VX_M1, VCLMULH_VX }, // 507 |
| 21778 | { PseudoVCLMULH_VX_M1_MASK, VCLMULH_VX }, // 508 |
| 21779 | { PseudoVCLMULH_VX_M2, VCLMULH_VX }, // 509 |
| 21780 | { PseudoVCLMULH_VX_M2_MASK, VCLMULH_VX }, // 510 |
| 21781 | { PseudoVCLMULH_VX_M4, VCLMULH_VX }, // 511 |
| 21782 | { PseudoVCLMULH_VX_M4_MASK, VCLMULH_VX }, // 512 |
| 21783 | { PseudoVCLMULH_VX_M8, VCLMULH_VX }, // 513 |
| 21784 | { PseudoVCLMULH_VX_M8_MASK, VCLMULH_VX }, // 514 |
| 21785 | { PseudoVCLMULH_VX_MF2, VCLMULH_VX }, // 515 |
| 21786 | { PseudoVCLMULH_VX_MF2_MASK, VCLMULH_VX }, // 516 |
| 21787 | { PseudoVCLMULH_VX_MF4, VCLMULH_VX }, // 517 |
| 21788 | { PseudoVCLMULH_VX_MF4_MASK, VCLMULH_VX }, // 518 |
| 21789 | { PseudoVCLMULH_VX_MF8, VCLMULH_VX }, // 519 |
| 21790 | { PseudoVCLMULH_VX_MF8_MASK, VCLMULH_VX }, // 520 |
| 21791 | { PseudoVCLMUL_VV_M1, VCLMUL_VV }, // 521 |
| 21792 | { PseudoVCLMUL_VV_M1_MASK, VCLMUL_VV }, // 522 |
| 21793 | { PseudoVCLMUL_VV_M2, VCLMUL_VV }, // 523 |
| 21794 | { PseudoVCLMUL_VV_M2_MASK, VCLMUL_VV }, // 524 |
| 21795 | { PseudoVCLMUL_VV_M4, VCLMUL_VV }, // 525 |
| 21796 | { PseudoVCLMUL_VV_M4_MASK, VCLMUL_VV }, // 526 |
| 21797 | { PseudoVCLMUL_VV_M8, VCLMUL_VV }, // 527 |
| 21798 | { PseudoVCLMUL_VV_M8_MASK, VCLMUL_VV }, // 528 |
| 21799 | { PseudoVCLMUL_VV_MF2, VCLMUL_VV }, // 529 |
| 21800 | { PseudoVCLMUL_VV_MF2_MASK, VCLMUL_VV }, // 530 |
| 21801 | { PseudoVCLMUL_VV_MF4, VCLMUL_VV }, // 531 |
| 21802 | { PseudoVCLMUL_VV_MF4_MASK, VCLMUL_VV }, // 532 |
| 21803 | { PseudoVCLMUL_VV_MF8, VCLMUL_VV }, // 533 |
| 21804 | { PseudoVCLMUL_VV_MF8_MASK, VCLMUL_VV }, // 534 |
| 21805 | { PseudoVCLMUL_VX_M1, VCLMUL_VX }, // 535 |
| 21806 | { PseudoVCLMUL_VX_M1_MASK, VCLMUL_VX }, // 536 |
| 21807 | { PseudoVCLMUL_VX_M2, VCLMUL_VX }, // 537 |
| 21808 | { PseudoVCLMUL_VX_M2_MASK, VCLMUL_VX }, // 538 |
| 21809 | { PseudoVCLMUL_VX_M4, VCLMUL_VX }, // 539 |
| 21810 | { PseudoVCLMUL_VX_M4_MASK, VCLMUL_VX }, // 540 |
| 21811 | { PseudoVCLMUL_VX_M8, VCLMUL_VX }, // 541 |
| 21812 | { PseudoVCLMUL_VX_M8_MASK, VCLMUL_VX }, // 542 |
| 21813 | { PseudoVCLMUL_VX_MF2, VCLMUL_VX }, // 543 |
| 21814 | { PseudoVCLMUL_VX_MF2_MASK, VCLMUL_VX }, // 544 |
| 21815 | { PseudoVCLMUL_VX_MF4, VCLMUL_VX }, // 545 |
| 21816 | { PseudoVCLMUL_VX_MF4_MASK, VCLMUL_VX }, // 546 |
| 21817 | { PseudoVCLMUL_VX_MF8, VCLMUL_VX }, // 547 |
| 21818 | { PseudoVCLMUL_VX_MF8_MASK, VCLMUL_VX }, // 548 |
| 21819 | { PseudoVCLZ_V_M1, VCLZ_V }, // 549 |
| 21820 | { PseudoVCLZ_V_M1_MASK, VCLZ_V }, // 550 |
| 21821 | { PseudoVCLZ_V_M2, VCLZ_V }, // 551 |
| 21822 | { PseudoVCLZ_V_M2_MASK, VCLZ_V }, // 552 |
| 21823 | { PseudoVCLZ_V_M4, VCLZ_V }, // 553 |
| 21824 | { PseudoVCLZ_V_M4_MASK, VCLZ_V }, // 554 |
| 21825 | { PseudoVCLZ_V_M8, VCLZ_V }, // 555 |
| 21826 | { PseudoVCLZ_V_M8_MASK, VCLZ_V }, // 556 |
| 21827 | { PseudoVCLZ_V_MF2, VCLZ_V }, // 557 |
| 21828 | { PseudoVCLZ_V_MF2_MASK, VCLZ_V }, // 558 |
| 21829 | { PseudoVCLZ_V_MF4, VCLZ_V }, // 559 |
| 21830 | { PseudoVCLZ_V_MF4_MASK, VCLZ_V }, // 560 |
| 21831 | { PseudoVCLZ_V_MF8, VCLZ_V }, // 561 |
| 21832 | { PseudoVCLZ_V_MF8_MASK, VCLZ_V }, // 562 |
| 21833 | { PseudoVCOMPRESS_VM_M1_E16, VCOMPRESS_VM }, // 563 |
| 21834 | { PseudoVCOMPRESS_VM_M1_E32, VCOMPRESS_VM }, // 564 |
| 21835 | { PseudoVCOMPRESS_VM_M1_E64, VCOMPRESS_VM }, // 565 |
| 21836 | { PseudoVCOMPRESS_VM_M1_E8, VCOMPRESS_VM }, // 566 |
| 21837 | { PseudoVCOMPRESS_VM_M2_E16, VCOMPRESS_VM }, // 567 |
| 21838 | { PseudoVCOMPRESS_VM_M2_E32, VCOMPRESS_VM }, // 568 |
| 21839 | { PseudoVCOMPRESS_VM_M2_E64, VCOMPRESS_VM }, // 569 |
| 21840 | { PseudoVCOMPRESS_VM_M2_E8, VCOMPRESS_VM }, // 570 |
| 21841 | { PseudoVCOMPRESS_VM_M4_E16, VCOMPRESS_VM }, // 571 |
| 21842 | { PseudoVCOMPRESS_VM_M4_E32, VCOMPRESS_VM }, // 572 |
| 21843 | { PseudoVCOMPRESS_VM_M4_E64, VCOMPRESS_VM }, // 573 |
| 21844 | { PseudoVCOMPRESS_VM_M4_E8, VCOMPRESS_VM }, // 574 |
| 21845 | { PseudoVCOMPRESS_VM_M8_E16, VCOMPRESS_VM }, // 575 |
| 21846 | { PseudoVCOMPRESS_VM_M8_E32, VCOMPRESS_VM }, // 576 |
| 21847 | { PseudoVCOMPRESS_VM_M8_E64, VCOMPRESS_VM }, // 577 |
| 21848 | { PseudoVCOMPRESS_VM_M8_E8, VCOMPRESS_VM }, // 578 |
| 21849 | { PseudoVCOMPRESS_VM_MF2_E16, VCOMPRESS_VM }, // 579 |
| 21850 | { PseudoVCOMPRESS_VM_MF2_E32, VCOMPRESS_VM }, // 580 |
| 21851 | { PseudoVCOMPRESS_VM_MF2_E8, VCOMPRESS_VM }, // 581 |
| 21852 | { PseudoVCOMPRESS_VM_MF4_E16, VCOMPRESS_VM }, // 582 |
| 21853 | { PseudoVCOMPRESS_VM_MF4_E8, VCOMPRESS_VM }, // 583 |
| 21854 | { PseudoVCOMPRESS_VM_MF8_E8, VCOMPRESS_VM }, // 584 |
| 21855 | { PseudoVCPOP_M_B1, VCPOP_M }, // 585 |
| 21856 | { PseudoVCPOP_M_B16, VCPOP_M }, // 586 |
| 21857 | { PseudoVCPOP_M_B16_MASK, VCPOP_M }, // 587 |
| 21858 | { PseudoVCPOP_M_B1_MASK, VCPOP_M }, // 588 |
| 21859 | { PseudoVCPOP_M_B2, VCPOP_M }, // 589 |
| 21860 | { PseudoVCPOP_M_B2_MASK, VCPOP_M }, // 590 |
| 21861 | { PseudoVCPOP_M_B32, VCPOP_M }, // 591 |
| 21862 | { PseudoVCPOP_M_B32_MASK, VCPOP_M }, // 592 |
| 21863 | { PseudoVCPOP_M_B4, VCPOP_M }, // 593 |
| 21864 | { PseudoVCPOP_M_B4_MASK, VCPOP_M }, // 594 |
| 21865 | { PseudoVCPOP_M_B64, VCPOP_M }, // 595 |
| 21866 | { PseudoVCPOP_M_B64_MASK, VCPOP_M }, // 596 |
| 21867 | { PseudoVCPOP_M_B8, VCPOP_M }, // 597 |
| 21868 | { PseudoVCPOP_M_B8_MASK, VCPOP_M }, // 598 |
| 21869 | { PseudoVCPOP_V_M1, VCPOP_V }, // 599 |
| 21870 | { PseudoVCPOP_V_M1_MASK, VCPOP_V }, // 600 |
| 21871 | { PseudoVCPOP_V_M2, VCPOP_V }, // 601 |
| 21872 | { PseudoVCPOP_V_M2_MASK, VCPOP_V }, // 602 |
| 21873 | { PseudoVCPOP_V_M4, VCPOP_V }, // 603 |
| 21874 | { PseudoVCPOP_V_M4_MASK, VCPOP_V }, // 604 |
| 21875 | { PseudoVCPOP_V_M8, VCPOP_V }, // 605 |
| 21876 | { PseudoVCPOP_V_M8_MASK, VCPOP_V }, // 606 |
| 21877 | { PseudoVCPOP_V_MF2, VCPOP_V }, // 607 |
| 21878 | { PseudoVCPOP_V_MF2_MASK, VCPOP_V }, // 608 |
| 21879 | { PseudoVCPOP_V_MF4, VCPOP_V }, // 609 |
| 21880 | { PseudoVCPOP_V_MF4_MASK, VCPOP_V }, // 610 |
| 21881 | { PseudoVCPOP_V_MF8, VCPOP_V }, // 611 |
| 21882 | { PseudoVCPOP_V_MF8_MASK, VCPOP_V }, // 612 |
| 21883 | { PseudoVCTZ_V_M1, VCTZ_V }, // 613 |
| 21884 | { PseudoVCTZ_V_M1_MASK, VCTZ_V }, // 614 |
| 21885 | { PseudoVCTZ_V_M2, VCTZ_V }, // 615 |
| 21886 | { PseudoVCTZ_V_M2_MASK, VCTZ_V }, // 616 |
| 21887 | { PseudoVCTZ_V_M4, VCTZ_V }, // 617 |
| 21888 | { PseudoVCTZ_V_M4_MASK, VCTZ_V }, // 618 |
| 21889 | { PseudoVCTZ_V_M8, VCTZ_V }, // 619 |
| 21890 | { PseudoVCTZ_V_M8_MASK, VCTZ_V }, // 620 |
| 21891 | { PseudoVCTZ_V_MF2, VCTZ_V }, // 621 |
| 21892 | { PseudoVCTZ_V_MF2_MASK, VCTZ_V }, // 622 |
| 21893 | { PseudoVCTZ_V_MF4, VCTZ_V }, // 623 |
| 21894 | { PseudoVCTZ_V_MF4_MASK, VCTZ_V }, // 624 |
| 21895 | { PseudoVCTZ_V_MF8, VCTZ_V }, // 625 |
| 21896 | { PseudoVCTZ_V_MF8_MASK, VCTZ_V }, // 626 |
| 21897 | { PseudoVC_FPR16VV_SE_M1, VC_FVV }, // 627 |
| 21898 | { PseudoVC_FPR16VV_SE_M2, VC_FVV }, // 628 |
| 21899 | { PseudoVC_FPR16VV_SE_M4, VC_FVV }, // 629 |
| 21900 | { PseudoVC_FPR16VV_SE_M8, VC_FVV }, // 630 |
| 21901 | { PseudoVC_FPR16VV_SE_MF2, VC_FVV }, // 631 |
| 21902 | { PseudoVC_FPR16VV_SE_MF4, VC_FVV }, // 632 |
| 21903 | { PseudoVC_FPR16VW_SE_M1, VC_FVW }, // 633 |
| 21904 | { PseudoVC_FPR16VW_SE_M2, VC_FVW }, // 634 |
| 21905 | { PseudoVC_FPR16VW_SE_M4, VC_FVW }, // 635 |
| 21906 | { PseudoVC_FPR16VW_SE_M8, VC_FVW }, // 636 |
| 21907 | { PseudoVC_FPR16VW_SE_MF2, VC_FVW }, // 637 |
| 21908 | { PseudoVC_FPR16VW_SE_MF4, VC_FVW }, // 638 |
| 21909 | { PseudoVC_FPR16V_SE_M1, VC_FV }, // 639 |
| 21910 | { PseudoVC_FPR16V_SE_M2, VC_FV }, // 640 |
| 21911 | { PseudoVC_FPR16V_SE_M4, VC_FV }, // 641 |
| 21912 | { PseudoVC_FPR16V_SE_M8, VC_FV }, // 642 |
| 21913 | { PseudoVC_FPR16V_SE_MF2, VC_FV }, // 643 |
| 21914 | { PseudoVC_FPR16V_SE_MF4, VC_FV }, // 644 |
| 21915 | { PseudoVC_FPR32VV_SE_M1, VC_FVV }, // 645 |
| 21916 | { PseudoVC_FPR32VV_SE_M2, VC_FVV }, // 646 |
| 21917 | { PseudoVC_FPR32VV_SE_M4, VC_FVV }, // 647 |
| 21918 | { PseudoVC_FPR32VV_SE_M8, VC_FVV }, // 648 |
| 21919 | { PseudoVC_FPR32VV_SE_MF2, VC_FVV }, // 649 |
| 21920 | { PseudoVC_FPR32VW_SE_M1, VC_FVW }, // 650 |
| 21921 | { PseudoVC_FPR32VW_SE_M2, VC_FVW }, // 651 |
| 21922 | { PseudoVC_FPR32VW_SE_M4, VC_FVW }, // 652 |
| 21923 | { PseudoVC_FPR32VW_SE_M8, VC_FVW }, // 653 |
| 21924 | { PseudoVC_FPR32VW_SE_MF2, VC_FVW }, // 654 |
| 21925 | { PseudoVC_FPR32V_SE_M1, VC_FV }, // 655 |
| 21926 | { PseudoVC_FPR32V_SE_M2, VC_FV }, // 656 |
| 21927 | { PseudoVC_FPR32V_SE_M4, VC_FV }, // 657 |
| 21928 | { PseudoVC_FPR32V_SE_M8, VC_FV }, // 658 |
| 21929 | { PseudoVC_FPR32V_SE_MF2, VC_FV }, // 659 |
| 21930 | { PseudoVC_FPR64VV_SE_M1, VC_FVV }, // 660 |
| 21931 | { PseudoVC_FPR64VV_SE_M2, VC_FVV }, // 661 |
| 21932 | { PseudoVC_FPR64VV_SE_M4, VC_FVV }, // 662 |
| 21933 | { PseudoVC_FPR64VV_SE_M8, VC_FVV }, // 663 |
| 21934 | { PseudoVC_FPR64V_SE_M1, VC_FV }, // 664 |
| 21935 | { PseudoVC_FPR64V_SE_M2, VC_FV }, // 665 |
| 21936 | { PseudoVC_FPR64V_SE_M4, VC_FV }, // 666 |
| 21937 | { PseudoVC_FPR64V_SE_M8, VC_FV }, // 667 |
| 21938 | { PseudoVC_IVV_SE_M1, VC_IVV }, // 668 |
| 21939 | { PseudoVC_IVV_SE_M2, VC_IVV }, // 669 |
| 21940 | { PseudoVC_IVV_SE_M4, VC_IVV }, // 670 |
| 21941 | { PseudoVC_IVV_SE_M8, VC_IVV }, // 671 |
| 21942 | { PseudoVC_IVV_SE_MF2, VC_IVV }, // 672 |
| 21943 | { PseudoVC_IVV_SE_MF4, VC_IVV }, // 673 |
| 21944 | { PseudoVC_IVV_SE_MF8, VC_IVV }, // 674 |
| 21945 | { PseudoVC_IVW_SE_M1, VC_IVW }, // 675 |
| 21946 | { PseudoVC_IVW_SE_M2, VC_IVW }, // 676 |
| 21947 | { PseudoVC_IVW_SE_M4, VC_IVW }, // 677 |
| 21948 | { PseudoVC_IVW_SE_MF2, VC_IVW }, // 678 |
| 21949 | { PseudoVC_IVW_SE_MF4, VC_IVW }, // 679 |
| 21950 | { PseudoVC_IVW_SE_MF8, VC_IVW }, // 680 |
| 21951 | { PseudoVC_IV_SE_M1, VC_IV }, // 681 |
| 21952 | { PseudoVC_IV_SE_M2, VC_IV }, // 682 |
| 21953 | { PseudoVC_IV_SE_M4, VC_IV }, // 683 |
| 21954 | { PseudoVC_IV_SE_M8, VC_IV }, // 684 |
| 21955 | { PseudoVC_IV_SE_MF2, VC_IV }, // 685 |
| 21956 | { PseudoVC_IV_SE_MF4, VC_IV }, // 686 |
| 21957 | { PseudoVC_IV_SE_MF8, VC_IV }, // 687 |
| 21958 | { PseudoVC_I_SE_M1, VC_I }, // 688 |
| 21959 | { PseudoVC_I_SE_M2, VC_I }, // 689 |
| 21960 | { PseudoVC_I_SE_M4, VC_I }, // 690 |
| 21961 | { PseudoVC_I_SE_M8, VC_I }, // 691 |
| 21962 | { PseudoVC_I_SE_MF2, VC_I }, // 692 |
| 21963 | { PseudoVC_I_SE_MF4, VC_I }, // 693 |
| 21964 | { PseudoVC_I_SE_MF8, VC_I }, // 694 |
| 21965 | { PseudoVC_VVV_SE_M1, VC_VVV }, // 695 |
| 21966 | { PseudoVC_VVV_SE_M2, VC_VVV }, // 696 |
| 21967 | { PseudoVC_VVV_SE_M4, VC_VVV }, // 697 |
| 21968 | { PseudoVC_VVV_SE_M8, VC_VVV }, // 698 |
| 21969 | { PseudoVC_VVV_SE_MF2, VC_VVV }, // 699 |
| 21970 | { PseudoVC_VVV_SE_MF4, VC_VVV }, // 700 |
| 21971 | { PseudoVC_VVV_SE_MF8, VC_VVV }, // 701 |
| 21972 | { PseudoVC_VVW_SE_M1, VC_VVW }, // 702 |
| 21973 | { PseudoVC_VVW_SE_M2, VC_VVW }, // 703 |
| 21974 | { PseudoVC_VVW_SE_M4, VC_VVW }, // 704 |
| 21975 | { PseudoVC_VVW_SE_MF2, VC_VVW }, // 705 |
| 21976 | { PseudoVC_VVW_SE_MF4, VC_VVW }, // 706 |
| 21977 | { PseudoVC_VVW_SE_MF8, VC_VVW }, // 707 |
| 21978 | { PseudoVC_VV_SE_M1, VC_VV }, // 708 |
| 21979 | { PseudoVC_VV_SE_M2, VC_VV }, // 709 |
| 21980 | { PseudoVC_VV_SE_M4, VC_VV }, // 710 |
| 21981 | { PseudoVC_VV_SE_M8, VC_VV }, // 711 |
| 21982 | { PseudoVC_VV_SE_MF2, VC_VV }, // 712 |
| 21983 | { PseudoVC_VV_SE_MF4, VC_VV }, // 713 |
| 21984 | { PseudoVC_VV_SE_MF8, VC_VV }, // 714 |
| 21985 | { PseudoVC_V_FPR16VV_M1, VC_V_FVV }, // 715 |
| 21986 | { PseudoVC_V_FPR16VV_M2, VC_V_FVV }, // 716 |
| 21987 | { PseudoVC_V_FPR16VV_M4, VC_V_FVV }, // 717 |
| 21988 | { PseudoVC_V_FPR16VV_M8, VC_V_FVV }, // 718 |
| 21989 | { PseudoVC_V_FPR16VV_MF2, VC_V_FVV }, // 719 |
| 21990 | { PseudoVC_V_FPR16VV_MF4, VC_V_FVV }, // 720 |
| 21991 | { PseudoVC_V_FPR16VV_SE_M1, VC_V_FVV }, // 721 |
| 21992 | { PseudoVC_V_FPR16VV_SE_M2, VC_V_FVV }, // 722 |
| 21993 | { PseudoVC_V_FPR16VV_SE_M4, VC_V_FVV }, // 723 |
| 21994 | { PseudoVC_V_FPR16VV_SE_M8, VC_V_FVV }, // 724 |
| 21995 | { PseudoVC_V_FPR16VV_SE_MF2, VC_V_FVV }, // 725 |
| 21996 | { PseudoVC_V_FPR16VV_SE_MF4, VC_V_FVV }, // 726 |
| 21997 | { PseudoVC_V_FPR16VW_M1, VC_V_FVW }, // 727 |
| 21998 | { PseudoVC_V_FPR16VW_M2, VC_V_FVW }, // 728 |
| 21999 | { PseudoVC_V_FPR16VW_M4, VC_V_FVW }, // 729 |
| 22000 | { PseudoVC_V_FPR16VW_M8, VC_V_FVW }, // 730 |
| 22001 | { PseudoVC_V_FPR16VW_MF2, VC_V_FVW }, // 731 |
| 22002 | { PseudoVC_V_FPR16VW_MF4, VC_V_FVW }, // 732 |
| 22003 | { PseudoVC_V_FPR16VW_SE_M1, VC_V_FVW }, // 733 |
| 22004 | { PseudoVC_V_FPR16VW_SE_M2, VC_V_FVW }, // 734 |
| 22005 | { PseudoVC_V_FPR16VW_SE_M4, VC_V_FVW }, // 735 |
| 22006 | { PseudoVC_V_FPR16VW_SE_M8, VC_V_FVW }, // 736 |
| 22007 | { PseudoVC_V_FPR16VW_SE_MF2, VC_V_FVW }, // 737 |
| 22008 | { PseudoVC_V_FPR16VW_SE_MF4, VC_V_FVW }, // 738 |
| 22009 | { PseudoVC_V_FPR16V_M1, VC_V_FV }, // 739 |
| 22010 | { PseudoVC_V_FPR16V_M2, VC_V_FV }, // 740 |
| 22011 | { PseudoVC_V_FPR16V_M4, VC_V_FV }, // 741 |
| 22012 | { PseudoVC_V_FPR16V_M8, VC_V_FV }, // 742 |
| 22013 | { PseudoVC_V_FPR16V_MF2, VC_V_FV }, // 743 |
| 22014 | { PseudoVC_V_FPR16V_MF4, VC_V_FV }, // 744 |
| 22015 | { PseudoVC_V_FPR16V_SE_M1, VC_V_FV }, // 745 |
| 22016 | { PseudoVC_V_FPR16V_SE_M2, VC_V_FV }, // 746 |
| 22017 | { PseudoVC_V_FPR16V_SE_M4, VC_V_FV }, // 747 |
| 22018 | { PseudoVC_V_FPR16V_SE_M8, VC_V_FV }, // 748 |
| 22019 | { PseudoVC_V_FPR16V_SE_MF2, VC_V_FV }, // 749 |
| 22020 | { PseudoVC_V_FPR16V_SE_MF4, VC_V_FV }, // 750 |
| 22021 | { PseudoVC_V_FPR32VV_M1, VC_V_FVV }, // 751 |
| 22022 | { PseudoVC_V_FPR32VV_M2, VC_V_FVV }, // 752 |
| 22023 | { PseudoVC_V_FPR32VV_M4, VC_V_FVV }, // 753 |
| 22024 | { PseudoVC_V_FPR32VV_M8, VC_V_FVV }, // 754 |
| 22025 | { PseudoVC_V_FPR32VV_MF2, VC_V_FVV }, // 755 |
| 22026 | { PseudoVC_V_FPR32VV_SE_M1, VC_V_FVV }, // 756 |
| 22027 | { PseudoVC_V_FPR32VV_SE_M2, VC_V_FVV }, // 757 |
| 22028 | { PseudoVC_V_FPR32VV_SE_M4, VC_V_FVV }, // 758 |
| 22029 | { PseudoVC_V_FPR32VV_SE_M8, VC_V_FVV }, // 759 |
| 22030 | { PseudoVC_V_FPR32VV_SE_MF2, VC_V_FVV }, // 760 |
| 22031 | { PseudoVC_V_FPR32VW_M1, VC_V_FVW }, // 761 |
| 22032 | { PseudoVC_V_FPR32VW_M2, VC_V_FVW }, // 762 |
| 22033 | { PseudoVC_V_FPR32VW_M4, VC_V_FVW }, // 763 |
| 22034 | { PseudoVC_V_FPR32VW_M8, VC_V_FVW }, // 764 |
| 22035 | { PseudoVC_V_FPR32VW_MF2, VC_V_FVW }, // 765 |
| 22036 | { PseudoVC_V_FPR32VW_SE_M1, VC_V_FVW }, // 766 |
| 22037 | { PseudoVC_V_FPR32VW_SE_M2, VC_V_FVW }, // 767 |
| 22038 | { PseudoVC_V_FPR32VW_SE_M4, VC_V_FVW }, // 768 |
| 22039 | { PseudoVC_V_FPR32VW_SE_M8, VC_V_FVW }, // 769 |
| 22040 | { PseudoVC_V_FPR32VW_SE_MF2, VC_V_FVW }, // 770 |
| 22041 | { PseudoVC_V_FPR32V_M1, VC_V_FV }, // 771 |
| 22042 | { PseudoVC_V_FPR32V_M2, VC_V_FV }, // 772 |
| 22043 | { PseudoVC_V_FPR32V_M4, VC_V_FV }, // 773 |
| 22044 | { PseudoVC_V_FPR32V_M8, VC_V_FV }, // 774 |
| 22045 | { PseudoVC_V_FPR32V_MF2, VC_V_FV }, // 775 |
| 22046 | { PseudoVC_V_FPR32V_SE_M1, VC_V_FV }, // 776 |
| 22047 | { PseudoVC_V_FPR32V_SE_M2, VC_V_FV }, // 777 |
| 22048 | { PseudoVC_V_FPR32V_SE_M4, VC_V_FV }, // 778 |
| 22049 | { PseudoVC_V_FPR32V_SE_M8, VC_V_FV }, // 779 |
| 22050 | { PseudoVC_V_FPR32V_SE_MF2, VC_V_FV }, // 780 |
| 22051 | { PseudoVC_V_FPR64VV_M1, VC_V_FVV }, // 781 |
| 22052 | { PseudoVC_V_FPR64VV_M2, VC_V_FVV }, // 782 |
| 22053 | { PseudoVC_V_FPR64VV_M4, VC_V_FVV }, // 783 |
| 22054 | { PseudoVC_V_FPR64VV_M8, VC_V_FVV }, // 784 |
| 22055 | { PseudoVC_V_FPR64VV_SE_M1, VC_V_FVV }, // 785 |
| 22056 | { PseudoVC_V_FPR64VV_SE_M2, VC_V_FVV }, // 786 |
| 22057 | { PseudoVC_V_FPR64VV_SE_M4, VC_V_FVV }, // 787 |
| 22058 | { PseudoVC_V_FPR64VV_SE_M8, VC_V_FVV }, // 788 |
| 22059 | { PseudoVC_V_FPR64V_M1, VC_V_FV }, // 789 |
| 22060 | { PseudoVC_V_FPR64V_M2, VC_V_FV }, // 790 |
| 22061 | { PseudoVC_V_FPR64V_M4, VC_V_FV }, // 791 |
| 22062 | { PseudoVC_V_FPR64V_M8, VC_V_FV }, // 792 |
| 22063 | { PseudoVC_V_FPR64V_SE_M1, VC_V_FV }, // 793 |
| 22064 | { PseudoVC_V_FPR64V_SE_M2, VC_V_FV }, // 794 |
| 22065 | { PseudoVC_V_FPR64V_SE_M4, VC_V_FV }, // 795 |
| 22066 | { PseudoVC_V_FPR64V_SE_M8, VC_V_FV }, // 796 |
| 22067 | { PseudoVC_V_IVV_M1, VC_V_IVV }, // 797 |
| 22068 | { PseudoVC_V_IVV_M2, VC_V_IVV }, // 798 |
| 22069 | { PseudoVC_V_IVV_M4, VC_V_IVV }, // 799 |
| 22070 | { PseudoVC_V_IVV_M8, VC_V_IVV }, // 800 |
| 22071 | { PseudoVC_V_IVV_MF2, VC_V_IVV }, // 801 |
| 22072 | { PseudoVC_V_IVV_MF4, VC_V_IVV }, // 802 |
| 22073 | { PseudoVC_V_IVV_MF8, VC_V_IVV }, // 803 |
| 22074 | { PseudoVC_V_IVV_SE_M1, VC_V_IVV }, // 804 |
| 22075 | { PseudoVC_V_IVV_SE_M2, VC_V_IVV }, // 805 |
| 22076 | { PseudoVC_V_IVV_SE_M4, VC_V_IVV }, // 806 |
| 22077 | { PseudoVC_V_IVV_SE_M8, VC_V_IVV }, // 807 |
| 22078 | { PseudoVC_V_IVV_SE_MF2, VC_V_IVV }, // 808 |
| 22079 | { PseudoVC_V_IVV_SE_MF4, VC_V_IVV }, // 809 |
| 22080 | { PseudoVC_V_IVV_SE_MF8, VC_V_IVV }, // 810 |
| 22081 | { PseudoVC_V_IVW_M1, VC_V_IVW }, // 811 |
| 22082 | { PseudoVC_V_IVW_M2, VC_V_IVW }, // 812 |
| 22083 | { PseudoVC_V_IVW_M4, VC_V_IVW }, // 813 |
| 22084 | { PseudoVC_V_IVW_MF2, VC_V_IVW }, // 814 |
| 22085 | { PseudoVC_V_IVW_MF4, VC_V_IVW }, // 815 |
| 22086 | { PseudoVC_V_IVW_MF8, VC_V_IVW }, // 816 |
| 22087 | { PseudoVC_V_IVW_SE_M1, VC_V_IVW }, // 817 |
| 22088 | { PseudoVC_V_IVW_SE_M2, VC_V_IVW }, // 818 |
| 22089 | { PseudoVC_V_IVW_SE_M4, VC_V_IVW }, // 819 |
| 22090 | { PseudoVC_V_IVW_SE_MF2, VC_V_IVW }, // 820 |
| 22091 | { PseudoVC_V_IVW_SE_MF4, VC_V_IVW }, // 821 |
| 22092 | { PseudoVC_V_IVW_SE_MF8, VC_V_IVW }, // 822 |
| 22093 | { PseudoVC_V_IV_M1, VC_V_IV }, // 823 |
| 22094 | { PseudoVC_V_IV_M2, VC_V_IV }, // 824 |
| 22095 | { PseudoVC_V_IV_M4, VC_V_IV }, // 825 |
| 22096 | { PseudoVC_V_IV_M8, VC_V_IV }, // 826 |
| 22097 | { PseudoVC_V_IV_MF2, VC_V_IV }, // 827 |
| 22098 | { PseudoVC_V_IV_MF4, VC_V_IV }, // 828 |
| 22099 | { PseudoVC_V_IV_MF8, VC_V_IV }, // 829 |
| 22100 | { PseudoVC_V_IV_SE_M1, VC_V_IV }, // 830 |
| 22101 | { PseudoVC_V_IV_SE_M2, VC_V_IV }, // 831 |
| 22102 | { PseudoVC_V_IV_SE_M4, VC_V_IV }, // 832 |
| 22103 | { PseudoVC_V_IV_SE_M8, VC_V_IV }, // 833 |
| 22104 | { PseudoVC_V_IV_SE_MF2, VC_V_IV }, // 834 |
| 22105 | { PseudoVC_V_IV_SE_MF4, VC_V_IV }, // 835 |
| 22106 | { PseudoVC_V_IV_SE_MF8, VC_V_IV }, // 836 |
| 22107 | { PseudoVC_V_I_M1, VC_V_I }, // 837 |
| 22108 | { PseudoVC_V_I_M2, VC_V_I }, // 838 |
| 22109 | { PseudoVC_V_I_M4, VC_V_I }, // 839 |
| 22110 | { PseudoVC_V_I_M8, VC_V_I }, // 840 |
| 22111 | { PseudoVC_V_I_MF2, VC_V_I }, // 841 |
| 22112 | { PseudoVC_V_I_MF4, VC_V_I }, // 842 |
| 22113 | { PseudoVC_V_I_MF8, VC_V_I }, // 843 |
| 22114 | { PseudoVC_V_I_SE_M1, VC_V_I }, // 844 |
| 22115 | { PseudoVC_V_I_SE_M2, VC_V_I }, // 845 |
| 22116 | { PseudoVC_V_I_SE_M4, VC_V_I }, // 846 |
| 22117 | { PseudoVC_V_I_SE_M8, VC_V_I }, // 847 |
| 22118 | { PseudoVC_V_I_SE_MF2, VC_V_I }, // 848 |
| 22119 | { PseudoVC_V_I_SE_MF4, VC_V_I }, // 849 |
| 22120 | { PseudoVC_V_I_SE_MF8, VC_V_I }, // 850 |
| 22121 | { PseudoVC_V_VVV_M1, VC_V_VVV }, // 851 |
| 22122 | { PseudoVC_V_VVV_M2, VC_V_VVV }, // 852 |
| 22123 | { PseudoVC_V_VVV_M4, VC_V_VVV }, // 853 |
| 22124 | { PseudoVC_V_VVV_M8, VC_V_VVV }, // 854 |
| 22125 | { PseudoVC_V_VVV_MF2, VC_V_VVV }, // 855 |
| 22126 | { PseudoVC_V_VVV_MF4, VC_V_VVV }, // 856 |
| 22127 | { PseudoVC_V_VVV_MF8, VC_V_VVV }, // 857 |
| 22128 | { PseudoVC_V_VVV_SE_M1, VC_V_VVV }, // 858 |
| 22129 | { PseudoVC_V_VVV_SE_M2, VC_V_VVV }, // 859 |
| 22130 | { PseudoVC_V_VVV_SE_M4, VC_V_VVV }, // 860 |
| 22131 | { PseudoVC_V_VVV_SE_M8, VC_V_VVV }, // 861 |
| 22132 | { PseudoVC_V_VVV_SE_MF2, VC_V_VVV }, // 862 |
| 22133 | { PseudoVC_V_VVV_SE_MF4, VC_V_VVV }, // 863 |
| 22134 | { PseudoVC_V_VVV_SE_MF8, VC_V_VVV }, // 864 |
| 22135 | { PseudoVC_V_VVW_M1, VC_V_VVW }, // 865 |
| 22136 | { PseudoVC_V_VVW_M2, VC_V_VVW }, // 866 |
| 22137 | { PseudoVC_V_VVW_M4, VC_V_VVW }, // 867 |
| 22138 | { PseudoVC_V_VVW_MF2, VC_V_VVW }, // 868 |
| 22139 | { PseudoVC_V_VVW_MF4, VC_V_VVW }, // 869 |
| 22140 | { PseudoVC_V_VVW_MF8, VC_V_VVW }, // 870 |
| 22141 | { PseudoVC_V_VVW_SE_M1, VC_V_VVW }, // 871 |
| 22142 | { PseudoVC_V_VVW_SE_M2, VC_V_VVW }, // 872 |
| 22143 | { PseudoVC_V_VVW_SE_M4, VC_V_VVW }, // 873 |
| 22144 | { PseudoVC_V_VVW_SE_MF2, VC_V_VVW }, // 874 |
| 22145 | { PseudoVC_V_VVW_SE_MF4, VC_V_VVW }, // 875 |
| 22146 | { PseudoVC_V_VVW_SE_MF8, VC_V_VVW }, // 876 |
| 22147 | { PseudoVC_V_VV_M1, VC_V_VV }, // 877 |
| 22148 | { PseudoVC_V_VV_M2, VC_V_VV }, // 878 |
| 22149 | { PseudoVC_V_VV_M4, VC_V_VV }, // 879 |
| 22150 | { PseudoVC_V_VV_M8, VC_V_VV }, // 880 |
| 22151 | { PseudoVC_V_VV_MF2, VC_V_VV }, // 881 |
| 22152 | { PseudoVC_V_VV_MF4, VC_V_VV }, // 882 |
| 22153 | { PseudoVC_V_VV_MF8, VC_V_VV }, // 883 |
| 22154 | { PseudoVC_V_VV_SE_M1, VC_V_VV }, // 884 |
| 22155 | { PseudoVC_V_VV_SE_M2, VC_V_VV }, // 885 |
| 22156 | { PseudoVC_V_VV_SE_M4, VC_V_VV }, // 886 |
| 22157 | { PseudoVC_V_VV_SE_M8, VC_V_VV }, // 887 |
| 22158 | { PseudoVC_V_VV_SE_MF2, VC_V_VV }, // 888 |
| 22159 | { PseudoVC_V_VV_SE_MF4, VC_V_VV }, // 889 |
| 22160 | { PseudoVC_V_VV_SE_MF8, VC_V_VV }, // 890 |
| 22161 | { PseudoVC_V_XVV_M1, VC_V_XVV }, // 891 |
| 22162 | { PseudoVC_V_XVV_M2, VC_V_XVV }, // 892 |
| 22163 | { PseudoVC_V_XVV_M4, VC_V_XVV }, // 893 |
| 22164 | { PseudoVC_V_XVV_M8, VC_V_XVV }, // 894 |
| 22165 | { PseudoVC_V_XVV_MF2, VC_V_XVV }, // 895 |
| 22166 | { PseudoVC_V_XVV_MF4, VC_V_XVV }, // 896 |
| 22167 | { PseudoVC_V_XVV_MF8, VC_V_XVV }, // 897 |
| 22168 | { PseudoVC_V_XVV_SE_M1, VC_V_XVV }, // 898 |
| 22169 | { PseudoVC_V_XVV_SE_M2, VC_V_XVV }, // 899 |
| 22170 | { PseudoVC_V_XVV_SE_M4, VC_V_XVV }, // 900 |
| 22171 | { PseudoVC_V_XVV_SE_M8, VC_V_XVV }, // 901 |
| 22172 | { PseudoVC_V_XVV_SE_MF2, VC_V_XVV }, // 902 |
| 22173 | { PseudoVC_V_XVV_SE_MF4, VC_V_XVV }, // 903 |
| 22174 | { PseudoVC_V_XVV_SE_MF8, VC_V_XVV }, // 904 |
| 22175 | { PseudoVC_V_XVW_M1, VC_V_XVW }, // 905 |
| 22176 | { PseudoVC_V_XVW_M2, VC_V_XVW }, // 906 |
| 22177 | { PseudoVC_V_XVW_M4, VC_V_XVW }, // 907 |
| 22178 | { PseudoVC_V_XVW_MF2, VC_V_XVW }, // 908 |
| 22179 | { PseudoVC_V_XVW_MF4, VC_V_XVW }, // 909 |
| 22180 | { PseudoVC_V_XVW_MF8, VC_V_XVW }, // 910 |
| 22181 | { PseudoVC_V_XVW_SE_M1, VC_V_XVW }, // 911 |
| 22182 | { PseudoVC_V_XVW_SE_M2, VC_V_XVW }, // 912 |
| 22183 | { PseudoVC_V_XVW_SE_M4, VC_V_XVW }, // 913 |
| 22184 | { PseudoVC_V_XVW_SE_MF2, VC_V_XVW }, // 914 |
| 22185 | { PseudoVC_V_XVW_SE_MF4, VC_V_XVW }, // 915 |
| 22186 | { PseudoVC_V_XVW_SE_MF8, VC_V_XVW }, // 916 |
| 22187 | { PseudoVC_V_XV_M1, VC_V_XV }, // 917 |
| 22188 | { PseudoVC_V_XV_M2, VC_V_XV }, // 918 |
| 22189 | { PseudoVC_V_XV_M4, VC_V_XV }, // 919 |
| 22190 | { PseudoVC_V_XV_M8, VC_V_XV }, // 920 |
| 22191 | { PseudoVC_V_XV_MF2, VC_V_XV }, // 921 |
| 22192 | { PseudoVC_V_XV_MF4, VC_V_XV }, // 922 |
| 22193 | { PseudoVC_V_XV_MF8, VC_V_XV }, // 923 |
| 22194 | { PseudoVC_V_XV_SE_M1, VC_V_XV }, // 924 |
| 22195 | { PseudoVC_V_XV_SE_M2, VC_V_XV }, // 925 |
| 22196 | { PseudoVC_V_XV_SE_M4, VC_V_XV }, // 926 |
| 22197 | { PseudoVC_V_XV_SE_M8, VC_V_XV }, // 927 |
| 22198 | { PseudoVC_V_XV_SE_MF2, VC_V_XV }, // 928 |
| 22199 | { PseudoVC_V_XV_SE_MF4, VC_V_XV }, // 929 |
| 22200 | { PseudoVC_V_XV_SE_MF8, VC_V_XV }, // 930 |
| 22201 | { PseudoVC_V_X_M1, VC_V_X }, // 931 |
| 22202 | { PseudoVC_V_X_M2, VC_V_X }, // 932 |
| 22203 | { PseudoVC_V_X_M4, VC_V_X }, // 933 |
| 22204 | { PseudoVC_V_X_M8, VC_V_X }, // 934 |
| 22205 | { PseudoVC_V_X_MF2, VC_V_X }, // 935 |
| 22206 | { PseudoVC_V_X_MF4, VC_V_X }, // 936 |
| 22207 | { PseudoVC_V_X_MF8, VC_V_X }, // 937 |
| 22208 | { PseudoVC_V_X_SE_M1, VC_V_X }, // 938 |
| 22209 | { PseudoVC_V_X_SE_M2, VC_V_X }, // 939 |
| 22210 | { PseudoVC_V_X_SE_M4, VC_V_X }, // 940 |
| 22211 | { PseudoVC_V_X_SE_M8, VC_V_X }, // 941 |
| 22212 | { PseudoVC_V_X_SE_MF2, VC_V_X }, // 942 |
| 22213 | { PseudoVC_V_X_SE_MF4, VC_V_X }, // 943 |
| 22214 | { PseudoVC_V_X_SE_MF8, VC_V_X }, // 944 |
| 22215 | { PseudoVC_XVV_SE_M1, VC_XVV }, // 945 |
| 22216 | { PseudoVC_XVV_SE_M2, VC_XVV }, // 946 |
| 22217 | { PseudoVC_XVV_SE_M4, VC_XVV }, // 947 |
| 22218 | { PseudoVC_XVV_SE_M8, VC_XVV }, // 948 |
| 22219 | { PseudoVC_XVV_SE_MF2, VC_XVV }, // 949 |
| 22220 | { PseudoVC_XVV_SE_MF4, VC_XVV }, // 950 |
| 22221 | { PseudoVC_XVV_SE_MF8, VC_XVV }, // 951 |
| 22222 | { PseudoVC_XVW_SE_M1, VC_XVW }, // 952 |
| 22223 | { PseudoVC_XVW_SE_M2, VC_XVW }, // 953 |
| 22224 | { PseudoVC_XVW_SE_M4, VC_XVW }, // 954 |
| 22225 | { PseudoVC_XVW_SE_MF2, VC_XVW }, // 955 |
| 22226 | { PseudoVC_XVW_SE_MF4, VC_XVW }, // 956 |
| 22227 | { PseudoVC_XVW_SE_MF8, VC_XVW }, // 957 |
| 22228 | { PseudoVC_XV_SE_M1, VC_XV }, // 958 |
| 22229 | { PseudoVC_XV_SE_M2, VC_XV }, // 959 |
| 22230 | { PseudoVC_XV_SE_M4, VC_XV }, // 960 |
| 22231 | { PseudoVC_XV_SE_M8, VC_XV }, // 961 |
| 22232 | { PseudoVC_XV_SE_MF2, VC_XV }, // 962 |
| 22233 | { PseudoVC_XV_SE_MF4, VC_XV }, // 963 |
| 22234 | { PseudoVC_XV_SE_MF8, VC_XV }, // 964 |
| 22235 | { PseudoVC_X_SE_M1, VC_X }, // 965 |
| 22236 | { PseudoVC_X_SE_M2, VC_X }, // 966 |
| 22237 | { PseudoVC_X_SE_M4, VC_X }, // 967 |
| 22238 | { PseudoVC_X_SE_M8, VC_X }, // 968 |
| 22239 | { PseudoVC_X_SE_MF2, VC_X }, // 969 |
| 22240 | { PseudoVC_X_SE_MF4, VC_X }, // 970 |
| 22241 | { PseudoVC_X_SE_MF8, VC_X }, // 971 |
| 22242 | { PseudoVDIVU_VV_M1_E16, VDIVU_VV }, // 972 |
| 22243 | { PseudoVDIVU_VV_M1_E16_MASK, VDIVU_VV }, // 973 |
| 22244 | { PseudoVDIVU_VV_M1_E32, VDIVU_VV }, // 974 |
| 22245 | { PseudoVDIVU_VV_M1_E32_MASK, VDIVU_VV }, // 975 |
| 22246 | { PseudoVDIVU_VV_M1_E64, VDIVU_VV }, // 976 |
| 22247 | { PseudoVDIVU_VV_M1_E64_MASK, VDIVU_VV }, // 977 |
| 22248 | { PseudoVDIVU_VV_M1_E8, VDIVU_VV }, // 978 |
| 22249 | { PseudoVDIVU_VV_M1_E8_MASK, VDIVU_VV }, // 979 |
| 22250 | { PseudoVDIVU_VV_M2_E16, VDIVU_VV }, // 980 |
| 22251 | { PseudoVDIVU_VV_M2_E16_MASK, VDIVU_VV }, // 981 |
| 22252 | { PseudoVDIVU_VV_M2_E32, VDIVU_VV }, // 982 |
| 22253 | { PseudoVDIVU_VV_M2_E32_MASK, VDIVU_VV }, // 983 |
| 22254 | { PseudoVDIVU_VV_M2_E64, VDIVU_VV }, // 984 |
| 22255 | { PseudoVDIVU_VV_M2_E64_MASK, VDIVU_VV }, // 985 |
| 22256 | { PseudoVDIVU_VV_M2_E8, VDIVU_VV }, // 986 |
| 22257 | { PseudoVDIVU_VV_M2_E8_MASK, VDIVU_VV }, // 987 |
| 22258 | { PseudoVDIVU_VV_M4_E16, VDIVU_VV }, // 988 |
| 22259 | { PseudoVDIVU_VV_M4_E16_MASK, VDIVU_VV }, // 989 |
| 22260 | { PseudoVDIVU_VV_M4_E32, VDIVU_VV }, // 990 |
| 22261 | { PseudoVDIVU_VV_M4_E32_MASK, VDIVU_VV }, // 991 |
| 22262 | { PseudoVDIVU_VV_M4_E64, VDIVU_VV }, // 992 |
| 22263 | { PseudoVDIVU_VV_M4_E64_MASK, VDIVU_VV }, // 993 |
| 22264 | { PseudoVDIVU_VV_M4_E8, VDIVU_VV }, // 994 |
| 22265 | { PseudoVDIVU_VV_M4_E8_MASK, VDIVU_VV }, // 995 |
| 22266 | { PseudoVDIVU_VV_M8_E16, VDIVU_VV }, // 996 |
| 22267 | { PseudoVDIVU_VV_M8_E16_MASK, VDIVU_VV }, // 997 |
| 22268 | { PseudoVDIVU_VV_M8_E32, VDIVU_VV }, // 998 |
| 22269 | { PseudoVDIVU_VV_M8_E32_MASK, VDIVU_VV }, // 999 |
| 22270 | { PseudoVDIVU_VV_M8_E64, VDIVU_VV }, // 1000 |
| 22271 | { PseudoVDIVU_VV_M8_E64_MASK, VDIVU_VV }, // 1001 |
| 22272 | { PseudoVDIVU_VV_M8_E8, VDIVU_VV }, // 1002 |
| 22273 | { PseudoVDIVU_VV_M8_E8_MASK, VDIVU_VV }, // 1003 |
| 22274 | { PseudoVDIVU_VV_MF2_E16, VDIVU_VV }, // 1004 |
| 22275 | { PseudoVDIVU_VV_MF2_E16_MASK, VDIVU_VV }, // 1005 |
| 22276 | { PseudoVDIVU_VV_MF2_E32, VDIVU_VV }, // 1006 |
| 22277 | { PseudoVDIVU_VV_MF2_E32_MASK, VDIVU_VV }, // 1007 |
| 22278 | { PseudoVDIVU_VV_MF2_E8, VDIVU_VV }, // 1008 |
| 22279 | { PseudoVDIVU_VV_MF2_E8_MASK, VDIVU_VV }, // 1009 |
| 22280 | { PseudoVDIVU_VV_MF4_E16, VDIVU_VV }, // 1010 |
| 22281 | { PseudoVDIVU_VV_MF4_E16_MASK, VDIVU_VV }, // 1011 |
| 22282 | { PseudoVDIVU_VV_MF4_E8, VDIVU_VV }, // 1012 |
| 22283 | { PseudoVDIVU_VV_MF4_E8_MASK, VDIVU_VV }, // 1013 |
| 22284 | { PseudoVDIVU_VV_MF8_E8, VDIVU_VV }, // 1014 |
| 22285 | { PseudoVDIVU_VV_MF8_E8_MASK, VDIVU_VV }, // 1015 |
| 22286 | { PseudoVDIVU_VX_M1_E16, VDIVU_VX }, // 1016 |
| 22287 | { PseudoVDIVU_VX_M1_E16_MASK, VDIVU_VX }, // 1017 |
| 22288 | { PseudoVDIVU_VX_M1_E32, VDIVU_VX }, // 1018 |
| 22289 | { PseudoVDIVU_VX_M1_E32_MASK, VDIVU_VX }, // 1019 |
| 22290 | { PseudoVDIVU_VX_M1_E64, VDIVU_VX }, // 1020 |
| 22291 | { PseudoVDIVU_VX_M1_E64_MASK, VDIVU_VX }, // 1021 |
| 22292 | { PseudoVDIVU_VX_M1_E8, VDIVU_VX }, // 1022 |
| 22293 | { PseudoVDIVU_VX_M1_E8_MASK, VDIVU_VX }, // 1023 |
| 22294 | { PseudoVDIVU_VX_M2_E16, VDIVU_VX }, // 1024 |
| 22295 | { PseudoVDIVU_VX_M2_E16_MASK, VDIVU_VX }, // 1025 |
| 22296 | { PseudoVDIVU_VX_M2_E32, VDIVU_VX }, // 1026 |
| 22297 | { PseudoVDIVU_VX_M2_E32_MASK, VDIVU_VX }, // 1027 |
| 22298 | { PseudoVDIVU_VX_M2_E64, VDIVU_VX }, // 1028 |
| 22299 | { PseudoVDIVU_VX_M2_E64_MASK, VDIVU_VX }, // 1029 |
| 22300 | { PseudoVDIVU_VX_M2_E8, VDIVU_VX }, // 1030 |
| 22301 | { PseudoVDIVU_VX_M2_E8_MASK, VDIVU_VX }, // 1031 |
| 22302 | { PseudoVDIVU_VX_M4_E16, VDIVU_VX }, // 1032 |
| 22303 | { PseudoVDIVU_VX_M4_E16_MASK, VDIVU_VX }, // 1033 |
| 22304 | { PseudoVDIVU_VX_M4_E32, VDIVU_VX }, // 1034 |
| 22305 | { PseudoVDIVU_VX_M4_E32_MASK, VDIVU_VX }, // 1035 |
| 22306 | { PseudoVDIVU_VX_M4_E64, VDIVU_VX }, // 1036 |
| 22307 | { PseudoVDIVU_VX_M4_E64_MASK, VDIVU_VX }, // 1037 |
| 22308 | { PseudoVDIVU_VX_M4_E8, VDIVU_VX }, // 1038 |
| 22309 | { PseudoVDIVU_VX_M4_E8_MASK, VDIVU_VX }, // 1039 |
| 22310 | { PseudoVDIVU_VX_M8_E16, VDIVU_VX }, // 1040 |
| 22311 | { PseudoVDIVU_VX_M8_E16_MASK, VDIVU_VX }, // 1041 |
| 22312 | { PseudoVDIVU_VX_M8_E32, VDIVU_VX }, // 1042 |
| 22313 | { PseudoVDIVU_VX_M8_E32_MASK, VDIVU_VX }, // 1043 |
| 22314 | { PseudoVDIVU_VX_M8_E64, VDIVU_VX }, // 1044 |
| 22315 | { PseudoVDIVU_VX_M8_E64_MASK, VDIVU_VX }, // 1045 |
| 22316 | { PseudoVDIVU_VX_M8_E8, VDIVU_VX }, // 1046 |
| 22317 | { PseudoVDIVU_VX_M8_E8_MASK, VDIVU_VX }, // 1047 |
| 22318 | { PseudoVDIVU_VX_MF2_E16, VDIVU_VX }, // 1048 |
| 22319 | { PseudoVDIVU_VX_MF2_E16_MASK, VDIVU_VX }, // 1049 |
| 22320 | { PseudoVDIVU_VX_MF2_E32, VDIVU_VX }, // 1050 |
| 22321 | { PseudoVDIVU_VX_MF2_E32_MASK, VDIVU_VX }, // 1051 |
| 22322 | { PseudoVDIVU_VX_MF2_E8, VDIVU_VX }, // 1052 |
| 22323 | { PseudoVDIVU_VX_MF2_E8_MASK, VDIVU_VX }, // 1053 |
| 22324 | { PseudoVDIVU_VX_MF4_E16, VDIVU_VX }, // 1054 |
| 22325 | { PseudoVDIVU_VX_MF4_E16_MASK, VDIVU_VX }, // 1055 |
| 22326 | { PseudoVDIVU_VX_MF4_E8, VDIVU_VX }, // 1056 |
| 22327 | { PseudoVDIVU_VX_MF4_E8_MASK, VDIVU_VX }, // 1057 |
| 22328 | { PseudoVDIVU_VX_MF8_E8, VDIVU_VX }, // 1058 |
| 22329 | { PseudoVDIVU_VX_MF8_E8_MASK, VDIVU_VX }, // 1059 |
| 22330 | { PseudoVDIV_VV_M1_E16, VDIV_VV }, // 1060 |
| 22331 | { PseudoVDIV_VV_M1_E16_MASK, VDIV_VV }, // 1061 |
| 22332 | { PseudoVDIV_VV_M1_E32, VDIV_VV }, // 1062 |
| 22333 | { PseudoVDIV_VV_M1_E32_MASK, VDIV_VV }, // 1063 |
| 22334 | { PseudoVDIV_VV_M1_E64, VDIV_VV }, // 1064 |
| 22335 | { PseudoVDIV_VV_M1_E64_MASK, VDIV_VV }, // 1065 |
| 22336 | { PseudoVDIV_VV_M1_E8, VDIV_VV }, // 1066 |
| 22337 | { PseudoVDIV_VV_M1_E8_MASK, VDIV_VV }, // 1067 |
| 22338 | { PseudoVDIV_VV_M2_E16, VDIV_VV }, // 1068 |
| 22339 | { PseudoVDIV_VV_M2_E16_MASK, VDIV_VV }, // 1069 |
| 22340 | { PseudoVDIV_VV_M2_E32, VDIV_VV }, // 1070 |
| 22341 | { PseudoVDIV_VV_M2_E32_MASK, VDIV_VV }, // 1071 |
| 22342 | { PseudoVDIV_VV_M2_E64, VDIV_VV }, // 1072 |
| 22343 | { PseudoVDIV_VV_M2_E64_MASK, VDIV_VV }, // 1073 |
| 22344 | { PseudoVDIV_VV_M2_E8, VDIV_VV }, // 1074 |
| 22345 | { PseudoVDIV_VV_M2_E8_MASK, VDIV_VV }, // 1075 |
| 22346 | { PseudoVDIV_VV_M4_E16, VDIV_VV }, // 1076 |
| 22347 | { PseudoVDIV_VV_M4_E16_MASK, VDIV_VV }, // 1077 |
| 22348 | { PseudoVDIV_VV_M4_E32, VDIV_VV }, // 1078 |
| 22349 | { PseudoVDIV_VV_M4_E32_MASK, VDIV_VV }, // 1079 |
| 22350 | { PseudoVDIV_VV_M4_E64, VDIV_VV }, // 1080 |
| 22351 | { PseudoVDIV_VV_M4_E64_MASK, VDIV_VV }, // 1081 |
| 22352 | { PseudoVDIV_VV_M4_E8, VDIV_VV }, // 1082 |
| 22353 | { PseudoVDIV_VV_M4_E8_MASK, VDIV_VV }, // 1083 |
| 22354 | { PseudoVDIV_VV_M8_E16, VDIV_VV }, // 1084 |
| 22355 | { PseudoVDIV_VV_M8_E16_MASK, VDIV_VV }, // 1085 |
| 22356 | { PseudoVDIV_VV_M8_E32, VDIV_VV }, // 1086 |
| 22357 | { PseudoVDIV_VV_M8_E32_MASK, VDIV_VV }, // 1087 |
| 22358 | { PseudoVDIV_VV_M8_E64, VDIV_VV }, // 1088 |
| 22359 | { PseudoVDIV_VV_M8_E64_MASK, VDIV_VV }, // 1089 |
| 22360 | { PseudoVDIV_VV_M8_E8, VDIV_VV }, // 1090 |
| 22361 | { PseudoVDIV_VV_M8_E8_MASK, VDIV_VV }, // 1091 |
| 22362 | { PseudoVDIV_VV_MF2_E16, VDIV_VV }, // 1092 |
| 22363 | { PseudoVDIV_VV_MF2_E16_MASK, VDIV_VV }, // 1093 |
| 22364 | { PseudoVDIV_VV_MF2_E32, VDIV_VV }, // 1094 |
| 22365 | { PseudoVDIV_VV_MF2_E32_MASK, VDIV_VV }, // 1095 |
| 22366 | { PseudoVDIV_VV_MF2_E8, VDIV_VV }, // 1096 |
| 22367 | { PseudoVDIV_VV_MF2_E8_MASK, VDIV_VV }, // 1097 |
| 22368 | { PseudoVDIV_VV_MF4_E16, VDIV_VV }, // 1098 |
| 22369 | { PseudoVDIV_VV_MF4_E16_MASK, VDIV_VV }, // 1099 |
| 22370 | { PseudoVDIV_VV_MF4_E8, VDIV_VV }, // 1100 |
| 22371 | { PseudoVDIV_VV_MF4_E8_MASK, VDIV_VV }, // 1101 |
| 22372 | { PseudoVDIV_VV_MF8_E8, VDIV_VV }, // 1102 |
| 22373 | { PseudoVDIV_VV_MF8_E8_MASK, VDIV_VV }, // 1103 |
| 22374 | { PseudoVDIV_VX_M1_E16, VDIV_VX }, // 1104 |
| 22375 | { PseudoVDIV_VX_M1_E16_MASK, VDIV_VX }, // 1105 |
| 22376 | { PseudoVDIV_VX_M1_E32, VDIV_VX }, // 1106 |
| 22377 | { PseudoVDIV_VX_M1_E32_MASK, VDIV_VX }, // 1107 |
| 22378 | { PseudoVDIV_VX_M1_E64, VDIV_VX }, // 1108 |
| 22379 | { PseudoVDIV_VX_M1_E64_MASK, VDIV_VX }, // 1109 |
| 22380 | { PseudoVDIV_VX_M1_E8, VDIV_VX }, // 1110 |
| 22381 | { PseudoVDIV_VX_M1_E8_MASK, VDIV_VX }, // 1111 |
| 22382 | { PseudoVDIV_VX_M2_E16, VDIV_VX }, // 1112 |
| 22383 | { PseudoVDIV_VX_M2_E16_MASK, VDIV_VX }, // 1113 |
| 22384 | { PseudoVDIV_VX_M2_E32, VDIV_VX }, // 1114 |
| 22385 | { PseudoVDIV_VX_M2_E32_MASK, VDIV_VX }, // 1115 |
| 22386 | { PseudoVDIV_VX_M2_E64, VDIV_VX }, // 1116 |
| 22387 | { PseudoVDIV_VX_M2_E64_MASK, VDIV_VX }, // 1117 |
| 22388 | { PseudoVDIV_VX_M2_E8, VDIV_VX }, // 1118 |
| 22389 | { PseudoVDIV_VX_M2_E8_MASK, VDIV_VX }, // 1119 |
| 22390 | { PseudoVDIV_VX_M4_E16, VDIV_VX }, // 1120 |
| 22391 | { PseudoVDIV_VX_M4_E16_MASK, VDIV_VX }, // 1121 |
| 22392 | { PseudoVDIV_VX_M4_E32, VDIV_VX }, // 1122 |
| 22393 | { PseudoVDIV_VX_M4_E32_MASK, VDIV_VX }, // 1123 |
| 22394 | { PseudoVDIV_VX_M4_E64, VDIV_VX }, // 1124 |
| 22395 | { PseudoVDIV_VX_M4_E64_MASK, VDIV_VX }, // 1125 |
| 22396 | { PseudoVDIV_VX_M4_E8, VDIV_VX }, // 1126 |
| 22397 | { PseudoVDIV_VX_M4_E8_MASK, VDIV_VX }, // 1127 |
| 22398 | { PseudoVDIV_VX_M8_E16, VDIV_VX }, // 1128 |
| 22399 | { PseudoVDIV_VX_M8_E16_MASK, VDIV_VX }, // 1129 |
| 22400 | { PseudoVDIV_VX_M8_E32, VDIV_VX }, // 1130 |
| 22401 | { PseudoVDIV_VX_M8_E32_MASK, VDIV_VX }, // 1131 |
| 22402 | { PseudoVDIV_VX_M8_E64, VDIV_VX }, // 1132 |
| 22403 | { PseudoVDIV_VX_M8_E64_MASK, VDIV_VX }, // 1133 |
| 22404 | { PseudoVDIV_VX_M8_E8, VDIV_VX }, // 1134 |
| 22405 | { PseudoVDIV_VX_M8_E8_MASK, VDIV_VX }, // 1135 |
| 22406 | { PseudoVDIV_VX_MF2_E16, VDIV_VX }, // 1136 |
| 22407 | { PseudoVDIV_VX_MF2_E16_MASK, VDIV_VX }, // 1137 |
| 22408 | { PseudoVDIV_VX_MF2_E32, VDIV_VX }, // 1138 |
| 22409 | { PseudoVDIV_VX_MF2_E32_MASK, VDIV_VX }, // 1139 |
| 22410 | { PseudoVDIV_VX_MF2_E8, VDIV_VX }, // 1140 |
| 22411 | { PseudoVDIV_VX_MF2_E8_MASK, VDIV_VX }, // 1141 |
| 22412 | { PseudoVDIV_VX_MF4_E16, VDIV_VX }, // 1142 |
| 22413 | { PseudoVDIV_VX_MF4_E16_MASK, VDIV_VX }, // 1143 |
| 22414 | { PseudoVDIV_VX_MF4_E8, VDIV_VX }, // 1144 |
| 22415 | { PseudoVDIV_VX_MF4_E8_MASK, VDIV_VX }, // 1145 |
| 22416 | { PseudoVDIV_VX_MF8_E8, VDIV_VX }, // 1146 |
| 22417 | { PseudoVDIV_VX_MF8_E8_MASK, VDIV_VX }, // 1147 |
| 22418 | { PseudoVFADD_VFPR16_M1_E16, VFADD_VF }, // 1148 |
| 22419 | { PseudoVFADD_VFPR16_M1_E16_MASK, VFADD_VF }, // 1149 |
| 22420 | { PseudoVFADD_VFPR16_M2_E16, VFADD_VF }, // 1150 |
| 22421 | { PseudoVFADD_VFPR16_M2_E16_MASK, VFADD_VF }, // 1151 |
| 22422 | { PseudoVFADD_VFPR16_M4_E16, VFADD_VF }, // 1152 |
| 22423 | { PseudoVFADD_VFPR16_M4_E16_MASK, VFADD_VF }, // 1153 |
| 22424 | { PseudoVFADD_VFPR16_M8_E16, VFADD_VF }, // 1154 |
| 22425 | { PseudoVFADD_VFPR16_M8_E16_MASK, VFADD_VF }, // 1155 |
| 22426 | { PseudoVFADD_VFPR16_MF2_E16, VFADD_VF }, // 1156 |
| 22427 | { PseudoVFADD_VFPR16_MF2_E16_MASK, VFADD_VF }, // 1157 |
| 22428 | { PseudoVFADD_VFPR16_MF4_E16, VFADD_VF }, // 1158 |
| 22429 | { PseudoVFADD_VFPR16_MF4_E16_MASK, VFADD_VF }, // 1159 |
| 22430 | { PseudoVFADD_VFPR32_M1_E32, VFADD_VF }, // 1160 |
| 22431 | { PseudoVFADD_VFPR32_M1_E32_MASK, VFADD_VF }, // 1161 |
| 22432 | { PseudoVFADD_VFPR32_M2_E32, VFADD_VF }, // 1162 |
| 22433 | { PseudoVFADD_VFPR32_M2_E32_MASK, VFADD_VF }, // 1163 |
| 22434 | { PseudoVFADD_VFPR32_M4_E32, VFADD_VF }, // 1164 |
| 22435 | { PseudoVFADD_VFPR32_M4_E32_MASK, VFADD_VF }, // 1165 |
| 22436 | { PseudoVFADD_VFPR32_M8_E32, VFADD_VF }, // 1166 |
| 22437 | { PseudoVFADD_VFPR32_M8_E32_MASK, VFADD_VF }, // 1167 |
| 22438 | { PseudoVFADD_VFPR32_MF2_E32, VFADD_VF }, // 1168 |
| 22439 | { PseudoVFADD_VFPR32_MF2_E32_MASK, VFADD_VF }, // 1169 |
| 22440 | { PseudoVFADD_VFPR64_M1_E64, VFADD_VF }, // 1170 |
| 22441 | { PseudoVFADD_VFPR64_M1_E64_MASK, VFADD_VF }, // 1171 |
| 22442 | { PseudoVFADD_VFPR64_M2_E64, VFADD_VF }, // 1172 |
| 22443 | { PseudoVFADD_VFPR64_M2_E64_MASK, VFADD_VF }, // 1173 |
| 22444 | { PseudoVFADD_VFPR64_M4_E64, VFADD_VF }, // 1174 |
| 22445 | { PseudoVFADD_VFPR64_M4_E64_MASK, VFADD_VF }, // 1175 |
| 22446 | { PseudoVFADD_VFPR64_M8_E64, VFADD_VF }, // 1176 |
| 22447 | { PseudoVFADD_VFPR64_M8_E64_MASK, VFADD_VF }, // 1177 |
| 22448 | { PseudoVFADD_VV_M1_E16, VFADD_VV }, // 1178 |
| 22449 | { PseudoVFADD_VV_M1_E16_MASK, VFADD_VV }, // 1179 |
| 22450 | { PseudoVFADD_VV_M1_E32, VFADD_VV }, // 1180 |
| 22451 | { PseudoVFADD_VV_M1_E32_MASK, VFADD_VV }, // 1181 |
| 22452 | { PseudoVFADD_VV_M1_E64, VFADD_VV }, // 1182 |
| 22453 | { PseudoVFADD_VV_M1_E64_MASK, VFADD_VV }, // 1183 |
| 22454 | { PseudoVFADD_VV_M2_E16, VFADD_VV }, // 1184 |
| 22455 | { PseudoVFADD_VV_M2_E16_MASK, VFADD_VV }, // 1185 |
| 22456 | { PseudoVFADD_VV_M2_E32, VFADD_VV }, // 1186 |
| 22457 | { PseudoVFADD_VV_M2_E32_MASK, VFADD_VV }, // 1187 |
| 22458 | { PseudoVFADD_VV_M2_E64, VFADD_VV }, // 1188 |
| 22459 | { PseudoVFADD_VV_M2_E64_MASK, VFADD_VV }, // 1189 |
| 22460 | { PseudoVFADD_VV_M4_E16, VFADD_VV }, // 1190 |
| 22461 | { PseudoVFADD_VV_M4_E16_MASK, VFADD_VV }, // 1191 |
| 22462 | { PseudoVFADD_VV_M4_E32, VFADD_VV }, // 1192 |
| 22463 | { PseudoVFADD_VV_M4_E32_MASK, VFADD_VV }, // 1193 |
| 22464 | { PseudoVFADD_VV_M4_E64, VFADD_VV }, // 1194 |
| 22465 | { PseudoVFADD_VV_M4_E64_MASK, VFADD_VV }, // 1195 |
| 22466 | { PseudoVFADD_VV_M8_E16, VFADD_VV }, // 1196 |
| 22467 | { PseudoVFADD_VV_M8_E16_MASK, VFADD_VV }, // 1197 |
| 22468 | { PseudoVFADD_VV_M8_E32, VFADD_VV }, // 1198 |
| 22469 | { PseudoVFADD_VV_M8_E32_MASK, VFADD_VV }, // 1199 |
| 22470 | { PseudoVFADD_VV_M8_E64, VFADD_VV }, // 1200 |
| 22471 | { PseudoVFADD_VV_M8_E64_MASK, VFADD_VV }, // 1201 |
| 22472 | { PseudoVFADD_VV_MF2_E16, VFADD_VV }, // 1202 |
| 22473 | { PseudoVFADD_VV_MF2_E16_MASK, VFADD_VV }, // 1203 |
| 22474 | { PseudoVFADD_VV_MF2_E32, VFADD_VV }, // 1204 |
| 22475 | { PseudoVFADD_VV_MF2_E32_MASK, VFADD_VV }, // 1205 |
| 22476 | { PseudoVFADD_VV_MF4_E16, VFADD_VV }, // 1206 |
| 22477 | { PseudoVFADD_VV_MF4_E16_MASK, VFADD_VV }, // 1207 |
| 22478 | { PseudoVFCLASS_V_M1, VFCLASS_V }, // 1208 |
| 22479 | { PseudoVFCLASS_V_M1_MASK, VFCLASS_V }, // 1209 |
| 22480 | { PseudoVFCLASS_V_M2, VFCLASS_V }, // 1210 |
| 22481 | { PseudoVFCLASS_V_M2_MASK, VFCLASS_V }, // 1211 |
| 22482 | { PseudoVFCLASS_V_M4, VFCLASS_V }, // 1212 |
| 22483 | { PseudoVFCLASS_V_M4_MASK, VFCLASS_V }, // 1213 |
| 22484 | { PseudoVFCLASS_V_M8, VFCLASS_V }, // 1214 |
| 22485 | { PseudoVFCLASS_V_M8_MASK, VFCLASS_V }, // 1215 |
| 22486 | { PseudoVFCLASS_V_MF2, VFCLASS_V }, // 1216 |
| 22487 | { PseudoVFCLASS_V_MF2_MASK, VFCLASS_V }, // 1217 |
| 22488 | { PseudoVFCLASS_V_MF4, VFCLASS_V }, // 1218 |
| 22489 | { PseudoVFCLASS_V_MF4_MASK, VFCLASS_V }, // 1219 |
| 22490 | { PseudoVFCVT_F_XU_V_M1_E16, VFCVT_F_XU_V }, // 1220 |
| 22491 | { PseudoVFCVT_F_XU_V_M1_E16_MASK, VFCVT_F_XU_V }, // 1221 |
| 22492 | { PseudoVFCVT_F_XU_V_M1_E32, VFCVT_F_XU_V }, // 1222 |
| 22493 | { PseudoVFCVT_F_XU_V_M1_E32_MASK, VFCVT_F_XU_V }, // 1223 |
| 22494 | { PseudoVFCVT_F_XU_V_M1_E64, VFCVT_F_XU_V }, // 1224 |
| 22495 | { PseudoVFCVT_F_XU_V_M1_E64_MASK, VFCVT_F_XU_V }, // 1225 |
| 22496 | { PseudoVFCVT_F_XU_V_M2_E16, VFCVT_F_XU_V }, // 1226 |
| 22497 | { PseudoVFCVT_F_XU_V_M2_E16_MASK, VFCVT_F_XU_V }, // 1227 |
| 22498 | { PseudoVFCVT_F_XU_V_M2_E32, VFCVT_F_XU_V }, // 1228 |
| 22499 | { PseudoVFCVT_F_XU_V_M2_E32_MASK, VFCVT_F_XU_V }, // 1229 |
| 22500 | { PseudoVFCVT_F_XU_V_M2_E64, VFCVT_F_XU_V }, // 1230 |
| 22501 | { PseudoVFCVT_F_XU_V_M2_E64_MASK, VFCVT_F_XU_V }, // 1231 |
| 22502 | { PseudoVFCVT_F_XU_V_M4_E16, VFCVT_F_XU_V }, // 1232 |
| 22503 | { PseudoVFCVT_F_XU_V_M4_E16_MASK, VFCVT_F_XU_V }, // 1233 |
| 22504 | { PseudoVFCVT_F_XU_V_M4_E32, VFCVT_F_XU_V }, // 1234 |
| 22505 | { PseudoVFCVT_F_XU_V_M4_E32_MASK, VFCVT_F_XU_V }, // 1235 |
| 22506 | { PseudoVFCVT_F_XU_V_M4_E64, VFCVT_F_XU_V }, // 1236 |
| 22507 | { PseudoVFCVT_F_XU_V_M4_E64_MASK, VFCVT_F_XU_V }, // 1237 |
| 22508 | { PseudoVFCVT_F_XU_V_M8_E16, VFCVT_F_XU_V }, // 1238 |
| 22509 | { PseudoVFCVT_F_XU_V_M8_E16_MASK, VFCVT_F_XU_V }, // 1239 |
| 22510 | { PseudoVFCVT_F_XU_V_M8_E32, VFCVT_F_XU_V }, // 1240 |
| 22511 | { PseudoVFCVT_F_XU_V_M8_E32_MASK, VFCVT_F_XU_V }, // 1241 |
| 22512 | { PseudoVFCVT_F_XU_V_M8_E64, VFCVT_F_XU_V }, // 1242 |
| 22513 | { PseudoVFCVT_F_XU_V_M8_E64_MASK, VFCVT_F_XU_V }, // 1243 |
| 22514 | { PseudoVFCVT_F_XU_V_MF2_E16, VFCVT_F_XU_V }, // 1244 |
| 22515 | { PseudoVFCVT_F_XU_V_MF2_E16_MASK, VFCVT_F_XU_V }, // 1245 |
| 22516 | { PseudoVFCVT_F_XU_V_MF2_E32, VFCVT_F_XU_V }, // 1246 |
| 22517 | { PseudoVFCVT_F_XU_V_MF2_E32_MASK, VFCVT_F_XU_V }, // 1247 |
| 22518 | { PseudoVFCVT_F_XU_V_MF4_E16, VFCVT_F_XU_V }, // 1248 |
| 22519 | { PseudoVFCVT_F_XU_V_MF4_E16_MASK, VFCVT_F_XU_V }, // 1249 |
| 22520 | { PseudoVFCVT_F_X_V_M1_E16, VFCVT_F_X_V }, // 1250 |
| 22521 | { PseudoVFCVT_F_X_V_M1_E16_MASK, VFCVT_F_X_V }, // 1251 |
| 22522 | { PseudoVFCVT_F_X_V_M1_E32, VFCVT_F_X_V }, // 1252 |
| 22523 | { PseudoVFCVT_F_X_V_M1_E32_MASK, VFCVT_F_X_V }, // 1253 |
| 22524 | { PseudoVFCVT_F_X_V_M1_E64, VFCVT_F_X_V }, // 1254 |
| 22525 | { PseudoVFCVT_F_X_V_M1_E64_MASK, VFCVT_F_X_V }, // 1255 |
| 22526 | { PseudoVFCVT_F_X_V_M2_E16, VFCVT_F_X_V }, // 1256 |
| 22527 | { PseudoVFCVT_F_X_V_M2_E16_MASK, VFCVT_F_X_V }, // 1257 |
| 22528 | { PseudoVFCVT_F_X_V_M2_E32, VFCVT_F_X_V }, // 1258 |
| 22529 | { PseudoVFCVT_F_X_V_M2_E32_MASK, VFCVT_F_X_V }, // 1259 |
| 22530 | { PseudoVFCVT_F_X_V_M2_E64, VFCVT_F_X_V }, // 1260 |
| 22531 | { PseudoVFCVT_F_X_V_M2_E64_MASK, VFCVT_F_X_V }, // 1261 |
| 22532 | { PseudoVFCVT_F_X_V_M4_E16, VFCVT_F_X_V }, // 1262 |
| 22533 | { PseudoVFCVT_F_X_V_M4_E16_MASK, VFCVT_F_X_V }, // 1263 |
| 22534 | { PseudoVFCVT_F_X_V_M4_E32, VFCVT_F_X_V }, // 1264 |
| 22535 | { PseudoVFCVT_F_X_V_M4_E32_MASK, VFCVT_F_X_V }, // 1265 |
| 22536 | { PseudoVFCVT_F_X_V_M4_E64, VFCVT_F_X_V }, // 1266 |
| 22537 | { PseudoVFCVT_F_X_V_M4_E64_MASK, VFCVT_F_X_V }, // 1267 |
| 22538 | { PseudoVFCVT_F_X_V_M8_E16, VFCVT_F_X_V }, // 1268 |
| 22539 | { PseudoVFCVT_F_X_V_M8_E16_MASK, VFCVT_F_X_V }, // 1269 |
| 22540 | { PseudoVFCVT_F_X_V_M8_E32, VFCVT_F_X_V }, // 1270 |
| 22541 | { PseudoVFCVT_F_X_V_M8_E32_MASK, VFCVT_F_X_V }, // 1271 |
| 22542 | { PseudoVFCVT_F_X_V_M8_E64, VFCVT_F_X_V }, // 1272 |
| 22543 | { PseudoVFCVT_F_X_V_M8_E64_MASK, VFCVT_F_X_V }, // 1273 |
| 22544 | { PseudoVFCVT_F_X_V_MF2_E16, VFCVT_F_X_V }, // 1274 |
| 22545 | { PseudoVFCVT_F_X_V_MF2_E16_MASK, VFCVT_F_X_V }, // 1275 |
| 22546 | { PseudoVFCVT_F_X_V_MF2_E32, VFCVT_F_X_V }, // 1276 |
| 22547 | { PseudoVFCVT_F_X_V_MF2_E32_MASK, VFCVT_F_X_V }, // 1277 |
| 22548 | { PseudoVFCVT_F_X_V_MF4_E16, VFCVT_F_X_V }, // 1278 |
| 22549 | { PseudoVFCVT_F_X_V_MF4_E16_MASK, VFCVT_F_X_V }, // 1279 |
| 22550 | { PseudoVFCVT_RM_F_XU_V_M1_E16, VFCVT_F_XU_V }, // 1280 |
| 22551 | { PseudoVFCVT_RM_F_XU_V_M1_E16_MASK, VFCVT_F_XU_V }, // 1281 |
| 22552 | { PseudoVFCVT_RM_F_XU_V_M1_E32, VFCVT_F_XU_V }, // 1282 |
| 22553 | { PseudoVFCVT_RM_F_XU_V_M1_E32_MASK, VFCVT_F_XU_V }, // 1283 |
| 22554 | { PseudoVFCVT_RM_F_XU_V_M1_E64, VFCVT_F_XU_V }, // 1284 |
| 22555 | { PseudoVFCVT_RM_F_XU_V_M1_E64_MASK, VFCVT_F_XU_V }, // 1285 |
| 22556 | { PseudoVFCVT_RM_F_XU_V_M2_E16, VFCVT_F_XU_V }, // 1286 |
| 22557 | { PseudoVFCVT_RM_F_XU_V_M2_E16_MASK, VFCVT_F_XU_V }, // 1287 |
| 22558 | { PseudoVFCVT_RM_F_XU_V_M2_E32, VFCVT_F_XU_V }, // 1288 |
| 22559 | { PseudoVFCVT_RM_F_XU_V_M2_E32_MASK, VFCVT_F_XU_V }, // 1289 |
| 22560 | { PseudoVFCVT_RM_F_XU_V_M2_E64, VFCVT_F_XU_V }, // 1290 |
| 22561 | { PseudoVFCVT_RM_F_XU_V_M2_E64_MASK, VFCVT_F_XU_V }, // 1291 |
| 22562 | { PseudoVFCVT_RM_F_XU_V_M4_E16, VFCVT_F_XU_V }, // 1292 |
| 22563 | { PseudoVFCVT_RM_F_XU_V_M4_E16_MASK, VFCVT_F_XU_V }, // 1293 |
| 22564 | { PseudoVFCVT_RM_F_XU_V_M4_E32, VFCVT_F_XU_V }, // 1294 |
| 22565 | { PseudoVFCVT_RM_F_XU_V_M4_E32_MASK, VFCVT_F_XU_V }, // 1295 |
| 22566 | { PseudoVFCVT_RM_F_XU_V_M4_E64, VFCVT_F_XU_V }, // 1296 |
| 22567 | { PseudoVFCVT_RM_F_XU_V_M4_E64_MASK, VFCVT_F_XU_V }, // 1297 |
| 22568 | { PseudoVFCVT_RM_F_XU_V_M8_E16, VFCVT_F_XU_V }, // 1298 |
| 22569 | { PseudoVFCVT_RM_F_XU_V_M8_E16_MASK, VFCVT_F_XU_V }, // 1299 |
| 22570 | { PseudoVFCVT_RM_F_XU_V_M8_E32, VFCVT_F_XU_V }, // 1300 |
| 22571 | { PseudoVFCVT_RM_F_XU_V_M8_E32_MASK, VFCVT_F_XU_V }, // 1301 |
| 22572 | { PseudoVFCVT_RM_F_XU_V_M8_E64, VFCVT_F_XU_V }, // 1302 |
| 22573 | { PseudoVFCVT_RM_F_XU_V_M8_E64_MASK, VFCVT_F_XU_V }, // 1303 |
| 22574 | { PseudoVFCVT_RM_F_XU_V_MF2_E16, VFCVT_F_XU_V }, // 1304 |
| 22575 | { PseudoVFCVT_RM_F_XU_V_MF2_E16_MASK, VFCVT_F_XU_V }, // 1305 |
| 22576 | { PseudoVFCVT_RM_F_XU_V_MF2_E32, VFCVT_F_XU_V }, // 1306 |
| 22577 | { PseudoVFCVT_RM_F_XU_V_MF2_E32_MASK, VFCVT_F_XU_V }, // 1307 |
| 22578 | { PseudoVFCVT_RM_F_XU_V_MF4_E16, VFCVT_F_XU_V }, // 1308 |
| 22579 | { PseudoVFCVT_RM_F_XU_V_MF4_E16_MASK, VFCVT_F_XU_V }, // 1309 |
| 22580 | { PseudoVFCVT_RM_F_X_V_M1_E16, VFCVT_F_X_V }, // 1310 |
| 22581 | { PseudoVFCVT_RM_F_X_V_M1_E16_MASK, VFCVT_F_X_V }, // 1311 |
| 22582 | { PseudoVFCVT_RM_F_X_V_M1_E32, VFCVT_F_X_V }, // 1312 |
| 22583 | { PseudoVFCVT_RM_F_X_V_M1_E32_MASK, VFCVT_F_X_V }, // 1313 |
| 22584 | { PseudoVFCVT_RM_F_X_V_M1_E64, VFCVT_F_X_V }, // 1314 |
| 22585 | { PseudoVFCVT_RM_F_X_V_M1_E64_MASK, VFCVT_F_X_V }, // 1315 |
| 22586 | { PseudoVFCVT_RM_F_X_V_M2_E16, VFCVT_F_X_V }, // 1316 |
| 22587 | { PseudoVFCVT_RM_F_X_V_M2_E16_MASK, VFCVT_F_X_V }, // 1317 |
| 22588 | { PseudoVFCVT_RM_F_X_V_M2_E32, VFCVT_F_X_V }, // 1318 |
| 22589 | { PseudoVFCVT_RM_F_X_V_M2_E32_MASK, VFCVT_F_X_V }, // 1319 |
| 22590 | { PseudoVFCVT_RM_F_X_V_M2_E64, VFCVT_F_X_V }, // 1320 |
| 22591 | { PseudoVFCVT_RM_F_X_V_M2_E64_MASK, VFCVT_F_X_V }, // 1321 |
| 22592 | { PseudoVFCVT_RM_F_X_V_M4_E16, VFCVT_F_X_V }, // 1322 |
| 22593 | { PseudoVFCVT_RM_F_X_V_M4_E16_MASK, VFCVT_F_X_V }, // 1323 |
| 22594 | { PseudoVFCVT_RM_F_X_V_M4_E32, VFCVT_F_X_V }, // 1324 |
| 22595 | { PseudoVFCVT_RM_F_X_V_M4_E32_MASK, VFCVT_F_X_V }, // 1325 |
| 22596 | { PseudoVFCVT_RM_F_X_V_M4_E64, VFCVT_F_X_V }, // 1326 |
| 22597 | { PseudoVFCVT_RM_F_X_V_M4_E64_MASK, VFCVT_F_X_V }, // 1327 |
| 22598 | { PseudoVFCVT_RM_F_X_V_M8_E16, VFCVT_F_X_V }, // 1328 |
| 22599 | { PseudoVFCVT_RM_F_X_V_M8_E16_MASK, VFCVT_F_X_V }, // 1329 |
| 22600 | { PseudoVFCVT_RM_F_X_V_M8_E32, VFCVT_F_X_V }, // 1330 |
| 22601 | { PseudoVFCVT_RM_F_X_V_M8_E32_MASK, VFCVT_F_X_V }, // 1331 |
| 22602 | { PseudoVFCVT_RM_F_X_V_M8_E64, VFCVT_F_X_V }, // 1332 |
| 22603 | { PseudoVFCVT_RM_F_X_V_M8_E64_MASK, VFCVT_F_X_V }, // 1333 |
| 22604 | { PseudoVFCVT_RM_F_X_V_MF2_E16, VFCVT_F_X_V }, // 1334 |
| 22605 | { PseudoVFCVT_RM_F_X_V_MF2_E16_MASK, VFCVT_F_X_V }, // 1335 |
| 22606 | { PseudoVFCVT_RM_F_X_V_MF2_E32, VFCVT_F_X_V }, // 1336 |
| 22607 | { PseudoVFCVT_RM_F_X_V_MF2_E32_MASK, VFCVT_F_X_V }, // 1337 |
| 22608 | { PseudoVFCVT_RM_F_X_V_MF4_E16, VFCVT_F_X_V }, // 1338 |
| 22609 | { PseudoVFCVT_RM_F_X_V_MF4_E16_MASK, VFCVT_F_X_V }, // 1339 |
| 22610 | { PseudoVFCVT_RM_XU_F_V_M1, VFCVT_XU_F_V }, // 1340 |
| 22611 | { PseudoVFCVT_RM_XU_F_V_M1_MASK, VFCVT_XU_F_V }, // 1341 |
| 22612 | { PseudoVFCVT_RM_XU_F_V_M2, VFCVT_XU_F_V }, // 1342 |
| 22613 | { PseudoVFCVT_RM_XU_F_V_M2_MASK, VFCVT_XU_F_V }, // 1343 |
| 22614 | { PseudoVFCVT_RM_XU_F_V_M4, VFCVT_XU_F_V }, // 1344 |
| 22615 | { PseudoVFCVT_RM_XU_F_V_M4_MASK, VFCVT_XU_F_V }, // 1345 |
| 22616 | { PseudoVFCVT_RM_XU_F_V_M8, VFCVT_XU_F_V }, // 1346 |
| 22617 | { PseudoVFCVT_RM_XU_F_V_M8_MASK, VFCVT_XU_F_V }, // 1347 |
| 22618 | { PseudoVFCVT_RM_XU_F_V_MF2, VFCVT_XU_F_V }, // 1348 |
| 22619 | { PseudoVFCVT_RM_XU_F_V_MF2_MASK, VFCVT_XU_F_V }, // 1349 |
| 22620 | { PseudoVFCVT_RM_XU_F_V_MF4, VFCVT_XU_F_V }, // 1350 |
| 22621 | { PseudoVFCVT_RM_XU_F_V_MF4_MASK, VFCVT_XU_F_V }, // 1351 |
| 22622 | { PseudoVFCVT_RM_X_F_V_M1, VFCVT_X_F_V }, // 1352 |
| 22623 | { PseudoVFCVT_RM_X_F_V_M1_MASK, VFCVT_X_F_V }, // 1353 |
| 22624 | { PseudoVFCVT_RM_X_F_V_M2, VFCVT_X_F_V }, // 1354 |
| 22625 | { PseudoVFCVT_RM_X_F_V_M2_MASK, VFCVT_X_F_V }, // 1355 |
| 22626 | { PseudoVFCVT_RM_X_F_V_M4, VFCVT_X_F_V }, // 1356 |
| 22627 | { PseudoVFCVT_RM_X_F_V_M4_MASK, VFCVT_X_F_V }, // 1357 |
| 22628 | { PseudoVFCVT_RM_X_F_V_M8, VFCVT_X_F_V }, // 1358 |
| 22629 | { PseudoVFCVT_RM_X_F_V_M8_MASK, VFCVT_X_F_V }, // 1359 |
| 22630 | { PseudoVFCVT_RM_X_F_V_MF2, VFCVT_X_F_V }, // 1360 |
| 22631 | { PseudoVFCVT_RM_X_F_V_MF2_MASK, VFCVT_X_F_V }, // 1361 |
| 22632 | { PseudoVFCVT_RM_X_F_V_MF4, VFCVT_X_F_V }, // 1362 |
| 22633 | { PseudoVFCVT_RM_X_F_V_MF4_MASK, VFCVT_X_F_V }, // 1363 |
| 22634 | { PseudoVFCVT_RTZ_XU_F_V_M1, VFCVT_RTZ_XU_F_V }, // 1364 |
| 22635 | { PseudoVFCVT_RTZ_XU_F_V_M1_MASK, VFCVT_RTZ_XU_F_V }, // 1365 |
| 22636 | { PseudoVFCVT_RTZ_XU_F_V_M2, VFCVT_RTZ_XU_F_V }, // 1366 |
| 22637 | { PseudoVFCVT_RTZ_XU_F_V_M2_MASK, VFCVT_RTZ_XU_F_V }, // 1367 |
| 22638 | { PseudoVFCVT_RTZ_XU_F_V_M4, VFCVT_RTZ_XU_F_V }, // 1368 |
| 22639 | { PseudoVFCVT_RTZ_XU_F_V_M4_MASK, VFCVT_RTZ_XU_F_V }, // 1369 |
| 22640 | { PseudoVFCVT_RTZ_XU_F_V_M8, VFCVT_RTZ_XU_F_V }, // 1370 |
| 22641 | { PseudoVFCVT_RTZ_XU_F_V_M8_MASK, VFCVT_RTZ_XU_F_V }, // 1371 |
| 22642 | { PseudoVFCVT_RTZ_XU_F_V_MF2, VFCVT_RTZ_XU_F_V }, // 1372 |
| 22643 | { PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, VFCVT_RTZ_XU_F_V }, // 1373 |
| 22644 | { PseudoVFCVT_RTZ_XU_F_V_MF4, VFCVT_RTZ_XU_F_V }, // 1374 |
| 22645 | { PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, VFCVT_RTZ_XU_F_V }, // 1375 |
| 22646 | { PseudoVFCVT_RTZ_X_F_V_M1, VFCVT_RTZ_X_F_V }, // 1376 |
| 22647 | { PseudoVFCVT_RTZ_X_F_V_M1_MASK, VFCVT_RTZ_X_F_V }, // 1377 |
| 22648 | { PseudoVFCVT_RTZ_X_F_V_M2, VFCVT_RTZ_X_F_V }, // 1378 |
| 22649 | { PseudoVFCVT_RTZ_X_F_V_M2_MASK, VFCVT_RTZ_X_F_V }, // 1379 |
| 22650 | { PseudoVFCVT_RTZ_X_F_V_M4, VFCVT_RTZ_X_F_V }, // 1380 |
| 22651 | { PseudoVFCVT_RTZ_X_F_V_M4_MASK, VFCVT_RTZ_X_F_V }, // 1381 |
| 22652 | { PseudoVFCVT_RTZ_X_F_V_M8, VFCVT_RTZ_X_F_V }, // 1382 |
| 22653 | { PseudoVFCVT_RTZ_X_F_V_M8_MASK, VFCVT_RTZ_X_F_V }, // 1383 |
| 22654 | { PseudoVFCVT_RTZ_X_F_V_MF2, VFCVT_RTZ_X_F_V }, // 1384 |
| 22655 | { PseudoVFCVT_RTZ_X_F_V_MF2_MASK, VFCVT_RTZ_X_F_V }, // 1385 |
| 22656 | { PseudoVFCVT_RTZ_X_F_V_MF4, VFCVT_RTZ_X_F_V }, // 1386 |
| 22657 | { PseudoVFCVT_RTZ_X_F_V_MF4_MASK, VFCVT_RTZ_X_F_V }, // 1387 |
| 22658 | { PseudoVFCVT_XU_F_V_M1, VFCVT_XU_F_V }, // 1388 |
| 22659 | { PseudoVFCVT_XU_F_V_M1_MASK, VFCVT_XU_F_V }, // 1389 |
| 22660 | { PseudoVFCVT_XU_F_V_M2, VFCVT_XU_F_V }, // 1390 |
| 22661 | { PseudoVFCVT_XU_F_V_M2_MASK, VFCVT_XU_F_V }, // 1391 |
| 22662 | { PseudoVFCVT_XU_F_V_M4, VFCVT_XU_F_V }, // 1392 |
| 22663 | { PseudoVFCVT_XU_F_V_M4_MASK, VFCVT_XU_F_V }, // 1393 |
| 22664 | { PseudoVFCVT_XU_F_V_M8, VFCVT_XU_F_V }, // 1394 |
| 22665 | { PseudoVFCVT_XU_F_V_M8_MASK, VFCVT_XU_F_V }, // 1395 |
| 22666 | { PseudoVFCVT_XU_F_V_MF2, VFCVT_XU_F_V }, // 1396 |
| 22667 | { PseudoVFCVT_XU_F_V_MF2_MASK, VFCVT_XU_F_V }, // 1397 |
| 22668 | { PseudoVFCVT_XU_F_V_MF4, VFCVT_XU_F_V }, // 1398 |
| 22669 | { PseudoVFCVT_XU_F_V_MF4_MASK, VFCVT_XU_F_V }, // 1399 |
| 22670 | { PseudoVFCVT_X_F_V_M1, VFCVT_X_F_V }, // 1400 |
| 22671 | { PseudoVFCVT_X_F_V_M1_MASK, VFCVT_X_F_V }, // 1401 |
| 22672 | { PseudoVFCVT_X_F_V_M2, VFCVT_X_F_V }, // 1402 |
| 22673 | { PseudoVFCVT_X_F_V_M2_MASK, VFCVT_X_F_V }, // 1403 |
| 22674 | { PseudoVFCVT_X_F_V_M4, VFCVT_X_F_V }, // 1404 |
| 22675 | { PseudoVFCVT_X_F_V_M4_MASK, VFCVT_X_F_V }, // 1405 |
| 22676 | { PseudoVFCVT_X_F_V_M8, VFCVT_X_F_V }, // 1406 |
| 22677 | { PseudoVFCVT_X_F_V_M8_MASK, VFCVT_X_F_V }, // 1407 |
| 22678 | { PseudoVFCVT_X_F_V_MF2, VFCVT_X_F_V }, // 1408 |
| 22679 | { PseudoVFCVT_X_F_V_MF2_MASK, VFCVT_X_F_V }, // 1409 |
| 22680 | { PseudoVFCVT_X_F_V_MF4, VFCVT_X_F_V }, // 1410 |
| 22681 | { PseudoVFCVT_X_F_V_MF4_MASK, VFCVT_X_F_V }, // 1411 |
| 22682 | { PseudoVFDIV_VFPR16_M1_E16, VFDIV_VF }, // 1412 |
| 22683 | { PseudoVFDIV_VFPR16_M1_E16_MASK, VFDIV_VF }, // 1413 |
| 22684 | { PseudoVFDIV_VFPR16_M2_E16, VFDIV_VF }, // 1414 |
| 22685 | { PseudoVFDIV_VFPR16_M2_E16_MASK, VFDIV_VF }, // 1415 |
| 22686 | { PseudoVFDIV_VFPR16_M4_E16, VFDIV_VF }, // 1416 |
| 22687 | { PseudoVFDIV_VFPR16_M4_E16_MASK, VFDIV_VF }, // 1417 |
| 22688 | { PseudoVFDIV_VFPR16_M8_E16, VFDIV_VF }, // 1418 |
| 22689 | { PseudoVFDIV_VFPR16_M8_E16_MASK, VFDIV_VF }, // 1419 |
| 22690 | { PseudoVFDIV_VFPR16_MF2_E16, VFDIV_VF }, // 1420 |
| 22691 | { PseudoVFDIV_VFPR16_MF2_E16_MASK, VFDIV_VF }, // 1421 |
| 22692 | { PseudoVFDIV_VFPR16_MF4_E16, VFDIV_VF }, // 1422 |
| 22693 | { PseudoVFDIV_VFPR16_MF4_E16_MASK, VFDIV_VF }, // 1423 |
| 22694 | { PseudoVFDIV_VFPR32_M1_E32, VFDIV_VF }, // 1424 |
| 22695 | { PseudoVFDIV_VFPR32_M1_E32_MASK, VFDIV_VF }, // 1425 |
| 22696 | { PseudoVFDIV_VFPR32_M2_E32, VFDIV_VF }, // 1426 |
| 22697 | { PseudoVFDIV_VFPR32_M2_E32_MASK, VFDIV_VF }, // 1427 |
| 22698 | { PseudoVFDIV_VFPR32_M4_E32, VFDIV_VF }, // 1428 |
| 22699 | { PseudoVFDIV_VFPR32_M4_E32_MASK, VFDIV_VF }, // 1429 |
| 22700 | { PseudoVFDIV_VFPR32_M8_E32, VFDIV_VF }, // 1430 |
| 22701 | { PseudoVFDIV_VFPR32_M8_E32_MASK, VFDIV_VF }, // 1431 |
| 22702 | { PseudoVFDIV_VFPR32_MF2_E32, VFDIV_VF }, // 1432 |
| 22703 | { PseudoVFDIV_VFPR32_MF2_E32_MASK, VFDIV_VF }, // 1433 |
| 22704 | { PseudoVFDIV_VFPR64_M1_E64, VFDIV_VF }, // 1434 |
| 22705 | { PseudoVFDIV_VFPR64_M1_E64_MASK, VFDIV_VF }, // 1435 |
| 22706 | { PseudoVFDIV_VFPR64_M2_E64, VFDIV_VF }, // 1436 |
| 22707 | { PseudoVFDIV_VFPR64_M2_E64_MASK, VFDIV_VF }, // 1437 |
| 22708 | { PseudoVFDIV_VFPR64_M4_E64, VFDIV_VF }, // 1438 |
| 22709 | { PseudoVFDIV_VFPR64_M4_E64_MASK, VFDIV_VF }, // 1439 |
| 22710 | { PseudoVFDIV_VFPR64_M8_E64, VFDIV_VF }, // 1440 |
| 22711 | { PseudoVFDIV_VFPR64_M8_E64_MASK, VFDIV_VF }, // 1441 |
| 22712 | { PseudoVFDIV_VV_M1_E16, VFDIV_VV }, // 1442 |
| 22713 | { PseudoVFDIV_VV_M1_E16_MASK, VFDIV_VV }, // 1443 |
| 22714 | { PseudoVFDIV_VV_M1_E32, VFDIV_VV }, // 1444 |
| 22715 | { PseudoVFDIV_VV_M1_E32_MASK, VFDIV_VV }, // 1445 |
| 22716 | { PseudoVFDIV_VV_M1_E64, VFDIV_VV }, // 1446 |
| 22717 | { PseudoVFDIV_VV_M1_E64_MASK, VFDIV_VV }, // 1447 |
| 22718 | { PseudoVFDIV_VV_M2_E16, VFDIV_VV }, // 1448 |
| 22719 | { PseudoVFDIV_VV_M2_E16_MASK, VFDIV_VV }, // 1449 |
| 22720 | { PseudoVFDIV_VV_M2_E32, VFDIV_VV }, // 1450 |
| 22721 | { PseudoVFDIV_VV_M2_E32_MASK, VFDIV_VV }, // 1451 |
| 22722 | { PseudoVFDIV_VV_M2_E64, VFDIV_VV }, // 1452 |
| 22723 | { PseudoVFDIV_VV_M2_E64_MASK, VFDIV_VV }, // 1453 |
| 22724 | { PseudoVFDIV_VV_M4_E16, VFDIV_VV }, // 1454 |
| 22725 | { PseudoVFDIV_VV_M4_E16_MASK, VFDIV_VV }, // 1455 |
| 22726 | { PseudoVFDIV_VV_M4_E32, VFDIV_VV }, // 1456 |
| 22727 | { PseudoVFDIV_VV_M4_E32_MASK, VFDIV_VV }, // 1457 |
| 22728 | { PseudoVFDIV_VV_M4_E64, VFDIV_VV }, // 1458 |
| 22729 | { PseudoVFDIV_VV_M4_E64_MASK, VFDIV_VV }, // 1459 |
| 22730 | { PseudoVFDIV_VV_M8_E16, VFDIV_VV }, // 1460 |
| 22731 | { PseudoVFDIV_VV_M8_E16_MASK, VFDIV_VV }, // 1461 |
| 22732 | { PseudoVFDIV_VV_M8_E32, VFDIV_VV }, // 1462 |
| 22733 | { PseudoVFDIV_VV_M8_E32_MASK, VFDIV_VV }, // 1463 |
| 22734 | { PseudoVFDIV_VV_M8_E64, VFDIV_VV }, // 1464 |
| 22735 | { PseudoVFDIV_VV_M8_E64_MASK, VFDIV_VV }, // 1465 |
| 22736 | { PseudoVFDIV_VV_MF2_E16, VFDIV_VV }, // 1466 |
| 22737 | { PseudoVFDIV_VV_MF2_E16_MASK, VFDIV_VV }, // 1467 |
| 22738 | { PseudoVFDIV_VV_MF2_E32, VFDIV_VV }, // 1468 |
| 22739 | { PseudoVFDIV_VV_MF2_E32_MASK, VFDIV_VV }, // 1469 |
| 22740 | { PseudoVFDIV_VV_MF4_E16, VFDIV_VV }, // 1470 |
| 22741 | { PseudoVFDIV_VV_MF4_E16_MASK, VFDIV_VV }, // 1471 |
| 22742 | { PseudoVFIRST_M_B1, VFIRST_M }, // 1472 |
| 22743 | { PseudoVFIRST_M_B16, VFIRST_M }, // 1473 |
| 22744 | { PseudoVFIRST_M_B16_MASK, VFIRST_M }, // 1474 |
| 22745 | { PseudoVFIRST_M_B1_MASK, VFIRST_M }, // 1475 |
| 22746 | { PseudoVFIRST_M_B2, VFIRST_M }, // 1476 |
| 22747 | { PseudoVFIRST_M_B2_MASK, VFIRST_M }, // 1477 |
| 22748 | { PseudoVFIRST_M_B32, VFIRST_M }, // 1478 |
| 22749 | { PseudoVFIRST_M_B32_MASK, VFIRST_M }, // 1479 |
| 22750 | { PseudoVFIRST_M_B4, VFIRST_M }, // 1480 |
| 22751 | { PseudoVFIRST_M_B4_MASK, VFIRST_M }, // 1481 |
| 22752 | { PseudoVFIRST_M_B64, VFIRST_M }, // 1482 |
| 22753 | { PseudoVFIRST_M_B64_MASK, VFIRST_M }, // 1483 |
| 22754 | { PseudoVFIRST_M_B8, VFIRST_M }, // 1484 |
| 22755 | { PseudoVFIRST_M_B8_MASK, VFIRST_M }, // 1485 |
| 22756 | { PseudoVFMACC_VFPR16_M1_E16, VFMACC_VF }, // 1486 |
| 22757 | { PseudoVFMACC_VFPR16_M1_E16_MASK, VFMACC_VF }, // 1487 |
| 22758 | { PseudoVFMACC_VFPR16_M2_E16, VFMACC_VF }, // 1488 |
| 22759 | { PseudoVFMACC_VFPR16_M2_E16_MASK, VFMACC_VF }, // 1489 |
| 22760 | { PseudoVFMACC_VFPR16_M4_E16, VFMACC_VF }, // 1490 |
| 22761 | { PseudoVFMACC_VFPR16_M4_E16_MASK, VFMACC_VF }, // 1491 |
| 22762 | { PseudoVFMACC_VFPR16_M8_E16, VFMACC_VF }, // 1492 |
| 22763 | { PseudoVFMACC_VFPR16_M8_E16_MASK, VFMACC_VF }, // 1493 |
| 22764 | { PseudoVFMACC_VFPR16_MF2_E16, VFMACC_VF }, // 1494 |
| 22765 | { PseudoVFMACC_VFPR16_MF2_E16_MASK, VFMACC_VF }, // 1495 |
| 22766 | { PseudoVFMACC_VFPR16_MF4_E16, VFMACC_VF }, // 1496 |
| 22767 | { PseudoVFMACC_VFPR16_MF4_E16_MASK, VFMACC_VF }, // 1497 |
| 22768 | { PseudoVFMACC_VFPR32_M1_E32, VFMACC_VF }, // 1498 |
| 22769 | { PseudoVFMACC_VFPR32_M1_E32_MASK, VFMACC_VF }, // 1499 |
| 22770 | { PseudoVFMACC_VFPR32_M2_E32, VFMACC_VF }, // 1500 |
| 22771 | { PseudoVFMACC_VFPR32_M2_E32_MASK, VFMACC_VF }, // 1501 |
| 22772 | { PseudoVFMACC_VFPR32_M4_E32, VFMACC_VF }, // 1502 |
| 22773 | { PseudoVFMACC_VFPR32_M4_E32_MASK, VFMACC_VF }, // 1503 |
| 22774 | { PseudoVFMACC_VFPR32_M8_E32, VFMACC_VF }, // 1504 |
| 22775 | { PseudoVFMACC_VFPR32_M8_E32_MASK, VFMACC_VF }, // 1505 |
| 22776 | { PseudoVFMACC_VFPR32_MF2_E32, VFMACC_VF }, // 1506 |
| 22777 | { PseudoVFMACC_VFPR32_MF2_E32_MASK, VFMACC_VF }, // 1507 |
| 22778 | { PseudoVFMACC_VFPR64_M1_E64, VFMACC_VF }, // 1508 |
| 22779 | { PseudoVFMACC_VFPR64_M1_E64_MASK, VFMACC_VF }, // 1509 |
| 22780 | { PseudoVFMACC_VFPR64_M2_E64, VFMACC_VF }, // 1510 |
| 22781 | { PseudoVFMACC_VFPR64_M2_E64_MASK, VFMACC_VF }, // 1511 |
| 22782 | { PseudoVFMACC_VFPR64_M4_E64, VFMACC_VF }, // 1512 |
| 22783 | { PseudoVFMACC_VFPR64_M4_E64_MASK, VFMACC_VF }, // 1513 |
| 22784 | { PseudoVFMACC_VFPR64_M8_E64, VFMACC_VF }, // 1514 |
| 22785 | { PseudoVFMACC_VFPR64_M8_E64_MASK, VFMACC_VF }, // 1515 |
| 22786 | { PseudoVFMACC_VV_M1_E16, VFMACC_VV }, // 1516 |
| 22787 | { PseudoVFMACC_VV_M1_E16_MASK, VFMACC_VV }, // 1517 |
| 22788 | { PseudoVFMACC_VV_M1_E32, VFMACC_VV }, // 1518 |
| 22789 | { PseudoVFMACC_VV_M1_E32_MASK, VFMACC_VV }, // 1519 |
| 22790 | { PseudoVFMACC_VV_M1_E64, VFMACC_VV }, // 1520 |
| 22791 | { PseudoVFMACC_VV_M1_E64_MASK, VFMACC_VV }, // 1521 |
| 22792 | { PseudoVFMACC_VV_M2_E16, VFMACC_VV }, // 1522 |
| 22793 | { PseudoVFMACC_VV_M2_E16_MASK, VFMACC_VV }, // 1523 |
| 22794 | { PseudoVFMACC_VV_M2_E32, VFMACC_VV }, // 1524 |
| 22795 | { PseudoVFMACC_VV_M2_E32_MASK, VFMACC_VV }, // 1525 |
| 22796 | { PseudoVFMACC_VV_M2_E64, VFMACC_VV }, // 1526 |
| 22797 | { PseudoVFMACC_VV_M2_E64_MASK, VFMACC_VV }, // 1527 |
| 22798 | { PseudoVFMACC_VV_M4_E16, VFMACC_VV }, // 1528 |
| 22799 | { PseudoVFMACC_VV_M4_E16_MASK, VFMACC_VV }, // 1529 |
| 22800 | { PseudoVFMACC_VV_M4_E32, VFMACC_VV }, // 1530 |
| 22801 | { PseudoVFMACC_VV_M4_E32_MASK, VFMACC_VV }, // 1531 |
| 22802 | { PseudoVFMACC_VV_M4_E64, VFMACC_VV }, // 1532 |
| 22803 | { PseudoVFMACC_VV_M4_E64_MASK, VFMACC_VV }, // 1533 |
| 22804 | { PseudoVFMACC_VV_M8_E16, VFMACC_VV }, // 1534 |
| 22805 | { PseudoVFMACC_VV_M8_E16_MASK, VFMACC_VV }, // 1535 |
| 22806 | { PseudoVFMACC_VV_M8_E32, VFMACC_VV }, // 1536 |
| 22807 | { PseudoVFMACC_VV_M8_E32_MASK, VFMACC_VV }, // 1537 |
| 22808 | { PseudoVFMACC_VV_M8_E64, VFMACC_VV }, // 1538 |
| 22809 | { PseudoVFMACC_VV_M8_E64_MASK, VFMACC_VV }, // 1539 |
| 22810 | { PseudoVFMACC_VV_MF2_E16, VFMACC_VV }, // 1540 |
| 22811 | { PseudoVFMACC_VV_MF2_E16_MASK, VFMACC_VV }, // 1541 |
| 22812 | { PseudoVFMACC_VV_MF2_E32, VFMACC_VV }, // 1542 |
| 22813 | { PseudoVFMACC_VV_MF2_E32_MASK, VFMACC_VV }, // 1543 |
| 22814 | { PseudoVFMACC_VV_MF4_E16, VFMACC_VV }, // 1544 |
| 22815 | { PseudoVFMACC_VV_MF4_E16_MASK, VFMACC_VV }, // 1545 |
| 22816 | { PseudoVFMADD_VFPR16_M1_E16, VFMADD_VF }, // 1546 |
| 22817 | { PseudoVFMADD_VFPR16_M1_E16_MASK, VFMADD_VF }, // 1547 |
| 22818 | { PseudoVFMADD_VFPR16_M2_E16, VFMADD_VF }, // 1548 |
| 22819 | { PseudoVFMADD_VFPR16_M2_E16_MASK, VFMADD_VF }, // 1549 |
| 22820 | { PseudoVFMADD_VFPR16_M4_E16, VFMADD_VF }, // 1550 |
| 22821 | { PseudoVFMADD_VFPR16_M4_E16_MASK, VFMADD_VF }, // 1551 |
| 22822 | { PseudoVFMADD_VFPR16_M8_E16, VFMADD_VF }, // 1552 |
| 22823 | { PseudoVFMADD_VFPR16_M8_E16_MASK, VFMADD_VF }, // 1553 |
| 22824 | { PseudoVFMADD_VFPR16_MF2_E16, VFMADD_VF }, // 1554 |
| 22825 | { PseudoVFMADD_VFPR16_MF2_E16_MASK, VFMADD_VF }, // 1555 |
| 22826 | { PseudoVFMADD_VFPR16_MF4_E16, VFMADD_VF }, // 1556 |
| 22827 | { PseudoVFMADD_VFPR16_MF4_E16_MASK, VFMADD_VF }, // 1557 |
| 22828 | { PseudoVFMADD_VFPR32_M1_E32, VFMADD_VF }, // 1558 |
| 22829 | { PseudoVFMADD_VFPR32_M1_E32_MASK, VFMADD_VF }, // 1559 |
| 22830 | { PseudoVFMADD_VFPR32_M2_E32, VFMADD_VF }, // 1560 |
| 22831 | { PseudoVFMADD_VFPR32_M2_E32_MASK, VFMADD_VF }, // 1561 |
| 22832 | { PseudoVFMADD_VFPR32_M4_E32, VFMADD_VF }, // 1562 |
| 22833 | { PseudoVFMADD_VFPR32_M4_E32_MASK, VFMADD_VF }, // 1563 |
| 22834 | { PseudoVFMADD_VFPR32_M8_E32, VFMADD_VF }, // 1564 |
| 22835 | { PseudoVFMADD_VFPR32_M8_E32_MASK, VFMADD_VF }, // 1565 |
| 22836 | { PseudoVFMADD_VFPR32_MF2_E32, VFMADD_VF }, // 1566 |
| 22837 | { PseudoVFMADD_VFPR32_MF2_E32_MASK, VFMADD_VF }, // 1567 |
| 22838 | { PseudoVFMADD_VFPR64_M1_E64, VFMADD_VF }, // 1568 |
| 22839 | { PseudoVFMADD_VFPR64_M1_E64_MASK, VFMADD_VF }, // 1569 |
| 22840 | { PseudoVFMADD_VFPR64_M2_E64, VFMADD_VF }, // 1570 |
| 22841 | { PseudoVFMADD_VFPR64_M2_E64_MASK, VFMADD_VF }, // 1571 |
| 22842 | { PseudoVFMADD_VFPR64_M4_E64, VFMADD_VF }, // 1572 |
| 22843 | { PseudoVFMADD_VFPR64_M4_E64_MASK, VFMADD_VF }, // 1573 |
| 22844 | { PseudoVFMADD_VFPR64_M8_E64, VFMADD_VF }, // 1574 |
| 22845 | { PseudoVFMADD_VFPR64_M8_E64_MASK, VFMADD_VF }, // 1575 |
| 22846 | { PseudoVFMADD_VV_M1_E16, VFMADD_VV }, // 1576 |
| 22847 | { PseudoVFMADD_VV_M1_E16_MASK, VFMADD_VV }, // 1577 |
| 22848 | { PseudoVFMADD_VV_M1_E32, VFMADD_VV }, // 1578 |
| 22849 | { PseudoVFMADD_VV_M1_E32_MASK, VFMADD_VV }, // 1579 |
| 22850 | { PseudoVFMADD_VV_M1_E64, VFMADD_VV }, // 1580 |
| 22851 | { PseudoVFMADD_VV_M1_E64_MASK, VFMADD_VV }, // 1581 |
| 22852 | { PseudoVFMADD_VV_M2_E16, VFMADD_VV }, // 1582 |
| 22853 | { PseudoVFMADD_VV_M2_E16_MASK, VFMADD_VV }, // 1583 |
| 22854 | { PseudoVFMADD_VV_M2_E32, VFMADD_VV }, // 1584 |
| 22855 | { PseudoVFMADD_VV_M2_E32_MASK, VFMADD_VV }, // 1585 |
| 22856 | { PseudoVFMADD_VV_M2_E64, VFMADD_VV }, // 1586 |
| 22857 | { PseudoVFMADD_VV_M2_E64_MASK, VFMADD_VV }, // 1587 |
| 22858 | { PseudoVFMADD_VV_M4_E16, VFMADD_VV }, // 1588 |
| 22859 | { PseudoVFMADD_VV_M4_E16_MASK, VFMADD_VV }, // 1589 |
| 22860 | { PseudoVFMADD_VV_M4_E32, VFMADD_VV }, // 1590 |
| 22861 | { PseudoVFMADD_VV_M4_E32_MASK, VFMADD_VV }, // 1591 |
| 22862 | { PseudoVFMADD_VV_M4_E64, VFMADD_VV }, // 1592 |
| 22863 | { PseudoVFMADD_VV_M4_E64_MASK, VFMADD_VV }, // 1593 |
| 22864 | { PseudoVFMADD_VV_M8_E16, VFMADD_VV }, // 1594 |
| 22865 | { PseudoVFMADD_VV_M8_E16_MASK, VFMADD_VV }, // 1595 |
| 22866 | { PseudoVFMADD_VV_M8_E32, VFMADD_VV }, // 1596 |
| 22867 | { PseudoVFMADD_VV_M8_E32_MASK, VFMADD_VV }, // 1597 |
| 22868 | { PseudoVFMADD_VV_M8_E64, VFMADD_VV }, // 1598 |
| 22869 | { PseudoVFMADD_VV_M8_E64_MASK, VFMADD_VV }, // 1599 |
| 22870 | { PseudoVFMADD_VV_MF2_E16, VFMADD_VV }, // 1600 |
| 22871 | { PseudoVFMADD_VV_MF2_E16_MASK, VFMADD_VV }, // 1601 |
| 22872 | { PseudoVFMADD_VV_MF2_E32, VFMADD_VV }, // 1602 |
| 22873 | { PseudoVFMADD_VV_MF2_E32_MASK, VFMADD_VV }, // 1603 |
| 22874 | { PseudoVFMADD_VV_MF4_E16, VFMADD_VV }, // 1604 |
| 22875 | { PseudoVFMADD_VV_MF4_E16_MASK, VFMADD_VV }, // 1605 |
| 22876 | { PseudoVFMAX_VFPR16_M1_E16, VFMAX_VF }, // 1606 |
| 22877 | { PseudoVFMAX_VFPR16_M1_E16_MASK, VFMAX_VF }, // 1607 |
| 22878 | { PseudoVFMAX_VFPR16_M2_E16, VFMAX_VF }, // 1608 |
| 22879 | { PseudoVFMAX_VFPR16_M2_E16_MASK, VFMAX_VF }, // 1609 |
| 22880 | { PseudoVFMAX_VFPR16_M4_E16, VFMAX_VF }, // 1610 |
| 22881 | { PseudoVFMAX_VFPR16_M4_E16_MASK, VFMAX_VF }, // 1611 |
| 22882 | { PseudoVFMAX_VFPR16_M8_E16, VFMAX_VF }, // 1612 |
| 22883 | { PseudoVFMAX_VFPR16_M8_E16_MASK, VFMAX_VF }, // 1613 |
| 22884 | { PseudoVFMAX_VFPR16_MF2_E16, VFMAX_VF }, // 1614 |
| 22885 | { PseudoVFMAX_VFPR16_MF2_E16_MASK, VFMAX_VF }, // 1615 |
| 22886 | { PseudoVFMAX_VFPR16_MF4_E16, VFMAX_VF }, // 1616 |
| 22887 | { PseudoVFMAX_VFPR16_MF4_E16_MASK, VFMAX_VF }, // 1617 |
| 22888 | { PseudoVFMAX_VFPR32_M1_E32, VFMAX_VF }, // 1618 |
| 22889 | { PseudoVFMAX_VFPR32_M1_E32_MASK, VFMAX_VF }, // 1619 |
| 22890 | { PseudoVFMAX_VFPR32_M2_E32, VFMAX_VF }, // 1620 |
| 22891 | { PseudoVFMAX_VFPR32_M2_E32_MASK, VFMAX_VF }, // 1621 |
| 22892 | { PseudoVFMAX_VFPR32_M4_E32, VFMAX_VF }, // 1622 |
| 22893 | { PseudoVFMAX_VFPR32_M4_E32_MASK, VFMAX_VF }, // 1623 |
| 22894 | { PseudoVFMAX_VFPR32_M8_E32, VFMAX_VF }, // 1624 |
| 22895 | { PseudoVFMAX_VFPR32_M8_E32_MASK, VFMAX_VF }, // 1625 |
| 22896 | { PseudoVFMAX_VFPR32_MF2_E32, VFMAX_VF }, // 1626 |
| 22897 | { PseudoVFMAX_VFPR32_MF2_E32_MASK, VFMAX_VF }, // 1627 |
| 22898 | { PseudoVFMAX_VFPR64_M1_E64, VFMAX_VF }, // 1628 |
| 22899 | { PseudoVFMAX_VFPR64_M1_E64_MASK, VFMAX_VF }, // 1629 |
| 22900 | { PseudoVFMAX_VFPR64_M2_E64, VFMAX_VF }, // 1630 |
| 22901 | { PseudoVFMAX_VFPR64_M2_E64_MASK, VFMAX_VF }, // 1631 |
| 22902 | { PseudoVFMAX_VFPR64_M4_E64, VFMAX_VF }, // 1632 |
| 22903 | { PseudoVFMAX_VFPR64_M4_E64_MASK, VFMAX_VF }, // 1633 |
| 22904 | { PseudoVFMAX_VFPR64_M8_E64, VFMAX_VF }, // 1634 |
| 22905 | { PseudoVFMAX_VFPR64_M8_E64_MASK, VFMAX_VF }, // 1635 |
| 22906 | { PseudoVFMAX_VV_M1_E16, VFMAX_VV }, // 1636 |
| 22907 | { PseudoVFMAX_VV_M1_E16_MASK, VFMAX_VV }, // 1637 |
| 22908 | { PseudoVFMAX_VV_M1_E32, VFMAX_VV }, // 1638 |
| 22909 | { PseudoVFMAX_VV_M1_E32_MASK, VFMAX_VV }, // 1639 |
| 22910 | { PseudoVFMAX_VV_M1_E64, VFMAX_VV }, // 1640 |
| 22911 | { PseudoVFMAX_VV_M1_E64_MASK, VFMAX_VV }, // 1641 |
| 22912 | { PseudoVFMAX_VV_M2_E16, VFMAX_VV }, // 1642 |
| 22913 | { PseudoVFMAX_VV_M2_E16_MASK, VFMAX_VV }, // 1643 |
| 22914 | { PseudoVFMAX_VV_M2_E32, VFMAX_VV }, // 1644 |
| 22915 | { PseudoVFMAX_VV_M2_E32_MASK, VFMAX_VV }, // 1645 |
| 22916 | { PseudoVFMAX_VV_M2_E64, VFMAX_VV }, // 1646 |
| 22917 | { PseudoVFMAX_VV_M2_E64_MASK, VFMAX_VV }, // 1647 |
| 22918 | { PseudoVFMAX_VV_M4_E16, VFMAX_VV }, // 1648 |
| 22919 | { PseudoVFMAX_VV_M4_E16_MASK, VFMAX_VV }, // 1649 |
| 22920 | { PseudoVFMAX_VV_M4_E32, VFMAX_VV }, // 1650 |
| 22921 | { PseudoVFMAX_VV_M4_E32_MASK, VFMAX_VV }, // 1651 |
| 22922 | { PseudoVFMAX_VV_M4_E64, VFMAX_VV }, // 1652 |
| 22923 | { PseudoVFMAX_VV_M4_E64_MASK, VFMAX_VV }, // 1653 |
| 22924 | { PseudoVFMAX_VV_M8_E16, VFMAX_VV }, // 1654 |
| 22925 | { PseudoVFMAX_VV_M8_E16_MASK, VFMAX_VV }, // 1655 |
| 22926 | { PseudoVFMAX_VV_M8_E32, VFMAX_VV }, // 1656 |
| 22927 | { PseudoVFMAX_VV_M8_E32_MASK, VFMAX_VV }, // 1657 |
| 22928 | { PseudoVFMAX_VV_M8_E64, VFMAX_VV }, // 1658 |
| 22929 | { PseudoVFMAX_VV_M8_E64_MASK, VFMAX_VV }, // 1659 |
| 22930 | { PseudoVFMAX_VV_MF2_E16, VFMAX_VV }, // 1660 |
| 22931 | { PseudoVFMAX_VV_MF2_E16_MASK, VFMAX_VV }, // 1661 |
| 22932 | { PseudoVFMAX_VV_MF2_E32, VFMAX_VV }, // 1662 |
| 22933 | { PseudoVFMAX_VV_MF2_E32_MASK, VFMAX_VV }, // 1663 |
| 22934 | { PseudoVFMAX_VV_MF4_E16, VFMAX_VV }, // 1664 |
| 22935 | { PseudoVFMAX_VV_MF4_E16_MASK, VFMAX_VV }, // 1665 |
| 22936 | { PseudoVFMERGE_VFPR16M_M1, VFMERGE_VFM }, // 1666 |
| 22937 | { PseudoVFMERGE_VFPR16M_M2, VFMERGE_VFM }, // 1667 |
| 22938 | { PseudoVFMERGE_VFPR16M_M4, VFMERGE_VFM }, // 1668 |
| 22939 | { PseudoVFMERGE_VFPR16M_M8, VFMERGE_VFM }, // 1669 |
| 22940 | { PseudoVFMERGE_VFPR16M_MF2, VFMERGE_VFM }, // 1670 |
| 22941 | { PseudoVFMERGE_VFPR16M_MF4, VFMERGE_VFM }, // 1671 |
| 22942 | { PseudoVFMERGE_VFPR32M_M1, VFMERGE_VFM }, // 1672 |
| 22943 | { PseudoVFMERGE_VFPR32M_M2, VFMERGE_VFM }, // 1673 |
| 22944 | { PseudoVFMERGE_VFPR32M_M4, VFMERGE_VFM }, // 1674 |
| 22945 | { PseudoVFMERGE_VFPR32M_M8, VFMERGE_VFM }, // 1675 |
| 22946 | { PseudoVFMERGE_VFPR32M_MF2, VFMERGE_VFM }, // 1676 |
| 22947 | { PseudoVFMERGE_VFPR64M_M1, VFMERGE_VFM }, // 1677 |
| 22948 | { PseudoVFMERGE_VFPR64M_M2, VFMERGE_VFM }, // 1678 |
| 22949 | { PseudoVFMERGE_VFPR64M_M4, VFMERGE_VFM }, // 1679 |
| 22950 | { PseudoVFMERGE_VFPR64M_M8, VFMERGE_VFM }, // 1680 |
| 22951 | { PseudoVFMIN_VFPR16_M1_E16, VFMIN_VF }, // 1681 |
| 22952 | { PseudoVFMIN_VFPR16_M1_E16_MASK, VFMIN_VF }, // 1682 |
| 22953 | { PseudoVFMIN_VFPR16_M2_E16, VFMIN_VF }, // 1683 |
| 22954 | { PseudoVFMIN_VFPR16_M2_E16_MASK, VFMIN_VF }, // 1684 |
| 22955 | { PseudoVFMIN_VFPR16_M4_E16, VFMIN_VF }, // 1685 |
| 22956 | { PseudoVFMIN_VFPR16_M4_E16_MASK, VFMIN_VF }, // 1686 |
| 22957 | { PseudoVFMIN_VFPR16_M8_E16, VFMIN_VF }, // 1687 |
| 22958 | { PseudoVFMIN_VFPR16_M8_E16_MASK, VFMIN_VF }, // 1688 |
| 22959 | { PseudoVFMIN_VFPR16_MF2_E16, VFMIN_VF }, // 1689 |
| 22960 | { PseudoVFMIN_VFPR16_MF2_E16_MASK, VFMIN_VF }, // 1690 |
| 22961 | { PseudoVFMIN_VFPR16_MF4_E16, VFMIN_VF }, // 1691 |
| 22962 | { PseudoVFMIN_VFPR16_MF4_E16_MASK, VFMIN_VF }, // 1692 |
| 22963 | { PseudoVFMIN_VFPR32_M1_E32, VFMIN_VF }, // 1693 |
| 22964 | { PseudoVFMIN_VFPR32_M1_E32_MASK, VFMIN_VF }, // 1694 |
| 22965 | { PseudoVFMIN_VFPR32_M2_E32, VFMIN_VF }, // 1695 |
| 22966 | { PseudoVFMIN_VFPR32_M2_E32_MASK, VFMIN_VF }, // 1696 |
| 22967 | { PseudoVFMIN_VFPR32_M4_E32, VFMIN_VF }, // 1697 |
| 22968 | { PseudoVFMIN_VFPR32_M4_E32_MASK, VFMIN_VF }, // 1698 |
| 22969 | { PseudoVFMIN_VFPR32_M8_E32, VFMIN_VF }, // 1699 |
| 22970 | { PseudoVFMIN_VFPR32_M8_E32_MASK, VFMIN_VF }, // 1700 |
| 22971 | { PseudoVFMIN_VFPR32_MF2_E32, VFMIN_VF }, // 1701 |
| 22972 | { PseudoVFMIN_VFPR32_MF2_E32_MASK, VFMIN_VF }, // 1702 |
| 22973 | { PseudoVFMIN_VFPR64_M1_E64, VFMIN_VF }, // 1703 |
| 22974 | { PseudoVFMIN_VFPR64_M1_E64_MASK, VFMIN_VF }, // 1704 |
| 22975 | { PseudoVFMIN_VFPR64_M2_E64, VFMIN_VF }, // 1705 |
| 22976 | { PseudoVFMIN_VFPR64_M2_E64_MASK, VFMIN_VF }, // 1706 |
| 22977 | { PseudoVFMIN_VFPR64_M4_E64, VFMIN_VF }, // 1707 |
| 22978 | { PseudoVFMIN_VFPR64_M4_E64_MASK, VFMIN_VF }, // 1708 |
| 22979 | { PseudoVFMIN_VFPR64_M8_E64, VFMIN_VF }, // 1709 |
| 22980 | { PseudoVFMIN_VFPR64_M8_E64_MASK, VFMIN_VF }, // 1710 |
| 22981 | { PseudoVFMIN_VV_M1_E16, VFMIN_VV }, // 1711 |
| 22982 | { PseudoVFMIN_VV_M1_E16_MASK, VFMIN_VV }, // 1712 |
| 22983 | { PseudoVFMIN_VV_M1_E32, VFMIN_VV }, // 1713 |
| 22984 | { PseudoVFMIN_VV_M1_E32_MASK, VFMIN_VV }, // 1714 |
| 22985 | { PseudoVFMIN_VV_M1_E64, VFMIN_VV }, // 1715 |
| 22986 | { PseudoVFMIN_VV_M1_E64_MASK, VFMIN_VV }, // 1716 |
| 22987 | { PseudoVFMIN_VV_M2_E16, VFMIN_VV }, // 1717 |
| 22988 | { PseudoVFMIN_VV_M2_E16_MASK, VFMIN_VV }, // 1718 |
| 22989 | { PseudoVFMIN_VV_M2_E32, VFMIN_VV }, // 1719 |
| 22990 | { PseudoVFMIN_VV_M2_E32_MASK, VFMIN_VV }, // 1720 |
| 22991 | { PseudoVFMIN_VV_M2_E64, VFMIN_VV }, // 1721 |
| 22992 | { PseudoVFMIN_VV_M2_E64_MASK, VFMIN_VV }, // 1722 |
| 22993 | { PseudoVFMIN_VV_M4_E16, VFMIN_VV }, // 1723 |
| 22994 | { PseudoVFMIN_VV_M4_E16_MASK, VFMIN_VV }, // 1724 |
| 22995 | { PseudoVFMIN_VV_M4_E32, VFMIN_VV }, // 1725 |
| 22996 | { PseudoVFMIN_VV_M4_E32_MASK, VFMIN_VV }, // 1726 |
| 22997 | { PseudoVFMIN_VV_M4_E64, VFMIN_VV }, // 1727 |
| 22998 | { PseudoVFMIN_VV_M4_E64_MASK, VFMIN_VV }, // 1728 |
| 22999 | { PseudoVFMIN_VV_M8_E16, VFMIN_VV }, // 1729 |
| 23000 | { PseudoVFMIN_VV_M8_E16_MASK, VFMIN_VV }, // 1730 |
| 23001 | { PseudoVFMIN_VV_M8_E32, VFMIN_VV }, // 1731 |
| 23002 | { PseudoVFMIN_VV_M8_E32_MASK, VFMIN_VV }, // 1732 |
| 23003 | { PseudoVFMIN_VV_M8_E64, VFMIN_VV }, // 1733 |
| 23004 | { PseudoVFMIN_VV_M8_E64_MASK, VFMIN_VV }, // 1734 |
| 23005 | { PseudoVFMIN_VV_MF2_E16, VFMIN_VV }, // 1735 |
| 23006 | { PseudoVFMIN_VV_MF2_E16_MASK, VFMIN_VV }, // 1736 |
| 23007 | { PseudoVFMIN_VV_MF2_E32, VFMIN_VV }, // 1737 |
| 23008 | { PseudoVFMIN_VV_MF2_E32_MASK, VFMIN_VV }, // 1738 |
| 23009 | { PseudoVFMIN_VV_MF4_E16, VFMIN_VV }, // 1739 |
| 23010 | { PseudoVFMIN_VV_MF4_E16_MASK, VFMIN_VV }, // 1740 |
| 23011 | { PseudoVFMSAC_VFPR16_M1_E16, VFMSAC_VF }, // 1741 |
| 23012 | { PseudoVFMSAC_VFPR16_M1_E16_MASK, VFMSAC_VF }, // 1742 |
| 23013 | { PseudoVFMSAC_VFPR16_M2_E16, VFMSAC_VF }, // 1743 |
| 23014 | { PseudoVFMSAC_VFPR16_M2_E16_MASK, VFMSAC_VF }, // 1744 |
| 23015 | { PseudoVFMSAC_VFPR16_M4_E16, VFMSAC_VF }, // 1745 |
| 23016 | { PseudoVFMSAC_VFPR16_M4_E16_MASK, VFMSAC_VF }, // 1746 |
| 23017 | { PseudoVFMSAC_VFPR16_M8_E16, VFMSAC_VF }, // 1747 |
| 23018 | { PseudoVFMSAC_VFPR16_M8_E16_MASK, VFMSAC_VF }, // 1748 |
| 23019 | { PseudoVFMSAC_VFPR16_MF2_E16, VFMSAC_VF }, // 1749 |
| 23020 | { PseudoVFMSAC_VFPR16_MF2_E16_MASK, VFMSAC_VF }, // 1750 |
| 23021 | { PseudoVFMSAC_VFPR16_MF4_E16, VFMSAC_VF }, // 1751 |
| 23022 | { PseudoVFMSAC_VFPR16_MF4_E16_MASK, VFMSAC_VF }, // 1752 |
| 23023 | { PseudoVFMSAC_VFPR32_M1_E32, VFMSAC_VF }, // 1753 |
| 23024 | { PseudoVFMSAC_VFPR32_M1_E32_MASK, VFMSAC_VF }, // 1754 |
| 23025 | { PseudoVFMSAC_VFPR32_M2_E32, VFMSAC_VF }, // 1755 |
| 23026 | { PseudoVFMSAC_VFPR32_M2_E32_MASK, VFMSAC_VF }, // 1756 |
| 23027 | { PseudoVFMSAC_VFPR32_M4_E32, VFMSAC_VF }, // 1757 |
| 23028 | { PseudoVFMSAC_VFPR32_M4_E32_MASK, VFMSAC_VF }, // 1758 |
| 23029 | { PseudoVFMSAC_VFPR32_M8_E32, VFMSAC_VF }, // 1759 |
| 23030 | { PseudoVFMSAC_VFPR32_M8_E32_MASK, VFMSAC_VF }, // 1760 |
| 23031 | { PseudoVFMSAC_VFPR32_MF2_E32, VFMSAC_VF }, // 1761 |
| 23032 | { PseudoVFMSAC_VFPR32_MF2_E32_MASK, VFMSAC_VF }, // 1762 |
| 23033 | { PseudoVFMSAC_VFPR64_M1_E64, VFMSAC_VF }, // 1763 |
| 23034 | { PseudoVFMSAC_VFPR64_M1_E64_MASK, VFMSAC_VF }, // 1764 |
| 23035 | { PseudoVFMSAC_VFPR64_M2_E64, VFMSAC_VF }, // 1765 |
| 23036 | { PseudoVFMSAC_VFPR64_M2_E64_MASK, VFMSAC_VF }, // 1766 |
| 23037 | { PseudoVFMSAC_VFPR64_M4_E64, VFMSAC_VF }, // 1767 |
| 23038 | { PseudoVFMSAC_VFPR64_M4_E64_MASK, VFMSAC_VF }, // 1768 |
| 23039 | { PseudoVFMSAC_VFPR64_M8_E64, VFMSAC_VF }, // 1769 |
| 23040 | { PseudoVFMSAC_VFPR64_M8_E64_MASK, VFMSAC_VF }, // 1770 |
| 23041 | { PseudoVFMSAC_VV_M1_E16, VFMSAC_VV }, // 1771 |
| 23042 | { PseudoVFMSAC_VV_M1_E16_MASK, VFMSAC_VV }, // 1772 |
| 23043 | { PseudoVFMSAC_VV_M1_E32, VFMSAC_VV }, // 1773 |
| 23044 | { PseudoVFMSAC_VV_M1_E32_MASK, VFMSAC_VV }, // 1774 |
| 23045 | { PseudoVFMSAC_VV_M1_E64, VFMSAC_VV }, // 1775 |
| 23046 | { PseudoVFMSAC_VV_M1_E64_MASK, VFMSAC_VV }, // 1776 |
| 23047 | { PseudoVFMSAC_VV_M2_E16, VFMSAC_VV }, // 1777 |
| 23048 | { PseudoVFMSAC_VV_M2_E16_MASK, VFMSAC_VV }, // 1778 |
| 23049 | { PseudoVFMSAC_VV_M2_E32, VFMSAC_VV }, // 1779 |
| 23050 | { PseudoVFMSAC_VV_M2_E32_MASK, VFMSAC_VV }, // 1780 |
| 23051 | { PseudoVFMSAC_VV_M2_E64, VFMSAC_VV }, // 1781 |
| 23052 | { PseudoVFMSAC_VV_M2_E64_MASK, VFMSAC_VV }, // 1782 |
| 23053 | { PseudoVFMSAC_VV_M4_E16, VFMSAC_VV }, // 1783 |
| 23054 | { PseudoVFMSAC_VV_M4_E16_MASK, VFMSAC_VV }, // 1784 |
| 23055 | { PseudoVFMSAC_VV_M4_E32, VFMSAC_VV }, // 1785 |
| 23056 | { PseudoVFMSAC_VV_M4_E32_MASK, VFMSAC_VV }, // 1786 |
| 23057 | { PseudoVFMSAC_VV_M4_E64, VFMSAC_VV }, // 1787 |
| 23058 | { PseudoVFMSAC_VV_M4_E64_MASK, VFMSAC_VV }, // 1788 |
| 23059 | { PseudoVFMSAC_VV_M8_E16, VFMSAC_VV }, // 1789 |
| 23060 | { PseudoVFMSAC_VV_M8_E16_MASK, VFMSAC_VV }, // 1790 |
| 23061 | { PseudoVFMSAC_VV_M8_E32, VFMSAC_VV }, // 1791 |
| 23062 | { PseudoVFMSAC_VV_M8_E32_MASK, VFMSAC_VV }, // 1792 |
| 23063 | { PseudoVFMSAC_VV_M8_E64, VFMSAC_VV }, // 1793 |
| 23064 | { PseudoVFMSAC_VV_M8_E64_MASK, VFMSAC_VV }, // 1794 |
| 23065 | { PseudoVFMSAC_VV_MF2_E16, VFMSAC_VV }, // 1795 |
| 23066 | { PseudoVFMSAC_VV_MF2_E16_MASK, VFMSAC_VV }, // 1796 |
| 23067 | { PseudoVFMSAC_VV_MF2_E32, VFMSAC_VV }, // 1797 |
| 23068 | { PseudoVFMSAC_VV_MF2_E32_MASK, VFMSAC_VV }, // 1798 |
| 23069 | { PseudoVFMSAC_VV_MF4_E16, VFMSAC_VV }, // 1799 |
| 23070 | { PseudoVFMSAC_VV_MF4_E16_MASK, VFMSAC_VV }, // 1800 |
| 23071 | { PseudoVFMSUB_VFPR16_M1_E16, VFMSUB_VF }, // 1801 |
| 23072 | { PseudoVFMSUB_VFPR16_M1_E16_MASK, VFMSUB_VF }, // 1802 |
| 23073 | { PseudoVFMSUB_VFPR16_M2_E16, VFMSUB_VF }, // 1803 |
| 23074 | { PseudoVFMSUB_VFPR16_M2_E16_MASK, VFMSUB_VF }, // 1804 |
| 23075 | { PseudoVFMSUB_VFPR16_M4_E16, VFMSUB_VF }, // 1805 |
| 23076 | { PseudoVFMSUB_VFPR16_M4_E16_MASK, VFMSUB_VF }, // 1806 |
| 23077 | { PseudoVFMSUB_VFPR16_M8_E16, VFMSUB_VF }, // 1807 |
| 23078 | { PseudoVFMSUB_VFPR16_M8_E16_MASK, VFMSUB_VF }, // 1808 |
| 23079 | { PseudoVFMSUB_VFPR16_MF2_E16, VFMSUB_VF }, // 1809 |
| 23080 | { PseudoVFMSUB_VFPR16_MF2_E16_MASK, VFMSUB_VF }, // 1810 |
| 23081 | { PseudoVFMSUB_VFPR16_MF4_E16, VFMSUB_VF }, // 1811 |
| 23082 | { PseudoVFMSUB_VFPR16_MF4_E16_MASK, VFMSUB_VF }, // 1812 |
| 23083 | { PseudoVFMSUB_VFPR32_M1_E32, VFMSUB_VF }, // 1813 |
| 23084 | { PseudoVFMSUB_VFPR32_M1_E32_MASK, VFMSUB_VF }, // 1814 |
| 23085 | { PseudoVFMSUB_VFPR32_M2_E32, VFMSUB_VF }, // 1815 |
| 23086 | { PseudoVFMSUB_VFPR32_M2_E32_MASK, VFMSUB_VF }, // 1816 |
| 23087 | { PseudoVFMSUB_VFPR32_M4_E32, VFMSUB_VF }, // 1817 |
| 23088 | { PseudoVFMSUB_VFPR32_M4_E32_MASK, VFMSUB_VF }, // 1818 |
| 23089 | { PseudoVFMSUB_VFPR32_M8_E32, VFMSUB_VF }, // 1819 |
| 23090 | { PseudoVFMSUB_VFPR32_M8_E32_MASK, VFMSUB_VF }, // 1820 |
| 23091 | { PseudoVFMSUB_VFPR32_MF2_E32, VFMSUB_VF }, // 1821 |
| 23092 | { PseudoVFMSUB_VFPR32_MF2_E32_MASK, VFMSUB_VF }, // 1822 |
| 23093 | { PseudoVFMSUB_VFPR64_M1_E64, VFMSUB_VF }, // 1823 |
| 23094 | { PseudoVFMSUB_VFPR64_M1_E64_MASK, VFMSUB_VF }, // 1824 |
| 23095 | { PseudoVFMSUB_VFPR64_M2_E64, VFMSUB_VF }, // 1825 |
| 23096 | { PseudoVFMSUB_VFPR64_M2_E64_MASK, VFMSUB_VF }, // 1826 |
| 23097 | { PseudoVFMSUB_VFPR64_M4_E64, VFMSUB_VF }, // 1827 |
| 23098 | { PseudoVFMSUB_VFPR64_M4_E64_MASK, VFMSUB_VF }, // 1828 |
| 23099 | { PseudoVFMSUB_VFPR64_M8_E64, VFMSUB_VF }, // 1829 |
| 23100 | { PseudoVFMSUB_VFPR64_M8_E64_MASK, VFMSUB_VF }, // 1830 |
| 23101 | { PseudoVFMSUB_VV_M1_E16, VFMSUB_VV }, // 1831 |
| 23102 | { PseudoVFMSUB_VV_M1_E16_MASK, VFMSUB_VV }, // 1832 |
| 23103 | { PseudoVFMSUB_VV_M1_E32, VFMSUB_VV }, // 1833 |
| 23104 | { PseudoVFMSUB_VV_M1_E32_MASK, VFMSUB_VV }, // 1834 |
| 23105 | { PseudoVFMSUB_VV_M1_E64, VFMSUB_VV }, // 1835 |
| 23106 | { PseudoVFMSUB_VV_M1_E64_MASK, VFMSUB_VV }, // 1836 |
| 23107 | { PseudoVFMSUB_VV_M2_E16, VFMSUB_VV }, // 1837 |
| 23108 | { PseudoVFMSUB_VV_M2_E16_MASK, VFMSUB_VV }, // 1838 |
| 23109 | { PseudoVFMSUB_VV_M2_E32, VFMSUB_VV }, // 1839 |
| 23110 | { PseudoVFMSUB_VV_M2_E32_MASK, VFMSUB_VV }, // 1840 |
| 23111 | { PseudoVFMSUB_VV_M2_E64, VFMSUB_VV }, // 1841 |
| 23112 | { PseudoVFMSUB_VV_M2_E64_MASK, VFMSUB_VV }, // 1842 |
| 23113 | { PseudoVFMSUB_VV_M4_E16, VFMSUB_VV }, // 1843 |
| 23114 | { PseudoVFMSUB_VV_M4_E16_MASK, VFMSUB_VV }, // 1844 |
| 23115 | { PseudoVFMSUB_VV_M4_E32, VFMSUB_VV }, // 1845 |
| 23116 | { PseudoVFMSUB_VV_M4_E32_MASK, VFMSUB_VV }, // 1846 |
| 23117 | { PseudoVFMSUB_VV_M4_E64, VFMSUB_VV }, // 1847 |
| 23118 | { PseudoVFMSUB_VV_M4_E64_MASK, VFMSUB_VV }, // 1848 |
| 23119 | { PseudoVFMSUB_VV_M8_E16, VFMSUB_VV }, // 1849 |
| 23120 | { PseudoVFMSUB_VV_M8_E16_MASK, VFMSUB_VV }, // 1850 |
| 23121 | { PseudoVFMSUB_VV_M8_E32, VFMSUB_VV }, // 1851 |
| 23122 | { PseudoVFMSUB_VV_M8_E32_MASK, VFMSUB_VV }, // 1852 |
| 23123 | { PseudoVFMSUB_VV_M8_E64, VFMSUB_VV }, // 1853 |
| 23124 | { PseudoVFMSUB_VV_M8_E64_MASK, VFMSUB_VV }, // 1854 |
| 23125 | { PseudoVFMSUB_VV_MF2_E16, VFMSUB_VV }, // 1855 |
| 23126 | { PseudoVFMSUB_VV_MF2_E16_MASK, VFMSUB_VV }, // 1856 |
| 23127 | { PseudoVFMSUB_VV_MF2_E32, VFMSUB_VV }, // 1857 |
| 23128 | { PseudoVFMSUB_VV_MF2_E32_MASK, VFMSUB_VV }, // 1858 |
| 23129 | { PseudoVFMSUB_VV_MF4_E16, VFMSUB_VV }, // 1859 |
| 23130 | { PseudoVFMSUB_VV_MF4_E16_MASK, VFMSUB_VV }, // 1860 |
| 23131 | { PseudoVFMUL_VFPR16_M1_E16, VFMUL_VF }, // 1861 |
| 23132 | { PseudoVFMUL_VFPR16_M1_E16_MASK, VFMUL_VF }, // 1862 |
| 23133 | { PseudoVFMUL_VFPR16_M2_E16, VFMUL_VF }, // 1863 |
| 23134 | { PseudoVFMUL_VFPR16_M2_E16_MASK, VFMUL_VF }, // 1864 |
| 23135 | { PseudoVFMUL_VFPR16_M4_E16, VFMUL_VF }, // 1865 |
| 23136 | { PseudoVFMUL_VFPR16_M4_E16_MASK, VFMUL_VF }, // 1866 |
| 23137 | { PseudoVFMUL_VFPR16_M8_E16, VFMUL_VF }, // 1867 |
| 23138 | { PseudoVFMUL_VFPR16_M8_E16_MASK, VFMUL_VF }, // 1868 |
| 23139 | { PseudoVFMUL_VFPR16_MF2_E16, VFMUL_VF }, // 1869 |
| 23140 | { PseudoVFMUL_VFPR16_MF2_E16_MASK, VFMUL_VF }, // 1870 |
| 23141 | { PseudoVFMUL_VFPR16_MF4_E16, VFMUL_VF }, // 1871 |
| 23142 | { PseudoVFMUL_VFPR16_MF4_E16_MASK, VFMUL_VF }, // 1872 |
| 23143 | { PseudoVFMUL_VFPR32_M1_E32, VFMUL_VF }, // 1873 |
| 23144 | { PseudoVFMUL_VFPR32_M1_E32_MASK, VFMUL_VF }, // 1874 |
| 23145 | { PseudoVFMUL_VFPR32_M2_E32, VFMUL_VF }, // 1875 |
| 23146 | { PseudoVFMUL_VFPR32_M2_E32_MASK, VFMUL_VF }, // 1876 |
| 23147 | { PseudoVFMUL_VFPR32_M4_E32, VFMUL_VF }, // 1877 |
| 23148 | { PseudoVFMUL_VFPR32_M4_E32_MASK, VFMUL_VF }, // 1878 |
| 23149 | { PseudoVFMUL_VFPR32_M8_E32, VFMUL_VF }, // 1879 |
| 23150 | { PseudoVFMUL_VFPR32_M8_E32_MASK, VFMUL_VF }, // 1880 |
| 23151 | { PseudoVFMUL_VFPR32_MF2_E32, VFMUL_VF }, // 1881 |
| 23152 | { PseudoVFMUL_VFPR32_MF2_E32_MASK, VFMUL_VF }, // 1882 |
| 23153 | { PseudoVFMUL_VFPR64_M1_E64, VFMUL_VF }, // 1883 |
| 23154 | { PseudoVFMUL_VFPR64_M1_E64_MASK, VFMUL_VF }, // 1884 |
| 23155 | { PseudoVFMUL_VFPR64_M2_E64, VFMUL_VF }, // 1885 |
| 23156 | { PseudoVFMUL_VFPR64_M2_E64_MASK, VFMUL_VF }, // 1886 |
| 23157 | { PseudoVFMUL_VFPR64_M4_E64, VFMUL_VF }, // 1887 |
| 23158 | { PseudoVFMUL_VFPR64_M4_E64_MASK, VFMUL_VF }, // 1888 |
| 23159 | { PseudoVFMUL_VFPR64_M8_E64, VFMUL_VF }, // 1889 |
| 23160 | { PseudoVFMUL_VFPR64_M8_E64_MASK, VFMUL_VF }, // 1890 |
| 23161 | { PseudoVFMUL_VV_M1_E16, VFMUL_VV }, // 1891 |
| 23162 | { PseudoVFMUL_VV_M1_E16_MASK, VFMUL_VV }, // 1892 |
| 23163 | { PseudoVFMUL_VV_M1_E32, VFMUL_VV }, // 1893 |
| 23164 | { PseudoVFMUL_VV_M1_E32_MASK, VFMUL_VV }, // 1894 |
| 23165 | { PseudoVFMUL_VV_M1_E64, VFMUL_VV }, // 1895 |
| 23166 | { PseudoVFMUL_VV_M1_E64_MASK, VFMUL_VV }, // 1896 |
| 23167 | { PseudoVFMUL_VV_M2_E16, VFMUL_VV }, // 1897 |
| 23168 | { PseudoVFMUL_VV_M2_E16_MASK, VFMUL_VV }, // 1898 |
| 23169 | { PseudoVFMUL_VV_M2_E32, VFMUL_VV }, // 1899 |
| 23170 | { PseudoVFMUL_VV_M2_E32_MASK, VFMUL_VV }, // 1900 |
| 23171 | { PseudoVFMUL_VV_M2_E64, VFMUL_VV }, // 1901 |
| 23172 | { PseudoVFMUL_VV_M2_E64_MASK, VFMUL_VV }, // 1902 |
| 23173 | { PseudoVFMUL_VV_M4_E16, VFMUL_VV }, // 1903 |
| 23174 | { PseudoVFMUL_VV_M4_E16_MASK, VFMUL_VV }, // 1904 |
| 23175 | { PseudoVFMUL_VV_M4_E32, VFMUL_VV }, // 1905 |
| 23176 | { PseudoVFMUL_VV_M4_E32_MASK, VFMUL_VV }, // 1906 |
| 23177 | { PseudoVFMUL_VV_M4_E64, VFMUL_VV }, // 1907 |
| 23178 | { PseudoVFMUL_VV_M4_E64_MASK, VFMUL_VV }, // 1908 |
| 23179 | { PseudoVFMUL_VV_M8_E16, VFMUL_VV }, // 1909 |
| 23180 | { PseudoVFMUL_VV_M8_E16_MASK, VFMUL_VV }, // 1910 |
| 23181 | { PseudoVFMUL_VV_M8_E32, VFMUL_VV }, // 1911 |
| 23182 | { PseudoVFMUL_VV_M8_E32_MASK, VFMUL_VV }, // 1912 |
| 23183 | { PseudoVFMUL_VV_M8_E64, VFMUL_VV }, // 1913 |
| 23184 | { PseudoVFMUL_VV_M8_E64_MASK, VFMUL_VV }, // 1914 |
| 23185 | { PseudoVFMUL_VV_MF2_E16, VFMUL_VV }, // 1915 |
| 23186 | { PseudoVFMUL_VV_MF2_E16_MASK, VFMUL_VV }, // 1916 |
| 23187 | { PseudoVFMUL_VV_MF2_E32, VFMUL_VV }, // 1917 |
| 23188 | { PseudoVFMUL_VV_MF2_E32_MASK, VFMUL_VV }, // 1918 |
| 23189 | { PseudoVFMUL_VV_MF4_E16, VFMUL_VV }, // 1919 |
| 23190 | { PseudoVFMUL_VV_MF4_E16_MASK, VFMUL_VV }, // 1920 |
| 23191 | { PseudoVFMV_FPR16_S_M1, VFMV_F_S }, // 1921 |
| 23192 | { PseudoVFMV_FPR16_S_M2, VFMV_F_S }, // 1922 |
| 23193 | { PseudoVFMV_FPR16_S_M4, VFMV_F_S }, // 1923 |
| 23194 | { PseudoVFMV_FPR16_S_M8, VFMV_F_S }, // 1924 |
| 23195 | { PseudoVFMV_FPR16_S_MF2, VFMV_F_S }, // 1925 |
| 23196 | { PseudoVFMV_FPR16_S_MF4, VFMV_F_S }, // 1926 |
| 23197 | { PseudoVFMV_FPR32_S_M1, VFMV_F_S }, // 1927 |
| 23198 | { PseudoVFMV_FPR32_S_M2, VFMV_F_S }, // 1928 |
| 23199 | { PseudoVFMV_FPR32_S_M4, VFMV_F_S }, // 1929 |
| 23200 | { PseudoVFMV_FPR32_S_M8, VFMV_F_S }, // 1930 |
| 23201 | { PseudoVFMV_FPR32_S_MF2, VFMV_F_S }, // 1931 |
| 23202 | { PseudoVFMV_FPR64_S_M1, VFMV_F_S }, // 1932 |
| 23203 | { PseudoVFMV_FPR64_S_M2, VFMV_F_S }, // 1933 |
| 23204 | { PseudoVFMV_FPR64_S_M4, VFMV_F_S }, // 1934 |
| 23205 | { PseudoVFMV_FPR64_S_M8, VFMV_F_S }, // 1935 |
| 23206 | { PseudoVFMV_S_FPR16_M1, VFMV_S_F }, // 1936 |
| 23207 | { PseudoVFMV_S_FPR16_M2, VFMV_S_F }, // 1937 |
| 23208 | { PseudoVFMV_S_FPR16_M4, VFMV_S_F }, // 1938 |
| 23209 | { PseudoVFMV_S_FPR16_M8, VFMV_S_F }, // 1939 |
| 23210 | { PseudoVFMV_S_FPR16_MF2, VFMV_S_F }, // 1940 |
| 23211 | { PseudoVFMV_S_FPR16_MF4, VFMV_S_F }, // 1941 |
| 23212 | { PseudoVFMV_S_FPR32_M1, VFMV_S_F }, // 1942 |
| 23213 | { PseudoVFMV_S_FPR32_M2, VFMV_S_F }, // 1943 |
| 23214 | { PseudoVFMV_S_FPR32_M4, VFMV_S_F }, // 1944 |
| 23215 | { PseudoVFMV_S_FPR32_M8, VFMV_S_F }, // 1945 |
| 23216 | { PseudoVFMV_S_FPR32_MF2, VFMV_S_F }, // 1946 |
| 23217 | { PseudoVFMV_S_FPR64_M1, VFMV_S_F }, // 1947 |
| 23218 | { PseudoVFMV_S_FPR64_M2, VFMV_S_F }, // 1948 |
| 23219 | { PseudoVFMV_S_FPR64_M4, VFMV_S_F }, // 1949 |
| 23220 | { PseudoVFMV_S_FPR64_M8, VFMV_S_F }, // 1950 |
| 23221 | { PseudoVFMV_V_FPR16_M1, VFMV_V_F }, // 1951 |
| 23222 | { PseudoVFMV_V_FPR16_M2, VFMV_V_F }, // 1952 |
| 23223 | { PseudoVFMV_V_FPR16_M4, VFMV_V_F }, // 1953 |
| 23224 | { PseudoVFMV_V_FPR16_M8, VFMV_V_F }, // 1954 |
| 23225 | { PseudoVFMV_V_FPR16_MF2, VFMV_V_F }, // 1955 |
| 23226 | { PseudoVFMV_V_FPR16_MF4, VFMV_V_F }, // 1956 |
| 23227 | { PseudoVFMV_V_FPR32_M1, VFMV_V_F }, // 1957 |
| 23228 | { PseudoVFMV_V_FPR32_M2, VFMV_V_F }, // 1958 |
| 23229 | { PseudoVFMV_V_FPR32_M4, VFMV_V_F }, // 1959 |
| 23230 | { PseudoVFMV_V_FPR32_M8, VFMV_V_F }, // 1960 |
| 23231 | { PseudoVFMV_V_FPR32_MF2, VFMV_V_F }, // 1961 |
| 23232 | { PseudoVFMV_V_FPR64_M1, VFMV_V_F }, // 1962 |
| 23233 | { PseudoVFMV_V_FPR64_M2, VFMV_V_F }, // 1963 |
| 23234 | { PseudoVFMV_V_FPR64_M4, VFMV_V_F }, // 1964 |
| 23235 | { PseudoVFMV_V_FPR64_M8, VFMV_V_F }, // 1965 |
| 23236 | { PseudoVFNCVTBF16_F_F_W_M1_E16, VFNCVTBF16_F_F_W }, // 1966 |
| 23237 | { PseudoVFNCVTBF16_F_F_W_M1_E16_MASK, VFNCVTBF16_F_F_W }, // 1967 |
| 23238 | { PseudoVFNCVTBF16_F_F_W_M1_E32, VFNCVTBF16_F_F_W }, // 1968 |
| 23239 | { PseudoVFNCVTBF16_F_F_W_M1_E32_MASK, VFNCVTBF16_F_F_W }, // 1969 |
| 23240 | { PseudoVFNCVTBF16_F_F_W_M2_E16, VFNCVTBF16_F_F_W }, // 1970 |
| 23241 | { PseudoVFNCVTBF16_F_F_W_M2_E16_MASK, VFNCVTBF16_F_F_W }, // 1971 |
| 23242 | { PseudoVFNCVTBF16_F_F_W_M2_E32, VFNCVTBF16_F_F_W }, // 1972 |
| 23243 | { PseudoVFNCVTBF16_F_F_W_M2_E32_MASK, VFNCVTBF16_F_F_W }, // 1973 |
| 23244 | { PseudoVFNCVTBF16_F_F_W_M4_E16, VFNCVTBF16_F_F_W }, // 1974 |
| 23245 | { PseudoVFNCVTBF16_F_F_W_M4_E16_MASK, VFNCVTBF16_F_F_W }, // 1975 |
| 23246 | { PseudoVFNCVTBF16_F_F_W_M4_E32, VFNCVTBF16_F_F_W }, // 1976 |
| 23247 | { PseudoVFNCVTBF16_F_F_W_M4_E32_MASK, VFNCVTBF16_F_F_W }, // 1977 |
| 23248 | { PseudoVFNCVTBF16_F_F_W_MF2_E16, VFNCVTBF16_F_F_W }, // 1978 |
| 23249 | { PseudoVFNCVTBF16_F_F_W_MF2_E16_MASK, VFNCVTBF16_F_F_W }, // 1979 |
| 23250 | { PseudoVFNCVTBF16_F_F_W_MF2_E32, VFNCVTBF16_F_F_W }, // 1980 |
| 23251 | { PseudoVFNCVTBF16_F_F_W_MF2_E32_MASK, VFNCVTBF16_F_F_W }, // 1981 |
| 23252 | { PseudoVFNCVTBF16_F_F_W_MF4_E16, VFNCVTBF16_F_F_W }, // 1982 |
| 23253 | { PseudoVFNCVTBF16_F_F_W_MF4_E16_MASK, VFNCVTBF16_F_F_W }, // 1983 |
| 23254 | { PseudoVFNCVT_F_F_W_M1_E16, VFNCVT_F_F_W }, // 1984 |
| 23255 | { PseudoVFNCVT_F_F_W_M1_E16_MASK, VFNCVT_F_F_W }, // 1985 |
| 23256 | { PseudoVFNCVT_F_F_W_M1_E32, VFNCVT_F_F_W }, // 1986 |
| 23257 | { PseudoVFNCVT_F_F_W_M1_E32_MASK, VFNCVT_F_F_W }, // 1987 |
| 23258 | { PseudoVFNCVT_F_F_W_M2_E16, VFNCVT_F_F_W }, // 1988 |
| 23259 | { PseudoVFNCVT_F_F_W_M2_E16_MASK, VFNCVT_F_F_W }, // 1989 |
| 23260 | { PseudoVFNCVT_F_F_W_M2_E32, VFNCVT_F_F_W }, // 1990 |
| 23261 | { PseudoVFNCVT_F_F_W_M2_E32_MASK, VFNCVT_F_F_W }, // 1991 |
| 23262 | { PseudoVFNCVT_F_F_W_M4_E16, VFNCVT_F_F_W }, // 1992 |
| 23263 | { PseudoVFNCVT_F_F_W_M4_E16_MASK, VFNCVT_F_F_W }, // 1993 |
| 23264 | { PseudoVFNCVT_F_F_W_M4_E32, VFNCVT_F_F_W }, // 1994 |
| 23265 | { PseudoVFNCVT_F_F_W_M4_E32_MASK, VFNCVT_F_F_W }, // 1995 |
| 23266 | { PseudoVFNCVT_F_F_W_MF2_E16, VFNCVT_F_F_W }, // 1996 |
| 23267 | { PseudoVFNCVT_F_F_W_MF2_E16_MASK, VFNCVT_F_F_W }, // 1997 |
| 23268 | { PseudoVFNCVT_F_F_W_MF2_E32, VFNCVT_F_F_W }, // 1998 |
| 23269 | { PseudoVFNCVT_F_F_W_MF2_E32_MASK, VFNCVT_F_F_W }, // 1999 |
| 23270 | { PseudoVFNCVT_F_F_W_MF4_E16, VFNCVT_F_F_W }, // 2000 |
| 23271 | { PseudoVFNCVT_F_F_W_MF4_E16_MASK, VFNCVT_F_F_W }, // 2001 |
| 23272 | { PseudoVFNCVT_F_XU_W_M1_E16, VFNCVT_F_XU_W }, // 2002 |
| 23273 | { PseudoVFNCVT_F_XU_W_M1_E16_MASK, VFNCVT_F_XU_W }, // 2003 |
| 23274 | { PseudoVFNCVT_F_XU_W_M1_E32, VFNCVT_F_XU_W }, // 2004 |
| 23275 | { PseudoVFNCVT_F_XU_W_M1_E32_MASK, VFNCVT_F_XU_W }, // 2005 |
| 23276 | { PseudoVFNCVT_F_XU_W_M2_E16, VFNCVT_F_XU_W }, // 2006 |
| 23277 | { PseudoVFNCVT_F_XU_W_M2_E16_MASK, VFNCVT_F_XU_W }, // 2007 |
| 23278 | { PseudoVFNCVT_F_XU_W_M2_E32, VFNCVT_F_XU_W }, // 2008 |
| 23279 | { PseudoVFNCVT_F_XU_W_M2_E32_MASK, VFNCVT_F_XU_W }, // 2009 |
| 23280 | { PseudoVFNCVT_F_XU_W_M4_E16, VFNCVT_F_XU_W }, // 2010 |
| 23281 | { PseudoVFNCVT_F_XU_W_M4_E16_MASK, VFNCVT_F_XU_W }, // 2011 |
| 23282 | { PseudoVFNCVT_F_XU_W_M4_E32, VFNCVT_F_XU_W }, // 2012 |
| 23283 | { PseudoVFNCVT_F_XU_W_M4_E32_MASK, VFNCVT_F_XU_W }, // 2013 |
| 23284 | { PseudoVFNCVT_F_XU_W_MF2_E16, VFNCVT_F_XU_W }, // 2014 |
| 23285 | { PseudoVFNCVT_F_XU_W_MF2_E16_MASK, VFNCVT_F_XU_W }, // 2015 |
| 23286 | { PseudoVFNCVT_F_XU_W_MF2_E32, VFNCVT_F_XU_W }, // 2016 |
| 23287 | { PseudoVFNCVT_F_XU_W_MF2_E32_MASK, VFNCVT_F_XU_W }, // 2017 |
| 23288 | { PseudoVFNCVT_F_XU_W_MF4_E16, VFNCVT_F_XU_W }, // 2018 |
| 23289 | { PseudoVFNCVT_F_XU_W_MF4_E16_MASK, VFNCVT_F_XU_W }, // 2019 |
| 23290 | { PseudoVFNCVT_F_X_W_M1_E16, VFNCVT_F_X_W }, // 2020 |
| 23291 | { PseudoVFNCVT_F_X_W_M1_E16_MASK, VFNCVT_F_X_W }, // 2021 |
| 23292 | { PseudoVFNCVT_F_X_W_M1_E32, VFNCVT_F_X_W }, // 2022 |
| 23293 | { PseudoVFNCVT_F_X_W_M1_E32_MASK, VFNCVT_F_X_W }, // 2023 |
| 23294 | { PseudoVFNCVT_F_X_W_M2_E16, VFNCVT_F_X_W }, // 2024 |
| 23295 | { PseudoVFNCVT_F_X_W_M2_E16_MASK, VFNCVT_F_X_W }, // 2025 |
| 23296 | { PseudoVFNCVT_F_X_W_M2_E32, VFNCVT_F_X_W }, // 2026 |
| 23297 | { PseudoVFNCVT_F_X_W_M2_E32_MASK, VFNCVT_F_X_W }, // 2027 |
| 23298 | { PseudoVFNCVT_F_X_W_M4_E16, VFNCVT_F_X_W }, // 2028 |
| 23299 | { PseudoVFNCVT_F_X_W_M4_E16_MASK, VFNCVT_F_X_W }, // 2029 |
| 23300 | { PseudoVFNCVT_F_X_W_M4_E32, VFNCVT_F_X_W }, // 2030 |
| 23301 | { PseudoVFNCVT_F_X_W_M4_E32_MASK, VFNCVT_F_X_W }, // 2031 |
| 23302 | { PseudoVFNCVT_F_X_W_MF2_E16, VFNCVT_F_X_W }, // 2032 |
| 23303 | { PseudoVFNCVT_F_X_W_MF2_E16_MASK, VFNCVT_F_X_W }, // 2033 |
| 23304 | { PseudoVFNCVT_F_X_W_MF2_E32, VFNCVT_F_X_W }, // 2034 |
| 23305 | { PseudoVFNCVT_F_X_W_MF2_E32_MASK, VFNCVT_F_X_W }, // 2035 |
| 23306 | { PseudoVFNCVT_F_X_W_MF4_E16, VFNCVT_F_X_W }, // 2036 |
| 23307 | { PseudoVFNCVT_F_X_W_MF4_E16_MASK, VFNCVT_F_X_W }, // 2037 |
| 23308 | { PseudoVFNCVT_RM_F_XU_W_M1_E16, VFNCVT_F_XU_W }, // 2038 |
| 23309 | { PseudoVFNCVT_RM_F_XU_W_M1_E16_MASK, VFNCVT_F_XU_W }, // 2039 |
| 23310 | { PseudoVFNCVT_RM_F_XU_W_M1_E32, VFNCVT_F_XU_W }, // 2040 |
| 23311 | { PseudoVFNCVT_RM_F_XU_W_M1_E32_MASK, VFNCVT_F_XU_W }, // 2041 |
| 23312 | { PseudoVFNCVT_RM_F_XU_W_M2_E16, VFNCVT_F_XU_W }, // 2042 |
| 23313 | { PseudoVFNCVT_RM_F_XU_W_M2_E16_MASK, VFNCVT_F_XU_W }, // 2043 |
| 23314 | { PseudoVFNCVT_RM_F_XU_W_M2_E32, VFNCVT_F_XU_W }, // 2044 |
| 23315 | { PseudoVFNCVT_RM_F_XU_W_M2_E32_MASK, VFNCVT_F_XU_W }, // 2045 |
| 23316 | { PseudoVFNCVT_RM_F_XU_W_M4_E16, VFNCVT_F_XU_W }, // 2046 |
| 23317 | { PseudoVFNCVT_RM_F_XU_W_M4_E16_MASK, VFNCVT_F_XU_W }, // 2047 |
| 23318 | { PseudoVFNCVT_RM_F_XU_W_M4_E32, VFNCVT_F_XU_W }, // 2048 |
| 23319 | { PseudoVFNCVT_RM_F_XU_W_M4_E32_MASK, VFNCVT_F_XU_W }, // 2049 |
| 23320 | { PseudoVFNCVT_RM_F_XU_W_MF2_E16, VFNCVT_F_XU_W }, // 2050 |
| 23321 | { PseudoVFNCVT_RM_F_XU_W_MF2_E16_MASK, VFNCVT_F_XU_W }, // 2051 |
| 23322 | { PseudoVFNCVT_RM_F_XU_W_MF2_E32, VFNCVT_F_XU_W }, // 2052 |
| 23323 | { PseudoVFNCVT_RM_F_XU_W_MF2_E32_MASK, VFNCVT_F_XU_W }, // 2053 |
| 23324 | { PseudoVFNCVT_RM_F_XU_W_MF4_E16, VFNCVT_F_XU_W }, // 2054 |
| 23325 | { PseudoVFNCVT_RM_F_XU_W_MF4_E16_MASK, VFNCVT_F_XU_W }, // 2055 |
| 23326 | { PseudoVFNCVT_RM_F_X_W_M1_E16, VFNCVT_F_X_W }, // 2056 |
| 23327 | { PseudoVFNCVT_RM_F_X_W_M1_E16_MASK, VFNCVT_F_X_W }, // 2057 |
| 23328 | { PseudoVFNCVT_RM_F_X_W_M1_E32, VFNCVT_F_X_W }, // 2058 |
| 23329 | { PseudoVFNCVT_RM_F_X_W_M1_E32_MASK, VFNCVT_F_X_W }, // 2059 |
| 23330 | { PseudoVFNCVT_RM_F_X_W_M2_E16, VFNCVT_F_X_W }, // 2060 |
| 23331 | { PseudoVFNCVT_RM_F_X_W_M2_E16_MASK, VFNCVT_F_X_W }, // 2061 |
| 23332 | { PseudoVFNCVT_RM_F_X_W_M2_E32, VFNCVT_F_X_W }, // 2062 |
| 23333 | { PseudoVFNCVT_RM_F_X_W_M2_E32_MASK, VFNCVT_F_X_W }, // 2063 |
| 23334 | { PseudoVFNCVT_RM_F_X_W_M4_E16, VFNCVT_F_X_W }, // 2064 |
| 23335 | { PseudoVFNCVT_RM_F_X_W_M4_E16_MASK, VFNCVT_F_X_W }, // 2065 |
| 23336 | { PseudoVFNCVT_RM_F_X_W_M4_E32, VFNCVT_F_X_W }, // 2066 |
| 23337 | { PseudoVFNCVT_RM_F_X_W_M4_E32_MASK, VFNCVT_F_X_W }, // 2067 |
| 23338 | { PseudoVFNCVT_RM_F_X_W_MF2_E16, VFNCVT_F_X_W }, // 2068 |
| 23339 | { PseudoVFNCVT_RM_F_X_W_MF2_E16_MASK, VFNCVT_F_X_W }, // 2069 |
| 23340 | { PseudoVFNCVT_RM_F_X_W_MF2_E32, VFNCVT_F_X_W }, // 2070 |
| 23341 | { PseudoVFNCVT_RM_F_X_W_MF2_E32_MASK, VFNCVT_F_X_W }, // 2071 |
| 23342 | { PseudoVFNCVT_RM_F_X_W_MF4_E16, VFNCVT_F_X_W }, // 2072 |
| 23343 | { PseudoVFNCVT_RM_F_X_W_MF4_E16_MASK, VFNCVT_F_X_W }, // 2073 |
| 23344 | { PseudoVFNCVT_RM_XU_F_W_M1, VFNCVT_XU_F_W }, // 2074 |
| 23345 | { PseudoVFNCVT_RM_XU_F_W_M1_MASK, VFNCVT_XU_F_W }, // 2075 |
| 23346 | { PseudoVFNCVT_RM_XU_F_W_M2, VFNCVT_XU_F_W }, // 2076 |
| 23347 | { PseudoVFNCVT_RM_XU_F_W_M2_MASK, VFNCVT_XU_F_W }, // 2077 |
| 23348 | { PseudoVFNCVT_RM_XU_F_W_M4, VFNCVT_XU_F_W }, // 2078 |
| 23349 | { PseudoVFNCVT_RM_XU_F_W_M4_MASK, VFNCVT_XU_F_W }, // 2079 |
| 23350 | { PseudoVFNCVT_RM_XU_F_W_MF2, VFNCVT_XU_F_W }, // 2080 |
| 23351 | { PseudoVFNCVT_RM_XU_F_W_MF2_MASK, VFNCVT_XU_F_W }, // 2081 |
| 23352 | { PseudoVFNCVT_RM_XU_F_W_MF4, VFNCVT_XU_F_W }, // 2082 |
| 23353 | { PseudoVFNCVT_RM_XU_F_W_MF4_MASK, VFNCVT_XU_F_W }, // 2083 |
| 23354 | { PseudoVFNCVT_RM_XU_F_W_MF8, VFNCVT_XU_F_W }, // 2084 |
| 23355 | { PseudoVFNCVT_RM_XU_F_W_MF8_MASK, VFNCVT_XU_F_W }, // 2085 |
| 23356 | { PseudoVFNCVT_RM_X_F_W_M1, VFNCVT_X_F_W }, // 2086 |
| 23357 | { PseudoVFNCVT_RM_X_F_W_M1_MASK, VFNCVT_X_F_W }, // 2087 |
| 23358 | { PseudoVFNCVT_RM_X_F_W_M2, VFNCVT_X_F_W }, // 2088 |
| 23359 | { PseudoVFNCVT_RM_X_F_W_M2_MASK, VFNCVT_X_F_W }, // 2089 |
| 23360 | { PseudoVFNCVT_RM_X_F_W_M4, VFNCVT_X_F_W }, // 2090 |
| 23361 | { PseudoVFNCVT_RM_X_F_W_M4_MASK, VFNCVT_X_F_W }, // 2091 |
| 23362 | { PseudoVFNCVT_RM_X_F_W_MF2, VFNCVT_X_F_W }, // 2092 |
| 23363 | { PseudoVFNCVT_RM_X_F_W_MF2_MASK, VFNCVT_X_F_W }, // 2093 |
| 23364 | { PseudoVFNCVT_RM_X_F_W_MF4, VFNCVT_X_F_W }, // 2094 |
| 23365 | { PseudoVFNCVT_RM_X_F_W_MF4_MASK, VFNCVT_X_F_W }, // 2095 |
| 23366 | { PseudoVFNCVT_RM_X_F_W_MF8, VFNCVT_X_F_W }, // 2096 |
| 23367 | { PseudoVFNCVT_RM_X_F_W_MF8_MASK, VFNCVT_X_F_W }, // 2097 |
| 23368 | { PseudoVFNCVT_ROD_F_F_W_M1_E16, VFNCVT_ROD_F_F_W }, // 2098 |
| 23369 | { PseudoVFNCVT_ROD_F_F_W_M1_E16_MASK, VFNCVT_ROD_F_F_W }, // 2099 |
| 23370 | { PseudoVFNCVT_ROD_F_F_W_M1_E32, VFNCVT_ROD_F_F_W }, // 2100 |
| 23371 | { PseudoVFNCVT_ROD_F_F_W_M1_E32_MASK, VFNCVT_ROD_F_F_W }, // 2101 |
| 23372 | { PseudoVFNCVT_ROD_F_F_W_M2_E16, VFNCVT_ROD_F_F_W }, // 2102 |
| 23373 | { PseudoVFNCVT_ROD_F_F_W_M2_E16_MASK, VFNCVT_ROD_F_F_W }, // 2103 |
| 23374 | { PseudoVFNCVT_ROD_F_F_W_M2_E32, VFNCVT_ROD_F_F_W }, // 2104 |
| 23375 | { PseudoVFNCVT_ROD_F_F_W_M2_E32_MASK, VFNCVT_ROD_F_F_W }, // 2105 |
| 23376 | { PseudoVFNCVT_ROD_F_F_W_M4_E16, VFNCVT_ROD_F_F_W }, // 2106 |
| 23377 | { PseudoVFNCVT_ROD_F_F_W_M4_E16_MASK, VFNCVT_ROD_F_F_W }, // 2107 |
| 23378 | { PseudoVFNCVT_ROD_F_F_W_M4_E32, VFNCVT_ROD_F_F_W }, // 2108 |
| 23379 | { PseudoVFNCVT_ROD_F_F_W_M4_E32_MASK, VFNCVT_ROD_F_F_W }, // 2109 |
| 23380 | { PseudoVFNCVT_ROD_F_F_W_MF2_E16, VFNCVT_ROD_F_F_W }, // 2110 |
| 23381 | { PseudoVFNCVT_ROD_F_F_W_MF2_E16_MASK, VFNCVT_ROD_F_F_W }, // 2111 |
| 23382 | { PseudoVFNCVT_ROD_F_F_W_MF2_E32, VFNCVT_ROD_F_F_W }, // 2112 |
| 23383 | { PseudoVFNCVT_ROD_F_F_W_MF2_E32_MASK, VFNCVT_ROD_F_F_W }, // 2113 |
| 23384 | { PseudoVFNCVT_ROD_F_F_W_MF4_E16, VFNCVT_ROD_F_F_W }, // 2114 |
| 23385 | { PseudoVFNCVT_ROD_F_F_W_MF4_E16_MASK, VFNCVT_ROD_F_F_W }, // 2115 |
| 23386 | { PseudoVFNCVT_RTZ_XU_F_W_M1, VFNCVT_RTZ_XU_F_W }, // 2116 |
| 23387 | { PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, VFNCVT_RTZ_XU_F_W }, // 2117 |
| 23388 | { PseudoVFNCVT_RTZ_XU_F_W_M2, VFNCVT_RTZ_XU_F_W }, // 2118 |
| 23389 | { PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, VFNCVT_RTZ_XU_F_W }, // 2119 |
| 23390 | { PseudoVFNCVT_RTZ_XU_F_W_M4, VFNCVT_RTZ_XU_F_W }, // 2120 |
| 23391 | { PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, VFNCVT_RTZ_XU_F_W }, // 2121 |
| 23392 | { PseudoVFNCVT_RTZ_XU_F_W_MF2, VFNCVT_RTZ_XU_F_W }, // 2122 |
| 23393 | { PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, VFNCVT_RTZ_XU_F_W }, // 2123 |
| 23394 | { PseudoVFNCVT_RTZ_XU_F_W_MF4, VFNCVT_RTZ_XU_F_W }, // 2124 |
| 23395 | { PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, VFNCVT_RTZ_XU_F_W }, // 2125 |
| 23396 | { PseudoVFNCVT_RTZ_XU_F_W_MF8, VFNCVT_RTZ_XU_F_W }, // 2126 |
| 23397 | { PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, VFNCVT_RTZ_XU_F_W }, // 2127 |
| 23398 | { PseudoVFNCVT_RTZ_X_F_W_M1, VFNCVT_RTZ_X_F_W }, // 2128 |
| 23399 | { PseudoVFNCVT_RTZ_X_F_W_M1_MASK, VFNCVT_RTZ_X_F_W }, // 2129 |
| 23400 | { PseudoVFNCVT_RTZ_X_F_W_M2, VFNCVT_RTZ_X_F_W }, // 2130 |
| 23401 | { PseudoVFNCVT_RTZ_X_F_W_M2_MASK, VFNCVT_RTZ_X_F_W }, // 2131 |
| 23402 | { PseudoVFNCVT_RTZ_X_F_W_M4, VFNCVT_RTZ_X_F_W }, // 2132 |
| 23403 | { PseudoVFNCVT_RTZ_X_F_W_M4_MASK, VFNCVT_RTZ_X_F_W }, // 2133 |
| 23404 | { PseudoVFNCVT_RTZ_X_F_W_MF2, VFNCVT_RTZ_X_F_W }, // 2134 |
| 23405 | { PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, VFNCVT_RTZ_X_F_W }, // 2135 |
| 23406 | { PseudoVFNCVT_RTZ_X_F_W_MF4, VFNCVT_RTZ_X_F_W }, // 2136 |
| 23407 | { PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, VFNCVT_RTZ_X_F_W }, // 2137 |
| 23408 | { PseudoVFNCVT_RTZ_X_F_W_MF8, VFNCVT_RTZ_X_F_W }, // 2138 |
| 23409 | { PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, VFNCVT_RTZ_X_F_W }, // 2139 |
| 23410 | { PseudoVFNCVT_XU_F_W_M1, VFNCVT_XU_F_W }, // 2140 |
| 23411 | { PseudoVFNCVT_XU_F_W_M1_MASK, VFNCVT_XU_F_W }, // 2141 |
| 23412 | { PseudoVFNCVT_XU_F_W_M2, VFNCVT_XU_F_W }, // 2142 |
| 23413 | { PseudoVFNCVT_XU_F_W_M2_MASK, VFNCVT_XU_F_W }, // 2143 |
| 23414 | { PseudoVFNCVT_XU_F_W_M4, VFNCVT_XU_F_W }, // 2144 |
| 23415 | { PseudoVFNCVT_XU_F_W_M4_MASK, VFNCVT_XU_F_W }, // 2145 |
| 23416 | { PseudoVFNCVT_XU_F_W_MF2, VFNCVT_XU_F_W }, // 2146 |
| 23417 | { PseudoVFNCVT_XU_F_W_MF2_MASK, VFNCVT_XU_F_W }, // 2147 |
| 23418 | { PseudoVFNCVT_XU_F_W_MF4, VFNCVT_XU_F_W }, // 2148 |
| 23419 | { PseudoVFNCVT_XU_F_W_MF4_MASK, VFNCVT_XU_F_W }, // 2149 |
| 23420 | { PseudoVFNCVT_XU_F_W_MF8, VFNCVT_XU_F_W }, // 2150 |
| 23421 | { PseudoVFNCVT_XU_F_W_MF8_MASK, VFNCVT_XU_F_W }, // 2151 |
| 23422 | { PseudoVFNCVT_X_F_W_M1, VFNCVT_X_F_W }, // 2152 |
| 23423 | { PseudoVFNCVT_X_F_W_M1_MASK, VFNCVT_X_F_W }, // 2153 |
| 23424 | { PseudoVFNCVT_X_F_W_M2, VFNCVT_X_F_W }, // 2154 |
| 23425 | { PseudoVFNCVT_X_F_W_M2_MASK, VFNCVT_X_F_W }, // 2155 |
| 23426 | { PseudoVFNCVT_X_F_W_M4, VFNCVT_X_F_W }, // 2156 |
| 23427 | { PseudoVFNCVT_X_F_W_M4_MASK, VFNCVT_X_F_W }, // 2157 |
| 23428 | { PseudoVFNCVT_X_F_W_MF2, VFNCVT_X_F_W }, // 2158 |
| 23429 | { PseudoVFNCVT_X_F_W_MF2_MASK, VFNCVT_X_F_W }, // 2159 |
| 23430 | { PseudoVFNCVT_X_F_W_MF4, VFNCVT_X_F_W }, // 2160 |
| 23431 | { PseudoVFNCVT_X_F_W_MF4_MASK, VFNCVT_X_F_W }, // 2161 |
| 23432 | { PseudoVFNCVT_X_F_W_MF8, VFNCVT_X_F_W }, // 2162 |
| 23433 | { PseudoVFNCVT_X_F_W_MF8_MASK, VFNCVT_X_F_W }, // 2163 |
| 23434 | { PseudoVFNMACC_VFPR16_M1_E16, VFNMACC_VF }, // 2164 |
| 23435 | { PseudoVFNMACC_VFPR16_M1_E16_MASK, VFNMACC_VF }, // 2165 |
| 23436 | { PseudoVFNMACC_VFPR16_M2_E16, VFNMACC_VF }, // 2166 |
| 23437 | { PseudoVFNMACC_VFPR16_M2_E16_MASK, VFNMACC_VF }, // 2167 |
| 23438 | { PseudoVFNMACC_VFPR16_M4_E16, VFNMACC_VF }, // 2168 |
| 23439 | { PseudoVFNMACC_VFPR16_M4_E16_MASK, VFNMACC_VF }, // 2169 |
| 23440 | { PseudoVFNMACC_VFPR16_M8_E16, VFNMACC_VF }, // 2170 |
| 23441 | { PseudoVFNMACC_VFPR16_M8_E16_MASK, VFNMACC_VF }, // 2171 |
| 23442 | { PseudoVFNMACC_VFPR16_MF2_E16, VFNMACC_VF }, // 2172 |
| 23443 | { PseudoVFNMACC_VFPR16_MF2_E16_MASK, VFNMACC_VF }, // 2173 |
| 23444 | { PseudoVFNMACC_VFPR16_MF4_E16, VFNMACC_VF }, // 2174 |
| 23445 | { PseudoVFNMACC_VFPR16_MF4_E16_MASK, VFNMACC_VF }, // 2175 |
| 23446 | { PseudoVFNMACC_VFPR32_M1_E32, VFNMACC_VF }, // 2176 |
| 23447 | { PseudoVFNMACC_VFPR32_M1_E32_MASK, VFNMACC_VF }, // 2177 |
| 23448 | { PseudoVFNMACC_VFPR32_M2_E32, VFNMACC_VF }, // 2178 |
| 23449 | { PseudoVFNMACC_VFPR32_M2_E32_MASK, VFNMACC_VF }, // 2179 |
| 23450 | { PseudoVFNMACC_VFPR32_M4_E32, VFNMACC_VF }, // 2180 |
| 23451 | { PseudoVFNMACC_VFPR32_M4_E32_MASK, VFNMACC_VF }, // 2181 |
| 23452 | { PseudoVFNMACC_VFPR32_M8_E32, VFNMACC_VF }, // 2182 |
| 23453 | { PseudoVFNMACC_VFPR32_M8_E32_MASK, VFNMACC_VF }, // 2183 |
| 23454 | { PseudoVFNMACC_VFPR32_MF2_E32, VFNMACC_VF }, // 2184 |
| 23455 | { PseudoVFNMACC_VFPR32_MF2_E32_MASK, VFNMACC_VF }, // 2185 |
| 23456 | { PseudoVFNMACC_VFPR64_M1_E64, VFNMACC_VF }, // 2186 |
| 23457 | { PseudoVFNMACC_VFPR64_M1_E64_MASK, VFNMACC_VF }, // 2187 |
| 23458 | { PseudoVFNMACC_VFPR64_M2_E64, VFNMACC_VF }, // 2188 |
| 23459 | { PseudoVFNMACC_VFPR64_M2_E64_MASK, VFNMACC_VF }, // 2189 |
| 23460 | { PseudoVFNMACC_VFPR64_M4_E64, VFNMACC_VF }, // 2190 |
| 23461 | { PseudoVFNMACC_VFPR64_M4_E64_MASK, VFNMACC_VF }, // 2191 |
| 23462 | { PseudoVFNMACC_VFPR64_M8_E64, VFNMACC_VF }, // 2192 |
| 23463 | { PseudoVFNMACC_VFPR64_M8_E64_MASK, VFNMACC_VF }, // 2193 |
| 23464 | { PseudoVFNMACC_VV_M1_E16, VFNMACC_VV }, // 2194 |
| 23465 | { PseudoVFNMACC_VV_M1_E16_MASK, VFNMACC_VV }, // 2195 |
| 23466 | { PseudoVFNMACC_VV_M1_E32, VFNMACC_VV }, // 2196 |
| 23467 | { PseudoVFNMACC_VV_M1_E32_MASK, VFNMACC_VV }, // 2197 |
| 23468 | { PseudoVFNMACC_VV_M1_E64, VFNMACC_VV }, // 2198 |
| 23469 | { PseudoVFNMACC_VV_M1_E64_MASK, VFNMACC_VV }, // 2199 |
| 23470 | { PseudoVFNMACC_VV_M2_E16, VFNMACC_VV }, // 2200 |
| 23471 | { PseudoVFNMACC_VV_M2_E16_MASK, VFNMACC_VV }, // 2201 |
| 23472 | { PseudoVFNMACC_VV_M2_E32, VFNMACC_VV }, // 2202 |
| 23473 | { PseudoVFNMACC_VV_M2_E32_MASK, VFNMACC_VV }, // 2203 |
| 23474 | { PseudoVFNMACC_VV_M2_E64, VFNMACC_VV }, // 2204 |
| 23475 | { PseudoVFNMACC_VV_M2_E64_MASK, VFNMACC_VV }, // 2205 |
| 23476 | { PseudoVFNMACC_VV_M4_E16, VFNMACC_VV }, // 2206 |
| 23477 | { PseudoVFNMACC_VV_M4_E16_MASK, VFNMACC_VV }, // 2207 |
| 23478 | { PseudoVFNMACC_VV_M4_E32, VFNMACC_VV }, // 2208 |
| 23479 | { PseudoVFNMACC_VV_M4_E32_MASK, VFNMACC_VV }, // 2209 |
| 23480 | { PseudoVFNMACC_VV_M4_E64, VFNMACC_VV }, // 2210 |
| 23481 | { PseudoVFNMACC_VV_M4_E64_MASK, VFNMACC_VV }, // 2211 |
| 23482 | { PseudoVFNMACC_VV_M8_E16, VFNMACC_VV }, // 2212 |
| 23483 | { PseudoVFNMACC_VV_M8_E16_MASK, VFNMACC_VV }, // 2213 |
| 23484 | { PseudoVFNMACC_VV_M8_E32, VFNMACC_VV }, // 2214 |
| 23485 | { PseudoVFNMACC_VV_M8_E32_MASK, VFNMACC_VV }, // 2215 |
| 23486 | { PseudoVFNMACC_VV_M8_E64, VFNMACC_VV }, // 2216 |
| 23487 | { PseudoVFNMACC_VV_M8_E64_MASK, VFNMACC_VV }, // 2217 |
| 23488 | { PseudoVFNMACC_VV_MF2_E16, VFNMACC_VV }, // 2218 |
| 23489 | { PseudoVFNMACC_VV_MF2_E16_MASK, VFNMACC_VV }, // 2219 |
| 23490 | { PseudoVFNMACC_VV_MF2_E32, VFNMACC_VV }, // 2220 |
| 23491 | { PseudoVFNMACC_VV_MF2_E32_MASK, VFNMACC_VV }, // 2221 |
| 23492 | { PseudoVFNMACC_VV_MF4_E16, VFNMACC_VV }, // 2222 |
| 23493 | { PseudoVFNMACC_VV_MF4_E16_MASK, VFNMACC_VV }, // 2223 |
| 23494 | { PseudoVFNMADD_VFPR16_M1_E16, VFNMADD_VF }, // 2224 |
| 23495 | { PseudoVFNMADD_VFPR16_M1_E16_MASK, VFNMADD_VF }, // 2225 |
| 23496 | { PseudoVFNMADD_VFPR16_M2_E16, VFNMADD_VF }, // 2226 |
| 23497 | { PseudoVFNMADD_VFPR16_M2_E16_MASK, VFNMADD_VF }, // 2227 |
| 23498 | { PseudoVFNMADD_VFPR16_M4_E16, VFNMADD_VF }, // 2228 |
| 23499 | { PseudoVFNMADD_VFPR16_M4_E16_MASK, VFNMADD_VF }, // 2229 |
| 23500 | { PseudoVFNMADD_VFPR16_M8_E16, VFNMADD_VF }, // 2230 |
| 23501 | { PseudoVFNMADD_VFPR16_M8_E16_MASK, VFNMADD_VF }, // 2231 |
| 23502 | { PseudoVFNMADD_VFPR16_MF2_E16, VFNMADD_VF }, // 2232 |
| 23503 | { PseudoVFNMADD_VFPR16_MF2_E16_MASK, VFNMADD_VF }, // 2233 |
| 23504 | { PseudoVFNMADD_VFPR16_MF4_E16, VFNMADD_VF }, // 2234 |
| 23505 | { PseudoVFNMADD_VFPR16_MF4_E16_MASK, VFNMADD_VF }, // 2235 |
| 23506 | { PseudoVFNMADD_VFPR32_M1_E32, VFNMADD_VF }, // 2236 |
| 23507 | { PseudoVFNMADD_VFPR32_M1_E32_MASK, VFNMADD_VF }, // 2237 |
| 23508 | { PseudoVFNMADD_VFPR32_M2_E32, VFNMADD_VF }, // 2238 |
| 23509 | { PseudoVFNMADD_VFPR32_M2_E32_MASK, VFNMADD_VF }, // 2239 |
| 23510 | { PseudoVFNMADD_VFPR32_M4_E32, VFNMADD_VF }, // 2240 |
| 23511 | { PseudoVFNMADD_VFPR32_M4_E32_MASK, VFNMADD_VF }, // 2241 |
| 23512 | { PseudoVFNMADD_VFPR32_M8_E32, VFNMADD_VF }, // 2242 |
| 23513 | { PseudoVFNMADD_VFPR32_M8_E32_MASK, VFNMADD_VF }, // 2243 |
| 23514 | { PseudoVFNMADD_VFPR32_MF2_E32, VFNMADD_VF }, // 2244 |
| 23515 | { PseudoVFNMADD_VFPR32_MF2_E32_MASK, VFNMADD_VF }, // 2245 |
| 23516 | { PseudoVFNMADD_VFPR64_M1_E64, VFNMADD_VF }, // 2246 |
| 23517 | { PseudoVFNMADD_VFPR64_M1_E64_MASK, VFNMADD_VF }, // 2247 |
| 23518 | { PseudoVFNMADD_VFPR64_M2_E64, VFNMADD_VF }, // 2248 |
| 23519 | { PseudoVFNMADD_VFPR64_M2_E64_MASK, VFNMADD_VF }, // 2249 |
| 23520 | { PseudoVFNMADD_VFPR64_M4_E64, VFNMADD_VF }, // 2250 |
| 23521 | { PseudoVFNMADD_VFPR64_M4_E64_MASK, VFNMADD_VF }, // 2251 |
| 23522 | { PseudoVFNMADD_VFPR64_M8_E64, VFNMADD_VF }, // 2252 |
| 23523 | { PseudoVFNMADD_VFPR64_M8_E64_MASK, VFNMADD_VF }, // 2253 |
| 23524 | { PseudoVFNMADD_VV_M1_E16, VFNMADD_VV }, // 2254 |
| 23525 | { PseudoVFNMADD_VV_M1_E16_MASK, VFNMADD_VV }, // 2255 |
| 23526 | { PseudoVFNMADD_VV_M1_E32, VFNMADD_VV }, // 2256 |
| 23527 | { PseudoVFNMADD_VV_M1_E32_MASK, VFNMADD_VV }, // 2257 |
| 23528 | { PseudoVFNMADD_VV_M1_E64, VFNMADD_VV }, // 2258 |
| 23529 | { PseudoVFNMADD_VV_M1_E64_MASK, VFNMADD_VV }, // 2259 |
| 23530 | { PseudoVFNMADD_VV_M2_E16, VFNMADD_VV }, // 2260 |
| 23531 | { PseudoVFNMADD_VV_M2_E16_MASK, VFNMADD_VV }, // 2261 |
| 23532 | { PseudoVFNMADD_VV_M2_E32, VFNMADD_VV }, // 2262 |
| 23533 | { PseudoVFNMADD_VV_M2_E32_MASK, VFNMADD_VV }, // 2263 |
| 23534 | { PseudoVFNMADD_VV_M2_E64, VFNMADD_VV }, // 2264 |
| 23535 | { PseudoVFNMADD_VV_M2_E64_MASK, VFNMADD_VV }, // 2265 |
| 23536 | { PseudoVFNMADD_VV_M4_E16, VFNMADD_VV }, // 2266 |
| 23537 | { PseudoVFNMADD_VV_M4_E16_MASK, VFNMADD_VV }, // 2267 |
| 23538 | { PseudoVFNMADD_VV_M4_E32, VFNMADD_VV }, // 2268 |
| 23539 | { PseudoVFNMADD_VV_M4_E32_MASK, VFNMADD_VV }, // 2269 |
| 23540 | { PseudoVFNMADD_VV_M4_E64, VFNMADD_VV }, // 2270 |
| 23541 | { PseudoVFNMADD_VV_M4_E64_MASK, VFNMADD_VV }, // 2271 |
| 23542 | { PseudoVFNMADD_VV_M8_E16, VFNMADD_VV }, // 2272 |
| 23543 | { PseudoVFNMADD_VV_M8_E16_MASK, VFNMADD_VV }, // 2273 |
| 23544 | { PseudoVFNMADD_VV_M8_E32, VFNMADD_VV }, // 2274 |
| 23545 | { PseudoVFNMADD_VV_M8_E32_MASK, VFNMADD_VV }, // 2275 |
| 23546 | { PseudoVFNMADD_VV_M8_E64, VFNMADD_VV }, // 2276 |
| 23547 | { PseudoVFNMADD_VV_M8_E64_MASK, VFNMADD_VV }, // 2277 |
| 23548 | { PseudoVFNMADD_VV_MF2_E16, VFNMADD_VV }, // 2278 |
| 23549 | { PseudoVFNMADD_VV_MF2_E16_MASK, VFNMADD_VV }, // 2279 |
| 23550 | { PseudoVFNMADD_VV_MF2_E32, VFNMADD_VV }, // 2280 |
| 23551 | { PseudoVFNMADD_VV_MF2_E32_MASK, VFNMADD_VV }, // 2281 |
| 23552 | { PseudoVFNMADD_VV_MF4_E16, VFNMADD_VV }, // 2282 |
| 23553 | { PseudoVFNMADD_VV_MF4_E16_MASK, VFNMADD_VV }, // 2283 |
| 23554 | { PseudoVFNMSAC_VFPR16_M1_E16, VFNMSAC_VF }, // 2284 |
| 23555 | { PseudoVFNMSAC_VFPR16_M1_E16_MASK, VFNMSAC_VF }, // 2285 |
| 23556 | { PseudoVFNMSAC_VFPR16_M2_E16, VFNMSAC_VF }, // 2286 |
| 23557 | { PseudoVFNMSAC_VFPR16_M2_E16_MASK, VFNMSAC_VF }, // 2287 |
| 23558 | { PseudoVFNMSAC_VFPR16_M4_E16, VFNMSAC_VF }, // 2288 |
| 23559 | { PseudoVFNMSAC_VFPR16_M4_E16_MASK, VFNMSAC_VF }, // 2289 |
| 23560 | { PseudoVFNMSAC_VFPR16_M8_E16, VFNMSAC_VF }, // 2290 |
| 23561 | { PseudoVFNMSAC_VFPR16_M8_E16_MASK, VFNMSAC_VF }, // 2291 |
| 23562 | { PseudoVFNMSAC_VFPR16_MF2_E16, VFNMSAC_VF }, // 2292 |
| 23563 | { PseudoVFNMSAC_VFPR16_MF2_E16_MASK, VFNMSAC_VF }, // 2293 |
| 23564 | { PseudoVFNMSAC_VFPR16_MF4_E16, VFNMSAC_VF }, // 2294 |
| 23565 | { PseudoVFNMSAC_VFPR16_MF4_E16_MASK, VFNMSAC_VF }, // 2295 |
| 23566 | { PseudoVFNMSAC_VFPR32_M1_E32, VFNMSAC_VF }, // 2296 |
| 23567 | { PseudoVFNMSAC_VFPR32_M1_E32_MASK, VFNMSAC_VF }, // 2297 |
| 23568 | { PseudoVFNMSAC_VFPR32_M2_E32, VFNMSAC_VF }, // 2298 |
| 23569 | { PseudoVFNMSAC_VFPR32_M2_E32_MASK, VFNMSAC_VF }, // 2299 |
| 23570 | { PseudoVFNMSAC_VFPR32_M4_E32, VFNMSAC_VF }, // 2300 |
| 23571 | { PseudoVFNMSAC_VFPR32_M4_E32_MASK, VFNMSAC_VF }, // 2301 |
| 23572 | { PseudoVFNMSAC_VFPR32_M8_E32, VFNMSAC_VF }, // 2302 |
| 23573 | { PseudoVFNMSAC_VFPR32_M8_E32_MASK, VFNMSAC_VF }, // 2303 |
| 23574 | { PseudoVFNMSAC_VFPR32_MF2_E32, VFNMSAC_VF }, // 2304 |
| 23575 | { PseudoVFNMSAC_VFPR32_MF2_E32_MASK, VFNMSAC_VF }, // 2305 |
| 23576 | { PseudoVFNMSAC_VFPR64_M1_E64, VFNMSAC_VF }, // 2306 |
| 23577 | { PseudoVFNMSAC_VFPR64_M1_E64_MASK, VFNMSAC_VF }, // 2307 |
| 23578 | { PseudoVFNMSAC_VFPR64_M2_E64, VFNMSAC_VF }, // 2308 |
| 23579 | { PseudoVFNMSAC_VFPR64_M2_E64_MASK, VFNMSAC_VF }, // 2309 |
| 23580 | { PseudoVFNMSAC_VFPR64_M4_E64, VFNMSAC_VF }, // 2310 |
| 23581 | { PseudoVFNMSAC_VFPR64_M4_E64_MASK, VFNMSAC_VF }, // 2311 |
| 23582 | { PseudoVFNMSAC_VFPR64_M8_E64, VFNMSAC_VF }, // 2312 |
| 23583 | { PseudoVFNMSAC_VFPR64_M8_E64_MASK, VFNMSAC_VF }, // 2313 |
| 23584 | { PseudoVFNMSAC_VV_M1_E16, VFNMSAC_VV }, // 2314 |
| 23585 | { PseudoVFNMSAC_VV_M1_E16_MASK, VFNMSAC_VV }, // 2315 |
| 23586 | { PseudoVFNMSAC_VV_M1_E32, VFNMSAC_VV }, // 2316 |
| 23587 | { PseudoVFNMSAC_VV_M1_E32_MASK, VFNMSAC_VV }, // 2317 |
| 23588 | { PseudoVFNMSAC_VV_M1_E64, VFNMSAC_VV }, // 2318 |
| 23589 | { PseudoVFNMSAC_VV_M1_E64_MASK, VFNMSAC_VV }, // 2319 |
| 23590 | { PseudoVFNMSAC_VV_M2_E16, VFNMSAC_VV }, // 2320 |
| 23591 | { PseudoVFNMSAC_VV_M2_E16_MASK, VFNMSAC_VV }, // 2321 |
| 23592 | { PseudoVFNMSAC_VV_M2_E32, VFNMSAC_VV }, // 2322 |
| 23593 | { PseudoVFNMSAC_VV_M2_E32_MASK, VFNMSAC_VV }, // 2323 |
| 23594 | { PseudoVFNMSAC_VV_M2_E64, VFNMSAC_VV }, // 2324 |
| 23595 | { PseudoVFNMSAC_VV_M2_E64_MASK, VFNMSAC_VV }, // 2325 |
| 23596 | { PseudoVFNMSAC_VV_M4_E16, VFNMSAC_VV }, // 2326 |
| 23597 | { PseudoVFNMSAC_VV_M4_E16_MASK, VFNMSAC_VV }, // 2327 |
| 23598 | { PseudoVFNMSAC_VV_M4_E32, VFNMSAC_VV }, // 2328 |
| 23599 | { PseudoVFNMSAC_VV_M4_E32_MASK, VFNMSAC_VV }, // 2329 |
| 23600 | { PseudoVFNMSAC_VV_M4_E64, VFNMSAC_VV }, // 2330 |
| 23601 | { PseudoVFNMSAC_VV_M4_E64_MASK, VFNMSAC_VV }, // 2331 |
| 23602 | { PseudoVFNMSAC_VV_M8_E16, VFNMSAC_VV }, // 2332 |
| 23603 | { PseudoVFNMSAC_VV_M8_E16_MASK, VFNMSAC_VV }, // 2333 |
| 23604 | { PseudoVFNMSAC_VV_M8_E32, VFNMSAC_VV }, // 2334 |
| 23605 | { PseudoVFNMSAC_VV_M8_E32_MASK, VFNMSAC_VV }, // 2335 |
| 23606 | { PseudoVFNMSAC_VV_M8_E64, VFNMSAC_VV }, // 2336 |
| 23607 | { PseudoVFNMSAC_VV_M8_E64_MASK, VFNMSAC_VV }, // 2337 |
| 23608 | { PseudoVFNMSAC_VV_MF2_E16, VFNMSAC_VV }, // 2338 |
| 23609 | { PseudoVFNMSAC_VV_MF2_E16_MASK, VFNMSAC_VV }, // 2339 |
| 23610 | { PseudoVFNMSAC_VV_MF2_E32, VFNMSAC_VV }, // 2340 |
| 23611 | { PseudoVFNMSAC_VV_MF2_E32_MASK, VFNMSAC_VV }, // 2341 |
| 23612 | { PseudoVFNMSAC_VV_MF4_E16, VFNMSAC_VV }, // 2342 |
| 23613 | { PseudoVFNMSAC_VV_MF4_E16_MASK, VFNMSAC_VV }, // 2343 |
| 23614 | { PseudoVFNMSUB_VFPR16_M1_E16, VFNMSUB_VF }, // 2344 |
| 23615 | { PseudoVFNMSUB_VFPR16_M1_E16_MASK, VFNMSUB_VF }, // 2345 |
| 23616 | { PseudoVFNMSUB_VFPR16_M2_E16, VFNMSUB_VF }, // 2346 |
| 23617 | { PseudoVFNMSUB_VFPR16_M2_E16_MASK, VFNMSUB_VF }, // 2347 |
| 23618 | { PseudoVFNMSUB_VFPR16_M4_E16, VFNMSUB_VF }, // 2348 |
| 23619 | { PseudoVFNMSUB_VFPR16_M4_E16_MASK, VFNMSUB_VF }, // 2349 |
| 23620 | { PseudoVFNMSUB_VFPR16_M8_E16, VFNMSUB_VF }, // 2350 |
| 23621 | { PseudoVFNMSUB_VFPR16_M8_E16_MASK, VFNMSUB_VF }, // 2351 |
| 23622 | { PseudoVFNMSUB_VFPR16_MF2_E16, VFNMSUB_VF }, // 2352 |
| 23623 | { PseudoVFNMSUB_VFPR16_MF2_E16_MASK, VFNMSUB_VF }, // 2353 |
| 23624 | { PseudoVFNMSUB_VFPR16_MF4_E16, VFNMSUB_VF }, // 2354 |
| 23625 | { PseudoVFNMSUB_VFPR16_MF4_E16_MASK, VFNMSUB_VF }, // 2355 |
| 23626 | { PseudoVFNMSUB_VFPR32_M1_E32, VFNMSUB_VF }, // 2356 |
| 23627 | { PseudoVFNMSUB_VFPR32_M1_E32_MASK, VFNMSUB_VF }, // 2357 |
| 23628 | { PseudoVFNMSUB_VFPR32_M2_E32, VFNMSUB_VF }, // 2358 |
| 23629 | { PseudoVFNMSUB_VFPR32_M2_E32_MASK, VFNMSUB_VF }, // 2359 |
| 23630 | { PseudoVFNMSUB_VFPR32_M4_E32, VFNMSUB_VF }, // 2360 |
| 23631 | { PseudoVFNMSUB_VFPR32_M4_E32_MASK, VFNMSUB_VF }, // 2361 |
| 23632 | { PseudoVFNMSUB_VFPR32_M8_E32, VFNMSUB_VF }, // 2362 |
| 23633 | { PseudoVFNMSUB_VFPR32_M8_E32_MASK, VFNMSUB_VF }, // 2363 |
| 23634 | { PseudoVFNMSUB_VFPR32_MF2_E32, VFNMSUB_VF }, // 2364 |
| 23635 | { PseudoVFNMSUB_VFPR32_MF2_E32_MASK, VFNMSUB_VF }, // 2365 |
| 23636 | { PseudoVFNMSUB_VFPR64_M1_E64, VFNMSUB_VF }, // 2366 |
| 23637 | { PseudoVFNMSUB_VFPR64_M1_E64_MASK, VFNMSUB_VF }, // 2367 |
| 23638 | { PseudoVFNMSUB_VFPR64_M2_E64, VFNMSUB_VF }, // 2368 |
| 23639 | { PseudoVFNMSUB_VFPR64_M2_E64_MASK, VFNMSUB_VF }, // 2369 |
| 23640 | { PseudoVFNMSUB_VFPR64_M4_E64, VFNMSUB_VF }, // 2370 |
| 23641 | { PseudoVFNMSUB_VFPR64_M4_E64_MASK, VFNMSUB_VF }, // 2371 |
| 23642 | { PseudoVFNMSUB_VFPR64_M8_E64, VFNMSUB_VF }, // 2372 |
| 23643 | { PseudoVFNMSUB_VFPR64_M8_E64_MASK, VFNMSUB_VF }, // 2373 |
| 23644 | { PseudoVFNMSUB_VV_M1_E16, VFNMSUB_VV }, // 2374 |
| 23645 | { PseudoVFNMSUB_VV_M1_E16_MASK, VFNMSUB_VV }, // 2375 |
| 23646 | { PseudoVFNMSUB_VV_M1_E32, VFNMSUB_VV }, // 2376 |
| 23647 | { PseudoVFNMSUB_VV_M1_E32_MASK, VFNMSUB_VV }, // 2377 |
| 23648 | { PseudoVFNMSUB_VV_M1_E64, VFNMSUB_VV }, // 2378 |
| 23649 | { PseudoVFNMSUB_VV_M1_E64_MASK, VFNMSUB_VV }, // 2379 |
| 23650 | { PseudoVFNMSUB_VV_M2_E16, VFNMSUB_VV }, // 2380 |
| 23651 | { PseudoVFNMSUB_VV_M2_E16_MASK, VFNMSUB_VV }, // 2381 |
| 23652 | { PseudoVFNMSUB_VV_M2_E32, VFNMSUB_VV }, // 2382 |
| 23653 | { PseudoVFNMSUB_VV_M2_E32_MASK, VFNMSUB_VV }, // 2383 |
| 23654 | { PseudoVFNMSUB_VV_M2_E64, VFNMSUB_VV }, // 2384 |
| 23655 | { PseudoVFNMSUB_VV_M2_E64_MASK, VFNMSUB_VV }, // 2385 |
| 23656 | { PseudoVFNMSUB_VV_M4_E16, VFNMSUB_VV }, // 2386 |
| 23657 | { PseudoVFNMSUB_VV_M4_E16_MASK, VFNMSUB_VV }, // 2387 |
| 23658 | { PseudoVFNMSUB_VV_M4_E32, VFNMSUB_VV }, // 2388 |
| 23659 | { PseudoVFNMSUB_VV_M4_E32_MASK, VFNMSUB_VV }, // 2389 |
| 23660 | { PseudoVFNMSUB_VV_M4_E64, VFNMSUB_VV }, // 2390 |
| 23661 | { PseudoVFNMSUB_VV_M4_E64_MASK, VFNMSUB_VV }, // 2391 |
| 23662 | { PseudoVFNMSUB_VV_M8_E16, VFNMSUB_VV }, // 2392 |
| 23663 | { PseudoVFNMSUB_VV_M8_E16_MASK, VFNMSUB_VV }, // 2393 |
| 23664 | { PseudoVFNMSUB_VV_M8_E32, VFNMSUB_VV }, // 2394 |
| 23665 | { PseudoVFNMSUB_VV_M8_E32_MASK, VFNMSUB_VV }, // 2395 |
| 23666 | { PseudoVFNMSUB_VV_M8_E64, VFNMSUB_VV }, // 2396 |
| 23667 | { PseudoVFNMSUB_VV_M8_E64_MASK, VFNMSUB_VV }, // 2397 |
| 23668 | { PseudoVFNMSUB_VV_MF2_E16, VFNMSUB_VV }, // 2398 |
| 23669 | { PseudoVFNMSUB_VV_MF2_E16_MASK, VFNMSUB_VV }, // 2399 |
| 23670 | { PseudoVFNMSUB_VV_MF2_E32, VFNMSUB_VV }, // 2400 |
| 23671 | { PseudoVFNMSUB_VV_MF2_E32_MASK, VFNMSUB_VV }, // 2401 |
| 23672 | { PseudoVFNMSUB_VV_MF4_E16, VFNMSUB_VV }, // 2402 |
| 23673 | { PseudoVFNMSUB_VV_MF4_E16_MASK, VFNMSUB_VV }, // 2403 |
| 23674 | { PseudoVFNRCLIP_XU_F_QF_M1, VFNRCLIP_XU_F_QF }, // 2404 |
| 23675 | { PseudoVFNRCLIP_XU_F_QF_M1_MASK, VFNRCLIP_XU_F_QF }, // 2405 |
| 23676 | { PseudoVFNRCLIP_XU_F_QF_M2, VFNRCLIP_XU_F_QF }, // 2406 |
| 23677 | { PseudoVFNRCLIP_XU_F_QF_M2_MASK, VFNRCLIP_XU_F_QF }, // 2407 |
| 23678 | { PseudoVFNRCLIP_XU_F_QF_MF2, VFNRCLIP_XU_F_QF }, // 2408 |
| 23679 | { PseudoVFNRCLIP_XU_F_QF_MF2_MASK, VFNRCLIP_XU_F_QF }, // 2409 |
| 23680 | { PseudoVFNRCLIP_XU_F_QF_MF4, VFNRCLIP_XU_F_QF }, // 2410 |
| 23681 | { PseudoVFNRCLIP_XU_F_QF_MF4_MASK, VFNRCLIP_XU_F_QF }, // 2411 |
| 23682 | { PseudoVFNRCLIP_XU_F_QF_MF8, VFNRCLIP_XU_F_QF }, // 2412 |
| 23683 | { PseudoVFNRCLIP_XU_F_QF_MF8_MASK, VFNRCLIP_XU_F_QF }, // 2413 |
| 23684 | { PseudoVFNRCLIP_X_F_QF_M1, VFNRCLIP_X_F_QF }, // 2414 |
| 23685 | { PseudoVFNRCLIP_X_F_QF_M1_MASK, VFNRCLIP_X_F_QF }, // 2415 |
| 23686 | { PseudoVFNRCLIP_X_F_QF_M2, VFNRCLIP_X_F_QF }, // 2416 |
| 23687 | { PseudoVFNRCLIP_X_F_QF_M2_MASK, VFNRCLIP_X_F_QF }, // 2417 |
| 23688 | { PseudoVFNRCLIP_X_F_QF_MF2, VFNRCLIP_X_F_QF }, // 2418 |
| 23689 | { PseudoVFNRCLIP_X_F_QF_MF2_MASK, VFNRCLIP_X_F_QF }, // 2419 |
| 23690 | { PseudoVFNRCLIP_X_F_QF_MF4, VFNRCLIP_X_F_QF }, // 2420 |
| 23691 | { PseudoVFNRCLIP_X_F_QF_MF4_MASK, VFNRCLIP_X_F_QF }, // 2421 |
| 23692 | { PseudoVFNRCLIP_X_F_QF_MF8, VFNRCLIP_X_F_QF }, // 2422 |
| 23693 | { PseudoVFNRCLIP_X_F_QF_MF8_MASK, VFNRCLIP_X_F_QF }, // 2423 |
| 23694 | { PseudoVFRDIV_VFPR16_M1_E16, VFRDIV_VF }, // 2424 |
| 23695 | { PseudoVFRDIV_VFPR16_M1_E16_MASK, VFRDIV_VF }, // 2425 |
| 23696 | { PseudoVFRDIV_VFPR16_M2_E16, VFRDIV_VF }, // 2426 |
| 23697 | { PseudoVFRDIV_VFPR16_M2_E16_MASK, VFRDIV_VF }, // 2427 |
| 23698 | { PseudoVFRDIV_VFPR16_M4_E16, VFRDIV_VF }, // 2428 |
| 23699 | { PseudoVFRDIV_VFPR16_M4_E16_MASK, VFRDIV_VF }, // 2429 |
| 23700 | { PseudoVFRDIV_VFPR16_M8_E16, VFRDIV_VF }, // 2430 |
| 23701 | { PseudoVFRDIV_VFPR16_M8_E16_MASK, VFRDIV_VF }, // 2431 |
| 23702 | { PseudoVFRDIV_VFPR16_MF2_E16, VFRDIV_VF }, // 2432 |
| 23703 | { PseudoVFRDIV_VFPR16_MF2_E16_MASK, VFRDIV_VF }, // 2433 |
| 23704 | { PseudoVFRDIV_VFPR16_MF4_E16, VFRDIV_VF }, // 2434 |
| 23705 | { PseudoVFRDIV_VFPR16_MF4_E16_MASK, VFRDIV_VF }, // 2435 |
| 23706 | { PseudoVFRDIV_VFPR32_M1_E32, VFRDIV_VF }, // 2436 |
| 23707 | { PseudoVFRDIV_VFPR32_M1_E32_MASK, VFRDIV_VF }, // 2437 |
| 23708 | { PseudoVFRDIV_VFPR32_M2_E32, VFRDIV_VF }, // 2438 |
| 23709 | { PseudoVFRDIV_VFPR32_M2_E32_MASK, VFRDIV_VF }, // 2439 |
| 23710 | { PseudoVFRDIV_VFPR32_M4_E32, VFRDIV_VF }, // 2440 |
| 23711 | { PseudoVFRDIV_VFPR32_M4_E32_MASK, VFRDIV_VF }, // 2441 |
| 23712 | { PseudoVFRDIV_VFPR32_M8_E32, VFRDIV_VF }, // 2442 |
| 23713 | { PseudoVFRDIV_VFPR32_M8_E32_MASK, VFRDIV_VF }, // 2443 |
| 23714 | { PseudoVFRDIV_VFPR32_MF2_E32, VFRDIV_VF }, // 2444 |
| 23715 | { PseudoVFRDIV_VFPR32_MF2_E32_MASK, VFRDIV_VF }, // 2445 |
| 23716 | { PseudoVFRDIV_VFPR64_M1_E64, VFRDIV_VF }, // 2446 |
| 23717 | { PseudoVFRDIV_VFPR64_M1_E64_MASK, VFRDIV_VF }, // 2447 |
| 23718 | { PseudoVFRDIV_VFPR64_M2_E64, VFRDIV_VF }, // 2448 |
| 23719 | { PseudoVFRDIV_VFPR64_M2_E64_MASK, VFRDIV_VF }, // 2449 |
| 23720 | { PseudoVFRDIV_VFPR64_M4_E64, VFRDIV_VF }, // 2450 |
| 23721 | { PseudoVFRDIV_VFPR64_M4_E64_MASK, VFRDIV_VF }, // 2451 |
| 23722 | { PseudoVFRDIV_VFPR64_M8_E64, VFRDIV_VF }, // 2452 |
| 23723 | { PseudoVFRDIV_VFPR64_M8_E64_MASK, VFRDIV_VF }, // 2453 |
| 23724 | { PseudoVFREC7_V_M1_E16, VFREC7_V }, // 2454 |
| 23725 | { PseudoVFREC7_V_M1_E16_MASK, VFREC7_V }, // 2455 |
| 23726 | { PseudoVFREC7_V_M1_E32, VFREC7_V }, // 2456 |
| 23727 | { PseudoVFREC7_V_M1_E32_MASK, VFREC7_V }, // 2457 |
| 23728 | { PseudoVFREC7_V_M1_E64, VFREC7_V }, // 2458 |
| 23729 | { PseudoVFREC7_V_M1_E64_MASK, VFREC7_V }, // 2459 |
| 23730 | { PseudoVFREC7_V_M2_E16, VFREC7_V }, // 2460 |
| 23731 | { PseudoVFREC7_V_M2_E16_MASK, VFREC7_V }, // 2461 |
| 23732 | { PseudoVFREC7_V_M2_E32, VFREC7_V }, // 2462 |
| 23733 | { PseudoVFREC7_V_M2_E32_MASK, VFREC7_V }, // 2463 |
| 23734 | { PseudoVFREC7_V_M2_E64, VFREC7_V }, // 2464 |
| 23735 | { PseudoVFREC7_V_M2_E64_MASK, VFREC7_V }, // 2465 |
| 23736 | { PseudoVFREC7_V_M4_E16, VFREC7_V }, // 2466 |
| 23737 | { PseudoVFREC7_V_M4_E16_MASK, VFREC7_V }, // 2467 |
| 23738 | { PseudoVFREC7_V_M4_E32, VFREC7_V }, // 2468 |
| 23739 | { PseudoVFREC7_V_M4_E32_MASK, VFREC7_V }, // 2469 |
| 23740 | { PseudoVFREC7_V_M4_E64, VFREC7_V }, // 2470 |
| 23741 | { PseudoVFREC7_V_M4_E64_MASK, VFREC7_V }, // 2471 |
| 23742 | { PseudoVFREC7_V_M8_E16, VFREC7_V }, // 2472 |
| 23743 | { PseudoVFREC7_V_M8_E16_MASK, VFREC7_V }, // 2473 |
| 23744 | { PseudoVFREC7_V_M8_E32, VFREC7_V }, // 2474 |
| 23745 | { PseudoVFREC7_V_M8_E32_MASK, VFREC7_V }, // 2475 |
| 23746 | { PseudoVFREC7_V_M8_E64, VFREC7_V }, // 2476 |
| 23747 | { PseudoVFREC7_V_M8_E64_MASK, VFREC7_V }, // 2477 |
| 23748 | { PseudoVFREC7_V_MF2_E16, VFREC7_V }, // 2478 |
| 23749 | { PseudoVFREC7_V_MF2_E16_MASK, VFREC7_V }, // 2479 |
| 23750 | { PseudoVFREC7_V_MF2_E32, VFREC7_V }, // 2480 |
| 23751 | { PseudoVFREC7_V_MF2_E32_MASK, VFREC7_V }, // 2481 |
| 23752 | { PseudoVFREC7_V_MF4_E16, VFREC7_V }, // 2482 |
| 23753 | { PseudoVFREC7_V_MF4_E16_MASK, VFREC7_V }, // 2483 |
| 23754 | { PseudoVFREDMAX_VS_M1_E16, VFREDMAX_VS }, // 2484 |
| 23755 | { PseudoVFREDMAX_VS_M1_E16_MASK, VFREDMAX_VS }, // 2485 |
| 23756 | { PseudoVFREDMAX_VS_M1_E32, VFREDMAX_VS }, // 2486 |
| 23757 | { PseudoVFREDMAX_VS_M1_E32_MASK, VFREDMAX_VS }, // 2487 |
| 23758 | { PseudoVFREDMAX_VS_M1_E64, VFREDMAX_VS }, // 2488 |
| 23759 | { PseudoVFREDMAX_VS_M1_E64_MASK, VFREDMAX_VS }, // 2489 |
| 23760 | { PseudoVFREDMAX_VS_M2_E16, VFREDMAX_VS }, // 2490 |
| 23761 | { PseudoVFREDMAX_VS_M2_E16_MASK, VFREDMAX_VS }, // 2491 |
| 23762 | { PseudoVFREDMAX_VS_M2_E32, VFREDMAX_VS }, // 2492 |
| 23763 | { PseudoVFREDMAX_VS_M2_E32_MASK, VFREDMAX_VS }, // 2493 |
| 23764 | { PseudoVFREDMAX_VS_M2_E64, VFREDMAX_VS }, // 2494 |
| 23765 | { PseudoVFREDMAX_VS_M2_E64_MASK, VFREDMAX_VS }, // 2495 |
| 23766 | { PseudoVFREDMAX_VS_M4_E16, VFREDMAX_VS }, // 2496 |
| 23767 | { PseudoVFREDMAX_VS_M4_E16_MASK, VFREDMAX_VS }, // 2497 |
| 23768 | { PseudoVFREDMAX_VS_M4_E32, VFREDMAX_VS }, // 2498 |
| 23769 | { PseudoVFREDMAX_VS_M4_E32_MASK, VFREDMAX_VS }, // 2499 |
| 23770 | { PseudoVFREDMAX_VS_M4_E64, VFREDMAX_VS }, // 2500 |
| 23771 | { PseudoVFREDMAX_VS_M4_E64_MASK, VFREDMAX_VS }, // 2501 |
| 23772 | { PseudoVFREDMAX_VS_M8_E16, VFREDMAX_VS }, // 2502 |
| 23773 | { PseudoVFREDMAX_VS_M8_E16_MASK, VFREDMAX_VS }, // 2503 |
| 23774 | { PseudoVFREDMAX_VS_M8_E32, VFREDMAX_VS }, // 2504 |
| 23775 | { PseudoVFREDMAX_VS_M8_E32_MASK, VFREDMAX_VS }, // 2505 |
| 23776 | { PseudoVFREDMAX_VS_M8_E64, VFREDMAX_VS }, // 2506 |
| 23777 | { PseudoVFREDMAX_VS_M8_E64_MASK, VFREDMAX_VS }, // 2507 |
| 23778 | { PseudoVFREDMAX_VS_MF2_E16, VFREDMAX_VS }, // 2508 |
| 23779 | { PseudoVFREDMAX_VS_MF2_E16_MASK, VFREDMAX_VS }, // 2509 |
| 23780 | { PseudoVFREDMAX_VS_MF2_E32, VFREDMAX_VS }, // 2510 |
| 23781 | { PseudoVFREDMAX_VS_MF2_E32_MASK, VFREDMAX_VS }, // 2511 |
| 23782 | { PseudoVFREDMAX_VS_MF4_E16, VFREDMAX_VS }, // 2512 |
| 23783 | { PseudoVFREDMAX_VS_MF4_E16_MASK, VFREDMAX_VS }, // 2513 |
| 23784 | { PseudoVFREDMIN_VS_M1_E16, VFREDMIN_VS }, // 2514 |
| 23785 | { PseudoVFREDMIN_VS_M1_E16_MASK, VFREDMIN_VS }, // 2515 |
| 23786 | { PseudoVFREDMIN_VS_M1_E32, VFREDMIN_VS }, // 2516 |
| 23787 | { PseudoVFREDMIN_VS_M1_E32_MASK, VFREDMIN_VS }, // 2517 |
| 23788 | { PseudoVFREDMIN_VS_M1_E64, VFREDMIN_VS }, // 2518 |
| 23789 | { PseudoVFREDMIN_VS_M1_E64_MASK, VFREDMIN_VS }, // 2519 |
| 23790 | { PseudoVFREDMIN_VS_M2_E16, VFREDMIN_VS }, // 2520 |
| 23791 | { PseudoVFREDMIN_VS_M2_E16_MASK, VFREDMIN_VS }, // 2521 |
| 23792 | { PseudoVFREDMIN_VS_M2_E32, VFREDMIN_VS }, // 2522 |
| 23793 | { PseudoVFREDMIN_VS_M2_E32_MASK, VFREDMIN_VS }, // 2523 |
| 23794 | { PseudoVFREDMIN_VS_M2_E64, VFREDMIN_VS }, // 2524 |
| 23795 | { PseudoVFREDMIN_VS_M2_E64_MASK, VFREDMIN_VS }, // 2525 |
| 23796 | { PseudoVFREDMIN_VS_M4_E16, VFREDMIN_VS }, // 2526 |
| 23797 | { PseudoVFREDMIN_VS_M4_E16_MASK, VFREDMIN_VS }, // 2527 |
| 23798 | { PseudoVFREDMIN_VS_M4_E32, VFREDMIN_VS }, // 2528 |
| 23799 | { PseudoVFREDMIN_VS_M4_E32_MASK, VFREDMIN_VS }, // 2529 |
| 23800 | { PseudoVFREDMIN_VS_M4_E64, VFREDMIN_VS }, // 2530 |
| 23801 | { PseudoVFREDMIN_VS_M4_E64_MASK, VFREDMIN_VS }, // 2531 |
| 23802 | { PseudoVFREDMIN_VS_M8_E16, VFREDMIN_VS }, // 2532 |
| 23803 | { PseudoVFREDMIN_VS_M8_E16_MASK, VFREDMIN_VS }, // 2533 |
| 23804 | { PseudoVFREDMIN_VS_M8_E32, VFREDMIN_VS }, // 2534 |
| 23805 | { PseudoVFREDMIN_VS_M8_E32_MASK, VFREDMIN_VS }, // 2535 |
| 23806 | { PseudoVFREDMIN_VS_M8_E64, VFREDMIN_VS }, // 2536 |
| 23807 | { PseudoVFREDMIN_VS_M8_E64_MASK, VFREDMIN_VS }, // 2537 |
| 23808 | { PseudoVFREDMIN_VS_MF2_E16, VFREDMIN_VS }, // 2538 |
| 23809 | { PseudoVFREDMIN_VS_MF2_E16_MASK, VFREDMIN_VS }, // 2539 |
| 23810 | { PseudoVFREDMIN_VS_MF2_E32, VFREDMIN_VS }, // 2540 |
| 23811 | { PseudoVFREDMIN_VS_MF2_E32_MASK, VFREDMIN_VS }, // 2541 |
| 23812 | { PseudoVFREDMIN_VS_MF4_E16, VFREDMIN_VS }, // 2542 |
| 23813 | { PseudoVFREDMIN_VS_MF4_E16_MASK, VFREDMIN_VS }, // 2543 |
| 23814 | { PseudoVFREDOSUM_VS_M1_E16, VFREDOSUM_VS }, // 2544 |
| 23815 | { PseudoVFREDOSUM_VS_M1_E16_MASK, VFREDOSUM_VS }, // 2545 |
| 23816 | { PseudoVFREDOSUM_VS_M1_E32, VFREDOSUM_VS }, // 2546 |
| 23817 | { PseudoVFREDOSUM_VS_M1_E32_MASK, VFREDOSUM_VS }, // 2547 |
| 23818 | { PseudoVFREDOSUM_VS_M1_E64, VFREDOSUM_VS }, // 2548 |
| 23819 | { PseudoVFREDOSUM_VS_M1_E64_MASK, VFREDOSUM_VS }, // 2549 |
| 23820 | { PseudoVFREDOSUM_VS_M2_E16, VFREDOSUM_VS }, // 2550 |
| 23821 | { PseudoVFREDOSUM_VS_M2_E16_MASK, VFREDOSUM_VS }, // 2551 |
| 23822 | { PseudoVFREDOSUM_VS_M2_E32, VFREDOSUM_VS }, // 2552 |
| 23823 | { PseudoVFREDOSUM_VS_M2_E32_MASK, VFREDOSUM_VS }, // 2553 |
| 23824 | { PseudoVFREDOSUM_VS_M2_E64, VFREDOSUM_VS }, // 2554 |
| 23825 | { PseudoVFREDOSUM_VS_M2_E64_MASK, VFREDOSUM_VS }, // 2555 |
| 23826 | { PseudoVFREDOSUM_VS_M4_E16, VFREDOSUM_VS }, // 2556 |
| 23827 | { PseudoVFREDOSUM_VS_M4_E16_MASK, VFREDOSUM_VS }, // 2557 |
| 23828 | { PseudoVFREDOSUM_VS_M4_E32, VFREDOSUM_VS }, // 2558 |
| 23829 | { PseudoVFREDOSUM_VS_M4_E32_MASK, VFREDOSUM_VS }, // 2559 |
| 23830 | { PseudoVFREDOSUM_VS_M4_E64, VFREDOSUM_VS }, // 2560 |
| 23831 | { PseudoVFREDOSUM_VS_M4_E64_MASK, VFREDOSUM_VS }, // 2561 |
| 23832 | { PseudoVFREDOSUM_VS_M8_E16, VFREDOSUM_VS }, // 2562 |
| 23833 | { PseudoVFREDOSUM_VS_M8_E16_MASK, VFREDOSUM_VS }, // 2563 |
| 23834 | { PseudoVFREDOSUM_VS_M8_E32, VFREDOSUM_VS }, // 2564 |
| 23835 | { PseudoVFREDOSUM_VS_M8_E32_MASK, VFREDOSUM_VS }, // 2565 |
| 23836 | { PseudoVFREDOSUM_VS_M8_E64, VFREDOSUM_VS }, // 2566 |
| 23837 | { PseudoVFREDOSUM_VS_M8_E64_MASK, VFREDOSUM_VS }, // 2567 |
| 23838 | { PseudoVFREDOSUM_VS_MF2_E16, VFREDOSUM_VS }, // 2568 |
| 23839 | { PseudoVFREDOSUM_VS_MF2_E16_MASK, VFREDOSUM_VS }, // 2569 |
| 23840 | { PseudoVFREDOSUM_VS_MF2_E32, VFREDOSUM_VS }, // 2570 |
| 23841 | { PseudoVFREDOSUM_VS_MF2_E32_MASK, VFREDOSUM_VS }, // 2571 |
| 23842 | { PseudoVFREDOSUM_VS_MF4_E16, VFREDOSUM_VS }, // 2572 |
| 23843 | { PseudoVFREDOSUM_VS_MF4_E16_MASK, VFREDOSUM_VS }, // 2573 |
| 23844 | { PseudoVFREDUSUM_VS_M1_E16, VFREDUSUM_VS }, // 2574 |
| 23845 | { PseudoVFREDUSUM_VS_M1_E16_MASK, VFREDUSUM_VS }, // 2575 |
| 23846 | { PseudoVFREDUSUM_VS_M1_E32, VFREDUSUM_VS }, // 2576 |
| 23847 | { PseudoVFREDUSUM_VS_M1_E32_MASK, VFREDUSUM_VS }, // 2577 |
| 23848 | { PseudoVFREDUSUM_VS_M1_E64, VFREDUSUM_VS }, // 2578 |
| 23849 | { PseudoVFREDUSUM_VS_M1_E64_MASK, VFREDUSUM_VS }, // 2579 |
| 23850 | { PseudoVFREDUSUM_VS_M2_E16, VFREDUSUM_VS }, // 2580 |
| 23851 | { PseudoVFREDUSUM_VS_M2_E16_MASK, VFREDUSUM_VS }, // 2581 |
| 23852 | { PseudoVFREDUSUM_VS_M2_E32, VFREDUSUM_VS }, // 2582 |
| 23853 | { PseudoVFREDUSUM_VS_M2_E32_MASK, VFREDUSUM_VS }, // 2583 |
| 23854 | { PseudoVFREDUSUM_VS_M2_E64, VFREDUSUM_VS }, // 2584 |
| 23855 | { PseudoVFREDUSUM_VS_M2_E64_MASK, VFREDUSUM_VS }, // 2585 |
| 23856 | { PseudoVFREDUSUM_VS_M4_E16, VFREDUSUM_VS }, // 2586 |
| 23857 | { PseudoVFREDUSUM_VS_M4_E16_MASK, VFREDUSUM_VS }, // 2587 |
| 23858 | { PseudoVFREDUSUM_VS_M4_E32, VFREDUSUM_VS }, // 2588 |
| 23859 | { PseudoVFREDUSUM_VS_M4_E32_MASK, VFREDUSUM_VS }, // 2589 |
| 23860 | { PseudoVFREDUSUM_VS_M4_E64, VFREDUSUM_VS }, // 2590 |
| 23861 | { PseudoVFREDUSUM_VS_M4_E64_MASK, VFREDUSUM_VS }, // 2591 |
| 23862 | { PseudoVFREDUSUM_VS_M8_E16, VFREDUSUM_VS }, // 2592 |
| 23863 | { PseudoVFREDUSUM_VS_M8_E16_MASK, VFREDUSUM_VS }, // 2593 |
| 23864 | { PseudoVFREDUSUM_VS_M8_E32, VFREDUSUM_VS }, // 2594 |
| 23865 | { PseudoVFREDUSUM_VS_M8_E32_MASK, VFREDUSUM_VS }, // 2595 |
| 23866 | { PseudoVFREDUSUM_VS_M8_E64, VFREDUSUM_VS }, // 2596 |
| 23867 | { PseudoVFREDUSUM_VS_M8_E64_MASK, VFREDUSUM_VS }, // 2597 |
| 23868 | { PseudoVFREDUSUM_VS_MF2_E16, VFREDUSUM_VS }, // 2598 |
| 23869 | { PseudoVFREDUSUM_VS_MF2_E16_MASK, VFREDUSUM_VS }, // 2599 |
| 23870 | { PseudoVFREDUSUM_VS_MF2_E32, VFREDUSUM_VS }, // 2600 |
| 23871 | { PseudoVFREDUSUM_VS_MF2_E32_MASK, VFREDUSUM_VS }, // 2601 |
| 23872 | { PseudoVFREDUSUM_VS_MF4_E16, VFREDUSUM_VS }, // 2602 |
| 23873 | { PseudoVFREDUSUM_VS_MF4_E16_MASK, VFREDUSUM_VS }, // 2603 |
| 23874 | { PseudoVFRSQRT7_V_M1_E16, VFRSQRT7_V }, // 2604 |
| 23875 | { PseudoVFRSQRT7_V_M1_E16_MASK, VFRSQRT7_V }, // 2605 |
| 23876 | { PseudoVFRSQRT7_V_M1_E32, VFRSQRT7_V }, // 2606 |
| 23877 | { PseudoVFRSQRT7_V_M1_E32_MASK, VFRSQRT7_V }, // 2607 |
| 23878 | { PseudoVFRSQRT7_V_M1_E64, VFRSQRT7_V }, // 2608 |
| 23879 | { PseudoVFRSQRT7_V_M1_E64_MASK, VFRSQRT7_V }, // 2609 |
| 23880 | { PseudoVFRSQRT7_V_M2_E16, VFRSQRT7_V }, // 2610 |
| 23881 | { PseudoVFRSQRT7_V_M2_E16_MASK, VFRSQRT7_V }, // 2611 |
| 23882 | { PseudoVFRSQRT7_V_M2_E32, VFRSQRT7_V }, // 2612 |
| 23883 | { PseudoVFRSQRT7_V_M2_E32_MASK, VFRSQRT7_V }, // 2613 |
| 23884 | { PseudoVFRSQRT7_V_M2_E64, VFRSQRT7_V }, // 2614 |
| 23885 | { PseudoVFRSQRT7_V_M2_E64_MASK, VFRSQRT7_V }, // 2615 |
| 23886 | { PseudoVFRSQRT7_V_M4_E16, VFRSQRT7_V }, // 2616 |
| 23887 | { PseudoVFRSQRT7_V_M4_E16_MASK, VFRSQRT7_V }, // 2617 |
| 23888 | { PseudoVFRSQRT7_V_M4_E32, VFRSQRT7_V }, // 2618 |
| 23889 | { PseudoVFRSQRT7_V_M4_E32_MASK, VFRSQRT7_V }, // 2619 |
| 23890 | { PseudoVFRSQRT7_V_M4_E64, VFRSQRT7_V }, // 2620 |
| 23891 | { PseudoVFRSQRT7_V_M4_E64_MASK, VFRSQRT7_V }, // 2621 |
| 23892 | { PseudoVFRSQRT7_V_M8_E16, VFRSQRT7_V }, // 2622 |
| 23893 | { PseudoVFRSQRT7_V_M8_E16_MASK, VFRSQRT7_V }, // 2623 |
| 23894 | { PseudoVFRSQRT7_V_M8_E32, VFRSQRT7_V }, // 2624 |
| 23895 | { PseudoVFRSQRT7_V_M8_E32_MASK, VFRSQRT7_V }, // 2625 |
| 23896 | { PseudoVFRSQRT7_V_M8_E64, VFRSQRT7_V }, // 2626 |
| 23897 | { PseudoVFRSQRT7_V_M8_E64_MASK, VFRSQRT7_V }, // 2627 |
| 23898 | { PseudoVFRSQRT7_V_MF2_E16, VFRSQRT7_V }, // 2628 |
| 23899 | { PseudoVFRSQRT7_V_MF2_E16_MASK, VFRSQRT7_V }, // 2629 |
| 23900 | { PseudoVFRSQRT7_V_MF2_E32, VFRSQRT7_V }, // 2630 |
| 23901 | { PseudoVFRSQRT7_V_MF2_E32_MASK, VFRSQRT7_V }, // 2631 |
| 23902 | { PseudoVFRSQRT7_V_MF4_E16, VFRSQRT7_V }, // 2632 |
| 23903 | { PseudoVFRSQRT7_V_MF4_E16_MASK, VFRSQRT7_V }, // 2633 |
| 23904 | { PseudoVFRSUB_VFPR16_M1_E16, VFRSUB_VF }, // 2634 |
| 23905 | { PseudoVFRSUB_VFPR16_M1_E16_MASK, VFRSUB_VF }, // 2635 |
| 23906 | { PseudoVFRSUB_VFPR16_M2_E16, VFRSUB_VF }, // 2636 |
| 23907 | { PseudoVFRSUB_VFPR16_M2_E16_MASK, VFRSUB_VF }, // 2637 |
| 23908 | { PseudoVFRSUB_VFPR16_M4_E16, VFRSUB_VF }, // 2638 |
| 23909 | { PseudoVFRSUB_VFPR16_M4_E16_MASK, VFRSUB_VF }, // 2639 |
| 23910 | { PseudoVFRSUB_VFPR16_M8_E16, VFRSUB_VF }, // 2640 |
| 23911 | { PseudoVFRSUB_VFPR16_M8_E16_MASK, VFRSUB_VF }, // 2641 |
| 23912 | { PseudoVFRSUB_VFPR16_MF2_E16, VFRSUB_VF }, // 2642 |
| 23913 | { PseudoVFRSUB_VFPR16_MF2_E16_MASK, VFRSUB_VF }, // 2643 |
| 23914 | { PseudoVFRSUB_VFPR16_MF4_E16, VFRSUB_VF }, // 2644 |
| 23915 | { PseudoVFRSUB_VFPR16_MF4_E16_MASK, VFRSUB_VF }, // 2645 |
| 23916 | { PseudoVFRSUB_VFPR32_M1_E32, VFRSUB_VF }, // 2646 |
| 23917 | { PseudoVFRSUB_VFPR32_M1_E32_MASK, VFRSUB_VF }, // 2647 |
| 23918 | { PseudoVFRSUB_VFPR32_M2_E32, VFRSUB_VF }, // 2648 |
| 23919 | { PseudoVFRSUB_VFPR32_M2_E32_MASK, VFRSUB_VF }, // 2649 |
| 23920 | { PseudoVFRSUB_VFPR32_M4_E32, VFRSUB_VF }, // 2650 |
| 23921 | { PseudoVFRSUB_VFPR32_M4_E32_MASK, VFRSUB_VF }, // 2651 |
| 23922 | { PseudoVFRSUB_VFPR32_M8_E32, VFRSUB_VF }, // 2652 |
| 23923 | { PseudoVFRSUB_VFPR32_M8_E32_MASK, VFRSUB_VF }, // 2653 |
| 23924 | { PseudoVFRSUB_VFPR32_MF2_E32, VFRSUB_VF }, // 2654 |
| 23925 | { PseudoVFRSUB_VFPR32_MF2_E32_MASK, VFRSUB_VF }, // 2655 |
| 23926 | { PseudoVFRSUB_VFPR64_M1_E64, VFRSUB_VF }, // 2656 |
| 23927 | { PseudoVFRSUB_VFPR64_M1_E64_MASK, VFRSUB_VF }, // 2657 |
| 23928 | { PseudoVFRSUB_VFPR64_M2_E64, VFRSUB_VF }, // 2658 |
| 23929 | { PseudoVFRSUB_VFPR64_M2_E64_MASK, VFRSUB_VF }, // 2659 |
| 23930 | { PseudoVFRSUB_VFPR64_M4_E64, VFRSUB_VF }, // 2660 |
| 23931 | { PseudoVFRSUB_VFPR64_M4_E64_MASK, VFRSUB_VF }, // 2661 |
| 23932 | { PseudoVFRSUB_VFPR64_M8_E64, VFRSUB_VF }, // 2662 |
| 23933 | { PseudoVFRSUB_VFPR64_M8_E64_MASK, VFRSUB_VF }, // 2663 |
| 23934 | { PseudoVFSGNJN_VFPR16_M1_E16, VFSGNJN_VF }, // 2664 |
| 23935 | { PseudoVFSGNJN_VFPR16_M1_E16_MASK, VFSGNJN_VF }, // 2665 |
| 23936 | { PseudoVFSGNJN_VFPR16_M2_E16, VFSGNJN_VF }, // 2666 |
| 23937 | { PseudoVFSGNJN_VFPR16_M2_E16_MASK, VFSGNJN_VF }, // 2667 |
| 23938 | { PseudoVFSGNJN_VFPR16_M4_E16, VFSGNJN_VF }, // 2668 |
| 23939 | { PseudoVFSGNJN_VFPR16_M4_E16_MASK, VFSGNJN_VF }, // 2669 |
| 23940 | { PseudoVFSGNJN_VFPR16_M8_E16, VFSGNJN_VF }, // 2670 |
| 23941 | { PseudoVFSGNJN_VFPR16_M8_E16_MASK, VFSGNJN_VF }, // 2671 |
| 23942 | { PseudoVFSGNJN_VFPR16_MF2_E16, VFSGNJN_VF }, // 2672 |
| 23943 | { PseudoVFSGNJN_VFPR16_MF2_E16_MASK, VFSGNJN_VF }, // 2673 |
| 23944 | { PseudoVFSGNJN_VFPR16_MF4_E16, VFSGNJN_VF }, // 2674 |
| 23945 | { PseudoVFSGNJN_VFPR16_MF4_E16_MASK, VFSGNJN_VF }, // 2675 |
| 23946 | { PseudoVFSGNJN_VFPR32_M1_E32, VFSGNJN_VF }, // 2676 |
| 23947 | { PseudoVFSGNJN_VFPR32_M1_E32_MASK, VFSGNJN_VF }, // 2677 |
| 23948 | { PseudoVFSGNJN_VFPR32_M2_E32, VFSGNJN_VF }, // 2678 |
| 23949 | { PseudoVFSGNJN_VFPR32_M2_E32_MASK, VFSGNJN_VF }, // 2679 |
| 23950 | { PseudoVFSGNJN_VFPR32_M4_E32, VFSGNJN_VF }, // 2680 |
| 23951 | { PseudoVFSGNJN_VFPR32_M4_E32_MASK, VFSGNJN_VF }, // 2681 |
| 23952 | { PseudoVFSGNJN_VFPR32_M8_E32, VFSGNJN_VF }, // 2682 |
| 23953 | { PseudoVFSGNJN_VFPR32_M8_E32_MASK, VFSGNJN_VF }, // 2683 |
| 23954 | { PseudoVFSGNJN_VFPR32_MF2_E32, VFSGNJN_VF }, // 2684 |
| 23955 | { PseudoVFSGNJN_VFPR32_MF2_E32_MASK, VFSGNJN_VF }, // 2685 |
| 23956 | { PseudoVFSGNJN_VFPR64_M1_E64, VFSGNJN_VF }, // 2686 |
| 23957 | { PseudoVFSGNJN_VFPR64_M1_E64_MASK, VFSGNJN_VF }, // 2687 |
| 23958 | { PseudoVFSGNJN_VFPR64_M2_E64, VFSGNJN_VF }, // 2688 |
| 23959 | { PseudoVFSGNJN_VFPR64_M2_E64_MASK, VFSGNJN_VF }, // 2689 |
| 23960 | { PseudoVFSGNJN_VFPR64_M4_E64, VFSGNJN_VF }, // 2690 |
| 23961 | { PseudoVFSGNJN_VFPR64_M4_E64_MASK, VFSGNJN_VF }, // 2691 |
| 23962 | { PseudoVFSGNJN_VFPR64_M8_E64, VFSGNJN_VF }, // 2692 |
| 23963 | { PseudoVFSGNJN_VFPR64_M8_E64_MASK, VFSGNJN_VF }, // 2693 |
| 23964 | { PseudoVFSGNJN_VV_M1_E16, VFSGNJN_VV }, // 2694 |
| 23965 | { PseudoVFSGNJN_VV_M1_E16_MASK, VFSGNJN_VV }, // 2695 |
| 23966 | { PseudoVFSGNJN_VV_M1_E32, VFSGNJN_VV }, // 2696 |
| 23967 | { PseudoVFSGNJN_VV_M1_E32_MASK, VFSGNJN_VV }, // 2697 |
| 23968 | { PseudoVFSGNJN_VV_M1_E64, VFSGNJN_VV }, // 2698 |
| 23969 | { PseudoVFSGNJN_VV_M1_E64_MASK, VFSGNJN_VV }, // 2699 |
| 23970 | { PseudoVFSGNJN_VV_M2_E16, VFSGNJN_VV }, // 2700 |
| 23971 | { PseudoVFSGNJN_VV_M2_E16_MASK, VFSGNJN_VV }, // 2701 |
| 23972 | { PseudoVFSGNJN_VV_M2_E32, VFSGNJN_VV }, // 2702 |
| 23973 | { PseudoVFSGNJN_VV_M2_E32_MASK, VFSGNJN_VV }, // 2703 |
| 23974 | { PseudoVFSGNJN_VV_M2_E64, VFSGNJN_VV }, // 2704 |
| 23975 | { PseudoVFSGNJN_VV_M2_E64_MASK, VFSGNJN_VV }, // 2705 |
| 23976 | { PseudoVFSGNJN_VV_M4_E16, VFSGNJN_VV }, // 2706 |
| 23977 | { PseudoVFSGNJN_VV_M4_E16_MASK, VFSGNJN_VV }, // 2707 |
| 23978 | { PseudoVFSGNJN_VV_M4_E32, VFSGNJN_VV }, // 2708 |
| 23979 | { PseudoVFSGNJN_VV_M4_E32_MASK, VFSGNJN_VV }, // 2709 |
| 23980 | { PseudoVFSGNJN_VV_M4_E64, VFSGNJN_VV }, // 2710 |
| 23981 | { PseudoVFSGNJN_VV_M4_E64_MASK, VFSGNJN_VV }, // 2711 |
| 23982 | { PseudoVFSGNJN_VV_M8_E16, VFSGNJN_VV }, // 2712 |
| 23983 | { PseudoVFSGNJN_VV_M8_E16_MASK, VFSGNJN_VV }, // 2713 |
| 23984 | { PseudoVFSGNJN_VV_M8_E32, VFSGNJN_VV }, // 2714 |
| 23985 | { PseudoVFSGNJN_VV_M8_E32_MASK, VFSGNJN_VV }, // 2715 |
| 23986 | { PseudoVFSGNJN_VV_M8_E64, VFSGNJN_VV }, // 2716 |
| 23987 | { PseudoVFSGNJN_VV_M8_E64_MASK, VFSGNJN_VV }, // 2717 |
| 23988 | { PseudoVFSGNJN_VV_MF2_E16, VFSGNJN_VV }, // 2718 |
| 23989 | { PseudoVFSGNJN_VV_MF2_E16_MASK, VFSGNJN_VV }, // 2719 |
| 23990 | { PseudoVFSGNJN_VV_MF2_E32, VFSGNJN_VV }, // 2720 |
| 23991 | { PseudoVFSGNJN_VV_MF2_E32_MASK, VFSGNJN_VV }, // 2721 |
| 23992 | { PseudoVFSGNJN_VV_MF4_E16, VFSGNJN_VV }, // 2722 |
| 23993 | { PseudoVFSGNJN_VV_MF4_E16_MASK, VFSGNJN_VV }, // 2723 |
| 23994 | { PseudoVFSGNJX_VFPR16_M1_E16, VFSGNJX_VF }, // 2724 |
| 23995 | { PseudoVFSGNJX_VFPR16_M1_E16_MASK, VFSGNJX_VF }, // 2725 |
| 23996 | { PseudoVFSGNJX_VFPR16_M2_E16, VFSGNJX_VF }, // 2726 |
| 23997 | { PseudoVFSGNJX_VFPR16_M2_E16_MASK, VFSGNJX_VF }, // 2727 |
| 23998 | { PseudoVFSGNJX_VFPR16_M4_E16, VFSGNJX_VF }, // 2728 |
| 23999 | { PseudoVFSGNJX_VFPR16_M4_E16_MASK, VFSGNJX_VF }, // 2729 |
| 24000 | { PseudoVFSGNJX_VFPR16_M8_E16, VFSGNJX_VF }, // 2730 |
| 24001 | { PseudoVFSGNJX_VFPR16_M8_E16_MASK, VFSGNJX_VF }, // 2731 |
| 24002 | { PseudoVFSGNJX_VFPR16_MF2_E16, VFSGNJX_VF }, // 2732 |
| 24003 | { PseudoVFSGNJX_VFPR16_MF2_E16_MASK, VFSGNJX_VF }, // 2733 |
| 24004 | { PseudoVFSGNJX_VFPR16_MF4_E16, VFSGNJX_VF }, // 2734 |
| 24005 | { PseudoVFSGNJX_VFPR16_MF4_E16_MASK, VFSGNJX_VF }, // 2735 |
| 24006 | { PseudoVFSGNJX_VFPR32_M1_E32, VFSGNJX_VF }, // 2736 |
| 24007 | { PseudoVFSGNJX_VFPR32_M1_E32_MASK, VFSGNJX_VF }, // 2737 |
| 24008 | { PseudoVFSGNJX_VFPR32_M2_E32, VFSGNJX_VF }, // 2738 |
| 24009 | { PseudoVFSGNJX_VFPR32_M2_E32_MASK, VFSGNJX_VF }, // 2739 |
| 24010 | { PseudoVFSGNJX_VFPR32_M4_E32, VFSGNJX_VF }, // 2740 |
| 24011 | { PseudoVFSGNJX_VFPR32_M4_E32_MASK, VFSGNJX_VF }, // 2741 |
| 24012 | { PseudoVFSGNJX_VFPR32_M8_E32, VFSGNJX_VF }, // 2742 |
| 24013 | { PseudoVFSGNJX_VFPR32_M8_E32_MASK, VFSGNJX_VF }, // 2743 |
| 24014 | { PseudoVFSGNJX_VFPR32_MF2_E32, VFSGNJX_VF }, // 2744 |
| 24015 | { PseudoVFSGNJX_VFPR32_MF2_E32_MASK, VFSGNJX_VF }, // 2745 |
| 24016 | { PseudoVFSGNJX_VFPR64_M1_E64, VFSGNJX_VF }, // 2746 |
| 24017 | { PseudoVFSGNJX_VFPR64_M1_E64_MASK, VFSGNJX_VF }, // 2747 |
| 24018 | { PseudoVFSGNJX_VFPR64_M2_E64, VFSGNJX_VF }, // 2748 |
| 24019 | { PseudoVFSGNJX_VFPR64_M2_E64_MASK, VFSGNJX_VF }, // 2749 |
| 24020 | { PseudoVFSGNJX_VFPR64_M4_E64, VFSGNJX_VF }, // 2750 |
| 24021 | { PseudoVFSGNJX_VFPR64_M4_E64_MASK, VFSGNJX_VF }, // 2751 |
| 24022 | { PseudoVFSGNJX_VFPR64_M8_E64, VFSGNJX_VF }, // 2752 |
| 24023 | { PseudoVFSGNJX_VFPR64_M8_E64_MASK, VFSGNJX_VF }, // 2753 |
| 24024 | { PseudoVFSGNJX_VV_M1_E16, VFSGNJX_VV }, // 2754 |
| 24025 | { PseudoVFSGNJX_VV_M1_E16_MASK, VFSGNJX_VV }, // 2755 |
| 24026 | { PseudoVFSGNJX_VV_M1_E32, VFSGNJX_VV }, // 2756 |
| 24027 | { PseudoVFSGNJX_VV_M1_E32_MASK, VFSGNJX_VV }, // 2757 |
| 24028 | { PseudoVFSGNJX_VV_M1_E64, VFSGNJX_VV }, // 2758 |
| 24029 | { PseudoVFSGNJX_VV_M1_E64_MASK, VFSGNJX_VV }, // 2759 |
| 24030 | { PseudoVFSGNJX_VV_M2_E16, VFSGNJX_VV }, // 2760 |
| 24031 | { PseudoVFSGNJX_VV_M2_E16_MASK, VFSGNJX_VV }, // 2761 |
| 24032 | { PseudoVFSGNJX_VV_M2_E32, VFSGNJX_VV }, // 2762 |
| 24033 | { PseudoVFSGNJX_VV_M2_E32_MASK, VFSGNJX_VV }, // 2763 |
| 24034 | { PseudoVFSGNJX_VV_M2_E64, VFSGNJX_VV }, // 2764 |
| 24035 | { PseudoVFSGNJX_VV_M2_E64_MASK, VFSGNJX_VV }, // 2765 |
| 24036 | { PseudoVFSGNJX_VV_M4_E16, VFSGNJX_VV }, // 2766 |
| 24037 | { PseudoVFSGNJX_VV_M4_E16_MASK, VFSGNJX_VV }, // 2767 |
| 24038 | { PseudoVFSGNJX_VV_M4_E32, VFSGNJX_VV }, // 2768 |
| 24039 | { PseudoVFSGNJX_VV_M4_E32_MASK, VFSGNJX_VV }, // 2769 |
| 24040 | { PseudoVFSGNJX_VV_M4_E64, VFSGNJX_VV }, // 2770 |
| 24041 | { PseudoVFSGNJX_VV_M4_E64_MASK, VFSGNJX_VV }, // 2771 |
| 24042 | { PseudoVFSGNJX_VV_M8_E16, VFSGNJX_VV }, // 2772 |
| 24043 | { PseudoVFSGNJX_VV_M8_E16_MASK, VFSGNJX_VV }, // 2773 |
| 24044 | { PseudoVFSGNJX_VV_M8_E32, VFSGNJX_VV }, // 2774 |
| 24045 | { PseudoVFSGNJX_VV_M8_E32_MASK, VFSGNJX_VV }, // 2775 |
| 24046 | { PseudoVFSGNJX_VV_M8_E64, VFSGNJX_VV }, // 2776 |
| 24047 | { PseudoVFSGNJX_VV_M8_E64_MASK, VFSGNJX_VV }, // 2777 |
| 24048 | { PseudoVFSGNJX_VV_MF2_E16, VFSGNJX_VV }, // 2778 |
| 24049 | { PseudoVFSGNJX_VV_MF2_E16_MASK, VFSGNJX_VV }, // 2779 |
| 24050 | { PseudoVFSGNJX_VV_MF2_E32, VFSGNJX_VV }, // 2780 |
| 24051 | { PseudoVFSGNJX_VV_MF2_E32_MASK, VFSGNJX_VV }, // 2781 |
| 24052 | { PseudoVFSGNJX_VV_MF4_E16, VFSGNJX_VV }, // 2782 |
| 24053 | { PseudoVFSGNJX_VV_MF4_E16_MASK, VFSGNJX_VV }, // 2783 |
| 24054 | { PseudoVFSGNJ_VFPR16_M1_E16, VFSGNJ_VF }, // 2784 |
| 24055 | { PseudoVFSGNJ_VFPR16_M1_E16_MASK, VFSGNJ_VF }, // 2785 |
| 24056 | { PseudoVFSGNJ_VFPR16_M2_E16, VFSGNJ_VF }, // 2786 |
| 24057 | { PseudoVFSGNJ_VFPR16_M2_E16_MASK, VFSGNJ_VF }, // 2787 |
| 24058 | { PseudoVFSGNJ_VFPR16_M4_E16, VFSGNJ_VF }, // 2788 |
| 24059 | { PseudoVFSGNJ_VFPR16_M4_E16_MASK, VFSGNJ_VF }, // 2789 |
| 24060 | { PseudoVFSGNJ_VFPR16_M8_E16, VFSGNJ_VF }, // 2790 |
| 24061 | { PseudoVFSGNJ_VFPR16_M8_E16_MASK, VFSGNJ_VF }, // 2791 |
| 24062 | { PseudoVFSGNJ_VFPR16_MF2_E16, VFSGNJ_VF }, // 2792 |
| 24063 | { PseudoVFSGNJ_VFPR16_MF2_E16_MASK, VFSGNJ_VF }, // 2793 |
| 24064 | { PseudoVFSGNJ_VFPR16_MF4_E16, VFSGNJ_VF }, // 2794 |
| 24065 | { PseudoVFSGNJ_VFPR16_MF4_E16_MASK, VFSGNJ_VF }, // 2795 |
| 24066 | { PseudoVFSGNJ_VFPR32_M1_E32, VFSGNJ_VF }, // 2796 |
| 24067 | { PseudoVFSGNJ_VFPR32_M1_E32_MASK, VFSGNJ_VF }, // 2797 |
| 24068 | { PseudoVFSGNJ_VFPR32_M2_E32, VFSGNJ_VF }, // 2798 |
| 24069 | { PseudoVFSGNJ_VFPR32_M2_E32_MASK, VFSGNJ_VF }, // 2799 |
| 24070 | { PseudoVFSGNJ_VFPR32_M4_E32, VFSGNJ_VF }, // 2800 |
| 24071 | { PseudoVFSGNJ_VFPR32_M4_E32_MASK, VFSGNJ_VF }, // 2801 |
| 24072 | { PseudoVFSGNJ_VFPR32_M8_E32, VFSGNJ_VF }, // 2802 |
| 24073 | { PseudoVFSGNJ_VFPR32_M8_E32_MASK, VFSGNJ_VF }, // 2803 |
| 24074 | { PseudoVFSGNJ_VFPR32_MF2_E32, VFSGNJ_VF }, // 2804 |
| 24075 | { PseudoVFSGNJ_VFPR32_MF2_E32_MASK, VFSGNJ_VF }, // 2805 |
| 24076 | { PseudoVFSGNJ_VFPR64_M1_E64, VFSGNJ_VF }, // 2806 |
| 24077 | { PseudoVFSGNJ_VFPR64_M1_E64_MASK, VFSGNJ_VF }, // 2807 |
| 24078 | { PseudoVFSGNJ_VFPR64_M2_E64, VFSGNJ_VF }, // 2808 |
| 24079 | { PseudoVFSGNJ_VFPR64_M2_E64_MASK, VFSGNJ_VF }, // 2809 |
| 24080 | { PseudoVFSGNJ_VFPR64_M4_E64, VFSGNJ_VF }, // 2810 |
| 24081 | { PseudoVFSGNJ_VFPR64_M4_E64_MASK, VFSGNJ_VF }, // 2811 |
| 24082 | { PseudoVFSGNJ_VFPR64_M8_E64, VFSGNJ_VF }, // 2812 |
| 24083 | { PseudoVFSGNJ_VFPR64_M8_E64_MASK, VFSGNJ_VF }, // 2813 |
| 24084 | { PseudoVFSGNJ_VV_M1_E16, VFSGNJ_VV }, // 2814 |
| 24085 | { PseudoVFSGNJ_VV_M1_E16_MASK, VFSGNJ_VV }, // 2815 |
| 24086 | { PseudoVFSGNJ_VV_M1_E32, VFSGNJ_VV }, // 2816 |
| 24087 | { PseudoVFSGNJ_VV_M1_E32_MASK, VFSGNJ_VV }, // 2817 |
| 24088 | { PseudoVFSGNJ_VV_M1_E64, VFSGNJ_VV }, // 2818 |
| 24089 | { PseudoVFSGNJ_VV_M1_E64_MASK, VFSGNJ_VV }, // 2819 |
| 24090 | { PseudoVFSGNJ_VV_M2_E16, VFSGNJ_VV }, // 2820 |
| 24091 | { PseudoVFSGNJ_VV_M2_E16_MASK, VFSGNJ_VV }, // 2821 |
| 24092 | { PseudoVFSGNJ_VV_M2_E32, VFSGNJ_VV }, // 2822 |
| 24093 | { PseudoVFSGNJ_VV_M2_E32_MASK, VFSGNJ_VV }, // 2823 |
| 24094 | { PseudoVFSGNJ_VV_M2_E64, VFSGNJ_VV }, // 2824 |
| 24095 | { PseudoVFSGNJ_VV_M2_E64_MASK, VFSGNJ_VV }, // 2825 |
| 24096 | { PseudoVFSGNJ_VV_M4_E16, VFSGNJ_VV }, // 2826 |
| 24097 | { PseudoVFSGNJ_VV_M4_E16_MASK, VFSGNJ_VV }, // 2827 |
| 24098 | { PseudoVFSGNJ_VV_M4_E32, VFSGNJ_VV }, // 2828 |
| 24099 | { PseudoVFSGNJ_VV_M4_E32_MASK, VFSGNJ_VV }, // 2829 |
| 24100 | { PseudoVFSGNJ_VV_M4_E64, VFSGNJ_VV }, // 2830 |
| 24101 | { PseudoVFSGNJ_VV_M4_E64_MASK, VFSGNJ_VV }, // 2831 |
| 24102 | { PseudoVFSGNJ_VV_M8_E16, VFSGNJ_VV }, // 2832 |
| 24103 | { PseudoVFSGNJ_VV_M8_E16_MASK, VFSGNJ_VV }, // 2833 |
| 24104 | { PseudoVFSGNJ_VV_M8_E32, VFSGNJ_VV }, // 2834 |
| 24105 | { PseudoVFSGNJ_VV_M8_E32_MASK, VFSGNJ_VV }, // 2835 |
| 24106 | { PseudoVFSGNJ_VV_M8_E64, VFSGNJ_VV }, // 2836 |
| 24107 | { PseudoVFSGNJ_VV_M8_E64_MASK, VFSGNJ_VV }, // 2837 |
| 24108 | { PseudoVFSGNJ_VV_MF2_E16, VFSGNJ_VV }, // 2838 |
| 24109 | { PseudoVFSGNJ_VV_MF2_E16_MASK, VFSGNJ_VV }, // 2839 |
| 24110 | { PseudoVFSGNJ_VV_MF2_E32, VFSGNJ_VV }, // 2840 |
| 24111 | { PseudoVFSGNJ_VV_MF2_E32_MASK, VFSGNJ_VV }, // 2841 |
| 24112 | { PseudoVFSGNJ_VV_MF4_E16, VFSGNJ_VV }, // 2842 |
| 24113 | { PseudoVFSGNJ_VV_MF4_E16_MASK, VFSGNJ_VV }, // 2843 |
| 24114 | { PseudoVFSLIDE1DOWN_VFPR16_M1, VFSLIDE1DOWN_VF }, // 2844 |
| 24115 | { PseudoVFSLIDE1DOWN_VFPR16_M1_MASK, VFSLIDE1DOWN_VF }, // 2845 |
| 24116 | { PseudoVFSLIDE1DOWN_VFPR16_M2, VFSLIDE1DOWN_VF }, // 2846 |
| 24117 | { PseudoVFSLIDE1DOWN_VFPR16_M2_MASK, VFSLIDE1DOWN_VF }, // 2847 |
| 24118 | { PseudoVFSLIDE1DOWN_VFPR16_M4, VFSLIDE1DOWN_VF }, // 2848 |
| 24119 | { PseudoVFSLIDE1DOWN_VFPR16_M4_MASK, VFSLIDE1DOWN_VF }, // 2849 |
| 24120 | { PseudoVFSLIDE1DOWN_VFPR16_M8, VFSLIDE1DOWN_VF }, // 2850 |
| 24121 | { PseudoVFSLIDE1DOWN_VFPR16_M8_MASK, VFSLIDE1DOWN_VF }, // 2851 |
| 24122 | { PseudoVFSLIDE1DOWN_VFPR16_MF2, VFSLIDE1DOWN_VF }, // 2852 |
| 24123 | { PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK, VFSLIDE1DOWN_VF }, // 2853 |
| 24124 | { PseudoVFSLIDE1DOWN_VFPR16_MF4, VFSLIDE1DOWN_VF }, // 2854 |
| 24125 | { PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK, VFSLIDE1DOWN_VF }, // 2855 |
| 24126 | { PseudoVFSLIDE1DOWN_VFPR32_M1, VFSLIDE1DOWN_VF }, // 2856 |
| 24127 | { PseudoVFSLIDE1DOWN_VFPR32_M1_MASK, VFSLIDE1DOWN_VF }, // 2857 |
| 24128 | { PseudoVFSLIDE1DOWN_VFPR32_M2, VFSLIDE1DOWN_VF }, // 2858 |
| 24129 | { PseudoVFSLIDE1DOWN_VFPR32_M2_MASK, VFSLIDE1DOWN_VF }, // 2859 |
| 24130 | { PseudoVFSLIDE1DOWN_VFPR32_M4, VFSLIDE1DOWN_VF }, // 2860 |
| 24131 | { PseudoVFSLIDE1DOWN_VFPR32_M4_MASK, VFSLIDE1DOWN_VF }, // 2861 |
| 24132 | { PseudoVFSLIDE1DOWN_VFPR32_M8, VFSLIDE1DOWN_VF }, // 2862 |
| 24133 | { PseudoVFSLIDE1DOWN_VFPR32_M8_MASK, VFSLIDE1DOWN_VF }, // 2863 |
| 24134 | { PseudoVFSLIDE1DOWN_VFPR32_MF2, VFSLIDE1DOWN_VF }, // 2864 |
| 24135 | { PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK, VFSLIDE1DOWN_VF }, // 2865 |
| 24136 | { PseudoVFSLIDE1DOWN_VFPR64_M1, VFSLIDE1DOWN_VF }, // 2866 |
| 24137 | { PseudoVFSLIDE1DOWN_VFPR64_M1_MASK, VFSLIDE1DOWN_VF }, // 2867 |
| 24138 | { PseudoVFSLIDE1DOWN_VFPR64_M2, VFSLIDE1DOWN_VF }, // 2868 |
| 24139 | { PseudoVFSLIDE1DOWN_VFPR64_M2_MASK, VFSLIDE1DOWN_VF }, // 2869 |
| 24140 | { PseudoVFSLIDE1DOWN_VFPR64_M4, VFSLIDE1DOWN_VF }, // 2870 |
| 24141 | { PseudoVFSLIDE1DOWN_VFPR64_M4_MASK, VFSLIDE1DOWN_VF }, // 2871 |
| 24142 | { PseudoVFSLIDE1DOWN_VFPR64_M8, VFSLIDE1DOWN_VF }, // 2872 |
| 24143 | { PseudoVFSLIDE1DOWN_VFPR64_M8_MASK, VFSLIDE1DOWN_VF }, // 2873 |
| 24144 | { PseudoVFSLIDE1UP_VFPR16_M1, VFSLIDE1UP_VF }, // 2874 |
| 24145 | { PseudoVFSLIDE1UP_VFPR16_M1_MASK, VFSLIDE1UP_VF }, // 2875 |
| 24146 | { PseudoVFSLIDE1UP_VFPR16_M2, VFSLIDE1UP_VF }, // 2876 |
| 24147 | { PseudoVFSLIDE1UP_VFPR16_M2_MASK, VFSLIDE1UP_VF }, // 2877 |
| 24148 | { PseudoVFSLIDE1UP_VFPR16_M4, VFSLIDE1UP_VF }, // 2878 |
| 24149 | { PseudoVFSLIDE1UP_VFPR16_M4_MASK, VFSLIDE1UP_VF }, // 2879 |
| 24150 | { PseudoVFSLIDE1UP_VFPR16_M8, VFSLIDE1UP_VF }, // 2880 |
| 24151 | { PseudoVFSLIDE1UP_VFPR16_M8_MASK, VFSLIDE1UP_VF }, // 2881 |
| 24152 | { PseudoVFSLIDE1UP_VFPR16_MF2, VFSLIDE1UP_VF }, // 2882 |
| 24153 | { PseudoVFSLIDE1UP_VFPR16_MF2_MASK, VFSLIDE1UP_VF }, // 2883 |
| 24154 | { PseudoVFSLIDE1UP_VFPR16_MF4, VFSLIDE1UP_VF }, // 2884 |
| 24155 | { PseudoVFSLIDE1UP_VFPR16_MF4_MASK, VFSLIDE1UP_VF }, // 2885 |
| 24156 | { PseudoVFSLIDE1UP_VFPR32_M1, VFSLIDE1UP_VF }, // 2886 |
| 24157 | { PseudoVFSLIDE1UP_VFPR32_M1_MASK, VFSLIDE1UP_VF }, // 2887 |
| 24158 | { PseudoVFSLIDE1UP_VFPR32_M2, VFSLIDE1UP_VF }, // 2888 |
| 24159 | { PseudoVFSLIDE1UP_VFPR32_M2_MASK, VFSLIDE1UP_VF }, // 2889 |
| 24160 | { PseudoVFSLIDE1UP_VFPR32_M4, VFSLIDE1UP_VF }, // 2890 |
| 24161 | { PseudoVFSLIDE1UP_VFPR32_M4_MASK, VFSLIDE1UP_VF }, // 2891 |
| 24162 | { PseudoVFSLIDE1UP_VFPR32_M8, VFSLIDE1UP_VF }, // 2892 |
| 24163 | { PseudoVFSLIDE1UP_VFPR32_M8_MASK, VFSLIDE1UP_VF }, // 2893 |
| 24164 | { PseudoVFSLIDE1UP_VFPR32_MF2, VFSLIDE1UP_VF }, // 2894 |
| 24165 | { PseudoVFSLIDE1UP_VFPR32_MF2_MASK, VFSLIDE1UP_VF }, // 2895 |
| 24166 | { PseudoVFSLIDE1UP_VFPR64_M1, VFSLIDE1UP_VF }, // 2896 |
| 24167 | { PseudoVFSLIDE1UP_VFPR64_M1_MASK, VFSLIDE1UP_VF }, // 2897 |
| 24168 | { PseudoVFSLIDE1UP_VFPR64_M2, VFSLIDE1UP_VF }, // 2898 |
| 24169 | { PseudoVFSLIDE1UP_VFPR64_M2_MASK, VFSLIDE1UP_VF }, // 2899 |
| 24170 | { PseudoVFSLIDE1UP_VFPR64_M4, VFSLIDE1UP_VF }, // 2900 |
| 24171 | { PseudoVFSLIDE1UP_VFPR64_M4_MASK, VFSLIDE1UP_VF }, // 2901 |
| 24172 | { PseudoVFSLIDE1UP_VFPR64_M8, VFSLIDE1UP_VF }, // 2902 |
| 24173 | { PseudoVFSLIDE1UP_VFPR64_M8_MASK, VFSLIDE1UP_VF }, // 2903 |
| 24174 | { PseudoVFSQRT_V_M1_E16, VFSQRT_V }, // 2904 |
| 24175 | { PseudoVFSQRT_V_M1_E16_MASK, VFSQRT_V }, // 2905 |
| 24176 | { PseudoVFSQRT_V_M1_E32, VFSQRT_V }, // 2906 |
| 24177 | { PseudoVFSQRT_V_M1_E32_MASK, VFSQRT_V }, // 2907 |
| 24178 | { PseudoVFSQRT_V_M1_E64, VFSQRT_V }, // 2908 |
| 24179 | { PseudoVFSQRT_V_M1_E64_MASK, VFSQRT_V }, // 2909 |
| 24180 | { PseudoVFSQRT_V_M2_E16, VFSQRT_V }, // 2910 |
| 24181 | { PseudoVFSQRT_V_M2_E16_MASK, VFSQRT_V }, // 2911 |
| 24182 | { PseudoVFSQRT_V_M2_E32, VFSQRT_V }, // 2912 |
| 24183 | { PseudoVFSQRT_V_M2_E32_MASK, VFSQRT_V }, // 2913 |
| 24184 | { PseudoVFSQRT_V_M2_E64, VFSQRT_V }, // 2914 |
| 24185 | { PseudoVFSQRT_V_M2_E64_MASK, VFSQRT_V }, // 2915 |
| 24186 | { PseudoVFSQRT_V_M4_E16, VFSQRT_V }, // 2916 |
| 24187 | { PseudoVFSQRT_V_M4_E16_MASK, VFSQRT_V }, // 2917 |
| 24188 | { PseudoVFSQRT_V_M4_E32, VFSQRT_V }, // 2918 |
| 24189 | { PseudoVFSQRT_V_M4_E32_MASK, VFSQRT_V }, // 2919 |
| 24190 | { PseudoVFSQRT_V_M4_E64, VFSQRT_V }, // 2920 |
| 24191 | { PseudoVFSQRT_V_M4_E64_MASK, VFSQRT_V }, // 2921 |
| 24192 | { PseudoVFSQRT_V_M8_E16, VFSQRT_V }, // 2922 |
| 24193 | { PseudoVFSQRT_V_M8_E16_MASK, VFSQRT_V }, // 2923 |
| 24194 | { PseudoVFSQRT_V_M8_E32, VFSQRT_V }, // 2924 |
| 24195 | { PseudoVFSQRT_V_M8_E32_MASK, VFSQRT_V }, // 2925 |
| 24196 | { PseudoVFSQRT_V_M8_E64, VFSQRT_V }, // 2926 |
| 24197 | { PseudoVFSQRT_V_M8_E64_MASK, VFSQRT_V }, // 2927 |
| 24198 | { PseudoVFSQRT_V_MF2_E16, VFSQRT_V }, // 2928 |
| 24199 | { PseudoVFSQRT_V_MF2_E16_MASK, VFSQRT_V }, // 2929 |
| 24200 | { PseudoVFSQRT_V_MF2_E32, VFSQRT_V }, // 2930 |
| 24201 | { PseudoVFSQRT_V_MF2_E32_MASK, VFSQRT_V }, // 2931 |
| 24202 | { PseudoVFSQRT_V_MF4_E16, VFSQRT_V }, // 2932 |
| 24203 | { PseudoVFSQRT_V_MF4_E16_MASK, VFSQRT_V }, // 2933 |
| 24204 | { PseudoVFSUB_VFPR16_M1_E16, VFSUB_VF }, // 2934 |
| 24205 | { PseudoVFSUB_VFPR16_M1_E16_MASK, VFSUB_VF }, // 2935 |
| 24206 | { PseudoVFSUB_VFPR16_M2_E16, VFSUB_VF }, // 2936 |
| 24207 | { PseudoVFSUB_VFPR16_M2_E16_MASK, VFSUB_VF }, // 2937 |
| 24208 | { PseudoVFSUB_VFPR16_M4_E16, VFSUB_VF }, // 2938 |
| 24209 | { PseudoVFSUB_VFPR16_M4_E16_MASK, VFSUB_VF }, // 2939 |
| 24210 | { PseudoVFSUB_VFPR16_M8_E16, VFSUB_VF }, // 2940 |
| 24211 | { PseudoVFSUB_VFPR16_M8_E16_MASK, VFSUB_VF }, // 2941 |
| 24212 | { PseudoVFSUB_VFPR16_MF2_E16, VFSUB_VF }, // 2942 |
| 24213 | { PseudoVFSUB_VFPR16_MF2_E16_MASK, VFSUB_VF }, // 2943 |
| 24214 | { PseudoVFSUB_VFPR16_MF4_E16, VFSUB_VF }, // 2944 |
| 24215 | { PseudoVFSUB_VFPR16_MF4_E16_MASK, VFSUB_VF }, // 2945 |
| 24216 | { PseudoVFSUB_VFPR32_M1_E32, VFSUB_VF }, // 2946 |
| 24217 | { PseudoVFSUB_VFPR32_M1_E32_MASK, VFSUB_VF }, // 2947 |
| 24218 | { PseudoVFSUB_VFPR32_M2_E32, VFSUB_VF }, // 2948 |
| 24219 | { PseudoVFSUB_VFPR32_M2_E32_MASK, VFSUB_VF }, // 2949 |
| 24220 | { PseudoVFSUB_VFPR32_M4_E32, VFSUB_VF }, // 2950 |
| 24221 | { PseudoVFSUB_VFPR32_M4_E32_MASK, VFSUB_VF }, // 2951 |
| 24222 | { PseudoVFSUB_VFPR32_M8_E32, VFSUB_VF }, // 2952 |
| 24223 | { PseudoVFSUB_VFPR32_M8_E32_MASK, VFSUB_VF }, // 2953 |
| 24224 | { PseudoVFSUB_VFPR32_MF2_E32, VFSUB_VF }, // 2954 |
| 24225 | { PseudoVFSUB_VFPR32_MF2_E32_MASK, VFSUB_VF }, // 2955 |
| 24226 | { PseudoVFSUB_VFPR64_M1_E64, VFSUB_VF }, // 2956 |
| 24227 | { PseudoVFSUB_VFPR64_M1_E64_MASK, VFSUB_VF }, // 2957 |
| 24228 | { PseudoVFSUB_VFPR64_M2_E64, VFSUB_VF }, // 2958 |
| 24229 | { PseudoVFSUB_VFPR64_M2_E64_MASK, VFSUB_VF }, // 2959 |
| 24230 | { PseudoVFSUB_VFPR64_M4_E64, VFSUB_VF }, // 2960 |
| 24231 | { PseudoVFSUB_VFPR64_M4_E64_MASK, VFSUB_VF }, // 2961 |
| 24232 | { PseudoVFSUB_VFPR64_M8_E64, VFSUB_VF }, // 2962 |
| 24233 | { PseudoVFSUB_VFPR64_M8_E64_MASK, VFSUB_VF }, // 2963 |
| 24234 | { PseudoVFSUB_VV_M1_E16, VFSUB_VV }, // 2964 |
| 24235 | { PseudoVFSUB_VV_M1_E16_MASK, VFSUB_VV }, // 2965 |
| 24236 | { PseudoVFSUB_VV_M1_E32, VFSUB_VV }, // 2966 |
| 24237 | { PseudoVFSUB_VV_M1_E32_MASK, VFSUB_VV }, // 2967 |
| 24238 | { PseudoVFSUB_VV_M1_E64, VFSUB_VV }, // 2968 |
| 24239 | { PseudoVFSUB_VV_M1_E64_MASK, VFSUB_VV }, // 2969 |
| 24240 | { PseudoVFSUB_VV_M2_E16, VFSUB_VV }, // 2970 |
| 24241 | { PseudoVFSUB_VV_M2_E16_MASK, VFSUB_VV }, // 2971 |
| 24242 | { PseudoVFSUB_VV_M2_E32, VFSUB_VV }, // 2972 |
| 24243 | { PseudoVFSUB_VV_M2_E32_MASK, VFSUB_VV }, // 2973 |
| 24244 | { PseudoVFSUB_VV_M2_E64, VFSUB_VV }, // 2974 |
| 24245 | { PseudoVFSUB_VV_M2_E64_MASK, VFSUB_VV }, // 2975 |
| 24246 | { PseudoVFSUB_VV_M4_E16, VFSUB_VV }, // 2976 |
| 24247 | { PseudoVFSUB_VV_M4_E16_MASK, VFSUB_VV }, // 2977 |
| 24248 | { PseudoVFSUB_VV_M4_E32, VFSUB_VV }, // 2978 |
| 24249 | { PseudoVFSUB_VV_M4_E32_MASK, VFSUB_VV }, // 2979 |
| 24250 | { PseudoVFSUB_VV_M4_E64, VFSUB_VV }, // 2980 |
| 24251 | { PseudoVFSUB_VV_M4_E64_MASK, VFSUB_VV }, // 2981 |
| 24252 | { PseudoVFSUB_VV_M8_E16, VFSUB_VV }, // 2982 |
| 24253 | { PseudoVFSUB_VV_M8_E16_MASK, VFSUB_VV }, // 2983 |
| 24254 | { PseudoVFSUB_VV_M8_E32, VFSUB_VV }, // 2984 |
| 24255 | { PseudoVFSUB_VV_M8_E32_MASK, VFSUB_VV }, // 2985 |
| 24256 | { PseudoVFSUB_VV_M8_E64, VFSUB_VV }, // 2986 |
| 24257 | { PseudoVFSUB_VV_M8_E64_MASK, VFSUB_VV }, // 2987 |
| 24258 | { PseudoVFSUB_VV_MF2_E16, VFSUB_VV }, // 2988 |
| 24259 | { PseudoVFSUB_VV_MF2_E16_MASK, VFSUB_VV }, // 2989 |
| 24260 | { PseudoVFSUB_VV_MF2_E32, VFSUB_VV }, // 2990 |
| 24261 | { PseudoVFSUB_VV_MF2_E32_MASK, VFSUB_VV }, // 2991 |
| 24262 | { PseudoVFSUB_VV_MF4_E16, VFSUB_VV }, // 2992 |
| 24263 | { PseudoVFSUB_VV_MF4_E16_MASK, VFSUB_VV }, // 2993 |
| 24264 | { PseudoVFWADD_VFPR16_M1_E16, VFWADD_VF }, // 2994 |
| 24265 | { PseudoVFWADD_VFPR16_M1_E16_MASK, VFWADD_VF }, // 2995 |
| 24266 | { PseudoVFWADD_VFPR16_M2_E16, VFWADD_VF }, // 2996 |
| 24267 | { PseudoVFWADD_VFPR16_M2_E16_MASK, VFWADD_VF }, // 2997 |
| 24268 | { PseudoVFWADD_VFPR16_M4_E16, VFWADD_VF }, // 2998 |
| 24269 | { PseudoVFWADD_VFPR16_M4_E16_MASK, VFWADD_VF }, // 2999 |
| 24270 | { PseudoVFWADD_VFPR16_MF2_E16, VFWADD_VF }, // 3000 |
| 24271 | { PseudoVFWADD_VFPR16_MF2_E16_MASK, VFWADD_VF }, // 3001 |
| 24272 | { PseudoVFWADD_VFPR16_MF4_E16, VFWADD_VF }, // 3002 |
| 24273 | { PseudoVFWADD_VFPR16_MF4_E16_MASK, VFWADD_VF }, // 3003 |
| 24274 | { PseudoVFWADD_VFPR32_M1_E32, VFWADD_VF }, // 3004 |
| 24275 | { PseudoVFWADD_VFPR32_M1_E32_MASK, VFWADD_VF }, // 3005 |
| 24276 | { PseudoVFWADD_VFPR32_M2_E32, VFWADD_VF }, // 3006 |
| 24277 | { PseudoVFWADD_VFPR32_M2_E32_MASK, VFWADD_VF }, // 3007 |
| 24278 | { PseudoVFWADD_VFPR32_M4_E32, VFWADD_VF }, // 3008 |
| 24279 | { PseudoVFWADD_VFPR32_M4_E32_MASK, VFWADD_VF }, // 3009 |
| 24280 | { PseudoVFWADD_VFPR32_MF2_E32, VFWADD_VF }, // 3010 |
| 24281 | { PseudoVFWADD_VFPR32_MF2_E32_MASK, VFWADD_VF }, // 3011 |
| 24282 | { PseudoVFWADD_VV_M1_E16, VFWADD_VV }, // 3012 |
| 24283 | { PseudoVFWADD_VV_M1_E16_MASK, VFWADD_VV }, // 3013 |
| 24284 | { PseudoVFWADD_VV_M1_E32, VFWADD_VV }, // 3014 |
| 24285 | { PseudoVFWADD_VV_M1_E32_MASK, VFWADD_VV }, // 3015 |
| 24286 | { PseudoVFWADD_VV_M2_E16, VFWADD_VV }, // 3016 |
| 24287 | { PseudoVFWADD_VV_M2_E16_MASK, VFWADD_VV }, // 3017 |
| 24288 | { PseudoVFWADD_VV_M2_E32, VFWADD_VV }, // 3018 |
| 24289 | { PseudoVFWADD_VV_M2_E32_MASK, VFWADD_VV }, // 3019 |
| 24290 | { PseudoVFWADD_VV_M4_E16, VFWADD_VV }, // 3020 |
| 24291 | { PseudoVFWADD_VV_M4_E16_MASK, VFWADD_VV }, // 3021 |
| 24292 | { PseudoVFWADD_VV_M4_E32, VFWADD_VV }, // 3022 |
| 24293 | { PseudoVFWADD_VV_M4_E32_MASK, VFWADD_VV }, // 3023 |
| 24294 | { PseudoVFWADD_VV_MF2_E16, VFWADD_VV }, // 3024 |
| 24295 | { PseudoVFWADD_VV_MF2_E16_MASK, VFWADD_VV }, // 3025 |
| 24296 | { PseudoVFWADD_VV_MF2_E32, VFWADD_VV }, // 3026 |
| 24297 | { PseudoVFWADD_VV_MF2_E32_MASK, VFWADD_VV }, // 3027 |
| 24298 | { PseudoVFWADD_VV_MF4_E16, VFWADD_VV }, // 3028 |
| 24299 | { PseudoVFWADD_VV_MF4_E16_MASK, VFWADD_VV }, // 3029 |
| 24300 | { PseudoVFWADD_WFPR16_M1_E16, VFWADD_WF }, // 3030 |
| 24301 | { PseudoVFWADD_WFPR16_M1_E16_MASK, VFWADD_WF }, // 3031 |
| 24302 | { PseudoVFWADD_WFPR16_M2_E16, VFWADD_WF }, // 3032 |
| 24303 | { PseudoVFWADD_WFPR16_M2_E16_MASK, VFWADD_WF }, // 3033 |
| 24304 | { PseudoVFWADD_WFPR16_M4_E16, VFWADD_WF }, // 3034 |
| 24305 | { PseudoVFWADD_WFPR16_M4_E16_MASK, VFWADD_WF }, // 3035 |
| 24306 | { PseudoVFWADD_WFPR16_MF2_E16, VFWADD_WF }, // 3036 |
| 24307 | { PseudoVFWADD_WFPR16_MF2_E16_MASK, VFWADD_WF }, // 3037 |
| 24308 | { PseudoVFWADD_WFPR16_MF4_E16, VFWADD_WF }, // 3038 |
| 24309 | { PseudoVFWADD_WFPR16_MF4_E16_MASK, VFWADD_WF }, // 3039 |
| 24310 | { PseudoVFWADD_WFPR32_M1_E32, VFWADD_WF }, // 3040 |
| 24311 | { PseudoVFWADD_WFPR32_M1_E32_MASK, VFWADD_WF }, // 3041 |
| 24312 | { PseudoVFWADD_WFPR32_M2_E32, VFWADD_WF }, // 3042 |
| 24313 | { PseudoVFWADD_WFPR32_M2_E32_MASK, VFWADD_WF }, // 3043 |
| 24314 | { PseudoVFWADD_WFPR32_M4_E32, VFWADD_WF }, // 3044 |
| 24315 | { PseudoVFWADD_WFPR32_M4_E32_MASK, VFWADD_WF }, // 3045 |
| 24316 | { PseudoVFWADD_WFPR32_MF2_E32, VFWADD_WF }, // 3046 |
| 24317 | { PseudoVFWADD_WFPR32_MF2_E32_MASK, VFWADD_WF }, // 3047 |
| 24318 | { PseudoVFWADD_WV_M1_E16, VFWADD_WV }, // 3048 |
| 24319 | { PseudoVFWADD_WV_M1_E16_MASK, VFWADD_WV }, // 3049 |
| 24320 | { PseudoVFWADD_WV_M1_E16_MASK_TIED, VFWADD_WV }, // 3050 |
| 24321 | { PseudoVFWADD_WV_M1_E16_TIED, VFWADD_WV }, // 3051 |
| 24322 | { PseudoVFWADD_WV_M1_E32, VFWADD_WV }, // 3052 |
| 24323 | { PseudoVFWADD_WV_M1_E32_MASK, VFWADD_WV }, // 3053 |
| 24324 | { PseudoVFWADD_WV_M1_E32_MASK_TIED, VFWADD_WV }, // 3054 |
| 24325 | { PseudoVFWADD_WV_M1_E32_TIED, VFWADD_WV }, // 3055 |
| 24326 | { PseudoVFWADD_WV_M2_E16, VFWADD_WV }, // 3056 |
| 24327 | { PseudoVFWADD_WV_M2_E16_MASK, VFWADD_WV }, // 3057 |
| 24328 | { PseudoVFWADD_WV_M2_E16_MASK_TIED, VFWADD_WV }, // 3058 |
| 24329 | { PseudoVFWADD_WV_M2_E16_TIED, VFWADD_WV }, // 3059 |
| 24330 | { PseudoVFWADD_WV_M2_E32, VFWADD_WV }, // 3060 |
| 24331 | { PseudoVFWADD_WV_M2_E32_MASK, VFWADD_WV }, // 3061 |
| 24332 | { PseudoVFWADD_WV_M2_E32_MASK_TIED, VFWADD_WV }, // 3062 |
| 24333 | { PseudoVFWADD_WV_M2_E32_TIED, VFWADD_WV }, // 3063 |
| 24334 | { PseudoVFWADD_WV_M4_E16, VFWADD_WV }, // 3064 |
| 24335 | { PseudoVFWADD_WV_M4_E16_MASK, VFWADD_WV }, // 3065 |
| 24336 | { PseudoVFWADD_WV_M4_E16_MASK_TIED, VFWADD_WV }, // 3066 |
| 24337 | { PseudoVFWADD_WV_M4_E16_TIED, VFWADD_WV }, // 3067 |
| 24338 | { PseudoVFWADD_WV_M4_E32, VFWADD_WV }, // 3068 |
| 24339 | { PseudoVFWADD_WV_M4_E32_MASK, VFWADD_WV }, // 3069 |
| 24340 | { PseudoVFWADD_WV_M4_E32_MASK_TIED, VFWADD_WV }, // 3070 |
| 24341 | { PseudoVFWADD_WV_M4_E32_TIED, VFWADD_WV }, // 3071 |
| 24342 | { PseudoVFWADD_WV_MF2_E16, VFWADD_WV }, // 3072 |
| 24343 | { PseudoVFWADD_WV_MF2_E16_MASK, VFWADD_WV }, // 3073 |
| 24344 | { PseudoVFWADD_WV_MF2_E16_MASK_TIED, VFWADD_WV }, // 3074 |
| 24345 | { PseudoVFWADD_WV_MF2_E16_TIED, VFWADD_WV }, // 3075 |
| 24346 | { PseudoVFWADD_WV_MF2_E32, VFWADD_WV }, // 3076 |
| 24347 | { PseudoVFWADD_WV_MF2_E32_MASK, VFWADD_WV }, // 3077 |
| 24348 | { PseudoVFWADD_WV_MF2_E32_MASK_TIED, VFWADD_WV }, // 3078 |
| 24349 | { PseudoVFWADD_WV_MF2_E32_TIED, VFWADD_WV }, // 3079 |
| 24350 | { PseudoVFWADD_WV_MF4_E16, VFWADD_WV }, // 3080 |
| 24351 | { PseudoVFWADD_WV_MF4_E16_MASK, VFWADD_WV }, // 3081 |
| 24352 | { PseudoVFWADD_WV_MF4_E16_MASK_TIED, VFWADD_WV }, // 3082 |
| 24353 | { PseudoVFWADD_WV_MF4_E16_TIED, VFWADD_WV }, // 3083 |
| 24354 | { PseudoVFWCVTBF16_F_F_V_M1_E16, VFWCVTBF16_F_F_V }, // 3084 |
| 24355 | { PseudoVFWCVTBF16_F_F_V_M1_E16_MASK, VFWCVTBF16_F_F_V }, // 3085 |
| 24356 | { PseudoVFWCVTBF16_F_F_V_M1_E32, VFWCVTBF16_F_F_V }, // 3086 |
| 24357 | { PseudoVFWCVTBF16_F_F_V_M1_E32_MASK, VFWCVTBF16_F_F_V }, // 3087 |
| 24358 | { PseudoVFWCVTBF16_F_F_V_M2_E16, VFWCVTBF16_F_F_V }, // 3088 |
| 24359 | { PseudoVFWCVTBF16_F_F_V_M2_E16_MASK, VFWCVTBF16_F_F_V }, // 3089 |
| 24360 | { PseudoVFWCVTBF16_F_F_V_M2_E32, VFWCVTBF16_F_F_V }, // 3090 |
| 24361 | { PseudoVFWCVTBF16_F_F_V_M2_E32_MASK, VFWCVTBF16_F_F_V }, // 3091 |
| 24362 | { PseudoVFWCVTBF16_F_F_V_M4_E16, VFWCVTBF16_F_F_V }, // 3092 |
| 24363 | { PseudoVFWCVTBF16_F_F_V_M4_E16_MASK, VFWCVTBF16_F_F_V }, // 3093 |
| 24364 | { PseudoVFWCVTBF16_F_F_V_M4_E32, VFWCVTBF16_F_F_V }, // 3094 |
| 24365 | { PseudoVFWCVTBF16_F_F_V_M4_E32_MASK, VFWCVTBF16_F_F_V }, // 3095 |
| 24366 | { PseudoVFWCVTBF16_F_F_V_MF2_E16, VFWCVTBF16_F_F_V }, // 3096 |
| 24367 | { PseudoVFWCVTBF16_F_F_V_MF2_E16_MASK, VFWCVTBF16_F_F_V }, // 3097 |
| 24368 | { PseudoVFWCVTBF16_F_F_V_MF2_E32, VFWCVTBF16_F_F_V }, // 3098 |
| 24369 | { PseudoVFWCVTBF16_F_F_V_MF2_E32_MASK, VFWCVTBF16_F_F_V }, // 3099 |
| 24370 | { PseudoVFWCVTBF16_F_F_V_MF4_E16, VFWCVTBF16_F_F_V }, // 3100 |
| 24371 | { PseudoVFWCVTBF16_F_F_V_MF4_E16_MASK, VFWCVTBF16_F_F_V }, // 3101 |
| 24372 | { PseudoVFWCVT_F_F_V_M1_E16, VFWCVT_F_F_V }, // 3102 |
| 24373 | { PseudoVFWCVT_F_F_V_M1_E16_MASK, VFWCVT_F_F_V }, // 3103 |
| 24374 | { PseudoVFWCVT_F_F_V_M1_E32, VFWCVT_F_F_V }, // 3104 |
| 24375 | { PseudoVFWCVT_F_F_V_M1_E32_MASK, VFWCVT_F_F_V }, // 3105 |
| 24376 | { PseudoVFWCVT_F_F_V_M2_E16, VFWCVT_F_F_V }, // 3106 |
| 24377 | { PseudoVFWCVT_F_F_V_M2_E16_MASK, VFWCVT_F_F_V }, // 3107 |
| 24378 | { PseudoVFWCVT_F_F_V_M2_E32, VFWCVT_F_F_V }, // 3108 |
| 24379 | { PseudoVFWCVT_F_F_V_M2_E32_MASK, VFWCVT_F_F_V }, // 3109 |
| 24380 | { PseudoVFWCVT_F_F_V_M4_E16, VFWCVT_F_F_V }, // 3110 |
| 24381 | { PseudoVFWCVT_F_F_V_M4_E16_MASK, VFWCVT_F_F_V }, // 3111 |
| 24382 | { PseudoVFWCVT_F_F_V_M4_E32, VFWCVT_F_F_V }, // 3112 |
| 24383 | { PseudoVFWCVT_F_F_V_M4_E32_MASK, VFWCVT_F_F_V }, // 3113 |
| 24384 | { PseudoVFWCVT_F_F_V_MF2_E16, VFWCVT_F_F_V }, // 3114 |
| 24385 | { PseudoVFWCVT_F_F_V_MF2_E16_MASK, VFWCVT_F_F_V }, // 3115 |
| 24386 | { PseudoVFWCVT_F_F_V_MF2_E32, VFWCVT_F_F_V }, // 3116 |
| 24387 | { PseudoVFWCVT_F_F_V_MF2_E32_MASK, VFWCVT_F_F_V }, // 3117 |
| 24388 | { PseudoVFWCVT_F_F_V_MF4_E16, VFWCVT_F_F_V }, // 3118 |
| 24389 | { PseudoVFWCVT_F_F_V_MF4_E16_MASK, VFWCVT_F_F_V }, // 3119 |
| 24390 | { PseudoVFWCVT_F_XU_V_M1_E16, VFWCVT_F_XU_V }, // 3120 |
| 24391 | { PseudoVFWCVT_F_XU_V_M1_E16_MASK, VFWCVT_F_XU_V }, // 3121 |
| 24392 | { PseudoVFWCVT_F_XU_V_M1_E32, VFWCVT_F_XU_V }, // 3122 |
| 24393 | { PseudoVFWCVT_F_XU_V_M1_E32_MASK, VFWCVT_F_XU_V }, // 3123 |
| 24394 | { PseudoVFWCVT_F_XU_V_M1_E8, VFWCVT_F_XU_V }, // 3124 |
| 24395 | { PseudoVFWCVT_F_XU_V_M1_E8_MASK, VFWCVT_F_XU_V }, // 3125 |
| 24396 | { PseudoVFWCVT_F_XU_V_M2_E16, VFWCVT_F_XU_V }, // 3126 |
| 24397 | { PseudoVFWCVT_F_XU_V_M2_E16_MASK, VFWCVT_F_XU_V }, // 3127 |
| 24398 | { PseudoVFWCVT_F_XU_V_M2_E32, VFWCVT_F_XU_V }, // 3128 |
| 24399 | { PseudoVFWCVT_F_XU_V_M2_E32_MASK, VFWCVT_F_XU_V }, // 3129 |
| 24400 | { PseudoVFWCVT_F_XU_V_M2_E8, VFWCVT_F_XU_V }, // 3130 |
| 24401 | { PseudoVFWCVT_F_XU_V_M2_E8_MASK, VFWCVT_F_XU_V }, // 3131 |
| 24402 | { PseudoVFWCVT_F_XU_V_M4_E16, VFWCVT_F_XU_V }, // 3132 |
| 24403 | { PseudoVFWCVT_F_XU_V_M4_E16_MASK, VFWCVT_F_XU_V }, // 3133 |
| 24404 | { PseudoVFWCVT_F_XU_V_M4_E32, VFWCVT_F_XU_V }, // 3134 |
| 24405 | { PseudoVFWCVT_F_XU_V_M4_E32_MASK, VFWCVT_F_XU_V }, // 3135 |
| 24406 | { PseudoVFWCVT_F_XU_V_M4_E8, VFWCVT_F_XU_V }, // 3136 |
| 24407 | { PseudoVFWCVT_F_XU_V_M4_E8_MASK, VFWCVT_F_XU_V }, // 3137 |
| 24408 | { PseudoVFWCVT_F_XU_V_MF2_E16, VFWCVT_F_XU_V }, // 3138 |
| 24409 | { PseudoVFWCVT_F_XU_V_MF2_E16_MASK, VFWCVT_F_XU_V }, // 3139 |
| 24410 | { PseudoVFWCVT_F_XU_V_MF2_E32, VFWCVT_F_XU_V }, // 3140 |
| 24411 | { PseudoVFWCVT_F_XU_V_MF2_E32_MASK, VFWCVT_F_XU_V }, // 3141 |
| 24412 | { PseudoVFWCVT_F_XU_V_MF2_E8, VFWCVT_F_XU_V }, // 3142 |
| 24413 | { PseudoVFWCVT_F_XU_V_MF2_E8_MASK, VFWCVT_F_XU_V }, // 3143 |
| 24414 | { PseudoVFWCVT_F_XU_V_MF4_E16, VFWCVT_F_XU_V }, // 3144 |
| 24415 | { PseudoVFWCVT_F_XU_V_MF4_E16_MASK, VFWCVT_F_XU_V }, // 3145 |
| 24416 | { PseudoVFWCVT_F_XU_V_MF4_E8, VFWCVT_F_XU_V }, // 3146 |
| 24417 | { PseudoVFWCVT_F_XU_V_MF4_E8_MASK, VFWCVT_F_XU_V }, // 3147 |
| 24418 | { PseudoVFWCVT_F_XU_V_MF8_E8, VFWCVT_F_XU_V }, // 3148 |
| 24419 | { PseudoVFWCVT_F_XU_V_MF8_E8_MASK, VFWCVT_F_XU_V }, // 3149 |
| 24420 | { PseudoVFWCVT_F_X_V_M1_E16, VFWCVT_F_X_V }, // 3150 |
| 24421 | { PseudoVFWCVT_F_X_V_M1_E16_MASK, VFWCVT_F_X_V }, // 3151 |
| 24422 | { PseudoVFWCVT_F_X_V_M1_E32, VFWCVT_F_X_V }, // 3152 |
| 24423 | { PseudoVFWCVT_F_X_V_M1_E32_MASK, VFWCVT_F_X_V }, // 3153 |
| 24424 | { PseudoVFWCVT_F_X_V_M1_E8, VFWCVT_F_X_V }, // 3154 |
| 24425 | { PseudoVFWCVT_F_X_V_M1_E8_MASK, VFWCVT_F_X_V }, // 3155 |
| 24426 | { PseudoVFWCVT_F_X_V_M2_E16, VFWCVT_F_X_V }, // 3156 |
| 24427 | { PseudoVFWCVT_F_X_V_M2_E16_MASK, VFWCVT_F_X_V }, // 3157 |
| 24428 | { PseudoVFWCVT_F_X_V_M2_E32, VFWCVT_F_X_V }, // 3158 |
| 24429 | { PseudoVFWCVT_F_X_V_M2_E32_MASK, VFWCVT_F_X_V }, // 3159 |
| 24430 | { PseudoVFWCVT_F_X_V_M2_E8, VFWCVT_F_X_V }, // 3160 |
| 24431 | { PseudoVFWCVT_F_X_V_M2_E8_MASK, VFWCVT_F_X_V }, // 3161 |
| 24432 | { PseudoVFWCVT_F_X_V_M4_E16, VFWCVT_F_X_V }, // 3162 |
| 24433 | { PseudoVFWCVT_F_X_V_M4_E16_MASK, VFWCVT_F_X_V }, // 3163 |
| 24434 | { PseudoVFWCVT_F_X_V_M4_E32, VFWCVT_F_X_V }, // 3164 |
| 24435 | { PseudoVFWCVT_F_X_V_M4_E32_MASK, VFWCVT_F_X_V }, // 3165 |
| 24436 | { PseudoVFWCVT_F_X_V_M4_E8, VFWCVT_F_X_V }, // 3166 |
| 24437 | { PseudoVFWCVT_F_X_V_M4_E8_MASK, VFWCVT_F_X_V }, // 3167 |
| 24438 | { PseudoVFWCVT_F_X_V_MF2_E16, VFWCVT_F_X_V }, // 3168 |
| 24439 | { PseudoVFWCVT_F_X_V_MF2_E16_MASK, VFWCVT_F_X_V }, // 3169 |
| 24440 | { PseudoVFWCVT_F_X_V_MF2_E32, VFWCVT_F_X_V }, // 3170 |
| 24441 | { PseudoVFWCVT_F_X_V_MF2_E32_MASK, VFWCVT_F_X_V }, // 3171 |
| 24442 | { PseudoVFWCVT_F_X_V_MF2_E8, VFWCVT_F_X_V }, // 3172 |
| 24443 | { PseudoVFWCVT_F_X_V_MF2_E8_MASK, VFWCVT_F_X_V }, // 3173 |
| 24444 | { PseudoVFWCVT_F_X_V_MF4_E16, VFWCVT_F_X_V }, // 3174 |
| 24445 | { PseudoVFWCVT_F_X_V_MF4_E16_MASK, VFWCVT_F_X_V }, // 3175 |
| 24446 | { PseudoVFWCVT_F_X_V_MF4_E8, VFWCVT_F_X_V }, // 3176 |
| 24447 | { PseudoVFWCVT_F_X_V_MF4_E8_MASK, VFWCVT_F_X_V }, // 3177 |
| 24448 | { PseudoVFWCVT_F_X_V_MF8_E8, VFWCVT_F_X_V }, // 3178 |
| 24449 | { PseudoVFWCVT_F_X_V_MF8_E8_MASK, VFWCVT_F_X_V }, // 3179 |
| 24450 | { PseudoVFWCVT_RM_XU_F_V_M1, VFWCVT_XU_F_V }, // 3180 |
| 24451 | { PseudoVFWCVT_RM_XU_F_V_M1_MASK, VFWCVT_XU_F_V }, // 3181 |
| 24452 | { PseudoVFWCVT_RM_XU_F_V_M2, VFWCVT_XU_F_V }, // 3182 |
| 24453 | { PseudoVFWCVT_RM_XU_F_V_M2_MASK, VFWCVT_XU_F_V }, // 3183 |
| 24454 | { PseudoVFWCVT_RM_XU_F_V_M4, VFWCVT_XU_F_V }, // 3184 |
| 24455 | { PseudoVFWCVT_RM_XU_F_V_M4_MASK, VFWCVT_XU_F_V }, // 3185 |
| 24456 | { PseudoVFWCVT_RM_XU_F_V_MF2, VFWCVT_XU_F_V }, // 3186 |
| 24457 | { PseudoVFWCVT_RM_XU_F_V_MF2_MASK, VFWCVT_XU_F_V }, // 3187 |
| 24458 | { PseudoVFWCVT_RM_XU_F_V_MF4, VFWCVT_XU_F_V }, // 3188 |
| 24459 | { PseudoVFWCVT_RM_XU_F_V_MF4_MASK, VFWCVT_XU_F_V }, // 3189 |
| 24460 | { PseudoVFWCVT_RM_X_F_V_M1, VFWCVT_X_F_V }, // 3190 |
| 24461 | { PseudoVFWCVT_RM_X_F_V_M1_MASK, VFWCVT_X_F_V }, // 3191 |
| 24462 | { PseudoVFWCVT_RM_X_F_V_M2, VFWCVT_X_F_V }, // 3192 |
| 24463 | { PseudoVFWCVT_RM_X_F_V_M2_MASK, VFWCVT_X_F_V }, // 3193 |
| 24464 | { PseudoVFWCVT_RM_X_F_V_M4, VFWCVT_X_F_V }, // 3194 |
| 24465 | { PseudoVFWCVT_RM_X_F_V_M4_MASK, VFWCVT_X_F_V }, // 3195 |
| 24466 | { PseudoVFWCVT_RM_X_F_V_MF2, VFWCVT_X_F_V }, // 3196 |
| 24467 | { PseudoVFWCVT_RM_X_F_V_MF2_MASK, VFWCVT_X_F_V }, // 3197 |
| 24468 | { PseudoVFWCVT_RM_X_F_V_MF4, VFWCVT_X_F_V }, // 3198 |
| 24469 | { PseudoVFWCVT_RM_X_F_V_MF4_MASK, VFWCVT_X_F_V }, // 3199 |
| 24470 | { PseudoVFWCVT_RTZ_XU_F_V_M1, VFWCVT_RTZ_XU_F_V }, // 3200 |
| 24471 | { PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, VFWCVT_RTZ_XU_F_V }, // 3201 |
| 24472 | { PseudoVFWCVT_RTZ_XU_F_V_M2, VFWCVT_RTZ_XU_F_V }, // 3202 |
| 24473 | { PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, VFWCVT_RTZ_XU_F_V }, // 3203 |
| 24474 | { PseudoVFWCVT_RTZ_XU_F_V_M4, VFWCVT_RTZ_XU_F_V }, // 3204 |
| 24475 | { PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, VFWCVT_RTZ_XU_F_V }, // 3205 |
| 24476 | { PseudoVFWCVT_RTZ_XU_F_V_MF2, VFWCVT_RTZ_XU_F_V }, // 3206 |
| 24477 | { PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, VFWCVT_RTZ_XU_F_V }, // 3207 |
| 24478 | { PseudoVFWCVT_RTZ_XU_F_V_MF4, VFWCVT_RTZ_XU_F_V }, // 3208 |
| 24479 | { PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, VFWCVT_RTZ_XU_F_V }, // 3209 |
| 24480 | { PseudoVFWCVT_RTZ_X_F_V_M1, VFWCVT_RTZ_X_F_V }, // 3210 |
| 24481 | { PseudoVFWCVT_RTZ_X_F_V_M1_MASK, VFWCVT_RTZ_X_F_V }, // 3211 |
| 24482 | { PseudoVFWCVT_RTZ_X_F_V_M2, VFWCVT_RTZ_X_F_V }, // 3212 |
| 24483 | { PseudoVFWCVT_RTZ_X_F_V_M2_MASK, VFWCVT_RTZ_X_F_V }, // 3213 |
| 24484 | { PseudoVFWCVT_RTZ_X_F_V_M4, VFWCVT_RTZ_X_F_V }, // 3214 |
| 24485 | { PseudoVFWCVT_RTZ_X_F_V_M4_MASK, VFWCVT_RTZ_X_F_V }, // 3215 |
| 24486 | { PseudoVFWCVT_RTZ_X_F_V_MF2, VFWCVT_RTZ_X_F_V }, // 3216 |
| 24487 | { PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, VFWCVT_RTZ_X_F_V }, // 3217 |
| 24488 | { PseudoVFWCVT_RTZ_X_F_V_MF4, VFWCVT_RTZ_X_F_V }, // 3218 |
| 24489 | { PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, VFWCVT_RTZ_X_F_V }, // 3219 |
| 24490 | { PseudoVFWCVT_XU_F_V_M1, VFWCVT_XU_F_V }, // 3220 |
| 24491 | { PseudoVFWCVT_XU_F_V_M1_MASK, VFWCVT_XU_F_V }, // 3221 |
| 24492 | { PseudoVFWCVT_XU_F_V_M2, VFWCVT_XU_F_V }, // 3222 |
| 24493 | { PseudoVFWCVT_XU_F_V_M2_MASK, VFWCVT_XU_F_V }, // 3223 |
| 24494 | { PseudoVFWCVT_XU_F_V_M4, VFWCVT_XU_F_V }, // 3224 |
| 24495 | { PseudoVFWCVT_XU_F_V_M4_MASK, VFWCVT_XU_F_V }, // 3225 |
| 24496 | { PseudoVFWCVT_XU_F_V_MF2, VFWCVT_XU_F_V }, // 3226 |
| 24497 | { PseudoVFWCVT_XU_F_V_MF2_MASK, VFWCVT_XU_F_V }, // 3227 |
| 24498 | { PseudoVFWCVT_XU_F_V_MF4, VFWCVT_XU_F_V }, // 3228 |
| 24499 | { PseudoVFWCVT_XU_F_V_MF4_MASK, VFWCVT_XU_F_V }, // 3229 |
| 24500 | { PseudoVFWCVT_X_F_V_M1, VFWCVT_X_F_V }, // 3230 |
| 24501 | { PseudoVFWCVT_X_F_V_M1_MASK, VFWCVT_X_F_V }, // 3231 |
| 24502 | { PseudoVFWCVT_X_F_V_M2, VFWCVT_X_F_V }, // 3232 |
| 24503 | { PseudoVFWCVT_X_F_V_M2_MASK, VFWCVT_X_F_V }, // 3233 |
| 24504 | { PseudoVFWCVT_X_F_V_M4, VFWCVT_X_F_V }, // 3234 |
| 24505 | { PseudoVFWCVT_X_F_V_M4_MASK, VFWCVT_X_F_V }, // 3235 |
| 24506 | { PseudoVFWCVT_X_F_V_MF2, VFWCVT_X_F_V }, // 3236 |
| 24507 | { PseudoVFWCVT_X_F_V_MF2_MASK, VFWCVT_X_F_V }, // 3237 |
| 24508 | { PseudoVFWCVT_X_F_V_MF4, VFWCVT_X_F_V }, // 3238 |
| 24509 | { PseudoVFWCVT_X_F_V_MF4_MASK, VFWCVT_X_F_V }, // 3239 |
| 24510 | { PseudoVFWMACCBF16_VFPR16_M1_E16, VFWMACCBF16_VF }, // 3240 |
| 24511 | { PseudoVFWMACCBF16_VFPR16_M1_E16_MASK, VFWMACCBF16_VF }, // 3241 |
| 24512 | { PseudoVFWMACCBF16_VFPR16_M2_E16, VFWMACCBF16_VF }, // 3242 |
| 24513 | { PseudoVFWMACCBF16_VFPR16_M2_E16_MASK, VFWMACCBF16_VF }, // 3243 |
| 24514 | { PseudoVFWMACCBF16_VFPR16_M4_E16, VFWMACCBF16_VF }, // 3244 |
| 24515 | { PseudoVFWMACCBF16_VFPR16_M4_E16_MASK, VFWMACCBF16_VF }, // 3245 |
| 24516 | { PseudoVFWMACCBF16_VFPR16_MF2_E16, VFWMACCBF16_VF }, // 3246 |
| 24517 | { PseudoVFWMACCBF16_VFPR16_MF2_E16_MASK, VFWMACCBF16_VF }, // 3247 |
| 24518 | { PseudoVFWMACCBF16_VFPR16_MF4_E16, VFWMACCBF16_VF }, // 3248 |
| 24519 | { PseudoVFWMACCBF16_VFPR16_MF4_E16_MASK, VFWMACCBF16_VF }, // 3249 |
| 24520 | { PseudoVFWMACCBF16_VV_M1_E16, VFWMACCBF16_VV }, // 3250 |
| 24521 | { PseudoVFWMACCBF16_VV_M1_E16_MASK, VFWMACCBF16_VV }, // 3251 |
| 24522 | { PseudoVFWMACCBF16_VV_M1_E32, VFWMACCBF16_VV }, // 3252 |
| 24523 | { PseudoVFWMACCBF16_VV_M1_E32_MASK, VFWMACCBF16_VV }, // 3253 |
| 24524 | { PseudoVFWMACCBF16_VV_M2_E16, VFWMACCBF16_VV }, // 3254 |
| 24525 | { PseudoVFWMACCBF16_VV_M2_E16_MASK, VFWMACCBF16_VV }, // 3255 |
| 24526 | { PseudoVFWMACCBF16_VV_M2_E32, VFWMACCBF16_VV }, // 3256 |
| 24527 | { PseudoVFWMACCBF16_VV_M2_E32_MASK, VFWMACCBF16_VV }, // 3257 |
| 24528 | { PseudoVFWMACCBF16_VV_M4_E16, VFWMACCBF16_VV }, // 3258 |
| 24529 | { PseudoVFWMACCBF16_VV_M4_E16_MASK, VFWMACCBF16_VV }, // 3259 |
| 24530 | { PseudoVFWMACCBF16_VV_M4_E32, VFWMACCBF16_VV }, // 3260 |
| 24531 | { PseudoVFWMACCBF16_VV_M4_E32_MASK, VFWMACCBF16_VV }, // 3261 |
| 24532 | { PseudoVFWMACCBF16_VV_MF2_E16, VFWMACCBF16_VV }, // 3262 |
| 24533 | { PseudoVFWMACCBF16_VV_MF2_E16_MASK, VFWMACCBF16_VV }, // 3263 |
| 24534 | { PseudoVFWMACCBF16_VV_MF2_E32, VFWMACCBF16_VV }, // 3264 |
| 24535 | { PseudoVFWMACCBF16_VV_MF2_E32_MASK, VFWMACCBF16_VV }, // 3265 |
| 24536 | { PseudoVFWMACCBF16_VV_MF4_E16, VFWMACCBF16_VV }, // 3266 |
| 24537 | { PseudoVFWMACCBF16_VV_MF4_E16_MASK, VFWMACCBF16_VV }, // 3267 |
| 24538 | { PseudoVFWMACC_4x4x4_M1, VFWMACC_4x4x4 }, // 3268 |
| 24539 | { PseudoVFWMACC_4x4x4_M2, VFWMACC_4x4x4 }, // 3269 |
| 24540 | { PseudoVFWMACC_4x4x4_M4, VFWMACC_4x4x4 }, // 3270 |
| 24541 | { PseudoVFWMACC_4x4x4_M8, VFWMACC_4x4x4 }, // 3271 |
| 24542 | { PseudoVFWMACC_4x4x4_MF2, VFWMACC_4x4x4 }, // 3272 |
| 24543 | { PseudoVFWMACC_4x4x4_MF4, VFWMACC_4x4x4 }, // 3273 |
| 24544 | { PseudoVFWMACC_VFPR16_M1_E16, VFWMACC_VF }, // 3274 |
| 24545 | { PseudoVFWMACC_VFPR16_M1_E16_MASK, VFWMACC_VF }, // 3275 |
| 24546 | { PseudoVFWMACC_VFPR16_M2_E16, VFWMACC_VF }, // 3276 |
| 24547 | { PseudoVFWMACC_VFPR16_M2_E16_MASK, VFWMACC_VF }, // 3277 |
| 24548 | { PseudoVFWMACC_VFPR16_M4_E16, VFWMACC_VF }, // 3278 |
| 24549 | { PseudoVFWMACC_VFPR16_M4_E16_MASK, VFWMACC_VF }, // 3279 |
| 24550 | { PseudoVFWMACC_VFPR16_MF2_E16, VFWMACC_VF }, // 3280 |
| 24551 | { PseudoVFWMACC_VFPR16_MF2_E16_MASK, VFWMACC_VF }, // 3281 |
| 24552 | { PseudoVFWMACC_VFPR16_MF4_E16, VFWMACC_VF }, // 3282 |
| 24553 | { PseudoVFWMACC_VFPR16_MF4_E16_MASK, VFWMACC_VF }, // 3283 |
| 24554 | { PseudoVFWMACC_VFPR32_M1_E32, VFWMACC_VF }, // 3284 |
| 24555 | { PseudoVFWMACC_VFPR32_M1_E32_MASK, VFWMACC_VF }, // 3285 |
| 24556 | { PseudoVFWMACC_VFPR32_M2_E32, VFWMACC_VF }, // 3286 |
| 24557 | { PseudoVFWMACC_VFPR32_M2_E32_MASK, VFWMACC_VF }, // 3287 |
| 24558 | { PseudoVFWMACC_VFPR32_M4_E32, VFWMACC_VF }, // 3288 |
| 24559 | { PseudoVFWMACC_VFPR32_M4_E32_MASK, VFWMACC_VF }, // 3289 |
| 24560 | { PseudoVFWMACC_VFPR32_MF2_E32, VFWMACC_VF }, // 3290 |
| 24561 | { PseudoVFWMACC_VFPR32_MF2_E32_MASK, VFWMACC_VF }, // 3291 |
| 24562 | { PseudoVFWMACC_VV_M1_E16, VFWMACC_VV }, // 3292 |
| 24563 | { PseudoVFWMACC_VV_M1_E16_MASK, VFWMACC_VV }, // 3293 |
| 24564 | { PseudoVFWMACC_VV_M1_E32, VFWMACC_VV }, // 3294 |
| 24565 | { PseudoVFWMACC_VV_M1_E32_MASK, VFWMACC_VV }, // 3295 |
| 24566 | { PseudoVFWMACC_VV_M2_E16, VFWMACC_VV }, // 3296 |
| 24567 | { PseudoVFWMACC_VV_M2_E16_MASK, VFWMACC_VV }, // 3297 |
| 24568 | { PseudoVFWMACC_VV_M2_E32, VFWMACC_VV }, // 3298 |
| 24569 | { PseudoVFWMACC_VV_M2_E32_MASK, VFWMACC_VV }, // 3299 |
| 24570 | { PseudoVFWMACC_VV_M4_E16, VFWMACC_VV }, // 3300 |
| 24571 | { PseudoVFWMACC_VV_M4_E16_MASK, VFWMACC_VV }, // 3301 |
| 24572 | { PseudoVFWMACC_VV_M4_E32, VFWMACC_VV }, // 3302 |
| 24573 | { PseudoVFWMACC_VV_M4_E32_MASK, VFWMACC_VV }, // 3303 |
| 24574 | { PseudoVFWMACC_VV_MF2_E16, VFWMACC_VV }, // 3304 |
| 24575 | { PseudoVFWMACC_VV_MF2_E16_MASK, VFWMACC_VV }, // 3305 |
| 24576 | { PseudoVFWMACC_VV_MF2_E32, VFWMACC_VV }, // 3306 |
| 24577 | { PseudoVFWMACC_VV_MF2_E32_MASK, VFWMACC_VV }, // 3307 |
| 24578 | { PseudoVFWMACC_VV_MF4_E16, VFWMACC_VV }, // 3308 |
| 24579 | { PseudoVFWMACC_VV_MF4_E16_MASK, VFWMACC_VV }, // 3309 |
| 24580 | { PseudoVFWMSAC_VFPR16_M1_E16, VFWMSAC_VF }, // 3310 |
| 24581 | { PseudoVFWMSAC_VFPR16_M1_E16_MASK, VFWMSAC_VF }, // 3311 |
| 24582 | { PseudoVFWMSAC_VFPR16_M2_E16, VFWMSAC_VF }, // 3312 |
| 24583 | { PseudoVFWMSAC_VFPR16_M2_E16_MASK, VFWMSAC_VF }, // 3313 |
| 24584 | { PseudoVFWMSAC_VFPR16_M4_E16, VFWMSAC_VF }, // 3314 |
| 24585 | { PseudoVFWMSAC_VFPR16_M4_E16_MASK, VFWMSAC_VF }, // 3315 |
| 24586 | { PseudoVFWMSAC_VFPR16_MF2_E16, VFWMSAC_VF }, // 3316 |
| 24587 | { PseudoVFWMSAC_VFPR16_MF2_E16_MASK, VFWMSAC_VF }, // 3317 |
| 24588 | { PseudoVFWMSAC_VFPR16_MF4_E16, VFWMSAC_VF }, // 3318 |
| 24589 | { PseudoVFWMSAC_VFPR16_MF4_E16_MASK, VFWMSAC_VF }, // 3319 |
| 24590 | { PseudoVFWMSAC_VFPR32_M1_E32, VFWMSAC_VF }, // 3320 |
| 24591 | { PseudoVFWMSAC_VFPR32_M1_E32_MASK, VFWMSAC_VF }, // 3321 |
| 24592 | { PseudoVFWMSAC_VFPR32_M2_E32, VFWMSAC_VF }, // 3322 |
| 24593 | { PseudoVFWMSAC_VFPR32_M2_E32_MASK, VFWMSAC_VF }, // 3323 |
| 24594 | { PseudoVFWMSAC_VFPR32_M4_E32, VFWMSAC_VF }, // 3324 |
| 24595 | { PseudoVFWMSAC_VFPR32_M4_E32_MASK, VFWMSAC_VF }, // 3325 |
| 24596 | { PseudoVFWMSAC_VFPR32_MF2_E32, VFWMSAC_VF }, // 3326 |
| 24597 | { PseudoVFWMSAC_VFPR32_MF2_E32_MASK, VFWMSAC_VF }, // 3327 |
| 24598 | { PseudoVFWMSAC_VV_M1_E16, VFWMSAC_VV }, // 3328 |
| 24599 | { PseudoVFWMSAC_VV_M1_E16_MASK, VFWMSAC_VV }, // 3329 |
| 24600 | { PseudoVFWMSAC_VV_M1_E32, VFWMSAC_VV }, // 3330 |
| 24601 | { PseudoVFWMSAC_VV_M1_E32_MASK, VFWMSAC_VV }, // 3331 |
| 24602 | { PseudoVFWMSAC_VV_M2_E16, VFWMSAC_VV }, // 3332 |
| 24603 | { PseudoVFWMSAC_VV_M2_E16_MASK, VFWMSAC_VV }, // 3333 |
| 24604 | { PseudoVFWMSAC_VV_M2_E32, VFWMSAC_VV }, // 3334 |
| 24605 | { PseudoVFWMSAC_VV_M2_E32_MASK, VFWMSAC_VV }, // 3335 |
| 24606 | { PseudoVFWMSAC_VV_M4_E16, VFWMSAC_VV }, // 3336 |
| 24607 | { PseudoVFWMSAC_VV_M4_E16_MASK, VFWMSAC_VV }, // 3337 |
| 24608 | { PseudoVFWMSAC_VV_M4_E32, VFWMSAC_VV }, // 3338 |
| 24609 | { PseudoVFWMSAC_VV_M4_E32_MASK, VFWMSAC_VV }, // 3339 |
| 24610 | { PseudoVFWMSAC_VV_MF2_E16, VFWMSAC_VV }, // 3340 |
| 24611 | { PseudoVFWMSAC_VV_MF2_E16_MASK, VFWMSAC_VV }, // 3341 |
| 24612 | { PseudoVFWMSAC_VV_MF2_E32, VFWMSAC_VV }, // 3342 |
| 24613 | { PseudoVFWMSAC_VV_MF2_E32_MASK, VFWMSAC_VV }, // 3343 |
| 24614 | { PseudoVFWMSAC_VV_MF4_E16, VFWMSAC_VV }, // 3344 |
| 24615 | { PseudoVFWMSAC_VV_MF4_E16_MASK, VFWMSAC_VV }, // 3345 |
| 24616 | { PseudoVFWMUL_VFPR16_M1_E16, VFWMUL_VF }, // 3346 |
| 24617 | { PseudoVFWMUL_VFPR16_M1_E16_MASK, VFWMUL_VF }, // 3347 |
| 24618 | { PseudoVFWMUL_VFPR16_M2_E16, VFWMUL_VF }, // 3348 |
| 24619 | { PseudoVFWMUL_VFPR16_M2_E16_MASK, VFWMUL_VF }, // 3349 |
| 24620 | { PseudoVFWMUL_VFPR16_M4_E16, VFWMUL_VF }, // 3350 |
| 24621 | { PseudoVFWMUL_VFPR16_M4_E16_MASK, VFWMUL_VF }, // 3351 |
| 24622 | { PseudoVFWMUL_VFPR16_MF2_E16, VFWMUL_VF }, // 3352 |
| 24623 | { PseudoVFWMUL_VFPR16_MF2_E16_MASK, VFWMUL_VF }, // 3353 |
| 24624 | { PseudoVFWMUL_VFPR16_MF4_E16, VFWMUL_VF }, // 3354 |
| 24625 | { PseudoVFWMUL_VFPR16_MF4_E16_MASK, VFWMUL_VF }, // 3355 |
| 24626 | { PseudoVFWMUL_VFPR32_M1_E32, VFWMUL_VF }, // 3356 |
| 24627 | { PseudoVFWMUL_VFPR32_M1_E32_MASK, VFWMUL_VF }, // 3357 |
| 24628 | { PseudoVFWMUL_VFPR32_M2_E32, VFWMUL_VF }, // 3358 |
| 24629 | { PseudoVFWMUL_VFPR32_M2_E32_MASK, VFWMUL_VF }, // 3359 |
| 24630 | { PseudoVFWMUL_VFPR32_M4_E32, VFWMUL_VF }, // 3360 |
| 24631 | { PseudoVFWMUL_VFPR32_M4_E32_MASK, VFWMUL_VF }, // 3361 |
| 24632 | { PseudoVFWMUL_VFPR32_MF2_E32, VFWMUL_VF }, // 3362 |
| 24633 | { PseudoVFWMUL_VFPR32_MF2_E32_MASK, VFWMUL_VF }, // 3363 |
| 24634 | { PseudoVFWMUL_VV_M1_E16, VFWMUL_VV }, // 3364 |
| 24635 | { PseudoVFWMUL_VV_M1_E16_MASK, VFWMUL_VV }, // 3365 |
| 24636 | { PseudoVFWMUL_VV_M1_E32, VFWMUL_VV }, // 3366 |
| 24637 | { PseudoVFWMUL_VV_M1_E32_MASK, VFWMUL_VV }, // 3367 |
| 24638 | { PseudoVFWMUL_VV_M2_E16, VFWMUL_VV }, // 3368 |
| 24639 | { PseudoVFWMUL_VV_M2_E16_MASK, VFWMUL_VV }, // 3369 |
| 24640 | { PseudoVFWMUL_VV_M2_E32, VFWMUL_VV }, // 3370 |
| 24641 | { PseudoVFWMUL_VV_M2_E32_MASK, VFWMUL_VV }, // 3371 |
| 24642 | { PseudoVFWMUL_VV_M4_E16, VFWMUL_VV }, // 3372 |
| 24643 | { PseudoVFWMUL_VV_M4_E16_MASK, VFWMUL_VV }, // 3373 |
| 24644 | { PseudoVFWMUL_VV_M4_E32, VFWMUL_VV }, // 3374 |
| 24645 | { PseudoVFWMUL_VV_M4_E32_MASK, VFWMUL_VV }, // 3375 |
| 24646 | { PseudoVFWMUL_VV_MF2_E16, VFWMUL_VV }, // 3376 |
| 24647 | { PseudoVFWMUL_VV_MF2_E16_MASK, VFWMUL_VV }, // 3377 |
| 24648 | { PseudoVFWMUL_VV_MF2_E32, VFWMUL_VV }, // 3378 |
| 24649 | { PseudoVFWMUL_VV_MF2_E32_MASK, VFWMUL_VV }, // 3379 |
| 24650 | { PseudoVFWMUL_VV_MF4_E16, VFWMUL_VV }, // 3380 |
| 24651 | { PseudoVFWMUL_VV_MF4_E16_MASK, VFWMUL_VV }, // 3381 |
| 24652 | { PseudoVFWNMACC_VFPR16_M1_E16, VFWNMACC_VF }, // 3382 |
| 24653 | { PseudoVFWNMACC_VFPR16_M1_E16_MASK, VFWNMACC_VF }, // 3383 |
| 24654 | { PseudoVFWNMACC_VFPR16_M2_E16, VFWNMACC_VF }, // 3384 |
| 24655 | { PseudoVFWNMACC_VFPR16_M2_E16_MASK, VFWNMACC_VF }, // 3385 |
| 24656 | { PseudoVFWNMACC_VFPR16_M4_E16, VFWNMACC_VF }, // 3386 |
| 24657 | { PseudoVFWNMACC_VFPR16_M4_E16_MASK, VFWNMACC_VF }, // 3387 |
| 24658 | { PseudoVFWNMACC_VFPR16_MF2_E16, VFWNMACC_VF }, // 3388 |
| 24659 | { PseudoVFWNMACC_VFPR16_MF2_E16_MASK, VFWNMACC_VF }, // 3389 |
| 24660 | { PseudoVFWNMACC_VFPR16_MF4_E16, VFWNMACC_VF }, // 3390 |
| 24661 | { PseudoVFWNMACC_VFPR16_MF4_E16_MASK, VFWNMACC_VF }, // 3391 |
| 24662 | { PseudoVFWNMACC_VFPR32_M1_E32, VFWNMACC_VF }, // 3392 |
| 24663 | { PseudoVFWNMACC_VFPR32_M1_E32_MASK, VFWNMACC_VF }, // 3393 |
| 24664 | { PseudoVFWNMACC_VFPR32_M2_E32, VFWNMACC_VF }, // 3394 |
| 24665 | { PseudoVFWNMACC_VFPR32_M2_E32_MASK, VFWNMACC_VF }, // 3395 |
| 24666 | { PseudoVFWNMACC_VFPR32_M4_E32, VFWNMACC_VF }, // 3396 |
| 24667 | { PseudoVFWNMACC_VFPR32_M4_E32_MASK, VFWNMACC_VF }, // 3397 |
| 24668 | { PseudoVFWNMACC_VFPR32_MF2_E32, VFWNMACC_VF }, // 3398 |
| 24669 | { PseudoVFWNMACC_VFPR32_MF2_E32_MASK, VFWNMACC_VF }, // 3399 |
| 24670 | { PseudoVFWNMACC_VV_M1_E16, VFWNMACC_VV }, // 3400 |
| 24671 | { PseudoVFWNMACC_VV_M1_E16_MASK, VFWNMACC_VV }, // 3401 |
| 24672 | { PseudoVFWNMACC_VV_M1_E32, VFWNMACC_VV }, // 3402 |
| 24673 | { PseudoVFWNMACC_VV_M1_E32_MASK, VFWNMACC_VV }, // 3403 |
| 24674 | { PseudoVFWNMACC_VV_M2_E16, VFWNMACC_VV }, // 3404 |
| 24675 | { PseudoVFWNMACC_VV_M2_E16_MASK, VFWNMACC_VV }, // 3405 |
| 24676 | { PseudoVFWNMACC_VV_M2_E32, VFWNMACC_VV }, // 3406 |
| 24677 | { PseudoVFWNMACC_VV_M2_E32_MASK, VFWNMACC_VV }, // 3407 |
| 24678 | { PseudoVFWNMACC_VV_M4_E16, VFWNMACC_VV }, // 3408 |
| 24679 | { PseudoVFWNMACC_VV_M4_E16_MASK, VFWNMACC_VV }, // 3409 |
| 24680 | { PseudoVFWNMACC_VV_M4_E32, VFWNMACC_VV }, // 3410 |
| 24681 | { PseudoVFWNMACC_VV_M4_E32_MASK, VFWNMACC_VV }, // 3411 |
| 24682 | { PseudoVFWNMACC_VV_MF2_E16, VFWNMACC_VV }, // 3412 |
| 24683 | { PseudoVFWNMACC_VV_MF2_E16_MASK, VFWNMACC_VV }, // 3413 |
| 24684 | { PseudoVFWNMACC_VV_MF2_E32, VFWNMACC_VV }, // 3414 |
| 24685 | { PseudoVFWNMACC_VV_MF2_E32_MASK, VFWNMACC_VV }, // 3415 |
| 24686 | { PseudoVFWNMACC_VV_MF4_E16, VFWNMACC_VV }, // 3416 |
| 24687 | { PseudoVFWNMACC_VV_MF4_E16_MASK, VFWNMACC_VV }, // 3417 |
| 24688 | { PseudoVFWNMSAC_VFPR16_M1_E16, VFWNMSAC_VF }, // 3418 |
| 24689 | { PseudoVFWNMSAC_VFPR16_M1_E16_MASK, VFWNMSAC_VF }, // 3419 |
| 24690 | { PseudoVFWNMSAC_VFPR16_M2_E16, VFWNMSAC_VF }, // 3420 |
| 24691 | { PseudoVFWNMSAC_VFPR16_M2_E16_MASK, VFWNMSAC_VF }, // 3421 |
| 24692 | { PseudoVFWNMSAC_VFPR16_M4_E16, VFWNMSAC_VF }, // 3422 |
| 24693 | { PseudoVFWNMSAC_VFPR16_M4_E16_MASK, VFWNMSAC_VF }, // 3423 |
| 24694 | { PseudoVFWNMSAC_VFPR16_MF2_E16, VFWNMSAC_VF }, // 3424 |
| 24695 | { PseudoVFWNMSAC_VFPR16_MF2_E16_MASK, VFWNMSAC_VF }, // 3425 |
| 24696 | { PseudoVFWNMSAC_VFPR16_MF4_E16, VFWNMSAC_VF }, // 3426 |
| 24697 | { PseudoVFWNMSAC_VFPR16_MF4_E16_MASK, VFWNMSAC_VF }, // 3427 |
| 24698 | { PseudoVFWNMSAC_VFPR32_M1_E32, VFWNMSAC_VF }, // 3428 |
| 24699 | { PseudoVFWNMSAC_VFPR32_M1_E32_MASK, VFWNMSAC_VF }, // 3429 |
| 24700 | { PseudoVFWNMSAC_VFPR32_M2_E32, VFWNMSAC_VF }, // 3430 |
| 24701 | { PseudoVFWNMSAC_VFPR32_M2_E32_MASK, VFWNMSAC_VF }, // 3431 |
| 24702 | { PseudoVFWNMSAC_VFPR32_M4_E32, VFWNMSAC_VF }, // 3432 |
| 24703 | { PseudoVFWNMSAC_VFPR32_M4_E32_MASK, VFWNMSAC_VF }, // 3433 |
| 24704 | { PseudoVFWNMSAC_VFPR32_MF2_E32, VFWNMSAC_VF }, // 3434 |
| 24705 | { PseudoVFWNMSAC_VFPR32_MF2_E32_MASK, VFWNMSAC_VF }, // 3435 |
| 24706 | { PseudoVFWNMSAC_VV_M1_E16, VFWNMSAC_VV }, // 3436 |
| 24707 | { PseudoVFWNMSAC_VV_M1_E16_MASK, VFWNMSAC_VV }, // 3437 |
| 24708 | { PseudoVFWNMSAC_VV_M1_E32, VFWNMSAC_VV }, // 3438 |
| 24709 | { PseudoVFWNMSAC_VV_M1_E32_MASK, VFWNMSAC_VV }, // 3439 |
| 24710 | { PseudoVFWNMSAC_VV_M2_E16, VFWNMSAC_VV }, // 3440 |
| 24711 | { PseudoVFWNMSAC_VV_M2_E16_MASK, VFWNMSAC_VV }, // 3441 |
| 24712 | { PseudoVFWNMSAC_VV_M2_E32, VFWNMSAC_VV }, // 3442 |
| 24713 | { PseudoVFWNMSAC_VV_M2_E32_MASK, VFWNMSAC_VV }, // 3443 |
| 24714 | { PseudoVFWNMSAC_VV_M4_E16, VFWNMSAC_VV }, // 3444 |
| 24715 | { PseudoVFWNMSAC_VV_M4_E16_MASK, VFWNMSAC_VV }, // 3445 |
| 24716 | { PseudoVFWNMSAC_VV_M4_E32, VFWNMSAC_VV }, // 3446 |
| 24717 | { PseudoVFWNMSAC_VV_M4_E32_MASK, VFWNMSAC_VV }, // 3447 |
| 24718 | { PseudoVFWNMSAC_VV_MF2_E16, VFWNMSAC_VV }, // 3448 |
| 24719 | { PseudoVFWNMSAC_VV_MF2_E16_MASK, VFWNMSAC_VV }, // 3449 |
| 24720 | { PseudoVFWNMSAC_VV_MF2_E32, VFWNMSAC_VV }, // 3450 |
| 24721 | { PseudoVFWNMSAC_VV_MF2_E32_MASK, VFWNMSAC_VV }, // 3451 |
| 24722 | { PseudoVFWNMSAC_VV_MF4_E16, VFWNMSAC_VV }, // 3452 |
| 24723 | { PseudoVFWNMSAC_VV_MF4_E16_MASK, VFWNMSAC_VV }, // 3453 |
| 24724 | { PseudoVFWREDOSUM_VS_M1_E16, VFWREDOSUM_VS }, // 3454 |
| 24725 | { PseudoVFWREDOSUM_VS_M1_E16_MASK, VFWREDOSUM_VS }, // 3455 |
| 24726 | { PseudoVFWREDOSUM_VS_M1_E32, VFWREDOSUM_VS }, // 3456 |
| 24727 | { PseudoVFWREDOSUM_VS_M1_E32_MASK, VFWREDOSUM_VS }, // 3457 |
| 24728 | { PseudoVFWREDOSUM_VS_M2_E16, VFWREDOSUM_VS }, // 3458 |
| 24729 | { PseudoVFWREDOSUM_VS_M2_E16_MASK, VFWREDOSUM_VS }, // 3459 |
| 24730 | { PseudoVFWREDOSUM_VS_M2_E32, VFWREDOSUM_VS }, // 3460 |
| 24731 | { PseudoVFWREDOSUM_VS_M2_E32_MASK, VFWREDOSUM_VS }, // 3461 |
| 24732 | { PseudoVFWREDOSUM_VS_M4_E16, VFWREDOSUM_VS }, // 3462 |
| 24733 | { PseudoVFWREDOSUM_VS_M4_E16_MASK, VFWREDOSUM_VS }, // 3463 |
| 24734 | { PseudoVFWREDOSUM_VS_M4_E32, VFWREDOSUM_VS }, // 3464 |
| 24735 | { PseudoVFWREDOSUM_VS_M4_E32_MASK, VFWREDOSUM_VS }, // 3465 |
| 24736 | { PseudoVFWREDOSUM_VS_M8_E16, VFWREDOSUM_VS }, // 3466 |
| 24737 | { PseudoVFWREDOSUM_VS_M8_E16_MASK, VFWREDOSUM_VS }, // 3467 |
| 24738 | { PseudoVFWREDOSUM_VS_M8_E32, VFWREDOSUM_VS }, // 3468 |
| 24739 | { PseudoVFWREDOSUM_VS_M8_E32_MASK, VFWREDOSUM_VS }, // 3469 |
| 24740 | { PseudoVFWREDOSUM_VS_MF2_E16, VFWREDOSUM_VS }, // 3470 |
| 24741 | { PseudoVFWREDOSUM_VS_MF2_E16_MASK, VFWREDOSUM_VS }, // 3471 |
| 24742 | { PseudoVFWREDOSUM_VS_MF2_E32, VFWREDOSUM_VS }, // 3472 |
| 24743 | { PseudoVFWREDOSUM_VS_MF2_E32_MASK, VFWREDOSUM_VS }, // 3473 |
| 24744 | { PseudoVFWREDOSUM_VS_MF4_E16, VFWREDOSUM_VS }, // 3474 |
| 24745 | { PseudoVFWREDOSUM_VS_MF4_E16_MASK, VFWREDOSUM_VS }, // 3475 |
| 24746 | { PseudoVFWREDUSUM_VS_M1_E16, VFWREDUSUM_VS }, // 3476 |
| 24747 | { PseudoVFWREDUSUM_VS_M1_E16_MASK, VFWREDUSUM_VS }, // 3477 |
| 24748 | { PseudoVFWREDUSUM_VS_M1_E32, VFWREDUSUM_VS }, // 3478 |
| 24749 | { PseudoVFWREDUSUM_VS_M1_E32_MASK, VFWREDUSUM_VS }, // 3479 |
| 24750 | { PseudoVFWREDUSUM_VS_M2_E16, VFWREDUSUM_VS }, // 3480 |
| 24751 | { PseudoVFWREDUSUM_VS_M2_E16_MASK, VFWREDUSUM_VS }, // 3481 |
| 24752 | { PseudoVFWREDUSUM_VS_M2_E32, VFWREDUSUM_VS }, // 3482 |
| 24753 | { PseudoVFWREDUSUM_VS_M2_E32_MASK, VFWREDUSUM_VS }, // 3483 |
| 24754 | { PseudoVFWREDUSUM_VS_M4_E16, VFWREDUSUM_VS }, // 3484 |
| 24755 | { PseudoVFWREDUSUM_VS_M4_E16_MASK, VFWREDUSUM_VS }, // 3485 |
| 24756 | { PseudoVFWREDUSUM_VS_M4_E32, VFWREDUSUM_VS }, // 3486 |
| 24757 | { PseudoVFWREDUSUM_VS_M4_E32_MASK, VFWREDUSUM_VS }, // 3487 |
| 24758 | { PseudoVFWREDUSUM_VS_M8_E16, VFWREDUSUM_VS }, // 3488 |
| 24759 | { PseudoVFWREDUSUM_VS_M8_E16_MASK, VFWREDUSUM_VS }, // 3489 |
| 24760 | { PseudoVFWREDUSUM_VS_M8_E32, VFWREDUSUM_VS }, // 3490 |
| 24761 | { PseudoVFWREDUSUM_VS_M8_E32_MASK, VFWREDUSUM_VS }, // 3491 |
| 24762 | { PseudoVFWREDUSUM_VS_MF2_E16, VFWREDUSUM_VS }, // 3492 |
| 24763 | { PseudoVFWREDUSUM_VS_MF2_E16_MASK, VFWREDUSUM_VS }, // 3493 |
| 24764 | { PseudoVFWREDUSUM_VS_MF2_E32, VFWREDUSUM_VS }, // 3494 |
| 24765 | { PseudoVFWREDUSUM_VS_MF2_E32_MASK, VFWREDUSUM_VS }, // 3495 |
| 24766 | { PseudoVFWREDUSUM_VS_MF4_E16, VFWREDUSUM_VS }, // 3496 |
| 24767 | { PseudoVFWREDUSUM_VS_MF4_E16_MASK, VFWREDUSUM_VS }, // 3497 |
| 24768 | { PseudoVFWSUB_VFPR16_M1_E16, VFWSUB_VF }, // 3498 |
| 24769 | { PseudoVFWSUB_VFPR16_M1_E16_MASK, VFWSUB_VF }, // 3499 |
| 24770 | { PseudoVFWSUB_VFPR16_M2_E16, VFWSUB_VF }, // 3500 |
| 24771 | { PseudoVFWSUB_VFPR16_M2_E16_MASK, VFWSUB_VF }, // 3501 |
| 24772 | { PseudoVFWSUB_VFPR16_M4_E16, VFWSUB_VF }, // 3502 |
| 24773 | { PseudoVFWSUB_VFPR16_M4_E16_MASK, VFWSUB_VF }, // 3503 |
| 24774 | { PseudoVFWSUB_VFPR16_MF2_E16, VFWSUB_VF }, // 3504 |
| 24775 | { PseudoVFWSUB_VFPR16_MF2_E16_MASK, VFWSUB_VF }, // 3505 |
| 24776 | { PseudoVFWSUB_VFPR16_MF4_E16, VFWSUB_VF }, // 3506 |
| 24777 | { PseudoVFWSUB_VFPR16_MF4_E16_MASK, VFWSUB_VF }, // 3507 |
| 24778 | { PseudoVFWSUB_VFPR32_M1_E32, VFWSUB_VF }, // 3508 |
| 24779 | { PseudoVFWSUB_VFPR32_M1_E32_MASK, VFWSUB_VF }, // 3509 |
| 24780 | { PseudoVFWSUB_VFPR32_M2_E32, VFWSUB_VF }, // 3510 |
| 24781 | { PseudoVFWSUB_VFPR32_M2_E32_MASK, VFWSUB_VF }, // 3511 |
| 24782 | { PseudoVFWSUB_VFPR32_M4_E32, VFWSUB_VF }, // 3512 |
| 24783 | { PseudoVFWSUB_VFPR32_M4_E32_MASK, VFWSUB_VF }, // 3513 |
| 24784 | { PseudoVFWSUB_VFPR32_MF2_E32, VFWSUB_VF }, // 3514 |
| 24785 | { PseudoVFWSUB_VFPR32_MF2_E32_MASK, VFWSUB_VF }, // 3515 |
| 24786 | { PseudoVFWSUB_VV_M1_E16, VFWSUB_VV }, // 3516 |
| 24787 | { PseudoVFWSUB_VV_M1_E16_MASK, VFWSUB_VV }, // 3517 |
| 24788 | { PseudoVFWSUB_VV_M1_E32, VFWSUB_VV }, // 3518 |
| 24789 | { PseudoVFWSUB_VV_M1_E32_MASK, VFWSUB_VV }, // 3519 |
| 24790 | { PseudoVFWSUB_VV_M2_E16, VFWSUB_VV }, // 3520 |
| 24791 | { PseudoVFWSUB_VV_M2_E16_MASK, VFWSUB_VV }, // 3521 |
| 24792 | { PseudoVFWSUB_VV_M2_E32, VFWSUB_VV }, // 3522 |
| 24793 | { PseudoVFWSUB_VV_M2_E32_MASK, VFWSUB_VV }, // 3523 |
| 24794 | { PseudoVFWSUB_VV_M4_E16, VFWSUB_VV }, // 3524 |
| 24795 | { PseudoVFWSUB_VV_M4_E16_MASK, VFWSUB_VV }, // 3525 |
| 24796 | { PseudoVFWSUB_VV_M4_E32, VFWSUB_VV }, // 3526 |
| 24797 | { PseudoVFWSUB_VV_M4_E32_MASK, VFWSUB_VV }, // 3527 |
| 24798 | { PseudoVFWSUB_VV_MF2_E16, VFWSUB_VV }, // 3528 |
| 24799 | { PseudoVFWSUB_VV_MF2_E16_MASK, VFWSUB_VV }, // 3529 |
| 24800 | { PseudoVFWSUB_VV_MF2_E32, VFWSUB_VV }, // 3530 |
| 24801 | { PseudoVFWSUB_VV_MF2_E32_MASK, VFWSUB_VV }, // 3531 |
| 24802 | { PseudoVFWSUB_VV_MF4_E16, VFWSUB_VV }, // 3532 |
| 24803 | { PseudoVFWSUB_VV_MF4_E16_MASK, VFWSUB_VV }, // 3533 |
| 24804 | { PseudoVFWSUB_WFPR16_M1_E16, VFWSUB_WF }, // 3534 |
| 24805 | { PseudoVFWSUB_WFPR16_M1_E16_MASK, VFWSUB_WF }, // 3535 |
| 24806 | { PseudoVFWSUB_WFPR16_M2_E16, VFWSUB_WF }, // 3536 |
| 24807 | { PseudoVFWSUB_WFPR16_M2_E16_MASK, VFWSUB_WF }, // 3537 |
| 24808 | { PseudoVFWSUB_WFPR16_M4_E16, VFWSUB_WF }, // 3538 |
| 24809 | { PseudoVFWSUB_WFPR16_M4_E16_MASK, VFWSUB_WF }, // 3539 |
| 24810 | { PseudoVFWSUB_WFPR16_MF2_E16, VFWSUB_WF }, // 3540 |
| 24811 | { PseudoVFWSUB_WFPR16_MF2_E16_MASK, VFWSUB_WF }, // 3541 |
| 24812 | { PseudoVFWSUB_WFPR16_MF4_E16, VFWSUB_WF }, // 3542 |
| 24813 | { PseudoVFWSUB_WFPR16_MF4_E16_MASK, VFWSUB_WF }, // 3543 |
| 24814 | { PseudoVFWSUB_WFPR32_M1_E32, VFWSUB_WF }, // 3544 |
| 24815 | { PseudoVFWSUB_WFPR32_M1_E32_MASK, VFWSUB_WF }, // 3545 |
| 24816 | { PseudoVFWSUB_WFPR32_M2_E32, VFWSUB_WF }, // 3546 |
| 24817 | { PseudoVFWSUB_WFPR32_M2_E32_MASK, VFWSUB_WF }, // 3547 |
| 24818 | { PseudoVFWSUB_WFPR32_M4_E32, VFWSUB_WF }, // 3548 |
| 24819 | { PseudoVFWSUB_WFPR32_M4_E32_MASK, VFWSUB_WF }, // 3549 |
| 24820 | { PseudoVFWSUB_WFPR32_MF2_E32, VFWSUB_WF }, // 3550 |
| 24821 | { PseudoVFWSUB_WFPR32_MF2_E32_MASK, VFWSUB_WF }, // 3551 |
| 24822 | { PseudoVFWSUB_WV_M1_E16, VFWSUB_WV }, // 3552 |
| 24823 | { PseudoVFWSUB_WV_M1_E16_MASK, VFWSUB_WV }, // 3553 |
| 24824 | { PseudoVFWSUB_WV_M1_E16_MASK_TIED, VFWSUB_WV }, // 3554 |
| 24825 | { PseudoVFWSUB_WV_M1_E16_TIED, VFWSUB_WV }, // 3555 |
| 24826 | { PseudoVFWSUB_WV_M1_E32, VFWSUB_WV }, // 3556 |
| 24827 | { PseudoVFWSUB_WV_M1_E32_MASK, VFWSUB_WV }, // 3557 |
| 24828 | { PseudoVFWSUB_WV_M1_E32_MASK_TIED, VFWSUB_WV }, // 3558 |
| 24829 | { PseudoVFWSUB_WV_M1_E32_TIED, VFWSUB_WV }, // 3559 |
| 24830 | { PseudoVFWSUB_WV_M2_E16, VFWSUB_WV }, // 3560 |
| 24831 | { PseudoVFWSUB_WV_M2_E16_MASK, VFWSUB_WV }, // 3561 |
| 24832 | { PseudoVFWSUB_WV_M2_E16_MASK_TIED, VFWSUB_WV }, // 3562 |
| 24833 | { PseudoVFWSUB_WV_M2_E16_TIED, VFWSUB_WV }, // 3563 |
| 24834 | { PseudoVFWSUB_WV_M2_E32, VFWSUB_WV }, // 3564 |
| 24835 | { PseudoVFWSUB_WV_M2_E32_MASK, VFWSUB_WV }, // 3565 |
| 24836 | { PseudoVFWSUB_WV_M2_E32_MASK_TIED, VFWSUB_WV }, // 3566 |
| 24837 | { PseudoVFWSUB_WV_M2_E32_TIED, VFWSUB_WV }, // 3567 |
| 24838 | { PseudoVFWSUB_WV_M4_E16, VFWSUB_WV }, // 3568 |
| 24839 | { PseudoVFWSUB_WV_M4_E16_MASK, VFWSUB_WV }, // 3569 |
| 24840 | { PseudoVFWSUB_WV_M4_E16_MASK_TIED, VFWSUB_WV }, // 3570 |
| 24841 | { PseudoVFWSUB_WV_M4_E16_TIED, VFWSUB_WV }, // 3571 |
| 24842 | { PseudoVFWSUB_WV_M4_E32, VFWSUB_WV }, // 3572 |
| 24843 | { PseudoVFWSUB_WV_M4_E32_MASK, VFWSUB_WV }, // 3573 |
| 24844 | { PseudoVFWSUB_WV_M4_E32_MASK_TIED, VFWSUB_WV }, // 3574 |
| 24845 | { PseudoVFWSUB_WV_M4_E32_TIED, VFWSUB_WV }, // 3575 |
| 24846 | { PseudoVFWSUB_WV_MF2_E16, VFWSUB_WV }, // 3576 |
| 24847 | { PseudoVFWSUB_WV_MF2_E16_MASK, VFWSUB_WV }, // 3577 |
| 24848 | { PseudoVFWSUB_WV_MF2_E16_MASK_TIED, VFWSUB_WV }, // 3578 |
| 24849 | { PseudoVFWSUB_WV_MF2_E16_TIED, VFWSUB_WV }, // 3579 |
| 24850 | { PseudoVFWSUB_WV_MF2_E32, VFWSUB_WV }, // 3580 |
| 24851 | { PseudoVFWSUB_WV_MF2_E32_MASK, VFWSUB_WV }, // 3581 |
| 24852 | { PseudoVFWSUB_WV_MF2_E32_MASK_TIED, VFWSUB_WV }, // 3582 |
| 24853 | { PseudoVFWSUB_WV_MF2_E32_TIED, VFWSUB_WV }, // 3583 |
| 24854 | { PseudoVFWSUB_WV_MF4_E16, VFWSUB_WV }, // 3584 |
| 24855 | { PseudoVFWSUB_WV_MF4_E16_MASK, VFWSUB_WV }, // 3585 |
| 24856 | { PseudoVFWSUB_WV_MF4_E16_MASK_TIED, VFWSUB_WV }, // 3586 |
| 24857 | { PseudoVFWSUB_WV_MF4_E16_TIED, VFWSUB_WV }, // 3587 |
| 24858 | { PseudoVGHSH_VV_M1, VGHSH_VV }, // 3588 |
| 24859 | { PseudoVGHSH_VV_M2, VGHSH_VV }, // 3589 |
| 24860 | { PseudoVGHSH_VV_M4, VGHSH_VV }, // 3590 |
| 24861 | { PseudoVGHSH_VV_M8, VGHSH_VV }, // 3591 |
| 24862 | { PseudoVGHSH_VV_MF2, VGHSH_VV }, // 3592 |
| 24863 | { PseudoVGMUL_VV_M1, VGMUL_VV }, // 3593 |
| 24864 | { PseudoVGMUL_VV_M2, VGMUL_VV }, // 3594 |
| 24865 | { PseudoVGMUL_VV_M4, VGMUL_VV }, // 3595 |
| 24866 | { PseudoVGMUL_VV_M8, VGMUL_VV }, // 3596 |
| 24867 | { PseudoVGMUL_VV_MF2, VGMUL_VV }, // 3597 |
| 24868 | { PseudoVID_V_M1, VID_V }, // 3598 |
| 24869 | { PseudoVID_V_M1_MASK, VID_V }, // 3599 |
| 24870 | { PseudoVID_V_M2, VID_V }, // 3600 |
| 24871 | { PseudoVID_V_M2_MASK, VID_V }, // 3601 |
| 24872 | { PseudoVID_V_M4, VID_V }, // 3602 |
| 24873 | { PseudoVID_V_M4_MASK, VID_V }, // 3603 |
| 24874 | { PseudoVID_V_M8, VID_V }, // 3604 |
| 24875 | { PseudoVID_V_M8_MASK, VID_V }, // 3605 |
| 24876 | { PseudoVID_V_MF2, VID_V }, // 3606 |
| 24877 | { PseudoVID_V_MF2_MASK, VID_V }, // 3607 |
| 24878 | { PseudoVID_V_MF4, VID_V }, // 3608 |
| 24879 | { PseudoVID_V_MF4_MASK, VID_V }, // 3609 |
| 24880 | { PseudoVID_V_MF8, VID_V }, // 3610 |
| 24881 | { PseudoVID_V_MF8_MASK, VID_V }, // 3611 |
| 24882 | { PseudoVIOTA_M_M1, VIOTA_M }, // 3612 |
| 24883 | { PseudoVIOTA_M_M1_MASK, VIOTA_M }, // 3613 |
| 24884 | { PseudoVIOTA_M_M2, VIOTA_M }, // 3614 |
| 24885 | { PseudoVIOTA_M_M2_MASK, VIOTA_M }, // 3615 |
| 24886 | { PseudoVIOTA_M_M4, VIOTA_M }, // 3616 |
| 24887 | { PseudoVIOTA_M_M4_MASK, VIOTA_M }, // 3617 |
| 24888 | { PseudoVIOTA_M_M8, VIOTA_M }, // 3618 |
| 24889 | { PseudoVIOTA_M_M8_MASK, VIOTA_M }, // 3619 |
| 24890 | { PseudoVIOTA_M_MF2, VIOTA_M }, // 3620 |
| 24891 | { PseudoVIOTA_M_MF2_MASK, VIOTA_M }, // 3621 |
| 24892 | { PseudoVIOTA_M_MF4, VIOTA_M }, // 3622 |
| 24893 | { PseudoVIOTA_M_MF4_MASK, VIOTA_M }, // 3623 |
| 24894 | { PseudoVIOTA_M_MF8, VIOTA_M }, // 3624 |
| 24895 | { PseudoVIOTA_M_MF8_MASK, VIOTA_M }, // 3625 |
| 24896 | { PseudoVLE16FF_V_M1, VLE16FF_V }, // 3626 |
| 24897 | { PseudoVLE16FF_V_M1_MASK, VLE16FF_V }, // 3627 |
| 24898 | { PseudoVLE16FF_V_M2, VLE16FF_V }, // 3628 |
| 24899 | { PseudoVLE16FF_V_M2_MASK, VLE16FF_V }, // 3629 |
| 24900 | { PseudoVLE16FF_V_M4, VLE16FF_V }, // 3630 |
| 24901 | { PseudoVLE16FF_V_M4_MASK, VLE16FF_V }, // 3631 |
| 24902 | { PseudoVLE16FF_V_M8, VLE16FF_V }, // 3632 |
| 24903 | { PseudoVLE16FF_V_M8_MASK, VLE16FF_V }, // 3633 |
| 24904 | { PseudoVLE16FF_V_MF2, VLE16FF_V }, // 3634 |
| 24905 | { PseudoVLE16FF_V_MF2_MASK, VLE16FF_V }, // 3635 |
| 24906 | { PseudoVLE16FF_V_MF4, VLE16FF_V }, // 3636 |
| 24907 | { PseudoVLE16FF_V_MF4_MASK, VLE16FF_V }, // 3637 |
| 24908 | { PseudoVLE16_V_M1, VLE16_V }, // 3638 |
| 24909 | { PseudoVLE16_V_M1_MASK, VLE16_V }, // 3639 |
| 24910 | { PseudoVLE16_V_M2, VLE16_V }, // 3640 |
| 24911 | { PseudoVLE16_V_M2_MASK, VLE16_V }, // 3641 |
| 24912 | { PseudoVLE16_V_M4, VLE16_V }, // 3642 |
| 24913 | { PseudoVLE16_V_M4_MASK, VLE16_V }, // 3643 |
| 24914 | { PseudoVLE16_V_M8, VLE16_V }, // 3644 |
| 24915 | { PseudoVLE16_V_M8_MASK, VLE16_V }, // 3645 |
| 24916 | { PseudoVLE16_V_MF2, VLE16_V }, // 3646 |
| 24917 | { PseudoVLE16_V_MF2_MASK, VLE16_V }, // 3647 |
| 24918 | { PseudoVLE16_V_MF4, VLE16_V }, // 3648 |
| 24919 | { PseudoVLE16_V_MF4_MASK, VLE16_V }, // 3649 |
| 24920 | { PseudoVLE32FF_V_M1, VLE32FF_V }, // 3650 |
| 24921 | { PseudoVLE32FF_V_M1_MASK, VLE32FF_V }, // 3651 |
| 24922 | { PseudoVLE32FF_V_M2, VLE32FF_V }, // 3652 |
| 24923 | { PseudoVLE32FF_V_M2_MASK, VLE32FF_V }, // 3653 |
| 24924 | { PseudoVLE32FF_V_M4, VLE32FF_V }, // 3654 |
| 24925 | { PseudoVLE32FF_V_M4_MASK, VLE32FF_V }, // 3655 |
| 24926 | { PseudoVLE32FF_V_M8, VLE32FF_V }, // 3656 |
| 24927 | { PseudoVLE32FF_V_M8_MASK, VLE32FF_V }, // 3657 |
| 24928 | { PseudoVLE32FF_V_MF2, VLE32FF_V }, // 3658 |
| 24929 | { PseudoVLE32FF_V_MF2_MASK, VLE32FF_V }, // 3659 |
| 24930 | { PseudoVLE32_V_M1, VLE32_V }, // 3660 |
| 24931 | { PseudoVLE32_V_M1_MASK, VLE32_V }, // 3661 |
| 24932 | { PseudoVLE32_V_M2, VLE32_V }, // 3662 |
| 24933 | { PseudoVLE32_V_M2_MASK, VLE32_V }, // 3663 |
| 24934 | { PseudoVLE32_V_M4, VLE32_V }, // 3664 |
| 24935 | { PseudoVLE32_V_M4_MASK, VLE32_V }, // 3665 |
| 24936 | { PseudoVLE32_V_M8, VLE32_V }, // 3666 |
| 24937 | { PseudoVLE32_V_M8_MASK, VLE32_V }, // 3667 |
| 24938 | { PseudoVLE32_V_MF2, VLE32_V }, // 3668 |
| 24939 | { PseudoVLE32_V_MF2_MASK, VLE32_V }, // 3669 |
| 24940 | { PseudoVLE64FF_V_M1, VLE64FF_V }, // 3670 |
| 24941 | { PseudoVLE64FF_V_M1_MASK, VLE64FF_V }, // 3671 |
| 24942 | { PseudoVLE64FF_V_M2, VLE64FF_V }, // 3672 |
| 24943 | { PseudoVLE64FF_V_M2_MASK, VLE64FF_V }, // 3673 |
| 24944 | { PseudoVLE64FF_V_M4, VLE64FF_V }, // 3674 |
| 24945 | { PseudoVLE64FF_V_M4_MASK, VLE64FF_V }, // 3675 |
| 24946 | { PseudoVLE64FF_V_M8, VLE64FF_V }, // 3676 |
| 24947 | { PseudoVLE64FF_V_M8_MASK, VLE64FF_V }, // 3677 |
| 24948 | { PseudoVLE64_V_M1, VLE64_V }, // 3678 |
| 24949 | { PseudoVLE64_V_M1_MASK, VLE64_V }, // 3679 |
| 24950 | { PseudoVLE64_V_M2, VLE64_V }, // 3680 |
| 24951 | { PseudoVLE64_V_M2_MASK, VLE64_V }, // 3681 |
| 24952 | { PseudoVLE64_V_M4, VLE64_V }, // 3682 |
| 24953 | { PseudoVLE64_V_M4_MASK, VLE64_V }, // 3683 |
| 24954 | { PseudoVLE64_V_M8, VLE64_V }, // 3684 |
| 24955 | { PseudoVLE64_V_M8_MASK, VLE64_V }, // 3685 |
| 24956 | { PseudoVLE8FF_V_M1, VLE8FF_V }, // 3686 |
| 24957 | { PseudoVLE8FF_V_M1_MASK, VLE8FF_V }, // 3687 |
| 24958 | { PseudoVLE8FF_V_M2, VLE8FF_V }, // 3688 |
| 24959 | { PseudoVLE8FF_V_M2_MASK, VLE8FF_V }, // 3689 |
| 24960 | { PseudoVLE8FF_V_M4, VLE8FF_V }, // 3690 |
| 24961 | { PseudoVLE8FF_V_M4_MASK, VLE8FF_V }, // 3691 |
| 24962 | { PseudoVLE8FF_V_M8, VLE8FF_V }, // 3692 |
| 24963 | { PseudoVLE8FF_V_M8_MASK, VLE8FF_V }, // 3693 |
| 24964 | { PseudoVLE8FF_V_MF2, VLE8FF_V }, // 3694 |
| 24965 | { PseudoVLE8FF_V_MF2_MASK, VLE8FF_V }, // 3695 |
| 24966 | { PseudoVLE8FF_V_MF4, VLE8FF_V }, // 3696 |
| 24967 | { PseudoVLE8FF_V_MF4_MASK, VLE8FF_V }, // 3697 |
| 24968 | { PseudoVLE8FF_V_MF8, VLE8FF_V }, // 3698 |
| 24969 | { PseudoVLE8FF_V_MF8_MASK, VLE8FF_V }, // 3699 |
| 24970 | { PseudoVLE8_V_M1, VLE8_V }, // 3700 |
| 24971 | { PseudoVLE8_V_M1_MASK, VLE8_V }, // 3701 |
| 24972 | { PseudoVLE8_V_M2, VLE8_V }, // 3702 |
| 24973 | { PseudoVLE8_V_M2_MASK, VLE8_V }, // 3703 |
| 24974 | { PseudoVLE8_V_M4, VLE8_V }, // 3704 |
| 24975 | { PseudoVLE8_V_M4_MASK, VLE8_V }, // 3705 |
| 24976 | { PseudoVLE8_V_M8, VLE8_V }, // 3706 |
| 24977 | { PseudoVLE8_V_M8_MASK, VLE8_V }, // 3707 |
| 24978 | { PseudoVLE8_V_MF2, VLE8_V }, // 3708 |
| 24979 | { PseudoVLE8_V_MF2_MASK, VLE8_V }, // 3709 |
| 24980 | { PseudoVLE8_V_MF4, VLE8_V }, // 3710 |
| 24981 | { PseudoVLE8_V_MF4_MASK, VLE8_V }, // 3711 |
| 24982 | { PseudoVLE8_V_MF8, VLE8_V }, // 3712 |
| 24983 | { PseudoVLE8_V_MF8_MASK, VLE8_V }, // 3713 |
| 24984 | { PseudoVLM_V_B1, VLM_V }, // 3714 |
| 24985 | { PseudoVLM_V_B16, VLM_V }, // 3715 |
| 24986 | { PseudoVLM_V_B2, VLM_V }, // 3716 |
| 24987 | { PseudoVLM_V_B32, VLM_V }, // 3717 |
| 24988 | { PseudoVLM_V_B4, VLM_V }, // 3718 |
| 24989 | { PseudoVLM_V_B64, VLM_V }, // 3719 |
| 24990 | { PseudoVLM_V_B8, VLM_V }, // 3720 |
| 24991 | { PseudoVLOXEI16_V_M1_M1, VLOXEI16_V }, // 3721 |
| 24992 | { PseudoVLOXEI16_V_M1_M1_MASK, VLOXEI16_V }, // 3722 |
| 24993 | { PseudoVLOXEI16_V_M1_M2, VLOXEI16_V }, // 3723 |
| 24994 | { PseudoVLOXEI16_V_M1_M2_MASK, VLOXEI16_V }, // 3724 |
| 24995 | { PseudoVLOXEI16_V_M1_M4, VLOXEI16_V }, // 3725 |
| 24996 | { PseudoVLOXEI16_V_M1_M4_MASK, VLOXEI16_V }, // 3726 |
| 24997 | { PseudoVLOXEI16_V_M1_MF2, VLOXEI16_V }, // 3727 |
| 24998 | { PseudoVLOXEI16_V_M1_MF2_MASK, VLOXEI16_V }, // 3728 |
| 24999 | { PseudoVLOXEI16_V_M2_M1, VLOXEI16_V }, // 3729 |
| 25000 | { PseudoVLOXEI16_V_M2_M1_MASK, VLOXEI16_V }, // 3730 |
| 25001 | { PseudoVLOXEI16_V_M2_M2, VLOXEI16_V }, // 3731 |
| 25002 | { PseudoVLOXEI16_V_M2_M2_MASK, VLOXEI16_V }, // 3732 |
| 25003 | { PseudoVLOXEI16_V_M2_M4, VLOXEI16_V }, // 3733 |
| 25004 | { PseudoVLOXEI16_V_M2_M4_MASK, VLOXEI16_V }, // 3734 |
| 25005 | { PseudoVLOXEI16_V_M2_M8, VLOXEI16_V }, // 3735 |
| 25006 | { PseudoVLOXEI16_V_M2_M8_MASK, VLOXEI16_V }, // 3736 |
| 25007 | { PseudoVLOXEI16_V_M4_M2, VLOXEI16_V }, // 3737 |
| 25008 | { PseudoVLOXEI16_V_M4_M2_MASK, VLOXEI16_V }, // 3738 |
| 25009 | { PseudoVLOXEI16_V_M4_M4, VLOXEI16_V }, // 3739 |
| 25010 | { PseudoVLOXEI16_V_M4_M4_MASK, VLOXEI16_V }, // 3740 |
| 25011 | { PseudoVLOXEI16_V_M4_M8, VLOXEI16_V }, // 3741 |
| 25012 | { PseudoVLOXEI16_V_M4_M8_MASK, VLOXEI16_V }, // 3742 |
| 25013 | { PseudoVLOXEI16_V_M8_M4, VLOXEI16_V }, // 3743 |
| 25014 | { PseudoVLOXEI16_V_M8_M4_MASK, VLOXEI16_V }, // 3744 |
| 25015 | { PseudoVLOXEI16_V_M8_M8, VLOXEI16_V }, // 3745 |
| 25016 | { PseudoVLOXEI16_V_M8_M8_MASK, VLOXEI16_V }, // 3746 |
| 25017 | { PseudoVLOXEI16_V_MF2_M1, VLOXEI16_V }, // 3747 |
| 25018 | { PseudoVLOXEI16_V_MF2_M1_MASK, VLOXEI16_V }, // 3748 |
| 25019 | { PseudoVLOXEI16_V_MF2_M2, VLOXEI16_V }, // 3749 |
| 25020 | { PseudoVLOXEI16_V_MF2_M2_MASK, VLOXEI16_V }, // 3750 |
| 25021 | { PseudoVLOXEI16_V_MF2_MF2, VLOXEI16_V }, // 3751 |
| 25022 | { PseudoVLOXEI16_V_MF2_MF2_MASK, VLOXEI16_V }, // 3752 |
| 25023 | { PseudoVLOXEI16_V_MF2_MF4, VLOXEI16_V }, // 3753 |
| 25024 | { PseudoVLOXEI16_V_MF2_MF4_MASK, VLOXEI16_V }, // 3754 |
| 25025 | { PseudoVLOXEI16_V_MF4_M1, VLOXEI16_V }, // 3755 |
| 25026 | { PseudoVLOXEI16_V_MF4_M1_MASK, VLOXEI16_V }, // 3756 |
| 25027 | { PseudoVLOXEI16_V_MF4_MF2, VLOXEI16_V }, // 3757 |
| 25028 | { PseudoVLOXEI16_V_MF4_MF2_MASK, VLOXEI16_V }, // 3758 |
| 25029 | { PseudoVLOXEI16_V_MF4_MF4, VLOXEI16_V }, // 3759 |
| 25030 | { PseudoVLOXEI16_V_MF4_MF4_MASK, VLOXEI16_V }, // 3760 |
| 25031 | { PseudoVLOXEI16_V_MF4_MF8, VLOXEI16_V }, // 3761 |
| 25032 | { PseudoVLOXEI16_V_MF4_MF8_MASK, VLOXEI16_V }, // 3762 |
| 25033 | { PseudoVLOXEI32_V_M1_M1, VLOXEI32_V }, // 3763 |
| 25034 | { PseudoVLOXEI32_V_M1_M1_MASK, VLOXEI32_V }, // 3764 |
| 25035 | { PseudoVLOXEI32_V_M1_M2, VLOXEI32_V }, // 3765 |
| 25036 | { PseudoVLOXEI32_V_M1_M2_MASK, VLOXEI32_V }, // 3766 |
| 25037 | { PseudoVLOXEI32_V_M1_MF2, VLOXEI32_V }, // 3767 |
| 25038 | { PseudoVLOXEI32_V_M1_MF2_MASK, VLOXEI32_V }, // 3768 |
| 25039 | { PseudoVLOXEI32_V_M1_MF4, VLOXEI32_V }, // 3769 |
| 25040 | { PseudoVLOXEI32_V_M1_MF4_MASK, VLOXEI32_V }, // 3770 |
| 25041 | { PseudoVLOXEI32_V_M2_M1, VLOXEI32_V }, // 3771 |
| 25042 | { PseudoVLOXEI32_V_M2_M1_MASK, VLOXEI32_V }, // 3772 |
| 25043 | { PseudoVLOXEI32_V_M2_M2, VLOXEI32_V }, // 3773 |
| 25044 | { PseudoVLOXEI32_V_M2_M2_MASK, VLOXEI32_V }, // 3774 |
| 25045 | { PseudoVLOXEI32_V_M2_M4, VLOXEI32_V }, // 3775 |
| 25046 | { PseudoVLOXEI32_V_M2_M4_MASK, VLOXEI32_V }, // 3776 |
| 25047 | { PseudoVLOXEI32_V_M2_MF2, VLOXEI32_V }, // 3777 |
| 25048 | { PseudoVLOXEI32_V_M2_MF2_MASK, VLOXEI32_V }, // 3778 |
| 25049 | { PseudoVLOXEI32_V_M4_M1, VLOXEI32_V }, // 3779 |
| 25050 | { PseudoVLOXEI32_V_M4_M1_MASK, VLOXEI32_V }, // 3780 |
| 25051 | { PseudoVLOXEI32_V_M4_M2, VLOXEI32_V }, // 3781 |
| 25052 | { PseudoVLOXEI32_V_M4_M2_MASK, VLOXEI32_V }, // 3782 |
| 25053 | { PseudoVLOXEI32_V_M4_M4, VLOXEI32_V }, // 3783 |
| 25054 | { PseudoVLOXEI32_V_M4_M4_MASK, VLOXEI32_V }, // 3784 |
| 25055 | { PseudoVLOXEI32_V_M4_M8, VLOXEI32_V }, // 3785 |
| 25056 | { PseudoVLOXEI32_V_M4_M8_MASK, VLOXEI32_V }, // 3786 |
| 25057 | { PseudoVLOXEI32_V_M8_M2, VLOXEI32_V }, // 3787 |
| 25058 | { PseudoVLOXEI32_V_M8_M2_MASK, VLOXEI32_V }, // 3788 |
| 25059 | { PseudoVLOXEI32_V_M8_M4, VLOXEI32_V }, // 3789 |
| 25060 | { PseudoVLOXEI32_V_M8_M4_MASK, VLOXEI32_V }, // 3790 |
| 25061 | { PseudoVLOXEI32_V_M8_M8, VLOXEI32_V }, // 3791 |
| 25062 | { PseudoVLOXEI32_V_M8_M8_MASK, VLOXEI32_V }, // 3792 |
| 25063 | { PseudoVLOXEI32_V_MF2_M1, VLOXEI32_V }, // 3793 |
| 25064 | { PseudoVLOXEI32_V_MF2_M1_MASK, VLOXEI32_V }, // 3794 |
| 25065 | { PseudoVLOXEI32_V_MF2_MF2, VLOXEI32_V }, // 3795 |
| 25066 | { PseudoVLOXEI32_V_MF2_MF2_MASK, VLOXEI32_V }, // 3796 |
| 25067 | { PseudoVLOXEI32_V_MF2_MF4, VLOXEI32_V }, // 3797 |
| 25068 | { PseudoVLOXEI32_V_MF2_MF4_MASK, VLOXEI32_V }, // 3798 |
| 25069 | { PseudoVLOXEI32_V_MF2_MF8, VLOXEI32_V }, // 3799 |
| 25070 | { PseudoVLOXEI32_V_MF2_MF8_MASK, VLOXEI32_V }, // 3800 |
| 25071 | { PseudoVLOXEI64_V_M1_M1, VLOXEI64_V }, // 3801 |
| 25072 | { PseudoVLOXEI64_V_M1_M1_MASK, VLOXEI64_V }, // 3802 |
| 25073 | { PseudoVLOXEI64_V_M1_MF2, VLOXEI64_V }, // 3803 |
| 25074 | { PseudoVLOXEI64_V_M1_MF2_MASK, VLOXEI64_V }, // 3804 |
| 25075 | { PseudoVLOXEI64_V_M1_MF4, VLOXEI64_V }, // 3805 |
| 25076 | { PseudoVLOXEI64_V_M1_MF4_MASK, VLOXEI64_V }, // 3806 |
| 25077 | { PseudoVLOXEI64_V_M1_MF8, VLOXEI64_V }, // 3807 |
| 25078 | { PseudoVLOXEI64_V_M1_MF8_MASK, VLOXEI64_V }, // 3808 |
| 25079 | { PseudoVLOXEI64_V_M2_M1, VLOXEI64_V }, // 3809 |
| 25080 | { PseudoVLOXEI64_V_M2_M1_MASK, VLOXEI64_V }, // 3810 |
| 25081 | { PseudoVLOXEI64_V_M2_M2, VLOXEI64_V }, // 3811 |
| 25082 | { PseudoVLOXEI64_V_M2_M2_MASK, VLOXEI64_V }, // 3812 |
| 25083 | { PseudoVLOXEI64_V_M2_MF2, VLOXEI64_V }, // 3813 |
| 25084 | { PseudoVLOXEI64_V_M2_MF2_MASK, VLOXEI64_V }, // 3814 |
| 25085 | { PseudoVLOXEI64_V_M2_MF4, VLOXEI64_V }, // 3815 |
| 25086 | { PseudoVLOXEI64_V_M2_MF4_MASK, VLOXEI64_V }, // 3816 |
| 25087 | { PseudoVLOXEI64_V_M4_M1, VLOXEI64_V }, // 3817 |
| 25088 | { PseudoVLOXEI64_V_M4_M1_MASK, VLOXEI64_V }, // 3818 |
| 25089 | { PseudoVLOXEI64_V_M4_M2, VLOXEI64_V }, // 3819 |
| 25090 | { PseudoVLOXEI64_V_M4_M2_MASK, VLOXEI64_V }, // 3820 |
| 25091 | { PseudoVLOXEI64_V_M4_M4, VLOXEI64_V }, // 3821 |
| 25092 | { PseudoVLOXEI64_V_M4_M4_MASK, VLOXEI64_V }, // 3822 |
| 25093 | { PseudoVLOXEI64_V_M4_MF2, VLOXEI64_V }, // 3823 |
| 25094 | { PseudoVLOXEI64_V_M4_MF2_MASK, VLOXEI64_V }, // 3824 |
| 25095 | { PseudoVLOXEI64_V_M8_M1, VLOXEI64_V }, // 3825 |
| 25096 | { PseudoVLOXEI64_V_M8_M1_MASK, VLOXEI64_V }, // 3826 |
| 25097 | { PseudoVLOXEI64_V_M8_M2, VLOXEI64_V }, // 3827 |
| 25098 | { PseudoVLOXEI64_V_M8_M2_MASK, VLOXEI64_V }, // 3828 |
| 25099 | { PseudoVLOXEI64_V_M8_M4, VLOXEI64_V }, // 3829 |
| 25100 | { PseudoVLOXEI64_V_M8_M4_MASK, VLOXEI64_V }, // 3830 |
| 25101 | { PseudoVLOXEI64_V_M8_M8, VLOXEI64_V }, // 3831 |
| 25102 | { PseudoVLOXEI64_V_M8_M8_MASK, VLOXEI64_V }, // 3832 |
| 25103 | { PseudoVLOXEI8_V_M1_M1, VLOXEI8_V }, // 3833 |
| 25104 | { PseudoVLOXEI8_V_M1_M1_MASK, VLOXEI8_V }, // 3834 |
| 25105 | { PseudoVLOXEI8_V_M1_M2, VLOXEI8_V }, // 3835 |
| 25106 | { PseudoVLOXEI8_V_M1_M2_MASK, VLOXEI8_V }, // 3836 |
| 25107 | { PseudoVLOXEI8_V_M1_M4, VLOXEI8_V }, // 3837 |
| 25108 | { PseudoVLOXEI8_V_M1_M4_MASK, VLOXEI8_V }, // 3838 |
| 25109 | { PseudoVLOXEI8_V_M1_M8, VLOXEI8_V }, // 3839 |
| 25110 | { PseudoVLOXEI8_V_M1_M8_MASK, VLOXEI8_V }, // 3840 |
| 25111 | { PseudoVLOXEI8_V_M2_M2, VLOXEI8_V }, // 3841 |
| 25112 | { PseudoVLOXEI8_V_M2_M2_MASK, VLOXEI8_V }, // 3842 |
| 25113 | { PseudoVLOXEI8_V_M2_M4, VLOXEI8_V }, // 3843 |
| 25114 | { PseudoVLOXEI8_V_M2_M4_MASK, VLOXEI8_V }, // 3844 |
| 25115 | { PseudoVLOXEI8_V_M2_M8, VLOXEI8_V }, // 3845 |
| 25116 | { PseudoVLOXEI8_V_M2_M8_MASK, VLOXEI8_V }, // 3846 |
| 25117 | { PseudoVLOXEI8_V_M4_M4, VLOXEI8_V }, // 3847 |
| 25118 | { PseudoVLOXEI8_V_M4_M4_MASK, VLOXEI8_V }, // 3848 |
| 25119 | { PseudoVLOXEI8_V_M4_M8, VLOXEI8_V }, // 3849 |
| 25120 | { PseudoVLOXEI8_V_M4_M8_MASK, VLOXEI8_V }, // 3850 |
| 25121 | { PseudoVLOXEI8_V_M8_M8, VLOXEI8_V }, // 3851 |
| 25122 | { PseudoVLOXEI8_V_M8_M8_MASK, VLOXEI8_V }, // 3852 |
| 25123 | { PseudoVLOXEI8_V_MF2_M1, VLOXEI8_V }, // 3853 |
| 25124 | { PseudoVLOXEI8_V_MF2_M1_MASK, VLOXEI8_V }, // 3854 |
| 25125 | { PseudoVLOXEI8_V_MF2_M2, VLOXEI8_V }, // 3855 |
| 25126 | { PseudoVLOXEI8_V_MF2_M2_MASK, VLOXEI8_V }, // 3856 |
| 25127 | { PseudoVLOXEI8_V_MF2_M4, VLOXEI8_V }, // 3857 |
| 25128 | { PseudoVLOXEI8_V_MF2_M4_MASK, VLOXEI8_V }, // 3858 |
| 25129 | { PseudoVLOXEI8_V_MF2_MF2, VLOXEI8_V }, // 3859 |
| 25130 | { PseudoVLOXEI8_V_MF2_MF2_MASK, VLOXEI8_V }, // 3860 |
| 25131 | { PseudoVLOXEI8_V_MF4_M1, VLOXEI8_V }, // 3861 |
| 25132 | { PseudoVLOXEI8_V_MF4_M1_MASK, VLOXEI8_V }, // 3862 |
| 25133 | { PseudoVLOXEI8_V_MF4_M2, VLOXEI8_V }, // 3863 |
| 25134 | { PseudoVLOXEI8_V_MF4_M2_MASK, VLOXEI8_V }, // 3864 |
| 25135 | { PseudoVLOXEI8_V_MF4_MF2, VLOXEI8_V }, // 3865 |
| 25136 | { PseudoVLOXEI8_V_MF4_MF2_MASK, VLOXEI8_V }, // 3866 |
| 25137 | { PseudoVLOXEI8_V_MF4_MF4, VLOXEI8_V }, // 3867 |
| 25138 | { PseudoVLOXEI8_V_MF4_MF4_MASK, VLOXEI8_V }, // 3868 |
| 25139 | { PseudoVLOXEI8_V_MF8_M1, VLOXEI8_V }, // 3869 |
| 25140 | { PseudoVLOXEI8_V_MF8_M1_MASK, VLOXEI8_V }, // 3870 |
| 25141 | { PseudoVLOXEI8_V_MF8_MF2, VLOXEI8_V }, // 3871 |
| 25142 | { PseudoVLOXEI8_V_MF8_MF2_MASK, VLOXEI8_V }, // 3872 |
| 25143 | { PseudoVLOXEI8_V_MF8_MF4, VLOXEI8_V }, // 3873 |
| 25144 | { PseudoVLOXEI8_V_MF8_MF4_MASK, VLOXEI8_V }, // 3874 |
| 25145 | { PseudoVLOXEI8_V_MF8_MF8, VLOXEI8_V }, // 3875 |
| 25146 | { PseudoVLOXEI8_V_MF8_MF8_MASK, VLOXEI8_V }, // 3876 |
| 25147 | { PseudoVLOXSEG2EI16_V_M1_M1, VLOXSEG2EI16_V }, // 3877 |
| 25148 | { PseudoVLOXSEG2EI16_V_M1_M1_MASK, VLOXSEG2EI16_V }, // 3878 |
| 25149 | { PseudoVLOXSEG2EI16_V_M1_M2, VLOXSEG2EI16_V }, // 3879 |
| 25150 | { PseudoVLOXSEG2EI16_V_M1_M2_MASK, VLOXSEG2EI16_V }, // 3880 |
| 25151 | { PseudoVLOXSEG2EI16_V_M1_M4, VLOXSEG2EI16_V }, // 3881 |
| 25152 | { PseudoVLOXSEG2EI16_V_M1_M4_MASK, VLOXSEG2EI16_V }, // 3882 |
| 25153 | { PseudoVLOXSEG2EI16_V_M1_MF2, VLOXSEG2EI16_V }, // 3883 |
| 25154 | { PseudoVLOXSEG2EI16_V_M1_MF2_MASK, VLOXSEG2EI16_V }, // 3884 |
| 25155 | { PseudoVLOXSEG2EI16_V_M2_M1, VLOXSEG2EI16_V }, // 3885 |
| 25156 | { PseudoVLOXSEG2EI16_V_M2_M1_MASK, VLOXSEG2EI16_V }, // 3886 |
| 25157 | { PseudoVLOXSEG2EI16_V_M2_M2, VLOXSEG2EI16_V }, // 3887 |
| 25158 | { PseudoVLOXSEG2EI16_V_M2_M2_MASK, VLOXSEG2EI16_V }, // 3888 |
| 25159 | { PseudoVLOXSEG2EI16_V_M2_M4, VLOXSEG2EI16_V }, // 3889 |
| 25160 | { PseudoVLOXSEG2EI16_V_M2_M4_MASK, VLOXSEG2EI16_V }, // 3890 |
| 25161 | { PseudoVLOXSEG2EI16_V_M4_M2, VLOXSEG2EI16_V }, // 3891 |
| 25162 | { PseudoVLOXSEG2EI16_V_M4_M2_MASK, VLOXSEG2EI16_V }, // 3892 |
| 25163 | { PseudoVLOXSEG2EI16_V_M4_M4, VLOXSEG2EI16_V }, // 3893 |
| 25164 | { PseudoVLOXSEG2EI16_V_M4_M4_MASK, VLOXSEG2EI16_V }, // 3894 |
| 25165 | { PseudoVLOXSEG2EI16_V_M8_M4, VLOXSEG2EI16_V }, // 3895 |
| 25166 | { PseudoVLOXSEG2EI16_V_M8_M4_MASK, VLOXSEG2EI16_V }, // 3896 |
| 25167 | { PseudoVLOXSEG2EI16_V_MF2_M1, VLOXSEG2EI16_V }, // 3897 |
| 25168 | { PseudoVLOXSEG2EI16_V_MF2_M1_MASK, VLOXSEG2EI16_V }, // 3898 |
| 25169 | { PseudoVLOXSEG2EI16_V_MF2_M2, VLOXSEG2EI16_V }, // 3899 |
| 25170 | { PseudoVLOXSEG2EI16_V_MF2_M2_MASK, VLOXSEG2EI16_V }, // 3900 |
| 25171 | { PseudoVLOXSEG2EI16_V_MF2_MF2, VLOXSEG2EI16_V }, // 3901 |
| 25172 | { PseudoVLOXSEG2EI16_V_MF2_MF2_MASK, VLOXSEG2EI16_V }, // 3902 |
| 25173 | { PseudoVLOXSEG2EI16_V_MF2_MF4, VLOXSEG2EI16_V }, // 3903 |
| 25174 | { PseudoVLOXSEG2EI16_V_MF2_MF4_MASK, VLOXSEG2EI16_V }, // 3904 |
| 25175 | { PseudoVLOXSEG2EI16_V_MF4_M1, VLOXSEG2EI16_V }, // 3905 |
| 25176 | { PseudoVLOXSEG2EI16_V_MF4_M1_MASK, VLOXSEG2EI16_V }, // 3906 |
| 25177 | { PseudoVLOXSEG2EI16_V_MF4_MF2, VLOXSEG2EI16_V }, // 3907 |
| 25178 | { PseudoVLOXSEG2EI16_V_MF4_MF2_MASK, VLOXSEG2EI16_V }, // 3908 |
| 25179 | { PseudoVLOXSEG2EI16_V_MF4_MF4, VLOXSEG2EI16_V }, // 3909 |
| 25180 | { PseudoVLOXSEG2EI16_V_MF4_MF4_MASK, VLOXSEG2EI16_V }, // 3910 |
| 25181 | { PseudoVLOXSEG2EI16_V_MF4_MF8, VLOXSEG2EI16_V }, // 3911 |
| 25182 | { PseudoVLOXSEG2EI16_V_MF4_MF8_MASK, VLOXSEG2EI16_V }, // 3912 |
| 25183 | { PseudoVLOXSEG2EI32_V_M1_M1, VLOXSEG2EI32_V }, // 3913 |
| 25184 | { PseudoVLOXSEG2EI32_V_M1_M1_MASK, VLOXSEG2EI32_V }, // 3914 |
| 25185 | { PseudoVLOXSEG2EI32_V_M1_M2, VLOXSEG2EI32_V }, // 3915 |
| 25186 | { PseudoVLOXSEG2EI32_V_M1_M2_MASK, VLOXSEG2EI32_V }, // 3916 |
| 25187 | { PseudoVLOXSEG2EI32_V_M1_MF2, VLOXSEG2EI32_V }, // 3917 |
| 25188 | { PseudoVLOXSEG2EI32_V_M1_MF2_MASK, VLOXSEG2EI32_V }, // 3918 |
| 25189 | { PseudoVLOXSEG2EI32_V_M1_MF4, VLOXSEG2EI32_V }, // 3919 |
| 25190 | { PseudoVLOXSEG2EI32_V_M1_MF4_MASK, VLOXSEG2EI32_V }, // 3920 |
| 25191 | { PseudoVLOXSEG2EI32_V_M2_M1, VLOXSEG2EI32_V }, // 3921 |
| 25192 | { PseudoVLOXSEG2EI32_V_M2_M1_MASK, VLOXSEG2EI32_V }, // 3922 |
| 25193 | { PseudoVLOXSEG2EI32_V_M2_M2, VLOXSEG2EI32_V }, // 3923 |
| 25194 | { PseudoVLOXSEG2EI32_V_M2_M2_MASK, VLOXSEG2EI32_V }, // 3924 |
| 25195 | { PseudoVLOXSEG2EI32_V_M2_M4, VLOXSEG2EI32_V }, // 3925 |
| 25196 | { PseudoVLOXSEG2EI32_V_M2_M4_MASK, VLOXSEG2EI32_V }, // 3926 |
| 25197 | { PseudoVLOXSEG2EI32_V_M2_MF2, VLOXSEG2EI32_V }, // 3927 |
| 25198 | { PseudoVLOXSEG2EI32_V_M2_MF2_MASK, VLOXSEG2EI32_V }, // 3928 |
| 25199 | { PseudoVLOXSEG2EI32_V_M4_M1, VLOXSEG2EI32_V }, // 3929 |
| 25200 | { PseudoVLOXSEG2EI32_V_M4_M1_MASK, VLOXSEG2EI32_V }, // 3930 |
| 25201 | { PseudoVLOXSEG2EI32_V_M4_M2, VLOXSEG2EI32_V }, // 3931 |
| 25202 | { PseudoVLOXSEG2EI32_V_M4_M2_MASK, VLOXSEG2EI32_V }, // 3932 |
| 25203 | { PseudoVLOXSEG2EI32_V_M4_M4, VLOXSEG2EI32_V }, // 3933 |
| 25204 | { PseudoVLOXSEG2EI32_V_M4_M4_MASK, VLOXSEG2EI32_V }, // 3934 |
| 25205 | { PseudoVLOXSEG2EI32_V_M8_M2, VLOXSEG2EI32_V }, // 3935 |
| 25206 | { PseudoVLOXSEG2EI32_V_M8_M2_MASK, VLOXSEG2EI32_V }, // 3936 |
| 25207 | { PseudoVLOXSEG2EI32_V_M8_M4, VLOXSEG2EI32_V }, // 3937 |
| 25208 | { PseudoVLOXSEG2EI32_V_M8_M4_MASK, VLOXSEG2EI32_V }, // 3938 |
| 25209 | { PseudoVLOXSEG2EI32_V_MF2_M1, VLOXSEG2EI32_V }, // 3939 |
| 25210 | { PseudoVLOXSEG2EI32_V_MF2_M1_MASK, VLOXSEG2EI32_V }, // 3940 |
| 25211 | { PseudoVLOXSEG2EI32_V_MF2_MF2, VLOXSEG2EI32_V }, // 3941 |
| 25212 | { PseudoVLOXSEG2EI32_V_MF2_MF2_MASK, VLOXSEG2EI32_V }, // 3942 |
| 25213 | { PseudoVLOXSEG2EI32_V_MF2_MF4, VLOXSEG2EI32_V }, // 3943 |
| 25214 | { PseudoVLOXSEG2EI32_V_MF2_MF4_MASK, VLOXSEG2EI32_V }, // 3944 |
| 25215 | { PseudoVLOXSEG2EI32_V_MF2_MF8, VLOXSEG2EI32_V }, // 3945 |
| 25216 | { PseudoVLOXSEG2EI32_V_MF2_MF8_MASK, VLOXSEG2EI32_V }, // 3946 |
| 25217 | { PseudoVLOXSEG2EI64_V_M1_M1, VLOXSEG2EI64_V }, // 3947 |
| 25218 | { PseudoVLOXSEG2EI64_V_M1_M1_MASK, VLOXSEG2EI64_V }, // 3948 |
| 25219 | { PseudoVLOXSEG2EI64_V_M1_MF2, VLOXSEG2EI64_V }, // 3949 |
| 25220 | { PseudoVLOXSEG2EI64_V_M1_MF2_MASK, VLOXSEG2EI64_V }, // 3950 |
| 25221 | { PseudoVLOXSEG2EI64_V_M1_MF4, VLOXSEG2EI64_V }, // 3951 |
| 25222 | { PseudoVLOXSEG2EI64_V_M1_MF4_MASK, VLOXSEG2EI64_V }, // 3952 |
| 25223 | { PseudoVLOXSEG2EI64_V_M1_MF8, VLOXSEG2EI64_V }, // 3953 |
| 25224 | { PseudoVLOXSEG2EI64_V_M1_MF8_MASK, VLOXSEG2EI64_V }, // 3954 |
| 25225 | { PseudoVLOXSEG2EI64_V_M2_M1, VLOXSEG2EI64_V }, // 3955 |
| 25226 | { PseudoVLOXSEG2EI64_V_M2_M1_MASK, VLOXSEG2EI64_V }, // 3956 |
| 25227 | { PseudoVLOXSEG2EI64_V_M2_M2, VLOXSEG2EI64_V }, // 3957 |
| 25228 | { PseudoVLOXSEG2EI64_V_M2_M2_MASK, VLOXSEG2EI64_V }, // 3958 |
| 25229 | { PseudoVLOXSEG2EI64_V_M2_MF2, VLOXSEG2EI64_V }, // 3959 |
| 25230 | { PseudoVLOXSEG2EI64_V_M2_MF2_MASK, VLOXSEG2EI64_V }, // 3960 |
| 25231 | { PseudoVLOXSEG2EI64_V_M2_MF4, VLOXSEG2EI64_V }, // 3961 |
| 25232 | { PseudoVLOXSEG2EI64_V_M2_MF4_MASK, VLOXSEG2EI64_V }, // 3962 |
| 25233 | { PseudoVLOXSEG2EI64_V_M4_M1, VLOXSEG2EI64_V }, // 3963 |
| 25234 | { PseudoVLOXSEG2EI64_V_M4_M1_MASK, VLOXSEG2EI64_V }, // 3964 |
| 25235 | { PseudoVLOXSEG2EI64_V_M4_M2, VLOXSEG2EI64_V }, // 3965 |
| 25236 | { PseudoVLOXSEG2EI64_V_M4_M2_MASK, VLOXSEG2EI64_V }, // 3966 |
| 25237 | { PseudoVLOXSEG2EI64_V_M4_M4, VLOXSEG2EI64_V }, // 3967 |
| 25238 | { PseudoVLOXSEG2EI64_V_M4_M4_MASK, VLOXSEG2EI64_V }, // 3968 |
| 25239 | { PseudoVLOXSEG2EI64_V_M4_MF2, VLOXSEG2EI64_V }, // 3969 |
| 25240 | { PseudoVLOXSEG2EI64_V_M4_MF2_MASK, VLOXSEG2EI64_V }, // 3970 |
| 25241 | { PseudoVLOXSEG2EI64_V_M8_M1, VLOXSEG2EI64_V }, // 3971 |
| 25242 | { PseudoVLOXSEG2EI64_V_M8_M1_MASK, VLOXSEG2EI64_V }, // 3972 |
| 25243 | { PseudoVLOXSEG2EI64_V_M8_M2, VLOXSEG2EI64_V }, // 3973 |
| 25244 | { PseudoVLOXSEG2EI64_V_M8_M2_MASK, VLOXSEG2EI64_V }, // 3974 |
| 25245 | { PseudoVLOXSEG2EI64_V_M8_M4, VLOXSEG2EI64_V }, // 3975 |
| 25246 | { PseudoVLOXSEG2EI64_V_M8_M4_MASK, VLOXSEG2EI64_V }, // 3976 |
| 25247 | { PseudoVLOXSEG2EI8_V_M1_M1, VLOXSEG2EI8_V }, // 3977 |
| 25248 | { PseudoVLOXSEG2EI8_V_M1_M1_MASK, VLOXSEG2EI8_V }, // 3978 |
| 25249 | { PseudoVLOXSEG2EI8_V_M1_M2, VLOXSEG2EI8_V }, // 3979 |
| 25250 | { PseudoVLOXSEG2EI8_V_M1_M2_MASK, VLOXSEG2EI8_V }, // 3980 |
| 25251 | { PseudoVLOXSEG2EI8_V_M1_M4, VLOXSEG2EI8_V }, // 3981 |
| 25252 | { PseudoVLOXSEG2EI8_V_M1_M4_MASK, VLOXSEG2EI8_V }, // 3982 |
| 25253 | { PseudoVLOXSEG2EI8_V_M2_M2, VLOXSEG2EI8_V }, // 3983 |
| 25254 | { PseudoVLOXSEG2EI8_V_M2_M2_MASK, VLOXSEG2EI8_V }, // 3984 |
| 25255 | { PseudoVLOXSEG2EI8_V_M2_M4, VLOXSEG2EI8_V }, // 3985 |
| 25256 | { PseudoVLOXSEG2EI8_V_M2_M4_MASK, VLOXSEG2EI8_V }, // 3986 |
| 25257 | { PseudoVLOXSEG2EI8_V_M4_M4, VLOXSEG2EI8_V }, // 3987 |
| 25258 | { PseudoVLOXSEG2EI8_V_M4_M4_MASK, VLOXSEG2EI8_V }, // 3988 |
| 25259 | { PseudoVLOXSEG2EI8_V_MF2_M1, VLOXSEG2EI8_V }, // 3989 |
| 25260 | { PseudoVLOXSEG2EI8_V_MF2_M1_MASK, VLOXSEG2EI8_V }, // 3990 |
| 25261 | { PseudoVLOXSEG2EI8_V_MF2_M2, VLOXSEG2EI8_V }, // 3991 |
| 25262 | { PseudoVLOXSEG2EI8_V_MF2_M2_MASK, VLOXSEG2EI8_V }, // 3992 |
| 25263 | { PseudoVLOXSEG2EI8_V_MF2_M4, VLOXSEG2EI8_V }, // 3993 |
| 25264 | { PseudoVLOXSEG2EI8_V_MF2_M4_MASK, VLOXSEG2EI8_V }, // 3994 |
| 25265 | { PseudoVLOXSEG2EI8_V_MF2_MF2, VLOXSEG2EI8_V }, // 3995 |
| 25266 | { PseudoVLOXSEG2EI8_V_MF2_MF2_MASK, VLOXSEG2EI8_V }, // 3996 |
| 25267 | { PseudoVLOXSEG2EI8_V_MF4_M1, VLOXSEG2EI8_V }, // 3997 |
| 25268 | { PseudoVLOXSEG2EI8_V_MF4_M1_MASK, VLOXSEG2EI8_V }, // 3998 |
| 25269 | { PseudoVLOXSEG2EI8_V_MF4_M2, VLOXSEG2EI8_V }, // 3999 |
| 25270 | { PseudoVLOXSEG2EI8_V_MF4_M2_MASK, VLOXSEG2EI8_V }, // 4000 |
| 25271 | { PseudoVLOXSEG2EI8_V_MF4_MF2, VLOXSEG2EI8_V }, // 4001 |
| 25272 | { PseudoVLOXSEG2EI8_V_MF4_MF2_MASK, VLOXSEG2EI8_V }, // 4002 |
| 25273 | { PseudoVLOXSEG2EI8_V_MF4_MF4, VLOXSEG2EI8_V }, // 4003 |
| 25274 | { PseudoVLOXSEG2EI8_V_MF4_MF4_MASK, VLOXSEG2EI8_V }, // 4004 |
| 25275 | { PseudoVLOXSEG2EI8_V_MF8_M1, VLOXSEG2EI8_V }, // 4005 |
| 25276 | { PseudoVLOXSEG2EI8_V_MF8_M1_MASK, VLOXSEG2EI8_V }, // 4006 |
| 25277 | { PseudoVLOXSEG2EI8_V_MF8_MF2, VLOXSEG2EI8_V }, // 4007 |
| 25278 | { PseudoVLOXSEG2EI8_V_MF8_MF2_MASK, VLOXSEG2EI8_V }, // 4008 |
| 25279 | { PseudoVLOXSEG2EI8_V_MF8_MF4, VLOXSEG2EI8_V }, // 4009 |
| 25280 | { PseudoVLOXSEG2EI8_V_MF8_MF4_MASK, VLOXSEG2EI8_V }, // 4010 |
| 25281 | { PseudoVLOXSEG2EI8_V_MF8_MF8, VLOXSEG2EI8_V }, // 4011 |
| 25282 | { PseudoVLOXSEG2EI8_V_MF8_MF8_MASK, VLOXSEG2EI8_V }, // 4012 |
| 25283 | { PseudoVLOXSEG3EI16_V_M1_M1, VLOXSEG3EI16_V }, // 4013 |
| 25284 | { PseudoVLOXSEG3EI16_V_M1_M1_MASK, VLOXSEG3EI16_V }, // 4014 |
| 25285 | { PseudoVLOXSEG3EI16_V_M1_M2, VLOXSEG3EI16_V }, // 4015 |
| 25286 | { PseudoVLOXSEG3EI16_V_M1_M2_MASK, VLOXSEG3EI16_V }, // 4016 |
| 25287 | { PseudoVLOXSEG3EI16_V_M1_MF2, VLOXSEG3EI16_V }, // 4017 |
| 25288 | { PseudoVLOXSEG3EI16_V_M1_MF2_MASK, VLOXSEG3EI16_V }, // 4018 |
| 25289 | { PseudoVLOXSEG3EI16_V_M2_M1, VLOXSEG3EI16_V }, // 4019 |
| 25290 | { PseudoVLOXSEG3EI16_V_M2_M1_MASK, VLOXSEG3EI16_V }, // 4020 |
| 25291 | { PseudoVLOXSEG3EI16_V_M2_M2, VLOXSEG3EI16_V }, // 4021 |
| 25292 | { PseudoVLOXSEG3EI16_V_M2_M2_MASK, VLOXSEG3EI16_V }, // 4022 |
| 25293 | { PseudoVLOXSEG3EI16_V_M4_M2, VLOXSEG3EI16_V }, // 4023 |
| 25294 | { PseudoVLOXSEG3EI16_V_M4_M2_MASK, VLOXSEG3EI16_V }, // 4024 |
| 25295 | { PseudoVLOXSEG3EI16_V_MF2_M1, VLOXSEG3EI16_V }, // 4025 |
| 25296 | { PseudoVLOXSEG3EI16_V_MF2_M1_MASK, VLOXSEG3EI16_V }, // 4026 |
| 25297 | { PseudoVLOXSEG3EI16_V_MF2_M2, VLOXSEG3EI16_V }, // 4027 |
| 25298 | { PseudoVLOXSEG3EI16_V_MF2_M2_MASK, VLOXSEG3EI16_V }, // 4028 |
| 25299 | { PseudoVLOXSEG3EI16_V_MF2_MF2, VLOXSEG3EI16_V }, // 4029 |
| 25300 | { PseudoVLOXSEG3EI16_V_MF2_MF2_MASK, VLOXSEG3EI16_V }, // 4030 |
| 25301 | { PseudoVLOXSEG3EI16_V_MF2_MF4, VLOXSEG3EI16_V }, // 4031 |
| 25302 | { PseudoVLOXSEG3EI16_V_MF2_MF4_MASK, VLOXSEG3EI16_V }, // 4032 |
| 25303 | { PseudoVLOXSEG3EI16_V_MF4_M1, VLOXSEG3EI16_V }, // 4033 |
| 25304 | { PseudoVLOXSEG3EI16_V_MF4_M1_MASK, VLOXSEG3EI16_V }, // 4034 |
| 25305 | { PseudoVLOXSEG3EI16_V_MF4_MF2, VLOXSEG3EI16_V }, // 4035 |
| 25306 | { PseudoVLOXSEG3EI16_V_MF4_MF2_MASK, VLOXSEG3EI16_V }, // 4036 |
| 25307 | { PseudoVLOXSEG3EI16_V_MF4_MF4, VLOXSEG3EI16_V }, // 4037 |
| 25308 | { PseudoVLOXSEG3EI16_V_MF4_MF4_MASK, VLOXSEG3EI16_V }, // 4038 |
| 25309 | { PseudoVLOXSEG3EI16_V_MF4_MF8, VLOXSEG3EI16_V }, // 4039 |
| 25310 | { PseudoVLOXSEG3EI16_V_MF4_MF8_MASK, VLOXSEG3EI16_V }, // 4040 |
| 25311 | { PseudoVLOXSEG3EI32_V_M1_M1, VLOXSEG3EI32_V }, // 4041 |
| 25312 | { PseudoVLOXSEG3EI32_V_M1_M1_MASK, VLOXSEG3EI32_V }, // 4042 |
| 25313 | { PseudoVLOXSEG3EI32_V_M1_M2, VLOXSEG3EI32_V }, // 4043 |
| 25314 | { PseudoVLOXSEG3EI32_V_M1_M2_MASK, VLOXSEG3EI32_V }, // 4044 |
| 25315 | { PseudoVLOXSEG3EI32_V_M1_MF2, VLOXSEG3EI32_V }, // 4045 |
| 25316 | { PseudoVLOXSEG3EI32_V_M1_MF2_MASK, VLOXSEG3EI32_V }, // 4046 |
| 25317 | { PseudoVLOXSEG3EI32_V_M1_MF4, VLOXSEG3EI32_V }, // 4047 |
| 25318 | { PseudoVLOXSEG3EI32_V_M1_MF4_MASK, VLOXSEG3EI32_V }, // 4048 |
| 25319 | { PseudoVLOXSEG3EI32_V_M2_M1, VLOXSEG3EI32_V }, // 4049 |
| 25320 | { PseudoVLOXSEG3EI32_V_M2_M1_MASK, VLOXSEG3EI32_V }, // 4050 |
| 25321 | { PseudoVLOXSEG3EI32_V_M2_M2, VLOXSEG3EI32_V }, // 4051 |
| 25322 | { PseudoVLOXSEG3EI32_V_M2_M2_MASK, VLOXSEG3EI32_V }, // 4052 |
| 25323 | { PseudoVLOXSEG3EI32_V_M2_MF2, VLOXSEG3EI32_V }, // 4053 |
| 25324 | { PseudoVLOXSEG3EI32_V_M2_MF2_MASK, VLOXSEG3EI32_V }, // 4054 |
| 25325 | { PseudoVLOXSEG3EI32_V_M4_M1, VLOXSEG3EI32_V }, // 4055 |
| 25326 | { PseudoVLOXSEG3EI32_V_M4_M1_MASK, VLOXSEG3EI32_V }, // 4056 |
| 25327 | { PseudoVLOXSEG3EI32_V_M4_M2, VLOXSEG3EI32_V }, // 4057 |
| 25328 | { PseudoVLOXSEG3EI32_V_M4_M2_MASK, VLOXSEG3EI32_V }, // 4058 |
| 25329 | { PseudoVLOXSEG3EI32_V_M8_M2, VLOXSEG3EI32_V }, // 4059 |
| 25330 | { PseudoVLOXSEG3EI32_V_M8_M2_MASK, VLOXSEG3EI32_V }, // 4060 |
| 25331 | { PseudoVLOXSEG3EI32_V_MF2_M1, VLOXSEG3EI32_V }, // 4061 |
| 25332 | { PseudoVLOXSEG3EI32_V_MF2_M1_MASK, VLOXSEG3EI32_V }, // 4062 |
| 25333 | { PseudoVLOXSEG3EI32_V_MF2_MF2, VLOXSEG3EI32_V }, // 4063 |
| 25334 | { PseudoVLOXSEG3EI32_V_MF2_MF2_MASK, VLOXSEG3EI32_V }, // 4064 |
| 25335 | { PseudoVLOXSEG3EI32_V_MF2_MF4, VLOXSEG3EI32_V }, // 4065 |
| 25336 | { PseudoVLOXSEG3EI32_V_MF2_MF4_MASK, VLOXSEG3EI32_V }, // 4066 |
| 25337 | { PseudoVLOXSEG3EI32_V_MF2_MF8, VLOXSEG3EI32_V }, // 4067 |
| 25338 | { PseudoVLOXSEG3EI32_V_MF2_MF8_MASK, VLOXSEG3EI32_V }, // 4068 |
| 25339 | { PseudoVLOXSEG3EI64_V_M1_M1, VLOXSEG3EI64_V }, // 4069 |
| 25340 | { PseudoVLOXSEG3EI64_V_M1_M1_MASK, VLOXSEG3EI64_V }, // 4070 |
| 25341 | { PseudoVLOXSEG3EI64_V_M1_MF2, VLOXSEG3EI64_V }, // 4071 |
| 25342 | { PseudoVLOXSEG3EI64_V_M1_MF2_MASK, VLOXSEG3EI64_V }, // 4072 |
| 25343 | { PseudoVLOXSEG3EI64_V_M1_MF4, VLOXSEG3EI64_V }, // 4073 |
| 25344 | { PseudoVLOXSEG3EI64_V_M1_MF4_MASK, VLOXSEG3EI64_V }, // 4074 |
| 25345 | { PseudoVLOXSEG3EI64_V_M1_MF8, VLOXSEG3EI64_V }, // 4075 |
| 25346 | { PseudoVLOXSEG3EI64_V_M1_MF8_MASK, VLOXSEG3EI64_V }, // 4076 |
| 25347 | { PseudoVLOXSEG3EI64_V_M2_M1, VLOXSEG3EI64_V }, // 4077 |
| 25348 | { PseudoVLOXSEG3EI64_V_M2_M1_MASK, VLOXSEG3EI64_V }, // 4078 |
| 25349 | { PseudoVLOXSEG3EI64_V_M2_M2, VLOXSEG3EI64_V }, // 4079 |
| 25350 | { PseudoVLOXSEG3EI64_V_M2_M2_MASK, VLOXSEG3EI64_V }, // 4080 |
| 25351 | { PseudoVLOXSEG3EI64_V_M2_MF2, VLOXSEG3EI64_V }, // 4081 |
| 25352 | { PseudoVLOXSEG3EI64_V_M2_MF2_MASK, VLOXSEG3EI64_V }, // 4082 |
| 25353 | { PseudoVLOXSEG3EI64_V_M2_MF4, VLOXSEG3EI64_V }, // 4083 |
| 25354 | { PseudoVLOXSEG3EI64_V_M2_MF4_MASK, VLOXSEG3EI64_V }, // 4084 |
| 25355 | { PseudoVLOXSEG3EI64_V_M4_M1, VLOXSEG3EI64_V }, // 4085 |
| 25356 | { PseudoVLOXSEG3EI64_V_M4_M1_MASK, VLOXSEG3EI64_V }, // 4086 |
| 25357 | { PseudoVLOXSEG3EI64_V_M4_M2, VLOXSEG3EI64_V }, // 4087 |
| 25358 | { PseudoVLOXSEG3EI64_V_M4_M2_MASK, VLOXSEG3EI64_V }, // 4088 |
| 25359 | { PseudoVLOXSEG3EI64_V_M4_MF2, VLOXSEG3EI64_V }, // 4089 |
| 25360 | { PseudoVLOXSEG3EI64_V_M4_MF2_MASK, VLOXSEG3EI64_V }, // 4090 |
| 25361 | { PseudoVLOXSEG3EI64_V_M8_M1, VLOXSEG3EI64_V }, // 4091 |
| 25362 | { PseudoVLOXSEG3EI64_V_M8_M1_MASK, VLOXSEG3EI64_V }, // 4092 |
| 25363 | { PseudoVLOXSEG3EI64_V_M8_M2, VLOXSEG3EI64_V }, // 4093 |
| 25364 | { PseudoVLOXSEG3EI64_V_M8_M2_MASK, VLOXSEG3EI64_V }, // 4094 |
| 25365 | { PseudoVLOXSEG3EI8_V_M1_M1, VLOXSEG3EI8_V }, // 4095 |
| 25366 | { PseudoVLOXSEG3EI8_V_M1_M1_MASK, VLOXSEG3EI8_V }, // 4096 |
| 25367 | { PseudoVLOXSEG3EI8_V_M1_M2, VLOXSEG3EI8_V }, // 4097 |
| 25368 | { PseudoVLOXSEG3EI8_V_M1_M2_MASK, VLOXSEG3EI8_V }, // 4098 |
| 25369 | { PseudoVLOXSEG3EI8_V_M2_M2, VLOXSEG3EI8_V }, // 4099 |
| 25370 | { PseudoVLOXSEG3EI8_V_M2_M2_MASK, VLOXSEG3EI8_V }, // 4100 |
| 25371 | { PseudoVLOXSEG3EI8_V_MF2_M1, VLOXSEG3EI8_V }, // 4101 |
| 25372 | { PseudoVLOXSEG3EI8_V_MF2_M1_MASK, VLOXSEG3EI8_V }, // 4102 |
| 25373 | { PseudoVLOXSEG3EI8_V_MF2_M2, VLOXSEG3EI8_V }, // 4103 |
| 25374 | { PseudoVLOXSEG3EI8_V_MF2_M2_MASK, VLOXSEG3EI8_V }, // 4104 |
| 25375 | { PseudoVLOXSEG3EI8_V_MF2_MF2, VLOXSEG3EI8_V }, // 4105 |
| 25376 | { PseudoVLOXSEG3EI8_V_MF2_MF2_MASK, VLOXSEG3EI8_V }, // 4106 |
| 25377 | { PseudoVLOXSEG3EI8_V_MF4_M1, VLOXSEG3EI8_V }, // 4107 |
| 25378 | { PseudoVLOXSEG3EI8_V_MF4_M1_MASK, VLOXSEG3EI8_V }, // 4108 |
| 25379 | { PseudoVLOXSEG3EI8_V_MF4_M2, VLOXSEG3EI8_V }, // 4109 |
| 25380 | { PseudoVLOXSEG3EI8_V_MF4_M2_MASK, VLOXSEG3EI8_V }, // 4110 |
| 25381 | { PseudoVLOXSEG3EI8_V_MF4_MF2, VLOXSEG3EI8_V }, // 4111 |
| 25382 | { PseudoVLOXSEG3EI8_V_MF4_MF2_MASK, VLOXSEG3EI8_V }, // 4112 |
| 25383 | { PseudoVLOXSEG3EI8_V_MF4_MF4, VLOXSEG3EI8_V }, // 4113 |
| 25384 | { PseudoVLOXSEG3EI8_V_MF4_MF4_MASK, VLOXSEG3EI8_V }, // 4114 |
| 25385 | { PseudoVLOXSEG3EI8_V_MF8_M1, VLOXSEG3EI8_V }, // 4115 |
| 25386 | { PseudoVLOXSEG3EI8_V_MF8_M1_MASK, VLOXSEG3EI8_V }, // 4116 |
| 25387 | { PseudoVLOXSEG3EI8_V_MF8_MF2, VLOXSEG3EI8_V }, // 4117 |
| 25388 | { PseudoVLOXSEG3EI8_V_MF8_MF2_MASK, VLOXSEG3EI8_V }, // 4118 |
| 25389 | { PseudoVLOXSEG3EI8_V_MF8_MF4, VLOXSEG3EI8_V }, // 4119 |
| 25390 | { PseudoVLOXSEG3EI8_V_MF8_MF4_MASK, VLOXSEG3EI8_V }, // 4120 |
| 25391 | { PseudoVLOXSEG3EI8_V_MF8_MF8, VLOXSEG3EI8_V }, // 4121 |
| 25392 | { PseudoVLOXSEG3EI8_V_MF8_MF8_MASK, VLOXSEG3EI8_V }, // 4122 |
| 25393 | { PseudoVLOXSEG4EI16_V_M1_M1, VLOXSEG4EI16_V }, // 4123 |
| 25394 | { PseudoVLOXSEG4EI16_V_M1_M1_MASK, VLOXSEG4EI16_V }, // 4124 |
| 25395 | { PseudoVLOXSEG4EI16_V_M1_M2, VLOXSEG4EI16_V }, // 4125 |
| 25396 | { PseudoVLOXSEG4EI16_V_M1_M2_MASK, VLOXSEG4EI16_V }, // 4126 |
| 25397 | { PseudoVLOXSEG4EI16_V_M1_MF2, VLOXSEG4EI16_V }, // 4127 |
| 25398 | { PseudoVLOXSEG4EI16_V_M1_MF2_MASK, VLOXSEG4EI16_V }, // 4128 |
| 25399 | { PseudoVLOXSEG4EI16_V_M2_M1, VLOXSEG4EI16_V }, // 4129 |
| 25400 | { PseudoVLOXSEG4EI16_V_M2_M1_MASK, VLOXSEG4EI16_V }, // 4130 |
| 25401 | { PseudoVLOXSEG4EI16_V_M2_M2, VLOXSEG4EI16_V }, // 4131 |
| 25402 | { PseudoVLOXSEG4EI16_V_M2_M2_MASK, VLOXSEG4EI16_V }, // 4132 |
| 25403 | { PseudoVLOXSEG4EI16_V_M4_M2, VLOXSEG4EI16_V }, // 4133 |
| 25404 | { PseudoVLOXSEG4EI16_V_M4_M2_MASK, VLOXSEG4EI16_V }, // 4134 |
| 25405 | { PseudoVLOXSEG4EI16_V_MF2_M1, VLOXSEG4EI16_V }, // 4135 |
| 25406 | { PseudoVLOXSEG4EI16_V_MF2_M1_MASK, VLOXSEG4EI16_V }, // 4136 |
| 25407 | { PseudoVLOXSEG4EI16_V_MF2_M2, VLOXSEG4EI16_V }, // 4137 |
| 25408 | { PseudoVLOXSEG4EI16_V_MF2_M2_MASK, VLOXSEG4EI16_V }, // 4138 |
| 25409 | { PseudoVLOXSEG4EI16_V_MF2_MF2, VLOXSEG4EI16_V }, // 4139 |
| 25410 | { PseudoVLOXSEG4EI16_V_MF2_MF2_MASK, VLOXSEG4EI16_V }, // 4140 |
| 25411 | { PseudoVLOXSEG4EI16_V_MF2_MF4, VLOXSEG4EI16_V }, // 4141 |
| 25412 | { PseudoVLOXSEG4EI16_V_MF2_MF4_MASK, VLOXSEG4EI16_V }, // 4142 |
| 25413 | { PseudoVLOXSEG4EI16_V_MF4_M1, VLOXSEG4EI16_V }, // 4143 |
| 25414 | { PseudoVLOXSEG4EI16_V_MF4_M1_MASK, VLOXSEG4EI16_V }, // 4144 |
| 25415 | { PseudoVLOXSEG4EI16_V_MF4_MF2, VLOXSEG4EI16_V }, // 4145 |
| 25416 | { PseudoVLOXSEG4EI16_V_MF4_MF2_MASK, VLOXSEG4EI16_V }, // 4146 |
| 25417 | { PseudoVLOXSEG4EI16_V_MF4_MF4, VLOXSEG4EI16_V }, // 4147 |
| 25418 | { PseudoVLOXSEG4EI16_V_MF4_MF4_MASK, VLOXSEG4EI16_V }, // 4148 |
| 25419 | { PseudoVLOXSEG4EI16_V_MF4_MF8, VLOXSEG4EI16_V }, // 4149 |
| 25420 | { PseudoVLOXSEG4EI16_V_MF4_MF8_MASK, VLOXSEG4EI16_V }, // 4150 |
| 25421 | { PseudoVLOXSEG4EI32_V_M1_M1, VLOXSEG4EI32_V }, // 4151 |
| 25422 | { PseudoVLOXSEG4EI32_V_M1_M1_MASK, VLOXSEG4EI32_V }, // 4152 |
| 25423 | { PseudoVLOXSEG4EI32_V_M1_M2, VLOXSEG4EI32_V }, // 4153 |
| 25424 | { PseudoVLOXSEG4EI32_V_M1_M2_MASK, VLOXSEG4EI32_V }, // 4154 |
| 25425 | { PseudoVLOXSEG4EI32_V_M1_MF2, VLOXSEG4EI32_V }, // 4155 |
| 25426 | { PseudoVLOXSEG4EI32_V_M1_MF2_MASK, VLOXSEG4EI32_V }, // 4156 |
| 25427 | { PseudoVLOXSEG4EI32_V_M1_MF4, VLOXSEG4EI32_V }, // 4157 |
| 25428 | { PseudoVLOXSEG4EI32_V_M1_MF4_MASK, VLOXSEG4EI32_V }, // 4158 |
| 25429 | { PseudoVLOXSEG4EI32_V_M2_M1, VLOXSEG4EI32_V }, // 4159 |
| 25430 | { PseudoVLOXSEG4EI32_V_M2_M1_MASK, VLOXSEG4EI32_V }, // 4160 |
| 25431 | { PseudoVLOXSEG4EI32_V_M2_M2, VLOXSEG4EI32_V }, // 4161 |
| 25432 | { PseudoVLOXSEG4EI32_V_M2_M2_MASK, VLOXSEG4EI32_V }, // 4162 |
| 25433 | { PseudoVLOXSEG4EI32_V_M2_MF2, VLOXSEG4EI32_V }, // 4163 |
| 25434 | { PseudoVLOXSEG4EI32_V_M2_MF2_MASK, VLOXSEG4EI32_V }, // 4164 |
| 25435 | { PseudoVLOXSEG4EI32_V_M4_M1, VLOXSEG4EI32_V }, // 4165 |
| 25436 | { PseudoVLOXSEG4EI32_V_M4_M1_MASK, VLOXSEG4EI32_V }, // 4166 |
| 25437 | { PseudoVLOXSEG4EI32_V_M4_M2, VLOXSEG4EI32_V }, // 4167 |
| 25438 | { PseudoVLOXSEG4EI32_V_M4_M2_MASK, VLOXSEG4EI32_V }, // 4168 |
| 25439 | { PseudoVLOXSEG4EI32_V_M8_M2, VLOXSEG4EI32_V }, // 4169 |
| 25440 | { PseudoVLOXSEG4EI32_V_M8_M2_MASK, VLOXSEG4EI32_V }, // 4170 |
| 25441 | { PseudoVLOXSEG4EI32_V_MF2_M1, VLOXSEG4EI32_V }, // 4171 |
| 25442 | { PseudoVLOXSEG4EI32_V_MF2_M1_MASK, VLOXSEG4EI32_V }, // 4172 |
| 25443 | { PseudoVLOXSEG4EI32_V_MF2_MF2, VLOXSEG4EI32_V }, // 4173 |
| 25444 | { PseudoVLOXSEG4EI32_V_MF2_MF2_MASK, VLOXSEG4EI32_V }, // 4174 |
| 25445 | { PseudoVLOXSEG4EI32_V_MF2_MF4, VLOXSEG4EI32_V }, // 4175 |
| 25446 | { PseudoVLOXSEG4EI32_V_MF2_MF4_MASK, VLOXSEG4EI32_V }, // 4176 |
| 25447 | { PseudoVLOXSEG4EI32_V_MF2_MF8, VLOXSEG4EI32_V }, // 4177 |
| 25448 | { PseudoVLOXSEG4EI32_V_MF2_MF8_MASK, VLOXSEG4EI32_V }, // 4178 |
| 25449 | { PseudoVLOXSEG4EI64_V_M1_M1, VLOXSEG4EI64_V }, // 4179 |
| 25450 | { PseudoVLOXSEG4EI64_V_M1_M1_MASK, VLOXSEG4EI64_V }, // 4180 |
| 25451 | { PseudoVLOXSEG4EI64_V_M1_MF2, VLOXSEG4EI64_V }, // 4181 |
| 25452 | { PseudoVLOXSEG4EI64_V_M1_MF2_MASK, VLOXSEG4EI64_V }, // 4182 |
| 25453 | { PseudoVLOXSEG4EI64_V_M1_MF4, VLOXSEG4EI64_V }, // 4183 |
| 25454 | { PseudoVLOXSEG4EI64_V_M1_MF4_MASK, VLOXSEG4EI64_V }, // 4184 |
| 25455 | { PseudoVLOXSEG4EI64_V_M1_MF8, VLOXSEG4EI64_V }, // 4185 |
| 25456 | { PseudoVLOXSEG4EI64_V_M1_MF8_MASK, VLOXSEG4EI64_V }, // 4186 |
| 25457 | { PseudoVLOXSEG4EI64_V_M2_M1, VLOXSEG4EI64_V }, // 4187 |
| 25458 | { PseudoVLOXSEG4EI64_V_M2_M1_MASK, VLOXSEG4EI64_V }, // 4188 |
| 25459 | { PseudoVLOXSEG4EI64_V_M2_M2, VLOXSEG4EI64_V }, // 4189 |
| 25460 | { PseudoVLOXSEG4EI64_V_M2_M2_MASK, VLOXSEG4EI64_V }, // 4190 |
| 25461 | { PseudoVLOXSEG4EI64_V_M2_MF2, VLOXSEG4EI64_V }, // 4191 |
| 25462 | { PseudoVLOXSEG4EI64_V_M2_MF2_MASK, VLOXSEG4EI64_V }, // 4192 |
| 25463 | { PseudoVLOXSEG4EI64_V_M2_MF4, VLOXSEG4EI64_V }, // 4193 |
| 25464 | { PseudoVLOXSEG4EI64_V_M2_MF4_MASK, VLOXSEG4EI64_V }, // 4194 |
| 25465 | { PseudoVLOXSEG4EI64_V_M4_M1, VLOXSEG4EI64_V }, // 4195 |
| 25466 | { PseudoVLOXSEG4EI64_V_M4_M1_MASK, VLOXSEG4EI64_V }, // 4196 |
| 25467 | { PseudoVLOXSEG4EI64_V_M4_M2, VLOXSEG4EI64_V }, // 4197 |
| 25468 | { PseudoVLOXSEG4EI64_V_M4_M2_MASK, VLOXSEG4EI64_V }, // 4198 |
| 25469 | { PseudoVLOXSEG4EI64_V_M4_MF2, VLOXSEG4EI64_V }, // 4199 |
| 25470 | { PseudoVLOXSEG4EI64_V_M4_MF2_MASK, VLOXSEG4EI64_V }, // 4200 |
| 25471 | { PseudoVLOXSEG4EI64_V_M8_M1, VLOXSEG4EI64_V }, // 4201 |
| 25472 | { PseudoVLOXSEG4EI64_V_M8_M1_MASK, VLOXSEG4EI64_V }, // 4202 |
| 25473 | { PseudoVLOXSEG4EI64_V_M8_M2, VLOXSEG4EI64_V }, // 4203 |
| 25474 | { PseudoVLOXSEG4EI64_V_M8_M2_MASK, VLOXSEG4EI64_V }, // 4204 |
| 25475 | { PseudoVLOXSEG4EI8_V_M1_M1, VLOXSEG4EI8_V }, // 4205 |
| 25476 | { PseudoVLOXSEG4EI8_V_M1_M1_MASK, VLOXSEG4EI8_V }, // 4206 |
| 25477 | { PseudoVLOXSEG4EI8_V_M1_M2, VLOXSEG4EI8_V }, // 4207 |
| 25478 | { PseudoVLOXSEG4EI8_V_M1_M2_MASK, VLOXSEG4EI8_V }, // 4208 |
| 25479 | { PseudoVLOXSEG4EI8_V_M2_M2, VLOXSEG4EI8_V }, // 4209 |
| 25480 | { PseudoVLOXSEG4EI8_V_M2_M2_MASK, VLOXSEG4EI8_V }, // 4210 |
| 25481 | { PseudoVLOXSEG4EI8_V_MF2_M1, VLOXSEG4EI8_V }, // 4211 |
| 25482 | { PseudoVLOXSEG4EI8_V_MF2_M1_MASK, VLOXSEG4EI8_V }, // 4212 |
| 25483 | { PseudoVLOXSEG4EI8_V_MF2_M2, VLOXSEG4EI8_V }, // 4213 |
| 25484 | { PseudoVLOXSEG4EI8_V_MF2_M2_MASK, VLOXSEG4EI8_V }, // 4214 |
| 25485 | { PseudoVLOXSEG4EI8_V_MF2_MF2, VLOXSEG4EI8_V }, // 4215 |
| 25486 | { PseudoVLOXSEG4EI8_V_MF2_MF2_MASK, VLOXSEG4EI8_V }, // 4216 |
| 25487 | { PseudoVLOXSEG4EI8_V_MF4_M1, VLOXSEG4EI8_V }, // 4217 |
| 25488 | { PseudoVLOXSEG4EI8_V_MF4_M1_MASK, VLOXSEG4EI8_V }, // 4218 |
| 25489 | { PseudoVLOXSEG4EI8_V_MF4_M2, VLOXSEG4EI8_V }, // 4219 |
| 25490 | { PseudoVLOXSEG4EI8_V_MF4_M2_MASK, VLOXSEG4EI8_V }, // 4220 |
| 25491 | { PseudoVLOXSEG4EI8_V_MF4_MF2, VLOXSEG4EI8_V }, // 4221 |
| 25492 | { PseudoVLOXSEG4EI8_V_MF4_MF2_MASK, VLOXSEG4EI8_V }, // 4222 |
| 25493 | { PseudoVLOXSEG4EI8_V_MF4_MF4, VLOXSEG4EI8_V }, // 4223 |
| 25494 | { PseudoVLOXSEG4EI8_V_MF4_MF4_MASK, VLOXSEG4EI8_V }, // 4224 |
| 25495 | { PseudoVLOXSEG4EI8_V_MF8_M1, VLOXSEG4EI8_V }, // 4225 |
| 25496 | { PseudoVLOXSEG4EI8_V_MF8_M1_MASK, VLOXSEG4EI8_V }, // 4226 |
| 25497 | { PseudoVLOXSEG4EI8_V_MF8_MF2, VLOXSEG4EI8_V }, // 4227 |
| 25498 | { PseudoVLOXSEG4EI8_V_MF8_MF2_MASK, VLOXSEG4EI8_V }, // 4228 |
| 25499 | { PseudoVLOXSEG4EI8_V_MF8_MF4, VLOXSEG4EI8_V }, // 4229 |
| 25500 | { PseudoVLOXSEG4EI8_V_MF8_MF4_MASK, VLOXSEG4EI8_V }, // 4230 |
| 25501 | { PseudoVLOXSEG4EI8_V_MF8_MF8, VLOXSEG4EI8_V }, // 4231 |
| 25502 | { PseudoVLOXSEG4EI8_V_MF8_MF8_MASK, VLOXSEG4EI8_V }, // 4232 |
| 25503 | { PseudoVLOXSEG5EI16_V_M1_M1, VLOXSEG5EI16_V }, // 4233 |
| 25504 | { PseudoVLOXSEG5EI16_V_M1_M1_MASK, VLOXSEG5EI16_V }, // 4234 |
| 25505 | { PseudoVLOXSEG5EI16_V_M1_MF2, VLOXSEG5EI16_V }, // 4235 |
| 25506 | { PseudoVLOXSEG5EI16_V_M1_MF2_MASK, VLOXSEG5EI16_V }, // 4236 |
| 25507 | { PseudoVLOXSEG5EI16_V_M2_M1, VLOXSEG5EI16_V }, // 4237 |
| 25508 | { PseudoVLOXSEG5EI16_V_M2_M1_MASK, VLOXSEG5EI16_V }, // 4238 |
| 25509 | { PseudoVLOXSEG5EI16_V_MF2_M1, VLOXSEG5EI16_V }, // 4239 |
| 25510 | { PseudoVLOXSEG5EI16_V_MF2_M1_MASK, VLOXSEG5EI16_V }, // 4240 |
| 25511 | { PseudoVLOXSEG5EI16_V_MF2_MF2, VLOXSEG5EI16_V }, // 4241 |
| 25512 | { PseudoVLOXSEG5EI16_V_MF2_MF2_MASK, VLOXSEG5EI16_V }, // 4242 |
| 25513 | { PseudoVLOXSEG5EI16_V_MF2_MF4, VLOXSEG5EI16_V }, // 4243 |
| 25514 | { PseudoVLOXSEG5EI16_V_MF2_MF4_MASK, VLOXSEG5EI16_V }, // 4244 |
| 25515 | { PseudoVLOXSEG5EI16_V_MF4_M1, VLOXSEG5EI16_V }, // 4245 |
| 25516 | { PseudoVLOXSEG5EI16_V_MF4_M1_MASK, VLOXSEG5EI16_V }, // 4246 |
| 25517 | { PseudoVLOXSEG5EI16_V_MF4_MF2, VLOXSEG5EI16_V }, // 4247 |
| 25518 | { PseudoVLOXSEG5EI16_V_MF4_MF2_MASK, VLOXSEG5EI16_V }, // 4248 |
| 25519 | { PseudoVLOXSEG5EI16_V_MF4_MF4, VLOXSEG5EI16_V }, // 4249 |
| 25520 | { PseudoVLOXSEG5EI16_V_MF4_MF4_MASK, VLOXSEG5EI16_V }, // 4250 |
| 25521 | { PseudoVLOXSEG5EI16_V_MF4_MF8, VLOXSEG5EI16_V }, // 4251 |
| 25522 | { PseudoVLOXSEG5EI16_V_MF4_MF8_MASK, VLOXSEG5EI16_V }, // 4252 |
| 25523 | { PseudoVLOXSEG5EI32_V_M1_M1, VLOXSEG5EI32_V }, // 4253 |
| 25524 | { PseudoVLOXSEG5EI32_V_M1_M1_MASK, VLOXSEG5EI32_V }, // 4254 |
| 25525 | { PseudoVLOXSEG5EI32_V_M1_MF2, VLOXSEG5EI32_V }, // 4255 |
| 25526 | { PseudoVLOXSEG5EI32_V_M1_MF2_MASK, VLOXSEG5EI32_V }, // 4256 |
| 25527 | { PseudoVLOXSEG5EI32_V_M1_MF4, VLOXSEG5EI32_V }, // 4257 |
| 25528 | { PseudoVLOXSEG5EI32_V_M1_MF4_MASK, VLOXSEG5EI32_V }, // 4258 |
| 25529 | { PseudoVLOXSEG5EI32_V_M2_M1, VLOXSEG5EI32_V }, // 4259 |
| 25530 | { PseudoVLOXSEG5EI32_V_M2_M1_MASK, VLOXSEG5EI32_V }, // 4260 |
| 25531 | { PseudoVLOXSEG5EI32_V_M2_MF2, VLOXSEG5EI32_V }, // 4261 |
| 25532 | { PseudoVLOXSEG5EI32_V_M2_MF2_MASK, VLOXSEG5EI32_V }, // 4262 |
| 25533 | { PseudoVLOXSEG5EI32_V_M4_M1, VLOXSEG5EI32_V }, // 4263 |
| 25534 | { PseudoVLOXSEG5EI32_V_M4_M1_MASK, VLOXSEG5EI32_V }, // 4264 |
| 25535 | { PseudoVLOXSEG5EI32_V_MF2_M1, VLOXSEG5EI32_V }, // 4265 |
| 25536 | { PseudoVLOXSEG5EI32_V_MF2_M1_MASK, VLOXSEG5EI32_V }, // 4266 |
| 25537 | { PseudoVLOXSEG5EI32_V_MF2_MF2, VLOXSEG5EI32_V }, // 4267 |
| 25538 | { PseudoVLOXSEG5EI32_V_MF2_MF2_MASK, VLOXSEG5EI32_V }, // 4268 |
| 25539 | { PseudoVLOXSEG5EI32_V_MF2_MF4, VLOXSEG5EI32_V }, // 4269 |
| 25540 | { PseudoVLOXSEG5EI32_V_MF2_MF4_MASK, VLOXSEG5EI32_V }, // 4270 |
| 25541 | { PseudoVLOXSEG5EI32_V_MF2_MF8, VLOXSEG5EI32_V }, // 4271 |
| 25542 | { PseudoVLOXSEG5EI32_V_MF2_MF8_MASK, VLOXSEG5EI32_V }, // 4272 |
| 25543 | { PseudoVLOXSEG5EI64_V_M1_M1, VLOXSEG5EI64_V }, // 4273 |
| 25544 | { PseudoVLOXSEG5EI64_V_M1_M1_MASK, VLOXSEG5EI64_V }, // 4274 |
| 25545 | { PseudoVLOXSEG5EI64_V_M1_MF2, VLOXSEG5EI64_V }, // 4275 |
| 25546 | { PseudoVLOXSEG5EI64_V_M1_MF2_MASK, VLOXSEG5EI64_V }, // 4276 |
| 25547 | { PseudoVLOXSEG5EI64_V_M1_MF4, VLOXSEG5EI64_V }, // 4277 |
| 25548 | { PseudoVLOXSEG5EI64_V_M1_MF4_MASK, VLOXSEG5EI64_V }, // 4278 |
| 25549 | { PseudoVLOXSEG5EI64_V_M1_MF8, VLOXSEG5EI64_V }, // 4279 |
| 25550 | { PseudoVLOXSEG5EI64_V_M1_MF8_MASK, VLOXSEG5EI64_V }, // 4280 |
| 25551 | { PseudoVLOXSEG5EI64_V_M2_M1, VLOXSEG5EI64_V }, // 4281 |
| 25552 | { PseudoVLOXSEG5EI64_V_M2_M1_MASK, VLOXSEG5EI64_V }, // 4282 |
| 25553 | { PseudoVLOXSEG5EI64_V_M2_MF2, VLOXSEG5EI64_V }, // 4283 |
| 25554 | { PseudoVLOXSEG5EI64_V_M2_MF2_MASK, VLOXSEG5EI64_V }, // 4284 |
| 25555 | { PseudoVLOXSEG5EI64_V_M2_MF4, VLOXSEG5EI64_V }, // 4285 |
| 25556 | { PseudoVLOXSEG5EI64_V_M2_MF4_MASK, VLOXSEG5EI64_V }, // 4286 |
| 25557 | { PseudoVLOXSEG5EI64_V_M4_M1, VLOXSEG5EI64_V }, // 4287 |
| 25558 | { PseudoVLOXSEG5EI64_V_M4_M1_MASK, VLOXSEG5EI64_V }, // 4288 |
| 25559 | { PseudoVLOXSEG5EI64_V_M4_MF2, VLOXSEG5EI64_V }, // 4289 |
| 25560 | { PseudoVLOXSEG5EI64_V_M4_MF2_MASK, VLOXSEG5EI64_V }, // 4290 |
| 25561 | { PseudoVLOXSEG5EI64_V_M8_M1, VLOXSEG5EI64_V }, // 4291 |
| 25562 | { PseudoVLOXSEG5EI64_V_M8_M1_MASK, VLOXSEG5EI64_V }, // 4292 |
| 25563 | { PseudoVLOXSEG5EI8_V_M1_M1, VLOXSEG5EI8_V }, // 4293 |
| 25564 | { PseudoVLOXSEG5EI8_V_M1_M1_MASK, VLOXSEG5EI8_V }, // 4294 |
| 25565 | { PseudoVLOXSEG5EI8_V_MF2_M1, VLOXSEG5EI8_V }, // 4295 |
| 25566 | { PseudoVLOXSEG5EI8_V_MF2_M1_MASK, VLOXSEG5EI8_V }, // 4296 |
| 25567 | { PseudoVLOXSEG5EI8_V_MF2_MF2, VLOXSEG5EI8_V }, // 4297 |
| 25568 | { PseudoVLOXSEG5EI8_V_MF2_MF2_MASK, VLOXSEG5EI8_V }, // 4298 |
| 25569 | { PseudoVLOXSEG5EI8_V_MF4_M1, VLOXSEG5EI8_V }, // 4299 |
| 25570 | { PseudoVLOXSEG5EI8_V_MF4_M1_MASK, VLOXSEG5EI8_V }, // 4300 |
| 25571 | { PseudoVLOXSEG5EI8_V_MF4_MF2, VLOXSEG5EI8_V }, // 4301 |
| 25572 | { PseudoVLOXSEG5EI8_V_MF4_MF2_MASK, VLOXSEG5EI8_V }, // 4302 |
| 25573 | { PseudoVLOXSEG5EI8_V_MF4_MF4, VLOXSEG5EI8_V }, // 4303 |
| 25574 | { PseudoVLOXSEG5EI8_V_MF4_MF4_MASK, VLOXSEG5EI8_V }, // 4304 |
| 25575 | { PseudoVLOXSEG5EI8_V_MF8_M1, VLOXSEG5EI8_V }, // 4305 |
| 25576 | { PseudoVLOXSEG5EI8_V_MF8_M1_MASK, VLOXSEG5EI8_V }, // 4306 |
| 25577 | { PseudoVLOXSEG5EI8_V_MF8_MF2, VLOXSEG5EI8_V }, // 4307 |
| 25578 | { PseudoVLOXSEG5EI8_V_MF8_MF2_MASK, VLOXSEG5EI8_V }, // 4308 |
| 25579 | { PseudoVLOXSEG5EI8_V_MF8_MF4, VLOXSEG5EI8_V }, // 4309 |
| 25580 | { PseudoVLOXSEG5EI8_V_MF8_MF4_MASK, VLOXSEG5EI8_V }, // 4310 |
| 25581 | { PseudoVLOXSEG5EI8_V_MF8_MF8, VLOXSEG5EI8_V }, // 4311 |
| 25582 | { PseudoVLOXSEG5EI8_V_MF8_MF8_MASK, VLOXSEG5EI8_V }, // 4312 |
| 25583 | { PseudoVLOXSEG6EI16_V_M1_M1, VLOXSEG6EI16_V }, // 4313 |
| 25584 | { PseudoVLOXSEG6EI16_V_M1_M1_MASK, VLOXSEG6EI16_V }, // 4314 |
| 25585 | { PseudoVLOXSEG6EI16_V_M1_MF2, VLOXSEG6EI16_V }, // 4315 |
| 25586 | { PseudoVLOXSEG6EI16_V_M1_MF2_MASK, VLOXSEG6EI16_V }, // 4316 |
| 25587 | { PseudoVLOXSEG6EI16_V_M2_M1, VLOXSEG6EI16_V }, // 4317 |
| 25588 | { PseudoVLOXSEG6EI16_V_M2_M1_MASK, VLOXSEG6EI16_V }, // 4318 |
| 25589 | { PseudoVLOXSEG6EI16_V_MF2_M1, VLOXSEG6EI16_V }, // 4319 |
| 25590 | { PseudoVLOXSEG6EI16_V_MF2_M1_MASK, VLOXSEG6EI16_V }, // 4320 |
| 25591 | { PseudoVLOXSEG6EI16_V_MF2_MF2, VLOXSEG6EI16_V }, // 4321 |
| 25592 | { PseudoVLOXSEG6EI16_V_MF2_MF2_MASK, VLOXSEG6EI16_V }, // 4322 |
| 25593 | { PseudoVLOXSEG6EI16_V_MF2_MF4, VLOXSEG6EI16_V }, // 4323 |
| 25594 | { PseudoVLOXSEG6EI16_V_MF2_MF4_MASK, VLOXSEG6EI16_V }, // 4324 |
| 25595 | { PseudoVLOXSEG6EI16_V_MF4_M1, VLOXSEG6EI16_V }, // 4325 |
| 25596 | { PseudoVLOXSEG6EI16_V_MF4_M1_MASK, VLOXSEG6EI16_V }, // 4326 |
| 25597 | { PseudoVLOXSEG6EI16_V_MF4_MF2, VLOXSEG6EI16_V }, // 4327 |
| 25598 | { PseudoVLOXSEG6EI16_V_MF4_MF2_MASK, VLOXSEG6EI16_V }, // 4328 |
| 25599 | { PseudoVLOXSEG6EI16_V_MF4_MF4, VLOXSEG6EI16_V }, // 4329 |
| 25600 | { PseudoVLOXSEG6EI16_V_MF4_MF4_MASK, VLOXSEG6EI16_V }, // 4330 |
| 25601 | { PseudoVLOXSEG6EI16_V_MF4_MF8, VLOXSEG6EI16_V }, // 4331 |
| 25602 | { PseudoVLOXSEG6EI16_V_MF4_MF8_MASK, VLOXSEG6EI16_V }, // 4332 |
| 25603 | { PseudoVLOXSEG6EI32_V_M1_M1, VLOXSEG6EI32_V }, // 4333 |
| 25604 | { PseudoVLOXSEG6EI32_V_M1_M1_MASK, VLOXSEG6EI32_V }, // 4334 |
| 25605 | { PseudoVLOXSEG6EI32_V_M1_MF2, VLOXSEG6EI32_V }, // 4335 |
| 25606 | { PseudoVLOXSEG6EI32_V_M1_MF2_MASK, VLOXSEG6EI32_V }, // 4336 |
| 25607 | { PseudoVLOXSEG6EI32_V_M1_MF4, VLOXSEG6EI32_V }, // 4337 |
| 25608 | { PseudoVLOXSEG6EI32_V_M1_MF4_MASK, VLOXSEG6EI32_V }, // 4338 |
| 25609 | { PseudoVLOXSEG6EI32_V_M2_M1, VLOXSEG6EI32_V }, // 4339 |
| 25610 | { PseudoVLOXSEG6EI32_V_M2_M1_MASK, VLOXSEG6EI32_V }, // 4340 |
| 25611 | { PseudoVLOXSEG6EI32_V_M2_MF2, VLOXSEG6EI32_V }, // 4341 |
| 25612 | { PseudoVLOXSEG6EI32_V_M2_MF2_MASK, VLOXSEG6EI32_V }, // 4342 |
| 25613 | { PseudoVLOXSEG6EI32_V_M4_M1, VLOXSEG6EI32_V }, // 4343 |
| 25614 | { PseudoVLOXSEG6EI32_V_M4_M1_MASK, VLOXSEG6EI32_V }, // 4344 |
| 25615 | { PseudoVLOXSEG6EI32_V_MF2_M1, VLOXSEG6EI32_V }, // 4345 |
| 25616 | { PseudoVLOXSEG6EI32_V_MF2_M1_MASK, VLOXSEG6EI32_V }, // 4346 |
| 25617 | { PseudoVLOXSEG6EI32_V_MF2_MF2, VLOXSEG6EI32_V }, // 4347 |
| 25618 | { PseudoVLOXSEG6EI32_V_MF2_MF2_MASK, VLOXSEG6EI32_V }, // 4348 |
| 25619 | { PseudoVLOXSEG6EI32_V_MF2_MF4, VLOXSEG6EI32_V }, // 4349 |
| 25620 | { PseudoVLOXSEG6EI32_V_MF2_MF4_MASK, VLOXSEG6EI32_V }, // 4350 |
| 25621 | { PseudoVLOXSEG6EI32_V_MF2_MF8, VLOXSEG6EI32_V }, // 4351 |
| 25622 | { PseudoVLOXSEG6EI32_V_MF2_MF8_MASK, VLOXSEG6EI32_V }, // 4352 |
| 25623 | { PseudoVLOXSEG6EI64_V_M1_M1, VLOXSEG6EI64_V }, // 4353 |
| 25624 | { PseudoVLOXSEG6EI64_V_M1_M1_MASK, VLOXSEG6EI64_V }, // 4354 |
| 25625 | { PseudoVLOXSEG6EI64_V_M1_MF2, VLOXSEG6EI64_V }, // 4355 |
| 25626 | { PseudoVLOXSEG6EI64_V_M1_MF2_MASK, VLOXSEG6EI64_V }, // 4356 |
| 25627 | { PseudoVLOXSEG6EI64_V_M1_MF4, VLOXSEG6EI64_V }, // 4357 |
| 25628 | { PseudoVLOXSEG6EI64_V_M1_MF4_MASK, VLOXSEG6EI64_V }, // 4358 |
| 25629 | { PseudoVLOXSEG6EI64_V_M1_MF8, VLOXSEG6EI64_V }, // 4359 |
| 25630 | { PseudoVLOXSEG6EI64_V_M1_MF8_MASK, VLOXSEG6EI64_V }, // 4360 |
| 25631 | { PseudoVLOXSEG6EI64_V_M2_M1, VLOXSEG6EI64_V }, // 4361 |
| 25632 | { PseudoVLOXSEG6EI64_V_M2_M1_MASK, VLOXSEG6EI64_V }, // 4362 |
| 25633 | { PseudoVLOXSEG6EI64_V_M2_MF2, VLOXSEG6EI64_V }, // 4363 |
| 25634 | { PseudoVLOXSEG6EI64_V_M2_MF2_MASK, VLOXSEG6EI64_V }, // 4364 |
| 25635 | { PseudoVLOXSEG6EI64_V_M2_MF4, VLOXSEG6EI64_V }, // 4365 |
| 25636 | { PseudoVLOXSEG6EI64_V_M2_MF4_MASK, VLOXSEG6EI64_V }, // 4366 |
| 25637 | { PseudoVLOXSEG6EI64_V_M4_M1, VLOXSEG6EI64_V }, // 4367 |
| 25638 | { PseudoVLOXSEG6EI64_V_M4_M1_MASK, VLOXSEG6EI64_V }, // 4368 |
| 25639 | { PseudoVLOXSEG6EI64_V_M4_MF2, VLOXSEG6EI64_V }, // 4369 |
| 25640 | { PseudoVLOXSEG6EI64_V_M4_MF2_MASK, VLOXSEG6EI64_V }, // 4370 |
| 25641 | { PseudoVLOXSEG6EI64_V_M8_M1, VLOXSEG6EI64_V }, // 4371 |
| 25642 | { PseudoVLOXSEG6EI64_V_M8_M1_MASK, VLOXSEG6EI64_V }, // 4372 |
| 25643 | { PseudoVLOXSEG6EI8_V_M1_M1, VLOXSEG6EI8_V }, // 4373 |
| 25644 | { PseudoVLOXSEG6EI8_V_M1_M1_MASK, VLOXSEG6EI8_V }, // 4374 |
| 25645 | { PseudoVLOXSEG6EI8_V_MF2_M1, VLOXSEG6EI8_V }, // 4375 |
| 25646 | { PseudoVLOXSEG6EI8_V_MF2_M1_MASK, VLOXSEG6EI8_V }, // 4376 |
| 25647 | { PseudoVLOXSEG6EI8_V_MF2_MF2, VLOXSEG6EI8_V }, // 4377 |
| 25648 | { PseudoVLOXSEG6EI8_V_MF2_MF2_MASK, VLOXSEG6EI8_V }, // 4378 |
| 25649 | { PseudoVLOXSEG6EI8_V_MF4_M1, VLOXSEG6EI8_V }, // 4379 |
| 25650 | { PseudoVLOXSEG6EI8_V_MF4_M1_MASK, VLOXSEG6EI8_V }, // 4380 |
| 25651 | { PseudoVLOXSEG6EI8_V_MF4_MF2, VLOXSEG6EI8_V }, // 4381 |
| 25652 | { PseudoVLOXSEG6EI8_V_MF4_MF2_MASK, VLOXSEG6EI8_V }, // 4382 |
| 25653 | { PseudoVLOXSEG6EI8_V_MF4_MF4, VLOXSEG6EI8_V }, // 4383 |
| 25654 | { PseudoVLOXSEG6EI8_V_MF4_MF4_MASK, VLOXSEG6EI8_V }, // 4384 |
| 25655 | { PseudoVLOXSEG6EI8_V_MF8_M1, VLOXSEG6EI8_V }, // 4385 |
| 25656 | { PseudoVLOXSEG6EI8_V_MF8_M1_MASK, VLOXSEG6EI8_V }, // 4386 |
| 25657 | { PseudoVLOXSEG6EI8_V_MF8_MF2, VLOXSEG6EI8_V }, // 4387 |
| 25658 | { PseudoVLOXSEG6EI8_V_MF8_MF2_MASK, VLOXSEG6EI8_V }, // 4388 |
| 25659 | { PseudoVLOXSEG6EI8_V_MF8_MF4, VLOXSEG6EI8_V }, // 4389 |
| 25660 | { PseudoVLOXSEG6EI8_V_MF8_MF4_MASK, VLOXSEG6EI8_V }, // 4390 |
| 25661 | { PseudoVLOXSEG6EI8_V_MF8_MF8, VLOXSEG6EI8_V }, // 4391 |
| 25662 | { PseudoVLOXSEG6EI8_V_MF8_MF8_MASK, VLOXSEG6EI8_V }, // 4392 |
| 25663 | { PseudoVLOXSEG7EI16_V_M1_M1, VLOXSEG7EI16_V }, // 4393 |
| 25664 | { PseudoVLOXSEG7EI16_V_M1_M1_MASK, VLOXSEG7EI16_V }, // 4394 |
| 25665 | { PseudoVLOXSEG7EI16_V_M1_MF2, VLOXSEG7EI16_V }, // 4395 |
| 25666 | { PseudoVLOXSEG7EI16_V_M1_MF2_MASK, VLOXSEG7EI16_V }, // 4396 |
| 25667 | { PseudoVLOXSEG7EI16_V_M2_M1, VLOXSEG7EI16_V }, // 4397 |
| 25668 | { PseudoVLOXSEG7EI16_V_M2_M1_MASK, VLOXSEG7EI16_V }, // 4398 |
| 25669 | { PseudoVLOXSEG7EI16_V_MF2_M1, VLOXSEG7EI16_V }, // 4399 |
| 25670 | { PseudoVLOXSEG7EI16_V_MF2_M1_MASK, VLOXSEG7EI16_V }, // 4400 |
| 25671 | { PseudoVLOXSEG7EI16_V_MF2_MF2, VLOXSEG7EI16_V }, // 4401 |
| 25672 | { PseudoVLOXSEG7EI16_V_MF2_MF2_MASK, VLOXSEG7EI16_V }, // 4402 |
| 25673 | { PseudoVLOXSEG7EI16_V_MF2_MF4, VLOXSEG7EI16_V }, // 4403 |
| 25674 | { PseudoVLOXSEG7EI16_V_MF2_MF4_MASK, VLOXSEG7EI16_V }, // 4404 |
| 25675 | { PseudoVLOXSEG7EI16_V_MF4_M1, VLOXSEG7EI16_V }, // 4405 |
| 25676 | { PseudoVLOXSEG7EI16_V_MF4_M1_MASK, VLOXSEG7EI16_V }, // 4406 |
| 25677 | { PseudoVLOXSEG7EI16_V_MF4_MF2, VLOXSEG7EI16_V }, // 4407 |
| 25678 | { PseudoVLOXSEG7EI16_V_MF4_MF2_MASK, VLOXSEG7EI16_V }, // 4408 |
| 25679 | { PseudoVLOXSEG7EI16_V_MF4_MF4, VLOXSEG7EI16_V }, // 4409 |
| 25680 | { PseudoVLOXSEG7EI16_V_MF4_MF4_MASK, VLOXSEG7EI16_V }, // 4410 |
| 25681 | { PseudoVLOXSEG7EI16_V_MF4_MF8, VLOXSEG7EI16_V }, // 4411 |
| 25682 | { PseudoVLOXSEG7EI16_V_MF4_MF8_MASK, VLOXSEG7EI16_V }, // 4412 |
| 25683 | { PseudoVLOXSEG7EI32_V_M1_M1, VLOXSEG7EI32_V }, // 4413 |
| 25684 | { PseudoVLOXSEG7EI32_V_M1_M1_MASK, VLOXSEG7EI32_V }, // 4414 |
| 25685 | { PseudoVLOXSEG7EI32_V_M1_MF2, VLOXSEG7EI32_V }, // 4415 |
| 25686 | { PseudoVLOXSEG7EI32_V_M1_MF2_MASK, VLOXSEG7EI32_V }, // 4416 |
| 25687 | { PseudoVLOXSEG7EI32_V_M1_MF4, VLOXSEG7EI32_V }, // 4417 |
| 25688 | { PseudoVLOXSEG7EI32_V_M1_MF4_MASK, VLOXSEG7EI32_V }, // 4418 |
| 25689 | { PseudoVLOXSEG7EI32_V_M2_M1, VLOXSEG7EI32_V }, // 4419 |
| 25690 | { PseudoVLOXSEG7EI32_V_M2_M1_MASK, VLOXSEG7EI32_V }, // 4420 |
| 25691 | { PseudoVLOXSEG7EI32_V_M2_MF2, VLOXSEG7EI32_V }, // 4421 |
| 25692 | { PseudoVLOXSEG7EI32_V_M2_MF2_MASK, VLOXSEG7EI32_V }, // 4422 |
| 25693 | { PseudoVLOXSEG7EI32_V_M4_M1, VLOXSEG7EI32_V }, // 4423 |
| 25694 | { PseudoVLOXSEG7EI32_V_M4_M1_MASK, VLOXSEG7EI32_V }, // 4424 |
| 25695 | { PseudoVLOXSEG7EI32_V_MF2_M1, VLOXSEG7EI32_V }, // 4425 |
| 25696 | { PseudoVLOXSEG7EI32_V_MF2_M1_MASK, VLOXSEG7EI32_V }, // 4426 |
| 25697 | { PseudoVLOXSEG7EI32_V_MF2_MF2, VLOXSEG7EI32_V }, // 4427 |
| 25698 | { PseudoVLOXSEG7EI32_V_MF2_MF2_MASK, VLOXSEG7EI32_V }, // 4428 |
| 25699 | { PseudoVLOXSEG7EI32_V_MF2_MF4, VLOXSEG7EI32_V }, // 4429 |
| 25700 | { PseudoVLOXSEG7EI32_V_MF2_MF4_MASK, VLOXSEG7EI32_V }, // 4430 |
| 25701 | { PseudoVLOXSEG7EI32_V_MF2_MF8, VLOXSEG7EI32_V }, // 4431 |
| 25702 | { PseudoVLOXSEG7EI32_V_MF2_MF8_MASK, VLOXSEG7EI32_V }, // 4432 |
| 25703 | { PseudoVLOXSEG7EI64_V_M1_M1, VLOXSEG7EI64_V }, // 4433 |
| 25704 | { PseudoVLOXSEG7EI64_V_M1_M1_MASK, VLOXSEG7EI64_V }, // 4434 |
| 25705 | { PseudoVLOXSEG7EI64_V_M1_MF2, VLOXSEG7EI64_V }, // 4435 |
| 25706 | { PseudoVLOXSEG7EI64_V_M1_MF2_MASK, VLOXSEG7EI64_V }, // 4436 |
| 25707 | { PseudoVLOXSEG7EI64_V_M1_MF4, VLOXSEG7EI64_V }, // 4437 |
| 25708 | { PseudoVLOXSEG7EI64_V_M1_MF4_MASK, VLOXSEG7EI64_V }, // 4438 |
| 25709 | { PseudoVLOXSEG7EI64_V_M1_MF8, VLOXSEG7EI64_V }, // 4439 |
| 25710 | { PseudoVLOXSEG7EI64_V_M1_MF8_MASK, VLOXSEG7EI64_V }, // 4440 |
| 25711 | { PseudoVLOXSEG7EI64_V_M2_M1, VLOXSEG7EI64_V }, // 4441 |
| 25712 | { PseudoVLOXSEG7EI64_V_M2_M1_MASK, VLOXSEG7EI64_V }, // 4442 |
| 25713 | { PseudoVLOXSEG7EI64_V_M2_MF2, VLOXSEG7EI64_V }, // 4443 |
| 25714 | { PseudoVLOXSEG7EI64_V_M2_MF2_MASK, VLOXSEG7EI64_V }, // 4444 |
| 25715 | { PseudoVLOXSEG7EI64_V_M2_MF4, VLOXSEG7EI64_V }, // 4445 |
| 25716 | { PseudoVLOXSEG7EI64_V_M2_MF4_MASK, VLOXSEG7EI64_V }, // 4446 |
| 25717 | { PseudoVLOXSEG7EI64_V_M4_M1, VLOXSEG7EI64_V }, // 4447 |
| 25718 | { PseudoVLOXSEG7EI64_V_M4_M1_MASK, VLOXSEG7EI64_V }, // 4448 |
| 25719 | { PseudoVLOXSEG7EI64_V_M4_MF2, VLOXSEG7EI64_V }, // 4449 |
| 25720 | { PseudoVLOXSEG7EI64_V_M4_MF2_MASK, VLOXSEG7EI64_V }, // 4450 |
| 25721 | { PseudoVLOXSEG7EI64_V_M8_M1, VLOXSEG7EI64_V }, // 4451 |
| 25722 | { PseudoVLOXSEG7EI64_V_M8_M1_MASK, VLOXSEG7EI64_V }, // 4452 |
| 25723 | { PseudoVLOXSEG7EI8_V_M1_M1, VLOXSEG7EI8_V }, // 4453 |
| 25724 | { PseudoVLOXSEG7EI8_V_M1_M1_MASK, VLOXSEG7EI8_V }, // 4454 |
| 25725 | { PseudoVLOXSEG7EI8_V_MF2_M1, VLOXSEG7EI8_V }, // 4455 |
| 25726 | { PseudoVLOXSEG7EI8_V_MF2_M1_MASK, VLOXSEG7EI8_V }, // 4456 |
| 25727 | { PseudoVLOXSEG7EI8_V_MF2_MF2, VLOXSEG7EI8_V }, // 4457 |
| 25728 | { PseudoVLOXSEG7EI8_V_MF2_MF2_MASK, VLOXSEG7EI8_V }, // 4458 |
| 25729 | { PseudoVLOXSEG7EI8_V_MF4_M1, VLOXSEG7EI8_V }, // 4459 |
| 25730 | { PseudoVLOXSEG7EI8_V_MF4_M1_MASK, VLOXSEG7EI8_V }, // 4460 |
| 25731 | { PseudoVLOXSEG7EI8_V_MF4_MF2, VLOXSEG7EI8_V }, // 4461 |
| 25732 | { PseudoVLOXSEG7EI8_V_MF4_MF2_MASK, VLOXSEG7EI8_V }, // 4462 |
| 25733 | { PseudoVLOXSEG7EI8_V_MF4_MF4, VLOXSEG7EI8_V }, // 4463 |
| 25734 | { PseudoVLOXSEG7EI8_V_MF4_MF4_MASK, VLOXSEG7EI8_V }, // 4464 |
| 25735 | { PseudoVLOXSEG7EI8_V_MF8_M1, VLOXSEG7EI8_V }, // 4465 |
| 25736 | { PseudoVLOXSEG7EI8_V_MF8_M1_MASK, VLOXSEG7EI8_V }, // 4466 |
| 25737 | { PseudoVLOXSEG7EI8_V_MF8_MF2, VLOXSEG7EI8_V }, // 4467 |
| 25738 | { PseudoVLOXSEG7EI8_V_MF8_MF2_MASK, VLOXSEG7EI8_V }, // 4468 |
| 25739 | { PseudoVLOXSEG7EI8_V_MF8_MF4, VLOXSEG7EI8_V }, // 4469 |
| 25740 | { PseudoVLOXSEG7EI8_V_MF8_MF4_MASK, VLOXSEG7EI8_V }, // 4470 |
| 25741 | { PseudoVLOXSEG7EI8_V_MF8_MF8, VLOXSEG7EI8_V }, // 4471 |
| 25742 | { PseudoVLOXSEG7EI8_V_MF8_MF8_MASK, VLOXSEG7EI8_V }, // 4472 |
| 25743 | { PseudoVLOXSEG8EI16_V_M1_M1, VLOXSEG8EI16_V }, // 4473 |
| 25744 | { PseudoVLOXSEG8EI16_V_M1_M1_MASK, VLOXSEG8EI16_V }, // 4474 |
| 25745 | { PseudoVLOXSEG8EI16_V_M1_MF2, VLOXSEG8EI16_V }, // 4475 |
| 25746 | { PseudoVLOXSEG8EI16_V_M1_MF2_MASK, VLOXSEG8EI16_V }, // 4476 |
| 25747 | { PseudoVLOXSEG8EI16_V_M2_M1, VLOXSEG8EI16_V }, // 4477 |
| 25748 | { PseudoVLOXSEG8EI16_V_M2_M1_MASK, VLOXSEG8EI16_V }, // 4478 |
| 25749 | { PseudoVLOXSEG8EI16_V_MF2_M1, VLOXSEG8EI16_V }, // 4479 |
| 25750 | { PseudoVLOXSEG8EI16_V_MF2_M1_MASK, VLOXSEG8EI16_V }, // 4480 |
| 25751 | { PseudoVLOXSEG8EI16_V_MF2_MF2, VLOXSEG8EI16_V }, // 4481 |
| 25752 | { PseudoVLOXSEG8EI16_V_MF2_MF2_MASK, VLOXSEG8EI16_V }, // 4482 |
| 25753 | { PseudoVLOXSEG8EI16_V_MF2_MF4, VLOXSEG8EI16_V }, // 4483 |
| 25754 | { PseudoVLOXSEG8EI16_V_MF2_MF4_MASK, VLOXSEG8EI16_V }, // 4484 |
| 25755 | { PseudoVLOXSEG8EI16_V_MF4_M1, VLOXSEG8EI16_V }, // 4485 |
| 25756 | { PseudoVLOXSEG8EI16_V_MF4_M1_MASK, VLOXSEG8EI16_V }, // 4486 |
| 25757 | { PseudoVLOXSEG8EI16_V_MF4_MF2, VLOXSEG8EI16_V }, // 4487 |
| 25758 | { PseudoVLOXSEG8EI16_V_MF4_MF2_MASK, VLOXSEG8EI16_V }, // 4488 |
| 25759 | { PseudoVLOXSEG8EI16_V_MF4_MF4, VLOXSEG8EI16_V }, // 4489 |
| 25760 | { PseudoVLOXSEG8EI16_V_MF4_MF4_MASK, VLOXSEG8EI16_V }, // 4490 |
| 25761 | { PseudoVLOXSEG8EI16_V_MF4_MF8, VLOXSEG8EI16_V }, // 4491 |
| 25762 | { PseudoVLOXSEG8EI16_V_MF4_MF8_MASK, VLOXSEG8EI16_V }, // 4492 |
| 25763 | { PseudoVLOXSEG8EI32_V_M1_M1, VLOXSEG8EI32_V }, // 4493 |
| 25764 | { PseudoVLOXSEG8EI32_V_M1_M1_MASK, VLOXSEG8EI32_V }, // 4494 |
| 25765 | { PseudoVLOXSEG8EI32_V_M1_MF2, VLOXSEG8EI32_V }, // 4495 |
| 25766 | { PseudoVLOXSEG8EI32_V_M1_MF2_MASK, VLOXSEG8EI32_V }, // 4496 |
| 25767 | { PseudoVLOXSEG8EI32_V_M1_MF4, VLOXSEG8EI32_V }, // 4497 |
| 25768 | { PseudoVLOXSEG8EI32_V_M1_MF4_MASK, VLOXSEG8EI32_V }, // 4498 |
| 25769 | { PseudoVLOXSEG8EI32_V_M2_M1, VLOXSEG8EI32_V }, // 4499 |
| 25770 | { PseudoVLOXSEG8EI32_V_M2_M1_MASK, VLOXSEG8EI32_V }, // 4500 |
| 25771 | { PseudoVLOXSEG8EI32_V_M2_MF2, VLOXSEG8EI32_V }, // 4501 |
| 25772 | { PseudoVLOXSEG8EI32_V_M2_MF2_MASK, VLOXSEG8EI32_V }, // 4502 |
| 25773 | { PseudoVLOXSEG8EI32_V_M4_M1, VLOXSEG8EI32_V }, // 4503 |
| 25774 | { PseudoVLOXSEG8EI32_V_M4_M1_MASK, VLOXSEG8EI32_V }, // 4504 |
| 25775 | { PseudoVLOXSEG8EI32_V_MF2_M1, VLOXSEG8EI32_V }, // 4505 |
| 25776 | { PseudoVLOXSEG8EI32_V_MF2_M1_MASK, VLOXSEG8EI32_V }, // 4506 |
| 25777 | { PseudoVLOXSEG8EI32_V_MF2_MF2, VLOXSEG8EI32_V }, // 4507 |
| 25778 | { PseudoVLOXSEG8EI32_V_MF2_MF2_MASK, VLOXSEG8EI32_V }, // 4508 |
| 25779 | { PseudoVLOXSEG8EI32_V_MF2_MF4, VLOXSEG8EI32_V }, // 4509 |
| 25780 | { PseudoVLOXSEG8EI32_V_MF2_MF4_MASK, VLOXSEG8EI32_V }, // 4510 |
| 25781 | { PseudoVLOXSEG8EI32_V_MF2_MF8, VLOXSEG8EI32_V }, // 4511 |
| 25782 | { PseudoVLOXSEG8EI32_V_MF2_MF8_MASK, VLOXSEG8EI32_V }, // 4512 |
| 25783 | { PseudoVLOXSEG8EI64_V_M1_M1, VLOXSEG8EI64_V }, // 4513 |
| 25784 | { PseudoVLOXSEG8EI64_V_M1_M1_MASK, VLOXSEG8EI64_V }, // 4514 |
| 25785 | { PseudoVLOXSEG8EI64_V_M1_MF2, VLOXSEG8EI64_V }, // 4515 |
| 25786 | { PseudoVLOXSEG8EI64_V_M1_MF2_MASK, VLOXSEG8EI64_V }, // 4516 |
| 25787 | { PseudoVLOXSEG8EI64_V_M1_MF4, VLOXSEG8EI64_V }, // 4517 |
| 25788 | { PseudoVLOXSEG8EI64_V_M1_MF4_MASK, VLOXSEG8EI64_V }, // 4518 |
| 25789 | { PseudoVLOXSEG8EI64_V_M1_MF8, VLOXSEG8EI64_V }, // 4519 |
| 25790 | { PseudoVLOXSEG8EI64_V_M1_MF8_MASK, VLOXSEG8EI64_V }, // 4520 |
| 25791 | { PseudoVLOXSEG8EI64_V_M2_M1, VLOXSEG8EI64_V }, // 4521 |
| 25792 | { PseudoVLOXSEG8EI64_V_M2_M1_MASK, VLOXSEG8EI64_V }, // 4522 |
| 25793 | { PseudoVLOXSEG8EI64_V_M2_MF2, VLOXSEG8EI64_V }, // 4523 |
| 25794 | { PseudoVLOXSEG8EI64_V_M2_MF2_MASK, VLOXSEG8EI64_V }, // 4524 |
| 25795 | { PseudoVLOXSEG8EI64_V_M2_MF4, VLOXSEG8EI64_V }, // 4525 |
| 25796 | { PseudoVLOXSEG8EI64_V_M2_MF4_MASK, VLOXSEG8EI64_V }, // 4526 |
| 25797 | { PseudoVLOXSEG8EI64_V_M4_M1, VLOXSEG8EI64_V }, // 4527 |
| 25798 | { PseudoVLOXSEG8EI64_V_M4_M1_MASK, VLOXSEG8EI64_V }, // 4528 |
| 25799 | { PseudoVLOXSEG8EI64_V_M4_MF2, VLOXSEG8EI64_V }, // 4529 |
| 25800 | { PseudoVLOXSEG8EI64_V_M4_MF2_MASK, VLOXSEG8EI64_V }, // 4530 |
| 25801 | { PseudoVLOXSEG8EI64_V_M8_M1, VLOXSEG8EI64_V }, // 4531 |
| 25802 | { PseudoVLOXSEG8EI64_V_M8_M1_MASK, VLOXSEG8EI64_V }, // 4532 |
| 25803 | { PseudoVLOXSEG8EI8_V_M1_M1, VLOXSEG8EI8_V }, // 4533 |
| 25804 | { PseudoVLOXSEG8EI8_V_M1_M1_MASK, VLOXSEG8EI8_V }, // 4534 |
| 25805 | { PseudoVLOXSEG8EI8_V_MF2_M1, VLOXSEG8EI8_V }, // 4535 |
| 25806 | { PseudoVLOXSEG8EI8_V_MF2_M1_MASK, VLOXSEG8EI8_V }, // 4536 |
| 25807 | { PseudoVLOXSEG8EI8_V_MF2_MF2, VLOXSEG8EI8_V }, // 4537 |
| 25808 | { PseudoVLOXSEG8EI8_V_MF2_MF2_MASK, VLOXSEG8EI8_V }, // 4538 |
| 25809 | { PseudoVLOXSEG8EI8_V_MF4_M1, VLOXSEG8EI8_V }, // 4539 |
| 25810 | { PseudoVLOXSEG8EI8_V_MF4_M1_MASK, VLOXSEG8EI8_V }, // 4540 |
| 25811 | { PseudoVLOXSEG8EI8_V_MF4_MF2, VLOXSEG8EI8_V }, // 4541 |
| 25812 | { PseudoVLOXSEG8EI8_V_MF4_MF2_MASK, VLOXSEG8EI8_V }, // 4542 |
| 25813 | { PseudoVLOXSEG8EI8_V_MF4_MF4, VLOXSEG8EI8_V }, // 4543 |
| 25814 | { PseudoVLOXSEG8EI8_V_MF4_MF4_MASK, VLOXSEG8EI8_V }, // 4544 |
| 25815 | { PseudoVLOXSEG8EI8_V_MF8_M1, VLOXSEG8EI8_V }, // 4545 |
| 25816 | { PseudoVLOXSEG8EI8_V_MF8_M1_MASK, VLOXSEG8EI8_V }, // 4546 |
| 25817 | { PseudoVLOXSEG8EI8_V_MF8_MF2, VLOXSEG8EI8_V }, // 4547 |
| 25818 | { PseudoVLOXSEG8EI8_V_MF8_MF2_MASK, VLOXSEG8EI8_V }, // 4548 |
| 25819 | { PseudoVLOXSEG8EI8_V_MF8_MF4, VLOXSEG8EI8_V }, // 4549 |
| 25820 | { PseudoVLOXSEG8EI8_V_MF8_MF4_MASK, VLOXSEG8EI8_V }, // 4550 |
| 25821 | { PseudoVLOXSEG8EI8_V_MF8_MF8, VLOXSEG8EI8_V }, // 4551 |
| 25822 | { PseudoVLOXSEG8EI8_V_MF8_MF8_MASK, VLOXSEG8EI8_V }, // 4552 |
| 25823 | { PseudoVLSE16_V_M1, VLSE16_V }, // 4553 |
| 25824 | { PseudoVLSE16_V_M1_MASK, VLSE16_V }, // 4554 |
| 25825 | { PseudoVLSE16_V_M2, VLSE16_V }, // 4555 |
| 25826 | { PseudoVLSE16_V_M2_MASK, VLSE16_V }, // 4556 |
| 25827 | { PseudoVLSE16_V_M4, VLSE16_V }, // 4557 |
| 25828 | { PseudoVLSE16_V_M4_MASK, VLSE16_V }, // 4558 |
| 25829 | { PseudoVLSE16_V_M8, VLSE16_V }, // 4559 |
| 25830 | { PseudoVLSE16_V_M8_MASK, VLSE16_V }, // 4560 |
| 25831 | { PseudoVLSE16_V_MF2, VLSE16_V }, // 4561 |
| 25832 | { PseudoVLSE16_V_MF2_MASK, VLSE16_V }, // 4562 |
| 25833 | { PseudoVLSE16_V_MF4, VLSE16_V }, // 4563 |
| 25834 | { PseudoVLSE16_V_MF4_MASK, VLSE16_V }, // 4564 |
| 25835 | { PseudoVLSE32_V_M1, VLSE32_V }, // 4565 |
| 25836 | { PseudoVLSE32_V_M1_MASK, VLSE32_V }, // 4566 |
| 25837 | { PseudoVLSE32_V_M2, VLSE32_V }, // 4567 |
| 25838 | { PseudoVLSE32_V_M2_MASK, VLSE32_V }, // 4568 |
| 25839 | { PseudoVLSE32_V_M4, VLSE32_V }, // 4569 |
| 25840 | { PseudoVLSE32_V_M4_MASK, VLSE32_V }, // 4570 |
| 25841 | { PseudoVLSE32_V_M8, VLSE32_V }, // 4571 |
| 25842 | { PseudoVLSE32_V_M8_MASK, VLSE32_V }, // 4572 |
| 25843 | { PseudoVLSE32_V_MF2, VLSE32_V }, // 4573 |
| 25844 | { PseudoVLSE32_V_MF2_MASK, VLSE32_V }, // 4574 |
| 25845 | { PseudoVLSE64_V_M1, VLSE64_V }, // 4575 |
| 25846 | { PseudoVLSE64_V_M1_MASK, VLSE64_V }, // 4576 |
| 25847 | { PseudoVLSE64_V_M2, VLSE64_V }, // 4577 |
| 25848 | { PseudoVLSE64_V_M2_MASK, VLSE64_V }, // 4578 |
| 25849 | { PseudoVLSE64_V_M4, VLSE64_V }, // 4579 |
| 25850 | { PseudoVLSE64_V_M4_MASK, VLSE64_V }, // 4580 |
| 25851 | { PseudoVLSE64_V_M8, VLSE64_V }, // 4581 |
| 25852 | { PseudoVLSE64_V_M8_MASK, VLSE64_V }, // 4582 |
| 25853 | { PseudoVLSE8_V_M1, VLSE8_V }, // 4583 |
| 25854 | { PseudoVLSE8_V_M1_MASK, VLSE8_V }, // 4584 |
| 25855 | { PseudoVLSE8_V_M2, VLSE8_V }, // 4585 |
| 25856 | { PseudoVLSE8_V_M2_MASK, VLSE8_V }, // 4586 |
| 25857 | { PseudoVLSE8_V_M4, VLSE8_V }, // 4587 |
| 25858 | { PseudoVLSE8_V_M4_MASK, VLSE8_V }, // 4588 |
| 25859 | { PseudoVLSE8_V_M8, VLSE8_V }, // 4589 |
| 25860 | { PseudoVLSE8_V_M8_MASK, VLSE8_V }, // 4590 |
| 25861 | { PseudoVLSE8_V_MF2, VLSE8_V }, // 4591 |
| 25862 | { PseudoVLSE8_V_MF2_MASK, VLSE8_V }, // 4592 |
| 25863 | { PseudoVLSE8_V_MF4, VLSE8_V }, // 4593 |
| 25864 | { PseudoVLSE8_V_MF4_MASK, VLSE8_V }, // 4594 |
| 25865 | { PseudoVLSE8_V_MF8, VLSE8_V }, // 4595 |
| 25866 | { PseudoVLSE8_V_MF8_MASK, VLSE8_V }, // 4596 |
| 25867 | { PseudoVLSEG2E16FF_V_M1, VLSEG2E16FF_V }, // 4597 |
| 25868 | { PseudoVLSEG2E16FF_V_M1_MASK, VLSEG2E16FF_V }, // 4598 |
| 25869 | { PseudoVLSEG2E16FF_V_M2, VLSEG2E16FF_V }, // 4599 |
| 25870 | { PseudoVLSEG2E16FF_V_M2_MASK, VLSEG2E16FF_V }, // 4600 |
| 25871 | { PseudoVLSEG2E16FF_V_M4, VLSEG2E16FF_V }, // 4601 |
| 25872 | { PseudoVLSEG2E16FF_V_M4_MASK, VLSEG2E16FF_V }, // 4602 |
| 25873 | { PseudoVLSEG2E16FF_V_MF2, VLSEG2E16FF_V }, // 4603 |
| 25874 | { PseudoVLSEG2E16FF_V_MF2_MASK, VLSEG2E16FF_V }, // 4604 |
| 25875 | { PseudoVLSEG2E16FF_V_MF4, VLSEG2E16FF_V }, // 4605 |
| 25876 | { PseudoVLSEG2E16FF_V_MF4_MASK, VLSEG2E16FF_V }, // 4606 |
| 25877 | { PseudoVLSEG2E16_V_M1, VLSEG2E16_V }, // 4607 |
| 25878 | { PseudoVLSEG2E16_V_M1_MASK, VLSEG2E16_V }, // 4608 |
| 25879 | { PseudoVLSEG2E16_V_M2, VLSEG2E16_V }, // 4609 |
| 25880 | { PseudoVLSEG2E16_V_M2_MASK, VLSEG2E16_V }, // 4610 |
| 25881 | { PseudoVLSEG2E16_V_M4, VLSEG2E16_V }, // 4611 |
| 25882 | { PseudoVLSEG2E16_V_M4_MASK, VLSEG2E16_V }, // 4612 |
| 25883 | { PseudoVLSEG2E16_V_MF2, VLSEG2E16_V }, // 4613 |
| 25884 | { PseudoVLSEG2E16_V_MF2_MASK, VLSEG2E16_V }, // 4614 |
| 25885 | { PseudoVLSEG2E16_V_MF4, VLSEG2E16_V }, // 4615 |
| 25886 | { PseudoVLSEG2E16_V_MF4_MASK, VLSEG2E16_V }, // 4616 |
| 25887 | { PseudoVLSEG2E32FF_V_M1, VLSEG2E32FF_V }, // 4617 |
| 25888 | { PseudoVLSEG2E32FF_V_M1_MASK, VLSEG2E32FF_V }, // 4618 |
| 25889 | { PseudoVLSEG2E32FF_V_M2, VLSEG2E32FF_V }, // 4619 |
| 25890 | { PseudoVLSEG2E32FF_V_M2_MASK, VLSEG2E32FF_V }, // 4620 |
| 25891 | { PseudoVLSEG2E32FF_V_M4, VLSEG2E32FF_V }, // 4621 |
| 25892 | { PseudoVLSEG2E32FF_V_M4_MASK, VLSEG2E32FF_V }, // 4622 |
| 25893 | { PseudoVLSEG2E32FF_V_MF2, VLSEG2E32FF_V }, // 4623 |
| 25894 | { PseudoVLSEG2E32FF_V_MF2_MASK, VLSEG2E32FF_V }, // 4624 |
| 25895 | { PseudoVLSEG2E32_V_M1, VLSEG2E32_V }, // 4625 |
| 25896 | { PseudoVLSEG2E32_V_M1_MASK, VLSEG2E32_V }, // 4626 |
| 25897 | { PseudoVLSEG2E32_V_M2, VLSEG2E32_V }, // 4627 |
| 25898 | { PseudoVLSEG2E32_V_M2_MASK, VLSEG2E32_V }, // 4628 |
| 25899 | { PseudoVLSEG2E32_V_M4, VLSEG2E32_V }, // 4629 |
| 25900 | { PseudoVLSEG2E32_V_M4_MASK, VLSEG2E32_V }, // 4630 |
| 25901 | { PseudoVLSEG2E32_V_MF2, VLSEG2E32_V }, // 4631 |
| 25902 | { PseudoVLSEG2E32_V_MF2_MASK, VLSEG2E32_V }, // 4632 |
| 25903 | { PseudoVLSEG2E64FF_V_M1, VLSEG2E64FF_V }, // 4633 |
| 25904 | { PseudoVLSEG2E64FF_V_M1_MASK, VLSEG2E64FF_V }, // 4634 |
| 25905 | { PseudoVLSEG2E64FF_V_M2, VLSEG2E64FF_V }, // 4635 |
| 25906 | { PseudoVLSEG2E64FF_V_M2_MASK, VLSEG2E64FF_V }, // 4636 |
| 25907 | { PseudoVLSEG2E64FF_V_M4, VLSEG2E64FF_V }, // 4637 |
| 25908 | { PseudoVLSEG2E64FF_V_M4_MASK, VLSEG2E64FF_V }, // 4638 |
| 25909 | { PseudoVLSEG2E64_V_M1, VLSEG2E64_V }, // 4639 |
| 25910 | { PseudoVLSEG2E64_V_M1_MASK, VLSEG2E64_V }, // 4640 |
| 25911 | { PseudoVLSEG2E64_V_M2, VLSEG2E64_V }, // 4641 |
| 25912 | { PseudoVLSEG2E64_V_M2_MASK, VLSEG2E64_V }, // 4642 |
| 25913 | { PseudoVLSEG2E64_V_M4, VLSEG2E64_V }, // 4643 |
| 25914 | { PseudoVLSEG2E64_V_M4_MASK, VLSEG2E64_V }, // 4644 |
| 25915 | { PseudoVLSEG2E8FF_V_M1, VLSEG2E8FF_V }, // 4645 |
| 25916 | { PseudoVLSEG2E8FF_V_M1_MASK, VLSEG2E8FF_V }, // 4646 |
| 25917 | { PseudoVLSEG2E8FF_V_M2, VLSEG2E8FF_V }, // 4647 |
| 25918 | { PseudoVLSEG2E8FF_V_M2_MASK, VLSEG2E8FF_V }, // 4648 |
| 25919 | { PseudoVLSEG2E8FF_V_M4, VLSEG2E8FF_V }, // 4649 |
| 25920 | { PseudoVLSEG2E8FF_V_M4_MASK, VLSEG2E8FF_V }, // 4650 |
| 25921 | { PseudoVLSEG2E8FF_V_MF2, VLSEG2E8FF_V }, // 4651 |
| 25922 | { PseudoVLSEG2E8FF_V_MF2_MASK, VLSEG2E8FF_V }, // 4652 |
| 25923 | { PseudoVLSEG2E8FF_V_MF4, VLSEG2E8FF_V }, // 4653 |
| 25924 | { PseudoVLSEG2E8FF_V_MF4_MASK, VLSEG2E8FF_V }, // 4654 |
| 25925 | { PseudoVLSEG2E8FF_V_MF8, VLSEG2E8FF_V }, // 4655 |
| 25926 | { PseudoVLSEG2E8FF_V_MF8_MASK, VLSEG2E8FF_V }, // 4656 |
| 25927 | { PseudoVLSEG2E8_V_M1, VLSEG2E8_V }, // 4657 |
| 25928 | { PseudoVLSEG2E8_V_M1_MASK, VLSEG2E8_V }, // 4658 |
| 25929 | { PseudoVLSEG2E8_V_M2, VLSEG2E8_V }, // 4659 |
| 25930 | { PseudoVLSEG2E8_V_M2_MASK, VLSEG2E8_V }, // 4660 |
| 25931 | { PseudoVLSEG2E8_V_M4, VLSEG2E8_V }, // 4661 |
| 25932 | { PseudoVLSEG2E8_V_M4_MASK, VLSEG2E8_V }, // 4662 |
| 25933 | { PseudoVLSEG2E8_V_MF2, VLSEG2E8_V }, // 4663 |
| 25934 | { PseudoVLSEG2E8_V_MF2_MASK, VLSEG2E8_V }, // 4664 |
| 25935 | { PseudoVLSEG2E8_V_MF4, VLSEG2E8_V }, // 4665 |
| 25936 | { PseudoVLSEG2E8_V_MF4_MASK, VLSEG2E8_V }, // 4666 |
| 25937 | { PseudoVLSEG2E8_V_MF8, VLSEG2E8_V }, // 4667 |
| 25938 | { PseudoVLSEG2E8_V_MF8_MASK, VLSEG2E8_V }, // 4668 |
| 25939 | { PseudoVLSEG3E16FF_V_M1, VLSEG3E16FF_V }, // 4669 |
| 25940 | { PseudoVLSEG3E16FF_V_M1_MASK, VLSEG3E16FF_V }, // 4670 |
| 25941 | { PseudoVLSEG3E16FF_V_M2, VLSEG3E16FF_V }, // 4671 |
| 25942 | { PseudoVLSEG3E16FF_V_M2_MASK, VLSEG3E16FF_V }, // 4672 |
| 25943 | { PseudoVLSEG3E16FF_V_MF2, VLSEG3E16FF_V }, // 4673 |
| 25944 | { PseudoVLSEG3E16FF_V_MF2_MASK, VLSEG3E16FF_V }, // 4674 |
| 25945 | { PseudoVLSEG3E16FF_V_MF4, VLSEG3E16FF_V }, // 4675 |
| 25946 | { PseudoVLSEG3E16FF_V_MF4_MASK, VLSEG3E16FF_V }, // 4676 |
| 25947 | { PseudoVLSEG3E16_V_M1, VLSEG3E16_V }, // 4677 |
| 25948 | { PseudoVLSEG3E16_V_M1_MASK, VLSEG3E16_V }, // 4678 |
| 25949 | { PseudoVLSEG3E16_V_M2, VLSEG3E16_V }, // 4679 |
| 25950 | { PseudoVLSEG3E16_V_M2_MASK, VLSEG3E16_V }, // 4680 |
| 25951 | { PseudoVLSEG3E16_V_MF2, VLSEG3E16_V }, // 4681 |
| 25952 | { PseudoVLSEG3E16_V_MF2_MASK, VLSEG3E16_V }, // 4682 |
| 25953 | { PseudoVLSEG3E16_V_MF4, VLSEG3E16_V }, // 4683 |
| 25954 | { PseudoVLSEG3E16_V_MF4_MASK, VLSEG3E16_V }, // 4684 |
| 25955 | { PseudoVLSEG3E32FF_V_M1, VLSEG3E32FF_V }, // 4685 |
| 25956 | { PseudoVLSEG3E32FF_V_M1_MASK, VLSEG3E32FF_V }, // 4686 |
| 25957 | { PseudoVLSEG3E32FF_V_M2, VLSEG3E32FF_V }, // 4687 |
| 25958 | { PseudoVLSEG3E32FF_V_M2_MASK, VLSEG3E32FF_V }, // 4688 |
| 25959 | { PseudoVLSEG3E32FF_V_MF2, VLSEG3E32FF_V }, // 4689 |
| 25960 | { PseudoVLSEG3E32FF_V_MF2_MASK, VLSEG3E32FF_V }, // 4690 |
| 25961 | { PseudoVLSEG3E32_V_M1, VLSEG3E32_V }, // 4691 |
| 25962 | { PseudoVLSEG3E32_V_M1_MASK, VLSEG3E32_V }, // 4692 |
| 25963 | { PseudoVLSEG3E32_V_M2, VLSEG3E32_V }, // 4693 |
| 25964 | { PseudoVLSEG3E32_V_M2_MASK, VLSEG3E32_V }, // 4694 |
| 25965 | { PseudoVLSEG3E32_V_MF2, VLSEG3E32_V }, // 4695 |
| 25966 | { PseudoVLSEG3E32_V_MF2_MASK, VLSEG3E32_V }, // 4696 |
| 25967 | { PseudoVLSEG3E64FF_V_M1, VLSEG3E64FF_V }, // 4697 |
| 25968 | { PseudoVLSEG3E64FF_V_M1_MASK, VLSEG3E64FF_V }, // 4698 |
| 25969 | { PseudoVLSEG3E64FF_V_M2, VLSEG3E64FF_V }, // 4699 |
| 25970 | { PseudoVLSEG3E64FF_V_M2_MASK, VLSEG3E64FF_V }, // 4700 |
| 25971 | { PseudoVLSEG3E64_V_M1, VLSEG3E64_V }, // 4701 |
| 25972 | { PseudoVLSEG3E64_V_M1_MASK, VLSEG3E64_V }, // 4702 |
| 25973 | { PseudoVLSEG3E64_V_M2, VLSEG3E64_V }, // 4703 |
| 25974 | { PseudoVLSEG3E64_V_M2_MASK, VLSEG3E64_V }, // 4704 |
| 25975 | { PseudoVLSEG3E8FF_V_M1, VLSEG3E8FF_V }, // 4705 |
| 25976 | { PseudoVLSEG3E8FF_V_M1_MASK, VLSEG3E8FF_V }, // 4706 |
| 25977 | { PseudoVLSEG3E8FF_V_M2, VLSEG3E8FF_V }, // 4707 |
| 25978 | { PseudoVLSEG3E8FF_V_M2_MASK, VLSEG3E8FF_V }, // 4708 |
| 25979 | { PseudoVLSEG3E8FF_V_MF2, VLSEG3E8FF_V }, // 4709 |
| 25980 | { PseudoVLSEG3E8FF_V_MF2_MASK, VLSEG3E8FF_V }, // 4710 |
| 25981 | { PseudoVLSEG3E8FF_V_MF4, VLSEG3E8FF_V }, // 4711 |
| 25982 | { PseudoVLSEG3E8FF_V_MF4_MASK, VLSEG3E8FF_V }, // 4712 |
| 25983 | { PseudoVLSEG3E8FF_V_MF8, VLSEG3E8FF_V }, // 4713 |
| 25984 | { PseudoVLSEG3E8FF_V_MF8_MASK, VLSEG3E8FF_V }, // 4714 |
| 25985 | { PseudoVLSEG3E8_V_M1, VLSEG3E8_V }, // 4715 |
| 25986 | { PseudoVLSEG3E8_V_M1_MASK, VLSEG3E8_V }, // 4716 |
| 25987 | { PseudoVLSEG3E8_V_M2, VLSEG3E8_V }, // 4717 |
| 25988 | { PseudoVLSEG3E8_V_M2_MASK, VLSEG3E8_V }, // 4718 |
| 25989 | { PseudoVLSEG3E8_V_MF2, VLSEG3E8_V }, // 4719 |
| 25990 | { PseudoVLSEG3E8_V_MF2_MASK, VLSEG3E8_V }, // 4720 |
| 25991 | { PseudoVLSEG3E8_V_MF4, VLSEG3E8_V }, // 4721 |
| 25992 | { PseudoVLSEG3E8_V_MF4_MASK, VLSEG3E8_V }, // 4722 |
| 25993 | { PseudoVLSEG3E8_V_MF8, VLSEG3E8_V }, // 4723 |
| 25994 | { PseudoVLSEG3E8_V_MF8_MASK, VLSEG3E8_V }, // 4724 |
| 25995 | { PseudoVLSEG4E16FF_V_M1, VLSEG4E16FF_V }, // 4725 |
| 25996 | { PseudoVLSEG4E16FF_V_M1_MASK, VLSEG4E16FF_V }, // 4726 |
| 25997 | { PseudoVLSEG4E16FF_V_M2, VLSEG4E16FF_V }, // 4727 |
| 25998 | { PseudoVLSEG4E16FF_V_M2_MASK, VLSEG4E16FF_V }, // 4728 |
| 25999 | { PseudoVLSEG4E16FF_V_MF2, VLSEG4E16FF_V }, // 4729 |
| 26000 | { PseudoVLSEG4E16FF_V_MF2_MASK, VLSEG4E16FF_V }, // 4730 |
| 26001 | { PseudoVLSEG4E16FF_V_MF4, VLSEG4E16FF_V }, // 4731 |
| 26002 | { PseudoVLSEG4E16FF_V_MF4_MASK, VLSEG4E16FF_V }, // 4732 |
| 26003 | { PseudoVLSEG4E16_V_M1, VLSEG4E16_V }, // 4733 |
| 26004 | { PseudoVLSEG4E16_V_M1_MASK, VLSEG4E16_V }, // 4734 |
| 26005 | { PseudoVLSEG4E16_V_M2, VLSEG4E16_V }, // 4735 |
| 26006 | { PseudoVLSEG4E16_V_M2_MASK, VLSEG4E16_V }, // 4736 |
| 26007 | { PseudoVLSEG4E16_V_MF2, VLSEG4E16_V }, // 4737 |
| 26008 | { PseudoVLSEG4E16_V_MF2_MASK, VLSEG4E16_V }, // 4738 |
| 26009 | { PseudoVLSEG4E16_V_MF4, VLSEG4E16_V }, // 4739 |
| 26010 | { PseudoVLSEG4E16_V_MF4_MASK, VLSEG4E16_V }, // 4740 |
| 26011 | { PseudoVLSEG4E32FF_V_M1, VLSEG4E32FF_V }, // 4741 |
| 26012 | { PseudoVLSEG4E32FF_V_M1_MASK, VLSEG4E32FF_V }, // 4742 |
| 26013 | { PseudoVLSEG4E32FF_V_M2, VLSEG4E32FF_V }, // 4743 |
| 26014 | { PseudoVLSEG4E32FF_V_M2_MASK, VLSEG4E32FF_V }, // 4744 |
| 26015 | { PseudoVLSEG4E32FF_V_MF2, VLSEG4E32FF_V }, // 4745 |
| 26016 | { PseudoVLSEG4E32FF_V_MF2_MASK, VLSEG4E32FF_V }, // 4746 |
| 26017 | { PseudoVLSEG4E32_V_M1, VLSEG4E32_V }, // 4747 |
| 26018 | { PseudoVLSEG4E32_V_M1_MASK, VLSEG4E32_V }, // 4748 |
| 26019 | { PseudoVLSEG4E32_V_M2, VLSEG4E32_V }, // 4749 |
| 26020 | { PseudoVLSEG4E32_V_M2_MASK, VLSEG4E32_V }, // 4750 |
| 26021 | { PseudoVLSEG4E32_V_MF2, VLSEG4E32_V }, // 4751 |
| 26022 | { PseudoVLSEG4E32_V_MF2_MASK, VLSEG4E32_V }, // 4752 |
| 26023 | { PseudoVLSEG4E64FF_V_M1, VLSEG4E64FF_V }, // 4753 |
| 26024 | { PseudoVLSEG4E64FF_V_M1_MASK, VLSEG4E64FF_V }, // 4754 |
| 26025 | { PseudoVLSEG4E64FF_V_M2, VLSEG4E64FF_V }, // 4755 |
| 26026 | { PseudoVLSEG4E64FF_V_M2_MASK, VLSEG4E64FF_V }, // 4756 |
| 26027 | { PseudoVLSEG4E64_V_M1, VLSEG4E64_V }, // 4757 |
| 26028 | { PseudoVLSEG4E64_V_M1_MASK, VLSEG4E64_V }, // 4758 |
| 26029 | { PseudoVLSEG4E64_V_M2, VLSEG4E64_V }, // 4759 |
| 26030 | { PseudoVLSEG4E64_V_M2_MASK, VLSEG4E64_V }, // 4760 |
| 26031 | { PseudoVLSEG4E8FF_V_M1, VLSEG4E8FF_V }, // 4761 |
| 26032 | { PseudoVLSEG4E8FF_V_M1_MASK, VLSEG4E8FF_V }, // 4762 |
| 26033 | { PseudoVLSEG4E8FF_V_M2, VLSEG4E8FF_V }, // 4763 |
| 26034 | { PseudoVLSEG4E8FF_V_M2_MASK, VLSEG4E8FF_V }, // 4764 |
| 26035 | { PseudoVLSEG4E8FF_V_MF2, VLSEG4E8FF_V }, // 4765 |
| 26036 | { PseudoVLSEG4E8FF_V_MF2_MASK, VLSEG4E8FF_V }, // 4766 |
| 26037 | { PseudoVLSEG4E8FF_V_MF4, VLSEG4E8FF_V }, // 4767 |
| 26038 | { PseudoVLSEG4E8FF_V_MF4_MASK, VLSEG4E8FF_V }, // 4768 |
| 26039 | { PseudoVLSEG4E8FF_V_MF8, VLSEG4E8FF_V }, // 4769 |
| 26040 | { PseudoVLSEG4E8FF_V_MF8_MASK, VLSEG4E8FF_V }, // 4770 |
| 26041 | { PseudoVLSEG4E8_V_M1, VLSEG4E8_V }, // 4771 |
| 26042 | { PseudoVLSEG4E8_V_M1_MASK, VLSEG4E8_V }, // 4772 |
| 26043 | { PseudoVLSEG4E8_V_M2, VLSEG4E8_V }, // 4773 |
| 26044 | { PseudoVLSEG4E8_V_M2_MASK, VLSEG4E8_V }, // 4774 |
| 26045 | { PseudoVLSEG4E8_V_MF2, VLSEG4E8_V }, // 4775 |
| 26046 | { PseudoVLSEG4E8_V_MF2_MASK, VLSEG4E8_V }, // 4776 |
| 26047 | { PseudoVLSEG4E8_V_MF4, VLSEG4E8_V }, // 4777 |
| 26048 | { PseudoVLSEG4E8_V_MF4_MASK, VLSEG4E8_V }, // 4778 |
| 26049 | { PseudoVLSEG4E8_V_MF8, VLSEG4E8_V }, // 4779 |
| 26050 | { PseudoVLSEG4E8_V_MF8_MASK, VLSEG4E8_V }, // 4780 |
| 26051 | { PseudoVLSEG5E16FF_V_M1, VLSEG5E16FF_V }, // 4781 |
| 26052 | { PseudoVLSEG5E16FF_V_M1_MASK, VLSEG5E16FF_V }, // 4782 |
| 26053 | { PseudoVLSEG5E16FF_V_MF2, VLSEG5E16FF_V }, // 4783 |
| 26054 | { PseudoVLSEG5E16FF_V_MF2_MASK, VLSEG5E16FF_V }, // 4784 |
| 26055 | { PseudoVLSEG5E16FF_V_MF4, VLSEG5E16FF_V }, // 4785 |
| 26056 | { PseudoVLSEG5E16FF_V_MF4_MASK, VLSEG5E16FF_V }, // 4786 |
| 26057 | { PseudoVLSEG5E16_V_M1, VLSEG5E16_V }, // 4787 |
| 26058 | { PseudoVLSEG5E16_V_M1_MASK, VLSEG5E16_V }, // 4788 |
| 26059 | { PseudoVLSEG5E16_V_MF2, VLSEG5E16_V }, // 4789 |
| 26060 | { PseudoVLSEG5E16_V_MF2_MASK, VLSEG5E16_V }, // 4790 |
| 26061 | { PseudoVLSEG5E16_V_MF4, VLSEG5E16_V }, // 4791 |
| 26062 | { PseudoVLSEG5E16_V_MF4_MASK, VLSEG5E16_V }, // 4792 |
| 26063 | { PseudoVLSEG5E32FF_V_M1, VLSEG5E32FF_V }, // 4793 |
| 26064 | { PseudoVLSEG5E32FF_V_M1_MASK, VLSEG5E32FF_V }, // 4794 |
| 26065 | { PseudoVLSEG5E32FF_V_MF2, VLSEG5E32FF_V }, // 4795 |
| 26066 | { PseudoVLSEG5E32FF_V_MF2_MASK, VLSEG5E32FF_V }, // 4796 |
| 26067 | { PseudoVLSEG5E32_V_M1, VLSEG5E32_V }, // 4797 |
| 26068 | { PseudoVLSEG5E32_V_M1_MASK, VLSEG5E32_V }, // 4798 |
| 26069 | { PseudoVLSEG5E32_V_MF2, VLSEG5E32_V }, // 4799 |
| 26070 | { PseudoVLSEG5E32_V_MF2_MASK, VLSEG5E32_V }, // 4800 |
| 26071 | { PseudoVLSEG5E64FF_V_M1, VLSEG5E64FF_V }, // 4801 |
| 26072 | { PseudoVLSEG5E64FF_V_M1_MASK, VLSEG5E64FF_V }, // 4802 |
| 26073 | { PseudoVLSEG5E64_V_M1, VLSEG5E64_V }, // 4803 |
| 26074 | { PseudoVLSEG5E64_V_M1_MASK, VLSEG5E64_V }, // 4804 |
| 26075 | { PseudoVLSEG5E8FF_V_M1, VLSEG5E8FF_V }, // 4805 |
| 26076 | { PseudoVLSEG5E8FF_V_M1_MASK, VLSEG5E8FF_V }, // 4806 |
| 26077 | { PseudoVLSEG5E8FF_V_MF2, VLSEG5E8FF_V }, // 4807 |
| 26078 | { PseudoVLSEG5E8FF_V_MF2_MASK, VLSEG5E8FF_V }, // 4808 |
| 26079 | { PseudoVLSEG5E8FF_V_MF4, VLSEG5E8FF_V }, // 4809 |
| 26080 | { PseudoVLSEG5E8FF_V_MF4_MASK, VLSEG5E8FF_V }, // 4810 |
| 26081 | { PseudoVLSEG5E8FF_V_MF8, VLSEG5E8FF_V }, // 4811 |
| 26082 | { PseudoVLSEG5E8FF_V_MF8_MASK, VLSEG5E8FF_V }, // 4812 |
| 26083 | { PseudoVLSEG5E8_V_M1, VLSEG5E8_V }, // 4813 |
| 26084 | { PseudoVLSEG5E8_V_M1_MASK, VLSEG5E8_V }, // 4814 |
| 26085 | { PseudoVLSEG5E8_V_MF2, VLSEG5E8_V }, // 4815 |
| 26086 | { PseudoVLSEG5E8_V_MF2_MASK, VLSEG5E8_V }, // 4816 |
| 26087 | { PseudoVLSEG5E8_V_MF4, VLSEG5E8_V }, // 4817 |
| 26088 | { PseudoVLSEG5E8_V_MF4_MASK, VLSEG5E8_V }, // 4818 |
| 26089 | { PseudoVLSEG5E8_V_MF8, VLSEG5E8_V }, // 4819 |
| 26090 | { PseudoVLSEG5E8_V_MF8_MASK, VLSEG5E8_V }, // 4820 |
| 26091 | { PseudoVLSEG6E16FF_V_M1, VLSEG6E16FF_V }, // 4821 |
| 26092 | { PseudoVLSEG6E16FF_V_M1_MASK, VLSEG6E16FF_V }, // 4822 |
| 26093 | { PseudoVLSEG6E16FF_V_MF2, VLSEG6E16FF_V }, // 4823 |
| 26094 | { PseudoVLSEG6E16FF_V_MF2_MASK, VLSEG6E16FF_V }, // 4824 |
| 26095 | { PseudoVLSEG6E16FF_V_MF4, VLSEG6E16FF_V }, // 4825 |
| 26096 | { PseudoVLSEG6E16FF_V_MF4_MASK, VLSEG6E16FF_V }, // 4826 |
| 26097 | { PseudoVLSEG6E16_V_M1, VLSEG6E16_V }, // 4827 |
| 26098 | { PseudoVLSEG6E16_V_M1_MASK, VLSEG6E16_V }, // 4828 |
| 26099 | { PseudoVLSEG6E16_V_MF2, VLSEG6E16_V }, // 4829 |
| 26100 | { PseudoVLSEG6E16_V_MF2_MASK, VLSEG6E16_V }, // 4830 |
| 26101 | { PseudoVLSEG6E16_V_MF4, VLSEG6E16_V }, // 4831 |
| 26102 | { PseudoVLSEG6E16_V_MF4_MASK, VLSEG6E16_V }, // 4832 |
| 26103 | { PseudoVLSEG6E32FF_V_M1, VLSEG6E32FF_V }, // 4833 |
| 26104 | { PseudoVLSEG6E32FF_V_M1_MASK, VLSEG6E32FF_V }, // 4834 |
| 26105 | { PseudoVLSEG6E32FF_V_MF2, VLSEG6E32FF_V }, // 4835 |
| 26106 | { PseudoVLSEG6E32FF_V_MF2_MASK, VLSEG6E32FF_V }, // 4836 |
| 26107 | { PseudoVLSEG6E32_V_M1, VLSEG6E32_V }, // 4837 |
| 26108 | { PseudoVLSEG6E32_V_M1_MASK, VLSEG6E32_V }, // 4838 |
| 26109 | { PseudoVLSEG6E32_V_MF2, VLSEG6E32_V }, // 4839 |
| 26110 | { PseudoVLSEG6E32_V_MF2_MASK, VLSEG6E32_V }, // 4840 |
| 26111 | { PseudoVLSEG6E64FF_V_M1, VLSEG6E64FF_V }, // 4841 |
| 26112 | { PseudoVLSEG6E64FF_V_M1_MASK, VLSEG6E64FF_V }, // 4842 |
| 26113 | { PseudoVLSEG6E64_V_M1, VLSEG6E64_V }, // 4843 |
| 26114 | { PseudoVLSEG6E64_V_M1_MASK, VLSEG6E64_V }, // 4844 |
| 26115 | { PseudoVLSEG6E8FF_V_M1, VLSEG6E8FF_V }, // 4845 |
| 26116 | { PseudoVLSEG6E8FF_V_M1_MASK, VLSEG6E8FF_V }, // 4846 |
| 26117 | { PseudoVLSEG6E8FF_V_MF2, VLSEG6E8FF_V }, // 4847 |
| 26118 | { PseudoVLSEG6E8FF_V_MF2_MASK, VLSEG6E8FF_V }, // 4848 |
| 26119 | { PseudoVLSEG6E8FF_V_MF4, VLSEG6E8FF_V }, // 4849 |
| 26120 | { PseudoVLSEG6E8FF_V_MF4_MASK, VLSEG6E8FF_V }, // 4850 |
| 26121 | { PseudoVLSEG6E8FF_V_MF8, VLSEG6E8FF_V }, // 4851 |
| 26122 | { PseudoVLSEG6E8FF_V_MF8_MASK, VLSEG6E8FF_V }, // 4852 |
| 26123 | { PseudoVLSEG6E8_V_M1, VLSEG6E8_V }, // 4853 |
| 26124 | { PseudoVLSEG6E8_V_M1_MASK, VLSEG6E8_V }, // 4854 |
| 26125 | { PseudoVLSEG6E8_V_MF2, VLSEG6E8_V }, // 4855 |
| 26126 | { PseudoVLSEG6E8_V_MF2_MASK, VLSEG6E8_V }, // 4856 |
| 26127 | { PseudoVLSEG6E8_V_MF4, VLSEG6E8_V }, // 4857 |
| 26128 | { PseudoVLSEG6E8_V_MF4_MASK, VLSEG6E8_V }, // 4858 |
| 26129 | { PseudoVLSEG6E8_V_MF8, VLSEG6E8_V }, // 4859 |
| 26130 | { PseudoVLSEG6E8_V_MF8_MASK, VLSEG6E8_V }, // 4860 |
| 26131 | { PseudoVLSEG7E16FF_V_M1, VLSEG7E16FF_V }, // 4861 |
| 26132 | { PseudoVLSEG7E16FF_V_M1_MASK, VLSEG7E16FF_V }, // 4862 |
| 26133 | { PseudoVLSEG7E16FF_V_MF2, VLSEG7E16FF_V }, // 4863 |
| 26134 | { PseudoVLSEG7E16FF_V_MF2_MASK, VLSEG7E16FF_V }, // 4864 |
| 26135 | { PseudoVLSEG7E16FF_V_MF4, VLSEG7E16FF_V }, // 4865 |
| 26136 | { PseudoVLSEG7E16FF_V_MF4_MASK, VLSEG7E16FF_V }, // 4866 |
| 26137 | { PseudoVLSEG7E16_V_M1, VLSEG7E16_V }, // 4867 |
| 26138 | { PseudoVLSEG7E16_V_M1_MASK, VLSEG7E16_V }, // 4868 |
| 26139 | { PseudoVLSEG7E16_V_MF2, VLSEG7E16_V }, // 4869 |
| 26140 | { PseudoVLSEG7E16_V_MF2_MASK, VLSEG7E16_V }, // 4870 |
| 26141 | { PseudoVLSEG7E16_V_MF4, VLSEG7E16_V }, // 4871 |
| 26142 | { PseudoVLSEG7E16_V_MF4_MASK, VLSEG7E16_V }, // 4872 |
| 26143 | { PseudoVLSEG7E32FF_V_M1, VLSEG7E32FF_V }, // 4873 |
| 26144 | { PseudoVLSEG7E32FF_V_M1_MASK, VLSEG7E32FF_V }, // 4874 |
| 26145 | { PseudoVLSEG7E32FF_V_MF2, VLSEG7E32FF_V }, // 4875 |
| 26146 | { PseudoVLSEG7E32FF_V_MF2_MASK, VLSEG7E32FF_V }, // 4876 |
| 26147 | { PseudoVLSEG7E32_V_M1, VLSEG7E32_V }, // 4877 |
| 26148 | { PseudoVLSEG7E32_V_M1_MASK, VLSEG7E32_V }, // 4878 |
| 26149 | { PseudoVLSEG7E32_V_MF2, VLSEG7E32_V }, // 4879 |
| 26150 | { PseudoVLSEG7E32_V_MF2_MASK, VLSEG7E32_V }, // 4880 |
| 26151 | { PseudoVLSEG7E64FF_V_M1, VLSEG7E64FF_V }, // 4881 |
| 26152 | { PseudoVLSEG7E64FF_V_M1_MASK, VLSEG7E64FF_V }, // 4882 |
| 26153 | { PseudoVLSEG7E64_V_M1, VLSEG7E64_V }, // 4883 |
| 26154 | { PseudoVLSEG7E64_V_M1_MASK, VLSEG7E64_V }, // 4884 |
| 26155 | { PseudoVLSEG7E8FF_V_M1, VLSEG7E8FF_V }, // 4885 |
| 26156 | { PseudoVLSEG7E8FF_V_M1_MASK, VLSEG7E8FF_V }, // 4886 |
| 26157 | { PseudoVLSEG7E8FF_V_MF2, VLSEG7E8FF_V }, // 4887 |
| 26158 | { PseudoVLSEG7E8FF_V_MF2_MASK, VLSEG7E8FF_V }, // 4888 |
| 26159 | { PseudoVLSEG7E8FF_V_MF4, VLSEG7E8FF_V }, // 4889 |
| 26160 | { PseudoVLSEG7E8FF_V_MF4_MASK, VLSEG7E8FF_V }, // 4890 |
| 26161 | { PseudoVLSEG7E8FF_V_MF8, VLSEG7E8FF_V }, // 4891 |
| 26162 | { PseudoVLSEG7E8FF_V_MF8_MASK, VLSEG7E8FF_V }, // 4892 |
| 26163 | { PseudoVLSEG7E8_V_M1, VLSEG7E8_V }, // 4893 |
| 26164 | { PseudoVLSEG7E8_V_M1_MASK, VLSEG7E8_V }, // 4894 |
| 26165 | { PseudoVLSEG7E8_V_MF2, VLSEG7E8_V }, // 4895 |
| 26166 | { PseudoVLSEG7E8_V_MF2_MASK, VLSEG7E8_V }, // 4896 |
| 26167 | { PseudoVLSEG7E8_V_MF4, VLSEG7E8_V }, // 4897 |
| 26168 | { PseudoVLSEG7E8_V_MF4_MASK, VLSEG7E8_V }, // 4898 |
| 26169 | { PseudoVLSEG7E8_V_MF8, VLSEG7E8_V }, // 4899 |
| 26170 | { PseudoVLSEG7E8_V_MF8_MASK, VLSEG7E8_V }, // 4900 |
| 26171 | { PseudoVLSEG8E16FF_V_M1, VLSEG8E16FF_V }, // 4901 |
| 26172 | { PseudoVLSEG8E16FF_V_M1_MASK, VLSEG8E16FF_V }, // 4902 |
| 26173 | { PseudoVLSEG8E16FF_V_MF2, VLSEG8E16FF_V }, // 4903 |
| 26174 | { PseudoVLSEG8E16FF_V_MF2_MASK, VLSEG8E16FF_V }, // 4904 |
| 26175 | { PseudoVLSEG8E16FF_V_MF4, VLSEG8E16FF_V }, // 4905 |
| 26176 | { PseudoVLSEG8E16FF_V_MF4_MASK, VLSEG8E16FF_V }, // 4906 |
| 26177 | { PseudoVLSEG8E16_V_M1, VLSEG8E16_V }, // 4907 |
| 26178 | { PseudoVLSEG8E16_V_M1_MASK, VLSEG8E16_V }, // 4908 |
| 26179 | { PseudoVLSEG8E16_V_MF2, VLSEG8E16_V }, // 4909 |
| 26180 | { PseudoVLSEG8E16_V_MF2_MASK, VLSEG8E16_V }, // 4910 |
| 26181 | { PseudoVLSEG8E16_V_MF4, VLSEG8E16_V }, // 4911 |
| 26182 | { PseudoVLSEG8E16_V_MF4_MASK, VLSEG8E16_V }, // 4912 |
| 26183 | { PseudoVLSEG8E32FF_V_M1, VLSEG8E32FF_V }, // 4913 |
| 26184 | { PseudoVLSEG8E32FF_V_M1_MASK, VLSEG8E32FF_V }, // 4914 |
| 26185 | { PseudoVLSEG8E32FF_V_MF2, VLSEG8E32FF_V }, // 4915 |
| 26186 | { PseudoVLSEG8E32FF_V_MF2_MASK, VLSEG8E32FF_V }, // 4916 |
| 26187 | { PseudoVLSEG8E32_V_M1, VLSEG8E32_V }, // 4917 |
| 26188 | { PseudoVLSEG8E32_V_M1_MASK, VLSEG8E32_V }, // 4918 |
| 26189 | { PseudoVLSEG8E32_V_MF2, VLSEG8E32_V }, // 4919 |
| 26190 | { PseudoVLSEG8E32_V_MF2_MASK, VLSEG8E32_V }, // 4920 |
| 26191 | { PseudoVLSEG8E64FF_V_M1, VLSEG8E64FF_V }, // 4921 |
| 26192 | { PseudoVLSEG8E64FF_V_M1_MASK, VLSEG8E64FF_V }, // 4922 |
| 26193 | { PseudoVLSEG8E64_V_M1, VLSEG8E64_V }, // 4923 |
| 26194 | { PseudoVLSEG8E64_V_M1_MASK, VLSEG8E64_V }, // 4924 |
| 26195 | { PseudoVLSEG8E8FF_V_M1, VLSEG8E8FF_V }, // 4925 |
| 26196 | { PseudoVLSEG8E8FF_V_M1_MASK, VLSEG8E8FF_V }, // 4926 |
| 26197 | { PseudoVLSEG8E8FF_V_MF2, VLSEG8E8FF_V }, // 4927 |
| 26198 | { PseudoVLSEG8E8FF_V_MF2_MASK, VLSEG8E8FF_V }, // 4928 |
| 26199 | { PseudoVLSEG8E8FF_V_MF4, VLSEG8E8FF_V }, // 4929 |
| 26200 | { PseudoVLSEG8E8FF_V_MF4_MASK, VLSEG8E8FF_V }, // 4930 |
| 26201 | { PseudoVLSEG8E8FF_V_MF8, VLSEG8E8FF_V }, // 4931 |
| 26202 | { PseudoVLSEG8E8FF_V_MF8_MASK, VLSEG8E8FF_V }, // 4932 |
| 26203 | { PseudoVLSEG8E8_V_M1, VLSEG8E8_V }, // 4933 |
| 26204 | { PseudoVLSEG8E8_V_M1_MASK, VLSEG8E8_V }, // 4934 |
| 26205 | { PseudoVLSEG8E8_V_MF2, VLSEG8E8_V }, // 4935 |
| 26206 | { PseudoVLSEG8E8_V_MF2_MASK, VLSEG8E8_V }, // 4936 |
| 26207 | { PseudoVLSEG8E8_V_MF4, VLSEG8E8_V }, // 4937 |
| 26208 | { PseudoVLSEG8E8_V_MF4_MASK, VLSEG8E8_V }, // 4938 |
| 26209 | { PseudoVLSEG8E8_V_MF8, VLSEG8E8_V }, // 4939 |
| 26210 | { PseudoVLSEG8E8_V_MF8_MASK, VLSEG8E8_V }, // 4940 |
| 26211 | { PseudoVLSSEG2E16_V_M1, VLSSEG2E16_V }, // 4941 |
| 26212 | { PseudoVLSSEG2E16_V_M1_MASK, VLSSEG2E16_V }, // 4942 |
| 26213 | { PseudoVLSSEG2E16_V_M2, VLSSEG2E16_V }, // 4943 |
| 26214 | { PseudoVLSSEG2E16_V_M2_MASK, VLSSEG2E16_V }, // 4944 |
| 26215 | { PseudoVLSSEG2E16_V_M4, VLSSEG2E16_V }, // 4945 |
| 26216 | { PseudoVLSSEG2E16_V_M4_MASK, VLSSEG2E16_V }, // 4946 |
| 26217 | { PseudoVLSSEG2E16_V_MF2, VLSSEG2E16_V }, // 4947 |
| 26218 | { PseudoVLSSEG2E16_V_MF2_MASK, VLSSEG2E16_V }, // 4948 |
| 26219 | { PseudoVLSSEG2E16_V_MF4, VLSSEG2E16_V }, // 4949 |
| 26220 | { PseudoVLSSEG2E16_V_MF4_MASK, VLSSEG2E16_V }, // 4950 |
| 26221 | { PseudoVLSSEG2E32_V_M1, VLSSEG2E32_V }, // 4951 |
| 26222 | { PseudoVLSSEG2E32_V_M1_MASK, VLSSEG2E32_V }, // 4952 |
| 26223 | { PseudoVLSSEG2E32_V_M2, VLSSEG2E32_V }, // 4953 |
| 26224 | { PseudoVLSSEG2E32_V_M2_MASK, VLSSEG2E32_V }, // 4954 |
| 26225 | { PseudoVLSSEG2E32_V_M4, VLSSEG2E32_V }, // 4955 |
| 26226 | { PseudoVLSSEG2E32_V_M4_MASK, VLSSEG2E32_V }, // 4956 |
| 26227 | { PseudoVLSSEG2E32_V_MF2, VLSSEG2E32_V }, // 4957 |
| 26228 | { PseudoVLSSEG2E32_V_MF2_MASK, VLSSEG2E32_V }, // 4958 |
| 26229 | { PseudoVLSSEG2E64_V_M1, VLSSEG2E64_V }, // 4959 |
| 26230 | { PseudoVLSSEG2E64_V_M1_MASK, VLSSEG2E64_V }, // 4960 |
| 26231 | { PseudoVLSSEG2E64_V_M2, VLSSEG2E64_V }, // 4961 |
| 26232 | { PseudoVLSSEG2E64_V_M2_MASK, VLSSEG2E64_V }, // 4962 |
| 26233 | { PseudoVLSSEG2E64_V_M4, VLSSEG2E64_V }, // 4963 |
| 26234 | { PseudoVLSSEG2E64_V_M4_MASK, VLSSEG2E64_V }, // 4964 |
| 26235 | { PseudoVLSSEG2E8_V_M1, VLSSEG2E8_V }, // 4965 |
| 26236 | { PseudoVLSSEG2E8_V_M1_MASK, VLSSEG2E8_V }, // 4966 |
| 26237 | { PseudoVLSSEG2E8_V_M2, VLSSEG2E8_V }, // 4967 |
| 26238 | { PseudoVLSSEG2E8_V_M2_MASK, VLSSEG2E8_V }, // 4968 |
| 26239 | { PseudoVLSSEG2E8_V_M4, VLSSEG2E8_V }, // 4969 |
| 26240 | { PseudoVLSSEG2E8_V_M4_MASK, VLSSEG2E8_V }, // 4970 |
| 26241 | { PseudoVLSSEG2E8_V_MF2, VLSSEG2E8_V }, // 4971 |
| 26242 | { PseudoVLSSEG2E8_V_MF2_MASK, VLSSEG2E8_V }, // 4972 |
| 26243 | { PseudoVLSSEG2E8_V_MF4, VLSSEG2E8_V }, // 4973 |
| 26244 | { PseudoVLSSEG2E8_V_MF4_MASK, VLSSEG2E8_V }, // 4974 |
| 26245 | { PseudoVLSSEG2E8_V_MF8, VLSSEG2E8_V }, // 4975 |
| 26246 | { PseudoVLSSEG2E8_V_MF8_MASK, VLSSEG2E8_V }, // 4976 |
| 26247 | { PseudoVLSSEG3E16_V_M1, VLSSEG3E16_V }, // 4977 |
| 26248 | { PseudoVLSSEG3E16_V_M1_MASK, VLSSEG3E16_V }, // 4978 |
| 26249 | { PseudoVLSSEG3E16_V_M2, VLSSEG3E16_V }, // 4979 |
| 26250 | { PseudoVLSSEG3E16_V_M2_MASK, VLSSEG3E16_V }, // 4980 |
| 26251 | { PseudoVLSSEG3E16_V_MF2, VLSSEG3E16_V }, // 4981 |
| 26252 | { PseudoVLSSEG3E16_V_MF2_MASK, VLSSEG3E16_V }, // 4982 |
| 26253 | { PseudoVLSSEG3E16_V_MF4, VLSSEG3E16_V }, // 4983 |
| 26254 | { PseudoVLSSEG3E16_V_MF4_MASK, VLSSEG3E16_V }, // 4984 |
| 26255 | { PseudoVLSSEG3E32_V_M1, VLSSEG3E32_V }, // 4985 |
| 26256 | { PseudoVLSSEG3E32_V_M1_MASK, VLSSEG3E32_V }, // 4986 |
| 26257 | { PseudoVLSSEG3E32_V_M2, VLSSEG3E32_V }, // 4987 |
| 26258 | { PseudoVLSSEG3E32_V_M2_MASK, VLSSEG3E32_V }, // 4988 |
| 26259 | { PseudoVLSSEG3E32_V_MF2, VLSSEG3E32_V }, // 4989 |
| 26260 | { PseudoVLSSEG3E32_V_MF2_MASK, VLSSEG3E32_V }, // 4990 |
| 26261 | { PseudoVLSSEG3E64_V_M1, VLSSEG3E64_V }, // 4991 |
| 26262 | { PseudoVLSSEG3E64_V_M1_MASK, VLSSEG3E64_V }, // 4992 |
| 26263 | { PseudoVLSSEG3E64_V_M2, VLSSEG3E64_V }, // 4993 |
| 26264 | { PseudoVLSSEG3E64_V_M2_MASK, VLSSEG3E64_V }, // 4994 |
| 26265 | { PseudoVLSSEG3E8_V_M1, VLSSEG3E8_V }, // 4995 |
| 26266 | { PseudoVLSSEG3E8_V_M1_MASK, VLSSEG3E8_V }, // 4996 |
| 26267 | { PseudoVLSSEG3E8_V_M2, VLSSEG3E8_V }, // 4997 |
| 26268 | { PseudoVLSSEG3E8_V_M2_MASK, VLSSEG3E8_V }, // 4998 |
| 26269 | { PseudoVLSSEG3E8_V_MF2, VLSSEG3E8_V }, // 4999 |
| 26270 | { PseudoVLSSEG3E8_V_MF2_MASK, VLSSEG3E8_V }, // 5000 |
| 26271 | { PseudoVLSSEG3E8_V_MF4, VLSSEG3E8_V }, // 5001 |
| 26272 | { PseudoVLSSEG3E8_V_MF4_MASK, VLSSEG3E8_V }, // 5002 |
| 26273 | { PseudoVLSSEG3E8_V_MF8, VLSSEG3E8_V }, // 5003 |
| 26274 | { PseudoVLSSEG3E8_V_MF8_MASK, VLSSEG3E8_V }, // 5004 |
| 26275 | { PseudoVLSSEG4E16_V_M1, VLSSEG4E16_V }, // 5005 |
| 26276 | { PseudoVLSSEG4E16_V_M1_MASK, VLSSEG4E16_V }, // 5006 |
| 26277 | { PseudoVLSSEG4E16_V_M2, VLSSEG4E16_V }, // 5007 |
| 26278 | { PseudoVLSSEG4E16_V_M2_MASK, VLSSEG4E16_V }, // 5008 |
| 26279 | { PseudoVLSSEG4E16_V_MF2, VLSSEG4E16_V }, // 5009 |
| 26280 | { PseudoVLSSEG4E16_V_MF2_MASK, VLSSEG4E16_V }, // 5010 |
| 26281 | { PseudoVLSSEG4E16_V_MF4, VLSSEG4E16_V }, // 5011 |
| 26282 | { PseudoVLSSEG4E16_V_MF4_MASK, VLSSEG4E16_V }, // 5012 |
| 26283 | { PseudoVLSSEG4E32_V_M1, VLSSEG4E32_V }, // 5013 |
| 26284 | { PseudoVLSSEG4E32_V_M1_MASK, VLSSEG4E32_V }, // 5014 |
| 26285 | { PseudoVLSSEG4E32_V_M2, VLSSEG4E32_V }, // 5015 |
| 26286 | { PseudoVLSSEG4E32_V_M2_MASK, VLSSEG4E32_V }, // 5016 |
| 26287 | { PseudoVLSSEG4E32_V_MF2, VLSSEG4E32_V }, // 5017 |
| 26288 | { PseudoVLSSEG4E32_V_MF2_MASK, VLSSEG4E32_V }, // 5018 |
| 26289 | { PseudoVLSSEG4E64_V_M1, VLSSEG4E64_V }, // 5019 |
| 26290 | { PseudoVLSSEG4E64_V_M1_MASK, VLSSEG4E64_V }, // 5020 |
| 26291 | { PseudoVLSSEG4E64_V_M2, VLSSEG4E64_V }, // 5021 |
| 26292 | { PseudoVLSSEG4E64_V_M2_MASK, VLSSEG4E64_V }, // 5022 |
| 26293 | { PseudoVLSSEG4E8_V_M1, VLSSEG4E8_V }, // 5023 |
| 26294 | { PseudoVLSSEG4E8_V_M1_MASK, VLSSEG4E8_V }, // 5024 |
| 26295 | { PseudoVLSSEG4E8_V_M2, VLSSEG4E8_V }, // 5025 |
| 26296 | { PseudoVLSSEG4E8_V_M2_MASK, VLSSEG4E8_V }, // 5026 |
| 26297 | { PseudoVLSSEG4E8_V_MF2, VLSSEG4E8_V }, // 5027 |
| 26298 | { PseudoVLSSEG4E8_V_MF2_MASK, VLSSEG4E8_V }, // 5028 |
| 26299 | { PseudoVLSSEG4E8_V_MF4, VLSSEG4E8_V }, // 5029 |
| 26300 | { PseudoVLSSEG4E8_V_MF4_MASK, VLSSEG4E8_V }, // 5030 |
| 26301 | { PseudoVLSSEG4E8_V_MF8, VLSSEG4E8_V }, // 5031 |
| 26302 | { PseudoVLSSEG4E8_V_MF8_MASK, VLSSEG4E8_V }, // 5032 |
| 26303 | { PseudoVLSSEG5E16_V_M1, VLSSEG5E16_V }, // 5033 |
| 26304 | { PseudoVLSSEG5E16_V_M1_MASK, VLSSEG5E16_V }, // 5034 |
| 26305 | { PseudoVLSSEG5E16_V_MF2, VLSSEG5E16_V }, // 5035 |
| 26306 | { PseudoVLSSEG5E16_V_MF2_MASK, VLSSEG5E16_V }, // 5036 |
| 26307 | { PseudoVLSSEG5E16_V_MF4, VLSSEG5E16_V }, // 5037 |
| 26308 | { PseudoVLSSEG5E16_V_MF4_MASK, VLSSEG5E16_V }, // 5038 |
| 26309 | { PseudoVLSSEG5E32_V_M1, VLSSEG5E32_V }, // 5039 |
| 26310 | { PseudoVLSSEG5E32_V_M1_MASK, VLSSEG5E32_V }, // 5040 |
| 26311 | { PseudoVLSSEG5E32_V_MF2, VLSSEG5E32_V }, // 5041 |
| 26312 | { PseudoVLSSEG5E32_V_MF2_MASK, VLSSEG5E32_V }, // 5042 |
| 26313 | { PseudoVLSSEG5E64_V_M1, VLSSEG5E64_V }, // 5043 |
| 26314 | { PseudoVLSSEG5E64_V_M1_MASK, VLSSEG5E64_V }, // 5044 |
| 26315 | { PseudoVLSSEG5E8_V_M1, VLSSEG5E8_V }, // 5045 |
| 26316 | { PseudoVLSSEG5E8_V_M1_MASK, VLSSEG5E8_V }, // 5046 |
| 26317 | { PseudoVLSSEG5E8_V_MF2, VLSSEG5E8_V }, // 5047 |
| 26318 | { PseudoVLSSEG5E8_V_MF2_MASK, VLSSEG5E8_V }, // 5048 |
| 26319 | { PseudoVLSSEG5E8_V_MF4, VLSSEG5E8_V }, // 5049 |
| 26320 | { PseudoVLSSEG5E8_V_MF4_MASK, VLSSEG5E8_V }, // 5050 |
| 26321 | { PseudoVLSSEG5E8_V_MF8, VLSSEG5E8_V }, // 5051 |
| 26322 | { PseudoVLSSEG5E8_V_MF8_MASK, VLSSEG5E8_V }, // 5052 |
| 26323 | { PseudoVLSSEG6E16_V_M1, VLSSEG6E16_V }, // 5053 |
| 26324 | { PseudoVLSSEG6E16_V_M1_MASK, VLSSEG6E16_V }, // 5054 |
| 26325 | { PseudoVLSSEG6E16_V_MF2, VLSSEG6E16_V }, // 5055 |
| 26326 | { PseudoVLSSEG6E16_V_MF2_MASK, VLSSEG6E16_V }, // 5056 |
| 26327 | { PseudoVLSSEG6E16_V_MF4, VLSSEG6E16_V }, // 5057 |
| 26328 | { PseudoVLSSEG6E16_V_MF4_MASK, VLSSEG6E16_V }, // 5058 |
| 26329 | { PseudoVLSSEG6E32_V_M1, VLSSEG6E32_V }, // 5059 |
| 26330 | { PseudoVLSSEG6E32_V_M1_MASK, VLSSEG6E32_V }, // 5060 |
| 26331 | { PseudoVLSSEG6E32_V_MF2, VLSSEG6E32_V }, // 5061 |
| 26332 | { PseudoVLSSEG6E32_V_MF2_MASK, VLSSEG6E32_V }, // 5062 |
| 26333 | { PseudoVLSSEG6E64_V_M1, VLSSEG6E64_V }, // 5063 |
| 26334 | { PseudoVLSSEG6E64_V_M1_MASK, VLSSEG6E64_V }, // 5064 |
| 26335 | { PseudoVLSSEG6E8_V_M1, VLSSEG6E8_V }, // 5065 |
| 26336 | { PseudoVLSSEG6E8_V_M1_MASK, VLSSEG6E8_V }, // 5066 |
| 26337 | { PseudoVLSSEG6E8_V_MF2, VLSSEG6E8_V }, // 5067 |
| 26338 | { PseudoVLSSEG6E8_V_MF2_MASK, VLSSEG6E8_V }, // 5068 |
| 26339 | { PseudoVLSSEG6E8_V_MF4, VLSSEG6E8_V }, // 5069 |
| 26340 | { PseudoVLSSEG6E8_V_MF4_MASK, VLSSEG6E8_V }, // 5070 |
| 26341 | { PseudoVLSSEG6E8_V_MF8, VLSSEG6E8_V }, // 5071 |
| 26342 | { PseudoVLSSEG6E8_V_MF8_MASK, VLSSEG6E8_V }, // 5072 |
| 26343 | { PseudoVLSSEG7E16_V_M1, VLSSEG7E16_V }, // 5073 |
| 26344 | { PseudoVLSSEG7E16_V_M1_MASK, VLSSEG7E16_V }, // 5074 |
| 26345 | { PseudoVLSSEG7E16_V_MF2, VLSSEG7E16_V }, // 5075 |
| 26346 | { PseudoVLSSEG7E16_V_MF2_MASK, VLSSEG7E16_V }, // 5076 |
| 26347 | { PseudoVLSSEG7E16_V_MF4, VLSSEG7E16_V }, // 5077 |
| 26348 | { PseudoVLSSEG7E16_V_MF4_MASK, VLSSEG7E16_V }, // 5078 |
| 26349 | { PseudoVLSSEG7E32_V_M1, VLSSEG7E32_V }, // 5079 |
| 26350 | { PseudoVLSSEG7E32_V_M1_MASK, VLSSEG7E32_V }, // 5080 |
| 26351 | { PseudoVLSSEG7E32_V_MF2, VLSSEG7E32_V }, // 5081 |
| 26352 | { PseudoVLSSEG7E32_V_MF2_MASK, VLSSEG7E32_V }, // 5082 |
| 26353 | { PseudoVLSSEG7E64_V_M1, VLSSEG7E64_V }, // 5083 |
| 26354 | { PseudoVLSSEG7E64_V_M1_MASK, VLSSEG7E64_V }, // 5084 |
| 26355 | { PseudoVLSSEG7E8_V_M1, VLSSEG7E8_V }, // 5085 |
| 26356 | { PseudoVLSSEG7E8_V_M1_MASK, VLSSEG7E8_V }, // 5086 |
| 26357 | { PseudoVLSSEG7E8_V_MF2, VLSSEG7E8_V }, // 5087 |
| 26358 | { PseudoVLSSEG7E8_V_MF2_MASK, VLSSEG7E8_V }, // 5088 |
| 26359 | { PseudoVLSSEG7E8_V_MF4, VLSSEG7E8_V }, // 5089 |
| 26360 | { PseudoVLSSEG7E8_V_MF4_MASK, VLSSEG7E8_V }, // 5090 |
| 26361 | { PseudoVLSSEG7E8_V_MF8, VLSSEG7E8_V }, // 5091 |
| 26362 | { PseudoVLSSEG7E8_V_MF8_MASK, VLSSEG7E8_V }, // 5092 |
| 26363 | { PseudoVLSSEG8E16_V_M1, VLSSEG8E16_V }, // 5093 |
| 26364 | { PseudoVLSSEG8E16_V_M1_MASK, VLSSEG8E16_V }, // 5094 |
| 26365 | { PseudoVLSSEG8E16_V_MF2, VLSSEG8E16_V }, // 5095 |
| 26366 | { PseudoVLSSEG8E16_V_MF2_MASK, VLSSEG8E16_V }, // 5096 |
| 26367 | { PseudoVLSSEG8E16_V_MF4, VLSSEG8E16_V }, // 5097 |
| 26368 | { PseudoVLSSEG8E16_V_MF4_MASK, VLSSEG8E16_V }, // 5098 |
| 26369 | { PseudoVLSSEG8E32_V_M1, VLSSEG8E32_V }, // 5099 |
| 26370 | { PseudoVLSSEG8E32_V_M1_MASK, VLSSEG8E32_V }, // 5100 |
| 26371 | { PseudoVLSSEG8E32_V_MF2, VLSSEG8E32_V }, // 5101 |
| 26372 | { PseudoVLSSEG8E32_V_MF2_MASK, VLSSEG8E32_V }, // 5102 |
| 26373 | { PseudoVLSSEG8E64_V_M1, VLSSEG8E64_V }, // 5103 |
| 26374 | { PseudoVLSSEG8E64_V_M1_MASK, VLSSEG8E64_V }, // 5104 |
| 26375 | { PseudoVLSSEG8E8_V_M1, VLSSEG8E8_V }, // 5105 |
| 26376 | { PseudoVLSSEG8E8_V_M1_MASK, VLSSEG8E8_V }, // 5106 |
| 26377 | { PseudoVLSSEG8E8_V_MF2, VLSSEG8E8_V }, // 5107 |
| 26378 | { PseudoVLSSEG8E8_V_MF2_MASK, VLSSEG8E8_V }, // 5108 |
| 26379 | { PseudoVLSSEG8E8_V_MF4, VLSSEG8E8_V }, // 5109 |
| 26380 | { PseudoVLSSEG8E8_V_MF4_MASK, VLSSEG8E8_V }, // 5110 |
| 26381 | { PseudoVLSSEG8E8_V_MF8, VLSSEG8E8_V }, // 5111 |
| 26382 | { PseudoVLSSEG8E8_V_MF8_MASK, VLSSEG8E8_V }, // 5112 |
| 26383 | { PseudoVLUXEI16_V_M1_M1, VLUXEI16_V }, // 5113 |
| 26384 | { PseudoVLUXEI16_V_M1_M1_MASK, VLUXEI16_V }, // 5114 |
| 26385 | { PseudoVLUXEI16_V_M1_M2, VLUXEI16_V }, // 5115 |
| 26386 | { PseudoVLUXEI16_V_M1_M2_MASK, VLUXEI16_V }, // 5116 |
| 26387 | { PseudoVLUXEI16_V_M1_M4, VLUXEI16_V }, // 5117 |
| 26388 | { PseudoVLUXEI16_V_M1_M4_MASK, VLUXEI16_V }, // 5118 |
| 26389 | { PseudoVLUXEI16_V_M1_MF2, VLUXEI16_V }, // 5119 |
| 26390 | { PseudoVLUXEI16_V_M1_MF2_MASK, VLUXEI16_V }, // 5120 |
| 26391 | { PseudoVLUXEI16_V_M2_M1, VLUXEI16_V }, // 5121 |
| 26392 | { PseudoVLUXEI16_V_M2_M1_MASK, VLUXEI16_V }, // 5122 |
| 26393 | { PseudoVLUXEI16_V_M2_M2, VLUXEI16_V }, // 5123 |
| 26394 | { PseudoVLUXEI16_V_M2_M2_MASK, VLUXEI16_V }, // 5124 |
| 26395 | { PseudoVLUXEI16_V_M2_M4, VLUXEI16_V }, // 5125 |
| 26396 | { PseudoVLUXEI16_V_M2_M4_MASK, VLUXEI16_V }, // 5126 |
| 26397 | { PseudoVLUXEI16_V_M2_M8, VLUXEI16_V }, // 5127 |
| 26398 | { PseudoVLUXEI16_V_M2_M8_MASK, VLUXEI16_V }, // 5128 |
| 26399 | { PseudoVLUXEI16_V_M4_M2, VLUXEI16_V }, // 5129 |
| 26400 | { PseudoVLUXEI16_V_M4_M2_MASK, VLUXEI16_V }, // 5130 |
| 26401 | { PseudoVLUXEI16_V_M4_M4, VLUXEI16_V }, // 5131 |
| 26402 | { PseudoVLUXEI16_V_M4_M4_MASK, VLUXEI16_V }, // 5132 |
| 26403 | { PseudoVLUXEI16_V_M4_M8, VLUXEI16_V }, // 5133 |
| 26404 | { PseudoVLUXEI16_V_M4_M8_MASK, VLUXEI16_V }, // 5134 |
| 26405 | { PseudoVLUXEI16_V_M8_M4, VLUXEI16_V }, // 5135 |
| 26406 | { PseudoVLUXEI16_V_M8_M4_MASK, VLUXEI16_V }, // 5136 |
| 26407 | { PseudoVLUXEI16_V_M8_M8, VLUXEI16_V }, // 5137 |
| 26408 | { PseudoVLUXEI16_V_M8_M8_MASK, VLUXEI16_V }, // 5138 |
| 26409 | { PseudoVLUXEI16_V_MF2_M1, VLUXEI16_V }, // 5139 |
| 26410 | { PseudoVLUXEI16_V_MF2_M1_MASK, VLUXEI16_V }, // 5140 |
| 26411 | { PseudoVLUXEI16_V_MF2_M2, VLUXEI16_V }, // 5141 |
| 26412 | { PseudoVLUXEI16_V_MF2_M2_MASK, VLUXEI16_V }, // 5142 |
| 26413 | { PseudoVLUXEI16_V_MF2_MF2, VLUXEI16_V }, // 5143 |
| 26414 | { PseudoVLUXEI16_V_MF2_MF2_MASK, VLUXEI16_V }, // 5144 |
| 26415 | { PseudoVLUXEI16_V_MF2_MF4, VLUXEI16_V }, // 5145 |
| 26416 | { PseudoVLUXEI16_V_MF2_MF4_MASK, VLUXEI16_V }, // 5146 |
| 26417 | { PseudoVLUXEI16_V_MF4_M1, VLUXEI16_V }, // 5147 |
| 26418 | { PseudoVLUXEI16_V_MF4_M1_MASK, VLUXEI16_V }, // 5148 |
| 26419 | { PseudoVLUXEI16_V_MF4_MF2, VLUXEI16_V }, // 5149 |
| 26420 | { PseudoVLUXEI16_V_MF4_MF2_MASK, VLUXEI16_V }, // 5150 |
| 26421 | { PseudoVLUXEI16_V_MF4_MF4, VLUXEI16_V }, // 5151 |
| 26422 | { PseudoVLUXEI16_V_MF4_MF4_MASK, VLUXEI16_V }, // 5152 |
| 26423 | { PseudoVLUXEI16_V_MF4_MF8, VLUXEI16_V }, // 5153 |
| 26424 | { PseudoVLUXEI16_V_MF4_MF8_MASK, VLUXEI16_V }, // 5154 |
| 26425 | { PseudoVLUXEI32_V_M1_M1, VLUXEI32_V }, // 5155 |
| 26426 | { PseudoVLUXEI32_V_M1_M1_MASK, VLUXEI32_V }, // 5156 |
| 26427 | { PseudoVLUXEI32_V_M1_M2, VLUXEI32_V }, // 5157 |
| 26428 | { PseudoVLUXEI32_V_M1_M2_MASK, VLUXEI32_V }, // 5158 |
| 26429 | { PseudoVLUXEI32_V_M1_MF2, VLUXEI32_V }, // 5159 |
| 26430 | { PseudoVLUXEI32_V_M1_MF2_MASK, VLUXEI32_V }, // 5160 |
| 26431 | { PseudoVLUXEI32_V_M1_MF4, VLUXEI32_V }, // 5161 |
| 26432 | { PseudoVLUXEI32_V_M1_MF4_MASK, VLUXEI32_V }, // 5162 |
| 26433 | { PseudoVLUXEI32_V_M2_M1, VLUXEI32_V }, // 5163 |
| 26434 | { PseudoVLUXEI32_V_M2_M1_MASK, VLUXEI32_V }, // 5164 |
| 26435 | { PseudoVLUXEI32_V_M2_M2, VLUXEI32_V }, // 5165 |
| 26436 | { PseudoVLUXEI32_V_M2_M2_MASK, VLUXEI32_V }, // 5166 |
| 26437 | { PseudoVLUXEI32_V_M2_M4, VLUXEI32_V }, // 5167 |
| 26438 | { PseudoVLUXEI32_V_M2_M4_MASK, VLUXEI32_V }, // 5168 |
| 26439 | { PseudoVLUXEI32_V_M2_MF2, VLUXEI32_V }, // 5169 |
| 26440 | { PseudoVLUXEI32_V_M2_MF2_MASK, VLUXEI32_V }, // 5170 |
| 26441 | { PseudoVLUXEI32_V_M4_M1, VLUXEI32_V }, // 5171 |
| 26442 | { PseudoVLUXEI32_V_M4_M1_MASK, VLUXEI32_V }, // 5172 |
| 26443 | { PseudoVLUXEI32_V_M4_M2, VLUXEI32_V }, // 5173 |
| 26444 | { PseudoVLUXEI32_V_M4_M2_MASK, VLUXEI32_V }, // 5174 |
| 26445 | { PseudoVLUXEI32_V_M4_M4, VLUXEI32_V }, // 5175 |
| 26446 | { PseudoVLUXEI32_V_M4_M4_MASK, VLUXEI32_V }, // 5176 |
| 26447 | { PseudoVLUXEI32_V_M4_M8, VLUXEI32_V }, // 5177 |
| 26448 | { PseudoVLUXEI32_V_M4_M8_MASK, VLUXEI32_V }, // 5178 |
| 26449 | { PseudoVLUXEI32_V_M8_M2, VLUXEI32_V }, // 5179 |
| 26450 | { PseudoVLUXEI32_V_M8_M2_MASK, VLUXEI32_V }, // 5180 |
| 26451 | { PseudoVLUXEI32_V_M8_M4, VLUXEI32_V }, // 5181 |
| 26452 | { PseudoVLUXEI32_V_M8_M4_MASK, VLUXEI32_V }, // 5182 |
| 26453 | { PseudoVLUXEI32_V_M8_M8, VLUXEI32_V }, // 5183 |
| 26454 | { PseudoVLUXEI32_V_M8_M8_MASK, VLUXEI32_V }, // 5184 |
| 26455 | { PseudoVLUXEI32_V_MF2_M1, VLUXEI32_V }, // 5185 |
| 26456 | { PseudoVLUXEI32_V_MF2_M1_MASK, VLUXEI32_V }, // 5186 |
| 26457 | { PseudoVLUXEI32_V_MF2_MF2, VLUXEI32_V }, // 5187 |
| 26458 | { PseudoVLUXEI32_V_MF2_MF2_MASK, VLUXEI32_V }, // 5188 |
| 26459 | { PseudoVLUXEI32_V_MF2_MF4, VLUXEI32_V }, // 5189 |
| 26460 | { PseudoVLUXEI32_V_MF2_MF4_MASK, VLUXEI32_V }, // 5190 |
| 26461 | { PseudoVLUXEI32_V_MF2_MF8, VLUXEI32_V }, // 5191 |
| 26462 | { PseudoVLUXEI32_V_MF2_MF8_MASK, VLUXEI32_V }, // 5192 |
| 26463 | { PseudoVLUXEI64_V_M1_M1, VLUXEI64_V }, // 5193 |
| 26464 | { PseudoVLUXEI64_V_M1_M1_MASK, VLUXEI64_V }, // 5194 |
| 26465 | { PseudoVLUXEI64_V_M1_MF2, VLUXEI64_V }, // 5195 |
| 26466 | { PseudoVLUXEI64_V_M1_MF2_MASK, VLUXEI64_V }, // 5196 |
| 26467 | { PseudoVLUXEI64_V_M1_MF4, VLUXEI64_V }, // 5197 |
| 26468 | { PseudoVLUXEI64_V_M1_MF4_MASK, VLUXEI64_V }, // 5198 |
| 26469 | { PseudoVLUXEI64_V_M1_MF8, VLUXEI64_V }, // 5199 |
| 26470 | { PseudoVLUXEI64_V_M1_MF8_MASK, VLUXEI64_V }, // 5200 |
| 26471 | { PseudoVLUXEI64_V_M2_M1, VLUXEI64_V }, // 5201 |
| 26472 | { PseudoVLUXEI64_V_M2_M1_MASK, VLUXEI64_V }, // 5202 |
| 26473 | { PseudoVLUXEI64_V_M2_M2, VLUXEI64_V }, // 5203 |
| 26474 | { PseudoVLUXEI64_V_M2_M2_MASK, VLUXEI64_V }, // 5204 |
| 26475 | { PseudoVLUXEI64_V_M2_MF2, VLUXEI64_V }, // 5205 |
| 26476 | { PseudoVLUXEI64_V_M2_MF2_MASK, VLUXEI64_V }, // 5206 |
| 26477 | { PseudoVLUXEI64_V_M2_MF4, VLUXEI64_V }, // 5207 |
| 26478 | { PseudoVLUXEI64_V_M2_MF4_MASK, VLUXEI64_V }, // 5208 |
| 26479 | { PseudoVLUXEI64_V_M4_M1, VLUXEI64_V }, // 5209 |
| 26480 | { PseudoVLUXEI64_V_M4_M1_MASK, VLUXEI64_V }, // 5210 |
| 26481 | { PseudoVLUXEI64_V_M4_M2, VLUXEI64_V }, // 5211 |
| 26482 | { PseudoVLUXEI64_V_M4_M2_MASK, VLUXEI64_V }, // 5212 |
| 26483 | { PseudoVLUXEI64_V_M4_M4, VLUXEI64_V }, // 5213 |
| 26484 | { PseudoVLUXEI64_V_M4_M4_MASK, VLUXEI64_V }, // 5214 |
| 26485 | { PseudoVLUXEI64_V_M4_MF2, VLUXEI64_V }, // 5215 |
| 26486 | { PseudoVLUXEI64_V_M4_MF2_MASK, VLUXEI64_V }, // 5216 |
| 26487 | { PseudoVLUXEI64_V_M8_M1, VLUXEI64_V }, // 5217 |
| 26488 | { PseudoVLUXEI64_V_M8_M1_MASK, VLUXEI64_V }, // 5218 |
| 26489 | { PseudoVLUXEI64_V_M8_M2, VLUXEI64_V }, // 5219 |
| 26490 | { PseudoVLUXEI64_V_M8_M2_MASK, VLUXEI64_V }, // 5220 |
| 26491 | { PseudoVLUXEI64_V_M8_M4, VLUXEI64_V }, // 5221 |
| 26492 | { PseudoVLUXEI64_V_M8_M4_MASK, VLUXEI64_V }, // 5222 |
| 26493 | { PseudoVLUXEI64_V_M8_M8, VLUXEI64_V }, // 5223 |
| 26494 | { PseudoVLUXEI64_V_M8_M8_MASK, VLUXEI64_V }, // 5224 |
| 26495 | { PseudoVLUXEI8_V_M1_M1, VLUXEI8_V }, // 5225 |
| 26496 | { PseudoVLUXEI8_V_M1_M1_MASK, VLUXEI8_V }, // 5226 |
| 26497 | { PseudoVLUXEI8_V_M1_M2, VLUXEI8_V }, // 5227 |
| 26498 | { PseudoVLUXEI8_V_M1_M2_MASK, VLUXEI8_V }, // 5228 |
| 26499 | { PseudoVLUXEI8_V_M1_M4, VLUXEI8_V }, // 5229 |
| 26500 | { PseudoVLUXEI8_V_M1_M4_MASK, VLUXEI8_V }, // 5230 |
| 26501 | { PseudoVLUXEI8_V_M1_M8, VLUXEI8_V }, // 5231 |
| 26502 | { PseudoVLUXEI8_V_M1_M8_MASK, VLUXEI8_V }, // 5232 |
| 26503 | { PseudoVLUXEI8_V_M2_M2, VLUXEI8_V }, // 5233 |
| 26504 | { PseudoVLUXEI8_V_M2_M2_MASK, VLUXEI8_V }, // 5234 |
| 26505 | { PseudoVLUXEI8_V_M2_M4, VLUXEI8_V }, // 5235 |
| 26506 | { PseudoVLUXEI8_V_M2_M4_MASK, VLUXEI8_V }, // 5236 |
| 26507 | { PseudoVLUXEI8_V_M2_M8, VLUXEI8_V }, // 5237 |
| 26508 | { PseudoVLUXEI8_V_M2_M8_MASK, VLUXEI8_V }, // 5238 |
| 26509 | { PseudoVLUXEI8_V_M4_M4, VLUXEI8_V }, // 5239 |
| 26510 | { PseudoVLUXEI8_V_M4_M4_MASK, VLUXEI8_V }, // 5240 |
| 26511 | { PseudoVLUXEI8_V_M4_M8, VLUXEI8_V }, // 5241 |
| 26512 | { PseudoVLUXEI8_V_M4_M8_MASK, VLUXEI8_V }, // 5242 |
| 26513 | { PseudoVLUXEI8_V_M8_M8, VLUXEI8_V }, // 5243 |
| 26514 | { PseudoVLUXEI8_V_M8_M8_MASK, VLUXEI8_V }, // 5244 |
| 26515 | { PseudoVLUXEI8_V_MF2_M1, VLUXEI8_V }, // 5245 |
| 26516 | { PseudoVLUXEI8_V_MF2_M1_MASK, VLUXEI8_V }, // 5246 |
| 26517 | { PseudoVLUXEI8_V_MF2_M2, VLUXEI8_V }, // 5247 |
| 26518 | { PseudoVLUXEI8_V_MF2_M2_MASK, VLUXEI8_V }, // 5248 |
| 26519 | { PseudoVLUXEI8_V_MF2_M4, VLUXEI8_V }, // 5249 |
| 26520 | { PseudoVLUXEI8_V_MF2_M4_MASK, VLUXEI8_V }, // 5250 |
| 26521 | { PseudoVLUXEI8_V_MF2_MF2, VLUXEI8_V }, // 5251 |
| 26522 | { PseudoVLUXEI8_V_MF2_MF2_MASK, VLUXEI8_V }, // 5252 |
| 26523 | { PseudoVLUXEI8_V_MF4_M1, VLUXEI8_V }, // 5253 |
| 26524 | { PseudoVLUXEI8_V_MF4_M1_MASK, VLUXEI8_V }, // 5254 |
| 26525 | { PseudoVLUXEI8_V_MF4_M2, VLUXEI8_V }, // 5255 |
| 26526 | { PseudoVLUXEI8_V_MF4_M2_MASK, VLUXEI8_V }, // 5256 |
| 26527 | { PseudoVLUXEI8_V_MF4_MF2, VLUXEI8_V }, // 5257 |
| 26528 | { PseudoVLUXEI8_V_MF4_MF2_MASK, VLUXEI8_V }, // 5258 |
| 26529 | { PseudoVLUXEI8_V_MF4_MF4, VLUXEI8_V }, // 5259 |
| 26530 | { PseudoVLUXEI8_V_MF4_MF4_MASK, VLUXEI8_V }, // 5260 |
| 26531 | { PseudoVLUXEI8_V_MF8_M1, VLUXEI8_V }, // 5261 |
| 26532 | { PseudoVLUXEI8_V_MF8_M1_MASK, VLUXEI8_V }, // 5262 |
| 26533 | { PseudoVLUXEI8_V_MF8_MF2, VLUXEI8_V }, // 5263 |
| 26534 | { PseudoVLUXEI8_V_MF8_MF2_MASK, VLUXEI8_V }, // 5264 |
| 26535 | { PseudoVLUXEI8_V_MF8_MF4, VLUXEI8_V }, // 5265 |
| 26536 | { PseudoVLUXEI8_V_MF8_MF4_MASK, VLUXEI8_V }, // 5266 |
| 26537 | { PseudoVLUXEI8_V_MF8_MF8, VLUXEI8_V }, // 5267 |
| 26538 | { PseudoVLUXEI8_V_MF8_MF8_MASK, VLUXEI8_V }, // 5268 |
| 26539 | { PseudoVLUXSEG2EI16_V_M1_M1, VLUXSEG2EI16_V }, // 5269 |
| 26540 | { PseudoVLUXSEG2EI16_V_M1_M1_MASK, VLUXSEG2EI16_V }, // 5270 |
| 26541 | { PseudoVLUXSEG2EI16_V_M1_M2, VLUXSEG2EI16_V }, // 5271 |
| 26542 | { PseudoVLUXSEG2EI16_V_M1_M2_MASK, VLUXSEG2EI16_V }, // 5272 |
| 26543 | { PseudoVLUXSEG2EI16_V_M1_M4, VLUXSEG2EI16_V }, // 5273 |
| 26544 | { PseudoVLUXSEG2EI16_V_M1_M4_MASK, VLUXSEG2EI16_V }, // 5274 |
| 26545 | { PseudoVLUXSEG2EI16_V_M1_MF2, VLUXSEG2EI16_V }, // 5275 |
| 26546 | { PseudoVLUXSEG2EI16_V_M1_MF2_MASK, VLUXSEG2EI16_V }, // 5276 |
| 26547 | { PseudoVLUXSEG2EI16_V_M2_M1, VLUXSEG2EI16_V }, // 5277 |
| 26548 | { PseudoVLUXSEG2EI16_V_M2_M1_MASK, VLUXSEG2EI16_V }, // 5278 |
| 26549 | { PseudoVLUXSEG2EI16_V_M2_M2, VLUXSEG2EI16_V }, // 5279 |
| 26550 | { PseudoVLUXSEG2EI16_V_M2_M2_MASK, VLUXSEG2EI16_V }, // 5280 |
| 26551 | { PseudoVLUXSEG2EI16_V_M2_M4, VLUXSEG2EI16_V }, // 5281 |
| 26552 | { PseudoVLUXSEG2EI16_V_M2_M4_MASK, VLUXSEG2EI16_V }, // 5282 |
| 26553 | { PseudoVLUXSEG2EI16_V_M4_M2, VLUXSEG2EI16_V }, // 5283 |
| 26554 | { PseudoVLUXSEG2EI16_V_M4_M2_MASK, VLUXSEG2EI16_V }, // 5284 |
| 26555 | { PseudoVLUXSEG2EI16_V_M4_M4, VLUXSEG2EI16_V }, // 5285 |
| 26556 | { PseudoVLUXSEG2EI16_V_M4_M4_MASK, VLUXSEG2EI16_V }, // 5286 |
| 26557 | { PseudoVLUXSEG2EI16_V_M8_M4, VLUXSEG2EI16_V }, // 5287 |
| 26558 | { PseudoVLUXSEG2EI16_V_M8_M4_MASK, VLUXSEG2EI16_V }, // 5288 |
| 26559 | { PseudoVLUXSEG2EI16_V_MF2_M1, VLUXSEG2EI16_V }, // 5289 |
| 26560 | { PseudoVLUXSEG2EI16_V_MF2_M1_MASK, VLUXSEG2EI16_V }, // 5290 |
| 26561 | { PseudoVLUXSEG2EI16_V_MF2_M2, VLUXSEG2EI16_V }, // 5291 |
| 26562 | { PseudoVLUXSEG2EI16_V_MF2_M2_MASK, VLUXSEG2EI16_V }, // 5292 |
| 26563 | { PseudoVLUXSEG2EI16_V_MF2_MF2, VLUXSEG2EI16_V }, // 5293 |
| 26564 | { PseudoVLUXSEG2EI16_V_MF2_MF2_MASK, VLUXSEG2EI16_V }, // 5294 |
| 26565 | { PseudoVLUXSEG2EI16_V_MF2_MF4, VLUXSEG2EI16_V }, // 5295 |
| 26566 | { PseudoVLUXSEG2EI16_V_MF2_MF4_MASK, VLUXSEG2EI16_V }, // 5296 |
| 26567 | { PseudoVLUXSEG2EI16_V_MF4_M1, VLUXSEG2EI16_V }, // 5297 |
| 26568 | { PseudoVLUXSEG2EI16_V_MF4_M1_MASK, VLUXSEG2EI16_V }, // 5298 |
| 26569 | { PseudoVLUXSEG2EI16_V_MF4_MF2, VLUXSEG2EI16_V }, // 5299 |
| 26570 | { PseudoVLUXSEG2EI16_V_MF4_MF2_MASK, VLUXSEG2EI16_V }, // 5300 |
| 26571 | { PseudoVLUXSEG2EI16_V_MF4_MF4, VLUXSEG2EI16_V }, // 5301 |
| 26572 | { PseudoVLUXSEG2EI16_V_MF4_MF4_MASK, VLUXSEG2EI16_V }, // 5302 |
| 26573 | { PseudoVLUXSEG2EI16_V_MF4_MF8, VLUXSEG2EI16_V }, // 5303 |
| 26574 | { PseudoVLUXSEG2EI16_V_MF4_MF8_MASK, VLUXSEG2EI16_V }, // 5304 |
| 26575 | { PseudoVLUXSEG2EI32_V_M1_M1, VLUXSEG2EI32_V }, // 5305 |
| 26576 | { PseudoVLUXSEG2EI32_V_M1_M1_MASK, VLUXSEG2EI32_V }, // 5306 |
| 26577 | { PseudoVLUXSEG2EI32_V_M1_M2, VLUXSEG2EI32_V }, // 5307 |
| 26578 | { PseudoVLUXSEG2EI32_V_M1_M2_MASK, VLUXSEG2EI32_V }, // 5308 |
| 26579 | { PseudoVLUXSEG2EI32_V_M1_MF2, VLUXSEG2EI32_V }, // 5309 |
| 26580 | { PseudoVLUXSEG2EI32_V_M1_MF2_MASK, VLUXSEG2EI32_V }, // 5310 |
| 26581 | { PseudoVLUXSEG2EI32_V_M1_MF4, VLUXSEG2EI32_V }, // 5311 |
| 26582 | { PseudoVLUXSEG2EI32_V_M1_MF4_MASK, VLUXSEG2EI32_V }, // 5312 |
| 26583 | { PseudoVLUXSEG2EI32_V_M2_M1, VLUXSEG2EI32_V }, // 5313 |
| 26584 | { PseudoVLUXSEG2EI32_V_M2_M1_MASK, VLUXSEG2EI32_V }, // 5314 |
| 26585 | { PseudoVLUXSEG2EI32_V_M2_M2, VLUXSEG2EI32_V }, // 5315 |
| 26586 | { PseudoVLUXSEG2EI32_V_M2_M2_MASK, VLUXSEG2EI32_V }, // 5316 |
| 26587 | { PseudoVLUXSEG2EI32_V_M2_M4, VLUXSEG2EI32_V }, // 5317 |
| 26588 | { PseudoVLUXSEG2EI32_V_M2_M4_MASK, VLUXSEG2EI32_V }, // 5318 |
| 26589 | { PseudoVLUXSEG2EI32_V_M2_MF2, VLUXSEG2EI32_V }, // 5319 |
| 26590 | { PseudoVLUXSEG2EI32_V_M2_MF2_MASK, VLUXSEG2EI32_V }, // 5320 |
| 26591 | { PseudoVLUXSEG2EI32_V_M4_M1, VLUXSEG2EI32_V }, // 5321 |
| 26592 | { PseudoVLUXSEG2EI32_V_M4_M1_MASK, VLUXSEG2EI32_V }, // 5322 |
| 26593 | { PseudoVLUXSEG2EI32_V_M4_M2, VLUXSEG2EI32_V }, // 5323 |
| 26594 | { PseudoVLUXSEG2EI32_V_M4_M2_MASK, VLUXSEG2EI32_V }, // 5324 |
| 26595 | { PseudoVLUXSEG2EI32_V_M4_M4, VLUXSEG2EI32_V }, // 5325 |
| 26596 | { PseudoVLUXSEG2EI32_V_M4_M4_MASK, VLUXSEG2EI32_V }, // 5326 |
| 26597 | { PseudoVLUXSEG2EI32_V_M8_M2, VLUXSEG2EI32_V }, // 5327 |
| 26598 | { PseudoVLUXSEG2EI32_V_M8_M2_MASK, VLUXSEG2EI32_V }, // 5328 |
| 26599 | { PseudoVLUXSEG2EI32_V_M8_M4, VLUXSEG2EI32_V }, // 5329 |
| 26600 | { PseudoVLUXSEG2EI32_V_M8_M4_MASK, VLUXSEG2EI32_V }, // 5330 |
| 26601 | { PseudoVLUXSEG2EI32_V_MF2_M1, VLUXSEG2EI32_V }, // 5331 |
| 26602 | { PseudoVLUXSEG2EI32_V_MF2_M1_MASK, VLUXSEG2EI32_V }, // 5332 |
| 26603 | { PseudoVLUXSEG2EI32_V_MF2_MF2, VLUXSEG2EI32_V }, // 5333 |
| 26604 | { PseudoVLUXSEG2EI32_V_MF2_MF2_MASK, VLUXSEG2EI32_V }, // 5334 |
| 26605 | { PseudoVLUXSEG2EI32_V_MF2_MF4, VLUXSEG2EI32_V }, // 5335 |
| 26606 | { PseudoVLUXSEG2EI32_V_MF2_MF4_MASK, VLUXSEG2EI32_V }, // 5336 |
| 26607 | { PseudoVLUXSEG2EI32_V_MF2_MF8, VLUXSEG2EI32_V }, // 5337 |
| 26608 | { PseudoVLUXSEG2EI32_V_MF2_MF8_MASK, VLUXSEG2EI32_V }, // 5338 |
| 26609 | { PseudoVLUXSEG2EI64_V_M1_M1, VLUXSEG2EI64_V }, // 5339 |
| 26610 | { PseudoVLUXSEG2EI64_V_M1_M1_MASK, VLUXSEG2EI64_V }, // 5340 |
| 26611 | { PseudoVLUXSEG2EI64_V_M1_MF2, VLUXSEG2EI64_V }, // 5341 |
| 26612 | { PseudoVLUXSEG2EI64_V_M1_MF2_MASK, VLUXSEG2EI64_V }, // 5342 |
| 26613 | { PseudoVLUXSEG2EI64_V_M1_MF4, VLUXSEG2EI64_V }, // 5343 |
| 26614 | { PseudoVLUXSEG2EI64_V_M1_MF4_MASK, VLUXSEG2EI64_V }, // 5344 |
| 26615 | { PseudoVLUXSEG2EI64_V_M1_MF8, VLUXSEG2EI64_V }, // 5345 |
| 26616 | { PseudoVLUXSEG2EI64_V_M1_MF8_MASK, VLUXSEG2EI64_V }, // 5346 |
| 26617 | { PseudoVLUXSEG2EI64_V_M2_M1, VLUXSEG2EI64_V }, // 5347 |
| 26618 | { PseudoVLUXSEG2EI64_V_M2_M1_MASK, VLUXSEG2EI64_V }, // 5348 |
| 26619 | { PseudoVLUXSEG2EI64_V_M2_M2, VLUXSEG2EI64_V }, // 5349 |
| 26620 | { PseudoVLUXSEG2EI64_V_M2_M2_MASK, VLUXSEG2EI64_V }, // 5350 |
| 26621 | { PseudoVLUXSEG2EI64_V_M2_MF2, VLUXSEG2EI64_V }, // 5351 |
| 26622 | { PseudoVLUXSEG2EI64_V_M2_MF2_MASK, VLUXSEG2EI64_V }, // 5352 |
| 26623 | { PseudoVLUXSEG2EI64_V_M2_MF4, VLUXSEG2EI64_V }, // 5353 |
| 26624 | { PseudoVLUXSEG2EI64_V_M2_MF4_MASK, VLUXSEG2EI64_V }, // 5354 |
| 26625 | { PseudoVLUXSEG2EI64_V_M4_M1, VLUXSEG2EI64_V }, // 5355 |
| 26626 | { PseudoVLUXSEG2EI64_V_M4_M1_MASK, VLUXSEG2EI64_V }, // 5356 |
| 26627 | { PseudoVLUXSEG2EI64_V_M4_M2, VLUXSEG2EI64_V }, // 5357 |
| 26628 | { PseudoVLUXSEG2EI64_V_M4_M2_MASK, VLUXSEG2EI64_V }, // 5358 |
| 26629 | { PseudoVLUXSEG2EI64_V_M4_M4, VLUXSEG2EI64_V }, // 5359 |
| 26630 | { PseudoVLUXSEG2EI64_V_M4_M4_MASK, VLUXSEG2EI64_V }, // 5360 |
| 26631 | { PseudoVLUXSEG2EI64_V_M4_MF2, VLUXSEG2EI64_V }, // 5361 |
| 26632 | { PseudoVLUXSEG2EI64_V_M4_MF2_MASK, VLUXSEG2EI64_V }, // 5362 |
| 26633 | { PseudoVLUXSEG2EI64_V_M8_M1, VLUXSEG2EI64_V }, // 5363 |
| 26634 | { PseudoVLUXSEG2EI64_V_M8_M1_MASK, VLUXSEG2EI64_V }, // 5364 |
| 26635 | { PseudoVLUXSEG2EI64_V_M8_M2, VLUXSEG2EI64_V }, // 5365 |
| 26636 | { PseudoVLUXSEG2EI64_V_M8_M2_MASK, VLUXSEG2EI64_V }, // 5366 |
| 26637 | { PseudoVLUXSEG2EI64_V_M8_M4, VLUXSEG2EI64_V }, // 5367 |
| 26638 | { PseudoVLUXSEG2EI64_V_M8_M4_MASK, VLUXSEG2EI64_V }, // 5368 |
| 26639 | { PseudoVLUXSEG2EI8_V_M1_M1, VLUXSEG2EI8_V }, // 5369 |
| 26640 | { PseudoVLUXSEG2EI8_V_M1_M1_MASK, VLUXSEG2EI8_V }, // 5370 |
| 26641 | { PseudoVLUXSEG2EI8_V_M1_M2, VLUXSEG2EI8_V }, // 5371 |
| 26642 | { PseudoVLUXSEG2EI8_V_M1_M2_MASK, VLUXSEG2EI8_V }, // 5372 |
| 26643 | { PseudoVLUXSEG2EI8_V_M1_M4, VLUXSEG2EI8_V }, // 5373 |
| 26644 | { PseudoVLUXSEG2EI8_V_M1_M4_MASK, VLUXSEG2EI8_V }, // 5374 |
| 26645 | { PseudoVLUXSEG2EI8_V_M2_M2, VLUXSEG2EI8_V }, // 5375 |
| 26646 | { PseudoVLUXSEG2EI8_V_M2_M2_MASK, VLUXSEG2EI8_V }, // 5376 |
| 26647 | { PseudoVLUXSEG2EI8_V_M2_M4, VLUXSEG2EI8_V }, // 5377 |
| 26648 | { PseudoVLUXSEG2EI8_V_M2_M4_MASK, VLUXSEG2EI8_V }, // 5378 |
| 26649 | { PseudoVLUXSEG2EI8_V_M4_M4, VLUXSEG2EI8_V }, // 5379 |
| 26650 | { PseudoVLUXSEG2EI8_V_M4_M4_MASK, VLUXSEG2EI8_V }, // 5380 |
| 26651 | { PseudoVLUXSEG2EI8_V_MF2_M1, VLUXSEG2EI8_V }, // 5381 |
| 26652 | { PseudoVLUXSEG2EI8_V_MF2_M1_MASK, VLUXSEG2EI8_V }, // 5382 |
| 26653 | { PseudoVLUXSEG2EI8_V_MF2_M2, VLUXSEG2EI8_V }, // 5383 |
| 26654 | { PseudoVLUXSEG2EI8_V_MF2_M2_MASK, VLUXSEG2EI8_V }, // 5384 |
| 26655 | { PseudoVLUXSEG2EI8_V_MF2_M4, VLUXSEG2EI8_V }, // 5385 |
| 26656 | { PseudoVLUXSEG2EI8_V_MF2_M4_MASK, VLUXSEG2EI8_V }, // 5386 |
| 26657 | { PseudoVLUXSEG2EI8_V_MF2_MF2, VLUXSEG2EI8_V }, // 5387 |
| 26658 | { PseudoVLUXSEG2EI8_V_MF2_MF2_MASK, VLUXSEG2EI8_V }, // 5388 |
| 26659 | { PseudoVLUXSEG2EI8_V_MF4_M1, VLUXSEG2EI8_V }, // 5389 |
| 26660 | { PseudoVLUXSEG2EI8_V_MF4_M1_MASK, VLUXSEG2EI8_V }, // 5390 |
| 26661 | { PseudoVLUXSEG2EI8_V_MF4_M2, VLUXSEG2EI8_V }, // 5391 |
| 26662 | { PseudoVLUXSEG2EI8_V_MF4_M2_MASK, VLUXSEG2EI8_V }, // 5392 |
| 26663 | { PseudoVLUXSEG2EI8_V_MF4_MF2, VLUXSEG2EI8_V }, // 5393 |
| 26664 | { PseudoVLUXSEG2EI8_V_MF4_MF2_MASK, VLUXSEG2EI8_V }, // 5394 |
| 26665 | { PseudoVLUXSEG2EI8_V_MF4_MF4, VLUXSEG2EI8_V }, // 5395 |
| 26666 | { PseudoVLUXSEG2EI8_V_MF4_MF4_MASK, VLUXSEG2EI8_V }, // 5396 |
| 26667 | { PseudoVLUXSEG2EI8_V_MF8_M1, VLUXSEG2EI8_V }, // 5397 |
| 26668 | { PseudoVLUXSEG2EI8_V_MF8_M1_MASK, VLUXSEG2EI8_V }, // 5398 |
| 26669 | { PseudoVLUXSEG2EI8_V_MF8_MF2, VLUXSEG2EI8_V }, // 5399 |
| 26670 | { PseudoVLUXSEG2EI8_V_MF8_MF2_MASK, VLUXSEG2EI8_V }, // 5400 |
| 26671 | { PseudoVLUXSEG2EI8_V_MF8_MF4, VLUXSEG2EI8_V }, // 5401 |
| 26672 | { PseudoVLUXSEG2EI8_V_MF8_MF4_MASK, VLUXSEG2EI8_V }, // 5402 |
| 26673 | { PseudoVLUXSEG2EI8_V_MF8_MF8, VLUXSEG2EI8_V }, // 5403 |
| 26674 | { PseudoVLUXSEG2EI8_V_MF8_MF8_MASK, VLUXSEG2EI8_V }, // 5404 |
| 26675 | { PseudoVLUXSEG3EI16_V_M1_M1, VLUXSEG3EI16_V }, // 5405 |
| 26676 | { PseudoVLUXSEG3EI16_V_M1_M1_MASK, VLUXSEG3EI16_V }, // 5406 |
| 26677 | { PseudoVLUXSEG3EI16_V_M1_M2, VLUXSEG3EI16_V }, // 5407 |
| 26678 | { PseudoVLUXSEG3EI16_V_M1_M2_MASK, VLUXSEG3EI16_V }, // 5408 |
| 26679 | { PseudoVLUXSEG3EI16_V_M1_MF2, VLUXSEG3EI16_V }, // 5409 |
| 26680 | { PseudoVLUXSEG3EI16_V_M1_MF2_MASK, VLUXSEG3EI16_V }, // 5410 |
| 26681 | { PseudoVLUXSEG3EI16_V_M2_M1, VLUXSEG3EI16_V }, // 5411 |
| 26682 | { PseudoVLUXSEG3EI16_V_M2_M1_MASK, VLUXSEG3EI16_V }, // 5412 |
| 26683 | { PseudoVLUXSEG3EI16_V_M2_M2, VLUXSEG3EI16_V }, // 5413 |
| 26684 | { PseudoVLUXSEG3EI16_V_M2_M2_MASK, VLUXSEG3EI16_V }, // 5414 |
| 26685 | { PseudoVLUXSEG3EI16_V_M4_M2, VLUXSEG3EI16_V }, // 5415 |
| 26686 | { PseudoVLUXSEG3EI16_V_M4_M2_MASK, VLUXSEG3EI16_V }, // 5416 |
| 26687 | { PseudoVLUXSEG3EI16_V_MF2_M1, VLUXSEG3EI16_V }, // 5417 |
| 26688 | { PseudoVLUXSEG3EI16_V_MF2_M1_MASK, VLUXSEG3EI16_V }, // 5418 |
| 26689 | { PseudoVLUXSEG3EI16_V_MF2_M2, VLUXSEG3EI16_V }, // 5419 |
| 26690 | { PseudoVLUXSEG3EI16_V_MF2_M2_MASK, VLUXSEG3EI16_V }, // 5420 |
| 26691 | { PseudoVLUXSEG3EI16_V_MF2_MF2, VLUXSEG3EI16_V }, // 5421 |
| 26692 | { PseudoVLUXSEG3EI16_V_MF2_MF2_MASK, VLUXSEG3EI16_V }, // 5422 |
| 26693 | { PseudoVLUXSEG3EI16_V_MF2_MF4, VLUXSEG3EI16_V }, // 5423 |
| 26694 | { PseudoVLUXSEG3EI16_V_MF2_MF4_MASK, VLUXSEG3EI16_V }, // 5424 |
| 26695 | { PseudoVLUXSEG3EI16_V_MF4_M1, VLUXSEG3EI16_V }, // 5425 |
| 26696 | { PseudoVLUXSEG3EI16_V_MF4_M1_MASK, VLUXSEG3EI16_V }, // 5426 |
| 26697 | { PseudoVLUXSEG3EI16_V_MF4_MF2, VLUXSEG3EI16_V }, // 5427 |
| 26698 | { PseudoVLUXSEG3EI16_V_MF4_MF2_MASK, VLUXSEG3EI16_V }, // 5428 |
| 26699 | { PseudoVLUXSEG3EI16_V_MF4_MF4, VLUXSEG3EI16_V }, // 5429 |
| 26700 | { PseudoVLUXSEG3EI16_V_MF4_MF4_MASK, VLUXSEG3EI16_V }, // 5430 |
| 26701 | { PseudoVLUXSEG3EI16_V_MF4_MF8, VLUXSEG3EI16_V }, // 5431 |
| 26702 | { PseudoVLUXSEG3EI16_V_MF4_MF8_MASK, VLUXSEG3EI16_V }, // 5432 |
| 26703 | { PseudoVLUXSEG3EI32_V_M1_M1, VLUXSEG3EI32_V }, // 5433 |
| 26704 | { PseudoVLUXSEG3EI32_V_M1_M1_MASK, VLUXSEG3EI32_V }, // 5434 |
| 26705 | { PseudoVLUXSEG3EI32_V_M1_M2, VLUXSEG3EI32_V }, // 5435 |
| 26706 | { PseudoVLUXSEG3EI32_V_M1_M2_MASK, VLUXSEG3EI32_V }, // 5436 |
| 26707 | { PseudoVLUXSEG3EI32_V_M1_MF2, VLUXSEG3EI32_V }, // 5437 |
| 26708 | { PseudoVLUXSEG3EI32_V_M1_MF2_MASK, VLUXSEG3EI32_V }, // 5438 |
| 26709 | { PseudoVLUXSEG3EI32_V_M1_MF4, VLUXSEG3EI32_V }, // 5439 |
| 26710 | { PseudoVLUXSEG3EI32_V_M1_MF4_MASK, VLUXSEG3EI32_V }, // 5440 |
| 26711 | { PseudoVLUXSEG3EI32_V_M2_M1, VLUXSEG3EI32_V }, // 5441 |
| 26712 | { PseudoVLUXSEG3EI32_V_M2_M1_MASK, VLUXSEG3EI32_V }, // 5442 |
| 26713 | { PseudoVLUXSEG3EI32_V_M2_M2, VLUXSEG3EI32_V }, // 5443 |
| 26714 | { PseudoVLUXSEG3EI32_V_M2_M2_MASK, VLUXSEG3EI32_V }, // 5444 |
| 26715 | { PseudoVLUXSEG3EI32_V_M2_MF2, VLUXSEG3EI32_V }, // 5445 |
| 26716 | { PseudoVLUXSEG3EI32_V_M2_MF2_MASK, VLUXSEG3EI32_V }, // 5446 |
| 26717 | { PseudoVLUXSEG3EI32_V_M4_M1, VLUXSEG3EI32_V }, // 5447 |
| 26718 | { PseudoVLUXSEG3EI32_V_M4_M1_MASK, VLUXSEG3EI32_V }, // 5448 |
| 26719 | { PseudoVLUXSEG3EI32_V_M4_M2, VLUXSEG3EI32_V }, // 5449 |
| 26720 | { PseudoVLUXSEG3EI32_V_M4_M2_MASK, VLUXSEG3EI32_V }, // 5450 |
| 26721 | { PseudoVLUXSEG3EI32_V_M8_M2, VLUXSEG3EI32_V }, // 5451 |
| 26722 | { PseudoVLUXSEG3EI32_V_M8_M2_MASK, VLUXSEG3EI32_V }, // 5452 |
| 26723 | { PseudoVLUXSEG3EI32_V_MF2_M1, VLUXSEG3EI32_V }, // 5453 |
| 26724 | { PseudoVLUXSEG3EI32_V_MF2_M1_MASK, VLUXSEG3EI32_V }, // 5454 |
| 26725 | { PseudoVLUXSEG3EI32_V_MF2_MF2, VLUXSEG3EI32_V }, // 5455 |
| 26726 | { PseudoVLUXSEG3EI32_V_MF2_MF2_MASK, VLUXSEG3EI32_V }, // 5456 |
| 26727 | { PseudoVLUXSEG3EI32_V_MF2_MF4, VLUXSEG3EI32_V }, // 5457 |
| 26728 | { PseudoVLUXSEG3EI32_V_MF2_MF4_MASK, VLUXSEG3EI32_V }, // 5458 |
| 26729 | { PseudoVLUXSEG3EI32_V_MF2_MF8, VLUXSEG3EI32_V }, // 5459 |
| 26730 | { PseudoVLUXSEG3EI32_V_MF2_MF8_MASK, VLUXSEG3EI32_V }, // 5460 |
| 26731 | { PseudoVLUXSEG3EI64_V_M1_M1, VLUXSEG3EI64_V }, // 5461 |
| 26732 | { PseudoVLUXSEG3EI64_V_M1_M1_MASK, VLUXSEG3EI64_V }, // 5462 |
| 26733 | { PseudoVLUXSEG3EI64_V_M1_MF2, VLUXSEG3EI64_V }, // 5463 |
| 26734 | { PseudoVLUXSEG3EI64_V_M1_MF2_MASK, VLUXSEG3EI64_V }, // 5464 |
| 26735 | { PseudoVLUXSEG3EI64_V_M1_MF4, VLUXSEG3EI64_V }, // 5465 |
| 26736 | { PseudoVLUXSEG3EI64_V_M1_MF4_MASK, VLUXSEG3EI64_V }, // 5466 |
| 26737 | { PseudoVLUXSEG3EI64_V_M1_MF8, VLUXSEG3EI64_V }, // 5467 |
| 26738 | { PseudoVLUXSEG3EI64_V_M1_MF8_MASK, VLUXSEG3EI64_V }, // 5468 |
| 26739 | { PseudoVLUXSEG3EI64_V_M2_M1, VLUXSEG3EI64_V }, // 5469 |
| 26740 | { PseudoVLUXSEG3EI64_V_M2_M1_MASK, VLUXSEG3EI64_V }, // 5470 |
| 26741 | { PseudoVLUXSEG3EI64_V_M2_M2, VLUXSEG3EI64_V }, // 5471 |
| 26742 | { PseudoVLUXSEG3EI64_V_M2_M2_MASK, VLUXSEG3EI64_V }, // 5472 |
| 26743 | { PseudoVLUXSEG3EI64_V_M2_MF2, VLUXSEG3EI64_V }, // 5473 |
| 26744 | { PseudoVLUXSEG3EI64_V_M2_MF2_MASK, VLUXSEG3EI64_V }, // 5474 |
| 26745 | { PseudoVLUXSEG3EI64_V_M2_MF4, VLUXSEG3EI64_V }, // 5475 |
| 26746 | { PseudoVLUXSEG3EI64_V_M2_MF4_MASK, VLUXSEG3EI64_V }, // 5476 |
| 26747 | { PseudoVLUXSEG3EI64_V_M4_M1, VLUXSEG3EI64_V }, // 5477 |
| 26748 | { PseudoVLUXSEG3EI64_V_M4_M1_MASK, VLUXSEG3EI64_V }, // 5478 |
| 26749 | { PseudoVLUXSEG3EI64_V_M4_M2, VLUXSEG3EI64_V }, // 5479 |
| 26750 | { PseudoVLUXSEG3EI64_V_M4_M2_MASK, VLUXSEG3EI64_V }, // 5480 |
| 26751 | { PseudoVLUXSEG3EI64_V_M4_MF2, VLUXSEG3EI64_V }, // 5481 |
| 26752 | { PseudoVLUXSEG3EI64_V_M4_MF2_MASK, VLUXSEG3EI64_V }, // 5482 |
| 26753 | { PseudoVLUXSEG3EI64_V_M8_M1, VLUXSEG3EI64_V }, // 5483 |
| 26754 | { PseudoVLUXSEG3EI64_V_M8_M1_MASK, VLUXSEG3EI64_V }, // 5484 |
| 26755 | { PseudoVLUXSEG3EI64_V_M8_M2, VLUXSEG3EI64_V }, // 5485 |
| 26756 | { PseudoVLUXSEG3EI64_V_M8_M2_MASK, VLUXSEG3EI64_V }, // 5486 |
| 26757 | { PseudoVLUXSEG3EI8_V_M1_M1, VLUXSEG3EI8_V }, // 5487 |
| 26758 | { PseudoVLUXSEG3EI8_V_M1_M1_MASK, VLUXSEG3EI8_V }, // 5488 |
| 26759 | { PseudoVLUXSEG3EI8_V_M1_M2, VLUXSEG3EI8_V }, // 5489 |
| 26760 | { PseudoVLUXSEG3EI8_V_M1_M2_MASK, VLUXSEG3EI8_V }, // 5490 |
| 26761 | { PseudoVLUXSEG3EI8_V_M2_M2, VLUXSEG3EI8_V }, // 5491 |
| 26762 | { PseudoVLUXSEG3EI8_V_M2_M2_MASK, VLUXSEG3EI8_V }, // 5492 |
| 26763 | { PseudoVLUXSEG3EI8_V_MF2_M1, VLUXSEG3EI8_V }, // 5493 |
| 26764 | { PseudoVLUXSEG3EI8_V_MF2_M1_MASK, VLUXSEG3EI8_V }, // 5494 |
| 26765 | { PseudoVLUXSEG3EI8_V_MF2_M2, VLUXSEG3EI8_V }, // 5495 |
| 26766 | { PseudoVLUXSEG3EI8_V_MF2_M2_MASK, VLUXSEG3EI8_V }, // 5496 |
| 26767 | { PseudoVLUXSEG3EI8_V_MF2_MF2, VLUXSEG3EI8_V }, // 5497 |
| 26768 | { PseudoVLUXSEG3EI8_V_MF2_MF2_MASK, VLUXSEG3EI8_V }, // 5498 |
| 26769 | { PseudoVLUXSEG3EI8_V_MF4_M1, VLUXSEG3EI8_V }, // 5499 |
| 26770 | { PseudoVLUXSEG3EI8_V_MF4_M1_MASK, VLUXSEG3EI8_V }, // 5500 |
| 26771 | { PseudoVLUXSEG3EI8_V_MF4_M2, VLUXSEG3EI8_V }, // 5501 |
| 26772 | { PseudoVLUXSEG3EI8_V_MF4_M2_MASK, VLUXSEG3EI8_V }, // 5502 |
| 26773 | { PseudoVLUXSEG3EI8_V_MF4_MF2, VLUXSEG3EI8_V }, // 5503 |
| 26774 | { PseudoVLUXSEG3EI8_V_MF4_MF2_MASK, VLUXSEG3EI8_V }, // 5504 |
| 26775 | { PseudoVLUXSEG3EI8_V_MF4_MF4, VLUXSEG3EI8_V }, // 5505 |
| 26776 | { PseudoVLUXSEG3EI8_V_MF4_MF4_MASK, VLUXSEG3EI8_V }, // 5506 |
| 26777 | { PseudoVLUXSEG3EI8_V_MF8_M1, VLUXSEG3EI8_V }, // 5507 |
| 26778 | { PseudoVLUXSEG3EI8_V_MF8_M1_MASK, VLUXSEG3EI8_V }, // 5508 |
| 26779 | { PseudoVLUXSEG3EI8_V_MF8_MF2, VLUXSEG3EI8_V }, // 5509 |
| 26780 | { PseudoVLUXSEG3EI8_V_MF8_MF2_MASK, VLUXSEG3EI8_V }, // 5510 |
| 26781 | { PseudoVLUXSEG3EI8_V_MF8_MF4, VLUXSEG3EI8_V }, // 5511 |
| 26782 | { PseudoVLUXSEG3EI8_V_MF8_MF4_MASK, VLUXSEG3EI8_V }, // 5512 |
| 26783 | { PseudoVLUXSEG3EI8_V_MF8_MF8, VLUXSEG3EI8_V }, // 5513 |
| 26784 | { PseudoVLUXSEG3EI8_V_MF8_MF8_MASK, VLUXSEG3EI8_V }, // 5514 |
| 26785 | { PseudoVLUXSEG4EI16_V_M1_M1, VLUXSEG4EI16_V }, // 5515 |
| 26786 | { PseudoVLUXSEG4EI16_V_M1_M1_MASK, VLUXSEG4EI16_V }, // 5516 |
| 26787 | { PseudoVLUXSEG4EI16_V_M1_M2, VLUXSEG4EI16_V }, // 5517 |
| 26788 | { PseudoVLUXSEG4EI16_V_M1_M2_MASK, VLUXSEG4EI16_V }, // 5518 |
| 26789 | { PseudoVLUXSEG4EI16_V_M1_MF2, VLUXSEG4EI16_V }, // 5519 |
| 26790 | { PseudoVLUXSEG4EI16_V_M1_MF2_MASK, VLUXSEG4EI16_V }, // 5520 |
| 26791 | { PseudoVLUXSEG4EI16_V_M2_M1, VLUXSEG4EI16_V }, // 5521 |
| 26792 | { PseudoVLUXSEG4EI16_V_M2_M1_MASK, VLUXSEG4EI16_V }, // 5522 |
| 26793 | { PseudoVLUXSEG4EI16_V_M2_M2, VLUXSEG4EI16_V }, // 5523 |
| 26794 | { PseudoVLUXSEG4EI16_V_M2_M2_MASK, VLUXSEG4EI16_V }, // 5524 |
| 26795 | { PseudoVLUXSEG4EI16_V_M4_M2, VLUXSEG4EI16_V }, // 5525 |
| 26796 | { PseudoVLUXSEG4EI16_V_M4_M2_MASK, VLUXSEG4EI16_V }, // 5526 |
| 26797 | { PseudoVLUXSEG4EI16_V_MF2_M1, VLUXSEG4EI16_V }, // 5527 |
| 26798 | { PseudoVLUXSEG4EI16_V_MF2_M1_MASK, VLUXSEG4EI16_V }, // 5528 |
| 26799 | { PseudoVLUXSEG4EI16_V_MF2_M2, VLUXSEG4EI16_V }, // 5529 |
| 26800 | { PseudoVLUXSEG4EI16_V_MF2_M2_MASK, VLUXSEG4EI16_V }, // 5530 |
| 26801 | { PseudoVLUXSEG4EI16_V_MF2_MF2, VLUXSEG4EI16_V }, // 5531 |
| 26802 | { PseudoVLUXSEG4EI16_V_MF2_MF2_MASK, VLUXSEG4EI16_V }, // 5532 |
| 26803 | { PseudoVLUXSEG4EI16_V_MF2_MF4, VLUXSEG4EI16_V }, // 5533 |
| 26804 | { PseudoVLUXSEG4EI16_V_MF2_MF4_MASK, VLUXSEG4EI16_V }, // 5534 |
| 26805 | { PseudoVLUXSEG4EI16_V_MF4_M1, VLUXSEG4EI16_V }, // 5535 |
| 26806 | { PseudoVLUXSEG4EI16_V_MF4_M1_MASK, VLUXSEG4EI16_V }, // 5536 |
| 26807 | { PseudoVLUXSEG4EI16_V_MF4_MF2, VLUXSEG4EI16_V }, // 5537 |
| 26808 | { PseudoVLUXSEG4EI16_V_MF4_MF2_MASK, VLUXSEG4EI16_V }, // 5538 |
| 26809 | { PseudoVLUXSEG4EI16_V_MF4_MF4, VLUXSEG4EI16_V }, // 5539 |
| 26810 | { PseudoVLUXSEG4EI16_V_MF4_MF4_MASK, VLUXSEG4EI16_V }, // 5540 |
| 26811 | { PseudoVLUXSEG4EI16_V_MF4_MF8, VLUXSEG4EI16_V }, // 5541 |
| 26812 | { PseudoVLUXSEG4EI16_V_MF4_MF8_MASK, VLUXSEG4EI16_V }, // 5542 |
| 26813 | { PseudoVLUXSEG4EI32_V_M1_M1, VLUXSEG4EI32_V }, // 5543 |
| 26814 | { PseudoVLUXSEG4EI32_V_M1_M1_MASK, VLUXSEG4EI32_V }, // 5544 |
| 26815 | { PseudoVLUXSEG4EI32_V_M1_M2, VLUXSEG4EI32_V }, // 5545 |
| 26816 | { PseudoVLUXSEG4EI32_V_M1_M2_MASK, VLUXSEG4EI32_V }, // 5546 |
| 26817 | { PseudoVLUXSEG4EI32_V_M1_MF2, VLUXSEG4EI32_V }, // 5547 |
| 26818 | { PseudoVLUXSEG4EI32_V_M1_MF2_MASK, VLUXSEG4EI32_V }, // 5548 |
| 26819 | { PseudoVLUXSEG4EI32_V_M1_MF4, VLUXSEG4EI32_V }, // 5549 |
| 26820 | { PseudoVLUXSEG4EI32_V_M1_MF4_MASK, VLUXSEG4EI32_V }, // 5550 |
| 26821 | { PseudoVLUXSEG4EI32_V_M2_M1, VLUXSEG4EI32_V }, // 5551 |
| 26822 | { PseudoVLUXSEG4EI32_V_M2_M1_MASK, VLUXSEG4EI32_V }, // 5552 |
| 26823 | { PseudoVLUXSEG4EI32_V_M2_M2, VLUXSEG4EI32_V }, // 5553 |
| 26824 | { PseudoVLUXSEG4EI32_V_M2_M2_MASK, VLUXSEG4EI32_V }, // 5554 |
| 26825 | { PseudoVLUXSEG4EI32_V_M2_MF2, VLUXSEG4EI32_V }, // 5555 |
| 26826 | { PseudoVLUXSEG4EI32_V_M2_MF2_MASK, VLUXSEG4EI32_V }, // 5556 |
| 26827 | { PseudoVLUXSEG4EI32_V_M4_M1, VLUXSEG4EI32_V }, // 5557 |
| 26828 | { PseudoVLUXSEG4EI32_V_M4_M1_MASK, VLUXSEG4EI32_V }, // 5558 |
| 26829 | { PseudoVLUXSEG4EI32_V_M4_M2, VLUXSEG4EI32_V }, // 5559 |
| 26830 | { PseudoVLUXSEG4EI32_V_M4_M2_MASK, VLUXSEG4EI32_V }, // 5560 |
| 26831 | { PseudoVLUXSEG4EI32_V_M8_M2, VLUXSEG4EI32_V }, // 5561 |
| 26832 | { PseudoVLUXSEG4EI32_V_M8_M2_MASK, VLUXSEG4EI32_V }, // 5562 |
| 26833 | { PseudoVLUXSEG4EI32_V_MF2_M1, VLUXSEG4EI32_V }, // 5563 |
| 26834 | { PseudoVLUXSEG4EI32_V_MF2_M1_MASK, VLUXSEG4EI32_V }, // 5564 |
| 26835 | { PseudoVLUXSEG4EI32_V_MF2_MF2, VLUXSEG4EI32_V }, // 5565 |
| 26836 | { PseudoVLUXSEG4EI32_V_MF2_MF2_MASK, VLUXSEG4EI32_V }, // 5566 |
| 26837 | { PseudoVLUXSEG4EI32_V_MF2_MF4, VLUXSEG4EI32_V }, // 5567 |
| 26838 | { PseudoVLUXSEG4EI32_V_MF2_MF4_MASK, VLUXSEG4EI32_V }, // 5568 |
| 26839 | { PseudoVLUXSEG4EI32_V_MF2_MF8, VLUXSEG4EI32_V }, // 5569 |
| 26840 | { PseudoVLUXSEG4EI32_V_MF2_MF8_MASK, VLUXSEG4EI32_V }, // 5570 |
| 26841 | { PseudoVLUXSEG4EI64_V_M1_M1, VLUXSEG4EI64_V }, // 5571 |
| 26842 | { PseudoVLUXSEG4EI64_V_M1_M1_MASK, VLUXSEG4EI64_V }, // 5572 |
| 26843 | { PseudoVLUXSEG4EI64_V_M1_MF2, VLUXSEG4EI64_V }, // 5573 |
| 26844 | { PseudoVLUXSEG4EI64_V_M1_MF2_MASK, VLUXSEG4EI64_V }, // 5574 |
| 26845 | { PseudoVLUXSEG4EI64_V_M1_MF4, VLUXSEG4EI64_V }, // 5575 |
| 26846 | { PseudoVLUXSEG4EI64_V_M1_MF4_MASK, VLUXSEG4EI64_V }, // 5576 |
| 26847 | { PseudoVLUXSEG4EI64_V_M1_MF8, VLUXSEG4EI64_V }, // 5577 |
| 26848 | { PseudoVLUXSEG4EI64_V_M1_MF8_MASK, VLUXSEG4EI64_V }, // 5578 |
| 26849 | { PseudoVLUXSEG4EI64_V_M2_M1, VLUXSEG4EI64_V }, // 5579 |
| 26850 | { PseudoVLUXSEG4EI64_V_M2_M1_MASK, VLUXSEG4EI64_V }, // 5580 |
| 26851 | { PseudoVLUXSEG4EI64_V_M2_M2, VLUXSEG4EI64_V }, // 5581 |
| 26852 | { PseudoVLUXSEG4EI64_V_M2_M2_MASK, VLUXSEG4EI64_V }, // 5582 |
| 26853 | { PseudoVLUXSEG4EI64_V_M2_MF2, VLUXSEG4EI64_V }, // 5583 |
| 26854 | { PseudoVLUXSEG4EI64_V_M2_MF2_MASK, VLUXSEG4EI64_V }, // 5584 |
| 26855 | { PseudoVLUXSEG4EI64_V_M2_MF4, VLUXSEG4EI64_V }, // 5585 |
| 26856 | { PseudoVLUXSEG4EI64_V_M2_MF4_MASK, VLUXSEG4EI64_V }, // 5586 |
| 26857 | { PseudoVLUXSEG4EI64_V_M4_M1, VLUXSEG4EI64_V }, // 5587 |
| 26858 | { PseudoVLUXSEG4EI64_V_M4_M1_MASK, VLUXSEG4EI64_V }, // 5588 |
| 26859 | { PseudoVLUXSEG4EI64_V_M4_M2, VLUXSEG4EI64_V }, // 5589 |
| 26860 | { PseudoVLUXSEG4EI64_V_M4_M2_MASK, VLUXSEG4EI64_V }, // 5590 |
| 26861 | { PseudoVLUXSEG4EI64_V_M4_MF2, VLUXSEG4EI64_V }, // 5591 |
| 26862 | { PseudoVLUXSEG4EI64_V_M4_MF2_MASK, VLUXSEG4EI64_V }, // 5592 |
| 26863 | { PseudoVLUXSEG4EI64_V_M8_M1, VLUXSEG4EI64_V }, // 5593 |
| 26864 | { PseudoVLUXSEG4EI64_V_M8_M1_MASK, VLUXSEG4EI64_V }, // 5594 |
| 26865 | { PseudoVLUXSEG4EI64_V_M8_M2, VLUXSEG4EI64_V }, // 5595 |
| 26866 | { PseudoVLUXSEG4EI64_V_M8_M2_MASK, VLUXSEG4EI64_V }, // 5596 |
| 26867 | { PseudoVLUXSEG4EI8_V_M1_M1, VLUXSEG4EI8_V }, // 5597 |
| 26868 | { PseudoVLUXSEG4EI8_V_M1_M1_MASK, VLUXSEG4EI8_V }, // 5598 |
| 26869 | { PseudoVLUXSEG4EI8_V_M1_M2, VLUXSEG4EI8_V }, // 5599 |
| 26870 | { PseudoVLUXSEG4EI8_V_M1_M2_MASK, VLUXSEG4EI8_V }, // 5600 |
| 26871 | { PseudoVLUXSEG4EI8_V_M2_M2, VLUXSEG4EI8_V }, // 5601 |
| 26872 | { PseudoVLUXSEG4EI8_V_M2_M2_MASK, VLUXSEG4EI8_V }, // 5602 |
| 26873 | { PseudoVLUXSEG4EI8_V_MF2_M1, VLUXSEG4EI8_V }, // 5603 |
| 26874 | { PseudoVLUXSEG4EI8_V_MF2_M1_MASK, VLUXSEG4EI8_V }, // 5604 |
| 26875 | { PseudoVLUXSEG4EI8_V_MF2_M2, VLUXSEG4EI8_V }, // 5605 |
| 26876 | { PseudoVLUXSEG4EI8_V_MF2_M2_MASK, VLUXSEG4EI8_V }, // 5606 |
| 26877 | { PseudoVLUXSEG4EI8_V_MF2_MF2, VLUXSEG4EI8_V }, // 5607 |
| 26878 | { PseudoVLUXSEG4EI8_V_MF2_MF2_MASK, VLUXSEG4EI8_V }, // 5608 |
| 26879 | { PseudoVLUXSEG4EI8_V_MF4_M1, VLUXSEG4EI8_V }, // 5609 |
| 26880 | { PseudoVLUXSEG4EI8_V_MF4_M1_MASK, VLUXSEG4EI8_V }, // 5610 |
| 26881 | { PseudoVLUXSEG4EI8_V_MF4_M2, VLUXSEG4EI8_V }, // 5611 |
| 26882 | { PseudoVLUXSEG4EI8_V_MF4_M2_MASK, VLUXSEG4EI8_V }, // 5612 |
| 26883 | { PseudoVLUXSEG4EI8_V_MF4_MF2, VLUXSEG4EI8_V }, // 5613 |
| 26884 | { PseudoVLUXSEG4EI8_V_MF4_MF2_MASK, VLUXSEG4EI8_V }, // 5614 |
| 26885 | { PseudoVLUXSEG4EI8_V_MF4_MF4, VLUXSEG4EI8_V }, // 5615 |
| 26886 | { PseudoVLUXSEG4EI8_V_MF4_MF4_MASK, VLUXSEG4EI8_V }, // 5616 |
| 26887 | { PseudoVLUXSEG4EI8_V_MF8_M1, VLUXSEG4EI8_V }, // 5617 |
| 26888 | { PseudoVLUXSEG4EI8_V_MF8_M1_MASK, VLUXSEG4EI8_V }, // 5618 |
| 26889 | { PseudoVLUXSEG4EI8_V_MF8_MF2, VLUXSEG4EI8_V }, // 5619 |
| 26890 | { PseudoVLUXSEG4EI8_V_MF8_MF2_MASK, VLUXSEG4EI8_V }, // 5620 |
| 26891 | { PseudoVLUXSEG4EI8_V_MF8_MF4, VLUXSEG4EI8_V }, // 5621 |
| 26892 | { PseudoVLUXSEG4EI8_V_MF8_MF4_MASK, VLUXSEG4EI8_V }, // 5622 |
| 26893 | { PseudoVLUXSEG4EI8_V_MF8_MF8, VLUXSEG4EI8_V }, // 5623 |
| 26894 | { PseudoVLUXSEG4EI8_V_MF8_MF8_MASK, VLUXSEG4EI8_V }, // 5624 |
| 26895 | { PseudoVLUXSEG5EI16_V_M1_M1, VLUXSEG5EI16_V }, // 5625 |
| 26896 | { PseudoVLUXSEG5EI16_V_M1_M1_MASK, VLUXSEG5EI16_V }, // 5626 |
| 26897 | { PseudoVLUXSEG5EI16_V_M1_MF2, VLUXSEG5EI16_V }, // 5627 |
| 26898 | { PseudoVLUXSEG5EI16_V_M1_MF2_MASK, VLUXSEG5EI16_V }, // 5628 |
| 26899 | { PseudoVLUXSEG5EI16_V_M2_M1, VLUXSEG5EI16_V }, // 5629 |
| 26900 | { PseudoVLUXSEG5EI16_V_M2_M1_MASK, VLUXSEG5EI16_V }, // 5630 |
| 26901 | { PseudoVLUXSEG5EI16_V_MF2_M1, VLUXSEG5EI16_V }, // 5631 |
| 26902 | { PseudoVLUXSEG5EI16_V_MF2_M1_MASK, VLUXSEG5EI16_V }, // 5632 |
| 26903 | { PseudoVLUXSEG5EI16_V_MF2_MF2, VLUXSEG5EI16_V }, // 5633 |
| 26904 | { PseudoVLUXSEG5EI16_V_MF2_MF2_MASK, VLUXSEG5EI16_V }, // 5634 |
| 26905 | { PseudoVLUXSEG5EI16_V_MF2_MF4, VLUXSEG5EI16_V }, // 5635 |
| 26906 | { PseudoVLUXSEG5EI16_V_MF2_MF4_MASK, VLUXSEG5EI16_V }, // 5636 |
| 26907 | { PseudoVLUXSEG5EI16_V_MF4_M1, VLUXSEG5EI16_V }, // 5637 |
| 26908 | { PseudoVLUXSEG5EI16_V_MF4_M1_MASK, VLUXSEG5EI16_V }, // 5638 |
| 26909 | { PseudoVLUXSEG5EI16_V_MF4_MF2, VLUXSEG5EI16_V }, // 5639 |
| 26910 | { PseudoVLUXSEG5EI16_V_MF4_MF2_MASK, VLUXSEG5EI16_V }, // 5640 |
| 26911 | { PseudoVLUXSEG5EI16_V_MF4_MF4, VLUXSEG5EI16_V }, // 5641 |
| 26912 | { PseudoVLUXSEG5EI16_V_MF4_MF4_MASK, VLUXSEG5EI16_V }, // 5642 |
| 26913 | { PseudoVLUXSEG5EI16_V_MF4_MF8, VLUXSEG5EI16_V }, // 5643 |
| 26914 | { PseudoVLUXSEG5EI16_V_MF4_MF8_MASK, VLUXSEG5EI16_V }, // 5644 |
| 26915 | { PseudoVLUXSEG5EI32_V_M1_M1, VLUXSEG5EI32_V }, // 5645 |
| 26916 | { PseudoVLUXSEG5EI32_V_M1_M1_MASK, VLUXSEG5EI32_V }, // 5646 |
| 26917 | { PseudoVLUXSEG5EI32_V_M1_MF2, VLUXSEG5EI32_V }, // 5647 |
| 26918 | { PseudoVLUXSEG5EI32_V_M1_MF2_MASK, VLUXSEG5EI32_V }, // 5648 |
| 26919 | { PseudoVLUXSEG5EI32_V_M1_MF4, VLUXSEG5EI32_V }, // 5649 |
| 26920 | { PseudoVLUXSEG5EI32_V_M1_MF4_MASK, VLUXSEG5EI32_V }, // 5650 |
| 26921 | { PseudoVLUXSEG5EI32_V_M2_M1, VLUXSEG5EI32_V }, // 5651 |
| 26922 | { PseudoVLUXSEG5EI32_V_M2_M1_MASK, VLUXSEG5EI32_V }, // 5652 |
| 26923 | { PseudoVLUXSEG5EI32_V_M2_MF2, VLUXSEG5EI32_V }, // 5653 |
| 26924 | { PseudoVLUXSEG5EI32_V_M2_MF2_MASK, VLUXSEG5EI32_V }, // 5654 |
| 26925 | { PseudoVLUXSEG5EI32_V_M4_M1, VLUXSEG5EI32_V }, // 5655 |
| 26926 | { PseudoVLUXSEG5EI32_V_M4_M1_MASK, VLUXSEG5EI32_V }, // 5656 |
| 26927 | { PseudoVLUXSEG5EI32_V_MF2_M1, VLUXSEG5EI32_V }, // 5657 |
| 26928 | { PseudoVLUXSEG5EI32_V_MF2_M1_MASK, VLUXSEG5EI32_V }, // 5658 |
| 26929 | { PseudoVLUXSEG5EI32_V_MF2_MF2, VLUXSEG5EI32_V }, // 5659 |
| 26930 | { PseudoVLUXSEG5EI32_V_MF2_MF2_MASK, VLUXSEG5EI32_V }, // 5660 |
| 26931 | { PseudoVLUXSEG5EI32_V_MF2_MF4, VLUXSEG5EI32_V }, // 5661 |
| 26932 | { PseudoVLUXSEG5EI32_V_MF2_MF4_MASK, VLUXSEG5EI32_V }, // 5662 |
| 26933 | { PseudoVLUXSEG5EI32_V_MF2_MF8, VLUXSEG5EI32_V }, // 5663 |
| 26934 | { PseudoVLUXSEG5EI32_V_MF2_MF8_MASK, VLUXSEG5EI32_V }, // 5664 |
| 26935 | { PseudoVLUXSEG5EI64_V_M1_M1, VLUXSEG5EI64_V }, // 5665 |
| 26936 | { PseudoVLUXSEG5EI64_V_M1_M1_MASK, VLUXSEG5EI64_V }, // 5666 |
| 26937 | { PseudoVLUXSEG5EI64_V_M1_MF2, VLUXSEG5EI64_V }, // 5667 |
| 26938 | { PseudoVLUXSEG5EI64_V_M1_MF2_MASK, VLUXSEG5EI64_V }, // 5668 |
| 26939 | { PseudoVLUXSEG5EI64_V_M1_MF4, VLUXSEG5EI64_V }, // 5669 |
| 26940 | { PseudoVLUXSEG5EI64_V_M1_MF4_MASK, VLUXSEG5EI64_V }, // 5670 |
| 26941 | { PseudoVLUXSEG5EI64_V_M1_MF8, VLUXSEG5EI64_V }, // 5671 |
| 26942 | { PseudoVLUXSEG5EI64_V_M1_MF8_MASK, VLUXSEG5EI64_V }, // 5672 |
| 26943 | { PseudoVLUXSEG5EI64_V_M2_M1, VLUXSEG5EI64_V }, // 5673 |
| 26944 | { PseudoVLUXSEG5EI64_V_M2_M1_MASK, VLUXSEG5EI64_V }, // 5674 |
| 26945 | { PseudoVLUXSEG5EI64_V_M2_MF2, VLUXSEG5EI64_V }, // 5675 |
| 26946 | { PseudoVLUXSEG5EI64_V_M2_MF2_MASK, VLUXSEG5EI64_V }, // 5676 |
| 26947 | { PseudoVLUXSEG5EI64_V_M2_MF4, VLUXSEG5EI64_V }, // 5677 |
| 26948 | { PseudoVLUXSEG5EI64_V_M2_MF4_MASK, VLUXSEG5EI64_V }, // 5678 |
| 26949 | { PseudoVLUXSEG5EI64_V_M4_M1, VLUXSEG5EI64_V }, // 5679 |
| 26950 | { PseudoVLUXSEG5EI64_V_M4_M1_MASK, VLUXSEG5EI64_V }, // 5680 |
| 26951 | { PseudoVLUXSEG5EI64_V_M4_MF2, VLUXSEG5EI64_V }, // 5681 |
| 26952 | { PseudoVLUXSEG5EI64_V_M4_MF2_MASK, VLUXSEG5EI64_V }, // 5682 |
| 26953 | { PseudoVLUXSEG5EI64_V_M8_M1, VLUXSEG5EI64_V }, // 5683 |
| 26954 | { PseudoVLUXSEG5EI64_V_M8_M1_MASK, VLUXSEG5EI64_V }, // 5684 |
| 26955 | { PseudoVLUXSEG5EI8_V_M1_M1, VLUXSEG5EI8_V }, // 5685 |
| 26956 | { PseudoVLUXSEG5EI8_V_M1_M1_MASK, VLUXSEG5EI8_V }, // 5686 |
| 26957 | { PseudoVLUXSEG5EI8_V_MF2_M1, VLUXSEG5EI8_V }, // 5687 |
| 26958 | { PseudoVLUXSEG5EI8_V_MF2_M1_MASK, VLUXSEG5EI8_V }, // 5688 |
| 26959 | { PseudoVLUXSEG5EI8_V_MF2_MF2, VLUXSEG5EI8_V }, // 5689 |
| 26960 | { PseudoVLUXSEG5EI8_V_MF2_MF2_MASK, VLUXSEG5EI8_V }, // 5690 |
| 26961 | { PseudoVLUXSEG5EI8_V_MF4_M1, VLUXSEG5EI8_V }, // 5691 |
| 26962 | { PseudoVLUXSEG5EI8_V_MF4_M1_MASK, VLUXSEG5EI8_V }, // 5692 |
| 26963 | { PseudoVLUXSEG5EI8_V_MF4_MF2, VLUXSEG5EI8_V }, // 5693 |
| 26964 | { PseudoVLUXSEG5EI8_V_MF4_MF2_MASK, VLUXSEG5EI8_V }, // 5694 |
| 26965 | { PseudoVLUXSEG5EI8_V_MF4_MF4, VLUXSEG5EI8_V }, // 5695 |
| 26966 | { PseudoVLUXSEG5EI8_V_MF4_MF4_MASK, VLUXSEG5EI8_V }, // 5696 |
| 26967 | { PseudoVLUXSEG5EI8_V_MF8_M1, VLUXSEG5EI8_V }, // 5697 |
| 26968 | { PseudoVLUXSEG5EI8_V_MF8_M1_MASK, VLUXSEG5EI8_V }, // 5698 |
| 26969 | { PseudoVLUXSEG5EI8_V_MF8_MF2, VLUXSEG5EI8_V }, // 5699 |
| 26970 | { PseudoVLUXSEG5EI8_V_MF8_MF2_MASK, VLUXSEG5EI8_V }, // 5700 |
| 26971 | { PseudoVLUXSEG5EI8_V_MF8_MF4, VLUXSEG5EI8_V }, // 5701 |
| 26972 | { PseudoVLUXSEG5EI8_V_MF8_MF4_MASK, VLUXSEG5EI8_V }, // 5702 |
| 26973 | { PseudoVLUXSEG5EI8_V_MF8_MF8, VLUXSEG5EI8_V }, // 5703 |
| 26974 | { PseudoVLUXSEG5EI8_V_MF8_MF8_MASK, VLUXSEG5EI8_V }, // 5704 |
| 26975 | { PseudoVLUXSEG6EI16_V_M1_M1, VLUXSEG6EI16_V }, // 5705 |
| 26976 | { PseudoVLUXSEG6EI16_V_M1_M1_MASK, VLUXSEG6EI16_V }, // 5706 |
| 26977 | { PseudoVLUXSEG6EI16_V_M1_MF2, VLUXSEG6EI16_V }, // 5707 |
| 26978 | { PseudoVLUXSEG6EI16_V_M1_MF2_MASK, VLUXSEG6EI16_V }, // 5708 |
| 26979 | { PseudoVLUXSEG6EI16_V_M2_M1, VLUXSEG6EI16_V }, // 5709 |
| 26980 | { PseudoVLUXSEG6EI16_V_M2_M1_MASK, VLUXSEG6EI16_V }, // 5710 |
| 26981 | { PseudoVLUXSEG6EI16_V_MF2_M1, VLUXSEG6EI16_V }, // 5711 |
| 26982 | { PseudoVLUXSEG6EI16_V_MF2_M1_MASK, VLUXSEG6EI16_V }, // 5712 |
| 26983 | { PseudoVLUXSEG6EI16_V_MF2_MF2, VLUXSEG6EI16_V }, // 5713 |
| 26984 | { PseudoVLUXSEG6EI16_V_MF2_MF2_MASK, VLUXSEG6EI16_V }, // 5714 |
| 26985 | { PseudoVLUXSEG6EI16_V_MF2_MF4, VLUXSEG6EI16_V }, // 5715 |
| 26986 | { PseudoVLUXSEG6EI16_V_MF2_MF4_MASK, VLUXSEG6EI16_V }, // 5716 |
| 26987 | { PseudoVLUXSEG6EI16_V_MF4_M1, VLUXSEG6EI16_V }, // 5717 |
| 26988 | { PseudoVLUXSEG6EI16_V_MF4_M1_MASK, VLUXSEG6EI16_V }, // 5718 |
| 26989 | { PseudoVLUXSEG6EI16_V_MF4_MF2, VLUXSEG6EI16_V }, // 5719 |
| 26990 | { PseudoVLUXSEG6EI16_V_MF4_MF2_MASK, VLUXSEG6EI16_V }, // 5720 |
| 26991 | { PseudoVLUXSEG6EI16_V_MF4_MF4, VLUXSEG6EI16_V }, // 5721 |
| 26992 | { PseudoVLUXSEG6EI16_V_MF4_MF4_MASK, VLUXSEG6EI16_V }, // 5722 |
| 26993 | { PseudoVLUXSEG6EI16_V_MF4_MF8, VLUXSEG6EI16_V }, // 5723 |
| 26994 | { PseudoVLUXSEG6EI16_V_MF4_MF8_MASK, VLUXSEG6EI16_V }, // 5724 |
| 26995 | { PseudoVLUXSEG6EI32_V_M1_M1, VLUXSEG6EI32_V }, // 5725 |
| 26996 | { PseudoVLUXSEG6EI32_V_M1_M1_MASK, VLUXSEG6EI32_V }, // 5726 |
| 26997 | { PseudoVLUXSEG6EI32_V_M1_MF2, VLUXSEG6EI32_V }, // 5727 |
| 26998 | { PseudoVLUXSEG6EI32_V_M1_MF2_MASK, VLUXSEG6EI32_V }, // 5728 |
| 26999 | { PseudoVLUXSEG6EI32_V_M1_MF4, VLUXSEG6EI32_V }, // 5729 |
| 27000 | { PseudoVLUXSEG6EI32_V_M1_MF4_MASK, VLUXSEG6EI32_V }, // 5730 |
| 27001 | { PseudoVLUXSEG6EI32_V_M2_M1, VLUXSEG6EI32_V }, // 5731 |
| 27002 | { PseudoVLUXSEG6EI32_V_M2_M1_MASK, VLUXSEG6EI32_V }, // 5732 |
| 27003 | { PseudoVLUXSEG6EI32_V_M2_MF2, VLUXSEG6EI32_V }, // 5733 |
| 27004 | { PseudoVLUXSEG6EI32_V_M2_MF2_MASK, VLUXSEG6EI32_V }, // 5734 |
| 27005 | { PseudoVLUXSEG6EI32_V_M4_M1, VLUXSEG6EI32_V }, // 5735 |
| 27006 | { PseudoVLUXSEG6EI32_V_M4_M1_MASK, VLUXSEG6EI32_V }, // 5736 |
| 27007 | { PseudoVLUXSEG6EI32_V_MF2_M1, VLUXSEG6EI32_V }, // 5737 |
| 27008 | { PseudoVLUXSEG6EI32_V_MF2_M1_MASK, VLUXSEG6EI32_V }, // 5738 |
| 27009 | { PseudoVLUXSEG6EI32_V_MF2_MF2, VLUXSEG6EI32_V }, // 5739 |
| 27010 | { PseudoVLUXSEG6EI32_V_MF2_MF2_MASK, VLUXSEG6EI32_V }, // 5740 |
| 27011 | { PseudoVLUXSEG6EI32_V_MF2_MF4, VLUXSEG6EI32_V }, // 5741 |
| 27012 | { PseudoVLUXSEG6EI32_V_MF2_MF4_MASK, VLUXSEG6EI32_V }, // 5742 |
| 27013 | { PseudoVLUXSEG6EI32_V_MF2_MF8, VLUXSEG6EI32_V }, // 5743 |
| 27014 | { PseudoVLUXSEG6EI32_V_MF2_MF8_MASK, VLUXSEG6EI32_V }, // 5744 |
| 27015 | { PseudoVLUXSEG6EI64_V_M1_M1, VLUXSEG6EI64_V }, // 5745 |
| 27016 | { PseudoVLUXSEG6EI64_V_M1_M1_MASK, VLUXSEG6EI64_V }, // 5746 |
| 27017 | { PseudoVLUXSEG6EI64_V_M1_MF2, VLUXSEG6EI64_V }, // 5747 |
| 27018 | { PseudoVLUXSEG6EI64_V_M1_MF2_MASK, VLUXSEG6EI64_V }, // 5748 |
| 27019 | { PseudoVLUXSEG6EI64_V_M1_MF4, VLUXSEG6EI64_V }, // 5749 |
| 27020 | { PseudoVLUXSEG6EI64_V_M1_MF4_MASK, VLUXSEG6EI64_V }, // 5750 |
| 27021 | { PseudoVLUXSEG6EI64_V_M1_MF8, VLUXSEG6EI64_V }, // 5751 |
| 27022 | { PseudoVLUXSEG6EI64_V_M1_MF8_MASK, VLUXSEG6EI64_V }, // 5752 |
| 27023 | { PseudoVLUXSEG6EI64_V_M2_M1, VLUXSEG6EI64_V }, // 5753 |
| 27024 | { PseudoVLUXSEG6EI64_V_M2_M1_MASK, VLUXSEG6EI64_V }, // 5754 |
| 27025 | { PseudoVLUXSEG6EI64_V_M2_MF2, VLUXSEG6EI64_V }, // 5755 |
| 27026 | { PseudoVLUXSEG6EI64_V_M2_MF2_MASK, VLUXSEG6EI64_V }, // 5756 |
| 27027 | { PseudoVLUXSEG6EI64_V_M2_MF4, VLUXSEG6EI64_V }, // 5757 |
| 27028 | { PseudoVLUXSEG6EI64_V_M2_MF4_MASK, VLUXSEG6EI64_V }, // 5758 |
| 27029 | { PseudoVLUXSEG6EI64_V_M4_M1, VLUXSEG6EI64_V }, // 5759 |
| 27030 | { PseudoVLUXSEG6EI64_V_M4_M1_MASK, VLUXSEG6EI64_V }, // 5760 |
| 27031 | { PseudoVLUXSEG6EI64_V_M4_MF2, VLUXSEG6EI64_V }, // 5761 |
| 27032 | { PseudoVLUXSEG6EI64_V_M4_MF2_MASK, VLUXSEG6EI64_V }, // 5762 |
| 27033 | { PseudoVLUXSEG6EI64_V_M8_M1, VLUXSEG6EI64_V }, // 5763 |
| 27034 | { PseudoVLUXSEG6EI64_V_M8_M1_MASK, VLUXSEG6EI64_V }, // 5764 |
| 27035 | { PseudoVLUXSEG6EI8_V_M1_M1, VLUXSEG6EI8_V }, // 5765 |
| 27036 | { PseudoVLUXSEG6EI8_V_M1_M1_MASK, VLUXSEG6EI8_V }, // 5766 |
| 27037 | { PseudoVLUXSEG6EI8_V_MF2_M1, VLUXSEG6EI8_V }, // 5767 |
| 27038 | { PseudoVLUXSEG6EI8_V_MF2_M1_MASK, VLUXSEG6EI8_V }, // 5768 |
| 27039 | { PseudoVLUXSEG6EI8_V_MF2_MF2, VLUXSEG6EI8_V }, // 5769 |
| 27040 | { PseudoVLUXSEG6EI8_V_MF2_MF2_MASK, VLUXSEG6EI8_V }, // 5770 |
| 27041 | { PseudoVLUXSEG6EI8_V_MF4_M1, VLUXSEG6EI8_V }, // 5771 |
| 27042 | { PseudoVLUXSEG6EI8_V_MF4_M1_MASK, VLUXSEG6EI8_V }, // 5772 |
| 27043 | { PseudoVLUXSEG6EI8_V_MF4_MF2, VLUXSEG6EI8_V }, // 5773 |
| 27044 | { PseudoVLUXSEG6EI8_V_MF4_MF2_MASK, VLUXSEG6EI8_V }, // 5774 |
| 27045 | { PseudoVLUXSEG6EI8_V_MF4_MF4, VLUXSEG6EI8_V }, // 5775 |
| 27046 | { PseudoVLUXSEG6EI8_V_MF4_MF4_MASK, VLUXSEG6EI8_V }, // 5776 |
| 27047 | { PseudoVLUXSEG6EI8_V_MF8_M1, VLUXSEG6EI8_V }, // 5777 |
| 27048 | { PseudoVLUXSEG6EI8_V_MF8_M1_MASK, VLUXSEG6EI8_V }, // 5778 |
| 27049 | { PseudoVLUXSEG6EI8_V_MF8_MF2, VLUXSEG6EI8_V }, // 5779 |
| 27050 | { PseudoVLUXSEG6EI8_V_MF8_MF2_MASK, VLUXSEG6EI8_V }, // 5780 |
| 27051 | { PseudoVLUXSEG6EI8_V_MF8_MF4, VLUXSEG6EI8_V }, // 5781 |
| 27052 | { PseudoVLUXSEG6EI8_V_MF8_MF4_MASK, VLUXSEG6EI8_V }, // 5782 |
| 27053 | { PseudoVLUXSEG6EI8_V_MF8_MF8, VLUXSEG6EI8_V }, // 5783 |
| 27054 | { PseudoVLUXSEG6EI8_V_MF8_MF8_MASK, VLUXSEG6EI8_V }, // 5784 |
| 27055 | { PseudoVLUXSEG7EI16_V_M1_M1, VLUXSEG7EI16_V }, // 5785 |
| 27056 | { PseudoVLUXSEG7EI16_V_M1_M1_MASK, VLUXSEG7EI16_V }, // 5786 |
| 27057 | { PseudoVLUXSEG7EI16_V_M1_MF2, VLUXSEG7EI16_V }, // 5787 |
| 27058 | { PseudoVLUXSEG7EI16_V_M1_MF2_MASK, VLUXSEG7EI16_V }, // 5788 |
| 27059 | { PseudoVLUXSEG7EI16_V_M2_M1, VLUXSEG7EI16_V }, // 5789 |
| 27060 | { PseudoVLUXSEG7EI16_V_M2_M1_MASK, VLUXSEG7EI16_V }, // 5790 |
| 27061 | { PseudoVLUXSEG7EI16_V_MF2_M1, VLUXSEG7EI16_V }, // 5791 |
| 27062 | { PseudoVLUXSEG7EI16_V_MF2_M1_MASK, VLUXSEG7EI16_V }, // 5792 |
| 27063 | { PseudoVLUXSEG7EI16_V_MF2_MF2, VLUXSEG7EI16_V }, // 5793 |
| 27064 | { PseudoVLUXSEG7EI16_V_MF2_MF2_MASK, VLUXSEG7EI16_V }, // 5794 |
| 27065 | { PseudoVLUXSEG7EI16_V_MF2_MF4, VLUXSEG7EI16_V }, // 5795 |
| 27066 | { PseudoVLUXSEG7EI16_V_MF2_MF4_MASK, VLUXSEG7EI16_V }, // 5796 |
| 27067 | { PseudoVLUXSEG7EI16_V_MF4_M1, VLUXSEG7EI16_V }, // 5797 |
| 27068 | { PseudoVLUXSEG7EI16_V_MF4_M1_MASK, VLUXSEG7EI16_V }, // 5798 |
| 27069 | { PseudoVLUXSEG7EI16_V_MF4_MF2, VLUXSEG7EI16_V }, // 5799 |
| 27070 | { PseudoVLUXSEG7EI16_V_MF4_MF2_MASK, VLUXSEG7EI16_V }, // 5800 |
| 27071 | { PseudoVLUXSEG7EI16_V_MF4_MF4, VLUXSEG7EI16_V }, // 5801 |
| 27072 | { PseudoVLUXSEG7EI16_V_MF4_MF4_MASK, VLUXSEG7EI16_V }, // 5802 |
| 27073 | { PseudoVLUXSEG7EI16_V_MF4_MF8, VLUXSEG7EI16_V }, // 5803 |
| 27074 | { PseudoVLUXSEG7EI16_V_MF4_MF8_MASK, VLUXSEG7EI16_V }, // 5804 |
| 27075 | { PseudoVLUXSEG7EI32_V_M1_M1, VLUXSEG7EI32_V }, // 5805 |
| 27076 | { PseudoVLUXSEG7EI32_V_M1_M1_MASK, VLUXSEG7EI32_V }, // 5806 |
| 27077 | { PseudoVLUXSEG7EI32_V_M1_MF2, VLUXSEG7EI32_V }, // 5807 |
| 27078 | { PseudoVLUXSEG7EI32_V_M1_MF2_MASK, VLUXSEG7EI32_V }, // 5808 |
| 27079 | { PseudoVLUXSEG7EI32_V_M1_MF4, VLUXSEG7EI32_V }, // 5809 |
| 27080 | { PseudoVLUXSEG7EI32_V_M1_MF4_MASK, VLUXSEG7EI32_V }, // 5810 |
| 27081 | { PseudoVLUXSEG7EI32_V_M2_M1, VLUXSEG7EI32_V }, // 5811 |
| 27082 | { PseudoVLUXSEG7EI32_V_M2_M1_MASK, VLUXSEG7EI32_V }, // 5812 |
| 27083 | { PseudoVLUXSEG7EI32_V_M2_MF2, VLUXSEG7EI32_V }, // 5813 |
| 27084 | { PseudoVLUXSEG7EI32_V_M2_MF2_MASK, VLUXSEG7EI32_V }, // 5814 |
| 27085 | { PseudoVLUXSEG7EI32_V_M4_M1, VLUXSEG7EI32_V }, // 5815 |
| 27086 | { PseudoVLUXSEG7EI32_V_M4_M1_MASK, VLUXSEG7EI32_V }, // 5816 |
| 27087 | { PseudoVLUXSEG7EI32_V_MF2_M1, VLUXSEG7EI32_V }, // 5817 |
| 27088 | { PseudoVLUXSEG7EI32_V_MF2_M1_MASK, VLUXSEG7EI32_V }, // 5818 |
| 27089 | { PseudoVLUXSEG7EI32_V_MF2_MF2, VLUXSEG7EI32_V }, // 5819 |
| 27090 | { PseudoVLUXSEG7EI32_V_MF2_MF2_MASK, VLUXSEG7EI32_V }, // 5820 |
| 27091 | { PseudoVLUXSEG7EI32_V_MF2_MF4, VLUXSEG7EI32_V }, // 5821 |
| 27092 | { PseudoVLUXSEG7EI32_V_MF2_MF4_MASK, VLUXSEG7EI32_V }, // 5822 |
| 27093 | { PseudoVLUXSEG7EI32_V_MF2_MF8, VLUXSEG7EI32_V }, // 5823 |
| 27094 | { PseudoVLUXSEG7EI32_V_MF2_MF8_MASK, VLUXSEG7EI32_V }, // 5824 |
| 27095 | { PseudoVLUXSEG7EI64_V_M1_M1, VLUXSEG7EI64_V }, // 5825 |
| 27096 | { PseudoVLUXSEG7EI64_V_M1_M1_MASK, VLUXSEG7EI64_V }, // 5826 |
| 27097 | { PseudoVLUXSEG7EI64_V_M1_MF2, VLUXSEG7EI64_V }, // 5827 |
| 27098 | { PseudoVLUXSEG7EI64_V_M1_MF2_MASK, VLUXSEG7EI64_V }, // 5828 |
| 27099 | { PseudoVLUXSEG7EI64_V_M1_MF4, VLUXSEG7EI64_V }, // 5829 |
| 27100 | { PseudoVLUXSEG7EI64_V_M1_MF4_MASK, VLUXSEG7EI64_V }, // 5830 |
| 27101 | { PseudoVLUXSEG7EI64_V_M1_MF8, VLUXSEG7EI64_V }, // 5831 |
| 27102 | { PseudoVLUXSEG7EI64_V_M1_MF8_MASK, VLUXSEG7EI64_V }, // 5832 |
| 27103 | { PseudoVLUXSEG7EI64_V_M2_M1, VLUXSEG7EI64_V }, // 5833 |
| 27104 | { PseudoVLUXSEG7EI64_V_M2_M1_MASK, VLUXSEG7EI64_V }, // 5834 |
| 27105 | { PseudoVLUXSEG7EI64_V_M2_MF2, VLUXSEG7EI64_V }, // 5835 |
| 27106 | { PseudoVLUXSEG7EI64_V_M2_MF2_MASK, VLUXSEG7EI64_V }, // 5836 |
| 27107 | { PseudoVLUXSEG7EI64_V_M2_MF4, VLUXSEG7EI64_V }, // 5837 |
| 27108 | { PseudoVLUXSEG7EI64_V_M2_MF4_MASK, VLUXSEG7EI64_V }, // 5838 |
| 27109 | { PseudoVLUXSEG7EI64_V_M4_M1, VLUXSEG7EI64_V }, // 5839 |
| 27110 | { PseudoVLUXSEG7EI64_V_M4_M1_MASK, VLUXSEG7EI64_V }, // 5840 |
| 27111 | { PseudoVLUXSEG7EI64_V_M4_MF2, VLUXSEG7EI64_V }, // 5841 |
| 27112 | { PseudoVLUXSEG7EI64_V_M4_MF2_MASK, VLUXSEG7EI64_V }, // 5842 |
| 27113 | { PseudoVLUXSEG7EI64_V_M8_M1, VLUXSEG7EI64_V }, // 5843 |
| 27114 | { PseudoVLUXSEG7EI64_V_M8_M1_MASK, VLUXSEG7EI64_V }, // 5844 |
| 27115 | { PseudoVLUXSEG7EI8_V_M1_M1, VLUXSEG7EI8_V }, // 5845 |
| 27116 | { PseudoVLUXSEG7EI8_V_M1_M1_MASK, VLUXSEG7EI8_V }, // 5846 |
| 27117 | { PseudoVLUXSEG7EI8_V_MF2_M1, VLUXSEG7EI8_V }, // 5847 |
| 27118 | { PseudoVLUXSEG7EI8_V_MF2_M1_MASK, VLUXSEG7EI8_V }, // 5848 |
| 27119 | { PseudoVLUXSEG7EI8_V_MF2_MF2, VLUXSEG7EI8_V }, // 5849 |
| 27120 | { PseudoVLUXSEG7EI8_V_MF2_MF2_MASK, VLUXSEG7EI8_V }, // 5850 |
| 27121 | { PseudoVLUXSEG7EI8_V_MF4_M1, VLUXSEG7EI8_V }, // 5851 |
| 27122 | { PseudoVLUXSEG7EI8_V_MF4_M1_MASK, VLUXSEG7EI8_V }, // 5852 |
| 27123 | { PseudoVLUXSEG7EI8_V_MF4_MF2, VLUXSEG7EI8_V }, // 5853 |
| 27124 | { PseudoVLUXSEG7EI8_V_MF4_MF2_MASK, VLUXSEG7EI8_V }, // 5854 |
| 27125 | { PseudoVLUXSEG7EI8_V_MF4_MF4, VLUXSEG7EI8_V }, // 5855 |
| 27126 | { PseudoVLUXSEG7EI8_V_MF4_MF4_MASK, VLUXSEG7EI8_V }, // 5856 |
| 27127 | { PseudoVLUXSEG7EI8_V_MF8_M1, VLUXSEG7EI8_V }, // 5857 |
| 27128 | { PseudoVLUXSEG7EI8_V_MF8_M1_MASK, VLUXSEG7EI8_V }, // 5858 |
| 27129 | { PseudoVLUXSEG7EI8_V_MF8_MF2, VLUXSEG7EI8_V }, // 5859 |
| 27130 | { PseudoVLUXSEG7EI8_V_MF8_MF2_MASK, VLUXSEG7EI8_V }, // 5860 |
| 27131 | { PseudoVLUXSEG7EI8_V_MF8_MF4, VLUXSEG7EI8_V }, // 5861 |
| 27132 | { PseudoVLUXSEG7EI8_V_MF8_MF4_MASK, VLUXSEG7EI8_V }, // 5862 |
| 27133 | { PseudoVLUXSEG7EI8_V_MF8_MF8, VLUXSEG7EI8_V }, // 5863 |
| 27134 | { PseudoVLUXSEG7EI8_V_MF8_MF8_MASK, VLUXSEG7EI8_V }, // 5864 |
| 27135 | { PseudoVLUXSEG8EI16_V_M1_M1, VLUXSEG8EI16_V }, // 5865 |
| 27136 | { PseudoVLUXSEG8EI16_V_M1_M1_MASK, VLUXSEG8EI16_V }, // 5866 |
| 27137 | { PseudoVLUXSEG8EI16_V_M1_MF2, VLUXSEG8EI16_V }, // 5867 |
| 27138 | { PseudoVLUXSEG8EI16_V_M1_MF2_MASK, VLUXSEG8EI16_V }, // 5868 |
| 27139 | { PseudoVLUXSEG8EI16_V_M2_M1, VLUXSEG8EI16_V }, // 5869 |
| 27140 | { PseudoVLUXSEG8EI16_V_M2_M1_MASK, VLUXSEG8EI16_V }, // 5870 |
| 27141 | { PseudoVLUXSEG8EI16_V_MF2_M1, VLUXSEG8EI16_V }, // 5871 |
| 27142 | { PseudoVLUXSEG8EI16_V_MF2_M1_MASK, VLUXSEG8EI16_V }, // 5872 |
| 27143 | { PseudoVLUXSEG8EI16_V_MF2_MF2, VLUXSEG8EI16_V }, // 5873 |
| 27144 | { PseudoVLUXSEG8EI16_V_MF2_MF2_MASK, VLUXSEG8EI16_V }, // 5874 |
| 27145 | { PseudoVLUXSEG8EI16_V_MF2_MF4, VLUXSEG8EI16_V }, // 5875 |
| 27146 | { PseudoVLUXSEG8EI16_V_MF2_MF4_MASK, VLUXSEG8EI16_V }, // 5876 |
| 27147 | { PseudoVLUXSEG8EI16_V_MF4_M1, VLUXSEG8EI16_V }, // 5877 |
| 27148 | { PseudoVLUXSEG8EI16_V_MF4_M1_MASK, VLUXSEG8EI16_V }, // 5878 |
| 27149 | { PseudoVLUXSEG8EI16_V_MF4_MF2, VLUXSEG8EI16_V }, // 5879 |
| 27150 | { PseudoVLUXSEG8EI16_V_MF4_MF2_MASK, VLUXSEG8EI16_V }, // 5880 |
| 27151 | { PseudoVLUXSEG8EI16_V_MF4_MF4, VLUXSEG8EI16_V }, // 5881 |
| 27152 | { PseudoVLUXSEG8EI16_V_MF4_MF4_MASK, VLUXSEG8EI16_V }, // 5882 |
| 27153 | { PseudoVLUXSEG8EI16_V_MF4_MF8, VLUXSEG8EI16_V }, // 5883 |
| 27154 | { PseudoVLUXSEG8EI16_V_MF4_MF8_MASK, VLUXSEG8EI16_V }, // 5884 |
| 27155 | { PseudoVLUXSEG8EI32_V_M1_M1, VLUXSEG8EI32_V }, // 5885 |
| 27156 | { PseudoVLUXSEG8EI32_V_M1_M1_MASK, VLUXSEG8EI32_V }, // 5886 |
| 27157 | { PseudoVLUXSEG8EI32_V_M1_MF2, VLUXSEG8EI32_V }, // 5887 |
| 27158 | { PseudoVLUXSEG8EI32_V_M1_MF2_MASK, VLUXSEG8EI32_V }, // 5888 |
| 27159 | { PseudoVLUXSEG8EI32_V_M1_MF4, VLUXSEG8EI32_V }, // 5889 |
| 27160 | { PseudoVLUXSEG8EI32_V_M1_MF4_MASK, VLUXSEG8EI32_V }, // 5890 |
| 27161 | { PseudoVLUXSEG8EI32_V_M2_M1, VLUXSEG8EI32_V }, // 5891 |
| 27162 | { PseudoVLUXSEG8EI32_V_M2_M1_MASK, VLUXSEG8EI32_V }, // 5892 |
| 27163 | { PseudoVLUXSEG8EI32_V_M2_MF2, VLUXSEG8EI32_V }, // 5893 |
| 27164 | { PseudoVLUXSEG8EI32_V_M2_MF2_MASK, VLUXSEG8EI32_V }, // 5894 |
| 27165 | { PseudoVLUXSEG8EI32_V_M4_M1, VLUXSEG8EI32_V }, // 5895 |
| 27166 | { PseudoVLUXSEG8EI32_V_M4_M1_MASK, VLUXSEG8EI32_V }, // 5896 |
| 27167 | { PseudoVLUXSEG8EI32_V_MF2_M1, VLUXSEG8EI32_V }, // 5897 |
| 27168 | { PseudoVLUXSEG8EI32_V_MF2_M1_MASK, VLUXSEG8EI32_V }, // 5898 |
| 27169 | { PseudoVLUXSEG8EI32_V_MF2_MF2, VLUXSEG8EI32_V }, // 5899 |
| 27170 | { PseudoVLUXSEG8EI32_V_MF2_MF2_MASK, VLUXSEG8EI32_V }, // 5900 |
| 27171 | { PseudoVLUXSEG8EI32_V_MF2_MF4, VLUXSEG8EI32_V }, // 5901 |
| 27172 | { PseudoVLUXSEG8EI32_V_MF2_MF4_MASK, VLUXSEG8EI32_V }, // 5902 |
| 27173 | { PseudoVLUXSEG8EI32_V_MF2_MF8, VLUXSEG8EI32_V }, // 5903 |
| 27174 | { PseudoVLUXSEG8EI32_V_MF2_MF8_MASK, VLUXSEG8EI32_V }, // 5904 |
| 27175 | { PseudoVLUXSEG8EI64_V_M1_M1, VLUXSEG8EI64_V }, // 5905 |
| 27176 | { PseudoVLUXSEG8EI64_V_M1_M1_MASK, VLUXSEG8EI64_V }, // 5906 |
| 27177 | { PseudoVLUXSEG8EI64_V_M1_MF2, VLUXSEG8EI64_V }, // 5907 |
| 27178 | { PseudoVLUXSEG8EI64_V_M1_MF2_MASK, VLUXSEG8EI64_V }, // 5908 |
| 27179 | { PseudoVLUXSEG8EI64_V_M1_MF4, VLUXSEG8EI64_V }, // 5909 |
| 27180 | { PseudoVLUXSEG8EI64_V_M1_MF4_MASK, VLUXSEG8EI64_V }, // 5910 |
| 27181 | { PseudoVLUXSEG8EI64_V_M1_MF8, VLUXSEG8EI64_V }, // 5911 |
| 27182 | { PseudoVLUXSEG8EI64_V_M1_MF8_MASK, VLUXSEG8EI64_V }, // 5912 |
| 27183 | { PseudoVLUXSEG8EI64_V_M2_M1, VLUXSEG8EI64_V }, // 5913 |
| 27184 | { PseudoVLUXSEG8EI64_V_M2_M1_MASK, VLUXSEG8EI64_V }, // 5914 |
| 27185 | { PseudoVLUXSEG8EI64_V_M2_MF2, VLUXSEG8EI64_V }, // 5915 |
| 27186 | { PseudoVLUXSEG8EI64_V_M2_MF2_MASK, VLUXSEG8EI64_V }, // 5916 |
| 27187 | { PseudoVLUXSEG8EI64_V_M2_MF4, VLUXSEG8EI64_V }, // 5917 |
| 27188 | { PseudoVLUXSEG8EI64_V_M2_MF4_MASK, VLUXSEG8EI64_V }, // 5918 |
| 27189 | { PseudoVLUXSEG8EI64_V_M4_M1, VLUXSEG8EI64_V }, // 5919 |
| 27190 | { PseudoVLUXSEG8EI64_V_M4_M1_MASK, VLUXSEG8EI64_V }, // 5920 |
| 27191 | { PseudoVLUXSEG8EI64_V_M4_MF2, VLUXSEG8EI64_V }, // 5921 |
| 27192 | { PseudoVLUXSEG8EI64_V_M4_MF2_MASK, VLUXSEG8EI64_V }, // 5922 |
| 27193 | { PseudoVLUXSEG8EI64_V_M8_M1, VLUXSEG8EI64_V }, // 5923 |
| 27194 | { PseudoVLUXSEG8EI64_V_M8_M1_MASK, VLUXSEG8EI64_V }, // 5924 |
| 27195 | { PseudoVLUXSEG8EI8_V_M1_M1, VLUXSEG8EI8_V }, // 5925 |
| 27196 | { PseudoVLUXSEG8EI8_V_M1_M1_MASK, VLUXSEG8EI8_V }, // 5926 |
| 27197 | { PseudoVLUXSEG8EI8_V_MF2_M1, VLUXSEG8EI8_V }, // 5927 |
| 27198 | { PseudoVLUXSEG8EI8_V_MF2_M1_MASK, VLUXSEG8EI8_V }, // 5928 |
| 27199 | { PseudoVLUXSEG8EI8_V_MF2_MF2, VLUXSEG8EI8_V }, // 5929 |
| 27200 | { PseudoVLUXSEG8EI8_V_MF2_MF2_MASK, VLUXSEG8EI8_V }, // 5930 |
| 27201 | { PseudoVLUXSEG8EI8_V_MF4_M1, VLUXSEG8EI8_V }, // 5931 |
| 27202 | { PseudoVLUXSEG8EI8_V_MF4_M1_MASK, VLUXSEG8EI8_V }, // 5932 |
| 27203 | { PseudoVLUXSEG8EI8_V_MF4_MF2, VLUXSEG8EI8_V }, // 5933 |
| 27204 | { PseudoVLUXSEG8EI8_V_MF4_MF2_MASK, VLUXSEG8EI8_V }, // 5934 |
| 27205 | { PseudoVLUXSEG8EI8_V_MF4_MF4, VLUXSEG8EI8_V }, // 5935 |
| 27206 | { PseudoVLUXSEG8EI8_V_MF4_MF4_MASK, VLUXSEG8EI8_V }, // 5936 |
| 27207 | { PseudoVLUXSEG8EI8_V_MF8_M1, VLUXSEG8EI8_V }, // 5937 |
| 27208 | { PseudoVLUXSEG8EI8_V_MF8_M1_MASK, VLUXSEG8EI8_V }, // 5938 |
| 27209 | { PseudoVLUXSEG8EI8_V_MF8_MF2, VLUXSEG8EI8_V }, // 5939 |
| 27210 | { PseudoVLUXSEG8EI8_V_MF8_MF2_MASK, VLUXSEG8EI8_V }, // 5940 |
| 27211 | { PseudoVLUXSEG8EI8_V_MF8_MF4, VLUXSEG8EI8_V }, // 5941 |
| 27212 | { PseudoVLUXSEG8EI8_V_MF8_MF4_MASK, VLUXSEG8EI8_V }, // 5942 |
| 27213 | { PseudoVLUXSEG8EI8_V_MF8_MF8, VLUXSEG8EI8_V }, // 5943 |
| 27214 | { PseudoVLUXSEG8EI8_V_MF8_MF8_MASK, VLUXSEG8EI8_V }, // 5944 |
| 27215 | { PseudoVMACC_VV_M1, VMACC_VV }, // 5945 |
| 27216 | { PseudoVMACC_VV_M1_MASK, VMACC_VV }, // 5946 |
| 27217 | { PseudoVMACC_VV_M2, VMACC_VV }, // 5947 |
| 27218 | { PseudoVMACC_VV_M2_MASK, VMACC_VV }, // 5948 |
| 27219 | { PseudoVMACC_VV_M4, VMACC_VV }, // 5949 |
| 27220 | { PseudoVMACC_VV_M4_MASK, VMACC_VV }, // 5950 |
| 27221 | { PseudoVMACC_VV_M8, VMACC_VV }, // 5951 |
| 27222 | { PseudoVMACC_VV_M8_MASK, VMACC_VV }, // 5952 |
| 27223 | { PseudoVMACC_VV_MF2, VMACC_VV }, // 5953 |
| 27224 | { PseudoVMACC_VV_MF2_MASK, VMACC_VV }, // 5954 |
| 27225 | { PseudoVMACC_VV_MF4, VMACC_VV }, // 5955 |
| 27226 | { PseudoVMACC_VV_MF4_MASK, VMACC_VV }, // 5956 |
| 27227 | { PseudoVMACC_VV_MF8, VMACC_VV }, // 5957 |
| 27228 | { PseudoVMACC_VV_MF8_MASK, VMACC_VV }, // 5958 |
| 27229 | { PseudoVMACC_VX_M1, VMACC_VX }, // 5959 |
| 27230 | { PseudoVMACC_VX_M1_MASK, VMACC_VX }, // 5960 |
| 27231 | { PseudoVMACC_VX_M2, VMACC_VX }, // 5961 |
| 27232 | { PseudoVMACC_VX_M2_MASK, VMACC_VX }, // 5962 |
| 27233 | { PseudoVMACC_VX_M4, VMACC_VX }, // 5963 |
| 27234 | { PseudoVMACC_VX_M4_MASK, VMACC_VX }, // 5964 |
| 27235 | { PseudoVMACC_VX_M8, VMACC_VX }, // 5965 |
| 27236 | { PseudoVMACC_VX_M8_MASK, VMACC_VX }, // 5966 |
| 27237 | { PseudoVMACC_VX_MF2, VMACC_VX }, // 5967 |
| 27238 | { PseudoVMACC_VX_MF2_MASK, VMACC_VX }, // 5968 |
| 27239 | { PseudoVMACC_VX_MF4, VMACC_VX }, // 5969 |
| 27240 | { PseudoVMACC_VX_MF4_MASK, VMACC_VX }, // 5970 |
| 27241 | { PseudoVMACC_VX_MF8, VMACC_VX }, // 5971 |
| 27242 | { PseudoVMACC_VX_MF8_MASK, VMACC_VX }, // 5972 |
| 27243 | { PseudoVMADC_VIM_M1, VMADC_VIM }, // 5973 |
| 27244 | { PseudoVMADC_VIM_M2, VMADC_VIM }, // 5974 |
| 27245 | { PseudoVMADC_VIM_M4, VMADC_VIM }, // 5975 |
| 27246 | { PseudoVMADC_VIM_M8, VMADC_VIM }, // 5976 |
| 27247 | { PseudoVMADC_VIM_MF2, VMADC_VIM }, // 5977 |
| 27248 | { PseudoVMADC_VIM_MF4, VMADC_VIM }, // 5978 |
| 27249 | { PseudoVMADC_VIM_MF8, VMADC_VIM }, // 5979 |
| 27250 | { PseudoVMADC_VI_M1, VMADC_VI }, // 5980 |
| 27251 | { PseudoVMADC_VI_M2, VMADC_VI }, // 5981 |
| 27252 | { PseudoVMADC_VI_M4, VMADC_VI }, // 5982 |
| 27253 | { PseudoVMADC_VI_M8, VMADC_VI }, // 5983 |
| 27254 | { PseudoVMADC_VI_MF2, VMADC_VI }, // 5984 |
| 27255 | { PseudoVMADC_VI_MF4, VMADC_VI }, // 5985 |
| 27256 | { PseudoVMADC_VI_MF8, VMADC_VI }, // 5986 |
| 27257 | { PseudoVMADC_VVM_M1, VMADC_VVM }, // 5987 |
| 27258 | { PseudoVMADC_VVM_M2, VMADC_VVM }, // 5988 |
| 27259 | { PseudoVMADC_VVM_M4, VMADC_VVM }, // 5989 |
| 27260 | { PseudoVMADC_VVM_M8, VMADC_VVM }, // 5990 |
| 27261 | { PseudoVMADC_VVM_MF2, VMADC_VVM }, // 5991 |
| 27262 | { PseudoVMADC_VVM_MF4, VMADC_VVM }, // 5992 |
| 27263 | { PseudoVMADC_VVM_MF8, VMADC_VVM }, // 5993 |
| 27264 | { PseudoVMADC_VV_M1, VMADC_VV }, // 5994 |
| 27265 | { PseudoVMADC_VV_M2, VMADC_VV }, // 5995 |
| 27266 | { PseudoVMADC_VV_M4, VMADC_VV }, // 5996 |
| 27267 | { PseudoVMADC_VV_M8, VMADC_VV }, // 5997 |
| 27268 | { PseudoVMADC_VV_MF2, VMADC_VV }, // 5998 |
| 27269 | { PseudoVMADC_VV_MF4, VMADC_VV }, // 5999 |
| 27270 | { PseudoVMADC_VV_MF8, VMADC_VV }, // 6000 |
| 27271 | { PseudoVMADC_VXM_M1, VMADC_VXM }, // 6001 |
| 27272 | { PseudoVMADC_VXM_M2, VMADC_VXM }, // 6002 |
| 27273 | { PseudoVMADC_VXM_M4, VMADC_VXM }, // 6003 |
| 27274 | { PseudoVMADC_VXM_M8, VMADC_VXM }, // 6004 |
| 27275 | { PseudoVMADC_VXM_MF2, VMADC_VXM }, // 6005 |
| 27276 | { PseudoVMADC_VXM_MF4, VMADC_VXM }, // 6006 |
| 27277 | { PseudoVMADC_VXM_MF8, VMADC_VXM }, // 6007 |
| 27278 | { PseudoVMADC_VX_M1, VMADC_VX }, // 6008 |
| 27279 | { PseudoVMADC_VX_M2, VMADC_VX }, // 6009 |
| 27280 | { PseudoVMADC_VX_M4, VMADC_VX }, // 6010 |
| 27281 | { PseudoVMADC_VX_M8, VMADC_VX }, // 6011 |
| 27282 | { PseudoVMADC_VX_MF2, VMADC_VX }, // 6012 |
| 27283 | { PseudoVMADC_VX_MF4, VMADC_VX }, // 6013 |
| 27284 | { PseudoVMADC_VX_MF8, VMADC_VX }, // 6014 |
| 27285 | { PseudoVMADD_VV_M1, VMADD_VV }, // 6015 |
| 27286 | { PseudoVMADD_VV_M1_MASK, VMADD_VV }, // 6016 |
| 27287 | { PseudoVMADD_VV_M2, VMADD_VV }, // 6017 |
| 27288 | { PseudoVMADD_VV_M2_MASK, VMADD_VV }, // 6018 |
| 27289 | { PseudoVMADD_VV_M4, VMADD_VV }, // 6019 |
| 27290 | { PseudoVMADD_VV_M4_MASK, VMADD_VV }, // 6020 |
| 27291 | { PseudoVMADD_VV_M8, VMADD_VV }, // 6021 |
| 27292 | { PseudoVMADD_VV_M8_MASK, VMADD_VV }, // 6022 |
| 27293 | { PseudoVMADD_VV_MF2, VMADD_VV }, // 6023 |
| 27294 | { PseudoVMADD_VV_MF2_MASK, VMADD_VV }, // 6024 |
| 27295 | { PseudoVMADD_VV_MF4, VMADD_VV }, // 6025 |
| 27296 | { PseudoVMADD_VV_MF4_MASK, VMADD_VV }, // 6026 |
| 27297 | { PseudoVMADD_VV_MF8, VMADD_VV }, // 6027 |
| 27298 | { PseudoVMADD_VV_MF8_MASK, VMADD_VV }, // 6028 |
| 27299 | { PseudoVMADD_VX_M1, VMADD_VX }, // 6029 |
| 27300 | { PseudoVMADD_VX_M1_MASK, VMADD_VX }, // 6030 |
| 27301 | { PseudoVMADD_VX_M2, VMADD_VX }, // 6031 |
| 27302 | { PseudoVMADD_VX_M2_MASK, VMADD_VX }, // 6032 |
| 27303 | { PseudoVMADD_VX_M4, VMADD_VX }, // 6033 |
| 27304 | { PseudoVMADD_VX_M4_MASK, VMADD_VX }, // 6034 |
| 27305 | { PseudoVMADD_VX_M8, VMADD_VX }, // 6035 |
| 27306 | { PseudoVMADD_VX_M8_MASK, VMADD_VX }, // 6036 |
| 27307 | { PseudoVMADD_VX_MF2, VMADD_VX }, // 6037 |
| 27308 | { PseudoVMADD_VX_MF2_MASK, VMADD_VX }, // 6038 |
| 27309 | { PseudoVMADD_VX_MF4, VMADD_VX }, // 6039 |
| 27310 | { PseudoVMADD_VX_MF4_MASK, VMADD_VX }, // 6040 |
| 27311 | { PseudoVMADD_VX_MF8, VMADD_VX }, // 6041 |
| 27312 | { PseudoVMADD_VX_MF8_MASK, VMADD_VX }, // 6042 |
| 27313 | { PseudoVMANDN_MM_M1, VMANDN_MM }, // 6043 |
| 27314 | { PseudoVMANDN_MM_M2, VMANDN_MM }, // 6044 |
| 27315 | { PseudoVMANDN_MM_M4, VMANDN_MM }, // 6045 |
| 27316 | { PseudoVMANDN_MM_M8, VMANDN_MM }, // 6046 |
| 27317 | { PseudoVMANDN_MM_MF2, VMANDN_MM }, // 6047 |
| 27318 | { PseudoVMANDN_MM_MF4, VMANDN_MM }, // 6048 |
| 27319 | { PseudoVMANDN_MM_MF8, VMANDN_MM }, // 6049 |
| 27320 | { PseudoVMAND_MM_M1, VMAND_MM }, // 6050 |
| 27321 | { PseudoVMAND_MM_M2, VMAND_MM }, // 6051 |
| 27322 | { PseudoVMAND_MM_M4, VMAND_MM }, // 6052 |
| 27323 | { PseudoVMAND_MM_M8, VMAND_MM }, // 6053 |
| 27324 | { PseudoVMAND_MM_MF2, VMAND_MM }, // 6054 |
| 27325 | { PseudoVMAND_MM_MF4, VMAND_MM }, // 6055 |
| 27326 | { PseudoVMAND_MM_MF8, VMAND_MM }, // 6056 |
| 27327 | { PseudoVMAXU_VV_M1, VMAXU_VV }, // 6057 |
| 27328 | { PseudoVMAXU_VV_M1_MASK, VMAXU_VV }, // 6058 |
| 27329 | { PseudoVMAXU_VV_M2, VMAXU_VV }, // 6059 |
| 27330 | { PseudoVMAXU_VV_M2_MASK, VMAXU_VV }, // 6060 |
| 27331 | { PseudoVMAXU_VV_M4, VMAXU_VV }, // 6061 |
| 27332 | { PseudoVMAXU_VV_M4_MASK, VMAXU_VV }, // 6062 |
| 27333 | { PseudoVMAXU_VV_M8, VMAXU_VV }, // 6063 |
| 27334 | { PseudoVMAXU_VV_M8_MASK, VMAXU_VV }, // 6064 |
| 27335 | { PseudoVMAXU_VV_MF2, VMAXU_VV }, // 6065 |
| 27336 | { PseudoVMAXU_VV_MF2_MASK, VMAXU_VV }, // 6066 |
| 27337 | { PseudoVMAXU_VV_MF4, VMAXU_VV }, // 6067 |
| 27338 | { PseudoVMAXU_VV_MF4_MASK, VMAXU_VV }, // 6068 |
| 27339 | { PseudoVMAXU_VV_MF8, VMAXU_VV }, // 6069 |
| 27340 | { PseudoVMAXU_VV_MF8_MASK, VMAXU_VV }, // 6070 |
| 27341 | { PseudoVMAXU_VX_M1, VMAXU_VX }, // 6071 |
| 27342 | { PseudoVMAXU_VX_M1_MASK, VMAXU_VX }, // 6072 |
| 27343 | { PseudoVMAXU_VX_M2, VMAXU_VX }, // 6073 |
| 27344 | { PseudoVMAXU_VX_M2_MASK, VMAXU_VX }, // 6074 |
| 27345 | { PseudoVMAXU_VX_M4, VMAXU_VX }, // 6075 |
| 27346 | { PseudoVMAXU_VX_M4_MASK, VMAXU_VX }, // 6076 |
| 27347 | { PseudoVMAXU_VX_M8, VMAXU_VX }, // 6077 |
| 27348 | { PseudoVMAXU_VX_M8_MASK, VMAXU_VX }, // 6078 |
| 27349 | { PseudoVMAXU_VX_MF2, VMAXU_VX }, // 6079 |
| 27350 | { PseudoVMAXU_VX_MF2_MASK, VMAXU_VX }, // 6080 |
| 27351 | { PseudoVMAXU_VX_MF4, VMAXU_VX }, // 6081 |
| 27352 | { PseudoVMAXU_VX_MF4_MASK, VMAXU_VX }, // 6082 |
| 27353 | { PseudoVMAXU_VX_MF8, VMAXU_VX }, // 6083 |
| 27354 | { PseudoVMAXU_VX_MF8_MASK, VMAXU_VX }, // 6084 |
| 27355 | { PseudoVMAX_VV_M1, VMAX_VV }, // 6085 |
| 27356 | { PseudoVMAX_VV_M1_MASK, VMAX_VV }, // 6086 |
| 27357 | { PseudoVMAX_VV_M2, VMAX_VV }, // 6087 |
| 27358 | { PseudoVMAX_VV_M2_MASK, VMAX_VV }, // 6088 |
| 27359 | { PseudoVMAX_VV_M4, VMAX_VV }, // 6089 |
| 27360 | { PseudoVMAX_VV_M4_MASK, VMAX_VV }, // 6090 |
| 27361 | { PseudoVMAX_VV_M8, VMAX_VV }, // 6091 |
| 27362 | { PseudoVMAX_VV_M8_MASK, VMAX_VV }, // 6092 |
| 27363 | { PseudoVMAX_VV_MF2, VMAX_VV }, // 6093 |
| 27364 | { PseudoVMAX_VV_MF2_MASK, VMAX_VV }, // 6094 |
| 27365 | { PseudoVMAX_VV_MF4, VMAX_VV }, // 6095 |
| 27366 | { PseudoVMAX_VV_MF4_MASK, VMAX_VV }, // 6096 |
| 27367 | { PseudoVMAX_VV_MF8, VMAX_VV }, // 6097 |
| 27368 | { PseudoVMAX_VV_MF8_MASK, VMAX_VV }, // 6098 |
| 27369 | { PseudoVMAX_VX_M1, VMAX_VX }, // 6099 |
| 27370 | { PseudoVMAX_VX_M1_MASK, VMAX_VX }, // 6100 |
| 27371 | { PseudoVMAX_VX_M2, VMAX_VX }, // 6101 |
| 27372 | { PseudoVMAX_VX_M2_MASK, VMAX_VX }, // 6102 |
| 27373 | { PseudoVMAX_VX_M4, VMAX_VX }, // 6103 |
| 27374 | { PseudoVMAX_VX_M4_MASK, VMAX_VX }, // 6104 |
| 27375 | { PseudoVMAX_VX_M8, VMAX_VX }, // 6105 |
| 27376 | { PseudoVMAX_VX_M8_MASK, VMAX_VX }, // 6106 |
| 27377 | { PseudoVMAX_VX_MF2, VMAX_VX }, // 6107 |
| 27378 | { PseudoVMAX_VX_MF2_MASK, VMAX_VX }, // 6108 |
| 27379 | { PseudoVMAX_VX_MF4, VMAX_VX }, // 6109 |
| 27380 | { PseudoVMAX_VX_MF4_MASK, VMAX_VX }, // 6110 |
| 27381 | { PseudoVMAX_VX_MF8, VMAX_VX }, // 6111 |
| 27382 | { PseudoVMAX_VX_MF8_MASK, VMAX_VX }, // 6112 |
| 27383 | { PseudoVMERGE_VIM_M1, VMERGE_VIM }, // 6113 |
| 27384 | { PseudoVMERGE_VIM_M2, VMERGE_VIM }, // 6114 |
| 27385 | { PseudoVMERGE_VIM_M4, VMERGE_VIM }, // 6115 |
| 27386 | { PseudoVMERGE_VIM_M8, VMERGE_VIM }, // 6116 |
| 27387 | { PseudoVMERGE_VIM_MF2, VMERGE_VIM }, // 6117 |
| 27388 | { PseudoVMERGE_VIM_MF4, VMERGE_VIM }, // 6118 |
| 27389 | { PseudoVMERGE_VIM_MF8, VMERGE_VIM }, // 6119 |
| 27390 | { PseudoVMERGE_VVM_M1, VMERGE_VVM }, // 6120 |
| 27391 | { PseudoVMERGE_VVM_M2, VMERGE_VVM }, // 6121 |
| 27392 | { PseudoVMERGE_VVM_M4, VMERGE_VVM }, // 6122 |
| 27393 | { PseudoVMERGE_VVM_M8, VMERGE_VVM }, // 6123 |
| 27394 | { PseudoVMERGE_VVM_MF2, VMERGE_VVM }, // 6124 |
| 27395 | { PseudoVMERGE_VVM_MF4, VMERGE_VVM }, // 6125 |
| 27396 | { PseudoVMERGE_VVM_MF8, VMERGE_VVM }, // 6126 |
| 27397 | { PseudoVMERGE_VXM_M1, VMERGE_VXM }, // 6127 |
| 27398 | { PseudoVMERGE_VXM_M2, VMERGE_VXM }, // 6128 |
| 27399 | { PseudoVMERGE_VXM_M4, VMERGE_VXM }, // 6129 |
| 27400 | { PseudoVMERGE_VXM_M8, VMERGE_VXM }, // 6130 |
| 27401 | { PseudoVMERGE_VXM_MF2, VMERGE_VXM }, // 6131 |
| 27402 | { PseudoVMERGE_VXM_MF4, VMERGE_VXM }, // 6132 |
| 27403 | { PseudoVMERGE_VXM_MF8, VMERGE_VXM }, // 6133 |
| 27404 | { PseudoVMFEQ_VFPR16_M1, VMFEQ_VF }, // 6134 |
| 27405 | { PseudoVMFEQ_VFPR16_M1_MASK, VMFEQ_VF }, // 6135 |
| 27406 | { PseudoVMFEQ_VFPR16_M2, VMFEQ_VF }, // 6136 |
| 27407 | { PseudoVMFEQ_VFPR16_M2_MASK, VMFEQ_VF }, // 6137 |
| 27408 | { PseudoVMFEQ_VFPR16_M4, VMFEQ_VF }, // 6138 |
| 27409 | { PseudoVMFEQ_VFPR16_M4_MASK, VMFEQ_VF }, // 6139 |
| 27410 | { PseudoVMFEQ_VFPR16_M8, VMFEQ_VF }, // 6140 |
| 27411 | { PseudoVMFEQ_VFPR16_M8_MASK, VMFEQ_VF }, // 6141 |
| 27412 | { PseudoVMFEQ_VFPR16_MF2, VMFEQ_VF }, // 6142 |
| 27413 | { PseudoVMFEQ_VFPR16_MF2_MASK, VMFEQ_VF }, // 6143 |
| 27414 | { PseudoVMFEQ_VFPR16_MF4, VMFEQ_VF }, // 6144 |
| 27415 | { PseudoVMFEQ_VFPR16_MF4_MASK, VMFEQ_VF }, // 6145 |
| 27416 | { PseudoVMFEQ_VFPR32_M1, VMFEQ_VF }, // 6146 |
| 27417 | { PseudoVMFEQ_VFPR32_M1_MASK, VMFEQ_VF }, // 6147 |
| 27418 | { PseudoVMFEQ_VFPR32_M2, VMFEQ_VF }, // 6148 |
| 27419 | { PseudoVMFEQ_VFPR32_M2_MASK, VMFEQ_VF }, // 6149 |
| 27420 | { PseudoVMFEQ_VFPR32_M4, VMFEQ_VF }, // 6150 |
| 27421 | { PseudoVMFEQ_VFPR32_M4_MASK, VMFEQ_VF }, // 6151 |
| 27422 | { PseudoVMFEQ_VFPR32_M8, VMFEQ_VF }, // 6152 |
| 27423 | { PseudoVMFEQ_VFPR32_M8_MASK, VMFEQ_VF }, // 6153 |
| 27424 | { PseudoVMFEQ_VFPR32_MF2, VMFEQ_VF }, // 6154 |
| 27425 | { PseudoVMFEQ_VFPR32_MF2_MASK, VMFEQ_VF }, // 6155 |
| 27426 | { PseudoVMFEQ_VFPR64_M1, VMFEQ_VF }, // 6156 |
| 27427 | { PseudoVMFEQ_VFPR64_M1_MASK, VMFEQ_VF }, // 6157 |
| 27428 | { PseudoVMFEQ_VFPR64_M2, VMFEQ_VF }, // 6158 |
| 27429 | { PseudoVMFEQ_VFPR64_M2_MASK, VMFEQ_VF }, // 6159 |
| 27430 | { PseudoVMFEQ_VFPR64_M4, VMFEQ_VF }, // 6160 |
| 27431 | { PseudoVMFEQ_VFPR64_M4_MASK, VMFEQ_VF }, // 6161 |
| 27432 | { PseudoVMFEQ_VFPR64_M8, VMFEQ_VF }, // 6162 |
| 27433 | { PseudoVMFEQ_VFPR64_M8_MASK, VMFEQ_VF }, // 6163 |
| 27434 | { PseudoVMFEQ_VV_M1, VMFEQ_VV }, // 6164 |
| 27435 | { PseudoVMFEQ_VV_M1_MASK, VMFEQ_VV }, // 6165 |
| 27436 | { PseudoVMFEQ_VV_M2, VMFEQ_VV }, // 6166 |
| 27437 | { PseudoVMFEQ_VV_M2_MASK, VMFEQ_VV }, // 6167 |
| 27438 | { PseudoVMFEQ_VV_M4, VMFEQ_VV }, // 6168 |
| 27439 | { PseudoVMFEQ_VV_M4_MASK, VMFEQ_VV }, // 6169 |
| 27440 | { PseudoVMFEQ_VV_M8, VMFEQ_VV }, // 6170 |
| 27441 | { PseudoVMFEQ_VV_M8_MASK, VMFEQ_VV }, // 6171 |
| 27442 | { PseudoVMFEQ_VV_MF2, VMFEQ_VV }, // 6172 |
| 27443 | { PseudoVMFEQ_VV_MF2_MASK, VMFEQ_VV }, // 6173 |
| 27444 | { PseudoVMFEQ_VV_MF4, VMFEQ_VV }, // 6174 |
| 27445 | { PseudoVMFEQ_VV_MF4_MASK, VMFEQ_VV }, // 6175 |
| 27446 | { PseudoVMFGE_VFPR16_M1, VMFGE_VF }, // 6176 |
| 27447 | { PseudoVMFGE_VFPR16_M1_MASK, VMFGE_VF }, // 6177 |
| 27448 | { PseudoVMFGE_VFPR16_M2, VMFGE_VF }, // 6178 |
| 27449 | { PseudoVMFGE_VFPR16_M2_MASK, VMFGE_VF }, // 6179 |
| 27450 | { PseudoVMFGE_VFPR16_M4, VMFGE_VF }, // 6180 |
| 27451 | { PseudoVMFGE_VFPR16_M4_MASK, VMFGE_VF }, // 6181 |
| 27452 | { PseudoVMFGE_VFPR16_M8, VMFGE_VF }, // 6182 |
| 27453 | { PseudoVMFGE_VFPR16_M8_MASK, VMFGE_VF }, // 6183 |
| 27454 | { PseudoVMFGE_VFPR16_MF2, VMFGE_VF }, // 6184 |
| 27455 | { PseudoVMFGE_VFPR16_MF2_MASK, VMFGE_VF }, // 6185 |
| 27456 | { PseudoVMFGE_VFPR16_MF4, VMFGE_VF }, // 6186 |
| 27457 | { PseudoVMFGE_VFPR16_MF4_MASK, VMFGE_VF }, // 6187 |
| 27458 | { PseudoVMFGE_VFPR32_M1, VMFGE_VF }, // 6188 |
| 27459 | { PseudoVMFGE_VFPR32_M1_MASK, VMFGE_VF }, // 6189 |
| 27460 | { PseudoVMFGE_VFPR32_M2, VMFGE_VF }, // 6190 |
| 27461 | { PseudoVMFGE_VFPR32_M2_MASK, VMFGE_VF }, // 6191 |
| 27462 | { PseudoVMFGE_VFPR32_M4, VMFGE_VF }, // 6192 |
| 27463 | { PseudoVMFGE_VFPR32_M4_MASK, VMFGE_VF }, // 6193 |
| 27464 | { PseudoVMFGE_VFPR32_M8, VMFGE_VF }, // 6194 |
| 27465 | { PseudoVMFGE_VFPR32_M8_MASK, VMFGE_VF }, // 6195 |
| 27466 | { PseudoVMFGE_VFPR32_MF2, VMFGE_VF }, // 6196 |
| 27467 | { PseudoVMFGE_VFPR32_MF2_MASK, VMFGE_VF }, // 6197 |
| 27468 | { PseudoVMFGE_VFPR64_M1, VMFGE_VF }, // 6198 |
| 27469 | { PseudoVMFGE_VFPR64_M1_MASK, VMFGE_VF }, // 6199 |
| 27470 | { PseudoVMFGE_VFPR64_M2, VMFGE_VF }, // 6200 |
| 27471 | { PseudoVMFGE_VFPR64_M2_MASK, VMFGE_VF }, // 6201 |
| 27472 | { PseudoVMFGE_VFPR64_M4, VMFGE_VF }, // 6202 |
| 27473 | { PseudoVMFGE_VFPR64_M4_MASK, VMFGE_VF }, // 6203 |
| 27474 | { PseudoVMFGE_VFPR64_M8, VMFGE_VF }, // 6204 |
| 27475 | { PseudoVMFGE_VFPR64_M8_MASK, VMFGE_VF }, // 6205 |
| 27476 | { PseudoVMFGT_VFPR16_M1, VMFGT_VF }, // 6206 |
| 27477 | { PseudoVMFGT_VFPR16_M1_MASK, VMFGT_VF }, // 6207 |
| 27478 | { PseudoVMFGT_VFPR16_M2, VMFGT_VF }, // 6208 |
| 27479 | { PseudoVMFGT_VFPR16_M2_MASK, VMFGT_VF }, // 6209 |
| 27480 | { PseudoVMFGT_VFPR16_M4, VMFGT_VF }, // 6210 |
| 27481 | { PseudoVMFGT_VFPR16_M4_MASK, VMFGT_VF }, // 6211 |
| 27482 | { PseudoVMFGT_VFPR16_M8, VMFGT_VF }, // 6212 |
| 27483 | { PseudoVMFGT_VFPR16_M8_MASK, VMFGT_VF }, // 6213 |
| 27484 | { PseudoVMFGT_VFPR16_MF2, VMFGT_VF }, // 6214 |
| 27485 | { PseudoVMFGT_VFPR16_MF2_MASK, VMFGT_VF }, // 6215 |
| 27486 | { PseudoVMFGT_VFPR16_MF4, VMFGT_VF }, // 6216 |
| 27487 | { PseudoVMFGT_VFPR16_MF4_MASK, VMFGT_VF }, // 6217 |
| 27488 | { PseudoVMFGT_VFPR32_M1, VMFGT_VF }, // 6218 |
| 27489 | { PseudoVMFGT_VFPR32_M1_MASK, VMFGT_VF }, // 6219 |
| 27490 | { PseudoVMFGT_VFPR32_M2, VMFGT_VF }, // 6220 |
| 27491 | { PseudoVMFGT_VFPR32_M2_MASK, VMFGT_VF }, // 6221 |
| 27492 | { PseudoVMFGT_VFPR32_M4, VMFGT_VF }, // 6222 |
| 27493 | { PseudoVMFGT_VFPR32_M4_MASK, VMFGT_VF }, // 6223 |
| 27494 | { PseudoVMFGT_VFPR32_M8, VMFGT_VF }, // 6224 |
| 27495 | { PseudoVMFGT_VFPR32_M8_MASK, VMFGT_VF }, // 6225 |
| 27496 | { PseudoVMFGT_VFPR32_MF2, VMFGT_VF }, // 6226 |
| 27497 | { PseudoVMFGT_VFPR32_MF2_MASK, VMFGT_VF }, // 6227 |
| 27498 | { PseudoVMFGT_VFPR64_M1, VMFGT_VF }, // 6228 |
| 27499 | { PseudoVMFGT_VFPR64_M1_MASK, VMFGT_VF }, // 6229 |
| 27500 | { PseudoVMFGT_VFPR64_M2, VMFGT_VF }, // 6230 |
| 27501 | { PseudoVMFGT_VFPR64_M2_MASK, VMFGT_VF }, // 6231 |
| 27502 | { PseudoVMFGT_VFPR64_M4, VMFGT_VF }, // 6232 |
| 27503 | { PseudoVMFGT_VFPR64_M4_MASK, VMFGT_VF }, // 6233 |
| 27504 | { PseudoVMFGT_VFPR64_M8, VMFGT_VF }, // 6234 |
| 27505 | { PseudoVMFGT_VFPR64_M8_MASK, VMFGT_VF }, // 6235 |
| 27506 | { PseudoVMFLE_VFPR16_M1, VMFLE_VF }, // 6236 |
| 27507 | { PseudoVMFLE_VFPR16_M1_MASK, VMFLE_VF }, // 6237 |
| 27508 | { PseudoVMFLE_VFPR16_M2, VMFLE_VF }, // 6238 |
| 27509 | { PseudoVMFLE_VFPR16_M2_MASK, VMFLE_VF }, // 6239 |
| 27510 | { PseudoVMFLE_VFPR16_M4, VMFLE_VF }, // 6240 |
| 27511 | { PseudoVMFLE_VFPR16_M4_MASK, VMFLE_VF }, // 6241 |
| 27512 | { PseudoVMFLE_VFPR16_M8, VMFLE_VF }, // 6242 |
| 27513 | { PseudoVMFLE_VFPR16_M8_MASK, VMFLE_VF }, // 6243 |
| 27514 | { PseudoVMFLE_VFPR16_MF2, VMFLE_VF }, // 6244 |
| 27515 | { PseudoVMFLE_VFPR16_MF2_MASK, VMFLE_VF }, // 6245 |
| 27516 | { PseudoVMFLE_VFPR16_MF4, VMFLE_VF }, // 6246 |
| 27517 | { PseudoVMFLE_VFPR16_MF4_MASK, VMFLE_VF }, // 6247 |
| 27518 | { PseudoVMFLE_VFPR32_M1, VMFLE_VF }, // 6248 |
| 27519 | { PseudoVMFLE_VFPR32_M1_MASK, VMFLE_VF }, // 6249 |
| 27520 | { PseudoVMFLE_VFPR32_M2, VMFLE_VF }, // 6250 |
| 27521 | { PseudoVMFLE_VFPR32_M2_MASK, VMFLE_VF }, // 6251 |
| 27522 | { PseudoVMFLE_VFPR32_M4, VMFLE_VF }, // 6252 |
| 27523 | { PseudoVMFLE_VFPR32_M4_MASK, VMFLE_VF }, // 6253 |
| 27524 | { PseudoVMFLE_VFPR32_M8, VMFLE_VF }, // 6254 |
| 27525 | { PseudoVMFLE_VFPR32_M8_MASK, VMFLE_VF }, // 6255 |
| 27526 | { PseudoVMFLE_VFPR32_MF2, VMFLE_VF }, // 6256 |
| 27527 | { PseudoVMFLE_VFPR32_MF2_MASK, VMFLE_VF }, // 6257 |
| 27528 | { PseudoVMFLE_VFPR64_M1, VMFLE_VF }, // 6258 |
| 27529 | { PseudoVMFLE_VFPR64_M1_MASK, VMFLE_VF }, // 6259 |
| 27530 | { PseudoVMFLE_VFPR64_M2, VMFLE_VF }, // 6260 |
| 27531 | { PseudoVMFLE_VFPR64_M2_MASK, VMFLE_VF }, // 6261 |
| 27532 | { PseudoVMFLE_VFPR64_M4, VMFLE_VF }, // 6262 |
| 27533 | { PseudoVMFLE_VFPR64_M4_MASK, VMFLE_VF }, // 6263 |
| 27534 | { PseudoVMFLE_VFPR64_M8, VMFLE_VF }, // 6264 |
| 27535 | { PseudoVMFLE_VFPR64_M8_MASK, VMFLE_VF }, // 6265 |
| 27536 | { PseudoVMFLE_VV_M1, VMFLE_VV }, // 6266 |
| 27537 | { PseudoVMFLE_VV_M1_MASK, VMFLE_VV }, // 6267 |
| 27538 | { PseudoVMFLE_VV_M2, VMFLE_VV }, // 6268 |
| 27539 | { PseudoVMFLE_VV_M2_MASK, VMFLE_VV }, // 6269 |
| 27540 | { PseudoVMFLE_VV_M4, VMFLE_VV }, // 6270 |
| 27541 | { PseudoVMFLE_VV_M4_MASK, VMFLE_VV }, // 6271 |
| 27542 | { PseudoVMFLE_VV_M8, VMFLE_VV }, // 6272 |
| 27543 | { PseudoVMFLE_VV_M8_MASK, VMFLE_VV }, // 6273 |
| 27544 | { PseudoVMFLE_VV_MF2, VMFLE_VV }, // 6274 |
| 27545 | { PseudoVMFLE_VV_MF2_MASK, VMFLE_VV }, // 6275 |
| 27546 | { PseudoVMFLE_VV_MF4, VMFLE_VV }, // 6276 |
| 27547 | { PseudoVMFLE_VV_MF4_MASK, VMFLE_VV }, // 6277 |
| 27548 | { PseudoVMFLT_VFPR16_M1, VMFLT_VF }, // 6278 |
| 27549 | { PseudoVMFLT_VFPR16_M1_MASK, VMFLT_VF }, // 6279 |
| 27550 | { PseudoVMFLT_VFPR16_M2, VMFLT_VF }, // 6280 |
| 27551 | { PseudoVMFLT_VFPR16_M2_MASK, VMFLT_VF }, // 6281 |
| 27552 | { PseudoVMFLT_VFPR16_M4, VMFLT_VF }, // 6282 |
| 27553 | { PseudoVMFLT_VFPR16_M4_MASK, VMFLT_VF }, // 6283 |
| 27554 | { PseudoVMFLT_VFPR16_M8, VMFLT_VF }, // 6284 |
| 27555 | { PseudoVMFLT_VFPR16_M8_MASK, VMFLT_VF }, // 6285 |
| 27556 | { PseudoVMFLT_VFPR16_MF2, VMFLT_VF }, // 6286 |
| 27557 | { PseudoVMFLT_VFPR16_MF2_MASK, VMFLT_VF }, // 6287 |
| 27558 | { PseudoVMFLT_VFPR16_MF4, VMFLT_VF }, // 6288 |
| 27559 | { PseudoVMFLT_VFPR16_MF4_MASK, VMFLT_VF }, // 6289 |
| 27560 | { PseudoVMFLT_VFPR32_M1, VMFLT_VF }, // 6290 |
| 27561 | { PseudoVMFLT_VFPR32_M1_MASK, VMFLT_VF }, // 6291 |
| 27562 | { PseudoVMFLT_VFPR32_M2, VMFLT_VF }, // 6292 |
| 27563 | { PseudoVMFLT_VFPR32_M2_MASK, VMFLT_VF }, // 6293 |
| 27564 | { PseudoVMFLT_VFPR32_M4, VMFLT_VF }, // 6294 |
| 27565 | { PseudoVMFLT_VFPR32_M4_MASK, VMFLT_VF }, // 6295 |
| 27566 | { PseudoVMFLT_VFPR32_M8, VMFLT_VF }, // 6296 |
| 27567 | { PseudoVMFLT_VFPR32_M8_MASK, VMFLT_VF }, // 6297 |
| 27568 | { PseudoVMFLT_VFPR32_MF2, VMFLT_VF }, // 6298 |
| 27569 | { PseudoVMFLT_VFPR32_MF2_MASK, VMFLT_VF }, // 6299 |
| 27570 | { PseudoVMFLT_VFPR64_M1, VMFLT_VF }, // 6300 |
| 27571 | { PseudoVMFLT_VFPR64_M1_MASK, VMFLT_VF }, // 6301 |
| 27572 | { PseudoVMFLT_VFPR64_M2, VMFLT_VF }, // 6302 |
| 27573 | { PseudoVMFLT_VFPR64_M2_MASK, VMFLT_VF }, // 6303 |
| 27574 | { PseudoVMFLT_VFPR64_M4, VMFLT_VF }, // 6304 |
| 27575 | { PseudoVMFLT_VFPR64_M4_MASK, VMFLT_VF }, // 6305 |
| 27576 | { PseudoVMFLT_VFPR64_M8, VMFLT_VF }, // 6306 |
| 27577 | { PseudoVMFLT_VFPR64_M8_MASK, VMFLT_VF }, // 6307 |
| 27578 | { PseudoVMFLT_VV_M1, VMFLT_VV }, // 6308 |
| 27579 | { PseudoVMFLT_VV_M1_MASK, VMFLT_VV }, // 6309 |
| 27580 | { PseudoVMFLT_VV_M2, VMFLT_VV }, // 6310 |
| 27581 | { PseudoVMFLT_VV_M2_MASK, VMFLT_VV }, // 6311 |
| 27582 | { PseudoVMFLT_VV_M4, VMFLT_VV }, // 6312 |
| 27583 | { PseudoVMFLT_VV_M4_MASK, VMFLT_VV }, // 6313 |
| 27584 | { PseudoVMFLT_VV_M8, VMFLT_VV }, // 6314 |
| 27585 | { PseudoVMFLT_VV_M8_MASK, VMFLT_VV }, // 6315 |
| 27586 | { PseudoVMFLT_VV_MF2, VMFLT_VV }, // 6316 |
| 27587 | { PseudoVMFLT_VV_MF2_MASK, VMFLT_VV }, // 6317 |
| 27588 | { PseudoVMFLT_VV_MF4, VMFLT_VV }, // 6318 |
| 27589 | { PseudoVMFLT_VV_MF4_MASK, VMFLT_VV }, // 6319 |
| 27590 | { PseudoVMFNE_VFPR16_M1, VMFNE_VF }, // 6320 |
| 27591 | { PseudoVMFNE_VFPR16_M1_MASK, VMFNE_VF }, // 6321 |
| 27592 | { PseudoVMFNE_VFPR16_M2, VMFNE_VF }, // 6322 |
| 27593 | { PseudoVMFNE_VFPR16_M2_MASK, VMFNE_VF }, // 6323 |
| 27594 | { PseudoVMFNE_VFPR16_M4, VMFNE_VF }, // 6324 |
| 27595 | { PseudoVMFNE_VFPR16_M4_MASK, VMFNE_VF }, // 6325 |
| 27596 | { PseudoVMFNE_VFPR16_M8, VMFNE_VF }, // 6326 |
| 27597 | { PseudoVMFNE_VFPR16_M8_MASK, VMFNE_VF }, // 6327 |
| 27598 | { PseudoVMFNE_VFPR16_MF2, VMFNE_VF }, // 6328 |
| 27599 | { PseudoVMFNE_VFPR16_MF2_MASK, VMFNE_VF }, // 6329 |
| 27600 | { PseudoVMFNE_VFPR16_MF4, VMFNE_VF }, // 6330 |
| 27601 | { PseudoVMFNE_VFPR16_MF4_MASK, VMFNE_VF }, // 6331 |
| 27602 | { PseudoVMFNE_VFPR32_M1, VMFNE_VF }, // 6332 |
| 27603 | { PseudoVMFNE_VFPR32_M1_MASK, VMFNE_VF }, // 6333 |
| 27604 | { PseudoVMFNE_VFPR32_M2, VMFNE_VF }, // 6334 |
| 27605 | { PseudoVMFNE_VFPR32_M2_MASK, VMFNE_VF }, // 6335 |
| 27606 | { PseudoVMFNE_VFPR32_M4, VMFNE_VF }, // 6336 |
| 27607 | { PseudoVMFNE_VFPR32_M4_MASK, VMFNE_VF }, // 6337 |
| 27608 | { PseudoVMFNE_VFPR32_M8, VMFNE_VF }, // 6338 |
| 27609 | { PseudoVMFNE_VFPR32_M8_MASK, VMFNE_VF }, // 6339 |
| 27610 | { PseudoVMFNE_VFPR32_MF2, VMFNE_VF }, // 6340 |
| 27611 | { PseudoVMFNE_VFPR32_MF2_MASK, VMFNE_VF }, // 6341 |
| 27612 | { PseudoVMFNE_VFPR64_M1, VMFNE_VF }, // 6342 |
| 27613 | { PseudoVMFNE_VFPR64_M1_MASK, VMFNE_VF }, // 6343 |
| 27614 | { PseudoVMFNE_VFPR64_M2, VMFNE_VF }, // 6344 |
| 27615 | { PseudoVMFNE_VFPR64_M2_MASK, VMFNE_VF }, // 6345 |
| 27616 | { PseudoVMFNE_VFPR64_M4, VMFNE_VF }, // 6346 |
| 27617 | { PseudoVMFNE_VFPR64_M4_MASK, VMFNE_VF }, // 6347 |
| 27618 | { PseudoVMFNE_VFPR64_M8, VMFNE_VF }, // 6348 |
| 27619 | { PseudoVMFNE_VFPR64_M8_MASK, VMFNE_VF }, // 6349 |
| 27620 | { PseudoVMFNE_VV_M1, VMFNE_VV }, // 6350 |
| 27621 | { PseudoVMFNE_VV_M1_MASK, VMFNE_VV }, // 6351 |
| 27622 | { PseudoVMFNE_VV_M2, VMFNE_VV }, // 6352 |
| 27623 | { PseudoVMFNE_VV_M2_MASK, VMFNE_VV }, // 6353 |
| 27624 | { PseudoVMFNE_VV_M4, VMFNE_VV }, // 6354 |
| 27625 | { PseudoVMFNE_VV_M4_MASK, VMFNE_VV }, // 6355 |
| 27626 | { PseudoVMFNE_VV_M8, VMFNE_VV }, // 6356 |
| 27627 | { PseudoVMFNE_VV_M8_MASK, VMFNE_VV }, // 6357 |
| 27628 | { PseudoVMFNE_VV_MF2, VMFNE_VV }, // 6358 |
| 27629 | { PseudoVMFNE_VV_MF2_MASK, VMFNE_VV }, // 6359 |
| 27630 | { PseudoVMFNE_VV_MF4, VMFNE_VV }, // 6360 |
| 27631 | { PseudoVMFNE_VV_MF4_MASK, VMFNE_VV }, // 6361 |
| 27632 | { PseudoVMINU_VV_M1, VMINU_VV }, // 6362 |
| 27633 | { PseudoVMINU_VV_M1_MASK, VMINU_VV }, // 6363 |
| 27634 | { PseudoVMINU_VV_M2, VMINU_VV }, // 6364 |
| 27635 | { PseudoVMINU_VV_M2_MASK, VMINU_VV }, // 6365 |
| 27636 | { PseudoVMINU_VV_M4, VMINU_VV }, // 6366 |
| 27637 | { PseudoVMINU_VV_M4_MASK, VMINU_VV }, // 6367 |
| 27638 | { PseudoVMINU_VV_M8, VMINU_VV }, // 6368 |
| 27639 | { PseudoVMINU_VV_M8_MASK, VMINU_VV }, // 6369 |
| 27640 | { PseudoVMINU_VV_MF2, VMINU_VV }, // 6370 |
| 27641 | { PseudoVMINU_VV_MF2_MASK, VMINU_VV }, // 6371 |
| 27642 | { PseudoVMINU_VV_MF4, VMINU_VV }, // 6372 |
| 27643 | { PseudoVMINU_VV_MF4_MASK, VMINU_VV }, // 6373 |
| 27644 | { PseudoVMINU_VV_MF8, VMINU_VV }, // 6374 |
| 27645 | { PseudoVMINU_VV_MF8_MASK, VMINU_VV }, // 6375 |
| 27646 | { PseudoVMINU_VX_M1, VMINU_VX }, // 6376 |
| 27647 | { PseudoVMINU_VX_M1_MASK, VMINU_VX }, // 6377 |
| 27648 | { PseudoVMINU_VX_M2, VMINU_VX }, // 6378 |
| 27649 | { PseudoVMINU_VX_M2_MASK, VMINU_VX }, // 6379 |
| 27650 | { PseudoVMINU_VX_M4, VMINU_VX }, // 6380 |
| 27651 | { PseudoVMINU_VX_M4_MASK, VMINU_VX }, // 6381 |
| 27652 | { PseudoVMINU_VX_M8, VMINU_VX }, // 6382 |
| 27653 | { PseudoVMINU_VX_M8_MASK, VMINU_VX }, // 6383 |
| 27654 | { PseudoVMINU_VX_MF2, VMINU_VX }, // 6384 |
| 27655 | { PseudoVMINU_VX_MF2_MASK, VMINU_VX }, // 6385 |
| 27656 | { PseudoVMINU_VX_MF4, VMINU_VX }, // 6386 |
| 27657 | { PseudoVMINU_VX_MF4_MASK, VMINU_VX }, // 6387 |
| 27658 | { PseudoVMINU_VX_MF8, VMINU_VX }, // 6388 |
| 27659 | { PseudoVMINU_VX_MF8_MASK, VMINU_VX }, // 6389 |
| 27660 | { PseudoVMIN_VV_M1, VMIN_VV }, // 6390 |
| 27661 | { PseudoVMIN_VV_M1_MASK, VMIN_VV }, // 6391 |
| 27662 | { PseudoVMIN_VV_M2, VMIN_VV }, // 6392 |
| 27663 | { PseudoVMIN_VV_M2_MASK, VMIN_VV }, // 6393 |
| 27664 | { PseudoVMIN_VV_M4, VMIN_VV }, // 6394 |
| 27665 | { PseudoVMIN_VV_M4_MASK, VMIN_VV }, // 6395 |
| 27666 | { PseudoVMIN_VV_M8, VMIN_VV }, // 6396 |
| 27667 | { PseudoVMIN_VV_M8_MASK, VMIN_VV }, // 6397 |
| 27668 | { PseudoVMIN_VV_MF2, VMIN_VV }, // 6398 |
| 27669 | { PseudoVMIN_VV_MF2_MASK, VMIN_VV }, // 6399 |
| 27670 | { PseudoVMIN_VV_MF4, VMIN_VV }, // 6400 |
| 27671 | { PseudoVMIN_VV_MF4_MASK, VMIN_VV }, // 6401 |
| 27672 | { PseudoVMIN_VV_MF8, VMIN_VV }, // 6402 |
| 27673 | { PseudoVMIN_VV_MF8_MASK, VMIN_VV }, // 6403 |
| 27674 | { PseudoVMIN_VX_M1, VMIN_VX }, // 6404 |
| 27675 | { PseudoVMIN_VX_M1_MASK, VMIN_VX }, // 6405 |
| 27676 | { PseudoVMIN_VX_M2, VMIN_VX }, // 6406 |
| 27677 | { PseudoVMIN_VX_M2_MASK, VMIN_VX }, // 6407 |
| 27678 | { PseudoVMIN_VX_M4, VMIN_VX }, // 6408 |
| 27679 | { PseudoVMIN_VX_M4_MASK, VMIN_VX }, // 6409 |
| 27680 | { PseudoVMIN_VX_M8, VMIN_VX }, // 6410 |
| 27681 | { PseudoVMIN_VX_M8_MASK, VMIN_VX }, // 6411 |
| 27682 | { PseudoVMIN_VX_MF2, VMIN_VX }, // 6412 |
| 27683 | { PseudoVMIN_VX_MF2_MASK, VMIN_VX }, // 6413 |
| 27684 | { PseudoVMIN_VX_MF4, VMIN_VX }, // 6414 |
| 27685 | { PseudoVMIN_VX_MF4_MASK, VMIN_VX }, // 6415 |
| 27686 | { PseudoVMIN_VX_MF8, VMIN_VX }, // 6416 |
| 27687 | { PseudoVMIN_VX_MF8_MASK, VMIN_VX }, // 6417 |
| 27688 | { PseudoVMNAND_MM_M1, VMNAND_MM }, // 6418 |
| 27689 | { PseudoVMNAND_MM_M2, VMNAND_MM }, // 6419 |
| 27690 | { PseudoVMNAND_MM_M4, VMNAND_MM }, // 6420 |
| 27691 | { PseudoVMNAND_MM_M8, VMNAND_MM }, // 6421 |
| 27692 | { PseudoVMNAND_MM_MF2, VMNAND_MM }, // 6422 |
| 27693 | { PseudoVMNAND_MM_MF4, VMNAND_MM }, // 6423 |
| 27694 | { PseudoVMNAND_MM_MF8, VMNAND_MM }, // 6424 |
| 27695 | { PseudoVMNOR_MM_M1, VMNOR_MM }, // 6425 |
| 27696 | { PseudoVMNOR_MM_M2, VMNOR_MM }, // 6426 |
| 27697 | { PseudoVMNOR_MM_M4, VMNOR_MM }, // 6427 |
| 27698 | { PseudoVMNOR_MM_M8, VMNOR_MM }, // 6428 |
| 27699 | { PseudoVMNOR_MM_MF2, VMNOR_MM }, // 6429 |
| 27700 | { PseudoVMNOR_MM_MF4, VMNOR_MM }, // 6430 |
| 27701 | { PseudoVMNOR_MM_MF8, VMNOR_MM }, // 6431 |
| 27702 | { PseudoVMORN_MM_M1, VMORN_MM }, // 6432 |
| 27703 | { PseudoVMORN_MM_M2, VMORN_MM }, // 6433 |
| 27704 | { PseudoVMORN_MM_M4, VMORN_MM }, // 6434 |
| 27705 | { PseudoVMORN_MM_M8, VMORN_MM }, // 6435 |
| 27706 | { PseudoVMORN_MM_MF2, VMORN_MM }, // 6436 |
| 27707 | { PseudoVMORN_MM_MF4, VMORN_MM }, // 6437 |
| 27708 | { PseudoVMORN_MM_MF8, VMORN_MM }, // 6438 |
| 27709 | { PseudoVMOR_MM_M1, VMOR_MM }, // 6439 |
| 27710 | { PseudoVMOR_MM_M2, VMOR_MM }, // 6440 |
| 27711 | { PseudoVMOR_MM_M4, VMOR_MM }, // 6441 |
| 27712 | { PseudoVMOR_MM_M8, VMOR_MM }, // 6442 |
| 27713 | { PseudoVMOR_MM_MF2, VMOR_MM }, // 6443 |
| 27714 | { PseudoVMOR_MM_MF4, VMOR_MM }, // 6444 |
| 27715 | { PseudoVMOR_MM_MF8, VMOR_MM }, // 6445 |
| 27716 | { PseudoVMSBC_VVM_M1, VMSBC_VVM }, // 6446 |
| 27717 | { PseudoVMSBC_VVM_M2, VMSBC_VVM }, // 6447 |
| 27718 | { PseudoVMSBC_VVM_M4, VMSBC_VVM }, // 6448 |
| 27719 | { PseudoVMSBC_VVM_M8, VMSBC_VVM }, // 6449 |
| 27720 | { PseudoVMSBC_VVM_MF2, VMSBC_VVM }, // 6450 |
| 27721 | { PseudoVMSBC_VVM_MF4, VMSBC_VVM }, // 6451 |
| 27722 | { PseudoVMSBC_VVM_MF8, VMSBC_VVM }, // 6452 |
| 27723 | { PseudoVMSBC_VV_M1, VMSBC_VV }, // 6453 |
| 27724 | { PseudoVMSBC_VV_M2, VMSBC_VV }, // 6454 |
| 27725 | { PseudoVMSBC_VV_M4, VMSBC_VV }, // 6455 |
| 27726 | { PseudoVMSBC_VV_M8, VMSBC_VV }, // 6456 |
| 27727 | { PseudoVMSBC_VV_MF2, VMSBC_VV }, // 6457 |
| 27728 | { PseudoVMSBC_VV_MF4, VMSBC_VV }, // 6458 |
| 27729 | { PseudoVMSBC_VV_MF8, VMSBC_VV }, // 6459 |
| 27730 | { PseudoVMSBC_VXM_M1, VMSBC_VXM }, // 6460 |
| 27731 | { PseudoVMSBC_VXM_M2, VMSBC_VXM }, // 6461 |
| 27732 | { PseudoVMSBC_VXM_M4, VMSBC_VXM }, // 6462 |
| 27733 | { PseudoVMSBC_VXM_M8, VMSBC_VXM }, // 6463 |
| 27734 | { PseudoVMSBC_VXM_MF2, VMSBC_VXM }, // 6464 |
| 27735 | { PseudoVMSBC_VXM_MF4, VMSBC_VXM }, // 6465 |
| 27736 | { PseudoVMSBC_VXM_MF8, VMSBC_VXM }, // 6466 |
| 27737 | { PseudoVMSBC_VX_M1, VMSBC_VX }, // 6467 |
| 27738 | { PseudoVMSBC_VX_M2, VMSBC_VX }, // 6468 |
| 27739 | { PseudoVMSBC_VX_M4, VMSBC_VX }, // 6469 |
| 27740 | { PseudoVMSBC_VX_M8, VMSBC_VX }, // 6470 |
| 27741 | { PseudoVMSBC_VX_MF2, VMSBC_VX }, // 6471 |
| 27742 | { PseudoVMSBC_VX_MF4, VMSBC_VX }, // 6472 |
| 27743 | { PseudoVMSBC_VX_MF8, VMSBC_VX }, // 6473 |
| 27744 | { PseudoVMSBF_M_B1, VMSBF_M }, // 6474 |
| 27745 | { PseudoVMSBF_M_B16, VMSBF_M }, // 6475 |
| 27746 | { PseudoVMSBF_M_B16_MASK, VMSBF_M }, // 6476 |
| 27747 | { PseudoVMSBF_M_B1_MASK, VMSBF_M }, // 6477 |
| 27748 | { PseudoVMSBF_M_B2, VMSBF_M }, // 6478 |
| 27749 | { PseudoVMSBF_M_B2_MASK, VMSBF_M }, // 6479 |
| 27750 | { PseudoVMSBF_M_B32, VMSBF_M }, // 6480 |
| 27751 | { PseudoVMSBF_M_B32_MASK, VMSBF_M }, // 6481 |
| 27752 | { PseudoVMSBF_M_B4, VMSBF_M }, // 6482 |
| 27753 | { PseudoVMSBF_M_B4_MASK, VMSBF_M }, // 6483 |
| 27754 | { PseudoVMSBF_M_B64, VMSBF_M }, // 6484 |
| 27755 | { PseudoVMSBF_M_B64_MASK, VMSBF_M }, // 6485 |
| 27756 | { PseudoVMSBF_M_B8, VMSBF_M }, // 6486 |
| 27757 | { PseudoVMSBF_M_B8_MASK, VMSBF_M }, // 6487 |
| 27758 | { PseudoVMSEQ_VI_M1, VMSEQ_VI }, // 6488 |
| 27759 | { PseudoVMSEQ_VI_M1_MASK, VMSEQ_VI }, // 6489 |
| 27760 | { PseudoVMSEQ_VI_M2, VMSEQ_VI }, // 6490 |
| 27761 | { PseudoVMSEQ_VI_M2_MASK, VMSEQ_VI }, // 6491 |
| 27762 | { PseudoVMSEQ_VI_M4, VMSEQ_VI }, // 6492 |
| 27763 | { PseudoVMSEQ_VI_M4_MASK, VMSEQ_VI }, // 6493 |
| 27764 | { PseudoVMSEQ_VI_M8, VMSEQ_VI }, // 6494 |
| 27765 | { PseudoVMSEQ_VI_M8_MASK, VMSEQ_VI }, // 6495 |
| 27766 | { PseudoVMSEQ_VI_MF2, VMSEQ_VI }, // 6496 |
| 27767 | { PseudoVMSEQ_VI_MF2_MASK, VMSEQ_VI }, // 6497 |
| 27768 | { PseudoVMSEQ_VI_MF4, VMSEQ_VI }, // 6498 |
| 27769 | { PseudoVMSEQ_VI_MF4_MASK, VMSEQ_VI }, // 6499 |
| 27770 | { PseudoVMSEQ_VI_MF8, VMSEQ_VI }, // 6500 |
| 27771 | { PseudoVMSEQ_VI_MF8_MASK, VMSEQ_VI }, // 6501 |
| 27772 | { PseudoVMSEQ_VV_M1, VMSEQ_VV }, // 6502 |
| 27773 | { PseudoVMSEQ_VV_M1_MASK, VMSEQ_VV }, // 6503 |
| 27774 | { PseudoVMSEQ_VV_M2, VMSEQ_VV }, // 6504 |
| 27775 | { PseudoVMSEQ_VV_M2_MASK, VMSEQ_VV }, // 6505 |
| 27776 | { PseudoVMSEQ_VV_M4, VMSEQ_VV }, // 6506 |
| 27777 | { PseudoVMSEQ_VV_M4_MASK, VMSEQ_VV }, // 6507 |
| 27778 | { PseudoVMSEQ_VV_M8, VMSEQ_VV }, // 6508 |
| 27779 | { PseudoVMSEQ_VV_M8_MASK, VMSEQ_VV }, // 6509 |
| 27780 | { PseudoVMSEQ_VV_MF2, VMSEQ_VV }, // 6510 |
| 27781 | { PseudoVMSEQ_VV_MF2_MASK, VMSEQ_VV }, // 6511 |
| 27782 | { PseudoVMSEQ_VV_MF4, VMSEQ_VV }, // 6512 |
| 27783 | { PseudoVMSEQ_VV_MF4_MASK, VMSEQ_VV }, // 6513 |
| 27784 | { PseudoVMSEQ_VV_MF8, VMSEQ_VV }, // 6514 |
| 27785 | { PseudoVMSEQ_VV_MF8_MASK, VMSEQ_VV }, // 6515 |
| 27786 | { PseudoVMSEQ_VX_M1, VMSEQ_VX }, // 6516 |
| 27787 | { PseudoVMSEQ_VX_M1_MASK, VMSEQ_VX }, // 6517 |
| 27788 | { PseudoVMSEQ_VX_M2, VMSEQ_VX }, // 6518 |
| 27789 | { PseudoVMSEQ_VX_M2_MASK, VMSEQ_VX }, // 6519 |
| 27790 | { PseudoVMSEQ_VX_M4, VMSEQ_VX }, // 6520 |
| 27791 | { PseudoVMSEQ_VX_M4_MASK, VMSEQ_VX }, // 6521 |
| 27792 | { PseudoVMSEQ_VX_M8, VMSEQ_VX }, // 6522 |
| 27793 | { PseudoVMSEQ_VX_M8_MASK, VMSEQ_VX }, // 6523 |
| 27794 | { PseudoVMSEQ_VX_MF2, VMSEQ_VX }, // 6524 |
| 27795 | { PseudoVMSEQ_VX_MF2_MASK, VMSEQ_VX }, // 6525 |
| 27796 | { PseudoVMSEQ_VX_MF4, VMSEQ_VX }, // 6526 |
| 27797 | { PseudoVMSEQ_VX_MF4_MASK, VMSEQ_VX }, // 6527 |
| 27798 | { PseudoVMSEQ_VX_MF8, VMSEQ_VX }, // 6528 |
| 27799 | { PseudoVMSEQ_VX_MF8_MASK, VMSEQ_VX }, // 6529 |
| 27800 | { PseudoVMSGTU_VI_M1, VMSGTU_VI }, // 6530 |
| 27801 | { PseudoVMSGTU_VI_M1_MASK, VMSGTU_VI }, // 6531 |
| 27802 | { PseudoVMSGTU_VI_M2, VMSGTU_VI }, // 6532 |
| 27803 | { PseudoVMSGTU_VI_M2_MASK, VMSGTU_VI }, // 6533 |
| 27804 | { PseudoVMSGTU_VI_M4, VMSGTU_VI }, // 6534 |
| 27805 | { PseudoVMSGTU_VI_M4_MASK, VMSGTU_VI }, // 6535 |
| 27806 | { PseudoVMSGTU_VI_M8, VMSGTU_VI }, // 6536 |
| 27807 | { PseudoVMSGTU_VI_M8_MASK, VMSGTU_VI }, // 6537 |
| 27808 | { PseudoVMSGTU_VI_MF2, VMSGTU_VI }, // 6538 |
| 27809 | { PseudoVMSGTU_VI_MF2_MASK, VMSGTU_VI }, // 6539 |
| 27810 | { PseudoVMSGTU_VI_MF4, VMSGTU_VI }, // 6540 |
| 27811 | { PseudoVMSGTU_VI_MF4_MASK, VMSGTU_VI }, // 6541 |
| 27812 | { PseudoVMSGTU_VI_MF8, VMSGTU_VI }, // 6542 |
| 27813 | { PseudoVMSGTU_VI_MF8_MASK, VMSGTU_VI }, // 6543 |
| 27814 | { PseudoVMSGTU_VX_M1, VMSGTU_VX }, // 6544 |
| 27815 | { PseudoVMSGTU_VX_M1_MASK, VMSGTU_VX }, // 6545 |
| 27816 | { PseudoVMSGTU_VX_M2, VMSGTU_VX }, // 6546 |
| 27817 | { PseudoVMSGTU_VX_M2_MASK, VMSGTU_VX }, // 6547 |
| 27818 | { PseudoVMSGTU_VX_M4, VMSGTU_VX }, // 6548 |
| 27819 | { PseudoVMSGTU_VX_M4_MASK, VMSGTU_VX }, // 6549 |
| 27820 | { PseudoVMSGTU_VX_M8, VMSGTU_VX }, // 6550 |
| 27821 | { PseudoVMSGTU_VX_M8_MASK, VMSGTU_VX }, // 6551 |
| 27822 | { PseudoVMSGTU_VX_MF2, VMSGTU_VX }, // 6552 |
| 27823 | { PseudoVMSGTU_VX_MF2_MASK, VMSGTU_VX }, // 6553 |
| 27824 | { PseudoVMSGTU_VX_MF4, VMSGTU_VX }, // 6554 |
| 27825 | { PseudoVMSGTU_VX_MF4_MASK, VMSGTU_VX }, // 6555 |
| 27826 | { PseudoVMSGTU_VX_MF8, VMSGTU_VX }, // 6556 |
| 27827 | { PseudoVMSGTU_VX_MF8_MASK, VMSGTU_VX }, // 6557 |
| 27828 | { PseudoVMSGT_VI_M1, VMSGT_VI }, // 6558 |
| 27829 | { PseudoVMSGT_VI_M1_MASK, VMSGT_VI }, // 6559 |
| 27830 | { PseudoVMSGT_VI_M2, VMSGT_VI }, // 6560 |
| 27831 | { PseudoVMSGT_VI_M2_MASK, VMSGT_VI }, // 6561 |
| 27832 | { PseudoVMSGT_VI_M4, VMSGT_VI }, // 6562 |
| 27833 | { PseudoVMSGT_VI_M4_MASK, VMSGT_VI }, // 6563 |
| 27834 | { PseudoVMSGT_VI_M8, VMSGT_VI }, // 6564 |
| 27835 | { PseudoVMSGT_VI_M8_MASK, VMSGT_VI }, // 6565 |
| 27836 | { PseudoVMSGT_VI_MF2, VMSGT_VI }, // 6566 |
| 27837 | { PseudoVMSGT_VI_MF2_MASK, VMSGT_VI }, // 6567 |
| 27838 | { PseudoVMSGT_VI_MF4, VMSGT_VI }, // 6568 |
| 27839 | { PseudoVMSGT_VI_MF4_MASK, VMSGT_VI }, // 6569 |
| 27840 | { PseudoVMSGT_VI_MF8, VMSGT_VI }, // 6570 |
| 27841 | { PseudoVMSGT_VI_MF8_MASK, VMSGT_VI }, // 6571 |
| 27842 | { PseudoVMSGT_VX_M1, VMSGT_VX }, // 6572 |
| 27843 | { PseudoVMSGT_VX_M1_MASK, VMSGT_VX }, // 6573 |
| 27844 | { PseudoVMSGT_VX_M2, VMSGT_VX }, // 6574 |
| 27845 | { PseudoVMSGT_VX_M2_MASK, VMSGT_VX }, // 6575 |
| 27846 | { PseudoVMSGT_VX_M4, VMSGT_VX }, // 6576 |
| 27847 | { PseudoVMSGT_VX_M4_MASK, VMSGT_VX }, // 6577 |
| 27848 | { PseudoVMSGT_VX_M8, VMSGT_VX }, // 6578 |
| 27849 | { PseudoVMSGT_VX_M8_MASK, VMSGT_VX }, // 6579 |
| 27850 | { PseudoVMSGT_VX_MF2, VMSGT_VX }, // 6580 |
| 27851 | { PseudoVMSGT_VX_MF2_MASK, VMSGT_VX }, // 6581 |
| 27852 | { PseudoVMSGT_VX_MF4, VMSGT_VX }, // 6582 |
| 27853 | { PseudoVMSGT_VX_MF4_MASK, VMSGT_VX }, // 6583 |
| 27854 | { PseudoVMSGT_VX_MF8, VMSGT_VX }, // 6584 |
| 27855 | { PseudoVMSGT_VX_MF8_MASK, VMSGT_VX }, // 6585 |
| 27856 | { PseudoVMSIF_M_B1, VMSIF_M }, // 6586 |
| 27857 | { PseudoVMSIF_M_B16, VMSIF_M }, // 6587 |
| 27858 | { PseudoVMSIF_M_B16_MASK, VMSIF_M }, // 6588 |
| 27859 | { PseudoVMSIF_M_B1_MASK, VMSIF_M }, // 6589 |
| 27860 | { PseudoVMSIF_M_B2, VMSIF_M }, // 6590 |
| 27861 | { PseudoVMSIF_M_B2_MASK, VMSIF_M }, // 6591 |
| 27862 | { PseudoVMSIF_M_B32, VMSIF_M }, // 6592 |
| 27863 | { PseudoVMSIF_M_B32_MASK, VMSIF_M }, // 6593 |
| 27864 | { PseudoVMSIF_M_B4, VMSIF_M }, // 6594 |
| 27865 | { PseudoVMSIF_M_B4_MASK, VMSIF_M }, // 6595 |
| 27866 | { PseudoVMSIF_M_B64, VMSIF_M }, // 6596 |
| 27867 | { PseudoVMSIF_M_B64_MASK, VMSIF_M }, // 6597 |
| 27868 | { PseudoVMSIF_M_B8, VMSIF_M }, // 6598 |
| 27869 | { PseudoVMSIF_M_B8_MASK, VMSIF_M }, // 6599 |
| 27870 | { PseudoVMSLEU_VI_M1, VMSLEU_VI }, // 6600 |
| 27871 | { PseudoVMSLEU_VI_M1_MASK, VMSLEU_VI }, // 6601 |
| 27872 | { PseudoVMSLEU_VI_M2, VMSLEU_VI }, // 6602 |
| 27873 | { PseudoVMSLEU_VI_M2_MASK, VMSLEU_VI }, // 6603 |
| 27874 | { PseudoVMSLEU_VI_M4, VMSLEU_VI }, // 6604 |
| 27875 | { PseudoVMSLEU_VI_M4_MASK, VMSLEU_VI }, // 6605 |
| 27876 | { PseudoVMSLEU_VI_M8, VMSLEU_VI }, // 6606 |
| 27877 | { PseudoVMSLEU_VI_M8_MASK, VMSLEU_VI }, // 6607 |
| 27878 | { PseudoVMSLEU_VI_MF2, VMSLEU_VI }, // 6608 |
| 27879 | { PseudoVMSLEU_VI_MF2_MASK, VMSLEU_VI }, // 6609 |
| 27880 | { PseudoVMSLEU_VI_MF4, VMSLEU_VI }, // 6610 |
| 27881 | { PseudoVMSLEU_VI_MF4_MASK, VMSLEU_VI }, // 6611 |
| 27882 | { PseudoVMSLEU_VI_MF8, VMSLEU_VI }, // 6612 |
| 27883 | { PseudoVMSLEU_VI_MF8_MASK, VMSLEU_VI }, // 6613 |
| 27884 | { PseudoVMSLEU_VV_M1, VMSLEU_VV }, // 6614 |
| 27885 | { PseudoVMSLEU_VV_M1_MASK, VMSLEU_VV }, // 6615 |
| 27886 | { PseudoVMSLEU_VV_M2, VMSLEU_VV }, // 6616 |
| 27887 | { PseudoVMSLEU_VV_M2_MASK, VMSLEU_VV }, // 6617 |
| 27888 | { PseudoVMSLEU_VV_M4, VMSLEU_VV }, // 6618 |
| 27889 | { PseudoVMSLEU_VV_M4_MASK, VMSLEU_VV }, // 6619 |
| 27890 | { PseudoVMSLEU_VV_M8, VMSLEU_VV }, // 6620 |
| 27891 | { PseudoVMSLEU_VV_M8_MASK, VMSLEU_VV }, // 6621 |
| 27892 | { PseudoVMSLEU_VV_MF2, VMSLEU_VV }, // 6622 |
| 27893 | { PseudoVMSLEU_VV_MF2_MASK, VMSLEU_VV }, // 6623 |
| 27894 | { PseudoVMSLEU_VV_MF4, VMSLEU_VV }, // 6624 |
| 27895 | { PseudoVMSLEU_VV_MF4_MASK, VMSLEU_VV }, // 6625 |
| 27896 | { PseudoVMSLEU_VV_MF8, VMSLEU_VV }, // 6626 |
| 27897 | { PseudoVMSLEU_VV_MF8_MASK, VMSLEU_VV }, // 6627 |
| 27898 | { PseudoVMSLEU_VX_M1, VMSLEU_VX }, // 6628 |
| 27899 | { PseudoVMSLEU_VX_M1_MASK, VMSLEU_VX }, // 6629 |
| 27900 | { PseudoVMSLEU_VX_M2, VMSLEU_VX }, // 6630 |
| 27901 | { PseudoVMSLEU_VX_M2_MASK, VMSLEU_VX }, // 6631 |
| 27902 | { PseudoVMSLEU_VX_M4, VMSLEU_VX }, // 6632 |
| 27903 | { PseudoVMSLEU_VX_M4_MASK, VMSLEU_VX }, // 6633 |
| 27904 | { PseudoVMSLEU_VX_M8, VMSLEU_VX }, // 6634 |
| 27905 | { PseudoVMSLEU_VX_M8_MASK, VMSLEU_VX }, // 6635 |
| 27906 | { PseudoVMSLEU_VX_MF2, VMSLEU_VX }, // 6636 |
| 27907 | { PseudoVMSLEU_VX_MF2_MASK, VMSLEU_VX }, // 6637 |
| 27908 | { PseudoVMSLEU_VX_MF4, VMSLEU_VX }, // 6638 |
| 27909 | { PseudoVMSLEU_VX_MF4_MASK, VMSLEU_VX }, // 6639 |
| 27910 | { PseudoVMSLEU_VX_MF8, VMSLEU_VX }, // 6640 |
| 27911 | { PseudoVMSLEU_VX_MF8_MASK, VMSLEU_VX }, // 6641 |
| 27912 | { PseudoVMSLE_VI_M1, VMSLE_VI }, // 6642 |
| 27913 | { PseudoVMSLE_VI_M1_MASK, VMSLE_VI }, // 6643 |
| 27914 | { PseudoVMSLE_VI_M2, VMSLE_VI }, // 6644 |
| 27915 | { PseudoVMSLE_VI_M2_MASK, VMSLE_VI }, // 6645 |
| 27916 | { PseudoVMSLE_VI_M4, VMSLE_VI }, // 6646 |
| 27917 | { PseudoVMSLE_VI_M4_MASK, VMSLE_VI }, // 6647 |
| 27918 | { PseudoVMSLE_VI_M8, VMSLE_VI }, // 6648 |
| 27919 | { PseudoVMSLE_VI_M8_MASK, VMSLE_VI }, // 6649 |
| 27920 | { PseudoVMSLE_VI_MF2, VMSLE_VI }, // 6650 |
| 27921 | { PseudoVMSLE_VI_MF2_MASK, VMSLE_VI }, // 6651 |
| 27922 | { PseudoVMSLE_VI_MF4, VMSLE_VI }, // 6652 |
| 27923 | { PseudoVMSLE_VI_MF4_MASK, VMSLE_VI }, // 6653 |
| 27924 | { PseudoVMSLE_VI_MF8, VMSLE_VI }, // 6654 |
| 27925 | { PseudoVMSLE_VI_MF8_MASK, VMSLE_VI }, // 6655 |
| 27926 | { PseudoVMSLE_VV_M1, VMSLE_VV }, // 6656 |
| 27927 | { PseudoVMSLE_VV_M1_MASK, VMSLE_VV }, // 6657 |
| 27928 | { PseudoVMSLE_VV_M2, VMSLE_VV }, // 6658 |
| 27929 | { PseudoVMSLE_VV_M2_MASK, VMSLE_VV }, // 6659 |
| 27930 | { PseudoVMSLE_VV_M4, VMSLE_VV }, // 6660 |
| 27931 | { PseudoVMSLE_VV_M4_MASK, VMSLE_VV }, // 6661 |
| 27932 | { PseudoVMSLE_VV_M8, VMSLE_VV }, // 6662 |
| 27933 | { PseudoVMSLE_VV_M8_MASK, VMSLE_VV }, // 6663 |
| 27934 | { PseudoVMSLE_VV_MF2, VMSLE_VV }, // 6664 |
| 27935 | { PseudoVMSLE_VV_MF2_MASK, VMSLE_VV }, // 6665 |
| 27936 | { PseudoVMSLE_VV_MF4, VMSLE_VV }, // 6666 |
| 27937 | { PseudoVMSLE_VV_MF4_MASK, VMSLE_VV }, // 6667 |
| 27938 | { PseudoVMSLE_VV_MF8, VMSLE_VV }, // 6668 |
| 27939 | { PseudoVMSLE_VV_MF8_MASK, VMSLE_VV }, // 6669 |
| 27940 | { PseudoVMSLE_VX_M1, VMSLE_VX }, // 6670 |
| 27941 | { PseudoVMSLE_VX_M1_MASK, VMSLE_VX }, // 6671 |
| 27942 | { PseudoVMSLE_VX_M2, VMSLE_VX }, // 6672 |
| 27943 | { PseudoVMSLE_VX_M2_MASK, VMSLE_VX }, // 6673 |
| 27944 | { PseudoVMSLE_VX_M4, VMSLE_VX }, // 6674 |
| 27945 | { PseudoVMSLE_VX_M4_MASK, VMSLE_VX }, // 6675 |
| 27946 | { PseudoVMSLE_VX_M8, VMSLE_VX }, // 6676 |
| 27947 | { PseudoVMSLE_VX_M8_MASK, VMSLE_VX }, // 6677 |
| 27948 | { PseudoVMSLE_VX_MF2, VMSLE_VX }, // 6678 |
| 27949 | { PseudoVMSLE_VX_MF2_MASK, VMSLE_VX }, // 6679 |
| 27950 | { PseudoVMSLE_VX_MF4, VMSLE_VX }, // 6680 |
| 27951 | { PseudoVMSLE_VX_MF4_MASK, VMSLE_VX }, // 6681 |
| 27952 | { PseudoVMSLE_VX_MF8, VMSLE_VX }, // 6682 |
| 27953 | { PseudoVMSLE_VX_MF8_MASK, VMSLE_VX }, // 6683 |
| 27954 | { PseudoVMSLTU_VV_M1, VMSLTU_VV }, // 6684 |
| 27955 | { PseudoVMSLTU_VV_M1_MASK, VMSLTU_VV }, // 6685 |
| 27956 | { PseudoVMSLTU_VV_M2, VMSLTU_VV }, // 6686 |
| 27957 | { PseudoVMSLTU_VV_M2_MASK, VMSLTU_VV }, // 6687 |
| 27958 | { PseudoVMSLTU_VV_M4, VMSLTU_VV }, // 6688 |
| 27959 | { PseudoVMSLTU_VV_M4_MASK, VMSLTU_VV }, // 6689 |
| 27960 | { PseudoVMSLTU_VV_M8, VMSLTU_VV }, // 6690 |
| 27961 | { PseudoVMSLTU_VV_M8_MASK, VMSLTU_VV }, // 6691 |
| 27962 | { PseudoVMSLTU_VV_MF2, VMSLTU_VV }, // 6692 |
| 27963 | { PseudoVMSLTU_VV_MF2_MASK, VMSLTU_VV }, // 6693 |
| 27964 | { PseudoVMSLTU_VV_MF4, VMSLTU_VV }, // 6694 |
| 27965 | { PseudoVMSLTU_VV_MF4_MASK, VMSLTU_VV }, // 6695 |
| 27966 | { PseudoVMSLTU_VV_MF8, VMSLTU_VV }, // 6696 |
| 27967 | { PseudoVMSLTU_VV_MF8_MASK, VMSLTU_VV }, // 6697 |
| 27968 | { PseudoVMSLTU_VX_M1, VMSLTU_VX }, // 6698 |
| 27969 | { PseudoVMSLTU_VX_M1_MASK, VMSLTU_VX }, // 6699 |
| 27970 | { PseudoVMSLTU_VX_M2, VMSLTU_VX }, // 6700 |
| 27971 | { PseudoVMSLTU_VX_M2_MASK, VMSLTU_VX }, // 6701 |
| 27972 | { PseudoVMSLTU_VX_M4, VMSLTU_VX }, // 6702 |
| 27973 | { PseudoVMSLTU_VX_M4_MASK, VMSLTU_VX }, // 6703 |
| 27974 | { PseudoVMSLTU_VX_M8, VMSLTU_VX }, // 6704 |
| 27975 | { PseudoVMSLTU_VX_M8_MASK, VMSLTU_VX }, // 6705 |
| 27976 | { PseudoVMSLTU_VX_MF2, VMSLTU_VX }, // 6706 |
| 27977 | { PseudoVMSLTU_VX_MF2_MASK, VMSLTU_VX }, // 6707 |
| 27978 | { PseudoVMSLTU_VX_MF4, VMSLTU_VX }, // 6708 |
| 27979 | { PseudoVMSLTU_VX_MF4_MASK, VMSLTU_VX }, // 6709 |
| 27980 | { PseudoVMSLTU_VX_MF8, VMSLTU_VX }, // 6710 |
| 27981 | { PseudoVMSLTU_VX_MF8_MASK, VMSLTU_VX }, // 6711 |
| 27982 | { PseudoVMSLT_VV_M1, VMSLT_VV }, // 6712 |
| 27983 | { PseudoVMSLT_VV_M1_MASK, VMSLT_VV }, // 6713 |
| 27984 | { PseudoVMSLT_VV_M2, VMSLT_VV }, // 6714 |
| 27985 | { PseudoVMSLT_VV_M2_MASK, VMSLT_VV }, // 6715 |
| 27986 | { PseudoVMSLT_VV_M4, VMSLT_VV }, // 6716 |
| 27987 | { PseudoVMSLT_VV_M4_MASK, VMSLT_VV }, // 6717 |
| 27988 | { PseudoVMSLT_VV_M8, VMSLT_VV }, // 6718 |
| 27989 | { PseudoVMSLT_VV_M8_MASK, VMSLT_VV }, // 6719 |
| 27990 | { PseudoVMSLT_VV_MF2, VMSLT_VV }, // 6720 |
| 27991 | { PseudoVMSLT_VV_MF2_MASK, VMSLT_VV }, // 6721 |
| 27992 | { PseudoVMSLT_VV_MF4, VMSLT_VV }, // 6722 |
| 27993 | { PseudoVMSLT_VV_MF4_MASK, VMSLT_VV }, // 6723 |
| 27994 | { PseudoVMSLT_VV_MF8, VMSLT_VV }, // 6724 |
| 27995 | { PseudoVMSLT_VV_MF8_MASK, VMSLT_VV }, // 6725 |
| 27996 | { PseudoVMSLT_VX_M1, VMSLT_VX }, // 6726 |
| 27997 | { PseudoVMSLT_VX_M1_MASK, VMSLT_VX }, // 6727 |
| 27998 | { PseudoVMSLT_VX_M2, VMSLT_VX }, // 6728 |
| 27999 | { PseudoVMSLT_VX_M2_MASK, VMSLT_VX }, // 6729 |
| 28000 | { PseudoVMSLT_VX_M4, VMSLT_VX }, // 6730 |
| 28001 | { PseudoVMSLT_VX_M4_MASK, VMSLT_VX }, // 6731 |
| 28002 | { PseudoVMSLT_VX_M8, VMSLT_VX }, // 6732 |
| 28003 | { PseudoVMSLT_VX_M8_MASK, VMSLT_VX }, // 6733 |
| 28004 | { PseudoVMSLT_VX_MF2, VMSLT_VX }, // 6734 |
| 28005 | { PseudoVMSLT_VX_MF2_MASK, VMSLT_VX }, // 6735 |
| 28006 | { PseudoVMSLT_VX_MF4, VMSLT_VX }, // 6736 |
| 28007 | { PseudoVMSLT_VX_MF4_MASK, VMSLT_VX }, // 6737 |
| 28008 | { PseudoVMSLT_VX_MF8, VMSLT_VX }, // 6738 |
| 28009 | { PseudoVMSLT_VX_MF8_MASK, VMSLT_VX }, // 6739 |
| 28010 | { PseudoVMSNE_VI_M1, VMSNE_VI }, // 6740 |
| 28011 | { PseudoVMSNE_VI_M1_MASK, VMSNE_VI }, // 6741 |
| 28012 | { PseudoVMSNE_VI_M2, VMSNE_VI }, // 6742 |
| 28013 | { PseudoVMSNE_VI_M2_MASK, VMSNE_VI }, // 6743 |
| 28014 | { PseudoVMSNE_VI_M4, VMSNE_VI }, // 6744 |
| 28015 | { PseudoVMSNE_VI_M4_MASK, VMSNE_VI }, // 6745 |
| 28016 | { PseudoVMSNE_VI_M8, VMSNE_VI }, // 6746 |
| 28017 | { PseudoVMSNE_VI_M8_MASK, VMSNE_VI }, // 6747 |
| 28018 | { PseudoVMSNE_VI_MF2, VMSNE_VI }, // 6748 |
| 28019 | { PseudoVMSNE_VI_MF2_MASK, VMSNE_VI }, // 6749 |
| 28020 | { PseudoVMSNE_VI_MF4, VMSNE_VI }, // 6750 |
| 28021 | { PseudoVMSNE_VI_MF4_MASK, VMSNE_VI }, // 6751 |
| 28022 | { PseudoVMSNE_VI_MF8, VMSNE_VI }, // 6752 |
| 28023 | { PseudoVMSNE_VI_MF8_MASK, VMSNE_VI }, // 6753 |
| 28024 | { PseudoVMSNE_VV_M1, VMSNE_VV }, // 6754 |
| 28025 | { PseudoVMSNE_VV_M1_MASK, VMSNE_VV }, // 6755 |
| 28026 | { PseudoVMSNE_VV_M2, VMSNE_VV }, // 6756 |
| 28027 | { PseudoVMSNE_VV_M2_MASK, VMSNE_VV }, // 6757 |
| 28028 | { PseudoVMSNE_VV_M4, VMSNE_VV }, // 6758 |
| 28029 | { PseudoVMSNE_VV_M4_MASK, VMSNE_VV }, // 6759 |
| 28030 | { PseudoVMSNE_VV_M8, VMSNE_VV }, // 6760 |
| 28031 | { PseudoVMSNE_VV_M8_MASK, VMSNE_VV }, // 6761 |
| 28032 | { PseudoVMSNE_VV_MF2, VMSNE_VV }, // 6762 |
| 28033 | { PseudoVMSNE_VV_MF2_MASK, VMSNE_VV }, // 6763 |
| 28034 | { PseudoVMSNE_VV_MF4, VMSNE_VV }, // 6764 |
| 28035 | { PseudoVMSNE_VV_MF4_MASK, VMSNE_VV }, // 6765 |
| 28036 | { PseudoVMSNE_VV_MF8, VMSNE_VV }, // 6766 |
| 28037 | { PseudoVMSNE_VV_MF8_MASK, VMSNE_VV }, // 6767 |
| 28038 | { PseudoVMSNE_VX_M1, VMSNE_VX }, // 6768 |
| 28039 | { PseudoVMSNE_VX_M1_MASK, VMSNE_VX }, // 6769 |
| 28040 | { PseudoVMSNE_VX_M2, VMSNE_VX }, // 6770 |
| 28041 | { PseudoVMSNE_VX_M2_MASK, VMSNE_VX }, // 6771 |
| 28042 | { PseudoVMSNE_VX_M4, VMSNE_VX }, // 6772 |
| 28043 | { PseudoVMSNE_VX_M4_MASK, VMSNE_VX }, // 6773 |
| 28044 | { PseudoVMSNE_VX_M8, VMSNE_VX }, // 6774 |
| 28045 | { PseudoVMSNE_VX_M8_MASK, VMSNE_VX }, // 6775 |
| 28046 | { PseudoVMSNE_VX_MF2, VMSNE_VX }, // 6776 |
| 28047 | { PseudoVMSNE_VX_MF2_MASK, VMSNE_VX }, // 6777 |
| 28048 | { PseudoVMSNE_VX_MF4, VMSNE_VX }, // 6778 |
| 28049 | { PseudoVMSNE_VX_MF4_MASK, VMSNE_VX }, // 6779 |
| 28050 | { PseudoVMSNE_VX_MF8, VMSNE_VX }, // 6780 |
| 28051 | { PseudoVMSNE_VX_MF8_MASK, VMSNE_VX }, // 6781 |
| 28052 | { PseudoVMSOF_M_B1, VMSOF_M }, // 6782 |
| 28053 | { PseudoVMSOF_M_B16, VMSOF_M }, // 6783 |
| 28054 | { PseudoVMSOF_M_B16_MASK, VMSOF_M }, // 6784 |
| 28055 | { PseudoVMSOF_M_B1_MASK, VMSOF_M }, // 6785 |
| 28056 | { PseudoVMSOF_M_B2, VMSOF_M }, // 6786 |
| 28057 | { PseudoVMSOF_M_B2_MASK, VMSOF_M }, // 6787 |
| 28058 | { PseudoVMSOF_M_B32, VMSOF_M }, // 6788 |
| 28059 | { PseudoVMSOF_M_B32_MASK, VMSOF_M }, // 6789 |
| 28060 | { PseudoVMSOF_M_B4, VMSOF_M }, // 6790 |
| 28061 | { PseudoVMSOF_M_B4_MASK, VMSOF_M }, // 6791 |
| 28062 | { PseudoVMSOF_M_B64, VMSOF_M }, // 6792 |
| 28063 | { PseudoVMSOF_M_B64_MASK, VMSOF_M }, // 6793 |
| 28064 | { PseudoVMSOF_M_B8, VMSOF_M }, // 6794 |
| 28065 | { PseudoVMSOF_M_B8_MASK, VMSOF_M }, // 6795 |
| 28066 | { PseudoVMULHSU_VV_M1, VMULHSU_VV }, // 6796 |
| 28067 | { PseudoVMULHSU_VV_M1_MASK, VMULHSU_VV }, // 6797 |
| 28068 | { PseudoVMULHSU_VV_M2, VMULHSU_VV }, // 6798 |
| 28069 | { PseudoVMULHSU_VV_M2_MASK, VMULHSU_VV }, // 6799 |
| 28070 | { PseudoVMULHSU_VV_M4, VMULHSU_VV }, // 6800 |
| 28071 | { PseudoVMULHSU_VV_M4_MASK, VMULHSU_VV }, // 6801 |
| 28072 | { PseudoVMULHSU_VV_M8, VMULHSU_VV }, // 6802 |
| 28073 | { PseudoVMULHSU_VV_M8_MASK, VMULHSU_VV }, // 6803 |
| 28074 | { PseudoVMULHSU_VV_MF2, VMULHSU_VV }, // 6804 |
| 28075 | { PseudoVMULHSU_VV_MF2_MASK, VMULHSU_VV }, // 6805 |
| 28076 | { PseudoVMULHSU_VV_MF4, VMULHSU_VV }, // 6806 |
| 28077 | { PseudoVMULHSU_VV_MF4_MASK, VMULHSU_VV }, // 6807 |
| 28078 | { PseudoVMULHSU_VV_MF8, VMULHSU_VV }, // 6808 |
| 28079 | { PseudoVMULHSU_VV_MF8_MASK, VMULHSU_VV }, // 6809 |
| 28080 | { PseudoVMULHSU_VX_M1, VMULHSU_VX }, // 6810 |
| 28081 | { PseudoVMULHSU_VX_M1_MASK, VMULHSU_VX }, // 6811 |
| 28082 | { PseudoVMULHSU_VX_M2, VMULHSU_VX }, // 6812 |
| 28083 | { PseudoVMULHSU_VX_M2_MASK, VMULHSU_VX }, // 6813 |
| 28084 | { PseudoVMULHSU_VX_M4, VMULHSU_VX }, // 6814 |
| 28085 | { PseudoVMULHSU_VX_M4_MASK, VMULHSU_VX }, // 6815 |
| 28086 | { PseudoVMULHSU_VX_M8, VMULHSU_VX }, // 6816 |
| 28087 | { PseudoVMULHSU_VX_M8_MASK, VMULHSU_VX }, // 6817 |
| 28088 | { PseudoVMULHSU_VX_MF2, VMULHSU_VX }, // 6818 |
| 28089 | { PseudoVMULHSU_VX_MF2_MASK, VMULHSU_VX }, // 6819 |
| 28090 | { PseudoVMULHSU_VX_MF4, VMULHSU_VX }, // 6820 |
| 28091 | { PseudoVMULHSU_VX_MF4_MASK, VMULHSU_VX }, // 6821 |
| 28092 | { PseudoVMULHSU_VX_MF8, VMULHSU_VX }, // 6822 |
| 28093 | { PseudoVMULHSU_VX_MF8_MASK, VMULHSU_VX }, // 6823 |
| 28094 | { PseudoVMULHU_VV_M1, VMULHU_VV }, // 6824 |
| 28095 | { PseudoVMULHU_VV_M1_MASK, VMULHU_VV }, // 6825 |
| 28096 | { PseudoVMULHU_VV_M2, VMULHU_VV }, // 6826 |
| 28097 | { PseudoVMULHU_VV_M2_MASK, VMULHU_VV }, // 6827 |
| 28098 | { PseudoVMULHU_VV_M4, VMULHU_VV }, // 6828 |
| 28099 | { PseudoVMULHU_VV_M4_MASK, VMULHU_VV }, // 6829 |
| 28100 | { PseudoVMULHU_VV_M8, VMULHU_VV }, // 6830 |
| 28101 | { PseudoVMULHU_VV_M8_MASK, VMULHU_VV }, // 6831 |
| 28102 | { PseudoVMULHU_VV_MF2, VMULHU_VV }, // 6832 |
| 28103 | { PseudoVMULHU_VV_MF2_MASK, VMULHU_VV }, // 6833 |
| 28104 | { PseudoVMULHU_VV_MF4, VMULHU_VV }, // 6834 |
| 28105 | { PseudoVMULHU_VV_MF4_MASK, VMULHU_VV }, // 6835 |
| 28106 | { PseudoVMULHU_VV_MF8, VMULHU_VV }, // 6836 |
| 28107 | { PseudoVMULHU_VV_MF8_MASK, VMULHU_VV }, // 6837 |
| 28108 | { PseudoVMULHU_VX_M1, VMULHU_VX }, // 6838 |
| 28109 | { PseudoVMULHU_VX_M1_MASK, VMULHU_VX }, // 6839 |
| 28110 | { PseudoVMULHU_VX_M2, VMULHU_VX }, // 6840 |
| 28111 | { PseudoVMULHU_VX_M2_MASK, VMULHU_VX }, // 6841 |
| 28112 | { PseudoVMULHU_VX_M4, VMULHU_VX }, // 6842 |
| 28113 | { PseudoVMULHU_VX_M4_MASK, VMULHU_VX }, // 6843 |
| 28114 | { PseudoVMULHU_VX_M8, VMULHU_VX }, // 6844 |
| 28115 | { PseudoVMULHU_VX_M8_MASK, VMULHU_VX }, // 6845 |
| 28116 | { PseudoVMULHU_VX_MF2, VMULHU_VX }, // 6846 |
| 28117 | { PseudoVMULHU_VX_MF2_MASK, VMULHU_VX }, // 6847 |
| 28118 | { PseudoVMULHU_VX_MF4, VMULHU_VX }, // 6848 |
| 28119 | { PseudoVMULHU_VX_MF4_MASK, VMULHU_VX }, // 6849 |
| 28120 | { PseudoVMULHU_VX_MF8, VMULHU_VX }, // 6850 |
| 28121 | { PseudoVMULHU_VX_MF8_MASK, VMULHU_VX }, // 6851 |
| 28122 | { PseudoVMULH_VV_M1, VMULH_VV }, // 6852 |
| 28123 | { PseudoVMULH_VV_M1_MASK, VMULH_VV }, // 6853 |
| 28124 | { PseudoVMULH_VV_M2, VMULH_VV }, // 6854 |
| 28125 | { PseudoVMULH_VV_M2_MASK, VMULH_VV }, // 6855 |
| 28126 | { PseudoVMULH_VV_M4, VMULH_VV }, // 6856 |
| 28127 | { PseudoVMULH_VV_M4_MASK, VMULH_VV }, // 6857 |
| 28128 | { PseudoVMULH_VV_M8, VMULH_VV }, // 6858 |
| 28129 | { PseudoVMULH_VV_M8_MASK, VMULH_VV }, // 6859 |
| 28130 | { PseudoVMULH_VV_MF2, VMULH_VV }, // 6860 |
| 28131 | { PseudoVMULH_VV_MF2_MASK, VMULH_VV }, // 6861 |
| 28132 | { PseudoVMULH_VV_MF4, VMULH_VV }, // 6862 |
| 28133 | { PseudoVMULH_VV_MF4_MASK, VMULH_VV }, // 6863 |
| 28134 | { PseudoVMULH_VV_MF8, VMULH_VV }, // 6864 |
| 28135 | { PseudoVMULH_VV_MF8_MASK, VMULH_VV }, // 6865 |
| 28136 | { PseudoVMULH_VX_M1, VMULH_VX }, // 6866 |
| 28137 | { PseudoVMULH_VX_M1_MASK, VMULH_VX }, // 6867 |
| 28138 | { PseudoVMULH_VX_M2, VMULH_VX }, // 6868 |
| 28139 | { PseudoVMULH_VX_M2_MASK, VMULH_VX }, // 6869 |
| 28140 | { PseudoVMULH_VX_M4, VMULH_VX }, // 6870 |
| 28141 | { PseudoVMULH_VX_M4_MASK, VMULH_VX }, // 6871 |
| 28142 | { PseudoVMULH_VX_M8, VMULH_VX }, // 6872 |
| 28143 | { PseudoVMULH_VX_M8_MASK, VMULH_VX }, // 6873 |
| 28144 | { PseudoVMULH_VX_MF2, VMULH_VX }, // 6874 |
| 28145 | { PseudoVMULH_VX_MF2_MASK, VMULH_VX }, // 6875 |
| 28146 | { PseudoVMULH_VX_MF4, VMULH_VX }, // 6876 |
| 28147 | { PseudoVMULH_VX_MF4_MASK, VMULH_VX }, // 6877 |
| 28148 | { PseudoVMULH_VX_MF8, VMULH_VX }, // 6878 |
| 28149 | { PseudoVMULH_VX_MF8_MASK, VMULH_VX }, // 6879 |
| 28150 | { PseudoVMUL_VV_M1, VMUL_VV }, // 6880 |
| 28151 | { PseudoVMUL_VV_M1_MASK, VMUL_VV }, // 6881 |
| 28152 | { PseudoVMUL_VV_M2, VMUL_VV }, // 6882 |
| 28153 | { PseudoVMUL_VV_M2_MASK, VMUL_VV }, // 6883 |
| 28154 | { PseudoVMUL_VV_M4, VMUL_VV }, // 6884 |
| 28155 | { PseudoVMUL_VV_M4_MASK, VMUL_VV }, // 6885 |
| 28156 | { PseudoVMUL_VV_M8, VMUL_VV }, // 6886 |
| 28157 | { PseudoVMUL_VV_M8_MASK, VMUL_VV }, // 6887 |
| 28158 | { PseudoVMUL_VV_MF2, VMUL_VV }, // 6888 |
| 28159 | { PseudoVMUL_VV_MF2_MASK, VMUL_VV }, // 6889 |
| 28160 | { PseudoVMUL_VV_MF4, VMUL_VV }, // 6890 |
| 28161 | { PseudoVMUL_VV_MF4_MASK, VMUL_VV }, // 6891 |
| 28162 | { PseudoVMUL_VV_MF8, VMUL_VV }, // 6892 |
| 28163 | { PseudoVMUL_VV_MF8_MASK, VMUL_VV }, // 6893 |
| 28164 | { PseudoVMUL_VX_M1, VMUL_VX }, // 6894 |
| 28165 | { PseudoVMUL_VX_M1_MASK, VMUL_VX }, // 6895 |
| 28166 | { PseudoVMUL_VX_M2, VMUL_VX }, // 6896 |
| 28167 | { PseudoVMUL_VX_M2_MASK, VMUL_VX }, // 6897 |
| 28168 | { PseudoVMUL_VX_M4, VMUL_VX }, // 6898 |
| 28169 | { PseudoVMUL_VX_M4_MASK, VMUL_VX }, // 6899 |
| 28170 | { PseudoVMUL_VX_M8, VMUL_VX }, // 6900 |
| 28171 | { PseudoVMUL_VX_M8_MASK, VMUL_VX }, // 6901 |
| 28172 | { PseudoVMUL_VX_MF2, VMUL_VX }, // 6902 |
| 28173 | { PseudoVMUL_VX_MF2_MASK, VMUL_VX }, // 6903 |
| 28174 | { PseudoVMUL_VX_MF4, VMUL_VX }, // 6904 |
| 28175 | { PseudoVMUL_VX_MF4_MASK, VMUL_VX }, // 6905 |
| 28176 | { PseudoVMUL_VX_MF8, VMUL_VX }, // 6906 |
| 28177 | { PseudoVMUL_VX_MF8_MASK, VMUL_VX }, // 6907 |
| 28178 | { PseudoVMV_S_X, VMV_S_X }, // 6908 |
| 28179 | { PseudoVMV_V_I_M1, VMV_V_I }, // 6909 |
| 28180 | { PseudoVMV_V_I_M2, VMV_V_I }, // 6910 |
| 28181 | { PseudoVMV_V_I_M4, VMV_V_I }, // 6911 |
| 28182 | { PseudoVMV_V_I_M8, VMV_V_I }, // 6912 |
| 28183 | { PseudoVMV_V_I_MF2, VMV_V_I }, // 6913 |
| 28184 | { PseudoVMV_V_I_MF4, VMV_V_I }, // 6914 |
| 28185 | { PseudoVMV_V_I_MF8, VMV_V_I }, // 6915 |
| 28186 | { PseudoVMV_V_V_M1, VMV_V_V }, // 6916 |
| 28187 | { PseudoVMV_V_V_M2, VMV_V_V }, // 6917 |
| 28188 | { PseudoVMV_V_V_M4, VMV_V_V }, // 6918 |
| 28189 | { PseudoVMV_V_V_M8, VMV_V_V }, // 6919 |
| 28190 | { PseudoVMV_V_V_MF2, VMV_V_V }, // 6920 |
| 28191 | { PseudoVMV_V_V_MF4, VMV_V_V }, // 6921 |
| 28192 | { PseudoVMV_V_V_MF8, VMV_V_V }, // 6922 |
| 28193 | { PseudoVMV_V_X_M1, VMV_V_X }, // 6923 |
| 28194 | { PseudoVMV_V_X_M2, VMV_V_X }, // 6924 |
| 28195 | { PseudoVMV_V_X_M4, VMV_V_X }, // 6925 |
| 28196 | { PseudoVMV_V_X_M8, VMV_V_X }, // 6926 |
| 28197 | { PseudoVMV_V_X_MF2, VMV_V_X }, // 6927 |
| 28198 | { PseudoVMV_V_X_MF4, VMV_V_X }, // 6928 |
| 28199 | { PseudoVMV_V_X_MF8, VMV_V_X }, // 6929 |
| 28200 | { PseudoVMV_X_S, VMV_X_S }, // 6930 |
| 28201 | { PseudoVMXNOR_MM_M1, VMXNOR_MM }, // 6931 |
| 28202 | { PseudoVMXNOR_MM_M2, VMXNOR_MM }, // 6932 |
| 28203 | { PseudoVMXNOR_MM_M4, VMXNOR_MM }, // 6933 |
| 28204 | { PseudoVMXNOR_MM_M8, VMXNOR_MM }, // 6934 |
| 28205 | { PseudoVMXNOR_MM_MF2, VMXNOR_MM }, // 6935 |
| 28206 | { PseudoVMXNOR_MM_MF4, VMXNOR_MM }, // 6936 |
| 28207 | { PseudoVMXNOR_MM_MF8, VMXNOR_MM }, // 6937 |
| 28208 | { PseudoVMXOR_MM_M1, VMXOR_MM }, // 6938 |
| 28209 | { PseudoVMXOR_MM_M2, VMXOR_MM }, // 6939 |
| 28210 | { PseudoVMXOR_MM_M4, VMXOR_MM }, // 6940 |
| 28211 | { PseudoVMXOR_MM_M8, VMXOR_MM }, // 6941 |
| 28212 | { PseudoVMXOR_MM_MF2, VMXOR_MM }, // 6942 |
| 28213 | { PseudoVMXOR_MM_MF4, VMXOR_MM }, // 6943 |
| 28214 | { PseudoVMXOR_MM_MF8, VMXOR_MM }, // 6944 |
| 28215 | { PseudoVNCLIPU_WI_M1, VNCLIPU_WI }, // 6945 |
| 28216 | { PseudoVNCLIPU_WI_M1_MASK, VNCLIPU_WI }, // 6946 |
| 28217 | { PseudoVNCLIPU_WI_M2, VNCLIPU_WI }, // 6947 |
| 28218 | { PseudoVNCLIPU_WI_M2_MASK, VNCLIPU_WI }, // 6948 |
| 28219 | { PseudoVNCLIPU_WI_M4, VNCLIPU_WI }, // 6949 |
| 28220 | { PseudoVNCLIPU_WI_M4_MASK, VNCLIPU_WI }, // 6950 |
| 28221 | { PseudoVNCLIPU_WI_MF2, VNCLIPU_WI }, // 6951 |
| 28222 | { PseudoVNCLIPU_WI_MF2_MASK, VNCLIPU_WI }, // 6952 |
| 28223 | { PseudoVNCLIPU_WI_MF4, VNCLIPU_WI }, // 6953 |
| 28224 | { PseudoVNCLIPU_WI_MF4_MASK, VNCLIPU_WI }, // 6954 |
| 28225 | { PseudoVNCLIPU_WI_MF8, VNCLIPU_WI }, // 6955 |
| 28226 | { PseudoVNCLIPU_WI_MF8_MASK, VNCLIPU_WI }, // 6956 |
| 28227 | { PseudoVNCLIPU_WV_M1, VNCLIPU_WV }, // 6957 |
| 28228 | { PseudoVNCLIPU_WV_M1_MASK, VNCLIPU_WV }, // 6958 |
| 28229 | { PseudoVNCLIPU_WV_M2, VNCLIPU_WV }, // 6959 |
| 28230 | { PseudoVNCLIPU_WV_M2_MASK, VNCLIPU_WV }, // 6960 |
| 28231 | { PseudoVNCLIPU_WV_M4, VNCLIPU_WV }, // 6961 |
| 28232 | { PseudoVNCLIPU_WV_M4_MASK, VNCLIPU_WV }, // 6962 |
| 28233 | { PseudoVNCLIPU_WV_MF2, VNCLIPU_WV }, // 6963 |
| 28234 | { PseudoVNCLIPU_WV_MF2_MASK, VNCLIPU_WV }, // 6964 |
| 28235 | { PseudoVNCLIPU_WV_MF4, VNCLIPU_WV }, // 6965 |
| 28236 | { PseudoVNCLIPU_WV_MF4_MASK, VNCLIPU_WV }, // 6966 |
| 28237 | { PseudoVNCLIPU_WV_MF8, VNCLIPU_WV }, // 6967 |
| 28238 | { PseudoVNCLIPU_WV_MF8_MASK, VNCLIPU_WV }, // 6968 |
| 28239 | { PseudoVNCLIPU_WX_M1, VNCLIPU_WX }, // 6969 |
| 28240 | { PseudoVNCLIPU_WX_M1_MASK, VNCLIPU_WX }, // 6970 |
| 28241 | { PseudoVNCLIPU_WX_M2, VNCLIPU_WX }, // 6971 |
| 28242 | { PseudoVNCLIPU_WX_M2_MASK, VNCLIPU_WX }, // 6972 |
| 28243 | { PseudoVNCLIPU_WX_M4, VNCLIPU_WX }, // 6973 |
| 28244 | { PseudoVNCLIPU_WX_M4_MASK, VNCLIPU_WX }, // 6974 |
| 28245 | { PseudoVNCLIPU_WX_MF2, VNCLIPU_WX }, // 6975 |
| 28246 | { PseudoVNCLIPU_WX_MF2_MASK, VNCLIPU_WX }, // 6976 |
| 28247 | { PseudoVNCLIPU_WX_MF4, VNCLIPU_WX }, // 6977 |
| 28248 | { PseudoVNCLIPU_WX_MF4_MASK, VNCLIPU_WX }, // 6978 |
| 28249 | { PseudoVNCLIPU_WX_MF8, VNCLIPU_WX }, // 6979 |
| 28250 | { PseudoVNCLIPU_WX_MF8_MASK, VNCLIPU_WX }, // 6980 |
| 28251 | { PseudoVNCLIP_WI_M1, VNCLIP_WI }, // 6981 |
| 28252 | { PseudoVNCLIP_WI_M1_MASK, VNCLIP_WI }, // 6982 |
| 28253 | { PseudoVNCLIP_WI_M2, VNCLIP_WI }, // 6983 |
| 28254 | { PseudoVNCLIP_WI_M2_MASK, VNCLIP_WI }, // 6984 |
| 28255 | { PseudoVNCLIP_WI_M4, VNCLIP_WI }, // 6985 |
| 28256 | { PseudoVNCLIP_WI_M4_MASK, VNCLIP_WI }, // 6986 |
| 28257 | { PseudoVNCLIP_WI_MF2, VNCLIP_WI }, // 6987 |
| 28258 | { PseudoVNCLIP_WI_MF2_MASK, VNCLIP_WI }, // 6988 |
| 28259 | { PseudoVNCLIP_WI_MF4, VNCLIP_WI }, // 6989 |
| 28260 | { PseudoVNCLIP_WI_MF4_MASK, VNCLIP_WI }, // 6990 |
| 28261 | { PseudoVNCLIP_WI_MF8, VNCLIP_WI }, // 6991 |
| 28262 | { PseudoVNCLIP_WI_MF8_MASK, VNCLIP_WI }, // 6992 |
| 28263 | { PseudoVNCLIP_WV_M1, VNCLIP_WV }, // 6993 |
| 28264 | { PseudoVNCLIP_WV_M1_MASK, VNCLIP_WV }, // 6994 |
| 28265 | { PseudoVNCLIP_WV_M2, VNCLIP_WV }, // 6995 |
| 28266 | { PseudoVNCLIP_WV_M2_MASK, VNCLIP_WV }, // 6996 |
| 28267 | { PseudoVNCLIP_WV_M4, VNCLIP_WV }, // 6997 |
| 28268 | { PseudoVNCLIP_WV_M4_MASK, VNCLIP_WV }, // 6998 |
| 28269 | { PseudoVNCLIP_WV_MF2, VNCLIP_WV }, // 6999 |
| 28270 | { PseudoVNCLIP_WV_MF2_MASK, VNCLIP_WV }, // 7000 |
| 28271 | { PseudoVNCLIP_WV_MF4, VNCLIP_WV }, // 7001 |
| 28272 | { PseudoVNCLIP_WV_MF4_MASK, VNCLIP_WV }, // 7002 |
| 28273 | { PseudoVNCLIP_WV_MF8, VNCLIP_WV }, // 7003 |
| 28274 | { PseudoVNCLIP_WV_MF8_MASK, VNCLIP_WV }, // 7004 |
| 28275 | { PseudoVNCLIP_WX_M1, VNCLIP_WX }, // 7005 |
| 28276 | { PseudoVNCLIP_WX_M1_MASK, VNCLIP_WX }, // 7006 |
| 28277 | { PseudoVNCLIP_WX_M2, VNCLIP_WX }, // 7007 |
| 28278 | { PseudoVNCLIP_WX_M2_MASK, VNCLIP_WX }, // 7008 |
| 28279 | { PseudoVNCLIP_WX_M4, VNCLIP_WX }, // 7009 |
| 28280 | { PseudoVNCLIP_WX_M4_MASK, VNCLIP_WX }, // 7010 |
| 28281 | { PseudoVNCLIP_WX_MF2, VNCLIP_WX }, // 7011 |
| 28282 | { PseudoVNCLIP_WX_MF2_MASK, VNCLIP_WX }, // 7012 |
| 28283 | { PseudoVNCLIP_WX_MF4, VNCLIP_WX }, // 7013 |
| 28284 | { PseudoVNCLIP_WX_MF4_MASK, VNCLIP_WX }, // 7014 |
| 28285 | { PseudoVNCLIP_WX_MF8, VNCLIP_WX }, // 7015 |
| 28286 | { PseudoVNCLIP_WX_MF8_MASK, VNCLIP_WX }, // 7016 |
| 28287 | { PseudoVNMSAC_VV_M1, VNMSAC_VV }, // 7017 |
| 28288 | { PseudoVNMSAC_VV_M1_MASK, VNMSAC_VV }, // 7018 |
| 28289 | { PseudoVNMSAC_VV_M2, VNMSAC_VV }, // 7019 |
| 28290 | { PseudoVNMSAC_VV_M2_MASK, VNMSAC_VV }, // 7020 |
| 28291 | { PseudoVNMSAC_VV_M4, VNMSAC_VV }, // 7021 |
| 28292 | { PseudoVNMSAC_VV_M4_MASK, VNMSAC_VV }, // 7022 |
| 28293 | { PseudoVNMSAC_VV_M8, VNMSAC_VV }, // 7023 |
| 28294 | { PseudoVNMSAC_VV_M8_MASK, VNMSAC_VV }, // 7024 |
| 28295 | { PseudoVNMSAC_VV_MF2, VNMSAC_VV }, // 7025 |
| 28296 | { PseudoVNMSAC_VV_MF2_MASK, VNMSAC_VV }, // 7026 |
| 28297 | { PseudoVNMSAC_VV_MF4, VNMSAC_VV }, // 7027 |
| 28298 | { PseudoVNMSAC_VV_MF4_MASK, VNMSAC_VV }, // 7028 |
| 28299 | { PseudoVNMSAC_VV_MF8, VNMSAC_VV }, // 7029 |
| 28300 | { PseudoVNMSAC_VV_MF8_MASK, VNMSAC_VV }, // 7030 |
| 28301 | { PseudoVNMSAC_VX_M1, VNMSAC_VX }, // 7031 |
| 28302 | { PseudoVNMSAC_VX_M1_MASK, VNMSAC_VX }, // 7032 |
| 28303 | { PseudoVNMSAC_VX_M2, VNMSAC_VX }, // 7033 |
| 28304 | { PseudoVNMSAC_VX_M2_MASK, VNMSAC_VX }, // 7034 |
| 28305 | { PseudoVNMSAC_VX_M4, VNMSAC_VX }, // 7035 |
| 28306 | { PseudoVNMSAC_VX_M4_MASK, VNMSAC_VX }, // 7036 |
| 28307 | { PseudoVNMSAC_VX_M8, VNMSAC_VX }, // 7037 |
| 28308 | { PseudoVNMSAC_VX_M8_MASK, VNMSAC_VX }, // 7038 |
| 28309 | { PseudoVNMSAC_VX_MF2, VNMSAC_VX }, // 7039 |
| 28310 | { PseudoVNMSAC_VX_MF2_MASK, VNMSAC_VX }, // 7040 |
| 28311 | { PseudoVNMSAC_VX_MF4, VNMSAC_VX }, // 7041 |
| 28312 | { PseudoVNMSAC_VX_MF4_MASK, VNMSAC_VX }, // 7042 |
| 28313 | { PseudoVNMSAC_VX_MF8, VNMSAC_VX }, // 7043 |
| 28314 | { PseudoVNMSAC_VX_MF8_MASK, VNMSAC_VX }, // 7044 |
| 28315 | { PseudoVNMSUB_VV_M1, VNMSUB_VV }, // 7045 |
| 28316 | { PseudoVNMSUB_VV_M1_MASK, VNMSUB_VV }, // 7046 |
| 28317 | { PseudoVNMSUB_VV_M2, VNMSUB_VV }, // 7047 |
| 28318 | { PseudoVNMSUB_VV_M2_MASK, VNMSUB_VV }, // 7048 |
| 28319 | { PseudoVNMSUB_VV_M4, VNMSUB_VV }, // 7049 |
| 28320 | { PseudoVNMSUB_VV_M4_MASK, VNMSUB_VV }, // 7050 |
| 28321 | { PseudoVNMSUB_VV_M8, VNMSUB_VV }, // 7051 |
| 28322 | { PseudoVNMSUB_VV_M8_MASK, VNMSUB_VV }, // 7052 |
| 28323 | { PseudoVNMSUB_VV_MF2, VNMSUB_VV }, // 7053 |
| 28324 | { PseudoVNMSUB_VV_MF2_MASK, VNMSUB_VV }, // 7054 |
| 28325 | { PseudoVNMSUB_VV_MF4, VNMSUB_VV }, // 7055 |
| 28326 | { PseudoVNMSUB_VV_MF4_MASK, VNMSUB_VV }, // 7056 |
| 28327 | { PseudoVNMSUB_VV_MF8, VNMSUB_VV }, // 7057 |
| 28328 | { PseudoVNMSUB_VV_MF8_MASK, VNMSUB_VV }, // 7058 |
| 28329 | { PseudoVNMSUB_VX_M1, VNMSUB_VX }, // 7059 |
| 28330 | { PseudoVNMSUB_VX_M1_MASK, VNMSUB_VX }, // 7060 |
| 28331 | { PseudoVNMSUB_VX_M2, VNMSUB_VX }, // 7061 |
| 28332 | { PseudoVNMSUB_VX_M2_MASK, VNMSUB_VX }, // 7062 |
| 28333 | { PseudoVNMSUB_VX_M4, VNMSUB_VX }, // 7063 |
| 28334 | { PseudoVNMSUB_VX_M4_MASK, VNMSUB_VX }, // 7064 |
| 28335 | { PseudoVNMSUB_VX_M8, VNMSUB_VX }, // 7065 |
| 28336 | { PseudoVNMSUB_VX_M8_MASK, VNMSUB_VX }, // 7066 |
| 28337 | { PseudoVNMSUB_VX_MF2, VNMSUB_VX }, // 7067 |
| 28338 | { PseudoVNMSUB_VX_MF2_MASK, VNMSUB_VX }, // 7068 |
| 28339 | { PseudoVNMSUB_VX_MF4, VNMSUB_VX }, // 7069 |
| 28340 | { PseudoVNMSUB_VX_MF4_MASK, VNMSUB_VX }, // 7070 |
| 28341 | { PseudoVNMSUB_VX_MF8, VNMSUB_VX }, // 7071 |
| 28342 | { PseudoVNMSUB_VX_MF8_MASK, VNMSUB_VX }, // 7072 |
| 28343 | { PseudoVNSRA_WI_M1, VNSRA_WI }, // 7073 |
| 28344 | { PseudoVNSRA_WI_M1_MASK, VNSRA_WI }, // 7074 |
| 28345 | { PseudoVNSRA_WI_M2, VNSRA_WI }, // 7075 |
| 28346 | { PseudoVNSRA_WI_M2_MASK, VNSRA_WI }, // 7076 |
| 28347 | { PseudoVNSRA_WI_M4, VNSRA_WI }, // 7077 |
| 28348 | { PseudoVNSRA_WI_M4_MASK, VNSRA_WI }, // 7078 |
| 28349 | { PseudoVNSRA_WI_MF2, VNSRA_WI }, // 7079 |
| 28350 | { PseudoVNSRA_WI_MF2_MASK, VNSRA_WI }, // 7080 |
| 28351 | { PseudoVNSRA_WI_MF4, VNSRA_WI }, // 7081 |
| 28352 | { PseudoVNSRA_WI_MF4_MASK, VNSRA_WI }, // 7082 |
| 28353 | { PseudoVNSRA_WI_MF8, VNSRA_WI }, // 7083 |
| 28354 | { PseudoVNSRA_WI_MF8_MASK, VNSRA_WI }, // 7084 |
| 28355 | { PseudoVNSRA_WV_M1, VNSRA_WV }, // 7085 |
| 28356 | { PseudoVNSRA_WV_M1_MASK, VNSRA_WV }, // 7086 |
| 28357 | { PseudoVNSRA_WV_M2, VNSRA_WV }, // 7087 |
| 28358 | { PseudoVNSRA_WV_M2_MASK, VNSRA_WV }, // 7088 |
| 28359 | { PseudoVNSRA_WV_M4, VNSRA_WV }, // 7089 |
| 28360 | { PseudoVNSRA_WV_M4_MASK, VNSRA_WV }, // 7090 |
| 28361 | { PseudoVNSRA_WV_MF2, VNSRA_WV }, // 7091 |
| 28362 | { PseudoVNSRA_WV_MF2_MASK, VNSRA_WV }, // 7092 |
| 28363 | { PseudoVNSRA_WV_MF4, VNSRA_WV }, // 7093 |
| 28364 | { PseudoVNSRA_WV_MF4_MASK, VNSRA_WV }, // 7094 |
| 28365 | { PseudoVNSRA_WV_MF8, VNSRA_WV }, // 7095 |
| 28366 | { PseudoVNSRA_WV_MF8_MASK, VNSRA_WV }, // 7096 |
| 28367 | { PseudoVNSRA_WX_M1, VNSRA_WX }, // 7097 |
| 28368 | { PseudoVNSRA_WX_M1_MASK, VNSRA_WX }, // 7098 |
| 28369 | { PseudoVNSRA_WX_M2, VNSRA_WX }, // 7099 |
| 28370 | { PseudoVNSRA_WX_M2_MASK, VNSRA_WX }, // 7100 |
| 28371 | { PseudoVNSRA_WX_M4, VNSRA_WX }, // 7101 |
| 28372 | { PseudoVNSRA_WX_M4_MASK, VNSRA_WX }, // 7102 |
| 28373 | { PseudoVNSRA_WX_MF2, VNSRA_WX }, // 7103 |
| 28374 | { PseudoVNSRA_WX_MF2_MASK, VNSRA_WX }, // 7104 |
| 28375 | { PseudoVNSRA_WX_MF4, VNSRA_WX }, // 7105 |
| 28376 | { PseudoVNSRA_WX_MF4_MASK, VNSRA_WX }, // 7106 |
| 28377 | { PseudoVNSRA_WX_MF8, VNSRA_WX }, // 7107 |
| 28378 | { PseudoVNSRA_WX_MF8_MASK, VNSRA_WX }, // 7108 |
| 28379 | { PseudoVNSRL_WI_M1, VNSRL_WI }, // 7109 |
| 28380 | { PseudoVNSRL_WI_M1_MASK, VNSRL_WI }, // 7110 |
| 28381 | { PseudoVNSRL_WI_M2, VNSRL_WI }, // 7111 |
| 28382 | { PseudoVNSRL_WI_M2_MASK, VNSRL_WI }, // 7112 |
| 28383 | { PseudoVNSRL_WI_M4, VNSRL_WI }, // 7113 |
| 28384 | { PseudoVNSRL_WI_M4_MASK, VNSRL_WI }, // 7114 |
| 28385 | { PseudoVNSRL_WI_MF2, VNSRL_WI }, // 7115 |
| 28386 | { PseudoVNSRL_WI_MF2_MASK, VNSRL_WI }, // 7116 |
| 28387 | { PseudoVNSRL_WI_MF4, VNSRL_WI }, // 7117 |
| 28388 | { PseudoVNSRL_WI_MF4_MASK, VNSRL_WI }, // 7118 |
| 28389 | { PseudoVNSRL_WI_MF8, VNSRL_WI }, // 7119 |
| 28390 | { PseudoVNSRL_WI_MF8_MASK, VNSRL_WI }, // 7120 |
| 28391 | { PseudoVNSRL_WV_M1, VNSRL_WV }, // 7121 |
| 28392 | { PseudoVNSRL_WV_M1_MASK, VNSRL_WV }, // 7122 |
| 28393 | { PseudoVNSRL_WV_M2, VNSRL_WV }, // 7123 |
| 28394 | { PseudoVNSRL_WV_M2_MASK, VNSRL_WV }, // 7124 |
| 28395 | { PseudoVNSRL_WV_M4, VNSRL_WV }, // 7125 |
| 28396 | { PseudoVNSRL_WV_M4_MASK, VNSRL_WV }, // 7126 |
| 28397 | { PseudoVNSRL_WV_MF2, VNSRL_WV }, // 7127 |
| 28398 | { PseudoVNSRL_WV_MF2_MASK, VNSRL_WV }, // 7128 |
| 28399 | { PseudoVNSRL_WV_MF4, VNSRL_WV }, // 7129 |
| 28400 | { PseudoVNSRL_WV_MF4_MASK, VNSRL_WV }, // 7130 |
| 28401 | { PseudoVNSRL_WV_MF8, VNSRL_WV }, // 7131 |
| 28402 | { PseudoVNSRL_WV_MF8_MASK, VNSRL_WV }, // 7132 |
| 28403 | { PseudoVNSRL_WX_M1, VNSRL_WX }, // 7133 |
| 28404 | { PseudoVNSRL_WX_M1_MASK, VNSRL_WX }, // 7134 |
| 28405 | { PseudoVNSRL_WX_M2, VNSRL_WX }, // 7135 |
| 28406 | { PseudoVNSRL_WX_M2_MASK, VNSRL_WX }, // 7136 |
| 28407 | { PseudoVNSRL_WX_M4, VNSRL_WX }, // 7137 |
| 28408 | { PseudoVNSRL_WX_M4_MASK, VNSRL_WX }, // 7138 |
| 28409 | { PseudoVNSRL_WX_MF2, VNSRL_WX }, // 7139 |
| 28410 | { PseudoVNSRL_WX_MF2_MASK, VNSRL_WX }, // 7140 |
| 28411 | { PseudoVNSRL_WX_MF4, VNSRL_WX }, // 7141 |
| 28412 | { PseudoVNSRL_WX_MF4_MASK, VNSRL_WX }, // 7142 |
| 28413 | { PseudoVNSRL_WX_MF8, VNSRL_WX }, // 7143 |
| 28414 | { PseudoVNSRL_WX_MF8_MASK, VNSRL_WX }, // 7144 |
| 28415 | { PseudoVOR_VI_M1, VOR_VI }, // 7145 |
| 28416 | { PseudoVOR_VI_M1_MASK, VOR_VI }, // 7146 |
| 28417 | { PseudoVOR_VI_M2, VOR_VI }, // 7147 |
| 28418 | { PseudoVOR_VI_M2_MASK, VOR_VI }, // 7148 |
| 28419 | { PseudoVOR_VI_M4, VOR_VI }, // 7149 |
| 28420 | { PseudoVOR_VI_M4_MASK, VOR_VI }, // 7150 |
| 28421 | { PseudoVOR_VI_M8, VOR_VI }, // 7151 |
| 28422 | { PseudoVOR_VI_M8_MASK, VOR_VI }, // 7152 |
| 28423 | { PseudoVOR_VI_MF2, VOR_VI }, // 7153 |
| 28424 | { PseudoVOR_VI_MF2_MASK, VOR_VI }, // 7154 |
| 28425 | { PseudoVOR_VI_MF4, VOR_VI }, // 7155 |
| 28426 | { PseudoVOR_VI_MF4_MASK, VOR_VI }, // 7156 |
| 28427 | { PseudoVOR_VI_MF8, VOR_VI }, // 7157 |
| 28428 | { PseudoVOR_VI_MF8_MASK, VOR_VI }, // 7158 |
| 28429 | { PseudoVOR_VV_M1, VOR_VV }, // 7159 |
| 28430 | { PseudoVOR_VV_M1_MASK, VOR_VV }, // 7160 |
| 28431 | { PseudoVOR_VV_M2, VOR_VV }, // 7161 |
| 28432 | { PseudoVOR_VV_M2_MASK, VOR_VV }, // 7162 |
| 28433 | { PseudoVOR_VV_M4, VOR_VV }, // 7163 |
| 28434 | { PseudoVOR_VV_M4_MASK, VOR_VV }, // 7164 |
| 28435 | { PseudoVOR_VV_M8, VOR_VV }, // 7165 |
| 28436 | { PseudoVOR_VV_M8_MASK, VOR_VV }, // 7166 |
| 28437 | { PseudoVOR_VV_MF2, VOR_VV }, // 7167 |
| 28438 | { PseudoVOR_VV_MF2_MASK, VOR_VV }, // 7168 |
| 28439 | { PseudoVOR_VV_MF4, VOR_VV }, // 7169 |
| 28440 | { PseudoVOR_VV_MF4_MASK, VOR_VV }, // 7170 |
| 28441 | { PseudoVOR_VV_MF8, VOR_VV }, // 7171 |
| 28442 | { PseudoVOR_VV_MF8_MASK, VOR_VV }, // 7172 |
| 28443 | { PseudoVOR_VX_M1, VOR_VX }, // 7173 |
| 28444 | { PseudoVOR_VX_M1_MASK, VOR_VX }, // 7174 |
| 28445 | { PseudoVOR_VX_M2, VOR_VX }, // 7175 |
| 28446 | { PseudoVOR_VX_M2_MASK, VOR_VX }, // 7176 |
| 28447 | { PseudoVOR_VX_M4, VOR_VX }, // 7177 |
| 28448 | { PseudoVOR_VX_M4_MASK, VOR_VX }, // 7178 |
| 28449 | { PseudoVOR_VX_M8, VOR_VX }, // 7179 |
| 28450 | { PseudoVOR_VX_M8_MASK, VOR_VX }, // 7180 |
| 28451 | { PseudoVOR_VX_MF2, VOR_VX }, // 7181 |
| 28452 | { PseudoVOR_VX_MF2_MASK, VOR_VX }, // 7182 |
| 28453 | { PseudoVOR_VX_MF4, VOR_VX }, // 7183 |
| 28454 | { PseudoVOR_VX_MF4_MASK, VOR_VX }, // 7184 |
| 28455 | { PseudoVOR_VX_MF8, VOR_VX }, // 7185 |
| 28456 | { PseudoVOR_VX_MF8_MASK, VOR_VX }, // 7186 |
| 28457 | { PseudoVQMACCSU_2x8x2_M1, VQMACCSU_2x8x2 }, // 7187 |
| 28458 | { PseudoVQMACCSU_2x8x2_M2, VQMACCSU_2x8x2 }, // 7188 |
| 28459 | { PseudoVQMACCSU_2x8x2_M4, VQMACCSU_2x8x2 }, // 7189 |
| 28460 | { PseudoVQMACCSU_2x8x2_M8, VQMACCSU_2x8x2 }, // 7190 |
| 28461 | { PseudoVQMACCSU_4x8x4_M1, VQMACCSU_4x8x4 }, // 7191 |
| 28462 | { PseudoVQMACCSU_4x8x4_M2, VQMACCSU_4x8x4 }, // 7192 |
| 28463 | { PseudoVQMACCSU_4x8x4_M4, VQMACCSU_4x8x4 }, // 7193 |
| 28464 | { PseudoVQMACCSU_4x8x4_MF2, VQMACCSU_4x8x4 }, // 7194 |
| 28465 | { PseudoVQMACCUS_2x8x2_M1, VQMACCUS_2x8x2 }, // 7195 |
| 28466 | { PseudoVQMACCUS_2x8x2_M2, VQMACCUS_2x8x2 }, // 7196 |
| 28467 | { PseudoVQMACCUS_2x8x2_M4, VQMACCUS_2x8x2 }, // 7197 |
| 28468 | { PseudoVQMACCUS_2x8x2_M8, VQMACCUS_2x8x2 }, // 7198 |
| 28469 | { PseudoVQMACCUS_4x8x4_M1, VQMACCUS_4x8x4 }, // 7199 |
| 28470 | { PseudoVQMACCUS_4x8x4_M2, VQMACCUS_4x8x4 }, // 7200 |
| 28471 | { PseudoVQMACCUS_4x8x4_M4, VQMACCUS_4x8x4 }, // 7201 |
| 28472 | { PseudoVQMACCUS_4x8x4_MF2, VQMACCUS_4x8x4 }, // 7202 |
| 28473 | { PseudoVQMACCU_2x8x2_M1, VQMACCU_2x8x2 }, // 7203 |
| 28474 | { PseudoVQMACCU_2x8x2_M2, VQMACCU_2x8x2 }, // 7204 |
| 28475 | { PseudoVQMACCU_2x8x2_M4, VQMACCU_2x8x2 }, // 7205 |
| 28476 | { PseudoVQMACCU_2x8x2_M8, VQMACCU_2x8x2 }, // 7206 |
| 28477 | { PseudoVQMACCU_4x8x4_M1, VQMACCU_4x8x4 }, // 7207 |
| 28478 | { PseudoVQMACCU_4x8x4_M2, VQMACCU_4x8x4 }, // 7208 |
| 28479 | { PseudoVQMACCU_4x8x4_M4, VQMACCU_4x8x4 }, // 7209 |
| 28480 | { PseudoVQMACCU_4x8x4_MF2, VQMACCU_4x8x4 }, // 7210 |
| 28481 | { PseudoVQMACC_2x8x2_M1, VQMACC_2x8x2 }, // 7211 |
| 28482 | { PseudoVQMACC_2x8x2_M2, VQMACC_2x8x2 }, // 7212 |
| 28483 | { PseudoVQMACC_2x8x2_M4, VQMACC_2x8x2 }, // 7213 |
| 28484 | { PseudoVQMACC_2x8x2_M8, VQMACC_2x8x2 }, // 7214 |
| 28485 | { PseudoVQMACC_4x8x4_M1, VQMACC_4x8x4 }, // 7215 |
| 28486 | { PseudoVQMACC_4x8x4_M2, VQMACC_4x8x4 }, // 7216 |
| 28487 | { PseudoVQMACC_4x8x4_M4, VQMACC_4x8x4 }, // 7217 |
| 28488 | { PseudoVQMACC_4x8x4_MF2, VQMACC_4x8x4 }, // 7218 |
| 28489 | { PseudoVREDAND_VS_M1_E16, VREDAND_VS }, // 7219 |
| 28490 | { PseudoVREDAND_VS_M1_E16_MASK, VREDAND_VS }, // 7220 |
| 28491 | { PseudoVREDAND_VS_M1_E32, VREDAND_VS }, // 7221 |
| 28492 | { PseudoVREDAND_VS_M1_E32_MASK, VREDAND_VS }, // 7222 |
| 28493 | { PseudoVREDAND_VS_M1_E64, VREDAND_VS }, // 7223 |
| 28494 | { PseudoVREDAND_VS_M1_E64_MASK, VREDAND_VS }, // 7224 |
| 28495 | { PseudoVREDAND_VS_M1_E8, VREDAND_VS }, // 7225 |
| 28496 | { PseudoVREDAND_VS_M1_E8_MASK, VREDAND_VS }, // 7226 |
| 28497 | { PseudoVREDAND_VS_M2_E16, VREDAND_VS }, // 7227 |
| 28498 | { PseudoVREDAND_VS_M2_E16_MASK, VREDAND_VS }, // 7228 |
| 28499 | { PseudoVREDAND_VS_M2_E32, VREDAND_VS }, // 7229 |
| 28500 | { PseudoVREDAND_VS_M2_E32_MASK, VREDAND_VS }, // 7230 |
| 28501 | { PseudoVREDAND_VS_M2_E64, VREDAND_VS }, // 7231 |
| 28502 | { PseudoVREDAND_VS_M2_E64_MASK, VREDAND_VS }, // 7232 |
| 28503 | { PseudoVREDAND_VS_M2_E8, VREDAND_VS }, // 7233 |
| 28504 | { PseudoVREDAND_VS_M2_E8_MASK, VREDAND_VS }, // 7234 |
| 28505 | { PseudoVREDAND_VS_M4_E16, VREDAND_VS }, // 7235 |
| 28506 | { PseudoVREDAND_VS_M4_E16_MASK, VREDAND_VS }, // 7236 |
| 28507 | { PseudoVREDAND_VS_M4_E32, VREDAND_VS }, // 7237 |
| 28508 | { PseudoVREDAND_VS_M4_E32_MASK, VREDAND_VS }, // 7238 |
| 28509 | { PseudoVREDAND_VS_M4_E64, VREDAND_VS }, // 7239 |
| 28510 | { PseudoVREDAND_VS_M4_E64_MASK, VREDAND_VS }, // 7240 |
| 28511 | { PseudoVREDAND_VS_M4_E8, VREDAND_VS }, // 7241 |
| 28512 | { PseudoVREDAND_VS_M4_E8_MASK, VREDAND_VS }, // 7242 |
| 28513 | { PseudoVREDAND_VS_M8_E16, VREDAND_VS }, // 7243 |
| 28514 | { PseudoVREDAND_VS_M8_E16_MASK, VREDAND_VS }, // 7244 |
| 28515 | { PseudoVREDAND_VS_M8_E32, VREDAND_VS }, // 7245 |
| 28516 | { PseudoVREDAND_VS_M8_E32_MASK, VREDAND_VS }, // 7246 |
| 28517 | { PseudoVREDAND_VS_M8_E64, VREDAND_VS }, // 7247 |
| 28518 | { PseudoVREDAND_VS_M8_E64_MASK, VREDAND_VS }, // 7248 |
| 28519 | { PseudoVREDAND_VS_M8_E8, VREDAND_VS }, // 7249 |
| 28520 | { PseudoVREDAND_VS_M8_E8_MASK, VREDAND_VS }, // 7250 |
| 28521 | { PseudoVREDAND_VS_MF2_E16, VREDAND_VS }, // 7251 |
| 28522 | { PseudoVREDAND_VS_MF2_E16_MASK, VREDAND_VS }, // 7252 |
| 28523 | { PseudoVREDAND_VS_MF2_E32, VREDAND_VS }, // 7253 |
| 28524 | { PseudoVREDAND_VS_MF2_E32_MASK, VREDAND_VS }, // 7254 |
| 28525 | { PseudoVREDAND_VS_MF2_E8, VREDAND_VS }, // 7255 |
| 28526 | { PseudoVREDAND_VS_MF2_E8_MASK, VREDAND_VS }, // 7256 |
| 28527 | { PseudoVREDAND_VS_MF4_E16, VREDAND_VS }, // 7257 |
| 28528 | { PseudoVREDAND_VS_MF4_E16_MASK, VREDAND_VS }, // 7258 |
| 28529 | { PseudoVREDAND_VS_MF4_E8, VREDAND_VS }, // 7259 |
| 28530 | { PseudoVREDAND_VS_MF4_E8_MASK, VREDAND_VS }, // 7260 |
| 28531 | { PseudoVREDAND_VS_MF8_E8, VREDAND_VS }, // 7261 |
| 28532 | { PseudoVREDAND_VS_MF8_E8_MASK, VREDAND_VS }, // 7262 |
| 28533 | { PseudoVREDMAXU_VS_M1_E16, VREDMAXU_VS }, // 7263 |
| 28534 | { PseudoVREDMAXU_VS_M1_E16_MASK, VREDMAXU_VS }, // 7264 |
| 28535 | { PseudoVREDMAXU_VS_M1_E32, VREDMAXU_VS }, // 7265 |
| 28536 | { PseudoVREDMAXU_VS_M1_E32_MASK, VREDMAXU_VS }, // 7266 |
| 28537 | { PseudoVREDMAXU_VS_M1_E64, VREDMAXU_VS }, // 7267 |
| 28538 | { PseudoVREDMAXU_VS_M1_E64_MASK, VREDMAXU_VS }, // 7268 |
| 28539 | { PseudoVREDMAXU_VS_M1_E8, VREDMAXU_VS }, // 7269 |
| 28540 | { PseudoVREDMAXU_VS_M1_E8_MASK, VREDMAXU_VS }, // 7270 |
| 28541 | { PseudoVREDMAXU_VS_M2_E16, VREDMAXU_VS }, // 7271 |
| 28542 | { PseudoVREDMAXU_VS_M2_E16_MASK, VREDMAXU_VS }, // 7272 |
| 28543 | { PseudoVREDMAXU_VS_M2_E32, VREDMAXU_VS }, // 7273 |
| 28544 | { PseudoVREDMAXU_VS_M2_E32_MASK, VREDMAXU_VS }, // 7274 |
| 28545 | { PseudoVREDMAXU_VS_M2_E64, VREDMAXU_VS }, // 7275 |
| 28546 | { PseudoVREDMAXU_VS_M2_E64_MASK, VREDMAXU_VS }, // 7276 |
| 28547 | { PseudoVREDMAXU_VS_M2_E8, VREDMAXU_VS }, // 7277 |
| 28548 | { PseudoVREDMAXU_VS_M2_E8_MASK, VREDMAXU_VS }, // 7278 |
| 28549 | { PseudoVREDMAXU_VS_M4_E16, VREDMAXU_VS }, // 7279 |
| 28550 | { PseudoVREDMAXU_VS_M4_E16_MASK, VREDMAXU_VS }, // 7280 |
| 28551 | { PseudoVREDMAXU_VS_M4_E32, VREDMAXU_VS }, // 7281 |
| 28552 | { PseudoVREDMAXU_VS_M4_E32_MASK, VREDMAXU_VS }, // 7282 |
| 28553 | { PseudoVREDMAXU_VS_M4_E64, VREDMAXU_VS }, // 7283 |
| 28554 | { PseudoVREDMAXU_VS_M4_E64_MASK, VREDMAXU_VS }, // 7284 |
| 28555 | { PseudoVREDMAXU_VS_M4_E8, VREDMAXU_VS }, // 7285 |
| 28556 | { PseudoVREDMAXU_VS_M4_E8_MASK, VREDMAXU_VS }, // 7286 |
| 28557 | { PseudoVREDMAXU_VS_M8_E16, VREDMAXU_VS }, // 7287 |
| 28558 | { PseudoVREDMAXU_VS_M8_E16_MASK, VREDMAXU_VS }, // 7288 |
| 28559 | { PseudoVREDMAXU_VS_M8_E32, VREDMAXU_VS }, // 7289 |
| 28560 | { PseudoVREDMAXU_VS_M8_E32_MASK, VREDMAXU_VS }, // 7290 |
| 28561 | { PseudoVREDMAXU_VS_M8_E64, VREDMAXU_VS }, // 7291 |
| 28562 | { PseudoVREDMAXU_VS_M8_E64_MASK, VREDMAXU_VS }, // 7292 |
| 28563 | { PseudoVREDMAXU_VS_M8_E8, VREDMAXU_VS }, // 7293 |
| 28564 | { PseudoVREDMAXU_VS_M8_E8_MASK, VREDMAXU_VS }, // 7294 |
| 28565 | { PseudoVREDMAXU_VS_MF2_E16, VREDMAXU_VS }, // 7295 |
| 28566 | { PseudoVREDMAXU_VS_MF2_E16_MASK, VREDMAXU_VS }, // 7296 |
| 28567 | { PseudoVREDMAXU_VS_MF2_E32, VREDMAXU_VS }, // 7297 |
| 28568 | { PseudoVREDMAXU_VS_MF2_E32_MASK, VREDMAXU_VS }, // 7298 |
| 28569 | { PseudoVREDMAXU_VS_MF2_E8, VREDMAXU_VS }, // 7299 |
| 28570 | { PseudoVREDMAXU_VS_MF2_E8_MASK, VREDMAXU_VS }, // 7300 |
| 28571 | { PseudoVREDMAXU_VS_MF4_E16, VREDMAXU_VS }, // 7301 |
| 28572 | { PseudoVREDMAXU_VS_MF4_E16_MASK, VREDMAXU_VS }, // 7302 |
| 28573 | { PseudoVREDMAXU_VS_MF4_E8, VREDMAXU_VS }, // 7303 |
| 28574 | { PseudoVREDMAXU_VS_MF4_E8_MASK, VREDMAXU_VS }, // 7304 |
| 28575 | { PseudoVREDMAXU_VS_MF8_E8, VREDMAXU_VS }, // 7305 |
| 28576 | { PseudoVREDMAXU_VS_MF8_E8_MASK, VREDMAXU_VS }, // 7306 |
| 28577 | { PseudoVREDMAX_VS_M1_E16, VREDMAX_VS }, // 7307 |
| 28578 | { PseudoVREDMAX_VS_M1_E16_MASK, VREDMAX_VS }, // 7308 |
| 28579 | { PseudoVREDMAX_VS_M1_E32, VREDMAX_VS }, // 7309 |
| 28580 | { PseudoVREDMAX_VS_M1_E32_MASK, VREDMAX_VS }, // 7310 |
| 28581 | { PseudoVREDMAX_VS_M1_E64, VREDMAX_VS }, // 7311 |
| 28582 | { PseudoVREDMAX_VS_M1_E64_MASK, VREDMAX_VS }, // 7312 |
| 28583 | { PseudoVREDMAX_VS_M1_E8, VREDMAX_VS }, // 7313 |
| 28584 | { PseudoVREDMAX_VS_M1_E8_MASK, VREDMAX_VS }, // 7314 |
| 28585 | { PseudoVREDMAX_VS_M2_E16, VREDMAX_VS }, // 7315 |
| 28586 | { PseudoVREDMAX_VS_M2_E16_MASK, VREDMAX_VS }, // 7316 |
| 28587 | { PseudoVREDMAX_VS_M2_E32, VREDMAX_VS }, // 7317 |
| 28588 | { PseudoVREDMAX_VS_M2_E32_MASK, VREDMAX_VS }, // 7318 |
| 28589 | { PseudoVREDMAX_VS_M2_E64, VREDMAX_VS }, // 7319 |
| 28590 | { PseudoVREDMAX_VS_M2_E64_MASK, VREDMAX_VS }, // 7320 |
| 28591 | { PseudoVREDMAX_VS_M2_E8, VREDMAX_VS }, // 7321 |
| 28592 | { PseudoVREDMAX_VS_M2_E8_MASK, VREDMAX_VS }, // 7322 |
| 28593 | { PseudoVREDMAX_VS_M4_E16, VREDMAX_VS }, // 7323 |
| 28594 | { PseudoVREDMAX_VS_M4_E16_MASK, VREDMAX_VS }, // 7324 |
| 28595 | { PseudoVREDMAX_VS_M4_E32, VREDMAX_VS }, // 7325 |
| 28596 | { PseudoVREDMAX_VS_M4_E32_MASK, VREDMAX_VS }, // 7326 |
| 28597 | { PseudoVREDMAX_VS_M4_E64, VREDMAX_VS }, // 7327 |
| 28598 | { PseudoVREDMAX_VS_M4_E64_MASK, VREDMAX_VS }, // 7328 |
| 28599 | { PseudoVREDMAX_VS_M4_E8, VREDMAX_VS }, // 7329 |
| 28600 | { PseudoVREDMAX_VS_M4_E8_MASK, VREDMAX_VS }, // 7330 |
| 28601 | { PseudoVREDMAX_VS_M8_E16, VREDMAX_VS }, // 7331 |
| 28602 | { PseudoVREDMAX_VS_M8_E16_MASK, VREDMAX_VS }, // 7332 |
| 28603 | { PseudoVREDMAX_VS_M8_E32, VREDMAX_VS }, // 7333 |
| 28604 | { PseudoVREDMAX_VS_M8_E32_MASK, VREDMAX_VS }, // 7334 |
| 28605 | { PseudoVREDMAX_VS_M8_E64, VREDMAX_VS }, // 7335 |
| 28606 | { PseudoVREDMAX_VS_M8_E64_MASK, VREDMAX_VS }, // 7336 |
| 28607 | { PseudoVREDMAX_VS_M8_E8, VREDMAX_VS }, // 7337 |
| 28608 | { PseudoVREDMAX_VS_M8_E8_MASK, VREDMAX_VS }, // 7338 |
| 28609 | { PseudoVREDMAX_VS_MF2_E16, VREDMAX_VS }, // 7339 |
| 28610 | { PseudoVREDMAX_VS_MF2_E16_MASK, VREDMAX_VS }, // 7340 |
| 28611 | { PseudoVREDMAX_VS_MF2_E32, VREDMAX_VS }, // 7341 |
| 28612 | { PseudoVREDMAX_VS_MF2_E32_MASK, VREDMAX_VS }, // 7342 |
| 28613 | { PseudoVREDMAX_VS_MF2_E8, VREDMAX_VS }, // 7343 |
| 28614 | { PseudoVREDMAX_VS_MF2_E8_MASK, VREDMAX_VS }, // 7344 |
| 28615 | { PseudoVREDMAX_VS_MF4_E16, VREDMAX_VS }, // 7345 |
| 28616 | { PseudoVREDMAX_VS_MF4_E16_MASK, VREDMAX_VS }, // 7346 |
| 28617 | { PseudoVREDMAX_VS_MF4_E8, VREDMAX_VS }, // 7347 |
| 28618 | { PseudoVREDMAX_VS_MF4_E8_MASK, VREDMAX_VS }, // 7348 |
| 28619 | { PseudoVREDMAX_VS_MF8_E8, VREDMAX_VS }, // 7349 |
| 28620 | { PseudoVREDMAX_VS_MF8_E8_MASK, VREDMAX_VS }, // 7350 |
| 28621 | { PseudoVREDMINU_VS_M1_E16, VREDMINU_VS }, // 7351 |
| 28622 | { PseudoVREDMINU_VS_M1_E16_MASK, VREDMINU_VS }, // 7352 |
| 28623 | { PseudoVREDMINU_VS_M1_E32, VREDMINU_VS }, // 7353 |
| 28624 | { PseudoVREDMINU_VS_M1_E32_MASK, VREDMINU_VS }, // 7354 |
| 28625 | { PseudoVREDMINU_VS_M1_E64, VREDMINU_VS }, // 7355 |
| 28626 | { PseudoVREDMINU_VS_M1_E64_MASK, VREDMINU_VS }, // 7356 |
| 28627 | { PseudoVREDMINU_VS_M1_E8, VREDMINU_VS }, // 7357 |
| 28628 | { PseudoVREDMINU_VS_M1_E8_MASK, VREDMINU_VS }, // 7358 |
| 28629 | { PseudoVREDMINU_VS_M2_E16, VREDMINU_VS }, // 7359 |
| 28630 | { PseudoVREDMINU_VS_M2_E16_MASK, VREDMINU_VS }, // 7360 |
| 28631 | { PseudoVREDMINU_VS_M2_E32, VREDMINU_VS }, // 7361 |
| 28632 | { PseudoVREDMINU_VS_M2_E32_MASK, VREDMINU_VS }, // 7362 |
| 28633 | { PseudoVREDMINU_VS_M2_E64, VREDMINU_VS }, // 7363 |
| 28634 | { PseudoVREDMINU_VS_M2_E64_MASK, VREDMINU_VS }, // 7364 |
| 28635 | { PseudoVREDMINU_VS_M2_E8, VREDMINU_VS }, // 7365 |
| 28636 | { PseudoVREDMINU_VS_M2_E8_MASK, VREDMINU_VS }, // 7366 |
| 28637 | { PseudoVREDMINU_VS_M4_E16, VREDMINU_VS }, // 7367 |
| 28638 | { PseudoVREDMINU_VS_M4_E16_MASK, VREDMINU_VS }, // 7368 |
| 28639 | { PseudoVREDMINU_VS_M4_E32, VREDMINU_VS }, // 7369 |
| 28640 | { PseudoVREDMINU_VS_M4_E32_MASK, VREDMINU_VS }, // 7370 |
| 28641 | { PseudoVREDMINU_VS_M4_E64, VREDMINU_VS }, // 7371 |
| 28642 | { PseudoVREDMINU_VS_M4_E64_MASK, VREDMINU_VS }, // 7372 |
| 28643 | { PseudoVREDMINU_VS_M4_E8, VREDMINU_VS }, // 7373 |
| 28644 | { PseudoVREDMINU_VS_M4_E8_MASK, VREDMINU_VS }, // 7374 |
| 28645 | { PseudoVREDMINU_VS_M8_E16, VREDMINU_VS }, // 7375 |
| 28646 | { PseudoVREDMINU_VS_M8_E16_MASK, VREDMINU_VS }, // 7376 |
| 28647 | { PseudoVREDMINU_VS_M8_E32, VREDMINU_VS }, // 7377 |
| 28648 | { PseudoVREDMINU_VS_M8_E32_MASK, VREDMINU_VS }, // 7378 |
| 28649 | { PseudoVREDMINU_VS_M8_E64, VREDMINU_VS }, // 7379 |
| 28650 | { PseudoVREDMINU_VS_M8_E64_MASK, VREDMINU_VS }, // 7380 |
| 28651 | { PseudoVREDMINU_VS_M8_E8, VREDMINU_VS }, // 7381 |
| 28652 | { PseudoVREDMINU_VS_M8_E8_MASK, VREDMINU_VS }, // 7382 |
| 28653 | { PseudoVREDMINU_VS_MF2_E16, VREDMINU_VS }, // 7383 |
| 28654 | { PseudoVREDMINU_VS_MF2_E16_MASK, VREDMINU_VS }, // 7384 |
| 28655 | { PseudoVREDMINU_VS_MF2_E32, VREDMINU_VS }, // 7385 |
| 28656 | { PseudoVREDMINU_VS_MF2_E32_MASK, VREDMINU_VS }, // 7386 |
| 28657 | { PseudoVREDMINU_VS_MF2_E8, VREDMINU_VS }, // 7387 |
| 28658 | { PseudoVREDMINU_VS_MF2_E8_MASK, VREDMINU_VS }, // 7388 |
| 28659 | { PseudoVREDMINU_VS_MF4_E16, VREDMINU_VS }, // 7389 |
| 28660 | { PseudoVREDMINU_VS_MF4_E16_MASK, VREDMINU_VS }, // 7390 |
| 28661 | { PseudoVREDMINU_VS_MF4_E8, VREDMINU_VS }, // 7391 |
| 28662 | { PseudoVREDMINU_VS_MF4_E8_MASK, VREDMINU_VS }, // 7392 |
| 28663 | { PseudoVREDMINU_VS_MF8_E8, VREDMINU_VS }, // 7393 |
| 28664 | { PseudoVREDMINU_VS_MF8_E8_MASK, VREDMINU_VS }, // 7394 |
| 28665 | { PseudoVREDMIN_VS_M1_E16, VREDMIN_VS }, // 7395 |
| 28666 | { PseudoVREDMIN_VS_M1_E16_MASK, VREDMIN_VS }, // 7396 |
| 28667 | { PseudoVREDMIN_VS_M1_E32, VREDMIN_VS }, // 7397 |
| 28668 | { PseudoVREDMIN_VS_M1_E32_MASK, VREDMIN_VS }, // 7398 |
| 28669 | { PseudoVREDMIN_VS_M1_E64, VREDMIN_VS }, // 7399 |
| 28670 | { PseudoVREDMIN_VS_M1_E64_MASK, VREDMIN_VS }, // 7400 |
| 28671 | { PseudoVREDMIN_VS_M1_E8, VREDMIN_VS }, // 7401 |
| 28672 | { PseudoVREDMIN_VS_M1_E8_MASK, VREDMIN_VS }, // 7402 |
| 28673 | { PseudoVREDMIN_VS_M2_E16, VREDMIN_VS }, // 7403 |
| 28674 | { PseudoVREDMIN_VS_M2_E16_MASK, VREDMIN_VS }, // 7404 |
| 28675 | { PseudoVREDMIN_VS_M2_E32, VREDMIN_VS }, // 7405 |
| 28676 | { PseudoVREDMIN_VS_M2_E32_MASK, VREDMIN_VS }, // 7406 |
| 28677 | { PseudoVREDMIN_VS_M2_E64, VREDMIN_VS }, // 7407 |
| 28678 | { PseudoVREDMIN_VS_M2_E64_MASK, VREDMIN_VS }, // 7408 |
| 28679 | { PseudoVREDMIN_VS_M2_E8, VREDMIN_VS }, // 7409 |
| 28680 | { PseudoVREDMIN_VS_M2_E8_MASK, VREDMIN_VS }, // 7410 |
| 28681 | { PseudoVREDMIN_VS_M4_E16, VREDMIN_VS }, // 7411 |
| 28682 | { PseudoVREDMIN_VS_M4_E16_MASK, VREDMIN_VS }, // 7412 |
| 28683 | { PseudoVREDMIN_VS_M4_E32, VREDMIN_VS }, // 7413 |
| 28684 | { PseudoVREDMIN_VS_M4_E32_MASK, VREDMIN_VS }, // 7414 |
| 28685 | { PseudoVREDMIN_VS_M4_E64, VREDMIN_VS }, // 7415 |
| 28686 | { PseudoVREDMIN_VS_M4_E64_MASK, VREDMIN_VS }, // 7416 |
| 28687 | { PseudoVREDMIN_VS_M4_E8, VREDMIN_VS }, // 7417 |
| 28688 | { PseudoVREDMIN_VS_M4_E8_MASK, VREDMIN_VS }, // 7418 |
| 28689 | { PseudoVREDMIN_VS_M8_E16, VREDMIN_VS }, // 7419 |
| 28690 | { PseudoVREDMIN_VS_M8_E16_MASK, VREDMIN_VS }, // 7420 |
| 28691 | { PseudoVREDMIN_VS_M8_E32, VREDMIN_VS }, // 7421 |
| 28692 | { PseudoVREDMIN_VS_M8_E32_MASK, VREDMIN_VS }, // 7422 |
| 28693 | { PseudoVREDMIN_VS_M8_E64, VREDMIN_VS }, // 7423 |
| 28694 | { PseudoVREDMIN_VS_M8_E64_MASK, VREDMIN_VS }, // 7424 |
| 28695 | { PseudoVREDMIN_VS_M8_E8, VREDMIN_VS }, // 7425 |
| 28696 | { PseudoVREDMIN_VS_M8_E8_MASK, VREDMIN_VS }, // 7426 |
| 28697 | { PseudoVREDMIN_VS_MF2_E16, VREDMIN_VS }, // 7427 |
| 28698 | { PseudoVREDMIN_VS_MF2_E16_MASK, VREDMIN_VS }, // 7428 |
| 28699 | { PseudoVREDMIN_VS_MF2_E32, VREDMIN_VS }, // 7429 |
| 28700 | { PseudoVREDMIN_VS_MF2_E32_MASK, VREDMIN_VS }, // 7430 |
| 28701 | { PseudoVREDMIN_VS_MF2_E8, VREDMIN_VS }, // 7431 |
| 28702 | { PseudoVREDMIN_VS_MF2_E8_MASK, VREDMIN_VS }, // 7432 |
| 28703 | { PseudoVREDMIN_VS_MF4_E16, VREDMIN_VS }, // 7433 |
| 28704 | { PseudoVREDMIN_VS_MF4_E16_MASK, VREDMIN_VS }, // 7434 |
| 28705 | { PseudoVREDMIN_VS_MF4_E8, VREDMIN_VS }, // 7435 |
| 28706 | { PseudoVREDMIN_VS_MF4_E8_MASK, VREDMIN_VS }, // 7436 |
| 28707 | { PseudoVREDMIN_VS_MF8_E8, VREDMIN_VS }, // 7437 |
| 28708 | { PseudoVREDMIN_VS_MF8_E8_MASK, VREDMIN_VS }, // 7438 |
| 28709 | { PseudoVREDOR_VS_M1_E16, VREDOR_VS }, // 7439 |
| 28710 | { PseudoVREDOR_VS_M1_E16_MASK, VREDOR_VS }, // 7440 |
| 28711 | { PseudoVREDOR_VS_M1_E32, VREDOR_VS }, // 7441 |
| 28712 | { PseudoVREDOR_VS_M1_E32_MASK, VREDOR_VS }, // 7442 |
| 28713 | { PseudoVREDOR_VS_M1_E64, VREDOR_VS }, // 7443 |
| 28714 | { PseudoVREDOR_VS_M1_E64_MASK, VREDOR_VS }, // 7444 |
| 28715 | { PseudoVREDOR_VS_M1_E8, VREDOR_VS }, // 7445 |
| 28716 | { PseudoVREDOR_VS_M1_E8_MASK, VREDOR_VS }, // 7446 |
| 28717 | { PseudoVREDOR_VS_M2_E16, VREDOR_VS }, // 7447 |
| 28718 | { PseudoVREDOR_VS_M2_E16_MASK, VREDOR_VS }, // 7448 |
| 28719 | { PseudoVREDOR_VS_M2_E32, VREDOR_VS }, // 7449 |
| 28720 | { PseudoVREDOR_VS_M2_E32_MASK, VREDOR_VS }, // 7450 |
| 28721 | { PseudoVREDOR_VS_M2_E64, VREDOR_VS }, // 7451 |
| 28722 | { PseudoVREDOR_VS_M2_E64_MASK, VREDOR_VS }, // 7452 |
| 28723 | { PseudoVREDOR_VS_M2_E8, VREDOR_VS }, // 7453 |
| 28724 | { PseudoVREDOR_VS_M2_E8_MASK, VREDOR_VS }, // 7454 |
| 28725 | { PseudoVREDOR_VS_M4_E16, VREDOR_VS }, // 7455 |
| 28726 | { PseudoVREDOR_VS_M4_E16_MASK, VREDOR_VS }, // 7456 |
| 28727 | { PseudoVREDOR_VS_M4_E32, VREDOR_VS }, // 7457 |
| 28728 | { PseudoVREDOR_VS_M4_E32_MASK, VREDOR_VS }, // 7458 |
| 28729 | { PseudoVREDOR_VS_M4_E64, VREDOR_VS }, // 7459 |
| 28730 | { PseudoVREDOR_VS_M4_E64_MASK, VREDOR_VS }, // 7460 |
| 28731 | { PseudoVREDOR_VS_M4_E8, VREDOR_VS }, // 7461 |
| 28732 | { PseudoVREDOR_VS_M4_E8_MASK, VREDOR_VS }, // 7462 |
| 28733 | { PseudoVREDOR_VS_M8_E16, VREDOR_VS }, // 7463 |
| 28734 | { PseudoVREDOR_VS_M8_E16_MASK, VREDOR_VS }, // 7464 |
| 28735 | { PseudoVREDOR_VS_M8_E32, VREDOR_VS }, // 7465 |
| 28736 | { PseudoVREDOR_VS_M8_E32_MASK, VREDOR_VS }, // 7466 |
| 28737 | { PseudoVREDOR_VS_M8_E64, VREDOR_VS }, // 7467 |
| 28738 | { PseudoVREDOR_VS_M8_E64_MASK, VREDOR_VS }, // 7468 |
| 28739 | { PseudoVREDOR_VS_M8_E8, VREDOR_VS }, // 7469 |
| 28740 | { PseudoVREDOR_VS_M8_E8_MASK, VREDOR_VS }, // 7470 |
| 28741 | { PseudoVREDOR_VS_MF2_E16, VREDOR_VS }, // 7471 |
| 28742 | { PseudoVREDOR_VS_MF2_E16_MASK, VREDOR_VS }, // 7472 |
| 28743 | { PseudoVREDOR_VS_MF2_E32, VREDOR_VS }, // 7473 |
| 28744 | { PseudoVREDOR_VS_MF2_E32_MASK, VREDOR_VS }, // 7474 |
| 28745 | { PseudoVREDOR_VS_MF2_E8, VREDOR_VS }, // 7475 |
| 28746 | { PseudoVREDOR_VS_MF2_E8_MASK, VREDOR_VS }, // 7476 |
| 28747 | { PseudoVREDOR_VS_MF4_E16, VREDOR_VS }, // 7477 |
| 28748 | { PseudoVREDOR_VS_MF4_E16_MASK, VREDOR_VS }, // 7478 |
| 28749 | { PseudoVREDOR_VS_MF4_E8, VREDOR_VS }, // 7479 |
| 28750 | { PseudoVREDOR_VS_MF4_E8_MASK, VREDOR_VS }, // 7480 |
| 28751 | { PseudoVREDOR_VS_MF8_E8, VREDOR_VS }, // 7481 |
| 28752 | { PseudoVREDOR_VS_MF8_E8_MASK, VREDOR_VS }, // 7482 |
| 28753 | { PseudoVREDSUM_VS_M1_E16, VREDSUM_VS }, // 7483 |
| 28754 | { PseudoVREDSUM_VS_M1_E16_MASK, VREDSUM_VS }, // 7484 |
| 28755 | { PseudoVREDSUM_VS_M1_E32, VREDSUM_VS }, // 7485 |
| 28756 | { PseudoVREDSUM_VS_M1_E32_MASK, VREDSUM_VS }, // 7486 |
| 28757 | { PseudoVREDSUM_VS_M1_E64, VREDSUM_VS }, // 7487 |
| 28758 | { PseudoVREDSUM_VS_M1_E64_MASK, VREDSUM_VS }, // 7488 |
| 28759 | { PseudoVREDSUM_VS_M1_E8, VREDSUM_VS }, // 7489 |
| 28760 | { PseudoVREDSUM_VS_M1_E8_MASK, VREDSUM_VS }, // 7490 |
| 28761 | { PseudoVREDSUM_VS_M2_E16, VREDSUM_VS }, // 7491 |
| 28762 | { PseudoVREDSUM_VS_M2_E16_MASK, VREDSUM_VS }, // 7492 |
| 28763 | { PseudoVREDSUM_VS_M2_E32, VREDSUM_VS }, // 7493 |
| 28764 | { PseudoVREDSUM_VS_M2_E32_MASK, VREDSUM_VS }, // 7494 |
| 28765 | { PseudoVREDSUM_VS_M2_E64, VREDSUM_VS }, // 7495 |
| 28766 | { PseudoVREDSUM_VS_M2_E64_MASK, VREDSUM_VS }, // 7496 |
| 28767 | { PseudoVREDSUM_VS_M2_E8, VREDSUM_VS }, // 7497 |
| 28768 | { PseudoVREDSUM_VS_M2_E8_MASK, VREDSUM_VS }, // 7498 |
| 28769 | { PseudoVREDSUM_VS_M4_E16, VREDSUM_VS }, // 7499 |
| 28770 | { PseudoVREDSUM_VS_M4_E16_MASK, VREDSUM_VS }, // 7500 |
| 28771 | { PseudoVREDSUM_VS_M4_E32, VREDSUM_VS }, // 7501 |
| 28772 | { PseudoVREDSUM_VS_M4_E32_MASK, VREDSUM_VS }, // 7502 |
| 28773 | { PseudoVREDSUM_VS_M4_E64, VREDSUM_VS }, // 7503 |
| 28774 | { PseudoVREDSUM_VS_M4_E64_MASK, VREDSUM_VS }, // 7504 |
| 28775 | { PseudoVREDSUM_VS_M4_E8, VREDSUM_VS }, // 7505 |
| 28776 | { PseudoVREDSUM_VS_M4_E8_MASK, VREDSUM_VS }, // 7506 |
| 28777 | { PseudoVREDSUM_VS_M8_E16, VREDSUM_VS }, // 7507 |
| 28778 | { PseudoVREDSUM_VS_M8_E16_MASK, VREDSUM_VS }, // 7508 |
| 28779 | { PseudoVREDSUM_VS_M8_E32, VREDSUM_VS }, // 7509 |
| 28780 | { PseudoVREDSUM_VS_M8_E32_MASK, VREDSUM_VS }, // 7510 |
| 28781 | { PseudoVREDSUM_VS_M8_E64, VREDSUM_VS }, // 7511 |
| 28782 | { PseudoVREDSUM_VS_M8_E64_MASK, VREDSUM_VS }, // 7512 |
| 28783 | { PseudoVREDSUM_VS_M8_E8, VREDSUM_VS }, // 7513 |
| 28784 | { PseudoVREDSUM_VS_M8_E8_MASK, VREDSUM_VS }, // 7514 |
| 28785 | { PseudoVREDSUM_VS_MF2_E16, VREDSUM_VS }, // 7515 |
| 28786 | { PseudoVREDSUM_VS_MF2_E16_MASK, VREDSUM_VS }, // 7516 |
| 28787 | { PseudoVREDSUM_VS_MF2_E32, VREDSUM_VS }, // 7517 |
| 28788 | { PseudoVREDSUM_VS_MF2_E32_MASK, VREDSUM_VS }, // 7518 |
| 28789 | { PseudoVREDSUM_VS_MF2_E8, VREDSUM_VS }, // 7519 |
| 28790 | { PseudoVREDSUM_VS_MF2_E8_MASK, VREDSUM_VS }, // 7520 |
| 28791 | { PseudoVREDSUM_VS_MF4_E16, VREDSUM_VS }, // 7521 |
| 28792 | { PseudoVREDSUM_VS_MF4_E16_MASK, VREDSUM_VS }, // 7522 |
| 28793 | { PseudoVREDSUM_VS_MF4_E8, VREDSUM_VS }, // 7523 |
| 28794 | { PseudoVREDSUM_VS_MF4_E8_MASK, VREDSUM_VS }, // 7524 |
| 28795 | { PseudoVREDSUM_VS_MF8_E8, VREDSUM_VS }, // 7525 |
| 28796 | { PseudoVREDSUM_VS_MF8_E8_MASK, VREDSUM_VS }, // 7526 |
| 28797 | { PseudoVREDXOR_VS_M1_E16, VREDXOR_VS }, // 7527 |
| 28798 | { PseudoVREDXOR_VS_M1_E16_MASK, VREDXOR_VS }, // 7528 |
| 28799 | { PseudoVREDXOR_VS_M1_E32, VREDXOR_VS }, // 7529 |
| 28800 | { PseudoVREDXOR_VS_M1_E32_MASK, VREDXOR_VS }, // 7530 |
| 28801 | { PseudoVREDXOR_VS_M1_E64, VREDXOR_VS }, // 7531 |
| 28802 | { PseudoVREDXOR_VS_M1_E64_MASK, VREDXOR_VS }, // 7532 |
| 28803 | { PseudoVREDXOR_VS_M1_E8, VREDXOR_VS }, // 7533 |
| 28804 | { PseudoVREDXOR_VS_M1_E8_MASK, VREDXOR_VS }, // 7534 |
| 28805 | { PseudoVREDXOR_VS_M2_E16, VREDXOR_VS }, // 7535 |
| 28806 | { PseudoVREDXOR_VS_M2_E16_MASK, VREDXOR_VS }, // 7536 |
| 28807 | { PseudoVREDXOR_VS_M2_E32, VREDXOR_VS }, // 7537 |
| 28808 | { PseudoVREDXOR_VS_M2_E32_MASK, VREDXOR_VS }, // 7538 |
| 28809 | { PseudoVREDXOR_VS_M2_E64, VREDXOR_VS }, // 7539 |
| 28810 | { PseudoVREDXOR_VS_M2_E64_MASK, VREDXOR_VS }, // 7540 |
| 28811 | { PseudoVREDXOR_VS_M2_E8, VREDXOR_VS }, // 7541 |
| 28812 | { PseudoVREDXOR_VS_M2_E8_MASK, VREDXOR_VS }, // 7542 |
| 28813 | { PseudoVREDXOR_VS_M4_E16, VREDXOR_VS }, // 7543 |
| 28814 | { PseudoVREDXOR_VS_M4_E16_MASK, VREDXOR_VS }, // 7544 |
| 28815 | { PseudoVREDXOR_VS_M4_E32, VREDXOR_VS }, // 7545 |
| 28816 | { PseudoVREDXOR_VS_M4_E32_MASK, VREDXOR_VS }, // 7546 |
| 28817 | { PseudoVREDXOR_VS_M4_E64, VREDXOR_VS }, // 7547 |
| 28818 | { PseudoVREDXOR_VS_M4_E64_MASK, VREDXOR_VS }, // 7548 |
| 28819 | { PseudoVREDXOR_VS_M4_E8, VREDXOR_VS }, // 7549 |
| 28820 | { PseudoVREDXOR_VS_M4_E8_MASK, VREDXOR_VS }, // 7550 |
| 28821 | { PseudoVREDXOR_VS_M8_E16, VREDXOR_VS }, // 7551 |
| 28822 | { PseudoVREDXOR_VS_M8_E16_MASK, VREDXOR_VS }, // 7552 |
| 28823 | { PseudoVREDXOR_VS_M8_E32, VREDXOR_VS }, // 7553 |
| 28824 | { PseudoVREDXOR_VS_M8_E32_MASK, VREDXOR_VS }, // 7554 |
| 28825 | { PseudoVREDXOR_VS_M8_E64, VREDXOR_VS }, // 7555 |
| 28826 | { PseudoVREDXOR_VS_M8_E64_MASK, VREDXOR_VS }, // 7556 |
| 28827 | { PseudoVREDXOR_VS_M8_E8, VREDXOR_VS }, // 7557 |
| 28828 | { PseudoVREDXOR_VS_M8_E8_MASK, VREDXOR_VS }, // 7558 |
| 28829 | { PseudoVREDXOR_VS_MF2_E16, VREDXOR_VS }, // 7559 |
| 28830 | { PseudoVREDXOR_VS_MF2_E16_MASK, VREDXOR_VS }, // 7560 |
| 28831 | { PseudoVREDXOR_VS_MF2_E32, VREDXOR_VS }, // 7561 |
| 28832 | { PseudoVREDXOR_VS_MF2_E32_MASK, VREDXOR_VS }, // 7562 |
| 28833 | { PseudoVREDXOR_VS_MF2_E8, VREDXOR_VS }, // 7563 |
| 28834 | { PseudoVREDXOR_VS_MF2_E8_MASK, VREDXOR_VS }, // 7564 |
| 28835 | { PseudoVREDXOR_VS_MF4_E16, VREDXOR_VS }, // 7565 |
| 28836 | { PseudoVREDXOR_VS_MF4_E16_MASK, VREDXOR_VS }, // 7566 |
| 28837 | { PseudoVREDXOR_VS_MF4_E8, VREDXOR_VS }, // 7567 |
| 28838 | { PseudoVREDXOR_VS_MF4_E8_MASK, VREDXOR_VS }, // 7568 |
| 28839 | { PseudoVREDXOR_VS_MF8_E8, VREDXOR_VS }, // 7569 |
| 28840 | { PseudoVREDXOR_VS_MF8_E8_MASK, VREDXOR_VS }, // 7570 |
| 28841 | { PseudoVREMU_VV_M1_E16, VREMU_VV }, // 7571 |
| 28842 | { PseudoVREMU_VV_M1_E16_MASK, VREMU_VV }, // 7572 |
| 28843 | { PseudoVREMU_VV_M1_E32, VREMU_VV }, // 7573 |
| 28844 | { PseudoVREMU_VV_M1_E32_MASK, VREMU_VV }, // 7574 |
| 28845 | { PseudoVREMU_VV_M1_E64, VREMU_VV }, // 7575 |
| 28846 | { PseudoVREMU_VV_M1_E64_MASK, VREMU_VV }, // 7576 |
| 28847 | { PseudoVREMU_VV_M1_E8, VREMU_VV }, // 7577 |
| 28848 | { PseudoVREMU_VV_M1_E8_MASK, VREMU_VV }, // 7578 |
| 28849 | { PseudoVREMU_VV_M2_E16, VREMU_VV }, // 7579 |
| 28850 | { PseudoVREMU_VV_M2_E16_MASK, VREMU_VV }, // 7580 |
| 28851 | { PseudoVREMU_VV_M2_E32, VREMU_VV }, // 7581 |
| 28852 | { PseudoVREMU_VV_M2_E32_MASK, VREMU_VV }, // 7582 |
| 28853 | { PseudoVREMU_VV_M2_E64, VREMU_VV }, // 7583 |
| 28854 | { PseudoVREMU_VV_M2_E64_MASK, VREMU_VV }, // 7584 |
| 28855 | { PseudoVREMU_VV_M2_E8, VREMU_VV }, // 7585 |
| 28856 | { PseudoVREMU_VV_M2_E8_MASK, VREMU_VV }, // 7586 |
| 28857 | { PseudoVREMU_VV_M4_E16, VREMU_VV }, // 7587 |
| 28858 | { PseudoVREMU_VV_M4_E16_MASK, VREMU_VV }, // 7588 |
| 28859 | { PseudoVREMU_VV_M4_E32, VREMU_VV }, // 7589 |
| 28860 | { PseudoVREMU_VV_M4_E32_MASK, VREMU_VV }, // 7590 |
| 28861 | { PseudoVREMU_VV_M4_E64, VREMU_VV }, // 7591 |
| 28862 | { PseudoVREMU_VV_M4_E64_MASK, VREMU_VV }, // 7592 |
| 28863 | { PseudoVREMU_VV_M4_E8, VREMU_VV }, // 7593 |
| 28864 | { PseudoVREMU_VV_M4_E8_MASK, VREMU_VV }, // 7594 |
| 28865 | { PseudoVREMU_VV_M8_E16, VREMU_VV }, // 7595 |
| 28866 | { PseudoVREMU_VV_M8_E16_MASK, VREMU_VV }, // 7596 |
| 28867 | { PseudoVREMU_VV_M8_E32, VREMU_VV }, // 7597 |
| 28868 | { PseudoVREMU_VV_M8_E32_MASK, VREMU_VV }, // 7598 |
| 28869 | { PseudoVREMU_VV_M8_E64, VREMU_VV }, // 7599 |
| 28870 | { PseudoVREMU_VV_M8_E64_MASK, VREMU_VV }, // 7600 |
| 28871 | { PseudoVREMU_VV_M8_E8, VREMU_VV }, // 7601 |
| 28872 | { PseudoVREMU_VV_M8_E8_MASK, VREMU_VV }, // 7602 |
| 28873 | { PseudoVREMU_VV_MF2_E16, VREMU_VV }, // 7603 |
| 28874 | { PseudoVREMU_VV_MF2_E16_MASK, VREMU_VV }, // 7604 |
| 28875 | { PseudoVREMU_VV_MF2_E32, VREMU_VV }, // 7605 |
| 28876 | { PseudoVREMU_VV_MF2_E32_MASK, VREMU_VV }, // 7606 |
| 28877 | { PseudoVREMU_VV_MF2_E8, VREMU_VV }, // 7607 |
| 28878 | { PseudoVREMU_VV_MF2_E8_MASK, VREMU_VV }, // 7608 |
| 28879 | { PseudoVREMU_VV_MF4_E16, VREMU_VV }, // 7609 |
| 28880 | { PseudoVREMU_VV_MF4_E16_MASK, VREMU_VV }, // 7610 |
| 28881 | { PseudoVREMU_VV_MF4_E8, VREMU_VV }, // 7611 |
| 28882 | { PseudoVREMU_VV_MF4_E8_MASK, VREMU_VV }, // 7612 |
| 28883 | { PseudoVREMU_VV_MF8_E8, VREMU_VV }, // 7613 |
| 28884 | { PseudoVREMU_VV_MF8_E8_MASK, VREMU_VV }, // 7614 |
| 28885 | { PseudoVREMU_VX_M1_E16, VREMU_VX }, // 7615 |
| 28886 | { PseudoVREMU_VX_M1_E16_MASK, VREMU_VX }, // 7616 |
| 28887 | { PseudoVREMU_VX_M1_E32, VREMU_VX }, // 7617 |
| 28888 | { PseudoVREMU_VX_M1_E32_MASK, VREMU_VX }, // 7618 |
| 28889 | { PseudoVREMU_VX_M1_E64, VREMU_VX }, // 7619 |
| 28890 | { PseudoVREMU_VX_M1_E64_MASK, VREMU_VX }, // 7620 |
| 28891 | { PseudoVREMU_VX_M1_E8, VREMU_VX }, // 7621 |
| 28892 | { PseudoVREMU_VX_M1_E8_MASK, VREMU_VX }, // 7622 |
| 28893 | { PseudoVREMU_VX_M2_E16, VREMU_VX }, // 7623 |
| 28894 | { PseudoVREMU_VX_M2_E16_MASK, VREMU_VX }, // 7624 |
| 28895 | { PseudoVREMU_VX_M2_E32, VREMU_VX }, // 7625 |
| 28896 | { PseudoVREMU_VX_M2_E32_MASK, VREMU_VX }, // 7626 |
| 28897 | { PseudoVREMU_VX_M2_E64, VREMU_VX }, // 7627 |
| 28898 | { PseudoVREMU_VX_M2_E64_MASK, VREMU_VX }, // 7628 |
| 28899 | { PseudoVREMU_VX_M2_E8, VREMU_VX }, // 7629 |
| 28900 | { PseudoVREMU_VX_M2_E8_MASK, VREMU_VX }, // 7630 |
| 28901 | { PseudoVREMU_VX_M4_E16, VREMU_VX }, // 7631 |
| 28902 | { PseudoVREMU_VX_M4_E16_MASK, VREMU_VX }, // 7632 |
| 28903 | { PseudoVREMU_VX_M4_E32, VREMU_VX }, // 7633 |
| 28904 | { PseudoVREMU_VX_M4_E32_MASK, VREMU_VX }, // 7634 |
| 28905 | { PseudoVREMU_VX_M4_E64, VREMU_VX }, // 7635 |
| 28906 | { PseudoVREMU_VX_M4_E64_MASK, VREMU_VX }, // 7636 |
| 28907 | { PseudoVREMU_VX_M4_E8, VREMU_VX }, // 7637 |
| 28908 | { PseudoVREMU_VX_M4_E8_MASK, VREMU_VX }, // 7638 |
| 28909 | { PseudoVREMU_VX_M8_E16, VREMU_VX }, // 7639 |
| 28910 | { PseudoVREMU_VX_M8_E16_MASK, VREMU_VX }, // 7640 |
| 28911 | { PseudoVREMU_VX_M8_E32, VREMU_VX }, // 7641 |
| 28912 | { PseudoVREMU_VX_M8_E32_MASK, VREMU_VX }, // 7642 |
| 28913 | { PseudoVREMU_VX_M8_E64, VREMU_VX }, // 7643 |
| 28914 | { PseudoVREMU_VX_M8_E64_MASK, VREMU_VX }, // 7644 |
| 28915 | { PseudoVREMU_VX_M8_E8, VREMU_VX }, // 7645 |
| 28916 | { PseudoVREMU_VX_M8_E8_MASK, VREMU_VX }, // 7646 |
| 28917 | { PseudoVREMU_VX_MF2_E16, VREMU_VX }, // 7647 |
| 28918 | { PseudoVREMU_VX_MF2_E16_MASK, VREMU_VX }, // 7648 |
| 28919 | { PseudoVREMU_VX_MF2_E32, VREMU_VX }, // 7649 |
| 28920 | { PseudoVREMU_VX_MF2_E32_MASK, VREMU_VX }, // 7650 |
| 28921 | { PseudoVREMU_VX_MF2_E8, VREMU_VX }, // 7651 |
| 28922 | { PseudoVREMU_VX_MF2_E8_MASK, VREMU_VX }, // 7652 |
| 28923 | { PseudoVREMU_VX_MF4_E16, VREMU_VX }, // 7653 |
| 28924 | { PseudoVREMU_VX_MF4_E16_MASK, VREMU_VX }, // 7654 |
| 28925 | { PseudoVREMU_VX_MF4_E8, VREMU_VX }, // 7655 |
| 28926 | { PseudoVREMU_VX_MF4_E8_MASK, VREMU_VX }, // 7656 |
| 28927 | { PseudoVREMU_VX_MF8_E8, VREMU_VX }, // 7657 |
| 28928 | { PseudoVREMU_VX_MF8_E8_MASK, VREMU_VX }, // 7658 |
| 28929 | { PseudoVREM_VV_M1_E16, VREM_VV }, // 7659 |
| 28930 | { PseudoVREM_VV_M1_E16_MASK, VREM_VV }, // 7660 |
| 28931 | { PseudoVREM_VV_M1_E32, VREM_VV }, // 7661 |
| 28932 | { PseudoVREM_VV_M1_E32_MASK, VREM_VV }, // 7662 |
| 28933 | { PseudoVREM_VV_M1_E64, VREM_VV }, // 7663 |
| 28934 | { PseudoVREM_VV_M1_E64_MASK, VREM_VV }, // 7664 |
| 28935 | { PseudoVREM_VV_M1_E8, VREM_VV }, // 7665 |
| 28936 | { PseudoVREM_VV_M1_E8_MASK, VREM_VV }, // 7666 |
| 28937 | { PseudoVREM_VV_M2_E16, VREM_VV }, // 7667 |
| 28938 | { PseudoVREM_VV_M2_E16_MASK, VREM_VV }, // 7668 |
| 28939 | { PseudoVREM_VV_M2_E32, VREM_VV }, // 7669 |
| 28940 | { PseudoVREM_VV_M2_E32_MASK, VREM_VV }, // 7670 |
| 28941 | { PseudoVREM_VV_M2_E64, VREM_VV }, // 7671 |
| 28942 | { PseudoVREM_VV_M2_E64_MASK, VREM_VV }, // 7672 |
| 28943 | { PseudoVREM_VV_M2_E8, VREM_VV }, // 7673 |
| 28944 | { PseudoVREM_VV_M2_E8_MASK, VREM_VV }, // 7674 |
| 28945 | { PseudoVREM_VV_M4_E16, VREM_VV }, // 7675 |
| 28946 | { PseudoVREM_VV_M4_E16_MASK, VREM_VV }, // 7676 |
| 28947 | { PseudoVREM_VV_M4_E32, VREM_VV }, // 7677 |
| 28948 | { PseudoVREM_VV_M4_E32_MASK, VREM_VV }, // 7678 |
| 28949 | { PseudoVREM_VV_M4_E64, VREM_VV }, // 7679 |
| 28950 | { PseudoVREM_VV_M4_E64_MASK, VREM_VV }, // 7680 |
| 28951 | { PseudoVREM_VV_M4_E8, VREM_VV }, // 7681 |
| 28952 | { PseudoVREM_VV_M4_E8_MASK, VREM_VV }, // 7682 |
| 28953 | { PseudoVREM_VV_M8_E16, VREM_VV }, // 7683 |
| 28954 | { PseudoVREM_VV_M8_E16_MASK, VREM_VV }, // 7684 |
| 28955 | { PseudoVREM_VV_M8_E32, VREM_VV }, // 7685 |
| 28956 | { PseudoVREM_VV_M8_E32_MASK, VREM_VV }, // 7686 |
| 28957 | { PseudoVREM_VV_M8_E64, VREM_VV }, // 7687 |
| 28958 | { PseudoVREM_VV_M8_E64_MASK, VREM_VV }, // 7688 |
| 28959 | { PseudoVREM_VV_M8_E8, VREM_VV }, // 7689 |
| 28960 | { PseudoVREM_VV_M8_E8_MASK, VREM_VV }, // 7690 |
| 28961 | { PseudoVREM_VV_MF2_E16, VREM_VV }, // 7691 |
| 28962 | { PseudoVREM_VV_MF2_E16_MASK, VREM_VV }, // 7692 |
| 28963 | { PseudoVREM_VV_MF2_E32, VREM_VV }, // 7693 |
| 28964 | { PseudoVREM_VV_MF2_E32_MASK, VREM_VV }, // 7694 |
| 28965 | { PseudoVREM_VV_MF2_E8, VREM_VV }, // 7695 |
| 28966 | { PseudoVREM_VV_MF2_E8_MASK, VREM_VV }, // 7696 |
| 28967 | { PseudoVREM_VV_MF4_E16, VREM_VV }, // 7697 |
| 28968 | { PseudoVREM_VV_MF4_E16_MASK, VREM_VV }, // 7698 |
| 28969 | { PseudoVREM_VV_MF4_E8, VREM_VV }, // 7699 |
| 28970 | { PseudoVREM_VV_MF4_E8_MASK, VREM_VV }, // 7700 |
| 28971 | { PseudoVREM_VV_MF8_E8, VREM_VV }, // 7701 |
| 28972 | { PseudoVREM_VV_MF8_E8_MASK, VREM_VV }, // 7702 |
| 28973 | { PseudoVREM_VX_M1_E16, VREM_VX }, // 7703 |
| 28974 | { PseudoVREM_VX_M1_E16_MASK, VREM_VX }, // 7704 |
| 28975 | { PseudoVREM_VX_M1_E32, VREM_VX }, // 7705 |
| 28976 | { PseudoVREM_VX_M1_E32_MASK, VREM_VX }, // 7706 |
| 28977 | { PseudoVREM_VX_M1_E64, VREM_VX }, // 7707 |
| 28978 | { PseudoVREM_VX_M1_E64_MASK, VREM_VX }, // 7708 |
| 28979 | { PseudoVREM_VX_M1_E8, VREM_VX }, // 7709 |
| 28980 | { PseudoVREM_VX_M1_E8_MASK, VREM_VX }, // 7710 |
| 28981 | { PseudoVREM_VX_M2_E16, VREM_VX }, // 7711 |
| 28982 | { PseudoVREM_VX_M2_E16_MASK, VREM_VX }, // 7712 |
| 28983 | { PseudoVREM_VX_M2_E32, VREM_VX }, // 7713 |
| 28984 | { PseudoVREM_VX_M2_E32_MASK, VREM_VX }, // 7714 |
| 28985 | { PseudoVREM_VX_M2_E64, VREM_VX }, // 7715 |
| 28986 | { PseudoVREM_VX_M2_E64_MASK, VREM_VX }, // 7716 |
| 28987 | { PseudoVREM_VX_M2_E8, VREM_VX }, // 7717 |
| 28988 | { PseudoVREM_VX_M2_E8_MASK, VREM_VX }, // 7718 |
| 28989 | { PseudoVREM_VX_M4_E16, VREM_VX }, // 7719 |
| 28990 | { PseudoVREM_VX_M4_E16_MASK, VREM_VX }, // 7720 |
| 28991 | { PseudoVREM_VX_M4_E32, VREM_VX }, // 7721 |
| 28992 | { PseudoVREM_VX_M4_E32_MASK, VREM_VX }, // 7722 |
| 28993 | { PseudoVREM_VX_M4_E64, VREM_VX }, // 7723 |
| 28994 | { PseudoVREM_VX_M4_E64_MASK, VREM_VX }, // 7724 |
| 28995 | { PseudoVREM_VX_M4_E8, VREM_VX }, // 7725 |
| 28996 | { PseudoVREM_VX_M4_E8_MASK, VREM_VX }, // 7726 |
| 28997 | { PseudoVREM_VX_M8_E16, VREM_VX }, // 7727 |
| 28998 | { PseudoVREM_VX_M8_E16_MASK, VREM_VX }, // 7728 |
| 28999 | { PseudoVREM_VX_M8_E32, VREM_VX }, // 7729 |
| 29000 | { PseudoVREM_VX_M8_E32_MASK, VREM_VX }, // 7730 |
| 29001 | { PseudoVREM_VX_M8_E64, VREM_VX }, // 7731 |
| 29002 | { PseudoVREM_VX_M8_E64_MASK, VREM_VX }, // 7732 |
| 29003 | { PseudoVREM_VX_M8_E8, VREM_VX }, // 7733 |
| 29004 | { PseudoVREM_VX_M8_E8_MASK, VREM_VX }, // 7734 |
| 29005 | { PseudoVREM_VX_MF2_E16, VREM_VX }, // 7735 |
| 29006 | { PseudoVREM_VX_MF2_E16_MASK, VREM_VX }, // 7736 |
| 29007 | { PseudoVREM_VX_MF2_E32, VREM_VX }, // 7737 |
| 29008 | { PseudoVREM_VX_MF2_E32_MASK, VREM_VX }, // 7738 |
| 29009 | { PseudoVREM_VX_MF2_E8, VREM_VX }, // 7739 |
| 29010 | { PseudoVREM_VX_MF2_E8_MASK, VREM_VX }, // 7740 |
| 29011 | { PseudoVREM_VX_MF4_E16, VREM_VX }, // 7741 |
| 29012 | { PseudoVREM_VX_MF4_E16_MASK, VREM_VX }, // 7742 |
| 29013 | { PseudoVREM_VX_MF4_E8, VREM_VX }, // 7743 |
| 29014 | { PseudoVREM_VX_MF4_E8_MASK, VREM_VX }, // 7744 |
| 29015 | { PseudoVREM_VX_MF8_E8, VREM_VX }, // 7745 |
| 29016 | { PseudoVREM_VX_MF8_E8_MASK, VREM_VX }, // 7746 |
| 29017 | { PseudoVREV8_V_M1, VREV8_V }, // 7747 |
| 29018 | { PseudoVREV8_V_M1_MASK, VREV8_V }, // 7748 |
| 29019 | { PseudoVREV8_V_M2, VREV8_V }, // 7749 |
| 29020 | { PseudoVREV8_V_M2_MASK, VREV8_V }, // 7750 |
| 29021 | { PseudoVREV8_V_M4, VREV8_V }, // 7751 |
| 29022 | { PseudoVREV8_V_M4_MASK, VREV8_V }, // 7752 |
| 29023 | { PseudoVREV8_V_M8, VREV8_V }, // 7753 |
| 29024 | { PseudoVREV8_V_M8_MASK, VREV8_V }, // 7754 |
| 29025 | { PseudoVREV8_V_MF2, VREV8_V }, // 7755 |
| 29026 | { PseudoVREV8_V_MF2_MASK, VREV8_V }, // 7756 |
| 29027 | { PseudoVREV8_V_MF4, VREV8_V }, // 7757 |
| 29028 | { PseudoVREV8_V_MF4_MASK, VREV8_V }, // 7758 |
| 29029 | { PseudoVREV8_V_MF8, VREV8_V }, // 7759 |
| 29030 | { PseudoVREV8_V_MF8_MASK, VREV8_V }, // 7760 |
| 29031 | { PseudoVRGATHEREI16_VV_M1_E16_M1, VRGATHEREI16_VV }, // 7761 |
| 29032 | { PseudoVRGATHEREI16_VV_M1_E16_M1_MASK, VRGATHEREI16_VV }, // 7762 |
| 29033 | { PseudoVRGATHEREI16_VV_M1_E16_M2, VRGATHEREI16_VV }, // 7763 |
| 29034 | { PseudoVRGATHEREI16_VV_M1_E16_M2_MASK, VRGATHEREI16_VV }, // 7764 |
| 29035 | { PseudoVRGATHEREI16_VV_M1_E16_MF2, VRGATHEREI16_VV }, // 7765 |
| 29036 | { PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK, VRGATHEREI16_VV }, // 7766 |
| 29037 | { PseudoVRGATHEREI16_VV_M1_E16_MF4, VRGATHEREI16_VV }, // 7767 |
| 29038 | { PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK, VRGATHEREI16_VV }, // 7768 |
| 29039 | { PseudoVRGATHEREI16_VV_M1_E32_M1, VRGATHEREI16_VV }, // 7769 |
| 29040 | { PseudoVRGATHEREI16_VV_M1_E32_M1_MASK, VRGATHEREI16_VV }, // 7770 |
| 29041 | { PseudoVRGATHEREI16_VV_M1_E32_M2, VRGATHEREI16_VV }, // 7771 |
| 29042 | { PseudoVRGATHEREI16_VV_M1_E32_M2_MASK, VRGATHEREI16_VV }, // 7772 |
| 29043 | { PseudoVRGATHEREI16_VV_M1_E32_MF2, VRGATHEREI16_VV }, // 7773 |
| 29044 | { PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK, VRGATHEREI16_VV }, // 7774 |
| 29045 | { PseudoVRGATHEREI16_VV_M1_E32_MF4, VRGATHEREI16_VV }, // 7775 |
| 29046 | { PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK, VRGATHEREI16_VV }, // 7776 |
| 29047 | { PseudoVRGATHEREI16_VV_M1_E64_M1, VRGATHEREI16_VV }, // 7777 |
| 29048 | { PseudoVRGATHEREI16_VV_M1_E64_M1_MASK, VRGATHEREI16_VV }, // 7778 |
| 29049 | { PseudoVRGATHEREI16_VV_M1_E64_M2, VRGATHEREI16_VV }, // 7779 |
| 29050 | { PseudoVRGATHEREI16_VV_M1_E64_M2_MASK, VRGATHEREI16_VV }, // 7780 |
| 29051 | { PseudoVRGATHEREI16_VV_M1_E64_MF2, VRGATHEREI16_VV }, // 7781 |
| 29052 | { PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK, VRGATHEREI16_VV }, // 7782 |
| 29053 | { PseudoVRGATHEREI16_VV_M1_E64_MF4, VRGATHEREI16_VV }, // 7783 |
| 29054 | { PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK, VRGATHEREI16_VV }, // 7784 |
| 29055 | { PseudoVRGATHEREI16_VV_M1_E8_M1, VRGATHEREI16_VV }, // 7785 |
| 29056 | { PseudoVRGATHEREI16_VV_M1_E8_M1_MASK, VRGATHEREI16_VV }, // 7786 |
| 29057 | { PseudoVRGATHEREI16_VV_M1_E8_M2, VRGATHEREI16_VV }, // 7787 |
| 29058 | { PseudoVRGATHEREI16_VV_M1_E8_M2_MASK, VRGATHEREI16_VV }, // 7788 |
| 29059 | { PseudoVRGATHEREI16_VV_M1_E8_MF2, VRGATHEREI16_VV }, // 7789 |
| 29060 | { PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK, VRGATHEREI16_VV }, // 7790 |
| 29061 | { PseudoVRGATHEREI16_VV_M1_E8_MF4, VRGATHEREI16_VV }, // 7791 |
| 29062 | { PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK, VRGATHEREI16_VV }, // 7792 |
| 29063 | { PseudoVRGATHEREI16_VV_M2_E16_M1, VRGATHEREI16_VV }, // 7793 |
| 29064 | { PseudoVRGATHEREI16_VV_M2_E16_M1_MASK, VRGATHEREI16_VV }, // 7794 |
| 29065 | { PseudoVRGATHEREI16_VV_M2_E16_M2, VRGATHEREI16_VV }, // 7795 |
| 29066 | { PseudoVRGATHEREI16_VV_M2_E16_M2_MASK, VRGATHEREI16_VV }, // 7796 |
| 29067 | { PseudoVRGATHEREI16_VV_M2_E16_M4, VRGATHEREI16_VV }, // 7797 |
| 29068 | { PseudoVRGATHEREI16_VV_M2_E16_M4_MASK, VRGATHEREI16_VV }, // 7798 |
| 29069 | { PseudoVRGATHEREI16_VV_M2_E16_MF2, VRGATHEREI16_VV }, // 7799 |
| 29070 | { PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK, VRGATHEREI16_VV }, // 7800 |
| 29071 | { PseudoVRGATHEREI16_VV_M2_E32_M1, VRGATHEREI16_VV }, // 7801 |
| 29072 | { PseudoVRGATHEREI16_VV_M2_E32_M1_MASK, VRGATHEREI16_VV }, // 7802 |
| 29073 | { PseudoVRGATHEREI16_VV_M2_E32_M2, VRGATHEREI16_VV }, // 7803 |
| 29074 | { PseudoVRGATHEREI16_VV_M2_E32_M2_MASK, VRGATHEREI16_VV }, // 7804 |
| 29075 | { PseudoVRGATHEREI16_VV_M2_E32_M4, VRGATHEREI16_VV }, // 7805 |
| 29076 | { PseudoVRGATHEREI16_VV_M2_E32_M4_MASK, VRGATHEREI16_VV }, // 7806 |
| 29077 | { PseudoVRGATHEREI16_VV_M2_E32_MF2, VRGATHEREI16_VV }, // 7807 |
| 29078 | { PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK, VRGATHEREI16_VV }, // 7808 |
| 29079 | { PseudoVRGATHEREI16_VV_M2_E64_M1, VRGATHEREI16_VV }, // 7809 |
| 29080 | { PseudoVRGATHEREI16_VV_M2_E64_M1_MASK, VRGATHEREI16_VV }, // 7810 |
| 29081 | { PseudoVRGATHEREI16_VV_M2_E64_M2, VRGATHEREI16_VV }, // 7811 |
| 29082 | { PseudoVRGATHEREI16_VV_M2_E64_M2_MASK, VRGATHEREI16_VV }, // 7812 |
| 29083 | { PseudoVRGATHEREI16_VV_M2_E64_M4, VRGATHEREI16_VV }, // 7813 |
| 29084 | { PseudoVRGATHEREI16_VV_M2_E64_M4_MASK, VRGATHEREI16_VV }, // 7814 |
| 29085 | { PseudoVRGATHEREI16_VV_M2_E64_MF2, VRGATHEREI16_VV }, // 7815 |
| 29086 | { PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK, VRGATHEREI16_VV }, // 7816 |
| 29087 | { PseudoVRGATHEREI16_VV_M2_E8_M1, VRGATHEREI16_VV }, // 7817 |
| 29088 | { PseudoVRGATHEREI16_VV_M2_E8_M1_MASK, VRGATHEREI16_VV }, // 7818 |
| 29089 | { PseudoVRGATHEREI16_VV_M2_E8_M2, VRGATHEREI16_VV }, // 7819 |
| 29090 | { PseudoVRGATHEREI16_VV_M2_E8_M2_MASK, VRGATHEREI16_VV }, // 7820 |
| 29091 | { PseudoVRGATHEREI16_VV_M2_E8_M4, VRGATHEREI16_VV }, // 7821 |
| 29092 | { PseudoVRGATHEREI16_VV_M2_E8_M4_MASK, VRGATHEREI16_VV }, // 7822 |
| 29093 | { PseudoVRGATHEREI16_VV_M2_E8_MF2, VRGATHEREI16_VV }, // 7823 |
| 29094 | { PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK, VRGATHEREI16_VV }, // 7824 |
| 29095 | { PseudoVRGATHEREI16_VV_M4_E16_M1, VRGATHEREI16_VV }, // 7825 |
| 29096 | { PseudoVRGATHEREI16_VV_M4_E16_M1_MASK, VRGATHEREI16_VV }, // 7826 |
| 29097 | { PseudoVRGATHEREI16_VV_M4_E16_M2, VRGATHEREI16_VV }, // 7827 |
| 29098 | { PseudoVRGATHEREI16_VV_M4_E16_M2_MASK, VRGATHEREI16_VV }, // 7828 |
| 29099 | { PseudoVRGATHEREI16_VV_M4_E16_M4, VRGATHEREI16_VV }, // 7829 |
| 29100 | { PseudoVRGATHEREI16_VV_M4_E16_M4_MASK, VRGATHEREI16_VV }, // 7830 |
| 29101 | { PseudoVRGATHEREI16_VV_M4_E16_M8, VRGATHEREI16_VV }, // 7831 |
| 29102 | { PseudoVRGATHEREI16_VV_M4_E16_M8_MASK, VRGATHEREI16_VV }, // 7832 |
| 29103 | { PseudoVRGATHEREI16_VV_M4_E32_M1, VRGATHEREI16_VV }, // 7833 |
| 29104 | { PseudoVRGATHEREI16_VV_M4_E32_M1_MASK, VRGATHEREI16_VV }, // 7834 |
| 29105 | { PseudoVRGATHEREI16_VV_M4_E32_M2, VRGATHEREI16_VV }, // 7835 |
| 29106 | { PseudoVRGATHEREI16_VV_M4_E32_M2_MASK, VRGATHEREI16_VV }, // 7836 |
| 29107 | { PseudoVRGATHEREI16_VV_M4_E32_M4, VRGATHEREI16_VV }, // 7837 |
| 29108 | { PseudoVRGATHEREI16_VV_M4_E32_M4_MASK, VRGATHEREI16_VV }, // 7838 |
| 29109 | { PseudoVRGATHEREI16_VV_M4_E32_M8, VRGATHEREI16_VV }, // 7839 |
| 29110 | { PseudoVRGATHEREI16_VV_M4_E32_M8_MASK, VRGATHEREI16_VV }, // 7840 |
| 29111 | { PseudoVRGATHEREI16_VV_M4_E64_M1, VRGATHEREI16_VV }, // 7841 |
| 29112 | { PseudoVRGATHEREI16_VV_M4_E64_M1_MASK, VRGATHEREI16_VV }, // 7842 |
| 29113 | { PseudoVRGATHEREI16_VV_M4_E64_M2, VRGATHEREI16_VV }, // 7843 |
| 29114 | { PseudoVRGATHEREI16_VV_M4_E64_M2_MASK, VRGATHEREI16_VV }, // 7844 |
| 29115 | { PseudoVRGATHEREI16_VV_M4_E64_M4, VRGATHEREI16_VV }, // 7845 |
| 29116 | { PseudoVRGATHEREI16_VV_M4_E64_M4_MASK, VRGATHEREI16_VV }, // 7846 |
| 29117 | { PseudoVRGATHEREI16_VV_M4_E64_M8, VRGATHEREI16_VV }, // 7847 |
| 29118 | { PseudoVRGATHEREI16_VV_M4_E64_M8_MASK, VRGATHEREI16_VV }, // 7848 |
| 29119 | { PseudoVRGATHEREI16_VV_M4_E8_M1, VRGATHEREI16_VV }, // 7849 |
| 29120 | { PseudoVRGATHEREI16_VV_M4_E8_M1_MASK, VRGATHEREI16_VV }, // 7850 |
| 29121 | { PseudoVRGATHEREI16_VV_M4_E8_M2, VRGATHEREI16_VV }, // 7851 |
| 29122 | { PseudoVRGATHEREI16_VV_M4_E8_M2_MASK, VRGATHEREI16_VV }, // 7852 |
| 29123 | { PseudoVRGATHEREI16_VV_M4_E8_M4, VRGATHEREI16_VV }, // 7853 |
| 29124 | { PseudoVRGATHEREI16_VV_M4_E8_M4_MASK, VRGATHEREI16_VV }, // 7854 |
| 29125 | { PseudoVRGATHEREI16_VV_M4_E8_M8, VRGATHEREI16_VV }, // 7855 |
| 29126 | { PseudoVRGATHEREI16_VV_M4_E8_M8_MASK, VRGATHEREI16_VV }, // 7856 |
| 29127 | { PseudoVRGATHEREI16_VV_M8_E16_M2, VRGATHEREI16_VV }, // 7857 |
| 29128 | { PseudoVRGATHEREI16_VV_M8_E16_M2_MASK, VRGATHEREI16_VV }, // 7858 |
| 29129 | { PseudoVRGATHEREI16_VV_M8_E16_M4, VRGATHEREI16_VV }, // 7859 |
| 29130 | { PseudoVRGATHEREI16_VV_M8_E16_M4_MASK, VRGATHEREI16_VV }, // 7860 |
| 29131 | { PseudoVRGATHEREI16_VV_M8_E16_M8, VRGATHEREI16_VV }, // 7861 |
| 29132 | { PseudoVRGATHEREI16_VV_M8_E16_M8_MASK, VRGATHEREI16_VV }, // 7862 |
| 29133 | { PseudoVRGATHEREI16_VV_M8_E32_M2, VRGATHEREI16_VV }, // 7863 |
| 29134 | { PseudoVRGATHEREI16_VV_M8_E32_M2_MASK, VRGATHEREI16_VV }, // 7864 |
| 29135 | { PseudoVRGATHEREI16_VV_M8_E32_M4, VRGATHEREI16_VV }, // 7865 |
| 29136 | { PseudoVRGATHEREI16_VV_M8_E32_M4_MASK, VRGATHEREI16_VV }, // 7866 |
| 29137 | { PseudoVRGATHEREI16_VV_M8_E32_M8, VRGATHEREI16_VV }, // 7867 |
| 29138 | { PseudoVRGATHEREI16_VV_M8_E32_M8_MASK, VRGATHEREI16_VV }, // 7868 |
| 29139 | { PseudoVRGATHEREI16_VV_M8_E64_M2, VRGATHEREI16_VV }, // 7869 |
| 29140 | { PseudoVRGATHEREI16_VV_M8_E64_M2_MASK, VRGATHEREI16_VV }, // 7870 |
| 29141 | { PseudoVRGATHEREI16_VV_M8_E64_M4, VRGATHEREI16_VV }, // 7871 |
| 29142 | { PseudoVRGATHEREI16_VV_M8_E64_M4_MASK, VRGATHEREI16_VV }, // 7872 |
| 29143 | { PseudoVRGATHEREI16_VV_M8_E64_M8, VRGATHEREI16_VV }, // 7873 |
| 29144 | { PseudoVRGATHEREI16_VV_M8_E64_M8_MASK, VRGATHEREI16_VV }, // 7874 |
| 29145 | { PseudoVRGATHEREI16_VV_M8_E8_M2, VRGATHEREI16_VV }, // 7875 |
| 29146 | { PseudoVRGATHEREI16_VV_M8_E8_M2_MASK, VRGATHEREI16_VV }, // 7876 |
| 29147 | { PseudoVRGATHEREI16_VV_M8_E8_M4, VRGATHEREI16_VV }, // 7877 |
| 29148 | { PseudoVRGATHEREI16_VV_M8_E8_M4_MASK, VRGATHEREI16_VV }, // 7878 |
| 29149 | { PseudoVRGATHEREI16_VV_M8_E8_M8, VRGATHEREI16_VV }, // 7879 |
| 29150 | { PseudoVRGATHEREI16_VV_M8_E8_M8_MASK, VRGATHEREI16_VV }, // 7880 |
| 29151 | { PseudoVRGATHEREI16_VV_MF2_E16_M1, VRGATHEREI16_VV }, // 7881 |
| 29152 | { PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK, VRGATHEREI16_VV }, // 7882 |
| 29153 | { PseudoVRGATHEREI16_VV_MF2_E16_MF2, VRGATHEREI16_VV }, // 7883 |
| 29154 | { PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK, VRGATHEREI16_VV }, // 7884 |
| 29155 | { PseudoVRGATHEREI16_VV_MF2_E16_MF4, VRGATHEREI16_VV }, // 7885 |
| 29156 | { PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK, VRGATHEREI16_VV }, // 7886 |
| 29157 | { PseudoVRGATHEREI16_VV_MF2_E16_MF8, VRGATHEREI16_VV }, // 7887 |
| 29158 | { PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK, VRGATHEREI16_VV }, // 7888 |
| 29159 | { PseudoVRGATHEREI16_VV_MF2_E32_M1, VRGATHEREI16_VV }, // 7889 |
| 29160 | { PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK, VRGATHEREI16_VV }, // 7890 |
| 29161 | { PseudoVRGATHEREI16_VV_MF2_E32_MF2, VRGATHEREI16_VV }, // 7891 |
| 29162 | { PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK, VRGATHEREI16_VV }, // 7892 |
| 29163 | { PseudoVRGATHEREI16_VV_MF2_E32_MF4, VRGATHEREI16_VV }, // 7893 |
| 29164 | { PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK, VRGATHEREI16_VV }, // 7894 |
| 29165 | { PseudoVRGATHEREI16_VV_MF2_E32_MF8, VRGATHEREI16_VV }, // 7895 |
| 29166 | { PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK, VRGATHEREI16_VV }, // 7896 |
| 29167 | { PseudoVRGATHEREI16_VV_MF2_E8_M1, VRGATHEREI16_VV }, // 7897 |
| 29168 | { PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK, VRGATHEREI16_VV }, // 7898 |
| 29169 | { PseudoVRGATHEREI16_VV_MF2_E8_MF2, VRGATHEREI16_VV }, // 7899 |
| 29170 | { PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK, VRGATHEREI16_VV }, // 7900 |
| 29171 | { PseudoVRGATHEREI16_VV_MF2_E8_MF4, VRGATHEREI16_VV }, // 7901 |
| 29172 | { PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK, VRGATHEREI16_VV }, // 7902 |
| 29173 | { PseudoVRGATHEREI16_VV_MF2_E8_MF8, VRGATHEREI16_VV }, // 7903 |
| 29174 | { PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK, VRGATHEREI16_VV }, // 7904 |
| 29175 | { PseudoVRGATHEREI16_VV_MF4_E16_MF2, VRGATHEREI16_VV }, // 7905 |
| 29176 | { PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK, VRGATHEREI16_VV }, // 7906 |
| 29177 | { PseudoVRGATHEREI16_VV_MF4_E16_MF4, VRGATHEREI16_VV }, // 7907 |
| 29178 | { PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK, VRGATHEREI16_VV }, // 7908 |
| 29179 | { PseudoVRGATHEREI16_VV_MF4_E16_MF8, VRGATHEREI16_VV }, // 7909 |
| 29180 | { PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK, VRGATHEREI16_VV }, // 7910 |
| 29181 | { PseudoVRGATHEREI16_VV_MF4_E8_MF2, VRGATHEREI16_VV }, // 7911 |
| 29182 | { PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK, VRGATHEREI16_VV }, // 7912 |
| 29183 | { PseudoVRGATHEREI16_VV_MF4_E8_MF4, VRGATHEREI16_VV }, // 7913 |
| 29184 | { PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK, VRGATHEREI16_VV }, // 7914 |
| 29185 | { PseudoVRGATHEREI16_VV_MF4_E8_MF8, VRGATHEREI16_VV }, // 7915 |
| 29186 | { PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK, VRGATHEREI16_VV }, // 7916 |
| 29187 | { PseudoVRGATHEREI16_VV_MF8_E8_MF4, VRGATHEREI16_VV }, // 7917 |
| 29188 | { PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK, VRGATHEREI16_VV }, // 7918 |
| 29189 | { PseudoVRGATHEREI16_VV_MF8_E8_MF8, VRGATHEREI16_VV }, // 7919 |
| 29190 | { PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK, VRGATHEREI16_VV }, // 7920 |
| 29191 | { PseudoVRGATHER_VI_M1, VRGATHER_VI }, // 7921 |
| 29192 | { PseudoVRGATHER_VI_M1_MASK, VRGATHER_VI }, // 7922 |
| 29193 | { PseudoVRGATHER_VI_M2, VRGATHER_VI }, // 7923 |
| 29194 | { PseudoVRGATHER_VI_M2_MASK, VRGATHER_VI }, // 7924 |
| 29195 | { PseudoVRGATHER_VI_M4, VRGATHER_VI }, // 7925 |
| 29196 | { PseudoVRGATHER_VI_M4_MASK, VRGATHER_VI }, // 7926 |
| 29197 | { PseudoVRGATHER_VI_M8, VRGATHER_VI }, // 7927 |
| 29198 | { PseudoVRGATHER_VI_M8_MASK, VRGATHER_VI }, // 7928 |
| 29199 | { PseudoVRGATHER_VI_MF2, VRGATHER_VI }, // 7929 |
| 29200 | { PseudoVRGATHER_VI_MF2_MASK, VRGATHER_VI }, // 7930 |
| 29201 | { PseudoVRGATHER_VI_MF4, VRGATHER_VI }, // 7931 |
| 29202 | { PseudoVRGATHER_VI_MF4_MASK, VRGATHER_VI }, // 7932 |
| 29203 | { PseudoVRGATHER_VI_MF8, VRGATHER_VI }, // 7933 |
| 29204 | { PseudoVRGATHER_VI_MF8_MASK, VRGATHER_VI }, // 7934 |
| 29205 | { PseudoVRGATHER_VV_M1_E16, VRGATHER_VV }, // 7935 |
| 29206 | { PseudoVRGATHER_VV_M1_E16_MASK, VRGATHER_VV }, // 7936 |
| 29207 | { PseudoVRGATHER_VV_M1_E32, VRGATHER_VV }, // 7937 |
| 29208 | { PseudoVRGATHER_VV_M1_E32_MASK, VRGATHER_VV }, // 7938 |
| 29209 | { PseudoVRGATHER_VV_M1_E64, VRGATHER_VV }, // 7939 |
| 29210 | { PseudoVRGATHER_VV_M1_E64_MASK, VRGATHER_VV }, // 7940 |
| 29211 | { PseudoVRGATHER_VV_M1_E8, VRGATHER_VV }, // 7941 |
| 29212 | { PseudoVRGATHER_VV_M1_E8_MASK, VRGATHER_VV }, // 7942 |
| 29213 | { PseudoVRGATHER_VV_M2_E16, VRGATHER_VV }, // 7943 |
| 29214 | { PseudoVRGATHER_VV_M2_E16_MASK, VRGATHER_VV }, // 7944 |
| 29215 | { PseudoVRGATHER_VV_M2_E32, VRGATHER_VV }, // 7945 |
| 29216 | { PseudoVRGATHER_VV_M2_E32_MASK, VRGATHER_VV }, // 7946 |
| 29217 | { PseudoVRGATHER_VV_M2_E64, VRGATHER_VV }, // 7947 |
| 29218 | { PseudoVRGATHER_VV_M2_E64_MASK, VRGATHER_VV }, // 7948 |
| 29219 | { PseudoVRGATHER_VV_M2_E8, VRGATHER_VV }, // 7949 |
| 29220 | { PseudoVRGATHER_VV_M2_E8_MASK, VRGATHER_VV }, // 7950 |
| 29221 | { PseudoVRGATHER_VV_M4_E16, VRGATHER_VV }, // 7951 |
| 29222 | { PseudoVRGATHER_VV_M4_E16_MASK, VRGATHER_VV }, // 7952 |
| 29223 | { PseudoVRGATHER_VV_M4_E32, VRGATHER_VV }, // 7953 |
| 29224 | { PseudoVRGATHER_VV_M4_E32_MASK, VRGATHER_VV }, // 7954 |
| 29225 | { PseudoVRGATHER_VV_M4_E64, VRGATHER_VV }, // 7955 |
| 29226 | { PseudoVRGATHER_VV_M4_E64_MASK, VRGATHER_VV }, // 7956 |
| 29227 | { PseudoVRGATHER_VV_M4_E8, VRGATHER_VV }, // 7957 |
| 29228 | { PseudoVRGATHER_VV_M4_E8_MASK, VRGATHER_VV }, // 7958 |
| 29229 | { PseudoVRGATHER_VV_M8_E16, VRGATHER_VV }, // 7959 |
| 29230 | { PseudoVRGATHER_VV_M8_E16_MASK, VRGATHER_VV }, // 7960 |
| 29231 | { PseudoVRGATHER_VV_M8_E32, VRGATHER_VV }, // 7961 |
| 29232 | { PseudoVRGATHER_VV_M8_E32_MASK, VRGATHER_VV }, // 7962 |
| 29233 | { PseudoVRGATHER_VV_M8_E64, VRGATHER_VV }, // 7963 |
| 29234 | { PseudoVRGATHER_VV_M8_E64_MASK, VRGATHER_VV }, // 7964 |
| 29235 | { PseudoVRGATHER_VV_M8_E8, VRGATHER_VV }, // 7965 |
| 29236 | { PseudoVRGATHER_VV_M8_E8_MASK, VRGATHER_VV }, // 7966 |
| 29237 | { PseudoVRGATHER_VV_MF2_E16, VRGATHER_VV }, // 7967 |
| 29238 | { PseudoVRGATHER_VV_MF2_E16_MASK, VRGATHER_VV }, // 7968 |
| 29239 | { PseudoVRGATHER_VV_MF2_E32, VRGATHER_VV }, // 7969 |
| 29240 | { PseudoVRGATHER_VV_MF2_E32_MASK, VRGATHER_VV }, // 7970 |
| 29241 | { PseudoVRGATHER_VV_MF2_E8, VRGATHER_VV }, // 7971 |
| 29242 | { PseudoVRGATHER_VV_MF2_E8_MASK, VRGATHER_VV }, // 7972 |
| 29243 | { PseudoVRGATHER_VV_MF4_E16, VRGATHER_VV }, // 7973 |
| 29244 | { PseudoVRGATHER_VV_MF4_E16_MASK, VRGATHER_VV }, // 7974 |
| 29245 | { PseudoVRGATHER_VV_MF4_E8, VRGATHER_VV }, // 7975 |
| 29246 | { PseudoVRGATHER_VV_MF4_E8_MASK, VRGATHER_VV }, // 7976 |
| 29247 | { PseudoVRGATHER_VV_MF8_E8, VRGATHER_VV }, // 7977 |
| 29248 | { PseudoVRGATHER_VV_MF8_E8_MASK, VRGATHER_VV }, // 7978 |
| 29249 | { PseudoVRGATHER_VX_M1, VRGATHER_VX }, // 7979 |
| 29250 | { PseudoVRGATHER_VX_M1_MASK, VRGATHER_VX }, // 7980 |
| 29251 | { PseudoVRGATHER_VX_M2, VRGATHER_VX }, // 7981 |
| 29252 | { PseudoVRGATHER_VX_M2_MASK, VRGATHER_VX }, // 7982 |
| 29253 | { PseudoVRGATHER_VX_M4, VRGATHER_VX }, // 7983 |
| 29254 | { PseudoVRGATHER_VX_M4_MASK, VRGATHER_VX }, // 7984 |
| 29255 | { PseudoVRGATHER_VX_M8, VRGATHER_VX }, // 7985 |
| 29256 | { PseudoVRGATHER_VX_M8_MASK, VRGATHER_VX }, // 7986 |
| 29257 | { PseudoVRGATHER_VX_MF2, VRGATHER_VX }, // 7987 |
| 29258 | { PseudoVRGATHER_VX_MF2_MASK, VRGATHER_VX }, // 7988 |
| 29259 | { PseudoVRGATHER_VX_MF4, VRGATHER_VX }, // 7989 |
| 29260 | { PseudoVRGATHER_VX_MF4_MASK, VRGATHER_VX }, // 7990 |
| 29261 | { PseudoVRGATHER_VX_MF8, VRGATHER_VX }, // 7991 |
| 29262 | { PseudoVRGATHER_VX_MF8_MASK, VRGATHER_VX }, // 7992 |
| 29263 | { PseudoVROL_VV_M1, VROL_VV }, // 7993 |
| 29264 | { PseudoVROL_VV_M1_MASK, VROL_VV }, // 7994 |
| 29265 | { PseudoVROL_VV_M2, VROL_VV }, // 7995 |
| 29266 | { PseudoVROL_VV_M2_MASK, VROL_VV }, // 7996 |
| 29267 | { PseudoVROL_VV_M4, VROL_VV }, // 7997 |
| 29268 | { PseudoVROL_VV_M4_MASK, VROL_VV }, // 7998 |
| 29269 | { PseudoVROL_VV_M8, VROL_VV }, // 7999 |
| 29270 | { PseudoVROL_VV_M8_MASK, VROL_VV }, // 8000 |
| 29271 | { PseudoVROL_VV_MF2, VROL_VV }, // 8001 |
| 29272 | { PseudoVROL_VV_MF2_MASK, VROL_VV }, // 8002 |
| 29273 | { PseudoVROL_VV_MF4, VROL_VV }, // 8003 |
| 29274 | { PseudoVROL_VV_MF4_MASK, VROL_VV }, // 8004 |
| 29275 | { PseudoVROL_VV_MF8, VROL_VV }, // 8005 |
| 29276 | { PseudoVROL_VV_MF8_MASK, VROL_VV }, // 8006 |
| 29277 | { PseudoVROL_VX_M1, VROL_VX }, // 8007 |
| 29278 | { PseudoVROL_VX_M1_MASK, VROL_VX }, // 8008 |
| 29279 | { PseudoVROL_VX_M2, VROL_VX }, // 8009 |
| 29280 | { PseudoVROL_VX_M2_MASK, VROL_VX }, // 8010 |
| 29281 | { PseudoVROL_VX_M4, VROL_VX }, // 8011 |
| 29282 | { PseudoVROL_VX_M4_MASK, VROL_VX }, // 8012 |
| 29283 | { PseudoVROL_VX_M8, VROL_VX }, // 8013 |
| 29284 | { PseudoVROL_VX_M8_MASK, VROL_VX }, // 8014 |
| 29285 | { PseudoVROL_VX_MF2, VROL_VX }, // 8015 |
| 29286 | { PseudoVROL_VX_MF2_MASK, VROL_VX }, // 8016 |
| 29287 | { PseudoVROL_VX_MF4, VROL_VX }, // 8017 |
| 29288 | { PseudoVROL_VX_MF4_MASK, VROL_VX }, // 8018 |
| 29289 | { PseudoVROL_VX_MF8, VROL_VX }, // 8019 |
| 29290 | { PseudoVROL_VX_MF8_MASK, VROL_VX }, // 8020 |
| 29291 | { PseudoVROR_VI_M1, VROR_VI }, // 8021 |
| 29292 | { PseudoVROR_VI_M1_MASK, VROR_VI }, // 8022 |
| 29293 | { PseudoVROR_VI_M2, VROR_VI }, // 8023 |
| 29294 | { PseudoVROR_VI_M2_MASK, VROR_VI }, // 8024 |
| 29295 | { PseudoVROR_VI_M4, VROR_VI }, // 8025 |
| 29296 | { PseudoVROR_VI_M4_MASK, VROR_VI }, // 8026 |
| 29297 | { PseudoVROR_VI_M8, VROR_VI }, // 8027 |
| 29298 | { PseudoVROR_VI_M8_MASK, VROR_VI }, // 8028 |
| 29299 | { PseudoVROR_VI_MF2, VROR_VI }, // 8029 |
| 29300 | { PseudoVROR_VI_MF2_MASK, VROR_VI }, // 8030 |
| 29301 | { PseudoVROR_VI_MF4, VROR_VI }, // 8031 |
| 29302 | { PseudoVROR_VI_MF4_MASK, VROR_VI }, // 8032 |
| 29303 | { PseudoVROR_VI_MF8, VROR_VI }, // 8033 |
| 29304 | { PseudoVROR_VI_MF8_MASK, VROR_VI }, // 8034 |
| 29305 | { PseudoVROR_VV_M1, VROR_VV }, // 8035 |
| 29306 | { PseudoVROR_VV_M1_MASK, VROR_VV }, // 8036 |
| 29307 | { PseudoVROR_VV_M2, VROR_VV }, // 8037 |
| 29308 | { PseudoVROR_VV_M2_MASK, VROR_VV }, // 8038 |
| 29309 | { PseudoVROR_VV_M4, VROR_VV }, // 8039 |
| 29310 | { PseudoVROR_VV_M4_MASK, VROR_VV }, // 8040 |
| 29311 | { PseudoVROR_VV_M8, VROR_VV }, // 8041 |
| 29312 | { PseudoVROR_VV_M8_MASK, VROR_VV }, // 8042 |
| 29313 | { PseudoVROR_VV_MF2, VROR_VV }, // 8043 |
| 29314 | { PseudoVROR_VV_MF2_MASK, VROR_VV }, // 8044 |
| 29315 | { PseudoVROR_VV_MF4, VROR_VV }, // 8045 |
| 29316 | { PseudoVROR_VV_MF4_MASK, VROR_VV }, // 8046 |
| 29317 | { PseudoVROR_VV_MF8, VROR_VV }, // 8047 |
| 29318 | { PseudoVROR_VV_MF8_MASK, VROR_VV }, // 8048 |
| 29319 | { PseudoVROR_VX_M1, VROR_VX }, // 8049 |
| 29320 | { PseudoVROR_VX_M1_MASK, VROR_VX }, // 8050 |
| 29321 | { PseudoVROR_VX_M2, VROR_VX }, // 8051 |
| 29322 | { PseudoVROR_VX_M2_MASK, VROR_VX }, // 8052 |
| 29323 | { PseudoVROR_VX_M4, VROR_VX }, // 8053 |
| 29324 | { PseudoVROR_VX_M4_MASK, VROR_VX }, // 8054 |
| 29325 | { PseudoVROR_VX_M8, VROR_VX }, // 8055 |
| 29326 | { PseudoVROR_VX_M8_MASK, VROR_VX }, // 8056 |
| 29327 | { PseudoVROR_VX_MF2, VROR_VX }, // 8057 |
| 29328 | { PseudoVROR_VX_MF2_MASK, VROR_VX }, // 8058 |
| 29329 | { PseudoVROR_VX_MF4, VROR_VX }, // 8059 |
| 29330 | { PseudoVROR_VX_MF4_MASK, VROR_VX }, // 8060 |
| 29331 | { PseudoVROR_VX_MF8, VROR_VX }, // 8061 |
| 29332 | { PseudoVROR_VX_MF8_MASK, VROR_VX }, // 8062 |
| 29333 | { PseudoVRSUB_VI_M1, VRSUB_VI }, // 8063 |
| 29334 | { PseudoVRSUB_VI_M1_MASK, VRSUB_VI }, // 8064 |
| 29335 | { PseudoVRSUB_VI_M2, VRSUB_VI }, // 8065 |
| 29336 | { PseudoVRSUB_VI_M2_MASK, VRSUB_VI }, // 8066 |
| 29337 | { PseudoVRSUB_VI_M4, VRSUB_VI }, // 8067 |
| 29338 | { PseudoVRSUB_VI_M4_MASK, VRSUB_VI }, // 8068 |
| 29339 | { PseudoVRSUB_VI_M8, VRSUB_VI }, // 8069 |
| 29340 | { PseudoVRSUB_VI_M8_MASK, VRSUB_VI }, // 8070 |
| 29341 | { PseudoVRSUB_VI_MF2, VRSUB_VI }, // 8071 |
| 29342 | { PseudoVRSUB_VI_MF2_MASK, VRSUB_VI }, // 8072 |
| 29343 | { PseudoVRSUB_VI_MF4, VRSUB_VI }, // 8073 |
| 29344 | { PseudoVRSUB_VI_MF4_MASK, VRSUB_VI }, // 8074 |
| 29345 | { PseudoVRSUB_VI_MF8, VRSUB_VI }, // 8075 |
| 29346 | { PseudoVRSUB_VI_MF8_MASK, VRSUB_VI }, // 8076 |
| 29347 | { PseudoVRSUB_VX_M1, VRSUB_VX }, // 8077 |
| 29348 | { PseudoVRSUB_VX_M1_MASK, VRSUB_VX }, // 8078 |
| 29349 | { PseudoVRSUB_VX_M2, VRSUB_VX }, // 8079 |
| 29350 | { PseudoVRSUB_VX_M2_MASK, VRSUB_VX }, // 8080 |
| 29351 | { PseudoVRSUB_VX_M4, VRSUB_VX }, // 8081 |
| 29352 | { PseudoVRSUB_VX_M4_MASK, VRSUB_VX }, // 8082 |
| 29353 | { PseudoVRSUB_VX_M8, VRSUB_VX }, // 8083 |
| 29354 | { PseudoVRSUB_VX_M8_MASK, VRSUB_VX }, // 8084 |
| 29355 | { PseudoVRSUB_VX_MF2, VRSUB_VX }, // 8085 |
| 29356 | { PseudoVRSUB_VX_MF2_MASK, VRSUB_VX }, // 8086 |
| 29357 | { PseudoVRSUB_VX_MF4, VRSUB_VX }, // 8087 |
| 29358 | { PseudoVRSUB_VX_MF4_MASK, VRSUB_VX }, // 8088 |
| 29359 | { PseudoVRSUB_VX_MF8, VRSUB_VX }, // 8089 |
| 29360 | { PseudoVRSUB_VX_MF8_MASK, VRSUB_VX }, // 8090 |
| 29361 | { PseudoVSADDU_VI_M1, VSADDU_VI }, // 8091 |
| 29362 | { PseudoVSADDU_VI_M1_MASK, VSADDU_VI }, // 8092 |
| 29363 | { PseudoVSADDU_VI_M2, VSADDU_VI }, // 8093 |
| 29364 | { PseudoVSADDU_VI_M2_MASK, VSADDU_VI }, // 8094 |
| 29365 | { PseudoVSADDU_VI_M4, VSADDU_VI }, // 8095 |
| 29366 | { PseudoVSADDU_VI_M4_MASK, VSADDU_VI }, // 8096 |
| 29367 | { PseudoVSADDU_VI_M8, VSADDU_VI }, // 8097 |
| 29368 | { PseudoVSADDU_VI_M8_MASK, VSADDU_VI }, // 8098 |
| 29369 | { PseudoVSADDU_VI_MF2, VSADDU_VI }, // 8099 |
| 29370 | { PseudoVSADDU_VI_MF2_MASK, VSADDU_VI }, // 8100 |
| 29371 | { PseudoVSADDU_VI_MF4, VSADDU_VI }, // 8101 |
| 29372 | { PseudoVSADDU_VI_MF4_MASK, VSADDU_VI }, // 8102 |
| 29373 | { PseudoVSADDU_VI_MF8, VSADDU_VI }, // 8103 |
| 29374 | { PseudoVSADDU_VI_MF8_MASK, VSADDU_VI }, // 8104 |
| 29375 | { PseudoVSADDU_VV_M1, VSADDU_VV }, // 8105 |
| 29376 | { PseudoVSADDU_VV_M1_MASK, VSADDU_VV }, // 8106 |
| 29377 | { PseudoVSADDU_VV_M2, VSADDU_VV }, // 8107 |
| 29378 | { PseudoVSADDU_VV_M2_MASK, VSADDU_VV }, // 8108 |
| 29379 | { PseudoVSADDU_VV_M4, VSADDU_VV }, // 8109 |
| 29380 | { PseudoVSADDU_VV_M4_MASK, VSADDU_VV }, // 8110 |
| 29381 | { PseudoVSADDU_VV_M8, VSADDU_VV }, // 8111 |
| 29382 | { PseudoVSADDU_VV_M8_MASK, VSADDU_VV }, // 8112 |
| 29383 | { PseudoVSADDU_VV_MF2, VSADDU_VV }, // 8113 |
| 29384 | { PseudoVSADDU_VV_MF2_MASK, VSADDU_VV }, // 8114 |
| 29385 | { PseudoVSADDU_VV_MF4, VSADDU_VV }, // 8115 |
| 29386 | { PseudoVSADDU_VV_MF4_MASK, VSADDU_VV }, // 8116 |
| 29387 | { PseudoVSADDU_VV_MF8, VSADDU_VV }, // 8117 |
| 29388 | { PseudoVSADDU_VV_MF8_MASK, VSADDU_VV }, // 8118 |
| 29389 | { PseudoVSADDU_VX_M1, VSADDU_VX }, // 8119 |
| 29390 | { PseudoVSADDU_VX_M1_MASK, VSADDU_VX }, // 8120 |
| 29391 | { PseudoVSADDU_VX_M2, VSADDU_VX }, // 8121 |
| 29392 | { PseudoVSADDU_VX_M2_MASK, VSADDU_VX }, // 8122 |
| 29393 | { PseudoVSADDU_VX_M4, VSADDU_VX }, // 8123 |
| 29394 | { PseudoVSADDU_VX_M4_MASK, VSADDU_VX }, // 8124 |
| 29395 | { PseudoVSADDU_VX_M8, VSADDU_VX }, // 8125 |
| 29396 | { PseudoVSADDU_VX_M8_MASK, VSADDU_VX }, // 8126 |
| 29397 | { PseudoVSADDU_VX_MF2, VSADDU_VX }, // 8127 |
| 29398 | { PseudoVSADDU_VX_MF2_MASK, VSADDU_VX }, // 8128 |
| 29399 | { PseudoVSADDU_VX_MF4, VSADDU_VX }, // 8129 |
| 29400 | { PseudoVSADDU_VX_MF4_MASK, VSADDU_VX }, // 8130 |
| 29401 | { PseudoVSADDU_VX_MF8, VSADDU_VX }, // 8131 |
| 29402 | { PseudoVSADDU_VX_MF8_MASK, VSADDU_VX }, // 8132 |
| 29403 | { PseudoVSADD_VI_M1, VSADD_VI }, // 8133 |
| 29404 | { PseudoVSADD_VI_M1_MASK, VSADD_VI }, // 8134 |
| 29405 | { PseudoVSADD_VI_M2, VSADD_VI }, // 8135 |
| 29406 | { PseudoVSADD_VI_M2_MASK, VSADD_VI }, // 8136 |
| 29407 | { PseudoVSADD_VI_M4, VSADD_VI }, // 8137 |
| 29408 | { PseudoVSADD_VI_M4_MASK, VSADD_VI }, // 8138 |
| 29409 | { PseudoVSADD_VI_M8, VSADD_VI }, // 8139 |
| 29410 | { PseudoVSADD_VI_M8_MASK, VSADD_VI }, // 8140 |
| 29411 | { PseudoVSADD_VI_MF2, VSADD_VI }, // 8141 |
| 29412 | { PseudoVSADD_VI_MF2_MASK, VSADD_VI }, // 8142 |
| 29413 | { PseudoVSADD_VI_MF4, VSADD_VI }, // 8143 |
| 29414 | { PseudoVSADD_VI_MF4_MASK, VSADD_VI }, // 8144 |
| 29415 | { PseudoVSADD_VI_MF8, VSADD_VI }, // 8145 |
| 29416 | { PseudoVSADD_VI_MF8_MASK, VSADD_VI }, // 8146 |
| 29417 | { PseudoVSADD_VV_M1, VSADD_VV }, // 8147 |
| 29418 | { PseudoVSADD_VV_M1_MASK, VSADD_VV }, // 8148 |
| 29419 | { PseudoVSADD_VV_M2, VSADD_VV }, // 8149 |
| 29420 | { PseudoVSADD_VV_M2_MASK, VSADD_VV }, // 8150 |
| 29421 | { PseudoVSADD_VV_M4, VSADD_VV }, // 8151 |
| 29422 | { PseudoVSADD_VV_M4_MASK, VSADD_VV }, // 8152 |
| 29423 | { PseudoVSADD_VV_M8, VSADD_VV }, // 8153 |
| 29424 | { PseudoVSADD_VV_M8_MASK, VSADD_VV }, // 8154 |
| 29425 | { PseudoVSADD_VV_MF2, VSADD_VV }, // 8155 |
| 29426 | { PseudoVSADD_VV_MF2_MASK, VSADD_VV }, // 8156 |
| 29427 | { PseudoVSADD_VV_MF4, VSADD_VV }, // 8157 |
| 29428 | { PseudoVSADD_VV_MF4_MASK, VSADD_VV }, // 8158 |
| 29429 | { PseudoVSADD_VV_MF8, VSADD_VV }, // 8159 |
| 29430 | { PseudoVSADD_VV_MF8_MASK, VSADD_VV }, // 8160 |
| 29431 | { PseudoVSADD_VX_M1, VSADD_VX }, // 8161 |
| 29432 | { PseudoVSADD_VX_M1_MASK, VSADD_VX }, // 8162 |
| 29433 | { PseudoVSADD_VX_M2, VSADD_VX }, // 8163 |
| 29434 | { PseudoVSADD_VX_M2_MASK, VSADD_VX }, // 8164 |
| 29435 | { PseudoVSADD_VX_M4, VSADD_VX }, // 8165 |
| 29436 | { PseudoVSADD_VX_M4_MASK, VSADD_VX }, // 8166 |
| 29437 | { PseudoVSADD_VX_M8, VSADD_VX }, // 8167 |
| 29438 | { PseudoVSADD_VX_M8_MASK, VSADD_VX }, // 8168 |
| 29439 | { PseudoVSADD_VX_MF2, VSADD_VX }, // 8169 |
| 29440 | { PseudoVSADD_VX_MF2_MASK, VSADD_VX }, // 8170 |
| 29441 | { PseudoVSADD_VX_MF4, VSADD_VX }, // 8171 |
| 29442 | { PseudoVSADD_VX_MF4_MASK, VSADD_VX }, // 8172 |
| 29443 | { PseudoVSADD_VX_MF8, VSADD_VX }, // 8173 |
| 29444 | { PseudoVSADD_VX_MF8_MASK, VSADD_VX }, // 8174 |
| 29445 | { PseudoVSBC_VVM_M1, VSBC_VVM }, // 8175 |
| 29446 | { PseudoVSBC_VVM_M2, VSBC_VVM }, // 8176 |
| 29447 | { PseudoVSBC_VVM_M4, VSBC_VVM }, // 8177 |
| 29448 | { PseudoVSBC_VVM_M8, VSBC_VVM }, // 8178 |
| 29449 | { PseudoVSBC_VVM_MF2, VSBC_VVM }, // 8179 |
| 29450 | { PseudoVSBC_VVM_MF4, VSBC_VVM }, // 8180 |
| 29451 | { PseudoVSBC_VVM_MF8, VSBC_VVM }, // 8181 |
| 29452 | { PseudoVSBC_VXM_M1, VSBC_VXM }, // 8182 |
| 29453 | { PseudoVSBC_VXM_M2, VSBC_VXM }, // 8183 |
| 29454 | { PseudoVSBC_VXM_M4, VSBC_VXM }, // 8184 |
| 29455 | { PseudoVSBC_VXM_M8, VSBC_VXM }, // 8185 |
| 29456 | { PseudoVSBC_VXM_MF2, VSBC_VXM }, // 8186 |
| 29457 | { PseudoVSBC_VXM_MF4, VSBC_VXM }, // 8187 |
| 29458 | { PseudoVSBC_VXM_MF8, VSBC_VXM }, // 8188 |
| 29459 | { PseudoVSE16_V_M1, VSE16_V }, // 8189 |
| 29460 | { PseudoVSE16_V_M1_MASK, VSE16_V }, // 8190 |
| 29461 | { PseudoVSE16_V_M2, VSE16_V }, // 8191 |
| 29462 | { PseudoVSE16_V_M2_MASK, VSE16_V }, // 8192 |
| 29463 | { PseudoVSE16_V_M4, VSE16_V }, // 8193 |
| 29464 | { PseudoVSE16_V_M4_MASK, VSE16_V }, // 8194 |
| 29465 | { PseudoVSE16_V_M8, VSE16_V }, // 8195 |
| 29466 | { PseudoVSE16_V_M8_MASK, VSE16_V }, // 8196 |
| 29467 | { PseudoVSE16_V_MF2, VSE16_V }, // 8197 |
| 29468 | { PseudoVSE16_V_MF2_MASK, VSE16_V }, // 8198 |
| 29469 | { PseudoVSE16_V_MF4, VSE16_V }, // 8199 |
| 29470 | { PseudoVSE16_V_MF4_MASK, VSE16_V }, // 8200 |
| 29471 | { PseudoVSE32_V_M1, VSE32_V }, // 8201 |
| 29472 | { PseudoVSE32_V_M1_MASK, VSE32_V }, // 8202 |
| 29473 | { PseudoVSE32_V_M2, VSE32_V }, // 8203 |
| 29474 | { PseudoVSE32_V_M2_MASK, VSE32_V }, // 8204 |
| 29475 | { PseudoVSE32_V_M4, VSE32_V }, // 8205 |
| 29476 | { PseudoVSE32_V_M4_MASK, VSE32_V }, // 8206 |
| 29477 | { PseudoVSE32_V_M8, VSE32_V }, // 8207 |
| 29478 | { PseudoVSE32_V_M8_MASK, VSE32_V }, // 8208 |
| 29479 | { PseudoVSE32_V_MF2, VSE32_V }, // 8209 |
| 29480 | { PseudoVSE32_V_MF2_MASK, VSE32_V }, // 8210 |
| 29481 | { PseudoVSE64_V_M1, VSE64_V }, // 8211 |
| 29482 | { PseudoVSE64_V_M1_MASK, VSE64_V }, // 8212 |
| 29483 | { PseudoVSE64_V_M2, VSE64_V }, // 8213 |
| 29484 | { PseudoVSE64_V_M2_MASK, VSE64_V }, // 8214 |
| 29485 | { PseudoVSE64_V_M4, VSE64_V }, // 8215 |
| 29486 | { PseudoVSE64_V_M4_MASK, VSE64_V }, // 8216 |
| 29487 | { PseudoVSE64_V_M8, VSE64_V }, // 8217 |
| 29488 | { PseudoVSE64_V_M8_MASK, VSE64_V }, // 8218 |
| 29489 | { PseudoVSE8_V_M1, VSE8_V }, // 8219 |
| 29490 | { PseudoVSE8_V_M1_MASK, VSE8_V }, // 8220 |
| 29491 | { PseudoVSE8_V_M2, VSE8_V }, // 8221 |
| 29492 | { PseudoVSE8_V_M2_MASK, VSE8_V }, // 8222 |
| 29493 | { PseudoVSE8_V_M4, VSE8_V }, // 8223 |
| 29494 | { PseudoVSE8_V_M4_MASK, VSE8_V }, // 8224 |
| 29495 | { PseudoVSE8_V_M8, VSE8_V }, // 8225 |
| 29496 | { PseudoVSE8_V_M8_MASK, VSE8_V }, // 8226 |
| 29497 | { PseudoVSE8_V_MF2, VSE8_V }, // 8227 |
| 29498 | { PseudoVSE8_V_MF2_MASK, VSE8_V }, // 8228 |
| 29499 | { PseudoVSE8_V_MF4, VSE8_V }, // 8229 |
| 29500 | { PseudoVSE8_V_MF4_MASK, VSE8_V }, // 8230 |
| 29501 | { PseudoVSE8_V_MF8, VSE8_V }, // 8231 |
| 29502 | { PseudoVSE8_V_MF8_MASK, VSE8_V }, // 8232 |
| 29503 | { PseudoVSEXT_VF2_M1, VSEXT_VF2 }, // 8233 |
| 29504 | { PseudoVSEXT_VF2_M1_MASK, VSEXT_VF2 }, // 8234 |
| 29505 | { PseudoVSEXT_VF2_M2, VSEXT_VF2 }, // 8235 |
| 29506 | { PseudoVSEXT_VF2_M2_MASK, VSEXT_VF2 }, // 8236 |
| 29507 | { PseudoVSEXT_VF2_M4, VSEXT_VF2 }, // 8237 |
| 29508 | { PseudoVSEXT_VF2_M4_MASK, VSEXT_VF2 }, // 8238 |
| 29509 | { PseudoVSEXT_VF2_M8, VSEXT_VF2 }, // 8239 |
| 29510 | { PseudoVSEXT_VF2_M8_MASK, VSEXT_VF2 }, // 8240 |
| 29511 | { PseudoVSEXT_VF2_MF2, VSEXT_VF2 }, // 8241 |
| 29512 | { PseudoVSEXT_VF2_MF2_MASK, VSEXT_VF2 }, // 8242 |
| 29513 | { PseudoVSEXT_VF2_MF4, VSEXT_VF2 }, // 8243 |
| 29514 | { PseudoVSEXT_VF2_MF4_MASK, VSEXT_VF2 }, // 8244 |
| 29515 | { PseudoVSEXT_VF4_M1, VSEXT_VF4 }, // 8245 |
| 29516 | { PseudoVSEXT_VF4_M1_MASK, VSEXT_VF4 }, // 8246 |
| 29517 | { PseudoVSEXT_VF4_M2, VSEXT_VF4 }, // 8247 |
| 29518 | { PseudoVSEXT_VF4_M2_MASK, VSEXT_VF4 }, // 8248 |
| 29519 | { PseudoVSEXT_VF4_M4, VSEXT_VF4 }, // 8249 |
| 29520 | { PseudoVSEXT_VF4_M4_MASK, VSEXT_VF4 }, // 8250 |
| 29521 | { PseudoVSEXT_VF4_M8, VSEXT_VF4 }, // 8251 |
| 29522 | { PseudoVSEXT_VF4_M8_MASK, VSEXT_VF4 }, // 8252 |
| 29523 | { PseudoVSEXT_VF4_MF2, VSEXT_VF4 }, // 8253 |
| 29524 | { PseudoVSEXT_VF4_MF2_MASK, VSEXT_VF4 }, // 8254 |
| 29525 | { PseudoVSEXT_VF8_M1, VSEXT_VF8 }, // 8255 |
| 29526 | { PseudoVSEXT_VF8_M1_MASK, VSEXT_VF8 }, // 8256 |
| 29527 | { PseudoVSEXT_VF8_M2, VSEXT_VF8 }, // 8257 |
| 29528 | { PseudoVSEXT_VF8_M2_MASK, VSEXT_VF8 }, // 8258 |
| 29529 | { PseudoVSEXT_VF8_M4, VSEXT_VF8 }, // 8259 |
| 29530 | { PseudoVSEXT_VF8_M4_MASK, VSEXT_VF8 }, // 8260 |
| 29531 | { PseudoVSEXT_VF8_M8, VSEXT_VF8 }, // 8261 |
| 29532 | { PseudoVSEXT_VF8_M8_MASK, VSEXT_VF8 }, // 8262 |
| 29533 | { PseudoVSHA2CH_VV_M1, VSHA2CH_VV }, // 8263 |
| 29534 | { PseudoVSHA2CH_VV_M2, VSHA2CH_VV }, // 8264 |
| 29535 | { PseudoVSHA2CH_VV_M4, VSHA2CH_VV }, // 8265 |
| 29536 | { PseudoVSHA2CH_VV_M8, VSHA2CH_VV }, // 8266 |
| 29537 | { PseudoVSHA2CH_VV_MF2, VSHA2CH_VV }, // 8267 |
| 29538 | { PseudoVSHA2CL_VV_M1, VSHA2CL_VV }, // 8268 |
| 29539 | { PseudoVSHA2CL_VV_M2, VSHA2CL_VV }, // 8269 |
| 29540 | { PseudoVSHA2CL_VV_M4, VSHA2CL_VV }, // 8270 |
| 29541 | { PseudoVSHA2CL_VV_M8, VSHA2CL_VV }, // 8271 |
| 29542 | { PseudoVSHA2CL_VV_MF2, VSHA2CL_VV }, // 8272 |
| 29543 | { PseudoVSHA2MS_VV_M1, VSHA2MS_VV }, // 8273 |
| 29544 | { PseudoVSHA2MS_VV_M2, VSHA2MS_VV }, // 8274 |
| 29545 | { PseudoVSHA2MS_VV_M4, VSHA2MS_VV }, // 8275 |
| 29546 | { PseudoVSHA2MS_VV_M8, VSHA2MS_VV }, // 8276 |
| 29547 | { PseudoVSHA2MS_VV_MF2, VSHA2MS_VV }, // 8277 |
| 29548 | { PseudoVSLIDE1DOWN_VX_M1, VSLIDE1DOWN_VX }, // 8278 |
| 29549 | { PseudoVSLIDE1DOWN_VX_M1_MASK, VSLIDE1DOWN_VX }, // 8279 |
| 29550 | { PseudoVSLIDE1DOWN_VX_M2, VSLIDE1DOWN_VX }, // 8280 |
| 29551 | { PseudoVSLIDE1DOWN_VX_M2_MASK, VSLIDE1DOWN_VX }, // 8281 |
| 29552 | { PseudoVSLIDE1DOWN_VX_M4, VSLIDE1DOWN_VX }, // 8282 |
| 29553 | { PseudoVSLIDE1DOWN_VX_M4_MASK, VSLIDE1DOWN_VX }, // 8283 |
| 29554 | { PseudoVSLIDE1DOWN_VX_M8, VSLIDE1DOWN_VX }, // 8284 |
| 29555 | { PseudoVSLIDE1DOWN_VX_M8_MASK, VSLIDE1DOWN_VX }, // 8285 |
| 29556 | { PseudoVSLIDE1DOWN_VX_MF2, VSLIDE1DOWN_VX }, // 8286 |
| 29557 | { PseudoVSLIDE1DOWN_VX_MF2_MASK, VSLIDE1DOWN_VX }, // 8287 |
| 29558 | { PseudoVSLIDE1DOWN_VX_MF4, VSLIDE1DOWN_VX }, // 8288 |
| 29559 | { PseudoVSLIDE1DOWN_VX_MF4_MASK, VSLIDE1DOWN_VX }, // 8289 |
| 29560 | { PseudoVSLIDE1DOWN_VX_MF8, VSLIDE1DOWN_VX }, // 8290 |
| 29561 | { PseudoVSLIDE1DOWN_VX_MF8_MASK, VSLIDE1DOWN_VX }, // 8291 |
| 29562 | { PseudoVSLIDE1UP_VX_M1, VSLIDE1UP_VX }, // 8292 |
| 29563 | { PseudoVSLIDE1UP_VX_M1_MASK, VSLIDE1UP_VX }, // 8293 |
| 29564 | { PseudoVSLIDE1UP_VX_M2, VSLIDE1UP_VX }, // 8294 |
| 29565 | { PseudoVSLIDE1UP_VX_M2_MASK, VSLIDE1UP_VX }, // 8295 |
| 29566 | { PseudoVSLIDE1UP_VX_M4, VSLIDE1UP_VX }, // 8296 |
| 29567 | { PseudoVSLIDE1UP_VX_M4_MASK, VSLIDE1UP_VX }, // 8297 |
| 29568 | { PseudoVSLIDE1UP_VX_M8, VSLIDE1UP_VX }, // 8298 |
| 29569 | { PseudoVSLIDE1UP_VX_M8_MASK, VSLIDE1UP_VX }, // 8299 |
| 29570 | { PseudoVSLIDE1UP_VX_MF2, VSLIDE1UP_VX }, // 8300 |
| 29571 | { PseudoVSLIDE1UP_VX_MF2_MASK, VSLIDE1UP_VX }, // 8301 |
| 29572 | { PseudoVSLIDE1UP_VX_MF4, VSLIDE1UP_VX }, // 8302 |
| 29573 | { PseudoVSLIDE1UP_VX_MF4_MASK, VSLIDE1UP_VX }, // 8303 |
| 29574 | { PseudoVSLIDE1UP_VX_MF8, VSLIDE1UP_VX }, // 8304 |
| 29575 | { PseudoVSLIDE1UP_VX_MF8_MASK, VSLIDE1UP_VX }, // 8305 |
| 29576 | { PseudoVSLIDEDOWN_VI_M1, VSLIDEDOWN_VI }, // 8306 |
| 29577 | { PseudoVSLIDEDOWN_VI_M1_MASK, VSLIDEDOWN_VI }, // 8307 |
| 29578 | { PseudoVSLIDEDOWN_VI_M2, VSLIDEDOWN_VI }, // 8308 |
| 29579 | { PseudoVSLIDEDOWN_VI_M2_MASK, VSLIDEDOWN_VI }, // 8309 |
| 29580 | { PseudoVSLIDEDOWN_VI_M4, VSLIDEDOWN_VI }, // 8310 |
| 29581 | { PseudoVSLIDEDOWN_VI_M4_MASK, VSLIDEDOWN_VI }, // 8311 |
| 29582 | { PseudoVSLIDEDOWN_VI_M8, VSLIDEDOWN_VI }, // 8312 |
| 29583 | { PseudoVSLIDEDOWN_VI_M8_MASK, VSLIDEDOWN_VI }, // 8313 |
| 29584 | { PseudoVSLIDEDOWN_VI_MF2, VSLIDEDOWN_VI }, // 8314 |
| 29585 | { PseudoVSLIDEDOWN_VI_MF2_MASK, VSLIDEDOWN_VI }, // 8315 |
| 29586 | { PseudoVSLIDEDOWN_VI_MF4, VSLIDEDOWN_VI }, // 8316 |
| 29587 | { PseudoVSLIDEDOWN_VI_MF4_MASK, VSLIDEDOWN_VI }, // 8317 |
| 29588 | { PseudoVSLIDEDOWN_VI_MF8, VSLIDEDOWN_VI }, // 8318 |
| 29589 | { PseudoVSLIDEDOWN_VI_MF8_MASK, VSLIDEDOWN_VI }, // 8319 |
| 29590 | { PseudoVSLIDEDOWN_VX_M1, VSLIDEDOWN_VX }, // 8320 |
| 29591 | { PseudoVSLIDEDOWN_VX_M1_MASK, VSLIDEDOWN_VX }, // 8321 |
| 29592 | { PseudoVSLIDEDOWN_VX_M2, VSLIDEDOWN_VX }, // 8322 |
| 29593 | { PseudoVSLIDEDOWN_VX_M2_MASK, VSLIDEDOWN_VX }, // 8323 |
| 29594 | { PseudoVSLIDEDOWN_VX_M4, VSLIDEDOWN_VX }, // 8324 |
| 29595 | { PseudoVSLIDEDOWN_VX_M4_MASK, VSLIDEDOWN_VX }, // 8325 |
| 29596 | { PseudoVSLIDEDOWN_VX_M8, VSLIDEDOWN_VX }, // 8326 |
| 29597 | { PseudoVSLIDEDOWN_VX_M8_MASK, VSLIDEDOWN_VX }, // 8327 |
| 29598 | { PseudoVSLIDEDOWN_VX_MF2, VSLIDEDOWN_VX }, // 8328 |
| 29599 | { PseudoVSLIDEDOWN_VX_MF2_MASK, VSLIDEDOWN_VX }, // 8329 |
| 29600 | { PseudoVSLIDEDOWN_VX_MF4, VSLIDEDOWN_VX }, // 8330 |
| 29601 | { PseudoVSLIDEDOWN_VX_MF4_MASK, VSLIDEDOWN_VX }, // 8331 |
| 29602 | { PseudoVSLIDEDOWN_VX_MF8, VSLIDEDOWN_VX }, // 8332 |
| 29603 | { PseudoVSLIDEDOWN_VX_MF8_MASK, VSLIDEDOWN_VX }, // 8333 |
| 29604 | { PseudoVSLIDEUP_VI_M1, VSLIDEUP_VI }, // 8334 |
| 29605 | { PseudoVSLIDEUP_VI_M1_MASK, VSLIDEUP_VI }, // 8335 |
| 29606 | { PseudoVSLIDEUP_VI_M2, VSLIDEUP_VI }, // 8336 |
| 29607 | { PseudoVSLIDEUP_VI_M2_MASK, VSLIDEUP_VI }, // 8337 |
| 29608 | { PseudoVSLIDEUP_VI_M4, VSLIDEUP_VI }, // 8338 |
| 29609 | { PseudoVSLIDEUP_VI_M4_MASK, VSLIDEUP_VI }, // 8339 |
| 29610 | { PseudoVSLIDEUP_VI_M8, VSLIDEUP_VI }, // 8340 |
| 29611 | { PseudoVSLIDEUP_VI_M8_MASK, VSLIDEUP_VI }, // 8341 |
| 29612 | { PseudoVSLIDEUP_VI_MF2, VSLIDEUP_VI }, // 8342 |
| 29613 | { PseudoVSLIDEUP_VI_MF2_MASK, VSLIDEUP_VI }, // 8343 |
| 29614 | { PseudoVSLIDEUP_VI_MF4, VSLIDEUP_VI }, // 8344 |
| 29615 | { PseudoVSLIDEUP_VI_MF4_MASK, VSLIDEUP_VI }, // 8345 |
| 29616 | { PseudoVSLIDEUP_VI_MF8, VSLIDEUP_VI }, // 8346 |
| 29617 | { PseudoVSLIDEUP_VI_MF8_MASK, VSLIDEUP_VI }, // 8347 |
| 29618 | { PseudoVSLIDEUP_VX_M1, VSLIDEUP_VX }, // 8348 |
| 29619 | { PseudoVSLIDEUP_VX_M1_MASK, VSLIDEUP_VX }, // 8349 |
| 29620 | { PseudoVSLIDEUP_VX_M2, VSLIDEUP_VX }, // 8350 |
| 29621 | { PseudoVSLIDEUP_VX_M2_MASK, VSLIDEUP_VX }, // 8351 |
| 29622 | { PseudoVSLIDEUP_VX_M4, VSLIDEUP_VX }, // 8352 |
| 29623 | { PseudoVSLIDEUP_VX_M4_MASK, VSLIDEUP_VX }, // 8353 |
| 29624 | { PseudoVSLIDEUP_VX_M8, VSLIDEUP_VX }, // 8354 |
| 29625 | { PseudoVSLIDEUP_VX_M8_MASK, VSLIDEUP_VX }, // 8355 |
| 29626 | { PseudoVSLIDEUP_VX_MF2, VSLIDEUP_VX }, // 8356 |
| 29627 | { PseudoVSLIDEUP_VX_MF2_MASK, VSLIDEUP_VX }, // 8357 |
| 29628 | { PseudoVSLIDEUP_VX_MF4, VSLIDEUP_VX }, // 8358 |
| 29629 | { PseudoVSLIDEUP_VX_MF4_MASK, VSLIDEUP_VX }, // 8359 |
| 29630 | { PseudoVSLIDEUP_VX_MF8, VSLIDEUP_VX }, // 8360 |
| 29631 | { PseudoVSLIDEUP_VX_MF8_MASK, VSLIDEUP_VX }, // 8361 |
| 29632 | { PseudoVSLL_VI_M1, VSLL_VI }, // 8362 |
| 29633 | { PseudoVSLL_VI_M1_MASK, VSLL_VI }, // 8363 |
| 29634 | { PseudoVSLL_VI_M2, VSLL_VI }, // 8364 |
| 29635 | { PseudoVSLL_VI_M2_MASK, VSLL_VI }, // 8365 |
| 29636 | { PseudoVSLL_VI_M4, VSLL_VI }, // 8366 |
| 29637 | { PseudoVSLL_VI_M4_MASK, VSLL_VI }, // 8367 |
| 29638 | { PseudoVSLL_VI_M8, VSLL_VI }, // 8368 |
| 29639 | { PseudoVSLL_VI_M8_MASK, VSLL_VI }, // 8369 |
| 29640 | { PseudoVSLL_VI_MF2, VSLL_VI }, // 8370 |
| 29641 | { PseudoVSLL_VI_MF2_MASK, VSLL_VI }, // 8371 |
| 29642 | { PseudoVSLL_VI_MF4, VSLL_VI }, // 8372 |
| 29643 | { PseudoVSLL_VI_MF4_MASK, VSLL_VI }, // 8373 |
| 29644 | { PseudoVSLL_VI_MF8, VSLL_VI }, // 8374 |
| 29645 | { PseudoVSLL_VI_MF8_MASK, VSLL_VI }, // 8375 |
| 29646 | { PseudoVSLL_VV_M1, VSLL_VV }, // 8376 |
| 29647 | { PseudoVSLL_VV_M1_MASK, VSLL_VV }, // 8377 |
| 29648 | { PseudoVSLL_VV_M2, VSLL_VV }, // 8378 |
| 29649 | { PseudoVSLL_VV_M2_MASK, VSLL_VV }, // 8379 |
| 29650 | { PseudoVSLL_VV_M4, VSLL_VV }, // 8380 |
| 29651 | { PseudoVSLL_VV_M4_MASK, VSLL_VV }, // 8381 |
| 29652 | { PseudoVSLL_VV_M8, VSLL_VV }, // 8382 |
| 29653 | { PseudoVSLL_VV_M8_MASK, VSLL_VV }, // 8383 |
| 29654 | { PseudoVSLL_VV_MF2, VSLL_VV }, // 8384 |
| 29655 | { PseudoVSLL_VV_MF2_MASK, VSLL_VV }, // 8385 |
| 29656 | { PseudoVSLL_VV_MF4, VSLL_VV }, // 8386 |
| 29657 | { PseudoVSLL_VV_MF4_MASK, VSLL_VV }, // 8387 |
| 29658 | { PseudoVSLL_VV_MF8, VSLL_VV }, // 8388 |
| 29659 | { PseudoVSLL_VV_MF8_MASK, VSLL_VV }, // 8389 |
| 29660 | { PseudoVSLL_VX_M1, VSLL_VX }, // 8390 |
| 29661 | { PseudoVSLL_VX_M1_MASK, VSLL_VX }, // 8391 |
| 29662 | { PseudoVSLL_VX_M2, VSLL_VX }, // 8392 |
| 29663 | { PseudoVSLL_VX_M2_MASK, VSLL_VX }, // 8393 |
| 29664 | { PseudoVSLL_VX_M4, VSLL_VX }, // 8394 |
| 29665 | { PseudoVSLL_VX_M4_MASK, VSLL_VX }, // 8395 |
| 29666 | { PseudoVSLL_VX_M8, VSLL_VX }, // 8396 |
| 29667 | { PseudoVSLL_VX_M8_MASK, VSLL_VX }, // 8397 |
| 29668 | { PseudoVSLL_VX_MF2, VSLL_VX }, // 8398 |
| 29669 | { PseudoVSLL_VX_MF2_MASK, VSLL_VX }, // 8399 |
| 29670 | { PseudoVSLL_VX_MF4, VSLL_VX }, // 8400 |
| 29671 | { PseudoVSLL_VX_MF4_MASK, VSLL_VX }, // 8401 |
| 29672 | { PseudoVSLL_VX_MF8, VSLL_VX }, // 8402 |
| 29673 | { PseudoVSLL_VX_MF8_MASK, VSLL_VX }, // 8403 |
| 29674 | { PseudoVSM3C_VI_M1, VSM3C_VI }, // 8404 |
| 29675 | { PseudoVSM3C_VI_M2, VSM3C_VI }, // 8405 |
| 29676 | { PseudoVSM3C_VI_M4, VSM3C_VI }, // 8406 |
| 29677 | { PseudoVSM3C_VI_M8, VSM3C_VI }, // 8407 |
| 29678 | { PseudoVSM3C_VI_MF2, VSM3C_VI }, // 8408 |
| 29679 | { PseudoVSM3ME_VV_M1, VSM3ME_VV }, // 8409 |
| 29680 | { PseudoVSM3ME_VV_M2, VSM3ME_VV }, // 8410 |
| 29681 | { PseudoVSM3ME_VV_M4, VSM3ME_VV }, // 8411 |
| 29682 | { PseudoVSM3ME_VV_M8, VSM3ME_VV }, // 8412 |
| 29683 | { PseudoVSM3ME_VV_MF2, VSM3ME_VV }, // 8413 |
| 29684 | { PseudoVSM4K_VI_M1, VSM4K_VI }, // 8414 |
| 29685 | { PseudoVSM4K_VI_M2, VSM4K_VI }, // 8415 |
| 29686 | { PseudoVSM4K_VI_M4, VSM4K_VI }, // 8416 |
| 29687 | { PseudoVSM4K_VI_M8, VSM4K_VI }, // 8417 |
| 29688 | { PseudoVSM4K_VI_MF2, VSM4K_VI }, // 8418 |
| 29689 | { PseudoVSM4R_VS_M1_M1, VSM4R_VS }, // 8419 |
| 29690 | { PseudoVSM4R_VS_M1_MF2, VSM4R_VS }, // 8420 |
| 29691 | { PseudoVSM4R_VS_M1_MF4, VSM4R_VS }, // 8421 |
| 29692 | { PseudoVSM4R_VS_M1_MF8, VSM4R_VS }, // 8422 |
| 29693 | { PseudoVSM4R_VS_M2_M1, VSM4R_VS }, // 8423 |
| 29694 | { PseudoVSM4R_VS_M2_M2, VSM4R_VS }, // 8424 |
| 29695 | { PseudoVSM4R_VS_M2_MF2, VSM4R_VS }, // 8425 |
| 29696 | { PseudoVSM4R_VS_M2_MF4, VSM4R_VS }, // 8426 |
| 29697 | { PseudoVSM4R_VS_M2_MF8, VSM4R_VS }, // 8427 |
| 29698 | { PseudoVSM4R_VS_M4_M1, VSM4R_VS }, // 8428 |
| 29699 | { PseudoVSM4R_VS_M4_M2, VSM4R_VS }, // 8429 |
| 29700 | { PseudoVSM4R_VS_M4_M4, VSM4R_VS }, // 8430 |
| 29701 | { PseudoVSM4R_VS_M4_MF2, VSM4R_VS }, // 8431 |
| 29702 | { PseudoVSM4R_VS_M4_MF4, VSM4R_VS }, // 8432 |
| 29703 | { PseudoVSM4R_VS_M4_MF8, VSM4R_VS }, // 8433 |
| 29704 | { PseudoVSM4R_VS_M8_M1, VSM4R_VS }, // 8434 |
| 29705 | { PseudoVSM4R_VS_M8_M2, VSM4R_VS }, // 8435 |
| 29706 | { PseudoVSM4R_VS_M8_M4, VSM4R_VS }, // 8436 |
| 29707 | { PseudoVSM4R_VS_M8_MF2, VSM4R_VS }, // 8437 |
| 29708 | { PseudoVSM4R_VS_M8_MF4, VSM4R_VS }, // 8438 |
| 29709 | { PseudoVSM4R_VS_M8_MF8, VSM4R_VS }, // 8439 |
| 29710 | { PseudoVSM4R_VS_MF2_MF2, VSM4R_VS }, // 8440 |
| 29711 | { PseudoVSM4R_VS_MF2_MF4, VSM4R_VS }, // 8441 |
| 29712 | { PseudoVSM4R_VS_MF2_MF8, VSM4R_VS }, // 8442 |
| 29713 | { PseudoVSM4R_VV_M1, VSM4R_VV }, // 8443 |
| 29714 | { PseudoVSM4R_VV_M2, VSM4R_VV }, // 8444 |
| 29715 | { PseudoVSM4R_VV_M4, VSM4R_VV }, // 8445 |
| 29716 | { PseudoVSM4R_VV_M8, VSM4R_VV }, // 8446 |
| 29717 | { PseudoVSM4R_VV_MF2, VSM4R_VV }, // 8447 |
| 29718 | { PseudoVSMUL_VV_M1, VSMUL_VV }, // 8448 |
| 29719 | { PseudoVSMUL_VV_M1_MASK, VSMUL_VV }, // 8449 |
| 29720 | { PseudoVSMUL_VV_M2, VSMUL_VV }, // 8450 |
| 29721 | { PseudoVSMUL_VV_M2_MASK, VSMUL_VV }, // 8451 |
| 29722 | { PseudoVSMUL_VV_M4, VSMUL_VV }, // 8452 |
| 29723 | { PseudoVSMUL_VV_M4_MASK, VSMUL_VV }, // 8453 |
| 29724 | { PseudoVSMUL_VV_M8, VSMUL_VV }, // 8454 |
| 29725 | { PseudoVSMUL_VV_M8_MASK, VSMUL_VV }, // 8455 |
| 29726 | { PseudoVSMUL_VV_MF2, VSMUL_VV }, // 8456 |
| 29727 | { PseudoVSMUL_VV_MF2_MASK, VSMUL_VV }, // 8457 |
| 29728 | { PseudoVSMUL_VV_MF4, VSMUL_VV }, // 8458 |
| 29729 | { PseudoVSMUL_VV_MF4_MASK, VSMUL_VV }, // 8459 |
| 29730 | { PseudoVSMUL_VV_MF8, VSMUL_VV }, // 8460 |
| 29731 | { PseudoVSMUL_VV_MF8_MASK, VSMUL_VV }, // 8461 |
| 29732 | { PseudoVSMUL_VX_M1, VSMUL_VX }, // 8462 |
| 29733 | { PseudoVSMUL_VX_M1_MASK, VSMUL_VX }, // 8463 |
| 29734 | { PseudoVSMUL_VX_M2, VSMUL_VX }, // 8464 |
| 29735 | { PseudoVSMUL_VX_M2_MASK, VSMUL_VX }, // 8465 |
| 29736 | { PseudoVSMUL_VX_M4, VSMUL_VX }, // 8466 |
| 29737 | { PseudoVSMUL_VX_M4_MASK, VSMUL_VX }, // 8467 |
| 29738 | { PseudoVSMUL_VX_M8, VSMUL_VX }, // 8468 |
| 29739 | { PseudoVSMUL_VX_M8_MASK, VSMUL_VX }, // 8469 |
| 29740 | { PseudoVSMUL_VX_MF2, VSMUL_VX }, // 8470 |
| 29741 | { PseudoVSMUL_VX_MF2_MASK, VSMUL_VX }, // 8471 |
| 29742 | { PseudoVSMUL_VX_MF4, VSMUL_VX }, // 8472 |
| 29743 | { PseudoVSMUL_VX_MF4_MASK, VSMUL_VX }, // 8473 |
| 29744 | { PseudoVSMUL_VX_MF8, VSMUL_VX }, // 8474 |
| 29745 | { PseudoVSMUL_VX_MF8_MASK, VSMUL_VX }, // 8475 |
| 29746 | { PseudoVSM_V_B1, VSM_V }, // 8476 |
| 29747 | { PseudoVSM_V_B16, VSM_V }, // 8477 |
| 29748 | { PseudoVSM_V_B2, VSM_V }, // 8478 |
| 29749 | { PseudoVSM_V_B32, VSM_V }, // 8479 |
| 29750 | { PseudoVSM_V_B4, VSM_V }, // 8480 |
| 29751 | { PseudoVSM_V_B64, VSM_V }, // 8481 |
| 29752 | { PseudoVSM_V_B8, VSM_V }, // 8482 |
| 29753 | { PseudoVSOXEI16_V_M1_M1, VSOXEI16_V }, // 8483 |
| 29754 | { PseudoVSOXEI16_V_M1_M1_MASK, VSOXEI16_V }, // 8484 |
| 29755 | { PseudoVSOXEI16_V_M1_M2, VSOXEI16_V }, // 8485 |
| 29756 | { PseudoVSOXEI16_V_M1_M2_MASK, VSOXEI16_V }, // 8486 |
| 29757 | { PseudoVSOXEI16_V_M1_M4, VSOXEI16_V }, // 8487 |
| 29758 | { PseudoVSOXEI16_V_M1_M4_MASK, VSOXEI16_V }, // 8488 |
| 29759 | { PseudoVSOXEI16_V_M1_MF2, VSOXEI16_V }, // 8489 |
| 29760 | { PseudoVSOXEI16_V_M1_MF2_MASK, VSOXEI16_V }, // 8490 |
| 29761 | { PseudoVSOXEI16_V_M2_M1, VSOXEI16_V }, // 8491 |
| 29762 | { PseudoVSOXEI16_V_M2_M1_MASK, VSOXEI16_V }, // 8492 |
| 29763 | { PseudoVSOXEI16_V_M2_M2, VSOXEI16_V }, // 8493 |
| 29764 | { PseudoVSOXEI16_V_M2_M2_MASK, VSOXEI16_V }, // 8494 |
| 29765 | { PseudoVSOXEI16_V_M2_M4, VSOXEI16_V }, // 8495 |
| 29766 | { PseudoVSOXEI16_V_M2_M4_MASK, VSOXEI16_V }, // 8496 |
| 29767 | { PseudoVSOXEI16_V_M2_M8, VSOXEI16_V }, // 8497 |
| 29768 | { PseudoVSOXEI16_V_M2_M8_MASK, VSOXEI16_V }, // 8498 |
| 29769 | { PseudoVSOXEI16_V_M4_M2, VSOXEI16_V }, // 8499 |
| 29770 | { PseudoVSOXEI16_V_M4_M2_MASK, VSOXEI16_V }, // 8500 |
| 29771 | { PseudoVSOXEI16_V_M4_M4, VSOXEI16_V }, // 8501 |
| 29772 | { PseudoVSOXEI16_V_M4_M4_MASK, VSOXEI16_V }, // 8502 |
| 29773 | { PseudoVSOXEI16_V_M4_M8, VSOXEI16_V }, // 8503 |
| 29774 | { PseudoVSOXEI16_V_M4_M8_MASK, VSOXEI16_V }, // 8504 |
| 29775 | { PseudoVSOXEI16_V_M8_M4, VSOXEI16_V }, // 8505 |
| 29776 | { PseudoVSOXEI16_V_M8_M4_MASK, VSOXEI16_V }, // 8506 |
| 29777 | { PseudoVSOXEI16_V_M8_M8, VSOXEI16_V }, // 8507 |
| 29778 | { PseudoVSOXEI16_V_M8_M8_MASK, VSOXEI16_V }, // 8508 |
| 29779 | { PseudoVSOXEI16_V_MF2_M1, VSOXEI16_V }, // 8509 |
| 29780 | { PseudoVSOXEI16_V_MF2_M1_MASK, VSOXEI16_V }, // 8510 |
| 29781 | { PseudoVSOXEI16_V_MF2_M2, VSOXEI16_V }, // 8511 |
| 29782 | { PseudoVSOXEI16_V_MF2_M2_MASK, VSOXEI16_V }, // 8512 |
| 29783 | { PseudoVSOXEI16_V_MF2_MF2, VSOXEI16_V }, // 8513 |
| 29784 | { PseudoVSOXEI16_V_MF2_MF2_MASK, VSOXEI16_V }, // 8514 |
| 29785 | { PseudoVSOXEI16_V_MF2_MF4, VSOXEI16_V }, // 8515 |
| 29786 | { PseudoVSOXEI16_V_MF2_MF4_MASK, VSOXEI16_V }, // 8516 |
| 29787 | { PseudoVSOXEI16_V_MF4_M1, VSOXEI16_V }, // 8517 |
| 29788 | { PseudoVSOXEI16_V_MF4_M1_MASK, VSOXEI16_V }, // 8518 |
| 29789 | { PseudoVSOXEI16_V_MF4_MF2, VSOXEI16_V }, // 8519 |
| 29790 | { PseudoVSOXEI16_V_MF4_MF2_MASK, VSOXEI16_V }, // 8520 |
| 29791 | { PseudoVSOXEI16_V_MF4_MF4, VSOXEI16_V }, // 8521 |
| 29792 | { PseudoVSOXEI16_V_MF4_MF4_MASK, VSOXEI16_V }, // 8522 |
| 29793 | { PseudoVSOXEI16_V_MF4_MF8, VSOXEI16_V }, // 8523 |
| 29794 | { PseudoVSOXEI16_V_MF4_MF8_MASK, VSOXEI16_V }, // 8524 |
| 29795 | { PseudoVSOXEI32_V_M1_M1, VSOXEI32_V }, // 8525 |
| 29796 | { PseudoVSOXEI32_V_M1_M1_MASK, VSOXEI32_V }, // 8526 |
| 29797 | { PseudoVSOXEI32_V_M1_M2, VSOXEI32_V }, // 8527 |
| 29798 | { PseudoVSOXEI32_V_M1_M2_MASK, VSOXEI32_V }, // 8528 |
| 29799 | { PseudoVSOXEI32_V_M1_MF2, VSOXEI32_V }, // 8529 |
| 29800 | { PseudoVSOXEI32_V_M1_MF2_MASK, VSOXEI32_V }, // 8530 |
| 29801 | { PseudoVSOXEI32_V_M1_MF4, VSOXEI32_V }, // 8531 |
| 29802 | { PseudoVSOXEI32_V_M1_MF4_MASK, VSOXEI32_V }, // 8532 |
| 29803 | { PseudoVSOXEI32_V_M2_M1, VSOXEI32_V }, // 8533 |
| 29804 | { PseudoVSOXEI32_V_M2_M1_MASK, VSOXEI32_V }, // 8534 |
| 29805 | { PseudoVSOXEI32_V_M2_M2, VSOXEI32_V }, // 8535 |
| 29806 | { PseudoVSOXEI32_V_M2_M2_MASK, VSOXEI32_V }, // 8536 |
| 29807 | { PseudoVSOXEI32_V_M2_M4, VSOXEI32_V }, // 8537 |
| 29808 | { PseudoVSOXEI32_V_M2_M4_MASK, VSOXEI32_V }, // 8538 |
| 29809 | { PseudoVSOXEI32_V_M2_MF2, VSOXEI32_V }, // 8539 |
| 29810 | { PseudoVSOXEI32_V_M2_MF2_MASK, VSOXEI32_V }, // 8540 |
| 29811 | { PseudoVSOXEI32_V_M4_M1, VSOXEI32_V }, // 8541 |
| 29812 | { PseudoVSOXEI32_V_M4_M1_MASK, VSOXEI32_V }, // 8542 |
| 29813 | { PseudoVSOXEI32_V_M4_M2, VSOXEI32_V }, // 8543 |
| 29814 | { PseudoVSOXEI32_V_M4_M2_MASK, VSOXEI32_V }, // 8544 |
| 29815 | { PseudoVSOXEI32_V_M4_M4, VSOXEI32_V }, // 8545 |
| 29816 | { PseudoVSOXEI32_V_M4_M4_MASK, VSOXEI32_V }, // 8546 |
| 29817 | { PseudoVSOXEI32_V_M4_M8, VSOXEI32_V }, // 8547 |
| 29818 | { PseudoVSOXEI32_V_M4_M8_MASK, VSOXEI32_V }, // 8548 |
| 29819 | { PseudoVSOXEI32_V_M8_M2, VSOXEI32_V }, // 8549 |
| 29820 | { PseudoVSOXEI32_V_M8_M2_MASK, VSOXEI32_V }, // 8550 |
| 29821 | { PseudoVSOXEI32_V_M8_M4, VSOXEI32_V }, // 8551 |
| 29822 | { PseudoVSOXEI32_V_M8_M4_MASK, VSOXEI32_V }, // 8552 |
| 29823 | { PseudoVSOXEI32_V_M8_M8, VSOXEI32_V }, // 8553 |
| 29824 | { PseudoVSOXEI32_V_M8_M8_MASK, VSOXEI32_V }, // 8554 |
| 29825 | { PseudoVSOXEI32_V_MF2_M1, VSOXEI32_V }, // 8555 |
| 29826 | { PseudoVSOXEI32_V_MF2_M1_MASK, VSOXEI32_V }, // 8556 |
| 29827 | { PseudoVSOXEI32_V_MF2_MF2, VSOXEI32_V }, // 8557 |
| 29828 | { PseudoVSOXEI32_V_MF2_MF2_MASK, VSOXEI32_V }, // 8558 |
| 29829 | { PseudoVSOXEI32_V_MF2_MF4, VSOXEI32_V }, // 8559 |
| 29830 | { PseudoVSOXEI32_V_MF2_MF4_MASK, VSOXEI32_V }, // 8560 |
| 29831 | { PseudoVSOXEI32_V_MF2_MF8, VSOXEI32_V }, // 8561 |
| 29832 | { PseudoVSOXEI32_V_MF2_MF8_MASK, VSOXEI32_V }, // 8562 |
| 29833 | { PseudoVSOXEI64_V_M1_M1, VSOXEI64_V }, // 8563 |
| 29834 | { PseudoVSOXEI64_V_M1_M1_MASK, VSOXEI64_V }, // 8564 |
| 29835 | { PseudoVSOXEI64_V_M1_MF2, VSOXEI64_V }, // 8565 |
| 29836 | { PseudoVSOXEI64_V_M1_MF2_MASK, VSOXEI64_V }, // 8566 |
| 29837 | { PseudoVSOXEI64_V_M1_MF4, VSOXEI64_V }, // 8567 |
| 29838 | { PseudoVSOXEI64_V_M1_MF4_MASK, VSOXEI64_V }, // 8568 |
| 29839 | { PseudoVSOXEI64_V_M1_MF8, VSOXEI64_V }, // 8569 |
| 29840 | { PseudoVSOXEI64_V_M1_MF8_MASK, VSOXEI64_V }, // 8570 |
| 29841 | { PseudoVSOXEI64_V_M2_M1, VSOXEI64_V }, // 8571 |
| 29842 | { PseudoVSOXEI64_V_M2_M1_MASK, VSOXEI64_V }, // 8572 |
| 29843 | { PseudoVSOXEI64_V_M2_M2, VSOXEI64_V }, // 8573 |
| 29844 | { PseudoVSOXEI64_V_M2_M2_MASK, VSOXEI64_V }, // 8574 |
| 29845 | { PseudoVSOXEI64_V_M2_MF2, VSOXEI64_V }, // 8575 |
| 29846 | { PseudoVSOXEI64_V_M2_MF2_MASK, VSOXEI64_V }, // 8576 |
| 29847 | { PseudoVSOXEI64_V_M2_MF4, VSOXEI64_V }, // 8577 |
| 29848 | { PseudoVSOXEI64_V_M2_MF4_MASK, VSOXEI64_V }, // 8578 |
| 29849 | { PseudoVSOXEI64_V_M4_M1, VSOXEI64_V }, // 8579 |
| 29850 | { PseudoVSOXEI64_V_M4_M1_MASK, VSOXEI64_V }, // 8580 |
| 29851 | { PseudoVSOXEI64_V_M4_M2, VSOXEI64_V }, // 8581 |
| 29852 | { PseudoVSOXEI64_V_M4_M2_MASK, VSOXEI64_V }, // 8582 |
| 29853 | { PseudoVSOXEI64_V_M4_M4, VSOXEI64_V }, // 8583 |
| 29854 | { PseudoVSOXEI64_V_M4_M4_MASK, VSOXEI64_V }, // 8584 |
| 29855 | { PseudoVSOXEI64_V_M4_MF2, VSOXEI64_V }, // 8585 |
| 29856 | { PseudoVSOXEI64_V_M4_MF2_MASK, VSOXEI64_V }, // 8586 |
| 29857 | { PseudoVSOXEI64_V_M8_M1, VSOXEI64_V }, // 8587 |
| 29858 | { PseudoVSOXEI64_V_M8_M1_MASK, VSOXEI64_V }, // 8588 |
| 29859 | { PseudoVSOXEI64_V_M8_M2, VSOXEI64_V }, // 8589 |
| 29860 | { PseudoVSOXEI64_V_M8_M2_MASK, VSOXEI64_V }, // 8590 |
| 29861 | { PseudoVSOXEI64_V_M8_M4, VSOXEI64_V }, // 8591 |
| 29862 | { PseudoVSOXEI64_V_M8_M4_MASK, VSOXEI64_V }, // 8592 |
| 29863 | { PseudoVSOXEI64_V_M8_M8, VSOXEI64_V }, // 8593 |
| 29864 | { PseudoVSOXEI64_V_M8_M8_MASK, VSOXEI64_V }, // 8594 |
| 29865 | { PseudoVSOXEI8_V_M1_M1, VSOXEI8_V }, // 8595 |
| 29866 | { PseudoVSOXEI8_V_M1_M1_MASK, VSOXEI8_V }, // 8596 |
| 29867 | { PseudoVSOXEI8_V_M1_M2, VSOXEI8_V }, // 8597 |
| 29868 | { PseudoVSOXEI8_V_M1_M2_MASK, VSOXEI8_V }, // 8598 |
| 29869 | { PseudoVSOXEI8_V_M1_M4, VSOXEI8_V }, // 8599 |
| 29870 | { PseudoVSOXEI8_V_M1_M4_MASK, VSOXEI8_V }, // 8600 |
| 29871 | { PseudoVSOXEI8_V_M1_M8, VSOXEI8_V }, // 8601 |
| 29872 | { PseudoVSOXEI8_V_M1_M8_MASK, VSOXEI8_V }, // 8602 |
| 29873 | { PseudoVSOXEI8_V_M2_M2, VSOXEI8_V }, // 8603 |
| 29874 | { PseudoVSOXEI8_V_M2_M2_MASK, VSOXEI8_V }, // 8604 |
| 29875 | { PseudoVSOXEI8_V_M2_M4, VSOXEI8_V }, // 8605 |
| 29876 | { PseudoVSOXEI8_V_M2_M4_MASK, VSOXEI8_V }, // 8606 |
| 29877 | { PseudoVSOXEI8_V_M2_M8, VSOXEI8_V }, // 8607 |
| 29878 | { PseudoVSOXEI8_V_M2_M8_MASK, VSOXEI8_V }, // 8608 |
| 29879 | { PseudoVSOXEI8_V_M4_M4, VSOXEI8_V }, // 8609 |
| 29880 | { PseudoVSOXEI8_V_M4_M4_MASK, VSOXEI8_V }, // 8610 |
| 29881 | { PseudoVSOXEI8_V_M4_M8, VSOXEI8_V }, // 8611 |
| 29882 | { PseudoVSOXEI8_V_M4_M8_MASK, VSOXEI8_V }, // 8612 |
| 29883 | { PseudoVSOXEI8_V_M8_M8, VSOXEI8_V }, // 8613 |
| 29884 | { PseudoVSOXEI8_V_M8_M8_MASK, VSOXEI8_V }, // 8614 |
| 29885 | { PseudoVSOXEI8_V_MF2_M1, VSOXEI8_V }, // 8615 |
| 29886 | { PseudoVSOXEI8_V_MF2_M1_MASK, VSOXEI8_V }, // 8616 |
| 29887 | { PseudoVSOXEI8_V_MF2_M2, VSOXEI8_V }, // 8617 |
| 29888 | { PseudoVSOXEI8_V_MF2_M2_MASK, VSOXEI8_V }, // 8618 |
| 29889 | { PseudoVSOXEI8_V_MF2_M4, VSOXEI8_V }, // 8619 |
| 29890 | { PseudoVSOXEI8_V_MF2_M4_MASK, VSOXEI8_V }, // 8620 |
| 29891 | { PseudoVSOXEI8_V_MF2_MF2, VSOXEI8_V }, // 8621 |
| 29892 | { PseudoVSOXEI8_V_MF2_MF2_MASK, VSOXEI8_V }, // 8622 |
| 29893 | { PseudoVSOXEI8_V_MF4_M1, VSOXEI8_V }, // 8623 |
| 29894 | { PseudoVSOXEI8_V_MF4_M1_MASK, VSOXEI8_V }, // 8624 |
| 29895 | { PseudoVSOXEI8_V_MF4_M2, VSOXEI8_V }, // 8625 |
| 29896 | { PseudoVSOXEI8_V_MF4_M2_MASK, VSOXEI8_V }, // 8626 |
| 29897 | { PseudoVSOXEI8_V_MF4_MF2, VSOXEI8_V }, // 8627 |
| 29898 | { PseudoVSOXEI8_V_MF4_MF2_MASK, VSOXEI8_V }, // 8628 |
| 29899 | { PseudoVSOXEI8_V_MF4_MF4, VSOXEI8_V }, // 8629 |
| 29900 | { PseudoVSOXEI8_V_MF4_MF4_MASK, VSOXEI8_V }, // 8630 |
| 29901 | { PseudoVSOXEI8_V_MF8_M1, VSOXEI8_V }, // 8631 |
| 29902 | { PseudoVSOXEI8_V_MF8_M1_MASK, VSOXEI8_V }, // 8632 |
| 29903 | { PseudoVSOXEI8_V_MF8_MF2, VSOXEI8_V }, // 8633 |
| 29904 | { PseudoVSOXEI8_V_MF8_MF2_MASK, VSOXEI8_V }, // 8634 |
| 29905 | { PseudoVSOXEI8_V_MF8_MF4, VSOXEI8_V }, // 8635 |
| 29906 | { PseudoVSOXEI8_V_MF8_MF4_MASK, VSOXEI8_V }, // 8636 |
| 29907 | { PseudoVSOXEI8_V_MF8_MF8, VSOXEI8_V }, // 8637 |
| 29908 | { PseudoVSOXEI8_V_MF8_MF8_MASK, VSOXEI8_V }, // 8638 |
| 29909 | { PseudoVSOXSEG2EI16_V_M1_M1, VSOXSEG2EI16_V }, // 8639 |
| 29910 | { PseudoVSOXSEG2EI16_V_M1_M1_MASK, VSOXSEG2EI16_V }, // 8640 |
| 29911 | { PseudoVSOXSEG2EI16_V_M1_M2, VSOXSEG2EI16_V }, // 8641 |
| 29912 | { PseudoVSOXSEG2EI16_V_M1_M2_MASK, VSOXSEG2EI16_V }, // 8642 |
| 29913 | { PseudoVSOXSEG2EI16_V_M1_M4, VSOXSEG2EI16_V }, // 8643 |
| 29914 | { PseudoVSOXSEG2EI16_V_M1_M4_MASK, VSOXSEG2EI16_V }, // 8644 |
| 29915 | { PseudoVSOXSEG2EI16_V_M1_MF2, VSOXSEG2EI16_V }, // 8645 |
| 29916 | { PseudoVSOXSEG2EI16_V_M1_MF2_MASK, VSOXSEG2EI16_V }, // 8646 |
| 29917 | { PseudoVSOXSEG2EI16_V_M2_M1, VSOXSEG2EI16_V }, // 8647 |
| 29918 | { PseudoVSOXSEG2EI16_V_M2_M1_MASK, VSOXSEG2EI16_V }, // 8648 |
| 29919 | { PseudoVSOXSEG2EI16_V_M2_M2, VSOXSEG2EI16_V }, // 8649 |
| 29920 | { PseudoVSOXSEG2EI16_V_M2_M2_MASK, VSOXSEG2EI16_V }, // 8650 |
| 29921 | { PseudoVSOXSEG2EI16_V_M2_M4, VSOXSEG2EI16_V }, // 8651 |
| 29922 | { PseudoVSOXSEG2EI16_V_M2_M4_MASK, VSOXSEG2EI16_V }, // 8652 |
| 29923 | { PseudoVSOXSEG2EI16_V_M4_M2, VSOXSEG2EI16_V }, // 8653 |
| 29924 | { PseudoVSOXSEG2EI16_V_M4_M2_MASK, VSOXSEG2EI16_V }, // 8654 |
| 29925 | { PseudoVSOXSEG2EI16_V_M4_M4, VSOXSEG2EI16_V }, // 8655 |
| 29926 | { PseudoVSOXSEG2EI16_V_M4_M4_MASK, VSOXSEG2EI16_V }, // 8656 |
| 29927 | { PseudoVSOXSEG2EI16_V_M8_M4, VSOXSEG2EI16_V }, // 8657 |
| 29928 | { PseudoVSOXSEG2EI16_V_M8_M4_MASK, VSOXSEG2EI16_V }, // 8658 |
| 29929 | { PseudoVSOXSEG2EI16_V_MF2_M1, VSOXSEG2EI16_V }, // 8659 |
| 29930 | { PseudoVSOXSEG2EI16_V_MF2_M1_MASK, VSOXSEG2EI16_V }, // 8660 |
| 29931 | { PseudoVSOXSEG2EI16_V_MF2_M2, VSOXSEG2EI16_V }, // 8661 |
| 29932 | { PseudoVSOXSEG2EI16_V_MF2_M2_MASK, VSOXSEG2EI16_V }, // 8662 |
| 29933 | { PseudoVSOXSEG2EI16_V_MF2_MF2, VSOXSEG2EI16_V }, // 8663 |
| 29934 | { PseudoVSOXSEG2EI16_V_MF2_MF2_MASK, VSOXSEG2EI16_V }, // 8664 |
| 29935 | { PseudoVSOXSEG2EI16_V_MF2_MF4, VSOXSEG2EI16_V }, // 8665 |
| 29936 | { PseudoVSOXSEG2EI16_V_MF2_MF4_MASK, VSOXSEG2EI16_V }, // 8666 |
| 29937 | { PseudoVSOXSEG2EI16_V_MF4_M1, VSOXSEG2EI16_V }, // 8667 |
| 29938 | { PseudoVSOXSEG2EI16_V_MF4_M1_MASK, VSOXSEG2EI16_V }, // 8668 |
| 29939 | { PseudoVSOXSEG2EI16_V_MF4_MF2, VSOXSEG2EI16_V }, // 8669 |
| 29940 | { PseudoVSOXSEG2EI16_V_MF4_MF2_MASK, VSOXSEG2EI16_V }, // 8670 |
| 29941 | { PseudoVSOXSEG2EI16_V_MF4_MF4, VSOXSEG2EI16_V }, // 8671 |
| 29942 | { PseudoVSOXSEG2EI16_V_MF4_MF4_MASK, VSOXSEG2EI16_V }, // 8672 |
| 29943 | { PseudoVSOXSEG2EI16_V_MF4_MF8, VSOXSEG2EI16_V }, // 8673 |
| 29944 | { PseudoVSOXSEG2EI16_V_MF4_MF8_MASK, VSOXSEG2EI16_V }, // 8674 |
| 29945 | { PseudoVSOXSEG2EI32_V_M1_M1, VSOXSEG2EI32_V }, // 8675 |
| 29946 | { PseudoVSOXSEG2EI32_V_M1_M1_MASK, VSOXSEG2EI32_V }, // 8676 |
| 29947 | { PseudoVSOXSEG2EI32_V_M1_M2, VSOXSEG2EI32_V }, // 8677 |
| 29948 | { PseudoVSOXSEG2EI32_V_M1_M2_MASK, VSOXSEG2EI32_V }, // 8678 |
| 29949 | { PseudoVSOXSEG2EI32_V_M1_MF2, VSOXSEG2EI32_V }, // 8679 |
| 29950 | { PseudoVSOXSEG2EI32_V_M1_MF2_MASK, VSOXSEG2EI32_V }, // 8680 |
| 29951 | { PseudoVSOXSEG2EI32_V_M1_MF4, VSOXSEG2EI32_V }, // 8681 |
| 29952 | { PseudoVSOXSEG2EI32_V_M1_MF4_MASK, VSOXSEG2EI32_V }, // 8682 |
| 29953 | { PseudoVSOXSEG2EI32_V_M2_M1, VSOXSEG2EI32_V }, // 8683 |
| 29954 | { PseudoVSOXSEG2EI32_V_M2_M1_MASK, VSOXSEG2EI32_V }, // 8684 |
| 29955 | { PseudoVSOXSEG2EI32_V_M2_M2, VSOXSEG2EI32_V }, // 8685 |
| 29956 | { PseudoVSOXSEG2EI32_V_M2_M2_MASK, VSOXSEG2EI32_V }, // 8686 |
| 29957 | { PseudoVSOXSEG2EI32_V_M2_M4, VSOXSEG2EI32_V }, // 8687 |
| 29958 | { PseudoVSOXSEG2EI32_V_M2_M4_MASK, VSOXSEG2EI32_V }, // 8688 |
| 29959 | { PseudoVSOXSEG2EI32_V_M2_MF2, VSOXSEG2EI32_V }, // 8689 |
| 29960 | { PseudoVSOXSEG2EI32_V_M2_MF2_MASK, VSOXSEG2EI32_V }, // 8690 |
| 29961 | { PseudoVSOXSEG2EI32_V_M4_M1, VSOXSEG2EI32_V }, // 8691 |
| 29962 | { PseudoVSOXSEG2EI32_V_M4_M1_MASK, VSOXSEG2EI32_V }, // 8692 |
| 29963 | { PseudoVSOXSEG2EI32_V_M4_M2, VSOXSEG2EI32_V }, // 8693 |
| 29964 | { PseudoVSOXSEG2EI32_V_M4_M2_MASK, VSOXSEG2EI32_V }, // 8694 |
| 29965 | { PseudoVSOXSEG2EI32_V_M4_M4, VSOXSEG2EI32_V }, // 8695 |
| 29966 | { PseudoVSOXSEG2EI32_V_M4_M4_MASK, VSOXSEG2EI32_V }, // 8696 |
| 29967 | { PseudoVSOXSEG2EI32_V_M8_M2, VSOXSEG2EI32_V }, // 8697 |
| 29968 | { PseudoVSOXSEG2EI32_V_M8_M2_MASK, VSOXSEG2EI32_V }, // 8698 |
| 29969 | { PseudoVSOXSEG2EI32_V_M8_M4, VSOXSEG2EI32_V }, // 8699 |
| 29970 | { PseudoVSOXSEG2EI32_V_M8_M4_MASK, VSOXSEG2EI32_V }, // 8700 |
| 29971 | { PseudoVSOXSEG2EI32_V_MF2_M1, VSOXSEG2EI32_V }, // 8701 |
| 29972 | { PseudoVSOXSEG2EI32_V_MF2_M1_MASK, VSOXSEG2EI32_V }, // 8702 |
| 29973 | { PseudoVSOXSEG2EI32_V_MF2_MF2, VSOXSEG2EI32_V }, // 8703 |
| 29974 | { PseudoVSOXSEG2EI32_V_MF2_MF2_MASK, VSOXSEG2EI32_V }, // 8704 |
| 29975 | { PseudoVSOXSEG2EI32_V_MF2_MF4, VSOXSEG2EI32_V }, // 8705 |
| 29976 | { PseudoVSOXSEG2EI32_V_MF2_MF4_MASK, VSOXSEG2EI32_V }, // 8706 |
| 29977 | { PseudoVSOXSEG2EI32_V_MF2_MF8, VSOXSEG2EI32_V }, // 8707 |
| 29978 | { PseudoVSOXSEG2EI32_V_MF2_MF8_MASK, VSOXSEG2EI32_V }, // 8708 |
| 29979 | { PseudoVSOXSEG2EI64_V_M1_M1, VSOXSEG2EI64_V }, // 8709 |
| 29980 | { PseudoVSOXSEG2EI64_V_M1_M1_MASK, VSOXSEG2EI64_V }, // 8710 |
| 29981 | { PseudoVSOXSEG2EI64_V_M1_MF2, VSOXSEG2EI64_V }, // 8711 |
| 29982 | { PseudoVSOXSEG2EI64_V_M1_MF2_MASK, VSOXSEG2EI64_V }, // 8712 |
| 29983 | { PseudoVSOXSEG2EI64_V_M1_MF4, VSOXSEG2EI64_V }, // 8713 |
| 29984 | { PseudoVSOXSEG2EI64_V_M1_MF4_MASK, VSOXSEG2EI64_V }, // 8714 |
| 29985 | { PseudoVSOXSEG2EI64_V_M1_MF8, VSOXSEG2EI64_V }, // 8715 |
| 29986 | { PseudoVSOXSEG2EI64_V_M1_MF8_MASK, VSOXSEG2EI64_V }, // 8716 |
| 29987 | { PseudoVSOXSEG2EI64_V_M2_M1, VSOXSEG2EI64_V }, // 8717 |
| 29988 | { PseudoVSOXSEG2EI64_V_M2_M1_MASK, VSOXSEG2EI64_V }, // 8718 |
| 29989 | { PseudoVSOXSEG2EI64_V_M2_M2, VSOXSEG2EI64_V }, // 8719 |
| 29990 | { PseudoVSOXSEG2EI64_V_M2_M2_MASK, VSOXSEG2EI64_V }, // 8720 |
| 29991 | { PseudoVSOXSEG2EI64_V_M2_MF2, VSOXSEG2EI64_V }, // 8721 |
| 29992 | { PseudoVSOXSEG2EI64_V_M2_MF2_MASK, VSOXSEG2EI64_V }, // 8722 |
| 29993 | { PseudoVSOXSEG2EI64_V_M2_MF4, VSOXSEG2EI64_V }, // 8723 |
| 29994 | { PseudoVSOXSEG2EI64_V_M2_MF4_MASK, VSOXSEG2EI64_V }, // 8724 |
| 29995 | { PseudoVSOXSEG2EI64_V_M4_M1, VSOXSEG2EI64_V }, // 8725 |
| 29996 | { PseudoVSOXSEG2EI64_V_M4_M1_MASK, VSOXSEG2EI64_V }, // 8726 |
| 29997 | { PseudoVSOXSEG2EI64_V_M4_M2, VSOXSEG2EI64_V }, // 8727 |
| 29998 | { PseudoVSOXSEG2EI64_V_M4_M2_MASK, VSOXSEG2EI64_V }, // 8728 |
| 29999 | { PseudoVSOXSEG2EI64_V_M4_M4, VSOXSEG2EI64_V }, // 8729 |
| 30000 | { PseudoVSOXSEG2EI64_V_M4_M4_MASK, VSOXSEG2EI64_V }, // 8730 |
| 30001 | { PseudoVSOXSEG2EI64_V_M4_MF2, VSOXSEG2EI64_V }, // 8731 |
| 30002 | { PseudoVSOXSEG2EI64_V_M4_MF2_MASK, VSOXSEG2EI64_V }, // 8732 |
| 30003 | { PseudoVSOXSEG2EI64_V_M8_M1, VSOXSEG2EI64_V }, // 8733 |
| 30004 | { PseudoVSOXSEG2EI64_V_M8_M1_MASK, VSOXSEG2EI64_V }, // 8734 |
| 30005 | { PseudoVSOXSEG2EI64_V_M8_M2, VSOXSEG2EI64_V }, // 8735 |
| 30006 | { PseudoVSOXSEG2EI64_V_M8_M2_MASK, VSOXSEG2EI64_V }, // 8736 |
| 30007 | { PseudoVSOXSEG2EI64_V_M8_M4, VSOXSEG2EI64_V }, // 8737 |
| 30008 | { PseudoVSOXSEG2EI64_V_M8_M4_MASK, VSOXSEG2EI64_V }, // 8738 |
| 30009 | { PseudoVSOXSEG2EI8_V_M1_M1, VSOXSEG2EI8_V }, // 8739 |
| 30010 | { PseudoVSOXSEG2EI8_V_M1_M1_MASK, VSOXSEG2EI8_V }, // 8740 |
| 30011 | { PseudoVSOXSEG2EI8_V_M1_M2, VSOXSEG2EI8_V }, // 8741 |
| 30012 | { PseudoVSOXSEG2EI8_V_M1_M2_MASK, VSOXSEG2EI8_V }, // 8742 |
| 30013 | { PseudoVSOXSEG2EI8_V_M1_M4, VSOXSEG2EI8_V }, // 8743 |
| 30014 | { PseudoVSOXSEG2EI8_V_M1_M4_MASK, VSOXSEG2EI8_V }, // 8744 |
| 30015 | { PseudoVSOXSEG2EI8_V_M2_M2, VSOXSEG2EI8_V }, // 8745 |
| 30016 | { PseudoVSOXSEG2EI8_V_M2_M2_MASK, VSOXSEG2EI8_V }, // 8746 |
| 30017 | { PseudoVSOXSEG2EI8_V_M2_M4, VSOXSEG2EI8_V }, // 8747 |
| 30018 | { PseudoVSOXSEG2EI8_V_M2_M4_MASK, VSOXSEG2EI8_V }, // 8748 |
| 30019 | { PseudoVSOXSEG2EI8_V_M4_M4, VSOXSEG2EI8_V }, // 8749 |
| 30020 | { PseudoVSOXSEG2EI8_V_M4_M4_MASK, VSOXSEG2EI8_V }, // 8750 |
| 30021 | { PseudoVSOXSEG2EI8_V_MF2_M1, VSOXSEG2EI8_V }, // 8751 |
| 30022 | { PseudoVSOXSEG2EI8_V_MF2_M1_MASK, VSOXSEG2EI8_V }, // 8752 |
| 30023 | { PseudoVSOXSEG2EI8_V_MF2_M2, VSOXSEG2EI8_V }, // 8753 |
| 30024 | { PseudoVSOXSEG2EI8_V_MF2_M2_MASK, VSOXSEG2EI8_V }, // 8754 |
| 30025 | { PseudoVSOXSEG2EI8_V_MF2_M4, VSOXSEG2EI8_V }, // 8755 |
| 30026 | { PseudoVSOXSEG2EI8_V_MF2_M4_MASK, VSOXSEG2EI8_V }, // 8756 |
| 30027 | { PseudoVSOXSEG2EI8_V_MF2_MF2, VSOXSEG2EI8_V }, // 8757 |
| 30028 | { PseudoVSOXSEG2EI8_V_MF2_MF2_MASK, VSOXSEG2EI8_V }, // 8758 |
| 30029 | { PseudoVSOXSEG2EI8_V_MF4_M1, VSOXSEG2EI8_V }, // 8759 |
| 30030 | { PseudoVSOXSEG2EI8_V_MF4_M1_MASK, VSOXSEG2EI8_V }, // 8760 |
| 30031 | { PseudoVSOXSEG2EI8_V_MF4_M2, VSOXSEG2EI8_V }, // 8761 |
| 30032 | { PseudoVSOXSEG2EI8_V_MF4_M2_MASK, VSOXSEG2EI8_V }, // 8762 |
| 30033 | { PseudoVSOXSEG2EI8_V_MF4_MF2, VSOXSEG2EI8_V }, // 8763 |
| 30034 | { PseudoVSOXSEG2EI8_V_MF4_MF2_MASK, VSOXSEG2EI8_V }, // 8764 |
| 30035 | { PseudoVSOXSEG2EI8_V_MF4_MF4, VSOXSEG2EI8_V }, // 8765 |
| 30036 | { PseudoVSOXSEG2EI8_V_MF4_MF4_MASK, VSOXSEG2EI8_V }, // 8766 |
| 30037 | { PseudoVSOXSEG2EI8_V_MF8_M1, VSOXSEG2EI8_V }, // 8767 |
| 30038 | { PseudoVSOXSEG2EI8_V_MF8_M1_MASK, VSOXSEG2EI8_V }, // 8768 |
| 30039 | { PseudoVSOXSEG2EI8_V_MF8_MF2, VSOXSEG2EI8_V }, // 8769 |
| 30040 | { PseudoVSOXSEG2EI8_V_MF8_MF2_MASK, VSOXSEG2EI8_V }, // 8770 |
| 30041 | { PseudoVSOXSEG2EI8_V_MF8_MF4, VSOXSEG2EI8_V }, // 8771 |
| 30042 | { PseudoVSOXSEG2EI8_V_MF8_MF4_MASK, VSOXSEG2EI8_V }, // 8772 |
| 30043 | { PseudoVSOXSEG2EI8_V_MF8_MF8, VSOXSEG2EI8_V }, // 8773 |
| 30044 | { PseudoVSOXSEG2EI8_V_MF8_MF8_MASK, VSOXSEG2EI8_V }, // 8774 |
| 30045 | { PseudoVSOXSEG3EI16_V_M1_M1, VSOXSEG3EI16_V }, // 8775 |
| 30046 | { PseudoVSOXSEG3EI16_V_M1_M1_MASK, VSOXSEG3EI16_V }, // 8776 |
| 30047 | { PseudoVSOXSEG3EI16_V_M1_M2, VSOXSEG3EI16_V }, // 8777 |
| 30048 | { PseudoVSOXSEG3EI16_V_M1_M2_MASK, VSOXSEG3EI16_V }, // 8778 |
| 30049 | { PseudoVSOXSEG3EI16_V_M1_MF2, VSOXSEG3EI16_V }, // 8779 |
| 30050 | { PseudoVSOXSEG3EI16_V_M1_MF2_MASK, VSOXSEG3EI16_V }, // 8780 |
| 30051 | { PseudoVSOXSEG3EI16_V_M2_M1, VSOXSEG3EI16_V }, // 8781 |
| 30052 | { PseudoVSOXSEG3EI16_V_M2_M1_MASK, VSOXSEG3EI16_V }, // 8782 |
| 30053 | { PseudoVSOXSEG3EI16_V_M2_M2, VSOXSEG3EI16_V }, // 8783 |
| 30054 | { PseudoVSOXSEG3EI16_V_M2_M2_MASK, VSOXSEG3EI16_V }, // 8784 |
| 30055 | { PseudoVSOXSEG3EI16_V_M4_M2, VSOXSEG3EI16_V }, // 8785 |
| 30056 | { PseudoVSOXSEG3EI16_V_M4_M2_MASK, VSOXSEG3EI16_V }, // 8786 |
| 30057 | { PseudoVSOXSEG3EI16_V_MF2_M1, VSOXSEG3EI16_V }, // 8787 |
| 30058 | { PseudoVSOXSEG3EI16_V_MF2_M1_MASK, VSOXSEG3EI16_V }, // 8788 |
| 30059 | { PseudoVSOXSEG3EI16_V_MF2_M2, VSOXSEG3EI16_V }, // 8789 |
| 30060 | { PseudoVSOXSEG3EI16_V_MF2_M2_MASK, VSOXSEG3EI16_V }, // 8790 |
| 30061 | { PseudoVSOXSEG3EI16_V_MF2_MF2, VSOXSEG3EI16_V }, // 8791 |
| 30062 | { PseudoVSOXSEG3EI16_V_MF2_MF2_MASK, VSOXSEG3EI16_V }, // 8792 |
| 30063 | { PseudoVSOXSEG3EI16_V_MF2_MF4, VSOXSEG3EI16_V }, // 8793 |
| 30064 | { PseudoVSOXSEG3EI16_V_MF2_MF4_MASK, VSOXSEG3EI16_V }, // 8794 |
| 30065 | { PseudoVSOXSEG3EI16_V_MF4_M1, VSOXSEG3EI16_V }, // 8795 |
| 30066 | { PseudoVSOXSEG3EI16_V_MF4_M1_MASK, VSOXSEG3EI16_V }, // 8796 |
| 30067 | { PseudoVSOXSEG3EI16_V_MF4_MF2, VSOXSEG3EI16_V }, // 8797 |
| 30068 | { PseudoVSOXSEG3EI16_V_MF4_MF2_MASK, VSOXSEG3EI16_V }, // 8798 |
| 30069 | { PseudoVSOXSEG3EI16_V_MF4_MF4, VSOXSEG3EI16_V }, // 8799 |
| 30070 | { PseudoVSOXSEG3EI16_V_MF4_MF4_MASK, VSOXSEG3EI16_V }, // 8800 |
| 30071 | { PseudoVSOXSEG3EI16_V_MF4_MF8, VSOXSEG3EI16_V }, // 8801 |
| 30072 | { PseudoVSOXSEG3EI16_V_MF4_MF8_MASK, VSOXSEG3EI16_V }, // 8802 |
| 30073 | { PseudoVSOXSEG3EI32_V_M1_M1, VSOXSEG3EI32_V }, // 8803 |
| 30074 | { PseudoVSOXSEG3EI32_V_M1_M1_MASK, VSOXSEG3EI32_V }, // 8804 |
| 30075 | { PseudoVSOXSEG3EI32_V_M1_M2, VSOXSEG3EI32_V }, // 8805 |
| 30076 | { PseudoVSOXSEG3EI32_V_M1_M2_MASK, VSOXSEG3EI32_V }, // 8806 |
| 30077 | { PseudoVSOXSEG3EI32_V_M1_MF2, VSOXSEG3EI32_V }, // 8807 |
| 30078 | { PseudoVSOXSEG3EI32_V_M1_MF2_MASK, VSOXSEG3EI32_V }, // 8808 |
| 30079 | { PseudoVSOXSEG3EI32_V_M1_MF4, VSOXSEG3EI32_V }, // 8809 |
| 30080 | { PseudoVSOXSEG3EI32_V_M1_MF4_MASK, VSOXSEG3EI32_V }, // 8810 |
| 30081 | { PseudoVSOXSEG3EI32_V_M2_M1, VSOXSEG3EI32_V }, // 8811 |
| 30082 | { PseudoVSOXSEG3EI32_V_M2_M1_MASK, VSOXSEG3EI32_V }, // 8812 |
| 30083 | { PseudoVSOXSEG3EI32_V_M2_M2, VSOXSEG3EI32_V }, // 8813 |
| 30084 | { PseudoVSOXSEG3EI32_V_M2_M2_MASK, VSOXSEG3EI32_V }, // 8814 |
| 30085 | { PseudoVSOXSEG3EI32_V_M2_MF2, VSOXSEG3EI32_V }, // 8815 |
| 30086 | { PseudoVSOXSEG3EI32_V_M2_MF2_MASK, VSOXSEG3EI32_V }, // 8816 |
| 30087 | { PseudoVSOXSEG3EI32_V_M4_M1, VSOXSEG3EI32_V }, // 8817 |
| 30088 | { PseudoVSOXSEG3EI32_V_M4_M1_MASK, VSOXSEG3EI32_V }, // 8818 |
| 30089 | { PseudoVSOXSEG3EI32_V_M4_M2, VSOXSEG3EI32_V }, // 8819 |
| 30090 | { PseudoVSOXSEG3EI32_V_M4_M2_MASK, VSOXSEG3EI32_V }, // 8820 |
| 30091 | { PseudoVSOXSEG3EI32_V_M8_M2, VSOXSEG3EI32_V }, // 8821 |
| 30092 | { PseudoVSOXSEG3EI32_V_M8_M2_MASK, VSOXSEG3EI32_V }, // 8822 |
| 30093 | { PseudoVSOXSEG3EI32_V_MF2_M1, VSOXSEG3EI32_V }, // 8823 |
| 30094 | { PseudoVSOXSEG3EI32_V_MF2_M1_MASK, VSOXSEG3EI32_V }, // 8824 |
| 30095 | { PseudoVSOXSEG3EI32_V_MF2_MF2, VSOXSEG3EI32_V }, // 8825 |
| 30096 | { PseudoVSOXSEG3EI32_V_MF2_MF2_MASK, VSOXSEG3EI32_V }, // 8826 |
| 30097 | { PseudoVSOXSEG3EI32_V_MF2_MF4, VSOXSEG3EI32_V }, // 8827 |
| 30098 | { PseudoVSOXSEG3EI32_V_MF2_MF4_MASK, VSOXSEG3EI32_V }, // 8828 |
| 30099 | { PseudoVSOXSEG3EI32_V_MF2_MF8, VSOXSEG3EI32_V }, // 8829 |
| 30100 | { PseudoVSOXSEG3EI32_V_MF2_MF8_MASK, VSOXSEG3EI32_V }, // 8830 |
| 30101 | { PseudoVSOXSEG3EI64_V_M1_M1, VSOXSEG3EI64_V }, // 8831 |
| 30102 | { PseudoVSOXSEG3EI64_V_M1_M1_MASK, VSOXSEG3EI64_V }, // 8832 |
| 30103 | { PseudoVSOXSEG3EI64_V_M1_MF2, VSOXSEG3EI64_V }, // 8833 |
| 30104 | { PseudoVSOXSEG3EI64_V_M1_MF2_MASK, VSOXSEG3EI64_V }, // 8834 |
| 30105 | { PseudoVSOXSEG3EI64_V_M1_MF4, VSOXSEG3EI64_V }, // 8835 |
| 30106 | { PseudoVSOXSEG3EI64_V_M1_MF4_MASK, VSOXSEG3EI64_V }, // 8836 |
| 30107 | { PseudoVSOXSEG3EI64_V_M1_MF8, VSOXSEG3EI64_V }, // 8837 |
| 30108 | { PseudoVSOXSEG3EI64_V_M1_MF8_MASK, VSOXSEG3EI64_V }, // 8838 |
| 30109 | { PseudoVSOXSEG3EI64_V_M2_M1, VSOXSEG3EI64_V }, // 8839 |
| 30110 | { PseudoVSOXSEG3EI64_V_M2_M1_MASK, VSOXSEG3EI64_V }, // 8840 |
| 30111 | { PseudoVSOXSEG3EI64_V_M2_M2, VSOXSEG3EI64_V }, // 8841 |
| 30112 | { PseudoVSOXSEG3EI64_V_M2_M2_MASK, VSOXSEG3EI64_V }, // 8842 |
| 30113 | { PseudoVSOXSEG3EI64_V_M2_MF2, VSOXSEG3EI64_V }, // 8843 |
| 30114 | { PseudoVSOXSEG3EI64_V_M2_MF2_MASK, VSOXSEG3EI64_V }, // 8844 |
| 30115 | { PseudoVSOXSEG3EI64_V_M2_MF4, VSOXSEG3EI64_V }, // 8845 |
| 30116 | { PseudoVSOXSEG3EI64_V_M2_MF4_MASK, VSOXSEG3EI64_V }, // 8846 |
| 30117 | { PseudoVSOXSEG3EI64_V_M4_M1, VSOXSEG3EI64_V }, // 8847 |
| 30118 | { PseudoVSOXSEG3EI64_V_M4_M1_MASK, VSOXSEG3EI64_V }, // 8848 |
| 30119 | { PseudoVSOXSEG3EI64_V_M4_M2, VSOXSEG3EI64_V }, // 8849 |
| 30120 | { PseudoVSOXSEG3EI64_V_M4_M2_MASK, VSOXSEG3EI64_V }, // 8850 |
| 30121 | { PseudoVSOXSEG3EI64_V_M4_MF2, VSOXSEG3EI64_V }, // 8851 |
| 30122 | { PseudoVSOXSEG3EI64_V_M4_MF2_MASK, VSOXSEG3EI64_V }, // 8852 |
| 30123 | { PseudoVSOXSEG3EI64_V_M8_M1, VSOXSEG3EI64_V }, // 8853 |
| 30124 | { PseudoVSOXSEG3EI64_V_M8_M1_MASK, VSOXSEG3EI64_V }, // 8854 |
| 30125 | { PseudoVSOXSEG3EI64_V_M8_M2, VSOXSEG3EI64_V }, // 8855 |
| 30126 | { PseudoVSOXSEG3EI64_V_M8_M2_MASK, VSOXSEG3EI64_V }, // 8856 |
| 30127 | { PseudoVSOXSEG3EI8_V_M1_M1, VSOXSEG3EI8_V }, // 8857 |
| 30128 | { PseudoVSOXSEG3EI8_V_M1_M1_MASK, VSOXSEG3EI8_V }, // 8858 |
| 30129 | { PseudoVSOXSEG3EI8_V_M1_M2, VSOXSEG3EI8_V }, // 8859 |
| 30130 | { PseudoVSOXSEG3EI8_V_M1_M2_MASK, VSOXSEG3EI8_V }, // 8860 |
| 30131 | { PseudoVSOXSEG3EI8_V_M2_M2, VSOXSEG3EI8_V }, // 8861 |
| 30132 | { PseudoVSOXSEG3EI8_V_M2_M2_MASK, VSOXSEG3EI8_V }, // 8862 |
| 30133 | { PseudoVSOXSEG3EI8_V_MF2_M1, VSOXSEG3EI8_V }, // 8863 |
| 30134 | { PseudoVSOXSEG3EI8_V_MF2_M1_MASK, VSOXSEG3EI8_V }, // 8864 |
| 30135 | { PseudoVSOXSEG3EI8_V_MF2_M2, VSOXSEG3EI8_V }, // 8865 |
| 30136 | { PseudoVSOXSEG3EI8_V_MF2_M2_MASK, VSOXSEG3EI8_V }, // 8866 |
| 30137 | { PseudoVSOXSEG3EI8_V_MF2_MF2, VSOXSEG3EI8_V }, // 8867 |
| 30138 | { PseudoVSOXSEG3EI8_V_MF2_MF2_MASK, VSOXSEG3EI8_V }, // 8868 |
| 30139 | { PseudoVSOXSEG3EI8_V_MF4_M1, VSOXSEG3EI8_V }, // 8869 |
| 30140 | { PseudoVSOXSEG3EI8_V_MF4_M1_MASK, VSOXSEG3EI8_V }, // 8870 |
| 30141 | { PseudoVSOXSEG3EI8_V_MF4_M2, VSOXSEG3EI8_V }, // 8871 |
| 30142 | { PseudoVSOXSEG3EI8_V_MF4_M2_MASK, VSOXSEG3EI8_V }, // 8872 |
| 30143 | { PseudoVSOXSEG3EI8_V_MF4_MF2, VSOXSEG3EI8_V }, // 8873 |
| 30144 | { PseudoVSOXSEG3EI8_V_MF4_MF2_MASK, VSOXSEG3EI8_V }, // 8874 |
| 30145 | { PseudoVSOXSEG3EI8_V_MF4_MF4, VSOXSEG3EI8_V }, // 8875 |
| 30146 | { PseudoVSOXSEG3EI8_V_MF4_MF4_MASK, VSOXSEG3EI8_V }, // 8876 |
| 30147 | { PseudoVSOXSEG3EI8_V_MF8_M1, VSOXSEG3EI8_V }, // 8877 |
| 30148 | { PseudoVSOXSEG3EI8_V_MF8_M1_MASK, VSOXSEG3EI8_V }, // 8878 |
| 30149 | { PseudoVSOXSEG3EI8_V_MF8_MF2, VSOXSEG3EI8_V }, // 8879 |
| 30150 | { PseudoVSOXSEG3EI8_V_MF8_MF2_MASK, VSOXSEG3EI8_V }, // 8880 |
| 30151 | { PseudoVSOXSEG3EI8_V_MF8_MF4, VSOXSEG3EI8_V }, // 8881 |
| 30152 | { PseudoVSOXSEG3EI8_V_MF8_MF4_MASK, VSOXSEG3EI8_V }, // 8882 |
| 30153 | { PseudoVSOXSEG3EI8_V_MF8_MF8, VSOXSEG3EI8_V }, // 8883 |
| 30154 | { PseudoVSOXSEG3EI8_V_MF8_MF8_MASK, VSOXSEG3EI8_V }, // 8884 |
| 30155 | { PseudoVSOXSEG4EI16_V_M1_M1, VSOXSEG4EI16_V }, // 8885 |
| 30156 | { PseudoVSOXSEG4EI16_V_M1_M1_MASK, VSOXSEG4EI16_V }, // 8886 |
| 30157 | { PseudoVSOXSEG4EI16_V_M1_M2, VSOXSEG4EI16_V }, // 8887 |
| 30158 | { PseudoVSOXSEG4EI16_V_M1_M2_MASK, VSOXSEG4EI16_V }, // 8888 |
| 30159 | { PseudoVSOXSEG4EI16_V_M1_MF2, VSOXSEG4EI16_V }, // 8889 |
| 30160 | { PseudoVSOXSEG4EI16_V_M1_MF2_MASK, VSOXSEG4EI16_V }, // 8890 |
| 30161 | { PseudoVSOXSEG4EI16_V_M2_M1, VSOXSEG4EI16_V }, // 8891 |
| 30162 | { PseudoVSOXSEG4EI16_V_M2_M1_MASK, VSOXSEG4EI16_V }, // 8892 |
| 30163 | { PseudoVSOXSEG4EI16_V_M2_M2, VSOXSEG4EI16_V }, // 8893 |
| 30164 | { PseudoVSOXSEG4EI16_V_M2_M2_MASK, VSOXSEG4EI16_V }, // 8894 |
| 30165 | { PseudoVSOXSEG4EI16_V_M4_M2, VSOXSEG4EI16_V }, // 8895 |
| 30166 | { PseudoVSOXSEG4EI16_V_M4_M2_MASK, VSOXSEG4EI16_V }, // 8896 |
| 30167 | { PseudoVSOXSEG4EI16_V_MF2_M1, VSOXSEG4EI16_V }, // 8897 |
| 30168 | { PseudoVSOXSEG4EI16_V_MF2_M1_MASK, VSOXSEG4EI16_V }, // 8898 |
| 30169 | { PseudoVSOXSEG4EI16_V_MF2_M2, VSOXSEG4EI16_V }, // 8899 |
| 30170 | { PseudoVSOXSEG4EI16_V_MF2_M2_MASK, VSOXSEG4EI16_V }, // 8900 |
| 30171 | { PseudoVSOXSEG4EI16_V_MF2_MF2, VSOXSEG4EI16_V }, // 8901 |
| 30172 | { PseudoVSOXSEG4EI16_V_MF2_MF2_MASK, VSOXSEG4EI16_V }, // 8902 |
| 30173 | { PseudoVSOXSEG4EI16_V_MF2_MF4, VSOXSEG4EI16_V }, // 8903 |
| 30174 | { PseudoVSOXSEG4EI16_V_MF2_MF4_MASK, VSOXSEG4EI16_V }, // 8904 |
| 30175 | { PseudoVSOXSEG4EI16_V_MF4_M1, VSOXSEG4EI16_V }, // 8905 |
| 30176 | { PseudoVSOXSEG4EI16_V_MF4_M1_MASK, VSOXSEG4EI16_V }, // 8906 |
| 30177 | { PseudoVSOXSEG4EI16_V_MF4_MF2, VSOXSEG4EI16_V }, // 8907 |
| 30178 | { PseudoVSOXSEG4EI16_V_MF4_MF2_MASK, VSOXSEG4EI16_V }, // 8908 |
| 30179 | { PseudoVSOXSEG4EI16_V_MF4_MF4, VSOXSEG4EI16_V }, // 8909 |
| 30180 | { PseudoVSOXSEG4EI16_V_MF4_MF4_MASK, VSOXSEG4EI16_V }, // 8910 |
| 30181 | { PseudoVSOXSEG4EI16_V_MF4_MF8, VSOXSEG4EI16_V }, // 8911 |
| 30182 | { PseudoVSOXSEG4EI16_V_MF4_MF8_MASK, VSOXSEG4EI16_V }, // 8912 |
| 30183 | { PseudoVSOXSEG4EI32_V_M1_M1, VSOXSEG4EI32_V }, // 8913 |
| 30184 | { PseudoVSOXSEG4EI32_V_M1_M1_MASK, VSOXSEG4EI32_V }, // 8914 |
| 30185 | { PseudoVSOXSEG4EI32_V_M1_M2, VSOXSEG4EI32_V }, // 8915 |
| 30186 | { PseudoVSOXSEG4EI32_V_M1_M2_MASK, VSOXSEG4EI32_V }, // 8916 |
| 30187 | { PseudoVSOXSEG4EI32_V_M1_MF2, VSOXSEG4EI32_V }, // 8917 |
| 30188 | { PseudoVSOXSEG4EI32_V_M1_MF2_MASK, VSOXSEG4EI32_V }, // 8918 |
| 30189 | { PseudoVSOXSEG4EI32_V_M1_MF4, VSOXSEG4EI32_V }, // 8919 |
| 30190 | { PseudoVSOXSEG4EI32_V_M1_MF4_MASK, VSOXSEG4EI32_V }, // 8920 |
| 30191 | { PseudoVSOXSEG4EI32_V_M2_M1, VSOXSEG4EI32_V }, // 8921 |
| 30192 | { PseudoVSOXSEG4EI32_V_M2_M1_MASK, VSOXSEG4EI32_V }, // 8922 |
| 30193 | { PseudoVSOXSEG4EI32_V_M2_M2, VSOXSEG4EI32_V }, // 8923 |
| 30194 | { PseudoVSOXSEG4EI32_V_M2_M2_MASK, VSOXSEG4EI32_V }, // 8924 |
| 30195 | { PseudoVSOXSEG4EI32_V_M2_MF2, VSOXSEG4EI32_V }, // 8925 |
| 30196 | { PseudoVSOXSEG4EI32_V_M2_MF2_MASK, VSOXSEG4EI32_V }, // 8926 |
| 30197 | { PseudoVSOXSEG4EI32_V_M4_M1, VSOXSEG4EI32_V }, // 8927 |
| 30198 | { PseudoVSOXSEG4EI32_V_M4_M1_MASK, VSOXSEG4EI32_V }, // 8928 |
| 30199 | { PseudoVSOXSEG4EI32_V_M4_M2, VSOXSEG4EI32_V }, // 8929 |
| 30200 | { PseudoVSOXSEG4EI32_V_M4_M2_MASK, VSOXSEG4EI32_V }, // 8930 |
| 30201 | { PseudoVSOXSEG4EI32_V_M8_M2, VSOXSEG4EI32_V }, // 8931 |
| 30202 | { PseudoVSOXSEG4EI32_V_M8_M2_MASK, VSOXSEG4EI32_V }, // 8932 |
| 30203 | { PseudoVSOXSEG4EI32_V_MF2_M1, VSOXSEG4EI32_V }, // 8933 |
| 30204 | { PseudoVSOXSEG4EI32_V_MF2_M1_MASK, VSOXSEG4EI32_V }, // 8934 |
| 30205 | { PseudoVSOXSEG4EI32_V_MF2_MF2, VSOXSEG4EI32_V }, // 8935 |
| 30206 | { PseudoVSOXSEG4EI32_V_MF2_MF2_MASK, VSOXSEG4EI32_V }, // 8936 |
| 30207 | { PseudoVSOXSEG4EI32_V_MF2_MF4, VSOXSEG4EI32_V }, // 8937 |
| 30208 | { PseudoVSOXSEG4EI32_V_MF2_MF4_MASK, VSOXSEG4EI32_V }, // 8938 |
| 30209 | { PseudoVSOXSEG4EI32_V_MF2_MF8, VSOXSEG4EI32_V }, // 8939 |
| 30210 | { PseudoVSOXSEG4EI32_V_MF2_MF8_MASK, VSOXSEG4EI32_V }, // 8940 |
| 30211 | { PseudoVSOXSEG4EI64_V_M1_M1, VSOXSEG4EI64_V }, // 8941 |
| 30212 | { PseudoVSOXSEG4EI64_V_M1_M1_MASK, VSOXSEG4EI64_V }, // 8942 |
| 30213 | { PseudoVSOXSEG4EI64_V_M1_MF2, VSOXSEG4EI64_V }, // 8943 |
| 30214 | { PseudoVSOXSEG4EI64_V_M1_MF2_MASK, VSOXSEG4EI64_V }, // 8944 |
| 30215 | { PseudoVSOXSEG4EI64_V_M1_MF4, VSOXSEG4EI64_V }, // 8945 |
| 30216 | { PseudoVSOXSEG4EI64_V_M1_MF4_MASK, VSOXSEG4EI64_V }, // 8946 |
| 30217 | { PseudoVSOXSEG4EI64_V_M1_MF8, VSOXSEG4EI64_V }, // 8947 |
| 30218 | { PseudoVSOXSEG4EI64_V_M1_MF8_MASK, VSOXSEG4EI64_V }, // 8948 |
| 30219 | { PseudoVSOXSEG4EI64_V_M2_M1, VSOXSEG4EI64_V }, // 8949 |
| 30220 | { PseudoVSOXSEG4EI64_V_M2_M1_MASK, VSOXSEG4EI64_V }, // 8950 |
| 30221 | { PseudoVSOXSEG4EI64_V_M2_M2, VSOXSEG4EI64_V }, // 8951 |
| 30222 | { PseudoVSOXSEG4EI64_V_M2_M2_MASK, VSOXSEG4EI64_V }, // 8952 |
| 30223 | { PseudoVSOXSEG4EI64_V_M2_MF2, VSOXSEG4EI64_V }, // 8953 |
| 30224 | { PseudoVSOXSEG4EI64_V_M2_MF2_MASK, VSOXSEG4EI64_V }, // 8954 |
| 30225 | { PseudoVSOXSEG4EI64_V_M2_MF4, VSOXSEG4EI64_V }, // 8955 |
| 30226 | { PseudoVSOXSEG4EI64_V_M2_MF4_MASK, VSOXSEG4EI64_V }, // 8956 |
| 30227 | { PseudoVSOXSEG4EI64_V_M4_M1, VSOXSEG4EI64_V }, // 8957 |
| 30228 | { PseudoVSOXSEG4EI64_V_M4_M1_MASK, VSOXSEG4EI64_V }, // 8958 |
| 30229 | { PseudoVSOXSEG4EI64_V_M4_M2, VSOXSEG4EI64_V }, // 8959 |
| 30230 | { PseudoVSOXSEG4EI64_V_M4_M2_MASK, VSOXSEG4EI64_V }, // 8960 |
| 30231 | { PseudoVSOXSEG4EI64_V_M4_MF2, VSOXSEG4EI64_V }, // 8961 |
| 30232 | { PseudoVSOXSEG4EI64_V_M4_MF2_MASK, VSOXSEG4EI64_V }, // 8962 |
| 30233 | { PseudoVSOXSEG4EI64_V_M8_M1, VSOXSEG4EI64_V }, // 8963 |
| 30234 | { PseudoVSOXSEG4EI64_V_M8_M1_MASK, VSOXSEG4EI64_V }, // 8964 |
| 30235 | { PseudoVSOXSEG4EI64_V_M8_M2, VSOXSEG4EI64_V }, // 8965 |
| 30236 | { PseudoVSOXSEG4EI64_V_M8_M2_MASK, VSOXSEG4EI64_V }, // 8966 |
| 30237 | { PseudoVSOXSEG4EI8_V_M1_M1, VSOXSEG4EI8_V }, // 8967 |
| 30238 | { PseudoVSOXSEG4EI8_V_M1_M1_MASK, VSOXSEG4EI8_V }, // 8968 |
| 30239 | { PseudoVSOXSEG4EI8_V_M1_M2, VSOXSEG4EI8_V }, // 8969 |
| 30240 | { PseudoVSOXSEG4EI8_V_M1_M2_MASK, VSOXSEG4EI8_V }, // 8970 |
| 30241 | { PseudoVSOXSEG4EI8_V_M2_M2, VSOXSEG4EI8_V }, // 8971 |
| 30242 | { PseudoVSOXSEG4EI8_V_M2_M2_MASK, VSOXSEG4EI8_V }, // 8972 |
| 30243 | { PseudoVSOXSEG4EI8_V_MF2_M1, VSOXSEG4EI8_V }, // 8973 |
| 30244 | { PseudoVSOXSEG4EI8_V_MF2_M1_MASK, VSOXSEG4EI8_V }, // 8974 |
| 30245 | { PseudoVSOXSEG4EI8_V_MF2_M2, VSOXSEG4EI8_V }, // 8975 |
| 30246 | { PseudoVSOXSEG4EI8_V_MF2_M2_MASK, VSOXSEG4EI8_V }, // 8976 |
| 30247 | { PseudoVSOXSEG4EI8_V_MF2_MF2, VSOXSEG4EI8_V }, // 8977 |
| 30248 | { PseudoVSOXSEG4EI8_V_MF2_MF2_MASK, VSOXSEG4EI8_V }, // 8978 |
| 30249 | { PseudoVSOXSEG4EI8_V_MF4_M1, VSOXSEG4EI8_V }, // 8979 |
| 30250 | { PseudoVSOXSEG4EI8_V_MF4_M1_MASK, VSOXSEG4EI8_V }, // 8980 |
| 30251 | { PseudoVSOXSEG4EI8_V_MF4_M2, VSOXSEG4EI8_V }, // 8981 |
| 30252 | { PseudoVSOXSEG4EI8_V_MF4_M2_MASK, VSOXSEG4EI8_V }, // 8982 |
| 30253 | { PseudoVSOXSEG4EI8_V_MF4_MF2, VSOXSEG4EI8_V }, // 8983 |
| 30254 | { PseudoVSOXSEG4EI8_V_MF4_MF2_MASK, VSOXSEG4EI8_V }, // 8984 |
| 30255 | { PseudoVSOXSEG4EI8_V_MF4_MF4, VSOXSEG4EI8_V }, // 8985 |
| 30256 | { PseudoVSOXSEG4EI8_V_MF4_MF4_MASK, VSOXSEG4EI8_V }, // 8986 |
| 30257 | { PseudoVSOXSEG4EI8_V_MF8_M1, VSOXSEG4EI8_V }, // 8987 |
| 30258 | { PseudoVSOXSEG4EI8_V_MF8_M1_MASK, VSOXSEG4EI8_V }, // 8988 |
| 30259 | { PseudoVSOXSEG4EI8_V_MF8_MF2, VSOXSEG4EI8_V }, // 8989 |
| 30260 | { PseudoVSOXSEG4EI8_V_MF8_MF2_MASK, VSOXSEG4EI8_V }, // 8990 |
| 30261 | { PseudoVSOXSEG4EI8_V_MF8_MF4, VSOXSEG4EI8_V }, // 8991 |
| 30262 | { PseudoVSOXSEG4EI8_V_MF8_MF4_MASK, VSOXSEG4EI8_V }, // 8992 |
| 30263 | { PseudoVSOXSEG4EI8_V_MF8_MF8, VSOXSEG4EI8_V }, // 8993 |
| 30264 | { PseudoVSOXSEG4EI8_V_MF8_MF8_MASK, VSOXSEG4EI8_V }, // 8994 |
| 30265 | { PseudoVSOXSEG5EI16_V_M1_M1, VSOXSEG5EI16_V }, // 8995 |
| 30266 | { PseudoVSOXSEG5EI16_V_M1_M1_MASK, VSOXSEG5EI16_V }, // 8996 |
| 30267 | { PseudoVSOXSEG5EI16_V_M1_MF2, VSOXSEG5EI16_V }, // 8997 |
| 30268 | { PseudoVSOXSEG5EI16_V_M1_MF2_MASK, VSOXSEG5EI16_V }, // 8998 |
| 30269 | { PseudoVSOXSEG5EI16_V_M2_M1, VSOXSEG5EI16_V }, // 8999 |
| 30270 | { PseudoVSOXSEG5EI16_V_M2_M1_MASK, VSOXSEG5EI16_V }, // 9000 |
| 30271 | { PseudoVSOXSEG5EI16_V_MF2_M1, VSOXSEG5EI16_V }, // 9001 |
| 30272 | { PseudoVSOXSEG5EI16_V_MF2_M1_MASK, VSOXSEG5EI16_V }, // 9002 |
| 30273 | { PseudoVSOXSEG5EI16_V_MF2_MF2, VSOXSEG5EI16_V }, // 9003 |
| 30274 | { PseudoVSOXSEG5EI16_V_MF2_MF2_MASK, VSOXSEG5EI16_V }, // 9004 |
| 30275 | { PseudoVSOXSEG5EI16_V_MF2_MF4, VSOXSEG5EI16_V }, // 9005 |
| 30276 | { PseudoVSOXSEG5EI16_V_MF2_MF4_MASK, VSOXSEG5EI16_V }, // 9006 |
| 30277 | { PseudoVSOXSEG5EI16_V_MF4_M1, VSOXSEG5EI16_V }, // 9007 |
| 30278 | { PseudoVSOXSEG5EI16_V_MF4_M1_MASK, VSOXSEG5EI16_V }, // 9008 |
| 30279 | { PseudoVSOXSEG5EI16_V_MF4_MF2, VSOXSEG5EI16_V }, // 9009 |
| 30280 | { PseudoVSOXSEG5EI16_V_MF4_MF2_MASK, VSOXSEG5EI16_V }, // 9010 |
| 30281 | { PseudoVSOXSEG5EI16_V_MF4_MF4, VSOXSEG5EI16_V }, // 9011 |
| 30282 | { PseudoVSOXSEG5EI16_V_MF4_MF4_MASK, VSOXSEG5EI16_V }, // 9012 |
| 30283 | { PseudoVSOXSEG5EI16_V_MF4_MF8, VSOXSEG5EI16_V }, // 9013 |
| 30284 | { PseudoVSOXSEG5EI16_V_MF4_MF8_MASK, VSOXSEG5EI16_V }, // 9014 |
| 30285 | { PseudoVSOXSEG5EI32_V_M1_M1, VSOXSEG5EI32_V }, // 9015 |
| 30286 | { PseudoVSOXSEG5EI32_V_M1_M1_MASK, VSOXSEG5EI32_V }, // 9016 |
| 30287 | { PseudoVSOXSEG5EI32_V_M1_MF2, VSOXSEG5EI32_V }, // 9017 |
| 30288 | { PseudoVSOXSEG5EI32_V_M1_MF2_MASK, VSOXSEG5EI32_V }, // 9018 |
| 30289 | { PseudoVSOXSEG5EI32_V_M1_MF4, VSOXSEG5EI32_V }, // 9019 |
| 30290 | { PseudoVSOXSEG5EI32_V_M1_MF4_MASK, VSOXSEG5EI32_V }, // 9020 |
| 30291 | { PseudoVSOXSEG5EI32_V_M2_M1, VSOXSEG5EI32_V }, // 9021 |
| 30292 | { PseudoVSOXSEG5EI32_V_M2_M1_MASK, VSOXSEG5EI32_V }, // 9022 |
| 30293 | { PseudoVSOXSEG5EI32_V_M2_MF2, VSOXSEG5EI32_V }, // 9023 |
| 30294 | { PseudoVSOXSEG5EI32_V_M2_MF2_MASK, VSOXSEG5EI32_V }, // 9024 |
| 30295 | { PseudoVSOXSEG5EI32_V_M4_M1, VSOXSEG5EI32_V }, // 9025 |
| 30296 | { PseudoVSOXSEG5EI32_V_M4_M1_MASK, VSOXSEG5EI32_V }, // 9026 |
| 30297 | { PseudoVSOXSEG5EI32_V_MF2_M1, VSOXSEG5EI32_V }, // 9027 |
| 30298 | { PseudoVSOXSEG5EI32_V_MF2_M1_MASK, VSOXSEG5EI32_V }, // 9028 |
| 30299 | { PseudoVSOXSEG5EI32_V_MF2_MF2, VSOXSEG5EI32_V }, // 9029 |
| 30300 | { PseudoVSOXSEG5EI32_V_MF2_MF2_MASK, VSOXSEG5EI32_V }, // 9030 |
| 30301 | { PseudoVSOXSEG5EI32_V_MF2_MF4, VSOXSEG5EI32_V }, // 9031 |
| 30302 | { PseudoVSOXSEG5EI32_V_MF2_MF4_MASK, VSOXSEG5EI32_V }, // 9032 |
| 30303 | { PseudoVSOXSEG5EI32_V_MF2_MF8, VSOXSEG5EI32_V }, // 9033 |
| 30304 | { PseudoVSOXSEG5EI32_V_MF2_MF8_MASK, VSOXSEG5EI32_V }, // 9034 |
| 30305 | { PseudoVSOXSEG5EI64_V_M1_M1, VSOXSEG5EI64_V }, // 9035 |
| 30306 | { PseudoVSOXSEG5EI64_V_M1_M1_MASK, VSOXSEG5EI64_V }, // 9036 |
| 30307 | { PseudoVSOXSEG5EI64_V_M1_MF2, VSOXSEG5EI64_V }, // 9037 |
| 30308 | { PseudoVSOXSEG5EI64_V_M1_MF2_MASK, VSOXSEG5EI64_V }, // 9038 |
| 30309 | { PseudoVSOXSEG5EI64_V_M1_MF4, VSOXSEG5EI64_V }, // 9039 |
| 30310 | { PseudoVSOXSEG5EI64_V_M1_MF4_MASK, VSOXSEG5EI64_V }, // 9040 |
| 30311 | { PseudoVSOXSEG5EI64_V_M1_MF8, VSOXSEG5EI64_V }, // 9041 |
| 30312 | { PseudoVSOXSEG5EI64_V_M1_MF8_MASK, VSOXSEG5EI64_V }, // 9042 |
| 30313 | { PseudoVSOXSEG5EI64_V_M2_M1, VSOXSEG5EI64_V }, // 9043 |
| 30314 | { PseudoVSOXSEG5EI64_V_M2_M1_MASK, VSOXSEG5EI64_V }, // 9044 |
| 30315 | { PseudoVSOXSEG5EI64_V_M2_MF2, VSOXSEG5EI64_V }, // 9045 |
| 30316 | { PseudoVSOXSEG5EI64_V_M2_MF2_MASK, VSOXSEG5EI64_V }, // 9046 |
| 30317 | { PseudoVSOXSEG5EI64_V_M2_MF4, VSOXSEG5EI64_V }, // 9047 |
| 30318 | { PseudoVSOXSEG5EI64_V_M2_MF4_MASK, VSOXSEG5EI64_V }, // 9048 |
| 30319 | { PseudoVSOXSEG5EI64_V_M4_M1, VSOXSEG5EI64_V }, // 9049 |
| 30320 | { PseudoVSOXSEG5EI64_V_M4_M1_MASK, VSOXSEG5EI64_V }, // 9050 |
| 30321 | { PseudoVSOXSEG5EI64_V_M4_MF2, VSOXSEG5EI64_V }, // 9051 |
| 30322 | { PseudoVSOXSEG5EI64_V_M4_MF2_MASK, VSOXSEG5EI64_V }, // 9052 |
| 30323 | { PseudoVSOXSEG5EI64_V_M8_M1, VSOXSEG5EI64_V }, // 9053 |
| 30324 | { PseudoVSOXSEG5EI64_V_M8_M1_MASK, VSOXSEG5EI64_V }, // 9054 |
| 30325 | { PseudoVSOXSEG5EI8_V_M1_M1, VSOXSEG5EI8_V }, // 9055 |
| 30326 | { PseudoVSOXSEG5EI8_V_M1_M1_MASK, VSOXSEG5EI8_V }, // 9056 |
| 30327 | { PseudoVSOXSEG5EI8_V_MF2_M1, VSOXSEG5EI8_V }, // 9057 |
| 30328 | { PseudoVSOXSEG5EI8_V_MF2_M1_MASK, VSOXSEG5EI8_V }, // 9058 |
| 30329 | { PseudoVSOXSEG5EI8_V_MF2_MF2, VSOXSEG5EI8_V }, // 9059 |
| 30330 | { PseudoVSOXSEG5EI8_V_MF2_MF2_MASK, VSOXSEG5EI8_V }, // 9060 |
| 30331 | { PseudoVSOXSEG5EI8_V_MF4_M1, VSOXSEG5EI8_V }, // 9061 |
| 30332 | { PseudoVSOXSEG5EI8_V_MF4_M1_MASK, VSOXSEG5EI8_V }, // 9062 |
| 30333 | { PseudoVSOXSEG5EI8_V_MF4_MF2, VSOXSEG5EI8_V }, // 9063 |
| 30334 | { PseudoVSOXSEG5EI8_V_MF4_MF2_MASK, VSOXSEG5EI8_V }, // 9064 |
| 30335 | { PseudoVSOXSEG5EI8_V_MF4_MF4, VSOXSEG5EI8_V }, // 9065 |
| 30336 | { PseudoVSOXSEG5EI8_V_MF4_MF4_MASK, VSOXSEG5EI8_V }, // 9066 |
| 30337 | { PseudoVSOXSEG5EI8_V_MF8_M1, VSOXSEG5EI8_V }, // 9067 |
| 30338 | { PseudoVSOXSEG5EI8_V_MF8_M1_MASK, VSOXSEG5EI8_V }, // 9068 |
| 30339 | { PseudoVSOXSEG5EI8_V_MF8_MF2, VSOXSEG5EI8_V }, // 9069 |
| 30340 | { PseudoVSOXSEG5EI8_V_MF8_MF2_MASK, VSOXSEG5EI8_V }, // 9070 |
| 30341 | { PseudoVSOXSEG5EI8_V_MF8_MF4, VSOXSEG5EI8_V }, // 9071 |
| 30342 | { PseudoVSOXSEG5EI8_V_MF8_MF4_MASK, VSOXSEG5EI8_V }, // 9072 |
| 30343 | { PseudoVSOXSEG5EI8_V_MF8_MF8, VSOXSEG5EI8_V }, // 9073 |
| 30344 | { PseudoVSOXSEG5EI8_V_MF8_MF8_MASK, VSOXSEG5EI8_V }, // 9074 |
| 30345 | { PseudoVSOXSEG6EI16_V_M1_M1, VSOXSEG6EI16_V }, // 9075 |
| 30346 | { PseudoVSOXSEG6EI16_V_M1_M1_MASK, VSOXSEG6EI16_V }, // 9076 |
| 30347 | { PseudoVSOXSEG6EI16_V_M1_MF2, VSOXSEG6EI16_V }, // 9077 |
| 30348 | { PseudoVSOXSEG6EI16_V_M1_MF2_MASK, VSOXSEG6EI16_V }, // 9078 |
| 30349 | { PseudoVSOXSEG6EI16_V_M2_M1, VSOXSEG6EI16_V }, // 9079 |
| 30350 | { PseudoVSOXSEG6EI16_V_M2_M1_MASK, VSOXSEG6EI16_V }, // 9080 |
| 30351 | { PseudoVSOXSEG6EI16_V_MF2_M1, VSOXSEG6EI16_V }, // 9081 |
| 30352 | { PseudoVSOXSEG6EI16_V_MF2_M1_MASK, VSOXSEG6EI16_V }, // 9082 |
| 30353 | { PseudoVSOXSEG6EI16_V_MF2_MF2, VSOXSEG6EI16_V }, // 9083 |
| 30354 | { PseudoVSOXSEG6EI16_V_MF2_MF2_MASK, VSOXSEG6EI16_V }, // 9084 |
| 30355 | { PseudoVSOXSEG6EI16_V_MF2_MF4, VSOXSEG6EI16_V }, // 9085 |
| 30356 | { PseudoVSOXSEG6EI16_V_MF2_MF4_MASK, VSOXSEG6EI16_V }, // 9086 |
| 30357 | { PseudoVSOXSEG6EI16_V_MF4_M1, VSOXSEG6EI16_V }, // 9087 |
| 30358 | { PseudoVSOXSEG6EI16_V_MF4_M1_MASK, VSOXSEG6EI16_V }, // 9088 |
| 30359 | { PseudoVSOXSEG6EI16_V_MF4_MF2, VSOXSEG6EI16_V }, // 9089 |
| 30360 | { PseudoVSOXSEG6EI16_V_MF4_MF2_MASK, VSOXSEG6EI16_V }, // 9090 |
| 30361 | { PseudoVSOXSEG6EI16_V_MF4_MF4, VSOXSEG6EI16_V }, // 9091 |
| 30362 | { PseudoVSOXSEG6EI16_V_MF4_MF4_MASK, VSOXSEG6EI16_V }, // 9092 |
| 30363 | { PseudoVSOXSEG6EI16_V_MF4_MF8, VSOXSEG6EI16_V }, // 9093 |
| 30364 | { PseudoVSOXSEG6EI16_V_MF4_MF8_MASK, VSOXSEG6EI16_V }, // 9094 |
| 30365 | { PseudoVSOXSEG6EI32_V_M1_M1, VSOXSEG6EI32_V }, // 9095 |
| 30366 | { PseudoVSOXSEG6EI32_V_M1_M1_MASK, VSOXSEG6EI32_V }, // 9096 |
| 30367 | { PseudoVSOXSEG6EI32_V_M1_MF2, VSOXSEG6EI32_V }, // 9097 |
| 30368 | { PseudoVSOXSEG6EI32_V_M1_MF2_MASK, VSOXSEG6EI32_V }, // 9098 |
| 30369 | { PseudoVSOXSEG6EI32_V_M1_MF4, VSOXSEG6EI32_V }, // 9099 |
| 30370 | { PseudoVSOXSEG6EI32_V_M1_MF4_MASK, VSOXSEG6EI32_V }, // 9100 |
| 30371 | { PseudoVSOXSEG6EI32_V_M2_M1, VSOXSEG6EI32_V }, // 9101 |
| 30372 | { PseudoVSOXSEG6EI32_V_M2_M1_MASK, VSOXSEG6EI32_V }, // 9102 |
| 30373 | { PseudoVSOXSEG6EI32_V_M2_MF2, VSOXSEG6EI32_V }, // 9103 |
| 30374 | { PseudoVSOXSEG6EI32_V_M2_MF2_MASK, VSOXSEG6EI32_V }, // 9104 |
| 30375 | { PseudoVSOXSEG6EI32_V_M4_M1, VSOXSEG6EI32_V }, // 9105 |
| 30376 | { PseudoVSOXSEG6EI32_V_M4_M1_MASK, VSOXSEG6EI32_V }, // 9106 |
| 30377 | { PseudoVSOXSEG6EI32_V_MF2_M1, VSOXSEG6EI32_V }, // 9107 |
| 30378 | { PseudoVSOXSEG6EI32_V_MF2_M1_MASK, VSOXSEG6EI32_V }, // 9108 |
| 30379 | { PseudoVSOXSEG6EI32_V_MF2_MF2, VSOXSEG6EI32_V }, // 9109 |
| 30380 | { PseudoVSOXSEG6EI32_V_MF2_MF2_MASK, VSOXSEG6EI32_V }, // 9110 |
| 30381 | { PseudoVSOXSEG6EI32_V_MF2_MF4, VSOXSEG6EI32_V }, // 9111 |
| 30382 | { PseudoVSOXSEG6EI32_V_MF2_MF4_MASK, VSOXSEG6EI32_V }, // 9112 |
| 30383 | { PseudoVSOXSEG6EI32_V_MF2_MF8, VSOXSEG6EI32_V }, // 9113 |
| 30384 | { PseudoVSOXSEG6EI32_V_MF2_MF8_MASK, VSOXSEG6EI32_V }, // 9114 |
| 30385 | { PseudoVSOXSEG6EI64_V_M1_M1, VSOXSEG6EI64_V }, // 9115 |
| 30386 | { PseudoVSOXSEG6EI64_V_M1_M1_MASK, VSOXSEG6EI64_V }, // 9116 |
| 30387 | { PseudoVSOXSEG6EI64_V_M1_MF2, VSOXSEG6EI64_V }, // 9117 |
| 30388 | { PseudoVSOXSEG6EI64_V_M1_MF2_MASK, VSOXSEG6EI64_V }, // 9118 |
| 30389 | { PseudoVSOXSEG6EI64_V_M1_MF4, VSOXSEG6EI64_V }, // 9119 |
| 30390 | { PseudoVSOXSEG6EI64_V_M1_MF4_MASK, VSOXSEG6EI64_V }, // 9120 |
| 30391 | { PseudoVSOXSEG6EI64_V_M1_MF8, VSOXSEG6EI64_V }, // 9121 |
| 30392 | { PseudoVSOXSEG6EI64_V_M1_MF8_MASK, VSOXSEG6EI64_V }, // 9122 |
| 30393 | { PseudoVSOXSEG6EI64_V_M2_M1, VSOXSEG6EI64_V }, // 9123 |
| 30394 | { PseudoVSOXSEG6EI64_V_M2_M1_MASK, VSOXSEG6EI64_V }, // 9124 |
| 30395 | { PseudoVSOXSEG6EI64_V_M2_MF2, VSOXSEG6EI64_V }, // 9125 |
| 30396 | { PseudoVSOXSEG6EI64_V_M2_MF2_MASK, VSOXSEG6EI64_V }, // 9126 |
| 30397 | { PseudoVSOXSEG6EI64_V_M2_MF4, VSOXSEG6EI64_V }, // 9127 |
| 30398 | { PseudoVSOXSEG6EI64_V_M2_MF4_MASK, VSOXSEG6EI64_V }, // 9128 |
| 30399 | { PseudoVSOXSEG6EI64_V_M4_M1, VSOXSEG6EI64_V }, // 9129 |
| 30400 | { PseudoVSOXSEG6EI64_V_M4_M1_MASK, VSOXSEG6EI64_V }, // 9130 |
| 30401 | { PseudoVSOXSEG6EI64_V_M4_MF2, VSOXSEG6EI64_V }, // 9131 |
| 30402 | { PseudoVSOXSEG6EI64_V_M4_MF2_MASK, VSOXSEG6EI64_V }, // 9132 |
| 30403 | { PseudoVSOXSEG6EI64_V_M8_M1, VSOXSEG6EI64_V }, // 9133 |
| 30404 | { PseudoVSOXSEG6EI64_V_M8_M1_MASK, VSOXSEG6EI64_V }, // 9134 |
| 30405 | { PseudoVSOXSEG6EI8_V_M1_M1, VSOXSEG6EI8_V }, // 9135 |
| 30406 | { PseudoVSOXSEG6EI8_V_M1_M1_MASK, VSOXSEG6EI8_V }, // 9136 |
| 30407 | { PseudoVSOXSEG6EI8_V_MF2_M1, VSOXSEG6EI8_V }, // 9137 |
| 30408 | { PseudoVSOXSEG6EI8_V_MF2_M1_MASK, VSOXSEG6EI8_V }, // 9138 |
| 30409 | { PseudoVSOXSEG6EI8_V_MF2_MF2, VSOXSEG6EI8_V }, // 9139 |
| 30410 | { PseudoVSOXSEG6EI8_V_MF2_MF2_MASK, VSOXSEG6EI8_V }, // 9140 |
| 30411 | { PseudoVSOXSEG6EI8_V_MF4_M1, VSOXSEG6EI8_V }, // 9141 |
| 30412 | { PseudoVSOXSEG6EI8_V_MF4_M1_MASK, VSOXSEG6EI8_V }, // 9142 |
| 30413 | { PseudoVSOXSEG6EI8_V_MF4_MF2, VSOXSEG6EI8_V }, // 9143 |
| 30414 | { PseudoVSOXSEG6EI8_V_MF4_MF2_MASK, VSOXSEG6EI8_V }, // 9144 |
| 30415 | { PseudoVSOXSEG6EI8_V_MF4_MF4, VSOXSEG6EI8_V }, // 9145 |
| 30416 | { PseudoVSOXSEG6EI8_V_MF4_MF4_MASK, VSOXSEG6EI8_V }, // 9146 |
| 30417 | { PseudoVSOXSEG6EI8_V_MF8_M1, VSOXSEG6EI8_V }, // 9147 |
| 30418 | { PseudoVSOXSEG6EI8_V_MF8_M1_MASK, VSOXSEG6EI8_V }, // 9148 |
| 30419 | { PseudoVSOXSEG6EI8_V_MF8_MF2, VSOXSEG6EI8_V }, // 9149 |
| 30420 | { PseudoVSOXSEG6EI8_V_MF8_MF2_MASK, VSOXSEG6EI8_V }, // 9150 |
| 30421 | { PseudoVSOXSEG6EI8_V_MF8_MF4, VSOXSEG6EI8_V }, // 9151 |
| 30422 | { PseudoVSOXSEG6EI8_V_MF8_MF4_MASK, VSOXSEG6EI8_V }, // 9152 |
| 30423 | { PseudoVSOXSEG6EI8_V_MF8_MF8, VSOXSEG6EI8_V }, // 9153 |
| 30424 | { PseudoVSOXSEG6EI8_V_MF8_MF8_MASK, VSOXSEG6EI8_V }, // 9154 |
| 30425 | { PseudoVSOXSEG7EI16_V_M1_M1, VSOXSEG7EI16_V }, // 9155 |
| 30426 | { PseudoVSOXSEG7EI16_V_M1_M1_MASK, VSOXSEG7EI16_V }, // 9156 |
| 30427 | { PseudoVSOXSEG7EI16_V_M1_MF2, VSOXSEG7EI16_V }, // 9157 |
| 30428 | { PseudoVSOXSEG7EI16_V_M1_MF2_MASK, VSOXSEG7EI16_V }, // 9158 |
| 30429 | { PseudoVSOXSEG7EI16_V_M2_M1, VSOXSEG7EI16_V }, // 9159 |
| 30430 | { PseudoVSOXSEG7EI16_V_M2_M1_MASK, VSOXSEG7EI16_V }, // 9160 |
| 30431 | { PseudoVSOXSEG7EI16_V_MF2_M1, VSOXSEG7EI16_V }, // 9161 |
| 30432 | { PseudoVSOXSEG7EI16_V_MF2_M1_MASK, VSOXSEG7EI16_V }, // 9162 |
| 30433 | { PseudoVSOXSEG7EI16_V_MF2_MF2, VSOXSEG7EI16_V }, // 9163 |
| 30434 | { PseudoVSOXSEG7EI16_V_MF2_MF2_MASK, VSOXSEG7EI16_V }, // 9164 |
| 30435 | { PseudoVSOXSEG7EI16_V_MF2_MF4, VSOXSEG7EI16_V }, // 9165 |
| 30436 | { PseudoVSOXSEG7EI16_V_MF2_MF4_MASK, VSOXSEG7EI16_V }, // 9166 |
| 30437 | { PseudoVSOXSEG7EI16_V_MF4_M1, VSOXSEG7EI16_V }, // 9167 |
| 30438 | { PseudoVSOXSEG7EI16_V_MF4_M1_MASK, VSOXSEG7EI16_V }, // 9168 |
| 30439 | { PseudoVSOXSEG7EI16_V_MF4_MF2, VSOXSEG7EI16_V }, // 9169 |
| 30440 | { PseudoVSOXSEG7EI16_V_MF4_MF2_MASK, VSOXSEG7EI16_V }, // 9170 |
| 30441 | { PseudoVSOXSEG7EI16_V_MF4_MF4, VSOXSEG7EI16_V }, // 9171 |
| 30442 | { PseudoVSOXSEG7EI16_V_MF4_MF4_MASK, VSOXSEG7EI16_V }, // 9172 |
| 30443 | { PseudoVSOXSEG7EI16_V_MF4_MF8, VSOXSEG7EI16_V }, // 9173 |
| 30444 | { PseudoVSOXSEG7EI16_V_MF4_MF8_MASK, VSOXSEG7EI16_V }, // 9174 |
| 30445 | { PseudoVSOXSEG7EI32_V_M1_M1, VSOXSEG7EI32_V }, // 9175 |
| 30446 | { PseudoVSOXSEG7EI32_V_M1_M1_MASK, VSOXSEG7EI32_V }, // 9176 |
| 30447 | { PseudoVSOXSEG7EI32_V_M1_MF2, VSOXSEG7EI32_V }, // 9177 |
| 30448 | { PseudoVSOXSEG7EI32_V_M1_MF2_MASK, VSOXSEG7EI32_V }, // 9178 |
| 30449 | { PseudoVSOXSEG7EI32_V_M1_MF4, VSOXSEG7EI32_V }, // 9179 |
| 30450 | { PseudoVSOXSEG7EI32_V_M1_MF4_MASK, VSOXSEG7EI32_V }, // 9180 |
| 30451 | { PseudoVSOXSEG7EI32_V_M2_M1, VSOXSEG7EI32_V }, // 9181 |
| 30452 | { PseudoVSOXSEG7EI32_V_M2_M1_MASK, VSOXSEG7EI32_V }, // 9182 |
| 30453 | { PseudoVSOXSEG7EI32_V_M2_MF2, VSOXSEG7EI32_V }, // 9183 |
| 30454 | { PseudoVSOXSEG7EI32_V_M2_MF2_MASK, VSOXSEG7EI32_V }, // 9184 |
| 30455 | { PseudoVSOXSEG7EI32_V_M4_M1, VSOXSEG7EI32_V }, // 9185 |
| 30456 | { PseudoVSOXSEG7EI32_V_M4_M1_MASK, VSOXSEG7EI32_V }, // 9186 |
| 30457 | { PseudoVSOXSEG7EI32_V_MF2_M1, VSOXSEG7EI32_V }, // 9187 |
| 30458 | { PseudoVSOXSEG7EI32_V_MF2_M1_MASK, VSOXSEG7EI32_V }, // 9188 |
| 30459 | { PseudoVSOXSEG7EI32_V_MF2_MF2, VSOXSEG7EI32_V }, // 9189 |
| 30460 | { PseudoVSOXSEG7EI32_V_MF2_MF2_MASK, VSOXSEG7EI32_V }, // 9190 |
| 30461 | { PseudoVSOXSEG7EI32_V_MF2_MF4, VSOXSEG7EI32_V }, // 9191 |
| 30462 | { PseudoVSOXSEG7EI32_V_MF2_MF4_MASK, VSOXSEG7EI32_V }, // 9192 |
| 30463 | { PseudoVSOXSEG7EI32_V_MF2_MF8, VSOXSEG7EI32_V }, // 9193 |
| 30464 | { PseudoVSOXSEG7EI32_V_MF2_MF8_MASK, VSOXSEG7EI32_V }, // 9194 |
| 30465 | { PseudoVSOXSEG7EI64_V_M1_M1, VSOXSEG7EI64_V }, // 9195 |
| 30466 | { PseudoVSOXSEG7EI64_V_M1_M1_MASK, VSOXSEG7EI64_V }, // 9196 |
| 30467 | { PseudoVSOXSEG7EI64_V_M1_MF2, VSOXSEG7EI64_V }, // 9197 |
| 30468 | { PseudoVSOXSEG7EI64_V_M1_MF2_MASK, VSOXSEG7EI64_V }, // 9198 |
| 30469 | { PseudoVSOXSEG7EI64_V_M1_MF4, VSOXSEG7EI64_V }, // 9199 |
| 30470 | { PseudoVSOXSEG7EI64_V_M1_MF4_MASK, VSOXSEG7EI64_V }, // 9200 |
| 30471 | { PseudoVSOXSEG7EI64_V_M1_MF8, VSOXSEG7EI64_V }, // 9201 |
| 30472 | { PseudoVSOXSEG7EI64_V_M1_MF8_MASK, VSOXSEG7EI64_V }, // 9202 |
| 30473 | { PseudoVSOXSEG7EI64_V_M2_M1, VSOXSEG7EI64_V }, // 9203 |
| 30474 | { PseudoVSOXSEG7EI64_V_M2_M1_MASK, VSOXSEG7EI64_V }, // 9204 |
| 30475 | { PseudoVSOXSEG7EI64_V_M2_MF2, VSOXSEG7EI64_V }, // 9205 |
| 30476 | { PseudoVSOXSEG7EI64_V_M2_MF2_MASK, VSOXSEG7EI64_V }, // 9206 |
| 30477 | { PseudoVSOXSEG7EI64_V_M2_MF4, VSOXSEG7EI64_V }, // 9207 |
| 30478 | { PseudoVSOXSEG7EI64_V_M2_MF4_MASK, VSOXSEG7EI64_V }, // 9208 |
| 30479 | { PseudoVSOXSEG7EI64_V_M4_M1, VSOXSEG7EI64_V }, // 9209 |
| 30480 | { PseudoVSOXSEG7EI64_V_M4_M1_MASK, VSOXSEG7EI64_V }, // 9210 |
| 30481 | { PseudoVSOXSEG7EI64_V_M4_MF2, VSOXSEG7EI64_V }, // 9211 |
| 30482 | { PseudoVSOXSEG7EI64_V_M4_MF2_MASK, VSOXSEG7EI64_V }, // 9212 |
| 30483 | { PseudoVSOXSEG7EI64_V_M8_M1, VSOXSEG7EI64_V }, // 9213 |
| 30484 | { PseudoVSOXSEG7EI64_V_M8_M1_MASK, VSOXSEG7EI64_V }, // 9214 |
| 30485 | { PseudoVSOXSEG7EI8_V_M1_M1, VSOXSEG7EI8_V }, // 9215 |
| 30486 | { PseudoVSOXSEG7EI8_V_M1_M1_MASK, VSOXSEG7EI8_V }, // 9216 |
| 30487 | { PseudoVSOXSEG7EI8_V_MF2_M1, VSOXSEG7EI8_V }, // 9217 |
| 30488 | { PseudoVSOXSEG7EI8_V_MF2_M1_MASK, VSOXSEG7EI8_V }, // 9218 |
| 30489 | { PseudoVSOXSEG7EI8_V_MF2_MF2, VSOXSEG7EI8_V }, // 9219 |
| 30490 | { PseudoVSOXSEG7EI8_V_MF2_MF2_MASK, VSOXSEG7EI8_V }, // 9220 |
| 30491 | { PseudoVSOXSEG7EI8_V_MF4_M1, VSOXSEG7EI8_V }, // 9221 |
| 30492 | { PseudoVSOXSEG7EI8_V_MF4_M1_MASK, VSOXSEG7EI8_V }, // 9222 |
| 30493 | { PseudoVSOXSEG7EI8_V_MF4_MF2, VSOXSEG7EI8_V }, // 9223 |
| 30494 | { PseudoVSOXSEG7EI8_V_MF4_MF2_MASK, VSOXSEG7EI8_V }, // 9224 |
| 30495 | { PseudoVSOXSEG7EI8_V_MF4_MF4, VSOXSEG7EI8_V }, // 9225 |
| 30496 | { PseudoVSOXSEG7EI8_V_MF4_MF4_MASK, VSOXSEG7EI8_V }, // 9226 |
| 30497 | { PseudoVSOXSEG7EI8_V_MF8_M1, VSOXSEG7EI8_V }, // 9227 |
| 30498 | { PseudoVSOXSEG7EI8_V_MF8_M1_MASK, VSOXSEG7EI8_V }, // 9228 |
| 30499 | { PseudoVSOXSEG7EI8_V_MF8_MF2, VSOXSEG7EI8_V }, // 9229 |
| 30500 | { PseudoVSOXSEG7EI8_V_MF8_MF2_MASK, VSOXSEG7EI8_V }, // 9230 |
| 30501 | { PseudoVSOXSEG7EI8_V_MF8_MF4, VSOXSEG7EI8_V }, // 9231 |
| 30502 | { PseudoVSOXSEG7EI8_V_MF8_MF4_MASK, VSOXSEG7EI8_V }, // 9232 |
| 30503 | { PseudoVSOXSEG7EI8_V_MF8_MF8, VSOXSEG7EI8_V }, // 9233 |
| 30504 | { PseudoVSOXSEG7EI8_V_MF8_MF8_MASK, VSOXSEG7EI8_V }, // 9234 |
| 30505 | { PseudoVSOXSEG8EI16_V_M1_M1, VSOXSEG8EI16_V }, // 9235 |
| 30506 | { PseudoVSOXSEG8EI16_V_M1_M1_MASK, VSOXSEG8EI16_V }, // 9236 |
| 30507 | { PseudoVSOXSEG8EI16_V_M1_MF2, VSOXSEG8EI16_V }, // 9237 |
| 30508 | { PseudoVSOXSEG8EI16_V_M1_MF2_MASK, VSOXSEG8EI16_V }, // 9238 |
| 30509 | { PseudoVSOXSEG8EI16_V_M2_M1, VSOXSEG8EI16_V }, // 9239 |
| 30510 | { PseudoVSOXSEG8EI16_V_M2_M1_MASK, VSOXSEG8EI16_V }, // 9240 |
| 30511 | { PseudoVSOXSEG8EI16_V_MF2_M1, VSOXSEG8EI16_V }, // 9241 |
| 30512 | { PseudoVSOXSEG8EI16_V_MF2_M1_MASK, VSOXSEG8EI16_V }, // 9242 |
| 30513 | { PseudoVSOXSEG8EI16_V_MF2_MF2, VSOXSEG8EI16_V }, // 9243 |
| 30514 | { PseudoVSOXSEG8EI16_V_MF2_MF2_MASK, VSOXSEG8EI16_V }, // 9244 |
| 30515 | { PseudoVSOXSEG8EI16_V_MF2_MF4, VSOXSEG8EI16_V }, // 9245 |
| 30516 | { PseudoVSOXSEG8EI16_V_MF2_MF4_MASK, VSOXSEG8EI16_V }, // 9246 |
| 30517 | { PseudoVSOXSEG8EI16_V_MF4_M1, VSOXSEG8EI16_V }, // 9247 |
| 30518 | { PseudoVSOXSEG8EI16_V_MF4_M1_MASK, VSOXSEG8EI16_V }, // 9248 |
| 30519 | { PseudoVSOXSEG8EI16_V_MF4_MF2, VSOXSEG8EI16_V }, // 9249 |
| 30520 | { PseudoVSOXSEG8EI16_V_MF4_MF2_MASK, VSOXSEG8EI16_V }, // 9250 |
| 30521 | { PseudoVSOXSEG8EI16_V_MF4_MF4, VSOXSEG8EI16_V }, // 9251 |
| 30522 | { PseudoVSOXSEG8EI16_V_MF4_MF4_MASK, VSOXSEG8EI16_V }, // 9252 |
| 30523 | { PseudoVSOXSEG8EI16_V_MF4_MF8, VSOXSEG8EI16_V }, // 9253 |
| 30524 | { PseudoVSOXSEG8EI16_V_MF4_MF8_MASK, VSOXSEG8EI16_V }, // 9254 |
| 30525 | { PseudoVSOXSEG8EI32_V_M1_M1, VSOXSEG8EI32_V }, // 9255 |
| 30526 | { PseudoVSOXSEG8EI32_V_M1_M1_MASK, VSOXSEG8EI32_V }, // 9256 |
| 30527 | { PseudoVSOXSEG8EI32_V_M1_MF2, VSOXSEG8EI32_V }, // 9257 |
| 30528 | { PseudoVSOXSEG8EI32_V_M1_MF2_MASK, VSOXSEG8EI32_V }, // 9258 |
| 30529 | { PseudoVSOXSEG8EI32_V_M1_MF4, VSOXSEG8EI32_V }, // 9259 |
| 30530 | { PseudoVSOXSEG8EI32_V_M1_MF4_MASK, VSOXSEG8EI32_V }, // 9260 |
| 30531 | { PseudoVSOXSEG8EI32_V_M2_M1, VSOXSEG8EI32_V }, // 9261 |
| 30532 | { PseudoVSOXSEG8EI32_V_M2_M1_MASK, VSOXSEG8EI32_V }, // 9262 |
| 30533 | { PseudoVSOXSEG8EI32_V_M2_MF2, VSOXSEG8EI32_V }, // 9263 |
| 30534 | { PseudoVSOXSEG8EI32_V_M2_MF2_MASK, VSOXSEG8EI32_V }, // 9264 |
| 30535 | { PseudoVSOXSEG8EI32_V_M4_M1, VSOXSEG8EI32_V }, // 9265 |
| 30536 | { PseudoVSOXSEG8EI32_V_M4_M1_MASK, VSOXSEG8EI32_V }, // 9266 |
| 30537 | { PseudoVSOXSEG8EI32_V_MF2_M1, VSOXSEG8EI32_V }, // 9267 |
| 30538 | { PseudoVSOXSEG8EI32_V_MF2_M1_MASK, VSOXSEG8EI32_V }, // 9268 |
| 30539 | { PseudoVSOXSEG8EI32_V_MF2_MF2, VSOXSEG8EI32_V }, // 9269 |
| 30540 | { PseudoVSOXSEG8EI32_V_MF2_MF2_MASK, VSOXSEG8EI32_V }, // 9270 |
| 30541 | { PseudoVSOXSEG8EI32_V_MF2_MF4, VSOXSEG8EI32_V }, // 9271 |
| 30542 | { PseudoVSOXSEG8EI32_V_MF2_MF4_MASK, VSOXSEG8EI32_V }, // 9272 |
| 30543 | { PseudoVSOXSEG8EI32_V_MF2_MF8, VSOXSEG8EI32_V }, // 9273 |
| 30544 | { PseudoVSOXSEG8EI32_V_MF2_MF8_MASK, VSOXSEG8EI32_V }, // 9274 |
| 30545 | { PseudoVSOXSEG8EI64_V_M1_M1, VSOXSEG8EI64_V }, // 9275 |
| 30546 | { PseudoVSOXSEG8EI64_V_M1_M1_MASK, VSOXSEG8EI64_V }, // 9276 |
| 30547 | { PseudoVSOXSEG8EI64_V_M1_MF2, VSOXSEG8EI64_V }, // 9277 |
| 30548 | { PseudoVSOXSEG8EI64_V_M1_MF2_MASK, VSOXSEG8EI64_V }, // 9278 |
| 30549 | { PseudoVSOXSEG8EI64_V_M1_MF4, VSOXSEG8EI64_V }, // 9279 |
| 30550 | { PseudoVSOXSEG8EI64_V_M1_MF4_MASK, VSOXSEG8EI64_V }, // 9280 |
| 30551 | { PseudoVSOXSEG8EI64_V_M1_MF8, VSOXSEG8EI64_V }, // 9281 |
| 30552 | { PseudoVSOXSEG8EI64_V_M1_MF8_MASK, VSOXSEG8EI64_V }, // 9282 |
| 30553 | { PseudoVSOXSEG8EI64_V_M2_M1, VSOXSEG8EI64_V }, // 9283 |
| 30554 | { PseudoVSOXSEG8EI64_V_M2_M1_MASK, VSOXSEG8EI64_V }, // 9284 |
| 30555 | { PseudoVSOXSEG8EI64_V_M2_MF2, VSOXSEG8EI64_V }, // 9285 |
| 30556 | { PseudoVSOXSEG8EI64_V_M2_MF2_MASK, VSOXSEG8EI64_V }, // 9286 |
| 30557 | { PseudoVSOXSEG8EI64_V_M2_MF4, VSOXSEG8EI64_V }, // 9287 |
| 30558 | { PseudoVSOXSEG8EI64_V_M2_MF4_MASK, VSOXSEG8EI64_V }, // 9288 |
| 30559 | { PseudoVSOXSEG8EI64_V_M4_M1, VSOXSEG8EI64_V }, // 9289 |
| 30560 | { PseudoVSOXSEG8EI64_V_M4_M1_MASK, VSOXSEG8EI64_V }, // 9290 |
| 30561 | { PseudoVSOXSEG8EI64_V_M4_MF2, VSOXSEG8EI64_V }, // 9291 |
| 30562 | { PseudoVSOXSEG8EI64_V_M4_MF2_MASK, VSOXSEG8EI64_V }, // 9292 |
| 30563 | { PseudoVSOXSEG8EI64_V_M8_M1, VSOXSEG8EI64_V }, // 9293 |
| 30564 | { PseudoVSOXSEG8EI64_V_M8_M1_MASK, VSOXSEG8EI64_V }, // 9294 |
| 30565 | { PseudoVSOXSEG8EI8_V_M1_M1, VSOXSEG8EI8_V }, // 9295 |
| 30566 | { PseudoVSOXSEG8EI8_V_M1_M1_MASK, VSOXSEG8EI8_V }, // 9296 |
| 30567 | { PseudoVSOXSEG8EI8_V_MF2_M1, VSOXSEG8EI8_V }, // 9297 |
| 30568 | { PseudoVSOXSEG8EI8_V_MF2_M1_MASK, VSOXSEG8EI8_V }, // 9298 |
| 30569 | { PseudoVSOXSEG8EI8_V_MF2_MF2, VSOXSEG8EI8_V }, // 9299 |
| 30570 | { PseudoVSOXSEG8EI8_V_MF2_MF2_MASK, VSOXSEG8EI8_V }, // 9300 |
| 30571 | { PseudoVSOXSEG8EI8_V_MF4_M1, VSOXSEG8EI8_V }, // 9301 |
| 30572 | { PseudoVSOXSEG8EI8_V_MF4_M1_MASK, VSOXSEG8EI8_V }, // 9302 |
| 30573 | { PseudoVSOXSEG8EI8_V_MF4_MF2, VSOXSEG8EI8_V }, // 9303 |
| 30574 | { PseudoVSOXSEG8EI8_V_MF4_MF2_MASK, VSOXSEG8EI8_V }, // 9304 |
| 30575 | { PseudoVSOXSEG8EI8_V_MF4_MF4, VSOXSEG8EI8_V }, // 9305 |
| 30576 | { PseudoVSOXSEG8EI8_V_MF4_MF4_MASK, VSOXSEG8EI8_V }, // 9306 |
| 30577 | { PseudoVSOXSEG8EI8_V_MF8_M1, VSOXSEG8EI8_V }, // 9307 |
| 30578 | { PseudoVSOXSEG8EI8_V_MF8_M1_MASK, VSOXSEG8EI8_V }, // 9308 |
| 30579 | { PseudoVSOXSEG8EI8_V_MF8_MF2, VSOXSEG8EI8_V }, // 9309 |
| 30580 | { PseudoVSOXSEG8EI8_V_MF8_MF2_MASK, VSOXSEG8EI8_V }, // 9310 |
| 30581 | { PseudoVSOXSEG8EI8_V_MF8_MF4, VSOXSEG8EI8_V }, // 9311 |
| 30582 | { PseudoVSOXSEG8EI8_V_MF8_MF4_MASK, VSOXSEG8EI8_V }, // 9312 |
| 30583 | { PseudoVSOXSEG8EI8_V_MF8_MF8, VSOXSEG8EI8_V }, // 9313 |
| 30584 | { PseudoVSOXSEG8EI8_V_MF8_MF8_MASK, VSOXSEG8EI8_V }, // 9314 |
| 30585 | { PseudoVSRA_VI_M1, VSRA_VI }, // 9315 |
| 30586 | { PseudoVSRA_VI_M1_MASK, VSRA_VI }, // 9316 |
| 30587 | { PseudoVSRA_VI_M2, VSRA_VI }, // 9317 |
| 30588 | { PseudoVSRA_VI_M2_MASK, VSRA_VI }, // 9318 |
| 30589 | { PseudoVSRA_VI_M4, VSRA_VI }, // 9319 |
| 30590 | { PseudoVSRA_VI_M4_MASK, VSRA_VI }, // 9320 |
| 30591 | { PseudoVSRA_VI_M8, VSRA_VI }, // 9321 |
| 30592 | { PseudoVSRA_VI_M8_MASK, VSRA_VI }, // 9322 |
| 30593 | { PseudoVSRA_VI_MF2, VSRA_VI }, // 9323 |
| 30594 | { PseudoVSRA_VI_MF2_MASK, VSRA_VI }, // 9324 |
| 30595 | { PseudoVSRA_VI_MF4, VSRA_VI }, // 9325 |
| 30596 | { PseudoVSRA_VI_MF4_MASK, VSRA_VI }, // 9326 |
| 30597 | { PseudoVSRA_VI_MF8, VSRA_VI }, // 9327 |
| 30598 | { PseudoVSRA_VI_MF8_MASK, VSRA_VI }, // 9328 |
| 30599 | { PseudoVSRA_VV_M1, VSRA_VV }, // 9329 |
| 30600 | { PseudoVSRA_VV_M1_MASK, VSRA_VV }, // 9330 |
| 30601 | { PseudoVSRA_VV_M2, VSRA_VV }, // 9331 |
| 30602 | { PseudoVSRA_VV_M2_MASK, VSRA_VV }, // 9332 |
| 30603 | { PseudoVSRA_VV_M4, VSRA_VV }, // 9333 |
| 30604 | { PseudoVSRA_VV_M4_MASK, VSRA_VV }, // 9334 |
| 30605 | { PseudoVSRA_VV_M8, VSRA_VV }, // 9335 |
| 30606 | { PseudoVSRA_VV_M8_MASK, VSRA_VV }, // 9336 |
| 30607 | { PseudoVSRA_VV_MF2, VSRA_VV }, // 9337 |
| 30608 | { PseudoVSRA_VV_MF2_MASK, VSRA_VV }, // 9338 |
| 30609 | { PseudoVSRA_VV_MF4, VSRA_VV }, // 9339 |
| 30610 | { PseudoVSRA_VV_MF4_MASK, VSRA_VV }, // 9340 |
| 30611 | { PseudoVSRA_VV_MF8, VSRA_VV }, // 9341 |
| 30612 | { PseudoVSRA_VV_MF8_MASK, VSRA_VV }, // 9342 |
| 30613 | { PseudoVSRA_VX_M1, VSRA_VX }, // 9343 |
| 30614 | { PseudoVSRA_VX_M1_MASK, VSRA_VX }, // 9344 |
| 30615 | { PseudoVSRA_VX_M2, VSRA_VX }, // 9345 |
| 30616 | { PseudoVSRA_VX_M2_MASK, VSRA_VX }, // 9346 |
| 30617 | { PseudoVSRA_VX_M4, VSRA_VX }, // 9347 |
| 30618 | { PseudoVSRA_VX_M4_MASK, VSRA_VX }, // 9348 |
| 30619 | { PseudoVSRA_VX_M8, VSRA_VX }, // 9349 |
| 30620 | { PseudoVSRA_VX_M8_MASK, VSRA_VX }, // 9350 |
| 30621 | { PseudoVSRA_VX_MF2, VSRA_VX }, // 9351 |
| 30622 | { PseudoVSRA_VX_MF2_MASK, VSRA_VX }, // 9352 |
| 30623 | { PseudoVSRA_VX_MF4, VSRA_VX }, // 9353 |
| 30624 | { PseudoVSRA_VX_MF4_MASK, VSRA_VX }, // 9354 |
| 30625 | { PseudoVSRA_VX_MF8, VSRA_VX }, // 9355 |
| 30626 | { PseudoVSRA_VX_MF8_MASK, VSRA_VX }, // 9356 |
| 30627 | { PseudoVSRL_VI_M1, VSRL_VI }, // 9357 |
| 30628 | { PseudoVSRL_VI_M1_MASK, VSRL_VI }, // 9358 |
| 30629 | { PseudoVSRL_VI_M2, VSRL_VI }, // 9359 |
| 30630 | { PseudoVSRL_VI_M2_MASK, VSRL_VI }, // 9360 |
| 30631 | { PseudoVSRL_VI_M4, VSRL_VI }, // 9361 |
| 30632 | { PseudoVSRL_VI_M4_MASK, VSRL_VI }, // 9362 |
| 30633 | { PseudoVSRL_VI_M8, VSRL_VI }, // 9363 |
| 30634 | { PseudoVSRL_VI_M8_MASK, VSRL_VI }, // 9364 |
| 30635 | { PseudoVSRL_VI_MF2, VSRL_VI }, // 9365 |
| 30636 | { PseudoVSRL_VI_MF2_MASK, VSRL_VI }, // 9366 |
| 30637 | { PseudoVSRL_VI_MF4, VSRL_VI }, // 9367 |
| 30638 | { PseudoVSRL_VI_MF4_MASK, VSRL_VI }, // 9368 |
| 30639 | { PseudoVSRL_VI_MF8, VSRL_VI }, // 9369 |
| 30640 | { PseudoVSRL_VI_MF8_MASK, VSRL_VI }, // 9370 |
| 30641 | { PseudoVSRL_VV_M1, VSRL_VV }, // 9371 |
| 30642 | { PseudoVSRL_VV_M1_MASK, VSRL_VV }, // 9372 |
| 30643 | { PseudoVSRL_VV_M2, VSRL_VV }, // 9373 |
| 30644 | { PseudoVSRL_VV_M2_MASK, VSRL_VV }, // 9374 |
| 30645 | { PseudoVSRL_VV_M4, VSRL_VV }, // 9375 |
| 30646 | { PseudoVSRL_VV_M4_MASK, VSRL_VV }, // 9376 |
| 30647 | { PseudoVSRL_VV_M8, VSRL_VV }, // 9377 |
| 30648 | { PseudoVSRL_VV_M8_MASK, VSRL_VV }, // 9378 |
| 30649 | { PseudoVSRL_VV_MF2, VSRL_VV }, // 9379 |
| 30650 | { PseudoVSRL_VV_MF2_MASK, VSRL_VV }, // 9380 |
| 30651 | { PseudoVSRL_VV_MF4, VSRL_VV }, // 9381 |
| 30652 | { PseudoVSRL_VV_MF4_MASK, VSRL_VV }, // 9382 |
| 30653 | { PseudoVSRL_VV_MF8, VSRL_VV }, // 9383 |
| 30654 | { PseudoVSRL_VV_MF8_MASK, VSRL_VV }, // 9384 |
| 30655 | { PseudoVSRL_VX_M1, VSRL_VX }, // 9385 |
| 30656 | { PseudoVSRL_VX_M1_MASK, VSRL_VX }, // 9386 |
| 30657 | { PseudoVSRL_VX_M2, VSRL_VX }, // 9387 |
| 30658 | { PseudoVSRL_VX_M2_MASK, VSRL_VX }, // 9388 |
| 30659 | { PseudoVSRL_VX_M4, VSRL_VX }, // 9389 |
| 30660 | { PseudoVSRL_VX_M4_MASK, VSRL_VX }, // 9390 |
| 30661 | { PseudoVSRL_VX_M8, VSRL_VX }, // 9391 |
| 30662 | { PseudoVSRL_VX_M8_MASK, VSRL_VX }, // 9392 |
| 30663 | { PseudoVSRL_VX_MF2, VSRL_VX }, // 9393 |
| 30664 | { PseudoVSRL_VX_MF2_MASK, VSRL_VX }, // 9394 |
| 30665 | { PseudoVSRL_VX_MF4, VSRL_VX }, // 9395 |
| 30666 | { PseudoVSRL_VX_MF4_MASK, VSRL_VX }, // 9396 |
| 30667 | { PseudoVSRL_VX_MF8, VSRL_VX }, // 9397 |
| 30668 | { PseudoVSRL_VX_MF8_MASK, VSRL_VX }, // 9398 |
| 30669 | { PseudoVSSE16_V_M1, VSSE16_V }, // 9399 |
| 30670 | { PseudoVSSE16_V_M1_MASK, VSSE16_V }, // 9400 |
| 30671 | { PseudoVSSE16_V_M2, VSSE16_V }, // 9401 |
| 30672 | { PseudoVSSE16_V_M2_MASK, VSSE16_V }, // 9402 |
| 30673 | { PseudoVSSE16_V_M4, VSSE16_V }, // 9403 |
| 30674 | { PseudoVSSE16_V_M4_MASK, VSSE16_V }, // 9404 |
| 30675 | { PseudoVSSE16_V_M8, VSSE16_V }, // 9405 |
| 30676 | { PseudoVSSE16_V_M8_MASK, VSSE16_V }, // 9406 |
| 30677 | { PseudoVSSE16_V_MF2, VSSE16_V }, // 9407 |
| 30678 | { PseudoVSSE16_V_MF2_MASK, VSSE16_V }, // 9408 |
| 30679 | { PseudoVSSE16_V_MF4, VSSE16_V }, // 9409 |
| 30680 | { PseudoVSSE16_V_MF4_MASK, VSSE16_V }, // 9410 |
| 30681 | { PseudoVSSE32_V_M1, VSSE32_V }, // 9411 |
| 30682 | { PseudoVSSE32_V_M1_MASK, VSSE32_V }, // 9412 |
| 30683 | { PseudoVSSE32_V_M2, VSSE32_V }, // 9413 |
| 30684 | { PseudoVSSE32_V_M2_MASK, VSSE32_V }, // 9414 |
| 30685 | { PseudoVSSE32_V_M4, VSSE32_V }, // 9415 |
| 30686 | { PseudoVSSE32_V_M4_MASK, VSSE32_V }, // 9416 |
| 30687 | { PseudoVSSE32_V_M8, VSSE32_V }, // 9417 |
| 30688 | { PseudoVSSE32_V_M8_MASK, VSSE32_V }, // 9418 |
| 30689 | { PseudoVSSE32_V_MF2, VSSE32_V }, // 9419 |
| 30690 | { PseudoVSSE32_V_MF2_MASK, VSSE32_V }, // 9420 |
| 30691 | { PseudoVSSE64_V_M1, VSSE64_V }, // 9421 |
| 30692 | { PseudoVSSE64_V_M1_MASK, VSSE64_V }, // 9422 |
| 30693 | { PseudoVSSE64_V_M2, VSSE64_V }, // 9423 |
| 30694 | { PseudoVSSE64_V_M2_MASK, VSSE64_V }, // 9424 |
| 30695 | { PseudoVSSE64_V_M4, VSSE64_V }, // 9425 |
| 30696 | { PseudoVSSE64_V_M4_MASK, VSSE64_V }, // 9426 |
| 30697 | { PseudoVSSE64_V_M8, VSSE64_V }, // 9427 |
| 30698 | { PseudoVSSE64_V_M8_MASK, VSSE64_V }, // 9428 |
| 30699 | { PseudoVSSE8_V_M1, VSSE8_V }, // 9429 |
| 30700 | { PseudoVSSE8_V_M1_MASK, VSSE8_V }, // 9430 |
| 30701 | { PseudoVSSE8_V_M2, VSSE8_V }, // 9431 |
| 30702 | { PseudoVSSE8_V_M2_MASK, VSSE8_V }, // 9432 |
| 30703 | { PseudoVSSE8_V_M4, VSSE8_V }, // 9433 |
| 30704 | { PseudoVSSE8_V_M4_MASK, VSSE8_V }, // 9434 |
| 30705 | { PseudoVSSE8_V_M8, VSSE8_V }, // 9435 |
| 30706 | { PseudoVSSE8_V_M8_MASK, VSSE8_V }, // 9436 |
| 30707 | { PseudoVSSE8_V_MF2, VSSE8_V }, // 9437 |
| 30708 | { PseudoVSSE8_V_MF2_MASK, VSSE8_V }, // 9438 |
| 30709 | { PseudoVSSE8_V_MF4, VSSE8_V }, // 9439 |
| 30710 | { PseudoVSSE8_V_MF4_MASK, VSSE8_V }, // 9440 |
| 30711 | { PseudoVSSE8_V_MF8, VSSE8_V }, // 9441 |
| 30712 | { PseudoVSSE8_V_MF8_MASK, VSSE8_V }, // 9442 |
| 30713 | { PseudoVSSEG2E16_V_M1, VSSEG2E16_V }, // 9443 |
| 30714 | { PseudoVSSEG2E16_V_M1_MASK, VSSEG2E16_V }, // 9444 |
| 30715 | { PseudoVSSEG2E16_V_M2, VSSEG2E16_V }, // 9445 |
| 30716 | { PseudoVSSEG2E16_V_M2_MASK, VSSEG2E16_V }, // 9446 |
| 30717 | { PseudoVSSEG2E16_V_M4, VSSEG2E16_V }, // 9447 |
| 30718 | { PseudoVSSEG2E16_V_M4_MASK, VSSEG2E16_V }, // 9448 |
| 30719 | { PseudoVSSEG2E16_V_MF2, VSSEG2E16_V }, // 9449 |
| 30720 | { PseudoVSSEG2E16_V_MF2_MASK, VSSEG2E16_V }, // 9450 |
| 30721 | { PseudoVSSEG2E16_V_MF4, VSSEG2E16_V }, // 9451 |
| 30722 | { PseudoVSSEG2E16_V_MF4_MASK, VSSEG2E16_V }, // 9452 |
| 30723 | { PseudoVSSEG2E32_V_M1, VSSEG2E32_V }, // 9453 |
| 30724 | { PseudoVSSEG2E32_V_M1_MASK, VSSEG2E32_V }, // 9454 |
| 30725 | { PseudoVSSEG2E32_V_M2, VSSEG2E32_V }, // 9455 |
| 30726 | { PseudoVSSEG2E32_V_M2_MASK, VSSEG2E32_V }, // 9456 |
| 30727 | { PseudoVSSEG2E32_V_M4, VSSEG2E32_V }, // 9457 |
| 30728 | { PseudoVSSEG2E32_V_M4_MASK, VSSEG2E32_V }, // 9458 |
| 30729 | { PseudoVSSEG2E32_V_MF2, VSSEG2E32_V }, // 9459 |
| 30730 | { PseudoVSSEG2E32_V_MF2_MASK, VSSEG2E32_V }, // 9460 |
| 30731 | { PseudoVSSEG2E64_V_M1, VSSEG2E64_V }, // 9461 |
| 30732 | { PseudoVSSEG2E64_V_M1_MASK, VSSEG2E64_V }, // 9462 |
| 30733 | { PseudoVSSEG2E64_V_M2, VSSEG2E64_V }, // 9463 |
| 30734 | { PseudoVSSEG2E64_V_M2_MASK, VSSEG2E64_V }, // 9464 |
| 30735 | { PseudoVSSEG2E64_V_M4, VSSEG2E64_V }, // 9465 |
| 30736 | { PseudoVSSEG2E64_V_M4_MASK, VSSEG2E64_V }, // 9466 |
| 30737 | { PseudoVSSEG2E8_V_M1, VSSEG2E8_V }, // 9467 |
| 30738 | { PseudoVSSEG2E8_V_M1_MASK, VSSEG2E8_V }, // 9468 |
| 30739 | { PseudoVSSEG2E8_V_M2, VSSEG2E8_V }, // 9469 |
| 30740 | { PseudoVSSEG2E8_V_M2_MASK, VSSEG2E8_V }, // 9470 |
| 30741 | { PseudoVSSEG2E8_V_M4, VSSEG2E8_V }, // 9471 |
| 30742 | { PseudoVSSEG2E8_V_M4_MASK, VSSEG2E8_V }, // 9472 |
| 30743 | { PseudoVSSEG2E8_V_MF2, VSSEG2E8_V }, // 9473 |
| 30744 | { PseudoVSSEG2E8_V_MF2_MASK, VSSEG2E8_V }, // 9474 |
| 30745 | { PseudoVSSEG2E8_V_MF4, VSSEG2E8_V }, // 9475 |
| 30746 | { PseudoVSSEG2E8_V_MF4_MASK, VSSEG2E8_V }, // 9476 |
| 30747 | { PseudoVSSEG2E8_V_MF8, VSSEG2E8_V }, // 9477 |
| 30748 | { PseudoVSSEG2E8_V_MF8_MASK, VSSEG2E8_V }, // 9478 |
| 30749 | { PseudoVSSEG3E16_V_M1, VSSEG3E16_V }, // 9479 |
| 30750 | { PseudoVSSEG3E16_V_M1_MASK, VSSEG3E16_V }, // 9480 |
| 30751 | { PseudoVSSEG3E16_V_M2, VSSEG3E16_V }, // 9481 |
| 30752 | { PseudoVSSEG3E16_V_M2_MASK, VSSEG3E16_V }, // 9482 |
| 30753 | { PseudoVSSEG3E16_V_MF2, VSSEG3E16_V }, // 9483 |
| 30754 | { PseudoVSSEG3E16_V_MF2_MASK, VSSEG3E16_V }, // 9484 |
| 30755 | { PseudoVSSEG3E16_V_MF4, VSSEG3E16_V }, // 9485 |
| 30756 | { PseudoVSSEG3E16_V_MF4_MASK, VSSEG3E16_V }, // 9486 |
| 30757 | { PseudoVSSEG3E32_V_M1, VSSEG3E32_V }, // 9487 |
| 30758 | { PseudoVSSEG3E32_V_M1_MASK, VSSEG3E32_V }, // 9488 |
| 30759 | { PseudoVSSEG3E32_V_M2, VSSEG3E32_V }, // 9489 |
| 30760 | { PseudoVSSEG3E32_V_M2_MASK, VSSEG3E32_V }, // 9490 |
| 30761 | { PseudoVSSEG3E32_V_MF2, VSSEG3E32_V }, // 9491 |
| 30762 | { PseudoVSSEG3E32_V_MF2_MASK, VSSEG3E32_V }, // 9492 |
| 30763 | { PseudoVSSEG3E64_V_M1, VSSEG3E64_V }, // 9493 |
| 30764 | { PseudoVSSEG3E64_V_M1_MASK, VSSEG3E64_V }, // 9494 |
| 30765 | { PseudoVSSEG3E64_V_M2, VSSEG3E64_V }, // 9495 |
| 30766 | { PseudoVSSEG3E64_V_M2_MASK, VSSEG3E64_V }, // 9496 |
| 30767 | { PseudoVSSEG3E8_V_M1, VSSEG3E8_V }, // 9497 |
| 30768 | { PseudoVSSEG3E8_V_M1_MASK, VSSEG3E8_V }, // 9498 |
| 30769 | { PseudoVSSEG3E8_V_M2, VSSEG3E8_V }, // 9499 |
| 30770 | { PseudoVSSEG3E8_V_M2_MASK, VSSEG3E8_V }, // 9500 |
| 30771 | { PseudoVSSEG3E8_V_MF2, VSSEG3E8_V }, // 9501 |
| 30772 | { PseudoVSSEG3E8_V_MF2_MASK, VSSEG3E8_V }, // 9502 |
| 30773 | { PseudoVSSEG3E8_V_MF4, VSSEG3E8_V }, // 9503 |
| 30774 | { PseudoVSSEG3E8_V_MF4_MASK, VSSEG3E8_V }, // 9504 |
| 30775 | { PseudoVSSEG3E8_V_MF8, VSSEG3E8_V }, // 9505 |
| 30776 | { PseudoVSSEG3E8_V_MF8_MASK, VSSEG3E8_V }, // 9506 |
| 30777 | { PseudoVSSEG4E16_V_M1, VSSEG4E16_V }, // 9507 |
| 30778 | { PseudoVSSEG4E16_V_M1_MASK, VSSEG4E16_V }, // 9508 |
| 30779 | { PseudoVSSEG4E16_V_M2, VSSEG4E16_V }, // 9509 |
| 30780 | { PseudoVSSEG4E16_V_M2_MASK, VSSEG4E16_V }, // 9510 |
| 30781 | { PseudoVSSEG4E16_V_MF2, VSSEG4E16_V }, // 9511 |
| 30782 | { PseudoVSSEG4E16_V_MF2_MASK, VSSEG4E16_V }, // 9512 |
| 30783 | { PseudoVSSEG4E16_V_MF4, VSSEG4E16_V }, // 9513 |
| 30784 | { PseudoVSSEG4E16_V_MF4_MASK, VSSEG4E16_V }, // 9514 |
| 30785 | { PseudoVSSEG4E32_V_M1, VSSEG4E32_V }, // 9515 |
| 30786 | { PseudoVSSEG4E32_V_M1_MASK, VSSEG4E32_V }, // 9516 |
| 30787 | { PseudoVSSEG4E32_V_M2, VSSEG4E32_V }, // 9517 |
| 30788 | { PseudoVSSEG4E32_V_M2_MASK, VSSEG4E32_V }, // 9518 |
| 30789 | { PseudoVSSEG4E32_V_MF2, VSSEG4E32_V }, // 9519 |
| 30790 | { PseudoVSSEG4E32_V_MF2_MASK, VSSEG4E32_V }, // 9520 |
| 30791 | { PseudoVSSEG4E64_V_M1, VSSEG4E64_V }, // 9521 |
| 30792 | { PseudoVSSEG4E64_V_M1_MASK, VSSEG4E64_V }, // 9522 |
| 30793 | { PseudoVSSEG4E64_V_M2, VSSEG4E64_V }, // 9523 |
| 30794 | { PseudoVSSEG4E64_V_M2_MASK, VSSEG4E64_V }, // 9524 |
| 30795 | { PseudoVSSEG4E8_V_M1, VSSEG4E8_V }, // 9525 |
| 30796 | { PseudoVSSEG4E8_V_M1_MASK, VSSEG4E8_V }, // 9526 |
| 30797 | { PseudoVSSEG4E8_V_M2, VSSEG4E8_V }, // 9527 |
| 30798 | { PseudoVSSEG4E8_V_M2_MASK, VSSEG4E8_V }, // 9528 |
| 30799 | { PseudoVSSEG4E8_V_MF2, VSSEG4E8_V }, // 9529 |
| 30800 | { PseudoVSSEG4E8_V_MF2_MASK, VSSEG4E8_V }, // 9530 |
| 30801 | { PseudoVSSEG4E8_V_MF4, VSSEG4E8_V }, // 9531 |
| 30802 | { PseudoVSSEG4E8_V_MF4_MASK, VSSEG4E8_V }, // 9532 |
| 30803 | { PseudoVSSEG4E8_V_MF8, VSSEG4E8_V }, // 9533 |
| 30804 | { PseudoVSSEG4E8_V_MF8_MASK, VSSEG4E8_V }, // 9534 |
| 30805 | { PseudoVSSEG5E16_V_M1, VSSEG5E16_V }, // 9535 |
| 30806 | { PseudoVSSEG5E16_V_M1_MASK, VSSEG5E16_V }, // 9536 |
| 30807 | { PseudoVSSEG5E16_V_MF2, VSSEG5E16_V }, // 9537 |
| 30808 | { PseudoVSSEG5E16_V_MF2_MASK, VSSEG5E16_V }, // 9538 |
| 30809 | { PseudoVSSEG5E16_V_MF4, VSSEG5E16_V }, // 9539 |
| 30810 | { PseudoVSSEG5E16_V_MF4_MASK, VSSEG5E16_V }, // 9540 |
| 30811 | { PseudoVSSEG5E32_V_M1, VSSEG5E32_V }, // 9541 |
| 30812 | { PseudoVSSEG5E32_V_M1_MASK, VSSEG5E32_V }, // 9542 |
| 30813 | { PseudoVSSEG5E32_V_MF2, VSSEG5E32_V }, // 9543 |
| 30814 | { PseudoVSSEG5E32_V_MF2_MASK, VSSEG5E32_V }, // 9544 |
| 30815 | { PseudoVSSEG5E64_V_M1, VSSEG5E64_V }, // 9545 |
| 30816 | { PseudoVSSEG5E64_V_M1_MASK, VSSEG5E64_V }, // 9546 |
| 30817 | { PseudoVSSEG5E8_V_M1, VSSEG5E8_V }, // 9547 |
| 30818 | { PseudoVSSEG5E8_V_M1_MASK, VSSEG5E8_V }, // 9548 |
| 30819 | { PseudoVSSEG5E8_V_MF2, VSSEG5E8_V }, // 9549 |
| 30820 | { PseudoVSSEG5E8_V_MF2_MASK, VSSEG5E8_V }, // 9550 |
| 30821 | { PseudoVSSEG5E8_V_MF4, VSSEG5E8_V }, // 9551 |
| 30822 | { PseudoVSSEG5E8_V_MF4_MASK, VSSEG5E8_V }, // 9552 |
| 30823 | { PseudoVSSEG5E8_V_MF8, VSSEG5E8_V }, // 9553 |
| 30824 | { PseudoVSSEG5E8_V_MF8_MASK, VSSEG5E8_V }, // 9554 |
| 30825 | { PseudoVSSEG6E16_V_M1, VSSEG6E16_V }, // 9555 |
| 30826 | { PseudoVSSEG6E16_V_M1_MASK, VSSEG6E16_V }, // 9556 |
| 30827 | { PseudoVSSEG6E16_V_MF2, VSSEG6E16_V }, // 9557 |
| 30828 | { PseudoVSSEG6E16_V_MF2_MASK, VSSEG6E16_V }, // 9558 |
| 30829 | { PseudoVSSEG6E16_V_MF4, VSSEG6E16_V }, // 9559 |
| 30830 | { PseudoVSSEG6E16_V_MF4_MASK, VSSEG6E16_V }, // 9560 |
| 30831 | { PseudoVSSEG6E32_V_M1, VSSEG6E32_V }, // 9561 |
| 30832 | { PseudoVSSEG6E32_V_M1_MASK, VSSEG6E32_V }, // 9562 |
| 30833 | { PseudoVSSEG6E32_V_MF2, VSSEG6E32_V }, // 9563 |
| 30834 | { PseudoVSSEG6E32_V_MF2_MASK, VSSEG6E32_V }, // 9564 |
| 30835 | { PseudoVSSEG6E64_V_M1, VSSEG6E64_V }, // 9565 |
| 30836 | { PseudoVSSEG6E64_V_M1_MASK, VSSEG6E64_V }, // 9566 |
| 30837 | { PseudoVSSEG6E8_V_M1, VSSEG6E8_V }, // 9567 |
| 30838 | { PseudoVSSEG6E8_V_M1_MASK, VSSEG6E8_V }, // 9568 |
| 30839 | { PseudoVSSEG6E8_V_MF2, VSSEG6E8_V }, // 9569 |
| 30840 | { PseudoVSSEG6E8_V_MF2_MASK, VSSEG6E8_V }, // 9570 |
| 30841 | { PseudoVSSEG6E8_V_MF4, VSSEG6E8_V }, // 9571 |
| 30842 | { PseudoVSSEG6E8_V_MF4_MASK, VSSEG6E8_V }, // 9572 |
| 30843 | { PseudoVSSEG6E8_V_MF8, VSSEG6E8_V }, // 9573 |
| 30844 | { PseudoVSSEG6E8_V_MF8_MASK, VSSEG6E8_V }, // 9574 |
| 30845 | { PseudoVSSEG7E16_V_M1, VSSEG7E16_V }, // 9575 |
| 30846 | { PseudoVSSEG7E16_V_M1_MASK, VSSEG7E16_V }, // 9576 |
| 30847 | { PseudoVSSEG7E16_V_MF2, VSSEG7E16_V }, // 9577 |
| 30848 | { PseudoVSSEG7E16_V_MF2_MASK, VSSEG7E16_V }, // 9578 |
| 30849 | { PseudoVSSEG7E16_V_MF4, VSSEG7E16_V }, // 9579 |
| 30850 | { PseudoVSSEG7E16_V_MF4_MASK, VSSEG7E16_V }, // 9580 |
| 30851 | { PseudoVSSEG7E32_V_M1, VSSEG7E32_V }, // 9581 |
| 30852 | { PseudoVSSEG7E32_V_M1_MASK, VSSEG7E32_V }, // 9582 |
| 30853 | { PseudoVSSEG7E32_V_MF2, VSSEG7E32_V }, // 9583 |
| 30854 | { PseudoVSSEG7E32_V_MF2_MASK, VSSEG7E32_V }, // 9584 |
| 30855 | { PseudoVSSEG7E64_V_M1, VSSEG7E64_V }, // 9585 |
| 30856 | { PseudoVSSEG7E64_V_M1_MASK, VSSEG7E64_V }, // 9586 |
| 30857 | { PseudoVSSEG7E8_V_M1, VSSEG7E8_V }, // 9587 |
| 30858 | { PseudoVSSEG7E8_V_M1_MASK, VSSEG7E8_V }, // 9588 |
| 30859 | { PseudoVSSEG7E8_V_MF2, VSSEG7E8_V }, // 9589 |
| 30860 | { PseudoVSSEG7E8_V_MF2_MASK, VSSEG7E8_V }, // 9590 |
| 30861 | { PseudoVSSEG7E8_V_MF4, VSSEG7E8_V }, // 9591 |
| 30862 | { PseudoVSSEG7E8_V_MF4_MASK, VSSEG7E8_V }, // 9592 |
| 30863 | { PseudoVSSEG7E8_V_MF8, VSSEG7E8_V }, // 9593 |
| 30864 | { PseudoVSSEG7E8_V_MF8_MASK, VSSEG7E8_V }, // 9594 |
| 30865 | { PseudoVSSEG8E16_V_M1, VSSEG8E16_V }, // 9595 |
| 30866 | { PseudoVSSEG8E16_V_M1_MASK, VSSEG8E16_V }, // 9596 |
| 30867 | { PseudoVSSEG8E16_V_MF2, VSSEG8E16_V }, // 9597 |
| 30868 | { PseudoVSSEG8E16_V_MF2_MASK, VSSEG8E16_V }, // 9598 |
| 30869 | { PseudoVSSEG8E16_V_MF4, VSSEG8E16_V }, // 9599 |
| 30870 | { PseudoVSSEG8E16_V_MF4_MASK, VSSEG8E16_V }, // 9600 |
| 30871 | { PseudoVSSEG8E32_V_M1, VSSEG8E32_V }, // 9601 |
| 30872 | { PseudoVSSEG8E32_V_M1_MASK, VSSEG8E32_V }, // 9602 |
| 30873 | { PseudoVSSEG8E32_V_MF2, VSSEG8E32_V }, // 9603 |
| 30874 | { PseudoVSSEG8E32_V_MF2_MASK, VSSEG8E32_V }, // 9604 |
| 30875 | { PseudoVSSEG8E64_V_M1, VSSEG8E64_V }, // 9605 |
| 30876 | { PseudoVSSEG8E64_V_M1_MASK, VSSEG8E64_V }, // 9606 |
| 30877 | { PseudoVSSEG8E8_V_M1, VSSEG8E8_V }, // 9607 |
| 30878 | { PseudoVSSEG8E8_V_M1_MASK, VSSEG8E8_V }, // 9608 |
| 30879 | { PseudoVSSEG8E8_V_MF2, VSSEG8E8_V }, // 9609 |
| 30880 | { PseudoVSSEG8E8_V_MF2_MASK, VSSEG8E8_V }, // 9610 |
| 30881 | { PseudoVSSEG8E8_V_MF4, VSSEG8E8_V }, // 9611 |
| 30882 | { PseudoVSSEG8E8_V_MF4_MASK, VSSEG8E8_V }, // 9612 |
| 30883 | { PseudoVSSEG8E8_V_MF8, VSSEG8E8_V }, // 9613 |
| 30884 | { PseudoVSSEG8E8_V_MF8_MASK, VSSEG8E8_V }, // 9614 |
| 30885 | { PseudoVSSRA_VI_M1, VSSRA_VI }, // 9615 |
| 30886 | { PseudoVSSRA_VI_M1_MASK, VSSRA_VI }, // 9616 |
| 30887 | { PseudoVSSRA_VI_M2, VSSRA_VI }, // 9617 |
| 30888 | { PseudoVSSRA_VI_M2_MASK, VSSRA_VI }, // 9618 |
| 30889 | { PseudoVSSRA_VI_M4, VSSRA_VI }, // 9619 |
| 30890 | { PseudoVSSRA_VI_M4_MASK, VSSRA_VI }, // 9620 |
| 30891 | { PseudoVSSRA_VI_M8, VSSRA_VI }, // 9621 |
| 30892 | { PseudoVSSRA_VI_M8_MASK, VSSRA_VI }, // 9622 |
| 30893 | { PseudoVSSRA_VI_MF2, VSSRA_VI }, // 9623 |
| 30894 | { PseudoVSSRA_VI_MF2_MASK, VSSRA_VI }, // 9624 |
| 30895 | { PseudoVSSRA_VI_MF4, VSSRA_VI }, // 9625 |
| 30896 | { PseudoVSSRA_VI_MF4_MASK, VSSRA_VI }, // 9626 |
| 30897 | { PseudoVSSRA_VI_MF8, VSSRA_VI }, // 9627 |
| 30898 | { PseudoVSSRA_VI_MF8_MASK, VSSRA_VI }, // 9628 |
| 30899 | { PseudoVSSRA_VV_M1, VSSRA_VV }, // 9629 |
| 30900 | { PseudoVSSRA_VV_M1_MASK, VSSRA_VV }, // 9630 |
| 30901 | { PseudoVSSRA_VV_M2, VSSRA_VV }, // 9631 |
| 30902 | { PseudoVSSRA_VV_M2_MASK, VSSRA_VV }, // 9632 |
| 30903 | { PseudoVSSRA_VV_M4, VSSRA_VV }, // 9633 |
| 30904 | { PseudoVSSRA_VV_M4_MASK, VSSRA_VV }, // 9634 |
| 30905 | { PseudoVSSRA_VV_M8, VSSRA_VV }, // 9635 |
| 30906 | { PseudoVSSRA_VV_M8_MASK, VSSRA_VV }, // 9636 |
| 30907 | { PseudoVSSRA_VV_MF2, VSSRA_VV }, // 9637 |
| 30908 | { PseudoVSSRA_VV_MF2_MASK, VSSRA_VV }, // 9638 |
| 30909 | { PseudoVSSRA_VV_MF4, VSSRA_VV }, // 9639 |
| 30910 | { PseudoVSSRA_VV_MF4_MASK, VSSRA_VV }, // 9640 |
| 30911 | { PseudoVSSRA_VV_MF8, VSSRA_VV }, // 9641 |
| 30912 | { PseudoVSSRA_VV_MF8_MASK, VSSRA_VV }, // 9642 |
| 30913 | { PseudoVSSRA_VX_M1, VSSRA_VX }, // 9643 |
| 30914 | { PseudoVSSRA_VX_M1_MASK, VSSRA_VX }, // 9644 |
| 30915 | { PseudoVSSRA_VX_M2, VSSRA_VX }, // 9645 |
| 30916 | { PseudoVSSRA_VX_M2_MASK, VSSRA_VX }, // 9646 |
| 30917 | { PseudoVSSRA_VX_M4, VSSRA_VX }, // 9647 |
| 30918 | { PseudoVSSRA_VX_M4_MASK, VSSRA_VX }, // 9648 |
| 30919 | { PseudoVSSRA_VX_M8, VSSRA_VX }, // 9649 |
| 30920 | { PseudoVSSRA_VX_M8_MASK, VSSRA_VX }, // 9650 |
| 30921 | { PseudoVSSRA_VX_MF2, VSSRA_VX }, // 9651 |
| 30922 | { PseudoVSSRA_VX_MF2_MASK, VSSRA_VX }, // 9652 |
| 30923 | { PseudoVSSRA_VX_MF4, VSSRA_VX }, // 9653 |
| 30924 | { PseudoVSSRA_VX_MF4_MASK, VSSRA_VX }, // 9654 |
| 30925 | { PseudoVSSRA_VX_MF8, VSSRA_VX }, // 9655 |
| 30926 | { PseudoVSSRA_VX_MF8_MASK, VSSRA_VX }, // 9656 |
| 30927 | { PseudoVSSRL_VI_M1, VSSRL_VI }, // 9657 |
| 30928 | { PseudoVSSRL_VI_M1_MASK, VSSRL_VI }, // 9658 |
| 30929 | { PseudoVSSRL_VI_M2, VSSRL_VI }, // 9659 |
| 30930 | { PseudoVSSRL_VI_M2_MASK, VSSRL_VI }, // 9660 |
| 30931 | { PseudoVSSRL_VI_M4, VSSRL_VI }, // 9661 |
| 30932 | { PseudoVSSRL_VI_M4_MASK, VSSRL_VI }, // 9662 |
| 30933 | { PseudoVSSRL_VI_M8, VSSRL_VI }, // 9663 |
| 30934 | { PseudoVSSRL_VI_M8_MASK, VSSRL_VI }, // 9664 |
| 30935 | { PseudoVSSRL_VI_MF2, VSSRL_VI }, // 9665 |
| 30936 | { PseudoVSSRL_VI_MF2_MASK, VSSRL_VI }, // 9666 |
| 30937 | { PseudoVSSRL_VI_MF4, VSSRL_VI }, // 9667 |
| 30938 | { PseudoVSSRL_VI_MF4_MASK, VSSRL_VI }, // 9668 |
| 30939 | { PseudoVSSRL_VI_MF8, VSSRL_VI }, // 9669 |
| 30940 | { PseudoVSSRL_VI_MF8_MASK, VSSRL_VI }, // 9670 |
| 30941 | { PseudoVSSRL_VV_M1, VSSRL_VV }, // 9671 |
| 30942 | { PseudoVSSRL_VV_M1_MASK, VSSRL_VV }, // 9672 |
| 30943 | { PseudoVSSRL_VV_M2, VSSRL_VV }, // 9673 |
| 30944 | { PseudoVSSRL_VV_M2_MASK, VSSRL_VV }, // 9674 |
| 30945 | { PseudoVSSRL_VV_M4, VSSRL_VV }, // 9675 |
| 30946 | { PseudoVSSRL_VV_M4_MASK, VSSRL_VV }, // 9676 |
| 30947 | { PseudoVSSRL_VV_M8, VSSRL_VV }, // 9677 |
| 30948 | { PseudoVSSRL_VV_M8_MASK, VSSRL_VV }, // 9678 |
| 30949 | { PseudoVSSRL_VV_MF2, VSSRL_VV }, // 9679 |
| 30950 | { PseudoVSSRL_VV_MF2_MASK, VSSRL_VV }, // 9680 |
| 30951 | { PseudoVSSRL_VV_MF4, VSSRL_VV }, // 9681 |
| 30952 | { PseudoVSSRL_VV_MF4_MASK, VSSRL_VV }, // 9682 |
| 30953 | { PseudoVSSRL_VV_MF8, VSSRL_VV }, // 9683 |
| 30954 | { PseudoVSSRL_VV_MF8_MASK, VSSRL_VV }, // 9684 |
| 30955 | { PseudoVSSRL_VX_M1, VSSRL_VX }, // 9685 |
| 30956 | { PseudoVSSRL_VX_M1_MASK, VSSRL_VX }, // 9686 |
| 30957 | { PseudoVSSRL_VX_M2, VSSRL_VX }, // 9687 |
| 30958 | { PseudoVSSRL_VX_M2_MASK, VSSRL_VX }, // 9688 |
| 30959 | { PseudoVSSRL_VX_M4, VSSRL_VX }, // 9689 |
| 30960 | { PseudoVSSRL_VX_M4_MASK, VSSRL_VX }, // 9690 |
| 30961 | { PseudoVSSRL_VX_M8, VSSRL_VX }, // 9691 |
| 30962 | { PseudoVSSRL_VX_M8_MASK, VSSRL_VX }, // 9692 |
| 30963 | { PseudoVSSRL_VX_MF2, VSSRL_VX }, // 9693 |
| 30964 | { PseudoVSSRL_VX_MF2_MASK, VSSRL_VX }, // 9694 |
| 30965 | { PseudoVSSRL_VX_MF4, VSSRL_VX }, // 9695 |
| 30966 | { PseudoVSSRL_VX_MF4_MASK, VSSRL_VX }, // 9696 |
| 30967 | { PseudoVSSRL_VX_MF8, VSSRL_VX }, // 9697 |
| 30968 | { PseudoVSSRL_VX_MF8_MASK, VSSRL_VX }, // 9698 |
| 30969 | { PseudoVSSSEG2E16_V_M1, VSSSEG2E16_V }, // 9699 |
| 30970 | { PseudoVSSSEG2E16_V_M1_MASK, VSSSEG2E16_V }, // 9700 |
| 30971 | { PseudoVSSSEG2E16_V_M2, VSSSEG2E16_V }, // 9701 |
| 30972 | { PseudoVSSSEG2E16_V_M2_MASK, VSSSEG2E16_V }, // 9702 |
| 30973 | { PseudoVSSSEG2E16_V_M4, VSSSEG2E16_V }, // 9703 |
| 30974 | { PseudoVSSSEG2E16_V_M4_MASK, VSSSEG2E16_V }, // 9704 |
| 30975 | { PseudoVSSSEG2E16_V_MF2, VSSSEG2E16_V }, // 9705 |
| 30976 | { PseudoVSSSEG2E16_V_MF2_MASK, VSSSEG2E16_V }, // 9706 |
| 30977 | { PseudoVSSSEG2E16_V_MF4, VSSSEG2E16_V }, // 9707 |
| 30978 | { PseudoVSSSEG2E16_V_MF4_MASK, VSSSEG2E16_V }, // 9708 |
| 30979 | { PseudoVSSSEG2E32_V_M1, VSSSEG2E32_V }, // 9709 |
| 30980 | { PseudoVSSSEG2E32_V_M1_MASK, VSSSEG2E32_V }, // 9710 |
| 30981 | { PseudoVSSSEG2E32_V_M2, VSSSEG2E32_V }, // 9711 |
| 30982 | { PseudoVSSSEG2E32_V_M2_MASK, VSSSEG2E32_V }, // 9712 |
| 30983 | { PseudoVSSSEG2E32_V_M4, VSSSEG2E32_V }, // 9713 |
| 30984 | { PseudoVSSSEG2E32_V_M4_MASK, VSSSEG2E32_V }, // 9714 |
| 30985 | { PseudoVSSSEG2E32_V_MF2, VSSSEG2E32_V }, // 9715 |
| 30986 | { PseudoVSSSEG2E32_V_MF2_MASK, VSSSEG2E32_V }, // 9716 |
| 30987 | { PseudoVSSSEG2E64_V_M1, VSSSEG2E64_V }, // 9717 |
| 30988 | { PseudoVSSSEG2E64_V_M1_MASK, VSSSEG2E64_V }, // 9718 |
| 30989 | { PseudoVSSSEG2E64_V_M2, VSSSEG2E64_V }, // 9719 |
| 30990 | { PseudoVSSSEG2E64_V_M2_MASK, VSSSEG2E64_V }, // 9720 |
| 30991 | { PseudoVSSSEG2E64_V_M4, VSSSEG2E64_V }, // 9721 |
| 30992 | { PseudoVSSSEG2E64_V_M4_MASK, VSSSEG2E64_V }, // 9722 |
| 30993 | { PseudoVSSSEG2E8_V_M1, VSSSEG2E8_V }, // 9723 |
| 30994 | { PseudoVSSSEG2E8_V_M1_MASK, VSSSEG2E8_V }, // 9724 |
| 30995 | { PseudoVSSSEG2E8_V_M2, VSSSEG2E8_V }, // 9725 |
| 30996 | { PseudoVSSSEG2E8_V_M2_MASK, VSSSEG2E8_V }, // 9726 |
| 30997 | { PseudoVSSSEG2E8_V_M4, VSSSEG2E8_V }, // 9727 |
| 30998 | { PseudoVSSSEG2E8_V_M4_MASK, VSSSEG2E8_V }, // 9728 |
| 30999 | { PseudoVSSSEG2E8_V_MF2, VSSSEG2E8_V }, // 9729 |
| 31000 | { PseudoVSSSEG2E8_V_MF2_MASK, VSSSEG2E8_V }, // 9730 |
| 31001 | { PseudoVSSSEG2E8_V_MF4, VSSSEG2E8_V }, // 9731 |
| 31002 | { PseudoVSSSEG2E8_V_MF4_MASK, VSSSEG2E8_V }, // 9732 |
| 31003 | { PseudoVSSSEG2E8_V_MF8, VSSSEG2E8_V }, // 9733 |
| 31004 | { PseudoVSSSEG2E8_V_MF8_MASK, VSSSEG2E8_V }, // 9734 |
| 31005 | { PseudoVSSSEG3E16_V_M1, VSSSEG3E16_V }, // 9735 |
| 31006 | { PseudoVSSSEG3E16_V_M1_MASK, VSSSEG3E16_V }, // 9736 |
| 31007 | { PseudoVSSSEG3E16_V_M2, VSSSEG3E16_V }, // 9737 |
| 31008 | { PseudoVSSSEG3E16_V_M2_MASK, VSSSEG3E16_V }, // 9738 |
| 31009 | { PseudoVSSSEG3E16_V_MF2, VSSSEG3E16_V }, // 9739 |
| 31010 | { PseudoVSSSEG3E16_V_MF2_MASK, VSSSEG3E16_V }, // 9740 |
| 31011 | { PseudoVSSSEG3E16_V_MF4, VSSSEG3E16_V }, // 9741 |
| 31012 | { PseudoVSSSEG3E16_V_MF4_MASK, VSSSEG3E16_V }, // 9742 |
| 31013 | { PseudoVSSSEG3E32_V_M1, VSSSEG3E32_V }, // 9743 |
| 31014 | { PseudoVSSSEG3E32_V_M1_MASK, VSSSEG3E32_V }, // 9744 |
| 31015 | { PseudoVSSSEG3E32_V_M2, VSSSEG3E32_V }, // 9745 |
| 31016 | { PseudoVSSSEG3E32_V_M2_MASK, VSSSEG3E32_V }, // 9746 |
| 31017 | { PseudoVSSSEG3E32_V_MF2, VSSSEG3E32_V }, // 9747 |
| 31018 | { PseudoVSSSEG3E32_V_MF2_MASK, VSSSEG3E32_V }, // 9748 |
| 31019 | { PseudoVSSSEG3E64_V_M1, VSSSEG3E64_V }, // 9749 |
| 31020 | { PseudoVSSSEG3E64_V_M1_MASK, VSSSEG3E64_V }, // 9750 |
| 31021 | { PseudoVSSSEG3E64_V_M2, VSSSEG3E64_V }, // 9751 |
| 31022 | { PseudoVSSSEG3E64_V_M2_MASK, VSSSEG3E64_V }, // 9752 |
| 31023 | { PseudoVSSSEG3E8_V_M1, VSSSEG3E8_V }, // 9753 |
| 31024 | { PseudoVSSSEG3E8_V_M1_MASK, VSSSEG3E8_V }, // 9754 |
| 31025 | { PseudoVSSSEG3E8_V_M2, VSSSEG3E8_V }, // 9755 |
| 31026 | { PseudoVSSSEG3E8_V_M2_MASK, VSSSEG3E8_V }, // 9756 |
| 31027 | { PseudoVSSSEG3E8_V_MF2, VSSSEG3E8_V }, // 9757 |
| 31028 | { PseudoVSSSEG3E8_V_MF2_MASK, VSSSEG3E8_V }, // 9758 |
| 31029 | { PseudoVSSSEG3E8_V_MF4, VSSSEG3E8_V }, // 9759 |
| 31030 | { PseudoVSSSEG3E8_V_MF4_MASK, VSSSEG3E8_V }, // 9760 |
| 31031 | { PseudoVSSSEG3E8_V_MF8, VSSSEG3E8_V }, // 9761 |
| 31032 | { PseudoVSSSEG3E8_V_MF8_MASK, VSSSEG3E8_V }, // 9762 |
| 31033 | { PseudoVSSSEG4E16_V_M1, VSSSEG4E16_V }, // 9763 |
| 31034 | { PseudoVSSSEG4E16_V_M1_MASK, VSSSEG4E16_V }, // 9764 |
| 31035 | { PseudoVSSSEG4E16_V_M2, VSSSEG4E16_V }, // 9765 |
| 31036 | { PseudoVSSSEG4E16_V_M2_MASK, VSSSEG4E16_V }, // 9766 |
| 31037 | { PseudoVSSSEG4E16_V_MF2, VSSSEG4E16_V }, // 9767 |
| 31038 | { PseudoVSSSEG4E16_V_MF2_MASK, VSSSEG4E16_V }, // 9768 |
| 31039 | { PseudoVSSSEG4E16_V_MF4, VSSSEG4E16_V }, // 9769 |
| 31040 | { PseudoVSSSEG4E16_V_MF4_MASK, VSSSEG4E16_V }, // 9770 |
| 31041 | { PseudoVSSSEG4E32_V_M1, VSSSEG4E32_V }, // 9771 |
| 31042 | { PseudoVSSSEG4E32_V_M1_MASK, VSSSEG4E32_V }, // 9772 |
| 31043 | { PseudoVSSSEG4E32_V_M2, VSSSEG4E32_V }, // 9773 |
| 31044 | { PseudoVSSSEG4E32_V_M2_MASK, VSSSEG4E32_V }, // 9774 |
| 31045 | { PseudoVSSSEG4E32_V_MF2, VSSSEG4E32_V }, // 9775 |
| 31046 | { PseudoVSSSEG4E32_V_MF2_MASK, VSSSEG4E32_V }, // 9776 |
| 31047 | { PseudoVSSSEG4E64_V_M1, VSSSEG4E64_V }, // 9777 |
| 31048 | { PseudoVSSSEG4E64_V_M1_MASK, VSSSEG4E64_V }, // 9778 |
| 31049 | { PseudoVSSSEG4E64_V_M2, VSSSEG4E64_V }, // 9779 |
| 31050 | { PseudoVSSSEG4E64_V_M2_MASK, VSSSEG4E64_V }, // 9780 |
| 31051 | { PseudoVSSSEG4E8_V_M1, VSSSEG4E8_V }, // 9781 |
| 31052 | { PseudoVSSSEG4E8_V_M1_MASK, VSSSEG4E8_V }, // 9782 |
| 31053 | { PseudoVSSSEG4E8_V_M2, VSSSEG4E8_V }, // 9783 |
| 31054 | { PseudoVSSSEG4E8_V_M2_MASK, VSSSEG4E8_V }, // 9784 |
| 31055 | { PseudoVSSSEG4E8_V_MF2, VSSSEG4E8_V }, // 9785 |
| 31056 | { PseudoVSSSEG4E8_V_MF2_MASK, VSSSEG4E8_V }, // 9786 |
| 31057 | { PseudoVSSSEG4E8_V_MF4, VSSSEG4E8_V }, // 9787 |
| 31058 | { PseudoVSSSEG4E8_V_MF4_MASK, VSSSEG4E8_V }, // 9788 |
| 31059 | { PseudoVSSSEG4E8_V_MF8, VSSSEG4E8_V }, // 9789 |
| 31060 | { PseudoVSSSEG4E8_V_MF8_MASK, VSSSEG4E8_V }, // 9790 |
| 31061 | { PseudoVSSSEG5E16_V_M1, VSSSEG5E16_V }, // 9791 |
| 31062 | { PseudoVSSSEG5E16_V_M1_MASK, VSSSEG5E16_V }, // 9792 |
| 31063 | { PseudoVSSSEG5E16_V_MF2, VSSSEG5E16_V }, // 9793 |
| 31064 | { PseudoVSSSEG5E16_V_MF2_MASK, VSSSEG5E16_V }, // 9794 |
| 31065 | { PseudoVSSSEG5E16_V_MF4, VSSSEG5E16_V }, // 9795 |
| 31066 | { PseudoVSSSEG5E16_V_MF4_MASK, VSSSEG5E16_V }, // 9796 |
| 31067 | { PseudoVSSSEG5E32_V_M1, VSSSEG5E32_V }, // 9797 |
| 31068 | { PseudoVSSSEG5E32_V_M1_MASK, VSSSEG5E32_V }, // 9798 |
| 31069 | { PseudoVSSSEG5E32_V_MF2, VSSSEG5E32_V }, // 9799 |
| 31070 | { PseudoVSSSEG5E32_V_MF2_MASK, VSSSEG5E32_V }, // 9800 |
| 31071 | { PseudoVSSSEG5E64_V_M1, VSSSEG5E64_V }, // 9801 |
| 31072 | { PseudoVSSSEG5E64_V_M1_MASK, VSSSEG5E64_V }, // 9802 |
| 31073 | { PseudoVSSSEG5E8_V_M1, VSSSEG5E8_V }, // 9803 |
| 31074 | { PseudoVSSSEG5E8_V_M1_MASK, VSSSEG5E8_V }, // 9804 |
| 31075 | { PseudoVSSSEG5E8_V_MF2, VSSSEG5E8_V }, // 9805 |
| 31076 | { PseudoVSSSEG5E8_V_MF2_MASK, VSSSEG5E8_V }, // 9806 |
| 31077 | { PseudoVSSSEG5E8_V_MF4, VSSSEG5E8_V }, // 9807 |
| 31078 | { PseudoVSSSEG5E8_V_MF4_MASK, VSSSEG5E8_V }, // 9808 |
| 31079 | { PseudoVSSSEG5E8_V_MF8, VSSSEG5E8_V }, // 9809 |
| 31080 | { PseudoVSSSEG5E8_V_MF8_MASK, VSSSEG5E8_V }, // 9810 |
| 31081 | { PseudoVSSSEG6E16_V_M1, VSSSEG6E16_V }, // 9811 |
| 31082 | { PseudoVSSSEG6E16_V_M1_MASK, VSSSEG6E16_V }, // 9812 |
| 31083 | { PseudoVSSSEG6E16_V_MF2, VSSSEG6E16_V }, // 9813 |
| 31084 | { PseudoVSSSEG6E16_V_MF2_MASK, VSSSEG6E16_V }, // 9814 |
| 31085 | { PseudoVSSSEG6E16_V_MF4, VSSSEG6E16_V }, // 9815 |
| 31086 | { PseudoVSSSEG6E16_V_MF4_MASK, VSSSEG6E16_V }, // 9816 |
| 31087 | { PseudoVSSSEG6E32_V_M1, VSSSEG6E32_V }, // 9817 |
| 31088 | { PseudoVSSSEG6E32_V_M1_MASK, VSSSEG6E32_V }, // 9818 |
| 31089 | { PseudoVSSSEG6E32_V_MF2, VSSSEG6E32_V }, // 9819 |
| 31090 | { PseudoVSSSEG6E32_V_MF2_MASK, VSSSEG6E32_V }, // 9820 |
| 31091 | { PseudoVSSSEG6E64_V_M1, VSSSEG6E64_V }, // 9821 |
| 31092 | { PseudoVSSSEG6E64_V_M1_MASK, VSSSEG6E64_V }, // 9822 |
| 31093 | { PseudoVSSSEG6E8_V_M1, VSSSEG6E8_V }, // 9823 |
| 31094 | { PseudoVSSSEG6E8_V_M1_MASK, VSSSEG6E8_V }, // 9824 |
| 31095 | { PseudoVSSSEG6E8_V_MF2, VSSSEG6E8_V }, // 9825 |
| 31096 | { PseudoVSSSEG6E8_V_MF2_MASK, VSSSEG6E8_V }, // 9826 |
| 31097 | { PseudoVSSSEG6E8_V_MF4, VSSSEG6E8_V }, // 9827 |
| 31098 | { PseudoVSSSEG6E8_V_MF4_MASK, VSSSEG6E8_V }, // 9828 |
| 31099 | { PseudoVSSSEG6E8_V_MF8, VSSSEG6E8_V }, // 9829 |
| 31100 | { PseudoVSSSEG6E8_V_MF8_MASK, VSSSEG6E8_V }, // 9830 |
| 31101 | { PseudoVSSSEG7E16_V_M1, VSSSEG7E16_V }, // 9831 |
| 31102 | { PseudoVSSSEG7E16_V_M1_MASK, VSSSEG7E16_V }, // 9832 |
| 31103 | { PseudoVSSSEG7E16_V_MF2, VSSSEG7E16_V }, // 9833 |
| 31104 | { PseudoVSSSEG7E16_V_MF2_MASK, VSSSEG7E16_V }, // 9834 |
| 31105 | { PseudoVSSSEG7E16_V_MF4, VSSSEG7E16_V }, // 9835 |
| 31106 | { PseudoVSSSEG7E16_V_MF4_MASK, VSSSEG7E16_V }, // 9836 |
| 31107 | { PseudoVSSSEG7E32_V_M1, VSSSEG7E32_V }, // 9837 |
| 31108 | { PseudoVSSSEG7E32_V_M1_MASK, VSSSEG7E32_V }, // 9838 |
| 31109 | { PseudoVSSSEG7E32_V_MF2, VSSSEG7E32_V }, // 9839 |
| 31110 | { PseudoVSSSEG7E32_V_MF2_MASK, VSSSEG7E32_V }, // 9840 |
| 31111 | { PseudoVSSSEG7E64_V_M1, VSSSEG7E64_V }, // 9841 |
| 31112 | { PseudoVSSSEG7E64_V_M1_MASK, VSSSEG7E64_V }, // 9842 |
| 31113 | { PseudoVSSSEG7E8_V_M1, VSSSEG7E8_V }, // 9843 |
| 31114 | { PseudoVSSSEG7E8_V_M1_MASK, VSSSEG7E8_V }, // 9844 |
| 31115 | { PseudoVSSSEG7E8_V_MF2, VSSSEG7E8_V }, // 9845 |
| 31116 | { PseudoVSSSEG7E8_V_MF2_MASK, VSSSEG7E8_V }, // 9846 |
| 31117 | { PseudoVSSSEG7E8_V_MF4, VSSSEG7E8_V }, // 9847 |
| 31118 | { PseudoVSSSEG7E8_V_MF4_MASK, VSSSEG7E8_V }, // 9848 |
| 31119 | { PseudoVSSSEG7E8_V_MF8, VSSSEG7E8_V }, // 9849 |
| 31120 | { PseudoVSSSEG7E8_V_MF8_MASK, VSSSEG7E8_V }, // 9850 |
| 31121 | { PseudoVSSSEG8E16_V_M1, VSSSEG8E16_V }, // 9851 |
| 31122 | { PseudoVSSSEG8E16_V_M1_MASK, VSSSEG8E16_V }, // 9852 |
| 31123 | { PseudoVSSSEG8E16_V_MF2, VSSSEG8E16_V }, // 9853 |
| 31124 | { PseudoVSSSEG8E16_V_MF2_MASK, VSSSEG8E16_V }, // 9854 |
| 31125 | { PseudoVSSSEG8E16_V_MF4, VSSSEG8E16_V }, // 9855 |
| 31126 | { PseudoVSSSEG8E16_V_MF4_MASK, VSSSEG8E16_V }, // 9856 |
| 31127 | { PseudoVSSSEG8E32_V_M1, VSSSEG8E32_V }, // 9857 |
| 31128 | { PseudoVSSSEG8E32_V_M1_MASK, VSSSEG8E32_V }, // 9858 |
| 31129 | { PseudoVSSSEG8E32_V_MF2, VSSSEG8E32_V }, // 9859 |
| 31130 | { PseudoVSSSEG8E32_V_MF2_MASK, VSSSEG8E32_V }, // 9860 |
| 31131 | { PseudoVSSSEG8E64_V_M1, VSSSEG8E64_V }, // 9861 |
| 31132 | { PseudoVSSSEG8E64_V_M1_MASK, VSSSEG8E64_V }, // 9862 |
| 31133 | { PseudoVSSSEG8E8_V_M1, VSSSEG8E8_V }, // 9863 |
| 31134 | { PseudoVSSSEG8E8_V_M1_MASK, VSSSEG8E8_V }, // 9864 |
| 31135 | { PseudoVSSSEG8E8_V_MF2, VSSSEG8E8_V }, // 9865 |
| 31136 | { PseudoVSSSEG8E8_V_MF2_MASK, VSSSEG8E8_V }, // 9866 |
| 31137 | { PseudoVSSSEG8E8_V_MF4, VSSSEG8E8_V }, // 9867 |
| 31138 | { PseudoVSSSEG8E8_V_MF4_MASK, VSSSEG8E8_V }, // 9868 |
| 31139 | { PseudoVSSSEG8E8_V_MF8, VSSSEG8E8_V }, // 9869 |
| 31140 | { PseudoVSSSEG8E8_V_MF8_MASK, VSSSEG8E8_V }, // 9870 |
| 31141 | { PseudoVSSUBU_VV_M1, VSSUBU_VV }, // 9871 |
| 31142 | { PseudoVSSUBU_VV_M1_MASK, VSSUBU_VV }, // 9872 |
| 31143 | { PseudoVSSUBU_VV_M2, VSSUBU_VV }, // 9873 |
| 31144 | { PseudoVSSUBU_VV_M2_MASK, VSSUBU_VV }, // 9874 |
| 31145 | { PseudoVSSUBU_VV_M4, VSSUBU_VV }, // 9875 |
| 31146 | { PseudoVSSUBU_VV_M4_MASK, VSSUBU_VV }, // 9876 |
| 31147 | { PseudoVSSUBU_VV_M8, VSSUBU_VV }, // 9877 |
| 31148 | { PseudoVSSUBU_VV_M8_MASK, VSSUBU_VV }, // 9878 |
| 31149 | { PseudoVSSUBU_VV_MF2, VSSUBU_VV }, // 9879 |
| 31150 | { PseudoVSSUBU_VV_MF2_MASK, VSSUBU_VV }, // 9880 |
| 31151 | { PseudoVSSUBU_VV_MF4, VSSUBU_VV }, // 9881 |
| 31152 | { PseudoVSSUBU_VV_MF4_MASK, VSSUBU_VV }, // 9882 |
| 31153 | { PseudoVSSUBU_VV_MF8, VSSUBU_VV }, // 9883 |
| 31154 | { PseudoVSSUBU_VV_MF8_MASK, VSSUBU_VV }, // 9884 |
| 31155 | { PseudoVSSUBU_VX_M1, VSSUBU_VX }, // 9885 |
| 31156 | { PseudoVSSUBU_VX_M1_MASK, VSSUBU_VX }, // 9886 |
| 31157 | { PseudoVSSUBU_VX_M2, VSSUBU_VX }, // 9887 |
| 31158 | { PseudoVSSUBU_VX_M2_MASK, VSSUBU_VX }, // 9888 |
| 31159 | { PseudoVSSUBU_VX_M4, VSSUBU_VX }, // 9889 |
| 31160 | { PseudoVSSUBU_VX_M4_MASK, VSSUBU_VX }, // 9890 |
| 31161 | { PseudoVSSUBU_VX_M8, VSSUBU_VX }, // 9891 |
| 31162 | { PseudoVSSUBU_VX_M8_MASK, VSSUBU_VX }, // 9892 |
| 31163 | { PseudoVSSUBU_VX_MF2, VSSUBU_VX }, // 9893 |
| 31164 | { PseudoVSSUBU_VX_MF2_MASK, VSSUBU_VX }, // 9894 |
| 31165 | { PseudoVSSUBU_VX_MF4, VSSUBU_VX }, // 9895 |
| 31166 | { PseudoVSSUBU_VX_MF4_MASK, VSSUBU_VX }, // 9896 |
| 31167 | { PseudoVSSUBU_VX_MF8, VSSUBU_VX }, // 9897 |
| 31168 | { PseudoVSSUBU_VX_MF8_MASK, VSSUBU_VX }, // 9898 |
| 31169 | { PseudoVSSUB_VV_M1, VSSUB_VV }, // 9899 |
| 31170 | { PseudoVSSUB_VV_M1_MASK, VSSUB_VV }, // 9900 |
| 31171 | { PseudoVSSUB_VV_M2, VSSUB_VV }, // 9901 |
| 31172 | { PseudoVSSUB_VV_M2_MASK, VSSUB_VV }, // 9902 |
| 31173 | { PseudoVSSUB_VV_M4, VSSUB_VV }, // 9903 |
| 31174 | { PseudoVSSUB_VV_M4_MASK, VSSUB_VV }, // 9904 |
| 31175 | { PseudoVSSUB_VV_M8, VSSUB_VV }, // 9905 |
| 31176 | { PseudoVSSUB_VV_M8_MASK, VSSUB_VV }, // 9906 |
| 31177 | { PseudoVSSUB_VV_MF2, VSSUB_VV }, // 9907 |
| 31178 | { PseudoVSSUB_VV_MF2_MASK, VSSUB_VV }, // 9908 |
| 31179 | { PseudoVSSUB_VV_MF4, VSSUB_VV }, // 9909 |
| 31180 | { PseudoVSSUB_VV_MF4_MASK, VSSUB_VV }, // 9910 |
| 31181 | { PseudoVSSUB_VV_MF8, VSSUB_VV }, // 9911 |
| 31182 | { PseudoVSSUB_VV_MF8_MASK, VSSUB_VV }, // 9912 |
| 31183 | { PseudoVSSUB_VX_M1, VSSUB_VX }, // 9913 |
| 31184 | { PseudoVSSUB_VX_M1_MASK, VSSUB_VX }, // 9914 |
| 31185 | { PseudoVSSUB_VX_M2, VSSUB_VX }, // 9915 |
| 31186 | { PseudoVSSUB_VX_M2_MASK, VSSUB_VX }, // 9916 |
| 31187 | { PseudoVSSUB_VX_M4, VSSUB_VX }, // 9917 |
| 31188 | { PseudoVSSUB_VX_M4_MASK, VSSUB_VX }, // 9918 |
| 31189 | { PseudoVSSUB_VX_M8, VSSUB_VX }, // 9919 |
| 31190 | { PseudoVSSUB_VX_M8_MASK, VSSUB_VX }, // 9920 |
| 31191 | { PseudoVSSUB_VX_MF2, VSSUB_VX }, // 9921 |
| 31192 | { PseudoVSSUB_VX_MF2_MASK, VSSUB_VX }, // 9922 |
| 31193 | { PseudoVSSUB_VX_MF4, VSSUB_VX }, // 9923 |
| 31194 | { PseudoVSSUB_VX_MF4_MASK, VSSUB_VX }, // 9924 |
| 31195 | { PseudoVSSUB_VX_MF8, VSSUB_VX }, // 9925 |
| 31196 | { PseudoVSSUB_VX_MF8_MASK, VSSUB_VX }, // 9926 |
| 31197 | { PseudoVSUB_VV_M1, VSUB_VV }, // 9927 |
| 31198 | { PseudoVSUB_VV_M1_MASK, VSUB_VV }, // 9928 |
| 31199 | { PseudoVSUB_VV_M2, VSUB_VV }, // 9929 |
| 31200 | { PseudoVSUB_VV_M2_MASK, VSUB_VV }, // 9930 |
| 31201 | { PseudoVSUB_VV_M4, VSUB_VV }, // 9931 |
| 31202 | { PseudoVSUB_VV_M4_MASK, VSUB_VV }, // 9932 |
| 31203 | { PseudoVSUB_VV_M8, VSUB_VV }, // 9933 |
| 31204 | { PseudoVSUB_VV_M8_MASK, VSUB_VV }, // 9934 |
| 31205 | { PseudoVSUB_VV_MF2, VSUB_VV }, // 9935 |
| 31206 | { PseudoVSUB_VV_MF2_MASK, VSUB_VV }, // 9936 |
| 31207 | { PseudoVSUB_VV_MF4, VSUB_VV }, // 9937 |
| 31208 | { PseudoVSUB_VV_MF4_MASK, VSUB_VV }, // 9938 |
| 31209 | { PseudoVSUB_VV_MF8, VSUB_VV }, // 9939 |
| 31210 | { PseudoVSUB_VV_MF8_MASK, VSUB_VV }, // 9940 |
| 31211 | { PseudoVSUB_VX_M1, VSUB_VX }, // 9941 |
| 31212 | { PseudoVSUB_VX_M1_MASK, VSUB_VX }, // 9942 |
| 31213 | { PseudoVSUB_VX_M2, VSUB_VX }, // 9943 |
| 31214 | { PseudoVSUB_VX_M2_MASK, VSUB_VX }, // 9944 |
| 31215 | { PseudoVSUB_VX_M4, VSUB_VX }, // 9945 |
| 31216 | { PseudoVSUB_VX_M4_MASK, VSUB_VX }, // 9946 |
| 31217 | { PseudoVSUB_VX_M8, VSUB_VX }, // 9947 |
| 31218 | { PseudoVSUB_VX_M8_MASK, VSUB_VX }, // 9948 |
| 31219 | { PseudoVSUB_VX_MF2, VSUB_VX }, // 9949 |
| 31220 | { PseudoVSUB_VX_MF2_MASK, VSUB_VX }, // 9950 |
| 31221 | { PseudoVSUB_VX_MF4, VSUB_VX }, // 9951 |
| 31222 | { PseudoVSUB_VX_MF4_MASK, VSUB_VX }, // 9952 |
| 31223 | { PseudoVSUB_VX_MF8, VSUB_VX }, // 9953 |
| 31224 | { PseudoVSUB_VX_MF8_MASK, VSUB_VX }, // 9954 |
| 31225 | { PseudoVSUXEI16_V_M1_M1, VSUXEI16_V }, // 9955 |
| 31226 | { PseudoVSUXEI16_V_M1_M1_MASK, VSUXEI16_V }, // 9956 |
| 31227 | { PseudoVSUXEI16_V_M1_M2, VSUXEI16_V }, // 9957 |
| 31228 | { PseudoVSUXEI16_V_M1_M2_MASK, VSUXEI16_V }, // 9958 |
| 31229 | { PseudoVSUXEI16_V_M1_M4, VSUXEI16_V }, // 9959 |
| 31230 | { PseudoVSUXEI16_V_M1_M4_MASK, VSUXEI16_V }, // 9960 |
| 31231 | { PseudoVSUXEI16_V_M1_MF2, VSUXEI16_V }, // 9961 |
| 31232 | { PseudoVSUXEI16_V_M1_MF2_MASK, VSUXEI16_V }, // 9962 |
| 31233 | { PseudoVSUXEI16_V_M2_M1, VSUXEI16_V }, // 9963 |
| 31234 | { PseudoVSUXEI16_V_M2_M1_MASK, VSUXEI16_V }, // 9964 |
| 31235 | { PseudoVSUXEI16_V_M2_M2, VSUXEI16_V }, // 9965 |
| 31236 | { PseudoVSUXEI16_V_M2_M2_MASK, VSUXEI16_V }, // 9966 |
| 31237 | { PseudoVSUXEI16_V_M2_M4, VSUXEI16_V }, // 9967 |
| 31238 | { PseudoVSUXEI16_V_M2_M4_MASK, VSUXEI16_V }, // 9968 |
| 31239 | { PseudoVSUXEI16_V_M2_M8, VSUXEI16_V }, // 9969 |
| 31240 | { PseudoVSUXEI16_V_M2_M8_MASK, VSUXEI16_V }, // 9970 |
| 31241 | { PseudoVSUXEI16_V_M4_M2, VSUXEI16_V }, // 9971 |
| 31242 | { PseudoVSUXEI16_V_M4_M2_MASK, VSUXEI16_V }, // 9972 |
| 31243 | { PseudoVSUXEI16_V_M4_M4, VSUXEI16_V }, // 9973 |
| 31244 | { PseudoVSUXEI16_V_M4_M4_MASK, VSUXEI16_V }, // 9974 |
| 31245 | { PseudoVSUXEI16_V_M4_M8, VSUXEI16_V }, // 9975 |
| 31246 | { PseudoVSUXEI16_V_M4_M8_MASK, VSUXEI16_V }, // 9976 |
| 31247 | { PseudoVSUXEI16_V_M8_M4, VSUXEI16_V }, // 9977 |
| 31248 | { PseudoVSUXEI16_V_M8_M4_MASK, VSUXEI16_V }, // 9978 |
| 31249 | { PseudoVSUXEI16_V_M8_M8, VSUXEI16_V }, // 9979 |
| 31250 | { PseudoVSUXEI16_V_M8_M8_MASK, VSUXEI16_V }, // 9980 |
| 31251 | { PseudoVSUXEI16_V_MF2_M1, VSUXEI16_V }, // 9981 |
| 31252 | { PseudoVSUXEI16_V_MF2_M1_MASK, VSUXEI16_V }, // 9982 |
| 31253 | { PseudoVSUXEI16_V_MF2_M2, VSUXEI16_V }, // 9983 |
| 31254 | { PseudoVSUXEI16_V_MF2_M2_MASK, VSUXEI16_V }, // 9984 |
| 31255 | { PseudoVSUXEI16_V_MF2_MF2, VSUXEI16_V }, // 9985 |
| 31256 | { PseudoVSUXEI16_V_MF2_MF2_MASK, VSUXEI16_V }, // 9986 |
| 31257 | { PseudoVSUXEI16_V_MF2_MF4, VSUXEI16_V }, // 9987 |
| 31258 | { PseudoVSUXEI16_V_MF2_MF4_MASK, VSUXEI16_V }, // 9988 |
| 31259 | { PseudoVSUXEI16_V_MF4_M1, VSUXEI16_V }, // 9989 |
| 31260 | { PseudoVSUXEI16_V_MF4_M1_MASK, VSUXEI16_V }, // 9990 |
| 31261 | { PseudoVSUXEI16_V_MF4_MF2, VSUXEI16_V }, // 9991 |
| 31262 | { PseudoVSUXEI16_V_MF4_MF2_MASK, VSUXEI16_V }, // 9992 |
| 31263 | { PseudoVSUXEI16_V_MF4_MF4, VSUXEI16_V }, // 9993 |
| 31264 | { PseudoVSUXEI16_V_MF4_MF4_MASK, VSUXEI16_V }, // 9994 |
| 31265 | { PseudoVSUXEI16_V_MF4_MF8, VSUXEI16_V }, // 9995 |
| 31266 | { PseudoVSUXEI16_V_MF4_MF8_MASK, VSUXEI16_V }, // 9996 |
| 31267 | { PseudoVSUXEI32_V_M1_M1, VSUXEI32_V }, // 9997 |
| 31268 | { PseudoVSUXEI32_V_M1_M1_MASK, VSUXEI32_V }, // 9998 |
| 31269 | { PseudoVSUXEI32_V_M1_M2, VSUXEI32_V }, // 9999 |
| 31270 | { PseudoVSUXEI32_V_M1_M2_MASK, VSUXEI32_V }, // 10000 |
| 31271 | { PseudoVSUXEI32_V_M1_MF2, VSUXEI32_V }, // 10001 |
| 31272 | { PseudoVSUXEI32_V_M1_MF2_MASK, VSUXEI32_V }, // 10002 |
| 31273 | { PseudoVSUXEI32_V_M1_MF4, VSUXEI32_V }, // 10003 |
| 31274 | { PseudoVSUXEI32_V_M1_MF4_MASK, VSUXEI32_V }, // 10004 |
| 31275 | { PseudoVSUXEI32_V_M2_M1, VSUXEI32_V }, // 10005 |
| 31276 | { PseudoVSUXEI32_V_M2_M1_MASK, VSUXEI32_V }, // 10006 |
| 31277 | { PseudoVSUXEI32_V_M2_M2, VSUXEI32_V }, // 10007 |
| 31278 | { PseudoVSUXEI32_V_M2_M2_MASK, VSUXEI32_V }, // 10008 |
| 31279 | { PseudoVSUXEI32_V_M2_M4, VSUXEI32_V }, // 10009 |
| 31280 | { PseudoVSUXEI32_V_M2_M4_MASK, VSUXEI32_V }, // 10010 |
| 31281 | { PseudoVSUXEI32_V_M2_MF2, VSUXEI32_V }, // 10011 |
| 31282 | { PseudoVSUXEI32_V_M2_MF2_MASK, VSUXEI32_V }, // 10012 |
| 31283 | { PseudoVSUXEI32_V_M4_M1, VSUXEI32_V }, // 10013 |
| 31284 | { PseudoVSUXEI32_V_M4_M1_MASK, VSUXEI32_V }, // 10014 |
| 31285 | { PseudoVSUXEI32_V_M4_M2, VSUXEI32_V }, // 10015 |
| 31286 | { PseudoVSUXEI32_V_M4_M2_MASK, VSUXEI32_V }, // 10016 |
| 31287 | { PseudoVSUXEI32_V_M4_M4, VSUXEI32_V }, // 10017 |
| 31288 | { PseudoVSUXEI32_V_M4_M4_MASK, VSUXEI32_V }, // 10018 |
| 31289 | { PseudoVSUXEI32_V_M4_M8, VSUXEI32_V }, // 10019 |
| 31290 | { PseudoVSUXEI32_V_M4_M8_MASK, VSUXEI32_V }, // 10020 |
| 31291 | { PseudoVSUXEI32_V_M8_M2, VSUXEI32_V }, // 10021 |
| 31292 | { PseudoVSUXEI32_V_M8_M2_MASK, VSUXEI32_V }, // 10022 |
| 31293 | { PseudoVSUXEI32_V_M8_M4, VSUXEI32_V }, // 10023 |
| 31294 | { PseudoVSUXEI32_V_M8_M4_MASK, VSUXEI32_V }, // 10024 |
| 31295 | { PseudoVSUXEI32_V_M8_M8, VSUXEI32_V }, // 10025 |
| 31296 | { PseudoVSUXEI32_V_M8_M8_MASK, VSUXEI32_V }, // 10026 |
| 31297 | { PseudoVSUXEI32_V_MF2_M1, VSUXEI32_V }, // 10027 |
| 31298 | { PseudoVSUXEI32_V_MF2_M1_MASK, VSUXEI32_V }, // 10028 |
| 31299 | { PseudoVSUXEI32_V_MF2_MF2, VSUXEI32_V }, // 10029 |
| 31300 | { PseudoVSUXEI32_V_MF2_MF2_MASK, VSUXEI32_V }, // 10030 |
| 31301 | { PseudoVSUXEI32_V_MF2_MF4, VSUXEI32_V }, // 10031 |
| 31302 | { PseudoVSUXEI32_V_MF2_MF4_MASK, VSUXEI32_V }, // 10032 |
| 31303 | { PseudoVSUXEI32_V_MF2_MF8, VSUXEI32_V }, // 10033 |
| 31304 | { PseudoVSUXEI32_V_MF2_MF8_MASK, VSUXEI32_V }, // 10034 |
| 31305 | { PseudoVSUXEI64_V_M1_M1, VSUXEI64_V }, // 10035 |
| 31306 | { PseudoVSUXEI64_V_M1_M1_MASK, VSUXEI64_V }, // 10036 |
| 31307 | { PseudoVSUXEI64_V_M1_MF2, VSUXEI64_V }, // 10037 |
| 31308 | { PseudoVSUXEI64_V_M1_MF2_MASK, VSUXEI64_V }, // 10038 |
| 31309 | { PseudoVSUXEI64_V_M1_MF4, VSUXEI64_V }, // 10039 |
| 31310 | { PseudoVSUXEI64_V_M1_MF4_MASK, VSUXEI64_V }, // 10040 |
| 31311 | { PseudoVSUXEI64_V_M1_MF8, VSUXEI64_V }, // 10041 |
| 31312 | { PseudoVSUXEI64_V_M1_MF8_MASK, VSUXEI64_V }, // 10042 |
| 31313 | { PseudoVSUXEI64_V_M2_M1, VSUXEI64_V }, // 10043 |
| 31314 | { PseudoVSUXEI64_V_M2_M1_MASK, VSUXEI64_V }, // 10044 |
| 31315 | { PseudoVSUXEI64_V_M2_M2, VSUXEI64_V }, // 10045 |
| 31316 | { PseudoVSUXEI64_V_M2_M2_MASK, VSUXEI64_V }, // 10046 |
| 31317 | { PseudoVSUXEI64_V_M2_MF2, VSUXEI64_V }, // 10047 |
| 31318 | { PseudoVSUXEI64_V_M2_MF2_MASK, VSUXEI64_V }, // 10048 |
| 31319 | { PseudoVSUXEI64_V_M2_MF4, VSUXEI64_V }, // 10049 |
| 31320 | { PseudoVSUXEI64_V_M2_MF4_MASK, VSUXEI64_V }, // 10050 |
| 31321 | { PseudoVSUXEI64_V_M4_M1, VSUXEI64_V }, // 10051 |
| 31322 | { PseudoVSUXEI64_V_M4_M1_MASK, VSUXEI64_V }, // 10052 |
| 31323 | { PseudoVSUXEI64_V_M4_M2, VSUXEI64_V }, // 10053 |
| 31324 | { PseudoVSUXEI64_V_M4_M2_MASK, VSUXEI64_V }, // 10054 |
| 31325 | { PseudoVSUXEI64_V_M4_M4, VSUXEI64_V }, // 10055 |
| 31326 | { PseudoVSUXEI64_V_M4_M4_MASK, VSUXEI64_V }, // 10056 |
| 31327 | { PseudoVSUXEI64_V_M4_MF2, VSUXEI64_V }, // 10057 |
| 31328 | { PseudoVSUXEI64_V_M4_MF2_MASK, VSUXEI64_V }, // 10058 |
| 31329 | { PseudoVSUXEI64_V_M8_M1, VSUXEI64_V }, // 10059 |
| 31330 | { PseudoVSUXEI64_V_M8_M1_MASK, VSUXEI64_V }, // 10060 |
| 31331 | { PseudoVSUXEI64_V_M8_M2, VSUXEI64_V }, // 10061 |
| 31332 | { PseudoVSUXEI64_V_M8_M2_MASK, VSUXEI64_V }, // 10062 |
| 31333 | { PseudoVSUXEI64_V_M8_M4, VSUXEI64_V }, // 10063 |
| 31334 | { PseudoVSUXEI64_V_M8_M4_MASK, VSUXEI64_V }, // 10064 |
| 31335 | { PseudoVSUXEI64_V_M8_M8, VSUXEI64_V }, // 10065 |
| 31336 | { PseudoVSUXEI64_V_M8_M8_MASK, VSUXEI64_V }, // 10066 |
| 31337 | { PseudoVSUXEI8_V_M1_M1, VSUXEI8_V }, // 10067 |
| 31338 | { PseudoVSUXEI8_V_M1_M1_MASK, VSUXEI8_V }, // 10068 |
| 31339 | { PseudoVSUXEI8_V_M1_M2, VSUXEI8_V }, // 10069 |
| 31340 | { PseudoVSUXEI8_V_M1_M2_MASK, VSUXEI8_V }, // 10070 |
| 31341 | { PseudoVSUXEI8_V_M1_M4, VSUXEI8_V }, // 10071 |
| 31342 | { PseudoVSUXEI8_V_M1_M4_MASK, VSUXEI8_V }, // 10072 |
| 31343 | { PseudoVSUXEI8_V_M1_M8, VSUXEI8_V }, // 10073 |
| 31344 | { PseudoVSUXEI8_V_M1_M8_MASK, VSUXEI8_V }, // 10074 |
| 31345 | { PseudoVSUXEI8_V_M2_M2, VSUXEI8_V }, // 10075 |
| 31346 | { PseudoVSUXEI8_V_M2_M2_MASK, VSUXEI8_V }, // 10076 |
| 31347 | { PseudoVSUXEI8_V_M2_M4, VSUXEI8_V }, // 10077 |
| 31348 | { PseudoVSUXEI8_V_M2_M4_MASK, VSUXEI8_V }, // 10078 |
| 31349 | { PseudoVSUXEI8_V_M2_M8, VSUXEI8_V }, // 10079 |
| 31350 | { PseudoVSUXEI8_V_M2_M8_MASK, VSUXEI8_V }, // 10080 |
| 31351 | { PseudoVSUXEI8_V_M4_M4, VSUXEI8_V }, // 10081 |
| 31352 | { PseudoVSUXEI8_V_M4_M4_MASK, VSUXEI8_V }, // 10082 |
| 31353 | { PseudoVSUXEI8_V_M4_M8, VSUXEI8_V }, // 10083 |
| 31354 | { PseudoVSUXEI8_V_M4_M8_MASK, VSUXEI8_V }, // 10084 |
| 31355 | { PseudoVSUXEI8_V_M8_M8, VSUXEI8_V }, // 10085 |
| 31356 | { PseudoVSUXEI8_V_M8_M8_MASK, VSUXEI8_V }, // 10086 |
| 31357 | { PseudoVSUXEI8_V_MF2_M1, VSUXEI8_V }, // 10087 |
| 31358 | { PseudoVSUXEI8_V_MF2_M1_MASK, VSUXEI8_V }, // 10088 |
| 31359 | { PseudoVSUXEI8_V_MF2_M2, VSUXEI8_V }, // 10089 |
| 31360 | { PseudoVSUXEI8_V_MF2_M2_MASK, VSUXEI8_V }, // 10090 |
| 31361 | { PseudoVSUXEI8_V_MF2_M4, VSUXEI8_V }, // 10091 |
| 31362 | { PseudoVSUXEI8_V_MF2_M4_MASK, VSUXEI8_V }, // 10092 |
| 31363 | { PseudoVSUXEI8_V_MF2_MF2, VSUXEI8_V }, // 10093 |
| 31364 | { PseudoVSUXEI8_V_MF2_MF2_MASK, VSUXEI8_V }, // 10094 |
| 31365 | { PseudoVSUXEI8_V_MF4_M1, VSUXEI8_V }, // 10095 |
| 31366 | { PseudoVSUXEI8_V_MF4_M1_MASK, VSUXEI8_V }, // 10096 |
| 31367 | { PseudoVSUXEI8_V_MF4_M2, VSUXEI8_V }, // 10097 |
| 31368 | { PseudoVSUXEI8_V_MF4_M2_MASK, VSUXEI8_V }, // 10098 |
| 31369 | { PseudoVSUXEI8_V_MF4_MF2, VSUXEI8_V }, // 10099 |
| 31370 | { PseudoVSUXEI8_V_MF4_MF2_MASK, VSUXEI8_V }, // 10100 |
| 31371 | { PseudoVSUXEI8_V_MF4_MF4, VSUXEI8_V }, // 10101 |
| 31372 | { PseudoVSUXEI8_V_MF4_MF4_MASK, VSUXEI8_V }, // 10102 |
| 31373 | { PseudoVSUXEI8_V_MF8_M1, VSUXEI8_V }, // 10103 |
| 31374 | { PseudoVSUXEI8_V_MF8_M1_MASK, VSUXEI8_V }, // 10104 |
| 31375 | { PseudoVSUXEI8_V_MF8_MF2, VSUXEI8_V }, // 10105 |
| 31376 | { PseudoVSUXEI8_V_MF8_MF2_MASK, VSUXEI8_V }, // 10106 |
| 31377 | { PseudoVSUXEI8_V_MF8_MF4, VSUXEI8_V }, // 10107 |
| 31378 | { PseudoVSUXEI8_V_MF8_MF4_MASK, VSUXEI8_V }, // 10108 |
| 31379 | { PseudoVSUXEI8_V_MF8_MF8, VSUXEI8_V }, // 10109 |
| 31380 | { PseudoVSUXEI8_V_MF8_MF8_MASK, VSUXEI8_V }, // 10110 |
| 31381 | { PseudoVSUXSEG2EI16_V_M1_M1, VSUXSEG2EI16_V }, // 10111 |
| 31382 | { PseudoVSUXSEG2EI16_V_M1_M1_MASK, VSUXSEG2EI16_V }, // 10112 |
| 31383 | { PseudoVSUXSEG2EI16_V_M1_M2, VSUXSEG2EI16_V }, // 10113 |
| 31384 | { PseudoVSUXSEG2EI16_V_M1_M2_MASK, VSUXSEG2EI16_V }, // 10114 |
| 31385 | { PseudoVSUXSEG2EI16_V_M1_M4, VSUXSEG2EI16_V }, // 10115 |
| 31386 | { PseudoVSUXSEG2EI16_V_M1_M4_MASK, VSUXSEG2EI16_V }, // 10116 |
| 31387 | { PseudoVSUXSEG2EI16_V_M1_MF2, VSUXSEG2EI16_V }, // 10117 |
| 31388 | { PseudoVSUXSEG2EI16_V_M1_MF2_MASK, VSUXSEG2EI16_V }, // 10118 |
| 31389 | { PseudoVSUXSEG2EI16_V_M2_M1, VSUXSEG2EI16_V }, // 10119 |
| 31390 | { PseudoVSUXSEG2EI16_V_M2_M1_MASK, VSUXSEG2EI16_V }, // 10120 |
| 31391 | { PseudoVSUXSEG2EI16_V_M2_M2, VSUXSEG2EI16_V }, // 10121 |
| 31392 | { PseudoVSUXSEG2EI16_V_M2_M2_MASK, VSUXSEG2EI16_V }, // 10122 |
| 31393 | { PseudoVSUXSEG2EI16_V_M2_M4, VSUXSEG2EI16_V }, // 10123 |
| 31394 | { PseudoVSUXSEG2EI16_V_M2_M4_MASK, VSUXSEG2EI16_V }, // 10124 |
| 31395 | { PseudoVSUXSEG2EI16_V_M4_M2, VSUXSEG2EI16_V }, // 10125 |
| 31396 | { PseudoVSUXSEG2EI16_V_M4_M2_MASK, VSUXSEG2EI16_V }, // 10126 |
| 31397 | { PseudoVSUXSEG2EI16_V_M4_M4, VSUXSEG2EI16_V }, // 10127 |
| 31398 | { PseudoVSUXSEG2EI16_V_M4_M4_MASK, VSUXSEG2EI16_V }, // 10128 |
| 31399 | { PseudoVSUXSEG2EI16_V_M8_M4, VSUXSEG2EI16_V }, // 10129 |
| 31400 | { PseudoVSUXSEG2EI16_V_M8_M4_MASK, VSUXSEG2EI16_V }, // 10130 |
| 31401 | { PseudoVSUXSEG2EI16_V_MF2_M1, VSUXSEG2EI16_V }, // 10131 |
| 31402 | { PseudoVSUXSEG2EI16_V_MF2_M1_MASK, VSUXSEG2EI16_V }, // 10132 |
| 31403 | { PseudoVSUXSEG2EI16_V_MF2_M2, VSUXSEG2EI16_V }, // 10133 |
| 31404 | { PseudoVSUXSEG2EI16_V_MF2_M2_MASK, VSUXSEG2EI16_V }, // 10134 |
| 31405 | { PseudoVSUXSEG2EI16_V_MF2_MF2, VSUXSEG2EI16_V }, // 10135 |
| 31406 | { PseudoVSUXSEG2EI16_V_MF2_MF2_MASK, VSUXSEG2EI16_V }, // 10136 |
| 31407 | { PseudoVSUXSEG2EI16_V_MF2_MF4, VSUXSEG2EI16_V }, // 10137 |
| 31408 | { PseudoVSUXSEG2EI16_V_MF2_MF4_MASK, VSUXSEG2EI16_V }, // 10138 |
| 31409 | { PseudoVSUXSEG2EI16_V_MF4_M1, VSUXSEG2EI16_V }, // 10139 |
| 31410 | { PseudoVSUXSEG2EI16_V_MF4_M1_MASK, VSUXSEG2EI16_V }, // 10140 |
| 31411 | { PseudoVSUXSEG2EI16_V_MF4_MF2, VSUXSEG2EI16_V }, // 10141 |
| 31412 | { PseudoVSUXSEG2EI16_V_MF4_MF2_MASK, VSUXSEG2EI16_V }, // 10142 |
| 31413 | { PseudoVSUXSEG2EI16_V_MF4_MF4, VSUXSEG2EI16_V }, // 10143 |
| 31414 | { PseudoVSUXSEG2EI16_V_MF4_MF4_MASK, VSUXSEG2EI16_V }, // 10144 |
| 31415 | { PseudoVSUXSEG2EI16_V_MF4_MF8, VSUXSEG2EI16_V }, // 10145 |
| 31416 | { PseudoVSUXSEG2EI16_V_MF4_MF8_MASK, VSUXSEG2EI16_V }, // 10146 |
| 31417 | { PseudoVSUXSEG2EI32_V_M1_M1, VSUXSEG2EI32_V }, // 10147 |
| 31418 | { PseudoVSUXSEG2EI32_V_M1_M1_MASK, VSUXSEG2EI32_V }, // 10148 |
| 31419 | { PseudoVSUXSEG2EI32_V_M1_M2, VSUXSEG2EI32_V }, // 10149 |
| 31420 | { PseudoVSUXSEG2EI32_V_M1_M2_MASK, VSUXSEG2EI32_V }, // 10150 |
| 31421 | { PseudoVSUXSEG2EI32_V_M1_MF2, VSUXSEG2EI32_V }, // 10151 |
| 31422 | { PseudoVSUXSEG2EI32_V_M1_MF2_MASK, VSUXSEG2EI32_V }, // 10152 |
| 31423 | { PseudoVSUXSEG2EI32_V_M1_MF4, VSUXSEG2EI32_V }, // 10153 |
| 31424 | { PseudoVSUXSEG2EI32_V_M1_MF4_MASK, VSUXSEG2EI32_V }, // 10154 |
| 31425 | { PseudoVSUXSEG2EI32_V_M2_M1, VSUXSEG2EI32_V }, // 10155 |
| 31426 | { PseudoVSUXSEG2EI32_V_M2_M1_MASK, VSUXSEG2EI32_V }, // 10156 |
| 31427 | { PseudoVSUXSEG2EI32_V_M2_M2, VSUXSEG2EI32_V }, // 10157 |
| 31428 | { PseudoVSUXSEG2EI32_V_M2_M2_MASK, VSUXSEG2EI32_V }, // 10158 |
| 31429 | { PseudoVSUXSEG2EI32_V_M2_M4, VSUXSEG2EI32_V }, // 10159 |
| 31430 | { PseudoVSUXSEG2EI32_V_M2_M4_MASK, VSUXSEG2EI32_V }, // 10160 |
| 31431 | { PseudoVSUXSEG2EI32_V_M2_MF2, VSUXSEG2EI32_V }, // 10161 |
| 31432 | { PseudoVSUXSEG2EI32_V_M2_MF2_MASK, VSUXSEG2EI32_V }, // 10162 |
| 31433 | { PseudoVSUXSEG2EI32_V_M4_M1, VSUXSEG2EI32_V }, // 10163 |
| 31434 | { PseudoVSUXSEG2EI32_V_M4_M1_MASK, VSUXSEG2EI32_V }, // 10164 |
| 31435 | { PseudoVSUXSEG2EI32_V_M4_M2, VSUXSEG2EI32_V }, // 10165 |
| 31436 | { PseudoVSUXSEG2EI32_V_M4_M2_MASK, VSUXSEG2EI32_V }, // 10166 |
| 31437 | { PseudoVSUXSEG2EI32_V_M4_M4, VSUXSEG2EI32_V }, // 10167 |
| 31438 | { PseudoVSUXSEG2EI32_V_M4_M4_MASK, VSUXSEG2EI32_V }, // 10168 |
| 31439 | { PseudoVSUXSEG2EI32_V_M8_M2, VSUXSEG2EI32_V }, // 10169 |
| 31440 | { PseudoVSUXSEG2EI32_V_M8_M2_MASK, VSUXSEG2EI32_V }, // 10170 |
| 31441 | { PseudoVSUXSEG2EI32_V_M8_M4, VSUXSEG2EI32_V }, // 10171 |
| 31442 | { PseudoVSUXSEG2EI32_V_M8_M4_MASK, VSUXSEG2EI32_V }, // 10172 |
| 31443 | { PseudoVSUXSEG2EI32_V_MF2_M1, VSUXSEG2EI32_V }, // 10173 |
| 31444 | { PseudoVSUXSEG2EI32_V_MF2_M1_MASK, VSUXSEG2EI32_V }, // 10174 |
| 31445 | { PseudoVSUXSEG2EI32_V_MF2_MF2, VSUXSEG2EI32_V }, // 10175 |
| 31446 | { PseudoVSUXSEG2EI32_V_MF2_MF2_MASK, VSUXSEG2EI32_V }, // 10176 |
| 31447 | { PseudoVSUXSEG2EI32_V_MF2_MF4, VSUXSEG2EI32_V }, // 10177 |
| 31448 | { PseudoVSUXSEG2EI32_V_MF2_MF4_MASK, VSUXSEG2EI32_V }, // 10178 |
| 31449 | { PseudoVSUXSEG2EI32_V_MF2_MF8, VSUXSEG2EI32_V }, // 10179 |
| 31450 | { PseudoVSUXSEG2EI32_V_MF2_MF8_MASK, VSUXSEG2EI32_V }, // 10180 |
| 31451 | { PseudoVSUXSEG2EI64_V_M1_M1, VSUXSEG2EI64_V }, // 10181 |
| 31452 | { PseudoVSUXSEG2EI64_V_M1_M1_MASK, VSUXSEG2EI64_V }, // 10182 |
| 31453 | { PseudoVSUXSEG2EI64_V_M1_MF2, VSUXSEG2EI64_V }, // 10183 |
| 31454 | { PseudoVSUXSEG2EI64_V_M1_MF2_MASK, VSUXSEG2EI64_V }, // 10184 |
| 31455 | { PseudoVSUXSEG2EI64_V_M1_MF4, VSUXSEG2EI64_V }, // 10185 |
| 31456 | { PseudoVSUXSEG2EI64_V_M1_MF4_MASK, VSUXSEG2EI64_V }, // 10186 |
| 31457 | { PseudoVSUXSEG2EI64_V_M1_MF8, VSUXSEG2EI64_V }, // 10187 |
| 31458 | { PseudoVSUXSEG2EI64_V_M1_MF8_MASK, VSUXSEG2EI64_V }, // 10188 |
| 31459 | { PseudoVSUXSEG2EI64_V_M2_M1, VSUXSEG2EI64_V }, // 10189 |
| 31460 | { PseudoVSUXSEG2EI64_V_M2_M1_MASK, VSUXSEG2EI64_V }, // 10190 |
| 31461 | { PseudoVSUXSEG2EI64_V_M2_M2, VSUXSEG2EI64_V }, // 10191 |
| 31462 | { PseudoVSUXSEG2EI64_V_M2_M2_MASK, VSUXSEG2EI64_V }, // 10192 |
| 31463 | { PseudoVSUXSEG2EI64_V_M2_MF2, VSUXSEG2EI64_V }, // 10193 |
| 31464 | { PseudoVSUXSEG2EI64_V_M2_MF2_MASK, VSUXSEG2EI64_V }, // 10194 |
| 31465 | { PseudoVSUXSEG2EI64_V_M2_MF4, VSUXSEG2EI64_V }, // 10195 |
| 31466 | { PseudoVSUXSEG2EI64_V_M2_MF4_MASK, VSUXSEG2EI64_V }, // 10196 |
| 31467 | { PseudoVSUXSEG2EI64_V_M4_M1, VSUXSEG2EI64_V }, // 10197 |
| 31468 | { PseudoVSUXSEG2EI64_V_M4_M1_MASK, VSUXSEG2EI64_V }, // 10198 |
| 31469 | { PseudoVSUXSEG2EI64_V_M4_M2, VSUXSEG2EI64_V }, // 10199 |
| 31470 | { PseudoVSUXSEG2EI64_V_M4_M2_MASK, VSUXSEG2EI64_V }, // 10200 |
| 31471 | { PseudoVSUXSEG2EI64_V_M4_M4, VSUXSEG2EI64_V }, // 10201 |
| 31472 | { PseudoVSUXSEG2EI64_V_M4_M4_MASK, VSUXSEG2EI64_V }, // 10202 |
| 31473 | { PseudoVSUXSEG2EI64_V_M4_MF2, VSUXSEG2EI64_V }, // 10203 |
| 31474 | { PseudoVSUXSEG2EI64_V_M4_MF2_MASK, VSUXSEG2EI64_V }, // 10204 |
| 31475 | { PseudoVSUXSEG2EI64_V_M8_M1, VSUXSEG2EI64_V }, // 10205 |
| 31476 | { PseudoVSUXSEG2EI64_V_M8_M1_MASK, VSUXSEG2EI64_V }, // 10206 |
| 31477 | { PseudoVSUXSEG2EI64_V_M8_M2, VSUXSEG2EI64_V }, // 10207 |
| 31478 | { PseudoVSUXSEG2EI64_V_M8_M2_MASK, VSUXSEG2EI64_V }, // 10208 |
| 31479 | { PseudoVSUXSEG2EI64_V_M8_M4, VSUXSEG2EI64_V }, // 10209 |
| 31480 | { PseudoVSUXSEG2EI64_V_M8_M4_MASK, VSUXSEG2EI64_V }, // 10210 |
| 31481 | { PseudoVSUXSEG2EI8_V_M1_M1, VSUXSEG2EI8_V }, // 10211 |
| 31482 | { PseudoVSUXSEG2EI8_V_M1_M1_MASK, VSUXSEG2EI8_V }, // 10212 |
| 31483 | { PseudoVSUXSEG2EI8_V_M1_M2, VSUXSEG2EI8_V }, // 10213 |
| 31484 | { PseudoVSUXSEG2EI8_V_M1_M2_MASK, VSUXSEG2EI8_V }, // 10214 |
| 31485 | { PseudoVSUXSEG2EI8_V_M1_M4, VSUXSEG2EI8_V }, // 10215 |
| 31486 | { PseudoVSUXSEG2EI8_V_M1_M4_MASK, VSUXSEG2EI8_V }, // 10216 |
| 31487 | { PseudoVSUXSEG2EI8_V_M2_M2, VSUXSEG2EI8_V }, // 10217 |
| 31488 | { PseudoVSUXSEG2EI8_V_M2_M2_MASK, VSUXSEG2EI8_V }, // 10218 |
| 31489 | { PseudoVSUXSEG2EI8_V_M2_M4, VSUXSEG2EI8_V }, // 10219 |
| 31490 | { PseudoVSUXSEG2EI8_V_M2_M4_MASK, VSUXSEG2EI8_V }, // 10220 |
| 31491 | { PseudoVSUXSEG2EI8_V_M4_M4, VSUXSEG2EI8_V }, // 10221 |
| 31492 | { PseudoVSUXSEG2EI8_V_M4_M4_MASK, VSUXSEG2EI8_V }, // 10222 |
| 31493 | { PseudoVSUXSEG2EI8_V_MF2_M1, VSUXSEG2EI8_V }, // 10223 |
| 31494 | { PseudoVSUXSEG2EI8_V_MF2_M1_MASK, VSUXSEG2EI8_V }, // 10224 |
| 31495 | { PseudoVSUXSEG2EI8_V_MF2_M2, VSUXSEG2EI8_V }, // 10225 |
| 31496 | { PseudoVSUXSEG2EI8_V_MF2_M2_MASK, VSUXSEG2EI8_V }, // 10226 |
| 31497 | { PseudoVSUXSEG2EI8_V_MF2_M4, VSUXSEG2EI8_V }, // 10227 |
| 31498 | { PseudoVSUXSEG2EI8_V_MF2_M4_MASK, VSUXSEG2EI8_V }, // 10228 |
| 31499 | { PseudoVSUXSEG2EI8_V_MF2_MF2, VSUXSEG2EI8_V }, // 10229 |
| 31500 | { PseudoVSUXSEG2EI8_V_MF2_MF2_MASK, VSUXSEG2EI8_V }, // 10230 |
| 31501 | { PseudoVSUXSEG2EI8_V_MF4_M1, VSUXSEG2EI8_V }, // 10231 |
| 31502 | { PseudoVSUXSEG2EI8_V_MF4_M1_MASK, VSUXSEG2EI8_V }, // 10232 |
| 31503 | { PseudoVSUXSEG2EI8_V_MF4_M2, VSUXSEG2EI8_V }, // 10233 |
| 31504 | { PseudoVSUXSEG2EI8_V_MF4_M2_MASK, VSUXSEG2EI8_V }, // 10234 |
| 31505 | { PseudoVSUXSEG2EI8_V_MF4_MF2, VSUXSEG2EI8_V }, // 10235 |
| 31506 | { PseudoVSUXSEG2EI8_V_MF4_MF2_MASK, VSUXSEG2EI8_V }, // 10236 |
| 31507 | { PseudoVSUXSEG2EI8_V_MF4_MF4, VSUXSEG2EI8_V }, // 10237 |
| 31508 | { PseudoVSUXSEG2EI8_V_MF4_MF4_MASK, VSUXSEG2EI8_V }, // 10238 |
| 31509 | { PseudoVSUXSEG2EI8_V_MF8_M1, VSUXSEG2EI8_V }, // 10239 |
| 31510 | { PseudoVSUXSEG2EI8_V_MF8_M1_MASK, VSUXSEG2EI8_V }, // 10240 |
| 31511 | { PseudoVSUXSEG2EI8_V_MF8_MF2, VSUXSEG2EI8_V }, // 10241 |
| 31512 | { PseudoVSUXSEG2EI8_V_MF8_MF2_MASK, VSUXSEG2EI8_V }, // 10242 |
| 31513 | { PseudoVSUXSEG2EI8_V_MF8_MF4, VSUXSEG2EI8_V }, // 10243 |
| 31514 | { PseudoVSUXSEG2EI8_V_MF8_MF4_MASK, VSUXSEG2EI8_V }, // 10244 |
| 31515 | { PseudoVSUXSEG2EI8_V_MF8_MF8, VSUXSEG2EI8_V }, // 10245 |
| 31516 | { PseudoVSUXSEG2EI8_V_MF8_MF8_MASK, VSUXSEG2EI8_V }, // 10246 |
| 31517 | { PseudoVSUXSEG3EI16_V_M1_M1, VSUXSEG3EI16_V }, // 10247 |
| 31518 | { PseudoVSUXSEG3EI16_V_M1_M1_MASK, VSUXSEG3EI16_V }, // 10248 |
| 31519 | { PseudoVSUXSEG3EI16_V_M1_M2, VSUXSEG3EI16_V }, // 10249 |
| 31520 | { PseudoVSUXSEG3EI16_V_M1_M2_MASK, VSUXSEG3EI16_V }, // 10250 |
| 31521 | { PseudoVSUXSEG3EI16_V_M1_MF2, VSUXSEG3EI16_V }, // 10251 |
| 31522 | { PseudoVSUXSEG3EI16_V_M1_MF2_MASK, VSUXSEG3EI16_V }, // 10252 |
| 31523 | { PseudoVSUXSEG3EI16_V_M2_M1, VSUXSEG3EI16_V }, // 10253 |
| 31524 | { PseudoVSUXSEG3EI16_V_M2_M1_MASK, VSUXSEG3EI16_V }, // 10254 |
| 31525 | { PseudoVSUXSEG3EI16_V_M2_M2, VSUXSEG3EI16_V }, // 10255 |
| 31526 | { PseudoVSUXSEG3EI16_V_M2_M2_MASK, VSUXSEG3EI16_V }, // 10256 |
| 31527 | { PseudoVSUXSEG3EI16_V_M4_M2, VSUXSEG3EI16_V }, // 10257 |
| 31528 | { PseudoVSUXSEG3EI16_V_M4_M2_MASK, VSUXSEG3EI16_V }, // 10258 |
| 31529 | { PseudoVSUXSEG3EI16_V_MF2_M1, VSUXSEG3EI16_V }, // 10259 |
| 31530 | { PseudoVSUXSEG3EI16_V_MF2_M1_MASK, VSUXSEG3EI16_V }, // 10260 |
| 31531 | { PseudoVSUXSEG3EI16_V_MF2_M2, VSUXSEG3EI16_V }, // 10261 |
| 31532 | { PseudoVSUXSEG3EI16_V_MF2_M2_MASK, VSUXSEG3EI16_V }, // 10262 |
| 31533 | { PseudoVSUXSEG3EI16_V_MF2_MF2, VSUXSEG3EI16_V }, // 10263 |
| 31534 | { PseudoVSUXSEG3EI16_V_MF2_MF2_MASK, VSUXSEG3EI16_V }, // 10264 |
| 31535 | { PseudoVSUXSEG3EI16_V_MF2_MF4, VSUXSEG3EI16_V }, // 10265 |
| 31536 | { PseudoVSUXSEG3EI16_V_MF2_MF4_MASK, VSUXSEG3EI16_V }, // 10266 |
| 31537 | { PseudoVSUXSEG3EI16_V_MF4_M1, VSUXSEG3EI16_V }, // 10267 |
| 31538 | { PseudoVSUXSEG3EI16_V_MF4_M1_MASK, VSUXSEG3EI16_V }, // 10268 |
| 31539 | { PseudoVSUXSEG3EI16_V_MF4_MF2, VSUXSEG3EI16_V }, // 10269 |
| 31540 | { PseudoVSUXSEG3EI16_V_MF4_MF2_MASK, VSUXSEG3EI16_V }, // 10270 |
| 31541 | { PseudoVSUXSEG3EI16_V_MF4_MF4, VSUXSEG3EI16_V }, // 10271 |
| 31542 | { PseudoVSUXSEG3EI16_V_MF4_MF4_MASK, VSUXSEG3EI16_V }, // 10272 |
| 31543 | { PseudoVSUXSEG3EI16_V_MF4_MF8, VSUXSEG3EI16_V }, // 10273 |
| 31544 | { PseudoVSUXSEG3EI16_V_MF4_MF8_MASK, VSUXSEG3EI16_V }, // 10274 |
| 31545 | { PseudoVSUXSEG3EI32_V_M1_M1, VSUXSEG3EI32_V }, // 10275 |
| 31546 | { PseudoVSUXSEG3EI32_V_M1_M1_MASK, VSUXSEG3EI32_V }, // 10276 |
| 31547 | { PseudoVSUXSEG3EI32_V_M1_M2, VSUXSEG3EI32_V }, // 10277 |
| 31548 | { PseudoVSUXSEG3EI32_V_M1_M2_MASK, VSUXSEG3EI32_V }, // 10278 |
| 31549 | { PseudoVSUXSEG3EI32_V_M1_MF2, VSUXSEG3EI32_V }, // 10279 |
| 31550 | { PseudoVSUXSEG3EI32_V_M1_MF2_MASK, VSUXSEG3EI32_V }, // 10280 |
| 31551 | { PseudoVSUXSEG3EI32_V_M1_MF4, VSUXSEG3EI32_V }, // 10281 |
| 31552 | { PseudoVSUXSEG3EI32_V_M1_MF4_MASK, VSUXSEG3EI32_V }, // 10282 |
| 31553 | { PseudoVSUXSEG3EI32_V_M2_M1, VSUXSEG3EI32_V }, // 10283 |
| 31554 | { PseudoVSUXSEG3EI32_V_M2_M1_MASK, VSUXSEG3EI32_V }, // 10284 |
| 31555 | { PseudoVSUXSEG3EI32_V_M2_M2, VSUXSEG3EI32_V }, // 10285 |
| 31556 | { PseudoVSUXSEG3EI32_V_M2_M2_MASK, VSUXSEG3EI32_V }, // 10286 |
| 31557 | { PseudoVSUXSEG3EI32_V_M2_MF2, VSUXSEG3EI32_V }, // 10287 |
| 31558 | { PseudoVSUXSEG3EI32_V_M2_MF2_MASK, VSUXSEG3EI32_V }, // 10288 |
| 31559 | { PseudoVSUXSEG3EI32_V_M4_M1, VSUXSEG3EI32_V }, // 10289 |
| 31560 | { PseudoVSUXSEG3EI32_V_M4_M1_MASK, VSUXSEG3EI32_V }, // 10290 |
| 31561 | { PseudoVSUXSEG3EI32_V_M4_M2, VSUXSEG3EI32_V }, // 10291 |
| 31562 | { PseudoVSUXSEG3EI32_V_M4_M2_MASK, VSUXSEG3EI32_V }, // 10292 |
| 31563 | { PseudoVSUXSEG3EI32_V_M8_M2, VSUXSEG3EI32_V }, // 10293 |
| 31564 | { PseudoVSUXSEG3EI32_V_M8_M2_MASK, VSUXSEG3EI32_V }, // 10294 |
| 31565 | { PseudoVSUXSEG3EI32_V_MF2_M1, VSUXSEG3EI32_V }, // 10295 |
| 31566 | { PseudoVSUXSEG3EI32_V_MF2_M1_MASK, VSUXSEG3EI32_V }, // 10296 |
| 31567 | { PseudoVSUXSEG3EI32_V_MF2_MF2, VSUXSEG3EI32_V }, // 10297 |
| 31568 | { PseudoVSUXSEG3EI32_V_MF2_MF2_MASK, VSUXSEG3EI32_V }, // 10298 |
| 31569 | { PseudoVSUXSEG3EI32_V_MF2_MF4, VSUXSEG3EI32_V }, // 10299 |
| 31570 | { PseudoVSUXSEG3EI32_V_MF2_MF4_MASK, VSUXSEG3EI32_V }, // 10300 |
| 31571 | { PseudoVSUXSEG3EI32_V_MF2_MF8, VSUXSEG3EI32_V }, // 10301 |
| 31572 | { PseudoVSUXSEG3EI32_V_MF2_MF8_MASK, VSUXSEG3EI32_V }, // 10302 |
| 31573 | { PseudoVSUXSEG3EI64_V_M1_M1, VSUXSEG3EI64_V }, // 10303 |
| 31574 | { PseudoVSUXSEG3EI64_V_M1_M1_MASK, VSUXSEG3EI64_V }, // 10304 |
| 31575 | { PseudoVSUXSEG3EI64_V_M1_MF2, VSUXSEG3EI64_V }, // 10305 |
| 31576 | { PseudoVSUXSEG3EI64_V_M1_MF2_MASK, VSUXSEG3EI64_V }, // 10306 |
| 31577 | { PseudoVSUXSEG3EI64_V_M1_MF4, VSUXSEG3EI64_V }, // 10307 |
| 31578 | { PseudoVSUXSEG3EI64_V_M1_MF4_MASK, VSUXSEG3EI64_V }, // 10308 |
| 31579 | { PseudoVSUXSEG3EI64_V_M1_MF8, VSUXSEG3EI64_V }, // 10309 |
| 31580 | { PseudoVSUXSEG3EI64_V_M1_MF8_MASK, VSUXSEG3EI64_V }, // 10310 |
| 31581 | { PseudoVSUXSEG3EI64_V_M2_M1, VSUXSEG3EI64_V }, // 10311 |
| 31582 | { PseudoVSUXSEG3EI64_V_M2_M1_MASK, VSUXSEG3EI64_V }, // 10312 |
| 31583 | { PseudoVSUXSEG3EI64_V_M2_M2, VSUXSEG3EI64_V }, // 10313 |
| 31584 | { PseudoVSUXSEG3EI64_V_M2_M2_MASK, VSUXSEG3EI64_V }, // 10314 |
| 31585 | { PseudoVSUXSEG3EI64_V_M2_MF2, VSUXSEG3EI64_V }, // 10315 |
| 31586 | { PseudoVSUXSEG3EI64_V_M2_MF2_MASK, VSUXSEG3EI64_V }, // 10316 |
| 31587 | { PseudoVSUXSEG3EI64_V_M2_MF4, VSUXSEG3EI64_V }, // 10317 |
| 31588 | { PseudoVSUXSEG3EI64_V_M2_MF4_MASK, VSUXSEG3EI64_V }, // 10318 |
| 31589 | { PseudoVSUXSEG3EI64_V_M4_M1, VSUXSEG3EI64_V }, // 10319 |
| 31590 | { PseudoVSUXSEG3EI64_V_M4_M1_MASK, VSUXSEG3EI64_V }, // 10320 |
| 31591 | { PseudoVSUXSEG3EI64_V_M4_M2, VSUXSEG3EI64_V }, // 10321 |
| 31592 | { PseudoVSUXSEG3EI64_V_M4_M2_MASK, VSUXSEG3EI64_V }, // 10322 |
| 31593 | { PseudoVSUXSEG3EI64_V_M4_MF2, VSUXSEG3EI64_V }, // 10323 |
| 31594 | { PseudoVSUXSEG3EI64_V_M4_MF2_MASK, VSUXSEG3EI64_V }, // 10324 |
| 31595 | { PseudoVSUXSEG3EI64_V_M8_M1, VSUXSEG3EI64_V }, // 10325 |
| 31596 | { PseudoVSUXSEG3EI64_V_M8_M1_MASK, VSUXSEG3EI64_V }, // 10326 |
| 31597 | { PseudoVSUXSEG3EI64_V_M8_M2, VSUXSEG3EI64_V }, // 10327 |
| 31598 | { PseudoVSUXSEG3EI64_V_M8_M2_MASK, VSUXSEG3EI64_V }, // 10328 |
| 31599 | { PseudoVSUXSEG3EI8_V_M1_M1, VSUXSEG3EI8_V }, // 10329 |
| 31600 | { PseudoVSUXSEG3EI8_V_M1_M1_MASK, VSUXSEG3EI8_V }, // 10330 |
| 31601 | { PseudoVSUXSEG3EI8_V_M1_M2, VSUXSEG3EI8_V }, // 10331 |
| 31602 | { PseudoVSUXSEG3EI8_V_M1_M2_MASK, VSUXSEG3EI8_V }, // 10332 |
| 31603 | { PseudoVSUXSEG3EI8_V_M2_M2, VSUXSEG3EI8_V }, // 10333 |
| 31604 | { PseudoVSUXSEG3EI8_V_M2_M2_MASK, VSUXSEG3EI8_V }, // 10334 |
| 31605 | { PseudoVSUXSEG3EI8_V_MF2_M1, VSUXSEG3EI8_V }, // 10335 |
| 31606 | { PseudoVSUXSEG3EI8_V_MF2_M1_MASK, VSUXSEG3EI8_V }, // 10336 |
| 31607 | { PseudoVSUXSEG3EI8_V_MF2_M2, VSUXSEG3EI8_V }, // 10337 |
| 31608 | { PseudoVSUXSEG3EI8_V_MF2_M2_MASK, VSUXSEG3EI8_V }, // 10338 |
| 31609 | { PseudoVSUXSEG3EI8_V_MF2_MF2, VSUXSEG3EI8_V }, // 10339 |
| 31610 | { PseudoVSUXSEG3EI8_V_MF2_MF2_MASK, VSUXSEG3EI8_V }, // 10340 |
| 31611 | { PseudoVSUXSEG3EI8_V_MF4_M1, VSUXSEG3EI8_V }, // 10341 |
| 31612 | { PseudoVSUXSEG3EI8_V_MF4_M1_MASK, VSUXSEG3EI8_V }, // 10342 |
| 31613 | { PseudoVSUXSEG3EI8_V_MF4_M2, VSUXSEG3EI8_V }, // 10343 |
| 31614 | { PseudoVSUXSEG3EI8_V_MF4_M2_MASK, VSUXSEG3EI8_V }, // 10344 |
| 31615 | { PseudoVSUXSEG3EI8_V_MF4_MF2, VSUXSEG3EI8_V }, // 10345 |
| 31616 | { PseudoVSUXSEG3EI8_V_MF4_MF2_MASK, VSUXSEG3EI8_V }, // 10346 |
| 31617 | { PseudoVSUXSEG3EI8_V_MF4_MF4, VSUXSEG3EI8_V }, // 10347 |
| 31618 | { PseudoVSUXSEG3EI8_V_MF4_MF4_MASK, VSUXSEG3EI8_V }, // 10348 |
| 31619 | { PseudoVSUXSEG3EI8_V_MF8_M1, VSUXSEG3EI8_V }, // 10349 |
| 31620 | { PseudoVSUXSEG3EI8_V_MF8_M1_MASK, VSUXSEG3EI8_V }, // 10350 |
| 31621 | { PseudoVSUXSEG3EI8_V_MF8_MF2, VSUXSEG3EI8_V }, // 10351 |
| 31622 | { PseudoVSUXSEG3EI8_V_MF8_MF2_MASK, VSUXSEG3EI8_V }, // 10352 |
| 31623 | { PseudoVSUXSEG3EI8_V_MF8_MF4, VSUXSEG3EI8_V }, // 10353 |
| 31624 | { PseudoVSUXSEG3EI8_V_MF8_MF4_MASK, VSUXSEG3EI8_V }, // 10354 |
| 31625 | { PseudoVSUXSEG3EI8_V_MF8_MF8, VSUXSEG3EI8_V }, // 10355 |
| 31626 | { PseudoVSUXSEG3EI8_V_MF8_MF8_MASK, VSUXSEG3EI8_V }, // 10356 |
| 31627 | { PseudoVSUXSEG4EI16_V_M1_M1, VSUXSEG4EI16_V }, // 10357 |
| 31628 | { PseudoVSUXSEG4EI16_V_M1_M1_MASK, VSUXSEG4EI16_V }, // 10358 |
| 31629 | { PseudoVSUXSEG4EI16_V_M1_M2, VSUXSEG4EI16_V }, // 10359 |
| 31630 | { PseudoVSUXSEG4EI16_V_M1_M2_MASK, VSUXSEG4EI16_V }, // 10360 |
| 31631 | { PseudoVSUXSEG4EI16_V_M1_MF2, VSUXSEG4EI16_V }, // 10361 |
| 31632 | { PseudoVSUXSEG4EI16_V_M1_MF2_MASK, VSUXSEG4EI16_V }, // 10362 |
| 31633 | { PseudoVSUXSEG4EI16_V_M2_M1, VSUXSEG4EI16_V }, // 10363 |
| 31634 | { PseudoVSUXSEG4EI16_V_M2_M1_MASK, VSUXSEG4EI16_V }, // 10364 |
| 31635 | { PseudoVSUXSEG4EI16_V_M2_M2, VSUXSEG4EI16_V }, // 10365 |
| 31636 | { PseudoVSUXSEG4EI16_V_M2_M2_MASK, VSUXSEG4EI16_V }, // 10366 |
| 31637 | { PseudoVSUXSEG4EI16_V_M4_M2, VSUXSEG4EI16_V }, // 10367 |
| 31638 | { PseudoVSUXSEG4EI16_V_M4_M2_MASK, VSUXSEG4EI16_V }, // 10368 |
| 31639 | { PseudoVSUXSEG4EI16_V_MF2_M1, VSUXSEG4EI16_V }, // 10369 |
| 31640 | { PseudoVSUXSEG4EI16_V_MF2_M1_MASK, VSUXSEG4EI16_V }, // 10370 |
| 31641 | { PseudoVSUXSEG4EI16_V_MF2_M2, VSUXSEG4EI16_V }, // 10371 |
| 31642 | { PseudoVSUXSEG4EI16_V_MF2_M2_MASK, VSUXSEG4EI16_V }, // 10372 |
| 31643 | { PseudoVSUXSEG4EI16_V_MF2_MF2, VSUXSEG4EI16_V }, // 10373 |
| 31644 | { PseudoVSUXSEG4EI16_V_MF2_MF2_MASK, VSUXSEG4EI16_V }, // 10374 |
| 31645 | { PseudoVSUXSEG4EI16_V_MF2_MF4, VSUXSEG4EI16_V }, // 10375 |
| 31646 | { PseudoVSUXSEG4EI16_V_MF2_MF4_MASK, VSUXSEG4EI16_V }, // 10376 |
| 31647 | { PseudoVSUXSEG4EI16_V_MF4_M1, VSUXSEG4EI16_V }, // 10377 |
| 31648 | { PseudoVSUXSEG4EI16_V_MF4_M1_MASK, VSUXSEG4EI16_V }, // 10378 |
| 31649 | { PseudoVSUXSEG4EI16_V_MF4_MF2, VSUXSEG4EI16_V }, // 10379 |
| 31650 | { PseudoVSUXSEG4EI16_V_MF4_MF2_MASK, VSUXSEG4EI16_V }, // 10380 |
| 31651 | { PseudoVSUXSEG4EI16_V_MF4_MF4, VSUXSEG4EI16_V }, // 10381 |
| 31652 | { PseudoVSUXSEG4EI16_V_MF4_MF4_MASK, VSUXSEG4EI16_V }, // 10382 |
| 31653 | { PseudoVSUXSEG4EI16_V_MF4_MF8, VSUXSEG4EI16_V }, // 10383 |
| 31654 | { PseudoVSUXSEG4EI16_V_MF4_MF8_MASK, VSUXSEG4EI16_V }, // 10384 |
| 31655 | { PseudoVSUXSEG4EI32_V_M1_M1, VSUXSEG4EI32_V }, // 10385 |
| 31656 | { PseudoVSUXSEG4EI32_V_M1_M1_MASK, VSUXSEG4EI32_V }, // 10386 |
| 31657 | { PseudoVSUXSEG4EI32_V_M1_M2, VSUXSEG4EI32_V }, // 10387 |
| 31658 | { PseudoVSUXSEG4EI32_V_M1_M2_MASK, VSUXSEG4EI32_V }, // 10388 |
| 31659 | { PseudoVSUXSEG4EI32_V_M1_MF2, VSUXSEG4EI32_V }, // 10389 |
| 31660 | { PseudoVSUXSEG4EI32_V_M1_MF2_MASK, VSUXSEG4EI32_V }, // 10390 |
| 31661 | { PseudoVSUXSEG4EI32_V_M1_MF4, VSUXSEG4EI32_V }, // 10391 |
| 31662 | { PseudoVSUXSEG4EI32_V_M1_MF4_MASK, VSUXSEG4EI32_V }, // 10392 |
| 31663 | { PseudoVSUXSEG4EI32_V_M2_M1, VSUXSEG4EI32_V }, // 10393 |
| 31664 | { PseudoVSUXSEG4EI32_V_M2_M1_MASK, VSUXSEG4EI32_V }, // 10394 |
| 31665 | { PseudoVSUXSEG4EI32_V_M2_M2, VSUXSEG4EI32_V }, // 10395 |
| 31666 | { PseudoVSUXSEG4EI32_V_M2_M2_MASK, VSUXSEG4EI32_V }, // 10396 |
| 31667 | { PseudoVSUXSEG4EI32_V_M2_MF2, VSUXSEG4EI32_V }, // 10397 |
| 31668 | { PseudoVSUXSEG4EI32_V_M2_MF2_MASK, VSUXSEG4EI32_V }, // 10398 |
| 31669 | { PseudoVSUXSEG4EI32_V_M4_M1, VSUXSEG4EI32_V }, // 10399 |
| 31670 | { PseudoVSUXSEG4EI32_V_M4_M1_MASK, VSUXSEG4EI32_V }, // 10400 |
| 31671 | { PseudoVSUXSEG4EI32_V_M4_M2, VSUXSEG4EI32_V }, // 10401 |
| 31672 | { PseudoVSUXSEG4EI32_V_M4_M2_MASK, VSUXSEG4EI32_V }, // 10402 |
| 31673 | { PseudoVSUXSEG4EI32_V_M8_M2, VSUXSEG4EI32_V }, // 10403 |
| 31674 | { PseudoVSUXSEG4EI32_V_M8_M2_MASK, VSUXSEG4EI32_V }, // 10404 |
| 31675 | { PseudoVSUXSEG4EI32_V_MF2_M1, VSUXSEG4EI32_V }, // 10405 |
| 31676 | { PseudoVSUXSEG4EI32_V_MF2_M1_MASK, VSUXSEG4EI32_V }, // 10406 |
| 31677 | { PseudoVSUXSEG4EI32_V_MF2_MF2, VSUXSEG4EI32_V }, // 10407 |
| 31678 | { PseudoVSUXSEG4EI32_V_MF2_MF2_MASK, VSUXSEG4EI32_V }, // 10408 |
| 31679 | { PseudoVSUXSEG4EI32_V_MF2_MF4, VSUXSEG4EI32_V }, // 10409 |
| 31680 | { PseudoVSUXSEG4EI32_V_MF2_MF4_MASK, VSUXSEG4EI32_V }, // 10410 |
| 31681 | { PseudoVSUXSEG4EI32_V_MF2_MF8, VSUXSEG4EI32_V }, // 10411 |
| 31682 | { PseudoVSUXSEG4EI32_V_MF2_MF8_MASK, VSUXSEG4EI32_V }, // 10412 |
| 31683 | { PseudoVSUXSEG4EI64_V_M1_M1, VSUXSEG4EI64_V }, // 10413 |
| 31684 | { PseudoVSUXSEG4EI64_V_M1_M1_MASK, VSUXSEG4EI64_V }, // 10414 |
| 31685 | { PseudoVSUXSEG4EI64_V_M1_MF2, VSUXSEG4EI64_V }, // 10415 |
| 31686 | { PseudoVSUXSEG4EI64_V_M1_MF2_MASK, VSUXSEG4EI64_V }, // 10416 |
| 31687 | { PseudoVSUXSEG4EI64_V_M1_MF4, VSUXSEG4EI64_V }, // 10417 |
| 31688 | { PseudoVSUXSEG4EI64_V_M1_MF4_MASK, VSUXSEG4EI64_V }, // 10418 |
| 31689 | { PseudoVSUXSEG4EI64_V_M1_MF8, VSUXSEG4EI64_V }, // 10419 |
| 31690 | { PseudoVSUXSEG4EI64_V_M1_MF8_MASK, VSUXSEG4EI64_V }, // 10420 |
| 31691 | { PseudoVSUXSEG4EI64_V_M2_M1, VSUXSEG4EI64_V }, // 10421 |
| 31692 | { PseudoVSUXSEG4EI64_V_M2_M1_MASK, VSUXSEG4EI64_V }, // 10422 |
| 31693 | { PseudoVSUXSEG4EI64_V_M2_M2, VSUXSEG4EI64_V }, // 10423 |
| 31694 | { PseudoVSUXSEG4EI64_V_M2_M2_MASK, VSUXSEG4EI64_V }, // 10424 |
| 31695 | { PseudoVSUXSEG4EI64_V_M2_MF2, VSUXSEG4EI64_V }, // 10425 |
| 31696 | { PseudoVSUXSEG4EI64_V_M2_MF2_MASK, VSUXSEG4EI64_V }, // 10426 |
| 31697 | { PseudoVSUXSEG4EI64_V_M2_MF4, VSUXSEG4EI64_V }, // 10427 |
| 31698 | { PseudoVSUXSEG4EI64_V_M2_MF4_MASK, VSUXSEG4EI64_V }, // 10428 |
| 31699 | { PseudoVSUXSEG4EI64_V_M4_M1, VSUXSEG4EI64_V }, // 10429 |
| 31700 | { PseudoVSUXSEG4EI64_V_M4_M1_MASK, VSUXSEG4EI64_V }, // 10430 |
| 31701 | { PseudoVSUXSEG4EI64_V_M4_M2, VSUXSEG4EI64_V }, // 10431 |
| 31702 | { PseudoVSUXSEG4EI64_V_M4_M2_MASK, VSUXSEG4EI64_V }, // 10432 |
| 31703 | { PseudoVSUXSEG4EI64_V_M4_MF2, VSUXSEG4EI64_V }, // 10433 |
| 31704 | { PseudoVSUXSEG4EI64_V_M4_MF2_MASK, VSUXSEG4EI64_V }, // 10434 |
| 31705 | { PseudoVSUXSEG4EI64_V_M8_M1, VSUXSEG4EI64_V }, // 10435 |
| 31706 | { PseudoVSUXSEG4EI64_V_M8_M1_MASK, VSUXSEG4EI64_V }, // 10436 |
| 31707 | { PseudoVSUXSEG4EI64_V_M8_M2, VSUXSEG4EI64_V }, // 10437 |
| 31708 | { PseudoVSUXSEG4EI64_V_M8_M2_MASK, VSUXSEG4EI64_V }, // 10438 |
| 31709 | { PseudoVSUXSEG4EI8_V_M1_M1, VSUXSEG4EI8_V }, // 10439 |
| 31710 | { PseudoVSUXSEG4EI8_V_M1_M1_MASK, VSUXSEG4EI8_V }, // 10440 |
| 31711 | { PseudoVSUXSEG4EI8_V_M1_M2, VSUXSEG4EI8_V }, // 10441 |
| 31712 | { PseudoVSUXSEG4EI8_V_M1_M2_MASK, VSUXSEG4EI8_V }, // 10442 |
| 31713 | { PseudoVSUXSEG4EI8_V_M2_M2, VSUXSEG4EI8_V }, // 10443 |
| 31714 | { PseudoVSUXSEG4EI8_V_M2_M2_MASK, VSUXSEG4EI8_V }, // 10444 |
| 31715 | { PseudoVSUXSEG4EI8_V_MF2_M1, VSUXSEG4EI8_V }, // 10445 |
| 31716 | { PseudoVSUXSEG4EI8_V_MF2_M1_MASK, VSUXSEG4EI8_V }, // 10446 |
| 31717 | { PseudoVSUXSEG4EI8_V_MF2_M2, VSUXSEG4EI8_V }, // 10447 |
| 31718 | { PseudoVSUXSEG4EI8_V_MF2_M2_MASK, VSUXSEG4EI8_V }, // 10448 |
| 31719 | { PseudoVSUXSEG4EI8_V_MF2_MF2, VSUXSEG4EI8_V }, // 10449 |
| 31720 | { PseudoVSUXSEG4EI8_V_MF2_MF2_MASK, VSUXSEG4EI8_V }, // 10450 |
| 31721 | { PseudoVSUXSEG4EI8_V_MF4_M1, VSUXSEG4EI8_V }, // 10451 |
| 31722 | { PseudoVSUXSEG4EI8_V_MF4_M1_MASK, VSUXSEG4EI8_V }, // 10452 |
| 31723 | { PseudoVSUXSEG4EI8_V_MF4_M2, VSUXSEG4EI8_V }, // 10453 |
| 31724 | { PseudoVSUXSEG4EI8_V_MF4_M2_MASK, VSUXSEG4EI8_V }, // 10454 |
| 31725 | { PseudoVSUXSEG4EI8_V_MF4_MF2, VSUXSEG4EI8_V }, // 10455 |
| 31726 | { PseudoVSUXSEG4EI8_V_MF4_MF2_MASK, VSUXSEG4EI8_V }, // 10456 |
| 31727 | { PseudoVSUXSEG4EI8_V_MF4_MF4, VSUXSEG4EI8_V }, // 10457 |
| 31728 | { PseudoVSUXSEG4EI8_V_MF4_MF4_MASK, VSUXSEG4EI8_V }, // 10458 |
| 31729 | { PseudoVSUXSEG4EI8_V_MF8_M1, VSUXSEG4EI8_V }, // 10459 |
| 31730 | { PseudoVSUXSEG4EI8_V_MF8_M1_MASK, VSUXSEG4EI8_V }, // 10460 |
| 31731 | { PseudoVSUXSEG4EI8_V_MF8_MF2, VSUXSEG4EI8_V }, // 10461 |
| 31732 | { PseudoVSUXSEG4EI8_V_MF8_MF2_MASK, VSUXSEG4EI8_V }, // 10462 |
| 31733 | { PseudoVSUXSEG4EI8_V_MF8_MF4, VSUXSEG4EI8_V }, // 10463 |
| 31734 | { PseudoVSUXSEG4EI8_V_MF8_MF4_MASK, VSUXSEG4EI8_V }, // 10464 |
| 31735 | { PseudoVSUXSEG4EI8_V_MF8_MF8, VSUXSEG4EI8_V }, // 10465 |
| 31736 | { PseudoVSUXSEG4EI8_V_MF8_MF8_MASK, VSUXSEG4EI8_V }, // 10466 |
| 31737 | { PseudoVSUXSEG5EI16_V_M1_M1, VSUXSEG5EI16_V }, // 10467 |
| 31738 | { PseudoVSUXSEG5EI16_V_M1_M1_MASK, VSUXSEG5EI16_V }, // 10468 |
| 31739 | { PseudoVSUXSEG5EI16_V_M1_MF2, VSUXSEG5EI16_V }, // 10469 |
| 31740 | { PseudoVSUXSEG5EI16_V_M1_MF2_MASK, VSUXSEG5EI16_V }, // 10470 |
| 31741 | { PseudoVSUXSEG5EI16_V_M2_M1, VSUXSEG5EI16_V }, // 10471 |
| 31742 | { PseudoVSUXSEG5EI16_V_M2_M1_MASK, VSUXSEG5EI16_V }, // 10472 |
| 31743 | { PseudoVSUXSEG5EI16_V_MF2_M1, VSUXSEG5EI16_V }, // 10473 |
| 31744 | { PseudoVSUXSEG5EI16_V_MF2_M1_MASK, VSUXSEG5EI16_V }, // 10474 |
| 31745 | { PseudoVSUXSEG5EI16_V_MF2_MF2, VSUXSEG5EI16_V }, // 10475 |
| 31746 | { PseudoVSUXSEG5EI16_V_MF2_MF2_MASK, VSUXSEG5EI16_V }, // 10476 |
| 31747 | { PseudoVSUXSEG5EI16_V_MF2_MF4, VSUXSEG5EI16_V }, // 10477 |
| 31748 | { PseudoVSUXSEG5EI16_V_MF2_MF4_MASK, VSUXSEG5EI16_V }, // 10478 |
| 31749 | { PseudoVSUXSEG5EI16_V_MF4_M1, VSUXSEG5EI16_V }, // 10479 |
| 31750 | { PseudoVSUXSEG5EI16_V_MF4_M1_MASK, VSUXSEG5EI16_V }, // 10480 |
| 31751 | { PseudoVSUXSEG5EI16_V_MF4_MF2, VSUXSEG5EI16_V }, // 10481 |
| 31752 | { PseudoVSUXSEG5EI16_V_MF4_MF2_MASK, VSUXSEG5EI16_V }, // 10482 |
| 31753 | { PseudoVSUXSEG5EI16_V_MF4_MF4, VSUXSEG5EI16_V }, // 10483 |
| 31754 | { PseudoVSUXSEG5EI16_V_MF4_MF4_MASK, VSUXSEG5EI16_V }, // 10484 |
| 31755 | { PseudoVSUXSEG5EI16_V_MF4_MF8, VSUXSEG5EI16_V }, // 10485 |
| 31756 | { PseudoVSUXSEG5EI16_V_MF4_MF8_MASK, VSUXSEG5EI16_V }, // 10486 |
| 31757 | { PseudoVSUXSEG5EI32_V_M1_M1, VSUXSEG5EI32_V }, // 10487 |
| 31758 | { PseudoVSUXSEG5EI32_V_M1_M1_MASK, VSUXSEG5EI32_V }, // 10488 |
| 31759 | { PseudoVSUXSEG5EI32_V_M1_MF2, VSUXSEG5EI32_V }, // 10489 |
| 31760 | { PseudoVSUXSEG5EI32_V_M1_MF2_MASK, VSUXSEG5EI32_V }, // 10490 |
| 31761 | { PseudoVSUXSEG5EI32_V_M1_MF4, VSUXSEG5EI32_V }, // 10491 |
| 31762 | { PseudoVSUXSEG5EI32_V_M1_MF4_MASK, VSUXSEG5EI32_V }, // 10492 |
| 31763 | { PseudoVSUXSEG5EI32_V_M2_M1, VSUXSEG5EI32_V }, // 10493 |
| 31764 | { PseudoVSUXSEG5EI32_V_M2_M1_MASK, VSUXSEG5EI32_V }, // 10494 |
| 31765 | { PseudoVSUXSEG5EI32_V_M2_MF2, VSUXSEG5EI32_V }, // 10495 |
| 31766 | { PseudoVSUXSEG5EI32_V_M2_MF2_MASK, VSUXSEG5EI32_V }, // 10496 |
| 31767 | { PseudoVSUXSEG5EI32_V_M4_M1, VSUXSEG5EI32_V }, // 10497 |
| 31768 | { PseudoVSUXSEG5EI32_V_M4_M1_MASK, VSUXSEG5EI32_V }, // 10498 |
| 31769 | { PseudoVSUXSEG5EI32_V_MF2_M1, VSUXSEG5EI32_V }, // 10499 |
| 31770 | { PseudoVSUXSEG5EI32_V_MF2_M1_MASK, VSUXSEG5EI32_V }, // 10500 |
| 31771 | { PseudoVSUXSEG5EI32_V_MF2_MF2, VSUXSEG5EI32_V }, // 10501 |
| 31772 | { PseudoVSUXSEG5EI32_V_MF2_MF2_MASK, VSUXSEG5EI32_V }, // 10502 |
| 31773 | { PseudoVSUXSEG5EI32_V_MF2_MF4, VSUXSEG5EI32_V }, // 10503 |
| 31774 | { PseudoVSUXSEG5EI32_V_MF2_MF4_MASK, VSUXSEG5EI32_V }, // 10504 |
| 31775 | { PseudoVSUXSEG5EI32_V_MF2_MF8, VSUXSEG5EI32_V }, // 10505 |
| 31776 | { PseudoVSUXSEG5EI32_V_MF2_MF8_MASK, VSUXSEG5EI32_V }, // 10506 |
| 31777 | { PseudoVSUXSEG5EI64_V_M1_M1, VSUXSEG5EI64_V }, // 10507 |
| 31778 | { PseudoVSUXSEG5EI64_V_M1_M1_MASK, VSUXSEG5EI64_V }, // 10508 |
| 31779 | { PseudoVSUXSEG5EI64_V_M1_MF2, VSUXSEG5EI64_V }, // 10509 |
| 31780 | { PseudoVSUXSEG5EI64_V_M1_MF2_MASK, VSUXSEG5EI64_V }, // 10510 |
| 31781 | { PseudoVSUXSEG5EI64_V_M1_MF4, VSUXSEG5EI64_V }, // 10511 |
| 31782 | { PseudoVSUXSEG5EI64_V_M1_MF4_MASK, VSUXSEG5EI64_V }, // 10512 |
| 31783 | { PseudoVSUXSEG5EI64_V_M1_MF8, VSUXSEG5EI64_V }, // 10513 |
| 31784 | { PseudoVSUXSEG5EI64_V_M1_MF8_MASK, VSUXSEG5EI64_V }, // 10514 |
| 31785 | { PseudoVSUXSEG5EI64_V_M2_M1, VSUXSEG5EI64_V }, // 10515 |
| 31786 | { PseudoVSUXSEG5EI64_V_M2_M1_MASK, VSUXSEG5EI64_V }, // 10516 |
| 31787 | { PseudoVSUXSEG5EI64_V_M2_MF2, VSUXSEG5EI64_V }, // 10517 |
| 31788 | { PseudoVSUXSEG5EI64_V_M2_MF2_MASK, VSUXSEG5EI64_V }, // 10518 |
| 31789 | { PseudoVSUXSEG5EI64_V_M2_MF4, VSUXSEG5EI64_V }, // 10519 |
| 31790 | { PseudoVSUXSEG5EI64_V_M2_MF4_MASK, VSUXSEG5EI64_V }, // 10520 |
| 31791 | { PseudoVSUXSEG5EI64_V_M4_M1, VSUXSEG5EI64_V }, // 10521 |
| 31792 | { PseudoVSUXSEG5EI64_V_M4_M1_MASK, VSUXSEG5EI64_V }, // 10522 |
| 31793 | { PseudoVSUXSEG5EI64_V_M4_MF2, VSUXSEG5EI64_V }, // 10523 |
| 31794 | { PseudoVSUXSEG5EI64_V_M4_MF2_MASK, VSUXSEG5EI64_V }, // 10524 |
| 31795 | { PseudoVSUXSEG5EI64_V_M8_M1, VSUXSEG5EI64_V }, // 10525 |
| 31796 | { PseudoVSUXSEG5EI64_V_M8_M1_MASK, VSUXSEG5EI64_V }, // 10526 |
| 31797 | { PseudoVSUXSEG5EI8_V_M1_M1, VSUXSEG5EI8_V }, // 10527 |
| 31798 | { PseudoVSUXSEG5EI8_V_M1_M1_MASK, VSUXSEG5EI8_V }, // 10528 |
| 31799 | { PseudoVSUXSEG5EI8_V_MF2_M1, VSUXSEG5EI8_V }, // 10529 |
| 31800 | { PseudoVSUXSEG5EI8_V_MF2_M1_MASK, VSUXSEG5EI8_V }, // 10530 |
| 31801 | { PseudoVSUXSEG5EI8_V_MF2_MF2, VSUXSEG5EI8_V }, // 10531 |
| 31802 | { PseudoVSUXSEG5EI8_V_MF2_MF2_MASK, VSUXSEG5EI8_V }, // 10532 |
| 31803 | { PseudoVSUXSEG5EI8_V_MF4_M1, VSUXSEG5EI8_V }, // 10533 |
| 31804 | { PseudoVSUXSEG5EI8_V_MF4_M1_MASK, VSUXSEG5EI8_V }, // 10534 |
| 31805 | { PseudoVSUXSEG5EI8_V_MF4_MF2, VSUXSEG5EI8_V }, // 10535 |
| 31806 | { PseudoVSUXSEG5EI8_V_MF4_MF2_MASK, VSUXSEG5EI8_V }, // 10536 |
| 31807 | { PseudoVSUXSEG5EI8_V_MF4_MF4, VSUXSEG5EI8_V }, // 10537 |
| 31808 | { PseudoVSUXSEG5EI8_V_MF4_MF4_MASK, VSUXSEG5EI8_V }, // 10538 |
| 31809 | { PseudoVSUXSEG5EI8_V_MF8_M1, VSUXSEG5EI8_V }, // 10539 |
| 31810 | { PseudoVSUXSEG5EI8_V_MF8_M1_MASK, VSUXSEG5EI8_V }, // 10540 |
| 31811 | { PseudoVSUXSEG5EI8_V_MF8_MF2, VSUXSEG5EI8_V }, // 10541 |
| 31812 | { PseudoVSUXSEG5EI8_V_MF8_MF2_MASK, VSUXSEG5EI8_V }, // 10542 |
| 31813 | { PseudoVSUXSEG5EI8_V_MF8_MF4, VSUXSEG5EI8_V }, // 10543 |
| 31814 | { PseudoVSUXSEG5EI8_V_MF8_MF4_MASK, VSUXSEG5EI8_V }, // 10544 |
| 31815 | { PseudoVSUXSEG5EI8_V_MF8_MF8, VSUXSEG5EI8_V }, // 10545 |
| 31816 | { PseudoVSUXSEG5EI8_V_MF8_MF8_MASK, VSUXSEG5EI8_V }, // 10546 |
| 31817 | { PseudoVSUXSEG6EI16_V_M1_M1, VSUXSEG6EI16_V }, // 10547 |
| 31818 | { PseudoVSUXSEG6EI16_V_M1_M1_MASK, VSUXSEG6EI16_V }, // 10548 |
| 31819 | { PseudoVSUXSEG6EI16_V_M1_MF2, VSUXSEG6EI16_V }, // 10549 |
| 31820 | { PseudoVSUXSEG6EI16_V_M1_MF2_MASK, VSUXSEG6EI16_V }, // 10550 |
| 31821 | { PseudoVSUXSEG6EI16_V_M2_M1, VSUXSEG6EI16_V }, // 10551 |
| 31822 | { PseudoVSUXSEG6EI16_V_M2_M1_MASK, VSUXSEG6EI16_V }, // 10552 |
| 31823 | { PseudoVSUXSEG6EI16_V_MF2_M1, VSUXSEG6EI16_V }, // 10553 |
| 31824 | { PseudoVSUXSEG6EI16_V_MF2_M1_MASK, VSUXSEG6EI16_V }, // 10554 |
| 31825 | { PseudoVSUXSEG6EI16_V_MF2_MF2, VSUXSEG6EI16_V }, // 10555 |
| 31826 | { PseudoVSUXSEG6EI16_V_MF2_MF2_MASK, VSUXSEG6EI16_V }, // 10556 |
| 31827 | { PseudoVSUXSEG6EI16_V_MF2_MF4, VSUXSEG6EI16_V }, // 10557 |
| 31828 | { PseudoVSUXSEG6EI16_V_MF2_MF4_MASK, VSUXSEG6EI16_V }, // 10558 |
| 31829 | { PseudoVSUXSEG6EI16_V_MF4_M1, VSUXSEG6EI16_V }, // 10559 |
| 31830 | { PseudoVSUXSEG6EI16_V_MF4_M1_MASK, VSUXSEG6EI16_V }, // 10560 |
| 31831 | { PseudoVSUXSEG6EI16_V_MF4_MF2, VSUXSEG6EI16_V }, // 10561 |
| 31832 | { PseudoVSUXSEG6EI16_V_MF4_MF2_MASK, VSUXSEG6EI16_V }, // 10562 |
| 31833 | { PseudoVSUXSEG6EI16_V_MF4_MF4, VSUXSEG6EI16_V }, // 10563 |
| 31834 | { PseudoVSUXSEG6EI16_V_MF4_MF4_MASK, VSUXSEG6EI16_V }, // 10564 |
| 31835 | { PseudoVSUXSEG6EI16_V_MF4_MF8, VSUXSEG6EI16_V }, // 10565 |
| 31836 | { PseudoVSUXSEG6EI16_V_MF4_MF8_MASK, VSUXSEG6EI16_V }, // 10566 |
| 31837 | { PseudoVSUXSEG6EI32_V_M1_M1, VSUXSEG6EI32_V }, // 10567 |
| 31838 | { PseudoVSUXSEG6EI32_V_M1_M1_MASK, VSUXSEG6EI32_V }, // 10568 |
| 31839 | { PseudoVSUXSEG6EI32_V_M1_MF2, VSUXSEG6EI32_V }, // 10569 |
| 31840 | { PseudoVSUXSEG6EI32_V_M1_MF2_MASK, VSUXSEG6EI32_V }, // 10570 |
| 31841 | { PseudoVSUXSEG6EI32_V_M1_MF4, VSUXSEG6EI32_V }, // 10571 |
| 31842 | { PseudoVSUXSEG6EI32_V_M1_MF4_MASK, VSUXSEG6EI32_V }, // 10572 |
| 31843 | { PseudoVSUXSEG6EI32_V_M2_M1, VSUXSEG6EI32_V }, // 10573 |
| 31844 | { PseudoVSUXSEG6EI32_V_M2_M1_MASK, VSUXSEG6EI32_V }, // 10574 |
| 31845 | { PseudoVSUXSEG6EI32_V_M2_MF2, VSUXSEG6EI32_V }, // 10575 |
| 31846 | { PseudoVSUXSEG6EI32_V_M2_MF2_MASK, VSUXSEG6EI32_V }, // 10576 |
| 31847 | { PseudoVSUXSEG6EI32_V_M4_M1, VSUXSEG6EI32_V }, // 10577 |
| 31848 | { PseudoVSUXSEG6EI32_V_M4_M1_MASK, VSUXSEG6EI32_V }, // 10578 |
| 31849 | { PseudoVSUXSEG6EI32_V_MF2_M1, VSUXSEG6EI32_V }, // 10579 |
| 31850 | { PseudoVSUXSEG6EI32_V_MF2_M1_MASK, VSUXSEG6EI32_V }, // 10580 |
| 31851 | { PseudoVSUXSEG6EI32_V_MF2_MF2, VSUXSEG6EI32_V }, // 10581 |
| 31852 | { PseudoVSUXSEG6EI32_V_MF2_MF2_MASK, VSUXSEG6EI32_V }, // 10582 |
| 31853 | { PseudoVSUXSEG6EI32_V_MF2_MF4, VSUXSEG6EI32_V }, // 10583 |
| 31854 | { PseudoVSUXSEG6EI32_V_MF2_MF4_MASK, VSUXSEG6EI32_V }, // 10584 |
| 31855 | { PseudoVSUXSEG6EI32_V_MF2_MF8, VSUXSEG6EI32_V }, // 10585 |
| 31856 | { PseudoVSUXSEG6EI32_V_MF2_MF8_MASK, VSUXSEG6EI32_V }, // 10586 |
| 31857 | { PseudoVSUXSEG6EI64_V_M1_M1, VSUXSEG6EI64_V }, // 10587 |
| 31858 | { PseudoVSUXSEG6EI64_V_M1_M1_MASK, VSUXSEG6EI64_V }, // 10588 |
| 31859 | { PseudoVSUXSEG6EI64_V_M1_MF2, VSUXSEG6EI64_V }, // 10589 |
| 31860 | { PseudoVSUXSEG6EI64_V_M1_MF2_MASK, VSUXSEG6EI64_V }, // 10590 |
| 31861 | { PseudoVSUXSEG6EI64_V_M1_MF4, VSUXSEG6EI64_V }, // 10591 |
| 31862 | { PseudoVSUXSEG6EI64_V_M1_MF4_MASK, VSUXSEG6EI64_V }, // 10592 |
| 31863 | { PseudoVSUXSEG6EI64_V_M1_MF8, VSUXSEG6EI64_V }, // 10593 |
| 31864 | { PseudoVSUXSEG6EI64_V_M1_MF8_MASK, VSUXSEG6EI64_V }, // 10594 |
| 31865 | { PseudoVSUXSEG6EI64_V_M2_M1, VSUXSEG6EI64_V }, // 10595 |
| 31866 | { PseudoVSUXSEG6EI64_V_M2_M1_MASK, VSUXSEG6EI64_V }, // 10596 |
| 31867 | { PseudoVSUXSEG6EI64_V_M2_MF2, VSUXSEG6EI64_V }, // 10597 |
| 31868 | { PseudoVSUXSEG6EI64_V_M2_MF2_MASK, VSUXSEG6EI64_V }, // 10598 |
| 31869 | { PseudoVSUXSEG6EI64_V_M2_MF4, VSUXSEG6EI64_V }, // 10599 |
| 31870 | { PseudoVSUXSEG6EI64_V_M2_MF4_MASK, VSUXSEG6EI64_V }, // 10600 |
| 31871 | { PseudoVSUXSEG6EI64_V_M4_M1, VSUXSEG6EI64_V }, // 10601 |
| 31872 | { PseudoVSUXSEG6EI64_V_M4_M1_MASK, VSUXSEG6EI64_V }, // 10602 |
| 31873 | { PseudoVSUXSEG6EI64_V_M4_MF2, VSUXSEG6EI64_V }, // 10603 |
| 31874 | { PseudoVSUXSEG6EI64_V_M4_MF2_MASK, VSUXSEG6EI64_V }, // 10604 |
| 31875 | { PseudoVSUXSEG6EI64_V_M8_M1, VSUXSEG6EI64_V }, // 10605 |
| 31876 | { PseudoVSUXSEG6EI64_V_M8_M1_MASK, VSUXSEG6EI64_V }, // 10606 |
| 31877 | { PseudoVSUXSEG6EI8_V_M1_M1, VSUXSEG6EI8_V }, // 10607 |
| 31878 | { PseudoVSUXSEG6EI8_V_M1_M1_MASK, VSUXSEG6EI8_V }, // 10608 |
| 31879 | { PseudoVSUXSEG6EI8_V_MF2_M1, VSUXSEG6EI8_V }, // 10609 |
| 31880 | { PseudoVSUXSEG6EI8_V_MF2_M1_MASK, VSUXSEG6EI8_V }, // 10610 |
| 31881 | { PseudoVSUXSEG6EI8_V_MF2_MF2, VSUXSEG6EI8_V }, // 10611 |
| 31882 | { PseudoVSUXSEG6EI8_V_MF2_MF2_MASK, VSUXSEG6EI8_V }, // 10612 |
| 31883 | { PseudoVSUXSEG6EI8_V_MF4_M1, VSUXSEG6EI8_V }, // 10613 |
| 31884 | { PseudoVSUXSEG6EI8_V_MF4_M1_MASK, VSUXSEG6EI8_V }, // 10614 |
| 31885 | { PseudoVSUXSEG6EI8_V_MF4_MF2, VSUXSEG6EI8_V }, // 10615 |
| 31886 | { PseudoVSUXSEG6EI8_V_MF4_MF2_MASK, VSUXSEG6EI8_V }, // 10616 |
| 31887 | { PseudoVSUXSEG6EI8_V_MF4_MF4, VSUXSEG6EI8_V }, // 10617 |
| 31888 | { PseudoVSUXSEG6EI8_V_MF4_MF4_MASK, VSUXSEG6EI8_V }, // 10618 |
| 31889 | { PseudoVSUXSEG6EI8_V_MF8_M1, VSUXSEG6EI8_V }, // 10619 |
| 31890 | { PseudoVSUXSEG6EI8_V_MF8_M1_MASK, VSUXSEG6EI8_V }, // 10620 |
| 31891 | { PseudoVSUXSEG6EI8_V_MF8_MF2, VSUXSEG6EI8_V }, // 10621 |
| 31892 | { PseudoVSUXSEG6EI8_V_MF8_MF2_MASK, VSUXSEG6EI8_V }, // 10622 |
| 31893 | { PseudoVSUXSEG6EI8_V_MF8_MF4, VSUXSEG6EI8_V }, // 10623 |
| 31894 | { PseudoVSUXSEG6EI8_V_MF8_MF4_MASK, VSUXSEG6EI8_V }, // 10624 |
| 31895 | { PseudoVSUXSEG6EI8_V_MF8_MF8, VSUXSEG6EI8_V }, // 10625 |
| 31896 | { PseudoVSUXSEG6EI8_V_MF8_MF8_MASK, VSUXSEG6EI8_V }, // 10626 |
| 31897 | { PseudoVSUXSEG7EI16_V_M1_M1, VSUXSEG7EI16_V }, // 10627 |
| 31898 | { PseudoVSUXSEG7EI16_V_M1_M1_MASK, VSUXSEG7EI16_V }, // 10628 |
| 31899 | { PseudoVSUXSEG7EI16_V_M1_MF2, VSUXSEG7EI16_V }, // 10629 |
| 31900 | { PseudoVSUXSEG7EI16_V_M1_MF2_MASK, VSUXSEG7EI16_V }, // 10630 |
| 31901 | { PseudoVSUXSEG7EI16_V_M2_M1, VSUXSEG7EI16_V }, // 10631 |
| 31902 | { PseudoVSUXSEG7EI16_V_M2_M1_MASK, VSUXSEG7EI16_V }, // 10632 |
| 31903 | { PseudoVSUXSEG7EI16_V_MF2_M1, VSUXSEG7EI16_V }, // 10633 |
| 31904 | { PseudoVSUXSEG7EI16_V_MF2_M1_MASK, VSUXSEG7EI16_V }, // 10634 |
| 31905 | { PseudoVSUXSEG7EI16_V_MF2_MF2, VSUXSEG7EI16_V }, // 10635 |
| 31906 | { PseudoVSUXSEG7EI16_V_MF2_MF2_MASK, VSUXSEG7EI16_V }, // 10636 |
| 31907 | { PseudoVSUXSEG7EI16_V_MF2_MF4, VSUXSEG7EI16_V }, // 10637 |
| 31908 | { PseudoVSUXSEG7EI16_V_MF2_MF4_MASK, VSUXSEG7EI16_V }, // 10638 |
| 31909 | { PseudoVSUXSEG7EI16_V_MF4_M1, VSUXSEG7EI16_V }, // 10639 |
| 31910 | { PseudoVSUXSEG7EI16_V_MF4_M1_MASK, VSUXSEG7EI16_V }, // 10640 |
| 31911 | { PseudoVSUXSEG7EI16_V_MF4_MF2, VSUXSEG7EI16_V }, // 10641 |
| 31912 | { PseudoVSUXSEG7EI16_V_MF4_MF2_MASK, VSUXSEG7EI16_V }, // 10642 |
| 31913 | { PseudoVSUXSEG7EI16_V_MF4_MF4, VSUXSEG7EI16_V }, // 10643 |
| 31914 | { PseudoVSUXSEG7EI16_V_MF4_MF4_MASK, VSUXSEG7EI16_V }, // 10644 |
| 31915 | { PseudoVSUXSEG7EI16_V_MF4_MF8, VSUXSEG7EI16_V }, // 10645 |
| 31916 | { PseudoVSUXSEG7EI16_V_MF4_MF8_MASK, VSUXSEG7EI16_V }, // 10646 |
| 31917 | { PseudoVSUXSEG7EI32_V_M1_M1, VSUXSEG7EI32_V }, // 10647 |
| 31918 | { PseudoVSUXSEG7EI32_V_M1_M1_MASK, VSUXSEG7EI32_V }, // 10648 |
| 31919 | { PseudoVSUXSEG7EI32_V_M1_MF2, VSUXSEG7EI32_V }, // 10649 |
| 31920 | { PseudoVSUXSEG7EI32_V_M1_MF2_MASK, VSUXSEG7EI32_V }, // 10650 |
| 31921 | { PseudoVSUXSEG7EI32_V_M1_MF4, VSUXSEG7EI32_V }, // 10651 |
| 31922 | { PseudoVSUXSEG7EI32_V_M1_MF4_MASK, VSUXSEG7EI32_V }, // 10652 |
| 31923 | { PseudoVSUXSEG7EI32_V_M2_M1, VSUXSEG7EI32_V }, // 10653 |
| 31924 | { PseudoVSUXSEG7EI32_V_M2_M1_MASK, VSUXSEG7EI32_V }, // 10654 |
| 31925 | { PseudoVSUXSEG7EI32_V_M2_MF2, VSUXSEG7EI32_V }, // 10655 |
| 31926 | { PseudoVSUXSEG7EI32_V_M2_MF2_MASK, VSUXSEG7EI32_V }, // 10656 |
| 31927 | { PseudoVSUXSEG7EI32_V_M4_M1, VSUXSEG7EI32_V }, // 10657 |
| 31928 | { PseudoVSUXSEG7EI32_V_M4_M1_MASK, VSUXSEG7EI32_V }, // 10658 |
| 31929 | { PseudoVSUXSEG7EI32_V_MF2_M1, VSUXSEG7EI32_V }, // 10659 |
| 31930 | { PseudoVSUXSEG7EI32_V_MF2_M1_MASK, VSUXSEG7EI32_V }, // 10660 |
| 31931 | { PseudoVSUXSEG7EI32_V_MF2_MF2, VSUXSEG7EI32_V }, // 10661 |
| 31932 | { PseudoVSUXSEG7EI32_V_MF2_MF2_MASK, VSUXSEG7EI32_V }, // 10662 |
| 31933 | { PseudoVSUXSEG7EI32_V_MF2_MF4, VSUXSEG7EI32_V }, // 10663 |
| 31934 | { PseudoVSUXSEG7EI32_V_MF2_MF4_MASK, VSUXSEG7EI32_V }, // 10664 |
| 31935 | { PseudoVSUXSEG7EI32_V_MF2_MF8, VSUXSEG7EI32_V }, // 10665 |
| 31936 | { PseudoVSUXSEG7EI32_V_MF2_MF8_MASK, VSUXSEG7EI32_V }, // 10666 |
| 31937 | { PseudoVSUXSEG7EI64_V_M1_M1, VSUXSEG7EI64_V }, // 10667 |
| 31938 | { PseudoVSUXSEG7EI64_V_M1_M1_MASK, VSUXSEG7EI64_V }, // 10668 |
| 31939 | { PseudoVSUXSEG7EI64_V_M1_MF2, VSUXSEG7EI64_V }, // 10669 |
| 31940 | { PseudoVSUXSEG7EI64_V_M1_MF2_MASK, VSUXSEG7EI64_V }, // 10670 |
| 31941 | { PseudoVSUXSEG7EI64_V_M1_MF4, VSUXSEG7EI64_V }, // 10671 |
| 31942 | { PseudoVSUXSEG7EI64_V_M1_MF4_MASK, VSUXSEG7EI64_V }, // 10672 |
| 31943 | { PseudoVSUXSEG7EI64_V_M1_MF8, VSUXSEG7EI64_V }, // 10673 |
| 31944 | { PseudoVSUXSEG7EI64_V_M1_MF8_MASK, VSUXSEG7EI64_V }, // 10674 |
| 31945 | { PseudoVSUXSEG7EI64_V_M2_M1, VSUXSEG7EI64_V }, // 10675 |
| 31946 | { PseudoVSUXSEG7EI64_V_M2_M1_MASK, VSUXSEG7EI64_V }, // 10676 |
| 31947 | { PseudoVSUXSEG7EI64_V_M2_MF2, VSUXSEG7EI64_V }, // 10677 |
| 31948 | { PseudoVSUXSEG7EI64_V_M2_MF2_MASK, VSUXSEG7EI64_V }, // 10678 |
| 31949 | { PseudoVSUXSEG7EI64_V_M2_MF4, VSUXSEG7EI64_V }, // 10679 |
| 31950 | { PseudoVSUXSEG7EI64_V_M2_MF4_MASK, VSUXSEG7EI64_V }, // 10680 |
| 31951 | { PseudoVSUXSEG7EI64_V_M4_M1, VSUXSEG7EI64_V }, // 10681 |
| 31952 | { PseudoVSUXSEG7EI64_V_M4_M1_MASK, VSUXSEG7EI64_V }, // 10682 |
| 31953 | { PseudoVSUXSEG7EI64_V_M4_MF2, VSUXSEG7EI64_V }, // 10683 |
| 31954 | { PseudoVSUXSEG7EI64_V_M4_MF2_MASK, VSUXSEG7EI64_V }, // 10684 |
| 31955 | { PseudoVSUXSEG7EI64_V_M8_M1, VSUXSEG7EI64_V }, // 10685 |
| 31956 | { PseudoVSUXSEG7EI64_V_M8_M1_MASK, VSUXSEG7EI64_V }, // 10686 |
| 31957 | { PseudoVSUXSEG7EI8_V_M1_M1, VSUXSEG7EI8_V }, // 10687 |
| 31958 | { PseudoVSUXSEG7EI8_V_M1_M1_MASK, VSUXSEG7EI8_V }, // 10688 |
| 31959 | { PseudoVSUXSEG7EI8_V_MF2_M1, VSUXSEG7EI8_V }, // 10689 |
| 31960 | { PseudoVSUXSEG7EI8_V_MF2_M1_MASK, VSUXSEG7EI8_V }, // 10690 |
| 31961 | { PseudoVSUXSEG7EI8_V_MF2_MF2, VSUXSEG7EI8_V }, // 10691 |
| 31962 | { PseudoVSUXSEG7EI8_V_MF2_MF2_MASK, VSUXSEG7EI8_V }, // 10692 |
| 31963 | { PseudoVSUXSEG7EI8_V_MF4_M1, VSUXSEG7EI8_V }, // 10693 |
| 31964 | { PseudoVSUXSEG7EI8_V_MF4_M1_MASK, VSUXSEG7EI8_V }, // 10694 |
| 31965 | { PseudoVSUXSEG7EI8_V_MF4_MF2, VSUXSEG7EI8_V }, // 10695 |
| 31966 | { PseudoVSUXSEG7EI8_V_MF4_MF2_MASK, VSUXSEG7EI8_V }, // 10696 |
| 31967 | { PseudoVSUXSEG7EI8_V_MF4_MF4, VSUXSEG7EI8_V }, // 10697 |
| 31968 | { PseudoVSUXSEG7EI8_V_MF4_MF4_MASK, VSUXSEG7EI8_V }, // 10698 |
| 31969 | { PseudoVSUXSEG7EI8_V_MF8_M1, VSUXSEG7EI8_V }, // 10699 |
| 31970 | { PseudoVSUXSEG7EI8_V_MF8_M1_MASK, VSUXSEG7EI8_V }, // 10700 |
| 31971 | { PseudoVSUXSEG7EI8_V_MF8_MF2, VSUXSEG7EI8_V }, // 10701 |
| 31972 | { PseudoVSUXSEG7EI8_V_MF8_MF2_MASK, VSUXSEG7EI8_V }, // 10702 |
| 31973 | { PseudoVSUXSEG7EI8_V_MF8_MF4, VSUXSEG7EI8_V }, // 10703 |
| 31974 | { PseudoVSUXSEG7EI8_V_MF8_MF4_MASK, VSUXSEG7EI8_V }, // 10704 |
| 31975 | { PseudoVSUXSEG7EI8_V_MF8_MF8, VSUXSEG7EI8_V }, // 10705 |
| 31976 | { PseudoVSUXSEG7EI8_V_MF8_MF8_MASK, VSUXSEG7EI8_V }, // 10706 |
| 31977 | { PseudoVSUXSEG8EI16_V_M1_M1, VSUXSEG8EI16_V }, // 10707 |
| 31978 | { PseudoVSUXSEG8EI16_V_M1_M1_MASK, VSUXSEG8EI16_V }, // 10708 |
| 31979 | { PseudoVSUXSEG8EI16_V_M1_MF2, VSUXSEG8EI16_V }, // 10709 |
| 31980 | { PseudoVSUXSEG8EI16_V_M1_MF2_MASK, VSUXSEG8EI16_V }, // 10710 |
| 31981 | { PseudoVSUXSEG8EI16_V_M2_M1, VSUXSEG8EI16_V }, // 10711 |
| 31982 | { PseudoVSUXSEG8EI16_V_M2_M1_MASK, VSUXSEG8EI16_V }, // 10712 |
| 31983 | { PseudoVSUXSEG8EI16_V_MF2_M1, VSUXSEG8EI16_V }, // 10713 |
| 31984 | { PseudoVSUXSEG8EI16_V_MF2_M1_MASK, VSUXSEG8EI16_V }, // 10714 |
| 31985 | { PseudoVSUXSEG8EI16_V_MF2_MF2, VSUXSEG8EI16_V }, // 10715 |
| 31986 | { PseudoVSUXSEG8EI16_V_MF2_MF2_MASK, VSUXSEG8EI16_V }, // 10716 |
| 31987 | { PseudoVSUXSEG8EI16_V_MF2_MF4, VSUXSEG8EI16_V }, // 10717 |
| 31988 | { PseudoVSUXSEG8EI16_V_MF2_MF4_MASK, VSUXSEG8EI16_V }, // 10718 |
| 31989 | { PseudoVSUXSEG8EI16_V_MF4_M1, VSUXSEG8EI16_V }, // 10719 |
| 31990 | { PseudoVSUXSEG8EI16_V_MF4_M1_MASK, VSUXSEG8EI16_V }, // 10720 |
| 31991 | { PseudoVSUXSEG8EI16_V_MF4_MF2, VSUXSEG8EI16_V }, // 10721 |
| 31992 | { PseudoVSUXSEG8EI16_V_MF4_MF2_MASK, VSUXSEG8EI16_V }, // 10722 |
| 31993 | { PseudoVSUXSEG8EI16_V_MF4_MF4, VSUXSEG8EI16_V }, // 10723 |
| 31994 | { PseudoVSUXSEG8EI16_V_MF4_MF4_MASK, VSUXSEG8EI16_V }, // 10724 |
| 31995 | { PseudoVSUXSEG8EI16_V_MF4_MF8, VSUXSEG8EI16_V }, // 10725 |
| 31996 | { PseudoVSUXSEG8EI16_V_MF4_MF8_MASK, VSUXSEG8EI16_V }, // 10726 |
| 31997 | { PseudoVSUXSEG8EI32_V_M1_M1, VSUXSEG8EI32_V }, // 10727 |
| 31998 | { PseudoVSUXSEG8EI32_V_M1_M1_MASK, VSUXSEG8EI32_V }, // 10728 |
| 31999 | { PseudoVSUXSEG8EI32_V_M1_MF2, VSUXSEG8EI32_V }, // 10729 |
| 32000 | { PseudoVSUXSEG8EI32_V_M1_MF2_MASK, VSUXSEG8EI32_V }, // 10730 |
| 32001 | { PseudoVSUXSEG8EI32_V_M1_MF4, VSUXSEG8EI32_V }, // 10731 |
| 32002 | { PseudoVSUXSEG8EI32_V_M1_MF4_MASK, VSUXSEG8EI32_V }, // 10732 |
| 32003 | { PseudoVSUXSEG8EI32_V_M2_M1, VSUXSEG8EI32_V }, // 10733 |
| 32004 | { PseudoVSUXSEG8EI32_V_M2_M1_MASK, VSUXSEG8EI32_V }, // 10734 |
| 32005 | { PseudoVSUXSEG8EI32_V_M2_MF2, VSUXSEG8EI32_V }, // 10735 |
| 32006 | { PseudoVSUXSEG8EI32_V_M2_MF2_MASK, VSUXSEG8EI32_V }, // 10736 |
| 32007 | { PseudoVSUXSEG8EI32_V_M4_M1, VSUXSEG8EI32_V }, // 10737 |
| 32008 | { PseudoVSUXSEG8EI32_V_M4_M1_MASK, VSUXSEG8EI32_V }, // 10738 |
| 32009 | { PseudoVSUXSEG8EI32_V_MF2_M1, VSUXSEG8EI32_V }, // 10739 |
| 32010 | { PseudoVSUXSEG8EI32_V_MF2_M1_MASK, VSUXSEG8EI32_V }, // 10740 |
| 32011 | { PseudoVSUXSEG8EI32_V_MF2_MF2, VSUXSEG8EI32_V }, // 10741 |
| 32012 | { PseudoVSUXSEG8EI32_V_MF2_MF2_MASK, VSUXSEG8EI32_V }, // 10742 |
| 32013 | { PseudoVSUXSEG8EI32_V_MF2_MF4, VSUXSEG8EI32_V }, // 10743 |
| 32014 | { PseudoVSUXSEG8EI32_V_MF2_MF4_MASK, VSUXSEG8EI32_V }, // 10744 |
| 32015 | { PseudoVSUXSEG8EI32_V_MF2_MF8, VSUXSEG8EI32_V }, // 10745 |
| 32016 | { PseudoVSUXSEG8EI32_V_MF2_MF8_MASK, VSUXSEG8EI32_V }, // 10746 |
| 32017 | { PseudoVSUXSEG8EI64_V_M1_M1, VSUXSEG8EI64_V }, // 10747 |
| 32018 | { PseudoVSUXSEG8EI64_V_M1_M1_MASK, VSUXSEG8EI64_V }, // 10748 |
| 32019 | { PseudoVSUXSEG8EI64_V_M1_MF2, VSUXSEG8EI64_V }, // 10749 |
| 32020 | { PseudoVSUXSEG8EI64_V_M1_MF2_MASK, VSUXSEG8EI64_V }, // 10750 |
| 32021 | { PseudoVSUXSEG8EI64_V_M1_MF4, VSUXSEG8EI64_V }, // 10751 |
| 32022 | { PseudoVSUXSEG8EI64_V_M1_MF4_MASK, VSUXSEG8EI64_V }, // 10752 |
| 32023 | { PseudoVSUXSEG8EI64_V_M1_MF8, VSUXSEG8EI64_V }, // 10753 |
| 32024 | { PseudoVSUXSEG8EI64_V_M1_MF8_MASK, VSUXSEG8EI64_V }, // 10754 |
| 32025 | { PseudoVSUXSEG8EI64_V_M2_M1, VSUXSEG8EI64_V }, // 10755 |
| 32026 | { PseudoVSUXSEG8EI64_V_M2_M1_MASK, VSUXSEG8EI64_V }, // 10756 |
| 32027 | { PseudoVSUXSEG8EI64_V_M2_MF2, VSUXSEG8EI64_V }, // 10757 |
| 32028 | { PseudoVSUXSEG8EI64_V_M2_MF2_MASK, VSUXSEG8EI64_V }, // 10758 |
| 32029 | { PseudoVSUXSEG8EI64_V_M2_MF4, VSUXSEG8EI64_V }, // 10759 |
| 32030 | { PseudoVSUXSEG8EI64_V_M2_MF4_MASK, VSUXSEG8EI64_V }, // 10760 |
| 32031 | { PseudoVSUXSEG8EI64_V_M4_M1, VSUXSEG8EI64_V }, // 10761 |
| 32032 | { PseudoVSUXSEG8EI64_V_M4_M1_MASK, VSUXSEG8EI64_V }, // 10762 |
| 32033 | { PseudoVSUXSEG8EI64_V_M4_MF2, VSUXSEG8EI64_V }, // 10763 |
| 32034 | { PseudoVSUXSEG8EI64_V_M4_MF2_MASK, VSUXSEG8EI64_V }, // 10764 |
| 32035 | { PseudoVSUXSEG8EI64_V_M8_M1, VSUXSEG8EI64_V }, // 10765 |
| 32036 | { PseudoVSUXSEG8EI64_V_M8_M1_MASK, VSUXSEG8EI64_V }, // 10766 |
| 32037 | { PseudoVSUXSEG8EI8_V_M1_M1, VSUXSEG8EI8_V }, // 10767 |
| 32038 | { PseudoVSUXSEG8EI8_V_M1_M1_MASK, VSUXSEG8EI8_V }, // 10768 |
| 32039 | { PseudoVSUXSEG8EI8_V_MF2_M1, VSUXSEG8EI8_V }, // 10769 |
| 32040 | { PseudoVSUXSEG8EI8_V_MF2_M1_MASK, VSUXSEG8EI8_V }, // 10770 |
| 32041 | { PseudoVSUXSEG8EI8_V_MF2_MF2, VSUXSEG8EI8_V }, // 10771 |
| 32042 | { PseudoVSUXSEG8EI8_V_MF2_MF2_MASK, VSUXSEG8EI8_V }, // 10772 |
| 32043 | { PseudoVSUXSEG8EI8_V_MF4_M1, VSUXSEG8EI8_V }, // 10773 |
| 32044 | { PseudoVSUXSEG8EI8_V_MF4_M1_MASK, VSUXSEG8EI8_V }, // 10774 |
| 32045 | { PseudoVSUXSEG8EI8_V_MF4_MF2, VSUXSEG8EI8_V }, // 10775 |
| 32046 | { PseudoVSUXSEG8EI8_V_MF4_MF2_MASK, VSUXSEG8EI8_V }, // 10776 |
| 32047 | { PseudoVSUXSEG8EI8_V_MF4_MF4, VSUXSEG8EI8_V }, // 10777 |
| 32048 | { PseudoVSUXSEG8EI8_V_MF4_MF4_MASK, VSUXSEG8EI8_V }, // 10778 |
| 32049 | { PseudoVSUXSEG8EI8_V_MF8_M1, VSUXSEG8EI8_V }, // 10779 |
| 32050 | { PseudoVSUXSEG8EI8_V_MF8_M1_MASK, VSUXSEG8EI8_V }, // 10780 |
| 32051 | { PseudoVSUXSEG8EI8_V_MF8_MF2, VSUXSEG8EI8_V }, // 10781 |
| 32052 | { PseudoVSUXSEG8EI8_V_MF8_MF2_MASK, VSUXSEG8EI8_V }, // 10782 |
| 32053 | { PseudoVSUXSEG8EI8_V_MF8_MF4, VSUXSEG8EI8_V }, // 10783 |
| 32054 | { PseudoVSUXSEG8EI8_V_MF8_MF4_MASK, VSUXSEG8EI8_V }, // 10784 |
| 32055 | { PseudoVSUXSEG8EI8_V_MF8_MF8, VSUXSEG8EI8_V }, // 10785 |
| 32056 | { PseudoVSUXSEG8EI8_V_MF8_MF8_MASK, VSUXSEG8EI8_V }, // 10786 |
| 32057 | { PseudoVWADDU_VV_M1, VWADDU_VV }, // 10787 |
| 32058 | { PseudoVWADDU_VV_M1_MASK, VWADDU_VV }, // 10788 |
| 32059 | { PseudoVWADDU_VV_M2, VWADDU_VV }, // 10789 |
| 32060 | { PseudoVWADDU_VV_M2_MASK, VWADDU_VV }, // 10790 |
| 32061 | { PseudoVWADDU_VV_M4, VWADDU_VV }, // 10791 |
| 32062 | { PseudoVWADDU_VV_M4_MASK, VWADDU_VV }, // 10792 |
| 32063 | { PseudoVWADDU_VV_MF2, VWADDU_VV }, // 10793 |
| 32064 | { PseudoVWADDU_VV_MF2_MASK, VWADDU_VV }, // 10794 |
| 32065 | { PseudoVWADDU_VV_MF4, VWADDU_VV }, // 10795 |
| 32066 | { PseudoVWADDU_VV_MF4_MASK, VWADDU_VV }, // 10796 |
| 32067 | { PseudoVWADDU_VV_MF8, VWADDU_VV }, // 10797 |
| 32068 | { PseudoVWADDU_VV_MF8_MASK, VWADDU_VV }, // 10798 |
| 32069 | { PseudoVWADDU_VX_M1, VWADDU_VX }, // 10799 |
| 32070 | { PseudoVWADDU_VX_M1_MASK, VWADDU_VX }, // 10800 |
| 32071 | { PseudoVWADDU_VX_M2, VWADDU_VX }, // 10801 |
| 32072 | { PseudoVWADDU_VX_M2_MASK, VWADDU_VX }, // 10802 |
| 32073 | { PseudoVWADDU_VX_M4, VWADDU_VX }, // 10803 |
| 32074 | { PseudoVWADDU_VX_M4_MASK, VWADDU_VX }, // 10804 |
| 32075 | { PseudoVWADDU_VX_MF2, VWADDU_VX }, // 10805 |
| 32076 | { PseudoVWADDU_VX_MF2_MASK, VWADDU_VX }, // 10806 |
| 32077 | { PseudoVWADDU_VX_MF4, VWADDU_VX }, // 10807 |
| 32078 | { PseudoVWADDU_VX_MF4_MASK, VWADDU_VX }, // 10808 |
| 32079 | { PseudoVWADDU_VX_MF8, VWADDU_VX }, // 10809 |
| 32080 | { PseudoVWADDU_VX_MF8_MASK, VWADDU_VX }, // 10810 |
| 32081 | { PseudoVWADDU_WV_M1, VWADDU_WV }, // 10811 |
| 32082 | { PseudoVWADDU_WV_M1_MASK, VWADDU_WV }, // 10812 |
| 32083 | { PseudoVWADDU_WV_M1_MASK_TIED, VWADDU_WV }, // 10813 |
| 32084 | { PseudoVWADDU_WV_M1_TIED, VWADDU_WV }, // 10814 |
| 32085 | { PseudoVWADDU_WV_M2, VWADDU_WV }, // 10815 |
| 32086 | { PseudoVWADDU_WV_M2_MASK, VWADDU_WV }, // 10816 |
| 32087 | { PseudoVWADDU_WV_M2_MASK_TIED, VWADDU_WV }, // 10817 |
| 32088 | { PseudoVWADDU_WV_M2_TIED, VWADDU_WV }, // 10818 |
| 32089 | { PseudoVWADDU_WV_M4, VWADDU_WV }, // 10819 |
| 32090 | { PseudoVWADDU_WV_M4_MASK, VWADDU_WV }, // 10820 |
| 32091 | { PseudoVWADDU_WV_M4_MASK_TIED, VWADDU_WV }, // 10821 |
| 32092 | { PseudoVWADDU_WV_M4_TIED, VWADDU_WV }, // 10822 |
| 32093 | { PseudoVWADDU_WV_MF2, VWADDU_WV }, // 10823 |
| 32094 | { PseudoVWADDU_WV_MF2_MASK, VWADDU_WV }, // 10824 |
| 32095 | { PseudoVWADDU_WV_MF2_MASK_TIED, VWADDU_WV }, // 10825 |
| 32096 | { PseudoVWADDU_WV_MF2_TIED, VWADDU_WV }, // 10826 |
| 32097 | { PseudoVWADDU_WV_MF4, VWADDU_WV }, // 10827 |
| 32098 | { PseudoVWADDU_WV_MF4_MASK, VWADDU_WV }, // 10828 |
| 32099 | { PseudoVWADDU_WV_MF4_MASK_TIED, VWADDU_WV }, // 10829 |
| 32100 | { PseudoVWADDU_WV_MF4_TIED, VWADDU_WV }, // 10830 |
| 32101 | { PseudoVWADDU_WV_MF8, VWADDU_WV }, // 10831 |
| 32102 | { PseudoVWADDU_WV_MF8_MASK, VWADDU_WV }, // 10832 |
| 32103 | { PseudoVWADDU_WV_MF8_MASK_TIED, VWADDU_WV }, // 10833 |
| 32104 | { PseudoVWADDU_WV_MF8_TIED, VWADDU_WV }, // 10834 |
| 32105 | { PseudoVWADDU_WX_M1, VWADDU_WX }, // 10835 |
| 32106 | { PseudoVWADDU_WX_M1_MASK, VWADDU_WX }, // 10836 |
| 32107 | { PseudoVWADDU_WX_M2, VWADDU_WX }, // 10837 |
| 32108 | { PseudoVWADDU_WX_M2_MASK, VWADDU_WX }, // 10838 |
| 32109 | { PseudoVWADDU_WX_M4, VWADDU_WX }, // 10839 |
| 32110 | { PseudoVWADDU_WX_M4_MASK, VWADDU_WX }, // 10840 |
| 32111 | { PseudoVWADDU_WX_MF2, VWADDU_WX }, // 10841 |
| 32112 | { PseudoVWADDU_WX_MF2_MASK, VWADDU_WX }, // 10842 |
| 32113 | { PseudoVWADDU_WX_MF4, VWADDU_WX }, // 10843 |
| 32114 | { PseudoVWADDU_WX_MF4_MASK, VWADDU_WX }, // 10844 |
| 32115 | { PseudoVWADDU_WX_MF8, VWADDU_WX }, // 10845 |
| 32116 | { PseudoVWADDU_WX_MF8_MASK, VWADDU_WX }, // 10846 |
| 32117 | { PseudoVWADD_VV_M1, VWADD_VV }, // 10847 |
| 32118 | { PseudoVWADD_VV_M1_MASK, VWADD_VV }, // 10848 |
| 32119 | { PseudoVWADD_VV_M2, VWADD_VV }, // 10849 |
| 32120 | { PseudoVWADD_VV_M2_MASK, VWADD_VV }, // 10850 |
| 32121 | { PseudoVWADD_VV_M4, VWADD_VV }, // 10851 |
| 32122 | { PseudoVWADD_VV_M4_MASK, VWADD_VV }, // 10852 |
| 32123 | { PseudoVWADD_VV_MF2, VWADD_VV }, // 10853 |
| 32124 | { PseudoVWADD_VV_MF2_MASK, VWADD_VV }, // 10854 |
| 32125 | { PseudoVWADD_VV_MF4, VWADD_VV }, // 10855 |
| 32126 | { PseudoVWADD_VV_MF4_MASK, VWADD_VV }, // 10856 |
| 32127 | { PseudoVWADD_VV_MF8, VWADD_VV }, // 10857 |
| 32128 | { PseudoVWADD_VV_MF8_MASK, VWADD_VV }, // 10858 |
| 32129 | { PseudoVWADD_VX_M1, VWADD_VX }, // 10859 |
| 32130 | { PseudoVWADD_VX_M1_MASK, VWADD_VX }, // 10860 |
| 32131 | { PseudoVWADD_VX_M2, VWADD_VX }, // 10861 |
| 32132 | { PseudoVWADD_VX_M2_MASK, VWADD_VX }, // 10862 |
| 32133 | { PseudoVWADD_VX_M4, VWADD_VX }, // 10863 |
| 32134 | { PseudoVWADD_VX_M4_MASK, VWADD_VX }, // 10864 |
| 32135 | { PseudoVWADD_VX_MF2, VWADD_VX }, // 10865 |
| 32136 | { PseudoVWADD_VX_MF2_MASK, VWADD_VX }, // 10866 |
| 32137 | { PseudoVWADD_VX_MF4, VWADD_VX }, // 10867 |
| 32138 | { PseudoVWADD_VX_MF4_MASK, VWADD_VX }, // 10868 |
| 32139 | { PseudoVWADD_VX_MF8, VWADD_VX }, // 10869 |
| 32140 | { PseudoVWADD_VX_MF8_MASK, VWADD_VX }, // 10870 |
| 32141 | { PseudoVWADD_WV_M1, VWADD_WV }, // 10871 |
| 32142 | { PseudoVWADD_WV_M1_MASK, VWADD_WV }, // 10872 |
| 32143 | { PseudoVWADD_WV_M1_MASK_TIED, VWADD_WV }, // 10873 |
| 32144 | { PseudoVWADD_WV_M1_TIED, VWADD_WV }, // 10874 |
| 32145 | { PseudoVWADD_WV_M2, VWADD_WV }, // 10875 |
| 32146 | { PseudoVWADD_WV_M2_MASK, VWADD_WV }, // 10876 |
| 32147 | { PseudoVWADD_WV_M2_MASK_TIED, VWADD_WV }, // 10877 |
| 32148 | { PseudoVWADD_WV_M2_TIED, VWADD_WV }, // 10878 |
| 32149 | { PseudoVWADD_WV_M4, VWADD_WV }, // 10879 |
| 32150 | { PseudoVWADD_WV_M4_MASK, VWADD_WV }, // 10880 |
| 32151 | { PseudoVWADD_WV_M4_MASK_TIED, VWADD_WV }, // 10881 |
| 32152 | { PseudoVWADD_WV_M4_TIED, VWADD_WV }, // 10882 |
| 32153 | { PseudoVWADD_WV_MF2, VWADD_WV }, // 10883 |
| 32154 | { PseudoVWADD_WV_MF2_MASK, VWADD_WV }, // 10884 |
| 32155 | { PseudoVWADD_WV_MF2_MASK_TIED, VWADD_WV }, // 10885 |
| 32156 | { PseudoVWADD_WV_MF2_TIED, VWADD_WV }, // 10886 |
| 32157 | { PseudoVWADD_WV_MF4, VWADD_WV }, // 10887 |
| 32158 | { PseudoVWADD_WV_MF4_MASK, VWADD_WV }, // 10888 |
| 32159 | { PseudoVWADD_WV_MF4_MASK_TIED, VWADD_WV }, // 10889 |
| 32160 | { PseudoVWADD_WV_MF4_TIED, VWADD_WV }, // 10890 |
| 32161 | { PseudoVWADD_WV_MF8, VWADD_WV }, // 10891 |
| 32162 | { PseudoVWADD_WV_MF8_MASK, VWADD_WV }, // 10892 |
| 32163 | { PseudoVWADD_WV_MF8_MASK_TIED, VWADD_WV }, // 10893 |
| 32164 | { PseudoVWADD_WV_MF8_TIED, VWADD_WV }, // 10894 |
| 32165 | { PseudoVWADD_WX_M1, VWADD_WX }, // 10895 |
| 32166 | { PseudoVWADD_WX_M1_MASK, VWADD_WX }, // 10896 |
| 32167 | { PseudoVWADD_WX_M2, VWADD_WX }, // 10897 |
| 32168 | { PseudoVWADD_WX_M2_MASK, VWADD_WX }, // 10898 |
| 32169 | { PseudoVWADD_WX_M4, VWADD_WX }, // 10899 |
| 32170 | { PseudoVWADD_WX_M4_MASK, VWADD_WX }, // 10900 |
| 32171 | { PseudoVWADD_WX_MF2, VWADD_WX }, // 10901 |
| 32172 | { PseudoVWADD_WX_MF2_MASK, VWADD_WX }, // 10902 |
| 32173 | { PseudoVWADD_WX_MF4, VWADD_WX }, // 10903 |
| 32174 | { PseudoVWADD_WX_MF4_MASK, VWADD_WX }, // 10904 |
| 32175 | { PseudoVWADD_WX_MF8, VWADD_WX }, // 10905 |
| 32176 | { PseudoVWADD_WX_MF8_MASK, VWADD_WX }, // 10906 |
| 32177 | { PseudoVWMACCSU_VV_M1, VWMACCSU_VV }, // 10907 |
| 32178 | { PseudoVWMACCSU_VV_M1_MASK, VWMACCSU_VV }, // 10908 |
| 32179 | { PseudoVWMACCSU_VV_M2, VWMACCSU_VV }, // 10909 |
| 32180 | { PseudoVWMACCSU_VV_M2_MASK, VWMACCSU_VV }, // 10910 |
| 32181 | { PseudoVWMACCSU_VV_M4, VWMACCSU_VV }, // 10911 |
| 32182 | { PseudoVWMACCSU_VV_M4_MASK, VWMACCSU_VV }, // 10912 |
| 32183 | { PseudoVWMACCSU_VV_MF2, VWMACCSU_VV }, // 10913 |
| 32184 | { PseudoVWMACCSU_VV_MF2_MASK, VWMACCSU_VV }, // 10914 |
| 32185 | { PseudoVWMACCSU_VV_MF4, VWMACCSU_VV }, // 10915 |
| 32186 | { PseudoVWMACCSU_VV_MF4_MASK, VWMACCSU_VV }, // 10916 |
| 32187 | { PseudoVWMACCSU_VV_MF8, VWMACCSU_VV }, // 10917 |
| 32188 | { PseudoVWMACCSU_VV_MF8_MASK, VWMACCSU_VV }, // 10918 |
| 32189 | { PseudoVWMACCSU_VX_M1, VWMACCSU_VX }, // 10919 |
| 32190 | { PseudoVWMACCSU_VX_M1_MASK, VWMACCSU_VX }, // 10920 |
| 32191 | { PseudoVWMACCSU_VX_M2, VWMACCSU_VX }, // 10921 |
| 32192 | { PseudoVWMACCSU_VX_M2_MASK, VWMACCSU_VX }, // 10922 |
| 32193 | { PseudoVWMACCSU_VX_M4, VWMACCSU_VX }, // 10923 |
| 32194 | { PseudoVWMACCSU_VX_M4_MASK, VWMACCSU_VX }, // 10924 |
| 32195 | { PseudoVWMACCSU_VX_MF2, VWMACCSU_VX }, // 10925 |
| 32196 | { PseudoVWMACCSU_VX_MF2_MASK, VWMACCSU_VX }, // 10926 |
| 32197 | { PseudoVWMACCSU_VX_MF4, VWMACCSU_VX }, // 10927 |
| 32198 | { PseudoVWMACCSU_VX_MF4_MASK, VWMACCSU_VX }, // 10928 |
| 32199 | { PseudoVWMACCSU_VX_MF8, VWMACCSU_VX }, // 10929 |
| 32200 | { PseudoVWMACCSU_VX_MF8_MASK, VWMACCSU_VX }, // 10930 |
| 32201 | { PseudoVWMACCUS_VX_M1, VWMACCUS_VX }, // 10931 |
| 32202 | { PseudoVWMACCUS_VX_M1_MASK, VWMACCUS_VX }, // 10932 |
| 32203 | { PseudoVWMACCUS_VX_M2, VWMACCUS_VX }, // 10933 |
| 32204 | { PseudoVWMACCUS_VX_M2_MASK, VWMACCUS_VX }, // 10934 |
| 32205 | { PseudoVWMACCUS_VX_M4, VWMACCUS_VX }, // 10935 |
| 32206 | { PseudoVWMACCUS_VX_M4_MASK, VWMACCUS_VX }, // 10936 |
| 32207 | { PseudoVWMACCUS_VX_MF2, VWMACCUS_VX }, // 10937 |
| 32208 | { PseudoVWMACCUS_VX_MF2_MASK, VWMACCUS_VX }, // 10938 |
| 32209 | { PseudoVWMACCUS_VX_MF4, VWMACCUS_VX }, // 10939 |
| 32210 | { PseudoVWMACCUS_VX_MF4_MASK, VWMACCUS_VX }, // 10940 |
| 32211 | { PseudoVWMACCUS_VX_MF8, VWMACCUS_VX }, // 10941 |
| 32212 | { PseudoVWMACCUS_VX_MF8_MASK, VWMACCUS_VX }, // 10942 |
| 32213 | { PseudoVWMACCU_VV_M1, VWMACCU_VV }, // 10943 |
| 32214 | { PseudoVWMACCU_VV_M1_MASK, VWMACCU_VV }, // 10944 |
| 32215 | { PseudoVWMACCU_VV_M2, VWMACCU_VV }, // 10945 |
| 32216 | { PseudoVWMACCU_VV_M2_MASK, VWMACCU_VV }, // 10946 |
| 32217 | { PseudoVWMACCU_VV_M4, VWMACCU_VV }, // 10947 |
| 32218 | { PseudoVWMACCU_VV_M4_MASK, VWMACCU_VV }, // 10948 |
| 32219 | { PseudoVWMACCU_VV_MF2, VWMACCU_VV }, // 10949 |
| 32220 | { PseudoVWMACCU_VV_MF2_MASK, VWMACCU_VV }, // 10950 |
| 32221 | { PseudoVWMACCU_VV_MF4, VWMACCU_VV }, // 10951 |
| 32222 | { PseudoVWMACCU_VV_MF4_MASK, VWMACCU_VV }, // 10952 |
| 32223 | { PseudoVWMACCU_VV_MF8, VWMACCU_VV }, // 10953 |
| 32224 | { PseudoVWMACCU_VV_MF8_MASK, VWMACCU_VV }, // 10954 |
| 32225 | { PseudoVWMACCU_VX_M1, VWMACCU_VX }, // 10955 |
| 32226 | { PseudoVWMACCU_VX_M1_MASK, VWMACCU_VX }, // 10956 |
| 32227 | { PseudoVWMACCU_VX_M2, VWMACCU_VX }, // 10957 |
| 32228 | { PseudoVWMACCU_VX_M2_MASK, VWMACCU_VX }, // 10958 |
| 32229 | { PseudoVWMACCU_VX_M4, VWMACCU_VX }, // 10959 |
| 32230 | { PseudoVWMACCU_VX_M4_MASK, VWMACCU_VX }, // 10960 |
| 32231 | { PseudoVWMACCU_VX_MF2, VWMACCU_VX }, // 10961 |
| 32232 | { PseudoVWMACCU_VX_MF2_MASK, VWMACCU_VX }, // 10962 |
| 32233 | { PseudoVWMACCU_VX_MF4, VWMACCU_VX }, // 10963 |
| 32234 | { PseudoVWMACCU_VX_MF4_MASK, VWMACCU_VX }, // 10964 |
| 32235 | { PseudoVWMACCU_VX_MF8, VWMACCU_VX }, // 10965 |
| 32236 | { PseudoVWMACCU_VX_MF8_MASK, VWMACCU_VX }, // 10966 |
| 32237 | { PseudoVWMACC_VV_M1, VWMACC_VV }, // 10967 |
| 32238 | { PseudoVWMACC_VV_M1_MASK, VWMACC_VV }, // 10968 |
| 32239 | { PseudoVWMACC_VV_M2, VWMACC_VV }, // 10969 |
| 32240 | { PseudoVWMACC_VV_M2_MASK, VWMACC_VV }, // 10970 |
| 32241 | { PseudoVWMACC_VV_M4, VWMACC_VV }, // 10971 |
| 32242 | { PseudoVWMACC_VV_M4_MASK, VWMACC_VV }, // 10972 |
| 32243 | { PseudoVWMACC_VV_MF2, VWMACC_VV }, // 10973 |
| 32244 | { PseudoVWMACC_VV_MF2_MASK, VWMACC_VV }, // 10974 |
| 32245 | { PseudoVWMACC_VV_MF4, VWMACC_VV }, // 10975 |
| 32246 | { PseudoVWMACC_VV_MF4_MASK, VWMACC_VV }, // 10976 |
| 32247 | { PseudoVWMACC_VV_MF8, VWMACC_VV }, // 10977 |
| 32248 | { PseudoVWMACC_VV_MF8_MASK, VWMACC_VV }, // 10978 |
| 32249 | { PseudoVWMACC_VX_M1, VWMACC_VX }, // 10979 |
| 32250 | { PseudoVWMACC_VX_M1_MASK, VWMACC_VX }, // 10980 |
| 32251 | { PseudoVWMACC_VX_M2, VWMACC_VX }, // 10981 |
| 32252 | { PseudoVWMACC_VX_M2_MASK, VWMACC_VX }, // 10982 |
| 32253 | { PseudoVWMACC_VX_M4, VWMACC_VX }, // 10983 |
| 32254 | { PseudoVWMACC_VX_M4_MASK, VWMACC_VX }, // 10984 |
| 32255 | { PseudoVWMACC_VX_MF2, VWMACC_VX }, // 10985 |
| 32256 | { PseudoVWMACC_VX_MF2_MASK, VWMACC_VX }, // 10986 |
| 32257 | { PseudoVWMACC_VX_MF4, VWMACC_VX }, // 10987 |
| 32258 | { PseudoVWMACC_VX_MF4_MASK, VWMACC_VX }, // 10988 |
| 32259 | { PseudoVWMACC_VX_MF8, VWMACC_VX }, // 10989 |
| 32260 | { PseudoVWMACC_VX_MF8_MASK, VWMACC_VX }, // 10990 |
| 32261 | { PseudoVWMULSU_VV_M1, VWMULSU_VV }, // 10991 |
| 32262 | { PseudoVWMULSU_VV_M1_MASK, VWMULSU_VV }, // 10992 |
| 32263 | { PseudoVWMULSU_VV_M2, VWMULSU_VV }, // 10993 |
| 32264 | { PseudoVWMULSU_VV_M2_MASK, VWMULSU_VV }, // 10994 |
| 32265 | { PseudoVWMULSU_VV_M4, VWMULSU_VV }, // 10995 |
| 32266 | { PseudoVWMULSU_VV_M4_MASK, VWMULSU_VV }, // 10996 |
| 32267 | { PseudoVWMULSU_VV_MF2, VWMULSU_VV }, // 10997 |
| 32268 | { PseudoVWMULSU_VV_MF2_MASK, VWMULSU_VV }, // 10998 |
| 32269 | { PseudoVWMULSU_VV_MF4, VWMULSU_VV }, // 10999 |
| 32270 | { PseudoVWMULSU_VV_MF4_MASK, VWMULSU_VV }, // 11000 |
| 32271 | { PseudoVWMULSU_VV_MF8, VWMULSU_VV }, // 11001 |
| 32272 | { PseudoVWMULSU_VV_MF8_MASK, VWMULSU_VV }, // 11002 |
| 32273 | { PseudoVWMULSU_VX_M1, VWMULSU_VX }, // 11003 |
| 32274 | { PseudoVWMULSU_VX_M1_MASK, VWMULSU_VX }, // 11004 |
| 32275 | { PseudoVWMULSU_VX_M2, VWMULSU_VX }, // 11005 |
| 32276 | { PseudoVWMULSU_VX_M2_MASK, VWMULSU_VX }, // 11006 |
| 32277 | { PseudoVWMULSU_VX_M4, VWMULSU_VX }, // 11007 |
| 32278 | { PseudoVWMULSU_VX_M4_MASK, VWMULSU_VX }, // 11008 |
| 32279 | { PseudoVWMULSU_VX_MF2, VWMULSU_VX }, // 11009 |
| 32280 | { PseudoVWMULSU_VX_MF2_MASK, VWMULSU_VX }, // 11010 |
| 32281 | { PseudoVWMULSU_VX_MF4, VWMULSU_VX }, // 11011 |
| 32282 | { PseudoVWMULSU_VX_MF4_MASK, VWMULSU_VX }, // 11012 |
| 32283 | { PseudoVWMULSU_VX_MF8, VWMULSU_VX }, // 11013 |
| 32284 | { PseudoVWMULSU_VX_MF8_MASK, VWMULSU_VX }, // 11014 |
| 32285 | { PseudoVWMULU_VV_M1, VWMULU_VV }, // 11015 |
| 32286 | { PseudoVWMULU_VV_M1_MASK, VWMULU_VV }, // 11016 |
| 32287 | { PseudoVWMULU_VV_M2, VWMULU_VV }, // 11017 |
| 32288 | { PseudoVWMULU_VV_M2_MASK, VWMULU_VV }, // 11018 |
| 32289 | { PseudoVWMULU_VV_M4, VWMULU_VV }, // 11019 |
| 32290 | { PseudoVWMULU_VV_M4_MASK, VWMULU_VV }, // 11020 |
| 32291 | { PseudoVWMULU_VV_MF2, VWMULU_VV }, // 11021 |
| 32292 | { PseudoVWMULU_VV_MF2_MASK, VWMULU_VV }, // 11022 |
| 32293 | { PseudoVWMULU_VV_MF4, VWMULU_VV }, // 11023 |
| 32294 | { PseudoVWMULU_VV_MF4_MASK, VWMULU_VV }, // 11024 |
| 32295 | { PseudoVWMULU_VV_MF8, VWMULU_VV }, // 11025 |
| 32296 | { PseudoVWMULU_VV_MF8_MASK, VWMULU_VV }, // 11026 |
| 32297 | { PseudoVWMULU_VX_M1, VWMULU_VX }, // 11027 |
| 32298 | { PseudoVWMULU_VX_M1_MASK, VWMULU_VX }, // 11028 |
| 32299 | { PseudoVWMULU_VX_M2, VWMULU_VX }, // 11029 |
| 32300 | { PseudoVWMULU_VX_M2_MASK, VWMULU_VX }, // 11030 |
| 32301 | { PseudoVWMULU_VX_M4, VWMULU_VX }, // 11031 |
| 32302 | { PseudoVWMULU_VX_M4_MASK, VWMULU_VX }, // 11032 |
| 32303 | { PseudoVWMULU_VX_MF2, VWMULU_VX }, // 11033 |
| 32304 | { PseudoVWMULU_VX_MF2_MASK, VWMULU_VX }, // 11034 |
| 32305 | { PseudoVWMULU_VX_MF4, VWMULU_VX }, // 11035 |
| 32306 | { PseudoVWMULU_VX_MF4_MASK, VWMULU_VX }, // 11036 |
| 32307 | { PseudoVWMULU_VX_MF8, VWMULU_VX }, // 11037 |
| 32308 | { PseudoVWMULU_VX_MF8_MASK, VWMULU_VX }, // 11038 |
| 32309 | { PseudoVWMUL_VV_M1, VWMUL_VV }, // 11039 |
| 32310 | { PseudoVWMUL_VV_M1_MASK, VWMUL_VV }, // 11040 |
| 32311 | { PseudoVWMUL_VV_M2, VWMUL_VV }, // 11041 |
| 32312 | { PseudoVWMUL_VV_M2_MASK, VWMUL_VV }, // 11042 |
| 32313 | { PseudoVWMUL_VV_M4, VWMUL_VV }, // 11043 |
| 32314 | { PseudoVWMUL_VV_M4_MASK, VWMUL_VV }, // 11044 |
| 32315 | { PseudoVWMUL_VV_MF2, VWMUL_VV }, // 11045 |
| 32316 | { PseudoVWMUL_VV_MF2_MASK, VWMUL_VV }, // 11046 |
| 32317 | { PseudoVWMUL_VV_MF4, VWMUL_VV }, // 11047 |
| 32318 | { PseudoVWMUL_VV_MF4_MASK, VWMUL_VV }, // 11048 |
| 32319 | { PseudoVWMUL_VV_MF8, VWMUL_VV }, // 11049 |
| 32320 | { PseudoVWMUL_VV_MF8_MASK, VWMUL_VV }, // 11050 |
| 32321 | { PseudoVWMUL_VX_M1, VWMUL_VX }, // 11051 |
| 32322 | { PseudoVWMUL_VX_M1_MASK, VWMUL_VX }, // 11052 |
| 32323 | { PseudoVWMUL_VX_M2, VWMUL_VX }, // 11053 |
| 32324 | { PseudoVWMUL_VX_M2_MASK, VWMUL_VX }, // 11054 |
| 32325 | { PseudoVWMUL_VX_M4, VWMUL_VX }, // 11055 |
| 32326 | { PseudoVWMUL_VX_M4_MASK, VWMUL_VX }, // 11056 |
| 32327 | { PseudoVWMUL_VX_MF2, VWMUL_VX }, // 11057 |
| 32328 | { PseudoVWMUL_VX_MF2_MASK, VWMUL_VX }, // 11058 |
| 32329 | { PseudoVWMUL_VX_MF4, VWMUL_VX }, // 11059 |
| 32330 | { PseudoVWMUL_VX_MF4_MASK, VWMUL_VX }, // 11060 |
| 32331 | { PseudoVWMUL_VX_MF8, VWMUL_VX }, // 11061 |
| 32332 | { PseudoVWMUL_VX_MF8_MASK, VWMUL_VX }, // 11062 |
| 32333 | { PseudoVWREDSUMU_VS_M1_E16, VWREDSUMU_VS }, // 11063 |
| 32334 | { PseudoVWREDSUMU_VS_M1_E16_MASK, VWREDSUMU_VS }, // 11064 |
| 32335 | { PseudoVWREDSUMU_VS_M1_E32, VWREDSUMU_VS }, // 11065 |
| 32336 | { PseudoVWREDSUMU_VS_M1_E32_MASK, VWREDSUMU_VS }, // 11066 |
| 32337 | { PseudoVWREDSUMU_VS_M1_E8, VWREDSUMU_VS }, // 11067 |
| 32338 | { PseudoVWREDSUMU_VS_M1_E8_MASK, VWREDSUMU_VS }, // 11068 |
| 32339 | { PseudoVWREDSUMU_VS_M2_E16, VWREDSUMU_VS }, // 11069 |
| 32340 | { PseudoVWREDSUMU_VS_M2_E16_MASK, VWREDSUMU_VS }, // 11070 |
| 32341 | { PseudoVWREDSUMU_VS_M2_E32, VWREDSUMU_VS }, // 11071 |
| 32342 | { PseudoVWREDSUMU_VS_M2_E32_MASK, VWREDSUMU_VS }, // 11072 |
| 32343 | { PseudoVWREDSUMU_VS_M2_E8, VWREDSUMU_VS }, // 11073 |
| 32344 | { PseudoVWREDSUMU_VS_M2_E8_MASK, VWREDSUMU_VS }, // 11074 |
| 32345 | { PseudoVWREDSUMU_VS_M4_E16, VWREDSUMU_VS }, // 11075 |
| 32346 | { PseudoVWREDSUMU_VS_M4_E16_MASK, VWREDSUMU_VS }, // 11076 |
| 32347 | { PseudoVWREDSUMU_VS_M4_E32, VWREDSUMU_VS }, // 11077 |
| 32348 | { PseudoVWREDSUMU_VS_M4_E32_MASK, VWREDSUMU_VS }, // 11078 |
| 32349 | { PseudoVWREDSUMU_VS_M4_E8, VWREDSUMU_VS }, // 11079 |
| 32350 | { PseudoVWREDSUMU_VS_M4_E8_MASK, VWREDSUMU_VS }, // 11080 |
| 32351 | { PseudoVWREDSUMU_VS_M8_E16, VWREDSUMU_VS }, // 11081 |
| 32352 | { PseudoVWREDSUMU_VS_M8_E16_MASK, VWREDSUMU_VS }, // 11082 |
| 32353 | { PseudoVWREDSUMU_VS_M8_E32, VWREDSUMU_VS }, // 11083 |
| 32354 | { PseudoVWREDSUMU_VS_M8_E32_MASK, VWREDSUMU_VS }, // 11084 |
| 32355 | { PseudoVWREDSUMU_VS_M8_E8, VWREDSUMU_VS }, // 11085 |
| 32356 | { PseudoVWREDSUMU_VS_M8_E8_MASK, VWREDSUMU_VS }, // 11086 |
| 32357 | { PseudoVWREDSUMU_VS_MF2_E16, VWREDSUMU_VS }, // 11087 |
| 32358 | { PseudoVWREDSUMU_VS_MF2_E16_MASK, VWREDSUMU_VS }, // 11088 |
| 32359 | { PseudoVWREDSUMU_VS_MF2_E32, VWREDSUMU_VS }, // 11089 |
| 32360 | { PseudoVWREDSUMU_VS_MF2_E32_MASK, VWREDSUMU_VS }, // 11090 |
| 32361 | { PseudoVWREDSUMU_VS_MF2_E8, VWREDSUMU_VS }, // 11091 |
| 32362 | { PseudoVWREDSUMU_VS_MF2_E8_MASK, VWREDSUMU_VS }, // 11092 |
| 32363 | { PseudoVWREDSUMU_VS_MF4_E16, VWREDSUMU_VS }, // 11093 |
| 32364 | { PseudoVWREDSUMU_VS_MF4_E16_MASK, VWREDSUMU_VS }, // 11094 |
| 32365 | { PseudoVWREDSUMU_VS_MF4_E8, VWREDSUMU_VS }, // 11095 |
| 32366 | { PseudoVWREDSUMU_VS_MF4_E8_MASK, VWREDSUMU_VS }, // 11096 |
| 32367 | { PseudoVWREDSUMU_VS_MF8_E8, VWREDSUMU_VS }, // 11097 |
| 32368 | { PseudoVWREDSUMU_VS_MF8_E8_MASK, VWREDSUMU_VS }, // 11098 |
| 32369 | { PseudoVWREDSUM_VS_M1_E16, VWREDSUM_VS }, // 11099 |
| 32370 | { PseudoVWREDSUM_VS_M1_E16_MASK, VWREDSUM_VS }, // 11100 |
| 32371 | { PseudoVWREDSUM_VS_M1_E32, VWREDSUM_VS }, // 11101 |
| 32372 | { PseudoVWREDSUM_VS_M1_E32_MASK, VWREDSUM_VS }, // 11102 |
| 32373 | { PseudoVWREDSUM_VS_M1_E8, VWREDSUM_VS }, // 11103 |
| 32374 | { PseudoVWREDSUM_VS_M1_E8_MASK, VWREDSUM_VS }, // 11104 |
| 32375 | { PseudoVWREDSUM_VS_M2_E16, VWREDSUM_VS }, // 11105 |
| 32376 | { PseudoVWREDSUM_VS_M2_E16_MASK, VWREDSUM_VS }, // 11106 |
| 32377 | { PseudoVWREDSUM_VS_M2_E32, VWREDSUM_VS }, // 11107 |
| 32378 | { PseudoVWREDSUM_VS_M2_E32_MASK, VWREDSUM_VS }, // 11108 |
| 32379 | { PseudoVWREDSUM_VS_M2_E8, VWREDSUM_VS }, // 11109 |
| 32380 | { PseudoVWREDSUM_VS_M2_E8_MASK, VWREDSUM_VS }, // 11110 |
| 32381 | { PseudoVWREDSUM_VS_M4_E16, VWREDSUM_VS }, // 11111 |
| 32382 | { PseudoVWREDSUM_VS_M4_E16_MASK, VWREDSUM_VS }, // 11112 |
| 32383 | { PseudoVWREDSUM_VS_M4_E32, VWREDSUM_VS }, // 11113 |
| 32384 | { PseudoVWREDSUM_VS_M4_E32_MASK, VWREDSUM_VS }, // 11114 |
| 32385 | { PseudoVWREDSUM_VS_M4_E8, VWREDSUM_VS }, // 11115 |
| 32386 | { PseudoVWREDSUM_VS_M4_E8_MASK, VWREDSUM_VS }, // 11116 |
| 32387 | { PseudoVWREDSUM_VS_M8_E16, VWREDSUM_VS }, // 11117 |
| 32388 | { PseudoVWREDSUM_VS_M8_E16_MASK, VWREDSUM_VS }, // 11118 |
| 32389 | { PseudoVWREDSUM_VS_M8_E32, VWREDSUM_VS }, // 11119 |
| 32390 | { PseudoVWREDSUM_VS_M8_E32_MASK, VWREDSUM_VS }, // 11120 |
| 32391 | { PseudoVWREDSUM_VS_M8_E8, VWREDSUM_VS }, // 11121 |
| 32392 | { PseudoVWREDSUM_VS_M8_E8_MASK, VWREDSUM_VS }, // 11122 |
| 32393 | { PseudoVWREDSUM_VS_MF2_E16, VWREDSUM_VS }, // 11123 |
| 32394 | { PseudoVWREDSUM_VS_MF2_E16_MASK, VWREDSUM_VS }, // 11124 |
| 32395 | { PseudoVWREDSUM_VS_MF2_E32, VWREDSUM_VS }, // 11125 |
| 32396 | { PseudoVWREDSUM_VS_MF2_E32_MASK, VWREDSUM_VS }, // 11126 |
| 32397 | { PseudoVWREDSUM_VS_MF2_E8, VWREDSUM_VS }, // 11127 |
| 32398 | { PseudoVWREDSUM_VS_MF2_E8_MASK, VWREDSUM_VS }, // 11128 |
| 32399 | { PseudoVWREDSUM_VS_MF4_E16, VWREDSUM_VS }, // 11129 |
| 32400 | { PseudoVWREDSUM_VS_MF4_E16_MASK, VWREDSUM_VS }, // 11130 |
| 32401 | { PseudoVWREDSUM_VS_MF4_E8, VWREDSUM_VS }, // 11131 |
| 32402 | { PseudoVWREDSUM_VS_MF4_E8_MASK, VWREDSUM_VS }, // 11132 |
| 32403 | { PseudoVWREDSUM_VS_MF8_E8, VWREDSUM_VS }, // 11133 |
| 32404 | { PseudoVWREDSUM_VS_MF8_E8_MASK, VWREDSUM_VS }, // 11134 |
| 32405 | { PseudoVWSLL_VI_M1, VWSLL_VI }, // 11135 |
| 32406 | { PseudoVWSLL_VI_M1_MASK, VWSLL_VI }, // 11136 |
| 32407 | { PseudoVWSLL_VI_M2, VWSLL_VI }, // 11137 |
| 32408 | { PseudoVWSLL_VI_M2_MASK, VWSLL_VI }, // 11138 |
| 32409 | { PseudoVWSLL_VI_M4, VWSLL_VI }, // 11139 |
| 32410 | { PseudoVWSLL_VI_M4_MASK, VWSLL_VI }, // 11140 |
| 32411 | { PseudoVWSLL_VI_MF2, VWSLL_VI }, // 11141 |
| 32412 | { PseudoVWSLL_VI_MF2_MASK, VWSLL_VI }, // 11142 |
| 32413 | { PseudoVWSLL_VI_MF4, VWSLL_VI }, // 11143 |
| 32414 | { PseudoVWSLL_VI_MF4_MASK, VWSLL_VI }, // 11144 |
| 32415 | { PseudoVWSLL_VI_MF8, VWSLL_VI }, // 11145 |
| 32416 | { PseudoVWSLL_VI_MF8_MASK, VWSLL_VI }, // 11146 |
| 32417 | { PseudoVWSLL_VV_M1, VWSLL_VV }, // 11147 |
| 32418 | { PseudoVWSLL_VV_M1_MASK, VWSLL_VV }, // 11148 |
| 32419 | { PseudoVWSLL_VV_M2, VWSLL_VV }, // 11149 |
| 32420 | { PseudoVWSLL_VV_M2_MASK, VWSLL_VV }, // 11150 |
| 32421 | { PseudoVWSLL_VV_M4, VWSLL_VV }, // 11151 |
| 32422 | { PseudoVWSLL_VV_M4_MASK, VWSLL_VV }, // 11152 |
| 32423 | { PseudoVWSLL_VV_MF2, VWSLL_VV }, // 11153 |
| 32424 | { PseudoVWSLL_VV_MF2_MASK, VWSLL_VV }, // 11154 |
| 32425 | { PseudoVWSLL_VV_MF4, VWSLL_VV }, // 11155 |
| 32426 | { PseudoVWSLL_VV_MF4_MASK, VWSLL_VV }, // 11156 |
| 32427 | { PseudoVWSLL_VV_MF8, VWSLL_VV }, // 11157 |
| 32428 | { PseudoVWSLL_VV_MF8_MASK, VWSLL_VV }, // 11158 |
| 32429 | { PseudoVWSLL_VX_M1, VWSLL_VX }, // 11159 |
| 32430 | { PseudoVWSLL_VX_M1_MASK, VWSLL_VX }, // 11160 |
| 32431 | { PseudoVWSLL_VX_M2, VWSLL_VX }, // 11161 |
| 32432 | { PseudoVWSLL_VX_M2_MASK, VWSLL_VX }, // 11162 |
| 32433 | { PseudoVWSLL_VX_M4, VWSLL_VX }, // 11163 |
| 32434 | { PseudoVWSLL_VX_M4_MASK, VWSLL_VX }, // 11164 |
| 32435 | { PseudoVWSLL_VX_MF2, VWSLL_VX }, // 11165 |
| 32436 | { PseudoVWSLL_VX_MF2_MASK, VWSLL_VX }, // 11166 |
| 32437 | { PseudoVWSLL_VX_MF4, VWSLL_VX }, // 11167 |
| 32438 | { PseudoVWSLL_VX_MF4_MASK, VWSLL_VX }, // 11168 |
| 32439 | { PseudoVWSLL_VX_MF8, VWSLL_VX }, // 11169 |
| 32440 | { PseudoVWSLL_VX_MF8_MASK, VWSLL_VX }, // 11170 |
| 32441 | { PseudoVWSUBU_VV_M1, VWSUBU_VV }, // 11171 |
| 32442 | { PseudoVWSUBU_VV_M1_MASK, VWSUBU_VV }, // 11172 |
| 32443 | { PseudoVWSUBU_VV_M2, VWSUBU_VV }, // 11173 |
| 32444 | { PseudoVWSUBU_VV_M2_MASK, VWSUBU_VV }, // 11174 |
| 32445 | { PseudoVWSUBU_VV_M4, VWSUBU_VV }, // 11175 |
| 32446 | { PseudoVWSUBU_VV_M4_MASK, VWSUBU_VV }, // 11176 |
| 32447 | { PseudoVWSUBU_VV_MF2, VWSUBU_VV }, // 11177 |
| 32448 | { PseudoVWSUBU_VV_MF2_MASK, VWSUBU_VV }, // 11178 |
| 32449 | { PseudoVWSUBU_VV_MF4, VWSUBU_VV }, // 11179 |
| 32450 | { PseudoVWSUBU_VV_MF4_MASK, VWSUBU_VV }, // 11180 |
| 32451 | { PseudoVWSUBU_VV_MF8, VWSUBU_VV }, // 11181 |
| 32452 | { PseudoVWSUBU_VV_MF8_MASK, VWSUBU_VV }, // 11182 |
| 32453 | { PseudoVWSUBU_VX_M1, VWSUBU_VX }, // 11183 |
| 32454 | { PseudoVWSUBU_VX_M1_MASK, VWSUBU_VX }, // 11184 |
| 32455 | { PseudoVWSUBU_VX_M2, VWSUBU_VX }, // 11185 |
| 32456 | { PseudoVWSUBU_VX_M2_MASK, VWSUBU_VX }, // 11186 |
| 32457 | { PseudoVWSUBU_VX_M4, VWSUBU_VX }, // 11187 |
| 32458 | { PseudoVWSUBU_VX_M4_MASK, VWSUBU_VX }, // 11188 |
| 32459 | { PseudoVWSUBU_VX_MF2, VWSUBU_VX }, // 11189 |
| 32460 | { PseudoVWSUBU_VX_MF2_MASK, VWSUBU_VX }, // 11190 |
| 32461 | { PseudoVWSUBU_VX_MF4, VWSUBU_VX }, // 11191 |
| 32462 | { PseudoVWSUBU_VX_MF4_MASK, VWSUBU_VX }, // 11192 |
| 32463 | { PseudoVWSUBU_VX_MF8, VWSUBU_VX }, // 11193 |
| 32464 | { PseudoVWSUBU_VX_MF8_MASK, VWSUBU_VX }, // 11194 |
| 32465 | { PseudoVWSUBU_WV_M1, VWSUBU_WV }, // 11195 |
| 32466 | { PseudoVWSUBU_WV_M1_MASK, VWSUBU_WV }, // 11196 |
| 32467 | { PseudoVWSUBU_WV_M1_MASK_TIED, VWSUBU_WV }, // 11197 |
| 32468 | { PseudoVWSUBU_WV_M1_TIED, VWSUBU_WV }, // 11198 |
| 32469 | { PseudoVWSUBU_WV_M2, VWSUBU_WV }, // 11199 |
| 32470 | { PseudoVWSUBU_WV_M2_MASK, VWSUBU_WV }, // 11200 |
| 32471 | { PseudoVWSUBU_WV_M2_MASK_TIED, VWSUBU_WV }, // 11201 |
| 32472 | { PseudoVWSUBU_WV_M2_TIED, VWSUBU_WV }, // 11202 |
| 32473 | { PseudoVWSUBU_WV_M4, VWSUBU_WV }, // 11203 |
| 32474 | { PseudoVWSUBU_WV_M4_MASK, VWSUBU_WV }, // 11204 |
| 32475 | { PseudoVWSUBU_WV_M4_MASK_TIED, VWSUBU_WV }, // 11205 |
| 32476 | { PseudoVWSUBU_WV_M4_TIED, VWSUBU_WV }, // 11206 |
| 32477 | { PseudoVWSUBU_WV_MF2, VWSUBU_WV }, // 11207 |
| 32478 | { PseudoVWSUBU_WV_MF2_MASK, VWSUBU_WV }, // 11208 |
| 32479 | { PseudoVWSUBU_WV_MF2_MASK_TIED, VWSUBU_WV }, // 11209 |
| 32480 | { PseudoVWSUBU_WV_MF2_TIED, VWSUBU_WV }, // 11210 |
| 32481 | { PseudoVWSUBU_WV_MF4, VWSUBU_WV }, // 11211 |
| 32482 | { PseudoVWSUBU_WV_MF4_MASK, VWSUBU_WV }, // 11212 |
| 32483 | { PseudoVWSUBU_WV_MF4_MASK_TIED, VWSUBU_WV }, // 11213 |
| 32484 | { PseudoVWSUBU_WV_MF4_TIED, VWSUBU_WV }, // 11214 |
| 32485 | { PseudoVWSUBU_WV_MF8, VWSUBU_WV }, // 11215 |
| 32486 | { PseudoVWSUBU_WV_MF8_MASK, VWSUBU_WV }, // 11216 |
| 32487 | { PseudoVWSUBU_WV_MF8_MASK_TIED, VWSUBU_WV }, // 11217 |
| 32488 | { PseudoVWSUBU_WV_MF8_TIED, VWSUBU_WV }, // 11218 |
| 32489 | { PseudoVWSUBU_WX_M1, VWSUBU_WX }, // 11219 |
| 32490 | { PseudoVWSUBU_WX_M1_MASK, VWSUBU_WX }, // 11220 |
| 32491 | { PseudoVWSUBU_WX_M2, VWSUBU_WX }, // 11221 |
| 32492 | { PseudoVWSUBU_WX_M2_MASK, VWSUBU_WX }, // 11222 |
| 32493 | { PseudoVWSUBU_WX_M4, VWSUBU_WX }, // 11223 |
| 32494 | { PseudoVWSUBU_WX_M4_MASK, VWSUBU_WX }, // 11224 |
| 32495 | { PseudoVWSUBU_WX_MF2, VWSUBU_WX }, // 11225 |
| 32496 | { PseudoVWSUBU_WX_MF2_MASK, VWSUBU_WX }, // 11226 |
| 32497 | { PseudoVWSUBU_WX_MF4, VWSUBU_WX }, // 11227 |
| 32498 | { PseudoVWSUBU_WX_MF4_MASK, VWSUBU_WX }, // 11228 |
| 32499 | { PseudoVWSUBU_WX_MF8, VWSUBU_WX }, // 11229 |
| 32500 | { PseudoVWSUBU_WX_MF8_MASK, VWSUBU_WX }, // 11230 |
| 32501 | { PseudoVWSUB_VV_M1, VWSUB_VV }, // 11231 |
| 32502 | { PseudoVWSUB_VV_M1_MASK, VWSUB_VV }, // 11232 |
| 32503 | { PseudoVWSUB_VV_M2, VWSUB_VV }, // 11233 |
| 32504 | { PseudoVWSUB_VV_M2_MASK, VWSUB_VV }, // 11234 |
| 32505 | { PseudoVWSUB_VV_M4, VWSUB_VV }, // 11235 |
| 32506 | { PseudoVWSUB_VV_M4_MASK, VWSUB_VV }, // 11236 |
| 32507 | { PseudoVWSUB_VV_MF2, VWSUB_VV }, // 11237 |
| 32508 | { PseudoVWSUB_VV_MF2_MASK, VWSUB_VV }, // 11238 |
| 32509 | { PseudoVWSUB_VV_MF4, VWSUB_VV }, // 11239 |
| 32510 | { PseudoVWSUB_VV_MF4_MASK, VWSUB_VV }, // 11240 |
| 32511 | { PseudoVWSUB_VV_MF8, VWSUB_VV }, // 11241 |
| 32512 | { PseudoVWSUB_VV_MF8_MASK, VWSUB_VV }, // 11242 |
| 32513 | { PseudoVWSUB_VX_M1, VWSUB_VX }, // 11243 |
| 32514 | { PseudoVWSUB_VX_M1_MASK, VWSUB_VX }, // 11244 |
| 32515 | { PseudoVWSUB_VX_M2, VWSUB_VX }, // 11245 |
| 32516 | { PseudoVWSUB_VX_M2_MASK, VWSUB_VX }, // 11246 |
| 32517 | { PseudoVWSUB_VX_M4, VWSUB_VX }, // 11247 |
| 32518 | { PseudoVWSUB_VX_M4_MASK, VWSUB_VX }, // 11248 |
| 32519 | { PseudoVWSUB_VX_MF2, VWSUB_VX }, // 11249 |
| 32520 | { PseudoVWSUB_VX_MF2_MASK, VWSUB_VX }, // 11250 |
| 32521 | { PseudoVWSUB_VX_MF4, VWSUB_VX }, // 11251 |
| 32522 | { PseudoVWSUB_VX_MF4_MASK, VWSUB_VX }, // 11252 |
| 32523 | { PseudoVWSUB_VX_MF8, VWSUB_VX }, // 11253 |
| 32524 | { PseudoVWSUB_VX_MF8_MASK, VWSUB_VX }, // 11254 |
| 32525 | { PseudoVWSUB_WV_M1, VWSUB_WV }, // 11255 |
| 32526 | { PseudoVWSUB_WV_M1_MASK, VWSUB_WV }, // 11256 |
| 32527 | { PseudoVWSUB_WV_M1_MASK_TIED, VWSUB_WV }, // 11257 |
| 32528 | { PseudoVWSUB_WV_M1_TIED, VWSUB_WV }, // 11258 |
| 32529 | { PseudoVWSUB_WV_M2, VWSUB_WV }, // 11259 |
| 32530 | { PseudoVWSUB_WV_M2_MASK, VWSUB_WV }, // 11260 |
| 32531 | { PseudoVWSUB_WV_M2_MASK_TIED, VWSUB_WV }, // 11261 |
| 32532 | { PseudoVWSUB_WV_M2_TIED, VWSUB_WV }, // 11262 |
| 32533 | { PseudoVWSUB_WV_M4, VWSUB_WV }, // 11263 |
| 32534 | { PseudoVWSUB_WV_M4_MASK, VWSUB_WV }, // 11264 |
| 32535 | { PseudoVWSUB_WV_M4_MASK_TIED, VWSUB_WV }, // 11265 |
| 32536 | { PseudoVWSUB_WV_M4_TIED, VWSUB_WV }, // 11266 |
| 32537 | { PseudoVWSUB_WV_MF2, VWSUB_WV }, // 11267 |
| 32538 | { PseudoVWSUB_WV_MF2_MASK, VWSUB_WV }, // 11268 |
| 32539 | { PseudoVWSUB_WV_MF2_MASK_TIED, VWSUB_WV }, // 11269 |
| 32540 | { PseudoVWSUB_WV_MF2_TIED, VWSUB_WV }, // 11270 |
| 32541 | { PseudoVWSUB_WV_MF4, VWSUB_WV }, // 11271 |
| 32542 | { PseudoVWSUB_WV_MF4_MASK, VWSUB_WV }, // 11272 |
| 32543 | { PseudoVWSUB_WV_MF4_MASK_TIED, VWSUB_WV }, // 11273 |
| 32544 | { PseudoVWSUB_WV_MF4_TIED, VWSUB_WV }, // 11274 |
| 32545 | { PseudoVWSUB_WV_MF8, VWSUB_WV }, // 11275 |
| 32546 | { PseudoVWSUB_WV_MF8_MASK, VWSUB_WV }, // 11276 |
| 32547 | { PseudoVWSUB_WV_MF8_MASK_TIED, VWSUB_WV }, // 11277 |
| 32548 | { PseudoVWSUB_WV_MF8_TIED, VWSUB_WV }, // 11278 |
| 32549 | { PseudoVWSUB_WX_M1, VWSUB_WX }, // 11279 |
| 32550 | { PseudoVWSUB_WX_M1_MASK, VWSUB_WX }, // 11280 |
| 32551 | { PseudoVWSUB_WX_M2, VWSUB_WX }, // 11281 |
| 32552 | { PseudoVWSUB_WX_M2_MASK, VWSUB_WX }, // 11282 |
| 32553 | { PseudoVWSUB_WX_M4, VWSUB_WX }, // 11283 |
| 32554 | { PseudoVWSUB_WX_M4_MASK, VWSUB_WX }, // 11284 |
| 32555 | { PseudoVWSUB_WX_MF2, VWSUB_WX }, // 11285 |
| 32556 | { PseudoVWSUB_WX_MF2_MASK, VWSUB_WX }, // 11286 |
| 32557 | { PseudoVWSUB_WX_MF4, VWSUB_WX }, // 11287 |
| 32558 | { PseudoVWSUB_WX_MF4_MASK, VWSUB_WX }, // 11288 |
| 32559 | { PseudoVWSUB_WX_MF8, VWSUB_WX }, // 11289 |
| 32560 | { PseudoVWSUB_WX_MF8_MASK, VWSUB_WX }, // 11290 |
| 32561 | { PseudoVXOR_VI_M1, VXOR_VI }, // 11291 |
| 32562 | { PseudoVXOR_VI_M1_MASK, VXOR_VI }, // 11292 |
| 32563 | { PseudoVXOR_VI_M2, VXOR_VI }, // 11293 |
| 32564 | { PseudoVXOR_VI_M2_MASK, VXOR_VI }, // 11294 |
| 32565 | { PseudoVXOR_VI_M4, VXOR_VI }, // 11295 |
| 32566 | { PseudoVXOR_VI_M4_MASK, VXOR_VI }, // 11296 |
| 32567 | { PseudoVXOR_VI_M8, VXOR_VI }, // 11297 |
| 32568 | { PseudoVXOR_VI_M8_MASK, VXOR_VI }, // 11298 |
| 32569 | { PseudoVXOR_VI_MF2, VXOR_VI }, // 11299 |
| 32570 | { PseudoVXOR_VI_MF2_MASK, VXOR_VI }, // 11300 |
| 32571 | { PseudoVXOR_VI_MF4, VXOR_VI }, // 11301 |
| 32572 | { PseudoVXOR_VI_MF4_MASK, VXOR_VI }, // 11302 |
| 32573 | { PseudoVXOR_VI_MF8, VXOR_VI }, // 11303 |
| 32574 | { PseudoVXOR_VI_MF8_MASK, VXOR_VI }, // 11304 |
| 32575 | { PseudoVXOR_VV_M1, VXOR_VV }, // 11305 |
| 32576 | { PseudoVXOR_VV_M1_MASK, VXOR_VV }, // 11306 |
| 32577 | { PseudoVXOR_VV_M2, VXOR_VV }, // 11307 |
| 32578 | { PseudoVXOR_VV_M2_MASK, VXOR_VV }, // 11308 |
| 32579 | { PseudoVXOR_VV_M4, VXOR_VV }, // 11309 |
| 32580 | { PseudoVXOR_VV_M4_MASK, VXOR_VV }, // 11310 |
| 32581 | { PseudoVXOR_VV_M8, VXOR_VV }, // 11311 |
| 32582 | { PseudoVXOR_VV_M8_MASK, VXOR_VV }, // 11312 |
| 32583 | { PseudoVXOR_VV_MF2, VXOR_VV }, // 11313 |
| 32584 | { PseudoVXOR_VV_MF2_MASK, VXOR_VV }, // 11314 |
| 32585 | { PseudoVXOR_VV_MF4, VXOR_VV }, // 11315 |
| 32586 | { PseudoVXOR_VV_MF4_MASK, VXOR_VV }, // 11316 |
| 32587 | { PseudoVXOR_VV_MF8, VXOR_VV }, // 11317 |
| 32588 | { PseudoVXOR_VV_MF8_MASK, VXOR_VV }, // 11318 |
| 32589 | { PseudoVXOR_VX_M1, VXOR_VX }, // 11319 |
| 32590 | { PseudoVXOR_VX_M1_MASK, VXOR_VX }, // 11320 |
| 32591 | { PseudoVXOR_VX_M2, VXOR_VX }, // 11321 |
| 32592 | { PseudoVXOR_VX_M2_MASK, VXOR_VX }, // 11322 |
| 32593 | { PseudoVXOR_VX_M4, VXOR_VX }, // 11323 |
| 32594 | { PseudoVXOR_VX_M4_MASK, VXOR_VX }, // 11324 |
| 32595 | { PseudoVXOR_VX_M8, VXOR_VX }, // 11325 |
| 32596 | { PseudoVXOR_VX_M8_MASK, VXOR_VX }, // 11326 |
| 32597 | { PseudoVXOR_VX_MF2, VXOR_VX }, // 11327 |
| 32598 | { PseudoVXOR_VX_MF2_MASK, VXOR_VX }, // 11328 |
| 32599 | { PseudoVXOR_VX_MF4, VXOR_VX }, // 11329 |
| 32600 | { PseudoVXOR_VX_MF4_MASK, VXOR_VX }, // 11330 |
| 32601 | { PseudoVXOR_VX_MF8, VXOR_VX }, // 11331 |
| 32602 | { PseudoVXOR_VX_MF8_MASK, VXOR_VX }, // 11332 |
| 32603 | { PseudoVZEXT_VF2_M1, VZEXT_VF2 }, // 11333 |
| 32604 | { PseudoVZEXT_VF2_M1_MASK, VZEXT_VF2 }, // 11334 |
| 32605 | { PseudoVZEXT_VF2_M2, VZEXT_VF2 }, // 11335 |
| 32606 | { PseudoVZEXT_VF2_M2_MASK, VZEXT_VF2 }, // 11336 |
| 32607 | { PseudoVZEXT_VF2_M4, VZEXT_VF2 }, // 11337 |
| 32608 | { PseudoVZEXT_VF2_M4_MASK, VZEXT_VF2 }, // 11338 |
| 32609 | { PseudoVZEXT_VF2_M8, VZEXT_VF2 }, // 11339 |
| 32610 | { PseudoVZEXT_VF2_M8_MASK, VZEXT_VF2 }, // 11340 |
| 32611 | { PseudoVZEXT_VF2_MF2, VZEXT_VF2 }, // 11341 |
| 32612 | { PseudoVZEXT_VF2_MF2_MASK, VZEXT_VF2 }, // 11342 |
| 32613 | { PseudoVZEXT_VF2_MF4, VZEXT_VF2 }, // 11343 |
| 32614 | { PseudoVZEXT_VF2_MF4_MASK, VZEXT_VF2 }, // 11344 |
| 32615 | { PseudoVZEXT_VF4_M1, VZEXT_VF4 }, // 11345 |
| 32616 | { PseudoVZEXT_VF4_M1_MASK, VZEXT_VF4 }, // 11346 |
| 32617 | { PseudoVZEXT_VF4_M2, VZEXT_VF4 }, // 11347 |
| 32618 | { PseudoVZEXT_VF4_M2_MASK, VZEXT_VF4 }, // 11348 |
| 32619 | { PseudoVZEXT_VF4_M4, VZEXT_VF4 }, // 11349 |
| 32620 | { PseudoVZEXT_VF4_M4_MASK, VZEXT_VF4 }, // 11350 |
| 32621 | { PseudoVZEXT_VF4_M8, VZEXT_VF4 }, // 11351 |
| 32622 | { PseudoVZEXT_VF4_M8_MASK, VZEXT_VF4 }, // 11352 |
| 32623 | { PseudoVZEXT_VF4_MF2, VZEXT_VF4 }, // 11353 |
| 32624 | { PseudoVZEXT_VF4_MF2_MASK, VZEXT_VF4 }, // 11354 |
| 32625 | { PseudoVZEXT_VF8_M1, VZEXT_VF8 }, // 11355 |
| 32626 | { PseudoVZEXT_VF8_M1_MASK, VZEXT_VF8 }, // 11356 |
| 32627 | { PseudoVZEXT_VF8_M2, VZEXT_VF8 }, // 11357 |
| 32628 | { PseudoVZEXT_VF8_M2_MASK, VZEXT_VF8 }, // 11358 |
| 32629 | { PseudoVZEXT_VF8_M4, VZEXT_VF8 }, // 11359 |
| 32630 | { PseudoVZEXT_VF8_M4_MASK, VZEXT_VF8 }, // 11360 |
| 32631 | { PseudoVZEXT_VF8_M8, VZEXT_VF8 }, // 11361 |
| 32632 | { PseudoVZEXT_VF8_M8_MASK, VZEXT_VF8 }, // 11362 |
| 32633 | }; |
| 32634 | |
| 32635 | const PseudoInfo *getPseudoInfo(unsigned Pseudo) { |
| 32636 | if ((Pseudo < PseudoTHVdotVMAQASU_VV_M1) || |
| 32637 | (Pseudo > PseudoVZEXT_VF8_M8_MASK)) |
| 32638 | return nullptr; |
| 32639 | |
| 32640 | struct KeyType { |
| 32641 | unsigned Pseudo; |
| 32642 | }; |
| 32643 | KeyType Key = {Pseudo}; |
| 32644 | struct Comp { |
| 32645 | bool operator()(const PseudoInfo &LHS, const KeyType &RHS) const { |
| 32646 | if (LHS.Pseudo < RHS.Pseudo) |
| 32647 | return true; |
| 32648 | if (LHS.Pseudo > RHS.Pseudo) |
| 32649 | return false; |
| 32650 | return false; |
| 32651 | } |
| 32652 | }; |
| 32653 | auto Table = ArrayRef(RISCVVPseudosTable); |
| 32654 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 32655 | if (Idx == Table.end() || |
| 32656 | Key.Pseudo != Idx->Pseudo) |
| 32657 | return nullptr; |
| 32658 | |
| 32659 | return &*Idx; |
| 32660 | } |
| 32661 | #endif |
| 32662 | |
| 32663 | #ifdef GET_RISCVVSETable_DECL |
| 32664 | const VSEPseudo *getVSEPseudo(uint8_t Masked, uint8_t Strided, uint8_t Log2SEW, uint8_t LMUL); |
| 32665 | #endif |
| 32666 | |
| 32667 | #ifdef GET_RISCVVSETable_IMPL |
| 32668 | constexpr VSEPseudo RISCVVSETable[] = { |
| 32669 | { 0x0, 0x0, 0x0, 0x0, PseudoVSM_V_B8 }, // 0 |
| 32670 | { 0x0, 0x0, 0x0, 0x1, PseudoVSM_V_B16 }, // 1 |
| 32671 | { 0x0, 0x0, 0x0, 0x2, PseudoVSM_V_B32 }, // 2 |
| 32672 | { 0x0, 0x0, 0x0, 0x3, PseudoVSM_V_B64 }, // 3 |
| 32673 | { 0x0, 0x0, 0x0, 0x5, PseudoVSM_V_B1 }, // 4 |
| 32674 | { 0x0, 0x0, 0x0, 0x6, PseudoVSM_V_B2 }, // 5 |
| 32675 | { 0x0, 0x0, 0x0, 0x7, PseudoVSM_V_B4 }, // 6 |
| 32676 | { 0x0, 0x0, 0x3, 0x0, PseudoVSE8_V_M1 }, // 7 |
| 32677 | { 0x0, 0x0, 0x3, 0x1, PseudoVSE8_V_M2 }, // 8 |
| 32678 | { 0x0, 0x0, 0x3, 0x2, PseudoVSE8_V_M4 }, // 9 |
| 32679 | { 0x0, 0x0, 0x3, 0x3, PseudoVSE8_V_M8 }, // 10 |
| 32680 | { 0x0, 0x0, 0x3, 0x5, PseudoVSE8_V_MF8 }, // 11 |
| 32681 | { 0x0, 0x0, 0x3, 0x6, PseudoVSE8_V_MF4 }, // 12 |
| 32682 | { 0x0, 0x0, 0x3, 0x7, PseudoVSE8_V_MF2 }, // 13 |
| 32683 | { 0x0, 0x0, 0x4, 0x0, PseudoVSE16_V_M1 }, // 14 |
| 32684 | { 0x0, 0x0, 0x4, 0x1, PseudoVSE16_V_M2 }, // 15 |
| 32685 | { 0x0, 0x0, 0x4, 0x2, PseudoVSE16_V_M4 }, // 16 |
| 32686 | { 0x0, 0x0, 0x4, 0x3, PseudoVSE16_V_M8 }, // 17 |
| 32687 | { 0x0, 0x0, 0x4, 0x6, PseudoVSE16_V_MF4 }, // 18 |
| 32688 | { 0x0, 0x0, 0x4, 0x7, PseudoVSE16_V_MF2 }, // 19 |
| 32689 | { 0x0, 0x0, 0x5, 0x0, PseudoVSE32_V_M1 }, // 20 |
| 32690 | { 0x0, 0x0, 0x5, 0x1, PseudoVSE32_V_M2 }, // 21 |
| 32691 | { 0x0, 0x0, 0x5, 0x2, PseudoVSE32_V_M4 }, // 22 |
| 32692 | { 0x0, 0x0, 0x5, 0x3, PseudoVSE32_V_M8 }, // 23 |
| 32693 | { 0x0, 0x0, 0x5, 0x7, PseudoVSE32_V_MF2 }, // 24 |
| 32694 | { 0x0, 0x0, 0x6, 0x0, PseudoVSE64_V_M1 }, // 25 |
| 32695 | { 0x0, 0x0, 0x6, 0x1, PseudoVSE64_V_M2 }, // 26 |
| 32696 | { 0x0, 0x0, 0x6, 0x2, PseudoVSE64_V_M4 }, // 27 |
| 32697 | { 0x0, 0x0, 0x6, 0x3, PseudoVSE64_V_M8 }, // 28 |
| 32698 | { 0x0, 0x1, 0x3, 0x0, PseudoVSSE8_V_M1 }, // 29 |
| 32699 | { 0x0, 0x1, 0x3, 0x1, PseudoVSSE8_V_M2 }, // 30 |
| 32700 | { 0x0, 0x1, 0x3, 0x2, PseudoVSSE8_V_M4 }, // 31 |
| 32701 | { 0x0, 0x1, 0x3, 0x3, PseudoVSSE8_V_M8 }, // 32 |
| 32702 | { 0x0, 0x1, 0x3, 0x5, PseudoVSSE8_V_MF8 }, // 33 |
| 32703 | { 0x0, 0x1, 0x3, 0x6, PseudoVSSE8_V_MF4 }, // 34 |
| 32704 | { 0x0, 0x1, 0x3, 0x7, PseudoVSSE8_V_MF2 }, // 35 |
| 32705 | { 0x0, 0x1, 0x4, 0x0, PseudoVSSE16_V_M1 }, // 36 |
| 32706 | { 0x0, 0x1, 0x4, 0x1, PseudoVSSE16_V_M2 }, // 37 |
| 32707 | { 0x0, 0x1, 0x4, 0x2, PseudoVSSE16_V_M4 }, // 38 |
| 32708 | { 0x0, 0x1, 0x4, 0x3, PseudoVSSE16_V_M8 }, // 39 |
| 32709 | { 0x0, 0x1, 0x4, 0x6, PseudoVSSE16_V_MF4 }, // 40 |
| 32710 | { 0x0, 0x1, 0x4, 0x7, PseudoVSSE16_V_MF2 }, // 41 |
| 32711 | { 0x0, 0x1, 0x5, 0x0, PseudoVSSE32_V_M1 }, // 42 |
| 32712 | { 0x0, 0x1, 0x5, 0x1, PseudoVSSE32_V_M2 }, // 43 |
| 32713 | { 0x0, 0x1, 0x5, 0x2, PseudoVSSE32_V_M4 }, // 44 |
| 32714 | { 0x0, 0x1, 0x5, 0x3, PseudoVSSE32_V_M8 }, // 45 |
| 32715 | { 0x0, 0x1, 0x5, 0x7, PseudoVSSE32_V_MF2 }, // 46 |
| 32716 | { 0x0, 0x1, 0x6, 0x0, PseudoVSSE64_V_M1 }, // 47 |
| 32717 | { 0x0, 0x1, 0x6, 0x1, PseudoVSSE64_V_M2 }, // 48 |
| 32718 | { 0x0, 0x1, 0x6, 0x2, PseudoVSSE64_V_M4 }, // 49 |
| 32719 | { 0x0, 0x1, 0x6, 0x3, PseudoVSSE64_V_M8 }, // 50 |
| 32720 | { 0x1, 0x0, 0x3, 0x0, PseudoVSE8_V_M1_MASK }, // 51 |
| 32721 | { 0x1, 0x0, 0x3, 0x1, PseudoVSE8_V_M2_MASK }, // 52 |
| 32722 | { 0x1, 0x0, 0x3, 0x2, PseudoVSE8_V_M4_MASK }, // 53 |
| 32723 | { 0x1, 0x0, 0x3, 0x3, PseudoVSE8_V_M8_MASK }, // 54 |
| 32724 | { 0x1, 0x0, 0x3, 0x5, PseudoVSE8_V_MF8_MASK }, // 55 |
| 32725 | { 0x1, 0x0, 0x3, 0x6, PseudoVSE8_V_MF4_MASK }, // 56 |
| 32726 | { 0x1, 0x0, 0x3, 0x7, PseudoVSE8_V_MF2_MASK }, // 57 |
| 32727 | { 0x1, 0x0, 0x4, 0x0, PseudoVSE16_V_M1_MASK }, // 58 |
| 32728 | { 0x1, 0x0, 0x4, 0x1, PseudoVSE16_V_M2_MASK }, // 59 |
| 32729 | { 0x1, 0x0, 0x4, 0x2, PseudoVSE16_V_M4_MASK }, // 60 |
| 32730 | { 0x1, 0x0, 0x4, 0x3, PseudoVSE16_V_M8_MASK }, // 61 |
| 32731 | { 0x1, 0x0, 0x4, 0x6, PseudoVSE16_V_MF4_MASK }, // 62 |
| 32732 | { 0x1, 0x0, 0x4, 0x7, PseudoVSE16_V_MF2_MASK }, // 63 |
| 32733 | { 0x1, 0x0, 0x5, 0x0, PseudoVSE32_V_M1_MASK }, // 64 |
| 32734 | { 0x1, 0x0, 0x5, 0x1, PseudoVSE32_V_M2_MASK }, // 65 |
| 32735 | { 0x1, 0x0, 0x5, 0x2, PseudoVSE32_V_M4_MASK }, // 66 |
| 32736 | { 0x1, 0x0, 0x5, 0x3, PseudoVSE32_V_M8_MASK }, // 67 |
| 32737 | { 0x1, 0x0, 0x5, 0x7, PseudoVSE32_V_MF2_MASK }, // 68 |
| 32738 | { 0x1, 0x0, 0x6, 0x0, PseudoVSE64_V_M1_MASK }, // 69 |
| 32739 | { 0x1, 0x0, 0x6, 0x1, PseudoVSE64_V_M2_MASK }, // 70 |
| 32740 | { 0x1, 0x0, 0x6, 0x2, PseudoVSE64_V_M4_MASK }, // 71 |
| 32741 | { 0x1, 0x0, 0x6, 0x3, PseudoVSE64_V_M8_MASK }, // 72 |
| 32742 | { 0x1, 0x1, 0x3, 0x0, PseudoVSSE8_V_M1_MASK }, // 73 |
| 32743 | { 0x1, 0x1, 0x3, 0x1, PseudoVSSE8_V_M2_MASK }, // 74 |
| 32744 | { 0x1, 0x1, 0x3, 0x2, PseudoVSSE8_V_M4_MASK }, // 75 |
| 32745 | { 0x1, 0x1, 0x3, 0x3, PseudoVSSE8_V_M8_MASK }, // 76 |
| 32746 | { 0x1, 0x1, 0x3, 0x5, PseudoVSSE8_V_MF8_MASK }, // 77 |
| 32747 | { 0x1, 0x1, 0x3, 0x6, PseudoVSSE8_V_MF4_MASK }, // 78 |
| 32748 | { 0x1, 0x1, 0x3, 0x7, PseudoVSSE8_V_MF2_MASK }, // 79 |
| 32749 | { 0x1, 0x1, 0x4, 0x0, PseudoVSSE16_V_M1_MASK }, // 80 |
| 32750 | { 0x1, 0x1, 0x4, 0x1, PseudoVSSE16_V_M2_MASK }, // 81 |
| 32751 | { 0x1, 0x1, 0x4, 0x2, PseudoVSSE16_V_M4_MASK }, // 82 |
| 32752 | { 0x1, 0x1, 0x4, 0x3, PseudoVSSE16_V_M8_MASK }, // 83 |
| 32753 | { 0x1, 0x1, 0x4, 0x6, PseudoVSSE16_V_MF4_MASK }, // 84 |
| 32754 | { 0x1, 0x1, 0x4, 0x7, PseudoVSSE16_V_MF2_MASK }, // 85 |
| 32755 | { 0x1, 0x1, 0x5, 0x0, PseudoVSSE32_V_M1_MASK }, // 86 |
| 32756 | { 0x1, 0x1, 0x5, 0x1, PseudoVSSE32_V_M2_MASK }, // 87 |
| 32757 | { 0x1, 0x1, 0x5, 0x2, PseudoVSSE32_V_M4_MASK }, // 88 |
| 32758 | { 0x1, 0x1, 0x5, 0x3, PseudoVSSE32_V_M8_MASK }, // 89 |
| 32759 | { 0x1, 0x1, 0x5, 0x7, PseudoVSSE32_V_MF2_MASK }, // 90 |
| 32760 | { 0x1, 0x1, 0x6, 0x0, PseudoVSSE64_V_M1_MASK }, // 91 |
| 32761 | { 0x1, 0x1, 0x6, 0x1, PseudoVSSE64_V_M2_MASK }, // 92 |
| 32762 | { 0x1, 0x1, 0x6, 0x2, PseudoVSSE64_V_M4_MASK }, // 93 |
| 32763 | { 0x1, 0x1, 0x6, 0x3, PseudoVSSE64_V_M8_MASK }, // 94 |
| 32764 | }; |
| 32765 | |
| 32766 | const VSEPseudo *getVSEPseudo(uint8_t Masked, uint8_t Strided, uint8_t Log2SEW, uint8_t LMUL) { |
| 32767 | struct KeyType { |
| 32768 | uint8_t Masked; |
| 32769 | uint8_t Strided; |
| 32770 | uint8_t Log2SEW; |
| 32771 | uint8_t LMUL; |
| 32772 | }; |
| 32773 | KeyType Key = {Masked, Strided, Log2SEW, LMUL}; |
| 32774 | struct Comp { |
| 32775 | bool operator()(const VSEPseudo &LHS, const KeyType &RHS) const { |
| 32776 | if (LHS.Masked < RHS.Masked) |
| 32777 | return true; |
| 32778 | if (LHS.Masked > RHS.Masked) |
| 32779 | return false; |
| 32780 | if (LHS.Strided < RHS.Strided) |
| 32781 | return true; |
| 32782 | if (LHS.Strided > RHS.Strided) |
| 32783 | return false; |
| 32784 | if (LHS.Log2SEW < RHS.Log2SEW) |
| 32785 | return true; |
| 32786 | if (LHS.Log2SEW > RHS.Log2SEW) |
| 32787 | return false; |
| 32788 | if (LHS.LMUL < RHS.LMUL) |
| 32789 | return true; |
| 32790 | if (LHS.LMUL > RHS.LMUL) |
| 32791 | return false; |
| 32792 | return false; |
| 32793 | } |
| 32794 | }; |
| 32795 | auto Table = ArrayRef(RISCVVSETable); |
| 32796 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 32797 | if (Idx == Table.end() || |
| 32798 | Key.Masked != Idx->Masked || |
| 32799 | Key.Strided != Idx->Strided || |
| 32800 | Key.Log2SEW != Idx->Log2SEW || |
| 32801 | Key.LMUL != Idx->LMUL) |
| 32802 | return nullptr; |
| 32803 | |
| 32804 | return &*Idx; |
| 32805 | } |
| 32806 | #endif |
| 32807 | |
| 32808 | #ifdef GET_RISCVVSSEGTable_DECL |
| 32809 | const VSSEGPseudo *getVSSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Strided, uint8_t Log2SEW, uint8_t LMUL); |
| 32810 | #endif |
| 32811 | |
| 32812 | #ifdef GET_RISCVVSSEGTable_IMPL |
| 32813 | constexpr VSSEGPseudo RISCVVSSEGTable[] = { |
| 32814 | { 0x2, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG2E8_V_M1 }, // 0 |
| 32815 | { 0x2, 0x0, 0x0, 0x3, 0x1, PseudoVSSEG2E8_V_M2 }, // 1 |
| 32816 | { 0x2, 0x0, 0x0, 0x3, 0x2, PseudoVSSEG2E8_V_M4 }, // 2 |
| 32817 | { 0x2, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG2E8_V_MF8 }, // 3 |
| 32818 | { 0x2, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG2E8_V_MF4 }, // 4 |
| 32819 | { 0x2, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG2E8_V_MF2 }, // 5 |
| 32820 | { 0x2, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG2E16_V_M1 }, // 6 |
| 32821 | { 0x2, 0x0, 0x0, 0x4, 0x1, PseudoVSSEG2E16_V_M2 }, // 7 |
| 32822 | { 0x2, 0x0, 0x0, 0x4, 0x2, PseudoVSSEG2E16_V_M4 }, // 8 |
| 32823 | { 0x2, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG2E16_V_MF4 }, // 9 |
| 32824 | { 0x2, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG2E16_V_MF2 }, // 10 |
| 32825 | { 0x2, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG2E32_V_M1 }, // 11 |
| 32826 | { 0x2, 0x0, 0x0, 0x5, 0x1, PseudoVSSEG2E32_V_M2 }, // 12 |
| 32827 | { 0x2, 0x0, 0x0, 0x5, 0x2, PseudoVSSEG2E32_V_M4 }, // 13 |
| 32828 | { 0x2, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG2E32_V_MF2 }, // 14 |
| 32829 | { 0x2, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG2E64_V_M1 }, // 15 |
| 32830 | { 0x2, 0x0, 0x0, 0x6, 0x1, PseudoVSSEG2E64_V_M2 }, // 16 |
| 32831 | { 0x2, 0x0, 0x0, 0x6, 0x2, PseudoVSSEG2E64_V_M4 }, // 17 |
| 32832 | { 0x2, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG2E8_V_M1 }, // 18 |
| 32833 | { 0x2, 0x0, 0x1, 0x3, 0x1, PseudoVSSSEG2E8_V_M2 }, // 19 |
| 32834 | { 0x2, 0x0, 0x1, 0x3, 0x2, PseudoVSSSEG2E8_V_M4 }, // 20 |
| 32835 | { 0x2, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG2E8_V_MF8 }, // 21 |
| 32836 | { 0x2, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG2E8_V_MF4 }, // 22 |
| 32837 | { 0x2, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG2E8_V_MF2 }, // 23 |
| 32838 | { 0x2, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG2E16_V_M1 }, // 24 |
| 32839 | { 0x2, 0x0, 0x1, 0x4, 0x1, PseudoVSSSEG2E16_V_M2 }, // 25 |
| 32840 | { 0x2, 0x0, 0x1, 0x4, 0x2, PseudoVSSSEG2E16_V_M4 }, // 26 |
| 32841 | { 0x2, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG2E16_V_MF4 }, // 27 |
| 32842 | { 0x2, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG2E16_V_MF2 }, // 28 |
| 32843 | { 0x2, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG2E32_V_M1 }, // 29 |
| 32844 | { 0x2, 0x0, 0x1, 0x5, 0x1, PseudoVSSSEG2E32_V_M2 }, // 30 |
| 32845 | { 0x2, 0x0, 0x1, 0x5, 0x2, PseudoVSSSEG2E32_V_M4 }, // 31 |
| 32846 | { 0x2, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG2E32_V_MF2 }, // 32 |
| 32847 | { 0x2, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG2E64_V_M1 }, // 33 |
| 32848 | { 0x2, 0x0, 0x1, 0x6, 0x1, PseudoVSSSEG2E64_V_M2 }, // 34 |
| 32849 | { 0x2, 0x0, 0x1, 0x6, 0x2, PseudoVSSSEG2E64_V_M4 }, // 35 |
| 32850 | { 0x2, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG2E8_V_M1_MASK }, // 36 |
| 32851 | { 0x2, 0x1, 0x0, 0x3, 0x1, PseudoVSSEG2E8_V_M2_MASK }, // 37 |
| 32852 | { 0x2, 0x1, 0x0, 0x3, 0x2, PseudoVSSEG2E8_V_M4_MASK }, // 38 |
| 32853 | { 0x2, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG2E8_V_MF8_MASK }, // 39 |
| 32854 | { 0x2, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG2E8_V_MF4_MASK }, // 40 |
| 32855 | { 0x2, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG2E8_V_MF2_MASK }, // 41 |
| 32856 | { 0x2, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG2E16_V_M1_MASK }, // 42 |
| 32857 | { 0x2, 0x1, 0x0, 0x4, 0x1, PseudoVSSEG2E16_V_M2_MASK }, // 43 |
| 32858 | { 0x2, 0x1, 0x0, 0x4, 0x2, PseudoVSSEG2E16_V_M4_MASK }, // 44 |
| 32859 | { 0x2, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG2E16_V_MF4_MASK }, // 45 |
| 32860 | { 0x2, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG2E16_V_MF2_MASK }, // 46 |
| 32861 | { 0x2, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG2E32_V_M1_MASK }, // 47 |
| 32862 | { 0x2, 0x1, 0x0, 0x5, 0x1, PseudoVSSEG2E32_V_M2_MASK }, // 48 |
| 32863 | { 0x2, 0x1, 0x0, 0x5, 0x2, PseudoVSSEG2E32_V_M4_MASK }, // 49 |
| 32864 | { 0x2, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG2E32_V_MF2_MASK }, // 50 |
| 32865 | { 0x2, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG2E64_V_M1_MASK }, // 51 |
| 32866 | { 0x2, 0x1, 0x0, 0x6, 0x1, PseudoVSSEG2E64_V_M2_MASK }, // 52 |
| 32867 | { 0x2, 0x1, 0x0, 0x6, 0x2, PseudoVSSEG2E64_V_M4_MASK }, // 53 |
| 32868 | { 0x2, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG2E8_V_M1_MASK }, // 54 |
| 32869 | { 0x2, 0x1, 0x1, 0x3, 0x1, PseudoVSSSEG2E8_V_M2_MASK }, // 55 |
| 32870 | { 0x2, 0x1, 0x1, 0x3, 0x2, PseudoVSSSEG2E8_V_M4_MASK }, // 56 |
| 32871 | { 0x2, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG2E8_V_MF8_MASK }, // 57 |
| 32872 | { 0x2, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG2E8_V_MF4_MASK }, // 58 |
| 32873 | { 0x2, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG2E8_V_MF2_MASK }, // 59 |
| 32874 | { 0x2, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG2E16_V_M1_MASK }, // 60 |
| 32875 | { 0x2, 0x1, 0x1, 0x4, 0x1, PseudoVSSSEG2E16_V_M2_MASK }, // 61 |
| 32876 | { 0x2, 0x1, 0x1, 0x4, 0x2, PseudoVSSSEG2E16_V_M4_MASK }, // 62 |
| 32877 | { 0x2, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG2E16_V_MF4_MASK }, // 63 |
| 32878 | { 0x2, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG2E16_V_MF2_MASK }, // 64 |
| 32879 | { 0x2, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG2E32_V_M1_MASK }, // 65 |
| 32880 | { 0x2, 0x1, 0x1, 0x5, 0x1, PseudoVSSSEG2E32_V_M2_MASK }, // 66 |
| 32881 | { 0x2, 0x1, 0x1, 0x5, 0x2, PseudoVSSSEG2E32_V_M4_MASK }, // 67 |
| 32882 | { 0x2, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG2E32_V_MF2_MASK }, // 68 |
| 32883 | { 0x2, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG2E64_V_M1_MASK }, // 69 |
| 32884 | { 0x2, 0x1, 0x1, 0x6, 0x1, PseudoVSSSEG2E64_V_M2_MASK }, // 70 |
| 32885 | { 0x2, 0x1, 0x1, 0x6, 0x2, PseudoVSSSEG2E64_V_M4_MASK }, // 71 |
| 32886 | { 0x3, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG3E8_V_M1 }, // 72 |
| 32887 | { 0x3, 0x0, 0x0, 0x3, 0x1, PseudoVSSEG3E8_V_M2 }, // 73 |
| 32888 | { 0x3, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG3E8_V_MF8 }, // 74 |
| 32889 | { 0x3, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG3E8_V_MF4 }, // 75 |
| 32890 | { 0x3, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG3E8_V_MF2 }, // 76 |
| 32891 | { 0x3, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG3E16_V_M1 }, // 77 |
| 32892 | { 0x3, 0x0, 0x0, 0x4, 0x1, PseudoVSSEG3E16_V_M2 }, // 78 |
| 32893 | { 0x3, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG3E16_V_MF4 }, // 79 |
| 32894 | { 0x3, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG3E16_V_MF2 }, // 80 |
| 32895 | { 0x3, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG3E32_V_M1 }, // 81 |
| 32896 | { 0x3, 0x0, 0x0, 0x5, 0x1, PseudoVSSEG3E32_V_M2 }, // 82 |
| 32897 | { 0x3, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG3E32_V_MF2 }, // 83 |
| 32898 | { 0x3, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG3E64_V_M1 }, // 84 |
| 32899 | { 0x3, 0x0, 0x0, 0x6, 0x1, PseudoVSSEG3E64_V_M2 }, // 85 |
| 32900 | { 0x3, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG3E8_V_M1 }, // 86 |
| 32901 | { 0x3, 0x0, 0x1, 0x3, 0x1, PseudoVSSSEG3E8_V_M2 }, // 87 |
| 32902 | { 0x3, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG3E8_V_MF8 }, // 88 |
| 32903 | { 0x3, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG3E8_V_MF4 }, // 89 |
| 32904 | { 0x3, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG3E8_V_MF2 }, // 90 |
| 32905 | { 0x3, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG3E16_V_M1 }, // 91 |
| 32906 | { 0x3, 0x0, 0x1, 0x4, 0x1, PseudoVSSSEG3E16_V_M2 }, // 92 |
| 32907 | { 0x3, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG3E16_V_MF4 }, // 93 |
| 32908 | { 0x3, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG3E16_V_MF2 }, // 94 |
| 32909 | { 0x3, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG3E32_V_M1 }, // 95 |
| 32910 | { 0x3, 0x0, 0x1, 0x5, 0x1, PseudoVSSSEG3E32_V_M2 }, // 96 |
| 32911 | { 0x3, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG3E32_V_MF2 }, // 97 |
| 32912 | { 0x3, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG3E64_V_M1 }, // 98 |
| 32913 | { 0x3, 0x0, 0x1, 0x6, 0x1, PseudoVSSSEG3E64_V_M2 }, // 99 |
| 32914 | { 0x3, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG3E8_V_M1_MASK }, // 100 |
| 32915 | { 0x3, 0x1, 0x0, 0x3, 0x1, PseudoVSSEG3E8_V_M2_MASK }, // 101 |
| 32916 | { 0x3, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG3E8_V_MF8_MASK }, // 102 |
| 32917 | { 0x3, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG3E8_V_MF4_MASK }, // 103 |
| 32918 | { 0x3, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG3E8_V_MF2_MASK }, // 104 |
| 32919 | { 0x3, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG3E16_V_M1_MASK }, // 105 |
| 32920 | { 0x3, 0x1, 0x0, 0x4, 0x1, PseudoVSSEG3E16_V_M2_MASK }, // 106 |
| 32921 | { 0x3, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG3E16_V_MF4_MASK }, // 107 |
| 32922 | { 0x3, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG3E16_V_MF2_MASK }, // 108 |
| 32923 | { 0x3, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG3E32_V_M1_MASK }, // 109 |
| 32924 | { 0x3, 0x1, 0x0, 0x5, 0x1, PseudoVSSEG3E32_V_M2_MASK }, // 110 |
| 32925 | { 0x3, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG3E32_V_MF2_MASK }, // 111 |
| 32926 | { 0x3, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG3E64_V_M1_MASK }, // 112 |
| 32927 | { 0x3, 0x1, 0x0, 0x6, 0x1, PseudoVSSEG3E64_V_M2_MASK }, // 113 |
| 32928 | { 0x3, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG3E8_V_M1_MASK }, // 114 |
| 32929 | { 0x3, 0x1, 0x1, 0x3, 0x1, PseudoVSSSEG3E8_V_M2_MASK }, // 115 |
| 32930 | { 0x3, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG3E8_V_MF8_MASK }, // 116 |
| 32931 | { 0x3, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG3E8_V_MF4_MASK }, // 117 |
| 32932 | { 0x3, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG3E8_V_MF2_MASK }, // 118 |
| 32933 | { 0x3, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG3E16_V_M1_MASK }, // 119 |
| 32934 | { 0x3, 0x1, 0x1, 0x4, 0x1, PseudoVSSSEG3E16_V_M2_MASK }, // 120 |
| 32935 | { 0x3, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG3E16_V_MF4_MASK }, // 121 |
| 32936 | { 0x3, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG3E16_V_MF2_MASK }, // 122 |
| 32937 | { 0x3, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG3E32_V_M1_MASK }, // 123 |
| 32938 | { 0x3, 0x1, 0x1, 0x5, 0x1, PseudoVSSSEG3E32_V_M2_MASK }, // 124 |
| 32939 | { 0x3, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG3E32_V_MF2_MASK }, // 125 |
| 32940 | { 0x3, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG3E64_V_M1_MASK }, // 126 |
| 32941 | { 0x3, 0x1, 0x1, 0x6, 0x1, PseudoVSSSEG3E64_V_M2_MASK }, // 127 |
| 32942 | { 0x4, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG4E8_V_M1 }, // 128 |
| 32943 | { 0x4, 0x0, 0x0, 0x3, 0x1, PseudoVSSEG4E8_V_M2 }, // 129 |
| 32944 | { 0x4, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG4E8_V_MF8 }, // 130 |
| 32945 | { 0x4, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG4E8_V_MF4 }, // 131 |
| 32946 | { 0x4, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG4E8_V_MF2 }, // 132 |
| 32947 | { 0x4, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG4E16_V_M1 }, // 133 |
| 32948 | { 0x4, 0x0, 0x0, 0x4, 0x1, PseudoVSSEG4E16_V_M2 }, // 134 |
| 32949 | { 0x4, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG4E16_V_MF4 }, // 135 |
| 32950 | { 0x4, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG4E16_V_MF2 }, // 136 |
| 32951 | { 0x4, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG4E32_V_M1 }, // 137 |
| 32952 | { 0x4, 0x0, 0x0, 0x5, 0x1, PseudoVSSEG4E32_V_M2 }, // 138 |
| 32953 | { 0x4, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG4E32_V_MF2 }, // 139 |
| 32954 | { 0x4, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG4E64_V_M1 }, // 140 |
| 32955 | { 0x4, 0x0, 0x0, 0x6, 0x1, PseudoVSSEG4E64_V_M2 }, // 141 |
| 32956 | { 0x4, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG4E8_V_M1 }, // 142 |
| 32957 | { 0x4, 0x0, 0x1, 0x3, 0x1, PseudoVSSSEG4E8_V_M2 }, // 143 |
| 32958 | { 0x4, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG4E8_V_MF8 }, // 144 |
| 32959 | { 0x4, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG4E8_V_MF4 }, // 145 |
| 32960 | { 0x4, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG4E8_V_MF2 }, // 146 |
| 32961 | { 0x4, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG4E16_V_M1 }, // 147 |
| 32962 | { 0x4, 0x0, 0x1, 0x4, 0x1, PseudoVSSSEG4E16_V_M2 }, // 148 |
| 32963 | { 0x4, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG4E16_V_MF4 }, // 149 |
| 32964 | { 0x4, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG4E16_V_MF2 }, // 150 |
| 32965 | { 0x4, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG4E32_V_M1 }, // 151 |
| 32966 | { 0x4, 0x0, 0x1, 0x5, 0x1, PseudoVSSSEG4E32_V_M2 }, // 152 |
| 32967 | { 0x4, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG4E32_V_MF2 }, // 153 |
| 32968 | { 0x4, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG4E64_V_M1 }, // 154 |
| 32969 | { 0x4, 0x0, 0x1, 0x6, 0x1, PseudoVSSSEG4E64_V_M2 }, // 155 |
| 32970 | { 0x4, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG4E8_V_M1_MASK }, // 156 |
| 32971 | { 0x4, 0x1, 0x0, 0x3, 0x1, PseudoVSSEG4E8_V_M2_MASK }, // 157 |
| 32972 | { 0x4, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG4E8_V_MF8_MASK }, // 158 |
| 32973 | { 0x4, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG4E8_V_MF4_MASK }, // 159 |
| 32974 | { 0x4, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG4E8_V_MF2_MASK }, // 160 |
| 32975 | { 0x4, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG4E16_V_M1_MASK }, // 161 |
| 32976 | { 0x4, 0x1, 0x0, 0x4, 0x1, PseudoVSSEG4E16_V_M2_MASK }, // 162 |
| 32977 | { 0x4, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG4E16_V_MF4_MASK }, // 163 |
| 32978 | { 0x4, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG4E16_V_MF2_MASK }, // 164 |
| 32979 | { 0x4, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG4E32_V_M1_MASK }, // 165 |
| 32980 | { 0x4, 0x1, 0x0, 0x5, 0x1, PseudoVSSEG4E32_V_M2_MASK }, // 166 |
| 32981 | { 0x4, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG4E32_V_MF2_MASK }, // 167 |
| 32982 | { 0x4, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG4E64_V_M1_MASK }, // 168 |
| 32983 | { 0x4, 0x1, 0x0, 0x6, 0x1, PseudoVSSEG4E64_V_M2_MASK }, // 169 |
| 32984 | { 0x4, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG4E8_V_M1_MASK }, // 170 |
| 32985 | { 0x4, 0x1, 0x1, 0x3, 0x1, PseudoVSSSEG4E8_V_M2_MASK }, // 171 |
| 32986 | { 0x4, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG4E8_V_MF8_MASK }, // 172 |
| 32987 | { 0x4, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG4E8_V_MF4_MASK }, // 173 |
| 32988 | { 0x4, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG4E8_V_MF2_MASK }, // 174 |
| 32989 | { 0x4, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG4E16_V_M1_MASK }, // 175 |
| 32990 | { 0x4, 0x1, 0x1, 0x4, 0x1, PseudoVSSSEG4E16_V_M2_MASK }, // 176 |
| 32991 | { 0x4, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG4E16_V_MF4_MASK }, // 177 |
| 32992 | { 0x4, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG4E16_V_MF2_MASK }, // 178 |
| 32993 | { 0x4, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG4E32_V_M1_MASK }, // 179 |
| 32994 | { 0x4, 0x1, 0x1, 0x5, 0x1, PseudoVSSSEG4E32_V_M2_MASK }, // 180 |
| 32995 | { 0x4, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG4E32_V_MF2_MASK }, // 181 |
| 32996 | { 0x4, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG4E64_V_M1_MASK }, // 182 |
| 32997 | { 0x4, 0x1, 0x1, 0x6, 0x1, PseudoVSSSEG4E64_V_M2_MASK }, // 183 |
| 32998 | { 0x5, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG5E8_V_M1 }, // 184 |
| 32999 | { 0x5, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG5E8_V_MF8 }, // 185 |
| 33000 | { 0x5, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG5E8_V_MF4 }, // 186 |
| 33001 | { 0x5, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG5E8_V_MF2 }, // 187 |
| 33002 | { 0x5, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG5E16_V_M1 }, // 188 |
| 33003 | { 0x5, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG5E16_V_MF4 }, // 189 |
| 33004 | { 0x5, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG5E16_V_MF2 }, // 190 |
| 33005 | { 0x5, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG5E32_V_M1 }, // 191 |
| 33006 | { 0x5, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG5E32_V_MF2 }, // 192 |
| 33007 | { 0x5, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG5E64_V_M1 }, // 193 |
| 33008 | { 0x5, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG5E8_V_M1 }, // 194 |
| 33009 | { 0x5, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG5E8_V_MF8 }, // 195 |
| 33010 | { 0x5, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG5E8_V_MF4 }, // 196 |
| 33011 | { 0x5, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG5E8_V_MF2 }, // 197 |
| 33012 | { 0x5, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG5E16_V_M1 }, // 198 |
| 33013 | { 0x5, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG5E16_V_MF4 }, // 199 |
| 33014 | { 0x5, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG5E16_V_MF2 }, // 200 |
| 33015 | { 0x5, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG5E32_V_M1 }, // 201 |
| 33016 | { 0x5, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG5E32_V_MF2 }, // 202 |
| 33017 | { 0x5, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG5E64_V_M1 }, // 203 |
| 33018 | { 0x5, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG5E8_V_M1_MASK }, // 204 |
| 33019 | { 0x5, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG5E8_V_MF8_MASK }, // 205 |
| 33020 | { 0x5, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG5E8_V_MF4_MASK }, // 206 |
| 33021 | { 0x5, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG5E8_V_MF2_MASK }, // 207 |
| 33022 | { 0x5, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG5E16_V_M1_MASK }, // 208 |
| 33023 | { 0x5, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG5E16_V_MF4_MASK }, // 209 |
| 33024 | { 0x5, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG5E16_V_MF2_MASK }, // 210 |
| 33025 | { 0x5, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG5E32_V_M1_MASK }, // 211 |
| 33026 | { 0x5, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG5E32_V_MF2_MASK }, // 212 |
| 33027 | { 0x5, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG5E64_V_M1_MASK }, // 213 |
| 33028 | { 0x5, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG5E8_V_M1_MASK }, // 214 |
| 33029 | { 0x5, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG5E8_V_MF8_MASK }, // 215 |
| 33030 | { 0x5, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG5E8_V_MF4_MASK }, // 216 |
| 33031 | { 0x5, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG5E8_V_MF2_MASK }, // 217 |
| 33032 | { 0x5, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG5E16_V_M1_MASK }, // 218 |
| 33033 | { 0x5, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG5E16_V_MF4_MASK }, // 219 |
| 33034 | { 0x5, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG5E16_V_MF2_MASK }, // 220 |
| 33035 | { 0x5, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG5E32_V_M1_MASK }, // 221 |
| 33036 | { 0x5, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG5E32_V_MF2_MASK }, // 222 |
| 33037 | { 0x5, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG5E64_V_M1_MASK }, // 223 |
| 33038 | { 0x6, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG6E8_V_M1 }, // 224 |
| 33039 | { 0x6, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG6E8_V_MF8 }, // 225 |
| 33040 | { 0x6, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG6E8_V_MF4 }, // 226 |
| 33041 | { 0x6, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG6E8_V_MF2 }, // 227 |
| 33042 | { 0x6, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG6E16_V_M1 }, // 228 |
| 33043 | { 0x6, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG6E16_V_MF4 }, // 229 |
| 33044 | { 0x6, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG6E16_V_MF2 }, // 230 |
| 33045 | { 0x6, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG6E32_V_M1 }, // 231 |
| 33046 | { 0x6, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG6E32_V_MF2 }, // 232 |
| 33047 | { 0x6, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG6E64_V_M1 }, // 233 |
| 33048 | { 0x6, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG6E8_V_M1 }, // 234 |
| 33049 | { 0x6, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG6E8_V_MF8 }, // 235 |
| 33050 | { 0x6, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG6E8_V_MF4 }, // 236 |
| 33051 | { 0x6, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG6E8_V_MF2 }, // 237 |
| 33052 | { 0x6, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG6E16_V_M1 }, // 238 |
| 33053 | { 0x6, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG6E16_V_MF4 }, // 239 |
| 33054 | { 0x6, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG6E16_V_MF2 }, // 240 |
| 33055 | { 0x6, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG6E32_V_M1 }, // 241 |
| 33056 | { 0x6, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG6E32_V_MF2 }, // 242 |
| 33057 | { 0x6, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG6E64_V_M1 }, // 243 |
| 33058 | { 0x6, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG6E8_V_M1_MASK }, // 244 |
| 33059 | { 0x6, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG6E8_V_MF8_MASK }, // 245 |
| 33060 | { 0x6, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG6E8_V_MF4_MASK }, // 246 |
| 33061 | { 0x6, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG6E8_V_MF2_MASK }, // 247 |
| 33062 | { 0x6, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG6E16_V_M1_MASK }, // 248 |
| 33063 | { 0x6, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG6E16_V_MF4_MASK }, // 249 |
| 33064 | { 0x6, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG6E16_V_MF2_MASK }, // 250 |
| 33065 | { 0x6, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG6E32_V_M1_MASK }, // 251 |
| 33066 | { 0x6, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG6E32_V_MF2_MASK }, // 252 |
| 33067 | { 0x6, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG6E64_V_M1_MASK }, // 253 |
| 33068 | { 0x6, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG6E8_V_M1_MASK }, // 254 |
| 33069 | { 0x6, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG6E8_V_MF8_MASK }, // 255 |
| 33070 | { 0x6, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG6E8_V_MF4_MASK }, // 256 |
| 33071 | { 0x6, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG6E8_V_MF2_MASK }, // 257 |
| 33072 | { 0x6, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG6E16_V_M1_MASK }, // 258 |
| 33073 | { 0x6, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG6E16_V_MF4_MASK }, // 259 |
| 33074 | { 0x6, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG6E16_V_MF2_MASK }, // 260 |
| 33075 | { 0x6, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG6E32_V_M1_MASK }, // 261 |
| 33076 | { 0x6, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG6E32_V_MF2_MASK }, // 262 |
| 33077 | { 0x6, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG6E64_V_M1_MASK }, // 263 |
| 33078 | { 0x7, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG7E8_V_M1 }, // 264 |
| 33079 | { 0x7, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG7E8_V_MF8 }, // 265 |
| 33080 | { 0x7, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG7E8_V_MF4 }, // 266 |
| 33081 | { 0x7, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG7E8_V_MF2 }, // 267 |
| 33082 | { 0x7, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG7E16_V_M1 }, // 268 |
| 33083 | { 0x7, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG7E16_V_MF4 }, // 269 |
| 33084 | { 0x7, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG7E16_V_MF2 }, // 270 |
| 33085 | { 0x7, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG7E32_V_M1 }, // 271 |
| 33086 | { 0x7, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG7E32_V_MF2 }, // 272 |
| 33087 | { 0x7, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG7E64_V_M1 }, // 273 |
| 33088 | { 0x7, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG7E8_V_M1 }, // 274 |
| 33089 | { 0x7, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG7E8_V_MF8 }, // 275 |
| 33090 | { 0x7, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG7E8_V_MF4 }, // 276 |
| 33091 | { 0x7, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG7E8_V_MF2 }, // 277 |
| 33092 | { 0x7, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG7E16_V_M1 }, // 278 |
| 33093 | { 0x7, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG7E16_V_MF4 }, // 279 |
| 33094 | { 0x7, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG7E16_V_MF2 }, // 280 |
| 33095 | { 0x7, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG7E32_V_M1 }, // 281 |
| 33096 | { 0x7, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG7E32_V_MF2 }, // 282 |
| 33097 | { 0x7, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG7E64_V_M1 }, // 283 |
| 33098 | { 0x7, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG7E8_V_M1_MASK }, // 284 |
| 33099 | { 0x7, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG7E8_V_MF8_MASK }, // 285 |
| 33100 | { 0x7, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG7E8_V_MF4_MASK }, // 286 |
| 33101 | { 0x7, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG7E8_V_MF2_MASK }, // 287 |
| 33102 | { 0x7, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG7E16_V_M1_MASK }, // 288 |
| 33103 | { 0x7, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG7E16_V_MF4_MASK }, // 289 |
| 33104 | { 0x7, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG7E16_V_MF2_MASK }, // 290 |
| 33105 | { 0x7, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG7E32_V_M1_MASK }, // 291 |
| 33106 | { 0x7, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG7E32_V_MF2_MASK }, // 292 |
| 33107 | { 0x7, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG7E64_V_M1_MASK }, // 293 |
| 33108 | { 0x7, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG7E8_V_M1_MASK }, // 294 |
| 33109 | { 0x7, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG7E8_V_MF8_MASK }, // 295 |
| 33110 | { 0x7, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG7E8_V_MF4_MASK }, // 296 |
| 33111 | { 0x7, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG7E8_V_MF2_MASK }, // 297 |
| 33112 | { 0x7, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG7E16_V_M1_MASK }, // 298 |
| 33113 | { 0x7, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG7E16_V_MF4_MASK }, // 299 |
| 33114 | { 0x7, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG7E16_V_MF2_MASK }, // 300 |
| 33115 | { 0x7, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG7E32_V_M1_MASK }, // 301 |
| 33116 | { 0x7, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG7E32_V_MF2_MASK }, // 302 |
| 33117 | { 0x7, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG7E64_V_M1_MASK }, // 303 |
| 33118 | { 0x8, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG8E8_V_M1 }, // 304 |
| 33119 | { 0x8, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG8E8_V_MF8 }, // 305 |
| 33120 | { 0x8, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG8E8_V_MF4 }, // 306 |
| 33121 | { 0x8, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG8E8_V_MF2 }, // 307 |
| 33122 | { 0x8, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG8E16_V_M1 }, // 308 |
| 33123 | { 0x8, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG8E16_V_MF4 }, // 309 |
| 33124 | { 0x8, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG8E16_V_MF2 }, // 310 |
| 33125 | { 0x8, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG8E32_V_M1 }, // 311 |
| 33126 | { 0x8, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG8E32_V_MF2 }, // 312 |
| 33127 | { 0x8, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG8E64_V_M1 }, // 313 |
| 33128 | { 0x8, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG8E8_V_M1 }, // 314 |
| 33129 | { 0x8, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG8E8_V_MF8 }, // 315 |
| 33130 | { 0x8, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG8E8_V_MF4 }, // 316 |
| 33131 | { 0x8, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG8E8_V_MF2 }, // 317 |
| 33132 | { 0x8, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG8E16_V_M1 }, // 318 |
| 33133 | { 0x8, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG8E16_V_MF4 }, // 319 |
| 33134 | { 0x8, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG8E16_V_MF2 }, // 320 |
| 33135 | { 0x8, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG8E32_V_M1 }, // 321 |
| 33136 | { 0x8, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG8E32_V_MF2 }, // 322 |
| 33137 | { 0x8, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG8E64_V_M1 }, // 323 |
| 33138 | { 0x8, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG8E8_V_M1_MASK }, // 324 |
| 33139 | { 0x8, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG8E8_V_MF8_MASK }, // 325 |
| 33140 | { 0x8, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG8E8_V_MF4_MASK }, // 326 |
| 33141 | { 0x8, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG8E8_V_MF2_MASK }, // 327 |
| 33142 | { 0x8, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG8E16_V_M1_MASK }, // 328 |
| 33143 | { 0x8, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG8E16_V_MF4_MASK }, // 329 |
| 33144 | { 0x8, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG8E16_V_MF2_MASK }, // 330 |
| 33145 | { 0x8, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG8E32_V_M1_MASK }, // 331 |
| 33146 | { 0x8, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG8E32_V_MF2_MASK }, // 332 |
| 33147 | { 0x8, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG8E64_V_M1_MASK }, // 333 |
| 33148 | { 0x8, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG8E8_V_M1_MASK }, // 334 |
| 33149 | { 0x8, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG8E8_V_MF8_MASK }, // 335 |
| 33150 | { 0x8, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG8E8_V_MF4_MASK }, // 336 |
| 33151 | { 0x8, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG8E8_V_MF2_MASK }, // 337 |
| 33152 | { 0x8, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG8E16_V_M1_MASK }, // 338 |
| 33153 | { 0x8, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG8E16_V_MF4_MASK }, // 339 |
| 33154 | { 0x8, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG8E16_V_MF2_MASK }, // 340 |
| 33155 | { 0x8, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG8E32_V_M1_MASK }, // 341 |
| 33156 | { 0x8, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG8E32_V_MF2_MASK }, // 342 |
| 33157 | { 0x8, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG8E64_V_M1_MASK }, // 343 |
| 33158 | }; |
| 33159 | |
| 33160 | const VSSEGPseudo *getVSSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Strided, uint8_t Log2SEW, uint8_t LMUL) { |
| 33161 | struct KeyType { |
| 33162 | uint8_t NF; |
| 33163 | uint8_t Masked; |
| 33164 | uint8_t Strided; |
| 33165 | uint8_t Log2SEW; |
| 33166 | uint8_t LMUL; |
| 33167 | }; |
| 33168 | KeyType Key = {NF, Masked, Strided, Log2SEW, LMUL}; |
| 33169 | struct Comp { |
| 33170 | bool operator()(const VSSEGPseudo &LHS, const KeyType &RHS) const { |
| 33171 | if (LHS.NF < RHS.NF) |
| 33172 | return true; |
| 33173 | if (LHS.NF > RHS.NF) |
| 33174 | return false; |
| 33175 | if (LHS.Masked < RHS.Masked) |
| 33176 | return true; |
| 33177 | if (LHS.Masked > RHS.Masked) |
| 33178 | return false; |
| 33179 | if (LHS.Strided < RHS.Strided) |
| 33180 | return true; |
| 33181 | if (LHS.Strided > RHS.Strided) |
| 33182 | return false; |
| 33183 | if (LHS.Log2SEW < RHS.Log2SEW) |
| 33184 | return true; |
| 33185 | if (LHS.Log2SEW > RHS.Log2SEW) |
| 33186 | return false; |
| 33187 | if (LHS.LMUL < RHS.LMUL) |
| 33188 | return true; |
| 33189 | if (LHS.LMUL > RHS.LMUL) |
| 33190 | return false; |
| 33191 | return false; |
| 33192 | } |
| 33193 | }; |
| 33194 | auto Table = ArrayRef(RISCVVSSEGTable); |
| 33195 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 33196 | if (Idx == Table.end() || |
| 33197 | Key.NF != Idx->NF || |
| 33198 | Key.Masked != Idx->Masked || |
| 33199 | Key.Strided != Idx->Strided || |
| 33200 | Key.Log2SEW != Idx->Log2SEW || |
| 33201 | Key.LMUL != Idx->LMUL) |
| 33202 | return nullptr; |
| 33203 | |
| 33204 | return &*Idx; |
| 33205 | } |
| 33206 | #endif |
| 33207 | |
| 33208 | #ifdef GET_RISCVVSXSEGTable_DECL |
| 33209 | const VSXSEGPseudo *getVSXSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL); |
| 33210 | #endif |
| 33211 | |
| 33212 | #ifdef GET_RISCVVSXSEGTable_IMPL |
| 33213 | constexpr VSXSEGPseudo RISCVVSXSEGTable[] = { |
| 33214 | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG2EI8_V_M1_M1 }, // 0 |
| 33215 | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG2EI8_V_MF8_M1 }, // 1 |
| 33216 | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG2EI8_V_MF4_M1 }, // 2 |
| 33217 | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG2EI8_V_MF2_M1 }, // 3 |
| 33218 | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG2EI8_V_M1_M2 }, // 4 |
| 33219 | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG2EI8_V_M2_M2 }, // 5 |
| 33220 | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG2EI8_V_MF4_M2 }, // 6 |
| 33221 | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG2EI8_V_MF2_M2 }, // 7 |
| 33222 | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x0, PseudoVSUXSEG2EI8_V_M1_M4 }, // 8 |
| 33223 | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x1, PseudoVSUXSEG2EI8_V_M2_M4 }, // 9 |
| 33224 | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x2, PseudoVSUXSEG2EI8_V_M4_M4 }, // 10 |
| 33225 | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x7, PseudoVSUXSEG2EI8_V_MF2_M4 }, // 11 |
| 33226 | { 0x2, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF8 }, // 12 |
| 33227 | { 0x2, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF4 }, // 13 |
| 33228 | { 0x2, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG2EI8_V_MF4_MF4 }, // 14 |
| 33229 | { 0x2, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF2 }, // 15 |
| 33230 | { 0x2, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG2EI8_V_MF4_MF2 }, // 16 |
| 33231 | { 0x2, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG2EI8_V_MF2_MF2 }, // 17 |
| 33232 | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG2EI16_V_M1_M1 }, // 18 |
| 33233 | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG2EI16_V_M2_M1 }, // 19 |
| 33234 | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG2EI16_V_MF4_M1 }, // 20 |
| 33235 | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG2EI16_V_MF2_M1 }, // 21 |
| 33236 | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG2EI16_V_M1_M2 }, // 22 |
| 33237 | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG2EI16_V_M2_M2 }, // 23 |
| 33238 | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG2EI16_V_M4_M2 }, // 24 |
| 33239 | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG2EI16_V_MF2_M2 }, // 25 |
| 33240 | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x0, PseudoVSUXSEG2EI16_V_M1_M4 }, // 26 |
| 33241 | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x1, PseudoVSUXSEG2EI16_V_M2_M4 }, // 27 |
| 33242 | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x2, PseudoVSUXSEG2EI16_V_M4_M4 }, // 28 |
| 33243 | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x3, PseudoVSUXSEG2EI16_V_M8_M4 }, // 29 |
| 33244 | { 0x2, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF8 }, // 30 |
| 33245 | { 0x2, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF4 }, // 31 |
| 33246 | { 0x2, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG2EI16_V_MF2_MF4 }, // 32 |
| 33247 | { 0x2, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG2EI16_V_M1_MF2 }, // 33 |
| 33248 | { 0x2, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF2 }, // 34 |
| 33249 | { 0x2, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG2EI16_V_MF2_MF2 }, // 35 |
| 33250 | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG2EI32_V_M1_M1 }, // 36 |
| 33251 | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG2EI32_V_M2_M1 }, // 37 |
| 33252 | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG2EI32_V_M4_M1 }, // 38 |
| 33253 | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG2EI32_V_MF2_M1 }, // 39 |
| 33254 | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG2EI32_V_M1_M2 }, // 40 |
| 33255 | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG2EI32_V_M2_M2 }, // 41 |
| 33256 | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG2EI32_V_M4_M2 }, // 42 |
| 33257 | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG2EI32_V_M8_M2 }, // 43 |
| 33258 | { 0x2, 0x0, 0x0, 0x5, 0x2, 0x1, PseudoVSUXSEG2EI32_V_M2_M4 }, // 44 |
| 33259 | { 0x2, 0x0, 0x0, 0x5, 0x2, 0x2, PseudoVSUXSEG2EI32_V_M4_M4 }, // 45 |
| 33260 | { 0x2, 0x0, 0x0, 0x5, 0x2, 0x3, PseudoVSUXSEG2EI32_V_M8_M4 }, // 46 |
| 33261 | { 0x2, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF8 }, // 47 |
| 33262 | { 0x2, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG2EI32_V_M1_MF4 }, // 48 |
| 33263 | { 0x2, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF4 }, // 49 |
| 33264 | { 0x2, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG2EI32_V_M1_MF2 }, // 50 |
| 33265 | { 0x2, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG2EI32_V_M2_MF2 }, // 51 |
| 33266 | { 0x2, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF2 }, // 52 |
| 33267 | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG2EI64_V_M1_M1 }, // 53 |
| 33268 | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG2EI64_V_M2_M1 }, // 54 |
| 33269 | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG2EI64_V_M4_M1 }, // 55 |
| 33270 | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG2EI64_V_M8_M1 }, // 56 |
| 33271 | { 0x2, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG2EI64_V_M2_M2 }, // 57 |
| 33272 | { 0x2, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG2EI64_V_M4_M2 }, // 58 |
| 33273 | { 0x2, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG2EI64_V_M8_M2 }, // 59 |
| 33274 | { 0x2, 0x0, 0x0, 0x6, 0x2, 0x2, PseudoVSUXSEG2EI64_V_M4_M4 }, // 60 |
| 33275 | { 0x2, 0x0, 0x0, 0x6, 0x2, 0x3, PseudoVSUXSEG2EI64_V_M8_M4 }, // 61 |
| 33276 | { 0x2, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG2EI64_V_M1_MF8 }, // 62 |
| 33277 | { 0x2, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG2EI64_V_M1_MF4 }, // 63 |
| 33278 | { 0x2, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG2EI64_V_M2_MF4 }, // 64 |
| 33279 | { 0x2, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG2EI64_V_M1_MF2 }, // 65 |
| 33280 | { 0x2, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG2EI64_V_M2_MF2 }, // 66 |
| 33281 | { 0x2, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG2EI64_V_M4_MF2 }, // 67 |
| 33282 | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG2EI8_V_M1_M1 }, // 68 |
| 33283 | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG2EI8_V_MF8_M1 }, // 69 |
| 33284 | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG2EI8_V_MF4_M1 }, // 70 |
| 33285 | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG2EI8_V_MF2_M1 }, // 71 |
| 33286 | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG2EI8_V_M1_M2 }, // 72 |
| 33287 | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG2EI8_V_M2_M2 }, // 73 |
| 33288 | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG2EI8_V_MF4_M2 }, // 74 |
| 33289 | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG2EI8_V_MF2_M2 }, // 75 |
| 33290 | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x0, PseudoVSOXSEG2EI8_V_M1_M4 }, // 76 |
| 33291 | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x1, PseudoVSOXSEG2EI8_V_M2_M4 }, // 77 |
| 33292 | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x2, PseudoVSOXSEG2EI8_V_M4_M4 }, // 78 |
| 33293 | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x7, PseudoVSOXSEG2EI8_V_MF2_M4 }, // 79 |
| 33294 | { 0x2, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF8 }, // 80 |
| 33295 | { 0x2, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF4 }, // 81 |
| 33296 | { 0x2, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG2EI8_V_MF4_MF4 }, // 82 |
| 33297 | { 0x2, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF2 }, // 83 |
| 33298 | { 0x2, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG2EI8_V_MF4_MF2 }, // 84 |
| 33299 | { 0x2, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG2EI8_V_MF2_MF2 }, // 85 |
| 33300 | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG2EI16_V_M1_M1 }, // 86 |
| 33301 | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG2EI16_V_M2_M1 }, // 87 |
| 33302 | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG2EI16_V_MF4_M1 }, // 88 |
| 33303 | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG2EI16_V_MF2_M1 }, // 89 |
| 33304 | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG2EI16_V_M1_M2 }, // 90 |
| 33305 | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG2EI16_V_M2_M2 }, // 91 |
| 33306 | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG2EI16_V_M4_M2 }, // 92 |
| 33307 | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG2EI16_V_MF2_M2 }, // 93 |
| 33308 | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x0, PseudoVSOXSEG2EI16_V_M1_M4 }, // 94 |
| 33309 | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x1, PseudoVSOXSEG2EI16_V_M2_M4 }, // 95 |
| 33310 | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x2, PseudoVSOXSEG2EI16_V_M4_M4 }, // 96 |
| 33311 | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x3, PseudoVSOXSEG2EI16_V_M8_M4 }, // 97 |
| 33312 | { 0x2, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF8 }, // 98 |
| 33313 | { 0x2, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF4 }, // 99 |
| 33314 | { 0x2, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG2EI16_V_MF2_MF4 }, // 100 |
| 33315 | { 0x2, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG2EI16_V_M1_MF2 }, // 101 |
| 33316 | { 0x2, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF2 }, // 102 |
| 33317 | { 0x2, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG2EI16_V_MF2_MF2 }, // 103 |
| 33318 | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG2EI32_V_M1_M1 }, // 104 |
| 33319 | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG2EI32_V_M2_M1 }, // 105 |
| 33320 | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG2EI32_V_M4_M1 }, // 106 |
| 33321 | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG2EI32_V_MF2_M1 }, // 107 |
| 33322 | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG2EI32_V_M1_M2 }, // 108 |
| 33323 | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG2EI32_V_M2_M2 }, // 109 |
| 33324 | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG2EI32_V_M4_M2 }, // 110 |
| 33325 | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG2EI32_V_M8_M2 }, // 111 |
| 33326 | { 0x2, 0x0, 0x1, 0x5, 0x2, 0x1, PseudoVSOXSEG2EI32_V_M2_M4 }, // 112 |
| 33327 | { 0x2, 0x0, 0x1, 0x5, 0x2, 0x2, PseudoVSOXSEG2EI32_V_M4_M4 }, // 113 |
| 33328 | { 0x2, 0x0, 0x1, 0x5, 0x2, 0x3, PseudoVSOXSEG2EI32_V_M8_M4 }, // 114 |
| 33329 | { 0x2, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF8 }, // 115 |
| 33330 | { 0x2, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG2EI32_V_M1_MF4 }, // 116 |
| 33331 | { 0x2, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF4 }, // 117 |
| 33332 | { 0x2, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG2EI32_V_M1_MF2 }, // 118 |
| 33333 | { 0x2, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG2EI32_V_M2_MF2 }, // 119 |
| 33334 | { 0x2, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF2 }, // 120 |
| 33335 | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG2EI64_V_M1_M1 }, // 121 |
| 33336 | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG2EI64_V_M2_M1 }, // 122 |
| 33337 | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG2EI64_V_M4_M1 }, // 123 |
| 33338 | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG2EI64_V_M8_M1 }, // 124 |
| 33339 | { 0x2, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG2EI64_V_M2_M2 }, // 125 |
| 33340 | { 0x2, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG2EI64_V_M4_M2 }, // 126 |
| 33341 | { 0x2, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG2EI64_V_M8_M2 }, // 127 |
| 33342 | { 0x2, 0x0, 0x1, 0x6, 0x2, 0x2, PseudoVSOXSEG2EI64_V_M4_M4 }, // 128 |
| 33343 | { 0x2, 0x0, 0x1, 0x6, 0x2, 0x3, PseudoVSOXSEG2EI64_V_M8_M4 }, // 129 |
| 33344 | { 0x2, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG2EI64_V_M1_MF8 }, // 130 |
| 33345 | { 0x2, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG2EI64_V_M1_MF4 }, // 131 |
| 33346 | { 0x2, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG2EI64_V_M2_MF4 }, // 132 |
| 33347 | { 0x2, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG2EI64_V_M1_MF2 }, // 133 |
| 33348 | { 0x2, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG2EI64_V_M2_MF2 }, // 134 |
| 33349 | { 0x2, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG2EI64_V_M4_MF2 }, // 135 |
| 33350 | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG2EI8_V_M1_M1_MASK }, // 136 |
| 33351 | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG2EI8_V_MF8_M1_MASK }, // 137 |
| 33352 | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG2EI8_V_MF4_M1_MASK }, // 138 |
| 33353 | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG2EI8_V_MF2_M1_MASK }, // 139 |
| 33354 | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG2EI8_V_M1_M2_MASK }, // 140 |
| 33355 | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG2EI8_V_M2_M2_MASK }, // 141 |
| 33356 | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG2EI8_V_MF4_M2_MASK }, // 142 |
| 33357 | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG2EI8_V_MF2_M2_MASK }, // 143 |
| 33358 | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x0, PseudoVSUXSEG2EI8_V_M1_M4_MASK }, // 144 |
| 33359 | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x1, PseudoVSUXSEG2EI8_V_M2_M4_MASK }, // 145 |
| 33360 | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x2, PseudoVSUXSEG2EI8_V_M4_M4_MASK }, // 146 |
| 33361 | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x7, PseudoVSUXSEG2EI8_V_MF2_M4_MASK }, // 147 |
| 33362 | { 0x2, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF8_MASK }, // 148 |
| 33363 | { 0x2, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF4_MASK }, // 149 |
| 33364 | { 0x2, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG2EI8_V_MF4_MF4_MASK }, // 150 |
| 33365 | { 0x2, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF2_MASK }, // 151 |
| 33366 | { 0x2, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG2EI8_V_MF4_MF2_MASK }, // 152 |
| 33367 | { 0x2, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG2EI8_V_MF2_MF2_MASK }, // 153 |
| 33368 | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG2EI16_V_M1_M1_MASK }, // 154 |
| 33369 | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG2EI16_V_M2_M1_MASK }, // 155 |
| 33370 | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG2EI16_V_MF4_M1_MASK }, // 156 |
| 33371 | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG2EI16_V_MF2_M1_MASK }, // 157 |
| 33372 | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG2EI16_V_M1_M2_MASK }, // 158 |
| 33373 | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG2EI16_V_M2_M2_MASK }, // 159 |
| 33374 | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG2EI16_V_M4_M2_MASK }, // 160 |
| 33375 | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG2EI16_V_MF2_M2_MASK }, // 161 |
| 33376 | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x0, PseudoVSUXSEG2EI16_V_M1_M4_MASK }, // 162 |
| 33377 | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x1, PseudoVSUXSEG2EI16_V_M2_M4_MASK }, // 163 |
| 33378 | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x2, PseudoVSUXSEG2EI16_V_M4_M4_MASK }, // 164 |
| 33379 | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x3, PseudoVSUXSEG2EI16_V_M8_M4_MASK }, // 165 |
| 33380 | { 0x2, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF8_MASK }, // 166 |
| 33381 | { 0x2, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF4_MASK }, // 167 |
| 33382 | { 0x2, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG2EI16_V_MF2_MF4_MASK }, // 168 |
| 33383 | { 0x2, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG2EI16_V_M1_MF2_MASK }, // 169 |
| 33384 | { 0x2, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF2_MASK }, // 170 |
| 33385 | { 0x2, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG2EI16_V_MF2_MF2_MASK }, // 171 |
| 33386 | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG2EI32_V_M1_M1_MASK }, // 172 |
| 33387 | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG2EI32_V_M2_M1_MASK }, // 173 |
| 33388 | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG2EI32_V_M4_M1_MASK }, // 174 |
| 33389 | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG2EI32_V_MF2_M1_MASK }, // 175 |
| 33390 | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG2EI32_V_M1_M2_MASK }, // 176 |
| 33391 | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG2EI32_V_M2_M2_MASK }, // 177 |
| 33392 | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG2EI32_V_M4_M2_MASK }, // 178 |
| 33393 | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG2EI32_V_M8_M2_MASK }, // 179 |
| 33394 | { 0x2, 0x1, 0x0, 0x5, 0x2, 0x1, PseudoVSUXSEG2EI32_V_M2_M4_MASK }, // 180 |
| 33395 | { 0x2, 0x1, 0x0, 0x5, 0x2, 0x2, PseudoVSUXSEG2EI32_V_M4_M4_MASK }, // 181 |
| 33396 | { 0x2, 0x1, 0x0, 0x5, 0x2, 0x3, PseudoVSUXSEG2EI32_V_M8_M4_MASK }, // 182 |
| 33397 | { 0x2, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF8_MASK }, // 183 |
| 33398 | { 0x2, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG2EI32_V_M1_MF4_MASK }, // 184 |
| 33399 | { 0x2, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF4_MASK }, // 185 |
| 33400 | { 0x2, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG2EI32_V_M1_MF2_MASK }, // 186 |
| 33401 | { 0x2, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG2EI32_V_M2_MF2_MASK }, // 187 |
| 33402 | { 0x2, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF2_MASK }, // 188 |
| 33403 | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG2EI64_V_M1_M1_MASK }, // 189 |
| 33404 | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG2EI64_V_M2_M1_MASK }, // 190 |
| 33405 | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG2EI64_V_M4_M1_MASK }, // 191 |
| 33406 | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG2EI64_V_M8_M1_MASK }, // 192 |
| 33407 | { 0x2, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG2EI64_V_M2_M2_MASK }, // 193 |
| 33408 | { 0x2, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG2EI64_V_M4_M2_MASK }, // 194 |
| 33409 | { 0x2, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG2EI64_V_M8_M2_MASK }, // 195 |
| 33410 | { 0x2, 0x1, 0x0, 0x6, 0x2, 0x2, PseudoVSUXSEG2EI64_V_M4_M4_MASK }, // 196 |
| 33411 | { 0x2, 0x1, 0x0, 0x6, 0x2, 0x3, PseudoVSUXSEG2EI64_V_M8_M4_MASK }, // 197 |
| 33412 | { 0x2, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG2EI64_V_M1_MF8_MASK }, // 198 |
| 33413 | { 0x2, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG2EI64_V_M1_MF4_MASK }, // 199 |
| 33414 | { 0x2, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG2EI64_V_M2_MF4_MASK }, // 200 |
| 33415 | { 0x2, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG2EI64_V_M1_MF2_MASK }, // 201 |
| 33416 | { 0x2, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG2EI64_V_M2_MF2_MASK }, // 202 |
| 33417 | { 0x2, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG2EI64_V_M4_MF2_MASK }, // 203 |
| 33418 | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG2EI8_V_M1_M1_MASK }, // 204 |
| 33419 | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG2EI8_V_MF8_M1_MASK }, // 205 |
| 33420 | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG2EI8_V_MF4_M1_MASK }, // 206 |
| 33421 | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG2EI8_V_MF2_M1_MASK }, // 207 |
| 33422 | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG2EI8_V_M1_M2_MASK }, // 208 |
| 33423 | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG2EI8_V_M2_M2_MASK }, // 209 |
| 33424 | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG2EI8_V_MF4_M2_MASK }, // 210 |
| 33425 | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG2EI8_V_MF2_M2_MASK }, // 211 |
| 33426 | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x0, PseudoVSOXSEG2EI8_V_M1_M4_MASK }, // 212 |
| 33427 | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x1, PseudoVSOXSEG2EI8_V_M2_M4_MASK }, // 213 |
| 33428 | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x2, PseudoVSOXSEG2EI8_V_M4_M4_MASK }, // 214 |
| 33429 | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x7, PseudoVSOXSEG2EI8_V_MF2_M4_MASK }, // 215 |
| 33430 | { 0x2, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF8_MASK }, // 216 |
| 33431 | { 0x2, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF4_MASK }, // 217 |
| 33432 | { 0x2, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG2EI8_V_MF4_MF4_MASK }, // 218 |
| 33433 | { 0x2, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF2_MASK }, // 219 |
| 33434 | { 0x2, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG2EI8_V_MF4_MF2_MASK }, // 220 |
| 33435 | { 0x2, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG2EI8_V_MF2_MF2_MASK }, // 221 |
| 33436 | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG2EI16_V_M1_M1_MASK }, // 222 |
| 33437 | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG2EI16_V_M2_M1_MASK }, // 223 |
| 33438 | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG2EI16_V_MF4_M1_MASK }, // 224 |
| 33439 | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG2EI16_V_MF2_M1_MASK }, // 225 |
| 33440 | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG2EI16_V_M1_M2_MASK }, // 226 |
| 33441 | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG2EI16_V_M2_M2_MASK }, // 227 |
| 33442 | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG2EI16_V_M4_M2_MASK }, // 228 |
| 33443 | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG2EI16_V_MF2_M2_MASK }, // 229 |
| 33444 | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x0, PseudoVSOXSEG2EI16_V_M1_M4_MASK }, // 230 |
| 33445 | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x1, PseudoVSOXSEG2EI16_V_M2_M4_MASK }, // 231 |
| 33446 | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x2, PseudoVSOXSEG2EI16_V_M4_M4_MASK }, // 232 |
| 33447 | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x3, PseudoVSOXSEG2EI16_V_M8_M4_MASK }, // 233 |
| 33448 | { 0x2, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF8_MASK }, // 234 |
| 33449 | { 0x2, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF4_MASK }, // 235 |
| 33450 | { 0x2, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG2EI16_V_MF2_MF4_MASK }, // 236 |
| 33451 | { 0x2, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG2EI16_V_M1_MF2_MASK }, // 237 |
| 33452 | { 0x2, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF2_MASK }, // 238 |
| 33453 | { 0x2, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG2EI16_V_MF2_MF2_MASK }, // 239 |
| 33454 | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG2EI32_V_M1_M1_MASK }, // 240 |
| 33455 | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG2EI32_V_M2_M1_MASK }, // 241 |
| 33456 | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG2EI32_V_M4_M1_MASK }, // 242 |
| 33457 | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG2EI32_V_MF2_M1_MASK }, // 243 |
| 33458 | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG2EI32_V_M1_M2_MASK }, // 244 |
| 33459 | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG2EI32_V_M2_M2_MASK }, // 245 |
| 33460 | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG2EI32_V_M4_M2_MASK }, // 246 |
| 33461 | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG2EI32_V_M8_M2_MASK }, // 247 |
| 33462 | { 0x2, 0x1, 0x1, 0x5, 0x2, 0x1, PseudoVSOXSEG2EI32_V_M2_M4_MASK }, // 248 |
| 33463 | { 0x2, 0x1, 0x1, 0x5, 0x2, 0x2, PseudoVSOXSEG2EI32_V_M4_M4_MASK }, // 249 |
| 33464 | { 0x2, 0x1, 0x1, 0x5, 0x2, 0x3, PseudoVSOXSEG2EI32_V_M8_M4_MASK }, // 250 |
| 33465 | { 0x2, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF8_MASK }, // 251 |
| 33466 | { 0x2, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG2EI32_V_M1_MF4_MASK }, // 252 |
| 33467 | { 0x2, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF4_MASK }, // 253 |
| 33468 | { 0x2, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG2EI32_V_M1_MF2_MASK }, // 254 |
| 33469 | { 0x2, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG2EI32_V_M2_MF2_MASK }, // 255 |
| 33470 | { 0x2, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF2_MASK }, // 256 |
| 33471 | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG2EI64_V_M1_M1_MASK }, // 257 |
| 33472 | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG2EI64_V_M2_M1_MASK }, // 258 |
| 33473 | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG2EI64_V_M4_M1_MASK }, // 259 |
| 33474 | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG2EI64_V_M8_M1_MASK }, // 260 |
| 33475 | { 0x2, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG2EI64_V_M2_M2_MASK }, // 261 |
| 33476 | { 0x2, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG2EI64_V_M4_M2_MASK }, // 262 |
| 33477 | { 0x2, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG2EI64_V_M8_M2_MASK }, // 263 |
| 33478 | { 0x2, 0x1, 0x1, 0x6, 0x2, 0x2, PseudoVSOXSEG2EI64_V_M4_M4_MASK }, // 264 |
| 33479 | { 0x2, 0x1, 0x1, 0x6, 0x2, 0x3, PseudoVSOXSEG2EI64_V_M8_M4_MASK }, // 265 |
| 33480 | { 0x2, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG2EI64_V_M1_MF8_MASK }, // 266 |
| 33481 | { 0x2, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG2EI64_V_M1_MF4_MASK }, // 267 |
| 33482 | { 0x2, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG2EI64_V_M2_MF4_MASK }, // 268 |
| 33483 | { 0x2, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG2EI64_V_M1_MF2_MASK }, // 269 |
| 33484 | { 0x2, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG2EI64_V_M2_MF2_MASK }, // 270 |
| 33485 | { 0x2, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG2EI64_V_M4_MF2_MASK }, // 271 |
| 33486 | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG3EI8_V_M1_M1 }, // 272 |
| 33487 | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG3EI8_V_MF8_M1 }, // 273 |
| 33488 | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG3EI8_V_MF4_M1 }, // 274 |
| 33489 | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG3EI8_V_MF2_M1 }, // 275 |
| 33490 | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG3EI8_V_M1_M2 }, // 276 |
| 33491 | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG3EI8_V_M2_M2 }, // 277 |
| 33492 | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG3EI8_V_MF4_M2 }, // 278 |
| 33493 | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG3EI8_V_MF2_M2 }, // 279 |
| 33494 | { 0x3, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF8 }, // 280 |
| 33495 | { 0x3, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF4 }, // 281 |
| 33496 | { 0x3, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG3EI8_V_MF4_MF4 }, // 282 |
| 33497 | { 0x3, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF2 }, // 283 |
| 33498 | { 0x3, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG3EI8_V_MF4_MF2 }, // 284 |
| 33499 | { 0x3, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG3EI8_V_MF2_MF2 }, // 285 |
| 33500 | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG3EI16_V_M1_M1 }, // 286 |
| 33501 | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG3EI16_V_M2_M1 }, // 287 |
| 33502 | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG3EI16_V_MF4_M1 }, // 288 |
| 33503 | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG3EI16_V_MF2_M1 }, // 289 |
| 33504 | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG3EI16_V_M1_M2 }, // 290 |
| 33505 | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG3EI16_V_M2_M2 }, // 291 |
| 33506 | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG3EI16_V_M4_M2 }, // 292 |
| 33507 | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG3EI16_V_MF2_M2 }, // 293 |
| 33508 | { 0x3, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF8 }, // 294 |
| 33509 | { 0x3, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF4 }, // 295 |
| 33510 | { 0x3, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG3EI16_V_MF2_MF4 }, // 296 |
| 33511 | { 0x3, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG3EI16_V_M1_MF2 }, // 297 |
| 33512 | { 0x3, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF2 }, // 298 |
| 33513 | { 0x3, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG3EI16_V_MF2_MF2 }, // 299 |
| 33514 | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG3EI32_V_M1_M1 }, // 300 |
| 33515 | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG3EI32_V_M2_M1 }, // 301 |
| 33516 | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG3EI32_V_M4_M1 }, // 302 |
| 33517 | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG3EI32_V_MF2_M1 }, // 303 |
| 33518 | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG3EI32_V_M1_M2 }, // 304 |
| 33519 | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG3EI32_V_M2_M2 }, // 305 |
| 33520 | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG3EI32_V_M4_M2 }, // 306 |
| 33521 | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG3EI32_V_M8_M2 }, // 307 |
| 33522 | { 0x3, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF8 }, // 308 |
| 33523 | { 0x3, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG3EI32_V_M1_MF4 }, // 309 |
| 33524 | { 0x3, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF4 }, // 310 |
| 33525 | { 0x3, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG3EI32_V_M1_MF2 }, // 311 |
| 33526 | { 0x3, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG3EI32_V_M2_MF2 }, // 312 |
| 33527 | { 0x3, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF2 }, // 313 |
| 33528 | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG3EI64_V_M1_M1 }, // 314 |
| 33529 | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG3EI64_V_M2_M1 }, // 315 |
| 33530 | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG3EI64_V_M4_M1 }, // 316 |
| 33531 | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG3EI64_V_M8_M1 }, // 317 |
| 33532 | { 0x3, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG3EI64_V_M2_M2 }, // 318 |
| 33533 | { 0x3, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG3EI64_V_M4_M2 }, // 319 |
| 33534 | { 0x3, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG3EI64_V_M8_M2 }, // 320 |
| 33535 | { 0x3, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG3EI64_V_M1_MF8 }, // 321 |
| 33536 | { 0x3, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG3EI64_V_M1_MF4 }, // 322 |
| 33537 | { 0x3, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG3EI64_V_M2_MF4 }, // 323 |
| 33538 | { 0x3, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG3EI64_V_M1_MF2 }, // 324 |
| 33539 | { 0x3, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG3EI64_V_M2_MF2 }, // 325 |
| 33540 | { 0x3, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG3EI64_V_M4_MF2 }, // 326 |
| 33541 | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG3EI8_V_M1_M1 }, // 327 |
| 33542 | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG3EI8_V_MF8_M1 }, // 328 |
| 33543 | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG3EI8_V_MF4_M1 }, // 329 |
| 33544 | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG3EI8_V_MF2_M1 }, // 330 |
| 33545 | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG3EI8_V_M1_M2 }, // 331 |
| 33546 | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG3EI8_V_M2_M2 }, // 332 |
| 33547 | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG3EI8_V_MF4_M2 }, // 333 |
| 33548 | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG3EI8_V_MF2_M2 }, // 334 |
| 33549 | { 0x3, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF8 }, // 335 |
| 33550 | { 0x3, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF4 }, // 336 |
| 33551 | { 0x3, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG3EI8_V_MF4_MF4 }, // 337 |
| 33552 | { 0x3, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF2 }, // 338 |
| 33553 | { 0x3, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG3EI8_V_MF4_MF2 }, // 339 |
| 33554 | { 0x3, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG3EI8_V_MF2_MF2 }, // 340 |
| 33555 | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG3EI16_V_M1_M1 }, // 341 |
| 33556 | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG3EI16_V_M2_M1 }, // 342 |
| 33557 | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG3EI16_V_MF4_M1 }, // 343 |
| 33558 | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG3EI16_V_MF2_M1 }, // 344 |
| 33559 | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG3EI16_V_M1_M2 }, // 345 |
| 33560 | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG3EI16_V_M2_M2 }, // 346 |
| 33561 | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG3EI16_V_M4_M2 }, // 347 |
| 33562 | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG3EI16_V_MF2_M2 }, // 348 |
| 33563 | { 0x3, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF8 }, // 349 |
| 33564 | { 0x3, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF4 }, // 350 |
| 33565 | { 0x3, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG3EI16_V_MF2_MF4 }, // 351 |
| 33566 | { 0x3, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG3EI16_V_M1_MF2 }, // 352 |
| 33567 | { 0x3, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF2 }, // 353 |
| 33568 | { 0x3, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG3EI16_V_MF2_MF2 }, // 354 |
| 33569 | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG3EI32_V_M1_M1 }, // 355 |
| 33570 | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG3EI32_V_M2_M1 }, // 356 |
| 33571 | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG3EI32_V_M4_M1 }, // 357 |
| 33572 | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG3EI32_V_MF2_M1 }, // 358 |
| 33573 | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG3EI32_V_M1_M2 }, // 359 |
| 33574 | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG3EI32_V_M2_M2 }, // 360 |
| 33575 | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG3EI32_V_M4_M2 }, // 361 |
| 33576 | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG3EI32_V_M8_M2 }, // 362 |
| 33577 | { 0x3, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF8 }, // 363 |
| 33578 | { 0x3, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG3EI32_V_M1_MF4 }, // 364 |
| 33579 | { 0x3, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF4 }, // 365 |
| 33580 | { 0x3, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG3EI32_V_M1_MF2 }, // 366 |
| 33581 | { 0x3, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG3EI32_V_M2_MF2 }, // 367 |
| 33582 | { 0x3, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF2 }, // 368 |
| 33583 | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG3EI64_V_M1_M1 }, // 369 |
| 33584 | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG3EI64_V_M2_M1 }, // 370 |
| 33585 | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG3EI64_V_M4_M1 }, // 371 |
| 33586 | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG3EI64_V_M8_M1 }, // 372 |
| 33587 | { 0x3, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG3EI64_V_M2_M2 }, // 373 |
| 33588 | { 0x3, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG3EI64_V_M4_M2 }, // 374 |
| 33589 | { 0x3, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG3EI64_V_M8_M2 }, // 375 |
| 33590 | { 0x3, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG3EI64_V_M1_MF8 }, // 376 |
| 33591 | { 0x3, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG3EI64_V_M1_MF4 }, // 377 |
| 33592 | { 0x3, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG3EI64_V_M2_MF4 }, // 378 |
| 33593 | { 0x3, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG3EI64_V_M1_MF2 }, // 379 |
| 33594 | { 0x3, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG3EI64_V_M2_MF2 }, // 380 |
| 33595 | { 0x3, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG3EI64_V_M4_MF2 }, // 381 |
| 33596 | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG3EI8_V_M1_M1_MASK }, // 382 |
| 33597 | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG3EI8_V_MF8_M1_MASK }, // 383 |
| 33598 | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG3EI8_V_MF4_M1_MASK }, // 384 |
| 33599 | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG3EI8_V_MF2_M1_MASK }, // 385 |
| 33600 | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG3EI8_V_M1_M2_MASK }, // 386 |
| 33601 | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG3EI8_V_M2_M2_MASK }, // 387 |
| 33602 | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG3EI8_V_MF4_M2_MASK }, // 388 |
| 33603 | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG3EI8_V_MF2_M2_MASK }, // 389 |
| 33604 | { 0x3, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF8_MASK }, // 390 |
| 33605 | { 0x3, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF4_MASK }, // 391 |
| 33606 | { 0x3, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG3EI8_V_MF4_MF4_MASK }, // 392 |
| 33607 | { 0x3, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF2_MASK }, // 393 |
| 33608 | { 0x3, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG3EI8_V_MF4_MF2_MASK }, // 394 |
| 33609 | { 0x3, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG3EI8_V_MF2_MF2_MASK }, // 395 |
| 33610 | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG3EI16_V_M1_M1_MASK }, // 396 |
| 33611 | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG3EI16_V_M2_M1_MASK }, // 397 |
| 33612 | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG3EI16_V_MF4_M1_MASK }, // 398 |
| 33613 | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG3EI16_V_MF2_M1_MASK }, // 399 |
| 33614 | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG3EI16_V_M1_M2_MASK }, // 400 |
| 33615 | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG3EI16_V_M2_M2_MASK }, // 401 |
| 33616 | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG3EI16_V_M4_M2_MASK }, // 402 |
| 33617 | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG3EI16_V_MF2_M2_MASK }, // 403 |
| 33618 | { 0x3, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF8_MASK }, // 404 |
| 33619 | { 0x3, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF4_MASK }, // 405 |
| 33620 | { 0x3, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG3EI16_V_MF2_MF4_MASK }, // 406 |
| 33621 | { 0x3, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG3EI16_V_M1_MF2_MASK }, // 407 |
| 33622 | { 0x3, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF2_MASK }, // 408 |
| 33623 | { 0x3, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG3EI16_V_MF2_MF2_MASK }, // 409 |
| 33624 | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG3EI32_V_M1_M1_MASK }, // 410 |
| 33625 | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG3EI32_V_M2_M1_MASK }, // 411 |
| 33626 | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG3EI32_V_M4_M1_MASK }, // 412 |
| 33627 | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG3EI32_V_MF2_M1_MASK }, // 413 |
| 33628 | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG3EI32_V_M1_M2_MASK }, // 414 |
| 33629 | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG3EI32_V_M2_M2_MASK }, // 415 |
| 33630 | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG3EI32_V_M4_M2_MASK }, // 416 |
| 33631 | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG3EI32_V_M8_M2_MASK }, // 417 |
| 33632 | { 0x3, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF8_MASK }, // 418 |
| 33633 | { 0x3, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG3EI32_V_M1_MF4_MASK }, // 419 |
| 33634 | { 0x3, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF4_MASK }, // 420 |
| 33635 | { 0x3, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG3EI32_V_M1_MF2_MASK }, // 421 |
| 33636 | { 0x3, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG3EI32_V_M2_MF2_MASK }, // 422 |
| 33637 | { 0x3, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF2_MASK }, // 423 |
| 33638 | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG3EI64_V_M1_M1_MASK }, // 424 |
| 33639 | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG3EI64_V_M2_M1_MASK }, // 425 |
| 33640 | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG3EI64_V_M4_M1_MASK }, // 426 |
| 33641 | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG3EI64_V_M8_M1_MASK }, // 427 |
| 33642 | { 0x3, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG3EI64_V_M2_M2_MASK }, // 428 |
| 33643 | { 0x3, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG3EI64_V_M4_M2_MASK }, // 429 |
| 33644 | { 0x3, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG3EI64_V_M8_M2_MASK }, // 430 |
| 33645 | { 0x3, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG3EI64_V_M1_MF8_MASK }, // 431 |
| 33646 | { 0x3, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG3EI64_V_M1_MF4_MASK }, // 432 |
| 33647 | { 0x3, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG3EI64_V_M2_MF4_MASK }, // 433 |
| 33648 | { 0x3, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG3EI64_V_M1_MF2_MASK }, // 434 |
| 33649 | { 0x3, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG3EI64_V_M2_MF2_MASK }, // 435 |
| 33650 | { 0x3, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG3EI64_V_M4_MF2_MASK }, // 436 |
| 33651 | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG3EI8_V_M1_M1_MASK }, // 437 |
| 33652 | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG3EI8_V_MF8_M1_MASK }, // 438 |
| 33653 | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG3EI8_V_MF4_M1_MASK }, // 439 |
| 33654 | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG3EI8_V_MF2_M1_MASK }, // 440 |
| 33655 | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG3EI8_V_M1_M2_MASK }, // 441 |
| 33656 | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG3EI8_V_M2_M2_MASK }, // 442 |
| 33657 | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG3EI8_V_MF4_M2_MASK }, // 443 |
| 33658 | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG3EI8_V_MF2_M2_MASK }, // 444 |
| 33659 | { 0x3, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF8_MASK }, // 445 |
| 33660 | { 0x3, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF4_MASK }, // 446 |
| 33661 | { 0x3, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG3EI8_V_MF4_MF4_MASK }, // 447 |
| 33662 | { 0x3, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF2_MASK }, // 448 |
| 33663 | { 0x3, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG3EI8_V_MF4_MF2_MASK }, // 449 |
| 33664 | { 0x3, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG3EI8_V_MF2_MF2_MASK }, // 450 |
| 33665 | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG3EI16_V_M1_M1_MASK }, // 451 |
| 33666 | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG3EI16_V_M2_M1_MASK }, // 452 |
| 33667 | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG3EI16_V_MF4_M1_MASK }, // 453 |
| 33668 | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG3EI16_V_MF2_M1_MASK }, // 454 |
| 33669 | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG3EI16_V_M1_M2_MASK }, // 455 |
| 33670 | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG3EI16_V_M2_M2_MASK }, // 456 |
| 33671 | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG3EI16_V_M4_M2_MASK }, // 457 |
| 33672 | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG3EI16_V_MF2_M2_MASK }, // 458 |
| 33673 | { 0x3, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF8_MASK }, // 459 |
| 33674 | { 0x3, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF4_MASK }, // 460 |
| 33675 | { 0x3, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG3EI16_V_MF2_MF4_MASK }, // 461 |
| 33676 | { 0x3, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG3EI16_V_M1_MF2_MASK }, // 462 |
| 33677 | { 0x3, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF2_MASK }, // 463 |
| 33678 | { 0x3, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG3EI16_V_MF2_MF2_MASK }, // 464 |
| 33679 | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG3EI32_V_M1_M1_MASK }, // 465 |
| 33680 | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG3EI32_V_M2_M1_MASK }, // 466 |
| 33681 | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG3EI32_V_M4_M1_MASK }, // 467 |
| 33682 | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG3EI32_V_MF2_M1_MASK }, // 468 |
| 33683 | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG3EI32_V_M1_M2_MASK }, // 469 |
| 33684 | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG3EI32_V_M2_M2_MASK }, // 470 |
| 33685 | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG3EI32_V_M4_M2_MASK }, // 471 |
| 33686 | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG3EI32_V_M8_M2_MASK }, // 472 |
| 33687 | { 0x3, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF8_MASK }, // 473 |
| 33688 | { 0x3, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG3EI32_V_M1_MF4_MASK }, // 474 |
| 33689 | { 0x3, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF4_MASK }, // 475 |
| 33690 | { 0x3, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG3EI32_V_M1_MF2_MASK }, // 476 |
| 33691 | { 0x3, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG3EI32_V_M2_MF2_MASK }, // 477 |
| 33692 | { 0x3, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF2_MASK }, // 478 |
| 33693 | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG3EI64_V_M1_M1_MASK }, // 479 |
| 33694 | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG3EI64_V_M2_M1_MASK }, // 480 |
| 33695 | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG3EI64_V_M4_M1_MASK }, // 481 |
| 33696 | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG3EI64_V_M8_M1_MASK }, // 482 |
| 33697 | { 0x3, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG3EI64_V_M2_M2_MASK }, // 483 |
| 33698 | { 0x3, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG3EI64_V_M4_M2_MASK }, // 484 |
| 33699 | { 0x3, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG3EI64_V_M8_M2_MASK }, // 485 |
| 33700 | { 0x3, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG3EI64_V_M1_MF8_MASK }, // 486 |
| 33701 | { 0x3, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG3EI64_V_M1_MF4_MASK }, // 487 |
| 33702 | { 0x3, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG3EI64_V_M2_MF4_MASK }, // 488 |
| 33703 | { 0x3, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG3EI64_V_M1_MF2_MASK }, // 489 |
| 33704 | { 0x3, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG3EI64_V_M2_MF2_MASK }, // 490 |
| 33705 | { 0x3, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG3EI64_V_M4_MF2_MASK }, // 491 |
| 33706 | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG4EI8_V_M1_M1 }, // 492 |
| 33707 | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG4EI8_V_MF8_M1 }, // 493 |
| 33708 | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG4EI8_V_MF4_M1 }, // 494 |
| 33709 | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG4EI8_V_MF2_M1 }, // 495 |
| 33710 | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG4EI8_V_M1_M2 }, // 496 |
| 33711 | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG4EI8_V_M2_M2 }, // 497 |
| 33712 | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG4EI8_V_MF4_M2 }, // 498 |
| 33713 | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG4EI8_V_MF2_M2 }, // 499 |
| 33714 | { 0x4, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF8 }, // 500 |
| 33715 | { 0x4, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF4 }, // 501 |
| 33716 | { 0x4, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG4EI8_V_MF4_MF4 }, // 502 |
| 33717 | { 0x4, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF2 }, // 503 |
| 33718 | { 0x4, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG4EI8_V_MF4_MF2 }, // 504 |
| 33719 | { 0x4, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG4EI8_V_MF2_MF2 }, // 505 |
| 33720 | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG4EI16_V_M1_M1 }, // 506 |
| 33721 | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG4EI16_V_M2_M1 }, // 507 |
| 33722 | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG4EI16_V_MF4_M1 }, // 508 |
| 33723 | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG4EI16_V_MF2_M1 }, // 509 |
| 33724 | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG4EI16_V_M1_M2 }, // 510 |
| 33725 | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG4EI16_V_M2_M2 }, // 511 |
| 33726 | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG4EI16_V_M4_M2 }, // 512 |
| 33727 | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG4EI16_V_MF2_M2 }, // 513 |
| 33728 | { 0x4, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF8 }, // 514 |
| 33729 | { 0x4, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF4 }, // 515 |
| 33730 | { 0x4, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG4EI16_V_MF2_MF4 }, // 516 |
| 33731 | { 0x4, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG4EI16_V_M1_MF2 }, // 517 |
| 33732 | { 0x4, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF2 }, // 518 |
| 33733 | { 0x4, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG4EI16_V_MF2_MF2 }, // 519 |
| 33734 | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG4EI32_V_M1_M1 }, // 520 |
| 33735 | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG4EI32_V_M2_M1 }, // 521 |
| 33736 | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG4EI32_V_M4_M1 }, // 522 |
| 33737 | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG4EI32_V_MF2_M1 }, // 523 |
| 33738 | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG4EI32_V_M1_M2 }, // 524 |
| 33739 | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG4EI32_V_M2_M2 }, // 525 |
| 33740 | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG4EI32_V_M4_M2 }, // 526 |
| 33741 | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG4EI32_V_M8_M2 }, // 527 |
| 33742 | { 0x4, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF8 }, // 528 |
| 33743 | { 0x4, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG4EI32_V_M1_MF4 }, // 529 |
| 33744 | { 0x4, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF4 }, // 530 |
| 33745 | { 0x4, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG4EI32_V_M1_MF2 }, // 531 |
| 33746 | { 0x4, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG4EI32_V_M2_MF2 }, // 532 |
| 33747 | { 0x4, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF2 }, // 533 |
| 33748 | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG4EI64_V_M1_M1 }, // 534 |
| 33749 | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG4EI64_V_M2_M1 }, // 535 |
| 33750 | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG4EI64_V_M4_M1 }, // 536 |
| 33751 | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG4EI64_V_M8_M1 }, // 537 |
| 33752 | { 0x4, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG4EI64_V_M2_M2 }, // 538 |
| 33753 | { 0x4, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG4EI64_V_M4_M2 }, // 539 |
| 33754 | { 0x4, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG4EI64_V_M8_M2 }, // 540 |
| 33755 | { 0x4, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG4EI64_V_M1_MF8 }, // 541 |
| 33756 | { 0x4, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG4EI64_V_M1_MF4 }, // 542 |
| 33757 | { 0x4, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG4EI64_V_M2_MF4 }, // 543 |
| 33758 | { 0x4, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG4EI64_V_M1_MF2 }, // 544 |
| 33759 | { 0x4, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG4EI64_V_M2_MF2 }, // 545 |
| 33760 | { 0x4, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG4EI64_V_M4_MF2 }, // 546 |
| 33761 | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG4EI8_V_M1_M1 }, // 547 |
| 33762 | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG4EI8_V_MF8_M1 }, // 548 |
| 33763 | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG4EI8_V_MF4_M1 }, // 549 |
| 33764 | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG4EI8_V_MF2_M1 }, // 550 |
| 33765 | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG4EI8_V_M1_M2 }, // 551 |
| 33766 | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG4EI8_V_M2_M2 }, // 552 |
| 33767 | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG4EI8_V_MF4_M2 }, // 553 |
| 33768 | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG4EI8_V_MF2_M2 }, // 554 |
| 33769 | { 0x4, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF8 }, // 555 |
| 33770 | { 0x4, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF4 }, // 556 |
| 33771 | { 0x4, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG4EI8_V_MF4_MF4 }, // 557 |
| 33772 | { 0x4, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF2 }, // 558 |
| 33773 | { 0x4, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG4EI8_V_MF4_MF2 }, // 559 |
| 33774 | { 0x4, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG4EI8_V_MF2_MF2 }, // 560 |
| 33775 | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG4EI16_V_M1_M1 }, // 561 |
| 33776 | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG4EI16_V_M2_M1 }, // 562 |
| 33777 | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG4EI16_V_MF4_M1 }, // 563 |
| 33778 | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG4EI16_V_MF2_M1 }, // 564 |
| 33779 | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG4EI16_V_M1_M2 }, // 565 |
| 33780 | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG4EI16_V_M2_M2 }, // 566 |
| 33781 | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG4EI16_V_M4_M2 }, // 567 |
| 33782 | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG4EI16_V_MF2_M2 }, // 568 |
| 33783 | { 0x4, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF8 }, // 569 |
| 33784 | { 0x4, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF4 }, // 570 |
| 33785 | { 0x4, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG4EI16_V_MF2_MF4 }, // 571 |
| 33786 | { 0x4, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG4EI16_V_M1_MF2 }, // 572 |
| 33787 | { 0x4, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF2 }, // 573 |
| 33788 | { 0x4, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG4EI16_V_MF2_MF2 }, // 574 |
| 33789 | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG4EI32_V_M1_M1 }, // 575 |
| 33790 | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG4EI32_V_M2_M1 }, // 576 |
| 33791 | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG4EI32_V_M4_M1 }, // 577 |
| 33792 | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG4EI32_V_MF2_M1 }, // 578 |
| 33793 | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG4EI32_V_M1_M2 }, // 579 |
| 33794 | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG4EI32_V_M2_M2 }, // 580 |
| 33795 | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG4EI32_V_M4_M2 }, // 581 |
| 33796 | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG4EI32_V_M8_M2 }, // 582 |
| 33797 | { 0x4, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF8 }, // 583 |
| 33798 | { 0x4, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG4EI32_V_M1_MF4 }, // 584 |
| 33799 | { 0x4, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF4 }, // 585 |
| 33800 | { 0x4, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG4EI32_V_M1_MF2 }, // 586 |
| 33801 | { 0x4, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG4EI32_V_M2_MF2 }, // 587 |
| 33802 | { 0x4, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF2 }, // 588 |
| 33803 | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG4EI64_V_M1_M1 }, // 589 |
| 33804 | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG4EI64_V_M2_M1 }, // 590 |
| 33805 | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG4EI64_V_M4_M1 }, // 591 |
| 33806 | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG4EI64_V_M8_M1 }, // 592 |
| 33807 | { 0x4, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG4EI64_V_M2_M2 }, // 593 |
| 33808 | { 0x4, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG4EI64_V_M4_M2 }, // 594 |
| 33809 | { 0x4, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG4EI64_V_M8_M2 }, // 595 |
| 33810 | { 0x4, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG4EI64_V_M1_MF8 }, // 596 |
| 33811 | { 0x4, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG4EI64_V_M1_MF4 }, // 597 |
| 33812 | { 0x4, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG4EI64_V_M2_MF4 }, // 598 |
| 33813 | { 0x4, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG4EI64_V_M1_MF2 }, // 599 |
| 33814 | { 0x4, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG4EI64_V_M2_MF2 }, // 600 |
| 33815 | { 0x4, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG4EI64_V_M4_MF2 }, // 601 |
| 33816 | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG4EI8_V_M1_M1_MASK }, // 602 |
| 33817 | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG4EI8_V_MF8_M1_MASK }, // 603 |
| 33818 | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG4EI8_V_MF4_M1_MASK }, // 604 |
| 33819 | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG4EI8_V_MF2_M1_MASK }, // 605 |
| 33820 | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG4EI8_V_M1_M2_MASK }, // 606 |
| 33821 | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG4EI8_V_M2_M2_MASK }, // 607 |
| 33822 | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG4EI8_V_MF4_M2_MASK }, // 608 |
| 33823 | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG4EI8_V_MF2_M2_MASK }, // 609 |
| 33824 | { 0x4, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF8_MASK }, // 610 |
| 33825 | { 0x4, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF4_MASK }, // 611 |
| 33826 | { 0x4, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG4EI8_V_MF4_MF4_MASK }, // 612 |
| 33827 | { 0x4, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF2_MASK }, // 613 |
| 33828 | { 0x4, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG4EI8_V_MF4_MF2_MASK }, // 614 |
| 33829 | { 0x4, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG4EI8_V_MF2_MF2_MASK }, // 615 |
| 33830 | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG4EI16_V_M1_M1_MASK }, // 616 |
| 33831 | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG4EI16_V_M2_M1_MASK }, // 617 |
| 33832 | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG4EI16_V_MF4_M1_MASK }, // 618 |
| 33833 | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG4EI16_V_MF2_M1_MASK }, // 619 |
| 33834 | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG4EI16_V_M1_M2_MASK }, // 620 |
| 33835 | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG4EI16_V_M2_M2_MASK }, // 621 |
| 33836 | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG4EI16_V_M4_M2_MASK }, // 622 |
| 33837 | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG4EI16_V_MF2_M2_MASK }, // 623 |
| 33838 | { 0x4, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF8_MASK }, // 624 |
| 33839 | { 0x4, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF4_MASK }, // 625 |
| 33840 | { 0x4, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG4EI16_V_MF2_MF4_MASK }, // 626 |
| 33841 | { 0x4, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG4EI16_V_M1_MF2_MASK }, // 627 |
| 33842 | { 0x4, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF2_MASK }, // 628 |
| 33843 | { 0x4, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG4EI16_V_MF2_MF2_MASK }, // 629 |
| 33844 | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG4EI32_V_M1_M1_MASK }, // 630 |
| 33845 | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG4EI32_V_M2_M1_MASK }, // 631 |
| 33846 | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG4EI32_V_M4_M1_MASK }, // 632 |
| 33847 | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG4EI32_V_MF2_M1_MASK }, // 633 |
| 33848 | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG4EI32_V_M1_M2_MASK }, // 634 |
| 33849 | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG4EI32_V_M2_M2_MASK }, // 635 |
| 33850 | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG4EI32_V_M4_M2_MASK }, // 636 |
| 33851 | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG4EI32_V_M8_M2_MASK }, // 637 |
| 33852 | { 0x4, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF8_MASK }, // 638 |
| 33853 | { 0x4, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG4EI32_V_M1_MF4_MASK }, // 639 |
| 33854 | { 0x4, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF4_MASK }, // 640 |
| 33855 | { 0x4, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG4EI32_V_M1_MF2_MASK }, // 641 |
| 33856 | { 0x4, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG4EI32_V_M2_MF2_MASK }, // 642 |
| 33857 | { 0x4, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF2_MASK }, // 643 |
| 33858 | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG4EI64_V_M1_M1_MASK }, // 644 |
| 33859 | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG4EI64_V_M2_M1_MASK }, // 645 |
| 33860 | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG4EI64_V_M4_M1_MASK }, // 646 |
| 33861 | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG4EI64_V_M8_M1_MASK }, // 647 |
| 33862 | { 0x4, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG4EI64_V_M2_M2_MASK }, // 648 |
| 33863 | { 0x4, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG4EI64_V_M4_M2_MASK }, // 649 |
| 33864 | { 0x4, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG4EI64_V_M8_M2_MASK }, // 650 |
| 33865 | { 0x4, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG4EI64_V_M1_MF8_MASK }, // 651 |
| 33866 | { 0x4, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG4EI64_V_M1_MF4_MASK }, // 652 |
| 33867 | { 0x4, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG4EI64_V_M2_MF4_MASK }, // 653 |
| 33868 | { 0x4, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG4EI64_V_M1_MF2_MASK }, // 654 |
| 33869 | { 0x4, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG4EI64_V_M2_MF2_MASK }, // 655 |
| 33870 | { 0x4, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG4EI64_V_M4_MF2_MASK }, // 656 |
| 33871 | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG4EI8_V_M1_M1_MASK }, // 657 |
| 33872 | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG4EI8_V_MF8_M1_MASK }, // 658 |
| 33873 | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG4EI8_V_MF4_M1_MASK }, // 659 |
| 33874 | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG4EI8_V_MF2_M1_MASK }, // 660 |
| 33875 | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG4EI8_V_M1_M2_MASK }, // 661 |
| 33876 | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG4EI8_V_M2_M2_MASK }, // 662 |
| 33877 | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG4EI8_V_MF4_M2_MASK }, // 663 |
| 33878 | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG4EI8_V_MF2_M2_MASK }, // 664 |
| 33879 | { 0x4, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF8_MASK }, // 665 |
| 33880 | { 0x4, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF4_MASK }, // 666 |
| 33881 | { 0x4, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG4EI8_V_MF4_MF4_MASK }, // 667 |
| 33882 | { 0x4, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF2_MASK }, // 668 |
| 33883 | { 0x4, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG4EI8_V_MF4_MF2_MASK }, // 669 |
| 33884 | { 0x4, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG4EI8_V_MF2_MF2_MASK }, // 670 |
| 33885 | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG4EI16_V_M1_M1_MASK }, // 671 |
| 33886 | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG4EI16_V_M2_M1_MASK }, // 672 |
| 33887 | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG4EI16_V_MF4_M1_MASK }, // 673 |
| 33888 | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG4EI16_V_MF2_M1_MASK }, // 674 |
| 33889 | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG4EI16_V_M1_M2_MASK }, // 675 |
| 33890 | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG4EI16_V_M2_M2_MASK }, // 676 |
| 33891 | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG4EI16_V_M4_M2_MASK }, // 677 |
| 33892 | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG4EI16_V_MF2_M2_MASK }, // 678 |
| 33893 | { 0x4, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF8_MASK }, // 679 |
| 33894 | { 0x4, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF4_MASK }, // 680 |
| 33895 | { 0x4, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG4EI16_V_MF2_MF4_MASK }, // 681 |
| 33896 | { 0x4, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG4EI16_V_M1_MF2_MASK }, // 682 |
| 33897 | { 0x4, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF2_MASK }, // 683 |
| 33898 | { 0x4, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG4EI16_V_MF2_MF2_MASK }, // 684 |
| 33899 | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG4EI32_V_M1_M1_MASK }, // 685 |
| 33900 | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG4EI32_V_M2_M1_MASK }, // 686 |
| 33901 | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG4EI32_V_M4_M1_MASK }, // 687 |
| 33902 | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG4EI32_V_MF2_M1_MASK }, // 688 |
| 33903 | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG4EI32_V_M1_M2_MASK }, // 689 |
| 33904 | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG4EI32_V_M2_M2_MASK }, // 690 |
| 33905 | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG4EI32_V_M4_M2_MASK }, // 691 |
| 33906 | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG4EI32_V_M8_M2_MASK }, // 692 |
| 33907 | { 0x4, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF8_MASK }, // 693 |
| 33908 | { 0x4, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG4EI32_V_M1_MF4_MASK }, // 694 |
| 33909 | { 0x4, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF4_MASK }, // 695 |
| 33910 | { 0x4, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG4EI32_V_M1_MF2_MASK }, // 696 |
| 33911 | { 0x4, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG4EI32_V_M2_MF2_MASK }, // 697 |
| 33912 | { 0x4, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF2_MASK }, // 698 |
| 33913 | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG4EI64_V_M1_M1_MASK }, // 699 |
| 33914 | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG4EI64_V_M2_M1_MASK }, // 700 |
| 33915 | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG4EI64_V_M4_M1_MASK }, // 701 |
| 33916 | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG4EI64_V_M8_M1_MASK }, // 702 |
| 33917 | { 0x4, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG4EI64_V_M2_M2_MASK }, // 703 |
| 33918 | { 0x4, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG4EI64_V_M4_M2_MASK }, // 704 |
| 33919 | { 0x4, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG4EI64_V_M8_M2_MASK }, // 705 |
| 33920 | { 0x4, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG4EI64_V_M1_MF8_MASK }, // 706 |
| 33921 | { 0x4, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG4EI64_V_M1_MF4_MASK }, // 707 |
| 33922 | { 0x4, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG4EI64_V_M2_MF4_MASK }, // 708 |
| 33923 | { 0x4, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG4EI64_V_M1_MF2_MASK }, // 709 |
| 33924 | { 0x4, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG4EI64_V_M2_MF2_MASK }, // 710 |
| 33925 | { 0x4, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG4EI64_V_M4_MF2_MASK }, // 711 |
| 33926 | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG5EI8_V_M1_M1 }, // 712 |
| 33927 | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG5EI8_V_MF8_M1 }, // 713 |
| 33928 | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG5EI8_V_MF4_M1 }, // 714 |
| 33929 | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG5EI8_V_MF2_M1 }, // 715 |
| 33930 | { 0x5, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF8 }, // 716 |
| 33931 | { 0x5, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF4 }, // 717 |
| 33932 | { 0x5, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG5EI8_V_MF4_MF4 }, // 718 |
| 33933 | { 0x5, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF2 }, // 719 |
| 33934 | { 0x5, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG5EI8_V_MF4_MF2 }, // 720 |
| 33935 | { 0x5, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG5EI8_V_MF2_MF2 }, // 721 |
| 33936 | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG5EI16_V_M1_M1 }, // 722 |
| 33937 | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG5EI16_V_M2_M1 }, // 723 |
| 33938 | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG5EI16_V_MF4_M1 }, // 724 |
| 33939 | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG5EI16_V_MF2_M1 }, // 725 |
| 33940 | { 0x5, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF8 }, // 726 |
| 33941 | { 0x5, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF4 }, // 727 |
| 33942 | { 0x5, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG5EI16_V_MF2_MF4 }, // 728 |
| 33943 | { 0x5, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG5EI16_V_M1_MF2 }, // 729 |
| 33944 | { 0x5, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF2 }, // 730 |
| 33945 | { 0x5, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG5EI16_V_MF2_MF2 }, // 731 |
| 33946 | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG5EI32_V_M1_M1 }, // 732 |
| 33947 | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG5EI32_V_M2_M1 }, // 733 |
| 33948 | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG5EI32_V_M4_M1 }, // 734 |
| 33949 | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG5EI32_V_MF2_M1 }, // 735 |
| 33950 | { 0x5, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF8 }, // 736 |
| 33951 | { 0x5, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG5EI32_V_M1_MF4 }, // 737 |
| 33952 | { 0x5, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF4 }, // 738 |
| 33953 | { 0x5, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG5EI32_V_M1_MF2 }, // 739 |
| 33954 | { 0x5, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG5EI32_V_M2_MF2 }, // 740 |
| 33955 | { 0x5, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF2 }, // 741 |
| 33956 | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG5EI64_V_M1_M1 }, // 742 |
| 33957 | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG5EI64_V_M2_M1 }, // 743 |
| 33958 | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG5EI64_V_M4_M1 }, // 744 |
| 33959 | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG5EI64_V_M8_M1 }, // 745 |
| 33960 | { 0x5, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG5EI64_V_M1_MF8 }, // 746 |
| 33961 | { 0x5, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG5EI64_V_M1_MF4 }, // 747 |
| 33962 | { 0x5, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG5EI64_V_M2_MF4 }, // 748 |
| 33963 | { 0x5, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG5EI64_V_M1_MF2 }, // 749 |
| 33964 | { 0x5, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG5EI64_V_M2_MF2 }, // 750 |
| 33965 | { 0x5, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG5EI64_V_M4_MF2 }, // 751 |
| 33966 | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG5EI8_V_M1_M1 }, // 752 |
| 33967 | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG5EI8_V_MF8_M1 }, // 753 |
| 33968 | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG5EI8_V_MF4_M1 }, // 754 |
| 33969 | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG5EI8_V_MF2_M1 }, // 755 |
| 33970 | { 0x5, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF8 }, // 756 |
| 33971 | { 0x5, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF4 }, // 757 |
| 33972 | { 0x5, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG5EI8_V_MF4_MF4 }, // 758 |
| 33973 | { 0x5, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF2 }, // 759 |
| 33974 | { 0x5, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG5EI8_V_MF4_MF2 }, // 760 |
| 33975 | { 0x5, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG5EI8_V_MF2_MF2 }, // 761 |
| 33976 | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG5EI16_V_M1_M1 }, // 762 |
| 33977 | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG5EI16_V_M2_M1 }, // 763 |
| 33978 | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG5EI16_V_MF4_M1 }, // 764 |
| 33979 | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG5EI16_V_MF2_M1 }, // 765 |
| 33980 | { 0x5, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF8 }, // 766 |
| 33981 | { 0x5, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF4 }, // 767 |
| 33982 | { 0x5, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG5EI16_V_MF2_MF4 }, // 768 |
| 33983 | { 0x5, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG5EI16_V_M1_MF2 }, // 769 |
| 33984 | { 0x5, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF2 }, // 770 |
| 33985 | { 0x5, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG5EI16_V_MF2_MF2 }, // 771 |
| 33986 | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG5EI32_V_M1_M1 }, // 772 |
| 33987 | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG5EI32_V_M2_M1 }, // 773 |
| 33988 | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG5EI32_V_M4_M1 }, // 774 |
| 33989 | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG5EI32_V_MF2_M1 }, // 775 |
| 33990 | { 0x5, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF8 }, // 776 |
| 33991 | { 0x5, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG5EI32_V_M1_MF4 }, // 777 |
| 33992 | { 0x5, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF4 }, // 778 |
| 33993 | { 0x5, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG5EI32_V_M1_MF2 }, // 779 |
| 33994 | { 0x5, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG5EI32_V_M2_MF2 }, // 780 |
| 33995 | { 0x5, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF2 }, // 781 |
| 33996 | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG5EI64_V_M1_M1 }, // 782 |
| 33997 | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG5EI64_V_M2_M1 }, // 783 |
| 33998 | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG5EI64_V_M4_M1 }, // 784 |
| 33999 | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG5EI64_V_M8_M1 }, // 785 |
| 34000 | { 0x5, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG5EI64_V_M1_MF8 }, // 786 |
| 34001 | { 0x5, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG5EI64_V_M1_MF4 }, // 787 |
| 34002 | { 0x5, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG5EI64_V_M2_MF4 }, // 788 |
| 34003 | { 0x5, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG5EI64_V_M1_MF2 }, // 789 |
| 34004 | { 0x5, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG5EI64_V_M2_MF2 }, // 790 |
| 34005 | { 0x5, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG5EI64_V_M4_MF2 }, // 791 |
| 34006 | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG5EI8_V_M1_M1_MASK }, // 792 |
| 34007 | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG5EI8_V_MF8_M1_MASK }, // 793 |
| 34008 | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG5EI8_V_MF4_M1_MASK }, // 794 |
| 34009 | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG5EI8_V_MF2_M1_MASK }, // 795 |
| 34010 | { 0x5, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF8_MASK }, // 796 |
| 34011 | { 0x5, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF4_MASK }, // 797 |
| 34012 | { 0x5, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG5EI8_V_MF4_MF4_MASK }, // 798 |
| 34013 | { 0x5, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF2_MASK }, // 799 |
| 34014 | { 0x5, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG5EI8_V_MF4_MF2_MASK }, // 800 |
| 34015 | { 0x5, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG5EI8_V_MF2_MF2_MASK }, // 801 |
| 34016 | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG5EI16_V_M1_M1_MASK }, // 802 |
| 34017 | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG5EI16_V_M2_M1_MASK }, // 803 |
| 34018 | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG5EI16_V_MF4_M1_MASK }, // 804 |
| 34019 | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG5EI16_V_MF2_M1_MASK }, // 805 |
| 34020 | { 0x5, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF8_MASK }, // 806 |
| 34021 | { 0x5, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF4_MASK }, // 807 |
| 34022 | { 0x5, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG5EI16_V_MF2_MF4_MASK }, // 808 |
| 34023 | { 0x5, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG5EI16_V_M1_MF2_MASK }, // 809 |
| 34024 | { 0x5, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF2_MASK }, // 810 |
| 34025 | { 0x5, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG5EI16_V_MF2_MF2_MASK }, // 811 |
| 34026 | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG5EI32_V_M1_M1_MASK }, // 812 |
| 34027 | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG5EI32_V_M2_M1_MASK }, // 813 |
| 34028 | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG5EI32_V_M4_M1_MASK }, // 814 |
| 34029 | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG5EI32_V_MF2_M1_MASK }, // 815 |
| 34030 | { 0x5, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF8_MASK }, // 816 |
| 34031 | { 0x5, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG5EI32_V_M1_MF4_MASK }, // 817 |
| 34032 | { 0x5, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF4_MASK }, // 818 |
| 34033 | { 0x5, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG5EI32_V_M1_MF2_MASK }, // 819 |
| 34034 | { 0x5, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG5EI32_V_M2_MF2_MASK }, // 820 |
| 34035 | { 0x5, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF2_MASK }, // 821 |
| 34036 | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG5EI64_V_M1_M1_MASK }, // 822 |
| 34037 | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG5EI64_V_M2_M1_MASK }, // 823 |
| 34038 | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG5EI64_V_M4_M1_MASK }, // 824 |
| 34039 | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG5EI64_V_M8_M1_MASK }, // 825 |
| 34040 | { 0x5, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG5EI64_V_M1_MF8_MASK }, // 826 |
| 34041 | { 0x5, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG5EI64_V_M1_MF4_MASK }, // 827 |
| 34042 | { 0x5, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG5EI64_V_M2_MF4_MASK }, // 828 |
| 34043 | { 0x5, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG5EI64_V_M1_MF2_MASK }, // 829 |
| 34044 | { 0x5, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG5EI64_V_M2_MF2_MASK }, // 830 |
| 34045 | { 0x5, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG5EI64_V_M4_MF2_MASK }, // 831 |
| 34046 | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG5EI8_V_M1_M1_MASK }, // 832 |
| 34047 | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG5EI8_V_MF8_M1_MASK }, // 833 |
| 34048 | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG5EI8_V_MF4_M1_MASK }, // 834 |
| 34049 | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG5EI8_V_MF2_M1_MASK }, // 835 |
| 34050 | { 0x5, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF8_MASK }, // 836 |
| 34051 | { 0x5, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF4_MASK }, // 837 |
| 34052 | { 0x5, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG5EI8_V_MF4_MF4_MASK }, // 838 |
| 34053 | { 0x5, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF2_MASK }, // 839 |
| 34054 | { 0x5, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG5EI8_V_MF4_MF2_MASK }, // 840 |
| 34055 | { 0x5, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG5EI8_V_MF2_MF2_MASK }, // 841 |
| 34056 | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG5EI16_V_M1_M1_MASK }, // 842 |
| 34057 | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG5EI16_V_M2_M1_MASK }, // 843 |
| 34058 | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG5EI16_V_MF4_M1_MASK }, // 844 |
| 34059 | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG5EI16_V_MF2_M1_MASK }, // 845 |
| 34060 | { 0x5, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF8_MASK }, // 846 |
| 34061 | { 0x5, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF4_MASK }, // 847 |
| 34062 | { 0x5, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG5EI16_V_MF2_MF4_MASK }, // 848 |
| 34063 | { 0x5, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG5EI16_V_M1_MF2_MASK }, // 849 |
| 34064 | { 0x5, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF2_MASK }, // 850 |
| 34065 | { 0x5, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG5EI16_V_MF2_MF2_MASK }, // 851 |
| 34066 | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG5EI32_V_M1_M1_MASK }, // 852 |
| 34067 | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG5EI32_V_M2_M1_MASK }, // 853 |
| 34068 | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG5EI32_V_M4_M1_MASK }, // 854 |
| 34069 | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG5EI32_V_MF2_M1_MASK }, // 855 |
| 34070 | { 0x5, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF8_MASK }, // 856 |
| 34071 | { 0x5, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG5EI32_V_M1_MF4_MASK }, // 857 |
| 34072 | { 0x5, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF4_MASK }, // 858 |
| 34073 | { 0x5, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG5EI32_V_M1_MF2_MASK }, // 859 |
| 34074 | { 0x5, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG5EI32_V_M2_MF2_MASK }, // 860 |
| 34075 | { 0x5, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF2_MASK }, // 861 |
| 34076 | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG5EI64_V_M1_M1_MASK }, // 862 |
| 34077 | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG5EI64_V_M2_M1_MASK }, // 863 |
| 34078 | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG5EI64_V_M4_M1_MASK }, // 864 |
| 34079 | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG5EI64_V_M8_M1_MASK }, // 865 |
| 34080 | { 0x5, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG5EI64_V_M1_MF8_MASK }, // 866 |
| 34081 | { 0x5, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG5EI64_V_M1_MF4_MASK }, // 867 |
| 34082 | { 0x5, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG5EI64_V_M2_MF4_MASK }, // 868 |
| 34083 | { 0x5, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG5EI64_V_M1_MF2_MASK }, // 869 |
| 34084 | { 0x5, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG5EI64_V_M2_MF2_MASK }, // 870 |
| 34085 | { 0x5, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG5EI64_V_M4_MF2_MASK }, // 871 |
| 34086 | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG6EI8_V_M1_M1 }, // 872 |
| 34087 | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG6EI8_V_MF8_M1 }, // 873 |
| 34088 | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG6EI8_V_MF4_M1 }, // 874 |
| 34089 | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG6EI8_V_MF2_M1 }, // 875 |
| 34090 | { 0x6, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF8 }, // 876 |
| 34091 | { 0x6, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF4 }, // 877 |
| 34092 | { 0x6, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG6EI8_V_MF4_MF4 }, // 878 |
| 34093 | { 0x6, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF2 }, // 879 |
| 34094 | { 0x6, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG6EI8_V_MF4_MF2 }, // 880 |
| 34095 | { 0x6, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG6EI8_V_MF2_MF2 }, // 881 |
| 34096 | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG6EI16_V_M1_M1 }, // 882 |
| 34097 | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG6EI16_V_M2_M1 }, // 883 |
| 34098 | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG6EI16_V_MF4_M1 }, // 884 |
| 34099 | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG6EI16_V_MF2_M1 }, // 885 |
| 34100 | { 0x6, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF8 }, // 886 |
| 34101 | { 0x6, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF4 }, // 887 |
| 34102 | { 0x6, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG6EI16_V_MF2_MF4 }, // 888 |
| 34103 | { 0x6, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG6EI16_V_M1_MF2 }, // 889 |
| 34104 | { 0x6, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF2 }, // 890 |
| 34105 | { 0x6, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG6EI16_V_MF2_MF2 }, // 891 |
| 34106 | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG6EI32_V_M1_M1 }, // 892 |
| 34107 | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG6EI32_V_M2_M1 }, // 893 |
| 34108 | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG6EI32_V_M4_M1 }, // 894 |
| 34109 | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG6EI32_V_MF2_M1 }, // 895 |
| 34110 | { 0x6, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF8 }, // 896 |
| 34111 | { 0x6, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG6EI32_V_M1_MF4 }, // 897 |
| 34112 | { 0x6, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF4 }, // 898 |
| 34113 | { 0x6, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG6EI32_V_M1_MF2 }, // 899 |
| 34114 | { 0x6, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG6EI32_V_M2_MF2 }, // 900 |
| 34115 | { 0x6, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF2 }, // 901 |
| 34116 | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG6EI64_V_M1_M1 }, // 902 |
| 34117 | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG6EI64_V_M2_M1 }, // 903 |
| 34118 | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG6EI64_V_M4_M1 }, // 904 |
| 34119 | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG6EI64_V_M8_M1 }, // 905 |
| 34120 | { 0x6, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG6EI64_V_M1_MF8 }, // 906 |
| 34121 | { 0x6, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG6EI64_V_M1_MF4 }, // 907 |
| 34122 | { 0x6, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG6EI64_V_M2_MF4 }, // 908 |
| 34123 | { 0x6, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG6EI64_V_M1_MF2 }, // 909 |
| 34124 | { 0x6, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG6EI64_V_M2_MF2 }, // 910 |
| 34125 | { 0x6, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG6EI64_V_M4_MF2 }, // 911 |
| 34126 | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG6EI8_V_M1_M1 }, // 912 |
| 34127 | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG6EI8_V_MF8_M1 }, // 913 |
| 34128 | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG6EI8_V_MF4_M1 }, // 914 |
| 34129 | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG6EI8_V_MF2_M1 }, // 915 |
| 34130 | { 0x6, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF8 }, // 916 |
| 34131 | { 0x6, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF4 }, // 917 |
| 34132 | { 0x6, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG6EI8_V_MF4_MF4 }, // 918 |
| 34133 | { 0x6, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF2 }, // 919 |
| 34134 | { 0x6, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG6EI8_V_MF4_MF2 }, // 920 |
| 34135 | { 0x6, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG6EI8_V_MF2_MF2 }, // 921 |
| 34136 | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG6EI16_V_M1_M1 }, // 922 |
| 34137 | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG6EI16_V_M2_M1 }, // 923 |
| 34138 | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG6EI16_V_MF4_M1 }, // 924 |
| 34139 | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG6EI16_V_MF2_M1 }, // 925 |
| 34140 | { 0x6, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF8 }, // 926 |
| 34141 | { 0x6, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF4 }, // 927 |
| 34142 | { 0x6, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG6EI16_V_MF2_MF4 }, // 928 |
| 34143 | { 0x6, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG6EI16_V_M1_MF2 }, // 929 |
| 34144 | { 0x6, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF2 }, // 930 |
| 34145 | { 0x6, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG6EI16_V_MF2_MF2 }, // 931 |
| 34146 | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG6EI32_V_M1_M1 }, // 932 |
| 34147 | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG6EI32_V_M2_M1 }, // 933 |
| 34148 | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG6EI32_V_M4_M1 }, // 934 |
| 34149 | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG6EI32_V_MF2_M1 }, // 935 |
| 34150 | { 0x6, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF8 }, // 936 |
| 34151 | { 0x6, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG6EI32_V_M1_MF4 }, // 937 |
| 34152 | { 0x6, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF4 }, // 938 |
| 34153 | { 0x6, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG6EI32_V_M1_MF2 }, // 939 |
| 34154 | { 0x6, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG6EI32_V_M2_MF2 }, // 940 |
| 34155 | { 0x6, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF2 }, // 941 |
| 34156 | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG6EI64_V_M1_M1 }, // 942 |
| 34157 | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG6EI64_V_M2_M1 }, // 943 |
| 34158 | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG6EI64_V_M4_M1 }, // 944 |
| 34159 | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG6EI64_V_M8_M1 }, // 945 |
| 34160 | { 0x6, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG6EI64_V_M1_MF8 }, // 946 |
| 34161 | { 0x6, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG6EI64_V_M1_MF4 }, // 947 |
| 34162 | { 0x6, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG6EI64_V_M2_MF4 }, // 948 |
| 34163 | { 0x6, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG6EI64_V_M1_MF2 }, // 949 |
| 34164 | { 0x6, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG6EI64_V_M2_MF2 }, // 950 |
| 34165 | { 0x6, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG6EI64_V_M4_MF2 }, // 951 |
| 34166 | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG6EI8_V_M1_M1_MASK }, // 952 |
| 34167 | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG6EI8_V_MF8_M1_MASK }, // 953 |
| 34168 | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG6EI8_V_MF4_M1_MASK }, // 954 |
| 34169 | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG6EI8_V_MF2_M1_MASK }, // 955 |
| 34170 | { 0x6, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF8_MASK }, // 956 |
| 34171 | { 0x6, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF4_MASK }, // 957 |
| 34172 | { 0x6, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG6EI8_V_MF4_MF4_MASK }, // 958 |
| 34173 | { 0x6, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF2_MASK }, // 959 |
| 34174 | { 0x6, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG6EI8_V_MF4_MF2_MASK }, // 960 |
| 34175 | { 0x6, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG6EI8_V_MF2_MF2_MASK }, // 961 |
| 34176 | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG6EI16_V_M1_M1_MASK }, // 962 |
| 34177 | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG6EI16_V_M2_M1_MASK }, // 963 |
| 34178 | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG6EI16_V_MF4_M1_MASK }, // 964 |
| 34179 | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG6EI16_V_MF2_M1_MASK }, // 965 |
| 34180 | { 0x6, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF8_MASK }, // 966 |
| 34181 | { 0x6, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF4_MASK }, // 967 |
| 34182 | { 0x6, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG6EI16_V_MF2_MF4_MASK }, // 968 |
| 34183 | { 0x6, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG6EI16_V_M1_MF2_MASK }, // 969 |
| 34184 | { 0x6, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF2_MASK }, // 970 |
| 34185 | { 0x6, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG6EI16_V_MF2_MF2_MASK }, // 971 |
| 34186 | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG6EI32_V_M1_M1_MASK }, // 972 |
| 34187 | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG6EI32_V_M2_M1_MASK }, // 973 |
| 34188 | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG6EI32_V_M4_M1_MASK }, // 974 |
| 34189 | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG6EI32_V_MF2_M1_MASK }, // 975 |
| 34190 | { 0x6, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF8_MASK }, // 976 |
| 34191 | { 0x6, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG6EI32_V_M1_MF4_MASK }, // 977 |
| 34192 | { 0x6, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF4_MASK }, // 978 |
| 34193 | { 0x6, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG6EI32_V_M1_MF2_MASK }, // 979 |
| 34194 | { 0x6, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG6EI32_V_M2_MF2_MASK }, // 980 |
| 34195 | { 0x6, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF2_MASK }, // 981 |
| 34196 | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG6EI64_V_M1_M1_MASK }, // 982 |
| 34197 | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG6EI64_V_M2_M1_MASK }, // 983 |
| 34198 | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG6EI64_V_M4_M1_MASK }, // 984 |
| 34199 | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG6EI64_V_M8_M1_MASK }, // 985 |
| 34200 | { 0x6, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG6EI64_V_M1_MF8_MASK }, // 986 |
| 34201 | { 0x6, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG6EI64_V_M1_MF4_MASK }, // 987 |
| 34202 | { 0x6, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG6EI64_V_M2_MF4_MASK }, // 988 |
| 34203 | { 0x6, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG6EI64_V_M1_MF2_MASK }, // 989 |
| 34204 | { 0x6, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG6EI64_V_M2_MF2_MASK }, // 990 |
| 34205 | { 0x6, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG6EI64_V_M4_MF2_MASK }, // 991 |
| 34206 | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG6EI8_V_M1_M1_MASK }, // 992 |
| 34207 | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG6EI8_V_MF8_M1_MASK }, // 993 |
| 34208 | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG6EI8_V_MF4_M1_MASK }, // 994 |
| 34209 | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG6EI8_V_MF2_M1_MASK }, // 995 |
| 34210 | { 0x6, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF8_MASK }, // 996 |
| 34211 | { 0x6, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF4_MASK }, // 997 |
| 34212 | { 0x6, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG6EI8_V_MF4_MF4_MASK }, // 998 |
| 34213 | { 0x6, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF2_MASK }, // 999 |
| 34214 | { 0x6, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG6EI8_V_MF4_MF2_MASK }, // 1000 |
| 34215 | { 0x6, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG6EI8_V_MF2_MF2_MASK }, // 1001 |
| 34216 | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG6EI16_V_M1_M1_MASK }, // 1002 |
| 34217 | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG6EI16_V_M2_M1_MASK }, // 1003 |
| 34218 | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG6EI16_V_MF4_M1_MASK }, // 1004 |
| 34219 | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG6EI16_V_MF2_M1_MASK }, // 1005 |
| 34220 | { 0x6, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF8_MASK }, // 1006 |
| 34221 | { 0x6, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF4_MASK }, // 1007 |
| 34222 | { 0x6, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG6EI16_V_MF2_MF4_MASK }, // 1008 |
| 34223 | { 0x6, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG6EI16_V_M1_MF2_MASK }, // 1009 |
| 34224 | { 0x6, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF2_MASK }, // 1010 |
| 34225 | { 0x6, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG6EI16_V_MF2_MF2_MASK }, // 1011 |
| 34226 | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG6EI32_V_M1_M1_MASK }, // 1012 |
| 34227 | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG6EI32_V_M2_M1_MASK }, // 1013 |
| 34228 | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG6EI32_V_M4_M1_MASK }, // 1014 |
| 34229 | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG6EI32_V_MF2_M1_MASK }, // 1015 |
| 34230 | { 0x6, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF8_MASK }, // 1016 |
| 34231 | { 0x6, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG6EI32_V_M1_MF4_MASK }, // 1017 |
| 34232 | { 0x6, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF4_MASK }, // 1018 |
| 34233 | { 0x6, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG6EI32_V_M1_MF2_MASK }, // 1019 |
| 34234 | { 0x6, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG6EI32_V_M2_MF2_MASK }, // 1020 |
| 34235 | { 0x6, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF2_MASK }, // 1021 |
| 34236 | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG6EI64_V_M1_M1_MASK }, // 1022 |
| 34237 | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG6EI64_V_M2_M1_MASK }, // 1023 |
| 34238 | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG6EI64_V_M4_M1_MASK }, // 1024 |
| 34239 | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG6EI64_V_M8_M1_MASK }, // 1025 |
| 34240 | { 0x6, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG6EI64_V_M1_MF8_MASK }, // 1026 |
| 34241 | { 0x6, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG6EI64_V_M1_MF4_MASK }, // 1027 |
| 34242 | { 0x6, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG6EI64_V_M2_MF4_MASK }, // 1028 |
| 34243 | { 0x6, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG6EI64_V_M1_MF2_MASK }, // 1029 |
| 34244 | { 0x6, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG6EI64_V_M2_MF2_MASK }, // 1030 |
| 34245 | { 0x6, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG6EI64_V_M4_MF2_MASK }, // 1031 |
| 34246 | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG7EI8_V_M1_M1 }, // 1032 |
| 34247 | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG7EI8_V_MF8_M1 }, // 1033 |
| 34248 | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG7EI8_V_MF4_M1 }, // 1034 |
| 34249 | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG7EI8_V_MF2_M1 }, // 1035 |
| 34250 | { 0x7, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF8 }, // 1036 |
| 34251 | { 0x7, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF4 }, // 1037 |
| 34252 | { 0x7, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG7EI8_V_MF4_MF4 }, // 1038 |
| 34253 | { 0x7, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF2 }, // 1039 |
| 34254 | { 0x7, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG7EI8_V_MF4_MF2 }, // 1040 |
| 34255 | { 0x7, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG7EI8_V_MF2_MF2 }, // 1041 |
| 34256 | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG7EI16_V_M1_M1 }, // 1042 |
| 34257 | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG7EI16_V_M2_M1 }, // 1043 |
| 34258 | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG7EI16_V_MF4_M1 }, // 1044 |
| 34259 | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG7EI16_V_MF2_M1 }, // 1045 |
| 34260 | { 0x7, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF8 }, // 1046 |
| 34261 | { 0x7, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF4 }, // 1047 |
| 34262 | { 0x7, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG7EI16_V_MF2_MF4 }, // 1048 |
| 34263 | { 0x7, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG7EI16_V_M1_MF2 }, // 1049 |
| 34264 | { 0x7, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF2 }, // 1050 |
| 34265 | { 0x7, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG7EI16_V_MF2_MF2 }, // 1051 |
| 34266 | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG7EI32_V_M1_M1 }, // 1052 |
| 34267 | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG7EI32_V_M2_M1 }, // 1053 |
| 34268 | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG7EI32_V_M4_M1 }, // 1054 |
| 34269 | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG7EI32_V_MF2_M1 }, // 1055 |
| 34270 | { 0x7, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF8 }, // 1056 |
| 34271 | { 0x7, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG7EI32_V_M1_MF4 }, // 1057 |
| 34272 | { 0x7, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF4 }, // 1058 |
| 34273 | { 0x7, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG7EI32_V_M1_MF2 }, // 1059 |
| 34274 | { 0x7, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG7EI32_V_M2_MF2 }, // 1060 |
| 34275 | { 0x7, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF2 }, // 1061 |
| 34276 | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG7EI64_V_M1_M1 }, // 1062 |
| 34277 | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG7EI64_V_M2_M1 }, // 1063 |
| 34278 | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG7EI64_V_M4_M1 }, // 1064 |
| 34279 | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG7EI64_V_M8_M1 }, // 1065 |
| 34280 | { 0x7, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG7EI64_V_M1_MF8 }, // 1066 |
| 34281 | { 0x7, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG7EI64_V_M1_MF4 }, // 1067 |
| 34282 | { 0x7, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG7EI64_V_M2_MF4 }, // 1068 |
| 34283 | { 0x7, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG7EI64_V_M1_MF2 }, // 1069 |
| 34284 | { 0x7, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG7EI64_V_M2_MF2 }, // 1070 |
| 34285 | { 0x7, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG7EI64_V_M4_MF2 }, // 1071 |
| 34286 | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG7EI8_V_M1_M1 }, // 1072 |
| 34287 | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG7EI8_V_MF8_M1 }, // 1073 |
| 34288 | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG7EI8_V_MF4_M1 }, // 1074 |
| 34289 | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG7EI8_V_MF2_M1 }, // 1075 |
| 34290 | { 0x7, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF8 }, // 1076 |
| 34291 | { 0x7, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF4 }, // 1077 |
| 34292 | { 0x7, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG7EI8_V_MF4_MF4 }, // 1078 |
| 34293 | { 0x7, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF2 }, // 1079 |
| 34294 | { 0x7, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG7EI8_V_MF4_MF2 }, // 1080 |
| 34295 | { 0x7, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG7EI8_V_MF2_MF2 }, // 1081 |
| 34296 | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG7EI16_V_M1_M1 }, // 1082 |
| 34297 | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG7EI16_V_M2_M1 }, // 1083 |
| 34298 | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG7EI16_V_MF4_M1 }, // 1084 |
| 34299 | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG7EI16_V_MF2_M1 }, // 1085 |
| 34300 | { 0x7, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF8 }, // 1086 |
| 34301 | { 0x7, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF4 }, // 1087 |
| 34302 | { 0x7, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG7EI16_V_MF2_MF4 }, // 1088 |
| 34303 | { 0x7, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG7EI16_V_M1_MF2 }, // 1089 |
| 34304 | { 0x7, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF2 }, // 1090 |
| 34305 | { 0x7, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG7EI16_V_MF2_MF2 }, // 1091 |
| 34306 | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG7EI32_V_M1_M1 }, // 1092 |
| 34307 | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG7EI32_V_M2_M1 }, // 1093 |
| 34308 | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG7EI32_V_M4_M1 }, // 1094 |
| 34309 | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG7EI32_V_MF2_M1 }, // 1095 |
| 34310 | { 0x7, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF8 }, // 1096 |
| 34311 | { 0x7, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG7EI32_V_M1_MF4 }, // 1097 |
| 34312 | { 0x7, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF4 }, // 1098 |
| 34313 | { 0x7, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG7EI32_V_M1_MF2 }, // 1099 |
| 34314 | { 0x7, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG7EI32_V_M2_MF2 }, // 1100 |
| 34315 | { 0x7, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF2 }, // 1101 |
| 34316 | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG7EI64_V_M1_M1 }, // 1102 |
| 34317 | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG7EI64_V_M2_M1 }, // 1103 |
| 34318 | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG7EI64_V_M4_M1 }, // 1104 |
| 34319 | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG7EI64_V_M8_M1 }, // 1105 |
| 34320 | { 0x7, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG7EI64_V_M1_MF8 }, // 1106 |
| 34321 | { 0x7, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG7EI64_V_M1_MF4 }, // 1107 |
| 34322 | { 0x7, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG7EI64_V_M2_MF4 }, // 1108 |
| 34323 | { 0x7, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG7EI64_V_M1_MF2 }, // 1109 |
| 34324 | { 0x7, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG7EI64_V_M2_MF2 }, // 1110 |
| 34325 | { 0x7, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG7EI64_V_M4_MF2 }, // 1111 |
| 34326 | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG7EI8_V_M1_M1_MASK }, // 1112 |
| 34327 | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG7EI8_V_MF8_M1_MASK }, // 1113 |
| 34328 | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG7EI8_V_MF4_M1_MASK }, // 1114 |
| 34329 | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG7EI8_V_MF2_M1_MASK }, // 1115 |
| 34330 | { 0x7, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF8_MASK }, // 1116 |
| 34331 | { 0x7, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF4_MASK }, // 1117 |
| 34332 | { 0x7, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG7EI8_V_MF4_MF4_MASK }, // 1118 |
| 34333 | { 0x7, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF2_MASK }, // 1119 |
| 34334 | { 0x7, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG7EI8_V_MF4_MF2_MASK }, // 1120 |
| 34335 | { 0x7, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG7EI8_V_MF2_MF2_MASK }, // 1121 |
| 34336 | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG7EI16_V_M1_M1_MASK }, // 1122 |
| 34337 | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG7EI16_V_M2_M1_MASK }, // 1123 |
| 34338 | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG7EI16_V_MF4_M1_MASK }, // 1124 |
| 34339 | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG7EI16_V_MF2_M1_MASK }, // 1125 |
| 34340 | { 0x7, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF8_MASK }, // 1126 |
| 34341 | { 0x7, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF4_MASK }, // 1127 |
| 34342 | { 0x7, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG7EI16_V_MF2_MF4_MASK }, // 1128 |
| 34343 | { 0x7, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG7EI16_V_M1_MF2_MASK }, // 1129 |
| 34344 | { 0x7, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF2_MASK }, // 1130 |
| 34345 | { 0x7, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG7EI16_V_MF2_MF2_MASK }, // 1131 |
| 34346 | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG7EI32_V_M1_M1_MASK }, // 1132 |
| 34347 | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG7EI32_V_M2_M1_MASK }, // 1133 |
| 34348 | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG7EI32_V_M4_M1_MASK }, // 1134 |
| 34349 | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG7EI32_V_MF2_M1_MASK }, // 1135 |
| 34350 | { 0x7, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF8_MASK }, // 1136 |
| 34351 | { 0x7, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG7EI32_V_M1_MF4_MASK }, // 1137 |
| 34352 | { 0x7, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF4_MASK }, // 1138 |
| 34353 | { 0x7, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG7EI32_V_M1_MF2_MASK }, // 1139 |
| 34354 | { 0x7, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG7EI32_V_M2_MF2_MASK }, // 1140 |
| 34355 | { 0x7, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF2_MASK }, // 1141 |
| 34356 | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG7EI64_V_M1_M1_MASK }, // 1142 |
| 34357 | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG7EI64_V_M2_M1_MASK }, // 1143 |
| 34358 | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG7EI64_V_M4_M1_MASK }, // 1144 |
| 34359 | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG7EI64_V_M8_M1_MASK }, // 1145 |
| 34360 | { 0x7, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG7EI64_V_M1_MF8_MASK }, // 1146 |
| 34361 | { 0x7, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG7EI64_V_M1_MF4_MASK }, // 1147 |
| 34362 | { 0x7, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG7EI64_V_M2_MF4_MASK }, // 1148 |
| 34363 | { 0x7, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG7EI64_V_M1_MF2_MASK }, // 1149 |
| 34364 | { 0x7, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG7EI64_V_M2_MF2_MASK }, // 1150 |
| 34365 | { 0x7, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG7EI64_V_M4_MF2_MASK }, // 1151 |
| 34366 | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG7EI8_V_M1_M1_MASK }, // 1152 |
| 34367 | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG7EI8_V_MF8_M1_MASK }, // 1153 |
| 34368 | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG7EI8_V_MF4_M1_MASK }, // 1154 |
| 34369 | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG7EI8_V_MF2_M1_MASK }, // 1155 |
| 34370 | { 0x7, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF8_MASK }, // 1156 |
| 34371 | { 0x7, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF4_MASK }, // 1157 |
| 34372 | { 0x7, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG7EI8_V_MF4_MF4_MASK }, // 1158 |
| 34373 | { 0x7, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF2_MASK }, // 1159 |
| 34374 | { 0x7, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG7EI8_V_MF4_MF2_MASK }, // 1160 |
| 34375 | { 0x7, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG7EI8_V_MF2_MF2_MASK }, // 1161 |
| 34376 | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG7EI16_V_M1_M1_MASK }, // 1162 |
| 34377 | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG7EI16_V_M2_M1_MASK }, // 1163 |
| 34378 | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG7EI16_V_MF4_M1_MASK }, // 1164 |
| 34379 | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG7EI16_V_MF2_M1_MASK }, // 1165 |
| 34380 | { 0x7, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF8_MASK }, // 1166 |
| 34381 | { 0x7, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF4_MASK }, // 1167 |
| 34382 | { 0x7, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG7EI16_V_MF2_MF4_MASK }, // 1168 |
| 34383 | { 0x7, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG7EI16_V_M1_MF2_MASK }, // 1169 |
| 34384 | { 0x7, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF2_MASK }, // 1170 |
| 34385 | { 0x7, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG7EI16_V_MF2_MF2_MASK }, // 1171 |
| 34386 | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG7EI32_V_M1_M1_MASK }, // 1172 |
| 34387 | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG7EI32_V_M2_M1_MASK }, // 1173 |
| 34388 | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG7EI32_V_M4_M1_MASK }, // 1174 |
| 34389 | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG7EI32_V_MF2_M1_MASK }, // 1175 |
| 34390 | { 0x7, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF8_MASK }, // 1176 |
| 34391 | { 0x7, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG7EI32_V_M1_MF4_MASK }, // 1177 |
| 34392 | { 0x7, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF4_MASK }, // 1178 |
| 34393 | { 0x7, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG7EI32_V_M1_MF2_MASK }, // 1179 |
| 34394 | { 0x7, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG7EI32_V_M2_MF2_MASK }, // 1180 |
| 34395 | { 0x7, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF2_MASK }, // 1181 |
| 34396 | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG7EI64_V_M1_M1_MASK }, // 1182 |
| 34397 | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG7EI64_V_M2_M1_MASK }, // 1183 |
| 34398 | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG7EI64_V_M4_M1_MASK }, // 1184 |
| 34399 | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG7EI64_V_M8_M1_MASK }, // 1185 |
| 34400 | { 0x7, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG7EI64_V_M1_MF8_MASK }, // 1186 |
| 34401 | { 0x7, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG7EI64_V_M1_MF4_MASK }, // 1187 |
| 34402 | { 0x7, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG7EI64_V_M2_MF4_MASK }, // 1188 |
| 34403 | { 0x7, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG7EI64_V_M1_MF2_MASK }, // 1189 |
| 34404 | { 0x7, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG7EI64_V_M2_MF2_MASK }, // 1190 |
| 34405 | { 0x7, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG7EI64_V_M4_MF2_MASK }, // 1191 |
| 34406 | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG8EI8_V_M1_M1 }, // 1192 |
| 34407 | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG8EI8_V_MF8_M1 }, // 1193 |
| 34408 | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG8EI8_V_MF4_M1 }, // 1194 |
| 34409 | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG8EI8_V_MF2_M1 }, // 1195 |
| 34410 | { 0x8, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF8 }, // 1196 |
| 34411 | { 0x8, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF4 }, // 1197 |
| 34412 | { 0x8, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG8EI8_V_MF4_MF4 }, // 1198 |
| 34413 | { 0x8, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF2 }, // 1199 |
| 34414 | { 0x8, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG8EI8_V_MF4_MF2 }, // 1200 |
| 34415 | { 0x8, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG8EI8_V_MF2_MF2 }, // 1201 |
| 34416 | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG8EI16_V_M1_M1 }, // 1202 |
| 34417 | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG8EI16_V_M2_M1 }, // 1203 |
| 34418 | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG8EI16_V_MF4_M1 }, // 1204 |
| 34419 | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG8EI16_V_MF2_M1 }, // 1205 |
| 34420 | { 0x8, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF8 }, // 1206 |
| 34421 | { 0x8, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF4 }, // 1207 |
| 34422 | { 0x8, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG8EI16_V_MF2_MF4 }, // 1208 |
| 34423 | { 0x8, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG8EI16_V_M1_MF2 }, // 1209 |
| 34424 | { 0x8, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF2 }, // 1210 |
| 34425 | { 0x8, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG8EI16_V_MF2_MF2 }, // 1211 |
| 34426 | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG8EI32_V_M1_M1 }, // 1212 |
| 34427 | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG8EI32_V_M2_M1 }, // 1213 |
| 34428 | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG8EI32_V_M4_M1 }, // 1214 |
| 34429 | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG8EI32_V_MF2_M1 }, // 1215 |
| 34430 | { 0x8, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF8 }, // 1216 |
| 34431 | { 0x8, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG8EI32_V_M1_MF4 }, // 1217 |
| 34432 | { 0x8, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF4 }, // 1218 |
| 34433 | { 0x8, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG8EI32_V_M1_MF2 }, // 1219 |
| 34434 | { 0x8, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG8EI32_V_M2_MF2 }, // 1220 |
| 34435 | { 0x8, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF2 }, // 1221 |
| 34436 | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG8EI64_V_M1_M1 }, // 1222 |
| 34437 | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG8EI64_V_M2_M1 }, // 1223 |
| 34438 | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG8EI64_V_M4_M1 }, // 1224 |
| 34439 | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG8EI64_V_M8_M1 }, // 1225 |
| 34440 | { 0x8, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG8EI64_V_M1_MF8 }, // 1226 |
| 34441 | { 0x8, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG8EI64_V_M1_MF4 }, // 1227 |
| 34442 | { 0x8, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG8EI64_V_M2_MF4 }, // 1228 |
| 34443 | { 0x8, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG8EI64_V_M1_MF2 }, // 1229 |
| 34444 | { 0x8, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG8EI64_V_M2_MF2 }, // 1230 |
| 34445 | { 0x8, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG8EI64_V_M4_MF2 }, // 1231 |
| 34446 | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG8EI8_V_M1_M1 }, // 1232 |
| 34447 | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG8EI8_V_MF8_M1 }, // 1233 |
| 34448 | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG8EI8_V_MF4_M1 }, // 1234 |
| 34449 | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG8EI8_V_MF2_M1 }, // 1235 |
| 34450 | { 0x8, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF8 }, // 1236 |
| 34451 | { 0x8, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF4 }, // 1237 |
| 34452 | { 0x8, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG8EI8_V_MF4_MF4 }, // 1238 |
| 34453 | { 0x8, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF2 }, // 1239 |
| 34454 | { 0x8, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG8EI8_V_MF4_MF2 }, // 1240 |
| 34455 | { 0x8, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG8EI8_V_MF2_MF2 }, // 1241 |
| 34456 | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG8EI16_V_M1_M1 }, // 1242 |
| 34457 | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG8EI16_V_M2_M1 }, // 1243 |
| 34458 | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG8EI16_V_MF4_M1 }, // 1244 |
| 34459 | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG8EI16_V_MF2_M1 }, // 1245 |
| 34460 | { 0x8, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF8 }, // 1246 |
| 34461 | { 0x8, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF4 }, // 1247 |
| 34462 | { 0x8, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG8EI16_V_MF2_MF4 }, // 1248 |
| 34463 | { 0x8, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG8EI16_V_M1_MF2 }, // 1249 |
| 34464 | { 0x8, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF2 }, // 1250 |
| 34465 | { 0x8, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG8EI16_V_MF2_MF2 }, // 1251 |
| 34466 | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG8EI32_V_M1_M1 }, // 1252 |
| 34467 | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG8EI32_V_M2_M1 }, // 1253 |
| 34468 | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG8EI32_V_M4_M1 }, // 1254 |
| 34469 | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG8EI32_V_MF2_M1 }, // 1255 |
| 34470 | { 0x8, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF8 }, // 1256 |
| 34471 | { 0x8, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG8EI32_V_M1_MF4 }, // 1257 |
| 34472 | { 0x8, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF4 }, // 1258 |
| 34473 | { 0x8, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG8EI32_V_M1_MF2 }, // 1259 |
| 34474 | { 0x8, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG8EI32_V_M2_MF2 }, // 1260 |
| 34475 | { 0x8, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF2 }, // 1261 |
| 34476 | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG8EI64_V_M1_M1 }, // 1262 |
| 34477 | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG8EI64_V_M2_M1 }, // 1263 |
| 34478 | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG8EI64_V_M4_M1 }, // 1264 |
| 34479 | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG8EI64_V_M8_M1 }, // 1265 |
| 34480 | { 0x8, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG8EI64_V_M1_MF8 }, // 1266 |
| 34481 | { 0x8, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG8EI64_V_M1_MF4 }, // 1267 |
| 34482 | { 0x8, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG8EI64_V_M2_MF4 }, // 1268 |
| 34483 | { 0x8, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG8EI64_V_M1_MF2 }, // 1269 |
| 34484 | { 0x8, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG8EI64_V_M2_MF2 }, // 1270 |
| 34485 | { 0x8, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG8EI64_V_M4_MF2 }, // 1271 |
| 34486 | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG8EI8_V_M1_M1_MASK }, // 1272 |
| 34487 | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG8EI8_V_MF8_M1_MASK }, // 1273 |
| 34488 | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG8EI8_V_MF4_M1_MASK }, // 1274 |
| 34489 | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG8EI8_V_MF2_M1_MASK }, // 1275 |
| 34490 | { 0x8, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF8_MASK }, // 1276 |
| 34491 | { 0x8, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF4_MASK }, // 1277 |
| 34492 | { 0x8, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG8EI8_V_MF4_MF4_MASK }, // 1278 |
| 34493 | { 0x8, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF2_MASK }, // 1279 |
| 34494 | { 0x8, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG8EI8_V_MF4_MF2_MASK }, // 1280 |
| 34495 | { 0x8, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG8EI8_V_MF2_MF2_MASK }, // 1281 |
| 34496 | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG8EI16_V_M1_M1_MASK }, // 1282 |
| 34497 | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG8EI16_V_M2_M1_MASK }, // 1283 |
| 34498 | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG8EI16_V_MF4_M1_MASK }, // 1284 |
| 34499 | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG8EI16_V_MF2_M1_MASK }, // 1285 |
| 34500 | { 0x8, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF8_MASK }, // 1286 |
| 34501 | { 0x8, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF4_MASK }, // 1287 |
| 34502 | { 0x8, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG8EI16_V_MF2_MF4_MASK }, // 1288 |
| 34503 | { 0x8, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG8EI16_V_M1_MF2_MASK }, // 1289 |
| 34504 | { 0x8, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF2_MASK }, // 1290 |
| 34505 | { 0x8, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG8EI16_V_MF2_MF2_MASK }, // 1291 |
| 34506 | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG8EI32_V_M1_M1_MASK }, // 1292 |
| 34507 | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG8EI32_V_M2_M1_MASK }, // 1293 |
| 34508 | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG8EI32_V_M4_M1_MASK }, // 1294 |
| 34509 | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG8EI32_V_MF2_M1_MASK }, // 1295 |
| 34510 | { 0x8, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF8_MASK }, // 1296 |
| 34511 | { 0x8, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG8EI32_V_M1_MF4_MASK }, // 1297 |
| 34512 | { 0x8, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF4_MASK }, // 1298 |
| 34513 | { 0x8, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG8EI32_V_M1_MF2_MASK }, // 1299 |
| 34514 | { 0x8, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG8EI32_V_M2_MF2_MASK }, // 1300 |
| 34515 | { 0x8, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF2_MASK }, // 1301 |
| 34516 | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG8EI64_V_M1_M1_MASK }, // 1302 |
| 34517 | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG8EI64_V_M2_M1_MASK }, // 1303 |
| 34518 | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG8EI64_V_M4_M1_MASK }, // 1304 |
| 34519 | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG8EI64_V_M8_M1_MASK }, // 1305 |
| 34520 | { 0x8, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG8EI64_V_M1_MF8_MASK }, // 1306 |
| 34521 | { 0x8, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG8EI64_V_M1_MF4_MASK }, // 1307 |
| 34522 | { 0x8, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG8EI64_V_M2_MF4_MASK }, // 1308 |
| 34523 | { 0x8, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG8EI64_V_M1_MF2_MASK }, // 1309 |
| 34524 | { 0x8, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG8EI64_V_M2_MF2_MASK }, // 1310 |
| 34525 | { 0x8, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG8EI64_V_M4_MF2_MASK }, // 1311 |
| 34526 | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG8EI8_V_M1_M1_MASK }, // 1312 |
| 34527 | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG8EI8_V_MF8_M1_MASK }, // 1313 |
| 34528 | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG8EI8_V_MF4_M1_MASK }, // 1314 |
| 34529 | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG8EI8_V_MF2_M1_MASK }, // 1315 |
| 34530 | { 0x8, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF8_MASK }, // 1316 |
| 34531 | { 0x8, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF4_MASK }, // 1317 |
| 34532 | { 0x8, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG8EI8_V_MF4_MF4_MASK }, // 1318 |
| 34533 | { 0x8, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF2_MASK }, // 1319 |
| 34534 | { 0x8, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG8EI8_V_MF4_MF2_MASK }, // 1320 |
| 34535 | { 0x8, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG8EI8_V_MF2_MF2_MASK }, // 1321 |
| 34536 | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG8EI16_V_M1_M1_MASK }, // 1322 |
| 34537 | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG8EI16_V_M2_M1_MASK }, // 1323 |
| 34538 | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG8EI16_V_MF4_M1_MASK }, // 1324 |
| 34539 | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG8EI16_V_MF2_M1_MASK }, // 1325 |
| 34540 | { 0x8, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF8_MASK }, // 1326 |
| 34541 | { 0x8, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF4_MASK }, // 1327 |
| 34542 | { 0x8, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG8EI16_V_MF2_MF4_MASK }, // 1328 |
| 34543 | { 0x8, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG8EI16_V_M1_MF2_MASK }, // 1329 |
| 34544 | { 0x8, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF2_MASK }, // 1330 |
| 34545 | { 0x8, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG8EI16_V_MF2_MF2_MASK }, // 1331 |
| 34546 | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG8EI32_V_M1_M1_MASK }, // 1332 |
| 34547 | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG8EI32_V_M2_M1_MASK }, // 1333 |
| 34548 | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG8EI32_V_M4_M1_MASK }, // 1334 |
| 34549 | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG8EI32_V_MF2_M1_MASK }, // 1335 |
| 34550 | { 0x8, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF8_MASK }, // 1336 |
| 34551 | { 0x8, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG8EI32_V_M1_MF4_MASK }, // 1337 |
| 34552 | { 0x8, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF4_MASK }, // 1338 |
| 34553 | { 0x8, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG8EI32_V_M1_MF2_MASK }, // 1339 |
| 34554 | { 0x8, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG8EI32_V_M2_MF2_MASK }, // 1340 |
| 34555 | { 0x8, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF2_MASK }, // 1341 |
| 34556 | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG8EI64_V_M1_M1_MASK }, // 1342 |
| 34557 | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG8EI64_V_M2_M1_MASK }, // 1343 |
| 34558 | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG8EI64_V_M4_M1_MASK }, // 1344 |
| 34559 | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG8EI64_V_M8_M1_MASK }, // 1345 |
| 34560 | { 0x8, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG8EI64_V_M1_MF8_MASK }, // 1346 |
| 34561 | { 0x8, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG8EI64_V_M1_MF4_MASK }, // 1347 |
| 34562 | { 0x8, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG8EI64_V_M2_MF4_MASK }, // 1348 |
| 34563 | { 0x8, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG8EI64_V_M1_MF2_MASK }, // 1349 |
| 34564 | { 0x8, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG8EI64_V_M2_MF2_MASK }, // 1350 |
| 34565 | { 0x8, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG8EI64_V_M4_MF2_MASK }, // 1351 |
| 34566 | }; |
| 34567 | |
| 34568 | const VSXSEGPseudo *getVSXSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL) { |
| 34569 | struct KeyType { |
| 34570 | uint8_t NF; |
| 34571 | uint8_t Masked; |
| 34572 | uint8_t Ordered; |
| 34573 | uint8_t Log2SEW; |
| 34574 | uint8_t LMUL; |
| 34575 | uint8_t IndexLMUL; |
| 34576 | }; |
| 34577 | KeyType Key = {NF, Masked, Ordered, Log2SEW, LMUL, IndexLMUL}; |
| 34578 | struct Comp { |
| 34579 | bool operator()(const VSXSEGPseudo &LHS, const KeyType &RHS) const { |
| 34580 | if (LHS.NF < RHS.NF) |
| 34581 | return true; |
| 34582 | if (LHS.NF > RHS.NF) |
| 34583 | return false; |
| 34584 | if (LHS.Masked < RHS.Masked) |
| 34585 | return true; |
| 34586 | if (LHS.Masked > RHS.Masked) |
| 34587 | return false; |
| 34588 | if (LHS.Ordered < RHS.Ordered) |
| 34589 | return true; |
| 34590 | if (LHS.Ordered > RHS.Ordered) |
| 34591 | return false; |
| 34592 | if (LHS.Log2SEW < RHS.Log2SEW) |
| 34593 | return true; |
| 34594 | if (LHS.Log2SEW > RHS.Log2SEW) |
| 34595 | return false; |
| 34596 | if (LHS.LMUL < RHS.LMUL) |
| 34597 | return true; |
| 34598 | if (LHS.LMUL > RHS.LMUL) |
| 34599 | return false; |
| 34600 | if (LHS.IndexLMUL < RHS.IndexLMUL) |
| 34601 | return true; |
| 34602 | if (LHS.IndexLMUL > RHS.IndexLMUL) |
| 34603 | return false; |
| 34604 | return false; |
| 34605 | } |
| 34606 | }; |
| 34607 | auto Table = ArrayRef(RISCVVSXSEGTable); |
| 34608 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 34609 | if (Idx == Table.end() || |
| 34610 | Key.NF != Idx->NF || |
| 34611 | Key.Masked != Idx->Masked || |
| 34612 | Key.Ordered != Idx->Ordered || |
| 34613 | Key.Log2SEW != Idx->Log2SEW || |
| 34614 | Key.LMUL != Idx->LMUL || |
| 34615 | Key.IndexLMUL != Idx->IndexLMUL) |
| 34616 | return nullptr; |
| 34617 | |
| 34618 | return &*Idx; |
| 34619 | } |
| 34620 | #endif |
| 34621 | |
| 34622 | #ifdef GET_RISCVVSXTable_DECL |
| 34623 | const VLX_VSXPseudo *getVSXPseudo(uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL); |
| 34624 | #endif |
| 34625 | |
| 34626 | #ifdef GET_RISCVVSXTable_IMPL |
| 34627 | constexpr VLX_VSXPseudo RISCVVSXTable[] = { |
| 34628 | { 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXEI8_V_M1_M1 }, // 0 |
| 34629 | { 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXEI8_V_MF8_M1 }, // 1 |
| 34630 | { 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXEI8_V_MF4_M1 }, // 2 |
| 34631 | { 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXEI8_V_MF2_M1 }, // 3 |
| 34632 | { 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVSUXEI8_V_M1_M2 }, // 4 |
| 34633 | { 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVSUXEI8_V_M2_M2 }, // 5 |
| 34634 | { 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVSUXEI8_V_MF4_M2 }, // 6 |
| 34635 | { 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVSUXEI8_V_MF2_M2 }, // 7 |
| 34636 | { 0x0, 0x0, 0x3, 0x2, 0x0, PseudoVSUXEI8_V_M1_M4 }, // 8 |
| 34637 | { 0x0, 0x0, 0x3, 0x2, 0x1, PseudoVSUXEI8_V_M2_M4 }, // 9 |
| 34638 | { 0x0, 0x0, 0x3, 0x2, 0x2, PseudoVSUXEI8_V_M4_M4 }, // 10 |
| 34639 | { 0x0, 0x0, 0x3, 0x2, 0x7, PseudoVSUXEI8_V_MF2_M4 }, // 11 |
| 34640 | { 0x0, 0x0, 0x3, 0x3, 0x0, PseudoVSUXEI8_V_M1_M8 }, // 12 |
| 34641 | { 0x0, 0x0, 0x3, 0x3, 0x1, PseudoVSUXEI8_V_M2_M8 }, // 13 |
| 34642 | { 0x0, 0x0, 0x3, 0x3, 0x2, PseudoVSUXEI8_V_M4_M8 }, // 14 |
| 34643 | { 0x0, 0x0, 0x3, 0x3, 0x3, PseudoVSUXEI8_V_M8_M8 }, // 15 |
| 34644 | { 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXEI8_V_MF8_MF8 }, // 16 |
| 34645 | { 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXEI8_V_MF8_MF4 }, // 17 |
| 34646 | { 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXEI8_V_MF4_MF4 }, // 18 |
| 34647 | { 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXEI8_V_MF8_MF2 }, // 19 |
| 34648 | { 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXEI8_V_MF4_MF2 }, // 20 |
| 34649 | { 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXEI8_V_MF2_MF2 }, // 21 |
| 34650 | { 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXEI16_V_M1_M1 }, // 22 |
| 34651 | { 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXEI16_V_M2_M1 }, // 23 |
| 34652 | { 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXEI16_V_MF4_M1 }, // 24 |
| 34653 | { 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXEI16_V_MF2_M1 }, // 25 |
| 34654 | { 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVSUXEI16_V_M1_M2 }, // 26 |
| 34655 | { 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVSUXEI16_V_M2_M2 }, // 27 |
| 34656 | { 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVSUXEI16_V_M4_M2 }, // 28 |
| 34657 | { 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVSUXEI16_V_MF2_M2 }, // 29 |
| 34658 | { 0x0, 0x0, 0x4, 0x2, 0x0, PseudoVSUXEI16_V_M1_M4 }, // 30 |
| 34659 | { 0x0, 0x0, 0x4, 0x2, 0x1, PseudoVSUXEI16_V_M2_M4 }, // 31 |
| 34660 | { 0x0, 0x0, 0x4, 0x2, 0x2, PseudoVSUXEI16_V_M4_M4 }, // 32 |
| 34661 | { 0x0, 0x0, 0x4, 0x2, 0x3, PseudoVSUXEI16_V_M8_M4 }, // 33 |
| 34662 | { 0x0, 0x0, 0x4, 0x3, 0x1, PseudoVSUXEI16_V_M2_M8 }, // 34 |
| 34663 | { 0x0, 0x0, 0x4, 0x3, 0x2, PseudoVSUXEI16_V_M4_M8 }, // 35 |
| 34664 | { 0x0, 0x0, 0x4, 0x3, 0x3, PseudoVSUXEI16_V_M8_M8 }, // 36 |
| 34665 | { 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXEI16_V_MF4_MF8 }, // 37 |
| 34666 | { 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXEI16_V_MF4_MF4 }, // 38 |
| 34667 | { 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXEI16_V_MF2_MF4 }, // 39 |
| 34668 | { 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXEI16_V_M1_MF2 }, // 40 |
| 34669 | { 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXEI16_V_MF4_MF2 }, // 41 |
| 34670 | { 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXEI16_V_MF2_MF2 }, // 42 |
| 34671 | { 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXEI32_V_M1_M1 }, // 43 |
| 34672 | { 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXEI32_V_M2_M1 }, // 44 |
| 34673 | { 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXEI32_V_M4_M1 }, // 45 |
| 34674 | { 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXEI32_V_MF2_M1 }, // 46 |
| 34675 | { 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVSUXEI32_V_M1_M2 }, // 47 |
| 34676 | { 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVSUXEI32_V_M2_M2 }, // 48 |
| 34677 | { 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVSUXEI32_V_M4_M2 }, // 49 |
| 34678 | { 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVSUXEI32_V_M8_M2 }, // 50 |
| 34679 | { 0x0, 0x0, 0x5, 0x2, 0x1, PseudoVSUXEI32_V_M2_M4 }, // 51 |
| 34680 | { 0x0, 0x0, 0x5, 0x2, 0x2, PseudoVSUXEI32_V_M4_M4 }, // 52 |
| 34681 | { 0x0, 0x0, 0x5, 0x2, 0x3, PseudoVSUXEI32_V_M8_M4 }, // 53 |
| 34682 | { 0x0, 0x0, 0x5, 0x3, 0x2, PseudoVSUXEI32_V_M4_M8 }, // 54 |
| 34683 | { 0x0, 0x0, 0x5, 0x3, 0x3, PseudoVSUXEI32_V_M8_M8 }, // 55 |
| 34684 | { 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXEI32_V_MF2_MF8 }, // 56 |
| 34685 | { 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXEI32_V_M1_MF4 }, // 57 |
| 34686 | { 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXEI32_V_MF2_MF4 }, // 58 |
| 34687 | { 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXEI32_V_M1_MF2 }, // 59 |
| 34688 | { 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXEI32_V_M2_MF2 }, // 60 |
| 34689 | { 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXEI32_V_MF2_MF2 }, // 61 |
| 34690 | { 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXEI64_V_M1_M1 }, // 62 |
| 34691 | { 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXEI64_V_M2_M1 }, // 63 |
| 34692 | { 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXEI64_V_M4_M1 }, // 64 |
| 34693 | { 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXEI64_V_M8_M1 }, // 65 |
| 34694 | { 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVSUXEI64_V_M2_M2 }, // 66 |
| 34695 | { 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVSUXEI64_V_M4_M2 }, // 67 |
| 34696 | { 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVSUXEI64_V_M8_M2 }, // 68 |
| 34697 | { 0x0, 0x0, 0x6, 0x2, 0x2, PseudoVSUXEI64_V_M4_M4 }, // 69 |
| 34698 | { 0x0, 0x0, 0x6, 0x2, 0x3, PseudoVSUXEI64_V_M8_M4 }, // 70 |
| 34699 | { 0x0, 0x0, 0x6, 0x3, 0x3, PseudoVSUXEI64_V_M8_M8 }, // 71 |
| 34700 | { 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXEI64_V_M1_MF8 }, // 72 |
| 34701 | { 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXEI64_V_M1_MF4 }, // 73 |
| 34702 | { 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXEI64_V_M2_MF4 }, // 74 |
| 34703 | { 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXEI64_V_M1_MF2 }, // 75 |
| 34704 | { 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXEI64_V_M2_MF2 }, // 76 |
| 34705 | { 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXEI64_V_M4_MF2 }, // 77 |
| 34706 | { 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXEI8_V_M1_M1 }, // 78 |
| 34707 | { 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXEI8_V_MF8_M1 }, // 79 |
| 34708 | { 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXEI8_V_MF4_M1 }, // 80 |
| 34709 | { 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXEI8_V_MF2_M1 }, // 81 |
| 34710 | { 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVSOXEI8_V_M1_M2 }, // 82 |
| 34711 | { 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVSOXEI8_V_M2_M2 }, // 83 |
| 34712 | { 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVSOXEI8_V_MF4_M2 }, // 84 |
| 34713 | { 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVSOXEI8_V_MF2_M2 }, // 85 |
| 34714 | { 0x0, 0x1, 0x3, 0x2, 0x0, PseudoVSOXEI8_V_M1_M4 }, // 86 |
| 34715 | { 0x0, 0x1, 0x3, 0x2, 0x1, PseudoVSOXEI8_V_M2_M4 }, // 87 |
| 34716 | { 0x0, 0x1, 0x3, 0x2, 0x2, PseudoVSOXEI8_V_M4_M4 }, // 88 |
| 34717 | { 0x0, 0x1, 0x3, 0x2, 0x7, PseudoVSOXEI8_V_MF2_M4 }, // 89 |
| 34718 | { 0x0, 0x1, 0x3, 0x3, 0x0, PseudoVSOXEI8_V_M1_M8 }, // 90 |
| 34719 | { 0x0, 0x1, 0x3, 0x3, 0x1, PseudoVSOXEI8_V_M2_M8 }, // 91 |
| 34720 | { 0x0, 0x1, 0x3, 0x3, 0x2, PseudoVSOXEI8_V_M4_M8 }, // 92 |
| 34721 | { 0x0, 0x1, 0x3, 0x3, 0x3, PseudoVSOXEI8_V_M8_M8 }, // 93 |
| 34722 | { 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXEI8_V_MF8_MF8 }, // 94 |
| 34723 | { 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXEI8_V_MF8_MF4 }, // 95 |
| 34724 | { 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXEI8_V_MF4_MF4 }, // 96 |
| 34725 | { 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXEI8_V_MF8_MF2 }, // 97 |
| 34726 | { 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXEI8_V_MF4_MF2 }, // 98 |
| 34727 | { 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXEI8_V_MF2_MF2 }, // 99 |
| 34728 | { 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXEI16_V_M1_M1 }, // 100 |
| 34729 | { 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXEI16_V_M2_M1 }, // 101 |
| 34730 | { 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXEI16_V_MF4_M1 }, // 102 |
| 34731 | { 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXEI16_V_MF2_M1 }, // 103 |
| 34732 | { 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVSOXEI16_V_M1_M2 }, // 104 |
| 34733 | { 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVSOXEI16_V_M2_M2 }, // 105 |
| 34734 | { 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVSOXEI16_V_M4_M2 }, // 106 |
| 34735 | { 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVSOXEI16_V_MF2_M2 }, // 107 |
| 34736 | { 0x0, 0x1, 0x4, 0x2, 0x0, PseudoVSOXEI16_V_M1_M4 }, // 108 |
| 34737 | { 0x0, 0x1, 0x4, 0x2, 0x1, PseudoVSOXEI16_V_M2_M4 }, // 109 |
| 34738 | { 0x0, 0x1, 0x4, 0x2, 0x2, PseudoVSOXEI16_V_M4_M4 }, // 110 |
| 34739 | { 0x0, 0x1, 0x4, 0x2, 0x3, PseudoVSOXEI16_V_M8_M4 }, // 111 |
| 34740 | { 0x0, 0x1, 0x4, 0x3, 0x1, PseudoVSOXEI16_V_M2_M8 }, // 112 |
| 34741 | { 0x0, 0x1, 0x4, 0x3, 0x2, PseudoVSOXEI16_V_M4_M8 }, // 113 |
| 34742 | { 0x0, 0x1, 0x4, 0x3, 0x3, PseudoVSOXEI16_V_M8_M8 }, // 114 |
| 34743 | { 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXEI16_V_MF4_MF8 }, // 115 |
| 34744 | { 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXEI16_V_MF4_MF4 }, // 116 |
| 34745 | { 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXEI16_V_MF2_MF4 }, // 117 |
| 34746 | { 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXEI16_V_M1_MF2 }, // 118 |
| 34747 | { 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXEI16_V_MF4_MF2 }, // 119 |
| 34748 | { 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXEI16_V_MF2_MF2 }, // 120 |
| 34749 | { 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXEI32_V_M1_M1 }, // 121 |
| 34750 | { 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXEI32_V_M2_M1 }, // 122 |
| 34751 | { 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXEI32_V_M4_M1 }, // 123 |
| 34752 | { 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXEI32_V_MF2_M1 }, // 124 |
| 34753 | { 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVSOXEI32_V_M1_M2 }, // 125 |
| 34754 | { 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVSOXEI32_V_M2_M2 }, // 126 |
| 34755 | { 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVSOXEI32_V_M4_M2 }, // 127 |
| 34756 | { 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVSOXEI32_V_M8_M2 }, // 128 |
| 34757 | { 0x0, 0x1, 0x5, 0x2, 0x1, PseudoVSOXEI32_V_M2_M4 }, // 129 |
| 34758 | { 0x0, 0x1, 0x5, 0x2, 0x2, PseudoVSOXEI32_V_M4_M4 }, // 130 |
| 34759 | { 0x0, 0x1, 0x5, 0x2, 0x3, PseudoVSOXEI32_V_M8_M4 }, // 131 |
| 34760 | { 0x0, 0x1, 0x5, 0x3, 0x2, PseudoVSOXEI32_V_M4_M8 }, // 132 |
| 34761 | { 0x0, 0x1, 0x5, 0x3, 0x3, PseudoVSOXEI32_V_M8_M8 }, // 133 |
| 34762 | { 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXEI32_V_MF2_MF8 }, // 134 |
| 34763 | { 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXEI32_V_M1_MF4 }, // 135 |
| 34764 | { 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXEI32_V_MF2_MF4 }, // 136 |
| 34765 | { 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXEI32_V_M1_MF2 }, // 137 |
| 34766 | { 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXEI32_V_M2_MF2 }, // 138 |
| 34767 | { 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXEI32_V_MF2_MF2 }, // 139 |
| 34768 | { 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXEI64_V_M1_M1 }, // 140 |
| 34769 | { 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXEI64_V_M2_M1 }, // 141 |
| 34770 | { 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXEI64_V_M4_M1 }, // 142 |
| 34771 | { 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXEI64_V_M8_M1 }, // 143 |
| 34772 | { 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVSOXEI64_V_M2_M2 }, // 144 |
| 34773 | { 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVSOXEI64_V_M4_M2 }, // 145 |
| 34774 | { 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVSOXEI64_V_M8_M2 }, // 146 |
| 34775 | { 0x0, 0x1, 0x6, 0x2, 0x2, PseudoVSOXEI64_V_M4_M4 }, // 147 |
| 34776 | { 0x0, 0x1, 0x6, 0x2, 0x3, PseudoVSOXEI64_V_M8_M4 }, // 148 |
| 34777 | { 0x0, 0x1, 0x6, 0x3, 0x3, PseudoVSOXEI64_V_M8_M8 }, // 149 |
| 34778 | { 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXEI64_V_M1_MF8 }, // 150 |
| 34779 | { 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXEI64_V_M1_MF4 }, // 151 |
| 34780 | { 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXEI64_V_M2_MF4 }, // 152 |
| 34781 | { 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXEI64_V_M1_MF2 }, // 153 |
| 34782 | { 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXEI64_V_M2_MF2 }, // 154 |
| 34783 | { 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXEI64_V_M4_MF2 }, // 155 |
| 34784 | { 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXEI8_V_M1_M1_MASK }, // 156 |
| 34785 | { 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXEI8_V_MF8_M1_MASK }, // 157 |
| 34786 | { 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXEI8_V_MF4_M1_MASK }, // 158 |
| 34787 | { 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXEI8_V_MF2_M1_MASK }, // 159 |
| 34788 | { 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVSUXEI8_V_M1_M2_MASK }, // 160 |
| 34789 | { 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVSUXEI8_V_M2_M2_MASK }, // 161 |
| 34790 | { 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVSUXEI8_V_MF4_M2_MASK }, // 162 |
| 34791 | { 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVSUXEI8_V_MF2_M2_MASK }, // 163 |
| 34792 | { 0x1, 0x0, 0x3, 0x2, 0x0, PseudoVSUXEI8_V_M1_M4_MASK }, // 164 |
| 34793 | { 0x1, 0x0, 0x3, 0x2, 0x1, PseudoVSUXEI8_V_M2_M4_MASK }, // 165 |
| 34794 | { 0x1, 0x0, 0x3, 0x2, 0x2, PseudoVSUXEI8_V_M4_M4_MASK }, // 166 |
| 34795 | { 0x1, 0x0, 0x3, 0x2, 0x7, PseudoVSUXEI8_V_MF2_M4_MASK }, // 167 |
| 34796 | { 0x1, 0x0, 0x3, 0x3, 0x0, PseudoVSUXEI8_V_M1_M8_MASK }, // 168 |
| 34797 | { 0x1, 0x0, 0x3, 0x3, 0x1, PseudoVSUXEI8_V_M2_M8_MASK }, // 169 |
| 34798 | { 0x1, 0x0, 0x3, 0x3, 0x2, PseudoVSUXEI8_V_M4_M8_MASK }, // 170 |
| 34799 | { 0x1, 0x0, 0x3, 0x3, 0x3, PseudoVSUXEI8_V_M8_M8_MASK }, // 171 |
| 34800 | { 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXEI8_V_MF8_MF8_MASK }, // 172 |
| 34801 | { 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXEI8_V_MF8_MF4_MASK }, // 173 |
| 34802 | { 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXEI8_V_MF4_MF4_MASK }, // 174 |
| 34803 | { 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXEI8_V_MF8_MF2_MASK }, // 175 |
| 34804 | { 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXEI8_V_MF4_MF2_MASK }, // 176 |
| 34805 | { 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXEI8_V_MF2_MF2_MASK }, // 177 |
| 34806 | { 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXEI16_V_M1_M1_MASK }, // 178 |
| 34807 | { 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXEI16_V_M2_M1_MASK }, // 179 |
| 34808 | { 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXEI16_V_MF4_M1_MASK }, // 180 |
| 34809 | { 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXEI16_V_MF2_M1_MASK }, // 181 |
| 34810 | { 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVSUXEI16_V_M1_M2_MASK }, // 182 |
| 34811 | { 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVSUXEI16_V_M2_M2_MASK }, // 183 |
| 34812 | { 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVSUXEI16_V_M4_M2_MASK }, // 184 |
| 34813 | { 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVSUXEI16_V_MF2_M2_MASK }, // 185 |
| 34814 | { 0x1, 0x0, 0x4, 0x2, 0x0, PseudoVSUXEI16_V_M1_M4_MASK }, // 186 |
| 34815 | { 0x1, 0x0, 0x4, 0x2, 0x1, PseudoVSUXEI16_V_M2_M4_MASK }, // 187 |
| 34816 | { 0x1, 0x0, 0x4, 0x2, 0x2, PseudoVSUXEI16_V_M4_M4_MASK }, // 188 |
| 34817 | { 0x1, 0x0, 0x4, 0x2, 0x3, PseudoVSUXEI16_V_M8_M4_MASK }, // 189 |
| 34818 | { 0x1, 0x0, 0x4, 0x3, 0x1, PseudoVSUXEI16_V_M2_M8_MASK }, // 190 |
| 34819 | { 0x1, 0x0, 0x4, 0x3, 0x2, PseudoVSUXEI16_V_M4_M8_MASK }, // 191 |
| 34820 | { 0x1, 0x0, 0x4, 0x3, 0x3, PseudoVSUXEI16_V_M8_M8_MASK }, // 192 |
| 34821 | { 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXEI16_V_MF4_MF8_MASK }, // 193 |
| 34822 | { 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXEI16_V_MF4_MF4_MASK }, // 194 |
| 34823 | { 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXEI16_V_MF2_MF4_MASK }, // 195 |
| 34824 | { 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXEI16_V_M1_MF2_MASK }, // 196 |
| 34825 | { 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXEI16_V_MF4_MF2_MASK }, // 197 |
| 34826 | { 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXEI16_V_MF2_MF2_MASK }, // 198 |
| 34827 | { 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXEI32_V_M1_M1_MASK }, // 199 |
| 34828 | { 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXEI32_V_M2_M1_MASK }, // 200 |
| 34829 | { 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXEI32_V_M4_M1_MASK }, // 201 |
| 34830 | { 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXEI32_V_MF2_M1_MASK }, // 202 |
| 34831 | { 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVSUXEI32_V_M1_M2_MASK }, // 203 |
| 34832 | { 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVSUXEI32_V_M2_M2_MASK }, // 204 |
| 34833 | { 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVSUXEI32_V_M4_M2_MASK }, // 205 |
| 34834 | { 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVSUXEI32_V_M8_M2_MASK }, // 206 |
| 34835 | { 0x1, 0x0, 0x5, 0x2, 0x1, PseudoVSUXEI32_V_M2_M4_MASK }, // 207 |
| 34836 | { 0x1, 0x0, 0x5, 0x2, 0x2, PseudoVSUXEI32_V_M4_M4_MASK }, // 208 |
| 34837 | { 0x1, 0x0, 0x5, 0x2, 0x3, PseudoVSUXEI32_V_M8_M4_MASK }, // 209 |
| 34838 | { 0x1, 0x0, 0x5, 0x3, 0x2, PseudoVSUXEI32_V_M4_M8_MASK }, // 210 |
| 34839 | { 0x1, 0x0, 0x5, 0x3, 0x3, PseudoVSUXEI32_V_M8_M8_MASK }, // 211 |
| 34840 | { 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXEI32_V_MF2_MF8_MASK }, // 212 |
| 34841 | { 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXEI32_V_M1_MF4_MASK }, // 213 |
| 34842 | { 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXEI32_V_MF2_MF4_MASK }, // 214 |
| 34843 | { 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXEI32_V_M1_MF2_MASK }, // 215 |
| 34844 | { 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXEI32_V_M2_MF2_MASK }, // 216 |
| 34845 | { 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXEI32_V_MF2_MF2_MASK }, // 217 |
| 34846 | { 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXEI64_V_M1_M1_MASK }, // 218 |
| 34847 | { 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXEI64_V_M2_M1_MASK }, // 219 |
| 34848 | { 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXEI64_V_M4_M1_MASK }, // 220 |
| 34849 | { 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXEI64_V_M8_M1_MASK }, // 221 |
| 34850 | { 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVSUXEI64_V_M2_M2_MASK }, // 222 |
| 34851 | { 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVSUXEI64_V_M4_M2_MASK }, // 223 |
| 34852 | { 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVSUXEI64_V_M8_M2_MASK }, // 224 |
| 34853 | { 0x1, 0x0, 0x6, 0x2, 0x2, PseudoVSUXEI64_V_M4_M4_MASK }, // 225 |
| 34854 | { 0x1, 0x0, 0x6, 0x2, 0x3, PseudoVSUXEI64_V_M8_M4_MASK }, // 226 |
| 34855 | { 0x1, 0x0, 0x6, 0x3, 0x3, PseudoVSUXEI64_V_M8_M8_MASK }, // 227 |
| 34856 | { 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXEI64_V_M1_MF8_MASK }, // 228 |
| 34857 | { 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXEI64_V_M1_MF4_MASK }, // 229 |
| 34858 | { 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXEI64_V_M2_MF4_MASK }, // 230 |
| 34859 | { 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXEI64_V_M1_MF2_MASK }, // 231 |
| 34860 | { 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXEI64_V_M2_MF2_MASK }, // 232 |
| 34861 | { 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXEI64_V_M4_MF2_MASK }, // 233 |
| 34862 | { 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXEI8_V_M1_M1_MASK }, // 234 |
| 34863 | { 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXEI8_V_MF8_M1_MASK }, // 235 |
| 34864 | { 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXEI8_V_MF4_M1_MASK }, // 236 |
| 34865 | { 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXEI8_V_MF2_M1_MASK }, // 237 |
| 34866 | { 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVSOXEI8_V_M1_M2_MASK }, // 238 |
| 34867 | { 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVSOXEI8_V_M2_M2_MASK }, // 239 |
| 34868 | { 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVSOXEI8_V_MF4_M2_MASK }, // 240 |
| 34869 | { 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVSOXEI8_V_MF2_M2_MASK }, // 241 |
| 34870 | { 0x1, 0x1, 0x3, 0x2, 0x0, PseudoVSOXEI8_V_M1_M4_MASK }, // 242 |
| 34871 | { 0x1, 0x1, 0x3, 0x2, 0x1, PseudoVSOXEI8_V_M2_M4_MASK }, // 243 |
| 34872 | { 0x1, 0x1, 0x3, 0x2, 0x2, PseudoVSOXEI8_V_M4_M4_MASK }, // 244 |
| 34873 | { 0x1, 0x1, 0x3, 0x2, 0x7, PseudoVSOXEI8_V_MF2_M4_MASK }, // 245 |
| 34874 | { 0x1, 0x1, 0x3, 0x3, 0x0, PseudoVSOXEI8_V_M1_M8_MASK }, // 246 |
| 34875 | { 0x1, 0x1, 0x3, 0x3, 0x1, PseudoVSOXEI8_V_M2_M8_MASK }, // 247 |
| 34876 | { 0x1, 0x1, 0x3, 0x3, 0x2, PseudoVSOXEI8_V_M4_M8_MASK }, // 248 |
| 34877 | { 0x1, 0x1, 0x3, 0x3, 0x3, PseudoVSOXEI8_V_M8_M8_MASK }, // 249 |
| 34878 | { 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXEI8_V_MF8_MF8_MASK }, // 250 |
| 34879 | { 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXEI8_V_MF8_MF4_MASK }, // 251 |
| 34880 | { 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXEI8_V_MF4_MF4_MASK }, // 252 |
| 34881 | { 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXEI8_V_MF8_MF2_MASK }, // 253 |
| 34882 | { 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXEI8_V_MF4_MF2_MASK }, // 254 |
| 34883 | { 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXEI8_V_MF2_MF2_MASK }, // 255 |
| 34884 | { 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXEI16_V_M1_M1_MASK }, // 256 |
| 34885 | { 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXEI16_V_M2_M1_MASK }, // 257 |
| 34886 | { 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXEI16_V_MF4_M1_MASK }, // 258 |
| 34887 | { 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXEI16_V_MF2_M1_MASK }, // 259 |
| 34888 | { 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVSOXEI16_V_M1_M2_MASK }, // 260 |
| 34889 | { 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVSOXEI16_V_M2_M2_MASK }, // 261 |
| 34890 | { 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVSOXEI16_V_M4_M2_MASK }, // 262 |
| 34891 | { 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVSOXEI16_V_MF2_M2_MASK }, // 263 |
| 34892 | { 0x1, 0x1, 0x4, 0x2, 0x0, PseudoVSOXEI16_V_M1_M4_MASK }, // 264 |
| 34893 | { 0x1, 0x1, 0x4, 0x2, 0x1, PseudoVSOXEI16_V_M2_M4_MASK }, // 265 |
| 34894 | { 0x1, 0x1, 0x4, 0x2, 0x2, PseudoVSOXEI16_V_M4_M4_MASK }, // 266 |
| 34895 | { 0x1, 0x1, 0x4, 0x2, 0x3, PseudoVSOXEI16_V_M8_M4_MASK }, // 267 |
| 34896 | { 0x1, 0x1, 0x4, 0x3, 0x1, PseudoVSOXEI16_V_M2_M8_MASK }, // 268 |
| 34897 | { 0x1, 0x1, 0x4, 0x3, 0x2, PseudoVSOXEI16_V_M4_M8_MASK }, // 269 |
| 34898 | { 0x1, 0x1, 0x4, 0x3, 0x3, PseudoVSOXEI16_V_M8_M8_MASK }, // 270 |
| 34899 | { 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXEI16_V_MF4_MF8_MASK }, // 271 |
| 34900 | { 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXEI16_V_MF4_MF4_MASK }, // 272 |
| 34901 | { 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXEI16_V_MF2_MF4_MASK }, // 273 |
| 34902 | { 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXEI16_V_M1_MF2_MASK }, // 274 |
| 34903 | { 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXEI16_V_MF4_MF2_MASK }, // 275 |
| 34904 | { 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXEI16_V_MF2_MF2_MASK }, // 276 |
| 34905 | { 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXEI32_V_M1_M1_MASK }, // 277 |
| 34906 | { 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXEI32_V_M2_M1_MASK }, // 278 |
| 34907 | { 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXEI32_V_M4_M1_MASK }, // 279 |
| 34908 | { 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXEI32_V_MF2_M1_MASK }, // 280 |
| 34909 | { 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVSOXEI32_V_M1_M2_MASK }, // 281 |
| 34910 | { 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVSOXEI32_V_M2_M2_MASK }, // 282 |
| 34911 | { 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVSOXEI32_V_M4_M2_MASK }, // 283 |
| 34912 | { 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVSOXEI32_V_M8_M2_MASK }, // 284 |
| 34913 | { 0x1, 0x1, 0x5, 0x2, 0x1, PseudoVSOXEI32_V_M2_M4_MASK }, // 285 |
| 34914 | { 0x1, 0x1, 0x5, 0x2, 0x2, PseudoVSOXEI32_V_M4_M4_MASK }, // 286 |
| 34915 | { 0x1, 0x1, 0x5, 0x2, 0x3, PseudoVSOXEI32_V_M8_M4_MASK }, // 287 |
| 34916 | { 0x1, 0x1, 0x5, 0x3, 0x2, PseudoVSOXEI32_V_M4_M8_MASK }, // 288 |
| 34917 | { 0x1, 0x1, 0x5, 0x3, 0x3, PseudoVSOXEI32_V_M8_M8_MASK }, // 289 |
| 34918 | { 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXEI32_V_MF2_MF8_MASK }, // 290 |
| 34919 | { 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXEI32_V_M1_MF4_MASK }, // 291 |
| 34920 | { 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXEI32_V_MF2_MF4_MASK }, // 292 |
| 34921 | { 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXEI32_V_M1_MF2_MASK }, // 293 |
| 34922 | { 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXEI32_V_M2_MF2_MASK }, // 294 |
| 34923 | { 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXEI32_V_MF2_MF2_MASK }, // 295 |
| 34924 | { 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXEI64_V_M1_M1_MASK }, // 296 |
| 34925 | { 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXEI64_V_M2_M1_MASK }, // 297 |
| 34926 | { 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXEI64_V_M4_M1_MASK }, // 298 |
| 34927 | { 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXEI64_V_M8_M1_MASK }, // 299 |
| 34928 | { 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVSOXEI64_V_M2_M2_MASK }, // 300 |
| 34929 | { 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVSOXEI64_V_M4_M2_MASK }, // 301 |
| 34930 | { 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVSOXEI64_V_M8_M2_MASK }, // 302 |
| 34931 | { 0x1, 0x1, 0x6, 0x2, 0x2, PseudoVSOXEI64_V_M4_M4_MASK }, // 303 |
| 34932 | { 0x1, 0x1, 0x6, 0x2, 0x3, PseudoVSOXEI64_V_M8_M4_MASK }, // 304 |
| 34933 | { 0x1, 0x1, 0x6, 0x3, 0x3, PseudoVSOXEI64_V_M8_M8_MASK }, // 305 |
| 34934 | { 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXEI64_V_M1_MF8_MASK }, // 306 |
| 34935 | { 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXEI64_V_M1_MF4_MASK }, // 307 |
| 34936 | { 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXEI64_V_M2_MF4_MASK }, // 308 |
| 34937 | { 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXEI64_V_M1_MF2_MASK }, // 309 |
| 34938 | { 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXEI64_V_M2_MF2_MASK }, // 310 |
| 34939 | { 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXEI64_V_M4_MF2_MASK }, // 311 |
| 34940 | }; |
| 34941 | |
| 34942 | const VLX_VSXPseudo *getVSXPseudo(uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL) { |
| 34943 | struct KeyType { |
| 34944 | uint8_t Masked; |
| 34945 | uint8_t Ordered; |
| 34946 | uint8_t Log2SEW; |
| 34947 | uint8_t LMUL; |
| 34948 | uint8_t IndexLMUL; |
| 34949 | }; |
| 34950 | KeyType Key = {Masked, Ordered, Log2SEW, LMUL, IndexLMUL}; |
| 34951 | struct Comp { |
| 34952 | bool operator()(const VLX_VSXPseudo &LHS, const KeyType &RHS) const { |
| 34953 | if (LHS.Masked < RHS.Masked) |
| 34954 | return true; |
| 34955 | if (LHS.Masked > RHS.Masked) |
| 34956 | return false; |
| 34957 | if (LHS.Ordered < RHS.Ordered) |
| 34958 | return true; |
| 34959 | if (LHS.Ordered > RHS.Ordered) |
| 34960 | return false; |
| 34961 | if (LHS.Log2SEW < RHS.Log2SEW) |
| 34962 | return true; |
| 34963 | if (LHS.Log2SEW > RHS.Log2SEW) |
| 34964 | return false; |
| 34965 | if (LHS.LMUL < RHS.LMUL) |
| 34966 | return true; |
| 34967 | if (LHS.LMUL > RHS.LMUL) |
| 34968 | return false; |
| 34969 | if (LHS.IndexLMUL < RHS.IndexLMUL) |
| 34970 | return true; |
| 34971 | if (LHS.IndexLMUL > RHS.IndexLMUL) |
| 34972 | return false; |
| 34973 | return false; |
| 34974 | } |
| 34975 | }; |
| 34976 | auto Table = ArrayRef(RISCVVSXTable); |
| 34977 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 34978 | if (Idx == Table.end() || |
| 34979 | Key.Masked != Idx->Masked || |
| 34980 | Key.Ordered != Idx->Ordered || |
| 34981 | Key.Log2SEW != Idx->Log2SEW || |
| 34982 | Key.LMUL != Idx->LMUL || |
| 34983 | Key.IndexLMUL != Idx->IndexLMUL) |
| 34984 | return nullptr; |
| 34985 | |
| 34986 | return &*Idx; |
| 34987 | } |
| 34988 | #endif |
| 34989 | |
| 34990 | #ifdef GET_SysRegsList_DECL |
| 34991 | llvm::iterator_range<const SysReg *> lookupSysRegByEncoding(uint16_t Encoding); |
| 34992 | const SysReg *lookupSysRegByAltName(StringRef AltName); |
| 34993 | const SysReg *lookupSysRegByDeprecatedName(StringRef DeprecatedName); |
| 34994 | const SysReg *lookupSysRegByName(StringRef Name); |
| 34995 | #endif |
| 34996 | |
| 34997 | #ifdef GET_SysRegsList_IMPL |
| 34998 | constexpr SysReg SysRegsList[] = { |
| 34999 | { "fflags", "fflags", "", 0x1, {} , false }, // 0 |
| 35000 | { "frm", "frm", "", 0x2, {} , false }, // 1 |
| 35001 | { "fcsr", "fcsr", "", 0x3, {} , false }, // 2 |
| 35002 | { "vstart", "vstart", "", 0x8, {} , false }, // 3 |
| 35003 | { "vxsat", "vxsat", "", 0x9, {} , false }, // 4 |
| 35004 | { "vxrm", "vxrm", "", 0xA, {} , false }, // 5 |
| 35005 | { "vcsr", "vcsr", "", 0xF, {} , false }, // 6 |
| 35006 | { "ssp", "ssp", "", 0x11, {} , false }, // 7 |
| 35007 | { "seed", "seed", "", 0x15, {} , false }, // 8 |
| 35008 | { "jvt", "jvt", "", 0x17, {} , false }, // 9 |
| 35009 | { "sstatus", "sstatus", "", 0x100, {} , false }, // 10 |
| 35010 | { "sie", "sie", "", 0x104, {} , false }, // 11 |
| 35011 | { "stvec", "stvec", "", 0x105, {} , false }, // 12 |
| 35012 | { "scounteren", "scounteren", "", 0x106, {} , false }, // 13 |
| 35013 | { "senvcfg", "senvcfg", "", 0x10A, {} , false }, // 14 |
| 35014 | { "sstateen0", "sstateen0", "", 0x10C, {} , false }, // 15 |
| 35015 | { "sstateen1", "sstateen1", "", 0x10D, {} , false }, // 16 |
| 35016 | { "sstateen2", "sstateen2", "", 0x10E, {} , false }, // 17 |
| 35017 | { "sstateen3", "sstateen3", "", 0x10F, {} , false }, // 18 |
| 35018 | { "sieh", "sieh", "", 0x114, {} , true }, // 19 |
| 35019 | { "scountinhibit", "scountinhibit", "", 0x120, {} , false }, // 20 |
| 35020 | { "sscratch", "sscratch", "", 0x140, {} , false }, // 21 |
| 35021 | { "sepc", "sepc", "", 0x141, {} , false }, // 22 |
| 35022 | { "scause", "scause", "", 0x142, {} , false }, // 23 |
| 35023 | { "stval", "stval", "sbadaddr", 0x143, {} , false }, // 24 |
| 35024 | { "sip", "sip", "", 0x144, {} , false }, // 25 |
| 35025 | { "stimecmp", "stimecmp", "", 0x14D, {} , false }, // 26 |
| 35026 | { "siselect", "siselect", "", 0x150, {} , false }, // 27 |
| 35027 | { "sireg", "sireg", "", 0x151, {} , false }, // 28 |
| 35028 | { "sireg2", "sireg2", "", 0x152, {} , false }, // 29 |
| 35029 | { "sireg3", "sireg3", "", 0x153, {} , false }, // 30 |
| 35030 | { "siph", "siph", "", 0x154, {} , true }, // 31 |
| 35031 | { "sireg4", "sireg4", "", 0x155, {} , false }, // 32 |
| 35032 | { "sireg5", "sireg5", "", 0x156, {} , false }, // 33 |
| 35033 | { "sireg6", "sireg6", "", 0x157, {} , false }, // 34 |
| 35034 | { "stopei", "stopei", "", 0x15C, {} , false }, // 35 |
| 35035 | { "stimecmph", "stimecmph", "", 0x15D, {} , true }, // 36 |
| 35036 | { "satp", "satp", "sptbr", 0x180, {} , false }, // 37 |
| 35037 | { "srmcfg", "srmcfg", "", 0x181, {} , false }, // 38 |
| 35038 | { "vsstatus", "vsstatus", "", 0x200, {} , false }, // 39 |
| 35039 | { "vsie", "vsie", "", 0x204, {} , false }, // 40 |
| 35040 | { "vstvec", "vstvec", "", 0x205, {} , false }, // 41 |
| 35041 | { "vsieh", "vsieh", "", 0x214, {} , true }, // 42 |
| 35042 | { "vsscratch", "vsscratch", "", 0x240, {} , false }, // 43 |
| 35043 | { "vsepc", "vsepc", "", 0x241, {} , false }, // 44 |
| 35044 | { "vscause", "vscause", "", 0x242, {} , false }, // 45 |
| 35045 | { "vstval", "vstval", "", 0x243, {} , false }, // 46 |
| 35046 | { "vsip", "vsip", "", 0x244, {} , false }, // 47 |
| 35047 | { "vstimecmp", "vstimecmp", "", 0x24D, {} , false }, // 48 |
| 35048 | { "vsiselect", "vsiselect", "", 0x250, {} , false }, // 49 |
| 35049 | { "vsireg", "vsireg", "", 0x251, {} , false }, // 50 |
| 35050 | { "vsireg2", "vsireg2", "", 0x252, {} , false }, // 51 |
| 35051 | { "vsireg3", "vsireg3", "", 0x253, {} , false }, // 52 |
| 35052 | { "vsiph", "vsiph", "", 0x254, {} , true }, // 53 |
| 35053 | { "vsireg4", "vsireg4", "", 0x255, {} , false }, // 54 |
| 35054 | { "vsireg5", "vsireg5", "", 0x256, {} , false }, // 55 |
| 35055 | { "vsireg6", "vsireg6", "", 0x257, {} , false }, // 56 |
| 35056 | { "vstopei", "vstopei", "", 0x25C, {} , false }, // 57 |
| 35057 | { "vstimecmph", "vstimecmph", "", 0x25D, {} , true }, // 58 |
| 35058 | { "vsatp", "vsatp", "", 0x280, {} , false }, // 59 |
| 35059 | { "mstatus", "mstatus", "", 0x300, {} , false }, // 60 |
| 35060 | { "misa", "misa", "", 0x301, {} , false }, // 61 |
| 35061 | { "medeleg", "medeleg", "", 0x302, {} , false }, // 62 |
| 35062 | { "mideleg", "mideleg", "", 0x303, {} , false }, // 63 |
| 35063 | { "mie", "mie", "", 0x304, {} , false }, // 64 |
| 35064 | { "mtvec", "mtvec", "", 0x305, {} , false }, // 65 |
| 35065 | { "mcounteren", "mcounteren", "", 0x306, {} , false }, // 66 |
| 35066 | { "mvien", "mvien", "", 0x308, {} , false }, // 67 |
| 35067 | { "mvip", "mvip", "", 0x309, {} , false }, // 68 |
| 35068 | { "menvcfg", "menvcfg", "", 0x30A, {} , false }, // 69 |
| 35069 | { "mstateen0", "mstateen0", "", 0x30C, {} , false }, // 70 |
| 35070 | { "mstateen1", "mstateen1", "", 0x30D, {} , false }, // 71 |
| 35071 | { "mstateen2", "mstateen2", "", 0x30E, {} , false }, // 72 |
| 35072 | { "mstateen3", "mstateen3", "", 0x30F, {} , false }, // 73 |
| 35073 | { "mstatush", "mstatush", "", 0x310, {} , true }, // 74 |
| 35074 | { "midelegh", "midelegh", "", 0x313, {} , true }, // 75 |
| 35075 | { "mieh", "mieh", "", 0x314, {} , true }, // 76 |
| 35076 | { "mvienh", "mvienh", "", 0x318, {} , true }, // 77 |
| 35077 | { "mviph", "mviph", "", 0x319, {} , true }, // 78 |
| 35078 | { "menvcfgh", "menvcfgh", "", 0x31A, {} , true }, // 79 |
| 35079 | { "mstateen0h", "mstateen0h", "", 0x31C, {} , true }, // 80 |
| 35080 | { "mstateen1h", "mstateen1h", "", 0x31D, {} , true }, // 81 |
| 35081 | { "mstateen2h", "mstateen2h", "", 0x31E, {} , true }, // 82 |
| 35082 | { "mstateen3h", "mstateen3h", "", 0x31F, {} , true }, // 83 |
| 35083 | { "mcountinhibit", "mucounteren", "", 0x320, {} , false }, // 84 |
| 35084 | { "mhpmevent3", "mhpmevent3", "", 0x323, {} , false }, // 85 |
| 35085 | { "mhpmevent4", "mhpmevent4", "", 0x324, {} , false }, // 86 |
| 35086 | { "mhpmevent5", "mhpmevent5", "", 0x325, {} , false }, // 87 |
| 35087 | { "mhpmevent6", "mhpmevent6", "", 0x326, {} , false }, // 88 |
| 35088 | { "mhpmevent7", "mhpmevent7", "", 0x327, {} , false }, // 89 |
| 35089 | { "mhpmevent8", "mhpmevent8", "", 0x328, {} , false }, // 90 |
| 35090 | { "mhpmevent9", "mhpmevent9", "", 0x329, {} , false }, // 91 |
| 35091 | { "mhpmevent10", "mhpmevent10", "", 0x32A, {} , false }, // 92 |
| 35092 | { "mhpmevent11", "mhpmevent11", "", 0x32B, {} , false }, // 93 |
| 35093 | { "mhpmevent12", "mhpmevent12", "", 0x32C, {} , false }, // 94 |
| 35094 | { "mhpmevent13", "mhpmevent13", "", 0x32D, {} , false }, // 95 |
| 35095 | { "mhpmevent14", "mhpmevent14", "", 0x32E, {} , false }, // 96 |
| 35096 | { "mhpmevent15", "mhpmevent15", "", 0x32F, {} , false }, // 97 |
| 35097 | { "mhpmevent16", "mhpmevent16", "", 0x330, {} , false }, // 98 |
| 35098 | { "mhpmevent17", "mhpmevent17", "", 0x331, {} , false }, // 99 |
| 35099 | { "mhpmevent18", "mhpmevent18", "", 0x332, {} , false }, // 100 |
| 35100 | { "mhpmevent19", "mhpmevent19", "", 0x333, {} , false }, // 101 |
| 35101 | { "mhpmevent20", "mhpmevent20", "", 0x334, {} , false }, // 102 |
| 35102 | { "mhpmevent21", "mhpmevent21", "", 0x335, {} , false }, // 103 |
| 35103 | { "mhpmevent22", "mhpmevent22", "", 0x336, {} , false }, // 104 |
| 35104 | { "mhpmevent23", "mhpmevent23", "", 0x337, {} , false }, // 105 |
| 35105 | { "mhpmevent24", "mhpmevent24", "", 0x338, {} , false }, // 106 |
| 35106 | { "mhpmevent25", "mhpmevent25", "", 0x339, {} , false }, // 107 |
| 35107 | { "mhpmevent26", "mhpmevent26", "", 0x33A, {} , false }, // 108 |
| 35108 | { "mhpmevent27", "mhpmevent27", "", 0x33B, {} , false }, // 109 |
| 35109 | { "mhpmevent28", "mhpmevent28", "", 0x33C, {} , false }, // 110 |
| 35110 | { "mhpmevent29", "mhpmevent29", "", 0x33D, {} , false }, // 111 |
| 35111 | { "mhpmevent30", "mhpmevent30", "", 0x33E, {} , false }, // 112 |
| 35112 | { "mhpmevent31", "mhpmevent31", "", 0x33F, {} , false }, // 113 |
| 35113 | { "mscratch", "mscratch", "", 0x340, {} , false }, // 114 |
| 35114 | { "mepc", "mepc", "", 0x341, {} , false }, // 115 |
| 35115 | { "mcause", "mcause", "", 0x342, {} , false }, // 116 |
| 35116 | { "mtval", "mtval", "mbadaddr", 0x343, {} , false }, // 117 |
| 35117 | { "mip", "mip", "", 0x344, {} , false }, // 118 |
| 35118 | { "mtinst", "mtinst", "", 0x34A, {} , false }, // 119 |
| 35119 | { "mtval2", "mtval2", "", 0x34B, {} , false }, // 120 |
| 35120 | { "miselect", "miselect", "", 0x350, {} , false }, // 121 |
| 35121 | { "mireg", "mireg", "", 0x351, {} , false }, // 122 |
| 35122 | { "mireg2", "mireg2", "", 0x352, {} , false }, // 123 |
| 35123 | { "mireg3", "mireg3", "", 0x353, {} , false }, // 124 |
| 35124 | { "miph", "miph", "", 0x354, {} , true }, // 125 |
| 35125 | { "mireg4", "mireg4", "", 0x355, {} , false }, // 126 |
| 35126 | { "mireg5", "mireg5", "", 0x356, {} , false }, // 127 |
| 35127 | { "mireg6", "mireg6", "", 0x357, {} , false }, // 128 |
| 35128 | { "mtopei", "mtopei", "", 0x35C, {} , false }, // 129 |
| 35129 | { "pmpcfg0", "pmpcfg0", "", 0x3A0, {} , false }, // 130 |
| 35130 | { "pmpcfg1", "pmpcfg1", "", 0x3A1, {} , true }, // 131 |
| 35131 | { "pmpcfg2", "pmpcfg2", "", 0x3A2, {} , false }, // 132 |
| 35132 | { "pmpcfg3", "pmpcfg3", "", 0x3A3, {} , true }, // 133 |
| 35133 | { "pmpcfg4", "pmpcfg4", "", 0x3A4, {} , false }, // 134 |
| 35134 | { "pmpcfg5", "pmpcfg5", "", 0x3A5, {} , true }, // 135 |
| 35135 | { "pmpcfg6", "pmpcfg6", "", 0x3A6, {} , false }, // 136 |
| 35136 | { "pmpcfg7", "pmpcfg7", "", 0x3A7, {} , true }, // 137 |
| 35137 | { "pmpcfg8", "pmpcfg8", "", 0x3A8, {} , false }, // 138 |
| 35138 | { "pmpcfg9", "pmpcfg9", "", 0x3A9, {} , true }, // 139 |
| 35139 | { "pmpcfg10", "pmpcfg10", "", 0x3AA, {} , false }, // 140 |
| 35140 | { "pmpcfg11", "pmpcfg11", "", 0x3AB, {} , true }, // 141 |
| 35141 | { "pmpcfg12", "pmpcfg12", "", 0x3AC, {} , false }, // 142 |
| 35142 | { "pmpcfg13", "pmpcfg13", "", 0x3AD, {} , true }, // 143 |
| 35143 | { "pmpcfg14", "pmpcfg14", "", 0x3AE, {} , false }, // 144 |
| 35144 | { "pmpcfg15", "pmpcfg15", "", 0x3AF, {} , true }, // 145 |
| 35145 | { "pmpaddr0", "pmpaddr0", "", 0x3B0, {} , false }, // 146 |
| 35146 | { "pmpaddr1", "pmpaddr1", "", 0x3B1, {} , false }, // 147 |
| 35147 | { "pmpaddr2", "pmpaddr2", "", 0x3B2, {} , false }, // 148 |
| 35148 | { "pmpaddr3", "pmpaddr3", "", 0x3B3, {} , false }, // 149 |
| 35149 | { "pmpaddr4", "pmpaddr4", "", 0x3B4, {} , false }, // 150 |
| 35150 | { "pmpaddr5", "pmpaddr5", "", 0x3B5, {} , false }, // 151 |
| 35151 | { "pmpaddr6", "pmpaddr6", "", 0x3B6, {} , false }, // 152 |
| 35152 | { "pmpaddr7", "pmpaddr7", "", 0x3B7, {} , false }, // 153 |
| 35153 | { "pmpaddr8", "pmpaddr8", "", 0x3B8, {} , false }, // 154 |
| 35154 | { "pmpaddr9", "pmpaddr9", "", 0x3B9, {} , false }, // 155 |
| 35155 | { "pmpaddr10", "pmpaddr10", "", 0x3BA, {} , false }, // 156 |
| 35156 | { "pmpaddr11", "pmpaddr11", "", 0x3BB, {} , false }, // 157 |
| 35157 | { "pmpaddr12", "pmpaddr12", "", 0x3BC, {} , false }, // 158 |
| 35158 | { "pmpaddr13", "pmpaddr13", "", 0x3BD, {} , false }, // 159 |
| 35159 | { "pmpaddr14", "pmpaddr14", "", 0x3BE, {} , false }, // 160 |
| 35160 | { "pmpaddr15", "pmpaddr15", "", 0x3BF, {} , false }, // 161 |
| 35161 | { "pmpaddr16", "pmpaddr16", "", 0x3C0, {} , false }, // 162 |
| 35162 | { "pmpaddr17", "pmpaddr17", "", 0x3C1, {} , false }, // 163 |
| 35163 | { "pmpaddr18", "pmpaddr18", "", 0x3C2, {} , false }, // 164 |
| 35164 | { "pmpaddr19", "pmpaddr19", "", 0x3C3, {} , false }, // 165 |
| 35165 | { "pmpaddr20", "pmpaddr20", "", 0x3C4, {} , false }, // 166 |
| 35166 | { "pmpaddr21", "pmpaddr21", "", 0x3C5, {} , false }, // 167 |
| 35167 | { "pmpaddr22", "pmpaddr22", "", 0x3C6, {} , false }, // 168 |
| 35168 | { "pmpaddr23", "pmpaddr23", "", 0x3C7, {} , false }, // 169 |
| 35169 | { "pmpaddr24", "pmpaddr24", "", 0x3C8, {} , false }, // 170 |
| 35170 | { "pmpaddr25", "pmpaddr25", "", 0x3C9, {} , false }, // 171 |
| 35171 | { "pmpaddr26", "pmpaddr26", "", 0x3CA, {} , false }, // 172 |
| 35172 | { "pmpaddr27", "pmpaddr27", "", 0x3CB, {} , false }, // 173 |
| 35173 | { "pmpaddr28", "pmpaddr28", "", 0x3CC, {} , false }, // 174 |
| 35174 | { "pmpaddr29", "pmpaddr29", "", 0x3CD, {} , false }, // 175 |
| 35175 | { "pmpaddr30", "pmpaddr30", "", 0x3CE, {} , false }, // 176 |
| 35176 | { "pmpaddr31", "pmpaddr31", "", 0x3CF, {} , false }, // 177 |
| 35177 | { "pmpaddr32", "pmpaddr32", "", 0x3D0, {} , false }, // 178 |
| 35178 | { "pmpaddr33", "pmpaddr33", "", 0x3D1, {} , false }, // 179 |
| 35179 | { "pmpaddr34", "pmpaddr34", "", 0x3D2, {} , false }, // 180 |
| 35180 | { "pmpaddr35", "pmpaddr35", "", 0x3D3, {} , false }, // 181 |
| 35181 | { "pmpaddr36", "pmpaddr36", "", 0x3D4, {} , false }, // 182 |
| 35182 | { "pmpaddr37", "pmpaddr37", "", 0x3D5, {} , false }, // 183 |
| 35183 | { "pmpaddr38", "pmpaddr38", "", 0x3D6, {} , false }, // 184 |
| 35184 | { "pmpaddr39", "pmpaddr39", "", 0x3D7, {} , false }, // 185 |
| 35185 | { "pmpaddr40", "pmpaddr40", "", 0x3D8, {} , false }, // 186 |
| 35186 | { "pmpaddr41", "pmpaddr41", "", 0x3D9, {} , false }, // 187 |
| 35187 | { "pmpaddr42", "pmpaddr42", "", 0x3DA, {} , false }, // 188 |
| 35188 | { "pmpaddr43", "pmpaddr43", "", 0x3DB, {} , false }, // 189 |
| 35189 | { "pmpaddr44", "pmpaddr44", "", 0x3DC, {} , false }, // 190 |
| 35190 | { "pmpaddr45", "pmpaddr45", "", 0x3DD, {} , false }, // 191 |
| 35191 | { "pmpaddr46", "pmpaddr46", "", 0x3DE, {} , false }, // 192 |
| 35192 | { "pmpaddr47", "pmpaddr47", "", 0x3DF, {} , false }, // 193 |
| 35193 | { "pmpaddr48", "pmpaddr48", "", 0x3E0, {} , false }, // 194 |
| 35194 | { "pmpaddr49", "pmpaddr49", "", 0x3E1, {} , false }, // 195 |
| 35195 | { "pmpaddr50", "pmpaddr50", "", 0x3E2, {} , false }, // 196 |
| 35196 | { "pmpaddr51", "pmpaddr51", "", 0x3E3, {} , false }, // 197 |
| 35197 | { "pmpaddr52", "pmpaddr52", "", 0x3E4, {} , false }, // 198 |
| 35198 | { "pmpaddr53", "pmpaddr53", "", 0x3E5, {} , false }, // 199 |
| 35199 | { "pmpaddr54", "pmpaddr54", "", 0x3E6, {} , false }, // 200 |
| 35200 | { "pmpaddr55", "pmpaddr55", "", 0x3E7, {} , false }, // 201 |
| 35201 | { "pmpaddr56", "pmpaddr56", "", 0x3E8, {} , false }, // 202 |
| 35202 | { "pmpaddr57", "pmpaddr57", "", 0x3E9, {} , false }, // 203 |
| 35203 | { "pmpaddr58", "pmpaddr58", "", 0x3EA, {} , false }, // 204 |
| 35204 | { "pmpaddr59", "pmpaddr59", "", 0x3EB, {} , false }, // 205 |
| 35205 | { "pmpaddr60", "pmpaddr60", "", 0x3EC, {} , false }, // 206 |
| 35206 | { "pmpaddr61", "pmpaddr61", "", 0x3ED, {} , false }, // 207 |
| 35207 | { "pmpaddr62", "pmpaddr62", "", 0x3EE, {} , false }, // 208 |
| 35208 | { "pmpaddr63", "pmpaddr63", "", 0x3EF, {} , false }, // 209 |
| 35209 | { "scontext", "scontext", "", 0x5A8, {} , false }, // 210 |
| 35210 | { "hstatus", "hstatus", "", 0x600, {} , false }, // 211 |
| 35211 | { "hedeleg", "hedeleg", "", 0x602, {} , false }, // 212 |
| 35212 | { "hideleg", "hideleg", "", 0x603, {} , false }, // 213 |
| 35213 | { "hie", "hie", "", 0x604, {} , false }, // 214 |
| 35214 | { "htimedelta", "htimedelta", "", 0x605, {} , false }, // 215 |
| 35215 | { "hcounteren", "hcounteren", "", 0x606, {} , false }, // 216 |
| 35216 | { "hgeie", "hgeie", "", 0x607, {} , false }, // 217 |
| 35217 | { "hvien", "hvien", "", 0x608, {} , false }, // 218 |
| 35218 | { "hvictl", "hvictl", "", 0x609, {} , false }, // 219 |
| 35219 | { "henvcfg", "henvcfg", "", 0x60A, {} , false }, // 220 |
| 35220 | { "hstateen0", "hstateen0", "", 0x60C, {} , false }, // 221 |
| 35221 | { "hstateen1", "hstateen1", "", 0x60D, {} , false }, // 222 |
| 35222 | { "hstateen2", "hstateen2", "", 0x60E, {} , false }, // 223 |
| 35223 | { "hstateen3", "hstateen3", "", 0x60F, {} , false }, // 224 |
| 35224 | { "hidelegh", "hidelegh", "", 0x613, {} , true }, // 225 |
| 35225 | { "htimedeltah", "htimedeltah", "", 0x615, {} , true }, // 226 |
| 35226 | { "hvienh", "hvienh", "", 0x618, {} , true }, // 227 |
| 35227 | { "henvcfgh", "henvcfgh", "", 0x61A, {} , true }, // 228 |
| 35228 | { "hstateen0h", "hstateen0h", "", 0x61C, {} , true }, // 229 |
| 35229 | { "hstateen1h", "hstateen1h", "", 0x61D, {} , true }, // 230 |
| 35230 | { "hstateen2h", "hstateen2h", "", 0x61E, {} , true }, // 231 |
| 35231 | { "hstateen3h", "hstateen3h", "", 0x61F, {} , true }, // 232 |
| 35232 | { "htval", "htval", "", 0x643, {} , false }, // 233 |
| 35233 | { "hip", "hip", "", 0x644, {} , false }, // 234 |
| 35234 | { "hvip", "hvip", "", 0x645, {} , false }, // 235 |
| 35235 | { "hviprio1", "hviprio1", "", 0x646, {} , false }, // 236 |
| 35236 | { "hviprio2", "hviprio2", "", 0x647, {} , false }, // 237 |
| 35237 | { "htinst", "htinst", "", 0x64A, {} , false }, // 238 |
| 35238 | { "hviph", "hviph", "", 0x655, {} , true }, // 239 |
| 35239 | { "hviprio1h", "hviprio1h", "", 0x656, {} , true }, // 240 |
| 35240 | { "hviprio2h", "hviprio2h", "", 0x657, {} , true }, // 241 |
| 35241 | { "hgatp", "hgatp", "", 0x680, {} , false }, // 242 |
| 35242 | { "hcontext", "hcontext", "", 0x6A8, {} , false }, // 243 |
| 35243 | { "mhpmevent3h", "mhpmevent3h", "", 0x723, {} , true }, // 244 |
| 35244 | { "mhpmevent4h", "mhpmevent4h", "", 0x724, {} , true }, // 245 |
| 35245 | { "mhpmevent5h", "mhpmevent5h", "", 0x725, {} , true }, // 246 |
| 35246 | { "mhpmevent6h", "mhpmevent6h", "", 0x726, {} , true }, // 247 |
| 35247 | { "mhpmevent7h", "mhpmevent7h", "", 0x727, {} , true }, // 248 |
| 35248 | { "mhpmevent8h", "mhpmevent8h", "", 0x728, {} , true }, // 249 |
| 35249 | { "mhpmevent9h", "mhpmevent9h", "", 0x729, {} , true }, // 250 |
| 35250 | { "mhpmevent10h", "mhpmevent10h", "", 0x72A, {} , true }, // 251 |
| 35251 | { "mhpmevent11h", "mhpmevent11h", "", 0x72B, {} , true }, // 252 |
| 35252 | { "mhpmevent12h", "mhpmevent12h", "", 0x72C, {} , true }, // 253 |
| 35253 | { "mhpmevent13h", "mhpmevent13h", "", 0x72D, {} , true }, // 254 |
| 35254 | { "mhpmevent14h", "mhpmevent14h", "", 0x72E, {} , true }, // 255 |
| 35255 | { "mhpmevent15h", "mhpmevent15h", "", 0x72F, {} , true }, // 256 |
| 35256 | { "mhpmevent16h", "mhpmevent16h", "", 0x730, {} , true }, // 257 |
| 35257 | { "mhpmevent17h", "mhpmevent17h", "", 0x731, {} , true }, // 258 |
| 35258 | { "mhpmevent18h", "mhpmevent18h", "", 0x732, {} , true }, // 259 |
| 35259 | { "mhpmevent19h", "mhpmevent19h", "", 0x733, {} , true }, // 260 |
| 35260 | { "mhpmevent20h", "mhpmevent20h", "", 0x734, {} , true }, // 261 |
| 35261 | { "mhpmevent21h", "mhpmevent21h", "", 0x735, {} , true }, // 262 |
| 35262 | { "mhpmevent22h", "mhpmevent22h", "", 0x736, {} , true }, // 263 |
| 35263 | { "mhpmevent23h", "mhpmevent23h", "", 0x737, {} , true }, // 264 |
| 35264 | { "mhpmevent24h", "mhpmevent24h", "", 0x738, {} , true }, // 265 |
| 35265 | { "mhpmevent25h", "mhpmevent25h", "", 0x739, {} , true }, // 266 |
| 35266 | { "mhpmevent26h", "mhpmevent26h", "", 0x73A, {} , true }, // 267 |
| 35267 | { "mhpmevent27h", "mhpmevent27h", "", 0x73B, {} , true }, // 268 |
| 35268 | { "mhpmevent28h", "mhpmevent28h", "", 0x73C, {} , true }, // 269 |
| 35269 | { "mhpmevent29h", "mhpmevent29h", "", 0x73D, {} , true }, // 270 |
| 35270 | { "mhpmevent30h", "mhpmevent30h", "", 0x73E, {} , true }, // 271 |
| 35271 | { "mhpmevent31h", "mhpmevent31h", "", 0x73F, {} , true }, // 272 |
| 35272 | { "mnscratch", "mnscratch", "", 0x740, {} , false }, // 273 |
| 35273 | { "mnepc", "mnepc", "", 0x741, {} , false }, // 274 |
| 35274 | { "mncause", "mncause", "", 0x742, {} , false }, // 275 |
| 35275 | { "mnstatus", "mnstatus", "", 0x744, {} , false }, // 276 |
| 35276 | { "mseccfg", "mseccfg", "", 0x747, {} , false }, // 277 |
| 35277 | { "mseccfgh", "mseccfgh", "", 0x757, {} , true }, // 278 |
| 35278 | { "tselect", "tselect", "", 0x7A0, {} , false }, // 279 |
| 35279 | { "tdata1", "tdata1", "", 0x7A1, {} , false }, // 280 |
| 35280 | { "tdata2", "tdata2", "", 0x7A2, {} , false }, // 281 |
| 35281 | { "tdata3", "tdata3", "", 0x7A3, {} , false }, // 282 |
| 35282 | { "mcontext", "mcontext", "", 0x7A8, {} , false }, // 283 |
| 35283 | { "dcsr", "dcsr", "", 0x7B0, {} , false }, // 284 |
| 35284 | { "dpc", "dpc", "", 0x7B1, {} , false }, // 285 |
| 35285 | { "dscratch0", "dscratch", "", 0x7B2, {} , false }, // 286 |
| 35286 | { "dscratch1", "dscratch1", "", 0x7B3, {} , false }, // 287 |
| 35287 | { "mcycle", "mcycle", "", 0xB00, {} , false }, // 288 |
| 35288 | { "minstret", "minstret", "", 0xB02, {} , false }, // 289 |
| 35289 | { "mhpmcounter3", "mhpmcounter3", "", 0xB03, {} , false }, // 290 |
| 35290 | { "mhpmcounter4", "mhpmcounter4", "", 0xB04, {} , false }, // 291 |
| 35291 | { "mhpmcounter5", "mhpmcounter5", "", 0xB05, {} , false }, // 292 |
| 35292 | { "mhpmcounter6", "mhpmcounter6", "", 0xB06, {} , false }, // 293 |
| 35293 | { "mhpmcounter7", "mhpmcounter7", "", 0xB07, {} , false }, // 294 |
| 35294 | { "mhpmcounter8", "mhpmcounter8", "", 0xB08, {} , false }, // 295 |
| 35295 | { "mhpmcounter9", "mhpmcounter9", "", 0xB09, {} , false }, // 296 |
| 35296 | { "mhpmcounter10", "mhpmcounter10", "", 0xB0A, {} , false }, // 297 |
| 35297 | { "mhpmcounter11", "mhpmcounter11", "", 0xB0B, {} , false }, // 298 |
| 35298 | { "mhpmcounter12", "mhpmcounter12", "", 0xB0C, {} , false }, // 299 |
| 35299 | { "mhpmcounter13", "mhpmcounter13", "", 0xB0D, {} , false }, // 300 |
| 35300 | { "mhpmcounter14", "mhpmcounter14", "", 0xB0E, {} , false }, // 301 |
| 35301 | { "mhpmcounter15", "mhpmcounter15", "", 0xB0F, {} , false }, // 302 |
| 35302 | { "mhpmcounter16", "mhpmcounter16", "", 0xB10, {} , false }, // 303 |
| 35303 | { "mhpmcounter17", "mhpmcounter17", "", 0xB11, {} , false }, // 304 |
| 35304 | { "mhpmcounter18", "mhpmcounter18", "", 0xB12, {} , false }, // 305 |
| 35305 | { "mhpmcounter19", "mhpmcounter19", "", 0xB13, {} , false }, // 306 |
| 35306 | { "mhpmcounter20", "mhpmcounter20", "", 0xB14, {} , false }, // 307 |
| 35307 | { "mhpmcounter21", "mhpmcounter21", "", 0xB15, {} , false }, // 308 |
| 35308 | { "mhpmcounter22", "mhpmcounter22", "", 0xB16, {} , false }, // 309 |
| 35309 | { "mhpmcounter23", "mhpmcounter23", "", 0xB17, {} , false }, // 310 |
| 35310 | { "mhpmcounter24", "mhpmcounter24", "", 0xB18, {} , false }, // 311 |
| 35311 | { "mhpmcounter25", "mhpmcounter25", "", 0xB19, {} , false }, // 312 |
| 35312 | { "mhpmcounter26", "mhpmcounter26", "", 0xB1A, {} , false }, // 313 |
| 35313 | { "mhpmcounter27", "mhpmcounter27", "", 0xB1B, {} , false }, // 314 |
| 35314 | { "mhpmcounter28", "mhpmcounter28", "", 0xB1C, {} , false }, // 315 |
| 35315 | { "mhpmcounter29", "mhpmcounter29", "", 0xB1D, {} , false }, // 316 |
| 35316 | { "mhpmcounter30", "mhpmcounter30", "", 0xB1E, {} , false }, // 317 |
| 35317 | { "mhpmcounter31", "mhpmcounter31", "", 0xB1F, {} , false }, // 318 |
| 35318 | { "mcycleh", "mcycleh", "", 0xB80, {} , true }, // 319 |
| 35319 | { "minstreth", "minstreth", "", 0xB82, {} , true }, // 320 |
| 35320 | { "mhpmcounter3h", "mhpmcounter3h", "", 0xB83, {} , true }, // 321 |
| 35321 | { "mhpmcounter4h", "mhpmcounter4h", "", 0xB84, {} , true }, // 322 |
| 35322 | { "mhpmcounter5h", "mhpmcounter5h", "", 0xB85, {} , true }, // 323 |
| 35323 | { "mhpmcounter6h", "mhpmcounter6h", "", 0xB86, {} , true }, // 324 |
| 35324 | { "mhpmcounter7h", "mhpmcounter7h", "", 0xB87, {} , true }, // 325 |
| 35325 | { "mhpmcounter8h", "mhpmcounter8h", "", 0xB88, {} , true }, // 326 |
| 35326 | { "mhpmcounter9h", "mhpmcounter9h", "", 0xB89, {} , true }, // 327 |
| 35327 | { "mhpmcounter10h", "mhpmcounter10h", "", 0xB8A, {} , true }, // 328 |
| 35328 | { "mhpmcounter11h", "mhpmcounter11h", "", 0xB8B, {} , true }, // 329 |
| 35329 | { "mhpmcounter12h", "mhpmcounter12h", "", 0xB8C, {} , true }, // 330 |
| 35330 | { "mhpmcounter13h", "mhpmcounter13h", "", 0xB8D, {} , true }, // 331 |
| 35331 | { "mhpmcounter14h", "mhpmcounter14h", "", 0xB8E, {} , true }, // 332 |
| 35332 | { "mhpmcounter15h", "mhpmcounter15h", "", 0xB8F, {} , true }, // 333 |
| 35333 | { "mhpmcounter16h", "mhpmcounter16h", "", 0xB90, {} , true }, // 334 |
| 35334 | { "mhpmcounter17h", "mhpmcounter17h", "", 0xB91, {} , true }, // 335 |
| 35335 | { "mhpmcounter18h", "mhpmcounter18h", "", 0xB92, {} , true }, // 336 |
| 35336 | { "mhpmcounter19h", "mhpmcounter19h", "", 0xB93, {} , true }, // 337 |
| 35337 | { "mhpmcounter20h", "mhpmcounter20h", "", 0xB94, {} , true }, // 338 |
| 35338 | { "mhpmcounter21h", "mhpmcounter21h", "", 0xB95, {} , true }, // 339 |
| 35339 | { "mhpmcounter22h", "mhpmcounter22h", "", 0xB96, {} , true }, // 340 |
| 35340 | { "mhpmcounter23h", "mhpmcounter23h", "", 0xB97, {} , true }, // 341 |
| 35341 | { "mhpmcounter24h", "mhpmcounter24h", "", 0xB98, {} , true }, // 342 |
| 35342 | { "mhpmcounter25h", "mhpmcounter25h", "", 0xB99, {} , true }, // 343 |
| 35343 | { "mhpmcounter26h", "mhpmcounter26h", "", 0xB9A, {} , true }, // 344 |
| 35344 | { "mhpmcounter27h", "mhpmcounter27h", "", 0xB9B, {} , true }, // 345 |
| 35345 | { "mhpmcounter28h", "mhpmcounter28h", "", 0xB9C, {} , true }, // 346 |
| 35346 | { "mhpmcounter29h", "mhpmcounter29h", "", 0xB9D, {} , true }, // 347 |
| 35347 | { "mhpmcounter30h", "mhpmcounter30h", "", 0xB9E, {} , true }, // 348 |
| 35348 | { "mhpmcounter31h", "mhpmcounter31h", "", 0xB9F, {} , true }, // 349 |
| 35349 | { "cycle", "cycle", "", 0xC00, {} , false }, // 350 |
| 35350 | { "time", "time", "", 0xC01, {} , false }, // 351 |
| 35351 | { "instret", "instret", "", 0xC02, {} , false }, // 352 |
| 35352 | { "hpmcounter3", "hpmcounter3", "", 0xC03, {} , false }, // 353 |
| 35353 | { "hpmcounter4", "hpmcounter4", "", 0xC04, {} , false }, // 354 |
| 35354 | { "hpmcounter5", "hpmcounter5", "", 0xC05, {} , false }, // 355 |
| 35355 | { "hpmcounter6", "hpmcounter6", "", 0xC06, {} , false }, // 356 |
| 35356 | { "hpmcounter7", "hpmcounter7", "", 0xC07, {} , false }, // 357 |
| 35357 | { "hpmcounter8", "hpmcounter8", "", 0xC08, {} , false }, // 358 |
| 35358 | { "hpmcounter9", "hpmcounter9", "", 0xC09, {} , false }, // 359 |
| 35359 | { "hpmcounter10", "hpmcounter10", "", 0xC0A, {} , false }, // 360 |
| 35360 | { "hpmcounter11", "hpmcounter11", "", 0xC0B, {} , false }, // 361 |
| 35361 | { "hpmcounter12", "hpmcounter12", "", 0xC0C, {} , false }, // 362 |
| 35362 | { "hpmcounter13", "hpmcounter13", "", 0xC0D, {} , false }, // 363 |
| 35363 | { "hpmcounter14", "hpmcounter14", "", 0xC0E, {} , false }, // 364 |
| 35364 | { "hpmcounter15", "hpmcounter15", "", 0xC0F, {} , false }, // 365 |
| 35365 | { "hpmcounter16", "hpmcounter16", "", 0xC10, {} , false }, // 366 |
| 35366 | { "hpmcounter17", "hpmcounter17", "", 0xC11, {} , false }, // 367 |
| 35367 | { "hpmcounter18", "hpmcounter18", "", 0xC12, {} , false }, // 368 |
| 35368 | { "hpmcounter19", "hpmcounter19", "", 0xC13, {} , false }, // 369 |
| 35369 | { "hpmcounter20", "hpmcounter20", "", 0xC14, {} , false }, // 370 |
| 35370 | { "hpmcounter21", "hpmcounter21", "", 0xC15, {} , false }, // 371 |
| 35371 | { "hpmcounter22", "hpmcounter22", "", 0xC16, {} , false }, // 372 |
| 35372 | { "hpmcounter23", "hpmcounter23", "", 0xC17, {} , false }, // 373 |
| 35373 | { "hpmcounter24", "hpmcounter24", "", 0xC18, {} , false }, // 374 |
| 35374 | { "hpmcounter25", "hpmcounter25", "", 0xC19, {} , false }, // 375 |
| 35375 | { "hpmcounter26", "hpmcounter26", "", 0xC1A, {} , false }, // 376 |
| 35376 | { "hpmcounter27", "hpmcounter27", "", 0xC1B, {} , false }, // 377 |
| 35377 | { "hpmcounter28", "hpmcounter28", "", 0xC1C, {} , false }, // 378 |
| 35378 | { "hpmcounter29", "hpmcounter29", "", 0xC1D, {} , false }, // 379 |
| 35379 | { "hpmcounter30", "hpmcounter30", "", 0xC1E, {} , false }, // 380 |
| 35380 | { "hpmcounter31", "hpmcounter31", "", 0xC1F, {} , false }, // 381 |
| 35381 | { "vl", "vl", "", 0xC20, {} , false }, // 382 |
| 35382 | { "vtype", "vtype", "", 0xC21, {} , false }, // 383 |
| 35383 | { "vlenb", "vlenb", "", 0xC22, {} , false }, // 384 |
| 35384 | { "cycleh", "cycleh", "", 0xC80, {} , true }, // 385 |
| 35385 | { "timeh", "timeh", "", 0xC81, {} , true }, // 386 |
| 35386 | { "instreth", "instreth", "", 0xC82, {} , true }, // 387 |
| 35387 | { "hpmcounter3h", "hpmcounter3h", "", 0xC83, {} , true }, // 388 |
| 35388 | { "hpmcounter4h", "hpmcounter4h", "", 0xC84, {} , true }, // 389 |
| 35389 | { "hpmcounter5h", "hpmcounter5h", "", 0xC85, {} , true }, // 390 |
| 35390 | { "hpmcounter6h", "hpmcounter6h", "", 0xC86, {} , true }, // 391 |
| 35391 | { "hpmcounter7h", "hpmcounter7h", "", 0xC87, {} , true }, // 392 |
| 35392 | { "hpmcounter8h", "hpmcounter8h", "", 0xC88, {} , true }, // 393 |
| 35393 | { "hpmcounter9h", "hpmcounter9h", "", 0xC89, {} , true }, // 394 |
| 35394 | { "hpmcounter10h", "hpmcounter10h", "", 0xC8A, {} , true }, // 395 |
| 35395 | { "hpmcounter11h", "hpmcounter11h", "", 0xC8B, {} , true }, // 396 |
| 35396 | { "hpmcounter12h", "hpmcounter12h", "", 0xC8C, {} , true }, // 397 |
| 35397 | { "hpmcounter13h", "hpmcounter13h", "", 0xC8D, {} , true }, // 398 |
| 35398 | { "hpmcounter14h", "hpmcounter14h", "", 0xC8E, {} , true }, // 399 |
| 35399 | { "hpmcounter15h", "hpmcounter15h", "", 0xC8F, {} , true }, // 400 |
| 35400 | { "hpmcounter16h", "hpmcounter16h", "", 0xC90, {} , true }, // 401 |
| 35401 | { "hpmcounter17h", "hpmcounter17h", "", 0xC91, {} , true }, // 402 |
| 35402 | { "hpmcounter18h", "hpmcounter18h", "", 0xC92, {} , true }, // 403 |
| 35403 | { "hpmcounter19h", "hpmcounter19h", "", 0xC93, {} , true }, // 404 |
| 35404 | { "hpmcounter20h", "hpmcounter20h", "", 0xC94, {} , true }, // 405 |
| 35405 | { "hpmcounter21h", "hpmcounter21h", "", 0xC95, {} , true }, // 406 |
| 35406 | { "hpmcounter22h", "hpmcounter22h", "", 0xC96, {} , true }, // 407 |
| 35407 | { "hpmcounter23h", "hpmcounter23h", "", 0xC97, {} , true }, // 408 |
| 35408 | { "hpmcounter24h", "hpmcounter24h", "", 0xC98, {} , true }, // 409 |
| 35409 | { "hpmcounter25h", "hpmcounter25h", "", 0xC99, {} , true }, // 410 |
| 35410 | { "hpmcounter26h", "hpmcounter26h", "", 0xC9A, {} , true }, // 411 |
| 35411 | { "hpmcounter27h", "hpmcounter27h", "", 0xC9B, {} , true }, // 412 |
| 35412 | { "hpmcounter28h", "hpmcounter28h", "", 0xC9C, {} , true }, // 413 |
| 35413 | { "hpmcounter29h", "hpmcounter29h", "", 0xC9D, {} , true }, // 414 |
| 35414 | { "hpmcounter30h", "hpmcounter30h", "", 0xC9E, {} , true }, // 415 |
| 35415 | { "hpmcounter31h", "hpmcounter31h", "", 0xC9F, {} , true }, // 416 |
| 35416 | { "scountovf", "scountovf", "", 0xDA0, {} , false }, // 417 |
| 35417 | { "stopi", "stopi", "", 0xDB0, {} , false }, // 418 |
| 35418 | { "hgeip", "hgeip", "", 0xE12, {} , false }, // 419 |
| 35419 | { "vstopi", "vstopi", "", 0xEB0, {} , false }, // 420 |
| 35420 | { "mvendorid", "mvendorid", "", 0xF11, {} , false }, // 421 |
| 35421 | { "marchid", "marchid", "", 0xF12, {} , false }, // 422 |
| 35422 | { "mimpid", "mimpid", "", 0xF13, {} , false }, // 423 |
| 35423 | { "mhartid", "mhartid", "", 0xF14, {} , false }, // 424 |
| 35424 | { "mconfigptr", "mconfigptr", "", 0xF15, {} , false }, // 425 |
| 35425 | { "mtopi", "mtopi", "", 0xFB0, {} , false }, // 426 |
| 35426 | }; |
| 35427 | |
| 35428 | llvm::iterator_range<const SysReg *> lookupSysRegByEncoding(uint16_t Encoding) { |
| 35429 | struct KeyType { |
| 35430 | uint16_t Encoding; |
| 35431 | }; |
| 35432 | KeyType Key = {Encoding}; |
| 35433 | struct Comp { |
| 35434 | bool operator()(const SysReg &LHS, const KeyType &RHS) const { |
| 35435 | if (LHS.Encoding < RHS.Encoding) |
| 35436 | return true; |
| 35437 | if (LHS.Encoding > RHS.Encoding) |
| 35438 | return false; |
| 35439 | return false; |
| 35440 | } |
| 35441 | bool operator()(const KeyType &LHS, const SysReg &RHS) const { |
| 35442 | if (LHS.Encoding < RHS.Encoding) |
| 35443 | return true; |
| 35444 | if (LHS.Encoding > RHS.Encoding) |
| 35445 | return false; |
| 35446 | return false; |
| 35447 | } |
| 35448 | }; |
| 35449 | auto Table = ArrayRef(SysRegsList); |
| 35450 | auto It = std::equal_range(Table.begin(), Table.end(), Key, Comp()); |
| 35451 | return llvm::make_range(It.first, It.second); |
| 35452 | } |
| 35453 | |
| 35454 | const SysReg *lookupSysRegByAltName(StringRef AltName) { |
| 35455 | struct IndexType { |
| 35456 | const char * AltName; |
| 35457 | unsigned _index; |
| 35458 | }; |
| 35459 | static const struct IndexType Index[] = { |
| 35460 | { "CYCLE", 350 }, |
| 35461 | { "CYCLEH", 385 }, |
| 35462 | { "DCSR", 284 }, |
| 35463 | { "DPC", 285 }, |
| 35464 | { "DSCRATCH", 286 }, |
| 35465 | { "DSCRATCH1", 287 }, |
| 35466 | { "FCSR", 2 }, |
| 35467 | { "FFLAGS", 0 }, |
| 35468 | { "FRM", 1 }, |
| 35469 | { "HCONTEXT", 243 }, |
| 35470 | { "HCOUNTEREN", 216 }, |
| 35471 | { "HEDELEG", 212 }, |
| 35472 | { "HENVCFG", 220 }, |
| 35473 | { "HENVCFGH", 228 }, |
| 35474 | { "HGATP", 242 }, |
| 35475 | { "HGEIE", 217 }, |
| 35476 | { "HGEIP", 419 }, |
| 35477 | { "HIDELEG", 213 }, |
| 35478 | { "HIDELEGH", 225 }, |
| 35479 | { "HIE", 214 }, |
| 35480 | { "HIP", 234 }, |
| 35481 | { "HPMCOUNTER10", 360 }, |
| 35482 | { "HPMCOUNTER10H", 395 }, |
| 35483 | { "HPMCOUNTER11", 361 }, |
| 35484 | { "HPMCOUNTER11H", 396 }, |
| 35485 | { "HPMCOUNTER12", 362 }, |
| 35486 | { "HPMCOUNTER12H", 397 }, |
| 35487 | { "HPMCOUNTER13", 363 }, |
| 35488 | { "HPMCOUNTER13H", 398 }, |
| 35489 | { "HPMCOUNTER14", 364 }, |
| 35490 | { "HPMCOUNTER14H", 399 }, |
| 35491 | { "HPMCOUNTER15", 365 }, |
| 35492 | { "HPMCOUNTER15H", 400 }, |
| 35493 | { "HPMCOUNTER16", 366 }, |
| 35494 | { "HPMCOUNTER16H", 401 }, |
| 35495 | { "HPMCOUNTER17", 367 }, |
| 35496 | { "HPMCOUNTER17H", 402 }, |
| 35497 | { "HPMCOUNTER18", 368 }, |
| 35498 | { "HPMCOUNTER18H", 403 }, |
| 35499 | { "HPMCOUNTER19", 369 }, |
| 35500 | { "HPMCOUNTER19H", 404 }, |
| 35501 | { "HPMCOUNTER20", 370 }, |
| 35502 | { "HPMCOUNTER20H", 405 }, |
| 35503 | { "HPMCOUNTER21", 371 }, |
| 35504 | { "HPMCOUNTER21H", 406 }, |
| 35505 | { "HPMCOUNTER22", 372 }, |
| 35506 | { "HPMCOUNTER22H", 407 }, |
| 35507 | { "HPMCOUNTER23", 373 }, |
| 35508 | { "HPMCOUNTER23H", 408 }, |
| 35509 | { "HPMCOUNTER24", 374 }, |
| 35510 | { "HPMCOUNTER24H", 409 }, |
| 35511 | { "HPMCOUNTER25", 375 }, |
| 35512 | { "HPMCOUNTER25H", 410 }, |
| 35513 | { "HPMCOUNTER26", 376 }, |
| 35514 | { "HPMCOUNTER26H", 411 }, |
| 35515 | { "HPMCOUNTER27", 377 }, |
| 35516 | { "HPMCOUNTER27H", 412 }, |
| 35517 | { "HPMCOUNTER28", 378 }, |
| 35518 | { "HPMCOUNTER28H", 413 }, |
| 35519 | { "HPMCOUNTER29", 379 }, |
| 35520 | { "HPMCOUNTER29H", 414 }, |
| 35521 | { "HPMCOUNTER3", 353 }, |
| 35522 | { "HPMCOUNTER30", 380 }, |
| 35523 | { "HPMCOUNTER30H", 415 }, |
| 35524 | { "HPMCOUNTER31", 381 }, |
| 35525 | { "HPMCOUNTER31H", 416 }, |
| 35526 | { "HPMCOUNTER3H", 388 }, |
| 35527 | { "HPMCOUNTER4", 354 }, |
| 35528 | { "HPMCOUNTER4H", 389 }, |
| 35529 | { "HPMCOUNTER5", 355 }, |
| 35530 | { "HPMCOUNTER5H", 390 }, |
| 35531 | { "HPMCOUNTER6", 356 }, |
| 35532 | { "HPMCOUNTER6H", 391 }, |
| 35533 | { "HPMCOUNTER7", 357 }, |
| 35534 | { "HPMCOUNTER7H", 392 }, |
| 35535 | { "HPMCOUNTER8", 358 }, |
| 35536 | { "HPMCOUNTER8H", 393 }, |
| 35537 | { "HPMCOUNTER9", 359 }, |
| 35538 | { "HPMCOUNTER9H", 394 }, |
| 35539 | { "HSTATEEN0", 221 }, |
| 35540 | { "HSTATEEN0H", 229 }, |
| 35541 | { "HSTATEEN1", 222 }, |
| 35542 | { "HSTATEEN1H", 230 }, |
| 35543 | { "HSTATEEN2", 223 }, |
| 35544 | { "HSTATEEN2H", 231 }, |
| 35545 | { "HSTATEEN3", 224 }, |
| 35546 | { "HSTATEEN3H", 232 }, |
| 35547 | { "HSTATUS", 211 }, |
| 35548 | { "HTIMEDELTA", 215 }, |
| 35549 | { "HTIMEDELTAH", 226 }, |
| 35550 | { "HTINST", 238 }, |
| 35551 | { "HTVAL", 233 }, |
| 35552 | { "HVICTL", 219 }, |
| 35553 | { "HVIEN", 218 }, |
| 35554 | { "HVIENH", 227 }, |
| 35555 | { "HVIP", 235 }, |
| 35556 | { "HVIPH", 239 }, |
| 35557 | { "HVIPRIO1", 236 }, |
| 35558 | { "HVIPRIO1H", 240 }, |
| 35559 | { "HVIPRIO2", 237 }, |
| 35560 | { "HVIPRIO2H", 241 }, |
| 35561 | { "INSTRET", 352 }, |
| 35562 | { "INSTRETH", 387 }, |
| 35563 | { "JVT", 9 }, |
| 35564 | { "MARCHID", 422 }, |
| 35565 | { "MCAUSE", 116 }, |
| 35566 | { "MCONFIGPTR", 425 }, |
| 35567 | { "MCONTEXT", 283 }, |
| 35568 | { "MCOUNTEREN", 66 }, |
| 35569 | { "MCYCLE", 288 }, |
| 35570 | { "MCYCLEH", 319 }, |
| 35571 | { "MEDELEG", 62 }, |
| 35572 | { "MENVCFG", 69 }, |
| 35573 | { "MENVCFGH", 79 }, |
| 35574 | { "MEPC", 115 }, |
| 35575 | { "MHARTID", 424 }, |
| 35576 | { "MHPMCOUNTER10", 297 }, |
| 35577 | { "MHPMCOUNTER10H", 328 }, |
| 35578 | { "MHPMCOUNTER11", 298 }, |
| 35579 | { "MHPMCOUNTER11H", 329 }, |
| 35580 | { "MHPMCOUNTER12", 299 }, |
| 35581 | { "MHPMCOUNTER12H", 330 }, |
| 35582 | { "MHPMCOUNTER13", 300 }, |
| 35583 | { "MHPMCOUNTER13H", 331 }, |
| 35584 | { "MHPMCOUNTER14", 301 }, |
| 35585 | { "MHPMCOUNTER14H", 332 }, |
| 35586 | { "MHPMCOUNTER15", 302 }, |
| 35587 | { "MHPMCOUNTER15H", 333 }, |
| 35588 | { "MHPMCOUNTER16", 303 }, |
| 35589 | { "MHPMCOUNTER16H", 334 }, |
| 35590 | { "MHPMCOUNTER17", 304 }, |
| 35591 | { "MHPMCOUNTER17H", 335 }, |
| 35592 | { "MHPMCOUNTER18", 305 }, |
| 35593 | { "MHPMCOUNTER18H", 336 }, |
| 35594 | { "MHPMCOUNTER19", 306 }, |
| 35595 | { "MHPMCOUNTER19H", 337 }, |
| 35596 | { "MHPMCOUNTER20", 307 }, |
| 35597 | { "MHPMCOUNTER20H", 338 }, |
| 35598 | { "MHPMCOUNTER21", 308 }, |
| 35599 | { "MHPMCOUNTER21H", 339 }, |
| 35600 | { "MHPMCOUNTER22", 309 }, |
| 35601 | { "MHPMCOUNTER22H", 340 }, |
| 35602 | { "MHPMCOUNTER23", 310 }, |
| 35603 | { "MHPMCOUNTER23H", 341 }, |
| 35604 | { "MHPMCOUNTER24", 311 }, |
| 35605 | { "MHPMCOUNTER24H", 342 }, |
| 35606 | { "MHPMCOUNTER25", 312 }, |
| 35607 | { "MHPMCOUNTER25H", 343 }, |
| 35608 | { "MHPMCOUNTER26", 313 }, |
| 35609 | { "MHPMCOUNTER26H", 344 }, |
| 35610 | { "MHPMCOUNTER27", 314 }, |
| 35611 | { "MHPMCOUNTER27H", 345 }, |
| 35612 | { "MHPMCOUNTER28", 315 }, |
| 35613 | { "MHPMCOUNTER28H", 346 }, |
| 35614 | { "MHPMCOUNTER29", 316 }, |
| 35615 | { "MHPMCOUNTER29H", 347 }, |
| 35616 | { "MHPMCOUNTER3", 290 }, |
| 35617 | { "MHPMCOUNTER30", 317 }, |
| 35618 | { "MHPMCOUNTER30H", 348 }, |
| 35619 | { "MHPMCOUNTER31", 318 }, |
| 35620 | { "MHPMCOUNTER31H", 349 }, |
| 35621 | { "MHPMCOUNTER3H", 321 }, |
| 35622 | { "MHPMCOUNTER4", 291 }, |
| 35623 | { "MHPMCOUNTER4H", 322 }, |
| 35624 | { "MHPMCOUNTER5", 292 }, |
| 35625 | { "MHPMCOUNTER5H", 323 }, |
| 35626 | { "MHPMCOUNTER6", 293 }, |
| 35627 | { "MHPMCOUNTER6H", 324 }, |
| 35628 | { "MHPMCOUNTER7", 294 }, |
| 35629 | { "MHPMCOUNTER7H", 325 }, |
| 35630 | { "MHPMCOUNTER8", 295 }, |
| 35631 | { "MHPMCOUNTER8H", 326 }, |
| 35632 | { "MHPMCOUNTER9", 296 }, |
| 35633 | { "MHPMCOUNTER9H", 327 }, |
| 35634 | { "MHPMEVENT10", 92 }, |
| 35635 | { "MHPMEVENT10H", 251 }, |
| 35636 | { "MHPMEVENT11", 93 }, |
| 35637 | { "MHPMEVENT11H", 252 }, |
| 35638 | { "MHPMEVENT12", 94 }, |
| 35639 | { "MHPMEVENT12H", 253 }, |
| 35640 | { "MHPMEVENT13", 95 }, |
| 35641 | { "MHPMEVENT13H", 254 }, |
| 35642 | { "MHPMEVENT14", 96 }, |
| 35643 | { "MHPMEVENT14H", 255 }, |
| 35644 | { "MHPMEVENT15", 97 }, |
| 35645 | { "MHPMEVENT15H", 256 }, |
| 35646 | { "MHPMEVENT16", 98 }, |
| 35647 | { "MHPMEVENT16H", 257 }, |
| 35648 | { "MHPMEVENT17", 99 }, |
| 35649 | { "MHPMEVENT17H", 258 }, |
| 35650 | { "MHPMEVENT18", 100 }, |
| 35651 | { "MHPMEVENT18H", 259 }, |
| 35652 | { "MHPMEVENT19", 101 }, |
| 35653 | { "MHPMEVENT19H", 260 }, |
| 35654 | { "MHPMEVENT20", 102 }, |
| 35655 | { "MHPMEVENT20H", 261 }, |
| 35656 | { "MHPMEVENT21", 103 }, |
| 35657 | { "MHPMEVENT21H", 262 }, |
| 35658 | { "MHPMEVENT22", 104 }, |
| 35659 | { "MHPMEVENT22H", 263 }, |
| 35660 | { "MHPMEVENT23", 105 }, |
| 35661 | { "MHPMEVENT23H", 264 }, |
| 35662 | { "MHPMEVENT24", 106 }, |
| 35663 | { "MHPMEVENT24H", 265 }, |
| 35664 | { "MHPMEVENT25", 107 }, |
| 35665 | { "MHPMEVENT25H", 266 }, |
| 35666 | { "MHPMEVENT26", 108 }, |
| 35667 | { "MHPMEVENT26H", 267 }, |
| 35668 | { "MHPMEVENT27", 109 }, |
| 35669 | { "MHPMEVENT27H", 268 }, |
| 35670 | { "MHPMEVENT28", 110 }, |
| 35671 | { "MHPMEVENT28H", 269 }, |
| 35672 | { "MHPMEVENT29", 111 }, |
| 35673 | { "MHPMEVENT29H", 270 }, |
| 35674 | { "MHPMEVENT3", 85 }, |
| 35675 | { "MHPMEVENT30", 112 }, |
| 35676 | { "MHPMEVENT30H", 271 }, |
| 35677 | { "MHPMEVENT31", 113 }, |
| 35678 | { "MHPMEVENT31H", 272 }, |
| 35679 | { "MHPMEVENT3H", 244 }, |
| 35680 | { "MHPMEVENT4", 86 }, |
| 35681 | { "MHPMEVENT4H", 245 }, |
| 35682 | { "MHPMEVENT5", 87 }, |
| 35683 | { "MHPMEVENT5H", 246 }, |
| 35684 | { "MHPMEVENT6", 88 }, |
| 35685 | { "MHPMEVENT6H", 247 }, |
| 35686 | { "MHPMEVENT7", 89 }, |
| 35687 | { "MHPMEVENT7H", 248 }, |
| 35688 | { "MHPMEVENT8", 90 }, |
| 35689 | { "MHPMEVENT8H", 249 }, |
| 35690 | { "MHPMEVENT9", 91 }, |
| 35691 | { "MHPMEVENT9H", 250 }, |
| 35692 | { "MIDELEG", 63 }, |
| 35693 | { "MIDELEGH", 75 }, |
| 35694 | { "MIE", 64 }, |
| 35695 | { "MIEH", 76 }, |
| 35696 | { "MIMPID", 423 }, |
| 35697 | { "MINSTRET", 289 }, |
| 35698 | { "MINSTRETH", 320 }, |
| 35699 | { "MIP", 118 }, |
| 35700 | { "MIPH", 125 }, |
| 35701 | { "MIREG", 122 }, |
| 35702 | { "MIREG2", 123 }, |
| 35703 | { "MIREG3", 124 }, |
| 35704 | { "MIREG4", 126 }, |
| 35705 | { "MIREG5", 127 }, |
| 35706 | { "MIREG6", 128 }, |
| 35707 | { "MISA", 61 }, |
| 35708 | { "MISELECT", 121 }, |
| 35709 | { "MNCAUSE", 275 }, |
| 35710 | { "MNEPC", 274 }, |
| 35711 | { "MNSCRATCH", 273 }, |
| 35712 | { "MNSTATUS", 276 }, |
| 35713 | { "MSCRATCH", 114 }, |
| 35714 | { "MSECCFG", 277 }, |
| 35715 | { "MSECCFGH", 278 }, |
| 35716 | { "MSTATEEN0", 70 }, |
| 35717 | { "MSTATEEN0H", 80 }, |
| 35718 | { "MSTATEEN1", 71 }, |
| 35719 | { "MSTATEEN1H", 81 }, |
| 35720 | { "MSTATEEN2", 72 }, |
| 35721 | { "MSTATEEN2H", 82 }, |
| 35722 | { "MSTATEEN3", 73 }, |
| 35723 | { "MSTATEEN3H", 83 }, |
| 35724 | { "MSTATUS", 60 }, |
| 35725 | { "MSTATUSH", 74 }, |
| 35726 | { "MTINST", 119 }, |
| 35727 | { "MTOPEI", 129 }, |
| 35728 | { "MTOPI", 426 }, |
| 35729 | { "MTVAL", 117 }, |
| 35730 | { "MTVAL2", 120 }, |
| 35731 | { "MTVEC", 65 }, |
| 35732 | { "MUCOUNTEREN", 84 }, |
| 35733 | { "MVENDORID", 421 }, |
| 35734 | { "MVIEN", 67 }, |
| 35735 | { "MVIENH", 77 }, |
| 35736 | { "MVIP", 68 }, |
| 35737 | { "MVIPH", 78 }, |
| 35738 | { "PMPADDR0", 146 }, |
| 35739 | { "PMPADDR1", 147 }, |
| 35740 | { "PMPADDR10", 156 }, |
| 35741 | { "PMPADDR11", 157 }, |
| 35742 | { "PMPADDR12", 158 }, |
| 35743 | { "PMPADDR13", 159 }, |
| 35744 | { "PMPADDR14", 160 }, |
| 35745 | { "PMPADDR15", 161 }, |
| 35746 | { "PMPADDR16", 162 }, |
| 35747 | { "PMPADDR17", 163 }, |
| 35748 | { "PMPADDR18", 164 }, |
| 35749 | { "PMPADDR19", 165 }, |
| 35750 | { "PMPADDR2", 148 }, |
| 35751 | { "PMPADDR20", 166 }, |
| 35752 | { "PMPADDR21", 167 }, |
| 35753 | { "PMPADDR22", 168 }, |
| 35754 | { "PMPADDR23", 169 }, |
| 35755 | { "PMPADDR24", 170 }, |
| 35756 | { "PMPADDR25", 171 }, |
| 35757 | { "PMPADDR26", 172 }, |
| 35758 | { "PMPADDR27", 173 }, |
| 35759 | { "PMPADDR28", 174 }, |
| 35760 | { "PMPADDR29", 175 }, |
| 35761 | { "PMPADDR3", 149 }, |
| 35762 | { "PMPADDR30", 176 }, |
| 35763 | { "PMPADDR31", 177 }, |
| 35764 | { "PMPADDR32", 178 }, |
| 35765 | { "PMPADDR33", 179 }, |
| 35766 | { "PMPADDR34", 180 }, |
| 35767 | { "PMPADDR35", 181 }, |
| 35768 | { "PMPADDR36", 182 }, |
| 35769 | { "PMPADDR37", 183 }, |
| 35770 | { "PMPADDR38", 184 }, |
| 35771 | { "PMPADDR39", 185 }, |
| 35772 | { "PMPADDR4", 150 }, |
| 35773 | { "PMPADDR40", 186 }, |
| 35774 | { "PMPADDR41", 187 }, |
| 35775 | { "PMPADDR42", 188 }, |
| 35776 | { "PMPADDR43", 189 }, |
| 35777 | { "PMPADDR44", 190 }, |
| 35778 | { "PMPADDR45", 191 }, |
| 35779 | { "PMPADDR46", 192 }, |
| 35780 | { "PMPADDR47", 193 }, |
| 35781 | { "PMPADDR48", 194 }, |
| 35782 | { "PMPADDR49", 195 }, |
| 35783 | { "PMPADDR5", 151 }, |
| 35784 | { "PMPADDR50", 196 }, |
| 35785 | { "PMPADDR51", 197 }, |
| 35786 | { "PMPADDR52", 198 }, |
| 35787 | { "PMPADDR53", 199 }, |
| 35788 | { "PMPADDR54", 200 }, |
| 35789 | { "PMPADDR55", 201 }, |
| 35790 | { "PMPADDR56", 202 }, |
| 35791 | { "PMPADDR57", 203 }, |
| 35792 | { "PMPADDR58", 204 }, |
| 35793 | { "PMPADDR59", 205 }, |
| 35794 | { "PMPADDR6", 152 }, |
| 35795 | { "PMPADDR60", 206 }, |
| 35796 | { "PMPADDR61", 207 }, |
| 35797 | { "PMPADDR62", 208 }, |
| 35798 | { "PMPADDR63", 209 }, |
| 35799 | { "PMPADDR7", 153 }, |
| 35800 | { "PMPADDR8", 154 }, |
| 35801 | { "PMPADDR9", 155 }, |
| 35802 | { "PMPCFG0", 130 }, |
| 35803 | { "PMPCFG1", 131 }, |
| 35804 | { "PMPCFG10", 140 }, |
| 35805 | { "PMPCFG11", 141 }, |
| 35806 | { "PMPCFG12", 142 }, |
| 35807 | { "PMPCFG13", 143 }, |
| 35808 | { "PMPCFG14", 144 }, |
| 35809 | { "PMPCFG15", 145 }, |
| 35810 | { "PMPCFG2", 132 }, |
| 35811 | { "PMPCFG3", 133 }, |
| 35812 | { "PMPCFG4", 134 }, |
| 35813 | { "PMPCFG5", 135 }, |
| 35814 | { "PMPCFG6", 136 }, |
| 35815 | { "PMPCFG7", 137 }, |
| 35816 | { "PMPCFG8", 138 }, |
| 35817 | { "PMPCFG9", 139 }, |
| 35818 | { "SATP", 37 }, |
| 35819 | { "SCAUSE", 23 }, |
| 35820 | { "SCONTEXT", 210 }, |
| 35821 | { "SCOUNTEREN", 13 }, |
| 35822 | { "SCOUNTINHIBIT", 20 }, |
| 35823 | { "SCOUNTOVF", 417 }, |
| 35824 | { "SEED", 8 }, |
| 35825 | { "SENVCFG", 14 }, |
| 35826 | { "SEPC", 22 }, |
| 35827 | { "SIE", 11 }, |
| 35828 | { "SIEH", 19 }, |
| 35829 | { "SIP", 25 }, |
| 35830 | { "SIPH", 31 }, |
| 35831 | { "SIREG", 28 }, |
| 35832 | { "SIREG2", 29 }, |
| 35833 | { "SIREG3", 30 }, |
| 35834 | { "SIREG4", 32 }, |
| 35835 | { "SIREG5", 33 }, |
| 35836 | { "SIREG6", 34 }, |
| 35837 | { "SISELECT", 27 }, |
| 35838 | { "SRMCFG", 38 }, |
| 35839 | { "SSCRATCH", 21 }, |
| 35840 | { "SSP", 7 }, |
| 35841 | { "SSTATEEN0", 15 }, |
| 35842 | { "SSTATEEN1", 16 }, |
| 35843 | { "SSTATEEN2", 17 }, |
| 35844 | { "SSTATEEN3", 18 }, |
| 35845 | { "SSTATUS", 10 }, |
| 35846 | { "STIMECMP", 26 }, |
| 35847 | { "STIMECMPH", 36 }, |
| 35848 | { "STOPEI", 35 }, |
| 35849 | { "STOPI", 418 }, |
| 35850 | { "STVAL", 24 }, |
| 35851 | { "STVEC", 12 }, |
| 35852 | { "TDATA1", 280 }, |
| 35853 | { "TDATA2", 281 }, |
| 35854 | { "TDATA3", 282 }, |
| 35855 | { "TIME", 351 }, |
| 35856 | { "TIMEH", 386 }, |
| 35857 | { "TSELECT", 279 }, |
| 35858 | { "VCSR", 6 }, |
| 35859 | { "VL", 382 }, |
| 35860 | { "VLENB", 384 }, |
| 35861 | { "VSATP", 59 }, |
| 35862 | { "VSCAUSE", 45 }, |
| 35863 | { "VSEPC", 44 }, |
| 35864 | { "VSIE", 40 }, |
| 35865 | { "VSIEH", 42 }, |
| 35866 | { "VSIP", 47 }, |
| 35867 | { "VSIPH", 53 }, |
| 35868 | { "VSIREG", 50 }, |
| 35869 | { "VSIREG2", 51 }, |
| 35870 | { "VSIREG3", 52 }, |
| 35871 | { "VSIREG4", 54 }, |
| 35872 | { "VSIREG5", 55 }, |
| 35873 | { "VSIREG6", 56 }, |
| 35874 | { "VSISELECT", 49 }, |
| 35875 | { "VSSCRATCH", 43 }, |
| 35876 | { "VSSTATUS", 39 }, |
| 35877 | { "VSTART", 3 }, |
| 35878 | { "VSTIMECMP", 48 }, |
| 35879 | { "VSTIMECMPH", 58 }, |
| 35880 | { "VSTOPEI", 57 }, |
| 35881 | { "VSTOPI", 420 }, |
| 35882 | { "VSTVAL", 46 }, |
| 35883 | { "VSTVEC", 41 }, |
| 35884 | { "VTYPE", 383 }, |
| 35885 | { "VXRM", 5 }, |
| 35886 | { "VXSAT", 4 }, |
| 35887 | }; |
| 35888 | |
| 35889 | struct KeyType { |
| 35890 | std::string AltName; |
| 35891 | }; |
| 35892 | KeyType Key = {AltName.upper()}; |
| 35893 | struct Comp { |
| 35894 | bool operator()(const IndexType &LHS, const KeyType &RHS) const { |
| 35895 | int CmpAltName = StringRef(LHS.AltName).compare(RHS.AltName); |
| 35896 | if (CmpAltName < 0) return true; |
| 35897 | if (CmpAltName > 0) return false; |
| 35898 | return false; |
| 35899 | } |
| 35900 | }; |
| 35901 | auto Table = ArrayRef(Index); |
| 35902 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 35903 | if (Idx == Table.end() || |
| 35904 | Key.AltName != Idx->AltName) |
| 35905 | return nullptr; |
| 35906 | |
| 35907 | return &SysRegsList[Idx->_index]; |
| 35908 | } |
| 35909 | |
| 35910 | const SysReg *lookupSysRegByDeprecatedName(StringRef DeprecatedName) { |
| 35911 | struct IndexType { |
| 35912 | const char * DeprecatedName; |
| 35913 | unsigned _index; |
| 35914 | }; |
| 35915 | static const struct IndexType Index[] = { |
| 35916 | { "", 0 }, |
| 35917 | { "", 1 }, |
| 35918 | { "", 2 }, |
| 35919 | { "", 3 }, |
| 35920 | { "", 4 }, |
| 35921 | { "", 5 }, |
| 35922 | { "", 6 }, |
| 35923 | { "", 7 }, |
| 35924 | { "", 8 }, |
| 35925 | { "", 9 }, |
| 35926 | { "", 10 }, |
| 35927 | { "", 11 }, |
| 35928 | { "", 12 }, |
| 35929 | { "", 13 }, |
| 35930 | { "", 14 }, |
| 35931 | { "", 15 }, |
| 35932 | { "", 16 }, |
| 35933 | { "", 17 }, |
| 35934 | { "", 18 }, |
| 35935 | { "", 19 }, |
| 35936 | { "", 20 }, |
| 35937 | { "", 21 }, |
| 35938 | { "", 22 }, |
| 35939 | { "", 23 }, |
| 35940 | { "", 25 }, |
| 35941 | { "", 26 }, |
| 35942 | { "", 27 }, |
| 35943 | { "", 28 }, |
| 35944 | { "", 29 }, |
| 35945 | { "", 30 }, |
| 35946 | { "", 31 }, |
| 35947 | { "", 32 }, |
| 35948 | { "", 33 }, |
| 35949 | { "", 34 }, |
| 35950 | { "", 35 }, |
| 35951 | { "", 36 }, |
| 35952 | { "", 38 }, |
| 35953 | { "", 39 }, |
| 35954 | { "", 40 }, |
| 35955 | { "", 41 }, |
| 35956 | { "", 42 }, |
| 35957 | { "", 43 }, |
| 35958 | { "", 44 }, |
| 35959 | { "", 45 }, |
| 35960 | { "", 46 }, |
| 35961 | { "", 47 }, |
| 35962 | { "", 48 }, |
| 35963 | { "", 49 }, |
| 35964 | { "", 50 }, |
| 35965 | { "", 51 }, |
| 35966 | { "", 52 }, |
| 35967 | { "", 53 }, |
| 35968 | { "", 54 }, |
| 35969 | { "", 55 }, |
| 35970 | { "", 56 }, |
| 35971 | { "", 57 }, |
| 35972 | { "", 58 }, |
| 35973 | { "", 59 }, |
| 35974 | { "", 60 }, |
| 35975 | { "", 61 }, |
| 35976 | { "", 62 }, |
| 35977 | { "", 63 }, |
| 35978 | { "", 64 }, |
| 35979 | { "", 65 }, |
| 35980 | { "", 66 }, |
| 35981 | { "", 67 }, |
| 35982 | { "", 68 }, |
| 35983 | { "", 69 }, |
| 35984 | { "", 70 }, |
| 35985 | { "", 71 }, |
| 35986 | { "", 72 }, |
| 35987 | { "", 73 }, |
| 35988 | { "", 74 }, |
| 35989 | { "", 75 }, |
| 35990 | { "", 76 }, |
| 35991 | { "", 77 }, |
| 35992 | { "", 78 }, |
| 35993 | { "", 79 }, |
| 35994 | { "", 80 }, |
| 35995 | { "", 81 }, |
| 35996 | { "", 82 }, |
| 35997 | { "", 83 }, |
| 35998 | { "", 84 }, |
| 35999 | { "", 85 }, |
| 36000 | { "", 86 }, |
| 36001 | { "", 87 }, |
| 36002 | { "", 88 }, |
| 36003 | { "", 89 }, |
| 36004 | { "", 90 }, |
| 36005 | { "", 91 }, |
| 36006 | { "", 92 }, |
| 36007 | { "", 93 }, |
| 36008 | { "", 94 }, |
| 36009 | { "", 95 }, |
| 36010 | { "", 96 }, |
| 36011 | { "", 97 }, |
| 36012 | { "", 98 }, |
| 36013 | { "", 99 }, |
| 36014 | { "", 100 }, |
| 36015 | { "", 101 }, |
| 36016 | { "", 102 }, |
| 36017 | { "", 103 }, |
| 36018 | { "", 104 }, |
| 36019 | { "", 105 }, |
| 36020 | { "", 106 }, |
| 36021 | { "", 107 }, |
| 36022 | { "", 108 }, |
| 36023 | { "", 109 }, |
| 36024 | { "", 110 }, |
| 36025 | { "", 111 }, |
| 36026 | { "", 112 }, |
| 36027 | { "", 113 }, |
| 36028 | { "", 114 }, |
| 36029 | { "", 115 }, |
| 36030 | { "", 116 }, |
| 36031 | { "", 118 }, |
| 36032 | { "", 119 }, |
| 36033 | { "", 120 }, |
| 36034 | { "", 121 }, |
| 36035 | { "", 122 }, |
| 36036 | { "", 123 }, |
| 36037 | { "", 124 }, |
| 36038 | { "", 125 }, |
| 36039 | { "", 126 }, |
| 36040 | { "", 127 }, |
| 36041 | { "", 128 }, |
| 36042 | { "", 129 }, |
| 36043 | { "", 130 }, |
| 36044 | { "", 131 }, |
| 36045 | { "", 132 }, |
| 36046 | { "", 133 }, |
| 36047 | { "", 134 }, |
| 36048 | { "", 135 }, |
| 36049 | { "", 136 }, |
| 36050 | { "", 137 }, |
| 36051 | { "", 138 }, |
| 36052 | { "", 139 }, |
| 36053 | { "", 140 }, |
| 36054 | { "", 141 }, |
| 36055 | { "", 142 }, |
| 36056 | { "", 143 }, |
| 36057 | { "", 144 }, |
| 36058 | { "", 145 }, |
| 36059 | { "", 146 }, |
| 36060 | { "", 147 }, |
| 36061 | { "", 148 }, |
| 36062 | { "", 149 }, |
| 36063 | { "", 150 }, |
| 36064 | { "", 151 }, |
| 36065 | { "", 152 }, |
| 36066 | { "", 153 }, |
| 36067 | { "", 154 }, |
| 36068 | { "", 155 }, |
| 36069 | { "", 156 }, |
| 36070 | { "", 157 }, |
| 36071 | { "", 158 }, |
| 36072 | { "", 159 }, |
| 36073 | { "", 160 }, |
| 36074 | { "", 161 }, |
| 36075 | { "", 162 }, |
| 36076 | { "", 163 }, |
| 36077 | { "", 164 }, |
| 36078 | { "", 165 }, |
| 36079 | { "", 166 }, |
| 36080 | { "", 167 }, |
| 36081 | { "", 168 }, |
| 36082 | { "", 169 }, |
| 36083 | { "", 170 }, |
| 36084 | { "", 171 }, |
| 36085 | { "", 172 }, |
| 36086 | { "", 173 }, |
| 36087 | { "", 174 }, |
| 36088 | { "", 175 }, |
| 36089 | { "", 176 }, |
| 36090 | { "", 177 }, |
| 36091 | { "", 178 }, |
| 36092 | { "", 179 }, |
| 36093 | { "", 180 }, |
| 36094 | { "", 181 }, |
| 36095 | { "", 182 }, |
| 36096 | { "", 183 }, |
| 36097 | { "", 184 }, |
| 36098 | { "", 185 }, |
| 36099 | { "", 186 }, |
| 36100 | { "", 187 }, |
| 36101 | { "", 188 }, |
| 36102 | { "", 189 }, |
| 36103 | { "", 190 }, |
| 36104 | { "", 191 }, |
| 36105 | { "", 192 }, |
| 36106 | { "", 193 }, |
| 36107 | { "", 194 }, |
| 36108 | { "", 195 }, |
| 36109 | { "", 196 }, |
| 36110 | { "", 197 }, |
| 36111 | { "", 198 }, |
| 36112 | { "", 199 }, |
| 36113 | { "", 200 }, |
| 36114 | { "", 201 }, |
| 36115 | { "", 202 }, |
| 36116 | { "", 203 }, |
| 36117 | { "", 204 }, |
| 36118 | { "", 205 }, |
| 36119 | { "", 206 }, |
| 36120 | { "", 207 }, |
| 36121 | { "", 208 }, |
| 36122 | { "", 209 }, |
| 36123 | { "", 210 }, |
| 36124 | { "", 211 }, |
| 36125 | { "", 212 }, |
| 36126 | { "", 213 }, |
| 36127 | { "", 214 }, |
| 36128 | { "", 215 }, |
| 36129 | { "", 216 }, |
| 36130 | { "", 217 }, |
| 36131 | { "", 218 }, |
| 36132 | { "", 219 }, |
| 36133 | { "", 220 }, |
| 36134 | { "", 221 }, |
| 36135 | { "", 222 }, |
| 36136 | { "", 223 }, |
| 36137 | { "", 224 }, |
| 36138 | { "", 225 }, |
| 36139 | { "", 226 }, |
| 36140 | { "", 227 }, |
| 36141 | { "", 228 }, |
| 36142 | { "", 229 }, |
| 36143 | { "", 230 }, |
| 36144 | { "", 231 }, |
| 36145 | { "", 232 }, |
| 36146 | { "", 233 }, |
| 36147 | { "", 234 }, |
| 36148 | { "", 235 }, |
| 36149 | { "", 236 }, |
| 36150 | { "", 237 }, |
| 36151 | { "", 238 }, |
| 36152 | { "", 239 }, |
| 36153 | { "", 240 }, |
| 36154 | { "", 241 }, |
| 36155 | { "", 242 }, |
| 36156 | { "", 243 }, |
| 36157 | { "", 244 }, |
| 36158 | { "", 245 }, |
| 36159 | { "", 246 }, |
| 36160 | { "", 247 }, |
| 36161 | { "", 248 }, |
| 36162 | { "", 249 }, |
| 36163 | { "", 250 }, |
| 36164 | { "", 251 }, |
| 36165 | { "", 252 }, |
| 36166 | { "", 253 }, |
| 36167 | { "", 254 }, |
| 36168 | { "", 255 }, |
| 36169 | { "", 256 }, |
| 36170 | { "", 257 }, |
| 36171 | { "", 258 }, |
| 36172 | { "", 259 }, |
| 36173 | { "", 260 }, |
| 36174 | { "", 261 }, |
| 36175 | { "", 262 }, |
| 36176 | { "", 263 }, |
| 36177 | { "", 264 }, |
| 36178 | { "", 265 }, |
| 36179 | { "", 266 }, |
| 36180 | { "", 267 }, |
| 36181 | { "", 268 }, |
| 36182 | { "", 269 }, |
| 36183 | { "", 270 }, |
| 36184 | { "", 271 }, |
| 36185 | { "", 272 }, |
| 36186 | { "", 273 }, |
| 36187 | { "", 274 }, |
| 36188 | { "", 275 }, |
| 36189 | { "", 276 }, |
| 36190 | { "", 277 }, |
| 36191 | { "", 278 }, |
| 36192 | { "", 279 }, |
| 36193 | { "", 280 }, |
| 36194 | { "", 281 }, |
| 36195 | { "", 282 }, |
| 36196 | { "", 283 }, |
| 36197 | { "", 284 }, |
| 36198 | { "", 285 }, |
| 36199 | { "", 286 }, |
| 36200 | { "", 287 }, |
| 36201 | { "", 288 }, |
| 36202 | { "", 289 }, |
| 36203 | { "", 290 }, |
| 36204 | { "", 291 }, |
| 36205 | { "", 292 }, |
| 36206 | { "", 293 }, |
| 36207 | { "", 294 }, |
| 36208 | { "", 295 }, |
| 36209 | { "", 296 }, |
| 36210 | { "", 297 }, |
| 36211 | { "", 298 }, |
| 36212 | { "", 299 }, |
| 36213 | { "", 300 }, |
| 36214 | { "", 301 }, |
| 36215 | { "", 302 }, |
| 36216 | { "", 303 }, |
| 36217 | { "", 304 }, |
| 36218 | { "", 305 }, |
| 36219 | { "", 306 }, |
| 36220 | { "", 307 }, |
| 36221 | { "", 308 }, |
| 36222 | { "", 309 }, |
| 36223 | { "", 310 }, |
| 36224 | { "", 311 }, |
| 36225 | { "", 312 }, |
| 36226 | { "", 313 }, |
| 36227 | { "", 314 }, |
| 36228 | { "", 315 }, |
| 36229 | { "", 316 }, |
| 36230 | { "", 317 }, |
| 36231 | { "", 318 }, |
| 36232 | { "", 319 }, |
| 36233 | { "", 320 }, |
| 36234 | { "", 321 }, |
| 36235 | { "", 322 }, |
| 36236 | { "", 323 }, |
| 36237 | { "", 324 }, |
| 36238 | { "", 325 }, |
| 36239 | { "", 326 }, |
| 36240 | { "", 327 }, |
| 36241 | { "", 328 }, |
| 36242 | { "", 329 }, |
| 36243 | { "", 330 }, |
| 36244 | { "", 331 }, |
| 36245 | { "", 332 }, |
| 36246 | { "", 333 }, |
| 36247 | { "", 334 }, |
| 36248 | { "", 335 }, |
| 36249 | { "", 336 }, |
| 36250 | { "", 337 }, |
| 36251 | { "", 338 }, |
| 36252 | { "", 339 }, |
| 36253 | { "", 340 }, |
| 36254 | { "", 341 }, |
| 36255 | { "", 342 }, |
| 36256 | { "", 343 }, |
| 36257 | { "", 344 }, |
| 36258 | { "", 345 }, |
| 36259 | { "", 346 }, |
| 36260 | { "", 347 }, |
| 36261 | { "", 348 }, |
| 36262 | { "", 349 }, |
| 36263 | { "", 350 }, |
| 36264 | { "", 351 }, |
| 36265 | { "", 352 }, |
| 36266 | { "", 353 }, |
| 36267 | { "", 354 }, |
| 36268 | { "", 355 }, |
| 36269 | { "", 356 }, |
| 36270 | { "", 357 }, |
| 36271 | { "", 358 }, |
| 36272 | { "", 359 }, |
| 36273 | { "", 360 }, |
| 36274 | { "", 361 }, |
| 36275 | { "", 362 }, |
| 36276 | { "", 363 }, |
| 36277 | { "", 364 }, |
| 36278 | { "", 365 }, |
| 36279 | { "", 366 }, |
| 36280 | { "", 367 }, |
| 36281 | { "", 368 }, |
| 36282 | { "", 369 }, |
| 36283 | { "", 370 }, |
| 36284 | { "", 371 }, |
| 36285 | { "", 372 }, |
| 36286 | { "", 373 }, |
| 36287 | { "", 374 }, |
| 36288 | { "", 375 }, |
| 36289 | { "", 376 }, |
| 36290 | { "", 377 }, |
| 36291 | { "", 378 }, |
| 36292 | { "", 379 }, |
| 36293 | { "", 380 }, |
| 36294 | { "", 381 }, |
| 36295 | { "", 382 }, |
| 36296 | { "", 383 }, |
| 36297 | { "", 384 }, |
| 36298 | { "", 385 }, |
| 36299 | { "", 386 }, |
| 36300 | { "", 387 }, |
| 36301 | { "", 388 }, |
| 36302 | { "", 389 }, |
| 36303 | { "", 390 }, |
| 36304 | { "", 391 }, |
| 36305 | { "", 392 }, |
| 36306 | { "", 393 }, |
| 36307 | { "", 394 }, |
| 36308 | { "", 395 }, |
| 36309 | { "", 396 }, |
| 36310 | { "", 397 }, |
| 36311 | { "", 398 }, |
| 36312 | { "", 399 }, |
| 36313 | { "", 400 }, |
| 36314 | { "", 401 }, |
| 36315 | { "", 402 }, |
| 36316 | { "", 403 }, |
| 36317 | { "", 404 }, |
| 36318 | { "", 405 }, |
| 36319 | { "", 406 }, |
| 36320 | { "", 407 }, |
| 36321 | { "", 408 }, |
| 36322 | { "", 409 }, |
| 36323 | { "", 410 }, |
| 36324 | { "", 411 }, |
| 36325 | { "", 412 }, |
| 36326 | { "", 413 }, |
| 36327 | { "", 414 }, |
| 36328 | { "", 415 }, |
| 36329 | { "", 416 }, |
| 36330 | { "", 417 }, |
| 36331 | { "", 418 }, |
| 36332 | { "", 419 }, |
| 36333 | { "", 420 }, |
| 36334 | { "", 421 }, |
| 36335 | { "", 422 }, |
| 36336 | { "", 423 }, |
| 36337 | { "", 424 }, |
| 36338 | { "", 425 }, |
| 36339 | { "", 426 }, |
| 36340 | { "MBADADDR", 117 }, |
| 36341 | { "SBADADDR", 24 }, |
| 36342 | { "SPTBR", 37 }, |
| 36343 | }; |
| 36344 | |
| 36345 | struct KeyType { |
| 36346 | std::string DeprecatedName; |
| 36347 | }; |
| 36348 | KeyType Key = {DeprecatedName.upper()}; |
| 36349 | struct Comp { |
| 36350 | bool operator()(const IndexType &LHS, const KeyType &RHS) const { |
| 36351 | int CmpDeprecatedName = StringRef(LHS.DeprecatedName).compare(RHS.DeprecatedName); |
| 36352 | if (CmpDeprecatedName < 0) return true; |
| 36353 | if (CmpDeprecatedName > 0) return false; |
| 36354 | return false; |
| 36355 | } |
| 36356 | }; |
| 36357 | auto Table = ArrayRef(Index); |
| 36358 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 36359 | if (Idx == Table.end() || |
| 36360 | Key.DeprecatedName != Idx->DeprecatedName) |
| 36361 | return nullptr; |
| 36362 | |
| 36363 | return &SysRegsList[Idx->_index]; |
| 36364 | } |
| 36365 | |
| 36366 | const SysReg *lookupSysRegByName(StringRef Name) { |
| 36367 | struct IndexType { |
| 36368 | const char * Name; |
| 36369 | unsigned _index; |
| 36370 | }; |
| 36371 | static const struct IndexType Index[] = { |
| 36372 | { "CYCLE", 350 }, |
| 36373 | { "CYCLEH", 385 }, |
| 36374 | { "DCSR", 284 }, |
| 36375 | { "DPC", 285 }, |
| 36376 | { "DSCRATCH0", 286 }, |
| 36377 | { "DSCRATCH1", 287 }, |
| 36378 | { "FCSR", 2 }, |
| 36379 | { "FFLAGS", 0 }, |
| 36380 | { "FRM", 1 }, |
| 36381 | { "HCONTEXT", 243 }, |
| 36382 | { "HCOUNTEREN", 216 }, |
| 36383 | { "HEDELEG", 212 }, |
| 36384 | { "HENVCFG", 220 }, |
| 36385 | { "HENVCFGH", 228 }, |
| 36386 | { "HGATP", 242 }, |
| 36387 | { "HGEIE", 217 }, |
| 36388 | { "HGEIP", 419 }, |
| 36389 | { "HIDELEG", 213 }, |
| 36390 | { "HIDELEGH", 225 }, |
| 36391 | { "HIE", 214 }, |
| 36392 | { "HIP", 234 }, |
| 36393 | { "HPMCOUNTER10", 360 }, |
| 36394 | { "HPMCOUNTER10H", 395 }, |
| 36395 | { "HPMCOUNTER11", 361 }, |
| 36396 | { "HPMCOUNTER11H", 396 }, |
| 36397 | { "HPMCOUNTER12", 362 }, |
| 36398 | { "HPMCOUNTER12H", 397 }, |
| 36399 | { "HPMCOUNTER13", 363 }, |
| 36400 | { "HPMCOUNTER13H", 398 }, |
| 36401 | { "HPMCOUNTER14", 364 }, |
| 36402 | { "HPMCOUNTER14H", 399 }, |
| 36403 | { "HPMCOUNTER15", 365 }, |
| 36404 | { "HPMCOUNTER15H", 400 }, |
| 36405 | { "HPMCOUNTER16", 366 }, |
| 36406 | { "HPMCOUNTER16H", 401 }, |
| 36407 | { "HPMCOUNTER17", 367 }, |
| 36408 | { "HPMCOUNTER17H", 402 }, |
| 36409 | { "HPMCOUNTER18", 368 }, |
| 36410 | { "HPMCOUNTER18H", 403 }, |
| 36411 | { "HPMCOUNTER19", 369 }, |
| 36412 | { "HPMCOUNTER19H", 404 }, |
| 36413 | { "HPMCOUNTER20", 370 }, |
| 36414 | { "HPMCOUNTER20H", 405 }, |
| 36415 | { "HPMCOUNTER21", 371 }, |
| 36416 | { "HPMCOUNTER21H", 406 }, |
| 36417 | { "HPMCOUNTER22", 372 }, |
| 36418 | { "HPMCOUNTER22H", 407 }, |
| 36419 | { "HPMCOUNTER23", 373 }, |
| 36420 | { "HPMCOUNTER23H", 408 }, |
| 36421 | { "HPMCOUNTER24", 374 }, |
| 36422 | { "HPMCOUNTER24H", 409 }, |
| 36423 | { "HPMCOUNTER25", 375 }, |
| 36424 | { "HPMCOUNTER25H", 410 }, |
| 36425 | { "HPMCOUNTER26", 376 }, |
| 36426 | { "HPMCOUNTER26H", 411 }, |
| 36427 | { "HPMCOUNTER27", 377 }, |
| 36428 | { "HPMCOUNTER27H", 412 }, |
| 36429 | { "HPMCOUNTER28", 378 }, |
| 36430 | { "HPMCOUNTER28H", 413 }, |
| 36431 | { "HPMCOUNTER29", 379 }, |
| 36432 | { "HPMCOUNTER29H", 414 }, |
| 36433 | { "HPMCOUNTER3", 353 }, |
| 36434 | { "HPMCOUNTER30", 380 }, |
| 36435 | { "HPMCOUNTER30H", 415 }, |
| 36436 | { "HPMCOUNTER31", 381 }, |
| 36437 | { "HPMCOUNTER31H", 416 }, |
| 36438 | { "HPMCOUNTER3H", 388 }, |
| 36439 | { "HPMCOUNTER4", 354 }, |
| 36440 | { "HPMCOUNTER4H", 389 }, |
| 36441 | { "HPMCOUNTER5", 355 }, |
| 36442 | { "HPMCOUNTER5H", 390 }, |
| 36443 | { "HPMCOUNTER6", 356 }, |
| 36444 | { "HPMCOUNTER6H", 391 }, |
| 36445 | { "HPMCOUNTER7", 357 }, |
| 36446 | { "HPMCOUNTER7H", 392 }, |
| 36447 | { "HPMCOUNTER8", 358 }, |
| 36448 | { "HPMCOUNTER8H", 393 }, |
| 36449 | { "HPMCOUNTER9", 359 }, |
| 36450 | { "HPMCOUNTER9H", 394 }, |
| 36451 | { "HSTATEEN0", 221 }, |
| 36452 | { "HSTATEEN0H", 229 }, |
| 36453 | { "HSTATEEN1", 222 }, |
| 36454 | { "HSTATEEN1H", 230 }, |
| 36455 | { "HSTATEEN2", 223 }, |
| 36456 | { "HSTATEEN2H", 231 }, |
| 36457 | { "HSTATEEN3", 224 }, |
| 36458 | { "HSTATEEN3H", 232 }, |
| 36459 | { "HSTATUS", 211 }, |
| 36460 | { "HTIMEDELTA", 215 }, |
| 36461 | { "HTIMEDELTAH", 226 }, |
| 36462 | { "HTINST", 238 }, |
| 36463 | { "HTVAL", 233 }, |
| 36464 | { "HVICTL", 219 }, |
| 36465 | { "HVIEN", 218 }, |
| 36466 | { "HVIENH", 227 }, |
| 36467 | { "HVIP", 235 }, |
| 36468 | { "HVIPH", 239 }, |
| 36469 | { "HVIPRIO1", 236 }, |
| 36470 | { "HVIPRIO1H", 240 }, |
| 36471 | { "HVIPRIO2", 237 }, |
| 36472 | { "HVIPRIO2H", 241 }, |
| 36473 | { "INSTRET", 352 }, |
| 36474 | { "INSTRETH", 387 }, |
| 36475 | { "JVT", 9 }, |
| 36476 | { "MARCHID", 422 }, |
| 36477 | { "MCAUSE", 116 }, |
| 36478 | { "MCONFIGPTR", 425 }, |
| 36479 | { "MCONTEXT", 283 }, |
| 36480 | { "MCOUNTEREN", 66 }, |
| 36481 | { "MCOUNTINHIBIT", 84 }, |
| 36482 | { "MCYCLE", 288 }, |
| 36483 | { "MCYCLEH", 319 }, |
| 36484 | { "MEDELEG", 62 }, |
| 36485 | { "MENVCFG", 69 }, |
| 36486 | { "MENVCFGH", 79 }, |
| 36487 | { "MEPC", 115 }, |
| 36488 | { "MHARTID", 424 }, |
| 36489 | { "MHPMCOUNTER10", 297 }, |
| 36490 | { "MHPMCOUNTER10H", 328 }, |
| 36491 | { "MHPMCOUNTER11", 298 }, |
| 36492 | { "MHPMCOUNTER11H", 329 }, |
| 36493 | { "MHPMCOUNTER12", 299 }, |
| 36494 | { "MHPMCOUNTER12H", 330 }, |
| 36495 | { "MHPMCOUNTER13", 300 }, |
| 36496 | { "MHPMCOUNTER13H", 331 }, |
| 36497 | { "MHPMCOUNTER14", 301 }, |
| 36498 | { "MHPMCOUNTER14H", 332 }, |
| 36499 | { "MHPMCOUNTER15", 302 }, |
| 36500 | { "MHPMCOUNTER15H", 333 }, |
| 36501 | { "MHPMCOUNTER16", 303 }, |
| 36502 | { "MHPMCOUNTER16H", 334 }, |
| 36503 | { "MHPMCOUNTER17", 304 }, |
| 36504 | { "MHPMCOUNTER17H", 335 }, |
| 36505 | { "MHPMCOUNTER18", 305 }, |
| 36506 | { "MHPMCOUNTER18H", 336 }, |
| 36507 | { "MHPMCOUNTER19", 306 }, |
| 36508 | { "MHPMCOUNTER19H", 337 }, |
| 36509 | { "MHPMCOUNTER20", 307 }, |
| 36510 | { "MHPMCOUNTER20H", 338 }, |
| 36511 | { "MHPMCOUNTER21", 308 }, |
| 36512 | { "MHPMCOUNTER21H", 339 }, |
| 36513 | { "MHPMCOUNTER22", 309 }, |
| 36514 | { "MHPMCOUNTER22H", 340 }, |
| 36515 | { "MHPMCOUNTER23", 310 }, |
| 36516 | { "MHPMCOUNTER23H", 341 }, |
| 36517 | { "MHPMCOUNTER24", 311 }, |
| 36518 | { "MHPMCOUNTER24H", 342 }, |
| 36519 | { "MHPMCOUNTER25", 312 }, |
| 36520 | { "MHPMCOUNTER25H", 343 }, |
| 36521 | { "MHPMCOUNTER26", 313 }, |
| 36522 | { "MHPMCOUNTER26H", 344 }, |
| 36523 | { "MHPMCOUNTER27", 314 }, |
| 36524 | { "MHPMCOUNTER27H", 345 }, |
| 36525 | { "MHPMCOUNTER28", 315 }, |
| 36526 | { "MHPMCOUNTER28H", 346 }, |
| 36527 | { "MHPMCOUNTER29", 316 }, |
| 36528 | { "MHPMCOUNTER29H", 347 }, |
| 36529 | { "MHPMCOUNTER3", 290 }, |
| 36530 | { "MHPMCOUNTER30", 317 }, |
| 36531 | { "MHPMCOUNTER30H", 348 }, |
| 36532 | { "MHPMCOUNTER31", 318 }, |
| 36533 | { "MHPMCOUNTER31H", 349 }, |
| 36534 | { "MHPMCOUNTER3H", 321 }, |
| 36535 | { "MHPMCOUNTER4", 291 }, |
| 36536 | { "MHPMCOUNTER4H", 322 }, |
| 36537 | { "MHPMCOUNTER5", 292 }, |
| 36538 | { "MHPMCOUNTER5H", 323 }, |
| 36539 | { "MHPMCOUNTER6", 293 }, |
| 36540 | { "MHPMCOUNTER6H", 324 }, |
| 36541 | { "MHPMCOUNTER7", 294 }, |
| 36542 | { "MHPMCOUNTER7H", 325 }, |
| 36543 | { "MHPMCOUNTER8", 295 }, |
| 36544 | { "MHPMCOUNTER8H", 326 }, |
| 36545 | { "MHPMCOUNTER9", 296 }, |
| 36546 | { "MHPMCOUNTER9H", 327 }, |
| 36547 | { "MHPMEVENT10", 92 }, |
| 36548 | { "MHPMEVENT10H", 251 }, |
| 36549 | { "MHPMEVENT11", 93 }, |
| 36550 | { "MHPMEVENT11H", 252 }, |
| 36551 | { "MHPMEVENT12", 94 }, |
| 36552 | { "MHPMEVENT12H", 253 }, |
| 36553 | { "MHPMEVENT13", 95 }, |
| 36554 | { "MHPMEVENT13H", 254 }, |
| 36555 | { "MHPMEVENT14", 96 }, |
| 36556 | { "MHPMEVENT14H", 255 }, |
| 36557 | { "MHPMEVENT15", 97 }, |
| 36558 | { "MHPMEVENT15H", 256 }, |
| 36559 | { "MHPMEVENT16", 98 }, |
| 36560 | { "MHPMEVENT16H", 257 }, |
| 36561 | { "MHPMEVENT17", 99 }, |
| 36562 | { "MHPMEVENT17H", 258 }, |
| 36563 | { "MHPMEVENT18", 100 }, |
| 36564 | { "MHPMEVENT18H", 259 }, |
| 36565 | { "MHPMEVENT19", 101 }, |
| 36566 | { "MHPMEVENT19H", 260 }, |
| 36567 | { "MHPMEVENT20", 102 }, |
| 36568 | { "MHPMEVENT20H", 261 }, |
| 36569 | { "MHPMEVENT21", 103 }, |
| 36570 | { "MHPMEVENT21H", 262 }, |
| 36571 | { "MHPMEVENT22", 104 }, |
| 36572 | { "MHPMEVENT22H", 263 }, |
| 36573 | { "MHPMEVENT23", 105 }, |
| 36574 | { "MHPMEVENT23H", 264 }, |
| 36575 | { "MHPMEVENT24", 106 }, |
| 36576 | { "MHPMEVENT24H", 265 }, |
| 36577 | { "MHPMEVENT25", 107 }, |
| 36578 | { "MHPMEVENT25H", 266 }, |
| 36579 | { "MHPMEVENT26", 108 }, |
| 36580 | { "MHPMEVENT26H", 267 }, |
| 36581 | { "MHPMEVENT27", 109 }, |
| 36582 | { "MHPMEVENT27H", 268 }, |
| 36583 | { "MHPMEVENT28", 110 }, |
| 36584 | { "MHPMEVENT28H", 269 }, |
| 36585 | { "MHPMEVENT29", 111 }, |
| 36586 | { "MHPMEVENT29H", 270 }, |
| 36587 | { "MHPMEVENT3", 85 }, |
| 36588 | { "MHPMEVENT30", 112 }, |
| 36589 | { "MHPMEVENT30H", 271 }, |
| 36590 | { "MHPMEVENT31", 113 }, |
| 36591 | { "MHPMEVENT31H", 272 }, |
| 36592 | { "MHPMEVENT3H", 244 }, |
| 36593 | { "MHPMEVENT4", 86 }, |
| 36594 | { "MHPMEVENT4H", 245 }, |
| 36595 | { "MHPMEVENT5", 87 }, |
| 36596 | { "MHPMEVENT5H", 246 }, |
| 36597 | { "MHPMEVENT6", 88 }, |
| 36598 | { "MHPMEVENT6H", 247 }, |
| 36599 | { "MHPMEVENT7", 89 }, |
| 36600 | { "MHPMEVENT7H", 248 }, |
| 36601 | { "MHPMEVENT8", 90 }, |
| 36602 | { "MHPMEVENT8H", 249 }, |
| 36603 | { "MHPMEVENT9", 91 }, |
| 36604 | { "MHPMEVENT9H", 250 }, |
| 36605 | { "MIDELEG", 63 }, |
| 36606 | { "MIDELEGH", 75 }, |
| 36607 | { "MIE", 64 }, |
| 36608 | { "MIEH", 76 }, |
| 36609 | { "MIMPID", 423 }, |
| 36610 | { "MINSTRET", 289 }, |
| 36611 | { "MINSTRETH", 320 }, |
| 36612 | { "MIP", 118 }, |
| 36613 | { "MIPH", 125 }, |
| 36614 | { "MIREG", 122 }, |
| 36615 | { "MIREG2", 123 }, |
| 36616 | { "MIREG3", 124 }, |
| 36617 | { "MIREG4", 126 }, |
| 36618 | { "MIREG5", 127 }, |
| 36619 | { "MIREG6", 128 }, |
| 36620 | { "MISA", 61 }, |
| 36621 | { "MISELECT", 121 }, |
| 36622 | { "MNCAUSE", 275 }, |
| 36623 | { "MNEPC", 274 }, |
| 36624 | { "MNSCRATCH", 273 }, |
| 36625 | { "MNSTATUS", 276 }, |
| 36626 | { "MSCRATCH", 114 }, |
| 36627 | { "MSECCFG", 277 }, |
| 36628 | { "MSECCFGH", 278 }, |
| 36629 | { "MSTATEEN0", 70 }, |
| 36630 | { "MSTATEEN0H", 80 }, |
| 36631 | { "MSTATEEN1", 71 }, |
| 36632 | { "MSTATEEN1H", 81 }, |
| 36633 | { "MSTATEEN2", 72 }, |
| 36634 | { "MSTATEEN2H", 82 }, |
| 36635 | { "MSTATEEN3", 73 }, |
| 36636 | { "MSTATEEN3H", 83 }, |
| 36637 | { "MSTATUS", 60 }, |
| 36638 | { "MSTATUSH", 74 }, |
| 36639 | { "MTINST", 119 }, |
| 36640 | { "MTOPEI", 129 }, |
| 36641 | { "MTOPI", 426 }, |
| 36642 | { "MTVAL", 117 }, |
| 36643 | { "MTVAL2", 120 }, |
| 36644 | { "MTVEC", 65 }, |
| 36645 | { "MVENDORID", 421 }, |
| 36646 | { "MVIEN", 67 }, |
| 36647 | { "MVIENH", 77 }, |
| 36648 | { "MVIP", 68 }, |
| 36649 | { "MVIPH", 78 }, |
| 36650 | { "PMPADDR0", 146 }, |
| 36651 | { "PMPADDR1", 147 }, |
| 36652 | { "PMPADDR10", 156 }, |
| 36653 | { "PMPADDR11", 157 }, |
| 36654 | { "PMPADDR12", 158 }, |
| 36655 | { "PMPADDR13", 159 }, |
| 36656 | { "PMPADDR14", 160 }, |
| 36657 | { "PMPADDR15", 161 }, |
| 36658 | { "PMPADDR16", 162 }, |
| 36659 | { "PMPADDR17", 163 }, |
| 36660 | { "PMPADDR18", 164 }, |
| 36661 | { "PMPADDR19", 165 }, |
| 36662 | { "PMPADDR2", 148 }, |
| 36663 | { "PMPADDR20", 166 }, |
| 36664 | { "PMPADDR21", 167 }, |
| 36665 | { "PMPADDR22", 168 }, |
| 36666 | { "PMPADDR23", 169 }, |
| 36667 | { "PMPADDR24", 170 }, |
| 36668 | { "PMPADDR25", 171 }, |
| 36669 | { "PMPADDR26", 172 }, |
| 36670 | { "PMPADDR27", 173 }, |
| 36671 | { "PMPADDR28", 174 }, |
| 36672 | { "PMPADDR29", 175 }, |
| 36673 | { "PMPADDR3", 149 }, |
| 36674 | { "PMPADDR30", 176 }, |
| 36675 | { "PMPADDR31", 177 }, |
| 36676 | { "PMPADDR32", 178 }, |
| 36677 | { "PMPADDR33", 179 }, |
| 36678 | { "PMPADDR34", 180 }, |
| 36679 | { "PMPADDR35", 181 }, |
| 36680 | { "PMPADDR36", 182 }, |
| 36681 | { "PMPADDR37", 183 }, |
| 36682 | { "PMPADDR38", 184 }, |
| 36683 | { "PMPADDR39", 185 }, |
| 36684 | { "PMPADDR4", 150 }, |
| 36685 | { "PMPADDR40", 186 }, |
| 36686 | { "PMPADDR41", 187 }, |
| 36687 | { "PMPADDR42", 188 }, |
| 36688 | { "PMPADDR43", 189 }, |
| 36689 | { "PMPADDR44", 190 }, |
| 36690 | { "PMPADDR45", 191 }, |
| 36691 | { "PMPADDR46", 192 }, |
| 36692 | { "PMPADDR47", 193 }, |
| 36693 | { "PMPADDR48", 194 }, |
| 36694 | { "PMPADDR49", 195 }, |
| 36695 | { "PMPADDR5", 151 }, |
| 36696 | { "PMPADDR50", 196 }, |
| 36697 | { "PMPADDR51", 197 }, |
| 36698 | { "PMPADDR52", 198 }, |
| 36699 | { "PMPADDR53", 199 }, |
| 36700 | { "PMPADDR54", 200 }, |
| 36701 | { "PMPADDR55", 201 }, |
| 36702 | { "PMPADDR56", 202 }, |
| 36703 | { "PMPADDR57", 203 }, |
| 36704 | { "PMPADDR58", 204 }, |
| 36705 | { "PMPADDR59", 205 }, |
| 36706 | { "PMPADDR6", 152 }, |
| 36707 | { "PMPADDR60", 206 }, |
| 36708 | { "PMPADDR61", 207 }, |
| 36709 | { "PMPADDR62", 208 }, |
| 36710 | { "PMPADDR63", 209 }, |
| 36711 | { "PMPADDR7", 153 }, |
| 36712 | { "PMPADDR8", 154 }, |
| 36713 | { "PMPADDR9", 155 }, |
| 36714 | { "PMPCFG0", 130 }, |
| 36715 | { "PMPCFG1", 131 }, |
| 36716 | { "PMPCFG10", 140 }, |
| 36717 | { "PMPCFG11", 141 }, |
| 36718 | { "PMPCFG12", 142 }, |
| 36719 | { "PMPCFG13", 143 }, |
| 36720 | { "PMPCFG14", 144 }, |
| 36721 | { "PMPCFG15", 145 }, |
| 36722 | { "PMPCFG2", 132 }, |
| 36723 | { "PMPCFG3", 133 }, |
| 36724 | { "PMPCFG4", 134 }, |
| 36725 | { "PMPCFG5", 135 }, |
| 36726 | { "PMPCFG6", 136 }, |
| 36727 | { "PMPCFG7", 137 }, |
| 36728 | { "PMPCFG8", 138 }, |
| 36729 | { "PMPCFG9", 139 }, |
| 36730 | { "SATP", 37 }, |
| 36731 | { "SCAUSE", 23 }, |
| 36732 | { "SCONTEXT", 210 }, |
| 36733 | { "SCOUNTEREN", 13 }, |
| 36734 | { "SCOUNTINHIBIT", 20 }, |
| 36735 | { "SCOUNTOVF", 417 }, |
| 36736 | { "SEED", 8 }, |
| 36737 | { "SENVCFG", 14 }, |
| 36738 | { "SEPC", 22 }, |
| 36739 | { "SIE", 11 }, |
| 36740 | { "SIEH", 19 }, |
| 36741 | { "SIP", 25 }, |
| 36742 | { "SIPH", 31 }, |
| 36743 | { "SIREG", 28 }, |
| 36744 | { "SIREG2", 29 }, |
| 36745 | { "SIREG3", 30 }, |
| 36746 | { "SIREG4", 32 }, |
| 36747 | { "SIREG5", 33 }, |
| 36748 | { "SIREG6", 34 }, |
| 36749 | { "SISELECT", 27 }, |
| 36750 | { "SRMCFG", 38 }, |
| 36751 | { "SSCRATCH", 21 }, |
| 36752 | { "SSP", 7 }, |
| 36753 | { "SSTATEEN0", 15 }, |
| 36754 | { "SSTATEEN1", 16 }, |
| 36755 | { "SSTATEEN2", 17 }, |
| 36756 | { "SSTATEEN3", 18 }, |
| 36757 | { "SSTATUS", 10 }, |
| 36758 | { "STIMECMP", 26 }, |
| 36759 | { "STIMECMPH", 36 }, |
| 36760 | { "STOPEI", 35 }, |
| 36761 | { "STOPI", 418 }, |
| 36762 | { "STVAL", 24 }, |
| 36763 | { "STVEC", 12 }, |
| 36764 | { "TDATA1", 280 }, |
| 36765 | { "TDATA2", 281 }, |
| 36766 | { "TDATA3", 282 }, |
| 36767 | { "TIME", 351 }, |
| 36768 | { "TIMEH", 386 }, |
| 36769 | { "TSELECT", 279 }, |
| 36770 | { "VCSR", 6 }, |
| 36771 | { "VL", 382 }, |
| 36772 | { "VLENB", 384 }, |
| 36773 | { "VSATP", 59 }, |
| 36774 | { "VSCAUSE", 45 }, |
| 36775 | { "VSEPC", 44 }, |
| 36776 | { "VSIE", 40 }, |
| 36777 | { "VSIEH", 42 }, |
| 36778 | { "VSIP", 47 }, |
| 36779 | { "VSIPH", 53 }, |
| 36780 | { "VSIREG", 50 }, |
| 36781 | { "VSIREG2", 51 }, |
| 36782 | { "VSIREG3", 52 }, |
| 36783 | { "VSIREG4", 54 }, |
| 36784 | { "VSIREG5", 55 }, |
| 36785 | { "VSIREG6", 56 }, |
| 36786 | { "VSISELECT", 49 }, |
| 36787 | { "VSSCRATCH", 43 }, |
| 36788 | { "VSSTATUS", 39 }, |
| 36789 | { "VSTART", 3 }, |
| 36790 | { "VSTIMECMP", 48 }, |
| 36791 | { "VSTIMECMPH", 58 }, |
| 36792 | { "VSTOPEI", 57 }, |
| 36793 | { "VSTOPI", 420 }, |
| 36794 | { "VSTVAL", 46 }, |
| 36795 | { "VSTVEC", 41 }, |
| 36796 | { "VTYPE", 383 }, |
| 36797 | { "VXRM", 5 }, |
| 36798 | { "VXSAT", 4 }, |
| 36799 | }; |
| 36800 | |
| 36801 | struct KeyType { |
| 36802 | std::string Name; |
| 36803 | }; |
| 36804 | KeyType Key = {Name.upper()}; |
| 36805 | struct Comp { |
| 36806 | bool operator()(const IndexType &LHS, const KeyType &RHS) const { |
| 36807 | int CmpName = StringRef(LHS.Name).compare(RHS.Name); |
| 36808 | if (CmpName < 0) return true; |
| 36809 | if (CmpName > 0) return false; |
| 36810 | return false; |
| 36811 | } |
| 36812 | }; |
| 36813 | auto Table = ArrayRef(Index); |
| 36814 | auto Idx = std::lower_bound(Table.begin(), Table.end(), Key, Comp()); |
| 36815 | if (Idx == Table.end() || |
| 36816 | Key.Name != Idx->Name) |
| 36817 | return nullptr; |
| 36818 | |
| 36819 | return &SysRegsList[Idx->_index]; |
| 36820 | } |
| 36821 | #endif |
| 36822 | |
| 36823 | #undef GET_RISCVMaskedPseudosTable_DECL |
| 36824 | #undef GET_RISCVMaskedPseudosTable_IMPL |
| 36825 | #undef GET_RISCVOpcodesList_DECL |
| 36826 | #undef GET_RISCVOpcodesList_IMPL |
| 36827 | #undef GET_RISCVTuneInfoTable_DECL |
| 36828 | #undef GET_RISCVTuneInfoTable_IMPL |
| 36829 | #undef GET_RISCVVIntrinsicsTable_DECL |
| 36830 | #undef GET_RISCVVIntrinsicsTable_IMPL |
| 36831 | #undef GET_RISCVVInversePseudosTable_DECL |
| 36832 | #undef GET_RISCVVInversePseudosTable_IMPL |
| 36833 | #undef GET_RISCVVLETable_DECL |
| 36834 | #undef GET_RISCVVLETable_IMPL |
| 36835 | #undef GET_RISCVVLSEGTable_DECL |
| 36836 | #undef GET_RISCVVLSEGTable_IMPL |
| 36837 | #undef GET_RISCVVLXSEGTable_DECL |
| 36838 | #undef GET_RISCVVLXSEGTable_IMPL |
| 36839 | #undef GET_RISCVVLXTable_DECL |
| 36840 | #undef GET_RISCVVLXTable_IMPL |
| 36841 | #undef GET_RISCVVPseudosTable_DECL |
| 36842 | #undef GET_RISCVVPseudosTable_IMPL |
| 36843 | #undef GET_RISCVVSETable_DECL |
| 36844 | #undef GET_RISCVVSETable_IMPL |
| 36845 | #undef GET_RISCVVSSEGTable_DECL |
| 36846 | #undef GET_RISCVVSSEGTable_IMPL |
| 36847 | #undef GET_RISCVVSXSEGTable_DECL |
| 36848 | #undef GET_RISCVVSXSEGTable_IMPL |
| 36849 | #undef GET_RISCVVSXTable_DECL |
| 36850 | #undef GET_RISCVVSXTable_IMPL |
| 36851 | #undef GET_SysRegsList_DECL |
| 36852 | #undef GET_SysRegsList_IMPL |
| 36853 |
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