1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm {
12
13namespace SP {
14 enum {
15 PHI = 0,
16 INLINEASM = 1,
17 INLINEASM_BR = 2,
18 CFI_INSTRUCTION = 3,
19 EH_LABEL = 4,
20 GC_LABEL = 5,
21 ANNOTATION_LABEL = 6,
22 KILL = 7,
23 EXTRACT_SUBREG = 8,
24 INSERT_SUBREG = 9,
25 IMPLICIT_DEF = 10,
26 SUBREG_TO_REG = 11,
27 COPY_TO_REGCLASS = 12,
28 DBG_VALUE = 13,
29 DBG_VALUE_LIST = 14,
30 DBG_INSTR_REF = 15,
31 DBG_PHI = 16,
32 DBG_LABEL = 17,
33 REG_SEQUENCE = 18,
34 COPY = 19,
35 BUNDLE = 20,
36 LIFETIME_START = 21,
37 LIFETIME_END = 22,
38 PSEUDO_PROBE = 23,
39 ARITH_FENCE = 24,
40 STACKMAP = 25,
41 FENTRY_CALL = 26,
42 PATCHPOINT = 27,
43 LOAD_STACK_GUARD = 28,
44 PREALLOCATED_SETUP = 29,
45 PREALLOCATED_ARG = 30,
46 STATEPOINT = 31,
47 LOCAL_ESCAPE = 32,
48 FAULTING_OP = 33,
49 PATCHABLE_OP = 34,
50 PATCHABLE_FUNCTION_ENTER = 35,
51 PATCHABLE_RET = 36,
52 PATCHABLE_FUNCTION_EXIT = 37,
53 PATCHABLE_TAIL_CALL = 38,
54 PATCHABLE_EVENT_CALL = 39,
55 PATCHABLE_TYPED_EVENT_CALL = 40,
56 ICALL_BRANCH_FUNNEL = 41,
57 MEMBARRIER = 42,
58 JUMP_TABLE_DEBUG_INFO = 43,
59 CONVERGENCECTRL_ENTRY = 44,
60 CONVERGENCECTRL_ANCHOR = 45,
61 CONVERGENCECTRL_LOOP = 46,
62 CONVERGENCECTRL_GLUE = 47,
63 G_ASSERT_SEXT = 48,
64 G_ASSERT_ZEXT = 49,
65 G_ASSERT_ALIGN = 50,
66 G_ADD = 51,
67 G_SUB = 52,
68 G_MUL = 53,
69 G_SDIV = 54,
70 G_UDIV = 55,
71 G_SREM = 56,
72 G_UREM = 57,
73 G_SDIVREM = 58,
74 G_UDIVREM = 59,
75 G_AND = 60,
76 G_OR = 61,
77 G_XOR = 62,
78 G_IMPLICIT_DEF = 63,
79 G_PHI = 64,
80 G_FRAME_INDEX = 65,
81 G_GLOBAL_VALUE = 66,
82 G_PTRAUTH_GLOBAL_VALUE = 67,
83 G_CONSTANT_POOL = 68,
84 G_EXTRACT = 69,
85 G_UNMERGE_VALUES = 70,
86 G_INSERT = 71,
87 G_MERGE_VALUES = 72,
88 G_BUILD_VECTOR = 73,
89 G_BUILD_VECTOR_TRUNC = 74,
90 G_CONCAT_VECTORS = 75,
91 G_PTRTOINT = 76,
92 G_INTTOPTR = 77,
93 G_BITCAST = 78,
94 G_FREEZE = 79,
95 G_CONSTANT_FOLD_BARRIER = 80,
96 G_INTRINSIC_FPTRUNC_ROUND = 81,
97 G_INTRINSIC_TRUNC = 82,
98 G_INTRINSIC_ROUND = 83,
99 G_INTRINSIC_LRINT = 84,
100 G_INTRINSIC_LLRINT = 85,
101 G_INTRINSIC_ROUNDEVEN = 86,
102 G_READCYCLECOUNTER = 87,
103 G_READSTEADYCOUNTER = 88,
104 G_LOAD = 89,
105 G_SEXTLOAD = 90,
106 G_ZEXTLOAD = 91,
107 G_INDEXED_LOAD = 92,
108 G_INDEXED_SEXTLOAD = 93,
109 G_INDEXED_ZEXTLOAD = 94,
110 G_STORE = 95,
111 G_INDEXED_STORE = 96,
112 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97,
113 G_ATOMIC_CMPXCHG = 98,
114 G_ATOMICRMW_XCHG = 99,
115 G_ATOMICRMW_ADD = 100,
116 G_ATOMICRMW_SUB = 101,
117 G_ATOMICRMW_AND = 102,
118 G_ATOMICRMW_NAND = 103,
119 G_ATOMICRMW_OR = 104,
120 G_ATOMICRMW_XOR = 105,
121 G_ATOMICRMW_MAX = 106,
122 G_ATOMICRMW_MIN = 107,
123 G_ATOMICRMW_UMAX = 108,
124 G_ATOMICRMW_UMIN = 109,
125 G_ATOMICRMW_FADD = 110,
126 G_ATOMICRMW_FSUB = 111,
127 G_ATOMICRMW_FMAX = 112,
128 G_ATOMICRMW_FMIN = 113,
129 G_ATOMICRMW_UINC_WRAP = 114,
130 G_ATOMICRMW_UDEC_WRAP = 115,
131 G_FENCE = 116,
132 G_PREFETCH = 117,
133 G_BRCOND = 118,
134 G_BRINDIRECT = 119,
135 G_INVOKE_REGION_START = 120,
136 G_INTRINSIC = 121,
137 G_INTRINSIC_W_SIDE_EFFECTS = 122,
138 G_INTRINSIC_CONVERGENT = 123,
139 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124,
140 G_ANYEXT = 125,
141 G_TRUNC = 126,
142 G_CONSTANT = 127,
143 G_FCONSTANT = 128,
144 G_VASTART = 129,
145 G_VAARG = 130,
146 G_SEXT = 131,
147 G_SEXT_INREG = 132,
148 G_ZEXT = 133,
149 G_SHL = 134,
150 G_LSHR = 135,
151 G_ASHR = 136,
152 G_FSHL = 137,
153 G_FSHR = 138,
154 G_ROTR = 139,
155 G_ROTL = 140,
156 G_ICMP = 141,
157 G_FCMP = 142,
158 G_SCMP = 143,
159 G_UCMP = 144,
160 G_SELECT = 145,
161 G_UADDO = 146,
162 G_UADDE = 147,
163 G_USUBO = 148,
164 G_USUBE = 149,
165 G_SADDO = 150,
166 G_SADDE = 151,
167 G_SSUBO = 152,
168 G_SSUBE = 153,
169 G_UMULO = 154,
170 G_SMULO = 155,
171 G_UMULH = 156,
172 G_SMULH = 157,
173 G_UADDSAT = 158,
174 G_SADDSAT = 159,
175 G_USUBSAT = 160,
176 G_SSUBSAT = 161,
177 G_USHLSAT = 162,
178 G_SSHLSAT = 163,
179 G_SMULFIX = 164,
180 G_UMULFIX = 165,
181 G_SMULFIXSAT = 166,
182 G_UMULFIXSAT = 167,
183 G_SDIVFIX = 168,
184 G_UDIVFIX = 169,
185 G_SDIVFIXSAT = 170,
186 G_UDIVFIXSAT = 171,
187 G_FADD = 172,
188 G_FSUB = 173,
189 G_FMUL = 174,
190 G_FMA = 175,
191 G_FMAD = 176,
192 G_FDIV = 177,
193 G_FREM = 178,
194 G_FPOW = 179,
195 G_FPOWI = 180,
196 G_FEXP = 181,
197 G_FEXP2 = 182,
198 G_FEXP10 = 183,
199 G_FLOG = 184,
200 G_FLOG2 = 185,
201 G_FLOG10 = 186,
202 G_FLDEXP = 187,
203 G_FFREXP = 188,
204 G_FNEG = 189,
205 G_FPEXT = 190,
206 G_FPTRUNC = 191,
207 G_FPTOSI = 192,
208 G_FPTOUI = 193,
209 G_SITOFP = 194,
210 G_UITOFP = 195,
211 G_FABS = 196,
212 G_FCOPYSIGN = 197,
213 G_IS_FPCLASS = 198,
214 G_FCANONICALIZE = 199,
215 G_FMINNUM = 200,
216 G_FMAXNUM = 201,
217 G_FMINNUM_IEEE = 202,
218 G_FMAXNUM_IEEE = 203,
219 G_FMINIMUM = 204,
220 G_FMAXIMUM = 205,
221 G_GET_FPENV = 206,
222 G_SET_FPENV = 207,
223 G_RESET_FPENV = 208,
224 G_GET_FPMODE = 209,
225 G_SET_FPMODE = 210,
226 G_RESET_FPMODE = 211,
227 G_PTR_ADD = 212,
228 G_PTRMASK = 213,
229 G_SMIN = 214,
230 G_SMAX = 215,
231 G_UMIN = 216,
232 G_UMAX = 217,
233 G_ABS = 218,
234 G_LROUND = 219,
235 G_LLROUND = 220,
236 G_BR = 221,
237 G_BRJT = 222,
238 G_VSCALE = 223,
239 G_INSERT_SUBVECTOR = 224,
240 G_EXTRACT_SUBVECTOR = 225,
241 G_INSERT_VECTOR_ELT = 226,
242 G_EXTRACT_VECTOR_ELT = 227,
243 G_SHUFFLE_VECTOR = 228,
244 G_SPLAT_VECTOR = 229,
245 G_VECTOR_COMPRESS = 230,
246 G_CTTZ = 231,
247 G_CTTZ_ZERO_UNDEF = 232,
248 G_CTLZ = 233,
249 G_CTLZ_ZERO_UNDEF = 234,
250 G_CTPOP = 235,
251 G_BSWAP = 236,
252 G_BITREVERSE = 237,
253 G_FCEIL = 238,
254 G_FCOS = 239,
255 G_FSIN = 240,
256 G_FTAN = 241,
257 G_FACOS = 242,
258 G_FASIN = 243,
259 G_FATAN = 244,
260 G_FCOSH = 245,
261 G_FSINH = 246,
262 G_FTANH = 247,
263 G_FSQRT = 248,
264 G_FFLOOR = 249,
265 G_FRINT = 250,
266 G_FNEARBYINT = 251,
267 G_ADDRSPACE_CAST = 252,
268 G_BLOCK_ADDR = 253,
269 G_JUMP_TABLE = 254,
270 G_DYN_STACKALLOC = 255,
271 G_STACKSAVE = 256,
272 G_STACKRESTORE = 257,
273 G_STRICT_FADD = 258,
274 G_STRICT_FSUB = 259,
275 G_STRICT_FMUL = 260,
276 G_STRICT_FDIV = 261,
277 G_STRICT_FREM = 262,
278 G_STRICT_FMA = 263,
279 G_STRICT_FSQRT = 264,
280 G_STRICT_FLDEXP = 265,
281 G_READ_REGISTER = 266,
282 G_WRITE_REGISTER = 267,
283 G_MEMCPY = 268,
284 G_MEMCPY_INLINE = 269,
285 G_MEMMOVE = 270,
286 G_MEMSET = 271,
287 G_BZERO = 272,
288 G_TRAP = 273,
289 G_DEBUGTRAP = 274,
290 G_UBSANTRAP = 275,
291 G_VECREDUCE_SEQ_FADD = 276,
292 G_VECREDUCE_SEQ_FMUL = 277,
293 G_VECREDUCE_FADD = 278,
294 G_VECREDUCE_FMUL = 279,
295 G_VECREDUCE_FMAX = 280,
296 G_VECREDUCE_FMIN = 281,
297 G_VECREDUCE_FMAXIMUM = 282,
298 G_VECREDUCE_FMINIMUM = 283,
299 G_VECREDUCE_ADD = 284,
300 G_VECREDUCE_MUL = 285,
301 G_VECREDUCE_AND = 286,
302 G_VECREDUCE_OR = 287,
303 G_VECREDUCE_XOR = 288,
304 G_VECREDUCE_SMAX = 289,
305 G_VECREDUCE_SMIN = 290,
306 G_VECREDUCE_UMAX = 291,
307 G_VECREDUCE_UMIN = 292,
308 G_SBFX = 293,
309 G_UBFX = 294,
310 ADJCALLSTACKDOWN = 295,
311 ADJCALLSTACKUP = 296,
312 GETPCX = 297,
313 SELECT_CC_DFP_FCC = 298,
314 SELECT_CC_DFP_ICC = 299,
315 SELECT_CC_DFP_XCC = 300,
316 SELECT_CC_FP_FCC = 301,
317 SELECT_CC_FP_ICC = 302,
318 SELECT_CC_FP_XCC = 303,
319 SELECT_CC_Int_FCC = 304,
320 SELECT_CC_Int_ICC = 305,
321 SELECT_CC_Int_XCC = 306,
322 SELECT_CC_QFP_FCC = 307,
323 SELECT_CC_QFP_ICC = 308,
324 SELECT_CC_QFP_XCC = 309,
325 SET = 310,
326 SETX = 311,
327 ADDCCri = 312,
328 ADDCCrr = 313,
329 ADDCri = 314,
330 ADDCrr = 315,
331 ADDEri = 316,
332 ADDErr = 317,
333 ADDXC = 318,
334 ADDXCCC = 319,
335 ADDri = 320,
336 ADDrr = 321,
337 ALIGNADDR = 322,
338 ALIGNADDRL = 323,
339 ANDCCri = 324,
340 ANDCCrr = 325,
341 ANDNCCri = 326,
342 ANDNCCrr = 327,
343 ANDNri = 328,
344 ANDNrr = 329,
345 ANDri = 330,
346 ANDrr = 331,
347 ARRAY16 = 332,
348 ARRAY32 = 333,
349 ARRAY8 = 334,
350 BA = 335,
351 BCOND = 336,
352 BCONDA = 337,
353 BINDri = 338,
354 BINDrr = 339,
355 BMASK = 340,
356 BPFCC = 341,
357 BPFCCA = 342,
358 BPFCCANT = 343,
359 BPFCCNT = 344,
360 BPICC = 345,
361 BPICCA = 346,
362 BPICCANT = 347,
363 BPICCNT = 348,
364 BPR = 349,
365 BPRA = 350,
366 BPRANT = 351,
367 BPRNT = 352,
368 BPXCC = 353,
369 BPXCCA = 354,
370 BPXCCANT = 355,
371 BPXCCNT = 356,
372 BSHUFFLE = 357,
373 CALL = 358,
374 CALLri = 359,
375 CALLrr = 360,
376 CASAri = 361,
377 CASArr = 362,
378 CASXAri = 363,
379 CASXArr = 364,
380 CBCOND = 365,
381 CBCONDA = 366,
382 CMASK16 = 367,
383 CMASK32 = 368,
384 CMASK8 = 369,
385 DONE = 370,
386 EDGE16 = 371,
387 EDGE16L = 372,
388 EDGE16LN = 373,
389 EDGE16N = 374,
390 EDGE32 = 375,
391 EDGE32L = 376,
392 EDGE32LN = 377,
393 EDGE32N = 378,
394 EDGE8 = 379,
395 EDGE8L = 380,
396 EDGE8LN = 381,
397 EDGE8N = 382,
398 FABSD = 383,
399 FABSQ = 384,
400 FABSS = 385,
401 FADDD = 386,
402 FADDQ = 387,
403 FADDS = 388,
404 FALIGNADATA = 389,
405 FAND = 390,
406 FANDNOT1 = 391,
407 FANDNOT1S = 392,
408 FANDNOT2 = 393,
409 FANDNOT2S = 394,
410 FANDS = 395,
411 FBCOND = 396,
412 FBCONDA = 397,
413 FBCONDA_V9 = 398,
414 FBCOND_V9 = 399,
415 FCHKSM16 = 400,
416 FCMPD = 401,
417 FCMPD_V9 = 402,
418 FCMPEQ16 = 403,
419 FCMPEQ32 = 404,
420 FCMPGT16 = 405,
421 FCMPGT32 = 406,
422 FCMPLE16 = 407,
423 FCMPLE32 = 408,
424 FCMPNE16 = 409,
425 FCMPNE32 = 410,
426 FCMPQ = 411,
427 FCMPQ_V9 = 412,
428 FCMPS = 413,
429 FCMPS_V9 = 414,
430 FDIVD = 415,
431 FDIVQ = 416,
432 FDIVS = 417,
433 FDMULQ = 418,
434 FDTOI = 419,
435 FDTOQ = 420,
436 FDTOS = 421,
437 FDTOX = 422,
438 FEXPAND = 423,
439 FHADDD = 424,
440 FHADDS = 425,
441 FHSUBD = 426,
442 FHSUBS = 427,
443 FITOD = 428,
444 FITOQ = 429,
445 FITOS = 430,
446 FLCMPD = 431,
447 FLCMPS = 432,
448 FLUSH = 433,
449 FLUSHW = 434,
450 FLUSHri = 435,
451 FLUSHrr = 436,
452 FMEAN16 = 437,
453 FMOVD = 438,
454 FMOVD_FCC = 439,
455 FMOVD_ICC = 440,
456 FMOVD_XCC = 441,
457 FMOVQ = 442,
458 FMOVQ_FCC = 443,
459 FMOVQ_ICC = 444,
460 FMOVQ_XCC = 445,
461 FMOVRD = 446,
462 FMOVRQ = 447,
463 FMOVRS = 448,
464 FMOVS = 449,
465 FMOVS_FCC = 450,
466 FMOVS_ICC = 451,
467 FMOVS_XCC = 452,
468 FMUL8SUX16 = 453,
469 FMUL8ULX16 = 454,
470 FMUL8X16 = 455,
471 FMUL8X16AL = 456,
472 FMUL8X16AU = 457,
473 FMULD = 458,
474 FMULD8SUX16 = 459,
475 FMULD8ULX16 = 460,
476 FMULQ = 461,
477 FMULS = 462,
478 FNADDD = 463,
479 FNADDS = 464,
480 FNAND = 465,
481 FNANDS = 466,
482 FNEGD = 467,
483 FNEGQ = 468,
484 FNEGS = 469,
485 FNHADDD = 470,
486 FNHADDS = 471,
487 FNMULD = 472,
488 FNMULS = 473,
489 FNOR = 474,
490 FNORS = 475,
491 FNOT1 = 476,
492 FNOT1S = 477,
493 FNOT2 = 478,
494 FNOT2S = 479,
495 FNSMULD = 480,
496 FONE = 481,
497 FONES = 482,
498 FOR = 483,
499 FORNOT1 = 484,
500 FORNOT1S = 485,
501 FORNOT2 = 486,
502 FORNOT2S = 487,
503 FORS = 488,
504 FPACK16 = 489,
505 FPACK32 = 490,
506 FPACKFIX = 491,
507 FPADD16 = 492,
508 FPADD16S = 493,
509 FPADD32 = 494,
510 FPADD32S = 495,
511 FPADD64 = 496,
512 FPMERGE = 497,
513 FPSUB16 = 498,
514 FPSUB16S = 499,
515 FPSUB32 = 500,
516 FPSUB32S = 501,
517 FQTOD = 502,
518 FQTOI = 503,
519 FQTOS = 504,
520 FQTOX = 505,
521 FSLAS16 = 506,
522 FSLAS32 = 507,
523 FSLL16 = 508,
524 FSLL32 = 509,
525 FSMULD = 510,
526 FSQRTD = 511,
527 FSQRTQ = 512,
528 FSQRTS = 513,
529 FSRA16 = 514,
530 FSRA32 = 515,
531 FSRC1 = 516,
532 FSRC1S = 517,
533 FSRC2 = 518,
534 FSRC2S = 519,
535 FSRL16 = 520,
536 FSRL32 = 521,
537 FSTOD = 522,
538 FSTOI = 523,
539 FSTOQ = 524,
540 FSTOX = 525,
541 FSUBD = 526,
542 FSUBQ = 527,
543 FSUBS = 528,
544 FXNOR = 529,
545 FXNORS = 530,
546 FXOR = 531,
547 FXORS = 532,
548 FXTOD = 533,
549 FXTOQ = 534,
550 FXTOS = 535,
551 FZERO = 536,
552 FZEROS = 537,
553 GDOP_LDXrr = 538,
554 GDOP_LDrr = 539,
555 JMPLri = 540,
556 JMPLrr = 541,
557 LDAri = 542,
558 LDArr = 543,
559 LDCSRri = 544,
560 LDCSRrr = 545,
561 LDCri = 546,
562 LDCrr = 547,
563 LDDAri = 548,
564 LDDArr = 549,
565 LDDCri = 550,
566 LDDCrr = 551,
567 LDDFAri = 552,
568 LDDFArr = 553,
569 LDDFri = 554,
570 LDDFrr = 555,
571 LDDri = 556,
572 LDDrr = 557,
573 LDFAri = 558,
574 LDFArr = 559,
575 LDFSRri = 560,
576 LDFSRrr = 561,
577 LDFri = 562,
578 LDFrr = 563,
579 LDQFAri = 564,
580 LDQFArr = 565,
581 LDQFri = 566,
582 LDQFrr = 567,
583 LDSBAri = 568,
584 LDSBArr = 569,
585 LDSBri = 570,
586 LDSBrr = 571,
587 LDSHAri = 572,
588 LDSHArr = 573,
589 LDSHri = 574,
590 LDSHrr = 575,
591 LDSTUBAri = 576,
592 LDSTUBArr = 577,
593 LDSTUBri = 578,
594 LDSTUBrr = 579,
595 LDSWAri = 580,
596 LDSWArr = 581,
597 LDSWri = 582,
598 LDSWrr = 583,
599 LDUBAri = 584,
600 LDUBArr = 585,
601 LDUBri = 586,
602 LDUBrr = 587,
603 LDUHAri = 588,
604 LDUHArr = 589,
605 LDUHri = 590,
606 LDUHrr = 591,
607 LDXAri = 592,
608 LDXArr = 593,
609 LDXFSRri = 594,
610 LDXFSRrr = 595,
611 LDXri = 596,
612 LDXrr = 597,
613 LDri = 598,
614 LDrr = 599,
615 LZCNT = 600,
616 MEMBARi = 601,
617 MOVDTOX = 602,
618 MOVFCCri = 603,
619 MOVFCCrr = 604,
620 MOVICCri = 605,
621 MOVICCrr = 606,
622 MOVRri = 607,
623 MOVRrr = 608,
624 MOVSTOSW = 609,
625 MOVSTOUW = 610,
626 MOVWTOS = 611,
627 MOVXCCri = 612,
628 MOVXCCrr = 613,
629 MOVXTOD = 614,
630 MULSCCri = 615,
631 MULSCCrr = 616,
632 MULXri = 617,
633 MULXrr = 618,
634 NOP = 619,
635 ORCCri = 620,
636 ORCCrr = 621,
637 ORNCCri = 622,
638 ORNCCrr = 623,
639 ORNri = 624,
640 ORNrr = 625,
641 ORri = 626,
642 ORrr = 627,
643 PDIST = 628,
644 PDISTN = 629,
645 POPCrr = 630,
646 PREFETCHAi = 631,
647 PREFETCHAr = 632,
648 PREFETCHi = 633,
649 PREFETCHr = 634,
650 PWRPSRri = 635,
651 PWRPSRrr = 636,
652 RDASR = 637,
653 RDFQ = 638,
654 RDPR = 639,
655 RDPSR = 640,
656 RDTBR = 641,
657 RDWIM = 642,
658 RESTORED = 643,
659 RESTOREri = 644,
660 RESTORErr = 645,
661 RET = 646,
662 RETL = 647,
663 RETRY = 648,
664 RETTri = 649,
665 RETTrr = 650,
666 SAVED = 651,
667 SAVEri = 652,
668 SAVErr = 653,
669 SDIVCCri = 654,
670 SDIVCCrr = 655,
671 SDIVXri = 656,
672 SDIVXrr = 657,
673 SDIVri = 658,
674 SDIVrr = 659,
675 SETHIi = 660,
676 SHUTDOWN = 661,
677 SIAM = 662,
678 SIR = 663,
679 SLLXri = 664,
680 SLLXrr = 665,
681 SLLri = 666,
682 SLLrr = 667,
683 SMACri = 668,
684 SMACrr = 669,
685 SMULCCri = 670,
686 SMULCCrr = 671,
687 SMULri = 672,
688 SMULrr = 673,
689 SRAXri = 674,
690 SRAXrr = 675,
691 SRAri = 676,
692 SRArr = 677,
693 SRLXri = 678,
694 SRLXrr = 679,
695 SRLri = 680,
696 SRLrr = 681,
697 STAri = 682,
698 STArr = 683,
699 STBAR = 684,
700 STBAri = 685,
701 STBArr = 686,
702 STBri = 687,
703 STBrr = 688,
704 STCSRri = 689,
705 STCSRrr = 690,
706 STCri = 691,
707 STCrr = 692,
708 STDAri = 693,
709 STDArr = 694,
710 STDCQri = 695,
711 STDCQrr = 696,
712 STDCri = 697,
713 STDCrr = 698,
714 STDFAri = 699,
715 STDFArr = 700,
716 STDFQri = 701,
717 STDFQrr = 702,
718 STDFri = 703,
719 STDFrr = 704,
720 STDri = 705,
721 STDrr = 706,
722 STFAri = 707,
723 STFArr = 708,
724 STFSRri = 709,
725 STFSRrr = 710,
726 STFri = 711,
727 STFrr = 712,
728 STHAri = 713,
729 STHArr = 714,
730 STHri = 715,
731 STHrr = 716,
732 STQFAri = 717,
733 STQFArr = 718,
734 STQFri = 719,
735 STQFrr = 720,
736 STXAri = 721,
737 STXArr = 722,
738 STXFSRri = 723,
739 STXFSRrr = 724,
740 STXri = 725,
741 STXrr = 726,
742 STri = 727,
743 STrr = 728,
744 SUBCCri = 729,
745 SUBCCrr = 730,
746 SUBCri = 731,
747 SUBCrr = 732,
748 SUBEri = 733,
749 SUBErr = 734,
750 SUBri = 735,
751 SUBrr = 736,
752 SWAPAri = 737,
753 SWAPArr = 738,
754 SWAPri = 739,
755 SWAPrr = 740,
756 TA1 = 741,
757 TA3 = 742,
758 TA5 = 743,
759 TADDCCTVri = 744,
760 TADDCCTVrr = 745,
761 TADDCCri = 746,
762 TADDCCrr = 747,
763 TAIL_CALL = 748,
764 TAIL_CALLri = 749,
765 TICCri = 750,
766 TICCrr = 751,
767 TLS_ADDrr = 752,
768 TLS_CALL = 753,
769 TLS_LDXrr = 754,
770 TLS_LDrr = 755,
771 TRAPri = 756,
772 TRAPrr = 757,
773 TSUBCCTVri = 758,
774 TSUBCCTVrr = 759,
775 TSUBCCri = 760,
776 TSUBCCrr = 761,
777 TXCCri = 762,
778 TXCCrr = 763,
779 UDIVCCri = 764,
780 UDIVCCrr = 765,
781 UDIVXri = 766,
782 UDIVXrr = 767,
783 UDIVri = 768,
784 UDIVrr = 769,
785 UMACri = 770,
786 UMACrr = 771,
787 UMULCCri = 772,
788 UMULCCrr = 773,
789 UMULXHI = 774,
790 UMULri = 775,
791 UMULrr = 776,
792 UNIMP = 777,
793 V9FCMPD = 778,
794 V9FCMPED = 779,
795 V9FCMPEQ = 780,
796 V9FCMPES = 781,
797 V9FCMPQ = 782,
798 V9FCMPS = 783,
799 V9FMOVD_FCC = 784,
800 V9FMOVQ_FCC = 785,
801 V9FMOVS_FCC = 786,
802 V9MOVFCCri = 787,
803 V9MOVFCCrr = 788,
804 WRASRri = 789,
805 WRASRrr = 790,
806 WRPRri = 791,
807 WRPRrr = 792,
808 WRPSRri = 793,
809 WRPSRrr = 794,
810 WRTBRri = 795,
811 WRTBRrr = 796,
812 WRWIMri = 797,
813 WRWIMrr = 798,
814 XMULX = 799,
815 XMULXHI = 800,
816 XNORCCri = 801,
817 XNORCCrr = 802,
818 XNORri = 803,
819 XNORrr = 804,
820 XORCCri = 805,
821 XORCCrr = 806,
822 XORri = 807,
823 XORrr = 808,
824 INSTRUCTION_LIST_END = 809
825 };
826
827} // end namespace SP
828} // end namespace llvm
829#endif // GET_INSTRINFO_ENUM
830
831#ifdef GET_INSTRINFO_SCHED_ENUM
832#undef GET_INSTRINFO_SCHED_ENUM
833namespace llvm {
834
835namespace SP {
836namespace Sched {
837 enum {
838 NoInstrModel = 0,
839 IIC_iu_instr = 1,
840 IIC_fpu_normal_instr = 2,
841 IIC_jmp_or_call = 3,
842 IIC_fpu_abs = 4,
843 IIC_fpu_fast_instr = 5,
844 IIC_fpu_divd = 6,
845 IIC_fpu_divs = 7,
846 IIC_fpu_muld = 8,
847 IIC_fpu_muls = 9,
848 IIC_fpu_negs = 10,
849 IIC_fpu_sqrtd = 11,
850 IIC_fpu_sqrts = 12,
851 IIC_fpu_stod = 13,
852 IIC_ldd = 14,
853 IIC_iu_or_fpu_instr = 15,
854 IIC_iu_div = 16,
855 IIC_smac_umac = 17,
856 IIC_iu_smul = 18,
857 IIC_st = 19,
858 IIC_std = 20,
859 IIC_iu_umul = 21,
860 SCHED_LIST_END = 22
861 };
862} // end namespace Sched
863} // end namespace SP
864} // end namespace llvm
865#endif // GET_INSTRINFO_SCHED_ENUM
866
867#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
868namespace llvm {
869
870struct SparcInstrTable {
871 MCInstrDesc Insts[809];
872 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
873 MCOperandInfo OperandInfo[544];
874 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
875 MCPhysReg ImplicitOps[32];
876};
877
878} // end namespace llvm
879#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
880
881#ifdef GET_INSTRINFO_MC_DESC
882#undef GET_INSTRINFO_MC_DESC
883namespace llvm {
884
885static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
886static constexpr unsigned SparcImpOpBase = sizeof SparcInstrTable::OperandInfo / (sizeof(MCPhysReg));
887
888extern const SparcInstrTable SparcDescs = {
889 {
890 { 808, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #808 = XORrr
891 { 807, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL }, // Inst #807 = XORri
892 { 806, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #806 = XORCCrr
893 { 805, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #805 = XORCCri
894 { 804, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #804 = XNORrr
895 { 803, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #803 = XNORri
896 { 802, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #802 = XNORCCrr
897 { 801, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #801 = XNORCCri
898 { 800, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #800 = XMULXHI
899 { 799, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #799 = XMULX
900 { 798, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 18, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #798 = WRWIMrr
901 { 797, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 18, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #797 = WRWIMri
902 { 796, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 17, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #796 = WRTBRrr
903 { 795, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 17, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #795 = WRTBRri
904 { 794, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 15, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #794 = WRPSRrr
905 { 793, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 15, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #793 = WRPSRri
906 { 792, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 541, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #792 = WRPRrr
907 { 791, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 538, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #791 = WRPRri
908 { 790, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 535, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #790 = WRASRrr
909 { 789, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 532, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #789 = WRASRri
910 { 788, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 527, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #788 = V9MOVFCCrr
911 { 787, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 522, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #787 = V9MOVFCCri
912 { 786, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 517, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #786 = V9FMOVS_FCC
913 { 785, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 512, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #785 = V9FMOVQ_FCC
914 { 784, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 507, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #784 = V9FMOVD_FCC
915 { 783, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 504, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #783 = V9FCMPS
916 { 782, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 501, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #782 = V9FCMPQ
917 { 781, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 504, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #781 = V9FCMPES
918 { 780, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 501, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #780 = V9FCMPEQ
919 { 779, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #779 = V9FCMPED
920 { 778, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #778 = V9FCMPD
921 { 777, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #777 = UNIMP
922 { 776, 3, 1, 4, 21, 0, 1, SparcImpOpBase + 30, 176, 0, 0x0ULL }, // Inst #776 = UMULrr
923 { 775, 3, 1, 4, 21, 0, 1, SparcImpOpBase + 30, 173, 0, 0x0ULL }, // Inst #775 = UMULri
924 { 774, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #774 = UMULXHI
925 { 773, 3, 1, 4, 21, 0, 2, SparcImpOpBase + 28, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #773 = UMULCCrr
926 { 772, 3, 1, 4, 21, 0, 2, SparcImpOpBase + 28, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #772 = UMULCCri
927 { 771, 4, 1, 4, 17, 2, 2, SparcImpOpBase + 24, 405, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #771 = UMACrr
928 { 770, 4, 1, 4, 17, 2, 2, SparcImpOpBase + 24, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #770 = UMACri
929 { 769, 3, 1, 4, 16, 1, 1, SparcImpOpBase + 22, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #769 = UDIVrr
930 { 768, 3, 1, 4, 16, 1, 1, SparcImpOpBase + 22, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #768 = UDIVri
931 { 767, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #767 = UDIVXrr
932 { 766, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #766 = UDIVXri
933 { 765, 3, 1, 4, 16, 1, 2, SparcImpOpBase + 19, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #765 = UDIVCCrr
934 { 764, 3, 1, 4, 16, 1, 2, SparcImpOpBase + 19, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #764 = UDIVCCri
935 { 763, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 398, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #763 = TXCCrr
936 { 762, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 494, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #762 = TXCCri
937 { 761, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #761 = TSUBCCrr
938 { 760, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #760 = TSUBCCri
939 { 759, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #759 = TSUBCCTVrr
940 { 758, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #758 = TSUBCCTVri
941 { 757, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 398, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #757 = TRAPrr
942 { 756, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 494, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #756 = TRAPri
943 { 755, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #755 = TLS_LDrr
944 { 754, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #754 = TLS_LDXrr
945 { 753, 2, 0, 4, 3, 1, 0, SparcImpOpBase + 7, 13, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #753 = TLS_CALL
946 { 752, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 497, 0, 0x0ULL }, // Inst #752 = TLS_ADDrr
947 { 751, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 398, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #751 = TICCrr
948 { 750, 3, 0, 4, 0, 1, 0, SparcImpOpBase + 4, 494, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #750 = TICCri
949 { 749, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #749 = TAIL_CALLri
950 { 748, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #748 = TAIL_CALL
951 { 747, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #747 = TADDCCrr
952 { 746, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #746 = TADDCCri
953 { 745, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #745 = TADDCCTVrr
954 { 744, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #744 = TADDCCTVri
955 { 743, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #743 = TA5
956 { 742, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #742 = TA3
957 { 741, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #741 = TA1
958 { 740, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 490, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #740 = SWAPrr
959 { 739, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 481, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #739 = SWAPri
960 { 738, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 485, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #738 = SWAPArr
961 { 737, 4, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 481, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #737 = SWAPAri
962 { 736, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #736 = SUBrr
963 { 735, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL }, // Inst #735 = SUBri
964 { 734, 3, 1, 4, 1, 1, 1, SparcImpOpBase + 5, 176, 0, 0x0ULL }, // Inst #734 = SUBErr
965 { 733, 3, 1, 4, 1, 1, 1, SparcImpOpBase + 5, 173, 0, 0x0ULL }, // Inst #733 = SUBEri
966 { 732, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #732 = SUBCrr
967 { 731, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #731 = SUBCri
968 { 730, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #730 = SUBCCrr
969 { 729, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #729 = SUBCCri
970 { 728, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 416, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #728 = STrr
971 { 727, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 409, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #727 = STri
972 { 726, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 478, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #726 = STXrr
973 { 725, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 471, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #725 = STXri
974 { 724, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 10, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #724 = STXFSRrr
975 { 723, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 10, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #723 = STXFSRri
976 { 722, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #722 = STXArr
977 { 721, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 471, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #721 = STXAri
978 { 720, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 468, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #720 = STQFrr
979 { 719, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 461, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #719 = STQFri
980 { 718, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 464, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #718 = STQFArr
981 { 717, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 461, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #717 = STQFAri
982 { 716, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 416, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #716 = STHrr
983 { 715, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 409, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #715 = STHri
984 { 714, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 412, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #714 = STHArr
985 { 713, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 409, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #713 = STHAri
986 { 712, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 458, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #712 = STFrr
987 { 711, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 451, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #711 = STFri
988 { 710, 2, 0, 4, 19, 1, 0, SparcImpOpBase + 10, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #710 = STFSRrr
989 { 709, 2, 0, 4, 19, 1, 0, SparcImpOpBase + 10, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #709 = STFSRri
990 { 708, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 454, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #708 = STFArr
991 { 707, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 451, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #707 = STFAri
992 { 706, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 448, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #706 = STDrr
993 { 705, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 425, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #705 = STDri
994 { 704, 3, 0, 4, 20, 0, 0, SparcImpOpBase + 0, 445, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #704 = STDFrr
995 { 703, 3, 0, 4, 20, 0, 0, SparcImpOpBase + 0, 438, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #703 = STDFri
996 { 702, 2, 0, 4, 20, 0, 1, SparcImpOpBase + 16, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #702 = STDFQrr
997 { 701, 2, 0, 4, 20, 0, 1, SparcImpOpBase + 16, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #701 = STDFQri
998 { 700, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 441, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #700 = STDFArr
999 { 699, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 438, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #699 = STDFAri
1000 { 698, 3, 0, 4, 20, 0, 0, SparcImpOpBase + 0, 435, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #698 = STDCrr
1001 { 697, 3, 0, 4, 20, 0, 0, SparcImpOpBase + 0, 432, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #697 = STDCri
1002 { 696, 2, 0, 4, 20, 1, 0, SparcImpOpBase + 31, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #696 = STDCQrr
1003 { 695, 2, 0, 4, 20, 1, 0, SparcImpOpBase + 31, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #695 = STDCQri
1004 { 694, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 428, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #694 = STDArr
1005 { 693, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 425, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #693 = STDAri
1006 { 692, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 422, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #692 = STCrr
1007 { 691, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 419, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #691 = STCri
1008 { 690, 2, 0, 4, 19, 1, 0, SparcImpOpBase + 9, 182, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #690 = STCSRrr
1009 { 689, 2, 0, 4, 19, 1, 0, SparcImpOpBase + 9, 35, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #689 = STCSRri
1010 { 688, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 416, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #688 = STBrr
1011 { 687, 3, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 409, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #687 = STBri
1012 { 686, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 412, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #686 = STBArr
1013 { 685, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 409, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #685 = STBAri
1014 { 684, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #684 = STBAR
1015 { 683, 4, 0, 4, 19, 0, 0, SparcImpOpBase + 0, 412, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #683 = STArr
1016 { 682, 3, 0, 4, 19, 1, 0, SparcImpOpBase + 8, 409, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #682 = STAri
1017 { 681, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #681 = SRLrr
1018 { 680, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 398, 0, 0x0ULL }, // Inst #680 = SRLri
1019 { 679, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 395, 0, 0x0ULL }, // Inst #679 = SRLXrr
1020 { 678, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 392, 0, 0x0ULL }, // Inst #678 = SRLXri
1021 { 677, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #677 = SRArr
1022 { 676, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 398, 0, 0x0ULL }, // Inst #676 = SRAri
1023 { 675, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 395, 0, 0x0ULL }, // Inst #675 = SRAXrr
1024 { 674, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 392, 0, 0x0ULL }, // Inst #674 = SRAXri
1025 { 673, 3, 1, 4, 18, 0, 1, SparcImpOpBase + 30, 176, 0, 0x0ULL }, // Inst #673 = SMULrr
1026 { 672, 3, 1, 4, 18, 0, 1, SparcImpOpBase + 30, 173, 0, 0x0ULL }, // Inst #672 = SMULri
1027 { 671, 3, 1, 4, 18, 0, 2, SparcImpOpBase + 28, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #671 = SMULCCrr
1028 { 670, 3, 1, 4, 18, 0, 2, SparcImpOpBase + 28, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #670 = SMULCCri
1029 { 669, 4, 1, 4, 17, 2, 2, SparcImpOpBase + 24, 405, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #669 = SMACrr
1030 { 668, 4, 1, 4, 17, 2, 2, SparcImpOpBase + 24, 401, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #668 = SMACri
1031 { 667, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #667 = SLLrr
1032 { 666, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 398, 0, 0x0ULL }, // Inst #666 = SLLri
1033 { 665, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 395, 0, 0x0ULL }, // Inst #665 = SLLXrr
1034 { 664, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 392, 0, 0x0ULL }, // Inst #664 = SLLXri
1035 { 663, 1, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #663 = SIR
1036 { 662, 0, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #662 = SIAM
1037 { 661, 0, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #661 = SHUTDOWN
1038 { 660, 2, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 168, 0, 0x0ULL }, // Inst #660 = SETHIi
1039 { 659, 3, 1, 4, 16, 1, 1, SparcImpOpBase + 22, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #659 = SDIVrr
1040 { 658, 3, 1, 4, 16, 1, 1, SparcImpOpBase + 22, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #658 = SDIVri
1041 { 657, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #657 = SDIVXrr
1042 { 656, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #656 = SDIVXri
1043 { 655, 3, 1, 4, 16, 1, 2, SparcImpOpBase + 19, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #655 = SDIVCCrr
1044 { 654, 3, 1, 4, 16, 1, 2, SparcImpOpBase + 19, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #654 = SDIVCCri
1045 { 653, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #653 = SAVErr
1046 { 652, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #652 = SAVEri
1047 { 651, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #651 = SAVED
1048 { 650, 2, 0, 4, 3, 0, 0, SparcImpOpBase + 0, 182, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #650 = RETTrr
1049 { 649, 2, 0, 4, 3, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #649 = RETTri
1050 { 648, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #648 = RETRY
1051 { 647, 1, 0, 4, 3, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #647 = RETL
1052 { 646, 1, 0, 4, 3, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #646 = RET
1053 { 645, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #645 = RESTORErr
1054 { 644, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #644 = RESTOREri
1055 { 643, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #643 = RESTORED
1056 { 642, 1, 1, 4, 1, 1, 0, SparcImpOpBase + 18, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #642 = RDWIM
1057 { 641, 1, 1, 4, 1, 1, 0, SparcImpOpBase + 17, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #641 = RDTBR
1058 { 640, 1, 1, 4, 1, 1, 0, SparcImpOpBase + 15, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #640 = RDPSR
1059 { 639, 2, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 390, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #639 = RDPR
1060 { 638, 1, 1, 4, 1, 1, 0, SparcImpOpBase + 16, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #638 = RDFQ
1061 { 637, 2, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 387, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #637 = RDASR
1062 { 636, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 15, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #636 = PWRPSRrr
1063 { 635, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 15, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #635 = PWRPSRri
1064 { 634, 3, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #634 = PREFETCHr
1065 { 633, 3, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 377, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #633 = PREFETCHi
1066 { 632, 4, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 380, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #632 = PREFETCHAr
1067 { 631, 3, 0, 4, 1, 1, 0, SparcImpOpBase + 8, 377, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #631 = PREFETCHAi
1068 { 630, 2, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 375, 0, 0x0ULL }, // Inst #630 = POPCrr
1069 { 629, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #629 = PDISTN
1070 { 628, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #628 = PDIST
1071 { 627, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #627 = ORrr
1072 { 626, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL }, // Inst #626 = ORri
1073 { 625, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #625 = ORNrr
1074 { 624, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #624 = ORNri
1075 { 623, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #623 = ORNCCrr
1076 { 622, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #622 = ORNCCri
1077 { 621, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #621 = ORCCrr
1078 { 620, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #620 = ORCCri
1079 { 619, 0, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #619 = NOP
1080 { 618, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 179, 0, 0x0ULL }, // Inst #618 = MULXrr
1081 { 617, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL }, // Inst #617 = MULXri
1082 { 616, 3, 1, 4, 1, 2, 2, SparcImpOpBase + 11, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #616 = MULSCCrr
1083 { 615, 3, 1, 4, 1, 2, 2, SparcImpOpBase + 11, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #615 = MULSCCri
1084 { 614, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 373, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #614 = MOVXTOD
1085 { 613, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 359, 0, 0x0ULL }, // Inst #613 = MOVXCCrr
1086 { 612, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 355, 0, 0x0ULL }, // Inst #612 = MOVXCCri
1087 { 611, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 373, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #611 = MOVWTOS
1088 { 610, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 353, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #610 = MOVSTOUW
1089 { 609, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 353, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #609 = MOVSTOSW
1090 { 608, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #608 = MOVRrr
1091 { 607, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 363, 0, 0x0ULL }, // Inst #607 = MOVRri
1092 { 606, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 359, 0, 0x0ULL }, // Inst #606 = MOVICCrr
1093 { 605, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 355, 0, 0x0ULL }, // Inst #605 = MOVICCri
1094 { 604, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 359, 0, 0x0ULL }, // Inst #604 = MOVFCCrr
1095 { 603, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 355, 0, 0x0ULL }, // Inst #603 = MOVFCCri
1096 { 602, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 353, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #602 = MOVDTOX
1097 { 601, 1, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #601 = MEMBARi
1098 { 600, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 351, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #600 = LZCNT
1099 { 599, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #599 = LDrr
1100 { 598, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #598 = LDri
1101 { 597, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 348, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #597 = LDXrr
1102 { 596, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 345, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #596 = LDXri
1103 { 595, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 10, 182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #595 = LDXFSRrr
1104 { 594, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 10, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #594 = LDXFSRri
1105 { 593, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 279, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #593 = LDXArr
1106 { 592, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 345, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #592 = LDXAri
1107 { 591, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #591 = LDUHrr
1108 { 590, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #590 = LDUHri
1109 { 589, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #589 = LDUHArr
1110 { 588, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #588 = LDUHAri
1111 { 587, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #587 = LDUBrr
1112 { 586, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #586 = LDUBri
1113 { 585, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #585 = LDUBArr
1114 { 584, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #584 = LDUBAri
1115 { 583, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 348, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #583 = LDSWrr
1116 { 582, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 345, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #582 = LDSWri
1117 { 581, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 279, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #581 = LDSWArr
1118 { 580, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 345, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #580 = LDSWAri
1119 { 579, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #579 = LDSTUBrr
1120 { 578, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #578 = LDSTUBri
1121 { 577, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #577 = LDSTUBArr
1122 { 576, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #576 = LDSTUBAri
1123 { 575, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #575 = LDSHrr
1124 { 574, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #574 = LDSHri
1125 { 573, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #573 = LDSHArr
1126 { 572, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #572 = LDSHAri
1127 { 571, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #571 = LDSBrr
1128 { 570, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #570 = LDSBri
1129 { 569, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #569 = LDSBArr
1130 { 568, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #568 = LDSBAri
1131 { 567, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 342, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #567 = LDQFrr
1132 { 566, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 335, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #566 = LDQFri
1133 { 565, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 338, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #565 = LDQFArr
1134 { 564, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 335, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #564 = LDQFAri
1135 { 563, 3, 1, 4, 15, 0, 0, SparcImpOpBase + 0, 332, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #563 = LDFrr
1136 { 562, 3, 1, 4, 15, 0, 0, SparcImpOpBase + 0, 325, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #562 = LDFri
1137 { 561, 2, 0, 4, 15, 0, 1, SparcImpOpBase + 10, 182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #561 = LDFSRrr
1138 { 560, 2, 0, 4, 15, 0, 1, SparcImpOpBase + 10, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #560 = LDFSRri
1139 { 559, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 328, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #559 = LDFArr
1140 { 558, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 325, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #558 = LDFAri
1141 { 557, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 322, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #557 = LDDrr
1142 { 556, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 299, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #556 = LDDri
1143 { 555, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 319, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #555 = LDDFrr
1144 { 554, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 312, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #554 = LDDFri
1145 { 553, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 315, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #553 = LDDFArr
1146 { 552, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 312, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #552 = LDDFAri
1147 { 551, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 309, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #551 = LDDCrr
1148 { 550, 3, 1, 4, 14, 0, 0, SparcImpOpBase + 0, 306, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #550 = LDDCri
1149 { 549, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 302, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #549 = LDDArr
1150 { 548, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #548 = LDDAri
1151 { 547, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 296, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #547 = LDCrr
1152 { 546, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 293, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #546 = LDCri
1153 { 545, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 9, 182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #545 = LDCSRrr
1154 { 544, 2, 0, 4, 1, 0, 1, SparcImpOpBase + 9, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #544 = LDCSRri
1155 { 543, 4, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #543 = LDArr
1156 { 542, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 8, 287, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #542 = LDAri
1157 { 541, 3, 1, 4, 3, 0, 0, SparcImpOpBase + 0, 290, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #541 = JMPLrr
1158 { 540, 3, 1, 4, 3, 0, 0, SparcImpOpBase + 0, 287, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #540 = JMPLri
1159 { 539, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 283, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #539 = GDOP_LDrr
1160 { 538, 4, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 279, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #538 = GDOP_LDXrr
1161 { 537, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 270, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #537 = FZEROS
1162 { 536, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 268, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #536 = FZERO
1163 { 535, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 230, 0, 0x0ULL }, // Inst #535 = FXTOS
1164 { 534, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 232, 0, 0x0ULL }, // Inst #534 = FXTOQ
1165 { 533, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL }, // Inst #533 = FXTOD
1166 { 532, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #532 = FXORS
1167 { 531, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #531 = FXOR
1168 { 530, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #530 = FXNORS
1169 { 529, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #529 = FXNOR
1170 { 528, 3, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #528 = FSUBS
1171 { 527, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 218, 0, 0x0ULL }, // Inst #527 = FSUBQ
1172 { 526, 3, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 190, 0, 0x0ULL }, // Inst #526 = FSUBD
1173 { 525, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 234, 0, 0x0ULL }, // Inst #525 = FSTOX
1174 { 524, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 236, 0, 0x0ULL }, // Inst #524 = FSTOQ
1175 { 523, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL }, // Inst #523 = FSTOI
1176 { 522, 2, 1, 4, 13, 0, 0, SparcImpOpBase + 0, 234, 0, 0x0ULL }, // Inst #522 = FSTOD
1177 { 521, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #521 = FSRL32
1178 { 520, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #520 = FSRL16
1179 { 519, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #519 = FSRC2S
1180 { 518, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #518 = FSRC2
1181 { 517, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #517 = FSRC1S
1182 { 516, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #516 = FSRC1
1183 { 515, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #515 = FSRA32
1184 { 514, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #514 = FSRA16
1185 { 513, 2, 1, 4, 12, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL }, // Inst #513 = FSQRTS
1186 { 512, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 214, 0, 0x0ULL }, // Inst #512 = FSQRTQ
1187 { 511, 2, 1, 4, 11, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL }, // Inst #511 = FSQRTD
1188 { 510, 3, 1, 4, 8, 0, 0, SparcImpOpBase + 0, 276, 0, 0x0ULL }, // Inst #510 = FSMULD
1189 { 509, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #509 = FSLL32
1190 { 508, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #508 = FSLL16
1191 { 507, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #507 = FSLAS32
1192 { 506, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #506 = FSLAS16
1193 { 505, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 272, 0, 0x0ULL }, // Inst #505 = FQTOX
1194 { 504, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 274, 0, 0x0ULL }, // Inst #504 = FQTOS
1195 { 503, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 274, 0, 0x0ULL }, // Inst #503 = FQTOI
1196 { 502, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 272, 0, 0x0ULL }, // Inst #502 = FQTOD
1197 { 501, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #501 = FPSUB32S
1198 { 500, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #500 = FPSUB32
1199 { 499, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #499 = FPSUB16S
1200 { 498, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #498 = FPSUB16
1201 { 497, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #497 = FPMERGE
1202 { 496, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #496 = FPADD64
1203 { 495, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #495 = FPADD32S
1204 { 494, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #494 = FPADD32
1205 { 493, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #493 = FPADD16S
1206 { 492, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #492 = FPADD16
1207 { 491, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #491 = FPACKFIX
1208 { 490, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #490 = FPACK32
1209 { 489, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #489 = FPACK16
1210 { 488, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #488 = FORS
1211 { 487, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #487 = FORNOT2S
1212 { 486, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #486 = FORNOT2
1213 { 485, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #485 = FORNOT1S
1214 { 484, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #484 = FORNOT1
1215 { 483, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #483 = FOR
1216 { 482, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 270, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #482 = FONES
1217 { 481, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 268, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #481 = FONE
1218 { 480, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #480 = FNSMULD
1219 { 479, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #479 = FNOT2S
1220 { 478, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #478 = FNOT2
1221 { 477, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #477 = FNOT1S
1222 { 476, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #476 = FNOT1
1223 { 475, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #475 = FNORS
1224 { 474, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #474 = FNOR
1225 { 473, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #473 = FNMULS
1226 { 472, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #472 = FNMULD
1227 { 471, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #471 = FNHADDS
1228 { 470, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #470 = FNHADDD
1229 { 469, 2, 1, 4, 10, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL }, // Inst #469 = FNEGS
1230 { 468, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 214, 0, 0x0ULL }, // Inst #468 = FNEGQ
1231 { 467, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL }, // Inst #467 = FNEGD
1232 { 466, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #466 = FNANDS
1233 { 465, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #465 = FNAND
1234 { 464, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #464 = FNADDS
1235 { 463, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #463 = FNADDD
1236 { 462, 3, 1, 4, 9, 0, 0, SparcImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #462 = FMULS
1237 { 461, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 218, 0, 0x0ULL }, // Inst #461 = FMULQ
1238 { 460, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #460 = FMULD8ULX16
1239 { 459, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #459 = FMULD8SUX16
1240 { 458, 3, 1, 4, 8, 0, 0, SparcImpOpBase + 0, 190, 0, 0x0ULL }, // Inst #458 = FMULD
1241 { 457, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #457 = FMUL8X16AU
1242 { 456, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #456 = FMUL8X16AL
1243 { 455, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #455 = FMUL8X16
1244 { 454, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #454 = FMUL8ULX16
1245 { 453, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #453 = FMUL8SUX16
1246 { 452, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 264, 0, 0x0ULL }, // Inst #452 = FMOVS_XCC
1247 { 451, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 264, 0, 0x0ULL }, // Inst #451 = FMOVS_ICC
1248 { 450, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 264, 0, 0x0ULL }, // Inst #450 = FMOVS_FCC
1249 { 449, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #449 = FMOVS
1250 { 448, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 259, 0, 0x0ULL }, // Inst #448 = FMOVRS
1251 { 447, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #447 = FMOVRQ
1252 { 446, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #446 = FMOVRD
1253 { 445, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 245, 0, 0x0ULL }, // Inst #445 = FMOVQ_XCC
1254 { 444, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 245, 0, 0x0ULL }, // Inst #444 = FMOVQ_ICC
1255 { 443, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 245, 0, 0x0ULL }, // Inst #443 = FMOVQ_FCC
1256 { 442, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 214, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #442 = FMOVQ
1257 { 441, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 241, 0, 0x0ULL }, // Inst #441 = FMOVD_XCC
1258 { 440, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 241, 0, 0x0ULL }, // Inst #440 = FMOVD_ICC
1259 { 439, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 241, 0, 0x0ULL }, // Inst #439 = FMOVD_FCC
1260 { 438, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #438 = FMOVD
1261 { 437, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #437 = FMEAN16
1262 { 436, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #436 = FLUSHrr
1263 { 435, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #435 = FLUSHri
1264 { 434, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #434 = FLUSHW
1265 { 433, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #433 = FLUSH
1266 { 432, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #432 = FLCMPS
1267 { 431, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #431 = FLCMPD
1268 { 430, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL }, // Inst #430 = FITOS
1269 { 429, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 236, 0, 0x0ULL }, // Inst #429 = FITOQ
1270 { 428, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 234, 0, 0x0ULL }, // Inst #428 = FITOD
1271 { 427, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #427 = FHSUBS
1272 { 426, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #426 = FHSUBD
1273 { 425, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #425 = FHADDS
1274 { 424, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #424 = FHADDD
1275 { 423, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #423 = FEXPAND
1276 { 422, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL }, // Inst #422 = FDTOX
1277 { 421, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 230, 0, 0x0ULL }, // Inst #421 = FDTOS
1278 { 420, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 232, 0, 0x0ULL }, // Inst #420 = FDTOQ
1279 { 419, 2, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 230, 0, 0x0ULL }, // Inst #419 = FDTOI
1280 { 418, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 227, 0, 0x0ULL }, // Inst #418 = FDMULQ
1281 { 417, 3, 1, 4, 7, 0, 0, SparcImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #417 = FDIVS
1282 { 416, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 218, 0, 0x0ULL }, // Inst #416 = FDIVQ
1283 { 415, 3, 1, 4, 6, 0, 0, SparcImpOpBase + 0, 190, 0, 0x0ULL }, // Inst #415 = FDIVD
1284 { 414, 2, 0, 4, 5, 0, 1, SparcImpOpBase + 3, 216, 0, 0x0ULL }, // Inst #414 = FCMPS_V9
1285 { 413, 2, 0, 4, 5, 0, 1, SparcImpOpBase + 3, 216, 0, 0x0ULL }, // Inst #413 = FCMPS
1286 { 412, 2, 0, 4, 0, 0, 1, SparcImpOpBase + 3, 214, 0, 0x0ULL }, // Inst #412 = FCMPQ_V9
1287 { 411, 2, 0, 4, 0, 0, 1, SparcImpOpBase + 3, 214, 0, 0x0ULL }, // Inst #411 = FCMPQ
1288 { 410, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #410 = FCMPNE32
1289 { 409, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #409 = FCMPNE16
1290 { 408, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #408 = FCMPLE32
1291 { 407, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #407 = FCMPLE16
1292 { 406, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #406 = FCMPGT32
1293 { 405, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #405 = FCMPGT16
1294 { 404, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #404 = FCMPEQ32
1295 { 403, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #403 = FCMPEQ16
1296 { 402, 2, 0, 4, 5, 0, 1, SparcImpOpBase + 3, 212, 0, 0x0ULL }, // Inst #402 = FCMPD_V9
1297 { 401, 2, 0, 4, 5, 0, 1, SparcImpOpBase + 3, 212, 0, 0x0ULL }, // Inst #401 = FCMPD
1298 { 400, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #400 = FCHKSM16
1299 { 399, 2, 0, 4, 2, 1, 0, SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #399 = FBCOND_V9
1300 { 398, 2, 0, 4, 2, 1, 0, SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #398 = FBCONDA_V9
1301 { 397, 2, 0, 4, 2, 1, 0, SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #397 = FBCONDA
1302 { 396, 2, 0, 4, 2, 1, 0, SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #396 = FBCOND
1303 { 395, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #395 = FANDS
1304 { 394, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #394 = FANDNOT2S
1305 { 393, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #393 = FANDNOT2
1306 { 392, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #392 = FANDNOT1S
1307 { 391, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #391 = FANDNOT1
1308 { 390, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #390 = FAND
1309 { 389, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #389 = FALIGNADATA
1310 { 388, 3, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #388 = FADDS
1311 { 387, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 218, 0, 0x0ULL }, // Inst #387 = FADDQ
1312 { 386, 3, 1, 4, 5, 0, 0, SparcImpOpBase + 0, 190, 0, 0x0ULL }, // Inst #386 = FADDD
1313 { 385, 2, 1, 4, 4, 0, 0, SparcImpOpBase + 0, 216, 0, 0x0ULL }, // Inst #385 = FABSS
1314 { 384, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 214, 0, 0x0ULL }, // Inst #384 = FABSQ
1315 { 383, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 212, 0, 0x0ULL }, // Inst #383 = FABSD
1316 { 382, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #382 = EDGE8N
1317 { 381, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #381 = EDGE8LN
1318 { 380, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #380 = EDGE8L
1319 { 379, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #379 = EDGE8
1320 { 378, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #378 = EDGE32N
1321 { 377, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #377 = EDGE32LN
1322 { 376, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #376 = EDGE32L
1323 { 375, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #375 = EDGE32
1324 { 374, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #374 = EDGE16N
1325 { 373, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #373 = EDGE16LN
1326 { 372, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #372 = EDGE16L
1327 { 371, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #371 = EDGE16
1328 { 370, 0, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #370 = DONE
1329 { 369, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #369 = CMASK8
1330 { 368, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #368 = CMASK32
1331 { 367, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #367 = CMASK16
1332 { 366, 2, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #366 = CBCONDA
1333 { 365, 2, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #365 = CBCOND
1334 { 364, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #364 = CASXArr
1335 { 363, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 8, 202, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #363 = CASXAri
1336 { 362, 5, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 197, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #362 = CASArr
1337 { 361, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 8, 193, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #361 = CASAri
1338 { 360, 2, 0, 4, 3, 1, 0, SparcImpOpBase + 7, 182, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #360 = CALLrr
1339 { 359, 2, 0, 4, 3, 1, 0, SparcImpOpBase + 7, 35, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #359 = CALLri
1340 { 358, 1, 0, 4, 3, 1, 0, SparcImpOpBase + 7, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #358 = CALL
1341 { 357, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #357 = BSHUFFLE
1342 { 356, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #356 = BPXCCNT
1343 { 355, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #355 = BPXCCANT
1344 { 354, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #354 = BPXCCA
1345 { 353, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #353 = BPXCC
1346 { 352, 3, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 187, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #352 = BPRNT
1347 { 351, 3, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 187, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #351 = BPRANT
1348 { 350, 3, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 187, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #350 = BPRA
1349 { 349, 3, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 187, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #349 = BPR
1350 { 348, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #348 = BPICCNT
1351 { 347, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #347 = BPICCANT
1352 { 346, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #346 = BPICCA
1353 { 345, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #345 = BPICC
1354 { 344, 3, 0, 4, 2, 0, 0, SparcImpOpBase + 0, 184, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #344 = BPFCCNT
1355 { 343, 3, 0, 4, 2, 0, 0, SparcImpOpBase + 0, 184, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #343 = BPFCCANT
1356 { 342, 3, 0, 4, 2, 0, 0, SparcImpOpBase + 0, 184, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #342 = BPFCCA
1357 { 341, 3, 0, 4, 2, 0, 0, SparcImpOpBase + 0, 184, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #341 = BPFCC
1358 { 340, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #340 = BMASK
1359 { 339, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #339 = BINDrr
1360 { 338, 2, 0, 4, 1, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #338 = BINDri
1361 { 337, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #337 = BCONDA
1362 { 336, 2, 0, 4, 1, 1, 0, SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #336 = BCOND
1363 { 335, 1, 0, 4, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #335 = BA
1364 { 334, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #334 = ARRAY8
1365 { 333, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #333 = ARRAY32
1366 { 332, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #332 = ARRAY16
1367 { 331, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #331 = ANDrr
1368 { 330, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL }, // Inst #330 = ANDri
1369 { 329, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #329 = ANDNrr
1370 { 328, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #328 = ANDNri
1371 { 327, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #327 = ANDNCCrr
1372 { 326, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #326 = ANDNCCri
1373 { 325, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #325 = ANDCCrr
1374 { 324, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #324 = ANDCCri
1375 { 323, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #323 = ALIGNADDRL
1376 { 322, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #322 = ALIGNADDR
1377 { 321, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 176, 0, 0x0ULL }, // Inst #321 = ADDrr
1378 { 320, 3, 1, 4, 1, 0, 0, SparcImpOpBase + 0, 173, 0, 0x0ULL }, // Inst #320 = ADDri
1379 { 319, 3, 1, 4, 0, 1, 1, SparcImpOpBase + 5, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #319 = ADDXCCC
1380 { 318, 3, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #318 = ADDXC
1381 { 317, 3, 1, 4, 1, 1, 1, SparcImpOpBase + 5, 176, 0, 0x0ULL }, // Inst #317 = ADDErr
1382 { 316, 3, 1, 4, 1, 1, 1, SparcImpOpBase + 5, 173, 0, 0x0ULL }, // Inst #316 = ADDEri
1383 { 315, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #315 = ADDCrr
1384 { 314, 3, 1, 4, 1, 1, 0, SparcImpOpBase + 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #314 = ADDCri
1385 { 313, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 176, 0, 0x0ULL }, // Inst #313 = ADDCCrr
1386 { 312, 3, 1, 4, 1, 0, 1, SparcImpOpBase + 4, 173, 0, 0x0ULL }, // Inst #312 = ADDCCri
1387 { 311, 3, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 170, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #311 = SETX
1388 { 310, 2, 1, 4, 0, 0, 0, SparcImpOpBase + 0, 168, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #310 = SET
1389 { 309, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #309 = SELECT_CC_QFP_XCC
1390 { 308, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #308 = SELECT_CC_QFP_ICC
1391 { 307, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #307 = SELECT_CC_QFP_FCC
1392 { 306, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 160, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #306 = SELECT_CC_Int_XCC
1393 { 305, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 160, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #305 = SELECT_CC_Int_ICC
1394 { 304, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 160, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #304 = SELECT_CC_Int_FCC
1395 { 303, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #303 = SELECT_CC_FP_XCC
1396 { 302, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #302 = SELECT_CC_FP_ICC
1397 { 301, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #301 = SELECT_CC_FP_FCC
1398 { 300, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #300 = SELECT_CC_DFP_XCC
1399 { 299, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 4, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #299 = SELECT_CC_DFP_ICC
1400 { 298, 4, 1, 4, 0, 1, 0, SparcImpOpBase + 3, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #298 = SELECT_CC_DFP_FCC
1401 { 297, 1, 1, 4, 0, 0, 1, SparcImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #297 = GETPCX
1402 { 296, 2, 0, 4, 0, 1, 1, SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #296 = ADJCALLSTACKUP
1403 { 295, 2, 0, 4, 0, 1, 1, SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #295 = ADJCALLSTACKDOWN
1404 { 294, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_UBFX
1405 { 293, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_SBFX
1406 { 292, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMIN
1407 { 291, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_UMAX
1408 { 290, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMIN
1409 { 289, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #289 = G_VECREDUCE_SMAX
1410 { 288, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #288 = G_VECREDUCE_XOR
1411 { 287, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #287 = G_VECREDUCE_OR
1412 { 286, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #286 = G_VECREDUCE_AND
1413 { 285, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #285 = G_VECREDUCE_MUL
1414 { 284, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #284 = G_VECREDUCE_ADD
1415 { 283, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMINIMUM
1416 { 282, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMAXIMUM
1417 { 281, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMIN
1418 { 280, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMAX
1419 { 279, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #279 = G_VECREDUCE_FMUL
1420 { 278, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #278 = G_VECREDUCE_FADD
1421 { 277, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FMUL
1422 { 276, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #276 = G_VECREDUCE_SEQ_FADD
1423 { 275, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_UBSANTRAP
1424 { 274, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_DEBUGTRAP
1425 { 273, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = G_TRAP
1426 { 272, 3, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #272 = G_BZERO
1427 { 271, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #271 = G_MEMSET
1428 { 270, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #270 = G_MEMMOVE
1429 { 269, 3, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #269 = G_MEMCPY_INLINE
1430 { 268, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #268 = G_MEMCPY
1431 { 267, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_WRITE_REGISTER
1432 { 266, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #266 = G_READ_REGISTER
1433 { 265, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #265 = G_STRICT_FLDEXP
1434 { 264, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #264 = G_STRICT_FSQRT
1435 { 263, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #263 = G_STRICT_FMA
1436 { 262, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #262 = G_STRICT_FREM
1437 { 261, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #261 = G_STRICT_FDIV
1438 { 260, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #260 = G_STRICT_FMUL
1439 { 259, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #259 = G_STRICT_FSUB
1440 { 258, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #258 = G_STRICT_FADD
1441 { 257, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #257 = G_STACKRESTORE
1442 { 256, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #256 = G_STACKSAVE
1443 { 255, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #255 = G_DYN_STACKALLOC
1444 { 254, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_JUMP_TABLE
1445 { 253, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_BLOCK_ADDR
1446 { 252, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_ADDRSPACE_CAST
1447 { 251, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FNEARBYINT
1448 { 250, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_FRINT
1449 { 249, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_FFLOOR
1450 { 248, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_FSQRT
1451 { 247, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_FTANH
1452 { 246, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_FSINH
1453 { 245, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_FCOSH
1454 { 244, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_FATAN
1455 { 243, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_FASIN
1456 { 242, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_FACOS
1457 { 241, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_FTAN
1458 { 240, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_FSIN
1459 { 239, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_FCOS
1460 { 238, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_FCEIL
1461 { 237, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_BITREVERSE
1462 { 236, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_BSWAP
1463 { 235, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_CTPOP
1464 { 234, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #234 = G_CTLZ_ZERO_UNDEF
1465 { 233, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #233 = G_CTLZ
1466 { 232, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_CTTZ_ZERO_UNDEF
1467 { 231, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_CTTZ
1468 { 230, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_VECTOR_COMPRESS
1469 { 229, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #229 = G_SPLAT_VECTOR
1470 { 228, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #228 = G_SHUFFLE_VECTOR
1471 { 227, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #227 = G_EXTRACT_VECTOR_ELT
1472 { 226, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #226 = G_INSERT_VECTOR_ELT
1473 { 225, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_EXTRACT_SUBVECTOR
1474 { 224, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_INSERT_SUBVECTOR
1475 { 223, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #223 = G_VSCALE
1476 { 222, 3, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #222 = G_BRJT
1477 { 221, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #221 = G_BR
1478 { 220, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #220 = G_LLROUND
1479 { 219, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #219 = G_LROUND
1480 { 218, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #218 = G_ABS
1481 { 217, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_UMAX
1482 { 216, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_UMIN
1483 { 215, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_SMAX
1484 { 214, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #214 = G_SMIN
1485 { 213, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #213 = G_PTRMASK
1486 { 212, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #212 = G_PTR_ADD
1487 { 211, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #211 = G_RESET_FPMODE
1488 { 210, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #210 = G_SET_FPMODE
1489 { 209, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #209 = G_GET_FPMODE
1490 { 208, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #208 = G_RESET_FPENV
1491 { 207, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #207 = G_SET_FPENV
1492 { 206, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #206 = G_GET_FPENV
1493 { 205, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #205 = G_FMAXIMUM
1494 { 204, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #204 = G_FMINIMUM
1495 { 203, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #203 = G_FMAXNUM_IEEE
1496 { 202, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #202 = G_FMINNUM_IEEE
1497 { 201, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #201 = G_FMAXNUM
1498 { 200, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #200 = G_FMINNUM
1499 { 199, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_FCANONICALIZE
1500 { 198, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_IS_FPCLASS
1501 { 197, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FCOPYSIGN
1502 { 196, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FABS
1503 { 195, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_UITOFP
1504 { 194, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_SITOFP
1505 { 193, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FPTOUI
1506 { 192, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FPTOSI
1507 { 191, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FPTRUNC
1508 { 190, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FPEXT
1509 { 189, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FNEG
1510 { 188, 3, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FFREXP
1511 { 187, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FLDEXP
1512 { 186, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FLOG10
1513 { 185, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FLOG2
1514 { 184, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FLOG
1515 { 183, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FEXP10
1516 { 182, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #182 = G_FEXP2
1517 { 181, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FEXP
1518 { 180, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #180 = G_FPOWI
1519 { 179, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_FPOW
1520 { 178, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_FREM
1521 { 177, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_FDIV
1522 { 176, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_FMAD
1523 { 175, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #175 = G_FMA
1524 { 174, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #174 = G_FMUL
1525 { 173, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #173 = G_FSUB
1526 { 172, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #172 = G_FADD
1527 { 171, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_UDIVFIXSAT
1528 { 170, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_SDIVFIXSAT
1529 { 169, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_UDIVFIX
1530 { 168, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_SDIVFIX
1531 { 167, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_UMULFIXSAT
1532 { 166, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_SMULFIXSAT
1533 { 165, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_UMULFIX
1534 { 164, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #164 = G_SMULFIX
1535 { 163, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #163 = G_SSHLSAT
1536 { 162, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #162 = G_USHLSAT
1537 { 161, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SSUBSAT
1538 { 160, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_USUBSAT
1539 { 159, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #159 = G_SADDSAT
1540 { 158, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_UADDSAT
1541 { 157, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #157 = G_SMULH
1542 { 156, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #156 = G_UMULH
1543 { 155, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #155 = G_SMULO
1544 { 154, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_UMULO
1545 { 153, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SSUBE
1546 { 152, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_SSUBO
1547 { 151, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_SADDE
1548 { 150, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #150 = G_SADDO
1549 { 149, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_USUBE
1550 { 148, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_USUBO
1551 { 147, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_UADDE
1552 { 146, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #146 = G_UADDO
1553 { 145, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_SELECT
1554 { 144, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_UCMP
1555 { 143, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_SCMP
1556 { 142, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_FCMP
1557 { 141, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ICMP
1558 { 140, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_ROTL
1559 { 139, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_ROTR
1560 { 138, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #138 = G_FSHR
1561 { 137, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #137 = G_FSHL
1562 { 136, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_ASHR
1563 { 135, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_LSHR
1564 { 134, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_SHL
1565 { 133, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ZEXT
1566 { 132, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #132 = G_SEXT_INREG
1567 { 131, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #131 = G_SEXT
1568 { 130, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #130 = G_VAARG
1569 { 129, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #129 = G_VASTART
1570 { 128, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #128 = G_FCONSTANT
1571 { 127, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #127 = G_CONSTANT
1572 { 126, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #126 = G_TRUNC
1573 { 125, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #125 = G_ANYEXT
1574 { 124, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1575 { 123, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #123 = G_INTRINSIC_CONVERGENT
1576 { 122, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #122 = G_INTRINSIC_W_SIDE_EFFECTS
1577 { 121, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #121 = G_INTRINSIC
1578 { 120, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #120 = G_INVOKE_REGION_START
1579 { 119, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #119 = G_BRINDIRECT
1580 { 118, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #118 = G_BRCOND
1581 { 117, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #117 = G_PREFETCH
1582 { 116, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #116 = G_FENCE
1583 { 115, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UDEC_WRAP
1584 { 114, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_UINC_WRAP
1585 { 113, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMIN
1586 { 112, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FMAX
1587 { 111, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FSUB
1588 { 110, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_FADD
1589 { 109, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMIN
1590 { 108, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_UMAX
1591 { 107, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MIN
1592 { 106, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_MAX
1593 { 105, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_XOR
1594 { 104, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_OR
1595 { 103, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_NAND
1596 { 102, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMICRMW_AND
1597 { 101, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMICRMW_SUB
1598 { 100, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_ATOMICRMW_ADD
1599 { 99, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_ATOMICRMW_XCHG
1600 { 98, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG
1601 { 97, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #97 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1602 { 96, 5, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #96 = G_INDEXED_STORE
1603 { 95, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #95 = G_STORE
1604 { 94, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_INDEXED_ZEXTLOAD
1605 { 93, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_INDEXED_SEXTLOAD
1606 { 92, 5, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #92 = G_INDEXED_LOAD
1607 { 91, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #91 = G_ZEXTLOAD
1608 { 90, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #90 = G_SEXTLOAD
1609 { 89, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #89 = G_LOAD
1610 { 88, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #88 = G_READSTEADYCOUNTER
1611 { 87, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #87 = G_READCYCLECOUNTER
1612 { 86, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_ROUNDEVEN
1613 { 85, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_LLRINT
1614 { 84, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_INTRINSIC_LRINT
1615 { 83, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_INTRINSIC_ROUND
1616 { 82, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_INTRINSIC_TRUNC
1617 { 81, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_INTRINSIC_FPTRUNC_ROUND
1618 { 80, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_CONSTANT_FOLD_BARRIER
1619 { 79, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #79 = G_FREEZE
1620 { 78, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #78 = G_BITCAST
1621 { 77, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #77 = G_INTTOPTR
1622 { 76, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #76 = G_PTRTOINT
1623 { 75, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #75 = G_CONCAT_VECTORS
1624 { 74, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR_TRUNC
1625 { 73, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #73 = G_BUILD_VECTOR
1626 { 72, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #72 = G_MERGE_VALUES
1627 { 71, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_INSERT
1628 { 70, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #70 = G_UNMERGE_VALUES
1629 { 69, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_EXTRACT
1630 { 68, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #68 = G_CONSTANT_POOL
1631 { 67, 5, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_PTRAUTH_GLOBAL_VALUE
1632 { 66, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #66 = G_GLOBAL_VALUE
1633 { 65, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #65 = G_FRAME_INDEX
1634 { 64, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #64 = G_PHI
1635 { 63, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #63 = G_IMPLICIT_DEF
1636 { 62, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_XOR
1637 { 61, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #61 = G_OR
1638 { 60, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #60 = G_AND
1639 { 59, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UDIVREM
1640 { 58, 4, 2, 0, 0, 0, 0, SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SDIVREM
1641 { 57, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UREM
1642 { 56, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SREM
1643 { 55, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #55 = G_UDIV
1644 { 54, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SDIV
1645 { 53, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_MUL
1646 { 52, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_SUB
1647 { 51, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #51 = G_ADD
1648 { 50, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_ALIGN
1649 { 49, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #49 = G_ASSERT_ZEXT
1650 { 48, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #48 = G_ASSERT_SEXT
1651 { 47, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_GLUE
1652 { 46, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_LOOP
1653 { 45, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ANCHOR
1654 { 44, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #44 = CONVERGENCECTRL_ENTRY
1655 { 43, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #43 = JUMP_TABLE_DEBUG_INFO
1656 { 42, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = MEMBARRIER
1657 { 41, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL
1658 { 40, 3, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
1659 { 39, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL
1660 { 38, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL
1661 { 37, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT
1662 { 36, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_RET
1663 { 35, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER
1664 { 34, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = PATCHABLE_OP
1665 { 33, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #33 = FAULTING_OP
1666 { 32, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE
1667 { 31, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = STATEPOINT
1668 { 30, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG
1669 { 29, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP
1670 { 28, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD
1671 { 27, 6, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = PATCHPOINT
1672 { 26, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = FENTRY_CALL
1673 { 25, 2, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #25 = STACKMAP
1674 { 24, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #24 = ARITH_FENCE
1675 { 23, 4, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #23 = PSEUDO_PROBE
1676 { 22, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_END
1677 { 21, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #21 = LIFETIME_START
1678 { 20, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #20 = BUNDLE
1679 { 19, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = COPY
1680 { 18, 2, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #18 = REG_SEQUENCE
1681 { 17, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #17 = DBG_LABEL
1682 { 16, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_PHI
1683 { 15, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_INSTR_REF
1684 { 14, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST
1685 { 13, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #13 = DBG_VALUE
1686 { 12, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS
1687 { 11, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = SUBREG_TO_REG
1688 { 10, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
1689 { 9, 4, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG
1690 { 8, 3, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
1691 { 7, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL
1692 { 6, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
1693 { 5, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL
1694 { 4, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL
1695 { 3, 1, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
1696 { 2, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR
1697 { 1, 0, 0, 0, 0, 0, 0, SparcImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM
1698 { 0, 1, 1, 0, 0, 0, 0, SparcImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI
1699 }, {
1700 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1701 /* 1 */
1702 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1703 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1704 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1705 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1706 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1707 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1708 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1709 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1710 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1711 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1712 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1713 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1714 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1715 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1716 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1717 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1718 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1719 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1720 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1721 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1722 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1723 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1724 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1725 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1726 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1727 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1728 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1729 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1730 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1731 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1732 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1733 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1734 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1735 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1736 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1737 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1738 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1739 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1740 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1741 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1742 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1743 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1744 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1745 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1746 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1747 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1748 /* 152 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1749 /* 156 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1750 /* 160 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1751 /* 164 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1752 /* 168 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1753 /* 170 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1754 /* 173 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1755 /* 176 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1756 /* 179 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1757 /* 182 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1758 /* 184 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1759 /* 187 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1760 /* 190 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1761 /* 193 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1762 /* 197 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1763 /* 202 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1764 /* 206 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1765 /* 211 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1766 /* 212 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1767 /* 214 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1768 /* 216 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1769 /* 218 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1770 /* 221 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1771 /* 224 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1772 /* 227 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1773 /* 230 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1774 /* 232 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1775 /* 234 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1776 /* 236 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1777 /* 238 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1778 /* 241 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1779 /* 245 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1780 /* 249 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1781 /* 254 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1782 /* 259 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1783 /* 264 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1784 /* 268 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1785 /* 270 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1786 /* 272 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1787 /* 274 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1788 /* 276 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1789 /* 279 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1790 /* 283 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1791 /* 287 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1792 /* 290 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1793 /* 293 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1794 /* 296 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1795 /* 299 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1796 /* 302 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1797 /* 306 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1798 /* 309 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1799 /* 312 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1800 /* 315 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1801 /* 319 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1802 /* 322 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1803 /* 325 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1804 /* 328 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1805 /* 332 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1806 /* 335 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1807 /* 338 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1808 /* 342 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1809 /* 345 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1810 /* 348 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1811 /* 351 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1812 /* 353 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1813 /* 355 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1814 /* 359 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1815 /* 363 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1816 /* 368 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1817 /* 373 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1818 /* 375 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1819 /* 377 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1820 /* 380 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1821 /* 384 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1822 /* 387 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1823 /* 389 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1824 /* 390 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1825 /* 392 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1826 /* 395 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1827 /* 398 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1828 /* 401 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1829 /* 405 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1830 /* 409 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1831 /* 412 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1832 /* 416 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1833 /* 419 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1834 /* 422 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1835 /* 425 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1836 /* 428 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1837 /* 432 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1838 /* 435 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1839 /* 438 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1840 /* 441 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1841 /* 445 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1842 /* 448 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1843 /* 451 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1844 /* 454 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1845 /* 458 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1846 /* 461 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1847 /* 464 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1848 /* 468 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1849 /* 471 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1850 /* 474 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1851 /* 478 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1852 /* 481 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1853 /* 485 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1854 /* 490 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1855 /* 494 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1856 /* 497 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1857 /* 501 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1858 /* 504 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1859 /* 507 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1860 /* 512 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1861 /* 517 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1862 /* 522 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1863 /* 527 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1864 /* 532 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1865 /* 535 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1866 /* 538 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1867 /* 541 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1868 }, {
1869 /* 0 */
1870 /* 0 */ SP::O6, SP::O6,
1871 /* 2 */ SP::O7,
1872 /* 3 */ SP::FCC0,
1873 /* 4 */ SP::ICC,
1874 /* 5 */ SP::ICC, SP::ICC,
1875 /* 7 */ SP::O6,
1876 /* 8 */ SP::ASR3,
1877 /* 9 */ SP::CPSR,
1878 /* 10 */ SP::FSR,
1879 /* 11 */ SP::Y, SP::ICC, SP::Y, SP::ICC,
1880 /* 15 */ SP::PSR,
1881 /* 16 */ SP::FQ,
1882 /* 17 */ SP::TBR,
1883 /* 18 */ SP::WIM,
1884 /* 19 */ SP::Y, SP::Y, SP::ICC,
1885 /* 22 */ SP::Y, SP::Y,
1886 /* 24 */ SP::Y, SP::ASR18, SP::Y, SP::ASR18,
1887 /* 28 */ SP::Y, SP::ICC,
1888 /* 30 */ SP::Y,
1889 /* 31 */ SP::CPQ,
1890 }
1891};
1892
1893
1894#ifdef __GNUC__
1895#pragma GCC diagnostic push
1896#pragma GCC diagnostic ignored "-Woverlength-strings"
1897#endif
1898extern const char SparcInstrNameData[] = {
1899 /* 0 */ "G_FLOG10\0"
1900 /* 9 */ "G_FEXP10\0"
1901 /* 18 */ "TA1\0"
1902 /* 22 */ "FSRC1\0"
1903 /* 28 */ "FANDNOT1\0"
1904 /* 37 */ "FNOT1\0"
1905 /* 43 */ "FORNOT1\0"
1906 /* 51 */ "FSRA32\0"
1907 /* 58 */ "FPSUB32\0"
1908 /* 66 */ "FPADD32\0"
1909 /* 74 */ "EDGE32\0"
1910 /* 81 */ "FCMPLE32\0"
1911 /* 90 */ "FCMPNE32\0"
1912 /* 99 */ "FPACK32\0"
1913 /* 107 */ "CMASK32\0"
1914 /* 115 */ "FSLL32\0"
1915 /* 122 */ "FSRL32\0"
1916 /* 129 */ "FCMPEQ32\0"
1917 /* 138 */ "FSLAS32\0"
1918 /* 146 */ "FCMPGT32\0"
1919 /* 155 */ "ARRAY32\0"
1920 /* 163 */ "FSRC2\0"
1921 /* 169 */ "G_FLOG2\0"
1922 /* 177 */ "G_FEXP2\0"
1923 /* 185 */ "FANDNOT2\0"
1924 /* 194 */ "FNOT2\0"
1925 /* 200 */ "FORNOT2\0"
1926 /* 208 */ "TA3\0"
1927 /* 212 */ "FPADD64\0"
1928 /* 220 */ "TA5\0"
1929 /* 224 */ "FSRA16\0"
1930 /* 231 */ "FPSUB16\0"
1931 /* 239 */ "FPADD16\0"
1932 /* 247 */ "EDGE16\0"
1933 /* 254 */ "FCMPLE16\0"
1934 /* 263 */ "FCMPNE16\0"
1935 /* 272 */ "FPACK16\0"
1936 /* 280 */ "CMASK16\0"
1937 /* 288 */ "FSLL16\0"
1938 /* 295 */ "FSRL16\0"
1939 /* 302 */ "FCHKSM16\0"
1940 /* 311 */ "FMEAN16\0"
1941 /* 319 */ "FCMPEQ16\0"
1942 /* 328 */ "FSLAS16\0"
1943 /* 336 */ "FCMPGT16\0"
1944 /* 345 */ "FMUL8X16\0"
1945 /* 354 */ "FMULD8ULX16\0"
1946 /* 366 */ "FMUL8ULX16\0"
1947 /* 377 */ "FMULD8SUX16\0"
1948 /* 389 */ "FMUL8SUX16\0"
1949 /* 400 */ "ARRAY16\0"
1950 /* 408 */ "EDGE8\0"
1951 /* 414 */ "CMASK8\0"
1952 /* 421 */ "ARRAY8\0"
1953 /* 428 */ "FBCONDA_V9\0"
1954 /* 439 */ "FBCOND_V9\0"
1955 /* 449 */ "FCMPD_V9\0"
1956 /* 458 */ "FCMPQ_V9\0"
1957 /* 467 */ "FCMPS_V9\0"
1958 /* 476 */ "BA\0"
1959 /* 479 */ "BPFCCA\0"
1960 /* 486 */ "BPICCA\0"
1961 /* 493 */ "BPXCCA\0"
1962 /* 500 */ "CBCONDA\0"
1963 /* 508 */ "FBCONDA\0"
1964 /* 516 */ "G_FMA\0"
1965 /* 522 */ "G_STRICT_FMA\0"
1966 /* 535 */ "BPRA\0"
1967 /* 540 */ "FALIGNADATA\0"
1968 /* 552 */ "G_FSUB\0"
1969 /* 559 */ "G_STRICT_FSUB\0"
1970 /* 573 */ "G_ATOMICRMW_FSUB\0"
1971 /* 590 */ "G_SUB\0"
1972 /* 596 */ "G_ATOMICRMW_SUB\0"
1973 /* 612 */ "ADDXCCC\0"
1974 /* 620 */ "BPFCC\0"
1975 /* 626 */ "V9FMOVD_FCC\0"
1976 /* 638 */ "SELECT_CC_DFP_FCC\0"
1977 /* 656 */ "SELECT_CC_QFP_FCC\0"
1978 /* 674 */ "SELECT_CC_FP_FCC\0"
1979 /* 691 */ "V9FMOVQ_FCC\0"
1980 /* 703 */ "V9FMOVS_FCC\0"
1981 /* 715 */ "SELECT_CC_Int_FCC\0"
1982 /* 733 */ "BPICC\0"
1983 /* 739 */ "FMOVD_ICC\0"
1984 /* 749 */ "SELECT_CC_DFP_ICC\0"
1985 /* 767 */ "SELECT_CC_QFP_ICC\0"
1986 /* 785 */ "SELECT_CC_FP_ICC\0"
1987 /* 802 */ "FMOVQ_ICC\0"
1988 /* 812 */ "FMOVS_ICC\0"
1989 /* 822 */ "SELECT_CC_Int_ICC\0"
1990 /* 840 */ "BPXCC\0"
1991 /* 846 */ "FMOVD_XCC\0"
1992 /* 856 */ "SELECT_CC_DFP_XCC\0"
1993 /* 874 */ "SELECT_CC_QFP_XCC\0"
1994 /* 892 */ "SELECT_CC_FP_XCC\0"
1995 /* 909 */ "FMOVQ_XCC\0"
1996 /* 919 */ "FMOVS_XCC\0"
1997 /* 929 */ "SELECT_CC_Int_XCC\0"
1998 /* 947 */ "G_INTRINSIC\0"
1999 /* 959 */ "G_FPTRUNC\0"
2000 /* 969 */ "G_INTRINSIC_TRUNC\0"
2001 /* 987 */ "G_TRUNC\0"
2002 /* 995 */ "G_BUILD_VECTOR_TRUNC\0"
2003 /* 1016 */ "G_DYN_STACKALLOC\0"
2004 /* 1033 */ "ADDXC\0"
2005 /* 1039 */ "G_FMAD\0"
2006 /* 1046 */ "G_INDEXED_SEXTLOAD\0"
2007 /* 1065 */ "G_SEXTLOAD\0"
2008 /* 1076 */ "G_INDEXED_ZEXTLOAD\0"
2009 /* 1095 */ "G_ZEXTLOAD\0"
2010 /* 1106 */ "G_INDEXED_LOAD\0"
2011 /* 1121 */ "G_LOAD\0"
2012 /* 1128 */ "FSUBD\0"
2013 /* 1134 */ "FHSUBD\0"
2014 /* 1141 */ "G_VECREDUCE_FADD\0"
2015 /* 1158 */ "G_FADD\0"
2016 /* 1165 */ "G_VECREDUCE_SEQ_FADD\0"
2017 /* 1186 */ "G_STRICT_FADD\0"
2018 /* 1200 */ "G_ATOMICRMW_FADD\0"
2019 /* 1217 */ "G_VECREDUCE_ADD\0"
2020 /* 1233 */ "G_ADD\0"
2021 /* 1239 */ "G_PTR_ADD\0"
2022 /* 1249 */ "G_ATOMICRMW_ADD\0"
2023 /* 1265 */ "FADDD\0"
2024 /* 1271 */ "FHADDD\0"
2025 /* 1278 */ "FNHADDD\0"
2026 /* 1286 */ "FNADDD\0"
2027 /* 1293 */ "V9FCMPED\0"
2028 /* 1302 */ "RESTORED\0"
2029 /* 1311 */ "SAVED\0"
2030 /* 1317 */ "FNEGD\0"
2031 /* 1323 */ "FMULD\0"
2032 /* 1329 */ "FNMULD\0"
2033 /* 1336 */ "FSMULD\0"
2034 /* 1343 */ "FNSMULD\0"
2035 /* 1351 */ "FAND\0"
2036 /* 1356 */ "FNAND\0"
2037 /* 1362 */ "G_ATOMICRMW_NAND\0"
2038 /* 1379 */ "FEXPAND\0"
2039 /* 1387 */ "G_VECREDUCE_AND\0"
2040 /* 1403 */ "G_AND\0"
2041 /* 1409 */ "G_ATOMICRMW_AND\0"
2042 /* 1425 */ "LIFETIME_END\0"
2043 /* 1438 */ "CBCOND\0"
2044 /* 1445 */ "FBCOND\0"
2045 /* 1452 */ "G_BRCOND\0"
2046 /* 1461 */ "G_LLROUND\0"
2047 /* 1471 */ "G_LROUND\0"
2048 /* 1480 */ "G_INTRINSIC_ROUND\0"
2049 /* 1498 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
2050 /* 1524 */ "FITOD\0"
2051 /* 1530 */ "FQTOD\0"
2052 /* 1536 */ "FSTOD\0"
2053 /* 1542 */ "FXTOD\0"
2054 /* 1548 */ "MOVXTOD\0"
2055 /* 1556 */ "V9FCMPD\0"
2056 /* 1564 */ "FLCMPD\0"
2057 /* 1571 */ "LOAD_STACK_GUARD\0"
2058 /* 1588 */ "FMOVRD\0"
2059 /* 1595 */ "FABSD\0"
2060 /* 1601 */ "FSQRTD\0"
2061 /* 1608 */ "FDIVD\0"
2062 /* 1614 */ "FMOVD\0"
2063 /* 1620 */ "PSEUDO_PROBE\0"
2064 /* 1633 */ "G_SSUBE\0"
2065 /* 1641 */ "G_USUBE\0"
2066 /* 1649 */ "G_FENCE\0"
2067 /* 1657 */ "ARITH_FENCE\0"
2068 /* 1669 */ "REG_SEQUENCE\0"
2069 /* 1682 */ "G_SADDE\0"
2070 /* 1690 */ "G_UADDE\0"
2071 /* 1698 */ "G_GET_FPMODE\0"
2072 /* 1711 */ "G_RESET_FPMODE\0"
2073 /* 1726 */ "G_SET_FPMODE\0"
2074 /* 1739 */ "G_FMINNUM_IEEE\0"
2075 /* 1754 */ "G_FMAXNUM_IEEE\0"
2076 /* 1769 */ "FPMERGE\0"
2077 /* 1777 */ "G_VSCALE\0"
2078 /* 1786 */ "G_JUMP_TABLE\0"
2079 /* 1799 */ "BUNDLE\0"
2080 /* 1806 */ "BSHUFFLE\0"
2081 /* 1815 */ "G_MEMCPY_INLINE\0"
2082 /* 1831 */ "DONE\0"
2083 /* 1836 */ "FONE\0"
2084 /* 1841 */ "LOCAL_ESCAPE\0"
2085 /* 1854 */ "G_STACKRESTORE\0"
2086 /* 1869 */ "G_INDEXED_STORE\0"
2087 /* 1885 */ "G_STORE\0"
2088 /* 1893 */ "G_BITREVERSE\0"
2089 /* 1906 */ "DBG_VALUE\0"
2090 /* 1916 */ "G_GLOBAL_VALUE\0"
2091 /* 1931 */ "G_PTRAUTH_GLOBAL_VALUE\0"
2092 /* 1954 */ "CONVERGENCECTRL_GLUE\0"
2093 /* 1975 */ "G_STACKSAVE\0"
2094 /* 1987 */ "G_MEMMOVE\0"
2095 /* 1997 */ "G_FREEZE\0"
2096 /* 2006 */ "G_FCANONICALIZE\0"
2097 /* 2022 */ "G_CTLZ_ZERO_UNDEF\0"
2098 /* 2040 */ "G_CTTZ_ZERO_UNDEF\0"
2099 /* 2058 */ "G_IMPLICIT_DEF\0"
2100 /* 2073 */ "DBG_INSTR_REF\0"
2101 /* 2087 */ "G_FNEG\0"
2102 /* 2094 */ "EXTRACT_SUBREG\0"
2103 /* 2109 */ "INSERT_SUBREG\0"
2104 /* 2123 */ "G_SEXT_INREG\0"
2105 /* 2136 */ "SUBREG_TO_REG\0"
2106 /* 2150 */ "G_ATOMIC_CMPXCHG\0"
2107 /* 2167 */ "G_ATOMICRMW_XCHG\0"
2108 /* 2184 */ "G_FLOG\0"
2109 /* 2191 */ "G_VAARG\0"
2110 /* 2199 */ "PREALLOCATED_ARG\0"
2111 /* 2216 */ "G_PREFETCH\0"
2112 /* 2227 */ "G_SMULH\0"
2113 /* 2235 */ "G_UMULH\0"
2114 /* 2243 */ "G_FTANH\0"
2115 /* 2251 */ "G_FSINH\0"
2116 /* 2259 */ "G_FCOSH\0"
2117 /* 2267 */ "FLUSH\0"
2118 /* 2273 */ "DBG_PHI\0"
2119 /* 2281 */ "UMULXHI\0"
2120 /* 2289 */ "XMULXHI\0"
2121 /* 2297 */ "FDTOI\0"
2122 /* 2303 */ "FQTOI\0"
2123 /* 2309 */ "FSTOI\0"
2124 /* 2315 */ "G_FPTOSI\0"
2125 /* 2324 */ "G_FPTOUI\0"
2126 /* 2333 */ "G_FPOWI\0"
2127 /* 2341 */ "BMASK\0"
2128 /* 2347 */ "G_PTRMASK\0"
2129 /* 2357 */ "EDGE32L\0"
2130 /* 2365 */ "EDGE16L\0"
2131 /* 2373 */ "EDGE8L\0"
2132 /* 2380 */ "FMUL8X16AL\0"
2133 /* 2391 */ "GC_LABEL\0"
2134 /* 2400 */ "DBG_LABEL\0"
2135 /* 2410 */ "EH_LABEL\0"
2136 /* 2419 */ "ANNOTATION_LABEL\0"
2137 /* 2436 */ "ICALL_BRANCH_FUNNEL\0"
2138 /* 2456 */ "G_FSHL\0"
2139 /* 2463 */ "G_SHL\0"
2140 /* 2469 */ "G_FCEIL\0"
2141 /* 2477 */ "PATCHABLE_TAIL_CALL\0"
2142 /* 2497 */ "TLS_CALL\0"
2143 /* 2506 */ "PATCHABLE_TYPED_EVENT_CALL\0"
2144 /* 2533 */ "PATCHABLE_EVENT_CALL\0"
2145 /* 2554 */ "FENTRY_CALL\0"
2146 /* 2566 */ "KILL\0"
2147 /* 2571 */ "G_CONSTANT_POOL\0"
2148 /* 2587 */ "ALIGNADDRL\0"
2149 /* 2598 */ "RETL\0"
2150 /* 2603 */ "G_ROTL\0"
2151 /* 2610 */ "G_VECREDUCE_FMUL\0"
2152 /* 2627 */ "G_FMUL\0"
2153 /* 2634 */ "G_VECREDUCE_SEQ_FMUL\0"
2154 /* 2655 */ "G_STRICT_FMUL\0"
2155 /* 2669 */ "G_VECREDUCE_MUL\0"
2156 /* 2685 */ "G_MUL\0"
2157 /* 2691 */ "SIAM\0"
2158 /* 2696 */ "G_FREM\0"
2159 /* 2703 */ "G_STRICT_FREM\0"
2160 /* 2717 */ "G_SREM\0"
2161 /* 2724 */ "G_UREM\0"
2162 /* 2731 */ "G_SDIVREM\0"
2163 /* 2741 */ "G_UDIVREM\0"
2164 /* 2751 */ "RDWIM\0"
2165 /* 2757 */ "INLINEASM\0"
2166 /* 2767 */ "G_VECREDUCE_FMINIMUM\0"
2167 /* 2788 */ "G_FMINIMUM\0"
2168 /* 2799 */ "G_VECREDUCE_FMAXIMUM\0"
2169 /* 2820 */ "G_FMAXIMUM\0"
2170 /* 2831 */ "G_FMINNUM\0"
2171 /* 2841 */ "G_FMAXNUM\0"
2172 /* 2851 */ "EDGE32N\0"
2173 /* 2859 */ "EDGE16N\0"
2174 /* 2867 */ "EDGE8N\0"
2175 /* 2874 */ "G_FATAN\0"
2176 /* 2882 */ "G_FTAN\0"
2177 /* 2889 */ "G_INTRINSIC_ROUNDEVEN\0"
2178 /* 2911 */ "G_ASSERT_ALIGN\0"
2179 /* 2926 */ "G_FCOPYSIGN\0"
2180 /* 2938 */ "G_VECREDUCE_FMIN\0"
2181 /* 2955 */ "G_ATOMICRMW_FMIN\0"
2182 /* 2972 */ "G_VECREDUCE_SMIN\0"
2183 /* 2989 */ "G_SMIN\0"
2184 /* 2996 */ "G_VECREDUCE_UMIN\0"
2185 /* 3013 */ "G_UMIN\0"
2186 /* 3020 */ "G_ATOMICRMW_UMIN\0"
2187 /* 3037 */ "G_ATOMICRMW_MIN\0"
2188 /* 3053 */ "G_FASIN\0"
2189 /* 3061 */ "G_FSIN\0"
2190 /* 3068 */ "EDGE32LN\0"
2191 /* 3077 */ "EDGE16LN\0"
2192 /* 3086 */ "EDGE8LN\0"
2193 /* 3094 */ "CFI_INSTRUCTION\0"
2194 /* 3110 */ "PDISTN\0"
2195 /* 3117 */ "ADJCALLSTACKDOWN\0"
2196 /* 3134 */ "SHUTDOWN\0"
2197 /* 3143 */ "G_SSUBO\0"
2198 /* 3151 */ "G_USUBO\0"
2199 /* 3159 */ "G_SADDO\0"
2200 /* 3167 */ "G_UADDO\0"
2201 /* 3175 */ "JUMP_TABLE_DEBUG_INFO\0"
2202 /* 3197 */ "G_SMULO\0"
2203 /* 3205 */ "G_UMULO\0"
2204 /* 3213 */ "G_BZERO\0"
2205 /* 3221 */ "FZERO\0"
2206 /* 3227 */ "STACKMAP\0"
2207 /* 3236 */ "G_DEBUGTRAP\0"
2208 /* 3248 */ "G_UBSANTRAP\0"
2209 /* 3260 */ "G_TRAP\0"
2210 /* 3267 */ "G_ATOMICRMW_UDEC_WRAP\0"
2211 /* 3289 */ "G_ATOMICRMW_UINC_WRAP\0"
2212 /* 3311 */ "G_BSWAP\0"
2213 /* 3319 */ "G_SITOFP\0"
2214 /* 3328 */ "G_UITOFP\0"
2215 /* 3337 */ "G_FCMP\0"
2216 /* 3344 */ "G_ICMP\0"
2217 /* 3351 */ "G_SCMP\0"
2218 /* 3358 */ "G_UCMP\0"
2219 /* 3365 */ "UNIMP\0"
2220 /* 3371 */ "NOP\0"
2221 /* 3375 */ "CONVERGENCECTRL_LOOP\0"
2222 /* 3396 */ "G_CTPOP\0"
2223 /* 3404 */ "PATCHABLE_OP\0"
2224 /* 3417 */ "FAULTING_OP\0"
2225 /* 3429 */ "ADJCALLSTACKUP\0"
2226 /* 3444 */ "PREALLOCATED_SETUP\0"
2227 /* 3463 */ "G_FLDEXP\0"
2228 /* 3472 */ "G_STRICT_FLDEXP\0"
2229 /* 3488 */ "G_FEXP\0"
2230 /* 3495 */ "G_FFREXP\0"
2231 /* 3504 */ "FSUBQ\0"
2232 /* 3510 */ "FADDQ\0"
2233 /* 3516 */ "V9FCMPEQ\0"
2234 /* 3525 */ "RDFQ\0"
2235 /* 3530 */ "FNEGQ\0"
2236 /* 3536 */ "FDMULQ\0"
2237 /* 3543 */ "FMULQ\0"
2238 /* 3549 */ "FDTOQ\0"
2239 /* 3555 */ "FITOQ\0"
2240 /* 3561 */ "FSTOQ\0"
2241 /* 3567 */ "FXTOQ\0"
2242 /* 3573 */ "V9FCMPQ\0"
2243 /* 3581 */ "FMOVRQ\0"
2244 /* 3588 */ "FABSQ\0"
2245 /* 3594 */ "FSQRTQ\0"
2246 /* 3601 */ "FDIVQ\0"
2247 /* 3607 */ "FMOVQ\0"
2248 /* 3613 */ "STBAR\0"
2249 /* 3619 */ "RDTBR\0"
2250 /* 3625 */ "G_BR\0"
2251 /* 3630 */ "INLINEASM_BR\0"
2252 /* 3643 */ "ALIGNADDR\0"
2253 /* 3653 */ "G_BLOCK_ADDR\0"
2254 /* 3666 */ "MEMBARRIER\0"
2255 /* 3677 */ "G_CONSTANT_FOLD_BARRIER\0"
2256 /* 3701 */ "PATCHABLE_FUNCTION_ENTER\0"
2257 /* 3726 */ "G_READCYCLECOUNTER\0"
2258 /* 3745 */ "G_READSTEADYCOUNTER\0"
2259 /* 3765 */ "G_READ_REGISTER\0"
2260 /* 3781 */ "G_WRITE_REGISTER\0"
2261 /* 3798 */ "G_ASHR\0"
2262 /* 3805 */ "G_FSHR\0"
2263 /* 3812 */ "G_LSHR\0"
2264 /* 3819 */ "SIR\0"
2265 /* 3823 */ "FOR\0"
2266 /* 3827 */ "CONVERGENCECTRL_ANCHOR\0"
2267 /* 3850 */ "FNOR\0"
2268 /* 3855 */ "FXNOR\0"
2269 /* 3861 */ "G_FFLOOR\0"
2270 /* 3870 */ "G_EXTRACT_SUBVECTOR\0"
2271 /* 3890 */ "G_INSERT_SUBVECTOR\0"
2272 /* 3909 */ "G_BUILD_VECTOR\0"
2273 /* 3924 */ "G_SHUFFLE_VECTOR\0"
2274 /* 3941 */ "G_SPLAT_VECTOR\0"
2275 /* 3956 */ "FXOR\0"
2276 /* 3961 */ "G_VECREDUCE_XOR\0"
2277 /* 3977 */ "G_XOR\0"
2278 /* 3983 */ "G_ATOMICRMW_XOR\0"
2279 /* 3999 */ "G_VECREDUCE_OR\0"
2280 /* 4014 */ "G_OR\0"
2281 /* 4019 */ "G_ATOMICRMW_OR\0"
2282 /* 4034 */ "BPR\0"
2283 /* 4038 */ "RDPR\0"
2284 /* 4043 */ "RDASR\0"
2285 /* 4049 */ "RDPSR\0"
2286 /* 4055 */ "G_ROTR\0"
2287 /* 4062 */ "G_INTTOPTR\0"
2288 /* 4073 */ "FSRC1S\0"
2289 /* 4080 */ "FANDNOT1S\0"
2290 /* 4090 */ "FNOT1S\0"
2291 /* 4097 */ "FORNOT1S\0"
2292 /* 4106 */ "FPSUB32S\0"
2293 /* 4115 */ "FPADD32S\0"
2294 /* 4124 */ "FSRC2S\0"
2295 /* 4131 */ "FANDNOT2S\0"
2296 /* 4141 */ "FNOT2S\0"
2297 /* 4148 */ "FORNOT2S\0"
2298 /* 4157 */ "FPSUB16S\0"
2299 /* 4166 */ "FPADD16S\0"
2300 /* 4175 */ "G_FABS\0"
2301 /* 4182 */ "G_ABS\0"
2302 /* 4188 */ "FSUBS\0"
2303 /* 4194 */ "FHSUBS\0"
2304 /* 4201 */ "FADDS\0"
2305 /* 4207 */ "FHADDS\0"
2306 /* 4214 */ "FNHADDS\0"
2307 /* 4222 */ "FNADDS\0"
2308 /* 4229 */ "FANDS\0"
2309 /* 4235 */ "FNANDS\0"
2310 /* 4242 */ "FONES\0"
2311 /* 4248 */ "V9FCMPES\0"
2312 /* 4257 */ "G_UNMERGE_VALUES\0"
2313 /* 4274 */ "G_MERGE_VALUES\0"
2314 /* 4289 */ "FNEGS\0"
2315 /* 4295 */ "FMULS\0"
2316 /* 4301 */ "FNMULS\0"
2317 /* 4308 */ "G_FACOS\0"
2318 /* 4316 */ "G_FCOS\0"
2319 /* 4323 */ "FZEROS\0"
2320 /* 4330 */ "FDTOS\0"
2321 /* 4336 */ "FITOS\0"
2322 /* 4342 */ "FQTOS\0"
2323 /* 4348 */ "MOVWTOS\0"
2324 /* 4356 */ "FXTOS\0"
2325 /* 4362 */ "V9FCMPS\0"
2326 /* 4370 */ "FLCMPS\0"
2327 /* 4377 */ "FORS\0"
2328 /* 4382 */ "FNORS\0"
2329 /* 4388 */ "FXNORS\0"
2330 /* 4395 */ "G_CONCAT_VECTORS\0"
2331 /* 4412 */ "FXORS\0"
2332 /* 4418 */ "FMOVRS\0"
2333 /* 4425 */ "COPY_TO_REGCLASS\0"
2334 /* 4442 */ "G_IS_FPCLASS\0"
2335 /* 4455 */ "FABSS\0"
2336 /* 4461 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
2337 /* 4491 */ "G_VECTOR_COMPRESS\0"
2338 /* 4509 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
2339 /* 4536 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
2340 /* 4574 */ "FSQRTS\0"
2341 /* 4581 */ "FDIVS\0"
2342 /* 4587 */ "FMOVS\0"
2343 /* 4593 */ "G_SSUBSAT\0"
2344 /* 4603 */ "G_USUBSAT\0"
2345 /* 4613 */ "G_SADDSAT\0"
2346 /* 4623 */ "G_UADDSAT\0"
2347 /* 4633 */ "G_SSHLSAT\0"
2348 /* 4643 */ "G_USHLSAT\0"
2349 /* 4653 */ "G_SMULFIXSAT\0"
2350 /* 4666 */ "G_UMULFIXSAT\0"
2351 /* 4679 */ "G_SDIVFIXSAT\0"
2352 /* 4692 */ "G_UDIVFIXSAT\0"
2353 /* 4705 */ "G_EXTRACT\0"
2354 /* 4715 */ "G_SELECT\0"
2355 /* 4724 */ "G_BRINDIRECT\0"
2356 /* 4737 */ "PATCHABLE_RET\0"
2357 /* 4751 */ "G_MEMSET\0"
2358 /* 4760 */ "PATCHABLE_FUNCTION_EXIT\0"
2359 /* 4784 */ "G_BRJT\0"
2360 /* 4791 */ "G_EXTRACT_VECTOR_ELT\0"
2361 /* 4812 */ "G_INSERT_VECTOR_ELT\0"
2362 /* 4832 */ "BPFCCANT\0"
2363 /* 4841 */ "BPICCANT\0"
2364 /* 4850 */ "BPXCCANT\0"
2365 /* 4859 */ "BPRANT\0"
2366 /* 4866 */ "G_FCONSTANT\0"
2367 /* 4878 */ "G_CONSTANT\0"
2368 /* 4889 */ "BPFCCNT\0"
2369 /* 4897 */ "BPICCNT\0"
2370 /* 4905 */ "BPXCCNT\0"
2371 /* 4913 */ "LZCNT\0"
2372 /* 4919 */ "G_INTRINSIC_CONVERGENT\0"
2373 /* 4942 */ "STATEPOINT\0"
2374 /* 4953 */ "PATCHPOINT\0"
2375 /* 4964 */ "G_PTRTOINT\0"
2376 /* 4975 */ "G_FRINT\0"
2377 /* 4983 */ "G_INTRINSIC_LLRINT\0"
2378 /* 5002 */ "G_INTRINSIC_LRINT\0"
2379 /* 5020 */ "G_FNEARBYINT\0"
2380 /* 5033 */ "BPRNT\0"
2381 /* 5039 */ "G_VASTART\0"
2382 /* 5049 */ "LIFETIME_START\0"
2383 /* 5064 */ "G_INVOKE_REGION_START\0"
2384 /* 5086 */ "G_INSERT\0"
2385 /* 5095 */ "G_FSQRT\0"
2386 /* 5103 */ "G_STRICT_FSQRT\0"
2387 /* 5118 */ "G_BITCAST\0"
2388 /* 5128 */ "G_ADDRSPACE_CAST\0"
2389 /* 5145 */ "PDIST\0"
2390 /* 5151 */ "DBG_VALUE_LIST\0"
2391 /* 5166 */ "G_FPEXT\0"
2392 /* 5174 */ "G_SEXT\0"
2393 /* 5181 */ "G_ASSERT_SEXT\0"
2394 /* 5195 */ "G_ANYEXT\0"
2395 /* 5204 */ "G_ZEXT\0"
2396 /* 5211 */ "G_ASSERT_ZEXT\0"
2397 /* 5225 */ "FMUL8X16AU\0"
2398 /* 5236 */ "G_FDIV\0"
2399 /* 5243 */ "G_STRICT_FDIV\0"
2400 /* 5257 */ "G_SDIV\0"
2401 /* 5264 */ "G_UDIV\0"
2402 /* 5271 */ "G_GET_FPENV\0"
2403 /* 5283 */ "G_RESET_FPENV\0"
2404 /* 5297 */ "G_SET_FPENV\0"
2405 /* 5309 */ "FLUSHW\0"
2406 /* 5316 */ "G_FPOW\0"
2407 /* 5323 */ "MOVSTOSW\0"
2408 /* 5332 */ "MOVSTOUW\0"
2409 /* 5341 */ "G_VECREDUCE_FMAX\0"
2410 /* 5358 */ "G_ATOMICRMW_FMAX\0"
2411 /* 5375 */ "G_VECREDUCE_SMAX\0"
2412 /* 5392 */ "G_SMAX\0"
2413 /* 5399 */ "G_VECREDUCE_UMAX\0"
2414 /* 5416 */ "G_UMAX\0"
2415 /* 5423 */ "G_ATOMICRMW_UMAX\0"
2416 /* 5440 */ "G_ATOMICRMW_MAX\0"
2417 /* 5456 */ "GETPCX\0"
2418 /* 5463 */ "G_FRAME_INDEX\0"
2419 /* 5477 */ "G_SBFX\0"
2420 /* 5484 */ "G_UBFX\0"
2421 /* 5491 */ "FPACKFIX\0"
2422 /* 5500 */ "G_SMULFIX\0"
2423 /* 5510 */ "G_UMULFIX\0"
2424 /* 5520 */ "G_SDIVFIX\0"
2425 /* 5530 */ "G_UDIVFIX\0"
2426 /* 5540 */ "XMULX\0"
2427 /* 5546 */ "FDTOX\0"
2428 /* 5552 */ "MOVDTOX\0"
2429 /* 5560 */ "FQTOX\0"
2430 /* 5566 */ "FSTOX\0"
2431 /* 5572 */ "SETX\0"
2432 /* 5577 */ "G_MEMCPY\0"
2433 /* 5586 */ "COPY\0"
2434 /* 5591 */ "RETRY\0"
2435 /* 5597 */ "CONVERGENCECTRL_ENTRY\0"
2436 /* 5619 */ "G_CTLZ\0"
2437 /* 5626 */ "G_CTTZ\0"
2438 /* 5633 */ "PREFETCHAi\0"
2439 /* 5644 */ "PREFETCHi\0"
2440 /* 5654 */ "SETHIi\0"
2441 /* 5661 */ "MEMBARi\0"
2442 /* 5669 */ "LDSBAri\0"
2443 /* 5677 */ "STBAri\0"
2444 /* 5684 */ "LDUBAri\0"
2445 /* 5692 */ "LDSTUBAri\0"
2446 /* 5702 */ "LDDAri\0"
2447 /* 5709 */ "LDAri\0"
2448 /* 5715 */ "STDAri\0"
2449 /* 5722 */ "LDDFAri\0"
2450 /* 5730 */ "LDFAri\0"
2451 /* 5737 */ "STDFAri\0"
2452 /* 5745 */ "LDQFAri\0"
2453 /* 5753 */ "STQFAri\0"
2454 /* 5761 */ "STFAri\0"
2455 /* 5768 */ "LDSHAri\0"
2456 /* 5776 */ "STHAri\0"
2457 /* 5783 */ "LDUHAri\0"
2458 /* 5791 */ "SWAPAri\0"
2459 /* 5799 */ "SRAri\0"
2460 /* 5805 */ "CASAri\0"
2461 /* 5812 */ "STAri\0"
2462 /* 5818 */ "LDSWAri\0"
2463 /* 5826 */ "LDXAri\0"
2464 /* 5833 */ "CASXAri\0"
2465 /* 5841 */ "STXAri\0"
2466 /* 5848 */ "LDSBri\0"
2467 /* 5855 */ "STBri\0"
2468 /* 5861 */ "LDUBri\0"
2469 /* 5868 */ "SUBri\0"
2470 /* 5874 */ "LDSTUBri\0"
2471 /* 5883 */ "SMACri\0"
2472 /* 5890 */ "UMACri\0"
2473 /* 5897 */ "SUBCri\0"
2474 /* 5904 */ "TSUBCCri\0"
2475 /* 5913 */ "TADDCCri\0"
2476 /* 5922 */ "ANDCCri\0"
2477 /* 5930 */ "V9MOVFCCri\0"
2478 /* 5941 */ "TICCri\0"
2479 /* 5948 */ "MOVICCri\0"
2480 /* 5957 */ "SMULCCri\0"
2481 /* 5966 */ "UMULCCri\0"
2482 /* 5975 */ "ANDNCCri\0"
2483 /* 5984 */ "ORNCCri\0"
2484 /* 5992 */ "XNORCCri\0"
2485 /* 6001 */ "XORCCri\0"
2486 /* 6009 */ "MULSCCri\0"
2487 /* 6018 */ "SDIVCCri\0"
2488 /* 6027 */ "UDIVCCri\0"
2489 /* 6036 */ "TXCCri\0"
2490 /* 6043 */ "MOVXCCri\0"
2491 /* 6052 */ "ADDCri\0"
2492 /* 6059 */ "LDDCri\0"
2493 /* 6066 */ "LDCri\0"
2494 /* 6072 */ "STDCri\0"
2495 /* 6079 */ "STCri\0"
2496 /* 6085 */ "ADDri\0"
2497 /* 6091 */ "LDDri\0"
2498 /* 6097 */ "LDri\0"
2499 /* 6102 */ "ANDri\0"
2500 /* 6108 */ "BINDri\0"
2501 /* 6115 */ "STDri\0"
2502 /* 6121 */ "SUBEri\0"
2503 /* 6128 */ "ADDEri\0"
2504 /* 6135 */ "RESTOREri\0"
2505 /* 6145 */ "SAVEri\0"
2506 /* 6152 */ "LDDFri\0"
2507 /* 6159 */ "LDFri\0"
2508 /* 6165 */ "STDFri\0"
2509 /* 6172 */ "LDQFri\0"
2510 /* 6179 */ "STQFri\0"
2511 /* 6186 */ "STFri\0"
2512 /* 6192 */ "LDSHri\0"
2513 /* 6199 */ "FLUSHri\0"
2514 /* 6207 */ "STHri\0"
2515 /* 6213 */ "LDUHri\0"
2516 /* 6220 */ "TAIL_CALLri\0"
2517 /* 6232 */ "SLLri\0"
2518 /* 6238 */ "JMPLri\0"
2519 /* 6245 */ "SRLri\0"
2520 /* 6251 */ "SMULri\0"
2521 /* 6258 */ "UMULri\0"
2522 /* 6265 */ "WRWIMri\0"
2523 /* 6273 */ "ANDNri\0"
2524 /* 6280 */ "ORNri\0"
2525 /* 6286 */ "TRAPri\0"
2526 /* 6293 */ "SWAPri\0"
2527 /* 6300 */ "STDCQri\0"
2528 /* 6308 */ "STDFQri\0"
2529 /* 6316 */ "WRTBRri\0"
2530 /* 6324 */ "XNORri\0"
2531 /* 6331 */ "XORri\0"
2532 /* 6337 */ "WRPRri\0"
2533 /* 6344 */ "WRASRri\0"
2534 /* 6352 */ "LDCSRri\0"
2535 /* 6360 */ "STCSRri\0"
2536 /* 6368 */ "LDFSRri\0"
2537 /* 6376 */ "STFSRri\0"
2538 /* 6384 */ "LDXFSRri\0"
2539 /* 6393 */ "STXFSRri\0"
2540 /* 6402 */ "PWRPSRri\0"
2541 /* 6411 */ "MOVRri\0"
2542 /* 6418 */ "STri\0"
2543 /* 6423 */ "RETTri\0"
2544 /* 6430 */ "SDIVri\0"
2545 /* 6437 */ "UDIVri\0"
2546 /* 6444 */ "TSUBCCTVri\0"
2547 /* 6455 */ "TADDCCTVri\0"
2548 /* 6466 */ "LDSWri\0"
2549 /* 6473 */ "SRAXri\0"
2550 /* 6480 */ "LDXri\0"
2551 /* 6486 */ "SLLXri\0"
2552 /* 6493 */ "SRLXri\0"
2553 /* 6500 */ "MULXri\0"
2554 /* 6507 */ "STXri\0"
2555 /* 6513 */ "SDIVXri\0"
2556 /* 6521 */ "UDIVXri\0"
2557 /* 6529 */ "PREFETCHAr\0"
2558 /* 6540 */ "PREFETCHr\0"
2559 /* 6550 */ "LDSBArr\0"
2560 /* 6558 */ "STBArr\0"
2561 /* 6565 */ "LDUBArr\0"
2562 /* 6573 */ "LDSTUBArr\0"
2563 /* 6583 */ "LDDArr\0"
2564 /* 6590 */ "LDArr\0"
2565 /* 6596 */ "STDArr\0"
2566 /* 6603 */ "LDDFArr\0"
2567 /* 6611 */ "LDFArr\0"
2568 /* 6618 */ "STDFArr\0"
2569 /* 6626 */ "LDQFArr\0"
2570 /* 6634 */ "STQFArr\0"
2571 /* 6642 */ "STFArr\0"
2572 /* 6649 */ "LDSHArr\0"
2573 /* 6657 */ "STHArr\0"
2574 /* 6664 */ "LDUHArr\0"
2575 /* 6672 */ "SWAPArr\0"
2576 /* 6680 */ "SRArr\0"
2577 /* 6686 */ "CASArr\0"
2578 /* 6693 */ "STArr\0"
2579 /* 6699 */ "LDSWArr\0"
2580 /* 6707 */ "LDXArr\0"
2581 /* 6714 */ "CASXArr\0"
2582 /* 6722 */ "STXArr\0"
2583 /* 6729 */ "LDSBrr\0"
2584 /* 6736 */ "STBrr\0"
2585 /* 6742 */ "LDUBrr\0"
2586 /* 6749 */ "SUBrr\0"
2587 /* 6755 */ "LDSTUBrr\0"
2588 /* 6764 */ "SMACrr\0"
2589 /* 6771 */ "UMACrr\0"
2590 /* 6778 */ "SUBCrr\0"
2591 /* 6785 */ "TSUBCCrr\0"
2592 /* 6794 */ "TADDCCrr\0"
2593 /* 6803 */ "ANDCCrr\0"
2594 /* 6811 */ "V9MOVFCCrr\0"
2595 /* 6822 */ "TICCrr\0"
2596 /* 6829 */ "MOVICCrr\0"
2597 /* 6838 */ "SMULCCrr\0"
2598 /* 6847 */ "UMULCCrr\0"
2599 /* 6856 */ "ANDNCCrr\0"
2600 /* 6865 */ "ORNCCrr\0"
2601 /* 6873 */ "XNORCCrr\0"
2602 /* 6882 */ "XORCCrr\0"
2603 /* 6890 */ "MULSCCrr\0"
2604 /* 6899 */ "SDIVCCrr\0"
2605 /* 6908 */ "UDIVCCrr\0"
2606 /* 6917 */ "TXCCrr\0"
2607 /* 6924 */ "MOVXCCrr\0"
2608 /* 6933 */ "ADDCrr\0"
2609 /* 6940 */ "LDDCrr\0"
2610 /* 6947 */ "LDCrr\0"
2611 /* 6953 */ "STDCrr\0"
2612 /* 6960 */ "POPCrr\0"
2613 /* 6967 */ "STCrr\0"
2614 /* 6973 */ "TLS_ADDrr\0"
2615 /* 6983 */ "LDDrr\0"
2616 /* 6989 */ "GDOP_LDrr\0"
2617 /* 6999 */ "TLS_LDrr\0"
2618 /* 7008 */ "ANDrr\0"
2619 /* 7014 */ "BINDrr\0"
2620 /* 7021 */ "STDrr\0"
2621 /* 7027 */ "SUBErr\0"
2622 /* 7034 */ "ADDErr\0"
2623 /* 7041 */ "RESTORErr\0"
2624 /* 7051 */ "SAVErr\0"
2625 /* 7058 */ "LDDFrr\0"
2626 /* 7065 */ "LDFrr\0"
2627 /* 7071 */ "STDFrr\0"
2628 /* 7078 */ "LDQFrr\0"
2629 /* 7085 */ "STQFrr\0"
2630 /* 7092 */ "STFrr\0"
2631 /* 7098 */ "LDSHrr\0"
2632 /* 7105 */ "FLUSHrr\0"
2633 /* 7113 */ "STHrr\0"
2634 /* 7119 */ "LDUHrr\0"
2635 /* 7126 */ "CALLrr\0"
2636 /* 7133 */ "SLLrr\0"
2637 /* 7139 */ "JMPLrr\0"
2638 /* 7146 */ "SRLrr\0"
2639 /* 7152 */ "SMULrr\0"
2640 /* 7159 */ "UMULrr\0"
2641 /* 7166 */ "WRWIMrr\0"
2642 /* 7174 */ "ANDNrr\0"
2643 /* 7181 */ "ORNrr\0"
2644 /* 7187 */ "TRAPrr\0"
2645 /* 7194 */ "SWAPrr\0"
2646 /* 7201 */ "STDCQrr\0"
2647 /* 7209 */ "STDFQrr\0"
2648 /* 7217 */ "WRTBRrr\0"
2649 /* 7225 */ "XNORrr\0"
2650 /* 7232 */ "XORrr\0"
2651 /* 7238 */ "WRPRrr\0"
2652 /* 7245 */ "WRASRrr\0"
2653 /* 7253 */ "LDCSRrr\0"
2654 /* 7261 */ "STCSRrr\0"
2655 /* 7269 */ "LDFSRrr\0"
2656 /* 7277 */ "STFSRrr\0"
2657 /* 7285 */ "LDXFSRrr\0"
2658 /* 7294 */ "STXFSRrr\0"
2659 /* 7303 */ "PWRPSRrr\0"
2660 /* 7312 */ "MOVRrr\0"
2661 /* 7319 */ "STrr\0"
2662 /* 7324 */ "RETTrr\0"
2663 /* 7331 */ "SDIVrr\0"
2664 /* 7338 */ "UDIVrr\0"
2665 /* 7345 */ "TSUBCCTVrr\0"
2666 /* 7356 */ "TADDCCTVrr\0"
2667 /* 7367 */ "LDSWrr\0"
2668 /* 7374 */ "SRAXrr\0"
2669 /* 7381 */ "GDOP_LDXrr\0"
2670 /* 7392 */ "TLS_LDXrr\0"
2671 /* 7402 */ "SLLXrr\0"
2672 /* 7409 */ "SRLXrr\0"
2673 /* 7416 */ "MULXrr\0"
2674 /* 7423 */ "STXrr\0"
2675 /* 7429 */ "SDIVXrr\0"
2676 /* 7437 */ "UDIVXrr\0"
2677};
2678#ifdef __GNUC__
2679#pragma GCC diagnostic pop
2680#endif
2681
2682extern const unsigned SparcInstrNameIndices[] = {
2683 2277U, 2757U, 3630U, 3094U, 2410U, 2391U, 2419U, 2566U,
2684 2094U, 2109U, 2060U, 2136U, 4425U, 1906U, 5151U, 2073U,
2685 2273U, 2400U, 1669U, 5586U, 1799U, 5049U, 1425U, 1620U,
2686 1657U, 3227U, 2554U, 4953U, 1571U, 3444U, 2199U, 4942U,
2687 1841U, 3417U, 3404U, 3701U, 4737U, 4760U, 2477U, 2533U,
2688 2506U, 2436U, 3666U, 3175U, 5597U, 3827U, 3375U, 1954U,
2689 5181U, 5211U, 2911U, 1233U, 590U, 2685U, 5257U, 5264U,
2690 2717U, 2724U, 2731U, 2741U, 1403U, 4014U, 3977U, 2058U,
2691 2275U, 5463U, 1916U, 1931U, 2571U, 4705U, 4257U, 5086U,
2692 4274U, 3909U, 995U, 4395U, 4964U, 4062U, 5118U, 1997U,
2693 3677U, 1498U, 969U, 1480U, 5002U, 4983U, 2889U, 3726U,
2694 3745U, 1121U, 1065U, 1095U, 1106U, 1046U, 1076U, 1885U,
2695 1869U, 4461U, 2150U, 2167U, 1249U, 596U, 1409U, 1362U,
2696 4019U, 3983U, 5440U, 3037U, 5423U, 3020U, 1200U, 573U,
2697 5358U, 2955U, 3289U, 3267U, 1649U, 2216U, 1452U, 4724U,
2698 5064U, 947U, 4509U, 4919U, 4536U, 5195U, 987U, 4878U,
2699 4866U, 5039U, 2191U, 5174U, 2123U, 5204U, 2463U, 3812U,
2700 3798U, 2456U, 3805U, 4055U, 2603U, 3344U, 3337U, 3351U,
2701 3358U, 4715U, 3167U, 1690U, 3151U, 1641U, 3159U, 1682U,
2702 3143U, 1633U, 3205U, 3197U, 2235U, 2227U, 4623U, 4613U,
2703 4603U, 4593U, 4643U, 4633U, 5500U, 5510U, 4653U, 4666U,
2704 5520U, 5530U, 4679U, 4692U, 1158U, 552U, 2627U, 516U,
2705 1039U, 5236U, 2696U, 5316U, 2333U, 3488U, 177U, 9U,
2706 2184U, 169U, 0U, 3463U, 3495U, 2087U, 5166U, 959U,
2707 2315U, 2324U, 3319U, 3328U, 4175U, 2926U, 4442U, 2006U,
2708 2831U, 2841U, 1739U, 1754U, 2788U, 2820U, 5271U, 5297U,
2709 5283U, 1698U, 1726U, 1711U, 1239U, 2347U, 2989U, 5392U,
2710 3013U, 5416U, 4182U, 1471U, 1461U, 3625U, 4784U, 1777U,
2711 3890U, 3870U, 4812U, 4791U, 3924U, 3941U, 4491U, 5626U,
2712 2040U, 5619U, 2022U, 3396U, 3311U, 1893U, 2469U, 4316U,
2713 3061U, 2882U, 4308U, 3053U, 2874U, 2259U, 2251U, 2243U,
2714 5095U, 3861U, 4975U, 5020U, 5128U, 3653U, 1786U, 1016U,
2715 1975U, 1854U, 1186U, 559U, 2655U, 5243U, 2703U, 522U,
2716 5103U, 3472U, 3765U, 3781U, 5577U, 1815U, 1987U, 4751U,
2717 3213U, 3260U, 3236U, 3248U, 1165U, 2634U, 1141U, 2610U,
2718 5341U, 2938U, 2799U, 2767U, 1217U, 2669U, 1387U, 3999U,
2719 3961U, 5375U, 2972U, 5399U, 2996U, 5477U, 5484U, 3117U,
2720 3429U, 5456U, 638U, 749U, 856U, 674U, 785U, 892U,
2721 715U, 822U, 929U, 656U, 767U, 874U, 4756U, 5572U,
2722 5914U, 6795U, 6052U, 6933U, 6128U, 7034U, 1033U, 612U,
2723 6085U, 6977U, 3643U, 2587U, 5922U, 6803U, 5975U, 6856U,
2724 6273U, 7174U, 6102U, 7008U, 400U, 155U, 421U, 476U,
2725 1439U, 501U, 6108U, 7014U, 2341U, 620U, 479U, 4832U,
2726 4889U, 733U, 486U, 4841U, 4897U, 4034U, 535U, 4859U,
2727 5033U, 840U, 493U, 4850U, 4905U, 1806U, 2492U, 6225U,
2728 7126U, 5805U, 6686U, 5833U, 6714U, 1438U, 500U, 280U,
2729 107U, 414U, 1831U, 247U, 2365U, 3077U, 2859U, 74U,
2730 2357U, 3068U, 2851U, 408U, 2373U, 3086U, 2867U, 1595U,
2731 3588U, 4455U, 1265U, 3510U, 4201U, 540U, 1351U, 28U,
2732 4080U, 185U, 4131U, 4229U, 1445U, 508U, 428U, 439U,
2733 302U, 1558U, 449U, 319U, 129U, 336U, 146U, 254U,
2734 81U, 263U, 90U, 3575U, 458U, 4364U, 467U, 1608U,
2735 3601U, 4581U, 3536U, 2297U, 3549U, 4330U, 5546U, 1379U,
2736 1271U, 4207U, 1134U, 4194U, 1524U, 3555U, 4336U, 1564U,
2737 4370U, 2267U, 5309U, 6199U, 7105U, 311U, 1614U, 628U,
2738 739U, 846U, 3607U, 693U, 802U, 909U, 1588U, 3581U,
2739 4418U, 4587U, 705U, 812U, 919U, 389U, 366U, 345U,
2740 2380U, 5225U, 1323U, 377U, 354U, 3543U, 4295U, 1286U,
2741 4222U, 1356U, 4235U, 1317U, 3530U, 4289U, 1278U, 4214U,
2742 1329U, 4301U, 3850U, 4382U, 37U, 4090U, 194U, 4141U,
2743 1343U, 1836U, 4242U, 3823U, 43U, 4097U, 200U, 4148U,
2744 4377U, 272U, 99U, 5491U, 239U, 4166U, 66U, 4115U,
2745 212U, 1769U, 231U, 4157U, 58U, 4106U, 1530U, 2303U,
2746 4342U, 5560U, 328U, 138U, 288U, 115U, 1336U, 1601U,
2747 3594U, 4574U, 224U, 51U, 22U, 4073U, 163U, 4124U,
2748 295U, 122U, 1536U, 2309U, 3561U, 5566U, 1128U, 3504U,
2749 4188U, 3855U, 4388U, 3956U, 4412U, 1542U, 3567U, 4356U,
2750 3221U, 4323U, 7381U, 6989U, 6238U, 7139U, 5709U, 6590U,
2751 6352U, 7253U, 6066U, 6947U, 5702U, 6583U, 6059U, 6940U,
2752 5722U, 6603U, 6152U, 7058U, 6091U, 6983U, 5730U, 6611U,
2753 6368U, 7269U, 6159U, 7065U, 5745U, 6626U, 6172U, 7078U,
2754 5669U, 6550U, 5848U, 6729U, 5768U, 6649U, 6192U, 7098U,
2755 5692U, 6573U, 5874U, 6755U, 5818U, 6699U, 6466U, 7367U,
2756 5684U, 6565U, 5861U, 6742U, 5783U, 6664U, 6213U, 7119U,
2757 5826U, 6707U, 6384U, 7285U, 6480U, 7386U, 6097U, 6994U,
2758 4913U, 5661U, 5552U, 5932U, 6813U, 5948U, 6829U, 6411U,
2759 7312U, 5323U, 5332U, 4348U, 6043U, 6924U, 1548U, 6009U,
2760 6890U, 6500U, 7416U, 3371U, 5994U, 6875U, 5984U, 6865U,
2761 6280U, 7181U, 6326U, 7227U, 5145U, 3110U, 6960U, 5633U,
2762 6529U, 5644U, 6540U, 6402U, 7303U, 4043U, 3525U, 4038U,
2763 4049U, 3619U, 2751U, 1302U, 6135U, 7041U, 4747U, 2598U,
2764 5591U, 6423U, 7324U, 1311U, 6145U, 7051U, 6018U, 6899U,
2765 6513U, 7429U, 6430U, 7331U, 5654U, 3134U, 2691U, 3819U,
2766 6486U, 7402U, 6232U, 7133U, 5883U, 6764U, 5957U, 6838U,
2767 6251U, 7152U, 6473U, 7374U, 5799U, 6680U, 6493U, 7409U,
2768 6245U, 7146U, 5812U, 6693U, 3613U, 5677U, 6558U, 5855U,
2769 6736U, 6360U, 7261U, 6079U, 6967U, 5715U, 6596U, 6300U,
2770 7201U, 6072U, 6953U, 5737U, 6618U, 6308U, 7209U, 6165U,
2771 7071U, 6115U, 7021U, 5761U, 6642U, 6376U, 7277U, 6186U,
2772 7092U, 5776U, 6657U, 6207U, 7113U, 5753U, 6634U, 6179U,
2773 7085U, 5841U, 6722U, 6393U, 7294U, 6507U, 7423U, 6418U,
2774 7319U, 5905U, 6786U, 5897U, 6778U, 6121U, 7027U, 5868U,
2775 6749U, 5791U, 6672U, 6293U, 7194U, 18U, 208U, 220U,
2776 6455U, 7356U, 5913U, 6794U, 2487U, 6220U, 5941U, 6822U,
2777 6973U, 2497U, 7392U, 6999U, 6286U, 7187U, 6444U, 7345U,
2778 5904U, 6785U, 6036U, 6917U, 6027U, 6908U, 6521U, 7437U,
2779 6437U, 7338U, 5890U, 6771U, 5966U, 6847U, 2281U, 6258U,
2780 7159U, 3365U, 1556U, 1293U, 3516U, 4248U, 3573U, 4362U,
2781 626U, 691U, 703U, 5930U, 6811U, 6344U, 7245U, 6337U,
2782 7238U, 6403U, 7304U, 6316U, 7217U, 6265U, 7166U, 5540U,
2783 2289U, 5992U, 6873U, 6324U, 7225U, 6001U, 6882U, 6331U,
2784 7232U,
2785};
2786
2787static inline void InitSparcMCInstrInfo(MCInstrInfo *II) {
2788 II->InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 809);
2789}
2790
2791} // end namespace llvm
2792#endif // GET_INSTRINFO_MC_DESC
2793
2794#ifdef GET_INSTRINFO_HEADER
2795#undef GET_INSTRINFO_HEADER
2796namespace llvm {
2797struct SparcGenInstrInfo : public TargetInstrInfo {
2798 explicit SparcGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2799 ~SparcGenInstrInfo() override = default;
2800
2801};
2802} // end namespace llvm
2803#endif // GET_INSTRINFO_HEADER
2804
2805#ifdef GET_INSTRINFO_HELPER_DECLS
2806#undef GET_INSTRINFO_HELPER_DECLS
2807
2808
2809#endif // GET_INSTRINFO_HELPER_DECLS
2810
2811#ifdef GET_INSTRINFO_HELPERS
2812#undef GET_INSTRINFO_HELPERS
2813
2814#endif // GET_INSTRINFO_HELPERS
2815
2816#ifdef GET_INSTRINFO_CTOR_DTOR
2817#undef GET_INSTRINFO_CTOR_DTOR
2818namespace llvm {
2819extern const SparcInstrTable SparcDescs;
2820extern const unsigned SparcInstrNameIndices[];
2821extern const char SparcInstrNameData[];
2822SparcGenInstrInfo::SparcGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2823 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2824 InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 809);
2825}
2826} // end namespace llvm
2827#endif // GET_INSTRINFO_CTOR_DTOR
2828
2829#ifdef GET_INSTRINFO_OPERAND_ENUM
2830#undef GET_INSTRINFO_OPERAND_ENUM
2831namespace llvm {
2832namespace SP {
2833namespace OpName {
2834enum {
2835 OPERAND_LAST
2836};
2837} // end namespace OpName
2838} // end namespace SP
2839} // end namespace llvm
2840#endif //GET_INSTRINFO_OPERAND_ENUM
2841
2842#ifdef GET_INSTRINFO_NAMED_OPS
2843#undef GET_INSTRINFO_NAMED_OPS
2844namespace llvm {
2845namespace SP {
2846LLVM_READONLY
2847int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
2848 return -1;
2849}
2850} // end namespace SP
2851} // end namespace llvm
2852#endif //GET_INSTRINFO_NAMED_OPS
2853
2854#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
2855#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
2856namespace llvm {
2857namespace SP {
2858namespace OpTypes {
2859enum OperandType {
2860 ASITag = 0,
2861 CCOp = 1,
2862 MEMri = 2,
2863 MEMrr = 3,
2864 MembarTag = 4,
2865 PrefetchTag = 5,
2866 RegCCOp = 6,
2867 TailRelocSymGOTLoad = 7,
2868 TailRelocSymTLSAdd = 8,
2869 TailRelocSymTLSCall = 9,
2870 TailRelocSymTLSLoad = 10,
2871 bprtarget = 11,
2872 bprtarget16 = 12,
2873 brtarget = 13,
2874 calltarget = 14,
2875 f32imm = 15,
2876 f64imm = 16,
2877 getPCX = 17,
2878 i1imm = 18,
2879 i8imm = 19,
2880 i16imm = 20,
2881 i32imm = 21,
2882 i64imm = 22,
2883 ptype0 = 23,
2884 ptype1 = 24,
2885 ptype2 = 25,
2886 ptype3 = 26,
2887 ptype4 = 27,
2888 ptype5 = 28,
2889 shift_imm5 = 29,
2890 shift_imm6 = 30,
2891 simm13Op = 31,
2892 type0 = 32,
2893 type1 = 33,
2894 type2 = 34,
2895 type3 = 35,
2896 type4 = 36,
2897 type5 = 37,
2898 untyped_imm_0 = 38,
2899 ASRRegs = 39,
2900 CoprocPair = 40,
2901 CoprocRegs = 41,
2902 DFPRegs = 42,
2903 FCCRegs = 43,
2904 FPRegs = 44,
2905 GPRIncomingArg = 45,
2906 GPROutgoingArg = 46,
2907 I64Regs = 47,
2908 IntPair = 48,
2909 IntRegs = 49,
2910 LowDFPRegs = 50,
2911 LowQFPRegs = 51,
2912 PRRegs = 52,
2913 QFPRegs = 53,
2914 OPERAND_TYPE_LIST_END
2915};
2916} // end namespace OpTypes
2917} // end namespace SP
2918} // end namespace llvm
2919#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
2920
2921#ifdef GET_INSTRINFO_OPERAND_TYPE
2922#undef GET_INSTRINFO_OPERAND_TYPE
2923namespace llvm {
2924namespace SP {
2925LLVM_READONLY
2926static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
2927 static const uint16_t Offsets[] = {
2928 /* PHI */
2929 0,
2930 /* INLINEASM */
2931 1,
2932 /* INLINEASM_BR */
2933 1,
2934 /* CFI_INSTRUCTION */
2935 1,
2936 /* EH_LABEL */
2937 2,
2938 /* GC_LABEL */
2939 3,
2940 /* ANNOTATION_LABEL */
2941 4,
2942 /* KILL */
2943 5,
2944 /* EXTRACT_SUBREG */
2945 5,
2946 /* INSERT_SUBREG */
2947 8,
2948 /* IMPLICIT_DEF */
2949 12,
2950 /* SUBREG_TO_REG */
2951 13,
2952 /* COPY_TO_REGCLASS */
2953 17,
2954 /* DBG_VALUE */
2955 20,
2956 /* DBG_VALUE_LIST */
2957 20,
2958 /* DBG_INSTR_REF */
2959 20,
2960 /* DBG_PHI */
2961 20,
2962 /* DBG_LABEL */
2963 20,
2964 /* REG_SEQUENCE */
2965 21,
2966 /* COPY */
2967 23,
2968 /* BUNDLE */
2969 25,
2970 /* LIFETIME_START */
2971 25,
2972 /* LIFETIME_END */
2973 26,
2974 /* PSEUDO_PROBE */
2975 27,
2976 /* ARITH_FENCE */
2977 31,
2978 /* STACKMAP */
2979 33,
2980 /* FENTRY_CALL */
2981 35,
2982 /* PATCHPOINT */
2983 35,
2984 /* LOAD_STACK_GUARD */
2985 41,
2986 /* PREALLOCATED_SETUP */
2987 42,
2988 /* PREALLOCATED_ARG */
2989 43,
2990 /* STATEPOINT */
2991 46,
2992 /* LOCAL_ESCAPE */
2993 46,
2994 /* FAULTING_OP */
2995 48,
2996 /* PATCHABLE_OP */
2997 49,
2998 /* PATCHABLE_FUNCTION_ENTER */
2999 49,
3000 /* PATCHABLE_RET */
3001 49,
3002 /* PATCHABLE_FUNCTION_EXIT */
3003 49,
3004 /* PATCHABLE_TAIL_CALL */
3005 49,
3006 /* PATCHABLE_EVENT_CALL */
3007 49,
3008 /* PATCHABLE_TYPED_EVENT_CALL */
3009 51,
3010 /* ICALL_BRANCH_FUNNEL */
3011 54,
3012 /* MEMBARRIER */
3013 54,
3014 /* JUMP_TABLE_DEBUG_INFO */
3015 54,
3016 /* CONVERGENCECTRL_ENTRY */
3017 55,
3018 /* CONVERGENCECTRL_ANCHOR */
3019 56,
3020 /* CONVERGENCECTRL_LOOP */
3021 57,
3022 /* CONVERGENCECTRL_GLUE */
3023 59,
3024 /* G_ASSERT_SEXT */
3025 60,
3026 /* G_ASSERT_ZEXT */
3027 63,
3028 /* G_ASSERT_ALIGN */
3029 66,
3030 /* G_ADD */
3031 69,
3032 /* G_SUB */
3033 72,
3034 /* G_MUL */
3035 75,
3036 /* G_SDIV */
3037 78,
3038 /* G_UDIV */
3039 81,
3040 /* G_SREM */
3041 84,
3042 /* G_UREM */
3043 87,
3044 /* G_SDIVREM */
3045 90,
3046 /* G_UDIVREM */
3047 94,
3048 /* G_AND */
3049 98,
3050 /* G_OR */
3051 101,
3052 /* G_XOR */
3053 104,
3054 /* G_IMPLICIT_DEF */
3055 107,
3056 /* G_PHI */
3057 108,
3058 /* G_FRAME_INDEX */
3059 109,
3060 /* G_GLOBAL_VALUE */
3061 111,
3062 /* G_PTRAUTH_GLOBAL_VALUE */
3063 113,
3064 /* G_CONSTANT_POOL */
3065 118,
3066 /* G_EXTRACT */
3067 120,
3068 /* G_UNMERGE_VALUES */
3069 123,
3070 /* G_INSERT */
3071 125,
3072 /* G_MERGE_VALUES */
3073 129,
3074 /* G_BUILD_VECTOR */
3075 131,
3076 /* G_BUILD_VECTOR_TRUNC */
3077 133,
3078 /* G_CONCAT_VECTORS */
3079 135,
3080 /* G_PTRTOINT */
3081 137,
3082 /* G_INTTOPTR */
3083 139,
3084 /* G_BITCAST */
3085 141,
3086 /* G_FREEZE */
3087 143,
3088 /* G_CONSTANT_FOLD_BARRIER */
3089 145,
3090 /* G_INTRINSIC_FPTRUNC_ROUND */
3091 147,
3092 /* G_INTRINSIC_TRUNC */
3093 150,
3094 /* G_INTRINSIC_ROUND */
3095 152,
3096 /* G_INTRINSIC_LRINT */
3097 154,
3098 /* G_INTRINSIC_LLRINT */
3099 156,
3100 /* G_INTRINSIC_ROUNDEVEN */
3101 158,
3102 /* G_READCYCLECOUNTER */
3103 160,
3104 /* G_READSTEADYCOUNTER */
3105 161,
3106 /* G_LOAD */
3107 162,
3108 /* G_SEXTLOAD */
3109 164,
3110 /* G_ZEXTLOAD */
3111 166,
3112 /* G_INDEXED_LOAD */
3113 168,
3114 /* G_INDEXED_SEXTLOAD */
3115 173,
3116 /* G_INDEXED_ZEXTLOAD */
3117 178,
3118 /* G_STORE */
3119 183,
3120 /* G_INDEXED_STORE */
3121 185,
3122 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
3123 190,
3124 /* G_ATOMIC_CMPXCHG */
3125 195,
3126 /* G_ATOMICRMW_XCHG */
3127 199,
3128 /* G_ATOMICRMW_ADD */
3129 202,
3130 /* G_ATOMICRMW_SUB */
3131 205,
3132 /* G_ATOMICRMW_AND */
3133 208,
3134 /* G_ATOMICRMW_NAND */
3135 211,
3136 /* G_ATOMICRMW_OR */
3137 214,
3138 /* G_ATOMICRMW_XOR */
3139 217,
3140 /* G_ATOMICRMW_MAX */
3141 220,
3142 /* G_ATOMICRMW_MIN */
3143 223,
3144 /* G_ATOMICRMW_UMAX */
3145 226,
3146 /* G_ATOMICRMW_UMIN */
3147 229,
3148 /* G_ATOMICRMW_FADD */
3149 232,
3150 /* G_ATOMICRMW_FSUB */
3151 235,
3152 /* G_ATOMICRMW_FMAX */
3153 238,
3154 /* G_ATOMICRMW_FMIN */
3155 241,
3156 /* G_ATOMICRMW_UINC_WRAP */
3157 244,
3158 /* G_ATOMICRMW_UDEC_WRAP */
3159 247,
3160 /* G_FENCE */
3161 250,
3162 /* G_PREFETCH */
3163 252,
3164 /* G_BRCOND */
3165 256,
3166 /* G_BRINDIRECT */
3167 258,
3168 /* G_INVOKE_REGION_START */
3169 259,
3170 /* G_INTRINSIC */
3171 259,
3172 /* G_INTRINSIC_W_SIDE_EFFECTS */
3173 260,
3174 /* G_INTRINSIC_CONVERGENT */
3175 261,
3176 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
3177 262,
3178 /* G_ANYEXT */
3179 263,
3180 /* G_TRUNC */
3181 265,
3182 /* G_CONSTANT */
3183 267,
3184 /* G_FCONSTANT */
3185 269,
3186 /* G_VASTART */
3187 271,
3188 /* G_VAARG */
3189 272,
3190 /* G_SEXT */
3191 275,
3192 /* G_SEXT_INREG */
3193 277,
3194 /* G_ZEXT */
3195 280,
3196 /* G_SHL */
3197 282,
3198 /* G_LSHR */
3199 285,
3200 /* G_ASHR */
3201 288,
3202 /* G_FSHL */
3203 291,
3204 /* G_FSHR */
3205 295,
3206 /* G_ROTR */
3207 299,
3208 /* G_ROTL */
3209 302,
3210 /* G_ICMP */
3211 305,
3212 /* G_FCMP */
3213 309,
3214 /* G_SCMP */
3215 313,
3216 /* G_UCMP */
3217 316,
3218 /* G_SELECT */
3219 319,
3220 /* G_UADDO */
3221 323,
3222 /* G_UADDE */
3223 327,
3224 /* G_USUBO */
3225 332,
3226 /* G_USUBE */
3227 336,
3228 /* G_SADDO */
3229 341,
3230 /* G_SADDE */
3231 345,
3232 /* G_SSUBO */
3233 350,
3234 /* G_SSUBE */
3235 354,
3236 /* G_UMULO */
3237 359,
3238 /* G_SMULO */
3239 363,
3240 /* G_UMULH */
3241 367,
3242 /* G_SMULH */
3243 370,
3244 /* G_UADDSAT */
3245 373,
3246 /* G_SADDSAT */
3247 376,
3248 /* G_USUBSAT */
3249 379,
3250 /* G_SSUBSAT */
3251 382,
3252 /* G_USHLSAT */
3253 385,
3254 /* G_SSHLSAT */
3255 388,
3256 /* G_SMULFIX */
3257 391,
3258 /* G_UMULFIX */
3259 395,
3260 /* G_SMULFIXSAT */
3261 399,
3262 /* G_UMULFIXSAT */
3263 403,
3264 /* G_SDIVFIX */
3265 407,
3266 /* G_UDIVFIX */
3267 411,
3268 /* G_SDIVFIXSAT */
3269 415,
3270 /* G_UDIVFIXSAT */
3271 419,
3272 /* G_FADD */
3273 423,
3274 /* G_FSUB */
3275 426,
3276 /* G_FMUL */
3277 429,
3278 /* G_FMA */
3279 432,
3280 /* G_FMAD */
3281 436,
3282 /* G_FDIV */
3283 440,
3284 /* G_FREM */
3285 443,
3286 /* G_FPOW */
3287 446,
3288 /* G_FPOWI */
3289 449,
3290 /* G_FEXP */
3291 452,
3292 /* G_FEXP2 */
3293 454,
3294 /* G_FEXP10 */
3295 456,
3296 /* G_FLOG */
3297 458,
3298 /* G_FLOG2 */
3299 460,
3300 /* G_FLOG10 */
3301 462,
3302 /* G_FLDEXP */
3303 464,
3304 /* G_FFREXP */
3305 467,
3306 /* G_FNEG */
3307 470,
3308 /* G_FPEXT */
3309 472,
3310 /* G_FPTRUNC */
3311 474,
3312 /* G_FPTOSI */
3313 476,
3314 /* G_FPTOUI */
3315 478,
3316 /* G_SITOFP */
3317 480,
3318 /* G_UITOFP */
3319 482,
3320 /* G_FABS */
3321 484,
3322 /* G_FCOPYSIGN */
3323 486,
3324 /* G_IS_FPCLASS */
3325 489,
3326 /* G_FCANONICALIZE */
3327 492,
3328 /* G_FMINNUM */
3329 494,
3330 /* G_FMAXNUM */
3331 497,
3332 /* G_FMINNUM_IEEE */
3333 500,
3334 /* G_FMAXNUM_IEEE */
3335 503,
3336 /* G_FMINIMUM */
3337 506,
3338 /* G_FMAXIMUM */
3339 509,
3340 /* G_GET_FPENV */
3341 512,
3342 /* G_SET_FPENV */
3343 513,
3344 /* G_RESET_FPENV */
3345 514,
3346 /* G_GET_FPMODE */
3347 514,
3348 /* G_SET_FPMODE */
3349 515,
3350 /* G_RESET_FPMODE */
3351 516,
3352 /* G_PTR_ADD */
3353 516,
3354 /* G_PTRMASK */
3355 519,
3356 /* G_SMIN */
3357 522,
3358 /* G_SMAX */
3359 525,
3360 /* G_UMIN */
3361 528,
3362 /* G_UMAX */
3363 531,
3364 /* G_ABS */
3365 534,
3366 /* G_LROUND */
3367 536,
3368 /* G_LLROUND */
3369 538,
3370 /* G_BR */
3371 540,
3372 /* G_BRJT */
3373 541,
3374 /* G_VSCALE */
3375 544,
3376 /* G_INSERT_SUBVECTOR */
3377 546,
3378 /* G_EXTRACT_SUBVECTOR */
3379 550,
3380 /* G_INSERT_VECTOR_ELT */
3381 553,
3382 /* G_EXTRACT_VECTOR_ELT */
3383 557,
3384 /* G_SHUFFLE_VECTOR */
3385 560,
3386 /* G_SPLAT_VECTOR */
3387 564,
3388 /* G_VECTOR_COMPRESS */
3389 566,
3390 /* G_CTTZ */
3391 570,
3392 /* G_CTTZ_ZERO_UNDEF */
3393 572,
3394 /* G_CTLZ */
3395 574,
3396 /* G_CTLZ_ZERO_UNDEF */
3397 576,
3398 /* G_CTPOP */
3399 578,
3400 /* G_BSWAP */
3401 580,
3402 /* G_BITREVERSE */
3403 582,
3404 /* G_FCEIL */
3405 584,
3406 /* G_FCOS */
3407 586,
3408 /* G_FSIN */
3409 588,
3410 /* G_FTAN */
3411 590,
3412 /* G_FACOS */
3413 592,
3414 /* G_FASIN */
3415 594,
3416 /* G_FATAN */
3417 596,
3418 /* G_FCOSH */
3419 598,
3420 /* G_FSINH */
3421 600,
3422 /* G_FTANH */
3423 602,
3424 /* G_FSQRT */
3425 604,
3426 /* G_FFLOOR */
3427 606,
3428 /* G_FRINT */
3429 608,
3430 /* G_FNEARBYINT */
3431 610,
3432 /* G_ADDRSPACE_CAST */
3433 612,
3434 /* G_BLOCK_ADDR */
3435 614,
3436 /* G_JUMP_TABLE */
3437 616,
3438 /* G_DYN_STACKALLOC */
3439 618,
3440 /* G_STACKSAVE */
3441 621,
3442 /* G_STACKRESTORE */
3443 622,
3444 /* G_STRICT_FADD */
3445 623,
3446 /* G_STRICT_FSUB */
3447 626,
3448 /* G_STRICT_FMUL */
3449 629,
3450 /* G_STRICT_FDIV */
3451 632,
3452 /* G_STRICT_FREM */
3453 635,
3454 /* G_STRICT_FMA */
3455 638,
3456 /* G_STRICT_FSQRT */
3457 642,
3458 /* G_STRICT_FLDEXP */
3459 644,
3460 /* G_READ_REGISTER */
3461 647,
3462 /* G_WRITE_REGISTER */
3463 649,
3464 /* G_MEMCPY */
3465 651,
3466 /* G_MEMCPY_INLINE */
3467 655,
3468 /* G_MEMMOVE */
3469 658,
3470 /* G_MEMSET */
3471 662,
3472 /* G_BZERO */
3473 666,
3474 /* G_TRAP */
3475 669,
3476 /* G_DEBUGTRAP */
3477 669,
3478 /* G_UBSANTRAP */
3479 669,
3480 /* G_VECREDUCE_SEQ_FADD */
3481 670,
3482 /* G_VECREDUCE_SEQ_FMUL */
3483 673,
3484 /* G_VECREDUCE_FADD */
3485 676,
3486 /* G_VECREDUCE_FMUL */
3487 678,
3488 /* G_VECREDUCE_FMAX */
3489 680,
3490 /* G_VECREDUCE_FMIN */
3491 682,
3492 /* G_VECREDUCE_FMAXIMUM */
3493 684,
3494 /* G_VECREDUCE_FMINIMUM */
3495 686,
3496 /* G_VECREDUCE_ADD */
3497 688,
3498 /* G_VECREDUCE_MUL */
3499 690,
3500 /* G_VECREDUCE_AND */
3501 692,
3502 /* G_VECREDUCE_OR */
3503 694,
3504 /* G_VECREDUCE_XOR */
3505 696,
3506 /* G_VECREDUCE_SMAX */
3507 698,
3508 /* G_VECREDUCE_SMIN */
3509 700,
3510 /* G_VECREDUCE_UMAX */
3511 702,
3512 /* G_VECREDUCE_UMIN */
3513 704,
3514 /* G_SBFX */
3515 706,
3516 /* G_UBFX */
3517 710,
3518 /* ADJCALLSTACKDOWN */
3519 714,
3520 /* ADJCALLSTACKUP */
3521 716,
3522 /* GETPCX */
3523 718,
3524 /* SELECT_CC_DFP_FCC */
3525 719,
3526 /* SELECT_CC_DFP_ICC */
3527 723,
3528 /* SELECT_CC_DFP_XCC */
3529 727,
3530 /* SELECT_CC_FP_FCC */
3531 731,
3532 /* SELECT_CC_FP_ICC */
3533 735,
3534 /* SELECT_CC_FP_XCC */
3535 739,
3536 /* SELECT_CC_Int_FCC */
3537 743,
3538 /* SELECT_CC_Int_ICC */
3539 747,
3540 /* SELECT_CC_Int_XCC */
3541 751,
3542 /* SELECT_CC_QFP_FCC */
3543 755,
3544 /* SELECT_CC_QFP_ICC */
3545 759,
3546 /* SELECT_CC_QFP_XCC */
3547 763,
3548 /* SET */
3549 767,
3550 /* SETX */
3551 769,
3552 /* ADDCCri */
3553 772,
3554 /* ADDCCrr */
3555 775,
3556 /* ADDCri */
3557 778,
3558 /* ADDCrr */
3559 781,
3560 /* ADDEri */
3561 784,
3562 /* ADDErr */
3563 787,
3564 /* ADDXC */
3565 790,
3566 /* ADDXCCC */
3567 793,
3568 /* ADDri */
3569 796,
3570 /* ADDrr */
3571 799,
3572 /* ALIGNADDR */
3573 802,
3574 /* ALIGNADDRL */
3575 805,
3576 /* ANDCCri */
3577 808,
3578 /* ANDCCrr */
3579 811,
3580 /* ANDNCCri */
3581 814,
3582 /* ANDNCCrr */
3583 817,
3584 /* ANDNri */
3585 820,
3586 /* ANDNrr */
3587 823,
3588 /* ANDri */
3589 826,
3590 /* ANDrr */
3591 829,
3592 /* ARRAY16 */
3593 832,
3594 /* ARRAY32 */
3595 835,
3596 /* ARRAY8 */
3597 838,
3598 /* BA */
3599 841,
3600 /* BCOND */
3601 842,
3602 /* BCONDA */
3603 844,
3604 /* BINDri */
3605 846,
3606 /* BINDrr */
3607 848,
3608 /* BMASK */
3609 850,
3610 /* BPFCC */
3611 853,
3612 /* BPFCCA */
3613 856,
3614 /* BPFCCANT */
3615 859,
3616 /* BPFCCNT */
3617 862,
3618 /* BPICC */
3619 865,
3620 /* BPICCA */
3621 867,
3622 /* BPICCANT */
3623 869,
3624 /* BPICCNT */
3625 871,
3626 /* BPR */
3627 873,
3628 /* BPRA */
3629 876,
3630 /* BPRANT */
3631 879,
3632 /* BPRNT */
3633 882,
3634 /* BPXCC */
3635 885,
3636 /* BPXCCA */
3637 887,
3638 /* BPXCCANT */
3639 889,
3640 /* BPXCCNT */
3641 891,
3642 /* BSHUFFLE */
3643 893,
3644 /* CALL */
3645 896,
3646 /* CALLri */
3647 897,
3648 /* CALLrr */
3649 899,
3650 /* CASAri */
3651 901,
3652 /* CASArr */
3653 905,
3654 /* CASXAri */
3655 910,
3656 /* CASXArr */
3657 914,
3658 /* CBCOND */
3659 919,
3660 /* CBCONDA */
3661 921,
3662 /* CMASK16 */
3663 923,
3664 /* CMASK32 */
3665 924,
3666 /* CMASK8 */
3667 925,
3668 /* DONE */
3669 926,
3670 /* EDGE16 */
3671 926,
3672 /* EDGE16L */
3673 929,
3674 /* EDGE16LN */
3675 932,
3676 /* EDGE16N */
3677 935,
3678 /* EDGE32 */
3679 938,
3680 /* EDGE32L */
3681 941,
3682 /* EDGE32LN */
3683 944,
3684 /* EDGE32N */
3685 947,
3686 /* EDGE8 */
3687 950,
3688 /* EDGE8L */
3689 953,
3690 /* EDGE8LN */
3691 956,
3692 /* EDGE8N */
3693 959,
3694 /* FABSD */
3695 962,
3696 /* FABSQ */
3697 964,
3698 /* FABSS */
3699 966,
3700 /* FADDD */
3701 968,
3702 /* FADDQ */
3703 971,
3704 /* FADDS */
3705 974,
3706 /* FALIGNADATA */
3707 977,
3708 /* FAND */
3709 980,
3710 /* FANDNOT1 */
3711 983,
3712 /* FANDNOT1S */
3713 986,
3714 /* FANDNOT2 */
3715 989,
3716 /* FANDNOT2S */
3717 992,
3718 /* FANDS */
3719 995,
3720 /* FBCOND */
3721 998,
3722 /* FBCONDA */
3723 1000,
3724 /* FBCONDA_V9 */
3725 1002,
3726 /* FBCOND_V9 */
3727 1004,
3728 /* FCHKSM16 */
3729 1006,
3730 /* FCMPD */
3731 1009,
3732 /* FCMPD_V9 */
3733 1011,
3734 /* FCMPEQ16 */
3735 1013,
3736 /* FCMPEQ32 */
3737 1016,
3738 /* FCMPGT16 */
3739 1019,
3740 /* FCMPGT32 */
3741 1022,
3742 /* FCMPLE16 */
3743 1025,
3744 /* FCMPLE32 */
3745 1028,
3746 /* FCMPNE16 */
3747 1031,
3748 /* FCMPNE32 */
3749 1034,
3750 /* FCMPQ */
3751 1037,
3752 /* FCMPQ_V9 */
3753 1039,
3754 /* FCMPS */
3755 1041,
3756 /* FCMPS_V9 */
3757 1043,
3758 /* FDIVD */
3759 1045,
3760 /* FDIVQ */
3761 1048,
3762 /* FDIVS */
3763 1051,
3764 /* FDMULQ */
3765 1054,
3766 /* FDTOI */
3767 1057,
3768 /* FDTOQ */
3769 1059,
3770 /* FDTOS */
3771 1061,
3772 /* FDTOX */
3773 1063,
3774 /* FEXPAND */
3775 1065,
3776 /* FHADDD */
3777 1067,
3778 /* FHADDS */
3779 1070,
3780 /* FHSUBD */
3781 1073,
3782 /* FHSUBS */
3783 1076,
3784 /* FITOD */
3785 1079,
3786 /* FITOQ */
3787 1081,
3788 /* FITOS */
3789 1083,
3790 /* FLCMPD */
3791 1085,
3792 /* FLCMPS */
3793 1088,
3794 /* FLUSH */
3795 1091,
3796 /* FLUSHW */
3797 1091,
3798 /* FLUSHri */
3799 1091,
3800 /* FLUSHrr */
3801 1093,
3802 /* FMEAN16 */
3803 1095,
3804 /* FMOVD */
3805 1098,
3806 /* FMOVD_FCC */
3807 1100,
3808 /* FMOVD_ICC */
3809 1104,
3810 /* FMOVD_XCC */
3811 1108,
3812 /* FMOVQ */
3813 1112,
3814 /* FMOVQ_FCC */
3815 1114,
3816 /* FMOVQ_ICC */
3817 1118,
3818 /* FMOVQ_XCC */
3819 1122,
3820 /* FMOVRD */
3821 1126,
3822 /* FMOVRQ */
3823 1131,
3824 /* FMOVRS */
3825 1136,
3826 /* FMOVS */
3827 1141,
3828 /* FMOVS_FCC */
3829 1143,
3830 /* FMOVS_ICC */
3831 1147,
3832 /* FMOVS_XCC */
3833 1151,
3834 /* FMUL8SUX16 */
3835 1155,
3836 /* FMUL8ULX16 */
3837 1158,
3838 /* FMUL8X16 */
3839 1161,
3840 /* FMUL8X16AL */
3841 1164,
3842 /* FMUL8X16AU */
3843 1167,
3844 /* FMULD */
3845 1170,
3846 /* FMULD8SUX16 */
3847 1173,
3848 /* FMULD8ULX16 */
3849 1176,
3850 /* FMULQ */
3851 1179,
3852 /* FMULS */
3853 1182,
3854 /* FNADDD */
3855 1185,
3856 /* FNADDS */
3857 1188,
3858 /* FNAND */
3859 1191,
3860 /* FNANDS */
3861 1194,
3862 /* FNEGD */
3863 1197,
3864 /* FNEGQ */
3865 1199,
3866 /* FNEGS */
3867 1201,
3868 /* FNHADDD */
3869 1203,
3870 /* FNHADDS */
3871 1206,
3872 /* FNMULD */
3873 1209,
3874 /* FNMULS */
3875 1212,
3876 /* FNOR */
3877 1215,
3878 /* FNORS */
3879 1218,
3880 /* FNOT1 */
3881 1221,
3882 /* FNOT1S */
3883 1223,
3884 /* FNOT2 */
3885 1225,
3886 /* FNOT2S */
3887 1227,
3888 /* FNSMULD */
3889 1229,
3890 /* FONE */
3891 1232,
3892 /* FONES */
3893 1234,
3894 /* FOR */
3895 1236,
3896 /* FORNOT1 */
3897 1239,
3898 /* FORNOT1S */
3899 1242,
3900 /* FORNOT2 */
3901 1245,
3902 /* FORNOT2S */
3903 1248,
3904 /* FORS */
3905 1251,
3906 /* FPACK16 */
3907 1254,
3908 /* FPACK32 */
3909 1256,
3910 /* FPACKFIX */
3911 1259,
3912 /* FPADD16 */
3913 1261,
3914 /* FPADD16S */
3915 1264,
3916 /* FPADD32 */
3917 1267,
3918 /* FPADD32S */
3919 1270,
3920 /* FPADD64 */
3921 1273,
3922 /* FPMERGE */
3923 1276,
3924 /* FPSUB16 */
3925 1279,
3926 /* FPSUB16S */
3927 1282,
3928 /* FPSUB32 */
3929 1285,
3930 /* FPSUB32S */
3931 1288,
3932 /* FQTOD */
3933 1291,
3934 /* FQTOI */
3935 1293,
3936 /* FQTOS */
3937 1295,
3938 /* FQTOX */
3939 1297,
3940 /* FSLAS16 */
3941 1299,
3942 /* FSLAS32 */
3943 1302,
3944 /* FSLL16 */
3945 1305,
3946 /* FSLL32 */
3947 1308,
3948 /* FSMULD */
3949 1311,
3950 /* FSQRTD */
3951 1314,
3952 /* FSQRTQ */
3953 1316,
3954 /* FSQRTS */
3955 1318,
3956 /* FSRA16 */
3957 1320,
3958 /* FSRA32 */
3959 1323,
3960 /* FSRC1 */
3961 1326,
3962 /* FSRC1S */
3963 1328,
3964 /* FSRC2 */
3965 1330,
3966 /* FSRC2S */
3967 1332,
3968 /* FSRL16 */
3969 1334,
3970 /* FSRL32 */
3971 1337,
3972 /* FSTOD */
3973 1340,
3974 /* FSTOI */
3975 1342,
3976 /* FSTOQ */
3977 1344,
3978 /* FSTOX */
3979 1346,
3980 /* FSUBD */
3981 1348,
3982 /* FSUBQ */
3983 1351,
3984 /* FSUBS */
3985 1354,
3986 /* FXNOR */
3987 1357,
3988 /* FXNORS */
3989 1360,
3990 /* FXOR */
3991 1363,
3992 /* FXORS */
3993 1366,
3994 /* FXTOD */
3995 1369,
3996 /* FXTOQ */
3997 1371,
3998 /* FXTOS */
3999 1373,
4000 /* FZERO */
4001 1375,
4002 /* FZEROS */
4003 1377,
4004 /* GDOP_LDXrr */
4005 1379,
4006 /* GDOP_LDrr */
4007 1383,
4008 /* JMPLri */
4009 1387,
4010 /* JMPLrr */
4011 1390,
4012 /* LDAri */
4013 1393,
4014 /* LDArr */
4015 1396,
4016 /* LDCSRri */
4017 1400,
4018 /* LDCSRrr */
4019 1402,
4020 /* LDCri */
4021 1404,
4022 /* LDCrr */
4023 1407,
4024 /* LDDAri */
4025 1410,
4026 /* LDDArr */
4027 1413,
4028 /* LDDCri */
4029 1417,
4030 /* LDDCrr */
4031 1420,
4032 /* LDDFAri */
4033 1423,
4034 /* LDDFArr */
4035 1426,
4036 /* LDDFri */
4037 1430,
4038 /* LDDFrr */
4039 1433,
4040 /* LDDri */
4041 1436,
4042 /* LDDrr */
4043 1439,
4044 /* LDFAri */
4045 1442,
4046 /* LDFArr */
4047 1445,
4048 /* LDFSRri */
4049 1449,
4050 /* LDFSRrr */
4051 1451,
4052 /* LDFri */
4053 1453,
4054 /* LDFrr */
4055 1456,
4056 /* LDQFAri */
4057 1459,
4058 /* LDQFArr */
4059 1462,
4060 /* LDQFri */
4061 1466,
4062 /* LDQFrr */
4063 1469,
4064 /* LDSBAri */
4065 1472,
4066 /* LDSBArr */
4067 1475,
4068 /* LDSBri */
4069 1479,
4070 /* LDSBrr */
4071 1482,
4072 /* LDSHAri */
4073 1485,
4074 /* LDSHArr */
4075 1488,
4076 /* LDSHri */
4077 1492,
4078 /* LDSHrr */
4079 1495,
4080 /* LDSTUBAri */
4081 1498,
4082 /* LDSTUBArr */
4083 1501,
4084 /* LDSTUBri */
4085 1505,
4086 /* LDSTUBrr */
4087 1508,
4088 /* LDSWAri */
4089 1511,
4090 /* LDSWArr */
4091 1514,
4092 /* LDSWri */
4093 1518,
4094 /* LDSWrr */
4095 1521,
4096 /* LDUBAri */
4097 1524,
4098 /* LDUBArr */
4099 1527,
4100 /* LDUBri */
4101 1531,
4102 /* LDUBrr */
4103 1534,
4104 /* LDUHAri */
4105 1537,
4106 /* LDUHArr */
4107 1540,
4108 /* LDUHri */
4109 1544,
4110 /* LDUHrr */
4111 1547,
4112 /* LDXAri */
4113 1550,
4114 /* LDXArr */
4115 1553,
4116 /* LDXFSRri */
4117 1557,
4118 /* LDXFSRrr */
4119 1559,
4120 /* LDXri */
4121 1561,
4122 /* LDXrr */
4123 1564,
4124 /* LDri */
4125 1567,
4126 /* LDrr */
4127 1570,
4128 /* LZCNT */
4129 1573,
4130 /* MEMBARi */
4131 1575,
4132 /* MOVDTOX */
4133 1576,
4134 /* MOVFCCri */
4135 1578,
4136 /* MOVFCCrr */
4137 1582,
4138 /* MOVICCri */
4139 1586,
4140 /* MOVICCrr */
4141 1590,
4142 /* MOVRri */
4143 1594,
4144 /* MOVRrr */
4145 1599,
4146 /* MOVSTOSW */
4147 1604,
4148 /* MOVSTOUW */
4149 1606,
4150 /* MOVWTOS */
4151 1608,
4152 /* MOVXCCri */
4153 1610,
4154 /* MOVXCCrr */
4155 1614,
4156 /* MOVXTOD */
4157 1618,
4158 /* MULSCCri */
4159 1620,
4160 /* MULSCCrr */
4161 1623,
4162 /* MULXri */
4163 1626,
4164 /* MULXrr */
4165 1629,
4166 /* NOP */
4167 1632,
4168 /* ORCCri */
4169 1632,
4170 /* ORCCrr */
4171 1635,
4172 /* ORNCCri */
4173 1638,
4174 /* ORNCCrr */
4175 1641,
4176 /* ORNri */
4177 1644,
4178 /* ORNrr */
4179 1647,
4180 /* ORri */
4181 1650,
4182 /* ORrr */
4183 1653,
4184 /* PDIST */
4185 1656,
4186 /* PDISTN */
4187 1659,
4188 /* POPCrr */
4189 1662,
4190 /* PREFETCHAi */
4191 1664,
4192 /* PREFETCHAr */
4193 1667,
4194 /* PREFETCHi */
4195 1671,
4196 /* PREFETCHr */
4197 1674,
4198 /* PWRPSRri */
4199 1677,
4200 /* PWRPSRrr */
4201 1679,
4202 /* RDASR */
4203 1681,
4204 /* RDFQ */
4205 1683,
4206 /* RDPR */
4207 1684,
4208 /* RDPSR */
4209 1686,
4210 /* RDTBR */
4211 1687,
4212 /* RDWIM */
4213 1688,
4214 /* RESTORED */
4215 1689,
4216 /* RESTOREri */
4217 1689,
4218 /* RESTORErr */
4219 1692,
4220 /* RET */
4221 1695,
4222 /* RETL */
4223 1696,
4224 /* RETRY */
4225 1697,
4226 /* RETTri */
4227 1697,
4228 /* RETTrr */
4229 1699,
4230 /* SAVED */
4231 1701,
4232 /* SAVEri */
4233 1701,
4234 /* SAVErr */
4235 1704,
4236 /* SDIVCCri */
4237 1707,
4238 /* SDIVCCrr */
4239 1710,
4240 /* SDIVXri */
4241 1713,
4242 /* SDIVXrr */
4243 1716,
4244 /* SDIVri */
4245 1719,
4246 /* SDIVrr */
4247 1722,
4248 /* SETHIi */
4249 1725,
4250 /* SHUTDOWN */
4251 1727,
4252 /* SIAM */
4253 1727,
4254 /* SIR */
4255 1727,
4256 /* SLLXri */
4257 1728,
4258 /* SLLXrr */
4259 1731,
4260 /* SLLri */
4261 1734,
4262 /* SLLrr */
4263 1737,
4264 /* SMACri */
4265 1740,
4266 /* SMACrr */
4267 1744,
4268 /* SMULCCri */
4269 1748,
4270 /* SMULCCrr */
4271 1751,
4272 /* SMULri */
4273 1754,
4274 /* SMULrr */
4275 1757,
4276 /* SRAXri */
4277 1760,
4278 /* SRAXrr */
4279 1763,
4280 /* SRAri */
4281 1766,
4282 /* SRArr */
4283 1769,
4284 /* SRLXri */
4285 1772,
4286 /* SRLXrr */
4287 1775,
4288 /* SRLri */
4289 1778,
4290 /* SRLrr */
4291 1781,
4292 /* STAri */
4293 1784,
4294 /* STArr */
4295 1787,
4296 /* STBAR */
4297 1791,
4298 /* STBAri */
4299 1791,
4300 /* STBArr */
4301 1794,
4302 /* STBri */
4303 1798,
4304 /* STBrr */
4305 1801,
4306 /* STCSRri */
4307 1804,
4308 /* STCSRrr */
4309 1806,
4310 /* STCri */
4311 1808,
4312 /* STCrr */
4313 1811,
4314 /* STDAri */
4315 1814,
4316 /* STDArr */
4317 1817,
4318 /* STDCQri */
4319 1821,
4320 /* STDCQrr */
4321 1823,
4322 /* STDCri */
4323 1825,
4324 /* STDCrr */
4325 1828,
4326 /* STDFAri */
4327 1831,
4328 /* STDFArr */
4329 1834,
4330 /* STDFQri */
4331 1838,
4332 /* STDFQrr */
4333 1840,
4334 /* STDFri */
4335 1842,
4336 /* STDFrr */
4337 1845,
4338 /* STDri */
4339 1848,
4340 /* STDrr */
4341 1851,
4342 /* STFAri */
4343 1854,
4344 /* STFArr */
4345 1857,
4346 /* STFSRri */
4347 1861,
4348 /* STFSRrr */
4349 1863,
4350 /* STFri */
4351 1865,
4352 /* STFrr */
4353 1868,
4354 /* STHAri */
4355 1871,
4356 /* STHArr */
4357 1874,
4358 /* STHri */
4359 1878,
4360 /* STHrr */
4361 1881,
4362 /* STQFAri */
4363 1884,
4364 /* STQFArr */
4365 1887,
4366 /* STQFri */
4367 1891,
4368 /* STQFrr */
4369 1894,
4370 /* STXAri */
4371 1897,
4372 /* STXArr */
4373 1900,
4374 /* STXFSRri */
4375 1904,
4376 /* STXFSRrr */
4377 1906,
4378 /* STXri */
4379 1908,
4380 /* STXrr */
4381 1911,
4382 /* STri */
4383 1914,
4384 /* STrr */
4385 1917,
4386 /* SUBCCri */
4387 1920,
4388 /* SUBCCrr */
4389 1923,
4390 /* SUBCri */
4391 1926,
4392 /* SUBCrr */
4393 1929,
4394 /* SUBEri */
4395 1932,
4396 /* SUBErr */
4397 1935,
4398 /* SUBri */
4399 1938,
4400 /* SUBrr */
4401 1941,
4402 /* SWAPAri */
4403 1944,
4404 /* SWAPArr */
4405 1948,
4406 /* SWAPri */
4407 1953,
4408 /* SWAPrr */
4409 1957,
4410 /* TA1 */
4411 1961,
4412 /* TA3 */
4413 1961,
4414 /* TA5 */
4415 1961,
4416 /* TADDCCTVri */
4417 1961,
4418 /* TADDCCTVrr */
4419 1964,
4420 /* TADDCCri */
4421 1967,
4422 /* TADDCCrr */
4423 1970,
4424 /* TAIL_CALL */
4425 1973,
4426 /* TAIL_CALLri */
4427 1974,
4428 /* TICCri */
4429 1976,
4430 /* TICCrr */
4431 1979,
4432 /* TLS_ADDrr */
4433 1982,
4434 /* TLS_CALL */
4435 1986,
4436 /* TLS_LDXrr */
4437 1988,
4438 /* TLS_LDrr */
4439 1992,
4440 /* TRAPri */
4441 1996,
4442 /* TRAPrr */
4443 1999,
4444 /* TSUBCCTVri */
4445 2002,
4446 /* TSUBCCTVrr */
4447 2005,
4448 /* TSUBCCri */
4449 2008,
4450 /* TSUBCCrr */
4451 2011,
4452 /* TXCCri */
4453 2014,
4454 /* TXCCrr */
4455 2017,
4456 /* UDIVCCri */
4457 2020,
4458 /* UDIVCCrr */
4459 2023,
4460 /* UDIVXri */
4461 2026,
4462 /* UDIVXrr */
4463 2029,
4464 /* UDIVri */
4465 2032,
4466 /* UDIVrr */
4467 2035,
4468 /* UMACri */
4469 2038,
4470 /* UMACrr */
4471 2042,
4472 /* UMULCCri */
4473 2046,
4474 /* UMULCCrr */
4475 2049,
4476 /* UMULXHI */
4477 2052,
4478 /* UMULri */
4479 2055,
4480 /* UMULrr */
4481 2058,
4482 /* UNIMP */
4483 2061,
4484 /* V9FCMPD */
4485 2062,
4486 /* V9FCMPED */
4487 2065,
4488 /* V9FCMPEQ */
4489 2068,
4490 /* V9FCMPES */
4491 2071,
4492 /* V9FCMPQ */
4493 2074,
4494 /* V9FCMPS */
4495 2077,
4496 /* V9FMOVD_FCC */
4497 2080,
4498 /* V9FMOVQ_FCC */
4499 2085,
4500 /* V9FMOVS_FCC */
4501 2090,
4502 /* V9MOVFCCri */
4503 2095,
4504 /* V9MOVFCCrr */
4505 2100,
4506 /* WRASRri */
4507 2105,
4508 /* WRASRrr */
4509 2108,
4510 /* WRPRri */
4511 2111,
4512 /* WRPRrr */
4513 2114,
4514 /* WRPSRri */
4515 2117,
4516 /* WRPSRrr */
4517 2119,
4518 /* WRTBRri */
4519 2121,
4520 /* WRTBRrr */
4521 2123,
4522 /* WRWIMri */
4523 2125,
4524 /* WRWIMrr */
4525 2127,
4526 /* XMULX */
4527 2129,
4528 /* XMULXHI */
4529 2132,
4530 /* XNORCCri */
4531 2135,
4532 /* XNORCCrr */
4533 2138,
4534 /* XNORri */
4535 2141,
4536 /* XNORrr */
4537 2144,
4538 /* XORCCri */
4539 2147,
4540 /* XORCCrr */
4541 2150,
4542 /* XORri */
4543 2153,
4544 /* XORrr */
4545 2156,
4546 };
4547
4548 using namespace OpTypes;
4549 static const int8_t OpcodeOperandTypes[] = {
4550
4551 /* PHI */
4552 -1,
4553 /* INLINEASM */
4554 /* INLINEASM_BR */
4555 /* CFI_INSTRUCTION */
4556 i32imm,
4557 /* EH_LABEL */
4558 i32imm,
4559 /* GC_LABEL */
4560 i32imm,
4561 /* ANNOTATION_LABEL */
4562 i32imm,
4563 /* KILL */
4564 /* EXTRACT_SUBREG */
4565 -1, -1, i32imm,
4566 /* INSERT_SUBREG */
4567 -1, -1, -1, i32imm,
4568 /* IMPLICIT_DEF */
4569 -1,
4570 /* SUBREG_TO_REG */
4571 -1, -1, -1, i32imm,
4572 /* COPY_TO_REGCLASS */
4573 -1, -1, i32imm,
4574 /* DBG_VALUE */
4575 /* DBG_VALUE_LIST */
4576 /* DBG_INSTR_REF */
4577 /* DBG_PHI */
4578 /* DBG_LABEL */
4579 -1,
4580 /* REG_SEQUENCE */
4581 -1, -1,
4582 /* COPY */
4583 -1, -1,
4584 /* BUNDLE */
4585 /* LIFETIME_START */
4586 i32imm,
4587 /* LIFETIME_END */
4588 i32imm,
4589 /* PSEUDO_PROBE */
4590 i64imm, i64imm, i8imm, i32imm,
4591 /* ARITH_FENCE */
4592 -1, -1,
4593 /* STACKMAP */
4594 i64imm, i32imm,
4595 /* FENTRY_CALL */
4596 /* PATCHPOINT */
4597 -1, i64imm, i32imm, -1, i32imm, i32imm,
4598 /* LOAD_STACK_GUARD */
4599 -1,
4600 /* PREALLOCATED_SETUP */
4601 i32imm,
4602 /* PREALLOCATED_ARG */
4603 -1, i32imm, i32imm,
4604 /* STATEPOINT */
4605 /* LOCAL_ESCAPE */
4606 -1, i32imm,
4607 /* FAULTING_OP */
4608 -1,
4609 /* PATCHABLE_OP */
4610 /* PATCHABLE_FUNCTION_ENTER */
4611 /* PATCHABLE_RET */
4612 /* PATCHABLE_FUNCTION_EXIT */
4613 /* PATCHABLE_TAIL_CALL */
4614 /* PATCHABLE_EVENT_CALL */
4615 -1, -1,
4616 /* PATCHABLE_TYPED_EVENT_CALL */
4617 -1, -1, -1,
4618 /* ICALL_BRANCH_FUNNEL */
4619 /* MEMBARRIER */
4620 /* JUMP_TABLE_DEBUG_INFO */
4621 i64imm,
4622 /* CONVERGENCECTRL_ENTRY */
4623 -1,
4624 /* CONVERGENCECTRL_ANCHOR */
4625 -1,
4626 /* CONVERGENCECTRL_LOOP */
4627 -1, -1,
4628 /* CONVERGENCECTRL_GLUE */
4629 -1,
4630 /* G_ASSERT_SEXT */
4631 type0, type0, untyped_imm_0,
4632 /* G_ASSERT_ZEXT */
4633 type0, type0, untyped_imm_0,
4634 /* G_ASSERT_ALIGN */
4635 type0, type0, untyped_imm_0,
4636 /* G_ADD */
4637 type0, type0, type0,
4638 /* G_SUB */
4639 type0, type0, type0,
4640 /* G_MUL */
4641 type0, type0, type0,
4642 /* G_SDIV */
4643 type0, type0, type0,
4644 /* G_UDIV */
4645 type0, type0, type0,
4646 /* G_SREM */
4647 type0, type0, type0,
4648 /* G_UREM */
4649 type0, type0, type0,
4650 /* G_SDIVREM */
4651 type0, type0, type0, type0,
4652 /* G_UDIVREM */
4653 type0, type0, type0, type0,
4654 /* G_AND */
4655 type0, type0, type0,
4656 /* G_OR */
4657 type0, type0, type0,
4658 /* G_XOR */
4659 type0, type0, type0,
4660 /* G_IMPLICIT_DEF */
4661 type0,
4662 /* G_PHI */
4663 type0,
4664 /* G_FRAME_INDEX */
4665 type0, -1,
4666 /* G_GLOBAL_VALUE */
4667 type0, -1,
4668 /* G_PTRAUTH_GLOBAL_VALUE */
4669 type0, -1, i32imm, type1, i64imm,
4670 /* G_CONSTANT_POOL */
4671 type0, -1,
4672 /* G_EXTRACT */
4673 type0, type1, untyped_imm_0,
4674 /* G_UNMERGE_VALUES */
4675 type0, type1,
4676 /* G_INSERT */
4677 type0, type0, type1, untyped_imm_0,
4678 /* G_MERGE_VALUES */
4679 type0, type1,
4680 /* G_BUILD_VECTOR */
4681 type0, type1,
4682 /* G_BUILD_VECTOR_TRUNC */
4683 type0, type1,
4684 /* G_CONCAT_VECTORS */
4685 type0, type1,
4686 /* G_PTRTOINT */
4687 type0, type1,
4688 /* G_INTTOPTR */
4689 type0, type1,
4690 /* G_BITCAST */
4691 type0, type1,
4692 /* G_FREEZE */
4693 type0, type0,
4694 /* G_CONSTANT_FOLD_BARRIER */
4695 type0, type0,
4696 /* G_INTRINSIC_FPTRUNC_ROUND */
4697 type0, type1, i32imm,
4698 /* G_INTRINSIC_TRUNC */
4699 type0, type0,
4700 /* G_INTRINSIC_ROUND */
4701 type0, type0,
4702 /* G_INTRINSIC_LRINT */
4703 type0, type1,
4704 /* G_INTRINSIC_LLRINT */
4705 type0, type1,
4706 /* G_INTRINSIC_ROUNDEVEN */
4707 type0, type0,
4708 /* G_READCYCLECOUNTER */
4709 type0,
4710 /* G_READSTEADYCOUNTER */
4711 type0,
4712 /* G_LOAD */
4713 type0, ptype1,
4714 /* G_SEXTLOAD */
4715 type0, ptype1,
4716 /* G_ZEXTLOAD */
4717 type0, ptype1,
4718 /* G_INDEXED_LOAD */
4719 type0, ptype1, ptype1, type2, -1,
4720 /* G_INDEXED_SEXTLOAD */
4721 type0, ptype1, ptype1, type2, -1,
4722 /* G_INDEXED_ZEXTLOAD */
4723 type0, ptype1, ptype1, type2, -1,
4724 /* G_STORE */
4725 type0, ptype1,
4726 /* G_INDEXED_STORE */
4727 ptype0, type1, ptype0, ptype2, -1,
4728 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
4729 type0, type1, type2, type0, type0,
4730 /* G_ATOMIC_CMPXCHG */
4731 type0, ptype1, type0, type0,
4732 /* G_ATOMICRMW_XCHG */
4733 type0, ptype1, type0,
4734 /* G_ATOMICRMW_ADD */
4735 type0, ptype1, type0,
4736 /* G_ATOMICRMW_SUB */
4737 type0, ptype1, type0,
4738 /* G_ATOMICRMW_AND */
4739 type0, ptype1, type0,
4740 /* G_ATOMICRMW_NAND */
4741 type0, ptype1, type0,
4742 /* G_ATOMICRMW_OR */
4743 type0, ptype1, type0,
4744 /* G_ATOMICRMW_XOR */
4745 type0, ptype1, type0,
4746 /* G_ATOMICRMW_MAX */
4747 type0, ptype1, type0,
4748 /* G_ATOMICRMW_MIN */
4749 type0, ptype1, type0,
4750 /* G_ATOMICRMW_UMAX */
4751 type0, ptype1, type0,
4752 /* G_ATOMICRMW_UMIN */
4753 type0, ptype1, type0,
4754 /* G_ATOMICRMW_FADD */
4755 type0, ptype1, type0,
4756 /* G_ATOMICRMW_FSUB */
4757 type0, ptype1, type0,
4758 /* G_ATOMICRMW_FMAX */
4759 type0, ptype1, type0,
4760 /* G_ATOMICRMW_FMIN */
4761 type0, ptype1, type0,
4762 /* G_ATOMICRMW_UINC_WRAP */
4763 type0, ptype1, type0,
4764 /* G_ATOMICRMW_UDEC_WRAP */
4765 type0, ptype1, type0,
4766 /* G_FENCE */
4767 i32imm, i32imm,
4768 /* G_PREFETCH */
4769 ptype0, i32imm, i32imm, i32imm,
4770 /* G_BRCOND */
4771 type0, -1,
4772 /* G_BRINDIRECT */
4773 type0,
4774 /* G_INVOKE_REGION_START */
4775 /* G_INTRINSIC */
4776 -1,
4777 /* G_INTRINSIC_W_SIDE_EFFECTS */
4778 -1,
4779 /* G_INTRINSIC_CONVERGENT */
4780 -1,
4781 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
4782 -1,
4783 /* G_ANYEXT */
4784 type0, type1,
4785 /* G_TRUNC */
4786 type0, type1,
4787 /* G_CONSTANT */
4788 type0, -1,
4789 /* G_FCONSTANT */
4790 type0, -1,
4791 /* G_VASTART */
4792 type0,
4793 /* G_VAARG */
4794 type0, type1, -1,
4795 /* G_SEXT */
4796 type0, type1,
4797 /* G_SEXT_INREG */
4798 type0, type0, untyped_imm_0,
4799 /* G_ZEXT */
4800 type0, type1,
4801 /* G_SHL */
4802 type0, type0, type1,
4803 /* G_LSHR */
4804 type0, type0, type1,
4805 /* G_ASHR */
4806 type0, type0, type1,
4807 /* G_FSHL */
4808 type0, type0, type0, type1,
4809 /* G_FSHR */
4810 type0, type0, type0, type1,
4811 /* G_ROTR */
4812 type0, type0, type1,
4813 /* G_ROTL */
4814 type0, type0, type1,
4815 /* G_ICMP */
4816 type0, -1, type1, type1,
4817 /* G_FCMP */
4818 type0, -1, type1, type1,
4819 /* G_SCMP */
4820 type0, type1, type1,
4821 /* G_UCMP */
4822 type0, type1, type1,
4823 /* G_SELECT */
4824 type0, type1, type0, type0,
4825 /* G_UADDO */
4826 type0, type1, type0, type0,
4827 /* G_UADDE */
4828 type0, type1, type0, type0, type1,
4829 /* G_USUBO */
4830 type0, type1, type0, type0,
4831 /* G_USUBE */
4832 type0, type1, type0, type0, type1,
4833 /* G_SADDO */
4834 type0, type1, type0, type0,
4835 /* G_SADDE */
4836 type0, type1, type0, type0, type1,
4837 /* G_SSUBO */
4838 type0, type1, type0, type0,
4839 /* G_SSUBE */
4840 type0, type1, type0, type0, type1,
4841 /* G_UMULO */
4842 type0, type1, type0, type0,
4843 /* G_SMULO */
4844 type0, type1, type0, type0,
4845 /* G_UMULH */
4846 type0, type0, type0,
4847 /* G_SMULH */
4848 type0, type0, type0,
4849 /* G_UADDSAT */
4850 type0, type0, type0,
4851 /* G_SADDSAT */
4852 type0, type0, type0,
4853 /* G_USUBSAT */
4854 type0, type0, type0,
4855 /* G_SSUBSAT */
4856 type0, type0, type0,
4857 /* G_USHLSAT */
4858 type0, type0, type1,
4859 /* G_SSHLSAT */
4860 type0, type0, type1,
4861 /* G_SMULFIX */
4862 type0, type0, type0, untyped_imm_0,
4863 /* G_UMULFIX */
4864 type0, type0, type0, untyped_imm_0,
4865 /* G_SMULFIXSAT */
4866 type0, type0, type0, untyped_imm_0,
4867 /* G_UMULFIXSAT */
4868 type0, type0, type0, untyped_imm_0,
4869 /* G_SDIVFIX */
4870 type0, type0, type0, untyped_imm_0,
4871 /* G_UDIVFIX */
4872 type0, type0, type0, untyped_imm_0,
4873 /* G_SDIVFIXSAT */
4874 type0, type0, type0, untyped_imm_0,
4875 /* G_UDIVFIXSAT */
4876 type0, type0, type0, untyped_imm_0,
4877 /* G_FADD */
4878 type0, type0, type0,
4879 /* G_FSUB */
4880 type0, type0, type0,
4881 /* G_FMUL */
4882 type0, type0, type0,
4883 /* G_FMA */
4884 type0, type0, type0, type0,
4885 /* G_FMAD */
4886 type0, type0, type0, type0,
4887 /* G_FDIV */
4888 type0, type0, type0,
4889 /* G_FREM */
4890 type0, type0, type0,
4891 /* G_FPOW */
4892 type0, type0, type0,
4893 /* G_FPOWI */
4894 type0, type0, type1,
4895 /* G_FEXP */
4896 type0, type0,
4897 /* G_FEXP2 */
4898 type0, type0,
4899 /* G_FEXP10 */
4900 type0, type0,
4901 /* G_FLOG */
4902 type0, type0,
4903 /* G_FLOG2 */
4904 type0, type0,
4905 /* G_FLOG10 */
4906 type0, type0,
4907 /* G_FLDEXP */
4908 type0, type0, type1,
4909 /* G_FFREXP */
4910 type0, type1, type0,
4911 /* G_FNEG */
4912 type0, type0,
4913 /* G_FPEXT */
4914 type0, type1,
4915 /* G_FPTRUNC */
4916 type0, type1,
4917 /* G_FPTOSI */
4918 type0, type1,
4919 /* G_FPTOUI */
4920 type0, type1,
4921 /* G_SITOFP */
4922 type0, type1,
4923 /* G_UITOFP */
4924 type0, type1,
4925 /* G_FABS */
4926 type0, type0,
4927 /* G_FCOPYSIGN */
4928 type0, type0, type1,
4929 /* G_IS_FPCLASS */
4930 type0, type1, -1,
4931 /* G_FCANONICALIZE */
4932 type0, type0,
4933 /* G_FMINNUM */
4934 type0, type0, type0,
4935 /* G_FMAXNUM */
4936 type0, type0, type0,
4937 /* G_FMINNUM_IEEE */
4938 type0, type0, type0,
4939 /* G_FMAXNUM_IEEE */
4940 type0, type0, type0,
4941 /* G_FMINIMUM */
4942 type0, type0, type0,
4943 /* G_FMAXIMUM */
4944 type0, type0, type0,
4945 /* G_GET_FPENV */
4946 type0,
4947 /* G_SET_FPENV */
4948 type0,
4949 /* G_RESET_FPENV */
4950 /* G_GET_FPMODE */
4951 type0,
4952 /* G_SET_FPMODE */
4953 type0,
4954 /* G_RESET_FPMODE */
4955 /* G_PTR_ADD */
4956 ptype0, ptype0, type1,
4957 /* G_PTRMASK */
4958 ptype0, ptype0, type1,
4959 /* G_SMIN */
4960 type0, type0, type0,
4961 /* G_SMAX */
4962 type0, type0, type0,
4963 /* G_UMIN */
4964 type0, type0, type0,
4965 /* G_UMAX */
4966 type0, type0, type0,
4967 /* G_ABS */
4968 type0, type0,
4969 /* G_LROUND */
4970 type0, type1,
4971 /* G_LLROUND */
4972 type0, type1,
4973 /* G_BR */
4974 -1,
4975 /* G_BRJT */
4976 ptype0, -1, type1,
4977 /* G_VSCALE */
4978 type0, -1,
4979 /* G_INSERT_SUBVECTOR */
4980 type0, type0, type1, untyped_imm_0,
4981 /* G_EXTRACT_SUBVECTOR */
4982 type0, type0, untyped_imm_0,
4983 /* G_INSERT_VECTOR_ELT */
4984 type0, type0, type1, type2,
4985 /* G_EXTRACT_VECTOR_ELT */
4986 type0, type1, type2,
4987 /* G_SHUFFLE_VECTOR */
4988 type0, type1, type1, -1,
4989 /* G_SPLAT_VECTOR */
4990 type0, type1,
4991 /* G_VECTOR_COMPRESS */
4992 type0, type0, type1, type0,
4993 /* G_CTTZ */
4994 type0, type1,
4995 /* G_CTTZ_ZERO_UNDEF */
4996 type0, type1,
4997 /* G_CTLZ */
4998 type0, type1,
4999 /* G_CTLZ_ZERO_UNDEF */
5000 type0, type1,
5001 /* G_CTPOP */
5002 type0, type1,
5003 /* G_BSWAP */
5004 type0, type0,
5005 /* G_BITREVERSE */
5006 type0, type0,
5007 /* G_FCEIL */
5008 type0, type0,
5009 /* G_FCOS */
5010 type0, type0,
5011 /* G_FSIN */
5012 type0, type0,
5013 /* G_FTAN */
5014 type0, type0,
5015 /* G_FACOS */
5016 type0, type0,
5017 /* G_FASIN */
5018 type0, type0,
5019 /* G_FATAN */
5020 type0, type0,
5021 /* G_FCOSH */
5022 type0, type0,
5023 /* G_FSINH */
5024 type0, type0,
5025 /* G_FTANH */
5026 type0, type0,
5027 /* G_FSQRT */
5028 type0, type0,
5029 /* G_FFLOOR */
5030 type0, type0,
5031 /* G_FRINT */
5032 type0, type0,
5033 /* G_FNEARBYINT */
5034 type0, type0,
5035 /* G_ADDRSPACE_CAST */
5036 type0, type1,
5037 /* G_BLOCK_ADDR */
5038 type0, -1,
5039 /* G_JUMP_TABLE */
5040 type0, -1,
5041 /* G_DYN_STACKALLOC */
5042 ptype0, type1, i32imm,
5043 /* G_STACKSAVE */
5044 ptype0,
5045 /* G_STACKRESTORE */
5046 ptype0,
5047 /* G_STRICT_FADD */
5048 type0, type0, type0,
5049 /* G_STRICT_FSUB */
5050 type0, type0, type0,
5051 /* G_STRICT_FMUL */
5052 type0, type0, type0,
5053 /* G_STRICT_FDIV */
5054 type0, type0, type0,
5055 /* G_STRICT_FREM */
5056 type0, type0, type0,
5057 /* G_STRICT_FMA */
5058 type0, type0, type0, type0,
5059 /* G_STRICT_FSQRT */
5060 type0, type0,
5061 /* G_STRICT_FLDEXP */
5062 type0, type0, type1,
5063 /* G_READ_REGISTER */
5064 type0, -1,
5065 /* G_WRITE_REGISTER */
5066 -1, type0,
5067 /* G_MEMCPY */
5068 ptype0, ptype1, type2, untyped_imm_0,
5069 /* G_MEMCPY_INLINE */
5070 ptype0, ptype1, type2,
5071 /* G_MEMMOVE */
5072 ptype0, ptype1, type2, untyped_imm_0,
5073 /* G_MEMSET */
5074 ptype0, type1, type2, untyped_imm_0,
5075 /* G_BZERO */
5076 ptype0, type1, untyped_imm_0,
5077 /* G_TRAP */
5078 /* G_DEBUGTRAP */
5079 /* G_UBSANTRAP */
5080 i8imm,
5081 /* G_VECREDUCE_SEQ_FADD */
5082 type0, type1, type2,
5083 /* G_VECREDUCE_SEQ_FMUL */
5084 type0, type1, type2,
5085 /* G_VECREDUCE_FADD */
5086 type0, type1,
5087 /* G_VECREDUCE_FMUL */
5088 type0, type1,
5089 /* G_VECREDUCE_FMAX */
5090 type0, type1,
5091 /* G_VECREDUCE_FMIN */
5092 type0, type1,
5093 /* G_VECREDUCE_FMAXIMUM */
5094 type0, type1,
5095 /* G_VECREDUCE_FMINIMUM */
5096 type0, type1,
5097 /* G_VECREDUCE_ADD */
5098 type0, type1,
5099 /* G_VECREDUCE_MUL */
5100 type0, type1,
5101 /* G_VECREDUCE_AND */
5102 type0, type1,
5103 /* G_VECREDUCE_OR */
5104 type0, type1,
5105 /* G_VECREDUCE_XOR */
5106 type0, type1,
5107 /* G_VECREDUCE_SMAX */
5108 type0, type1,
5109 /* G_VECREDUCE_SMIN */
5110 type0, type1,
5111 /* G_VECREDUCE_UMAX */
5112 type0, type1,
5113 /* G_VECREDUCE_UMIN */
5114 type0, type1,
5115 /* G_SBFX */
5116 type0, type0, type1, type1,
5117 /* G_UBFX */
5118 type0, type0, type1, type1,
5119 /* ADJCALLSTACKDOWN */
5120 i32imm, i32imm,
5121 /* ADJCALLSTACKUP */
5122 i32imm, i32imm,
5123 /* GETPCX */
5124 getPCX,
5125 /* SELECT_CC_DFP_FCC */
5126 DFPRegs, DFPRegs, DFPRegs, i32imm,
5127 /* SELECT_CC_DFP_ICC */
5128 DFPRegs, DFPRegs, DFPRegs, i32imm,
5129 /* SELECT_CC_DFP_XCC */
5130 DFPRegs, DFPRegs, DFPRegs, i32imm,
5131 /* SELECT_CC_FP_FCC */
5132 FPRegs, FPRegs, FPRegs, i32imm,
5133 /* SELECT_CC_FP_ICC */
5134 FPRegs, FPRegs, FPRegs, i32imm,
5135 /* SELECT_CC_FP_XCC */
5136 FPRegs, FPRegs, FPRegs, i32imm,
5137 /* SELECT_CC_Int_FCC */
5138 IntRegs, IntRegs, IntRegs, i32imm,
5139 /* SELECT_CC_Int_ICC */
5140 IntRegs, IntRegs, IntRegs, i32imm,
5141 /* SELECT_CC_Int_XCC */
5142 IntRegs, IntRegs, IntRegs, i32imm,
5143 /* SELECT_CC_QFP_FCC */
5144 QFPRegs, QFPRegs, QFPRegs, i32imm,
5145 /* SELECT_CC_QFP_ICC */
5146 QFPRegs, QFPRegs, QFPRegs, i32imm,
5147 /* SELECT_CC_QFP_XCC */
5148 QFPRegs, QFPRegs, QFPRegs, i32imm,
5149 /* SET */
5150 IntRegs, i32imm,
5151 /* SETX */
5152 I64Regs, i64imm, I64Regs,
5153 /* ADDCCri */
5154 IntRegs, IntRegs, simm13Op,
5155 /* ADDCCrr */
5156 IntRegs, IntRegs, IntRegs,
5157 /* ADDCri */
5158 IntRegs, IntRegs, simm13Op,
5159 /* ADDCrr */
5160 IntRegs, IntRegs, IntRegs,
5161 /* ADDEri */
5162 IntRegs, IntRegs, simm13Op,
5163 /* ADDErr */
5164 IntRegs, IntRegs, IntRegs,
5165 /* ADDXC */
5166 I64Regs, I64Regs, I64Regs,
5167 /* ADDXCCC */
5168 I64Regs, I64Regs, I64Regs,
5169 /* ADDri */
5170 IntRegs, IntRegs, simm13Op,
5171 /* ADDrr */
5172 IntRegs, IntRegs, IntRegs,
5173 /* ALIGNADDR */
5174 I64Regs, I64Regs, I64Regs,
5175 /* ALIGNADDRL */
5176 I64Regs, I64Regs, I64Regs,
5177 /* ANDCCri */
5178 IntRegs, IntRegs, simm13Op,
5179 /* ANDCCrr */
5180 IntRegs, IntRegs, IntRegs,
5181 /* ANDNCCri */
5182 IntRegs, IntRegs, simm13Op,
5183 /* ANDNCCrr */
5184 IntRegs, IntRegs, IntRegs,
5185 /* ANDNri */
5186 IntRegs, IntRegs, simm13Op,
5187 /* ANDNrr */
5188 IntRegs, IntRegs, IntRegs,
5189 /* ANDri */
5190 IntRegs, IntRegs, simm13Op,
5191 /* ANDrr */
5192 IntRegs, IntRegs, IntRegs,
5193 /* ARRAY16 */
5194 I64Regs, I64Regs, I64Regs,
5195 /* ARRAY32 */
5196 I64Regs, I64Regs, I64Regs,
5197 /* ARRAY8 */
5198 I64Regs, I64Regs, I64Regs,
5199 /* BA */
5200 brtarget,
5201 /* BCOND */
5202 brtarget, CCOp,
5203 /* BCONDA */
5204 brtarget, CCOp,
5205 /* BINDri */
5206 -1, i32imm,
5207 /* BINDrr */
5208 -1, -1,
5209 /* BMASK */
5210 I64Regs, I64Regs, I64Regs,
5211 /* BPFCC */
5212 bprtarget, CCOp, FCCRegs,
5213 /* BPFCCA */
5214 bprtarget, CCOp, FCCRegs,
5215 /* BPFCCANT */
5216 bprtarget, CCOp, FCCRegs,
5217 /* BPFCCNT */
5218 bprtarget, CCOp, FCCRegs,
5219 /* BPICC */
5220 bprtarget, CCOp,
5221 /* BPICCA */
5222 bprtarget, CCOp,
5223 /* BPICCANT */
5224 bprtarget, CCOp,
5225 /* BPICCNT */
5226 bprtarget, CCOp,
5227 /* BPR */
5228 bprtarget16, RegCCOp, I64Regs,
5229 /* BPRA */
5230 bprtarget16, RegCCOp, I64Regs,
5231 /* BPRANT */
5232 bprtarget16, RegCCOp, I64Regs,
5233 /* BPRNT */
5234 bprtarget16, RegCCOp, I64Regs,
5235 /* BPXCC */
5236 bprtarget, CCOp,
5237 /* BPXCCA */
5238 bprtarget, CCOp,
5239 /* BPXCCANT */
5240 bprtarget, CCOp,
5241 /* BPXCCNT */
5242 bprtarget, CCOp,
5243 /* BSHUFFLE */
5244 DFPRegs, DFPRegs, DFPRegs,
5245 /* CALL */
5246 calltarget,
5247 /* CALLri */
5248 -1, i32imm,
5249 /* CALLrr */
5250 -1, -1,
5251 /* CASAri */
5252 IntRegs, IntRegs, IntRegs, IntRegs,
5253 /* CASArr */
5254 IntRegs, IntRegs, IntRegs, IntRegs, ASITag,
5255 /* CASXAri */
5256 I64Regs, I64Regs, I64Regs, I64Regs,
5257 /* CASXArr */
5258 I64Regs, I64Regs, I64Regs, I64Regs, ASITag,
5259 /* CBCOND */
5260 brtarget, CCOp,
5261 /* CBCONDA */
5262 brtarget, CCOp,
5263 /* CMASK16 */
5264 I64Regs,
5265 /* CMASK32 */
5266 I64Regs,
5267 /* CMASK8 */
5268 I64Regs,
5269 /* DONE */
5270 /* EDGE16 */
5271 I64Regs, I64Regs, I64Regs,
5272 /* EDGE16L */
5273 I64Regs, I64Regs, I64Regs,
5274 /* EDGE16LN */
5275 I64Regs, I64Regs, I64Regs,
5276 /* EDGE16N */
5277 I64Regs, I64Regs, I64Regs,
5278 /* EDGE32 */
5279 I64Regs, I64Regs, I64Regs,
5280 /* EDGE32L */
5281 I64Regs, I64Regs, I64Regs,
5282 /* EDGE32LN */
5283 I64Regs, I64Regs, I64Regs,
5284 /* EDGE32N */
5285 I64Regs, I64Regs, I64Regs,
5286 /* EDGE8 */
5287 I64Regs, I64Regs, I64Regs,
5288 /* EDGE8L */
5289 I64Regs, I64Regs, I64Regs,
5290 /* EDGE8LN */
5291 I64Regs, I64Regs, I64Regs,
5292 /* EDGE8N */
5293 I64Regs, I64Regs, I64Regs,
5294 /* FABSD */
5295 DFPRegs, DFPRegs,
5296 /* FABSQ */
5297 QFPRegs, QFPRegs,
5298 /* FABSS */
5299 FPRegs, FPRegs,
5300 /* FADDD */
5301 DFPRegs, DFPRegs, DFPRegs,
5302 /* FADDQ */
5303 QFPRegs, QFPRegs, QFPRegs,
5304 /* FADDS */
5305 FPRegs, FPRegs, FPRegs,
5306 /* FALIGNADATA */
5307 DFPRegs, DFPRegs, DFPRegs,
5308 /* FAND */
5309 DFPRegs, DFPRegs, DFPRegs,
5310 /* FANDNOT1 */
5311 DFPRegs, DFPRegs, DFPRegs,
5312 /* FANDNOT1S */
5313 FPRegs, FPRegs, FPRegs,
5314 /* FANDNOT2 */
5315 DFPRegs, DFPRegs, DFPRegs,
5316 /* FANDNOT2S */
5317 FPRegs, FPRegs, FPRegs,
5318 /* FANDS */
5319 FPRegs, FPRegs, FPRegs,
5320 /* FBCOND */
5321 brtarget, CCOp,
5322 /* FBCONDA */
5323 brtarget, CCOp,
5324 /* FBCONDA_V9 */
5325 bprtarget, CCOp,
5326 /* FBCOND_V9 */
5327 bprtarget, CCOp,
5328 /* FCHKSM16 */
5329 DFPRegs, DFPRegs, DFPRegs,
5330 /* FCMPD */
5331 DFPRegs, DFPRegs,
5332 /* FCMPD_V9 */
5333 DFPRegs, DFPRegs,
5334 /* FCMPEQ16 */
5335 I64Regs, DFPRegs, DFPRegs,
5336 /* FCMPEQ32 */
5337 I64Regs, DFPRegs, DFPRegs,
5338 /* FCMPGT16 */
5339 I64Regs, DFPRegs, DFPRegs,
5340 /* FCMPGT32 */
5341 I64Regs, DFPRegs, DFPRegs,
5342 /* FCMPLE16 */
5343 I64Regs, DFPRegs, DFPRegs,
5344 /* FCMPLE32 */
5345 I64Regs, DFPRegs, DFPRegs,
5346 /* FCMPNE16 */
5347 I64Regs, DFPRegs, DFPRegs,
5348 /* FCMPNE32 */
5349 I64Regs, DFPRegs, DFPRegs,
5350 /* FCMPQ */
5351 QFPRegs, QFPRegs,
5352 /* FCMPQ_V9 */
5353 QFPRegs, QFPRegs,
5354 /* FCMPS */
5355 FPRegs, FPRegs,
5356 /* FCMPS_V9 */
5357 FPRegs, FPRegs,
5358 /* FDIVD */
5359 DFPRegs, DFPRegs, DFPRegs,
5360 /* FDIVQ */
5361 QFPRegs, QFPRegs, QFPRegs,
5362 /* FDIVS */
5363 FPRegs, FPRegs, FPRegs,
5364 /* FDMULQ */
5365 QFPRegs, DFPRegs, DFPRegs,
5366 /* FDTOI */
5367 FPRegs, DFPRegs,
5368 /* FDTOQ */
5369 QFPRegs, DFPRegs,
5370 /* FDTOS */
5371 FPRegs, DFPRegs,
5372 /* FDTOX */
5373 DFPRegs, DFPRegs,
5374 /* FEXPAND */
5375 DFPRegs, DFPRegs,
5376 /* FHADDD */
5377 DFPRegs, DFPRegs, DFPRegs,
5378 /* FHADDS */
5379 DFPRegs, DFPRegs, DFPRegs,
5380 /* FHSUBD */
5381 DFPRegs, DFPRegs, DFPRegs,
5382 /* FHSUBS */
5383 DFPRegs, DFPRegs, DFPRegs,
5384 /* FITOD */
5385 DFPRegs, FPRegs,
5386 /* FITOQ */
5387 QFPRegs, FPRegs,
5388 /* FITOS */
5389 FPRegs, FPRegs,
5390 /* FLCMPD */
5391 FCCRegs, DFPRegs, DFPRegs,
5392 /* FLCMPS */
5393 FCCRegs, DFPRegs, DFPRegs,
5394 /* FLUSH */
5395 /* FLUSHW */
5396 /* FLUSHri */
5397 -1, i32imm,
5398 /* FLUSHrr */
5399 -1, -1,
5400 /* FMEAN16 */
5401 DFPRegs, DFPRegs, DFPRegs,
5402 /* FMOVD */
5403 DFPRegs, DFPRegs,
5404 /* FMOVD_FCC */
5405 DFPRegs, DFPRegs, DFPRegs, CCOp,
5406 /* FMOVD_ICC */
5407 DFPRegs, DFPRegs, DFPRegs, CCOp,
5408 /* FMOVD_XCC */
5409 DFPRegs, DFPRegs, DFPRegs, CCOp,
5410 /* FMOVQ */
5411 QFPRegs, QFPRegs,
5412 /* FMOVQ_FCC */
5413 QFPRegs, QFPRegs, QFPRegs, CCOp,
5414 /* FMOVQ_ICC */
5415 QFPRegs, QFPRegs, QFPRegs, CCOp,
5416 /* FMOVQ_XCC */
5417 QFPRegs, QFPRegs, QFPRegs, CCOp,
5418 /* FMOVRD */
5419 DFPRegs, I64Regs, DFPRegs, DFPRegs, RegCCOp,
5420 /* FMOVRQ */
5421 QFPRegs, I64Regs, QFPRegs, QFPRegs, RegCCOp,
5422 /* FMOVRS */
5423 FPRegs, I64Regs, FPRegs, FPRegs, RegCCOp,
5424 /* FMOVS */
5425 FPRegs, FPRegs,
5426 /* FMOVS_FCC */
5427 FPRegs, FPRegs, FPRegs, CCOp,
5428 /* FMOVS_ICC */
5429 FPRegs, FPRegs, FPRegs, CCOp,
5430 /* FMOVS_XCC */
5431 FPRegs, FPRegs, FPRegs, CCOp,
5432 /* FMUL8SUX16 */
5433 DFPRegs, DFPRegs, DFPRegs,
5434 /* FMUL8ULX16 */
5435 DFPRegs, DFPRegs, DFPRegs,
5436 /* FMUL8X16 */
5437 DFPRegs, DFPRegs, DFPRegs,
5438 /* FMUL8X16AL */
5439 DFPRegs, DFPRegs, DFPRegs,
5440 /* FMUL8X16AU */
5441 DFPRegs, DFPRegs, DFPRegs,
5442 /* FMULD */
5443 DFPRegs, DFPRegs, DFPRegs,
5444 /* FMULD8SUX16 */
5445 DFPRegs, DFPRegs, DFPRegs,
5446 /* FMULD8ULX16 */
5447 DFPRegs, DFPRegs, DFPRegs,
5448 /* FMULQ */
5449 QFPRegs, QFPRegs, QFPRegs,
5450 /* FMULS */
5451 FPRegs, FPRegs, FPRegs,
5452 /* FNADDD */
5453 DFPRegs, DFPRegs, DFPRegs,
5454 /* FNADDS */
5455 DFPRegs, DFPRegs, DFPRegs,
5456 /* FNAND */
5457 DFPRegs, DFPRegs, DFPRegs,
5458 /* FNANDS */
5459 FPRegs, FPRegs, FPRegs,
5460 /* FNEGD */
5461 DFPRegs, DFPRegs,
5462 /* FNEGQ */
5463 QFPRegs, QFPRegs,
5464 /* FNEGS */
5465 FPRegs, FPRegs,
5466 /* FNHADDD */
5467 DFPRegs, DFPRegs, DFPRegs,
5468 /* FNHADDS */
5469 DFPRegs, DFPRegs, DFPRegs,
5470 /* FNMULD */
5471 DFPRegs, DFPRegs, DFPRegs,
5472 /* FNMULS */
5473 DFPRegs, DFPRegs, DFPRegs,
5474 /* FNOR */
5475 DFPRegs, DFPRegs, DFPRegs,
5476 /* FNORS */
5477 FPRegs, FPRegs, FPRegs,
5478 /* FNOT1 */
5479 DFPRegs, DFPRegs,
5480 /* FNOT1S */
5481 FPRegs, FPRegs,
5482 /* FNOT2 */
5483 DFPRegs, DFPRegs,
5484 /* FNOT2S */
5485 FPRegs, FPRegs,
5486 /* FNSMULD */
5487 DFPRegs, DFPRegs, DFPRegs,
5488 /* FONE */
5489 DFPRegs, DFPRegs,
5490 /* FONES */
5491 FPRegs, FPRegs,
5492 /* FOR */
5493 DFPRegs, DFPRegs, DFPRegs,
5494 /* FORNOT1 */
5495 DFPRegs, DFPRegs, DFPRegs,
5496 /* FORNOT1S */
5497 FPRegs, FPRegs, FPRegs,
5498 /* FORNOT2 */
5499 DFPRegs, DFPRegs, DFPRegs,
5500 /* FORNOT2S */
5501 FPRegs, FPRegs, FPRegs,
5502 /* FORS */
5503 FPRegs, FPRegs, FPRegs,
5504 /* FPACK16 */
5505 DFPRegs, DFPRegs,
5506 /* FPACK32 */
5507 DFPRegs, DFPRegs, DFPRegs,
5508 /* FPACKFIX */
5509 DFPRegs, DFPRegs,
5510 /* FPADD16 */
5511 DFPRegs, DFPRegs, DFPRegs,
5512 /* FPADD16S */
5513 DFPRegs, DFPRegs, DFPRegs,
5514 /* FPADD32 */
5515 DFPRegs, DFPRegs, DFPRegs,
5516 /* FPADD32S */
5517 DFPRegs, DFPRegs, DFPRegs,
5518 /* FPADD64 */
5519 DFPRegs, DFPRegs, DFPRegs,
5520 /* FPMERGE */
5521 DFPRegs, DFPRegs, DFPRegs,
5522 /* FPSUB16 */
5523 DFPRegs, DFPRegs, DFPRegs,
5524 /* FPSUB16S */
5525 DFPRegs, DFPRegs, DFPRegs,
5526 /* FPSUB32 */
5527 DFPRegs, DFPRegs, DFPRegs,
5528 /* FPSUB32S */
5529 DFPRegs, DFPRegs, DFPRegs,
5530 /* FQTOD */
5531 DFPRegs, QFPRegs,
5532 /* FQTOI */
5533 FPRegs, QFPRegs,
5534 /* FQTOS */
5535 FPRegs, QFPRegs,
5536 /* FQTOX */
5537 DFPRegs, QFPRegs,
5538 /* FSLAS16 */
5539 DFPRegs, DFPRegs, DFPRegs,
5540 /* FSLAS32 */
5541 DFPRegs, DFPRegs, DFPRegs,
5542 /* FSLL16 */
5543 DFPRegs, DFPRegs, DFPRegs,
5544 /* FSLL32 */
5545 DFPRegs, DFPRegs, DFPRegs,
5546 /* FSMULD */
5547 DFPRegs, FPRegs, FPRegs,
5548 /* FSQRTD */
5549 DFPRegs, DFPRegs,
5550 /* FSQRTQ */
5551 QFPRegs, QFPRegs,
5552 /* FSQRTS */
5553 FPRegs, FPRegs,
5554 /* FSRA16 */
5555 DFPRegs, DFPRegs, DFPRegs,
5556 /* FSRA32 */
5557 DFPRegs, DFPRegs, DFPRegs,
5558 /* FSRC1 */
5559 DFPRegs, DFPRegs,
5560 /* FSRC1S */
5561 FPRegs, FPRegs,
5562 /* FSRC2 */
5563 DFPRegs, DFPRegs,
5564 /* FSRC2S */
5565 FPRegs, FPRegs,
5566 /* FSRL16 */
5567 DFPRegs, DFPRegs, DFPRegs,
5568 /* FSRL32 */
5569 DFPRegs, DFPRegs, DFPRegs,
5570 /* FSTOD */
5571 DFPRegs, FPRegs,
5572 /* FSTOI */
5573 FPRegs, FPRegs,
5574 /* FSTOQ */
5575 QFPRegs, FPRegs,
5576 /* FSTOX */
5577 DFPRegs, FPRegs,
5578 /* FSUBD */
5579 DFPRegs, DFPRegs, DFPRegs,
5580 /* FSUBQ */
5581 QFPRegs, QFPRegs, QFPRegs,
5582 /* FSUBS */
5583 FPRegs, FPRegs, FPRegs,
5584 /* FXNOR */
5585 DFPRegs, DFPRegs, DFPRegs,
5586 /* FXNORS */
5587 FPRegs, FPRegs, FPRegs,
5588 /* FXOR */
5589 DFPRegs, DFPRegs, DFPRegs,
5590 /* FXORS */
5591 FPRegs, FPRegs, FPRegs,
5592 /* FXTOD */
5593 DFPRegs, DFPRegs,
5594 /* FXTOQ */
5595 QFPRegs, DFPRegs,
5596 /* FXTOS */
5597 FPRegs, DFPRegs,
5598 /* FZERO */
5599 DFPRegs, DFPRegs,
5600 /* FZEROS */
5601 FPRegs, FPRegs,
5602 /* GDOP_LDXrr */
5603 I64Regs, -1, -1, TailRelocSymGOTLoad,
5604 /* GDOP_LDrr */
5605 IntRegs, -1, -1, TailRelocSymGOTLoad,
5606 /* JMPLri */
5607 IntRegs, -1, i32imm,
5608 /* JMPLrr */
5609 IntRegs, -1, -1,
5610 /* LDAri */
5611 IntRegs, -1, i32imm,
5612 /* LDArr */
5613 IntRegs, -1, -1, ASITag,
5614 /* LDCSRri */
5615 -1, i32imm,
5616 /* LDCSRrr */
5617 -1, -1,
5618 /* LDCri */
5619 CoprocRegs, -1, i32imm,
5620 /* LDCrr */
5621 CoprocRegs, -1, -1,
5622 /* LDDAri */
5623 IntPair, -1, i32imm,
5624 /* LDDArr */
5625 IntPair, -1, -1, ASITag,
5626 /* LDDCri */
5627 CoprocPair, -1, i32imm,
5628 /* LDDCrr */
5629 CoprocPair, -1, -1,
5630 /* LDDFAri */
5631 DFPRegs, -1, i32imm,
5632 /* LDDFArr */
5633 DFPRegs, -1, -1, ASITag,
5634 /* LDDFri */
5635 DFPRegs, -1, i32imm,
5636 /* LDDFrr */
5637 DFPRegs, -1, -1,
5638 /* LDDri */
5639 IntPair, -1, i32imm,
5640 /* LDDrr */
5641 IntPair, -1, -1,
5642 /* LDFAri */
5643 FPRegs, -1, i32imm,
5644 /* LDFArr */
5645 FPRegs, -1, -1, ASITag,
5646 /* LDFSRri */
5647 -1, i32imm,
5648 /* LDFSRrr */
5649 -1, -1,
5650 /* LDFri */
5651 FPRegs, -1, i32imm,
5652 /* LDFrr */
5653 FPRegs, -1, -1,
5654 /* LDQFAri */
5655 QFPRegs, -1, i32imm,
5656 /* LDQFArr */
5657 QFPRegs, -1, -1, ASITag,
5658 /* LDQFri */
5659 QFPRegs, -1, i32imm,
5660 /* LDQFrr */
5661 QFPRegs, -1, -1,
5662 /* LDSBAri */
5663 IntRegs, -1, i32imm,
5664 /* LDSBArr */
5665 IntRegs, -1, -1, ASITag,
5666 /* LDSBri */
5667 IntRegs, -1, i32imm,
5668 /* LDSBrr */
5669 IntRegs, -1, -1,
5670 /* LDSHAri */
5671 IntRegs, -1, i32imm,
5672 /* LDSHArr */
5673 IntRegs, -1, -1, ASITag,
5674 /* LDSHri */
5675 IntRegs, -1, i32imm,
5676 /* LDSHrr */
5677 IntRegs, -1, -1,
5678 /* LDSTUBAri */
5679 IntRegs, -1, i32imm,
5680 /* LDSTUBArr */
5681 IntRegs, -1, -1, ASITag,
5682 /* LDSTUBri */
5683 IntRegs, -1, i32imm,
5684 /* LDSTUBrr */
5685 IntRegs, -1, -1,
5686 /* LDSWAri */
5687 I64Regs, -1, i32imm,
5688 /* LDSWArr */
5689 I64Regs, -1, -1, ASITag,
5690 /* LDSWri */
5691 I64Regs, -1, i32imm,
5692 /* LDSWrr */
5693 I64Regs, -1, -1,
5694 /* LDUBAri */
5695 IntRegs, -1, i32imm,
5696 /* LDUBArr */
5697 IntRegs, -1, -1, ASITag,
5698 /* LDUBri */
5699 IntRegs, -1, i32imm,
5700 /* LDUBrr */
5701 IntRegs, -1, -1,
5702 /* LDUHAri */
5703 IntRegs, -1, i32imm,
5704 /* LDUHArr */
5705 IntRegs, -1, -1, ASITag,
5706 /* LDUHri */
5707 IntRegs, -1, i32imm,
5708 /* LDUHrr */
5709 IntRegs, -1, -1,
5710 /* LDXAri */
5711 I64Regs, -1, i32imm,
5712 /* LDXArr */
5713 I64Regs, -1, -1, ASITag,
5714 /* LDXFSRri */
5715 -1, i32imm,
5716 /* LDXFSRrr */
5717 -1, -1,
5718 /* LDXri */
5719 I64Regs, -1, i32imm,
5720 /* LDXrr */
5721 I64Regs, -1, -1,
5722 /* LDri */
5723 IntRegs, -1, i32imm,
5724 /* LDrr */
5725 IntRegs, -1, -1,
5726 /* LZCNT */
5727 I64Regs, I64Regs,
5728 /* MEMBARi */
5729 MembarTag,
5730 /* MOVDTOX */
5731 I64Regs, DFPRegs,
5732 /* MOVFCCri */
5733 IntRegs, i32imm, IntRegs, CCOp,
5734 /* MOVFCCrr */
5735 IntRegs, IntRegs, IntRegs, CCOp,
5736 /* MOVICCri */
5737 IntRegs, i32imm, IntRegs, CCOp,
5738 /* MOVICCrr */
5739 IntRegs, IntRegs, IntRegs, CCOp,
5740 /* MOVRri */
5741 IntRegs, I64Regs, i32imm, IntRegs, RegCCOp,
5742 /* MOVRrr */
5743 IntRegs, I64Regs, IntRegs, IntRegs, RegCCOp,
5744 /* MOVSTOSW */
5745 I64Regs, DFPRegs,
5746 /* MOVSTOUW */
5747 I64Regs, DFPRegs,
5748 /* MOVWTOS */
5749 DFPRegs, I64Regs,
5750 /* MOVXCCri */
5751 IntRegs, i32imm, IntRegs, CCOp,
5752 /* MOVXCCrr */
5753 IntRegs, IntRegs, IntRegs, CCOp,
5754 /* MOVXTOD */
5755 DFPRegs, I64Regs,
5756 /* MULSCCri */
5757 IntRegs, IntRegs, simm13Op,
5758 /* MULSCCrr */
5759 IntRegs, IntRegs, IntRegs,
5760 /* MULXri */
5761 IntRegs, IntRegs, i64imm,
5762 /* MULXrr */
5763 I64Regs, I64Regs, I64Regs,
5764 /* NOP */
5765 /* ORCCri */
5766 IntRegs, IntRegs, simm13Op,
5767 /* ORCCrr */
5768 IntRegs, IntRegs, IntRegs,
5769 /* ORNCCri */
5770 IntRegs, IntRegs, simm13Op,
5771 /* ORNCCrr */
5772 IntRegs, IntRegs, IntRegs,
5773 /* ORNri */
5774 IntRegs, IntRegs, simm13Op,
5775 /* ORNrr */
5776 IntRegs, IntRegs, IntRegs,
5777 /* ORri */
5778 IntRegs, IntRegs, simm13Op,
5779 /* ORrr */
5780 IntRegs, IntRegs, IntRegs,
5781 /* PDIST */
5782 DFPRegs, DFPRegs, DFPRegs,
5783 /* PDISTN */
5784 DFPRegs, DFPRegs, DFPRegs,
5785 /* POPCrr */
5786 IntRegs, IntRegs,
5787 /* PREFETCHAi */
5788 -1, i32imm, PrefetchTag,
5789 /* PREFETCHAr */
5790 -1, -1, ASITag, PrefetchTag,
5791 /* PREFETCHi */
5792 -1, i32imm, PrefetchTag,
5793 /* PREFETCHr */
5794 -1, -1, PrefetchTag,
5795 /* PWRPSRri */
5796 IntRegs, simm13Op,
5797 /* PWRPSRrr */
5798 IntRegs, IntRegs,
5799 /* RDASR */
5800 IntRegs, ASRRegs,
5801 /* RDFQ */
5802 IntRegs,
5803 /* RDPR */
5804 IntRegs, PRRegs,
5805 /* RDPSR */
5806 IntRegs,
5807 /* RDTBR */
5808 IntRegs,
5809 /* RDWIM */
5810 IntRegs,
5811 /* RESTORED */
5812 /* RESTOREri */
5813 IntRegs, IntRegs, simm13Op,
5814 /* RESTORErr */
5815 IntRegs, IntRegs, IntRegs,
5816 /* RET */
5817 i32imm,
5818 /* RETL */
5819 i32imm,
5820 /* RETRY */
5821 /* RETTri */
5822 -1, i32imm,
5823 /* RETTrr */
5824 -1, -1,
5825 /* SAVED */
5826 /* SAVEri */
5827 IntRegs, IntRegs, simm13Op,
5828 /* SAVErr */
5829 IntRegs, IntRegs, IntRegs,
5830 /* SDIVCCri */
5831 IntRegs, IntRegs, simm13Op,
5832 /* SDIVCCrr */
5833 IntRegs, IntRegs, IntRegs,
5834 /* SDIVXri */
5835 IntRegs, IntRegs, i64imm,
5836 /* SDIVXrr */
5837 I64Regs, I64Regs, I64Regs,
5838 /* SDIVri */
5839 IntRegs, IntRegs, simm13Op,
5840 /* SDIVrr */
5841 IntRegs, IntRegs, IntRegs,
5842 /* SETHIi */
5843 IntRegs, i32imm,
5844 /* SHUTDOWN */
5845 /* SIAM */
5846 /* SIR */
5847 simm13Op,
5848 /* SLLXri */
5849 I64Regs, I64Regs, shift_imm6,
5850 /* SLLXrr */
5851 I64Regs, I64Regs, IntRegs,
5852 /* SLLri */
5853 IntRegs, IntRegs, shift_imm5,
5854 /* SLLrr */
5855 IntRegs, IntRegs, IntRegs,
5856 /* SMACri */
5857 IntRegs, IntRegs, simm13Op, ASRRegs,
5858 /* SMACrr */
5859 IntRegs, IntRegs, IntRegs, ASRRegs,
5860 /* SMULCCri */
5861 IntRegs, IntRegs, simm13Op,
5862 /* SMULCCrr */
5863 IntRegs, IntRegs, IntRegs,
5864 /* SMULri */
5865 IntRegs, IntRegs, simm13Op,
5866 /* SMULrr */
5867 IntRegs, IntRegs, IntRegs,
5868 /* SRAXri */
5869 I64Regs, I64Regs, shift_imm6,
5870 /* SRAXrr */
5871 I64Regs, I64Regs, IntRegs,
5872 /* SRAri */
5873 IntRegs, IntRegs, shift_imm5,
5874 /* SRArr */
5875 IntRegs, IntRegs, IntRegs,
5876 /* SRLXri */
5877 I64Regs, I64Regs, shift_imm6,
5878 /* SRLXrr */
5879 I64Regs, I64Regs, IntRegs,
5880 /* SRLri */
5881 IntRegs, IntRegs, shift_imm5,
5882 /* SRLrr */
5883 IntRegs, IntRegs, IntRegs,
5884 /* STAri */
5885 -1, i32imm, IntRegs,
5886 /* STArr */
5887 -1, -1, IntRegs, ASITag,
5888 /* STBAR */
5889 /* STBAri */
5890 -1, i32imm, IntRegs,
5891 /* STBArr */
5892 -1, -1, IntRegs, ASITag,
5893 /* STBri */
5894 -1, i32imm, IntRegs,
5895 /* STBrr */
5896 -1, -1, IntRegs,
5897 /* STCSRri */
5898 -1, i32imm,
5899 /* STCSRrr */
5900 -1, -1,
5901 /* STCri */
5902 -1, i32imm, CoprocRegs,
5903 /* STCrr */
5904 -1, -1, CoprocRegs,
5905 /* STDAri */
5906 -1, i32imm, IntPair,
5907 /* STDArr */
5908 -1, -1, IntPair, ASITag,
5909 /* STDCQri */
5910 -1, i32imm,
5911 /* STDCQrr */
5912 -1, -1,
5913 /* STDCri */
5914 -1, i32imm, CoprocPair,
5915 /* STDCrr */
5916 -1, -1, CoprocPair,
5917 /* STDFAri */
5918 -1, i32imm, DFPRegs,
5919 /* STDFArr */
5920 -1, -1, DFPRegs, ASITag,
5921 /* STDFQri */
5922 -1, i32imm,
5923 /* STDFQrr */
5924 -1, -1,
5925 /* STDFri */
5926 -1, i32imm, DFPRegs,
5927 /* STDFrr */
5928 -1, -1, DFPRegs,
5929 /* STDri */
5930 -1, i32imm, IntPair,
5931 /* STDrr */
5932 -1, -1, IntPair,
5933 /* STFAri */
5934 -1, i32imm, FPRegs,
5935 /* STFArr */
5936 -1, -1, FPRegs, ASITag,
5937 /* STFSRri */
5938 -1, i32imm,
5939 /* STFSRrr */
5940 -1, -1,
5941 /* STFri */
5942 -1, i32imm, FPRegs,
5943 /* STFrr */
5944 -1, -1, FPRegs,
5945 /* STHAri */
5946 -1, i32imm, IntRegs,
5947 /* STHArr */
5948 -1, -1, IntRegs, ASITag,
5949 /* STHri */
5950 -1, i32imm, IntRegs,
5951 /* STHrr */
5952 -1, -1, IntRegs,
5953 /* STQFAri */
5954 -1, i32imm, QFPRegs,
5955 /* STQFArr */
5956 -1, -1, QFPRegs, ASITag,
5957 /* STQFri */
5958 -1, i32imm, QFPRegs,
5959 /* STQFrr */
5960 -1, -1, QFPRegs,
5961 /* STXAri */
5962 -1, i32imm, I64Regs,
5963 /* STXArr */
5964 -1, -1, I64Regs, ASITag,
5965 /* STXFSRri */
5966 -1, i32imm,
5967 /* STXFSRrr */
5968 -1, -1,
5969 /* STXri */
5970 -1, i32imm, I64Regs,
5971 /* STXrr */
5972 -1, -1, I64Regs,
5973 /* STri */
5974 -1, i32imm, IntRegs,
5975 /* STrr */
5976 -1, -1, IntRegs,
5977 /* SUBCCri */
5978 IntRegs, IntRegs, simm13Op,
5979 /* SUBCCrr */
5980 IntRegs, IntRegs, IntRegs,
5981 /* SUBCri */
5982 IntRegs, IntRegs, simm13Op,
5983 /* SUBCrr */
5984 IntRegs, IntRegs, IntRegs,
5985 /* SUBEri */
5986 IntRegs, IntRegs, simm13Op,
5987 /* SUBErr */
5988 IntRegs, IntRegs, IntRegs,
5989 /* SUBri */
5990 IntRegs, IntRegs, simm13Op,
5991 /* SUBrr */
5992 IntRegs, IntRegs, IntRegs,
5993 /* SWAPAri */
5994 IntRegs, -1, i32imm, IntRegs,
5995 /* SWAPArr */
5996 IntRegs, -1, -1, ASITag, IntRegs,
5997 /* SWAPri */
5998 IntRegs, -1, i32imm, IntRegs,
5999 /* SWAPrr */
6000 IntRegs, -1, -1, IntRegs,
6001 /* TA1 */
6002 /* TA3 */
6003 /* TA5 */
6004 /* TADDCCTVri */
6005 IntRegs, IntRegs, simm13Op,
6006 /* TADDCCTVrr */
6007 IntRegs, IntRegs, IntRegs,
6008 /* TADDCCri */
6009 IntRegs, IntRegs, simm13Op,
6010 /* TADDCCrr */
6011 IntRegs, IntRegs, IntRegs,
6012 /* TAIL_CALL */
6013 calltarget,
6014 /* TAIL_CALLri */
6015 -1, i32imm,
6016 /* TICCri */
6017 IntRegs, i32imm, CCOp,
6018 /* TICCrr */
6019 IntRegs, IntRegs, CCOp,
6020 /* TLS_ADDrr */
6021 IntRegs, IntRegs, IntRegs, TailRelocSymTLSAdd,
6022 /* TLS_CALL */
6023 calltarget, TailRelocSymTLSCall,
6024 /* TLS_LDXrr */
6025 IntRegs, -1, -1, TailRelocSymTLSLoad,
6026 /* TLS_LDrr */
6027 IntRegs, -1, -1, TailRelocSymTLSLoad,
6028 /* TRAPri */
6029 IntRegs, i32imm, CCOp,
6030 /* TRAPrr */
6031 IntRegs, IntRegs, CCOp,
6032 /* TSUBCCTVri */
6033 IntRegs, IntRegs, simm13Op,
6034 /* TSUBCCTVrr */
6035 IntRegs, IntRegs, IntRegs,
6036 /* TSUBCCri */
6037 IntRegs, IntRegs, simm13Op,
6038 /* TSUBCCrr */
6039 IntRegs, IntRegs, IntRegs,
6040 /* TXCCri */
6041 IntRegs, i32imm, CCOp,
6042 /* TXCCrr */
6043 IntRegs, IntRegs, CCOp,
6044 /* UDIVCCri */
6045 IntRegs, IntRegs, simm13Op,
6046 /* UDIVCCrr */
6047 IntRegs, IntRegs, IntRegs,
6048 /* UDIVXri */
6049 IntRegs, IntRegs, i64imm,
6050 /* UDIVXrr */
6051 I64Regs, I64Regs, I64Regs,
6052 /* UDIVri */
6053 IntRegs, IntRegs, simm13Op,
6054 /* UDIVrr */
6055 IntRegs, IntRegs, IntRegs,
6056 /* UMACri */
6057 IntRegs, IntRegs, simm13Op, ASRRegs,
6058 /* UMACrr */
6059 IntRegs, IntRegs, IntRegs, ASRRegs,
6060 /* UMULCCri */
6061 IntRegs, IntRegs, simm13Op,
6062 /* UMULCCrr */
6063 IntRegs, IntRegs, IntRegs,
6064 /* UMULXHI */
6065 I64Regs, I64Regs, I64Regs,
6066 /* UMULri */
6067 IntRegs, IntRegs, simm13Op,
6068 /* UMULrr */
6069 IntRegs, IntRegs, IntRegs,
6070 /* UNIMP */
6071 i32imm,
6072 /* V9FCMPD */
6073 FCCRegs, DFPRegs, DFPRegs,
6074 /* V9FCMPED */
6075 FCCRegs, DFPRegs, DFPRegs,
6076 /* V9FCMPEQ */
6077 FCCRegs, QFPRegs, QFPRegs,
6078 /* V9FCMPES */
6079 FCCRegs, FPRegs, FPRegs,
6080 /* V9FCMPQ */
6081 FCCRegs, QFPRegs, QFPRegs,
6082 /* V9FCMPS */
6083 FCCRegs, FPRegs, FPRegs,
6084 /* V9FMOVD_FCC */
6085 DFPRegs, FCCRegs, DFPRegs, DFPRegs, CCOp,
6086 /* V9FMOVQ_FCC */
6087 QFPRegs, FCCRegs, QFPRegs, QFPRegs, CCOp,
6088 /* V9FMOVS_FCC */
6089 FPRegs, FCCRegs, FPRegs, FPRegs, CCOp,
6090 /* V9MOVFCCri */
6091 IntRegs, FCCRegs, i32imm, IntRegs, CCOp,
6092 /* V9MOVFCCrr */
6093 IntRegs, FCCRegs, IntRegs, IntRegs, CCOp,
6094 /* WRASRri */
6095 ASRRegs, IntRegs, simm13Op,
6096 /* WRASRrr */
6097 ASRRegs, IntRegs, IntRegs,
6098 /* WRPRri */
6099 PRRegs, IntRegs, simm13Op,
6100 /* WRPRrr */
6101 PRRegs, IntRegs, IntRegs,
6102 /* WRPSRri */
6103 IntRegs, simm13Op,
6104 /* WRPSRrr */
6105 IntRegs, IntRegs,
6106 /* WRTBRri */
6107 IntRegs, simm13Op,
6108 /* WRTBRrr */
6109 IntRegs, IntRegs,
6110 /* WRWIMri */
6111 IntRegs, simm13Op,
6112 /* WRWIMrr */
6113 IntRegs, IntRegs,
6114 /* XMULX */
6115 I64Regs, I64Regs, I64Regs,
6116 /* XMULXHI */
6117 I64Regs, I64Regs, I64Regs,
6118 /* XNORCCri */
6119 IntRegs, IntRegs, simm13Op,
6120 /* XNORCCrr */
6121 IntRegs, IntRegs, IntRegs,
6122 /* XNORri */
6123 IntRegs, IntRegs, simm13Op,
6124 /* XNORrr */
6125 IntRegs, IntRegs, IntRegs,
6126 /* XORCCri */
6127 IntRegs, IntRegs, simm13Op,
6128 /* XORCCrr */
6129 IntRegs, IntRegs, IntRegs,
6130 /* XORri */
6131 IntRegs, IntRegs, simm13Op,
6132 /* XORrr */
6133 IntRegs, IntRegs, IntRegs,
6134 };
6135 return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
6136}
6137} // end namespace SP
6138} // end namespace llvm
6139#endif // GET_INSTRINFO_OPERAND_TYPE
6140
6141#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
6142#undef GET_INSTRINFO_MEM_OPERAND_SIZE
6143namespace llvm {
6144namespace SP {
6145LLVM_READONLY
6146static int getMemOperandSize(int OpType) {
6147 switch (OpType) {
6148 default: return 0;
6149 }
6150}
6151} // end namespace SP
6152} // end namespace llvm
6153#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
6154
6155#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
6156#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
6157namespace llvm {
6158namespace Sparc {
6159LLVM_READONLY static unsigned
6160getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
6161 return LogicalOpIdx;
6162}
6163LLVM_READONLY static inline unsigned
6164getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
6165 auto S = 0U;
6166 for (auto i = 0U; i < LogicalOpIdx; ++i)
6167 S += getLogicalOperandSize(Opcode, i);
6168 return S;
6169}
6170} // end namespace Sparc
6171} // end namespace llvm
6172#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
6173
6174#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
6175#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
6176namespace llvm {
6177namespace Sparc {
6178LLVM_READONLY static int
6179getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
6180 return -1;
6181}
6182} // end namespace Sparc
6183} // end namespace llvm
6184#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
6185
6186#ifdef GET_INSTRINFO_MC_HELPER_DECLS
6187#undef GET_INSTRINFO_MC_HELPER_DECLS
6188
6189namespace llvm {
6190class MCInst;
6191class FeatureBitset;
6192
6193namespace Sparc_MC {
6194
6195void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
6196
6197} // end namespace Sparc_MC
6198} // end namespace llvm
6199
6200#endif // GET_INSTRINFO_MC_HELPER_DECLS
6201
6202#ifdef GET_INSTRINFO_MC_HELPERS
6203#undef GET_INSTRINFO_MC_HELPERS
6204
6205namespace llvm {
6206namespace Sparc_MC {
6207
6208} // end namespace Sparc_MC
6209} // end namespace llvm
6210
6211#endif // GET_GENISTRINFO_MC_HELPERS
6212
6213#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
6214 defined(GET_AVAILABLE_OPCODE_CHECKER)
6215#define GET_COMPUTE_FEATURES
6216#endif
6217#ifdef GET_COMPUTE_FEATURES
6218#undef GET_COMPUTE_FEATURES
6219namespace llvm {
6220namespace Sparc_MC {
6221
6222// Bits for subtarget features that participate in instruction matching.
6223enum SubtargetFeatureBits : uint8_t {
6224 Feature_UseSoftMulDivBit = 6,
6225 Feature_HasV9Bit = 2,
6226 Feature_HasVISBit = 3,
6227 Feature_HasVIS2Bit = 4,
6228 Feature_HasVIS3Bit = 5,
6229 Feature_HasCASABit = 0,
6230 Feature_HasPWRPSRBit = 1,
6231};
6232
6233inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
6234 FeatureBitset Features;
6235 if (FB[Sparc::FeatureSoftMulDiv])
6236 Features.set(Feature_UseSoftMulDivBit);
6237 if (FB[Sparc::FeatureV9])
6238 Features.set(Feature_HasV9Bit);
6239 if (FB[Sparc::FeatureVIS])
6240 Features.set(Feature_HasVISBit);
6241 if (FB[Sparc::FeatureVIS2])
6242 Features.set(Feature_HasVIS2Bit);
6243 if (FB[Sparc::FeatureVIS3])
6244 Features.set(Feature_HasVIS3Bit);
6245 if (FB[Sparc::LeonCASA] || FB[Sparc::FeatureV9])
6246 Features.set(Feature_HasCASABit);
6247 if (FB[Sparc::FeaturePWRPSR])
6248 Features.set(Feature_HasPWRPSRBit);
6249 return Features;
6250}
6251
6252inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
6253 enum : uint8_t {
6254 CEFBS_None,
6255 CEFBS_HasCASA,
6256 CEFBS_HasPWRPSR,
6257 CEFBS_HasV9,
6258 CEFBS_HasVIS,
6259 CEFBS_HasVIS2,
6260 CEFBS_HasVIS3,
6261 };
6262
6263 static constexpr FeatureBitset FeatureBitsets[] = {
6264 {}, // CEFBS_None
6265 {Feature_HasCASABit, },
6266 {Feature_HasPWRPSRBit, },
6267 {Feature_HasV9Bit, },
6268 {Feature_HasVISBit, },
6269 {Feature_HasVIS2Bit, },
6270 {Feature_HasVIS3Bit, },
6271 };
6272 static constexpr uint8_t RequiredFeaturesRefs[] = {
6273 CEFBS_None, // PHI = 0
6274 CEFBS_None, // INLINEASM = 1
6275 CEFBS_None, // INLINEASM_BR = 2
6276 CEFBS_None, // CFI_INSTRUCTION = 3
6277 CEFBS_None, // EH_LABEL = 4
6278 CEFBS_None, // GC_LABEL = 5
6279 CEFBS_None, // ANNOTATION_LABEL = 6
6280 CEFBS_None, // KILL = 7
6281 CEFBS_None, // EXTRACT_SUBREG = 8
6282 CEFBS_None, // INSERT_SUBREG = 9
6283 CEFBS_None, // IMPLICIT_DEF = 10
6284 CEFBS_None, // SUBREG_TO_REG = 11
6285 CEFBS_None, // COPY_TO_REGCLASS = 12
6286 CEFBS_None, // DBG_VALUE = 13
6287 CEFBS_None, // DBG_VALUE_LIST = 14
6288 CEFBS_None, // DBG_INSTR_REF = 15
6289 CEFBS_None, // DBG_PHI = 16
6290 CEFBS_None, // DBG_LABEL = 17
6291 CEFBS_None, // REG_SEQUENCE = 18
6292 CEFBS_None, // COPY = 19
6293 CEFBS_None, // BUNDLE = 20
6294 CEFBS_None, // LIFETIME_START = 21
6295 CEFBS_None, // LIFETIME_END = 22
6296 CEFBS_None, // PSEUDO_PROBE = 23
6297 CEFBS_None, // ARITH_FENCE = 24
6298 CEFBS_None, // STACKMAP = 25
6299 CEFBS_None, // FENTRY_CALL = 26
6300 CEFBS_None, // PATCHPOINT = 27
6301 CEFBS_None, // LOAD_STACK_GUARD = 28
6302 CEFBS_None, // PREALLOCATED_SETUP = 29
6303 CEFBS_None, // PREALLOCATED_ARG = 30
6304 CEFBS_None, // STATEPOINT = 31
6305 CEFBS_None, // LOCAL_ESCAPE = 32
6306 CEFBS_None, // FAULTING_OP = 33
6307 CEFBS_None, // PATCHABLE_OP = 34
6308 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
6309 CEFBS_None, // PATCHABLE_RET = 36
6310 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
6311 CEFBS_None, // PATCHABLE_TAIL_CALL = 38
6312 CEFBS_None, // PATCHABLE_EVENT_CALL = 39
6313 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
6314 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
6315 CEFBS_None, // MEMBARRIER = 42
6316 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
6317 CEFBS_None, // CONVERGENCECTRL_ENTRY = 44
6318 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 45
6319 CEFBS_None, // CONVERGENCECTRL_LOOP = 46
6320 CEFBS_None, // CONVERGENCECTRL_GLUE = 47
6321 CEFBS_None, // G_ASSERT_SEXT = 48
6322 CEFBS_None, // G_ASSERT_ZEXT = 49
6323 CEFBS_None, // G_ASSERT_ALIGN = 50
6324 CEFBS_None, // G_ADD = 51
6325 CEFBS_None, // G_SUB = 52
6326 CEFBS_None, // G_MUL = 53
6327 CEFBS_None, // G_SDIV = 54
6328 CEFBS_None, // G_UDIV = 55
6329 CEFBS_None, // G_SREM = 56
6330 CEFBS_None, // G_UREM = 57
6331 CEFBS_None, // G_SDIVREM = 58
6332 CEFBS_None, // G_UDIVREM = 59
6333 CEFBS_None, // G_AND = 60
6334 CEFBS_None, // G_OR = 61
6335 CEFBS_None, // G_XOR = 62
6336 CEFBS_None, // G_IMPLICIT_DEF = 63
6337 CEFBS_None, // G_PHI = 64
6338 CEFBS_None, // G_FRAME_INDEX = 65
6339 CEFBS_None, // G_GLOBAL_VALUE = 66
6340 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 67
6341 CEFBS_None, // G_CONSTANT_POOL = 68
6342 CEFBS_None, // G_EXTRACT = 69
6343 CEFBS_None, // G_UNMERGE_VALUES = 70
6344 CEFBS_None, // G_INSERT = 71
6345 CEFBS_None, // G_MERGE_VALUES = 72
6346 CEFBS_None, // G_BUILD_VECTOR = 73
6347 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 74
6348 CEFBS_None, // G_CONCAT_VECTORS = 75
6349 CEFBS_None, // G_PTRTOINT = 76
6350 CEFBS_None, // G_INTTOPTR = 77
6351 CEFBS_None, // G_BITCAST = 78
6352 CEFBS_None, // G_FREEZE = 79
6353 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 80
6354 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 81
6355 CEFBS_None, // G_INTRINSIC_TRUNC = 82
6356 CEFBS_None, // G_INTRINSIC_ROUND = 83
6357 CEFBS_None, // G_INTRINSIC_LRINT = 84
6358 CEFBS_None, // G_INTRINSIC_LLRINT = 85
6359 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 86
6360 CEFBS_None, // G_READCYCLECOUNTER = 87
6361 CEFBS_None, // G_READSTEADYCOUNTER = 88
6362 CEFBS_None, // G_LOAD = 89
6363 CEFBS_None, // G_SEXTLOAD = 90
6364 CEFBS_None, // G_ZEXTLOAD = 91
6365 CEFBS_None, // G_INDEXED_LOAD = 92
6366 CEFBS_None, // G_INDEXED_SEXTLOAD = 93
6367 CEFBS_None, // G_INDEXED_ZEXTLOAD = 94
6368 CEFBS_None, // G_STORE = 95
6369 CEFBS_None, // G_INDEXED_STORE = 96
6370 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97
6371 CEFBS_None, // G_ATOMIC_CMPXCHG = 98
6372 CEFBS_None, // G_ATOMICRMW_XCHG = 99
6373 CEFBS_None, // G_ATOMICRMW_ADD = 100
6374 CEFBS_None, // G_ATOMICRMW_SUB = 101
6375 CEFBS_None, // G_ATOMICRMW_AND = 102
6376 CEFBS_None, // G_ATOMICRMW_NAND = 103
6377 CEFBS_None, // G_ATOMICRMW_OR = 104
6378 CEFBS_None, // G_ATOMICRMW_XOR = 105
6379 CEFBS_None, // G_ATOMICRMW_MAX = 106
6380 CEFBS_None, // G_ATOMICRMW_MIN = 107
6381 CEFBS_None, // G_ATOMICRMW_UMAX = 108
6382 CEFBS_None, // G_ATOMICRMW_UMIN = 109
6383 CEFBS_None, // G_ATOMICRMW_FADD = 110
6384 CEFBS_None, // G_ATOMICRMW_FSUB = 111
6385 CEFBS_None, // G_ATOMICRMW_FMAX = 112
6386 CEFBS_None, // G_ATOMICRMW_FMIN = 113
6387 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 114
6388 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 115
6389 CEFBS_None, // G_FENCE = 116
6390 CEFBS_None, // G_PREFETCH = 117
6391 CEFBS_None, // G_BRCOND = 118
6392 CEFBS_None, // G_BRINDIRECT = 119
6393 CEFBS_None, // G_INVOKE_REGION_START = 120
6394 CEFBS_None, // G_INTRINSIC = 121
6395 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 122
6396 CEFBS_None, // G_INTRINSIC_CONVERGENT = 123
6397 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124
6398 CEFBS_None, // G_ANYEXT = 125
6399 CEFBS_None, // G_TRUNC = 126
6400 CEFBS_None, // G_CONSTANT = 127
6401 CEFBS_None, // G_FCONSTANT = 128
6402 CEFBS_None, // G_VASTART = 129
6403 CEFBS_None, // G_VAARG = 130
6404 CEFBS_None, // G_SEXT = 131
6405 CEFBS_None, // G_SEXT_INREG = 132
6406 CEFBS_None, // G_ZEXT = 133
6407 CEFBS_None, // G_SHL = 134
6408 CEFBS_None, // G_LSHR = 135
6409 CEFBS_None, // G_ASHR = 136
6410 CEFBS_None, // G_FSHL = 137
6411 CEFBS_None, // G_FSHR = 138
6412 CEFBS_None, // G_ROTR = 139
6413 CEFBS_None, // G_ROTL = 140
6414 CEFBS_None, // G_ICMP = 141
6415 CEFBS_None, // G_FCMP = 142
6416 CEFBS_None, // G_SCMP = 143
6417 CEFBS_None, // G_UCMP = 144
6418 CEFBS_None, // G_SELECT = 145
6419 CEFBS_None, // G_UADDO = 146
6420 CEFBS_None, // G_UADDE = 147
6421 CEFBS_None, // G_USUBO = 148
6422 CEFBS_None, // G_USUBE = 149
6423 CEFBS_None, // G_SADDO = 150
6424 CEFBS_None, // G_SADDE = 151
6425 CEFBS_None, // G_SSUBO = 152
6426 CEFBS_None, // G_SSUBE = 153
6427 CEFBS_None, // G_UMULO = 154
6428 CEFBS_None, // G_SMULO = 155
6429 CEFBS_None, // G_UMULH = 156
6430 CEFBS_None, // G_SMULH = 157
6431 CEFBS_None, // G_UADDSAT = 158
6432 CEFBS_None, // G_SADDSAT = 159
6433 CEFBS_None, // G_USUBSAT = 160
6434 CEFBS_None, // G_SSUBSAT = 161
6435 CEFBS_None, // G_USHLSAT = 162
6436 CEFBS_None, // G_SSHLSAT = 163
6437 CEFBS_None, // G_SMULFIX = 164
6438 CEFBS_None, // G_UMULFIX = 165
6439 CEFBS_None, // G_SMULFIXSAT = 166
6440 CEFBS_None, // G_UMULFIXSAT = 167
6441 CEFBS_None, // G_SDIVFIX = 168
6442 CEFBS_None, // G_UDIVFIX = 169
6443 CEFBS_None, // G_SDIVFIXSAT = 170
6444 CEFBS_None, // G_UDIVFIXSAT = 171
6445 CEFBS_None, // G_FADD = 172
6446 CEFBS_None, // G_FSUB = 173
6447 CEFBS_None, // G_FMUL = 174
6448 CEFBS_None, // G_FMA = 175
6449 CEFBS_None, // G_FMAD = 176
6450 CEFBS_None, // G_FDIV = 177
6451 CEFBS_None, // G_FREM = 178
6452 CEFBS_None, // G_FPOW = 179
6453 CEFBS_None, // G_FPOWI = 180
6454 CEFBS_None, // G_FEXP = 181
6455 CEFBS_None, // G_FEXP2 = 182
6456 CEFBS_None, // G_FEXP10 = 183
6457 CEFBS_None, // G_FLOG = 184
6458 CEFBS_None, // G_FLOG2 = 185
6459 CEFBS_None, // G_FLOG10 = 186
6460 CEFBS_None, // G_FLDEXP = 187
6461 CEFBS_None, // G_FFREXP = 188
6462 CEFBS_None, // G_FNEG = 189
6463 CEFBS_None, // G_FPEXT = 190
6464 CEFBS_None, // G_FPTRUNC = 191
6465 CEFBS_None, // G_FPTOSI = 192
6466 CEFBS_None, // G_FPTOUI = 193
6467 CEFBS_None, // G_SITOFP = 194
6468 CEFBS_None, // G_UITOFP = 195
6469 CEFBS_None, // G_FABS = 196
6470 CEFBS_None, // G_FCOPYSIGN = 197
6471 CEFBS_None, // G_IS_FPCLASS = 198
6472 CEFBS_None, // G_FCANONICALIZE = 199
6473 CEFBS_None, // G_FMINNUM = 200
6474 CEFBS_None, // G_FMAXNUM = 201
6475 CEFBS_None, // G_FMINNUM_IEEE = 202
6476 CEFBS_None, // G_FMAXNUM_IEEE = 203
6477 CEFBS_None, // G_FMINIMUM = 204
6478 CEFBS_None, // G_FMAXIMUM = 205
6479 CEFBS_None, // G_GET_FPENV = 206
6480 CEFBS_None, // G_SET_FPENV = 207
6481 CEFBS_None, // G_RESET_FPENV = 208
6482 CEFBS_None, // G_GET_FPMODE = 209
6483 CEFBS_None, // G_SET_FPMODE = 210
6484 CEFBS_None, // G_RESET_FPMODE = 211
6485 CEFBS_None, // G_PTR_ADD = 212
6486 CEFBS_None, // G_PTRMASK = 213
6487 CEFBS_None, // G_SMIN = 214
6488 CEFBS_None, // G_SMAX = 215
6489 CEFBS_None, // G_UMIN = 216
6490 CEFBS_None, // G_UMAX = 217
6491 CEFBS_None, // G_ABS = 218
6492 CEFBS_None, // G_LROUND = 219
6493 CEFBS_None, // G_LLROUND = 220
6494 CEFBS_None, // G_BR = 221
6495 CEFBS_None, // G_BRJT = 222
6496 CEFBS_None, // G_VSCALE = 223
6497 CEFBS_None, // G_INSERT_SUBVECTOR = 224
6498 CEFBS_None, // G_EXTRACT_SUBVECTOR = 225
6499 CEFBS_None, // G_INSERT_VECTOR_ELT = 226
6500 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 227
6501 CEFBS_None, // G_SHUFFLE_VECTOR = 228
6502 CEFBS_None, // G_SPLAT_VECTOR = 229
6503 CEFBS_None, // G_VECTOR_COMPRESS = 230
6504 CEFBS_None, // G_CTTZ = 231
6505 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 232
6506 CEFBS_None, // G_CTLZ = 233
6507 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 234
6508 CEFBS_None, // G_CTPOP = 235
6509 CEFBS_None, // G_BSWAP = 236
6510 CEFBS_None, // G_BITREVERSE = 237
6511 CEFBS_None, // G_FCEIL = 238
6512 CEFBS_None, // G_FCOS = 239
6513 CEFBS_None, // G_FSIN = 240
6514 CEFBS_None, // G_FTAN = 241
6515 CEFBS_None, // G_FACOS = 242
6516 CEFBS_None, // G_FASIN = 243
6517 CEFBS_None, // G_FATAN = 244
6518 CEFBS_None, // G_FCOSH = 245
6519 CEFBS_None, // G_FSINH = 246
6520 CEFBS_None, // G_FTANH = 247
6521 CEFBS_None, // G_FSQRT = 248
6522 CEFBS_None, // G_FFLOOR = 249
6523 CEFBS_None, // G_FRINT = 250
6524 CEFBS_None, // G_FNEARBYINT = 251
6525 CEFBS_None, // G_ADDRSPACE_CAST = 252
6526 CEFBS_None, // G_BLOCK_ADDR = 253
6527 CEFBS_None, // G_JUMP_TABLE = 254
6528 CEFBS_None, // G_DYN_STACKALLOC = 255
6529 CEFBS_None, // G_STACKSAVE = 256
6530 CEFBS_None, // G_STACKRESTORE = 257
6531 CEFBS_None, // G_STRICT_FADD = 258
6532 CEFBS_None, // G_STRICT_FSUB = 259
6533 CEFBS_None, // G_STRICT_FMUL = 260
6534 CEFBS_None, // G_STRICT_FDIV = 261
6535 CEFBS_None, // G_STRICT_FREM = 262
6536 CEFBS_None, // G_STRICT_FMA = 263
6537 CEFBS_None, // G_STRICT_FSQRT = 264
6538 CEFBS_None, // G_STRICT_FLDEXP = 265
6539 CEFBS_None, // G_READ_REGISTER = 266
6540 CEFBS_None, // G_WRITE_REGISTER = 267
6541 CEFBS_None, // G_MEMCPY = 268
6542 CEFBS_None, // G_MEMCPY_INLINE = 269
6543 CEFBS_None, // G_MEMMOVE = 270
6544 CEFBS_None, // G_MEMSET = 271
6545 CEFBS_None, // G_BZERO = 272
6546 CEFBS_None, // G_TRAP = 273
6547 CEFBS_None, // G_DEBUGTRAP = 274
6548 CEFBS_None, // G_UBSANTRAP = 275
6549 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 276
6550 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 277
6551 CEFBS_None, // G_VECREDUCE_FADD = 278
6552 CEFBS_None, // G_VECREDUCE_FMUL = 279
6553 CEFBS_None, // G_VECREDUCE_FMAX = 280
6554 CEFBS_None, // G_VECREDUCE_FMIN = 281
6555 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 282
6556 CEFBS_None, // G_VECREDUCE_FMINIMUM = 283
6557 CEFBS_None, // G_VECREDUCE_ADD = 284
6558 CEFBS_None, // G_VECREDUCE_MUL = 285
6559 CEFBS_None, // G_VECREDUCE_AND = 286
6560 CEFBS_None, // G_VECREDUCE_OR = 287
6561 CEFBS_None, // G_VECREDUCE_XOR = 288
6562 CEFBS_None, // G_VECREDUCE_SMAX = 289
6563 CEFBS_None, // G_VECREDUCE_SMIN = 290
6564 CEFBS_None, // G_VECREDUCE_UMAX = 291
6565 CEFBS_None, // G_VECREDUCE_UMIN = 292
6566 CEFBS_None, // G_SBFX = 293
6567 CEFBS_None, // G_UBFX = 294
6568 CEFBS_None, // ADJCALLSTACKDOWN = 295
6569 CEFBS_None, // ADJCALLSTACKUP = 296
6570 CEFBS_None, // GETPCX = 297
6571 CEFBS_None, // SELECT_CC_DFP_FCC = 298
6572 CEFBS_None, // SELECT_CC_DFP_ICC = 299
6573 CEFBS_None, // SELECT_CC_DFP_XCC = 300
6574 CEFBS_None, // SELECT_CC_FP_FCC = 301
6575 CEFBS_None, // SELECT_CC_FP_ICC = 302
6576 CEFBS_None, // SELECT_CC_FP_XCC = 303
6577 CEFBS_None, // SELECT_CC_Int_FCC = 304
6578 CEFBS_None, // SELECT_CC_Int_ICC = 305
6579 CEFBS_None, // SELECT_CC_Int_XCC = 306
6580 CEFBS_None, // SELECT_CC_QFP_FCC = 307
6581 CEFBS_None, // SELECT_CC_QFP_ICC = 308
6582 CEFBS_None, // SELECT_CC_QFP_XCC = 309
6583 CEFBS_None, // SET = 310
6584 CEFBS_HasV9, // SETX = 311
6585 CEFBS_None, // ADDCCri = 312
6586 CEFBS_None, // ADDCCrr = 313
6587 CEFBS_None, // ADDCri = 314
6588 CEFBS_None, // ADDCrr = 315
6589 CEFBS_None, // ADDEri = 316
6590 CEFBS_None, // ADDErr = 317
6591 CEFBS_HasVIS3, // ADDXC = 318
6592 CEFBS_HasVIS3, // ADDXCCC = 319
6593 CEFBS_None, // ADDri = 320
6594 CEFBS_None, // ADDrr = 321
6595 CEFBS_HasVIS, // ALIGNADDR = 322
6596 CEFBS_HasVIS, // ALIGNADDRL = 323
6597 CEFBS_None, // ANDCCri = 324
6598 CEFBS_None, // ANDCCrr = 325
6599 CEFBS_None, // ANDNCCri = 326
6600 CEFBS_None, // ANDNCCrr = 327
6601 CEFBS_None, // ANDNri = 328
6602 CEFBS_None, // ANDNrr = 329
6603 CEFBS_None, // ANDri = 330
6604 CEFBS_None, // ANDrr = 331
6605 CEFBS_HasVIS, // ARRAY16 = 332
6606 CEFBS_HasVIS, // ARRAY32 = 333
6607 CEFBS_HasVIS, // ARRAY8 = 334
6608 CEFBS_None, // BA = 335
6609 CEFBS_None, // BCOND = 336
6610 CEFBS_None, // BCONDA = 337
6611 CEFBS_None, // BINDri = 338
6612 CEFBS_None, // BINDrr = 339
6613 CEFBS_HasVIS2, // BMASK = 340
6614 CEFBS_HasV9, // BPFCC = 341
6615 CEFBS_HasV9, // BPFCCA = 342
6616 CEFBS_HasV9, // BPFCCANT = 343
6617 CEFBS_HasV9, // BPFCCNT = 344
6618 CEFBS_HasV9, // BPICC = 345
6619 CEFBS_HasV9, // BPICCA = 346
6620 CEFBS_HasV9, // BPICCANT = 347
6621 CEFBS_HasV9, // BPICCNT = 348
6622 CEFBS_None, // BPR = 349
6623 CEFBS_None, // BPRA = 350
6624 CEFBS_None, // BPRANT = 351
6625 CEFBS_None, // BPRNT = 352
6626 CEFBS_None, // BPXCC = 353
6627 CEFBS_None, // BPXCCA = 354
6628 CEFBS_None, // BPXCCANT = 355
6629 CEFBS_None, // BPXCCNT = 356
6630 CEFBS_HasVIS2, // BSHUFFLE = 357
6631 CEFBS_None, // CALL = 358
6632 CEFBS_None, // CALLri = 359
6633 CEFBS_None, // CALLrr = 360
6634 CEFBS_HasV9, // CASAri = 361
6635 CEFBS_HasCASA, // CASArr = 362
6636 CEFBS_HasV9, // CASXAri = 363
6637 CEFBS_HasV9, // CASXArr = 364
6638 CEFBS_None, // CBCOND = 365
6639 CEFBS_None, // CBCONDA = 366
6640 CEFBS_HasVIS3, // CMASK16 = 367
6641 CEFBS_HasVIS3, // CMASK32 = 368
6642 CEFBS_HasVIS3, // CMASK8 = 369
6643 CEFBS_HasV9, // DONE = 370
6644 CEFBS_HasVIS, // EDGE16 = 371
6645 CEFBS_HasVIS, // EDGE16L = 372
6646 CEFBS_HasVIS2, // EDGE16LN = 373
6647 CEFBS_HasVIS2, // EDGE16N = 374
6648 CEFBS_HasVIS, // EDGE32 = 375
6649 CEFBS_HasVIS, // EDGE32L = 376
6650 CEFBS_HasVIS2, // EDGE32LN = 377
6651 CEFBS_HasVIS2, // EDGE32N = 378
6652 CEFBS_HasVIS, // EDGE8 = 379
6653 CEFBS_HasVIS, // EDGE8L = 380
6654 CEFBS_HasVIS2, // EDGE8LN = 381
6655 CEFBS_HasVIS2, // EDGE8N = 382
6656 CEFBS_HasV9, // FABSD = 383
6657 CEFBS_HasV9, // FABSQ = 384
6658 CEFBS_None, // FABSS = 385
6659 CEFBS_None, // FADDD = 386
6660 CEFBS_None, // FADDQ = 387
6661 CEFBS_None, // FADDS = 388
6662 CEFBS_HasVIS, // FALIGNADATA = 389
6663 CEFBS_HasVIS, // FAND = 390
6664 CEFBS_HasVIS, // FANDNOT1 = 391
6665 CEFBS_HasVIS, // FANDNOT1S = 392
6666 CEFBS_HasVIS, // FANDNOT2 = 393
6667 CEFBS_HasVIS, // FANDNOT2S = 394
6668 CEFBS_HasVIS, // FANDS = 395
6669 CEFBS_None, // FBCOND = 396
6670 CEFBS_None, // FBCONDA = 397
6671 CEFBS_HasV9, // FBCONDA_V9 = 398
6672 CEFBS_HasV9, // FBCOND_V9 = 399
6673 CEFBS_HasVIS3, // FCHKSM16 = 400
6674 CEFBS_None, // FCMPD = 401
6675 CEFBS_HasV9, // FCMPD_V9 = 402
6676 CEFBS_HasVIS, // FCMPEQ16 = 403
6677 CEFBS_HasVIS, // FCMPEQ32 = 404
6678 CEFBS_HasVIS, // FCMPGT16 = 405
6679 CEFBS_HasVIS, // FCMPGT32 = 406
6680 CEFBS_HasVIS, // FCMPLE16 = 407
6681 CEFBS_HasVIS, // FCMPLE32 = 408
6682 CEFBS_HasVIS, // FCMPNE16 = 409
6683 CEFBS_HasVIS, // FCMPNE32 = 410
6684 CEFBS_None, // FCMPQ = 411
6685 CEFBS_HasV9, // FCMPQ_V9 = 412
6686 CEFBS_None, // FCMPS = 413
6687 CEFBS_HasV9, // FCMPS_V9 = 414
6688 CEFBS_None, // FDIVD = 415
6689 CEFBS_None, // FDIVQ = 416
6690 CEFBS_None, // FDIVS = 417
6691 CEFBS_None, // FDMULQ = 418
6692 CEFBS_None, // FDTOI = 419
6693 CEFBS_None, // FDTOQ = 420
6694 CEFBS_None, // FDTOS = 421
6695 CEFBS_None, // FDTOX = 422
6696 CEFBS_HasVIS, // FEXPAND = 423
6697 CEFBS_HasVIS3, // FHADDD = 424
6698 CEFBS_HasVIS3, // FHADDS = 425
6699 CEFBS_HasVIS3, // FHSUBD = 426
6700 CEFBS_HasVIS3, // FHSUBS = 427
6701 CEFBS_None, // FITOD = 428
6702 CEFBS_None, // FITOQ = 429
6703 CEFBS_None, // FITOS = 430
6704 CEFBS_HasVIS3, // FLCMPD = 431
6705 CEFBS_HasVIS3, // FLCMPS = 432
6706 CEFBS_None, // FLUSH = 433
6707 CEFBS_HasV9, // FLUSHW = 434
6708 CEFBS_None, // FLUSHri = 435
6709 CEFBS_None, // FLUSHrr = 436
6710 CEFBS_HasVIS3, // FMEAN16 = 437
6711 CEFBS_HasV9, // FMOVD = 438
6712 CEFBS_HasV9, // FMOVD_FCC = 439
6713 CEFBS_HasV9, // FMOVD_ICC = 440
6714 CEFBS_None, // FMOVD_XCC = 441
6715 CEFBS_HasV9, // FMOVQ = 442
6716 CEFBS_HasV9, // FMOVQ_FCC = 443
6717 CEFBS_HasV9, // FMOVQ_ICC = 444
6718 CEFBS_None, // FMOVQ_XCC = 445
6719 CEFBS_None, // FMOVRD = 446
6720 CEFBS_None, // FMOVRQ = 447
6721 CEFBS_None, // FMOVRS = 448
6722 CEFBS_None, // FMOVS = 449
6723 CEFBS_HasV9, // FMOVS_FCC = 450
6724 CEFBS_HasV9, // FMOVS_ICC = 451
6725 CEFBS_None, // FMOVS_XCC = 452
6726 CEFBS_HasVIS, // FMUL8SUX16 = 453
6727 CEFBS_HasVIS, // FMUL8ULX16 = 454
6728 CEFBS_HasVIS, // FMUL8X16 = 455
6729 CEFBS_HasVIS, // FMUL8X16AL = 456
6730 CEFBS_HasVIS, // FMUL8X16AU = 457
6731 CEFBS_None, // FMULD = 458
6732 CEFBS_HasVIS, // FMULD8SUX16 = 459
6733 CEFBS_HasVIS, // FMULD8ULX16 = 460
6734 CEFBS_None, // FMULQ = 461
6735 CEFBS_None, // FMULS = 462
6736 CEFBS_HasVIS3, // FNADDD = 463
6737 CEFBS_HasVIS3, // FNADDS = 464
6738 CEFBS_HasVIS, // FNAND = 465
6739 CEFBS_HasVIS, // FNANDS = 466
6740 CEFBS_HasV9, // FNEGD = 467
6741 CEFBS_HasV9, // FNEGQ = 468
6742 CEFBS_None, // FNEGS = 469
6743 CEFBS_HasVIS3, // FNHADDD = 470
6744 CEFBS_HasVIS3, // FNHADDS = 471
6745 CEFBS_HasVIS3, // FNMULD = 472
6746 CEFBS_HasVIS3, // FNMULS = 473
6747 CEFBS_HasVIS, // FNOR = 474
6748 CEFBS_HasVIS, // FNORS = 475
6749 CEFBS_HasVIS, // FNOT1 = 476
6750 CEFBS_HasVIS, // FNOT1S = 477
6751 CEFBS_HasVIS, // FNOT2 = 478
6752 CEFBS_HasVIS, // FNOT2S = 479
6753 CEFBS_HasVIS3, // FNSMULD = 480
6754 CEFBS_HasVIS, // FONE = 481
6755 CEFBS_HasVIS, // FONES = 482
6756 CEFBS_HasVIS, // FOR = 483
6757 CEFBS_HasVIS, // FORNOT1 = 484
6758 CEFBS_HasVIS, // FORNOT1S = 485
6759 CEFBS_HasVIS, // FORNOT2 = 486
6760 CEFBS_HasVIS, // FORNOT2S = 487
6761 CEFBS_HasVIS, // FORS = 488
6762 CEFBS_HasVIS, // FPACK16 = 489
6763 CEFBS_HasVIS, // FPACK32 = 490
6764 CEFBS_HasVIS, // FPACKFIX = 491
6765 CEFBS_HasVIS, // FPADD16 = 492
6766 CEFBS_HasVIS, // FPADD16S = 493
6767 CEFBS_HasVIS, // FPADD32 = 494
6768 CEFBS_HasVIS, // FPADD32S = 495
6769 CEFBS_HasVIS3, // FPADD64 = 496
6770 CEFBS_HasVIS, // FPMERGE = 497
6771 CEFBS_HasVIS, // FPSUB16 = 498
6772 CEFBS_HasVIS, // FPSUB16S = 499
6773 CEFBS_HasVIS, // FPSUB32 = 500
6774 CEFBS_HasVIS, // FPSUB32S = 501
6775 CEFBS_None, // FQTOD = 502
6776 CEFBS_None, // FQTOI = 503
6777 CEFBS_None, // FQTOS = 504
6778 CEFBS_None, // FQTOX = 505
6779 CEFBS_HasVIS3, // FSLAS16 = 506
6780 CEFBS_HasVIS3, // FSLAS32 = 507
6781 CEFBS_HasVIS3, // FSLL16 = 508
6782 CEFBS_HasVIS3, // FSLL32 = 509
6783 CEFBS_None, // FSMULD = 510
6784 CEFBS_None, // FSQRTD = 511
6785 CEFBS_None, // FSQRTQ = 512
6786 CEFBS_None, // FSQRTS = 513
6787 CEFBS_HasVIS3, // FSRA16 = 514
6788 CEFBS_HasVIS3, // FSRA32 = 515
6789 CEFBS_HasVIS, // FSRC1 = 516
6790 CEFBS_HasVIS, // FSRC1S = 517
6791 CEFBS_HasVIS, // FSRC2 = 518
6792 CEFBS_HasVIS, // FSRC2S = 519
6793 CEFBS_HasVIS3, // FSRL16 = 520
6794 CEFBS_HasVIS3, // FSRL32 = 521
6795 CEFBS_None, // FSTOD = 522
6796 CEFBS_None, // FSTOI = 523
6797 CEFBS_None, // FSTOQ = 524
6798 CEFBS_None, // FSTOX = 525
6799 CEFBS_None, // FSUBD = 526
6800 CEFBS_None, // FSUBQ = 527
6801 CEFBS_None, // FSUBS = 528
6802 CEFBS_HasVIS, // FXNOR = 529
6803 CEFBS_HasVIS, // FXNORS = 530
6804 CEFBS_HasVIS, // FXOR = 531
6805 CEFBS_HasVIS, // FXORS = 532
6806 CEFBS_None, // FXTOD = 533
6807 CEFBS_None, // FXTOQ = 534
6808 CEFBS_None, // FXTOS = 535
6809 CEFBS_HasVIS, // FZERO = 536
6810 CEFBS_HasVIS, // FZEROS = 537
6811 CEFBS_None, // GDOP_LDXrr = 538
6812 CEFBS_None, // GDOP_LDrr = 539
6813 CEFBS_None, // JMPLri = 540
6814 CEFBS_None, // JMPLrr = 541
6815 CEFBS_HasV9, // LDAri = 542
6816 CEFBS_None, // LDArr = 543
6817 CEFBS_None, // LDCSRri = 544
6818 CEFBS_None, // LDCSRrr = 545
6819 CEFBS_None, // LDCri = 546
6820 CEFBS_None, // LDCrr = 547
6821 CEFBS_HasV9, // LDDAri = 548
6822 CEFBS_None, // LDDArr = 549
6823 CEFBS_None, // LDDCri = 550
6824 CEFBS_None, // LDDCrr = 551
6825 CEFBS_HasV9, // LDDFAri = 552
6826 CEFBS_HasV9, // LDDFArr = 553
6827 CEFBS_None, // LDDFri = 554
6828 CEFBS_None, // LDDFrr = 555
6829 CEFBS_None, // LDDri = 556
6830 CEFBS_None, // LDDrr = 557
6831 CEFBS_HasV9, // LDFAri = 558
6832 CEFBS_HasV9, // LDFArr = 559
6833 CEFBS_None, // LDFSRri = 560
6834 CEFBS_None, // LDFSRrr = 561
6835 CEFBS_None, // LDFri = 562
6836 CEFBS_None, // LDFrr = 563
6837 CEFBS_HasV9, // LDQFAri = 564
6838 CEFBS_HasV9, // LDQFArr = 565
6839 CEFBS_HasV9, // LDQFri = 566
6840 CEFBS_HasV9, // LDQFrr = 567
6841 CEFBS_HasV9, // LDSBAri = 568
6842 CEFBS_None, // LDSBArr = 569
6843 CEFBS_None, // LDSBri = 570
6844 CEFBS_None, // LDSBrr = 571
6845 CEFBS_HasV9, // LDSHAri = 572
6846 CEFBS_None, // LDSHArr = 573
6847 CEFBS_None, // LDSHri = 574
6848 CEFBS_None, // LDSHrr = 575
6849 CEFBS_HasV9, // LDSTUBAri = 576
6850 CEFBS_None, // LDSTUBArr = 577
6851 CEFBS_None, // LDSTUBri = 578
6852 CEFBS_None, // LDSTUBrr = 579
6853 CEFBS_None, // LDSWAri = 580
6854 CEFBS_None, // LDSWArr = 581
6855 CEFBS_None, // LDSWri = 582
6856 CEFBS_None, // LDSWrr = 583
6857 CEFBS_HasV9, // LDUBAri = 584
6858 CEFBS_None, // LDUBArr = 585
6859 CEFBS_None, // LDUBri = 586
6860 CEFBS_None, // LDUBrr = 587
6861 CEFBS_HasV9, // LDUHAri = 588
6862 CEFBS_None, // LDUHArr = 589
6863 CEFBS_None, // LDUHri = 590
6864 CEFBS_None, // LDUHrr = 591
6865 CEFBS_None, // LDXAri = 592
6866 CEFBS_None, // LDXArr = 593
6867 CEFBS_HasV9, // LDXFSRri = 594
6868 CEFBS_HasV9, // LDXFSRrr = 595
6869 CEFBS_None, // LDXri = 596
6870 CEFBS_None, // LDXrr = 597
6871 CEFBS_None, // LDri = 598
6872 CEFBS_None, // LDrr = 599
6873 CEFBS_HasVIS3, // LZCNT = 600
6874 CEFBS_HasV9, // MEMBARi = 601
6875 CEFBS_HasVIS3, // MOVDTOX = 602
6876 CEFBS_HasV9, // MOVFCCri = 603
6877 CEFBS_HasV9, // MOVFCCrr = 604
6878 CEFBS_HasV9, // MOVICCri = 605
6879 CEFBS_HasV9, // MOVICCrr = 606
6880 CEFBS_None, // MOVRri = 607
6881 CEFBS_None, // MOVRrr = 608
6882 CEFBS_HasVIS3, // MOVSTOSW = 609
6883 CEFBS_HasVIS3, // MOVSTOUW = 610
6884 CEFBS_HasVIS3, // MOVWTOS = 611
6885 CEFBS_None, // MOVXCCri = 612
6886 CEFBS_None, // MOVXCCrr = 613
6887 CEFBS_HasVIS3, // MOVXTOD = 614
6888 CEFBS_None, // MULSCCri = 615
6889 CEFBS_None, // MULSCCrr = 616
6890 CEFBS_None, // MULXri = 617
6891 CEFBS_None, // MULXrr = 618
6892 CEFBS_None, // NOP = 619
6893 CEFBS_None, // ORCCri = 620
6894 CEFBS_None, // ORCCrr = 621
6895 CEFBS_None, // ORNCCri = 622
6896 CEFBS_None, // ORNCCrr = 623
6897 CEFBS_None, // ORNri = 624
6898 CEFBS_None, // ORNrr = 625
6899 CEFBS_None, // ORri = 626
6900 CEFBS_None, // ORrr = 627
6901 CEFBS_HasVIS, // PDIST = 628
6902 CEFBS_HasVIS3, // PDISTN = 629
6903 CEFBS_HasV9, // POPCrr = 630
6904 CEFBS_HasV9, // PREFETCHAi = 631
6905 CEFBS_HasV9, // PREFETCHAr = 632
6906 CEFBS_HasV9, // PREFETCHi = 633
6907 CEFBS_HasV9, // PREFETCHr = 634
6908 CEFBS_HasPWRPSR, // PWRPSRri = 635
6909 CEFBS_HasPWRPSR, // PWRPSRrr = 636
6910 CEFBS_None, // RDASR = 637
6911 CEFBS_HasV9, // RDFQ = 638
6912 CEFBS_HasV9, // RDPR = 639
6913 CEFBS_None, // RDPSR = 640
6914 CEFBS_None, // RDTBR = 641
6915 CEFBS_None, // RDWIM = 642
6916 CEFBS_HasV9, // RESTORED = 643
6917 CEFBS_None, // RESTOREri = 644
6918 CEFBS_None, // RESTORErr = 645
6919 CEFBS_None, // RET = 646
6920 CEFBS_None, // RETL = 647
6921 CEFBS_HasV9, // RETRY = 648
6922 CEFBS_None, // RETTri = 649
6923 CEFBS_None, // RETTrr = 650
6924 CEFBS_HasV9, // SAVED = 651
6925 CEFBS_None, // SAVEri = 652
6926 CEFBS_None, // SAVErr = 653
6927 CEFBS_None, // SDIVCCri = 654
6928 CEFBS_None, // SDIVCCrr = 655
6929 CEFBS_None, // SDIVXri = 656
6930 CEFBS_None, // SDIVXrr = 657
6931 CEFBS_None, // SDIVri = 658
6932 CEFBS_None, // SDIVrr = 659
6933 CEFBS_None, // SETHIi = 660
6934 CEFBS_HasVIS, // SHUTDOWN = 661
6935 CEFBS_HasVIS2, // SIAM = 662
6936 CEFBS_HasV9, // SIR = 663
6937 CEFBS_None, // SLLXri = 664
6938 CEFBS_None, // SLLXrr = 665
6939 CEFBS_None, // SLLri = 666
6940 CEFBS_None, // SLLrr = 667
6941 CEFBS_None, // SMACri = 668
6942 CEFBS_None, // SMACrr = 669
6943 CEFBS_None, // SMULCCri = 670
6944 CEFBS_None, // SMULCCrr = 671
6945 CEFBS_None, // SMULri = 672
6946 CEFBS_None, // SMULrr = 673
6947 CEFBS_None, // SRAXri = 674
6948 CEFBS_None, // SRAXrr = 675
6949 CEFBS_None, // SRAri = 676
6950 CEFBS_None, // SRArr = 677
6951 CEFBS_None, // SRLXri = 678
6952 CEFBS_None, // SRLXrr = 679
6953 CEFBS_None, // SRLri = 680
6954 CEFBS_None, // SRLrr = 681
6955 CEFBS_HasV9, // STAri = 682
6956 CEFBS_None, // STArr = 683
6957 CEFBS_None, // STBAR = 684
6958 CEFBS_HasV9, // STBAri = 685
6959 CEFBS_None, // STBArr = 686
6960 CEFBS_None, // STBri = 687
6961 CEFBS_None, // STBrr = 688
6962 CEFBS_None, // STCSRri = 689
6963 CEFBS_None, // STCSRrr = 690
6964 CEFBS_None, // STCri = 691
6965 CEFBS_None, // STCrr = 692
6966 CEFBS_HasV9, // STDAri = 693
6967 CEFBS_None, // STDArr = 694
6968 CEFBS_None, // STDCQri = 695
6969 CEFBS_None, // STDCQrr = 696
6970 CEFBS_None, // STDCri = 697
6971 CEFBS_None, // STDCrr = 698
6972 CEFBS_HasV9, // STDFAri = 699
6973 CEFBS_HasV9, // STDFArr = 700
6974 CEFBS_None, // STDFQri = 701
6975 CEFBS_None, // STDFQrr = 702
6976 CEFBS_None, // STDFri = 703
6977 CEFBS_None, // STDFrr = 704
6978 CEFBS_None, // STDri = 705
6979 CEFBS_None, // STDrr = 706
6980 CEFBS_HasV9, // STFAri = 707
6981 CEFBS_HasV9, // STFArr = 708
6982 CEFBS_None, // STFSRri = 709
6983 CEFBS_None, // STFSRrr = 710
6984 CEFBS_None, // STFri = 711
6985 CEFBS_None, // STFrr = 712
6986 CEFBS_HasV9, // STHAri = 713
6987 CEFBS_None, // STHArr = 714
6988 CEFBS_None, // STHri = 715
6989 CEFBS_None, // STHrr = 716
6990 CEFBS_HasV9, // STQFAri = 717
6991 CEFBS_HasV9, // STQFArr = 718
6992 CEFBS_HasV9, // STQFri = 719
6993 CEFBS_HasV9, // STQFrr = 720
6994 CEFBS_None, // STXAri = 721
6995 CEFBS_None, // STXArr = 722
6996 CEFBS_HasV9, // STXFSRri = 723
6997 CEFBS_HasV9, // STXFSRrr = 724
6998 CEFBS_None, // STXri = 725
6999 CEFBS_None, // STXrr = 726
7000 CEFBS_None, // STri = 727
7001 CEFBS_None, // STrr = 728
7002 CEFBS_None, // SUBCCri = 729
7003 CEFBS_None, // SUBCCrr = 730
7004 CEFBS_None, // SUBCri = 731
7005 CEFBS_None, // SUBCrr = 732
7006 CEFBS_None, // SUBEri = 733
7007 CEFBS_None, // SUBErr = 734
7008 CEFBS_None, // SUBri = 735
7009 CEFBS_None, // SUBrr = 736
7010 CEFBS_HasV9, // SWAPAri = 737
7011 CEFBS_None, // SWAPArr = 738
7012 CEFBS_None, // SWAPri = 739
7013 CEFBS_None, // SWAPrr = 740
7014 CEFBS_None, // TA1 = 741
7015 CEFBS_None, // TA3 = 742
7016 CEFBS_None, // TA5 = 743
7017 CEFBS_None, // TADDCCTVri = 744
7018 CEFBS_None, // TADDCCTVrr = 745
7019 CEFBS_None, // TADDCCri = 746
7020 CEFBS_None, // TADDCCrr = 747
7021 CEFBS_None, // TAIL_CALL = 748
7022 CEFBS_None, // TAIL_CALLri = 749
7023 CEFBS_HasV9, // TICCri = 750
7024 CEFBS_HasV9, // TICCrr = 751
7025 CEFBS_None, // TLS_ADDrr = 752
7026 CEFBS_None, // TLS_CALL = 753
7027 CEFBS_None, // TLS_LDXrr = 754
7028 CEFBS_None, // TLS_LDrr = 755
7029 CEFBS_None, // TRAPri = 756
7030 CEFBS_None, // TRAPrr = 757
7031 CEFBS_None, // TSUBCCTVri = 758
7032 CEFBS_None, // TSUBCCTVrr = 759
7033 CEFBS_None, // TSUBCCri = 760
7034 CEFBS_None, // TSUBCCrr = 761
7035 CEFBS_None, // TXCCri = 762
7036 CEFBS_None, // TXCCrr = 763
7037 CEFBS_None, // UDIVCCri = 764
7038 CEFBS_None, // UDIVCCrr = 765
7039 CEFBS_None, // UDIVXri = 766
7040 CEFBS_None, // UDIVXrr = 767
7041 CEFBS_None, // UDIVri = 768
7042 CEFBS_None, // UDIVrr = 769
7043 CEFBS_None, // UMACri = 770
7044 CEFBS_None, // UMACrr = 771
7045 CEFBS_None, // UMULCCri = 772
7046 CEFBS_None, // UMULCCrr = 773
7047 CEFBS_HasVIS3, // UMULXHI = 774
7048 CEFBS_None, // UMULri = 775
7049 CEFBS_None, // UMULrr = 776
7050 CEFBS_None, // UNIMP = 777
7051 CEFBS_None, // V9FCMPD = 778
7052 CEFBS_None, // V9FCMPED = 779
7053 CEFBS_None, // V9FCMPEQ = 780
7054 CEFBS_None, // V9FCMPES = 781
7055 CEFBS_None, // V9FCMPQ = 782
7056 CEFBS_None, // V9FCMPS = 783
7057 CEFBS_HasV9, // V9FMOVD_FCC = 784
7058 CEFBS_HasV9, // V9FMOVQ_FCC = 785
7059 CEFBS_HasV9, // V9FMOVS_FCC = 786
7060 CEFBS_HasV9, // V9MOVFCCri = 787
7061 CEFBS_HasV9, // V9MOVFCCrr = 788
7062 CEFBS_None, // WRASRri = 789
7063 CEFBS_None, // WRASRrr = 790
7064 CEFBS_HasV9, // WRPRri = 791
7065 CEFBS_HasV9, // WRPRrr = 792
7066 CEFBS_None, // WRPSRri = 793
7067 CEFBS_None, // WRPSRrr = 794
7068 CEFBS_None, // WRTBRri = 795
7069 CEFBS_None, // WRTBRrr = 796
7070 CEFBS_None, // WRWIMri = 797
7071 CEFBS_None, // WRWIMrr = 798
7072 CEFBS_HasVIS3, // XMULX = 799
7073 CEFBS_HasVIS3, // XMULXHI = 800
7074 CEFBS_None, // XNORCCri = 801
7075 CEFBS_None, // XNORCCrr = 802
7076 CEFBS_None, // XNORri = 803
7077 CEFBS_None, // XNORrr = 804
7078 CEFBS_None, // XORCCri = 805
7079 CEFBS_None, // XORCCrr = 806
7080 CEFBS_None, // XORri = 807
7081 CEFBS_None, // XORrr = 808
7082 };
7083
7084 assert(Opcode < 809);
7085 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
7086}
7087
7088} // end namespace Sparc_MC
7089} // end namespace llvm
7090#endif // GET_COMPUTE_FEATURES
7091
7092#ifdef GET_AVAILABLE_OPCODE_CHECKER
7093#undef GET_AVAILABLE_OPCODE_CHECKER
7094namespace llvm {
7095namespace Sparc_MC {
7096bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
7097 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
7098 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
7099 FeatureBitset MissingFeatures =
7100 (AvailableFeatures & RequiredFeatures) ^
7101 RequiredFeatures;
7102 return !MissingFeatures.any();
7103}
7104} // end namespace Sparc_MC
7105} // end namespace llvm
7106#endif // GET_AVAILABLE_OPCODE_CHECKER
7107
7108#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
7109#undef ENABLE_INSTR_PREDICATE_VERIFIER
7110#include <sstream>
7111
7112namespace llvm {
7113namespace Sparc_MC {
7114
7115#ifndef NDEBUG
7116static const char *SubtargetFeatureNames[] = {
7117 "Feature_HasCASA",
7118 "Feature_HasPWRPSR",
7119 "Feature_HasV9",
7120 "Feature_HasVIS",
7121 "Feature_HasVIS2",
7122 "Feature_HasVIS3",
7123 "Feature_UseSoftMulDiv",
7124 nullptr
7125};
7126
7127#endif // NDEBUG
7128
7129void verifyInstructionPredicates(
7130 unsigned Opcode, const FeatureBitset &Features) {
7131#ifndef NDEBUG
7132 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
7133 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
7134 FeatureBitset MissingFeatures =
7135 (AvailableFeatures & RequiredFeatures) ^
7136 RequiredFeatures;
7137 if (MissingFeatures.any()) {
7138 std::ostringstream Msg;
7139 Msg << "Attempting to emit " << &SparcInstrNameData[SparcInstrNameIndices[Opcode]]
7140 << " instruction but the ";
7141 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
7142 if (MissingFeatures.test(i))
7143 Msg << SubtargetFeatureNames[i] << " ";
7144 Msg << "predicate(s) are not met";
7145 report_fatal_error(Msg.str().c_str());
7146 }
7147#endif // NDEBUG
7148}
7149} // end namespace Sparc_MC
7150} // end namespace llvm
7151#endif // ENABLE_INSTR_PREDICATE_VERIFIER
7152
7153