1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass SparcMCRegisterClasses[];
17
18namespace SP {
19enum {
20 NoRegister,
21 CANRESTORE = 1,
22 CANSAVE = 2,
23 CLEANWIN = 3,
24 CPQ = 4,
25 CPSR = 5,
26 CWP = 6,
27 FQ = 7,
28 FSR = 8,
29 GL = 9,
30 ICC = 10,
31 OTHERWIN = 11,
32 PIL = 12,
33 PSR = 13,
34 PSTATE = 14,
35 TBA = 15,
36 TBR = 16,
37 TICK = 17,
38 TL = 18,
39 TNPC = 19,
40 TPC = 20,
41 TSTATE = 21,
42 TT = 22,
43 VER = 23,
44 WIM = 24,
45 WSTATE = 25,
46 Y = 26,
47 ASR1 = 27,
48 ASR2 = 28,
49 ASR3 = 29,
50 ASR4 = 30,
51 ASR5 = 31,
52 ASR6 = 32,
53 ASR7 = 33,
54 ASR8 = 34,
55 ASR9 = 35,
56 ASR10 = 36,
57 ASR11 = 37,
58 ASR12 = 38,
59 ASR13 = 39,
60 ASR14 = 40,
61 ASR15 = 41,
62 ASR16 = 42,
63 ASR17 = 43,
64 ASR18 = 44,
65 ASR19 = 45,
66 ASR20 = 46,
67 ASR21 = 47,
68 ASR22 = 48,
69 ASR23 = 49,
70 ASR24 = 50,
71 ASR25 = 51,
72 ASR26 = 52,
73 ASR27 = 53,
74 ASR28 = 54,
75 ASR29 = 55,
76 ASR30 = 56,
77 ASR31 = 57,
78 C0 = 58,
79 C1 = 59,
80 C2 = 60,
81 C3 = 61,
82 C4 = 62,
83 C5 = 63,
84 C6 = 64,
85 C7 = 65,
86 C8 = 66,
87 C9 = 67,
88 C10 = 68,
89 C11 = 69,
90 C12 = 70,
91 C13 = 71,
92 C14 = 72,
93 C15 = 73,
94 C16 = 74,
95 C17 = 75,
96 C18 = 76,
97 C19 = 77,
98 C20 = 78,
99 C21 = 79,
100 C22 = 80,
101 C23 = 81,
102 C24 = 82,
103 C25 = 83,
104 C26 = 84,
105 C27 = 85,
106 C28 = 86,
107 C29 = 87,
108 C30 = 88,
109 C31 = 89,
110 D0 = 90,
111 D1 = 91,
112 D2 = 92,
113 D3 = 93,
114 D4 = 94,
115 D5 = 95,
116 D6 = 96,
117 D7 = 97,
118 D8 = 98,
119 D9 = 99,
120 D10 = 100,
121 D11 = 101,
122 D12 = 102,
123 D13 = 103,
124 D14 = 104,
125 D15 = 105,
126 D16 = 106,
127 D17 = 107,
128 D18 = 108,
129 D19 = 109,
130 D20 = 110,
131 D21 = 111,
132 D22 = 112,
133 D23 = 113,
134 D24 = 114,
135 D25 = 115,
136 D26 = 116,
137 D27 = 117,
138 D28 = 118,
139 D29 = 119,
140 D30 = 120,
141 D31 = 121,
142 F0 = 122,
143 F1 = 123,
144 F2 = 124,
145 F3 = 125,
146 F4 = 126,
147 F5 = 127,
148 F6 = 128,
149 F7 = 129,
150 F8 = 130,
151 F9 = 131,
152 F10 = 132,
153 F11 = 133,
154 F12 = 134,
155 F13 = 135,
156 F14 = 136,
157 F15 = 137,
158 F16 = 138,
159 F17 = 139,
160 F18 = 140,
161 F19 = 141,
162 F20 = 142,
163 F21 = 143,
164 F22 = 144,
165 F23 = 145,
166 F24 = 146,
167 F25 = 147,
168 F26 = 148,
169 F27 = 149,
170 F28 = 150,
171 F29 = 151,
172 F30 = 152,
173 F31 = 153,
174 FCC0 = 154,
175 FCC1 = 155,
176 FCC2 = 156,
177 FCC3 = 157,
178 G0 = 158,
179 G1 = 159,
180 G2 = 160,
181 G3 = 161,
182 G4 = 162,
183 G5 = 163,
184 G6 = 164,
185 G7 = 165,
186 I0 = 166,
187 I1 = 167,
188 I2 = 168,
189 I3 = 169,
190 I4 = 170,
191 I5 = 171,
192 I6 = 172,
193 I7 = 173,
194 L0 = 174,
195 L1 = 175,
196 L2 = 176,
197 L3 = 177,
198 L4 = 178,
199 L5 = 179,
200 L6 = 180,
201 L7 = 181,
202 O0 = 182,
203 O1 = 183,
204 O2 = 184,
205 O3 = 185,
206 O4 = 186,
207 O5 = 187,
208 O6 = 188,
209 O7 = 189,
210 Q0 = 190,
211 Q1 = 191,
212 Q2 = 192,
213 Q3 = 193,
214 Q4 = 194,
215 Q5 = 195,
216 Q6 = 196,
217 Q7 = 197,
218 Q8 = 198,
219 Q9 = 199,
220 Q10 = 200,
221 Q11 = 201,
222 Q12 = 202,
223 Q13 = 203,
224 Q14 = 204,
225 Q15 = 205,
226 C0_C1 = 206,
227 C2_C3 = 207,
228 C4_C5 = 208,
229 C6_C7 = 209,
230 C8_C9 = 210,
231 C10_C11 = 211,
232 C12_C13 = 212,
233 C14_C15 = 213,
234 C16_C17 = 214,
235 C18_C19 = 215,
236 C20_C21 = 216,
237 C22_C23 = 217,
238 C24_C25 = 218,
239 C26_C27 = 219,
240 C28_C29 = 220,
241 C30_C31 = 221,
242 G0_G1 = 222,
243 G2_G3 = 223,
244 G4_G5 = 224,
245 G6_G7 = 225,
246 I0_I1 = 226,
247 I2_I3 = 227,
248 I4_I5 = 228,
249 I6_I7 = 229,
250 L0_L1 = 230,
251 L2_L3 = 231,
252 L4_L5 = 232,
253 L6_L7 = 233,
254 O0_O1 = 234,
255 O2_O3 = 235,
256 O4_O5 = 236,
257 O6_O7 = 237,
258 NUM_TARGET_REGS // 238
259};
260} // end namespace SP
261
262// Register classes
263
264namespace SP {
265enum {
266 FCCRegsRegClassID = 0,
267 ASRRegsRegClassID = 1,
268 CoprocRegsRegClassID = 2,
269 FPRegsRegClassID = 3,
270 IntRegsRegClassID = 4,
271 GPRIncomingArgRegClassID = 5,
272 GPROutgoingArgRegClassID = 6,
273 DFPRegsRegClassID = 7,
274 I64RegsRegClassID = 8,
275 PRRegsRegClassID = 9,
276 CoprocPairRegClassID = 10,
277 IntPairRegClassID = 11,
278 LowDFPRegsRegClassID = 12,
279 I64Regs_and_GPRIncomingArgRegClassID = 13,
280 I64Regs_and_GPROutgoingArgRegClassID = 14,
281 IntPair_with_sub_even_in_GPRIncomingArgRegClassID = 15,
282 IntPair_with_sub_even_in_GPROutgoingArgRegClassID = 16,
283 PRRegs_and_ASRRegsRegClassID = 17,
284 QFPRegsRegClassID = 18,
285 LowQFPRegsRegClassID = 19,
286
287};
288} // end namespace SP
289
290
291// Register alternate name indices
292
293namespace SP {
294enum {
295 NoRegAltName, // 0
296 RegNamesStateReg, // 1
297 NUM_TARGET_REG_ALT_NAMES = 2
298};
299} // end namespace SP
300
301
302// Subregister indices
303
304namespace SP {
305enum : uint16_t {
306 NoSubRegister,
307 sub_even, // 1
308 sub_even64, // 2
309 sub_odd, // 3
310 sub_odd64, // 4
311 sub_odd64_then_sub_even, // 5
312 sub_odd64_then_sub_odd, // 6
313 NUM_TARGET_SUBREGS
314};
315} // end namespace SP
316
317// Register pressure sets enum.
318namespace SP {
319enum RegisterPressureSets {
320 PRRegs_and_ASRRegs = 0,
321 FCCRegs = 1,
322 GPRIncomingArg = 2,
323 GPROutgoingArg = 3,
324 PRRegs = 4,
325 FPRegs = 5,
326 IntRegs = 6,
327 DFPRegs = 7,
328};
329} // end namespace SP
330
331} // end namespace llvm
332
333#endif // GET_REGINFO_ENUM
334
335/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
336|* *|
337|* MC Register Information *|
338|* *|
339|* Automatically generated file, do not edit! *|
340|* *|
341\*===----------------------------------------------------------------------===*/
342
343
344#ifdef GET_REGINFO_MC_DESC
345#undef GET_REGINFO_MC_DESC
346
347namespace llvm {
348
349extern const int16_t SparcRegDiffLists[] = {
350 /* 0 */ -148, 1, 0,
351 /* 3 */ -147, 1, 0,
352 /* 6 */ -146, 1, 0,
353 /* 9 */ -145, 1, 0,
354 /* 12 */ -144, 1, 0,
355 /* 15 */ -143, 1, 0,
356 /* 18 */ -142, 1, 0,
357 /* 21 */ -141, 1, 0,
358 /* 24 */ -140, 1, 0,
359 /* 27 */ -139, 1, 0,
360 /* 30 */ -138, 1, 0,
361 /* 33 */ -137, 1, 0,
362 /* 36 */ -136, 1, 0,
363 /* 39 */ -135, 1, 0,
364 /* 42 */ -134, 1, 0,
365 /* 45 */ -133, 1, 0,
366 /* 48 */ -92, 1, 0,
367 /* 51 */ -91, 1, 0,
368 /* 54 */ -90, 1, 0,
369 /* 57 */ -89, 1, 0,
370 /* 60 */ -88, 1, 0,
371 /* 63 */ -87, 1, 0,
372 /* 66 */ -86, 1, 0,
373 /* 69 */ -85, 1, 0,
374 /* 72 */ -64, 1, 0,
375 /* 75 */ -63, 1, 0,
376 /* 78 */ -62, 1, 0,
377 /* 81 */ -61, 1, 0,
378 /* 84 */ -60, 1, 0,
379 /* 87 */ -59, 1, 0,
380 /* 90 */ -58, 1, 0,
381 /* 93 */ -57, 1, 0,
382 /* 96 */ -56, 1, 0,
383 /* 99 */ -55, 1, 0,
384 /* 102 */ -54, 1, 0,
385 /* 105 */ -53, 1, 0,
386 /* 108 */ -52, 1, 0,
387 /* 111 */ -51, 1, 0,
388 /* 114 */ -50, 1, 0,
389 /* 117 */ -49, 1, 0,
390 /* 120 */ 1, 1, 1, 0,
391 /* 124 */ 32, 1, 0,
392 /* 127 */ -100, 32, 1, -32, 33, 1, 0,
393 /* 134 */ 34, 1, 0,
394 /* 137 */ -99, 34, 1, -34, 35, 1, 0,
395 /* 144 */ 36, 1, 0,
396 /* 147 */ -98, 36, 1, -36, 37, 1, 0,
397 /* 154 */ 38, 1, 0,
398 /* 157 */ -97, 38, 1, -38, 39, 1, 0,
399 /* 164 */ 40, 1, 0,
400 /* 167 */ -96, 40, 1, -40, 41, 1, 0,
401 /* 174 */ 42, 1, 0,
402 /* 177 */ -95, 42, 1, -42, 43, 1, 0,
403 /* 184 */ 44, 1, 0,
404 /* 187 */ -94, 44, 1, -44, 45, 1, 0,
405 /* 194 */ 46, 1, 0,
406 /* 197 */ -93, 46, 1, -46, 47, 1, 0,
407 /* 204 */ 48, 0,
408 /* 206 */ 49, 0,
409 /* 208 */ 50, 0,
410 /* 210 */ 51, 0,
411 /* 212 */ 52, 0,
412 /* 214 */ 53, 0,
413 /* 216 */ 54, 0,
414 /* 218 */ 55, 0,
415 /* 220 */ 56, 0,
416 /* 222 */ 57, 0,
417 /* 224 */ 58, 0,
418 /* 226 */ 59, 0,
419 /* 228 */ 60, 0,
420 /* 230 */ 61, 0,
421 /* 232 */ 62, 0,
422 /* 234 */ 63, 0,
423 /* 236 */ 64, 0,
424 /* 238 */ 84, 0,
425 /* 240 */ 85, 0,
426 /* 242 */ 86, 0,
427 /* 244 */ 87, 0,
428 /* 246 */ 88, 0,
429 /* 248 */ 89, 0,
430 /* 250 */ 90, 0,
431 /* 252 */ 91, 0,
432 /* 254 */ -48, 92, 0,
433 /* 257 */ -47, 92, 0,
434 /* 260 */ -47, 93, 0,
435 /* 263 */ -46, 93, 0,
436 /* 266 */ -45, 93, 0,
437 /* 269 */ -45, 94, 0,
438 /* 272 */ -44, 94, 0,
439 /* 275 */ -43, 94, 0,
440 /* 278 */ -43, 95, 0,
441 /* 281 */ -42, 95, 0,
442 /* 284 */ -41, 95, 0,
443 /* 287 */ -41, 96, 0,
444 /* 290 */ -40, 96, 0,
445 /* 293 */ -39, 96, 0,
446 /* 296 */ -39, 97, 0,
447 /* 299 */ -38, 97, 0,
448 /* 302 */ -37, 97, 0,
449 /* 305 */ -37, 98, 0,
450 /* 308 */ -36, 98, 0,
451 /* 311 */ -35, 98, 0,
452 /* 314 */ -35, 99, 0,
453 /* 317 */ -34, 99, 0,
454 /* 320 */ -33, 99, 0,
455 /* 323 */ -33, 100, 0,
456 /* 326 */ -32, 100, 0,
457 /* 329 */ 132, 0,
458 /* 331 */ 133, 0,
459 /* 333 */ 134, 0,
460 /* 335 */ 135, 0,
461 /* 337 */ 136, 0,
462 /* 339 */ 137, 0,
463 /* 341 */ 138, 0,
464 /* 343 */ 139, 0,
465 /* 345 */ 140, 0,
466 /* 347 */ 141, 0,
467 /* 349 */ 142, 0,
468 /* 351 */ 143, 0,
469 /* 353 */ 144, 0,
470 /* 355 */ 145, 0,
471 /* 357 */ 146, 0,
472 /* 359 */ 147, 0,
473 /* 361 */ 148, 0,
474};
475
476extern const LaneBitmask SparcLaneMaskLists[] = {
477 /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask::getAll(),
478 /* 3 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
479 /* 8 */ LaneBitmask(0x0000000000000003), LaneBitmask(0x000000000000000C), LaneBitmask::getAll(),
480 /* 11 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
481};
482
483extern const uint16_t SparcSubRegIdxLists[] = {
484 /* 0 */ 1, 3, 0,
485 /* 3 */ 2, 4, 0,
486 /* 6 */ 2, 1, 3, 4, 5, 6, 0,
487};
488
489
490#ifdef __GNUC__
491#pragma GCC diagnostic push
492#pragma GCC diagnostic ignored "-Woverlength-strings"
493#endif
494extern const char SparcRegStrings[] = {
495 /* 0 */ "C10\0"
496 /* 4 */ "D10\0"
497 /* 8 */ "F10\0"
498 /* 12 */ "Q10\0"
499 /* 16 */ "ASR10\0"
500 /* 22 */ "C20\0"
501 /* 26 */ "D20\0"
502 /* 30 */ "F20\0"
503 /* 34 */ "ASR20\0"
504 /* 40 */ "C30\0"
505 /* 44 */ "D30\0"
506 /* 48 */ "F30\0"
507 /* 52 */ "ASR30\0"
508 /* 58 */ "FCC0\0"
509 /* 63 */ "D0\0"
510 /* 66 */ "F0\0"
511 /* 69 */ "G0\0"
512 /* 72 */ "I0\0"
513 /* 75 */ "L0\0"
514 /* 78 */ "O0\0"
515 /* 81 */ "Q0\0"
516 /* 84 */ "C10_C11\0"
517 /* 92 */ "D11\0"
518 /* 96 */ "F11\0"
519 /* 100 */ "Q11\0"
520 /* 104 */ "ASR11\0"
521 /* 110 */ "C20_C21\0"
522 /* 118 */ "D21\0"
523 /* 122 */ "F21\0"
524 /* 126 */ "ASR21\0"
525 /* 132 */ "C30_C31\0"
526 /* 140 */ "D31\0"
527 /* 144 */ "F31\0"
528 /* 148 */ "ASR31\0"
529 /* 154 */ "FCC1\0"
530 /* 159 */ "C0_C1\0"
531 /* 165 */ "D1\0"
532 /* 168 */ "F1\0"
533 /* 171 */ "G0_G1\0"
534 /* 177 */ "I0_I1\0"
535 /* 183 */ "L0_L1\0"
536 /* 189 */ "O0_O1\0"
537 /* 195 */ "Q1\0"
538 /* 198 */ "ASR1\0"
539 /* 203 */ "C12\0"
540 /* 207 */ "D12\0"
541 /* 211 */ "F12\0"
542 /* 215 */ "Q12\0"
543 /* 219 */ "ASR12\0"
544 /* 225 */ "C22\0"
545 /* 229 */ "D22\0"
546 /* 233 */ "F22\0"
547 /* 237 */ "ASR22\0"
548 /* 243 */ "FCC2\0"
549 /* 248 */ "D2\0"
550 /* 251 */ "F2\0"
551 /* 254 */ "G2\0"
552 /* 257 */ "I2\0"
553 /* 260 */ "L2\0"
554 /* 263 */ "O2\0"
555 /* 266 */ "Q2\0"
556 /* 269 */ "ASR2\0"
557 /* 274 */ "C12_C13\0"
558 /* 282 */ "D13\0"
559 /* 286 */ "F13\0"
560 /* 290 */ "Q13\0"
561 /* 294 */ "ASR13\0"
562 /* 300 */ "C22_C23\0"
563 /* 308 */ "D23\0"
564 /* 312 */ "F23\0"
565 /* 316 */ "ASR23\0"
566 /* 322 */ "FCC3\0"
567 /* 327 */ "C2_C3\0"
568 /* 333 */ "D3\0"
569 /* 336 */ "F3\0"
570 /* 339 */ "G2_G3\0"
571 /* 345 */ "I2_I3\0"
572 /* 351 */ "L2_L3\0"
573 /* 357 */ "O2_O3\0"
574 /* 363 */ "Q3\0"
575 /* 366 */ "ASR3\0"
576 /* 371 */ "C14\0"
577 /* 375 */ "D14\0"
578 /* 379 */ "F14\0"
579 /* 383 */ "Q14\0"
580 /* 387 */ "ASR14\0"
581 /* 393 */ "C24\0"
582 /* 397 */ "D24\0"
583 /* 401 */ "F24\0"
584 /* 405 */ "ASR24\0"
585 /* 411 */ "C4\0"
586 /* 414 */ "D4\0"
587 /* 417 */ "F4\0"
588 /* 420 */ "G4\0"
589 /* 423 */ "I4\0"
590 /* 426 */ "L4\0"
591 /* 429 */ "O4\0"
592 /* 432 */ "Q4\0"
593 /* 435 */ "ASR4\0"
594 /* 440 */ "C14_C15\0"
595 /* 448 */ "D15\0"
596 /* 452 */ "F15\0"
597 /* 456 */ "Q15\0"
598 /* 460 */ "ASR15\0"
599 /* 466 */ "C24_C25\0"
600 /* 474 */ "D25\0"
601 /* 478 */ "F25\0"
602 /* 482 */ "ASR25\0"
603 /* 488 */ "C4_C5\0"
604 /* 494 */ "D5\0"
605 /* 497 */ "F5\0"
606 /* 500 */ "G4_G5\0"
607 /* 506 */ "I4_I5\0"
608 /* 512 */ "L4_L5\0"
609 /* 518 */ "O4_O5\0"
610 /* 524 */ "Q5\0"
611 /* 527 */ "ASR5\0"
612 /* 532 */ "C16\0"
613 /* 536 */ "D16\0"
614 /* 540 */ "F16\0"
615 /* 544 */ "ASR16\0"
616 /* 550 */ "C26\0"
617 /* 554 */ "D26\0"
618 /* 558 */ "F26\0"
619 /* 562 */ "ASR26\0"
620 /* 568 */ "C6\0"
621 /* 571 */ "D6\0"
622 /* 574 */ "F6\0"
623 /* 577 */ "G6\0"
624 /* 580 */ "I6\0"
625 /* 583 */ "L6\0"
626 /* 586 */ "O6\0"
627 /* 589 */ "Q6\0"
628 /* 592 */ "ASR6\0"
629 /* 597 */ "C16_C17\0"
630 /* 605 */ "D17\0"
631 /* 609 */ "F17\0"
632 /* 613 */ "ASR17\0"
633 /* 619 */ "C26_C27\0"
634 /* 627 */ "D27\0"
635 /* 631 */ "F27\0"
636 /* 635 */ "ASR27\0"
637 /* 641 */ "C6_C7\0"
638 /* 647 */ "D7\0"
639 /* 650 */ "F7\0"
640 /* 653 */ "G6_G7\0"
641 /* 659 */ "I6_I7\0"
642 /* 665 */ "L6_L7\0"
643 /* 671 */ "O6_O7\0"
644 /* 677 */ "Q7\0"
645 /* 680 */ "ASR7\0"
646 /* 685 */ "C18\0"
647 /* 689 */ "D18\0"
648 /* 693 */ "F18\0"
649 /* 697 */ "ASR18\0"
650 /* 703 */ "C28\0"
651 /* 707 */ "D28\0"
652 /* 711 */ "F28\0"
653 /* 715 */ "ASR28\0"
654 /* 721 */ "C8\0"
655 /* 724 */ "D8\0"
656 /* 727 */ "F8\0"
657 /* 730 */ "Q8\0"
658 /* 733 */ "ASR8\0"
659 /* 738 */ "C18_C19\0"
660 /* 746 */ "D19\0"
661 /* 750 */ "F19\0"
662 /* 754 */ "ASR19\0"
663 /* 760 */ "C28_C29\0"
664 /* 768 */ "D29\0"
665 /* 772 */ "F29\0"
666 /* 776 */ "ASR29\0"
667 /* 782 */ "C8_C9\0"
668 /* 788 */ "D9\0"
669 /* 791 */ "F9\0"
670 /* 794 */ "Q9\0"
671 /* 797 */ "ASR9\0"
672 /* 802 */ "TBA\0"
673 /* 806 */ "ICC\0"
674 /* 810 */ "TNPC\0"
675 /* 815 */ "TPC\0"
676 /* 819 */ "CANRESTORE\0"
677 /* 830 */ "PSTATE\0"
678 /* 837 */ "TSTATE\0"
679 /* 844 */ "WSTATE\0"
680 /* 851 */ "CANSAVE\0"
681 /* 859 */ "TICK\0"
682 /* 864 */ "GL\0"
683 /* 867 */ "PIL\0"
684 /* 871 */ "TL\0"
685 /* 874 */ "WIM\0"
686 /* 878 */ "CLEANWIN\0"
687 /* 887 */ "OTHERWIN\0"
688 /* 896 */ "CWP\0"
689 /* 900 */ "FQ\0"
690 /* 903 */ "CPQ\0"
691 /* 907 */ "TBR\0"
692 /* 911 */ "VER\0"
693 /* 915 */ "FSR\0"
694 /* 919 */ "CPSR\0"
695 /* 924 */ "TT\0"
696 /* 927 */ "Y\0"
697};
698#ifdef __GNUC__
699#pragma GCC diagnostic pop
700#endif
701
702extern const MCRegisterDesc SparcRegDesc[] = { // Descriptors
703 { 3, 0, 0, 0, 0, 0, 0 },
704 { 819, 2, 2, 2, 8192, 11, 0 },
705 { 851, 2, 2, 2, 8193, 11, 0 },
706 { 878, 2, 2, 2, 8194, 11, 0 },
707 { 903, 2, 2, 2, 8195, 11, 0 },
708 { 919, 2, 2, 2, 8196, 11, 0 },
709 { 896, 2, 2, 2, 8197, 11, 0 },
710 { 900, 2, 2, 2, 8198, 11, 0 },
711 { 915, 2, 2, 2, 8199, 11, 0 },
712 { 864, 2, 2, 2, 8200, 11, 0 },
713 { 806, 2, 2, 2, 8201, 11, 0 },
714 { 887, 2, 2, 2, 8202, 11, 0 },
715 { 867, 2, 2, 2, 8203, 11, 0 },
716 { 920, 2, 2, 2, 8204, 11, 0 },
717 { 830, 2, 2, 2, 8205, 11, 0 },
718 { 802, 2, 2, 2, 8206, 11, 0 },
719 { 907, 2, 2, 2, 8207, 11, 0 },
720 { 859, 2, 2, 2, 8208, 11, 0 },
721 { 871, 2, 2, 2, 8209, 11, 0 },
722 { 810, 2, 2, 2, 8210, 11, 0 },
723 { 815, 2, 2, 2, 8211, 11, 0 },
724 { 837, 2, 2, 2, 8212, 11, 0 },
725 { 924, 2, 2, 2, 8213, 11, 0 },
726 { 911, 2, 2, 2, 8214, 11, 0 },
727 { 874, 2, 2, 2, 8215, 11, 0 },
728 { 844, 2, 2, 2, 8216, 11, 0 },
729 { 927, 2, 2, 2, 8217, 11, 0 },
730 { 198, 2, 2, 2, 8218, 11, 0 },
731 { 269, 2, 2, 2, 8219, 11, 0 },
732 { 366, 2, 2, 2, 8220, 11, 0 },
733 { 435, 2, 2, 2, 8221, 11, 0 },
734 { 527, 2, 2, 2, 8222, 11, 0 },
735 { 592, 2, 2, 2, 8223, 11, 0 },
736 { 680, 2, 2, 2, 8224, 11, 0 },
737 { 733, 2, 2, 2, 8225, 11, 0 },
738 { 797, 2, 2, 2, 8226, 11, 0 },
739 { 16, 2, 2, 2, 8227, 11, 0 },
740 { 104, 2, 2, 2, 8228, 11, 0 },
741 { 219, 2, 2, 2, 8229, 11, 0 },
742 { 294, 2, 2, 2, 8230, 11, 0 },
743 { 387, 2, 2, 2, 8231, 11, 0 },
744 { 460, 2, 2, 2, 8232, 11, 0 },
745 { 544, 2, 2, 2, 8233, 11, 0 },
746 { 613, 2, 2, 2, 8234, 11, 0 },
747 { 697, 2, 2, 2, 8235, 11, 0 },
748 { 754, 2, 2, 2, 8236, 11, 0 },
749 { 34, 2, 2, 2, 8237, 11, 0 },
750 { 126, 2, 2, 2, 8238, 11, 0 },
751 { 237, 2, 2, 2, 8239, 11, 0 },
752 { 316, 2, 2, 2, 8240, 11, 0 },
753 { 405, 2, 2, 2, 8241, 11, 0 },
754 { 482, 2, 2, 2, 8242, 11, 0 },
755 { 562, 2, 2, 2, 8243, 11, 0 },
756 { 635, 2, 2, 2, 8244, 11, 0 },
757 { 715, 2, 2, 2, 8245, 11, 0 },
758 { 776, 2, 2, 2, 8246, 11, 0 },
759 { 52, 2, 2, 2, 8247, 11, 0 },
760 { 148, 2, 2, 2, 8248, 11, 0 },
761 { 60, 2, 361, 2, 8249, 11, 0 },
762 { 156, 2, 359, 2, 8250, 11, 0 },
763 { 245, 2, 359, 2, 8251, 11, 0 },
764 { 324, 2, 357, 2, 8252, 11, 0 },
765 { 411, 2, 357, 2, 8253, 11, 0 },
766 { 491, 2, 355, 2, 8254, 11, 0 },
767 { 568, 2, 355, 2, 8255, 11, 0 },
768 { 644, 2, 353, 2, 8256, 11, 0 },
769 { 721, 2, 353, 2, 8257, 11, 0 },
770 { 785, 2, 351, 2, 8258, 11, 0 },
771 { 0, 2, 351, 2, 8259, 11, 0 },
772 { 88, 2, 349, 2, 8260, 11, 0 },
773 { 203, 2, 349, 2, 8261, 11, 0 },
774 { 278, 2, 347, 2, 8262, 11, 0 },
775 { 371, 2, 347, 2, 8263, 11, 0 },
776 { 444, 2, 345, 2, 8264, 11, 0 },
777 { 532, 2, 345, 2, 8265, 11, 0 },
778 { 601, 2, 343, 2, 8266, 11, 0 },
779 { 685, 2, 343, 2, 8267, 11, 0 },
780 { 742, 2, 341, 2, 8268, 11, 0 },
781 { 22, 2, 341, 2, 8269, 11, 0 },
782 { 114, 2, 339, 2, 8270, 11, 0 },
783 { 225, 2, 339, 2, 8271, 11, 0 },
784 { 304, 2, 337, 2, 8272, 11, 0 },
785 { 393, 2, 337, 2, 8273, 11, 0 },
786 { 470, 2, 335, 2, 8274, 11, 0 },
787 { 550, 2, 335, 2, 8275, 11, 0 },
788 { 623, 2, 333, 2, 8276, 11, 0 },
789 { 703, 2, 333, 2, 8277, 11, 0 },
790 { 764, 2, 331, 2, 8278, 11, 0 },
791 { 40, 2, 331, 2, 8279, 11, 0 },
792 { 136, 2, 329, 2, 8280, 11, 0 },
793 { 63, 124, 324, 0, 4185, 0, 0 },
794 { 165, 131, 315, 0, 4187, 0, 0 },
795 { 248, 134, 315, 0, 4189, 0, 0 },
796 { 333, 141, 306, 0, 4191, 0, 0 },
797 { 414, 144, 306, 0, 4193, 0, 0 },
798 { 494, 151, 297, 0, 4195, 0, 0 },
799 { 571, 154, 297, 0, 4197, 0, 0 },
800 { 647, 161, 288, 0, 4199, 0, 0 },
801 { 724, 164, 288, 0, 4201, 0, 0 },
802 { 788, 171, 279, 0, 4203, 0, 0 },
803 { 4, 174, 279, 0, 4205, 0, 0 },
804 { 92, 181, 270, 0, 4207, 0, 0 },
805 { 207, 184, 270, 0, 4209, 0, 0 },
806 { 282, 191, 261, 0, 4211, 0, 0 },
807 { 375, 194, 261, 0, 4213, 0, 0 },
808 { 448, 201, 255, 0, 4215, 0, 0 },
809 { 536, 2, 255, 2, 8313, 11, 0 },
810 { 605, 2, 252, 2, 8314, 11, 0 },
811 { 689, 2, 252, 2, 8315, 11, 0 },
812 { 746, 2, 250, 2, 8316, 11, 0 },
813 { 26, 2, 250, 2, 8317, 11, 0 },
814 { 118, 2, 248, 2, 8318, 11, 0 },
815 { 229, 2, 248, 2, 8319, 11, 0 },
816 { 308, 2, 246, 2, 8320, 11, 0 },
817 { 397, 2, 246, 2, 8321, 11, 0 },
818 { 474, 2, 244, 2, 8322, 11, 0 },
819 { 554, 2, 244, 2, 8323, 11, 0 },
820 { 627, 2, 242, 2, 8324, 11, 0 },
821 { 707, 2, 242, 2, 8325, 11, 0 },
822 { 768, 2, 240, 2, 8326, 11, 0 },
823 { 44, 2, 240, 2, 8327, 11, 0 },
824 { 140, 2, 238, 2, 8328, 11, 0 },
825 { 66, 2, 326, 2, 8281, 11, 0 },
826 { 168, 2, 323, 2, 8282, 11, 0 },
827 { 251, 2, 320, 2, 8283, 11, 0 },
828 { 336, 2, 317, 2, 8284, 11, 0 },
829 { 417, 2, 317, 2, 8285, 11, 0 },
830 { 497, 2, 314, 2, 8286, 11, 0 },
831 { 574, 2, 311, 2, 8287, 11, 0 },
832 { 650, 2, 308, 2, 8288, 11, 0 },
833 { 727, 2, 308, 2, 8289, 11, 0 },
834 { 791, 2, 305, 2, 8290, 11, 0 },
835 { 8, 2, 302, 2, 8291, 11, 0 },
836 { 96, 2, 299, 2, 8292, 11, 0 },
837 { 211, 2, 299, 2, 8293, 11, 0 },
838 { 286, 2, 296, 2, 8294, 11, 0 },
839 { 379, 2, 293, 2, 8295, 11, 0 },
840 { 452, 2, 290, 2, 8296, 11, 0 },
841 { 540, 2, 290, 2, 8297, 11, 0 },
842 { 609, 2, 287, 2, 8298, 11, 0 },
843 { 693, 2, 284, 2, 8299, 11, 0 },
844 { 750, 2, 281, 2, 8300, 11, 0 },
845 { 30, 2, 281, 2, 8301, 11, 0 },
846 { 122, 2, 278, 2, 8302, 11, 0 },
847 { 233, 2, 275, 2, 8303, 11, 0 },
848 { 312, 2, 272, 2, 8304, 11, 0 },
849 { 401, 2, 272, 2, 8305, 11, 0 },
850 { 478, 2, 269, 2, 8306, 11, 0 },
851 { 558, 2, 266, 2, 8307, 11, 0 },
852 { 631, 2, 263, 2, 8308, 11, 0 },
853 { 711, 2, 263, 2, 8309, 11, 0 },
854 { 772, 2, 260, 2, 8310, 11, 0 },
855 { 48, 2, 257, 2, 8311, 11, 0 },
856 { 144, 2, 254, 2, 8312, 11, 0 },
857 { 58, 2, 2, 2, 8329, 11, 0 },
858 { 154, 2, 2, 2, 8330, 11, 0 },
859 { 243, 2, 2, 2, 8331, 11, 0 },
860 { 322, 2, 2, 2, 8332, 11, 0 },
861 { 69, 2, 236, 2, 8333, 11, 1 },
862 { 174, 2, 234, 2, 8334, 11, 0 },
863 { 254, 2, 234, 2, 8335, 11, 0 },
864 { 342, 2, 232, 2, 8336, 11, 0 },
865 { 420, 2, 232, 2, 8337, 11, 0 },
866 { 503, 2, 230, 2, 8338, 11, 0 },
867 { 577, 2, 230, 2, 8339, 11, 0 },
868 { 656, 2, 228, 2, 8340, 11, 0 },
869 { 72, 2, 228, 2, 8341, 11, 0 },
870 { 180, 2, 226, 2, 8342, 11, 0 },
871 { 257, 2, 226, 2, 8343, 11, 0 },
872 { 348, 2, 224, 2, 8344, 11, 0 },
873 { 423, 2, 224, 2, 8345, 11, 0 },
874 { 509, 2, 222, 2, 8346, 11, 0 },
875 { 580, 2, 222, 2, 8347, 11, 0 },
876 { 662, 2, 220, 2, 8348, 11, 0 },
877 { 75, 2, 220, 2, 8349, 11, 0 },
878 { 186, 2, 218, 2, 8350, 11, 0 },
879 { 260, 2, 218, 2, 8351, 11, 0 },
880 { 354, 2, 216, 2, 8352, 11, 0 },
881 { 426, 2, 216, 2, 8353, 11, 0 },
882 { 515, 2, 214, 2, 8354, 11, 0 },
883 { 583, 2, 214, 2, 8355, 11, 0 },
884 { 668, 2, 212, 2, 8356, 11, 0 },
885 { 78, 2, 212, 2, 8357, 11, 0 },
886 { 192, 2, 210, 2, 8358, 11, 0 },
887 { 263, 2, 210, 2, 8359, 11, 0 },
888 { 360, 2, 208, 2, 8360, 11, 0 },
889 { 429, 2, 208, 2, 8361, 11, 0 },
890 { 521, 2, 206, 2, 8362, 11, 0 },
891 { 586, 2, 206, 2, 8363, 11, 0 },
892 { 674, 2, 204, 2, 8364, 11, 0 },
893 { 81, 127, 2, 6, 491609, 3, 0 },
894 { 195, 137, 2, 6, 491613, 3, 0 },
895 { 266, 147, 2, 6, 491617, 3, 0 },
896 { 363, 157, 2, 6, 491621, 3, 0 },
897 { 432, 167, 2, 6, 491625, 3, 0 },
898 { 524, 177, 2, 6, 491629, 3, 0 },
899 { 589, 187, 2, 6, 491633, 3, 0 },
900 { 677, 197, 2, 6, 491637, 3, 0 },
901 { 730, 48, 2, 3, 4217, 8, 0 },
902 { 794, 51, 2, 3, 4219, 8, 0 },
903 { 12, 54, 2, 3, 4221, 8, 0 },
904 { 100, 57, 2, 3, 4223, 8, 0 },
905 { 215, 60, 2, 3, 4225, 8, 0 },
906 { 290, 63, 2, 3, 4227, 8, 0 },
907 { 383, 66, 2, 3, 4229, 8, 0 },
908 { 456, 69, 2, 3, 4231, 8, 0 },
909 { 159, 0, 2, 0, 4153, 0, 0 },
910 { 327, 3, 2, 0, 4155, 0, 0 },
911 { 488, 6, 2, 0, 4157, 0, 0 },
912 { 641, 9, 2, 0, 4159, 0, 0 },
913 { 782, 12, 2, 0, 4161, 0, 0 },
914 { 84, 15, 2, 0, 4163, 0, 0 },
915 { 274, 18, 2, 0, 4165, 0, 0 },
916 { 440, 21, 2, 0, 4167, 0, 0 },
917 { 597, 24, 2, 0, 4169, 0, 0 },
918 { 738, 27, 2, 0, 4171, 0, 0 },
919 { 110, 30, 2, 0, 4173, 0, 0 },
920 { 300, 33, 2, 0, 4175, 0, 0 },
921 { 466, 36, 2, 0, 4177, 0, 0 },
922 { 619, 39, 2, 0, 4179, 0, 0 },
923 { 760, 42, 2, 0, 4181, 0, 0 },
924 { 132, 45, 2, 0, 4183, 0, 0 },
925 { 171, 72, 2, 0, 4237, 0, 0 },
926 { 339, 75, 2, 0, 4239, 0, 0 },
927 { 500, 78, 2, 0, 4241, 0, 0 },
928 { 653, 81, 2, 0, 4243, 0, 0 },
929 { 177, 84, 2, 0, 4245, 0, 0 },
930 { 345, 87, 2, 0, 4247, 0, 0 },
931 { 506, 90, 2, 0, 4249, 0, 0 },
932 { 659, 93, 2, 0, 4251, 0, 0 },
933 { 183, 96, 2, 0, 4253, 0, 0 },
934 { 351, 99, 2, 0, 4255, 0, 0 },
935 { 512, 102, 2, 0, 4257, 0, 0 },
936 { 665, 105, 2, 0, 4259, 0, 0 },
937 { 189, 108, 2, 0, 4261, 0, 0 },
938 { 357, 111, 2, 0, 4263, 0, 0 },
939 { 518, 114, 2, 0, 4265, 0, 0 },
940 { 671, 117, 2, 0, 4267, 0, 0 },
941};
942
943extern const MCPhysReg SparcRegUnitRoots[][2] = {
944 { SP::CANRESTORE },
945 { SP::CANSAVE },
946 { SP::CLEANWIN },
947 { SP::CPQ },
948 { SP::CPSR },
949 { SP::CWP },
950 { SP::FQ },
951 { SP::FSR },
952 { SP::GL },
953 { SP::ICC },
954 { SP::OTHERWIN },
955 { SP::PIL },
956 { SP::PSR },
957 { SP::PSTATE },
958 { SP::TBA },
959 { SP::TBR },
960 { SP::TICK },
961 { SP::TL },
962 { SP::TNPC },
963 { SP::TPC },
964 { SP::TSTATE },
965 { SP::TT },
966 { SP::VER },
967 { SP::WIM },
968 { SP::WSTATE },
969 { SP::Y },
970 { SP::ASR1 },
971 { SP::ASR2 },
972 { SP::ASR3 },
973 { SP::ASR4 },
974 { SP::ASR5 },
975 { SP::ASR6 },
976 { SP::ASR7 },
977 { SP::ASR8 },
978 { SP::ASR9 },
979 { SP::ASR10 },
980 { SP::ASR11 },
981 { SP::ASR12 },
982 { SP::ASR13 },
983 { SP::ASR14 },
984 { SP::ASR15 },
985 { SP::ASR16 },
986 { SP::ASR17 },
987 { SP::ASR18 },
988 { SP::ASR19 },
989 { SP::ASR20 },
990 { SP::ASR21 },
991 { SP::ASR22 },
992 { SP::ASR23 },
993 { SP::ASR24 },
994 { SP::ASR25 },
995 { SP::ASR26 },
996 { SP::ASR27 },
997 { SP::ASR28 },
998 { SP::ASR29 },
999 { SP::ASR30 },
1000 { SP::ASR31 },
1001 { SP::C0 },
1002 { SP::C1 },
1003 { SP::C2 },
1004 { SP::C3 },
1005 { SP::C4 },
1006 { SP::C5 },
1007 { SP::C6 },
1008 { SP::C7 },
1009 { SP::C8 },
1010 { SP::C9 },
1011 { SP::C10 },
1012 { SP::C11 },
1013 { SP::C12 },
1014 { SP::C13 },
1015 { SP::C14 },
1016 { SP::C15 },
1017 { SP::C16 },
1018 { SP::C17 },
1019 { SP::C18 },
1020 { SP::C19 },
1021 { SP::C20 },
1022 { SP::C21 },
1023 { SP::C22 },
1024 { SP::C23 },
1025 { SP::C24 },
1026 { SP::C25 },
1027 { SP::C26 },
1028 { SP::C27 },
1029 { SP::C28 },
1030 { SP::C29 },
1031 { SP::C30 },
1032 { SP::C31 },
1033 { SP::F0 },
1034 { SP::F1 },
1035 { SP::F2 },
1036 { SP::F3 },
1037 { SP::F4 },
1038 { SP::F5 },
1039 { SP::F6 },
1040 { SP::F7 },
1041 { SP::F8 },
1042 { SP::F9 },
1043 { SP::F10 },
1044 { SP::F11 },
1045 { SP::F12 },
1046 { SP::F13 },
1047 { SP::F14 },
1048 { SP::F15 },
1049 { SP::F16 },
1050 { SP::F17 },
1051 { SP::F18 },
1052 { SP::F19 },
1053 { SP::F20 },
1054 { SP::F21 },
1055 { SP::F22 },
1056 { SP::F23 },
1057 { SP::F24 },
1058 { SP::F25 },
1059 { SP::F26 },
1060 { SP::F27 },
1061 { SP::F28 },
1062 { SP::F29 },
1063 { SP::F30 },
1064 { SP::F31 },
1065 { SP::D16 },
1066 { SP::D17 },
1067 { SP::D18 },
1068 { SP::D19 },
1069 { SP::D20 },
1070 { SP::D21 },
1071 { SP::D22 },
1072 { SP::D23 },
1073 { SP::D24 },
1074 { SP::D25 },
1075 { SP::D26 },
1076 { SP::D27 },
1077 { SP::D28 },
1078 { SP::D29 },
1079 { SP::D30 },
1080 { SP::D31 },
1081 { SP::FCC0 },
1082 { SP::FCC1 },
1083 { SP::FCC2 },
1084 { SP::FCC3 },
1085 { SP::G0 },
1086 { SP::G1 },
1087 { SP::G2 },
1088 { SP::G3 },
1089 { SP::G4 },
1090 { SP::G5 },
1091 { SP::G6 },
1092 { SP::G7 },
1093 { SP::I0 },
1094 { SP::I1 },
1095 { SP::I2 },
1096 { SP::I3 },
1097 { SP::I4 },
1098 { SP::I5 },
1099 { SP::I6 },
1100 { SP::I7 },
1101 { SP::L0 },
1102 { SP::L1 },
1103 { SP::L2 },
1104 { SP::L3 },
1105 { SP::L4 },
1106 { SP::L5 },
1107 { SP::L6 },
1108 { SP::L7 },
1109 { SP::O0 },
1110 { SP::O1 },
1111 { SP::O2 },
1112 { SP::O3 },
1113 { SP::O4 },
1114 { SP::O5 },
1115 { SP::O6 },
1116 { SP::O7 },
1117};
1118
1119namespace { // Register classes...
1120 // FCCRegs Register Class...
1121 const MCPhysReg FCCRegs[] = {
1122 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3,
1123 };
1124
1125 // FCCRegs Bit set.
1126 const uint8_t FCCRegsBits[] = {
1127 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
1128 };
1129
1130 // ASRRegs Register Class...
1131 const MCPhysReg ASRRegs[] = {
1132 SP::Y, SP::TICK, SP::ASR1, SP::ASR2, SP::ASR3, SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31,
1133 };
1134
1135 // ASRRegs Bit set.
1136 const uint8_t ASRRegsBits[] = {
1137 0x00, 0x00, 0x02, 0xfc, 0xff, 0xff, 0xff, 0x03,
1138 };
1139
1140 // CoprocRegs Register Class...
1141 const MCPhysReg CoprocRegs[] = {
1142 SP::C0, SP::C1, SP::C2, SP::C3, SP::C4, SP::C5, SP::C6, SP::C7, SP::C8, SP::C9, SP::C10, SP::C11, SP::C12, SP::C13, SP::C14, SP::C15, SP::C16, SP::C17, SP::C18, SP::C19, SP::C20, SP::C21, SP::C22, SP::C23, SP::C24, SP::C25, SP::C26, SP::C27, SP::C28, SP::C29, SP::C30, SP::C31,
1143 };
1144
1145 // CoprocRegs Bit set.
1146 const uint8_t CoprocRegsBits[] = {
1147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
1148 };
1149
1150 // FPRegs Register Class...
1151 const MCPhysReg FPRegs[] = {
1152 SP::F0, SP::F1, SP::F2, SP::F3, SP::F4, SP::F5, SP::F6, SP::F7, SP::F8, SP::F9, SP::F10, SP::F11, SP::F12, SP::F13, SP::F14, SP::F15, SP::F16, SP::F17, SP::F18, SP::F19, SP::F20, SP::F21, SP::F22, SP::F23, SP::F24, SP::F25, SP::F26, SP::F27, SP::F28, SP::F29, SP::F30, SP::F31,
1153 };
1154
1155 // FPRegs Bit set.
1156 const uint8_t FPRegsBits[] = {
1157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
1158 };
1159
1160 // IntRegs Register Class...
1161 const MCPhysReg IntRegs[] = {
1162 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7,
1163 };
1164
1165 // IntRegs Bit set.
1166 const uint8_t IntRegsBits[] = {
1167 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
1168 };
1169
1170 // GPRIncomingArg Register Class...
1171 const MCPhysReg GPRIncomingArg[] = {
1172 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5,
1173 };
1174
1175 // GPRIncomingArg Bit set.
1176 const uint8_t GPRIncomingArgBits[] = {
1177 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1178 };
1179
1180 // GPROutgoingArg Register Class...
1181 const MCPhysReg GPROutgoingArg[] = {
1182 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5,
1183 };
1184
1185 // GPROutgoingArg Bit set.
1186 const uint8_t GPROutgoingArgBits[] = {
1187 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1188 };
1189
1190 // DFPRegs Register Class...
1191 const MCPhysReg DFPRegs[] = {
1192 SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D24, SP::D25, SP::D26, SP::D27, SP::D28, SP::D29, SP::D30, SP::D31,
1193 };
1194
1195 // DFPRegs Bit set.
1196 const uint8_t DFPRegsBits[] = {
1197 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
1198 };
1199
1200 // I64Regs Register Class...
1201 const MCPhysReg I64Regs[] = {
1202 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7,
1203 };
1204
1205 // I64Regs Bit set.
1206 const uint8_t I64RegsBits[] = {
1207 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
1208 };
1209
1210 // PRRegs Register Class...
1211 const MCPhysReg PRRegs[] = {
1212 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE, SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, SP::OTHERWIN, SP::WSTATE, SP::GL, SP::VER,
1213 };
1214
1215 // PRRegs Bit set.
1216 const uint8_t PRRegsBits[] = {
1217 0x4e, 0xda, 0xfe, 0x02,
1218 };
1219
1220 // CoprocPair Register Class...
1221 const MCPhysReg CoprocPair[] = {
1222 SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7, SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15, SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23, SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31,
1223 };
1224
1225 // CoprocPair Bit set.
1226 const uint8_t CoprocPairBits[] = {
1227 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1228 };
1229
1230 // IntPair Register Class...
1231 const MCPhysReg IntPair[] = {
1232 SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7, SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7, SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7, SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
1233 };
1234
1235 // IntPair Bit set.
1236 const uint8_t IntPairBits[] = {
1237 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1238 };
1239
1240 // LowDFPRegs Register Class...
1241 const MCPhysReg LowDFPRegs[] = {
1242 SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15,
1243 };
1244
1245 // LowDFPRegs Bit set.
1246 const uint8_t LowDFPRegsBits[] = {
1247 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
1248 };
1249
1250 // I64Regs_and_GPRIncomingArg Register Class...
1251 const MCPhysReg I64Regs_and_GPRIncomingArg[] = {
1252 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5,
1253 };
1254
1255 // I64Regs_and_GPRIncomingArg Bit set.
1256 const uint8_t I64Regs_and_GPRIncomingArgBits[] = {
1257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1258 };
1259
1260 // I64Regs_and_GPROutgoingArg Register Class...
1261 const MCPhysReg I64Regs_and_GPROutgoingArg[] = {
1262 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5,
1263 };
1264
1265 // I64Regs_and_GPROutgoingArg Bit set.
1266 const uint8_t I64Regs_and_GPROutgoingArgBits[] = {
1267 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
1268 };
1269
1270 // IntPair_with_sub_even_in_GPRIncomingArg Register Class...
1271 const MCPhysReg IntPair_with_sub_even_in_GPRIncomingArg[] = {
1272 SP::I0_I1, SP::I2_I3, SP::I4_I5,
1273 };
1274
1275 // IntPair_with_sub_even_in_GPRIncomingArg Bit set.
1276 const uint8_t IntPair_with_sub_even_in_GPRIncomingArgBits[] = {
1277 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
1278 };
1279
1280 // IntPair_with_sub_even_in_GPROutgoingArg Register Class...
1281 const MCPhysReg IntPair_with_sub_even_in_GPROutgoingArg[] = {
1282 SP::O0_O1, SP::O2_O3, SP::O4_O5,
1283 };
1284
1285 // IntPair_with_sub_even_in_GPROutgoingArg Bit set.
1286 const uint8_t IntPair_with_sub_even_in_GPROutgoingArgBits[] = {
1287 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
1288 };
1289
1290 // PRRegs_and_ASRRegs Register Class...
1291 const MCPhysReg PRRegs_and_ASRRegs[] = {
1292 SP::TICK,
1293 };
1294
1295 // PRRegs_and_ASRRegs Bit set.
1296 const uint8_t PRRegs_and_ASRRegsBits[] = {
1297 0x00, 0x00, 0x02,
1298 };
1299
1300 // QFPRegs Register Class...
1301 const MCPhysReg QFPRegs[] = {
1302 SP::Q0, SP::Q1, SP::Q2, SP::Q3, SP::Q4, SP::Q5, SP::Q6, SP::Q7, SP::Q8, SP::Q9, SP::Q10, SP::Q11, SP::Q12, SP::Q13, SP::Q14, SP::Q15,
1303 };
1304
1305 // QFPRegs Bit set.
1306 const uint8_t QFPRegsBits[] = {
1307 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
1308 };
1309
1310 // LowQFPRegs Register Class...
1311 const MCPhysReg LowQFPRegs[] = {
1312 SP::Q0, SP::Q1, SP::Q2, SP::Q3, SP::Q4, SP::Q5, SP::Q6, SP::Q7,
1313 };
1314
1315 // LowQFPRegs Bit set.
1316 const uint8_t LowQFPRegsBits[] = {
1317 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
1318 };
1319
1320} // end anonymous namespace
1321
1322
1323#ifdef __GNUC__
1324#pragma GCC diagnostic push
1325#pragma GCC diagnostic ignored "-Woverlength-strings"
1326#endif
1327extern const char SparcRegClassStrings[] = {
1328 /* 0 */ "I64Regs_and_GPRIncomingArg\0"
1329 /* 27 */ "IntPair_with_sub_even_in_GPRIncomingArg\0"
1330 /* 67 */ "I64Regs_and_GPROutgoingArg\0"
1331 /* 94 */ "IntPair_with_sub_even_in_GPROutgoingArg\0"
1332 /* 134 */ "CoprocPair\0"
1333 /* 145 */ "IntPair\0"
1334 /* 153 */ "I64Regs\0"
1335 /* 161 */ "FCCRegs\0"
1336 /* 169 */ "LowDFPRegs\0"
1337 /* 180 */ "LowQFPRegs\0"
1338 /* 191 */ "PRRegs\0"
1339 /* 198 */ "PRRegs_and_ASRRegs\0"
1340 /* 217 */ "CoprocRegs\0"
1341 /* 228 */ "IntRegs\0"
1342};
1343#ifdef __GNUC__
1344#pragma GCC diagnostic pop
1345#endif
1346
1347extern const MCRegisterClass SparcMCRegisterClasses[] = {
1348 { FCCRegs, FCCRegsBits, 161, 4, sizeof(FCCRegsBits), SP::FCCRegsRegClassID, 1, 1, true, false },
1349 { ASRRegs, ASRRegsBits, 209, 33, sizeof(ASRRegsBits), SP::ASRRegsRegClassID, 32, 1, false, false },
1350 { CoprocRegs, CoprocRegsBits, 217, 32, sizeof(CoprocRegsBits), SP::CoprocRegsRegClassID, 32, 1, false, false },
1351 { FPRegs, FPRegsBits, 173, 32, sizeof(FPRegsBits), SP::FPRegsRegClassID, 32, 1, true, false },
1352 { IntRegs, IntRegsBits, 228, 32, sizeof(IntRegsBits), SP::IntRegsRegClassID, 32, 1, true, false },
1353 { GPRIncomingArg, GPRIncomingArgBits, 12, 6, sizeof(GPRIncomingArgBits), SP::GPRIncomingArgRegClassID, 32, 1, true, false },
1354 { GPROutgoingArg, GPROutgoingArgBits, 79, 6, sizeof(GPROutgoingArgBits), SP::GPROutgoingArgRegClassID, 32, 1, true, false },
1355 { DFPRegs, DFPRegsBits, 172, 32, sizeof(DFPRegsBits), SP::DFPRegsRegClassID, 64, 1, true, false },
1356 { I64Regs, I64RegsBits, 153, 32, sizeof(I64RegsBits), SP::I64RegsRegClassID, 64, 1, true, false },
1357 { PRRegs, PRRegsBits, 191, 17, sizeof(PRRegsBits), SP::PRRegsRegClassID, 64, 1, true, false },
1358 { CoprocPair, CoprocPairBits, 134, 16, sizeof(CoprocPairBits), SP::CoprocPairRegClassID, 64, 1, false, false },
1359 { IntPair, IntPairBits, 145, 16, sizeof(IntPairBits), SP::IntPairRegClassID, 64, 1, true, false },
1360 { LowDFPRegs, LowDFPRegsBits, 169, 16, sizeof(LowDFPRegsBits), SP::LowDFPRegsRegClassID, 64, 1, true, false },
1361 { I64Regs_and_GPRIncomingArg, I64Regs_and_GPRIncomingArgBits, 0, 6, sizeof(I64Regs_and_GPRIncomingArgBits), SP::I64Regs_and_GPRIncomingArgRegClassID, 64, 1, true, false },
1362 { I64Regs_and_GPROutgoingArg, I64Regs_and_GPROutgoingArgBits, 67, 6, sizeof(I64Regs_and_GPROutgoingArgBits), SP::I64Regs_and_GPROutgoingArgRegClassID, 64, 1, true, false },
1363 { IntPair_with_sub_even_in_GPRIncomingArg, IntPair_with_sub_even_in_GPRIncomingArgBits, 27, 3, sizeof(IntPair_with_sub_even_in_GPRIncomingArgBits), SP::IntPair_with_sub_even_in_GPRIncomingArgRegClassID, 64, 1, true, false },
1364 { IntPair_with_sub_even_in_GPROutgoingArg, IntPair_with_sub_even_in_GPROutgoingArgBits, 94, 3, sizeof(IntPair_with_sub_even_in_GPROutgoingArgBits), SP::IntPair_with_sub_even_in_GPROutgoingArgRegClassID, 64, 1, true, false },
1365 { PRRegs_and_ASRRegs, PRRegs_and_ASRRegsBits, 198, 1, sizeof(PRRegs_and_ASRRegsBits), SP::PRRegs_and_ASRRegsRegClassID, 64, 1, true, false },
1366 { QFPRegs, QFPRegsBits, 183, 16, sizeof(QFPRegsBits), SP::QFPRegsRegClassID, 128, 1, true, false },
1367 { LowQFPRegs, LowQFPRegsBits, 180, 8, sizeof(LowQFPRegsBits), SP::LowQFPRegsRegClassID, 128, 1, true, false },
1368};
1369
1370// SP Dwarf<->LLVM register mappings.
1371extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[] = {
1372 { 0U, SP::G0 },
1373 { 1U, SP::G1 },
1374 { 2U, SP::G2 },
1375 { 3U, SP::G3 },
1376 { 4U, SP::G4 },
1377 { 5U, SP::G5 },
1378 { 6U, SP::G6 },
1379 { 7U, SP::G7 },
1380 { 8U, SP::O0 },
1381 { 9U, SP::O1 },
1382 { 10U, SP::O2 },
1383 { 11U, SP::O3 },
1384 { 12U, SP::O4 },
1385 { 13U, SP::O5 },
1386 { 14U, SP::O6 },
1387 { 15U, SP::O7 },
1388 { 16U, SP::L0 },
1389 { 17U, SP::L1 },
1390 { 18U, SP::L2 },
1391 { 19U, SP::L3 },
1392 { 20U, SP::L4 },
1393 { 21U, SP::L5 },
1394 { 22U, SP::L6 },
1395 { 23U, SP::L7 },
1396 { 24U, SP::I0 },
1397 { 25U, SP::I1 },
1398 { 26U, SP::I2 },
1399 { 27U, SP::I3 },
1400 { 28U, SP::I4 },
1401 { 29U, SP::I5 },
1402 { 30U, SP::I6 },
1403 { 31U, SP::I7 },
1404 { 32U, SP::F0 },
1405 { 33U, SP::F1 },
1406 { 34U, SP::F2 },
1407 { 35U, SP::F3 },
1408 { 36U, SP::F4 },
1409 { 37U, SP::F5 },
1410 { 38U, SP::F6 },
1411 { 39U, SP::F7 },
1412 { 40U, SP::F8 },
1413 { 41U, SP::F9 },
1414 { 42U, SP::F10 },
1415 { 43U, SP::F11 },
1416 { 44U, SP::F12 },
1417 { 45U, SP::F13 },
1418 { 46U, SP::F14 },
1419 { 47U, SP::F15 },
1420 { 48U, SP::F16 },
1421 { 49U, SP::F17 },
1422 { 50U, SP::F18 },
1423 { 51U, SP::F19 },
1424 { 52U, SP::F20 },
1425 { 53U, SP::F21 },
1426 { 54U, SP::F22 },
1427 { 55U, SP::F23 },
1428 { 56U, SP::F24 },
1429 { 57U, SP::F25 },
1430 { 58U, SP::F26 },
1431 { 59U, SP::F27 },
1432 { 60U, SP::F28 },
1433 { 61U, SP::F29 },
1434 { 62U, SP::F30 },
1435 { 63U, SP::F31 },
1436 { 64U, SP::Y },
1437 { 72U, SP::D0 },
1438 { 73U, SP::D1 },
1439 { 74U, SP::D2 },
1440 { 75U, SP::D3 },
1441 { 76U, SP::D4 },
1442 { 77U, SP::D5 },
1443 { 78U, SP::D6 },
1444 { 79U, SP::D7 },
1445 { 80U, SP::D8 },
1446 { 81U, SP::D9 },
1447 { 82U, SP::D10 },
1448 { 83U, SP::D11 },
1449 { 84U, SP::D12 },
1450 { 85U, SP::D13 },
1451 { 86U, SP::D14 },
1452 { 87U, SP::D15 },
1453};
1454extern const unsigned SPDwarfFlavour0Dwarf2LSize = std::size(SPDwarfFlavour0Dwarf2L);
1455
1456extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[] = {
1457 { 0U, SP::G0 },
1458 { 1U, SP::G1 },
1459 { 2U, SP::G2 },
1460 { 3U, SP::G3 },
1461 { 4U, SP::G4 },
1462 { 5U, SP::G5 },
1463 { 6U, SP::G6 },
1464 { 7U, SP::G7 },
1465 { 8U, SP::O0 },
1466 { 9U, SP::O1 },
1467 { 10U, SP::O2 },
1468 { 11U, SP::O3 },
1469 { 12U, SP::O4 },
1470 { 13U, SP::O5 },
1471 { 14U, SP::O6 },
1472 { 15U, SP::O7 },
1473 { 16U, SP::L0 },
1474 { 17U, SP::L1 },
1475 { 18U, SP::L2 },
1476 { 19U, SP::L3 },
1477 { 20U, SP::L4 },
1478 { 21U, SP::L5 },
1479 { 22U, SP::L6 },
1480 { 23U, SP::L7 },
1481 { 24U, SP::I0 },
1482 { 25U, SP::I1 },
1483 { 26U, SP::I2 },
1484 { 27U, SP::I3 },
1485 { 28U, SP::I4 },
1486 { 29U, SP::I5 },
1487 { 30U, SP::I6 },
1488 { 31U, SP::I7 },
1489 { 32U, SP::F0 },
1490 { 33U, SP::F1 },
1491 { 34U, SP::F2 },
1492 { 35U, SP::F3 },
1493 { 36U, SP::F4 },
1494 { 37U, SP::F5 },
1495 { 38U, SP::F6 },
1496 { 39U, SP::F7 },
1497 { 40U, SP::F8 },
1498 { 41U, SP::F9 },
1499 { 42U, SP::F10 },
1500 { 43U, SP::F11 },
1501 { 44U, SP::F12 },
1502 { 45U, SP::F13 },
1503 { 46U, SP::F14 },
1504 { 47U, SP::F15 },
1505 { 48U, SP::F16 },
1506 { 49U, SP::F17 },
1507 { 50U, SP::F18 },
1508 { 51U, SP::F19 },
1509 { 52U, SP::F20 },
1510 { 53U, SP::F21 },
1511 { 54U, SP::F22 },
1512 { 55U, SP::F23 },
1513 { 56U, SP::F24 },
1514 { 57U, SP::F25 },
1515 { 58U, SP::F26 },
1516 { 59U, SP::F27 },
1517 { 60U, SP::F28 },
1518 { 61U, SP::F29 },
1519 { 62U, SP::F30 },
1520 { 63U, SP::F31 },
1521 { 64U, SP::Y },
1522 { 72U, SP::D0 },
1523 { 73U, SP::D1 },
1524 { 74U, SP::D2 },
1525 { 75U, SP::D3 },
1526 { 76U, SP::D4 },
1527 { 77U, SP::D5 },
1528 { 78U, SP::D6 },
1529 { 79U, SP::D7 },
1530 { 80U, SP::D8 },
1531 { 81U, SP::D9 },
1532 { 82U, SP::D10 },
1533 { 83U, SP::D11 },
1534 { 84U, SP::D12 },
1535 { 85U, SP::D13 },
1536 { 86U, SP::D14 },
1537 { 87U, SP::D15 },
1538};
1539extern const unsigned SPEHFlavour0Dwarf2LSize = std::size(SPEHFlavour0Dwarf2L);
1540
1541extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[] = {
1542 { SP::Y, 64U },
1543 { SP::D0, 72U },
1544 { SP::D1, 73U },
1545 { SP::D2, 74U },
1546 { SP::D3, 75U },
1547 { SP::D4, 76U },
1548 { SP::D5, 77U },
1549 { SP::D6, 78U },
1550 { SP::D7, 79U },
1551 { SP::D8, 80U },
1552 { SP::D9, 81U },
1553 { SP::D10, 82U },
1554 { SP::D11, 83U },
1555 { SP::D12, 84U },
1556 { SP::D13, 85U },
1557 { SP::D14, 86U },
1558 { SP::D15, 87U },
1559 { SP::F0, 32U },
1560 { SP::F1, 33U },
1561 { SP::F2, 34U },
1562 { SP::F3, 35U },
1563 { SP::F4, 36U },
1564 { SP::F5, 37U },
1565 { SP::F6, 38U },
1566 { SP::F7, 39U },
1567 { SP::F8, 40U },
1568 { SP::F9, 41U },
1569 { SP::F10, 42U },
1570 { SP::F11, 43U },
1571 { SP::F12, 44U },
1572 { SP::F13, 45U },
1573 { SP::F14, 46U },
1574 { SP::F15, 47U },
1575 { SP::F16, 48U },
1576 { SP::F17, 49U },
1577 { SP::F18, 50U },
1578 { SP::F19, 51U },
1579 { SP::F20, 52U },
1580 { SP::F21, 53U },
1581 { SP::F22, 54U },
1582 { SP::F23, 55U },
1583 { SP::F24, 56U },
1584 { SP::F25, 57U },
1585 { SP::F26, 58U },
1586 { SP::F27, 59U },
1587 { SP::F28, 60U },
1588 { SP::F29, 61U },
1589 { SP::F30, 62U },
1590 { SP::F31, 63U },
1591 { SP::G0, 0U },
1592 { SP::G1, 1U },
1593 { SP::G2, 2U },
1594 { SP::G3, 3U },
1595 { SP::G4, 4U },
1596 { SP::G5, 5U },
1597 { SP::G6, 6U },
1598 { SP::G7, 7U },
1599 { SP::I0, 24U },
1600 { SP::I1, 25U },
1601 { SP::I2, 26U },
1602 { SP::I3, 27U },
1603 { SP::I4, 28U },
1604 { SP::I5, 29U },
1605 { SP::I6, 30U },
1606 { SP::I7, 31U },
1607 { SP::L0, 16U },
1608 { SP::L1, 17U },
1609 { SP::L2, 18U },
1610 { SP::L3, 19U },
1611 { SP::L4, 20U },
1612 { SP::L5, 21U },
1613 { SP::L6, 22U },
1614 { SP::L7, 23U },
1615 { SP::O0, 8U },
1616 { SP::O1, 9U },
1617 { SP::O2, 10U },
1618 { SP::O3, 11U },
1619 { SP::O4, 12U },
1620 { SP::O5, 13U },
1621 { SP::O6, 14U },
1622 { SP::O7, 15U },
1623};
1624extern const unsigned SPDwarfFlavour0L2DwarfSize = std::size(SPDwarfFlavour0L2Dwarf);
1625
1626extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[] = {
1627 { SP::Y, 64U },
1628 { SP::D0, 72U },
1629 { SP::D1, 73U },
1630 { SP::D2, 74U },
1631 { SP::D3, 75U },
1632 { SP::D4, 76U },
1633 { SP::D5, 77U },
1634 { SP::D6, 78U },
1635 { SP::D7, 79U },
1636 { SP::D8, 80U },
1637 { SP::D9, 81U },
1638 { SP::D10, 82U },
1639 { SP::D11, 83U },
1640 { SP::D12, 84U },
1641 { SP::D13, 85U },
1642 { SP::D14, 86U },
1643 { SP::D15, 87U },
1644 { SP::F0, 32U },
1645 { SP::F1, 33U },
1646 { SP::F2, 34U },
1647 { SP::F3, 35U },
1648 { SP::F4, 36U },
1649 { SP::F5, 37U },
1650 { SP::F6, 38U },
1651 { SP::F7, 39U },
1652 { SP::F8, 40U },
1653 { SP::F9, 41U },
1654 { SP::F10, 42U },
1655 { SP::F11, 43U },
1656 { SP::F12, 44U },
1657 { SP::F13, 45U },
1658 { SP::F14, 46U },
1659 { SP::F15, 47U },
1660 { SP::F16, 48U },
1661 { SP::F17, 49U },
1662 { SP::F18, 50U },
1663 { SP::F19, 51U },
1664 { SP::F20, 52U },
1665 { SP::F21, 53U },
1666 { SP::F22, 54U },
1667 { SP::F23, 55U },
1668 { SP::F24, 56U },
1669 { SP::F25, 57U },
1670 { SP::F26, 58U },
1671 { SP::F27, 59U },
1672 { SP::F28, 60U },
1673 { SP::F29, 61U },
1674 { SP::F30, 62U },
1675 { SP::F31, 63U },
1676 { SP::G0, 0U },
1677 { SP::G1, 1U },
1678 { SP::G2, 2U },
1679 { SP::G3, 3U },
1680 { SP::G4, 4U },
1681 { SP::G5, 5U },
1682 { SP::G6, 6U },
1683 { SP::G7, 7U },
1684 { SP::I0, 24U },
1685 { SP::I1, 25U },
1686 { SP::I2, 26U },
1687 { SP::I3, 27U },
1688 { SP::I4, 28U },
1689 { SP::I5, 29U },
1690 { SP::I6, 30U },
1691 { SP::I7, 31U },
1692 { SP::L0, 16U },
1693 { SP::L1, 17U },
1694 { SP::L2, 18U },
1695 { SP::L3, 19U },
1696 { SP::L4, 20U },
1697 { SP::L5, 21U },
1698 { SP::L6, 22U },
1699 { SP::L7, 23U },
1700 { SP::O0, 8U },
1701 { SP::O1, 9U },
1702 { SP::O2, 10U },
1703 { SP::O3, 11U },
1704 { SP::O4, 12U },
1705 { SP::O5, 13U },
1706 { SP::O6, 14U },
1707 { SP::O7, 15U },
1708};
1709extern const unsigned SPEHFlavour0L2DwarfSize = std::size(SPEHFlavour0L2Dwarf);
1710
1711extern const uint16_t SparcRegEncodingTable[] = {
1712 0,
1713 11,
1714 10,
1715 12,
1716 0,
1717 0,
1718 9,
1719 0,
1720 0,
1721 16,
1722 0,
1723 13,
1724 8,
1725 0,
1726 6,
1727 5,
1728 0,
1729 4,
1730 7,
1731 1,
1732 0,
1733 2,
1734 3,
1735 31,
1736 0,
1737 14,
1738 0,
1739 1,
1740 2,
1741 3,
1742 4,
1743 5,
1744 6,
1745 7,
1746 8,
1747 9,
1748 10,
1749 11,
1750 12,
1751 13,
1752 14,
1753 15,
1754 16,
1755 17,
1756 18,
1757 19,
1758 20,
1759 21,
1760 22,
1761 23,
1762 24,
1763 25,
1764 26,
1765 27,
1766 28,
1767 29,
1768 30,
1769 31,
1770 0,
1771 1,
1772 2,
1773 3,
1774 4,
1775 5,
1776 6,
1777 7,
1778 8,
1779 9,
1780 10,
1781 11,
1782 12,
1783 13,
1784 14,
1785 15,
1786 16,
1787 17,
1788 18,
1789 19,
1790 20,
1791 21,
1792 22,
1793 23,
1794 24,
1795 25,
1796 26,
1797 27,
1798 28,
1799 29,
1800 30,
1801 31,
1802 0,
1803 2,
1804 4,
1805 6,
1806 8,
1807 10,
1808 12,
1809 14,
1810 16,
1811 18,
1812 20,
1813 22,
1814 24,
1815 26,
1816 28,
1817 30,
1818 1,
1819 3,
1820 5,
1821 7,
1822 9,
1823 11,
1824 13,
1825 15,
1826 17,
1827 19,
1828 21,
1829 23,
1830 25,
1831 27,
1832 29,
1833 31,
1834 0,
1835 1,
1836 2,
1837 3,
1838 4,
1839 5,
1840 6,
1841 7,
1842 8,
1843 9,
1844 10,
1845 11,
1846 12,
1847 13,
1848 14,
1849 15,
1850 16,
1851 17,
1852 18,
1853 19,
1854 20,
1855 21,
1856 22,
1857 23,
1858 24,
1859 25,
1860 26,
1861 27,
1862 28,
1863 29,
1864 30,
1865 31,
1866 0,
1867 1,
1868 2,
1869 3,
1870 0,
1871 1,
1872 2,
1873 3,
1874 4,
1875 5,
1876 6,
1877 7,
1878 24,
1879 25,
1880 26,
1881 27,
1882 28,
1883 29,
1884 30,
1885 31,
1886 16,
1887 17,
1888 18,
1889 19,
1890 20,
1891 21,
1892 22,
1893 23,
1894 8,
1895 9,
1896 10,
1897 11,
1898 12,
1899 13,
1900 14,
1901 15,
1902 0,
1903 4,
1904 8,
1905 12,
1906 16,
1907 20,
1908 24,
1909 28,
1910 1,
1911 5,
1912 9,
1913 13,
1914 17,
1915 21,
1916 25,
1917 29,
1918 0,
1919 2,
1920 4,
1921 6,
1922 8,
1923 10,
1924 12,
1925 14,
1926 16,
1927 18,
1928 20,
1929 22,
1930 24,
1931 26,
1932 28,
1933 30,
1934 0,
1935 2,
1936 4,
1937 6,
1938 24,
1939 26,
1940 28,
1941 30,
1942 16,
1943 18,
1944 20,
1945 22,
1946 8,
1947 10,
1948 12,
1949 14,
1950};
1951static inline void InitSparcMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1952 RI->InitMCRegisterInfo(SparcRegDesc, 238, RA, PC, SparcMCRegisterClasses, 20, SparcRegUnitRoots, 173, SparcRegDiffLists, SparcLaneMaskLists, SparcRegStrings, SparcRegClassStrings, SparcSubRegIdxLists, 7,
1953SparcRegEncodingTable);
1954
1955 switch (DwarfFlavour) {
1956 default:
1957 llvm_unreachable("Unknown DWARF flavour");
1958 case 0:
1959 RI->mapDwarfRegsToLLVMRegs(SPDwarfFlavour0Dwarf2L, SPDwarfFlavour0Dwarf2LSize, false);
1960 break;
1961 }
1962 switch (EHFlavour) {
1963 default:
1964 llvm_unreachable("Unknown DWARF flavour");
1965 case 0:
1966 RI->mapDwarfRegsToLLVMRegs(SPEHFlavour0Dwarf2L, SPEHFlavour0Dwarf2LSize, true);
1967 break;
1968 }
1969 switch (DwarfFlavour) {
1970 default:
1971 llvm_unreachable("Unknown DWARF flavour");
1972 case 0:
1973 RI->mapLLVMRegsToDwarfRegs(SPDwarfFlavour0L2Dwarf, SPDwarfFlavour0L2DwarfSize, false);
1974 break;
1975 }
1976 switch (EHFlavour) {
1977 default:
1978 llvm_unreachable("Unknown DWARF flavour");
1979 case 0:
1980 RI->mapLLVMRegsToDwarfRegs(SPEHFlavour0L2Dwarf, SPEHFlavour0L2DwarfSize, true);
1981 break;
1982 }
1983}
1984
1985} // end namespace llvm
1986
1987#endif // GET_REGINFO_MC_DESC
1988
1989/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1990|* *|
1991|* Register Information Header Fragment *|
1992|* *|
1993|* Automatically generated file, do not edit! *|
1994|* *|
1995\*===----------------------------------------------------------------------===*/
1996
1997
1998#ifdef GET_REGINFO_HEADER
1999#undef GET_REGINFO_HEADER
2000
2001#include "llvm/CodeGen/TargetRegisterInfo.h"
2002
2003namespace llvm {
2004
2005class SparcFrameLowering;
2006
2007struct SparcGenRegisterInfo : public TargetRegisterInfo {
2008 explicit SparcGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
2009 unsigned PC = 0, unsigned HwMode = 0);
2010 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
2011 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2012 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2013 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
2014 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
2015 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
2016 unsigned getRegUnitWeight(unsigned RegUnit) const override;
2017 unsigned getNumRegPressureSets() const override;
2018 const char *getRegPressureSetName(unsigned Idx) const override;
2019 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
2020 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
2021 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
2022 ArrayRef<const char *> getRegMaskNames() const override;
2023 ArrayRef<const uint32_t *> getRegMasks() const override;
2024 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
2025 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
2026 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
2027 bool isConstantPhysReg(MCRegister PhysReg) const override final;
2028 /// Devirtualized TargetFrameLowering.
2029 static const SparcFrameLowering *getFrameLowering(
2030 const MachineFunction &MF);
2031};
2032
2033namespace SP { // Register classes
2034 extern const TargetRegisterClass FCCRegsRegClass;
2035 extern const TargetRegisterClass ASRRegsRegClass;
2036 extern const TargetRegisterClass CoprocRegsRegClass;
2037 extern const TargetRegisterClass FPRegsRegClass;
2038 extern const TargetRegisterClass IntRegsRegClass;
2039 extern const TargetRegisterClass GPRIncomingArgRegClass;
2040 extern const TargetRegisterClass GPROutgoingArgRegClass;
2041 extern const TargetRegisterClass DFPRegsRegClass;
2042 extern const TargetRegisterClass I64RegsRegClass;
2043 extern const TargetRegisterClass PRRegsRegClass;
2044 extern const TargetRegisterClass CoprocPairRegClass;
2045 extern const TargetRegisterClass IntPairRegClass;
2046 extern const TargetRegisterClass LowDFPRegsRegClass;
2047 extern const TargetRegisterClass I64Regs_and_GPRIncomingArgRegClass;
2048 extern const TargetRegisterClass I64Regs_and_GPROutgoingArgRegClass;
2049 extern const TargetRegisterClass IntPair_with_sub_even_in_GPRIncomingArgRegClass;
2050 extern const TargetRegisterClass IntPair_with_sub_even_in_GPROutgoingArgRegClass;
2051 extern const TargetRegisterClass PRRegs_and_ASRRegsRegClass;
2052 extern const TargetRegisterClass QFPRegsRegClass;
2053 extern const TargetRegisterClass LowQFPRegsRegClass;
2054} // end namespace SP
2055
2056} // end namespace llvm
2057
2058#endif // GET_REGINFO_HEADER
2059
2060/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2061|* *|
2062|* Target Register and Register Classes Information *|
2063|* *|
2064|* Automatically generated file, do not edit! *|
2065|* *|
2066\*===----------------------------------------------------------------------===*/
2067
2068
2069#ifdef GET_REGINFO_TARGET_DESC
2070#undef GET_REGINFO_TARGET_DESC
2071
2072namespace llvm {
2073
2074extern const MCRegisterClass SparcMCRegisterClasses[];
2075
2076static const MVT::SimpleValueType VTLists[] = {
2077 /* 0 */ MVT::i1, MVT::Other,
2078 /* 2 */ MVT::i32, MVT::Other,
2079 /* 4 */ MVT::i32, MVT::i64, MVT::Other,
2080 /* 7 */ MVT::f32, MVT::Other,
2081 /* 9 */ MVT::f64, MVT::Other,
2082 /* 11 */ MVT::f128, MVT::Other,
2083 /* 13 */ MVT::v2i32, MVT::Other,
2084};
2085
2086static const char *SubRegIndexNameTable[] = { "sub_even", "sub_even64", "sub_odd", "sub_odd64", "sub_odd64_then_sub_even", "sub_odd64_then_sub_odd", "" };
2087
2088static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
2089 { 65535, 65535 },
2090 { 0, 32 }, // sub_even
2091 { 0, 64 }, // sub_even64
2092 { 32, 32 }, // sub_odd
2093 { 64, 64 }, // sub_odd64
2094 { 64, 32 }, // sub_odd64_then_sub_even
2095 { 96, 32 }, // sub_odd64_then_sub_odd
2096};
2097
2098
2099static const LaneBitmask SubRegIndexLaneMaskTable[] = {
2100 LaneBitmask::getAll(),
2101 LaneBitmask(0x0000000000000001), // sub_even
2102 LaneBitmask(0x0000000000000003), // sub_even64
2103 LaneBitmask(0x0000000000000002), // sub_odd
2104 LaneBitmask(0x000000000000000C), // sub_odd64
2105 LaneBitmask(0x0000000000000004), // sub_odd64_then_sub_even
2106 LaneBitmask(0x0000000000000008), // sub_odd64_then_sub_odd
2107 };
2108
2109
2110
2111static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
2112 // Mode = 0 (Default)
2113 { 1, 1, 1, /*VTLists+*/0 }, // FCCRegs
2114 { 32, 32, 32, /*VTLists+*/2 }, // ASRRegs
2115 { 32, 32, 32, /*VTLists+*/2 }, // CoprocRegs
2116 { 32, 32, 32, /*VTLists+*/7 }, // FPRegs
2117 { 32, 32, 32, /*VTLists+*/4 }, // IntRegs
2118 { 32, 32, 32, /*VTLists+*/4 }, // GPRIncomingArg
2119 { 32, 32, 32, /*VTLists+*/4 }, // GPROutgoingArg
2120 { 64, 64, 64, /*VTLists+*/9 }, // DFPRegs
2121 { 64, 64, 64, /*VTLists+*/5 }, // I64Regs
2122 { 64, 64, 64, /*VTLists+*/5 }, // PRRegs
2123 { 64, 64, 64, /*VTLists+*/13 }, // CoprocPair
2124 { 64, 64, 64, /*VTLists+*/13 }, // IntPair
2125 { 64, 64, 64, /*VTLists+*/9 }, // LowDFPRegs
2126 { 64, 64, 64, /*VTLists+*/5 }, // I64Regs_and_GPRIncomingArg
2127 { 64, 64, 64, /*VTLists+*/5 }, // I64Regs_and_GPROutgoingArg
2128 { 64, 64, 64, /*VTLists+*/13 }, // IntPair_with_sub_even_in_GPRIncomingArg
2129 { 64, 64, 64, /*VTLists+*/13 }, // IntPair_with_sub_even_in_GPROutgoingArg
2130 { 64, 64, 64, /*VTLists+*/5 }, // PRRegs_and_ASRRegs
2131 { 128, 128, 128, /*VTLists+*/11 }, // QFPRegs
2132 { 128, 128, 128, /*VTLists+*/11 }, // LowQFPRegs
2133};
2134
2135static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
2136
2137static const uint32_t FCCRegsSubClassMask[] = {
2138 0x00000001,
2139};
2140
2141static const uint32_t ASRRegsSubClassMask[] = {
2142 0x00020002,
2143};
2144
2145static const uint32_t CoprocRegsSubClassMask[] = {
2146 0x00000004,
2147 0x00000400, // sub_even
2148 0x00000400, // sub_odd
2149};
2150
2151static const uint32_t FPRegsSubClassMask[] = {
2152 0x00000008,
2153 0x00081000, // sub_even
2154 0x00081000, // sub_odd
2155 0x00080000, // sub_odd64_then_sub_even
2156 0x00080000, // sub_odd64_then_sub_odd
2157};
2158
2159static const uint32_t IntRegsSubClassMask[] = {
2160 0x00006170,
2161 0x00018800, // sub_even
2162 0x00018800, // sub_odd
2163};
2164
2165static const uint32_t GPRIncomingArgSubClassMask[] = {
2166 0x00002020,
2167 0x00008000, // sub_even
2168 0x00008000, // sub_odd
2169};
2170
2171static const uint32_t GPROutgoingArgSubClassMask[] = {
2172 0x00004040,
2173 0x00010000, // sub_even
2174 0x00010000, // sub_odd
2175};
2176
2177static const uint32_t DFPRegsSubClassMask[] = {
2178 0x00001080,
2179 0x000c0000, // sub_even64
2180 0x000c0000, // sub_odd64
2181};
2182
2183static const uint32_t I64RegsSubClassMask[] = {
2184 0x00006100,
2185 0x00018800, // sub_even
2186 0x00018800, // sub_odd
2187};
2188
2189static const uint32_t PRRegsSubClassMask[] = {
2190 0x00020200,
2191};
2192
2193static const uint32_t CoprocPairSubClassMask[] = {
2194 0x00000400,
2195};
2196
2197static const uint32_t IntPairSubClassMask[] = {
2198 0x00018800,
2199};
2200
2201static const uint32_t LowDFPRegsSubClassMask[] = {
2202 0x00001000,
2203 0x00080000, // sub_even64
2204 0x00080000, // sub_odd64
2205};
2206
2207static const uint32_t I64Regs_and_GPRIncomingArgSubClassMask[] = {
2208 0x00002000,
2209 0x00008000, // sub_even
2210 0x00008000, // sub_odd
2211};
2212
2213static const uint32_t I64Regs_and_GPROutgoingArgSubClassMask[] = {
2214 0x00004000,
2215 0x00010000, // sub_even
2216 0x00010000, // sub_odd
2217};
2218
2219static const uint32_t IntPair_with_sub_even_in_GPRIncomingArgSubClassMask[] = {
2220 0x00008000,
2221};
2222
2223static const uint32_t IntPair_with_sub_even_in_GPROutgoingArgSubClassMask[] = {
2224 0x00010000,
2225};
2226
2227static const uint32_t PRRegs_and_ASRRegsSubClassMask[] = {
2228 0x00020000,
2229};
2230
2231static const uint32_t QFPRegsSubClassMask[] = {
2232 0x000c0000,
2233};
2234
2235static const uint32_t LowQFPRegsSubClassMask[] = {
2236 0x00080000,
2237};
2238
2239static const uint16_t SuperRegIdxSeqs[] = {
2240 /* 0 */ 1, 3, 0,
2241 /* 3 */ 2, 4, 0,
2242 /* 6 */ 1, 3, 5, 6, 0,
2243};
2244
2245static const TargetRegisterClass *const GPRIncomingArgSuperclasses[] = {
2246 &SP::IntRegsRegClass,
2247 nullptr
2248};
2249
2250static const TargetRegisterClass *const GPROutgoingArgSuperclasses[] = {
2251 &SP::IntRegsRegClass,
2252 nullptr
2253};
2254
2255static const TargetRegisterClass *const I64RegsSuperclasses[] = {
2256 &SP::IntRegsRegClass,
2257 nullptr
2258};
2259
2260static const TargetRegisterClass *const LowDFPRegsSuperclasses[] = {
2261 &SP::DFPRegsRegClass,
2262 nullptr
2263};
2264
2265static const TargetRegisterClass *const I64Regs_and_GPRIncomingArgSuperclasses[] = {
2266 &SP::IntRegsRegClass,
2267 &SP::GPRIncomingArgRegClass,
2268 &SP::I64RegsRegClass,
2269 nullptr
2270};
2271
2272static const TargetRegisterClass *const I64Regs_and_GPROutgoingArgSuperclasses[] = {
2273 &SP::IntRegsRegClass,
2274 &SP::GPROutgoingArgRegClass,
2275 &SP::I64RegsRegClass,
2276 nullptr
2277};
2278
2279static const TargetRegisterClass *const IntPair_with_sub_even_in_GPRIncomingArgSuperclasses[] = {
2280 &SP::IntPairRegClass,
2281 nullptr
2282};
2283
2284static const TargetRegisterClass *const IntPair_with_sub_even_in_GPROutgoingArgSuperclasses[] = {
2285 &SP::IntPairRegClass,
2286 nullptr
2287};
2288
2289static const TargetRegisterClass *const PRRegs_and_ASRRegsSuperclasses[] = {
2290 &SP::ASRRegsRegClass,
2291 &SP::PRRegsRegClass,
2292 nullptr
2293};
2294
2295static const TargetRegisterClass *const LowQFPRegsSuperclasses[] = {
2296 &SP::QFPRegsRegClass,
2297 nullptr
2298};
2299
2300
2301namespace SP { // Register class instances
2302 extern const TargetRegisterClass FCCRegsRegClass = {
2303 &SparcMCRegisterClasses[FCCRegsRegClassID],
2304 FCCRegsSubClassMask,
2305 SuperRegIdxSeqs + 2,
2306 LaneBitmask(0x0000000000000001),
2307 0,
2308 false,
2309 0x00, /* TSFlags */
2310 false, /* HasDisjunctSubRegs */
2311 false, /* CoveredBySubRegs */
2312 NullRegClasses,
2313 nullptr
2314 };
2315
2316 extern const TargetRegisterClass ASRRegsRegClass = {
2317 &SparcMCRegisterClasses[ASRRegsRegClassID],
2318 ASRRegsSubClassMask,
2319 SuperRegIdxSeqs + 2,
2320 LaneBitmask(0x0000000000000001),
2321 0,
2322 false,
2323 0x00, /* TSFlags */
2324 false, /* HasDisjunctSubRegs */
2325 false, /* CoveredBySubRegs */
2326 NullRegClasses,
2327 nullptr
2328 };
2329
2330 extern const TargetRegisterClass CoprocRegsRegClass = {
2331 &SparcMCRegisterClasses[CoprocRegsRegClassID],
2332 CoprocRegsSubClassMask,
2333 SuperRegIdxSeqs + 0,
2334 LaneBitmask(0x0000000000000001),
2335 0,
2336 false,
2337 0x00, /* TSFlags */
2338 false, /* HasDisjunctSubRegs */
2339 false, /* CoveredBySubRegs */
2340 NullRegClasses,
2341 nullptr
2342 };
2343
2344 extern const TargetRegisterClass FPRegsRegClass = {
2345 &SparcMCRegisterClasses[FPRegsRegClassID],
2346 FPRegsSubClassMask,
2347 SuperRegIdxSeqs + 6,
2348 LaneBitmask(0x0000000000000001),
2349 0,
2350 false,
2351 0x00, /* TSFlags */
2352 false, /* HasDisjunctSubRegs */
2353 false, /* CoveredBySubRegs */
2354 NullRegClasses,
2355 nullptr
2356 };
2357
2358 extern const TargetRegisterClass IntRegsRegClass = {
2359 &SparcMCRegisterClasses[IntRegsRegClassID],
2360 IntRegsSubClassMask,
2361 SuperRegIdxSeqs + 0,
2362 LaneBitmask(0x0000000000000001),
2363 0,
2364 false,
2365 0x00, /* TSFlags */
2366 false, /* HasDisjunctSubRegs */
2367 false, /* CoveredBySubRegs */
2368 NullRegClasses,
2369 nullptr
2370 };
2371
2372 extern const TargetRegisterClass GPRIncomingArgRegClass = {
2373 &SparcMCRegisterClasses[GPRIncomingArgRegClassID],
2374 GPRIncomingArgSubClassMask,
2375 SuperRegIdxSeqs + 0,
2376 LaneBitmask(0x0000000000000001),
2377 0,
2378 false,
2379 0x00, /* TSFlags */
2380 false, /* HasDisjunctSubRegs */
2381 false, /* CoveredBySubRegs */
2382 GPRIncomingArgSuperclasses,
2383 nullptr
2384 };
2385
2386 extern const TargetRegisterClass GPROutgoingArgRegClass = {
2387 &SparcMCRegisterClasses[GPROutgoingArgRegClassID],
2388 GPROutgoingArgSubClassMask,
2389 SuperRegIdxSeqs + 0,
2390 LaneBitmask(0x0000000000000001),
2391 0,
2392 false,
2393 0x00, /* TSFlags */
2394 false, /* HasDisjunctSubRegs */
2395 false, /* CoveredBySubRegs */
2396 GPROutgoingArgSuperclasses,
2397 nullptr
2398 };
2399
2400 extern const TargetRegisterClass DFPRegsRegClass = {
2401 &SparcMCRegisterClasses[DFPRegsRegClassID],
2402 DFPRegsSubClassMask,
2403 SuperRegIdxSeqs + 3,
2404 LaneBitmask(0x0000000000000003),
2405 0,
2406 false,
2407 0x00, /* TSFlags */
2408 true, /* HasDisjunctSubRegs */
2409 false, /* CoveredBySubRegs */
2410 NullRegClasses,
2411 nullptr
2412 };
2413
2414 extern const TargetRegisterClass I64RegsRegClass = {
2415 &SparcMCRegisterClasses[I64RegsRegClassID],
2416 I64RegsSubClassMask,
2417 SuperRegIdxSeqs + 0,
2418 LaneBitmask(0x0000000000000001),
2419 0,
2420 false,
2421 0x00, /* TSFlags */
2422 false, /* HasDisjunctSubRegs */
2423 false, /* CoveredBySubRegs */
2424 I64RegsSuperclasses,
2425 nullptr
2426 };
2427
2428 extern const TargetRegisterClass PRRegsRegClass = {
2429 &SparcMCRegisterClasses[PRRegsRegClassID],
2430 PRRegsSubClassMask,
2431 SuperRegIdxSeqs + 2,
2432 LaneBitmask(0x0000000000000001),
2433 0,
2434 false,
2435 0x00, /* TSFlags */
2436 false, /* HasDisjunctSubRegs */
2437 false, /* CoveredBySubRegs */
2438 NullRegClasses,
2439 nullptr
2440 };
2441
2442 extern const TargetRegisterClass CoprocPairRegClass = {
2443 &SparcMCRegisterClasses[CoprocPairRegClassID],
2444 CoprocPairSubClassMask,
2445 SuperRegIdxSeqs + 2,
2446 LaneBitmask(0x0000000000000003),
2447 0,
2448 false,
2449 0x00, /* TSFlags */
2450 true, /* HasDisjunctSubRegs */
2451 true, /* CoveredBySubRegs */
2452 NullRegClasses,
2453 nullptr
2454 };
2455
2456 extern const TargetRegisterClass IntPairRegClass = {
2457 &SparcMCRegisterClasses[IntPairRegClassID],
2458 IntPairSubClassMask,
2459 SuperRegIdxSeqs + 2,
2460 LaneBitmask(0x0000000000000003),
2461 0,
2462 false,
2463 0x00, /* TSFlags */
2464 true, /* HasDisjunctSubRegs */
2465 true, /* CoveredBySubRegs */
2466 NullRegClasses,
2467 nullptr
2468 };
2469
2470 extern const TargetRegisterClass LowDFPRegsRegClass = {
2471 &SparcMCRegisterClasses[LowDFPRegsRegClassID],
2472 LowDFPRegsSubClassMask,
2473 SuperRegIdxSeqs + 3,
2474 LaneBitmask(0x0000000000000003),
2475 0,
2476 false,
2477 0x00, /* TSFlags */
2478 true, /* HasDisjunctSubRegs */
2479 true, /* CoveredBySubRegs */
2480 LowDFPRegsSuperclasses,
2481 nullptr
2482 };
2483
2484 extern const TargetRegisterClass I64Regs_and_GPRIncomingArgRegClass = {
2485 &SparcMCRegisterClasses[I64Regs_and_GPRIncomingArgRegClassID],
2486 I64Regs_and_GPRIncomingArgSubClassMask,
2487 SuperRegIdxSeqs + 0,
2488 LaneBitmask(0x0000000000000001),
2489 0,
2490 false,
2491 0x00, /* TSFlags */
2492 false, /* HasDisjunctSubRegs */
2493 false, /* CoveredBySubRegs */
2494 I64Regs_and_GPRIncomingArgSuperclasses,
2495 nullptr
2496 };
2497
2498 extern const TargetRegisterClass I64Regs_and_GPROutgoingArgRegClass = {
2499 &SparcMCRegisterClasses[I64Regs_and_GPROutgoingArgRegClassID],
2500 I64Regs_and_GPROutgoingArgSubClassMask,
2501 SuperRegIdxSeqs + 0,
2502 LaneBitmask(0x0000000000000001),
2503 0,
2504 false,
2505 0x00, /* TSFlags */
2506 false, /* HasDisjunctSubRegs */
2507 false, /* CoveredBySubRegs */
2508 I64Regs_and_GPROutgoingArgSuperclasses,
2509 nullptr
2510 };
2511
2512 extern const TargetRegisterClass IntPair_with_sub_even_in_GPRIncomingArgRegClass = {
2513 &SparcMCRegisterClasses[IntPair_with_sub_even_in_GPRIncomingArgRegClassID],
2514 IntPair_with_sub_even_in_GPRIncomingArgSubClassMask,
2515 SuperRegIdxSeqs + 2,
2516 LaneBitmask(0x0000000000000003),
2517 0,
2518 false,
2519 0x00, /* TSFlags */
2520 true, /* HasDisjunctSubRegs */
2521 true, /* CoveredBySubRegs */
2522 IntPair_with_sub_even_in_GPRIncomingArgSuperclasses,
2523 nullptr
2524 };
2525
2526 extern const TargetRegisterClass IntPair_with_sub_even_in_GPROutgoingArgRegClass = {
2527 &SparcMCRegisterClasses[IntPair_with_sub_even_in_GPROutgoingArgRegClassID],
2528 IntPair_with_sub_even_in_GPROutgoingArgSubClassMask,
2529 SuperRegIdxSeqs + 2,
2530 LaneBitmask(0x0000000000000003),
2531 0,
2532 false,
2533 0x00, /* TSFlags */
2534 true, /* HasDisjunctSubRegs */
2535 true, /* CoveredBySubRegs */
2536 IntPair_with_sub_even_in_GPROutgoingArgSuperclasses,
2537 nullptr
2538 };
2539
2540 extern const TargetRegisterClass PRRegs_and_ASRRegsRegClass = {
2541 &SparcMCRegisterClasses[PRRegs_and_ASRRegsRegClassID],
2542 PRRegs_and_ASRRegsSubClassMask,
2543 SuperRegIdxSeqs + 2,
2544 LaneBitmask(0x0000000000000001),
2545 0,
2546 false,
2547 0x00, /* TSFlags */
2548 false, /* HasDisjunctSubRegs */
2549 false, /* CoveredBySubRegs */
2550 PRRegs_and_ASRRegsSuperclasses,
2551 nullptr
2552 };
2553
2554 extern const TargetRegisterClass QFPRegsRegClass = {
2555 &SparcMCRegisterClasses[QFPRegsRegClassID],
2556 QFPRegsSubClassMask,
2557 SuperRegIdxSeqs + 2,
2558 LaneBitmask(0x000000000000000F),
2559 0,
2560 false,
2561 0x00, /* TSFlags */
2562 true, /* HasDisjunctSubRegs */
2563 true, /* CoveredBySubRegs */
2564 NullRegClasses,
2565 nullptr
2566 };
2567
2568 extern const TargetRegisterClass LowQFPRegsRegClass = {
2569 &SparcMCRegisterClasses[LowQFPRegsRegClassID],
2570 LowQFPRegsSubClassMask,
2571 SuperRegIdxSeqs + 2,
2572 LaneBitmask(0x000000000000000F),
2573 0,
2574 false,
2575 0x00, /* TSFlags */
2576 true, /* HasDisjunctSubRegs */
2577 true, /* CoveredBySubRegs */
2578 LowQFPRegsSuperclasses,
2579 nullptr
2580 };
2581
2582} // end namespace SP
2583
2584namespace {
2585 const TargetRegisterClass *const RegisterClasses[] = {
2586 &SP::FCCRegsRegClass,
2587 &SP::ASRRegsRegClass,
2588 &SP::CoprocRegsRegClass,
2589 &SP::FPRegsRegClass,
2590 &SP::IntRegsRegClass,
2591 &SP::GPRIncomingArgRegClass,
2592 &SP::GPROutgoingArgRegClass,
2593 &SP::DFPRegsRegClass,
2594 &SP::I64RegsRegClass,
2595 &SP::PRRegsRegClass,
2596 &SP::CoprocPairRegClass,
2597 &SP::IntPairRegClass,
2598 &SP::LowDFPRegsRegClass,
2599 &SP::I64Regs_and_GPRIncomingArgRegClass,
2600 &SP::I64Regs_and_GPROutgoingArgRegClass,
2601 &SP::IntPair_with_sub_even_in_GPRIncomingArgRegClass,
2602 &SP::IntPair_with_sub_even_in_GPROutgoingArgRegClass,
2603 &SP::PRRegs_and_ASRRegsRegClass,
2604 &SP::QFPRegsRegClass,
2605 &SP::LowQFPRegsRegClass,
2606 };
2607} // end anonymous namespace
2608
2609static const uint8_t CostPerUseTable[] = {
26100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
2611
2612
2613static const bool InAllocatableClassTable[] = {
2614false, true, true, true, false, false, true, false, false, true, false, true, true, false, true, true, false, true, true, true, true, true, true, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
2615
2616
2617static const TargetRegisterInfoDesc SparcRegInfoDesc = { // Extra Descriptors
2618CostPerUseTable, 1, InAllocatableClassTable};
2619
2620unsigned SparcGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
2621 static const uint8_t RowMap[6] = {
2622 0, 0, 0, 1, 0, 0,
2623 };
2624 static const uint8_t Rows[2][6] = {
2625 { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
2626 { SP::sub_odd64_then_sub_even, 0, SP::sub_odd64_then_sub_odd, 0, 0, 0, },
2627 };
2628
2629 --IdxA; assert(IdxA < 6); (void) IdxA;
2630 --IdxB; assert(IdxB < 6);
2631 return Rows[RowMap[IdxA]][IdxB];
2632}
2633
2634 struct MaskRolOp {
2635 LaneBitmask Mask;
2636 uint8_t RotateLeft;
2637 };
2638 static const MaskRolOp LaneMaskComposeSequences[] = {
2639 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
2640 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
2641 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
2642 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 } // Sequence 6
2643 };
2644 static const uint8_t CompositeSequences[] = {
2645 0, // to sub_even
2646 0, // to sub_even64
2647 2, // to sub_odd
2648 4, // to sub_odd64
2649 4, // to sub_odd64_then_sub_even
2650 6 // to sub_odd64_then_sub_odd
2651 };
2652
2653LaneBitmask SparcGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2654 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
2655 LaneBitmask Result;
2656 for (const MaskRolOp *Ops =
2657 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
2658 Ops->Mask.any(); ++Ops) {
2659 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
2660 if (unsigned S = Ops->RotateLeft)
2661 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
2662 else
2663 Result |= LaneBitmask(M);
2664 }
2665 return Result;
2666}
2667
2668LaneBitmask SparcGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
2669 LaneMask &= getSubRegIndexLaneMask(IdxA);
2670 --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
2671 LaneBitmask Result;
2672 for (const MaskRolOp *Ops =
2673 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
2674 Ops->Mask.any(); ++Ops) {
2675 LaneBitmask::Type M = LaneMask.getAsInteger();
2676 if (unsigned S = Ops->RotateLeft)
2677 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
2678 else
2679 Result |= LaneBitmask(M);
2680 }
2681 return Result;
2682}
2683
2684const TargetRegisterClass *SparcGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
2685 static const uint8_t Table[20][6] = {
2686 { // FCCRegs
2687 0, // sub_even
2688 0, // sub_even64
2689 0, // sub_odd
2690 0, // sub_odd64
2691 0, // sub_odd64_then_sub_even
2692 0, // sub_odd64_then_sub_odd
2693 },
2694 { // ASRRegs
2695 0, // sub_even
2696 0, // sub_even64
2697 0, // sub_odd
2698 0, // sub_odd64
2699 0, // sub_odd64_then_sub_even
2700 0, // sub_odd64_then_sub_odd
2701 },
2702 { // CoprocRegs
2703 0, // sub_even
2704 0, // sub_even64
2705 0, // sub_odd
2706 0, // sub_odd64
2707 0, // sub_odd64_then_sub_even
2708 0, // sub_odd64_then_sub_odd
2709 },
2710 { // FPRegs
2711 0, // sub_even
2712 0, // sub_even64
2713 0, // sub_odd
2714 0, // sub_odd64
2715 0, // sub_odd64_then_sub_even
2716 0, // sub_odd64_then_sub_odd
2717 },
2718 { // IntRegs
2719 0, // sub_even
2720 0, // sub_even64
2721 0, // sub_odd
2722 0, // sub_odd64
2723 0, // sub_odd64_then_sub_even
2724 0, // sub_odd64_then_sub_odd
2725 },
2726 { // GPRIncomingArg
2727 0, // sub_even
2728 0, // sub_even64
2729 0, // sub_odd
2730 0, // sub_odd64
2731 0, // sub_odd64_then_sub_even
2732 0, // sub_odd64_then_sub_odd
2733 },
2734 { // GPROutgoingArg
2735 0, // sub_even
2736 0, // sub_even64
2737 0, // sub_odd
2738 0, // sub_odd64
2739 0, // sub_odd64_then_sub_even
2740 0, // sub_odd64_then_sub_odd
2741 },
2742 { // DFPRegs
2743 13, // sub_even -> LowDFPRegs
2744 0, // sub_even64
2745 13, // sub_odd -> LowDFPRegs
2746 0, // sub_odd64
2747 0, // sub_odd64_then_sub_even
2748 0, // sub_odd64_then_sub_odd
2749 },
2750 { // I64Regs
2751 0, // sub_even
2752 0, // sub_even64
2753 0, // sub_odd
2754 0, // sub_odd64
2755 0, // sub_odd64_then_sub_even
2756 0, // sub_odd64_then_sub_odd
2757 },
2758 { // PRRegs
2759 0, // sub_even
2760 0, // sub_even64
2761 0, // sub_odd
2762 0, // sub_odd64
2763 0, // sub_odd64_then_sub_even
2764 0, // sub_odd64_then_sub_odd
2765 },
2766 { // CoprocPair
2767 11, // sub_even -> CoprocPair
2768 0, // sub_even64
2769 11, // sub_odd -> CoprocPair
2770 0, // sub_odd64
2771 0, // sub_odd64_then_sub_even
2772 0, // sub_odd64_then_sub_odd
2773 },
2774 { // IntPair
2775 12, // sub_even -> IntPair
2776 0, // sub_even64
2777 12, // sub_odd -> IntPair
2778 0, // sub_odd64
2779 0, // sub_odd64_then_sub_even
2780 0, // sub_odd64_then_sub_odd
2781 },
2782 { // LowDFPRegs
2783 13, // sub_even -> LowDFPRegs
2784 0, // sub_even64
2785 13, // sub_odd -> LowDFPRegs
2786 0, // sub_odd64
2787 0, // sub_odd64_then_sub_even
2788 0, // sub_odd64_then_sub_odd
2789 },
2790 { // I64Regs_and_GPRIncomingArg
2791 0, // sub_even
2792 0, // sub_even64
2793 0, // sub_odd
2794 0, // sub_odd64
2795 0, // sub_odd64_then_sub_even
2796 0, // sub_odd64_then_sub_odd
2797 },
2798 { // I64Regs_and_GPROutgoingArg
2799 0, // sub_even
2800 0, // sub_even64
2801 0, // sub_odd
2802 0, // sub_odd64
2803 0, // sub_odd64_then_sub_even
2804 0, // sub_odd64_then_sub_odd
2805 },
2806 { // IntPair_with_sub_even_in_GPRIncomingArg
2807 16, // sub_even -> IntPair_with_sub_even_in_GPRIncomingArg
2808 0, // sub_even64
2809 16, // sub_odd -> IntPair_with_sub_even_in_GPRIncomingArg
2810 0, // sub_odd64
2811 0, // sub_odd64_then_sub_even
2812 0, // sub_odd64_then_sub_odd
2813 },
2814 { // IntPair_with_sub_even_in_GPROutgoingArg
2815 17, // sub_even -> IntPair_with_sub_even_in_GPROutgoingArg
2816 0, // sub_even64
2817 17, // sub_odd -> IntPair_with_sub_even_in_GPROutgoingArg
2818 0, // sub_odd64
2819 0, // sub_odd64_then_sub_even
2820 0, // sub_odd64_then_sub_odd
2821 },
2822 { // PRRegs_and_ASRRegs
2823 0, // sub_even
2824 0, // sub_even64
2825 0, // sub_odd
2826 0, // sub_odd64
2827 0, // sub_odd64_then_sub_even
2828 0, // sub_odd64_then_sub_odd
2829 },
2830 { // QFPRegs
2831 20, // sub_even -> LowQFPRegs
2832 19, // sub_even64 -> QFPRegs
2833 20, // sub_odd -> LowQFPRegs
2834 19, // sub_odd64 -> QFPRegs
2835 20, // sub_odd64_then_sub_even -> LowQFPRegs
2836 20, // sub_odd64_then_sub_odd -> LowQFPRegs
2837 },
2838 { // LowQFPRegs
2839 20, // sub_even -> LowQFPRegs
2840 20, // sub_even64 -> LowQFPRegs
2841 20, // sub_odd -> LowQFPRegs
2842 20, // sub_odd64 -> LowQFPRegs
2843 20, // sub_odd64_then_sub_even -> LowQFPRegs
2844 20, // sub_odd64_then_sub_odd -> LowQFPRegs
2845 },
2846 };
2847 assert(RC && "Missing regclass");
2848 if (!Idx) return RC;
2849 --Idx;
2850 assert(Idx < 6 && "Bad subreg");
2851 unsigned TV = Table[RC->getID()][Idx];
2852 return TV ? getRegClass(TV - 1) : nullptr;
2853}
2854
2855const TargetRegisterClass *SparcGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
2856 static const uint8_t Table[20][6] = {
2857 { // FCCRegs
2858 0, // FCCRegs:sub_even
2859 0, // FCCRegs:sub_even64
2860 0, // FCCRegs:sub_odd
2861 0, // FCCRegs:sub_odd64
2862 0, // FCCRegs:sub_odd64_then_sub_even
2863 0, // FCCRegs:sub_odd64_then_sub_odd
2864 },
2865 { // ASRRegs
2866 0, // ASRRegs:sub_even
2867 0, // ASRRegs:sub_even64
2868 0, // ASRRegs:sub_odd
2869 0, // ASRRegs:sub_odd64
2870 0, // ASRRegs:sub_odd64_then_sub_even
2871 0, // ASRRegs:sub_odd64_then_sub_odd
2872 },
2873 { // CoprocRegs
2874 0, // CoprocRegs:sub_even
2875 0, // CoprocRegs:sub_even64
2876 0, // CoprocRegs:sub_odd
2877 0, // CoprocRegs:sub_odd64
2878 0, // CoprocRegs:sub_odd64_then_sub_even
2879 0, // CoprocRegs:sub_odd64_then_sub_odd
2880 },
2881 { // FPRegs
2882 0, // FPRegs:sub_even
2883 0, // FPRegs:sub_even64
2884 0, // FPRegs:sub_odd
2885 0, // FPRegs:sub_odd64
2886 0, // FPRegs:sub_odd64_then_sub_even
2887 0, // FPRegs:sub_odd64_then_sub_odd
2888 },
2889 { // IntRegs
2890 0, // IntRegs:sub_even
2891 0, // IntRegs:sub_even64
2892 0, // IntRegs:sub_odd
2893 0, // IntRegs:sub_odd64
2894 0, // IntRegs:sub_odd64_then_sub_even
2895 0, // IntRegs:sub_odd64_then_sub_odd
2896 },
2897 { // GPRIncomingArg
2898 0, // GPRIncomingArg:sub_even
2899 0, // GPRIncomingArg:sub_even64
2900 0, // GPRIncomingArg:sub_odd
2901 0, // GPRIncomingArg:sub_odd64
2902 0, // GPRIncomingArg:sub_odd64_then_sub_even
2903 0, // GPRIncomingArg:sub_odd64_then_sub_odd
2904 },
2905 { // GPROutgoingArg
2906 0, // GPROutgoingArg:sub_even
2907 0, // GPROutgoingArg:sub_even64
2908 0, // GPROutgoingArg:sub_odd
2909 0, // GPROutgoingArg:sub_odd64
2910 0, // GPROutgoingArg:sub_odd64_then_sub_even
2911 0, // GPROutgoingArg:sub_odd64_then_sub_odd
2912 },
2913 { // DFPRegs
2914 4, // DFPRegs:sub_even -> FPRegs
2915 0, // DFPRegs:sub_even64
2916 4, // DFPRegs:sub_odd -> FPRegs
2917 0, // DFPRegs:sub_odd64
2918 0, // DFPRegs:sub_odd64_then_sub_even
2919 0, // DFPRegs:sub_odd64_then_sub_odd
2920 },
2921 { // I64Regs
2922 0, // I64Regs:sub_even
2923 0, // I64Regs:sub_even64
2924 0, // I64Regs:sub_odd
2925 0, // I64Regs:sub_odd64
2926 0, // I64Regs:sub_odd64_then_sub_even
2927 0, // I64Regs:sub_odd64_then_sub_odd
2928 },
2929 { // PRRegs
2930 0, // PRRegs:sub_even
2931 0, // PRRegs:sub_even64
2932 0, // PRRegs:sub_odd
2933 0, // PRRegs:sub_odd64
2934 0, // PRRegs:sub_odd64_then_sub_even
2935 0, // PRRegs:sub_odd64_then_sub_odd
2936 },
2937 { // CoprocPair
2938 3, // CoprocPair:sub_even -> CoprocRegs
2939 0, // CoprocPair:sub_even64
2940 3, // CoprocPair:sub_odd -> CoprocRegs
2941 0, // CoprocPair:sub_odd64
2942 0, // CoprocPair:sub_odd64_then_sub_even
2943 0, // CoprocPair:sub_odd64_then_sub_odd
2944 },
2945 { // IntPair
2946 9, // IntPair:sub_even -> I64Regs
2947 0, // IntPair:sub_even64
2948 9, // IntPair:sub_odd -> I64Regs
2949 0, // IntPair:sub_odd64
2950 0, // IntPair:sub_odd64_then_sub_even
2951 0, // IntPair:sub_odd64_then_sub_odd
2952 },
2953 { // LowDFPRegs
2954 4, // LowDFPRegs:sub_even -> FPRegs
2955 0, // LowDFPRegs:sub_even64
2956 4, // LowDFPRegs:sub_odd -> FPRegs
2957 0, // LowDFPRegs:sub_odd64
2958 0, // LowDFPRegs:sub_odd64_then_sub_even
2959 0, // LowDFPRegs:sub_odd64_then_sub_odd
2960 },
2961 { // I64Regs_and_GPRIncomingArg
2962 0, // I64Regs_and_GPRIncomingArg:sub_even
2963 0, // I64Regs_and_GPRIncomingArg:sub_even64
2964 0, // I64Regs_and_GPRIncomingArg:sub_odd
2965 0, // I64Regs_and_GPRIncomingArg:sub_odd64
2966 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_even
2967 0, // I64Regs_and_GPRIncomingArg:sub_odd64_then_sub_odd
2968 },
2969 { // I64Regs_and_GPROutgoingArg
2970 0, // I64Regs_and_GPROutgoingArg:sub_even
2971 0, // I64Regs_and_GPROutgoingArg:sub_even64
2972 0, // I64Regs_and_GPROutgoingArg:sub_odd
2973 0, // I64Regs_and_GPROutgoingArg:sub_odd64
2974 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_even
2975 0, // I64Regs_and_GPROutgoingArg:sub_odd64_then_sub_odd
2976 },
2977 { // IntPair_with_sub_even_in_GPRIncomingArg
2978 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even -> I64Regs_and_GPRIncomingArg
2979 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_even64
2980 14, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd -> I64Regs_and_GPRIncomingArg
2981 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64
2982 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_even
2983 0, // IntPair_with_sub_even_in_GPRIncomingArg:sub_odd64_then_sub_odd
2984 },
2985 { // IntPair_with_sub_even_in_GPROutgoingArg
2986 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even -> I64Regs_and_GPROutgoingArg
2987 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_even64
2988 15, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd -> I64Regs_and_GPROutgoingArg
2989 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64
2990 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_even
2991 0, // IntPair_with_sub_even_in_GPROutgoingArg:sub_odd64_then_sub_odd
2992 },
2993 { // PRRegs_and_ASRRegs
2994 0, // PRRegs_and_ASRRegs:sub_even
2995 0, // PRRegs_and_ASRRegs:sub_even64
2996 0, // PRRegs_and_ASRRegs:sub_odd
2997 0, // PRRegs_and_ASRRegs:sub_odd64
2998 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_even
2999 0, // PRRegs_and_ASRRegs:sub_odd64_then_sub_odd
3000 },
3001 { // QFPRegs
3002 4, // QFPRegs:sub_even -> FPRegs
3003 8, // QFPRegs:sub_even64 -> DFPRegs
3004 4, // QFPRegs:sub_odd -> FPRegs
3005 8, // QFPRegs:sub_odd64 -> DFPRegs
3006 4, // QFPRegs:sub_odd64_then_sub_even -> FPRegs
3007 4, // QFPRegs:sub_odd64_then_sub_odd -> FPRegs
3008 },
3009 { // LowQFPRegs
3010 4, // LowQFPRegs:sub_even -> FPRegs
3011 13, // LowQFPRegs:sub_even64 -> LowDFPRegs
3012 4, // LowQFPRegs:sub_odd -> FPRegs
3013 13, // LowQFPRegs:sub_odd64 -> LowDFPRegs
3014 4, // LowQFPRegs:sub_odd64_then_sub_even -> FPRegs
3015 4, // LowQFPRegs:sub_odd64_then_sub_odd -> FPRegs
3016 },
3017 };
3018 assert(RC && "Missing regclass");
3019 if (!Idx) return RC;
3020 --Idx;
3021 assert(Idx < 6 && "Bad subreg");
3022 unsigned TV = Table[RC->getID()][Idx];
3023 return TV ? getRegClass(TV - 1) : nullptr;
3024}
3025
3026/// Get the weight in units of pressure for this register class.
3027const RegClassWeight &SparcGenRegisterInfo::
3028getRegClassWeight(const TargetRegisterClass *RC) const {
3029 static const RegClassWeight RCWeightTable[] = {
3030 {1, 4}, // FCCRegs
3031 {1, 1}, // ASRRegs
3032 {0, 0}, // CoprocRegs
3033 {1, 32}, // FPRegs
3034 {1, 32}, // IntRegs
3035 {1, 6}, // GPRIncomingArg
3036 {1, 6}, // GPROutgoingArg
3037 {2, 64}, // DFPRegs
3038 {1, 32}, // I64Regs
3039 {1, 17}, // PRRegs
3040 {0, 0}, // CoprocPair
3041 {2, 32}, // IntPair
3042 {2, 32}, // LowDFPRegs
3043 {1, 6}, // I64Regs_and_GPRIncomingArg
3044 {1, 6}, // I64Regs_and_GPROutgoingArg
3045 {2, 6}, // IntPair_with_sub_even_in_GPRIncomingArg
3046 {2, 6}, // IntPair_with_sub_even_in_GPROutgoingArg
3047 {1, 1}, // PRRegs_and_ASRRegs
3048 {4, 64}, // QFPRegs
3049 {4, 32}, // LowQFPRegs
3050 };
3051 return RCWeightTable[RC->getID()];
3052}
3053
3054/// Get the weight in units of pressure for this register unit.
3055unsigned SparcGenRegisterInfo::
3056getRegUnitWeight(unsigned RegUnit) const {
3057 assert(RegUnit < 173 && "invalid register unit");
3058 static const uint8_t RUWeightTable[] = {
3059 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
3060 return RUWeightTable[RegUnit];
3061}
3062
3063
3064// Get the number of dimensions of register pressure.
3065unsigned SparcGenRegisterInfo::getNumRegPressureSets() const {
3066 return 8;
3067}
3068
3069// Get the name of this register unit pressure set.
3070const char *SparcGenRegisterInfo::
3071getRegPressureSetName(unsigned Idx) const {
3072 static const char *PressureNameTable[] = {
3073 "PRRegs_and_ASRRegs",
3074 "FCCRegs",
3075 "GPRIncomingArg",
3076 "GPROutgoingArg",
3077 "PRRegs",
3078 "FPRegs",
3079 "IntRegs",
3080 "DFPRegs",
3081 };
3082 return PressureNameTable[Idx];
3083}
3084
3085// Get the register unit pressure limit for this dimension.
3086// This limit must be adjusted dynamically for reserved registers.
3087unsigned SparcGenRegisterInfo::
3088getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
3089 static const uint8_t PressureLimitTable[] = {
3090 1, // 0: PRRegs_and_ASRRegs
3091 4, // 1: FCCRegs
3092 6, // 2: GPRIncomingArg
3093 6, // 3: GPROutgoingArg
3094 17, // 4: PRRegs
3095 32, // 5: FPRegs
3096 32, // 6: IntRegs
3097 64, // 7: DFPRegs
3098 };
3099 return PressureLimitTable[Idx];
3100}
3101
3102/// Table of pressure sets per register class or unit.
3103static const int RCSetsTable[] = {
3104 /* 0 */ 1, -1,
3105 /* 2 */ 0, 4, -1,
3106 /* 5 */ 2, 6, -1,
3107 /* 8 */ 3, 6, -1,
3108 /* 11 */ 5, 7, -1,
3109};
3110
3111/// Get the dimensions of register pressure impacted by this register class.
3112/// Returns a -1 terminated array of pressure set IDs
3113const int *SparcGenRegisterInfo::
3114getRegClassPressureSets(const TargetRegisterClass *RC) const {
3115 static const uint8_t RCSetStartTable[] = {
3116 0,1,1,11,6,5,8,12,6,3,1,6,11,5,8,5,8,2,12,11,};
3117 return &RCSetsTable[RCSetStartTable[RC->getID()]];
3118}
3119
3120/// Get the dimensions of register pressure impacted by this register unit.
3121/// Returns a -1 terminated array of pressure set IDs
3122const int *SparcGenRegisterInfo::
3123getRegUnitPressureSets(unsigned RegUnit) const {
3124 assert(RegUnit < 173 && "invalid register unit");
3125 static const uint8_t RUSetStartTable[] = {
3126 3,3,3,1,1,3,1,1,3,1,3,3,1,3,3,1,2,3,3,3,3,3,3,1,3,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,0,0,0,0,6,6,6,6,6,6,6,6,5,5,5,5,5,5,6,6,6,6,6,6,6,6,6,6,8,8,8,8,8,8,6,6,};
3127 return &RCSetsTable[RUSetStartTable[RegUnit]];
3128}
3129
3130extern const MCRegisterDesc SparcRegDesc[];
3131extern const int16_t SparcRegDiffLists[];
3132extern const LaneBitmask SparcLaneMaskLists[];
3133extern const char SparcRegStrings[];
3134extern const char SparcRegClassStrings[];
3135extern const MCPhysReg SparcRegUnitRoots[][2];
3136extern const uint16_t SparcSubRegIdxLists[];
3137extern const uint16_t SparcRegEncodingTable[];
3138// SP Dwarf<->LLVM register mappings.
3139extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[];
3140extern const unsigned SPDwarfFlavour0Dwarf2LSize;
3141
3142extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[];
3143extern const unsigned SPEHFlavour0Dwarf2LSize;
3144
3145extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[];
3146extern const unsigned SPDwarfFlavour0L2DwarfSize;
3147
3148extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[];
3149extern const unsigned SPEHFlavour0L2DwarfSize;
3150
3151SparcGenRegisterInfo::
3152SparcGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
3153 unsigned PC, unsigned HwMode)
3154 : TargetRegisterInfo(&SparcRegInfoDesc, RegisterClasses, RegisterClasses+20,
3155 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
3156 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
3157 InitMCRegisterInfo(SparcRegDesc, 238, RA, PC,
3158 SparcMCRegisterClasses, 20,
3159 SparcRegUnitRoots,
3160 173,
3161 SparcRegDiffLists,
3162 SparcLaneMaskLists,
3163 SparcRegStrings,
3164 SparcRegClassStrings,
3165 SparcSubRegIdxLists,
3166 7,
3167 SparcRegEncodingTable);
3168
3169 switch (DwarfFlavour) {
3170 default:
3171 llvm_unreachable("Unknown DWARF flavour");
3172 case 0:
3173 mapDwarfRegsToLLVMRegs(SPDwarfFlavour0Dwarf2L, SPDwarfFlavour0Dwarf2LSize, false);
3174 break;
3175 }
3176 switch (EHFlavour) {
3177 default:
3178 llvm_unreachable("Unknown DWARF flavour");
3179 case 0:
3180 mapDwarfRegsToLLVMRegs(SPEHFlavour0Dwarf2L, SPEHFlavour0Dwarf2LSize, true);
3181 break;
3182 }
3183 switch (DwarfFlavour) {
3184 default:
3185 llvm_unreachable("Unknown DWARF flavour");
3186 case 0:
3187 mapLLVMRegsToDwarfRegs(SPDwarfFlavour0L2Dwarf, SPDwarfFlavour0L2DwarfSize, false);
3188 break;
3189 }
3190 switch (EHFlavour) {
3191 default:
3192 llvm_unreachable("Unknown DWARF flavour");
3193 case 0:
3194 mapLLVMRegsToDwarfRegs(SPEHFlavour0L2Dwarf, SPEHFlavour0L2DwarfSize, true);
3195 break;
3196 }
3197}
3198
3199static const MCPhysReg CSR_SaveList[] = { 0 };
3200static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x103fffc0, 0x00000000, 0x000003fc, };
3201static const MCPhysReg RTCSR_SaveList[] = { 0 };
3202static const uint32_t RTCSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00003000, 0x00000000, 0x00000020, };
3203
3204
3205ArrayRef<const uint32_t *> SparcGenRegisterInfo::getRegMasks() const {
3206 static const uint32_t *const Masks[] = {
3207 CSR_RegMask,
3208 RTCSR_RegMask,
3209 };
3210 return ArrayRef(Masks);
3211}
3212
3213bool SparcGenRegisterInfo::
3214isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3215 return
3216 false;
3217}
3218
3219bool SparcGenRegisterInfo::
3220isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3221 return
3222 false;
3223}
3224
3225bool SparcGenRegisterInfo::
3226isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3227 return
3228 false;
3229}
3230
3231bool SparcGenRegisterInfo::
3232isConstantPhysReg(MCRegister PhysReg) const {
3233 return
3234 PhysReg == SP::G0 ||
3235 false;
3236}
3237
3238ArrayRef<const char *> SparcGenRegisterInfo::getRegMaskNames() const {
3239 static const char *Names[] = {
3240 "CSR",
3241 "RTCSR",
3242 };
3243 return ArrayRef(Names);
3244}
3245
3246const SparcFrameLowering *
3247SparcGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
3248 return static_cast<const SparcFrameLowering *>(
3249 MF.getSubtarget().getFrameLowering());
3250}
3251
3252} // end namespace llvm
3253
3254#endif // GET_REGINFO_TARGET_DESC
3255
3256