1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace Sparc {
15enum {
16 DetectRoundChange = 0,
17 FeatureHardQuad = 1,
18 FeatureLeon = 2,
19 FeatureNoFMULS = 3,
20 FeatureNoFSMULD = 4,
21 FeaturePWRPSR = 5,
22 FeatureReserveG1 = 6,
23 FeatureReserveG2 = 7,
24 FeatureReserveG3 = 8,
25 FeatureReserveG4 = 9,
26 FeatureReserveG5 = 10,
27 FeatureReserveG6 = 11,
28 FeatureReserveG7 = 12,
29 FeatureReserveI0 = 13,
30 FeatureReserveI1 = 14,
31 FeatureReserveI2 = 15,
32 FeatureReserveI3 = 16,
33 FeatureReserveI4 = 17,
34 FeatureReserveI5 = 18,
35 FeatureReserveL0 = 19,
36 FeatureReserveL1 = 20,
37 FeatureReserveL2 = 21,
38 FeatureReserveL3 = 22,
39 FeatureReserveL4 = 23,
40 FeatureReserveL5 = 24,
41 FeatureReserveL6 = 25,
42 FeatureReserveL7 = 26,
43 FeatureReserveO0 = 27,
44 FeatureReserveO1 = 28,
45 FeatureReserveO2 = 29,
46 FeatureReserveO3 = 30,
47 FeatureReserveO4 = 31,
48 FeatureReserveO5 = 32,
49 FeatureSoftFloat = 33,
50 FeatureSoftMulDiv = 34,
51 FeatureV8Deprecated = 35,
52 FeatureV9 = 36,
53 FeatureVIS = 37,
54 FeatureVIS2 = 38,
55 FeatureVIS3 = 39,
56 FixAllFDIVSQRT = 40,
57 InsertNOPLoad = 41,
58 LeonCASA = 42,
59 LeonCycleCounter = 43,
60 TuneSlowRDPC = 44,
61 UMACSMACSupport = 45,
62 UsePopc = 46,
63 NumSubtargetFeatures = 47
64};
65} // end namespace Sparc
66} // end namespace llvm
67
68#endif // GET_SUBTARGETINFO_ENUM
69
70
71#ifdef GET_SUBTARGETINFO_MACRO
72GET_SUBTARGETINFO_MACRO(DetectRoundChange, false, detectRoundChange)
73GET_SUBTARGETINFO_MACRO(FixAllFDIVSQRT, false, fixAllFDIVSQRT)
74GET_SUBTARGETINFO_MACRO(HasHardQuad, false, hasHardQuad)
75GET_SUBTARGETINFO_MACRO(HasLeonCasa, false, hasLeonCasa)
76GET_SUBTARGETINFO_MACRO(HasLeonCycleCounter, false, hasLeonCycleCounter)
77GET_SUBTARGETINFO_MACRO(HasNoFMULS, false, hasNoFMULS)
78GET_SUBTARGETINFO_MACRO(HasNoFSMULD, false, hasNoFSMULD)
79GET_SUBTARGETINFO_MACRO(HasPWRPSR, false, hasPWRPSR)
80GET_SUBTARGETINFO_MACRO(HasSlowRDPC, false, hasSlowRDPC)
81GET_SUBTARGETINFO_MACRO(HasUmacSmac, false, hasUmacSmac)
82GET_SUBTARGETINFO_MACRO(InsertNOPLoad, false, insertNOPLoad)
83GET_SUBTARGETINFO_MACRO(IsLeon, false, isLeon)
84GET_SUBTARGETINFO_MACRO(IsV9, false, isV9)
85GET_SUBTARGETINFO_MACRO(IsVIS, false, isVIS)
86GET_SUBTARGETINFO_MACRO(IsVIS2, false, isVIS2)
87GET_SUBTARGETINFO_MACRO(IsVIS3, false, isVIS3)
88GET_SUBTARGETINFO_MACRO(UsePopc, false, usePopc)
89GET_SUBTARGETINFO_MACRO(UseSoftFloat, false, useSoftFloat)
90GET_SUBTARGETINFO_MACRO(UseSoftMulDiv, false, useSoftMulDiv)
91GET_SUBTARGETINFO_MACRO(UseV8DeprecatedInsts, false, useV8DeprecatedInsts)
92#undef GET_SUBTARGETINFO_MACRO
93#endif // GET_SUBTARGETINFO_MACRO
94
95
96#ifdef GET_SUBTARGETINFO_MC_DESC
97#undef GET_SUBTARGETINFO_MC_DESC
98
99namespace llvm {
100// Sorted (by key) array of values for CPU features.
101extern const llvm::SubtargetFeatureKV SparcFeatureKV[] = {
102 { "deprecated-v8", "Enable deprecated V8 instructions in V9 mode", Sparc::FeatureV8Deprecated, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
103 { "detectroundchange", "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode", Sparc::DetectRoundChange, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
104 { "fixallfdivsqrt", "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store", Sparc::FixAllFDIVSQRT, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
105 { "hard-quad-float", "Enable quad-word floating point instructions", Sparc::FeatureHardQuad, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
106 { "hasleoncasa", "Enable CASA instruction for LEON3 and LEON4 processors", Sparc::LeonCASA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
107 { "hasumacsmac", "Enable UMAC and SMAC for LEON3 and LEON4 processors", Sparc::UMACSMACSupport, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
108 { "insertnopload", "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction", Sparc::InsertNOPLoad, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
109 { "leon", "Enable LEON extensions", Sparc::FeatureLeon, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
110 { "leoncyclecounter", "Use the Leon cycle counter register", Sparc::LeonCycleCounter, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
111 { "leonpwrpsr", "Enable the PWRPSR instruction", Sparc::FeaturePWRPSR, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
112 { "no-fmuls", "Disable the fmuls instruction.", Sparc::FeatureNoFMULS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
113 { "no-fsmuld", "Disable the fsmuld instruction.", Sparc::FeatureNoFSMULD, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
114 { "popc", "Use the popc (population count) instruction", Sparc::UsePopc, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
115 { "reserve-g1", "Reserve G1, making it unavailable as a GPR", Sparc::FeatureReserveG1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
116 { "reserve-g2", "Reserve G2, making it unavailable as a GPR", Sparc::FeatureReserveG2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
117 { "reserve-g3", "Reserve G3, making it unavailable as a GPR", Sparc::FeatureReserveG3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
118 { "reserve-g4", "Reserve G4, making it unavailable as a GPR", Sparc::FeatureReserveG4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
119 { "reserve-g5", "Reserve G5, making it unavailable as a GPR", Sparc::FeatureReserveG5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
120 { "reserve-g6", "Reserve G6, making it unavailable as a GPR", Sparc::FeatureReserveG6, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
121 { "reserve-g7", "Reserve G7, making it unavailable as a GPR", Sparc::FeatureReserveG7, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
122 { "reserve-i0", "Reserve I0, making it unavailable as a GPR", Sparc::FeatureReserveI0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
123 { "reserve-i1", "Reserve I1, making it unavailable as a GPR", Sparc::FeatureReserveI1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
124 { "reserve-i2", "Reserve I2, making it unavailable as a GPR", Sparc::FeatureReserveI2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
125 { "reserve-i3", "Reserve I3, making it unavailable as a GPR", Sparc::FeatureReserveI3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
126 { "reserve-i4", "Reserve I4, making it unavailable as a GPR", Sparc::FeatureReserveI4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
127 { "reserve-i5", "Reserve I5, making it unavailable as a GPR", Sparc::FeatureReserveI5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
128 { "reserve-l0", "Reserve L0, making it unavailable as a GPR", Sparc::FeatureReserveL0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
129 { "reserve-l1", "Reserve L1, making it unavailable as a GPR", Sparc::FeatureReserveL1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
130 { "reserve-l2", "Reserve L2, making it unavailable as a GPR", Sparc::FeatureReserveL2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
131 { "reserve-l3", "Reserve L3, making it unavailable as a GPR", Sparc::FeatureReserveL3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
132 { "reserve-l4", "Reserve L4, making it unavailable as a GPR", Sparc::FeatureReserveL4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
133 { "reserve-l5", "Reserve L5, making it unavailable as a GPR", Sparc::FeatureReserveL5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
134 { "reserve-l6", "Reserve L6, making it unavailable as a GPR", Sparc::FeatureReserveL6, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
135 { "reserve-l7", "Reserve L7, making it unavailable as a GPR", Sparc::FeatureReserveL7, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
136 { "reserve-o0", "Reserve O0, making it unavailable as a GPR", Sparc::FeatureReserveO0, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
137 { "reserve-o1", "Reserve O1, making it unavailable as a GPR", Sparc::FeatureReserveO1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
138 { "reserve-o2", "Reserve O2, making it unavailable as a GPR", Sparc::FeatureReserveO2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
139 { "reserve-o3", "Reserve O3, making it unavailable as a GPR", Sparc::FeatureReserveO3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
140 { "reserve-o4", "Reserve O4, making it unavailable as a GPR", Sparc::FeatureReserveO4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
141 { "reserve-o5", "Reserve O5, making it unavailable as a GPR", Sparc::FeatureReserveO5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
142 { "slow-rdpc", "rd %pc, %XX is slow", Sparc::TuneSlowRDPC, { { { 0x1000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
143 { "soft-float", "Use software emulation for floating point", Sparc::FeatureSoftFloat, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
144 { "soft-mul-div", "Use software emulation for integer multiply and divide", Sparc::FeatureSoftMulDiv, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
145 { "v9", "Enable SPARC-V9 instructions", Sparc::FeatureV9, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
146 { "vis", "Enable UltraSPARC Visual Instruction Set extensions", Sparc::FeatureVIS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
147 { "vis2", "Enable Visual Instruction Set extensions II", Sparc::FeatureVIS2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
148 { "vis3", "Enable Visual Instruction Set extensions III", Sparc::FeatureVIS3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
149};
150
151#ifdef DBGFIELD
152#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
153#endif
154#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
155#define DBGFIELD(x) x,
156#else
157#define DBGFIELD(x)
158#endif
159
160// Functional units for "LEON2Itineraries"
161namespace LEON2ItinerariesFU {
162 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
163 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
164} // end namespace LEON2ItinerariesFU
165
166// Functional units for "LEON3Itineraries"
167namespace LEON3ItinerariesFU {
168 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
169 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
170} // end namespace LEON3ItinerariesFU
171
172// Functional units for "LEON4Itineraries"
173namespace LEON4ItinerariesFU {
174 const InstrStage::FuncUnits LEONIU = 1ULL << 0;
175 const InstrStage::FuncUnits LEONFPU = 1ULL << 1;
176} // end namespace LEON4ItinerariesFU
177
178extern const llvm::InstrStage SparcStages[] = {
179 { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
180 { 1, LEON2ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
181 { 1, LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
182 { 1, LEON2ItinerariesFU::LEONIU | LEON2ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
183 { 1, LEON3ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 4
184 { 1, LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 5
185 { 1, LEON3ItinerariesFU::LEONIU | LEON3ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 6
186 { 1, LEON4ItinerariesFU::LEONIU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 7
187 { 1, LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 8
188 { 1, LEON4ItinerariesFU::LEONIU | LEON4ItinerariesFU::LEONFPU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 9
189 { 0, 0, 0, llvm::InstrStage::Required } // End stages
190};
191extern const unsigned SparcOperandCycles[] = {
192 0, // No itinerary
193 1, 1, // 1-2
194 7, 1, // 3-4
195 2, 1, // 5-6
196 2, 1, // 7-8
197 7, 1, // 9-10
198 36, 1, // 11-12
199 20, 1, // 13-14
200 21, 1, // 15-16
201 16, 1, // 17-18
202 2, 1, // 19-20
203 65, 1, // 21-22
204 37, 1, // 23-24
205 2, 1, // 25-26
206 2, 1, // 27-28
207 1, 1, // 29-30
208 35, 1, // 31-32
209 5, 1, // 33-34
210 2, 1, // 35-36
211 3, 1, // 37-38
212 5, 1, // 39-40
213 1, 1, // 41-42
214 7, 1, // 43-44
215 3, 1, // 45-46
216 2, 1, // 47-48
217 4, 1, // 49-50
218 17, 1, // 51-52
219 16, 1, // 53-54
220 4, 1, // 55-56
221 4, 1, // 57-58
222 2, 1, // 59-60
223 25, 1, // 61-62
224 24, 1, // 63-64
225 4, 1, // 65-66
226 2, 1, // 67-68
227 1, 1, // 69-70
228 35, 1, // 71-72
229 2, 1, // 73-74
230 1, 1, // 75-76
231 4, 1, // 77-78
232 5, 1, // 79-80
233 4, 1, // 81-82
234 1, 1, // 83-84
235 7, 1, // 85-86
236 3, 1, // 87-88
237 2, 1, // 89-90
238 4, 1, // 91-92
239 17, 1, // 93-94
240 16, 1, // 95-96
241 4, 1, // 97-98
242 4, 1, // 99-100
243 2, 1, // 101-102
244 25, 1, // 103-104
245 24, 1, // 105-106
246 4, 1, // 107-108
247 1, 1, // 109-110
248 1, 1, // 111-112
249 35, 1, // 113-114
250 2, 1, // 115-116
251 1, 1, // 117-118
252 1, 1, // 119-120
253 1, 1, // 121-122
254 4, 1, // 123-124
255 0 // End operand cycles
256};
257extern const unsigned SparcForwardingPaths[] = {
258 0, // No itinerary
259 0, 0, // 1-2
260 0, 0, // 3-4
261 0, 0, // 5-6
262 0, 0, // 7-8
263 0, 0, // 9-10
264 0, 0, // 11-12
265 0, 0, // 13-14
266 0, 0, // 15-16
267 0, 0, // 17-18
268 0, 0, // 19-20
269 0, 0, // 21-22
270 0, 0, // 23-24
271 0, 0, // 25-26
272 0, 0, // 27-28
273 0, 0, // 29-30
274 0, 0, // 31-32
275 0, 0, // 33-34
276 0, 0, // 35-36
277 0, 0, // 37-38
278 0, 0, // 39-40
279 0, 0, // 41-42
280 0, 0, // 43-44
281 0, 0, // 45-46
282 0, 0, // 47-48
283 0, 0, // 49-50
284 0, 0, // 51-52
285 0, 0, // 53-54
286 0, 0, // 55-56
287 0, 0, // 57-58
288 0, 0, // 59-60
289 0, 0, // 61-62
290 0, 0, // 63-64
291 0, 0, // 65-66
292 0, 0, // 67-68
293 0, 0, // 69-70
294 0, 0, // 71-72
295 0, 0, // 73-74
296 0, 0, // 75-76
297 0, 0, // 77-78
298 0, 0, // 79-80
299 0, 0, // 81-82
300 0, 0, // 83-84
301 0, 0, // 85-86
302 0, 0, // 87-88
303 0, 0, // 89-90
304 0, 0, // 91-92
305 0, 0, // 93-94
306 0, 0, // 95-96
307 0, 0, // 97-98
308 0, 0, // 99-100
309 0, 0, // 101-102
310 0, 0, // 103-104
311 0, 0, // 105-106
312 0, 0, // 107-108
313 0, 0, // 109-110
314 0, 0, // 111-112
315 0, 0, // 113-114
316 0, 0, // 115-116
317 0, 0, // 117-118
318 0, 0, // 119-120
319 0, 0, // 121-122
320 0, 0, // 123-124
321 0 // End bypass tables
322};
323
324static const llvm::InstrItinerary LEON2Itineraries[] = {
325 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
326 { 1, 1, 2, 1, 3 }, // 1 IIC_iu_instr
327 { 1, 2, 3, 3, 5 }, // 2 IIC_fpu_normal_instr
328 { 1, 3, 4, 5, 7 }, // 3 IIC_jmp_or_call
329 { 1, 2, 3, 7, 9 }, // 4 IIC_fpu_abs
330 { 1, 2, 3, 9, 11 }, // 5 IIC_fpu_fast_instr
331 { 1, 2, 3, 11, 13 }, // 6 IIC_fpu_divd
332 { 1, 2, 3, 13, 15 }, // 7 IIC_fpu_divs
333 { 1, 2, 3, 15, 17 }, // 8 IIC_fpu_muld
334 { 1, 2, 3, 17, 19 }, // 9 IIC_fpu_muls
335 { 1, 2, 3, 19, 21 }, // 10 IIC_fpu_negs
336 { 1, 2, 3, 21, 23 }, // 11 IIC_fpu_sqrtd
337 { 1, 2, 3, 23, 25 }, // 12 IIC_fpu_sqrts
338 { 1, 2, 3, 25, 27 }, // 13 IIC_fpu_stod
339 { 1, 3, 4, 27, 29 }, // 14 IIC_ldd
340 { 1, 3, 4, 29, 31 }, // 15 IIC_iu_or_fpu_instr
341 { 1, 1, 2, 31, 33 }, // 16 IIC_iu_div
342 { 0, 0, 0, 0, 0 }, // 17 IIC_smac_umac
343 { 1, 1, 2, 33, 35 }, // 18 IIC_iu_smul
344 { 1, 3, 4, 35, 37 }, // 19 IIC_st
345 { 1, 3, 4, 37, 39 }, // 20 IIC_std
346 { 1, 1, 2, 39, 41 }, // 21 IIC_iu_umul
347 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
348};
349
350static const llvm::InstrItinerary LEON3Itineraries[] = {
351 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
352 { 1, 4, 5, 41, 43 }, // 1 IIC_iu_instr
353 { 1, 5, 6, 43, 45 }, // 2 IIC_fpu_normal_instr
354 { 1, 6, 7, 45, 47 }, // 3 IIC_jmp_or_call
355 { 1, 5, 6, 47, 49 }, // 4 IIC_fpu_abs
356 { 1, 5, 6, 49, 51 }, // 5 IIC_fpu_fast_instr
357 { 1, 5, 6, 51, 53 }, // 6 IIC_fpu_divd
358 { 1, 5, 6, 53, 55 }, // 7 IIC_fpu_divs
359 { 1, 5, 6, 55, 57 }, // 8 IIC_fpu_muld
360 { 1, 5, 6, 57, 59 }, // 9 IIC_fpu_muls
361 { 1, 5, 6, 59, 61 }, // 10 IIC_fpu_negs
362 { 1, 5, 6, 61, 63 }, // 11 IIC_fpu_sqrtd
363 { 1, 5, 6, 63, 65 }, // 12 IIC_fpu_sqrts
364 { 1, 5, 6, 65, 67 }, // 13 IIC_fpu_stod
365 { 1, 6, 7, 67, 69 }, // 14 IIC_ldd
366 { 1, 6, 7, 69, 71 }, // 15 IIC_iu_or_fpu_instr
367 { 1, 4, 5, 71, 73 }, // 16 IIC_iu_div
368 { 1, 4, 5, 73, 75 }, // 17 IIC_smac_umac
369 { 1, 4, 5, 75, 77 }, // 18 IIC_iu_smul
370 { 1, 6, 7, 77, 79 }, // 19 IIC_st
371 { 1, 6, 7, 79, 81 }, // 20 IIC_std
372 { 1, 4, 5, 81, 83 }, // 21 IIC_iu_umul
373 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
374};
375
376static const llvm::InstrItinerary LEON4Itineraries[] = {
377 { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
378 { 1, 7, 8, 83, 85 }, // 1 IIC_iu_instr
379 { 1, 8, 9, 85, 87 }, // 2 IIC_fpu_normal_instr
380 { 1, 9, 10, 87, 89 }, // 3 IIC_jmp_or_call
381 { 1, 8, 9, 89, 91 }, // 4 IIC_fpu_abs
382 { 1, 8, 9, 91, 93 }, // 5 IIC_fpu_fast_instr
383 { 1, 8, 9, 93, 95 }, // 6 IIC_fpu_divd
384 { 1, 8, 9, 95, 97 }, // 7 IIC_fpu_divs
385 { 1, 8, 9, 97, 99 }, // 8 IIC_fpu_muld
386 { 1, 8, 9, 99, 101 }, // 9 IIC_fpu_muls
387 { 1, 8, 9, 101, 103 }, // 10 IIC_fpu_negs
388 { 1, 8, 9, 103, 105 }, // 11 IIC_fpu_sqrtd
389 { 1, 8, 9, 105, 107 }, // 12 IIC_fpu_sqrts
390 { 1, 8, 9, 107, 109 }, // 13 IIC_fpu_stod
391 { 1, 9, 10, 109, 111 }, // 14 IIC_ldd
392 { 1, 9, 10, 111, 113 }, // 15 IIC_iu_or_fpu_instr
393 { 1, 7, 8, 113, 115 }, // 16 IIC_iu_div
394 { 1, 7, 8, 115, 117 }, // 17 IIC_smac_umac
395 { 1, 7, 8, 117, 119 }, // 18 IIC_iu_smul
396 { 1, 9, 10, 119, 121 }, // 19 IIC_st
397 { 1, 9, 10, 121, 123 }, // 20 IIC_std
398 { 1, 7, 8, 123, 125 }, // 21 IIC_iu_umul
399 { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
400};
401
402// ===============================================================
403// Data tables for the new per-operand machine model.
404
405// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
406extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[] = {
407 { 0, 0, 0 }, // Invalid
408}; // SparcWriteProcResTable
409
410// {Cycles, WriteResourceID}
411extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[] = {
412 { 0, 0}, // Invalid
413}; // SparcWriteLatencyTable
414
415// {UseIdx, WriteResourceID, Cycles}
416extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[] = {
417 {0, 0, 0}, // Invalid
418}; // SparcReadAdvanceTable
419
420#undef DBGFIELD
421
422static const llvm::MCSchedModel NoSchedModel = {
423 MCSchedModel::DefaultIssueWidth,
424 MCSchedModel::DefaultMicroOpBufferSize,
425 MCSchedModel::DefaultLoopMicroOpBufferSize,
426 MCSchedModel::DefaultLoadLatency,
427 MCSchedModel::DefaultHighLatency,
428 MCSchedModel::DefaultMispredictPenalty,
429 false, // PostRAScheduler
430 false, // CompleteModel
431 false, // EnableIntervals
432 0, // Processor ID
433 nullptr, nullptr, 0, 0, // No instruction-level machine model.
434 nullptr, // No Itinerary
435 nullptr // No extra processor descriptor
436};
437
438static const llvm::MCSchedModel LEON2ItinerariesModel = {
439 MCSchedModel::DefaultIssueWidth,
440 MCSchedModel::DefaultMicroOpBufferSize,
441 MCSchedModel::DefaultLoopMicroOpBufferSize,
442 MCSchedModel::DefaultLoadLatency,
443 MCSchedModel::DefaultHighLatency,
444 MCSchedModel::DefaultMispredictPenalty,
445 false, // PostRAScheduler
446 false, // CompleteModel
447 false, // EnableIntervals
448 1, // Processor ID
449 nullptr, nullptr, 0, 0, // No instruction-level machine model.
450 LEON2Itineraries,
451 nullptr // No extra processor descriptor
452};
453
454static const llvm::MCSchedModel LEON3ItinerariesModel = {
455 MCSchedModel::DefaultIssueWidth,
456 MCSchedModel::DefaultMicroOpBufferSize,
457 MCSchedModel::DefaultLoopMicroOpBufferSize,
458 MCSchedModel::DefaultLoadLatency,
459 MCSchedModel::DefaultHighLatency,
460 MCSchedModel::DefaultMispredictPenalty,
461 false, // PostRAScheduler
462 false, // CompleteModel
463 false, // EnableIntervals
464 2, // Processor ID
465 nullptr, nullptr, 0, 0, // No instruction-level machine model.
466 LEON3Itineraries,
467 nullptr // No extra processor descriptor
468};
469
470static const llvm::MCSchedModel LEON4ItinerariesModel = {
471 MCSchedModel::DefaultIssueWidth,
472 MCSchedModel::DefaultMicroOpBufferSize,
473 MCSchedModel::DefaultLoopMicroOpBufferSize,
474 MCSchedModel::DefaultLoadLatency,
475 MCSchedModel::DefaultHighLatency,
476 MCSchedModel::DefaultMispredictPenalty,
477 false, // PostRAScheduler
478 false, // CompleteModel
479 false, // EnableIntervals
480 3, // Processor ID
481 nullptr, nullptr, 0, 0, // No instruction-level machine model.
482 LEON4Itineraries,
483 nullptr // No extra processor descriptor
484};
485
486// Sorted (by key) array of values for CPU subtype.
487extern const llvm::SubtargetSubTypeKV SparcSubTypeKV[] = {
488 { "at697e", { { { 0x20000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON2ItinerariesModel },
489 { "at697f", { { { 0x20000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON2ItinerariesModel },
490 { "f934", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
491 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
492 { "gr712rc", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON3ItinerariesModel },
493 { "gr740", { { { 0x2c0000000024ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON4ItinerariesModel },
494 { "hypersparc", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
495 { "leon2", { { { 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON2ItinerariesModel },
496 { "leon3", { { { 0x200000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON3ItinerariesModel },
497 { "leon4", { { { 0x240000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON4ItinerariesModel },
498 { "ma2080", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
499 { "ma2085", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
500 { "ma2100", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
501 { "ma2150", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
502 { "ma2155", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
503 { "ma2450", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
504 { "ma2455", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
505 { "ma2480", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
506 { "ma2485", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
507 { "ma2x5x", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
508 { "ma2x8x", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
509 { "myriad2", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
510 { "myriad2.1", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
511 { "myriad2.2", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
512 { "myriad2.3", { { { 0x40000000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
513 { "niagara", { { { 0x7800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
514 { "niagara2", { { { 0x407800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
515 { "niagara3", { { { 0x407800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
516 { "niagara4", { { { 0x40f800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
517 { "sparclet", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
518 { "sparclite", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
519 { "sparclite86x", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
520 { "supersparc", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
521 { "tsc701", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
522 { "ultrasparc", { { { 0x3800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x100000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
523 { "ultrasparc3", { { { 0x7800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x100000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
524 { "ut699", { { { 0x3000000001cULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LEON3ItinerariesModel },
525 { "v7", { { { 0x400000010ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
526 { "v8", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
527 { "v9", { { { 0x1000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
528};
529
530namespace Sparc_MC {
531unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
532 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
533 // Don't know how to resolve this scheduling class.
534 return 0;
535}
536} // end namespace Sparc_MC
537
538struct SparcGenMCSubtargetInfo : public MCSubtargetInfo {
539 SparcGenMCSubtargetInfo(const Triple &TT,
540 StringRef CPU, StringRef TuneCPU, StringRef FS,
541 ArrayRef<SubtargetFeatureKV> PF,
542 ArrayRef<SubtargetSubTypeKV> PD,
543 const MCWriteProcResEntry *WPR,
544 const MCWriteLatencyEntry *WL,
545 const MCReadAdvanceEntry *RA, const InstrStage *IS,
546 const unsigned *OC, const unsigned *FP) :
547 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
548 WPR, WL, RA, IS, OC, FP) { }
549
550 unsigned resolveVariantSchedClass(unsigned SchedClass,
551 const MCInst *MI, const MCInstrInfo *MCII,
552 unsigned CPUID) const override {
553 return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
554 }
555};
556
557static inline MCSubtargetInfo *createSparcMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
558 return new SparcGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, SparcFeatureKV, SparcSubTypeKV,
559 SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable,
560 SparcStages, SparcOperandCycles, SparcForwardingPaths);
561}
562
563} // end namespace llvm
564
565#endif // GET_SUBTARGETINFO_MC_DESC
566
567
568#ifdef GET_SUBTARGETINFO_TARGET_DESC
569#undef GET_SUBTARGETINFO_TARGET_DESC
570
571#include "llvm/Support/Debug.h"
572#include "llvm/Support/raw_ostream.h"
573
574// ParseSubtargetFeatures - Parses features string setting specified
575// subtarget options.
576void llvm::SparcSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
577 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
578 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
579 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
580 InitMCProcessorInfo(CPU, TuneCPU, FS);
581 const FeatureBitset &Bits = getFeatureBits();
582 if (Bits[Sparc::DetectRoundChange]) DetectRoundChange = true;
583 if (Bits[Sparc::FeatureHardQuad]) HasHardQuad = true;
584 if (Bits[Sparc::FeatureLeon]) IsLeon = true;
585 if (Bits[Sparc::FeatureNoFMULS]) HasNoFMULS = true;
586 if (Bits[Sparc::FeatureNoFSMULD]) HasNoFSMULD = true;
587 if (Bits[Sparc::FeaturePWRPSR]) HasPWRPSR = true;
588 if (Bits[Sparc::FeatureReserveG1]) ReserveRegister[1 + SP::G0] = true;
589 if (Bits[Sparc::FeatureReserveG2]) ReserveRegister[2 + SP::G0] = true;
590 if (Bits[Sparc::FeatureReserveG3]) ReserveRegister[3 + SP::G0] = true;
591 if (Bits[Sparc::FeatureReserveG4]) ReserveRegister[4 + SP::G0] = true;
592 if (Bits[Sparc::FeatureReserveG5]) ReserveRegister[5 + SP::G0] = true;
593 if (Bits[Sparc::FeatureReserveG6]) ReserveRegister[6 + SP::G0] = true;
594 if (Bits[Sparc::FeatureReserveG7]) ReserveRegister[7 + SP::G0] = true;
595 if (Bits[Sparc::FeatureReserveI0]) ReserveRegister[0 + SP::I0] = true;
596 if (Bits[Sparc::FeatureReserveI1]) ReserveRegister[1 + SP::I0] = true;
597 if (Bits[Sparc::FeatureReserveI2]) ReserveRegister[2 + SP::I0] = true;
598 if (Bits[Sparc::FeatureReserveI3]) ReserveRegister[3 + SP::I0] = true;
599 if (Bits[Sparc::FeatureReserveI4]) ReserveRegister[4 + SP::I0] = true;
600 if (Bits[Sparc::FeatureReserveI5]) ReserveRegister[5 + SP::I0] = true;
601 if (Bits[Sparc::FeatureReserveL0]) ReserveRegister[0 + SP::L0] = true;
602 if (Bits[Sparc::FeatureReserveL1]) ReserveRegister[1 + SP::L0] = true;
603 if (Bits[Sparc::FeatureReserveL2]) ReserveRegister[2 + SP::L0] = true;
604 if (Bits[Sparc::FeatureReserveL3]) ReserveRegister[3 + SP::L0] = true;
605 if (Bits[Sparc::FeatureReserveL4]) ReserveRegister[4 + SP::L0] = true;
606 if (Bits[Sparc::FeatureReserveL5]) ReserveRegister[5 + SP::L0] = true;
607 if (Bits[Sparc::FeatureReserveL6]) ReserveRegister[6 + SP::L0] = true;
608 if (Bits[Sparc::FeatureReserveL7]) ReserveRegister[7 + SP::L0] = true;
609 if (Bits[Sparc::FeatureReserveO0]) ReserveRegister[0 + SP::O0] = true;
610 if (Bits[Sparc::FeatureReserveO1]) ReserveRegister[1 + SP::O0] = true;
611 if (Bits[Sparc::FeatureReserveO2]) ReserveRegister[2 + SP::O0] = true;
612 if (Bits[Sparc::FeatureReserveO3]) ReserveRegister[3 + SP::O0] = true;
613 if (Bits[Sparc::FeatureReserveO4]) ReserveRegister[4 + SP::O0] = true;
614 if (Bits[Sparc::FeatureReserveO5]) ReserveRegister[5 + SP::O0] = true;
615 if (Bits[Sparc::FeatureSoftFloat]) UseSoftFloat = true;
616 if (Bits[Sparc::FeatureSoftMulDiv]) UseSoftMulDiv = true;
617 if (Bits[Sparc::FeatureV8Deprecated]) UseV8DeprecatedInsts = true;
618 if (Bits[Sparc::FeatureV9]) IsV9 = true;
619 if (Bits[Sparc::FeatureVIS]) IsVIS = true;
620 if (Bits[Sparc::FeatureVIS2]) IsVIS2 = true;
621 if (Bits[Sparc::FeatureVIS3]) IsVIS3 = true;
622 if (Bits[Sparc::FixAllFDIVSQRT]) FixAllFDIVSQRT = true;
623 if (Bits[Sparc::InsertNOPLoad]) InsertNOPLoad = true;
624 if (Bits[Sparc::LeonCASA]) HasLeonCasa = true;
625 if (Bits[Sparc::LeonCycleCounter]) HasLeonCycleCounter = true;
626 if (Bits[Sparc::TuneSlowRDPC]) HasSlowRDPC = true;
627 if (Bits[Sparc::UMACSMACSupport]) HasUmacSmac = true;
628 if (Bits[Sparc::UsePopc]) UsePopc = true;
629}
630#endif // GET_SUBTARGETINFO_TARGET_DESC
631
632
633#ifdef GET_SUBTARGETINFO_HEADER
634#undef GET_SUBTARGETINFO_HEADER
635
636namespace llvm {
637class DFAPacketizer;
638namespace Sparc_MC {
639unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
640} // end namespace Sparc_MC
641
642struct SparcGenSubtargetInfo : public TargetSubtargetInfo {
643 explicit SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
644public:
645 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
646 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
647 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
648};
649} // end namespace llvm
650
651#endif // GET_SUBTARGETINFO_HEADER
652
653
654#ifdef GET_SUBTARGETINFO_CTOR
655#undef GET_SUBTARGETINFO_CTOR
656
657#include "llvm/CodeGen/TargetSchedule.h"
658
659namespace llvm {
660extern const llvm::SubtargetFeatureKV SparcFeatureKV[];
661extern const llvm::SubtargetSubTypeKV SparcSubTypeKV[];
662extern const llvm::MCWriteProcResEntry SparcWriteProcResTable[];
663extern const llvm::MCWriteLatencyEntry SparcWriteLatencyTable[];
664extern const llvm::MCReadAdvanceEntry SparcReadAdvanceTable[];
665extern const llvm::InstrStage SparcStages[];
666extern const unsigned SparcOperandCycles[];
667extern const unsigned SparcForwardingPaths[];
668SparcGenSubtargetInfo::SparcGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
669 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(SparcFeatureKV, 47), ArrayRef(SparcSubTypeKV, 40),
670 SparcWriteProcResTable, SparcWriteLatencyTable, SparcReadAdvanceTable,
671 SparcStages, SparcOperandCycles, SparcForwardingPaths) {}
672
673unsigned SparcGenSubtargetInfo
674::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
675 report_fatal_error("Expected a variant SchedClass");
676} // SparcGenSubtargetInfo::resolveSchedClass
677
678unsigned SparcGenSubtargetInfo
679::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
680 return Sparc_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
681} // SparcGenSubtargetInfo::resolveVariantSchedClass
682
683} // end namespace llvm
684
685#endif // GET_SUBTARGETINFO_CTOR
686
687
688#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
689#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
690
691#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
692
693
694#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
695#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
696
697#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
698
699