1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass VEMCRegisterClasses[];
17
18namespace VE {
19enum {
20 NoRegister,
21 IC = 1,
22 PMMR = 2,
23 PSW = 3,
24 SAR = 4,
25 USRCC = 5,
26 VIX = 6,
27 VL = 7,
28 PMC0 = 8,
29 PMC1 = 9,
30 PMC2 = 10,
31 PMC3 = 11,
32 PMC4 = 12,
33 PMC5 = 13,
34 PMC6 = 14,
35 PMC7 = 15,
36 PMC8 = 16,
37 PMC9 = 17,
38 PMC10 = 18,
39 PMC11 = 19,
40 PMC12 = 20,
41 PMC13 = 21,
42 PMC14 = 22,
43 PMCR0 = 23,
44 PMCR1 = 24,
45 PMCR2 = 25,
46 PMCR3 = 26,
47 Q0 = 27,
48 Q1 = 28,
49 Q2 = 29,
50 Q3 = 30,
51 Q4 = 31,
52 Q5 = 32,
53 Q6 = 33,
54 Q7 = 34,
55 Q8 = 35,
56 Q9 = 36,
57 Q10 = 37,
58 Q11 = 38,
59 Q12 = 39,
60 Q13 = 40,
61 Q14 = 41,
62 Q15 = 42,
63 Q16 = 43,
64 Q17 = 44,
65 Q18 = 45,
66 Q19 = 46,
67 Q20 = 47,
68 Q21 = 48,
69 Q22 = 49,
70 Q23 = 50,
71 Q24 = 51,
72 Q25 = 52,
73 Q26 = 53,
74 Q27 = 54,
75 Q28 = 55,
76 Q29 = 56,
77 Q30 = 57,
78 Q31 = 58,
79 SF0 = 59,
80 SF1 = 60,
81 SF2 = 61,
82 SF3 = 62,
83 SF4 = 63,
84 SF5 = 64,
85 SF6 = 65,
86 SF7 = 66,
87 SF8 = 67,
88 SF9 = 68,
89 SF10 = 69,
90 SF11 = 70,
91 SF12 = 71,
92 SF13 = 72,
93 SF14 = 73,
94 SF15 = 74,
95 SF16 = 75,
96 SF17 = 76,
97 SF18 = 77,
98 SF19 = 78,
99 SF20 = 79,
100 SF21 = 80,
101 SF22 = 81,
102 SF23 = 82,
103 SF24 = 83,
104 SF25 = 84,
105 SF26 = 85,
106 SF27 = 86,
107 SF28 = 87,
108 SF29 = 88,
109 SF30 = 89,
110 SF31 = 90,
111 SF32 = 91,
112 SF33 = 92,
113 SF34 = 93,
114 SF35 = 94,
115 SF36 = 95,
116 SF37 = 96,
117 SF38 = 97,
118 SF39 = 98,
119 SF40 = 99,
120 SF41 = 100,
121 SF42 = 101,
122 SF43 = 102,
123 SF44 = 103,
124 SF45 = 104,
125 SF46 = 105,
126 SF47 = 106,
127 SF48 = 107,
128 SF49 = 108,
129 SF50 = 109,
130 SF51 = 110,
131 SF52 = 111,
132 SF53 = 112,
133 SF54 = 113,
134 SF55 = 114,
135 SF56 = 115,
136 SF57 = 116,
137 SF58 = 117,
138 SF59 = 118,
139 SF60 = 119,
140 SF61 = 120,
141 SF62 = 121,
142 SF63 = 122,
143 SW0 = 123,
144 SW1 = 124,
145 SW2 = 125,
146 SW3 = 126,
147 SW4 = 127,
148 SW5 = 128,
149 SW6 = 129,
150 SW7 = 130,
151 SW8 = 131,
152 SW9 = 132,
153 SW10 = 133,
154 SW11 = 134,
155 SW12 = 135,
156 SW13 = 136,
157 SW14 = 137,
158 SW15 = 138,
159 SW16 = 139,
160 SW17 = 140,
161 SW18 = 141,
162 SW19 = 142,
163 SW20 = 143,
164 SW21 = 144,
165 SW22 = 145,
166 SW23 = 146,
167 SW24 = 147,
168 SW25 = 148,
169 SW26 = 149,
170 SW27 = 150,
171 SW28 = 151,
172 SW29 = 152,
173 SW30 = 153,
174 SW31 = 154,
175 SW32 = 155,
176 SW33 = 156,
177 SW34 = 157,
178 SW35 = 158,
179 SW36 = 159,
180 SW37 = 160,
181 SW38 = 161,
182 SW39 = 162,
183 SW40 = 163,
184 SW41 = 164,
185 SW42 = 165,
186 SW43 = 166,
187 SW44 = 167,
188 SW45 = 168,
189 SW46 = 169,
190 SW47 = 170,
191 SW48 = 171,
192 SW49 = 172,
193 SW50 = 173,
194 SW51 = 174,
195 SW52 = 175,
196 SW53 = 176,
197 SW54 = 177,
198 SW55 = 178,
199 SW56 = 179,
200 SW57 = 180,
201 SW58 = 181,
202 SW59 = 182,
203 SW60 = 183,
204 SW61 = 184,
205 SW62 = 185,
206 SW63 = 186,
207 SX0 = 187,
208 SX1 = 188,
209 SX2 = 189,
210 SX3 = 190,
211 SX4 = 191,
212 SX5 = 192,
213 SX6 = 193,
214 SX7 = 194,
215 SX8 = 195,
216 SX9 = 196,
217 SX10 = 197,
218 SX11 = 198,
219 SX12 = 199,
220 SX13 = 200,
221 SX14 = 201,
222 SX15 = 202,
223 SX16 = 203,
224 SX17 = 204,
225 SX18 = 205,
226 SX19 = 206,
227 SX20 = 207,
228 SX21 = 208,
229 SX22 = 209,
230 SX23 = 210,
231 SX24 = 211,
232 SX25 = 212,
233 SX26 = 213,
234 SX27 = 214,
235 SX28 = 215,
236 SX29 = 216,
237 SX30 = 217,
238 SX31 = 218,
239 SX32 = 219,
240 SX33 = 220,
241 SX34 = 221,
242 SX35 = 222,
243 SX36 = 223,
244 SX37 = 224,
245 SX38 = 225,
246 SX39 = 226,
247 SX40 = 227,
248 SX41 = 228,
249 SX42 = 229,
250 SX43 = 230,
251 SX44 = 231,
252 SX45 = 232,
253 SX46 = 233,
254 SX47 = 234,
255 SX48 = 235,
256 SX49 = 236,
257 SX50 = 237,
258 SX51 = 238,
259 SX52 = 239,
260 SX53 = 240,
261 SX54 = 241,
262 SX55 = 242,
263 SX56 = 243,
264 SX57 = 244,
265 SX58 = 245,
266 SX59 = 246,
267 SX60 = 247,
268 SX61 = 248,
269 SX62 = 249,
270 SX63 = 250,
271 V0 = 251,
272 V1 = 252,
273 V2 = 253,
274 V3 = 254,
275 V4 = 255,
276 V5 = 256,
277 V6 = 257,
278 V7 = 258,
279 V8 = 259,
280 V9 = 260,
281 V10 = 261,
282 V11 = 262,
283 V12 = 263,
284 V13 = 264,
285 V14 = 265,
286 V15 = 266,
287 V16 = 267,
288 V17 = 268,
289 V18 = 269,
290 V19 = 270,
291 V20 = 271,
292 V21 = 272,
293 V22 = 273,
294 V23 = 274,
295 V24 = 275,
296 V25 = 276,
297 V26 = 277,
298 V27 = 278,
299 V28 = 279,
300 V29 = 280,
301 V30 = 281,
302 V31 = 282,
303 V32 = 283,
304 V33 = 284,
305 V34 = 285,
306 V35 = 286,
307 V36 = 287,
308 V37 = 288,
309 V38 = 289,
310 V39 = 290,
311 V40 = 291,
312 V41 = 292,
313 V42 = 293,
314 V43 = 294,
315 V44 = 295,
316 V45 = 296,
317 V46 = 297,
318 V47 = 298,
319 V48 = 299,
320 V49 = 300,
321 V50 = 301,
322 V51 = 302,
323 V52 = 303,
324 V53 = 304,
325 V54 = 305,
326 V55 = 306,
327 V56 = 307,
328 V57 = 308,
329 V58 = 309,
330 V59 = 310,
331 V60 = 311,
332 V61 = 312,
333 V62 = 313,
334 V63 = 314,
335 VM0 = 315,
336 VM1 = 316,
337 VM2 = 317,
338 VM3 = 318,
339 VM4 = 319,
340 VM5 = 320,
341 VM6 = 321,
342 VM7 = 322,
343 VM8 = 323,
344 VM9 = 324,
345 VM10 = 325,
346 VM11 = 326,
347 VM12 = 327,
348 VM13 = 328,
349 VM14 = 329,
350 VM15 = 330,
351 VMP0 = 331,
352 VMP1 = 332,
353 VMP2 = 333,
354 VMP3 = 334,
355 VMP4 = 335,
356 VMP5 = 336,
357 VMP6 = 337,
358 VMP7 = 338,
359 NUM_TARGET_REGS // 339
360};
361} // end namespace VE
362
363// Register classes
364
365namespace VE {
366enum {
367 F32RegClassID = 0,
368 I32RegClassID = 1,
369 VLSRegClassID = 2,
370 I64RegClassID = 3,
371 MISCRegClassID = 4,
372 F128RegClassID = 5,
373 VMRegClassID = 6,
374 VM512RegClassID = 7,
375 VM512_with_sub_vm_evenRegClassID = 8,
376 V64RegClassID = 9,
377
378};
379} // end namespace VE
380
381
382// Register alternate name indices
383
384namespace VE {
385enum {
386 AsmName, // 0
387 NoRegAltName, // 1
388 NUM_TARGET_REG_ALT_NAMES = 2
389};
390} // end namespace VE
391
392
393// Subregister indices
394
395namespace VE {
396enum : uint16_t {
397 NoSubRegister,
398 sub_even, // 1
399 sub_f32, // 2
400 sub_i32, // 3
401 sub_odd, // 4
402 sub_vm_even, // 5
403 sub_vm_odd, // 6
404 sub_odd_then_sub_f32, // 7
405 sub_odd_then_sub_i32, // 8
406 NUM_TARGET_SUBREGS
407};
408} // end namespace VE
409
410// Register pressure sets enum.
411namespace VE {
412enum RegisterPressureSets {
413 VLS = 0,
414 VM512 = 1,
415 VM = 2,
416 VM_with_VM512 = 3,
417 MISC = 4,
418 F32 = 5,
419 V64 = 6,
420};
421} // end namespace VE
422
423} // end namespace llvm
424
425#endif // GET_REGINFO_ENUM
426
427/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
428|* *|
429|* MC Register Information *|
430|* *|
431|* Automatically generated file, do not edit! *|
432|* *|
433\*===----------------------------------------------------------------------===*/
434
435
436#ifdef GET_REGINFO_MC_DESC
437#undef GET_REGINFO_MC_DESC
438
439namespace llvm {
440
441extern const int16_t VERegDiffLists[] = {
442 /* 0 */ 64, -192, 0,
443 /* 3 */ 128, -192, 0,
444 /* 6 */ 64, -191, 0,
445 /* 9 */ 128, -191, 0,
446 /* 12 */ 64, -190, 0,
447 /* 15 */ 128, -190, 0,
448 /* 18 */ 64, -189, 0,
449 /* 21 */ 128, -189, 0,
450 /* 24 */ 64, -188, 0,
451 /* 27 */ 128, -188, 0,
452 /* 30 */ 64, -187, 0,
453 /* 33 */ 128, -187, 0,
454 /* 36 */ 64, -186, 0,
455 /* 39 */ 128, -186, 0,
456 /* 42 */ 64, -185, 0,
457 /* 45 */ 128, -185, 0,
458 /* 48 */ 64, -184, 0,
459 /* 51 */ 128, -184, 0,
460 /* 54 */ 64, -183, 0,
461 /* 57 */ 128, -183, 0,
462 /* 60 */ 64, -182, 0,
463 /* 63 */ 128, -182, 0,
464 /* 66 */ 64, -181, 0,
465 /* 69 */ 128, -181, 0,
466 /* 72 */ 64, -180, 0,
467 /* 75 */ 128, -180, 0,
468 /* 78 */ 64, -179, 0,
469 /* 81 */ 128, -179, 0,
470 /* 84 */ 64, -178, 0,
471 /* 87 */ 128, -178, 0,
472 /* 90 */ 64, -177, 0,
473 /* 93 */ 128, -177, 0,
474 /* 96 */ 64, -176, 0,
475 /* 99 */ 128, -176, 0,
476 /* 102 */ 64, -175, 0,
477 /* 105 */ 128, -175, 0,
478 /* 108 */ 64, -174, 0,
479 /* 111 */ 128, -174, 0,
480 /* 114 */ 64, -173, 0,
481 /* 117 */ 128, -173, 0,
482 /* 120 */ 64, -172, 0,
483 /* 123 */ 128, -172, 0,
484 /* 126 */ 64, -171, 0,
485 /* 129 */ 128, -171, 0,
486 /* 132 */ 64, -170, 0,
487 /* 135 */ 128, -170, 0,
488 /* 138 */ 64, -169, 0,
489 /* 141 */ 128, -169, 0,
490 /* 144 */ 64, -168, 0,
491 /* 147 */ 128, -168, 0,
492 /* 150 */ 64, -167, 0,
493 /* 153 */ 128, -167, 0,
494 /* 156 */ 64, -166, 0,
495 /* 159 */ 128, -166, 0,
496 /* 162 */ 64, -165, 0,
497 /* 165 */ 128, -165, 0,
498 /* 168 */ 64, -164, 0,
499 /* 171 */ 128, -164, 0,
500 /* 174 */ 64, -163, 0,
501 /* 177 */ 128, -163, 0,
502 /* 180 */ 64, -162, 0,
503 /* 183 */ 128, -162, 0,
504 /* 186 */ 64, -161, 0,
505 /* 189 */ 128, -161, 0,
506 /* 192 */ 64, -160, 0,
507 /* 195 */ 128, -160, 0,
508 /* 198 */ 160, -64, -64, 129, -64, -64, 0,
509 /* 205 */ 161, -64, -64, 129, -64, -64, 0,
510 /* 212 */ 162, -64, -64, 129, -64, -64, 0,
511 /* 219 */ 163, -64, -64, 129, -64, -64, 0,
512 /* 226 */ 164, -64, -64, 129, -64, -64, 0,
513 /* 233 */ 165, -64, -64, 129, -64, -64, 0,
514 /* 240 */ 166, -64, -64, 129, -64, -64, 0,
515 /* 247 */ 167, -64, -64, 129, -64, -64, 0,
516 /* 254 */ 168, -64, -64, 129, -64, -64, 0,
517 /* 261 */ 169, -64, -64, 129, -64, -64, 0,
518 /* 268 */ 170, -64, -64, 129, -64, -64, 0,
519 /* 275 */ 171, -64, -64, 129, -64, -64, 0,
520 /* 282 */ 172, -64, -64, 129, -64, -64, 0,
521 /* 289 */ 173, -64, -64, 129, -64, -64, 0,
522 /* 296 */ 174, -64, -64, 129, -64, -64, 0,
523 /* 303 */ 175, -64, -64, 129, -64, -64, 0,
524 /* 310 */ 176, -64, -64, 129, -64, -64, 0,
525 /* 317 */ 177, -64, -64, 129, -64, -64, 0,
526 /* 324 */ 178, -64, -64, 129, -64, -64, 0,
527 /* 331 */ 179, -64, -64, 129, -64, -64, 0,
528 /* 338 */ 180, -64, -64, 129, -64, -64, 0,
529 /* 345 */ 181, -64, -64, 129, -64, -64, 0,
530 /* 352 */ 182, -64, -64, 129, -64, -64, 0,
531 /* 359 */ 183, -64, -64, 129, -64, -64, 0,
532 /* 366 */ 184, -64, -64, 129, -64, -64, 0,
533 /* 373 */ 185, -64, -64, 129, -64, -64, 0,
534 /* 380 */ 186, -64, -64, 129, -64, -64, 0,
535 /* 387 */ 187, -64, -64, 129, -64, -64, 0,
536 /* 394 */ 188, -64, -64, 129, -64, -64, 0,
537 /* 401 */ 189, -64, -64, 129, -64, -64, 0,
538 /* 408 */ 190, -64, -64, 129, -64, -64, 0,
539 /* 415 */ 191, -64, -64, 129, -64, -64, 0,
540 /* 422 */ -15, 1, 0,
541 /* 425 */ -14, 1, 0,
542 /* 428 */ -13, 1, 0,
543 /* 431 */ -12, 1, 0,
544 /* 434 */ -11, 1, 0,
545 /* 437 */ -10, 1, 0,
546 /* 440 */ -9, 1, 0,
547 /* 443 */ 8, 0,
548 /* 445 */ 9, 0,
549 /* 447 */ 10, 0,
550 /* 449 */ 11, 0,
551 /* 451 */ 12, 0,
552 /* 453 */ 13, 0,
553 /* 455 */ 14, 0,
554 /* 457 */ 15, 0,
555};
556
557extern const LaneBitmask VELaneMaskLists[] = {
558 /* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),
559 /* 3 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
560 /* 6 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
561};
562
563extern const uint16_t VESubRegIdxLists[] = {
564 /* 0 */ 3, 2, 0,
565 /* 3 */ 5, 6, 0,
566 /* 6 */ 1, 3, 2, 4, 8, 7, 0,
567};
568
569
570#ifdef __GNUC__
571#pragma GCC diagnostic push
572#pragma GCC diagnostic ignored "-Woverlength-strings"
573#endif
574extern const char VERegStrings[] = {
575 /* 0 */ "PMC10\0"
576 /* 6 */ "SF10\0"
577 /* 11 */ "VM10\0"
578 /* 16 */ "Q10\0"
579 /* 20 */ "V10\0"
580 /* 24 */ "SW10\0"
581 /* 29 */ "SX10\0"
582 /* 34 */ "SF20\0"
583 /* 39 */ "Q20\0"
584 /* 43 */ "V20\0"
585 /* 47 */ "SW20\0"
586 /* 52 */ "SX20\0"
587 /* 57 */ "SF30\0"
588 /* 62 */ "Q30\0"
589 /* 66 */ "V30\0"
590 /* 70 */ "SW30\0"
591 /* 75 */ "SX30\0"
592 /* 80 */ "SF40\0"
593 /* 85 */ "V40\0"
594 /* 89 */ "SW40\0"
595 /* 94 */ "SX40\0"
596 /* 99 */ "SF50\0"
597 /* 104 */ "V50\0"
598 /* 108 */ "SW50\0"
599 /* 113 */ "SX50\0"
600 /* 118 */ "SF60\0"
601 /* 123 */ "V60\0"
602 /* 127 */ "SW60\0"
603 /* 132 */ "SX60\0"
604 /* 137 */ "PMC0\0"
605 /* 142 */ "SF0\0"
606 /* 146 */ "VM0\0"
607 /* 150 */ "VMP0\0"
608 /* 155 */ "Q0\0"
609 /* 158 */ "PMCR0\0"
610 /* 164 */ "V0\0"
611 /* 167 */ "SW0\0"
612 /* 171 */ "SX0\0"
613 /* 175 */ "PMC11\0"
614 /* 181 */ "SF11\0"
615 /* 186 */ "VM11\0"
616 /* 191 */ "Q11\0"
617 /* 195 */ "V11\0"
618 /* 199 */ "SW11\0"
619 /* 204 */ "SX11\0"
620 /* 209 */ "SF21\0"
621 /* 214 */ "Q21\0"
622 /* 218 */ "V21\0"
623 /* 222 */ "SW21\0"
624 /* 227 */ "SX21\0"
625 /* 232 */ "SF31\0"
626 /* 237 */ "Q31\0"
627 /* 241 */ "V31\0"
628 /* 245 */ "SW31\0"
629 /* 250 */ "SX31\0"
630 /* 255 */ "SF41\0"
631 /* 260 */ "V41\0"
632 /* 264 */ "SW41\0"
633 /* 269 */ "SX41\0"
634 /* 274 */ "SF51\0"
635 /* 279 */ "V51\0"
636 /* 283 */ "SW51\0"
637 /* 288 */ "SX51\0"
638 /* 293 */ "SF61\0"
639 /* 298 */ "V61\0"
640 /* 302 */ "SW61\0"
641 /* 307 */ "SX61\0"
642 /* 312 */ "PMC1\0"
643 /* 317 */ "SF1\0"
644 /* 321 */ "VM1\0"
645 /* 325 */ "VMP1\0"
646 /* 330 */ "Q1\0"
647 /* 333 */ "PMCR1\0"
648 /* 339 */ "V1\0"
649 /* 342 */ "SW1\0"
650 /* 346 */ "SX1\0"
651 /* 350 */ "PMC12\0"
652 /* 356 */ "SF12\0"
653 /* 361 */ "VM12\0"
654 /* 366 */ "Q12\0"
655 /* 370 */ "V12\0"
656 /* 374 */ "SW12\0"
657 /* 379 */ "SX12\0"
658 /* 384 */ "SF22\0"
659 /* 389 */ "Q22\0"
660 /* 393 */ "V22\0"
661 /* 397 */ "SW22\0"
662 /* 402 */ "SX22\0"
663 /* 407 */ "SF32\0"
664 /* 412 */ "V32\0"
665 /* 416 */ "SW32\0"
666 /* 421 */ "SX32\0"
667 /* 426 */ "SF42\0"
668 /* 431 */ "V42\0"
669 /* 435 */ "SW42\0"
670 /* 440 */ "SX42\0"
671 /* 445 */ "SF52\0"
672 /* 450 */ "V52\0"
673 /* 454 */ "SW52\0"
674 /* 459 */ "SX52\0"
675 /* 464 */ "SF62\0"
676 /* 469 */ "V62\0"
677 /* 473 */ "SW62\0"
678 /* 478 */ "SX62\0"
679 /* 483 */ "PMC2\0"
680 /* 488 */ "SF2\0"
681 /* 492 */ "VM2\0"
682 /* 496 */ "VMP2\0"
683 /* 501 */ "Q2\0"
684 /* 504 */ "PMCR2\0"
685 /* 510 */ "V2\0"
686 /* 513 */ "SW2\0"
687 /* 517 */ "SX2\0"
688 /* 521 */ "PMC13\0"
689 /* 527 */ "SF13\0"
690 /* 532 */ "VM13\0"
691 /* 537 */ "Q13\0"
692 /* 541 */ "V13\0"
693 /* 545 */ "SW13\0"
694 /* 550 */ "SX13\0"
695 /* 555 */ "SF23\0"
696 /* 560 */ "Q23\0"
697 /* 564 */ "V23\0"
698 /* 568 */ "SW23\0"
699 /* 573 */ "SX23\0"
700 /* 578 */ "SF33\0"
701 /* 583 */ "V33\0"
702 /* 587 */ "SW33\0"
703 /* 592 */ "SX33\0"
704 /* 597 */ "SF43\0"
705 /* 602 */ "V43\0"
706 /* 606 */ "SW43\0"
707 /* 611 */ "SX43\0"
708 /* 616 */ "SF53\0"
709 /* 621 */ "V53\0"
710 /* 625 */ "SW53\0"
711 /* 630 */ "SX53\0"
712 /* 635 */ "SF63\0"
713 /* 640 */ "V63\0"
714 /* 644 */ "SW63\0"
715 /* 649 */ "SX63\0"
716 /* 654 */ "PMC3\0"
717 /* 659 */ "SF3\0"
718 /* 663 */ "VM3\0"
719 /* 667 */ "VMP3\0"
720 /* 672 */ "Q3\0"
721 /* 675 */ "PMCR3\0"
722 /* 681 */ "V3\0"
723 /* 684 */ "SW3\0"
724 /* 688 */ "SX3\0"
725 /* 692 */ "PMC14\0"
726 /* 698 */ "SF14\0"
727 /* 703 */ "VM14\0"
728 /* 708 */ "Q14\0"
729 /* 712 */ "V14\0"
730 /* 716 */ "SW14\0"
731 /* 721 */ "SX14\0"
732 /* 726 */ "SF24\0"
733 /* 731 */ "Q24\0"
734 /* 735 */ "V24\0"
735 /* 739 */ "SW24\0"
736 /* 744 */ "SX24\0"
737 /* 749 */ "SF34\0"
738 /* 754 */ "V34\0"
739 /* 758 */ "SW34\0"
740 /* 763 */ "SX34\0"
741 /* 768 */ "SF44\0"
742 /* 773 */ "V44\0"
743 /* 777 */ "SW44\0"
744 /* 782 */ "SX44\0"
745 /* 787 */ "SF54\0"
746 /* 792 */ "V54\0"
747 /* 796 */ "SW54\0"
748 /* 801 */ "SX54\0"
749 /* 806 */ "PMC4\0"
750 /* 811 */ "SF4\0"
751 /* 815 */ "VM4\0"
752 /* 819 */ "VMP4\0"
753 /* 824 */ "Q4\0"
754 /* 827 */ "V4\0"
755 /* 830 */ "SW4\0"
756 /* 834 */ "SX4\0"
757 /* 838 */ "SF15\0"
758 /* 843 */ "VM15\0"
759 /* 848 */ "Q15\0"
760 /* 852 */ "V15\0"
761 /* 856 */ "SW15\0"
762 /* 861 */ "SX15\0"
763 /* 866 */ "SF25\0"
764 /* 871 */ "Q25\0"
765 /* 875 */ "V25\0"
766 /* 879 */ "SW25\0"
767 /* 884 */ "SX25\0"
768 /* 889 */ "SF35\0"
769 /* 894 */ "V35\0"
770 /* 898 */ "SW35\0"
771 /* 903 */ "SX35\0"
772 /* 908 */ "SF45\0"
773 /* 913 */ "V45\0"
774 /* 917 */ "SW45\0"
775 /* 922 */ "SX45\0"
776 /* 927 */ "SF55\0"
777 /* 932 */ "V55\0"
778 /* 936 */ "SW55\0"
779 /* 941 */ "SX55\0"
780 /* 946 */ "PMC5\0"
781 /* 951 */ "SF5\0"
782 /* 955 */ "VM5\0"
783 /* 959 */ "VMP5\0"
784 /* 964 */ "Q5\0"
785 /* 967 */ "V5\0"
786 /* 970 */ "SW5\0"
787 /* 974 */ "SX5\0"
788 /* 978 */ "SF16\0"
789 /* 983 */ "Q16\0"
790 /* 987 */ "V16\0"
791 /* 991 */ "SW16\0"
792 /* 996 */ "SX16\0"
793 /* 1001 */ "SF26\0"
794 /* 1006 */ "Q26\0"
795 /* 1010 */ "V26\0"
796 /* 1014 */ "SW26\0"
797 /* 1019 */ "SX26\0"
798 /* 1024 */ "SF36\0"
799 /* 1029 */ "V36\0"
800 /* 1033 */ "SW36\0"
801 /* 1038 */ "SX36\0"
802 /* 1043 */ "SF46\0"
803 /* 1048 */ "V46\0"
804 /* 1052 */ "SW46\0"
805 /* 1057 */ "SX46\0"
806 /* 1062 */ "SF56\0"
807 /* 1067 */ "V56\0"
808 /* 1071 */ "SW56\0"
809 /* 1076 */ "SX56\0"
810 /* 1081 */ "PMC6\0"
811 /* 1086 */ "SF6\0"
812 /* 1090 */ "VM6\0"
813 /* 1094 */ "VMP6\0"
814 /* 1099 */ "Q6\0"
815 /* 1102 */ "V6\0"
816 /* 1105 */ "SW6\0"
817 /* 1109 */ "SX6\0"
818 /* 1113 */ "SF17\0"
819 /* 1118 */ "Q17\0"
820 /* 1122 */ "V17\0"
821 /* 1126 */ "SW17\0"
822 /* 1131 */ "SX17\0"
823 /* 1136 */ "SF27\0"
824 /* 1141 */ "Q27\0"
825 /* 1145 */ "V27\0"
826 /* 1149 */ "SW27\0"
827 /* 1154 */ "SX27\0"
828 /* 1159 */ "SF37\0"
829 /* 1164 */ "V37\0"
830 /* 1168 */ "SW37\0"
831 /* 1173 */ "SX37\0"
832 /* 1178 */ "SF47\0"
833 /* 1183 */ "V47\0"
834 /* 1187 */ "SW47\0"
835 /* 1192 */ "SX47\0"
836 /* 1197 */ "SF57\0"
837 /* 1202 */ "V57\0"
838 /* 1206 */ "SW57\0"
839 /* 1211 */ "SX57\0"
840 /* 1216 */ "PMC7\0"
841 /* 1221 */ "SF7\0"
842 /* 1225 */ "VM7\0"
843 /* 1229 */ "VMP7\0"
844 /* 1234 */ "Q7\0"
845 /* 1237 */ "V7\0"
846 /* 1240 */ "SW7\0"
847 /* 1244 */ "SX7\0"
848 /* 1248 */ "SF18\0"
849 /* 1253 */ "Q18\0"
850 /* 1257 */ "V18\0"
851 /* 1261 */ "SW18\0"
852 /* 1266 */ "SX18\0"
853 /* 1271 */ "SF28\0"
854 /* 1276 */ "Q28\0"
855 /* 1280 */ "V28\0"
856 /* 1284 */ "SW28\0"
857 /* 1289 */ "SX28\0"
858 /* 1294 */ "SF38\0"
859 /* 1299 */ "V38\0"
860 /* 1303 */ "SW38\0"
861 /* 1308 */ "SX38\0"
862 /* 1313 */ "SF48\0"
863 /* 1318 */ "V48\0"
864 /* 1322 */ "SW48\0"
865 /* 1327 */ "SX48\0"
866 /* 1332 */ "SF58\0"
867 /* 1337 */ "V58\0"
868 /* 1341 */ "SW58\0"
869 /* 1346 */ "SX58\0"
870 /* 1351 */ "PMC8\0"
871 /* 1356 */ "SF8\0"
872 /* 1360 */ "VM8\0"
873 /* 1364 */ "Q8\0"
874 /* 1367 */ "V8\0"
875 /* 1370 */ "SW8\0"
876 /* 1374 */ "SX8\0"
877 /* 1378 */ "SF19\0"
878 /* 1383 */ "Q19\0"
879 /* 1387 */ "V19\0"
880 /* 1391 */ "SW19\0"
881 /* 1396 */ "SX19\0"
882 /* 1401 */ "SF29\0"
883 /* 1406 */ "Q29\0"
884 /* 1410 */ "V29\0"
885 /* 1414 */ "SW29\0"
886 /* 1419 */ "SX29\0"
887 /* 1424 */ "SF39\0"
888 /* 1429 */ "V39\0"
889 /* 1433 */ "SW39\0"
890 /* 1438 */ "SX39\0"
891 /* 1443 */ "SF49\0"
892 /* 1448 */ "V49\0"
893 /* 1452 */ "SW49\0"
894 /* 1457 */ "SX49\0"
895 /* 1462 */ "SF59\0"
896 /* 1467 */ "V59\0"
897 /* 1471 */ "SW59\0"
898 /* 1476 */ "SX59\0"
899 /* 1481 */ "PMC9\0"
900 /* 1486 */ "SF9\0"
901 /* 1490 */ "VM9\0"
902 /* 1494 */ "Q9\0"
903 /* 1497 */ "V9\0"
904 /* 1500 */ "SW9\0"
905 /* 1504 */ "SX9\0"
906 /* 1508 */ "USRCC\0"
907 /* 1514 */ "IC\0"
908 /* 1517 */ "VL\0"
909 /* 1520 */ "SAR\0"
910 /* 1524 */ "PMMR\0"
911 /* 1529 */ "PSW\0"
912 /* 1533 */ "VIX\0"
913};
914#ifdef __GNUC__
915#pragma GCC diagnostic pop
916#endif
917
918extern const MCRegisterDesc VERegDesc[] = { // Descriptors
919 { 5, 0, 0, 0, 0, 0, 0 },
920 { 1514, 2, 2, 2, 8192, 6, 0 },
921 { 1524, 2, 2, 2, 8193, 6, 0 },
922 { 1529, 2, 2, 2, 8194, 6, 0 },
923 { 1520, 2, 2, 2, 8195, 6, 0 },
924 { 1508, 2, 2, 2, 8196, 6, 0 },
925 { 1533, 2, 2, 2, 8197, 6, 0 },
926 { 1517, 2, 2, 2, 8198, 6, 0 },
927 { 137, 2, 2, 2, 8199, 6, 0 },
928 { 312, 2, 2, 2, 8200, 6, 0 },
929 { 483, 2, 2, 2, 8201, 6, 0 },
930 { 654, 2, 2, 2, 8202, 6, 0 },
931 { 806, 2, 2, 2, 8203, 6, 0 },
932 { 946, 2, 2, 2, 8204, 6, 0 },
933 { 1081, 2, 2, 2, 8205, 6, 0 },
934 { 1216, 2, 2, 2, 8206, 6, 0 },
935 { 1351, 2, 2, 2, 8207, 6, 0 },
936 { 1481, 2, 2, 2, 8208, 6, 0 },
937 { 0, 2, 2, 2, 8209, 6, 0 },
938 { 175, 2, 2, 2, 8210, 6, 0 },
939 { 350, 2, 2, 2, 8211, 6, 0 },
940 { 521, 2, 2, 2, 8212, 6, 0 },
941 { 692, 2, 2, 2, 8213, 6, 0 },
942 { 158, 2, 2, 2, 8214, 6, 0 },
943 { 333, 2, 2, 2, 8215, 6, 0 },
944 { 504, 2, 2, 2, 8216, 6, 0 },
945 { 675, 2, 2, 2, 8217, 6, 0 },
946 { 155, 198, 2, 6, 1732634, 0, 0 },
947 { 330, 205, 2, 6, 1732636, 0, 0 },
948 { 501, 212, 2, 6, 1732638, 0, 0 },
949 { 672, 219, 2, 6, 1732640, 0, 0 },
950 { 824, 226, 2, 6, 1732642, 0, 0 },
951 { 964, 233, 2, 6, 1732644, 0, 0 },
952 { 1099, 240, 2, 6, 1732646, 0, 0 },
953 { 1234, 247, 2, 6, 1732648, 0, 0 },
954 { 1364, 254, 2, 6, 1732650, 0, 0 },
955 { 1494, 261, 2, 6, 1732652, 0, 0 },
956 { 16, 268, 2, 6, 1732654, 0, 0 },
957 { 191, 275, 2, 6, 1732656, 0, 0 },
958 { 366, 282, 2, 6, 1732658, 0, 0 },
959 { 537, 289, 2, 6, 1732660, 0, 0 },
960 { 708, 296, 2, 6, 1732662, 0, 0 },
961 { 848, 303, 2, 6, 1732664, 0, 0 },
962 { 983, 310, 2, 6, 1732666, 0, 0 },
963 { 1118, 317, 2, 6, 1732668, 0, 0 },
964 { 1253, 324, 2, 6, 1732670, 0, 0 },
965 { 1383, 331, 2, 6, 1732672, 0, 0 },
966 { 39, 338, 2, 6, 1732674, 0, 0 },
967 { 214, 345, 2, 6, 1732676, 0, 0 },
968 { 389, 352, 2, 6, 1732678, 0, 0 },
969 { 560, 359, 2, 6, 1732680, 0, 0 },
970 { 731, 366, 2, 6, 1732682, 0, 0 },
971 { 871, 373, 2, 6, 1732684, 0, 0 },
972 { 1006, 380, 2, 6, 1732686, 0, 0 },
973 { 1141, 387, 2, 6, 1732688, 0, 0 },
974 { 1276, 394, 2, 6, 1732690, 0, 0 },
975 { 1406, 401, 2, 6, 1732692, 0, 0 },
976 { 62, 408, 2, 6, 1732694, 0, 0 },
977 { 237, 415, 2, 6, 1732696, 0, 0 },
978 { 142, 2, 195, 2, 8218, 6, 0 },
979 { 317, 2, 189, 2, 8219, 6, 0 },
980 { 488, 2, 189, 2, 8220, 6, 0 },
981 { 659, 2, 183, 2, 8221, 6, 0 },
982 { 811, 2, 183, 2, 8222, 6, 0 },
983 { 951, 2, 177, 2, 8223, 6, 0 },
984 { 1086, 2, 177, 2, 8224, 6, 0 },
985 { 1221, 2, 171, 2, 8225, 6, 0 },
986 { 1356, 2, 171, 2, 8226, 6, 0 },
987 { 1486, 2, 165, 2, 8227, 6, 0 },
988 { 6, 2, 165, 2, 8228, 6, 0 },
989 { 181, 2, 159, 2, 8229, 6, 0 },
990 { 356, 2, 159, 2, 8230, 6, 0 },
991 { 527, 2, 153, 2, 8231, 6, 0 },
992 { 698, 2, 153, 2, 8232, 6, 0 },
993 { 838, 2, 147, 2, 8233, 6, 0 },
994 { 978, 2, 147, 2, 8234, 6, 0 },
995 { 1113, 2, 141, 2, 8235, 6, 0 },
996 { 1248, 2, 141, 2, 8236, 6, 0 },
997 { 1378, 2, 135, 2, 8237, 6, 0 },
998 { 34, 2, 135, 2, 8238, 6, 0 },
999 { 209, 2, 129, 2, 8239, 6, 0 },
1000 { 384, 2, 129, 2, 8240, 6, 0 },
1001 { 555, 2, 123, 2, 8241, 6, 0 },
1002 { 726, 2, 123, 2, 8242, 6, 0 },
1003 { 866, 2, 117, 2, 8243, 6, 0 },
1004 { 1001, 2, 117, 2, 8244, 6, 0 },
1005 { 1136, 2, 111, 2, 8245, 6, 0 },
1006 { 1271, 2, 111, 2, 8246, 6, 0 },
1007 { 1401, 2, 105, 2, 8247, 6, 0 },
1008 { 57, 2, 105, 2, 8248, 6, 0 },
1009 { 232, 2, 99, 2, 8249, 6, 0 },
1010 { 407, 2, 99, 2, 8250, 6, 0 },
1011 { 578, 2, 93, 2, 8251, 6, 0 },
1012 { 749, 2, 93, 2, 8252, 6, 0 },
1013 { 889, 2, 87, 2, 8253, 6, 0 },
1014 { 1024, 2, 87, 2, 8254, 6, 0 },
1015 { 1159, 2, 81, 2, 8255, 6, 0 },
1016 { 1294, 2, 81, 2, 8256, 6, 0 },
1017 { 1424, 2, 75, 2, 8257, 6, 0 },
1018 { 80, 2, 75, 2, 8258, 6, 0 },
1019 { 255, 2, 69, 2, 8259, 6, 0 },
1020 { 426, 2, 69, 2, 8260, 6, 0 },
1021 { 597, 2, 63, 2, 8261, 6, 0 },
1022 { 768, 2, 63, 2, 8262, 6, 0 },
1023 { 908, 2, 57, 2, 8263, 6, 0 },
1024 { 1043, 2, 57, 2, 8264, 6, 0 },
1025 { 1178, 2, 51, 2, 8265, 6, 0 },
1026 { 1313, 2, 51, 2, 8266, 6, 0 },
1027 { 1443, 2, 45, 2, 8267, 6, 0 },
1028 { 99, 2, 45, 2, 8268, 6, 0 },
1029 { 274, 2, 39, 2, 8269, 6, 0 },
1030 { 445, 2, 39, 2, 8270, 6, 0 },
1031 { 616, 2, 33, 2, 8271, 6, 0 },
1032 { 787, 2, 33, 2, 8272, 6, 0 },
1033 { 927, 2, 27, 2, 8273, 6, 0 },
1034 { 1062, 2, 27, 2, 8274, 6, 0 },
1035 { 1197, 2, 21, 2, 8275, 6, 0 },
1036 { 1332, 2, 21, 2, 8276, 6, 0 },
1037 { 1462, 2, 15, 2, 8277, 6, 0 },
1038 { 118, 2, 15, 2, 8278, 6, 0 },
1039 { 293, 2, 9, 2, 8279, 6, 0 },
1040 { 464, 2, 9, 2, 8280, 6, 0 },
1041 { 635, 2, 3, 2, 8281, 6, 0 },
1042 { 167, 2, 192, 2, 8218, 6, 0 },
1043 { 342, 2, 186, 2, 8219, 6, 0 },
1044 { 513, 2, 186, 2, 8220, 6, 0 },
1045 { 684, 2, 180, 2, 8221, 6, 0 },
1046 { 830, 2, 180, 2, 8222, 6, 0 },
1047 { 970, 2, 174, 2, 8223, 6, 0 },
1048 { 1105, 2, 174, 2, 8224, 6, 0 },
1049 { 1240, 2, 168, 2, 8225, 6, 0 },
1050 { 1370, 2, 168, 2, 8226, 6, 0 },
1051 { 1500, 2, 162, 2, 8227, 6, 0 },
1052 { 24, 2, 162, 2, 8228, 6, 0 },
1053 { 199, 2, 156, 2, 8229, 6, 0 },
1054 { 374, 2, 156, 2, 8230, 6, 0 },
1055 { 545, 2, 150, 2, 8231, 6, 0 },
1056 { 716, 2, 150, 2, 8232, 6, 0 },
1057 { 856, 2, 144, 2, 8233, 6, 0 },
1058 { 991, 2, 144, 2, 8234, 6, 0 },
1059 { 1126, 2, 138, 2, 8235, 6, 0 },
1060 { 1261, 2, 138, 2, 8236, 6, 0 },
1061 { 1391, 2, 132, 2, 8237, 6, 0 },
1062 { 47, 2, 132, 2, 8238, 6, 0 },
1063 { 222, 2, 126, 2, 8239, 6, 0 },
1064 { 397, 2, 126, 2, 8240, 6, 0 },
1065 { 568, 2, 120, 2, 8241, 6, 0 },
1066 { 739, 2, 120, 2, 8242, 6, 0 },
1067 { 879, 2, 114, 2, 8243, 6, 0 },
1068 { 1014, 2, 114, 2, 8244, 6, 0 },
1069 { 1149, 2, 108, 2, 8245, 6, 0 },
1070 { 1284, 2, 108, 2, 8246, 6, 0 },
1071 { 1414, 2, 102, 2, 8247, 6, 0 },
1072 { 70, 2, 102, 2, 8248, 6, 0 },
1073 { 245, 2, 96, 2, 8249, 6, 0 },
1074 { 416, 2, 96, 2, 8250, 6, 0 },
1075 { 587, 2, 90, 2, 8251, 6, 0 },
1076 { 758, 2, 90, 2, 8252, 6, 0 },
1077 { 898, 2, 84, 2, 8253, 6, 0 },
1078 { 1033, 2, 84, 2, 8254, 6, 0 },
1079 { 1168, 2, 78, 2, 8255, 6, 0 },
1080 { 1303, 2, 78, 2, 8256, 6, 0 },
1081 { 1433, 2, 72, 2, 8257, 6, 0 },
1082 { 89, 2, 72, 2, 8258, 6, 0 },
1083 { 264, 2, 66, 2, 8259, 6, 0 },
1084 { 435, 2, 66, 2, 8260, 6, 0 },
1085 { 606, 2, 60, 2, 8261, 6, 0 },
1086 { 777, 2, 60, 2, 8262, 6, 0 },
1087 { 917, 2, 54, 2, 8263, 6, 0 },
1088 { 1052, 2, 54, 2, 8264, 6, 0 },
1089 { 1187, 2, 48, 2, 8265, 6, 0 },
1090 { 1322, 2, 48, 2, 8266, 6, 0 },
1091 { 1452, 2, 42, 2, 8267, 6, 0 },
1092 { 108, 2, 42, 2, 8268, 6, 0 },
1093 { 283, 2, 36, 2, 8269, 6, 0 },
1094 { 454, 2, 36, 2, 8270, 6, 0 },
1095 { 625, 2, 30, 2, 8271, 6, 0 },
1096 { 796, 2, 30, 2, 8272, 6, 0 },
1097 { 936, 2, 24, 2, 8273, 6, 0 },
1098 { 1071, 2, 24, 2, 8274, 6, 0 },
1099 { 1206, 2, 18, 2, 8275, 6, 0 },
1100 { 1341, 2, 18, 2, 8276, 6, 0 },
1101 { 1471, 2, 12, 2, 8277, 6, 0 },
1102 { 127, 2, 12, 2, 8278, 6, 0 },
1103 { 302, 2, 6, 2, 8279, 6, 0 },
1104 { 473, 2, 6, 2, 8280, 6, 0 },
1105 { 644, 2, 0, 2, 8281, 6, 0 },
1106 { 171, 202, 193, 0, 8218, 1, 0 },
1107 { 346, 202, 187, 0, 8219, 1, 0 },
1108 { 517, 202, 187, 0, 8220, 1, 0 },
1109 { 688, 202, 181, 0, 8221, 1, 0 },
1110 { 834, 202, 181, 0, 8222, 1, 0 },
1111 { 974, 202, 175, 0, 8223, 1, 0 },
1112 { 1109, 202, 175, 0, 8224, 1, 0 },
1113 { 1244, 202, 169, 0, 8225, 1, 0 },
1114 { 1374, 202, 169, 0, 8226, 1, 0 },
1115 { 1504, 202, 163, 0, 8227, 1, 0 },
1116 { 29, 202, 163, 0, 8228, 1, 0 },
1117 { 204, 202, 157, 0, 8229, 1, 0 },
1118 { 379, 202, 157, 0, 8230, 1, 0 },
1119 { 550, 202, 151, 0, 8231, 1, 0 },
1120 { 721, 202, 151, 0, 8232, 1, 0 },
1121 { 861, 202, 145, 0, 8233, 1, 0 },
1122 { 996, 202, 145, 0, 8234, 1, 0 },
1123 { 1131, 202, 139, 0, 8235, 1, 0 },
1124 { 1266, 202, 139, 0, 8236, 1, 0 },
1125 { 1396, 202, 133, 0, 8237, 1, 0 },
1126 { 52, 202, 133, 0, 8238, 1, 0 },
1127 { 227, 202, 127, 0, 8239, 1, 0 },
1128 { 402, 202, 127, 0, 8240, 1, 0 },
1129 { 573, 202, 121, 0, 8241, 1, 0 },
1130 { 744, 202, 121, 0, 8242, 1, 0 },
1131 { 884, 202, 115, 0, 8243, 1, 0 },
1132 { 1019, 202, 115, 0, 8244, 1, 0 },
1133 { 1154, 202, 109, 0, 8245, 1, 0 },
1134 { 1289, 202, 109, 0, 8246, 1, 0 },
1135 { 1419, 202, 103, 0, 8247, 1, 0 },
1136 { 75, 202, 103, 0, 8248, 1, 0 },
1137 { 250, 202, 97, 0, 8249, 1, 0 },
1138 { 421, 202, 97, 0, 8250, 1, 0 },
1139 { 592, 202, 91, 0, 8251, 1, 0 },
1140 { 763, 202, 91, 0, 8252, 1, 0 },
1141 { 903, 202, 85, 0, 8253, 1, 0 },
1142 { 1038, 202, 85, 0, 8254, 1, 0 },
1143 { 1173, 202, 79, 0, 8255, 1, 0 },
1144 { 1308, 202, 79, 0, 8256, 1, 0 },
1145 { 1438, 202, 73, 0, 8257, 1, 0 },
1146 { 94, 202, 73, 0, 8258, 1, 0 },
1147 { 269, 202, 67, 0, 8259, 1, 0 },
1148 { 440, 202, 67, 0, 8260, 1, 0 },
1149 { 611, 202, 61, 0, 8261, 1, 0 },
1150 { 782, 202, 61, 0, 8262, 1, 0 },
1151 { 922, 202, 55, 0, 8263, 1, 0 },
1152 { 1057, 202, 55, 0, 8264, 1, 0 },
1153 { 1192, 202, 49, 0, 8265, 1, 0 },
1154 { 1327, 202, 49, 0, 8266, 1, 0 },
1155 { 1457, 202, 43, 0, 8267, 1, 0 },
1156 { 113, 202, 43, 0, 8268, 1, 0 },
1157 { 288, 202, 37, 0, 8269, 1, 0 },
1158 { 459, 202, 37, 0, 8270, 1, 0 },
1159 { 630, 202, 31, 0, 8271, 1, 0 },
1160 { 801, 202, 31, 0, 8272, 1, 0 },
1161 { 941, 202, 25, 0, 8273, 1, 0 },
1162 { 1076, 202, 25, 0, 8274, 1, 0 },
1163 { 1211, 202, 19, 0, 8275, 1, 0 },
1164 { 1346, 202, 19, 0, 8276, 1, 0 },
1165 { 1476, 202, 13, 0, 8277, 1, 0 },
1166 { 132, 202, 13, 0, 8278, 1, 0 },
1167 { 307, 202, 7, 0, 8279, 1, 0 },
1168 { 478, 202, 7, 0, 8280, 1, 0 },
1169 { 649, 202, 1, 0, 8281, 1, 0 },
1170 { 164, 2, 2, 2, 8282, 6, 0 },
1171 { 339, 2, 2, 2, 8283, 6, 0 },
1172 { 510, 2, 2, 2, 8284, 6, 0 },
1173 { 681, 2, 2, 2, 8285, 6, 0 },
1174 { 827, 2, 2, 2, 8286, 6, 0 },
1175 { 967, 2, 2, 2, 8287, 6, 0 },
1176 { 1102, 2, 2, 2, 8288, 6, 0 },
1177 { 1237, 2, 2, 2, 8289, 6, 0 },
1178 { 1367, 2, 2, 2, 8290, 6, 0 },
1179 { 1497, 2, 2, 2, 8291, 6, 0 },
1180 { 20, 2, 2, 2, 8292, 6, 0 },
1181 { 195, 2, 2, 2, 8293, 6, 0 },
1182 { 370, 2, 2, 2, 8294, 6, 0 },
1183 { 541, 2, 2, 2, 8295, 6, 0 },
1184 { 712, 2, 2, 2, 8296, 6, 0 },
1185 { 852, 2, 2, 2, 8297, 6, 0 },
1186 { 987, 2, 2, 2, 8298, 6, 0 },
1187 { 1122, 2, 2, 2, 8299, 6, 0 },
1188 { 1257, 2, 2, 2, 8300, 6, 0 },
1189 { 1387, 2, 2, 2, 8301, 6, 0 },
1190 { 43, 2, 2, 2, 8302, 6, 0 },
1191 { 218, 2, 2, 2, 8303, 6, 0 },
1192 { 393, 2, 2, 2, 8304, 6, 0 },
1193 { 564, 2, 2, 2, 8305, 6, 0 },
1194 { 735, 2, 2, 2, 8306, 6, 0 },
1195 { 875, 2, 2, 2, 8307, 6, 0 },
1196 { 1010, 2, 2, 2, 8308, 6, 0 },
1197 { 1145, 2, 2, 2, 8309, 6, 0 },
1198 { 1280, 2, 2, 2, 8310, 6, 0 },
1199 { 1410, 2, 2, 2, 8311, 6, 0 },
1200 { 66, 2, 2, 2, 8312, 6, 0 },
1201 { 241, 2, 2, 2, 8313, 6, 0 },
1202 { 412, 2, 2, 2, 8314, 6, 0 },
1203 { 583, 2, 2, 2, 8315, 6, 0 },
1204 { 754, 2, 2, 2, 8316, 6, 0 },
1205 { 894, 2, 2, 2, 8317, 6, 0 },
1206 { 1029, 2, 2, 2, 8318, 6, 0 },
1207 { 1164, 2, 2, 2, 8319, 6, 0 },
1208 { 1299, 2, 2, 2, 8320, 6, 0 },
1209 { 1429, 2, 2, 2, 8321, 6, 0 },
1210 { 85, 2, 2, 2, 8322, 6, 0 },
1211 { 260, 2, 2, 2, 8323, 6, 0 },
1212 { 431, 2, 2, 2, 8324, 6, 0 },
1213 { 602, 2, 2, 2, 8325, 6, 0 },
1214 { 773, 2, 2, 2, 8326, 6, 0 },
1215 { 913, 2, 2, 2, 8327, 6, 0 },
1216 { 1048, 2, 2, 2, 8328, 6, 0 },
1217 { 1183, 2, 2, 2, 8329, 6, 0 },
1218 { 1318, 2, 2, 2, 8330, 6, 0 },
1219 { 1448, 2, 2, 2, 8331, 6, 0 },
1220 { 104, 2, 2, 2, 8332, 6, 0 },
1221 { 279, 2, 2, 2, 8333, 6, 0 },
1222 { 450, 2, 2, 2, 8334, 6, 0 },
1223 { 621, 2, 2, 2, 8335, 6, 0 },
1224 { 792, 2, 2, 2, 8336, 6, 0 },
1225 { 932, 2, 2, 2, 8337, 6, 0 },
1226 { 1067, 2, 2, 2, 8338, 6, 0 },
1227 { 1202, 2, 2, 2, 8339, 6, 0 },
1228 { 1337, 2, 2, 2, 8340, 6, 0 },
1229 { 1467, 2, 2, 2, 8341, 6, 0 },
1230 { 123, 2, 2, 2, 8342, 6, 0 },
1231 { 298, 2, 2, 2, 8343, 6, 0 },
1232 { 469, 2, 2, 2, 8344, 6, 0 },
1233 { 640, 2, 2, 2, 8345, 6, 0 },
1234 { 146, 2, 2, 2, 8346, 6, 1 },
1235 { 321, 2, 2, 2, 8347, 6, 0 },
1236 { 492, 2, 457, 2, 8348, 6, 0 },
1237 { 663, 2, 455, 2, 8349, 6, 0 },
1238 { 815, 2, 455, 2, 8350, 6, 0 },
1239 { 955, 2, 453, 2, 8351, 6, 0 },
1240 { 1090, 2, 453, 2, 8352, 6, 0 },
1241 { 1225, 2, 451, 2, 8353, 6, 0 },
1242 { 1360, 2, 451, 2, 8354, 6, 0 },
1243 { 1490, 2, 449, 2, 8355, 6, 0 },
1244 { 11, 2, 449, 2, 8356, 6, 0 },
1245 { 186, 2, 447, 2, 8357, 6, 0 },
1246 { 361, 2, 447, 2, 8358, 6, 0 },
1247 { 532, 2, 445, 2, 8359, 6, 0 },
1248 { 703, 2, 445, 2, 8360, 6, 0 },
1249 { 843, 2, 443, 2, 8361, 6, 0 },
1250 { 150, 2, 2, 2, 8362, 6, 1 },
1251 { 325, 422, 2, 3, 1732764, 3, 0 },
1252 { 496, 425, 2, 3, 1732766, 3, 0 },
1253 { 667, 428, 2, 3, 1732768, 3, 0 },
1254 { 819, 431, 2, 3, 1732770, 3, 0 },
1255 { 959, 434, 2, 3, 1732772, 3, 0 },
1256 { 1094, 437, 2, 3, 1732774, 3, 0 },
1257 { 1229, 440, 2, 3, 1732776, 3, 0 },
1258};
1259
1260extern const MCPhysReg VERegUnitRoots[][2] = {
1261 { VE::IC },
1262 { VE::PMMR },
1263 { VE::PSW },
1264 { VE::SAR },
1265 { VE::USRCC },
1266 { VE::VIX },
1267 { VE::VL },
1268 { VE::PMC0 },
1269 { VE::PMC1 },
1270 { VE::PMC2 },
1271 { VE::PMC3 },
1272 { VE::PMC4 },
1273 { VE::PMC5 },
1274 { VE::PMC6 },
1275 { VE::PMC7 },
1276 { VE::PMC8 },
1277 { VE::PMC9 },
1278 { VE::PMC10 },
1279 { VE::PMC11 },
1280 { VE::PMC12 },
1281 { VE::PMC13 },
1282 { VE::PMC14 },
1283 { VE::PMCR0 },
1284 { VE::PMCR1 },
1285 { VE::PMCR2 },
1286 { VE::PMCR3 },
1287 { VE::SW0, VE::SF0 },
1288 { VE::SW1, VE::SF1 },
1289 { VE::SW2, VE::SF2 },
1290 { VE::SW3, VE::SF3 },
1291 { VE::SW4, VE::SF4 },
1292 { VE::SW5, VE::SF5 },
1293 { VE::SW6, VE::SF6 },
1294 { VE::SW7, VE::SF7 },
1295 { VE::SW8, VE::SF8 },
1296 { VE::SW9, VE::SF9 },
1297 { VE::SW10, VE::SF10 },
1298 { VE::SW11, VE::SF11 },
1299 { VE::SW12, VE::SF12 },
1300 { VE::SW13, VE::SF13 },
1301 { VE::SW14, VE::SF14 },
1302 { VE::SW15, VE::SF15 },
1303 { VE::SW16, VE::SF16 },
1304 { VE::SW17, VE::SF17 },
1305 { VE::SW18, VE::SF18 },
1306 { VE::SW19, VE::SF19 },
1307 { VE::SW20, VE::SF20 },
1308 { VE::SW21, VE::SF21 },
1309 { VE::SW22, VE::SF22 },
1310 { VE::SW23, VE::SF23 },
1311 { VE::SW24, VE::SF24 },
1312 { VE::SW25, VE::SF25 },
1313 { VE::SW26, VE::SF26 },
1314 { VE::SW27, VE::SF27 },
1315 { VE::SW28, VE::SF28 },
1316 { VE::SW29, VE::SF29 },
1317 { VE::SW30, VE::SF30 },
1318 { VE::SW31, VE::SF31 },
1319 { VE::SW32, VE::SF32 },
1320 { VE::SW33, VE::SF33 },
1321 { VE::SW34, VE::SF34 },
1322 { VE::SW35, VE::SF35 },
1323 { VE::SW36, VE::SF36 },
1324 { VE::SW37, VE::SF37 },
1325 { VE::SW38, VE::SF38 },
1326 { VE::SW39, VE::SF39 },
1327 { VE::SW40, VE::SF40 },
1328 { VE::SW41, VE::SF41 },
1329 { VE::SW42, VE::SF42 },
1330 { VE::SW43, VE::SF43 },
1331 { VE::SW44, VE::SF44 },
1332 { VE::SW45, VE::SF45 },
1333 { VE::SW46, VE::SF46 },
1334 { VE::SW47, VE::SF47 },
1335 { VE::SW48, VE::SF48 },
1336 { VE::SW49, VE::SF49 },
1337 { VE::SW50, VE::SF50 },
1338 { VE::SW51, VE::SF51 },
1339 { VE::SW52, VE::SF52 },
1340 { VE::SW53, VE::SF53 },
1341 { VE::SW54, VE::SF54 },
1342 { VE::SW55, VE::SF55 },
1343 { VE::SW56, VE::SF56 },
1344 { VE::SW57, VE::SF57 },
1345 { VE::SW58, VE::SF58 },
1346 { VE::SW59, VE::SF59 },
1347 { VE::SW60, VE::SF60 },
1348 { VE::SW61, VE::SF61 },
1349 { VE::SW62, VE::SF62 },
1350 { VE::SW63, VE::SF63 },
1351 { VE::V0 },
1352 { VE::V1 },
1353 { VE::V2 },
1354 { VE::V3 },
1355 { VE::V4 },
1356 { VE::V5 },
1357 { VE::V6 },
1358 { VE::V7 },
1359 { VE::V8 },
1360 { VE::V9 },
1361 { VE::V10 },
1362 { VE::V11 },
1363 { VE::V12 },
1364 { VE::V13 },
1365 { VE::V14 },
1366 { VE::V15 },
1367 { VE::V16 },
1368 { VE::V17 },
1369 { VE::V18 },
1370 { VE::V19 },
1371 { VE::V20 },
1372 { VE::V21 },
1373 { VE::V22 },
1374 { VE::V23 },
1375 { VE::V24 },
1376 { VE::V25 },
1377 { VE::V26 },
1378 { VE::V27 },
1379 { VE::V28 },
1380 { VE::V29 },
1381 { VE::V30 },
1382 { VE::V31 },
1383 { VE::V32 },
1384 { VE::V33 },
1385 { VE::V34 },
1386 { VE::V35 },
1387 { VE::V36 },
1388 { VE::V37 },
1389 { VE::V38 },
1390 { VE::V39 },
1391 { VE::V40 },
1392 { VE::V41 },
1393 { VE::V42 },
1394 { VE::V43 },
1395 { VE::V44 },
1396 { VE::V45 },
1397 { VE::V46 },
1398 { VE::V47 },
1399 { VE::V48 },
1400 { VE::V49 },
1401 { VE::V50 },
1402 { VE::V51 },
1403 { VE::V52 },
1404 { VE::V53 },
1405 { VE::V54 },
1406 { VE::V55 },
1407 { VE::V56 },
1408 { VE::V57 },
1409 { VE::V58 },
1410 { VE::V59 },
1411 { VE::V60 },
1412 { VE::V61 },
1413 { VE::V62 },
1414 { VE::V63 },
1415 { VE::VM0 },
1416 { VE::VM1 },
1417 { VE::VM2 },
1418 { VE::VM3 },
1419 { VE::VM4 },
1420 { VE::VM5 },
1421 { VE::VM6 },
1422 { VE::VM7 },
1423 { VE::VM8 },
1424 { VE::VM9 },
1425 { VE::VM10 },
1426 { VE::VM11 },
1427 { VE::VM12 },
1428 { VE::VM13 },
1429 { VE::VM14 },
1430 { VE::VM15 },
1431 { VE::VMP0 },
1432};
1433
1434namespace { // Register classes...
1435 // F32 Register Class...
1436 const MCPhysReg F32[] = {
1437 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6, VE::SF7, VE::SF34, VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41, VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48, VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55, VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62, VE::SF63, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13, VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20, VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27, VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33,
1438 };
1439
1440 // F32 Bit set.
1441 const uint8_t F32Bits[] = {
1442 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07,
1443 };
1444
1445 // I32 Register Class...
1446 const MCPhysReg I32[] = {
1447 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6, VE::SW7, VE::SW34, VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41, VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48, VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55, VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62, VE::SW63, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13, VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20, VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27, VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33,
1448 };
1449
1450 // I32 Bit set.
1451 const uint8_t I32Bits[] = {
1452 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07,
1453 };
1454
1455 // VLS Register Class...
1456 const MCPhysReg VLS[] = {
1457 VE::VL,
1458 };
1459
1460 // VLS Bit set.
1461 const uint8_t VLSBits[] = {
1462 0x80,
1463 };
1464
1465 // I64 Register Class...
1466 const MCPhysReg I64[] = {
1467 VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7, VE::SX34, VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62, VE::SX63, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33,
1468 };
1469
1470 // I64 Bit set.
1471 const uint8_t I64Bits[] = {
1472 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07,
1473 };
1474
1475 // MISC Register Class...
1476 const MCPhysReg MISC[] = {
1477 VE::USRCC, VE::PSW, VE::SAR, VE::PMMR, VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3, VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3, VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7, VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11, VE::PMC12, VE::PMC13, VE::PMC14,
1478 };
1479
1480 // MISC Bit set.
1481 const uint8_t MISCBits[] = {
1482 0x3c, 0xff, 0xff, 0x07,
1483 };
1484
1485 // F128 Register Class...
1486 const MCPhysReg F128[] = {
1487 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23, VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31, VE::Q4, VE::Q5, VE::Q6, VE::Q7, VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15, VE::Q16,
1488 };
1489
1490 // F128 Bit set.
1491 const uint8_t F128Bits[] = {
1492 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1493 };
1494
1495 // VM Register Class...
1496 const MCPhysReg VM[] = {
1497 VE::VM0, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, VE::VM12, VE::VM13, VE::VM14, VE::VM15,
1498 };
1499
1500 // VM Bit set.
1501 const uint8_t VMBits[] = {
1502 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
1503 };
1504
1505 // VM512 Register Class...
1506 const MCPhysReg VM512[] = {
1507 VE::VMP0, VE::VMP1, VE::VMP2, VE::VMP3, VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7,
1508 };
1509
1510 // VM512 Bit set.
1511 const uint8_t VM512Bits[] = {
1512 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
1513 };
1514
1515 // VM512_with_sub_vm_even Register Class...
1516 const MCPhysReg VM512_with_sub_vm_even[] = {
1517 VE::VMP1, VE::VMP2, VE::VMP3, VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7,
1518 };
1519
1520 // VM512_with_sub_vm_even Bit set.
1521 const uint8_t VM512_with_sub_vm_evenBits[] = {
1522 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
1523 };
1524
1525 // V64 Register Class...
1526 const MCPhysReg V64[] = {
1527 VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63, VE::VIX,
1528 };
1529
1530 // V64 Bit set.
1531 const uint8_t V64Bits[] = {
1532 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x07,
1533 };
1534
1535} // end anonymous namespace
1536
1537
1538#ifdef __GNUC__
1539#pragma GCC diagnostic push
1540#pragma GCC diagnostic ignored "-Woverlength-strings"
1541#endif
1542extern const char VERegClassStrings[] = {
1543 /* 0 */ "VM512\0"
1544 /* 6 */ "F32\0"
1545 /* 10 */ "I32\0"
1546 /* 14 */ "I64\0"
1547 /* 18 */ "V64\0"
1548 /* 22 */ "F128\0"
1549 /* 27 */ "MISC\0"
1550 /* 32 */ "VM\0"
1551 /* 35 */ "VLS\0"
1552 /* 39 */ "VM512_with_sub_vm_even\0"
1553};
1554#ifdef __GNUC__
1555#pragma GCC diagnostic pop
1556#endif
1557
1558extern const MCRegisterClass VEMCRegisterClasses[] = {
1559 { F32, F32Bits, 6, 64, sizeof(F32Bits), VE::F32RegClassID, 32, 1, true, false },
1560 { I32, I32Bits, 10, 64, sizeof(I32Bits), VE::I32RegClassID, 32, 1, true, false },
1561 { VLS, VLSBits, 35, 1, sizeof(VLSBits), VE::VLSRegClassID, 32, 1, true, false },
1562 { I64, I64Bits, 14, 64, sizeof(I64Bits), VE::I64RegClassID, 64, 1, true, false },
1563 { MISC, MISCBits, 27, 23, sizeof(MISCBits), VE::MISCRegClassID, 64, 1, true, false },
1564 { F128, F128Bits, 22, 32, sizeof(F128Bits), VE::F128RegClassID, 128, 1, true, false },
1565 { VM, VMBits, 32, 16, sizeof(VMBits), VE::VMRegClassID, 256, 1, true, false },
1566 { VM512, VM512Bits, 0, 8, sizeof(VM512Bits), VE::VM512RegClassID, 512, 1, true, false },
1567 { VM512_with_sub_vm_even, VM512_with_sub_vm_evenBits, 39, 7, sizeof(VM512_with_sub_vm_evenBits), VE::VM512_with_sub_vm_evenRegClassID, 512, 1, true, false },
1568 { V64, V64Bits, 18, 65, sizeof(V64Bits), VE::V64RegClassID, 16384, 1, true, false },
1569};
1570
1571// VE Dwarf<->LLVM register mappings.
1572extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0Dwarf2L[] = {
1573 { 0U, VE::SX0 },
1574 { 1U, VE::SX1 },
1575 { 2U, VE::SX2 },
1576 { 3U, VE::SX3 },
1577 { 4U, VE::SX4 },
1578 { 5U, VE::SX5 },
1579 { 6U, VE::SX6 },
1580 { 7U, VE::SX7 },
1581 { 8U, VE::SX8 },
1582 { 9U, VE::SX9 },
1583 { 10U, VE::SX10 },
1584 { 11U, VE::SX11 },
1585 { 12U, VE::SX12 },
1586 { 13U, VE::SX13 },
1587 { 14U, VE::SX14 },
1588 { 15U, VE::SX15 },
1589 { 16U, VE::SX16 },
1590 { 17U, VE::SX17 },
1591 { 18U, VE::SX18 },
1592 { 19U, VE::SX19 },
1593 { 20U, VE::SX20 },
1594 { 21U, VE::SX21 },
1595 { 22U, VE::SX22 },
1596 { 23U, VE::SX23 },
1597 { 24U, VE::SX24 },
1598 { 25U, VE::SX25 },
1599 { 26U, VE::SX26 },
1600 { 27U, VE::SX27 },
1601 { 28U, VE::SX28 },
1602 { 29U, VE::SX29 },
1603 { 30U, VE::SX30 },
1604 { 31U, VE::SX31 },
1605 { 32U, VE::SX32 },
1606 { 33U, VE::SX33 },
1607 { 34U, VE::SX34 },
1608 { 35U, VE::SX35 },
1609 { 36U, VE::SX36 },
1610 { 37U, VE::SX37 },
1611 { 38U, VE::SX38 },
1612 { 39U, VE::SX39 },
1613 { 40U, VE::SX40 },
1614 { 41U, VE::SX41 },
1615 { 42U, VE::SX42 },
1616 { 43U, VE::SX43 },
1617 { 44U, VE::SX44 },
1618 { 45U, VE::SX45 },
1619 { 46U, VE::SX46 },
1620 { 47U, VE::SX47 },
1621 { 48U, VE::SX48 },
1622 { 49U, VE::SX49 },
1623 { 50U, VE::SX50 },
1624 { 51U, VE::SX51 },
1625 { 52U, VE::SX52 },
1626 { 53U, VE::SX53 },
1627 { 54U, VE::SX54 },
1628 { 55U, VE::SX55 },
1629 { 56U, VE::SX56 },
1630 { 57U, VE::SX57 },
1631 { 58U, VE::SX58 },
1632 { 59U, VE::SX59 },
1633 { 60U, VE::SX60 },
1634 { 61U, VE::SX61 },
1635 { 62U, VE::SX62 },
1636 { 63U, VE::SX63 },
1637 { 64U, VE::V0 },
1638 { 65U, VE::V1 },
1639 { 66U, VE::V2 },
1640 { 67U, VE::V3 },
1641 { 68U, VE::V4 },
1642 { 69U, VE::V5 },
1643 { 70U, VE::V6 },
1644 { 71U, VE::V7 },
1645 { 72U, VE::V8 },
1646 { 73U, VE::V9 },
1647 { 74U, VE::V10 },
1648 { 75U, VE::V11 },
1649 { 76U, VE::V12 },
1650 { 77U, VE::V13 },
1651 { 78U, VE::V14 },
1652 { 79U, VE::V15 },
1653 { 80U, VE::V16 },
1654 { 81U, VE::V17 },
1655 { 82U, VE::V18 },
1656 { 83U, VE::V19 },
1657 { 84U, VE::V20 },
1658 { 85U, VE::V21 },
1659 { 86U, VE::V22 },
1660 { 87U, VE::V23 },
1661 { 88U, VE::V24 },
1662 { 89U, VE::V25 },
1663 { 90U, VE::V26 },
1664 { 91U, VE::V27 },
1665 { 92U, VE::V28 },
1666 { 93U, VE::V29 },
1667 { 94U, VE::V30 },
1668 { 95U, VE::V31 },
1669 { 96U, VE::V32 },
1670 { 97U, VE::V33 },
1671 { 98U, VE::V34 },
1672 { 99U, VE::V35 },
1673 { 100U, VE::V36 },
1674 { 101U, VE::V37 },
1675 { 102U, VE::V38 },
1676 { 103U, VE::V39 },
1677 { 104U, VE::V40 },
1678 { 105U, VE::V41 },
1679 { 106U, VE::V42 },
1680 { 107U, VE::V43 },
1681 { 108U, VE::V44 },
1682 { 109U, VE::V45 },
1683 { 110U, VE::V46 },
1684 { 111U, VE::V47 },
1685 { 112U, VE::V48 },
1686 { 113U, VE::V49 },
1687 { 114U, VE::V50 },
1688 { 115U, VE::V51 },
1689 { 116U, VE::V52 },
1690 { 117U, VE::V53 },
1691 { 118U, VE::V54 },
1692 { 119U, VE::V55 },
1693 { 120U, VE::V56 },
1694 { 121U, VE::V57 },
1695 { 122U, VE::V58 },
1696 { 123U, VE::V59 },
1697 { 124U, VE::V60 },
1698 { 125U, VE::V61 },
1699 { 126U, VE::V62 },
1700 { 127U, VE::V63 },
1701 { 128U, VE::VM0 },
1702 { 129U, VE::VM1 },
1703 { 130U, VE::VM2 },
1704 { 131U, VE::VM3 },
1705 { 132U, VE::VM4 },
1706 { 133U, VE::VM5 },
1707 { 134U, VE::VM6 },
1708 { 135U, VE::VM7 },
1709 { 136U, VE::VM8 },
1710 { 137U, VE::VM9 },
1711 { 138U, VE::VM10 },
1712 { 139U, VE::VM11 },
1713 { 140U, VE::VM12 },
1714 { 141U, VE::VM13 },
1715 { 142U, VE::VM14 },
1716 { 143U, VE::VM15 },
1717};
1718extern const unsigned VEDwarfFlavour0Dwarf2LSize = std::size(VEDwarfFlavour0Dwarf2L);
1719
1720extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0Dwarf2L[] = {
1721 { 0U, VE::SX0 },
1722 { 1U, VE::SX1 },
1723 { 2U, VE::SX2 },
1724 { 3U, VE::SX3 },
1725 { 4U, VE::SX4 },
1726 { 5U, VE::SX5 },
1727 { 6U, VE::SX6 },
1728 { 7U, VE::SX7 },
1729 { 8U, VE::SX8 },
1730 { 9U, VE::SX9 },
1731 { 10U, VE::SX10 },
1732 { 11U, VE::SX11 },
1733 { 12U, VE::SX12 },
1734 { 13U, VE::SX13 },
1735 { 14U, VE::SX14 },
1736 { 15U, VE::SX15 },
1737 { 16U, VE::SX16 },
1738 { 17U, VE::SX17 },
1739 { 18U, VE::SX18 },
1740 { 19U, VE::SX19 },
1741 { 20U, VE::SX20 },
1742 { 21U, VE::SX21 },
1743 { 22U, VE::SX22 },
1744 { 23U, VE::SX23 },
1745 { 24U, VE::SX24 },
1746 { 25U, VE::SX25 },
1747 { 26U, VE::SX26 },
1748 { 27U, VE::SX27 },
1749 { 28U, VE::SX28 },
1750 { 29U, VE::SX29 },
1751 { 30U, VE::SX30 },
1752 { 31U, VE::SX31 },
1753 { 32U, VE::SX32 },
1754 { 33U, VE::SX33 },
1755 { 34U, VE::SX34 },
1756 { 35U, VE::SX35 },
1757 { 36U, VE::SX36 },
1758 { 37U, VE::SX37 },
1759 { 38U, VE::SX38 },
1760 { 39U, VE::SX39 },
1761 { 40U, VE::SX40 },
1762 { 41U, VE::SX41 },
1763 { 42U, VE::SX42 },
1764 { 43U, VE::SX43 },
1765 { 44U, VE::SX44 },
1766 { 45U, VE::SX45 },
1767 { 46U, VE::SX46 },
1768 { 47U, VE::SX47 },
1769 { 48U, VE::SX48 },
1770 { 49U, VE::SX49 },
1771 { 50U, VE::SX50 },
1772 { 51U, VE::SX51 },
1773 { 52U, VE::SX52 },
1774 { 53U, VE::SX53 },
1775 { 54U, VE::SX54 },
1776 { 55U, VE::SX55 },
1777 { 56U, VE::SX56 },
1778 { 57U, VE::SX57 },
1779 { 58U, VE::SX58 },
1780 { 59U, VE::SX59 },
1781 { 60U, VE::SX60 },
1782 { 61U, VE::SX61 },
1783 { 62U, VE::SX62 },
1784 { 63U, VE::SX63 },
1785 { 64U, VE::V0 },
1786 { 65U, VE::V1 },
1787 { 66U, VE::V2 },
1788 { 67U, VE::V3 },
1789 { 68U, VE::V4 },
1790 { 69U, VE::V5 },
1791 { 70U, VE::V6 },
1792 { 71U, VE::V7 },
1793 { 72U, VE::V8 },
1794 { 73U, VE::V9 },
1795 { 74U, VE::V10 },
1796 { 75U, VE::V11 },
1797 { 76U, VE::V12 },
1798 { 77U, VE::V13 },
1799 { 78U, VE::V14 },
1800 { 79U, VE::V15 },
1801 { 80U, VE::V16 },
1802 { 81U, VE::V17 },
1803 { 82U, VE::V18 },
1804 { 83U, VE::V19 },
1805 { 84U, VE::V20 },
1806 { 85U, VE::V21 },
1807 { 86U, VE::V22 },
1808 { 87U, VE::V23 },
1809 { 88U, VE::V24 },
1810 { 89U, VE::V25 },
1811 { 90U, VE::V26 },
1812 { 91U, VE::V27 },
1813 { 92U, VE::V28 },
1814 { 93U, VE::V29 },
1815 { 94U, VE::V30 },
1816 { 95U, VE::V31 },
1817 { 96U, VE::V32 },
1818 { 97U, VE::V33 },
1819 { 98U, VE::V34 },
1820 { 99U, VE::V35 },
1821 { 100U, VE::V36 },
1822 { 101U, VE::V37 },
1823 { 102U, VE::V38 },
1824 { 103U, VE::V39 },
1825 { 104U, VE::V40 },
1826 { 105U, VE::V41 },
1827 { 106U, VE::V42 },
1828 { 107U, VE::V43 },
1829 { 108U, VE::V44 },
1830 { 109U, VE::V45 },
1831 { 110U, VE::V46 },
1832 { 111U, VE::V47 },
1833 { 112U, VE::V48 },
1834 { 113U, VE::V49 },
1835 { 114U, VE::V50 },
1836 { 115U, VE::V51 },
1837 { 116U, VE::V52 },
1838 { 117U, VE::V53 },
1839 { 118U, VE::V54 },
1840 { 119U, VE::V55 },
1841 { 120U, VE::V56 },
1842 { 121U, VE::V57 },
1843 { 122U, VE::V58 },
1844 { 123U, VE::V59 },
1845 { 124U, VE::V60 },
1846 { 125U, VE::V61 },
1847 { 126U, VE::V62 },
1848 { 127U, VE::V63 },
1849 { 128U, VE::VM0 },
1850 { 129U, VE::VM1 },
1851 { 130U, VE::VM2 },
1852 { 131U, VE::VM3 },
1853 { 132U, VE::VM4 },
1854 { 133U, VE::VM5 },
1855 { 134U, VE::VM6 },
1856 { 135U, VE::VM7 },
1857 { 136U, VE::VM8 },
1858 { 137U, VE::VM9 },
1859 { 138U, VE::VM10 },
1860 { 139U, VE::VM11 },
1861 { 140U, VE::VM12 },
1862 { 141U, VE::VM13 },
1863 { 142U, VE::VM14 },
1864 { 143U, VE::VM15 },
1865};
1866extern const unsigned VEEHFlavour0Dwarf2LSize = std::size(VEEHFlavour0Dwarf2L);
1867
1868extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0L2Dwarf[] = {
1869 { VE::SF0, 0U },
1870 { VE::SF1, 1U },
1871 { VE::SF2, 2U },
1872 { VE::SF3, 3U },
1873 { VE::SF4, 4U },
1874 { VE::SF5, 5U },
1875 { VE::SF6, 6U },
1876 { VE::SF7, 7U },
1877 { VE::SF8, 8U },
1878 { VE::SF9, 9U },
1879 { VE::SF10, 10U },
1880 { VE::SF11, 11U },
1881 { VE::SF12, 12U },
1882 { VE::SF13, 13U },
1883 { VE::SF14, 14U },
1884 { VE::SF15, 15U },
1885 { VE::SF16, 16U },
1886 { VE::SF17, 17U },
1887 { VE::SF18, 18U },
1888 { VE::SF19, 19U },
1889 { VE::SF20, 20U },
1890 { VE::SF21, 21U },
1891 { VE::SF22, 22U },
1892 { VE::SF23, 23U },
1893 { VE::SF24, 24U },
1894 { VE::SF25, 25U },
1895 { VE::SF26, 26U },
1896 { VE::SF27, 27U },
1897 { VE::SF28, 28U },
1898 { VE::SF29, 29U },
1899 { VE::SF30, 30U },
1900 { VE::SF31, 31U },
1901 { VE::SF32, 32U },
1902 { VE::SF33, 33U },
1903 { VE::SF34, 34U },
1904 { VE::SF35, 35U },
1905 { VE::SF36, 36U },
1906 { VE::SF37, 37U },
1907 { VE::SF38, 38U },
1908 { VE::SF39, 39U },
1909 { VE::SF40, 40U },
1910 { VE::SF41, 41U },
1911 { VE::SF42, 42U },
1912 { VE::SF43, 43U },
1913 { VE::SF44, 44U },
1914 { VE::SF45, 45U },
1915 { VE::SF46, 46U },
1916 { VE::SF47, 47U },
1917 { VE::SF48, 48U },
1918 { VE::SF49, 49U },
1919 { VE::SF50, 50U },
1920 { VE::SF51, 51U },
1921 { VE::SF52, 52U },
1922 { VE::SF53, 53U },
1923 { VE::SF54, 54U },
1924 { VE::SF55, 55U },
1925 { VE::SF56, 56U },
1926 { VE::SF57, 57U },
1927 { VE::SF58, 58U },
1928 { VE::SF59, 59U },
1929 { VE::SF60, 60U },
1930 { VE::SF61, 61U },
1931 { VE::SF62, 62U },
1932 { VE::SF63, 63U },
1933 { VE::SW0, 0U },
1934 { VE::SW1, 1U },
1935 { VE::SW2, 2U },
1936 { VE::SW3, 3U },
1937 { VE::SW4, 4U },
1938 { VE::SW5, 5U },
1939 { VE::SW6, 6U },
1940 { VE::SW7, 7U },
1941 { VE::SW8, 8U },
1942 { VE::SW9, 9U },
1943 { VE::SW10, 10U },
1944 { VE::SW11, 11U },
1945 { VE::SW12, 12U },
1946 { VE::SW13, 13U },
1947 { VE::SW14, 14U },
1948 { VE::SW15, 15U },
1949 { VE::SW16, 16U },
1950 { VE::SW17, 17U },
1951 { VE::SW18, 18U },
1952 { VE::SW19, 19U },
1953 { VE::SW20, 20U },
1954 { VE::SW21, 21U },
1955 { VE::SW22, 22U },
1956 { VE::SW23, 23U },
1957 { VE::SW24, 24U },
1958 { VE::SW25, 25U },
1959 { VE::SW26, 26U },
1960 { VE::SW27, 27U },
1961 { VE::SW28, 28U },
1962 { VE::SW29, 29U },
1963 { VE::SW30, 30U },
1964 { VE::SW31, 31U },
1965 { VE::SW32, 32U },
1966 { VE::SW33, 33U },
1967 { VE::SW34, 34U },
1968 { VE::SW35, 35U },
1969 { VE::SW36, 36U },
1970 { VE::SW37, 37U },
1971 { VE::SW38, 38U },
1972 { VE::SW39, 39U },
1973 { VE::SW40, 40U },
1974 { VE::SW41, 41U },
1975 { VE::SW42, 42U },
1976 { VE::SW43, 43U },
1977 { VE::SW44, 44U },
1978 { VE::SW45, 45U },
1979 { VE::SW46, 46U },
1980 { VE::SW47, 47U },
1981 { VE::SW48, 48U },
1982 { VE::SW49, 49U },
1983 { VE::SW50, 50U },
1984 { VE::SW51, 51U },
1985 { VE::SW52, 52U },
1986 { VE::SW53, 53U },
1987 { VE::SW54, 54U },
1988 { VE::SW55, 55U },
1989 { VE::SW56, 56U },
1990 { VE::SW57, 57U },
1991 { VE::SW58, 58U },
1992 { VE::SW59, 59U },
1993 { VE::SW60, 60U },
1994 { VE::SW61, 61U },
1995 { VE::SW62, 62U },
1996 { VE::SW63, 63U },
1997 { VE::SX0, 0U },
1998 { VE::SX1, 1U },
1999 { VE::SX2, 2U },
2000 { VE::SX3, 3U },
2001 { VE::SX4, 4U },
2002 { VE::SX5, 5U },
2003 { VE::SX6, 6U },
2004 { VE::SX7, 7U },
2005 { VE::SX8, 8U },
2006 { VE::SX9, 9U },
2007 { VE::SX10, 10U },
2008 { VE::SX11, 11U },
2009 { VE::SX12, 12U },
2010 { VE::SX13, 13U },
2011 { VE::SX14, 14U },
2012 { VE::SX15, 15U },
2013 { VE::SX16, 16U },
2014 { VE::SX17, 17U },
2015 { VE::SX18, 18U },
2016 { VE::SX19, 19U },
2017 { VE::SX20, 20U },
2018 { VE::SX21, 21U },
2019 { VE::SX22, 22U },
2020 { VE::SX23, 23U },
2021 { VE::SX24, 24U },
2022 { VE::SX25, 25U },
2023 { VE::SX26, 26U },
2024 { VE::SX27, 27U },
2025 { VE::SX28, 28U },
2026 { VE::SX29, 29U },
2027 { VE::SX30, 30U },
2028 { VE::SX31, 31U },
2029 { VE::SX32, 32U },
2030 { VE::SX33, 33U },
2031 { VE::SX34, 34U },
2032 { VE::SX35, 35U },
2033 { VE::SX36, 36U },
2034 { VE::SX37, 37U },
2035 { VE::SX38, 38U },
2036 { VE::SX39, 39U },
2037 { VE::SX40, 40U },
2038 { VE::SX41, 41U },
2039 { VE::SX42, 42U },
2040 { VE::SX43, 43U },
2041 { VE::SX44, 44U },
2042 { VE::SX45, 45U },
2043 { VE::SX46, 46U },
2044 { VE::SX47, 47U },
2045 { VE::SX48, 48U },
2046 { VE::SX49, 49U },
2047 { VE::SX50, 50U },
2048 { VE::SX51, 51U },
2049 { VE::SX52, 52U },
2050 { VE::SX53, 53U },
2051 { VE::SX54, 54U },
2052 { VE::SX55, 55U },
2053 { VE::SX56, 56U },
2054 { VE::SX57, 57U },
2055 { VE::SX58, 58U },
2056 { VE::SX59, 59U },
2057 { VE::SX60, 60U },
2058 { VE::SX61, 61U },
2059 { VE::SX62, 62U },
2060 { VE::SX63, 63U },
2061 { VE::V0, 64U },
2062 { VE::V1, 65U },
2063 { VE::V2, 66U },
2064 { VE::V3, 67U },
2065 { VE::V4, 68U },
2066 { VE::V5, 69U },
2067 { VE::V6, 70U },
2068 { VE::V7, 71U },
2069 { VE::V8, 72U },
2070 { VE::V9, 73U },
2071 { VE::V10, 74U },
2072 { VE::V11, 75U },
2073 { VE::V12, 76U },
2074 { VE::V13, 77U },
2075 { VE::V14, 78U },
2076 { VE::V15, 79U },
2077 { VE::V16, 80U },
2078 { VE::V17, 81U },
2079 { VE::V18, 82U },
2080 { VE::V19, 83U },
2081 { VE::V20, 84U },
2082 { VE::V21, 85U },
2083 { VE::V22, 86U },
2084 { VE::V23, 87U },
2085 { VE::V24, 88U },
2086 { VE::V25, 89U },
2087 { VE::V26, 90U },
2088 { VE::V27, 91U },
2089 { VE::V28, 92U },
2090 { VE::V29, 93U },
2091 { VE::V30, 94U },
2092 { VE::V31, 95U },
2093 { VE::V32, 96U },
2094 { VE::V33, 97U },
2095 { VE::V34, 98U },
2096 { VE::V35, 99U },
2097 { VE::V36, 100U },
2098 { VE::V37, 101U },
2099 { VE::V38, 102U },
2100 { VE::V39, 103U },
2101 { VE::V40, 104U },
2102 { VE::V41, 105U },
2103 { VE::V42, 106U },
2104 { VE::V43, 107U },
2105 { VE::V44, 108U },
2106 { VE::V45, 109U },
2107 { VE::V46, 110U },
2108 { VE::V47, 111U },
2109 { VE::V48, 112U },
2110 { VE::V49, 113U },
2111 { VE::V50, 114U },
2112 { VE::V51, 115U },
2113 { VE::V52, 116U },
2114 { VE::V53, 117U },
2115 { VE::V54, 118U },
2116 { VE::V55, 119U },
2117 { VE::V56, 120U },
2118 { VE::V57, 121U },
2119 { VE::V58, 122U },
2120 { VE::V59, 123U },
2121 { VE::V60, 124U },
2122 { VE::V61, 125U },
2123 { VE::V62, 126U },
2124 { VE::V63, 127U },
2125 { VE::VM0, 128U },
2126 { VE::VM1, 129U },
2127 { VE::VM2, 130U },
2128 { VE::VM3, 131U },
2129 { VE::VM4, 132U },
2130 { VE::VM5, 133U },
2131 { VE::VM6, 134U },
2132 { VE::VM7, 135U },
2133 { VE::VM8, 136U },
2134 { VE::VM9, 137U },
2135 { VE::VM10, 138U },
2136 { VE::VM11, 139U },
2137 { VE::VM12, 140U },
2138 { VE::VM13, 141U },
2139 { VE::VM14, 142U },
2140 { VE::VM15, 143U },
2141};
2142extern const unsigned VEDwarfFlavour0L2DwarfSize = std::size(VEDwarfFlavour0L2Dwarf);
2143
2144extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0L2Dwarf[] = {
2145 { VE::SF0, 0U },
2146 { VE::SF1, 1U },
2147 { VE::SF2, 2U },
2148 { VE::SF3, 3U },
2149 { VE::SF4, 4U },
2150 { VE::SF5, 5U },
2151 { VE::SF6, 6U },
2152 { VE::SF7, 7U },
2153 { VE::SF8, 8U },
2154 { VE::SF9, 9U },
2155 { VE::SF10, 10U },
2156 { VE::SF11, 11U },
2157 { VE::SF12, 12U },
2158 { VE::SF13, 13U },
2159 { VE::SF14, 14U },
2160 { VE::SF15, 15U },
2161 { VE::SF16, 16U },
2162 { VE::SF17, 17U },
2163 { VE::SF18, 18U },
2164 { VE::SF19, 19U },
2165 { VE::SF20, 20U },
2166 { VE::SF21, 21U },
2167 { VE::SF22, 22U },
2168 { VE::SF23, 23U },
2169 { VE::SF24, 24U },
2170 { VE::SF25, 25U },
2171 { VE::SF26, 26U },
2172 { VE::SF27, 27U },
2173 { VE::SF28, 28U },
2174 { VE::SF29, 29U },
2175 { VE::SF30, 30U },
2176 { VE::SF31, 31U },
2177 { VE::SF32, 32U },
2178 { VE::SF33, 33U },
2179 { VE::SF34, 34U },
2180 { VE::SF35, 35U },
2181 { VE::SF36, 36U },
2182 { VE::SF37, 37U },
2183 { VE::SF38, 38U },
2184 { VE::SF39, 39U },
2185 { VE::SF40, 40U },
2186 { VE::SF41, 41U },
2187 { VE::SF42, 42U },
2188 { VE::SF43, 43U },
2189 { VE::SF44, 44U },
2190 { VE::SF45, 45U },
2191 { VE::SF46, 46U },
2192 { VE::SF47, 47U },
2193 { VE::SF48, 48U },
2194 { VE::SF49, 49U },
2195 { VE::SF50, 50U },
2196 { VE::SF51, 51U },
2197 { VE::SF52, 52U },
2198 { VE::SF53, 53U },
2199 { VE::SF54, 54U },
2200 { VE::SF55, 55U },
2201 { VE::SF56, 56U },
2202 { VE::SF57, 57U },
2203 { VE::SF58, 58U },
2204 { VE::SF59, 59U },
2205 { VE::SF60, 60U },
2206 { VE::SF61, 61U },
2207 { VE::SF62, 62U },
2208 { VE::SF63, 63U },
2209 { VE::SW0, 0U },
2210 { VE::SW1, 1U },
2211 { VE::SW2, 2U },
2212 { VE::SW3, 3U },
2213 { VE::SW4, 4U },
2214 { VE::SW5, 5U },
2215 { VE::SW6, 6U },
2216 { VE::SW7, 7U },
2217 { VE::SW8, 8U },
2218 { VE::SW9, 9U },
2219 { VE::SW10, 10U },
2220 { VE::SW11, 11U },
2221 { VE::SW12, 12U },
2222 { VE::SW13, 13U },
2223 { VE::SW14, 14U },
2224 { VE::SW15, 15U },
2225 { VE::SW16, 16U },
2226 { VE::SW17, 17U },
2227 { VE::SW18, 18U },
2228 { VE::SW19, 19U },
2229 { VE::SW20, 20U },
2230 { VE::SW21, 21U },
2231 { VE::SW22, 22U },
2232 { VE::SW23, 23U },
2233 { VE::SW24, 24U },
2234 { VE::SW25, 25U },
2235 { VE::SW26, 26U },
2236 { VE::SW27, 27U },
2237 { VE::SW28, 28U },
2238 { VE::SW29, 29U },
2239 { VE::SW30, 30U },
2240 { VE::SW31, 31U },
2241 { VE::SW32, 32U },
2242 { VE::SW33, 33U },
2243 { VE::SW34, 34U },
2244 { VE::SW35, 35U },
2245 { VE::SW36, 36U },
2246 { VE::SW37, 37U },
2247 { VE::SW38, 38U },
2248 { VE::SW39, 39U },
2249 { VE::SW40, 40U },
2250 { VE::SW41, 41U },
2251 { VE::SW42, 42U },
2252 { VE::SW43, 43U },
2253 { VE::SW44, 44U },
2254 { VE::SW45, 45U },
2255 { VE::SW46, 46U },
2256 { VE::SW47, 47U },
2257 { VE::SW48, 48U },
2258 { VE::SW49, 49U },
2259 { VE::SW50, 50U },
2260 { VE::SW51, 51U },
2261 { VE::SW52, 52U },
2262 { VE::SW53, 53U },
2263 { VE::SW54, 54U },
2264 { VE::SW55, 55U },
2265 { VE::SW56, 56U },
2266 { VE::SW57, 57U },
2267 { VE::SW58, 58U },
2268 { VE::SW59, 59U },
2269 { VE::SW60, 60U },
2270 { VE::SW61, 61U },
2271 { VE::SW62, 62U },
2272 { VE::SW63, 63U },
2273 { VE::SX0, 0U },
2274 { VE::SX1, 1U },
2275 { VE::SX2, 2U },
2276 { VE::SX3, 3U },
2277 { VE::SX4, 4U },
2278 { VE::SX5, 5U },
2279 { VE::SX6, 6U },
2280 { VE::SX7, 7U },
2281 { VE::SX8, 8U },
2282 { VE::SX9, 9U },
2283 { VE::SX10, 10U },
2284 { VE::SX11, 11U },
2285 { VE::SX12, 12U },
2286 { VE::SX13, 13U },
2287 { VE::SX14, 14U },
2288 { VE::SX15, 15U },
2289 { VE::SX16, 16U },
2290 { VE::SX17, 17U },
2291 { VE::SX18, 18U },
2292 { VE::SX19, 19U },
2293 { VE::SX20, 20U },
2294 { VE::SX21, 21U },
2295 { VE::SX22, 22U },
2296 { VE::SX23, 23U },
2297 { VE::SX24, 24U },
2298 { VE::SX25, 25U },
2299 { VE::SX26, 26U },
2300 { VE::SX27, 27U },
2301 { VE::SX28, 28U },
2302 { VE::SX29, 29U },
2303 { VE::SX30, 30U },
2304 { VE::SX31, 31U },
2305 { VE::SX32, 32U },
2306 { VE::SX33, 33U },
2307 { VE::SX34, 34U },
2308 { VE::SX35, 35U },
2309 { VE::SX36, 36U },
2310 { VE::SX37, 37U },
2311 { VE::SX38, 38U },
2312 { VE::SX39, 39U },
2313 { VE::SX40, 40U },
2314 { VE::SX41, 41U },
2315 { VE::SX42, 42U },
2316 { VE::SX43, 43U },
2317 { VE::SX44, 44U },
2318 { VE::SX45, 45U },
2319 { VE::SX46, 46U },
2320 { VE::SX47, 47U },
2321 { VE::SX48, 48U },
2322 { VE::SX49, 49U },
2323 { VE::SX50, 50U },
2324 { VE::SX51, 51U },
2325 { VE::SX52, 52U },
2326 { VE::SX53, 53U },
2327 { VE::SX54, 54U },
2328 { VE::SX55, 55U },
2329 { VE::SX56, 56U },
2330 { VE::SX57, 57U },
2331 { VE::SX58, 58U },
2332 { VE::SX59, 59U },
2333 { VE::SX60, 60U },
2334 { VE::SX61, 61U },
2335 { VE::SX62, 62U },
2336 { VE::SX63, 63U },
2337 { VE::V0, 64U },
2338 { VE::V1, 65U },
2339 { VE::V2, 66U },
2340 { VE::V3, 67U },
2341 { VE::V4, 68U },
2342 { VE::V5, 69U },
2343 { VE::V6, 70U },
2344 { VE::V7, 71U },
2345 { VE::V8, 72U },
2346 { VE::V9, 73U },
2347 { VE::V10, 74U },
2348 { VE::V11, 75U },
2349 { VE::V12, 76U },
2350 { VE::V13, 77U },
2351 { VE::V14, 78U },
2352 { VE::V15, 79U },
2353 { VE::V16, 80U },
2354 { VE::V17, 81U },
2355 { VE::V18, 82U },
2356 { VE::V19, 83U },
2357 { VE::V20, 84U },
2358 { VE::V21, 85U },
2359 { VE::V22, 86U },
2360 { VE::V23, 87U },
2361 { VE::V24, 88U },
2362 { VE::V25, 89U },
2363 { VE::V26, 90U },
2364 { VE::V27, 91U },
2365 { VE::V28, 92U },
2366 { VE::V29, 93U },
2367 { VE::V30, 94U },
2368 { VE::V31, 95U },
2369 { VE::V32, 96U },
2370 { VE::V33, 97U },
2371 { VE::V34, 98U },
2372 { VE::V35, 99U },
2373 { VE::V36, 100U },
2374 { VE::V37, 101U },
2375 { VE::V38, 102U },
2376 { VE::V39, 103U },
2377 { VE::V40, 104U },
2378 { VE::V41, 105U },
2379 { VE::V42, 106U },
2380 { VE::V43, 107U },
2381 { VE::V44, 108U },
2382 { VE::V45, 109U },
2383 { VE::V46, 110U },
2384 { VE::V47, 111U },
2385 { VE::V48, 112U },
2386 { VE::V49, 113U },
2387 { VE::V50, 114U },
2388 { VE::V51, 115U },
2389 { VE::V52, 116U },
2390 { VE::V53, 117U },
2391 { VE::V54, 118U },
2392 { VE::V55, 119U },
2393 { VE::V56, 120U },
2394 { VE::V57, 121U },
2395 { VE::V58, 122U },
2396 { VE::V59, 123U },
2397 { VE::V60, 124U },
2398 { VE::V61, 125U },
2399 { VE::V62, 126U },
2400 { VE::V63, 127U },
2401 { VE::VM0, 128U },
2402 { VE::VM1, 129U },
2403 { VE::VM2, 130U },
2404 { VE::VM3, 131U },
2405 { VE::VM4, 132U },
2406 { VE::VM5, 133U },
2407 { VE::VM6, 134U },
2408 { VE::VM7, 135U },
2409 { VE::VM8, 136U },
2410 { VE::VM9, 137U },
2411 { VE::VM10, 138U },
2412 { VE::VM11, 139U },
2413 { VE::VM12, 140U },
2414 { VE::VM13, 141U },
2415 { VE::VM14, 142U },
2416 { VE::VM15, 143U },
2417};
2418extern const unsigned VEEHFlavour0L2DwarfSize = std::size(VEEHFlavour0L2Dwarf);
2419
2420extern const uint16_t VERegEncodingTable[] = {
2421 0,
2422 62,
2423 7,
2424 1,
2425 2,
2426 0,
2427 255,
2428 63,
2429 16,
2430 17,
2431 18,
2432 19,
2433 20,
2434 21,
2435 22,
2436 23,
2437 24,
2438 25,
2439 26,
2440 27,
2441 28,
2442 29,
2443 30,
2444 8,
2445 9,
2446 10,
2447 11,
2448 0,
2449 2,
2450 4,
2451 6,
2452 8,
2453 10,
2454 12,
2455 14,
2456 16,
2457 18,
2458 20,
2459 22,
2460 24,
2461 26,
2462 28,
2463 30,
2464 32,
2465 34,
2466 36,
2467 38,
2468 40,
2469 42,
2470 44,
2471 46,
2472 48,
2473 50,
2474 52,
2475 54,
2476 56,
2477 58,
2478 60,
2479 62,
2480 0,
2481 1,
2482 2,
2483 3,
2484 4,
2485 5,
2486 6,
2487 7,
2488 8,
2489 9,
2490 10,
2491 11,
2492 12,
2493 13,
2494 14,
2495 15,
2496 16,
2497 17,
2498 18,
2499 19,
2500 20,
2501 21,
2502 22,
2503 23,
2504 24,
2505 25,
2506 26,
2507 27,
2508 28,
2509 29,
2510 30,
2511 31,
2512 32,
2513 33,
2514 34,
2515 35,
2516 36,
2517 37,
2518 38,
2519 39,
2520 40,
2521 41,
2522 42,
2523 43,
2524 44,
2525 45,
2526 46,
2527 47,
2528 48,
2529 49,
2530 50,
2531 51,
2532 52,
2533 53,
2534 54,
2535 55,
2536 56,
2537 57,
2538 58,
2539 59,
2540 60,
2541 61,
2542 62,
2543 63,
2544 0,
2545 1,
2546 2,
2547 3,
2548 4,
2549 5,
2550 6,
2551 7,
2552 8,
2553 9,
2554 10,
2555 11,
2556 12,
2557 13,
2558 14,
2559 15,
2560 16,
2561 17,
2562 18,
2563 19,
2564 20,
2565 21,
2566 22,
2567 23,
2568 24,
2569 25,
2570 26,
2571 27,
2572 28,
2573 29,
2574 30,
2575 31,
2576 32,
2577 33,
2578 34,
2579 35,
2580 36,
2581 37,
2582 38,
2583 39,
2584 40,
2585 41,
2586 42,
2587 43,
2588 44,
2589 45,
2590 46,
2591 47,
2592 48,
2593 49,
2594 50,
2595 51,
2596 52,
2597 53,
2598 54,
2599 55,
2600 56,
2601 57,
2602 58,
2603 59,
2604 60,
2605 61,
2606 62,
2607 63,
2608 0,
2609 1,
2610 2,
2611 3,
2612 4,
2613 5,
2614 6,
2615 7,
2616 8,
2617 9,
2618 10,
2619 11,
2620 12,
2621 13,
2622 14,
2623 15,
2624 16,
2625 17,
2626 18,
2627 19,
2628 20,
2629 21,
2630 22,
2631 23,
2632 24,
2633 25,
2634 26,
2635 27,
2636 28,
2637 29,
2638 30,
2639 31,
2640 32,
2641 33,
2642 34,
2643 35,
2644 36,
2645 37,
2646 38,
2647 39,
2648 40,
2649 41,
2650 42,
2651 43,
2652 44,
2653 45,
2654 46,
2655 47,
2656 48,
2657 49,
2658 50,
2659 51,
2660 52,
2661 53,
2662 54,
2663 55,
2664 56,
2665 57,
2666 58,
2667 59,
2668 60,
2669 61,
2670 62,
2671 63,
2672 0,
2673 1,
2674 2,
2675 3,
2676 4,
2677 5,
2678 6,
2679 7,
2680 8,
2681 9,
2682 10,
2683 11,
2684 12,
2685 13,
2686 14,
2687 15,
2688 16,
2689 17,
2690 18,
2691 19,
2692 20,
2693 21,
2694 22,
2695 23,
2696 24,
2697 25,
2698 26,
2699 27,
2700 28,
2701 29,
2702 30,
2703 31,
2704 32,
2705 33,
2706 34,
2707 35,
2708 36,
2709 37,
2710 38,
2711 39,
2712 40,
2713 41,
2714 42,
2715 43,
2716 44,
2717 45,
2718 46,
2719 47,
2720 48,
2721 49,
2722 50,
2723 51,
2724 52,
2725 53,
2726 54,
2727 55,
2728 56,
2729 57,
2730 58,
2731 59,
2732 60,
2733 61,
2734 62,
2735 63,
2736 0,
2737 1,
2738 2,
2739 3,
2740 4,
2741 5,
2742 6,
2743 7,
2744 8,
2745 9,
2746 10,
2747 11,
2748 12,
2749 13,
2750 14,
2751 15,
2752 0,
2753 2,
2754 4,
2755 6,
2756 8,
2757 10,
2758 12,
2759 14,
2760};
2761static inline void InitVEMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
2762 RI->InitMCRegisterInfo(VERegDesc, 339, RA, PC, VEMCRegisterClasses, 10, VERegUnitRoots, 171, VERegDiffLists, VELaneMaskLists, VERegStrings, VERegClassStrings, VESubRegIdxLists, 9,
2763VERegEncodingTable);
2764
2765 switch (DwarfFlavour) {
2766 default:
2767 llvm_unreachable("Unknown DWARF flavour");
2768 case 0:
2769 RI->mapDwarfRegsToLLVMRegs(VEDwarfFlavour0Dwarf2L, VEDwarfFlavour0Dwarf2LSize, false);
2770 break;
2771 }
2772 switch (EHFlavour) {
2773 default:
2774 llvm_unreachable("Unknown DWARF flavour");
2775 case 0:
2776 RI->mapDwarfRegsToLLVMRegs(VEEHFlavour0Dwarf2L, VEEHFlavour0Dwarf2LSize, true);
2777 break;
2778 }
2779 switch (DwarfFlavour) {
2780 default:
2781 llvm_unreachable("Unknown DWARF flavour");
2782 case 0:
2783 RI->mapLLVMRegsToDwarfRegs(VEDwarfFlavour0L2Dwarf, VEDwarfFlavour0L2DwarfSize, false);
2784 break;
2785 }
2786 switch (EHFlavour) {
2787 default:
2788 llvm_unreachable("Unknown DWARF flavour");
2789 case 0:
2790 RI->mapLLVMRegsToDwarfRegs(VEEHFlavour0L2Dwarf, VEEHFlavour0L2DwarfSize, true);
2791 break;
2792 }
2793}
2794
2795} // end namespace llvm
2796
2797#endif // GET_REGINFO_MC_DESC
2798
2799/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2800|* *|
2801|* Register Information Header Fragment *|
2802|* *|
2803|* Automatically generated file, do not edit! *|
2804|* *|
2805\*===----------------------------------------------------------------------===*/
2806
2807
2808#ifdef GET_REGINFO_HEADER
2809#undef GET_REGINFO_HEADER
2810
2811#include "llvm/CodeGen/TargetRegisterInfo.h"
2812
2813namespace llvm {
2814
2815class VEFrameLowering;
2816
2817struct VEGenRegisterInfo : public TargetRegisterInfo {
2818 explicit VEGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
2819 unsigned PC = 0, unsigned HwMode = 0);
2820 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
2821 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2822 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
2823 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
2824 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
2825 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
2826 unsigned getRegUnitWeight(unsigned RegUnit) const override;
2827 unsigned getNumRegPressureSets() const override;
2828 const char *getRegPressureSetName(unsigned Idx) const override;
2829 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
2830 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
2831 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
2832 ArrayRef<const char *> getRegMaskNames() const override;
2833 ArrayRef<const uint32_t *> getRegMasks() const override;
2834 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
2835 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
2836 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
2837 bool isConstantPhysReg(MCRegister PhysReg) const override final;
2838 /// Devirtualized TargetFrameLowering.
2839 static const VEFrameLowering *getFrameLowering(
2840 const MachineFunction &MF);
2841};
2842
2843namespace VE { // Register classes
2844 extern const TargetRegisterClass F32RegClass;
2845 extern const TargetRegisterClass I32RegClass;
2846 extern const TargetRegisterClass VLSRegClass;
2847 extern const TargetRegisterClass I64RegClass;
2848 extern const TargetRegisterClass MISCRegClass;
2849 extern const TargetRegisterClass F128RegClass;
2850 extern const TargetRegisterClass VMRegClass;
2851 extern const TargetRegisterClass VM512RegClass;
2852 extern const TargetRegisterClass VM512_with_sub_vm_evenRegClass;
2853 extern const TargetRegisterClass V64RegClass;
2854} // end namespace VE
2855
2856} // end namespace llvm
2857
2858#endif // GET_REGINFO_HEADER
2859
2860/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2861|* *|
2862|* Target Register and Register Classes Information *|
2863|* *|
2864|* Automatically generated file, do not edit! *|
2865|* *|
2866\*===----------------------------------------------------------------------===*/
2867
2868
2869#ifdef GET_REGINFO_TARGET_DESC
2870#undef GET_REGINFO_TARGET_DESC
2871
2872namespace llvm {
2873
2874extern const MCRegisterClass VEMCRegisterClasses[];
2875
2876static const MVT::SimpleValueType VTLists[] = {
2877 /* 0 */ MVT::i32, MVT::Other,
2878 /* 2 */ MVT::i64, MVT::Other,
2879 /* 4 */ MVT::f32, MVT::Other,
2880 /* 6 */ MVT::i64, MVT::f64, MVT::Other,
2881 /* 9 */ MVT::f128, MVT::Other,
2882 /* 11 */ MVT::v256i1, MVT::Other,
2883 /* 13 */ MVT::v512i1, MVT::Other,
2884 /* 15 */ MVT::v256f64, MVT::v512i32, MVT::v512f32, MVT::v256i64, MVT::v256i32, MVT::v256f32, MVT::Other,
2885};
2886
2887static const char *SubRegIndexNameTable[] = { "sub_even", "sub_f32", "sub_i32", "sub_odd", "sub_vm_even", "sub_vm_odd", "sub_odd_then_sub_f32", "sub_odd_then_sub_i32", "" };
2888
2889static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
2890 { 65535, 65535 },
2891 { 0, 64 }, // sub_even
2892 { 0, 32 }, // sub_f32
2893 { 32, 32 }, // sub_i32
2894 { 64, 64 }, // sub_odd
2895 { 0, 256 }, // sub_vm_even
2896 { 256, 256 }, // sub_vm_odd
2897 { 64, 32 }, // sub_odd_then_sub_f32
2898 { 96, 32 }, // sub_odd_then_sub_i32
2899};
2900
2901
2902static const LaneBitmask SubRegIndexLaneMaskTable[] = {
2903 LaneBitmask::getAll(),
2904 LaneBitmask(0x0000000000000003), // sub_even
2905 LaneBitmask(0x0000000000000001), // sub_f32
2906 LaneBitmask(0x0000000000000002), // sub_i32
2907 LaneBitmask(0x0000000000000030), // sub_odd
2908 LaneBitmask(0x0000000000000004), // sub_vm_even
2909 LaneBitmask(0x0000000000000008), // sub_vm_odd
2910 LaneBitmask(0x0000000000000010), // sub_odd_then_sub_f32
2911 LaneBitmask(0x0000000000000020), // sub_odd_then_sub_i32
2912 };
2913
2914
2915
2916static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
2917 // Mode = 0 (Default)
2918 { 32, 32, 32, /*VTLists+*/4 }, // F32
2919 { 32, 32, 32, /*VTLists+*/0 }, // I32
2920 { 32, 32, 64, /*VTLists+*/0 }, // VLS
2921 { 64, 64, 64, /*VTLists+*/6 }, // I64
2922 { 64, 64, 64, /*VTLists+*/2 }, // MISC
2923 { 128, 128, 128, /*VTLists+*/9 }, // F128
2924 { 256, 256, 64, /*VTLists+*/11 }, // VM
2925 { 512, 512, 64, /*VTLists+*/13 }, // VM512
2926 { 512, 512, 64, /*VTLists+*/13 }, // VM512_with_sub_vm_even
2927 { 16384, 16384, 64, /*VTLists+*/15 }, // V64
2928};
2929
2930static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
2931
2932static const uint32_t F32SubClassMask[] = {
2933 0x00000001,
2934 0x00000028, // sub_f32
2935 0x00000020, // sub_odd_then_sub_f32
2936};
2937
2938static const uint32_t I32SubClassMask[] = {
2939 0x00000002,
2940 0x00000028, // sub_i32
2941 0x00000020, // sub_odd_then_sub_i32
2942};
2943
2944static const uint32_t VLSSubClassMask[] = {
2945 0x00000004,
2946};
2947
2948static const uint32_t I64SubClassMask[] = {
2949 0x00000008,
2950 0x00000020, // sub_even
2951 0x00000020, // sub_odd
2952};
2953
2954static const uint32_t MISCSubClassMask[] = {
2955 0x00000010,
2956};
2957
2958static const uint32_t F128SubClassMask[] = {
2959 0x00000020,
2960};
2961
2962static const uint32_t VMSubClassMask[] = {
2963 0x00000040,
2964 0x00000100, // sub_vm_even
2965 0x00000100, // sub_vm_odd
2966};
2967
2968static const uint32_t VM512SubClassMask[] = {
2969 0x00000180,
2970};
2971
2972static const uint32_t VM512_with_sub_vm_evenSubClassMask[] = {
2973 0x00000100,
2974};
2975
2976static const uint32_t V64SubClassMask[] = {
2977 0x00000200,
2978};
2979
2980static const uint16_t SuperRegIdxSeqs[] = {
2981 /* 0 */ 1, 4, 0,
2982 /* 3 */ 5, 6, 0,
2983 /* 6 */ 2, 7, 0,
2984 /* 9 */ 3, 8, 0,
2985};
2986
2987static const TargetRegisterClass *const VM512_with_sub_vm_evenSuperclasses[] = {
2988 &VE::VM512RegClass,
2989 nullptr
2990};
2991
2992
2993namespace VE { // Register class instances
2994 extern const TargetRegisterClass F32RegClass = {
2995 &VEMCRegisterClasses[F32RegClassID],
2996 F32SubClassMask,
2997 SuperRegIdxSeqs + 6,
2998 LaneBitmask(0x0000000000000001),
2999 0,
3000 false,
3001 0x00, /* TSFlags */
3002 false, /* HasDisjunctSubRegs */
3003 false, /* CoveredBySubRegs */
3004 NullRegClasses,
3005 nullptr
3006 };
3007
3008 extern const TargetRegisterClass I32RegClass = {
3009 &VEMCRegisterClasses[I32RegClassID],
3010 I32SubClassMask,
3011 SuperRegIdxSeqs + 9,
3012 LaneBitmask(0x0000000000000001),
3013 0,
3014 false,
3015 0x00, /* TSFlags */
3016 false, /* HasDisjunctSubRegs */
3017 false, /* CoveredBySubRegs */
3018 NullRegClasses,
3019 nullptr
3020 };
3021
3022 extern const TargetRegisterClass VLSRegClass = {
3023 &VEMCRegisterClasses[VLSRegClassID],
3024 VLSSubClassMask,
3025 SuperRegIdxSeqs + 2,
3026 LaneBitmask(0x0000000000000001),
3027 0,
3028 false,
3029 0x00, /* TSFlags */
3030 false, /* HasDisjunctSubRegs */
3031 false, /* CoveredBySubRegs */
3032 NullRegClasses,
3033 nullptr
3034 };
3035
3036 extern const TargetRegisterClass I64RegClass = {
3037 &VEMCRegisterClasses[I64RegClassID],
3038 I64SubClassMask,
3039 SuperRegIdxSeqs + 0,
3040 LaneBitmask(0x0000000000000003),
3041 0,
3042 false,
3043 0x00, /* TSFlags */
3044 true, /* HasDisjunctSubRegs */
3045 true, /* CoveredBySubRegs */
3046 NullRegClasses,
3047 nullptr
3048 };
3049
3050 extern const TargetRegisterClass MISCRegClass = {
3051 &VEMCRegisterClasses[MISCRegClassID],
3052 MISCSubClassMask,
3053 SuperRegIdxSeqs + 2,
3054 LaneBitmask(0x0000000000000001),
3055 0,
3056 false,
3057 0x00, /* TSFlags */
3058 false, /* HasDisjunctSubRegs */
3059 false, /* CoveredBySubRegs */
3060 NullRegClasses,
3061 nullptr
3062 };
3063
3064 extern const TargetRegisterClass F128RegClass = {
3065 &VEMCRegisterClasses[F128RegClassID],
3066 F128SubClassMask,
3067 SuperRegIdxSeqs + 2,
3068 LaneBitmask(0x0000000000000033),
3069 0,
3070 false,
3071 0x00, /* TSFlags */
3072 true, /* HasDisjunctSubRegs */
3073 true, /* CoveredBySubRegs */
3074 NullRegClasses,
3075 nullptr
3076 };
3077
3078 extern const TargetRegisterClass VMRegClass = {
3079 &VEMCRegisterClasses[VMRegClassID],
3080 VMSubClassMask,
3081 SuperRegIdxSeqs + 3,
3082 LaneBitmask(0x0000000000000001),
3083 0,
3084 false,
3085 0x00, /* TSFlags */
3086 false, /* HasDisjunctSubRegs */
3087 false, /* CoveredBySubRegs */
3088 NullRegClasses,
3089 nullptr
3090 };
3091
3092 extern const TargetRegisterClass VM512RegClass = {
3093 &VEMCRegisterClasses[VM512RegClassID],
3094 VM512SubClassMask,
3095 SuperRegIdxSeqs + 2,
3096 LaneBitmask(0x000000000000000C),
3097 0,
3098 false,
3099 0x00, /* TSFlags */
3100 true, /* HasDisjunctSubRegs */
3101 false, /* CoveredBySubRegs */
3102 NullRegClasses,
3103 nullptr
3104 };
3105
3106 extern const TargetRegisterClass VM512_with_sub_vm_evenRegClass = {
3107 &VEMCRegisterClasses[VM512_with_sub_vm_evenRegClassID],
3108 VM512_with_sub_vm_evenSubClassMask,
3109 SuperRegIdxSeqs + 2,
3110 LaneBitmask(0x000000000000000C),
3111 0,
3112 false,
3113 0x00, /* TSFlags */
3114 true, /* HasDisjunctSubRegs */
3115 true, /* CoveredBySubRegs */
3116 VM512_with_sub_vm_evenSuperclasses,
3117 nullptr
3118 };
3119
3120 extern const TargetRegisterClass V64RegClass = {
3121 &VEMCRegisterClasses[V64RegClassID],
3122 V64SubClassMask,
3123 SuperRegIdxSeqs + 2,
3124 LaneBitmask(0x0000000000000001),
3125 0,
3126 false,
3127 0x00, /* TSFlags */
3128 false, /* HasDisjunctSubRegs */
3129 false, /* CoveredBySubRegs */
3130 NullRegClasses,
3131 nullptr
3132 };
3133
3134} // end namespace VE
3135
3136namespace {
3137 const TargetRegisterClass *const RegisterClasses[] = {
3138 &VE::F32RegClass,
3139 &VE::I32RegClass,
3140 &VE::VLSRegClass,
3141 &VE::I64RegClass,
3142 &VE::MISCRegClass,
3143 &VE::F128RegClass,
3144 &VE::VMRegClass,
3145 &VE::VM512RegClass,
3146 &VE::VM512_with_sub_vm_evenRegClass,
3147 &VE::V64RegClass,
3148 };
3149} // end anonymous namespace
3150
3151static const uint8_t CostPerUseTable[] = {
31520, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
3153
3154
3155static const bool InAllocatableClassTable[] = {
3156false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
3157
3158
3159static const TargetRegisterInfoDesc VERegInfoDesc = { // Extra Descriptors
3160CostPerUseTable, 1, InAllocatableClassTable};
3161
3162unsigned VEGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
3163 static const uint8_t RowMap[8] = {
3164 0, 0, 0, 1, 0, 0, 0, 0,
3165 };
3166 static const uint8_t Rows[2][8] = {
3167 { 0, VE::sub_f32, VE::sub_i32, 0, 0, 0, 0, 0, },
3168 { 0, VE::sub_odd_then_sub_f32, VE::sub_odd_then_sub_i32, 0, 0, 0, 0, 0, },
3169 };
3170
3171 --IdxA; assert(IdxA < 8); (void) IdxA;
3172 --IdxB; assert(IdxB < 8);
3173 return Rows[RowMap[IdxA]][IdxB];
3174}
3175
3176 struct MaskRolOp {
3177 LaneBitmask Mask;
3178 uint8_t RotateLeft;
3179 };
3180 static const MaskRolOp LaneMaskComposeSequences[] = {
3181 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
3182 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
3183 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
3184 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
3185 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
3186 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 } // Sequence 10
3187 };
3188 static const uint8_t CompositeSequences[] = {
3189 0, // to sub_even
3190 0, // to sub_f32
3191 2, // to sub_i32
3192 4, // to sub_odd
3193 6, // to sub_vm_even
3194 8, // to sub_vm_odd
3195 4, // to sub_odd_then_sub_f32
3196 10 // to sub_odd_then_sub_i32
3197 };
3198
3199LaneBitmask VEGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
3200 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
3201 LaneBitmask Result;
3202 for (const MaskRolOp *Ops =
3203 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
3204 Ops->Mask.any(); ++Ops) {
3205 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
3206 if (unsigned S = Ops->RotateLeft)
3207 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
3208 else
3209 Result |= LaneBitmask(M);
3210 }
3211 return Result;
3212}
3213
3214LaneBitmask VEGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
3215 LaneMask &= getSubRegIndexLaneMask(IdxA);
3216 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
3217 LaneBitmask Result;
3218 for (const MaskRolOp *Ops =
3219 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
3220 Ops->Mask.any(); ++Ops) {
3221 LaneBitmask::Type M = LaneMask.getAsInteger();
3222 if (unsigned S = Ops->RotateLeft)
3223 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
3224 else
3225 Result |= LaneBitmask(M);
3226 }
3227 return Result;
3228}
3229
3230const TargetRegisterClass *VEGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
3231 static const uint8_t Table[10][8] = {
3232 { // F32
3233 0, // sub_even
3234 0, // sub_f32
3235 0, // sub_i32
3236 0, // sub_odd
3237 0, // sub_vm_even
3238 0, // sub_vm_odd
3239 0, // sub_odd_then_sub_f32
3240 0, // sub_odd_then_sub_i32
3241 },
3242 { // I32
3243 0, // sub_even
3244 0, // sub_f32
3245 0, // sub_i32
3246 0, // sub_odd
3247 0, // sub_vm_even
3248 0, // sub_vm_odd
3249 0, // sub_odd_then_sub_f32
3250 0, // sub_odd_then_sub_i32
3251 },
3252 { // VLS
3253 0, // sub_even
3254 0, // sub_f32
3255 0, // sub_i32
3256 0, // sub_odd
3257 0, // sub_vm_even
3258 0, // sub_vm_odd
3259 0, // sub_odd_then_sub_f32
3260 0, // sub_odd_then_sub_i32
3261 },
3262 { // I64
3263 0, // sub_even
3264 4, // sub_f32 -> I64
3265 4, // sub_i32 -> I64
3266 0, // sub_odd
3267 0, // sub_vm_even
3268 0, // sub_vm_odd
3269 0, // sub_odd_then_sub_f32
3270 0, // sub_odd_then_sub_i32
3271 },
3272 { // MISC
3273 0, // sub_even
3274 0, // sub_f32
3275 0, // sub_i32
3276 0, // sub_odd
3277 0, // sub_vm_even
3278 0, // sub_vm_odd
3279 0, // sub_odd_then_sub_f32
3280 0, // sub_odd_then_sub_i32
3281 },
3282 { // F128
3283 6, // sub_even -> F128
3284 6, // sub_f32 -> F128
3285 6, // sub_i32 -> F128
3286 6, // sub_odd -> F128
3287 0, // sub_vm_even
3288 0, // sub_vm_odd
3289 6, // sub_odd_then_sub_f32 -> F128
3290 6, // sub_odd_then_sub_i32 -> F128
3291 },
3292 { // VM
3293 0, // sub_even
3294 0, // sub_f32
3295 0, // sub_i32
3296 0, // sub_odd
3297 0, // sub_vm_even
3298 0, // sub_vm_odd
3299 0, // sub_odd_then_sub_f32
3300 0, // sub_odd_then_sub_i32
3301 },
3302 { // VM512
3303 0, // sub_even
3304 0, // sub_f32
3305 0, // sub_i32
3306 0, // sub_odd
3307 9, // sub_vm_even -> VM512_with_sub_vm_even
3308 9, // sub_vm_odd -> VM512_with_sub_vm_even
3309 0, // sub_odd_then_sub_f32
3310 0, // sub_odd_then_sub_i32
3311 },
3312 { // VM512_with_sub_vm_even
3313 0, // sub_even
3314 0, // sub_f32
3315 0, // sub_i32
3316 0, // sub_odd
3317 9, // sub_vm_even -> VM512_with_sub_vm_even
3318 9, // sub_vm_odd -> VM512_with_sub_vm_even
3319 0, // sub_odd_then_sub_f32
3320 0, // sub_odd_then_sub_i32
3321 },
3322 { // V64
3323 0, // sub_even
3324 0, // sub_f32
3325 0, // sub_i32
3326 0, // sub_odd
3327 0, // sub_vm_even
3328 0, // sub_vm_odd
3329 0, // sub_odd_then_sub_f32
3330 0, // sub_odd_then_sub_i32
3331 },
3332 };
3333 assert(RC && "Missing regclass");
3334 if (!Idx) return RC;
3335 --Idx;
3336 assert(Idx < 8 && "Bad subreg");
3337 unsigned TV = Table[RC->getID()][Idx];
3338 return TV ? getRegClass(TV - 1) : nullptr;
3339}
3340
3341const TargetRegisterClass *VEGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
3342 static const uint8_t Table[10][8] = {
3343 { // F32
3344 0, // F32:sub_even
3345 0, // F32:sub_f32
3346 0, // F32:sub_i32
3347 0, // F32:sub_odd
3348 0, // F32:sub_vm_even
3349 0, // F32:sub_vm_odd
3350 0, // F32:sub_odd_then_sub_f32
3351 0, // F32:sub_odd_then_sub_i32
3352 },
3353 { // I32
3354 0, // I32:sub_even
3355 0, // I32:sub_f32
3356 0, // I32:sub_i32
3357 0, // I32:sub_odd
3358 0, // I32:sub_vm_even
3359 0, // I32:sub_vm_odd
3360 0, // I32:sub_odd_then_sub_f32
3361 0, // I32:sub_odd_then_sub_i32
3362 },
3363 { // VLS
3364 0, // VLS:sub_even
3365 0, // VLS:sub_f32
3366 0, // VLS:sub_i32
3367 0, // VLS:sub_odd
3368 0, // VLS:sub_vm_even
3369 0, // VLS:sub_vm_odd
3370 0, // VLS:sub_odd_then_sub_f32
3371 0, // VLS:sub_odd_then_sub_i32
3372 },
3373 { // I64
3374 0, // I64:sub_even
3375 1, // I64:sub_f32 -> F32
3376 2, // I64:sub_i32 -> I32
3377 0, // I64:sub_odd
3378 0, // I64:sub_vm_even
3379 0, // I64:sub_vm_odd
3380 0, // I64:sub_odd_then_sub_f32
3381 0, // I64:sub_odd_then_sub_i32
3382 },
3383 { // MISC
3384 0, // MISC:sub_even
3385 0, // MISC:sub_f32
3386 0, // MISC:sub_i32
3387 0, // MISC:sub_odd
3388 0, // MISC:sub_vm_even
3389 0, // MISC:sub_vm_odd
3390 0, // MISC:sub_odd_then_sub_f32
3391 0, // MISC:sub_odd_then_sub_i32
3392 },
3393 { // F128
3394 4, // F128:sub_even -> I64
3395 1, // F128:sub_f32 -> F32
3396 2, // F128:sub_i32 -> I32
3397 4, // F128:sub_odd -> I64
3398 0, // F128:sub_vm_even
3399 0, // F128:sub_vm_odd
3400 1, // F128:sub_odd_then_sub_f32 -> F32
3401 2, // F128:sub_odd_then_sub_i32 -> I32
3402 },
3403 { // VM
3404 0, // VM:sub_even
3405 0, // VM:sub_f32
3406 0, // VM:sub_i32
3407 0, // VM:sub_odd
3408 0, // VM:sub_vm_even
3409 0, // VM:sub_vm_odd
3410 0, // VM:sub_odd_then_sub_f32
3411 0, // VM:sub_odd_then_sub_i32
3412 },
3413 { // VM512
3414 0, // VM512:sub_even
3415 0, // VM512:sub_f32
3416 0, // VM512:sub_i32
3417 0, // VM512:sub_odd
3418 7, // VM512:sub_vm_even -> VM
3419 7, // VM512:sub_vm_odd -> VM
3420 0, // VM512:sub_odd_then_sub_f32
3421 0, // VM512:sub_odd_then_sub_i32
3422 },
3423 { // VM512_with_sub_vm_even
3424 0, // VM512_with_sub_vm_even:sub_even
3425 0, // VM512_with_sub_vm_even:sub_f32
3426 0, // VM512_with_sub_vm_even:sub_i32
3427 0, // VM512_with_sub_vm_even:sub_odd
3428 7, // VM512_with_sub_vm_even:sub_vm_even -> VM
3429 7, // VM512_with_sub_vm_even:sub_vm_odd -> VM
3430 0, // VM512_with_sub_vm_even:sub_odd_then_sub_f32
3431 0, // VM512_with_sub_vm_even:sub_odd_then_sub_i32
3432 },
3433 { // V64
3434 0, // V64:sub_even
3435 0, // V64:sub_f32
3436 0, // V64:sub_i32
3437 0, // V64:sub_odd
3438 0, // V64:sub_vm_even
3439 0, // V64:sub_vm_odd
3440 0, // V64:sub_odd_then_sub_f32
3441 0, // V64:sub_odd_then_sub_i32
3442 },
3443 };
3444 assert(RC && "Missing regclass");
3445 if (!Idx) return RC;
3446 --Idx;
3447 assert(Idx < 8 && "Bad subreg");
3448 unsigned TV = Table[RC->getID()][Idx];
3449 return TV ? getRegClass(TV - 1) : nullptr;
3450}
3451
3452/// Get the weight in units of pressure for this register class.
3453const RegClassWeight &VEGenRegisterInfo::
3454getRegClassWeight(const TargetRegisterClass *RC) const {
3455 static const RegClassWeight RCWeightTable[] = {
3456 {1, 64}, // F32
3457 {1, 64}, // I32
3458 {1, 1}, // VLS
3459 {1, 64}, // I64
3460 {1, 23}, // MISC
3461 {2, 64}, // F128
3462 {1, 16}, // VM
3463 {2, 16}, // VM512
3464 {2, 14}, // VM512_with_sub_vm_even
3465 {1, 65}, // V64
3466 };
3467 return RCWeightTable[RC->getID()];
3468}
3469
3470/// Get the weight in units of pressure for this register unit.
3471unsigned VEGenRegisterInfo::
3472getRegUnitWeight(unsigned RegUnit) const {
3473 assert(RegUnit < 171 && "invalid register unit");
3474 static const uint8_t RUWeightTable[] = {
3475 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, };
3476 return RUWeightTable[RegUnit];
3477}
3478
3479
3480// Get the number of dimensions of register pressure.
3481unsigned VEGenRegisterInfo::getNumRegPressureSets() const {
3482 return 7;
3483}
3484
3485// Get the name of this register unit pressure set.
3486const char *VEGenRegisterInfo::
3487getRegPressureSetName(unsigned Idx) const {
3488 static const char *PressureNameTable[] = {
3489 "VLS",
3490 "VM512",
3491 "VM",
3492 "VM_with_VM512",
3493 "MISC",
3494 "F32",
3495 "V64",
3496 };
3497 return PressureNameTable[Idx];
3498}
3499
3500// Get the register unit pressure limit for this dimension.
3501// This limit must be adjusted dynamically for reserved registers.
3502unsigned VEGenRegisterInfo::
3503getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
3504 static const uint8_t PressureLimitTable[] = {
3505 1, // 0: VLS
3506 16, // 1: VM512
3507 16, // 2: VM
3508 18, // 3: VM_with_VM512
3509 23, // 4: MISC
3510 64, // 5: F32
3511 65, // 6: V64
3512 };
3513 return PressureLimitTable[Idx];
3514}
3515
3516/// Table of pressure sets per register class or unit.
3517static const int RCSetsTable[] = {
3518 /* 0 */ 0, -1,
3519 /* 2 */ 1, 3, -1,
3520 /* 5 */ 1, 2, 3, -1,
3521 /* 9 */ 4, -1,
3522 /* 11 */ 5, -1,
3523 /* 13 */ 6, -1,
3524};
3525
3526/// Get the dimensions of register pressure impacted by this register class.
3527/// Returns a -1 terminated array of pressure set IDs
3528const int *VEGenRegisterInfo::
3529getRegClassPressureSets(const TargetRegisterClass *RC) const {
3530 static const uint8_t RCSetStartTable[] = {
3531 11,11,0,11,9,11,6,2,5,13,};
3532 return &RCSetsTable[RCSetStartTable[RC->getID()]];
3533}
3534
3535/// Get the dimensions of register pressure impacted by this register unit.
3536/// Returns a -1 terminated array of pressure set IDs
3537const int *VEGenRegisterInfo::
3538getRegUnitPressureSets(unsigned RegUnit) const {
3539 assert(RegUnit < 171 && "invalid register unit");
3540 static const uint8_t RUSetStartTable[] = {
3541 1,9,9,9,9,13,0,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,6,6,5,5,5,5,5,5,5,5,5,5,5,5,5,5,2,};
3542 return &RCSetsTable[RUSetStartTable[RegUnit]];
3543}
3544
3545extern const MCRegisterDesc VERegDesc[];
3546extern const int16_t VERegDiffLists[];
3547extern const LaneBitmask VELaneMaskLists[];
3548extern const char VERegStrings[];
3549extern const char VERegClassStrings[];
3550extern const MCPhysReg VERegUnitRoots[][2];
3551extern const uint16_t VESubRegIdxLists[];
3552extern const uint16_t VERegEncodingTable[];
3553// VE Dwarf<->LLVM register mappings.
3554extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0Dwarf2L[];
3555extern const unsigned VEDwarfFlavour0Dwarf2LSize;
3556
3557extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0Dwarf2L[];
3558extern const unsigned VEEHFlavour0Dwarf2LSize;
3559
3560extern const MCRegisterInfo::DwarfLLVMRegPair VEDwarfFlavour0L2Dwarf[];
3561extern const unsigned VEDwarfFlavour0L2DwarfSize;
3562
3563extern const MCRegisterInfo::DwarfLLVMRegPair VEEHFlavour0L2Dwarf[];
3564extern const unsigned VEEHFlavour0L2DwarfSize;
3565
3566VEGenRegisterInfo::
3567VEGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
3568 unsigned PC, unsigned HwMode)
3569 : TargetRegisterInfo(&VERegInfoDesc, RegisterClasses, RegisterClasses+10,
3570 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
3571 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
3572 InitMCRegisterInfo(VERegDesc, 339, RA, PC,
3573 VEMCRegisterClasses, 10,
3574 VERegUnitRoots,
3575 171,
3576 VERegDiffLists,
3577 VELaneMaskLists,
3578 VERegStrings,
3579 VERegClassStrings,
3580 VESubRegIdxLists,
3581 9,
3582 VERegEncodingTable);
3583
3584 switch (DwarfFlavour) {
3585 default:
3586 llvm_unreachable("Unknown DWARF flavour");
3587 case 0:
3588 mapDwarfRegsToLLVMRegs(VEDwarfFlavour0Dwarf2L, VEDwarfFlavour0Dwarf2LSize, false);
3589 break;
3590 }
3591 switch (EHFlavour) {
3592 default:
3593 llvm_unreachable("Unknown DWARF flavour");
3594 case 0:
3595 mapDwarfRegsToLLVMRegs(VEEHFlavour0Dwarf2L, VEEHFlavour0Dwarf2LSize, true);
3596 break;
3597 }
3598 switch (DwarfFlavour) {
3599 default:
3600 llvm_unreachable("Unknown DWARF flavour");
3601 case 0:
3602 mapLLVMRegsToDwarfRegs(VEDwarfFlavour0L2Dwarf, VEDwarfFlavour0L2DwarfSize, false);
3603 break;
3604 }
3605 switch (EHFlavour) {
3606 default:
3607 llvm_unreachable("Unknown DWARF flavour");
3608 case 0:
3609 mapLLVMRegsToDwarfRegs(VEEHFlavour0L2Dwarf, VEEHFlavour0L2DwarfSize, true);
3610 break;
3611 }
3612}
3613
3614static const MCPhysReg CSR_SaveList[] = { VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, 0 };
3615static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000ff0, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x1fffe000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
3616static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
3617static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000800, };
3618static const MCPhysReg CSR_preserve_all_SaveList[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7, VE::SX8, VE::SX9, VE::SX10, VE::SX11, VE::SX12, VE::SX13, VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20, VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27, VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34, VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41, VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48, VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55, VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, VE::VM12, VE::VM13, VE::VM14, VE::VM15, 0 };
3619static const uint32_t CSR_preserve_all_RegMask[] = { 0xf8000000, 0xfbffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xf9ffffff, 0xffffffff, 0xffffffff, 0x0007ffff, };
3620
3621
3622ArrayRef<const uint32_t *> VEGenRegisterInfo::getRegMasks() const {
3623 static const uint32_t *const Masks[] = {
3624 CSR_RegMask,
3625 CSR_NoRegs_RegMask,
3626 CSR_preserve_all_RegMask,
3627 };
3628 return ArrayRef(Masks);
3629}
3630
3631bool VEGenRegisterInfo::
3632isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3633 return
3634 false;
3635}
3636
3637bool VEGenRegisterInfo::
3638isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3639 return
3640 false;
3641}
3642
3643bool VEGenRegisterInfo::
3644isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
3645 return
3646 false;
3647}
3648
3649bool VEGenRegisterInfo::
3650isConstantPhysReg(MCRegister PhysReg) const {
3651 return
3652 PhysReg == VE::VM0 ||
3653 PhysReg == VE::VMP0 ||
3654 false;
3655}
3656
3657ArrayRef<const char *> VEGenRegisterInfo::getRegMaskNames() const {
3658 static const char *Names[] = {
3659 "CSR",
3660 "CSR_NoRegs",
3661 "CSR_preserve_all",
3662 };
3663 return ArrayRef(Names);
3664}
3665
3666const VEFrameLowering *
3667VEGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
3668 return static_cast<const VEFrameLowering *>(
3669 MF.getSubtarget().getFrameLowering());
3670}
3671
3672} // end namespace llvm
3673
3674#endif // GET_REGINFO_TARGET_DESC
3675
3676