1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace VE {
15enum {
16 FeatureEnableVPU = 0,
17 NumSubtargetFeatures = 1
18};
19} // end namespace VE
20} // end namespace llvm
21
22#endif // GET_SUBTARGETINFO_ENUM
23
24
25#ifdef GET_SUBTARGETINFO_MACRO
26GET_SUBTARGETINFO_MACRO(EnableVPU, false, enableVPU)
27#undef GET_SUBTARGETINFO_MACRO
28#endif // GET_SUBTARGETINFO_MACRO
29
30
31#ifdef GET_SUBTARGETINFO_MC_DESC
32#undef GET_SUBTARGETINFO_MC_DESC
33
34namespace llvm {
35// Sorted (by key) array of values for CPU features.
36extern const llvm::SubtargetFeatureKV VEFeatureKV[] = {
37 { "vpu", "Enable the VPU", VE::FeatureEnableVPU, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
38};
39
40#ifdef DBGFIELD
41#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
42#endif
43#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
44#define DBGFIELD(x) x,
45#else
46#define DBGFIELD(x)
47#endif
48
49// ===============================================================
50// Data tables for the new per-operand machine model.
51
52// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
53extern const llvm::MCWriteProcResEntry VEWriteProcResTable[] = {
54 { 0, 0, 0 }, // Invalid
55}; // VEWriteProcResTable
56
57// {Cycles, WriteResourceID}
58extern const llvm::MCWriteLatencyEntry VEWriteLatencyTable[] = {
59 { 0, 0}, // Invalid
60}; // VEWriteLatencyTable
61
62// {UseIdx, WriteResourceID, Cycles}
63extern const llvm::MCReadAdvanceEntry VEReadAdvanceTable[] = {
64 {0, 0, 0}, // Invalid
65}; // VEReadAdvanceTable
66
67#undef DBGFIELD
68
69static const llvm::MCSchedModel NoSchedModel = {
70 MCSchedModel::DefaultIssueWidth,
71 MCSchedModel::DefaultMicroOpBufferSize,
72 MCSchedModel::DefaultLoopMicroOpBufferSize,
73 MCSchedModel::DefaultLoadLatency,
74 MCSchedModel::DefaultHighLatency,
75 MCSchedModel::DefaultMispredictPenalty,
76 false, // PostRAScheduler
77 false, // CompleteModel
78 false, // EnableIntervals
79 0, // Processor ID
80 nullptr, nullptr, 0, 0, // No instruction-level machine model.
81 nullptr, // No Itinerary
82 nullptr // No extra processor descriptor
83};
84
85// Sorted (by key) array of values for CPU subtype.
86extern const llvm::SubtargetSubTypeKV VESubTypeKV[] = {
87 { "generic", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
88};
89
90namespace VE_MC {
91unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
92 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
93 // Don't know how to resolve this scheduling class.
94 return 0;
95}
96} // end namespace VE_MC
97
98struct VEGenMCSubtargetInfo : public MCSubtargetInfo {
99 VEGenMCSubtargetInfo(const Triple &TT,
100 StringRef CPU, StringRef TuneCPU, StringRef FS,
101 ArrayRef<SubtargetFeatureKV> PF,
102 ArrayRef<SubtargetSubTypeKV> PD,
103 const MCWriteProcResEntry *WPR,
104 const MCWriteLatencyEntry *WL,
105 const MCReadAdvanceEntry *RA, const InstrStage *IS,
106 const unsigned *OC, const unsigned *FP) :
107 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
108 WPR, WL, RA, IS, OC, FP) { }
109
110 unsigned resolveVariantSchedClass(unsigned SchedClass,
111 const MCInst *MI, const MCInstrInfo *MCII,
112 unsigned CPUID) const override {
113 return VE_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
114 }
115};
116
117static inline MCSubtargetInfo *createVEMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
118 return new VEGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, VEFeatureKV, VESubTypeKV,
119 VEWriteProcResTable, VEWriteLatencyTable, VEReadAdvanceTable,
120 nullptr, nullptr, nullptr);
121}
122
123} // end namespace llvm
124
125#endif // GET_SUBTARGETINFO_MC_DESC
126
127
128#ifdef GET_SUBTARGETINFO_TARGET_DESC
129#undef GET_SUBTARGETINFO_TARGET_DESC
130
131#include "llvm/Support/Debug.h"
132#include "llvm/Support/raw_ostream.h"
133
134// ParseSubtargetFeatures - Parses features string setting specified
135// subtarget options.
136void llvm::VESubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
137 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
138 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
139 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
140 InitMCProcessorInfo(CPU, TuneCPU, FS);
141 const FeatureBitset &Bits = getFeatureBits();
142 if (Bits[VE::FeatureEnableVPU]) EnableVPU = true;
143}
144#endif // GET_SUBTARGETINFO_TARGET_DESC
145
146
147#ifdef GET_SUBTARGETINFO_HEADER
148#undef GET_SUBTARGETINFO_HEADER
149
150namespace llvm {
151class DFAPacketizer;
152namespace VE_MC {
153unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
154} // end namespace VE_MC
155
156struct VEGenSubtargetInfo : public TargetSubtargetInfo {
157 explicit VEGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
158public:
159 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
160 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
161 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
162};
163} // end namespace llvm
164
165#endif // GET_SUBTARGETINFO_HEADER
166
167
168#ifdef GET_SUBTARGETINFO_CTOR
169#undef GET_SUBTARGETINFO_CTOR
170
171#include "llvm/CodeGen/TargetSchedule.h"
172
173namespace llvm {
174extern const llvm::SubtargetFeatureKV VEFeatureKV[];
175extern const llvm::SubtargetSubTypeKV VESubTypeKV[];
176extern const llvm::MCWriteProcResEntry VEWriteProcResTable[];
177extern const llvm::MCWriteLatencyEntry VEWriteLatencyTable[];
178extern const llvm::MCReadAdvanceEntry VEReadAdvanceTable[];
179VEGenSubtargetInfo::VEGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
180 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(VEFeatureKV, 1), ArrayRef(VESubTypeKV, 1),
181 VEWriteProcResTable, VEWriteLatencyTable, VEReadAdvanceTable,
182 nullptr, nullptr, nullptr) {}
183
184unsigned VEGenSubtargetInfo
185::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
186 report_fatal_error("Expected a variant SchedClass");
187} // VEGenSubtargetInfo::resolveSchedClass
188
189unsigned VEGenSubtargetInfo
190::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
191 return VE_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
192} // VEGenSubtargetInfo::resolveVariantSchedClass
193
194} // end namespace llvm
195
196#endif // GET_SUBTARGETINFO_CTOR
197
198
199#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
200#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
201
202#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
203
204
205#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
206#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
207
208#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
209
210