1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm {
12
13namespace WebAssembly {
14 enum {
15 PHI = 0,
16 INLINEASM = 1,
17 INLINEASM_BR = 2,
18 CFI_INSTRUCTION = 3,
19 EH_LABEL = 4,
20 GC_LABEL = 5,
21 ANNOTATION_LABEL = 6,
22 KILL = 7,
23 EXTRACT_SUBREG = 8,
24 INSERT_SUBREG = 9,
25 IMPLICIT_DEF = 10,
26 SUBREG_TO_REG = 11,
27 COPY_TO_REGCLASS = 12,
28 DBG_VALUE = 13,
29 DBG_VALUE_LIST = 14,
30 DBG_INSTR_REF = 15,
31 DBG_PHI = 16,
32 DBG_LABEL = 17,
33 REG_SEQUENCE = 18,
34 COPY = 19,
35 BUNDLE = 20,
36 LIFETIME_START = 21,
37 LIFETIME_END = 22,
38 PSEUDO_PROBE = 23,
39 ARITH_FENCE = 24,
40 STACKMAP = 25,
41 FENTRY_CALL = 26,
42 PATCHPOINT = 27,
43 LOAD_STACK_GUARD = 28,
44 PREALLOCATED_SETUP = 29,
45 PREALLOCATED_ARG = 30,
46 STATEPOINT = 31,
47 LOCAL_ESCAPE = 32,
48 FAULTING_OP = 33,
49 PATCHABLE_OP = 34,
50 PATCHABLE_FUNCTION_ENTER = 35,
51 PATCHABLE_RET = 36,
52 PATCHABLE_FUNCTION_EXIT = 37,
53 PATCHABLE_TAIL_CALL = 38,
54 PATCHABLE_EVENT_CALL = 39,
55 PATCHABLE_TYPED_EVENT_CALL = 40,
56 ICALL_BRANCH_FUNNEL = 41,
57 MEMBARRIER = 42,
58 JUMP_TABLE_DEBUG_INFO = 43,
59 CONVERGENCECTRL_ENTRY = 44,
60 CONVERGENCECTRL_ANCHOR = 45,
61 CONVERGENCECTRL_LOOP = 46,
62 CONVERGENCECTRL_GLUE = 47,
63 G_ASSERT_SEXT = 48,
64 G_ASSERT_ZEXT = 49,
65 G_ASSERT_ALIGN = 50,
66 G_ADD = 51,
67 G_SUB = 52,
68 G_MUL = 53,
69 G_SDIV = 54,
70 G_UDIV = 55,
71 G_SREM = 56,
72 G_UREM = 57,
73 G_SDIVREM = 58,
74 G_UDIVREM = 59,
75 G_AND = 60,
76 G_OR = 61,
77 G_XOR = 62,
78 G_IMPLICIT_DEF = 63,
79 G_PHI = 64,
80 G_FRAME_INDEX = 65,
81 G_GLOBAL_VALUE = 66,
82 G_PTRAUTH_GLOBAL_VALUE = 67,
83 G_CONSTANT_POOL = 68,
84 G_EXTRACT = 69,
85 G_UNMERGE_VALUES = 70,
86 G_INSERT = 71,
87 G_MERGE_VALUES = 72,
88 G_BUILD_VECTOR = 73,
89 G_BUILD_VECTOR_TRUNC = 74,
90 G_CONCAT_VECTORS = 75,
91 G_PTRTOINT = 76,
92 G_INTTOPTR = 77,
93 G_BITCAST = 78,
94 G_FREEZE = 79,
95 G_CONSTANT_FOLD_BARRIER = 80,
96 G_INTRINSIC_FPTRUNC_ROUND = 81,
97 G_INTRINSIC_TRUNC = 82,
98 G_INTRINSIC_ROUND = 83,
99 G_INTRINSIC_LRINT = 84,
100 G_INTRINSIC_LLRINT = 85,
101 G_INTRINSIC_ROUNDEVEN = 86,
102 G_READCYCLECOUNTER = 87,
103 G_READSTEADYCOUNTER = 88,
104 G_LOAD = 89,
105 G_SEXTLOAD = 90,
106 G_ZEXTLOAD = 91,
107 G_INDEXED_LOAD = 92,
108 G_INDEXED_SEXTLOAD = 93,
109 G_INDEXED_ZEXTLOAD = 94,
110 G_STORE = 95,
111 G_INDEXED_STORE = 96,
112 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97,
113 G_ATOMIC_CMPXCHG = 98,
114 G_ATOMICRMW_XCHG = 99,
115 G_ATOMICRMW_ADD = 100,
116 G_ATOMICRMW_SUB = 101,
117 G_ATOMICRMW_AND = 102,
118 G_ATOMICRMW_NAND = 103,
119 G_ATOMICRMW_OR = 104,
120 G_ATOMICRMW_XOR = 105,
121 G_ATOMICRMW_MAX = 106,
122 G_ATOMICRMW_MIN = 107,
123 G_ATOMICRMW_UMAX = 108,
124 G_ATOMICRMW_UMIN = 109,
125 G_ATOMICRMW_FADD = 110,
126 G_ATOMICRMW_FSUB = 111,
127 G_ATOMICRMW_FMAX = 112,
128 G_ATOMICRMW_FMIN = 113,
129 G_ATOMICRMW_UINC_WRAP = 114,
130 G_ATOMICRMW_UDEC_WRAP = 115,
131 G_FENCE = 116,
132 G_PREFETCH = 117,
133 G_BRCOND = 118,
134 G_BRINDIRECT = 119,
135 G_INVOKE_REGION_START = 120,
136 G_INTRINSIC = 121,
137 G_INTRINSIC_W_SIDE_EFFECTS = 122,
138 G_INTRINSIC_CONVERGENT = 123,
139 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124,
140 G_ANYEXT = 125,
141 G_TRUNC = 126,
142 G_CONSTANT = 127,
143 G_FCONSTANT = 128,
144 G_VASTART = 129,
145 G_VAARG = 130,
146 G_SEXT = 131,
147 G_SEXT_INREG = 132,
148 G_ZEXT = 133,
149 G_SHL = 134,
150 G_LSHR = 135,
151 G_ASHR = 136,
152 G_FSHL = 137,
153 G_FSHR = 138,
154 G_ROTR = 139,
155 G_ROTL = 140,
156 G_ICMP = 141,
157 G_FCMP = 142,
158 G_SCMP = 143,
159 G_UCMP = 144,
160 G_SELECT = 145,
161 G_UADDO = 146,
162 G_UADDE = 147,
163 G_USUBO = 148,
164 G_USUBE = 149,
165 G_SADDO = 150,
166 G_SADDE = 151,
167 G_SSUBO = 152,
168 G_SSUBE = 153,
169 G_UMULO = 154,
170 G_SMULO = 155,
171 G_UMULH = 156,
172 G_SMULH = 157,
173 G_UADDSAT = 158,
174 G_SADDSAT = 159,
175 G_USUBSAT = 160,
176 G_SSUBSAT = 161,
177 G_USHLSAT = 162,
178 G_SSHLSAT = 163,
179 G_SMULFIX = 164,
180 G_UMULFIX = 165,
181 G_SMULFIXSAT = 166,
182 G_UMULFIXSAT = 167,
183 G_SDIVFIX = 168,
184 G_UDIVFIX = 169,
185 G_SDIVFIXSAT = 170,
186 G_UDIVFIXSAT = 171,
187 G_FADD = 172,
188 G_FSUB = 173,
189 G_FMUL = 174,
190 G_FMA = 175,
191 G_FMAD = 176,
192 G_FDIV = 177,
193 G_FREM = 178,
194 G_FPOW = 179,
195 G_FPOWI = 180,
196 G_FEXP = 181,
197 G_FEXP2 = 182,
198 G_FEXP10 = 183,
199 G_FLOG = 184,
200 G_FLOG2 = 185,
201 G_FLOG10 = 186,
202 G_FLDEXP = 187,
203 G_FFREXP = 188,
204 G_FNEG = 189,
205 G_FPEXT = 190,
206 G_FPTRUNC = 191,
207 G_FPTOSI = 192,
208 G_FPTOUI = 193,
209 G_SITOFP = 194,
210 G_UITOFP = 195,
211 G_FABS = 196,
212 G_FCOPYSIGN = 197,
213 G_IS_FPCLASS = 198,
214 G_FCANONICALIZE = 199,
215 G_FMINNUM = 200,
216 G_FMAXNUM = 201,
217 G_FMINNUM_IEEE = 202,
218 G_FMAXNUM_IEEE = 203,
219 G_FMINIMUM = 204,
220 G_FMAXIMUM = 205,
221 G_GET_FPENV = 206,
222 G_SET_FPENV = 207,
223 G_RESET_FPENV = 208,
224 G_GET_FPMODE = 209,
225 G_SET_FPMODE = 210,
226 G_RESET_FPMODE = 211,
227 G_PTR_ADD = 212,
228 G_PTRMASK = 213,
229 G_SMIN = 214,
230 G_SMAX = 215,
231 G_UMIN = 216,
232 G_UMAX = 217,
233 G_ABS = 218,
234 G_LROUND = 219,
235 G_LLROUND = 220,
236 G_BR = 221,
237 G_BRJT = 222,
238 G_VSCALE = 223,
239 G_INSERT_SUBVECTOR = 224,
240 G_EXTRACT_SUBVECTOR = 225,
241 G_INSERT_VECTOR_ELT = 226,
242 G_EXTRACT_VECTOR_ELT = 227,
243 G_SHUFFLE_VECTOR = 228,
244 G_SPLAT_VECTOR = 229,
245 G_VECTOR_COMPRESS = 230,
246 G_CTTZ = 231,
247 G_CTTZ_ZERO_UNDEF = 232,
248 G_CTLZ = 233,
249 G_CTLZ_ZERO_UNDEF = 234,
250 G_CTPOP = 235,
251 G_BSWAP = 236,
252 G_BITREVERSE = 237,
253 G_FCEIL = 238,
254 G_FCOS = 239,
255 G_FSIN = 240,
256 G_FTAN = 241,
257 G_FACOS = 242,
258 G_FASIN = 243,
259 G_FATAN = 244,
260 G_FCOSH = 245,
261 G_FSINH = 246,
262 G_FTANH = 247,
263 G_FSQRT = 248,
264 G_FFLOOR = 249,
265 G_FRINT = 250,
266 G_FNEARBYINT = 251,
267 G_ADDRSPACE_CAST = 252,
268 G_BLOCK_ADDR = 253,
269 G_JUMP_TABLE = 254,
270 G_DYN_STACKALLOC = 255,
271 G_STACKSAVE = 256,
272 G_STACKRESTORE = 257,
273 G_STRICT_FADD = 258,
274 G_STRICT_FSUB = 259,
275 G_STRICT_FMUL = 260,
276 G_STRICT_FDIV = 261,
277 G_STRICT_FREM = 262,
278 G_STRICT_FMA = 263,
279 G_STRICT_FSQRT = 264,
280 G_STRICT_FLDEXP = 265,
281 G_READ_REGISTER = 266,
282 G_WRITE_REGISTER = 267,
283 G_MEMCPY = 268,
284 G_MEMCPY_INLINE = 269,
285 G_MEMMOVE = 270,
286 G_MEMSET = 271,
287 G_BZERO = 272,
288 G_TRAP = 273,
289 G_DEBUGTRAP = 274,
290 G_UBSANTRAP = 275,
291 G_VECREDUCE_SEQ_FADD = 276,
292 G_VECREDUCE_SEQ_FMUL = 277,
293 G_VECREDUCE_FADD = 278,
294 G_VECREDUCE_FMUL = 279,
295 G_VECREDUCE_FMAX = 280,
296 G_VECREDUCE_FMIN = 281,
297 G_VECREDUCE_FMAXIMUM = 282,
298 G_VECREDUCE_FMINIMUM = 283,
299 G_VECREDUCE_ADD = 284,
300 G_VECREDUCE_MUL = 285,
301 G_VECREDUCE_AND = 286,
302 G_VECREDUCE_OR = 287,
303 G_VECREDUCE_XOR = 288,
304 G_VECREDUCE_SMAX = 289,
305 G_VECREDUCE_SMIN = 290,
306 G_VECREDUCE_UMAX = 291,
307 G_VECREDUCE_UMIN = 292,
308 G_SBFX = 293,
309 G_UBFX = 294,
310 CALL_PARAMS = 295,
311 CALL_PARAMS_S = 296,
312 CALL_RESULTS = 297,
313 CALL_RESULTS_S = 298,
314 CATCHRET = 299,
315 CATCHRET_S = 300,
316 CLEANUPRET = 301,
317 CLEANUPRET_S = 302,
318 COMPILER_FENCE = 303,
319 COMPILER_FENCE_S = 304,
320 RET_CALL_RESULTS = 305,
321 RET_CALL_RESULTS_S = 306,
322 ABS_F16x8 = 307,
323 ABS_F16x8_S = 308,
324 ABS_F32 = 309,
325 ABS_F32_S = 310,
326 ABS_F32x4 = 311,
327 ABS_F32x4_S = 312,
328 ABS_F64 = 313,
329 ABS_F64_S = 314,
330 ABS_F64x2 = 315,
331 ABS_F64x2_S = 316,
332 ABS_I16x8 = 317,
333 ABS_I16x8_S = 318,
334 ABS_I32x4 = 319,
335 ABS_I32x4_S = 320,
336 ABS_I64x2 = 321,
337 ABS_I64x2_S = 322,
338 ABS_I8x16 = 323,
339 ABS_I8x16_S = 324,
340 ADD_F16x8 = 325,
341 ADD_F16x8_S = 326,
342 ADD_F32 = 327,
343 ADD_F32_S = 328,
344 ADD_F32x4 = 329,
345 ADD_F32x4_S = 330,
346 ADD_F64 = 331,
347 ADD_F64_S = 332,
348 ADD_F64x2 = 333,
349 ADD_F64x2_S = 334,
350 ADD_I16x8 = 335,
351 ADD_I16x8_S = 336,
352 ADD_I32 = 337,
353 ADD_I32_S = 338,
354 ADD_I32x4 = 339,
355 ADD_I32x4_S = 340,
356 ADD_I64 = 341,
357 ADD_I64_S = 342,
358 ADD_I64x2 = 343,
359 ADD_I64x2_S = 344,
360 ADD_I8x16 = 345,
361 ADD_I8x16_S = 346,
362 ADD_SAT_S_I16x8 = 347,
363 ADD_SAT_S_I16x8_S = 348,
364 ADD_SAT_S_I8x16 = 349,
365 ADD_SAT_S_I8x16_S = 350,
366 ADD_SAT_U_I16x8 = 351,
367 ADD_SAT_U_I16x8_S = 352,
368 ADD_SAT_U_I8x16 = 353,
369 ADD_SAT_U_I8x16_S = 354,
370 ADJCALLSTACKDOWN = 355,
371 ADJCALLSTACKDOWN_S = 356,
372 ADJCALLSTACKUP = 357,
373 ADJCALLSTACKUP_S = 358,
374 ALLTRUE_I16x8 = 359,
375 ALLTRUE_I16x8_S = 360,
376 ALLTRUE_I32x4 = 361,
377 ALLTRUE_I32x4_S = 362,
378 ALLTRUE_I64x2 = 363,
379 ALLTRUE_I64x2_S = 364,
380 ALLTRUE_I8x16 = 365,
381 ALLTRUE_I8x16_S = 366,
382 AND = 367,
383 ANDNOT = 368,
384 ANDNOT_S = 369,
385 AND_I32 = 370,
386 AND_I32_S = 371,
387 AND_I64 = 372,
388 AND_I64_S = 373,
389 AND_S = 374,
390 ANYTRUE = 375,
391 ANYTRUE_S = 376,
392 ARGUMENT_exnref = 377,
393 ARGUMENT_exnref_S = 378,
394 ARGUMENT_externref = 379,
395 ARGUMENT_externref_S = 380,
396 ARGUMENT_f32 = 381,
397 ARGUMENT_f32_S = 382,
398 ARGUMENT_f64 = 383,
399 ARGUMENT_f64_S = 384,
400 ARGUMENT_funcref = 385,
401 ARGUMENT_funcref_S = 386,
402 ARGUMENT_i32 = 387,
403 ARGUMENT_i32_S = 388,
404 ARGUMENT_i64 = 389,
405 ARGUMENT_i64_S = 390,
406 ARGUMENT_v16i8 = 391,
407 ARGUMENT_v16i8_S = 392,
408 ARGUMENT_v2f64 = 393,
409 ARGUMENT_v2f64_S = 394,
410 ARGUMENT_v2i64 = 395,
411 ARGUMENT_v2i64_S = 396,
412 ARGUMENT_v4f32 = 397,
413 ARGUMENT_v4f32_S = 398,
414 ARGUMENT_v4i32 = 399,
415 ARGUMENT_v4i32_S = 400,
416 ARGUMENT_v8f16 = 401,
417 ARGUMENT_v8f16_S = 402,
418 ARGUMENT_v8i16 = 403,
419 ARGUMENT_v8i16_S = 404,
420 ATOMIC_FENCE = 405,
421 ATOMIC_FENCE_S = 406,
422 ATOMIC_LOAD16_U_I32_A32 = 407,
423 ATOMIC_LOAD16_U_I32_A32_S = 408,
424 ATOMIC_LOAD16_U_I32_A64 = 409,
425 ATOMIC_LOAD16_U_I32_A64_S = 410,
426 ATOMIC_LOAD16_U_I64_A32 = 411,
427 ATOMIC_LOAD16_U_I64_A32_S = 412,
428 ATOMIC_LOAD16_U_I64_A64 = 413,
429 ATOMIC_LOAD16_U_I64_A64_S = 414,
430 ATOMIC_LOAD32_U_I64_A32 = 415,
431 ATOMIC_LOAD32_U_I64_A32_S = 416,
432 ATOMIC_LOAD32_U_I64_A64 = 417,
433 ATOMIC_LOAD32_U_I64_A64_S = 418,
434 ATOMIC_LOAD8_U_I32_A32 = 419,
435 ATOMIC_LOAD8_U_I32_A32_S = 420,
436 ATOMIC_LOAD8_U_I32_A64 = 421,
437 ATOMIC_LOAD8_U_I32_A64_S = 422,
438 ATOMIC_LOAD8_U_I64_A32 = 423,
439 ATOMIC_LOAD8_U_I64_A32_S = 424,
440 ATOMIC_LOAD8_U_I64_A64 = 425,
441 ATOMIC_LOAD8_U_I64_A64_S = 426,
442 ATOMIC_LOAD_I32_A32 = 427,
443 ATOMIC_LOAD_I32_A32_S = 428,
444 ATOMIC_LOAD_I32_A64 = 429,
445 ATOMIC_LOAD_I32_A64_S = 430,
446 ATOMIC_LOAD_I64_A32 = 431,
447 ATOMIC_LOAD_I64_A32_S = 432,
448 ATOMIC_LOAD_I64_A64 = 433,
449 ATOMIC_LOAD_I64_A64_S = 434,
450 ATOMIC_RMW16_U_ADD_I32_A32 = 435,
451 ATOMIC_RMW16_U_ADD_I32_A32_S = 436,
452 ATOMIC_RMW16_U_ADD_I32_A64 = 437,
453 ATOMIC_RMW16_U_ADD_I32_A64_S = 438,
454 ATOMIC_RMW16_U_ADD_I64_A32 = 439,
455 ATOMIC_RMW16_U_ADD_I64_A32_S = 440,
456 ATOMIC_RMW16_U_ADD_I64_A64 = 441,
457 ATOMIC_RMW16_U_ADD_I64_A64_S = 442,
458 ATOMIC_RMW16_U_AND_I32_A32 = 443,
459 ATOMIC_RMW16_U_AND_I32_A32_S = 444,
460 ATOMIC_RMW16_U_AND_I32_A64 = 445,
461 ATOMIC_RMW16_U_AND_I32_A64_S = 446,
462 ATOMIC_RMW16_U_AND_I64_A32 = 447,
463 ATOMIC_RMW16_U_AND_I64_A32_S = 448,
464 ATOMIC_RMW16_U_AND_I64_A64 = 449,
465 ATOMIC_RMW16_U_AND_I64_A64_S = 450,
466 ATOMIC_RMW16_U_CMPXCHG_I32_A32 = 451,
467 ATOMIC_RMW16_U_CMPXCHG_I32_A32_S = 452,
468 ATOMIC_RMW16_U_CMPXCHG_I32_A64 = 453,
469 ATOMIC_RMW16_U_CMPXCHG_I32_A64_S = 454,
470 ATOMIC_RMW16_U_CMPXCHG_I64_A32 = 455,
471 ATOMIC_RMW16_U_CMPXCHG_I64_A32_S = 456,
472 ATOMIC_RMW16_U_CMPXCHG_I64_A64 = 457,
473 ATOMIC_RMW16_U_CMPXCHG_I64_A64_S = 458,
474 ATOMIC_RMW16_U_OR_I32_A32 = 459,
475 ATOMIC_RMW16_U_OR_I32_A32_S = 460,
476 ATOMIC_RMW16_U_OR_I32_A64 = 461,
477 ATOMIC_RMW16_U_OR_I32_A64_S = 462,
478 ATOMIC_RMW16_U_OR_I64_A32 = 463,
479 ATOMIC_RMW16_U_OR_I64_A32_S = 464,
480 ATOMIC_RMW16_U_OR_I64_A64 = 465,
481 ATOMIC_RMW16_U_OR_I64_A64_S = 466,
482 ATOMIC_RMW16_U_SUB_I32_A32 = 467,
483 ATOMIC_RMW16_U_SUB_I32_A32_S = 468,
484 ATOMIC_RMW16_U_SUB_I32_A64 = 469,
485 ATOMIC_RMW16_U_SUB_I32_A64_S = 470,
486 ATOMIC_RMW16_U_SUB_I64_A32 = 471,
487 ATOMIC_RMW16_U_SUB_I64_A32_S = 472,
488 ATOMIC_RMW16_U_SUB_I64_A64 = 473,
489 ATOMIC_RMW16_U_SUB_I64_A64_S = 474,
490 ATOMIC_RMW16_U_XCHG_I32_A32 = 475,
491 ATOMIC_RMW16_U_XCHG_I32_A32_S = 476,
492 ATOMIC_RMW16_U_XCHG_I32_A64 = 477,
493 ATOMIC_RMW16_U_XCHG_I32_A64_S = 478,
494 ATOMIC_RMW16_U_XCHG_I64_A32 = 479,
495 ATOMIC_RMW16_U_XCHG_I64_A32_S = 480,
496 ATOMIC_RMW16_U_XCHG_I64_A64 = 481,
497 ATOMIC_RMW16_U_XCHG_I64_A64_S = 482,
498 ATOMIC_RMW16_U_XOR_I32_A32 = 483,
499 ATOMIC_RMW16_U_XOR_I32_A32_S = 484,
500 ATOMIC_RMW16_U_XOR_I32_A64 = 485,
501 ATOMIC_RMW16_U_XOR_I32_A64_S = 486,
502 ATOMIC_RMW16_U_XOR_I64_A32 = 487,
503 ATOMIC_RMW16_U_XOR_I64_A32_S = 488,
504 ATOMIC_RMW16_U_XOR_I64_A64 = 489,
505 ATOMIC_RMW16_U_XOR_I64_A64_S = 490,
506 ATOMIC_RMW32_U_ADD_I64_A32 = 491,
507 ATOMIC_RMW32_U_ADD_I64_A32_S = 492,
508 ATOMIC_RMW32_U_ADD_I64_A64 = 493,
509 ATOMIC_RMW32_U_ADD_I64_A64_S = 494,
510 ATOMIC_RMW32_U_AND_I64_A32 = 495,
511 ATOMIC_RMW32_U_AND_I64_A32_S = 496,
512 ATOMIC_RMW32_U_AND_I64_A64 = 497,
513 ATOMIC_RMW32_U_AND_I64_A64_S = 498,
514 ATOMIC_RMW32_U_CMPXCHG_I64_A32 = 499,
515 ATOMIC_RMW32_U_CMPXCHG_I64_A32_S = 500,
516 ATOMIC_RMW32_U_CMPXCHG_I64_A64 = 501,
517 ATOMIC_RMW32_U_CMPXCHG_I64_A64_S = 502,
518 ATOMIC_RMW32_U_OR_I64_A32 = 503,
519 ATOMIC_RMW32_U_OR_I64_A32_S = 504,
520 ATOMIC_RMW32_U_OR_I64_A64 = 505,
521 ATOMIC_RMW32_U_OR_I64_A64_S = 506,
522 ATOMIC_RMW32_U_SUB_I64_A32 = 507,
523 ATOMIC_RMW32_U_SUB_I64_A32_S = 508,
524 ATOMIC_RMW32_U_SUB_I64_A64 = 509,
525 ATOMIC_RMW32_U_SUB_I64_A64_S = 510,
526 ATOMIC_RMW32_U_XCHG_I64_A32 = 511,
527 ATOMIC_RMW32_U_XCHG_I64_A32_S = 512,
528 ATOMIC_RMW32_U_XCHG_I64_A64 = 513,
529 ATOMIC_RMW32_U_XCHG_I64_A64_S = 514,
530 ATOMIC_RMW32_U_XOR_I64_A32 = 515,
531 ATOMIC_RMW32_U_XOR_I64_A32_S = 516,
532 ATOMIC_RMW32_U_XOR_I64_A64 = 517,
533 ATOMIC_RMW32_U_XOR_I64_A64_S = 518,
534 ATOMIC_RMW8_U_ADD_I32_A32 = 519,
535 ATOMIC_RMW8_U_ADD_I32_A32_S = 520,
536 ATOMIC_RMW8_U_ADD_I32_A64 = 521,
537 ATOMIC_RMW8_U_ADD_I32_A64_S = 522,
538 ATOMIC_RMW8_U_ADD_I64_A32 = 523,
539 ATOMIC_RMW8_U_ADD_I64_A32_S = 524,
540 ATOMIC_RMW8_U_ADD_I64_A64 = 525,
541 ATOMIC_RMW8_U_ADD_I64_A64_S = 526,
542 ATOMIC_RMW8_U_AND_I32_A32 = 527,
543 ATOMIC_RMW8_U_AND_I32_A32_S = 528,
544 ATOMIC_RMW8_U_AND_I32_A64 = 529,
545 ATOMIC_RMW8_U_AND_I32_A64_S = 530,
546 ATOMIC_RMW8_U_AND_I64_A32 = 531,
547 ATOMIC_RMW8_U_AND_I64_A32_S = 532,
548 ATOMIC_RMW8_U_AND_I64_A64 = 533,
549 ATOMIC_RMW8_U_AND_I64_A64_S = 534,
550 ATOMIC_RMW8_U_CMPXCHG_I32_A32 = 535,
551 ATOMIC_RMW8_U_CMPXCHG_I32_A32_S = 536,
552 ATOMIC_RMW8_U_CMPXCHG_I32_A64 = 537,
553 ATOMIC_RMW8_U_CMPXCHG_I32_A64_S = 538,
554 ATOMIC_RMW8_U_CMPXCHG_I64_A32 = 539,
555 ATOMIC_RMW8_U_CMPXCHG_I64_A32_S = 540,
556 ATOMIC_RMW8_U_CMPXCHG_I64_A64 = 541,
557 ATOMIC_RMW8_U_CMPXCHG_I64_A64_S = 542,
558 ATOMIC_RMW8_U_OR_I32_A32 = 543,
559 ATOMIC_RMW8_U_OR_I32_A32_S = 544,
560 ATOMIC_RMW8_U_OR_I32_A64 = 545,
561 ATOMIC_RMW8_U_OR_I32_A64_S = 546,
562 ATOMIC_RMW8_U_OR_I64_A32 = 547,
563 ATOMIC_RMW8_U_OR_I64_A32_S = 548,
564 ATOMIC_RMW8_U_OR_I64_A64 = 549,
565 ATOMIC_RMW8_U_OR_I64_A64_S = 550,
566 ATOMIC_RMW8_U_SUB_I32_A32 = 551,
567 ATOMIC_RMW8_U_SUB_I32_A32_S = 552,
568 ATOMIC_RMW8_U_SUB_I32_A64 = 553,
569 ATOMIC_RMW8_U_SUB_I32_A64_S = 554,
570 ATOMIC_RMW8_U_SUB_I64_A32 = 555,
571 ATOMIC_RMW8_U_SUB_I64_A32_S = 556,
572 ATOMIC_RMW8_U_SUB_I64_A64 = 557,
573 ATOMIC_RMW8_U_SUB_I64_A64_S = 558,
574 ATOMIC_RMW8_U_XCHG_I32_A32 = 559,
575 ATOMIC_RMW8_U_XCHG_I32_A32_S = 560,
576 ATOMIC_RMW8_U_XCHG_I32_A64 = 561,
577 ATOMIC_RMW8_U_XCHG_I32_A64_S = 562,
578 ATOMIC_RMW8_U_XCHG_I64_A32 = 563,
579 ATOMIC_RMW8_U_XCHG_I64_A32_S = 564,
580 ATOMIC_RMW8_U_XCHG_I64_A64 = 565,
581 ATOMIC_RMW8_U_XCHG_I64_A64_S = 566,
582 ATOMIC_RMW8_U_XOR_I32_A32 = 567,
583 ATOMIC_RMW8_U_XOR_I32_A32_S = 568,
584 ATOMIC_RMW8_U_XOR_I32_A64 = 569,
585 ATOMIC_RMW8_U_XOR_I32_A64_S = 570,
586 ATOMIC_RMW8_U_XOR_I64_A32 = 571,
587 ATOMIC_RMW8_U_XOR_I64_A32_S = 572,
588 ATOMIC_RMW8_U_XOR_I64_A64 = 573,
589 ATOMIC_RMW8_U_XOR_I64_A64_S = 574,
590 ATOMIC_RMW_ADD_I32_A32 = 575,
591 ATOMIC_RMW_ADD_I32_A32_S = 576,
592 ATOMIC_RMW_ADD_I32_A64 = 577,
593 ATOMIC_RMW_ADD_I32_A64_S = 578,
594 ATOMIC_RMW_ADD_I64_A32 = 579,
595 ATOMIC_RMW_ADD_I64_A32_S = 580,
596 ATOMIC_RMW_ADD_I64_A64 = 581,
597 ATOMIC_RMW_ADD_I64_A64_S = 582,
598 ATOMIC_RMW_AND_I32_A32 = 583,
599 ATOMIC_RMW_AND_I32_A32_S = 584,
600 ATOMIC_RMW_AND_I32_A64 = 585,
601 ATOMIC_RMW_AND_I32_A64_S = 586,
602 ATOMIC_RMW_AND_I64_A32 = 587,
603 ATOMIC_RMW_AND_I64_A32_S = 588,
604 ATOMIC_RMW_AND_I64_A64 = 589,
605 ATOMIC_RMW_AND_I64_A64_S = 590,
606 ATOMIC_RMW_CMPXCHG_I32_A32 = 591,
607 ATOMIC_RMW_CMPXCHG_I32_A32_S = 592,
608 ATOMIC_RMW_CMPXCHG_I32_A64 = 593,
609 ATOMIC_RMW_CMPXCHG_I32_A64_S = 594,
610 ATOMIC_RMW_CMPXCHG_I64_A32 = 595,
611 ATOMIC_RMW_CMPXCHG_I64_A32_S = 596,
612 ATOMIC_RMW_CMPXCHG_I64_A64 = 597,
613 ATOMIC_RMW_CMPXCHG_I64_A64_S = 598,
614 ATOMIC_RMW_OR_I32_A32 = 599,
615 ATOMIC_RMW_OR_I32_A32_S = 600,
616 ATOMIC_RMW_OR_I32_A64 = 601,
617 ATOMIC_RMW_OR_I32_A64_S = 602,
618 ATOMIC_RMW_OR_I64_A32 = 603,
619 ATOMIC_RMW_OR_I64_A32_S = 604,
620 ATOMIC_RMW_OR_I64_A64 = 605,
621 ATOMIC_RMW_OR_I64_A64_S = 606,
622 ATOMIC_RMW_SUB_I32_A32 = 607,
623 ATOMIC_RMW_SUB_I32_A32_S = 608,
624 ATOMIC_RMW_SUB_I32_A64 = 609,
625 ATOMIC_RMW_SUB_I32_A64_S = 610,
626 ATOMIC_RMW_SUB_I64_A32 = 611,
627 ATOMIC_RMW_SUB_I64_A32_S = 612,
628 ATOMIC_RMW_SUB_I64_A64 = 613,
629 ATOMIC_RMW_SUB_I64_A64_S = 614,
630 ATOMIC_RMW_XCHG_I32_A32 = 615,
631 ATOMIC_RMW_XCHG_I32_A32_S = 616,
632 ATOMIC_RMW_XCHG_I32_A64 = 617,
633 ATOMIC_RMW_XCHG_I32_A64_S = 618,
634 ATOMIC_RMW_XCHG_I64_A32 = 619,
635 ATOMIC_RMW_XCHG_I64_A32_S = 620,
636 ATOMIC_RMW_XCHG_I64_A64 = 621,
637 ATOMIC_RMW_XCHG_I64_A64_S = 622,
638 ATOMIC_RMW_XOR_I32_A32 = 623,
639 ATOMIC_RMW_XOR_I32_A32_S = 624,
640 ATOMIC_RMW_XOR_I32_A64 = 625,
641 ATOMIC_RMW_XOR_I32_A64_S = 626,
642 ATOMIC_RMW_XOR_I64_A32 = 627,
643 ATOMIC_RMW_XOR_I64_A32_S = 628,
644 ATOMIC_RMW_XOR_I64_A64 = 629,
645 ATOMIC_RMW_XOR_I64_A64_S = 630,
646 ATOMIC_STORE16_I32_A32 = 631,
647 ATOMIC_STORE16_I32_A32_S = 632,
648 ATOMIC_STORE16_I32_A64 = 633,
649 ATOMIC_STORE16_I32_A64_S = 634,
650 ATOMIC_STORE16_I64_A32 = 635,
651 ATOMIC_STORE16_I64_A32_S = 636,
652 ATOMIC_STORE16_I64_A64 = 637,
653 ATOMIC_STORE16_I64_A64_S = 638,
654 ATOMIC_STORE32_I64_A32 = 639,
655 ATOMIC_STORE32_I64_A32_S = 640,
656 ATOMIC_STORE32_I64_A64 = 641,
657 ATOMIC_STORE32_I64_A64_S = 642,
658 ATOMIC_STORE8_I32_A32 = 643,
659 ATOMIC_STORE8_I32_A32_S = 644,
660 ATOMIC_STORE8_I32_A64 = 645,
661 ATOMIC_STORE8_I32_A64_S = 646,
662 ATOMIC_STORE8_I64_A32 = 647,
663 ATOMIC_STORE8_I64_A32_S = 648,
664 ATOMIC_STORE8_I64_A64 = 649,
665 ATOMIC_STORE8_I64_A64_S = 650,
666 ATOMIC_STORE_I32_A32 = 651,
667 ATOMIC_STORE_I32_A32_S = 652,
668 ATOMIC_STORE_I32_A64 = 653,
669 ATOMIC_STORE_I32_A64_S = 654,
670 ATOMIC_STORE_I64_A32 = 655,
671 ATOMIC_STORE_I64_A32_S = 656,
672 ATOMIC_STORE_I64_A64 = 657,
673 ATOMIC_STORE_I64_A64_S = 658,
674 AVGR_U_I16x8 = 659,
675 AVGR_U_I16x8_S = 660,
676 AVGR_U_I8x16 = 661,
677 AVGR_U_I8x16_S = 662,
678 BITMASK_I16x8 = 663,
679 BITMASK_I16x8_S = 664,
680 BITMASK_I32x4 = 665,
681 BITMASK_I32x4_S = 666,
682 BITMASK_I64x2 = 667,
683 BITMASK_I64x2_S = 668,
684 BITMASK_I8x16 = 669,
685 BITMASK_I8x16_S = 670,
686 BITSELECT = 671,
687 BITSELECT_S = 672,
688 BLOCK = 673,
689 BLOCK_S = 674,
690 BR = 675,
691 BR_IF = 676,
692 BR_IF_S = 677,
693 BR_S = 678,
694 BR_TABLE_I32 = 679,
695 BR_TABLE_I32_S = 680,
696 BR_TABLE_I64 = 681,
697 BR_TABLE_I64_S = 682,
698 BR_UNLESS = 683,
699 BR_UNLESS_S = 684,
700 CALL = 685,
701 CALL_INDIRECT = 686,
702 CALL_INDIRECT_S = 687,
703 CALL_S = 688,
704 CATCH = 689,
705 CATCH_ALL = 690,
706 CATCH_ALL_S = 691,
707 CATCH_S = 692,
708 CEIL_F16x8 = 693,
709 CEIL_F16x8_S = 694,
710 CEIL_F32 = 695,
711 CEIL_F32_S = 696,
712 CEIL_F32x4 = 697,
713 CEIL_F32x4_S = 698,
714 CEIL_F64 = 699,
715 CEIL_F64_S = 700,
716 CEIL_F64x2 = 701,
717 CEIL_F64x2_S = 702,
718 CLZ_I32 = 703,
719 CLZ_I32_S = 704,
720 CLZ_I64 = 705,
721 CLZ_I64_S = 706,
722 CONST_F32 = 707,
723 CONST_F32_S = 708,
724 CONST_F64 = 709,
725 CONST_F64_S = 710,
726 CONST_I32 = 711,
727 CONST_I32_S = 712,
728 CONST_I64 = 713,
729 CONST_I64_S = 714,
730 CONST_V128_F32x4 = 715,
731 CONST_V128_F32x4_S = 716,
732 CONST_V128_F64x2 = 717,
733 CONST_V128_F64x2_S = 718,
734 CONST_V128_I16x8 = 719,
735 CONST_V128_I16x8_S = 720,
736 CONST_V128_I32x4 = 721,
737 CONST_V128_I32x4_S = 722,
738 CONST_V128_I64x2 = 723,
739 CONST_V128_I64x2_S = 724,
740 CONST_V128_I8x16 = 725,
741 CONST_V128_I8x16_S = 726,
742 COPYSIGN_F32 = 727,
743 COPYSIGN_F32_S = 728,
744 COPYSIGN_F64 = 729,
745 COPYSIGN_F64_S = 730,
746 COPY_EXNREF = 731,
747 COPY_EXNREF_S = 732,
748 COPY_EXTERNREF = 733,
749 COPY_EXTERNREF_S = 734,
750 COPY_F32 = 735,
751 COPY_F32_S = 736,
752 COPY_F64 = 737,
753 COPY_F64_S = 738,
754 COPY_FUNCREF = 739,
755 COPY_FUNCREF_S = 740,
756 COPY_I32 = 741,
757 COPY_I32_S = 742,
758 COPY_I64 = 743,
759 COPY_I64_S = 744,
760 COPY_V128 = 745,
761 COPY_V128_S = 746,
762 CTZ_I32 = 747,
763 CTZ_I32_S = 748,
764 CTZ_I64 = 749,
765 CTZ_I64_S = 750,
766 DEBUG_UNREACHABLE = 751,
767 DEBUG_UNREACHABLE_S = 752,
768 DELEGATE = 753,
769 DELEGATE_S = 754,
770 DIV_F16x8 = 755,
771 DIV_F16x8_S = 756,
772 DIV_F32 = 757,
773 DIV_F32_S = 758,
774 DIV_F32x4 = 759,
775 DIV_F32x4_S = 760,
776 DIV_F64 = 761,
777 DIV_F64_S = 762,
778 DIV_F64x2 = 763,
779 DIV_F64x2_S = 764,
780 DIV_S_I32 = 765,
781 DIV_S_I32_S = 766,
782 DIV_S_I64 = 767,
783 DIV_S_I64_S = 768,
784 DIV_U_I32 = 769,
785 DIV_U_I32_S = 770,
786 DIV_U_I64 = 771,
787 DIV_U_I64_S = 772,
788 DOT = 773,
789 DOT_S = 774,
790 DROP_EXNREF = 775,
791 DROP_EXNREF_S = 776,
792 DROP_EXTERNREF = 777,
793 DROP_EXTERNREF_S = 778,
794 DROP_F32 = 779,
795 DROP_F32_S = 780,
796 DROP_F64 = 781,
797 DROP_F64_S = 782,
798 DROP_FUNCREF = 783,
799 DROP_FUNCREF_S = 784,
800 DROP_I32 = 785,
801 DROP_I32_S = 786,
802 DROP_I64 = 787,
803 DROP_I64_S = 788,
804 DROP_V128 = 789,
805 DROP_V128_S = 790,
806 ELSE = 791,
807 ELSE_S = 792,
808 END = 793,
809 END_BLOCK = 794,
810 END_BLOCK_S = 795,
811 END_FUNCTION = 796,
812 END_FUNCTION_S = 797,
813 END_IF = 798,
814 END_IF_S = 799,
815 END_LOOP = 800,
816 END_LOOP_S = 801,
817 END_S = 802,
818 END_TRY = 803,
819 END_TRY_S = 804,
820 EQZ_I32 = 805,
821 EQZ_I32_S = 806,
822 EQZ_I64 = 807,
823 EQZ_I64_S = 808,
824 EQ_F16x8 = 809,
825 EQ_F16x8_S = 810,
826 EQ_F32 = 811,
827 EQ_F32_S = 812,
828 EQ_F32x4 = 813,
829 EQ_F32x4_S = 814,
830 EQ_F64 = 815,
831 EQ_F64_S = 816,
832 EQ_F64x2 = 817,
833 EQ_F64x2_S = 818,
834 EQ_I16x8 = 819,
835 EQ_I16x8_S = 820,
836 EQ_I32 = 821,
837 EQ_I32_S = 822,
838 EQ_I32x4 = 823,
839 EQ_I32x4_S = 824,
840 EQ_I64 = 825,
841 EQ_I64_S = 826,
842 EQ_I64x2 = 827,
843 EQ_I64x2_S = 828,
844 EQ_I8x16 = 829,
845 EQ_I8x16_S = 830,
846 EXTMUL_HIGH_S_I16x8 = 831,
847 EXTMUL_HIGH_S_I16x8_S = 832,
848 EXTMUL_HIGH_S_I32x4 = 833,
849 EXTMUL_HIGH_S_I32x4_S = 834,
850 EXTMUL_HIGH_S_I64x2 = 835,
851 EXTMUL_HIGH_S_I64x2_S = 836,
852 EXTMUL_HIGH_U_I16x8 = 837,
853 EXTMUL_HIGH_U_I16x8_S = 838,
854 EXTMUL_HIGH_U_I32x4 = 839,
855 EXTMUL_HIGH_U_I32x4_S = 840,
856 EXTMUL_HIGH_U_I64x2 = 841,
857 EXTMUL_HIGH_U_I64x2_S = 842,
858 EXTMUL_LOW_S_I16x8 = 843,
859 EXTMUL_LOW_S_I16x8_S = 844,
860 EXTMUL_LOW_S_I32x4 = 845,
861 EXTMUL_LOW_S_I32x4_S = 846,
862 EXTMUL_LOW_S_I64x2 = 847,
863 EXTMUL_LOW_S_I64x2_S = 848,
864 EXTMUL_LOW_U_I16x8 = 849,
865 EXTMUL_LOW_U_I16x8_S = 850,
866 EXTMUL_LOW_U_I32x4 = 851,
867 EXTMUL_LOW_U_I32x4_S = 852,
868 EXTMUL_LOW_U_I64x2 = 853,
869 EXTMUL_LOW_U_I64x2_S = 854,
870 EXTRACT_LANE_F16x8 = 855,
871 EXTRACT_LANE_F16x8_S = 856,
872 EXTRACT_LANE_F32x4 = 857,
873 EXTRACT_LANE_F32x4_S = 858,
874 EXTRACT_LANE_F64x2 = 859,
875 EXTRACT_LANE_F64x2_S = 860,
876 EXTRACT_LANE_I16x8_s = 861,
877 EXTRACT_LANE_I16x8_s_S = 862,
878 EXTRACT_LANE_I16x8_u = 863,
879 EXTRACT_LANE_I16x8_u_S = 864,
880 EXTRACT_LANE_I32x4 = 865,
881 EXTRACT_LANE_I32x4_S = 866,
882 EXTRACT_LANE_I64x2 = 867,
883 EXTRACT_LANE_I64x2_S = 868,
884 EXTRACT_LANE_I8x16_s = 869,
885 EXTRACT_LANE_I8x16_s_S = 870,
886 EXTRACT_LANE_I8x16_u = 871,
887 EXTRACT_LANE_I8x16_u_S = 872,
888 F32_CONVERT_S_I32 = 873,
889 F32_CONVERT_S_I32_S = 874,
890 F32_CONVERT_S_I64 = 875,
891 F32_CONVERT_S_I64_S = 876,
892 F32_CONVERT_U_I32 = 877,
893 F32_CONVERT_U_I32_S = 878,
894 F32_CONVERT_U_I64 = 879,
895 F32_CONVERT_U_I64_S = 880,
896 F32_DEMOTE_F64 = 881,
897 F32_DEMOTE_F64_S = 882,
898 F32_REINTERPRET_I32 = 883,
899 F32_REINTERPRET_I32_S = 884,
900 F64_CONVERT_S_I32 = 885,
901 F64_CONVERT_S_I32_S = 886,
902 F64_CONVERT_S_I64 = 887,
903 F64_CONVERT_S_I64_S = 888,
904 F64_CONVERT_U_I32 = 889,
905 F64_CONVERT_U_I32_S = 890,
906 F64_CONVERT_U_I64 = 891,
907 F64_CONVERT_U_I64_S = 892,
908 F64_PROMOTE_F32 = 893,
909 F64_PROMOTE_F32_S = 894,
910 F64_REINTERPRET_I64 = 895,
911 F64_REINTERPRET_I64_S = 896,
912 FALLTHROUGH_RETURN = 897,
913 FALLTHROUGH_RETURN_S = 898,
914 FLOOR_F16x8 = 899,
915 FLOOR_F16x8_S = 900,
916 FLOOR_F32 = 901,
917 FLOOR_F32_S = 902,
918 FLOOR_F32x4 = 903,
919 FLOOR_F32x4_S = 904,
920 FLOOR_F64 = 905,
921 FLOOR_F64_S = 906,
922 FLOOR_F64x2 = 907,
923 FLOOR_F64x2_S = 908,
924 FP_TO_SINT_I32_F32 = 909,
925 FP_TO_SINT_I32_F32_S = 910,
926 FP_TO_SINT_I32_F64 = 911,
927 FP_TO_SINT_I32_F64_S = 912,
928 FP_TO_SINT_I64_F32 = 913,
929 FP_TO_SINT_I64_F32_S = 914,
930 FP_TO_SINT_I64_F64 = 915,
931 FP_TO_SINT_I64_F64_S = 916,
932 FP_TO_UINT_I32_F32 = 917,
933 FP_TO_UINT_I32_F32_S = 918,
934 FP_TO_UINT_I32_F64 = 919,
935 FP_TO_UINT_I32_F64_S = 920,
936 FP_TO_UINT_I64_F32 = 921,
937 FP_TO_UINT_I64_F32_S = 922,
938 FP_TO_UINT_I64_F64 = 923,
939 FP_TO_UINT_I64_F64_S = 924,
940 GE_F16x8 = 925,
941 GE_F16x8_S = 926,
942 GE_F32 = 927,
943 GE_F32_S = 928,
944 GE_F32x4 = 929,
945 GE_F32x4_S = 930,
946 GE_F64 = 931,
947 GE_F64_S = 932,
948 GE_F64x2 = 933,
949 GE_F64x2_S = 934,
950 GE_S_I16x8 = 935,
951 GE_S_I16x8_S = 936,
952 GE_S_I32 = 937,
953 GE_S_I32_S = 938,
954 GE_S_I32x4 = 939,
955 GE_S_I32x4_S = 940,
956 GE_S_I64 = 941,
957 GE_S_I64_S = 942,
958 GE_S_I64x2 = 943,
959 GE_S_I64x2_S = 944,
960 GE_S_I8x16 = 945,
961 GE_S_I8x16_S = 946,
962 GE_U_I16x8 = 947,
963 GE_U_I16x8_S = 948,
964 GE_U_I32 = 949,
965 GE_U_I32_S = 950,
966 GE_U_I32x4 = 951,
967 GE_U_I32x4_S = 952,
968 GE_U_I64 = 953,
969 GE_U_I64_S = 954,
970 GE_U_I8x16 = 955,
971 GE_U_I8x16_S = 956,
972 GLOBAL_GET_EXNREF = 957,
973 GLOBAL_GET_EXNREF_S = 958,
974 GLOBAL_GET_EXTERNREF = 959,
975 GLOBAL_GET_EXTERNREF_S = 960,
976 GLOBAL_GET_F32 = 961,
977 GLOBAL_GET_F32_S = 962,
978 GLOBAL_GET_F64 = 963,
979 GLOBAL_GET_F64_S = 964,
980 GLOBAL_GET_FUNCREF = 965,
981 GLOBAL_GET_FUNCREF_S = 966,
982 GLOBAL_GET_I32 = 967,
983 GLOBAL_GET_I32_S = 968,
984 GLOBAL_GET_I64 = 969,
985 GLOBAL_GET_I64_S = 970,
986 GLOBAL_GET_V128 = 971,
987 GLOBAL_GET_V128_S = 972,
988 GLOBAL_SET_EXNREF = 973,
989 GLOBAL_SET_EXNREF_S = 974,
990 GLOBAL_SET_EXTERNREF = 975,
991 GLOBAL_SET_EXTERNREF_S = 976,
992 GLOBAL_SET_F32 = 977,
993 GLOBAL_SET_F32_S = 978,
994 GLOBAL_SET_F64 = 979,
995 GLOBAL_SET_F64_S = 980,
996 GLOBAL_SET_FUNCREF = 981,
997 GLOBAL_SET_FUNCREF_S = 982,
998 GLOBAL_SET_I32 = 983,
999 GLOBAL_SET_I32_S = 984,
1000 GLOBAL_SET_I64 = 985,
1001 GLOBAL_SET_I64_S = 986,
1002 GLOBAL_SET_V128 = 987,
1003 GLOBAL_SET_V128_S = 988,
1004 GT_F16x8 = 989,
1005 GT_F16x8_S = 990,
1006 GT_F32 = 991,
1007 GT_F32_S = 992,
1008 GT_F32x4 = 993,
1009 GT_F32x4_S = 994,
1010 GT_F64 = 995,
1011 GT_F64_S = 996,
1012 GT_F64x2 = 997,
1013 GT_F64x2_S = 998,
1014 GT_S_I16x8 = 999,
1015 GT_S_I16x8_S = 1000,
1016 GT_S_I32 = 1001,
1017 GT_S_I32_S = 1002,
1018 GT_S_I32x4 = 1003,
1019 GT_S_I32x4_S = 1004,
1020 GT_S_I64 = 1005,
1021 GT_S_I64_S = 1006,
1022 GT_S_I64x2 = 1007,
1023 GT_S_I64x2_S = 1008,
1024 GT_S_I8x16 = 1009,
1025 GT_S_I8x16_S = 1010,
1026 GT_U_I16x8 = 1011,
1027 GT_U_I16x8_S = 1012,
1028 GT_U_I32 = 1013,
1029 GT_U_I32_S = 1014,
1030 GT_U_I32x4 = 1015,
1031 GT_U_I32x4_S = 1016,
1032 GT_U_I64 = 1017,
1033 GT_U_I64_S = 1018,
1034 GT_U_I8x16 = 1019,
1035 GT_U_I8x16_S = 1020,
1036 I32_EXTEND16_S_I32 = 1021,
1037 I32_EXTEND16_S_I32_S = 1022,
1038 I32_EXTEND8_S_I32 = 1023,
1039 I32_EXTEND8_S_I32_S = 1024,
1040 I32_REINTERPRET_F32 = 1025,
1041 I32_REINTERPRET_F32_S = 1026,
1042 I32_TRUNC_S_F32 = 1027,
1043 I32_TRUNC_S_F32_S = 1028,
1044 I32_TRUNC_S_F64 = 1029,
1045 I32_TRUNC_S_F64_S = 1030,
1046 I32_TRUNC_S_SAT_F32 = 1031,
1047 I32_TRUNC_S_SAT_F32_S = 1032,
1048 I32_TRUNC_S_SAT_F64 = 1033,
1049 I32_TRUNC_S_SAT_F64_S = 1034,
1050 I32_TRUNC_U_F32 = 1035,
1051 I32_TRUNC_U_F32_S = 1036,
1052 I32_TRUNC_U_F64 = 1037,
1053 I32_TRUNC_U_F64_S = 1038,
1054 I32_TRUNC_U_SAT_F32 = 1039,
1055 I32_TRUNC_U_SAT_F32_S = 1040,
1056 I32_TRUNC_U_SAT_F64 = 1041,
1057 I32_TRUNC_U_SAT_F64_S = 1042,
1058 I32_WRAP_I64 = 1043,
1059 I32_WRAP_I64_S = 1044,
1060 I64_EXTEND16_S_I64 = 1045,
1061 I64_EXTEND16_S_I64_S = 1046,
1062 I64_EXTEND32_S_I64 = 1047,
1063 I64_EXTEND32_S_I64_S = 1048,
1064 I64_EXTEND8_S_I64 = 1049,
1065 I64_EXTEND8_S_I64_S = 1050,
1066 I64_EXTEND_S_I32 = 1051,
1067 I64_EXTEND_S_I32_S = 1052,
1068 I64_EXTEND_U_I32 = 1053,
1069 I64_EXTEND_U_I32_S = 1054,
1070 I64_REINTERPRET_F64 = 1055,
1071 I64_REINTERPRET_F64_S = 1056,
1072 I64_TRUNC_S_F32 = 1057,
1073 I64_TRUNC_S_F32_S = 1058,
1074 I64_TRUNC_S_F64 = 1059,
1075 I64_TRUNC_S_F64_S = 1060,
1076 I64_TRUNC_S_SAT_F32 = 1061,
1077 I64_TRUNC_S_SAT_F32_S = 1062,
1078 I64_TRUNC_S_SAT_F64 = 1063,
1079 I64_TRUNC_S_SAT_F64_S = 1064,
1080 I64_TRUNC_U_F32 = 1065,
1081 I64_TRUNC_U_F32_S = 1066,
1082 I64_TRUNC_U_F64 = 1067,
1083 I64_TRUNC_U_F64_S = 1068,
1084 I64_TRUNC_U_SAT_F32 = 1069,
1085 I64_TRUNC_U_SAT_F32_S = 1070,
1086 I64_TRUNC_U_SAT_F64 = 1071,
1087 I64_TRUNC_U_SAT_F64_S = 1072,
1088 IF = 1073,
1089 IF_S = 1074,
1090 LANESELECT_I16x8 = 1075,
1091 LANESELECT_I16x8_S = 1076,
1092 LANESELECT_I32x4 = 1077,
1093 LANESELECT_I32x4_S = 1078,
1094 LANESELECT_I64x2 = 1079,
1095 LANESELECT_I64x2_S = 1080,
1096 LANESELECT_I8x16 = 1081,
1097 LANESELECT_I8x16_S = 1082,
1098 LE_F16x8 = 1083,
1099 LE_F16x8_S = 1084,
1100 LE_F32 = 1085,
1101 LE_F32_S = 1086,
1102 LE_F32x4 = 1087,
1103 LE_F32x4_S = 1088,
1104 LE_F64 = 1089,
1105 LE_F64_S = 1090,
1106 LE_F64x2 = 1091,
1107 LE_F64x2_S = 1092,
1108 LE_S_I16x8 = 1093,
1109 LE_S_I16x8_S = 1094,
1110 LE_S_I32 = 1095,
1111 LE_S_I32_S = 1096,
1112 LE_S_I32x4 = 1097,
1113 LE_S_I32x4_S = 1098,
1114 LE_S_I64 = 1099,
1115 LE_S_I64_S = 1100,
1116 LE_S_I64x2 = 1101,
1117 LE_S_I64x2_S = 1102,
1118 LE_S_I8x16 = 1103,
1119 LE_S_I8x16_S = 1104,
1120 LE_U_I16x8 = 1105,
1121 LE_U_I16x8_S = 1106,
1122 LE_U_I32 = 1107,
1123 LE_U_I32_S = 1108,
1124 LE_U_I32x4 = 1109,
1125 LE_U_I32x4_S = 1110,
1126 LE_U_I64 = 1111,
1127 LE_U_I64_S = 1112,
1128 LE_U_I8x16 = 1113,
1129 LE_U_I8x16_S = 1114,
1130 LOAD16_SPLAT_A32 = 1115,
1131 LOAD16_SPLAT_A32_S = 1116,
1132 LOAD16_SPLAT_A64 = 1117,
1133 LOAD16_SPLAT_A64_S = 1118,
1134 LOAD16_S_I32_A32 = 1119,
1135 LOAD16_S_I32_A32_S = 1120,
1136 LOAD16_S_I32_A64 = 1121,
1137 LOAD16_S_I32_A64_S = 1122,
1138 LOAD16_S_I64_A32 = 1123,
1139 LOAD16_S_I64_A32_S = 1124,
1140 LOAD16_S_I64_A64 = 1125,
1141 LOAD16_S_I64_A64_S = 1126,
1142 LOAD16_U_I32_A32 = 1127,
1143 LOAD16_U_I32_A32_S = 1128,
1144 LOAD16_U_I32_A64 = 1129,
1145 LOAD16_U_I32_A64_S = 1130,
1146 LOAD16_U_I64_A32 = 1131,
1147 LOAD16_U_I64_A32_S = 1132,
1148 LOAD16_U_I64_A64 = 1133,
1149 LOAD16_U_I64_A64_S = 1134,
1150 LOAD32_SPLAT_A32 = 1135,
1151 LOAD32_SPLAT_A32_S = 1136,
1152 LOAD32_SPLAT_A64 = 1137,
1153 LOAD32_SPLAT_A64_S = 1138,
1154 LOAD32_S_I64_A32 = 1139,
1155 LOAD32_S_I64_A32_S = 1140,
1156 LOAD32_S_I64_A64 = 1141,
1157 LOAD32_S_I64_A64_S = 1142,
1158 LOAD32_U_I64_A32 = 1143,
1159 LOAD32_U_I64_A32_S = 1144,
1160 LOAD32_U_I64_A64 = 1145,
1161 LOAD32_U_I64_A64_S = 1146,
1162 LOAD64_SPLAT_A32 = 1147,
1163 LOAD64_SPLAT_A32_S = 1148,
1164 LOAD64_SPLAT_A64 = 1149,
1165 LOAD64_SPLAT_A64_S = 1150,
1166 LOAD8_SPLAT_A32 = 1151,
1167 LOAD8_SPLAT_A32_S = 1152,
1168 LOAD8_SPLAT_A64 = 1153,
1169 LOAD8_SPLAT_A64_S = 1154,
1170 LOAD8_S_I32_A32 = 1155,
1171 LOAD8_S_I32_A32_S = 1156,
1172 LOAD8_S_I32_A64 = 1157,
1173 LOAD8_S_I32_A64_S = 1158,
1174 LOAD8_S_I64_A32 = 1159,
1175 LOAD8_S_I64_A32_S = 1160,
1176 LOAD8_S_I64_A64 = 1161,
1177 LOAD8_S_I64_A64_S = 1162,
1178 LOAD8_U_I32_A32 = 1163,
1179 LOAD8_U_I32_A32_S = 1164,
1180 LOAD8_U_I32_A64 = 1165,
1181 LOAD8_U_I32_A64_S = 1166,
1182 LOAD8_U_I64_A32 = 1167,
1183 LOAD8_U_I64_A32_S = 1168,
1184 LOAD8_U_I64_A64 = 1169,
1185 LOAD8_U_I64_A64_S = 1170,
1186 LOAD_EXTEND_S_I16x8_A32 = 1171,
1187 LOAD_EXTEND_S_I16x8_A32_S = 1172,
1188 LOAD_EXTEND_S_I16x8_A64 = 1173,
1189 LOAD_EXTEND_S_I16x8_A64_S = 1174,
1190 LOAD_EXTEND_S_I32x4_A32 = 1175,
1191 LOAD_EXTEND_S_I32x4_A32_S = 1176,
1192 LOAD_EXTEND_S_I32x4_A64 = 1177,
1193 LOAD_EXTEND_S_I32x4_A64_S = 1178,
1194 LOAD_EXTEND_S_I64x2_A32 = 1179,
1195 LOAD_EXTEND_S_I64x2_A32_S = 1180,
1196 LOAD_EXTEND_S_I64x2_A64 = 1181,
1197 LOAD_EXTEND_S_I64x2_A64_S = 1182,
1198 LOAD_EXTEND_U_I16x8_A32 = 1183,
1199 LOAD_EXTEND_U_I16x8_A32_S = 1184,
1200 LOAD_EXTEND_U_I16x8_A64 = 1185,
1201 LOAD_EXTEND_U_I16x8_A64_S = 1186,
1202 LOAD_EXTEND_U_I32x4_A32 = 1187,
1203 LOAD_EXTEND_U_I32x4_A32_S = 1188,
1204 LOAD_EXTEND_U_I32x4_A64 = 1189,
1205 LOAD_EXTEND_U_I32x4_A64_S = 1190,
1206 LOAD_EXTEND_U_I64x2_A32 = 1191,
1207 LOAD_EXTEND_U_I64x2_A32_S = 1192,
1208 LOAD_EXTEND_U_I64x2_A64 = 1193,
1209 LOAD_EXTEND_U_I64x2_A64_S = 1194,
1210 LOAD_F16_F32_A32 = 1195,
1211 LOAD_F16_F32_A32_S = 1196,
1212 LOAD_F16_F32_A64 = 1197,
1213 LOAD_F16_F32_A64_S = 1198,
1214 LOAD_F32_A32 = 1199,
1215 LOAD_F32_A32_S = 1200,
1216 LOAD_F32_A64 = 1201,
1217 LOAD_F32_A64_S = 1202,
1218 LOAD_F64_A32 = 1203,
1219 LOAD_F64_A32_S = 1204,
1220 LOAD_F64_A64 = 1205,
1221 LOAD_F64_A64_S = 1206,
1222 LOAD_I32_A32 = 1207,
1223 LOAD_I32_A32_S = 1208,
1224 LOAD_I32_A64 = 1209,
1225 LOAD_I32_A64_S = 1210,
1226 LOAD_I64_A32 = 1211,
1227 LOAD_I64_A32_S = 1212,
1228 LOAD_I64_A64 = 1213,
1229 LOAD_I64_A64_S = 1214,
1230 LOAD_LANE_I16x8_A32 = 1215,
1231 LOAD_LANE_I16x8_A32_S = 1216,
1232 LOAD_LANE_I16x8_A64 = 1217,
1233 LOAD_LANE_I16x8_A64_S = 1218,
1234 LOAD_LANE_I32x4_A32 = 1219,
1235 LOAD_LANE_I32x4_A32_S = 1220,
1236 LOAD_LANE_I32x4_A64 = 1221,
1237 LOAD_LANE_I32x4_A64_S = 1222,
1238 LOAD_LANE_I64x2_A32 = 1223,
1239 LOAD_LANE_I64x2_A32_S = 1224,
1240 LOAD_LANE_I64x2_A64 = 1225,
1241 LOAD_LANE_I64x2_A64_S = 1226,
1242 LOAD_LANE_I8x16_A32 = 1227,
1243 LOAD_LANE_I8x16_A32_S = 1228,
1244 LOAD_LANE_I8x16_A64 = 1229,
1245 LOAD_LANE_I8x16_A64_S = 1230,
1246 LOAD_V128_A32 = 1231,
1247 LOAD_V128_A32_S = 1232,
1248 LOAD_V128_A64 = 1233,
1249 LOAD_V128_A64_S = 1234,
1250 LOAD_ZERO_I32x4_A32 = 1235,
1251 LOAD_ZERO_I32x4_A32_S = 1236,
1252 LOAD_ZERO_I32x4_A64 = 1237,
1253 LOAD_ZERO_I32x4_A64_S = 1238,
1254 LOAD_ZERO_I64x2_A32 = 1239,
1255 LOAD_ZERO_I64x2_A32_S = 1240,
1256 LOAD_ZERO_I64x2_A64 = 1241,
1257 LOAD_ZERO_I64x2_A64_S = 1242,
1258 LOCAL_GET_EXNREF = 1243,
1259 LOCAL_GET_EXNREF_S = 1244,
1260 LOCAL_GET_EXTERNREF = 1245,
1261 LOCAL_GET_EXTERNREF_S = 1246,
1262 LOCAL_GET_F32 = 1247,
1263 LOCAL_GET_F32_S = 1248,
1264 LOCAL_GET_F64 = 1249,
1265 LOCAL_GET_F64_S = 1250,
1266 LOCAL_GET_FUNCREF = 1251,
1267 LOCAL_GET_FUNCREF_S = 1252,
1268 LOCAL_GET_I32 = 1253,
1269 LOCAL_GET_I32_S = 1254,
1270 LOCAL_GET_I64 = 1255,
1271 LOCAL_GET_I64_S = 1256,
1272 LOCAL_GET_V128 = 1257,
1273 LOCAL_GET_V128_S = 1258,
1274 LOCAL_SET_EXNREF = 1259,
1275 LOCAL_SET_EXNREF_S = 1260,
1276 LOCAL_SET_EXTERNREF = 1261,
1277 LOCAL_SET_EXTERNREF_S = 1262,
1278 LOCAL_SET_F32 = 1263,
1279 LOCAL_SET_F32_S = 1264,
1280 LOCAL_SET_F64 = 1265,
1281 LOCAL_SET_F64_S = 1266,
1282 LOCAL_SET_FUNCREF = 1267,
1283 LOCAL_SET_FUNCREF_S = 1268,
1284 LOCAL_SET_I32 = 1269,
1285 LOCAL_SET_I32_S = 1270,
1286 LOCAL_SET_I64 = 1271,
1287 LOCAL_SET_I64_S = 1272,
1288 LOCAL_SET_V128 = 1273,
1289 LOCAL_SET_V128_S = 1274,
1290 LOCAL_TEE_EXNREF = 1275,
1291 LOCAL_TEE_EXNREF_S = 1276,
1292 LOCAL_TEE_EXTERNREF = 1277,
1293 LOCAL_TEE_EXTERNREF_S = 1278,
1294 LOCAL_TEE_F32 = 1279,
1295 LOCAL_TEE_F32_S = 1280,
1296 LOCAL_TEE_F64 = 1281,
1297 LOCAL_TEE_F64_S = 1282,
1298 LOCAL_TEE_FUNCREF = 1283,
1299 LOCAL_TEE_FUNCREF_S = 1284,
1300 LOCAL_TEE_I32 = 1285,
1301 LOCAL_TEE_I32_S = 1286,
1302 LOCAL_TEE_I64 = 1287,
1303 LOCAL_TEE_I64_S = 1288,
1304 LOCAL_TEE_V128 = 1289,
1305 LOCAL_TEE_V128_S = 1290,
1306 LOOP = 1291,
1307 LOOP_S = 1292,
1308 LT_F16x8 = 1293,
1309 LT_F16x8_S = 1294,
1310 LT_F32 = 1295,
1311 LT_F32_S = 1296,
1312 LT_F32x4 = 1297,
1313 LT_F32x4_S = 1298,
1314 LT_F64 = 1299,
1315 LT_F64_S = 1300,
1316 LT_F64x2 = 1301,
1317 LT_F64x2_S = 1302,
1318 LT_S_I16x8 = 1303,
1319 LT_S_I16x8_S = 1304,
1320 LT_S_I32 = 1305,
1321 LT_S_I32_S = 1306,
1322 LT_S_I32x4 = 1307,
1323 LT_S_I32x4_S = 1308,
1324 LT_S_I64 = 1309,
1325 LT_S_I64_S = 1310,
1326 LT_S_I64x2 = 1311,
1327 LT_S_I64x2_S = 1312,
1328 LT_S_I8x16 = 1313,
1329 LT_S_I8x16_S = 1314,
1330 LT_U_I16x8 = 1315,
1331 LT_U_I16x8_S = 1316,
1332 LT_U_I32 = 1317,
1333 LT_U_I32_S = 1318,
1334 LT_U_I32x4 = 1319,
1335 LT_U_I32x4_S = 1320,
1336 LT_U_I64 = 1321,
1337 LT_U_I64_S = 1322,
1338 LT_U_I8x16 = 1323,
1339 LT_U_I8x16_S = 1324,
1340 MADD_F16x8 = 1325,
1341 MADD_F16x8_S = 1326,
1342 MADD_F32x4 = 1327,
1343 MADD_F32x4_S = 1328,
1344 MADD_F64x2 = 1329,
1345 MADD_F64x2_S = 1330,
1346 MAX_F16x8 = 1331,
1347 MAX_F16x8_S = 1332,
1348 MAX_F32 = 1333,
1349 MAX_F32_S = 1334,
1350 MAX_F32x4 = 1335,
1351 MAX_F32x4_S = 1336,
1352 MAX_F64 = 1337,
1353 MAX_F64_S = 1338,
1354 MAX_F64x2 = 1339,
1355 MAX_F64x2_S = 1340,
1356 MAX_S_I16x8 = 1341,
1357 MAX_S_I16x8_S = 1342,
1358 MAX_S_I32x4 = 1343,
1359 MAX_S_I32x4_S = 1344,
1360 MAX_S_I8x16 = 1345,
1361 MAX_S_I8x16_S = 1346,
1362 MAX_U_I16x8 = 1347,
1363 MAX_U_I16x8_S = 1348,
1364 MAX_U_I32x4 = 1349,
1365 MAX_U_I32x4_S = 1350,
1366 MAX_U_I8x16 = 1351,
1367 MAX_U_I8x16_S = 1352,
1368 MEMORY_ATOMIC_NOTIFY_A32 = 1353,
1369 MEMORY_ATOMIC_NOTIFY_A32_S = 1354,
1370 MEMORY_ATOMIC_NOTIFY_A64 = 1355,
1371 MEMORY_ATOMIC_NOTIFY_A64_S = 1356,
1372 MEMORY_ATOMIC_WAIT32_A32 = 1357,
1373 MEMORY_ATOMIC_WAIT32_A32_S = 1358,
1374 MEMORY_ATOMIC_WAIT32_A64 = 1359,
1375 MEMORY_ATOMIC_WAIT32_A64_S = 1360,
1376 MEMORY_ATOMIC_WAIT64_A32 = 1361,
1377 MEMORY_ATOMIC_WAIT64_A32_S = 1362,
1378 MEMORY_ATOMIC_WAIT64_A64 = 1363,
1379 MEMORY_ATOMIC_WAIT64_A64_S = 1364,
1380 MIN_F16x8 = 1365,
1381 MIN_F16x8_S = 1366,
1382 MIN_F32 = 1367,
1383 MIN_F32_S = 1368,
1384 MIN_F32x4 = 1369,
1385 MIN_F32x4_S = 1370,
1386 MIN_F64 = 1371,
1387 MIN_F64_S = 1372,
1388 MIN_F64x2 = 1373,
1389 MIN_F64x2_S = 1374,
1390 MIN_S_I16x8 = 1375,
1391 MIN_S_I16x8_S = 1376,
1392 MIN_S_I32x4 = 1377,
1393 MIN_S_I32x4_S = 1378,
1394 MIN_S_I8x16 = 1379,
1395 MIN_S_I8x16_S = 1380,
1396 MIN_U_I16x8 = 1381,
1397 MIN_U_I16x8_S = 1382,
1398 MIN_U_I32x4 = 1383,
1399 MIN_U_I32x4_S = 1384,
1400 MIN_U_I8x16 = 1385,
1401 MIN_U_I8x16_S = 1386,
1402 MUL_F16x8 = 1387,
1403 MUL_F16x8_S = 1388,
1404 MUL_F32 = 1389,
1405 MUL_F32_S = 1390,
1406 MUL_F32x4 = 1391,
1407 MUL_F32x4_S = 1392,
1408 MUL_F64 = 1393,
1409 MUL_F64_S = 1394,
1410 MUL_F64x2 = 1395,
1411 MUL_F64x2_S = 1396,
1412 MUL_I16x8 = 1397,
1413 MUL_I16x8_S = 1398,
1414 MUL_I32 = 1399,
1415 MUL_I32_S = 1400,
1416 MUL_I32x4 = 1401,
1417 MUL_I32x4_S = 1402,
1418 MUL_I64 = 1403,
1419 MUL_I64_S = 1404,
1420 MUL_I64x2 = 1405,
1421 MUL_I64x2_S = 1406,
1422 NARROW_S_I16x8 = 1407,
1423 NARROW_S_I16x8_S = 1408,
1424 NARROW_S_I8x16 = 1409,
1425 NARROW_S_I8x16_S = 1410,
1426 NARROW_U_I16x8 = 1411,
1427 NARROW_U_I16x8_S = 1412,
1428 NARROW_U_I8x16 = 1413,
1429 NARROW_U_I8x16_S = 1414,
1430 NEAREST_F16x8 = 1415,
1431 NEAREST_F16x8_S = 1416,
1432 NEAREST_F32 = 1417,
1433 NEAREST_F32_S = 1418,
1434 NEAREST_F32x4 = 1419,
1435 NEAREST_F32x4_S = 1420,
1436 NEAREST_F64 = 1421,
1437 NEAREST_F64_S = 1422,
1438 NEAREST_F64x2 = 1423,
1439 NEAREST_F64x2_S = 1424,
1440 NEG_F16x8 = 1425,
1441 NEG_F16x8_S = 1426,
1442 NEG_F32 = 1427,
1443 NEG_F32_S = 1428,
1444 NEG_F32x4 = 1429,
1445 NEG_F32x4_S = 1430,
1446 NEG_F64 = 1431,
1447 NEG_F64_S = 1432,
1448 NEG_F64x2 = 1433,
1449 NEG_F64x2_S = 1434,
1450 NEG_I16x8 = 1435,
1451 NEG_I16x8_S = 1436,
1452 NEG_I32x4 = 1437,
1453 NEG_I32x4_S = 1438,
1454 NEG_I64x2 = 1439,
1455 NEG_I64x2_S = 1440,
1456 NEG_I8x16 = 1441,
1457 NEG_I8x16_S = 1442,
1458 NE_F16x8 = 1443,
1459 NE_F16x8_S = 1444,
1460 NE_F32 = 1445,
1461 NE_F32_S = 1446,
1462 NE_F32x4 = 1447,
1463 NE_F32x4_S = 1448,
1464 NE_F64 = 1449,
1465 NE_F64_S = 1450,
1466 NE_F64x2 = 1451,
1467 NE_F64x2_S = 1452,
1468 NE_I16x8 = 1453,
1469 NE_I16x8_S = 1454,
1470 NE_I32 = 1455,
1471 NE_I32_S = 1456,
1472 NE_I32x4 = 1457,
1473 NE_I32x4_S = 1458,
1474 NE_I64 = 1459,
1475 NE_I64_S = 1460,
1476 NE_I64x2 = 1461,
1477 NE_I64x2_S = 1462,
1478 NE_I8x16 = 1463,
1479 NE_I8x16_S = 1464,
1480 NMADD_F16x8 = 1465,
1481 NMADD_F16x8_S = 1466,
1482 NMADD_F32x4 = 1467,
1483 NMADD_F32x4_S = 1468,
1484 NMADD_F64x2 = 1469,
1485 NMADD_F64x2_S = 1470,
1486 NOP = 1471,
1487 NOP_S = 1472,
1488 NOT = 1473,
1489 NOT_S = 1474,
1490 OR = 1475,
1491 OR_I32 = 1476,
1492 OR_I32_S = 1477,
1493 OR_I64 = 1478,
1494 OR_I64_S = 1479,
1495 OR_S = 1480,
1496 PMAX_F16x8 = 1481,
1497 PMAX_F16x8_S = 1482,
1498 PMAX_F32x4 = 1483,
1499 PMAX_F32x4_S = 1484,
1500 PMAX_F64x2 = 1485,
1501 PMAX_F64x2_S = 1486,
1502 PMIN_F16x8 = 1487,
1503 PMIN_F16x8_S = 1488,
1504 PMIN_F32x4 = 1489,
1505 PMIN_F32x4_S = 1490,
1506 PMIN_F64x2 = 1491,
1507 PMIN_F64x2_S = 1492,
1508 POPCNT_I32 = 1493,
1509 POPCNT_I32_S = 1494,
1510 POPCNT_I64 = 1495,
1511 POPCNT_I64_S = 1496,
1512 POPCNT_I8x16 = 1497,
1513 POPCNT_I8x16_S = 1498,
1514 Q15MULR_SAT_S_I16x8 = 1499,
1515 Q15MULR_SAT_S_I16x8_S = 1500,
1516 REF_IS_NULL_EXNREF = 1501,
1517 REF_IS_NULL_EXNREF_S = 1502,
1518 REF_IS_NULL_EXTERNREF = 1503,
1519 REF_IS_NULL_EXTERNREF_S = 1504,
1520 REF_IS_NULL_FUNCREF = 1505,
1521 REF_IS_NULL_FUNCREF_S = 1506,
1522 REF_NULL_EXNREF = 1507,
1523 REF_NULL_EXNREF_S = 1508,
1524 REF_NULL_EXTERNREF = 1509,
1525 REF_NULL_EXTERNREF_S = 1510,
1526 REF_NULL_FUNCREF = 1511,
1527 REF_NULL_FUNCREF_S = 1512,
1528 RELAXED_DOT = 1513,
1529 RELAXED_DOT_ADD = 1514,
1530 RELAXED_DOT_ADD_S = 1515,
1531 RELAXED_DOT_BFLOAT = 1516,
1532 RELAXED_DOT_BFLOAT_S = 1517,
1533 RELAXED_DOT_S = 1518,
1534 RELAXED_Q15MULR_S_I16x8 = 1519,
1535 RELAXED_Q15MULR_S_I16x8_S = 1520,
1536 RELAXED_SWIZZLE = 1521,
1537 RELAXED_SWIZZLE_S = 1522,
1538 REM_S_I32 = 1523,
1539 REM_S_I32_S = 1524,
1540 REM_S_I64 = 1525,
1541 REM_S_I64_S = 1526,
1542 REM_U_I32 = 1527,
1543 REM_U_I32_S = 1528,
1544 REM_U_I64 = 1529,
1545 REM_U_I64_S = 1530,
1546 REPLACE_LANE_F32x4 = 1531,
1547 REPLACE_LANE_F32x4_S = 1532,
1548 REPLACE_LANE_F64x2 = 1533,
1549 REPLACE_LANE_F64x2_S = 1534,
1550 REPLACE_LANE_I16x8 = 1535,
1551 REPLACE_LANE_I16x8_S = 1536,
1552 REPLACE_LANE_I32x4 = 1537,
1553 REPLACE_LANE_I32x4_S = 1538,
1554 REPLACE_LANE_I64x2 = 1539,
1555 REPLACE_LANE_I64x2_S = 1540,
1556 REPLACE_LANE_I8x16 = 1541,
1557 REPLACE_LANE_I8x16_S = 1542,
1558 RETHROW = 1543,
1559 RETHROW_S = 1544,
1560 RETURN = 1545,
1561 RETURN_S = 1546,
1562 RET_CALL = 1547,
1563 RET_CALL_INDIRECT = 1548,
1564 RET_CALL_INDIRECT_S = 1549,
1565 RET_CALL_S = 1550,
1566 ROTL_I32 = 1551,
1567 ROTL_I32_S = 1552,
1568 ROTL_I64 = 1553,
1569 ROTL_I64_S = 1554,
1570 ROTR_I32 = 1555,
1571 ROTR_I32_S = 1556,
1572 ROTR_I64 = 1557,
1573 ROTR_I64_S = 1558,
1574 SELECT_EXNREF = 1559,
1575 SELECT_EXNREF_S = 1560,
1576 SELECT_EXTERNREF = 1561,
1577 SELECT_EXTERNREF_S = 1562,
1578 SELECT_F32 = 1563,
1579 SELECT_F32_S = 1564,
1580 SELECT_F64 = 1565,
1581 SELECT_F64_S = 1566,
1582 SELECT_FUNCREF = 1567,
1583 SELECT_FUNCREF_S = 1568,
1584 SELECT_I32 = 1569,
1585 SELECT_I32_S = 1570,
1586 SELECT_I64 = 1571,
1587 SELECT_I64_S = 1572,
1588 SELECT_V128 = 1573,
1589 SELECT_V128_S = 1574,
1590 SHL_I16x8 = 1575,
1591 SHL_I16x8_S = 1576,
1592 SHL_I32 = 1577,
1593 SHL_I32_S = 1578,
1594 SHL_I32x4 = 1579,
1595 SHL_I32x4_S = 1580,
1596 SHL_I64 = 1581,
1597 SHL_I64_S = 1582,
1598 SHL_I64x2 = 1583,
1599 SHL_I64x2_S = 1584,
1600 SHL_I8x16 = 1585,
1601 SHL_I8x16_S = 1586,
1602 SHR_S_I16x8 = 1587,
1603 SHR_S_I16x8_S = 1588,
1604 SHR_S_I32 = 1589,
1605 SHR_S_I32_S = 1590,
1606 SHR_S_I32x4 = 1591,
1607 SHR_S_I32x4_S = 1592,
1608 SHR_S_I64 = 1593,
1609 SHR_S_I64_S = 1594,
1610 SHR_S_I64x2 = 1595,
1611 SHR_S_I64x2_S = 1596,
1612 SHR_S_I8x16 = 1597,
1613 SHR_S_I8x16_S = 1598,
1614 SHR_U_I16x8 = 1599,
1615 SHR_U_I16x8_S = 1600,
1616 SHR_U_I32 = 1601,
1617 SHR_U_I32_S = 1602,
1618 SHR_U_I32x4 = 1603,
1619 SHR_U_I32x4_S = 1604,
1620 SHR_U_I64 = 1605,
1621 SHR_U_I64_S = 1606,
1622 SHR_U_I64x2 = 1607,
1623 SHR_U_I64x2_S = 1608,
1624 SHR_U_I8x16 = 1609,
1625 SHR_U_I8x16_S = 1610,
1626 SHUFFLE = 1611,
1627 SHUFFLE_S = 1612,
1628 SIMD_RELAXED_FMAX_F32x4 = 1613,
1629 SIMD_RELAXED_FMAX_F32x4_S = 1614,
1630 SIMD_RELAXED_FMAX_F64x2 = 1615,
1631 SIMD_RELAXED_FMAX_F64x2_S = 1616,
1632 SIMD_RELAXED_FMIN_F32x4 = 1617,
1633 SIMD_RELAXED_FMIN_F32x4_S = 1618,
1634 SIMD_RELAXED_FMIN_F64x2 = 1619,
1635 SIMD_RELAXED_FMIN_F64x2_S = 1620,
1636 SPLAT_F16x8 = 1621,
1637 SPLAT_F16x8_S = 1622,
1638 SPLAT_F32x4 = 1623,
1639 SPLAT_F32x4_S = 1624,
1640 SPLAT_F64x2 = 1625,
1641 SPLAT_F64x2_S = 1626,
1642 SPLAT_I16x8 = 1627,
1643 SPLAT_I16x8_S = 1628,
1644 SPLAT_I32x4 = 1629,
1645 SPLAT_I32x4_S = 1630,
1646 SPLAT_I64x2 = 1631,
1647 SPLAT_I64x2_S = 1632,
1648 SPLAT_I8x16 = 1633,
1649 SPLAT_I8x16_S = 1634,
1650 SQRT_F16x8 = 1635,
1651 SQRT_F16x8_S = 1636,
1652 SQRT_F32 = 1637,
1653 SQRT_F32_S = 1638,
1654 SQRT_F32x4 = 1639,
1655 SQRT_F32x4_S = 1640,
1656 SQRT_F64 = 1641,
1657 SQRT_F64_S = 1642,
1658 SQRT_F64x2 = 1643,
1659 SQRT_F64x2_S = 1644,
1660 STORE16_I32_A32 = 1645,
1661 STORE16_I32_A32_S = 1646,
1662 STORE16_I32_A64 = 1647,
1663 STORE16_I32_A64_S = 1648,
1664 STORE16_I64_A32 = 1649,
1665 STORE16_I64_A32_S = 1650,
1666 STORE16_I64_A64 = 1651,
1667 STORE16_I64_A64_S = 1652,
1668 STORE32_I64_A32 = 1653,
1669 STORE32_I64_A32_S = 1654,
1670 STORE32_I64_A64 = 1655,
1671 STORE32_I64_A64_S = 1656,
1672 STORE8_I32_A32 = 1657,
1673 STORE8_I32_A32_S = 1658,
1674 STORE8_I32_A64 = 1659,
1675 STORE8_I32_A64_S = 1660,
1676 STORE8_I64_A32 = 1661,
1677 STORE8_I64_A32_S = 1662,
1678 STORE8_I64_A64 = 1663,
1679 STORE8_I64_A64_S = 1664,
1680 STORE_F16_F32_A32 = 1665,
1681 STORE_F16_F32_A32_S = 1666,
1682 STORE_F16_F32_A64 = 1667,
1683 STORE_F16_F32_A64_S = 1668,
1684 STORE_F32_A32 = 1669,
1685 STORE_F32_A32_S = 1670,
1686 STORE_F32_A64 = 1671,
1687 STORE_F32_A64_S = 1672,
1688 STORE_F64_A32 = 1673,
1689 STORE_F64_A32_S = 1674,
1690 STORE_F64_A64 = 1675,
1691 STORE_F64_A64_S = 1676,
1692 STORE_I32_A32 = 1677,
1693 STORE_I32_A32_S = 1678,
1694 STORE_I32_A64 = 1679,
1695 STORE_I32_A64_S = 1680,
1696 STORE_I64_A32 = 1681,
1697 STORE_I64_A32_S = 1682,
1698 STORE_I64_A64 = 1683,
1699 STORE_I64_A64_S = 1684,
1700 STORE_LANE_I16x8_A32 = 1685,
1701 STORE_LANE_I16x8_A32_S = 1686,
1702 STORE_LANE_I16x8_A64 = 1687,
1703 STORE_LANE_I16x8_A64_S = 1688,
1704 STORE_LANE_I32x4_A32 = 1689,
1705 STORE_LANE_I32x4_A32_S = 1690,
1706 STORE_LANE_I32x4_A64 = 1691,
1707 STORE_LANE_I32x4_A64_S = 1692,
1708 STORE_LANE_I64x2_A32 = 1693,
1709 STORE_LANE_I64x2_A32_S = 1694,
1710 STORE_LANE_I64x2_A64 = 1695,
1711 STORE_LANE_I64x2_A64_S = 1696,
1712 STORE_LANE_I8x16_A32 = 1697,
1713 STORE_LANE_I8x16_A32_S = 1698,
1714 STORE_LANE_I8x16_A64 = 1699,
1715 STORE_LANE_I8x16_A64_S = 1700,
1716 STORE_V128_A32 = 1701,
1717 STORE_V128_A32_S = 1702,
1718 STORE_V128_A64 = 1703,
1719 STORE_V128_A64_S = 1704,
1720 SUB_F16x8 = 1705,
1721 SUB_F16x8_S = 1706,
1722 SUB_F32 = 1707,
1723 SUB_F32_S = 1708,
1724 SUB_F32x4 = 1709,
1725 SUB_F32x4_S = 1710,
1726 SUB_F64 = 1711,
1727 SUB_F64_S = 1712,
1728 SUB_F64x2 = 1713,
1729 SUB_F64x2_S = 1714,
1730 SUB_I16x8 = 1715,
1731 SUB_I16x8_S = 1716,
1732 SUB_I32 = 1717,
1733 SUB_I32_S = 1718,
1734 SUB_I32x4 = 1719,
1735 SUB_I32x4_S = 1720,
1736 SUB_I64 = 1721,
1737 SUB_I64_S = 1722,
1738 SUB_I64x2 = 1723,
1739 SUB_I64x2_S = 1724,
1740 SUB_I8x16 = 1725,
1741 SUB_I8x16_S = 1726,
1742 SUB_SAT_S_I16x8 = 1727,
1743 SUB_SAT_S_I16x8_S = 1728,
1744 SUB_SAT_S_I8x16 = 1729,
1745 SUB_SAT_S_I8x16_S = 1730,
1746 SUB_SAT_U_I16x8 = 1731,
1747 SUB_SAT_U_I16x8_S = 1732,
1748 SUB_SAT_U_I8x16 = 1733,
1749 SUB_SAT_U_I8x16_S = 1734,
1750 SWIZZLE = 1735,
1751 SWIZZLE_S = 1736,
1752 TABLE_COPY = 1737,
1753 TABLE_COPY_S = 1738,
1754 TABLE_FILL_EXNREF = 1739,
1755 TABLE_FILL_EXNREF_S = 1740,
1756 TABLE_FILL_EXTERNREF = 1741,
1757 TABLE_FILL_EXTERNREF_S = 1742,
1758 TABLE_FILL_FUNCREF = 1743,
1759 TABLE_FILL_FUNCREF_S = 1744,
1760 TABLE_GET_EXNREF = 1745,
1761 TABLE_GET_EXNREF_S = 1746,
1762 TABLE_GET_EXTERNREF = 1747,
1763 TABLE_GET_EXTERNREF_S = 1748,
1764 TABLE_GET_FUNCREF = 1749,
1765 TABLE_GET_FUNCREF_S = 1750,
1766 TABLE_GROW_EXNREF = 1751,
1767 TABLE_GROW_EXNREF_S = 1752,
1768 TABLE_GROW_EXTERNREF = 1753,
1769 TABLE_GROW_EXTERNREF_S = 1754,
1770 TABLE_GROW_FUNCREF = 1755,
1771 TABLE_GROW_FUNCREF_S = 1756,
1772 TABLE_SET_EXNREF = 1757,
1773 TABLE_SET_EXNREF_S = 1758,
1774 TABLE_SET_EXTERNREF = 1759,
1775 TABLE_SET_EXTERNREF_S = 1760,
1776 TABLE_SET_FUNCREF = 1761,
1777 TABLE_SET_FUNCREF_S = 1762,
1778 TABLE_SIZE = 1763,
1779 TABLE_SIZE_S = 1764,
1780 TEE_EXNREF = 1765,
1781 TEE_EXNREF_S = 1766,
1782 TEE_EXTERNREF = 1767,
1783 TEE_EXTERNREF_S = 1768,
1784 TEE_F32 = 1769,
1785 TEE_F32_S = 1770,
1786 TEE_F64 = 1771,
1787 TEE_F64_S = 1772,
1788 TEE_FUNCREF = 1773,
1789 TEE_FUNCREF_S = 1774,
1790 TEE_I32 = 1775,
1791 TEE_I32_S = 1776,
1792 TEE_I64 = 1777,
1793 TEE_I64_S = 1778,
1794 TEE_V128 = 1779,
1795 TEE_V128_S = 1780,
1796 THROW = 1781,
1797 THROW_S = 1782,
1798 TRUNC_F16x8 = 1783,
1799 TRUNC_F16x8_S = 1784,
1800 TRUNC_F32 = 1785,
1801 TRUNC_F32_S = 1786,
1802 TRUNC_F32x4 = 1787,
1803 TRUNC_F32x4_S = 1788,
1804 TRUNC_F64 = 1789,
1805 TRUNC_F64_S = 1790,
1806 TRUNC_F64x2 = 1791,
1807 TRUNC_F64x2_S = 1792,
1808 TRY = 1793,
1809 TRY_S = 1794,
1810 UNREACHABLE = 1795,
1811 UNREACHABLE_S = 1796,
1812 XOR = 1797,
1813 XOR_I32 = 1798,
1814 XOR_I32_S = 1799,
1815 XOR_I64 = 1800,
1816 XOR_I64_S = 1801,
1817 XOR_S = 1802,
1818 anonymous_8187MEMORY_GROW_A32 = 1803,
1819 anonymous_8187MEMORY_GROW_A32_S = 1804,
1820 anonymous_8187MEMORY_SIZE_A32 = 1805,
1821 anonymous_8187MEMORY_SIZE_A32_S = 1806,
1822 anonymous_8188MEMORY_GROW_A64 = 1807,
1823 anonymous_8188MEMORY_GROW_A64_S = 1808,
1824 anonymous_8188MEMORY_SIZE_A64 = 1809,
1825 anonymous_8188MEMORY_SIZE_A64_S = 1810,
1826 anonymous_8878DATA_DROP = 1811,
1827 anonymous_8878DATA_DROP_S = 1812,
1828 anonymous_8878MEMORY_COPY_A32 = 1813,
1829 anonymous_8878MEMORY_COPY_A32_S = 1814,
1830 anonymous_8878MEMORY_FILL_A32 = 1815,
1831 anonymous_8878MEMORY_FILL_A32_S = 1816,
1832 anonymous_8878MEMORY_INIT_A32 = 1817,
1833 anonymous_8878MEMORY_INIT_A32_S = 1818,
1834 anonymous_8879DATA_DROP = 1819,
1835 anonymous_8879DATA_DROP_S = 1820,
1836 anonymous_8879MEMORY_COPY_A64 = 1821,
1837 anonymous_8879MEMORY_COPY_A64_S = 1822,
1838 anonymous_8879MEMORY_FILL_A64 = 1823,
1839 anonymous_8879MEMORY_FILL_A64_S = 1824,
1840 anonymous_8879MEMORY_INIT_A64 = 1825,
1841 anonymous_8879MEMORY_INIT_A64_S = 1826,
1842 convert_low_s_F64x2 = 1827,
1843 convert_low_s_F64x2_S = 1828,
1844 convert_low_u_F64x2 = 1829,
1845 convert_low_u_F64x2_S = 1830,
1846 demote_zero_F32x4 = 1831,
1847 demote_zero_F32x4_S = 1832,
1848 extend_high_s_I16x8 = 1833,
1849 extend_high_s_I16x8_S = 1834,
1850 extend_high_s_I32x4 = 1835,
1851 extend_high_s_I32x4_S = 1836,
1852 extend_high_s_I64x2 = 1837,
1853 extend_high_s_I64x2_S = 1838,
1854 extend_high_u_I16x8 = 1839,
1855 extend_high_u_I16x8_S = 1840,
1856 extend_high_u_I32x4 = 1841,
1857 extend_high_u_I32x4_S = 1842,
1858 extend_high_u_I64x2 = 1843,
1859 extend_high_u_I64x2_S = 1844,
1860 extend_low_s_I16x8 = 1845,
1861 extend_low_s_I16x8_S = 1846,
1862 extend_low_s_I32x4 = 1847,
1863 extend_low_s_I32x4_S = 1848,
1864 extend_low_s_I64x2 = 1849,
1865 extend_low_s_I64x2_S = 1850,
1866 extend_low_u_I16x8 = 1851,
1867 extend_low_u_I16x8_S = 1852,
1868 extend_low_u_I32x4 = 1853,
1869 extend_low_u_I32x4_S = 1854,
1870 extend_low_u_I64x2 = 1855,
1871 extend_low_u_I64x2_S = 1856,
1872 fp_to_sint_I16x8 = 1857,
1873 fp_to_sint_I16x8_S = 1858,
1874 fp_to_sint_I32x4 = 1859,
1875 fp_to_sint_I32x4_S = 1860,
1876 fp_to_uint_I16x8 = 1861,
1877 fp_to_uint_I16x8_S = 1862,
1878 fp_to_uint_I32x4 = 1863,
1879 fp_to_uint_I32x4_S = 1864,
1880 int_wasm_extadd_pairwise_signed_I16x8 = 1865,
1881 int_wasm_extadd_pairwise_signed_I16x8_S = 1866,
1882 int_wasm_extadd_pairwise_signed_I32x4 = 1867,
1883 int_wasm_extadd_pairwise_signed_I32x4_S = 1868,
1884 int_wasm_extadd_pairwise_unsigned_I16x8 = 1869,
1885 int_wasm_extadd_pairwise_unsigned_I16x8_S = 1870,
1886 int_wasm_extadd_pairwise_unsigned_I32x4 = 1871,
1887 int_wasm_extadd_pairwise_unsigned_I32x4_S = 1872,
1888 int_wasm_relaxed_trunc_signed_I32x4 = 1873,
1889 int_wasm_relaxed_trunc_signed_I32x4_S = 1874,
1890 int_wasm_relaxed_trunc_signed_zero_I32x4 = 1875,
1891 int_wasm_relaxed_trunc_signed_zero_I32x4_S = 1876,
1892 int_wasm_relaxed_trunc_unsigned_I32x4 = 1877,
1893 int_wasm_relaxed_trunc_unsigned_I32x4_S = 1878,
1894 int_wasm_relaxed_trunc_unsigned_zero_I32x4 = 1879,
1895 int_wasm_relaxed_trunc_unsigned_zero_I32x4_S = 1880,
1896 promote_low_F64x2 = 1881,
1897 promote_low_F64x2_S = 1882,
1898 sint_to_fp_F16x8 = 1883,
1899 sint_to_fp_F16x8_S = 1884,
1900 sint_to_fp_F32x4 = 1885,
1901 sint_to_fp_F32x4_S = 1886,
1902 trunc_sat_zero_s_I32x4 = 1887,
1903 trunc_sat_zero_s_I32x4_S = 1888,
1904 trunc_sat_zero_u_I32x4 = 1889,
1905 trunc_sat_zero_u_I32x4_S = 1890,
1906 uint_to_fp_F16x8 = 1891,
1907 uint_to_fp_F16x8_S = 1892,
1908 uint_to_fp_F32x4 = 1893,
1909 uint_to_fp_F32x4_S = 1894,
1910 INSTRUCTION_LIST_END = 1895
1911 };
1912
1913} // end namespace WebAssembly
1914} // end namespace llvm
1915#endif // GET_INSTRINFO_ENUM
1916
1917#ifdef GET_INSTRINFO_SCHED_ENUM
1918#undef GET_INSTRINFO_SCHED_ENUM
1919namespace llvm {
1920
1921namespace WebAssembly {
1922namespace Sched {
1923 enum {
1924 NoInstrModel = 0,
1925 SCHED_LIST_END = 1
1926 };
1927} // end namespace Sched
1928} // end namespace WebAssembly
1929} // end namespace llvm
1930#endif // GET_INSTRINFO_SCHED_ENUM
1931
1932#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
1933namespace llvm {
1934
1935struct WebAssemblyInstrTable {
1936 MCInstrDesc Insts[1895];
1937 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
1938 MCOperandInfo OperandInfo[808];
1939 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
1940 MCPhysReg ImplicitOps[10];
1941};
1942
1943} // end namespace llvm
1944#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
1945
1946#ifdef GET_INSTRINFO_MC_DESC
1947#undef GET_INSTRINFO_MC_DESC
1948namespace llvm {
1949
1950static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
1951static constexpr unsigned WebAssemblyImpOpBase = sizeof WebAssemblyInstrTable::OperandInfo / (sizeof(MCPhysReg));
1952
1953extern const WebAssemblyInstrTable WebAssemblyDescs = {
1954 {
1955 { 1894, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1894 = uint_to_fp_F32x4_S
1956 { 1893, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1893 = uint_to_fp_F32x4
1957 { 1892, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1892 = uint_to_fp_F16x8_S
1958 { 1891, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1891 = uint_to_fp_F16x8
1959 { 1890, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1890 = trunc_sat_zero_u_I32x4_S
1960 { 1889, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1889 = trunc_sat_zero_u_I32x4
1961 { 1888, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1888 = trunc_sat_zero_s_I32x4_S
1962 { 1887, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1887 = trunc_sat_zero_s_I32x4
1963 { 1886, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1886 = sint_to_fp_F32x4_S
1964 { 1885, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1885 = sint_to_fp_F32x4
1965 { 1884, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1884 = sint_to_fp_F16x8_S
1966 { 1883, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1883 = sint_to_fp_F16x8
1967 { 1882, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1882 = promote_low_F64x2_S
1968 { 1881, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1881 = promote_low_F64x2
1969 { 1880, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1880 = int_wasm_relaxed_trunc_unsigned_zero_I32x4_S
1970 { 1879, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1879 = int_wasm_relaxed_trunc_unsigned_zero_I32x4
1971 { 1878, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1878 = int_wasm_relaxed_trunc_unsigned_I32x4_S
1972 { 1877, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1877 = int_wasm_relaxed_trunc_unsigned_I32x4
1973 { 1876, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1876 = int_wasm_relaxed_trunc_signed_zero_I32x4_S
1974 { 1875, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1875 = int_wasm_relaxed_trunc_signed_zero_I32x4
1975 { 1874, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1874 = int_wasm_relaxed_trunc_signed_I32x4_S
1976 { 1873, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1873 = int_wasm_relaxed_trunc_signed_I32x4
1977 { 1872, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1872 = int_wasm_extadd_pairwise_unsigned_I32x4_S
1978 { 1871, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1871 = int_wasm_extadd_pairwise_unsigned_I32x4
1979 { 1870, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1870 = int_wasm_extadd_pairwise_unsigned_I16x8_S
1980 { 1869, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1869 = int_wasm_extadd_pairwise_unsigned_I16x8
1981 { 1868, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1868 = int_wasm_extadd_pairwise_signed_I32x4_S
1982 { 1867, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1867 = int_wasm_extadd_pairwise_signed_I32x4
1983 { 1866, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1866 = int_wasm_extadd_pairwise_signed_I16x8_S
1984 { 1865, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1865 = int_wasm_extadd_pairwise_signed_I16x8
1985 { 1864, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1864 = fp_to_uint_I32x4_S
1986 { 1863, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1863 = fp_to_uint_I32x4
1987 { 1862, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1862 = fp_to_uint_I16x8_S
1988 { 1861, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1861 = fp_to_uint_I16x8
1989 { 1860, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1860 = fp_to_sint_I32x4_S
1990 { 1859, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1859 = fp_to_sint_I32x4
1991 { 1858, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1858 = fp_to_sint_I16x8_S
1992 { 1857, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1857 = fp_to_sint_I16x8
1993 { 1856, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1856 = extend_low_u_I64x2_S
1994 { 1855, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1855 = extend_low_u_I64x2
1995 { 1854, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1854 = extend_low_u_I32x4_S
1996 { 1853, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1853 = extend_low_u_I32x4
1997 { 1852, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1852 = extend_low_u_I16x8_S
1998 { 1851, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1851 = extend_low_u_I16x8
1999 { 1850, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1850 = extend_low_s_I64x2_S
2000 { 1849, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1849 = extend_low_s_I64x2
2001 { 1848, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1848 = extend_low_s_I32x4_S
2002 { 1847, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1847 = extend_low_s_I32x4
2003 { 1846, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1846 = extend_low_s_I16x8_S
2004 { 1845, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1845 = extend_low_s_I16x8
2005 { 1844, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1844 = extend_high_u_I64x2_S
2006 { 1843, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1843 = extend_high_u_I64x2
2007 { 1842, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1842 = extend_high_u_I32x4_S
2008 { 1841, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1841 = extend_high_u_I32x4
2009 { 1840, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1840 = extend_high_u_I16x8_S
2010 { 1839, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1839 = extend_high_u_I16x8
2011 { 1838, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1838 = extend_high_s_I64x2_S
2012 { 1837, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1837 = extend_high_s_I64x2
2013 { 1836, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1836 = extend_high_s_I32x4_S
2014 { 1835, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1835 = extend_high_s_I32x4
2015 { 1834, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1834 = extend_high_s_I16x8_S
2016 { 1833, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1833 = extend_high_s_I16x8
2017 { 1832, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1832 = demote_zero_F32x4_S
2018 { 1831, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1831 = demote_zero_F32x4
2019 { 1830, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1830 = convert_low_u_F64x2_S
2020 { 1829, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1829 = convert_low_u_F64x2
2021 { 1828, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1828 = convert_low_s_F64x2_S
2022 { 1827, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1827 = convert_low_s_F64x2
2023 { 1826, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 788, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1826 = anonymous_8879MEMORY_INIT_A64_S
2024 { 1825, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 803, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1825 = anonymous_8879MEMORY_INIT_A64
2025 { 1824, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1824 = anonymous_8879MEMORY_FILL_A64_S
2026 { 1823, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 799, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1823 = anonymous_8879MEMORY_FILL_A64
2027 { 1822, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 788, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1822 = anonymous_8879MEMORY_COPY_A64_S
2028 { 1821, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 794, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1821 = anonymous_8879MEMORY_COPY_A64
2029 { 1820, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1820 = anonymous_8879DATA_DROP_S
2030 { 1819, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1819 = anonymous_8879DATA_DROP
2031 { 1818, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 788, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1818 = anonymous_8878MEMORY_INIT_A32_S
2032 { 1817, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 783, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1817 = anonymous_8878MEMORY_INIT_A32
2033 { 1816, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1816 = anonymous_8878MEMORY_FILL_A32_S
2034 { 1815, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 790, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1815 = anonymous_8878MEMORY_FILL_A32
2035 { 1814, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 788, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1814 = anonymous_8878MEMORY_COPY_A32_S
2036 { 1813, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 783, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1813 = anonymous_8878MEMORY_COPY_A32
2037 { 1812, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1812 = anonymous_8878DATA_DROP_S
2038 { 1811, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1811 = anonymous_8878DATA_DROP
2039 { 1810, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1810 = anonymous_8188MEMORY_SIZE_A64_S
2040 { 1809, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 190, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1809 = anonymous_8188MEMORY_SIZE_A64
2041 { 1808, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1808 = anonymous_8188MEMORY_GROW_A64_S
2042 { 1807, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 780, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1807 = anonymous_8188MEMORY_GROW_A64
2043 { 1806, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1806 = anonymous_8187MEMORY_SIZE_A32_S
2044 { 1805, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1805 = anonymous_8187MEMORY_SIZE_A32
2045 { 1804, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1804 = anonymous_8187MEMORY_GROW_A32_S
2046 { 1803, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 777, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1803 = anonymous_8187MEMORY_GROW_A32
2047 { 1802, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1802 = XOR_S
2048 { 1801, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1801 = XOR_I64_S
2049 { 1800, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1800 = XOR_I64
2050 { 1799, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1799 = XOR_I32_S
2051 { 1798, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1798 = XOR_I32
2052 { 1797, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1797 = XOR
2053 { 1796, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1796 = UNREACHABLE_S
2054 { 1795, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1795 = UNREACHABLE
2055 { 1794, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1794 = TRY_S
2056 { 1793, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1793 = TRY
2057 { 1792, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1792 = TRUNC_F64x2_S
2058 { 1791, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1791 = TRUNC_F64x2
2059 { 1790, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1790 = TRUNC_F64_S
2060 { 1789, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1789 = TRUNC_F64
2061 { 1788, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1788 = TRUNC_F32x4_S
2062 { 1787, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1787 = TRUNC_F32x4
2063 { 1786, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1786 = TRUNC_F32_S
2064 { 1785, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1785 = TRUNC_F32
2065 { 1784, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1784 = TRUNC_F16x8_S
2066 { 1783, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1783 = TRUNC_F16x8
2067 { 1782, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1782 = THROW_S
2068 { 1781, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1781 = THROW
2069 { 1780, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1780 = TEE_V128_S
2070 { 1779, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1779 = TEE_V128
2071 { 1778, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1778 = TEE_I64_S
2072 { 1777, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1777 = TEE_I64
2073 { 1776, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1776 = TEE_I32_S
2074 { 1775, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1775 = TEE_I32
2075 { 1774, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1774 = TEE_FUNCREF_S
2076 { 1773, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 774, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1773 = TEE_FUNCREF
2077 { 1772, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1772 = TEE_F64_S
2078 { 1771, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1771 = TEE_F64
2079 { 1770, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1770 = TEE_F32_S
2080 { 1769, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1769 = TEE_F32
2081 { 1768, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1768 = TEE_EXTERNREF_S
2082 { 1767, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 771, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1767 = TEE_EXTERNREF
2083 { 1766, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1766 = TEE_EXNREF_S
2084 { 1765, 3, 2, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 768, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1765 = TEE_EXNREF
2085 { 1764, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1764 = TABLE_SIZE_S
2086 { 1763, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 766, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1763 = TABLE_SIZE
2087 { 1762, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1762 = TABLE_SET_FUNCREF_S
2088 { 1761, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 763, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1761 = TABLE_SET_FUNCREF
2089 { 1760, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1760 = TABLE_SET_EXTERNREF_S
2090 { 1759, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 760, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1759 = TABLE_SET_EXTERNREF
2091 { 1758, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1758 = TABLE_SET_EXNREF_S
2092 { 1757, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 757, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1757 = TABLE_SET_EXNREF
2093 { 1756, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1756 = TABLE_GROW_FUNCREF_S
2094 { 1755, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 753, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1755 = TABLE_GROW_FUNCREF
2095 { 1754, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1754 = TABLE_GROW_EXTERNREF_S
2096 { 1753, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 749, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1753 = TABLE_GROW_EXTERNREF
2097 { 1752, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1752 = TABLE_GROW_EXNREF_S
2098 { 1751, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1751 = TABLE_GROW_EXNREF
2099 { 1750, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1750 = TABLE_GET_FUNCREF_S
2100 { 1749, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 742, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1749 = TABLE_GET_FUNCREF
2101 { 1748, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1748 = TABLE_GET_EXTERNREF_S
2102 { 1747, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 739, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1747 = TABLE_GET_EXTERNREF
2103 { 1746, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1746 = TABLE_GET_EXNREF_S
2104 { 1745, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 736, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1745 = TABLE_GET_EXNREF
2105 { 1744, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1744 = TABLE_FILL_FUNCREF_S
2106 { 1743, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 732, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1743 = TABLE_FILL_FUNCREF
2107 { 1742, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1742 = TABLE_FILL_EXTERNREF_S
2108 { 1741, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 728, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1741 = TABLE_FILL_EXTERNREF
2109 { 1740, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 727, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1740 = TABLE_FILL_EXNREF_S
2110 { 1739, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 723, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1739 = TABLE_FILL_EXNREF
2111 { 1738, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 721, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1738 = TABLE_COPY_S
2112 { 1737, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 716, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1737 = TABLE_COPY
2113 { 1736, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1736 = SWIZZLE_S
2114 { 1735, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1735 = SWIZZLE
2115 { 1734, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1734 = SUB_SAT_U_I8x16_S
2116 { 1733, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1733 = SUB_SAT_U_I8x16
2117 { 1732, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1732 = SUB_SAT_U_I16x8_S
2118 { 1731, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1731 = SUB_SAT_U_I16x8
2119 { 1730, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1730 = SUB_SAT_S_I8x16_S
2120 { 1729, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1729 = SUB_SAT_S_I8x16
2121 { 1728, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1728 = SUB_SAT_S_I16x8_S
2122 { 1727, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1727 = SUB_SAT_S_I16x8
2123 { 1726, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1726 = SUB_I8x16_S
2124 { 1725, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1725 = SUB_I8x16
2125 { 1724, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1724 = SUB_I64x2_S
2126 { 1723, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1723 = SUB_I64x2
2127 { 1722, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1722 = SUB_I64_S
2128 { 1721, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1721 = SUB_I64
2129 { 1720, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1720 = SUB_I32x4_S
2130 { 1719, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1719 = SUB_I32x4
2131 { 1718, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1718 = SUB_I32_S
2132 { 1717, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1717 = SUB_I32
2133 { 1716, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1716 = SUB_I16x8_S
2134 { 1715, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1715 = SUB_I16x8
2135 { 1714, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1714 = SUB_F64x2_S
2136 { 1713, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1713 = SUB_F64x2
2137 { 1712, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1712 = SUB_F64_S
2138 { 1711, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1711 = SUB_F64
2139 { 1710, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1710 = SUB_F32x4_S
2140 { 1709, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1709 = SUB_F32x4
2141 { 1708, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1708 = SUB_F32_S
2142 { 1707, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1707 = SUB_F32
2143 { 1706, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1706 = SUB_F16x8_S
2144 { 1705, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1705 = SUB_F16x8
2145 { 1704, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1704 = STORE_V128_A64_S
2146 { 1703, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 712, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1703 = STORE_V128_A64
2147 { 1702, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1702 = STORE_V128_A32_S
2148 { 1701, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 708, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1701 = STORE_V128_A32
2149 { 1700, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1700 = STORE_LANE_I8x16_A64_S
2150 { 1699, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1699 = STORE_LANE_I8x16_A64
2151 { 1698, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1698 = STORE_LANE_I8x16_A32_S
2152 { 1697, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1697 = STORE_LANE_I8x16_A32
2153 { 1696, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1696 = STORE_LANE_I64x2_A64_S
2154 { 1695, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1695 = STORE_LANE_I64x2_A64
2155 { 1694, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1694 = STORE_LANE_I64x2_A32_S
2156 { 1693, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1693 = STORE_LANE_I64x2_A32
2157 { 1692, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1692 = STORE_LANE_I32x4_A64_S
2158 { 1691, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1691 = STORE_LANE_I32x4_A64
2159 { 1690, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1690 = STORE_LANE_I32x4_A32_S
2160 { 1689, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1689 = STORE_LANE_I32x4_A32
2161 { 1688, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1688 = STORE_LANE_I16x8_A64_S
2162 { 1687, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 703, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1687 = STORE_LANE_I16x8_A64
2163 { 1686, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1686 = STORE_LANE_I16x8_A32_S
2164 { 1685, 5, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 698, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1685 = STORE_LANE_I16x8_A32
2165 { 1684, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1684 = STORE_I64_A64_S
2166 { 1683, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1683 = STORE_I64_A64
2167 { 1682, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1682 = STORE_I64_A32_S
2168 { 1681, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1681 = STORE_I64_A32
2169 { 1680, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1680 = STORE_I32_A64_S
2170 { 1679, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1679 = STORE_I32_A64
2171 { 1678, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1678 = STORE_I32_A32_S
2172 { 1677, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1677 = STORE_I32_A32
2173 { 1676, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1676 = STORE_F64_A64_S
2174 { 1675, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 694, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1675 = STORE_F64_A64
2175 { 1674, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1674 = STORE_F64_A32_S
2176 { 1673, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 690, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1673 = STORE_F64_A32
2177 { 1672, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1672 = STORE_F32_A64_S
2178 { 1671, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 686, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1671 = STORE_F32_A64
2179 { 1670, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1670 = STORE_F32_A32_S
2180 { 1669, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 682, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1669 = STORE_F32_A32
2181 { 1668, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1668 = STORE_F16_F32_A64_S
2182 { 1667, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 686, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1667 = STORE_F16_F32_A64
2183 { 1666, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1666 = STORE_F16_F32_A32_S
2184 { 1665, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 682, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1665 = STORE_F16_F32_A32
2185 { 1664, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1664 = STORE8_I64_A64_S
2186 { 1663, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1663 = STORE8_I64_A64
2187 { 1662, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1662 = STORE8_I64_A32_S
2188 { 1661, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1661 = STORE8_I64_A32
2189 { 1660, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1660 = STORE8_I32_A64_S
2190 { 1659, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1659 = STORE8_I32_A64
2191 { 1658, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1658 = STORE8_I32_A32_S
2192 { 1657, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1657 = STORE8_I32_A32
2193 { 1656, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1656 = STORE32_I64_A64_S
2194 { 1655, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1655 = STORE32_I64_A64
2195 { 1654, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1654 = STORE32_I64_A32_S
2196 { 1653, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1653 = STORE32_I64_A32
2197 { 1652, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1652 = STORE16_I64_A64_S
2198 { 1651, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1651 = STORE16_I64_A64
2199 { 1650, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1650 = STORE16_I64_A32_S
2200 { 1649, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1649 = STORE16_I64_A32
2201 { 1648, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1648 = STORE16_I32_A64_S
2202 { 1647, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1647 = STORE16_I32_A64
2203 { 1646, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1646 = STORE16_I32_A32_S
2204 { 1645, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1645 = STORE16_I32_A32
2205 { 1644, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1644 = SQRT_F64x2_S
2206 { 1643, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1643 = SQRT_F64x2
2207 { 1642, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1642 = SQRT_F64_S
2208 { 1641, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1641 = SQRT_F64
2209 { 1640, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1640 = SQRT_F32x4_S
2210 { 1639, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1639 = SQRT_F32x4
2211 { 1638, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1638 = SQRT_F32_S
2212 { 1637, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1637 = SQRT_F32
2213 { 1636, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1636 = SQRT_F16x8_S
2214 { 1635, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1635 = SQRT_F16x8
2215 { 1634, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1634 = SPLAT_I8x16_S
2216 { 1633, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 678, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1633 = SPLAT_I8x16
2217 { 1632, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1632 = SPLAT_I64x2_S
2218 { 1631, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 680, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1631 = SPLAT_I64x2
2219 { 1630, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1630 = SPLAT_I32x4_S
2220 { 1629, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 678, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1629 = SPLAT_I32x4
2221 { 1628, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1628 = SPLAT_I16x8_S
2222 { 1627, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 678, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1627 = SPLAT_I16x8
2223 { 1626, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1626 = SPLAT_F64x2_S
2224 { 1625, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 676, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1625 = SPLAT_F64x2
2225 { 1624, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1624 = SPLAT_F32x4_S
2226 { 1623, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 674, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1623 = SPLAT_F32x4
2227 { 1622, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1622 = SPLAT_F16x8_S
2228 { 1621, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 674, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1621 = SPLAT_F16x8
2229 { 1620, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1620 = SIMD_RELAXED_FMIN_F64x2_S
2230 { 1619, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1619 = SIMD_RELAXED_FMIN_F64x2
2231 { 1618, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1618 = SIMD_RELAXED_FMIN_F32x4_S
2232 { 1617, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1617 = SIMD_RELAXED_FMIN_F32x4
2233 { 1616, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1616 = SIMD_RELAXED_FMAX_F64x2_S
2234 { 1615, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1615 = SIMD_RELAXED_FMAX_F64x2
2235 { 1614, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1614 = SIMD_RELAXED_FMAX_F32x4_S
2236 { 1613, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1613 = SIMD_RELAXED_FMAX_F32x4
2237 { 1612, 16, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 366, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1612 = SHUFFLE_S
2238 { 1611, 19, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 655, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1611 = SHUFFLE
2239 { 1610, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1610 = SHR_U_I8x16_S
2240 { 1609, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1609 = SHR_U_I8x16
2241 { 1608, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1608 = SHR_U_I64x2_S
2242 { 1607, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1607 = SHR_U_I64x2
2243 { 1606, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1606 = SHR_U_I64_S
2244 { 1605, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1605 = SHR_U_I64
2245 { 1604, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1604 = SHR_U_I32x4_S
2246 { 1603, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1603 = SHR_U_I32x4
2247 { 1602, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1602 = SHR_U_I32_S
2248 { 1601, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1601 = SHR_U_I32
2249 { 1600, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1600 = SHR_U_I16x8_S
2250 { 1599, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1599 = SHR_U_I16x8
2251 { 1598, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1598 = SHR_S_I8x16_S
2252 { 1597, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1597 = SHR_S_I8x16
2253 { 1596, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1596 = SHR_S_I64x2_S
2254 { 1595, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1595 = SHR_S_I64x2
2255 { 1594, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1594 = SHR_S_I64_S
2256 { 1593, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1593 = SHR_S_I64
2257 { 1592, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1592 = SHR_S_I32x4_S
2258 { 1591, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1591 = SHR_S_I32x4
2259 { 1590, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1590 = SHR_S_I32_S
2260 { 1589, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1589 = SHR_S_I32
2261 { 1588, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1588 = SHR_S_I16x8_S
2262 { 1587, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1587 = SHR_S_I16x8
2263 { 1586, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1586 = SHL_I8x16_S
2264 { 1585, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1585 = SHL_I8x16
2265 { 1584, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1584 = SHL_I64x2_S
2266 { 1583, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1583 = SHL_I64x2
2267 { 1582, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1582 = SHL_I64_S
2268 { 1581, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1581 = SHL_I64
2269 { 1580, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1580 = SHL_I32x4_S
2270 { 1579, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1579 = SHL_I32x4
2271 { 1578, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1578 = SHL_I32_S
2272 { 1577, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1577 = SHL_I32
2273 { 1576, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1576 = SHL_I16x8_S
2274 { 1575, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 652, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1575 = SHL_I16x8
2275 { 1574, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1574 = SELECT_V128_S
2276 { 1573, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 648, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1573 = SELECT_V128
2277 { 1572, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1572 = SELECT_I64_S
2278 { 1571, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 644, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1571 = SELECT_I64
2279 { 1570, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1570 = SELECT_I32_S
2280 { 1569, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 640, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1569 = SELECT_I32
2281 { 1568, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1568 = SELECT_FUNCREF_S
2282 { 1567, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 636, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1567 = SELECT_FUNCREF
2283 { 1566, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1566 = SELECT_F64_S
2284 { 1565, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 632, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1565 = SELECT_F64
2285 { 1564, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1564 = SELECT_F32_S
2286 { 1563, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 628, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1563 = SELECT_F32
2287 { 1562, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1562 = SELECT_EXTERNREF_S
2288 { 1561, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 624, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1561 = SELECT_EXTERNREF
2289 { 1560, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1560 = SELECT_EXNREF_S
2290 { 1559, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 620, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1559 = SELECT_EXNREF
2291 { 1558, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1558 = ROTR_I64_S
2292 { 1557, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1557 = ROTR_I64
2293 { 1556, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1556 = ROTR_I32_S
2294 { 1555, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1555 = ROTR_I32
2295 { 1554, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1554 = ROTL_I64_S
2296 { 1553, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1553 = ROTL_I64
2297 { 1552, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1552 = ROTL_I32_S
2298 { 1551, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1551 = ROTL_I32
2299 { 1550, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1550 = RET_CALL_S
2300 { 1549, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1549 = RET_CALL_INDIRECT_S
2301 { 1548, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1548 = RET_CALL_INDIRECT
2302 { 1547, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1547 = RET_CALL
2303 { 1546, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1546 = RETURN_S
2304 { 1545, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1545 = RETURN
2305 { 1544, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1544 = RETHROW_S
2306 { 1543, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1543 = RETHROW
2307 { 1542, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1542 = REPLACE_LANE_I8x16_S
2308 { 1541, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 612, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1541 = REPLACE_LANE_I8x16
2309 { 1540, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1540 = REPLACE_LANE_I64x2_S
2310 { 1539, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 616, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1539 = REPLACE_LANE_I64x2
2311 { 1538, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1538 = REPLACE_LANE_I32x4_S
2312 { 1537, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 612, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1537 = REPLACE_LANE_I32x4
2313 { 1536, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1536 = REPLACE_LANE_I16x8_S
2314 { 1535, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 612, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1535 = REPLACE_LANE_I16x8
2315 { 1534, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1534 = REPLACE_LANE_F64x2_S
2316 { 1533, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 608, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1533 = REPLACE_LANE_F64x2
2317 { 1532, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1532 = REPLACE_LANE_F32x4_S
2318 { 1531, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 604, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1531 = REPLACE_LANE_F32x4
2319 { 1530, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1530 = REM_U_I64_S
2320 { 1529, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1529 = REM_U_I64
2321 { 1528, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1528 = REM_U_I32_S
2322 { 1527, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1527 = REM_U_I32
2323 { 1526, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1526 = REM_S_I64_S
2324 { 1525, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1525 = REM_S_I64
2325 { 1524, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1524 = REM_S_I32_S
2326 { 1523, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1523 = REM_S_I32
2327 { 1522, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1522 = RELAXED_SWIZZLE_S
2328 { 1521, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1521 = RELAXED_SWIZZLE
2329 { 1520, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1520 = RELAXED_Q15MULR_S_I16x8_S
2330 { 1519, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1519 = RELAXED_Q15MULR_S_I16x8
2331 { 1518, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1518 = RELAXED_DOT_S
2332 { 1517, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1517 = RELAXED_DOT_BFLOAT_S
2333 { 1516, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1516 = RELAXED_DOT_BFLOAT
2334 { 1515, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1515 = RELAXED_DOT_ADD_S
2335 { 1514, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1514 = RELAXED_DOT_ADD
2336 { 1513, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1513 = RELAXED_DOT
2337 { 1512, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1512 = REF_NULL_FUNCREF_S
2338 { 1511, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 392, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1511 = REF_NULL_FUNCREF
2339 { 1510, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1510 = REF_NULL_EXTERNREF_S
2340 { 1509, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 389, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1509 = REF_NULL_EXTERNREF
2341 { 1508, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1508 = REF_NULL_EXNREF_S
2342 { 1507, 1, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 388, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1507 = REF_NULL_EXNREF
2343 { 1506, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1506 = REF_IS_NULL_FUNCREF_S
2344 { 1505, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 602, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1505 = REF_IS_NULL_FUNCREF
2345 { 1504, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1504 = REF_IS_NULL_EXTERNREF_S
2346 { 1503, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 600, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1503 = REF_IS_NULL_EXTERNREF
2347 { 1502, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1502 = REF_IS_NULL_EXNREF_S
2348 { 1501, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 598, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1501 = REF_IS_NULL_EXNREF
2349 { 1500, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1500 = Q15MULR_SAT_S_I16x8_S
2350 { 1499, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1499 = Q15MULR_SAT_S_I16x8
2351 { 1498, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1498 = POPCNT_I8x16_S
2352 { 1497, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1497 = POPCNT_I8x16
2353 { 1496, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1496 = POPCNT_I64_S
2354 { 1495, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1495 = POPCNT_I64
2355 { 1494, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1494 = POPCNT_I32_S
2356 { 1493, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1493 = POPCNT_I32
2357 { 1492, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1492 = PMIN_F64x2_S
2358 { 1491, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1491 = PMIN_F64x2
2359 { 1490, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1490 = PMIN_F32x4_S
2360 { 1489, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1489 = PMIN_F32x4
2361 { 1488, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1488 = PMIN_F16x8_S
2362 { 1487, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1487 = PMIN_F16x8
2363 { 1486, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1486 = PMAX_F64x2_S
2364 { 1485, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1485 = PMAX_F64x2
2365 { 1484, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1484 = PMAX_F32x4_S
2366 { 1483, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1483 = PMAX_F32x4
2367 { 1482, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1482 = PMAX_F16x8_S
2368 { 1481, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1481 = PMAX_F16x8
2369 { 1480, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1480 = OR_S
2370 { 1479, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1479 = OR_I64_S
2371 { 1478, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1478 = OR_I64
2372 { 1477, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1477 = OR_I32_S
2373 { 1476, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1476 = OR_I32
2374 { 1475, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1475 = OR
2375 { 1474, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1474 = NOT_S
2376 { 1473, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1473 = NOT
2377 { 1472, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1472 = NOP_S
2378 { 1471, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1471 = NOP
2379 { 1470, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1470 = NMADD_F64x2_S
2380 { 1469, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1469 = NMADD_F64x2
2381 { 1468, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1468 = NMADD_F32x4_S
2382 { 1467, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1467 = NMADD_F32x4
2383 { 1466, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1466 = NMADD_F16x8_S
2384 { 1465, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1465 = NMADD_F16x8
2385 { 1464, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1464 = NE_I8x16_S
2386 { 1463, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1463 = NE_I8x16
2387 { 1462, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1462 = NE_I64x2_S
2388 { 1461, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1461 = NE_I64x2
2389 { 1460, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1460 = NE_I64_S
2390 { 1459, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1459 = NE_I64
2391 { 1458, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1458 = NE_I32x4_S
2392 { 1457, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1457 = NE_I32x4
2393 { 1456, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1456 = NE_I32_S
2394 { 1455, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1455 = NE_I32
2395 { 1454, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1454 = NE_I16x8_S
2396 { 1453, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1453 = NE_I16x8
2397 { 1452, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1452 = NE_F64x2_S
2398 { 1451, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1451 = NE_F64x2
2399 { 1450, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1450 = NE_F64_S
2400 { 1449, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1449 = NE_F64
2401 { 1448, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1448 = NE_F32x4_S
2402 { 1447, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1447 = NE_F32x4
2403 { 1446, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1446 = NE_F32_S
2404 { 1445, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1445 = NE_F32
2405 { 1444, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1444 = NE_F16x8_S
2406 { 1443, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1443 = NE_F16x8
2407 { 1442, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1442 = NEG_I8x16_S
2408 { 1441, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1441 = NEG_I8x16
2409 { 1440, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1440 = NEG_I64x2_S
2410 { 1439, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1439 = NEG_I64x2
2411 { 1438, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1438 = NEG_I32x4_S
2412 { 1437, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1437 = NEG_I32x4
2413 { 1436, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1436 = NEG_I16x8_S
2414 { 1435, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1435 = NEG_I16x8
2415 { 1434, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1434 = NEG_F64x2_S
2416 { 1433, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1433 = NEG_F64x2
2417 { 1432, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1432 = NEG_F64_S
2418 { 1431, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1431 = NEG_F64
2419 { 1430, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1430 = NEG_F32x4_S
2420 { 1429, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1429 = NEG_F32x4
2421 { 1428, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1428 = NEG_F32_S
2422 { 1427, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1427 = NEG_F32
2423 { 1426, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1426 = NEG_F16x8_S
2424 { 1425, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1425 = NEG_F16x8
2425 { 1424, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1424 = NEAREST_F64x2_S
2426 { 1423, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1423 = NEAREST_F64x2
2427 { 1422, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1422 = NEAREST_F64_S
2428 { 1421, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1421 = NEAREST_F64
2429 { 1420, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1420 = NEAREST_F32x4_S
2430 { 1419, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1419 = NEAREST_F32x4
2431 { 1418, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1418 = NEAREST_F32_S
2432 { 1417, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1417 = NEAREST_F32
2433 { 1416, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1416 = NEAREST_F16x8_S
2434 { 1415, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1415 = NEAREST_F16x8
2435 { 1414, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1414 = NARROW_U_I8x16_S
2436 { 1413, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1413 = NARROW_U_I8x16
2437 { 1412, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1412 = NARROW_U_I16x8_S
2438 { 1411, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1411 = NARROW_U_I16x8
2439 { 1410, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1410 = NARROW_S_I8x16_S
2440 { 1409, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1409 = NARROW_S_I8x16
2441 { 1408, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1408 = NARROW_S_I16x8_S
2442 { 1407, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1407 = NARROW_S_I16x8
2443 { 1406, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1406 = MUL_I64x2_S
2444 { 1405, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1405 = MUL_I64x2
2445 { 1404, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1404 = MUL_I64_S
2446 { 1403, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1403 = MUL_I64
2447 { 1402, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1402 = MUL_I32x4_S
2448 { 1401, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1401 = MUL_I32x4
2449 { 1400, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1400 = MUL_I32_S
2450 { 1399, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1399 = MUL_I32
2451 { 1398, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1398 = MUL_I16x8_S
2452 { 1397, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1397 = MUL_I16x8
2453 { 1396, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1396 = MUL_F64x2_S
2454 { 1395, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1395 = MUL_F64x2
2455 { 1394, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1394 = MUL_F64_S
2456 { 1393, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1393 = MUL_F64
2457 { 1392, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1392 = MUL_F32x4_S
2458 { 1391, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1391 = MUL_F32x4
2459 { 1390, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1390 = MUL_F32_S
2460 { 1389, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1389 = MUL_F32
2461 { 1388, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1388 = MUL_F16x8_S
2462 { 1387, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1387 = MUL_F16x8
2463 { 1386, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1386 = MIN_U_I8x16_S
2464 { 1385, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1385 = MIN_U_I8x16
2465 { 1384, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1384 = MIN_U_I32x4_S
2466 { 1383, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1383 = MIN_U_I32x4
2467 { 1382, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1382 = MIN_U_I16x8_S
2468 { 1381, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1381 = MIN_U_I16x8
2469 { 1380, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1380 = MIN_S_I8x16_S
2470 { 1379, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1379 = MIN_S_I8x16
2471 { 1378, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1378 = MIN_S_I32x4_S
2472 { 1377, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1377 = MIN_S_I32x4
2473 { 1376, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1376 = MIN_S_I16x8_S
2474 { 1375, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1375 = MIN_S_I16x8
2475 { 1374, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1374 = MIN_F64x2_S
2476 { 1373, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1373 = MIN_F64x2
2477 { 1372, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1372 = MIN_F64_S
2478 { 1371, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1371 = MIN_F64
2479 { 1370, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1370 = MIN_F32x4_S
2480 { 1369, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1369 = MIN_F32x4
2481 { 1368, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1368 = MIN_F32_S
2482 { 1367, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1367 = MIN_F32
2483 { 1366, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1366 = MIN_F16x8_S
2484 { 1365, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1365 = MIN_F16x8
2485 { 1364, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1364 = MEMORY_ATOMIC_WAIT64_A64_S
2486 { 1363, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 592, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1363 = MEMORY_ATOMIC_WAIT64_A64
2487 { 1362, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1362 = MEMORY_ATOMIC_WAIT64_A32_S
2488 { 1361, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 586, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1361 = MEMORY_ATOMIC_WAIT64_A32
2489 { 1360, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1360 = MEMORY_ATOMIC_WAIT32_A64_S
2490 { 1359, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1359 = MEMORY_ATOMIC_WAIT32_A64
2491 { 1358, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1358 = MEMORY_ATOMIC_WAIT32_A32_S
2492 { 1357, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1357 = MEMORY_ATOMIC_WAIT32_A32
2493 { 1356, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1356 = MEMORY_ATOMIC_NOTIFY_A64_S
2494 { 1355, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1355 = MEMORY_ATOMIC_NOTIFY_A64
2495 { 1354, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1354 = MEMORY_ATOMIC_NOTIFY_A32_S
2496 { 1353, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1353 = MEMORY_ATOMIC_NOTIFY_A32
2497 { 1352, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1352 = MAX_U_I8x16_S
2498 { 1351, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1351 = MAX_U_I8x16
2499 { 1350, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1350 = MAX_U_I32x4_S
2500 { 1349, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1349 = MAX_U_I32x4
2501 { 1348, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1348 = MAX_U_I16x8_S
2502 { 1347, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1347 = MAX_U_I16x8
2503 { 1346, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1346 = MAX_S_I8x16_S
2504 { 1345, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1345 = MAX_S_I8x16
2505 { 1344, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1344 = MAX_S_I32x4_S
2506 { 1343, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1343 = MAX_S_I32x4
2507 { 1342, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1342 = MAX_S_I16x8_S
2508 { 1341, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1341 = MAX_S_I16x8
2509 { 1340, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1340 = MAX_F64x2_S
2510 { 1339, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1339 = MAX_F64x2
2511 { 1338, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1338 = MAX_F64_S
2512 { 1337, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1337 = MAX_F64
2513 { 1336, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1336 = MAX_F32x4_S
2514 { 1335, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1335 = MAX_F32x4
2515 { 1334, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1334 = MAX_F32_S
2516 { 1333, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1333 = MAX_F32
2517 { 1332, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1332 = MAX_F16x8_S
2518 { 1331, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1331 = MAX_F16x8
2519 { 1330, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1330 = MADD_F64x2_S
2520 { 1329, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1329 = MADD_F64x2
2521 { 1328, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1328 = MADD_F32x4_S
2522 { 1327, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1327 = MADD_F32x4
2523 { 1326, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1326 = MADD_F16x8_S
2524 { 1325, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1325 = MADD_F16x8
2525 { 1324, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1324 = LT_U_I8x16_S
2526 { 1323, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1323 = LT_U_I8x16
2527 { 1322, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1322 = LT_U_I64_S
2528 { 1321, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1321 = LT_U_I64
2529 { 1320, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1320 = LT_U_I32x4_S
2530 { 1319, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1319 = LT_U_I32x4
2531 { 1318, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1318 = LT_U_I32_S
2532 { 1317, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1317 = LT_U_I32
2533 { 1316, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1316 = LT_U_I16x8_S
2534 { 1315, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1315 = LT_U_I16x8
2535 { 1314, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1314 = LT_S_I8x16_S
2536 { 1313, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1313 = LT_S_I8x16
2537 { 1312, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1312 = LT_S_I64x2_S
2538 { 1311, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1311 = LT_S_I64x2
2539 { 1310, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1310 = LT_S_I64_S
2540 { 1309, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1309 = LT_S_I64
2541 { 1308, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1308 = LT_S_I32x4_S
2542 { 1307, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1307 = LT_S_I32x4
2543 { 1306, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1306 = LT_S_I32_S
2544 { 1305, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1305 = LT_S_I32
2545 { 1304, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1304 = LT_S_I16x8_S
2546 { 1303, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1303 = LT_S_I16x8
2547 { 1302, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1302 = LT_F64x2_S
2548 { 1301, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1301 = LT_F64x2
2549 { 1300, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1300 = LT_F64_S
2550 { 1299, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1299 = LT_F64
2551 { 1298, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1298 = LT_F32x4_S
2552 { 1297, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1297 = LT_F32x4
2553 { 1296, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1296 = LT_F32_S
2554 { 1295, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1295 = LT_F32
2555 { 1294, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1294 = LT_F16x8_S
2556 { 1293, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1293 = LT_F16x8
2557 { 1292, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1292 = LOOP_S
2558 { 1291, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1291 = LOOP
2559 { 1290, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1290 = LOCAL_TEE_V128_S
2560 { 1289, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 571, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1289 = LOCAL_TEE_V128
2561 { 1288, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1288 = LOCAL_TEE_I64_S
2562 { 1287, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 568, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1287 = LOCAL_TEE_I64
2563 { 1286, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1286 = LOCAL_TEE_I32_S
2564 { 1285, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 565, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1285 = LOCAL_TEE_I32
2565 { 1284, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1284 = LOCAL_TEE_FUNCREF_S
2566 { 1283, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 562, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1283 = LOCAL_TEE_FUNCREF
2567 { 1282, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1282 = LOCAL_TEE_F64_S
2568 { 1281, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 559, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1281 = LOCAL_TEE_F64
2569 { 1280, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1280 = LOCAL_TEE_F32_S
2570 { 1279, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 556, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1279 = LOCAL_TEE_F32
2571 { 1278, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1278 = LOCAL_TEE_EXTERNREF_S
2572 { 1277, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 553, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1277 = LOCAL_TEE_EXTERNREF
2573 { 1276, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1276 = LOCAL_TEE_EXNREF_S
2574 { 1275, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 550, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1275 = LOCAL_TEE_EXNREF
2575 { 1274, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1274 = LOCAL_SET_V128_S
2576 { 1273, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 548, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1273 = LOCAL_SET_V128
2577 { 1272, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1272 = LOCAL_SET_I64_S
2578 { 1271, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 546, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1271 = LOCAL_SET_I64
2579 { 1270, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1270 = LOCAL_SET_I32_S
2580 { 1269, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 544, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1269 = LOCAL_SET_I32
2581 { 1268, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1268 = LOCAL_SET_FUNCREF_S
2582 { 1267, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 542, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1267 = LOCAL_SET_FUNCREF
2583 { 1266, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1266 = LOCAL_SET_F64_S
2584 { 1265, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 540, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1265 = LOCAL_SET_F64
2585 { 1264, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1264 = LOCAL_SET_F32_S
2586 { 1263, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 538, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1263 = LOCAL_SET_F32
2587 { 1262, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1262 = LOCAL_SET_EXTERNREF_S
2588 { 1261, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 536, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1261 = LOCAL_SET_EXTERNREF
2589 { 1260, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1260 = LOCAL_SET_EXNREF_S
2590 { 1259, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 534, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1259 = LOCAL_SET_EXNREF
2591 { 1258, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1258 = LOCAL_GET_V128_S
2592 { 1257, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 532, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1257 = LOCAL_GET_V128
2593 { 1256, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1256 = LOCAL_GET_I64_S
2594 { 1255, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 530, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1255 = LOCAL_GET_I64
2595 { 1254, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1254 = LOCAL_GET_I32_S
2596 { 1253, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 528, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1253 = LOCAL_GET_I32
2597 { 1252, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1252 = LOCAL_GET_FUNCREF_S
2598 { 1251, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 526, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1251 = LOCAL_GET_FUNCREF
2599 { 1250, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1250 = LOCAL_GET_F64_S
2600 { 1249, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 524, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1249 = LOCAL_GET_F64
2601 { 1248, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1248 = LOCAL_GET_F32_S
2602 { 1247, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 522, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1247 = LOCAL_GET_F32
2603 { 1246, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1246 = LOCAL_GET_EXTERNREF_S
2604 { 1245, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 520, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1245 = LOCAL_GET_EXTERNREF
2605 { 1244, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 519, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1244 = LOCAL_GET_EXNREF_S
2606 { 1243, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 517, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1243 = LOCAL_GET_EXNREF
2607 { 1242, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1242 = LOAD_ZERO_I64x2_A64_S
2608 { 1241, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1241 = LOAD_ZERO_I64x2_A64
2609 { 1240, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1240 = LOAD_ZERO_I64x2_A32_S
2610 { 1239, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1239 = LOAD_ZERO_I64x2_A32
2611 { 1238, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1238 = LOAD_ZERO_I32x4_A64_S
2612 { 1237, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1237 = LOAD_ZERO_I32x4_A64
2613 { 1236, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1236 = LOAD_ZERO_I32x4_A32_S
2614 { 1235, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1235 = LOAD_ZERO_I32x4_A32
2615 { 1234, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1234 = LOAD_V128_A64_S
2616 { 1233, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1233 = LOAD_V128_A64
2617 { 1232, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1232 = LOAD_V128_A32_S
2618 { 1231, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1231 = LOAD_V128_A32
2619 { 1230, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1230 = LOAD_LANE_I8x16_A64_S
2620 { 1229, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1229 = LOAD_LANE_I8x16_A64
2621 { 1228, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1228 = LOAD_LANE_I8x16_A32_S
2622 { 1227, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1227 = LOAD_LANE_I8x16_A32
2623 { 1226, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1226 = LOAD_LANE_I64x2_A64_S
2624 { 1225, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1225 = LOAD_LANE_I64x2_A64
2625 { 1224, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1224 = LOAD_LANE_I64x2_A32_S
2626 { 1223, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1223 = LOAD_LANE_I64x2_A32
2627 { 1222, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1222 = LOAD_LANE_I32x4_A64_S
2628 { 1221, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1221 = LOAD_LANE_I32x4_A64
2629 { 1220, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1220 = LOAD_LANE_I32x4_A32_S
2630 { 1219, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1219 = LOAD_LANE_I32x4_A32
2631 { 1218, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1218 = LOAD_LANE_I16x8_A64_S
2632 { 1217, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1217 = LOAD_LANE_I16x8_A64
2633 { 1216, 3, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 505, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1216 = LOAD_LANE_I16x8_A32_S
2634 { 1215, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 499, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1215 = LOAD_LANE_I16x8_A32
2635 { 1214, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1214 = LOAD_I64_A64_S
2636 { 1213, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1213 = LOAD_I64_A64
2637 { 1212, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1212 = LOAD_I64_A32_S
2638 { 1211, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1211 = LOAD_I64_A32
2639 { 1210, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1210 = LOAD_I32_A64_S
2640 { 1209, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1209 = LOAD_I32_A64
2641 { 1208, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1208 = LOAD_I32_A32_S
2642 { 1207, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1207 = LOAD_I32_A32
2643 { 1206, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1206 = LOAD_F64_A64_S
2644 { 1205, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 495, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1205 = LOAD_F64_A64
2645 { 1204, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1204 = LOAD_F64_A32_S
2646 { 1203, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 491, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1203 = LOAD_F64_A32
2647 { 1202, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1202 = LOAD_F32_A64_S
2648 { 1201, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 487, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1201 = LOAD_F32_A64
2649 { 1200, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1200 = LOAD_F32_A32_S
2650 { 1199, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 483, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1199 = LOAD_F32_A32
2651 { 1198, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1198 = LOAD_F16_F32_A64_S
2652 { 1197, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 487, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1197 = LOAD_F16_F32_A64
2653 { 1196, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1196 = LOAD_F16_F32_A32_S
2654 { 1195, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 483, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1195 = LOAD_F16_F32_A32
2655 { 1194, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1194 = LOAD_EXTEND_U_I64x2_A64_S
2656 { 1193, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1193 = LOAD_EXTEND_U_I64x2_A64
2657 { 1192, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1192 = LOAD_EXTEND_U_I64x2_A32_S
2658 { 1191, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1191 = LOAD_EXTEND_U_I64x2_A32
2659 { 1190, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1190 = LOAD_EXTEND_U_I32x4_A64_S
2660 { 1189, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1189 = LOAD_EXTEND_U_I32x4_A64
2661 { 1188, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1188 = LOAD_EXTEND_U_I32x4_A32_S
2662 { 1187, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1187 = LOAD_EXTEND_U_I32x4_A32
2663 { 1186, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1186 = LOAD_EXTEND_U_I16x8_A64_S
2664 { 1185, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1185 = LOAD_EXTEND_U_I16x8_A64
2665 { 1184, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1184 = LOAD_EXTEND_U_I16x8_A32_S
2666 { 1183, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1183 = LOAD_EXTEND_U_I16x8_A32
2667 { 1182, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1182 = LOAD_EXTEND_S_I64x2_A64_S
2668 { 1181, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1181 = LOAD_EXTEND_S_I64x2_A64
2669 { 1180, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1180 = LOAD_EXTEND_S_I64x2_A32_S
2670 { 1179, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1179 = LOAD_EXTEND_S_I64x2_A32
2671 { 1178, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1178 = LOAD_EXTEND_S_I32x4_A64_S
2672 { 1177, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1177 = LOAD_EXTEND_S_I32x4_A64
2673 { 1176, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1176 = LOAD_EXTEND_S_I32x4_A32_S
2674 { 1175, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1175 = LOAD_EXTEND_S_I32x4_A32
2675 { 1174, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1174 = LOAD_EXTEND_S_I16x8_A64_S
2676 { 1173, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1173 = LOAD_EXTEND_S_I16x8_A64
2677 { 1172, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1172 = LOAD_EXTEND_S_I16x8_A32_S
2678 { 1171, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1171 = LOAD_EXTEND_S_I16x8_A32
2679 { 1170, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1170 = LOAD8_U_I64_A64_S
2680 { 1169, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1169 = LOAD8_U_I64_A64
2681 { 1168, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1168 = LOAD8_U_I64_A32_S
2682 { 1167, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1167 = LOAD8_U_I64_A32
2683 { 1166, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1166 = LOAD8_U_I32_A64_S
2684 { 1165, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1165 = LOAD8_U_I32_A64
2685 { 1164, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1164 = LOAD8_U_I32_A32_S
2686 { 1163, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1163 = LOAD8_U_I32_A32
2687 { 1162, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1162 = LOAD8_S_I64_A64_S
2688 { 1161, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1161 = LOAD8_S_I64_A64
2689 { 1160, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1160 = LOAD8_S_I64_A32_S
2690 { 1159, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1159 = LOAD8_S_I64_A32
2691 { 1158, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1158 = LOAD8_S_I32_A64_S
2692 { 1157, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1157 = LOAD8_S_I32_A64
2693 { 1156, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1156 = LOAD8_S_I32_A32_S
2694 { 1155, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1155 = LOAD8_S_I32_A32
2695 { 1154, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1154 = LOAD8_SPLAT_A64_S
2696 { 1153, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1153 = LOAD8_SPLAT_A64
2697 { 1152, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1152 = LOAD8_SPLAT_A32_S
2698 { 1151, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1151 = LOAD8_SPLAT_A32
2699 { 1150, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1150 = LOAD64_SPLAT_A64_S
2700 { 1149, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1149 = LOAD64_SPLAT_A64
2701 { 1148, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1148 = LOAD64_SPLAT_A32_S
2702 { 1147, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1147 = LOAD64_SPLAT_A32
2703 { 1146, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1146 = LOAD32_U_I64_A64_S
2704 { 1145, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1145 = LOAD32_U_I64_A64
2705 { 1144, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1144 = LOAD32_U_I64_A32_S
2706 { 1143, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1143 = LOAD32_U_I64_A32
2707 { 1142, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1142 = LOAD32_S_I64_A64_S
2708 { 1141, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1141 = LOAD32_S_I64_A64
2709 { 1140, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1140 = LOAD32_S_I64_A32_S
2710 { 1139, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1139 = LOAD32_S_I64_A32
2711 { 1138, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1138 = LOAD32_SPLAT_A64_S
2712 { 1137, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1137 = LOAD32_SPLAT_A64
2713 { 1136, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1136 = LOAD32_SPLAT_A32_S
2714 { 1135, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1135 = LOAD32_SPLAT_A32
2715 { 1134, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1134 = LOAD16_U_I64_A64_S
2716 { 1133, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1133 = LOAD16_U_I64_A64
2717 { 1132, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1132 = LOAD16_U_I64_A32_S
2718 { 1131, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1131 = LOAD16_U_I64_A32
2719 { 1130, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1130 = LOAD16_U_I32_A64_S
2720 { 1129, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1129 = LOAD16_U_I32_A64
2721 { 1128, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1128 = LOAD16_U_I32_A32_S
2722 { 1127, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1127 = LOAD16_U_I32_A32
2723 { 1126, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1126 = LOAD16_S_I64_A64_S
2724 { 1125, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1125 = LOAD16_S_I64_A64
2725 { 1124, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1124 = LOAD16_S_I64_A32_S
2726 { 1123, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1123 = LOAD16_S_I64_A32
2727 { 1122, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1122 = LOAD16_S_I32_A64_S
2728 { 1121, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1121 = LOAD16_S_I32_A64
2729 { 1120, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1120 = LOAD16_S_I32_A32_S
2730 { 1119, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1119 = LOAD16_S_I32_A32
2731 { 1118, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1118 = LOAD16_SPLAT_A64_S
2732 { 1117, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 479, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1117 = LOAD16_SPLAT_A64
2733 { 1116, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1116 = LOAD16_SPLAT_A32_S
2734 { 1115, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1115 = LOAD16_SPLAT_A32
2735 { 1114, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1114 = LE_U_I8x16_S
2736 { 1113, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1113 = LE_U_I8x16
2737 { 1112, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1112 = LE_U_I64_S
2738 { 1111, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1111 = LE_U_I64
2739 { 1110, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1110 = LE_U_I32x4_S
2740 { 1109, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1109 = LE_U_I32x4
2741 { 1108, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1108 = LE_U_I32_S
2742 { 1107, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1107 = LE_U_I32
2743 { 1106, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1106 = LE_U_I16x8_S
2744 { 1105, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1105 = LE_U_I16x8
2745 { 1104, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1104 = LE_S_I8x16_S
2746 { 1103, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1103 = LE_S_I8x16
2747 { 1102, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1102 = LE_S_I64x2_S
2748 { 1101, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1101 = LE_S_I64x2
2749 { 1100, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1100 = LE_S_I64_S
2750 { 1099, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1099 = LE_S_I64
2751 { 1098, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1098 = LE_S_I32x4_S
2752 { 1097, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1097 = LE_S_I32x4
2753 { 1096, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1096 = LE_S_I32_S
2754 { 1095, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1095 = LE_S_I32
2755 { 1094, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1094 = LE_S_I16x8_S
2756 { 1093, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1093 = LE_S_I16x8
2757 { 1092, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1092 = LE_F64x2_S
2758 { 1091, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1091 = LE_F64x2
2759 { 1090, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1090 = LE_F64_S
2760 { 1089, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1089 = LE_F64
2761 { 1088, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1088 = LE_F32x4_S
2762 { 1087, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1087 = LE_F32x4
2763 { 1086, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1086 = LE_F32_S
2764 { 1085, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1085 = LE_F32
2765 { 1084, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1084 = LE_F16x8_S
2766 { 1083, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1083 = LE_F16x8
2767 { 1082, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1082 = LANESELECT_I8x16_S
2768 { 1081, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1081 = LANESELECT_I8x16
2769 { 1080, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1080 = LANESELECT_I64x2_S
2770 { 1079, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1079 = LANESELECT_I64x2
2771 { 1078, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1078 = LANESELECT_I32x4_S
2772 { 1077, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1077 = LANESELECT_I32x4
2773 { 1076, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1076 = LANESELECT_I16x8_S
2774 { 1075, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1075 = LANESELECT_I16x8
2775 { 1074, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1074 = IF_S
2776 { 1073, 2, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 473, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1073 = IF
2777 { 1072, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1072 = I64_TRUNC_U_SAT_F64_S
2778 { 1071, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1071 = I64_TRUNC_U_SAT_F64
2779 { 1070, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1070 = I64_TRUNC_U_SAT_F32_S
2780 { 1069, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1069 = I64_TRUNC_U_SAT_F32
2781 { 1068, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1068 = I64_TRUNC_U_F64_S
2782 { 1067, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1067 = I64_TRUNC_U_F64
2783 { 1066, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1066 = I64_TRUNC_U_F32_S
2784 { 1065, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1065 = I64_TRUNC_U_F32
2785 { 1064, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1064 = I64_TRUNC_S_SAT_F64_S
2786 { 1063, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1063 = I64_TRUNC_S_SAT_F64
2787 { 1062, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1062 = I64_TRUNC_S_SAT_F32_S
2788 { 1061, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1061 = I64_TRUNC_S_SAT_F32
2789 { 1060, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1060 = I64_TRUNC_S_F64_S
2790 { 1059, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1059 = I64_TRUNC_S_F64
2791 { 1058, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1058 = I64_TRUNC_S_F32_S
2792 { 1057, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1057 = I64_TRUNC_S_F32
2793 { 1056, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1056 = I64_REINTERPRET_F64_S
2794 { 1055, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1055 = I64_REINTERPRET_F64
2795 { 1054, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1054 = I64_EXTEND_U_I32_S
2796 { 1053, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 471, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1053 = I64_EXTEND_U_I32
2797 { 1052, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1052 = I64_EXTEND_S_I32_S
2798 { 1051, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 471, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1051 = I64_EXTEND_S_I32
2799 { 1050, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1050 = I64_EXTEND8_S_I64_S
2800 { 1049, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1049 = I64_EXTEND8_S_I64
2801 { 1048, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1048 = I64_EXTEND32_S_I64_S
2802 { 1047, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1047 = I64_EXTEND32_S_I64
2803 { 1046, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1046 = I64_EXTEND16_S_I64_S
2804 { 1045, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1045 = I64_EXTEND16_S_I64
2805 { 1044, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1044 = I32_WRAP_I64_S
2806 { 1043, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 394, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1043 = I32_WRAP_I64
2807 { 1042, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1042 = I32_TRUNC_U_SAT_F64_S
2808 { 1041, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1041 = I32_TRUNC_U_SAT_F64
2809 { 1040, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1040 = I32_TRUNC_U_SAT_F32_S
2810 { 1039, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1039 = I32_TRUNC_U_SAT_F32
2811 { 1038, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1038 = I32_TRUNC_U_F64_S
2812 { 1037, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1037 = I32_TRUNC_U_F64
2813 { 1036, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1036 = I32_TRUNC_U_F32_S
2814 { 1035, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1035 = I32_TRUNC_U_F32
2815 { 1034, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1034 = I32_TRUNC_S_SAT_F64_S
2816 { 1033, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1033 = I32_TRUNC_S_SAT_F64
2817 { 1032, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1032 = I32_TRUNC_S_SAT_F32_S
2818 { 1031, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1031 = I32_TRUNC_S_SAT_F32
2819 { 1030, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1030 = I32_TRUNC_S_F64_S
2820 { 1029, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1029 = I32_TRUNC_S_F64
2821 { 1028, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1028 = I32_TRUNC_S_F32_S
2822 { 1027, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1027 = I32_TRUNC_S_F32
2823 { 1026, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1026 = I32_REINTERPRET_F32_S
2824 { 1025, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1025 = I32_REINTERPRET_F32
2825 { 1024, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1024 = I32_EXTEND8_S_I32_S
2826 { 1023, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1023 = I32_EXTEND8_S_I32
2827 { 1022, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1022 = I32_EXTEND16_S_I32_S
2828 { 1021, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1021 = I32_EXTEND16_S_I32
2829 { 1020, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1020 = GT_U_I8x16_S
2830 { 1019, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1019 = GT_U_I8x16
2831 { 1018, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1018 = GT_U_I64_S
2832 { 1017, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1017 = GT_U_I64
2833 { 1016, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1016 = GT_U_I32x4_S
2834 { 1015, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1015 = GT_U_I32x4
2835 { 1014, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1014 = GT_U_I32_S
2836 { 1013, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1013 = GT_U_I32
2837 { 1012, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1012 = GT_U_I16x8_S
2838 { 1011, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1011 = GT_U_I16x8
2839 { 1010, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1010 = GT_S_I8x16_S
2840 { 1009, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1009 = GT_S_I8x16
2841 { 1008, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1008 = GT_S_I64x2_S
2842 { 1007, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1007 = GT_S_I64x2
2843 { 1006, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1006 = GT_S_I64_S
2844 { 1005, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1005 = GT_S_I64
2845 { 1004, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1004 = GT_S_I32x4_S
2846 { 1003, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1003 = GT_S_I32x4
2847 { 1002, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1002 = GT_S_I32_S
2848 { 1001, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1001 = GT_S_I32
2849 { 1000, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1000 = GT_S_I16x8_S
2850 { 999, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #999 = GT_S_I16x8
2851 { 998, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #998 = GT_F64x2_S
2852 { 997, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #997 = GT_F64x2
2853 { 996, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #996 = GT_F64_S
2854 { 995, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #995 = GT_F64
2855 { 994, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #994 = GT_F32x4_S
2856 { 993, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #993 = GT_F32x4
2857 { 992, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #992 = GT_F32_S
2858 { 991, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #991 = GT_F32
2859 { 990, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #990 = GT_F16x8_S
2860 { 989, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #989 = GT_F16x8
2861 { 988, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #988 = GLOBAL_SET_V128_S
2862 { 987, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 469, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #987 = GLOBAL_SET_V128
2863 { 986, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #986 = GLOBAL_SET_I64_S
2864 { 985, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 467, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #985 = GLOBAL_SET_I64
2865 { 984, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #984 = GLOBAL_SET_I32_S
2866 { 983, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 465, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #983 = GLOBAL_SET_I32
2867 { 982, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #982 = GLOBAL_SET_FUNCREF_S
2868 { 981, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 463, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #981 = GLOBAL_SET_FUNCREF
2869 { 980, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #980 = GLOBAL_SET_F64_S
2870 { 979, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 461, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #979 = GLOBAL_SET_F64
2871 { 978, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #978 = GLOBAL_SET_F32_S
2872 { 977, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 459, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #977 = GLOBAL_SET_F32
2873 { 976, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #976 = GLOBAL_SET_EXTERNREF_S
2874 { 975, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 457, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #975 = GLOBAL_SET_EXTERNREF
2875 { 974, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #974 = GLOBAL_SET_EXNREF_S
2876 { 973, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #973 = GLOBAL_SET_EXNREF
2877 { 972, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #972 = GLOBAL_GET_V128_S
2878 { 971, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 453, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #971 = GLOBAL_GET_V128
2879 { 970, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #970 = GLOBAL_GET_I64_S
2880 { 969, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 451, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #969 = GLOBAL_GET_I64
2881 { 968, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #968 = GLOBAL_GET_I32_S
2882 { 967, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 449, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #967 = GLOBAL_GET_I32
2883 { 966, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #966 = GLOBAL_GET_FUNCREF_S
2884 { 965, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 447, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #965 = GLOBAL_GET_FUNCREF
2885 { 964, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #964 = GLOBAL_GET_F64_S
2886 { 963, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 445, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #963 = GLOBAL_GET_F64
2887 { 962, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #962 = GLOBAL_GET_F32_S
2888 { 961, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 443, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #961 = GLOBAL_GET_F32
2889 { 960, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #960 = GLOBAL_GET_EXTERNREF_S
2890 { 959, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 441, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #959 = GLOBAL_GET_EXTERNREF
2891 { 958, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 440, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #958 = GLOBAL_GET_EXNREF_S
2892 { 957, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 438, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #957 = GLOBAL_GET_EXNREF
2893 { 956, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #956 = GE_U_I8x16_S
2894 { 955, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #955 = GE_U_I8x16
2895 { 954, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #954 = GE_U_I64_S
2896 { 953, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #953 = GE_U_I64
2897 { 952, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #952 = GE_U_I32x4_S
2898 { 951, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #951 = GE_U_I32x4
2899 { 950, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #950 = GE_U_I32_S
2900 { 949, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #949 = GE_U_I32
2901 { 948, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #948 = GE_U_I16x8_S
2902 { 947, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #947 = GE_U_I16x8
2903 { 946, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #946 = GE_S_I8x16_S
2904 { 945, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #945 = GE_S_I8x16
2905 { 944, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #944 = GE_S_I64x2_S
2906 { 943, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #943 = GE_S_I64x2
2907 { 942, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #942 = GE_S_I64_S
2908 { 941, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #941 = GE_S_I64
2909 { 940, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #940 = GE_S_I32x4_S
2910 { 939, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #939 = GE_S_I32x4
2911 { 938, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #938 = GE_S_I32_S
2912 { 937, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #937 = GE_S_I32
2913 { 936, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #936 = GE_S_I16x8_S
2914 { 935, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #935 = GE_S_I16x8
2915 { 934, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #934 = GE_F64x2_S
2916 { 933, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #933 = GE_F64x2
2917 { 932, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #932 = GE_F64_S
2918 { 931, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #931 = GE_F64
2919 { 930, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #930 = GE_F32x4_S
2920 { 929, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #929 = GE_F32x4
2921 { 928, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #928 = GE_F32_S
2922 { 927, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #927 = GE_F32
2923 { 926, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #926 = GE_F16x8_S
2924 { 925, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #925 = GE_F16x8
2925 { 924, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #924 = FP_TO_UINT_I64_F64_S
2926 { 923, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #923 = FP_TO_UINT_I64_F64
2927 { 922, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #922 = FP_TO_UINT_I64_F32_S
2928 { 921, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #921 = FP_TO_UINT_I64_F32
2929 { 920, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #920 = FP_TO_UINT_I32_F64_S
2930 { 919, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #919 = FP_TO_UINT_I32_F64
2931 { 918, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #918 = FP_TO_UINT_I32_F32_S
2932 { 917, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #917 = FP_TO_UINT_I32_F32
2933 { 916, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #916 = FP_TO_SINT_I64_F64_S
2934 { 915, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 436, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #915 = FP_TO_SINT_I64_F64
2935 { 914, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #914 = FP_TO_SINT_I64_F32_S
2936 { 913, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 434, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #913 = FP_TO_SINT_I64_F32
2937 { 912, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #912 = FP_TO_SINT_I32_F64_S
2938 { 911, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 432, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #911 = FP_TO_SINT_I32_F64
2939 { 910, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #910 = FP_TO_SINT_I32_F32_S
2940 { 909, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 430, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #909 = FP_TO_SINT_I32_F32
2941 { 908, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #908 = FLOOR_F64x2_S
2942 { 907, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #907 = FLOOR_F64x2
2943 { 906, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #906 = FLOOR_F64_S
2944 { 905, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #905 = FLOOR_F64
2945 { 904, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #904 = FLOOR_F32x4_S
2946 { 903, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #903 = FLOOR_F32x4
2947 { 902, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #902 = FLOOR_F32_S
2948 { 901, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #901 = FLOOR_F32
2949 { 900, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #900 = FLOOR_F16x8_S
2950 { 899, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #899 = FLOOR_F16x8
2951 { 898, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #898 = FALLTHROUGH_RETURN_S
2952 { 897, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #897 = FALLTHROUGH_RETURN
2953 { 896, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #896 = F64_REINTERPRET_I64_S
2954 { 895, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 426, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #895 = F64_REINTERPRET_I64
2955 { 894, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #894 = F64_PROMOTE_F32_S
2956 { 893, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 428, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #893 = F64_PROMOTE_F32
2957 { 892, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #892 = F64_CONVERT_U_I64_S
2958 { 891, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 426, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #891 = F64_CONVERT_U_I64
2959 { 890, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #890 = F64_CONVERT_U_I32_S
2960 { 889, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 424, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #889 = F64_CONVERT_U_I32
2961 { 888, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #888 = F64_CONVERT_S_I64_S
2962 { 887, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 426, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #887 = F64_CONVERT_S_I64
2963 { 886, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #886 = F64_CONVERT_S_I32_S
2964 { 885, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 424, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #885 = F64_CONVERT_S_I32
2965 { 884, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #884 = F32_REINTERPRET_I32_S
2966 { 883, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 418, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #883 = F32_REINTERPRET_I32
2967 { 882, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #882 = F32_DEMOTE_F64_S
2968 { 881, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 422, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #881 = F32_DEMOTE_F64
2969 { 880, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #880 = F32_CONVERT_U_I64_S
2970 { 879, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 420, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #879 = F32_CONVERT_U_I64
2971 { 878, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #878 = F32_CONVERT_U_I32_S
2972 { 877, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 418, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #877 = F32_CONVERT_U_I32
2973 { 876, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #876 = F32_CONVERT_S_I64_S
2974 { 875, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 420, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #875 = F32_CONVERT_S_I64
2975 { 874, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #874 = F32_CONVERT_S_I32_S
2976 { 873, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 418, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #873 = F32_CONVERT_S_I32
2977 { 872, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #872 = EXTRACT_LANE_I8x16_u_S
2978 { 871, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #871 = EXTRACT_LANE_I8x16_u
2979 { 870, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #870 = EXTRACT_LANE_I8x16_s_S
2980 { 869, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #869 = EXTRACT_LANE_I8x16_s
2981 { 868, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #868 = EXTRACT_LANE_I64x2_S
2982 { 867, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 415, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #867 = EXTRACT_LANE_I64x2
2983 { 866, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #866 = EXTRACT_LANE_I32x4_S
2984 { 865, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #865 = EXTRACT_LANE_I32x4
2985 { 864, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #864 = EXTRACT_LANE_I16x8_u_S
2986 { 863, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #863 = EXTRACT_LANE_I16x8_u
2987 { 862, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #862 = EXTRACT_LANE_I16x8_s_S
2988 { 861, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 412, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #861 = EXTRACT_LANE_I16x8_s
2989 { 860, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #860 = EXTRACT_LANE_F64x2_S
2990 { 859, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 409, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #859 = EXTRACT_LANE_F64x2
2991 { 858, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #858 = EXTRACT_LANE_F32x4_S
2992 { 857, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 405, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #857 = EXTRACT_LANE_F32x4
2993 { 856, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 408, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #856 = EXTRACT_LANE_F16x8_S
2994 { 855, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 405, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #855 = EXTRACT_LANE_F16x8
2995 { 854, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #854 = EXTMUL_LOW_U_I64x2_S
2996 { 853, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #853 = EXTMUL_LOW_U_I64x2
2997 { 852, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #852 = EXTMUL_LOW_U_I32x4_S
2998 { 851, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #851 = EXTMUL_LOW_U_I32x4
2999 { 850, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #850 = EXTMUL_LOW_U_I16x8_S
3000 { 849, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #849 = EXTMUL_LOW_U_I16x8
3001 { 848, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #848 = EXTMUL_LOW_S_I64x2_S
3002 { 847, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #847 = EXTMUL_LOW_S_I64x2
3003 { 846, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #846 = EXTMUL_LOW_S_I32x4_S
3004 { 845, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #845 = EXTMUL_LOW_S_I32x4
3005 { 844, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #844 = EXTMUL_LOW_S_I16x8_S
3006 { 843, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #843 = EXTMUL_LOW_S_I16x8
3007 { 842, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #842 = EXTMUL_HIGH_U_I64x2_S
3008 { 841, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #841 = EXTMUL_HIGH_U_I64x2
3009 { 840, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #840 = EXTMUL_HIGH_U_I32x4_S
3010 { 839, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #839 = EXTMUL_HIGH_U_I32x4
3011 { 838, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #838 = EXTMUL_HIGH_U_I16x8_S
3012 { 837, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #837 = EXTMUL_HIGH_U_I16x8
3013 { 836, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #836 = EXTMUL_HIGH_S_I64x2_S
3014 { 835, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #835 = EXTMUL_HIGH_S_I64x2
3015 { 834, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #834 = EXTMUL_HIGH_S_I32x4_S
3016 { 833, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #833 = EXTMUL_HIGH_S_I32x4
3017 { 832, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #832 = EXTMUL_HIGH_S_I16x8_S
3018 { 831, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #831 = EXTMUL_HIGH_S_I16x8
3019 { 830, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #830 = EQ_I8x16_S
3020 { 829, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #829 = EQ_I8x16
3021 { 828, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #828 = EQ_I64x2_S
3022 { 827, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #827 = EQ_I64x2
3023 { 826, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #826 = EQ_I64_S
3024 { 825, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 402, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #825 = EQ_I64
3025 { 824, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #824 = EQ_I32x4_S
3026 { 823, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #823 = EQ_I32x4
3027 { 822, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #822 = EQ_I32_S
3028 { 821, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #821 = EQ_I32
3029 { 820, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #820 = EQ_I16x8_S
3030 { 819, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #819 = EQ_I16x8
3031 { 818, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #818 = EQ_F64x2_S
3032 { 817, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #817 = EQ_F64x2
3033 { 816, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #816 = EQ_F64_S
3034 { 815, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 399, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #815 = EQ_F64
3035 { 814, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #814 = EQ_F32x4_S
3036 { 813, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #813 = EQ_F32x4
3037 { 812, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #812 = EQ_F32_S
3038 { 811, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 396, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #811 = EQ_F32
3039 { 810, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #810 = EQ_F16x8_S
3040 { 809, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #809 = EQ_F16x8
3041 { 808, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #808 = EQZ_I64_S
3042 { 807, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 394, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #807 = EQZ_I64
3043 { 806, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #806 = EQZ_I32_S
3044 { 805, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #805 = EQZ_I32
3045 { 804, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #804 = END_TRY_S
3046 { 803, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #803 = END_TRY
3047 { 802, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #802 = END_S
3048 { 801, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #801 = END_LOOP_S
3049 { 800, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #800 = END_LOOP
3050 { 799, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #799 = END_IF_S
3051 { 798, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #798 = END_IF
3052 { 797, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #797 = END_FUNCTION_S
3053 { 796, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #796 = END_FUNCTION
3054 { 795, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #795 = END_BLOCK_S
3055 { 794, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #794 = END_BLOCK
3056 { 793, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #793 = END
3057 { 792, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #792 = ELSE_S
3058 { 791, 0, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #791 = ELSE
3059 { 790, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #790 = DROP_V128_S
3060 { 789, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 393, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #789 = DROP_V128
3061 { 788, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #788 = DROP_I64_S
3062 { 787, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 284, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #787 = DROP_I64
3063 { 786, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #786 = DROP_I32_S
3064 { 785, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 282, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #785 = DROP_I32
3065 { 784, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #784 = DROP_FUNCREF_S
3066 { 783, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 392, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #783 = DROP_FUNCREF
3067 { 782, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #782 = DROP_F64_S
3068 { 781, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 391, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #781 = DROP_F64
3069 { 780, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #780 = DROP_F32_S
3070 { 779, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 390, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #779 = DROP_F32
3071 { 778, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #778 = DROP_EXTERNREF_S
3072 { 777, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 389, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #777 = DROP_EXTERNREF
3073 { 776, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #776 = DROP_EXNREF_S
3074 { 775, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 388, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #775 = DROP_EXNREF
3075 { 774, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #774 = DOT_S
3076 { 773, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #773 = DOT
3077 { 772, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #772 = DIV_U_I64_S
3078 { 771, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #771 = DIV_U_I64
3079 { 770, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #770 = DIV_U_I32_S
3080 { 769, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #769 = DIV_U_I32
3081 { 768, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #768 = DIV_S_I64_S
3082 { 767, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #767 = DIV_S_I64
3083 { 766, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #766 = DIV_S_I32_S
3084 { 765, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #765 = DIV_S_I32
3085 { 764, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #764 = DIV_F64x2_S
3086 { 763, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #763 = DIV_F64x2
3087 { 762, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #762 = DIV_F64_S
3088 { 761, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #761 = DIV_F64
3089 { 760, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #760 = DIV_F32x4_S
3090 { 759, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #759 = DIV_F32x4
3091 { 758, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #758 = DIV_F32_S
3092 { 757, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #757 = DIV_F32
3093 { 756, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #756 = DIV_F16x8_S
3094 { 755, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #755 = DIV_F16x8
3095 { 754, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #754 = DELEGATE_S
3096 { 753, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #753 = DELEGATE
3097 { 752, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #752 = DEBUG_UNREACHABLE_S
3098 { 751, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Trap)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #751 = DEBUG_UNREACHABLE
3099 { 750, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #750 = CTZ_I64_S
3100 { 749, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #749 = CTZ_I64
3101 { 748, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #748 = CTZ_I32_S
3102 { 747, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #747 = CTZ_I32
3103 { 746, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #746 = COPY_V128_S
3104 { 745, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #745 = COPY_V128
3105 { 744, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #744 = COPY_I64_S
3106 { 743, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #743 = COPY_I64
3107 { 742, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #742 = COPY_I32_S
3108 { 741, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #741 = COPY_I32
3109 { 740, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #740 = COPY_FUNCREF_S
3110 { 739, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 386, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #739 = COPY_FUNCREF
3111 { 738, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #738 = COPY_F64_S
3112 { 737, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #737 = COPY_F64
3113 { 736, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #736 = COPY_F32_S
3114 { 735, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #735 = COPY_F32
3115 { 734, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #734 = COPY_EXTERNREF_S
3116 { 733, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 384, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #733 = COPY_EXTERNREF
3117 { 732, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #732 = COPY_EXNREF_S
3118 { 731, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 382, 0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #731 = COPY_EXNREF
3119 { 730, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #730 = COPYSIGN_F64_S
3120 { 729, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #729 = COPYSIGN_F64
3121 { 728, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #728 = COPYSIGN_F32_S
3122 { 727, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #727 = COPYSIGN_F32
3123 { 726, 16, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 366, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #726 = CONST_V128_I8x16_S
3124 { 725, 17, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 349, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #725 = CONST_V128_I8x16
3125 { 724, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 347, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #724 = CONST_V128_I64x2_S
3126 { 723, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 344, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #723 = CONST_V128_I64x2
3127 { 722, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 340, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #722 = CONST_V128_I32x4_S
3128 { 721, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 335, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #721 = CONST_V128_I32x4
3129 { 720, 8, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 327, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #720 = CONST_V128_I16x8_S
3130 { 719, 9, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 318, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #719 = CONST_V128_I16x8
3131 { 718, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 316, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #718 = CONST_V128_F64x2_S
3132 { 717, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 313, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #717 = CONST_V128_F64x2
3133 { 716, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 309, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #716 = CONST_V128_F32x4_S
3134 { 715, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 304, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #715 = CONST_V128_F32x4
3135 { 714, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 303, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #714 = CONST_I64_S
3136 { 713, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 301, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #713 = CONST_I64
3137 { 712, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 300, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #712 = CONST_I32_S
3138 { 711, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 298, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #711 = CONST_I32
3139 { 710, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 297, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #710 = CONST_F64_S
3140 { 709, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 295, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #709 = CONST_F64
3141 { 708, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 294, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #708 = CONST_F32_S
3142 { 707, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 292, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #707 = CONST_F32
3143 { 706, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #706 = CLZ_I64_S
3144 { 705, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 290, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #705 = CLZ_I64
3145 { 704, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #704 = CLZ_I32_S
3146 { 703, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 288, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #703 = CLZ_I32
3147 { 702, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #702 = CEIL_F64x2_S
3148 { 701, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #701 = CEIL_F64x2
3149 { 700, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #700 = CEIL_F64_S
3150 { 699, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #699 = CEIL_F64
3151 { 698, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #698 = CEIL_F32x4_S
3152 { 697, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #697 = CEIL_F32x4
3153 { 696, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #696 = CEIL_F32_S
3154 { 695, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #695 = CEIL_F32
3155 { 694, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #694 = CEIL_F16x8_S
3156 { 693, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #693 = CEIL_F16x8
3157 { 692, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #692 = CATCH_S
3158 { 691, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #691 = CATCH_ALL_S
3159 { 690, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #690 = CATCH_ALL
3160 { 689, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 287, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #689 = CATCH
3161 { 688, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #688 = CALL_S
3162 { 687, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #687 = CALL_INDIRECT_S
3163 { 686, 2, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 285, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #686 = CALL_INDIRECT
3164 { 685, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #685 = CALL
3165 { 684, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #684 = BR_UNLESS_S
3166 { 683, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 280, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #683 = BR_UNLESS
3167 { 682, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 283, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #682 = BR_TABLE_I64_S
3168 { 681, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 284, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #681 = BR_TABLE_I64
3169 { 680, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 283, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #680 = BR_TABLE_I32_S
3170 { 679, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 282, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #679 = BR_TABLE_I32
3171 { 678, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #678 = BR_S
3172 { 677, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #677 = BR_IF_S
3173 { 676, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 280, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #676 = BR_IF
3174 { 675, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 279, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #675 = BR
3175 { 674, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #674 = BLOCK_S
3176 { 673, 1, 0, 0, 0, 1, 1, WebAssemblyImpOpBase + 8, 278, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #673 = BLOCK
3177 { 672, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #672 = BITSELECT_S
3178 { 671, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 274, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #671 = BITSELECT
3179 { 670, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #670 = BITMASK_I8x16_S
3180 { 669, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #669 = BITMASK_I8x16
3181 { 668, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #668 = BITMASK_I64x2_S
3182 { 667, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #667 = BITMASK_I64x2
3183 { 666, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #666 = BITMASK_I32x4_S
3184 { 665, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #665 = BITMASK_I32x4
3185 { 664, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #664 = BITMASK_I16x8_S
3186 { 663, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #663 = BITMASK_I16x8
3187 { 662, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #662 = AVGR_U_I8x16_S
3188 { 661, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #661 = AVGR_U_I8x16
3189 { 660, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #660 = AVGR_U_I16x8_S
3190 { 659, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #659 = AVGR_U_I16x8
3191 { 658, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #658 = ATOMIC_STORE_I64_A64_S
3192 { 657, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #657 = ATOMIC_STORE_I64_A64
3193 { 656, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #656 = ATOMIC_STORE_I64_A32_S
3194 { 655, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #655 = ATOMIC_STORE_I64_A32
3195 { 654, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #654 = ATOMIC_STORE_I32_A64_S
3196 { 653, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #653 = ATOMIC_STORE_I32_A64
3197 { 652, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #652 = ATOMIC_STORE_I32_A32_S
3198 { 651, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #651 = ATOMIC_STORE_I32_A32
3199 { 650, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #650 = ATOMIC_STORE8_I64_A64_S
3200 { 649, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #649 = ATOMIC_STORE8_I64_A64
3201 { 648, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #648 = ATOMIC_STORE8_I64_A32_S
3202 { 647, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #647 = ATOMIC_STORE8_I64_A32
3203 { 646, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #646 = ATOMIC_STORE8_I32_A64_S
3204 { 645, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #645 = ATOMIC_STORE8_I32_A64
3205 { 644, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #644 = ATOMIC_STORE8_I32_A32_S
3206 { 643, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #643 = ATOMIC_STORE8_I32_A32
3207 { 642, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #642 = ATOMIC_STORE32_I64_A64_S
3208 { 641, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #641 = ATOMIC_STORE32_I64_A64
3209 { 640, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #640 = ATOMIC_STORE32_I64_A32_S
3210 { 639, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #639 = ATOMIC_STORE32_I64_A32
3211 { 638, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #638 = ATOMIC_STORE16_I64_A64_S
3212 { 637, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 270, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #637 = ATOMIC_STORE16_I64_A64
3213 { 636, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #636 = ATOMIC_STORE16_I64_A32_S
3214 { 635, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 266, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #635 = ATOMIC_STORE16_I64_A32
3215 { 634, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #634 = ATOMIC_STORE16_I32_A64_S
3216 { 633, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 262, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #633 = ATOMIC_STORE16_I32_A64
3217 { 632, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #632 = ATOMIC_STORE16_I32_A32_S
3218 { 631, 4, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 258, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #631 = ATOMIC_STORE16_I32_A32
3219 { 630, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #630 = ATOMIC_RMW_XOR_I64_A64_S
3220 { 629, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #629 = ATOMIC_RMW_XOR_I64_A64
3221 { 628, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #628 = ATOMIC_RMW_XOR_I64_A32_S
3222 { 627, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #627 = ATOMIC_RMW_XOR_I64_A32
3223 { 626, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #626 = ATOMIC_RMW_XOR_I32_A64_S
3224 { 625, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #625 = ATOMIC_RMW_XOR_I32_A64
3225 { 624, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #624 = ATOMIC_RMW_XOR_I32_A32_S
3226 { 623, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #623 = ATOMIC_RMW_XOR_I32_A32
3227 { 622, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #622 = ATOMIC_RMW_XCHG_I64_A64_S
3228 { 621, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #621 = ATOMIC_RMW_XCHG_I64_A64
3229 { 620, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #620 = ATOMIC_RMW_XCHG_I64_A32_S
3230 { 619, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #619 = ATOMIC_RMW_XCHG_I64_A32
3231 { 618, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #618 = ATOMIC_RMW_XCHG_I32_A64_S
3232 { 617, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #617 = ATOMIC_RMW_XCHG_I32_A64
3233 { 616, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #616 = ATOMIC_RMW_XCHG_I32_A32_S
3234 { 615, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #615 = ATOMIC_RMW_XCHG_I32_A32
3235 { 614, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #614 = ATOMIC_RMW_SUB_I64_A64_S
3236 { 613, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #613 = ATOMIC_RMW_SUB_I64_A64
3237 { 612, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #612 = ATOMIC_RMW_SUB_I64_A32_S
3238 { 611, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #611 = ATOMIC_RMW_SUB_I64_A32
3239 { 610, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #610 = ATOMIC_RMW_SUB_I32_A64_S
3240 { 609, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #609 = ATOMIC_RMW_SUB_I32_A64
3241 { 608, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #608 = ATOMIC_RMW_SUB_I32_A32_S
3242 { 607, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #607 = ATOMIC_RMW_SUB_I32_A32
3243 { 606, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #606 = ATOMIC_RMW_OR_I64_A64_S
3244 { 605, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #605 = ATOMIC_RMW_OR_I64_A64
3245 { 604, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #604 = ATOMIC_RMW_OR_I64_A32_S
3246 { 603, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #603 = ATOMIC_RMW_OR_I64_A32
3247 { 602, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #602 = ATOMIC_RMW_OR_I32_A64_S
3248 { 601, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #601 = ATOMIC_RMW_OR_I32_A64
3249 { 600, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #600 = ATOMIC_RMW_OR_I32_A32_S
3250 { 599, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #599 = ATOMIC_RMW_OR_I32_A32
3251 { 598, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #598 = ATOMIC_RMW_CMPXCHG_I64_A64_S
3252 { 597, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #597 = ATOMIC_RMW_CMPXCHG_I64_A64
3253 { 596, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #596 = ATOMIC_RMW_CMPXCHG_I64_A32_S
3254 { 595, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #595 = ATOMIC_RMW_CMPXCHG_I64_A32
3255 { 594, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #594 = ATOMIC_RMW_CMPXCHG_I32_A64_S
3256 { 593, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 240, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #593 = ATOMIC_RMW_CMPXCHG_I32_A64
3257 { 592, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #592 = ATOMIC_RMW_CMPXCHG_I32_A32_S
3258 { 591, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #591 = ATOMIC_RMW_CMPXCHG_I32_A32
3259 { 590, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #590 = ATOMIC_RMW_AND_I64_A64_S
3260 { 589, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #589 = ATOMIC_RMW_AND_I64_A64
3261 { 588, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #588 = ATOMIC_RMW_AND_I64_A32_S
3262 { 587, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #587 = ATOMIC_RMW_AND_I64_A32
3263 { 586, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #586 = ATOMIC_RMW_AND_I32_A64_S
3264 { 585, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #585 = ATOMIC_RMW_AND_I32_A64
3265 { 584, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #584 = ATOMIC_RMW_AND_I32_A32_S
3266 { 583, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #583 = ATOMIC_RMW_AND_I32_A32
3267 { 582, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #582 = ATOMIC_RMW_ADD_I64_A64_S
3268 { 581, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #581 = ATOMIC_RMW_ADD_I64_A64
3269 { 580, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #580 = ATOMIC_RMW_ADD_I64_A32_S
3270 { 579, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #579 = ATOMIC_RMW_ADD_I64_A32
3271 { 578, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #578 = ATOMIC_RMW_ADD_I32_A64_S
3272 { 577, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #577 = ATOMIC_RMW_ADD_I32_A64
3273 { 576, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #576 = ATOMIC_RMW_ADD_I32_A32_S
3274 { 575, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #575 = ATOMIC_RMW_ADD_I32_A32
3275 { 574, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #574 = ATOMIC_RMW8_U_XOR_I64_A64_S
3276 { 573, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #573 = ATOMIC_RMW8_U_XOR_I64_A64
3277 { 572, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #572 = ATOMIC_RMW8_U_XOR_I64_A32_S
3278 { 571, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #571 = ATOMIC_RMW8_U_XOR_I64_A32
3279 { 570, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #570 = ATOMIC_RMW8_U_XOR_I32_A64_S
3280 { 569, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #569 = ATOMIC_RMW8_U_XOR_I32_A64
3281 { 568, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #568 = ATOMIC_RMW8_U_XOR_I32_A32_S
3282 { 567, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #567 = ATOMIC_RMW8_U_XOR_I32_A32
3283 { 566, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #566 = ATOMIC_RMW8_U_XCHG_I64_A64_S
3284 { 565, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #565 = ATOMIC_RMW8_U_XCHG_I64_A64
3285 { 564, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #564 = ATOMIC_RMW8_U_XCHG_I64_A32_S
3286 { 563, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #563 = ATOMIC_RMW8_U_XCHG_I64_A32
3287 { 562, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #562 = ATOMIC_RMW8_U_XCHG_I32_A64_S
3288 { 561, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #561 = ATOMIC_RMW8_U_XCHG_I32_A64
3289 { 560, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #560 = ATOMIC_RMW8_U_XCHG_I32_A32_S
3290 { 559, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #559 = ATOMIC_RMW8_U_XCHG_I32_A32
3291 { 558, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #558 = ATOMIC_RMW8_U_SUB_I64_A64_S
3292 { 557, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #557 = ATOMIC_RMW8_U_SUB_I64_A64
3293 { 556, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #556 = ATOMIC_RMW8_U_SUB_I64_A32_S
3294 { 555, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #555 = ATOMIC_RMW8_U_SUB_I64_A32
3295 { 554, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #554 = ATOMIC_RMW8_U_SUB_I32_A64_S
3296 { 553, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #553 = ATOMIC_RMW8_U_SUB_I32_A64
3297 { 552, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #552 = ATOMIC_RMW8_U_SUB_I32_A32_S
3298 { 551, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #551 = ATOMIC_RMW8_U_SUB_I32_A32
3299 { 550, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #550 = ATOMIC_RMW8_U_OR_I64_A64_S
3300 { 549, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #549 = ATOMIC_RMW8_U_OR_I64_A64
3301 { 548, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #548 = ATOMIC_RMW8_U_OR_I64_A32_S
3302 { 547, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #547 = ATOMIC_RMW8_U_OR_I64_A32
3303 { 546, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #546 = ATOMIC_RMW8_U_OR_I32_A64_S
3304 { 545, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #545 = ATOMIC_RMW8_U_OR_I32_A64
3305 { 544, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #544 = ATOMIC_RMW8_U_OR_I32_A32_S
3306 { 543, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #543 = ATOMIC_RMW8_U_OR_I32_A32
3307 { 542, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #542 = ATOMIC_RMW8_U_CMPXCHG_I64_A64_S
3308 { 541, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #541 = ATOMIC_RMW8_U_CMPXCHG_I64_A64
3309 { 540, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #540 = ATOMIC_RMW8_U_CMPXCHG_I64_A32_S
3310 { 539, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #539 = ATOMIC_RMW8_U_CMPXCHG_I64_A32
3311 { 538, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #538 = ATOMIC_RMW8_U_CMPXCHG_I32_A64_S
3312 { 537, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 240, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #537 = ATOMIC_RMW8_U_CMPXCHG_I32_A64
3313 { 536, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #536 = ATOMIC_RMW8_U_CMPXCHG_I32_A32_S
3314 { 535, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #535 = ATOMIC_RMW8_U_CMPXCHG_I32_A32
3315 { 534, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #534 = ATOMIC_RMW8_U_AND_I64_A64_S
3316 { 533, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #533 = ATOMIC_RMW8_U_AND_I64_A64
3317 { 532, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #532 = ATOMIC_RMW8_U_AND_I64_A32_S
3318 { 531, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #531 = ATOMIC_RMW8_U_AND_I64_A32
3319 { 530, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #530 = ATOMIC_RMW8_U_AND_I32_A64_S
3320 { 529, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #529 = ATOMIC_RMW8_U_AND_I32_A64
3321 { 528, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #528 = ATOMIC_RMW8_U_AND_I32_A32_S
3322 { 527, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #527 = ATOMIC_RMW8_U_AND_I32_A32
3323 { 526, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #526 = ATOMIC_RMW8_U_ADD_I64_A64_S
3324 { 525, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #525 = ATOMIC_RMW8_U_ADD_I64_A64
3325 { 524, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #524 = ATOMIC_RMW8_U_ADD_I64_A32_S
3326 { 523, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #523 = ATOMIC_RMW8_U_ADD_I64_A32
3327 { 522, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #522 = ATOMIC_RMW8_U_ADD_I32_A64_S
3328 { 521, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #521 = ATOMIC_RMW8_U_ADD_I32_A64
3329 { 520, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #520 = ATOMIC_RMW8_U_ADD_I32_A32_S
3330 { 519, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #519 = ATOMIC_RMW8_U_ADD_I32_A32
3331 { 518, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #518 = ATOMIC_RMW32_U_XOR_I64_A64_S
3332 { 517, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #517 = ATOMIC_RMW32_U_XOR_I64_A64
3333 { 516, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #516 = ATOMIC_RMW32_U_XOR_I64_A32_S
3334 { 515, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #515 = ATOMIC_RMW32_U_XOR_I64_A32
3335 { 514, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #514 = ATOMIC_RMW32_U_XCHG_I64_A64_S
3336 { 513, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #513 = ATOMIC_RMW32_U_XCHG_I64_A64
3337 { 512, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #512 = ATOMIC_RMW32_U_XCHG_I64_A32_S
3338 { 511, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #511 = ATOMIC_RMW32_U_XCHG_I64_A32
3339 { 510, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #510 = ATOMIC_RMW32_U_SUB_I64_A64_S
3340 { 509, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #509 = ATOMIC_RMW32_U_SUB_I64_A64
3341 { 508, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #508 = ATOMIC_RMW32_U_SUB_I64_A32_S
3342 { 507, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #507 = ATOMIC_RMW32_U_SUB_I64_A32
3343 { 506, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #506 = ATOMIC_RMW32_U_OR_I64_A64_S
3344 { 505, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #505 = ATOMIC_RMW32_U_OR_I64_A64
3345 { 504, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #504 = ATOMIC_RMW32_U_OR_I64_A32_S
3346 { 503, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #503 = ATOMIC_RMW32_U_OR_I64_A32
3347 { 502, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #502 = ATOMIC_RMW32_U_CMPXCHG_I64_A64_S
3348 { 501, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #501 = ATOMIC_RMW32_U_CMPXCHG_I64_A64
3349 { 500, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #500 = ATOMIC_RMW32_U_CMPXCHG_I64_A32_S
3350 { 499, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #499 = ATOMIC_RMW32_U_CMPXCHG_I64_A32
3351 { 498, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #498 = ATOMIC_RMW32_U_AND_I64_A64_S
3352 { 497, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #497 = ATOMIC_RMW32_U_AND_I64_A64
3353 { 496, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #496 = ATOMIC_RMW32_U_AND_I64_A32_S
3354 { 495, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #495 = ATOMIC_RMW32_U_AND_I64_A32
3355 { 494, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #494 = ATOMIC_RMW32_U_ADD_I64_A64_S
3356 { 493, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #493 = ATOMIC_RMW32_U_ADD_I64_A64
3357 { 492, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #492 = ATOMIC_RMW32_U_ADD_I64_A32_S
3358 { 491, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #491 = ATOMIC_RMW32_U_ADD_I64_A32
3359 { 490, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #490 = ATOMIC_RMW16_U_XOR_I64_A64_S
3360 { 489, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #489 = ATOMIC_RMW16_U_XOR_I64_A64
3361 { 488, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #488 = ATOMIC_RMW16_U_XOR_I64_A32_S
3362 { 487, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #487 = ATOMIC_RMW16_U_XOR_I64_A32
3363 { 486, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #486 = ATOMIC_RMW16_U_XOR_I32_A64_S
3364 { 485, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #485 = ATOMIC_RMW16_U_XOR_I32_A64
3365 { 484, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #484 = ATOMIC_RMW16_U_XOR_I32_A32_S
3366 { 483, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #483 = ATOMIC_RMW16_U_XOR_I32_A32
3367 { 482, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #482 = ATOMIC_RMW16_U_XCHG_I64_A64_S
3368 { 481, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #481 = ATOMIC_RMW16_U_XCHG_I64_A64
3369 { 480, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #480 = ATOMIC_RMW16_U_XCHG_I64_A32_S
3370 { 479, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #479 = ATOMIC_RMW16_U_XCHG_I64_A32
3371 { 478, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #478 = ATOMIC_RMW16_U_XCHG_I32_A64_S
3372 { 477, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #477 = ATOMIC_RMW16_U_XCHG_I32_A64
3373 { 476, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #476 = ATOMIC_RMW16_U_XCHG_I32_A32_S
3374 { 475, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #475 = ATOMIC_RMW16_U_XCHG_I32_A32
3375 { 474, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #474 = ATOMIC_RMW16_U_SUB_I64_A64_S
3376 { 473, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #473 = ATOMIC_RMW16_U_SUB_I64_A64
3377 { 472, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #472 = ATOMIC_RMW16_U_SUB_I64_A32_S
3378 { 471, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #471 = ATOMIC_RMW16_U_SUB_I64_A32
3379 { 470, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #470 = ATOMIC_RMW16_U_SUB_I32_A64_S
3380 { 469, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #469 = ATOMIC_RMW16_U_SUB_I32_A64
3381 { 468, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #468 = ATOMIC_RMW16_U_SUB_I32_A32_S
3382 { 467, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #467 = ATOMIC_RMW16_U_SUB_I32_A32
3383 { 466, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #466 = ATOMIC_RMW16_U_OR_I64_A64_S
3384 { 465, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #465 = ATOMIC_RMW16_U_OR_I64_A64
3385 { 464, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #464 = ATOMIC_RMW16_U_OR_I64_A32_S
3386 { 463, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #463 = ATOMIC_RMW16_U_OR_I64_A32
3387 { 462, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #462 = ATOMIC_RMW16_U_OR_I32_A64_S
3388 { 461, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #461 = ATOMIC_RMW16_U_OR_I32_A64
3389 { 460, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #460 = ATOMIC_RMW16_U_OR_I32_A32_S
3390 { 459, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #459 = ATOMIC_RMW16_U_OR_I32_A32
3391 { 458, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #458 = ATOMIC_RMW16_U_CMPXCHG_I64_A64_S
3392 { 457, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 252, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #457 = ATOMIC_RMW16_U_CMPXCHG_I64_A64
3393 { 456, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #456 = ATOMIC_RMW16_U_CMPXCHG_I64_A32_S
3394 { 455, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 246, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #455 = ATOMIC_RMW16_U_CMPXCHG_I64_A32
3395 { 454, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #454 = ATOMIC_RMW16_U_CMPXCHG_I32_A64_S
3396 { 453, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 240, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = ATOMIC_RMW16_U_CMPXCHG_I32_A64
3397 { 452, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = ATOMIC_RMW16_U_CMPXCHG_I32_A32_S
3398 { 451, 6, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 234, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #451 = ATOMIC_RMW16_U_CMPXCHG_I32_A32
3399 { 450, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #450 = ATOMIC_RMW16_U_AND_I64_A64_S
3400 { 449, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = ATOMIC_RMW16_U_AND_I64_A64
3401 { 448, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = ATOMIC_RMW16_U_AND_I64_A32_S
3402 { 447, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #447 = ATOMIC_RMW16_U_AND_I64_A32
3403 { 446, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #446 = ATOMIC_RMW16_U_AND_I32_A64_S
3404 { 445, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = ATOMIC_RMW16_U_AND_I32_A64
3405 { 444, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = ATOMIC_RMW16_U_AND_I32_A32_S
3406 { 443, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #443 = ATOMIC_RMW16_U_AND_I32_A32
3407 { 442, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #442 = ATOMIC_RMW16_U_ADD_I64_A64_S
3408 { 441, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = ATOMIC_RMW16_U_ADD_I64_A64
3409 { 440, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = ATOMIC_RMW16_U_ADD_I64_A32_S
3410 { 439, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #439 = ATOMIC_RMW16_U_ADD_I64_A32
3411 { 438, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #438 = ATOMIC_RMW16_U_ADD_I32_A64_S
3412 { 437, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 219, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #437 = ATOMIC_RMW16_U_ADD_I32_A64
3413 { 436, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #436 = ATOMIC_RMW16_U_ADD_I32_A32_S
3414 { 435, 5, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 214, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #435 = ATOMIC_RMW16_U_ADD_I32_A32
3415 { 434, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #434 = ATOMIC_LOAD_I64_A64_S
3416 { 433, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #433 = ATOMIC_LOAD_I64_A64
3417 { 432, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #432 = ATOMIC_LOAD_I64_A32_S
3418 { 431, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #431 = ATOMIC_LOAD_I64_A32
3419 { 430, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #430 = ATOMIC_LOAD_I32_A64_S
3420 { 429, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #429 = ATOMIC_LOAD_I32_A64
3421 { 428, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #428 = ATOMIC_LOAD_I32_A32_S
3422 { 427, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #427 = ATOMIC_LOAD_I32_A32
3423 { 426, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #426 = ATOMIC_LOAD8_U_I64_A64_S
3424 { 425, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #425 = ATOMIC_LOAD8_U_I64_A64
3425 { 424, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #424 = ATOMIC_LOAD8_U_I64_A32_S
3426 { 423, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #423 = ATOMIC_LOAD8_U_I64_A32
3427 { 422, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #422 = ATOMIC_LOAD8_U_I32_A64_S
3428 { 421, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #421 = ATOMIC_LOAD8_U_I32_A64
3429 { 420, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #420 = ATOMIC_LOAD8_U_I32_A32_S
3430 { 419, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #419 = ATOMIC_LOAD8_U_I32_A32
3431 { 418, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #418 = ATOMIC_LOAD32_U_I64_A64_S
3432 { 417, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #417 = ATOMIC_LOAD32_U_I64_A64
3433 { 416, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #416 = ATOMIC_LOAD32_U_I64_A32_S
3434 { 415, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #415 = ATOMIC_LOAD32_U_I64_A32
3435 { 414, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #414 = ATOMIC_LOAD16_U_I64_A64_S
3436 { 413, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 210, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #413 = ATOMIC_LOAD16_U_I64_A64
3437 { 412, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #412 = ATOMIC_LOAD16_U_I64_A32_S
3438 { 411, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 206, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #411 = ATOMIC_LOAD16_U_I64_A32
3439 { 410, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #410 = ATOMIC_LOAD16_U_I32_A64_S
3440 { 409, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 200, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #409 = ATOMIC_LOAD16_U_I32_A64
3441 { 408, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #408 = ATOMIC_LOAD16_U_I32_A32_S
3442 { 407, 4, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #407 = ATOMIC_LOAD16_U_I32_A32
3443 { 406, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #406 = ATOMIC_FENCE_S
3444 { 405, 1, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #405 = ATOMIC_FENCE
3445 { 404, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #404 = ARGUMENT_v8i16_S
3446 { 403, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #403 = ARGUMENT_v8i16
3447 { 402, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #402 = ARGUMENT_v8f16_S
3448 { 401, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #401 = ARGUMENT_v8f16
3449 { 400, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #400 = ARGUMENT_v4i32_S
3450 { 399, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #399 = ARGUMENT_v4i32
3451 { 398, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #398 = ARGUMENT_v4f32_S
3452 { 397, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #397 = ARGUMENT_v4f32
3453 { 396, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #396 = ARGUMENT_v2i64_S
3454 { 395, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #395 = ARGUMENT_v2i64
3455 { 394, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #394 = ARGUMENT_v2f64_S
3456 { 393, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = ARGUMENT_v2f64
3457 { 392, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = ARGUMENT_v16i8_S
3458 { 391, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 192, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = ARGUMENT_v16i8
3459 { 390, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = ARGUMENT_i64_S
3460 { 389, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 190, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = ARGUMENT_i64
3461 { 388, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = ARGUMENT_i32_S
3462 { 387, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 188, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = ARGUMENT_i32
3463 { 386, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = ARGUMENT_funcref_S
3464 { 385, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 186, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = ARGUMENT_funcref
3465 { 384, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = ARGUMENT_f64_S
3466 { 383, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 184, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = ARGUMENT_f64
3467 { 382, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = ARGUMENT_f32_S
3468 { 381, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 182, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = ARGUMENT_f32
3469 { 380, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = ARGUMENT_externref_S
3470 { 379, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 180, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = ARGUMENT_externref
3471 { 378, 1, 0, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = ARGUMENT_exnref_S
3472 { 377, 2, 1, 0, 0, 1, 0, WebAssemblyImpOpBase + 3, 178, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = ARGUMENT_exnref
3473 { 376, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = ANYTRUE_S
3474 { 375, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = ANYTRUE
3475 { 374, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = AND_S
3476 { 373, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = AND_I64_S
3477 { 372, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = AND_I64
3478 { 371, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = AND_I32_S
3479 { 370, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = AND_I32
3480 { 369, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = ANDNOT_S
3481 { 368, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = ANDNOT
3482 { 367, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = AND
3483 { 366, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = ALLTRUE_I8x16_S
3484 { 365, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = ALLTRUE_I8x16
3485 { 364, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = ALLTRUE_I64x2_S
3486 { 363, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = ALLTRUE_I64x2
3487 { 362, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = ALLTRUE_I32x4_S
3488 { 361, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = ALLTRUE_I32x4
3489 { 360, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = ALLTRUE_I16x8_S
3490 { 359, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 176, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = ALLTRUE_I16x8
3491 { 358, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = ADJCALLSTACKUP_S
3492 { 357, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = ADJCALLSTACKUP
3493 { 356, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = ADJCALLSTACKDOWN_S
3494 { 355, 2, 0, 0, 0, 2, 2, WebAssemblyImpOpBase + 4, 21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = ADJCALLSTACKDOWN
3495 { 354, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = ADD_SAT_U_I8x16_S
3496 { 353, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = ADD_SAT_U_I8x16
3497 { 352, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = ADD_SAT_U_I16x8_S
3498 { 351, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = ADD_SAT_U_I16x8
3499 { 350, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = ADD_SAT_S_I8x16_S
3500 { 349, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = ADD_SAT_S_I8x16
3501 { 348, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = ADD_SAT_S_I16x8_S
3502 { 347, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = ADD_SAT_S_I16x8
3503 { 346, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = ADD_I8x16_S
3504 { 345, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = ADD_I8x16
3505 { 344, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = ADD_I64x2_S
3506 { 343, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = ADD_I64x2
3507 { 342, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = ADD_I64_S
3508 { 341, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 173, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = ADD_I64
3509 { 340, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = ADD_I32x4_S
3510 { 339, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = ADD_I32x4
3511 { 338, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = ADD_I32_S
3512 { 337, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 170, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = ADD_I32
3513 { 336, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = ADD_I16x8_S
3514 { 335, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = ADD_I16x8
3515 { 334, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = ADD_F64x2_S
3516 { 333, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = ADD_F64x2
3517 { 332, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = ADD_F64_S
3518 { 331, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 167, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = ADD_F64
3519 { 330, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = ADD_F32x4_S
3520 { 329, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = ADD_F32x4
3521 { 328, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = ADD_F32_S
3522 { 327, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 164, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = ADD_F32
3523 { 326, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = ADD_F16x8_S
3524 { 325, 3, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 161, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = ADD_F16x8
3525 { 324, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = ABS_I8x16_S
3526 { 323, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = ABS_I8x16
3527 { 322, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = ABS_I64x2_S
3528 { 321, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #321 = ABS_I64x2
3529 { 320, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #320 = ABS_I32x4_S
3530 { 319, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = ABS_I32x4
3531 { 318, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = ABS_I16x8_S
3532 { 317, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = ABS_I16x8
3533 { 316, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = ABS_F64x2_S
3534 { 315, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = ABS_F64x2
3535 { 314, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = ABS_F64_S
3536 { 313, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 159, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #313 = ABS_F64
3537 { 312, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #312 = ABS_F32x4_S
3538 { 311, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #311 = ABS_F32x4
3539 { 310, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = ABS_F32_S
3540 { 309, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 157, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = ABS_F32
3541 { 308, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = ABS_F16x8_S
3542 { 307, 2, 1, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 155, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #307 = ABS_F16x8
3543 { 306, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #306 = RET_CALL_RESULTS_S
3544 { 305, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #305 = RET_CALL_RESULTS
3545 { 304, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #304 = COMPILER_FENCE_S
3546 { 303, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #303 = COMPILER_FENCE
3547 { 302, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = CLEANUPRET_S
3548 { 301, 0, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = CLEANUPRET
3549 { 300, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 153, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = CATCHRET_S
3550 { 299, 2, 0, 0, 0, 0, 1, WebAssemblyImpOpBase + 3, 153, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #299 = CATCHRET
3551 { 298, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #298 = CALL_RESULTS_S
3552 { 297, 0, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x0ULL }, // Inst #297 = CALL_RESULTS
3553 { 296, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = CALL_PARAMS_S
3554 { 295, 1, 0, 0, 0, 2, 1, WebAssemblyImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = CALL_PARAMS
3555 { 294, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_UBFX
3556 { 293, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_SBFX
3557 { 292, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMIN
3558 { 291, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_UMAX
3559 { 290, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMIN
3560 { 289, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_VECREDUCE_SMAX
3561 { 288, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_VECREDUCE_XOR
3562 { 287, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_VECREDUCE_OR
3563 { 286, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_VECREDUCE_AND
3564 { 285, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_VECREDUCE_MUL
3565 { 284, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_VECREDUCE_ADD
3566 { 283, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMINIMUM
3567 { 282, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMAXIMUM
3568 { 281, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMIN
3569 { 280, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMAX
3570 { 279, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_VECREDUCE_FMUL
3571 { 278, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_VECREDUCE_FADD
3572 { 277, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FMUL
3573 { 276, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_VECREDUCE_SEQ_FADD
3574 { 275, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_UBSANTRAP
3575 { 274, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #274 = G_DEBUGTRAP
3576 { 273, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #273 = G_TRAP
3577 { 272, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #272 = G_BZERO
3578 { 271, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_MEMSET
3579 { 270, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_MEMMOVE
3580 { 269, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_MEMCPY_INLINE
3581 { 268, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #268 = G_MEMCPY
3582 { 267, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_WRITE_REGISTER
3583 { 266, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #266 = G_READ_REGISTER
3584 { 265, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_STRICT_FLDEXP
3585 { 264, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_STRICT_FSQRT
3586 { 263, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_STRICT_FMA
3587 { 262, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_STRICT_FREM
3588 { 261, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_STRICT_FDIV
3589 { 260, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_STRICT_FMUL
3590 { 259, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_STRICT_FSUB
3591 { 258, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_STRICT_FADD
3592 { 257, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_STACKRESTORE
3593 { 256, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_STACKSAVE
3594 { 255, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_DYN_STACKALLOC
3595 { 254, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_JUMP_TABLE
3596 { 253, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_BLOCK_ADDR
3597 { 252, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_ADDRSPACE_CAST
3598 { 251, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FNEARBYINT
3599 { 250, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_FRINT
3600 { 249, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_FFLOOR
3601 { 248, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_FSQRT
3602 { 247, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_FTANH
3603 { 246, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_FSINH
3604 { 245, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_FCOSH
3605 { 244, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_FATAN
3606 { 243, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_FASIN
3607 { 242, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_FACOS
3608 { 241, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_FTAN
3609 { 240, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_FSIN
3610 { 239, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_FCOS
3611 { 238, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_FCEIL
3612 { 237, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_BITREVERSE
3613 { 236, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_BSWAP
3614 { 235, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_CTPOP
3615 { 234, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_CTLZ_ZERO_UNDEF
3616 { 233, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_CTLZ
3617 { 232, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_CTTZ_ZERO_UNDEF
3618 { 231, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_CTTZ
3619 { 230, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_VECTOR_COMPRESS
3620 { 229, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_SPLAT_VECTOR
3621 { 228, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_SHUFFLE_VECTOR
3622 { 227, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_EXTRACT_VECTOR_ELT
3623 { 226, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_INSERT_VECTOR_ELT
3624 { 225, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_EXTRACT_SUBVECTOR
3625 { 224, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_INSERT_SUBVECTOR
3626 { 223, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_VSCALE
3627 { 222, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_BRJT
3628 { 221, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_BR
3629 { 220, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_LLROUND
3630 { 219, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_LROUND
3631 { 218, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_ABS
3632 { 217, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_UMAX
3633 { 216, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_UMIN
3634 { 215, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_SMAX
3635 { 214, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_SMIN
3636 { 213, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_PTRMASK
3637 { 212, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_PTR_ADD
3638 { 211, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_RESET_FPMODE
3639 { 210, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_SET_FPMODE
3640 { 209, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_GET_FPMODE
3641 { 208, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_RESET_FPENV
3642 { 207, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_SET_FPENV
3643 { 206, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_GET_FPENV
3644 { 205, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FMAXIMUM
3645 { 204, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_FMINIMUM
3646 { 203, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_FMAXNUM_IEEE
3647 { 202, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_FMINNUM_IEEE
3648 { 201, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FMAXNUM
3649 { 200, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FMINNUM
3650 { 199, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_FCANONICALIZE
3651 { 198, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_IS_FPCLASS
3652 { 197, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FCOPYSIGN
3653 { 196, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_FABS
3654 { 195, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_UITOFP
3655 { 194, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_SITOFP
3656 { 193, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FPTOUI
3657 { 192, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FPTOSI
3658 { 191, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FPTRUNC
3659 { 190, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FPEXT
3660 { 189, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FNEG
3661 { 188, 3, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FFREXP
3662 { 187, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FLDEXP
3663 { 186, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FLOG10
3664 { 185, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FLOG2
3665 { 184, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FLOG
3666 { 183, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FEXP10
3667 { 182, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FEXP2
3668 { 181, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FEXP
3669 { 180, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FPOWI
3670 { 179, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #179 = G_FPOW
3671 { 178, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #178 = G_FREM
3672 { 177, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #177 = G_FDIV
3673 { 176, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #176 = G_FMAD
3674 { 175, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #175 = G_FMA
3675 { 174, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #174 = G_FMUL
3676 { 173, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #173 = G_FSUB
3677 { 172, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #172 = G_FADD
3678 { 171, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #171 = G_UDIVFIXSAT
3679 { 170, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #170 = G_SDIVFIXSAT
3680 { 169, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #169 = G_UDIVFIX
3681 { 168, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #168 = G_SDIVFIX
3682 { 167, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #167 = G_UMULFIXSAT
3683 { 166, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #166 = G_SMULFIXSAT
3684 { 165, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #165 = G_UMULFIX
3685 { 164, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #164 = G_SMULFIX
3686 { 163, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #163 = G_SSHLSAT
3687 { 162, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #162 = G_USHLSAT
3688 { 161, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #161 = G_SSUBSAT
3689 { 160, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #160 = G_USUBSAT
3690 { 159, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #159 = G_SADDSAT
3691 { 158, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #158 = G_UADDSAT
3692 { 157, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #157 = G_SMULH
3693 { 156, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #156 = G_UMULH
3694 { 155, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #155 = G_SMULO
3695 { 154, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #154 = G_UMULO
3696 { 153, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #153 = G_SSUBE
3697 { 152, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #152 = G_SSUBO
3698 { 151, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #151 = G_SADDE
3699 { 150, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #150 = G_SADDO
3700 { 149, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #149 = G_USUBE
3701 { 148, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #148 = G_USUBO
3702 { 147, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #147 = G_UADDE
3703 { 146, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #146 = G_UADDO
3704 { 145, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #145 = G_SELECT
3705 { 144, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #144 = G_UCMP
3706 { 143, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #143 = G_SCMP
3707 { 142, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #142 = G_FCMP
3708 { 141, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #141 = G_ICMP
3709 { 140, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #140 = G_ROTL
3710 { 139, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #139 = G_ROTR
3711 { 138, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #138 = G_FSHR
3712 { 137, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #137 = G_FSHL
3713 { 136, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #136 = G_ASHR
3714 { 135, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #135 = G_LSHR
3715 { 134, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #134 = G_SHL
3716 { 133, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #133 = G_ZEXT
3717 { 132, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #132 = G_SEXT_INREG
3718 { 131, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #131 = G_SEXT
3719 { 130, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #130 = G_VAARG
3720 { 129, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #129 = G_VASTART
3721 { 128, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #128 = G_FCONSTANT
3722 { 127, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #127 = G_CONSTANT
3723 { 126, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #126 = G_TRUNC
3724 { 125, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #125 = G_ANYEXT
3725 { 124, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
3726 { 123, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #123 = G_INTRINSIC_CONVERGENT
3727 { 122, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #122 = G_INTRINSIC_W_SIDE_EFFECTS
3728 { 121, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #121 = G_INTRINSIC
3729 { 120, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #120 = G_INVOKE_REGION_START
3730 { 119, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #119 = G_BRINDIRECT
3731 { 118, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #118 = G_BRCOND
3732 { 117, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #117 = G_PREFETCH
3733 { 116, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #116 = G_FENCE
3734 { 115, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UDEC_WRAP
3735 { 114, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #114 = G_ATOMICRMW_UINC_WRAP
3736 { 113, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMIN
3737 { 112, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FMAX
3738 { 111, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FSUB
3739 { 110, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #110 = G_ATOMICRMW_FADD
3740 { 109, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMIN
3741 { 108, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #108 = G_ATOMICRMW_UMAX
3742 { 107, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MIN
3743 { 106, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #106 = G_ATOMICRMW_MAX
3744 { 105, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #105 = G_ATOMICRMW_XOR
3745 { 104, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #104 = G_ATOMICRMW_OR
3746 { 103, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #103 = G_ATOMICRMW_NAND
3747 { 102, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #102 = G_ATOMICRMW_AND
3748 { 101, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #101 = G_ATOMICRMW_SUB
3749 { 100, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #100 = G_ATOMICRMW_ADD
3750 { 99, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #99 = G_ATOMICRMW_XCHG
3751 { 98, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG
3752 { 97, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #97 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
3753 { 96, 5, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #96 = G_INDEXED_STORE
3754 { 95, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #95 = G_STORE
3755 { 94, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #94 = G_INDEXED_ZEXTLOAD
3756 { 93, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #93 = G_INDEXED_SEXTLOAD
3757 { 92, 5, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #92 = G_INDEXED_LOAD
3758 { 91, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #91 = G_ZEXTLOAD
3759 { 90, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #90 = G_SEXTLOAD
3760 { 89, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #89 = G_LOAD
3761 { 88, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #88 = G_READSTEADYCOUNTER
3762 { 87, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #87 = G_READCYCLECOUNTER
3763 { 86, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #86 = G_INTRINSIC_ROUNDEVEN
3764 { 85, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #85 = G_INTRINSIC_LLRINT
3765 { 84, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #84 = G_INTRINSIC_LRINT
3766 { 83, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #83 = G_INTRINSIC_ROUND
3767 { 82, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #82 = G_INTRINSIC_TRUNC
3768 { 81, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #81 = G_INTRINSIC_FPTRUNC_ROUND
3769 { 80, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #80 = G_CONSTANT_FOLD_BARRIER
3770 { 79, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #79 = G_FREEZE
3771 { 78, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #78 = G_BITCAST
3772 { 77, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #77 = G_INTTOPTR
3773 { 76, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #76 = G_PTRTOINT
3774 { 75, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #75 = G_CONCAT_VECTORS
3775 { 74, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR_TRUNC
3776 { 73, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #73 = G_BUILD_VECTOR
3777 { 72, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #72 = G_MERGE_VALUES
3778 { 71, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #71 = G_INSERT
3779 { 70, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #70 = G_UNMERGE_VALUES
3780 { 69, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #69 = G_EXTRACT
3781 { 68, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #68 = G_CONSTANT_POOL
3782 { 67, 5, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #67 = G_PTRAUTH_GLOBAL_VALUE
3783 { 66, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #66 = G_GLOBAL_VALUE
3784 { 65, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #65 = G_FRAME_INDEX
3785 { 64, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #64 = G_PHI
3786 { 63, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #63 = G_IMPLICIT_DEF
3787 { 62, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #62 = G_XOR
3788 { 61, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #61 = G_OR
3789 { 60, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #60 = G_AND
3790 { 59, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #59 = G_UDIVREM
3791 { 58, 4, 2, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #58 = G_SDIVREM
3792 { 57, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #57 = G_UREM
3793 { 56, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #56 = G_SREM
3794 { 55, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #55 = G_UDIV
3795 { 54, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #54 = G_SDIV
3796 { 53, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #53 = G_MUL
3797 { 52, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #52 = G_SUB
3798 { 51, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #51 = G_ADD
3799 { 50, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #50 = G_ASSERT_ALIGN
3800 { 49, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #49 = G_ASSERT_ZEXT
3801 { 48, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #48 = G_ASSERT_SEXT
3802 { 47, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_GLUE
3803 { 46, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_LOOP
3804 { 45, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ANCHOR
3805 { 44, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #44 = CONVERGENCECTRL_ENTRY
3806 { 43, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #43 = JUMP_TABLE_DEBUG_INFO
3807 { 42, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #42 = MEMBARRIER
3808 { 41, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL
3809 { 40, 3, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
3810 { 39, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL
3811 { 38, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL
3812 { 37, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT
3813 { 36, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #36 = PATCHABLE_RET
3814 { 35, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER
3815 { 34, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #34 = PATCHABLE_OP
3816 { 33, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #33 = FAULTING_OP
3817 { 32, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE
3818 { 31, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #31 = STATEPOINT
3819 { 30, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG
3820 { 29, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP
3821 { 28, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD
3822 { 27, 6, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #27 = PATCHPOINT
3823 { 26, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #26 = FENTRY_CALL
3824 { 25, 2, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #25 = STACKMAP
3825 { 24, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #24 = ARITH_FENCE
3826 { 23, 4, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #23 = PSEUDO_PROBE
3827 { 22, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #22 = LIFETIME_END
3828 { 21, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #21 = LIFETIME_START
3829 { 20, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #20 = BUNDLE
3830 { 19, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #19 = COPY
3831 { 18, 2, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #18 = REG_SEQUENCE
3832 { 17, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #17 = DBG_LABEL
3833 { 16, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #16 = DBG_PHI
3834 { 15, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #15 = DBG_INSTR_REF
3835 { 14, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST
3836 { 13, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #13 = DBG_VALUE
3837 { 12, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS
3838 { 11, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #11 = SUBREG_TO_REG
3839 { 10, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
3840 { 9, 4, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #9 = INSERT_SUBREG
3841 { 8, 3, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
3842 { 7, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #7 = KILL
3843 { 6, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
3844 { 5, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #5 = GC_LABEL
3845 { 4, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #4 = EH_LABEL
3846 { 3, 1, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
3847 { 2, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #2 = INLINEASM_BR
3848 { 1, 0, 0, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1 = INLINEASM
3849 { 0, 1, 1, 0, 0, 0, 0, WebAssemblyImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #0 = PHI
3850 }, {
3851 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3852 /* 1 */
3853 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3854 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3855 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3856 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3857 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3858 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3859 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
3860 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3861 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3862 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
3863 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3864 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3865 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3866 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3867 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3868 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3869 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3870 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3871 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3872 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3873 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3874 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3875 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3876 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3877 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3878 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3879 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3880 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3881 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3882 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3883 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3884 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3885 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3886 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3887 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3888 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3889 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3890 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3891 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3892 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
3893 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
3894 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
3895 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3896 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
3897 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
3898 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
3899 /* 152 */ { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 },
3900 /* 153 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 },
3901 /* 155 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3902 /* 157 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3903 /* 159 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3904 /* 161 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3905 /* 164 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3906 /* 167 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3907 /* 170 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3908 /* 173 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3909 /* 176 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3910 /* 178 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3911 /* 180 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3912 /* 182 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3913 /* 184 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3914 /* 186 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3915 /* 188 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3916 /* 190 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3917 /* 192 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
3918 /* 194 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3919 /* 198 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 },
3920 /* 200 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3921 /* 204 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 },
3922 /* 206 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3923 /* 210 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3924 /* 214 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3925 /* 219 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3926 /* 224 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3927 /* 229 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3928 /* 234 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3929 /* 240 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3930 /* 246 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3931 /* 252 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3932 /* 258 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3933 /* 262 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3934 /* 266 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3935 /* 270 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3936 /* 274 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3937 /* 278 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 },
3938 /* 279 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 },
3939 /* 280 */ { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3940 /* 282 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3941 /* 283 */ { -1, 0, WebAssembly::OPERAND_BRLIST, 0 },
3942 /* 284 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3943 /* 285 */ { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
3944 /* 287 */ { -1, 0, WebAssembly::OPERAND_TAG, 0 },
3945 /* 288 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3946 /* 290 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3947 /* 292 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
3948 /* 294 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
3949 /* 295 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
3950 /* 297 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
3951 /* 298 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
3952 /* 300 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
3953 /* 301 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I64IMM, 0 },
3954 /* 303 */ { -1, 0, WebAssembly::OPERAND_I64IMM, 0 },
3955 /* 304 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
3956 /* 309 */ { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 },
3957 /* 313 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
3958 /* 316 */ { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 },
3959 /* 318 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 },
3960 /* 327 */ { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 },
3961 /* 335 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 },
3962 /* 340 */ { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 },
3963 /* 344 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 },
3964 /* 347 */ { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 },
3965 /* 349 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3966 /* 366 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3967 /* 382 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3968 /* 384 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3969 /* 386 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3970 /* 388 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3971 /* 389 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3972 /* 390 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3973 /* 391 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3974 /* 392 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3975 /* 393 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3976 /* 394 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3977 /* 396 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3978 /* 399 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3979 /* 402 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3980 /* 405 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3981 /* 408 */ { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3982 /* 409 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3983 /* 412 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3984 /* 415 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
3985 /* 418 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3986 /* 420 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3987 /* 422 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3988 /* 424 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3989 /* 426 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3990 /* 428 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3991 /* 430 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3992 /* 432 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3993 /* 434 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3994 /* 436 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
3995 /* 438 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
3996 /* 440 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
3997 /* 441 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
3998 /* 443 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
3999 /* 445 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4000 /* 447 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4001 /* 449 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4002 /* 451 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4003 /* 453 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 },
4004 /* 455 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4005 /* 457 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4006 /* 459 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4007 /* 461 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4008 /* 463 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4009 /* 465 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4010 /* 467 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4011 /* 469 */ { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4012 /* 471 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4013 /* 473 */ { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4014 /* 475 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4015 /* 479 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4016 /* 483 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4017 /* 487 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4018 /* 491 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4019 /* 495 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4020 /* 499 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4021 /* 505 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4022 /* 508 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4023 /* 514 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4024 /* 517 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4025 /* 519 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4026 /* 520 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4027 /* 522 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4028 /* 524 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4029 /* 526 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4030 /* 528 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4031 /* 530 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4032 /* 532 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 },
4033 /* 534 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4034 /* 536 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4035 /* 538 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4036 /* 540 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4037 /* 542 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4038 /* 544 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4039 /* 546 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4040 /* 548 */ { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4041 /* 550 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4042 /* 553 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4043 /* 556 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4044 /* 559 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4045 /* 562 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4046 /* 565 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4047 /* 568 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4048 /* 571 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4049 /* 574 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4050 /* 580 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4051 /* 586 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4052 /* 592 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4053 /* 598 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4054 /* 600 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4055 /* 602 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4056 /* 604 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4057 /* 608 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4058 /* 612 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4059 /* 616 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4060 /* 620 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4061 /* 624 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4062 /* 628 */ { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4063 /* 632 */ { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4064 /* 636 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4065 /* 640 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4066 /* 644 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4067 /* 648 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4068 /* 652 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4069 /* 655 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 },
4070 /* 674 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4071 /* 676 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4072 /* 678 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4073 /* 680 */ { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4074 /* 682 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4075 /* 686 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4076 /* 690 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4077 /* 694 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4078 /* 698 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4079 /* 703 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4080 /* 708 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4081 /* 712 */ { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET64, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4082 /* 716 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4083 /* 721 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4084 /* 723 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4085 /* 727 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4086 /* 728 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4087 /* 732 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4088 /* 736 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4089 /* 739 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4090 /* 742 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4091 /* 745 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4092 /* 749 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4093 /* 753 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4094 /* 757 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4095 /* 760 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4096 /* 763 */ { -1, 0, WebAssembly::OPERAND_TABLE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4097 /* 766 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TABLE, 0 },
4098 /* 768 */ { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4099 /* 771 */ { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXTERNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4100 /* 774 */ { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::FUNCREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4101 /* 777 */ { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4102 /* 780 */ { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4103 /* 783 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4104 /* 788 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 },
4105 /* 790 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4106 /* 794 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4107 /* 799 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4108 /* 803 */ { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4109 }, {
4110 /* 0 */
4111 /* 0 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::ARGUMENTS,
4112 /* 3 */ WebAssembly::ARGUMENTS,
4113 /* 4 */ WebAssembly::SP32, WebAssembly::SP64, WebAssembly::SP32, WebAssembly::SP64,
4114 /* 8 */ WebAssembly::VALUE_STACK, WebAssembly::VALUE_STACK,
4115 }
4116};
4117
4118
4119#ifdef __GNUC__
4120#pragma GCC diagnostic push
4121#pragma GCC diagnostic ignored "-Woverlength-strings"
4122#endif
4123extern const char WebAssemblyInstrNameData[] = {
4124 /* 0 */ "G_FLOG10\0"
4125 /* 9 */ "G_FEXP10\0"
4126 /* 18 */ "LOAD_F16_F32_A32\0"
4127 /* 35 */ "STORE_F16_F32_A32\0"
4128 /* 53 */ "LOAD_F32_A32\0"
4129 /* 66 */ "STORE_F32_A32\0"
4130 /* 80 */ "ATOMIC_STORE16_I32_A32\0"
4131 /* 103 */ "ATOMIC_STORE8_I32_A32\0"
4132 /* 125 */ "ATOMIC_RMW16_U_SUB_I32_A32\0"
4133 /* 152 */ "ATOMIC_RMW8_U_SUB_I32_A32\0"
4134 /* 178 */ "ATOMIC_RMW_SUB_I32_A32\0"
4135 /* 201 */ "ATOMIC_LOAD_I32_A32\0"
4136 /* 221 */ "ATOMIC_RMW16_U_ADD_I32_A32\0"
4137 /* 248 */ "ATOMIC_RMW8_U_ADD_I32_A32\0"
4138 /* 274 */ "ATOMIC_RMW_ADD_I32_A32\0"
4139 /* 297 */ "ATOMIC_RMW16_U_AND_I32_A32\0"
4140 /* 324 */ "ATOMIC_RMW8_U_AND_I32_A32\0"
4141 /* 350 */ "ATOMIC_RMW_AND_I32_A32\0"
4142 /* 373 */ "ATOMIC_STORE_I32_A32\0"
4143 /* 394 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32\0"
4144 /* 425 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32\0"
4145 /* 455 */ "ATOMIC_RMW_CMPXCHG_I32_A32\0"
4146 /* 482 */ "ATOMIC_RMW16_U_XCHG_I32_A32\0"
4147 /* 510 */ "ATOMIC_RMW8_U_XCHG_I32_A32\0"
4148 /* 537 */ "ATOMIC_RMW_XCHG_I32_A32\0"
4149 /* 561 */ "ATOMIC_RMW16_U_XOR_I32_A32\0"
4150 /* 588 */ "ATOMIC_RMW8_U_XOR_I32_A32\0"
4151 /* 614 */ "ATOMIC_RMW_XOR_I32_A32\0"
4152 /* 637 */ "ATOMIC_RMW16_U_OR_I32_A32\0"
4153 /* 663 */ "ATOMIC_RMW8_U_OR_I32_A32\0"
4154 /* 688 */ "ATOMIC_RMW_OR_I32_A32\0"
4155 /* 710 */ "LOAD16_S_I32_A32\0"
4156 /* 727 */ "LOAD8_S_I32_A32\0"
4157 /* 743 */ "ATOMIC_LOAD16_U_I32_A32\0"
4158 /* 767 */ "ATOMIC_LOAD8_U_I32_A32\0"
4159 /* 790 */ "MEMORY_ATOMIC_WAIT32_A32\0"
4160 /* 815 */ "LOAD_LANE_I64x2_A32\0"
4161 /* 835 */ "STORE_LANE_I64x2_A32\0"
4162 /* 856 */ "LOAD_ZERO_I64x2_A32\0"
4163 /* 876 */ "LOAD_EXTEND_S_I64x2_A32\0"
4164 /* 900 */ "LOAD_EXTEND_U_I64x2_A32\0"
4165 /* 924 */ "LOAD_F64_A32\0"
4166 /* 937 */ "STORE_F64_A32\0"
4167 /* 951 */ "ATOMIC_STORE32_I64_A32\0"
4168 /* 974 */ "ATOMIC_STORE16_I64_A32\0"
4169 /* 997 */ "ATOMIC_STORE8_I64_A32\0"
4170 /* 1019 */ "ATOMIC_RMW32_U_SUB_I64_A32\0"
4171 /* 1046 */ "ATOMIC_RMW16_U_SUB_I64_A32\0"
4172 /* 1073 */ "ATOMIC_RMW8_U_SUB_I64_A32\0"
4173 /* 1099 */ "ATOMIC_RMW_SUB_I64_A32\0"
4174 /* 1122 */ "ATOMIC_LOAD_I64_A32\0"
4175 /* 1142 */ "ATOMIC_RMW32_U_ADD_I64_A32\0"
4176 /* 1169 */ "ATOMIC_RMW16_U_ADD_I64_A32\0"
4177 /* 1196 */ "ATOMIC_RMW8_U_ADD_I64_A32\0"
4178 /* 1222 */ "ATOMIC_RMW_ADD_I64_A32\0"
4179 /* 1245 */ "ATOMIC_RMW32_U_AND_I64_A32\0"
4180 /* 1272 */ "ATOMIC_RMW16_U_AND_I64_A32\0"
4181 /* 1299 */ "ATOMIC_RMW8_U_AND_I64_A32\0"
4182 /* 1325 */ "ATOMIC_RMW_AND_I64_A32\0"
4183 /* 1348 */ "ATOMIC_STORE_I64_A32\0"
4184 /* 1369 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32\0"
4185 /* 1400 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32\0"
4186 /* 1431 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32\0"
4187 /* 1461 */ "ATOMIC_RMW_CMPXCHG_I64_A32\0"
4188 /* 1488 */ "ATOMIC_RMW32_U_XCHG_I64_A32\0"
4189 /* 1516 */ "ATOMIC_RMW16_U_XCHG_I64_A32\0"
4190 /* 1544 */ "ATOMIC_RMW8_U_XCHG_I64_A32\0"
4191 /* 1571 */ "ATOMIC_RMW_XCHG_I64_A32\0"
4192 /* 1595 */ "ATOMIC_RMW32_U_XOR_I64_A32\0"
4193 /* 1622 */ "ATOMIC_RMW16_U_XOR_I64_A32\0"
4194 /* 1649 */ "ATOMIC_RMW8_U_XOR_I64_A32\0"
4195 /* 1675 */ "ATOMIC_RMW_XOR_I64_A32\0"
4196 /* 1698 */ "ATOMIC_RMW32_U_OR_I64_A32\0"
4197 /* 1724 */ "ATOMIC_RMW16_U_OR_I64_A32\0"
4198 /* 1750 */ "ATOMIC_RMW8_U_OR_I64_A32\0"
4199 /* 1775 */ "ATOMIC_RMW_OR_I64_A32\0"
4200 /* 1797 */ "LOAD32_S_I64_A32\0"
4201 /* 1814 */ "LOAD16_S_I64_A32\0"
4202 /* 1831 */ "LOAD8_S_I64_A32\0"
4203 /* 1847 */ "ATOMIC_LOAD32_U_I64_A32\0"
4204 /* 1871 */ "ATOMIC_LOAD16_U_I64_A32\0"
4205 /* 1895 */ "ATOMIC_LOAD8_U_I64_A32\0"
4206 /* 1918 */ "MEMORY_ATOMIC_WAIT64_A32\0"
4207 /* 1943 */ "LOAD_LANE_I32x4_A32\0"
4208 /* 1963 */ "STORE_LANE_I32x4_A32\0"
4209 /* 1984 */ "LOAD_ZERO_I32x4_A32\0"
4210 /* 2004 */ "LOAD_EXTEND_S_I32x4_A32\0"
4211 /* 2028 */ "LOAD_EXTEND_U_I32x4_A32\0"
4212 /* 2052 */ "LOAD_LANE_I8x16_A32\0"
4213 /* 2072 */ "STORE_LANE_I8x16_A32\0"
4214 /* 2093 */ "LOAD_V128_A32\0"
4215 /* 2107 */ "STORE_V128_A32\0"
4216 /* 2122 */ "LOAD_LANE_I16x8_A32\0"
4217 /* 2142 */ "STORE_LANE_I16x8_A32\0"
4218 /* 2163 */ "LOAD_EXTEND_S_I16x8_A32\0"
4219 /* 2187 */ "LOAD_EXTEND_U_I16x8_A32\0"
4220 /* 2211 */ "anonymous_8187MEMORY_SIZE_A32\0"
4221 /* 2241 */ "anonymous_8878MEMORY_FILL_A32\0"
4222 /* 2271 */ "LOAD32_SPLAT_A32\0"
4223 /* 2288 */ "LOAD64_SPLAT_A32\0"
4224 /* 2305 */ "LOAD16_SPLAT_A32\0"
4225 /* 2322 */ "LOAD8_SPLAT_A32\0"
4226 /* 2338 */ "anonymous_8878MEMORY_INIT_A32\0"
4227 /* 2368 */ "anonymous_8187MEMORY_GROW_A32\0"
4228 /* 2398 */ "MEMORY_ATOMIC_NOTIFY_A32\0"
4229 /* 2423 */ "anonymous_8878MEMORY_COPY_A32\0"
4230 /* 2453 */ "FP_TO_SINT_I32_F32\0"
4231 /* 2472 */ "FP_TO_UINT_I32_F32\0"
4232 /* 2491 */ "FP_TO_SINT_I64_F32\0"
4233 /* 2510 */ "FP_TO_UINT_I64_F32\0"
4234 /* 2529 */ "SUB_F32\0"
4235 /* 2537 */ "TRUNC_F32\0"
4236 /* 2547 */ "ADD_F32\0"
4237 /* 2555 */ "LOCAL_TEE_F32\0"
4238 /* 2569 */ "GE_F32\0"
4239 /* 2576 */ "LE_F32\0"
4240 /* 2583 */ "NE_F32\0"
4241 /* 2590 */ "F64_PROMOTE_F32\0"
4242 /* 2606 */ "NEG_F32\0"
4243 /* 2614 */ "CEIL_F32\0"
4244 /* 2623 */ "MUL_F32\0"
4245 /* 2631 */ "COPYSIGN_F32\0"
4246 /* 2644 */ "MIN_F32\0"
4247 /* 2652 */ "DROP_F32\0"
4248 /* 2661 */ "EQ_F32\0"
4249 /* 2668 */ "FLOOR_F32\0"
4250 /* 2678 */ "ABS_F32\0"
4251 /* 2686 */ "I32_TRUNC_S_F32\0"
4252 /* 2702 */ "I64_TRUNC_S_F32\0"
4253 /* 2718 */ "I32_TRUNC_S_SAT_F32\0"
4254 /* 2738 */ "I64_TRUNC_S_SAT_F32\0"
4255 /* 2758 */ "I32_TRUNC_U_SAT_F32\0"
4256 /* 2778 */ "I64_TRUNC_U_SAT_F32\0"
4257 /* 2798 */ "SELECT_F32\0"
4258 /* 2809 */ "GLOBAL_GET_F32\0"
4259 /* 2824 */ "LOCAL_GET_F32\0"
4260 /* 2838 */ "I32_REINTERPRET_F32\0"
4261 /* 2858 */ "GLOBAL_SET_F32\0"
4262 /* 2873 */ "LOCAL_SET_F32\0"
4263 /* 2887 */ "GT_F32\0"
4264 /* 2894 */ "LT_F32\0"
4265 /* 2901 */ "SQRT_F32\0"
4266 /* 2910 */ "NEAREST_F32\0"
4267 /* 2922 */ "CONST_F32\0"
4268 /* 2932 */ "I32_TRUNC_U_F32\0"
4269 /* 2948 */ "I64_TRUNC_U_F32\0"
4270 /* 2964 */ "DIV_F32\0"
4271 /* 2972 */ "MAX_F32\0"
4272 /* 2980 */ "COPY_F32\0"
4273 /* 2989 */ "SUB_I32\0"
4274 /* 2997 */ "ADD_I32\0"
4275 /* 3005 */ "AND_I32\0"
4276 /* 3013 */ "LOCAL_TEE_I32\0"
4277 /* 3027 */ "BR_TABLE_I32\0"
4278 /* 3040 */ "NE_I32\0"
4279 /* 3047 */ "SHL_I32\0"
4280 /* 3055 */ "ROTL_I32\0"
4281 /* 3064 */ "MUL_I32\0"
4282 /* 3072 */ "DROP_I32\0"
4283 /* 3081 */ "EQ_I32\0"
4284 /* 3088 */ "XOR_I32\0"
4285 /* 3096 */ "ROTR_I32\0"
4286 /* 3105 */ "I32_EXTEND16_S_I32\0"
4287 /* 3124 */ "I32_EXTEND8_S_I32\0"
4288 /* 3142 */ "I64_EXTEND_S_I32\0"
4289 /* 3159 */ "GE_S_I32\0"
4290 /* 3168 */ "LE_S_I32\0"
4291 /* 3177 */ "REM_S_I32\0"
4292 /* 3187 */ "SHR_S_I32\0"
4293 /* 3197 */ "GT_S_I32\0"
4294 /* 3206 */ "LT_S_I32\0"
4295 /* 3215 */ "F32_CONVERT_S_I32\0"
4296 /* 3233 */ "F64_CONVERT_S_I32\0"
4297 /* 3251 */ "DIV_S_I32\0"
4298 /* 3261 */ "SELECT_I32\0"
4299 /* 3272 */ "GLOBAL_GET_I32\0"
4300 /* 3287 */ "LOCAL_GET_I32\0"
4301 /* 3301 */ "F32_REINTERPRET_I32\0"
4302 /* 3321 */ "GLOBAL_SET_I32\0"
4303 /* 3336 */ "LOCAL_SET_I32\0"
4304 /* 3350 */ "POPCNT_I32\0"
4305 /* 3361 */ "CONST_I32\0"
4306 /* 3371 */ "I64_EXTEND_U_I32\0"
4307 /* 3388 */ "GE_U_I32\0"
4308 /* 3397 */ "LE_U_I32\0"
4309 /* 3406 */ "REM_U_I32\0"
4310 /* 3416 */ "SHR_U_I32\0"
4311 /* 3426 */ "GT_U_I32\0"
4312 /* 3435 */ "LT_U_I32\0"
4313 /* 3444 */ "F32_CONVERT_U_I32\0"
4314 /* 3462 */ "F64_CONVERT_U_I32\0"
4315 /* 3480 */ "DIV_U_I32\0"
4316 /* 3490 */ "COPY_I32\0"
4317 /* 3499 */ "CLZ_I32\0"
4318 /* 3507 */ "EQZ_I32\0"
4319 /* 3515 */ "CTZ_I32\0"
4320 /* 3523 */ "ARGUMENT_v4f32\0"
4321 /* 3538 */ "ARGUMENT_f32\0"
4322 /* 3551 */ "ARGUMENT_v4i32\0"
4323 /* 3566 */ "ARGUMENT_i32\0"
4324 /* 3579 */ "G_FLOG2\0"
4325 /* 3587 */ "G_FEXP2\0"
4326 /* 3595 */ "CONST_V128_F64x2\0"
4327 /* 3612 */ "SUB_F64x2\0"
4328 /* 3622 */ "TRUNC_F64x2\0"
4329 /* 3634 */ "NMADD_F64x2\0"
4330 /* 3646 */ "GE_F64x2\0"
4331 /* 3655 */ "LE_F64x2\0"
4332 /* 3664 */ "REPLACE_LANE_F64x2\0"
4333 /* 3683 */ "EXTRACT_LANE_F64x2\0"
4334 /* 3702 */ "NEG_F64x2\0"
4335 /* 3712 */ "CEIL_F64x2\0"
4336 /* 3723 */ "MUL_F64x2\0"
4337 /* 3733 */ "SIMD_RELAXED_FMIN_F64x2\0"
4338 /* 3757 */ "PMIN_F64x2\0"
4339 /* 3768 */ "EQ_F64x2\0"
4340 /* 3777 */ "FLOOR_F64x2\0"
4341 /* 3789 */ "ABS_F64x2\0"
4342 /* 3799 */ "SPLAT_F64x2\0"
4343 /* 3811 */ "GT_F64x2\0"
4344 /* 3820 */ "LT_F64x2\0"
4345 /* 3829 */ "SQRT_F64x2\0"
4346 /* 3840 */ "NEAREST_F64x2\0"
4347 /* 3854 */ "DIV_F64x2\0"
4348 /* 3864 */ "SIMD_RELAXED_FMAX_F64x2\0"
4349 /* 3888 */ "PMAX_F64x2\0"
4350 /* 3899 */ "convert_low_s_F64x2\0"
4351 /* 3919 */ "convert_low_u_F64x2\0"
4352 /* 3939 */ "promote_low_F64x2\0"
4353 /* 3957 */ "CONST_V128_I64x2\0"
4354 /* 3974 */ "SUB_I64x2\0"
4355 /* 3984 */ "ADD_I64x2\0"
4356 /* 3994 */ "REPLACE_LANE_I64x2\0"
4357 /* 4013 */ "EXTRACT_LANE_I64x2\0"
4358 /* 4032 */ "ALLTRUE_I64x2\0"
4359 /* 4046 */ "NEG_I64x2\0"
4360 /* 4056 */ "BITMASK_I64x2\0"
4361 /* 4070 */ "SHL_I64x2\0"
4362 /* 4080 */ "MUL_I64x2\0"
4363 /* 4090 */ "EQ_I64x2\0"
4364 /* 4099 */ "ABS_I64x2\0"
4365 /* 4109 */ "GE_S_I64x2\0"
4366 /* 4120 */ "LE_S_I64x2\0"
4367 /* 4131 */ "EXTMUL_HIGH_S_I64x2\0"
4368 /* 4151 */ "SHR_S_I64x2\0"
4369 /* 4163 */ "GT_S_I64x2\0"
4370 /* 4174 */ "LT_S_I64x2\0"
4371 /* 4185 */ "EXTMUL_LOW_S_I64x2\0"
4372 /* 4204 */ "SPLAT_I64x2\0"
4373 /* 4216 */ "LANESELECT_I64x2\0"
4374 /* 4233 */ "EXTMUL_HIGH_U_I64x2\0"
4375 /* 4253 */ "SHR_U_I64x2\0"
4376 /* 4265 */ "EXTMUL_LOW_U_I64x2\0"
4377 /* 4284 */ "extend_high_s_I64x2\0"
4378 /* 4304 */ "extend_low_s_I64x2\0"
4379 /* 4323 */ "extend_high_u_I64x2\0"
4380 /* 4343 */ "extend_low_u_I64x2\0"
4381 /* 4362 */ "LOAD_F16_F32_A64\0"
4382 /* 4379 */ "STORE_F16_F32_A64\0"
4383 /* 4397 */ "LOAD_F32_A64\0"
4384 /* 4410 */ "STORE_F32_A64\0"
4385 /* 4424 */ "ATOMIC_STORE16_I32_A64\0"
4386 /* 4447 */ "ATOMIC_STORE8_I32_A64\0"
4387 /* 4469 */ "ATOMIC_RMW16_U_SUB_I32_A64\0"
4388 /* 4496 */ "ATOMIC_RMW8_U_SUB_I32_A64\0"
4389 /* 4522 */ "ATOMIC_RMW_SUB_I32_A64\0"
4390 /* 4545 */ "ATOMIC_LOAD_I32_A64\0"
4391 /* 4565 */ "ATOMIC_RMW16_U_ADD_I32_A64\0"
4392 /* 4592 */ "ATOMIC_RMW8_U_ADD_I32_A64\0"
4393 /* 4618 */ "ATOMIC_RMW_ADD_I32_A64\0"
4394 /* 4641 */ "ATOMIC_RMW16_U_AND_I32_A64\0"
4395 /* 4668 */ "ATOMIC_RMW8_U_AND_I32_A64\0"
4396 /* 4694 */ "ATOMIC_RMW_AND_I32_A64\0"
4397 /* 4717 */ "ATOMIC_STORE_I32_A64\0"
4398 /* 4738 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64\0"
4399 /* 4769 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64\0"
4400 /* 4799 */ "ATOMIC_RMW_CMPXCHG_I32_A64\0"
4401 /* 4826 */ "ATOMIC_RMW16_U_XCHG_I32_A64\0"
4402 /* 4854 */ "ATOMIC_RMW8_U_XCHG_I32_A64\0"
4403 /* 4881 */ "ATOMIC_RMW_XCHG_I32_A64\0"
4404 /* 4905 */ "ATOMIC_RMW16_U_XOR_I32_A64\0"
4405 /* 4932 */ "ATOMIC_RMW8_U_XOR_I32_A64\0"
4406 /* 4958 */ "ATOMIC_RMW_XOR_I32_A64\0"
4407 /* 4981 */ "ATOMIC_RMW16_U_OR_I32_A64\0"
4408 /* 5007 */ "ATOMIC_RMW8_U_OR_I32_A64\0"
4409 /* 5032 */ "ATOMIC_RMW_OR_I32_A64\0"
4410 /* 5054 */ "LOAD16_S_I32_A64\0"
4411 /* 5071 */ "LOAD8_S_I32_A64\0"
4412 /* 5087 */ "ATOMIC_LOAD16_U_I32_A64\0"
4413 /* 5111 */ "ATOMIC_LOAD8_U_I32_A64\0"
4414 /* 5134 */ "MEMORY_ATOMIC_WAIT32_A64\0"
4415 /* 5159 */ "LOAD_LANE_I64x2_A64\0"
4416 /* 5179 */ "STORE_LANE_I64x2_A64\0"
4417 /* 5200 */ "LOAD_ZERO_I64x2_A64\0"
4418 /* 5220 */ "LOAD_EXTEND_S_I64x2_A64\0"
4419 /* 5244 */ "LOAD_EXTEND_U_I64x2_A64\0"
4420 /* 5268 */ "LOAD_F64_A64\0"
4421 /* 5281 */ "STORE_F64_A64\0"
4422 /* 5295 */ "ATOMIC_STORE32_I64_A64\0"
4423 /* 5318 */ "ATOMIC_STORE16_I64_A64\0"
4424 /* 5341 */ "ATOMIC_STORE8_I64_A64\0"
4425 /* 5363 */ "ATOMIC_RMW32_U_SUB_I64_A64\0"
4426 /* 5390 */ "ATOMIC_RMW16_U_SUB_I64_A64\0"
4427 /* 5417 */ "ATOMIC_RMW8_U_SUB_I64_A64\0"
4428 /* 5443 */ "ATOMIC_RMW_SUB_I64_A64\0"
4429 /* 5466 */ "ATOMIC_LOAD_I64_A64\0"
4430 /* 5486 */ "ATOMIC_RMW32_U_ADD_I64_A64\0"
4431 /* 5513 */ "ATOMIC_RMW16_U_ADD_I64_A64\0"
4432 /* 5540 */ "ATOMIC_RMW8_U_ADD_I64_A64\0"
4433 /* 5566 */ "ATOMIC_RMW_ADD_I64_A64\0"
4434 /* 5589 */ "ATOMIC_RMW32_U_AND_I64_A64\0"
4435 /* 5616 */ "ATOMIC_RMW16_U_AND_I64_A64\0"
4436 /* 5643 */ "ATOMIC_RMW8_U_AND_I64_A64\0"
4437 /* 5669 */ "ATOMIC_RMW_AND_I64_A64\0"
4438 /* 5692 */ "ATOMIC_STORE_I64_A64\0"
4439 /* 5713 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64\0"
4440 /* 5744 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64\0"
4441 /* 5775 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64\0"
4442 /* 5805 */ "ATOMIC_RMW_CMPXCHG_I64_A64\0"
4443 /* 5832 */ "ATOMIC_RMW32_U_XCHG_I64_A64\0"
4444 /* 5860 */ "ATOMIC_RMW16_U_XCHG_I64_A64\0"
4445 /* 5888 */ "ATOMIC_RMW8_U_XCHG_I64_A64\0"
4446 /* 5915 */ "ATOMIC_RMW_XCHG_I64_A64\0"
4447 /* 5939 */ "ATOMIC_RMW32_U_XOR_I64_A64\0"
4448 /* 5966 */ "ATOMIC_RMW16_U_XOR_I64_A64\0"
4449 /* 5993 */ "ATOMIC_RMW8_U_XOR_I64_A64\0"
4450 /* 6019 */ "ATOMIC_RMW_XOR_I64_A64\0"
4451 /* 6042 */ "ATOMIC_RMW32_U_OR_I64_A64\0"
4452 /* 6068 */ "ATOMIC_RMW16_U_OR_I64_A64\0"
4453 /* 6094 */ "ATOMIC_RMW8_U_OR_I64_A64\0"
4454 /* 6119 */ "ATOMIC_RMW_OR_I64_A64\0"
4455 /* 6141 */ "LOAD32_S_I64_A64\0"
4456 /* 6158 */ "LOAD16_S_I64_A64\0"
4457 /* 6175 */ "LOAD8_S_I64_A64\0"
4458 /* 6191 */ "ATOMIC_LOAD32_U_I64_A64\0"
4459 /* 6215 */ "ATOMIC_LOAD16_U_I64_A64\0"
4460 /* 6239 */ "ATOMIC_LOAD8_U_I64_A64\0"
4461 /* 6262 */ "MEMORY_ATOMIC_WAIT64_A64\0"
4462 /* 6287 */ "LOAD_LANE_I32x4_A64\0"
4463 /* 6307 */ "STORE_LANE_I32x4_A64\0"
4464 /* 6328 */ "LOAD_ZERO_I32x4_A64\0"
4465 /* 6348 */ "LOAD_EXTEND_S_I32x4_A64\0"
4466 /* 6372 */ "LOAD_EXTEND_U_I32x4_A64\0"
4467 /* 6396 */ "LOAD_LANE_I8x16_A64\0"
4468 /* 6416 */ "STORE_LANE_I8x16_A64\0"
4469 /* 6437 */ "LOAD_V128_A64\0"
4470 /* 6451 */ "STORE_V128_A64\0"
4471 /* 6466 */ "LOAD_LANE_I16x8_A64\0"
4472 /* 6486 */ "STORE_LANE_I16x8_A64\0"
4473 /* 6507 */ "LOAD_EXTEND_S_I16x8_A64\0"
4474 /* 6531 */ "LOAD_EXTEND_U_I16x8_A64\0"
4475 /* 6555 */ "anonymous_8188MEMORY_SIZE_A64\0"
4476 /* 6585 */ "anonymous_8879MEMORY_FILL_A64\0"
4477 /* 6615 */ "LOAD32_SPLAT_A64\0"
4478 /* 6632 */ "LOAD64_SPLAT_A64\0"
4479 /* 6649 */ "LOAD16_SPLAT_A64\0"
4480 /* 6666 */ "LOAD8_SPLAT_A64\0"
4481 /* 6682 */ "anonymous_8879MEMORY_INIT_A64\0"
4482 /* 6712 */ "anonymous_8188MEMORY_GROW_A64\0"
4483 /* 6742 */ "MEMORY_ATOMIC_NOTIFY_A64\0"
4484 /* 6767 */ "anonymous_8879MEMORY_COPY_A64\0"
4485 /* 6797 */ "FP_TO_SINT_I32_F64\0"
4486 /* 6816 */ "FP_TO_UINT_I32_F64\0"
4487 /* 6835 */ "FP_TO_SINT_I64_F64\0"
4488 /* 6854 */ "FP_TO_UINT_I64_F64\0"
4489 /* 6873 */ "SUB_F64\0"
4490 /* 6881 */ "TRUNC_F64\0"
4491 /* 6891 */ "ADD_F64\0"
4492 /* 6899 */ "LOCAL_TEE_F64\0"
4493 /* 6913 */ "GE_F64\0"
4494 /* 6920 */ "LE_F64\0"
4495 /* 6927 */ "NE_F64\0"
4496 /* 6934 */ "F32_DEMOTE_F64\0"
4497 /* 6949 */ "NEG_F64\0"
4498 /* 6957 */ "CEIL_F64\0"
4499 /* 6966 */ "MUL_F64\0"
4500 /* 6974 */ "COPYSIGN_F64\0"
4501 /* 6987 */ "MIN_F64\0"
4502 /* 6995 */ "DROP_F64\0"
4503 /* 7004 */ "EQ_F64\0"
4504 /* 7011 */ "FLOOR_F64\0"
4505 /* 7021 */ "ABS_F64\0"
4506 /* 7029 */ "I32_TRUNC_S_F64\0"
4507 /* 7045 */ "I64_TRUNC_S_F64\0"
4508 /* 7061 */ "I32_TRUNC_S_SAT_F64\0"
4509 /* 7081 */ "I64_TRUNC_S_SAT_F64\0"
4510 /* 7101 */ "I32_TRUNC_U_SAT_F64\0"
4511 /* 7121 */ "I64_TRUNC_U_SAT_F64\0"
4512 /* 7141 */ "SELECT_F64\0"
4513 /* 7152 */ "GLOBAL_GET_F64\0"
4514 /* 7167 */ "LOCAL_GET_F64\0"
4515 /* 7181 */ "I64_REINTERPRET_F64\0"
4516 /* 7201 */ "GLOBAL_SET_F64\0"
4517 /* 7216 */ "LOCAL_SET_F64\0"
4518 /* 7230 */ "GT_F64\0"
4519 /* 7237 */ "LT_F64\0"
4520 /* 7244 */ "SQRT_F64\0"
4521 /* 7253 */ "NEAREST_F64\0"
4522 /* 7265 */ "CONST_F64\0"
4523 /* 7275 */ "I32_TRUNC_U_F64\0"
4524 /* 7291 */ "I64_TRUNC_U_F64\0"
4525 /* 7307 */ "DIV_F64\0"
4526 /* 7315 */ "MAX_F64\0"
4527 /* 7323 */ "COPY_F64\0"
4528 /* 7332 */ "SUB_I64\0"
4529 /* 7340 */ "ADD_I64\0"
4530 /* 7348 */ "AND_I64\0"
4531 /* 7356 */ "LOCAL_TEE_I64\0"
4532 /* 7370 */ "BR_TABLE_I64\0"
4533 /* 7383 */ "NE_I64\0"
4534 /* 7390 */ "SHL_I64\0"
4535 /* 7398 */ "ROTL_I64\0"
4536 /* 7407 */ "MUL_I64\0"
4537 /* 7415 */ "I32_WRAP_I64\0"
4538 /* 7428 */ "DROP_I64\0"
4539 /* 7437 */ "EQ_I64\0"
4540 /* 7444 */ "XOR_I64\0"
4541 /* 7452 */ "ROTR_I64\0"
4542 /* 7461 */ "I64_EXTEND32_S_I64\0"
4543 /* 7480 */ "I64_EXTEND16_S_I64\0"
4544 /* 7499 */ "I64_EXTEND8_S_I64\0"
4545 /* 7517 */ "GE_S_I64\0"
4546 /* 7526 */ "LE_S_I64\0"
4547 /* 7535 */ "REM_S_I64\0"
4548 /* 7545 */ "SHR_S_I64\0"
4549 /* 7555 */ "GT_S_I64\0"
4550 /* 7564 */ "LT_S_I64\0"
4551 /* 7573 */ "F32_CONVERT_S_I64\0"
4552 /* 7591 */ "F64_CONVERT_S_I64\0"
4553 /* 7609 */ "DIV_S_I64\0"
4554 /* 7619 */ "SELECT_I64\0"
4555 /* 7630 */ "GLOBAL_GET_I64\0"
4556 /* 7645 */ "LOCAL_GET_I64\0"
4557 /* 7659 */ "F64_REINTERPRET_I64\0"
4558 /* 7679 */ "GLOBAL_SET_I64\0"
4559 /* 7694 */ "LOCAL_SET_I64\0"
4560 /* 7708 */ "POPCNT_I64\0"
4561 /* 7719 */ "CONST_I64\0"
4562 /* 7729 */ "GE_U_I64\0"
4563 /* 7738 */ "LE_U_I64\0"
4564 /* 7747 */ "REM_U_I64\0"
4565 /* 7757 */ "SHR_U_I64\0"
4566 /* 7767 */ "GT_U_I64\0"
4567 /* 7776 */ "LT_U_I64\0"
4568 /* 7785 */ "F32_CONVERT_U_I64\0"
4569 /* 7803 */ "F64_CONVERT_U_I64\0"
4570 /* 7821 */ "DIV_U_I64\0"
4571 /* 7831 */ "COPY_I64\0"
4572 /* 7840 */ "CLZ_I64\0"
4573 /* 7848 */ "EQZ_I64\0"
4574 /* 7856 */ "CTZ_I64\0"
4575 /* 7864 */ "ARGUMENT_v2f64\0"
4576 /* 7879 */ "ARGUMENT_f64\0"
4577 /* 7892 */ "ARGUMENT_v2i64\0"
4578 /* 7907 */ "ARGUMENT_i64\0"
4579 /* 7920 */ "CONST_V128_F32x4\0"
4580 /* 7937 */ "SUB_F32x4\0"
4581 /* 7947 */ "TRUNC_F32x4\0"
4582 /* 7959 */ "NMADD_F32x4\0"
4583 /* 7971 */ "GE_F32x4\0"
4584 /* 7980 */ "LE_F32x4\0"
4585 /* 7989 */ "REPLACE_LANE_F32x4\0"
4586 /* 8008 */ "EXTRACT_LANE_F32x4\0"
4587 /* 8027 */ "NEG_F32x4\0"
4588 /* 8037 */ "CEIL_F32x4\0"
4589 /* 8048 */ "MUL_F32x4\0"
4590 /* 8058 */ "SIMD_RELAXED_FMIN_F32x4\0"
4591 /* 8082 */ "PMIN_F32x4\0"
4592 /* 8093 */ "EQ_F32x4\0"
4593 /* 8102 */ "FLOOR_F32x4\0"
4594 /* 8114 */ "ABS_F32x4\0"
4595 /* 8124 */ "SPLAT_F32x4\0"
4596 /* 8136 */ "GT_F32x4\0"
4597 /* 8145 */ "LT_F32x4\0"
4598 /* 8154 */ "SQRT_F32x4\0"
4599 /* 8165 */ "NEAREST_F32x4\0"
4600 /* 8179 */ "DIV_F32x4\0"
4601 /* 8189 */ "SIMD_RELAXED_FMAX_F32x4\0"
4602 /* 8213 */ "PMAX_F32x4\0"
4603 /* 8224 */ "demote_zero_F32x4\0"
4604 /* 8242 */ "sint_to_fp_F32x4\0"
4605 /* 8259 */ "uint_to_fp_F32x4\0"
4606 /* 8276 */ "CONST_V128_I32x4\0"
4607 /* 8293 */ "SUB_I32x4\0"
4608 /* 8303 */ "ADD_I32x4\0"
4609 /* 8313 */ "REPLACE_LANE_I32x4\0"
4610 /* 8332 */ "EXTRACT_LANE_I32x4\0"
4611 /* 8351 */ "ALLTRUE_I32x4\0"
4612 /* 8365 */ "NEG_I32x4\0"
4613 /* 8375 */ "BITMASK_I32x4\0"
4614 /* 8389 */ "SHL_I32x4\0"
4615 /* 8399 */ "MUL_I32x4\0"
4616 /* 8409 */ "EQ_I32x4\0"
4617 /* 8418 */ "ABS_I32x4\0"
4618 /* 8428 */ "GE_S_I32x4\0"
4619 /* 8439 */ "LE_S_I32x4\0"
4620 /* 8450 */ "EXTMUL_HIGH_S_I32x4\0"
4621 /* 8470 */ "MIN_S_I32x4\0"
4622 /* 8482 */ "SHR_S_I32x4\0"
4623 /* 8494 */ "GT_S_I32x4\0"
4624 /* 8505 */ "LT_S_I32x4\0"
4625 /* 8516 */ "EXTMUL_LOW_S_I32x4\0"
4626 /* 8535 */ "MAX_S_I32x4\0"
4627 /* 8547 */ "SPLAT_I32x4\0"
4628 /* 8559 */ "LANESELECT_I32x4\0"
4629 /* 8576 */ "GE_U_I32x4\0"
4630 /* 8587 */ "LE_U_I32x4\0"
4631 /* 8598 */ "EXTMUL_HIGH_U_I32x4\0"
4632 /* 8618 */ "MIN_U_I32x4\0"
4633 /* 8630 */ "SHR_U_I32x4\0"
4634 /* 8642 */ "GT_U_I32x4\0"
4635 /* 8653 */ "LT_U_I32x4\0"
4636 /* 8664 */ "EXTMUL_LOW_U_I32x4\0"
4637 /* 8683 */ "MAX_U_I32x4\0"
4638 /* 8695 */ "int_wasm_relaxed_trunc_signed_I32x4\0"
4639 /* 8731 */ "int_wasm_extadd_pairwise_signed_I32x4\0"
4640 /* 8769 */ "int_wasm_relaxed_trunc_unsigned_I32x4\0"
4641 /* 8807 */ "int_wasm_extadd_pairwise_unsigned_I32x4\0"
4642 /* 8847 */ "int_wasm_relaxed_trunc_signed_zero_I32x4\0"
4643 /* 8888 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4\0"
4644 /* 8931 */ "extend_high_s_I32x4\0"
4645 /* 8951 */ "trunc_sat_zero_s_I32x4\0"
4646 /* 8974 */ "extend_low_s_I32x4\0"
4647 /* 8993 */ "fp_to_sint_I32x4\0"
4648 /* 9010 */ "fp_to_uint_I32x4\0"
4649 /* 9027 */ "extend_high_u_I32x4\0"
4650 /* 9047 */ "trunc_sat_zero_u_I32x4\0"
4651 /* 9070 */ "extend_low_u_I32x4\0"
4652 /* 9089 */ "ARGUMENT_v8f16\0"
4653 /* 9104 */ "ARGUMENT_v8i16\0"
4654 /* 9119 */ "CONST_V128_I8x16\0"
4655 /* 9136 */ "SUB_I8x16\0"
4656 /* 9146 */ "ADD_I8x16\0"
4657 /* 9156 */ "REPLACE_LANE_I8x16\0"
4658 /* 9175 */ "ALLTRUE_I8x16\0"
4659 /* 9189 */ "NEG_I8x16\0"
4660 /* 9199 */ "BITMASK_I8x16\0"
4661 /* 9213 */ "SHL_I8x16\0"
4662 /* 9223 */ "EQ_I8x16\0"
4663 /* 9232 */ "ABS_I8x16\0"
4664 /* 9242 */ "GE_S_I8x16\0"
4665 /* 9253 */ "LE_S_I8x16\0"
4666 /* 9264 */ "MIN_S_I8x16\0"
4667 /* 9276 */ "SHR_S_I8x16\0"
4668 /* 9288 */ "SUB_SAT_S_I8x16\0"
4669 /* 9304 */ "ADD_SAT_S_I8x16\0"
4670 /* 9320 */ "GT_S_I8x16\0"
4671 /* 9331 */ "LT_S_I8x16\0"
4672 /* 9342 */ "NARROW_S_I8x16\0"
4673 /* 9357 */ "MAX_S_I8x16\0"
4674 /* 9369 */ "SPLAT_I8x16\0"
4675 /* 9381 */ "LANESELECT_I8x16\0"
4676 /* 9398 */ "POPCNT_I8x16\0"
4677 /* 9411 */ "GE_U_I8x16\0"
4678 /* 9422 */ "LE_U_I8x16\0"
4679 /* 9433 */ "MIN_U_I8x16\0"
4680 /* 9445 */ "AVGR_U_I8x16\0"
4681 /* 9458 */ "SHR_U_I8x16\0"
4682 /* 9470 */ "SUB_SAT_U_I8x16\0"
4683 /* 9486 */ "ADD_SAT_U_I8x16\0"
4684 /* 9502 */ "GT_U_I8x16\0"
4685 /* 9513 */ "LT_U_I8x16\0"
4686 /* 9524 */ "NARROW_U_I8x16\0"
4687 /* 9539 */ "MAX_U_I8x16\0"
4688 /* 9551 */ "LOCAL_TEE_V128\0"
4689 /* 9566 */ "DROP_V128\0"
4690 /* 9576 */ "SELECT_V128\0"
4691 /* 9588 */ "GLOBAL_GET_V128\0"
4692 /* 9604 */ "LOCAL_GET_V128\0"
4693 /* 9619 */ "GLOBAL_SET_V128\0"
4694 /* 9635 */ "LOCAL_SET_V128\0"
4695 /* 9650 */ "COPY_V128\0"
4696 /* 9660 */ "ARGUMENT_v16i8\0"
4697 /* 9675 */ "SUB_F16x8\0"
4698 /* 9685 */ "TRUNC_F16x8\0"
4699 /* 9697 */ "NMADD_F16x8\0"
4700 /* 9709 */ "GE_F16x8\0"
4701 /* 9718 */ "LE_F16x8\0"
4702 /* 9727 */ "EXTRACT_LANE_F16x8\0"
4703 /* 9746 */ "NEG_F16x8\0"
4704 /* 9756 */ "CEIL_F16x8\0"
4705 /* 9767 */ "MUL_F16x8\0"
4706 /* 9777 */ "PMIN_F16x8\0"
4707 /* 9788 */ "EQ_F16x8\0"
4708 /* 9797 */ "FLOOR_F16x8\0"
4709 /* 9809 */ "ABS_F16x8\0"
4710 /* 9819 */ "SPLAT_F16x8\0"
4711 /* 9831 */ "GT_F16x8\0"
4712 /* 9840 */ "LT_F16x8\0"
4713 /* 9849 */ "SQRT_F16x8\0"
4714 /* 9860 */ "NEAREST_F16x8\0"
4715 /* 9874 */ "DIV_F16x8\0"
4716 /* 9884 */ "PMAX_F16x8\0"
4717 /* 9895 */ "sint_to_fp_F16x8\0"
4718 /* 9912 */ "uint_to_fp_F16x8\0"
4719 /* 9929 */ "CONST_V128_I16x8\0"
4720 /* 9946 */ "SUB_I16x8\0"
4721 /* 9956 */ "ADD_I16x8\0"
4722 /* 9966 */ "REPLACE_LANE_I16x8\0"
4723 /* 9985 */ "ALLTRUE_I16x8\0"
4724 /* 9999 */ "NEG_I16x8\0"
4725 /* 10009 */ "BITMASK_I16x8\0"
4726 /* 10023 */ "SHL_I16x8\0"
4727 /* 10033 */ "MUL_I16x8\0"
4728 /* 10043 */ "EQ_I16x8\0"
4729 /* 10052 */ "ABS_I16x8\0"
4730 /* 10062 */ "GE_S_I16x8\0"
4731 /* 10073 */ "LE_S_I16x8\0"
4732 /* 10084 */ "EXTMUL_HIGH_S_I16x8\0"
4733 /* 10104 */ "MIN_S_I16x8\0"
4734 /* 10116 */ "SHR_S_I16x8\0"
4735 /* 10128 */ "RELAXED_Q15MULR_S_I16x8\0"
4736 /* 10152 */ "SUB_SAT_S_I16x8\0"
4737 /* 10168 */ "ADD_SAT_S_I16x8\0"
4738 /* 10184 */ "Q15MULR_SAT_S_I16x8\0"
4739 /* 10204 */ "GT_S_I16x8\0"
4740 /* 10215 */ "LT_S_I16x8\0"
4741 /* 10226 */ "EXTMUL_LOW_S_I16x8\0"
4742 /* 10245 */ "NARROW_S_I16x8\0"
4743 /* 10260 */ "MAX_S_I16x8\0"
4744 /* 10272 */ "SPLAT_I16x8\0"
4745 /* 10284 */ "LANESELECT_I16x8\0"
4746 /* 10301 */ "GE_U_I16x8\0"
4747 /* 10312 */ "LE_U_I16x8\0"
4748 /* 10323 */ "EXTMUL_HIGH_U_I16x8\0"
4749 /* 10343 */ "MIN_U_I16x8\0"
4750 /* 10355 */ "AVGR_U_I16x8\0"
4751 /* 10368 */ "SHR_U_I16x8\0"
4752 /* 10380 */ "SUB_SAT_U_I16x8\0"
4753 /* 10396 */ "ADD_SAT_U_I16x8\0"
4754 /* 10412 */ "GT_U_I16x8\0"
4755 /* 10423 */ "LT_U_I16x8\0"
4756 /* 10434 */ "EXTMUL_LOW_U_I16x8\0"
4757 /* 10453 */ "NARROW_U_I16x8\0"
4758 /* 10468 */ "MAX_U_I16x8\0"
4759 /* 10480 */ "int_wasm_extadd_pairwise_signed_I16x8\0"
4760 /* 10518 */ "int_wasm_extadd_pairwise_unsigned_I16x8\0"
4761 /* 10558 */ "extend_high_s_I16x8\0"
4762 /* 10578 */ "extend_low_s_I16x8\0"
4763 /* 10597 */ "fp_to_sint_I16x8\0"
4764 /* 10614 */ "fp_to_uint_I16x8\0"
4765 /* 10631 */ "extend_high_u_I16x8\0"
4766 /* 10651 */ "extend_low_u_I16x8\0"
4767 /* 10670 */ "G_FMA\0"
4768 /* 10676 */ "G_STRICT_FMA\0"
4769 /* 10689 */ "G_FSUB\0"
4770 /* 10696 */ "G_STRICT_FSUB\0"
4771 /* 10710 */ "G_ATOMICRMW_FSUB\0"
4772 /* 10727 */ "G_SUB\0"
4773 /* 10733 */ "G_ATOMICRMW_SUB\0"
4774 /* 10749 */ "G_INTRINSIC\0"
4775 /* 10761 */ "G_FPTRUNC\0"
4776 /* 10771 */ "G_INTRINSIC_TRUNC\0"
4777 /* 10789 */ "G_TRUNC\0"
4778 /* 10797 */ "G_BUILD_VECTOR_TRUNC\0"
4779 /* 10818 */ "G_DYN_STACKALLOC\0"
4780 /* 10835 */ "G_FMAD\0"
4781 /* 10842 */ "G_INDEXED_SEXTLOAD\0"
4782 /* 10861 */ "G_SEXTLOAD\0"
4783 /* 10872 */ "G_INDEXED_ZEXTLOAD\0"
4784 /* 10891 */ "G_ZEXTLOAD\0"
4785 /* 10902 */ "G_INDEXED_LOAD\0"
4786 /* 10917 */ "G_LOAD\0"
4787 /* 10924 */ "G_VECREDUCE_FADD\0"
4788 /* 10941 */ "G_FADD\0"
4789 /* 10948 */ "G_VECREDUCE_SEQ_FADD\0"
4790 /* 10969 */ "G_STRICT_FADD\0"
4791 /* 10983 */ "G_ATOMICRMW_FADD\0"
4792 /* 11000 */ "G_VECREDUCE_ADD\0"
4793 /* 11016 */ "G_ADD\0"
4794 /* 11022 */ "G_PTR_ADD\0"
4795 /* 11032 */ "RELAXED_DOT_ADD\0"
4796 /* 11048 */ "G_ATOMICRMW_ADD\0"
4797 /* 11064 */ "G_ATOMICRMW_NAND\0"
4798 /* 11081 */ "G_VECREDUCE_AND\0"
4799 /* 11097 */ "G_AND\0"
4800 /* 11103 */ "G_ATOMICRMW_AND\0"
4801 /* 11119 */ "LIFETIME_END\0"
4802 /* 11132 */ "G_BRCOND\0"
4803 /* 11141 */ "G_LLROUND\0"
4804 /* 11151 */ "G_LROUND\0"
4805 /* 11160 */ "G_INTRINSIC_ROUND\0"
4806 /* 11178 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
4807 /* 11204 */ "LOAD_STACK_GUARD\0"
4808 /* 11221 */ "PSEUDO_PROBE\0"
4809 /* 11234 */ "G_SSUBE\0"
4810 /* 11242 */ "G_USUBE\0"
4811 /* 11250 */ "ATOMIC_FENCE\0"
4812 /* 11263 */ "G_FENCE\0"
4813 /* 11271 */ "ARITH_FENCE\0"
4814 /* 11283 */ "COMPILER_FENCE\0"
4815 /* 11298 */ "REG_SEQUENCE\0"
4816 /* 11311 */ "G_SADDE\0"
4817 /* 11319 */ "G_UADDE\0"
4818 /* 11327 */ "G_GET_FPMODE\0"
4819 /* 11340 */ "G_RESET_FPMODE\0"
4820 /* 11355 */ "G_SET_FPMODE\0"
4821 /* 11368 */ "G_FMINNUM_IEEE\0"
4822 /* 11383 */ "G_FMAXNUM_IEEE\0"
4823 /* 11398 */ "G_VSCALE\0"
4824 /* 11407 */ "DEBUG_UNREACHABLE\0"
4825 /* 11425 */ "G_JUMP_TABLE\0"
4826 /* 11438 */ "BUNDLE\0"
4827 /* 11445 */ "SHUFFLE\0"
4828 /* 11453 */ "RELAXED_SWIZZLE\0"
4829 /* 11469 */ "G_MEMCPY_INLINE\0"
4830 /* 11485 */ "LOCAL_ESCAPE\0"
4831 /* 11498 */ "G_STACKRESTORE\0"
4832 /* 11513 */ "G_INDEXED_STORE\0"
4833 /* 11529 */ "G_STORE\0"
4834 /* 11537 */ "ELSE\0"
4835 /* 11542 */ "G_BITREVERSE\0"
4836 /* 11555 */ "DELEGATE\0"
4837 /* 11564 */ "DBG_VALUE\0"
4838 /* 11574 */ "G_GLOBAL_VALUE\0"
4839 /* 11589 */ "G_PTRAUTH_GLOBAL_VALUE\0"
4840 /* 11612 */ "CONVERGENCECTRL_GLUE\0"
4841 /* 11633 */ "ANYTRUE\0"
4842 /* 11641 */ "G_STACKSAVE\0"
4843 /* 11653 */ "G_MEMMOVE\0"
4844 /* 11663 */ "G_FREEZE\0"
4845 /* 11672 */ "G_FCANONICALIZE\0"
4846 /* 11688 */ "TABLE_SIZE\0"
4847 /* 11699 */ "G_CTLZ_ZERO_UNDEF\0"
4848 /* 11717 */ "G_CTTZ_ZERO_UNDEF\0"
4849 /* 11735 */ "G_IMPLICIT_DEF\0"
4850 /* 11750 */ "LOCAL_TEE_FUNCREF\0"
4851 /* 11768 */ "TABLE_FILL_FUNCREF\0"
4852 /* 11787 */ "REF_NULL_FUNCREF\0"
4853 /* 11804 */ "REF_IS_NULL_FUNCREF\0"
4854 /* 11824 */ "DROP_FUNCREF\0"
4855 /* 11837 */ "SELECT_FUNCREF\0"
4856 /* 11852 */ "TABLE_GET_FUNCREF\0"
4857 /* 11870 */ "GLOBAL_GET_FUNCREF\0"
4858 /* 11889 */ "LOCAL_GET_FUNCREF\0"
4859 /* 11907 */ "TABLE_SET_FUNCREF\0"
4860 /* 11925 */ "GLOBAL_SET_FUNCREF\0"
4861 /* 11944 */ "LOCAL_SET_FUNCREF\0"
4862 /* 11962 */ "TABLE_GROW_FUNCREF\0"
4863 /* 11981 */ "COPY_FUNCREF\0"
4864 /* 11994 */ "LOCAL_TEE_EXTERNREF\0"
4865 /* 12014 */ "TABLE_FILL_EXTERNREF\0"
4866 /* 12035 */ "REF_NULL_EXTERNREF\0"
4867 /* 12054 */ "REF_IS_NULL_EXTERNREF\0"
4868 /* 12076 */ "DROP_EXTERNREF\0"
4869 /* 12091 */ "SELECT_EXTERNREF\0"
4870 /* 12108 */ "TABLE_GET_EXTERNREF\0"
4871 /* 12128 */ "GLOBAL_GET_EXTERNREF\0"
4872 /* 12149 */ "LOCAL_GET_EXTERNREF\0"
4873 /* 12169 */ "TABLE_SET_EXTERNREF\0"
4874 /* 12189 */ "GLOBAL_SET_EXTERNREF\0"
4875 /* 12210 */ "LOCAL_SET_EXTERNREF\0"
4876 /* 12230 */ "TABLE_GROW_EXTERNREF\0"
4877 /* 12251 */ "COPY_EXTERNREF\0"
4878 /* 12266 */ "LOCAL_TEE_EXNREF\0"
4879 /* 12283 */ "TABLE_FILL_EXNREF\0"
4880 /* 12301 */ "REF_NULL_EXNREF\0"
4881 /* 12317 */ "REF_IS_NULL_EXNREF\0"
4882 /* 12336 */ "DROP_EXNREF\0"
4883 /* 12348 */ "SELECT_EXNREF\0"
4884 /* 12362 */ "TABLE_GET_EXNREF\0"
4885 /* 12379 */ "GLOBAL_GET_EXNREF\0"
4886 /* 12397 */ "LOCAL_GET_EXNREF\0"
4887 /* 12414 */ "TABLE_SET_EXNREF\0"
4888 /* 12431 */ "GLOBAL_SET_EXNREF\0"
4889 /* 12449 */ "LOCAL_SET_EXNREF\0"
4890 /* 12466 */ "TABLE_GROW_EXNREF\0"
4891 /* 12484 */ "COPY_EXNREF\0"
4892 /* 12496 */ "DBG_INSTR_REF\0"
4893 /* 12510 */ "END_IF\0"
4894 /* 12517 */ "BR_IF\0"
4895 /* 12523 */ "G_FNEG\0"
4896 /* 12530 */ "EXTRACT_SUBREG\0"
4897 /* 12545 */ "INSERT_SUBREG\0"
4898 /* 12559 */ "G_SEXT_INREG\0"
4899 /* 12572 */ "SUBREG_TO_REG\0"
4900 /* 12586 */ "G_ATOMIC_CMPXCHG\0"
4901 /* 12603 */ "G_ATOMICRMW_XCHG\0"
4902 /* 12620 */ "G_FLOG\0"
4903 /* 12627 */ "G_VAARG\0"
4904 /* 12635 */ "PREALLOCATED_ARG\0"
4905 /* 12652 */ "CATCH\0"
4906 /* 12658 */ "G_PREFETCH\0"
4907 /* 12669 */ "G_SMULH\0"
4908 /* 12677 */ "G_UMULH\0"
4909 /* 12685 */ "G_FTANH\0"
4910 /* 12693 */ "G_FSINH\0"
4911 /* 12701 */ "G_FCOSH\0"
4912 /* 12709 */ "DBG_PHI\0"
4913 /* 12717 */ "G_FPTOSI\0"
4914 /* 12726 */ "G_FPTOUI\0"
4915 /* 12735 */ "G_FPOWI\0"
4916 /* 12743 */ "END_BLOCK\0"
4917 /* 12753 */ "G_PTRMASK\0"
4918 /* 12763 */ "GC_LABEL\0"
4919 /* 12772 */ "DBG_LABEL\0"
4920 /* 12782 */ "EH_LABEL\0"
4921 /* 12791 */ "ANNOTATION_LABEL\0"
4922 /* 12808 */ "ICALL_BRANCH_FUNNEL\0"
4923 /* 12828 */ "G_FSHL\0"
4924 /* 12835 */ "G_SHL\0"
4925 /* 12841 */ "G_FCEIL\0"
4926 /* 12849 */ "PATCHABLE_TAIL_CALL\0"
4927 /* 12869 */ "RET_CALL\0"
4928 /* 12878 */ "PATCHABLE_TYPED_EVENT_CALL\0"
4929 /* 12905 */ "PATCHABLE_EVENT_CALL\0"
4930 /* 12926 */ "FENTRY_CALL\0"
4931 /* 12938 */ "CATCH_ALL\0"
4932 /* 12948 */ "KILL\0"
4933 /* 12953 */ "G_CONSTANT_POOL\0"
4934 /* 12969 */ "G_ROTL\0"
4935 /* 12976 */ "G_VECREDUCE_FMUL\0"
4936 /* 12993 */ "G_FMUL\0"
4937 /* 13000 */ "G_VECREDUCE_SEQ_FMUL\0"
4938 /* 13021 */ "G_STRICT_FMUL\0"
4939 /* 13035 */ "G_VECREDUCE_MUL\0"
4940 /* 13051 */ "G_MUL\0"
4941 /* 13057 */ "G_FREM\0"
4942 /* 13064 */ "G_STRICT_FREM\0"
4943 /* 13078 */ "G_SREM\0"
4944 /* 13085 */ "G_UREM\0"
4945 /* 13092 */ "G_SDIVREM\0"
4946 /* 13102 */ "G_UDIVREM\0"
4947 /* 13112 */ "INLINEASM\0"
4948 /* 13122 */ "G_VECREDUCE_FMINIMUM\0"
4949 /* 13143 */ "G_FMINIMUM\0"
4950 /* 13154 */ "G_VECREDUCE_FMAXIMUM\0"
4951 /* 13175 */ "G_FMAXIMUM\0"
4952 /* 13186 */ "G_FMINNUM\0"
4953 /* 13196 */ "G_FMAXNUM\0"
4954 /* 13206 */ "G_FATAN\0"
4955 /* 13214 */ "G_FTAN\0"
4956 /* 13221 */ "G_INTRINSIC_ROUNDEVEN\0"
4957 /* 13243 */ "G_ASSERT_ALIGN\0"
4958 /* 13258 */ "G_FCOPYSIGN\0"
4959 /* 13270 */ "G_VECREDUCE_FMIN\0"
4960 /* 13287 */ "G_ATOMICRMW_FMIN\0"
4961 /* 13304 */ "G_VECREDUCE_SMIN\0"
4962 /* 13321 */ "G_SMIN\0"
4963 /* 13328 */ "G_VECREDUCE_UMIN\0"
4964 /* 13345 */ "G_UMIN\0"
4965 /* 13352 */ "G_ATOMICRMW_UMIN\0"
4966 /* 13369 */ "G_ATOMICRMW_MIN\0"
4967 /* 13385 */ "G_FASIN\0"
4968 /* 13393 */ "G_FSIN\0"
4969 /* 13400 */ "END_FUNCTION\0"
4970 /* 13413 */ "CFI_INSTRUCTION\0"
4971 /* 13429 */ "FALLTHROUGH_RETURN\0"
4972 /* 13448 */ "ADJCALLSTACKDOWN\0"
4973 /* 13465 */ "G_SSUBO\0"
4974 /* 13473 */ "G_USUBO\0"
4975 /* 13481 */ "G_SADDO\0"
4976 /* 13489 */ "G_UADDO\0"
4977 /* 13497 */ "JUMP_TABLE_DEBUG_INFO\0"
4978 /* 13519 */ "G_SMULO\0"
4979 /* 13527 */ "G_UMULO\0"
4980 /* 13535 */ "G_BZERO\0"
4981 /* 13543 */ "STACKMAP\0"
4982 /* 13552 */ "G_DEBUGTRAP\0"
4983 /* 13564 */ "G_UBSANTRAP\0"
4984 /* 13576 */ "G_TRAP\0"
4985 /* 13583 */ "G_ATOMICRMW_UDEC_WRAP\0"
4986 /* 13605 */ "G_ATOMICRMW_UINC_WRAP\0"
4987 /* 13627 */ "G_BSWAP\0"
4988 /* 13635 */ "G_SITOFP\0"
4989 /* 13644 */ "G_UITOFP\0"
4990 /* 13653 */ "G_FCMP\0"
4991 /* 13660 */ "G_ICMP\0"
4992 /* 13667 */ "G_SCMP\0"
4993 /* 13674 */ "G_UCMP\0"
4994 /* 13681 */ "NOP\0"
4995 /* 13685 */ "END_LOOP\0"
4996 /* 13694 */ "CONVERGENCECTRL_LOOP\0"
4997 /* 13715 */ "G_CTPOP\0"
4998 /* 13723 */ "anonymous_8878DATA_DROP\0"
4999 /* 13747 */ "anonymous_8879DATA_DROP\0"
5000 /* 13771 */ "PATCHABLE_OP\0"
5001 /* 13784 */ "FAULTING_OP\0"
5002 /* 13796 */ "ADJCALLSTACKUP\0"
5003 /* 13811 */ "PREALLOCATED_SETUP\0"
5004 /* 13830 */ "G_FLDEXP\0"
5005 /* 13839 */ "G_STRICT_FLDEXP\0"
5006 /* 13855 */ "G_FEXP\0"
5007 /* 13862 */ "G_FFREXP\0"
5008 /* 13871 */ "G_BR\0"
5009 /* 13876 */ "INLINEASM_BR\0"
5010 /* 13889 */ "G_BLOCK_ADDR\0"
5011 /* 13902 */ "MEMBARRIER\0"
5012 /* 13913 */ "G_CONSTANT_FOLD_BARRIER\0"
5013 /* 13937 */ "PATCHABLE_FUNCTION_ENTER\0"
5014 /* 13962 */ "G_READCYCLECOUNTER\0"
5015 /* 13981 */ "G_READSTEADYCOUNTER\0"
5016 /* 14001 */ "G_READ_REGISTER\0"
5017 /* 14017 */ "G_WRITE_REGISTER\0"
5018 /* 14034 */ "G_ASHR\0"
5019 /* 14041 */ "G_FSHR\0"
5020 /* 14048 */ "G_LSHR\0"
5021 /* 14055 */ "CONVERGENCECTRL_ANCHOR\0"
5022 /* 14078 */ "G_FFLOOR\0"
5023 /* 14087 */ "G_EXTRACT_SUBVECTOR\0"
5024 /* 14107 */ "G_INSERT_SUBVECTOR\0"
5025 /* 14126 */ "G_BUILD_VECTOR\0"
5026 /* 14141 */ "G_SHUFFLE_VECTOR\0"
5027 /* 14158 */ "G_SPLAT_VECTOR\0"
5028 /* 14173 */ "G_VECREDUCE_XOR\0"
5029 /* 14189 */ "G_XOR\0"
5030 /* 14195 */ "G_ATOMICRMW_XOR\0"
5031 /* 14211 */ "G_VECREDUCE_OR\0"
5032 /* 14226 */ "G_OR\0"
5033 /* 14231 */ "G_ATOMICRMW_OR\0"
5034 /* 14246 */ "G_ROTR\0"
5035 /* 14253 */ "G_INTTOPTR\0"
5036 /* 14264 */ "G_FABS\0"
5037 /* 14271 */ "G_ABS\0"
5038 /* 14277 */ "G_UNMERGE_VALUES\0"
5039 /* 14294 */ "G_MERGE_VALUES\0"
5040 /* 14309 */ "CALL_PARAMS\0"
5041 /* 14321 */ "G_FACOS\0"
5042 /* 14329 */ "G_FCOS\0"
5043 /* 14336 */ "G_CONCAT_VECTORS\0"
5044 /* 14353 */ "COPY_TO_REGCLASS\0"
5045 /* 14370 */ "G_IS_FPCLASS\0"
5046 /* 14383 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
5047 /* 14413 */ "BR_UNLESS\0"
5048 /* 14423 */ "G_VECTOR_COMPRESS\0"
5049 /* 14441 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
5050 /* 14468 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
5051 /* 14506 */ "RET_CALL_RESULTS\0"
5052 /* 14523 */ "LOAD_F16_F32_A32_S\0"
5053 /* 14542 */ "STORE_F16_F32_A32_S\0"
5054 /* 14562 */ "LOAD_F32_A32_S\0"
5055 /* 14577 */ "STORE_F32_A32_S\0"
5056 /* 14593 */ "ATOMIC_STORE16_I32_A32_S\0"
5057 /* 14618 */ "ATOMIC_STORE8_I32_A32_S\0"
5058 /* 14642 */ "ATOMIC_RMW16_U_SUB_I32_A32_S\0"
5059 /* 14671 */ "ATOMIC_RMW8_U_SUB_I32_A32_S\0"
5060 /* 14699 */ "ATOMIC_RMW_SUB_I32_A32_S\0"
5061 /* 14724 */ "ATOMIC_LOAD_I32_A32_S\0"
5062 /* 14746 */ "ATOMIC_RMW16_U_ADD_I32_A32_S\0"
5063 /* 14775 */ "ATOMIC_RMW8_U_ADD_I32_A32_S\0"
5064 /* 14803 */ "ATOMIC_RMW_ADD_I32_A32_S\0"
5065 /* 14828 */ "ATOMIC_RMW16_U_AND_I32_A32_S\0"
5066 /* 14857 */ "ATOMIC_RMW8_U_AND_I32_A32_S\0"
5067 /* 14885 */ "ATOMIC_RMW_AND_I32_A32_S\0"
5068 /* 14910 */ "ATOMIC_STORE_I32_A32_S\0"
5069 /* 14933 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A32_S\0"
5070 /* 14966 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A32_S\0"
5071 /* 14998 */ "ATOMIC_RMW_CMPXCHG_I32_A32_S\0"
5072 /* 15027 */ "ATOMIC_RMW16_U_XCHG_I32_A32_S\0"
5073 /* 15057 */ "ATOMIC_RMW8_U_XCHG_I32_A32_S\0"
5074 /* 15086 */ "ATOMIC_RMW_XCHG_I32_A32_S\0"
5075 /* 15112 */ "ATOMIC_RMW16_U_XOR_I32_A32_S\0"
5076 /* 15141 */ "ATOMIC_RMW8_U_XOR_I32_A32_S\0"
5077 /* 15169 */ "ATOMIC_RMW_XOR_I32_A32_S\0"
5078 /* 15194 */ "ATOMIC_RMW16_U_OR_I32_A32_S\0"
5079 /* 15222 */ "ATOMIC_RMW8_U_OR_I32_A32_S\0"
5080 /* 15249 */ "ATOMIC_RMW_OR_I32_A32_S\0"
5081 /* 15273 */ "LOAD16_S_I32_A32_S\0"
5082 /* 15292 */ "LOAD8_S_I32_A32_S\0"
5083 /* 15310 */ "ATOMIC_LOAD16_U_I32_A32_S\0"
5084 /* 15336 */ "ATOMIC_LOAD8_U_I32_A32_S\0"
5085 /* 15361 */ "MEMORY_ATOMIC_WAIT32_A32_S\0"
5086 /* 15388 */ "LOAD_LANE_I64x2_A32_S\0"
5087 /* 15410 */ "STORE_LANE_I64x2_A32_S\0"
5088 /* 15433 */ "LOAD_ZERO_I64x2_A32_S\0"
5089 /* 15455 */ "LOAD_EXTEND_S_I64x2_A32_S\0"
5090 /* 15481 */ "LOAD_EXTEND_U_I64x2_A32_S\0"
5091 /* 15507 */ "LOAD_F64_A32_S\0"
5092 /* 15522 */ "STORE_F64_A32_S\0"
5093 /* 15538 */ "ATOMIC_STORE32_I64_A32_S\0"
5094 /* 15563 */ "ATOMIC_STORE16_I64_A32_S\0"
5095 /* 15588 */ "ATOMIC_STORE8_I64_A32_S\0"
5096 /* 15612 */ "ATOMIC_RMW32_U_SUB_I64_A32_S\0"
5097 /* 15641 */ "ATOMIC_RMW16_U_SUB_I64_A32_S\0"
5098 /* 15670 */ "ATOMIC_RMW8_U_SUB_I64_A32_S\0"
5099 /* 15698 */ "ATOMIC_RMW_SUB_I64_A32_S\0"
5100 /* 15723 */ "ATOMIC_LOAD_I64_A32_S\0"
5101 /* 15745 */ "ATOMIC_RMW32_U_ADD_I64_A32_S\0"
5102 /* 15774 */ "ATOMIC_RMW16_U_ADD_I64_A32_S\0"
5103 /* 15803 */ "ATOMIC_RMW8_U_ADD_I64_A32_S\0"
5104 /* 15831 */ "ATOMIC_RMW_ADD_I64_A32_S\0"
5105 /* 15856 */ "ATOMIC_RMW32_U_AND_I64_A32_S\0"
5106 /* 15885 */ "ATOMIC_RMW16_U_AND_I64_A32_S\0"
5107 /* 15914 */ "ATOMIC_RMW8_U_AND_I64_A32_S\0"
5108 /* 15942 */ "ATOMIC_RMW_AND_I64_A32_S\0"
5109 /* 15967 */ "ATOMIC_STORE_I64_A32_S\0"
5110 /* 15990 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A32_S\0"
5111 /* 16023 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A32_S\0"
5112 /* 16056 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A32_S\0"
5113 /* 16088 */ "ATOMIC_RMW_CMPXCHG_I64_A32_S\0"
5114 /* 16117 */ "ATOMIC_RMW32_U_XCHG_I64_A32_S\0"
5115 /* 16147 */ "ATOMIC_RMW16_U_XCHG_I64_A32_S\0"
5116 /* 16177 */ "ATOMIC_RMW8_U_XCHG_I64_A32_S\0"
5117 /* 16206 */ "ATOMIC_RMW_XCHG_I64_A32_S\0"
5118 /* 16232 */ "ATOMIC_RMW32_U_XOR_I64_A32_S\0"
5119 /* 16261 */ "ATOMIC_RMW16_U_XOR_I64_A32_S\0"
5120 /* 16290 */ "ATOMIC_RMW8_U_XOR_I64_A32_S\0"
5121 /* 16318 */ "ATOMIC_RMW_XOR_I64_A32_S\0"
5122 /* 16343 */ "ATOMIC_RMW32_U_OR_I64_A32_S\0"
5123 /* 16371 */ "ATOMIC_RMW16_U_OR_I64_A32_S\0"
5124 /* 16399 */ "ATOMIC_RMW8_U_OR_I64_A32_S\0"
5125 /* 16426 */ "ATOMIC_RMW_OR_I64_A32_S\0"
5126 /* 16450 */ "LOAD32_S_I64_A32_S\0"
5127 /* 16469 */ "LOAD16_S_I64_A32_S\0"
5128 /* 16488 */ "LOAD8_S_I64_A32_S\0"
5129 /* 16506 */ "ATOMIC_LOAD32_U_I64_A32_S\0"
5130 /* 16532 */ "ATOMIC_LOAD16_U_I64_A32_S\0"
5131 /* 16558 */ "ATOMIC_LOAD8_U_I64_A32_S\0"
5132 /* 16583 */ "MEMORY_ATOMIC_WAIT64_A32_S\0"
5133 /* 16610 */ "LOAD_LANE_I32x4_A32_S\0"
5134 /* 16632 */ "STORE_LANE_I32x4_A32_S\0"
5135 /* 16655 */ "LOAD_ZERO_I32x4_A32_S\0"
5136 /* 16677 */ "LOAD_EXTEND_S_I32x4_A32_S\0"
5137 /* 16703 */ "LOAD_EXTEND_U_I32x4_A32_S\0"
5138 /* 16729 */ "LOAD_LANE_I8x16_A32_S\0"
5139 /* 16751 */ "STORE_LANE_I8x16_A32_S\0"
5140 /* 16774 */ "LOAD_V128_A32_S\0"
5141 /* 16790 */ "STORE_V128_A32_S\0"
5142 /* 16807 */ "LOAD_LANE_I16x8_A32_S\0"
5143 /* 16829 */ "STORE_LANE_I16x8_A32_S\0"
5144 /* 16852 */ "LOAD_EXTEND_S_I16x8_A32_S\0"
5145 /* 16878 */ "LOAD_EXTEND_U_I16x8_A32_S\0"
5146 /* 16904 */ "anonymous_8187MEMORY_SIZE_A32_S\0"
5147 /* 16936 */ "anonymous_8878MEMORY_FILL_A32_S\0"
5148 /* 16968 */ "LOAD32_SPLAT_A32_S\0"
5149 /* 16987 */ "LOAD64_SPLAT_A32_S\0"
5150 /* 17006 */ "LOAD16_SPLAT_A32_S\0"
5151 /* 17025 */ "LOAD8_SPLAT_A32_S\0"
5152 /* 17043 */ "anonymous_8878MEMORY_INIT_A32_S\0"
5153 /* 17075 */ "anonymous_8187MEMORY_GROW_A32_S\0"
5154 /* 17107 */ "MEMORY_ATOMIC_NOTIFY_A32_S\0"
5155 /* 17134 */ "anonymous_8878MEMORY_COPY_A32_S\0"
5156 /* 17166 */ "FP_TO_SINT_I32_F32_S\0"
5157 /* 17187 */ "FP_TO_UINT_I32_F32_S\0"
5158 /* 17208 */ "FP_TO_SINT_I64_F32_S\0"
5159 /* 17229 */ "FP_TO_UINT_I64_F32_S\0"
5160 /* 17250 */ "SUB_F32_S\0"
5161 /* 17260 */ "TRUNC_F32_S\0"
5162 /* 17272 */ "ADD_F32_S\0"
5163 /* 17282 */ "LOCAL_TEE_F32_S\0"
5164 /* 17298 */ "GE_F32_S\0"
5165 /* 17307 */ "LE_F32_S\0"
5166 /* 17316 */ "NE_F32_S\0"
5167 /* 17325 */ "F64_PROMOTE_F32_S\0"
5168 /* 17343 */ "NEG_F32_S\0"
5169 /* 17353 */ "CEIL_F32_S\0"
5170 /* 17364 */ "MUL_F32_S\0"
5171 /* 17374 */ "COPYSIGN_F32_S\0"
5172 /* 17389 */ "MIN_F32_S\0"
5173 /* 17399 */ "DROP_F32_S\0"
5174 /* 17410 */ "EQ_F32_S\0"
5175 /* 17419 */ "FLOOR_F32_S\0"
5176 /* 17431 */ "ABS_F32_S\0"
5177 /* 17441 */ "I32_TRUNC_S_F32_S\0"
5178 /* 17459 */ "I64_TRUNC_S_F32_S\0"
5179 /* 17477 */ "I32_TRUNC_S_SAT_F32_S\0"
5180 /* 17499 */ "I64_TRUNC_S_SAT_F32_S\0"
5181 /* 17521 */ "I32_TRUNC_U_SAT_F32_S\0"
5182 /* 17543 */ "I64_TRUNC_U_SAT_F32_S\0"
5183 /* 17565 */ "SELECT_F32_S\0"
5184 /* 17578 */ "GLOBAL_GET_F32_S\0"
5185 /* 17595 */ "LOCAL_GET_F32_S\0"
5186 /* 17611 */ "I32_REINTERPRET_F32_S\0"
5187 /* 17633 */ "GLOBAL_SET_F32_S\0"
5188 /* 17650 */ "LOCAL_SET_F32_S\0"
5189 /* 17666 */ "GT_F32_S\0"
5190 /* 17675 */ "LT_F32_S\0"
5191 /* 17684 */ "SQRT_F32_S\0"
5192 /* 17695 */ "NEAREST_F32_S\0"
5193 /* 17709 */ "CONST_F32_S\0"
5194 /* 17721 */ "I32_TRUNC_U_F32_S\0"
5195 /* 17739 */ "I64_TRUNC_U_F32_S\0"
5196 /* 17757 */ "DIV_F32_S\0"
5197 /* 17767 */ "MAX_F32_S\0"
5198 /* 17777 */ "COPY_F32_S\0"
5199 /* 17788 */ "SUB_I32_S\0"
5200 /* 17798 */ "ADD_I32_S\0"
5201 /* 17808 */ "AND_I32_S\0"
5202 /* 17818 */ "LOCAL_TEE_I32_S\0"
5203 /* 17834 */ "BR_TABLE_I32_S\0"
5204 /* 17849 */ "NE_I32_S\0"
5205 /* 17858 */ "SHL_I32_S\0"
5206 /* 17868 */ "ROTL_I32_S\0"
5207 /* 17879 */ "MUL_I32_S\0"
5208 /* 17889 */ "DROP_I32_S\0"
5209 /* 17900 */ "EQ_I32_S\0"
5210 /* 17909 */ "XOR_I32_S\0"
5211 /* 17919 */ "ROTR_I32_S\0"
5212 /* 17930 */ "I32_EXTEND16_S_I32_S\0"
5213 /* 17951 */ "I32_EXTEND8_S_I32_S\0"
5214 /* 17971 */ "I64_EXTEND_S_I32_S\0"
5215 /* 17990 */ "GE_S_I32_S\0"
5216 /* 18001 */ "LE_S_I32_S\0"
5217 /* 18012 */ "REM_S_I32_S\0"
5218 /* 18024 */ "SHR_S_I32_S\0"
5219 /* 18036 */ "GT_S_I32_S\0"
5220 /* 18047 */ "LT_S_I32_S\0"
5221 /* 18058 */ "F32_CONVERT_S_I32_S\0"
5222 /* 18078 */ "F64_CONVERT_S_I32_S\0"
5223 /* 18098 */ "DIV_S_I32_S\0"
5224 /* 18110 */ "SELECT_I32_S\0"
5225 /* 18123 */ "GLOBAL_GET_I32_S\0"
5226 /* 18140 */ "LOCAL_GET_I32_S\0"
5227 /* 18156 */ "F32_REINTERPRET_I32_S\0"
5228 /* 18178 */ "GLOBAL_SET_I32_S\0"
5229 /* 18195 */ "LOCAL_SET_I32_S\0"
5230 /* 18211 */ "POPCNT_I32_S\0"
5231 /* 18224 */ "CONST_I32_S\0"
5232 /* 18236 */ "I64_EXTEND_U_I32_S\0"
5233 /* 18255 */ "GE_U_I32_S\0"
5234 /* 18266 */ "LE_U_I32_S\0"
5235 /* 18277 */ "REM_U_I32_S\0"
5236 /* 18289 */ "SHR_U_I32_S\0"
5237 /* 18301 */ "GT_U_I32_S\0"
5238 /* 18312 */ "LT_U_I32_S\0"
5239 /* 18323 */ "F32_CONVERT_U_I32_S\0"
5240 /* 18343 */ "F64_CONVERT_U_I32_S\0"
5241 /* 18363 */ "DIV_U_I32_S\0"
5242 /* 18375 */ "COPY_I32_S\0"
5243 /* 18386 */ "CLZ_I32_S\0"
5244 /* 18396 */ "EQZ_I32_S\0"
5245 /* 18406 */ "CTZ_I32_S\0"
5246 /* 18416 */ "ARGUMENT_v4f32_S\0"
5247 /* 18433 */ "ARGUMENT_f32_S\0"
5248 /* 18448 */ "ARGUMENT_v4i32_S\0"
5249 /* 18465 */ "ARGUMENT_i32_S\0"
5250 /* 18480 */ "CONST_V128_F64x2_S\0"
5251 /* 18499 */ "SUB_F64x2_S\0"
5252 /* 18511 */ "TRUNC_F64x2_S\0"
5253 /* 18525 */ "NMADD_F64x2_S\0"
5254 /* 18539 */ "GE_F64x2_S\0"
5255 /* 18550 */ "LE_F64x2_S\0"
5256 /* 18561 */ "REPLACE_LANE_F64x2_S\0"
5257 /* 18582 */ "EXTRACT_LANE_F64x2_S\0"
5258 /* 18603 */ "NEG_F64x2_S\0"
5259 /* 18615 */ "CEIL_F64x2_S\0"
5260 /* 18628 */ "MUL_F64x2_S\0"
5261 /* 18640 */ "SIMD_RELAXED_FMIN_F64x2_S\0"
5262 /* 18666 */ "PMIN_F64x2_S\0"
5263 /* 18679 */ "EQ_F64x2_S\0"
5264 /* 18690 */ "FLOOR_F64x2_S\0"
5265 /* 18704 */ "ABS_F64x2_S\0"
5266 /* 18716 */ "SPLAT_F64x2_S\0"
5267 /* 18730 */ "GT_F64x2_S\0"
5268 /* 18741 */ "LT_F64x2_S\0"
5269 /* 18752 */ "SQRT_F64x2_S\0"
5270 /* 18765 */ "NEAREST_F64x2_S\0"
5271 /* 18781 */ "DIV_F64x2_S\0"
5272 /* 18793 */ "SIMD_RELAXED_FMAX_F64x2_S\0"
5273 /* 18819 */ "PMAX_F64x2_S\0"
5274 /* 18832 */ "convert_low_s_F64x2_S\0"
5275 /* 18854 */ "convert_low_u_F64x2_S\0"
5276 /* 18876 */ "promote_low_F64x2_S\0"
5277 /* 18896 */ "CONST_V128_I64x2_S\0"
5278 /* 18915 */ "SUB_I64x2_S\0"
5279 /* 18927 */ "ADD_I64x2_S\0"
5280 /* 18939 */ "REPLACE_LANE_I64x2_S\0"
5281 /* 18960 */ "EXTRACT_LANE_I64x2_S\0"
5282 /* 18981 */ "ALLTRUE_I64x2_S\0"
5283 /* 18997 */ "NEG_I64x2_S\0"
5284 /* 19009 */ "BITMASK_I64x2_S\0"
5285 /* 19025 */ "SHL_I64x2_S\0"
5286 /* 19037 */ "MUL_I64x2_S\0"
5287 /* 19049 */ "EQ_I64x2_S\0"
5288 /* 19060 */ "ABS_I64x2_S\0"
5289 /* 19072 */ "GE_S_I64x2_S\0"
5290 /* 19085 */ "LE_S_I64x2_S\0"
5291 /* 19098 */ "EXTMUL_HIGH_S_I64x2_S\0"
5292 /* 19120 */ "SHR_S_I64x2_S\0"
5293 /* 19134 */ "GT_S_I64x2_S\0"
5294 /* 19147 */ "LT_S_I64x2_S\0"
5295 /* 19160 */ "EXTMUL_LOW_S_I64x2_S\0"
5296 /* 19181 */ "SPLAT_I64x2_S\0"
5297 /* 19195 */ "LANESELECT_I64x2_S\0"
5298 /* 19214 */ "EXTMUL_HIGH_U_I64x2_S\0"
5299 /* 19236 */ "SHR_U_I64x2_S\0"
5300 /* 19250 */ "EXTMUL_LOW_U_I64x2_S\0"
5301 /* 19271 */ "extend_high_s_I64x2_S\0"
5302 /* 19293 */ "extend_low_s_I64x2_S\0"
5303 /* 19314 */ "extend_high_u_I64x2_S\0"
5304 /* 19336 */ "extend_low_u_I64x2_S\0"
5305 /* 19357 */ "LOAD_F16_F32_A64_S\0"
5306 /* 19376 */ "STORE_F16_F32_A64_S\0"
5307 /* 19396 */ "LOAD_F32_A64_S\0"
5308 /* 19411 */ "STORE_F32_A64_S\0"
5309 /* 19427 */ "ATOMIC_STORE16_I32_A64_S\0"
5310 /* 19452 */ "ATOMIC_STORE8_I32_A64_S\0"
5311 /* 19476 */ "ATOMIC_RMW16_U_SUB_I32_A64_S\0"
5312 /* 19505 */ "ATOMIC_RMW8_U_SUB_I32_A64_S\0"
5313 /* 19533 */ "ATOMIC_RMW_SUB_I32_A64_S\0"
5314 /* 19558 */ "ATOMIC_LOAD_I32_A64_S\0"
5315 /* 19580 */ "ATOMIC_RMW16_U_ADD_I32_A64_S\0"
5316 /* 19609 */ "ATOMIC_RMW8_U_ADD_I32_A64_S\0"
5317 /* 19637 */ "ATOMIC_RMW_ADD_I32_A64_S\0"
5318 /* 19662 */ "ATOMIC_RMW16_U_AND_I32_A64_S\0"
5319 /* 19691 */ "ATOMIC_RMW8_U_AND_I32_A64_S\0"
5320 /* 19719 */ "ATOMIC_RMW_AND_I32_A64_S\0"
5321 /* 19744 */ "ATOMIC_STORE_I32_A64_S\0"
5322 /* 19767 */ "ATOMIC_RMW16_U_CMPXCHG_I32_A64_S\0"
5323 /* 19800 */ "ATOMIC_RMW8_U_CMPXCHG_I32_A64_S\0"
5324 /* 19832 */ "ATOMIC_RMW_CMPXCHG_I32_A64_S\0"
5325 /* 19861 */ "ATOMIC_RMW16_U_XCHG_I32_A64_S\0"
5326 /* 19891 */ "ATOMIC_RMW8_U_XCHG_I32_A64_S\0"
5327 /* 19920 */ "ATOMIC_RMW_XCHG_I32_A64_S\0"
5328 /* 19946 */ "ATOMIC_RMW16_U_XOR_I32_A64_S\0"
5329 /* 19975 */ "ATOMIC_RMW8_U_XOR_I32_A64_S\0"
5330 /* 20003 */ "ATOMIC_RMW_XOR_I32_A64_S\0"
5331 /* 20028 */ "ATOMIC_RMW16_U_OR_I32_A64_S\0"
5332 /* 20056 */ "ATOMIC_RMW8_U_OR_I32_A64_S\0"
5333 /* 20083 */ "ATOMIC_RMW_OR_I32_A64_S\0"
5334 /* 20107 */ "LOAD16_S_I32_A64_S\0"
5335 /* 20126 */ "LOAD8_S_I32_A64_S\0"
5336 /* 20144 */ "ATOMIC_LOAD16_U_I32_A64_S\0"
5337 /* 20170 */ "ATOMIC_LOAD8_U_I32_A64_S\0"
5338 /* 20195 */ "MEMORY_ATOMIC_WAIT32_A64_S\0"
5339 /* 20222 */ "LOAD_LANE_I64x2_A64_S\0"
5340 /* 20244 */ "STORE_LANE_I64x2_A64_S\0"
5341 /* 20267 */ "LOAD_ZERO_I64x2_A64_S\0"
5342 /* 20289 */ "LOAD_EXTEND_S_I64x2_A64_S\0"
5343 /* 20315 */ "LOAD_EXTEND_U_I64x2_A64_S\0"
5344 /* 20341 */ "LOAD_F64_A64_S\0"
5345 /* 20356 */ "STORE_F64_A64_S\0"
5346 /* 20372 */ "ATOMIC_STORE32_I64_A64_S\0"
5347 /* 20397 */ "ATOMIC_STORE16_I64_A64_S\0"
5348 /* 20422 */ "ATOMIC_STORE8_I64_A64_S\0"
5349 /* 20446 */ "ATOMIC_RMW32_U_SUB_I64_A64_S\0"
5350 /* 20475 */ "ATOMIC_RMW16_U_SUB_I64_A64_S\0"
5351 /* 20504 */ "ATOMIC_RMW8_U_SUB_I64_A64_S\0"
5352 /* 20532 */ "ATOMIC_RMW_SUB_I64_A64_S\0"
5353 /* 20557 */ "ATOMIC_LOAD_I64_A64_S\0"
5354 /* 20579 */ "ATOMIC_RMW32_U_ADD_I64_A64_S\0"
5355 /* 20608 */ "ATOMIC_RMW16_U_ADD_I64_A64_S\0"
5356 /* 20637 */ "ATOMIC_RMW8_U_ADD_I64_A64_S\0"
5357 /* 20665 */ "ATOMIC_RMW_ADD_I64_A64_S\0"
5358 /* 20690 */ "ATOMIC_RMW32_U_AND_I64_A64_S\0"
5359 /* 20719 */ "ATOMIC_RMW16_U_AND_I64_A64_S\0"
5360 /* 20748 */ "ATOMIC_RMW8_U_AND_I64_A64_S\0"
5361 /* 20776 */ "ATOMIC_RMW_AND_I64_A64_S\0"
5362 /* 20801 */ "ATOMIC_STORE_I64_A64_S\0"
5363 /* 20824 */ "ATOMIC_RMW32_U_CMPXCHG_I64_A64_S\0"
5364 /* 20857 */ "ATOMIC_RMW16_U_CMPXCHG_I64_A64_S\0"
5365 /* 20890 */ "ATOMIC_RMW8_U_CMPXCHG_I64_A64_S\0"
5366 /* 20922 */ "ATOMIC_RMW_CMPXCHG_I64_A64_S\0"
5367 /* 20951 */ "ATOMIC_RMW32_U_XCHG_I64_A64_S\0"
5368 /* 20981 */ "ATOMIC_RMW16_U_XCHG_I64_A64_S\0"
5369 /* 21011 */ "ATOMIC_RMW8_U_XCHG_I64_A64_S\0"
5370 /* 21040 */ "ATOMIC_RMW_XCHG_I64_A64_S\0"
5371 /* 21066 */ "ATOMIC_RMW32_U_XOR_I64_A64_S\0"
5372 /* 21095 */ "ATOMIC_RMW16_U_XOR_I64_A64_S\0"
5373 /* 21124 */ "ATOMIC_RMW8_U_XOR_I64_A64_S\0"
5374 /* 21152 */ "ATOMIC_RMW_XOR_I64_A64_S\0"
5375 /* 21177 */ "ATOMIC_RMW32_U_OR_I64_A64_S\0"
5376 /* 21205 */ "ATOMIC_RMW16_U_OR_I64_A64_S\0"
5377 /* 21233 */ "ATOMIC_RMW8_U_OR_I64_A64_S\0"
5378 /* 21260 */ "ATOMIC_RMW_OR_I64_A64_S\0"
5379 /* 21284 */ "LOAD32_S_I64_A64_S\0"
5380 /* 21303 */ "LOAD16_S_I64_A64_S\0"
5381 /* 21322 */ "LOAD8_S_I64_A64_S\0"
5382 /* 21340 */ "ATOMIC_LOAD32_U_I64_A64_S\0"
5383 /* 21366 */ "ATOMIC_LOAD16_U_I64_A64_S\0"
5384 /* 21392 */ "ATOMIC_LOAD8_U_I64_A64_S\0"
5385 /* 21417 */ "MEMORY_ATOMIC_WAIT64_A64_S\0"
5386 /* 21444 */ "LOAD_LANE_I32x4_A64_S\0"
5387 /* 21466 */ "STORE_LANE_I32x4_A64_S\0"
5388 /* 21489 */ "LOAD_ZERO_I32x4_A64_S\0"
5389 /* 21511 */ "LOAD_EXTEND_S_I32x4_A64_S\0"
5390 /* 21537 */ "LOAD_EXTEND_U_I32x4_A64_S\0"
5391 /* 21563 */ "LOAD_LANE_I8x16_A64_S\0"
5392 /* 21585 */ "STORE_LANE_I8x16_A64_S\0"
5393 /* 21608 */ "LOAD_V128_A64_S\0"
5394 /* 21624 */ "STORE_V128_A64_S\0"
5395 /* 21641 */ "LOAD_LANE_I16x8_A64_S\0"
5396 /* 21663 */ "STORE_LANE_I16x8_A64_S\0"
5397 /* 21686 */ "LOAD_EXTEND_S_I16x8_A64_S\0"
5398 /* 21712 */ "LOAD_EXTEND_U_I16x8_A64_S\0"
5399 /* 21738 */ "anonymous_8188MEMORY_SIZE_A64_S\0"
5400 /* 21770 */ "anonymous_8879MEMORY_FILL_A64_S\0"
5401 /* 21802 */ "LOAD32_SPLAT_A64_S\0"
5402 /* 21821 */ "LOAD64_SPLAT_A64_S\0"
5403 /* 21840 */ "LOAD16_SPLAT_A64_S\0"
5404 /* 21859 */ "LOAD8_SPLAT_A64_S\0"
5405 /* 21877 */ "anonymous_8879MEMORY_INIT_A64_S\0"
5406 /* 21909 */ "anonymous_8188MEMORY_GROW_A64_S\0"
5407 /* 21941 */ "MEMORY_ATOMIC_NOTIFY_A64_S\0"
5408 /* 21968 */ "anonymous_8879MEMORY_COPY_A64_S\0"
5409 /* 22000 */ "FP_TO_SINT_I32_F64_S\0"
5410 /* 22021 */ "FP_TO_UINT_I32_F64_S\0"
5411 /* 22042 */ "FP_TO_SINT_I64_F64_S\0"
5412 /* 22063 */ "FP_TO_UINT_I64_F64_S\0"
5413 /* 22084 */ "SUB_F64_S\0"
5414 /* 22094 */ "TRUNC_F64_S\0"
5415 /* 22106 */ "ADD_F64_S\0"
5416 /* 22116 */ "LOCAL_TEE_F64_S\0"
5417 /* 22132 */ "GE_F64_S\0"
5418 /* 22141 */ "LE_F64_S\0"
5419 /* 22150 */ "NE_F64_S\0"
5420 /* 22159 */ "F32_DEMOTE_F64_S\0"
5421 /* 22176 */ "NEG_F64_S\0"
5422 /* 22186 */ "CEIL_F64_S\0"
5423 /* 22197 */ "MUL_F64_S\0"
5424 /* 22207 */ "COPYSIGN_F64_S\0"
5425 /* 22222 */ "MIN_F64_S\0"
5426 /* 22232 */ "DROP_F64_S\0"
5427 /* 22243 */ "EQ_F64_S\0"
5428 /* 22252 */ "FLOOR_F64_S\0"
5429 /* 22264 */ "ABS_F64_S\0"
5430 /* 22274 */ "I32_TRUNC_S_F64_S\0"
5431 /* 22292 */ "I64_TRUNC_S_F64_S\0"
5432 /* 22310 */ "I32_TRUNC_S_SAT_F64_S\0"
5433 /* 22332 */ "I64_TRUNC_S_SAT_F64_S\0"
5434 /* 22354 */ "I32_TRUNC_U_SAT_F64_S\0"
5435 /* 22376 */ "I64_TRUNC_U_SAT_F64_S\0"
5436 /* 22398 */ "SELECT_F64_S\0"
5437 /* 22411 */ "GLOBAL_GET_F64_S\0"
5438 /* 22428 */ "LOCAL_GET_F64_S\0"
5439 /* 22444 */ "I64_REINTERPRET_F64_S\0"
5440 /* 22466 */ "GLOBAL_SET_F64_S\0"
5441 /* 22483 */ "LOCAL_SET_F64_S\0"
5442 /* 22499 */ "GT_F64_S\0"
5443 /* 22508 */ "LT_F64_S\0"
5444 /* 22517 */ "SQRT_F64_S\0"
5445 /* 22528 */ "NEAREST_F64_S\0"
5446 /* 22542 */ "CONST_F64_S\0"
5447 /* 22554 */ "I32_TRUNC_U_F64_S\0"
5448 /* 22572 */ "I64_TRUNC_U_F64_S\0"
5449 /* 22590 */ "DIV_F64_S\0"
5450 /* 22600 */ "MAX_F64_S\0"
5451 /* 22610 */ "COPY_F64_S\0"
5452 /* 22621 */ "SUB_I64_S\0"
5453 /* 22631 */ "ADD_I64_S\0"
5454 /* 22641 */ "AND_I64_S\0"
5455 /* 22651 */ "LOCAL_TEE_I64_S\0"
5456 /* 22667 */ "BR_TABLE_I64_S\0"
5457 /* 22682 */ "NE_I64_S\0"
5458 /* 22691 */ "SHL_I64_S\0"
5459 /* 22701 */ "ROTL_I64_S\0"
5460 /* 22712 */ "MUL_I64_S\0"
5461 /* 22722 */ "I32_WRAP_I64_S\0"
5462 /* 22737 */ "DROP_I64_S\0"
5463 /* 22748 */ "EQ_I64_S\0"
5464 /* 22757 */ "XOR_I64_S\0"
5465 /* 22767 */ "ROTR_I64_S\0"
5466 /* 22778 */ "I64_EXTEND32_S_I64_S\0"
5467 /* 22799 */ "I64_EXTEND16_S_I64_S\0"
5468 /* 22820 */ "I64_EXTEND8_S_I64_S\0"
5469 /* 22840 */ "GE_S_I64_S\0"
5470 /* 22851 */ "LE_S_I64_S\0"
5471 /* 22862 */ "REM_S_I64_S\0"
5472 /* 22874 */ "SHR_S_I64_S\0"
5473 /* 22886 */ "GT_S_I64_S\0"
5474 /* 22897 */ "LT_S_I64_S\0"
5475 /* 22908 */ "F32_CONVERT_S_I64_S\0"
5476 /* 22928 */ "F64_CONVERT_S_I64_S\0"
5477 /* 22948 */ "DIV_S_I64_S\0"
5478 /* 22960 */ "SELECT_I64_S\0"
5479 /* 22973 */ "GLOBAL_GET_I64_S\0"
5480 /* 22990 */ "LOCAL_GET_I64_S\0"
5481 /* 23006 */ "F64_REINTERPRET_I64_S\0"
5482 /* 23028 */ "GLOBAL_SET_I64_S\0"
5483 /* 23045 */ "LOCAL_SET_I64_S\0"
5484 /* 23061 */ "POPCNT_I64_S\0"
5485 /* 23074 */ "CONST_I64_S\0"
5486 /* 23086 */ "GE_U_I64_S\0"
5487 /* 23097 */ "LE_U_I64_S\0"
5488 /* 23108 */ "REM_U_I64_S\0"
5489 /* 23120 */ "SHR_U_I64_S\0"
5490 /* 23132 */ "GT_U_I64_S\0"
5491 /* 23143 */ "LT_U_I64_S\0"
5492 /* 23154 */ "F32_CONVERT_U_I64_S\0"
5493 /* 23174 */ "F64_CONVERT_U_I64_S\0"
5494 /* 23194 */ "DIV_U_I64_S\0"
5495 /* 23206 */ "COPY_I64_S\0"
5496 /* 23217 */ "CLZ_I64_S\0"
5497 /* 23227 */ "EQZ_I64_S\0"
5498 /* 23237 */ "CTZ_I64_S\0"
5499 /* 23247 */ "ARGUMENT_v2f64_S\0"
5500 /* 23264 */ "ARGUMENT_f64_S\0"
5501 /* 23279 */ "ARGUMENT_v2i64_S\0"
5502 /* 23296 */ "ARGUMENT_i64_S\0"
5503 /* 23311 */ "CONST_V128_F32x4_S\0"
5504 /* 23330 */ "SUB_F32x4_S\0"
5505 /* 23342 */ "TRUNC_F32x4_S\0"
5506 /* 23356 */ "NMADD_F32x4_S\0"
5507 /* 23370 */ "GE_F32x4_S\0"
5508 /* 23381 */ "LE_F32x4_S\0"
5509 /* 23392 */ "REPLACE_LANE_F32x4_S\0"
5510 /* 23413 */ "EXTRACT_LANE_F32x4_S\0"
5511 /* 23434 */ "NEG_F32x4_S\0"
5512 /* 23446 */ "CEIL_F32x4_S\0"
5513 /* 23459 */ "MUL_F32x4_S\0"
5514 /* 23471 */ "SIMD_RELAXED_FMIN_F32x4_S\0"
5515 /* 23497 */ "PMIN_F32x4_S\0"
5516 /* 23510 */ "EQ_F32x4_S\0"
5517 /* 23521 */ "FLOOR_F32x4_S\0"
5518 /* 23535 */ "ABS_F32x4_S\0"
5519 /* 23547 */ "SPLAT_F32x4_S\0"
5520 /* 23561 */ "GT_F32x4_S\0"
5521 /* 23572 */ "LT_F32x4_S\0"
5522 /* 23583 */ "SQRT_F32x4_S\0"
5523 /* 23596 */ "NEAREST_F32x4_S\0"
5524 /* 23612 */ "DIV_F32x4_S\0"
5525 /* 23624 */ "SIMD_RELAXED_FMAX_F32x4_S\0"
5526 /* 23650 */ "PMAX_F32x4_S\0"
5527 /* 23663 */ "demote_zero_F32x4_S\0"
5528 /* 23683 */ "sint_to_fp_F32x4_S\0"
5529 /* 23702 */ "uint_to_fp_F32x4_S\0"
5530 /* 23721 */ "CONST_V128_I32x4_S\0"
5531 /* 23740 */ "SUB_I32x4_S\0"
5532 /* 23752 */ "ADD_I32x4_S\0"
5533 /* 23764 */ "REPLACE_LANE_I32x4_S\0"
5534 /* 23785 */ "EXTRACT_LANE_I32x4_S\0"
5535 /* 23806 */ "ALLTRUE_I32x4_S\0"
5536 /* 23822 */ "NEG_I32x4_S\0"
5537 /* 23834 */ "BITMASK_I32x4_S\0"
5538 /* 23850 */ "SHL_I32x4_S\0"
5539 /* 23862 */ "MUL_I32x4_S\0"
5540 /* 23874 */ "EQ_I32x4_S\0"
5541 /* 23885 */ "ABS_I32x4_S\0"
5542 /* 23897 */ "GE_S_I32x4_S\0"
5543 /* 23910 */ "LE_S_I32x4_S\0"
5544 /* 23923 */ "EXTMUL_HIGH_S_I32x4_S\0"
5545 /* 23945 */ "MIN_S_I32x4_S\0"
5546 /* 23959 */ "SHR_S_I32x4_S\0"
5547 /* 23973 */ "GT_S_I32x4_S\0"
5548 /* 23986 */ "LT_S_I32x4_S\0"
5549 /* 23999 */ "EXTMUL_LOW_S_I32x4_S\0"
5550 /* 24020 */ "MAX_S_I32x4_S\0"
5551 /* 24034 */ "SPLAT_I32x4_S\0"
5552 /* 24048 */ "LANESELECT_I32x4_S\0"
5553 /* 24067 */ "GE_U_I32x4_S\0"
5554 /* 24080 */ "LE_U_I32x4_S\0"
5555 /* 24093 */ "EXTMUL_HIGH_U_I32x4_S\0"
5556 /* 24115 */ "MIN_U_I32x4_S\0"
5557 /* 24129 */ "SHR_U_I32x4_S\0"
5558 /* 24143 */ "GT_U_I32x4_S\0"
5559 /* 24156 */ "LT_U_I32x4_S\0"
5560 /* 24169 */ "EXTMUL_LOW_U_I32x4_S\0"
5561 /* 24190 */ "MAX_U_I32x4_S\0"
5562 /* 24204 */ "int_wasm_relaxed_trunc_signed_I32x4_S\0"
5563 /* 24242 */ "int_wasm_extadd_pairwise_signed_I32x4_S\0"
5564 /* 24282 */ "int_wasm_relaxed_trunc_unsigned_I32x4_S\0"
5565 /* 24322 */ "int_wasm_extadd_pairwise_unsigned_I32x4_S\0"
5566 /* 24364 */ "int_wasm_relaxed_trunc_signed_zero_I32x4_S\0"
5567 /* 24407 */ "int_wasm_relaxed_trunc_unsigned_zero_I32x4_S\0"
5568 /* 24452 */ "extend_high_s_I32x4_S\0"
5569 /* 24474 */ "trunc_sat_zero_s_I32x4_S\0"
5570 /* 24499 */ "extend_low_s_I32x4_S\0"
5571 /* 24520 */ "fp_to_sint_I32x4_S\0"
5572 /* 24539 */ "fp_to_uint_I32x4_S\0"
5573 /* 24558 */ "extend_high_u_I32x4_S\0"
5574 /* 24580 */ "trunc_sat_zero_u_I32x4_S\0"
5575 /* 24605 */ "extend_low_u_I32x4_S\0"
5576 /* 24626 */ "ARGUMENT_v8f16_S\0"
5577 /* 24643 */ "ARGUMENT_v8i16_S\0"
5578 /* 24660 */ "CONST_V128_I8x16_S\0"
5579 /* 24679 */ "SUB_I8x16_S\0"
5580 /* 24691 */ "ADD_I8x16_S\0"
5581 /* 24703 */ "REPLACE_LANE_I8x16_S\0"
5582 /* 24724 */ "ALLTRUE_I8x16_S\0"
5583 /* 24740 */ "NEG_I8x16_S\0"
5584 /* 24752 */ "BITMASK_I8x16_S\0"
5585 /* 24768 */ "SHL_I8x16_S\0"
5586 /* 24780 */ "EQ_I8x16_S\0"
5587 /* 24791 */ "ABS_I8x16_S\0"
5588 /* 24803 */ "GE_S_I8x16_S\0"
5589 /* 24816 */ "LE_S_I8x16_S\0"
5590 /* 24829 */ "MIN_S_I8x16_S\0"
5591 /* 24843 */ "SHR_S_I8x16_S\0"
5592 /* 24857 */ "SUB_SAT_S_I8x16_S\0"
5593 /* 24875 */ "ADD_SAT_S_I8x16_S\0"
5594 /* 24893 */ "GT_S_I8x16_S\0"
5595 /* 24906 */ "LT_S_I8x16_S\0"
5596 /* 24919 */ "NARROW_S_I8x16_S\0"
5597 /* 24936 */ "MAX_S_I8x16_S\0"
5598 /* 24950 */ "SPLAT_I8x16_S\0"
5599 /* 24964 */ "LANESELECT_I8x16_S\0"
5600 /* 24983 */ "POPCNT_I8x16_S\0"
5601 /* 24998 */ "GE_U_I8x16_S\0"
5602 /* 25011 */ "LE_U_I8x16_S\0"
5603 /* 25024 */ "MIN_U_I8x16_S\0"
5604 /* 25038 */ "AVGR_U_I8x16_S\0"
5605 /* 25053 */ "SHR_U_I8x16_S\0"
5606 /* 25067 */ "SUB_SAT_U_I8x16_S\0"
5607 /* 25085 */ "ADD_SAT_U_I8x16_S\0"
5608 /* 25103 */ "GT_U_I8x16_S\0"
5609 /* 25116 */ "LT_U_I8x16_S\0"
5610 /* 25129 */ "NARROW_U_I8x16_S\0"
5611 /* 25146 */ "MAX_U_I8x16_S\0"
5612 /* 25160 */ "LOCAL_TEE_V128_S\0"
5613 /* 25177 */ "DROP_V128_S\0"
5614 /* 25189 */ "SELECT_V128_S\0"
5615 /* 25203 */ "GLOBAL_GET_V128_S\0"
5616 /* 25221 */ "LOCAL_GET_V128_S\0"
5617 /* 25238 */ "GLOBAL_SET_V128_S\0"
5618 /* 25256 */ "LOCAL_SET_V128_S\0"
5619 /* 25273 */ "COPY_V128_S\0"
5620 /* 25285 */ "ARGUMENT_v16i8_S\0"
5621 /* 25302 */ "SUB_F16x8_S\0"
5622 /* 25314 */ "TRUNC_F16x8_S\0"
5623 /* 25328 */ "NMADD_F16x8_S\0"
5624 /* 25342 */ "GE_F16x8_S\0"
5625 /* 25353 */ "LE_F16x8_S\0"
5626 /* 25364 */ "EXTRACT_LANE_F16x8_S\0"
5627 /* 25385 */ "NEG_F16x8_S\0"
5628 /* 25397 */ "CEIL_F16x8_S\0"
5629 /* 25410 */ "MUL_F16x8_S\0"
5630 /* 25422 */ "PMIN_F16x8_S\0"
5631 /* 25435 */ "EQ_F16x8_S\0"
5632 /* 25446 */ "FLOOR_F16x8_S\0"
5633 /* 25460 */ "ABS_F16x8_S\0"
5634 /* 25472 */ "SPLAT_F16x8_S\0"
5635 /* 25486 */ "GT_F16x8_S\0"
5636 /* 25497 */ "LT_F16x8_S\0"
5637 /* 25508 */ "SQRT_F16x8_S\0"
5638 /* 25521 */ "NEAREST_F16x8_S\0"
5639 /* 25537 */ "DIV_F16x8_S\0"
5640 /* 25549 */ "PMAX_F16x8_S\0"
5641 /* 25562 */ "sint_to_fp_F16x8_S\0"
5642 /* 25581 */ "uint_to_fp_F16x8_S\0"
5643 /* 25600 */ "CONST_V128_I16x8_S\0"
5644 /* 25619 */ "SUB_I16x8_S\0"
5645 /* 25631 */ "ADD_I16x8_S\0"
5646 /* 25643 */ "REPLACE_LANE_I16x8_S\0"
5647 /* 25664 */ "ALLTRUE_I16x8_S\0"
5648 /* 25680 */ "NEG_I16x8_S\0"
5649 /* 25692 */ "BITMASK_I16x8_S\0"
5650 /* 25708 */ "SHL_I16x8_S\0"
5651 /* 25720 */ "MUL_I16x8_S\0"
5652 /* 25732 */ "EQ_I16x8_S\0"
5653 /* 25743 */ "ABS_I16x8_S\0"
5654 /* 25755 */ "GE_S_I16x8_S\0"
5655 /* 25768 */ "LE_S_I16x8_S\0"
5656 /* 25781 */ "EXTMUL_HIGH_S_I16x8_S\0"
5657 /* 25803 */ "MIN_S_I16x8_S\0"
5658 /* 25817 */ "SHR_S_I16x8_S\0"
5659 /* 25831 */ "RELAXED_Q15MULR_S_I16x8_S\0"
5660 /* 25857 */ "SUB_SAT_S_I16x8_S\0"
5661 /* 25875 */ "ADD_SAT_S_I16x8_S\0"
5662 /* 25893 */ "Q15MULR_SAT_S_I16x8_S\0"
5663 /* 25915 */ "GT_S_I16x8_S\0"
5664 /* 25928 */ "LT_S_I16x8_S\0"
5665 /* 25941 */ "EXTMUL_LOW_S_I16x8_S\0"
5666 /* 25962 */ "NARROW_S_I16x8_S\0"
5667 /* 25979 */ "MAX_S_I16x8_S\0"
5668 /* 25993 */ "SPLAT_I16x8_S\0"
5669 /* 26007 */ "LANESELECT_I16x8_S\0"
5670 /* 26026 */ "GE_U_I16x8_S\0"
5671 /* 26039 */ "LE_U_I16x8_S\0"
5672 /* 26052 */ "EXTMUL_HIGH_U_I16x8_S\0"
5673 /* 26074 */ "MIN_U_I16x8_S\0"
5674 /* 26088 */ "AVGR_U_I16x8_S\0"
5675 /* 26103 */ "SHR_U_I16x8_S\0"
5676 /* 26117 */ "SUB_SAT_U_I16x8_S\0"
5677 /* 26135 */ "ADD_SAT_U_I16x8_S\0"
5678 /* 26153 */ "GT_U_I16x8_S\0"
5679 /* 26166 */ "LT_U_I16x8_S\0"
5680 /* 26179 */ "EXTMUL_LOW_U_I16x8_S\0"
5681 /* 26200 */ "NARROW_U_I16x8_S\0"
5682 /* 26217 */ "MAX_U_I16x8_S\0"
5683 /* 26231 */ "int_wasm_extadd_pairwise_signed_I16x8_S\0"
5684 /* 26271 */ "int_wasm_extadd_pairwise_unsigned_I16x8_S\0"
5685 /* 26313 */ "extend_high_s_I16x8_S\0"
5686 /* 26335 */ "extend_low_s_I16x8_S\0"
5687 /* 26356 */ "fp_to_sint_I16x8_S\0"
5688 /* 26375 */ "fp_to_uint_I16x8_S\0"
5689 /* 26394 */ "extend_high_u_I16x8_S\0"
5690 /* 26416 */ "extend_low_u_I16x8_S\0"
5691 /* 26437 */ "RELAXED_DOT_ADD_S\0"
5692 /* 26455 */ "AND_S\0"
5693 /* 26461 */ "END_S\0"
5694 /* 26467 */ "ATOMIC_FENCE_S\0"
5695 /* 26482 */ "COMPILER_FENCE_S\0"
5696 /* 26499 */ "DEBUG_UNREACHABLE_S\0"
5697 /* 26519 */ "SHUFFLE_S\0"
5698 /* 26529 */ "RELAXED_SWIZZLE_S\0"
5699 /* 26547 */ "ELSE_S\0"
5700 /* 26554 */ "DELEGATE_S\0"
5701 /* 26565 */ "ANYTRUE_S\0"
5702 /* 26575 */ "TABLE_SIZE_S\0"
5703 /* 26588 */ "LOCAL_TEE_FUNCREF_S\0"
5704 /* 26608 */ "TABLE_FILL_FUNCREF_S\0"
5705 /* 26629 */ "REF_NULL_FUNCREF_S\0"
5706 /* 26648 */ "REF_IS_NULL_FUNCREF_S\0"
5707 /* 26670 */ "DROP_FUNCREF_S\0"
5708 /* 26685 */ "SELECT_FUNCREF_S\0"
5709 /* 26702 */ "TABLE_GET_FUNCREF_S\0"
5710 /* 26722 */ "GLOBAL_GET_FUNCREF_S\0"
5711 /* 26743 */ "LOCAL_GET_FUNCREF_S\0"
5712 /* 26763 */ "TABLE_SET_FUNCREF_S\0"
5713 /* 26783 */ "GLOBAL_SET_FUNCREF_S\0"
5714 /* 26804 */ "LOCAL_SET_FUNCREF_S\0"
5715 /* 26824 */ "TABLE_GROW_FUNCREF_S\0"
5716 /* 26845 */ "COPY_FUNCREF_S\0"
5717 /* 26860 */ "LOCAL_TEE_EXTERNREF_S\0"
5718 /* 26882 */ "TABLE_FILL_EXTERNREF_S\0"
5719 /* 26905 */ "REF_NULL_EXTERNREF_S\0"
5720 /* 26926 */ "REF_IS_NULL_EXTERNREF_S\0"
5721 /* 26950 */ "DROP_EXTERNREF_S\0"
5722 /* 26967 */ "SELECT_EXTERNREF_S\0"
5723 /* 26986 */ "TABLE_GET_EXTERNREF_S\0"
5724 /* 27008 */ "GLOBAL_GET_EXTERNREF_S\0"
5725 /* 27031 */ "LOCAL_GET_EXTERNREF_S\0"
5726 /* 27053 */ "TABLE_SET_EXTERNREF_S\0"
5727 /* 27075 */ "GLOBAL_SET_EXTERNREF_S\0"
5728 /* 27098 */ "LOCAL_SET_EXTERNREF_S\0"
5729 /* 27120 */ "TABLE_GROW_EXTERNREF_S\0"
5730 /* 27143 */ "COPY_EXTERNREF_S\0"
5731 /* 27160 */ "LOCAL_TEE_EXNREF_S\0"
5732 /* 27179 */ "TABLE_FILL_EXNREF_S\0"
5733 /* 27199 */ "REF_NULL_EXNREF_S\0"
5734 /* 27217 */ "REF_IS_NULL_EXNREF_S\0"
5735 /* 27238 */ "DROP_EXNREF_S\0"
5736 /* 27252 */ "SELECT_EXNREF_S\0"
5737 /* 27268 */ "TABLE_GET_EXNREF_S\0"
5738 /* 27287 */ "GLOBAL_GET_EXNREF_S\0"
5739 /* 27307 */ "LOCAL_GET_EXNREF_S\0"
5740 /* 27326 */ "TABLE_SET_EXNREF_S\0"
5741 /* 27345 */ "GLOBAL_SET_EXNREF_S\0"
5742 /* 27365 */ "LOCAL_SET_EXNREF_S\0"
5743 /* 27384 */ "TABLE_GROW_EXNREF_S\0"
5744 /* 27404 */ "COPY_EXNREF_S\0"
5745 /* 27418 */ "END_IF_S\0"
5746 /* 27427 */ "BR_IF_S\0"
5747 /* 27435 */ "CATCH_S\0"
5748 /* 27443 */ "END_BLOCK_S\0"
5749 /* 27455 */ "RET_CALL_S\0"
5750 /* 27466 */ "CATCH_ALL_S\0"
5751 /* 27478 */ "END_FUNCTION_S\0"
5752 /* 27493 */ "FALLTHROUGH_RETURN_S\0"
5753 /* 27514 */ "ADJCALLSTACKDOWN_S\0"
5754 /* 27533 */ "NOP_S\0"
5755 /* 27539 */ "END_LOOP_S\0"
5756 /* 27550 */ "anonymous_8878DATA_DROP_S\0"
5757 /* 27576 */ "anonymous_8879DATA_DROP_S\0"
5758 /* 27602 */ "ADJCALLSTACKUP_S\0"
5759 /* 27619 */ "BR_S\0"
5760 /* 27624 */ "XOR_S\0"
5761 /* 27630 */ "CALL_PARAMS_S\0"
5762 /* 27644 */ "BR_UNLESS_S\0"
5763 /* 27656 */ "RET_CALL_RESULTS_S\0"
5764 /* 27675 */ "RELAXED_DOT_BFLOAT_S\0"
5765 /* 27696 */ "BITSELECT_S\0"
5766 /* 27708 */ "RET_CALL_INDIRECT_S\0"
5767 /* 27728 */ "CATCHRET_S\0"
5768 /* 27739 */ "CLEANUPRET_S\0"
5769 /* 27752 */ "RELAXED_DOT_S\0"
5770 /* 27766 */ "ANDNOT_S\0"
5771 /* 27775 */ "RETHROW_S\0"
5772 /* 27785 */ "TABLE_COPY_S\0"
5773 /* 27798 */ "END_TRY_S\0"
5774 /* 27808 */ "ARGUMENT_funcref_S\0"
5775 /* 27827 */ "ARGUMENT_externref_S\0"
5776 /* 27848 */ "ARGUMENT_exnref_S\0"
5777 /* 27866 */ "EXTRACT_LANE_I8x16_s_S\0"
5778 /* 27889 */ "EXTRACT_LANE_I16x8_s_S\0"
5779 /* 27912 */ "EXTRACT_LANE_I8x16_u_S\0"
5780 /* 27935 */ "EXTRACT_LANE_I16x8_u_S\0"
5781 /* 27958 */ "RELAXED_DOT_BFLOAT\0"
5782 /* 27977 */ "G_SSUBSAT\0"
5783 /* 27987 */ "G_USUBSAT\0"
5784 /* 27997 */ "G_SADDSAT\0"
5785 /* 28007 */ "G_UADDSAT\0"
5786 /* 28017 */ "G_SSHLSAT\0"
5787 /* 28027 */ "G_USHLSAT\0"
5788 /* 28037 */ "G_SMULFIXSAT\0"
5789 /* 28050 */ "G_UMULFIXSAT\0"
5790 /* 28063 */ "G_SDIVFIXSAT\0"
5791 /* 28076 */ "G_UDIVFIXSAT\0"
5792 /* 28089 */ "G_EXTRACT\0"
5793 /* 28099 */ "BITSELECT\0"
5794 /* 28109 */ "G_SELECT\0"
5795 /* 28118 */ "G_BRINDIRECT\0"
5796 /* 28131 */ "RET_CALL_INDIRECT\0"
5797 /* 28149 */ "CATCHRET\0"
5798 /* 28158 */ "CLEANUPRET\0"
5799 /* 28169 */ "PATCHABLE_RET\0"
5800 /* 28183 */ "G_MEMSET\0"
5801 /* 28192 */ "PATCHABLE_FUNCTION_EXIT\0"
5802 /* 28216 */ "G_BRJT\0"
5803 /* 28223 */ "G_EXTRACT_VECTOR_ELT\0"
5804 /* 28244 */ "G_INSERT_VECTOR_ELT\0"
5805 /* 28264 */ "G_FCONSTANT\0"
5806 /* 28276 */ "G_CONSTANT\0"
5807 /* 28287 */ "G_INTRINSIC_CONVERGENT\0"
5808 /* 28310 */ "STATEPOINT\0"
5809 /* 28321 */ "PATCHPOINT\0"
5810 /* 28332 */ "G_PTRTOINT\0"
5811 /* 28343 */ "G_FRINT\0"
5812 /* 28351 */ "G_INTRINSIC_LLRINT\0"
5813 /* 28370 */ "G_INTRINSIC_LRINT\0"
5814 /* 28388 */ "G_FNEARBYINT\0"
5815 /* 28401 */ "RELAXED_DOT\0"
5816 /* 28413 */ "ANDNOT\0"
5817 /* 28420 */ "G_VASTART\0"
5818 /* 28430 */ "LIFETIME_START\0"
5819 /* 28445 */ "G_INVOKE_REGION_START\0"
5820 /* 28467 */ "G_INSERT\0"
5821 /* 28476 */ "G_FSQRT\0"
5822 /* 28484 */ "G_STRICT_FSQRT\0"
5823 /* 28499 */ "G_BITCAST\0"
5824 /* 28509 */ "G_ADDRSPACE_CAST\0"
5825 /* 28526 */ "DBG_VALUE_LIST\0"
5826 /* 28541 */ "G_FPEXT\0"
5827 /* 28549 */ "G_SEXT\0"
5828 /* 28556 */ "G_ASSERT_SEXT\0"
5829 /* 28570 */ "G_ANYEXT\0"
5830 /* 28579 */ "G_ZEXT\0"
5831 /* 28586 */ "G_ASSERT_ZEXT\0"
5832 /* 28600 */ "G_FDIV\0"
5833 /* 28607 */ "G_STRICT_FDIV\0"
5834 /* 28621 */ "G_SDIV\0"
5835 /* 28628 */ "G_UDIV\0"
5836 /* 28635 */ "G_GET_FPENV\0"
5837 /* 28647 */ "G_RESET_FPENV\0"
5838 /* 28661 */ "G_SET_FPENV\0"
5839 /* 28673 */ "G_FPOW\0"
5840 /* 28680 */ "RETHROW\0"
5841 /* 28688 */ "G_VECREDUCE_FMAX\0"
5842 /* 28705 */ "G_ATOMICRMW_FMAX\0"
5843 /* 28722 */ "G_VECREDUCE_SMAX\0"
5844 /* 28739 */ "G_SMAX\0"
5845 /* 28746 */ "G_VECREDUCE_UMAX\0"
5846 /* 28763 */ "G_UMAX\0"
5847 /* 28770 */ "G_ATOMICRMW_UMAX\0"
5848 /* 28787 */ "G_ATOMICRMW_MAX\0"
5849 /* 28803 */ "G_FRAME_INDEX\0"
5850 /* 28817 */ "G_SBFX\0"
5851 /* 28824 */ "G_UBFX\0"
5852 /* 28831 */ "G_SMULFIX\0"
5853 /* 28841 */ "G_UMULFIX\0"
5854 /* 28851 */ "G_SDIVFIX\0"
5855 /* 28861 */ "G_UDIVFIX\0"
5856 /* 28871 */ "G_MEMCPY\0"
5857 /* 28880 */ "TABLE_COPY\0"
5858 /* 28891 */ "CONVERGENCECTRL_ENTRY\0"
5859 /* 28913 */ "END_TRY\0"
5860 /* 28921 */ "G_CTLZ\0"
5861 /* 28928 */ "G_CTTZ\0"
5862 /* 28935 */ "ARGUMENT_funcref\0"
5863 /* 28952 */ "ARGUMENT_externref\0"
5864 /* 28971 */ "ARGUMENT_exnref\0"
5865 /* 28987 */ "EXTRACT_LANE_I8x16_s\0"
5866 /* 29008 */ "EXTRACT_LANE_I16x8_s\0"
5867 /* 29029 */ "EXTRACT_LANE_I8x16_u\0"
5868 /* 29050 */ "EXTRACT_LANE_I16x8_u\0"
5869};
5870#ifdef __GNUC__
5871#pragma GCC diagnostic pop
5872#endif
5873
5874extern const unsigned WebAssemblyInstrNameIndices[] = {
5875 12713U, 13112U, 13876U, 13413U, 12782U, 12763U, 12791U, 12948U,
5876 12530U, 12545U, 11737U, 12572U, 14353U, 11564U, 28526U, 12496U,
5877 12709U, 12772U, 11298U, 28886U, 11438U, 28430U, 11119U, 11221U,
5878 11271U, 13543U, 12926U, 28321U, 11204U, 13811U, 12635U, 28310U,
5879 11485U, 13784U, 13771U, 13937U, 28169U, 28192U, 12849U, 12905U,
5880 12878U, 12808U, 13902U, 13497U, 28891U, 14055U, 13694U, 11612U,
5881 28556U, 28586U, 13243U, 11016U, 10727U, 13051U, 28621U, 28628U,
5882 13078U, 13085U, 13092U, 13102U, 11097U, 14226U, 14189U, 11735U,
5883 12711U, 28803U, 11574U, 11589U, 12953U, 28089U, 14277U, 28467U,
5884 14294U, 14126U, 10797U, 14336U, 28332U, 14253U, 28499U, 11663U,
5885 13913U, 11178U, 10771U, 11160U, 28370U, 28351U, 13221U, 13962U,
5886 13981U, 10917U, 10861U, 10891U, 10902U, 10842U, 10872U, 11529U,
5887 11513U, 14383U, 12586U, 12603U, 11048U, 10733U, 11103U, 11064U,
5888 14231U, 14195U, 28787U, 13369U, 28770U, 13352U, 10983U, 10710U,
5889 28705U, 13287U, 13605U, 13583U, 11263U, 12658U, 11132U, 28118U,
5890 28445U, 10749U, 14441U, 28287U, 14468U, 28570U, 10789U, 28276U,
5891 28264U, 28420U, 12627U, 28549U, 12559U, 28579U, 12835U, 14048U,
5892 14034U, 12828U, 14041U, 14246U, 12969U, 13660U, 13653U, 13667U,
5893 13674U, 28109U, 13489U, 11319U, 13473U, 11242U, 13481U, 11311U,
5894 13465U, 11234U, 13527U, 13519U, 12677U, 12669U, 28007U, 27997U,
5895 27987U, 27977U, 28027U, 28017U, 28831U, 28841U, 28037U, 28050U,
5896 28851U, 28861U, 28063U, 28076U, 10941U, 10689U, 12993U, 10670U,
5897 10835U, 28600U, 13057U, 28673U, 12735U, 13855U, 3587U, 9U,
5898 12620U, 3579U, 0U, 13830U, 13862U, 12523U, 28541U, 10761U,
5899 12717U, 12726U, 13635U, 13644U, 14264U, 13258U, 14370U, 11672U,
5900 13186U, 13196U, 11368U, 11383U, 13143U, 13175U, 28635U, 28661U,
5901 28647U, 11327U, 11355U, 11340U, 11022U, 12753U, 13321U, 28739U,
5902 13345U, 28763U, 14271U, 11151U, 11141U, 13871U, 28216U, 11398U,
5903 14107U, 14087U, 28244U, 28223U, 14141U, 14158U, 14423U, 28928U,
5904 11717U, 28921U, 11699U, 13715U, 13627U, 11542U, 12841U, 14329U,
5905 13393U, 13214U, 14321U, 13385U, 13206U, 12701U, 12693U, 12685U,
5906 28476U, 14078U, 28343U, 28388U, 28509U, 13889U, 11425U, 10818U,
5907 11641U, 11498U, 10969U, 10696U, 13021U, 28607U, 13064U, 10676U,
5908 28484U, 13839U, 14001U, 14017U, 28871U, 11469U, 11653U, 28183U,
5909 13535U, 13576U, 13552U, 13564U, 10948U, 13000U, 10924U, 12976U,
5910 28688U, 13270U, 13154U, 13122U, 11000U, 13035U, 11081U, 14211U,
5911 14173U, 28722U, 13304U, 28746U, 13328U, 28817U, 28824U, 14309U,
5912 27630U, 14510U, 27660U, 28149U, 27728U, 28158U, 27739U, 11283U,
5913 26482U, 14506U, 27656U, 9809U, 25460U, 2678U, 17431U, 8114U,
5914 23535U, 7021U, 22264U, 3789U, 18704U, 10052U, 25743U, 8418U,
5915 23885U, 4099U, 19060U, 9232U, 24791U, 9699U, 25330U, 2547U,
5916 17272U, 7961U, 23358U, 6891U, 22106U, 3636U, 18527U, 9956U,
5917 25631U, 2997U, 17798U, 8303U, 23752U, 7340U, 22631U, 3984U,
5918 18927U, 9146U, 24691U, 10168U, 25875U, 9304U, 24875U, 10396U,
5919 26135U, 9486U, 25085U, 13448U, 27514U, 13796U, 27602U, 9985U,
5920 25664U, 8351U, 23806U, 4032U, 18981U, 9175U, 24724U, 11077U,
5921 28413U, 27766U, 3005U, 17808U, 7348U, 22641U, 26455U, 11633U,
5922 26565U, 28971U, 27848U, 28952U, 27827U, 3538U, 18433U, 7879U,
5923 23264U, 28935U, 27808U, 3566U, 18465U, 7907U, 23296U, 9660U,
5924 25285U, 7864U, 23247U, 7892U, 23279U, 3523U, 18416U, 3551U,
5925 18448U, 9089U, 24626U, 9104U, 24643U, 11250U, 26467U, 743U,
5926 15310U, 5087U, 20144U, 1871U, 16532U, 6215U, 21366U, 1847U,
5927 16506U, 6191U, 21340U, 767U, 15336U, 5111U, 20170U, 1895U,
5928 16558U, 6239U, 21392U, 201U, 14724U, 4545U, 19558U, 1122U,
5929 15723U, 5466U, 20557U, 221U, 14746U, 4565U, 19580U, 1169U,
5930 15774U, 5513U, 20608U, 297U, 14828U, 4641U, 19662U, 1272U,
5931 15885U, 5616U, 20719U, 394U, 14933U, 4738U, 19767U, 1400U,
5932 16023U, 5744U, 20857U, 637U, 15194U, 4981U, 20028U, 1724U,
5933 16371U, 6068U, 21205U, 125U, 14642U, 4469U, 19476U, 1046U,
5934 15641U, 5390U, 20475U, 482U, 15027U, 4826U, 19861U, 1516U,
5935 16147U, 5860U, 20981U, 561U, 15112U, 4905U, 19946U, 1622U,
5936 16261U, 5966U, 21095U, 1142U, 15745U, 5486U, 20579U, 1245U,
5937 15856U, 5589U, 20690U, 1369U, 15990U, 5713U, 20824U, 1698U,
5938 16343U, 6042U, 21177U, 1019U, 15612U, 5363U, 20446U, 1488U,
5939 16117U, 5832U, 20951U, 1595U, 16232U, 5939U, 21066U, 248U,
5940 14775U, 4592U, 19609U, 1196U, 15803U, 5540U, 20637U, 324U,
5941 14857U, 4668U, 19691U, 1299U, 15914U, 5643U, 20748U, 425U,
5942 14966U, 4769U, 19800U, 1431U, 16056U, 5775U, 20890U, 663U,
5943 15222U, 5007U, 20056U, 1750U, 16399U, 6094U, 21233U, 152U,
5944 14671U, 4496U, 19505U, 1073U, 15670U, 5417U, 20504U, 510U,
5945 15057U, 4854U, 19891U, 1544U, 16177U, 5888U, 21011U, 588U,
5946 15141U, 4932U, 19975U, 1649U, 16290U, 5993U, 21124U, 274U,
5947 14803U, 4618U, 19637U, 1222U, 15831U, 5566U, 20665U, 350U,
5948 14885U, 4694U, 19719U, 1325U, 15942U, 5669U, 20776U, 455U,
5949 14998U, 4799U, 19832U, 1461U, 16088U, 5805U, 20922U, 688U,
5950 15249U, 5032U, 20083U, 1775U, 16426U, 6119U, 21260U, 178U,
5951 14699U, 4522U, 19533U, 1099U, 15698U, 5443U, 20532U, 537U,
5952 15086U, 4881U, 19920U, 1571U, 16206U, 5915U, 21040U, 614U,
5953 15169U, 4958U, 20003U, 1675U, 16318U, 6019U, 21152U, 80U,
5954 14593U, 4424U, 19427U, 974U, 15563U, 5318U, 20397U, 951U,
5955 15538U, 5295U, 20372U, 103U, 14618U, 4447U, 19452U, 997U,
5956 15588U, 5341U, 20422U, 373U, 14910U, 4717U, 19744U, 1348U,
5957 15967U, 5692U, 20801U, 10355U, 26088U, 9445U, 25038U, 10009U,
5958 25692U, 8375U, 23834U, 4056U, 19009U, 9199U, 24752U, 28099U,
5959 27696U, 12747U, 27447U, 13873U, 12517U, 27427U, 27619U, 3027U,
5960 17834U, 7370U, 22667U, 14413U, 27644U, 12864U, 28135U, 27712U,
5961 27459U, 12652U, 12938U, 27466U, 27435U, 9756U, 25397U, 2614U,
5962 17353U, 8037U, 23446U, 6957U, 22186U, 3712U, 18615U, 3499U,
5963 18386U, 7840U, 23217U, 2922U, 17709U, 7265U, 22542U, 3361U,
5964 18224U, 7719U, 23074U, 7920U, 23311U, 3595U, 18480U, 9929U,
5965 25600U, 8276U, 23721U, 3957U, 18896U, 9119U, 24660U, 2631U,
5966 17374U, 6974U, 22207U, 12484U, 27404U, 12251U, 27143U, 2980U,
5967 17777U, 7323U, 22610U, 11981U, 26845U, 3490U, 18375U, 7831U,
5968 23206U, 9650U, 25273U, 3515U, 18406U, 7856U, 23237U, 11407U,
5969 26499U, 11555U, 26554U, 9874U, 25537U, 2964U, 17757U, 8179U,
5970 23612U, 7307U, 22590U, 3854U, 18781U, 3251U, 18098U, 7609U,
5971 22948U, 3480U, 18363U, 7821U, 23194U, 28409U, 27760U, 12336U,
5972 27238U, 12076U, 26950U, 2652U, 17399U, 6995U, 22232U, 11824U,
5973 26670U, 3072U, 17889U, 7428U, 22737U, 9566U, 25177U, 11537U,
5974 26547U, 11128U, 12743U, 27443U, 13400U, 27478U, 12510U, 27418U,
5975 13685U, 27539U, 26461U, 28913U, 27798U, 3507U, 18396U, 7848U,
5976 23227U, 9788U, 25435U, 2661U, 17410U, 8093U, 23510U, 7004U,
5977 22243U, 3768U, 18679U, 10043U, 25732U, 3081U, 17900U, 8409U,
5978 23874U, 7437U, 22748U, 4090U, 19049U, 9223U, 24780U, 10084U,
5979 25781U, 8450U, 23923U, 4131U, 19098U, 10323U, 26052U, 8598U,
5980 24093U, 4233U, 19214U, 10226U, 25941U, 8516U, 23999U, 4185U,
5981 19160U, 10434U, 26179U, 8664U, 24169U, 4265U, 19250U, 9727U,
5982 25364U, 8008U, 23413U, 3683U, 18582U, 29008U, 27889U, 29050U,
5983 27935U, 8332U, 23785U, 4013U, 18960U, 28987U, 27866U, 29029U,
5984 27912U, 3215U, 18058U, 7573U, 22908U, 3444U, 18323U, 7785U,
5985 23154U, 6934U, 22159U, 3301U, 18156U, 3233U, 18078U, 7591U,
5986 22928U, 3462U, 18343U, 7803U, 23174U, 2590U, 17325U, 7659U,
5987 23006U, 13429U, 27493U, 9797U, 25446U, 2668U, 17419U, 8102U,
5988 23521U, 7011U, 22252U, 3777U, 18690U, 2453U, 17166U, 6797U,
5989 22000U, 2491U, 17208U, 6835U, 22042U, 2472U, 17187U, 6816U,
5990 22021U, 2510U, 17229U, 6854U, 22063U, 9709U, 25342U, 2569U,
5991 17298U, 7971U, 23370U, 6913U, 22132U, 3646U, 18539U, 10062U,
5992 25755U, 3159U, 17990U, 8428U, 23897U, 7517U, 22840U, 4109U,
5993 19072U, 9242U, 24803U, 10301U, 26026U, 3388U, 18255U, 8576U,
5994 24067U, 7729U, 23086U, 9411U, 24998U, 12379U, 27287U, 12128U,
5995 27008U, 2809U, 17578U, 7152U, 22411U, 11870U, 26722U, 3272U,
5996 18123U, 7630U, 22973U, 9588U, 25203U, 12431U, 27345U, 12189U,
5997 27075U, 2858U, 17633U, 7201U, 22466U, 11925U, 26783U, 3321U,
5998 18178U, 7679U, 23028U, 9619U, 25238U, 9831U, 25486U, 2887U,
5999 17666U, 8136U, 23561U, 7230U, 22499U, 3811U, 18730U, 10204U,
6000 25915U, 3197U, 18036U, 8494U, 23973U, 7555U, 22886U, 4163U,
6001 19134U, 9320U, 24893U, 10412U, 26153U, 3426U, 18301U, 8642U,
6002 24143U, 7767U, 23132U, 9502U, 25103U, 3105U, 17930U, 3124U,
6003 17951U, 2838U, 17611U, 2686U, 17441U, 7029U, 22274U, 2718U,
6004 17477U, 7061U, 22310U, 2932U, 17721U, 7275U, 22554U, 2758U,
6005 17521U, 7101U, 22354U, 7415U, 22722U, 7480U, 22799U, 7461U,
6006 22778U, 7499U, 22820U, 3142U, 17971U, 3371U, 18236U, 7181U,
6007 22444U, 2702U, 17459U, 7045U, 22292U, 2738U, 17499U, 7081U,
6008 22332U, 2948U, 17739U, 7291U, 22572U, 2778U, 17543U, 7121U,
6009 22376U, 12514U, 27422U, 10284U, 26007U, 8559U, 24048U, 4216U,
6010 19195U, 9381U, 24964U, 9718U, 25353U, 2576U, 17307U, 7980U,
6011 23381U, 6920U, 22141U, 3655U, 18550U, 10073U, 25768U, 3168U,
6012 18001U, 8439U, 23910U, 7526U, 22851U, 4120U, 19085U, 9253U,
6013 24816U, 10312U, 26039U, 3397U, 18266U, 8587U, 24080U, 7738U,
6014 23097U, 9422U, 25011U, 2305U, 17006U, 6649U, 21840U, 710U,
6015 15273U, 5054U, 20107U, 1814U, 16469U, 6158U, 21303U, 750U,
6016 15317U, 5094U, 20151U, 1878U, 16539U, 6222U, 21373U, 2271U,
6017 16968U, 6615U, 21802U, 1797U, 16450U, 6141U, 21284U, 1854U,
6018 16513U, 6198U, 21347U, 2288U, 16987U, 6632U, 21821U, 2322U,
6019 17025U, 6666U, 21859U, 727U, 15292U, 5071U, 20126U, 1831U,
6020 16488U, 6175U, 21322U, 774U, 15343U, 5118U, 20177U, 1902U,
6021 16565U, 6246U, 21399U, 2163U, 16852U, 6507U, 21686U, 2004U,
6022 16677U, 6348U, 21511U, 876U, 15455U, 5220U, 20289U, 2187U,
6023 16878U, 6531U, 21712U, 2028U, 16703U, 6372U, 21537U, 900U,
6024 15481U, 5244U, 20315U, 18U, 14523U, 4362U, 19357U, 53U,
6025 14562U, 4397U, 19396U, 924U, 15507U, 5268U, 20341U, 208U,
6026 14731U, 4552U, 19565U, 1129U, 15730U, 5473U, 20564U, 2122U,
6027 16807U, 6466U, 21641U, 1943U, 16610U, 6287U, 21444U, 815U,
6028 15388U, 5159U, 20222U, 2052U, 16729U, 6396U, 21563U, 2093U,
6029 16774U, 6437U, 21608U, 1984U, 16655U, 6328U, 21489U, 856U,
6030 15433U, 5200U, 20267U, 12397U, 27307U, 12149U, 27031U, 2824U,
6031 17595U, 7167U, 22428U, 11889U, 26743U, 3287U, 18140U, 7645U,
6032 22990U, 9604U, 25221U, 12449U, 27365U, 12210U, 27098U, 2873U,
6033 17650U, 7216U, 22483U, 11944U, 26804U, 3336U, 18195U, 7694U,
6034 23045U, 9635U, 25256U, 12266U, 27160U, 11994U, 26860U, 2555U,
6035 17282U, 6899U, 22116U, 11750U, 26588U, 3013U, 17818U, 7356U,
6036 22651U, 9551U, 25160U, 13689U, 27543U, 9840U, 25497U, 2894U,
6037 17675U, 8145U, 23572U, 7237U, 22508U, 3820U, 18741U, 10215U,
6038 25928U, 3206U, 18047U, 8505U, 23986U, 7564U, 22897U, 4174U,
6039 19147U, 9331U, 24906U, 10423U, 26166U, 3435U, 18312U, 8653U,
6040 24156U, 7776U, 23143U, 9513U, 25116U, 9698U, 25329U, 7960U,
6041 23357U, 3635U, 18526U, 9885U, 25550U, 2972U, 17767U, 8203U,
6042 23638U, 7315U, 22600U, 3878U, 18807U, 10260U, 25979U, 8535U,
6043 24020U, 9357U, 24936U, 10468U, 26217U, 8683U, 24190U, 9539U,
6044 25146U, 2398U, 17107U, 6742U, 21941U, 790U, 15361U, 5134U,
6045 20195U, 1918U, 16583U, 6262U, 21417U, 9778U, 25423U, 2644U,
6046 17389U, 8072U, 23485U, 6987U, 22222U, 3747U, 18654U, 10104U,
6047 25803U, 8470U, 23945U, 9264U, 24829U, 10343U, 26074U, 8618U,
6048 24115U, 9433U, 25024U, 9767U, 25410U, 2623U, 17364U, 8048U,
6049 23459U, 6966U, 22197U, 3723U, 18628U, 10033U, 25720U, 3064U,
6050 17879U, 8399U, 23862U, 7407U, 22712U, 4080U, 19037U, 10245U,
6051 25962U, 9342U, 24919U, 10453U, 26200U, 9524U, 25129U, 9860U,
6052 25521U, 2910U, 17695U, 8165U, 23596U, 7253U, 22528U, 3840U,
6053 18765U, 9746U, 25385U, 2606U, 17343U, 8027U, 23434U, 6949U,
6054 22176U, 3702U, 18603U, 9999U, 25680U, 8365U, 23822U, 4046U,
6055 18997U, 9189U, 24740U, 9737U, 25374U, 2583U, 17316U, 7999U,
6056 23402U, 6927U, 22150U, 3674U, 18571U, 9976U, 25653U, 3040U,
6057 17849U, 8323U, 23774U, 7383U, 22682U, 4004U, 18949U, 9166U,
6058 24713U, 9697U, 25328U, 7959U, 23356U, 3634U, 18525U, 13681U,
6059 27533U, 28416U, 27769U, 14075U, 3089U, 17910U, 7445U, 22758U,
6060 27625U, 9884U, 25549U, 8213U, 23650U, 3888U, 18819U, 9777U,
6061 25422U, 8082U, 23497U, 3757U, 18666U, 3350U, 18211U, 7708U,
6062 23061U, 9398U, 24983U, 10184U, 25893U, 12317U, 27217U, 12054U,
6063 26926U, 11804U, 26648U, 12301U, 27199U, 12035U, 26905U, 11787U,
6064 26629U, 28401U, 11032U, 26437U, 27958U, 27675U, 27752U, 10128U,
6065 25831U, 11453U, 26529U, 3177U, 18012U, 7535U, 22862U, 3406U,
6066 18277U, 7747U, 23108U, 7989U, 23392U, 3664U, 18561U, 9966U,
6067 25643U, 8313U, 23764U, 3994U, 18939U, 9156U, 24703U, 28680U,
6068 27775U, 13441U, 27505U, 12869U, 28131U, 27708U, 27455U, 3055U,
6069 17868U, 7398U, 22701U, 3096U, 17919U, 7452U, 22767U, 12348U,
6070 27252U, 12091U, 26967U, 2798U, 17565U, 7141U, 22398U, 11837U,
6071 26685U, 3261U, 18110U, 7619U, 22960U, 9576U, 25189U, 10023U,
6072 25708U, 3047U, 17858U, 8389U, 23850U, 7390U, 22691U, 4070U,
6073 19025U, 9213U, 24768U, 10116U, 25817U, 3187U, 18024U, 8482U,
6074 23959U, 7545U, 22874U, 4151U, 19120U, 9276U, 24843U, 10368U,
6075 26103U, 3416U, 18289U, 8630U, 24129U, 7757U, 23120U, 4253U,
6076 19236U, 9458U, 25053U, 11445U, 26519U, 8189U, 23624U, 3864U,
6077 18793U, 8058U, 23471U, 3733U, 18640U, 9819U, 25472U, 8124U,
6078 23547U, 3799U, 18716U, 10272U, 25993U, 8547U, 24034U, 4204U,
6079 19181U, 9369U, 24950U, 9849U, 25508U, 2901U, 17684U, 8154U,
6080 23583U, 7244U, 22517U, 3829U, 18752U, 87U, 14600U, 4431U,
6081 19434U, 981U, 15570U, 5325U, 20404U, 958U, 15545U, 5302U,
6082 20379U, 110U, 14625U, 4454U, 19459U, 1004U, 15595U, 5348U,
6083 20429U, 35U, 14542U, 4379U, 19376U, 66U, 14577U, 4410U,
6084 19411U, 937U, 15522U, 5281U, 20356U, 380U, 14917U, 4724U,
6085 19751U, 1355U, 15974U, 5699U, 20808U, 2142U, 16829U, 6486U,
6086 21663U, 1963U, 16632U, 6307U, 21466U, 835U, 15410U, 5179U,
6087 20244U, 2072U, 16751U, 6416U, 21585U, 2107U, 16790U, 6451U,
6088 21624U, 9675U, 25302U, 2529U, 17250U, 7937U, 23330U, 6873U,
6089 22084U, 3612U, 18499U, 9946U, 25619U, 2989U, 17788U, 8293U,
6090 23740U, 7332U, 22621U, 3974U, 18915U, 9136U, 24679U, 10152U,
6091 25857U, 9288U, 24857U, 10380U, 26117U, 9470U, 25067U, 11461U,
6092 26537U, 28880U, 27785U, 12283U, 27179U, 12014U, 26882U, 11768U,
6093 26608U, 12362U, 27268U, 12108U, 26986U, 11852U, 26702U, 12466U,
6094 27384U, 12230U, 27120U, 11962U, 26824U, 12414U, 27326U, 12169U,
6095 27053U, 11907U, 26763U, 11688U, 26575U, 12272U, 27166U, 12000U,
6096 26866U, 2561U, 17288U, 6905U, 22122U, 11756U, 26594U, 3019U,
6097 17824U, 7362U, 22657U, 9557U, 25166U, 28682U, 27777U, 9685U,
6098 25314U, 2537U, 17260U, 7947U, 23342U, 6881U, 22094U, 3622U,
6099 18511U, 28909U, 27802U, 11413U, 26505U, 14185U, 3088U, 17909U,
6100 7444U, 22757U, 27624U, 2368U, 17075U, 2211U, 16904U, 6712U,
6101 21909U, 6555U, 21738U, 13723U, 27550U, 2423U, 17134U, 2241U,
6102 16936U, 2338U, 17043U, 13747U, 27576U, 6767U, 21968U, 6585U,
6103 21770U, 6682U, 21877U, 3899U, 18832U, 3919U, 18854U, 8224U,
6104 23663U, 10558U, 26313U, 8931U, 24452U, 4284U, 19271U, 10631U,
6105 26394U, 9027U, 24558U, 4323U, 19314U, 10578U, 26335U, 8974U,
6106 24499U, 4304U, 19293U, 10651U, 26416U, 9070U, 24605U, 4343U,
6107 19336U, 10597U, 26356U, 8993U, 24520U, 10614U, 26375U, 9010U,
6108 24539U, 10480U, 26231U, 8731U, 24242U, 10518U, 26271U, 8807U,
6109 24322U, 8695U, 24204U, 8847U, 24364U, 8769U, 24282U, 8888U,
6110 24407U, 3939U, 18876U, 9895U, 25562U, 8242U, 23683U, 8951U,
6111 24474U, 9047U, 24580U, 9912U, 25581U, 8259U, 23702U,
6112};
6113
6114static inline void InitWebAssemblyMCInstrInfo(MCInstrInfo *II) {
6115 II->InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1895);
6116}
6117
6118} // end namespace llvm
6119#endif // GET_INSTRINFO_MC_DESC
6120
6121#ifdef GET_INSTRINFO_HEADER
6122#undef GET_INSTRINFO_HEADER
6123namespace llvm {
6124struct WebAssemblyGenInstrInfo : public TargetInstrInfo {
6125 explicit WebAssemblyGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
6126 ~WebAssemblyGenInstrInfo() override = default;
6127
6128};
6129} // end namespace llvm
6130#endif // GET_INSTRINFO_HEADER
6131
6132#ifdef GET_INSTRINFO_HELPER_DECLS
6133#undef GET_INSTRINFO_HELPER_DECLS
6134
6135
6136#endif // GET_INSTRINFO_HELPER_DECLS
6137
6138#ifdef GET_INSTRINFO_HELPERS
6139#undef GET_INSTRINFO_HELPERS
6140
6141#endif // GET_INSTRINFO_HELPERS
6142
6143#ifdef GET_INSTRINFO_CTOR_DTOR
6144#undef GET_INSTRINFO_CTOR_DTOR
6145namespace llvm {
6146extern const WebAssemblyInstrTable WebAssemblyDescs;
6147extern const unsigned WebAssemblyInstrNameIndices[];
6148extern const char WebAssemblyInstrNameData[];
6149WebAssemblyGenInstrInfo::WebAssemblyGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
6150 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
6151 InitMCInstrInfo(WebAssemblyDescs.Insts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, nullptr, nullptr, 1895);
6152}
6153} // end namespace llvm
6154#endif // GET_INSTRINFO_CTOR_DTOR
6155
6156#ifdef GET_INSTRINFO_OPERAND_ENUM
6157#undef GET_INSTRINFO_OPERAND_ENUM
6158namespace llvm {
6159namespace WebAssembly {
6160namespace OpName {
6161enum {
6162 addr = 3,
6163 count = 9,
6164 dst = 0,
6165 exp = 5,
6166 idx = 7,
6167 new_ = 6,
6168 off = 2,
6169 p2align = 1,
6170 timeout = 10,
6171 val = 4,
6172 vec = 8,
6173 OPERAND_LAST
6174};
6175} // end namespace OpName
6176} // end namespace WebAssembly
6177} // end namespace llvm
6178#endif //GET_INSTRINFO_OPERAND_ENUM
6179
6180#ifdef GET_INSTRINFO_NAMED_OPS
6181#undef GET_INSTRINFO_NAMED_OPS
6182namespace llvm {
6183namespace WebAssembly {
6184LLVM_READONLY
6185int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
6186 static const int16_t OperandMap [][11] = {
6187{0, 1, 2, 3, -1, -1, -1, -1, -1, -1, -1, },
6188{0, 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, },
6189{0, 1, 2, 3, -1, 4, 5, -1, -1, -1, -1, },
6190{0, 1, 2, 3, -1, 4, -1, -1, -1, -1, 5, },
6191{0, 1, 2, 3, -1, -1, -1, -1, -1, 4, -1, },
6192{0, 1, 2, 4, -1, -1, -1, 3, 5, -1, -1, },
6193{-1, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, },
6194{-1, 0, 1, 2, 3, -1, -1, -1, -1, -1, -1, },
6195{-1, 0, 1, 2, -1, -1, -1, -1, 3, -1, -1, },
6196{-1, 0, 1, 3, -1, -1, -1, 2, 4, -1, -1, },
6197{-1, 0, 1, -1, -1, -1, -1, 2, -1, -1, -1, },
6198};
6199 switch(Opcode) {
6200 case WebAssembly::ATOMIC_LOAD16_U_I32_A32:
6201 case WebAssembly::ATOMIC_LOAD16_U_I32_A64:
6202 case WebAssembly::ATOMIC_LOAD16_U_I64_A32:
6203 case WebAssembly::ATOMIC_LOAD16_U_I64_A64:
6204 case WebAssembly::ATOMIC_LOAD32_U_I64_A32:
6205 case WebAssembly::ATOMIC_LOAD32_U_I64_A64:
6206 case WebAssembly::ATOMIC_LOAD8_U_I32_A32:
6207 case WebAssembly::ATOMIC_LOAD8_U_I32_A64:
6208 case WebAssembly::ATOMIC_LOAD8_U_I64_A32:
6209 case WebAssembly::ATOMIC_LOAD8_U_I64_A64:
6210 case WebAssembly::ATOMIC_LOAD_I32_A32:
6211 case WebAssembly::ATOMIC_LOAD_I32_A64:
6212 case WebAssembly::ATOMIC_LOAD_I64_A32:
6213 case WebAssembly::ATOMIC_LOAD_I64_A64:
6214 case WebAssembly::LOAD16_SPLAT_A32:
6215 case WebAssembly::LOAD16_SPLAT_A64:
6216 case WebAssembly::LOAD16_S_I32_A32:
6217 case WebAssembly::LOAD16_S_I32_A64:
6218 case WebAssembly::LOAD16_S_I64_A32:
6219 case WebAssembly::LOAD16_S_I64_A64:
6220 case WebAssembly::LOAD16_U_I32_A32:
6221 case WebAssembly::LOAD16_U_I32_A64:
6222 case WebAssembly::LOAD16_U_I64_A32:
6223 case WebAssembly::LOAD16_U_I64_A64:
6224 case WebAssembly::LOAD32_SPLAT_A32:
6225 case WebAssembly::LOAD32_SPLAT_A64:
6226 case WebAssembly::LOAD32_S_I64_A32:
6227 case WebAssembly::LOAD32_S_I64_A64:
6228 case WebAssembly::LOAD32_U_I64_A32:
6229 case WebAssembly::LOAD32_U_I64_A64:
6230 case WebAssembly::LOAD64_SPLAT_A32:
6231 case WebAssembly::LOAD64_SPLAT_A64:
6232 case WebAssembly::LOAD8_SPLAT_A32:
6233 case WebAssembly::LOAD8_SPLAT_A64:
6234 case WebAssembly::LOAD8_S_I32_A32:
6235 case WebAssembly::LOAD8_S_I32_A64:
6236 case WebAssembly::LOAD8_S_I64_A32:
6237 case WebAssembly::LOAD8_S_I64_A64:
6238 case WebAssembly::LOAD8_U_I32_A32:
6239 case WebAssembly::LOAD8_U_I32_A64:
6240 case WebAssembly::LOAD8_U_I64_A32:
6241 case WebAssembly::LOAD8_U_I64_A64:
6242 case WebAssembly::LOAD_EXTEND_S_I16x8_A32:
6243 case WebAssembly::LOAD_EXTEND_S_I16x8_A64:
6244 case WebAssembly::LOAD_EXTEND_S_I32x4_A32:
6245 case WebAssembly::LOAD_EXTEND_S_I32x4_A64:
6246 case WebAssembly::LOAD_EXTEND_S_I64x2_A32:
6247 case WebAssembly::LOAD_EXTEND_S_I64x2_A64:
6248 case WebAssembly::LOAD_EXTEND_U_I16x8_A32:
6249 case WebAssembly::LOAD_EXTEND_U_I16x8_A64:
6250 case WebAssembly::LOAD_EXTEND_U_I32x4_A32:
6251 case WebAssembly::LOAD_EXTEND_U_I32x4_A64:
6252 case WebAssembly::LOAD_EXTEND_U_I64x2_A32:
6253 case WebAssembly::LOAD_EXTEND_U_I64x2_A64:
6254 case WebAssembly::LOAD_F16_F32_A32:
6255 case WebAssembly::LOAD_F16_F32_A64:
6256 case WebAssembly::LOAD_F32_A32:
6257 case WebAssembly::LOAD_F32_A64:
6258 case WebAssembly::LOAD_F64_A32:
6259 case WebAssembly::LOAD_F64_A64:
6260 case WebAssembly::LOAD_I32_A32:
6261 case WebAssembly::LOAD_I32_A64:
6262 case WebAssembly::LOAD_I64_A32:
6263 case WebAssembly::LOAD_I64_A64:
6264 case WebAssembly::LOAD_V128_A32:
6265 case WebAssembly::LOAD_V128_A64:
6266 case WebAssembly::LOAD_ZERO_I32x4_A32:
6267 case WebAssembly::LOAD_ZERO_I32x4_A64:
6268 case WebAssembly::LOAD_ZERO_I64x2_A32:
6269 case WebAssembly::LOAD_ZERO_I64x2_A64:
6270 return OperandMap[0][NamedIdx];
6271 case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32:
6272 case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64:
6273 case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32:
6274 case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64:
6275 case WebAssembly::ATOMIC_RMW16_U_AND_I32_A32:
6276 case WebAssembly::ATOMIC_RMW16_U_AND_I32_A64:
6277 case WebAssembly::ATOMIC_RMW16_U_AND_I64_A32:
6278 case WebAssembly::ATOMIC_RMW16_U_AND_I64_A64:
6279 case WebAssembly::ATOMIC_RMW16_U_OR_I32_A32:
6280 case WebAssembly::ATOMIC_RMW16_U_OR_I32_A64:
6281 case WebAssembly::ATOMIC_RMW16_U_OR_I64_A32:
6282 case WebAssembly::ATOMIC_RMW16_U_OR_I64_A64:
6283 case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32:
6284 case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64:
6285 case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32:
6286 case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64:
6287 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32:
6288 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64:
6289 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32:
6290 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64:
6291 case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32:
6292 case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64:
6293 case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32:
6294 case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64:
6295 case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32:
6296 case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64:
6297 case WebAssembly::ATOMIC_RMW32_U_AND_I64_A32:
6298 case WebAssembly::ATOMIC_RMW32_U_AND_I64_A64:
6299 case WebAssembly::ATOMIC_RMW32_U_OR_I64_A32:
6300 case WebAssembly::ATOMIC_RMW32_U_OR_I64_A64:
6301 case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32:
6302 case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64:
6303 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32:
6304 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64:
6305 case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32:
6306 case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64:
6307 case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32:
6308 case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64:
6309 case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32:
6310 case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64:
6311 case WebAssembly::ATOMIC_RMW8_U_AND_I32_A32:
6312 case WebAssembly::ATOMIC_RMW8_U_AND_I32_A64:
6313 case WebAssembly::ATOMIC_RMW8_U_AND_I64_A32:
6314 case WebAssembly::ATOMIC_RMW8_U_AND_I64_A64:
6315 case WebAssembly::ATOMIC_RMW8_U_OR_I32_A32:
6316 case WebAssembly::ATOMIC_RMW8_U_OR_I32_A64:
6317 case WebAssembly::ATOMIC_RMW8_U_OR_I64_A32:
6318 case WebAssembly::ATOMIC_RMW8_U_OR_I64_A64:
6319 case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32:
6320 case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64:
6321 case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32:
6322 case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64:
6323 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32:
6324 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64:
6325 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32:
6326 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64:
6327 case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32:
6328 case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64:
6329 case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32:
6330 case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64:
6331 case WebAssembly::ATOMIC_RMW_ADD_I32_A32:
6332 case WebAssembly::ATOMIC_RMW_ADD_I32_A64:
6333 case WebAssembly::ATOMIC_RMW_ADD_I64_A32:
6334 case WebAssembly::ATOMIC_RMW_ADD_I64_A64:
6335 case WebAssembly::ATOMIC_RMW_AND_I32_A32:
6336 case WebAssembly::ATOMIC_RMW_AND_I32_A64:
6337 case WebAssembly::ATOMIC_RMW_AND_I64_A32:
6338 case WebAssembly::ATOMIC_RMW_AND_I64_A64:
6339 case WebAssembly::ATOMIC_RMW_OR_I32_A32:
6340 case WebAssembly::ATOMIC_RMW_OR_I32_A64:
6341 case WebAssembly::ATOMIC_RMW_OR_I64_A32:
6342 case WebAssembly::ATOMIC_RMW_OR_I64_A64:
6343 case WebAssembly::ATOMIC_RMW_SUB_I32_A32:
6344 case WebAssembly::ATOMIC_RMW_SUB_I32_A64:
6345 case WebAssembly::ATOMIC_RMW_SUB_I64_A32:
6346 case WebAssembly::ATOMIC_RMW_SUB_I64_A64:
6347 case WebAssembly::ATOMIC_RMW_XCHG_I32_A32:
6348 case WebAssembly::ATOMIC_RMW_XCHG_I32_A64:
6349 case WebAssembly::ATOMIC_RMW_XCHG_I64_A32:
6350 case WebAssembly::ATOMIC_RMW_XCHG_I64_A64:
6351 case WebAssembly::ATOMIC_RMW_XOR_I32_A32:
6352 case WebAssembly::ATOMIC_RMW_XOR_I32_A64:
6353 case WebAssembly::ATOMIC_RMW_XOR_I64_A32:
6354 case WebAssembly::ATOMIC_RMW_XOR_I64_A64:
6355 return OperandMap[1][NamedIdx];
6356 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32:
6357 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64:
6358 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32:
6359 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64:
6360 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32:
6361 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64:
6362 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32:
6363 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64:
6364 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32:
6365 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64:
6366 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32:
6367 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64:
6368 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32:
6369 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64:
6370 return OperandMap[2][NamedIdx];
6371 case WebAssembly::MEMORY_ATOMIC_WAIT32_A32:
6372 case WebAssembly::MEMORY_ATOMIC_WAIT32_A64:
6373 case WebAssembly::MEMORY_ATOMIC_WAIT64_A32:
6374 case WebAssembly::MEMORY_ATOMIC_WAIT64_A64:
6375 return OperandMap[3][NamedIdx];
6376 case WebAssembly::MEMORY_ATOMIC_NOTIFY_A32:
6377 case WebAssembly::MEMORY_ATOMIC_NOTIFY_A64:
6378 return OperandMap[4][NamedIdx];
6379 case WebAssembly::LOAD_LANE_I16x8_A32:
6380 case WebAssembly::LOAD_LANE_I16x8_A64:
6381 case WebAssembly::LOAD_LANE_I32x4_A32:
6382 case WebAssembly::LOAD_LANE_I32x4_A64:
6383 case WebAssembly::LOAD_LANE_I64x2_A32:
6384 case WebAssembly::LOAD_LANE_I64x2_A64:
6385 case WebAssembly::LOAD_LANE_I8x16_A32:
6386 case WebAssembly::LOAD_LANE_I8x16_A64:
6387 return OperandMap[5][NamedIdx];
6388 case WebAssembly::ATOMIC_LOAD16_U_I32_A32_S:
6389 case WebAssembly::ATOMIC_LOAD16_U_I32_A64_S:
6390 case WebAssembly::ATOMIC_LOAD16_U_I64_A32_S:
6391 case WebAssembly::ATOMIC_LOAD16_U_I64_A64_S:
6392 case WebAssembly::ATOMIC_LOAD32_U_I64_A32_S:
6393 case WebAssembly::ATOMIC_LOAD32_U_I64_A64_S:
6394 case WebAssembly::ATOMIC_LOAD8_U_I32_A32_S:
6395 case WebAssembly::ATOMIC_LOAD8_U_I32_A64_S:
6396 case WebAssembly::ATOMIC_LOAD8_U_I64_A32_S:
6397 case WebAssembly::ATOMIC_LOAD8_U_I64_A64_S:
6398 case WebAssembly::ATOMIC_LOAD_I32_A32_S:
6399 case WebAssembly::ATOMIC_LOAD_I32_A64_S:
6400 case WebAssembly::ATOMIC_LOAD_I64_A32_S:
6401 case WebAssembly::ATOMIC_LOAD_I64_A64_S:
6402 case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32_S:
6403 case WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64_S:
6404 case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32_S:
6405 case WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64_S:
6406 case WebAssembly::ATOMIC_RMW16_U_AND_I32_A32_S:
6407 case WebAssembly::ATOMIC_RMW16_U_AND_I32_A64_S:
6408 case WebAssembly::ATOMIC_RMW16_U_AND_I64_A32_S:
6409 case WebAssembly::ATOMIC_RMW16_U_AND_I64_A64_S:
6410 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32_S:
6411 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64_S:
6412 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32_S:
6413 case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64_S:
6414 case WebAssembly::ATOMIC_RMW16_U_OR_I32_A32_S:
6415 case WebAssembly::ATOMIC_RMW16_U_OR_I32_A64_S:
6416 case WebAssembly::ATOMIC_RMW16_U_OR_I64_A32_S:
6417 case WebAssembly::ATOMIC_RMW16_U_OR_I64_A64_S:
6418 case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32_S:
6419 case WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64_S:
6420 case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32_S:
6421 case WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64_S:
6422 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32_S:
6423 case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64_S:
6424 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32_S:
6425 case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64_S:
6426 case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32_S:
6427 case WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64_S:
6428 case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32_S:
6429 case WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64_S:
6430 case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32_S:
6431 case WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64_S:
6432 case WebAssembly::ATOMIC_RMW32_U_AND_I64_A32_S:
6433 case WebAssembly::ATOMIC_RMW32_U_AND_I64_A64_S:
6434 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32_S:
6435 case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64_S:
6436 case WebAssembly::ATOMIC_RMW32_U_OR_I64_A32_S:
6437 case WebAssembly::ATOMIC_RMW32_U_OR_I64_A64_S:
6438 case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32_S:
6439 case WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64_S:
6440 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32_S:
6441 case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64_S:
6442 case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32_S:
6443 case WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64_S:
6444 case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32_S:
6445 case WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64_S:
6446 case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32_S:
6447 case WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64_S:
6448 case WebAssembly::ATOMIC_RMW8_U_AND_I32_A32_S:
6449 case WebAssembly::ATOMIC_RMW8_U_AND_I32_A64_S:
6450 case WebAssembly::ATOMIC_RMW8_U_AND_I64_A32_S:
6451 case WebAssembly::ATOMIC_RMW8_U_AND_I64_A64_S:
6452 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32_S:
6453 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64_S:
6454 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32_S:
6455 case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64_S:
6456 case WebAssembly::ATOMIC_RMW8_U_OR_I32_A32_S:
6457 case WebAssembly::ATOMIC_RMW8_U_OR_I32_A64_S:
6458 case WebAssembly::ATOMIC_RMW8_U_OR_I64_A32_S:
6459 case WebAssembly::ATOMIC_RMW8_U_OR_I64_A64_S:
6460 case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32_S:
6461 case WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64_S:
6462 case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32_S:
6463 case WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64_S:
6464 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32_S:
6465 case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64_S:
6466 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32_S:
6467 case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64_S:
6468 case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32_S:
6469 case WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64_S:
6470 case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32_S:
6471 case WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64_S:
6472 case WebAssembly::ATOMIC_RMW_ADD_I32_A32_S:
6473 case WebAssembly::ATOMIC_RMW_ADD_I32_A64_S:
6474 case WebAssembly::ATOMIC_RMW_ADD_I64_A32_S:
6475 case WebAssembly::ATOMIC_RMW_ADD_I64_A64_S:
6476 case WebAssembly::ATOMIC_RMW_AND_I32_A32_S:
6477 case WebAssembly::ATOMIC_RMW_AND_I32_A64_S:
6478 case WebAssembly::ATOMIC_RMW_AND_I64_A32_S:
6479 case WebAssembly::ATOMIC_RMW_AND_I64_A64_S:
6480 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32_S:
6481 case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64_S:
6482 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32_S:
6483 case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64_S:
6484 case WebAssembly::ATOMIC_RMW_OR_I32_A32_S:
6485 case WebAssembly::ATOMIC_RMW_OR_I32_A64_S:
6486 case WebAssembly::ATOMIC_RMW_OR_I64_A32_S:
6487 case WebAssembly::ATOMIC_RMW_OR_I64_A64_S:
6488 case WebAssembly::ATOMIC_RMW_SUB_I32_A32_S:
6489 case WebAssembly::ATOMIC_RMW_SUB_I32_A64_S:
6490 case WebAssembly::ATOMIC_RMW_SUB_I64_A32_S:
6491 case WebAssembly::ATOMIC_RMW_SUB_I64_A64_S:
6492 case WebAssembly::ATOMIC_RMW_XCHG_I32_A32_S:
6493 case WebAssembly::ATOMIC_RMW_XCHG_I32_A64_S:
6494 case WebAssembly::ATOMIC_RMW_XCHG_I64_A32_S:
6495 case WebAssembly::ATOMIC_RMW_XCHG_I64_A64_S:
6496 case WebAssembly::ATOMIC_RMW_XOR_I32_A32_S:
6497 case WebAssembly::ATOMIC_RMW_XOR_I32_A64_S:
6498 case WebAssembly::ATOMIC_RMW_XOR_I64_A32_S:
6499 case WebAssembly::ATOMIC_RMW_XOR_I64_A64_S:
6500 case WebAssembly::ATOMIC_STORE16_I32_A32_S:
6501 case WebAssembly::ATOMIC_STORE16_I32_A64_S:
6502 case WebAssembly::ATOMIC_STORE16_I64_A32_S:
6503 case WebAssembly::ATOMIC_STORE16_I64_A64_S:
6504 case WebAssembly::ATOMIC_STORE32_I64_A32_S:
6505 case WebAssembly::ATOMIC_STORE32_I64_A64_S:
6506 case WebAssembly::ATOMIC_STORE8_I32_A32_S:
6507 case WebAssembly::ATOMIC_STORE8_I32_A64_S:
6508 case WebAssembly::ATOMIC_STORE8_I64_A32_S:
6509 case WebAssembly::ATOMIC_STORE8_I64_A64_S:
6510 case WebAssembly::ATOMIC_STORE_I32_A32_S:
6511 case WebAssembly::ATOMIC_STORE_I32_A64_S:
6512 case WebAssembly::ATOMIC_STORE_I64_A32_S:
6513 case WebAssembly::ATOMIC_STORE_I64_A64_S:
6514 case WebAssembly::LOAD16_SPLAT_A32_S:
6515 case WebAssembly::LOAD16_SPLAT_A64_S:
6516 case WebAssembly::LOAD16_S_I32_A32_S:
6517 case WebAssembly::LOAD16_S_I32_A64_S:
6518 case WebAssembly::LOAD16_S_I64_A32_S:
6519 case WebAssembly::LOAD16_S_I64_A64_S:
6520 case WebAssembly::LOAD16_U_I32_A32_S:
6521 case WebAssembly::LOAD16_U_I32_A64_S:
6522 case WebAssembly::LOAD16_U_I64_A32_S:
6523 case WebAssembly::LOAD16_U_I64_A64_S:
6524 case WebAssembly::LOAD32_SPLAT_A32_S:
6525 case WebAssembly::LOAD32_SPLAT_A64_S:
6526 case WebAssembly::LOAD32_S_I64_A32_S:
6527 case WebAssembly::LOAD32_S_I64_A64_S:
6528 case WebAssembly::LOAD32_U_I64_A32_S:
6529 case WebAssembly::LOAD32_U_I64_A64_S:
6530 case WebAssembly::LOAD64_SPLAT_A32_S:
6531 case WebAssembly::LOAD64_SPLAT_A64_S:
6532 case WebAssembly::LOAD8_SPLAT_A32_S:
6533 case WebAssembly::LOAD8_SPLAT_A64_S:
6534 case WebAssembly::LOAD8_S_I32_A32_S:
6535 case WebAssembly::LOAD8_S_I32_A64_S:
6536 case WebAssembly::LOAD8_S_I64_A32_S:
6537 case WebAssembly::LOAD8_S_I64_A64_S:
6538 case WebAssembly::LOAD8_U_I32_A32_S:
6539 case WebAssembly::LOAD8_U_I32_A64_S:
6540 case WebAssembly::LOAD8_U_I64_A32_S:
6541 case WebAssembly::LOAD8_U_I64_A64_S:
6542 case WebAssembly::LOAD_EXTEND_S_I16x8_A32_S:
6543 case WebAssembly::LOAD_EXTEND_S_I16x8_A64_S:
6544 case WebAssembly::LOAD_EXTEND_S_I32x4_A32_S:
6545 case WebAssembly::LOAD_EXTEND_S_I32x4_A64_S:
6546 case WebAssembly::LOAD_EXTEND_S_I64x2_A32_S:
6547 case WebAssembly::LOAD_EXTEND_S_I64x2_A64_S:
6548 case WebAssembly::LOAD_EXTEND_U_I16x8_A32_S:
6549 case WebAssembly::LOAD_EXTEND_U_I16x8_A64_S:
6550 case WebAssembly::LOAD_EXTEND_U_I32x4_A32_S:
6551 case WebAssembly::LOAD_EXTEND_U_I32x4_A64_S:
6552 case WebAssembly::LOAD_EXTEND_U_I64x2_A32_S:
6553 case WebAssembly::LOAD_EXTEND_U_I64x2_A64_S:
6554 case WebAssembly::LOAD_F16_F32_A32_S:
6555 case WebAssembly::LOAD_F16_F32_A64_S:
6556 case WebAssembly::LOAD_F32_A32_S:
6557 case WebAssembly::LOAD_F32_A64_S:
6558 case WebAssembly::LOAD_F64_A32_S:
6559 case WebAssembly::LOAD_F64_A64_S:
6560 case WebAssembly::LOAD_I32_A32_S:
6561 case WebAssembly::LOAD_I32_A64_S:
6562 case WebAssembly::LOAD_I64_A32_S:
6563 case WebAssembly::LOAD_I64_A64_S:
6564 case WebAssembly::LOAD_V128_A32_S:
6565 case WebAssembly::LOAD_V128_A64_S:
6566 case WebAssembly::LOAD_ZERO_I32x4_A32_S:
6567 case WebAssembly::LOAD_ZERO_I32x4_A64_S:
6568 case WebAssembly::LOAD_ZERO_I64x2_A32_S:
6569 case WebAssembly::LOAD_ZERO_I64x2_A64_S:
6570 case WebAssembly::MEMORY_ATOMIC_NOTIFY_A32_S:
6571 case WebAssembly::MEMORY_ATOMIC_NOTIFY_A64_S:
6572 case WebAssembly::MEMORY_ATOMIC_WAIT32_A32_S:
6573 case WebAssembly::MEMORY_ATOMIC_WAIT32_A64_S:
6574 case WebAssembly::MEMORY_ATOMIC_WAIT64_A32_S:
6575 case WebAssembly::MEMORY_ATOMIC_WAIT64_A64_S:
6576 case WebAssembly::STORE16_I32_A32_S:
6577 case WebAssembly::STORE16_I32_A64_S:
6578 case WebAssembly::STORE16_I64_A32_S:
6579 case WebAssembly::STORE16_I64_A64_S:
6580 case WebAssembly::STORE32_I64_A32_S:
6581 case WebAssembly::STORE32_I64_A64_S:
6582 case WebAssembly::STORE8_I32_A32_S:
6583 case WebAssembly::STORE8_I32_A64_S:
6584 case WebAssembly::STORE8_I64_A32_S:
6585 case WebAssembly::STORE8_I64_A64_S:
6586 case WebAssembly::STORE_F16_F32_A32_S:
6587 case WebAssembly::STORE_F16_F32_A64_S:
6588 case WebAssembly::STORE_F32_A32_S:
6589 case WebAssembly::STORE_F32_A64_S:
6590 case WebAssembly::STORE_F64_A32_S:
6591 case WebAssembly::STORE_F64_A64_S:
6592 case WebAssembly::STORE_I32_A32_S:
6593 case WebAssembly::STORE_I32_A64_S:
6594 case WebAssembly::STORE_I64_A32_S:
6595 case WebAssembly::STORE_I64_A64_S:
6596 case WebAssembly::STORE_V128_A32_S:
6597 case WebAssembly::STORE_V128_A64_S:
6598 return OperandMap[6][NamedIdx];
6599 case WebAssembly::ATOMIC_STORE16_I32_A32:
6600 case WebAssembly::ATOMIC_STORE16_I32_A64:
6601 case WebAssembly::ATOMIC_STORE16_I64_A32:
6602 case WebAssembly::ATOMIC_STORE16_I64_A64:
6603 case WebAssembly::ATOMIC_STORE32_I64_A32:
6604 case WebAssembly::ATOMIC_STORE32_I64_A64:
6605 case WebAssembly::ATOMIC_STORE8_I32_A32:
6606 case WebAssembly::ATOMIC_STORE8_I32_A64:
6607 case WebAssembly::ATOMIC_STORE8_I64_A32:
6608 case WebAssembly::ATOMIC_STORE8_I64_A64:
6609 case WebAssembly::ATOMIC_STORE_I32_A32:
6610 case WebAssembly::ATOMIC_STORE_I32_A64:
6611 case WebAssembly::ATOMIC_STORE_I64_A32:
6612 case WebAssembly::ATOMIC_STORE_I64_A64:
6613 case WebAssembly::STORE16_I32_A32:
6614 case WebAssembly::STORE16_I32_A64:
6615 case WebAssembly::STORE16_I64_A32:
6616 case WebAssembly::STORE16_I64_A64:
6617 case WebAssembly::STORE32_I64_A32:
6618 case WebAssembly::STORE32_I64_A64:
6619 case WebAssembly::STORE8_I32_A32:
6620 case WebAssembly::STORE8_I32_A64:
6621 case WebAssembly::STORE8_I64_A32:
6622 case WebAssembly::STORE8_I64_A64:
6623 case WebAssembly::STORE_F16_F32_A32:
6624 case WebAssembly::STORE_F16_F32_A64:
6625 case WebAssembly::STORE_F32_A32:
6626 case WebAssembly::STORE_F32_A64:
6627 case WebAssembly::STORE_F64_A32:
6628 case WebAssembly::STORE_F64_A64:
6629 case WebAssembly::STORE_I32_A32:
6630 case WebAssembly::STORE_I32_A64:
6631 case WebAssembly::STORE_I64_A32:
6632 case WebAssembly::STORE_I64_A64:
6633 return OperandMap[7][NamedIdx];
6634 case WebAssembly::STORE_V128_A32:
6635 case WebAssembly::STORE_V128_A64:
6636 return OperandMap[8][NamedIdx];
6637 case WebAssembly::STORE_LANE_I16x8_A32:
6638 case WebAssembly::STORE_LANE_I16x8_A64:
6639 case WebAssembly::STORE_LANE_I32x4_A32:
6640 case WebAssembly::STORE_LANE_I32x4_A64:
6641 case WebAssembly::STORE_LANE_I64x2_A32:
6642 case WebAssembly::STORE_LANE_I64x2_A64:
6643 case WebAssembly::STORE_LANE_I8x16_A32:
6644 case WebAssembly::STORE_LANE_I8x16_A64:
6645 return OperandMap[9][NamedIdx];
6646 case WebAssembly::LOAD_LANE_I16x8_A32_S:
6647 case WebAssembly::LOAD_LANE_I16x8_A64_S:
6648 case WebAssembly::LOAD_LANE_I32x4_A32_S:
6649 case WebAssembly::LOAD_LANE_I32x4_A64_S:
6650 case WebAssembly::LOAD_LANE_I64x2_A32_S:
6651 case WebAssembly::LOAD_LANE_I64x2_A64_S:
6652 case WebAssembly::LOAD_LANE_I8x16_A32_S:
6653 case WebAssembly::LOAD_LANE_I8x16_A64_S:
6654 case WebAssembly::STORE_LANE_I16x8_A32_S:
6655 case WebAssembly::STORE_LANE_I16x8_A64_S:
6656 case WebAssembly::STORE_LANE_I32x4_A32_S:
6657 case WebAssembly::STORE_LANE_I32x4_A64_S:
6658 case WebAssembly::STORE_LANE_I64x2_A32_S:
6659 case WebAssembly::STORE_LANE_I64x2_A64_S:
6660 case WebAssembly::STORE_LANE_I8x16_A32_S:
6661 case WebAssembly::STORE_LANE_I8x16_A64_S:
6662 return OperandMap[10][NamedIdx];
6663 default: return -1;
6664 }
6665}
6666} // end namespace WebAssembly
6667} // end namespace llvm
6668#endif //GET_INSTRINFO_NAMED_OPS
6669
6670#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
6671#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
6672namespace llvm {
6673namespace WebAssembly {
6674namespace OpTypes {
6675enum OperandType {
6676 P2Align = 0,
6677 Signature = 1,
6678 TypeIndex = 2,
6679 bb_op = 3,
6680 brlist = 4,
6681 f32imm = 5,
6682 f32imm_op = 6,
6683 f64imm = 7,
6684 f64imm_op = 8,
6685 function32_op = 9,
6686 global_op32 = 10,
6687 global_op64 = 11,
6688 i1imm = 12,
6689 i8imm = 13,
6690 i16imm = 14,
6691 i32imm = 15,
6692 i32imm_op = 16,
6693 i64imm = 17,
6694 i64imm_op = 18,
6695 local_op = 19,
6696 offset32_op = 20,
6697 offset64_op = 21,
6698 ptype0 = 22,
6699 ptype1 = 23,
6700 ptype2 = 24,
6701 ptype3 = 25,
6702 ptype4 = 26,
6703 ptype5 = 27,
6704 table32_op = 28,
6705 tag_op = 29,
6706 type0 = 30,
6707 type1 = 31,
6708 type2 = 32,
6709 type3 = 33,
6710 type4 = 34,
6711 type5 = 35,
6712 untyped_imm_0 = 36,
6713 vec_i8imm_op = 37,
6714 vec_i16imm_op = 38,
6715 vec_i32imm_op = 39,
6716 vec_i64imm_op = 40,
6717 EXNREF = 41,
6718 EXTERNREF = 42,
6719 F32 = 43,
6720 F64 = 44,
6721 FUNCREF = 45,
6722 I32 = 46,
6723 I64 = 47,
6724 V128 = 48,
6725 OPERAND_TYPE_LIST_END
6726};
6727} // end namespace OpTypes
6728} // end namespace WebAssembly
6729} // end namespace llvm
6730#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
6731
6732#ifdef GET_INSTRINFO_OPERAND_TYPE
6733#undef GET_INSTRINFO_OPERAND_TYPE
6734namespace llvm {
6735namespace WebAssembly {
6736LLVM_READONLY
6737static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
6738 static const uint16_t Offsets[] = {
6739 /* PHI */
6740 0,
6741 /* INLINEASM */
6742 1,
6743 /* INLINEASM_BR */
6744 1,
6745 /* CFI_INSTRUCTION */
6746 1,
6747 /* EH_LABEL */
6748 2,
6749 /* GC_LABEL */
6750 3,
6751 /* ANNOTATION_LABEL */
6752 4,
6753 /* KILL */
6754 5,
6755 /* EXTRACT_SUBREG */
6756 5,
6757 /* INSERT_SUBREG */
6758 8,
6759 /* IMPLICIT_DEF */
6760 12,
6761 /* SUBREG_TO_REG */
6762 13,
6763 /* COPY_TO_REGCLASS */
6764 17,
6765 /* DBG_VALUE */
6766 20,
6767 /* DBG_VALUE_LIST */
6768 20,
6769 /* DBG_INSTR_REF */
6770 20,
6771 /* DBG_PHI */
6772 20,
6773 /* DBG_LABEL */
6774 20,
6775 /* REG_SEQUENCE */
6776 21,
6777 /* COPY */
6778 23,
6779 /* BUNDLE */
6780 25,
6781 /* LIFETIME_START */
6782 25,
6783 /* LIFETIME_END */
6784 26,
6785 /* PSEUDO_PROBE */
6786 27,
6787 /* ARITH_FENCE */
6788 31,
6789 /* STACKMAP */
6790 33,
6791 /* FENTRY_CALL */
6792 35,
6793 /* PATCHPOINT */
6794 35,
6795 /* LOAD_STACK_GUARD */
6796 41,
6797 /* PREALLOCATED_SETUP */
6798 42,
6799 /* PREALLOCATED_ARG */
6800 43,
6801 /* STATEPOINT */
6802 46,
6803 /* LOCAL_ESCAPE */
6804 46,
6805 /* FAULTING_OP */
6806 48,
6807 /* PATCHABLE_OP */
6808 49,
6809 /* PATCHABLE_FUNCTION_ENTER */
6810 49,
6811 /* PATCHABLE_RET */
6812 49,
6813 /* PATCHABLE_FUNCTION_EXIT */
6814 49,
6815 /* PATCHABLE_TAIL_CALL */
6816 49,
6817 /* PATCHABLE_EVENT_CALL */
6818 49,
6819 /* PATCHABLE_TYPED_EVENT_CALL */
6820 51,
6821 /* ICALL_BRANCH_FUNNEL */
6822 54,
6823 /* MEMBARRIER */
6824 54,
6825 /* JUMP_TABLE_DEBUG_INFO */
6826 54,
6827 /* CONVERGENCECTRL_ENTRY */
6828 55,
6829 /* CONVERGENCECTRL_ANCHOR */
6830 56,
6831 /* CONVERGENCECTRL_LOOP */
6832 57,
6833 /* CONVERGENCECTRL_GLUE */
6834 59,
6835 /* G_ASSERT_SEXT */
6836 60,
6837 /* G_ASSERT_ZEXT */
6838 63,
6839 /* G_ASSERT_ALIGN */
6840 66,
6841 /* G_ADD */
6842 69,
6843 /* G_SUB */
6844 72,
6845 /* G_MUL */
6846 75,
6847 /* G_SDIV */
6848 78,
6849 /* G_UDIV */
6850 81,
6851 /* G_SREM */
6852 84,
6853 /* G_UREM */
6854 87,
6855 /* G_SDIVREM */
6856 90,
6857 /* G_UDIVREM */
6858 94,
6859 /* G_AND */
6860 98,
6861 /* G_OR */
6862 101,
6863 /* G_XOR */
6864 104,
6865 /* G_IMPLICIT_DEF */
6866 107,
6867 /* G_PHI */
6868 108,
6869 /* G_FRAME_INDEX */
6870 109,
6871 /* G_GLOBAL_VALUE */
6872 111,
6873 /* G_PTRAUTH_GLOBAL_VALUE */
6874 113,
6875 /* G_CONSTANT_POOL */
6876 118,
6877 /* G_EXTRACT */
6878 120,
6879 /* G_UNMERGE_VALUES */
6880 123,
6881 /* G_INSERT */
6882 125,
6883 /* G_MERGE_VALUES */
6884 129,
6885 /* G_BUILD_VECTOR */
6886 131,
6887 /* G_BUILD_VECTOR_TRUNC */
6888 133,
6889 /* G_CONCAT_VECTORS */
6890 135,
6891 /* G_PTRTOINT */
6892 137,
6893 /* G_INTTOPTR */
6894 139,
6895 /* G_BITCAST */
6896 141,
6897 /* G_FREEZE */
6898 143,
6899 /* G_CONSTANT_FOLD_BARRIER */
6900 145,
6901 /* G_INTRINSIC_FPTRUNC_ROUND */
6902 147,
6903 /* G_INTRINSIC_TRUNC */
6904 150,
6905 /* G_INTRINSIC_ROUND */
6906 152,
6907 /* G_INTRINSIC_LRINT */
6908 154,
6909 /* G_INTRINSIC_LLRINT */
6910 156,
6911 /* G_INTRINSIC_ROUNDEVEN */
6912 158,
6913 /* G_READCYCLECOUNTER */
6914 160,
6915 /* G_READSTEADYCOUNTER */
6916 161,
6917 /* G_LOAD */
6918 162,
6919 /* G_SEXTLOAD */
6920 164,
6921 /* G_ZEXTLOAD */
6922 166,
6923 /* G_INDEXED_LOAD */
6924 168,
6925 /* G_INDEXED_SEXTLOAD */
6926 173,
6927 /* G_INDEXED_ZEXTLOAD */
6928 178,
6929 /* G_STORE */
6930 183,
6931 /* G_INDEXED_STORE */
6932 185,
6933 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
6934 190,
6935 /* G_ATOMIC_CMPXCHG */
6936 195,
6937 /* G_ATOMICRMW_XCHG */
6938 199,
6939 /* G_ATOMICRMW_ADD */
6940 202,
6941 /* G_ATOMICRMW_SUB */
6942 205,
6943 /* G_ATOMICRMW_AND */
6944 208,
6945 /* G_ATOMICRMW_NAND */
6946 211,
6947 /* G_ATOMICRMW_OR */
6948 214,
6949 /* G_ATOMICRMW_XOR */
6950 217,
6951 /* G_ATOMICRMW_MAX */
6952 220,
6953 /* G_ATOMICRMW_MIN */
6954 223,
6955 /* G_ATOMICRMW_UMAX */
6956 226,
6957 /* G_ATOMICRMW_UMIN */
6958 229,
6959 /* G_ATOMICRMW_FADD */
6960 232,
6961 /* G_ATOMICRMW_FSUB */
6962 235,
6963 /* G_ATOMICRMW_FMAX */
6964 238,
6965 /* G_ATOMICRMW_FMIN */
6966 241,
6967 /* G_ATOMICRMW_UINC_WRAP */
6968 244,
6969 /* G_ATOMICRMW_UDEC_WRAP */
6970 247,
6971 /* G_FENCE */
6972 250,
6973 /* G_PREFETCH */
6974 252,
6975 /* G_BRCOND */
6976 256,
6977 /* G_BRINDIRECT */
6978 258,
6979 /* G_INVOKE_REGION_START */
6980 259,
6981 /* G_INTRINSIC */
6982 259,
6983 /* G_INTRINSIC_W_SIDE_EFFECTS */
6984 260,
6985 /* G_INTRINSIC_CONVERGENT */
6986 261,
6987 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
6988 262,
6989 /* G_ANYEXT */
6990 263,
6991 /* G_TRUNC */
6992 265,
6993 /* G_CONSTANT */
6994 267,
6995 /* G_FCONSTANT */
6996 269,
6997 /* G_VASTART */
6998 271,
6999 /* G_VAARG */
7000 272,
7001 /* G_SEXT */
7002 275,
7003 /* G_SEXT_INREG */
7004 277,
7005 /* G_ZEXT */
7006 280,
7007 /* G_SHL */
7008 282,
7009 /* G_LSHR */
7010 285,
7011 /* G_ASHR */
7012 288,
7013 /* G_FSHL */
7014 291,
7015 /* G_FSHR */
7016 295,
7017 /* G_ROTR */
7018 299,
7019 /* G_ROTL */
7020 302,
7021 /* G_ICMP */
7022 305,
7023 /* G_FCMP */
7024 309,
7025 /* G_SCMP */
7026 313,
7027 /* G_UCMP */
7028 316,
7029 /* G_SELECT */
7030 319,
7031 /* G_UADDO */
7032 323,
7033 /* G_UADDE */
7034 327,
7035 /* G_USUBO */
7036 332,
7037 /* G_USUBE */
7038 336,
7039 /* G_SADDO */
7040 341,
7041 /* G_SADDE */
7042 345,
7043 /* G_SSUBO */
7044 350,
7045 /* G_SSUBE */
7046 354,
7047 /* G_UMULO */
7048 359,
7049 /* G_SMULO */
7050 363,
7051 /* G_UMULH */
7052 367,
7053 /* G_SMULH */
7054 370,
7055 /* G_UADDSAT */
7056 373,
7057 /* G_SADDSAT */
7058 376,
7059 /* G_USUBSAT */
7060 379,
7061 /* G_SSUBSAT */
7062 382,
7063 /* G_USHLSAT */
7064 385,
7065 /* G_SSHLSAT */
7066 388,
7067 /* G_SMULFIX */
7068 391,
7069 /* G_UMULFIX */
7070 395,
7071 /* G_SMULFIXSAT */
7072 399,
7073 /* G_UMULFIXSAT */
7074 403,
7075 /* G_SDIVFIX */
7076 407,
7077 /* G_UDIVFIX */
7078 411,
7079 /* G_SDIVFIXSAT */
7080 415,
7081 /* G_UDIVFIXSAT */
7082 419,
7083 /* G_FADD */
7084 423,
7085 /* G_FSUB */
7086 426,
7087 /* G_FMUL */
7088 429,
7089 /* G_FMA */
7090 432,
7091 /* G_FMAD */
7092 436,
7093 /* G_FDIV */
7094 440,
7095 /* G_FREM */
7096 443,
7097 /* G_FPOW */
7098 446,
7099 /* G_FPOWI */
7100 449,
7101 /* G_FEXP */
7102 452,
7103 /* G_FEXP2 */
7104 454,
7105 /* G_FEXP10 */
7106 456,
7107 /* G_FLOG */
7108 458,
7109 /* G_FLOG2 */
7110 460,
7111 /* G_FLOG10 */
7112 462,
7113 /* G_FLDEXP */
7114 464,
7115 /* G_FFREXP */
7116 467,
7117 /* G_FNEG */
7118 470,
7119 /* G_FPEXT */
7120 472,
7121 /* G_FPTRUNC */
7122 474,
7123 /* G_FPTOSI */
7124 476,
7125 /* G_FPTOUI */
7126 478,
7127 /* G_SITOFP */
7128 480,
7129 /* G_UITOFP */
7130 482,
7131 /* G_FABS */
7132 484,
7133 /* G_FCOPYSIGN */
7134 486,
7135 /* G_IS_FPCLASS */
7136 489,
7137 /* G_FCANONICALIZE */
7138 492,
7139 /* G_FMINNUM */
7140 494,
7141 /* G_FMAXNUM */
7142 497,
7143 /* G_FMINNUM_IEEE */
7144 500,
7145 /* G_FMAXNUM_IEEE */
7146 503,
7147 /* G_FMINIMUM */
7148 506,
7149 /* G_FMAXIMUM */
7150 509,
7151 /* G_GET_FPENV */
7152 512,
7153 /* G_SET_FPENV */
7154 513,
7155 /* G_RESET_FPENV */
7156 514,
7157 /* G_GET_FPMODE */
7158 514,
7159 /* G_SET_FPMODE */
7160 515,
7161 /* G_RESET_FPMODE */
7162 516,
7163 /* G_PTR_ADD */
7164 516,
7165 /* G_PTRMASK */
7166 519,
7167 /* G_SMIN */
7168 522,
7169 /* G_SMAX */
7170 525,
7171 /* G_UMIN */
7172 528,
7173 /* G_UMAX */
7174 531,
7175 /* G_ABS */
7176 534,
7177 /* G_LROUND */
7178 536,
7179 /* G_LLROUND */
7180 538,
7181 /* G_BR */
7182 540,
7183 /* G_BRJT */
7184 541,
7185 /* G_VSCALE */
7186 544,
7187 /* G_INSERT_SUBVECTOR */
7188 546,
7189 /* G_EXTRACT_SUBVECTOR */
7190 550,
7191 /* G_INSERT_VECTOR_ELT */
7192 553,
7193 /* G_EXTRACT_VECTOR_ELT */
7194 557,
7195 /* G_SHUFFLE_VECTOR */
7196 560,
7197 /* G_SPLAT_VECTOR */
7198 564,
7199 /* G_VECTOR_COMPRESS */
7200 566,
7201 /* G_CTTZ */
7202 570,
7203 /* G_CTTZ_ZERO_UNDEF */
7204 572,
7205 /* G_CTLZ */
7206 574,
7207 /* G_CTLZ_ZERO_UNDEF */
7208 576,
7209 /* G_CTPOP */
7210 578,
7211 /* G_BSWAP */
7212 580,
7213 /* G_BITREVERSE */
7214 582,
7215 /* G_FCEIL */
7216 584,
7217 /* G_FCOS */
7218 586,
7219 /* G_FSIN */
7220 588,
7221 /* G_FTAN */
7222 590,
7223 /* G_FACOS */
7224 592,
7225 /* G_FASIN */
7226 594,
7227 /* G_FATAN */
7228 596,
7229 /* G_FCOSH */
7230 598,
7231 /* G_FSINH */
7232 600,
7233 /* G_FTANH */
7234 602,
7235 /* G_FSQRT */
7236 604,
7237 /* G_FFLOOR */
7238 606,
7239 /* G_FRINT */
7240 608,
7241 /* G_FNEARBYINT */
7242 610,
7243 /* G_ADDRSPACE_CAST */
7244 612,
7245 /* G_BLOCK_ADDR */
7246 614,
7247 /* G_JUMP_TABLE */
7248 616,
7249 /* G_DYN_STACKALLOC */
7250 618,
7251 /* G_STACKSAVE */
7252 621,
7253 /* G_STACKRESTORE */
7254 622,
7255 /* G_STRICT_FADD */
7256 623,
7257 /* G_STRICT_FSUB */
7258 626,
7259 /* G_STRICT_FMUL */
7260 629,
7261 /* G_STRICT_FDIV */
7262 632,
7263 /* G_STRICT_FREM */
7264 635,
7265 /* G_STRICT_FMA */
7266 638,
7267 /* G_STRICT_FSQRT */
7268 642,
7269 /* G_STRICT_FLDEXP */
7270 644,
7271 /* G_READ_REGISTER */
7272 647,
7273 /* G_WRITE_REGISTER */
7274 649,
7275 /* G_MEMCPY */
7276 651,
7277 /* G_MEMCPY_INLINE */
7278 655,
7279 /* G_MEMMOVE */
7280 658,
7281 /* G_MEMSET */
7282 662,
7283 /* G_BZERO */
7284 666,
7285 /* G_TRAP */
7286 669,
7287 /* G_DEBUGTRAP */
7288 669,
7289 /* G_UBSANTRAP */
7290 669,
7291 /* G_VECREDUCE_SEQ_FADD */
7292 670,
7293 /* G_VECREDUCE_SEQ_FMUL */
7294 673,
7295 /* G_VECREDUCE_FADD */
7296 676,
7297 /* G_VECREDUCE_FMUL */
7298 678,
7299 /* G_VECREDUCE_FMAX */
7300 680,
7301 /* G_VECREDUCE_FMIN */
7302 682,
7303 /* G_VECREDUCE_FMAXIMUM */
7304 684,
7305 /* G_VECREDUCE_FMINIMUM */
7306 686,
7307 /* G_VECREDUCE_ADD */
7308 688,
7309 /* G_VECREDUCE_MUL */
7310 690,
7311 /* G_VECREDUCE_AND */
7312 692,
7313 /* G_VECREDUCE_OR */
7314 694,
7315 /* G_VECREDUCE_XOR */
7316 696,
7317 /* G_VECREDUCE_SMAX */
7318 698,
7319 /* G_VECREDUCE_SMIN */
7320 700,
7321 /* G_VECREDUCE_UMAX */
7322 702,
7323 /* G_VECREDUCE_UMIN */
7324 704,
7325 /* G_SBFX */
7326 706,
7327 /* G_UBFX */
7328 710,
7329 /* CALL_PARAMS */
7330 714,
7331 /* CALL_PARAMS_S */
7332 715,
7333 /* CALL_RESULTS */
7334 716,
7335 /* CALL_RESULTS_S */
7336 716,
7337 /* CATCHRET */
7338 716,
7339 /* CATCHRET_S */
7340 718,
7341 /* CLEANUPRET */
7342 720,
7343 /* CLEANUPRET_S */
7344 720,
7345 /* COMPILER_FENCE */
7346 720,
7347 /* COMPILER_FENCE_S */
7348 720,
7349 /* RET_CALL_RESULTS */
7350 720,
7351 /* RET_CALL_RESULTS_S */
7352 720,
7353 /* ABS_F16x8 */
7354 720,
7355 /* ABS_F16x8_S */
7356 722,
7357 /* ABS_F32 */
7358 722,
7359 /* ABS_F32_S */
7360 724,
7361 /* ABS_F32x4 */
7362 724,
7363 /* ABS_F32x4_S */
7364 726,
7365 /* ABS_F64 */
7366 726,
7367 /* ABS_F64_S */
7368 728,
7369 /* ABS_F64x2 */
7370 728,
7371 /* ABS_F64x2_S */
7372 730,
7373 /* ABS_I16x8 */
7374 730,
7375 /* ABS_I16x8_S */
7376 732,
7377 /* ABS_I32x4 */
7378 732,
7379 /* ABS_I32x4_S */
7380 734,
7381 /* ABS_I64x2 */
7382 734,
7383 /* ABS_I64x2_S */
7384 736,
7385 /* ABS_I8x16 */
7386 736,
7387 /* ABS_I8x16_S */
7388 738,
7389 /* ADD_F16x8 */
7390 738,
7391 /* ADD_F16x8_S */
7392 741,
7393 /* ADD_F32 */
7394 741,
7395 /* ADD_F32_S */
7396 744,
7397 /* ADD_F32x4 */
7398 744,
7399 /* ADD_F32x4_S */
7400 747,
7401 /* ADD_F64 */
7402 747,
7403 /* ADD_F64_S */
7404 750,
7405 /* ADD_F64x2 */
7406 750,
7407 /* ADD_F64x2_S */
7408 753,
7409 /* ADD_I16x8 */
7410 753,
7411 /* ADD_I16x8_S */
7412 756,
7413 /* ADD_I32 */
7414 756,
7415 /* ADD_I32_S */
7416 759,
7417 /* ADD_I32x4 */
7418 759,
7419 /* ADD_I32x4_S */
7420 762,
7421 /* ADD_I64 */
7422 762,
7423 /* ADD_I64_S */
7424 765,
7425 /* ADD_I64x2 */
7426 765,
7427 /* ADD_I64x2_S */
7428 768,
7429 /* ADD_I8x16 */
7430 768,
7431 /* ADD_I8x16_S */
7432 771,
7433 /* ADD_SAT_S_I16x8 */
7434 771,
7435 /* ADD_SAT_S_I16x8_S */
7436 774,
7437 /* ADD_SAT_S_I8x16 */
7438 774,
7439 /* ADD_SAT_S_I8x16_S */
7440 777,
7441 /* ADD_SAT_U_I16x8 */
7442 777,
7443 /* ADD_SAT_U_I16x8_S */
7444 780,
7445 /* ADD_SAT_U_I8x16 */
7446 780,
7447 /* ADD_SAT_U_I8x16_S */
7448 783,
7449 /* ADJCALLSTACKDOWN */
7450 783,
7451 /* ADJCALLSTACKDOWN_S */
7452 785,
7453 /* ADJCALLSTACKUP */
7454 787,
7455 /* ADJCALLSTACKUP_S */
7456 789,
7457 /* ALLTRUE_I16x8 */
7458 791,
7459 /* ALLTRUE_I16x8_S */
7460 793,
7461 /* ALLTRUE_I32x4 */
7462 793,
7463 /* ALLTRUE_I32x4_S */
7464 795,
7465 /* ALLTRUE_I64x2 */
7466 795,
7467 /* ALLTRUE_I64x2_S */
7468 797,
7469 /* ALLTRUE_I8x16 */
7470 797,
7471 /* ALLTRUE_I8x16_S */
7472 799,
7473 /* AND */
7474 799,
7475 /* ANDNOT */
7476 802,
7477 /* ANDNOT_S */
7478 805,
7479 /* AND_I32 */
7480 805,
7481 /* AND_I32_S */
7482 808,
7483 /* AND_I64 */
7484 808,
7485 /* AND_I64_S */
7486 811,
7487 /* AND_S */
7488 811,
7489 /* ANYTRUE */
7490 811,
7491 /* ANYTRUE_S */
7492 813,
7493 /* ARGUMENT_exnref */
7494 813,
7495 /* ARGUMENT_exnref_S */
7496 815,
7497 /* ARGUMENT_externref */
7498 816,
7499 /* ARGUMENT_externref_S */
7500 818,
7501 /* ARGUMENT_f32 */
7502 819,
7503 /* ARGUMENT_f32_S */
7504 821,
7505 /* ARGUMENT_f64 */
7506 822,
7507 /* ARGUMENT_f64_S */
7508 824,
7509 /* ARGUMENT_funcref */
7510 825,
7511 /* ARGUMENT_funcref_S */
7512 827,
7513 /* ARGUMENT_i32 */
7514 828,
7515 /* ARGUMENT_i32_S */
7516 830,
7517 /* ARGUMENT_i64 */
7518 831,
7519 /* ARGUMENT_i64_S */
7520 833,
7521 /* ARGUMENT_v16i8 */
7522 834,
7523 /* ARGUMENT_v16i8_S */
7524 836,
7525 /* ARGUMENT_v2f64 */
7526 837,
7527 /* ARGUMENT_v2f64_S */
7528 839,
7529 /* ARGUMENT_v2i64 */
7530 840,
7531 /* ARGUMENT_v2i64_S */
7532 842,
7533 /* ARGUMENT_v4f32 */
7534 843,
7535 /* ARGUMENT_v4f32_S */
7536 845,
7537 /* ARGUMENT_v4i32 */
7538 846,
7539 /* ARGUMENT_v4i32_S */
7540 848,
7541 /* ARGUMENT_v8f16 */
7542 849,
7543 /* ARGUMENT_v8f16_S */
7544 851,
7545 /* ARGUMENT_v8i16 */
7546 852,
7547 /* ARGUMENT_v8i16_S */
7548 854,
7549 /* ATOMIC_FENCE */
7550 855,
7551 /* ATOMIC_FENCE_S */
7552 856,
7553 /* ATOMIC_LOAD16_U_I32_A32 */
7554 857,
7555 /* ATOMIC_LOAD16_U_I32_A32_S */
7556 861,
7557 /* ATOMIC_LOAD16_U_I32_A64 */
7558 863,
7559 /* ATOMIC_LOAD16_U_I32_A64_S */
7560 867,
7561 /* ATOMIC_LOAD16_U_I64_A32 */
7562 869,
7563 /* ATOMIC_LOAD16_U_I64_A32_S */
7564 873,
7565 /* ATOMIC_LOAD16_U_I64_A64 */
7566 875,
7567 /* ATOMIC_LOAD16_U_I64_A64_S */
7568 879,
7569 /* ATOMIC_LOAD32_U_I64_A32 */
7570 881,
7571 /* ATOMIC_LOAD32_U_I64_A32_S */
7572 885,
7573 /* ATOMIC_LOAD32_U_I64_A64 */
7574 887,
7575 /* ATOMIC_LOAD32_U_I64_A64_S */
7576 891,
7577 /* ATOMIC_LOAD8_U_I32_A32 */
7578 893,
7579 /* ATOMIC_LOAD8_U_I32_A32_S */
7580 897,
7581 /* ATOMIC_LOAD8_U_I32_A64 */
7582 899,
7583 /* ATOMIC_LOAD8_U_I32_A64_S */
7584 903,
7585 /* ATOMIC_LOAD8_U_I64_A32 */
7586 905,
7587 /* ATOMIC_LOAD8_U_I64_A32_S */
7588 909,
7589 /* ATOMIC_LOAD8_U_I64_A64 */
7590 911,
7591 /* ATOMIC_LOAD8_U_I64_A64_S */
7592 915,
7593 /* ATOMIC_LOAD_I32_A32 */
7594 917,
7595 /* ATOMIC_LOAD_I32_A32_S */
7596 921,
7597 /* ATOMIC_LOAD_I32_A64 */
7598 923,
7599 /* ATOMIC_LOAD_I32_A64_S */
7600 927,
7601 /* ATOMIC_LOAD_I64_A32 */
7602 929,
7603 /* ATOMIC_LOAD_I64_A32_S */
7604 933,
7605 /* ATOMIC_LOAD_I64_A64 */
7606 935,
7607 /* ATOMIC_LOAD_I64_A64_S */
7608 939,
7609 /* ATOMIC_RMW16_U_ADD_I32_A32 */
7610 941,
7611 /* ATOMIC_RMW16_U_ADD_I32_A32_S */
7612 946,
7613 /* ATOMIC_RMW16_U_ADD_I32_A64 */
7614 948,
7615 /* ATOMIC_RMW16_U_ADD_I32_A64_S */
7616 953,
7617 /* ATOMIC_RMW16_U_ADD_I64_A32 */
7618 955,
7619 /* ATOMIC_RMW16_U_ADD_I64_A32_S */
7620 960,
7621 /* ATOMIC_RMW16_U_ADD_I64_A64 */
7622 962,
7623 /* ATOMIC_RMW16_U_ADD_I64_A64_S */
7624 967,
7625 /* ATOMIC_RMW16_U_AND_I32_A32 */
7626 969,
7627 /* ATOMIC_RMW16_U_AND_I32_A32_S */
7628 974,
7629 /* ATOMIC_RMW16_U_AND_I32_A64 */
7630 976,
7631 /* ATOMIC_RMW16_U_AND_I32_A64_S */
7632 981,
7633 /* ATOMIC_RMW16_U_AND_I64_A32 */
7634 983,
7635 /* ATOMIC_RMW16_U_AND_I64_A32_S */
7636 988,
7637 /* ATOMIC_RMW16_U_AND_I64_A64 */
7638 990,
7639 /* ATOMIC_RMW16_U_AND_I64_A64_S */
7640 995,
7641 /* ATOMIC_RMW16_U_CMPXCHG_I32_A32 */
7642 997,
7643 /* ATOMIC_RMW16_U_CMPXCHG_I32_A32_S */
7644 1003,
7645 /* ATOMIC_RMW16_U_CMPXCHG_I32_A64 */
7646 1005,
7647 /* ATOMIC_RMW16_U_CMPXCHG_I32_A64_S */
7648 1011,
7649 /* ATOMIC_RMW16_U_CMPXCHG_I64_A32 */
7650 1013,
7651 /* ATOMIC_RMW16_U_CMPXCHG_I64_A32_S */
7652 1019,
7653 /* ATOMIC_RMW16_U_CMPXCHG_I64_A64 */
7654 1021,
7655 /* ATOMIC_RMW16_U_CMPXCHG_I64_A64_S */
7656 1027,
7657 /* ATOMIC_RMW16_U_OR_I32_A32 */
7658 1029,
7659 /* ATOMIC_RMW16_U_OR_I32_A32_S */
7660 1034,
7661 /* ATOMIC_RMW16_U_OR_I32_A64 */
7662 1036,
7663 /* ATOMIC_RMW16_U_OR_I32_A64_S */
7664 1041,
7665 /* ATOMIC_RMW16_U_OR_I64_A32 */
7666 1043,
7667 /* ATOMIC_RMW16_U_OR_I64_A32_S */
7668 1048,
7669 /* ATOMIC_RMW16_U_OR_I64_A64 */
7670 1050,
7671 /* ATOMIC_RMW16_U_OR_I64_A64_S */
7672 1055,
7673 /* ATOMIC_RMW16_U_SUB_I32_A32 */
7674 1057,
7675 /* ATOMIC_RMW16_U_SUB_I32_A32_S */
7676 1062,
7677 /* ATOMIC_RMW16_U_SUB_I32_A64 */
7678 1064,
7679 /* ATOMIC_RMW16_U_SUB_I32_A64_S */
7680 1069,
7681 /* ATOMIC_RMW16_U_SUB_I64_A32 */
7682 1071,
7683 /* ATOMIC_RMW16_U_SUB_I64_A32_S */
7684 1076,
7685 /* ATOMIC_RMW16_U_SUB_I64_A64 */
7686 1078,
7687 /* ATOMIC_RMW16_U_SUB_I64_A64_S */
7688 1083,
7689 /* ATOMIC_RMW16_U_XCHG_I32_A32 */
7690 1085,
7691 /* ATOMIC_RMW16_U_XCHG_I32_A32_S */
7692 1090,
7693 /* ATOMIC_RMW16_U_XCHG_I32_A64 */
7694 1092,
7695 /* ATOMIC_RMW16_U_XCHG_I32_A64_S */
7696 1097,
7697 /* ATOMIC_RMW16_U_XCHG_I64_A32 */
7698 1099,
7699 /* ATOMIC_RMW16_U_XCHG_I64_A32_S */
7700 1104,
7701 /* ATOMIC_RMW16_U_XCHG_I64_A64 */
7702 1106,
7703 /* ATOMIC_RMW16_U_XCHG_I64_A64_S */
7704 1111,
7705 /* ATOMIC_RMW16_U_XOR_I32_A32 */
7706 1113,
7707 /* ATOMIC_RMW16_U_XOR_I32_A32_S */
7708 1118,
7709 /* ATOMIC_RMW16_U_XOR_I32_A64 */
7710 1120,
7711 /* ATOMIC_RMW16_U_XOR_I32_A64_S */
7712 1125,
7713 /* ATOMIC_RMW16_U_XOR_I64_A32 */
7714 1127,
7715 /* ATOMIC_RMW16_U_XOR_I64_A32_S */
7716 1132,
7717 /* ATOMIC_RMW16_U_XOR_I64_A64 */
7718 1134,
7719 /* ATOMIC_RMW16_U_XOR_I64_A64_S */
7720 1139,
7721 /* ATOMIC_RMW32_U_ADD_I64_A32 */
7722 1141,
7723 /* ATOMIC_RMW32_U_ADD_I64_A32_S */
7724 1146,
7725 /* ATOMIC_RMW32_U_ADD_I64_A64 */
7726 1148,
7727 /* ATOMIC_RMW32_U_ADD_I64_A64_S */
7728 1153,
7729 /* ATOMIC_RMW32_U_AND_I64_A32 */
7730 1155,
7731 /* ATOMIC_RMW32_U_AND_I64_A32_S */
7732 1160,
7733 /* ATOMIC_RMW32_U_AND_I64_A64 */
7734 1162,
7735 /* ATOMIC_RMW32_U_AND_I64_A64_S */
7736 1167,
7737 /* ATOMIC_RMW32_U_CMPXCHG_I64_A32 */
7738 1169,
7739 /* ATOMIC_RMW32_U_CMPXCHG_I64_A32_S */
7740 1175,
7741 /* ATOMIC_RMW32_U_CMPXCHG_I64_A64 */
7742 1177,
7743 /* ATOMIC_RMW32_U_CMPXCHG_I64_A64_S */
7744 1183,
7745 /* ATOMIC_RMW32_U_OR_I64_A32 */
7746 1185,
7747 /* ATOMIC_RMW32_U_OR_I64_A32_S */
7748 1190,
7749 /* ATOMIC_RMW32_U_OR_I64_A64 */
7750 1192,
7751 /* ATOMIC_RMW32_U_OR_I64_A64_S */
7752 1197,
7753 /* ATOMIC_RMW32_U_SUB_I64_A32 */
7754 1199,
7755 /* ATOMIC_RMW32_U_SUB_I64_A32_S */
7756 1204,
7757 /* ATOMIC_RMW32_U_SUB_I64_A64 */
7758 1206,
7759 /* ATOMIC_RMW32_U_SUB_I64_A64_S */
7760 1211,
7761 /* ATOMIC_RMW32_U_XCHG_I64_A32 */
7762 1213,
7763 /* ATOMIC_RMW32_U_XCHG_I64_A32_S */
7764 1218,
7765 /* ATOMIC_RMW32_U_XCHG_I64_A64 */
7766 1220,
7767 /* ATOMIC_RMW32_U_XCHG_I64_A64_S */
7768 1225,
7769 /* ATOMIC_RMW32_U_XOR_I64_A32 */
7770 1227,
7771 /* ATOMIC_RMW32_U_XOR_I64_A32_S */
7772 1232,
7773 /* ATOMIC_RMW32_U_XOR_I64_A64 */
7774 1234,
7775 /* ATOMIC_RMW32_U_XOR_I64_A64_S */
7776 1239,
7777 /* ATOMIC_RMW8_U_ADD_I32_A32 */
7778 1241,
7779 /* ATOMIC_RMW8_U_ADD_I32_A32_S */
7780 1246,
7781 /* ATOMIC_RMW8_U_ADD_I32_A64 */
7782 1248,
7783 /* ATOMIC_RMW8_U_ADD_I32_A64_S */
7784 1253,
7785 /* ATOMIC_RMW8_U_ADD_I64_A32 */
7786 1255,
7787 /* ATOMIC_RMW8_U_ADD_I64_A32_S */
7788 1260,
7789 /* ATOMIC_RMW8_U_ADD_I64_A64 */
7790 1262,
7791 /* ATOMIC_RMW8_U_ADD_I64_A64_S */
7792 1267,
7793 /* ATOMIC_RMW8_U_AND_I32_A32 */
7794 1269,
7795 /* ATOMIC_RMW8_U_AND_I32_A32_S */
7796 1274,
7797 /* ATOMIC_RMW8_U_AND_I32_A64 */
7798 1276,
7799 /* ATOMIC_RMW8_U_AND_I32_A64_S */
7800 1281,
7801 /* ATOMIC_RMW8_U_AND_I64_A32 */
7802 1283,
7803 /* ATOMIC_RMW8_U_AND_I64_A32_S */
7804 1288,
7805 /* ATOMIC_RMW8_U_AND_I64_A64 */
7806 1290,
7807 /* ATOMIC_RMW8_U_AND_I64_A64_S */
7808 1295,
7809 /* ATOMIC_RMW8_U_CMPXCHG_I32_A32 */
7810 1297,
7811 /* ATOMIC_RMW8_U_CMPXCHG_I32_A32_S */
7812 1303,
7813 /* ATOMIC_RMW8_U_CMPXCHG_I32_A64 */
7814 1305,
7815 /* ATOMIC_RMW8_U_CMPXCHG_I32_A64_S */
7816 1311,
7817 /* ATOMIC_RMW8_U_CMPXCHG_I64_A32 */
7818 1313,
7819 /* ATOMIC_RMW8_U_CMPXCHG_I64_A32_S */
7820 1319,
7821 /* ATOMIC_RMW8_U_CMPXCHG_I64_A64 */
7822 1321,
7823 /* ATOMIC_RMW8_U_CMPXCHG_I64_A64_S */
7824 1327,
7825 /* ATOMIC_RMW8_U_OR_I32_A32 */
7826 1329,
7827 /* ATOMIC_RMW8_U_OR_I32_A32_S */
7828 1334,
7829 /* ATOMIC_RMW8_U_OR_I32_A64 */
7830 1336,
7831 /* ATOMIC_RMW8_U_OR_I32_A64_S */
7832 1341,
7833 /* ATOMIC_RMW8_U_OR_I64_A32 */
7834 1343,
7835 /* ATOMIC_RMW8_U_OR_I64_A32_S */
7836 1348,
7837 /* ATOMIC_RMW8_U_OR_I64_A64 */
7838 1350,
7839 /* ATOMIC_RMW8_U_OR_I64_A64_S */
7840 1355,
7841 /* ATOMIC_RMW8_U_SUB_I32_A32 */
7842 1357,
7843 /* ATOMIC_RMW8_U_SUB_I32_A32_S */
7844 1362,
7845 /* ATOMIC_RMW8_U_SUB_I32_A64 */
7846 1364,
7847 /* ATOMIC_RMW8_U_SUB_I32_A64_S */
7848 1369,
7849 /* ATOMIC_RMW8_U_SUB_I64_A32 */
7850 1371,
7851 /* ATOMIC_RMW8_U_SUB_I64_A32_S */
7852 1376,
7853 /* ATOMIC_RMW8_U_SUB_I64_A64 */
7854 1378,
7855 /* ATOMIC_RMW8_U_SUB_I64_A64_S */
7856 1383,
7857 /* ATOMIC_RMW8_U_XCHG_I32_A32 */
7858 1385,
7859 /* ATOMIC_RMW8_U_XCHG_I32_A32_S */
7860 1390,
7861 /* ATOMIC_RMW8_U_XCHG_I32_A64 */
7862 1392,
7863 /* ATOMIC_RMW8_U_XCHG_I32_A64_S */
7864 1397,
7865 /* ATOMIC_RMW8_U_XCHG_I64_A32 */
7866 1399,
7867 /* ATOMIC_RMW8_U_XCHG_I64_A32_S */
7868 1404,
7869 /* ATOMIC_RMW8_U_XCHG_I64_A64 */
7870 1406,
7871 /* ATOMIC_RMW8_U_XCHG_I64_A64_S */
7872 1411,
7873 /* ATOMIC_RMW8_U_XOR_I32_A32 */
7874 1413,
7875 /* ATOMIC_RMW8_U_XOR_I32_A32_S */
7876 1418,
7877 /* ATOMIC_RMW8_U_XOR_I32_A64 */
7878 1420,
7879 /* ATOMIC_RMW8_U_XOR_I32_A64_S */
7880 1425,
7881 /* ATOMIC_RMW8_U_XOR_I64_A32 */
7882 1427,
7883 /* ATOMIC_RMW8_U_XOR_I64_A32_S */
7884 1432,
7885 /* ATOMIC_RMW8_U_XOR_I64_A64 */
7886 1434,
7887 /* ATOMIC_RMW8_U_XOR_I64_A64_S */
7888 1439,
7889 /* ATOMIC_RMW_ADD_I32_A32 */
7890 1441,
7891 /* ATOMIC_RMW_ADD_I32_A32_S */
7892 1446,
7893 /* ATOMIC_RMW_ADD_I32_A64 */
7894 1448,
7895 /* ATOMIC_RMW_ADD_I32_A64_S */
7896 1453,
7897 /* ATOMIC_RMW_ADD_I64_A32 */
7898 1455,
7899 /* ATOMIC_RMW_ADD_I64_A32_S */
7900 1460,
7901 /* ATOMIC_RMW_ADD_I64_A64 */
7902 1462,
7903 /* ATOMIC_RMW_ADD_I64_A64_S */
7904 1467,
7905 /* ATOMIC_RMW_AND_I32_A32 */
7906 1469,
7907 /* ATOMIC_RMW_AND_I32_A32_S */
7908 1474,
7909 /* ATOMIC_RMW_AND_I32_A64 */
7910 1476,
7911 /* ATOMIC_RMW_AND_I32_A64_S */
7912 1481,
7913 /* ATOMIC_RMW_AND_I64_A32 */
7914 1483,
7915 /* ATOMIC_RMW_AND_I64_A32_S */
7916 1488,
7917 /* ATOMIC_RMW_AND_I64_A64 */
7918 1490,
7919 /* ATOMIC_RMW_AND_I64_A64_S */
7920 1495,
7921 /* ATOMIC_RMW_CMPXCHG_I32_A32 */
7922 1497,
7923 /* ATOMIC_RMW_CMPXCHG_I32_A32_S */
7924 1503,
7925 /* ATOMIC_RMW_CMPXCHG_I32_A64 */
7926 1505,
7927 /* ATOMIC_RMW_CMPXCHG_I32_A64_S */
7928 1511,
7929 /* ATOMIC_RMW_CMPXCHG_I64_A32 */
7930 1513,
7931 /* ATOMIC_RMW_CMPXCHG_I64_A32_S */
7932 1519,
7933 /* ATOMIC_RMW_CMPXCHG_I64_A64 */
7934 1521,
7935 /* ATOMIC_RMW_CMPXCHG_I64_A64_S */
7936 1527,
7937 /* ATOMIC_RMW_OR_I32_A32 */
7938 1529,
7939 /* ATOMIC_RMW_OR_I32_A32_S */
7940 1534,
7941 /* ATOMIC_RMW_OR_I32_A64 */
7942 1536,
7943 /* ATOMIC_RMW_OR_I32_A64_S */
7944 1541,
7945 /* ATOMIC_RMW_OR_I64_A32 */
7946 1543,
7947 /* ATOMIC_RMW_OR_I64_A32_S */
7948 1548,
7949 /* ATOMIC_RMW_OR_I64_A64 */
7950 1550,
7951 /* ATOMIC_RMW_OR_I64_A64_S */
7952 1555,
7953 /* ATOMIC_RMW_SUB_I32_A32 */
7954 1557,
7955 /* ATOMIC_RMW_SUB_I32_A32_S */
7956 1562,
7957 /* ATOMIC_RMW_SUB_I32_A64 */
7958 1564,
7959 /* ATOMIC_RMW_SUB_I32_A64_S */
7960 1569,
7961 /* ATOMIC_RMW_SUB_I64_A32 */
7962 1571,
7963 /* ATOMIC_RMW_SUB_I64_A32_S */
7964 1576,
7965 /* ATOMIC_RMW_SUB_I64_A64 */
7966 1578,
7967 /* ATOMIC_RMW_SUB_I64_A64_S */
7968 1583,
7969 /* ATOMIC_RMW_XCHG_I32_A32 */
7970 1585,
7971 /* ATOMIC_RMW_XCHG_I32_A32_S */
7972 1590,
7973 /* ATOMIC_RMW_XCHG_I32_A64 */
7974 1592,
7975 /* ATOMIC_RMW_XCHG_I32_A64_S */
7976 1597,
7977 /* ATOMIC_RMW_XCHG_I64_A32 */
7978 1599,
7979 /* ATOMIC_RMW_XCHG_I64_A32_S */
7980 1604,
7981 /* ATOMIC_RMW_XCHG_I64_A64 */
7982 1606,
7983 /* ATOMIC_RMW_XCHG_I64_A64_S */
7984 1611,
7985 /* ATOMIC_RMW_XOR_I32_A32 */
7986 1613,
7987 /* ATOMIC_RMW_XOR_I32_A32_S */
7988 1618,
7989 /* ATOMIC_RMW_XOR_I32_A64 */
7990 1620,
7991 /* ATOMIC_RMW_XOR_I32_A64_S */
7992 1625,
7993 /* ATOMIC_RMW_XOR_I64_A32 */
7994 1627,
7995 /* ATOMIC_RMW_XOR_I64_A32_S */
7996 1632,
7997 /* ATOMIC_RMW_XOR_I64_A64 */
7998 1634,
7999 /* ATOMIC_RMW_XOR_I64_A64_S */
8000 1639,
8001 /* ATOMIC_STORE16_I32_A32 */
8002 1641,
8003 /* ATOMIC_STORE16_I32_A32_S */
8004 1645,
8005 /* ATOMIC_STORE16_I32_A64 */
8006 1647,
8007 /* ATOMIC_STORE16_I32_A64_S */
8008 1651,
8009 /* ATOMIC_STORE16_I64_A32 */
8010 1653,
8011 /* ATOMIC_STORE16_I64_A32_S */
8012 1657,
8013 /* ATOMIC_STORE16_I64_A64 */
8014 1659,
8015 /* ATOMIC_STORE16_I64_A64_S */
8016 1663,
8017 /* ATOMIC_STORE32_I64_A32 */
8018 1665,
8019 /* ATOMIC_STORE32_I64_A32_S */
8020 1669,
8021 /* ATOMIC_STORE32_I64_A64 */
8022 1671,
8023 /* ATOMIC_STORE32_I64_A64_S */
8024 1675,
8025 /* ATOMIC_STORE8_I32_A32 */
8026 1677,
8027 /* ATOMIC_STORE8_I32_A32_S */
8028 1681,
8029 /* ATOMIC_STORE8_I32_A64 */
8030 1683,
8031 /* ATOMIC_STORE8_I32_A64_S */
8032 1687,
8033 /* ATOMIC_STORE8_I64_A32 */
8034 1689,
8035 /* ATOMIC_STORE8_I64_A32_S */
8036 1693,
8037 /* ATOMIC_STORE8_I64_A64 */
8038 1695,
8039 /* ATOMIC_STORE8_I64_A64_S */
8040 1699,
8041 /* ATOMIC_STORE_I32_A32 */
8042 1701,
8043 /* ATOMIC_STORE_I32_A32_S */
8044 1705,
8045 /* ATOMIC_STORE_I32_A64 */
8046 1707,
8047 /* ATOMIC_STORE_I32_A64_S */
8048 1711,
8049 /* ATOMIC_STORE_I64_A32 */
8050 1713,
8051 /* ATOMIC_STORE_I64_A32_S */
8052 1717,
8053 /* ATOMIC_STORE_I64_A64 */
8054 1719,
8055 /* ATOMIC_STORE_I64_A64_S */
8056 1723,
8057 /* AVGR_U_I16x8 */
8058 1725,
8059 /* AVGR_U_I16x8_S */
8060 1728,
8061 /* AVGR_U_I8x16 */
8062 1728,
8063 /* AVGR_U_I8x16_S */
8064 1731,
8065 /* BITMASK_I16x8 */
8066 1731,
8067 /* BITMASK_I16x8_S */
8068 1733,
8069 /* BITMASK_I32x4 */
8070 1733,
8071 /* BITMASK_I32x4_S */
8072 1735,
8073 /* BITMASK_I64x2 */
8074 1735,
8075 /* BITMASK_I64x2_S */
8076 1737,
8077 /* BITMASK_I8x16 */
8078 1737,
8079 /* BITMASK_I8x16_S */
8080 1739,
8081 /* BITSELECT */
8082 1739,
8083 /* BITSELECT_S */
8084 1743,
8085 /* BLOCK */
8086 1743,
8087 /* BLOCK_S */
8088 1744,
8089 /* BR */
8090 1745,
8091 /* BR_IF */
8092 1746,
8093 /* BR_IF_S */
8094 1748,
8095 /* BR_S */
8096 1749,
8097 /* BR_TABLE_I32 */
8098 1750,
8099 /* BR_TABLE_I32_S */
8100 1751,
8101 /* BR_TABLE_I64 */
8102 1752,
8103 /* BR_TABLE_I64_S */
8104 1753,
8105 /* BR_UNLESS */
8106 1754,
8107 /* BR_UNLESS_S */
8108 1756,
8109 /* CALL */
8110 1757,
8111 /* CALL_INDIRECT */
8112 1758,
8113 /* CALL_INDIRECT_S */
8114 1760,
8115 /* CALL_S */
8116 1762,
8117 /* CATCH */
8118 1763,
8119 /* CATCH_ALL */
8120 1764,
8121 /* CATCH_ALL_S */
8122 1764,
8123 /* CATCH_S */
8124 1764,
8125 /* CEIL_F16x8 */
8126 1765,
8127 /* CEIL_F16x8_S */
8128 1767,
8129 /* CEIL_F32 */
8130 1767,
8131 /* CEIL_F32_S */
8132 1769,
8133 /* CEIL_F32x4 */
8134 1769,
8135 /* CEIL_F32x4_S */
8136 1771,
8137 /* CEIL_F64 */
8138 1771,
8139 /* CEIL_F64_S */
8140 1773,
8141 /* CEIL_F64x2 */
8142 1773,
8143 /* CEIL_F64x2_S */
8144 1775,
8145 /* CLZ_I32 */
8146 1775,
8147 /* CLZ_I32_S */
8148 1777,
8149 /* CLZ_I64 */
8150 1777,
8151 /* CLZ_I64_S */
8152 1779,
8153 /* CONST_F32 */
8154 1779,
8155 /* CONST_F32_S */
8156 1781,
8157 /* CONST_F64 */
8158 1782,
8159 /* CONST_F64_S */
8160 1784,
8161 /* CONST_I32 */
8162 1785,
8163 /* CONST_I32_S */
8164 1787,
8165 /* CONST_I64 */
8166 1788,
8167 /* CONST_I64_S */
8168 1790,
8169 /* CONST_V128_F32x4 */
8170 1791,
8171 /* CONST_V128_F32x4_S */
8172 1796,
8173 /* CONST_V128_F64x2 */
8174 1800,
8175 /* CONST_V128_F64x2_S */
8176 1803,
8177 /* CONST_V128_I16x8 */
8178 1805,
8179 /* CONST_V128_I16x8_S */
8180 1814,
8181 /* CONST_V128_I32x4 */
8182 1822,
8183 /* CONST_V128_I32x4_S */
8184 1827,
8185 /* CONST_V128_I64x2 */
8186 1831,
8187 /* CONST_V128_I64x2_S */
8188 1834,
8189 /* CONST_V128_I8x16 */
8190 1836,
8191 /* CONST_V128_I8x16_S */
8192 1853,
8193 /* COPYSIGN_F32 */
8194 1869,
8195 /* COPYSIGN_F32_S */
8196 1872,
8197 /* COPYSIGN_F64 */
8198 1872,
8199 /* COPYSIGN_F64_S */
8200 1875,
8201 /* COPY_EXNREF */
8202 1875,
8203 /* COPY_EXNREF_S */
8204 1877,
8205 /* COPY_EXTERNREF */
8206 1877,
8207 /* COPY_EXTERNREF_S */
8208 1879,
8209 /* COPY_F32 */
8210 1879,
8211 /* COPY_F32_S */
8212 1881,
8213 /* COPY_F64 */
8214 1881,
8215 /* COPY_F64_S */
8216 1883,
8217 /* COPY_FUNCREF */
8218 1883,
8219 /* COPY_FUNCREF_S */
8220 1885,
8221 /* COPY_I32 */
8222 1885,
8223 /* COPY_I32_S */
8224 1887,
8225 /* COPY_I64 */
8226 1887,
8227 /* COPY_I64_S */
8228 1889,
8229 /* COPY_V128 */
8230 1889,
8231 /* COPY_V128_S */
8232 1891,
8233 /* CTZ_I32 */
8234 1891,
8235 /* CTZ_I32_S */
8236 1893,
8237 /* CTZ_I64 */
8238 1893,
8239 /* CTZ_I64_S */
8240 1895,
8241 /* DEBUG_UNREACHABLE */
8242 1895,
8243 /* DEBUG_UNREACHABLE_S */
8244 1895,
8245 /* DELEGATE */
8246 1895,
8247 /* DELEGATE_S */
8248 1896,
8249 /* DIV_F16x8 */
8250 1897,
8251 /* DIV_F16x8_S */
8252 1900,
8253 /* DIV_F32 */
8254 1900,
8255 /* DIV_F32_S */
8256 1903,
8257 /* DIV_F32x4 */
8258 1903,
8259 /* DIV_F32x4_S */
8260 1906,
8261 /* DIV_F64 */
8262 1906,
8263 /* DIV_F64_S */
8264 1909,
8265 /* DIV_F64x2 */
8266 1909,
8267 /* DIV_F64x2_S */
8268 1912,
8269 /* DIV_S_I32 */
8270 1912,
8271 /* DIV_S_I32_S */
8272 1915,
8273 /* DIV_S_I64 */
8274 1915,
8275 /* DIV_S_I64_S */
8276 1918,
8277 /* DIV_U_I32 */
8278 1918,
8279 /* DIV_U_I32_S */
8280 1921,
8281 /* DIV_U_I64 */
8282 1921,
8283 /* DIV_U_I64_S */
8284 1924,
8285 /* DOT */
8286 1924,
8287 /* DOT_S */
8288 1927,
8289 /* DROP_EXNREF */
8290 1927,
8291 /* DROP_EXNREF_S */
8292 1928,
8293 /* DROP_EXTERNREF */
8294 1928,
8295 /* DROP_EXTERNREF_S */
8296 1929,
8297 /* DROP_F32 */
8298 1929,
8299 /* DROP_F32_S */
8300 1930,
8301 /* DROP_F64 */
8302 1930,
8303 /* DROP_F64_S */
8304 1931,
8305 /* DROP_FUNCREF */
8306 1931,
8307 /* DROP_FUNCREF_S */
8308 1932,
8309 /* DROP_I32 */
8310 1932,
8311 /* DROP_I32_S */
8312 1933,
8313 /* DROP_I64 */
8314 1933,
8315 /* DROP_I64_S */
8316 1934,
8317 /* DROP_V128 */
8318 1934,
8319 /* DROP_V128_S */
8320 1935,
8321 /* ELSE */
8322 1935,
8323 /* ELSE_S */
8324 1935,
8325 /* END */
8326 1935,
8327 /* END_BLOCK */
8328 1935,
8329 /* END_BLOCK_S */
8330 1935,
8331 /* END_FUNCTION */
8332 1935,
8333 /* END_FUNCTION_S */
8334 1935,
8335 /* END_IF */
8336 1935,
8337 /* END_IF_S */
8338 1935,
8339 /* END_LOOP */
8340 1935,
8341 /* END_LOOP_S */
8342 1935,
8343 /* END_S */
8344 1935,
8345 /* END_TRY */
8346 1935,
8347 /* END_TRY_S */
8348 1935,
8349 /* EQZ_I32 */
8350 1935,
8351 /* EQZ_I32_S */
8352 1937,
8353 /* EQZ_I64 */
8354 1937,
8355 /* EQZ_I64_S */
8356 1939,
8357 /* EQ_F16x8 */
8358 1939,
8359 /* EQ_F16x8_S */
8360 1942,
8361 /* EQ_F32 */
8362 1942,
8363 /* EQ_F32_S */
8364 1945,
8365 /* EQ_F32x4 */
8366 1945,
8367 /* EQ_F32x4_S */
8368 1948,
8369 /* EQ_F64 */
8370 1948,
8371 /* EQ_F64_S */
8372 1951,
8373 /* EQ_F64x2 */
8374 1951,
8375 /* EQ_F64x2_S */
8376 1954,
8377 /* EQ_I16x8 */
8378 1954,
8379 /* EQ_I16x8_S */
8380 1957,
8381 /* EQ_I32 */
8382 1957,
8383 /* EQ_I32_S */
8384 1960,
8385 /* EQ_I32x4 */
8386 1960,
8387 /* EQ_I32x4_S */
8388 1963,
8389 /* EQ_I64 */
8390 1963,
8391 /* EQ_I64_S */
8392 1966,
8393 /* EQ_I64x2 */
8394 1966,
8395 /* EQ_I64x2_S */
8396 1969,
8397 /* EQ_I8x16 */
8398 1969,
8399 /* EQ_I8x16_S */
8400 1972,
8401 /* EXTMUL_HIGH_S_I16x8 */
8402 1972,
8403 /* EXTMUL_HIGH_S_I16x8_S */
8404 1975,
8405 /* EXTMUL_HIGH_S_I32x4 */
8406 1975,
8407 /* EXTMUL_HIGH_S_I32x4_S */
8408 1978,
8409 /* EXTMUL_HIGH_S_I64x2 */
8410 1978,
8411 /* EXTMUL_HIGH_S_I64x2_S */
8412 1981,
8413 /* EXTMUL_HIGH_U_I16x8 */
8414 1981,
8415 /* EXTMUL_HIGH_U_I16x8_S */
8416 1984,
8417 /* EXTMUL_HIGH_U_I32x4 */
8418 1984,
8419 /* EXTMUL_HIGH_U_I32x4_S */
8420 1987,
8421 /* EXTMUL_HIGH_U_I64x2 */
8422 1987,
8423 /* EXTMUL_HIGH_U_I64x2_S */
8424 1990,
8425 /* EXTMUL_LOW_S_I16x8 */
8426 1990,
8427 /* EXTMUL_LOW_S_I16x8_S */
8428 1993,
8429 /* EXTMUL_LOW_S_I32x4 */
8430 1993,
8431 /* EXTMUL_LOW_S_I32x4_S */
8432 1996,
8433 /* EXTMUL_LOW_S_I64x2 */
8434 1996,
8435 /* EXTMUL_LOW_S_I64x2_S */
8436 1999,
8437 /* EXTMUL_LOW_U_I16x8 */
8438 1999,
8439 /* EXTMUL_LOW_U_I16x8_S */
8440 2002,
8441 /* EXTMUL_LOW_U_I32x4 */
8442 2002,
8443 /* EXTMUL_LOW_U_I32x4_S */
8444 2005,
8445 /* EXTMUL_LOW_U_I64x2 */
8446 2005,
8447 /* EXTMUL_LOW_U_I64x2_S */
8448 2008,
8449 /* EXTRACT_LANE_F16x8 */
8450 2008,
8451 /* EXTRACT_LANE_F16x8_S */
8452 2011,
8453 /* EXTRACT_LANE_F32x4 */
8454 2012,
8455 /* EXTRACT_LANE_F32x4_S */
8456 2015,
8457 /* EXTRACT_LANE_F64x2 */
8458 2016,
8459 /* EXTRACT_LANE_F64x2_S */
8460 2019,
8461 /* EXTRACT_LANE_I16x8_s */
8462 2020,
8463 /* EXTRACT_LANE_I16x8_s_S */
8464 2023,
8465 /* EXTRACT_LANE_I16x8_u */
8466 2024,
8467 /* EXTRACT_LANE_I16x8_u_S */
8468 2027,
8469 /* EXTRACT_LANE_I32x4 */
8470 2028,
8471 /* EXTRACT_LANE_I32x4_S */
8472 2031,
8473 /* EXTRACT_LANE_I64x2 */
8474 2032,
8475 /* EXTRACT_LANE_I64x2_S */
8476 2035,
8477 /* EXTRACT_LANE_I8x16_s */
8478 2036,
8479 /* EXTRACT_LANE_I8x16_s_S */
8480 2039,
8481 /* EXTRACT_LANE_I8x16_u */
8482 2040,
8483 /* EXTRACT_LANE_I8x16_u_S */
8484 2043,
8485 /* F32_CONVERT_S_I32 */
8486 2044,
8487 /* F32_CONVERT_S_I32_S */
8488 2046,
8489 /* F32_CONVERT_S_I64 */
8490 2046,
8491 /* F32_CONVERT_S_I64_S */
8492 2048,
8493 /* F32_CONVERT_U_I32 */
8494 2048,
8495 /* F32_CONVERT_U_I32_S */
8496 2050,
8497 /* F32_CONVERT_U_I64 */
8498 2050,
8499 /* F32_CONVERT_U_I64_S */
8500 2052,
8501 /* F32_DEMOTE_F64 */
8502 2052,
8503 /* F32_DEMOTE_F64_S */
8504 2054,
8505 /* F32_REINTERPRET_I32 */
8506 2054,
8507 /* F32_REINTERPRET_I32_S */
8508 2056,
8509 /* F64_CONVERT_S_I32 */
8510 2056,
8511 /* F64_CONVERT_S_I32_S */
8512 2058,
8513 /* F64_CONVERT_S_I64 */
8514 2058,
8515 /* F64_CONVERT_S_I64_S */
8516 2060,
8517 /* F64_CONVERT_U_I32 */
8518 2060,
8519 /* F64_CONVERT_U_I32_S */
8520 2062,
8521 /* F64_CONVERT_U_I64 */
8522 2062,
8523 /* F64_CONVERT_U_I64_S */
8524 2064,
8525 /* F64_PROMOTE_F32 */
8526 2064,
8527 /* F64_PROMOTE_F32_S */
8528 2066,
8529 /* F64_REINTERPRET_I64 */
8530 2066,
8531 /* F64_REINTERPRET_I64_S */
8532 2068,
8533 /* FALLTHROUGH_RETURN */
8534 2068,
8535 /* FALLTHROUGH_RETURN_S */
8536 2068,
8537 /* FLOOR_F16x8 */
8538 2068,
8539 /* FLOOR_F16x8_S */
8540 2070,
8541 /* FLOOR_F32 */
8542 2070,
8543 /* FLOOR_F32_S */
8544 2072,
8545 /* FLOOR_F32x4 */
8546 2072,
8547 /* FLOOR_F32x4_S */
8548 2074,
8549 /* FLOOR_F64 */
8550 2074,
8551 /* FLOOR_F64_S */
8552 2076,
8553 /* FLOOR_F64x2 */
8554 2076,
8555 /* FLOOR_F64x2_S */
8556 2078,
8557 /* FP_TO_SINT_I32_F32 */
8558 2078,
8559 /* FP_TO_SINT_I32_F32_S */
8560 2080,
8561 /* FP_TO_SINT_I32_F64 */
8562 2080,
8563 /* FP_TO_SINT_I32_F64_S */
8564 2082,
8565 /* FP_TO_SINT_I64_F32 */
8566 2082,
8567 /* FP_TO_SINT_I64_F32_S */
8568 2084,
8569 /* FP_TO_SINT_I64_F64 */
8570 2084,
8571 /* FP_TO_SINT_I64_F64_S */
8572 2086,
8573 /* FP_TO_UINT_I32_F32 */
8574 2086,
8575 /* FP_TO_UINT_I32_F32_S */
8576 2088,
8577 /* FP_TO_UINT_I32_F64 */
8578 2088,
8579 /* FP_TO_UINT_I32_F64_S */
8580 2090,
8581 /* FP_TO_UINT_I64_F32 */
8582 2090,
8583 /* FP_TO_UINT_I64_F32_S */
8584 2092,
8585 /* FP_TO_UINT_I64_F64 */
8586 2092,
8587 /* FP_TO_UINT_I64_F64_S */
8588 2094,
8589 /* GE_F16x8 */
8590 2094,
8591 /* GE_F16x8_S */
8592 2097,
8593 /* GE_F32 */
8594 2097,
8595 /* GE_F32_S */
8596 2100,
8597 /* GE_F32x4 */
8598 2100,
8599 /* GE_F32x4_S */
8600 2103,
8601 /* GE_F64 */
8602 2103,
8603 /* GE_F64_S */
8604 2106,
8605 /* GE_F64x2 */
8606 2106,
8607 /* GE_F64x2_S */
8608 2109,
8609 /* GE_S_I16x8 */
8610 2109,
8611 /* GE_S_I16x8_S */
8612 2112,
8613 /* GE_S_I32 */
8614 2112,
8615 /* GE_S_I32_S */
8616 2115,
8617 /* GE_S_I32x4 */
8618 2115,
8619 /* GE_S_I32x4_S */
8620 2118,
8621 /* GE_S_I64 */
8622 2118,
8623 /* GE_S_I64_S */
8624 2121,
8625 /* GE_S_I64x2 */
8626 2121,
8627 /* GE_S_I64x2_S */
8628 2124,
8629 /* GE_S_I8x16 */
8630 2124,
8631 /* GE_S_I8x16_S */
8632 2127,
8633 /* GE_U_I16x8 */
8634 2127,
8635 /* GE_U_I16x8_S */
8636 2130,
8637 /* GE_U_I32 */
8638 2130,
8639 /* GE_U_I32_S */
8640 2133,
8641 /* GE_U_I32x4 */
8642 2133,
8643 /* GE_U_I32x4_S */
8644 2136,
8645 /* GE_U_I64 */
8646 2136,
8647 /* GE_U_I64_S */
8648 2139,
8649 /* GE_U_I8x16 */
8650 2139,
8651 /* GE_U_I8x16_S */
8652 2142,
8653 /* GLOBAL_GET_EXNREF */
8654 2142,
8655 /* GLOBAL_GET_EXNREF_S */
8656 2144,
8657 /* GLOBAL_GET_EXTERNREF */
8658 2145,
8659 /* GLOBAL_GET_EXTERNREF_S */
8660 2147,
8661 /* GLOBAL_GET_F32 */
8662 2148,
8663 /* GLOBAL_GET_F32_S */
8664 2150,
8665 /* GLOBAL_GET_F64 */
8666 2151,
8667 /* GLOBAL_GET_F64_S */
8668 2153,
8669 /* GLOBAL_GET_FUNCREF */
8670 2154,
8671 /* GLOBAL_GET_FUNCREF_S */
8672 2156,
8673 /* GLOBAL_GET_I32 */
8674 2157,
8675 /* GLOBAL_GET_I32_S */
8676 2159,
8677 /* GLOBAL_GET_I64 */
8678 2160,
8679 /* GLOBAL_GET_I64_S */
8680 2162,
8681 /* GLOBAL_GET_V128 */
8682 2163,
8683 /* GLOBAL_GET_V128_S */
8684 2165,
8685 /* GLOBAL_SET_EXNREF */
8686 2166,
8687 /* GLOBAL_SET_EXNREF_S */
8688 2168,
8689 /* GLOBAL_SET_EXTERNREF */
8690 2169,
8691 /* GLOBAL_SET_EXTERNREF_S */
8692 2171,
8693 /* GLOBAL_SET_F32 */
8694 2172,
8695 /* GLOBAL_SET_F32_S */
8696 2174,
8697 /* GLOBAL_SET_F64 */
8698 2175,
8699 /* GLOBAL_SET_F64_S */
8700 2177,
8701 /* GLOBAL_SET_FUNCREF */
8702 2178,
8703 /* GLOBAL_SET_FUNCREF_S */
8704 2180,
8705 /* GLOBAL_SET_I32 */
8706 2181,
8707 /* GLOBAL_SET_I32_S */
8708 2183,
8709 /* GLOBAL_SET_I64 */
8710 2184,
8711 /* GLOBAL_SET_I64_S */
8712 2186,
8713 /* GLOBAL_SET_V128 */
8714 2187,
8715 /* GLOBAL_SET_V128_S */
8716 2189,
8717 /* GT_F16x8 */
8718 2190,
8719 /* GT_F16x8_S */
8720 2193,
8721 /* GT_F32 */
8722 2193,
8723 /* GT_F32_S */
8724 2196,
8725 /* GT_F32x4 */
8726 2196,
8727 /* GT_F32x4_S */
8728 2199,
8729 /* GT_F64 */
8730 2199,
8731 /* GT_F64_S */
8732 2202,
8733 /* GT_F64x2 */
8734 2202,
8735 /* GT_F64x2_S */
8736 2205,
8737 /* GT_S_I16x8 */
8738 2205,
8739 /* GT_S_I16x8_S */
8740 2208,
8741 /* GT_S_I32 */
8742 2208,
8743 /* GT_S_I32_S */
8744 2211,
8745 /* GT_S_I32x4 */
8746 2211,
8747 /* GT_S_I32x4_S */
8748 2214,
8749 /* GT_S_I64 */
8750 2214,
8751 /* GT_S_I64_S */
8752 2217,
8753 /* GT_S_I64x2 */
8754 2217,
8755 /* GT_S_I64x2_S */
8756 2220,
8757 /* GT_S_I8x16 */
8758 2220,
8759 /* GT_S_I8x16_S */
8760 2223,
8761 /* GT_U_I16x8 */
8762 2223,
8763 /* GT_U_I16x8_S */
8764 2226,
8765 /* GT_U_I32 */
8766 2226,
8767 /* GT_U_I32_S */
8768 2229,
8769 /* GT_U_I32x4 */
8770 2229,
8771 /* GT_U_I32x4_S */
8772 2232,
8773 /* GT_U_I64 */
8774 2232,
8775 /* GT_U_I64_S */
8776 2235,
8777 /* GT_U_I8x16 */
8778 2235,
8779 /* GT_U_I8x16_S */
8780 2238,
8781 /* I32_EXTEND16_S_I32 */
8782 2238,
8783 /* I32_EXTEND16_S_I32_S */
8784 2240,
8785 /* I32_EXTEND8_S_I32 */
8786 2240,
8787 /* I32_EXTEND8_S_I32_S */
8788 2242,
8789 /* I32_REINTERPRET_F32 */
8790 2242,
8791 /* I32_REINTERPRET_F32_S */
8792 2244,
8793 /* I32_TRUNC_S_F32 */
8794 2244,
8795 /* I32_TRUNC_S_F32_S */
8796 2246,
8797 /* I32_TRUNC_S_F64 */
8798 2246,
8799 /* I32_TRUNC_S_F64_S */
8800 2248,
8801 /* I32_TRUNC_S_SAT_F32 */
8802 2248,
8803 /* I32_TRUNC_S_SAT_F32_S */
8804 2250,
8805 /* I32_TRUNC_S_SAT_F64 */
8806 2250,
8807 /* I32_TRUNC_S_SAT_F64_S */
8808 2252,
8809 /* I32_TRUNC_U_F32 */
8810 2252,
8811 /* I32_TRUNC_U_F32_S */
8812 2254,
8813 /* I32_TRUNC_U_F64 */
8814 2254,
8815 /* I32_TRUNC_U_F64_S */
8816 2256,
8817 /* I32_TRUNC_U_SAT_F32 */
8818 2256,
8819 /* I32_TRUNC_U_SAT_F32_S */
8820 2258,
8821 /* I32_TRUNC_U_SAT_F64 */
8822 2258,
8823 /* I32_TRUNC_U_SAT_F64_S */
8824 2260,
8825 /* I32_WRAP_I64 */
8826 2260,
8827 /* I32_WRAP_I64_S */
8828 2262,
8829 /* I64_EXTEND16_S_I64 */
8830 2262,
8831 /* I64_EXTEND16_S_I64_S */
8832 2264,
8833 /* I64_EXTEND32_S_I64 */
8834 2264,
8835 /* I64_EXTEND32_S_I64_S */
8836 2266,
8837 /* I64_EXTEND8_S_I64 */
8838 2266,
8839 /* I64_EXTEND8_S_I64_S */
8840 2268,
8841 /* I64_EXTEND_S_I32 */
8842 2268,
8843 /* I64_EXTEND_S_I32_S */
8844 2270,
8845 /* I64_EXTEND_U_I32 */
8846 2270,
8847 /* I64_EXTEND_U_I32_S */
8848 2272,
8849 /* I64_REINTERPRET_F64 */
8850 2272,
8851 /* I64_REINTERPRET_F64_S */
8852 2274,
8853 /* I64_TRUNC_S_F32 */
8854 2274,
8855 /* I64_TRUNC_S_F32_S */
8856 2276,
8857 /* I64_TRUNC_S_F64 */
8858 2276,
8859 /* I64_TRUNC_S_F64_S */
8860 2278,
8861 /* I64_TRUNC_S_SAT_F32 */
8862 2278,
8863 /* I64_TRUNC_S_SAT_F32_S */
8864 2280,
8865 /* I64_TRUNC_S_SAT_F64 */
8866 2280,
8867 /* I64_TRUNC_S_SAT_F64_S */
8868 2282,
8869 /* I64_TRUNC_U_F32 */
8870 2282,
8871 /* I64_TRUNC_U_F32_S */
8872 2284,
8873 /* I64_TRUNC_U_F64 */
8874 2284,
8875 /* I64_TRUNC_U_F64_S */
8876 2286,
8877 /* I64_TRUNC_U_SAT_F32 */
8878 2286,
8879 /* I64_TRUNC_U_SAT_F32_S */
8880 2288,
8881 /* I64_TRUNC_U_SAT_F64 */
8882 2288,
8883 /* I64_TRUNC_U_SAT_F64_S */
8884 2290,
8885 /* IF */
8886 2290,
8887 /* IF_S */
8888 2292,
8889 /* LANESELECT_I16x8 */
8890 2293,
8891 /* LANESELECT_I16x8_S */
8892 2297,
8893 /* LANESELECT_I32x4 */
8894 2297,
8895 /* LANESELECT_I32x4_S */
8896 2301,
8897 /* LANESELECT_I64x2 */
8898 2301,
8899 /* LANESELECT_I64x2_S */
8900 2305,
8901 /* LANESELECT_I8x16 */
8902 2305,
8903 /* LANESELECT_I8x16_S */
8904 2309,
8905 /* LE_F16x8 */
8906 2309,
8907 /* LE_F16x8_S */
8908 2312,
8909 /* LE_F32 */
8910 2312,
8911 /* LE_F32_S */
8912 2315,
8913 /* LE_F32x4 */
8914 2315,
8915 /* LE_F32x4_S */
8916 2318,
8917 /* LE_F64 */
8918 2318,
8919 /* LE_F64_S */
8920 2321,
8921 /* LE_F64x2 */
8922 2321,
8923 /* LE_F64x2_S */
8924 2324,
8925 /* LE_S_I16x8 */
8926 2324,
8927 /* LE_S_I16x8_S */
8928 2327,
8929 /* LE_S_I32 */
8930 2327,
8931 /* LE_S_I32_S */
8932 2330,
8933 /* LE_S_I32x4 */
8934 2330,
8935 /* LE_S_I32x4_S */
8936 2333,
8937 /* LE_S_I64 */
8938 2333,
8939 /* LE_S_I64_S */
8940 2336,
8941 /* LE_S_I64x2 */
8942 2336,
8943 /* LE_S_I64x2_S */
8944 2339,
8945 /* LE_S_I8x16 */
8946 2339,
8947 /* LE_S_I8x16_S */
8948 2342,
8949 /* LE_U_I16x8 */
8950 2342,
8951 /* LE_U_I16x8_S */
8952 2345,
8953 /* LE_U_I32 */
8954 2345,
8955 /* LE_U_I32_S */
8956 2348,
8957 /* LE_U_I32x4 */
8958 2348,
8959 /* LE_U_I32x4_S */
8960 2351,
8961 /* LE_U_I64 */
8962 2351,
8963 /* LE_U_I64_S */
8964 2354,
8965 /* LE_U_I8x16 */
8966 2354,
8967 /* LE_U_I8x16_S */
8968 2357,
8969 /* LOAD16_SPLAT_A32 */
8970 2357,
8971 /* LOAD16_SPLAT_A32_S */
8972 2361,
8973 /* LOAD16_SPLAT_A64 */
8974 2363,
8975 /* LOAD16_SPLAT_A64_S */
8976 2367,
8977 /* LOAD16_S_I32_A32 */
8978 2369,
8979 /* LOAD16_S_I32_A32_S */
8980 2373,
8981 /* LOAD16_S_I32_A64 */
8982 2375,
8983 /* LOAD16_S_I32_A64_S */
8984 2379,
8985 /* LOAD16_S_I64_A32 */
8986 2381,
8987 /* LOAD16_S_I64_A32_S */
8988 2385,
8989 /* LOAD16_S_I64_A64 */
8990 2387,
8991 /* LOAD16_S_I64_A64_S */
8992 2391,
8993 /* LOAD16_U_I32_A32 */
8994 2393,
8995 /* LOAD16_U_I32_A32_S */
8996 2397,
8997 /* LOAD16_U_I32_A64 */
8998 2399,
8999 /* LOAD16_U_I32_A64_S */
9000 2403,
9001 /* LOAD16_U_I64_A32 */
9002 2405,
9003 /* LOAD16_U_I64_A32_S */
9004 2409,
9005 /* LOAD16_U_I64_A64 */
9006 2411,
9007 /* LOAD16_U_I64_A64_S */
9008 2415,
9009 /* LOAD32_SPLAT_A32 */
9010 2417,
9011 /* LOAD32_SPLAT_A32_S */
9012 2421,
9013 /* LOAD32_SPLAT_A64 */
9014 2423,
9015 /* LOAD32_SPLAT_A64_S */
9016 2427,
9017 /* LOAD32_S_I64_A32 */
9018 2429,
9019 /* LOAD32_S_I64_A32_S */
9020 2433,
9021 /* LOAD32_S_I64_A64 */
9022 2435,
9023 /* LOAD32_S_I64_A64_S */
9024 2439,
9025 /* LOAD32_U_I64_A32 */
9026 2441,
9027 /* LOAD32_U_I64_A32_S */
9028 2445,
9029 /* LOAD32_U_I64_A64 */
9030 2447,
9031 /* LOAD32_U_I64_A64_S */
9032 2451,
9033 /* LOAD64_SPLAT_A32 */
9034 2453,
9035 /* LOAD64_SPLAT_A32_S */
9036 2457,
9037 /* LOAD64_SPLAT_A64 */
9038 2459,
9039 /* LOAD64_SPLAT_A64_S */
9040 2463,
9041 /* LOAD8_SPLAT_A32 */
9042 2465,
9043 /* LOAD8_SPLAT_A32_S */
9044 2469,
9045 /* LOAD8_SPLAT_A64 */
9046 2471,
9047 /* LOAD8_SPLAT_A64_S */
9048 2475,
9049 /* LOAD8_S_I32_A32 */
9050 2477,
9051 /* LOAD8_S_I32_A32_S */
9052 2481,
9053 /* LOAD8_S_I32_A64 */
9054 2483,
9055 /* LOAD8_S_I32_A64_S */
9056 2487,
9057 /* LOAD8_S_I64_A32 */
9058 2489,
9059 /* LOAD8_S_I64_A32_S */
9060 2493,
9061 /* LOAD8_S_I64_A64 */
9062 2495,
9063 /* LOAD8_S_I64_A64_S */
9064 2499,
9065 /* LOAD8_U_I32_A32 */
9066 2501,
9067 /* LOAD8_U_I32_A32_S */
9068 2505,
9069 /* LOAD8_U_I32_A64 */
9070 2507,
9071 /* LOAD8_U_I32_A64_S */
9072 2511,
9073 /* LOAD8_U_I64_A32 */
9074 2513,
9075 /* LOAD8_U_I64_A32_S */
9076 2517,
9077 /* LOAD8_U_I64_A64 */
9078 2519,
9079 /* LOAD8_U_I64_A64_S */
9080 2523,
9081 /* LOAD_EXTEND_S_I16x8_A32 */
9082 2525,
9083 /* LOAD_EXTEND_S_I16x8_A32_S */
9084 2529,
9085 /* LOAD_EXTEND_S_I16x8_A64 */
9086 2531,
9087 /* LOAD_EXTEND_S_I16x8_A64_S */
9088 2535,
9089 /* LOAD_EXTEND_S_I32x4_A32 */
9090 2537,
9091 /* LOAD_EXTEND_S_I32x4_A32_S */
9092 2541,
9093 /* LOAD_EXTEND_S_I32x4_A64 */
9094 2543,
9095 /* LOAD_EXTEND_S_I32x4_A64_S */
9096 2547,
9097 /* LOAD_EXTEND_S_I64x2_A32 */
9098 2549,
9099 /* LOAD_EXTEND_S_I64x2_A32_S */
9100 2553,
9101 /* LOAD_EXTEND_S_I64x2_A64 */
9102 2555,
9103 /* LOAD_EXTEND_S_I64x2_A64_S */
9104 2559,
9105 /* LOAD_EXTEND_U_I16x8_A32 */
9106 2561,
9107 /* LOAD_EXTEND_U_I16x8_A32_S */
9108 2565,
9109 /* LOAD_EXTEND_U_I16x8_A64 */
9110 2567,
9111 /* LOAD_EXTEND_U_I16x8_A64_S */
9112 2571,
9113 /* LOAD_EXTEND_U_I32x4_A32 */
9114 2573,
9115 /* LOAD_EXTEND_U_I32x4_A32_S */
9116 2577,
9117 /* LOAD_EXTEND_U_I32x4_A64 */
9118 2579,
9119 /* LOAD_EXTEND_U_I32x4_A64_S */
9120 2583,
9121 /* LOAD_EXTEND_U_I64x2_A32 */
9122 2585,
9123 /* LOAD_EXTEND_U_I64x2_A32_S */
9124 2589,
9125 /* LOAD_EXTEND_U_I64x2_A64 */
9126 2591,
9127 /* LOAD_EXTEND_U_I64x2_A64_S */
9128 2595,
9129 /* LOAD_F16_F32_A32 */
9130 2597,
9131 /* LOAD_F16_F32_A32_S */
9132 2601,
9133 /* LOAD_F16_F32_A64 */
9134 2603,
9135 /* LOAD_F16_F32_A64_S */
9136 2607,
9137 /* LOAD_F32_A32 */
9138 2609,
9139 /* LOAD_F32_A32_S */
9140 2613,
9141 /* LOAD_F32_A64 */
9142 2615,
9143 /* LOAD_F32_A64_S */
9144 2619,
9145 /* LOAD_F64_A32 */
9146 2621,
9147 /* LOAD_F64_A32_S */
9148 2625,
9149 /* LOAD_F64_A64 */
9150 2627,
9151 /* LOAD_F64_A64_S */
9152 2631,
9153 /* LOAD_I32_A32 */
9154 2633,
9155 /* LOAD_I32_A32_S */
9156 2637,
9157 /* LOAD_I32_A64 */
9158 2639,
9159 /* LOAD_I32_A64_S */
9160 2643,
9161 /* LOAD_I64_A32 */
9162 2645,
9163 /* LOAD_I64_A32_S */
9164 2649,
9165 /* LOAD_I64_A64 */
9166 2651,
9167 /* LOAD_I64_A64_S */
9168 2655,
9169 /* LOAD_LANE_I16x8_A32 */
9170 2657,
9171 /* LOAD_LANE_I16x8_A32_S */
9172 2663,
9173 /* LOAD_LANE_I16x8_A64 */
9174 2666,
9175 /* LOAD_LANE_I16x8_A64_S */
9176 2672,
9177 /* LOAD_LANE_I32x4_A32 */
9178 2675,
9179 /* LOAD_LANE_I32x4_A32_S */
9180 2681,
9181 /* LOAD_LANE_I32x4_A64 */
9182 2684,
9183 /* LOAD_LANE_I32x4_A64_S */
9184 2690,
9185 /* LOAD_LANE_I64x2_A32 */
9186 2693,
9187 /* LOAD_LANE_I64x2_A32_S */
9188 2699,
9189 /* LOAD_LANE_I64x2_A64 */
9190 2702,
9191 /* LOAD_LANE_I64x2_A64_S */
9192 2708,
9193 /* LOAD_LANE_I8x16_A32 */
9194 2711,
9195 /* LOAD_LANE_I8x16_A32_S */
9196 2717,
9197 /* LOAD_LANE_I8x16_A64 */
9198 2720,
9199 /* LOAD_LANE_I8x16_A64_S */
9200 2726,
9201 /* LOAD_V128_A32 */
9202 2729,
9203 /* LOAD_V128_A32_S */
9204 2733,
9205 /* LOAD_V128_A64 */
9206 2735,
9207 /* LOAD_V128_A64_S */
9208 2739,
9209 /* LOAD_ZERO_I32x4_A32 */
9210 2741,
9211 /* LOAD_ZERO_I32x4_A32_S */
9212 2745,
9213 /* LOAD_ZERO_I32x4_A64 */
9214 2747,
9215 /* LOAD_ZERO_I32x4_A64_S */
9216 2751,
9217 /* LOAD_ZERO_I64x2_A32 */
9218 2753,
9219 /* LOAD_ZERO_I64x2_A32_S */
9220 2757,
9221 /* LOAD_ZERO_I64x2_A64 */
9222 2759,
9223 /* LOAD_ZERO_I64x2_A64_S */
9224 2763,
9225 /* LOCAL_GET_EXNREF */
9226 2765,
9227 /* LOCAL_GET_EXNREF_S */
9228 2767,
9229 /* LOCAL_GET_EXTERNREF */
9230 2768,
9231 /* LOCAL_GET_EXTERNREF_S */
9232 2770,
9233 /* LOCAL_GET_F32 */
9234 2771,
9235 /* LOCAL_GET_F32_S */
9236 2773,
9237 /* LOCAL_GET_F64 */
9238 2774,
9239 /* LOCAL_GET_F64_S */
9240 2776,
9241 /* LOCAL_GET_FUNCREF */
9242 2777,
9243 /* LOCAL_GET_FUNCREF_S */
9244 2779,
9245 /* LOCAL_GET_I32 */
9246 2780,
9247 /* LOCAL_GET_I32_S */
9248 2782,
9249 /* LOCAL_GET_I64 */
9250 2783,
9251 /* LOCAL_GET_I64_S */
9252 2785,
9253 /* LOCAL_GET_V128 */
9254 2786,
9255 /* LOCAL_GET_V128_S */
9256 2788,
9257 /* LOCAL_SET_EXNREF */
9258 2789,
9259 /* LOCAL_SET_EXNREF_S */
9260 2791,
9261 /* LOCAL_SET_EXTERNREF */
9262 2792,
9263 /* LOCAL_SET_EXTERNREF_S */
9264 2794,
9265 /* LOCAL_SET_F32 */
9266 2795,
9267 /* LOCAL_SET_F32_S */
9268 2797,
9269 /* LOCAL_SET_F64 */
9270 2798,
9271 /* LOCAL_SET_F64_S */
9272 2800,
9273 /* LOCAL_SET_FUNCREF */
9274 2801,
9275 /* LOCAL_SET_FUNCREF_S */
9276 2803,
9277 /* LOCAL_SET_I32 */
9278 2804,
9279 /* LOCAL_SET_I32_S */
9280 2806,
9281 /* LOCAL_SET_I64 */
9282 2807,
9283 /* LOCAL_SET_I64_S */
9284 2809,
9285 /* LOCAL_SET_V128 */
9286 2810,
9287 /* LOCAL_SET_V128_S */
9288 2812,
9289 /* LOCAL_TEE_EXNREF */
9290 2813,
9291 /* LOCAL_TEE_EXNREF_S */
9292 2816,
9293 /* LOCAL_TEE_EXTERNREF */
9294 2817,
9295 /* LOCAL_TEE_EXTERNREF_S */
9296 2820,
9297 /* LOCAL_TEE_F32 */
9298 2821,
9299 /* LOCAL_TEE_F32_S */
9300 2824,
9301 /* LOCAL_TEE_F64 */
9302 2825,
9303 /* LOCAL_TEE_F64_S */
9304 2828,
9305 /* LOCAL_TEE_FUNCREF */
9306 2829,
9307 /* LOCAL_TEE_FUNCREF_S */
9308 2832,
9309 /* LOCAL_TEE_I32 */
9310 2833,
9311 /* LOCAL_TEE_I32_S */
9312 2836,
9313 /* LOCAL_TEE_I64 */
9314 2837,
9315 /* LOCAL_TEE_I64_S */
9316 2840,
9317 /* LOCAL_TEE_V128 */
9318 2841,
9319 /* LOCAL_TEE_V128_S */
9320 2844,
9321 /* LOOP */
9322 2845,
9323 /* LOOP_S */
9324 2846,
9325 /* LT_F16x8 */
9326 2847,
9327 /* LT_F16x8_S */
9328 2850,
9329 /* LT_F32 */
9330 2850,
9331 /* LT_F32_S */
9332 2853,
9333 /* LT_F32x4 */
9334 2853,
9335 /* LT_F32x4_S */
9336 2856,
9337 /* LT_F64 */
9338 2856,
9339 /* LT_F64_S */
9340 2859,
9341 /* LT_F64x2 */
9342 2859,
9343 /* LT_F64x2_S */
9344 2862,
9345 /* LT_S_I16x8 */
9346 2862,
9347 /* LT_S_I16x8_S */
9348 2865,
9349 /* LT_S_I32 */
9350 2865,
9351 /* LT_S_I32_S */
9352 2868,
9353 /* LT_S_I32x4 */
9354 2868,
9355 /* LT_S_I32x4_S */
9356 2871,
9357 /* LT_S_I64 */
9358 2871,
9359 /* LT_S_I64_S */
9360 2874,
9361 /* LT_S_I64x2 */
9362 2874,
9363 /* LT_S_I64x2_S */
9364 2877,
9365 /* LT_S_I8x16 */
9366 2877,
9367 /* LT_S_I8x16_S */
9368 2880,
9369 /* LT_U_I16x8 */
9370 2880,
9371 /* LT_U_I16x8_S */
9372 2883,
9373 /* LT_U_I32 */
9374 2883,
9375 /* LT_U_I32_S */
9376 2886,
9377 /* LT_U_I32x4 */
9378 2886,
9379 /* LT_U_I32x4_S */
9380 2889,
9381 /* LT_U_I64 */
9382 2889,
9383 /* LT_U_I64_S */
9384 2892,
9385 /* LT_U_I8x16 */
9386 2892,
9387 /* LT_U_I8x16_S */
9388 2895,
9389 /* MADD_F16x8 */
9390 2895,
9391 /* MADD_F16x8_S */
9392 2899,
9393 /* MADD_F32x4 */
9394 2899,
9395 /* MADD_F32x4_S */
9396 2903,
9397 /* MADD_F64x2 */
9398 2903,
9399 /* MADD_F64x2_S */
9400 2907,
9401 /* MAX_F16x8 */
9402 2907,
9403 /* MAX_F16x8_S */
9404 2910,
9405 /* MAX_F32 */
9406 2910,
9407 /* MAX_F32_S */
9408 2913,
9409 /* MAX_F32x4 */
9410 2913,
9411 /* MAX_F32x4_S */
9412 2916,
9413 /* MAX_F64 */
9414 2916,
9415 /* MAX_F64_S */
9416 2919,
9417 /* MAX_F64x2 */
9418 2919,
9419 /* MAX_F64x2_S */
9420 2922,
9421 /* MAX_S_I16x8 */
9422 2922,
9423 /* MAX_S_I16x8_S */
9424 2925,
9425 /* MAX_S_I32x4 */
9426 2925,
9427 /* MAX_S_I32x4_S */
9428 2928,
9429 /* MAX_S_I8x16 */
9430 2928,
9431 /* MAX_S_I8x16_S */
9432 2931,
9433 /* MAX_U_I16x8 */
9434 2931,
9435 /* MAX_U_I16x8_S */
9436 2934,
9437 /* MAX_U_I32x4 */
9438 2934,
9439 /* MAX_U_I32x4_S */
9440 2937,
9441 /* MAX_U_I8x16 */
9442 2937,
9443 /* MAX_U_I8x16_S */
9444 2940,
9445 /* MEMORY_ATOMIC_NOTIFY_A32 */
9446 2940,
9447 /* MEMORY_ATOMIC_NOTIFY_A32_S */
9448 2945,
9449 /* MEMORY_ATOMIC_NOTIFY_A64 */
9450 2947,
9451 /* MEMORY_ATOMIC_NOTIFY_A64_S */
9452 2952,
9453 /* MEMORY_ATOMIC_WAIT32_A32 */
9454 2954,
9455 /* MEMORY_ATOMIC_WAIT32_A32_S */
9456 2960,
9457 /* MEMORY_ATOMIC_WAIT32_A64 */
9458 2962,
9459 /* MEMORY_ATOMIC_WAIT32_A64_S */
9460 2968,
9461 /* MEMORY_ATOMIC_WAIT64_A32 */
9462 2970,
9463 /* MEMORY_ATOMIC_WAIT64_A32_S */
9464 2976,
9465 /* MEMORY_ATOMIC_WAIT64_A64 */
9466 2978,
9467 /* MEMORY_ATOMIC_WAIT64_A64_S */
9468 2984,
9469 /* MIN_F16x8 */
9470 2986,
9471 /* MIN_F16x8_S */
9472 2989,
9473 /* MIN_F32 */
9474 2989,
9475 /* MIN_F32_S */
9476 2992,
9477 /* MIN_F32x4 */
9478 2992,
9479 /* MIN_F32x4_S */
9480 2995,
9481 /* MIN_F64 */
9482 2995,
9483 /* MIN_F64_S */
9484 2998,
9485 /* MIN_F64x2 */
9486 2998,
9487 /* MIN_F64x2_S */
9488 3001,
9489 /* MIN_S_I16x8 */
9490 3001,
9491 /* MIN_S_I16x8_S */
9492 3004,
9493 /* MIN_S_I32x4 */
9494 3004,
9495 /* MIN_S_I32x4_S */
9496 3007,
9497 /* MIN_S_I8x16 */
9498 3007,
9499 /* MIN_S_I8x16_S */
9500 3010,
9501 /* MIN_U_I16x8 */
9502 3010,
9503 /* MIN_U_I16x8_S */
9504 3013,
9505 /* MIN_U_I32x4 */
9506 3013,
9507 /* MIN_U_I32x4_S */
9508 3016,
9509 /* MIN_U_I8x16 */
9510 3016,
9511 /* MIN_U_I8x16_S */
9512 3019,
9513 /* MUL_F16x8 */
9514 3019,
9515 /* MUL_F16x8_S */
9516 3022,
9517 /* MUL_F32 */
9518 3022,
9519 /* MUL_F32_S */
9520 3025,
9521 /* MUL_F32x4 */
9522 3025,
9523 /* MUL_F32x4_S */
9524 3028,
9525 /* MUL_F64 */
9526 3028,
9527 /* MUL_F64_S */
9528 3031,
9529 /* MUL_F64x2 */
9530 3031,
9531 /* MUL_F64x2_S */
9532 3034,
9533 /* MUL_I16x8 */
9534 3034,
9535 /* MUL_I16x8_S */
9536 3037,
9537 /* MUL_I32 */
9538 3037,
9539 /* MUL_I32_S */
9540 3040,
9541 /* MUL_I32x4 */
9542 3040,
9543 /* MUL_I32x4_S */
9544 3043,
9545 /* MUL_I64 */
9546 3043,
9547 /* MUL_I64_S */
9548 3046,
9549 /* MUL_I64x2 */
9550 3046,
9551 /* MUL_I64x2_S */
9552 3049,
9553 /* NARROW_S_I16x8 */
9554 3049,
9555 /* NARROW_S_I16x8_S */
9556 3052,
9557 /* NARROW_S_I8x16 */
9558 3052,
9559 /* NARROW_S_I8x16_S */
9560 3055,
9561 /* NARROW_U_I16x8 */
9562 3055,
9563 /* NARROW_U_I16x8_S */
9564 3058,
9565 /* NARROW_U_I8x16 */
9566 3058,
9567 /* NARROW_U_I8x16_S */
9568 3061,
9569 /* NEAREST_F16x8 */
9570 3061,
9571 /* NEAREST_F16x8_S */
9572 3063,
9573 /* NEAREST_F32 */
9574 3063,
9575 /* NEAREST_F32_S */
9576 3065,
9577 /* NEAREST_F32x4 */
9578 3065,
9579 /* NEAREST_F32x4_S */
9580 3067,
9581 /* NEAREST_F64 */
9582 3067,
9583 /* NEAREST_F64_S */
9584 3069,
9585 /* NEAREST_F64x2 */
9586 3069,
9587 /* NEAREST_F64x2_S */
9588 3071,
9589 /* NEG_F16x8 */
9590 3071,
9591 /* NEG_F16x8_S */
9592 3073,
9593 /* NEG_F32 */
9594 3073,
9595 /* NEG_F32_S */
9596 3075,
9597 /* NEG_F32x4 */
9598 3075,
9599 /* NEG_F32x4_S */
9600 3077,
9601 /* NEG_F64 */
9602 3077,
9603 /* NEG_F64_S */
9604 3079,
9605 /* NEG_F64x2 */
9606 3079,
9607 /* NEG_F64x2_S */
9608 3081,
9609 /* NEG_I16x8 */
9610 3081,
9611 /* NEG_I16x8_S */
9612 3083,
9613 /* NEG_I32x4 */
9614 3083,
9615 /* NEG_I32x4_S */
9616 3085,
9617 /* NEG_I64x2 */
9618 3085,
9619 /* NEG_I64x2_S */
9620 3087,
9621 /* NEG_I8x16 */
9622 3087,
9623 /* NEG_I8x16_S */
9624 3089,
9625 /* NE_F16x8 */
9626 3089,
9627 /* NE_F16x8_S */
9628 3092,
9629 /* NE_F32 */
9630 3092,
9631 /* NE_F32_S */
9632 3095,
9633 /* NE_F32x4 */
9634 3095,
9635 /* NE_F32x4_S */
9636 3098,
9637 /* NE_F64 */
9638 3098,
9639 /* NE_F64_S */
9640 3101,
9641 /* NE_F64x2 */
9642 3101,
9643 /* NE_F64x2_S */
9644 3104,
9645 /* NE_I16x8 */
9646 3104,
9647 /* NE_I16x8_S */
9648 3107,
9649 /* NE_I32 */
9650 3107,
9651 /* NE_I32_S */
9652 3110,
9653 /* NE_I32x4 */
9654 3110,
9655 /* NE_I32x4_S */
9656 3113,
9657 /* NE_I64 */
9658 3113,
9659 /* NE_I64_S */
9660 3116,
9661 /* NE_I64x2 */
9662 3116,
9663 /* NE_I64x2_S */
9664 3119,
9665 /* NE_I8x16 */
9666 3119,
9667 /* NE_I8x16_S */
9668 3122,
9669 /* NMADD_F16x8 */
9670 3122,
9671 /* NMADD_F16x8_S */
9672 3126,
9673 /* NMADD_F32x4 */
9674 3126,
9675 /* NMADD_F32x4_S */
9676 3130,
9677 /* NMADD_F64x2 */
9678 3130,
9679 /* NMADD_F64x2_S */
9680 3134,
9681 /* NOP */
9682 3134,
9683 /* NOP_S */
9684 3134,
9685 /* NOT */
9686 3134,
9687 /* NOT_S */
9688 3136,
9689 /* OR */
9690 3136,
9691 /* OR_I32 */
9692 3139,
9693 /* OR_I32_S */
9694 3142,
9695 /* OR_I64 */
9696 3142,
9697 /* OR_I64_S */
9698 3145,
9699 /* OR_S */
9700 3145,
9701 /* PMAX_F16x8 */
9702 3145,
9703 /* PMAX_F16x8_S */
9704 3148,
9705 /* PMAX_F32x4 */
9706 3148,
9707 /* PMAX_F32x4_S */
9708 3151,
9709 /* PMAX_F64x2 */
9710 3151,
9711 /* PMAX_F64x2_S */
9712 3154,
9713 /* PMIN_F16x8 */
9714 3154,
9715 /* PMIN_F16x8_S */
9716 3157,
9717 /* PMIN_F32x4 */
9718 3157,
9719 /* PMIN_F32x4_S */
9720 3160,
9721 /* PMIN_F64x2 */
9722 3160,
9723 /* PMIN_F64x2_S */
9724 3163,
9725 /* POPCNT_I32 */
9726 3163,
9727 /* POPCNT_I32_S */
9728 3165,
9729 /* POPCNT_I64 */
9730 3165,
9731 /* POPCNT_I64_S */
9732 3167,
9733 /* POPCNT_I8x16 */
9734 3167,
9735 /* POPCNT_I8x16_S */
9736 3169,
9737 /* Q15MULR_SAT_S_I16x8 */
9738 3169,
9739 /* Q15MULR_SAT_S_I16x8_S */
9740 3172,
9741 /* REF_IS_NULL_EXNREF */
9742 3172,
9743 /* REF_IS_NULL_EXNREF_S */
9744 3174,
9745 /* REF_IS_NULL_EXTERNREF */
9746 3174,
9747 /* REF_IS_NULL_EXTERNREF_S */
9748 3176,
9749 /* REF_IS_NULL_FUNCREF */
9750 3176,
9751 /* REF_IS_NULL_FUNCREF_S */
9752 3178,
9753 /* REF_NULL_EXNREF */
9754 3178,
9755 /* REF_NULL_EXNREF_S */
9756 3179,
9757 /* REF_NULL_EXTERNREF */
9758 3179,
9759 /* REF_NULL_EXTERNREF_S */
9760 3180,
9761 /* REF_NULL_FUNCREF */
9762 3180,
9763 /* REF_NULL_FUNCREF_S */
9764 3181,
9765 /* RELAXED_DOT */
9766 3181,
9767 /* RELAXED_DOT_ADD */
9768 3184,
9769 /* RELAXED_DOT_ADD_S */
9770 3188,
9771 /* RELAXED_DOT_BFLOAT */
9772 3188,
9773 /* RELAXED_DOT_BFLOAT_S */
9774 3192,
9775 /* RELAXED_DOT_S */
9776 3192,
9777 /* RELAXED_Q15MULR_S_I16x8 */
9778 3192,
9779 /* RELAXED_Q15MULR_S_I16x8_S */
9780 3195,
9781 /* RELAXED_SWIZZLE */
9782 3195,
9783 /* RELAXED_SWIZZLE_S */
9784 3198,
9785 /* REM_S_I32 */
9786 3198,
9787 /* REM_S_I32_S */
9788 3201,
9789 /* REM_S_I64 */
9790 3201,
9791 /* REM_S_I64_S */
9792 3204,
9793 /* REM_U_I32 */
9794 3204,
9795 /* REM_U_I32_S */
9796 3207,
9797 /* REM_U_I64 */
9798 3207,
9799 /* REM_U_I64_S */
9800 3210,
9801 /* REPLACE_LANE_F32x4 */
9802 3210,
9803 /* REPLACE_LANE_F32x4_S */
9804 3214,
9805 /* REPLACE_LANE_F64x2 */
9806 3215,
9807 /* REPLACE_LANE_F64x2_S */
9808 3219,
9809 /* REPLACE_LANE_I16x8 */
9810 3220,
9811 /* REPLACE_LANE_I16x8_S */
9812 3224,
9813 /* REPLACE_LANE_I32x4 */
9814 3225,
9815 /* REPLACE_LANE_I32x4_S */
9816 3229,
9817 /* REPLACE_LANE_I64x2 */
9818 3230,
9819 /* REPLACE_LANE_I64x2_S */
9820 3234,
9821 /* REPLACE_LANE_I8x16 */
9822 3235,
9823 /* REPLACE_LANE_I8x16_S */
9824 3239,
9825 /* RETHROW */
9826 3240,
9827 /* RETHROW_S */
9828 3241,
9829 /* RETURN */
9830 3242,
9831 /* RETURN_S */
9832 3242,
9833 /* RET_CALL */
9834 3242,
9835 /* RET_CALL_INDIRECT */
9836 3243,
9837 /* RET_CALL_INDIRECT_S */
9838 3245,
9839 /* RET_CALL_S */
9840 3247,
9841 /* ROTL_I32 */
9842 3248,
9843 /* ROTL_I32_S */
9844 3251,
9845 /* ROTL_I64 */
9846 3251,
9847 /* ROTL_I64_S */
9848 3254,
9849 /* ROTR_I32 */
9850 3254,
9851 /* ROTR_I32_S */
9852 3257,
9853 /* ROTR_I64 */
9854 3257,
9855 /* ROTR_I64_S */
9856 3260,
9857 /* SELECT_EXNREF */
9858 3260,
9859 /* SELECT_EXNREF_S */
9860 3264,
9861 /* SELECT_EXTERNREF */
9862 3264,
9863 /* SELECT_EXTERNREF_S */
9864 3268,
9865 /* SELECT_F32 */
9866 3268,
9867 /* SELECT_F32_S */
9868 3272,
9869 /* SELECT_F64 */
9870 3272,
9871 /* SELECT_F64_S */
9872 3276,
9873 /* SELECT_FUNCREF */
9874 3276,
9875 /* SELECT_FUNCREF_S */
9876 3280,
9877 /* SELECT_I32 */
9878 3280,
9879 /* SELECT_I32_S */
9880 3284,
9881 /* SELECT_I64 */
9882 3284,
9883 /* SELECT_I64_S */
9884 3288,
9885 /* SELECT_V128 */
9886 3288,
9887 /* SELECT_V128_S */
9888 3292,
9889 /* SHL_I16x8 */
9890 3292,
9891 /* SHL_I16x8_S */
9892 3295,
9893 /* SHL_I32 */
9894 3295,
9895 /* SHL_I32_S */
9896 3298,
9897 /* SHL_I32x4 */
9898 3298,
9899 /* SHL_I32x4_S */
9900 3301,
9901 /* SHL_I64 */
9902 3301,
9903 /* SHL_I64_S */
9904 3304,
9905 /* SHL_I64x2 */
9906 3304,
9907 /* SHL_I64x2_S */
9908 3307,
9909 /* SHL_I8x16 */
9910 3307,
9911 /* SHL_I8x16_S */
9912 3310,
9913 /* SHR_S_I16x8 */
9914 3310,
9915 /* SHR_S_I16x8_S */
9916 3313,
9917 /* SHR_S_I32 */
9918 3313,
9919 /* SHR_S_I32_S */
9920 3316,
9921 /* SHR_S_I32x4 */
9922 3316,
9923 /* SHR_S_I32x4_S */
9924 3319,
9925 /* SHR_S_I64 */
9926 3319,
9927 /* SHR_S_I64_S */
9928 3322,
9929 /* SHR_S_I64x2 */
9930 3322,
9931 /* SHR_S_I64x2_S */
9932 3325,
9933 /* SHR_S_I8x16 */
9934 3325,
9935 /* SHR_S_I8x16_S */
9936 3328,
9937 /* SHR_U_I16x8 */
9938 3328,
9939 /* SHR_U_I16x8_S */
9940 3331,
9941 /* SHR_U_I32 */
9942 3331,
9943 /* SHR_U_I32_S */
9944 3334,
9945 /* SHR_U_I32x4 */
9946 3334,
9947 /* SHR_U_I32x4_S */
9948 3337,
9949 /* SHR_U_I64 */
9950 3337,
9951 /* SHR_U_I64_S */
9952 3340,
9953 /* SHR_U_I64x2 */
9954 3340,
9955 /* SHR_U_I64x2_S */
9956 3343,
9957 /* SHR_U_I8x16 */
9958 3343,
9959 /* SHR_U_I8x16_S */
9960 3346,
9961 /* SHUFFLE */
9962 3346,
9963 /* SHUFFLE_S */
9964 3365,
9965 /* SIMD_RELAXED_FMAX_F32x4 */
9966 3381,
9967 /* SIMD_RELAXED_FMAX_F32x4_S */
9968 3384,
9969 /* SIMD_RELAXED_FMAX_F64x2 */
9970 3384,
9971 /* SIMD_RELAXED_FMAX_F64x2_S */
9972 3387,
9973 /* SIMD_RELAXED_FMIN_F32x4 */
9974 3387,
9975 /* SIMD_RELAXED_FMIN_F32x4_S */
9976 3390,
9977 /* SIMD_RELAXED_FMIN_F64x2 */
9978 3390,
9979 /* SIMD_RELAXED_FMIN_F64x2_S */
9980 3393,
9981 /* SPLAT_F16x8 */
9982 3393,
9983 /* SPLAT_F16x8_S */
9984 3395,
9985 /* SPLAT_F32x4 */
9986 3395,
9987 /* SPLAT_F32x4_S */
9988 3397,
9989 /* SPLAT_F64x2 */
9990 3397,
9991 /* SPLAT_F64x2_S */
9992 3399,
9993 /* SPLAT_I16x8 */
9994 3399,
9995 /* SPLAT_I16x8_S */
9996 3401,
9997 /* SPLAT_I32x4 */
9998 3401,
9999 /* SPLAT_I32x4_S */
10000 3403,
10001 /* SPLAT_I64x2 */
10002 3403,
10003 /* SPLAT_I64x2_S */
10004 3405,
10005 /* SPLAT_I8x16 */
10006 3405,
10007 /* SPLAT_I8x16_S */
10008 3407,
10009 /* SQRT_F16x8 */
10010 3407,
10011 /* SQRT_F16x8_S */
10012 3409,
10013 /* SQRT_F32 */
10014 3409,
10015 /* SQRT_F32_S */
10016 3411,
10017 /* SQRT_F32x4 */
10018 3411,
10019 /* SQRT_F32x4_S */
10020 3413,
10021 /* SQRT_F64 */
10022 3413,
10023 /* SQRT_F64_S */
10024 3415,
10025 /* SQRT_F64x2 */
10026 3415,
10027 /* SQRT_F64x2_S */
10028 3417,
10029 /* STORE16_I32_A32 */
10030 3417,
10031 /* STORE16_I32_A32_S */
10032 3421,
10033 /* STORE16_I32_A64 */
10034 3423,
10035 /* STORE16_I32_A64_S */
10036 3427,
10037 /* STORE16_I64_A32 */
10038 3429,
10039 /* STORE16_I64_A32_S */
10040 3433,
10041 /* STORE16_I64_A64 */
10042 3435,
10043 /* STORE16_I64_A64_S */
10044 3439,
10045 /* STORE32_I64_A32 */
10046 3441,
10047 /* STORE32_I64_A32_S */
10048 3445,
10049 /* STORE32_I64_A64 */
10050 3447,
10051 /* STORE32_I64_A64_S */
10052 3451,
10053 /* STORE8_I32_A32 */
10054 3453,
10055 /* STORE8_I32_A32_S */
10056 3457,
10057 /* STORE8_I32_A64 */
10058 3459,
10059 /* STORE8_I32_A64_S */
10060 3463,
10061 /* STORE8_I64_A32 */
10062 3465,
10063 /* STORE8_I64_A32_S */
10064 3469,
10065 /* STORE8_I64_A64 */
10066 3471,
10067 /* STORE8_I64_A64_S */
10068 3475,
10069 /* STORE_F16_F32_A32 */
10070 3477,
10071 /* STORE_F16_F32_A32_S */
10072 3481,
10073 /* STORE_F16_F32_A64 */
10074 3483,
10075 /* STORE_F16_F32_A64_S */
10076 3487,
10077 /* STORE_F32_A32 */
10078 3489,
10079 /* STORE_F32_A32_S */
10080 3493,
10081 /* STORE_F32_A64 */
10082 3495,
10083 /* STORE_F32_A64_S */
10084 3499,
10085 /* STORE_F64_A32 */
10086 3501,
10087 /* STORE_F64_A32_S */
10088 3505,
10089 /* STORE_F64_A64 */
10090 3507,
10091 /* STORE_F64_A64_S */
10092 3511,
10093 /* STORE_I32_A32 */
10094 3513,
10095 /* STORE_I32_A32_S */
10096 3517,
10097 /* STORE_I32_A64 */
10098 3519,
10099 /* STORE_I32_A64_S */
10100 3523,
10101 /* STORE_I64_A32 */
10102 3525,
10103 /* STORE_I64_A32_S */
10104 3529,
10105 /* STORE_I64_A64 */
10106 3531,
10107 /* STORE_I64_A64_S */
10108 3535,
10109 /* STORE_LANE_I16x8_A32 */
10110 3537,
10111 /* STORE_LANE_I16x8_A32_S */
10112 3542,
10113 /* STORE_LANE_I16x8_A64 */
10114 3545,
10115 /* STORE_LANE_I16x8_A64_S */
10116 3550,
10117 /* STORE_LANE_I32x4_A32 */
10118 3553,
10119 /* STORE_LANE_I32x4_A32_S */
10120 3558,
10121 /* STORE_LANE_I32x4_A64 */
10122 3561,
10123 /* STORE_LANE_I32x4_A64_S */
10124 3566,
10125 /* STORE_LANE_I64x2_A32 */
10126 3569,
10127 /* STORE_LANE_I64x2_A32_S */
10128 3574,
10129 /* STORE_LANE_I64x2_A64 */
10130 3577,
10131 /* STORE_LANE_I64x2_A64_S */
10132 3582,
10133 /* STORE_LANE_I8x16_A32 */
10134 3585,
10135 /* STORE_LANE_I8x16_A32_S */
10136 3590,
10137 /* STORE_LANE_I8x16_A64 */
10138 3593,
10139 /* STORE_LANE_I8x16_A64_S */
10140 3598,
10141 /* STORE_V128_A32 */
10142 3601,
10143 /* STORE_V128_A32_S */
10144 3605,
10145 /* STORE_V128_A64 */
10146 3607,
10147 /* STORE_V128_A64_S */
10148 3611,
10149 /* SUB_F16x8 */
10150 3613,
10151 /* SUB_F16x8_S */
10152 3616,
10153 /* SUB_F32 */
10154 3616,
10155 /* SUB_F32_S */
10156 3619,
10157 /* SUB_F32x4 */
10158 3619,
10159 /* SUB_F32x4_S */
10160 3622,
10161 /* SUB_F64 */
10162 3622,
10163 /* SUB_F64_S */
10164 3625,
10165 /* SUB_F64x2 */
10166 3625,
10167 /* SUB_F64x2_S */
10168 3628,
10169 /* SUB_I16x8 */
10170 3628,
10171 /* SUB_I16x8_S */
10172 3631,
10173 /* SUB_I32 */
10174 3631,
10175 /* SUB_I32_S */
10176 3634,
10177 /* SUB_I32x4 */
10178 3634,
10179 /* SUB_I32x4_S */
10180 3637,
10181 /* SUB_I64 */
10182 3637,
10183 /* SUB_I64_S */
10184 3640,
10185 /* SUB_I64x2 */
10186 3640,
10187 /* SUB_I64x2_S */
10188 3643,
10189 /* SUB_I8x16 */
10190 3643,
10191 /* SUB_I8x16_S */
10192 3646,
10193 /* SUB_SAT_S_I16x8 */
10194 3646,
10195 /* SUB_SAT_S_I16x8_S */
10196 3649,
10197 /* SUB_SAT_S_I8x16 */
10198 3649,
10199 /* SUB_SAT_S_I8x16_S */
10200 3652,
10201 /* SUB_SAT_U_I16x8 */
10202 3652,
10203 /* SUB_SAT_U_I16x8_S */
10204 3655,
10205 /* SUB_SAT_U_I8x16 */
10206 3655,
10207 /* SUB_SAT_U_I8x16_S */
10208 3658,
10209 /* SWIZZLE */
10210 3658,
10211 /* SWIZZLE_S */
10212 3661,
10213 /* TABLE_COPY */
10214 3661,
10215 /* TABLE_COPY_S */
10216 3666,
10217 /* TABLE_FILL_EXNREF */
10218 3668,
10219 /* TABLE_FILL_EXNREF_S */
10220 3672,
10221 /* TABLE_FILL_EXTERNREF */
10222 3673,
10223 /* TABLE_FILL_EXTERNREF_S */
10224 3677,
10225 /* TABLE_FILL_FUNCREF */
10226 3678,
10227 /* TABLE_FILL_FUNCREF_S */
10228 3682,
10229 /* TABLE_GET_EXNREF */
10230 3683,
10231 /* TABLE_GET_EXNREF_S */
10232 3686,
10233 /* TABLE_GET_EXTERNREF */
10234 3687,
10235 /* TABLE_GET_EXTERNREF_S */
10236 3690,
10237 /* TABLE_GET_FUNCREF */
10238 3691,
10239 /* TABLE_GET_FUNCREF_S */
10240 3694,
10241 /* TABLE_GROW_EXNREF */
10242 3695,
10243 /* TABLE_GROW_EXNREF_S */
10244 3699,
10245 /* TABLE_GROW_EXTERNREF */
10246 3700,
10247 /* TABLE_GROW_EXTERNREF_S */
10248 3704,
10249 /* TABLE_GROW_FUNCREF */
10250 3705,
10251 /* TABLE_GROW_FUNCREF_S */
10252 3709,
10253 /* TABLE_SET_EXNREF */
10254 3710,
10255 /* TABLE_SET_EXNREF_S */
10256 3713,
10257 /* TABLE_SET_EXTERNREF */
10258 3714,
10259 /* TABLE_SET_EXTERNREF_S */
10260 3717,
10261 /* TABLE_SET_FUNCREF */
10262 3718,
10263 /* TABLE_SET_FUNCREF_S */
10264 3721,
10265 /* TABLE_SIZE */
10266 3722,
10267 /* TABLE_SIZE_S */
10268 3724,
10269 /* TEE_EXNREF */
10270 3725,
10271 /* TEE_EXNREF_S */
10272 3728,
10273 /* TEE_EXTERNREF */
10274 3728,
10275 /* TEE_EXTERNREF_S */
10276 3731,
10277 /* TEE_F32 */
10278 3731,
10279 /* TEE_F32_S */
10280 3734,
10281 /* TEE_F64 */
10282 3734,
10283 /* TEE_F64_S */
10284 3737,
10285 /* TEE_FUNCREF */
10286 3737,
10287 /* TEE_FUNCREF_S */
10288 3740,
10289 /* TEE_I32 */
10290 3740,
10291 /* TEE_I32_S */
10292 3743,
10293 /* TEE_I64 */
10294 3743,
10295 /* TEE_I64_S */
10296 3746,
10297 /* TEE_V128 */
10298 3746,
10299 /* TEE_V128_S */
10300 3749,
10301 /* THROW */
10302 3749,
10303 /* THROW_S */
10304 3750,
10305 /* TRUNC_F16x8 */
10306 3751,
10307 /* TRUNC_F16x8_S */
10308 3753,
10309 /* TRUNC_F32 */
10310 3753,
10311 /* TRUNC_F32_S */
10312 3755,
10313 /* TRUNC_F32x4 */
10314 3755,
10315 /* TRUNC_F32x4_S */
10316 3757,
10317 /* TRUNC_F64 */
10318 3757,
10319 /* TRUNC_F64_S */
10320 3759,
10321 /* TRUNC_F64x2 */
10322 3759,
10323 /* TRUNC_F64x2_S */
10324 3761,
10325 /* TRY */
10326 3761,
10327 /* TRY_S */
10328 3762,
10329 /* UNREACHABLE */
10330 3763,
10331 /* UNREACHABLE_S */
10332 3763,
10333 /* XOR */
10334 3763,
10335 /* XOR_I32 */
10336 3766,
10337 /* XOR_I32_S */
10338 3769,
10339 /* XOR_I64 */
10340 3769,
10341 /* XOR_I64_S */
10342 3772,
10343 /* XOR_S */
10344 3772,
10345 /* anonymous_8187MEMORY_GROW_A32 */
10346 3772,
10347 /* anonymous_8187MEMORY_GROW_A32_S */
10348 3775,
10349 /* anonymous_8187MEMORY_SIZE_A32 */
10350 3776,
10351 /* anonymous_8187MEMORY_SIZE_A32_S */
10352 3778,
10353 /* anonymous_8188MEMORY_GROW_A64 */
10354 3779,
10355 /* anonymous_8188MEMORY_GROW_A64_S */
10356 3782,
10357 /* anonymous_8188MEMORY_SIZE_A64 */
10358 3783,
10359 /* anonymous_8188MEMORY_SIZE_A64_S */
10360 3785,
10361 /* anonymous_8878DATA_DROP */
10362 3786,
10363 /* anonymous_8878DATA_DROP_S */
10364 3787,
10365 /* anonymous_8878MEMORY_COPY_A32 */
10366 3788,
10367 /* anonymous_8878MEMORY_COPY_A32_S */
10368 3793,
10369 /* anonymous_8878MEMORY_FILL_A32 */
10370 3795,
10371 /* anonymous_8878MEMORY_FILL_A32_S */
10372 3799,
10373 /* anonymous_8878MEMORY_INIT_A32 */
10374 3800,
10375 /* anonymous_8878MEMORY_INIT_A32_S */
10376 3805,
10377 /* anonymous_8879DATA_DROP */
10378 3807,
10379 /* anonymous_8879DATA_DROP_S */
10380 3808,
10381 /* anonymous_8879MEMORY_COPY_A64 */
10382 3809,
10383 /* anonymous_8879MEMORY_COPY_A64_S */
10384 3814,
10385 /* anonymous_8879MEMORY_FILL_A64 */
10386 3816,
10387 /* anonymous_8879MEMORY_FILL_A64_S */
10388 3820,
10389 /* anonymous_8879MEMORY_INIT_A64 */
10390 3821,
10391 /* anonymous_8879MEMORY_INIT_A64_S */
10392 3826,
10393 /* convert_low_s_F64x2 */
10394 3828,
10395 /* convert_low_s_F64x2_S */
10396 3830,
10397 /* convert_low_u_F64x2 */
10398 3830,
10399 /* convert_low_u_F64x2_S */
10400 3832,
10401 /* demote_zero_F32x4 */
10402 3832,
10403 /* demote_zero_F32x4_S */
10404 3834,
10405 /* extend_high_s_I16x8 */
10406 3834,
10407 /* extend_high_s_I16x8_S */
10408 3836,
10409 /* extend_high_s_I32x4 */
10410 3836,
10411 /* extend_high_s_I32x4_S */
10412 3838,
10413 /* extend_high_s_I64x2 */
10414 3838,
10415 /* extend_high_s_I64x2_S */
10416 3840,
10417 /* extend_high_u_I16x8 */
10418 3840,
10419 /* extend_high_u_I16x8_S */
10420 3842,
10421 /* extend_high_u_I32x4 */
10422 3842,
10423 /* extend_high_u_I32x4_S */
10424 3844,
10425 /* extend_high_u_I64x2 */
10426 3844,
10427 /* extend_high_u_I64x2_S */
10428 3846,
10429 /* extend_low_s_I16x8 */
10430 3846,
10431 /* extend_low_s_I16x8_S */
10432 3848,
10433 /* extend_low_s_I32x4 */
10434 3848,
10435 /* extend_low_s_I32x4_S */
10436 3850,
10437 /* extend_low_s_I64x2 */
10438 3850,
10439 /* extend_low_s_I64x2_S */
10440 3852,
10441 /* extend_low_u_I16x8 */
10442 3852,
10443 /* extend_low_u_I16x8_S */
10444 3854,
10445 /* extend_low_u_I32x4 */
10446 3854,
10447 /* extend_low_u_I32x4_S */
10448 3856,
10449 /* extend_low_u_I64x2 */
10450 3856,
10451 /* extend_low_u_I64x2_S */
10452 3858,
10453 /* fp_to_sint_I16x8 */
10454 3858,
10455 /* fp_to_sint_I16x8_S */
10456 3860,
10457 /* fp_to_sint_I32x4 */
10458 3860,
10459 /* fp_to_sint_I32x4_S */
10460 3862,
10461 /* fp_to_uint_I16x8 */
10462 3862,
10463 /* fp_to_uint_I16x8_S */
10464 3864,
10465 /* fp_to_uint_I32x4 */
10466 3864,
10467 /* fp_to_uint_I32x4_S */
10468 3866,
10469 /* int_wasm_extadd_pairwise_signed_I16x8 */
10470 3866,
10471 /* int_wasm_extadd_pairwise_signed_I16x8_S */
10472 3868,
10473 /* int_wasm_extadd_pairwise_signed_I32x4 */
10474 3868,
10475 /* int_wasm_extadd_pairwise_signed_I32x4_S */
10476 3870,
10477 /* int_wasm_extadd_pairwise_unsigned_I16x8 */
10478 3870,
10479 /* int_wasm_extadd_pairwise_unsigned_I16x8_S */
10480 3872,
10481 /* int_wasm_extadd_pairwise_unsigned_I32x4 */
10482 3872,
10483 /* int_wasm_extadd_pairwise_unsigned_I32x4_S */
10484 3874,
10485 /* int_wasm_relaxed_trunc_signed_I32x4 */
10486 3874,
10487 /* int_wasm_relaxed_trunc_signed_I32x4_S */
10488 3876,
10489 /* int_wasm_relaxed_trunc_signed_zero_I32x4 */
10490 3876,
10491 /* int_wasm_relaxed_trunc_signed_zero_I32x4_S */
10492 3878,
10493 /* int_wasm_relaxed_trunc_unsigned_I32x4 */
10494 3878,
10495 /* int_wasm_relaxed_trunc_unsigned_I32x4_S */
10496 3880,
10497 /* int_wasm_relaxed_trunc_unsigned_zero_I32x4 */
10498 3880,
10499 /* int_wasm_relaxed_trunc_unsigned_zero_I32x4_S */
10500 3882,
10501 /* promote_low_F64x2 */
10502 3882,
10503 /* promote_low_F64x2_S */
10504 3884,
10505 /* sint_to_fp_F16x8 */
10506 3884,
10507 /* sint_to_fp_F16x8_S */
10508 3886,
10509 /* sint_to_fp_F32x4 */
10510 3886,
10511 /* sint_to_fp_F32x4_S */
10512 3888,
10513 /* trunc_sat_zero_s_I32x4 */
10514 3888,
10515 /* trunc_sat_zero_s_I32x4_S */
10516 3890,
10517 /* trunc_sat_zero_u_I32x4 */
10518 3890,
10519 /* trunc_sat_zero_u_I32x4_S */
10520 3892,
10521 /* uint_to_fp_F16x8 */
10522 3892,
10523 /* uint_to_fp_F16x8_S */
10524 3894,
10525 /* uint_to_fp_F32x4 */
10526 3894,
10527 /* uint_to_fp_F32x4_S */
10528 3896,
10529 };
10530
10531 using namespace OpTypes;
10532 static const int8_t OpcodeOperandTypes[] = {
10533
10534 /* PHI */
10535 -1,
10536 /* INLINEASM */
10537 /* INLINEASM_BR */
10538 /* CFI_INSTRUCTION */
10539 i32imm,
10540 /* EH_LABEL */
10541 i32imm,
10542 /* GC_LABEL */
10543 i32imm,
10544 /* ANNOTATION_LABEL */
10545 i32imm,
10546 /* KILL */
10547 /* EXTRACT_SUBREG */
10548 -1, -1, i32imm,
10549 /* INSERT_SUBREG */
10550 -1, -1, -1, i32imm,
10551 /* IMPLICIT_DEF */
10552 -1,
10553 /* SUBREG_TO_REG */
10554 -1, -1, -1, i32imm,
10555 /* COPY_TO_REGCLASS */
10556 -1, -1, i32imm,
10557 /* DBG_VALUE */
10558 /* DBG_VALUE_LIST */
10559 /* DBG_INSTR_REF */
10560 /* DBG_PHI */
10561 /* DBG_LABEL */
10562 -1,
10563 /* REG_SEQUENCE */
10564 -1, -1,
10565 /* COPY */
10566 -1, -1,
10567 /* BUNDLE */
10568 /* LIFETIME_START */
10569 i32imm,
10570 /* LIFETIME_END */
10571 i32imm,
10572 /* PSEUDO_PROBE */
10573 i64imm, i64imm, i8imm, i32imm,
10574 /* ARITH_FENCE */
10575 -1, -1,
10576 /* STACKMAP */
10577 i64imm, i32imm,
10578 /* FENTRY_CALL */
10579 /* PATCHPOINT */
10580 -1, i64imm, i32imm, -1, i32imm, i32imm,
10581 /* LOAD_STACK_GUARD */
10582 -1,
10583 /* PREALLOCATED_SETUP */
10584 i32imm,
10585 /* PREALLOCATED_ARG */
10586 -1, i32imm, i32imm,
10587 /* STATEPOINT */
10588 /* LOCAL_ESCAPE */
10589 -1, i32imm,
10590 /* FAULTING_OP */
10591 -1,
10592 /* PATCHABLE_OP */
10593 /* PATCHABLE_FUNCTION_ENTER */
10594 /* PATCHABLE_RET */
10595 /* PATCHABLE_FUNCTION_EXIT */
10596 /* PATCHABLE_TAIL_CALL */
10597 /* PATCHABLE_EVENT_CALL */
10598 -1, -1,
10599 /* PATCHABLE_TYPED_EVENT_CALL */
10600 -1, -1, -1,
10601 /* ICALL_BRANCH_FUNNEL */
10602 /* MEMBARRIER */
10603 /* JUMP_TABLE_DEBUG_INFO */
10604 i64imm,
10605 /* CONVERGENCECTRL_ENTRY */
10606 -1,
10607 /* CONVERGENCECTRL_ANCHOR */
10608 -1,
10609 /* CONVERGENCECTRL_LOOP */
10610 -1, -1,
10611 /* CONVERGENCECTRL_GLUE */
10612 -1,
10613 /* G_ASSERT_SEXT */
10614 type0, type0, untyped_imm_0,
10615 /* G_ASSERT_ZEXT */
10616 type0, type0, untyped_imm_0,
10617 /* G_ASSERT_ALIGN */
10618 type0, type0, untyped_imm_0,
10619 /* G_ADD */
10620 type0, type0, type0,
10621 /* G_SUB */
10622 type0, type0, type0,
10623 /* G_MUL */
10624 type0, type0, type0,
10625 /* G_SDIV */
10626 type0, type0, type0,
10627 /* G_UDIV */
10628 type0, type0, type0,
10629 /* G_SREM */
10630 type0, type0, type0,
10631 /* G_UREM */
10632 type0, type0, type0,
10633 /* G_SDIVREM */
10634 type0, type0, type0, type0,
10635 /* G_UDIVREM */
10636 type0, type0, type0, type0,
10637 /* G_AND */
10638 type0, type0, type0,
10639 /* G_OR */
10640 type0, type0, type0,
10641 /* G_XOR */
10642 type0, type0, type0,
10643 /* G_IMPLICIT_DEF */
10644 type0,
10645 /* G_PHI */
10646 type0,
10647 /* G_FRAME_INDEX */
10648 type0, -1,
10649 /* G_GLOBAL_VALUE */
10650 type0, -1,
10651 /* G_PTRAUTH_GLOBAL_VALUE */
10652 type0, -1, i32imm, type1, i64imm,
10653 /* G_CONSTANT_POOL */
10654 type0, -1,
10655 /* G_EXTRACT */
10656 type0, type1, untyped_imm_0,
10657 /* G_UNMERGE_VALUES */
10658 type0, type1,
10659 /* G_INSERT */
10660 type0, type0, type1, untyped_imm_0,
10661 /* G_MERGE_VALUES */
10662 type0, type1,
10663 /* G_BUILD_VECTOR */
10664 type0, type1,
10665 /* G_BUILD_VECTOR_TRUNC */
10666 type0, type1,
10667 /* G_CONCAT_VECTORS */
10668 type0, type1,
10669 /* G_PTRTOINT */
10670 type0, type1,
10671 /* G_INTTOPTR */
10672 type0, type1,
10673 /* G_BITCAST */
10674 type0, type1,
10675 /* G_FREEZE */
10676 type0, type0,
10677 /* G_CONSTANT_FOLD_BARRIER */
10678 type0, type0,
10679 /* G_INTRINSIC_FPTRUNC_ROUND */
10680 type0, type1, i32imm,
10681 /* G_INTRINSIC_TRUNC */
10682 type0, type0,
10683 /* G_INTRINSIC_ROUND */
10684 type0, type0,
10685 /* G_INTRINSIC_LRINT */
10686 type0, type1,
10687 /* G_INTRINSIC_LLRINT */
10688 type0, type1,
10689 /* G_INTRINSIC_ROUNDEVEN */
10690 type0, type0,
10691 /* G_READCYCLECOUNTER */
10692 type0,
10693 /* G_READSTEADYCOUNTER */
10694 type0,
10695 /* G_LOAD */
10696 type0, ptype1,
10697 /* G_SEXTLOAD */
10698 type0, ptype1,
10699 /* G_ZEXTLOAD */
10700 type0, ptype1,
10701 /* G_INDEXED_LOAD */
10702 type0, ptype1, ptype1, type2, -1,
10703 /* G_INDEXED_SEXTLOAD */
10704 type0, ptype1, ptype1, type2, -1,
10705 /* G_INDEXED_ZEXTLOAD */
10706 type0, ptype1, ptype1, type2, -1,
10707 /* G_STORE */
10708 type0, ptype1,
10709 /* G_INDEXED_STORE */
10710 ptype0, type1, ptype0, ptype2, -1,
10711 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
10712 type0, type1, type2, type0, type0,
10713 /* G_ATOMIC_CMPXCHG */
10714 type0, ptype1, type0, type0,
10715 /* G_ATOMICRMW_XCHG */
10716 type0, ptype1, type0,
10717 /* G_ATOMICRMW_ADD */
10718 type0, ptype1, type0,
10719 /* G_ATOMICRMW_SUB */
10720 type0, ptype1, type0,
10721 /* G_ATOMICRMW_AND */
10722 type0, ptype1, type0,
10723 /* G_ATOMICRMW_NAND */
10724 type0, ptype1, type0,
10725 /* G_ATOMICRMW_OR */
10726 type0, ptype1, type0,
10727 /* G_ATOMICRMW_XOR */
10728 type0, ptype1, type0,
10729 /* G_ATOMICRMW_MAX */
10730 type0, ptype1, type0,
10731 /* G_ATOMICRMW_MIN */
10732 type0, ptype1, type0,
10733 /* G_ATOMICRMW_UMAX */
10734 type0, ptype1, type0,
10735 /* G_ATOMICRMW_UMIN */
10736 type0, ptype1, type0,
10737 /* G_ATOMICRMW_FADD */
10738 type0, ptype1, type0,
10739 /* G_ATOMICRMW_FSUB */
10740 type0, ptype1, type0,
10741 /* G_ATOMICRMW_FMAX */
10742 type0, ptype1, type0,
10743 /* G_ATOMICRMW_FMIN */
10744 type0, ptype1, type0,
10745 /* G_ATOMICRMW_UINC_WRAP */
10746 type0, ptype1, type0,
10747 /* G_ATOMICRMW_UDEC_WRAP */
10748 type0, ptype1, type0,
10749 /* G_FENCE */
10750 i32imm, i32imm,
10751 /* G_PREFETCH */
10752 ptype0, i32imm, i32imm, i32imm,
10753 /* G_BRCOND */
10754 type0, -1,
10755 /* G_BRINDIRECT */
10756 type0,
10757 /* G_INVOKE_REGION_START */
10758 /* G_INTRINSIC */
10759 -1,
10760 /* G_INTRINSIC_W_SIDE_EFFECTS */
10761 -1,
10762 /* G_INTRINSIC_CONVERGENT */
10763 -1,
10764 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
10765 -1,
10766 /* G_ANYEXT */
10767 type0, type1,
10768 /* G_TRUNC */
10769 type0, type1,
10770 /* G_CONSTANT */
10771 type0, -1,
10772 /* G_FCONSTANT */
10773 type0, -1,
10774 /* G_VASTART */
10775 type0,
10776 /* G_VAARG */
10777 type0, type1, -1,
10778 /* G_SEXT */
10779 type0, type1,
10780 /* G_SEXT_INREG */
10781 type0, type0, untyped_imm_0,
10782 /* G_ZEXT */
10783 type0, type1,
10784 /* G_SHL */
10785 type0, type0, type1,
10786 /* G_LSHR */
10787 type0, type0, type1,
10788 /* G_ASHR */
10789 type0, type0, type1,
10790 /* G_FSHL */
10791 type0, type0, type0, type1,
10792 /* G_FSHR */
10793 type0, type0, type0, type1,
10794 /* G_ROTR */
10795 type0, type0, type1,
10796 /* G_ROTL */
10797 type0, type0, type1,
10798 /* G_ICMP */
10799 type0, -1, type1, type1,
10800 /* G_FCMP */
10801 type0, -1, type1, type1,
10802 /* G_SCMP */
10803 type0, type1, type1,
10804 /* G_UCMP */
10805 type0, type1, type1,
10806 /* G_SELECT */
10807 type0, type1, type0, type0,
10808 /* G_UADDO */
10809 type0, type1, type0, type0,
10810 /* G_UADDE */
10811 type0, type1, type0, type0, type1,
10812 /* G_USUBO */
10813 type0, type1, type0, type0,
10814 /* G_USUBE */
10815 type0, type1, type0, type0, type1,
10816 /* G_SADDO */
10817 type0, type1, type0, type0,
10818 /* G_SADDE */
10819 type0, type1, type0, type0, type1,
10820 /* G_SSUBO */
10821 type0, type1, type0, type0,
10822 /* G_SSUBE */
10823 type0, type1, type0, type0, type1,
10824 /* G_UMULO */
10825 type0, type1, type0, type0,
10826 /* G_SMULO */
10827 type0, type1, type0, type0,
10828 /* G_UMULH */
10829 type0, type0, type0,
10830 /* G_SMULH */
10831 type0, type0, type0,
10832 /* G_UADDSAT */
10833 type0, type0, type0,
10834 /* G_SADDSAT */
10835 type0, type0, type0,
10836 /* G_USUBSAT */
10837 type0, type0, type0,
10838 /* G_SSUBSAT */
10839 type0, type0, type0,
10840 /* G_USHLSAT */
10841 type0, type0, type1,
10842 /* G_SSHLSAT */
10843 type0, type0, type1,
10844 /* G_SMULFIX */
10845 type0, type0, type0, untyped_imm_0,
10846 /* G_UMULFIX */
10847 type0, type0, type0, untyped_imm_0,
10848 /* G_SMULFIXSAT */
10849 type0, type0, type0, untyped_imm_0,
10850 /* G_UMULFIXSAT */
10851 type0, type0, type0, untyped_imm_0,
10852 /* G_SDIVFIX */
10853 type0, type0, type0, untyped_imm_0,
10854 /* G_UDIVFIX */
10855 type0, type0, type0, untyped_imm_0,
10856 /* G_SDIVFIXSAT */
10857 type0, type0, type0, untyped_imm_0,
10858 /* G_UDIVFIXSAT */
10859 type0, type0, type0, untyped_imm_0,
10860 /* G_FADD */
10861 type0, type0, type0,
10862 /* G_FSUB */
10863 type0, type0, type0,
10864 /* G_FMUL */
10865 type0, type0, type0,
10866 /* G_FMA */
10867 type0, type0, type0, type0,
10868 /* G_FMAD */
10869 type0, type0, type0, type0,
10870 /* G_FDIV */
10871 type0, type0, type0,
10872 /* G_FREM */
10873 type0, type0, type0,
10874 /* G_FPOW */
10875 type0, type0, type0,
10876 /* G_FPOWI */
10877 type0, type0, type1,
10878 /* G_FEXP */
10879 type0, type0,
10880 /* G_FEXP2 */
10881 type0, type0,
10882 /* G_FEXP10 */
10883 type0, type0,
10884 /* G_FLOG */
10885 type0, type0,
10886 /* G_FLOG2 */
10887 type0, type0,
10888 /* G_FLOG10 */
10889 type0, type0,
10890 /* G_FLDEXP */
10891 type0, type0, type1,
10892 /* G_FFREXP */
10893 type0, type1, type0,
10894 /* G_FNEG */
10895 type0, type0,
10896 /* G_FPEXT */
10897 type0, type1,
10898 /* G_FPTRUNC */
10899 type0, type1,
10900 /* G_FPTOSI */
10901 type0, type1,
10902 /* G_FPTOUI */
10903 type0, type1,
10904 /* G_SITOFP */
10905 type0, type1,
10906 /* G_UITOFP */
10907 type0, type1,
10908 /* G_FABS */
10909 type0, type0,
10910 /* G_FCOPYSIGN */
10911 type0, type0, type1,
10912 /* G_IS_FPCLASS */
10913 type0, type1, -1,
10914 /* G_FCANONICALIZE */
10915 type0, type0,
10916 /* G_FMINNUM */
10917 type0, type0, type0,
10918 /* G_FMAXNUM */
10919 type0, type0, type0,
10920 /* G_FMINNUM_IEEE */
10921 type0, type0, type0,
10922 /* G_FMAXNUM_IEEE */
10923 type0, type0, type0,
10924 /* G_FMINIMUM */
10925 type0, type0, type0,
10926 /* G_FMAXIMUM */
10927 type0, type0, type0,
10928 /* G_GET_FPENV */
10929 type0,
10930 /* G_SET_FPENV */
10931 type0,
10932 /* G_RESET_FPENV */
10933 /* G_GET_FPMODE */
10934 type0,
10935 /* G_SET_FPMODE */
10936 type0,
10937 /* G_RESET_FPMODE */
10938 /* G_PTR_ADD */
10939 ptype0, ptype0, type1,
10940 /* G_PTRMASK */
10941 ptype0, ptype0, type1,
10942 /* G_SMIN */
10943 type0, type0, type0,
10944 /* G_SMAX */
10945 type0, type0, type0,
10946 /* G_UMIN */
10947 type0, type0, type0,
10948 /* G_UMAX */
10949 type0, type0, type0,
10950 /* G_ABS */
10951 type0, type0,
10952 /* G_LROUND */
10953 type0, type1,
10954 /* G_LLROUND */
10955 type0, type1,
10956 /* G_BR */
10957 -1,
10958 /* G_BRJT */
10959 ptype0, -1, type1,
10960 /* G_VSCALE */
10961 type0, -1,
10962 /* G_INSERT_SUBVECTOR */
10963 type0, type0, type1, untyped_imm_0,
10964 /* G_EXTRACT_SUBVECTOR */
10965 type0, type0, untyped_imm_0,
10966 /* G_INSERT_VECTOR_ELT */
10967 type0, type0, type1, type2,
10968 /* G_EXTRACT_VECTOR_ELT */
10969 type0, type1, type2,
10970 /* G_SHUFFLE_VECTOR */
10971 type0, type1, type1, -1,
10972 /* G_SPLAT_VECTOR */
10973 type0, type1,
10974 /* G_VECTOR_COMPRESS */
10975 type0, type0, type1, type0,
10976 /* G_CTTZ */
10977 type0, type1,
10978 /* G_CTTZ_ZERO_UNDEF */
10979 type0, type1,
10980 /* G_CTLZ */
10981 type0, type1,
10982 /* G_CTLZ_ZERO_UNDEF */
10983 type0, type1,
10984 /* G_CTPOP */
10985 type0, type1,
10986 /* G_BSWAP */
10987 type0, type0,
10988 /* G_BITREVERSE */
10989 type0, type0,
10990 /* G_FCEIL */
10991 type0, type0,
10992 /* G_FCOS */
10993 type0, type0,
10994 /* G_FSIN */
10995 type0, type0,
10996 /* G_FTAN */
10997 type0, type0,
10998 /* G_FACOS */
10999 type0, type0,
11000 /* G_FASIN */
11001 type0, type0,
11002 /* G_FATAN */
11003 type0, type0,
11004 /* G_FCOSH */
11005 type0, type0,
11006 /* G_FSINH */
11007 type0, type0,
11008 /* G_FTANH */
11009 type0, type0,
11010 /* G_FSQRT */
11011 type0, type0,
11012 /* G_FFLOOR */
11013 type0, type0,
11014 /* G_FRINT */
11015 type0, type0,
11016 /* G_FNEARBYINT */
11017 type0, type0,
11018 /* G_ADDRSPACE_CAST */
11019 type0, type1,
11020 /* G_BLOCK_ADDR */
11021 type0, -1,
11022 /* G_JUMP_TABLE */
11023 type0, -1,
11024 /* G_DYN_STACKALLOC */
11025 ptype0, type1, i32imm,
11026 /* G_STACKSAVE */
11027 ptype0,
11028 /* G_STACKRESTORE */
11029 ptype0,
11030 /* G_STRICT_FADD */
11031 type0, type0, type0,
11032 /* G_STRICT_FSUB */
11033 type0, type0, type0,
11034 /* G_STRICT_FMUL */
11035 type0, type0, type0,
11036 /* G_STRICT_FDIV */
11037 type0, type0, type0,
11038 /* G_STRICT_FREM */
11039 type0, type0, type0,
11040 /* G_STRICT_FMA */
11041 type0, type0, type0, type0,
11042 /* G_STRICT_FSQRT */
11043 type0, type0,
11044 /* G_STRICT_FLDEXP */
11045 type0, type0, type1,
11046 /* G_READ_REGISTER */
11047 type0, -1,
11048 /* G_WRITE_REGISTER */
11049 -1, type0,
11050 /* G_MEMCPY */
11051 ptype0, ptype1, type2, untyped_imm_0,
11052 /* G_MEMCPY_INLINE */
11053 ptype0, ptype1, type2,
11054 /* G_MEMMOVE */
11055 ptype0, ptype1, type2, untyped_imm_0,
11056 /* G_MEMSET */
11057 ptype0, type1, type2, untyped_imm_0,
11058 /* G_BZERO */
11059 ptype0, type1, untyped_imm_0,
11060 /* G_TRAP */
11061 /* G_DEBUGTRAP */
11062 /* G_UBSANTRAP */
11063 i8imm,
11064 /* G_VECREDUCE_SEQ_FADD */
11065 type0, type1, type2,
11066 /* G_VECREDUCE_SEQ_FMUL */
11067 type0, type1, type2,
11068 /* G_VECREDUCE_FADD */
11069 type0, type1,
11070 /* G_VECREDUCE_FMUL */
11071 type0, type1,
11072 /* G_VECREDUCE_FMAX */
11073 type0, type1,
11074 /* G_VECREDUCE_FMIN */
11075 type0, type1,
11076 /* G_VECREDUCE_FMAXIMUM */
11077 type0, type1,
11078 /* G_VECREDUCE_FMINIMUM */
11079 type0, type1,
11080 /* G_VECREDUCE_ADD */
11081 type0, type1,
11082 /* G_VECREDUCE_MUL */
11083 type0, type1,
11084 /* G_VECREDUCE_AND */
11085 type0, type1,
11086 /* G_VECREDUCE_OR */
11087 type0, type1,
11088 /* G_VECREDUCE_XOR */
11089 type0, type1,
11090 /* G_VECREDUCE_SMAX */
11091 type0, type1,
11092 /* G_VECREDUCE_SMIN */
11093 type0, type1,
11094 /* G_VECREDUCE_UMAX */
11095 type0, type1,
11096 /* G_VECREDUCE_UMIN */
11097 type0, type1,
11098 /* G_SBFX */
11099 type0, type0, type1, type1,
11100 /* G_UBFX */
11101 type0, type0, type1, type1,
11102 /* CALL_PARAMS */
11103 function32_op,
11104 /* CALL_PARAMS_S */
11105 function32_op,
11106 /* CALL_RESULTS */
11107 /* CALL_RESULTS_S */
11108 /* CATCHRET */
11109 bb_op, bb_op,
11110 /* CATCHRET_S */
11111 bb_op, bb_op,
11112 /* CLEANUPRET */
11113 /* CLEANUPRET_S */
11114 /* COMPILER_FENCE */
11115 /* COMPILER_FENCE_S */
11116 /* RET_CALL_RESULTS */
11117 /* RET_CALL_RESULTS_S */
11118 /* ABS_F16x8 */
11119 V128, V128,
11120 /* ABS_F16x8_S */
11121 /* ABS_F32 */
11122 F32, F32,
11123 /* ABS_F32_S */
11124 /* ABS_F32x4 */
11125 V128, V128,
11126 /* ABS_F32x4_S */
11127 /* ABS_F64 */
11128 F64, F64,
11129 /* ABS_F64_S */
11130 /* ABS_F64x2 */
11131 V128, V128,
11132 /* ABS_F64x2_S */
11133 /* ABS_I16x8 */
11134 V128, V128,
11135 /* ABS_I16x8_S */
11136 /* ABS_I32x4 */
11137 V128, V128,
11138 /* ABS_I32x4_S */
11139 /* ABS_I64x2 */
11140 V128, V128,
11141 /* ABS_I64x2_S */
11142 /* ABS_I8x16 */
11143 V128, V128,
11144 /* ABS_I8x16_S */
11145 /* ADD_F16x8 */
11146 V128, V128, V128,
11147 /* ADD_F16x8_S */
11148 /* ADD_F32 */
11149 F32, F32, F32,
11150 /* ADD_F32_S */
11151 /* ADD_F32x4 */
11152 V128, V128, V128,
11153 /* ADD_F32x4_S */
11154 /* ADD_F64 */
11155 F64, F64, F64,
11156 /* ADD_F64_S */
11157 /* ADD_F64x2 */
11158 V128, V128, V128,
11159 /* ADD_F64x2_S */
11160 /* ADD_I16x8 */
11161 V128, V128, V128,
11162 /* ADD_I16x8_S */
11163 /* ADD_I32 */
11164 I32, I32, I32,
11165 /* ADD_I32_S */
11166 /* ADD_I32x4 */
11167 V128, V128, V128,
11168 /* ADD_I32x4_S */
11169 /* ADD_I64 */
11170 I64, I64, I64,
11171 /* ADD_I64_S */
11172 /* ADD_I64x2 */
11173 V128, V128, V128,
11174 /* ADD_I64x2_S */
11175 /* ADD_I8x16 */
11176 V128, V128, V128,
11177 /* ADD_I8x16_S */
11178 /* ADD_SAT_S_I16x8 */
11179 V128, V128, V128,
11180 /* ADD_SAT_S_I16x8_S */
11181 /* ADD_SAT_S_I8x16 */
11182 V128, V128, V128,
11183 /* ADD_SAT_S_I8x16_S */
11184 /* ADD_SAT_U_I16x8 */
11185 V128, V128, V128,
11186 /* ADD_SAT_U_I16x8_S */
11187 /* ADD_SAT_U_I8x16 */
11188 V128, V128, V128,
11189 /* ADD_SAT_U_I8x16_S */
11190 /* ADJCALLSTACKDOWN */
11191 i32imm, i32imm,
11192 /* ADJCALLSTACKDOWN_S */
11193 i32imm, i32imm,
11194 /* ADJCALLSTACKUP */
11195 i32imm, i32imm,
11196 /* ADJCALLSTACKUP_S */
11197 i32imm, i32imm,
11198 /* ALLTRUE_I16x8 */
11199 I32, V128,
11200 /* ALLTRUE_I16x8_S */
11201 /* ALLTRUE_I32x4 */
11202 I32, V128,
11203 /* ALLTRUE_I32x4_S */
11204 /* ALLTRUE_I64x2 */
11205 I32, V128,
11206 /* ALLTRUE_I64x2_S */
11207 /* ALLTRUE_I8x16 */
11208 I32, V128,
11209 /* ALLTRUE_I8x16_S */
11210 /* AND */
11211 V128, V128, V128,
11212 /* ANDNOT */
11213 V128, V128, V128,
11214 /* ANDNOT_S */
11215 /* AND_I32 */
11216 I32, I32, I32,
11217 /* AND_I32_S */
11218 /* AND_I64 */
11219 I64, I64, I64,
11220 /* AND_I64_S */
11221 /* AND_S */
11222 /* ANYTRUE */
11223 I32, V128,
11224 /* ANYTRUE_S */
11225 /* ARGUMENT_exnref */
11226 EXNREF, i32imm,
11227 /* ARGUMENT_exnref_S */
11228 i32imm,
11229 /* ARGUMENT_externref */
11230 EXTERNREF, i32imm,
11231 /* ARGUMENT_externref_S */
11232 i32imm,
11233 /* ARGUMENT_f32 */
11234 F32, i32imm,
11235 /* ARGUMENT_f32_S */
11236 i32imm,
11237 /* ARGUMENT_f64 */
11238 F64, i32imm,
11239 /* ARGUMENT_f64_S */
11240 i32imm,
11241 /* ARGUMENT_funcref */
11242 FUNCREF, i32imm,
11243 /* ARGUMENT_funcref_S */
11244 i32imm,
11245 /* ARGUMENT_i32 */
11246 I32, i32imm,
11247 /* ARGUMENT_i32_S */
11248 i32imm,
11249 /* ARGUMENT_i64 */
11250 I64, i32imm,
11251 /* ARGUMENT_i64_S */
11252 i32imm,
11253 /* ARGUMENT_v16i8 */
11254 V128, i32imm,
11255 /* ARGUMENT_v16i8_S */
11256 i32imm,
11257 /* ARGUMENT_v2f64 */
11258 V128, i32imm,
11259 /* ARGUMENT_v2f64_S */
11260 i32imm,
11261 /* ARGUMENT_v2i64 */
11262 V128, i32imm,
11263 /* ARGUMENT_v2i64_S */
11264 i32imm,
11265 /* ARGUMENT_v4f32 */
11266 V128, i32imm,
11267 /* ARGUMENT_v4f32_S */
11268 i32imm,
11269 /* ARGUMENT_v4i32 */
11270 V128, i32imm,
11271 /* ARGUMENT_v4i32_S */
11272 i32imm,
11273 /* ARGUMENT_v8f16 */
11274 V128, i32imm,
11275 /* ARGUMENT_v8f16_S */
11276 i32imm,
11277 /* ARGUMENT_v8i16 */
11278 V128, i32imm,
11279 /* ARGUMENT_v8i16_S */
11280 i32imm,
11281 /* ATOMIC_FENCE */
11282 i8imm,
11283 /* ATOMIC_FENCE_S */
11284 i8imm,
11285 /* ATOMIC_LOAD16_U_I32_A32 */
11286 I32, P2Align, offset32_op, I32,
11287 /* ATOMIC_LOAD16_U_I32_A32_S */
11288 P2Align, offset32_op,
11289 /* ATOMIC_LOAD16_U_I32_A64 */
11290 I32, P2Align, offset64_op, I64,
11291 /* ATOMIC_LOAD16_U_I32_A64_S */
11292 P2Align, offset64_op,
11293 /* ATOMIC_LOAD16_U_I64_A32 */
11294 I64, P2Align, offset32_op, I32,
11295 /* ATOMIC_LOAD16_U_I64_A32_S */
11296 P2Align, offset32_op,
11297 /* ATOMIC_LOAD16_U_I64_A64 */
11298 I64, P2Align, offset64_op, I64,
11299 /* ATOMIC_LOAD16_U_I64_A64_S */
11300 P2Align, offset64_op,
11301 /* ATOMIC_LOAD32_U_I64_A32 */
11302 I64, P2Align, offset32_op, I32,
11303 /* ATOMIC_LOAD32_U_I64_A32_S */
11304 P2Align, offset32_op,
11305 /* ATOMIC_LOAD32_U_I64_A64 */
11306 I64, P2Align, offset64_op, I64,
11307 /* ATOMIC_LOAD32_U_I64_A64_S */
11308 P2Align, offset64_op,
11309 /* ATOMIC_LOAD8_U_I32_A32 */
11310 I32, P2Align, offset32_op, I32,
11311 /* ATOMIC_LOAD8_U_I32_A32_S */
11312 P2Align, offset32_op,
11313 /* ATOMIC_LOAD8_U_I32_A64 */
11314 I32, P2Align, offset64_op, I64,
11315 /* ATOMIC_LOAD8_U_I32_A64_S */
11316 P2Align, offset64_op,
11317 /* ATOMIC_LOAD8_U_I64_A32 */
11318 I64, P2Align, offset32_op, I32,
11319 /* ATOMIC_LOAD8_U_I64_A32_S */
11320 P2Align, offset32_op,
11321 /* ATOMIC_LOAD8_U_I64_A64 */
11322 I64, P2Align, offset64_op, I64,
11323 /* ATOMIC_LOAD8_U_I64_A64_S */
11324 P2Align, offset64_op,
11325 /* ATOMIC_LOAD_I32_A32 */
11326 I32, P2Align, offset32_op, I32,
11327 /* ATOMIC_LOAD_I32_A32_S */
11328 P2Align, offset32_op,
11329 /* ATOMIC_LOAD_I32_A64 */
11330 I32, P2Align, offset64_op, I64,
11331 /* ATOMIC_LOAD_I32_A64_S */
11332 P2Align, offset64_op,
11333 /* ATOMIC_LOAD_I64_A32 */
11334 I64, P2Align, offset32_op, I32,
11335 /* ATOMIC_LOAD_I64_A32_S */
11336 P2Align, offset32_op,
11337 /* ATOMIC_LOAD_I64_A64 */
11338 I64, P2Align, offset64_op, I64,
11339 /* ATOMIC_LOAD_I64_A64_S */
11340 P2Align, offset64_op,
11341 /* ATOMIC_RMW16_U_ADD_I32_A32 */
11342 I32, P2Align, offset32_op, I32, I32,
11343 /* ATOMIC_RMW16_U_ADD_I32_A32_S */
11344 P2Align, offset32_op,
11345 /* ATOMIC_RMW16_U_ADD_I32_A64 */
11346 I32, P2Align, offset64_op, I64, I32,
11347 /* ATOMIC_RMW16_U_ADD_I32_A64_S */
11348 P2Align, offset64_op,
11349 /* ATOMIC_RMW16_U_ADD_I64_A32 */
11350 I64, P2Align, offset32_op, I32, I64,
11351 /* ATOMIC_RMW16_U_ADD_I64_A32_S */
11352 P2Align, offset32_op,
11353 /* ATOMIC_RMW16_U_ADD_I64_A64 */
11354 I64, P2Align, offset64_op, I64, I64,
11355 /* ATOMIC_RMW16_U_ADD_I64_A64_S */
11356 P2Align, offset64_op,
11357 /* ATOMIC_RMW16_U_AND_I32_A32 */
11358 I32, P2Align, offset32_op, I32, I32,
11359 /* ATOMIC_RMW16_U_AND_I32_A32_S */
11360 P2Align, offset32_op,
11361 /* ATOMIC_RMW16_U_AND_I32_A64 */
11362 I32, P2Align, offset64_op, I64, I32,
11363 /* ATOMIC_RMW16_U_AND_I32_A64_S */
11364 P2Align, offset64_op,
11365 /* ATOMIC_RMW16_U_AND_I64_A32 */
11366 I64, P2Align, offset32_op, I32, I64,
11367 /* ATOMIC_RMW16_U_AND_I64_A32_S */
11368 P2Align, offset32_op,
11369 /* ATOMIC_RMW16_U_AND_I64_A64 */
11370 I64, P2Align, offset64_op, I64, I64,
11371 /* ATOMIC_RMW16_U_AND_I64_A64_S */
11372 P2Align, offset64_op,
11373 /* ATOMIC_RMW16_U_CMPXCHG_I32_A32 */
11374 I32, P2Align, offset32_op, I32, I32, I32,
11375 /* ATOMIC_RMW16_U_CMPXCHG_I32_A32_S */
11376 P2Align, offset32_op,
11377 /* ATOMIC_RMW16_U_CMPXCHG_I32_A64 */
11378 I32, P2Align, offset64_op, I64, I32, I32,
11379 /* ATOMIC_RMW16_U_CMPXCHG_I32_A64_S */
11380 P2Align, offset64_op,
11381 /* ATOMIC_RMW16_U_CMPXCHG_I64_A32 */
11382 I64, P2Align, offset32_op, I32, I64, I64,
11383 /* ATOMIC_RMW16_U_CMPXCHG_I64_A32_S */
11384 P2Align, offset32_op,
11385 /* ATOMIC_RMW16_U_CMPXCHG_I64_A64 */
11386 I64, P2Align, offset64_op, I64, I64, I64,
11387 /* ATOMIC_RMW16_U_CMPXCHG_I64_A64_S */
11388 P2Align, offset64_op,
11389 /* ATOMIC_RMW16_U_OR_I32_A32 */
11390 I32, P2Align, offset32_op, I32, I32,
11391 /* ATOMIC_RMW16_U_OR_I32_A32_S */
11392 P2Align, offset32_op,
11393 /* ATOMIC_RMW16_U_OR_I32_A64 */
11394 I32, P2Align, offset64_op, I64, I32,
11395 /* ATOMIC_RMW16_U_OR_I32_A64_S */
11396 P2Align, offset64_op,
11397 /* ATOMIC_RMW16_U_OR_I64_A32 */
11398 I64, P2Align, offset32_op, I32, I64,
11399 /* ATOMIC_RMW16_U_OR_I64_A32_S */
11400 P2Align, offset32_op,
11401 /* ATOMIC_RMW16_U_OR_I64_A64 */
11402 I64, P2Align, offset64_op, I64, I64,
11403 /* ATOMIC_RMW16_U_OR_I64_A64_S */
11404 P2Align, offset64_op,
11405 /* ATOMIC_RMW16_U_SUB_I32_A32 */
11406 I32, P2Align, offset32_op, I32, I32,
11407 /* ATOMIC_RMW16_U_SUB_I32_A32_S */
11408 P2Align, offset32_op,
11409 /* ATOMIC_RMW16_U_SUB_I32_A64 */
11410 I32, P2Align, offset64_op, I64, I32,
11411 /* ATOMIC_RMW16_U_SUB_I32_A64_S */
11412 P2Align, offset64_op,
11413 /* ATOMIC_RMW16_U_SUB_I64_A32 */
11414 I64, P2Align, offset32_op, I32, I64,
11415 /* ATOMIC_RMW16_U_SUB_I64_A32_S */
11416 P2Align, offset32_op,
11417 /* ATOMIC_RMW16_U_SUB_I64_A64 */
11418 I64, P2Align, offset64_op, I64, I64,
11419 /* ATOMIC_RMW16_U_SUB_I64_A64_S */
11420 P2Align, offset64_op,
11421 /* ATOMIC_RMW16_U_XCHG_I32_A32 */
11422 I32, P2Align, offset32_op, I32, I32,
11423 /* ATOMIC_RMW16_U_XCHG_I32_A32_S */
11424 P2Align, offset32_op,
11425 /* ATOMIC_RMW16_U_XCHG_I32_A64 */
11426 I32, P2Align, offset64_op, I64, I32,
11427 /* ATOMIC_RMW16_U_XCHG_I32_A64_S */
11428 P2Align, offset64_op,
11429 /* ATOMIC_RMW16_U_XCHG_I64_A32 */
11430 I64, P2Align, offset32_op, I32, I64,
11431 /* ATOMIC_RMW16_U_XCHG_I64_A32_S */
11432 P2Align, offset32_op,
11433 /* ATOMIC_RMW16_U_XCHG_I64_A64 */
11434 I64, P2Align, offset64_op, I64, I64,
11435 /* ATOMIC_RMW16_U_XCHG_I64_A64_S */
11436 P2Align, offset64_op,
11437 /* ATOMIC_RMW16_U_XOR_I32_A32 */
11438 I32, P2Align, offset32_op, I32, I32,
11439 /* ATOMIC_RMW16_U_XOR_I32_A32_S */
11440 P2Align, offset32_op,
11441 /* ATOMIC_RMW16_U_XOR_I32_A64 */
11442 I32, P2Align, offset64_op, I64, I32,
11443 /* ATOMIC_RMW16_U_XOR_I32_A64_S */
11444 P2Align, offset64_op,
11445 /* ATOMIC_RMW16_U_XOR_I64_A32 */
11446 I64, P2Align, offset32_op, I32, I64,
11447 /* ATOMIC_RMW16_U_XOR_I64_A32_S */
11448 P2Align, offset32_op,
11449 /* ATOMIC_RMW16_U_XOR_I64_A64 */
11450 I64, P2Align, offset64_op, I64, I64,
11451 /* ATOMIC_RMW16_U_XOR_I64_A64_S */
11452 P2Align, offset64_op,
11453 /* ATOMIC_RMW32_U_ADD_I64_A32 */
11454 I64, P2Align, offset32_op, I32, I64,
11455 /* ATOMIC_RMW32_U_ADD_I64_A32_S */
11456 P2Align, offset32_op,
11457 /* ATOMIC_RMW32_U_ADD_I64_A64 */
11458 I64, P2Align, offset64_op, I64, I64,
11459 /* ATOMIC_RMW32_U_ADD_I64_A64_S */
11460 P2Align, offset64_op,
11461 /* ATOMIC_RMW32_U_AND_I64_A32 */
11462 I64, P2Align, offset32_op, I32, I64,
11463 /* ATOMIC_RMW32_U_AND_I64_A32_S */
11464 P2Align, offset32_op,
11465 /* ATOMIC_RMW32_U_AND_I64_A64 */
11466 I64, P2Align, offset64_op, I64, I64,
11467 /* ATOMIC_RMW32_U_AND_I64_A64_S */
11468 P2Align, offset64_op,
11469 /* ATOMIC_RMW32_U_CMPXCHG_I64_A32 */
11470 I64, P2Align, offset32_op, I32, I64, I64,
11471 /* ATOMIC_RMW32_U_CMPXCHG_I64_A32_S */
11472 P2Align, offset32_op,
11473 /* ATOMIC_RMW32_U_CMPXCHG_I64_A64 */
11474 I64, P2Align, offset64_op, I64, I64, I64,
11475 /* ATOMIC_RMW32_U_CMPXCHG_I64_A64_S */
11476 P2Align, offset64_op,
11477 /* ATOMIC_RMW32_U_OR_I64_A32 */
11478 I64, P2Align, offset32_op, I32, I64,
11479 /* ATOMIC_RMW32_U_OR_I64_A32_S */
11480 P2Align, offset32_op,
11481 /* ATOMIC_RMW32_U_OR_I64_A64 */
11482 I64, P2Align, offset64_op, I64, I64,
11483 /* ATOMIC_RMW32_U_OR_I64_A64_S */
11484 P2Align, offset64_op,
11485 /* ATOMIC_RMW32_U_SUB_I64_A32 */
11486 I64, P2Align, offset32_op, I32, I64,
11487 /* ATOMIC_RMW32_U_SUB_I64_A32_S */
11488 P2Align, offset32_op,
11489 /* ATOMIC_RMW32_U_SUB_I64_A64 */
11490 I64, P2Align, offset64_op, I64, I64,
11491 /* ATOMIC_RMW32_U_SUB_I64_A64_S */
11492 P2Align, offset64_op,
11493 /* ATOMIC_RMW32_U_XCHG_I64_A32 */
11494 I64, P2Align, offset32_op, I32, I64,
11495 /* ATOMIC_RMW32_U_XCHG_I64_A32_S */
11496 P2Align, offset32_op,
11497 /* ATOMIC_RMW32_U_XCHG_I64_A64 */
11498 I64, P2Align, offset64_op, I64, I64,
11499 /* ATOMIC_RMW32_U_XCHG_I64_A64_S */
11500 P2Align, offset64_op,
11501 /* ATOMIC_RMW32_U_XOR_I64_A32 */
11502 I64, P2Align, offset32_op, I32, I64,
11503 /* ATOMIC_RMW32_U_XOR_I64_A32_S */
11504 P2Align, offset32_op,
11505 /* ATOMIC_RMW32_U_XOR_I64_A64 */
11506 I64, P2Align, offset64_op, I64, I64,
11507 /* ATOMIC_RMW32_U_XOR_I64_A64_S */
11508 P2Align, offset64_op,
11509 /* ATOMIC_RMW8_U_ADD_I32_A32 */
11510 I32, P2Align, offset32_op, I32, I32,
11511 /* ATOMIC_RMW8_U_ADD_I32_A32_S */
11512 P2Align, offset32_op,
11513 /* ATOMIC_RMW8_U_ADD_I32_A64 */
11514 I32, P2Align, offset64_op, I64, I32,
11515 /* ATOMIC_RMW8_U_ADD_I32_A64_S */
11516 P2Align, offset64_op,
11517 /* ATOMIC_RMW8_U_ADD_I64_A32 */
11518 I64, P2Align, offset32_op, I32, I64,
11519 /* ATOMIC_RMW8_U_ADD_I64_A32_S */
11520 P2Align, offset32_op,
11521 /* ATOMIC_RMW8_U_ADD_I64_A64 */
11522 I64, P2Align, offset64_op, I64, I64,
11523 /* ATOMIC_RMW8_U_ADD_I64_A64_S */
11524 P2Align, offset64_op,
11525 /* ATOMIC_RMW8_U_AND_I32_A32 */
11526 I32, P2Align, offset32_op, I32, I32,
11527 /* ATOMIC_RMW8_U_AND_I32_A32_S */
11528 P2Align, offset32_op,
11529 /* ATOMIC_RMW8_U_AND_I32_A64 */
11530 I32, P2Align, offset64_op, I64, I32,
11531 /* ATOMIC_RMW8_U_AND_I32_A64_S */
11532 P2Align, offset64_op,
11533 /* ATOMIC_RMW8_U_AND_I64_A32 */
11534 I64, P2Align, offset32_op, I32, I64,
11535 /* ATOMIC_RMW8_U_AND_I64_A32_S */
11536 P2Align, offset32_op,
11537 /* ATOMIC_RMW8_U_AND_I64_A64 */
11538 I64, P2Align, offset64_op, I64, I64,
11539 /* ATOMIC_RMW8_U_AND_I64_A64_S */
11540 P2Align, offset64_op,
11541 /* ATOMIC_RMW8_U_CMPXCHG_I32_A32 */
11542 I32, P2Align, offset32_op, I32, I32, I32,
11543 /* ATOMIC_RMW8_U_CMPXCHG_I32_A32_S */
11544 P2Align, offset32_op,
11545 /* ATOMIC_RMW8_U_CMPXCHG_I32_A64 */
11546 I32, P2Align, offset64_op, I64, I32, I32,
11547 /* ATOMIC_RMW8_U_CMPXCHG_I32_A64_S */
11548 P2Align, offset64_op,
11549 /* ATOMIC_RMW8_U_CMPXCHG_I64_A32 */
11550 I64, P2Align, offset32_op, I32, I64, I64,
11551 /* ATOMIC_RMW8_U_CMPXCHG_I64_A32_S */
11552 P2Align, offset32_op,
11553 /* ATOMIC_RMW8_U_CMPXCHG_I64_A64 */
11554 I64, P2Align, offset64_op, I64, I64, I64,
11555 /* ATOMIC_RMW8_U_CMPXCHG_I64_A64_S */
11556 P2Align, offset64_op,
11557 /* ATOMIC_RMW8_U_OR_I32_A32 */
11558 I32, P2Align, offset32_op, I32, I32,
11559 /* ATOMIC_RMW8_U_OR_I32_A32_S */
11560 P2Align, offset32_op,
11561 /* ATOMIC_RMW8_U_OR_I32_A64 */
11562 I32, P2Align, offset64_op, I64, I32,
11563 /* ATOMIC_RMW8_U_OR_I32_A64_S */
11564 P2Align, offset64_op,
11565 /* ATOMIC_RMW8_U_OR_I64_A32 */
11566 I64, P2Align, offset32_op, I32, I64,
11567 /* ATOMIC_RMW8_U_OR_I64_A32_S */
11568 P2Align, offset32_op,
11569 /* ATOMIC_RMW8_U_OR_I64_A64 */
11570 I64, P2Align, offset64_op, I64, I64,
11571 /* ATOMIC_RMW8_U_OR_I64_A64_S */
11572 P2Align, offset64_op,
11573 /* ATOMIC_RMW8_U_SUB_I32_A32 */
11574 I32, P2Align, offset32_op, I32, I32,
11575 /* ATOMIC_RMW8_U_SUB_I32_A32_S */
11576 P2Align, offset32_op,
11577 /* ATOMIC_RMW8_U_SUB_I32_A64 */
11578 I32, P2Align, offset64_op, I64, I32,
11579 /* ATOMIC_RMW8_U_SUB_I32_A64_S */
11580 P2Align, offset64_op,
11581 /* ATOMIC_RMW8_U_SUB_I64_A32 */
11582 I64, P2Align, offset32_op, I32, I64,
11583 /* ATOMIC_RMW8_U_SUB_I64_A32_S */
11584 P2Align, offset32_op,
11585 /* ATOMIC_RMW8_U_SUB_I64_A64 */
11586 I64, P2Align, offset64_op, I64, I64,
11587 /* ATOMIC_RMW8_U_SUB_I64_A64_S */
11588 P2Align, offset64_op,
11589 /* ATOMIC_RMW8_U_XCHG_I32_A32 */
11590 I32, P2Align, offset32_op, I32, I32,
11591 /* ATOMIC_RMW8_U_XCHG_I32_A32_S */
11592 P2Align, offset32_op,
11593 /* ATOMIC_RMW8_U_XCHG_I32_A64 */
11594 I32, P2Align, offset64_op, I64, I32,
11595 /* ATOMIC_RMW8_U_XCHG_I32_A64_S */
11596 P2Align, offset64_op,
11597 /* ATOMIC_RMW8_U_XCHG_I64_A32 */
11598 I64, P2Align, offset32_op, I32, I64,
11599 /* ATOMIC_RMW8_U_XCHG_I64_A32_S */
11600 P2Align, offset32_op,
11601 /* ATOMIC_RMW8_U_XCHG_I64_A64 */
11602 I64, P2Align, offset64_op, I64, I64,
11603 /* ATOMIC_RMW8_U_XCHG_I64_A64_S */
11604 P2Align, offset64_op,
11605 /* ATOMIC_RMW8_U_XOR_I32_A32 */
11606 I32, P2Align, offset32_op, I32, I32,
11607 /* ATOMIC_RMW8_U_XOR_I32_A32_S */
11608 P2Align, offset32_op,
11609 /* ATOMIC_RMW8_U_XOR_I32_A64 */
11610 I32, P2Align, offset64_op, I64, I32,
11611 /* ATOMIC_RMW8_U_XOR_I32_A64_S */
11612 P2Align, offset64_op,
11613 /* ATOMIC_RMW8_U_XOR_I64_A32 */
11614 I64, P2Align, offset32_op, I32, I64,
11615 /* ATOMIC_RMW8_U_XOR_I64_A32_S */
11616 P2Align, offset32_op,
11617 /* ATOMIC_RMW8_U_XOR_I64_A64 */
11618 I64, P2Align, offset64_op, I64, I64,
11619 /* ATOMIC_RMW8_U_XOR_I64_A64_S */
11620 P2Align, offset64_op,
11621 /* ATOMIC_RMW_ADD_I32_A32 */
11622 I32, P2Align, offset32_op, I32, I32,
11623 /* ATOMIC_RMW_ADD_I32_A32_S */
11624 P2Align, offset32_op,
11625 /* ATOMIC_RMW_ADD_I32_A64 */
11626 I32, P2Align, offset64_op, I64, I32,
11627 /* ATOMIC_RMW_ADD_I32_A64_S */
11628 P2Align, offset64_op,
11629 /* ATOMIC_RMW_ADD_I64_A32 */
11630 I64, P2Align, offset32_op, I32, I64,
11631 /* ATOMIC_RMW_ADD_I64_A32_S */
11632 P2Align, offset32_op,
11633 /* ATOMIC_RMW_ADD_I64_A64 */
11634 I64, P2Align, offset64_op, I64, I64,
11635 /* ATOMIC_RMW_ADD_I64_A64_S */
11636 P2Align, offset64_op,
11637 /* ATOMIC_RMW_AND_I32_A32 */
11638 I32, P2Align, offset32_op, I32, I32,
11639 /* ATOMIC_RMW_AND_I32_A32_S */
11640 P2Align, offset32_op,
11641 /* ATOMIC_RMW_AND_I32_A64 */
11642 I32, P2Align, offset64_op, I64, I32,
11643 /* ATOMIC_RMW_AND_I32_A64_S */
11644 P2Align, offset64_op,
11645 /* ATOMIC_RMW_AND_I64_A32 */
11646 I64, P2Align, offset32_op, I32, I64,
11647 /* ATOMIC_RMW_AND_I64_A32_S */
11648 P2Align, offset32_op,
11649 /* ATOMIC_RMW_AND_I64_A64 */
11650 I64, P2Align, offset64_op, I64, I64,
11651 /* ATOMIC_RMW_AND_I64_A64_S */
11652 P2Align, offset64_op,
11653 /* ATOMIC_RMW_CMPXCHG_I32_A32 */
11654 I32, P2Align, offset32_op, I32, I32, I32,
11655 /* ATOMIC_RMW_CMPXCHG_I32_A32_S */
11656 P2Align, offset32_op,
11657 /* ATOMIC_RMW_CMPXCHG_I32_A64 */
11658 I32, P2Align, offset64_op, I64, I32, I32,
11659 /* ATOMIC_RMW_CMPXCHG_I32_A64_S */
11660 P2Align, offset64_op,
11661 /* ATOMIC_RMW_CMPXCHG_I64_A32 */
11662 I64, P2Align, offset32_op, I32, I64, I64,
11663 /* ATOMIC_RMW_CMPXCHG_I64_A32_S */
11664 P2Align, offset32_op,
11665 /* ATOMIC_RMW_CMPXCHG_I64_A64 */
11666 I64, P2Align, offset64_op, I64, I64, I64,
11667 /* ATOMIC_RMW_CMPXCHG_I64_A64_S */
11668 P2Align, offset64_op,
11669 /* ATOMIC_RMW_OR_I32_A32 */
11670 I32, P2Align, offset32_op, I32, I32,
11671 /* ATOMIC_RMW_OR_I32_A32_S */
11672 P2Align, offset32_op,
11673 /* ATOMIC_RMW_OR_I32_A64 */
11674 I32, P2Align, offset64_op, I64, I32,
11675 /* ATOMIC_RMW_OR_I32_A64_S */
11676 P2Align, offset64_op,
11677 /* ATOMIC_RMW_OR_I64_A32 */
11678 I64, P2Align, offset32_op, I32, I64,
11679 /* ATOMIC_RMW_OR_I64_A32_S */
11680 P2Align, offset32_op,
11681 /* ATOMIC_RMW_OR_I64_A64 */
11682 I64, P2Align, offset64_op, I64, I64,
11683 /* ATOMIC_RMW_OR_I64_A64_S */
11684 P2Align, offset64_op,
11685 /* ATOMIC_RMW_SUB_I32_A32 */
11686 I32, P2Align, offset32_op, I32, I32,
11687 /* ATOMIC_RMW_SUB_I32_A32_S */
11688 P2Align, offset32_op,
11689 /* ATOMIC_RMW_SUB_I32_A64 */
11690 I32, P2Align, offset64_op, I64, I32,
11691 /* ATOMIC_RMW_SUB_I32_A64_S */
11692 P2Align, offset64_op,
11693 /* ATOMIC_RMW_SUB_I64_A32 */
11694 I64, P2Align, offset32_op, I32, I64,
11695 /* ATOMIC_RMW_SUB_I64_A32_S */
11696 P2Align, offset32_op,
11697 /* ATOMIC_RMW_SUB_I64_A64 */
11698 I64, P2Align, offset64_op, I64, I64,
11699 /* ATOMIC_RMW_SUB_I64_A64_S */
11700 P2Align, offset64_op,
11701 /* ATOMIC_RMW_XCHG_I32_A32 */
11702 I32, P2Align, offset32_op, I32, I32,
11703 /* ATOMIC_RMW_XCHG_I32_A32_S */
11704 P2Align, offset32_op,
11705 /* ATOMIC_RMW_XCHG_I32_A64 */
11706 I32, P2Align, offset64_op, I64, I32,
11707 /* ATOMIC_RMW_XCHG_I32_A64_S */
11708 P2Align, offset64_op,
11709 /* ATOMIC_RMW_XCHG_I64_A32 */
11710 I64, P2Align, offset32_op, I32, I64,
11711 /* ATOMIC_RMW_XCHG_I64_A32_S */
11712 P2Align, offset32_op,
11713 /* ATOMIC_RMW_XCHG_I64_A64 */
11714 I64, P2Align, offset64_op, I64, I64,
11715 /* ATOMIC_RMW_XCHG_I64_A64_S */
11716 P2Align, offset64_op,
11717 /* ATOMIC_RMW_XOR_I32_A32 */
11718 I32, P2Align, offset32_op, I32, I32,
11719 /* ATOMIC_RMW_XOR_I32_A32_S */
11720 P2Align, offset32_op,
11721 /* ATOMIC_RMW_XOR_I32_A64 */
11722 I32, P2Align, offset64_op, I64, I32,
11723 /* ATOMIC_RMW_XOR_I32_A64_S */
11724 P2Align, offset64_op,
11725 /* ATOMIC_RMW_XOR_I64_A32 */
11726 I64, P2Align, offset32_op, I32, I64,
11727 /* ATOMIC_RMW_XOR_I64_A32_S */
11728 P2Align, offset32_op,
11729 /* ATOMIC_RMW_XOR_I64_A64 */
11730 I64, P2Align, offset64_op, I64, I64,
11731 /* ATOMIC_RMW_XOR_I64_A64_S */
11732 P2Align, offset64_op,
11733 /* ATOMIC_STORE16_I32_A32 */
11734 P2Align, offset32_op, I32, I32,
11735 /* ATOMIC_STORE16_I32_A32_S */
11736 P2Align, offset32_op,
11737 /* ATOMIC_STORE16_I32_A64 */
11738 P2Align, offset64_op, I64, I32,
11739 /* ATOMIC_STORE16_I32_A64_S */
11740 P2Align, offset64_op,
11741 /* ATOMIC_STORE16_I64_A32 */
11742 P2Align, offset32_op, I32, I64,
11743 /* ATOMIC_STORE16_I64_A32_S */
11744 P2Align, offset32_op,
11745 /* ATOMIC_STORE16_I64_A64 */
11746 P2Align, offset64_op, I64, I64,
11747 /* ATOMIC_STORE16_I64_A64_S */
11748 P2Align, offset64_op,
11749 /* ATOMIC_STORE32_I64_A32 */
11750 P2Align, offset32_op, I32, I64,
11751 /* ATOMIC_STORE32_I64_A32_S */
11752 P2Align, offset32_op,
11753 /* ATOMIC_STORE32_I64_A64 */
11754 P2Align, offset64_op, I64, I64,
11755 /* ATOMIC_STORE32_I64_A64_S */
11756 P2Align, offset64_op,
11757 /* ATOMIC_STORE8_I32_A32 */
11758 P2Align, offset32_op, I32, I32,
11759 /* ATOMIC_STORE8_I32_A32_S */
11760 P2Align, offset32_op,
11761 /* ATOMIC_STORE8_I32_A64 */
11762 P2Align, offset64_op, I64, I32,
11763 /* ATOMIC_STORE8_I32_A64_S */
11764 P2Align, offset64_op,
11765 /* ATOMIC_STORE8_I64_A32 */
11766 P2Align, offset32_op, I32, I64,
11767 /* ATOMIC_STORE8_I64_A32_S */
11768 P2Align, offset32_op,
11769 /* ATOMIC_STORE8_I64_A64 */
11770 P2Align, offset64_op, I64, I64,
11771 /* ATOMIC_STORE8_I64_A64_S */
11772 P2Align, offset64_op,
11773 /* ATOMIC_STORE_I32_A32 */
11774 P2Align, offset32_op, I32, I32,
11775 /* ATOMIC_STORE_I32_A32_S */
11776 P2Align, offset32_op,
11777 /* ATOMIC_STORE_I32_A64 */
11778 P2Align, offset64_op, I64, I32,
11779 /* ATOMIC_STORE_I32_A64_S */
11780 P2Align, offset64_op,
11781 /* ATOMIC_STORE_I64_A32 */
11782 P2Align, offset32_op, I32, I64,
11783 /* ATOMIC_STORE_I64_A32_S */
11784 P2Align, offset32_op,
11785 /* ATOMIC_STORE_I64_A64 */
11786 P2Align, offset64_op, I64, I64,
11787 /* ATOMIC_STORE_I64_A64_S */
11788 P2Align, offset64_op,
11789 /* AVGR_U_I16x8 */
11790 V128, V128, V128,
11791 /* AVGR_U_I16x8_S */
11792 /* AVGR_U_I8x16 */
11793 V128, V128, V128,
11794 /* AVGR_U_I8x16_S */
11795 /* BITMASK_I16x8 */
11796 I32, V128,
11797 /* BITMASK_I16x8_S */
11798 /* BITMASK_I32x4 */
11799 I32, V128,
11800 /* BITMASK_I32x4_S */
11801 /* BITMASK_I64x2 */
11802 I32, V128,
11803 /* BITMASK_I64x2_S */
11804 /* BITMASK_I8x16 */
11805 I32, V128,
11806 /* BITMASK_I8x16_S */
11807 /* BITSELECT */
11808 V128, V128, V128, V128,
11809 /* BITSELECT_S */
11810 /* BLOCK */
11811 Signature,
11812 /* BLOCK_S */
11813 Signature,
11814 /* BR */
11815 bb_op,
11816 /* BR_IF */
11817 bb_op, I32,
11818 /* BR_IF_S */
11819 bb_op,
11820 /* BR_S */
11821 bb_op,
11822 /* BR_TABLE_I32 */
11823 I32,
11824 /* BR_TABLE_I32_S */
11825 brlist,
11826 /* BR_TABLE_I64 */
11827 I64,
11828 /* BR_TABLE_I64_S */
11829 brlist,
11830 /* BR_UNLESS */
11831 bb_op, I32,
11832 /* BR_UNLESS_S */
11833 bb_op,
11834 /* CALL */
11835 function32_op,
11836 /* CALL_INDIRECT */
11837 TypeIndex, table32_op,
11838 /* CALL_INDIRECT_S */
11839 TypeIndex, table32_op,
11840 /* CALL_S */
11841 function32_op,
11842 /* CATCH */
11843 tag_op,
11844 /* CATCH_ALL */
11845 /* CATCH_ALL_S */
11846 /* CATCH_S */
11847 tag_op,
11848 /* CEIL_F16x8 */
11849 V128, V128,
11850 /* CEIL_F16x8_S */
11851 /* CEIL_F32 */
11852 F32, F32,
11853 /* CEIL_F32_S */
11854 /* CEIL_F32x4 */
11855 V128, V128,
11856 /* CEIL_F32x4_S */
11857 /* CEIL_F64 */
11858 F64, F64,
11859 /* CEIL_F64_S */
11860 /* CEIL_F64x2 */
11861 V128, V128,
11862 /* CEIL_F64x2_S */
11863 /* CLZ_I32 */
11864 I32, I32,
11865 /* CLZ_I32_S */
11866 /* CLZ_I64 */
11867 I64, I64,
11868 /* CLZ_I64_S */
11869 /* CONST_F32 */
11870 F32, f32imm_op,
11871 /* CONST_F32_S */
11872 f32imm_op,
11873 /* CONST_F64 */
11874 F64, f64imm_op,
11875 /* CONST_F64_S */
11876 f64imm_op,
11877 /* CONST_I32 */
11878 I32, i32imm_op,
11879 /* CONST_I32_S */
11880 i32imm_op,
11881 /* CONST_I64 */
11882 I64, i64imm_op,
11883 /* CONST_I64_S */
11884 i64imm_op,
11885 /* CONST_V128_F32x4 */
11886 V128, f32imm_op, f32imm_op, f32imm_op, f32imm_op,
11887 /* CONST_V128_F32x4_S */
11888 f32imm_op, f32imm_op, f32imm_op, f32imm_op,
11889 /* CONST_V128_F64x2 */
11890 V128, f64imm_op, f64imm_op,
11891 /* CONST_V128_F64x2_S */
11892 f64imm_op, f64imm_op,
11893 /* CONST_V128_I16x8 */
11894 V128, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op,
11895 /* CONST_V128_I16x8_S */
11896 vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op, vec_i16imm_op,
11897 /* CONST_V128_I32x4 */
11898 V128, vec_i32imm_op, vec_i32imm_op, vec_i32imm_op, vec_i32imm_op,
11899 /* CONST_V128_I32x4_S */
11900 vec_i32imm_op, vec_i32imm_op, vec_i32imm_op, vec_i32imm_op,
11901 /* CONST_V128_I64x2 */
11902 V128, vec_i64imm_op, vec_i64imm_op,
11903 /* CONST_V128_I64x2_S */
11904 vec_i64imm_op, vec_i64imm_op,
11905 /* CONST_V128_I8x16 */
11906 V128, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op,
11907 /* CONST_V128_I8x16_S */
11908 vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op,
11909 /* COPYSIGN_F32 */
11910 F32, F32, F32,
11911 /* COPYSIGN_F32_S */
11912 /* COPYSIGN_F64 */
11913 F64, F64, F64,
11914 /* COPYSIGN_F64_S */
11915 /* COPY_EXNREF */
11916 EXNREF, EXNREF,
11917 /* COPY_EXNREF_S */
11918 /* COPY_EXTERNREF */
11919 EXTERNREF, EXTERNREF,
11920 /* COPY_EXTERNREF_S */
11921 /* COPY_F32 */
11922 F32, F32,
11923 /* COPY_F32_S */
11924 /* COPY_F64 */
11925 F64, F64,
11926 /* COPY_F64_S */
11927 /* COPY_FUNCREF */
11928 FUNCREF, FUNCREF,
11929 /* COPY_FUNCREF_S */
11930 /* COPY_I32 */
11931 I32, I32,
11932 /* COPY_I32_S */
11933 /* COPY_I64 */
11934 I64, I64,
11935 /* COPY_I64_S */
11936 /* COPY_V128 */
11937 V128, V128,
11938 /* COPY_V128_S */
11939 /* CTZ_I32 */
11940 I32, I32,
11941 /* CTZ_I32_S */
11942 /* CTZ_I64 */
11943 I64, I64,
11944 /* CTZ_I64_S */
11945 /* DEBUG_UNREACHABLE */
11946 /* DEBUG_UNREACHABLE_S */
11947 /* DELEGATE */
11948 bb_op,
11949 /* DELEGATE_S */
11950 bb_op,
11951 /* DIV_F16x8 */
11952 V128, V128, V128,
11953 /* DIV_F16x8_S */
11954 /* DIV_F32 */
11955 F32, F32, F32,
11956 /* DIV_F32_S */
11957 /* DIV_F32x4 */
11958 V128, V128, V128,
11959 /* DIV_F32x4_S */
11960 /* DIV_F64 */
11961 F64, F64, F64,
11962 /* DIV_F64_S */
11963 /* DIV_F64x2 */
11964 V128, V128, V128,
11965 /* DIV_F64x2_S */
11966 /* DIV_S_I32 */
11967 I32, I32, I32,
11968 /* DIV_S_I32_S */
11969 /* DIV_S_I64 */
11970 I64, I64, I64,
11971 /* DIV_S_I64_S */
11972 /* DIV_U_I32 */
11973 I32, I32, I32,
11974 /* DIV_U_I32_S */
11975 /* DIV_U_I64 */
11976 I64, I64, I64,
11977 /* DIV_U_I64_S */
11978 /* DOT */
11979 V128, V128, V128,
11980 /* DOT_S */
11981 /* DROP_EXNREF */
11982 EXNREF,
11983 /* DROP_EXNREF_S */
11984 /* DROP_EXTERNREF */
11985 EXTERNREF,
11986 /* DROP_EXTERNREF_S */
11987 /* DROP_F32 */
11988 F32,
11989 /* DROP_F32_S */
11990 /* DROP_F64 */
11991 F64,
11992 /* DROP_F64_S */
11993 /* DROP_FUNCREF */
11994 FUNCREF,
11995 /* DROP_FUNCREF_S */
11996 /* DROP_I32 */
11997 I32,
11998 /* DROP_I32_S */
11999 /* DROP_I64 */
12000 I64,
12001 /* DROP_I64_S */
12002 /* DROP_V128 */
12003 V128,
12004 /* DROP_V128_S */
12005 /* ELSE */
12006 /* ELSE_S */
12007 /* END */
12008 /* END_BLOCK */
12009 /* END_BLOCK_S */
12010 /* END_FUNCTION */
12011 /* END_FUNCTION_S */
12012 /* END_IF */
12013 /* END_IF_S */
12014 /* END_LOOP */
12015 /* END_LOOP_S */
12016 /* END_S */
12017 /* END_TRY */
12018 /* END_TRY_S */
12019 /* EQZ_I32 */
12020 I32, I32,
12021 /* EQZ_I32_S */
12022 /* EQZ_I64 */
12023 I32, I64,
12024 /* EQZ_I64_S */
12025 /* EQ_F16x8 */
12026 V128, V128, V128,
12027 /* EQ_F16x8_S */
12028 /* EQ_F32 */
12029 I32, F32, F32,
12030 /* EQ_F32_S */
12031 /* EQ_F32x4 */
12032 V128, V128, V128,
12033 /* EQ_F32x4_S */
12034 /* EQ_F64 */
12035 I32, F64, F64,
12036 /* EQ_F64_S */
12037 /* EQ_F64x2 */
12038 V128, V128, V128,
12039 /* EQ_F64x2_S */
12040 /* EQ_I16x8 */
12041 V128, V128, V128,
12042 /* EQ_I16x8_S */
12043 /* EQ_I32 */
12044 I32, I32, I32,
12045 /* EQ_I32_S */
12046 /* EQ_I32x4 */
12047 V128, V128, V128,
12048 /* EQ_I32x4_S */
12049 /* EQ_I64 */
12050 I32, I64, I64,
12051 /* EQ_I64_S */
12052 /* EQ_I64x2 */
12053 V128, V128, V128,
12054 /* EQ_I64x2_S */
12055 /* EQ_I8x16 */
12056 V128, V128, V128,
12057 /* EQ_I8x16_S */
12058 /* EXTMUL_HIGH_S_I16x8 */
12059 V128, V128, V128,
12060 /* EXTMUL_HIGH_S_I16x8_S */
12061 /* EXTMUL_HIGH_S_I32x4 */
12062 V128, V128, V128,
12063 /* EXTMUL_HIGH_S_I32x4_S */
12064 /* EXTMUL_HIGH_S_I64x2 */
12065 V128, V128, V128,
12066 /* EXTMUL_HIGH_S_I64x2_S */
12067 /* EXTMUL_HIGH_U_I16x8 */
12068 V128, V128, V128,
12069 /* EXTMUL_HIGH_U_I16x8_S */
12070 /* EXTMUL_HIGH_U_I32x4 */
12071 V128, V128, V128,
12072 /* EXTMUL_HIGH_U_I32x4_S */
12073 /* EXTMUL_HIGH_U_I64x2 */
12074 V128, V128, V128,
12075 /* EXTMUL_HIGH_U_I64x2_S */
12076 /* EXTMUL_LOW_S_I16x8 */
12077 V128, V128, V128,
12078 /* EXTMUL_LOW_S_I16x8_S */
12079 /* EXTMUL_LOW_S_I32x4 */
12080 V128, V128, V128,
12081 /* EXTMUL_LOW_S_I32x4_S */
12082 /* EXTMUL_LOW_S_I64x2 */
12083 V128, V128, V128,
12084 /* EXTMUL_LOW_S_I64x2_S */
12085 /* EXTMUL_LOW_U_I16x8 */
12086 V128, V128, V128,
12087 /* EXTMUL_LOW_U_I16x8_S */
12088 /* EXTMUL_LOW_U_I32x4 */
12089 V128, V128, V128,
12090 /* EXTMUL_LOW_U_I32x4_S */
12091 /* EXTMUL_LOW_U_I64x2 */
12092 V128, V128, V128,
12093 /* EXTMUL_LOW_U_I64x2_S */
12094 /* EXTRACT_LANE_F16x8 */
12095 F32, V128, vec_i8imm_op,
12096 /* EXTRACT_LANE_F16x8_S */
12097 vec_i8imm_op,
12098 /* EXTRACT_LANE_F32x4 */
12099 F32, V128, vec_i8imm_op,
12100 /* EXTRACT_LANE_F32x4_S */
12101 vec_i8imm_op,
12102 /* EXTRACT_LANE_F64x2 */
12103 F64, V128, vec_i8imm_op,
12104 /* EXTRACT_LANE_F64x2_S */
12105 vec_i8imm_op,
12106 /* EXTRACT_LANE_I16x8_s */
12107 I32, V128, vec_i8imm_op,
12108 /* EXTRACT_LANE_I16x8_s_S */
12109 vec_i8imm_op,
12110 /* EXTRACT_LANE_I16x8_u */
12111 I32, V128, vec_i8imm_op,
12112 /* EXTRACT_LANE_I16x8_u_S */
12113 vec_i8imm_op,
12114 /* EXTRACT_LANE_I32x4 */
12115 I32, V128, vec_i8imm_op,
12116 /* EXTRACT_LANE_I32x4_S */
12117 vec_i8imm_op,
12118 /* EXTRACT_LANE_I64x2 */
12119 I64, V128, vec_i8imm_op,
12120 /* EXTRACT_LANE_I64x2_S */
12121 vec_i8imm_op,
12122 /* EXTRACT_LANE_I8x16_s */
12123 I32, V128, vec_i8imm_op,
12124 /* EXTRACT_LANE_I8x16_s_S */
12125 vec_i8imm_op,
12126 /* EXTRACT_LANE_I8x16_u */
12127 I32, V128, vec_i8imm_op,
12128 /* EXTRACT_LANE_I8x16_u_S */
12129 vec_i8imm_op,
12130 /* F32_CONVERT_S_I32 */
12131 F32, I32,
12132 /* F32_CONVERT_S_I32_S */
12133 /* F32_CONVERT_S_I64 */
12134 F32, I64,
12135 /* F32_CONVERT_S_I64_S */
12136 /* F32_CONVERT_U_I32 */
12137 F32, I32,
12138 /* F32_CONVERT_U_I32_S */
12139 /* F32_CONVERT_U_I64 */
12140 F32, I64,
12141 /* F32_CONVERT_U_I64_S */
12142 /* F32_DEMOTE_F64 */
12143 F32, F64,
12144 /* F32_DEMOTE_F64_S */
12145 /* F32_REINTERPRET_I32 */
12146 F32, I32,
12147 /* F32_REINTERPRET_I32_S */
12148 /* F64_CONVERT_S_I32 */
12149 F64, I32,
12150 /* F64_CONVERT_S_I32_S */
12151 /* F64_CONVERT_S_I64 */
12152 F64, I64,
12153 /* F64_CONVERT_S_I64_S */
12154 /* F64_CONVERT_U_I32 */
12155 F64, I32,
12156 /* F64_CONVERT_U_I32_S */
12157 /* F64_CONVERT_U_I64 */
12158 F64, I64,
12159 /* F64_CONVERT_U_I64_S */
12160 /* F64_PROMOTE_F32 */
12161 F64, F32,
12162 /* F64_PROMOTE_F32_S */
12163 /* F64_REINTERPRET_I64 */
12164 F64, I64,
12165 /* F64_REINTERPRET_I64_S */
12166 /* FALLTHROUGH_RETURN */
12167 /* FALLTHROUGH_RETURN_S */
12168 /* FLOOR_F16x8 */
12169 V128, V128,
12170 /* FLOOR_F16x8_S */
12171 /* FLOOR_F32 */
12172 F32, F32,
12173 /* FLOOR_F32_S */
12174 /* FLOOR_F32x4 */
12175 V128, V128,
12176 /* FLOOR_F32x4_S */
12177 /* FLOOR_F64 */
12178 F64, F64,
12179 /* FLOOR_F64_S */
12180 /* FLOOR_F64x2 */
12181 V128, V128,
12182 /* FLOOR_F64x2_S */
12183 /* FP_TO_SINT_I32_F32 */
12184 I32, F32,
12185 /* FP_TO_SINT_I32_F32_S */
12186 /* FP_TO_SINT_I32_F64 */
12187 I32, F64,
12188 /* FP_TO_SINT_I32_F64_S */
12189 /* FP_TO_SINT_I64_F32 */
12190 I64, F32,
12191 /* FP_TO_SINT_I64_F32_S */
12192 /* FP_TO_SINT_I64_F64 */
12193 I64, F64,
12194 /* FP_TO_SINT_I64_F64_S */
12195 /* FP_TO_UINT_I32_F32 */
12196 I32, F32,
12197 /* FP_TO_UINT_I32_F32_S */
12198 /* FP_TO_UINT_I32_F64 */
12199 I32, F64,
12200 /* FP_TO_UINT_I32_F64_S */
12201 /* FP_TO_UINT_I64_F32 */
12202 I64, F32,
12203 /* FP_TO_UINT_I64_F32_S */
12204 /* FP_TO_UINT_I64_F64 */
12205 I64, F64,
12206 /* FP_TO_UINT_I64_F64_S */
12207 /* GE_F16x8 */
12208 V128, V128, V128,
12209 /* GE_F16x8_S */
12210 /* GE_F32 */
12211 I32, F32, F32,
12212 /* GE_F32_S */
12213 /* GE_F32x4 */
12214 V128, V128, V128,
12215 /* GE_F32x4_S */
12216 /* GE_F64 */
12217 I32, F64, F64,
12218 /* GE_F64_S */
12219 /* GE_F64x2 */
12220 V128, V128, V128,
12221 /* GE_F64x2_S */
12222 /* GE_S_I16x8 */
12223 V128, V128, V128,
12224 /* GE_S_I16x8_S */
12225 /* GE_S_I32 */
12226 I32, I32, I32,
12227 /* GE_S_I32_S */
12228 /* GE_S_I32x4 */
12229 V128, V128, V128,
12230 /* GE_S_I32x4_S */
12231 /* GE_S_I64 */
12232 I32, I64, I64,
12233 /* GE_S_I64_S */
12234 /* GE_S_I64x2 */
12235 V128, V128, V128,
12236 /* GE_S_I64x2_S */
12237 /* GE_S_I8x16 */
12238 V128, V128, V128,
12239 /* GE_S_I8x16_S */
12240 /* GE_U_I16x8 */
12241 V128, V128, V128,
12242 /* GE_U_I16x8_S */
12243 /* GE_U_I32 */
12244 I32, I32, I32,
12245 /* GE_U_I32_S */
12246 /* GE_U_I32x4 */
12247 V128, V128, V128,
12248 /* GE_U_I32x4_S */
12249 /* GE_U_I64 */
12250 I32, I64, I64,
12251 /* GE_U_I64_S */
12252 /* GE_U_I8x16 */
12253 V128, V128, V128,
12254 /* GE_U_I8x16_S */
12255 /* GLOBAL_GET_EXNREF */
12256 EXNREF, global_op32,
12257 /* GLOBAL_GET_EXNREF_S */
12258 global_op32,
12259 /* GLOBAL_GET_EXTERNREF */
12260 EXTERNREF, global_op32,
12261 /* GLOBAL_GET_EXTERNREF_S */
12262 global_op32,
12263 /* GLOBAL_GET_F32 */
12264 F32, global_op32,
12265 /* GLOBAL_GET_F32_S */
12266 global_op32,
12267 /* GLOBAL_GET_F64 */
12268 F64, global_op32,
12269 /* GLOBAL_GET_F64_S */
12270 global_op32,
12271 /* GLOBAL_GET_FUNCREF */
12272 FUNCREF, global_op32,
12273 /* GLOBAL_GET_FUNCREF_S */
12274 global_op32,
12275 /* GLOBAL_GET_I32 */
12276 I32, global_op32,
12277 /* GLOBAL_GET_I32_S */
12278 global_op32,
12279 /* GLOBAL_GET_I64 */
12280 I64, global_op64,
12281 /* GLOBAL_GET_I64_S */
12282 global_op64,
12283 /* GLOBAL_GET_V128 */
12284 V128, global_op32,
12285 /* GLOBAL_GET_V128_S */
12286 global_op32,
12287 /* GLOBAL_SET_EXNREF */
12288 global_op32, EXNREF,
12289 /* GLOBAL_SET_EXNREF_S */
12290 global_op32,
12291 /* GLOBAL_SET_EXTERNREF */
12292 global_op32, EXTERNREF,
12293 /* GLOBAL_SET_EXTERNREF_S */
12294 global_op32,
12295 /* GLOBAL_SET_F32 */
12296 global_op32, F32,
12297 /* GLOBAL_SET_F32_S */
12298 global_op32,
12299 /* GLOBAL_SET_F64 */
12300 global_op32, F64,
12301 /* GLOBAL_SET_F64_S */
12302 global_op32,
12303 /* GLOBAL_SET_FUNCREF */
12304 global_op32, FUNCREF,
12305 /* GLOBAL_SET_FUNCREF_S */
12306 global_op32,
12307 /* GLOBAL_SET_I32 */
12308 global_op32, I32,
12309 /* GLOBAL_SET_I32_S */
12310 global_op32,
12311 /* GLOBAL_SET_I64 */
12312 global_op64, I64,
12313 /* GLOBAL_SET_I64_S */
12314 global_op64,
12315 /* GLOBAL_SET_V128 */
12316 global_op32, V128,
12317 /* GLOBAL_SET_V128_S */
12318 global_op32,
12319 /* GT_F16x8 */
12320 V128, V128, V128,
12321 /* GT_F16x8_S */
12322 /* GT_F32 */
12323 I32, F32, F32,
12324 /* GT_F32_S */
12325 /* GT_F32x4 */
12326 V128, V128, V128,
12327 /* GT_F32x4_S */
12328 /* GT_F64 */
12329 I32, F64, F64,
12330 /* GT_F64_S */
12331 /* GT_F64x2 */
12332 V128, V128, V128,
12333 /* GT_F64x2_S */
12334 /* GT_S_I16x8 */
12335 V128, V128, V128,
12336 /* GT_S_I16x8_S */
12337 /* GT_S_I32 */
12338 I32, I32, I32,
12339 /* GT_S_I32_S */
12340 /* GT_S_I32x4 */
12341 V128, V128, V128,
12342 /* GT_S_I32x4_S */
12343 /* GT_S_I64 */
12344 I32, I64, I64,
12345 /* GT_S_I64_S */
12346 /* GT_S_I64x2 */
12347 V128, V128, V128,
12348 /* GT_S_I64x2_S */
12349 /* GT_S_I8x16 */
12350 V128, V128, V128,
12351 /* GT_S_I8x16_S */
12352 /* GT_U_I16x8 */
12353 V128, V128, V128,
12354 /* GT_U_I16x8_S */
12355 /* GT_U_I32 */
12356 I32, I32, I32,
12357 /* GT_U_I32_S */
12358 /* GT_U_I32x4 */
12359 V128, V128, V128,
12360 /* GT_U_I32x4_S */
12361 /* GT_U_I64 */
12362 I32, I64, I64,
12363 /* GT_U_I64_S */
12364 /* GT_U_I8x16 */
12365 V128, V128, V128,
12366 /* GT_U_I8x16_S */
12367 /* I32_EXTEND16_S_I32 */
12368 I32, I32,
12369 /* I32_EXTEND16_S_I32_S */
12370 /* I32_EXTEND8_S_I32 */
12371 I32, I32,
12372 /* I32_EXTEND8_S_I32_S */
12373 /* I32_REINTERPRET_F32 */
12374 I32, F32,
12375 /* I32_REINTERPRET_F32_S */
12376 /* I32_TRUNC_S_F32 */
12377 I32, F32,
12378 /* I32_TRUNC_S_F32_S */
12379 /* I32_TRUNC_S_F64 */
12380 I32, F64,
12381 /* I32_TRUNC_S_F64_S */
12382 /* I32_TRUNC_S_SAT_F32 */
12383 I32, F32,
12384 /* I32_TRUNC_S_SAT_F32_S */
12385 /* I32_TRUNC_S_SAT_F64 */
12386 I32, F64,
12387 /* I32_TRUNC_S_SAT_F64_S */
12388 /* I32_TRUNC_U_F32 */
12389 I32, F32,
12390 /* I32_TRUNC_U_F32_S */
12391 /* I32_TRUNC_U_F64 */
12392 I32, F64,
12393 /* I32_TRUNC_U_F64_S */
12394 /* I32_TRUNC_U_SAT_F32 */
12395 I32, F32,
12396 /* I32_TRUNC_U_SAT_F32_S */
12397 /* I32_TRUNC_U_SAT_F64 */
12398 I32, F64,
12399 /* I32_TRUNC_U_SAT_F64_S */
12400 /* I32_WRAP_I64 */
12401 I32, I64,
12402 /* I32_WRAP_I64_S */
12403 /* I64_EXTEND16_S_I64 */
12404 I64, I64,
12405 /* I64_EXTEND16_S_I64_S */
12406 /* I64_EXTEND32_S_I64 */
12407 I64, I64,
12408 /* I64_EXTEND32_S_I64_S */
12409 /* I64_EXTEND8_S_I64 */
12410 I64, I64,
12411 /* I64_EXTEND8_S_I64_S */
12412 /* I64_EXTEND_S_I32 */
12413 I64, I32,
12414 /* I64_EXTEND_S_I32_S */
12415 /* I64_EXTEND_U_I32 */
12416 I64, I32,
12417 /* I64_EXTEND_U_I32_S */
12418 /* I64_REINTERPRET_F64 */
12419 I64, F64,
12420 /* I64_REINTERPRET_F64_S */
12421 /* I64_TRUNC_S_F32 */
12422 I64, F32,
12423 /* I64_TRUNC_S_F32_S */
12424 /* I64_TRUNC_S_F64 */
12425 I64, F64,
12426 /* I64_TRUNC_S_F64_S */
12427 /* I64_TRUNC_S_SAT_F32 */
12428 I64, F32,
12429 /* I64_TRUNC_S_SAT_F32_S */
12430 /* I64_TRUNC_S_SAT_F64 */
12431 I64, F64,
12432 /* I64_TRUNC_S_SAT_F64_S */
12433 /* I64_TRUNC_U_F32 */
12434 I64, F32,
12435 /* I64_TRUNC_U_F32_S */
12436 /* I64_TRUNC_U_F64 */
12437 I64, F64,
12438 /* I64_TRUNC_U_F64_S */
12439 /* I64_TRUNC_U_SAT_F32 */
12440 I64, F32,
12441 /* I64_TRUNC_U_SAT_F32_S */
12442 /* I64_TRUNC_U_SAT_F64 */
12443 I64, F64,
12444 /* I64_TRUNC_U_SAT_F64_S */
12445 /* IF */
12446 Signature, I32,
12447 /* IF_S */
12448 Signature,
12449 /* LANESELECT_I16x8 */
12450 V128, V128, V128, V128,
12451 /* LANESELECT_I16x8_S */
12452 /* LANESELECT_I32x4 */
12453 V128, V128, V128, V128,
12454 /* LANESELECT_I32x4_S */
12455 /* LANESELECT_I64x2 */
12456 V128, V128, V128, V128,
12457 /* LANESELECT_I64x2_S */
12458 /* LANESELECT_I8x16 */
12459 V128, V128, V128, V128,
12460 /* LANESELECT_I8x16_S */
12461 /* LE_F16x8 */
12462 V128, V128, V128,
12463 /* LE_F16x8_S */
12464 /* LE_F32 */
12465 I32, F32, F32,
12466 /* LE_F32_S */
12467 /* LE_F32x4 */
12468 V128, V128, V128,
12469 /* LE_F32x4_S */
12470 /* LE_F64 */
12471 I32, F64, F64,
12472 /* LE_F64_S */
12473 /* LE_F64x2 */
12474 V128, V128, V128,
12475 /* LE_F64x2_S */
12476 /* LE_S_I16x8 */
12477 V128, V128, V128,
12478 /* LE_S_I16x8_S */
12479 /* LE_S_I32 */
12480 I32, I32, I32,
12481 /* LE_S_I32_S */
12482 /* LE_S_I32x4 */
12483 V128, V128, V128,
12484 /* LE_S_I32x4_S */
12485 /* LE_S_I64 */
12486 I32, I64, I64,
12487 /* LE_S_I64_S */
12488 /* LE_S_I64x2 */
12489 V128, V128, V128,
12490 /* LE_S_I64x2_S */
12491 /* LE_S_I8x16 */
12492 V128, V128, V128,
12493 /* LE_S_I8x16_S */
12494 /* LE_U_I16x8 */
12495 V128, V128, V128,
12496 /* LE_U_I16x8_S */
12497 /* LE_U_I32 */
12498 I32, I32, I32,
12499 /* LE_U_I32_S */
12500 /* LE_U_I32x4 */
12501 V128, V128, V128,
12502 /* LE_U_I32x4_S */
12503 /* LE_U_I64 */
12504 I32, I64, I64,
12505 /* LE_U_I64_S */
12506 /* LE_U_I8x16 */
12507 V128, V128, V128,
12508 /* LE_U_I8x16_S */
12509 /* LOAD16_SPLAT_A32 */
12510 V128, P2Align, offset32_op, I32,
12511 /* LOAD16_SPLAT_A32_S */
12512 P2Align, offset32_op,
12513 /* LOAD16_SPLAT_A64 */
12514 V128, P2Align, offset64_op, I64,
12515 /* LOAD16_SPLAT_A64_S */
12516 P2Align, offset64_op,
12517 /* LOAD16_S_I32_A32 */
12518 I32, P2Align, offset32_op, I32,
12519 /* LOAD16_S_I32_A32_S */
12520 P2Align, offset32_op,
12521 /* LOAD16_S_I32_A64 */
12522 I32, P2Align, offset64_op, I64,
12523 /* LOAD16_S_I32_A64_S */
12524 P2Align, offset64_op,
12525 /* LOAD16_S_I64_A32 */
12526 I64, P2Align, offset32_op, I32,
12527 /* LOAD16_S_I64_A32_S */
12528 P2Align, offset32_op,
12529 /* LOAD16_S_I64_A64 */
12530 I64, P2Align, offset64_op, I64,
12531 /* LOAD16_S_I64_A64_S */
12532 P2Align, offset64_op,
12533 /* LOAD16_U_I32_A32 */
12534 I32, P2Align, offset32_op, I32,
12535 /* LOAD16_U_I32_A32_S */
12536 P2Align, offset32_op,
12537 /* LOAD16_U_I32_A64 */
12538 I32, P2Align, offset64_op, I64,
12539 /* LOAD16_U_I32_A64_S */
12540 P2Align, offset64_op,
12541 /* LOAD16_U_I64_A32 */
12542 I64, P2Align, offset32_op, I32,
12543 /* LOAD16_U_I64_A32_S */
12544 P2Align, offset32_op,
12545 /* LOAD16_U_I64_A64 */
12546 I64, P2Align, offset64_op, I64,
12547 /* LOAD16_U_I64_A64_S */
12548 P2Align, offset64_op,
12549 /* LOAD32_SPLAT_A32 */
12550 V128, P2Align, offset32_op, I32,
12551 /* LOAD32_SPLAT_A32_S */
12552 P2Align, offset32_op,
12553 /* LOAD32_SPLAT_A64 */
12554 V128, P2Align, offset64_op, I64,
12555 /* LOAD32_SPLAT_A64_S */
12556 P2Align, offset64_op,
12557 /* LOAD32_S_I64_A32 */
12558 I64, P2Align, offset32_op, I32,
12559 /* LOAD32_S_I64_A32_S */
12560 P2Align, offset32_op,
12561 /* LOAD32_S_I64_A64 */
12562 I64, P2Align, offset64_op, I64,
12563 /* LOAD32_S_I64_A64_S */
12564 P2Align, offset64_op,
12565 /* LOAD32_U_I64_A32 */
12566 I64, P2Align, offset32_op, I32,
12567 /* LOAD32_U_I64_A32_S */
12568 P2Align, offset32_op,
12569 /* LOAD32_U_I64_A64 */
12570 I64, P2Align, offset64_op, I64,
12571 /* LOAD32_U_I64_A64_S */
12572 P2Align, offset64_op,
12573 /* LOAD64_SPLAT_A32 */
12574 V128, P2Align, offset32_op, I32,
12575 /* LOAD64_SPLAT_A32_S */
12576 P2Align, offset32_op,
12577 /* LOAD64_SPLAT_A64 */
12578 V128, P2Align, offset64_op, I64,
12579 /* LOAD64_SPLAT_A64_S */
12580 P2Align, offset64_op,
12581 /* LOAD8_SPLAT_A32 */
12582 V128, P2Align, offset32_op, I32,
12583 /* LOAD8_SPLAT_A32_S */
12584 P2Align, offset32_op,
12585 /* LOAD8_SPLAT_A64 */
12586 V128, P2Align, offset64_op, I64,
12587 /* LOAD8_SPLAT_A64_S */
12588 P2Align, offset64_op,
12589 /* LOAD8_S_I32_A32 */
12590 I32, P2Align, offset32_op, I32,
12591 /* LOAD8_S_I32_A32_S */
12592 P2Align, offset32_op,
12593 /* LOAD8_S_I32_A64 */
12594 I32, P2Align, offset64_op, I64,
12595 /* LOAD8_S_I32_A64_S */
12596 P2Align, offset64_op,
12597 /* LOAD8_S_I64_A32 */
12598 I64, P2Align, offset32_op, I32,
12599 /* LOAD8_S_I64_A32_S */
12600 P2Align, offset32_op,
12601 /* LOAD8_S_I64_A64 */
12602 I64, P2Align, offset64_op, I64,
12603 /* LOAD8_S_I64_A64_S */
12604 P2Align, offset64_op,
12605 /* LOAD8_U_I32_A32 */
12606 I32, P2Align, offset32_op, I32,
12607 /* LOAD8_U_I32_A32_S */
12608 P2Align, offset32_op,
12609 /* LOAD8_U_I32_A64 */
12610 I32, P2Align, offset64_op, I64,
12611 /* LOAD8_U_I32_A64_S */
12612 P2Align, offset64_op,
12613 /* LOAD8_U_I64_A32 */
12614 I64, P2Align, offset32_op, I32,
12615 /* LOAD8_U_I64_A32_S */
12616 P2Align, offset32_op,
12617 /* LOAD8_U_I64_A64 */
12618 I64, P2Align, offset64_op, I64,
12619 /* LOAD8_U_I64_A64_S */
12620 P2Align, offset64_op,
12621 /* LOAD_EXTEND_S_I16x8_A32 */
12622 V128, P2Align, offset32_op, I32,
12623 /* LOAD_EXTEND_S_I16x8_A32_S */
12624 P2Align, offset32_op,
12625 /* LOAD_EXTEND_S_I16x8_A64 */
12626 V128, P2Align, offset64_op, I64,
12627 /* LOAD_EXTEND_S_I16x8_A64_S */
12628 P2Align, offset64_op,
12629 /* LOAD_EXTEND_S_I32x4_A32 */
12630 V128, P2Align, offset32_op, I32,
12631 /* LOAD_EXTEND_S_I32x4_A32_S */
12632 P2Align, offset32_op,
12633 /* LOAD_EXTEND_S_I32x4_A64 */
12634 V128, P2Align, offset64_op, I64,
12635 /* LOAD_EXTEND_S_I32x4_A64_S */
12636 P2Align, offset64_op,
12637 /* LOAD_EXTEND_S_I64x2_A32 */
12638 V128, P2Align, offset32_op, I32,
12639 /* LOAD_EXTEND_S_I64x2_A32_S */
12640 P2Align, offset32_op,
12641 /* LOAD_EXTEND_S_I64x2_A64 */
12642 V128, P2Align, offset64_op, I64,
12643 /* LOAD_EXTEND_S_I64x2_A64_S */
12644 P2Align, offset64_op,
12645 /* LOAD_EXTEND_U_I16x8_A32 */
12646 V128, P2Align, offset32_op, I32,
12647 /* LOAD_EXTEND_U_I16x8_A32_S */
12648 P2Align, offset32_op,
12649 /* LOAD_EXTEND_U_I16x8_A64 */
12650 V128, P2Align, offset64_op, I64,
12651 /* LOAD_EXTEND_U_I16x8_A64_S */
12652 P2Align, offset64_op,
12653 /* LOAD_EXTEND_U_I32x4_A32 */
12654 V128, P2Align, offset32_op, I32,
12655 /* LOAD_EXTEND_U_I32x4_A32_S */
12656 P2Align, offset32_op,
12657 /* LOAD_EXTEND_U_I32x4_A64 */
12658 V128, P2Align, offset64_op, I64,
12659 /* LOAD_EXTEND_U_I32x4_A64_S */
12660 P2Align, offset64_op,
12661 /* LOAD_EXTEND_U_I64x2_A32 */
12662 V128, P2Align, offset32_op, I32,
12663 /* LOAD_EXTEND_U_I64x2_A32_S */
12664 P2Align, offset32_op,
12665 /* LOAD_EXTEND_U_I64x2_A64 */
12666 V128, P2Align, offset64_op, I64,
12667 /* LOAD_EXTEND_U_I64x2_A64_S */
12668 P2Align, offset64_op,
12669 /* LOAD_F16_F32_A32 */
12670 F32, P2Align, offset32_op, I32,
12671 /* LOAD_F16_F32_A32_S */
12672 P2Align, offset32_op,
12673 /* LOAD_F16_F32_A64 */
12674 F32, P2Align, offset64_op, I64,
12675 /* LOAD_F16_F32_A64_S */
12676 P2Align, offset64_op,
12677 /* LOAD_F32_A32 */
12678 F32, P2Align, offset32_op, I32,
12679 /* LOAD_F32_A32_S */
12680 P2Align, offset32_op,
12681 /* LOAD_F32_A64 */
12682 F32, P2Align, offset64_op, I64,
12683 /* LOAD_F32_A64_S */
12684 P2Align, offset64_op,
12685 /* LOAD_F64_A32 */
12686 F64, P2Align, offset32_op, I32,
12687 /* LOAD_F64_A32_S */
12688 P2Align, offset32_op,
12689 /* LOAD_F64_A64 */
12690 F64, P2Align, offset64_op, I64,
12691 /* LOAD_F64_A64_S */
12692 P2Align, offset64_op,
12693 /* LOAD_I32_A32 */
12694 I32, P2Align, offset32_op, I32,
12695 /* LOAD_I32_A32_S */
12696 P2Align, offset32_op,
12697 /* LOAD_I32_A64 */
12698 I32, P2Align, offset64_op, I64,
12699 /* LOAD_I32_A64_S */
12700 P2Align, offset64_op,
12701 /* LOAD_I64_A32 */
12702 I64, P2Align, offset32_op, I32,
12703 /* LOAD_I64_A32_S */
12704 P2Align, offset32_op,
12705 /* LOAD_I64_A64 */
12706 I64, P2Align, offset64_op, I64,
12707 /* LOAD_I64_A64_S */
12708 P2Align, offset64_op,
12709 /* LOAD_LANE_I16x8_A32 */
12710 V128, P2Align, offset32_op, vec_i8imm_op, I32, V128,
12711 /* LOAD_LANE_I16x8_A32_S */
12712 P2Align, offset32_op, vec_i8imm_op,
12713 /* LOAD_LANE_I16x8_A64 */
12714 V128, P2Align, offset64_op, vec_i8imm_op, I64, V128,
12715 /* LOAD_LANE_I16x8_A64_S */
12716 P2Align, offset64_op, vec_i8imm_op,
12717 /* LOAD_LANE_I32x4_A32 */
12718 V128, P2Align, offset32_op, vec_i8imm_op, I32, V128,
12719 /* LOAD_LANE_I32x4_A32_S */
12720 P2Align, offset32_op, vec_i8imm_op,
12721 /* LOAD_LANE_I32x4_A64 */
12722 V128, P2Align, offset64_op, vec_i8imm_op, I64, V128,
12723 /* LOAD_LANE_I32x4_A64_S */
12724 P2Align, offset64_op, vec_i8imm_op,
12725 /* LOAD_LANE_I64x2_A32 */
12726 V128, P2Align, offset32_op, vec_i8imm_op, I32, V128,
12727 /* LOAD_LANE_I64x2_A32_S */
12728 P2Align, offset32_op, vec_i8imm_op,
12729 /* LOAD_LANE_I64x2_A64 */
12730 V128, P2Align, offset64_op, vec_i8imm_op, I64, V128,
12731 /* LOAD_LANE_I64x2_A64_S */
12732 P2Align, offset64_op, vec_i8imm_op,
12733 /* LOAD_LANE_I8x16_A32 */
12734 V128, P2Align, offset32_op, vec_i8imm_op, I32, V128,
12735 /* LOAD_LANE_I8x16_A32_S */
12736 P2Align, offset32_op, vec_i8imm_op,
12737 /* LOAD_LANE_I8x16_A64 */
12738 V128, P2Align, offset64_op, vec_i8imm_op, I64, V128,
12739 /* LOAD_LANE_I8x16_A64_S */
12740 P2Align, offset64_op, vec_i8imm_op,
12741 /* LOAD_V128_A32 */
12742 V128, P2Align, offset32_op, I32,
12743 /* LOAD_V128_A32_S */
12744 P2Align, offset32_op,
12745 /* LOAD_V128_A64 */
12746 V128, P2Align, offset64_op, I64,
12747 /* LOAD_V128_A64_S */
12748 P2Align, offset64_op,
12749 /* LOAD_ZERO_I32x4_A32 */
12750 V128, P2Align, offset32_op, I32,
12751 /* LOAD_ZERO_I32x4_A32_S */
12752 P2Align, offset32_op,
12753 /* LOAD_ZERO_I32x4_A64 */
12754 V128, P2Align, offset64_op, I64,
12755 /* LOAD_ZERO_I32x4_A64_S */
12756 P2Align, offset64_op,
12757 /* LOAD_ZERO_I64x2_A32 */
12758 V128, P2Align, offset32_op, I32,
12759 /* LOAD_ZERO_I64x2_A32_S */
12760 P2Align, offset32_op,
12761 /* LOAD_ZERO_I64x2_A64 */
12762 V128, P2Align, offset64_op, I64,
12763 /* LOAD_ZERO_I64x2_A64_S */
12764 P2Align, offset64_op,
12765 /* LOCAL_GET_EXNREF */
12766 EXNREF, local_op,
12767 /* LOCAL_GET_EXNREF_S */
12768 local_op,
12769 /* LOCAL_GET_EXTERNREF */
12770 EXTERNREF, local_op,
12771 /* LOCAL_GET_EXTERNREF_S */
12772 local_op,
12773 /* LOCAL_GET_F32 */
12774 F32, local_op,
12775 /* LOCAL_GET_F32_S */
12776 local_op,
12777 /* LOCAL_GET_F64 */
12778 F64, local_op,
12779 /* LOCAL_GET_F64_S */
12780 local_op,
12781 /* LOCAL_GET_FUNCREF */
12782 FUNCREF, local_op,
12783 /* LOCAL_GET_FUNCREF_S */
12784 local_op,
12785 /* LOCAL_GET_I32 */
12786 I32, local_op,
12787 /* LOCAL_GET_I32_S */
12788 local_op,
12789 /* LOCAL_GET_I64 */
12790 I64, local_op,
12791 /* LOCAL_GET_I64_S */
12792 local_op,
12793 /* LOCAL_GET_V128 */
12794 V128, local_op,
12795 /* LOCAL_GET_V128_S */
12796 local_op,
12797 /* LOCAL_SET_EXNREF */
12798 local_op, EXNREF,
12799 /* LOCAL_SET_EXNREF_S */
12800 local_op,
12801 /* LOCAL_SET_EXTERNREF */
12802 local_op, EXTERNREF,
12803 /* LOCAL_SET_EXTERNREF_S */
12804 local_op,
12805 /* LOCAL_SET_F32 */
12806 local_op, F32,
12807 /* LOCAL_SET_F32_S */
12808 local_op,
12809 /* LOCAL_SET_F64 */
12810 local_op, F64,
12811 /* LOCAL_SET_F64_S */
12812 local_op,
12813 /* LOCAL_SET_FUNCREF */
12814 local_op, FUNCREF,
12815 /* LOCAL_SET_FUNCREF_S */
12816 local_op,
12817 /* LOCAL_SET_I32 */
12818 local_op, I32,
12819 /* LOCAL_SET_I32_S */
12820 local_op,
12821 /* LOCAL_SET_I64 */
12822 local_op, I64,
12823 /* LOCAL_SET_I64_S */
12824 local_op,
12825 /* LOCAL_SET_V128 */
12826 local_op, V128,
12827 /* LOCAL_SET_V128_S */
12828 local_op,
12829 /* LOCAL_TEE_EXNREF */
12830 EXNREF, local_op, EXNREF,
12831 /* LOCAL_TEE_EXNREF_S */
12832 local_op,
12833 /* LOCAL_TEE_EXTERNREF */
12834 EXTERNREF, local_op, EXTERNREF,
12835 /* LOCAL_TEE_EXTERNREF_S */
12836 local_op,
12837 /* LOCAL_TEE_F32 */
12838 F32, local_op, F32,
12839 /* LOCAL_TEE_F32_S */
12840 local_op,
12841 /* LOCAL_TEE_F64 */
12842 F64, local_op, F64,
12843 /* LOCAL_TEE_F64_S */
12844 local_op,
12845 /* LOCAL_TEE_FUNCREF */
12846 FUNCREF, local_op, FUNCREF,
12847 /* LOCAL_TEE_FUNCREF_S */
12848 local_op,
12849 /* LOCAL_TEE_I32 */
12850 I32, local_op, I32,
12851 /* LOCAL_TEE_I32_S */
12852 local_op,
12853 /* LOCAL_TEE_I64 */
12854 I64, local_op, I64,
12855 /* LOCAL_TEE_I64_S */
12856 local_op,
12857 /* LOCAL_TEE_V128 */
12858 V128, local_op, V128,
12859 /* LOCAL_TEE_V128_S */
12860 local_op,
12861 /* LOOP */
12862 Signature,
12863 /* LOOP_S */
12864 Signature,
12865 /* LT_F16x8 */
12866 V128, V128, V128,
12867 /* LT_F16x8_S */
12868 /* LT_F32 */
12869 I32, F32, F32,
12870 /* LT_F32_S */
12871 /* LT_F32x4 */
12872 V128, V128, V128,
12873 /* LT_F32x4_S */
12874 /* LT_F64 */
12875 I32, F64, F64,
12876 /* LT_F64_S */
12877 /* LT_F64x2 */
12878 V128, V128, V128,
12879 /* LT_F64x2_S */
12880 /* LT_S_I16x8 */
12881 V128, V128, V128,
12882 /* LT_S_I16x8_S */
12883 /* LT_S_I32 */
12884 I32, I32, I32,
12885 /* LT_S_I32_S */
12886 /* LT_S_I32x4 */
12887 V128, V128, V128,
12888 /* LT_S_I32x4_S */
12889 /* LT_S_I64 */
12890 I32, I64, I64,
12891 /* LT_S_I64_S */
12892 /* LT_S_I64x2 */
12893 V128, V128, V128,
12894 /* LT_S_I64x2_S */
12895 /* LT_S_I8x16 */
12896 V128, V128, V128,
12897 /* LT_S_I8x16_S */
12898 /* LT_U_I16x8 */
12899 V128, V128, V128,
12900 /* LT_U_I16x8_S */
12901 /* LT_U_I32 */
12902 I32, I32, I32,
12903 /* LT_U_I32_S */
12904 /* LT_U_I32x4 */
12905 V128, V128, V128,
12906 /* LT_U_I32x4_S */
12907 /* LT_U_I64 */
12908 I32, I64, I64,
12909 /* LT_U_I64_S */
12910 /* LT_U_I8x16 */
12911 V128, V128, V128,
12912 /* LT_U_I8x16_S */
12913 /* MADD_F16x8 */
12914 V128, V128, V128, V128,
12915 /* MADD_F16x8_S */
12916 /* MADD_F32x4 */
12917 V128, V128, V128, V128,
12918 /* MADD_F32x4_S */
12919 /* MADD_F64x2 */
12920 V128, V128, V128, V128,
12921 /* MADD_F64x2_S */
12922 /* MAX_F16x8 */
12923 V128, V128, V128,
12924 /* MAX_F16x8_S */
12925 /* MAX_F32 */
12926 F32, F32, F32,
12927 /* MAX_F32_S */
12928 /* MAX_F32x4 */
12929 V128, V128, V128,
12930 /* MAX_F32x4_S */
12931 /* MAX_F64 */
12932 F64, F64, F64,
12933 /* MAX_F64_S */
12934 /* MAX_F64x2 */
12935 V128, V128, V128,
12936 /* MAX_F64x2_S */
12937 /* MAX_S_I16x8 */
12938 V128, V128, V128,
12939 /* MAX_S_I16x8_S */
12940 /* MAX_S_I32x4 */
12941 V128, V128, V128,
12942 /* MAX_S_I32x4_S */
12943 /* MAX_S_I8x16 */
12944 V128, V128, V128,
12945 /* MAX_S_I8x16_S */
12946 /* MAX_U_I16x8 */
12947 V128, V128, V128,
12948 /* MAX_U_I16x8_S */
12949 /* MAX_U_I32x4 */
12950 V128, V128, V128,
12951 /* MAX_U_I32x4_S */
12952 /* MAX_U_I8x16 */
12953 V128, V128, V128,
12954 /* MAX_U_I8x16_S */
12955 /* MEMORY_ATOMIC_NOTIFY_A32 */
12956 I32, P2Align, offset32_op, I32, I32,
12957 /* MEMORY_ATOMIC_NOTIFY_A32_S */
12958 P2Align, offset32_op,
12959 /* MEMORY_ATOMIC_NOTIFY_A64 */
12960 I32, P2Align, offset64_op, I64, I32,
12961 /* MEMORY_ATOMIC_NOTIFY_A64_S */
12962 P2Align, offset64_op,
12963 /* MEMORY_ATOMIC_WAIT32_A32 */
12964 I32, P2Align, offset32_op, I32, I32, I64,
12965 /* MEMORY_ATOMIC_WAIT32_A32_S */
12966 P2Align, offset32_op,
12967 /* MEMORY_ATOMIC_WAIT32_A64 */
12968 I32, P2Align, offset64_op, I64, I32, I64,
12969 /* MEMORY_ATOMIC_WAIT32_A64_S */
12970 P2Align, offset64_op,
12971 /* MEMORY_ATOMIC_WAIT64_A32 */
12972 I32, P2Align, offset32_op, I32, I64, I64,
12973 /* MEMORY_ATOMIC_WAIT64_A32_S */
12974 P2Align, offset32_op,
12975 /* MEMORY_ATOMIC_WAIT64_A64 */
12976 I32, P2Align, offset64_op, I64, I64, I64,
12977 /* MEMORY_ATOMIC_WAIT64_A64_S */
12978 P2Align, offset64_op,
12979 /* MIN_F16x8 */
12980 V128, V128, V128,
12981 /* MIN_F16x8_S */
12982 /* MIN_F32 */
12983 F32, F32, F32,
12984 /* MIN_F32_S */
12985 /* MIN_F32x4 */
12986 V128, V128, V128,
12987 /* MIN_F32x4_S */
12988 /* MIN_F64 */
12989 F64, F64, F64,
12990 /* MIN_F64_S */
12991 /* MIN_F64x2 */
12992 V128, V128, V128,
12993 /* MIN_F64x2_S */
12994 /* MIN_S_I16x8 */
12995 V128, V128, V128,
12996 /* MIN_S_I16x8_S */
12997 /* MIN_S_I32x4 */
12998 V128, V128, V128,
12999 /* MIN_S_I32x4_S */
13000 /* MIN_S_I8x16 */
13001 V128, V128, V128,
13002 /* MIN_S_I8x16_S */
13003 /* MIN_U_I16x8 */
13004 V128, V128, V128,
13005 /* MIN_U_I16x8_S */
13006 /* MIN_U_I32x4 */
13007 V128, V128, V128,
13008 /* MIN_U_I32x4_S */
13009 /* MIN_U_I8x16 */
13010 V128, V128, V128,
13011 /* MIN_U_I8x16_S */
13012 /* MUL_F16x8 */
13013 V128, V128, V128,
13014 /* MUL_F16x8_S */
13015 /* MUL_F32 */
13016 F32, F32, F32,
13017 /* MUL_F32_S */
13018 /* MUL_F32x4 */
13019 V128, V128, V128,
13020 /* MUL_F32x4_S */
13021 /* MUL_F64 */
13022 F64, F64, F64,
13023 /* MUL_F64_S */
13024 /* MUL_F64x2 */
13025 V128, V128, V128,
13026 /* MUL_F64x2_S */
13027 /* MUL_I16x8 */
13028 V128, V128, V128,
13029 /* MUL_I16x8_S */
13030 /* MUL_I32 */
13031 I32, I32, I32,
13032 /* MUL_I32_S */
13033 /* MUL_I32x4 */
13034 V128, V128, V128,
13035 /* MUL_I32x4_S */
13036 /* MUL_I64 */
13037 I64, I64, I64,
13038 /* MUL_I64_S */
13039 /* MUL_I64x2 */
13040 V128, V128, V128,
13041 /* MUL_I64x2_S */
13042 /* NARROW_S_I16x8 */
13043 V128, V128, V128,
13044 /* NARROW_S_I16x8_S */
13045 /* NARROW_S_I8x16 */
13046 V128, V128, V128,
13047 /* NARROW_S_I8x16_S */
13048 /* NARROW_U_I16x8 */
13049 V128, V128, V128,
13050 /* NARROW_U_I16x8_S */
13051 /* NARROW_U_I8x16 */
13052 V128, V128, V128,
13053 /* NARROW_U_I8x16_S */
13054 /* NEAREST_F16x8 */
13055 V128, V128,
13056 /* NEAREST_F16x8_S */
13057 /* NEAREST_F32 */
13058 F32, F32,
13059 /* NEAREST_F32_S */
13060 /* NEAREST_F32x4 */
13061 V128, V128,
13062 /* NEAREST_F32x4_S */
13063 /* NEAREST_F64 */
13064 F64, F64,
13065 /* NEAREST_F64_S */
13066 /* NEAREST_F64x2 */
13067 V128, V128,
13068 /* NEAREST_F64x2_S */
13069 /* NEG_F16x8 */
13070 V128, V128,
13071 /* NEG_F16x8_S */
13072 /* NEG_F32 */
13073 F32, F32,
13074 /* NEG_F32_S */
13075 /* NEG_F32x4 */
13076 V128, V128,
13077 /* NEG_F32x4_S */
13078 /* NEG_F64 */
13079 F64, F64,
13080 /* NEG_F64_S */
13081 /* NEG_F64x2 */
13082 V128, V128,
13083 /* NEG_F64x2_S */
13084 /* NEG_I16x8 */
13085 V128, V128,
13086 /* NEG_I16x8_S */
13087 /* NEG_I32x4 */
13088 V128, V128,
13089 /* NEG_I32x4_S */
13090 /* NEG_I64x2 */
13091 V128, V128,
13092 /* NEG_I64x2_S */
13093 /* NEG_I8x16 */
13094 V128, V128,
13095 /* NEG_I8x16_S */
13096 /* NE_F16x8 */
13097 V128, V128, V128,
13098 /* NE_F16x8_S */
13099 /* NE_F32 */
13100 I32, F32, F32,
13101 /* NE_F32_S */
13102 /* NE_F32x4 */
13103 V128, V128, V128,
13104 /* NE_F32x4_S */
13105 /* NE_F64 */
13106 I32, F64, F64,
13107 /* NE_F64_S */
13108 /* NE_F64x2 */
13109 V128, V128, V128,
13110 /* NE_F64x2_S */
13111 /* NE_I16x8 */
13112 V128, V128, V128,
13113 /* NE_I16x8_S */
13114 /* NE_I32 */
13115 I32, I32, I32,
13116 /* NE_I32_S */
13117 /* NE_I32x4 */
13118 V128, V128, V128,
13119 /* NE_I32x4_S */
13120 /* NE_I64 */
13121 I32, I64, I64,
13122 /* NE_I64_S */
13123 /* NE_I64x2 */
13124 V128, V128, V128,
13125 /* NE_I64x2_S */
13126 /* NE_I8x16 */
13127 V128, V128, V128,
13128 /* NE_I8x16_S */
13129 /* NMADD_F16x8 */
13130 V128, V128, V128, V128,
13131 /* NMADD_F16x8_S */
13132 /* NMADD_F32x4 */
13133 V128, V128, V128, V128,
13134 /* NMADD_F32x4_S */
13135 /* NMADD_F64x2 */
13136 V128, V128, V128, V128,
13137 /* NMADD_F64x2_S */
13138 /* NOP */
13139 /* NOP_S */
13140 /* NOT */
13141 V128, V128,
13142 /* NOT_S */
13143 /* OR */
13144 V128, V128, V128,
13145 /* OR_I32 */
13146 I32, I32, I32,
13147 /* OR_I32_S */
13148 /* OR_I64 */
13149 I64, I64, I64,
13150 /* OR_I64_S */
13151 /* OR_S */
13152 /* PMAX_F16x8 */
13153 V128, V128, V128,
13154 /* PMAX_F16x8_S */
13155 /* PMAX_F32x4 */
13156 V128, V128, V128,
13157 /* PMAX_F32x4_S */
13158 /* PMAX_F64x2 */
13159 V128, V128, V128,
13160 /* PMAX_F64x2_S */
13161 /* PMIN_F16x8 */
13162 V128, V128, V128,
13163 /* PMIN_F16x8_S */
13164 /* PMIN_F32x4 */
13165 V128, V128, V128,
13166 /* PMIN_F32x4_S */
13167 /* PMIN_F64x2 */
13168 V128, V128, V128,
13169 /* PMIN_F64x2_S */
13170 /* POPCNT_I32 */
13171 I32, I32,
13172 /* POPCNT_I32_S */
13173 /* POPCNT_I64 */
13174 I64, I64,
13175 /* POPCNT_I64_S */
13176 /* POPCNT_I8x16 */
13177 V128, V128,
13178 /* POPCNT_I8x16_S */
13179 /* Q15MULR_SAT_S_I16x8 */
13180 V128, V128, V128,
13181 /* Q15MULR_SAT_S_I16x8_S */
13182 /* REF_IS_NULL_EXNREF */
13183 I32, EXNREF,
13184 /* REF_IS_NULL_EXNREF_S */
13185 /* REF_IS_NULL_EXTERNREF */
13186 I32, EXTERNREF,
13187 /* REF_IS_NULL_EXTERNREF_S */
13188 /* REF_IS_NULL_FUNCREF */
13189 I32, FUNCREF,
13190 /* REF_IS_NULL_FUNCREF_S */
13191 /* REF_NULL_EXNREF */
13192 EXNREF,
13193 /* REF_NULL_EXNREF_S */
13194 /* REF_NULL_EXTERNREF */
13195 EXTERNREF,
13196 /* REF_NULL_EXTERNREF_S */
13197 /* REF_NULL_FUNCREF */
13198 FUNCREF,
13199 /* REF_NULL_FUNCREF_S */
13200 /* RELAXED_DOT */
13201 V128, V128, V128,
13202 /* RELAXED_DOT_ADD */
13203 V128, V128, V128, V128,
13204 /* RELAXED_DOT_ADD_S */
13205 /* RELAXED_DOT_BFLOAT */
13206 V128, V128, V128, V128,
13207 /* RELAXED_DOT_BFLOAT_S */
13208 /* RELAXED_DOT_S */
13209 /* RELAXED_Q15MULR_S_I16x8 */
13210 V128, V128, V128,
13211 /* RELAXED_Q15MULR_S_I16x8_S */
13212 /* RELAXED_SWIZZLE */
13213 V128, V128, V128,
13214 /* RELAXED_SWIZZLE_S */
13215 /* REM_S_I32 */
13216 I32, I32, I32,
13217 /* REM_S_I32_S */
13218 /* REM_S_I64 */
13219 I64, I64, I64,
13220 /* REM_S_I64_S */
13221 /* REM_U_I32 */
13222 I32, I32, I32,
13223 /* REM_U_I32_S */
13224 /* REM_U_I64 */
13225 I64, I64, I64,
13226 /* REM_U_I64_S */
13227 /* REPLACE_LANE_F32x4 */
13228 V128, V128, vec_i8imm_op, F32,
13229 /* REPLACE_LANE_F32x4_S */
13230 vec_i8imm_op,
13231 /* REPLACE_LANE_F64x2 */
13232 V128, V128, vec_i8imm_op, F64,
13233 /* REPLACE_LANE_F64x2_S */
13234 vec_i8imm_op,
13235 /* REPLACE_LANE_I16x8 */
13236 V128, V128, vec_i8imm_op, I32,
13237 /* REPLACE_LANE_I16x8_S */
13238 vec_i8imm_op,
13239 /* REPLACE_LANE_I32x4 */
13240 V128, V128, vec_i8imm_op, I32,
13241 /* REPLACE_LANE_I32x4_S */
13242 vec_i8imm_op,
13243 /* REPLACE_LANE_I64x2 */
13244 V128, V128, vec_i8imm_op, I64,
13245 /* REPLACE_LANE_I64x2_S */
13246 vec_i8imm_op,
13247 /* REPLACE_LANE_I8x16 */
13248 V128, V128, vec_i8imm_op, I32,
13249 /* REPLACE_LANE_I8x16_S */
13250 vec_i8imm_op,
13251 /* RETHROW */
13252 i32imm,
13253 /* RETHROW_S */
13254 i32imm,
13255 /* RETURN */
13256 /* RETURN_S */
13257 /* RET_CALL */
13258 function32_op,
13259 /* RET_CALL_INDIRECT */
13260 TypeIndex, table32_op,
13261 /* RET_CALL_INDIRECT_S */
13262 TypeIndex, table32_op,
13263 /* RET_CALL_S */
13264 function32_op,
13265 /* ROTL_I32 */
13266 I32, I32, I32,
13267 /* ROTL_I32_S */
13268 /* ROTL_I64 */
13269 I64, I64, I64,
13270 /* ROTL_I64_S */
13271 /* ROTR_I32 */
13272 I32, I32, I32,
13273 /* ROTR_I32_S */
13274 /* ROTR_I64 */
13275 I64, I64, I64,
13276 /* ROTR_I64_S */
13277 /* SELECT_EXNREF */
13278 EXNREF, EXNREF, EXNREF, I32,
13279 /* SELECT_EXNREF_S */
13280 /* SELECT_EXTERNREF */
13281 EXTERNREF, EXTERNREF, EXTERNREF, I32,
13282 /* SELECT_EXTERNREF_S */
13283 /* SELECT_F32 */
13284 F32, F32, F32, I32,
13285 /* SELECT_F32_S */
13286 /* SELECT_F64 */
13287 F64, F64, F64, I32,
13288 /* SELECT_F64_S */
13289 /* SELECT_FUNCREF */
13290 FUNCREF, FUNCREF, FUNCREF, I32,
13291 /* SELECT_FUNCREF_S */
13292 /* SELECT_I32 */
13293 I32, I32, I32, I32,
13294 /* SELECT_I32_S */
13295 /* SELECT_I64 */
13296 I64, I64, I64, I32,
13297 /* SELECT_I64_S */
13298 /* SELECT_V128 */
13299 V128, V128, V128, I32,
13300 /* SELECT_V128_S */
13301 /* SHL_I16x8 */
13302 V128, V128, I32,
13303 /* SHL_I16x8_S */
13304 /* SHL_I32 */
13305 I32, I32, I32,
13306 /* SHL_I32_S */
13307 /* SHL_I32x4 */
13308 V128, V128, I32,
13309 /* SHL_I32x4_S */
13310 /* SHL_I64 */
13311 I64, I64, I64,
13312 /* SHL_I64_S */
13313 /* SHL_I64x2 */
13314 V128, V128, I32,
13315 /* SHL_I64x2_S */
13316 /* SHL_I8x16 */
13317 V128, V128, I32,
13318 /* SHL_I8x16_S */
13319 /* SHR_S_I16x8 */
13320 V128, V128, I32,
13321 /* SHR_S_I16x8_S */
13322 /* SHR_S_I32 */
13323 I32, I32, I32,
13324 /* SHR_S_I32_S */
13325 /* SHR_S_I32x4 */
13326 V128, V128, I32,
13327 /* SHR_S_I32x4_S */
13328 /* SHR_S_I64 */
13329 I64, I64, I64,
13330 /* SHR_S_I64_S */
13331 /* SHR_S_I64x2 */
13332 V128, V128, I32,
13333 /* SHR_S_I64x2_S */
13334 /* SHR_S_I8x16 */
13335 V128, V128, I32,
13336 /* SHR_S_I8x16_S */
13337 /* SHR_U_I16x8 */
13338 V128, V128, I32,
13339 /* SHR_U_I16x8_S */
13340 /* SHR_U_I32 */
13341 I32, I32, I32,
13342 /* SHR_U_I32_S */
13343 /* SHR_U_I32x4 */
13344 V128, V128, I32,
13345 /* SHR_U_I32x4_S */
13346 /* SHR_U_I64 */
13347 I64, I64, I64,
13348 /* SHR_U_I64_S */
13349 /* SHR_U_I64x2 */
13350 V128, V128, I32,
13351 /* SHR_U_I64x2_S */
13352 /* SHR_U_I8x16 */
13353 V128, V128, I32,
13354 /* SHR_U_I8x16_S */
13355 /* SHUFFLE */
13356 V128, V128, V128, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op,
13357 /* SHUFFLE_S */
13358 vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op, vec_i8imm_op,
13359 /* SIMD_RELAXED_FMAX_F32x4 */
13360 V128, V128, V128,
13361 /* SIMD_RELAXED_FMAX_F32x4_S */
13362 /* SIMD_RELAXED_FMAX_F64x2 */
13363 V128, V128, V128,
13364 /* SIMD_RELAXED_FMAX_F64x2_S */
13365 /* SIMD_RELAXED_FMIN_F32x4 */
13366 V128, V128, V128,
13367 /* SIMD_RELAXED_FMIN_F32x4_S */
13368 /* SIMD_RELAXED_FMIN_F64x2 */
13369 V128, V128, V128,
13370 /* SIMD_RELAXED_FMIN_F64x2_S */
13371 /* SPLAT_F16x8 */
13372 V128, F32,
13373 /* SPLAT_F16x8_S */
13374 /* SPLAT_F32x4 */
13375 V128, F32,
13376 /* SPLAT_F32x4_S */
13377 /* SPLAT_F64x2 */
13378 V128, F64,
13379 /* SPLAT_F64x2_S */
13380 /* SPLAT_I16x8 */
13381 V128, I32,
13382 /* SPLAT_I16x8_S */
13383 /* SPLAT_I32x4 */
13384 V128, I32,
13385 /* SPLAT_I32x4_S */
13386 /* SPLAT_I64x2 */
13387 V128, I64,
13388 /* SPLAT_I64x2_S */
13389 /* SPLAT_I8x16 */
13390 V128, I32,
13391 /* SPLAT_I8x16_S */
13392 /* SQRT_F16x8 */
13393 V128, V128,
13394 /* SQRT_F16x8_S */
13395 /* SQRT_F32 */
13396 F32, F32,
13397 /* SQRT_F32_S */
13398 /* SQRT_F32x4 */
13399 V128, V128,
13400 /* SQRT_F32x4_S */
13401 /* SQRT_F64 */
13402 F64, F64,
13403 /* SQRT_F64_S */
13404 /* SQRT_F64x2 */
13405 V128, V128,
13406 /* SQRT_F64x2_S */
13407 /* STORE16_I32_A32 */
13408 P2Align, offset32_op, I32, I32,
13409 /* STORE16_I32_A32_S */
13410 P2Align, offset32_op,
13411 /* STORE16_I32_A64 */
13412 P2Align, offset64_op, I64, I32,
13413 /* STORE16_I32_A64_S */
13414 P2Align, offset64_op,
13415 /* STORE16_I64_A32 */
13416 P2Align, offset32_op, I32, I64,
13417 /* STORE16_I64_A32_S */
13418 P2Align, offset32_op,
13419 /* STORE16_I64_A64 */
13420 P2Align, offset64_op, I64, I64,
13421 /* STORE16_I64_A64_S */
13422 P2Align, offset64_op,
13423 /* STORE32_I64_A32 */
13424 P2Align, offset32_op, I32, I64,
13425 /* STORE32_I64_A32_S */
13426 P2Align, offset32_op,
13427 /* STORE32_I64_A64 */
13428 P2Align, offset64_op, I64, I64,
13429 /* STORE32_I64_A64_S */
13430 P2Align, offset64_op,
13431 /* STORE8_I32_A32 */
13432 P2Align, offset32_op, I32, I32,
13433 /* STORE8_I32_A32_S */
13434 P2Align, offset32_op,
13435 /* STORE8_I32_A64 */
13436 P2Align, offset64_op, I64, I32,
13437 /* STORE8_I32_A64_S */
13438 P2Align, offset64_op,
13439 /* STORE8_I64_A32 */
13440 P2Align, offset32_op, I32, I64,
13441 /* STORE8_I64_A32_S */
13442 P2Align, offset32_op,
13443 /* STORE8_I64_A64 */
13444 P2Align, offset64_op, I64, I64,
13445 /* STORE8_I64_A64_S */
13446 P2Align, offset64_op,
13447 /* STORE_F16_F32_A32 */
13448 P2Align, offset32_op, I32, F32,
13449 /* STORE_F16_F32_A32_S */
13450 P2Align, offset32_op,
13451 /* STORE_F16_F32_A64 */
13452 P2Align, offset64_op, I64, F32,
13453 /* STORE_F16_F32_A64_S */
13454 P2Align, offset64_op,
13455 /* STORE_F32_A32 */
13456 P2Align, offset32_op, I32, F32,
13457 /* STORE_F32_A32_S */
13458 P2Align, offset32_op,
13459 /* STORE_F32_A64 */
13460 P2Align, offset64_op, I64, F32,
13461 /* STORE_F32_A64_S */
13462 P2Align, offset64_op,
13463 /* STORE_F64_A32 */
13464 P2Align, offset32_op, I32, F64,
13465 /* STORE_F64_A32_S */
13466 P2Align, offset32_op,
13467 /* STORE_F64_A64 */
13468 P2Align, offset64_op, I64, F64,
13469 /* STORE_F64_A64_S */
13470 P2Align, offset64_op,
13471 /* STORE_I32_A32 */
13472 P2Align, offset32_op, I32, I32,
13473 /* STORE_I32_A32_S */
13474 P2Align, offset32_op,
13475 /* STORE_I32_A64 */
13476 P2Align, offset64_op, I64, I32,
13477 /* STORE_I32_A64_S */
13478 P2Align, offset64_op,
13479 /* STORE_I64_A32 */
13480 P2Align, offset32_op, I32, I64,
13481 /* STORE_I64_A32_S */
13482 P2Align, offset32_op,
13483 /* STORE_I64_A64 */
13484 P2Align, offset64_op, I64, I64,
13485 /* STORE_I64_A64_S */
13486 P2Align, offset64_op,
13487 /* STORE_LANE_I16x8_A32 */
13488 P2Align, offset32_op, vec_i8imm_op, I32, V128,
13489 /* STORE_LANE_I16x8_A32_S */
13490 P2Align, offset32_op, vec_i8imm_op,
13491 /* STORE_LANE_I16x8_A64 */
13492 P2Align, offset64_op, vec_i8imm_op, I64, V128,
13493 /* STORE_LANE_I16x8_A64_S */
13494 P2Align, offset64_op, vec_i8imm_op,
13495 /* STORE_LANE_I32x4_A32 */
13496 P2Align, offset32_op, vec_i8imm_op, I32, V128,
13497 /* STORE_LANE_I32x4_A32_S */
13498 P2Align, offset32_op, vec_i8imm_op,
13499 /* STORE_LANE_I32x4_A64 */
13500 P2Align, offset64_op, vec_i8imm_op, I64, V128,
13501 /* STORE_LANE_I32x4_A64_S */
13502 P2Align, offset64_op, vec_i8imm_op,
13503 /* STORE_LANE_I64x2_A32 */
13504 P2Align, offset32_op, vec_i8imm_op, I32, V128,
13505 /* STORE_LANE_I64x2_A32_S */
13506 P2Align, offset32_op, vec_i8imm_op,
13507 /* STORE_LANE_I64x2_A64 */
13508 P2Align, offset64_op, vec_i8imm_op, I64, V128,
13509 /* STORE_LANE_I64x2_A64_S */
13510 P2Align, offset64_op, vec_i8imm_op,
13511 /* STORE_LANE_I8x16_A32 */
13512 P2Align, offset32_op, vec_i8imm_op, I32, V128,
13513 /* STORE_LANE_I8x16_A32_S */
13514 P2Align, offset32_op, vec_i8imm_op,
13515 /* STORE_LANE_I8x16_A64 */
13516 P2Align, offset64_op, vec_i8imm_op, I64, V128,
13517 /* STORE_LANE_I8x16_A64_S */
13518 P2Align, offset64_op, vec_i8imm_op,
13519 /* STORE_V128_A32 */
13520 P2Align, offset32_op, I32, V128,
13521 /* STORE_V128_A32_S */
13522 P2Align, offset32_op,
13523 /* STORE_V128_A64 */
13524 P2Align, offset64_op, I64, V128,
13525 /* STORE_V128_A64_S */
13526 P2Align, offset64_op,
13527 /* SUB_F16x8 */
13528 V128, V128, V128,
13529 /* SUB_F16x8_S */
13530 /* SUB_F32 */
13531 F32, F32, F32,
13532 /* SUB_F32_S */
13533 /* SUB_F32x4 */
13534 V128, V128, V128,
13535 /* SUB_F32x4_S */
13536 /* SUB_F64 */
13537 F64, F64, F64,
13538 /* SUB_F64_S */
13539 /* SUB_F64x2 */
13540 V128, V128, V128,
13541 /* SUB_F64x2_S */
13542 /* SUB_I16x8 */
13543 V128, V128, V128,
13544 /* SUB_I16x8_S */
13545 /* SUB_I32 */
13546 I32, I32, I32,
13547 /* SUB_I32_S */
13548 /* SUB_I32x4 */
13549 V128, V128, V128,
13550 /* SUB_I32x4_S */
13551 /* SUB_I64 */
13552 I64, I64, I64,
13553 /* SUB_I64_S */
13554 /* SUB_I64x2 */
13555 V128, V128, V128,
13556 /* SUB_I64x2_S */
13557 /* SUB_I8x16 */
13558 V128, V128, V128,
13559 /* SUB_I8x16_S */
13560 /* SUB_SAT_S_I16x8 */
13561 V128, V128, V128,
13562 /* SUB_SAT_S_I16x8_S */
13563 /* SUB_SAT_S_I8x16 */
13564 V128, V128, V128,
13565 /* SUB_SAT_S_I8x16_S */
13566 /* SUB_SAT_U_I16x8 */
13567 V128, V128, V128,
13568 /* SUB_SAT_U_I16x8_S */
13569 /* SUB_SAT_U_I8x16 */
13570 V128, V128, V128,
13571 /* SUB_SAT_U_I8x16_S */
13572 /* SWIZZLE */
13573 V128, V128, V128,
13574 /* SWIZZLE_S */
13575 /* TABLE_COPY */
13576 table32_op, table32_op, I32, I32, I32,
13577 /* TABLE_COPY_S */
13578 table32_op, table32_op,
13579 /* TABLE_FILL_EXNREF */
13580 table32_op, I32, EXNREF, I32,
13581 /* TABLE_FILL_EXNREF_S */
13582 table32_op,
13583 /* TABLE_FILL_EXTERNREF */
13584 table32_op, I32, EXTERNREF, I32,
13585 /* TABLE_FILL_EXTERNREF_S */
13586 table32_op,
13587 /* TABLE_FILL_FUNCREF */
13588 table32_op, I32, FUNCREF, I32,
13589 /* TABLE_FILL_FUNCREF_S */
13590 table32_op,
13591 /* TABLE_GET_EXNREF */
13592 EXNREF, table32_op, I32,
13593 /* TABLE_GET_EXNREF_S */
13594 table32_op,
13595 /* TABLE_GET_EXTERNREF */
13596 EXTERNREF, table32_op, I32,
13597 /* TABLE_GET_EXTERNREF_S */
13598 table32_op,
13599 /* TABLE_GET_FUNCREF */
13600 FUNCREF, table32_op, I32,
13601 /* TABLE_GET_FUNCREF_S */
13602 table32_op,
13603 /* TABLE_GROW_EXNREF */
13604 I32, table32_op, EXNREF, I32,
13605 /* TABLE_GROW_EXNREF_S */
13606 table32_op,
13607 /* TABLE_GROW_EXTERNREF */
13608 I32, table32_op, EXTERNREF, I32,
13609 /* TABLE_GROW_EXTERNREF_S */
13610 table32_op,
13611 /* TABLE_GROW_FUNCREF */
13612 I32, table32_op, FUNCREF, I32,
13613 /* TABLE_GROW_FUNCREF_S */
13614 table32_op,
13615 /* TABLE_SET_EXNREF */
13616 table32_op, I32, EXNREF,
13617 /* TABLE_SET_EXNREF_S */
13618 table32_op,
13619 /* TABLE_SET_EXTERNREF */
13620 table32_op, I32, EXTERNREF,
13621 /* TABLE_SET_EXTERNREF_S */
13622 table32_op,
13623 /* TABLE_SET_FUNCREF */
13624 table32_op, I32, FUNCREF,
13625 /* TABLE_SET_FUNCREF_S */
13626 table32_op,
13627 /* TABLE_SIZE */
13628 I32, table32_op,
13629 /* TABLE_SIZE_S */
13630 table32_op,
13631 /* TEE_EXNREF */
13632 EXNREF, EXNREF, EXNREF,
13633 /* TEE_EXNREF_S */
13634 /* TEE_EXTERNREF */
13635 EXTERNREF, EXTERNREF, EXTERNREF,
13636 /* TEE_EXTERNREF_S */
13637 /* TEE_F32 */
13638 F32, F32, F32,
13639 /* TEE_F32_S */
13640 /* TEE_F64 */
13641 F64, F64, F64,
13642 /* TEE_F64_S */
13643 /* TEE_FUNCREF */
13644 FUNCREF, FUNCREF, FUNCREF,
13645 /* TEE_FUNCREF_S */
13646 /* TEE_I32 */
13647 I32, I32, I32,
13648 /* TEE_I32_S */
13649 /* TEE_I64 */
13650 I64, I64, I64,
13651 /* TEE_I64_S */
13652 /* TEE_V128 */
13653 V128, V128, V128,
13654 /* TEE_V128_S */
13655 /* THROW */
13656 tag_op,
13657 /* THROW_S */
13658 tag_op,
13659 /* TRUNC_F16x8 */
13660 V128, V128,
13661 /* TRUNC_F16x8_S */
13662 /* TRUNC_F32 */
13663 F32, F32,
13664 /* TRUNC_F32_S */
13665 /* TRUNC_F32x4 */
13666 V128, V128,
13667 /* TRUNC_F32x4_S */
13668 /* TRUNC_F64 */
13669 F64, F64,
13670 /* TRUNC_F64_S */
13671 /* TRUNC_F64x2 */
13672 V128, V128,
13673 /* TRUNC_F64x2_S */
13674 /* TRY */
13675 Signature,
13676 /* TRY_S */
13677 Signature,
13678 /* UNREACHABLE */
13679 /* UNREACHABLE_S */
13680 /* XOR */
13681 V128, V128, V128,
13682 /* XOR_I32 */
13683 I32, I32, I32,
13684 /* XOR_I32_S */
13685 /* XOR_I64 */
13686 I64, I64, I64,
13687 /* XOR_I64_S */
13688 /* XOR_S */
13689 /* anonymous_8187MEMORY_GROW_A32 */
13690 I32, i32imm, I32,
13691 /* anonymous_8187MEMORY_GROW_A32_S */
13692 i32imm,
13693 /* anonymous_8187MEMORY_SIZE_A32 */
13694 I32, i32imm,
13695 /* anonymous_8187MEMORY_SIZE_A32_S */
13696 i32imm,
13697 /* anonymous_8188MEMORY_GROW_A64 */
13698 I64, i32imm, I64,
13699 /* anonymous_8188MEMORY_GROW_A64_S */
13700 i32imm,
13701 /* anonymous_8188MEMORY_SIZE_A64 */
13702 I64, i32imm,
13703 /* anonymous_8188MEMORY_SIZE_A64_S */
13704 i32imm,
13705 /* anonymous_8878DATA_DROP */
13706 i32imm_op,
13707 /* anonymous_8878DATA_DROP_S */
13708 i32imm_op,
13709 /* anonymous_8878MEMORY_COPY_A32 */
13710 i32imm_op, i32imm_op, I32, I32, I32,
13711 /* anonymous_8878MEMORY_COPY_A32_S */
13712 i32imm_op, i32imm_op,
13713 /* anonymous_8878MEMORY_FILL_A32 */
13714 i32imm_op, I32, I32, I32,
13715 /* anonymous_8878MEMORY_FILL_A32_S */
13716 i32imm_op,
13717 /* anonymous_8878MEMORY_INIT_A32 */
13718 i32imm_op, i32imm_op, I32, I32, I32,
13719 /* anonymous_8878MEMORY_INIT_A32_S */
13720 i32imm_op, i32imm_op,
13721 /* anonymous_8879DATA_DROP */
13722 i32imm_op,
13723 /* anonymous_8879DATA_DROP_S */
13724 i32imm_op,
13725 /* anonymous_8879MEMORY_COPY_A64 */
13726 i32imm_op, i32imm_op, I64, I64, I64,
13727 /* anonymous_8879MEMORY_COPY_A64_S */
13728 i32imm_op, i32imm_op,
13729 /* anonymous_8879MEMORY_FILL_A64 */
13730 i32imm_op, I64, I32, I64,
13731 /* anonymous_8879MEMORY_FILL_A64_S */
13732 i32imm_op,
13733 /* anonymous_8879MEMORY_INIT_A64 */
13734 i32imm_op, i32imm_op, I64, I32, I32,
13735 /* anonymous_8879MEMORY_INIT_A64_S */
13736 i32imm_op, i32imm_op,
13737 /* convert_low_s_F64x2 */
13738 V128, V128,
13739 /* convert_low_s_F64x2_S */
13740 /* convert_low_u_F64x2 */
13741 V128, V128,
13742 /* convert_low_u_F64x2_S */
13743 /* demote_zero_F32x4 */
13744 V128, V128,
13745 /* demote_zero_F32x4_S */
13746 /* extend_high_s_I16x8 */
13747 V128, V128,
13748 /* extend_high_s_I16x8_S */
13749 /* extend_high_s_I32x4 */
13750 V128, V128,
13751 /* extend_high_s_I32x4_S */
13752 /* extend_high_s_I64x2 */
13753 V128, V128,
13754 /* extend_high_s_I64x2_S */
13755 /* extend_high_u_I16x8 */
13756 V128, V128,
13757 /* extend_high_u_I16x8_S */
13758 /* extend_high_u_I32x4 */
13759 V128, V128,
13760 /* extend_high_u_I32x4_S */
13761 /* extend_high_u_I64x2 */
13762 V128, V128,
13763 /* extend_high_u_I64x2_S */
13764 /* extend_low_s_I16x8 */
13765 V128, V128,
13766 /* extend_low_s_I16x8_S */
13767 /* extend_low_s_I32x4 */
13768 V128, V128,
13769 /* extend_low_s_I32x4_S */
13770 /* extend_low_s_I64x2 */
13771 V128, V128,
13772 /* extend_low_s_I64x2_S */
13773 /* extend_low_u_I16x8 */
13774 V128, V128,
13775 /* extend_low_u_I16x8_S */
13776 /* extend_low_u_I32x4 */
13777 V128, V128,
13778 /* extend_low_u_I32x4_S */
13779 /* extend_low_u_I64x2 */
13780 V128, V128,
13781 /* extend_low_u_I64x2_S */
13782 /* fp_to_sint_I16x8 */
13783 V128, V128,
13784 /* fp_to_sint_I16x8_S */
13785 /* fp_to_sint_I32x4 */
13786 V128, V128,
13787 /* fp_to_sint_I32x4_S */
13788 /* fp_to_uint_I16x8 */
13789 V128, V128,
13790 /* fp_to_uint_I16x8_S */
13791 /* fp_to_uint_I32x4 */
13792 V128, V128,
13793 /* fp_to_uint_I32x4_S */
13794 /* int_wasm_extadd_pairwise_signed_I16x8 */
13795 V128, V128,
13796 /* int_wasm_extadd_pairwise_signed_I16x8_S */
13797 /* int_wasm_extadd_pairwise_signed_I32x4 */
13798 V128, V128,
13799 /* int_wasm_extadd_pairwise_signed_I32x4_S */
13800 /* int_wasm_extadd_pairwise_unsigned_I16x8 */
13801 V128, V128,
13802 /* int_wasm_extadd_pairwise_unsigned_I16x8_S */
13803 /* int_wasm_extadd_pairwise_unsigned_I32x4 */
13804 V128, V128,
13805 /* int_wasm_extadd_pairwise_unsigned_I32x4_S */
13806 /* int_wasm_relaxed_trunc_signed_I32x4 */
13807 V128, V128,
13808 /* int_wasm_relaxed_trunc_signed_I32x4_S */
13809 /* int_wasm_relaxed_trunc_signed_zero_I32x4 */
13810 V128, V128,
13811 /* int_wasm_relaxed_trunc_signed_zero_I32x4_S */
13812 /* int_wasm_relaxed_trunc_unsigned_I32x4 */
13813 V128, V128,
13814 /* int_wasm_relaxed_trunc_unsigned_I32x4_S */
13815 /* int_wasm_relaxed_trunc_unsigned_zero_I32x4 */
13816 V128, V128,
13817 /* int_wasm_relaxed_trunc_unsigned_zero_I32x4_S */
13818 /* promote_low_F64x2 */
13819 V128, V128,
13820 /* promote_low_F64x2_S */
13821 /* sint_to_fp_F16x8 */
13822 V128, V128,
13823 /* sint_to_fp_F16x8_S */
13824 /* sint_to_fp_F32x4 */
13825 V128, V128,
13826 /* sint_to_fp_F32x4_S */
13827 /* trunc_sat_zero_s_I32x4 */
13828 V128, V128,
13829 /* trunc_sat_zero_s_I32x4_S */
13830 /* trunc_sat_zero_u_I32x4 */
13831 V128, V128,
13832 /* trunc_sat_zero_u_I32x4_S */
13833 /* uint_to_fp_F16x8 */
13834 V128, V128,
13835 /* uint_to_fp_F16x8_S */
13836 /* uint_to_fp_F32x4 */
13837 V128, V128,
13838 };
13839 return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
13840}
13841} // end namespace WebAssembly
13842} // end namespace llvm
13843#endif // GET_INSTRINFO_OPERAND_TYPE
13844
13845#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
13846#undef GET_INSTRINFO_MEM_OPERAND_SIZE
13847namespace llvm {
13848namespace WebAssembly {
13849LLVM_READONLY
13850static int getMemOperandSize(int OpType) {
13851 switch (OpType) {
13852 default: return 0;
13853 }
13854}
13855} // end namespace WebAssembly
13856} // end namespace llvm
13857#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
13858
13859#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
13860#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
13861namespace llvm {
13862namespace WebAssembly {
13863LLVM_READONLY static unsigned
13864getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
13865 return LogicalOpIdx;
13866}
13867LLVM_READONLY static inline unsigned
13868getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
13869 auto S = 0U;
13870 for (auto i = 0U; i < LogicalOpIdx; ++i)
13871 S += getLogicalOperandSize(Opcode, i);
13872 return S;
13873}
13874} // end namespace WebAssembly
13875} // end namespace llvm
13876#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
13877
13878#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
13879#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
13880namespace llvm {
13881namespace WebAssembly {
13882LLVM_READONLY static int
13883getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
13884 return -1;
13885}
13886} // end namespace WebAssembly
13887} // end namespace llvm
13888#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
13889
13890#ifdef GET_INSTRINFO_MC_HELPER_DECLS
13891#undef GET_INSTRINFO_MC_HELPER_DECLS
13892
13893namespace llvm {
13894class MCInst;
13895class FeatureBitset;
13896
13897namespace WebAssembly_MC {
13898
13899void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
13900
13901} // end namespace WebAssembly_MC
13902} // end namespace llvm
13903
13904#endif // GET_INSTRINFO_MC_HELPER_DECLS
13905
13906#ifdef GET_INSTRINFO_MC_HELPERS
13907#undef GET_INSTRINFO_MC_HELPERS
13908
13909namespace llvm {
13910namespace WebAssembly_MC {
13911
13912} // end namespace WebAssembly_MC
13913} // end namespace llvm
13914
13915#endif // GET_GENISTRINFO_MC_HELPERS
13916
13917#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
13918 defined(GET_AVAILABLE_OPCODE_CHECKER)
13919#define GET_COMPUTE_FEATURES
13920#endif
13921#ifdef GET_COMPUTE_FEATURES
13922#undef GET_COMPUTE_FEATURES
13923namespace llvm {
13924namespace WebAssembly_MC {
13925
13926// Bits for subtarget features that participate in instruction matching.
13927enum SubtargetFeatureBits : uint8_t {
13928 Feature_HasAtomicsBit = 0,
13929 Feature_HasBulkMemoryBit = 1,
13930 Feature_HasExceptionHandlingBit = 2,
13931 Feature_HasExtendedConstBit = 3,
13932 Feature_HasHalfPrecisionBit = 4,
13933 Feature_HasMultiMemoryBit = 5,
13934 Feature_HasMultivalueBit = 6,
13935 Feature_HasMutableGlobalsBit = 7,
13936 Feature_HasNontrappingFPToIntBit = 8,
13937 Feature_NotHasNontrappingFPToIntBit = 14,
13938 Feature_HasReferenceTypesBit = 9,
13939 Feature_HasRelaxedSIMDBit = 10,
13940 Feature_HasSignExtBit = 12,
13941 Feature_HasSIMD128Bit = 11,
13942 Feature_HasTailCallBit = 13,
13943};
13944
13945inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
13946 FeatureBitset Features;
13947 if (FB[WebAssembly::FeatureAtomics])
13948 Features.set(Feature_HasAtomicsBit);
13949 if (FB[WebAssembly::FeatureBulkMemory])
13950 Features.set(Feature_HasBulkMemoryBit);
13951 if (FB[WebAssembly::FeatureExceptionHandling])
13952 Features.set(Feature_HasExceptionHandlingBit);
13953 if (FB[WebAssembly::FeatureExtendedConst])
13954 Features.set(Feature_HasExtendedConstBit);
13955 if (FB[WebAssembly::FeatureHalfPrecision])
13956 Features.set(Feature_HasHalfPrecisionBit);
13957 if (FB[WebAssembly::FeatureMultiMemory])
13958 Features.set(Feature_HasMultiMemoryBit);
13959 if (FB[WebAssembly::FeatureMultivalue])
13960 Features.set(Feature_HasMultivalueBit);
13961 if (FB[WebAssembly::FeatureMutableGlobals])
13962 Features.set(Feature_HasMutableGlobalsBit);
13963 if (FB[WebAssembly::FeatureNontrappingFPToInt])
13964 Features.set(Feature_HasNontrappingFPToIntBit);
13965 if (!FB[WebAssembly::FeatureNontrappingFPToInt])
13966 Features.set(Feature_NotHasNontrappingFPToIntBit);
13967 if (FB[WebAssembly::FeatureReferenceTypes])
13968 Features.set(Feature_HasReferenceTypesBit);
13969 if (FB[WebAssembly::FeatureRelaxedSIMD])
13970 Features.set(Feature_HasRelaxedSIMDBit);
13971 if (FB[WebAssembly::FeatureSignExt])
13972 Features.set(Feature_HasSignExtBit);
13973 if (FB[WebAssembly::FeatureSIMD128])
13974 Features.set(Feature_HasSIMD128Bit);
13975 if (FB[WebAssembly::FeatureTailCall])
13976 Features.set(Feature_HasTailCallBit);
13977 return Features;
13978}
13979
13980inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
13981 enum : uint8_t {
13982 CEFBS_None,
13983 CEFBS_HasAtomics,
13984 CEFBS_HasBulkMemory,
13985 CEFBS_HasExceptionHandling,
13986 CEFBS_HasHalfPrecision,
13987 CEFBS_HasNontrappingFPToInt,
13988 CEFBS_HasReferenceTypes,
13989 CEFBS_HasRelaxedSIMD,
13990 CEFBS_HasSIMD128,
13991 CEFBS_HasSignExt,
13992 CEFBS_HasTailCall,
13993 CEFBS_NotHasNontrappingFPToInt,
13994 CEFBS_HasReferenceTypes_HasExceptionHandling,
13995 CEFBS_HasSIMD128_HasHalfPrecision,
13996 CEFBS_HasSIMD128_HasRelaxedSIMD,
13997 };
13998
13999 static constexpr FeatureBitset FeatureBitsets[] = {
14000 {}, // CEFBS_None
14001 {Feature_HasAtomicsBit, },
14002 {Feature_HasBulkMemoryBit, },
14003 {Feature_HasExceptionHandlingBit, },
14004 {Feature_HasHalfPrecisionBit, },
14005 {Feature_HasNontrappingFPToIntBit, },
14006 {Feature_HasReferenceTypesBit, },
14007 {Feature_HasRelaxedSIMDBit, },
14008 {Feature_HasSIMD128Bit, },
14009 {Feature_HasSignExtBit, },
14010 {Feature_HasTailCallBit, },
14011 {Feature_NotHasNontrappingFPToIntBit, },
14012 {Feature_HasReferenceTypesBit, Feature_HasExceptionHandlingBit, },
14013 {Feature_HasSIMD128Bit, Feature_HasHalfPrecisionBit, },
14014 {Feature_HasSIMD128Bit, Feature_HasRelaxedSIMDBit, },
14015 };
14016 static constexpr uint8_t RequiredFeaturesRefs[] = {
14017 CEFBS_None, // PHI = 0
14018 CEFBS_None, // INLINEASM = 1
14019 CEFBS_None, // INLINEASM_BR = 2
14020 CEFBS_None, // CFI_INSTRUCTION = 3
14021 CEFBS_None, // EH_LABEL = 4
14022 CEFBS_None, // GC_LABEL = 5
14023 CEFBS_None, // ANNOTATION_LABEL = 6
14024 CEFBS_None, // KILL = 7
14025 CEFBS_None, // EXTRACT_SUBREG = 8
14026 CEFBS_None, // INSERT_SUBREG = 9
14027 CEFBS_None, // IMPLICIT_DEF = 10
14028 CEFBS_None, // SUBREG_TO_REG = 11
14029 CEFBS_None, // COPY_TO_REGCLASS = 12
14030 CEFBS_None, // DBG_VALUE = 13
14031 CEFBS_None, // DBG_VALUE_LIST = 14
14032 CEFBS_None, // DBG_INSTR_REF = 15
14033 CEFBS_None, // DBG_PHI = 16
14034 CEFBS_None, // DBG_LABEL = 17
14035 CEFBS_None, // REG_SEQUENCE = 18
14036 CEFBS_None, // COPY = 19
14037 CEFBS_None, // BUNDLE = 20
14038 CEFBS_None, // LIFETIME_START = 21
14039 CEFBS_None, // LIFETIME_END = 22
14040 CEFBS_None, // PSEUDO_PROBE = 23
14041 CEFBS_None, // ARITH_FENCE = 24
14042 CEFBS_None, // STACKMAP = 25
14043 CEFBS_None, // FENTRY_CALL = 26
14044 CEFBS_None, // PATCHPOINT = 27
14045 CEFBS_None, // LOAD_STACK_GUARD = 28
14046 CEFBS_None, // PREALLOCATED_SETUP = 29
14047 CEFBS_None, // PREALLOCATED_ARG = 30
14048 CEFBS_None, // STATEPOINT = 31
14049 CEFBS_None, // LOCAL_ESCAPE = 32
14050 CEFBS_None, // FAULTING_OP = 33
14051 CEFBS_None, // PATCHABLE_OP = 34
14052 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
14053 CEFBS_None, // PATCHABLE_RET = 36
14054 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
14055 CEFBS_None, // PATCHABLE_TAIL_CALL = 38
14056 CEFBS_None, // PATCHABLE_EVENT_CALL = 39
14057 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
14058 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
14059 CEFBS_None, // MEMBARRIER = 42
14060 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
14061 CEFBS_None, // CONVERGENCECTRL_ENTRY = 44
14062 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 45
14063 CEFBS_None, // CONVERGENCECTRL_LOOP = 46
14064 CEFBS_None, // CONVERGENCECTRL_GLUE = 47
14065 CEFBS_None, // G_ASSERT_SEXT = 48
14066 CEFBS_None, // G_ASSERT_ZEXT = 49
14067 CEFBS_None, // G_ASSERT_ALIGN = 50
14068 CEFBS_None, // G_ADD = 51
14069 CEFBS_None, // G_SUB = 52
14070 CEFBS_None, // G_MUL = 53
14071 CEFBS_None, // G_SDIV = 54
14072 CEFBS_None, // G_UDIV = 55
14073 CEFBS_None, // G_SREM = 56
14074 CEFBS_None, // G_UREM = 57
14075 CEFBS_None, // G_SDIVREM = 58
14076 CEFBS_None, // G_UDIVREM = 59
14077 CEFBS_None, // G_AND = 60
14078 CEFBS_None, // G_OR = 61
14079 CEFBS_None, // G_XOR = 62
14080 CEFBS_None, // G_IMPLICIT_DEF = 63
14081 CEFBS_None, // G_PHI = 64
14082 CEFBS_None, // G_FRAME_INDEX = 65
14083 CEFBS_None, // G_GLOBAL_VALUE = 66
14084 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 67
14085 CEFBS_None, // G_CONSTANT_POOL = 68
14086 CEFBS_None, // G_EXTRACT = 69
14087 CEFBS_None, // G_UNMERGE_VALUES = 70
14088 CEFBS_None, // G_INSERT = 71
14089 CEFBS_None, // G_MERGE_VALUES = 72
14090 CEFBS_None, // G_BUILD_VECTOR = 73
14091 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 74
14092 CEFBS_None, // G_CONCAT_VECTORS = 75
14093 CEFBS_None, // G_PTRTOINT = 76
14094 CEFBS_None, // G_INTTOPTR = 77
14095 CEFBS_None, // G_BITCAST = 78
14096 CEFBS_None, // G_FREEZE = 79
14097 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 80
14098 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 81
14099 CEFBS_None, // G_INTRINSIC_TRUNC = 82
14100 CEFBS_None, // G_INTRINSIC_ROUND = 83
14101 CEFBS_None, // G_INTRINSIC_LRINT = 84
14102 CEFBS_None, // G_INTRINSIC_LLRINT = 85
14103 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 86
14104 CEFBS_None, // G_READCYCLECOUNTER = 87
14105 CEFBS_None, // G_READSTEADYCOUNTER = 88
14106 CEFBS_None, // G_LOAD = 89
14107 CEFBS_None, // G_SEXTLOAD = 90
14108 CEFBS_None, // G_ZEXTLOAD = 91
14109 CEFBS_None, // G_INDEXED_LOAD = 92
14110 CEFBS_None, // G_INDEXED_SEXTLOAD = 93
14111 CEFBS_None, // G_INDEXED_ZEXTLOAD = 94
14112 CEFBS_None, // G_STORE = 95
14113 CEFBS_None, // G_INDEXED_STORE = 96
14114 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97
14115 CEFBS_None, // G_ATOMIC_CMPXCHG = 98
14116 CEFBS_None, // G_ATOMICRMW_XCHG = 99
14117 CEFBS_None, // G_ATOMICRMW_ADD = 100
14118 CEFBS_None, // G_ATOMICRMW_SUB = 101
14119 CEFBS_None, // G_ATOMICRMW_AND = 102
14120 CEFBS_None, // G_ATOMICRMW_NAND = 103
14121 CEFBS_None, // G_ATOMICRMW_OR = 104
14122 CEFBS_None, // G_ATOMICRMW_XOR = 105
14123 CEFBS_None, // G_ATOMICRMW_MAX = 106
14124 CEFBS_None, // G_ATOMICRMW_MIN = 107
14125 CEFBS_None, // G_ATOMICRMW_UMAX = 108
14126 CEFBS_None, // G_ATOMICRMW_UMIN = 109
14127 CEFBS_None, // G_ATOMICRMW_FADD = 110
14128 CEFBS_None, // G_ATOMICRMW_FSUB = 111
14129 CEFBS_None, // G_ATOMICRMW_FMAX = 112
14130 CEFBS_None, // G_ATOMICRMW_FMIN = 113
14131 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 114
14132 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 115
14133 CEFBS_None, // G_FENCE = 116
14134 CEFBS_None, // G_PREFETCH = 117
14135 CEFBS_None, // G_BRCOND = 118
14136 CEFBS_None, // G_BRINDIRECT = 119
14137 CEFBS_None, // G_INVOKE_REGION_START = 120
14138 CEFBS_None, // G_INTRINSIC = 121
14139 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 122
14140 CEFBS_None, // G_INTRINSIC_CONVERGENT = 123
14141 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124
14142 CEFBS_None, // G_ANYEXT = 125
14143 CEFBS_None, // G_TRUNC = 126
14144 CEFBS_None, // G_CONSTANT = 127
14145 CEFBS_None, // G_FCONSTANT = 128
14146 CEFBS_None, // G_VASTART = 129
14147 CEFBS_None, // G_VAARG = 130
14148 CEFBS_None, // G_SEXT = 131
14149 CEFBS_None, // G_SEXT_INREG = 132
14150 CEFBS_None, // G_ZEXT = 133
14151 CEFBS_None, // G_SHL = 134
14152 CEFBS_None, // G_LSHR = 135
14153 CEFBS_None, // G_ASHR = 136
14154 CEFBS_None, // G_FSHL = 137
14155 CEFBS_None, // G_FSHR = 138
14156 CEFBS_None, // G_ROTR = 139
14157 CEFBS_None, // G_ROTL = 140
14158 CEFBS_None, // G_ICMP = 141
14159 CEFBS_None, // G_FCMP = 142
14160 CEFBS_None, // G_SCMP = 143
14161 CEFBS_None, // G_UCMP = 144
14162 CEFBS_None, // G_SELECT = 145
14163 CEFBS_None, // G_UADDO = 146
14164 CEFBS_None, // G_UADDE = 147
14165 CEFBS_None, // G_USUBO = 148
14166 CEFBS_None, // G_USUBE = 149
14167 CEFBS_None, // G_SADDO = 150
14168 CEFBS_None, // G_SADDE = 151
14169 CEFBS_None, // G_SSUBO = 152
14170 CEFBS_None, // G_SSUBE = 153
14171 CEFBS_None, // G_UMULO = 154
14172 CEFBS_None, // G_SMULO = 155
14173 CEFBS_None, // G_UMULH = 156
14174 CEFBS_None, // G_SMULH = 157
14175 CEFBS_None, // G_UADDSAT = 158
14176 CEFBS_None, // G_SADDSAT = 159
14177 CEFBS_None, // G_USUBSAT = 160
14178 CEFBS_None, // G_SSUBSAT = 161
14179 CEFBS_None, // G_USHLSAT = 162
14180 CEFBS_None, // G_SSHLSAT = 163
14181 CEFBS_None, // G_SMULFIX = 164
14182 CEFBS_None, // G_UMULFIX = 165
14183 CEFBS_None, // G_SMULFIXSAT = 166
14184 CEFBS_None, // G_UMULFIXSAT = 167
14185 CEFBS_None, // G_SDIVFIX = 168
14186 CEFBS_None, // G_UDIVFIX = 169
14187 CEFBS_None, // G_SDIVFIXSAT = 170
14188 CEFBS_None, // G_UDIVFIXSAT = 171
14189 CEFBS_None, // G_FADD = 172
14190 CEFBS_None, // G_FSUB = 173
14191 CEFBS_None, // G_FMUL = 174
14192 CEFBS_None, // G_FMA = 175
14193 CEFBS_None, // G_FMAD = 176
14194 CEFBS_None, // G_FDIV = 177
14195 CEFBS_None, // G_FREM = 178
14196 CEFBS_None, // G_FPOW = 179
14197 CEFBS_None, // G_FPOWI = 180
14198 CEFBS_None, // G_FEXP = 181
14199 CEFBS_None, // G_FEXP2 = 182
14200 CEFBS_None, // G_FEXP10 = 183
14201 CEFBS_None, // G_FLOG = 184
14202 CEFBS_None, // G_FLOG2 = 185
14203 CEFBS_None, // G_FLOG10 = 186
14204 CEFBS_None, // G_FLDEXP = 187
14205 CEFBS_None, // G_FFREXP = 188
14206 CEFBS_None, // G_FNEG = 189
14207 CEFBS_None, // G_FPEXT = 190
14208 CEFBS_None, // G_FPTRUNC = 191
14209 CEFBS_None, // G_FPTOSI = 192
14210 CEFBS_None, // G_FPTOUI = 193
14211 CEFBS_None, // G_SITOFP = 194
14212 CEFBS_None, // G_UITOFP = 195
14213 CEFBS_None, // G_FABS = 196
14214 CEFBS_None, // G_FCOPYSIGN = 197
14215 CEFBS_None, // G_IS_FPCLASS = 198
14216 CEFBS_None, // G_FCANONICALIZE = 199
14217 CEFBS_None, // G_FMINNUM = 200
14218 CEFBS_None, // G_FMAXNUM = 201
14219 CEFBS_None, // G_FMINNUM_IEEE = 202
14220 CEFBS_None, // G_FMAXNUM_IEEE = 203
14221 CEFBS_None, // G_FMINIMUM = 204
14222 CEFBS_None, // G_FMAXIMUM = 205
14223 CEFBS_None, // G_GET_FPENV = 206
14224 CEFBS_None, // G_SET_FPENV = 207
14225 CEFBS_None, // G_RESET_FPENV = 208
14226 CEFBS_None, // G_GET_FPMODE = 209
14227 CEFBS_None, // G_SET_FPMODE = 210
14228 CEFBS_None, // G_RESET_FPMODE = 211
14229 CEFBS_None, // G_PTR_ADD = 212
14230 CEFBS_None, // G_PTRMASK = 213
14231 CEFBS_None, // G_SMIN = 214
14232 CEFBS_None, // G_SMAX = 215
14233 CEFBS_None, // G_UMIN = 216
14234 CEFBS_None, // G_UMAX = 217
14235 CEFBS_None, // G_ABS = 218
14236 CEFBS_None, // G_LROUND = 219
14237 CEFBS_None, // G_LLROUND = 220
14238 CEFBS_None, // G_BR = 221
14239 CEFBS_None, // G_BRJT = 222
14240 CEFBS_None, // G_VSCALE = 223
14241 CEFBS_None, // G_INSERT_SUBVECTOR = 224
14242 CEFBS_None, // G_EXTRACT_SUBVECTOR = 225
14243 CEFBS_None, // G_INSERT_VECTOR_ELT = 226
14244 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 227
14245 CEFBS_None, // G_SHUFFLE_VECTOR = 228
14246 CEFBS_None, // G_SPLAT_VECTOR = 229
14247 CEFBS_None, // G_VECTOR_COMPRESS = 230
14248 CEFBS_None, // G_CTTZ = 231
14249 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 232
14250 CEFBS_None, // G_CTLZ = 233
14251 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 234
14252 CEFBS_None, // G_CTPOP = 235
14253 CEFBS_None, // G_BSWAP = 236
14254 CEFBS_None, // G_BITREVERSE = 237
14255 CEFBS_None, // G_FCEIL = 238
14256 CEFBS_None, // G_FCOS = 239
14257 CEFBS_None, // G_FSIN = 240
14258 CEFBS_None, // G_FTAN = 241
14259 CEFBS_None, // G_FACOS = 242
14260 CEFBS_None, // G_FASIN = 243
14261 CEFBS_None, // G_FATAN = 244
14262 CEFBS_None, // G_FCOSH = 245
14263 CEFBS_None, // G_FSINH = 246
14264 CEFBS_None, // G_FTANH = 247
14265 CEFBS_None, // G_FSQRT = 248
14266 CEFBS_None, // G_FFLOOR = 249
14267 CEFBS_None, // G_FRINT = 250
14268 CEFBS_None, // G_FNEARBYINT = 251
14269 CEFBS_None, // G_ADDRSPACE_CAST = 252
14270 CEFBS_None, // G_BLOCK_ADDR = 253
14271 CEFBS_None, // G_JUMP_TABLE = 254
14272 CEFBS_None, // G_DYN_STACKALLOC = 255
14273 CEFBS_None, // G_STACKSAVE = 256
14274 CEFBS_None, // G_STACKRESTORE = 257
14275 CEFBS_None, // G_STRICT_FADD = 258
14276 CEFBS_None, // G_STRICT_FSUB = 259
14277 CEFBS_None, // G_STRICT_FMUL = 260
14278 CEFBS_None, // G_STRICT_FDIV = 261
14279 CEFBS_None, // G_STRICT_FREM = 262
14280 CEFBS_None, // G_STRICT_FMA = 263
14281 CEFBS_None, // G_STRICT_FSQRT = 264
14282 CEFBS_None, // G_STRICT_FLDEXP = 265
14283 CEFBS_None, // G_READ_REGISTER = 266
14284 CEFBS_None, // G_WRITE_REGISTER = 267
14285 CEFBS_None, // G_MEMCPY = 268
14286 CEFBS_None, // G_MEMCPY_INLINE = 269
14287 CEFBS_None, // G_MEMMOVE = 270
14288 CEFBS_None, // G_MEMSET = 271
14289 CEFBS_None, // G_BZERO = 272
14290 CEFBS_None, // G_TRAP = 273
14291 CEFBS_None, // G_DEBUGTRAP = 274
14292 CEFBS_None, // G_UBSANTRAP = 275
14293 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 276
14294 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 277
14295 CEFBS_None, // G_VECREDUCE_FADD = 278
14296 CEFBS_None, // G_VECREDUCE_FMUL = 279
14297 CEFBS_None, // G_VECREDUCE_FMAX = 280
14298 CEFBS_None, // G_VECREDUCE_FMIN = 281
14299 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 282
14300 CEFBS_None, // G_VECREDUCE_FMINIMUM = 283
14301 CEFBS_None, // G_VECREDUCE_ADD = 284
14302 CEFBS_None, // G_VECREDUCE_MUL = 285
14303 CEFBS_None, // G_VECREDUCE_AND = 286
14304 CEFBS_None, // G_VECREDUCE_OR = 287
14305 CEFBS_None, // G_VECREDUCE_XOR = 288
14306 CEFBS_None, // G_VECREDUCE_SMAX = 289
14307 CEFBS_None, // G_VECREDUCE_SMIN = 290
14308 CEFBS_None, // G_VECREDUCE_UMAX = 291
14309 CEFBS_None, // G_VECREDUCE_UMIN = 292
14310 CEFBS_None, // G_SBFX = 293
14311 CEFBS_None, // G_UBFX = 294
14312 CEFBS_None, // CALL_PARAMS = 295
14313 CEFBS_None, // CALL_PARAMS_S = 296
14314 CEFBS_None, // CALL_RESULTS = 297
14315 CEFBS_None, // CALL_RESULTS_S = 298
14316 CEFBS_HasExceptionHandling, // CATCHRET = 299
14317 CEFBS_HasExceptionHandling, // CATCHRET_S = 300
14318 CEFBS_HasExceptionHandling, // CLEANUPRET = 301
14319 CEFBS_HasExceptionHandling, // CLEANUPRET_S = 302
14320 CEFBS_HasAtomics, // COMPILER_FENCE = 303
14321 CEFBS_HasAtomics, // COMPILER_FENCE_S = 304
14322 CEFBS_None, // RET_CALL_RESULTS = 305
14323 CEFBS_None, // RET_CALL_RESULTS_S = 306
14324 CEFBS_HasSIMD128_HasHalfPrecision, // ABS_F16x8 = 307
14325 CEFBS_HasSIMD128_HasHalfPrecision, // ABS_F16x8_S = 308
14326 CEFBS_None, // ABS_F32 = 309
14327 CEFBS_None, // ABS_F32_S = 310
14328 CEFBS_HasSIMD128, // ABS_F32x4 = 311
14329 CEFBS_HasSIMD128, // ABS_F32x4_S = 312
14330 CEFBS_None, // ABS_F64 = 313
14331 CEFBS_None, // ABS_F64_S = 314
14332 CEFBS_HasSIMD128, // ABS_F64x2 = 315
14333 CEFBS_HasSIMD128, // ABS_F64x2_S = 316
14334 CEFBS_HasSIMD128, // ABS_I16x8 = 317
14335 CEFBS_HasSIMD128, // ABS_I16x8_S = 318
14336 CEFBS_HasSIMD128, // ABS_I32x4 = 319
14337 CEFBS_HasSIMD128, // ABS_I32x4_S = 320
14338 CEFBS_HasSIMD128, // ABS_I64x2 = 321
14339 CEFBS_HasSIMD128, // ABS_I64x2_S = 322
14340 CEFBS_HasSIMD128, // ABS_I8x16 = 323
14341 CEFBS_HasSIMD128, // ABS_I8x16_S = 324
14342 CEFBS_HasSIMD128_HasHalfPrecision, // ADD_F16x8 = 325
14343 CEFBS_HasSIMD128_HasHalfPrecision, // ADD_F16x8_S = 326
14344 CEFBS_None, // ADD_F32 = 327
14345 CEFBS_None, // ADD_F32_S = 328
14346 CEFBS_HasSIMD128, // ADD_F32x4 = 329
14347 CEFBS_HasSIMD128, // ADD_F32x4_S = 330
14348 CEFBS_None, // ADD_F64 = 331
14349 CEFBS_None, // ADD_F64_S = 332
14350 CEFBS_HasSIMD128, // ADD_F64x2 = 333
14351 CEFBS_HasSIMD128, // ADD_F64x2_S = 334
14352 CEFBS_HasSIMD128, // ADD_I16x8 = 335
14353 CEFBS_HasSIMD128, // ADD_I16x8_S = 336
14354 CEFBS_None, // ADD_I32 = 337
14355 CEFBS_None, // ADD_I32_S = 338
14356 CEFBS_HasSIMD128, // ADD_I32x4 = 339
14357 CEFBS_HasSIMD128, // ADD_I32x4_S = 340
14358 CEFBS_None, // ADD_I64 = 341
14359 CEFBS_None, // ADD_I64_S = 342
14360 CEFBS_HasSIMD128, // ADD_I64x2 = 343
14361 CEFBS_HasSIMD128, // ADD_I64x2_S = 344
14362 CEFBS_HasSIMD128, // ADD_I8x16 = 345
14363 CEFBS_HasSIMD128, // ADD_I8x16_S = 346
14364 CEFBS_HasSIMD128, // ADD_SAT_S_I16x8 = 347
14365 CEFBS_HasSIMD128, // ADD_SAT_S_I16x8_S = 348
14366 CEFBS_HasSIMD128, // ADD_SAT_S_I8x16 = 349
14367 CEFBS_HasSIMD128, // ADD_SAT_S_I8x16_S = 350
14368 CEFBS_HasSIMD128, // ADD_SAT_U_I16x8 = 351
14369 CEFBS_HasSIMD128, // ADD_SAT_U_I16x8_S = 352
14370 CEFBS_HasSIMD128, // ADD_SAT_U_I8x16 = 353
14371 CEFBS_HasSIMD128, // ADD_SAT_U_I8x16_S = 354
14372 CEFBS_None, // ADJCALLSTACKDOWN = 355
14373 CEFBS_None, // ADJCALLSTACKDOWN_S = 356
14374 CEFBS_None, // ADJCALLSTACKUP = 357
14375 CEFBS_None, // ADJCALLSTACKUP_S = 358
14376 CEFBS_HasSIMD128, // ALLTRUE_I16x8 = 359
14377 CEFBS_HasSIMD128, // ALLTRUE_I16x8_S = 360
14378 CEFBS_HasSIMD128, // ALLTRUE_I32x4 = 361
14379 CEFBS_HasSIMD128, // ALLTRUE_I32x4_S = 362
14380 CEFBS_HasSIMD128, // ALLTRUE_I64x2 = 363
14381 CEFBS_HasSIMD128, // ALLTRUE_I64x2_S = 364
14382 CEFBS_HasSIMD128, // ALLTRUE_I8x16 = 365
14383 CEFBS_HasSIMD128, // ALLTRUE_I8x16_S = 366
14384 CEFBS_HasSIMD128, // AND = 367
14385 CEFBS_HasSIMD128, // ANDNOT = 368
14386 CEFBS_HasSIMD128, // ANDNOT_S = 369
14387 CEFBS_None, // AND_I32 = 370
14388 CEFBS_None, // AND_I32_S = 371
14389 CEFBS_None, // AND_I64 = 372
14390 CEFBS_None, // AND_I64_S = 373
14391 CEFBS_HasSIMD128, // AND_S = 374
14392 CEFBS_HasSIMD128, // ANYTRUE = 375
14393 CEFBS_HasSIMD128, // ANYTRUE_S = 376
14394 CEFBS_None, // ARGUMENT_exnref = 377
14395 CEFBS_None, // ARGUMENT_exnref_S = 378
14396 CEFBS_None, // ARGUMENT_externref = 379
14397 CEFBS_None, // ARGUMENT_externref_S = 380
14398 CEFBS_None, // ARGUMENT_f32 = 381
14399 CEFBS_None, // ARGUMENT_f32_S = 382
14400 CEFBS_None, // ARGUMENT_f64 = 383
14401 CEFBS_None, // ARGUMENT_f64_S = 384
14402 CEFBS_None, // ARGUMENT_funcref = 385
14403 CEFBS_None, // ARGUMENT_funcref_S = 386
14404 CEFBS_None, // ARGUMENT_i32 = 387
14405 CEFBS_None, // ARGUMENT_i32_S = 388
14406 CEFBS_None, // ARGUMENT_i64 = 389
14407 CEFBS_None, // ARGUMENT_i64_S = 390
14408 CEFBS_None, // ARGUMENT_v16i8 = 391
14409 CEFBS_None, // ARGUMENT_v16i8_S = 392
14410 CEFBS_None, // ARGUMENT_v2f64 = 393
14411 CEFBS_None, // ARGUMENT_v2f64_S = 394
14412 CEFBS_None, // ARGUMENT_v2i64 = 395
14413 CEFBS_None, // ARGUMENT_v2i64_S = 396
14414 CEFBS_None, // ARGUMENT_v4f32 = 397
14415 CEFBS_None, // ARGUMENT_v4f32_S = 398
14416 CEFBS_None, // ARGUMENT_v4i32 = 399
14417 CEFBS_None, // ARGUMENT_v4i32_S = 400
14418 CEFBS_None, // ARGUMENT_v8f16 = 401
14419 CEFBS_None, // ARGUMENT_v8f16_S = 402
14420 CEFBS_None, // ARGUMENT_v8i16 = 403
14421 CEFBS_None, // ARGUMENT_v8i16_S = 404
14422 CEFBS_HasAtomics, // ATOMIC_FENCE = 405
14423 CEFBS_HasAtomics, // ATOMIC_FENCE_S = 406
14424 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32 = 407
14425 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A32_S = 408
14426 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64 = 409
14427 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I32_A64_S = 410
14428 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32 = 411
14429 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A32_S = 412
14430 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64 = 413
14431 CEFBS_HasAtomics, // ATOMIC_LOAD16_U_I64_A64_S = 414
14432 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32 = 415
14433 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A32_S = 416
14434 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64 = 417
14435 CEFBS_HasAtomics, // ATOMIC_LOAD32_U_I64_A64_S = 418
14436 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32 = 419
14437 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A32_S = 420
14438 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64 = 421
14439 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I32_A64_S = 422
14440 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32 = 423
14441 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A32_S = 424
14442 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64 = 425
14443 CEFBS_HasAtomics, // ATOMIC_LOAD8_U_I64_A64_S = 426
14444 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32 = 427
14445 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A32_S = 428
14446 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64 = 429
14447 CEFBS_HasAtomics, // ATOMIC_LOAD_I32_A64_S = 430
14448 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32 = 431
14449 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A32_S = 432
14450 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64 = 433
14451 CEFBS_HasAtomics, // ATOMIC_LOAD_I64_A64_S = 434
14452 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32 = 435
14453 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A32_S = 436
14454 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64 = 437
14455 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I32_A64_S = 438
14456 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32 = 439
14457 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A32_S = 440
14458 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64 = 441
14459 CEFBS_HasAtomics, // ATOMIC_RMW16_U_ADD_I64_A64_S = 442
14460 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32 = 443
14461 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A32_S = 444
14462 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64 = 445
14463 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I32_A64_S = 446
14464 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32 = 447
14465 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A32_S = 448
14466 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64 = 449
14467 CEFBS_HasAtomics, // ATOMIC_RMW16_U_AND_I64_A64_S = 450
14468 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32 = 451
14469 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A32_S = 452
14470 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64 = 453
14471 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I32_A64_S = 454
14472 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32 = 455
14473 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A32_S = 456
14474 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64 = 457
14475 CEFBS_HasAtomics, // ATOMIC_RMW16_U_CMPXCHG_I64_A64_S = 458
14476 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32 = 459
14477 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A32_S = 460
14478 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64 = 461
14479 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I32_A64_S = 462
14480 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32 = 463
14481 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A32_S = 464
14482 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64 = 465
14483 CEFBS_HasAtomics, // ATOMIC_RMW16_U_OR_I64_A64_S = 466
14484 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32 = 467
14485 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A32_S = 468
14486 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64 = 469
14487 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I32_A64_S = 470
14488 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32 = 471
14489 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A32_S = 472
14490 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64 = 473
14491 CEFBS_HasAtomics, // ATOMIC_RMW16_U_SUB_I64_A64_S = 474
14492 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32 = 475
14493 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A32_S = 476
14494 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64 = 477
14495 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I32_A64_S = 478
14496 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32 = 479
14497 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A32_S = 480
14498 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64 = 481
14499 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XCHG_I64_A64_S = 482
14500 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32 = 483
14501 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A32_S = 484
14502 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64 = 485
14503 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I32_A64_S = 486
14504 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32 = 487
14505 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A32_S = 488
14506 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64 = 489
14507 CEFBS_HasAtomics, // ATOMIC_RMW16_U_XOR_I64_A64_S = 490
14508 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32 = 491
14509 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A32_S = 492
14510 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64 = 493
14511 CEFBS_HasAtomics, // ATOMIC_RMW32_U_ADD_I64_A64_S = 494
14512 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32 = 495
14513 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A32_S = 496
14514 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64 = 497
14515 CEFBS_HasAtomics, // ATOMIC_RMW32_U_AND_I64_A64_S = 498
14516 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32 = 499
14517 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A32_S = 500
14518 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64 = 501
14519 CEFBS_HasAtomics, // ATOMIC_RMW32_U_CMPXCHG_I64_A64_S = 502
14520 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32 = 503
14521 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A32_S = 504
14522 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64 = 505
14523 CEFBS_HasAtomics, // ATOMIC_RMW32_U_OR_I64_A64_S = 506
14524 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32 = 507
14525 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A32_S = 508
14526 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64 = 509
14527 CEFBS_HasAtomics, // ATOMIC_RMW32_U_SUB_I64_A64_S = 510
14528 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32 = 511
14529 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A32_S = 512
14530 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64 = 513
14531 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XCHG_I64_A64_S = 514
14532 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32 = 515
14533 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A32_S = 516
14534 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64 = 517
14535 CEFBS_HasAtomics, // ATOMIC_RMW32_U_XOR_I64_A64_S = 518
14536 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32 = 519
14537 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A32_S = 520
14538 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64 = 521
14539 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I32_A64_S = 522
14540 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32 = 523
14541 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A32_S = 524
14542 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64 = 525
14543 CEFBS_HasAtomics, // ATOMIC_RMW8_U_ADD_I64_A64_S = 526
14544 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32 = 527
14545 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A32_S = 528
14546 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64 = 529
14547 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I32_A64_S = 530
14548 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32 = 531
14549 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A32_S = 532
14550 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64 = 533
14551 CEFBS_HasAtomics, // ATOMIC_RMW8_U_AND_I64_A64_S = 534
14552 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32 = 535
14553 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A32_S = 536
14554 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64 = 537
14555 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I32_A64_S = 538
14556 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32 = 539
14557 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A32_S = 540
14558 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64 = 541
14559 CEFBS_HasAtomics, // ATOMIC_RMW8_U_CMPXCHG_I64_A64_S = 542
14560 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32 = 543
14561 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A32_S = 544
14562 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64 = 545
14563 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I32_A64_S = 546
14564 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32 = 547
14565 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A32_S = 548
14566 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64 = 549
14567 CEFBS_HasAtomics, // ATOMIC_RMW8_U_OR_I64_A64_S = 550
14568 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32 = 551
14569 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A32_S = 552
14570 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64 = 553
14571 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I32_A64_S = 554
14572 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32 = 555
14573 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A32_S = 556
14574 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64 = 557
14575 CEFBS_HasAtomics, // ATOMIC_RMW8_U_SUB_I64_A64_S = 558
14576 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32 = 559
14577 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A32_S = 560
14578 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64 = 561
14579 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I32_A64_S = 562
14580 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32 = 563
14581 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A32_S = 564
14582 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64 = 565
14583 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XCHG_I64_A64_S = 566
14584 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32 = 567
14585 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A32_S = 568
14586 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64 = 569
14587 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I32_A64_S = 570
14588 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32 = 571
14589 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A32_S = 572
14590 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64 = 573
14591 CEFBS_HasAtomics, // ATOMIC_RMW8_U_XOR_I64_A64_S = 574
14592 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32 = 575
14593 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A32_S = 576
14594 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64 = 577
14595 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I32_A64_S = 578
14596 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32 = 579
14597 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A32_S = 580
14598 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64 = 581
14599 CEFBS_HasAtomics, // ATOMIC_RMW_ADD_I64_A64_S = 582
14600 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32 = 583
14601 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A32_S = 584
14602 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64 = 585
14603 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I32_A64_S = 586
14604 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32 = 587
14605 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A32_S = 588
14606 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64 = 589
14607 CEFBS_HasAtomics, // ATOMIC_RMW_AND_I64_A64_S = 590
14608 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32 = 591
14609 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A32_S = 592
14610 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64 = 593
14611 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I32_A64_S = 594
14612 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32 = 595
14613 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A32_S = 596
14614 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64 = 597
14615 CEFBS_HasAtomics, // ATOMIC_RMW_CMPXCHG_I64_A64_S = 598
14616 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32 = 599
14617 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A32_S = 600
14618 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64 = 601
14619 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I32_A64_S = 602
14620 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32 = 603
14621 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A32_S = 604
14622 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64 = 605
14623 CEFBS_HasAtomics, // ATOMIC_RMW_OR_I64_A64_S = 606
14624 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32 = 607
14625 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A32_S = 608
14626 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64 = 609
14627 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I32_A64_S = 610
14628 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32 = 611
14629 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A32_S = 612
14630 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64 = 613
14631 CEFBS_HasAtomics, // ATOMIC_RMW_SUB_I64_A64_S = 614
14632 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32 = 615
14633 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A32_S = 616
14634 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64 = 617
14635 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I32_A64_S = 618
14636 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32 = 619
14637 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A32_S = 620
14638 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64 = 621
14639 CEFBS_HasAtomics, // ATOMIC_RMW_XCHG_I64_A64_S = 622
14640 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32 = 623
14641 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A32_S = 624
14642 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64 = 625
14643 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I32_A64_S = 626
14644 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32 = 627
14645 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A32_S = 628
14646 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64 = 629
14647 CEFBS_HasAtomics, // ATOMIC_RMW_XOR_I64_A64_S = 630
14648 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32 = 631
14649 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A32_S = 632
14650 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64 = 633
14651 CEFBS_HasAtomics, // ATOMIC_STORE16_I32_A64_S = 634
14652 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32 = 635
14653 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A32_S = 636
14654 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64 = 637
14655 CEFBS_HasAtomics, // ATOMIC_STORE16_I64_A64_S = 638
14656 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32 = 639
14657 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A32_S = 640
14658 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64 = 641
14659 CEFBS_HasAtomics, // ATOMIC_STORE32_I64_A64_S = 642
14660 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32 = 643
14661 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A32_S = 644
14662 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64 = 645
14663 CEFBS_HasAtomics, // ATOMIC_STORE8_I32_A64_S = 646
14664 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32 = 647
14665 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A32_S = 648
14666 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64 = 649
14667 CEFBS_HasAtomics, // ATOMIC_STORE8_I64_A64_S = 650
14668 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32 = 651
14669 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A32_S = 652
14670 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64 = 653
14671 CEFBS_HasAtomics, // ATOMIC_STORE_I32_A64_S = 654
14672 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32 = 655
14673 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A32_S = 656
14674 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64 = 657
14675 CEFBS_HasAtomics, // ATOMIC_STORE_I64_A64_S = 658
14676 CEFBS_HasSIMD128, // AVGR_U_I16x8 = 659
14677 CEFBS_HasSIMD128, // AVGR_U_I16x8_S = 660
14678 CEFBS_HasSIMD128, // AVGR_U_I8x16 = 661
14679 CEFBS_HasSIMD128, // AVGR_U_I8x16_S = 662
14680 CEFBS_HasSIMD128, // BITMASK_I16x8 = 663
14681 CEFBS_HasSIMD128, // BITMASK_I16x8_S = 664
14682 CEFBS_HasSIMD128, // BITMASK_I32x4 = 665
14683 CEFBS_HasSIMD128, // BITMASK_I32x4_S = 666
14684 CEFBS_HasSIMD128, // BITMASK_I64x2 = 667
14685 CEFBS_HasSIMD128, // BITMASK_I64x2_S = 668
14686 CEFBS_HasSIMD128, // BITMASK_I8x16 = 669
14687 CEFBS_HasSIMD128, // BITMASK_I8x16_S = 670
14688 CEFBS_HasSIMD128, // BITSELECT = 671
14689 CEFBS_HasSIMD128, // BITSELECT_S = 672
14690 CEFBS_None, // BLOCK = 673
14691 CEFBS_None, // BLOCK_S = 674
14692 CEFBS_None, // BR = 675
14693 CEFBS_None, // BR_IF = 676
14694 CEFBS_None, // BR_IF_S = 677
14695 CEFBS_None, // BR_S = 678
14696 CEFBS_None, // BR_TABLE_I32 = 679
14697 CEFBS_None, // BR_TABLE_I32_S = 680
14698 CEFBS_None, // BR_TABLE_I64 = 681
14699 CEFBS_None, // BR_TABLE_I64_S = 682
14700 CEFBS_None, // BR_UNLESS = 683
14701 CEFBS_None, // BR_UNLESS_S = 684
14702 CEFBS_None, // CALL = 685
14703 CEFBS_None, // CALL_INDIRECT = 686
14704 CEFBS_None, // CALL_INDIRECT_S = 687
14705 CEFBS_None, // CALL_S = 688
14706 CEFBS_HasExceptionHandling, // CATCH = 689
14707 CEFBS_HasExceptionHandling, // CATCH_ALL = 690
14708 CEFBS_HasExceptionHandling, // CATCH_ALL_S = 691
14709 CEFBS_HasExceptionHandling, // CATCH_S = 692
14710 CEFBS_HasSIMD128_HasHalfPrecision, // CEIL_F16x8 = 693
14711 CEFBS_HasSIMD128_HasHalfPrecision, // CEIL_F16x8_S = 694
14712 CEFBS_None, // CEIL_F32 = 695
14713 CEFBS_None, // CEIL_F32_S = 696
14714 CEFBS_HasSIMD128, // CEIL_F32x4 = 697
14715 CEFBS_HasSIMD128, // CEIL_F32x4_S = 698
14716 CEFBS_None, // CEIL_F64 = 699
14717 CEFBS_None, // CEIL_F64_S = 700
14718 CEFBS_HasSIMD128, // CEIL_F64x2 = 701
14719 CEFBS_HasSIMD128, // CEIL_F64x2_S = 702
14720 CEFBS_None, // CLZ_I32 = 703
14721 CEFBS_None, // CLZ_I32_S = 704
14722 CEFBS_None, // CLZ_I64 = 705
14723 CEFBS_None, // CLZ_I64_S = 706
14724 CEFBS_None, // CONST_F32 = 707
14725 CEFBS_None, // CONST_F32_S = 708
14726 CEFBS_None, // CONST_F64 = 709
14727 CEFBS_None, // CONST_F64_S = 710
14728 CEFBS_None, // CONST_I32 = 711
14729 CEFBS_None, // CONST_I32_S = 712
14730 CEFBS_None, // CONST_I64 = 713
14731 CEFBS_None, // CONST_I64_S = 714
14732 CEFBS_HasSIMD128, // CONST_V128_F32x4 = 715
14733 CEFBS_HasSIMD128, // CONST_V128_F32x4_S = 716
14734 CEFBS_HasSIMD128, // CONST_V128_F64x2 = 717
14735 CEFBS_HasSIMD128, // CONST_V128_F64x2_S = 718
14736 CEFBS_HasSIMD128, // CONST_V128_I16x8 = 719
14737 CEFBS_HasSIMD128, // CONST_V128_I16x8_S = 720
14738 CEFBS_HasSIMD128, // CONST_V128_I32x4 = 721
14739 CEFBS_HasSIMD128, // CONST_V128_I32x4_S = 722
14740 CEFBS_HasSIMD128, // CONST_V128_I64x2 = 723
14741 CEFBS_HasSIMD128, // CONST_V128_I64x2_S = 724
14742 CEFBS_HasSIMD128, // CONST_V128_I8x16 = 725
14743 CEFBS_HasSIMD128, // CONST_V128_I8x16_S = 726
14744 CEFBS_None, // COPYSIGN_F32 = 727
14745 CEFBS_None, // COPYSIGN_F32_S = 728
14746 CEFBS_None, // COPYSIGN_F64 = 729
14747 CEFBS_None, // COPYSIGN_F64_S = 730
14748 CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF = 731
14749 CEFBS_HasReferenceTypes_HasExceptionHandling, // COPY_EXNREF_S = 732
14750 CEFBS_HasReferenceTypes, // COPY_EXTERNREF = 733
14751 CEFBS_HasReferenceTypes, // COPY_EXTERNREF_S = 734
14752 CEFBS_None, // COPY_F32 = 735
14753 CEFBS_None, // COPY_F32_S = 736
14754 CEFBS_None, // COPY_F64 = 737
14755 CEFBS_None, // COPY_F64_S = 738
14756 CEFBS_HasReferenceTypes, // COPY_FUNCREF = 739
14757 CEFBS_HasReferenceTypes, // COPY_FUNCREF_S = 740
14758 CEFBS_None, // COPY_I32 = 741
14759 CEFBS_None, // COPY_I32_S = 742
14760 CEFBS_None, // COPY_I64 = 743
14761 CEFBS_None, // COPY_I64_S = 744
14762 CEFBS_HasSIMD128, // COPY_V128 = 745
14763 CEFBS_HasSIMD128, // COPY_V128_S = 746
14764 CEFBS_None, // CTZ_I32 = 747
14765 CEFBS_None, // CTZ_I32_S = 748
14766 CEFBS_None, // CTZ_I64 = 749
14767 CEFBS_None, // CTZ_I64_S = 750
14768 CEFBS_None, // DEBUG_UNREACHABLE = 751
14769 CEFBS_None, // DEBUG_UNREACHABLE_S = 752
14770 CEFBS_HasExceptionHandling, // DELEGATE = 753
14771 CEFBS_HasExceptionHandling, // DELEGATE_S = 754
14772 CEFBS_HasSIMD128_HasHalfPrecision, // DIV_F16x8 = 755
14773 CEFBS_HasSIMD128_HasHalfPrecision, // DIV_F16x8_S = 756
14774 CEFBS_None, // DIV_F32 = 757
14775 CEFBS_None, // DIV_F32_S = 758
14776 CEFBS_HasSIMD128, // DIV_F32x4 = 759
14777 CEFBS_HasSIMD128, // DIV_F32x4_S = 760
14778 CEFBS_None, // DIV_F64 = 761
14779 CEFBS_None, // DIV_F64_S = 762
14780 CEFBS_HasSIMD128, // DIV_F64x2 = 763
14781 CEFBS_HasSIMD128, // DIV_F64x2_S = 764
14782 CEFBS_None, // DIV_S_I32 = 765
14783 CEFBS_None, // DIV_S_I32_S = 766
14784 CEFBS_None, // DIV_S_I64 = 767
14785 CEFBS_None, // DIV_S_I64_S = 768
14786 CEFBS_None, // DIV_U_I32 = 769
14787 CEFBS_None, // DIV_U_I32_S = 770
14788 CEFBS_None, // DIV_U_I64 = 771
14789 CEFBS_None, // DIV_U_I64_S = 772
14790 CEFBS_HasSIMD128, // DOT = 773
14791 CEFBS_HasSIMD128, // DOT_S = 774
14792 CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF = 775
14793 CEFBS_HasReferenceTypes_HasExceptionHandling, // DROP_EXNREF_S = 776
14794 CEFBS_HasReferenceTypes, // DROP_EXTERNREF = 777
14795 CEFBS_HasReferenceTypes, // DROP_EXTERNREF_S = 778
14796 CEFBS_None, // DROP_F32 = 779
14797 CEFBS_None, // DROP_F32_S = 780
14798 CEFBS_None, // DROP_F64 = 781
14799 CEFBS_None, // DROP_F64_S = 782
14800 CEFBS_HasReferenceTypes, // DROP_FUNCREF = 783
14801 CEFBS_HasReferenceTypes, // DROP_FUNCREF_S = 784
14802 CEFBS_None, // DROP_I32 = 785
14803 CEFBS_None, // DROP_I32_S = 786
14804 CEFBS_None, // DROP_I64 = 787
14805 CEFBS_None, // DROP_I64_S = 788
14806 CEFBS_HasSIMD128, // DROP_V128 = 789
14807 CEFBS_HasSIMD128, // DROP_V128_S = 790
14808 CEFBS_None, // ELSE = 791
14809 CEFBS_None, // ELSE_S = 792
14810 CEFBS_None, // END = 793
14811 CEFBS_None, // END_BLOCK = 794
14812 CEFBS_None, // END_BLOCK_S = 795
14813 CEFBS_None, // END_FUNCTION = 796
14814 CEFBS_None, // END_FUNCTION_S = 797
14815 CEFBS_None, // END_IF = 798
14816 CEFBS_None, // END_IF_S = 799
14817 CEFBS_None, // END_LOOP = 800
14818 CEFBS_None, // END_LOOP_S = 801
14819 CEFBS_None, // END_S = 802
14820 CEFBS_HasExceptionHandling, // END_TRY = 803
14821 CEFBS_HasExceptionHandling, // END_TRY_S = 804
14822 CEFBS_None, // EQZ_I32 = 805
14823 CEFBS_None, // EQZ_I32_S = 806
14824 CEFBS_None, // EQZ_I64 = 807
14825 CEFBS_None, // EQZ_I64_S = 808
14826 CEFBS_HasSIMD128_HasHalfPrecision, // EQ_F16x8 = 809
14827 CEFBS_HasSIMD128_HasHalfPrecision, // EQ_F16x8_S = 810
14828 CEFBS_None, // EQ_F32 = 811
14829 CEFBS_None, // EQ_F32_S = 812
14830 CEFBS_HasSIMD128, // EQ_F32x4 = 813
14831 CEFBS_HasSIMD128, // EQ_F32x4_S = 814
14832 CEFBS_None, // EQ_F64 = 815
14833 CEFBS_None, // EQ_F64_S = 816
14834 CEFBS_HasSIMD128, // EQ_F64x2 = 817
14835 CEFBS_HasSIMD128, // EQ_F64x2_S = 818
14836 CEFBS_HasSIMD128, // EQ_I16x8 = 819
14837 CEFBS_HasSIMD128, // EQ_I16x8_S = 820
14838 CEFBS_None, // EQ_I32 = 821
14839 CEFBS_None, // EQ_I32_S = 822
14840 CEFBS_HasSIMD128, // EQ_I32x4 = 823
14841 CEFBS_HasSIMD128, // EQ_I32x4_S = 824
14842 CEFBS_None, // EQ_I64 = 825
14843 CEFBS_None, // EQ_I64_S = 826
14844 CEFBS_HasSIMD128, // EQ_I64x2 = 827
14845 CEFBS_HasSIMD128, // EQ_I64x2_S = 828
14846 CEFBS_HasSIMD128, // EQ_I8x16 = 829
14847 CEFBS_HasSIMD128, // EQ_I8x16_S = 830
14848 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8 = 831
14849 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I16x8_S = 832
14850 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4 = 833
14851 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I32x4_S = 834
14852 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2 = 835
14853 CEFBS_HasSIMD128, // EXTMUL_HIGH_S_I64x2_S = 836
14854 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8 = 837
14855 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I16x8_S = 838
14856 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4 = 839
14857 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I32x4_S = 840
14858 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2 = 841
14859 CEFBS_HasSIMD128, // EXTMUL_HIGH_U_I64x2_S = 842
14860 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8 = 843
14861 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I16x8_S = 844
14862 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4 = 845
14863 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I32x4_S = 846
14864 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2 = 847
14865 CEFBS_HasSIMD128, // EXTMUL_LOW_S_I64x2_S = 848
14866 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8 = 849
14867 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I16x8_S = 850
14868 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4 = 851
14869 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I32x4_S = 852
14870 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2 = 853
14871 CEFBS_HasSIMD128, // EXTMUL_LOW_U_I64x2_S = 854
14872 CEFBS_HasHalfPrecision, // EXTRACT_LANE_F16x8 = 855
14873 CEFBS_HasHalfPrecision, // EXTRACT_LANE_F16x8_S = 856
14874 CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4 = 857
14875 CEFBS_HasSIMD128, // EXTRACT_LANE_F32x4_S = 858
14876 CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2 = 859
14877 CEFBS_HasSIMD128, // EXTRACT_LANE_F64x2_S = 860
14878 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s = 861
14879 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_s_S = 862
14880 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u = 863
14881 CEFBS_HasSIMD128, // EXTRACT_LANE_I16x8_u_S = 864
14882 CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4 = 865
14883 CEFBS_HasSIMD128, // EXTRACT_LANE_I32x4_S = 866
14884 CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2 = 867
14885 CEFBS_HasSIMD128, // EXTRACT_LANE_I64x2_S = 868
14886 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s = 869
14887 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_s_S = 870
14888 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u = 871
14889 CEFBS_HasSIMD128, // EXTRACT_LANE_I8x16_u_S = 872
14890 CEFBS_None, // F32_CONVERT_S_I32 = 873
14891 CEFBS_None, // F32_CONVERT_S_I32_S = 874
14892 CEFBS_None, // F32_CONVERT_S_I64 = 875
14893 CEFBS_None, // F32_CONVERT_S_I64_S = 876
14894 CEFBS_None, // F32_CONVERT_U_I32 = 877
14895 CEFBS_None, // F32_CONVERT_U_I32_S = 878
14896 CEFBS_None, // F32_CONVERT_U_I64 = 879
14897 CEFBS_None, // F32_CONVERT_U_I64_S = 880
14898 CEFBS_None, // F32_DEMOTE_F64 = 881
14899 CEFBS_None, // F32_DEMOTE_F64_S = 882
14900 CEFBS_None, // F32_REINTERPRET_I32 = 883
14901 CEFBS_None, // F32_REINTERPRET_I32_S = 884
14902 CEFBS_None, // F64_CONVERT_S_I32 = 885
14903 CEFBS_None, // F64_CONVERT_S_I32_S = 886
14904 CEFBS_None, // F64_CONVERT_S_I64 = 887
14905 CEFBS_None, // F64_CONVERT_S_I64_S = 888
14906 CEFBS_None, // F64_CONVERT_U_I32 = 889
14907 CEFBS_None, // F64_CONVERT_U_I32_S = 890
14908 CEFBS_None, // F64_CONVERT_U_I64 = 891
14909 CEFBS_None, // F64_CONVERT_U_I64_S = 892
14910 CEFBS_None, // F64_PROMOTE_F32 = 893
14911 CEFBS_None, // F64_PROMOTE_F32_S = 894
14912 CEFBS_None, // F64_REINTERPRET_I64 = 895
14913 CEFBS_None, // F64_REINTERPRET_I64_S = 896
14914 CEFBS_None, // FALLTHROUGH_RETURN = 897
14915 CEFBS_None, // FALLTHROUGH_RETURN_S = 898
14916 CEFBS_HasSIMD128_HasHalfPrecision, // FLOOR_F16x8 = 899
14917 CEFBS_HasSIMD128_HasHalfPrecision, // FLOOR_F16x8_S = 900
14918 CEFBS_None, // FLOOR_F32 = 901
14919 CEFBS_None, // FLOOR_F32_S = 902
14920 CEFBS_HasSIMD128, // FLOOR_F32x4 = 903
14921 CEFBS_HasSIMD128, // FLOOR_F32x4_S = 904
14922 CEFBS_None, // FLOOR_F64 = 905
14923 CEFBS_None, // FLOOR_F64_S = 906
14924 CEFBS_HasSIMD128, // FLOOR_F64x2 = 907
14925 CEFBS_HasSIMD128, // FLOOR_F64x2_S = 908
14926 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32 = 909
14927 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F32_S = 910
14928 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64 = 911
14929 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I32_F64_S = 912
14930 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32 = 913
14931 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F32_S = 914
14932 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64 = 915
14933 CEFBS_NotHasNontrappingFPToInt, // FP_TO_SINT_I64_F64_S = 916
14934 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32 = 917
14935 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F32_S = 918
14936 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64 = 919
14937 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I32_F64_S = 920
14938 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32 = 921
14939 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F32_S = 922
14940 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64 = 923
14941 CEFBS_NotHasNontrappingFPToInt, // FP_TO_UINT_I64_F64_S = 924
14942 CEFBS_HasSIMD128_HasHalfPrecision, // GE_F16x8 = 925
14943 CEFBS_HasSIMD128_HasHalfPrecision, // GE_F16x8_S = 926
14944 CEFBS_None, // GE_F32 = 927
14945 CEFBS_None, // GE_F32_S = 928
14946 CEFBS_HasSIMD128, // GE_F32x4 = 929
14947 CEFBS_HasSIMD128, // GE_F32x4_S = 930
14948 CEFBS_None, // GE_F64 = 931
14949 CEFBS_None, // GE_F64_S = 932
14950 CEFBS_HasSIMD128, // GE_F64x2 = 933
14951 CEFBS_HasSIMD128, // GE_F64x2_S = 934
14952 CEFBS_HasSIMD128, // GE_S_I16x8 = 935
14953 CEFBS_HasSIMD128, // GE_S_I16x8_S = 936
14954 CEFBS_None, // GE_S_I32 = 937
14955 CEFBS_None, // GE_S_I32_S = 938
14956 CEFBS_HasSIMD128, // GE_S_I32x4 = 939
14957 CEFBS_HasSIMD128, // GE_S_I32x4_S = 940
14958 CEFBS_None, // GE_S_I64 = 941
14959 CEFBS_None, // GE_S_I64_S = 942
14960 CEFBS_HasSIMD128, // GE_S_I64x2 = 943
14961 CEFBS_HasSIMD128, // GE_S_I64x2_S = 944
14962 CEFBS_HasSIMD128, // GE_S_I8x16 = 945
14963 CEFBS_HasSIMD128, // GE_S_I8x16_S = 946
14964 CEFBS_HasSIMD128, // GE_U_I16x8 = 947
14965 CEFBS_HasSIMD128, // GE_U_I16x8_S = 948
14966 CEFBS_None, // GE_U_I32 = 949
14967 CEFBS_None, // GE_U_I32_S = 950
14968 CEFBS_HasSIMD128, // GE_U_I32x4 = 951
14969 CEFBS_HasSIMD128, // GE_U_I32x4_S = 952
14970 CEFBS_None, // GE_U_I64 = 953
14971 CEFBS_None, // GE_U_I64_S = 954
14972 CEFBS_HasSIMD128, // GE_U_I8x16 = 955
14973 CEFBS_HasSIMD128, // GE_U_I8x16_S = 956
14974 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF = 957
14975 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_GET_EXNREF_S = 958
14976 CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF = 959
14977 CEFBS_HasReferenceTypes, // GLOBAL_GET_EXTERNREF_S = 960
14978 CEFBS_None, // GLOBAL_GET_F32 = 961
14979 CEFBS_None, // GLOBAL_GET_F32_S = 962
14980 CEFBS_None, // GLOBAL_GET_F64 = 963
14981 CEFBS_None, // GLOBAL_GET_F64_S = 964
14982 CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF = 965
14983 CEFBS_HasReferenceTypes, // GLOBAL_GET_FUNCREF_S = 966
14984 CEFBS_None, // GLOBAL_GET_I32 = 967
14985 CEFBS_None, // GLOBAL_GET_I32_S = 968
14986 CEFBS_None, // GLOBAL_GET_I64 = 969
14987 CEFBS_None, // GLOBAL_GET_I64_S = 970
14988 CEFBS_HasSIMD128, // GLOBAL_GET_V128 = 971
14989 CEFBS_HasSIMD128, // GLOBAL_GET_V128_S = 972
14990 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF = 973
14991 CEFBS_HasReferenceTypes_HasExceptionHandling, // GLOBAL_SET_EXNREF_S = 974
14992 CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF = 975
14993 CEFBS_HasReferenceTypes, // GLOBAL_SET_EXTERNREF_S = 976
14994 CEFBS_None, // GLOBAL_SET_F32 = 977
14995 CEFBS_None, // GLOBAL_SET_F32_S = 978
14996 CEFBS_None, // GLOBAL_SET_F64 = 979
14997 CEFBS_None, // GLOBAL_SET_F64_S = 980
14998 CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF = 981
14999 CEFBS_HasReferenceTypes, // GLOBAL_SET_FUNCREF_S = 982
15000 CEFBS_None, // GLOBAL_SET_I32 = 983
15001 CEFBS_None, // GLOBAL_SET_I32_S = 984
15002 CEFBS_None, // GLOBAL_SET_I64 = 985
15003 CEFBS_None, // GLOBAL_SET_I64_S = 986
15004 CEFBS_HasSIMD128, // GLOBAL_SET_V128 = 987
15005 CEFBS_HasSIMD128, // GLOBAL_SET_V128_S = 988
15006 CEFBS_HasSIMD128_HasHalfPrecision, // GT_F16x8 = 989
15007 CEFBS_HasSIMD128_HasHalfPrecision, // GT_F16x8_S = 990
15008 CEFBS_None, // GT_F32 = 991
15009 CEFBS_None, // GT_F32_S = 992
15010 CEFBS_HasSIMD128, // GT_F32x4 = 993
15011 CEFBS_HasSIMD128, // GT_F32x4_S = 994
15012 CEFBS_None, // GT_F64 = 995
15013 CEFBS_None, // GT_F64_S = 996
15014 CEFBS_HasSIMD128, // GT_F64x2 = 997
15015 CEFBS_HasSIMD128, // GT_F64x2_S = 998
15016 CEFBS_HasSIMD128, // GT_S_I16x8 = 999
15017 CEFBS_HasSIMD128, // GT_S_I16x8_S = 1000
15018 CEFBS_None, // GT_S_I32 = 1001
15019 CEFBS_None, // GT_S_I32_S = 1002
15020 CEFBS_HasSIMD128, // GT_S_I32x4 = 1003
15021 CEFBS_HasSIMD128, // GT_S_I32x4_S = 1004
15022 CEFBS_None, // GT_S_I64 = 1005
15023 CEFBS_None, // GT_S_I64_S = 1006
15024 CEFBS_HasSIMD128, // GT_S_I64x2 = 1007
15025 CEFBS_HasSIMD128, // GT_S_I64x2_S = 1008
15026 CEFBS_HasSIMD128, // GT_S_I8x16 = 1009
15027 CEFBS_HasSIMD128, // GT_S_I8x16_S = 1010
15028 CEFBS_HasSIMD128, // GT_U_I16x8 = 1011
15029 CEFBS_HasSIMD128, // GT_U_I16x8_S = 1012
15030 CEFBS_None, // GT_U_I32 = 1013
15031 CEFBS_None, // GT_U_I32_S = 1014
15032 CEFBS_HasSIMD128, // GT_U_I32x4 = 1015
15033 CEFBS_HasSIMD128, // GT_U_I32x4_S = 1016
15034 CEFBS_None, // GT_U_I64 = 1017
15035 CEFBS_None, // GT_U_I64_S = 1018
15036 CEFBS_HasSIMD128, // GT_U_I8x16 = 1019
15037 CEFBS_HasSIMD128, // GT_U_I8x16_S = 1020
15038 CEFBS_HasSignExt, // I32_EXTEND16_S_I32 = 1021
15039 CEFBS_HasSignExt, // I32_EXTEND16_S_I32_S = 1022
15040 CEFBS_HasSignExt, // I32_EXTEND8_S_I32 = 1023
15041 CEFBS_HasSignExt, // I32_EXTEND8_S_I32_S = 1024
15042 CEFBS_None, // I32_REINTERPRET_F32 = 1025
15043 CEFBS_None, // I32_REINTERPRET_F32_S = 1026
15044 CEFBS_None, // I32_TRUNC_S_F32 = 1027
15045 CEFBS_None, // I32_TRUNC_S_F32_S = 1028
15046 CEFBS_None, // I32_TRUNC_S_F64 = 1029
15047 CEFBS_None, // I32_TRUNC_S_F64_S = 1030
15048 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32 = 1031
15049 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F32_S = 1032
15050 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64 = 1033
15051 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_S_SAT_F64_S = 1034
15052 CEFBS_None, // I32_TRUNC_U_F32 = 1035
15053 CEFBS_None, // I32_TRUNC_U_F32_S = 1036
15054 CEFBS_None, // I32_TRUNC_U_F64 = 1037
15055 CEFBS_None, // I32_TRUNC_U_F64_S = 1038
15056 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32 = 1039
15057 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F32_S = 1040
15058 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64 = 1041
15059 CEFBS_HasNontrappingFPToInt, // I32_TRUNC_U_SAT_F64_S = 1042
15060 CEFBS_None, // I32_WRAP_I64 = 1043
15061 CEFBS_None, // I32_WRAP_I64_S = 1044
15062 CEFBS_HasSignExt, // I64_EXTEND16_S_I64 = 1045
15063 CEFBS_HasSignExt, // I64_EXTEND16_S_I64_S = 1046
15064 CEFBS_HasSignExt, // I64_EXTEND32_S_I64 = 1047
15065 CEFBS_HasSignExt, // I64_EXTEND32_S_I64_S = 1048
15066 CEFBS_HasSignExt, // I64_EXTEND8_S_I64 = 1049
15067 CEFBS_HasSignExt, // I64_EXTEND8_S_I64_S = 1050
15068 CEFBS_None, // I64_EXTEND_S_I32 = 1051
15069 CEFBS_None, // I64_EXTEND_S_I32_S = 1052
15070 CEFBS_None, // I64_EXTEND_U_I32 = 1053
15071 CEFBS_None, // I64_EXTEND_U_I32_S = 1054
15072 CEFBS_None, // I64_REINTERPRET_F64 = 1055
15073 CEFBS_None, // I64_REINTERPRET_F64_S = 1056
15074 CEFBS_None, // I64_TRUNC_S_F32 = 1057
15075 CEFBS_None, // I64_TRUNC_S_F32_S = 1058
15076 CEFBS_None, // I64_TRUNC_S_F64 = 1059
15077 CEFBS_None, // I64_TRUNC_S_F64_S = 1060
15078 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32 = 1061
15079 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F32_S = 1062
15080 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64 = 1063
15081 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_S_SAT_F64_S = 1064
15082 CEFBS_None, // I64_TRUNC_U_F32 = 1065
15083 CEFBS_None, // I64_TRUNC_U_F32_S = 1066
15084 CEFBS_None, // I64_TRUNC_U_F64 = 1067
15085 CEFBS_None, // I64_TRUNC_U_F64_S = 1068
15086 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32 = 1069
15087 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F32_S = 1070
15088 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64 = 1071
15089 CEFBS_HasNontrappingFPToInt, // I64_TRUNC_U_SAT_F64_S = 1072
15090 CEFBS_None, // IF = 1073
15091 CEFBS_None, // IF_S = 1074
15092 CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8 = 1075
15093 CEFBS_HasRelaxedSIMD, // LANESELECT_I16x8_S = 1076
15094 CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4 = 1077
15095 CEFBS_HasRelaxedSIMD, // LANESELECT_I32x4_S = 1078
15096 CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2 = 1079
15097 CEFBS_HasRelaxedSIMD, // LANESELECT_I64x2_S = 1080
15098 CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16 = 1081
15099 CEFBS_HasRelaxedSIMD, // LANESELECT_I8x16_S = 1082
15100 CEFBS_HasSIMD128_HasHalfPrecision, // LE_F16x8 = 1083
15101 CEFBS_HasSIMD128_HasHalfPrecision, // LE_F16x8_S = 1084
15102 CEFBS_None, // LE_F32 = 1085
15103 CEFBS_None, // LE_F32_S = 1086
15104 CEFBS_HasSIMD128, // LE_F32x4 = 1087
15105 CEFBS_HasSIMD128, // LE_F32x4_S = 1088
15106 CEFBS_None, // LE_F64 = 1089
15107 CEFBS_None, // LE_F64_S = 1090
15108 CEFBS_HasSIMD128, // LE_F64x2 = 1091
15109 CEFBS_HasSIMD128, // LE_F64x2_S = 1092
15110 CEFBS_HasSIMD128, // LE_S_I16x8 = 1093
15111 CEFBS_HasSIMD128, // LE_S_I16x8_S = 1094
15112 CEFBS_None, // LE_S_I32 = 1095
15113 CEFBS_None, // LE_S_I32_S = 1096
15114 CEFBS_HasSIMD128, // LE_S_I32x4 = 1097
15115 CEFBS_HasSIMD128, // LE_S_I32x4_S = 1098
15116 CEFBS_None, // LE_S_I64 = 1099
15117 CEFBS_None, // LE_S_I64_S = 1100
15118 CEFBS_HasSIMD128, // LE_S_I64x2 = 1101
15119 CEFBS_HasSIMD128, // LE_S_I64x2_S = 1102
15120 CEFBS_HasSIMD128, // LE_S_I8x16 = 1103
15121 CEFBS_HasSIMD128, // LE_S_I8x16_S = 1104
15122 CEFBS_HasSIMD128, // LE_U_I16x8 = 1105
15123 CEFBS_HasSIMD128, // LE_U_I16x8_S = 1106
15124 CEFBS_None, // LE_U_I32 = 1107
15125 CEFBS_None, // LE_U_I32_S = 1108
15126 CEFBS_HasSIMD128, // LE_U_I32x4 = 1109
15127 CEFBS_HasSIMD128, // LE_U_I32x4_S = 1110
15128 CEFBS_None, // LE_U_I64 = 1111
15129 CEFBS_None, // LE_U_I64_S = 1112
15130 CEFBS_HasSIMD128, // LE_U_I8x16 = 1113
15131 CEFBS_HasSIMD128, // LE_U_I8x16_S = 1114
15132 CEFBS_HasSIMD128, // LOAD16_SPLAT_A32 = 1115
15133 CEFBS_HasSIMD128, // LOAD16_SPLAT_A32_S = 1116
15134 CEFBS_HasSIMD128, // LOAD16_SPLAT_A64 = 1117
15135 CEFBS_HasSIMD128, // LOAD16_SPLAT_A64_S = 1118
15136 CEFBS_None, // LOAD16_S_I32_A32 = 1119
15137 CEFBS_None, // LOAD16_S_I32_A32_S = 1120
15138 CEFBS_None, // LOAD16_S_I32_A64 = 1121
15139 CEFBS_None, // LOAD16_S_I32_A64_S = 1122
15140 CEFBS_None, // LOAD16_S_I64_A32 = 1123
15141 CEFBS_None, // LOAD16_S_I64_A32_S = 1124
15142 CEFBS_None, // LOAD16_S_I64_A64 = 1125
15143 CEFBS_None, // LOAD16_S_I64_A64_S = 1126
15144 CEFBS_None, // LOAD16_U_I32_A32 = 1127
15145 CEFBS_None, // LOAD16_U_I32_A32_S = 1128
15146 CEFBS_None, // LOAD16_U_I32_A64 = 1129
15147 CEFBS_None, // LOAD16_U_I32_A64_S = 1130
15148 CEFBS_None, // LOAD16_U_I64_A32 = 1131
15149 CEFBS_None, // LOAD16_U_I64_A32_S = 1132
15150 CEFBS_None, // LOAD16_U_I64_A64 = 1133
15151 CEFBS_None, // LOAD16_U_I64_A64_S = 1134
15152 CEFBS_HasSIMD128, // LOAD32_SPLAT_A32 = 1135
15153 CEFBS_HasSIMD128, // LOAD32_SPLAT_A32_S = 1136
15154 CEFBS_HasSIMD128, // LOAD32_SPLAT_A64 = 1137
15155 CEFBS_HasSIMD128, // LOAD32_SPLAT_A64_S = 1138
15156 CEFBS_None, // LOAD32_S_I64_A32 = 1139
15157 CEFBS_None, // LOAD32_S_I64_A32_S = 1140
15158 CEFBS_None, // LOAD32_S_I64_A64 = 1141
15159 CEFBS_None, // LOAD32_S_I64_A64_S = 1142
15160 CEFBS_None, // LOAD32_U_I64_A32 = 1143
15161 CEFBS_None, // LOAD32_U_I64_A32_S = 1144
15162 CEFBS_None, // LOAD32_U_I64_A64 = 1145
15163 CEFBS_None, // LOAD32_U_I64_A64_S = 1146
15164 CEFBS_HasSIMD128, // LOAD64_SPLAT_A32 = 1147
15165 CEFBS_HasSIMD128, // LOAD64_SPLAT_A32_S = 1148
15166 CEFBS_HasSIMD128, // LOAD64_SPLAT_A64 = 1149
15167 CEFBS_HasSIMD128, // LOAD64_SPLAT_A64_S = 1150
15168 CEFBS_HasSIMD128, // LOAD8_SPLAT_A32 = 1151
15169 CEFBS_HasSIMD128, // LOAD8_SPLAT_A32_S = 1152
15170 CEFBS_HasSIMD128, // LOAD8_SPLAT_A64 = 1153
15171 CEFBS_HasSIMD128, // LOAD8_SPLAT_A64_S = 1154
15172 CEFBS_None, // LOAD8_S_I32_A32 = 1155
15173 CEFBS_None, // LOAD8_S_I32_A32_S = 1156
15174 CEFBS_None, // LOAD8_S_I32_A64 = 1157
15175 CEFBS_None, // LOAD8_S_I32_A64_S = 1158
15176 CEFBS_None, // LOAD8_S_I64_A32 = 1159
15177 CEFBS_None, // LOAD8_S_I64_A32_S = 1160
15178 CEFBS_None, // LOAD8_S_I64_A64 = 1161
15179 CEFBS_None, // LOAD8_S_I64_A64_S = 1162
15180 CEFBS_None, // LOAD8_U_I32_A32 = 1163
15181 CEFBS_None, // LOAD8_U_I32_A32_S = 1164
15182 CEFBS_None, // LOAD8_U_I32_A64 = 1165
15183 CEFBS_None, // LOAD8_U_I32_A64_S = 1166
15184 CEFBS_None, // LOAD8_U_I64_A32 = 1167
15185 CEFBS_None, // LOAD8_U_I64_A32_S = 1168
15186 CEFBS_None, // LOAD8_U_I64_A64 = 1169
15187 CEFBS_None, // LOAD8_U_I64_A64_S = 1170
15188 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32 = 1171
15189 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A32_S = 1172
15190 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64 = 1173
15191 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I16x8_A64_S = 1174
15192 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32 = 1175
15193 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A32_S = 1176
15194 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64 = 1177
15195 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I32x4_A64_S = 1178
15196 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32 = 1179
15197 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A32_S = 1180
15198 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64 = 1181
15199 CEFBS_HasSIMD128, // LOAD_EXTEND_S_I64x2_A64_S = 1182
15200 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32 = 1183
15201 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A32_S = 1184
15202 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64 = 1185
15203 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I16x8_A64_S = 1186
15204 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32 = 1187
15205 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A32_S = 1188
15206 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64 = 1189
15207 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I32x4_A64_S = 1190
15208 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32 = 1191
15209 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A32_S = 1192
15210 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64 = 1193
15211 CEFBS_HasSIMD128, // LOAD_EXTEND_U_I64x2_A64_S = 1194
15212 CEFBS_HasHalfPrecision, // LOAD_F16_F32_A32 = 1195
15213 CEFBS_HasHalfPrecision, // LOAD_F16_F32_A32_S = 1196
15214 CEFBS_HasHalfPrecision, // LOAD_F16_F32_A64 = 1197
15215 CEFBS_HasHalfPrecision, // LOAD_F16_F32_A64_S = 1198
15216 CEFBS_None, // LOAD_F32_A32 = 1199
15217 CEFBS_None, // LOAD_F32_A32_S = 1200
15218 CEFBS_None, // LOAD_F32_A64 = 1201
15219 CEFBS_None, // LOAD_F32_A64_S = 1202
15220 CEFBS_None, // LOAD_F64_A32 = 1203
15221 CEFBS_None, // LOAD_F64_A32_S = 1204
15222 CEFBS_None, // LOAD_F64_A64 = 1205
15223 CEFBS_None, // LOAD_F64_A64_S = 1206
15224 CEFBS_None, // LOAD_I32_A32 = 1207
15225 CEFBS_None, // LOAD_I32_A32_S = 1208
15226 CEFBS_None, // LOAD_I32_A64 = 1209
15227 CEFBS_None, // LOAD_I32_A64_S = 1210
15228 CEFBS_None, // LOAD_I64_A32 = 1211
15229 CEFBS_None, // LOAD_I64_A32_S = 1212
15230 CEFBS_None, // LOAD_I64_A64 = 1213
15231 CEFBS_None, // LOAD_I64_A64_S = 1214
15232 CEFBS_HasSIMD128, // LOAD_LANE_I16x8_A32 = 1215
15233 CEFBS_HasSIMD128, // LOAD_LANE_I16x8_A32_S = 1216
15234 CEFBS_HasSIMD128, // LOAD_LANE_I16x8_A64 = 1217
15235 CEFBS_HasSIMD128, // LOAD_LANE_I16x8_A64_S = 1218
15236 CEFBS_HasSIMD128, // LOAD_LANE_I32x4_A32 = 1219
15237 CEFBS_HasSIMD128, // LOAD_LANE_I32x4_A32_S = 1220
15238 CEFBS_HasSIMD128, // LOAD_LANE_I32x4_A64 = 1221
15239 CEFBS_HasSIMD128, // LOAD_LANE_I32x4_A64_S = 1222
15240 CEFBS_HasSIMD128, // LOAD_LANE_I64x2_A32 = 1223
15241 CEFBS_HasSIMD128, // LOAD_LANE_I64x2_A32_S = 1224
15242 CEFBS_HasSIMD128, // LOAD_LANE_I64x2_A64 = 1225
15243 CEFBS_HasSIMD128, // LOAD_LANE_I64x2_A64_S = 1226
15244 CEFBS_HasSIMD128, // LOAD_LANE_I8x16_A32 = 1227
15245 CEFBS_HasSIMD128, // LOAD_LANE_I8x16_A32_S = 1228
15246 CEFBS_HasSIMD128, // LOAD_LANE_I8x16_A64 = 1229
15247 CEFBS_HasSIMD128, // LOAD_LANE_I8x16_A64_S = 1230
15248 CEFBS_HasSIMD128, // LOAD_V128_A32 = 1231
15249 CEFBS_HasSIMD128, // LOAD_V128_A32_S = 1232
15250 CEFBS_HasSIMD128, // LOAD_V128_A64 = 1233
15251 CEFBS_HasSIMD128, // LOAD_V128_A64_S = 1234
15252 CEFBS_HasSIMD128, // LOAD_ZERO_I32x4_A32 = 1235
15253 CEFBS_HasSIMD128, // LOAD_ZERO_I32x4_A32_S = 1236
15254 CEFBS_HasSIMD128, // LOAD_ZERO_I32x4_A64 = 1237
15255 CEFBS_HasSIMD128, // LOAD_ZERO_I32x4_A64_S = 1238
15256 CEFBS_HasSIMD128, // LOAD_ZERO_I64x2_A32 = 1239
15257 CEFBS_HasSIMD128, // LOAD_ZERO_I64x2_A32_S = 1240
15258 CEFBS_HasSIMD128, // LOAD_ZERO_I64x2_A64 = 1241
15259 CEFBS_HasSIMD128, // LOAD_ZERO_I64x2_A64_S = 1242
15260 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF = 1243
15261 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_GET_EXNREF_S = 1244
15262 CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF = 1245
15263 CEFBS_HasReferenceTypes, // LOCAL_GET_EXTERNREF_S = 1246
15264 CEFBS_None, // LOCAL_GET_F32 = 1247
15265 CEFBS_None, // LOCAL_GET_F32_S = 1248
15266 CEFBS_None, // LOCAL_GET_F64 = 1249
15267 CEFBS_None, // LOCAL_GET_F64_S = 1250
15268 CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF = 1251
15269 CEFBS_HasReferenceTypes, // LOCAL_GET_FUNCREF_S = 1252
15270 CEFBS_None, // LOCAL_GET_I32 = 1253
15271 CEFBS_None, // LOCAL_GET_I32_S = 1254
15272 CEFBS_None, // LOCAL_GET_I64 = 1255
15273 CEFBS_None, // LOCAL_GET_I64_S = 1256
15274 CEFBS_HasSIMD128, // LOCAL_GET_V128 = 1257
15275 CEFBS_HasSIMD128, // LOCAL_GET_V128_S = 1258
15276 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF = 1259
15277 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_SET_EXNREF_S = 1260
15278 CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF = 1261
15279 CEFBS_HasReferenceTypes, // LOCAL_SET_EXTERNREF_S = 1262
15280 CEFBS_None, // LOCAL_SET_F32 = 1263
15281 CEFBS_None, // LOCAL_SET_F32_S = 1264
15282 CEFBS_None, // LOCAL_SET_F64 = 1265
15283 CEFBS_None, // LOCAL_SET_F64_S = 1266
15284 CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF = 1267
15285 CEFBS_HasReferenceTypes, // LOCAL_SET_FUNCREF_S = 1268
15286 CEFBS_None, // LOCAL_SET_I32 = 1269
15287 CEFBS_None, // LOCAL_SET_I32_S = 1270
15288 CEFBS_None, // LOCAL_SET_I64 = 1271
15289 CEFBS_None, // LOCAL_SET_I64_S = 1272
15290 CEFBS_HasSIMD128, // LOCAL_SET_V128 = 1273
15291 CEFBS_HasSIMD128, // LOCAL_SET_V128_S = 1274
15292 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF = 1275
15293 CEFBS_HasReferenceTypes_HasExceptionHandling, // LOCAL_TEE_EXNREF_S = 1276
15294 CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF = 1277
15295 CEFBS_HasReferenceTypes, // LOCAL_TEE_EXTERNREF_S = 1278
15296 CEFBS_None, // LOCAL_TEE_F32 = 1279
15297 CEFBS_None, // LOCAL_TEE_F32_S = 1280
15298 CEFBS_None, // LOCAL_TEE_F64 = 1281
15299 CEFBS_None, // LOCAL_TEE_F64_S = 1282
15300 CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF = 1283
15301 CEFBS_HasReferenceTypes, // LOCAL_TEE_FUNCREF_S = 1284
15302 CEFBS_None, // LOCAL_TEE_I32 = 1285
15303 CEFBS_None, // LOCAL_TEE_I32_S = 1286
15304 CEFBS_None, // LOCAL_TEE_I64 = 1287
15305 CEFBS_None, // LOCAL_TEE_I64_S = 1288
15306 CEFBS_HasSIMD128, // LOCAL_TEE_V128 = 1289
15307 CEFBS_HasSIMD128, // LOCAL_TEE_V128_S = 1290
15308 CEFBS_None, // LOOP = 1291
15309 CEFBS_None, // LOOP_S = 1292
15310 CEFBS_HasSIMD128_HasHalfPrecision, // LT_F16x8 = 1293
15311 CEFBS_HasSIMD128_HasHalfPrecision, // LT_F16x8_S = 1294
15312 CEFBS_None, // LT_F32 = 1295
15313 CEFBS_None, // LT_F32_S = 1296
15314 CEFBS_HasSIMD128, // LT_F32x4 = 1297
15315 CEFBS_HasSIMD128, // LT_F32x4_S = 1298
15316 CEFBS_None, // LT_F64 = 1299
15317 CEFBS_None, // LT_F64_S = 1300
15318 CEFBS_HasSIMD128, // LT_F64x2 = 1301
15319 CEFBS_HasSIMD128, // LT_F64x2_S = 1302
15320 CEFBS_HasSIMD128, // LT_S_I16x8 = 1303
15321 CEFBS_HasSIMD128, // LT_S_I16x8_S = 1304
15322 CEFBS_None, // LT_S_I32 = 1305
15323 CEFBS_None, // LT_S_I32_S = 1306
15324 CEFBS_HasSIMD128, // LT_S_I32x4 = 1307
15325 CEFBS_HasSIMD128, // LT_S_I32x4_S = 1308
15326 CEFBS_None, // LT_S_I64 = 1309
15327 CEFBS_None, // LT_S_I64_S = 1310
15328 CEFBS_HasSIMD128, // LT_S_I64x2 = 1311
15329 CEFBS_HasSIMD128, // LT_S_I64x2_S = 1312
15330 CEFBS_HasSIMD128, // LT_S_I8x16 = 1313
15331 CEFBS_HasSIMD128, // LT_S_I8x16_S = 1314
15332 CEFBS_HasSIMD128, // LT_U_I16x8 = 1315
15333 CEFBS_HasSIMD128, // LT_U_I16x8_S = 1316
15334 CEFBS_None, // LT_U_I32 = 1317
15335 CEFBS_None, // LT_U_I32_S = 1318
15336 CEFBS_HasSIMD128, // LT_U_I32x4 = 1319
15337 CEFBS_HasSIMD128, // LT_U_I32x4_S = 1320
15338 CEFBS_None, // LT_U_I64 = 1321
15339 CEFBS_None, // LT_U_I64_S = 1322
15340 CEFBS_HasSIMD128, // LT_U_I8x16 = 1323
15341 CEFBS_HasSIMD128, // LT_U_I8x16_S = 1324
15342 CEFBS_HasSIMD128_HasHalfPrecision, // MADD_F16x8 = 1325
15343 CEFBS_HasSIMD128_HasHalfPrecision, // MADD_F16x8_S = 1326
15344 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4 = 1327
15345 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F32x4_S = 1328
15346 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2 = 1329
15347 CEFBS_HasSIMD128_HasRelaxedSIMD, // MADD_F64x2_S = 1330
15348 CEFBS_HasSIMD128_HasHalfPrecision, // MAX_F16x8 = 1331
15349 CEFBS_HasSIMD128_HasHalfPrecision, // MAX_F16x8_S = 1332
15350 CEFBS_None, // MAX_F32 = 1333
15351 CEFBS_None, // MAX_F32_S = 1334
15352 CEFBS_HasSIMD128, // MAX_F32x4 = 1335
15353 CEFBS_HasSIMD128, // MAX_F32x4_S = 1336
15354 CEFBS_None, // MAX_F64 = 1337
15355 CEFBS_None, // MAX_F64_S = 1338
15356 CEFBS_HasSIMD128, // MAX_F64x2 = 1339
15357 CEFBS_HasSIMD128, // MAX_F64x2_S = 1340
15358 CEFBS_HasSIMD128, // MAX_S_I16x8 = 1341
15359 CEFBS_HasSIMD128, // MAX_S_I16x8_S = 1342
15360 CEFBS_HasSIMD128, // MAX_S_I32x4 = 1343
15361 CEFBS_HasSIMD128, // MAX_S_I32x4_S = 1344
15362 CEFBS_HasSIMD128, // MAX_S_I8x16 = 1345
15363 CEFBS_HasSIMD128, // MAX_S_I8x16_S = 1346
15364 CEFBS_HasSIMD128, // MAX_U_I16x8 = 1347
15365 CEFBS_HasSIMD128, // MAX_U_I16x8_S = 1348
15366 CEFBS_HasSIMD128, // MAX_U_I32x4 = 1349
15367 CEFBS_HasSIMD128, // MAX_U_I32x4_S = 1350
15368 CEFBS_HasSIMD128, // MAX_U_I8x16 = 1351
15369 CEFBS_HasSIMD128, // MAX_U_I8x16_S = 1352
15370 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32 = 1353
15371 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A32_S = 1354
15372 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64 = 1355
15373 CEFBS_HasAtomics, // MEMORY_ATOMIC_NOTIFY_A64_S = 1356
15374 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32 = 1357
15375 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A32_S = 1358
15376 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64 = 1359
15377 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT32_A64_S = 1360
15378 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32 = 1361
15379 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A32_S = 1362
15380 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64 = 1363
15381 CEFBS_HasAtomics, // MEMORY_ATOMIC_WAIT64_A64_S = 1364
15382 CEFBS_HasSIMD128_HasHalfPrecision, // MIN_F16x8 = 1365
15383 CEFBS_HasSIMD128_HasHalfPrecision, // MIN_F16x8_S = 1366
15384 CEFBS_None, // MIN_F32 = 1367
15385 CEFBS_None, // MIN_F32_S = 1368
15386 CEFBS_HasSIMD128, // MIN_F32x4 = 1369
15387 CEFBS_HasSIMD128, // MIN_F32x4_S = 1370
15388 CEFBS_None, // MIN_F64 = 1371
15389 CEFBS_None, // MIN_F64_S = 1372
15390 CEFBS_HasSIMD128, // MIN_F64x2 = 1373
15391 CEFBS_HasSIMD128, // MIN_F64x2_S = 1374
15392 CEFBS_HasSIMD128, // MIN_S_I16x8 = 1375
15393 CEFBS_HasSIMD128, // MIN_S_I16x8_S = 1376
15394 CEFBS_HasSIMD128, // MIN_S_I32x4 = 1377
15395 CEFBS_HasSIMD128, // MIN_S_I32x4_S = 1378
15396 CEFBS_HasSIMD128, // MIN_S_I8x16 = 1379
15397 CEFBS_HasSIMD128, // MIN_S_I8x16_S = 1380
15398 CEFBS_HasSIMD128, // MIN_U_I16x8 = 1381
15399 CEFBS_HasSIMD128, // MIN_U_I16x8_S = 1382
15400 CEFBS_HasSIMD128, // MIN_U_I32x4 = 1383
15401 CEFBS_HasSIMD128, // MIN_U_I32x4_S = 1384
15402 CEFBS_HasSIMD128, // MIN_U_I8x16 = 1385
15403 CEFBS_HasSIMD128, // MIN_U_I8x16_S = 1386
15404 CEFBS_HasSIMD128_HasHalfPrecision, // MUL_F16x8 = 1387
15405 CEFBS_HasSIMD128_HasHalfPrecision, // MUL_F16x8_S = 1388
15406 CEFBS_None, // MUL_F32 = 1389
15407 CEFBS_None, // MUL_F32_S = 1390
15408 CEFBS_HasSIMD128, // MUL_F32x4 = 1391
15409 CEFBS_HasSIMD128, // MUL_F32x4_S = 1392
15410 CEFBS_None, // MUL_F64 = 1393
15411 CEFBS_None, // MUL_F64_S = 1394
15412 CEFBS_HasSIMD128, // MUL_F64x2 = 1395
15413 CEFBS_HasSIMD128, // MUL_F64x2_S = 1396
15414 CEFBS_HasSIMD128, // MUL_I16x8 = 1397
15415 CEFBS_HasSIMD128, // MUL_I16x8_S = 1398
15416 CEFBS_None, // MUL_I32 = 1399
15417 CEFBS_None, // MUL_I32_S = 1400
15418 CEFBS_HasSIMD128, // MUL_I32x4 = 1401
15419 CEFBS_HasSIMD128, // MUL_I32x4_S = 1402
15420 CEFBS_None, // MUL_I64 = 1403
15421 CEFBS_None, // MUL_I64_S = 1404
15422 CEFBS_HasSIMD128, // MUL_I64x2 = 1405
15423 CEFBS_HasSIMD128, // MUL_I64x2_S = 1406
15424 CEFBS_HasSIMD128, // NARROW_S_I16x8 = 1407
15425 CEFBS_HasSIMD128, // NARROW_S_I16x8_S = 1408
15426 CEFBS_HasSIMD128, // NARROW_S_I8x16 = 1409
15427 CEFBS_HasSIMD128, // NARROW_S_I8x16_S = 1410
15428 CEFBS_HasSIMD128, // NARROW_U_I16x8 = 1411
15429 CEFBS_HasSIMD128, // NARROW_U_I16x8_S = 1412
15430 CEFBS_HasSIMD128, // NARROW_U_I8x16 = 1413
15431 CEFBS_HasSIMD128, // NARROW_U_I8x16_S = 1414
15432 CEFBS_HasSIMD128_HasHalfPrecision, // NEAREST_F16x8 = 1415
15433 CEFBS_HasSIMD128_HasHalfPrecision, // NEAREST_F16x8_S = 1416
15434 CEFBS_None, // NEAREST_F32 = 1417
15435 CEFBS_None, // NEAREST_F32_S = 1418
15436 CEFBS_HasSIMD128, // NEAREST_F32x4 = 1419
15437 CEFBS_HasSIMD128, // NEAREST_F32x4_S = 1420
15438 CEFBS_None, // NEAREST_F64 = 1421
15439 CEFBS_None, // NEAREST_F64_S = 1422
15440 CEFBS_HasSIMD128, // NEAREST_F64x2 = 1423
15441 CEFBS_HasSIMD128, // NEAREST_F64x2_S = 1424
15442 CEFBS_HasSIMD128_HasHalfPrecision, // NEG_F16x8 = 1425
15443 CEFBS_HasSIMD128_HasHalfPrecision, // NEG_F16x8_S = 1426
15444 CEFBS_None, // NEG_F32 = 1427
15445 CEFBS_None, // NEG_F32_S = 1428
15446 CEFBS_HasSIMD128, // NEG_F32x4 = 1429
15447 CEFBS_HasSIMD128, // NEG_F32x4_S = 1430
15448 CEFBS_None, // NEG_F64 = 1431
15449 CEFBS_None, // NEG_F64_S = 1432
15450 CEFBS_HasSIMD128, // NEG_F64x2 = 1433
15451 CEFBS_HasSIMD128, // NEG_F64x2_S = 1434
15452 CEFBS_HasSIMD128, // NEG_I16x8 = 1435
15453 CEFBS_HasSIMD128, // NEG_I16x8_S = 1436
15454 CEFBS_HasSIMD128, // NEG_I32x4 = 1437
15455 CEFBS_HasSIMD128, // NEG_I32x4_S = 1438
15456 CEFBS_HasSIMD128, // NEG_I64x2 = 1439
15457 CEFBS_HasSIMD128, // NEG_I64x2_S = 1440
15458 CEFBS_HasSIMD128, // NEG_I8x16 = 1441
15459 CEFBS_HasSIMD128, // NEG_I8x16_S = 1442
15460 CEFBS_HasSIMD128_HasHalfPrecision, // NE_F16x8 = 1443
15461 CEFBS_HasSIMD128_HasHalfPrecision, // NE_F16x8_S = 1444
15462 CEFBS_None, // NE_F32 = 1445
15463 CEFBS_None, // NE_F32_S = 1446
15464 CEFBS_HasSIMD128, // NE_F32x4 = 1447
15465 CEFBS_HasSIMD128, // NE_F32x4_S = 1448
15466 CEFBS_None, // NE_F64 = 1449
15467 CEFBS_None, // NE_F64_S = 1450
15468 CEFBS_HasSIMD128, // NE_F64x2 = 1451
15469 CEFBS_HasSIMD128, // NE_F64x2_S = 1452
15470 CEFBS_HasSIMD128, // NE_I16x8 = 1453
15471 CEFBS_HasSIMD128, // NE_I16x8_S = 1454
15472 CEFBS_None, // NE_I32 = 1455
15473 CEFBS_None, // NE_I32_S = 1456
15474 CEFBS_HasSIMD128, // NE_I32x4 = 1457
15475 CEFBS_HasSIMD128, // NE_I32x4_S = 1458
15476 CEFBS_None, // NE_I64 = 1459
15477 CEFBS_None, // NE_I64_S = 1460
15478 CEFBS_HasSIMD128, // NE_I64x2 = 1461
15479 CEFBS_HasSIMD128, // NE_I64x2_S = 1462
15480 CEFBS_HasSIMD128, // NE_I8x16 = 1463
15481 CEFBS_HasSIMD128, // NE_I8x16_S = 1464
15482 CEFBS_HasSIMD128_HasHalfPrecision, // NMADD_F16x8 = 1465
15483 CEFBS_HasSIMD128_HasHalfPrecision, // NMADD_F16x8_S = 1466
15484 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4 = 1467
15485 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F32x4_S = 1468
15486 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2 = 1469
15487 CEFBS_HasSIMD128_HasRelaxedSIMD, // NMADD_F64x2_S = 1470
15488 CEFBS_None, // NOP = 1471
15489 CEFBS_None, // NOP_S = 1472
15490 CEFBS_HasSIMD128, // NOT = 1473
15491 CEFBS_HasSIMD128, // NOT_S = 1474
15492 CEFBS_HasSIMD128, // OR = 1475
15493 CEFBS_None, // OR_I32 = 1476
15494 CEFBS_None, // OR_I32_S = 1477
15495 CEFBS_None, // OR_I64 = 1478
15496 CEFBS_None, // OR_I64_S = 1479
15497 CEFBS_HasSIMD128, // OR_S = 1480
15498 CEFBS_HasSIMD128_HasHalfPrecision, // PMAX_F16x8 = 1481
15499 CEFBS_HasSIMD128_HasHalfPrecision, // PMAX_F16x8_S = 1482
15500 CEFBS_HasSIMD128, // PMAX_F32x4 = 1483
15501 CEFBS_HasSIMD128, // PMAX_F32x4_S = 1484
15502 CEFBS_HasSIMD128, // PMAX_F64x2 = 1485
15503 CEFBS_HasSIMD128, // PMAX_F64x2_S = 1486
15504 CEFBS_HasSIMD128_HasHalfPrecision, // PMIN_F16x8 = 1487
15505 CEFBS_HasSIMD128_HasHalfPrecision, // PMIN_F16x8_S = 1488
15506 CEFBS_HasSIMD128, // PMIN_F32x4 = 1489
15507 CEFBS_HasSIMD128, // PMIN_F32x4_S = 1490
15508 CEFBS_HasSIMD128, // PMIN_F64x2 = 1491
15509 CEFBS_HasSIMD128, // PMIN_F64x2_S = 1492
15510 CEFBS_None, // POPCNT_I32 = 1493
15511 CEFBS_None, // POPCNT_I32_S = 1494
15512 CEFBS_None, // POPCNT_I64 = 1495
15513 CEFBS_None, // POPCNT_I64_S = 1496
15514 CEFBS_HasSIMD128, // POPCNT_I8x16 = 1497
15515 CEFBS_HasSIMD128, // POPCNT_I8x16_S = 1498
15516 CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8 = 1499
15517 CEFBS_HasSIMD128, // Q15MULR_SAT_S_I16x8_S = 1500
15518 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF = 1501
15519 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXNREF_S = 1502
15520 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF = 1503
15521 CEFBS_HasReferenceTypes, // REF_IS_NULL_EXTERNREF_S = 1504
15522 CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF = 1505
15523 CEFBS_HasReferenceTypes, // REF_IS_NULL_FUNCREF_S = 1506
15524 CEFBS_HasReferenceTypes, // REF_NULL_EXNREF = 1507
15525 CEFBS_HasReferenceTypes, // REF_NULL_EXNREF_S = 1508
15526 CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF = 1509
15527 CEFBS_HasReferenceTypes, // REF_NULL_EXTERNREF_S = 1510
15528 CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF = 1511
15529 CEFBS_HasReferenceTypes, // REF_NULL_FUNCREF_S = 1512
15530 CEFBS_HasRelaxedSIMD, // RELAXED_DOT = 1513
15531 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD = 1514
15532 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_ADD_S = 1515
15533 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT = 1516
15534 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_BFLOAT_S = 1517
15535 CEFBS_HasRelaxedSIMD, // RELAXED_DOT_S = 1518
15536 CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8 = 1519
15537 CEFBS_HasRelaxedSIMD, // RELAXED_Q15MULR_S_I16x8_S = 1520
15538 CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE = 1521
15539 CEFBS_HasRelaxedSIMD, // RELAXED_SWIZZLE_S = 1522
15540 CEFBS_None, // REM_S_I32 = 1523
15541 CEFBS_None, // REM_S_I32_S = 1524
15542 CEFBS_None, // REM_S_I64 = 1525
15543 CEFBS_None, // REM_S_I64_S = 1526
15544 CEFBS_None, // REM_U_I32 = 1527
15545 CEFBS_None, // REM_U_I32_S = 1528
15546 CEFBS_None, // REM_U_I64 = 1529
15547 CEFBS_None, // REM_U_I64_S = 1530
15548 CEFBS_HasSIMD128, // REPLACE_LANE_F32x4 = 1531
15549 CEFBS_HasSIMD128, // REPLACE_LANE_F32x4_S = 1532
15550 CEFBS_HasSIMD128, // REPLACE_LANE_F64x2 = 1533
15551 CEFBS_HasSIMD128, // REPLACE_LANE_F64x2_S = 1534
15552 CEFBS_HasSIMD128, // REPLACE_LANE_I16x8 = 1535
15553 CEFBS_HasSIMD128, // REPLACE_LANE_I16x8_S = 1536
15554 CEFBS_HasSIMD128, // REPLACE_LANE_I32x4 = 1537
15555 CEFBS_HasSIMD128, // REPLACE_LANE_I32x4_S = 1538
15556 CEFBS_HasSIMD128, // REPLACE_LANE_I64x2 = 1539
15557 CEFBS_HasSIMD128, // REPLACE_LANE_I64x2_S = 1540
15558 CEFBS_HasSIMD128, // REPLACE_LANE_I8x16 = 1541
15559 CEFBS_HasSIMD128, // REPLACE_LANE_I8x16_S = 1542
15560 CEFBS_HasExceptionHandling, // RETHROW = 1543
15561 CEFBS_HasExceptionHandling, // RETHROW_S = 1544
15562 CEFBS_None, // RETURN = 1545
15563 CEFBS_None, // RETURN_S = 1546
15564 CEFBS_HasTailCall, // RET_CALL = 1547
15565 CEFBS_HasTailCall, // RET_CALL_INDIRECT = 1548
15566 CEFBS_HasTailCall, // RET_CALL_INDIRECT_S = 1549
15567 CEFBS_HasTailCall, // RET_CALL_S = 1550
15568 CEFBS_None, // ROTL_I32 = 1551
15569 CEFBS_None, // ROTL_I32_S = 1552
15570 CEFBS_None, // ROTL_I64 = 1553
15571 CEFBS_None, // ROTL_I64_S = 1554
15572 CEFBS_None, // ROTR_I32 = 1555
15573 CEFBS_None, // ROTR_I32_S = 1556
15574 CEFBS_None, // ROTR_I64 = 1557
15575 CEFBS_None, // ROTR_I64_S = 1558
15576 CEFBS_HasReferenceTypes, // SELECT_EXNREF = 1559
15577 CEFBS_HasReferenceTypes, // SELECT_EXNREF_S = 1560
15578 CEFBS_HasReferenceTypes, // SELECT_EXTERNREF = 1561
15579 CEFBS_HasReferenceTypes, // SELECT_EXTERNREF_S = 1562
15580 CEFBS_None, // SELECT_F32 = 1563
15581 CEFBS_None, // SELECT_F32_S = 1564
15582 CEFBS_None, // SELECT_F64 = 1565
15583 CEFBS_None, // SELECT_F64_S = 1566
15584 CEFBS_HasReferenceTypes, // SELECT_FUNCREF = 1567
15585 CEFBS_HasReferenceTypes, // SELECT_FUNCREF_S = 1568
15586 CEFBS_None, // SELECT_I32 = 1569
15587 CEFBS_None, // SELECT_I32_S = 1570
15588 CEFBS_None, // SELECT_I64 = 1571
15589 CEFBS_None, // SELECT_I64_S = 1572
15590 CEFBS_None, // SELECT_V128 = 1573
15591 CEFBS_None, // SELECT_V128_S = 1574
15592 CEFBS_HasSIMD128, // SHL_I16x8 = 1575
15593 CEFBS_HasSIMD128, // SHL_I16x8_S = 1576
15594 CEFBS_None, // SHL_I32 = 1577
15595 CEFBS_None, // SHL_I32_S = 1578
15596 CEFBS_HasSIMD128, // SHL_I32x4 = 1579
15597 CEFBS_HasSIMD128, // SHL_I32x4_S = 1580
15598 CEFBS_None, // SHL_I64 = 1581
15599 CEFBS_None, // SHL_I64_S = 1582
15600 CEFBS_HasSIMD128, // SHL_I64x2 = 1583
15601 CEFBS_HasSIMD128, // SHL_I64x2_S = 1584
15602 CEFBS_HasSIMD128, // SHL_I8x16 = 1585
15603 CEFBS_HasSIMD128, // SHL_I8x16_S = 1586
15604 CEFBS_HasSIMD128, // SHR_S_I16x8 = 1587
15605 CEFBS_HasSIMD128, // SHR_S_I16x8_S = 1588
15606 CEFBS_None, // SHR_S_I32 = 1589
15607 CEFBS_None, // SHR_S_I32_S = 1590
15608 CEFBS_HasSIMD128, // SHR_S_I32x4 = 1591
15609 CEFBS_HasSIMD128, // SHR_S_I32x4_S = 1592
15610 CEFBS_None, // SHR_S_I64 = 1593
15611 CEFBS_None, // SHR_S_I64_S = 1594
15612 CEFBS_HasSIMD128, // SHR_S_I64x2 = 1595
15613 CEFBS_HasSIMD128, // SHR_S_I64x2_S = 1596
15614 CEFBS_HasSIMD128, // SHR_S_I8x16 = 1597
15615 CEFBS_HasSIMD128, // SHR_S_I8x16_S = 1598
15616 CEFBS_HasSIMD128, // SHR_U_I16x8 = 1599
15617 CEFBS_HasSIMD128, // SHR_U_I16x8_S = 1600
15618 CEFBS_None, // SHR_U_I32 = 1601
15619 CEFBS_None, // SHR_U_I32_S = 1602
15620 CEFBS_HasSIMD128, // SHR_U_I32x4 = 1603
15621 CEFBS_HasSIMD128, // SHR_U_I32x4_S = 1604
15622 CEFBS_None, // SHR_U_I64 = 1605
15623 CEFBS_None, // SHR_U_I64_S = 1606
15624 CEFBS_HasSIMD128, // SHR_U_I64x2 = 1607
15625 CEFBS_HasSIMD128, // SHR_U_I64x2_S = 1608
15626 CEFBS_HasSIMD128, // SHR_U_I8x16 = 1609
15627 CEFBS_HasSIMD128, // SHR_U_I8x16_S = 1610
15628 CEFBS_HasSIMD128, // SHUFFLE = 1611
15629 CEFBS_HasSIMD128, // SHUFFLE_S = 1612
15630 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4 = 1613
15631 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F32x4_S = 1614
15632 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2 = 1615
15633 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMAX_F64x2_S = 1616
15634 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4 = 1617
15635 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F32x4_S = 1618
15636 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2 = 1619
15637 CEFBS_HasRelaxedSIMD, // SIMD_RELAXED_FMIN_F64x2_S = 1620
15638 CEFBS_HasHalfPrecision, // SPLAT_F16x8 = 1621
15639 CEFBS_HasHalfPrecision, // SPLAT_F16x8_S = 1622
15640 CEFBS_HasSIMD128, // SPLAT_F32x4 = 1623
15641 CEFBS_HasSIMD128, // SPLAT_F32x4_S = 1624
15642 CEFBS_HasSIMD128, // SPLAT_F64x2 = 1625
15643 CEFBS_HasSIMD128, // SPLAT_F64x2_S = 1626
15644 CEFBS_HasSIMD128, // SPLAT_I16x8 = 1627
15645 CEFBS_HasSIMD128, // SPLAT_I16x8_S = 1628
15646 CEFBS_HasSIMD128, // SPLAT_I32x4 = 1629
15647 CEFBS_HasSIMD128, // SPLAT_I32x4_S = 1630
15648 CEFBS_HasSIMD128, // SPLAT_I64x2 = 1631
15649 CEFBS_HasSIMD128, // SPLAT_I64x2_S = 1632
15650 CEFBS_HasSIMD128, // SPLAT_I8x16 = 1633
15651 CEFBS_HasSIMD128, // SPLAT_I8x16_S = 1634
15652 CEFBS_HasSIMD128_HasHalfPrecision, // SQRT_F16x8 = 1635
15653 CEFBS_HasSIMD128_HasHalfPrecision, // SQRT_F16x8_S = 1636
15654 CEFBS_None, // SQRT_F32 = 1637
15655 CEFBS_None, // SQRT_F32_S = 1638
15656 CEFBS_HasSIMD128, // SQRT_F32x4 = 1639
15657 CEFBS_HasSIMD128, // SQRT_F32x4_S = 1640
15658 CEFBS_None, // SQRT_F64 = 1641
15659 CEFBS_None, // SQRT_F64_S = 1642
15660 CEFBS_HasSIMD128, // SQRT_F64x2 = 1643
15661 CEFBS_HasSIMD128, // SQRT_F64x2_S = 1644
15662 CEFBS_None, // STORE16_I32_A32 = 1645
15663 CEFBS_None, // STORE16_I32_A32_S = 1646
15664 CEFBS_None, // STORE16_I32_A64 = 1647
15665 CEFBS_None, // STORE16_I32_A64_S = 1648
15666 CEFBS_None, // STORE16_I64_A32 = 1649
15667 CEFBS_None, // STORE16_I64_A32_S = 1650
15668 CEFBS_None, // STORE16_I64_A64 = 1651
15669 CEFBS_None, // STORE16_I64_A64_S = 1652
15670 CEFBS_None, // STORE32_I64_A32 = 1653
15671 CEFBS_None, // STORE32_I64_A32_S = 1654
15672 CEFBS_None, // STORE32_I64_A64 = 1655
15673 CEFBS_None, // STORE32_I64_A64_S = 1656
15674 CEFBS_None, // STORE8_I32_A32 = 1657
15675 CEFBS_None, // STORE8_I32_A32_S = 1658
15676 CEFBS_None, // STORE8_I32_A64 = 1659
15677 CEFBS_None, // STORE8_I32_A64_S = 1660
15678 CEFBS_None, // STORE8_I64_A32 = 1661
15679 CEFBS_None, // STORE8_I64_A32_S = 1662
15680 CEFBS_None, // STORE8_I64_A64 = 1663
15681 CEFBS_None, // STORE8_I64_A64_S = 1664
15682 CEFBS_HasHalfPrecision, // STORE_F16_F32_A32 = 1665
15683 CEFBS_HasHalfPrecision, // STORE_F16_F32_A32_S = 1666
15684 CEFBS_HasHalfPrecision, // STORE_F16_F32_A64 = 1667
15685 CEFBS_HasHalfPrecision, // STORE_F16_F32_A64_S = 1668
15686 CEFBS_None, // STORE_F32_A32 = 1669
15687 CEFBS_None, // STORE_F32_A32_S = 1670
15688 CEFBS_None, // STORE_F32_A64 = 1671
15689 CEFBS_None, // STORE_F32_A64_S = 1672
15690 CEFBS_None, // STORE_F64_A32 = 1673
15691 CEFBS_None, // STORE_F64_A32_S = 1674
15692 CEFBS_None, // STORE_F64_A64 = 1675
15693 CEFBS_None, // STORE_F64_A64_S = 1676
15694 CEFBS_None, // STORE_I32_A32 = 1677
15695 CEFBS_None, // STORE_I32_A32_S = 1678
15696 CEFBS_None, // STORE_I32_A64 = 1679
15697 CEFBS_None, // STORE_I32_A64_S = 1680
15698 CEFBS_None, // STORE_I64_A32 = 1681
15699 CEFBS_None, // STORE_I64_A32_S = 1682
15700 CEFBS_None, // STORE_I64_A64 = 1683
15701 CEFBS_None, // STORE_I64_A64_S = 1684
15702 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32 = 1685
15703 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A32_S = 1686
15704 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64 = 1687
15705 CEFBS_HasSIMD128, // STORE_LANE_I16x8_A64_S = 1688
15706 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32 = 1689
15707 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A32_S = 1690
15708 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64 = 1691
15709 CEFBS_HasSIMD128, // STORE_LANE_I32x4_A64_S = 1692
15710 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32 = 1693
15711 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A32_S = 1694
15712 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64 = 1695
15713 CEFBS_HasSIMD128, // STORE_LANE_I64x2_A64_S = 1696
15714 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32 = 1697
15715 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A32_S = 1698
15716 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64 = 1699
15717 CEFBS_HasSIMD128, // STORE_LANE_I8x16_A64_S = 1700
15718 CEFBS_HasSIMD128, // STORE_V128_A32 = 1701
15719 CEFBS_HasSIMD128, // STORE_V128_A32_S = 1702
15720 CEFBS_HasSIMD128, // STORE_V128_A64 = 1703
15721 CEFBS_HasSIMD128, // STORE_V128_A64_S = 1704
15722 CEFBS_HasSIMD128_HasHalfPrecision, // SUB_F16x8 = 1705
15723 CEFBS_HasSIMD128_HasHalfPrecision, // SUB_F16x8_S = 1706
15724 CEFBS_None, // SUB_F32 = 1707
15725 CEFBS_None, // SUB_F32_S = 1708
15726 CEFBS_HasSIMD128, // SUB_F32x4 = 1709
15727 CEFBS_HasSIMD128, // SUB_F32x4_S = 1710
15728 CEFBS_None, // SUB_F64 = 1711
15729 CEFBS_None, // SUB_F64_S = 1712
15730 CEFBS_HasSIMD128, // SUB_F64x2 = 1713
15731 CEFBS_HasSIMD128, // SUB_F64x2_S = 1714
15732 CEFBS_HasSIMD128, // SUB_I16x8 = 1715
15733 CEFBS_HasSIMD128, // SUB_I16x8_S = 1716
15734 CEFBS_None, // SUB_I32 = 1717
15735 CEFBS_None, // SUB_I32_S = 1718
15736 CEFBS_HasSIMD128, // SUB_I32x4 = 1719
15737 CEFBS_HasSIMD128, // SUB_I32x4_S = 1720
15738 CEFBS_None, // SUB_I64 = 1721
15739 CEFBS_None, // SUB_I64_S = 1722
15740 CEFBS_HasSIMD128, // SUB_I64x2 = 1723
15741 CEFBS_HasSIMD128, // SUB_I64x2_S = 1724
15742 CEFBS_HasSIMD128, // SUB_I8x16 = 1725
15743 CEFBS_HasSIMD128, // SUB_I8x16_S = 1726
15744 CEFBS_HasSIMD128, // SUB_SAT_S_I16x8 = 1727
15745 CEFBS_HasSIMD128, // SUB_SAT_S_I16x8_S = 1728
15746 CEFBS_HasSIMD128, // SUB_SAT_S_I8x16 = 1729
15747 CEFBS_HasSIMD128, // SUB_SAT_S_I8x16_S = 1730
15748 CEFBS_HasSIMD128, // SUB_SAT_U_I16x8 = 1731
15749 CEFBS_HasSIMD128, // SUB_SAT_U_I16x8_S = 1732
15750 CEFBS_HasSIMD128, // SUB_SAT_U_I8x16 = 1733
15751 CEFBS_HasSIMD128, // SUB_SAT_U_I8x16_S = 1734
15752 CEFBS_HasSIMD128, // SWIZZLE = 1735
15753 CEFBS_HasSIMD128, // SWIZZLE_S = 1736
15754 CEFBS_HasReferenceTypes, // TABLE_COPY = 1737
15755 CEFBS_HasReferenceTypes, // TABLE_COPY_S = 1738
15756 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF = 1739
15757 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_FILL_EXNREF_S = 1740
15758 CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF = 1741
15759 CEFBS_HasReferenceTypes, // TABLE_FILL_EXTERNREF_S = 1742
15760 CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF = 1743
15761 CEFBS_HasReferenceTypes, // TABLE_FILL_FUNCREF_S = 1744
15762 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF = 1745
15763 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GET_EXNREF_S = 1746
15764 CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF = 1747
15765 CEFBS_HasReferenceTypes, // TABLE_GET_EXTERNREF_S = 1748
15766 CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF = 1749
15767 CEFBS_HasReferenceTypes, // TABLE_GET_FUNCREF_S = 1750
15768 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF = 1751
15769 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_GROW_EXNREF_S = 1752
15770 CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF = 1753
15771 CEFBS_HasReferenceTypes, // TABLE_GROW_EXTERNREF_S = 1754
15772 CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF = 1755
15773 CEFBS_HasReferenceTypes, // TABLE_GROW_FUNCREF_S = 1756
15774 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF = 1757
15775 CEFBS_HasReferenceTypes_HasExceptionHandling, // TABLE_SET_EXNREF_S = 1758
15776 CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF = 1759
15777 CEFBS_HasReferenceTypes, // TABLE_SET_EXTERNREF_S = 1760
15778 CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF = 1761
15779 CEFBS_HasReferenceTypes, // TABLE_SET_FUNCREF_S = 1762
15780 CEFBS_HasReferenceTypes, // TABLE_SIZE = 1763
15781 CEFBS_HasReferenceTypes, // TABLE_SIZE_S = 1764
15782 CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF = 1765
15783 CEFBS_HasReferenceTypes_HasExceptionHandling, // TEE_EXNREF_S = 1766
15784 CEFBS_HasReferenceTypes, // TEE_EXTERNREF = 1767
15785 CEFBS_HasReferenceTypes, // TEE_EXTERNREF_S = 1768
15786 CEFBS_None, // TEE_F32 = 1769
15787 CEFBS_None, // TEE_F32_S = 1770
15788 CEFBS_None, // TEE_F64 = 1771
15789 CEFBS_None, // TEE_F64_S = 1772
15790 CEFBS_HasReferenceTypes, // TEE_FUNCREF = 1773
15791 CEFBS_HasReferenceTypes, // TEE_FUNCREF_S = 1774
15792 CEFBS_None, // TEE_I32 = 1775
15793 CEFBS_None, // TEE_I32_S = 1776
15794 CEFBS_None, // TEE_I64 = 1777
15795 CEFBS_None, // TEE_I64_S = 1778
15796 CEFBS_HasSIMD128, // TEE_V128 = 1779
15797 CEFBS_HasSIMD128, // TEE_V128_S = 1780
15798 CEFBS_HasExceptionHandling, // THROW = 1781
15799 CEFBS_HasExceptionHandling, // THROW_S = 1782
15800 CEFBS_HasSIMD128_HasHalfPrecision, // TRUNC_F16x8 = 1783
15801 CEFBS_HasSIMD128_HasHalfPrecision, // TRUNC_F16x8_S = 1784
15802 CEFBS_None, // TRUNC_F32 = 1785
15803 CEFBS_None, // TRUNC_F32_S = 1786
15804 CEFBS_HasSIMD128, // TRUNC_F32x4 = 1787
15805 CEFBS_HasSIMD128, // TRUNC_F32x4_S = 1788
15806 CEFBS_None, // TRUNC_F64 = 1789
15807 CEFBS_None, // TRUNC_F64_S = 1790
15808 CEFBS_HasSIMD128, // TRUNC_F64x2 = 1791
15809 CEFBS_HasSIMD128, // TRUNC_F64x2_S = 1792
15810 CEFBS_HasExceptionHandling, // TRY = 1793
15811 CEFBS_HasExceptionHandling, // TRY_S = 1794
15812 CEFBS_None, // UNREACHABLE = 1795
15813 CEFBS_None, // UNREACHABLE_S = 1796
15814 CEFBS_HasSIMD128, // XOR = 1797
15815 CEFBS_None, // XOR_I32 = 1798
15816 CEFBS_None, // XOR_I32_S = 1799
15817 CEFBS_None, // XOR_I64 = 1800
15818 CEFBS_None, // XOR_I64_S = 1801
15819 CEFBS_HasSIMD128, // XOR_S = 1802
15820 CEFBS_None, // anonymous_8187MEMORY_GROW_A32 = 1803
15821 CEFBS_None, // anonymous_8187MEMORY_GROW_A32_S = 1804
15822 CEFBS_None, // anonymous_8187MEMORY_SIZE_A32 = 1805
15823 CEFBS_None, // anonymous_8187MEMORY_SIZE_A32_S = 1806
15824 CEFBS_None, // anonymous_8188MEMORY_GROW_A64 = 1807
15825 CEFBS_None, // anonymous_8188MEMORY_GROW_A64_S = 1808
15826 CEFBS_None, // anonymous_8188MEMORY_SIZE_A64 = 1809
15827 CEFBS_None, // anonymous_8188MEMORY_SIZE_A64_S = 1810
15828 CEFBS_HasBulkMemory, // anonymous_8878DATA_DROP = 1811
15829 CEFBS_HasBulkMemory, // anonymous_8878DATA_DROP_S = 1812
15830 CEFBS_HasBulkMemory, // anonymous_8878MEMORY_COPY_A32 = 1813
15831 CEFBS_HasBulkMemory, // anonymous_8878MEMORY_COPY_A32_S = 1814
15832 CEFBS_HasBulkMemory, // anonymous_8878MEMORY_FILL_A32 = 1815
15833 CEFBS_HasBulkMemory, // anonymous_8878MEMORY_FILL_A32_S = 1816
15834 CEFBS_HasBulkMemory, // anonymous_8878MEMORY_INIT_A32 = 1817
15835 CEFBS_HasBulkMemory, // anonymous_8878MEMORY_INIT_A32_S = 1818
15836 CEFBS_HasBulkMemory, // anonymous_8879DATA_DROP = 1819
15837 CEFBS_HasBulkMemory, // anonymous_8879DATA_DROP_S = 1820
15838 CEFBS_HasBulkMemory, // anonymous_8879MEMORY_COPY_A64 = 1821
15839 CEFBS_HasBulkMemory, // anonymous_8879MEMORY_COPY_A64_S = 1822
15840 CEFBS_HasBulkMemory, // anonymous_8879MEMORY_FILL_A64 = 1823
15841 CEFBS_HasBulkMemory, // anonymous_8879MEMORY_FILL_A64_S = 1824
15842 CEFBS_HasBulkMemory, // anonymous_8879MEMORY_INIT_A64 = 1825
15843 CEFBS_HasBulkMemory, // anonymous_8879MEMORY_INIT_A64_S = 1826
15844 CEFBS_HasSIMD128, // convert_low_s_F64x2 = 1827
15845 CEFBS_HasSIMD128, // convert_low_s_F64x2_S = 1828
15846 CEFBS_HasSIMD128, // convert_low_u_F64x2 = 1829
15847 CEFBS_HasSIMD128, // convert_low_u_F64x2_S = 1830
15848 CEFBS_HasSIMD128, // demote_zero_F32x4 = 1831
15849 CEFBS_HasSIMD128, // demote_zero_F32x4_S = 1832
15850 CEFBS_HasSIMD128, // extend_high_s_I16x8 = 1833
15851 CEFBS_HasSIMD128, // extend_high_s_I16x8_S = 1834
15852 CEFBS_HasSIMD128, // extend_high_s_I32x4 = 1835
15853 CEFBS_HasSIMD128, // extend_high_s_I32x4_S = 1836
15854 CEFBS_HasSIMD128, // extend_high_s_I64x2 = 1837
15855 CEFBS_HasSIMD128, // extend_high_s_I64x2_S = 1838
15856 CEFBS_HasSIMD128, // extend_high_u_I16x8 = 1839
15857 CEFBS_HasSIMD128, // extend_high_u_I16x8_S = 1840
15858 CEFBS_HasSIMD128, // extend_high_u_I32x4 = 1841
15859 CEFBS_HasSIMD128, // extend_high_u_I32x4_S = 1842
15860 CEFBS_HasSIMD128, // extend_high_u_I64x2 = 1843
15861 CEFBS_HasSIMD128, // extend_high_u_I64x2_S = 1844
15862 CEFBS_HasSIMD128, // extend_low_s_I16x8 = 1845
15863 CEFBS_HasSIMD128, // extend_low_s_I16x8_S = 1846
15864 CEFBS_HasSIMD128, // extend_low_s_I32x4 = 1847
15865 CEFBS_HasSIMD128, // extend_low_s_I32x4_S = 1848
15866 CEFBS_HasSIMD128, // extend_low_s_I64x2 = 1849
15867 CEFBS_HasSIMD128, // extend_low_s_I64x2_S = 1850
15868 CEFBS_HasSIMD128, // extend_low_u_I16x8 = 1851
15869 CEFBS_HasSIMD128, // extend_low_u_I16x8_S = 1852
15870 CEFBS_HasSIMD128, // extend_low_u_I32x4 = 1853
15871 CEFBS_HasSIMD128, // extend_low_u_I32x4_S = 1854
15872 CEFBS_HasSIMD128, // extend_low_u_I64x2 = 1855
15873 CEFBS_HasSIMD128, // extend_low_u_I64x2_S = 1856
15874 CEFBS_HasSIMD128_HasHalfPrecision, // fp_to_sint_I16x8 = 1857
15875 CEFBS_HasSIMD128_HasHalfPrecision, // fp_to_sint_I16x8_S = 1858
15876 CEFBS_HasSIMD128, // fp_to_sint_I32x4 = 1859
15877 CEFBS_HasSIMD128, // fp_to_sint_I32x4_S = 1860
15878 CEFBS_HasSIMD128_HasHalfPrecision, // fp_to_uint_I16x8 = 1861
15879 CEFBS_HasSIMD128_HasHalfPrecision, // fp_to_uint_I16x8_S = 1862
15880 CEFBS_HasSIMD128, // fp_to_uint_I32x4 = 1863
15881 CEFBS_HasSIMD128, // fp_to_uint_I32x4_S = 1864
15882 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I16x8 = 1865
15883 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I16x8_S = 1866
15884 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I32x4 = 1867
15885 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_signed_I32x4_S = 1868
15886 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I16x8 = 1869
15887 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I16x8_S = 1870
15888 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I32x4 = 1871
15889 CEFBS_HasSIMD128, // int_wasm_extadd_pairwise_unsigned_I32x4_S = 1872
15890 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4 = 1873
15891 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_I32x4_S = 1874
15892 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4 = 1875
15893 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_signed_zero_I32x4_S = 1876
15894 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4 = 1877
15895 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_I32x4_S = 1878
15896 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4 = 1879
15897 CEFBS_HasRelaxedSIMD, // int_wasm_relaxed_trunc_unsigned_zero_I32x4_S = 1880
15898 CEFBS_HasSIMD128, // promote_low_F64x2 = 1881
15899 CEFBS_HasSIMD128, // promote_low_F64x2_S = 1882
15900 CEFBS_HasSIMD128_HasHalfPrecision, // sint_to_fp_F16x8 = 1883
15901 CEFBS_HasSIMD128_HasHalfPrecision, // sint_to_fp_F16x8_S = 1884
15902 CEFBS_HasSIMD128, // sint_to_fp_F32x4 = 1885
15903 CEFBS_HasSIMD128, // sint_to_fp_F32x4_S = 1886
15904 CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4 = 1887
15905 CEFBS_HasSIMD128, // trunc_sat_zero_s_I32x4_S = 1888
15906 CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4 = 1889
15907 CEFBS_HasSIMD128, // trunc_sat_zero_u_I32x4_S = 1890
15908 CEFBS_HasSIMD128_HasHalfPrecision, // uint_to_fp_F16x8 = 1891
15909 CEFBS_HasSIMD128_HasHalfPrecision, // uint_to_fp_F16x8_S = 1892
15910 CEFBS_HasSIMD128, // uint_to_fp_F32x4 = 1893
15911 CEFBS_HasSIMD128, // uint_to_fp_F32x4_S = 1894
15912 };
15913
15914 assert(Opcode < 1895);
15915 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
15916}
15917
15918} // end namespace WebAssembly_MC
15919} // end namespace llvm
15920#endif // GET_COMPUTE_FEATURES
15921
15922#ifdef GET_AVAILABLE_OPCODE_CHECKER
15923#undef GET_AVAILABLE_OPCODE_CHECKER
15924namespace llvm {
15925namespace WebAssembly_MC {
15926bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
15927 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
15928 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
15929 FeatureBitset MissingFeatures =
15930 (AvailableFeatures & RequiredFeatures) ^
15931 RequiredFeatures;
15932 return !MissingFeatures.any();
15933}
15934} // end namespace WebAssembly_MC
15935} // end namespace llvm
15936#endif // GET_AVAILABLE_OPCODE_CHECKER
15937
15938#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
15939#undef ENABLE_INSTR_PREDICATE_VERIFIER
15940#include <sstream>
15941
15942namespace llvm {
15943namespace WebAssembly_MC {
15944
15945#ifndef NDEBUG
15946static const char *SubtargetFeatureNames[] = {
15947 "Feature_HasAtomics",
15948 "Feature_HasBulkMemory",
15949 "Feature_HasExceptionHandling",
15950 "Feature_HasExtendedConst",
15951 "Feature_HasHalfPrecision",
15952 "Feature_HasMultiMemory",
15953 "Feature_HasMultivalue",
15954 "Feature_HasMutableGlobals",
15955 "Feature_HasNontrappingFPToInt",
15956 "Feature_HasReferenceTypes",
15957 "Feature_HasRelaxedSIMD",
15958 "Feature_HasSIMD128",
15959 "Feature_HasSignExt",
15960 "Feature_HasTailCall",
15961 "Feature_NotHasNontrappingFPToInt",
15962 nullptr
15963};
15964
15965#endif // NDEBUG
15966
15967void verifyInstructionPredicates(
15968 unsigned Opcode, const FeatureBitset &Features) {
15969#ifndef NDEBUG
15970 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
15971 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
15972 FeatureBitset MissingFeatures =
15973 (AvailableFeatures & RequiredFeatures) ^
15974 RequiredFeatures;
15975 if (MissingFeatures.any()) {
15976 std::ostringstream Msg;
15977 Msg << "Attempting to emit " << &WebAssemblyInstrNameData[WebAssemblyInstrNameIndices[Opcode]]
15978 << " instruction but the ";
15979 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
15980 if (MissingFeatures.test(i))
15981 Msg << SubtargetFeatureNames[i] << " ";
15982 Msg << "predicate(s) are not met";
15983 report_fatal_error(Msg.str().c_str());
15984 }
15985#endif // NDEBUG
15986}
15987} // end namespace WebAssembly_MC
15988} // end namespace llvm
15989#endif // ENABLE_INSTR_PREDICATE_VERIFIER
15990
15991#ifdef GET_INSTRMAP_INFO
15992#undef GET_INSTRMAP_INFO
15993namespace llvm {
15994
15995namespace WebAssembly {
15996
15997enum IsWasm64 {
15998 IsWasm64_1
15999};
16000
16001enum StackBased {
16002 StackBased_0,
16003 StackBased_1
16004};
16005
16006// getRegisterOpcode
16007LLVM_READONLY
16008int getRegisterOpcode(uint16_t Opcode) {
16009static const uint16_t getRegisterOpcodeTable[][2] = {
16010 { WebAssembly::CALL_PARAMS_S, WebAssembly::CALL_PARAMS },
16011 { WebAssembly::CALL_RESULTS_S, WebAssembly::CALL_RESULTS },
16012 { WebAssembly::CATCHRET_S, WebAssembly::CATCHRET },
16013 { WebAssembly::CLEANUPRET_S, WebAssembly::CLEANUPRET },
16014 { WebAssembly::COMPILER_FENCE_S, WebAssembly::COMPILER_FENCE },
16015 { WebAssembly::RET_CALL_RESULTS_S, WebAssembly::RET_CALL_RESULTS },
16016 { WebAssembly::ABS_F16x8_S, WebAssembly::ABS_F16x8 },
16017 { WebAssembly::ABS_F32_S, WebAssembly::ABS_F32 },
16018 { WebAssembly::ABS_F32x4_S, WebAssembly::ABS_F32x4 },
16019 { WebAssembly::ABS_F64_S, WebAssembly::ABS_F64 },
16020 { WebAssembly::ABS_F64x2_S, WebAssembly::ABS_F64x2 },
16021 { WebAssembly::ABS_I16x8_S, WebAssembly::ABS_I16x8 },
16022 { WebAssembly::ABS_I32x4_S, WebAssembly::ABS_I32x4 },
16023 { WebAssembly::ABS_I64x2_S, WebAssembly::ABS_I64x2 },
16024 { WebAssembly::ABS_I8x16_S, WebAssembly::ABS_I8x16 },
16025 { WebAssembly::ADD_F16x8_S, WebAssembly::ADD_F16x8 },
16026 { WebAssembly::ADD_F32_S, WebAssembly::ADD_F32 },
16027 { WebAssembly::ADD_F32x4_S, WebAssembly::ADD_F32x4 },
16028 { WebAssembly::ADD_F64_S, WebAssembly::ADD_F64 },
16029 { WebAssembly::ADD_F64x2_S, WebAssembly::ADD_F64x2 },
16030 { WebAssembly::ADD_I16x8_S, WebAssembly::ADD_I16x8 },
16031 { WebAssembly::ADD_I32_S, WebAssembly::ADD_I32 },
16032 { WebAssembly::ADD_I32x4_S, WebAssembly::ADD_I32x4 },
16033 { WebAssembly::ADD_I64_S, WebAssembly::ADD_I64 },
16034 { WebAssembly::ADD_I64x2_S, WebAssembly::ADD_I64x2 },
16035 { WebAssembly::ADD_I8x16_S, WebAssembly::ADD_I8x16 },
16036 { WebAssembly::ADD_SAT_S_I16x8_S, WebAssembly::ADD_SAT_S_I16x8 },
16037 { WebAssembly::ADD_SAT_S_I8x16_S, WebAssembly::ADD_SAT_S_I8x16 },
16038 { WebAssembly::ADD_SAT_U_I16x8_S, WebAssembly::ADD_SAT_U_I16x8 },
16039 { WebAssembly::ADD_SAT_U_I8x16_S, WebAssembly::ADD_SAT_U_I8x16 },
16040 { WebAssembly::ADJCALLSTACKDOWN_S, WebAssembly::ADJCALLSTACKDOWN },
16041 { WebAssembly::ADJCALLSTACKUP_S, WebAssembly::ADJCALLSTACKUP },
16042 { WebAssembly::ALLTRUE_I16x8_S, WebAssembly::ALLTRUE_I16x8 },
16043 { WebAssembly::ALLTRUE_I32x4_S, WebAssembly::ALLTRUE_I32x4 },
16044 { WebAssembly::ALLTRUE_I64x2_S, WebAssembly::ALLTRUE_I64x2 },
16045 { WebAssembly::ALLTRUE_I8x16_S, WebAssembly::ALLTRUE_I8x16 },
16046 { WebAssembly::ANDNOT_S, WebAssembly::ANDNOT },
16047 { WebAssembly::AND_I32_S, WebAssembly::AND_I32 },
16048 { WebAssembly::AND_I64_S, WebAssembly::AND_I64 },
16049 { WebAssembly::AND_S, WebAssembly::AND },
16050 { WebAssembly::ANYTRUE_S, WebAssembly::ANYTRUE },
16051 { WebAssembly::ARGUMENT_exnref_S, WebAssembly::ARGUMENT_exnref },
16052 { WebAssembly::ARGUMENT_externref_S, WebAssembly::ARGUMENT_externref },
16053 { WebAssembly::ARGUMENT_f32_S, WebAssembly::ARGUMENT_f32 },
16054 { WebAssembly::ARGUMENT_f64_S, WebAssembly::ARGUMENT_f64 },
16055 { WebAssembly::ARGUMENT_funcref_S, WebAssembly::ARGUMENT_funcref },
16056 { WebAssembly::ARGUMENT_i32_S, WebAssembly::ARGUMENT_i32 },
16057 { WebAssembly::ARGUMENT_i64_S, WebAssembly::ARGUMENT_i64 },
16058 { WebAssembly::ARGUMENT_v16i8_S, WebAssembly::ARGUMENT_v16i8 },
16059 { WebAssembly::ARGUMENT_v2f64_S, WebAssembly::ARGUMENT_v2f64 },
16060 { WebAssembly::ARGUMENT_v2i64_S, WebAssembly::ARGUMENT_v2i64 },
16061 { WebAssembly::ARGUMENT_v4f32_S, WebAssembly::ARGUMENT_v4f32 },
16062 { WebAssembly::ARGUMENT_v4i32_S, WebAssembly::ARGUMENT_v4i32 },
16063 { WebAssembly::ARGUMENT_v8f16_S, WebAssembly::ARGUMENT_v8f16 },
16064 { WebAssembly::ARGUMENT_v8i16_S, WebAssembly::ARGUMENT_v8i16 },
16065 { WebAssembly::ATOMIC_FENCE_S, WebAssembly::ATOMIC_FENCE },
16066 { WebAssembly::ATOMIC_LOAD16_U_I32_A32_S, WebAssembly::ATOMIC_LOAD16_U_I32_A32 },
16067 { WebAssembly::ATOMIC_LOAD16_U_I32_A64_S, WebAssembly::ATOMIC_LOAD16_U_I32_A64 },
16068 { WebAssembly::ATOMIC_LOAD16_U_I64_A32_S, WebAssembly::ATOMIC_LOAD16_U_I64_A32 },
16069 { WebAssembly::ATOMIC_LOAD16_U_I64_A64_S, WebAssembly::ATOMIC_LOAD16_U_I64_A64 },
16070 { WebAssembly::ATOMIC_LOAD32_U_I64_A32_S, WebAssembly::ATOMIC_LOAD32_U_I64_A32 },
16071 { WebAssembly::ATOMIC_LOAD32_U_I64_A64_S, WebAssembly::ATOMIC_LOAD32_U_I64_A64 },
16072 { WebAssembly::ATOMIC_LOAD8_U_I32_A32_S, WebAssembly::ATOMIC_LOAD8_U_I32_A32 },
16073 { WebAssembly::ATOMIC_LOAD8_U_I32_A64_S, WebAssembly::ATOMIC_LOAD8_U_I32_A64 },
16074 { WebAssembly::ATOMIC_LOAD8_U_I64_A32_S, WebAssembly::ATOMIC_LOAD8_U_I64_A32 },
16075 { WebAssembly::ATOMIC_LOAD8_U_I64_A64_S, WebAssembly::ATOMIC_LOAD8_U_I64_A64 },
16076 { WebAssembly::ATOMIC_LOAD_I32_A32_S, WebAssembly::ATOMIC_LOAD_I32_A32 },
16077 { WebAssembly::ATOMIC_LOAD_I32_A64_S, WebAssembly::ATOMIC_LOAD_I32_A64 },
16078 { WebAssembly::ATOMIC_LOAD_I64_A32_S, WebAssembly::ATOMIC_LOAD_I64_A32 },
16079 { WebAssembly::ATOMIC_LOAD_I64_A64_S, WebAssembly::ATOMIC_LOAD_I64_A64 },
16080 { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32 },
16081 { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64 },
16082 { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32 },
16083 { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64 },
16084 { WebAssembly::ATOMIC_RMW16_U_AND_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_AND_I32_A32 },
16085 { WebAssembly::ATOMIC_RMW16_U_AND_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_AND_I32_A64 },
16086 { WebAssembly::ATOMIC_RMW16_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_AND_I64_A32 },
16087 { WebAssembly::ATOMIC_RMW16_U_AND_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_AND_I64_A64 },
16088 { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32 },
16089 { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64 },
16090 { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32 },
16091 { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64 },
16092 { WebAssembly::ATOMIC_RMW16_U_OR_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_OR_I32_A32 },
16093 { WebAssembly::ATOMIC_RMW16_U_OR_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_OR_I32_A64 },
16094 { WebAssembly::ATOMIC_RMW16_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_OR_I64_A32 },
16095 { WebAssembly::ATOMIC_RMW16_U_OR_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_OR_I64_A64 },
16096 { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32 },
16097 { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64 },
16098 { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32 },
16099 { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64 },
16100 { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32 },
16101 { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64 },
16102 { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32 },
16103 { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64 },
16104 { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32 },
16105 { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64_S, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64 },
16106 { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32 },
16107 { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64_S, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64 },
16108 { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32 },
16109 { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64 },
16110 { WebAssembly::ATOMIC_RMW32_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_AND_I64_A32 },
16111 { WebAssembly::ATOMIC_RMW32_U_AND_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_AND_I64_A64 },
16112 { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32 },
16113 { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64 },
16114 { WebAssembly::ATOMIC_RMW32_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_OR_I64_A32 },
16115 { WebAssembly::ATOMIC_RMW32_U_OR_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_OR_I64_A64 },
16116 { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32 },
16117 { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64 },
16118 { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32 },
16119 { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64 },
16120 { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32 },
16121 { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64_S, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64 },
16122 { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32 },
16123 { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64 },
16124 { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32 },
16125 { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64 },
16126 { WebAssembly::ATOMIC_RMW8_U_AND_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_AND_I32_A32 },
16127 { WebAssembly::ATOMIC_RMW8_U_AND_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_AND_I32_A64 },
16128 { WebAssembly::ATOMIC_RMW8_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_AND_I64_A32 },
16129 { WebAssembly::ATOMIC_RMW8_U_AND_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_AND_I64_A64 },
16130 { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32 },
16131 { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64 },
16132 { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32 },
16133 { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64 },
16134 { WebAssembly::ATOMIC_RMW8_U_OR_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_OR_I32_A32 },
16135 { WebAssembly::ATOMIC_RMW8_U_OR_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_OR_I32_A64 },
16136 { WebAssembly::ATOMIC_RMW8_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_OR_I64_A32 },
16137 { WebAssembly::ATOMIC_RMW8_U_OR_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_OR_I64_A64 },
16138 { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32 },
16139 { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64 },
16140 { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32 },
16141 { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64 },
16142 { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32 },
16143 { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64 },
16144 { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32 },
16145 { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64 },
16146 { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32 },
16147 { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64_S, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64 },
16148 { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32 },
16149 { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64_S, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64 },
16150 { WebAssembly::ATOMIC_RMW_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW_ADD_I32_A32 },
16151 { WebAssembly::ATOMIC_RMW_ADD_I32_A64_S, WebAssembly::ATOMIC_RMW_ADD_I32_A64 },
16152 { WebAssembly::ATOMIC_RMW_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW_ADD_I64_A32 },
16153 { WebAssembly::ATOMIC_RMW_ADD_I64_A64_S, WebAssembly::ATOMIC_RMW_ADD_I64_A64 },
16154 { WebAssembly::ATOMIC_RMW_AND_I32_A32_S, WebAssembly::ATOMIC_RMW_AND_I32_A32 },
16155 { WebAssembly::ATOMIC_RMW_AND_I32_A64_S, WebAssembly::ATOMIC_RMW_AND_I32_A64 },
16156 { WebAssembly::ATOMIC_RMW_AND_I64_A32_S, WebAssembly::ATOMIC_RMW_AND_I64_A32 },
16157 { WebAssembly::ATOMIC_RMW_AND_I64_A64_S, WebAssembly::ATOMIC_RMW_AND_I64_A64 },
16158 { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32 },
16159 { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64 },
16160 { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32 },
16161 { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64 },
16162 { WebAssembly::ATOMIC_RMW_OR_I32_A32_S, WebAssembly::ATOMIC_RMW_OR_I32_A32 },
16163 { WebAssembly::ATOMIC_RMW_OR_I32_A64_S, WebAssembly::ATOMIC_RMW_OR_I32_A64 },
16164 { WebAssembly::ATOMIC_RMW_OR_I64_A32_S, WebAssembly::ATOMIC_RMW_OR_I64_A32 },
16165 { WebAssembly::ATOMIC_RMW_OR_I64_A64_S, WebAssembly::ATOMIC_RMW_OR_I64_A64 },
16166 { WebAssembly::ATOMIC_RMW_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW_SUB_I32_A32 },
16167 { WebAssembly::ATOMIC_RMW_SUB_I32_A64_S, WebAssembly::ATOMIC_RMW_SUB_I32_A64 },
16168 { WebAssembly::ATOMIC_RMW_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW_SUB_I64_A32 },
16169 { WebAssembly::ATOMIC_RMW_SUB_I64_A64_S, WebAssembly::ATOMIC_RMW_SUB_I64_A64 },
16170 { WebAssembly::ATOMIC_RMW_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW_XCHG_I32_A32 },
16171 { WebAssembly::ATOMIC_RMW_XCHG_I32_A64_S, WebAssembly::ATOMIC_RMW_XCHG_I32_A64 },
16172 { WebAssembly::ATOMIC_RMW_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW_XCHG_I64_A32 },
16173 { WebAssembly::ATOMIC_RMW_XCHG_I64_A64_S, WebAssembly::ATOMIC_RMW_XCHG_I64_A64 },
16174 { WebAssembly::ATOMIC_RMW_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW_XOR_I32_A32 },
16175 { WebAssembly::ATOMIC_RMW_XOR_I32_A64_S, WebAssembly::ATOMIC_RMW_XOR_I32_A64 },
16176 { WebAssembly::ATOMIC_RMW_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW_XOR_I64_A32 },
16177 { WebAssembly::ATOMIC_RMW_XOR_I64_A64_S, WebAssembly::ATOMIC_RMW_XOR_I64_A64 },
16178 { WebAssembly::ATOMIC_STORE16_I32_A32_S, WebAssembly::ATOMIC_STORE16_I32_A32 },
16179 { WebAssembly::ATOMIC_STORE16_I32_A64_S, WebAssembly::ATOMIC_STORE16_I32_A64 },
16180 { WebAssembly::ATOMIC_STORE16_I64_A32_S, WebAssembly::ATOMIC_STORE16_I64_A32 },
16181 { WebAssembly::ATOMIC_STORE16_I64_A64_S, WebAssembly::ATOMIC_STORE16_I64_A64 },
16182 { WebAssembly::ATOMIC_STORE32_I64_A32_S, WebAssembly::ATOMIC_STORE32_I64_A32 },
16183 { WebAssembly::ATOMIC_STORE32_I64_A64_S, WebAssembly::ATOMIC_STORE32_I64_A64 },
16184 { WebAssembly::ATOMIC_STORE8_I32_A32_S, WebAssembly::ATOMIC_STORE8_I32_A32 },
16185 { WebAssembly::ATOMIC_STORE8_I32_A64_S, WebAssembly::ATOMIC_STORE8_I32_A64 },
16186 { WebAssembly::ATOMIC_STORE8_I64_A32_S, WebAssembly::ATOMIC_STORE8_I64_A32 },
16187 { WebAssembly::ATOMIC_STORE8_I64_A64_S, WebAssembly::ATOMIC_STORE8_I64_A64 },
16188 { WebAssembly::ATOMIC_STORE_I32_A32_S, WebAssembly::ATOMIC_STORE_I32_A32 },
16189 { WebAssembly::ATOMIC_STORE_I32_A64_S, WebAssembly::ATOMIC_STORE_I32_A64 },
16190 { WebAssembly::ATOMIC_STORE_I64_A32_S, WebAssembly::ATOMIC_STORE_I64_A32 },
16191 { WebAssembly::ATOMIC_STORE_I64_A64_S, WebAssembly::ATOMIC_STORE_I64_A64 },
16192 { WebAssembly::AVGR_U_I16x8_S, WebAssembly::AVGR_U_I16x8 },
16193 { WebAssembly::AVGR_U_I8x16_S, WebAssembly::AVGR_U_I8x16 },
16194 { WebAssembly::BITMASK_I16x8_S, WebAssembly::BITMASK_I16x8 },
16195 { WebAssembly::BITMASK_I32x4_S, WebAssembly::BITMASK_I32x4 },
16196 { WebAssembly::BITMASK_I64x2_S, WebAssembly::BITMASK_I64x2 },
16197 { WebAssembly::BITMASK_I8x16_S, WebAssembly::BITMASK_I8x16 },
16198 { WebAssembly::BITSELECT_S, WebAssembly::BITSELECT },
16199 { WebAssembly::BLOCK_S, WebAssembly::BLOCK },
16200 { WebAssembly::BR_IF_S, WebAssembly::BR_IF },
16201 { WebAssembly::BR_S, WebAssembly::BR },
16202 { WebAssembly::BR_TABLE_I32_S, WebAssembly::BR_TABLE_I32 },
16203 { WebAssembly::BR_TABLE_I64_S, WebAssembly::BR_TABLE_I64 },
16204 { WebAssembly::BR_UNLESS_S, WebAssembly::BR_UNLESS },
16205 { WebAssembly::CALL_INDIRECT_S, WebAssembly::CALL_INDIRECT },
16206 { WebAssembly::CALL_S, WebAssembly::CALL },
16207 { WebAssembly::CATCH_ALL_S, WebAssembly::CATCH_ALL },
16208 { WebAssembly::CATCH_S, WebAssembly::CATCH },
16209 { WebAssembly::CEIL_F16x8_S, WebAssembly::CEIL_F16x8 },
16210 { WebAssembly::CEIL_F32_S, WebAssembly::CEIL_F32 },
16211 { WebAssembly::CEIL_F32x4_S, WebAssembly::CEIL_F32x4 },
16212 { WebAssembly::CEIL_F64_S, WebAssembly::CEIL_F64 },
16213 { WebAssembly::CEIL_F64x2_S, WebAssembly::CEIL_F64x2 },
16214 { WebAssembly::CLZ_I32_S, WebAssembly::CLZ_I32 },
16215 { WebAssembly::CLZ_I64_S, WebAssembly::CLZ_I64 },
16216 { WebAssembly::CONST_F32_S, WebAssembly::CONST_F32 },
16217 { WebAssembly::CONST_F64_S, WebAssembly::CONST_F64 },
16218 { WebAssembly::CONST_I32_S, WebAssembly::CONST_I32 },
16219 { WebAssembly::CONST_I64_S, WebAssembly::CONST_I64 },
16220 { WebAssembly::CONST_V128_F32x4_S, WebAssembly::CONST_V128_F32x4 },
16221 { WebAssembly::CONST_V128_F64x2_S, WebAssembly::CONST_V128_F64x2 },
16222 { WebAssembly::CONST_V128_I16x8_S, WebAssembly::CONST_V128_I16x8 },
16223 { WebAssembly::CONST_V128_I32x4_S, WebAssembly::CONST_V128_I32x4 },
16224 { WebAssembly::CONST_V128_I64x2_S, WebAssembly::CONST_V128_I64x2 },
16225 { WebAssembly::CONST_V128_I8x16_S, WebAssembly::CONST_V128_I8x16 },
16226 { WebAssembly::COPYSIGN_F32_S, WebAssembly::COPYSIGN_F32 },
16227 { WebAssembly::COPYSIGN_F64_S, WebAssembly::COPYSIGN_F64 },
16228 { WebAssembly::COPY_EXNREF_S, WebAssembly::COPY_EXNREF },
16229 { WebAssembly::COPY_EXTERNREF_S, WebAssembly::COPY_EXTERNREF },
16230 { WebAssembly::COPY_F32_S, WebAssembly::COPY_F32 },
16231 { WebAssembly::COPY_F64_S, WebAssembly::COPY_F64 },
16232 { WebAssembly::COPY_FUNCREF_S, WebAssembly::COPY_FUNCREF },
16233 { WebAssembly::COPY_I32_S, WebAssembly::COPY_I32 },
16234 { WebAssembly::COPY_I64_S, WebAssembly::COPY_I64 },
16235 { WebAssembly::COPY_V128_S, WebAssembly::COPY_V128 },
16236 { WebAssembly::CTZ_I32_S, WebAssembly::CTZ_I32 },
16237 { WebAssembly::CTZ_I64_S, WebAssembly::CTZ_I64 },
16238 { WebAssembly::DEBUG_UNREACHABLE_S, WebAssembly::DEBUG_UNREACHABLE },
16239 { WebAssembly::DELEGATE_S, WebAssembly::DELEGATE },
16240 { WebAssembly::DIV_F16x8_S, WebAssembly::DIV_F16x8 },
16241 { WebAssembly::DIV_F32_S, WebAssembly::DIV_F32 },
16242 { WebAssembly::DIV_F32x4_S, WebAssembly::DIV_F32x4 },
16243 { WebAssembly::DIV_F64_S, WebAssembly::DIV_F64 },
16244 { WebAssembly::DIV_F64x2_S, WebAssembly::DIV_F64x2 },
16245 { WebAssembly::DIV_S_I32_S, WebAssembly::DIV_S_I32 },
16246 { WebAssembly::DIV_S_I64_S, WebAssembly::DIV_S_I64 },
16247 { WebAssembly::DIV_U_I32_S, WebAssembly::DIV_U_I32 },
16248 { WebAssembly::DIV_U_I64_S, WebAssembly::DIV_U_I64 },
16249 { WebAssembly::DOT_S, WebAssembly::DOT },
16250 { WebAssembly::DROP_EXNREF_S, WebAssembly::DROP_EXNREF },
16251 { WebAssembly::DROP_EXTERNREF_S, WebAssembly::DROP_EXTERNREF },
16252 { WebAssembly::DROP_F32_S, WebAssembly::DROP_F32 },
16253 { WebAssembly::DROP_F64_S, WebAssembly::DROP_F64 },
16254 { WebAssembly::DROP_FUNCREF_S, WebAssembly::DROP_FUNCREF },
16255 { WebAssembly::DROP_I32_S, WebAssembly::DROP_I32 },
16256 { WebAssembly::DROP_I64_S, WebAssembly::DROP_I64 },
16257 { WebAssembly::DROP_V128_S, WebAssembly::DROP_V128 },
16258 { WebAssembly::ELSE_S, WebAssembly::ELSE },
16259 { WebAssembly::END_BLOCK_S, WebAssembly::END_BLOCK },
16260 { WebAssembly::END_FUNCTION_S, WebAssembly::END_FUNCTION },
16261 { WebAssembly::END_IF_S, WebAssembly::END_IF },
16262 { WebAssembly::END_LOOP_S, WebAssembly::END_LOOP },
16263 { WebAssembly::END_S, WebAssembly::END },
16264 { WebAssembly::END_TRY_S, WebAssembly::END_TRY },
16265 { WebAssembly::EQZ_I32_S, WebAssembly::EQZ_I32 },
16266 { WebAssembly::EQZ_I64_S, WebAssembly::EQZ_I64 },
16267 { WebAssembly::EQ_F16x8_S, WebAssembly::EQ_F16x8 },
16268 { WebAssembly::EQ_F32_S, WebAssembly::EQ_F32 },
16269 { WebAssembly::EQ_F32x4_S, WebAssembly::EQ_F32x4 },
16270 { WebAssembly::EQ_F64_S, WebAssembly::EQ_F64 },
16271 { WebAssembly::EQ_F64x2_S, WebAssembly::EQ_F64x2 },
16272 { WebAssembly::EQ_I16x8_S, WebAssembly::EQ_I16x8 },
16273 { WebAssembly::EQ_I32_S, WebAssembly::EQ_I32 },
16274 { WebAssembly::EQ_I32x4_S, WebAssembly::EQ_I32x4 },
16275 { WebAssembly::EQ_I64_S, WebAssembly::EQ_I64 },
16276 { WebAssembly::EQ_I64x2_S, WebAssembly::EQ_I64x2 },
16277 { WebAssembly::EQ_I8x16_S, WebAssembly::EQ_I8x16 },
16278 { WebAssembly::EXTMUL_HIGH_S_I16x8_S, WebAssembly::EXTMUL_HIGH_S_I16x8 },
16279 { WebAssembly::EXTMUL_HIGH_S_I32x4_S, WebAssembly::EXTMUL_HIGH_S_I32x4 },
16280 { WebAssembly::EXTMUL_HIGH_S_I64x2_S, WebAssembly::EXTMUL_HIGH_S_I64x2 },
16281 { WebAssembly::EXTMUL_HIGH_U_I16x8_S, WebAssembly::EXTMUL_HIGH_U_I16x8 },
16282 { WebAssembly::EXTMUL_HIGH_U_I32x4_S, WebAssembly::EXTMUL_HIGH_U_I32x4 },
16283 { WebAssembly::EXTMUL_HIGH_U_I64x2_S, WebAssembly::EXTMUL_HIGH_U_I64x2 },
16284 { WebAssembly::EXTMUL_LOW_S_I16x8_S, WebAssembly::EXTMUL_LOW_S_I16x8 },
16285 { WebAssembly::EXTMUL_LOW_S_I32x4_S, WebAssembly::EXTMUL_LOW_S_I32x4 },
16286 { WebAssembly::EXTMUL_LOW_S_I64x2_S, WebAssembly::EXTMUL_LOW_S_I64x2 },
16287 { WebAssembly::EXTMUL_LOW_U_I16x8_S, WebAssembly::EXTMUL_LOW_U_I16x8 },
16288 { WebAssembly::EXTMUL_LOW_U_I32x4_S, WebAssembly::EXTMUL_LOW_U_I32x4 },
16289 { WebAssembly::EXTMUL_LOW_U_I64x2_S, WebAssembly::EXTMUL_LOW_U_I64x2 },
16290 { WebAssembly::EXTRACT_LANE_F16x8_S, WebAssembly::EXTRACT_LANE_F16x8 },
16291 { WebAssembly::EXTRACT_LANE_F32x4_S, WebAssembly::EXTRACT_LANE_F32x4 },
16292 { WebAssembly::EXTRACT_LANE_F64x2_S, WebAssembly::EXTRACT_LANE_F64x2 },
16293 { WebAssembly::EXTRACT_LANE_I16x8_s_S, WebAssembly::EXTRACT_LANE_I16x8_s },
16294 { WebAssembly::EXTRACT_LANE_I16x8_u_S, WebAssembly::EXTRACT_LANE_I16x8_u },
16295 { WebAssembly::EXTRACT_LANE_I32x4_S, WebAssembly::EXTRACT_LANE_I32x4 },
16296 { WebAssembly::EXTRACT_LANE_I64x2_S, WebAssembly::EXTRACT_LANE_I64x2 },
16297 { WebAssembly::EXTRACT_LANE_I8x16_s_S, WebAssembly::EXTRACT_LANE_I8x16_s },
16298 { WebAssembly::EXTRACT_LANE_I8x16_u_S, WebAssembly::EXTRACT_LANE_I8x16_u },
16299 { WebAssembly::F32_CONVERT_S_I32_S, WebAssembly::F32_CONVERT_S_I32 },
16300 { WebAssembly::F32_CONVERT_S_I64_S, WebAssembly::F32_CONVERT_S_I64 },
16301 { WebAssembly::F32_CONVERT_U_I32_S, WebAssembly::F32_CONVERT_U_I32 },
16302 { WebAssembly::F32_CONVERT_U_I64_S, WebAssembly::F32_CONVERT_U_I64 },
16303 { WebAssembly::F32_DEMOTE_F64_S, WebAssembly::F32_DEMOTE_F64 },
16304 { WebAssembly::F32_REINTERPRET_I32_S, WebAssembly::F32_REINTERPRET_I32 },
16305 { WebAssembly::F64_CONVERT_S_I32_S, WebAssembly::F64_CONVERT_S_I32 },
16306 { WebAssembly::F64_CONVERT_S_I64_S, WebAssembly::F64_CONVERT_S_I64 },
16307 { WebAssembly::F64_CONVERT_U_I32_S, WebAssembly::F64_CONVERT_U_I32 },
16308 { WebAssembly::F64_CONVERT_U_I64_S, WebAssembly::F64_CONVERT_U_I64 },
16309 { WebAssembly::F64_PROMOTE_F32_S, WebAssembly::F64_PROMOTE_F32 },
16310 { WebAssembly::F64_REINTERPRET_I64_S, WebAssembly::F64_REINTERPRET_I64 },
16311 { WebAssembly::FALLTHROUGH_RETURN_S, WebAssembly::FALLTHROUGH_RETURN },
16312 { WebAssembly::FLOOR_F16x8_S, WebAssembly::FLOOR_F16x8 },
16313 { WebAssembly::FLOOR_F32_S, WebAssembly::FLOOR_F32 },
16314 { WebAssembly::FLOOR_F32x4_S, WebAssembly::FLOOR_F32x4 },
16315 { WebAssembly::FLOOR_F64_S, WebAssembly::FLOOR_F64 },
16316 { WebAssembly::FLOOR_F64x2_S, WebAssembly::FLOOR_F64x2 },
16317 { WebAssembly::FP_TO_SINT_I32_F32_S, WebAssembly::FP_TO_SINT_I32_F32 },
16318 { WebAssembly::FP_TO_SINT_I32_F64_S, WebAssembly::FP_TO_SINT_I32_F64 },
16319 { WebAssembly::FP_TO_SINT_I64_F32_S, WebAssembly::FP_TO_SINT_I64_F32 },
16320 { WebAssembly::FP_TO_SINT_I64_F64_S, WebAssembly::FP_TO_SINT_I64_F64 },
16321 { WebAssembly::FP_TO_UINT_I32_F32_S, WebAssembly::FP_TO_UINT_I32_F32 },
16322 { WebAssembly::FP_TO_UINT_I32_F64_S, WebAssembly::FP_TO_UINT_I32_F64 },
16323 { WebAssembly::FP_TO_UINT_I64_F32_S, WebAssembly::FP_TO_UINT_I64_F32 },
16324 { WebAssembly::FP_TO_UINT_I64_F64_S, WebAssembly::FP_TO_UINT_I64_F64 },
16325 { WebAssembly::GE_F16x8_S, WebAssembly::GE_F16x8 },
16326 { WebAssembly::GE_F32_S, WebAssembly::GE_F32 },
16327 { WebAssembly::GE_F32x4_S, WebAssembly::GE_F32x4 },
16328 { WebAssembly::GE_F64_S, WebAssembly::GE_F64 },
16329 { WebAssembly::GE_F64x2_S, WebAssembly::GE_F64x2 },
16330 { WebAssembly::GE_S_I16x8_S, WebAssembly::GE_S_I16x8 },
16331 { WebAssembly::GE_S_I32_S, WebAssembly::GE_S_I32 },
16332 { WebAssembly::GE_S_I32x4_S, WebAssembly::GE_S_I32x4 },
16333 { WebAssembly::GE_S_I64_S, WebAssembly::GE_S_I64 },
16334 { WebAssembly::GE_S_I64x2_S, WebAssembly::GE_S_I64x2 },
16335 { WebAssembly::GE_S_I8x16_S, WebAssembly::GE_S_I8x16 },
16336 { WebAssembly::GE_U_I16x8_S, WebAssembly::GE_U_I16x8 },
16337 { WebAssembly::GE_U_I32_S, WebAssembly::GE_U_I32 },
16338 { WebAssembly::GE_U_I32x4_S, WebAssembly::GE_U_I32x4 },
16339 { WebAssembly::GE_U_I64_S, WebAssembly::GE_U_I64 },
16340 { WebAssembly::GE_U_I8x16_S, WebAssembly::GE_U_I8x16 },
16341 { WebAssembly::GLOBAL_GET_EXNREF_S, WebAssembly::GLOBAL_GET_EXNREF },
16342 { WebAssembly::GLOBAL_GET_EXTERNREF_S, WebAssembly::GLOBAL_GET_EXTERNREF },
16343 { WebAssembly::GLOBAL_GET_F32_S, WebAssembly::GLOBAL_GET_F32 },
16344 { WebAssembly::GLOBAL_GET_F64_S, WebAssembly::GLOBAL_GET_F64 },
16345 { WebAssembly::GLOBAL_GET_FUNCREF_S, WebAssembly::GLOBAL_GET_FUNCREF },
16346 { WebAssembly::GLOBAL_GET_I32_S, WebAssembly::GLOBAL_GET_I32 },
16347 { WebAssembly::GLOBAL_GET_I64_S, WebAssembly::GLOBAL_GET_I64 },
16348 { WebAssembly::GLOBAL_GET_V128_S, WebAssembly::GLOBAL_GET_V128 },
16349 { WebAssembly::GLOBAL_SET_EXNREF_S, WebAssembly::GLOBAL_SET_EXNREF },
16350 { WebAssembly::GLOBAL_SET_EXTERNREF_S, WebAssembly::GLOBAL_SET_EXTERNREF },
16351 { WebAssembly::GLOBAL_SET_F32_S, WebAssembly::GLOBAL_SET_F32 },
16352 { WebAssembly::GLOBAL_SET_F64_S, WebAssembly::GLOBAL_SET_F64 },
16353 { WebAssembly::GLOBAL_SET_FUNCREF_S, WebAssembly::GLOBAL_SET_FUNCREF },
16354 { WebAssembly::GLOBAL_SET_I32_S, WebAssembly::GLOBAL_SET_I32 },
16355 { WebAssembly::GLOBAL_SET_I64_S, WebAssembly::GLOBAL_SET_I64 },
16356 { WebAssembly::GLOBAL_SET_V128_S, WebAssembly::GLOBAL_SET_V128 },
16357 { WebAssembly::GT_F16x8_S, WebAssembly::GT_F16x8 },
16358 { WebAssembly::GT_F32_S, WebAssembly::GT_F32 },
16359 { WebAssembly::GT_F32x4_S, WebAssembly::GT_F32x4 },
16360 { WebAssembly::GT_F64_S, WebAssembly::GT_F64 },
16361 { WebAssembly::GT_F64x2_S, WebAssembly::GT_F64x2 },
16362 { WebAssembly::GT_S_I16x8_S, WebAssembly::GT_S_I16x8 },
16363 { WebAssembly::GT_S_I32_S, WebAssembly::GT_S_I32 },
16364 { WebAssembly::GT_S_I32x4_S, WebAssembly::GT_S_I32x4 },
16365 { WebAssembly::GT_S_I64_S, WebAssembly::GT_S_I64 },
16366 { WebAssembly::GT_S_I64x2_S, WebAssembly::GT_S_I64x2 },
16367 { WebAssembly::GT_S_I8x16_S, WebAssembly::GT_S_I8x16 },
16368 { WebAssembly::GT_U_I16x8_S, WebAssembly::GT_U_I16x8 },
16369 { WebAssembly::GT_U_I32_S, WebAssembly::GT_U_I32 },
16370 { WebAssembly::GT_U_I32x4_S, WebAssembly::GT_U_I32x4 },
16371 { WebAssembly::GT_U_I64_S, WebAssembly::GT_U_I64 },
16372 { WebAssembly::GT_U_I8x16_S, WebAssembly::GT_U_I8x16 },
16373 { WebAssembly::I32_EXTEND16_S_I32_S, WebAssembly::I32_EXTEND16_S_I32 },
16374 { WebAssembly::I32_EXTEND8_S_I32_S, WebAssembly::I32_EXTEND8_S_I32 },
16375 { WebAssembly::I32_REINTERPRET_F32_S, WebAssembly::I32_REINTERPRET_F32 },
16376 { WebAssembly::I32_TRUNC_S_F32_S, WebAssembly::I32_TRUNC_S_F32 },
16377 { WebAssembly::I32_TRUNC_S_F64_S, WebAssembly::I32_TRUNC_S_F64 },
16378 { WebAssembly::I32_TRUNC_S_SAT_F32_S, WebAssembly::I32_TRUNC_S_SAT_F32 },
16379 { WebAssembly::I32_TRUNC_S_SAT_F64_S, WebAssembly::I32_TRUNC_S_SAT_F64 },
16380 { WebAssembly::I32_TRUNC_U_F32_S, WebAssembly::I32_TRUNC_U_F32 },
16381 { WebAssembly::I32_TRUNC_U_F64_S, WebAssembly::I32_TRUNC_U_F64 },
16382 { WebAssembly::I32_TRUNC_U_SAT_F32_S, WebAssembly::I32_TRUNC_U_SAT_F32 },
16383 { WebAssembly::I32_TRUNC_U_SAT_F64_S, WebAssembly::I32_TRUNC_U_SAT_F64 },
16384 { WebAssembly::I32_WRAP_I64_S, WebAssembly::I32_WRAP_I64 },
16385 { WebAssembly::I64_EXTEND16_S_I64_S, WebAssembly::I64_EXTEND16_S_I64 },
16386 { WebAssembly::I64_EXTEND32_S_I64_S, WebAssembly::I64_EXTEND32_S_I64 },
16387 { WebAssembly::I64_EXTEND8_S_I64_S, WebAssembly::I64_EXTEND8_S_I64 },
16388 { WebAssembly::I64_EXTEND_S_I32_S, WebAssembly::I64_EXTEND_S_I32 },
16389 { WebAssembly::I64_EXTEND_U_I32_S, WebAssembly::I64_EXTEND_U_I32 },
16390 { WebAssembly::I64_REINTERPRET_F64_S, WebAssembly::I64_REINTERPRET_F64 },
16391 { WebAssembly::I64_TRUNC_S_F32_S, WebAssembly::I64_TRUNC_S_F32 },
16392 { WebAssembly::I64_TRUNC_S_F64_S, WebAssembly::I64_TRUNC_S_F64 },
16393 { WebAssembly::I64_TRUNC_S_SAT_F32_S, WebAssembly::I64_TRUNC_S_SAT_F32 },
16394 { WebAssembly::I64_TRUNC_S_SAT_F64_S, WebAssembly::I64_TRUNC_S_SAT_F64 },
16395 { WebAssembly::I64_TRUNC_U_F32_S, WebAssembly::I64_TRUNC_U_F32 },
16396 { WebAssembly::I64_TRUNC_U_F64_S, WebAssembly::I64_TRUNC_U_F64 },
16397 { WebAssembly::I64_TRUNC_U_SAT_F32_S, WebAssembly::I64_TRUNC_U_SAT_F32 },
16398 { WebAssembly::I64_TRUNC_U_SAT_F64_S, WebAssembly::I64_TRUNC_U_SAT_F64 },
16399 { WebAssembly::IF_S, WebAssembly::IF },
16400 { WebAssembly::LANESELECT_I16x8_S, WebAssembly::LANESELECT_I16x8 },
16401 { WebAssembly::LANESELECT_I32x4_S, WebAssembly::LANESELECT_I32x4 },
16402 { WebAssembly::LANESELECT_I64x2_S, WebAssembly::LANESELECT_I64x2 },
16403 { WebAssembly::LANESELECT_I8x16_S, WebAssembly::LANESELECT_I8x16 },
16404 { WebAssembly::LE_F16x8_S, WebAssembly::LE_F16x8 },
16405 { WebAssembly::LE_F32_S, WebAssembly::LE_F32 },
16406 { WebAssembly::LE_F32x4_S, WebAssembly::LE_F32x4 },
16407 { WebAssembly::LE_F64_S, WebAssembly::LE_F64 },
16408 { WebAssembly::LE_F64x2_S, WebAssembly::LE_F64x2 },
16409 { WebAssembly::LE_S_I16x8_S, WebAssembly::LE_S_I16x8 },
16410 { WebAssembly::LE_S_I32_S, WebAssembly::LE_S_I32 },
16411 { WebAssembly::LE_S_I32x4_S, WebAssembly::LE_S_I32x4 },
16412 { WebAssembly::LE_S_I64_S, WebAssembly::LE_S_I64 },
16413 { WebAssembly::LE_S_I64x2_S, WebAssembly::LE_S_I64x2 },
16414 { WebAssembly::LE_S_I8x16_S, WebAssembly::LE_S_I8x16 },
16415 { WebAssembly::LE_U_I16x8_S, WebAssembly::LE_U_I16x8 },
16416 { WebAssembly::LE_U_I32_S, WebAssembly::LE_U_I32 },
16417 { WebAssembly::LE_U_I32x4_S, WebAssembly::LE_U_I32x4 },
16418 { WebAssembly::LE_U_I64_S, WebAssembly::LE_U_I64 },
16419 { WebAssembly::LE_U_I8x16_S, WebAssembly::LE_U_I8x16 },
16420 { WebAssembly::LOAD16_SPLAT_A32_S, WebAssembly::LOAD16_SPLAT_A32 },
16421 { WebAssembly::LOAD16_SPLAT_A64_S, WebAssembly::LOAD16_SPLAT_A64 },
16422 { WebAssembly::LOAD16_S_I32_A32_S, WebAssembly::LOAD16_S_I32_A32 },
16423 { WebAssembly::LOAD16_S_I32_A64_S, WebAssembly::LOAD16_S_I32_A64 },
16424 { WebAssembly::LOAD16_S_I64_A32_S, WebAssembly::LOAD16_S_I64_A32 },
16425 { WebAssembly::LOAD16_S_I64_A64_S, WebAssembly::LOAD16_S_I64_A64 },
16426 { WebAssembly::LOAD16_U_I32_A32_S, WebAssembly::LOAD16_U_I32_A32 },
16427 { WebAssembly::LOAD16_U_I32_A64_S, WebAssembly::LOAD16_U_I32_A64 },
16428 { WebAssembly::LOAD16_U_I64_A32_S, WebAssembly::LOAD16_U_I64_A32 },
16429 { WebAssembly::LOAD16_U_I64_A64_S, WebAssembly::LOAD16_U_I64_A64 },
16430 { WebAssembly::LOAD32_SPLAT_A32_S, WebAssembly::LOAD32_SPLAT_A32 },
16431 { WebAssembly::LOAD32_SPLAT_A64_S, WebAssembly::LOAD32_SPLAT_A64 },
16432 { WebAssembly::LOAD32_S_I64_A32_S, WebAssembly::LOAD32_S_I64_A32 },
16433 { WebAssembly::LOAD32_S_I64_A64_S, WebAssembly::LOAD32_S_I64_A64 },
16434 { WebAssembly::LOAD32_U_I64_A32_S, WebAssembly::LOAD32_U_I64_A32 },
16435 { WebAssembly::LOAD32_U_I64_A64_S, WebAssembly::LOAD32_U_I64_A64 },
16436 { WebAssembly::LOAD64_SPLAT_A32_S, WebAssembly::LOAD64_SPLAT_A32 },
16437 { WebAssembly::LOAD64_SPLAT_A64_S, WebAssembly::LOAD64_SPLAT_A64 },
16438 { WebAssembly::LOAD8_SPLAT_A32_S, WebAssembly::LOAD8_SPLAT_A32 },
16439 { WebAssembly::LOAD8_SPLAT_A64_S, WebAssembly::LOAD8_SPLAT_A64 },
16440 { WebAssembly::LOAD8_S_I32_A32_S, WebAssembly::LOAD8_S_I32_A32 },
16441 { WebAssembly::LOAD8_S_I32_A64_S, WebAssembly::LOAD8_S_I32_A64 },
16442 { WebAssembly::LOAD8_S_I64_A32_S, WebAssembly::LOAD8_S_I64_A32 },
16443 { WebAssembly::LOAD8_S_I64_A64_S, WebAssembly::LOAD8_S_I64_A64 },
16444 { WebAssembly::LOAD8_U_I32_A32_S, WebAssembly::LOAD8_U_I32_A32 },
16445 { WebAssembly::LOAD8_U_I32_A64_S, WebAssembly::LOAD8_U_I32_A64 },
16446 { WebAssembly::LOAD8_U_I64_A32_S, WebAssembly::LOAD8_U_I64_A32 },
16447 { WebAssembly::LOAD8_U_I64_A64_S, WebAssembly::LOAD8_U_I64_A64 },
16448 { WebAssembly::LOAD_EXTEND_S_I16x8_A32_S, WebAssembly::LOAD_EXTEND_S_I16x8_A32 },
16449 { WebAssembly::LOAD_EXTEND_S_I16x8_A64_S, WebAssembly::LOAD_EXTEND_S_I16x8_A64 },
16450 { WebAssembly::LOAD_EXTEND_S_I32x4_A32_S, WebAssembly::LOAD_EXTEND_S_I32x4_A32 },
16451 { WebAssembly::LOAD_EXTEND_S_I32x4_A64_S, WebAssembly::LOAD_EXTEND_S_I32x4_A64 },
16452 { WebAssembly::LOAD_EXTEND_S_I64x2_A32_S, WebAssembly::LOAD_EXTEND_S_I64x2_A32 },
16453 { WebAssembly::LOAD_EXTEND_S_I64x2_A64_S, WebAssembly::LOAD_EXTEND_S_I64x2_A64 },
16454 { WebAssembly::LOAD_EXTEND_U_I16x8_A32_S, WebAssembly::LOAD_EXTEND_U_I16x8_A32 },
16455 { WebAssembly::LOAD_EXTEND_U_I16x8_A64_S, WebAssembly::LOAD_EXTEND_U_I16x8_A64 },
16456 { WebAssembly::LOAD_EXTEND_U_I32x4_A32_S, WebAssembly::LOAD_EXTEND_U_I32x4_A32 },
16457 { WebAssembly::LOAD_EXTEND_U_I32x4_A64_S, WebAssembly::LOAD_EXTEND_U_I32x4_A64 },
16458 { WebAssembly::LOAD_EXTEND_U_I64x2_A32_S, WebAssembly::LOAD_EXTEND_U_I64x2_A32 },
16459 { WebAssembly::LOAD_EXTEND_U_I64x2_A64_S, WebAssembly::LOAD_EXTEND_U_I64x2_A64 },
16460 { WebAssembly::LOAD_F16_F32_A32_S, WebAssembly::LOAD_F16_F32_A32 },
16461 { WebAssembly::LOAD_F16_F32_A64_S, WebAssembly::LOAD_F16_F32_A64 },
16462 { WebAssembly::LOAD_F32_A32_S, WebAssembly::LOAD_F32_A32 },
16463 { WebAssembly::LOAD_F32_A64_S, WebAssembly::LOAD_F32_A64 },
16464 { WebAssembly::LOAD_F64_A32_S, WebAssembly::LOAD_F64_A32 },
16465 { WebAssembly::LOAD_F64_A64_S, WebAssembly::LOAD_F64_A64 },
16466 { WebAssembly::LOAD_I32_A32_S, WebAssembly::LOAD_I32_A32 },
16467 { WebAssembly::LOAD_I32_A64_S, WebAssembly::LOAD_I32_A64 },
16468 { WebAssembly::LOAD_I64_A32_S, WebAssembly::LOAD_I64_A32 },
16469 { WebAssembly::LOAD_I64_A64_S, WebAssembly::LOAD_I64_A64 },
16470 { WebAssembly::LOAD_LANE_I16x8_A32_S, WebAssembly::LOAD_LANE_I16x8_A32 },
16471 { WebAssembly::LOAD_LANE_I16x8_A64_S, WebAssembly::LOAD_LANE_I16x8_A64 },
16472 { WebAssembly::LOAD_LANE_I32x4_A32_S, WebAssembly::LOAD_LANE_I32x4_A32 },
16473 { WebAssembly::LOAD_LANE_I32x4_A64_S, WebAssembly::LOAD_LANE_I32x4_A64 },
16474 { WebAssembly::LOAD_LANE_I64x2_A32_S, WebAssembly::LOAD_LANE_I64x2_A32 },
16475 { WebAssembly::LOAD_LANE_I64x2_A64_S, WebAssembly::LOAD_LANE_I64x2_A64 },
16476 { WebAssembly::LOAD_LANE_I8x16_A32_S, WebAssembly::LOAD_LANE_I8x16_A32 },
16477 { WebAssembly::LOAD_LANE_I8x16_A64_S, WebAssembly::LOAD_LANE_I8x16_A64 },
16478 { WebAssembly::LOAD_V128_A32_S, WebAssembly::LOAD_V128_A32 },
16479 { WebAssembly::LOAD_V128_A64_S, WebAssembly::LOAD_V128_A64 },
16480 { WebAssembly::LOAD_ZERO_I32x4_A32_S, WebAssembly::LOAD_ZERO_I32x4_A32 },
16481 { WebAssembly::LOAD_ZERO_I32x4_A64_S, WebAssembly::LOAD_ZERO_I32x4_A64 },
16482 { WebAssembly::LOAD_ZERO_I64x2_A32_S, WebAssembly::LOAD_ZERO_I64x2_A32 },
16483 { WebAssembly::LOAD_ZERO_I64x2_A64_S, WebAssembly::LOAD_ZERO_I64x2_A64 },
16484 { WebAssembly::LOCAL_GET_EXNREF_S, WebAssembly::LOCAL_GET_EXNREF },
16485 { WebAssembly::LOCAL_GET_EXTERNREF_S, WebAssembly::LOCAL_GET_EXTERNREF },
16486 { WebAssembly::LOCAL_GET_F32_S, WebAssembly::LOCAL_GET_F32 },
16487 { WebAssembly::LOCAL_GET_F64_S, WebAssembly::LOCAL_GET_F64 },
16488 { WebAssembly::LOCAL_GET_FUNCREF_S, WebAssembly::LOCAL_GET_FUNCREF },
16489 { WebAssembly::LOCAL_GET_I32_S, WebAssembly::LOCAL_GET_I32 },
16490 { WebAssembly::LOCAL_GET_I64_S, WebAssembly::LOCAL_GET_I64 },
16491 { WebAssembly::LOCAL_GET_V128_S, WebAssembly::LOCAL_GET_V128 },
16492 { WebAssembly::LOCAL_SET_EXNREF_S, WebAssembly::LOCAL_SET_EXNREF },
16493 { WebAssembly::LOCAL_SET_EXTERNREF_S, WebAssembly::LOCAL_SET_EXTERNREF },
16494 { WebAssembly::LOCAL_SET_F32_S, WebAssembly::LOCAL_SET_F32 },
16495 { WebAssembly::LOCAL_SET_F64_S, WebAssembly::LOCAL_SET_F64 },
16496 { WebAssembly::LOCAL_SET_FUNCREF_S, WebAssembly::LOCAL_SET_FUNCREF },
16497 { WebAssembly::LOCAL_SET_I32_S, WebAssembly::LOCAL_SET_I32 },
16498 { WebAssembly::LOCAL_SET_I64_S, WebAssembly::LOCAL_SET_I64 },
16499 { WebAssembly::LOCAL_SET_V128_S, WebAssembly::LOCAL_SET_V128 },
16500 { WebAssembly::LOCAL_TEE_EXNREF_S, WebAssembly::LOCAL_TEE_EXNREF },
16501 { WebAssembly::LOCAL_TEE_EXTERNREF_S, WebAssembly::LOCAL_TEE_EXTERNREF },
16502 { WebAssembly::LOCAL_TEE_F32_S, WebAssembly::LOCAL_TEE_F32 },
16503 { WebAssembly::LOCAL_TEE_F64_S, WebAssembly::LOCAL_TEE_F64 },
16504 { WebAssembly::LOCAL_TEE_FUNCREF_S, WebAssembly::LOCAL_TEE_FUNCREF },
16505 { WebAssembly::LOCAL_TEE_I32_S, WebAssembly::LOCAL_TEE_I32 },
16506 { WebAssembly::LOCAL_TEE_I64_S, WebAssembly::LOCAL_TEE_I64 },
16507 { WebAssembly::LOCAL_TEE_V128_S, WebAssembly::LOCAL_TEE_V128 },
16508 { WebAssembly::LOOP_S, WebAssembly::LOOP },
16509 { WebAssembly::LT_F16x8_S, WebAssembly::LT_F16x8 },
16510 { WebAssembly::LT_F32_S, WebAssembly::LT_F32 },
16511 { WebAssembly::LT_F32x4_S, WebAssembly::LT_F32x4 },
16512 { WebAssembly::LT_F64_S, WebAssembly::LT_F64 },
16513 { WebAssembly::LT_F64x2_S, WebAssembly::LT_F64x2 },
16514 { WebAssembly::LT_S_I16x8_S, WebAssembly::LT_S_I16x8 },
16515 { WebAssembly::LT_S_I32_S, WebAssembly::LT_S_I32 },
16516 { WebAssembly::LT_S_I32x4_S, WebAssembly::LT_S_I32x4 },
16517 { WebAssembly::LT_S_I64_S, WebAssembly::LT_S_I64 },
16518 { WebAssembly::LT_S_I64x2_S, WebAssembly::LT_S_I64x2 },
16519 { WebAssembly::LT_S_I8x16_S, WebAssembly::LT_S_I8x16 },
16520 { WebAssembly::LT_U_I16x8_S, WebAssembly::LT_U_I16x8 },
16521 { WebAssembly::LT_U_I32_S, WebAssembly::LT_U_I32 },
16522 { WebAssembly::LT_U_I32x4_S, WebAssembly::LT_U_I32x4 },
16523 { WebAssembly::LT_U_I64_S, WebAssembly::LT_U_I64 },
16524 { WebAssembly::LT_U_I8x16_S, WebAssembly::LT_U_I8x16 },
16525 { WebAssembly::MADD_F16x8_S, WebAssembly::MADD_F16x8 },
16526 { WebAssembly::MADD_F32x4_S, WebAssembly::MADD_F32x4 },
16527 { WebAssembly::MADD_F64x2_S, WebAssembly::MADD_F64x2 },
16528 { WebAssembly::MAX_F16x8_S, WebAssembly::MAX_F16x8 },
16529 { WebAssembly::MAX_F32_S, WebAssembly::MAX_F32 },
16530 { WebAssembly::MAX_F32x4_S, WebAssembly::MAX_F32x4 },
16531 { WebAssembly::MAX_F64_S, WebAssembly::MAX_F64 },
16532 { WebAssembly::MAX_F64x2_S, WebAssembly::MAX_F64x2 },
16533 { WebAssembly::MAX_S_I16x8_S, WebAssembly::MAX_S_I16x8 },
16534 { WebAssembly::MAX_S_I32x4_S, WebAssembly::MAX_S_I32x4 },
16535 { WebAssembly::MAX_S_I8x16_S, WebAssembly::MAX_S_I8x16 },
16536 { WebAssembly::MAX_U_I16x8_S, WebAssembly::MAX_U_I16x8 },
16537 { WebAssembly::MAX_U_I32x4_S, WebAssembly::MAX_U_I32x4 },
16538 { WebAssembly::MAX_U_I8x16_S, WebAssembly::MAX_U_I8x16 },
16539 { WebAssembly::MEMORY_ATOMIC_NOTIFY_A32_S, WebAssembly::MEMORY_ATOMIC_NOTIFY_A32 },
16540 { WebAssembly::MEMORY_ATOMIC_NOTIFY_A64_S, WebAssembly::MEMORY_ATOMIC_NOTIFY_A64 },
16541 { WebAssembly::MEMORY_ATOMIC_WAIT32_A32_S, WebAssembly::MEMORY_ATOMIC_WAIT32_A32 },
16542 { WebAssembly::MEMORY_ATOMIC_WAIT32_A64_S, WebAssembly::MEMORY_ATOMIC_WAIT32_A64 },
16543 { WebAssembly::MEMORY_ATOMIC_WAIT64_A32_S, WebAssembly::MEMORY_ATOMIC_WAIT64_A32 },
16544 { WebAssembly::MEMORY_ATOMIC_WAIT64_A64_S, WebAssembly::MEMORY_ATOMIC_WAIT64_A64 },
16545 { WebAssembly::MIN_F16x8_S, WebAssembly::MIN_F16x8 },
16546 { WebAssembly::MIN_F32_S, WebAssembly::MIN_F32 },
16547 { WebAssembly::MIN_F32x4_S, WebAssembly::MIN_F32x4 },
16548 { WebAssembly::MIN_F64_S, WebAssembly::MIN_F64 },
16549 { WebAssembly::MIN_F64x2_S, WebAssembly::MIN_F64x2 },
16550 { WebAssembly::MIN_S_I16x8_S, WebAssembly::MIN_S_I16x8 },
16551 { WebAssembly::MIN_S_I32x4_S, WebAssembly::MIN_S_I32x4 },
16552 { WebAssembly::MIN_S_I8x16_S, WebAssembly::MIN_S_I8x16 },
16553 { WebAssembly::MIN_U_I16x8_S, WebAssembly::MIN_U_I16x8 },
16554 { WebAssembly::MIN_U_I32x4_S, WebAssembly::MIN_U_I32x4 },
16555 { WebAssembly::MIN_U_I8x16_S, WebAssembly::MIN_U_I8x16 },
16556 { WebAssembly::MUL_F16x8_S, WebAssembly::MUL_F16x8 },
16557 { WebAssembly::MUL_F32_S, WebAssembly::MUL_F32 },
16558 { WebAssembly::MUL_F32x4_S, WebAssembly::MUL_F32x4 },
16559 { WebAssembly::MUL_F64_S, WebAssembly::MUL_F64 },
16560 { WebAssembly::MUL_F64x2_S, WebAssembly::MUL_F64x2 },
16561 { WebAssembly::MUL_I16x8_S, WebAssembly::MUL_I16x8 },
16562 { WebAssembly::MUL_I32_S, WebAssembly::MUL_I32 },
16563 { WebAssembly::MUL_I32x4_S, WebAssembly::MUL_I32x4 },
16564 { WebAssembly::MUL_I64_S, WebAssembly::MUL_I64 },
16565 { WebAssembly::MUL_I64x2_S, WebAssembly::MUL_I64x2 },
16566 { WebAssembly::NARROW_S_I16x8_S, WebAssembly::NARROW_S_I16x8 },
16567 { WebAssembly::NARROW_S_I8x16_S, WebAssembly::NARROW_S_I8x16 },
16568 { WebAssembly::NARROW_U_I16x8_S, WebAssembly::NARROW_U_I16x8 },
16569 { WebAssembly::NARROW_U_I8x16_S, WebAssembly::NARROW_U_I8x16 },
16570 { WebAssembly::NEAREST_F16x8_S, WebAssembly::NEAREST_F16x8 },
16571 { WebAssembly::NEAREST_F32_S, WebAssembly::NEAREST_F32 },
16572 { WebAssembly::NEAREST_F32x4_S, WebAssembly::NEAREST_F32x4 },
16573 { WebAssembly::NEAREST_F64_S, WebAssembly::NEAREST_F64 },
16574 { WebAssembly::NEAREST_F64x2_S, WebAssembly::NEAREST_F64x2 },
16575 { WebAssembly::NEG_F16x8_S, WebAssembly::NEG_F16x8 },
16576 { WebAssembly::NEG_F32_S, WebAssembly::NEG_F32 },
16577 { WebAssembly::NEG_F32x4_S, WebAssembly::NEG_F32x4 },
16578 { WebAssembly::NEG_F64_S, WebAssembly::NEG_F64 },
16579 { WebAssembly::NEG_F64x2_S, WebAssembly::NEG_F64x2 },
16580 { WebAssembly::NEG_I16x8_S, WebAssembly::NEG_I16x8 },
16581 { WebAssembly::NEG_I32x4_S, WebAssembly::NEG_I32x4 },
16582 { WebAssembly::NEG_I64x2_S, WebAssembly::NEG_I64x2 },
16583 { WebAssembly::NEG_I8x16_S, WebAssembly::NEG_I8x16 },
16584 { WebAssembly::NE_F16x8_S, WebAssembly::NE_F16x8 },
16585 { WebAssembly::NE_F32_S, WebAssembly::NE_F32 },
16586 { WebAssembly::NE_F32x4_S, WebAssembly::NE_F32x4 },
16587 { WebAssembly::NE_F64_S, WebAssembly::NE_F64 },
16588 { WebAssembly::NE_F64x2_S, WebAssembly::NE_F64x2 },
16589 { WebAssembly::NE_I16x8_S, WebAssembly::NE_I16x8 },
16590 { WebAssembly::NE_I32_S, WebAssembly::NE_I32 },
16591 { WebAssembly::NE_I32x4_S, WebAssembly::NE_I32x4 },
16592 { WebAssembly::NE_I64_S, WebAssembly::NE_I64 },
16593 { WebAssembly::NE_I64x2_S, WebAssembly::NE_I64x2 },
16594 { WebAssembly::NE_I8x16_S, WebAssembly::NE_I8x16 },
16595 { WebAssembly::NMADD_F16x8_S, WebAssembly::NMADD_F16x8 },
16596 { WebAssembly::NMADD_F32x4_S, WebAssembly::NMADD_F32x4 },
16597 { WebAssembly::NMADD_F64x2_S, WebAssembly::NMADD_F64x2 },
16598 { WebAssembly::NOP_S, WebAssembly::NOP },
16599 { WebAssembly::NOT_S, WebAssembly::NOT },
16600 { WebAssembly::OR_I32_S, WebAssembly::OR_I32 },
16601 { WebAssembly::OR_I64_S, WebAssembly::OR_I64 },
16602 { WebAssembly::OR_S, WebAssembly::OR },
16603 { WebAssembly::PMAX_F16x8_S, WebAssembly::PMAX_F16x8 },
16604 { WebAssembly::PMAX_F32x4_S, WebAssembly::PMAX_F32x4 },
16605 { WebAssembly::PMAX_F64x2_S, WebAssembly::PMAX_F64x2 },
16606 { WebAssembly::PMIN_F16x8_S, WebAssembly::PMIN_F16x8 },
16607 { WebAssembly::PMIN_F32x4_S, WebAssembly::PMIN_F32x4 },
16608 { WebAssembly::PMIN_F64x2_S, WebAssembly::PMIN_F64x2 },
16609 { WebAssembly::POPCNT_I32_S, WebAssembly::POPCNT_I32 },
16610 { WebAssembly::POPCNT_I64_S, WebAssembly::POPCNT_I64 },
16611 { WebAssembly::POPCNT_I8x16_S, WebAssembly::POPCNT_I8x16 },
16612 { WebAssembly::Q15MULR_SAT_S_I16x8_S, WebAssembly::Q15MULR_SAT_S_I16x8 },
16613 { WebAssembly::REF_IS_NULL_EXNREF_S, WebAssembly::REF_IS_NULL_EXNREF },
16614 { WebAssembly::REF_IS_NULL_EXTERNREF_S, WebAssembly::REF_IS_NULL_EXTERNREF },
16615 { WebAssembly::REF_IS_NULL_FUNCREF_S, WebAssembly::REF_IS_NULL_FUNCREF },
16616 { WebAssembly::REF_NULL_EXNREF_S, WebAssembly::REF_NULL_EXNREF },
16617 { WebAssembly::REF_NULL_EXTERNREF_S, WebAssembly::REF_NULL_EXTERNREF },
16618 { WebAssembly::REF_NULL_FUNCREF_S, WebAssembly::REF_NULL_FUNCREF },
16619 { WebAssembly::RELAXED_DOT_ADD_S, WebAssembly::RELAXED_DOT_ADD },
16620 { WebAssembly::RELAXED_DOT_BFLOAT_S, WebAssembly::RELAXED_DOT_BFLOAT },
16621 { WebAssembly::RELAXED_DOT_S, WebAssembly::RELAXED_DOT },
16622 { WebAssembly::RELAXED_Q15MULR_S_I16x8_S, WebAssembly::RELAXED_Q15MULR_S_I16x8 },
16623 { WebAssembly::RELAXED_SWIZZLE_S, WebAssembly::RELAXED_SWIZZLE },
16624 { WebAssembly::REM_S_I32_S, WebAssembly::REM_S_I32 },
16625 { WebAssembly::REM_S_I64_S, WebAssembly::REM_S_I64 },
16626 { WebAssembly::REM_U_I32_S, WebAssembly::REM_U_I32 },
16627 { WebAssembly::REM_U_I64_S, WebAssembly::REM_U_I64 },
16628 { WebAssembly::REPLACE_LANE_F32x4_S, WebAssembly::REPLACE_LANE_F32x4 },
16629 { WebAssembly::REPLACE_LANE_F64x2_S, WebAssembly::REPLACE_LANE_F64x2 },
16630 { WebAssembly::REPLACE_LANE_I16x8_S, WebAssembly::REPLACE_LANE_I16x8 },
16631 { WebAssembly::REPLACE_LANE_I32x4_S, WebAssembly::REPLACE_LANE_I32x4 },
16632 { WebAssembly::REPLACE_LANE_I64x2_S, WebAssembly::REPLACE_LANE_I64x2 },
16633 { WebAssembly::REPLACE_LANE_I8x16_S, WebAssembly::REPLACE_LANE_I8x16 },
16634 { WebAssembly::RETHROW_S, WebAssembly::RETHROW },
16635 { WebAssembly::RETURN_S, WebAssembly::RETURN },
16636 { WebAssembly::RET_CALL_INDIRECT_S, WebAssembly::RET_CALL_INDIRECT },
16637 { WebAssembly::RET_CALL_S, WebAssembly::RET_CALL },
16638 { WebAssembly::ROTL_I32_S, WebAssembly::ROTL_I32 },
16639 { WebAssembly::ROTL_I64_S, WebAssembly::ROTL_I64 },
16640 { WebAssembly::ROTR_I32_S, WebAssembly::ROTR_I32 },
16641 { WebAssembly::ROTR_I64_S, WebAssembly::ROTR_I64 },
16642 { WebAssembly::SELECT_EXNREF_S, WebAssembly::SELECT_EXNREF },
16643 { WebAssembly::SELECT_EXTERNREF_S, WebAssembly::SELECT_EXTERNREF },
16644 { WebAssembly::SELECT_F32_S, WebAssembly::SELECT_F32 },
16645 { WebAssembly::SELECT_F64_S, WebAssembly::SELECT_F64 },
16646 { WebAssembly::SELECT_FUNCREF_S, WebAssembly::SELECT_FUNCREF },
16647 { WebAssembly::SELECT_I32_S, WebAssembly::SELECT_I32 },
16648 { WebAssembly::SELECT_I64_S, WebAssembly::SELECT_I64 },
16649 { WebAssembly::SELECT_V128_S, WebAssembly::SELECT_V128 },
16650 { WebAssembly::SHL_I16x8_S, WebAssembly::SHL_I16x8 },
16651 { WebAssembly::SHL_I32_S, WebAssembly::SHL_I32 },
16652 { WebAssembly::SHL_I32x4_S, WebAssembly::SHL_I32x4 },
16653 { WebAssembly::SHL_I64_S, WebAssembly::SHL_I64 },
16654 { WebAssembly::SHL_I64x2_S, WebAssembly::SHL_I64x2 },
16655 { WebAssembly::SHL_I8x16_S, WebAssembly::SHL_I8x16 },
16656 { WebAssembly::SHR_S_I16x8_S, WebAssembly::SHR_S_I16x8 },
16657 { WebAssembly::SHR_S_I32_S, WebAssembly::SHR_S_I32 },
16658 { WebAssembly::SHR_S_I32x4_S, WebAssembly::SHR_S_I32x4 },
16659 { WebAssembly::SHR_S_I64_S, WebAssembly::SHR_S_I64 },
16660 { WebAssembly::SHR_S_I64x2_S, WebAssembly::SHR_S_I64x2 },
16661 { WebAssembly::SHR_S_I8x16_S, WebAssembly::SHR_S_I8x16 },
16662 { WebAssembly::SHR_U_I16x8_S, WebAssembly::SHR_U_I16x8 },
16663 { WebAssembly::SHR_U_I32_S, WebAssembly::SHR_U_I32 },
16664 { WebAssembly::SHR_U_I32x4_S, WebAssembly::SHR_U_I32x4 },
16665 { WebAssembly::SHR_U_I64_S, WebAssembly::SHR_U_I64 },
16666 { WebAssembly::SHR_U_I64x2_S, WebAssembly::SHR_U_I64x2 },
16667 { WebAssembly::SHR_U_I8x16_S, WebAssembly::SHR_U_I8x16 },
16668 { WebAssembly::SHUFFLE_S, WebAssembly::SHUFFLE },
16669 { WebAssembly::SIMD_RELAXED_FMAX_F32x4_S, WebAssembly::SIMD_RELAXED_FMAX_F32x4 },
16670 { WebAssembly::SIMD_RELAXED_FMAX_F64x2_S, WebAssembly::SIMD_RELAXED_FMAX_F64x2 },
16671 { WebAssembly::SIMD_RELAXED_FMIN_F32x4_S, WebAssembly::SIMD_RELAXED_FMIN_F32x4 },
16672 { WebAssembly::SIMD_RELAXED_FMIN_F64x2_S, WebAssembly::SIMD_RELAXED_FMIN_F64x2 },
16673 { WebAssembly::SPLAT_F16x8_S, WebAssembly::SPLAT_F16x8 },
16674 { WebAssembly::SPLAT_F32x4_S, WebAssembly::SPLAT_F32x4 },
16675 { WebAssembly::SPLAT_F64x2_S, WebAssembly::SPLAT_F64x2 },
16676 { WebAssembly::SPLAT_I16x8_S, WebAssembly::SPLAT_I16x8 },
16677 { WebAssembly::SPLAT_I32x4_S, WebAssembly::SPLAT_I32x4 },
16678 { WebAssembly::SPLAT_I64x2_S, WebAssembly::SPLAT_I64x2 },
16679 { WebAssembly::SPLAT_I8x16_S, WebAssembly::SPLAT_I8x16 },
16680 { WebAssembly::SQRT_F16x8_S, WebAssembly::SQRT_F16x8 },
16681 { WebAssembly::SQRT_F32_S, WebAssembly::SQRT_F32 },
16682 { WebAssembly::SQRT_F32x4_S, WebAssembly::SQRT_F32x4 },
16683 { WebAssembly::SQRT_F64_S, WebAssembly::SQRT_F64 },
16684 { WebAssembly::SQRT_F64x2_S, WebAssembly::SQRT_F64x2 },
16685 { WebAssembly::STORE16_I32_A32_S, WebAssembly::STORE16_I32_A32 },
16686 { WebAssembly::STORE16_I32_A64_S, WebAssembly::STORE16_I32_A64 },
16687 { WebAssembly::STORE16_I64_A32_S, WebAssembly::STORE16_I64_A32 },
16688 { WebAssembly::STORE16_I64_A64_S, WebAssembly::STORE16_I64_A64 },
16689 { WebAssembly::STORE32_I64_A32_S, WebAssembly::STORE32_I64_A32 },
16690 { WebAssembly::STORE32_I64_A64_S, WebAssembly::STORE32_I64_A64 },
16691 { WebAssembly::STORE8_I32_A32_S, WebAssembly::STORE8_I32_A32 },
16692 { WebAssembly::STORE8_I32_A64_S, WebAssembly::STORE8_I32_A64 },
16693 { WebAssembly::STORE8_I64_A32_S, WebAssembly::STORE8_I64_A32 },
16694 { WebAssembly::STORE8_I64_A64_S, WebAssembly::STORE8_I64_A64 },
16695 { WebAssembly::STORE_F16_F32_A32_S, WebAssembly::STORE_F16_F32_A32 },
16696 { WebAssembly::STORE_F16_F32_A64_S, WebAssembly::STORE_F16_F32_A64 },
16697 { WebAssembly::STORE_F32_A32_S, WebAssembly::STORE_F32_A32 },
16698 { WebAssembly::STORE_F32_A64_S, WebAssembly::STORE_F32_A64 },
16699 { WebAssembly::STORE_F64_A32_S, WebAssembly::STORE_F64_A32 },
16700 { WebAssembly::STORE_F64_A64_S, WebAssembly::STORE_F64_A64 },
16701 { WebAssembly::STORE_I32_A32_S, WebAssembly::STORE_I32_A32 },
16702 { WebAssembly::STORE_I32_A64_S, WebAssembly::STORE_I32_A64 },
16703 { WebAssembly::STORE_I64_A32_S, WebAssembly::STORE_I64_A32 },
16704 { WebAssembly::STORE_I64_A64_S, WebAssembly::STORE_I64_A64 },
16705 { WebAssembly::STORE_LANE_I16x8_A32_S, WebAssembly::STORE_LANE_I16x8_A32 },
16706 { WebAssembly::STORE_LANE_I16x8_A64_S, WebAssembly::STORE_LANE_I16x8_A64 },
16707 { WebAssembly::STORE_LANE_I32x4_A32_S, WebAssembly::STORE_LANE_I32x4_A32 },
16708 { WebAssembly::STORE_LANE_I32x4_A64_S, WebAssembly::STORE_LANE_I32x4_A64 },
16709 { WebAssembly::STORE_LANE_I64x2_A32_S, WebAssembly::STORE_LANE_I64x2_A32 },
16710 { WebAssembly::STORE_LANE_I64x2_A64_S, WebAssembly::STORE_LANE_I64x2_A64 },
16711 { WebAssembly::STORE_LANE_I8x16_A32_S, WebAssembly::STORE_LANE_I8x16_A32 },
16712 { WebAssembly::STORE_LANE_I8x16_A64_S, WebAssembly::STORE_LANE_I8x16_A64 },
16713 { WebAssembly::STORE_V128_A32_S, WebAssembly::STORE_V128_A32 },
16714 { WebAssembly::STORE_V128_A64_S, WebAssembly::STORE_V128_A64 },
16715 { WebAssembly::SUB_F16x8_S, WebAssembly::SUB_F16x8 },
16716 { WebAssembly::SUB_F32_S, WebAssembly::SUB_F32 },
16717 { WebAssembly::SUB_F32x4_S, WebAssembly::SUB_F32x4 },
16718 { WebAssembly::SUB_F64_S, WebAssembly::SUB_F64 },
16719 { WebAssembly::SUB_F64x2_S, WebAssembly::SUB_F64x2 },
16720 { WebAssembly::SUB_I16x8_S, WebAssembly::SUB_I16x8 },
16721 { WebAssembly::SUB_I32_S, WebAssembly::SUB_I32 },
16722 { WebAssembly::SUB_I32x4_S, WebAssembly::SUB_I32x4 },
16723 { WebAssembly::SUB_I64_S, WebAssembly::SUB_I64 },
16724 { WebAssembly::SUB_I64x2_S, WebAssembly::SUB_I64x2 },
16725 { WebAssembly::SUB_I8x16_S, WebAssembly::SUB_I8x16 },
16726 { WebAssembly::SUB_SAT_S_I16x8_S, WebAssembly::SUB_SAT_S_I16x8 },
16727 { WebAssembly::SUB_SAT_S_I8x16_S, WebAssembly::SUB_SAT_S_I8x16 },
16728 { WebAssembly::SUB_SAT_U_I16x8_S, WebAssembly::SUB_SAT_U_I16x8 },
16729 { WebAssembly::SUB_SAT_U_I8x16_S, WebAssembly::SUB_SAT_U_I8x16 },
16730 { WebAssembly::SWIZZLE_S, WebAssembly::SWIZZLE },
16731 { WebAssembly::TABLE_COPY_S, WebAssembly::TABLE_COPY },
16732 { WebAssembly::TABLE_FILL_EXNREF_S, WebAssembly::TABLE_FILL_EXNREF },
16733 { WebAssembly::TABLE_FILL_EXTERNREF_S, WebAssembly::TABLE_FILL_EXTERNREF },
16734 { WebAssembly::TABLE_FILL_FUNCREF_S, WebAssembly::TABLE_FILL_FUNCREF },
16735 { WebAssembly::TABLE_GET_EXNREF_S, WebAssembly::TABLE_GET_EXNREF },
16736 { WebAssembly::TABLE_GET_EXTERNREF_S, WebAssembly::TABLE_GET_EXTERNREF },
16737 { WebAssembly::TABLE_GET_FUNCREF_S, WebAssembly::TABLE_GET_FUNCREF },
16738 { WebAssembly::TABLE_GROW_EXNREF_S, WebAssembly::TABLE_GROW_EXNREF },
16739 { WebAssembly::TABLE_GROW_EXTERNREF_S, WebAssembly::TABLE_GROW_EXTERNREF },
16740 { WebAssembly::TABLE_GROW_FUNCREF_S, WebAssembly::TABLE_GROW_FUNCREF },
16741 { WebAssembly::TABLE_SET_EXNREF_S, WebAssembly::TABLE_SET_EXNREF },
16742 { WebAssembly::TABLE_SET_EXTERNREF_S, WebAssembly::TABLE_SET_EXTERNREF },
16743 { WebAssembly::TABLE_SET_FUNCREF_S, WebAssembly::TABLE_SET_FUNCREF },
16744 { WebAssembly::TABLE_SIZE_S, WebAssembly::TABLE_SIZE },
16745 { WebAssembly::TEE_EXNREF_S, WebAssembly::TEE_EXNREF },
16746 { WebAssembly::TEE_EXTERNREF_S, WebAssembly::TEE_EXTERNREF },
16747 { WebAssembly::TEE_F32_S, WebAssembly::TEE_F32 },
16748 { WebAssembly::TEE_F64_S, WebAssembly::TEE_F64 },
16749 { WebAssembly::TEE_FUNCREF_S, WebAssembly::TEE_FUNCREF },
16750 { WebAssembly::TEE_I32_S, WebAssembly::TEE_I32 },
16751 { WebAssembly::TEE_I64_S, WebAssembly::TEE_I64 },
16752 { WebAssembly::TEE_V128_S, WebAssembly::TEE_V128 },
16753 { WebAssembly::THROW_S, WebAssembly::THROW },
16754 { WebAssembly::TRUNC_F16x8_S, WebAssembly::TRUNC_F16x8 },
16755 { WebAssembly::TRUNC_F32_S, WebAssembly::TRUNC_F32 },
16756 { WebAssembly::TRUNC_F32x4_S, WebAssembly::TRUNC_F32x4 },
16757 { WebAssembly::TRUNC_F64_S, WebAssembly::TRUNC_F64 },
16758 { WebAssembly::TRUNC_F64x2_S, WebAssembly::TRUNC_F64x2 },
16759 { WebAssembly::TRY_S, WebAssembly::TRY },
16760 { WebAssembly::UNREACHABLE_S, WebAssembly::UNREACHABLE },
16761 { WebAssembly::XOR_I32_S, WebAssembly::XOR_I32 },
16762 { WebAssembly::XOR_I64_S, WebAssembly::XOR_I64 },
16763 { WebAssembly::XOR_S, WebAssembly::XOR },
16764 { WebAssembly::anonymous_8187MEMORY_GROW_A32_S, WebAssembly::anonymous_8187MEMORY_GROW_A32 },
16765 { WebAssembly::anonymous_8187MEMORY_SIZE_A32_S, WebAssembly::anonymous_8187MEMORY_SIZE_A32 },
16766 { WebAssembly::anonymous_8188MEMORY_GROW_A64_S, WebAssembly::anonymous_8188MEMORY_GROW_A64 },
16767 { WebAssembly::anonymous_8188MEMORY_SIZE_A64_S, WebAssembly::anonymous_8188MEMORY_SIZE_A64 },
16768 { WebAssembly::anonymous_8878DATA_DROP_S, WebAssembly::anonymous_8878DATA_DROP },
16769 { WebAssembly::anonymous_8878MEMORY_COPY_A32_S, WebAssembly::anonymous_8878MEMORY_COPY_A32 },
16770 { WebAssembly::anonymous_8878MEMORY_FILL_A32_S, WebAssembly::anonymous_8878MEMORY_FILL_A32 },
16771 { WebAssembly::anonymous_8878MEMORY_INIT_A32_S, WebAssembly::anonymous_8878MEMORY_INIT_A32 },
16772 { WebAssembly::anonymous_8879DATA_DROP_S, WebAssembly::anonymous_8879DATA_DROP },
16773 { WebAssembly::anonymous_8879MEMORY_COPY_A64_S, WebAssembly::anonymous_8879MEMORY_COPY_A64 },
16774 { WebAssembly::anonymous_8879MEMORY_FILL_A64_S, WebAssembly::anonymous_8879MEMORY_FILL_A64 },
16775 { WebAssembly::anonymous_8879MEMORY_INIT_A64_S, WebAssembly::anonymous_8879MEMORY_INIT_A64 },
16776 { WebAssembly::convert_low_s_F64x2_S, WebAssembly::convert_low_s_F64x2 },
16777 { WebAssembly::convert_low_u_F64x2_S, WebAssembly::convert_low_u_F64x2 },
16778 { WebAssembly::demote_zero_F32x4_S, WebAssembly::demote_zero_F32x4 },
16779 { WebAssembly::extend_high_s_I16x8_S, WebAssembly::extend_high_s_I16x8 },
16780 { WebAssembly::extend_high_s_I32x4_S, WebAssembly::extend_high_s_I32x4 },
16781 { WebAssembly::extend_high_s_I64x2_S, WebAssembly::extend_high_s_I64x2 },
16782 { WebAssembly::extend_high_u_I16x8_S, WebAssembly::extend_high_u_I16x8 },
16783 { WebAssembly::extend_high_u_I32x4_S, WebAssembly::extend_high_u_I32x4 },
16784 { WebAssembly::extend_high_u_I64x2_S, WebAssembly::extend_high_u_I64x2 },
16785 { WebAssembly::extend_low_s_I16x8_S, WebAssembly::extend_low_s_I16x8 },
16786 { WebAssembly::extend_low_s_I32x4_S, WebAssembly::extend_low_s_I32x4 },
16787 { WebAssembly::extend_low_s_I64x2_S, WebAssembly::extend_low_s_I64x2 },
16788 { WebAssembly::extend_low_u_I16x8_S, WebAssembly::extend_low_u_I16x8 },
16789 { WebAssembly::extend_low_u_I32x4_S, WebAssembly::extend_low_u_I32x4 },
16790 { WebAssembly::extend_low_u_I64x2_S, WebAssembly::extend_low_u_I64x2 },
16791 { WebAssembly::fp_to_sint_I16x8_S, WebAssembly::fp_to_sint_I16x8 },
16792 { WebAssembly::fp_to_sint_I32x4_S, WebAssembly::fp_to_sint_I32x4 },
16793 { WebAssembly::fp_to_uint_I16x8_S, WebAssembly::fp_to_uint_I16x8 },
16794 { WebAssembly::fp_to_uint_I32x4_S, WebAssembly::fp_to_uint_I32x4 },
16795 { WebAssembly::int_wasm_extadd_pairwise_signed_I16x8_S, WebAssembly::int_wasm_extadd_pairwise_signed_I16x8 },
16796 { WebAssembly::int_wasm_extadd_pairwise_signed_I32x4_S, WebAssembly::int_wasm_extadd_pairwise_signed_I32x4 },
16797 { WebAssembly::int_wasm_extadd_pairwise_unsigned_I16x8_S, WebAssembly::int_wasm_extadd_pairwise_unsigned_I16x8 },
16798 { WebAssembly::int_wasm_extadd_pairwise_unsigned_I32x4_S, WebAssembly::int_wasm_extadd_pairwise_unsigned_I32x4 },
16799 { WebAssembly::int_wasm_relaxed_trunc_signed_I32x4_S, WebAssembly::int_wasm_relaxed_trunc_signed_I32x4 },
16800 { WebAssembly::int_wasm_relaxed_trunc_signed_zero_I32x4_S, WebAssembly::int_wasm_relaxed_trunc_signed_zero_I32x4 },
16801 { WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4_S, WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4 },
16802 { WebAssembly::int_wasm_relaxed_trunc_unsigned_zero_I32x4_S, WebAssembly::int_wasm_relaxed_trunc_unsigned_zero_I32x4 },
16803 { WebAssembly::promote_low_F64x2_S, WebAssembly::promote_low_F64x2 },
16804 { WebAssembly::sint_to_fp_F16x8_S, WebAssembly::sint_to_fp_F16x8 },
16805 { WebAssembly::sint_to_fp_F32x4_S, WebAssembly::sint_to_fp_F32x4 },
16806 { WebAssembly::trunc_sat_zero_s_I32x4_S, WebAssembly::trunc_sat_zero_s_I32x4 },
16807 { WebAssembly::trunc_sat_zero_u_I32x4_S, WebAssembly::trunc_sat_zero_u_I32x4 },
16808 { WebAssembly::uint_to_fp_F16x8_S, WebAssembly::uint_to_fp_F16x8 },
16809 { WebAssembly::uint_to_fp_F32x4_S, WebAssembly::uint_to_fp_F32x4 },
16810}; // End of getRegisterOpcodeTable
16811
16812 unsigned mid;
16813 unsigned start = 0;
16814 unsigned end = 800;
16815 while (start < end) {
16816 mid = start + (end - start) / 2;
16817 if (Opcode == getRegisterOpcodeTable[mid][0]) {
16818 break;
16819 }
16820 if (Opcode < getRegisterOpcodeTable[mid][0])
16821 end = mid;
16822 else
16823 start = mid + 1;
16824 }
16825 if (start == end)
16826 return -1; // Instruction doesn't exist in this table.
16827
16828 return getRegisterOpcodeTable[mid][1];
16829}
16830
16831// getStackOpcode
16832LLVM_READONLY
16833int getStackOpcode(uint16_t Opcode) {
16834static const uint16_t getStackOpcodeTable[][2] = {
16835 { WebAssembly::CALL_PARAMS, WebAssembly::CALL_PARAMS_S },
16836 { WebAssembly::CALL_RESULTS, WebAssembly::CALL_RESULTS_S },
16837 { WebAssembly::CATCHRET, WebAssembly::CATCHRET_S },
16838 { WebAssembly::CLEANUPRET, WebAssembly::CLEANUPRET_S },
16839 { WebAssembly::COMPILER_FENCE, WebAssembly::COMPILER_FENCE_S },
16840 { WebAssembly::RET_CALL_RESULTS, WebAssembly::RET_CALL_RESULTS_S },
16841 { WebAssembly::ABS_F16x8, WebAssembly::ABS_F16x8_S },
16842 { WebAssembly::ABS_F32, WebAssembly::ABS_F32_S },
16843 { WebAssembly::ABS_F32x4, WebAssembly::ABS_F32x4_S },
16844 { WebAssembly::ABS_F64, WebAssembly::ABS_F64_S },
16845 { WebAssembly::ABS_F64x2, WebAssembly::ABS_F64x2_S },
16846 { WebAssembly::ABS_I16x8, WebAssembly::ABS_I16x8_S },
16847 { WebAssembly::ABS_I32x4, WebAssembly::ABS_I32x4_S },
16848 { WebAssembly::ABS_I64x2, WebAssembly::ABS_I64x2_S },
16849 { WebAssembly::ABS_I8x16, WebAssembly::ABS_I8x16_S },
16850 { WebAssembly::ADD_F16x8, WebAssembly::ADD_F16x8_S },
16851 { WebAssembly::ADD_F32, WebAssembly::ADD_F32_S },
16852 { WebAssembly::ADD_F32x4, WebAssembly::ADD_F32x4_S },
16853 { WebAssembly::ADD_F64, WebAssembly::ADD_F64_S },
16854 { WebAssembly::ADD_F64x2, WebAssembly::ADD_F64x2_S },
16855 { WebAssembly::ADD_I16x8, WebAssembly::ADD_I16x8_S },
16856 { WebAssembly::ADD_I32, WebAssembly::ADD_I32_S },
16857 { WebAssembly::ADD_I32x4, WebAssembly::ADD_I32x4_S },
16858 { WebAssembly::ADD_I64, WebAssembly::ADD_I64_S },
16859 { WebAssembly::ADD_I64x2, WebAssembly::ADD_I64x2_S },
16860 { WebAssembly::ADD_I8x16, WebAssembly::ADD_I8x16_S },
16861 { WebAssembly::ADD_SAT_S_I16x8, WebAssembly::ADD_SAT_S_I16x8_S },
16862 { WebAssembly::ADD_SAT_S_I8x16, WebAssembly::ADD_SAT_S_I8x16_S },
16863 { WebAssembly::ADD_SAT_U_I16x8, WebAssembly::ADD_SAT_U_I16x8_S },
16864 { WebAssembly::ADD_SAT_U_I8x16, WebAssembly::ADD_SAT_U_I8x16_S },
16865 { WebAssembly::ADJCALLSTACKDOWN, WebAssembly::ADJCALLSTACKDOWN_S },
16866 { WebAssembly::ADJCALLSTACKUP, WebAssembly::ADJCALLSTACKUP_S },
16867 { WebAssembly::ALLTRUE_I16x8, WebAssembly::ALLTRUE_I16x8_S },
16868 { WebAssembly::ALLTRUE_I32x4, WebAssembly::ALLTRUE_I32x4_S },
16869 { WebAssembly::ALLTRUE_I64x2, WebAssembly::ALLTRUE_I64x2_S },
16870 { WebAssembly::ALLTRUE_I8x16, WebAssembly::ALLTRUE_I8x16_S },
16871 { WebAssembly::AND, WebAssembly::AND_S },
16872 { WebAssembly::ANDNOT, WebAssembly::ANDNOT_S },
16873 { WebAssembly::AND_I32, WebAssembly::AND_I32_S },
16874 { WebAssembly::AND_I64, WebAssembly::AND_I64_S },
16875 { WebAssembly::ANYTRUE, WebAssembly::ANYTRUE_S },
16876 { WebAssembly::ARGUMENT_exnref, WebAssembly::ARGUMENT_exnref_S },
16877 { WebAssembly::ARGUMENT_externref, WebAssembly::ARGUMENT_externref_S },
16878 { WebAssembly::ARGUMENT_f32, WebAssembly::ARGUMENT_f32_S },
16879 { WebAssembly::ARGUMENT_f64, WebAssembly::ARGUMENT_f64_S },
16880 { WebAssembly::ARGUMENT_funcref, WebAssembly::ARGUMENT_funcref_S },
16881 { WebAssembly::ARGUMENT_i32, WebAssembly::ARGUMENT_i32_S },
16882 { WebAssembly::ARGUMENT_i64, WebAssembly::ARGUMENT_i64_S },
16883 { WebAssembly::ARGUMENT_v16i8, WebAssembly::ARGUMENT_v16i8_S },
16884 { WebAssembly::ARGUMENT_v2f64, WebAssembly::ARGUMENT_v2f64_S },
16885 { WebAssembly::ARGUMENT_v2i64, WebAssembly::ARGUMENT_v2i64_S },
16886 { WebAssembly::ARGUMENT_v4f32, WebAssembly::ARGUMENT_v4f32_S },
16887 { WebAssembly::ARGUMENT_v4i32, WebAssembly::ARGUMENT_v4i32_S },
16888 { WebAssembly::ARGUMENT_v8f16, WebAssembly::ARGUMENT_v8f16_S },
16889 { WebAssembly::ARGUMENT_v8i16, WebAssembly::ARGUMENT_v8i16_S },
16890 { WebAssembly::ATOMIC_FENCE, WebAssembly::ATOMIC_FENCE_S },
16891 { WebAssembly::ATOMIC_LOAD16_U_I32_A32, WebAssembly::ATOMIC_LOAD16_U_I32_A32_S },
16892 { WebAssembly::ATOMIC_LOAD16_U_I32_A64, WebAssembly::ATOMIC_LOAD16_U_I32_A64_S },
16893 { WebAssembly::ATOMIC_LOAD16_U_I64_A32, WebAssembly::ATOMIC_LOAD16_U_I64_A32_S },
16894 { WebAssembly::ATOMIC_LOAD16_U_I64_A64, WebAssembly::ATOMIC_LOAD16_U_I64_A64_S },
16895 { WebAssembly::ATOMIC_LOAD32_U_I64_A32, WebAssembly::ATOMIC_LOAD32_U_I64_A32_S },
16896 { WebAssembly::ATOMIC_LOAD32_U_I64_A64, WebAssembly::ATOMIC_LOAD32_U_I64_A64_S },
16897 { WebAssembly::ATOMIC_LOAD8_U_I32_A32, WebAssembly::ATOMIC_LOAD8_U_I32_A32_S },
16898 { WebAssembly::ATOMIC_LOAD8_U_I32_A64, WebAssembly::ATOMIC_LOAD8_U_I32_A64_S },
16899 { WebAssembly::ATOMIC_LOAD8_U_I64_A32, WebAssembly::ATOMIC_LOAD8_U_I64_A32_S },
16900 { WebAssembly::ATOMIC_LOAD8_U_I64_A64, WebAssembly::ATOMIC_LOAD8_U_I64_A64_S },
16901 { WebAssembly::ATOMIC_LOAD_I32_A32, WebAssembly::ATOMIC_LOAD_I32_A32_S },
16902 { WebAssembly::ATOMIC_LOAD_I32_A64, WebAssembly::ATOMIC_LOAD_I32_A64_S },
16903 { WebAssembly::ATOMIC_LOAD_I64_A32, WebAssembly::ATOMIC_LOAD_I64_A32_S },
16904 { WebAssembly::ATOMIC_LOAD_I64_A64, WebAssembly::ATOMIC_LOAD_I64_A64_S },
16905 { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32_S },
16906 { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64_S },
16907 { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32_S },
16908 { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64_S },
16909 { WebAssembly::ATOMIC_RMW16_U_AND_I32_A32, WebAssembly::ATOMIC_RMW16_U_AND_I32_A32_S },
16910 { WebAssembly::ATOMIC_RMW16_U_AND_I32_A64, WebAssembly::ATOMIC_RMW16_U_AND_I32_A64_S },
16911 { WebAssembly::ATOMIC_RMW16_U_AND_I64_A32, WebAssembly::ATOMIC_RMW16_U_AND_I64_A32_S },
16912 { WebAssembly::ATOMIC_RMW16_U_AND_I64_A64, WebAssembly::ATOMIC_RMW16_U_AND_I64_A64_S },
16913 { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32_S },
16914 { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64_S },
16915 { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32_S },
16916 { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64_S },
16917 { WebAssembly::ATOMIC_RMW16_U_OR_I32_A32, WebAssembly::ATOMIC_RMW16_U_OR_I32_A32_S },
16918 { WebAssembly::ATOMIC_RMW16_U_OR_I32_A64, WebAssembly::ATOMIC_RMW16_U_OR_I32_A64_S },
16919 { WebAssembly::ATOMIC_RMW16_U_OR_I64_A32, WebAssembly::ATOMIC_RMW16_U_OR_I64_A32_S },
16920 { WebAssembly::ATOMIC_RMW16_U_OR_I64_A64, WebAssembly::ATOMIC_RMW16_U_OR_I64_A64_S },
16921 { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32_S },
16922 { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64_S },
16923 { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32_S },
16924 { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64_S },
16925 { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32_S },
16926 { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64_S },
16927 { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32_S },
16928 { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64_S },
16929 { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32_S },
16930 { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64_S },
16931 { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32_S },
16932 { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64_S },
16933 { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32_S },
16934 { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64_S },
16935 { WebAssembly::ATOMIC_RMW32_U_AND_I64_A32, WebAssembly::ATOMIC_RMW32_U_AND_I64_A32_S },
16936 { WebAssembly::ATOMIC_RMW32_U_AND_I64_A64, WebAssembly::ATOMIC_RMW32_U_AND_I64_A64_S },
16937 { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32_S },
16938 { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64_S },
16939 { WebAssembly::ATOMIC_RMW32_U_OR_I64_A32, WebAssembly::ATOMIC_RMW32_U_OR_I64_A32_S },
16940 { WebAssembly::ATOMIC_RMW32_U_OR_I64_A64, WebAssembly::ATOMIC_RMW32_U_OR_I64_A64_S },
16941 { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32_S },
16942 { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64_S },
16943 { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32_S },
16944 { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64_S },
16945 { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32_S },
16946 { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64_S },
16947 { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32_S },
16948 { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64_S },
16949 { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32_S },
16950 { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64_S },
16951 { WebAssembly::ATOMIC_RMW8_U_AND_I32_A32, WebAssembly::ATOMIC_RMW8_U_AND_I32_A32_S },
16952 { WebAssembly::ATOMIC_RMW8_U_AND_I32_A64, WebAssembly::ATOMIC_RMW8_U_AND_I32_A64_S },
16953 { WebAssembly::ATOMIC_RMW8_U_AND_I64_A32, WebAssembly::ATOMIC_RMW8_U_AND_I64_A32_S },
16954 { WebAssembly::ATOMIC_RMW8_U_AND_I64_A64, WebAssembly::ATOMIC_RMW8_U_AND_I64_A64_S },
16955 { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32_S },
16956 { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64_S },
16957 { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32_S },
16958 { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64_S },
16959 { WebAssembly::ATOMIC_RMW8_U_OR_I32_A32, WebAssembly::ATOMIC_RMW8_U_OR_I32_A32_S },
16960 { WebAssembly::ATOMIC_RMW8_U_OR_I32_A64, WebAssembly::ATOMIC_RMW8_U_OR_I32_A64_S },
16961 { WebAssembly::ATOMIC_RMW8_U_OR_I64_A32, WebAssembly::ATOMIC_RMW8_U_OR_I64_A32_S },
16962 { WebAssembly::ATOMIC_RMW8_U_OR_I64_A64, WebAssembly::ATOMIC_RMW8_U_OR_I64_A64_S },
16963 { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32_S },
16964 { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64_S },
16965 { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32_S },
16966 { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64_S },
16967 { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32_S },
16968 { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64_S },
16969 { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32_S },
16970 { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64_S },
16971 { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32_S },
16972 { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64_S },
16973 { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32_S },
16974 { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64_S },
16975 { WebAssembly::ATOMIC_RMW_ADD_I32_A32, WebAssembly::ATOMIC_RMW_ADD_I32_A32_S },
16976 { WebAssembly::ATOMIC_RMW_ADD_I32_A64, WebAssembly::ATOMIC_RMW_ADD_I32_A64_S },
16977 { WebAssembly::ATOMIC_RMW_ADD_I64_A32, WebAssembly::ATOMIC_RMW_ADD_I64_A32_S },
16978 { WebAssembly::ATOMIC_RMW_ADD_I64_A64, WebAssembly::ATOMIC_RMW_ADD_I64_A64_S },
16979 { WebAssembly::ATOMIC_RMW_AND_I32_A32, WebAssembly::ATOMIC_RMW_AND_I32_A32_S },
16980 { WebAssembly::ATOMIC_RMW_AND_I32_A64, WebAssembly::ATOMIC_RMW_AND_I32_A64_S },
16981 { WebAssembly::ATOMIC_RMW_AND_I64_A32, WebAssembly::ATOMIC_RMW_AND_I64_A32_S },
16982 { WebAssembly::ATOMIC_RMW_AND_I64_A64, WebAssembly::ATOMIC_RMW_AND_I64_A64_S },
16983 { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32_S },
16984 { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64_S },
16985 { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32_S },
16986 { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64_S },
16987 { WebAssembly::ATOMIC_RMW_OR_I32_A32, WebAssembly::ATOMIC_RMW_OR_I32_A32_S },
16988 { WebAssembly::ATOMIC_RMW_OR_I32_A64, WebAssembly::ATOMIC_RMW_OR_I32_A64_S },
16989 { WebAssembly::ATOMIC_RMW_OR_I64_A32, WebAssembly::ATOMIC_RMW_OR_I64_A32_S },
16990 { WebAssembly::ATOMIC_RMW_OR_I64_A64, WebAssembly::ATOMIC_RMW_OR_I64_A64_S },
16991 { WebAssembly::ATOMIC_RMW_SUB_I32_A32, WebAssembly::ATOMIC_RMW_SUB_I32_A32_S },
16992 { WebAssembly::ATOMIC_RMW_SUB_I32_A64, WebAssembly::ATOMIC_RMW_SUB_I32_A64_S },
16993 { WebAssembly::ATOMIC_RMW_SUB_I64_A32, WebAssembly::ATOMIC_RMW_SUB_I64_A32_S },
16994 { WebAssembly::ATOMIC_RMW_SUB_I64_A64, WebAssembly::ATOMIC_RMW_SUB_I64_A64_S },
16995 { WebAssembly::ATOMIC_RMW_XCHG_I32_A32, WebAssembly::ATOMIC_RMW_XCHG_I32_A32_S },
16996 { WebAssembly::ATOMIC_RMW_XCHG_I32_A64, WebAssembly::ATOMIC_RMW_XCHG_I32_A64_S },
16997 { WebAssembly::ATOMIC_RMW_XCHG_I64_A32, WebAssembly::ATOMIC_RMW_XCHG_I64_A32_S },
16998 { WebAssembly::ATOMIC_RMW_XCHG_I64_A64, WebAssembly::ATOMIC_RMW_XCHG_I64_A64_S },
16999 { WebAssembly::ATOMIC_RMW_XOR_I32_A32, WebAssembly::ATOMIC_RMW_XOR_I32_A32_S },
17000 { WebAssembly::ATOMIC_RMW_XOR_I32_A64, WebAssembly::ATOMIC_RMW_XOR_I32_A64_S },
17001 { WebAssembly::ATOMIC_RMW_XOR_I64_A32, WebAssembly::ATOMIC_RMW_XOR_I64_A32_S },
17002 { WebAssembly::ATOMIC_RMW_XOR_I64_A64, WebAssembly::ATOMIC_RMW_XOR_I64_A64_S },
17003 { WebAssembly::ATOMIC_STORE16_I32_A32, WebAssembly::ATOMIC_STORE16_I32_A32_S },
17004 { WebAssembly::ATOMIC_STORE16_I32_A64, WebAssembly::ATOMIC_STORE16_I32_A64_S },
17005 { WebAssembly::ATOMIC_STORE16_I64_A32, WebAssembly::ATOMIC_STORE16_I64_A32_S },
17006 { WebAssembly::ATOMIC_STORE16_I64_A64, WebAssembly::ATOMIC_STORE16_I64_A64_S },
17007 { WebAssembly::ATOMIC_STORE32_I64_A32, WebAssembly::ATOMIC_STORE32_I64_A32_S },
17008 { WebAssembly::ATOMIC_STORE32_I64_A64, WebAssembly::ATOMIC_STORE32_I64_A64_S },
17009 { WebAssembly::ATOMIC_STORE8_I32_A32, WebAssembly::ATOMIC_STORE8_I32_A32_S },
17010 { WebAssembly::ATOMIC_STORE8_I32_A64, WebAssembly::ATOMIC_STORE8_I32_A64_S },
17011 { WebAssembly::ATOMIC_STORE8_I64_A32, WebAssembly::ATOMIC_STORE8_I64_A32_S },
17012 { WebAssembly::ATOMIC_STORE8_I64_A64, WebAssembly::ATOMIC_STORE8_I64_A64_S },
17013 { WebAssembly::ATOMIC_STORE_I32_A32, WebAssembly::ATOMIC_STORE_I32_A32_S },
17014 { WebAssembly::ATOMIC_STORE_I32_A64, WebAssembly::ATOMIC_STORE_I32_A64_S },
17015 { WebAssembly::ATOMIC_STORE_I64_A32, WebAssembly::ATOMIC_STORE_I64_A32_S },
17016 { WebAssembly::ATOMIC_STORE_I64_A64, WebAssembly::ATOMIC_STORE_I64_A64_S },
17017 { WebAssembly::AVGR_U_I16x8, WebAssembly::AVGR_U_I16x8_S },
17018 { WebAssembly::AVGR_U_I8x16, WebAssembly::AVGR_U_I8x16_S },
17019 { WebAssembly::BITMASK_I16x8, WebAssembly::BITMASK_I16x8_S },
17020 { WebAssembly::BITMASK_I32x4, WebAssembly::BITMASK_I32x4_S },
17021 { WebAssembly::BITMASK_I64x2, WebAssembly::BITMASK_I64x2_S },
17022 { WebAssembly::BITMASK_I8x16, WebAssembly::BITMASK_I8x16_S },
17023 { WebAssembly::BITSELECT, WebAssembly::BITSELECT_S },
17024 { WebAssembly::BLOCK, WebAssembly::BLOCK_S },
17025 { WebAssembly::BR, WebAssembly::BR_S },
17026 { WebAssembly::BR_IF, WebAssembly::BR_IF_S },
17027 { WebAssembly::BR_TABLE_I32, WebAssembly::BR_TABLE_I32_S },
17028 { WebAssembly::BR_TABLE_I64, WebAssembly::BR_TABLE_I64_S },
17029 { WebAssembly::BR_UNLESS, WebAssembly::BR_UNLESS_S },
17030 { WebAssembly::CALL, WebAssembly::CALL_S },
17031 { WebAssembly::CALL_INDIRECT, WebAssembly::CALL_INDIRECT_S },
17032 { WebAssembly::CATCH, WebAssembly::CATCH_S },
17033 { WebAssembly::CATCH_ALL, WebAssembly::CATCH_ALL_S },
17034 { WebAssembly::CEIL_F16x8, WebAssembly::CEIL_F16x8_S },
17035 { WebAssembly::CEIL_F32, WebAssembly::CEIL_F32_S },
17036 { WebAssembly::CEIL_F32x4, WebAssembly::CEIL_F32x4_S },
17037 { WebAssembly::CEIL_F64, WebAssembly::CEIL_F64_S },
17038 { WebAssembly::CEIL_F64x2, WebAssembly::CEIL_F64x2_S },
17039 { WebAssembly::CLZ_I32, WebAssembly::CLZ_I32_S },
17040 { WebAssembly::CLZ_I64, WebAssembly::CLZ_I64_S },
17041 { WebAssembly::CONST_F32, WebAssembly::CONST_F32_S },
17042 { WebAssembly::CONST_F64, WebAssembly::CONST_F64_S },
17043 { WebAssembly::CONST_I32, WebAssembly::CONST_I32_S },
17044 { WebAssembly::CONST_I64, WebAssembly::CONST_I64_S },
17045 { WebAssembly::CONST_V128_F32x4, WebAssembly::CONST_V128_F32x4_S },
17046 { WebAssembly::CONST_V128_F64x2, WebAssembly::CONST_V128_F64x2_S },
17047 { WebAssembly::CONST_V128_I16x8, WebAssembly::CONST_V128_I16x8_S },
17048 { WebAssembly::CONST_V128_I32x4, WebAssembly::CONST_V128_I32x4_S },
17049 { WebAssembly::CONST_V128_I64x2, WebAssembly::CONST_V128_I64x2_S },
17050 { WebAssembly::CONST_V128_I8x16, WebAssembly::CONST_V128_I8x16_S },
17051 { WebAssembly::COPYSIGN_F32, WebAssembly::COPYSIGN_F32_S },
17052 { WebAssembly::COPYSIGN_F64, WebAssembly::COPYSIGN_F64_S },
17053 { WebAssembly::COPY_EXNREF, WebAssembly::COPY_EXNREF_S },
17054 { WebAssembly::COPY_EXTERNREF, WebAssembly::COPY_EXTERNREF_S },
17055 { WebAssembly::COPY_F32, WebAssembly::COPY_F32_S },
17056 { WebAssembly::COPY_F64, WebAssembly::COPY_F64_S },
17057 { WebAssembly::COPY_FUNCREF, WebAssembly::COPY_FUNCREF_S },
17058 { WebAssembly::COPY_I32, WebAssembly::COPY_I32_S },
17059 { WebAssembly::COPY_I64, WebAssembly::COPY_I64_S },
17060 { WebAssembly::COPY_V128, WebAssembly::COPY_V128_S },
17061 { WebAssembly::CTZ_I32, WebAssembly::CTZ_I32_S },
17062 { WebAssembly::CTZ_I64, WebAssembly::CTZ_I64_S },
17063 { WebAssembly::DEBUG_UNREACHABLE, WebAssembly::DEBUG_UNREACHABLE_S },
17064 { WebAssembly::DELEGATE, WebAssembly::DELEGATE_S },
17065 { WebAssembly::DIV_F16x8, WebAssembly::DIV_F16x8_S },
17066 { WebAssembly::DIV_F32, WebAssembly::DIV_F32_S },
17067 { WebAssembly::DIV_F32x4, WebAssembly::DIV_F32x4_S },
17068 { WebAssembly::DIV_F64, WebAssembly::DIV_F64_S },
17069 { WebAssembly::DIV_F64x2, WebAssembly::DIV_F64x2_S },
17070 { WebAssembly::DIV_S_I32, WebAssembly::DIV_S_I32_S },
17071 { WebAssembly::DIV_S_I64, WebAssembly::DIV_S_I64_S },
17072 { WebAssembly::DIV_U_I32, WebAssembly::DIV_U_I32_S },
17073 { WebAssembly::DIV_U_I64, WebAssembly::DIV_U_I64_S },
17074 { WebAssembly::DOT, WebAssembly::DOT_S },
17075 { WebAssembly::DROP_EXNREF, WebAssembly::DROP_EXNREF_S },
17076 { WebAssembly::DROP_EXTERNREF, WebAssembly::DROP_EXTERNREF_S },
17077 { WebAssembly::DROP_F32, WebAssembly::DROP_F32_S },
17078 { WebAssembly::DROP_F64, WebAssembly::DROP_F64_S },
17079 { WebAssembly::DROP_FUNCREF, WebAssembly::DROP_FUNCREF_S },
17080 { WebAssembly::DROP_I32, WebAssembly::DROP_I32_S },
17081 { WebAssembly::DROP_I64, WebAssembly::DROP_I64_S },
17082 { WebAssembly::DROP_V128, WebAssembly::DROP_V128_S },
17083 { WebAssembly::ELSE, WebAssembly::ELSE_S },
17084 { WebAssembly::END, WebAssembly::END_S },
17085 { WebAssembly::END_BLOCK, WebAssembly::END_BLOCK_S },
17086 { WebAssembly::END_FUNCTION, WebAssembly::END_FUNCTION_S },
17087 { WebAssembly::END_IF, WebAssembly::END_IF_S },
17088 { WebAssembly::END_LOOP, WebAssembly::END_LOOP_S },
17089 { WebAssembly::END_TRY, WebAssembly::END_TRY_S },
17090 { WebAssembly::EQZ_I32, WebAssembly::EQZ_I32_S },
17091 { WebAssembly::EQZ_I64, WebAssembly::EQZ_I64_S },
17092 { WebAssembly::EQ_F16x8, WebAssembly::EQ_F16x8_S },
17093 { WebAssembly::EQ_F32, WebAssembly::EQ_F32_S },
17094 { WebAssembly::EQ_F32x4, WebAssembly::EQ_F32x4_S },
17095 { WebAssembly::EQ_F64, WebAssembly::EQ_F64_S },
17096 { WebAssembly::EQ_F64x2, WebAssembly::EQ_F64x2_S },
17097 { WebAssembly::EQ_I16x8, WebAssembly::EQ_I16x8_S },
17098 { WebAssembly::EQ_I32, WebAssembly::EQ_I32_S },
17099 { WebAssembly::EQ_I32x4, WebAssembly::EQ_I32x4_S },
17100 { WebAssembly::EQ_I64, WebAssembly::EQ_I64_S },
17101 { WebAssembly::EQ_I64x2, WebAssembly::EQ_I64x2_S },
17102 { WebAssembly::EQ_I8x16, WebAssembly::EQ_I8x16_S },
17103 { WebAssembly::EXTMUL_HIGH_S_I16x8, WebAssembly::EXTMUL_HIGH_S_I16x8_S },
17104 { WebAssembly::EXTMUL_HIGH_S_I32x4, WebAssembly::EXTMUL_HIGH_S_I32x4_S },
17105 { WebAssembly::EXTMUL_HIGH_S_I64x2, WebAssembly::EXTMUL_HIGH_S_I64x2_S },
17106 { WebAssembly::EXTMUL_HIGH_U_I16x8, WebAssembly::EXTMUL_HIGH_U_I16x8_S },
17107 { WebAssembly::EXTMUL_HIGH_U_I32x4, WebAssembly::EXTMUL_HIGH_U_I32x4_S },
17108 { WebAssembly::EXTMUL_HIGH_U_I64x2, WebAssembly::EXTMUL_HIGH_U_I64x2_S },
17109 { WebAssembly::EXTMUL_LOW_S_I16x8, WebAssembly::EXTMUL_LOW_S_I16x8_S },
17110 { WebAssembly::EXTMUL_LOW_S_I32x4, WebAssembly::EXTMUL_LOW_S_I32x4_S },
17111 { WebAssembly::EXTMUL_LOW_S_I64x2, WebAssembly::EXTMUL_LOW_S_I64x2_S },
17112 { WebAssembly::EXTMUL_LOW_U_I16x8, WebAssembly::EXTMUL_LOW_U_I16x8_S },
17113 { WebAssembly::EXTMUL_LOW_U_I32x4, WebAssembly::EXTMUL_LOW_U_I32x4_S },
17114 { WebAssembly::EXTMUL_LOW_U_I64x2, WebAssembly::EXTMUL_LOW_U_I64x2_S },
17115 { WebAssembly::EXTRACT_LANE_F16x8, WebAssembly::EXTRACT_LANE_F16x8_S },
17116 { WebAssembly::EXTRACT_LANE_F32x4, WebAssembly::EXTRACT_LANE_F32x4_S },
17117 { WebAssembly::EXTRACT_LANE_F64x2, WebAssembly::EXTRACT_LANE_F64x2_S },
17118 { WebAssembly::EXTRACT_LANE_I16x8_s, WebAssembly::EXTRACT_LANE_I16x8_s_S },
17119 { WebAssembly::EXTRACT_LANE_I16x8_u, WebAssembly::EXTRACT_LANE_I16x8_u_S },
17120 { WebAssembly::EXTRACT_LANE_I32x4, WebAssembly::EXTRACT_LANE_I32x4_S },
17121 { WebAssembly::EXTRACT_LANE_I64x2, WebAssembly::EXTRACT_LANE_I64x2_S },
17122 { WebAssembly::EXTRACT_LANE_I8x16_s, WebAssembly::EXTRACT_LANE_I8x16_s_S },
17123 { WebAssembly::EXTRACT_LANE_I8x16_u, WebAssembly::EXTRACT_LANE_I8x16_u_S },
17124 { WebAssembly::F32_CONVERT_S_I32, WebAssembly::F32_CONVERT_S_I32_S },
17125 { WebAssembly::F32_CONVERT_S_I64, WebAssembly::F32_CONVERT_S_I64_S },
17126 { WebAssembly::F32_CONVERT_U_I32, WebAssembly::F32_CONVERT_U_I32_S },
17127 { WebAssembly::F32_CONVERT_U_I64, WebAssembly::F32_CONVERT_U_I64_S },
17128 { WebAssembly::F32_DEMOTE_F64, WebAssembly::F32_DEMOTE_F64_S },
17129 { WebAssembly::F32_REINTERPRET_I32, WebAssembly::F32_REINTERPRET_I32_S },
17130 { WebAssembly::F64_CONVERT_S_I32, WebAssembly::F64_CONVERT_S_I32_S },
17131 { WebAssembly::F64_CONVERT_S_I64, WebAssembly::F64_CONVERT_S_I64_S },
17132 { WebAssembly::F64_CONVERT_U_I32, WebAssembly::F64_CONVERT_U_I32_S },
17133 { WebAssembly::F64_CONVERT_U_I64, WebAssembly::F64_CONVERT_U_I64_S },
17134 { WebAssembly::F64_PROMOTE_F32, WebAssembly::F64_PROMOTE_F32_S },
17135 { WebAssembly::F64_REINTERPRET_I64, WebAssembly::F64_REINTERPRET_I64_S },
17136 { WebAssembly::FALLTHROUGH_RETURN, WebAssembly::FALLTHROUGH_RETURN_S },
17137 { WebAssembly::FLOOR_F16x8, WebAssembly::FLOOR_F16x8_S },
17138 { WebAssembly::FLOOR_F32, WebAssembly::FLOOR_F32_S },
17139 { WebAssembly::FLOOR_F32x4, WebAssembly::FLOOR_F32x4_S },
17140 { WebAssembly::FLOOR_F64, WebAssembly::FLOOR_F64_S },
17141 { WebAssembly::FLOOR_F64x2, WebAssembly::FLOOR_F64x2_S },
17142 { WebAssembly::FP_TO_SINT_I32_F32, WebAssembly::FP_TO_SINT_I32_F32_S },
17143 { WebAssembly::FP_TO_SINT_I32_F64, WebAssembly::FP_TO_SINT_I32_F64_S },
17144 { WebAssembly::FP_TO_SINT_I64_F32, WebAssembly::FP_TO_SINT_I64_F32_S },
17145 { WebAssembly::FP_TO_SINT_I64_F64, WebAssembly::FP_TO_SINT_I64_F64_S },
17146 { WebAssembly::FP_TO_UINT_I32_F32, WebAssembly::FP_TO_UINT_I32_F32_S },
17147 { WebAssembly::FP_TO_UINT_I32_F64, WebAssembly::FP_TO_UINT_I32_F64_S },
17148 { WebAssembly::FP_TO_UINT_I64_F32, WebAssembly::FP_TO_UINT_I64_F32_S },
17149 { WebAssembly::FP_TO_UINT_I64_F64, WebAssembly::FP_TO_UINT_I64_F64_S },
17150 { WebAssembly::GE_F16x8, WebAssembly::GE_F16x8_S },
17151 { WebAssembly::GE_F32, WebAssembly::GE_F32_S },
17152 { WebAssembly::GE_F32x4, WebAssembly::GE_F32x4_S },
17153 { WebAssembly::GE_F64, WebAssembly::GE_F64_S },
17154 { WebAssembly::GE_F64x2, WebAssembly::GE_F64x2_S },
17155 { WebAssembly::GE_S_I16x8, WebAssembly::GE_S_I16x8_S },
17156 { WebAssembly::GE_S_I32, WebAssembly::GE_S_I32_S },
17157 { WebAssembly::GE_S_I32x4, WebAssembly::GE_S_I32x4_S },
17158 { WebAssembly::GE_S_I64, WebAssembly::GE_S_I64_S },
17159 { WebAssembly::GE_S_I64x2, WebAssembly::GE_S_I64x2_S },
17160 { WebAssembly::GE_S_I8x16, WebAssembly::GE_S_I8x16_S },
17161 { WebAssembly::GE_U_I16x8, WebAssembly::GE_U_I16x8_S },
17162 { WebAssembly::GE_U_I32, WebAssembly::GE_U_I32_S },
17163 { WebAssembly::GE_U_I32x4, WebAssembly::GE_U_I32x4_S },
17164 { WebAssembly::GE_U_I64, WebAssembly::GE_U_I64_S },
17165 { WebAssembly::GE_U_I8x16, WebAssembly::GE_U_I8x16_S },
17166 { WebAssembly::GLOBAL_GET_EXNREF, WebAssembly::GLOBAL_GET_EXNREF_S },
17167 { WebAssembly::GLOBAL_GET_EXTERNREF, WebAssembly::GLOBAL_GET_EXTERNREF_S },
17168 { WebAssembly::GLOBAL_GET_F32, WebAssembly::GLOBAL_GET_F32_S },
17169 { WebAssembly::GLOBAL_GET_F64, WebAssembly::GLOBAL_GET_F64_S },
17170 { WebAssembly::GLOBAL_GET_FUNCREF, WebAssembly::GLOBAL_GET_FUNCREF_S },
17171 { WebAssembly::GLOBAL_GET_I32, WebAssembly::GLOBAL_GET_I32_S },
17172 { WebAssembly::GLOBAL_GET_I64, WebAssembly::GLOBAL_GET_I64_S },
17173 { WebAssembly::GLOBAL_GET_V128, WebAssembly::GLOBAL_GET_V128_S },
17174 { WebAssembly::GLOBAL_SET_EXNREF, WebAssembly::GLOBAL_SET_EXNREF_S },
17175 { WebAssembly::GLOBAL_SET_EXTERNREF, WebAssembly::GLOBAL_SET_EXTERNREF_S },
17176 { WebAssembly::GLOBAL_SET_F32, WebAssembly::GLOBAL_SET_F32_S },
17177 { WebAssembly::GLOBAL_SET_F64, WebAssembly::GLOBAL_SET_F64_S },
17178 { WebAssembly::GLOBAL_SET_FUNCREF, WebAssembly::GLOBAL_SET_FUNCREF_S },
17179 { WebAssembly::GLOBAL_SET_I32, WebAssembly::GLOBAL_SET_I32_S },
17180 { WebAssembly::GLOBAL_SET_I64, WebAssembly::GLOBAL_SET_I64_S },
17181 { WebAssembly::GLOBAL_SET_V128, WebAssembly::GLOBAL_SET_V128_S },
17182 { WebAssembly::GT_F16x8, WebAssembly::GT_F16x8_S },
17183 { WebAssembly::GT_F32, WebAssembly::GT_F32_S },
17184 { WebAssembly::GT_F32x4, WebAssembly::GT_F32x4_S },
17185 { WebAssembly::GT_F64, WebAssembly::GT_F64_S },
17186 { WebAssembly::GT_F64x2, WebAssembly::GT_F64x2_S },
17187 { WebAssembly::GT_S_I16x8, WebAssembly::GT_S_I16x8_S },
17188 { WebAssembly::GT_S_I32, WebAssembly::GT_S_I32_S },
17189 { WebAssembly::GT_S_I32x4, WebAssembly::GT_S_I32x4_S },
17190 { WebAssembly::GT_S_I64, WebAssembly::GT_S_I64_S },
17191 { WebAssembly::GT_S_I64x2, WebAssembly::GT_S_I64x2_S },
17192 { WebAssembly::GT_S_I8x16, WebAssembly::GT_S_I8x16_S },
17193 { WebAssembly::GT_U_I16x8, WebAssembly::GT_U_I16x8_S },
17194 { WebAssembly::GT_U_I32, WebAssembly::GT_U_I32_S },
17195 { WebAssembly::GT_U_I32x4, WebAssembly::GT_U_I32x4_S },
17196 { WebAssembly::GT_U_I64, WebAssembly::GT_U_I64_S },
17197 { WebAssembly::GT_U_I8x16, WebAssembly::GT_U_I8x16_S },
17198 { WebAssembly::I32_EXTEND16_S_I32, WebAssembly::I32_EXTEND16_S_I32_S },
17199 { WebAssembly::I32_EXTEND8_S_I32, WebAssembly::I32_EXTEND8_S_I32_S },
17200 { WebAssembly::I32_REINTERPRET_F32, WebAssembly::I32_REINTERPRET_F32_S },
17201 { WebAssembly::I32_TRUNC_S_F32, WebAssembly::I32_TRUNC_S_F32_S },
17202 { WebAssembly::I32_TRUNC_S_F64, WebAssembly::I32_TRUNC_S_F64_S },
17203 { WebAssembly::I32_TRUNC_S_SAT_F32, WebAssembly::I32_TRUNC_S_SAT_F32_S },
17204 { WebAssembly::I32_TRUNC_S_SAT_F64, WebAssembly::I32_TRUNC_S_SAT_F64_S },
17205 { WebAssembly::I32_TRUNC_U_F32, WebAssembly::I32_TRUNC_U_F32_S },
17206 { WebAssembly::I32_TRUNC_U_F64, WebAssembly::I32_TRUNC_U_F64_S },
17207 { WebAssembly::I32_TRUNC_U_SAT_F32, WebAssembly::I32_TRUNC_U_SAT_F32_S },
17208 { WebAssembly::I32_TRUNC_U_SAT_F64, WebAssembly::I32_TRUNC_U_SAT_F64_S },
17209 { WebAssembly::I32_WRAP_I64, WebAssembly::I32_WRAP_I64_S },
17210 { WebAssembly::I64_EXTEND16_S_I64, WebAssembly::I64_EXTEND16_S_I64_S },
17211 { WebAssembly::I64_EXTEND32_S_I64, WebAssembly::I64_EXTEND32_S_I64_S },
17212 { WebAssembly::I64_EXTEND8_S_I64, WebAssembly::I64_EXTEND8_S_I64_S },
17213 { WebAssembly::I64_EXTEND_S_I32, WebAssembly::I64_EXTEND_S_I32_S },
17214 { WebAssembly::I64_EXTEND_U_I32, WebAssembly::I64_EXTEND_U_I32_S },
17215 { WebAssembly::I64_REINTERPRET_F64, WebAssembly::I64_REINTERPRET_F64_S },
17216 { WebAssembly::I64_TRUNC_S_F32, WebAssembly::I64_TRUNC_S_F32_S },
17217 { WebAssembly::I64_TRUNC_S_F64, WebAssembly::I64_TRUNC_S_F64_S },
17218 { WebAssembly::I64_TRUNC_S_SAT_F32, WebAssembly::I64_TRUNC_S_SAT_F32_S },
17219 { WebAssembly::I64_TRUNC_S_SAT_F64, WebAssembly::I64_TRUNC_S_SAT_F64_S },
17220 { WebAssembly::I64_TRUNC_U_F32, WebAssembly::I64_TRUNC_U_F32_S },
17221 { WebAssembly::I64_TRUNC_U_F64, WebAssembly::I64_TRUNC_U_F64_S },
17222 { WebAssembly::I64_TRUNC_U_SAT_F32, WebAssembly::I64_TRUNC_U_SAT_F32_S },
17223 { WebAssembly::I64_TRUNC_U_SAT_F64, WebAssembly::I64_TRUNC_U_SAT_F64_S },
17224 { WebAssembly::IF, WebAssembly::IF_S },
17225 { WebAssembly::LANESELECT_I16x8, WebAssembly::LANESELECT_I16x8_S },
17226 { WebAssembly::LANESELECT_I32x4, WebAssembly::LANESELECT_I32x4_S },
17227 { WebAssembly::LANESELECT_I64x2, WebAssembly::LANESELECT_I64x2_S },
17228 { WebAssembly::LANESELECT_I8x16, WebAssembly::LANESELECT_I8x16_S },
17229 { WebAssembly::LE_F16x8, WebAssembly::LE_F16x8_S },
17230 { WebAssembly::LE_F32, WebAssembly::LE_F32_S },
17231 { WebAssembly::LE_F32x4, WebAssembly::LE_F32x4_S },
17232 { WebAssembly::LE_F64, WebAssembly::LE_F64_S },
17233 { WebAssembly::LE_F64x2, WebAssembly::LE_F64x2_S },
17234 { WebAssembly::LE_S_I16x8, WebAssembly::LE_S_I16x8_S },
17235 { WebAssembly::LE_S_I32, WebAssembly::LE_S_I32_S },
17236 { WebAssembly::LE_S_I32x4, WebAssembly::LE_S_I32x4_S },
17237 { WebAssembly::LE_S_I64, WebAssembly::LE_S_I64_S },
17238 { WebAssembly::LE_S_I64x2, WebAssembly::LE_S_I64x2_S },
17239 { WebAssembly::LE_S_I8x16, WebAssembly::LE_S_I8x16_S },
17240 { WebAssembly::LE_U_I16x8, WebAssembly::LE_U_I16x8_S },
17241 { WebAssembly::LE_U_I32, WebAssembly::LE_U_I32_S },
17242 { WebAssembly::LE_U_I32x4, WebAssembly::LE_U_I32x4_S },
17243 { WebAssembly::LE_U_I64, WebAssembly::LE_U_I64_S },
17244 { WebAssembly::LE_U_I8x16, WebAssembly::LE_U_I8x16_S },
17245 { WebAssembly::LOAD16_SPLAT_A32, WebAssembly::LOAD16_SPLAT_A32_S },
17246 { WebAssembly::LOAD16_SPLAT_A64, WebAssembly::LOAD16_SPLAT_A64_S },
17247 { WebAssembly::LOAD16_S_I32_A32, WebAssembly::LOAD16_S_I32_A32_S },
17248 { WebAssembly::LOAD16_S_I32_A64, WebAssembly::LOAD16_S_I32_A64_S },
17249 { WebAssembly::LOAD16_S_I64_A32, WebAssembly::LOAD16_S_I64_A32_S },
17250 { WebAssembly::LOAD16_S_I64_A64, WebAssembly::LOAD16_S_I64_A64_S },
17251 { WebAssembly::LOAD16_U_I32_A32, WebAssembly::LOAD16_U_I32_A32_S },
17252 { WebAssembly::LOAD16_U_I32_A64, WebAssembly::LOAD16_U_I32_A64_S },
17253 { WebAssembly::LOAD16_U_I64_A32, WebAssembly::LOAD16_U_I64_A32_S },
17254 { WebAssembly::LOAD16_U_I64_A64, WebAssembly::LOAD16_U_I64_A64_S },
17255 { WebAssembly::LOAD32_SPLAT_A32, WebAssembly::LOAD32_SPLAT_A32_S },
17256 { WebAssembly::LOAD32_SPLAT_A64, WebAssembly::LOAD32_SPLAT_A64_S },
17257 { WebAssembly::LOAD32_S_I64_A32, WebAssembly::LOAD32_S_I64_A32_S },
17258 { WebAssembly::LOAD32_S_I64_A64, WebAssembly::LOAD32_S_I64_A64_S },
17259 { WebAssembly::LOAD32_U_I64_A32, WebAssembly::LOAD32_U_I64_A32_S },
17260 { WebAssembly::LOAD32_U_I64_A64, WebAssembly::LOAD32_U_I64_A64_S },
17261 { WebAssembly::LOAD64_SPLAT_A32, WebAssembly::LOAD64_SPLAT_A32_S },
17262 { WebAssembly::LOAD64_SPLAT_A64, WebAssembly::LOAD64_SPLAT_A64_S },
17263 { WebAssembly::LOAD8_SPLAT_A32, WebAssembly::LOAD8_SPLAT_A32_S },
17264 { WebAssembly::LOAD8_SPLAT_A64, WebAssembly::LOAD8_SPLAT_A64_S },
17265 { WebAssembly::LOAD8_S_I32_A32, WebAssembly::LOAD8_S_I32_A32_S },
17266 { WebAssembly::LOAD8_S_I32_A64, WebAssembly::LOAD8_S_I32_A64_S },
17267 { WebAssembly::LOAD8_S_I64_A32, WebAssembly::LOAD8_S_I64_A32_S },
17268 { WebAssembly::LOAD8_S_I64_A64, WebAssembly::LOAD8_S_I64_A64_S },
17269 { WebAssembly::LOAD8_U_I32_A32, WebAssembly::LOAD8_U_I32_A32_S },
17270 { WebAssembly::LOAD8_U_I32_A64, WebAssembly::LOAD8_U_I32_A64_S },
17271 { WebAssembly::LOAD8_U_I64_A32, WebAssembly::LOAD8_U_I64_A32_S },
17272 { WebAssembly::LOAD8_U_I64_A64, WebAssembly::LOAD8_U_I64_A64_S },
17273 { WebAssembly::LOAD_EXTEND_S_I16x8_A32, WebAssembly::LOAD_EXTEND_S_I16x8_A32_S },
17274 { WebAssembly::LOAD_EXTEND_S_I16x8_A64, WebAssembly::LOAD_EXTEND_S_I16x8_A64_S },
17275 { WebAssembly::LOAD_EXTEND_S_I32x4_A32, WebAssembly::LOAD_EXTEND_S_I32x4_A32_S },
17276 { WebAssembly::LOAD_EXTEND_S_I32x4_A64, WebAssembly::LOAD_EXTEND_S_I32x4_A64_S },
17277 { WebAssembly::LOAD_EXTEND_S_I64x2_A32, WebAssembly::LOAD_EXTEND_S_I64x2_A32_S },
17278 { WebAssembly::LOAD_EXTEND_S_I64x2_A64, WebAssembly::LOAD_EXTEND_S_I64x2_A64_S },
17279 { WebAssembly::LOAD_EXTEND_U_I16x8_A32, WebAssembly::LOAD_EXTEND_U_I16x8_A32_S },
17280 { WebAssembly::LOAD_EXTEND_U_I16x8_A64, WebAssembly::LOAD_EXTEND_U_I16x8_A64_S },
17281 { WebAssembly::LOAD_EXTEND_U_I32x4_A32, WebAssembly::LOAD_EXTEND_U_I32x4_A32_S },
17282 { WebAssembly::LOAD_EXTEND_U_I32x4_A64, WebAssembly::LOAD_EXTEND_U_I32x4_A64_S },
17283 { WebAssembly::LOAD_EXTEND_U_I64x2_A32, WebAssembly::LOAD_EXTEND_U_I64x2_A32_S },
17284 { WebAssembly::LOAD_EXTEND_U_I64x2_A64, WebAssembly::LOAD_EXTEND_U_I64x2_A64_S },
17285 { WebAssembly::LOAD_F16_F32_A32, WebAssembly::LOAD_F16_F32_A32_S },
17286 { WebAssembly::LOAD_F16_F32_A64, WebAssembly::LOAD_F16_F32_A64_S },
17287 { WebAssembly::LOAD_F32_A32, WebAssembly::LOAD_F32_A32_S },
17288 { WebAssembly::LOAD_F32_A64, WebAssembly::LOAD_F32_A64_S },
17289 { WebAssembly::LOAD_F64_A32, WebAssembly::LOAD_F64_A32_S },
17290 { WebAssembly::LOAD_F64_A64, WebAssembly::LOAD_F64_A64_S },
17291 { WebAssembly::LOAD_I32_A32, WebAssembly::LOAD_I32_A32_S },
17292 { WebAssembly::LOAD_I32_A64, WebAssembly::LOAD_I32_A64_S },
17293 { WebAssembly::LOAD_I64_A32, WebAssembly::LOAD_I64_A32_S },
17294 { WebAssembly::LOAD_I64_A64, WebAssembly::LOAD_I64_A64_S },
17295 { WebAssembly::LOAD_LANE_I16x8_A32, WebAssembly::LOAD_LANE_I16x8_A32_S },
17296 { WebAssembly::LOAD_LANE_I16x8_A64, WebAssembly::LOAD_LANE_I16x8_A64_S },
17297 { WebAssembly::LOAD_LANE_I32x4_A32, WebAssembly::LOAD_LANE_I32x4_A32_S },
17298 { WebAssembly::LOAD_LANE_I32x4_A64, WebAssembly::LOAD_LANE_I32x4_A64_S },
17299 { WebAssembly::LOAD_LANE_I64x2_A32, WebAssembly::LOAD_LANE_I64x2_A32_S },
17300 { WebAssembly::LOAD_LANE_I64x2_A64, WebAssembly::LOAD_LANE_I64x2_A64_S },
17301 { WebAssembly::LOAD_LANE_I8x16_A32, WebAssembly::LOAD_LANE_I8x16_A32_S },
17302 { WebAssembly::LOAD_LANE_I8x16_A64, WebAssembly::LOAD_LANE_I8x16_A64_S },
17303 { WebAssembly::LOAD_V128_A32, WebAssembly::LOAD_V128_A32_S },
17304 { WebAssembly::LOAD_V128_A64, WebAssembly::LOAD_V128_A64_S },
17305 { WebAssembly::LOAD_ZERO_I32x4_A32, WebAssembly::LOAD_ZERO_I32x4_A32_S },
17306 { WebAssembly::LOAD_ZERO_I32x4_A64, WebAssembly::LOAD_ZERO_I32x4_A64_S },
17307 { WebAssembly::LOAD_ZERO_I64x2_A32, WebAssembly::LOAD_ZERO_I64x2_A32_S },
17308 { WebAssembly::LOAD_ZERO_I64x2_A64, WebAssembly::LOAD_ZERO_I64x2_A64_S },
17309 { WebAssembly::LOCAL_GET_EXNREF, WebAssembly::LOCAL_GET_EXNREF_S },
17310 { WebAssembly::LOCAL_GET_EXTERNREF, WebAssembly::LOCAL_GET_EXTERNREF_S },
17311 { WebAssembly::LOCAL_GET_F32, WebAssembly::LOCAL_GET_F32_S },
17312 { WebAssembly::LOCAL_GET_F64, WebAssembly::LOCAL_GET_F64_S },
17313 { WebAssembly::LOCAL_GET_FUNCREF, WebAssembly::LOCAL_GET_FUNCREF_S },
17314 { WebAssembly::LOCAL_GET_I32, WebAssembly::LOCAL_GET_I32_S },
17315 { WebAssembly::LOCAL_GET_I64, WebAssembly::LOCAL_GET_I64_S },
17316 { WebAssembly::LOCAL_GET_V128, WebAssembly::LOCAL_GET_V128_S },
17317 { WebAssembly::LOCAL_SET_EXNREF, WebAssembly::LOCAL_SET_EXNREF_S },
17318 { WebAssembly::LOCAL_SET_EXTERNREF, WebAssembly::LOCAL_SET_EXTERNREF_S },
17319 { WebAssembly::LOCAL_SET_F32, WebAssembly::LOCAL_SET_F32_S },
17320 { WebAssembly::LOCAL_SET_F64, WebAssembly::LOCAL_SET_F64_S },
17321 { WebAssembly::LOCAL_SET_FUNCREF, WebAssembly::LOCAL_SET_FUNCREF_S },
17322 { WebAssembly::LOCAL_SET_I32, WebAssembly::LOCAL_SET_I32_S },
17323 { WebAssembly::LOCAL_SET_I64, WebAssembly::LOCAL_SET_I64_S },
17324 { WebAssembly::LOCAL_SET_V128, WebAssembly::LOCAL_SET_V128_S },
17325 { WebAssembly::LOCAL_TEE_EXNREF, WebAssembly::LOCAL_TEE_EXNREF_S },
17326 { WebAssembly::LOCAL_TEE_EXTERNREF, WebAssembly::LOCAL_TEE_EXTERNREF_S },
17327 { WebAssembly::LOCAL_TEE_F32, WebAssembly::LOCAL_TEE_F32_S },
17328 { WebAssembly::LOCAL_TEE_F64, WebAssembly::LOCAL_TEE_F64_S },
17329 { WebAssembly::LOCAL_TEE_FUNCREF, WebAssembly::LOCAL_TEE_FUNCREF_S },
17330 { WebAssembly::LOCAL_TEE_I32, WebAssembly::LOCAL_TEE_I32_S },
17331 { WebAssembly::LOCAL_TEE_I64, WebAssembly::LOCAL_TEE_I64_S },
17332 { WebAssembly::LOCAL_TEE_V128, WebAssembly::LOCAL_TEE_V128_S },
17333 { WebAssembly::LOOP, WebAssembly::LOOP_S },
17334 { WebAssembly::LT_F16x8, WebAssembly::LT_F16x8_S },
17335 { WebAssembly::LT_F32, WebAssembly::LT_F32_S },
17336 { WebAssembly::LT_F32x4, WebAssembly::LT_F32x4_S },
17337 { WebAssembly::LT_F64, WebAssembly::LT_F64_S },
17338 { WebAssembly::LT_F64x2, WebAssembly::LT_F64x2_S },
17339 { WebAssembly::LT_S_I16x8, WebAssembly::LT_S_I16x8_S },
17340 { WebAssembly::LT_S_I32, WebAssembly::LT_S_I32_S },
17341 { WebAssembly::LT_S_I32x4, WebAssembly::LT_S_I32x4_S },
17342 { WebAssembly::LT_S_I64, WebAssembly::LT_S_I64_S },
17343 { WebAssembly::LT_S_I64x2, WebAssembly::LT_S_I64x2_S },
17344 { WebAssembly::LT_S_I8x16, WebAssembly::LT_S_I8x16_S },
17345 { WebAssembly::LT_U_I16x8, WebAssembly::LT_U_I16x8_S },
17346 { WebAssembly::LT_U_I32, WebAssembly::LT_U_I32_S },
17347 { WebAssembly::LT_U_I32x4, WebAssembly::LT_U_I32x4_S },
17348 { WebAssembly::LT_U_I64, WebAssembly::LT_U_I64_S },
17349 { WebAssembly::LT_U_I8x16, WebAssembly::LT_U_I8x16_S },
17350 { WebAssembly::MADD_F16x8, WebAssembly::MADD_F16x8_S },
17351 { WebAssembly::MADD_F32x4, WebAssembly::MADD_F32x4_S },
17352 { WebAssembly::MADD_F64x2, WebAssembly::MADD_F64x2_S },
17353 { WebAssembly::MAX_F16x8, WebAssembly::MAX_F16x8_S },
17354 { WebAssembly::MAX_F32, WebAssembly::MAX_F32_S },
17355 { WebAssembly::MAX_F32x4, WebAssembly::MAX_F32x4_S },
17356 { WebAssembly::MAX_F64, WebAssembly::MAX_F64_S },
17357 { WebAssembly::MAX_F64x2, WebAssembly::MAX_F64x2_S },
17358 { WebAssembly::MAX_S_I16x8, WebAssembly::MAX_S_I16x8_S },
17359 { WebAssembly::MAX_S_I32x4, WebAssembly::MAX_S_I32x4_S },
17360 { WebAssembly::MAX_S_I8x16, WebAssembly::MAX_S_I8x16_S },
17361 { WebAssembly::MAX_U_I16x8, WebAssembly::MAX_U_I16x8_S },
17362 { WebAssembly::MAX_U_I32x4, WebAssembly::MAX_U_I32x4_S },
17363 { WebAssembly::MAX_U_I8x16, WebAssembly::MAX_U_I8x16_S },
17364 { WebAssembly::MEMORY_ATOMIC_NOTIFY_A32, WebAssembly::MEMORY_ATOMIC_NOTIFY_A32_S },
17365 { WebAssembly::MEMORY_ATOMIC_NOTIFY_A64, WebAssembly::MEMORY_ATOMIC_NOTIFY_A64_S },
17366 { WebAssembly::MEMORY_ATOMIC_WAIT32_A32, WebAssembly::MEMORY_ATOMIC_WAIT32_A32_S },
17367 { WebAssembly::MEMORY_ATOMIC_WAIT32_A64, WebAssembly::MEMORY_ATOMIC_WAIT32_A64_S },
17368 { WebAssembly::MEMORY_ATOMIC_WAIT64_A32, WebAssembly::MEMORY_ATOMIC_WAIT64_A32_S },
17369 { WebAssembly::MEMORY_ATOMIC_WAIT64_A64, WebAssembly::MEMORY_ATOMIC_WAIT64_A64_S },
17370 { WebAssembly::MIN_F16x8, WebAssembly::MIN_F16x8_S },
17371 { WebAssembly::MIN_F32, WebAssembly::MIN_F32_S },
17372 { WebAssembly::MIN_F32x4, WebAssembly::MIN_F32x4_S },
17373 { WebAssembly::MIN_F64, WebAssembly::MIN_F64_S },
17374 { WebAssembly::MIN_F64x2, WebAssembly::MIN_F64x2_S },
17375 { WebAssembly::MIN_S_I16x8, WebAssembly::MIN_S_I16x8_S },
17376 { WebAssembly::MIN_S_I32x4, WebAssembly::MIN_S_I32x4_S },
17377 { WebAssembly::MIN_S_I8x16, WebAssembly::MIN_S_I8x16_S },
17378 { WebAssembly::MIN_U_I16x8, WebAssembly::MIN_U_I16x8_S },
17379 { WebAssembly::MIN_U_I32x4, WebAssembly::MIN_U_I32x4_S },
17380 { WebAssembly::MIN_U_I8x16, WebAssembly::MIN_U_I8x16_S },
17381 { WebAssembly::MUL_F16x8, WebAssembly::MUL_F16x8_S },
17382 { WebAssembly::MUL_F32, WebAssembly::MUL_F32_S },
17383 { WebAssembly::MUL_F32x4, WebAssembly::MUL_F32x4_S },
17384 { WebAssembly::MUL_F64, WebAssembly::MUL_F64_S },
17385 { WebAssembly::MUL_F64x2, WebAssembly::MUL_F64x2_S },
17386 { WebAssembly::MUL_I16x8, WebAssembly::MUL_I16x8_S },
17387 { WebAssembly::MUL_I32, WebAssembly::MUL_I32_S },
17388 { WebAssembly::MUL_I32x4, WebAssembly::MUL_I32x4_S },
17389 { WebAssembly::MUL_I64, WebAssembly::MUL_I64_S },
17390 { WebAssembly::MUL_I64x2, WebAssembly::MUL_I64x2_S },
17391 { WebAssembly::NARROW_S_I16x8, WebAssembly::NARROW_S_I16x8_S },
17392 { WebAssembly::NARROW_S_I8x16, WebAssembly::NARROW_S_I8x16_S },
17393 { WebAssembly::NARROW_U_I16x8, WebAssembly::NARROW_U_I16x8_S },
17394 { WebAssembly::NARROW_U_I8x16, WebAssembly::NARROW_U_I8x16_S },
17395 { WebAssembly::NEAREST_F16x8, WebAssembly::NEAREST_F16x8_S },
17396 { WebAssembly::NEAREST_F32, WebAssembly::NEAREST_F32_S },
17397 { WebAssembly::NEAREST_F32x4, WebAssembly::NEAREST_F32x4_S },
17398 { WebAssembly::NEAREST_F64, WebAssembly::NEAREST_F64_S },
17399 { WebAssembly::NEAREST_F64x2, WebAssembly::NEAREST_F64x2_S },
17400 { WebAssembly::NEG_F16x8, WebAssembly::NEG_F16x8_S },
17401 { WebAssembly::NEG_F32, WebAssembly::NEG_F32_S },
17402 { WebAssembly::NEG_F32x4, WebAssembly::NEG_F32x4_S },
17403 { WebAssembly::NEG_F64, WebAssembly::NEG_F64_S },
17404 { WebAssembly::NEG_F64x2, WebAssembly::NEG_F64x2_S },
17405 { WebAssembly::NEG_I16x8, WebAssembly::NEG_I16x8_S },
17406 { WebAssembly::NEG_I32x4, WebAssembly::NEG_I32x4_S },
17407 { WebAssembly::NEG_I64x2, WebAssembly::NEG_I64x2_S },
17408 { WebAssembly::NEG_I8x16, WebAssembly::NEG_I8x16_S },
17409 { WebAssembly::NE_F16x8, WebAssembly::NE_F16x8_S },
17410 { WebAssembly::NE_F32, WebAssembly::NE_F32_S },
17411 { WebAssembly::NE_F32x4, WebAssembly::NE_F32x4_S },
17412 { WebAssembly::NE_F64, WebAssembly::NE_F64_S },
17413 { WebAssembly::NE_F64x2, WebAssembly::NE_F64x2_S },
17414 { WebAssembly::NE_I16x8, WebAssembly::NE_I16x8_S },
17415 { WebAssembly::NE_I32, WebAssembly::NE_I32_S },
17416 { WebAssembly::NE_I32x4, WebAssembly::NE_I32x4_S },
17417 { WebAssembly::NE_I64, WebAssembly::NE_I64_S },
17418 { WebAssembly::NE_I64x2, WebAssembly::NE_I64x2_S },
17419 { WebAssembly::NE_I8x16, WebAssembly::NE_I8x16_S },
17420 { WebAssembly::NMADD_F16x8, WebAssembly::NMADD_F16x8_S },
17421 { WebAssembly::NMADD_F32x4, WebAssembly::NMADD_F32x4_S },
17422 { WebAssembly::NMADD_F64x2, WebAssembly::NMADD_F64x2_S },
17423 { WebAssembly::NOP, WebAssembly::NOP_S },
17424 { WebAssembly::NOT, WebAssembly::NOT_S },
17425 { WebAssembly::OR, WebAssembly::OR_S },
17426 { WebAssembly::OR_I32, WebAssembly::OR_I32_S },
17427 { WebAssembly::OR_I64, WebAssembly::OR_I64_S },
17428 { WebAssembly::PMAX_F16x8, WebAssembly::PMAX_F16x8_S },
17429 { WebAssembly::PMAX_F32x4, WebAssembly::PMAX_F32x4_S },
17430 { WebAssembly::PMAX_F64x2, WebAssembly::PMAX_F64x2_S },
17431 { WebAssembly::PMIN_F16x8, WebAssembly::PMIN_F16x8_S },
17432 { WebAssembly::PMIN_F32x4, WebAssembly::PMIN_F32x4_S },
17433 { WebAssembly::PMIN_F64x2, WebAssembly::PMIN_F64x2_S },
17434 { WebAssembly::POPCNT_I32, WebAssembly::POPCNT_I32_S },
17435 { WebAssembly::POPCNT_I64, WebAssembly::POPCNT_I64_S },
17436 { WebAssembly::POPCNT_I8x16, WebAssembly::POPCNT_I8x16_S },
17437 { WebAssembly::Q15MULR_SAT_S_I16x8, WebAssembly::Q15MULR_SAT_S_I16x8_S },
17438 { WebAssembly::REF_IS_NULL_EXNREF, WebAssembly::REF_IS_NULL_EXNREF_S },
17439 { WebAssembly::REF_IS_NULL_EXTERNREF, WebAssembly::REF_IS_NULL_EXTERNREF_S },
17440 { WebAssembly::REF_IS_NULL_FUNCREF, WebAssembly::REF_IS_NULL_FUNCREF_S },
17441 { WebAssembly::REF_NULL_EXNREF, WebAssembly::REF_NULL_EXNREF_S },
17442 { WebAssembly::REF_NULL_EXTERNREF, WebAssembly::REF_NULL_EXTERNREF_S },
17443 { WebAssembly::REF_NULL_FUNCREF, WebAssembly::REF_NULL_FUNCREF_S },
17444 { WebAssembly::RELAXED_DOT, WebAssembly::RELAXED_DOT_S },
17445 { WebAssembly::RELAXED_DOT_ADD, WebAssembly::RELAXED_DOT_ADD_S },
17446 { WebAssembly::RELAXED_DOT_BFLOAT, WebAssembly::RELAXED_DOT_BFLOAT_S },
17447 { WebAssembly::RELAXED_Q15MULR_S_I16x8, WebAssembly::RELAXED_Q15MULR_S_I16x8_S },
17448 { WebAssembly::RELAXED_SWIZZLE, WebAssembly::RELAXED_SWIZZLE_S },
17449 { WebAssembly::REM_S_I32, WebAssembly::REM_S_I32_S },
17450 { WebAssembly::REM_S_I64, WebAssembly::REM_S_I64_S },
17451 { WebAssembly::REM_U_I32, WebAssembly::REM_U_I32_S },
17452 { WebAssembly::REM_U_I64, WebAssembly::REM_U_I64_S },
17453 { WebAssembly::REPLACE_LANE_F32x4, WebAssembly::REPLACE_LANE_F32x4_S },
17454 { WebAssembly::REPLACE_LANE_F64x2, WebAssembly::REPLACE_LANE_F64x2_S },
17455 { WebAssembly::REPLACE_LANE_I16x8, WebAssembly::REPLACE_LANE_I16x8_S },
17456 { WebAssembly::REPLACE_LANE_I32x4, WebAssembly::REPLACE_LANE_I32x4_S },
17457 { WebAssembly::REPLACE_LANE_I64x2, WebAssembly::REPLACE_LANE_I64x2_S },
17458 { WebAssembly::REPLACE_LANE_I8x16, WebAssembly::REPLACE_LANE_I8x16_S },
17459 { WebAssembly::RETHROW, WebAssembly::RETHROW_S },
17460 { WebAssembly::RETURN, WebAssembly::RETURN_S },
17461 { WebAssembly::RET_CALL, WebAssembly::RET_CALL_S },
17462 { WebAssembly::RET_CALL_INDIRECT, WebAssembly::RET_CALL_INDIRECT_S },
17463 { WebAssembly::ROTL_I32, WebAssembly::ROTL_I32_S },
17464 { WebAssembly::ROTL_I64, WebAssembly::ROTL_I64_S },
17465 { WebAssembly::ROTR_I32, WebAssembly::ROTR_I32_S },
17466 { WebAssembly::ROTR_I64, WebAssembly::ROTR_I64_S },
17467 { WebAssembly::SELECT_EXNREF, WebAssembly::SELECT_EXNREF_S },
17468 { WebAssembly::SELECT_EXTERNREF, WebAssembly::SELECT_EXTERNREF_S },
17469 { WebAssembly::SELECT_F32, WebAssembly::SELECT_F32_S },
17470 { WebAssembly::SELECT_F64, WebAssembly::SELECT_F64_S },
17471 { WebAssembly::SELECT_FUNCREF, WebAssembly::SELECT_FUNCREF_S },
17472 { WebAssembly::SELECT_I32, WebAssembly::SELECT_I32_S },
17473 { WebAssembly::SELECT_I64, WebAssembly::SELECT_I64_S },
17474 { WebAssembly::SELECT_V128, WebAssembly::SELECT_V128_S },
17475 { WebAssembly::SHL_I16x8, WebAssembly::SHL_I16x8_S },
17476 { WebAssembly::SHL_I32, WebAssembly::SHL_I32_S },
17477 { WebAssembly::SHL_I32x4, WebAssembly::SHL_I32x4_S },
17478 { WebAssembly::SHL_I64, WebAssembly::SHL_I64_S },
17479 { WebAssembly::SHL_I64x2, WebAssembly::SHL_I64x2_S },
17480 { WebAssembly::SHL_I8x16, WebAssembly::SHL_I8x16_S },
17481 { WebAssembly::SHR_S_I16x8, WebAssembly::SHR_S_I16x8_S },
17482 { WebAssembly::SHR_S_I32, WebAssembly::SHR_S_I32_S },
17483 { WebAssembly::SHR_S_I32x4, WebAssembly::SHR_S_I32x4_S },
17484 { WebAssembly::SHR_S_I64, WebAssembly::SHR_S_I64_S },
17485 { WebAssembly::SHR_S_I64x2, WebAssembly::SHR_S_I64x2_S },
17486 { WebAssembly::SHR_S_I8x16, WebAssembly::SHR_S_I8x16_S },
17487 { WebAssembly::SHR_U_I16x8, WebAssembly::SHR_U_I16x8_S },
17488 { WebAssembly::SHR_U_I32, WebAssembly::SHR_U_I32_S },
17489 { WebAssembly::SHR_U_I32x4, WebAssembly::SHR_U_I32x4_S },
17490 { WebAssembly::SHR_U_I64, WebAssembly::SHR_U_I64_S },
17491 { WebAssembly::SHR_U_I64x2, WebAssembly::SHR_U_I64x2_S },
17492 { WebAssembly::SHR_U_I8x16, WebAssembly::SHR_U_I8x16_S },
17493 { WebAssembly::SHUFFLE, WebAssembly::SHUFFLE_S },
17494 { WebAssembly::SIMD_RELAXED_FMAX_F32x4, WebAssembly::SIMD_RELAXED_FMAX_F32x4_S },
17495 { WebAssembly::SIMD_RELAXED_FMAX_F64x2, WebAssembly::SIMD_RELAXED_FMAX_F64x2_S },
17496 { WebAssembly::SIMD_RELAXED_FMIN_F32x4, WebAssembly::SIMD_RELAXED_FMIN_F32x4_S },
17497 { WebAssembly::SIMD_RELAXED_FMIN_F64x2, WebAssembly::SIMD_RELAXED_FMIN_F64x2_S },
17498 { WebAssembly::SPLAT_F16x8, WebAssembly::SPLAT_F16x8_S },
17499 { WebAssembly::SPLAT_F32x4, WebAssembly::SPLAT_F32x4_S },
17500 { WebAssembly::SPLAT_F64x2, WebAssembly::SPLAT_F64x2_S },
17501 { WebAssembly::SPLAT_I16x8, WebAssembly::SPLAT_I16x8_S },
17502 { WebAssembly::SPLAT_I32x4, WebAssembly::SPLAT_I32x4_S },
17503 { WebAssembly::SPLAT_I64x2, WebAssembly::SPLAT_I64x2_S },
17504 { WebAssembly::SPLAT_I8x16, WebAssembly::SPLAT_I8x16_S },
17505 { WebAssembly::SQRT_F16x8, WebAssembly::SQRT_F16x8_S },
17506 { WebAssembly::SQRT_F32, WebAssembly::SQRT_F32_S },
17507 { WebAssembly::SQRT_F32x4, WebAssembly::SQRT_F32x4_S },
17508 { WebAssembly::SQRT_F64, WebAssembly::SQRT_F64_S },
17509 { WebAssembly::SQRT_F64x2, WebAssembly::SQRT_F64x2_S },
17510 { WebAssembly::STORE16_I32_A32, WebAssembly::STORE16_I32_A32_S },
17511 { WebAssembly::STORE16_I32_A64, WebAssembly::STORE16_I32_A64_S },
17512 { WebAssembly::STORE16_I64_A32, WebAssembly::STORE16_I64_A32_S },
17513 { WebAssembly::STORE16_I64_A64, WebAssembly::STORE16_I64_A64_S },
17514 { WebAssembly::STORE32_I64_A32, WebAssembly::STORE32_I64_A32_S },
17515 { WebAssembly::STORE32_I64_A64, WebAssembly::STORE32_I64_A64_S },
17516 { WebAssembly::STORE8_I32_A32, WebAssembly::STORE8_I32_A32_S },
17517 { WebAssembly::STORE8_I32_A64, WebAssembly::STORE8_I32_A64_S },
17518 { WebAssembly::STORE8_I64_A32, WebAssembly::STORE8_I64_A32_S },
17519 { WebAssembly::STORE8_I64_A64, WebAssembly::STORE8_I64_A64_S },
17520 { WebAssembly::STORE_F16_F32_A32, WebAssembly::STORE_F16_F32_A32_S },
17521 { WebAssembly::STORE_F16_F32_A64, WebAssembly::STORE_F16_F32_A64_S },
17522 { WebAssembly::STORE_F32_A32, WebAssembly::STORE_F32_A32_S },
17523 { WebAssembly::STORE_F32_A64, WebAssembly::STORE_F32_A64_S },
17524 { WebAssembly::STORE_F64_A32, WebAssembly::STORE_F64_A32_S },
17525 { WebAssembly::STORE_F64_A64, WebAssembly::STORE_F64_A64_S },
17526 { WebAssembly::STORE_I32_A32, WebAssembly::STORE_I32_A32_S },
17527 { WebAssembly::STORE_I32_A64, WebAssembly::STORE_I32_A64_S },
17528 { WebAssembly::STORE_I64_A32, WebAssembly::STORE_I64_A32_S },
17529 { WebAssembly::STORE_I64_A64, WebAssembly::STORE_I64_A64_S },
17530 { WebAssembly::STORE_LANE_I16x8_A32, WebAssembly::STORE_LANE_I16x8_A32_S },
17531 { WebAssembly::STORE_LANE_I16x8_A64, WebAssembly::STORE_LANE_I16x8_A64_S },
17532 { WebAssembly::STORE_LANE_I32x4_A32, WebAssembly::STORE_LANE_I32x4_A32_S },
17533 { WebAssembly::STORE_LANE_I32x4_A64, WebAssembly::STORE_LANE_I32x4_A64_S },
17534 { WebAssembly::STORE_LANE_I64x2_A32, WebAssembly::STORE_LANE_I64x2_A32_S },
17535 { WebAssembly::STORE_LANE_I64x2_A64, WebAssembly::STORE_LANE_I64x2_A64_S },
17536 { WebAssembly::STORE_LANE_I8x16_A32, WebAssembly::STORE_LANE_I8x16_A32_S },
17537 { WebAssembly::STORE_LANE_I8x16_A64, WebAssembly::STORE_LANE_I8x16_A64_S },
17538 { WebAssembly::STORE_V128_A32, WebAssembly::STORE_V128_A32_S },
17539 { WebAssembly::STORE_V128_A64, WebAssembly::STORE_V128_A64_S },
17540 { WebAssembly::SUB_F16x8, WebAssembly::SUB_F16x8_S },
17541 { WebAssembly::SUB_F32, WebAssembly::SUB_F32_S },
17542 { WebAssembly::SUB_F32x4, WebAssembly::SUB_F32x4_S },
17543 { WebAssembly::SUB_F64, WebAssembly::SUB_F64_S },
17544 { WebAssembly::SUB_F64x2, WebAssembly::SUB_F64x2_S },
17545 { WebAssembly::SUB_I16x8, WebAssembly::SUB_I16x8_S },
17546 { WebAssembly::SUB_I32, WebAssembly::SUB_I32_S },
17547 { WebAssembly::SUB_I32x4, WebAssembly::SUB_I32x4_S },
17548 { WebAssembly::SUB_I64, WebAssembly::SUB_I64_S },
17549 { WebAssembly::SUB_I64x2, WebAssembly::SUB_I64x2_S },
17550 { WebAssembly::SUB_I8x16, WebAssembly::SUB_I8x16_S },
17551 { WebAssembly::SUB_SAT_S_I16x8, WebAssembly::SUB_SAT_S_I16x8_S },
17552 { WebAssembly::SUB_SAT_S_I8x16, WebAssembly::SUB_SAT_S_I8x16_S },
17553 { WebAssembly::SUB_SAT_U_I16x8, WebAssembly::SUB_SAT_U_I16x8_S },
17554 { WebAssembly::SUB_SAT_U_I8x16, WebAssembly::SUB_SAT_U_I8x16_S },
17555 { WebAssembly::SWIZZLE, WebAssembly::SWIZZLE_S },
17556 { WebAssembly::TABLE_COPY, WebAssembly::TABLE_COPY_S },
17557 { WebAssembly::TABLE_FILL_EXNREF, WebAssembly::TABLE_FILL_EXNREF_S },
17558 { WebAssembly::TABLE_FILL_EXTERNREF, WebAssembly::TABLE_FILL_EXTERNREF_S },
17559 { WebAssembly::TABLE_FILL_FUNCREF, WebAssembly::TABLE_FILL_FUNCREF_S },
17560 { WebAssembly::TABLE_GET_EXNREF, WebAssembly::TABLE_GET_EXNREF_S },
17561 { WebAssembly::TABLE_GET_EXTERNREF, WebAssembly::TABLE_GET_EXTERNREF_S },
17562 { WebAssembly::TABLE_GET_FUNCREF, WebAssembly::TABLE_GET_FUNCREF_S },
17563 { WebAssembly::TABLE_GROW_EXNREF, WebAssembly::TABLE_GROW_EXNREF_S },
17564 { WebAssembly::TABLE_GROW_EXTERNREF, WebAssembly::TABLE_GROW_EXTERNREF_S },
17565 { WebAssembly::TABLE_GROW_FUNCREF, WebAssembly::TABLE_GROW_FUNCREF_S },
17566 { WebAssembly::TABLE_SET_EXNREF, WebAssembly::TABLE_SET_EXNREF_S },
17567 { WebAssembly::TABLE_SET_EXTERNREF, WebAssembly::TABLE_SET_EXTERNREF_S },
17568 { WebAssembly::TABLE_SET_FUNCREF, WebAssembly::TABLE_SET_FUNCREF_S },
17569 { WebAssembly::TABLE_SIZE, WebAssembly::TABLE_SIZE_S },
17570 { WebAssembly::TEE_EXNREF, WebAssembly::TEE_EXNREF_S },
17571 { WebAssembly::TEE_EXTERNREF, WebAssembly::TEE_EXTERNREF_S },
17572 { WebAssembly::TEE_F32, WebAssembly::TEE_F32_S },
17573 { WebAssembly::TEE_F64, WebAssembly::TEE_F64_S },
17574 { WebAssembly::TEE_FUNCREF, WebAssembly::TEE_FUNCREF_S },
17575 { WebAssembly::TEE_I32, WebAssembly::TEE_I32_S },
17576 { WebAssembly::TEE_I64, WebAssembly::TEE_I64_S },
17577 { WebAssembly::TEE_V128, WebAssembly::TEE_V128_S },
17578 { WebAssembly::THROW, WebAssembly::THROW_S },
17579 { WebAssembly::TRUNC_F16x8, WebAssembly::TRUNC_F16x8_S },
17580 { WebAssembly::TRUNC_F32, WebAssembly::TRUNC_F32_S },
17581 { WebAssembly::TRUNC_F32x4, WebAssembly::TRUNC_F32x4_S },
17582 { WebAssembly::TRUNC_F64, WebAssembly::TRUNC_F64_S },
17583 { WebAssembly::TRUNC_F64x2, WebAssembly::TRUNC_F64x2_S },
17584 { WebAssembly::TRY, WebAssembly::TRY_S },
17585 { WebAssembly::UNREACHABLE, WebAssembly::UNREACHABLE_S },
17586 { WebAssembly::XOR, WebAssembly::XOR_S },
17587 { WebAssembly::XOR_I32, WebAssembly::XOR_I32_S },
17588 { WebAssembly::XOR_I64, WebAssembly::XOR_I64_S },
17589 { WebAssembly::anonymous_8187MEMORY_GROW_A32, WebAssembly::anonymous_8187MEMORY_GROW_A32_S },
17590 { WebAssembly::anonymous_8187MEMORY_SIZE_A32, WebAssembly::anonymous_8187MEMORY_SIZE_A32_S },
17591 { WebAssembly::anonymous_8188MEMORY_GROW_A64, WebAssembly::anonymous_8188MEMORY_GROW_A64_S },
17592 { WebAssembly::anonymous_8188MEMORY_SIZE_A64, WebAssembly::anonymous_8188MEMORY_SIZE_A64_S },
17593 { WebAssembly::anonymous_8878DATA_DROP, WebAssembly::anonymous_8878DATA_DROP_S },
17594 { WebAssembly::anonymous_8878MEMORY_COPY_A32, WebAssembly::anonymous_8878MEMORY_COPY_A32_S },
17595 { WebAssembly::anonymous_8878MEMORY_FILL_A32, WebAssembly::anonymous_8878MEMORY_FILL_A32_S },
17596 { WebAssembly::anonymous_8878MEMORY_INIT_A32, WebAssembly::anonymous_8878MEMORY_INIT_A32_S },
17597 { WebAssembly::anonymous_8879DATA_DROP, WebAssembly::anonymous_8879DATA_DROP_S },
17598 { WebAssembly::anonymous_8879MEMORY_COPY_A64, WebAssembly::anonymous_8879MEMORY_COPY_A64_S },
17599 { WebAssembly::anonymous_8879MEMORY_FILL_A64, WebAssembly::anonymous_8879MEMORY_FILL_A64_S },
17600 { WebAssembly::anonymous_8879MEMORY_INIT_A64, WebAssembly::anonymous_8879MEMORY_INIT_A64_S },
17601 { WebAssembly::convert_low_s_F64x2, WebAssembly::convert_low_s_F64x2_S },
17602 { WebAssembly::convert_low_u_F64x2, WebAssembly::convert_low_u_F64x2_S },
17603 { WebAssembly::demote_zero_F32x4, WebAssembly::demote_zero_F32x4_S },
17604 { WebAssembly::extend_high_s_I16x8, WebAssembly::extend_high_s_I16x8_S },
17605 { WebAssembly::extend_high_s_I32x4, WebAssembly::extend_high_s_I32x4_S },
17606 { WebAssembly::extend_high_s_I64x2, WebAssembly::extend_high_s_I64x2_S },
17607 { WebAssembly::extend_high_u_I16x8, WebAssembly::extend_high_u_I16x8_S },
17608 { WebAssembly::extend_high_u_I32x4, WebAssembly::extend_high_u_I32x4_S },
17609 { WebAssembly::extend_high_u_I64x2, WebAssembly::extend_high_u_I64x2_S },
17610 { WebAssembly::extend_low_s_I16x8, WebAssembly::extend_low_s_I16x8_S },
17611 { WebAssembly::extend_low_s_I32x4, WebAssembly::extend_low_s_I32x4_S },
17612 { WebAssembly::extend_low_s_I64x2, WebAssembly::extend_low_s_I64x2_S },
17613 { WebAssembly::extend_low_u_I16x8, WebAssembly::extend_low_u_I16x8_S },
17614 { WebAssembly::extend_low_u_I32x4, WebAssembly::extend_low_u_I32x4_S },
17615 { WebAssembly::extend_low_u_I64x2, WebAssembly::extend_low_u_I64x2_S },
17616 { WebAssembly::fp_to_sint_I16x8, WebAssembly::fp_to_sint_I16x8_S },
17617 { WebAssembly::fp_to_sint_I32x4, WebAssembly::fp_to_sint_I32x4_S },
17618 { WebAssembly::fp_to_uint_I16x8, WebAssembly::fp_to_uint_I16x8_S },
17619 { WebAssembly::fp_to_uint_I32x4, WebAssembly::fp_to_uint_I32x4_S },
17620 { WebAssembly::int_wasm_extadd_pairwise_signed_I16x8, WebAssembly::int_wasm_extadd_pairwise_signed_I16x8_S },
17621 { WebAssembly::int_wasm_extadd_pairwise_signed_I32x4, WebAssembly::int_wasm_extadd_pairwise_signed_I32x4_S },
17622 { WebAssembly::int_wasm_extadd_pairwise_unsigned_I16x8, WebAssembly::int_wasm_extadd_pairwise_unsigned_I16x8_S },
17623 { WebAssembly::int_wasm_extadd_pairwise_unsigned_I32x4, WebAssembly::int_wasm_extadd_pairwise_unsigned_I32x4_S },
17624 { WebAssembly::int_wasm_relaxed_trunc_signed_I32x4, WebAssembly::int_wasm_relaxed_trunc_signed_I32x4_S },
17625 { WebAssembly::int_wasm_relaxed_trunc_signed_zero_I32x4, WebAssembly::int_wasm_relaxed_trunc_signed_zero_I32x4_S },
17626 { WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4, WebAssembly::int_wasm_relaxed_trunc_unsigned_I32x4_S },
17627 { WebAssembly::int_wasm_relaxed_trunc_unsigned_zero_I32x4, WebAssembly::int_wasm_relaxed_trunc_unsigned_zero_I32x4_S },
17628 { WebAssembly::promote_low_F64x2, WebAssembly::promote_low_F64x2_S },
17629 { WebAssembly::sint_to_fp_F16x8, WebAssembly::sint_to_fp_F16x8_S },
17630 { WebAssembly::sint_to_fp_F32x4, WebAssembly::sint_to_fp_F32x4_S },
17631 { WebAssembly::trunc_sat_zero_s_I32x4, WebAssembly::trunc_sat_zero_s_I32x4_S },
17632 { WebAssembly::trunc_sat_zero_u_I32x4, WebAssembly::trunc_sat_zero_u_I32x4_S },
17633 { WebAssembly::uint_to_fp_F16x8, WebAssembly::uint_to_fp_F16x8_S },
17634 { WebAssembly::uint_to_fp_F32x4, WebAssembly::uint_to_fp_F32x4_S },
17635}; // End of getStackOpcodeTable
17636
17637 unsigned mid;
17638 unsigned start = 0;
17639 unsigned end = 800;
17640 while (start < end) {
17641 mid = start + (end - start) / 2;
17642 if (Opcode == getStackOpcodeTable[mid][0]) {
17643 break;
17644 }
17645 if (Opcode < getStackOpcodeTable[mid][0])
17646 end = mid;
17647 else
17648 start = mid + 1;
17649 }
17650 if (start == end)
17651 return -1; // Instruction doesn't exist in this table.
17652
17653 return getStackOpcodeTable[mid][1];
17654}
17655
17656// getWasm64Opcode
17657LLVM_READONLY
17658int getWasm64Opcode(uint16_t Opcode) {
17659static const uint16_t getWasm64OpcodeTable[][2] = {
17660 { WebAssembly::ATOMIC_LOAD16_U_I32_A32, WebAssembly::ATOMIC_LOAD16_U_I32_A64 },
17661 { WebAssembly::ATOMIC_LOAD16_U_I32_A32_S, WebAssembly::ATOMIC_LOAD16_U_I32_A64_S },
17662 { WebAssembly::ATOMIC_LOAD16_U_I64_A32, WebAssembly::ATOMIC_LOAD16_U_I64_A64 },
17663 { WebAssembly::ATOMIC_LOAD16_U_I64_A32_S, WebAssembly::ATOMIC_LOAD16_U_I64_A64_S },
17664 { WebAssembly::ATOMIC_LOAD32_U_I64_A32, WebAssembly::ATOMIC_LOAD32_U_I64_A64 },
17665 { WebAssembly::ATOMIC_LOAD32_U_I64_A32_S, WebAssembly::ATOMIC_LOAD32_U_I64_A64_S },
17666 { WebAssembly::ATOMIC_LOAD8_U_I32_A32, WebAssembly::ATOMIC_LOAD8_U_I32_A64 },
17667 { WebAssembly::ATOMIC_LOAD8_U_I32_A32_S, WebAssembly::ATOMIC_LOAD8_U_I32_A64_S },
17668 { WebAssembly::ATOMIC_LOAD8_U_I64_A32, WebAssembly::ATOMIC_LOAD8_U_I64_A64 },
17669 { WebAssembly::ATOMIC_LOAD8_U_I64_A32_S, WebAssembly::ATOMIC_LOAD8_U_I64_A64_S },
17670 { WebAssembly::ATOMIC_LOAD_I32_A32, WebAssembly::ATOMIC_LOAD_I32_A64 },
17671 { WebAssembly::ATOMIC_LOAD_I32_A32_S, WebAssembly::ATOMIC_LOAD_I32_A64_S },
17672 { WebAssembly::ATOMIC_LOAD_I64_A32, WebAssembly::ATOMIC_LOAD_I64_A64 },
17673 { WebAssembly::ATOMIC_LOAD_I64_A32_S, WebAssembly::ATOMIC_LOAD_I64_A64_S },
17674 { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64 },
17675 { WebAssembly::ATOMIC_RMW16_U_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_ADD_I32_A64_S },
17676 { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64 },
17677 { WebAssembly::ATOMIC_RMW16_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_ADD_I64_A64_S },
17678 { WebAssembly::ATOMIC_RMW16_U_AND_I32_A32, WebAssembly::ATOMIC_RMW16_U_AND_I32_A64 },
17679 { WebAssembly::ATOMIC_RMW16_U_AND_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_AND_I32_A64_S },
17680 { WebAssembly::ATOMIC_RMW16_U_AND_I64_A32, WebAssembly::ATOMIC_RMW16_U_AND_I64_A64 },
17681 { WebAssembly::ATOMIC_RMW16_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_AND_I64_A64_S },
17682 { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64 },
17683 { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_A64_S },
17684 { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64 },
17685 { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_A64_S },
17686 { WebAssembly::ATOMIC_RMW16_U_OR_I32_A32, WebAssembly::ATOMIC_RMW16_U_OR_I32_A64 },
17687 { WebAssembly::ATOMIC_RMW16_U_OR_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_OR_I32_A64_S },
17688 { WebAssembly::ATOMIC_RMW16_U_OR_I64_A32, WebAssembly::ATOMIC_RMW16_U_OR_I64_A64 },
17689 { WebAssembly::ATOMIC_RMW16_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_OR_I64_A64_S },
17690 { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64 },
17691 { WebAssembly::ATOMIC_RMW16_U_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_SUB_I32_A64_S },
17692 { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64 },
17693 { WebAssembly::ATOMIC_RMW16_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_SUB_I64_A64_S },
17694 { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64 },
17695 { WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_A64_S },
17696 { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64 },
17697 { WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_A64_S },
17698 { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64 },
17699 { WebAssembly::ATOMIC_RMW16_U_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW16_U_XOR_I32_A64_S },
17700 { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64 },
17701 { WebAssembly::ATOMIC_RMW16_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW16_U_XOR_I64_A64_S },
17702 { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64 },
17703 { WebAssembly::ATOMIC_RMW32_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_ADD_I64_A64_S },
17704 { WebAssembly::ATOMIC_RMW32_U_AND_I64_A32, WebAssembly::ATOMIC_RMW32_U_AND_I64_A64 },
17705 { WebAssembly::ATOMIC_RMW32_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_AND_I64_A64_S },
17706 { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64 },
17707 { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_A64_S },
17708 { WebAssembly::ATOMIC_RMW32_U_OR_I64_A32, WebAssembly::ATOMIC_RMW32_U_OR_I64_A64 },
17709 { WebAssembly::ATOMIC_RMW32_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_OR_I64_A64_S },
17710 { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64 },
17711 { WebAssembly::ATOMIC_RMW32_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_SUB_I64_A64_S },
17712 { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64 },
17713 { WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_A64_S },
17714 { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64 },
17715 { WebAssembly::ATOMIC_RMW32_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW32_U_XOR_I64_A64_S },
17716 { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64 },
17717 { WebAssembly::ATOMIC_RMW8_U_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_ADD_I32_A64_S },
17718 { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64 },
17719 { WebAssembly::ATOMIC_RMW8_U_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_ADD_I64_A64_S },
17720 { WebAssembly::ATOMIC_RMW8_U_AND_I32_A32, WebAssembly::ATOMIC_RMW8_U_AND_I32_A64 },
17721 { WebAssembly::ATOMIC_RMW8_U_AND_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_AND_I32_A64_S },
17722 { WebAssembly::ATOMIC_RMW8_U_AND_I64_A32, WebAssembly::ATOMIC_RMW8_U_AND_I64_A64 },
17723 { WebAssembly::ATOMIC_RMW8_U_AND_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_AND_I64_A64_S },
17724 { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64 },
17725 { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_A64_S },
17726 { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64 },
17727 { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_A64_S },
17728 { WebAssembly::ATOMIC_RMW8_U_OR_I32_A32, WebAssembly::ATOMIC_RMW8_U_OR_I32_A64 },
17729 { WebAssembly::ATOMIC_RMW8_U_OR_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_OR_I32_A64_S },
17730 { WebAssembly::ATOMIC_RMW8_U_OR_I64_A32, WebAssembly::ATOMIC_RMW8_U_OR_I64_A64 },
17731 { WebAssembly::ATOMIC_RMW8_U_OR_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_OR_I64_A64_S },
17732 { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64 },
17733 { WebAssembly::ATOMIC_RMW8_U_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_SUB_I32_A64_S },
17734 { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64 },
17735 { WebAssembly::ATOMIC_RMW8_U_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_SUB_I64_A64_S },
17736 { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64 },
17737 { WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_A64_S },
17738 { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64 },
17739 { WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_A64_S },
17740 { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64 },
17741 { WebAssembly::ATOMIC_RMW8_U_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW8_U_XOR_I32_A64_S },
17742 { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64 },
17743 { WebAssembly::ATOMIC_RMW8_U_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW8_U_XOR_I64_A64_S },
17744 { WebAssembly::ATOMIC_RMW_ADD_I32_A32, WebAssembly::ATOMIC_RMW_ADD_I32_A64 },
17745 { WebAssembly::ATOMIC_RMW_ADD_I32_A32_S, WebAssembly::ATOMIC_RMW_ADD_I32_A64_S },
17746 { WebAssembly::ATOMIC_RMW_ADD_I64_A32, WebAssembly::ATOMIC_RMW_ADD_I64_A64 },
17747 { WebAssembly::ATOMIC_RMW_ADD_I64_A32_S, WebAssembly::ATOMIC_RMW_ADD_I64_A64_S },
17748 { WebAssembly::ATOMIC_RMW_AND_I32_A32, WebAssembly::ATOMIC_RMW_AND_I32_A64 },
17749 { WebAssembly::ATOMIC_RMW_AND_I32_A32_S, WebAssembly::ATOMIC_RMW_AND_I32_A64_S },
17750 { WebAssembly::ATOMIC_RMW_AND_I64_A32, WebAssembly::ATOMIC_RMW_AND_I64_A64 },
17751 { WebAssembly::ATOMIC_RMW_AND_I64_A32_S, WebAssembly::ATOMIC_RMW_AND_I64_A64_S },
17752 { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64 },
17753 { WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A32_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_A64_S },
17754 { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64 },
17755 { WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A32_S, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_A64_S },
17756 { WebAssembly::ATOMIC_RMW_OR_I32_A32, WebAssembly::ATOMIC_RMW_OR_I32_A64 },
17757 { WebAssembly::ATOMIC_RMW_OR_I32_A32_S, WebAssembly::ATOMIC_RMW_OR_I32_A64_S },
17758 { WebAssembly::ATOMIC_RMW_OR_I64_A32, WebAssembly::ATOMIC_RMW_OR_I64_A64 },
17759 { WebAssembly::ATOMIC_RMW_OR_I64_A32_S, WebAssembly::ATOMIC_RMW_OR_I64_A64_S },
17760 { WebAssembly::ATOMIC_RMW_SUB_I32_A32, WebAssembly::ATOMIC_RMW_SUB_I32_A64 },
17761 { WebAssembly::ATOMIC_RMW_SUB_I32_A32_S, WebAssembly::ATOMIC_RMW_SUB_I32_A64_S },
17762 { WebAssembly::ATOMIC_RMW_SUB_I64_A32, WebAssembly::ATOMIC_RMW_SUB_I64_A64 },
17763 { WebAssembly::ATOMIC_RMW_SUB_I64_A32_S, WebAssembly::ATOMIC_RMW_SUB_I64_A64_S },
17764 { WebAssembly::ATOMIC_RMW_XCHG_I32_A32, WebAssembly::ATOMIC_RMW_XCHG_I32_A64 },
17765 { WebAssembly::ATOMIC_RMW_XCHG_I32_A32_S, WebAssembly::ATOMIC_RMW_XCHG_I32_A64_S },
17766 { WebAssembly::ATOMIC_RMW_XCHG_I64_A32, WebAssembly::ATOMIC_RMW_XCHG_I64_A64 },
17767 { WebAssembly::ATOMIC_RMW_XCHG_I64_A32_S, WebAssembly::ATOMIC_RMW_XCHG_I64_A64_S },
17768 { WebAssembly::ATOMIC_RMW_XOR_I32_A32, WebAssembly::ATOMIC_RMW_XOR_I32_A64 },
17769 { WebAssembly::ATOMIC_RMW_XOR_I32_A32_S, WebAssembly::ATOMIC_RMW_XOR_I32_A64_S },
17770 { WebAssembly::ATOMIC_RMW_XOR_I64_A32, WebAssembly::ATOMIC_RMW_XOR_I64_A64 },
17771 { WebAssembly::ATOMIC_RMW_XOR_I64_A32_S, WebAssembly::ATOMIC_RMW_XOR_I64_A64_S },
17772 { WebAssembly::ATOMIC_STORE16_I32_A32, WebAssembly::ATOMIC_STORE16_I32_A64 },
17773 { WebAssembly::ATOMIC_STORE16_I32_A32_S, WebAssembly::ATOMIC_STORE16_I32_A64_S },
17774 { WebAssembly::ATOMIC_STORE16_I64_A32, WebAssembly::ATOMIC_STORE16_I64_A64 },
17775 { WebAssembly::ATOMIC_STORE16_I64_A32_S, WebAssembly::ATOMIC_STORE16_I64_A64_S },
17776 { WebAssembly::ATOMIC_STORE32_I64_A32, WebAssembly::ATOMIC_STORE32_I64_A64 },
17777 { WebAssembly::ATOMIC_STORE32_I64_A32_S, WebAssembly::ATOMIC_STORE32_I64_A64_S },
17778 { WebAssembly::ATOMIC_STORE8_I32_A32, WebAssembly::ATOMIC_STORE8_I32_A64 },
17779 { WebAssembly::ATOMIC_STORE8_I32_A32_S, WebAssembly::ATOMIC_STORE8_I32_A64_S },
17780 { WebAssembly::ATOMIC_STORE8_I64_A32, WebAssembly::ATOMIC_STORE8_I64_A64 },
17781 { WebAssembly::ATOMIC_STORE8_I64_A32_S, WebAssembly::ATOMIC_STORE8_I64_A64_S },
17782 { WebAssembly::ATOMIC_STORE_I32_A32, WebAssembly::ATOMIC_STORE_I32_A64 },
17783 { WebAssembly::ATOMIC_STORE_I32_A32_S, WebAssembly::ATOMIC_STORE_I32_A64_S },
17784 { WebAssembly::ATOMIC_STORE_I64_A32, WebAssembly::ATOMIC_STORE_I64_A64 },
17785 { WebAssembly::ATOMIC_STORE_I64_A32_S, WebAssembly::ATOMIC_STORE_I64_A64_S },
17786 { WebAssembly::LOAD16_S_I32_A32, WebAssembly::LOAD16_S_I32_A64 },
17787 { WebAssembly::LOAD16_S_I32_A32_S, WebAssembly::LOAD16_S_I32_A64_S },
17788 { WebAssembly::LOAD16_S_I64_A32, WebAssembly::LOAD16_S_I64_A64 },
17789 { WebAssembly::LOAD16_S_I64_A32_S, WebAssembly::LOAD16_S_I64_A64_S },
17790 { WebAssembly::LOAD16_U_I32_A32, WebAssembly::LOAD16_U_I32_A64 },
17791 { WebAssembly::LOAD16_U_I32_A32_S, WebAssembly::LOAD16_U_I32_A64_S },
17792 { WebAssembly::LOAD16_U_I64_A32, WebAssembly::LOAD16_U_I64_A64 },
17793 { WebAssembly::LOAD16_U_I64_A32_S, WebAssembly::LOAD16_U_I64_A64_S },
17794 { WebAssembly::LOAD32_S_I64_A32, WebAssembly::LOAD32_S_I64_A64 },
17795 { WebAssembly::LOAD32_S_I64_A32_S, WebAssembly::LOAD32_S_I64_A64_S },
17796 { WebAssembly::LOAD32_U_I64_A32, WebAssembly::LOAD32_U_I64_A64 },
17797 { WebAssembly::LOAD32_U_I64_A32_S, WebAssembly::LOAD32_U_I64_A64_S },
17798 { WebAssembly::LOAD8_S_I32_A32, WebAssembly::LOAD8_S_I32_A64 },
17799 { WebAssembly::LOAD8_S_I32_A32_S, WebAssembly::LOAD8_S_I32_A64_S },
17800 { WebAssembly::LOAD8_S_I64_A32, WebAssembly::LOAD8_S_I64_A64 },
17801 { WebAssembly::LOAD8_S_I64_A32_S, WebAssembly::LOAD8_S_I64_A64_S },
17802 { WebAssembly::LOAD8_U_I32_A32, WebAssembly::LOAD8_U_I32_A64 },
17803 { WebAssembly::LOAD8_U_I32_A32_S, WebAssembly::LOAD8_U_I32_A64_S },
17804 { WebAssembly::LOAD8_U_I64_A32, WebAssembly::LOAD8_U_I64_A64 },
17805 { WebAssembly::LOAD8_U_I64_A32_S, WebAssembly::LOAD8_U_I64_A64_S },
17806 { WebAssembly::LOAD_F16_F32_A32, WebAssembly::LOAD_F16_F32_A64 },
17807 { WebAssembly::LOAD_F16_F32_A32_S, WebAssembly::LOAD_F16_F32_A64_S },
17808 { WebAssembly::LOAD_F32_A32, WebAssembly::LOAD_F32_A64 },
17809 { WebAssembly::LOAD_F32_A32_S, WebAssembly::LOAD_F32_A64_S },
17810 { WebAssembly::LOAD_F64_A32, WebAssembly::LOAD_F64_A64 },
17811 { WebAssembly::LOAD_F64_A32_S, WebAssembly::LOAD_F64_A64_S },
17812 { WebAssembly::LOAD_I32_A32, WebAssembly::LOAD_I32_A64 },
17813 { WebAssembly::LOAD_I32_A32_S, WebAssembly::LOAD_I32_A64_S },
17814 { WebAssembly::LOAD_I64_A32, WebAssembly::LOAD_I64_A64 },
17815 { WebAssembly::LOAD_I64_A32_S, WebAssembly::LOAD_I64_A64_S },
17816 { WebAssembly::MEMORY_ATOMIC_NOTIFY_A32, WebAssembly::MEMORY_ATOMIC_NOTIFY_A64 },
17817 { WebAssembly::MEMORY_ATOMIC_NOTIFY_A32_S, WebAssembly::MEMORY_ATOMIC_NOTIFY_A64_S },
17818 { WebAssembly::MEMORY_ATOMIC_WAIT32_A32, WebAssembly::MEMORY_ATOMIC_WAIT32_A64 },
17819 { WebAssembly::MEMORY_ATOMIC_WAIT32_A32_S, WebAssembly::MEMORY_ATOMIC_WAIT32_A64_S },
17820 { WebAssembly::MEMORY_ATOMIC_WAIT64_A32, WebAssembly::MEMORY_ATOMIC_WAIT64_A64 },
17821 { WebAssembly::MEMORY_ATOMIC_WAIT64_A32_S, WebAssembly::MEMORY_ATOMIC_WAIT64_A64_S },
17822 { WebAssembly::STORE16_I32_A32, WebAssembly::STORE16_I32_A64 },
17823 { WebAssembly::STORE16_I32_A32_S, WebAssembly::STORE16_I32_A64_S },
17824 { WebAssembly::STORE16_I64_A32, WebAssembly::STORE16_I64_A64 },
17825 { WebAssembly::STORE16_I64_A32_S, WebAssembly::STORE16_I64_A64_S },
17826 { WebAssembly::STORE32_I64_A32, WebAssembly::STORE32_I64_A64 },
17827 { WebAssembly::STORE32_I64_A32_S, WebAssembly::STORE32_I64_A64_S },
17828 { WebAssembly::STORE8_I32_A32, WebAssembly::STORE8_I32_A64 },
17829 { WebAssembly::STORE8_I32_A32_S, WebAssembly::STORE8_I32_A64_S },
17830 { WebAssembly::STORE8_I64_A32, WebAssembly::STORE8_I64_A64 },
17831 { WebAssembly::STORE8_I64_A32_S, WebAssembly::STORE8_I64_A64_S },
17832 { WebAssembly::STORE_F16_F32_A32, WebAssembly::STORE_F16_F32_A64 },
17833 { WebAssembly::STORE_F16_F32_A32_S, WebAssembly::STORE_F16_F32_A64_S },
17834 { WebAssembly::STORE_F32_A32, WebAssembly::STORE_F32_A64 },
17835 { WebAssembly::STORE_F32_A32_S, WebAssembly::STORE_F32_A64_S },
17836 { WebAssembly::STORE_F64_A32, WebAssembly::STORE_F64_A64 },
17837 { WebAssembly::STORE_F64_A32_S, WebAssembly::STORE_F64_A64_S },
17838 { WebAssembly::STORE_I32_A32, WebAssembly::STORE_I32_A64 },
17839 { WebAssembly::STORE_I32_A32_S, WebAssembly::STORE_I32_A64_S },
17840 { WebAssembly::STORE_I64_A32, WebAssembly::STORE_I64_A64 },
17841 { WebAssembly::STORE_I64_A32_S, WebAssembly::STORE_I64_A64_S },
17842}; // End of getWasm64OpcodeTable
17843
17844 unsigned mid;
17845 unsigned start = 0;
17846 unsigned end = 182;
17847 while (start < end) {
17848 mid = start + (end - start) / 2;
17849 if (Opcode == getWasm64OpcodeTable[mid][0]) {
17850 break;
17851 }
17852 if (Opcode < getWasm64OpcodeTable[mid][0])
17853 end = mid;
17854 else
17855 start = mid + 1;
17856 }
17857 if (start == end)
17858 return -1; // Instruction doesn't exist in this table.
17859
17860 return getWasm64OpcodeTable[mid][1];
17861}
17862
17863} // end namespace WebAssembly
17864} // end namespace llvm
17865#endif // GET_INSTRMAP_INFO
17866
17867