1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass WebAssemblyMCRegisterClasses[];
17
18namespace WebAssembly {
19enum {
20 NoRegister,
21 ARGUMENTS = 1,
22 VALUE_STACK = 2,
23 EXNREF_0 = 3,
24 EXTERNREF_0 = 4,
25 FP32 = 5,
26 FP64 = 6,
27 FUNCREF_0 = 7,
28 SP32 = 8,
29 SP64 = 9,
30 F32_0 = 10,
31 F64_0 = 11,
32 I32_0 = 12,
33 I64_0 = 13,
34 V128_0 = 14,
35 NUM_TARGET_REGS // 15
36};
37} // end namespace WebAssembly
38
39// Register classes
40
41namespace WebAssembly {
42enum {
43 EXNREFRegClassID = 0,
44 EXTERNREFRegClassID = 1,
45 FUNCREFRegClassID = 2,
46 I32RegClassID = 3,
47 F32RegClassID = 4,
48 I64RegClassID = 5,
49 F64RegClassID = 6,
50 V128RegClassID = 7,
51
52};
53} // end namespace WebAssembly
54
55// Register pressure sets enum.
56namespace WebAssembly {
57enum RegisterPressureSets {
58 EXNREF = 0,
59 EXTERNREF = 1,
60 FUNCREF = 2,
61 F32 = 3,
62 F64 = 4,
63 V128 = 5,
64 I32 = 6,
65 I64 = 7,
66};
67} // end namespace WebAssembly
68
69} // end namespace llvm
70
71#endif // GET_REGINFO_ENUM
72
73/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
74|* *|
75|* MC Register Information *|
76|* *|
77|* Automatically generated file, do not edit! *|
78|* *|
79\*===----------------------------------------------------------------------===*/
80
81
82#ifdef GET_REGINFO_MC_DESC
83#undef GET_REGINFO_MC_DESC
84
85namespace llvm {
86
87extern const int16_t WebAssemblyRegDiffLists[] = {
88 /* 0 */ 0,
89};
90
91extern const LaneBitmask WebAssemblyLaneMaskLists[] = {
92 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
93};
94
95extern const uint16_t WebAssemblySubRegIdxLists[] = {
96 /* 0 */ 0,
97};
98
99
100#ifdef __GNUC__
101#pragma GCC diagnostic push
102#pragma GCC diagnostic ignored "-Woverlength-strings"
103#endif
104extern const char WebAssemblyRegStrings[] = {
105 /* 0 */ "F32_0\0"
106 /* 6 */ "I32_0\0"
107 /* 12 */ "F64_0\0"
108 /* 18 */ "I64_0\0"
109 /* 24 */ "V128_0\0"
110 /* 31 */ "FUNCREF_0\0"
111 /* 41 */ "EXTERNREF_0\0"
112 /* 53 */ "EXNREF_0\0"
113 /* 62 */ "FP32\0"
114 /* 67 */ "SP32\0"
115 /* 72 */ "FP64\0"
116 /* 77 */ "SP64\0"
117 /* 82 */ "VALUE_STACK\0"
118 /* 94 */ "ARGUMENTS\0"
119};
120#ifdef __GNUC__
121#pragma GCC diagnostic pop
122#endif
123
124extern const MCRegisterDesc WebAssemblyRegDesc[] = { // Descriptors
125 { 5, 0, 0, 0, 0, 0, 0 },
126 { 94, 0, 0, 0, 0, 0, 0 },
127 { 82, 0, 0, 0, 1, 0, 0 },
128 { 53, 0, 0, 0, 2, 0, 0 },
129 { 41, 0, 0, 0, 3, 0, 0 },
130 { 62, 0, 0, 0, 4, 0, 0 },
131 { 72, 0, 0, 0, 5, 0, 0 },
132 { 31, 0, 0, 0, 6, 0, 0 },
133 { 67, 0, 0, 0, 7, 0, 0 },
134 { 77, 0, 0, 0, 8, 0, 0 },
135 { 0, 0, 0, 0, 9, 0, 0 },
136 { 12, 0, 0, 0, 10, 0, 0 },
137 { 6, 0, 0, 0, 11, 0, 0 },
138 { 18, 0, 0, 0, 12, 0, 0 },
139 { 24, 0, 0, 0, 13, 0, 0 },
140};
141
142extern const MCPhysReg WebAssemblyRegUnitRoots[][2] = {
143 { WebAssembly::ARGUMENTS },
144 { WebAssembly::VALUE_STACK },
145 { WebAssembly::EXNREF_0 },
146 { WebAssembly::EXTERNREF_0 },
147 { WebAssembly::FP32 },
148 { WebAssembly::FP64 },
149 { WebAssembly::FUNCREF_0 },
150 { WebAssembly::SP32 },
151 { WebAssembly::SP64 },
152 { WebAssembly::F32_0 },
153 { WebAssembly::F64_0 },
154 { WebAssembly::I32_0 },
155 { WebAssembly::I64_0 },
156 { WebAssembly::V128_0 },
157};
158
159namespace { // Register classes...
160 // EXNREF Register Class...
161 const MCPhysReg EXNREF[] = {
162 WebAssembly::EXNREF_0,
163 };
164
165 // EXNREF Bit set.
166 const uint8_t EXNREFBits[] = {
167 0x08,
168 };
169
170 // EXTERNREF Register Class...
171 const MCPhysReg EXTERNREF[] = {
172 WebAssembly::EXTERNREF_0,
173 };
174
175 // EXTERNREF Bit set.
176 const uint8_t EXTERNREFBits[] = {
177 0x10,
178 };
179
180 // FUNCREF Register Class...
181 const MCPhysReg FUNCREF[] = {
182 WebAssembly::FUNCREF_0,
183 };
184
185 // FUNCREF Bit set.
186 const uint8_t FUNCREFBits[] = {
187 0x80,
188 };
189
190 // I32 Register Class...
191 const MCPhysReg I32[] = {
192 WebAssembly::FP32, WebAssembly::SP32, WebAssembly::I32_0,
193 };
194
195 // I32 Bit set.
196 const uint8_t I32Bits[] = {
197 0x20, 0x11,
198 };
199
200 // F32 Register Class...
201 const MCPhysReg F32[] = {
202 WebAssembly::F32_0,
203 };
204
205 // F32 Bit set.
206 const uint8_t F32Bits[] = {
207 0x00, 0x04,
208 };
209
210 // I64 Register Class...
211 const MCPhysReg I64[] = {
212 WebAssembly::FP64, WebAssembly::SP64, WebAssembly::I64_0,
213 };
214
215 // I64 Bit set.
216 const uint8_t I64Bits[] = {
217 0x40, 0x22,
218 };
219
220 // F64 Register Class...
221 const MCPhysReg F64[] = {
222 WebAssembly::F64_0,
223 };
224
225 // F64 Bit set.
226 const uint8_t F64Bits[] = {
227 0x00, 0x08,
228 };
229
230 // V128 Register Class...
231 const MCPhysReg V128[] = {
232 WebAssembly::V128_0,
233 };
234
235 // V128 Bit set.
236 const uint8_t V128Bits[] = {
237 0x00, 0x40,
238 };
239
240} // end anonymous namespace
241
242
243#ifdef __GNUC__
244#pragma GCC diagnostic push
245#pragma GCC diagnostic ignored "-Woverlength-strings"
246#endif
247extern const char WebAssemblyRegClassStrings[] = {
248 /* 0 */ "F32\0"
249 /* 4 */ "I32\0"
250 /* 8 */ "F64\0"
251 /* 12 */ "I64\0"
252 /* 16 */ "V128\0"
253 /* 21 */ "FUNCREF\0"
254 /* 29 */ "EXTERNREF\0"
255 /* 39 */ "EXNREF\0"
256};
257#ifdef __GNUC__
258#pragma GCC diagnostic pop
259#endif
260
261extern const MCRegisterClass WebAssemblyMCRegisterClasses[] = {
262 { EXNREF, EXNREFBits, 39, 1, sizeof(EXNREFBits), WebAssembly::EXNREFRegClassID, 0, 1, true, false },
263 { EXTERNREF, EXTERNREFBits, 29, 1, sizeof(EXTERNREFBits), WebAssembly::EXTERNREFRegClassID, 0, 1, true, false },
264 { FUNCREF, FUNCREFBits, 21, 1, sizeof(FUNCREFBits), WebAssembly::FUNCREFRegClassID, 0, 1, true, false },
265 { I32, I32Bits, 4, 3, sizeof(I32Bits), WebAssembly::I32RegClassID, 32, 1, true, false },
266 { F32, F32Bits, 0, 1, sizeof(F32Bits), WebAssembly::F32RegClassID, 32, 1, true, false },
267 { I64, I64Bits, 12, 3, sizeof(I64Bits), WebAssembly::I64RegClassID, 64, 1, true, false },
268 { F64, F64Bits, 8, 1, sizeof(F64Bits), WebAssembly::F64RegClassID, 64, 1, true, false },
269 { V128, V128Bits, 16, 1, sizeof(V128Bits), WebAssembly::V128RegClassID, 128, 1, true, false },
270};
271
272extern const uint16_t WebAssemblyRegEncodingTable[] = {
273 0,
274 0,
275 0,
276 0,
277 0,
278 0,
279 0,
280 0,
281 0,
282 0,
283 0,
284 0,
285 0,
286 0,
287 0,
288};
289static inline void InitWebAssemblyMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
290 RI->InitMCRegisterInfo(WebAssemblyRegDesc, 15, RA, PC, WebAssemblyMCRegisterClasses, 8, WebAssemblyRegUnitRoots, 14, WebAssemblyRegDiffLists, WebAssemblyLaneMaskLists, WebAssemblyRegStrings, WebAssemblyRegClassStrings, WebAssemblySubRegIdxLists, 1,
291WebAssemblyRegEncodingTable);
292
293}
294
295} // end namespace llvm
296
297#endif // GET_REGINFO_MC_DESC
298
299/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
300|* *|
301|* Register Information Header Fragment *|
302|* *|
303|* Automatically generated file, do not edit! *|
304|* *|
305\*===----------------------------------------------------------------------===*/
306
307
308#ifdef GET_REGINFO_HEADER
309#undef GET_REGINFO_HEADER
310
311#include "llvm/CodeGen/TargetRegisterInfo.h"
312
313namespace llvm {
314
315class WebAssemblyFrameLowering;
316
317struct WebAssemblyGenRegisterInfo : public TargetRegisterInfo {
318 explicit WebAssemblyGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
319 unsigned PC = 0, unsigned HwMode = 0);
320 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
321 unsigned getRegUnitWeight(unsigned RegUnit) const override;
322 unsigned getNumRegPressureSets() const override;
323 const char *getRegPressureSetName(unsigned Idx) const override;
324 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
325 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
326 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
327 ArrayRef<const char *> getRegMaskNames() const override;
328 ArrayRef<const uint32_t *> getRegMasks() const override;
329 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
330 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
331 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
332 bool isConstantPhysReg(MCRegister PhysReg) const override final;
333 /// Devirtualized TargetFrameLowering.
334 static const WebAssemblyFrameLowering *getFrameLowering(
335 const MachineFunction &MF);
336};
337
338namespace WebAssembly { // Register classes
339 extern const TargetRegisterClass EXNREFRegClass;
340 extern const TargetRegisterClass EXTERNREFRegClass;
341 extern const TargetRegisterClass FUNCREFRegClass;
342 extern const TargetRegisterClass I32RegClass;
343 extern const TargetRegisterClass F32RegClass;
344 extern const TargetRegisterClass I64RegClass;
345 extern const TargetRegisterClass F64RegClass;
346 extern const TargetRegisterClass V128RegClass;
347} // end namespace WebAssembly
348
349} // end namespace llvm
350
351#endif // GET_REGINFO_HEADER
352
353/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
354|* *|
355|* Target Register and Register Classes Information *|
356|* *|
357|* Automatically generated file, do not edit! *|
358|* *|
359\*===----------------------------------------------------------------------===*/
360
361
362#ifdef GET_REGINFO_TARGET_DESC
363#undef GET_REGINFO_TARGET_DESC
364
365namespace llvm {
366
367extern const MCRegisterClass WebAssemblyMCRegisterClasses[];
368
369static const MVT::SimpleValueType VTLists[] = {
370 /* 0 */ MVT::i32, MVT::Other,
371 /* 2 */ MVT::i64, MVT::Other,
372 /* 4 */ MVT::f32, MVT::Other,
373 /* 6 */ MVT::f64, MVT::Other,
374 /* 8 */ MVT::v8f16, MVT::v4f32, MVT::v2f64, MVT::v2i64, MVT::v4i32, MVT::v16i8, MVT::v8i16, MVT::Other,
375 /* 16 */ MVT::funcref, MVT::Other,
376 /* 18 */ MVT::externref, MVT::Other,
377 /* 20 */ MVT::exnref, MVT::Other,
378};
379
380static const char *SubRegIndexNameTable[] = { "" };
381
382static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
383 { 65535, 65535 },
384};
385
386
387static const LaneBitmask SubRegIndexLaneMaskTable[] = {
388 LaneBitmask::getAll(),
389 };
390
391
392
393static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
394 // Mode = 0 (Default)
395 { 0, 0, 0, /*VTLists+*/20 }, // EXNREF
396 { 0, 0, 0, /*VTLists+*/18 }, // EXTERNREF
397 { 0, 0, 0, /*VTLists+*/16 }, // FUNCREF
398 { 32, 32, 32, /*VTLists+*/0 }, // I32
399 { 32, 32, 32, /*VTLists+*/4 }, // F32
400 { 64, 64, 64, /*VTLists+*/2 }, // I64
401 { 64, 64, 64, /*VTLists+*/6 }, // F64
402 { 128, 128, 128, /*VTLists+*/8 }, // V128
403};
404
405static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
406
407static const uint32_t EXNREFSubClassMask[] = {
408 0x00000001,
409};
410
411static const uint32_t EXTERNREFSubClassMask[] = {
412 0x00000002,
413};
414
415static const uint32_t FUNCREFSubClassMask[] = {
416 0x00000004,
417};
418
419static const uint32_t I32SubClassMask[] = {
420 0x00000008,
421};
422
423static const uint32_t F32SubClassMask[] = {
424 0x00000010,
425};
426
427static const uint32_t I64SubClassMask[] = {
428 0x00000020,
429};
430
431static const uint32_t F64SubClassMask[] = {
432 0x00000040,
433};
434
435static const uint32_t V128SubClassMask[] = {
436 0x00000080,
437};
438
439static const uint16_t SuperRegIdxSeqs[] = {
440 /* 0 */ 0,
441};
442
443
444namespace WebAssembly { // Register class instances
445 extern const TargetRegisterClass EXNREFRegClass = {
446 &WebAssemblyMCRegisterClasses[EXNREFRegClassID],
447 EXNREFSubClassMask,
448 SuperRegIdxSeqs + 0,
449 LaneBitmask(0x0000000000000001),
450 0,
451 false,
452 0x00, /* TSFlags */
453 false, /* HasDisjunctSubRegs */
454 false, /* CoveredBySubRegs */
455 NullRegClasses,
456 nullptr
457 };
458
459 extern const TargetRegisterClass EXTERNREFRegClass = {
460 &WebAssemblyMCRegisterClasses[EXTERNREFRegClassID],
461 EXTERNREFSubClassMask,
462 SuperRegIdxSeqs + 0,
463 LaneBitmask(0x0000000000000001),
464 0,
465 false,
466 0x00, /* TSFlags */
467 false, /* HasDisjunctSubRegs */
468 false, /* CoveredBySubRegs */
469 NullRegClasses,
470 nullptr
471 };
472
473 extern const TargetRegisterClass FUNCREFRegClass = {
474 &WebAssemblyMCRegisterClasses[FUNCREFRegClassID],
475 FUNCREFSubClassMask,
476 SuperRegIdxSeqs + 0,
477 LaneBitmask(0x0000000000000001),
478 0,
479 false,
480 0x00, /* TSFlags */
481 false, /* HasDisjunctSubRegs */
482 false, /* CoveredBySubRegs */
483 NullRegClasses,
484 nullptr
485 };
486
487 extern const TargetRegisterClass I32RegClass = {
488 &WebAssemblyMCRegisterClasses[I32RegClassID],
489 I32SubClassMask,
490 SuperRegIdxSeqs + 0,
491 LaneBitmask(0x0000000000000001),
492 0,
493 false,
494 0x00, /* TSFlags */
495 false, /* HasDisjunctSubRegs */
496 false, /* CoveredBySubRegs */
497 NullRegClasses,
498 nullptr
499 };
500
501 extern const TargetRegisterClass F32RegClass = {
502 &WebAssemblyMCRegisterClasses[F32RegClassID],
503 F32SubClassMask,
504 SuperRegIdxSeqs + 0,
505 LaneBitmask(0x0000000000000001),
506 0,
507 false,
508 0x00, /* TSFlags */
509 false, /* HasDisjunctSubRegs */
510 false, /* CoveredBySubRegs */
511 NullRegClasses,
512 nullptr
513 };
514
515 extern const TargetRegisterClass I64RegClass = {
516 &WebAssemblyMCRegisterClasses[I64RegClassID],
517 I64SubClassMask,
518 SuperRegIdxSeqs + 0,
519 LaneBitmask(0x0000000000000001),
520 0,
521 false,
522 0x00, /* TSFlags */
523 false, /* HasDisjunctSubRegs */
524 false, /* CoveredBySubRegs */
525 NullRegClasses,
526 nullptr
527 };
528
529 extern const TargetRegisterClass F64RegClass = {
530 &WebAssemblyMCRegisterClasses[F64RegClassID],
531 F64SubClassMask,
532 SuperRegIdxSeqs + 0,
533 LaneBitmask(0x0000000000000001),
534 0,
535 false,
536 0x00, /* TSFlags */
537 false, /* HasDisjunctSubRegs */
538 false, /* CoveredBySubRegs */
539 NullRegClasses,
540 nullptr
541 };
542
543 extern const TargetRegisterClass V128RegClass = {
544 &WebAssemblyMCRegisterClasses[V128RegClassID],
545 V128SubClassMask,
546 SuperRegIdxSeqs + 0,
547 LaneBitmask(0x0000000000000001),
548 0,
549 false,
550 0x00, /* TSFlags */
551 false, /* HasDisjunctSubRegs */
552 false, /* CoveredBySubRegs */
553 NullRegClasses,
554 nullptr
555 };
556
557} // end namespace WebAssembly
558
559namespace {
560 const TargetRegisterClass *const RegisterClasses[] = {
561 &WebAssembly::EXNREFRegClass,
562 &WebAssembly::EXTERNREFRegClass,
563 &WebAssembly::FUNCREFRegClass,
564 &WebAssembly::I32RegClass,
565 &WebAssembly::F32RegClass,
566 &WebAssembly::I64RegClass,
567 &WebAssembly::F64RegClass,
568 &WebAssembly::V128RegClass,
569 };
570} // end anonymous namespace
571
572static const uint8_t CostPerUseTable[] = {
5730, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
574
575
576static const bool InAllocatableClassTable[] = {
577false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
578
579
580static const TargetRegisterInfoDesc WebAssemblyRegInfoDesc = { // Extra Descriptors
581CostPerUseTable, 1, InAllocatableClassTable};
582
583/// Get the weight in units of pressure for this register class.
584const RegClassWeight &WebAssemblyGenRegisterInfo::
585getRegClassWeight(const TargetRegisterClass *RC) const {
586 static const RegClassWeight RCWeightTable[] = {
587 {1, 1}, // EXNREF
588 {1, 1}, // EXTERNREF
589 {1, 1}, // FUNCREF
590 {1, 3}, // I32
591 {1, 1}, // F32
592 {1, 3}, // I64
593 {1, 1}, // F64
594 {1, 1}, // V128
595 };
596 return RCWeightTable[RC->getID()];
597}
598
599/// Get the weight in units of pressure for this register unit.
600unsigned WebAssemblyGenRegisterInfo::
601getRegUnitWeight(unsigned RegUnit) const {
602 assert(RegUnit < 14 && "invalid register unit");
603 // All register units have unit weight.
604 return 1;
605}
606
607
608// Get the number of dimensions of register pressure.
609unsigned WebAssemblyGenRegisterInfo::getNumRegPressureSets() const {
610 return 8;
611}
612
613// Get the name of this register unit pressure set.
614const char *WebAssemblyGenRegisterInfo::
615getRegPressureSetName(unsigned Idx) const {
616 static const char *PressureNameTable[] = {
617 "EXNREF",
618 "EXTERNREF",
619 "FUNCREF",
620 "F32",
621 "F64",
622 "V128",
623 "I32",
624 "I64",
625 };
626 return PressureNameTable[Idx];
627}
628
629// Get the register unit pressure limit for this dimension.
630// This limit must be adjusted dynamically for reserved registers.
631unsigned WebAssemblyGenRegisterInfo::
632getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
633 static const uint8_t PressureLimitTable[] = {
634 1, // 0: EXNREF
635 1, // 1: EXTERNREF
636 1, // 2: FUNCREF
637 1, // 3: F32
638 1, // 4: F64
639 1, // 5: V128
640 3, // 6: I32
641 3, // 7: I64
642 };
643 return PressureLimitTable[Idx];
644}
645
646/// Table of pressure sets per register class or unit.
647static const int RCSetsTable[] = {
648 /* 0 */ 0, -1,
649 /* 2 */ 1, -1,
650 /* 4 */ 2, -1,
651 /* 6 */ 3, -1,
652 /* 8 */ 4, -1,
653 /* 10 */ 5, -1,
654 /* 12 */ 6, -1,
655 /* 14 */ 7, -1,
656};
657
658/// Get the dimensions of register pressure impacted by this register class.
659/// Returns a -1 terminated array of pressure set IDs
660const int *WebAssemblyGenRegisterInfo::
661getRegClassPressureSets(const TargetRegisterClass *RC) const {
662 static const uint8_t RCSetStartTable[] = {
663 0,2,4,12,6,14,8,10,};
664 return &RCSetsTable[RCSetStartTable[RC->getID()]];
665}
666
667/// Get the dimensions of register pressure impacted by this register unit.
668/// Returns a -1 terminated array of pressure set IDs
669const int *WebAssemblyGenRegisterInfo::
670getRegUnitPressureSets(unsigned RegUnit) const {
671 assert(RegUnit < 14 && "invalid register unit");
672 static const uint8_t RUSetStartTable[] = {
673 1,1,0,2,12,14,4,12,14,6,8,12,14,10,};
674 return &RCSetsTable[RUSetStartTable[RegUnit]];
675}
676
677extern const MCRegisterDesc WebAssemblyRegDesc[];
678extern const int16_t WebAssemblyRegDiffLists[];
679extern const LaneBitmask WebAssemblyLaneMaskLists[];
680extern const char WebAssemblyRegStrings[];
681extern const char WebAssemblyRegClassStrings[];
682extern const MCPhysReg WebAssemblyRegUnitRoots[][2];
683extern const uint16_t WebAssemblySubRegIdxLists[];
684extern const uint16_t WebAssemblyRegEncodingTable[];
685WebAssemblyGenRegisterInfo::
686WebAssemblyGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
687 unsigned PC, unsigned HwMode)
688 : TargetRegisterInfo(&WebAssemblyRegInfoDesc, RegisterClasses, RegisterClasses+8,
689 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
690 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
691 InitMCRegisterInfo(WebAssemblyRegDesc, 15, RA, PC,
692 WebAssemblyMCRegisterClasses, 8,
693 WebAssemblyRegUnitRoots,
694 14,
695 WebAssemblyRegDiffLists,
696 WebAssemblyLaneMaskLists,
697 WebAssemblyRegStrings,
698 WebAssemblyRegClassStrings,
699 WebAssemblySubRegIdxLists,
700 1,
701 WebAssemblyRegEncodingTable);
702
703}
704
705
706
707ArrayRef<const uint32_t *> WebAssemblyGenRegisterInfo::getRegMasks() const {
708 return std::nullopt;
709}
710
711bool WebAssemblyGenRegisterInfo::
712isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
713 return
714 false;
715}
716
717bool WebAssemblyGenRegisterInfo::
718isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
719 return
720 false;
721}
722
723bool WebAssemblyGenRegisterInfo::
724isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
725 return
726 false;
727}
728
729bool WebAssemblyGenRegisterInfo::
730isConstantPhysReg(MCRegister PhysReg) const {
731 return
732 false;
733}
734
735ArrayRef<const char *> WebAssemblyGenRegisterInfo::getRegMaskNames() const {
736 return std::nullopt;
737}
738
739const WebAssemblyFrameLowering *
740WebAssemblyGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
741 return static_cast<const WebAssemblyFrameLowering *>(
742 MF.getSubtarget().getFrameLowering());
743}
744
745} // end namespace llvm
746
747#endif // GET_REGINFO_TARGET_DESC
748
749