1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace WebAssembly {
15enum {
16 FeatureAtomics = 0,
17 FeatureBulkMemory = 1,
18 FeatureExceptionHandling = 2,
19 FeatureExtendedConst = 3,
20 FeatureHalfPrecision = 4,
21 FeatureMultiMemory = 5,
22 FeatureMultivalue = 6,
23 FeatureMutableGlobals = 7,
24 FeatureNontrappingFPToInt = 8,
25 FeatureReferenceTypes = 9,
26 FeatureRelaxedSIMD = 10,
27 FeatureSIMD128 = 11,
28 FeatureSignExt = 12,
29 FeatureTailCall = 13,
30 NumSubtargetFeatures = 14
31};
32} // end namespace WebAssembly
33} // end namespace llvm
34
35#endif // GET_SUBTARGETINFO_ENUM
36
37
38#ifdef GET_SUBTARGETINFO_MACRO
39GET_SUBTARGETINFO_MACRO(HasAtomics, false, hasAtomics)
40GET_SUBTARGETINFO_MACRO(HasBulkMemory, false, hasBulkMemory)
41GET_SUBTARGETINFO_MACRO(HasExceptionHandling, false, hasExceptionHandling)
42GET_SUBTARGETINFO_MACRO(HasExtendedConst, false, hasExtendedConst)
43GET_SUBTARGETINFO_MACRO(HasHalfPrecision, false, hasHalfPrecision)
44GET_SUBTARGETINFO_MACRO(HasMultiMemory, false, hasMultiMemory)
45GET_SUBTARGETINFO_MACRO(HasMultivalue, false, hasMultivalue)
46GET_SUBTARGETINFO_MACRO(HasMutableGlobals, false, hasMutableGlobals)
47GET_SUBTARGETINFO_MACRO(HasNontrappingFPToInt, false, hasNontrappingFPToInt)
48GET_SUBTARGETINFO_MACRO(HasReferenceTypes, false, hasReferenceTypes)
49GET_SUBTARGETINFO_MACRO(HasSignExt, false, hasSignExt)
50GET_SUBTARGETINFO_MACRO(HasTailCall, false, hasTailCall)
51#undef GET_SUBTARGETINFO_MACRO
52#endif // GET_SUBTARGETINFO_MACRO
53
54
55#ifdef GET_SUBTARGETINFO_MC_DESC
56#undef GET_SUBTARGETINFO_MC_DESC
57
58namespace llvm {
59// Sorted (by key) array of values for CPU features.
60extern const llvm::SubtargetFeatureKV WebAssemblyFeatureKV[] = {
61 { "atomics", "Enable Atomics", WebAssembly::FeatureAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
62 { "bulk-memory", "Enable bulk memory operations", WebAssembly::FeatureBulkMemory, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
63 { "exception-handling", "Enable Wasm exception handling", WebAssembly::FeatureExceptionHandling, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
64 { "extended-const", "Enable extended const expressions", WebAssembly::FeatureExtendedConst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
65 { "half-precision", "Enable half precision instructions", WebAssembly::FeatureHalfPrecision, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
66 { "multimemory", "Enable multiple memories", WebAssembly::FeatureMultiMemory, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
67 { "multivalue", "Enable multivalue blocks, instructions, and functions", WebAssembly::FeatureMultivalue, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
68 { "mutable-globals", "Enable mutable globals", WebAssembly::FeatureMutableGlobals, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
69 { "nontrapping-fptoint", "Enable non-trapping float-to-int conversion operators", WebAssembly::FeatureNontrappingFPToInt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
70 { "reference-types", "Enable reference types", WebAssembly::FeatureReferenceTypes, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
71 { "relaxed-simd", "Enable relaxed-simd instructions", WebAssembly::FeatureRelaxedSIMD, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
72 { "sign-ext", "Enable sign extension operators", WebAssembly::FeatureSignExt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
73 { "simd128", "Enable 128-bit SIMD", WebAssembly::FeatureSIMD128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
74 { "tail-call", "Enable tail call instructions", WebAssembly::FeatureTailCall, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
75};
76
77#ifdef DBGFIELD
78#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
79#endif
80#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
81#define DBGFIELD(x) x,
82#else
83#define DBGFIELD(x)
84#endif
85
86// ===============================================================
87// Data tables for the new per-operand machine model.
88
89// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
90extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[] = {
91 { 0, 0, 0 }, // Invalid
92}; // WebAssemblyWriteProcResTable
93
94// {Cycles, WriteResourceID}
95extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[] = {
96 { 0, 0}, // Invalid
97}; // WebAssemblyWriteLatencyTable
98
99// {UseIdx, WriteResourceID, Cycles}
100extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[] = {
101 {0, 0, 0}, // Invalid
102}; // WebAssemblyReadAdvanceTable
103
104#undef DBGFIELD
105
106static const llvm::MCSchedModel NoSchedModel = {
107 MCSchedModel::DefaultIssueWidth,
108 MCSchedModel::DefaultMicroOpBufferSize,
109 MCSchedModel::DefaultLoopMicroOpBufferSize,
110 MCSchedModel::DefaultLoadLatency,
111 MCSchedModel::DefaultHighLatency,
112 MCSchedModel::DefaultMispredictPenalty,
113 false, // PostRAScheduler
114 false, // CompleteModel
115 false, // EnableIntervals
116 0, // Processor ID
117 nullptr, nullptr, 0, 0, // No instruction-level machine model.
118 nullptr, // No Itinerary
119 nullptr // No extra processor descriptor
120};
121
122// Sorted (by key) array of values for CPU subtype.
123extern const llvm::SubtargetSubTypeKV WebAssemblySubTypeKV[] = {
124 { "bleeding-edge", { { { 0x3fffULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
125 { "generic", { { { 0x12c0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
126 { "mvp", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
127};
128
129namespace WebAssembly_MC {
130unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
131 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
132 // Don't know how to resolve this scheduling class.
133 return 0;
134}
135} // end namespace WebAssembly_MC
136
137struct WebAssemblyGenMCSubtargetInfo : public MCSubtargetInfo {
138 WebAssemblyGenMCSubtargetInfo(const Triple &TT,
139 StringRef CPU, StringRef TuneCPU, StringRef FS,
140 ArrayRef<SubtargetFeatureKV> PF,
141 ArrayRef<SubtargetSubTypeKV> PD,
142 const MCWriteProcResEntry *WPR,
143 const MCWriteLatencyEntry *WL,
144 const MCReadAdvanceEntry *RA, const InstrStage *IS,
145 const unsigned *OC, const unsigned *FP) :
146 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
147 WPR, WL, RA, IS, OC, FP) { }
148
149 unsigned resolveVariantSchedClass(unsigned SchedClass,
150 const MCInst *MI, const MCInstrInfo *MCII,
151 unsigned CPUID) const override {
152 return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
153 }
154};
155
156static inline MCSubtargetInfo *createWebAssemblyMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
157 return new WebAssemblyGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, WebAssemblyFeatureKV, WebAssemblySubTypeKV,
158 WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
159 nullptr, nullptr, nullptr);
160}
161
162} // end namespace llvm
163
164#endif // GET_SUBTARGETINFO_MC_DESC
165
166
167#ifdef GET_SUBTARGETINFO_TARGET_DESC
168#undef GET_SUBTARGETINFO_TARGET_DESC
169
170#include "llvm/Support/Debug.h"
171#include "llvm/Support/raw_ostream.h"
172
173// ParseSubtargetFeatures - Parses features string setting specified
174// subtarget options.
175void llvm::WebAssemblySubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
176 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
177 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
178 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
179 InitMCProcessorInfo(CPU, TuneCPU, FS);
180 const FeatureBitset &Bits = getFeatureBits();
181 if (Bits[WebAssembly::FeatureAtomics]) HasAtomics = true;
182 if (Bits[WebAssembly::FeatureBulkMemory]) HasBulkMemory = true;
183 if (Bits[WebAssembly::FeatureExceptionHandling]) HasExceptionHandling = true;
184 if (Bits[WebAssembly::FeatureExtendedConst]) HasExtendedConst = true;
185 if (Bits[WebAssembly::FeatureHalfPrecision]) HasHalfPrecision = true;
186 if (Bits[WebAssembly::FeatureMultiMemory]) HasMultiMemory = true;
187 if (Bits[WebAssembly::FeatureMultivalue]) HasMultivalue = true;
188 if (Bits[WebAssembly::FeatureMutableGlobals]) HasMutableGlobals = true;
189 if (Bits[WebAssembly::FeatureNontrappingFPToInt]) HasNontrappingFPToInt = true;
190 if (Bits[WebAssembly::FeatureReferenceTypes]) HasReferenceTypes = true;
191 if (Bits[WebAssembly::FeatureRelaxedSIMD] && SIMDLevel < RelaxedSIMD) SIMDLevel = RelaxedSIMD;
192 if (Bits[WebAssembly::FeatureSIMD128] && SIMDLevel < SIMD128) SIMDLevel = SIMD128;
193 if (Bits[WebAssembly::FeatureSignExt]) HasSignExt = true;
194 if (Bits[WebAssembly::FeatureTailCall]) HasTailCall = true;
195}
196#endif // GET_SUBTARGETINFO_TARGET_DESC
197
198
199#ifdef GET_SUBTARGETINFO_HEADER
200#undef GET_SUBTARGETINFO_HEADER
201
202namespace llvm {
203class DFAPacketizer;
204namespace WebAssembly_MC {
205unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
206} // end namespace WebAssembly_MC
207
208struct WebAssemblyGenSubtargetInfo : public TargetSubtargetInfo {
209 explicit WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
210public:
211 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
212 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
213 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
214};
215} // end namespace llvm
216
217#endif // GET_SUBTARGETINFO_HEADER
218
219
220#ifdef GET_SUBTARGETINFO_CTOR
221#undef GET_SUBTARGETINFO_CTOR
222
223#include "llvm/CodeGen/TargetSchedule.h"
224
225namespace llvm {
226extern const llvm::SubtargetFeatureKV WebAssemblyFeatureKV[];
227extern const llvm::SubtargetSubTypeKV WebAssemblySubTypeKV[];
228extern const llvm::MCWriteProcResEntry WebAssemblyWriteProcResTable[];
229extern const llvm::MCWriteLatencyEntry WebAssemblyWriteLatencyTable[];
230extern const llvm::MCReadAdvanceEntry WebAssemblyReadAdvanceTable[];
231WebAssemblyGenSubtargetInfo::WebAssemblyGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
232 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(WebAssemblyFeatureKV, 14), ArrayRef(WebAssemblySubTypeKV, 3),
233 WebAssemblyWriteProcResTable, WebAssemblyWriteLatencyTable, WebAssemblyReadAdvanceTable,
234 nullptr, nullptr, nullptr) {}
235
236unsigned WebAssemblyGenSubtargetInfo
237::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
238 report_fatal_error("Expected a variant SchedClass");
239} // WebAssemblyGenSubtargetInfo::resolveSchedClass
240
241unsigned WebAssemblyGenSubtargetInfo
242::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
243 return WebAssembly_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
244} // WebAssemblyGenSubtargetInfo::resolveVariantSchedClass
245
246} // end namespace llvm
247
248#endif // GET_SUBTARGETINFO_CTOR
249
250
251#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
252#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
253
254#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
255
256
257#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
258#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
259
260#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
261
262