1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* X86 Mnemonic tables *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9namespace llvm {
10namespace X86 {
11
12#ifdef GET_X86_MNEMONIC_TABLES_H
13#undef GET_X86_MNEMONIC_TABLES_H
14
15bool isFSUBRP(unsigned Opcode);
16bool isVPDPBUSDS(unsigned Opcode);
17bool isPUNPCKLWD(unsigned Opcode);
18bool isPUNPCKLQDQ(unsigned Opcode);
19bool isRDFSBASE(unsigned Opcode);
20bool isVPCMOV(unsigned Opcode);
21bool isVDIVSD(unsigned Opcode);
22bool isVPEXTRW(unsigned Opcode);
23bool isLODSD(unsigned Opcode);
24bool isVPTESTNMQ(unsigned Opcode);
25bool isCVTSS2SD(unsigned Opcode);
26bool isVGETMANTPD(unsigned Opcode);
27bool isVMOVDQA64(unsigned Opcode);
28bool isINVLPG(unsigned Opcode);
29bool isVBROADCASTF64X4(unsigned Opcode);
30bool isVPERMI2Q(unsigned Opcode);
31bool isVPMOVSXBD(unsigned Opcode);
32bool isVFMSUB132SS(unsigned Opcode);
33bool isVPMOVUSDW(unsigned Opcode);
34bool isAAD(unsigned Opcode);
35bool isIDIV(unsigned Opcode);
36bool isCVTTPS2DQ(unsigned Opcode);
37bool isVBROADCASTF32X8(unsigned Opcode);
38bool isVFMSUBSS(unsigned Opcode);
39bool isEMMS(unsigned Opcode);
40bool isVPDPBSUD(unsigned Opcode);
41bool isPMOVSXWQ(unsigned Opcode);
42bool isPSRLW(unsigned Opcode);
43bool isMOVNTDQA(unsigned Opcode);
44bool isFUCOMPI(unsigned Opcode);
45bool isANDNPS(unsigned Opcode);
46bool isVINSERTF64X2(unsigned Opcode);
47bool isCLTS(unsigned Opcode);
48bool isSETSSBSY(unsigned Opcode);
49bool isVMULPD(unsigned Opcode);
50bool isVFMADDSUB132PS(unsigned Opcode);
51bool isVPMADCSWD(unsigned Opcode);
52bool isVSCATTERPF0DPS(unsigned Opcode);
53bool isXCHG(unsigned Opcode);
54bool isVGATHERPF1QPS(unsigned Opcode);
55bool isVCVTNEPS2BF16(unsigned Opcode);
56bool isVFMADDSS(unsigned Opcode);
57bool isINTO(unsigned Opcode);
58bool isANDPD(unsigned Opcode);
59bool isSEAMCALL(unsigned Opcode);
60bool isVPDPBSSDS(unsigned Opcode);
61bool isUNPCKHPS(unsigned Opcode);
62bool isSETZUCC(unsigned Opcode);
63bool isSHUFPD(unsigned Opcode);
64bool isFCMOVNB(unsigned Opcode);
65bool isCVTTSS2SI(unsigned Opcode);
66bool isEXTRQ(unsigned Opcode);
67bool isSHLD(unsigned Opcode);
68bool isVBROADCASTSS(unsigned Opcode);
69bool isCLUI(unsigned Opcode);
70bool isVINSERTI128(unsigned Opcode);
71bool isVBLENDPD(unsigned Opcode);
72bool isVPSHLDW(unsigned Opcode);
73bool isVCVTNEEPH2PS(unsigned Opcode);
74bool isVCVTTSD2SI(unsigned Opcode);
75bool isVSM4KEY4(unsigned Opcode);
76bool isWRMSRNS(unsigned Opcode);
77bool isCMPSB(unsigned Opcode);
78bool isMULSS(unsigned Opcode);
79bool isVMRUN(unsigned Opcode);
80bool isVPSRLVD(unsigned Opcode);
81bool isLEAVE(unsigned Opcode);
82bool isVGETMANTPS(unsigned Opcode);
83bool isXSHA256(unsigned Opcode);
84bool isBOUND(unsigned Opcode);
85bool isSFENCE(unsigned Opcode);
86bool isVPHADDD(unsigned Opcode);
87bool isADOX(unsigned Opcode);
88bool isVPSLLQ(unsigned Opcode);
89bool isPFRSQIT1(unsigned Opcode);
90bool isCLAC(unsigned Opcode);
91bool isKNOTW(unsigned Opcode);
92bool isVCVTPH2PD(unsigned Opcode);
93bool isVAESENC(unsigned Opcode);
94bool isMOVNTI(unsigned Opcode);
95bool isFXCH(unsigned Opcode);
96bool isPOPP(unsigned Opcode);
97bool isVPBLENDMD(unsigned Opcode);
98bool isFSINCOS(unsigned Opcode);
99bool isVPMULLW(unsigned Opcode);
100bool isVPMOVSXBW(unsigned Opcode);
101bool isSTC(unsigned Opcode);
102bool isVPINSRB(unsigned Opcode);
103bool isLWPVAL(unsigned Opcode);
104bool isKXORB(unsigned Opcode);
105bool isRSTORSSP(unsigned Opcode);
106bool isVPRORQ(unsigned Opcode);
107bool isVSM3MSG1(unsigned Opcode);
108bool isFICOM(unsigned Opcode);
109bool isMAXPS(unsigned Opcode);
110bool isFNCLEX(unsigned Opcode);
111bool isVMOVMSKPS(unsigned Opcode);
112bool isVPMOVDB(unsigned Opcode);
113bool isLLWPCB(unsigned Opcode);
114bool isVMULSS(unsigned Opcode);
115bool isAESENCLAST(unsigned Opcode);
116bool isVPMAXUB(unsigned Opcode);
117bool isAAS(unsigned Opcode);
118bool isFADD(unsigned Opcode);
119bool isJMP(unsigned Opcode);
120bool isXCRYPTECB(unsigned Opcode);
121bool isPFRCPIT1(unsigned Opcode);
122bool isPMULHRW(unsigned Opcode);
123bool isVCVTPH2PS(unsigned Opcode);
124bool isVPBLENDVB(unsigned Opcode);
125bool isPCMPESTRI(unsigned Opcode);
126bool isSENDUIPI(unsigned Opcode);
127bool isFLDLN2(unsigned Opcode);
128bool isVPMACSWD(unsigned Opcode);
129bool isSHA1MSG1(unsigned Opcode);
130bool isVADDPS(unsigned Opcode);
131bool isVCVTPS2DQ(unsigned Opcode);
132bool isPFPNACC(unsigned Opcode);
133bool isFMUL(unsigned Opcode);
134bool isFNSAVE(unsigned Opcode);
135bool isCDQE(unsigned Opcode);
136bool isVPMACSDD(unsigned Opcode);
137bool isVSQRTPS(unsigned Opcode);
138bool isCMPSQ(unsigned Opcode);
139bool isVPSCATTERDD(unsigned Opcode);
140bool isVRNDSCALESD(unsigned Opcode);
141bool isSUBPS(unsigned Opcode);
142bool isVMAXSH(unsigned Opcode);
143bool isFLDZ(unsigned Opcode);
144bool isVFNMADD132SS(unsigned Opcode);
145bool isLGDTW(unsigned Opcode);
146bool isINC(unsigned Opcode);
147bool isVPANDN(unsigned Opcode);
148bool isPABSB(unsigned Opcode);
149bool isVSHA512RNDS2(unsigned Opcode);
150bool isPHADDSW(unsigned Opcode);
151bool isVPMOVSQW(unsigned Opcode);
152bool isVPMAXUD(unsigned Opcode);
153bool isADDSUBPS(unsigned Opcode);
154bool isVPMACSSDQL(unsigned Opcode);
155bool isPXOR(unsigned Opcode);
156bool isVPSRAD(unsigned Opcode);
157bool isVPSHAB(unsigned Opcode);
158bool isBTR(unsigned Opcode);
159bool isKORW(unsigned Opcode);
160bool isVRANGESS(unsigned Opcode);
161bool isVCMPPS(unsigned Opcode);
162bool isVPLZCNTD(unsigned Opcode);
163bool isTDPBUUD(unsigned Opcode);
164bool isROUNDPS(unsigned Opcode);
165bool isFABS(unsigned Opcode);
166bool isSUBPD(unsigned Opcode);
167bool isGF2P8MULB(unsigned Opcode);
168bool isTZMSK(unsigned Opcode);
169bool isANDPS(unsigned Opcode);
170bool isVEXTRACTF32X8(unsigned Opcode);
171bool isSEAMRET(unsigned Opcode);
172bool isVPCOMW(unsigned Opcode);
173bool isVFIXUPIMMPD(unsigned Opcode);
174bool isKANDND(unsigned Opcode);
175bool isVMRESUME(unsigned Opcode);
176bool isCVTPD2DQ(unsigned Opcode);
177bool isVFNMADD213PS(unsigned Opcode);
178bool isVPEXTRD(unsigned Opcode);
179bool isPACKUSWB(unsigned Opcode);
180bool isVEXTRACTI32X8(unsigned Opcode);
181bool isVHADDPD(unsigned Opcode);
182bool isVPSADBW(unsigned Opcode);
183bool isMOVDQ2Q(unsigned Opcode);
184bool isPUNPCKHBW(unsigned Opcode);
185bool isXOR(unsigned Opcode);
186bool isPSIGNB(unsigned Opcode);
187bool isVPHADDSW(unsigned Opcode);
188bool isFADDP(unsigned Opcode);
189bool isNEG(unsigned Opcode);
190bool isFLDLG2(unsigned Opcode);
191bool isFNOP(unsigned Opcode);
192bool isVMINSS(unsigned Opcode);
193bool isPCMPISTRM(unsigned Opcode);
194bool isVFMADD132SS(unsigned Opcode);
195bool isFDIVRP(unsigned Opcode);
196bool isPUSHAL(unsigned Opcode);
197bool isVPMACSDQL(unsigned Opcode);
198bool isSUBSD(unsigned Opcode);
199bool isVPBLENDMQ(unsigned Opcode);
200bool isVGATHERDPS(unsigned Opcode);
201bool isSYSRET(unsigned Opcode);
202bool isVPADDB(unsigned Opcode);
203bool isXEND(unsigned Opcode);
204bool isWRSSD(unsigned Opcode);
205bool isVCVTDQ2PH(unsigned Opcode);
206bool isCVTPD2PS(unsigned Opcode);
207bool isMAXPD(unsigned Opcode);
208bool isRCPSS(unsigned Opcode);
209bool isVMOVAPD(unsigned Opcode);
210bool isVPSUBSB(unsigned Opcode);
211bool isRDTSC(unsigned Opcode);
212bool isVPMADCSSWD(unsigned Opcode);
213bool isVFNMADD213PH(unsigned Opcode);
214bool isVGF2P8AFFINEQB(unsigned Opcode);
215bool isPMOVZXWD(unsigned Opcode);
216bool isPMINUD(unsigned Opcode);
217bool isVCVTPH2UW(unsigned Opcode);
218bool isPADDSW(unsigned Opcode);
219bool isXSUSLDTRK(unsigned Opcode);
220bool isLFENCE(unsigned Opcode);
221bool isCRC32(unsigned Opcode);
222bool isAESENCWIDE256KL(unsigned Opcode);
223bool isMOVAPD(unsigned Opcode);
224bool isVFMADD213PS(unsigned Opcode);
225bool isVPDPWUUDS(unsigned Opcode);
226bool isMOVSLDUP(unsigned Opcode);
227bool isCLDEMOTE(unsigned Opcode);
228bool isVFNMADD231PS(unsigned Opcode);
229bool isVMOVMSKPD(unsigned Opcode);
230bool isPREFETCHT0(unsigned Opcode);
231bool isVCVTNEOBF162PS(unsigned Opcode);
232bool isVPCMPUD(unsigned Opcode);
233bool isVMAXSD(unsigned Opcode);
234bool isVRCP28SD(unsigned Opcode);
235bool isVMAXPS(unsigned Opcode);
236bool isVPMOVD2M(unsigned Opcode);
237bool isVPMACSSWD(unsigned Opcode);
238bool isVUCOMISD(unsigned Opcode);
239bool isLTR(unsigned Opcode);
240bool isVCVTUSI2SH(unsigned Opcode);
241bool isVSCATTERPF1QPS(unsigned Opcode);
242bool isWRGSBASE(unsigned Opcode);
243bool isSTOSQ(unsigned Opcode);
244bool isVSQRTSD(unsigned Opcode);
245bool isVPERMIL2PD(unsigned Opcode);
246bool isVFCMADDCSH(unsigned Opcode);
247bool isVFMADDSUB213PS(unsigned Opcode);
248bool isPFSUB(unsigned Opcode);
249bool isVSQRTSS(unsigned Opcode);
250bool isVEXPANDPS(unsigned Opcode);
251bool isVPCOMPRESSW(unsigned Opcode);
252bool isPEXTRD(unsigned Opcode);
253bool isSYSEXITQ(unsigned Opcode);
254bool isROUNDSD(unsigned Opcode);
255bool isFCOM(unsigned Opcode);
256bool isVFNMSUBSS(unsigned Opcode);
257bool isKSHIFTLW(unsigned Opcode);
258bool isSCASD(unsigned Opcode);
259bool isVMPTRLD(unsigned Opcode);
260bool isVAESDECLAST(unsigned Opcode);
261bool isVFMADDSUBPS(unsigned Opcode);
262bool isVCVTUQQ2PS(unsigned Opcode);
263bool isVPMOVUSDB(unsigned Opcode);
264bool isVPROTW(unsigned Opcode);
265bool isVDPPS(unsigned Opcode);
266bool isVRSQRT14PD(unsigned Opcode);
267bool isVTESTPD(unsigned Opcode);
268bool isVFNMADD231SH(unsigned Opcode);
269bool isENDBR64(unsigned Opcode);
270bool isMULSD(unsigned Opcode);
271bool isXRSTORS(unsigned Opcode);
272bool isPREFETCHNTA(unsigned Opcode);
273bool isVPCOMD(unsigned Opcode);
274bool isVPCOMUB(unsigned Opcode);
275bool isVPHSUBD(unsigned Opcode);
276bool isVBROADCASTI64X2(unsigned Opcode);
277bool isFPATAN(unsigned Opcode);
278bool isLOOPE(unsigned Opcode);
279bool isPCMPEQW(unsigned Opcode);
280bool isVFMADDCSH(unsigned Opcode);
281bool isVPDPBSSD(unsigned Opcode);
282bool isVFMSUBADD132PH(unsigned Opcode);
283bool isVPADDSB(unsigned Opcode);
284bool isKADDW(unsigned Opcode);
285bool isPTEST(unsigned Opcode);
286bool isVRSQRT28PS(unsigned Opcode);
287bool isVGF2P8AFFINEINVQB(unsigned Opcode);
288bool isSERIALIZE(unsigned Opcode);
289bool isVPHADDWQ(unsigned Opcode);
290bool isVRNDSCALESH(unsigned Opcode);
291bool isAAA(unsigned Opcode);
292bool isWRMSRLIST(unsigned Opcode);
293bool isXORPS(unsigned Opcode);
294bool isVCVTPH2PSX(unsigned Opcode);
295bool isVFMSUB231PH(unsigned Opcode);
296bool isVGATHERQPD(unsigned Opcode);
297bool isKADDB(unsigned Opcode);
298bool isCVTPD2PI(unsigned Opcode);
299bool isVFNMSUB213PH(unsigned Opcode);
300bool isVPCMPESTRI(unsigned Opcode);
301bool isVPSHRDW(unsigned Opcode);
302bool isPOP2(unsigned Opcode);
303bool isRDMSRLIST(unsigned Opcode);
304bool isVPDPBUSD(unsigned Opcode);
305bool isVCMPPH(unsigned Opcode);
306bool isVANDNPD(unsigned Opcode);
307bool isSUB(unsigned Opcode);
308bool isVRSQRT28PD(unsigned Opcode);
309bool isVFNMADD132PH(unsigned Opcode);
310bool isVPMACSSWW(unsigned Opcode);
311bool isXSTORE(unsigned Opcode);
312bool isVPROTQ(unsigned Opcode);
313bool isVPHADDBD(unsigned Opcode);
314bool isVPMAXSB(unsigned Opcode);
315bool isVMOVDQU8(unsigned Opcode);
316bool isVPMOVSXWD(unsigned Opcode);
317bool isSHA256RNDS2(unsigned Opcode);
318bool isKANDB(unsigned Opcode);
319bool isTPAUSE(unsigned Opcode);
320bool isPUSH(unsigned Opcode);
321bool isVRNDSCALESS(unsigned Opcode);
322bool isVPCMPISTRI(unsigned Opcode);
323bool isSTGI(unsigned Opcode);
324bool isSBB(unsigned Opcode);
325bool isBLCS(unsigned Opcode);
326bool isVCVTSD2SH(unsigned Opcode);
327bool isVPERMW(unsigned Opcode);
328bool isXRESLDTRK(unsigned Opcode);
329bool isAESENC256KL(unsigned Opcode);
330bool isVGATHERDPD(unsigned Opcode);
331bool isHRESET(unsigned Opcode);
332bool isVFMSUBADD231PD(unsigned Opcode);
333bool isVFRCZSS(unsigned Opcode);
334bool isMINPS(unsigned Opcode);
335bool isFPREM1(unsigned Opcode);
336bool isVPCMPUB(unsigned Opcode);
337bool isVSQRTPD(unsigned Opcode);
338bool isVFRCZPS(unsigned Opcode);
339bool isVFNMADD213SS(unsigned Opcode);
340bool isVPMOVDW(unsigned Opcode);
341bool isVPSHRDVQ(unsigned Opcode);
342bool isVBROADCASTSD(unsigned Opcode);
343bool isVSHUFPD(unsigned Opcode);
344bool isVPSUBSW(unsigned Opcode);
345bool isKUNPCKBW(unsigned Opcode);
346bool isVPBLENDD(unsigned Opcode);
347bool isUNPCKHPD(unsigned Opcode);
348bool isVFNMADD231SD(unsigned Opcode);
349bool isVPBROADCASTMW2D(unsigned Opcode);
350bool isVPMULTISHIFTQB(unsigned Opcode);
351bool isVP2INTERSECTQ(unsigned Opcode);
352bool isVPUNPCKHWD(unsigned Opcode);
353bool isVPERM2F128(unsigned Opcode);
354bool isINSD(unsigned Opcode);
355bool isLFS(unsigned Opcode);
356bool isFMULP(unsigned Opcode);
357bool isCWD(unsigned Opcode);
358bool isVDIVSS(unsigned Opcode);
359bool isVPSRLQ(unsigned Opcode);
360bool isFSQRT(unsigned Opcode);
361bool isJRCXZ(unsigned Opcode);
362bool isVPMOVMSKB(unsigned Opcode);
363bool isAESDEC256KL(unsigned Opcode);
364bool isFLDENV(unsigned Opcode);
365bool isVPHSUBWD(unsigned Opcode);
366bool isWBNOINVD(unsigned Opcode);
367bool isVEXPANDPD(unsigned Opcode);
368bool isFYL2XP1(unsigned Opcode);
369bool isPREFETCHT2(unsigned Opcode);
370bool isVPDPBSUDS(unsigned Opcode);
371bool isVSHA512MSG2(unsigned Opcode);
372bool isPMULHUW(unsigned Opcode);
373bool isKANDNB(unsigned Opcode);
374bool isVCVTUW2PH(unsigned Opcode);
375bool isAESDECWIDE256KL(unsigned Opcode);
376bool isVPGATHERDD(unsigned Opcode);
377bool isVREDUCESH(unsigned Opcode);
378bool isPOPFQ(unsigned Opcode);
379bool isPAVGUSB(unsigned Opcode);
380bool isVALIGND(unsigned Opcode);
381bool isVPHMINPOSUW(unsigned Opcode);
382bool isLIDTD(unsigned Opcode);
383bool isVPERMT2PD(unsigned Opcode);
384bool isVMLAUNCH(unsigned Opcode);
385bool isVPXORQ(unsigned Opcode);
386bool isMOVNTDQ(unsigned Opcode);
387bool isPOP2P(unsigned Opcode);
388bool isVADDPD(unsigned Opcode);
389bool isSMSW(unsigned Opcode);
390bool isVEXP2PD(unsigned Opcode);
391bool isPMULUDQ(unsigned Opcode);
392bool isIRET(unsigned Opcode);
393bool isMULPS(unsigned Opcode);
394bool isVFNMSUBPD(unsigned Opcode);
395bool isPHADDW(unsigned Opcode);
396bool isRDSEED(unsigned Opcode);
397bool isVPSHLW(unsigned Opcode);
398bool isRMPUPDATE(unsigned Opcode);
399bool isVFMADD231PH(unsigned Opcode);
400bool isVPSHAD(unsigned Opcode);
401bool isCLWB(unsigned Opcode);
402bool isPSUBUSB(unsigned Opcode);
403bool isVCVTTSD2USI(unsigned Opcode);
404bool isVEXTRACTPS(unsigned Opcode);
405bool isMOVLPD(unsigned Opcode);
406bool isLGDTD(unsigned Opcode);
407bool isVPBROADCASTMB2Q(unsigned Opcode);
408bool isOUT(unsigned Opcode);
409bool isVMSAVE(unsigned Opcode);
410bool isVCVTQQ2PD(unsigned Opcode);
411bool isVFMADD213PH(unsigned Opcode);
412bool isFCMOVBE(unsigned Opcode);
413bool isMOVSHDUP(unsigned Opcode);
414bool isVPMOVUSQB(unsigned Opcode);
415bool isFIST(unsigned Opcode);
416bool isHADDPD(unsigned Opcode);
417bool isPACKSSWB(unsigned Opcode);
418bool isVPMACSSDQH(unsigned Opcode);
419bool isVFNMSUB132SD(unsigned Opcode);
420bool isVPMASKMOVQ(unsigned Opcode);
421bool isVCOMPRESSPD(unsigned Opcode);
422bool isVFMADD213SS(unsigned Opcode);
423bool isVPCMPQ(unsigned Opcode);
424bool isVADDSH(unsigned Opcode);
425bool isVFNMADDSD(unsigned Opcode);
426bool isUMWAIT(unsigned Opcode);
427bool isVPUNPCKHDQ(unsigned Opcode);
428bool isLCALL(unsigned Opcode);
429bool isAESDEC128KL(unsigned Opcode);
430bool isVSUBPS(unsigned Opcode);
431bool isFSTP(unsigned Opcode);
432bool isVCVTUDQ2PD(unsigned Opcode);
433bool isVPMOVSWB(unsigned Opcode);
434bool isVPANDNQ(unsigned Opcode);
435bool isSYSENTER(unsigned Opcode);
436bool isVPHADDWD(unsigned Opcode);
437bool isVMOVHPD(unsigned Opcode);
438bool isMOVHPD(unsigned Opcode);
439bool isVDIVPH(unsigned Opcode);
440bool isFFREE(unsigned Opcode);
441bool isVGATHERPF1DPS(unsigned Opcode);
442bool isVFNMADD231PD(unsigned Opcode);
443bool isVFCMULCPH(unsigned Opcode);
444bool isVPADDD(unsigned Opcode);
445bool isVSM3MSG2(unsigned Opcode);
446bool isVPCOMUQ(unsigned Opcode);
447bool isVERR(unsigned Opcode);
448bool isKORTESTQ(unsigned Opcode);
449bool isVFMSUB132SD(unsigned Opcode);
450bool isTILEZERO(unsigned Opcode);
451bool isPFADD(unsigned Opcode);
452bool isVCVTSI2SD(unsigned Opcode);
453bool isVSTMXCSR(unsigned Opcode);
454bool isVCVTTSH2SI(unsigned Opcode);
455bool isRET(unsigned Opcode);
456bool isLZCNT(unsigned Opcode);
457bool isMULPD(unsigned Opcode);
458bool isVBROADCASTI32X2(unsigned Opcode);
459bool isVCVTPH2W(unsigned Opcode);
460bool isCQO(unsigned Opcode);
461bool isFSUBR(unsigned Opcode);
462bool isDPPD(unsigned Opcode);
463bool isFCOS(unsigned Opcode);
464bool isXSAVES(unsigned Opcode);
465bool isTZCNT(unsigned Opcode);
466bool isLJMP(unsigned Opcode);
467bool isCMOVCC(unsigned Opcode);
468bool isVCVTSS2SD(unsigned Opcode);
469bool isINVEPT(unsigned Opcode);
470bool isADDSUBPD(unsigned Opcode);
471bool isVMOVSHDUP(unsigned Opcode);
472bool isKSHIFTRD(unsigned Opcode);
473bool isVPTERNLOGD(unsigned Opcode);
474bool isPADDQ(unsigned Opcode);
475bool isVEXTRACTI64X4(unsigned Opcode);
476bool isVFMSUB231SS(unsigned Opcode);
477bool isVPCMPEQB(unsigned Opcode);
478bool isLEA(unsigned Opcode);
479bool isPSUBB(unsigned Opcode);
480bool isKADDQ(unsigned Opcode);
481bool isMOVSX(unsigned Opcode);
482bool isVALIGNQ(unsigned Opcode);
483bool isVCVTNE2PS2BF16(unsigned Opcode);
484bool isVPSRAW(unsigned Opcode);
485bool isVFMSUBADD231PH(unsigned Opcode);
486bool isCVTDQ2PS(unsigned Opcode);
487bool isFBLD(unsigned Opcode);
488bool isLMSW(unsigned Opcode);
489bool isWRMSR(unsigned Opcode);
490bool isMINSS(unsigned Opcode);
491bool isFSCALE(unsigned Opcode);
492bool isVFNMADD213SH(unsigned Opcode);
493bool isIMULZU(unsigned Opcode);
494bool isVPHADDUBD(unsigned Opcode);
495bool isRDSSPQ(unsigned Opcode);
496bool isLGDT(unsigned Opcode);
497bool isVPSHLDVD(unsigned Opcode);
498bool isPFCMPGT(unsigned Opcode);
499bool isVRNDSCALEPH(unsigned Opcode);
500bool isJCXZ(unsigned Opcode);
501bool isVPMOVZXBW(unsigned Opcode);
502bool isVFMADDSUB231PD(unsigned Opcode);
503bool isVBLENDMPD(unsigned Opcode);
504bool isHSUBPS(unsigned Opcode);
505bool isPREFETCHIT0(unsigned Opcode);
506bool isKTESTD(unsigned Opcode);
507bool isVCVTNEOPH2PS(unsigned Opcode);
508bool isVBLENDVPD(unsigned Opcode);
509bool isVCVTSS2USI(unsigned Opcode);
510bool isVPANDD(unsigned Opcode);
511bool isPMINSW(unsigned Opcode);
512bool isSTAC(unsigned Opcode);
513bool isVFMSUB213PS(unsigned Opcode);
514bool isPOPAL(unsigned Opcode);
515bool isVCVTPS2UQQ(unsigned Opcode);
516bool isRDRAND(unsigned Opcode);
517bool isJCC(unsigned Opcode);
518bool isVPMINSQ(unsigned Opcode);
519bool isVADDSD(unsigned Opcode);
520bool isDPPS(unsigned Opcode);
521bool isPINSRQ(unsigned Opcode);
522bool isVUCOMISS(unsigned Opcode);
523bool isVPDPWSUD(unsigned Opcode);
524bool isKANDNW(unsigned Opcode);
525bool isAOR(unsigned Opcode);
526bool isPMAXUB(unsigned Opcode);
527bool isANDNPD(unsigned Opcode);
528bool isINVPCID(unsigned Opcode);
529bool isRDGSBASE(unsigned Opcode);
530bool isVPMOVSQD(unsigned Opcode);
531bool isBT(unsigned Opcode);
532bool isVPROLVQ(unsigned Opcode);
533bool isVFMADDSUB132PD(unsigned Opcode);
534bool isRORX(unsigned Opcode);
535bool isPADDUSW(unsigned Opcode);
536bool isPFNACC(unsigned Opcode);
537bool isAND(unsigned Opcode);
538bool isPSLLQ(unsigned Opcode);
539bool isVFMSUB132PH(unsigned Opcode);
540bool isXSAVE(unsigned Opcode);
541bool isKNOTQ(unsigned Opcode);
542bool isXTEST(unsigned Opcode);
543bool isVINSERTPS(unsigned Opcode);
544bool isXSAVEOPT(unsigned Opcode);
545bool isLDS(unsigned Opcode);
546bool isVFMADDSUB213PD(unsigned Opcode);
547bool isVINSERTF32X4(unsigned Opcode);
548bool isVRSQRTPS(unsigned Opcode);
549bool isVSUBPH(unsigned Opcode);
550bool isPMOVSXBW(unsigned Opcode);
551bool isVPSRLDQ(unsigned Opcode);
552bool isADC(unsigned Opcode);
553bool isPHADDD(unsigned Opcode);
554bool isVMINPH(unsigned Opcode);
555bool isVMINSD(unsigned Opcode);
556bool isVROUNDPD(unsigned Opcode);
557bool isVFCMADDCPH(unsigned Opcode);
558bool isINCSSPQ(unsigned Opcode);
559bool isVPUNPCKLDQ(unsigned Opcode);
560bool isVMINSH(unsigned Opcode);
561bool isINSERTQ(unsigned Opcode);
562bool isBLCI(unsigned Opcode);
563bool isHLT(unsigned Opcode);
564bool isVPCOMUW(unsigned Opcode);
565bool isVPMOVSXDQ(unsigned Opcode);
566bool isVFNMSUB231PS(unsigned Opcode);
567bool isVFNMSUB213SH(unsigned Opcode);
568bool isVCVTTPD2UQQ(unsigned Opcode);
569bool isSQRTSS(unsigned Opcode);
570bool isIMUL(unsigned Opcode);
571bool isVCVTSS2SI(unsigned Opcode);
572bool isPUSHAW(unsigned Opcode);
573bool isSTOSD(unsigned Opcode);
574bool isPSRLDQ(unsigned Opcode);
575bool isVSCATTERQPS(unsigned Opcode);
576bool isFIDIV(unsigned Opcode);
577bool isVFMSUB213PD(unsigned Opcode);
578bool isVFMADDSUB231PH(unsigned Opcode);
579bool isTDCALL(unsigned Opcode);
580bool isPVALIDATE(unsigned Opcode);
581bool isVPSHUFLW(unsigned Opcode);
582bool isPCLMULQDQ(unsigned Opcode);
583bool isCMPXCHG8B(unsigned Opcode);
584bool isVPMOVM2B(unsigned Opcode);
585bool isVCVTUDQ2PH(unsigned Opcode);
586bool isPEXTRQ(unsigned Opcode);
587bool isXCRYPTCTR(unsigned Opcode);
588bool isVREDUCEPH(unsigned Opcode);
589bool isUCOMISD(unsigned Opcode);
590bool isOUTSD(unsigned Opcode);
591bool isSUBSS(unsigned Opcode);
592bool isVFMSUBPS(unsigned Opcode);
593bool isVPBLENDW(unsigned Opcode);
594bool isBZHI(unsigned Opcode);
595bool isVPRORVD(unsigned Opcode);
596bool isRMPQUERY(unsigned Opcode);
597bool isVPEXPANDB(unsigned Opcode);
598bool isVPSCATTERDQ(unsigned Opcode);
599bool isPSMASH(unsigned Opcode);
600bool isVPSHLDQ(unsigned Opcode);
601bool isVSCATTERPF1DPD(unsigned Opcode);
602bool isMONTMUL(unsigned Opcode);
603bool isVCVTPH2UQQ(unsigned Opcode);
604bool isPSLLD(unsigned Opcode);
605bool isSAR(unsigned Opcode);
606bool isLDTILECFG(unsigned Opcode);
607bool isPMINUB(unsigned Opcode);
608bool isVCVTNEEBF162PS(unsigned Opcode);
609bool isMOVDIR64B(unsigned Opcode);
610bool isSTR(unsigned Opcode);
611bool isKANDNQ(unsigned Opcode);
612bool isBSF(unsigned Opcode);
613bool isVPDPBUUDS(unsigned Opcode);
614bool isINCSSPD(unsigned Opcode);
615bool isSQRTPS(unsigned Opcode);
616bool isCMPXCHG(unsigned Opcode);
617bool isVPSIGNW(unsigned Opcode);
618bool isLES(unsigned Opcode);
619bool isCVTSS2SI(unsigned Opcode);
620bool isVPMOVUSWB(unsigned Opcode);
621bool isFCOMPI(unsigned Opcode);
622bool isPUNPCKHWD(unsigned Opcode);
623bool isPFACC(unsigned Opcode);
624bool isVPTESTNMW(unsigned Opcode);
625bool isVPMULDQ(unsigned Opcode);
626bool isSHRX(unsigned Opcode);
627bool isKXORQ(unsigned Opcode);
628bool isVGETEXPSD(unsigned Opcode);
629bool isV4FNMADDPS(unsigned Opcode);
630bool isVFNMSUB231SD(unsigned Opcode);
631bool isVPSHLD(unsigned Opcode);
632bool isPAVGB(unsigned Opcode);
633bool isPMOVZXBD(unsigned Opcode);
634bool isKORTESTW(unsigned Opcode);
635bool isVSHUFPS(unsigned Opcode);
636bool isAESENCWIDE128KL(unsigned Opcode);
637bool isVPXORD(unsigned Opcode);
638bool isVPSHAW(unsigned Opcode);
639bool isVPERMT2B(unsigned Opcode);
640bool isVFMADD213PD(unsigned Opcode);
641bool isVPGATHERQD(unsigned Opcode);
642bool isVPCMPGTW(unsigned Opcode);
643bool isVGETMANTSH(unsigned Opcode);
644bool isVANDPS(unsigned Opcode);
645bool isVDIVPS(unsigned Opcode);
646bool isVANDNPS(unsigned Opcode);
647bool isVPBROADCASTW(unsigned Opcode);
648bool isFLDL2T(unsigned Opcode);
649bool isVPERMB(unsigned Opcode);
650bool isFCMOVNBE(unsigned Opcode);
651bool isVCVTTPH2W(unsigned Opcode);
652bool isPMOVZXBQ(unsigned Opcode);
653bool isPF2ID(unsigned Opcode);
654bool isVFNMADD132PD(unsigned Opcode);
655bool isPMULHRSW(unsigned Opcode);
656bool isKADDD(unsigned Opcode);
657bool isVFNMSUB132SH(unsigned Opcode);
658bool isUIRET(unsigned Opcode);
659bool isBSR(unsigned Opcode);
660bool isPCMPEQQ(unsigned Opcode);
661bool isCDQ(unsigned Opcode);
662bool isPMAXSW(unsigned Opcode);
663bool isSIDTD(unsigned Opcode);
664bool isVCVTPS2PHX(unsigned Opcode);
665bool isVPSLLVQ(unsigned Opcode);
666bool isMOVQ(unsigned Opcode);
667bool isPREFETCH(unsigned Opcode);
668bool isCLRSSBSY(unsigned Opcode);
669bool isPSHUFW(unsigned Opcode);
670bool isVPDPWSUDS(unsigned Opcode);
671bool isVPMOVSXBQ(unsigned Opcode);
672bool isFICOMP(unsigned Opcode);
673bool isVLDMXCSR(unsigned Opcode);
674bool isVPSUBUSW(unsigned Opcode);
675bool isVFNMSUB132SS(unsigned Opcode);
676bool isRETF(unsigned Opcode);
677bool isKMOVQ(unsigned Opcode);
678bool isVPADDUSW(unsigned Opcode);
679bool isPACKSSDW(unsigned Opcode);
680bool isUMONITOR(unsigned Opcode);
681bool isENQCMDS(unsigned Opcode);
682bool isVPMAXSQ(unsigned Opcode);
683bool isVPERMT2Q(unsigned Opcode);
684bool isFDECSTP(unsigned Opcode);
685bool isVPTESTMQ(unsigned Opcode);
686bool isVRCP14PD(unsigned Opcode);
687bool isARPL(unsigned Opcode);
688bool isVFMSUB213SD(unsigned Opcode);
689bool isJMPABS(unsigned Opcode);
690bool isVUNPCKHPS(unsigned Opcode);
691bool isVFNMADDSS(unsigned Opcode);
692bool isSIDT(unsigned Opcode);
693bool isVPCMPGTB(unsigned Opcode);
694bool isVPRORD(unsigned Opcode);
695bool isVSUBSS(unsigned Opcode);
696bool isPUSHFQ(unsigned Opcode);
697bool isVPCLMULQDQ(unsigned Opcode);
698bool isVPADDUSB(unsigned Opcode);
699bool isVPCMPD(unsigned Opcode);
700bool isMOVSD(unsigned Opcode);
701bool isPSUBUSW(unsigned Opcode);
702bool isVFMSUBADD132PS(unsigned Opcode);
703bool isMOVMSKPS(unsigned Opcode);
704bool isVFIXUPIMMSS(unsigned Opcode);
705bool isMFENCE(unsigned Opcode);
706bool isFTST(unsigned Opcode);
707bool isVPMADDWD(unsigned Opcode);
708bool isPOP(unsigned Opcode);
709bool isPSUBW(unsigned Opcode);
710bool isBSWAP(unsigned Opcode);
711bool isPFMIN(unsigned Opcode);
712bool isVFPCLASSPD(unsigned Opcode);
713bool isVPSHRDVD(unsigned Opcode);
714bool isPADDW(unsigned Opcode);
715bool isCVTSI2SD(unsigned Opcode);
716bool isENQCMD(unsigned Opcode);
717bool isXSHA1(unsigned Opcode);
718bool isVFNMADD132SD(unsigned Opcode);
719bool isMOVZX(unsigned Opcode);
720bool isVFIXUPIMMSD(unsigned Opcode);
721bool isINVD(unsigned Opcode);
722bool isVFIXUPIMMPS(unsigned Opcode);
723bool isMOVDQU(unsigned Opcode);
724bool isVFPCLASSPS(unsigned Opcode);
725bool isMOVSQ(unsigned Opcode);
726bool isAESDECWIDE128KL(unsigned Opcode);
727bool isROUNDSS(unsigned Opcode);
728bool isVPERMILPS(unsigned Opcode);
729bool isVPMOVW2M(unsigned Opcode);
730bool isVMULSD(unsigned Opcode);
731bool isVPERMI2W(unsigned Opcode);
732bool isVPSHUFB(unsigned Opcode);
733bool isFST(unsigned Opcode);
734bool isVPHSUBW(unsigned Opcode);
735bool isVREDUCESS(unsigned Opcode);
736bool isFRNDINT(unsigned Opcode);
737bool isSHR(unsigned Opcode);
738bool isLOOPNE(unsigned Opcode);
739bool isVCVTTPH2UQQ(unsigned Opcode);
740bool isSHA1NEXTE(unsigned Opcode);
741bool isVFMADD132SD(unsigned Opcode);
742bool isPSRAW(unsigned Opcode);
743bool isVPBROADCASTQ(unsigned Opcode);
744bool isCLC(unsigned Opcode);
745bool isPOPAW(unsigned Opcode);
746bool isTCMMIMFP16PS(unsigned Opcode);
747bool isVCVTTPS2UQQ(unsigned Opcode);
748bool isVCVTQQ2PH(unsigned Opcode);
749bool isVMOVUPD(unsigned Opcode);
750bool isFPTAN(unsigned Opcode);
751bool isVMASKMOVPD(unsigned Opcode);
752bool isVMOVLHPS(unsigned Opcode);
753bool isAESKEYGENASSIST(unsigned Opcode);
754bool isXSAVEOPT64(unsigned Opcode);
755bool isXSAVEC(unsigned Opcode);
756bool isVPLZCNTQ(unsigned Opcode);
757bool isVPSUBW(unsigned Opcode);
758bool isCMPCCXADD(unsigned Opcode);
759bool isVFMSUBADD213PH(unsigned Opcode);
760bool isVFMADDSUBPD(unsigned Opcode);
761bool isVPMINSW(unsigned Opcode);
762bool isVFNMSUB132PS(unsigned Opcode);
763bool isVMOVAPS(unsigned Opcode);
764bool isVPEXTRQ(unsigned Opcode);
765bool isVSCALEFSH(unsigned Opcode);
766bool isVCVTPD2PS(unsigned Opcode);
767bool isCLGI(unsigned Opcode);
768bool isVAESDEC(unsigned Opcode);
769bool isPFMUL(unsigned Opcode);
770bool isMOVDIRI(unsigned Opcode);
771bool isSHUFPS(unsigned Opcode);
772bool isVFNMSUB231SS(unsigned Opcode);
773bool isVMWRITE(unsigned Opcode);
774bool isVINSERTF128(unsigned Opcode);
775bool isFISUBR(unsigned Opcode);
776bool isVINSERTI32X4(unsigned Opcode);
777bool isVPSLLDQ(unsigned Opcode);
778bool isPOPCNT(unsigned Opcode);
779bool isVXORPD(unsigned Opcode);
780bool isXLATB(unsigned Opcode);
781bool isDIV(unsigned Opcode);
782bool isVPSHLDVQ(unsigned Opcode);
783bool isMOVDDUP(unsigned Opcode);
784bool isVMOVDQU64(unsigned Opcode);
785bool isVPCOMPRESSQ(unsigned Opcode);
786bool isVFMSUBADD132PD(unsigned Opcode);
787bool isADDSD(unsigned Opcode);
788bool isBLENDPD(unsigned Opcode);
789bool isVPERMILPD(unsigned Opcode);
790bool isPMADDUBSW(unsigned Opcode);
791bool isPOPFD(unsigned Opcode);
792bool isCMPSW(unsigned Opcode);
793bool isLDMXCSR(unsigned Opcode);
794bool isVMULPS(unsigned Opcode);
795bool isVROUNDSD(unsigned Opcode);
796bool isVFMADD132PD(unsigned Opcode);
797bool isVPANDQ(unsigned Opcode);
798bool isVPSRAQ(unsigned Opcode);
799bool isVCOMISD(unsigned Opcode);
800bool isFFREEP(unsigned Opcode);
801bool isVFNMADD213PD(unsigned Opcode);
802bool isVCMPPD(unsigned Opcode);
803bool isVFNMSUB132PH(unsigned Opcode);
804bool isVPHADDBW(unsigned Opcode);
805bool isVPPERM(unsigned Opcode);
806bool isVCVTPS2PD(unsigned Opcode);
807bool isCBW(unsigned Opcode);
808bool isVMOVUPS(unsigned Opcode);
809bool isVPMAXUQ(unsigned Opcode);
810bool isWRSSQ(unsigned Opcode);
811bool isPACKUSDW(unsigned Opcode);
812bool isXBEGIN(unsigned Opcode);
813bool isVCVTPD2UQQ(unsigned Opcode);
814bool isFCMOVB(unsigned Opcode);
815bool isNOP(unsigned Opcode);
816bool isVPABSQ(unsigned Opcode);
817bool isVTESTPS(unsigned Opcode);
818bool isPHSUBW(unsigned Opcode);
819bool isPUSH2P(unsigned Opcode);
820bool isFISTTP(unsigned Opcode);
821bool isCFCMOVCC(unsigned Opcode);
822bool isVPINSRD(unsigned Opcode);
823bool isPCMPESTRM(unsigned Opcode);
824bool isVFNMSUB213PS(unsigned Opcode);
825bool isPHSUBD(unsigned Opcode);
826bool isSLDT(unsigned Opcode);
827bool isVPMINSD(unsigned Opcode);
828bool isVHADDPS(unsigned Opcode);
829bool isVMOVNTDQ(unsigned Opcode);
830bool isVFRCZSD(unsigned Opcode);
831bool isVPTESTMW(unsigned Opcode);
832bool isVPMOVZXWD(unsigned Opcode);
833bool isPSADBW(unsigned Opcode);
834bool isVCVTSD2SI(unsigned Opcode);
835bool isVMAXPH(unsigned Opcode);
836bool isLODSB(unsigned Opcode);
837bool isPHMINPOSUW(unsigned Opcode);
838bool isVPROLVD(unsigned Opcode);
839bool isWRFSBASE(unsigned Opcode);
840bool isVRSQRT14PS(unsigned Opcode);
841bool isVPHSUBDQ(unsigned Opcode);
842bool isIRETD(unsigned Opcode);
843bool isCVTSI2SS(unsigned Opcode);
844bool isVPMULHRSW(unsigned Opcode);
845bool isPI2FD(unsigned Opcode);
846bool isGF2P8AFFINEQB(unsigned Opcode);
847bool isPAND(unsigned Opcode);
848bool isVFNMSUB231SH(unsigned Opcode);
849bool isVMOVHLPS(unsigned Opcode);
850bool isPEXTRB(unsigned Opcode);
851bool isKNOTD(unsigned Opcode);
852bool isVPUNPCKLQDQ(unsigned Opcode);
853bool isVMMCALL(unsigned Opcode);
854bool isVCVTSH2SS(unsigned Opcode);
855bool isVPERMIL2PS(unsigned Opcode);
856bool isVPCMPGTD(unsigned Opcode);
857bool isCMPXCHG16B(unsigned Opcode);
858bool isVZEROUPPER(unsigned Opcode);
859bool isMOVAPS(unsigned Opcode);
860bool isVPCMPW(unsigned Opcode);
861bool isFUCOMPP(unsigned Opcode);
862bool isXSETBV(unsigned Opcode);
863bool isSLWPCB(unsigned Opcode);
864bool isSCASW(unsigned Opcode);
865bool isFCMOVNE(unsigned Opcode);
866bool isPBNDKB(unsigned Opcode);
867bool isVPMULLD(unsigned Opcode);
868bool isVP4DPWSSDS(unsigned Opcode);
869bool isPINSRW(unsigned Opcode);
870bool isVCVTSI2SH(unsigned Opcode);
871bool isVINSERTF32X8(unsigned Opcode);
872bool isKSHIFTLB(unsigned Opcode);
873bool isSEAMOPS(unsigned Opcode);
874bool isVPMULUDQ(unsigned Opcode);
875bool isVPMOVSQB(unsigned Opcode);
876bool isVPTESTMD(unsigned Opcode);
877bool isVPHADDDQ(unsigned Opcode);
878bool isKUNPCKDQ(unsigned Opcode);
879bool isT1MSKC(unsigned Opcode);
880bool isVPCOMB(unsigned Opcode);
881bool isVBLENDPS(unsigned Opcode);
882bool isPTWRITE(unsigned Opcode);
883bool isCVTPS2PI(unsigned Opcode);
884bool isVPROTD(unsigned Opcode);
885bool isCALL(unsigned Opcode);
886bool isVPERMPS(unsigned Opcode);
887bool isVPSHUFBITQMB(unsigned Opcode);
888bool isVMOVSLDUP(unsigned Opcode);
889bool isINVLPGA(unsigned Opcode);
890bool isVCVTPH2QQ(unsigned Opcode);
891bool isADD(unsigned Opcode);
892bool isPSUBSW(unsigned Opcode);
893bool isSIDTW(unsigned Opcode);
894bool isVFNMADD231PH(unsigned Opcode);
895bool isVEXTRACTF64X2(unsigned Opcode);
896bool isFCOMI(unsigned Opcode);
897bool isRSM(unsigned Opcode);
898bool isVPCOMUD(unsigned Opcode);
899bool isVPMOVZXBQ(unsigned Opcode);
900bool isUWRMSR(unsigned Opcode);
901bool isLGS(unsigned Opcode);
902bool isVMOVNTPD(unsigned Opcode);
903bool isRDPRU(unsigned Opcode);
904bool isVPUNPCKHBW(unsigned Opcode);
905bool isANDN(unsigned Opcode);
906bool isVCVTTPH2UW(unsigned Opcode);
907bool isVMFUNC(unsigned Opcode);
908bool isFIMUL(unsigned Opcode);
909bool isBLCFILL(unsigned Opcode);
910bool isVGATHERPF0DPS(unsigned Opcode);
911bool isVFMSUBADD231PS(unsigned Opcode);
912bool isVREDUCESD(unsigned Opcode);
913bool isVXORPS(unsigned Opcode);
914bool isPSWAPD(unsigned Opcode);
915bool isPMAXSD(unsigned Opcode);
916bool isVCMPSS(unsigned Opcode);
917bool isEXTRACTPS(unsigned Opcode);
918bool isVPMOVZXBD(unsigned Opcode);
919bool isOUTSW(unsigned Opcode);
920bool isKORTESTB(unsigned Opcode);
921bool isVREDUCEPS(unsigned Opcode);
922bool isPEXTRW(unsigned Opcode);
923bool isFNINIT(unsigned Opcode);
924bool isROL(unsigned Opcode);
925bool isVCVTPS2QQ(unsigned Opcode);
926bool isVGETMANTPH(unsigned Opcode);
927bool isPUNPCKLDQ(unsigned Opcode);
928bool isPADDD(unsigned Opcode);
929bool isVPSLLD(unsigned Opcode);
930bool isPFCMPGE(unsigned Opcode);
931bool isVPMOVM2D(unsigned Opcode);
932bool isVHSUBPS(unsigned Opcode);
933bool isENDBR32(unsigned Opcode);
934bool isMOVSXD(unsigned Opcode);
935bool isPSIGND(unsigned Opcode);
936bool isVPTEST(unsigned Opcode);
937bool isVPDPWUSD(unsigned Opcode);
938bool isHSUBPD(unsigned Opcode);
939bool isADCX(unsigned Opcode);
940bool isCVTTPD2PI(unsigned Opcode);
941bool isPDEP(unsigned Opcode);
942bool isTDPBUSD(unsigned Opcode);
943bool isVBROADCASTI32X4(unsigned Opcode);
944bool isVCVTPH2UDQ(unsigned Opcode);
945bool isVPHADDW(unsigned Opcode);
946bool isFLDL2E(unsigned Opcode);
947bool isCLZERO(unsigned Opcode);
948bool isPBLENDW(unsigned Opcode);
949bool isVCVTSH2USI(unsigned Opcode);
950bool isVANDPD(unsigned Opcode);
951bool isBEXTR(unsigned Opcode);
952bool isSTD(unsigned Opcode);
953bool isVAESKEYGENASSIST(unsigned Opcode);
954bool isCMPSD(unsigned Opcode);
955bool isMOVSS(unsigned Opcode);
956bool isVCVTUQQ2PD(unsigned Opcode);
957bool isVEXTRACTI32X4(unsigned Opcode);
958bool isFLDCW(unsigned Opcode);
959bool isINSW(unsigned Opcode);
960bool isRDPID(unsigned Opcode);
961bool isKANDQ(unsigned Opcode);
962bool isV4FMADDPS(unsigned Opcode);
963bool isPMOVZXWQ(unsigned Opcode);
964bool isVFPCLASSSD(unsigned Opcode);
965bool isBLENDPS(unsigned Opcode);
966bool isVPACKSSDW(unsigned Opcode);
967bool isVPINSRW(unsigned Opcode);
968bool isFXAM(unsigned Opcode);
969bool isVPHSUBBW(unsigned Opcode);
970bool isVSHUFF64X2(unsigned Opcode);
971bool isVPACKUSWB(unsigned Opcode);
972bool isVRSQRT28SS(unsigned Opcode);
973bool isGETSEC(unsigned Opcode);
974bool isVEXTRACTF64X4(unsigned Opcode);
975bool isBLSR(unsigned Opcode);
976bool isFILD(unsigned Opcode);
977bool isRETFQ(unsigned Opcode);
978bool isVADDSS(unsigned Opcode);
979bool isCOMISS(unsigned Opcode);
980bool isCLI(unsigned Opcode);
981bool isVERW(unsigned Opcode);
982bool isBTC(unsigned Opcode);
983bool isVPHADDUBQ(unsigned Opcode);
984bool isVPORQ(unsigned Opcode);
985bool isORPD(unsigned Opcode);
986bool isVMOVSS(unsigned Opcode);
987bool isVPSUBD(unsigned Opcode);
988bool isVGATHERPF1QPD(unsigned Opcode);
989bool isENCODEKEY256(unsigned Opcode);
990bool isGF2P8AFFINEINVQB(unsigned Opcode);
991bool isXRSTOR64(unsigned Opcode);
992bool isKANDW(unsigned Opcode);
993bool isLODSQ(unsigned Opcode);
994bool isVSUBSH(unsigned Opcode);
995bool isLSS(unsigned Opcode);
996bool isPMOVSXBQ(unsigned Opcode);
997bool isVCMPSH(unsigned Opcode);
998bool isVFMADD132PS(unsigned Opcode);
999bool isVPACKSSWB(unsigned Opcode);
1000bool isPCMPGTQ(unsigned Opcode);
1001bool isVFMADD132SH(unsigned Opcode);
1002bool isVCVTUQQ2PH(unsigned Opcode);
1003bool isVCVTQQ2PS(unsigned Opcode);
1004bool isVCVTTSS2USI(unsigned Opcode);
1005bool isVPMOVM2Q(unsigned Opcode);
1006bool isVMOVD(unsigned Opcode);
1007bool isVFPCLASSPH(unsigned Opcode);
1008bool isVCVTSS2SH(unsigned Opcode);
1009bool isSCASB(unsigned Opcode);
1010bool isPSRLD(unsigned Opcode);
1011bool isVADDPH(unsigned Opcode);
1012bool isFSUB(unsigned Opcode);
1013bool isVEXTRACTI64X2(unsigned Opcode);
1014bool isPMINUW(unsigned Opcode);
1015bool isPSUBSB(unsigned Opcode);
1016bool isVPSHLDD(unsigned Opcode);
1017bool isVPCMPEQD(unsigned Opcode);
1018bool isVPSCATTERQD(unsigned Opcode);
1019bool isKXNORB(unsigned Opcode);
1020bool isLDDQU(unsigned Opcode);
1021bool isMASKMOVQ(unsigned Opcode);
1022bool isPABSW(unsigned Opcode);
1023bool isVPROLD(unsigned Opcode);
1024bool isVPCOMQ(unsigned Opcode);
1025bool isVSCATTERDPD(unsigned Opcode);
1026bool isFXRSTOR(unsigned Opcode);
1027bool isVPCMPUW(unsigned Opcode);
1028bool isWBINVD(unsigned Opcode);
1029bool isVCVTTPD2UDQ(unsigned Opcode);
1030bool isERETU(unsigned Opcode);
1031bool isPFRCPIT2(unsigned Opcode);
1032bool isVPERMT2W(unsigned Opcode);
1033bool isVEXTRACTF32X4(unsigned Opcode);
1034bool isVGATHERPF0DPD(unsigned Opcode);
1035bool isVBROADCASTF32X2(unsigned Opcode);
1036bool isVRCP14SD(unsigned Opcode);
1037bool isPABSD(unsigned Opcode);
1038bool isLAHF(unsigned Opcode);
1039bool isPINSRB(unsigned Opcode);
1040bool isSKINIT(unsigned Opcode);
1041bool isENTER(unsigned Opcode);
1042bool isVCVTSI2SS(unsigned Opcode);
1043bool isVFMADD231PD(unsigned Opcode);
1044bool isLOADIWKEY(unsigned Opcode);
1045bool isVMOVNTDQA(unsigned Opcode);
1046bool isVPERMT2PS(unsigned Opcode);
1047bool isPUSHF(unsigned Opcode);
1048bool isMPSADBW(unsigned Opcode);
1049bool isVRSQRT14SS(unsigned Opcode);
1050bool isVCVTDQ2PD(unsigned Opcode);
1051bool isVORPS(unsigned Opcode);
1052bool isVPEXPANDQ(unsigned Opcode);
1053bool isVPSHRDD(unsigned Opcode);
1054bool isTDPBSSD(unsigned Opcode);
1055bool isTESTUI(unsigned Opcode);
1056bool isVFMADDPD(unsigned Opcode);
1057bool isVPANDND(unsigned Opcode);
1058bool isVPMOVSDB(unsigned Opcode);
1059bool isVPBROADCASTB(unsigned Opcode);
1060bool isCVTPI2PD(unsigned Opcode);
1061bool isVPERMI2B(unsigned Opcode);
1062bool isVPMINSB(unsigned Opcode);
1063bool isLAR(unsigned Opcode);
1064bool isINVLPGB(unsigned Opcode);
1065bool isTLBSYNC(unsigned Opcode);
1066bool isFDIVP(unsigned Opcode);
1067bool isVPSRLW(unsigned Opcode);
1068bool isVRCP28SS(unsigned Opcode);
1069bool isVMOVHPS(unsigned Opcode);
1070bool isVPMACSSDD(unsigned Opcode);
1071bool isPEXT(unsigned Opcode);
1072bool isVRSQRT14SD(unsigned Opcode);
1073bool isVPDPWSSD(unsigned Opcode);
1074bool isVFMSUB231SD(unsigned Opcode);
1075bool isVPMOVZXWQ(unsigned Opcode);
1076bool isVMOVDQA(unsigned Opcode);
1077bool isVFNMSUB213SD(unsigned Opcode);
1078bool isVMINPS(unsigned Opcode);
1079bool isVFMSUB231PS(unsigned Opcode);
1080bool isVPCOMPRESSB(unsigned Opcode);
1081bool isVPCMPEQQ(unsigned Opcode);
1082bool isVRCPSS(unsigned Opcode);
1083bool isVSCATTERPF1DPS(unsigned Opcode);
1084bool isVPHADDUBW(unsigned Opcode);
1085bool isXORPD(unsigned Opcode);
1086bool isVPSCATTERQQ(unsigned Opcode);
1087bool isVCVTW2PH(unsigned Opcode);
1088bool isVFMADDCPH(unsigned Opcode);
1089bool isVSUBPD(unsigned Opcode);
1090bool isVPACKUSDW(unsigned Opcode);
1091bool isVSCALEFSS(unsigned Opcode);
1092bool isAESIMC(unsigned Opcode);
1093bool isVRCP28PS(unsigned Opcode);
1094bool isAAND(unsigned Opcode);
1095bool isDAA(unsigned Opcode);
1096bool isVCVTPD2UDQ(unsigned Opcode);
1097bool isKTESTW(unsigned Opcode);
1098bool isVPADDQ(unsigned Opcode);
1099bool isPALIGNR(unsigned Opcode);
1100bool isPMAXUW(unsigned Opcode);
1101bool isVFMADDSD(unsigned Opcode);
1102bool isPFMAX(unsigned Opcode);
1103bool isVPOR(unsigned Opcode);
1104bool isVPSUBB(unsigned Opcode);
1105bool isVPAVGB(unsigned Opcode);
1106bool isINSB(unsigned Opcode);
1107bool isFYL2X(unsigned Opcode);
1108bool isVFNMSUB132PD(unsigned Opcode);
1109bool isVFNMSUBPS(unsigned Opcode);
1110bool isVFMADD231PS(unsigned Opcode);
1111bool isVCVTTSS2SI(unsigned Opcode);
1112bool isTCMMRLFP16PS(unsigned Opcode);
1113bool isFCOMPP(unsigned Opcode);
1114bool isMOVD(unsigned Opcode);
1115bool isMOVBE(unsigned Opcode);
1116bool isVP2INTERSECTD(unsigned Opcode);
1117bool isVPMULLQ(unsigned Opcode);
1118bool isVSCALEFPS(unsigned Opcode);
1119bool isVPMACSDQH(unsigned Opcode);
1120bool isVPTESTNMD(unsigned Opcode);
1121bool isFCOMP(unsigned Opcode);
1122bool isPREFETCHWT1(unsigned Opcode);
1123bool isVCMPSD(unsigned Opcode);
1124bool isSGDTD(unsigned Opcode);
1125bool isWRUSSD(unsigned Opcode);
1126bool isFSUBP(unsigned Opcode);
1127bool isVUNPCKLPS(unsigned Opcode);
1128bool isVFNMSUB213SS(unsigned Opcode);
1129bool isROUNDPD(unsigned Opcode);
1130bool isVPMAXSW(unsigned Opcode);
1131bool isVCVTTPH2DQ(unsigned Opcode);
1132bool isVPUNPCKLWD(unsigned Opcode);
1133bool isKSHIFTLD(unsigned Opcode);
1134bool isVFMADD231SD(unsigned Opcode);
1135bool isADDPS(unsigned Opcode);
1136bool isVPSLLVD(unsigned Opcode);
1137bool isVFNMADD132SH(unsigned Opcode);
1138bool isVMOVNTPS(unsigned Opcode);
1139bool isVCVTPD2DQ(unsigned Opcode);
1140bool isVPXOR(unsigned Opcode);
1141bool isSTMXCSR(unsigned Opcode);
1142bool isVRCP14SS(unsigned Opcode);
1143bool isUD2(unsigned Opcode);
1144bool isVPOPCNTW(unsigned Opcode);
1145bool isVRSQRTSH(unsigned Opcode);
1146bool isVSCATTERPF0DPD(unsigned Opcode);
1147bool isVFMADDPS(unsigned Opcode);
1148bool isXSAVEC64(unsigned Opcode);
1149bool isVPMADDUBSW(unsigned Opcode);
1150bool isVPMOVZXDQ(unsigned Opcode);
1151bool isVRCP14PS(unsigned Opcode);
1152bool isVSQRTSH(unsigned Opcode);
1153bool isLOOP(unsigned Opcode);
1154bool isSTUI(unsigned Opcode);
1155bool isVCVTTPS2UDQ(unsigned Opcode);
1156bool isVCOMPRESSPS(unsigned Opcode);
1157bool isXABORT(unsigned Opcode);
1158bool isVPADDW(unsigned Opcode);
1159bool isVPSIGND(unsigned Opcode);
1160bool isVRNDSCALEPS(unsigned Opcode);
1161bool isVPHADDUWD(unsigned Opcode);
1162bool isVDBPSADBW(unsigned Opcode);
1163bool isPSLLW(unsigned Opcode);
1164bool isVPMOVQD(unsigned Opcode);
1165bool isVINSERTI64X4(unsigned Opcode);
1166bool isVPERMI2PS(unsigned Opcode);
1167bool isVMULPH(unsigned Opcode);
1168bool isVPCMPUQ(unsigned Opcode);
1169bool isVCVTUSI2SD(unsigned Opcode);
1170bool isKXNORW(unsigned Opcode);
1171bool isBLCIC(unsigned Opcode);
1172bool isVFNMADD213SD(unsigned Opcode);
1173bool isVPMACSWW(unsigned Opcode);
1174bool isVMOVLPS(unsigned Opcode);
1175bool isPCONFIG(unsigned Opcode);
1176bool isPANDN(unsigned Opcode);
1177bool isVGETEXPPD(unsigned Opcode);
1178bool isVPSRLVQ(unsigned Opcode);
1179bool isUD1(unsigned Opcode);
1180bool isPMAXSB(unsigned Opcode);
1181bool isVPROLQ(unsigned Opcode);
1182bool isVSCATTERPF1QPD(unsigned Opcode);
1183bool isVPSRLD(unsigned Opcode);
1184bool isINT3(unsigned Opcode);
1185bool isXRSTORS64(unsigned Opcode);
1186bool isCVTSD2SI(unsigned Opcode);
1187bool isVMAXSS(unsigned Opcode);
1188bool isVPMINUB(unsigned Opcode);
1189bool isKXNORQ(unsigned Opcode);
1190bool isFLD(unsigned Opcode);
1191bool isVSHUFI32X4(unsigned Opcode);
1192bool isSAHF(unsigned Opcode);
1193bool isPFRSQRT(unsigned Opcode);
1194bool isSHRD(unsigned Opcode);
1195bool isSYSEXIT(unsigned Opcode);
1196bool isXSAVE64(unsigned Opcode);
1197bool isVPMAXSD(unsigned Opcode);
1198bool isCVTTSD2SI(unsigned Opcode);
1199bool isPMOVMSKB(unsigned Opcode);
1200bool isVRANGEPS(unsigned Opcode);
1201bool isVADDSUBPS(unsigned Opcode);
1202bool isVBROADCASTI128(unsigned Opcode);
1203bool isPADDUSB(unsigned Opcode);
1204bool isENCODEKEY128(unsigned Opcode);
1205bool isOR(unsigned Opcode);
1206bool isSTOSW(unsigned Opcode);
1207bool isPAVGW(unsigned Opcode);
1208bool isVCVTPD2PH(unsigned Opcode);
1209bool isSHLX(unsigned Opcode);
1210bool isVCVTSH2SD(unsigned Opcode);
1211bool isVFMADD231SS(unsigned Opcode);
1212bool isMOVNTSD(unsigned Opcode);
1213bool isFLDPI(unsigned Opcode);
1214bool isVCVTUSI2SS(unsigned Opcode);
1215bool isPMOVSXBD(unsigned Opcode);
1216bool isVPRORVQ(unsigned Opcode);
1217bool isVPERMT2D(unsigned Opcode);
1218bool isADDSS(unsigned Opcode);
1219bool isAADD(unsigned Opcode);
1220bool isVPSRLVW(unsigned Opcode);
1221bool isVRSQRTPH(unsigned Opcode);
1222bool isVLDDQU(unsigned Opcode);
1223bool isKMOVD(unsigned Opcode);
1224bool isENCLV(unsigned Opcode);
1225bool isENCLU(unsigned Opcode);
1226bool isPREFETCHT1(unsigned Opcode);
1227bool isRSQRTPS(unsigned Opcode);
1228bool isVCVTTSH2USI(unsigned Opcode);
1229bool isPADDB(unsigned Opcode);
1230bool isVMASKMOVDQU(unsigned Opcode);
1231bool isPUNPCKLBW(unsigned Opcode);
1232bool isMOV(unsigned Opcode);
1233bool isMUL(unsigned Opcode);
1234bool isRCL(unsigned Opcode);
1235bool isVRCPSH(unsigned Opcode);
1236bool isPFCMPEQ(unsigned Opcode);
1237bool isMONITOR(unsigned Opcode);
1238bool isFDIVR(unsigned Opcode);
1239bool isPMINSD(unsigned Opcode);
1240bool isPFRCP(unsigned Opcode);
1241bool isKTESTQ(unsigned Opcode);
1242bool isVCVTTPD2DQ(unsigned Opcode);
1243bool isVSHUFF32X4(unsigned Opcode);
1244bool isVPSLLVW(unsigned Opcode);
1245bool isTDPBSUD(unsigned Opcode);
1246bool isVPMINUQ(unsigned Opcode);
1247bool isFIADD(unsigned Opcode);
1248bool isFCMOVNU(unsigned Opcode);
1249bool isVHSUBPD(unsigned Opcode);
1250bool isKSHIFTRQ(unsigned Opcode);
1251bool isMOVUPS(unsigned Opcode);
1252bool isVMCALL(unsigned Opcode);
1253bool isXADD(unsigned Opcode);
1254bool isXRSTOR(unsigned Opcode);
1255bool isVGATHERPF1DPD(unsigned Opcode);
1256bool isRCR(unsigned Opcode);
1257bool isFNSTCW(unsigned Opcode);
1258bool isVPMOVSDW(unsigned Opcode);
1259bool isVFMSUB132SH(unsigned Opcode);
1260bool isVPCONFLICTQ(unsigned Opcode);
1261bool isSWAPGS(unsigned Opcode);
1262bool isVPMOVQ2M(unsigned Opcode);
1263bool isVPSRAVW(unsigned Opcode);
1264bool isMOVDQA(unsigned Opcode);
1265bool isDIVSD(unsigned Opcode);
1266bool isPCMPGTB(unsigned Opcode);
1267bool isSHA256MSG2(unsigned Opcode);
1268bool isKXORW(unsigned Opcode);
1269bool isLIDTW(unsigned Opcode);
1270bool isPMULHW(unsigned Opcode);
1271bool isVAESENCLAST(unsigned Opcode);
1272bool isVINSERTI32X8(unsigned Opcode);
1273bool isVRCPPS(unsigned Opcode);
1274bool isVGATHERQPS(unsigned Opcode);
1275bool isCTESTCC(unsigned Opcode);
1276bool isPMADDWD(unsigned Opcode);
1277bool isUCOMISS(unsigned Opcode);
1278bool isXGETBV(unsigned Opcode);
1279bool isVCVTPD2QQ(unsigned Opcode);
1280bool isVGETEXPPS(unsigned Opcode);
1281bool isFISTP(unsigned Opcode);
1282bool isVINSERTF64X4(unsigned Opcode);
1283bool isVMOVDQU16(unsigned Opcode);
1284bool isVFMADD132PH(unsigned Opcode);
1285bool isVFMSUBADD213PS(unsigned Opcode);
1286bool isVMOVDQU32(unsigned Opcode);
1287bool isFUCOM(unsigned Opcode);
1288bool isHADDPS(unsigned Opcode);
1289bool isCMP(unsigned Opcode);
1290bool isCVTTPS2PI(unsigned Opcode);
1291bool isIRETQ(unsigned Opcode);
1292bool isPF2IW(unsigned Opcode);
1293bool isPSHUFD(unsigned Opcode);
1294bool isVDPPD(unsigned Opcode);
1295bool isPSHUFHW(unsigned Opcode);
1296bool isRMPADJUST(unsigned Opcode);
1297bool isPI2FW(unsigned Opcode);
1298bool isVCVTTPH2QQ(unsigned Opcode);
1299bool isDIVPD(unsigned Opcode);
1300bool isCLFLUSH(unsigned Opcode);
1301bool isVPMINUW(unsigned Opcode);
1302bool isIN(unsigned Opcode);
1303bool isWRPKRU(unsigned Opcode);
1304bool isINSERTPS(unsigned Opcode);
1305bool isAAM(unsigned Opcode);
1306bool isVPHADDUDQ(unsigned Opcode);
1307bool isVSHA512MSG1(unsigned Opcode);
1308bool isDIVPS(unsigned Opcode);
1309bool isKNOTB(unsigned Opcode);
1310bool isBLSFILL(unsigned Opcode);
1311bool isVPCMPGTQ(unsigned Opcode);
1312bool isMINSD(unsigned Opcode);
1313bool isFPREM(unsigned Opcode);
1314bool isVPUNPCKHQDQ(unsigned Opcode);
1315bool isMINPD(unsigned Opcode);
1316bool isVCVTTPD2QQ(unsigned Opcode);
1317bool isVFMSUBPD(unsigned Opcode);
1318bool isV4FMADDSS(unsigned Opcode);
1319bool isCPUID(unsigned Opcode);
1320bool isSETCC(unsigned Opcode);
1321bool isVPDPWUUD(unsigned Opcode);
1322bool isPMOVSXDQ(unsigned Opcode);
1323bool isMWAIT(unsigned Opcode);
1324bool isVPEXTRB(unsigned Opcode);
1325bool isINVVPID(unsigned Opcode);
1326bool isVPSHUFD(unsigned Opcode);
1327bool isMOVLPS(unsigned Opcode);
1328bool isVBLENDMPS(unsigned Opcode);
1329bool isPMULLW(unsigned Opcode);
1330bool isVCVTSH2SI(unsigned Opcode);
1331bool isVPMOVSXWQ(unsigned Opcode);
1332bool isFNSTENV(unsigned Opcode);
1333bool isVPERMI2PD(unsigned Opcode);
1334bool isMAXSS(unsigned Opcode);
1335bool isCWDE(unsigned Opcode);
1336bool isVBROADCASTI32X8(unsigned Opcode);
1337bool isINT(unsigned Opcode);
1338bool isENCLS(unsigned Opcode);
1339bool isMOVNTQ(unsigned Opcode);
1340bool isVDIVSH(unsigned Opcode);
1341bool isMOVHLPS(unsigned Opcode);
1342bool isVPMASKMOVD(unsigned Opcode);
1343bool isVMOVSD(unsigned Opcode);
1344bool isVPMINUD(unsigned Opcode);
1345bool isVPCMPISTRM(unsigned Opcode);
1346bool isVGETMANTSD(unsigned Opcode);
1347bool isKSHIFTRW(unsigned Opcode);
1348bool isAESDECLAST(unsigned Opcode);
1349bool isVPTESTMB(unsigned Opcode);
1350bool isVMPTRST(unsigned Opcode);
1351bool isLLDT(unsigned Opcode);
1352bool isMOVSB(unsigned Opcode);
1353bool isTILELOADD(unsigned Opcode);
1354bool isKTESTB(unsigned Opcode);
1355bool isMOVUPD(unsigned Opcode);
1356bool isLKGS(unsigned Opcode);
1357bool isSGDTW(unsigned Opcode);
1358bool isDIVSS(unsigned Opcode);
1359bool isPUNPCKHQDQ(unsigned Opcode);
1360bool isVFMADD213SD(unsigned Opcode);
1361bool isKXORD(unsigned Opcode);
1362bool isVPMOVB2M(unsigned Opcode);
1363bool isVMREAD(unsigned Opcode);
1364bool isVPDPWSSDS(unsigned Opcode);
1365bool isTILERELEASE(unsigned Opcode);
1366bool isCLFLUSHOPT(unsigned Opcode);
1367bool isDAS(unsigned Opcode);
1368bool isVSCALEFPH(unsigned Opcode);
1369bool isVSUBSD(unsigned Opcode);
1370bool isVCOMISS(unsigned Opcode);
1371bool isORPS(unsigned Opcode);
1372bool isTDPFP16PS(unsigned Opcode);
1373bool isVMAXPD(unsigned Opcode);
1374bool isVPMOVWB(unsigned Opcode);
1375bool isVEXP2PS(unsigned Opcode);
1376bool isVPGATHERDQ(unsigned Opcode);
1377bool isVPSRAVQ(unsigned Opcode);
1378bool isPCMPISTRI(unsigned Opcode);
1379bool isVFMSUB231PD(unsigned Opcode);
1380bool isRDMSR(unsigned Opcode);
1381bool isKORTESTD(unsigned Opcode);
1382bool isVPBLENDMW(unsigned Opcode);
1383bool isPSHUFB(unsigned Opcode);
1384bool isVDPBF16PS(unsigned Opcode);
1385bool isTDPBF16PS(unsigned Opcode);
1386bool isFCMOVE(unsigned Opcode);
1387bool isCMPSS(unsigned Opcode);
1388bool isMASKMOVDQU(unsigned Opcode);
1389bool isVPDPWUSDS(unsigned Opcode);
1390bool isSARX(unsigned Opcode);
1391bool isSGDT(unsigned Opcode);
1392bool isVFMULCPH(unsigned Opcode);
1393bool isURDMSR(unsigned Opcode);
1394bool isKUNPCKWD(unsigned Opcode);
1395bool isCVTPS2PD(unsigned Opcode);
1396bool isFBSTP(unsigned Opcode);
1397bool isPSUBQ(unsigned Opcode);
1398bool isFXSAVE64(unsigned Opcode);
1399bool isKMOVW(unsigned Opcode);
1400bool isBTS(unsigned Opcode);
1401bool isVPHADDBQ(unsigned Opcode);
1402bool isFRSTOR(unsigned Opcode);
1403bool isVFMSUB132PD(unsigned Opcode);
1404bool isPMULLD(unsigned Opcode);
1405bool isSHA1MSG2(unsigned Opcode);
1406bool isJECXZ(unsigned Opcode);
1407bool isVCVTUDQ2PS(unsigned Opcode);
1408bool isAESENC(unsigned Opcode);
1409bool isPSIGNW(unsigned Opcode);
1410bool isUNPCKLPD(unsigned Opcode);
1411bool isPUSHP(unsigned Opcode);
1412bool isBLSI(unsigned Opcode);
1413bool isVPTESTNMB(unsigned Opcode);
1414bool isWRUSSQ(unsigned Opcode);
1415bool isVGF2P8MULB(unsigned Opcode);
1416bool isVPUNPCKLBW(unsigned Opcode);
1417bool isVRANGESD(unsigned Opcode);
1418bool isCLD(unsigned Opcode);
1419bool isVSCALEFPD(unsigned Opcode);
1420bool isVPERMQ(unsigned Opcode);
1421bool isVPSHLDVW(unsigned Opcode);
1422bool isROR(unsigned Opcode);
1423bool isVFMADDSUB132PH(unsigned Opcode);
1424bool isDEC(unsigned Opcode);
1425bool isVGETEXPSH(unsigned Opcode);
1426bool isAESDEC(unsigned Opcode);
1427bool isKORD(unsigned Opcode);
1428bool isVPMULHW(unsigned Opcode);
1429bool isTILELOADDT1(unsigned Opcode);
1430bool isVMASKMOVPS(unsigned Opcode);
1431bool isPMOVZXDQ(unsigned Opcode);
1432bool isVCVTPS2PH(unsigned Opcode);
1433bool isCVTDQ2PD(unsigned Opcode);
1434bool isVCVTSD2SS(unsigned Opcode);
1435bool isVFMSUB213PH(unsigned Opcode);
1436bool isVPROTB(unsigned Opcode);
1437bool isPINSRD(unsigned Opcode);
1438bool isVMXON(unsigned Opcode);
1439bool isVFCMULCSH(unsigned Opcode);
1440bool isVFMULCSH(unsigned Opcode);
1441bool isVRANGEPD(unsigned Opcode);
1442bool isCMC(unsigned Opcode);
1443bool isSHA256MSG1(unsigned Opcode);
1444bool isFLD1(unsigned Opcode);
1445bool isCMPPS(unsigned Opcode);
1446bool isVPAVGW(unsigned Opcode);
1447bool isVFMADD213SH(unsigned Opcode);
1448bool isVPINSRQ(unsigned Opcode);
1449bool isMOVABS(unsigned Opcode);
1450bool isVPSHAQ(unsigned Opcode);
1451bool isRDTSCP(unsigned Opcode);
1452bool isVFNMADD231SS(unsigned Opcode);
1453bool isTEST(unsigned Opcode);
1454bool isVPERMD(unsigned Opcode);
1455bool isVBCSTNESH2PS(unsigned Opcode);
1456bool isVGATHERPF0QPD(unsigned Opcode);
1457bool isVPERM2I128(unsigned Opcode);
1458bool isVMPSADBW(unsigned Opcode);
1459bool isVFNMSUB231PD(unsigned Opcode);
1460bool isPADDSB(unsigned Opcode);
1461bool isMWAITX(unsigned Opcode);
1462bool isMONITORX(unsigned Opcode);
1463bool isVPEXPANDD(unsigned Opcode);
1464bool isVFRCZPD(unsigned Opcode);
1465bool isVRCPPH(unsigned Opcode);
1466bool isFEMMS(unsigned Opcode);
1467bool isVSCATTERQPD(unsigned Opcode);
1468bool isVMOVW(unsigned Opcode);
1469bool isVPBROADCASTD(unsigned Opcode);
1470bool isSTOSB(unsigned Opcode);
1471bool isFUCOMI(unsigned Opcode);
1472bool isVBROADCASTI64X4(unsigned Opcode);
1473bool isFCMOVU(unsigned Opcode);
1474bool isPSHUFLW(unsigned Opcode);
1475bool isCVTPI2PS(unsigned Opcode);
1476bool isVFMADD231SH(unsigned Opcode);
1477bool isSYSCALL(unsigned Opcode);
1478bool isVPOPCNTB(unsigned Opcode);
1479bool isPMOVZXBW(unsigned Opcode);
1480bool isVCVTDQ2PS(unsigned Opcode);
1481bool isPSUBD(unsigned Opcode);
1482bool isVPCMPEQW(unsigned Opcode);
1483bool isMOVSW(unsigned Opcode);
1484bool isVSM3RNDS2(unsigned Opcode);
1485bool isVPMOVUSQD(unsigned Opcode);
1486bool isCVTTPD2DQ(unsigned Opcode);
1487bool isVPEXPANDW(unsigned Opcode);
1488bool isVUCOMISH(unsigned Opcode);
1489bool isVZEROALL(unsigned Opcode);
1490bool isVPAND(unsigned Opcode);
1491bool isPMULDQ(unsigned Opcode);
1492bool isVPSHUFHW(unsigned Opcode);
1493bool isVPALIGNR(unsigned Opcode);
1494bool isSQRTSD(unsigned Opcode);
1495bool isVCVTTPH2UDQ(unsigned Opcode);
1496bool isVGETEXPPH(unsigned Opcode);
1497bool isADDPD(unsigned Opcode);
1498bool isVFNMADDPD(unsigned Opcode);
1499bool isSTTILECFG(unsigned Opcode);
1500bool isVMINPD(unsigned Opcode);
1501bool isSHA1RNDS4(unsigned Opcode);
1502bool isPBLENDVB(unsigned Opcode);
1503bool isVBROADCASTF128(unsigned Opcode);
1504bool isVPSHRDQ(unsigned Opcode);
1505bool isVAESIMC(unsigned Opcode);
1506bool isCOMISD(unsigned Opcode);
1507bool isVMOVSH(unsigned Opcode);
1508bool isPFSUBR(unsigned Opcode);
1509bool isRDSSPD(unsigned Opcode);
1510bool isWAIT(unsigned Opcode);
1511bool isVFPCLASSSS(unsigned Opcode);
1512bool isPCMPGTD(unsigned Opcode);
1513bool isVGATHERPF0QPS(unsigned Opcode);
1514bool isBLENDVPS(unsigned Opcode);
1515bool isVBROADCASTF32X4(unsigned Opcode);
1516bool isVPMADD52LUQ(unsigned Opcode);
1517bool isVMOVLPD(unsigned Opcode);
1518bool isVMOVQ(unsigned Opcode);
1519bool isVMOVDQU(unsigned Opcode);
1520bool isAESENC128KL(unsigned Opcode);
1521bool isVFMADDSUB231PS(unsigned Opcode);
1522bool isVFNMSUB213PD(unsigned Opcode);
1523bool isVPCONFLICTD(unsigned Opcode);
1524bool isVFMADDSUB213PH(unsigned Opcode);
1525bool isVPHSUBSW(unsigned Opcode);
1526bool isPUNPCKHDQ(unsigned Opcode);
1527bool isVSHUFI64X2(unsigned Opcode);
1528bool isVFMSUBSD(unsigned Opcode);
1529bool isVPORD(unsigned Opcode);
1530bool isRCPPS(unsigned Opcode);
1531bool isVEXTRACTI128(unsigned Opcode);
1532bool isVPSHRDVW(unsigned Opcode);
1533bool isVUNPCKLPD(unsigned Opcode);
1534bool isVPSRAVD(unsigned Opcode);
1535bool isVMULSH(unsigned Opcode);
1536bool isMOVNTSS(unsigned Opcode);
1537bool isSTI(unsigned Opcode);
1538bool isVSM4RNDS4(unsigned Opcode);
1539bool isVMCLEAR(unsigned Opcode);
1540bool isVPMADD52HUQ(unsigned Opcode);
1541bool isLIDT(unsigned Opcode);
1542bool isPUSH2(unsigned Opcode);
1543bool isRDPKRU(unsigned Opcode);
1544bool isVPCMPB(unsigned Opcode);
1545bool isFINCSTP(unsigned Opcode);
1546bool isKORQ(unsigned Opcode);
1547bool isXCRYPTCBC(unsigned Opcode);
1548bool isRDPMC(unsigned Opcode);
1549bool isMOVMSKPD(unsigned Opcode);
1550bool isVFMSUB231SH(unsigned Opcode);
1551bool isVEXTRACTF128(unsigned Opcode);
1552bool isVPSHLB(unsigned Opcode);
1553bool isXSAVES64(unsigned Opcode);
1554bool isSHL(unsigned Opcode);
1555bool isAXOR(unsigned Opcode);
1556bool isVINSERTI64X2(unsigned Opcode);
1557bool isSYSRETQ(unsigned Opcode);
1558bool isVSCATTERPF0QPD(unsigned Opcode);
1559bool isVFMSUB213SH(unsigned Opcode);
1560bool isVPMOVQW(unsigned Opcode);
1561bool isVREDUCEPD(unsigned Opcode);
1562bool isNOT(unsigned Opcode);
1563bool isLWPINS(unsigned Opcode);
1564bool isVSCATTERDPS(unsigned Opcode);
1565bool isVPMOVM2W(unsigned Opcode);
1566bool isVFNMADD132PS(unsigned Opcode);
1567bool isMOVNTPS(unsigned Opcode);
1568bool isVRSQRTSS(unsigned Opcode);
1569bool isKMOVB(unsigned Opcode);
1570bool isCVTSD2SS(unsigned Opcode);
1571bool isVBROADCASTF64X2(unsigned Opcode);
1572bool isMOVNTPD(unsigned Opcode);
1573bool isMAXSD(unsigned Opcode);
1574bool isCMPPD(unsigned Opcode);
1575bool isVPCMPESTRM(unsigned Opcode);
1576bool isVFMSUB132PS(unsigned Opcode);
1577bool isVCOMISH(unsigned Opcode);
1578bool isF2XM1(unsigned Opcode);
1579bool isSQRTPD(unsigned Opcode);
1580bool isVFMSUBADDPS(unsigned Opcode);
1581bool isFXTRACT(unsigned Opcode);
1582bool isVP4DPWSSD(unsigned Opcode);
1583bool isVFMSUBADDPD(unsigned Opcode);
1584bool isVBCSTNEBF162PS(unsigned Opcode);
1585bool isVPGATHERQQ(unsigned Opcode);
1586bool isPCMPEQB(unsigned Opcode);
1587bool isTILESTORED(unsigned Opcode);
1588bool isBLSMSK(unsigned Opcode);
1589bool isVCVTTPS2DQ(unsigned Opcode);
1590bool isVRNDSCALEPD(unsigned Opcode);
1591bool isVMLOAD(unsigned Opcode);
1592bool isVPTERNLOGQ(unsigned Opcode);
1593bool isKXNORD(unsigned Opcode);
1594bool isFXSAVE(unsigned Opcode);
1595bool isVUNPCKHPD(unsigned Opcode);
1596bool isCVTPS2DQ(unsigned Opcode);
1597bool isVFMSUB213SS(unsigned Opcode);
1598bool isVPOPCNTD(unsigned Opcode);
1599bool isSALC(unsigned Opcode);
1600bool isV4FNMADDSS(unsigned Opcode);
1601bool isXCRYPTOFB(unsigned Opcode);
1602bool isVORPD(unsigned Opcode);
1603bool isLSL(unsigned Opcode);
1604bool isXCRYPTCFB(unsigned Opcode);
1605bool isVGETEXPSS(unsigned Opcode);
1606bool isPSLLDQ(unsigned Opcode);
1607bool isVPDPBUUD(unsigned Opcode);
1608bool isVMXOFF(unsigned Opcode);
1609bool isBLSIC(unsigned Opcode);
1610bool isMOVLHPS(unsigned Opcode);
1611bool isVFNMSUBSD(unsigned Opcode);
1612bool isVFPCLASSSH(unsigned Opcode);
1613bool isVPSHLQ(unsigned Opcode);
1614bool isVROUNDPS(unsigned Opcode);
1615bool isVSCATTERPF0QPS(unsigned Opcode);
1616bool isERETS(unsigned Opcode);
1617bool isVPERMI2D(unsigned Opcode);
1618bool isFUCOMP(unsigned Opcode);
1619bool isVCVTTPS2QQ(unsigned Opcode);
1620bool isPUSHFD(unsigned Opcode);
1621bool isKORB(unsigned Opcode);
1622bool isVRCP28PD(unsigned Opcode);
1623bool isVPABSD(unsigned Opcode);
1624bool isVROUNDSS(unsigned Opcode);
1625bool isVCVTSD2USI(unsigned Opcode);
1626bool isVPABSB(unsigned Opcode);
1627bool isPMAXUD(unsigned Opcode);
1628bool isVPMULHUW(unsigned Opcode);
1629bool isVPERMPD(unsigned Opcode);
1630bool isFCHS(unsigned Opcode);
1631bool isVPBLENDMB(unsigned Opcode);
1632bool isVGETMANTSS(unsigned Opcode);
1633bool isVPSLLW(unsigned Opcode);
1634bool isVDIVPD(unsigned Opcode);
1635bool isBLCMSK(unsigned Opcode);
1636bool isFDIV(unsigned Opcode);
1637bool isRSQRTSS(unsigned Opcode);
1638bool isPOR(unsigned Opcode);
1639bool isVMOVDQA32(unsigned Opcode);
1640bool isVPHADDUWQ(unsigned Opcode);
1641bool isPSRAD(unsigned Opcode);
1642bool isPREFETCHW(unsigned Opcode);
1643bool isFIDIVR(unsigned Opcode);
1644bool isMOVHPS(unsigned Opcode);
1645bool isVFNMSUB231PH(unsigned Opcode);
1646bool isUNPCKLPS(unsigned Opcode);
1647bool isVPSIGNB(unsigned Opcode);
1648bool isSAVEPREVSSP(unsigned Opcode);
1649bool isVSCALEFSD(unsigned Opcode);
1650bool isFSIN(unsigned Opcode);
1651bool isSCASQ(unsigned Opcode);
1652bool isPCMPGTW(unsigned Opcode);
1653bool isMULX(unsigned Opcode);
1654bool isVPMAXUW(unsigned Opcode);
1655bool isPAUSE(unsigned Opcode);
1656bool isMOVQ2DQ(unsigned Opcode);
1657bool isVPSUBQ(unsigned Opcode);
1658bool isVPABSW(unsigned Opcode);
1659bool isVPCOMPRESSD(unsigned Opcode);
1660bool isVPMOVUSQW(unsigned Opcode);
1661bool isBLENDVPD(unsigned Opcode);
1662bool isVPMOVQB(unsigned Opcode);
1663bool isVBLENDVPS(unsigned Opcode);
1664bool isKSHIFTLQ(unsigned Opcode);
1665bool isPMOVSXWD(unsigned Opcode);
1666bool isPHSUBSW(unsigned Opcode);
1667bool isPSRLQ(unsigned Opcode);
1668bool isVCVTPH2DQ(unsigned Opcode);
1669bool isFISUB(unsigned Opcode);
1670bool isVCVTPS2UDQ(unsigned Opcode);
1671bool isVMOVDDUP(unsigned Opcode);
1672bool isPCMPEQD(unsigned Opcode);
1673bool isVRSQRT28SD(unsigned Opcode);
1674bool isLODSW(unsigned Opcode);
1675bool isVPOPCNTQ(unsigned Opcode);
1676bool isKSHIFTRB(unsigned Opcode);
1677bool isVFNMADDPS(unsigned Opcode);
1678bool isCCMPCC(unsigned Opcode);
1679bool isFXRSTOR64(unsigned Opcode);
1680bool isVFMSUBADD213PD(unsigned Opcode);
1681bool isVSQRTPH(unsigned Opcode);
1682bool isPOPF(unsigned Opcode);
1683bool isVPSUBUSB(unsigned Opcode);
1684bool isPREFETCHIT1(unsigned Opcode);
1685bool isVPADDSW(unsigned Opcode);
1686bool isVADDSUBPD(unsigned Opcode);
1687bool isKANDD(unsigned Opcode);
1688bool isOUTSB(unsigned Opcode);
1689bool isFNSTSW(unsigned Opcode);
1690bool isPMINSB(unsigned Opcode);
1691#endif // GET_X86_MNEMONIC_TABLES_H
1692
1693#ifdef GET_X86_MNEMONIC_TABLES_CPP
1694#undef GET_X86_MNEMONIC_TABLES_CPP
1695
1696bool isFSUBRP(unsigned Opcode) {
1697 return Opcode == SUBR_FPrST0;
1698}
1699
1700bool isVPDPBUSDS(unsigned Opcode) {
1701 switch (Opcode) {
1702 case VPDPBUSDSYrm:
1703 case VPDPBUSDSYrr:
1704 case VPDPBUSDSZ128m:
1705 case VPDPBUSDSZ128mb:
1706 case VPDPBUSDSZ128mbk:
1707 case VPDPBUSDSZ128mbkz:
1708 case VPDPBUSDSZ128mk:
1709 case VPDPBUSDSZ128mkz:
1710 case VPDPBUSDSZ128r:
1711 case VPDPBUSDSZ128rk:
1712 case VPDPBUSDSZ128rkz:
1713 case VPDPBUSDSZ256m:
1714 case VPDPBUSDSZ256mb:
1715 case VPDPBUSDSZ256mbk:
1716 case VPDPBUSDSZ256mbkz:
1717 case VPDPBUSDSZ256mk:
1718 case VPDPBUSDSZ256mkz:
1719 case VPDPBUSDSZ256r:
1720 case VPDPBUSDSZ256rk:
1721 case VPDPBUSDSZ256rkz:
1722 case VPDPBUSDSZm:
1723 case VPDPBUSDSZmb:
1724 case VPDPBUSDSZmbk:
1725 case VPDPBUSDSZmbkz:
1726 case VPDPBUSDSZmk:
1727 case VPDPBUSDSZmkz:
1728 case VPDPBUSDSZr:
1729 case VPDPBUSDSZrk:
1730 case VPDPBUSDSZrkz:
1731 case VPDPBUSDSrm:
1732 case VPDPBUSDSrr:
1733 return true;
1734 }
1735 return false;
1736}
1737
1738bool isPUNPCKLWD(unsigned Opcode) {
1739 switch (Opcode) {
1740 case MMX_PUNPCKLWDrm:
1741 case MMX_PUNPCKLWDrr:
1742 case PUNPCKLWDrm:
1743 case PUNPCKLWDrr:
1744 return true;
1745 }
1746 return false;
1747}
1748
1749bool isPUNPCKLQDQ(unsigned Opcode) {
1750 switch (Opcode) {
1751 case PUNPCKLQDQrm:
1752 case PUNPCKLQDQrr:
1753 return true;
1754 }
1755 return false;
1756}
1757
1758bool isRDFSBASE(unsigned Opcode) {
1759 switch (Opcode) {
1760 case RDFSBASE:
1761 case RDFSBASE64:
1762 return true;
1763 }
1764 return false;
1765}
1766
1767bool isVPCMOV(unsigned Opcode) {
1768 switch (Opcode) {
1769 case VPCMOVYrmr:
1770 case VPCMOVYrrm:
1771 case VPCMOVYrrr:
1772 case VPCMOVYrrr_REV:
1773 case VPCMOVrmr:
1774 case VPCMOVrrm:
1775 case VPCMOVrrr:
1776 case VPCMOVrrr_REV:
1777 return true;
1778 }
1779 return false;
1780}
1781
1782bool isVDIVSD(unsigned Opcode) {
1783 switch (Opcode) {
1784 case VDIVSDZrm_Int:
1785 case VDIVSDZrm_Intk:
1786 case VDIVSDZrm_Intkz:
1787 case VDIVSDZrr_Int:
1788 case VDIVSDZrr_Intk:
1789 case VDIVSDZrr_Intkz:
1790 case VDIVSDZrrb_Int:
1791 case VDIVSDZrrb_Intk:
1792 case VDIVSDZrrb_Intkz:
1793 case VDIVSDrm_Int:
1794 case VDIVSDrr_Int:
1795 return true;
1796 }
1797 return false;
1798}
1799
1800bool isVPEXTRW(unsigned Opcode) {
1801 switch (Opcode) {
1802 case VPEXTRWZmr:
1803 case VPEXTRWZrr:
1804 case VPEXTRWZrr_REV:
1805 case VPEXTRWmr:
1806 case VPEXTRWrr:
1807 case VPEXTRWrr_REV:
1808 return true;
1809 }
1810 return false;
1811}
1812
1813bool isLODSD(unsigned Opcode) {
1814 return Opcode == LODSL;
1815}
1816
1817bool isVPTESTNMQ(unsigned Opcode) {
1818 switch (Opcode) {
1819 case VPTESTNMQZ128rm:
1820 case VPTESTNMQZ128rmb:
1821 case VPTESTNMQZ128rmbk:
1822 case VPTESTNMQZ128rmk:
1823 case VPTESTNMQZ128rr:
1824 case VPTESTNMQZ128rrk:
1825 case VPTESTNMQZ256rm:
1826 case VPTESTNMQZ256rmb:
1827 case VPTESTNMQZ256rmbk:
1828 case VPTESTNMQZ256rmk:
1829 case VPTESTNMQZ256rr:
1830 case VPTESTNMQZ256rrk:
1831 case VPTESTNMQZrm:
1832 case VPTESTNMQZrmb:
1833 case VPTESTNMQZrmbk:
1834 case VPTESTNMQZrmk:
1835 case VPTESTNMQZrr:
1836 case VPTESTNMQZrrk:
1837 return true;
1838 }
1839 return false;
1840}
1841
1842bool isCVTSS2SD(unsigned Opcode) {
1843 switch (Opcode) {
1844 case CVTSS2SDrm_Int:
1845 case CVTSS2SDrr_Int:
1846 return true;
1847 }
1848 return false;
1849}
1850
1851bool isVGETMANTPD(unsigned Opcode) {
1852 switch (Opcode) {
1853 case VGETMANTPDZ128rmbi:
1854 case VGETMANTPDZ128rmbik:
1855 case VGETMANTPDZ128rmbikz:
1856 case VGETMANTPDZ128rmi:
1857 case VGETMANTPDZ128rmik:
1858 case VGETMANTPDZ128rmikz:
1859 case VGETMANTPDZ128rri:
1860 case VGETMANTPDZ128rrik:
1861 case VGETMANTPDZ128rrikz:
1862 case VGETMANTPDZ256rmbi:
1863 case VGETMANTPDZ256rmbik:
1864 case VGETMANTPDZ256rmbikz:
1865 case VGETMANTPDZ256rmi:
1866 case VGETMANTPDZ256rmik:
1867 case VGETMANTPDZ256rmikz:
1868 case VGETMANTPDZ256rri:
1869 case VGETMANTPDZ256rrik:
1870 case VGETMANTPDZ256rrikz:
1871 case VGETMANTPDZrmbi:
1872 case VGETMANTPDZrmbik:
1873 case VGETMANTPDZrmbikz:
1874 case VGETMANTPDZrmi:
1875 case VGETMANTPDZrmik:
1876 case VGETMANTPDZrmikz:
1877 case VGETMANTPDZrri:
1878 case VGETMANTPDZrrib:
1879 case VGETMANTPDZrribk:
1880 case VGETMANTPDZrribkz:
1881 case VGETMANTPDZrrik:
1882 case VGETMANTPDZrrikz:
1883 return true;
1884 }
1885 return false;
1886}
1887
1888bool isVMOVDQA64(unsigned Opcode) {
1889 switch (Opcode) {
1890 case VMOVDQA64Z128mr:
1891 case VMOVDQA64Z128mrk:
1892 case VMOVDQA64Z128rm:
1893 case VMOVDQA64Z128rmk:
1894 case VMOVDQA64Z128rmkz:
1895 case VMOVDQA64Z128rr:
1896 case VMOVDQA64Z128rr_REV:
1897 case VMOVDQA64Z128rrk:
1898 case VMOVDQA64Z128rrk_REV:
1899 case VMOVDQA64Z128rrkz:
1900 case VMOVDQA64Z128rrkz_REV:
1901 case VMOVDQA64Z256mr:
1902 case VMOVDQA64Z256mrk:
1903 case VMOVDQA64Z256rm:
1904 case VMOVDQA64Z256rmk:
1905 case VMOVDQA64Z256rmkz:
1906 case VMOVDQA64Z256rr:
1907 case VMOVDQA64Z256rr_REV:
1908 case VMOVDQA64Z256rrk:
1909 case VMOVDQA64Z256rrk_REV:
1910 case VMOVDQA64Z256rrkz:
1911 case VMOVDQA64Z256rrkz_REV:
1912 case VMOVDQA64Zmr:
1913 case VMOVDQA64Zmrk:
1914 case VMOVDQA64Zrm:
1915 case VMOVDQA64Zrmk:
1916 case VMOVDQA64Zrmkz:
1917 case VMOVDQA64Zrr:
1918 case VMOVDQA64Zrr_REV:
1919 case VMOVDQA64Zrrk:
1920 case VMOVDQA64Zrrk_REV:
1921 case VMOVDQA64Zrrkz:
1922 case VMOVDQA64Zrrkz_REV:
1923 return true;
1924 }
1925 return false;
1926}
1927
1928bool isINVLPG(unsigned Opcode) {
1929 return Opcode == INVLPG;
1930}
1931
1932bool isVBROADCASTF64X4(unsigned Opcode) {
1933 switch (Opcode) {
1934 case VBROADCASTF64X4rm:
1935 case VBROADCASTF64X4rmk:
1936 case VBROADCASTF64X4rmkz:
1937 return true;
1938 }
1939 return false;
1940}
1941
1942bool isVPERMI2Q(unsigned Opcode) {
1943 switch (Opcode) {
1944 case VPERMI2QZ128rm:
1945 case VPERMI2QZ128rmb:
1946 case VPERMI2QZ128rmbk:
1947 case VPERMI2QZ128rmbkz:
1948 case VPERMI2QZ128rmk:
1949 case VPERMI2QZ128rmkz:
1950 case VPERMI2QZ128rr:
1951 case VPERMI2QZ128rrk:
1952 case VPERMI2QZ128rrkz:
1953 case VPERMI2QZ256rm:
1954 case VPERMI2QZ256rmb:
1955 case VPERMI2QZ256rmbk:
1956 case VPERMI2QZ256rmbkz:
1957 case VPERMI2QZ256rmk:
1958 case VPERMI2QZ256rmkz:
1959 case VPERMI2QZ256rr:
1960 case VPERMI2QZ256rrk:
1961 case VPERMI2QZ256rrkz:
1962 case VPERMI2QZrm:
1963 case VPERMI2QZrmb:
1964 case VPERMI2QZrmbk:
1965 case VPERMI2QZrmbkz:
1966 case VPERMI2QZrmk:
1967 case VPERMI2QZrmkz:
1968 case VPERMI2QZrr:
1969 case VPERMI2QZrrk:
1970 case VPERMI2QZrrkz:
1971 return true;
1972 }
1973 return false;
1974}
1975
1976bool isVPMOVSXBD(unsigned Opcode) {
1977 switch (Opcode) {
1978 case VPMOVSXBDYrm:
1979 case VPMOVSXBDYrr:
1980 case VPMOVSXBDZ128rm:
1981 case VPMOVSXBDZ128rmk:
1982 case VPMOVSXBDZ128rmkz:
1983 case VPMOVSXBDZ128rr:
1984 case VPMOVSXBDZ128rrk:
1985 case VPMOVSXBDZ128rrkz:
1986 case VPMOVSXBDZ256rm:
1987 case VPMOVSXBDZ256rmk:
1988 case VPMOVSXBDZ256rmkz:
1989 case VPMOVSXBDZ256rr:
1990 case VPMOVSXBDZ256rrk:
1991 case VPMOVSXBDZ256rrkz:
1992 case VPMOVSXBDZrm:
1993 case VPMOVSXBDZrmk:
1994 case VPMOVSXBDZrmkz:
1995 case VPMOVSXBDZrr:
1996 case VPMOVSXBDZrrk:
1997 case VPMOVSXBDZrrkz:
1998 case VPMOVSXBDrm:
1999 case VPMOVSXBDrr:
2000 return true;
2001 }
2002 return false;
2003}
2004
2005bool isVFMSUB132SS(unsigned Opcode) {
2006 switch (Opcode) {
2007 case VFMSUB132SSZm_Int:
2008 case VFMSUB132SSZm_Intk:
2009 case VFMSUB132SSZm_Intkz:
2010 case VFMSUB132SSZr_Int:
2011 case VFMSUB132SSZr_Intk:
2012 case VFMSUB132SSZr_Intkz:
2013 case VFMSUB132SSZrb_Int:
2014 case VFMSUB132SSZrb_Intk:
2015 case VFMSUB132SSZrb_Intkz:
2016 case VFMSUB132SSm_Int:
2017 case VFMSUB132SSr_Int:
2018 return true;
2019 }
2020 return false;
2021}
2022
2023bool isVPMOVUSDW(unsigned Opcode) {
2024 switch (Opcode) {
2025 case VPMOVUSDWZ128mr:
2026 case VPMOVUSDWZ128mrk:
2027 case VPMOVUSDWZ128rr:
2028 case VPMOVUSDWZ128rrk:
2029 case VPMOVUSDWZ128rrkz:
2030 case VPMOVUSDWZ256mr:
2031 case VPMOVUSDWZ256mrk:
2032 case VPMOVUSDWZ256rr:
2033 case VPMOVUSDWZ256rrk:
2034 case VPMOVUSDWZ256rrkz:
2035 case VPMOVUSDWZmr:
2036 case VPMOVUSDWZmrk:
2037 case VPMOVUSDWZrr:
2038 case VPMOVUSDWZrrk:
2039 case VPMOVUSDWZrrkz:
2040 return true;
2041 }
2042 return false;
2043}
2044
2045bool isAAD(unsigned Opcode) {
2046 return Opcode == AAD8i8;
2047}
2048
2049bool isIDIV(unsigned Opcode) {
2050 switch (Opcode) {
2051 case IDIV16m:
2052 case IDIV16m_EVEX:
2053 case IDIV16m_NF:
2054 case IDIV16r:
2055 case IDIV16r_EVEX:
2056 case IDIV16r_NF:
2057 case IDIV32m:
2058 case IDIV32m_EVEX:
2059 case IDIV32m_NF:
2060 case IDIV32r:
2061 case IDIV32r_EVEX:
2062 case IDIV32r_NF:
2063 case IDIV64m:
2064 case IDIV64m_EVEX:
2065 case IDIV64m_NF:
2066 case IDIV64r:
2067 case IDIV64r_EVEX:
2068 case IDIV64r_NF:
2069 case IDIV8m:
2070 case IDIV8m_EVEX:
2071 case IDIV8m_NF:
2072 case IDIV8r:
2073 case IDIV8r_EVEX:
2074 case IDIV8r_NF:
2075 return true;
2076 }
2077 return false;
2078}
2079
2080bool isCVTTPS2DQ(unsigned Opcode) {
2081 switch (Opcode) {
2082 case CVTTPS2DQrm:
2083 case CVTTPS2DQrr:
2084 return true;
2085 }
2086 return false;
2087}
2088
2089bool isVBROADCASTF32X8(unsigned Opcode) {
2090 switch (Opcode) {
2091 case VBROADCASTF32X8rm:
2092 case VBROADCASTF32X8rmk:
2093 case VBROADCASTF32X8rmkz:
2094 return true;
2095 }
2096 return false;
2097}
2098
2099bool isVFMSUBSS(unsigned Opcode) {
2100 switch (Opcode) {
2101 case VFMSUBSS4mr:
2102 case VFMSUBSS4rm:
2103 case VFMSUBSS4rr:
2104 case VFMSUBSS4rr_REV:
2105 return true;
2106 }
2107 return false;
2108}
2109
2110bool isEMMS(unsigned Opcode) {
2111 return Opcode == MMX_EMMS;
2112}
2113
2114bool isVPDPBSUD(unsigned Opcode) {
2115 switch (Opcode) {
2116 case VPDPBSUDYrm:
2117 case VPDPBSUDYrr:
2118 case VPDPBSUDrm:
2119 case VPDPBSUDrr:
2120 return true;
2121 }
2122 return false;
2123}
2124
2125bool isPMOVSXWQ(unsigned Opcode) {
2126 switch (Opcode) {
2127 case PMOVSXWQrm:
2128 case PMOVSXWQrr:
2129 return true;
2130 }
2131 return false;
2132}
2133
2134bool isPSRLW(unsigned Opcode) {
2135 switch (Opcode) {
2136 case MMX_PSRLWri:
2137 case MMX_PSRLWrm:
2138 case MMX_PSRLWrr:
2139 case PSRLWri:
2140 case PSRLWrm:
2141 case PSRLWrr:
2142 return true;
2143 }
2144 return false;
2145}
2146
2147bool isMOVNTDQA(unsigned Opcode) {
2148 return Opcode == MOVNTDQArm;
2149}
2150
2151bool isFUCOMPI(unsigned Opcode) {
2152 return Opcode == UCOM_FIPr;
2153}
2154
2155bool isANDNPS(unsigned Opcode) {
2156 switch (Opcode) {
2157 case ANDNPSrm:
2158 case ANDNPSrr:
2159 return true;
2160 }
2161 return false;
2162}
2163
2164bool isVINSERTF64X2(unsigned Opcode) {
2165 switch (Opcode) {
2166 case VINSERTF64x2Z256rm:
2167 case VINSERTF64x2Z256rmk:
2168 case VINSERTF64x2Z256rmkz:
2169 case VINSERTF64x2Z256rr:
2170 case VINSERTF64x2Z256rrk:
2171 case VINSERTF64x2Z256rrkz:
2172 case VINSERTF64x2Zrm:
2173 case VINSERTF64x2Zrmk:
2174 case VINSERTF64x2Zrmkz:
2175 case VINSERTF64x2Zrr:
2176 case VINSERTF64x2Zrrk:
2177 case VINSERTF64x2Zrrkz:
2178 return true;
2179 }
2180 return false;
2181}
2182
2183bool isCLTS(unsigned Opcode) {
2184 return Opcode == CLTS;
2185}
2186
2187bool isSETSSBSY(unsigned Opcode) {
2188 return Opcode == SETSSBSY;
2189}
2190
2191bool isVMULPD(unsigned Opcode) {
2192 switch (Opcode) {
2193 case VMULPDYrm:
2194 case VMULPDYrr:
2195 case VMULPDZ128rm:
2196 case VMULPDZ128rmb:
2197 case VMULPDZ128rmbk:
2198 case VMULPDZ128rmbkz:
2199 case VMULPDZ128rmk:
2200 case VMULPDZ128rmkz:
2201 case VMULPDZ128rr:
2202 case VMULPDZ128rrk:
2203 case VMULPDZ128rrkz:
2204 case VMULPDZ256rm:
2205 case VMULPDZ256rmb:
2206 case VMULPDZ256rmbk:
2207 case VMULPDZ256rmbkz:
2208 case VMULPDZ256rmk:
2209 case VMULPDZ256rmkz:
2210 case VMULPDZ256rr:
2211 case VMULPDZ256rrk:
2212 case VMULPDZ256rrkz:
2213 case VMULPDZrm:
2214 case VMULPDZrmb:
2215 case VMULPDZrmbk:
2216 case VMULPDZrmbkz:
2217 case VMULPDZrmk:
2218 case VMULPDZrmkz:
2219 case VMULPDZrr:
2220 case VMULPDZrrb:
2221 case VMULPDZrrbk:
2222 case VMULPDZrrbkz:
2223 case VMULPDZrrk:
2224 case VMULPDZrrkz:
2225 case VMULPDrm:
2226 case VMULPDrr:
2227 return true;
2228 }
2229 return false;
2230}
2231
2232bool isVFMADDSUB132PS(unsigned Opcode) {
2233 switch (Opcode) {
2234 case VFMADDSUB132PSYm:
2235 case VFMADDSUB132PSYr:
2236 case VFMADDSUB132PSZ128m:
2237 case VFMADDSUB132PSZ128mb:
2238 case VFMADDSUB132PSZ128mbk:
2239 case VFMADDSUB132PSZ128mbkz:
2240 case VFMADDSUB132PSZ128mk:
2241 case VFMADDSUB132PSZ128mkz:
2242 case VFMADDSUB132PSZ128r:
2243 case VFMADDSUB132PSZ128rk:
2244 case VFMADDSUB132PSZ128rkz:
2245 case VFMADDSUB132PSZ256m:
2246 case VFMADDSUB132PSZ256mb:
2247 case VFMADDSUB132PSZ256mbk:
2248 case VFMADDSUB132PSZ256mbkz:
2249 case VFMADDSUB132PSZ256mk:
2250 case VFMADDSUB132PSZ256mkz:
2251 case VFMADDSUB132PSZ256r:
2252 case VFMADDSUB132PSZ256rk:
2253 case VFMADDSUB132PSZ256rkz:
2254 case VFMADDSUB132PSZm:
2255 case VFMADDSUB132PSZmb:
2256 case VFMADDSUB132PSZmbk:
2257 case VFMADDSUB132PSZmbkz:
2258 case VFMADDSUB132PSZmk:
2259 case VFMADDSUB132PSZmkz:
2260 case VFMADDSUB132PSZr:
2261 case VFMADDSUB132PSZrb:
2262 case VFMADDSUB132PSZrbk:
2263 case VFMADDSUB132PSZrbkz:
2264 case VFMADDSUB132PSZrk:
2265 case VFMADDSUB132PSZrkz:
2266 case VFMADDSUB132PSm:
2267 case VFMADDSUB132PSr:
2268 return true;
2269 }
2270 return false;
2271}
2272
2273bool isVPMADCSWD(unsigned Opcode) {
2274 switch (Opcode) {
2275 case VPMADCSWDrm:
2276 case VPMADCSWDrr:
2277 return true;
2278 }
2279 return false;
2280}
2281
2282bool isVSCATTERPF0DPS(unsigned Opcode) {
2283 return Opcode == VSCATTERPF0DPSm;
2284}
2285
2286bool isXCHG(unsigned Opcode) {
2287 switch (Opcode) {
2288 case XCHG16ar:
2289 case XCHG16rm:
2290 case XCHG16rr:
2291 case XCHG32ar:
2292 case XCHG32rm:
2293 case XCHG32rr:
2294 case XCHG64ar:
2295 case XCHG64rm:
2296 case XCHG64rr:
2297 case XCHG8rm:
2298 case XCHG8rr:
2299 return true;
2300 }
2301 return false;
2302}
2303
2304bool isVGATHERPF1QPS(unsigned Opcode) {
2305 return Opcode == VGATHERPF1QPSm;
2306}
2307
2308bool isVCVTNEPS2BF16(unsigned Opcode) {
2309 switch (Opcode) {
2310 case VCVTNEPS2BF16Yrm:
2311 case VCVTNEPS2BF16Yrr:
2312 case VCVTNEPS2BF16Z128rm:
2313 case VCVTNEPS2BF16Z128rmb:
2314 case VCVTNEPS2BF16Z128rmbk:
2315 case VCVTNEPS2BF16Z128rmbkz:
2316 case VCVTNEPS2BF16Z128rmk:
2317 case VCVTNEPS2BF16Z128rmkz:
2318 case VCVTNEPS2BF16Z128rr:
2319 case VCVTNEPS2BF16Z128rrk:
2320 case VCVTNEPS2BF16Z128rrkz:
2321 case VCVTNEPS2BF16Z256rm:
2322 case VCVTNEPS2BF16Z256rmb:
2323 case VCVTNEPS2BF16Z256rmbk:
2324 case VCVTNEPS2BF16Z256rmbkz:
2325 case VCVTNEPS2BF16Z256rmk:
2326 case VCVTNEPS2BF16Z256rmkz:
2327 case VCVTNEPS2BF16Z256rr:
2328 case VCVTNEPS2BF16Z256rrk:
2329 case VCVTNEPS2BF16Z256rrkz:
2330 case VCVTNEPS2BF16Zrm:
2331 case VCVTNEPS2BF16Zrmb:
2332 case VCVTNEPS2BF16Zrmbk:
2333 case VCVTNEPS2BF16Zrmbkz:
2334 case VCVTNEPS2BF16Zrmk:
2335 case VCVTNEPS2BF16Zrmkz:
2336 case VCVTNEPS2BF16Zrr:
2337 case VCVTNEPS2BF16Zrrk:
2338 case VCVTNEPS2BF16Zrrkz:
2339 case VCVTNEPS2BF16rm:
2340 case VCVTNEPS2BF16rr:
2341 return true;
2342 }
2343 return false;
2344}
2345
2346bool isVFMADDSS(unsigned Opcode) {
2347 switch (Opcode) {
2348 case VFMADDSS4mr:
2349 case VFMADDSS4rm:
2350 case VFMADDSS4rr:
2351 case VFMADDSS4rr_REV:
2352 return true;
2353 }
2354 return false;
2355}
2356
2357bool isINTO(unsigned Opcode) {
2358 return Opcode == INTO;
2359}
2360
2361bool isANDPD(unsigned Opcode) {
2362 switch (Opcode) {
2363 case ANDPDrm:
2364 case ANDPDrr:
2365 return true;
2366 }
2367 return false;
2368}
2369
2370bool isSEAMCALL(unsigned Opcode) {
2371 return Opcode == SEAMCALL;
2372}
2373
2374bool isVPDPBSSDS(unsigned Opcode) {
2375 switch (Opcode) {
2376 case VPDPBSSDSYrm:
2377 case VPDPBSSDSYrr:
2378 case VPDPBSSDSrm:
2379 case VPDPBSSDSrr:
2380 return true;
2381 }
2382 return false;
2383}
2384
2385bool isUNPCKHPS(unsigned Opcode) {
2386 switch (Opcode) {
2387 case UNPCKHPSrm:
2388 case UNPCKHPSrr:
2389 return true;
2390 }
2391 return false;
2392}
2393
2394bool isSETZUCC(unsigned Opcode) {
2395 switch (Opcode) {
2396 case SETZUCCm:
2397 case SETZUCCr:
2398 return true;
2399 }
2400 return false;
2401}
2402
2403bool isSHUFPD(unsigned Opcode) {
2404 switch (Opcode) {
2405 case SHUFPDrmi:
2406 case SHUFPDrri:
2407 return true;
2408 }
2409 return false;
2410}
2411
2412bool isFCMOVNB(unsigned Opcode) {
2413 return Opcode == CMOVNB_F;
2414}
2415
2416bool isCVTTSS2SI(unsigned Opcode) {
2417 switch (Opcode) {
2418 case CVTTSS2SI64rm_Int:
2419 case CVTTSS2SI64rr_Int:
2420 case CVTTSS2SIrm_Int:
2421 case CVTTSS2SIrr_Int:
2422 return true;
2423 }
2424 return false;
2425}
2426
2427bool isEXTRQ(unsigned Opcode) {
2428 switch (Opcode) {
2429 case EXTRQ:
2430 case EXTRQI:
2431 return true;
2432 }
2433 return false;
2434}
2435
2436bool isSHLD(unsigned Opcode) {
2437 switch (Opcode) {
2438 case SHLD16mrCL:
2439 case SHLD16mrCL_EVEX:
2440 case SHLD16mrCL_ND:
2441 case SHLD16mrCL_NF:
2442 case SHLD16mrCL_NF_ND:
2443 case SHLD16mri8:
2444 case SHLD16mri8_EVEX:
2445 case SHLD16mri8_ND:
2446 case SHLD16mri8_NF:
2447 case SHLD16mri8_NF_ND:
2448 case SHLD16rrCL:
2449 case SHLD16rrCL_EVEX:
2450 case SHLD16rrCL_ND:
2451 case SHLD16rrCL_NF:
2452 case SHLD16rrCL_NF_ND:
2453 case SHLD16rri8:
2454 case SHLD16rri8_EVEX:
2455 case SHLD16rri8_ND:
2456 case SHLD16rri8_NF:
2457 case SHLD16rri8_NF_ND:
2458 case SHLD32mrCL:
2459 case SHLD32mrCL_EVEX:
2460 case SHLD32mrCL_ND:
2461 case SHLD32mrCL_NF:
2462 case SHLD32mrCL_NF_ND:
2463 case SHLD32mri8:
2464 case SHLD32mri8_EVEX:
2465 case SHLD32mri8_ND:
2466 case SHLD32mri8_NF:
2467 case SHLD32mri8_NF_ND:
2468 case SHLD32rrCL:
2469 case SHLD32rrCL_EVEX:
2470 case SHLD32rrCL_ND:
2471 case SHLD32rrCL_NF:
2472 case SHLD32rrCL_NF_ND:
2473 case SHLD32rri8:
2474 case SHLD32rri8_EVEX:
2475 case SHLD32rri8_ND:
2476 case SHLD32rri8_NF:
2477 case SHLD32rri8_NF_ND:
2478 case SHLD64mrCL:
2479 case SHLD64mrCL_EVEX:
2480 case SHLD64mrCL_ND:
2481 case SHLD64mrCL_NF:
2482 case SHLD64mrCL_NF_ND:
2483 case SHLD64mri8:
2484 case SHLD64mri8_EVEX:
2485 case SHLD64mri8_ND:
2486 case SHLD64mri8_NF:
2487 case SHLD64mri8_NF_ND:
2488 case SHLD64rrCL:
2489 case SHLD64rrCL_EVEX:
2490 case SHLD64rrCL_ND:
2491 case SHLD64rrCL_NF:
2492 case SHLD64rrCL_NF_ND:
2493 case SHLD64rri8:
2494 case SHLD64rri8_EVEX:
2495 case SHLD64rri8_ND:
2496 case SHLD64rri8_NF:
2497 case SHLD64rri8_NF_ND:
2498 return true;
2499 }
2500 return false;
2501}
2502
2503bool isVBROADCASTSS(unsigned Opcode) {
2504 switch (Opcode) {
2505 case VBROADCASTSSYrm:
2506 case VBROADCASTSSYrr:
2507 case VBROADCASTSSZ128rm:
2508 case VBROADCASTSSZ128rmk:
2509 case VBROADCASTSSZ128rmkz:
2510 case VBROADCASTSSZ128rr:
2511 case VBROADCASTSSZ128rrk:
2512 case VBROADCASTSSZ128rrkz:
2513 case VBROADCASTSSZ256rm:
2514 case VBROADCASTSSZ256rmk:
2515 case VBROADCASTSSZ256rmkz:
2516 case VBROADCASTSSZ256rr:
2517 case VBROADCASTSSZ256rrk:
2518 case VBROADCASTSSZ256rrkz:
2519 case VBROADCASTSSZrm:
2520 case VBROADCASTSSZrmk:
2521 case VBROADCASTSSZrmkz:
2522 case VBROADCASTSSZrr:
2523 case VBROADCASTSSZrrk:
2524 case VBROADCASTSSZrrkz:
2525 case VBROADCASTSSrm:
2526 case VBROADCASTSSrr:
2527 return true;
2528 }
2529 return false;
2530}
2531
2532bool isCLUI(unsigned Opcode) {
2533 return Opcode == CLUI;
2534}
2535
2536bool isVINSERTI128(unsigned Opcode) {
2537 switch (Opcode) {
2538 case VINSERTI128rm:
2539 case VINSERTI128rr:
2540 return true;
2541 }
2542 return false;
2543}
2544
2545bool isVBLENDPD(unsigned Opcode) {
2546 switch (Opcode) {
2547 case VBLENDPDYrmi:
2548 case VBLENDPDYrri:
2549 case VBLENDPDrmi:
2550 case VBLENDPDrri:
2551 return true;
2552 }
2553 return false;
2554}
2555
2556bool isVPSHLDW(unsigned Opcode) {
2557 switch (Opcode) {
2558 case VPSHLDWZ128rmi:
2559 case VPSHLDWZ128rmik:
2560 case VPSHLDWZ128rmikz:
2561 case VPSHLDWZ128rri:
2562 case VPSHLDWZ128rrik:
2563 case VPSHLDWZ128rrikz:
2564 case VPSHLDWZ256rmi:
2565 case VPSHLDWZ256rmik:
2566 case VPSHLDWZ256rmikz:
2567 case VPSHLDWZ256rri:
2568 case VPSHLDWZ256rrik:
2569 case VPSHLDWZ256rrikz:
2570 case VPSHLDWZrmi:
2571 case VPSHLDWZrmik:
2572 case VPSHLDWZrmikz:
2573 case VPSHLDWZrri:
2574 case VPSHLDWZrrik:
2575 case VPSHLDWZrrikz:
2576 return true;
2577 }
2578 return false;
2579}
2580
2581bool isVCVTNEEPH2PS(unsigned Opcode) {
2582 switch (Opcode) {
2583 case VCVTNEEPH2PSYrm:
2584 case VCVTNEEPH2PSrm:
2585 return true;
2586 }
2587 return false;
2588}
2589
2590bool isVCVTTSD2SI(unsigned Opcode) {
2591 switch (Opcode) {
2592 case VCVTTSD2SI64Zrm_Int:
2593 case VCVTTSD2SI64Zrr_Int:
2594 case VCVTTSD2SI64Zrrb_Int:
2595 case VCVTTSD2SI64rm_Int:
2596 case VCVTTSD2SI64rr_Int:
2597 case VCVTTSD2SIZrm_Int:
2598 case VCVTTSD2SIZrr_Int:
2599 case VCVTTSD2SIZrrb_Int:
2600 case VCVTTSD2SIrm_Int:
2601 case VCVTTSD2SIrr_Int:
2602 return true;
2603 }
2604 return false;
2605}
2606
2607bool isVSM4KEY4(unsigned Opcode) {
2608 switch (Opcode) {
2609 case VSM4KEY4Yrm:
2610 case VSM4KEY4Yrr:
2611 case VSM4KEY4rm:
2612 case VSM4KEY4rr:
2613 return true;
2614 }
2615 return false;
2616}
2617
2618bool isWRMSRNS(unsigned Opcode) {
2619 return Opcode == WRMSRNS;
2620}
2621
2622bool isCMPSB(unsigned Opcode) {
2623 return Opcode == CMPSB;
2624}
2625
2626bool isMULSS(unsigned Opcode) {
2627 switch (Opcode) {
2628 case MULSSrm_Int:
2629 case MULSSrr_Int:
2630 return true;
2631 }
2632 return false;
2633}
2634
2635bool isVMRUN(unsigned Opcode) {
2636 switch (Opcode) {
2637 case VMRUN32:
2638 case VMRUN64:
2639 return true;
2640 }
2641 return false;
2642}
2643
2644bool isVPSRLVD(unsigned Opcode) {
2645 switch (Opcode) {
2646 case VPSRLVDYrm:
2647 case VPSRLVDYrr:
2648 case VPSRLVDZ128rm:
2649 case VPSRLVDZ128rmb:
2650 case VPSRLVDZ128rmbk:
2651 case VPSRLVDZ128rmbkz:
2652 case VPSRLVDZ128rmk:
2653 case VPSRLVDZ128rmkz:
2654 case VPSRLVDZ128rr:
2655 case VPSRLVDZ128rrk:
2656 case VPSRLVDZ128rrkz:
2657 case VPSRLVDZ256rm:
2658 case VPSRLVDZ256rmb:
2659 case VPSRLVDZ256rmbk:
2660 case VPSRLVDZ256rmbkz:
2661 case VPSRLVDZ256rmk:
2662 case VPSRLVDZ256rmkz:
2663 case VPSRLVDZ256rr:
2664 case VPSRLVDZ256rrk:
2665 case VPSRLVDZ256rrkz:
2666 case VPSRLVDZrm:
2667 case VPSRLVDZrmb:
2668 case VPSRLVDZrmbk:
2669 case VPSRLVDZrmbkz:
2670 case VPSRLVDZrmk:
2671 case VPSRLVDZrmkz:
2672 case VPSRLVDZrr:
2673 case VPSRLVDZrrk:
2674 case VPSRLVDZrrkz:
2675 case VPSRLVDrm:
2676 case VPSRLVDrr:
2677 return true;
2678 }
2679 return false;
2680}
2681
2682bool isLEAVE(unsigned Opcode) {
2683 switch (Opcode) {
2684 case LEAVE:
2685 case LEAVE64:
2686 return true;
2687 }
2688 return false;
2689}
2690
2691bool isVGETMANTPS(unsigned Opcode) {
2692 switch (Opcode) {
2693 case VGETMANTPSZ128rmbi:
2694 case VGETMANTPSZ128rmbik:
2695 case VGETMANTPSZ128rmbikz:
2696 case VGETMANTPSZ128rmi:
2697 case VGETMANTPSZ128rmik:
2698 case VGETMANTPSZ128rmikz:
2699 case VGETMANTPSZ128rri:
2700 case VGETMANTPSZ128rrik:
2701 case VGETMANTPSZ128rrikz:
2702 case VGETMANTPSZ256rmbi:
2703 case VGETMANTPSZ256rmbik:
2704 case VGETMANTPSZ256rmbikz:
2705 case VGETMANTPSZ256rmi:
2706 case VGETMANTPSZ256rmik:
2707 case VGETMANTPSZ256rmikz:
2708 case VGETMANTPSZ256rri:
2709 case VGETMANTPSZ256rrik:
2710 case VGETMANTPSZ256rrikz:
2711 case VGETMANTPSZrmbi:
2712 case VGETMANTPSZrmbik:
2713 case VGETMANTPSZrmbikz:
2714 case VGETMANTPSZrmi:
2715 case VGETMANTPSZrmik:
2716 case VGETMANTPSZrmikz:
2717 case VGETMANTPSZrri:
2718 case VGETMANTPSZrrib:
2719 case VGETMANTPSZrribk:
2720 case VGETMANTPSZrribkz:
2721 case VGETMANTPSZrrik:
2722 case VGETMANTPSZrrikz:
2723 return true;
2724 }
2725 return false;
2726}
2727
2728bool isXSHA256(unsigned Opcode) {
2729 return Opcode == XSHA256;
2730}
2731
2732bool isBOUND(unsigned Opcode) {
2733 switch (Opcode) {
2734 case BOUNDS16rm:
2735 case BOUNDS32rm:
2736 return true;
2737 }
2738 return false;
2739}
2740
2741bool isSFENCE(unsigned Opcode) {
2742 return Opcode == SFENCE;
2743}
2744
2745bool isVPHADDD(unsigned Opcode) {
2746 switch (Opcode) {
2747 case VPHADDDYrm:
2748 case VPHADDDYrr:
2749 case VPHADDDrm:
2750 case VPHADDDrr:
2751 return true;
2752 }
2753 return false;
2754}
2755
2756bool isADOX(unsigned Opcode) {
2757 switch (Opcode) {
2758 case ADOX32rm:
2759 case ADOX32rm_EVEX:
2760 case ADOX32rm_ND:
2761 case ADOX32rr:
2762 case ADOX32rr_EVEX:
2763 case ADOX32rr_ND:
2764 case ADOX64rm:
2765 case ADOX64rm_EVEX:
2766 case ADOX64rm_ND:
2767 case ADOX64rr:
2768 case ADOX64rr_EVEX:
2769 case ADOX64rr_ND:
2770 return true;
2771 }
2772 return false;
2773}
2774
2775bool isVPSLLQ(unsigned Opcode) {
2776 switch (Opcode) {
2777 case VPSLLQYri:
2778 case VPSLLQYrm:
2779 case VPSLLQYrr:
2780 case VPSLLQZ128mbi:
2781 case VPSLLQZ128mbik:
2782 case VPSLLQZ128mbikz:
2783 case VPSLLQZ128mi:
2784 case VPSLLQZ128mik:
2785 case VPSLLQZ128mikz:
2786 case VPSLLQZ128ri:
2787 case VPSLLQZ128rik:
2788 case VPSLLQZ128rikz:
2789 case VPSLLQZ128rm:
2790 case VPSLLQZ128rmk:
2791 case VPSLLQZ128rmkz:
2792 case VPSLLQZ128rr:
2793 case VPSLLQZ128rrk:
2794 case VPSLLQZ128rrkz:
2795 case VPSLLQZ256mbi:
2796 case VPSLLQZ256mbik:
2797 case VPSLLQZ256mbikz:
2798 case VPSLLQZ256mi:
2799 case VPSLLQZ256mik:
2800 case VPSLLQZ256mikz:
2801 case VPSLLQZ256ri:
2802 case VPSLLQZ256rik:
2803 case VPSLLQZ256rikz:
2804 case VPSLLQZ256rm:
2805 case VPSLLQZ256rmk:
2806 case VPSLLQZ256rmkz:
2807 case VPSLLQZ256rr:
2808 case VPSLLQZ256rrk:
2809 case VPSLLQZ256rrkz:
2810 case VPSLLQZmbi:
2811 case VPSLLQZmbik:
2812 case VPSLLQZmbikz:
2813 case VPSLLQZmi:
2814 case VPSLLQZmik:
2815 case VPSLLQZmikz:
2816 case VPSLLQZri:
2817 case VPSLLQZrik:
2818 case VPSLLQZrikz:
2819 case VPSLLQZrm:
2820 case VPSLLQZrmk:
2821 case VPSLLQZrmkz:
2822 case VPSLLQZrr:
2823 case VPSLLQZrrk:
2824 case VPSLLQZrrkz:
2825 case VPSLLQri:
2826 case VPSLLQrm:
2827 case VPSLLQrr:
2828 return true;
2829 }
2830 return false;
2831}
2832
2833bool isPFRSQIT1(unsigned Opcode) {
2834 switch (Opcode) {
2835 case PFRSQIT1rm:
2836 case PFRSQIT1rr:
2837 return true;
2838 }
2839 return false;
2840}
2841
2842bool isCLAC(unsigned Opcode) {
2843 return Opcode == CLAC;
2844}
2845
2846bool isKNOTW(unsigned Opcode) {
2847 return Opcode == KNOTWrr;
2848}
2849
2850bool isVCVTPH2PD(unsigned Opcode) {
2851 switch (Opcode) {
2852 case VCVTPH2PDZ128rm:
2853 case VCVTPH2PDZ128rmb:
2854 case VCVTPH2PDZ128rmbk:
2855 case VCVTPH2PDZ128rmbkz:
2856 case VCVTPH2PDZ128rmk:
2857 case VCVTPH2PDZ128rmkz:
2858 case VCVTPH2PDZ128rr:
2859 case VCVTPH2PDZ128rrk:
2860 case VCVTPH2PDZ128rrkz:
2861 case VCVTPH2PDZ256rm:
2862 case VCVTPH2PDZ256rmb:
2863 case VCVTPH2PDZ256rmbk:
2864 case VCVTPH2PDZ256rmbkz:
2865 case VCVTPH2PDZ256rmk:
2866 case VCVTPH2PDZ256rmkz:
2867 case VCVTPH2PDZ256rr:
2868 case VCVTPH2PDZ256rrk:
2869 case VCVTPH2PDZ256rrkz:
2870 case VCVTPH2PDZrm:
2871 case VCVTPH2PDZrmb:
2872 case VCVTPH2PDZrmbk:
2873 case VCVTPH2PDZrmbkz:
2874 case VCVTPH2PDZrmk:
2875 case VCVTPH2PDZrmkz:
2876 case VCVTPH2PDZrr:
2877 case VCVTPH2PDZrrb:
2878 case VCVTPH2PDZrrbk:
2879 case VCVTPH2PDZrrbkz:
2880 case VCVTPH2PDZrrk:
2881 case VCVTPH2PDZrrkz:
2882 return true;
2883 }
2884 return false;
2885}
2886
2887bool isVAESENC(unsigned Opcode) {
2888 switch (Opcode) {
2889 case VAESENCYrm:
2890 case VAESENCYrr:
2891 case VAESENCZ128rm:
2892 case VAESENCZ128rr:
2893 case VAESENCZ256rm:
2894 case VAESENCZ256rr:
2895 case VAESENCZrm:
2896 case VAESENCZrr:
2897 case VAESENCrm:
2898 case VAESENCrr:
2899 return true;
2900 }
2901 return false;
2902}
2903
2904bool isMOVNTI(unsigned Opcode) {
2905 switch (Opcode) {
2906 case MOVNTI_64mr:
2907 case MOVNTImr:
2908 return true;
2909 }
2910 return false;
2911}
2912
2913bool isFXCH(unsigned Opcode) {
2914 return Opcode == XCH_F;
2915}
2916
2917bool isPOPP(unsigned Opcode) {
2918 return Opcode == POPP64r;
2919}
2920
2921bool isVPBLENDMD(unsigned Opcode) {
2922 switch (Opcode) {
2923 case VPBLENDMDZ128rm:
2924 case VPBLENDMDZ128rmb:
2925 case VPBLENDMDZ128rmbk:
2926 case VPBLENDMDZ128rmbkz:
2927 case VPBLENDMDZ128rmk:
2928 case VPBLENDMDZ128rmkz:
2929 case VPBLENDMDZ128rr:
2930 case VPBLENDMDZ128rrk:
2931 case VPBLENDMDZ128rrkz:
2932 case VPBLENDMDZ256rm:
2933 case VPBLENDMDZ256rmb:
2934 case VPBLENDMDZ256rmbk:
2935 case VPBLENDMDZ256rmbkz:
2936 case VPBLENDMDZ256rmk:
2937 case VPBLENDMDZ256rmkz:
2938 case VPBLENDMDZ256rr:
2939 case VPBLENDMDZ256rrk:
2940 case VPBLENDMDZ256rrkz:
2941 case VPBLENDMDZrm:
2942 case VPBLENDMDZrmb:
2943 case VPBLENDMDZrmbk:
2944 case VPBLENDMDZrmbkz:
2945 case VPBLENDMDZrmk:
2946 case VPBLENDMDZrmkz:
2947 case VPBLENDMDZrr:
2948 case VPBLENDMDZrrk:
2949 case VPBLENDMDZrrkz:
2950 return true;
2951 }
2952 return false;
2953}
2954
2955bool isFSINCOS(unsigned Opcode) {
2956 return Opcode == FSINCOS;
2957}
2958
2959bool isVPMULLW(unsigned Opcode) {
2960 switch (Opcode) {
2961 case VPMULLWYrm:
2962 case VPMULLWYrr:
2963 case VPMULLWZ128rm:
2964 case VPMULLWZ128rmk:
2965 case VPMULLWZ128rmkz:
2966 case VPMULLWZ128rr:
2967 case VPMULLWZ128rrk:
2968 case VPMULLWZ128rrkz:
2969 case VPMULLWZ256rm:
2970 case VPMULLWZ256rmk:
2971 case VPMULLWZ256rmkz:
2972 case VPMULLWZ256rr:
2973 case VPMULLWZ256rrk:
2974 case VPMULLWZ256rrkz:
2975 case VPMULLWZrm:
2976 case VPMULLWZrmk:
2977 case VPMULLWZrmkz:
2978 case VPMULLWZrr:
2979 case VPMULLWZrrk:
2980 case VPMULLWZrrkz:
2981 case VPMULLWrm:
2982 case VPMULLWrr:
2983 return true;
2984 }
2985 return false;
2986}
2987
2988bool isVPMOVSXBW(unsigned Opcode) {
2989 switch (Opcode) {
2990 case VPMOVSXBWYrm:
2991 case VPMOVSXBWYrr:
2992 case VPMOVSXBWZ128rm:
2993 case VPMOVSXBWZ128rmk:
2994 case VPMOVSXBWZ128rmkz:
2995 case VPMOVSXBWZ128rr:
2996 case VPMOVSXBWZ128rrk:
2997 case VPMOVSXBWZ128rrkz:
2998 case VPMOVSXBWZ256rm:
2999 case VPMOVSXBWZ256rmk:
3000 case VPMOVSXBWZ256rmkz:
3001 case VPMOVSXBWZ256rr:
3002 case VPMOVSXBWZ256rrk:
3003 case VPMOVSXBWZ256rrkz:
3004 case VPMOVSXBWZrm:
3005 case VPMOVSXBWZrmk:
3006 case VPMOVSXBWZrmkz:
3007 case VPMOVSXBWZrr:
3008 case VPMOVSXBWZrrk:
3009 case VPMOVSXBWZrrkz:
3010 case VPMOVSXBWrm:
3011 case VPMOVSXBWrr:
3012 return true;
3013 }
3014 return false;
3015}
3016
3017bool isSTC(unsigned Opcode) {
3018 return Opcode == STC;
3019}
3020
3021bool isVPINSRB(unsigned Opcode) {
3022 switch (Opcode) {
3023 case VPINSRBZrm:
3024 case VPINSRBZrr:
3025 case VPINSRBrm:
3026 case VPINSRBrr:
3027 return true;
3028 }
3029 return false;
3030}
3031
3032bool isLWPVAL(unsigned Opcode) {
3033 switch (Opcode) {
3034 case LWPVAL32rmi:
3035 case LWPVAL32rri:
3036 case LWPVAL64rmi:
3037 case LWPVAL64rri:
3038 return true;
3039 }
3040 return false;
3041}
3042
3043bool isKXORB(unsigned Opcode) {
3044 return Opcode == KXORBrr;
3045}
3046
3047bool isRSTORSSP(unsigned Opcode) {
3048 return Opcode == RSTORSSP;
3049}
3050
3051bool isVPRORQ(unsigned Opcode) {
3052 switch (Opcode) {
3053 case VPRORQZ128mbi:
3054 case VPRORQZ128mbik:
3055 case VPRORQZ128mbikz:
3056 case VPRORQZ128mi:
3057 case VPRORQZ128mik:
3058 case VPRORQZ128mikz:
3059 case VPRORQZ128ri:
3060 case VPRORQZ128rik:
3061 case VPRORQZ128rikz:
3062 case VPRORQZ256mbi:
3063 case VPRORQZ256mbik:
3064 case VPRORQZ256mbikz:
3065 case VPRORQZ256mi:
3066 case VPRORQZ256mik:
3067 case VPRORQZ256mikz:
3068 case VPRORQZ256ri:
3069 case VPRORQZ256rik:
3070 case VPRORQZ256rikz:
3071 case VPRORQZmbi:
3072 case VPRORQZmbik:
3073 case VPRORQZmbikz:
3074 case VPRORQZmi:
3075 case VPRORQZmik:
3076 case VPRORQZmikz:
3077 case VPRORQZri:
3078 case VPRORQZrik:
3079 case VPRORQZrikz:
3080 return true;
3081 }
3082 return false;
3083}
3084
3085bool isVSM3MSG1(unsigned Opcode) {
3086 switch (Opcode) {
3087 case VSM3MSG1rm:
3088 case VSM3MSG1rr:
3089 return true;
3090 }
3091 return false;
3092}
3093
3094bool isFICOM(unsigned Opcode) {
3095 switch (Opcode) {
3096 case FICOM16m:
3097 case FICOM32m:
3098 return true;
3099 }
3100 return false;
3101}
3102
3103bool isMAXPS(unsigned Opcode) {
3104 switch (Opcode) {
3105 case MAXPSrm:
3106 case MAXPSrr:
3107 return true;
3108 }
3109 return false;
3110}
3111
3112bool isFNCLEX(unsigned Opcode) {
3113 return Opcode == FNCLEX;
3114}
3115
3116bool isVMOVMSKPS(unsigned Opcode) {
3117 switch (Opcode) {
3118 case VMOVMSKPSYrr:
3119 case VMOVMSKPSrr:
3120 return true;
3121 }
3122 return false;
3123}
3124
3125bool isVPMOVDB(unsigned Opcode) {
3126 switch (Opcode) {
3127 case VPMOVDBZ128mr:
3128 case VPMOVDBZ128mrk:
3129 case VPMOVDBZ128rr:
3130 case VPMOVDBZ128rrk:
3131 case VPMOVDBZ128rrkz:
3132 case VPMOVDBZ256mr:
3133 case VPMOVDBZ256mrk:
3134 case VPMOVDBZ256rr:
3135 case VPMOVDBZ256rrk:
3136 case VPMOVDBZ256rrkz:
3137 case VPMOVDBZmr:
3138 case VPMOVDBZmrk:
3139 case VPMOVDBZrr:
3140 case VPMOVDBZrrk:
3141 case VPMOVDBZrrkz:
3142 return true;
3143 }
3144 return false;
3145}
3146
3147bool isLLWPCB(unsigned Opcode) {
3148 switch (Opcode) {
3149 case LLWPCB:
3150 case LLWPCB64:
3151 return true;
3152 }
3153 return false;
3154}
3155
3156bool isVMULSS(unsigned Opcode) {
3157 switch (Opcode) {
3158 case VMULSSZrm_Int:
3159 case VMULSSZrm_Intk:
3160 case VMULSSZrm_Intkz:
3161 case VMULSSZrr_Int:
3162 case VMULSSZrr_Intk:
3163 case VMULSSZrr_Intkz:
3164 case VMULSSZrrb_Int:
3165 case VMULSSZrrb_Intk:
3166 case VMULSSZrrb_Intkz:
3167 case VMULSSrm_Int:
3168 case VMULSSrr_Int:
3169 return true;
3170 }
3171 return false;
3172}
3173
3174bool isAESENCLAST(unsigned Opcode) {
3175 switch (Opcode) {
3176 case AESENCLASTrm:
3177 case AESENCLASTrr:
3178 return true;
3179 }
3180 return false;
3181}
3182
3183bool isVPMAXUB(unsigned Opcode) {
3184 switch (Opcode) {
3185 case VPMAXUBYrm:
3186 case VPMAXUBYrr:
3187 case VPMAXUBZ128rm:
3188 case VPMAXUBZ128rmk:
3189 case VPMAXUBZ128rmkz:
3190 case VPMAXUBZ128rr:
3191 case VPMAXUBZ128rrk:
3192 case VPMAXUBZ128rrkz:
3193 case VPMAXUBZ256rm:
3194 case VPMAXUBZ256rmk:
3195 case VPMAXUBZ256rmkz:
3196 case VPMAXUBZ256rr:
3197 case VPMAXUBZ256rrk:
3198 case VPMAXUBZ256rrkz:
3199 case VPMAXUBZrm:
3200 case VPMAXUBZrmk:
3201 case VPMAXUBZrmkz:
3202 case VPMAXUBZrr:
3203 case VPMAXUBZrrk:
3204 case VPMAXUBZrrkz:
3205 case VPMAXUBrm:
3206 case VPMAXUBrr:
3207 return true;
3208 }
3209 return false;
3210}
3211
3212bool isAAS(unsigned Opcode) {
3213 return Opcode == AAS;
3214}
3215
3216bool isFADD(unsigned Opcode) {
3217 switch (Opcode) {
3218 case ADD_F32m:
3219 case ADD_F64m:
3220 case ADD_FST0r:
3221 case ADD_FrST0:
3222 return true;
3223 }
3224 return false;
3225}
3226
3227bool isJMP(unsigned Opcode) {
3228 switch (Opcode) {
3229 case FARJMP32m:
3230 case JMP16m:
3231 case JMP16r:
3232 case JMP32m:
3233 case JMP32r:
3234 case JMP64m:
3235 case JMP64r:
3236 case JMP_1:
3237 case JMP_2:
3238 case JMP_4:
3239 return true;
3240 }
3241 return false;
3242}
3243
3244bool isXCRYPTECB(unsigned Opcode) {
3245 return Opcode == XCRYPTECB;
3246}
3247
3248bool isPFRCPIT1(unsigned Opcode) {
3249 switch (Opcode) {
3250 case PFRCPIT1rm:
3251 case PFRCPIT1rr:
3252 return true;
3253 }
3254 return false;
3255}
3256
3257bool isPMULHRW(unsigned Opcode) {
3258 switch (Opcode) {
3259 case PMULHRWrm:
3260 case PMULHRWrr:
3261 return true;
3262 }
3263 return false;
3264}
3265
3266bool isVCVTPH2PS(unsigned Opcode) {
3267 switch (Opcode) {
3268 case VCVTPH2PSYrm:
3269 case VCVTPH2PSYrr:
3270 case VCVTPH2PSZ128rm:
3271 case VCVTPH2PSZ128rmk:
3272 case VCVTPH2PSZ128rmkz:
3273 case VCVTPH2PSZ128rr:
3274 case VCVTPH2PSZ128rrk:
3275 case VCVTPH2PSZ128rrkz:
3276 case VCVTPH2PSZ256rm:
3277 case VCVTPH2PSZ256rmk:
3278 case VCVTPH2PSZ256rmkz:
3279 case VCVTPH2PSZ256rr:
3280 case VCVTPH2PSZ256rrk:
3281 case VCVTPH2PSZ256rrkz:
3282 case VCVTPH2PSZrm:
3283 case VCVTPH2PSZrmk:
3284 case VCVTPH2PSZrmkz:
3285 case VCVTPH2PSZrr:
3286 case VCVTPH2PSZrrb:
3287 case VCVTPH2PSZrrbk:
3288 case VCVTPH2PSZrrbkz:
3289 case VCVTPH2PSZrrk:
3290 case VCVTPH2PSZrrkz:
3291 case VCVTPH2PSrm:
3292 case VCVTPH2PSrr:
3293 return true;
3294 }
3295 return false;
3296}
3297
3298bool isVPBLENDVB(unsigned Opcode) {
3299 switch (Opcode) {
3300 case VPBLENDVBYrmr:
3301 case VPBLENDVBYrrr:
3302 case VPBLENDVBrmr:
3303 case VPBLENDVBrrr:
3304 return true;
3305 }
3306 return false;
3307}
3308
3309bool isPCMPESTRI(unsigned Opcode) {
3310 switch (Opcode) {
3311 case PCMPESTRIrmi:
3312 case PCMPESTRIrri:
3313 return true;
3314 }
3315 return false;
3316}
3317
3318bool isSENDUIPI(unsigned Opcode) {
3319 return Opcode == SENDUIPI;
3320}
3321
3322bool isFLDLN2(unsigned Opcode) {
3323 return Opcode == FLDLN2;
3324}
3325
3326bool isVPMACSWD(unsigned Opcode) {
3327 switch (Opcode) {
3328 case VPMACSWDrm:
3329 case VPMACSWDrr:
3330 return true;
3331 }
3332 return false;
3333}
3334
3335bool isSHA1MSG1(unsigned Opcode) {
3336 switch (Opcode) {
3337 case SHA1MSG1rm:
3338 case SHA1MSG1rr:
3339 return true;
3340 }
3341 return false;
3342}
3343
3344bool isVADDPS(unsigned Opcode) {
3345 switch (Opcode) {
3346 case VADDPSYrm:
3347 case VADDPSYrr:
3348 case VADDPSZ128rm:
3349 case VADDPSZ128rmb:
3350 case VADDPSZ128rmbk:
3351 case VADDPSZ128rmbkz:
3352 case VADDPSZ128rmk:
3353 case VADDPSZ128rmkz:
3354 case VADDPSZ128rr:
3355 case VADDPSZ128rrk:
3356 case VADDPSZ128rrkz:
3357 case VADDPSZ256rm:
3358 case VADDPSZ256rmb:
3359 case VADDPSZ256rmbk:
3360 case VADDPSZ256rmbkz:
3361 case VADDPSZ256rmk:
3362 case VADDPSZ256rmkz:
3363 case VADDPSZ256rr:
3364 case VADDPSZ256rrk:
3365 case VADDPSZ256rrkz:
3366 case VADDPSZrm:
3367 case VADDPSZrmb:
3368 case VADDPSZrmbk:
3369 case VADDPSZrmbkz:
3370 case VADDPSZrmk:
3371 case VADDPSZrmkz:
3372 case VADDPSZrr:
3373 case VADDPSZrrb:
3374 case VADDPSZrrbk:
3375 case VADDPSZrrbkz:
3376 case VADDPSZrrk:
3377 case VADDPSZrrkz:
3378 case VADDPSrm:
3379 case VADDPSrr:
3380 return true;
3381 }
3382 return false;
3383}
3384
3385bool isVCVTPS2DQ(unsigned Opcode) {
3386 switch (Opcode) {
3387 case VCVTPS2DQYrm:
3388 case VCVTPS2DQYrr:
3389 case VCVTPS2DQZ128rm:
3390 case VCVTPS2DQZ128rmb:
3391 case VCVTPS2DQZ128rmbk:
3392 case VCVTPS2DQZ128rmbkz:
3393 case VCVTPS2DQZ128rmk:
3394 case VCVTPS2DQZ128rmkz:
3395 case VCVTPS2DQZ128rr:
3396 case VCVTPS2DQZ128rrk:
3397 case VCVTPS2DQZ128rrkz:
3398 case VCVTPS2DQZ256rm:
3399 case VCVTPS2DQZ256rmb:
3400 case VCVTPS2DQZ256rmbk:
3401 case VCVTPS2DQZ256rmbkz:
3402 case VCVTPS2DQZ256rmk:
3403 case VCVTPS2DQZ256rmkz:
3404 case VCVTPS2DQZ256rr:
3405 case VCVTPS2DQZ256rrk:
3406 case VCVTPS2DQZ256rrkz:
3407 case VCVTPS2DQZrm:
3408 case VCVTPS2DQZrmb:
3409 case VCVTPS2DQZrmbk:
3410 case VCVTPS2DQZrmbkz:
3411 case VCVTPS2DQZrmk:
3412 case VCVTPS2DQZrmkz:
3413 case VCVTPS2DQZrr:
3414 case VCVTPS2DQZrrb:
3415 case VCVTPS2DQZrrbk:
3416 case VCVTPS2DQZrrbkz:
3417 case VCVTPS2DQZrrk:
3418 case VCVTPS2DQZrrkz:
3419 case VCVTPS2DQrm:
3420 case VCVTPS2DQrr:
3421 return true;
3422 }
3423 return false;
3424}
3425
3426bool isPFPNACC(unsigned Opcode) {
3427 switch (Opcode) {
3428 case PFPNACCrm:
3429 case PFPNACCrr:
3430 return true;
3431 }
3432 return false;
3433}
3434
3435bool isFMUL(unsigned Opcode) {
3436 switch (Opcode) {
3437 case MUL_F32m:
3438 case MUL_F64m:
3439 case MUL_FST0r:
3440 case MUL_FrST0:
3441 return true;
3442 }
3443 return false;
3444}
3445
3446bool isFNSAVE(unsigned Opcode) {
3447 return Opcode == FSAVEm;
3448}
3449
3450bool isCDQE(unsigned Opcode) {
3451 return Opcode == CDQE;
3452}
3453
3454bool isVPMACSDD(unsigned Opcode) {
3455 switch (Opcode) {
3456 case VPMACSDDrm:
3457 case VPMACSDDrr:
3458 return true;
3459 }
3460 return false;
3461}
3462
3463bool isVSQRTPS(unsigned Opcode) {
3464 switch (Opcode) {
3465 case VSQRTPSYm:
3466 case VSQRTPSYr:
3467 case VSQRTPSZ128m:
3468 case VSQRTPSZ128mb:
3469 case VSQRTPSZ128mbk:
3470 case VSQRTPSZ128mbkz:
3471 case VSQRTPSZ128mk:
3472 case VSQRTPSZ128mkz:
3473 case VSQRTPSZ128r:
3474 case VSQRTPSZ128rk:
3475 case VSQRTPSZ128rkz:
3476 case VSQRTPSZ256m:
3477 case VSQRTPSZ256mb:
3478 case VSQRTPSZ256mbk:
3479 case VSQRTPSZ256mbkz:
3480 case VSQRTPSZ256mk:
3481 case VSQRTPSZ256mkz:
3482 case VSQRTPSZ256r:
3483 case VSQRTPSZ256rk:
3484 case VSQRTPSZ256rkz:
3485 case VSQRTPSZm:
3486 case VSQRTPSZmb:
3487 case VSQRTPSZmbk:
3488 case VSQRTPSZmbkz:
3489 case VSQRTPSZmk:
3490 case VSQRTPSZmkz:
3491 case VSQRTPSZr:
3492 case VSQRTPSZrb:
3493 case VSQRTPSZrbk:
3494 case VSQRTPSZrbkz:
3495 case VSQRTPSZrk:
3496 case VSQRTPSZrkz:
3497 case VSQRTPSm:
3498 case VSQRTPSr:
3499 return true;
3500 }
3501 return false;
3502}
3503
3504bool isCMPSQ(unsigned Opcode) {
3505 return Opcode == CMPSQ;
3506}
3507
3508bool isVPSCATTERDD(unsigned Opcode) {
3509 switch (Opcode) {
3510 case VPSCATTERDDZ128mr:
3511 case VPSCATTERDDZ256mr:
3512 case VPSCATTERDDZmr:
3513 return true;
3514 }
3515 return false;
3516}
3517
3518bool isVRNDSCALESD(unsigned Opcode) {
3519 switch (Opcode) {
3520 case VRNDSCALESDZm_Int:
3521 case VRNDSCALESDZm_Intk:
3522 case VRNDSCALESDZm_Intkz:
3523 case VRNDSCALESDZr_Int:
3524 case VRNDSCALESDZr_Intk:
3525 case VRNDSCALESDZr_Intkz:
3526 case VRNDSCALESDZrb_Int:
3527 case VRNDSCALESDZrb_Intk:
3528 case VRNDSCALESDZrb_Intkz:
3529 return true;
3530 }
3531 return false;
3532}
3533
3534bool isSUBPS(unsigned Opcode) {
3535 switch (Opcode) {
3536 case SUBPSrm:
3537 case SUBPSrr:
3538 return true;
3539 }
3540 return false;
3541}
3542
3543bool isVMAXSH(unsigned Opcode) {
3544 switch (Opcode) {
3545 case VMAXSHZrm_Int:
3546 case VMAXSHZrm_Intk:
3547 case VMAXSHZrm_Intkz:
3548 case VMAXSHZrr_Int:
3549 case VMAXSHZrr_Intk:
3550 case VMAXSHZrr_Intkz:
3551 case VMAXSHZrrb_Int:
3552 case VMAXSHZrrb_Intk:
3553 case VMAXSHZrrb_Intkz:
3554 return true;
3555 }
3556 return false;
3557}
3558
3559bool isFLDZ(unsigned Opcode) {
3560 return Opcode == LD_F0;
3561}
3562
3563bool isVFNMADD132SS(unsigned Opcode) {
3564 switch (Opcode) {
3565 case VFNMADD132SSZm_Int:
3566 case VFNMADD132SSZm_Intk:
3567 case VFNMADD132SSZm_Intkz:
3568 case VFNMADD132SSZr_Int:
3569 case VFNMADD132SSZr_Intk:
3570 case VFNMADD132SSZr_Intkz:
3571 case VFNMADD132SSZrb_Int:
3572 case VFNMADD132SSZrb_Intk:
3573 case VFNMADD132SSZrb_Intkz:
3574 case VFNMADD132SSm_Int:
3575 case VFNMADD132SSr_Int:
3576 return true;
3577 }
3578 return false;
3579}
3580
3581bool isLGDTW(unsigned Opcode) {
3582 return Opcode == LGDT16m;
3583}
3584
3585bool isINC(unsigned Opcode) {
3586 switch (Opcode) {
3587 case INC16m:
3588 case INC16m_EVEX:
3589 case INC16m_ND:
3590 case INC16m_NF:
3591 case INC16m_NF_ND:
3592 case INC16r:
3593 case INC16r_EVEX:
3594 case INC16r_ND:
3595 case INC16r_NF:
3596 case INC16r_NF_ND:
3597 case INC16r_alt:
3598 case INC32m:
3599 case INC32m_EVEX:
3600 case INC32m_ND:
3601 case INC32m_NF:
3602 case INC32m_NF_ND:
3603 case INC32r:
3604 case INC32r_EVEX:
3605 case INC32r_ND:
3606 case INC32r_NF:
3607 case INC32r_NF_ND:
3608 case INC32r_alt:
3609 case INC64m:
3610 case INC64m_EVEX:
3611 case INC64m_ND:
3612 case INC64m_NF:
3613 case INC64m_NF_ND:
3614 case INC64r:
3615 case INC64r_EVEX:
3616 case INC64r_ND:
3617 case INC64r_NF:
3618 case INC64r_NF_ND:
3619 case INC8m:
3620 case INC8m_EVEX:
3621 case INC8m_ND:
3622 case INC8m_NF:
3623 case INC8m_NF_ND:
3624 case INC8r:
3625 case INC8r_EVEX:
3626 case INC8r_ND:
3627 case INC8r_NF:
3628 case INC8r_NF_ND:
3629 return true;
3630 }
3631 return false;
3632}
3633
3634bool isVPANDN(unsigned Opcode) {
3635 switch (Opcode) {
3636 case VPANDNYrm:
3637 case VPANDNYrr:
3638 case VPANDNrm:
3639 case VPANDNrr:
3640 return true;
3641 }
3642 return false;
3643}
3644
3645bool isPABSB(unsigned Opcode) {
3646 switch (Opcode) {
3647 case MMX_PABSBrm:
3648 case MMX_PABSBrr:
3649 case PABSBrm:
3650 case PABSBrr:
3651 return true;
3652 }
3653 return false;
3654}
3655
3656bool isVSHA512RNDS2(unsigned Opcode) {
3657 return Opcode == VSHA512RNDS2rr;
3658}
3659
3660bool isPHADDSW(unsigned Opcode) {
3661 switch (Opcode) {
3662 case MMX_PHADDSWrm:
3663 case MMX_PHADDSWrr:
3664 case PHADDSWrm:
3665 case PHADDSWrr:
3666 return true;
3667 }
3668 return false;
3669}
3670
3671bool isVPMOVSQW(unsigned Opcode) {
3672 switch (Opcode) {
3673 case VPMOVSQWZ128mr:
3674 case VPMOVSQWZ128mrk:
3675 case VPMOVSQWZ128rr:
3676 case VPMOVSQWZ128rrk:
3677 case VPMOVSQWZ128rrkz:
3678 case VPMOVSQWZ256mr:
3679 case VPMOVSQWZ256mrk:
3680 case VPMOVSQWZ256rr:
3681 case VPMOVSQWZ256rrk:
3682 case VPMOVSQWZ256rrkz:
3683 case VPMOVSQWZmr:
3684 case VPMOVSQWZmrk:
3685 case VPMOVSQWZrr:
3686 case VPMOVSQWZrrk:
3687 case VPMOVSQWZrrkz:
3688 return true;
3689 }
3690 return false;
3691}
3692
3693bool isVPMAXUD(unsigned Opcode) {
3694 switch (Opcode) {
3695 case VPMAXUDYrm:
3696 case VPMAXUDYrr:
3697 case VPMAXUDZ128rm:
3698 case VPMAXUDZ128rmb:
3699 case VPMAXUDZ128rmbk:
3700 case VPMAXUDZ128rmbkz:
3701 case VPMAXUDZ128rmk:
3702 case VPMAXUDZ128rmkz:
3703 case VPMAXUDZ128rr:
3704 case VPMAXUDZ128rrk:
3705 case VPMAXUDZ128rrkz:
3706 case VPMAXUDZ256rm:
3707 case VPMAXUDZ256rmb:
3708 case VPMAXUDZ256rmbk:
3709 case VPMAXUDZ256rmbkz:
3710 case VPMAXUDZ256rmk:
3711 case VPMAXUDZ256rmkz:
3712 case VPMAXUDZ256rr:
3713 case VPMAXUDZ256rrk:
3714 case VPMAXUDZ256rrkz:
3715 case VPMAXUDZrm:
3716 case VPMAXUDZrmb:
3717 case VPMAXUDZrmbk:
3718 case VPMAXUDZrmbkz:
3719 case VPMAXUDZrmk:
3720 case VPMAXUDZrmkz:
3721 case VPMAXUDZrr:
3722 case VPMAXUDZrrk:
3723 case VPMAXUDZrrkz:
3724 case VPMAXUDrm:
3725 case VPMAXUDrr:
3726 return true;
3727 }
3728 return false;
3729}
3730
3731bool isADDSUBPS(unsigned Opcode) {
3732 switch (Opcode) {
3733 case ADDSUBPSrm:
3734 case ADDSUBPSrr:
3735 return true;
3736 }
3737 return false;
3738}
3739
3740bool isVPMACSSDQL(unsigned Opcode) {
3741 switch (Opcode) {
3742 case VPMACSSDQLrm:
3743 case VPMACSSDQLrr:
3744 return true;
3745 }
3746 return false;
3747}
3748
3749bool isPXOR(unsigned Opcode) {
3750 switch (Opcode) {
3751 case MMX_PXORrm:
3752 case MMX_PXORrr:
3753 case PXORrm:
3754 case PXORrr:
3755 return true;
3756 }
3757 return false;
3758}
3759
3760bool isVPSRAD(unsigned Opcode) {
3761 switch (Opcode) {
3762 case VPSRADYri:
3763 case VPSRADYrm:
3764 case VPSRADYrr:
3765 case VPSRADZ128mbi:
3766 case VPSRADZ128mbik:
3767 case VPSRADZ128mbikz:
3768 case VPSRADZ128mi:
3769 case VPSRADZ128mik:
3770 case VPSRADZ128mikz:
3771 case VPSRADZ128ri:
3772 case VPSRADZ128rik:
3773 case VPSRADZ128rikz:
3774 case VPSRADZ128rm:
3775 case VPSRADZ128rmk:
3776 case VPSRADZ128rmkz:
3777 case VPSRADZ128rr:
3778 case VPSRADZ128rrk:
3779 case VPSRADZ128rrkz:
3780 case VPSRADZ256mbi:
3781 case VPSRADZ256mbik:
3782 case VPSRADZ256mbikz:
3783 case VPSRADZ256mi:
3784 case VPSRADZ256mik:
3785 case VPSRADZ256mikz:
3786 case VPSRADZ256ri:
3787 case VPSRADZ256rik:
3788 case VPSRADZ256rikz:
3789 case VPSRADZ256rm:
3790 case VPSRADZ256rmk:
3791 case VPSRADZ256rmkz:
3792 case VPSRADZ256rr:
3793 case VPSRADZ256rrk:
3794 case VPSRADZ256rrkz:
3795 case VPSRADZmbi:
3796 case VPSRADZmbik:
3797 case VPSRADZmbikz:
3798 case VPSRADZmi:
3799 case VPSRADZmik:
3800 case VPSRADZmikz:
3801 case VPSRADZri:
3802 case VPSRADZrik:
3803 case VPSRADZrikz:
3804 case VPSRADZrm:
3805 case VPSRADZrmk:
3806 case VPSRADZrmkz:
3807 case VPSRADZrr:
3808 case VPSRADZrrk:
3809 case VPSRADZrrkz:
3810 case VPSRADri:
3811 case VPSRADrm:
3812 case VPSRADrr:
3813 return true;
3814 }
3815 return false;
3816}
3817
3818bool isVPSHAB(unsigned Opcode) {
3819 switch (Opcode) {
3820 case VPSHABmr:
3821 case VPSHABrm:
3822 case VPSHABrr:
3823 case VPSHABrr_REV:
3824 return true;
3825 }
3826 return false;
3827}
3828
3829bool isBTR(unsigned Opcode) {
3830 switch (Opcode) {
3831 case BTR16mi8:
3832 case BTR16mr:
3833 case BTR16ri8:
3834 case BTR16rr:
3835 case BTR32mi8:
3836 case BTR32mr:
3837 case BTR32ri8:
3838 case BTR32rr:
3839 case BTR64mi8:
3840 case BTR64mr:
3841 case BTR64ri8:
3842 case BTR64rr:
3843 return true;
3844 }
3845 return false;
3846}
3847
3848bool isKORW(unsigned Opcode) {
3849 return Opcode == KORWrr;
3850}
3851
3852bool isVRANGESS(unsigned Opcode) {
3853 switch (Opcode) {
3854 case VRANGESSZrmi:
3855 case VRANGESSZrmik:
3856 case VRANGESSZrmikz:
3857 case VRANGESSZrri:
3858 case VRANGESSZrrib:
3859 case VRANGESSZrribk:
3860 case VRANGESSZrribkz:
3861 case VRANGESSZrrik:
3862 case VRANGESSZrrikz:
3863 return true;
3864 }
3865 return false;
3866}
3867
3868bool isVCMPPS(unsigned Opcode) {
3869 switch (Opcode) {
3870 case VCMPPSYrmi:
3871 case VCMPPSYrri:
3872 case VCMPPSZ128rmbi:
3873 case VCMPPSZ128rmbik:
3874 case VCMPPSZ128rmi:
3875 case VCMPPSZ128rmik:
3876 case VCMPPSZ128rri:
3877 case VCMPPSZ128rrik:
3878 case VCMPPSZ256rmbi:
3879 case VCMPPSZ256rmbik:
3880 case VCMPPSZ256rmi:
3881 case VCMPPSZ256rmik:
3882 case VCMPPSZ256rri:
3883 case VCMPPSZ256rrik:
3884 case VCMPPSZrmbi:
3885 case VCMPPSZrmbik:
3886 case VCMPPSZrmi:
3887 case VCMPPSZrmik:
3888 case VCMPPSZrri:
3889 case VCMPPSZrrib:
3890 case VCMPPSZrribk:
3891 case VCMPPSZrrik:
3892 case VCMPPSrmi:
3893 case VCMPPSrri:
3894 return true;
3895 }
3896 return false;
3897}
3898
3899bool isVPLZCNTD(unsigned Opcode) {
3900 switch (Opcode) {
3901 case VPLZCNTDZ128rm:
3902 case VPLZCNTDZ128rmb:
3903 case VPLZCNTDZ128rmbk:
3904 case VPLZCNTDZ128rmbkz:
3905 case VPLZCNTDZ128rmk:
3906 case VPLZCNTDZ128rmkz:
3907 case VPLZCNTDZ128rr:
3908 case VPLZCNTDZ128rrk:
3909 case VPLZCNTDZ128rrkz:
3910 case VPLZCNTDZ256rm:
3911 case VPLZCNTDZ256rmb:
3912 case VPLZCNTDZ256rmbk:
3913 case VPLZCNTDZ256rmbkz:
3914 case VPLZCNTDZ256rmk:
3915 case VPLZCNTDZ256rmkz:
3916 case VPLZCNTDZ256rr:
3917 case VPLZCNTDZ256rrk:
3918 case VPLZCNTDZ256rrkz:
3919 case VPLZCNTDZrm:
3920 case VPLZCNTDZrmb:
3921 case VPLZCNTDZrmbk:
3922 case VPLZCNTDZrmbkz:
3923 case VPLZCNTDZrmk:
3924 case VPLZCNTDZrmkz:
3925 case VPLZCNTDZrr:
3926 case VPLZCNTDZrrk:
3927 case VPLZCNTDZrrkz:
3928 return true;
3929 }
3930 return false;
3931}
3932
3933bool isTDPBUUD(unsigned Opcode) {
3934 return Opcode == TDPBUUD;
3935}
3936
3937bool isROUNDPS(unsigned Opcode) {
3938 switch (Opcode) {
3939 case ROUNDPSmi:
3940 case ROUNDPSri:
3941 return true;
3942 }
3943 return false;
3944}
3945
3946bool isFABS(unsigned Opcode) {
3947 return Opcode == ABS_F;
3948}
3949
3950bool isSUBPD(unsigned Opcode) {
3951 switch (Opcode) {
3952 case SUBPDrm:
3953 case SUBPDrr:
3954 return true;
3955 }
3956 return false;
3957}
3958
3959bool isGF2P8MULB(unsigned Opcode) {
3960 switch (Opcode) {
3961 case GF2P8MULBrm:
3962 case GF2P8MULBrr:
3963 return true;
3964 }
3965 return false;
3966}
3967
3968bool isTZMSK(unsigned Opcode) {
3969 switch (Opcode) {
3970 case TZMSK32rm:
3971 case TZMSK32rr:
3972 case TZMSK64rm:
3973 case TZMSK64rr:
3974 return true;
3975 }
3976 return false;
3977}
3978
3979bool isANDPS(unsigned Opcode) {
3980 switch (Opcode) {
3981 case ANDPSrm:
3982 case ANDPSrr:
3983 return true;
3984 }
3985 return false;
3986}
3987
3988bool isVEXTRACTF32X8(unsigned Opcode) {
3989 switch (Opcode) {
3990 case VEXTRACTF32x8Zmr:
3991 case VEXTRACTF32x8Zmrk:
3992 case VEXTRACTF32x8Zrr:
3993 case VEXTRACTF32x8Zrrk:
3994 case VEXTRACTF32x8Zrrkz:
3995 return true;
3996 }
3997 return false;
3998}
3999
4000bool isSEAMRET(unsigned Opcode) {
4001 return Opcode == SEAMRET;
4002}
4003
4004bool isVPCOMW(unsigned Opcode) {
4005 switch (Opcode) {
4006 case VPCOMWmi:
4007 case VPCOMWri:
4008 return true;
4009 }
4010 return false;
4011}
4012
4013bool isVFIXUPIMMPD(unsigned Opcode) {
4014 switch (Opcode) {
4015 case VFIXUPIMMPDZ128rmbi:
4016 case VFIXUPIMMPDZ128rmbik:
4017 case VFIXUPIMMPDZ128rmbikz:
4018 case VFIXUPIMMPDZ128rmi:
4019 case VFIXUPIMMPDZ128rmik:
4020 case VFIXUPIMMPDZ128rmikz:
4021 case VFIXUPIMMPDZ128rri:
4022 case VFIXUPIMMPDZ128rrik:
4023 case VFIXUPIMMPDZ128rrikz:
4024 case VFIXUPIMMPDZ256rmbi:
4025 case VFIXUPIMMPDZ256rmbik:
4026 case VFIXUPIMMPDZ256rmbikz:
4027 case VFIXUPIMMPDZ256rmi:
4028 case VFIXUPIMMPDZ256rmik:
4029 case VFIXUPIMMPDZ256rmikz:
4030 case VFIXUPIMMPDZ256rri:
4031 case VFIXUPIMMPDZ256rrik:
4032 case VFIXUPIMMPDZ256rrikz:
4033 case VFIXUPIMMPDZrmbi:
4034 case VFIXUPIMMPDZrmbik:
4035 case VFIXUPIMMPDZrmbikz:
4036 case VFIXUPIMMPDZrmi:
4037 case VFIXUPIMMPDZrmik:
4038 case VFIXUPIMMPDZrmikz:
4039 case VFIXUPIMMPDZrri:
4040 case VFIXUPIMMPDZrrib:
4041 case VFIXUPIMMPDZrribk:
4042 case VFIXUPIMMPDZrribkz:
4043 case VFIXUPIMMPDZrrik:
4044 case VFIXUPIMMPDZrrikz:
4045 return true;
4046 }
4047 return false;
4048}
4049
4050bool isKANDND(unsigned Opcode) {
4051 return Opcode == KANDNDrr;
4052}
4053
4054bool isVMRESUME(unsigned Opcode) {
4055 return Opcode == VMRESUME;
4056}
4057
4058bool isCVTPD2DQ(unsigned Opcode) {
4059 switch (Opcode) {
4060 case CVTPD2DQrm:
4061 case CVTPD2DQrr:
4062 return true;
4063 }
4064 return false;
4065}
4066
4067bool isVFNMADD213PS(unsigned Opcode) {
4068 switch (Opcode) {
4069 case VFNMADD213PSYm:
4070 case VFNMADD213PSYr:
4071 case VFNMADD213PSZ128m:
4072 case VFNMADD213PSZ128mb:
4073 case VFNMADD213PSZ128mbk:
4074 case VFNMADD213PSZ128mbkz:
4075 case VFNMADD213PSZ128mk:
4076 case VFNMADD213PSZ128mkz:
4077 case VFNMADD213PSZ128r:
4078 case VFNMADD213PSZ128rk:
4079 case VFNMADD213PSZ128rkz:
4080 case VFNMADD213PSZ256m:
4081 case VFNMADD213PSZ256mb:
4082 case VFNMADD213PSZ256mbk:
4083 case VFNMADD213PSZ256mbkz:
4084 case VFNMADD213PSZ256mk:
4085 case VFNMADD213PSZ256mkz:
4086 case VFNMADD213PSZ256r:
4087 case VFNMADD213PSZ256rk:
4088 case VFNMADD213PSZ256rkz:
4089 case VFNMADD213PSZm:
4090 case VFNMADD213PSZmb:
4091 case VFNMADD213PSZmbk:
4092 case VFNMADD213PSZmbkz:
4093 case VFNMADD213PSZmk:
4094 case VFNMADD213PSZmkz:
4095 case VFNMADD213PSZr:
4096 case VFNMADD213PSZrb:
4097 case VFNMADD213PSZrbk:
4098 case VFNMADD213PSZrbkz:
4099 case VFNMADD213PSZrk:
4100 case VFNMADD213PSZrkz:
4101 case VFNMADD213PSm:
4102 case VFNMADD213PSr:
4103 return true;
4104 }
4105 return false;
4106}
4107
4108bool isVPEXTRD(unsigned Opcode) {
4109 switch (Opcode) {
4110 case VPEXTRDZmr:
4111 case VPEXTRDZrr:
4112 case VPEXTRDmr:
4113 case VPEXTRDrr:
4114 return true;
4115 }
4116 return false;
4117}
4118
4119bool isPACKUSWB(unsigned Opcode) {
4120 switch (Opcode) {
4121 case MMX_PACKUSWBrm:
4122 case MMX_PACKUSWBrr:
4123 case PACKUSWBrm:
4124 case PACKUSWBrr:
4125 return true;
4126 }
4127 return false;
4128}
4129
4130bool isVEXTRACTI32X8(unsigned Opcode) {
4131 switch (Opcode) {
4132 case VEXTRACTI32x8Zmr:
4133 case VEXTRACTI32x8Zmrk:
4134 case VEXTRACTI32x8Zrr:
4135 case VEXTRACTI32x8Zrrk:
4136 case VEXTRACTI32x8Zrrkz:
4137 return true;
4138 }
4139 return false;
4140}
4141
4142bool isVHADDPD(unsigned Opcode) {
4143 switch (Opcode) {
4144 case VHADDPDYrm:
4145 case VHADDPDYrr:
4146 case VHADDPDrm:
4147 case VHADDPDrr:
4148 return true;
4149 }
4150 return false;
4151}
4152
4153bool isVPSADBW(unsigned Opcode) {
4154 switch (Opcode) {
4155 case VPSADBWYrm:
4156 case VPSADBWYrr:
4157 case VPSADBWZ128rm:
4158 case VPSADBWZ128rr:
4159 case VPSADBWZ256rm:
4160 case VPSADBWZ256rr:
4161 case VPSADBWZrm:
4162 case VPSADBWZrr:
4163 case VPSADBWrm:
4164 case VPSADBWrr:
4165 return true;
4166 }
4167 return false;
4168}
4169
4170bool isMOVDQ2Q(unsigned Opcode) {
4171 return Opcode == MMX_MOVDQ2Qrr;
4172}
4173
4174bool isPUNPCKHBW(unsigned Opcode) {
4175 switch (Opcode) {
4176 case MMX_PUNPCKHBWrm:
4177 case MMX_PUNPCKHBWrr:
4178 case PUNPCKHBWrm:
4179 case PUNPCKHBWrr:
4180 return true;
4181 }
4182 return false;
4183}
4184
4185bool isXOR(unsigned Opcode) {
4186 switch (Opcode) {
4187 case XOR16i16:
4188 case XOR16mi:
4189 case XOR16mi8:
4190 case XOR16mi8_EVEX:
4191 case XOR16mi8_ND:
4192 case XOR16mi8_NF:
4193 case XOR16mi8_NF_ND:
4194 case XOR16mi_EVEX:
4195 case XOR16mi_ND:
4196 case XOR16mi_NF:
4197 case XOR16mi_NF_ND:
4198 case XOR16mr:
4199 case XOR16mr_EVEX:
4200 case XOR16mr_ND:
4201 case XOR16mr_NF:
4202 case XOR16mr_NF_ND:
4203 case XOR16ri:
4204 case XOR16ri8:
4205 case XOR16ri8_EVEX:
4206 case XOR16ri8_ND:
4207 case XOR16ri8_NF:
4208 case XOR16ri8_NF_ND:
4209 case XOR16ri_EVEX:
4210 case XOR16ri_ND:
4211 case XOR16ri_NF:
4212 case XOR16ri_NF_ND:
4213 case XOR16rm:
4214 case XOR16rm_EVEX:
4215 case XOR16rm_ND:
4216 case XOR16rm_NF:
4217 case XOR16rm_NF_ND:
4218 case XOR16rr:
4219 case XOR16rr_EVEX:
4220 case XOR16rr_EVEX_REV:
4221 case XOR16rr_ND:
4222 case XOR16rr_ND_REV:
4223 case XOR16rr_NF:
4224 case XOR16rr_NF_ND:
4225 case XOR16rr_NF_ND_REV:
4226 case XOR16rr_NF_REV:
4227 case XOR16rr_REV:
4228 case XOR32i32:
4229 case XOR32mi:
4230 case XOR32mi8:
4231 case XOR32mi8_EVEX:
4232 case XOR32mi8_ND:
4233 case XOR32mi8_NF:
4234 case XOR32mi8_NF_ND:
4235 case XOR32mi_EVEX:
4236 case XOR32mi_ND:
4237 case XOR32mi_NF:
4238 case XOR32mi_NF_ND:
4239 case XOR32mr:
4240 case XOR32mr_EVEX:
4241 case XOR32mr_ND:
4242 case XOR32mr_NF:
4243 case XOR32mr_NF_ND:
4244 case XOR32ri:
4245 case XOR32ri8:
4246 case XOR32ri8_EVEX:
4247 case XOR32ri8_ND:
4248 case XOR32ri8_NF:
4249 case XOR32ri8_NF_ND:
4250 case XOR32ri_EVEX:
4251 case XOR32ri_ND:
4252 case XOR32ri_NF:
4253 case XOR32ri_NF_ND:
4254 case XOR32rm:
4255 case XOR32rm_EVEX:
4256 case XOR32rm_ND:
4257 case XOR32rm_NF:
4258 case XOR32rm_NF_ND:
4259 case XOR32rr:
4260 case XOR32rr_EVEX:
4261 case XOR32rr_EVEX_REV:
4262 case XOR32rr_ND:
4263 case XOR32rr_ND_REV:
4264 case XOR32rr_NF:
4265 case XOR32rr_NF_ND:
4266 case XOR32rr_NF_ND_REV:
4267 case XOR32rr_NF_REV:
4268 case XOR32rr_REV:
4269 case XOR64i32:
4270 case XOR64mi32:
4271 case XOR64mi32_EVEX:
4272 case XOR64mi32_ND:
4273 case XOR64mi32_NF:
4274 case XOR64mi32_NF_ND:
4275 case XOR64mi8:
4276 case XOR64mi8_EVEX:
4277 case XOR64mi8_ND:
4278 case XOR64mi8_NF:
4279 case XOR64mi8_NF_ND:
4280 case XOR64mr:
4281 case XOR64mr_EVEX:
4282 case XOR64mr_ND:
4283 case XOR64mr_NF:
4284 case XOR64mr_NF_ND:
4285 case XOR64ri32:
4286 case XOR64ri32_EVEX:
4287 case XOR64ri32_ND:
4288 case XOR64ri32_NF:
4289 case XOR64ri32_NF_ND:
4290 case XOR64ri8:
4291 case XOR64ri8_EVEX:
4292 case XOR64ri8_ND:
4293 case XOR64ri8_NF:
4294 case XOR64ri8_NF_ND:
4295 case XOR64rm:
4296 case XOR64rm_EVEX:
4297 case XOR64rm_ND:
4298 case XOR64rm_NF:
4299 case XOR64rm_NF_ND:
4300 case XOR64rr:
4301 case XOR64rr_EVEX:
4302 case XOR64rr_EVEX_REV:
4303 case XOR64rr_ND:
4304 case XOR64rr_ND_REV:
4305 case XOR64rr_NF:
4306 case XOR64rr_NF_ND:
4307 case XOR64rr_NF_ND_REV:
4308 case XOR64rr_NF_REV:
4309 case XOR64rr_REV:
4310 case XOR8i8:
4311 case XOR8mi:
4312 case XOR8mi8:
4313 case XOR8mi_EVEX:
4314 case XOR8mi_ND:
4315 case XOR8mi_NF:
4316 case XOR8mi_NF_ND:
4317 case XOR8mr:
4318 case XOR8mr_EVEX:
4319 case XOR8mr_ND:
4320 case XOR8mr_NF:
4321 case XOR8mr_NF_ND:
4322 case XOR8ri:
4323 case XOR8ri8:
4324 case XOR8ri_EVEX:
4325 case XOR8ri_ND:
4326 case XOR8ri_NF:
4327 case XOR8ri_NF_ND:
4328 case XOR8rm:
4329 case XOR8rm_EVEX:
4330 case XOR8rm_ND:
4331 case XOR8rm_NF:
4332 case XOR8rm_NF_ND:
4333 case XOR8rr:
4334 case XOR8rr_EVEX:
4335 case XOR8rr_EVEX_REV:
4336 case XOR8rr_ND:
4337 case XOR8rr_ND_REV:
4338 case XOR8rr_NF:
4339 case XOR8rr_NF_ND:
4340 case XOR8rr_NF_ND_REV:
4341 case XOR8rr_NF_REV:
4342 case XOR8rr_REV:
4343 return true;
4344 }
4345 return false;
4346}
4347
4348bool isPSIGNB(unsigned Opcode) {
4349 switch (Opcode) {
4350 case MMX_PSIGNBrm:
4351 case MMX_PSIGNBrr:
4352 case PSIGNBrm:
4353 case PSIGNBrr:
4354 return true;
4355 }
4356 return false;
4357}
4358
4359bool isVPHADDSW(unsigned Opcode) {
4360 switch (Opcode) {
4361 case VPHADDSWYrm:
4362 case VPHADDSWYrr:
4363 case VPHADDSWrm:
4364 case VPHADDSWrr:
4365 return true;
4366 }
4367 return false;
4368}
4369
4370bool isFADDP(unsigned Opcode) {
4371 return Opcode == ADD_FPrST0;
4372}
4373
4374bool isNEG(unsigned Opcode) {
4375 switch (Opcode) {
4376 case NEG16m:
4377 case NEG16m_EVEX:
4378 case NEG16m_ND:
4379 case NEG16m_NF:
4380 case NEG16m_NF_ND:
4381 case NEG16r:
4382 case NEG16r_EVEX:
4383 case NEG16r_ND:
4384 case NEG16r_NF:
4385 case NEG16r_NF_ND:
4386 case NEG32m:
4387 case NEG32m_EVEX:
4388 case NEG32m_ND:
4389 case NEG32m_NF:
4390 case NEG32m_NF_ND:
4391 case NEG32r:
4392 case NEG32r_EVEX:
4393 case NEG32r_ND:
4394 case NEG32r_NF:
4395 case NEG32r_NF_ND:
4396 case NEG64m:
4397 case NEG64m_EVEX:
4398 case NEG64m_ND:
4399 case NEG64m_NF:
4400 case NEG64m_NF_ND:
4401 case NEG64r:
4402 case NEG64r_EVEX:
4403 case NEG64r_ND:
4404 case NEG64r_NF:
4405 case NEG64r_NF_ND:
4406 case NEG8m:
4407 case NEG8m_EVEX:
4408 case NEG8m_ND:
4409 case NEG8m_NF:
4410 case NEG8m_NF_ND:
4411 case NEG8r:
4412 case NEG8r_EVEX:
4413 case NEG8r_ND:
4414 case NEG8r_NF:
4415 case NEG8r_NF_ND:
4416 return true;
4417 }
4418 return false;
4419}
4420
4421bool isFLDLG2(unsigned Opcode) {
4422 return Opcode == FLDLG2;
4423}
4424
4425bool isFNOP(unsigned Opcode) {
4426 return Opcode == FNOP;
4427}
4428
4429bool isVMINSS(unsigned Opcode) {
4430 switch (Opcode) {
4431 case VMINSSZrm_Int:
4432 case VMINSSZrm_Intk:
4433 case VMINSSZrm_Intkz:
4434 case VMINSSZrr_Int:
4435 case VMINSSZrr_Intk:
4436 case VMINSSZrr_Intkz:
4437 case VMINSSZrrb_Int:
4438 case VMINSSZrrb_Intk:
4439 case VMINSSZrrb_Intkz:
4440 case VMINSSrm_Int:
4441 case VMINSSrr_Int:
4442 return true;
4443 }
4444 return false;
4445}
4446
4447bool isPCMPISTRM(unsigned Opcode) {
4448 switch (Opcode) {
4449 case PCMPISTRMrmi:
4450 case PCMPISTRMrri:
4451 return true;
4452 }
4453 return false;
4454}
4455
4456bool isVFMADD132SS(unsigned Opcode) {
4457 switch (Opcode) {
4458 case VFMADD132SSZm_Int:
4459 case VFMADD132SSZm_Intk:
4460 case VFMADD132SSZm_Intkz:
4461 case VFMADD132SSZr_Int:
4462 case VFMADD132SSZr_Intk:
4463 case VFMADD132SSZr_Intkz:
4464 case VFMADD132SSZrb_Int:
4465 case VFMADD132SSZrb_Intk:
4466 case VFMADD132SSZrb_Intkz:
4467 case VFMADD132SSm_Int:
4468 case VFMADD132SSr_Int:
4469 return true;
4470 }
4471 return false;
4472}
4473
4474bool isFDIVRP(unsigned Opcode) {
4475 return Opcode == DIVR_FPrST0;
4476}
4477
4478bool isPUSHAL(unsigned Opcode) {
4479 return Opcode == PUSHA32;
4480}
4481
4482bool isVPMACSDQL(unsigned Opcode) {
4483 switch (Opcode) {
4484 case VPMACSDQLrm:
4485 case VPMACSDQLrr:
4486 return true;
4487 }
4488 return false;
4489}
4490
4491bool isSUBSD(unsigned Opcode) {
4492 switch (Opcode) {
4493 case SUBSDrm_Int:
4494 case SUBSDrr_Int:
4495 return true;
4496 }
4497 return false;
4498}
4499
4500bool isVPBLENDMQ(unsigned Opcode) {
4501 switch (Opcode) {
4502 case VPBLENDMQZ128rm:
4503 case VPBLENDMQZ128rmb:
4504 case VPBLENDMQZ128rmbk:
4505 case VPBLENDMQZ128rmbkz:
4506 case VPBLENDMQZ128rmk:
4507 case VPBLENDMQZ128rmkz:
4508 case VPBLENDMQZ128rr:
4509 case VPBLENDMQZ128rrk:
4510 case VPBLENDMQZ128rrkz:
4511 case VPBLENDMQZ256rm:
4512 case VPBLENDMQZ256rmb:
4513 case VPBLENDMQZ256rmbk:
4514 case VPBLENDMQZ256rmbkz:
4515 case VPBLENDMQZ256rmk:
4516 case VPBLENDMQZ256rmkz:
4517 case VPBLENDMQZ256rr:
4518 case VPBLENDMQZ256rrk:
4519 case VPBLENDMQZ256rrkz:
4520 case VPBLENDMQZrm:
4521 case VPBLENDMQZrmb:
4522 case VPBLENDMQZrmbk:
4523 case VPBLENDMQZrmbkz:
4524 case VPBLENDMQZrmk:
4525 case VPBLENDMQZrmkz:
4526 case VPBLENDMQZrr:
4527 case VPBLENDMQZrrk:
4528 case VPBLENDMQZrrkz:
4529 return true;
4530 }
4531 return false;
4532}
4533
4534bool isVGATHERDPS(unsigned Opcode) {
4535 switch (Opcode) {
4536 case VGATHERDPSYrm:
4537 case VGATHERDPSZ128rm:
4538 case VGATHERDPSZ256rm:
4539 case VGATHERDPSZrm:
4540 case VGATHERDPSrm:
4541 return true;
4542 }
4543 return false;
4544}
4545
4546bool isSYSRET(unsigned Opcode) {
4547 return Opcode == SYSRET;
4548}
4549
4550bool isVPADDB(unsigned Opcode) {
4551 switch (Opcode) {
4552 case VPADDBYrm:
4553 case VPADDBYrr:
4554 case VPADDBZ128rm:
4555 case VPADDBZ128rmk:
4556 case VPADDBZ128rmkz:
4557 case VPADDBZ128rr:
4558 case VPADDBZ128rrk:
4559 case VPADDBZ128rrkz:
4560 case VPADDBZ256rm:
4561 case VPADDBZ256rmk:
4562 case VPADDBZ256rmkz:
4563 case VPADDBZ256rr:
4564 case VPADDBZ256rrk:
4565 case VPADDBZ256rrkz:
4566 case VPADDBZrm:
4567 case VPADDBZrmk:
4568 case VPADDBZrmkz:
4569 case VPADDBZrr:
4570 case VPADDBZrrk:
4571 case VPADDBZrrkz:
4572 case VPADDBrm:
4573 case VPADDBrr:
4574 return true;
4575 }
4576 return false;
4577}
4578
4579bool isXEND(unsigned Opcode) {
4580 return Opcode == XEND;
4581}
4582
4583bool isWRSSD(unsigned Opcode) {
4584 switch (Opcode) {
4585 case WRSSD:
4586 case WRSSD_EVEX:
4587 return true;
4588 }
4589 return false;
4590}
4591
4592bool isVCVTDQ2PH(unsigned Opcode) {
4593 switch (Opcode) {
4594 case VCVTDQ2PHZ128rm:
4595 case VCVTDQ2PHZ128rmb:
4596 case VCVTDQ2PHZ128rmbk:
4597 case VCVTDQ2PHZ128rmbkz:
4598 case VCVTDQ2PHZ128rmk:
4599 case VCVTDQ2PHZ128rmkz:
4600 case VCVTDQ2PHZ128rr:
4601 case VCVTDQ2PHZ128rrk:
4602 case VCVTDQ2PHZ128rrkz:
4603 case VCVTDQ2PHZ256rm:
4604 case VCVTDQ2PHZ256rmb:
4605 case VCVTDQ2PHZ256rmbk:
4606 case VCVTDQ2PHZ256rmbkz:
4607 case VCVTDQ2PHZ256rmk:
4608 case VCVTDQ2PHZ256rmkz:
4609 case VCVTDQ2PHZ256rr:
4610 case VCVTDQ2PHZ256rrk:
4611 case VCVTDQ2PHZ256rrkz:
4612 case VCVTDQ2PHZrm:
4613 case VCVTDQ2PHZrmb:
4614 case VCVTDQ2PHZrmbk:
4615 case VCVTDQ2PHZrmbkz:
4616 case VCVTDQ2PHZrmk:
4617 case VCVTDQ2PHZrmkz:
4618 case VCVTDQ2PHZrr:
4619 case VCVTDQ2PHZrrb:
4620 case VCVTDQ2PHZrrbk:
4621 case VCVTDQ2PHZrrbkz:
4622 case VCVTDQ2PHZrrk:
4623 case VCVTDQ2PHZrrkz:
4624 return true;
4625 }
4626 return false;
4627}
4628
4629bool isCVTPD2PS(unsigned Opcode) {
4630 switch (Opcode) {
4631 case CVTPD2PSrm:
4632 case CVTPD2PSrr:
4633 return true;
4634 }
4635 return false;
4636}
4637
4638bool isMAXPD(unsigned Opcode) {
4639 switch (Opcode) {
4640 case MAXPDrm:
4641 case MAXPDrr:
4642 return true;
4643 }
4644 return false;
4645}
4646
4647bool isRCPSS(unsigned Opcode) {
4648 switch (Opcode) {
4649 case RCPSSm_Int:
4650 case RCPSSr_Int:
4651 return true;
4652 }
4653 return false;
4654}
4655
4656bool isVMOVAPD(unsigned Opcode) {
4657 switch (Opcode) {
4658 case VMOVAPDYmr:
4659 case VMOVAPDYrm:
4660 case VMOVAPDYrr:
4661 case VMOVAPDYrr_REV:
4662 case VMOVAPDZ128mr:
4663 case VMOVAPDZ128mrk:
4664 case VMOVAPDZ128rm:
4665 case VMOVAPDZ128rmk:
4666 case VMOVAPDZ128rmkz:
4667 case VMOVAPDZ128rr:
4668 case VMOVAPDZ128rr_REV:
4669 case VMOVAPDZ128rrk:
4670 case VMOVAPDZ128rrk_REV:
4671 case VMOVAPDZ128rrkz:
4672 case VMOVAPDZ128rrkz_REV:
4673 case VMOVAPDZ256mr:
4674 case VMOVAPDZ256mrk:
4675 case VMOVAPDZ256rm:
4676 case VMOVAPDZ256rmk:
4677 case VMOVAPDZ256rmkz:
4678 case VMOVAPDZ256rr:
4679 case VMOVAPDZ256rr_REV:
4680 case VMOVAPDZ256rrk:
4681 case VMOVAPDZ256rrk_REV:
4682 case VMOVAPDZ256rrkz:
4683 case VMOVAPDZ256rrkz_REV:
4684 case VMOVAPDZmr:
4685 case VMOVAPDZmrk:
4686 case VMOVAPDZrm:
4687 case VMOVAPDZrmk:
4688 case VMOVAPDZrmkz:
4689 case VMOVAPDZrr:
4690 case VMOVAPDZrr_REV:
4691 case VMOVAPDZrrk:
4692 case VMOVAPDZrrk_REV:
4693 case VMOVAPDZrrkz:
4694 case VMOVAPDZrrkz_REV:
4695 case VMOVAPDmr:
4696 case VMOVAPDrm:
4697 case VMOVAPDrr:
4698 case VMOVAPDrr_REV:
4699 return true;
4700 }
4701 return false;
4702}
4703
4704bool isVPSUBSB(unsigned Opcode) {
4705 switch (Opcode) {
4706 case VPSUBSBYrm:
4707 case VPSUBSBYrr:
4708 case VPSUBSBZ128rm:
4709 case VPSUBSBZ128rmk:
4710 case VPSUBSBZ128rmkz:
4711 case VPSUBSBZ128rr:
4712 case VPSUBSBZ128rrk:
4713 case VPSUBSBZ128rrkz:
4714 case VPSUBSBZ256rm:
4715 case VPSUBSBZ256rmk:
4716 case VPSUBSBZ256rmkz:
4717 case VPSUBSBZ256rr:
4718 case VPSUBSBZ256rrk:
4719 case VPSUBSBZ256rrkz:
4720 case VPSUBSBZrm:
4721 case VPSUBSBZrmk:
4722 case VPSUBSBZrmkz:
4723 case VPSUBSBZrr:
4724 case VPSUBSBZrrk:
4725 case VPSUBSBZrrkz:
4726 case VPSUBSBrm:
4727 case VPSUBSBrr:
4728 return true;
4729 }
4730 return false;
4731}
4732
4733bool isRDTSC(unsigned Opcode) {
4734 return Opcode == RDTSC;
4735}
4736
4737bool isVPMADCSSWD(unsigned Opcode) {
4738 switch (Opcode) {
4739 case VPMADCSSWDrm:
4740 case VPMADCSSWDrr:
4741 return true;
4742 }
4743 return false;
4744}
4745
4746bool isVFNMADD213PH(unsigned Opcode) {
4747 switch (Opcode) {
4748 case VFNMADD213PHZ128m:
4749 case VFNMADD213PHZ128mb:
4750 case VFNMADD213PHZ128mbk:
4751 case VFNMADD213PHZ128mbkz:
4752 case VFNMADD213PHZ128mk:
4753 case VFNMADD213PHZ128mkz:
4754 case VFNMADD213PHZ128r:
4755 case VFNMADD213PHZ128rk:
4756 case VFNMADD213PHZ128rkz:
4757 case VFNMADD213PHZ256m:
4758 case VFNMADD213PHZ256mb:
4759 case VFNMADD213PHZ256mbk:
4760 case VFNMADD213PHZ256mbkz:
4761 case VFNMADD213PHZ256mk:
4762 case VFNMADD213PHZ256mkz:
4763 case VFNMADD213PHZ256r:
4764 case VFNMADD213PHZ256rk:
4765 case VFNMADD213PHZ256rkz:
4766 case VFNMADD213PHZm:
4767 case VFNMADD213PHZmb:
4768 case VFNMADD213PHZmbk:
4769 case VFNMADD213PHZmbkz:
4770 case VFNMADD213PHZmk:
4771 case VFNMADD213PHZmkz:
4772 case VFNMADD213PHZr:
4773 case VFNMADD213PHZrb:
4774 case VFNMADD213PHZrbk:
4775 case VFNMADD213PHZrbkz:
4776 case VFNMADD213PHZrk:
4777 case VFNMADD213PHZrkz:
4778 return true;
4779 }
4780 return false;
4781}
4782
4783bool isVGF2P8AFFINEQB(unsigned Opcode) {
4784 switch (Opcode) {
4785 case VGF2P8AFFINEQBYrmi:
4786 case VGF2P8AFFINEQBYrri:
4787 case VGF2P8AFFINEQBZ128rmbi:
4788 case VGF2P8AFFINEQBZ128rmbik:
4789 case VGF2P8AFFINEQBZ128rmbikz:
4790 case VGF2P8AFFINEQBZ128rmi:
4791 case VGF2P8AFFINEQBZ128rmik:
4792 case VGF2P8AFFINEQBZ128rmikz:
4793 case VGF2P8AFFINEQBZ128rri:
4794 case VGF2P8AFFINEQBZ128rrik:
4795 case VGF2P8AFFINEQBZ128rrikz:
4796 case VGF2P8AFFINEQBZ256rmbi:
4797 case VGF2P8AFFINEQBZ256rmbik:
4798 case VGF2P8AFFINEQBZ256rmbikz:
4799 case VGF2P8AFFINEQBZ256rmi:
4800 case VGF2P8AFFINEQBZ256rmik:
4801 case VGF2P8AFFINEQBZ256rmikz:
4802 case VGF2P8AFFINEQBZ256rri:
4803 case VGF2P8AFFINEQBZ256rrik:
4804 case VGF2P8AFFINEQBZ256rrikz:
4805 case VGF2P8AFFINEQBZrmbi:
4806 case VGF2P8AFFINEQBZrmbik:
4807 case VGF2P8AFFINEQBZrmbikz:
4808 case VGF2P8AFFINEQBZrmi:
4809 case VGF2P8AFFINEQBZrmik:
4810 case VGF2P8AFFINEQBZrmikz:
4811 case VGF2P8AFFINEQBZrri:
4812 case VGF2P8AFFINEQBZrrik:
4813 case VGF2P8AFFINEQBZrrikz:
4814 case VGF2P8AFFINEQBrmi:
4815 case VGF2P8AFFINEQBrri:
4816 return true;
4817 }
4818 return false;
4819}
4820
4821bool isPMOVZXWD(unsigned Opcode) {
4822 switch (Opcode) {
4823 case PMOVZXWDrm:
4824 case PMOVZXWDrr:
4825 return true;
4826 }
4827 return false;
4828}
4829
4830bool isPMINUD(unsigned Opcode) {
4831 switch (Opcode) {
4832 case PMINUDrm:
4833 case PMINUDrr:
4834 return true;
4835 }
4836 return false;
4837}
4838
4839bool isVCVTPH2UW(unsigned Opcode) {
4840 switch (Opcode) {
4841 case VCVTPH2UWZ128rm:
4842 case VCVTPH2UWZ128rmb:
4843 case VCVTPH2UWZ128rmbk:
4844 case VCVTPH2UWZ128rmbkz:
4845 case VCVTPH2UWZ128rmk:
4846 case VCVTPH2UWZ128rmkz:
4847 case VCVTPH2UWZ128rr:
4848 case VCVTPH2UWZ128rrk:
4849 case VCVTPH2UWZ128rrkz:
4850 case VCVTPH2UWZ256rm:
4851 case VCVTPH2UWZ256rmb:
4852 case VCVTPH2UWZ256rmbk:
4853 case VCVTPH2UWZ256rmbkz:
4854 case VCVTPH2UWZ256rmk:
4855 case VCVTPH2UWZ256rmkz:
4856 case VCVTPH2UWZ256rr:
4857 case VCVTPH2UWZ256rrk:
4858 case VCVTPH2UWZ256rrkz:
4859 case VCVTPH2UWZrm:
4860 case VCVTPH2UWZrmb:
4861 case VCVTPH2UWZrmbk:
4862 case VCVTPH2UWZrmbkz:
4863 case VCVTPH2UWZrmk:
4864 case VCVTPH2UWZrmkz:
4865 case VCVTPH2UWZrr:
4866 case VCVTPH2UWZrrb:
4867 case VCVTPH2UWZrrbk:
4868 case VCVTPH2UWZrrbkz:
4869 case VCVTPH2UWZrrk:
4870 case VCVTPH2UWZrrkz:
4871 return true;
4872 }
4873 return false;
4874}
4875
4876bool isPADDSW(unsigned Opcode) {
4877 switch (Opcode) {
4878 case MMX_PADDSWrm:
4879 case MMX_PADDSWrr:
4880 case PADDSWrm:
4881 case PADDSWrr:
4882 return true;
4883 }
4884 return false;
4885}
4886
4887bool isXSUSLDTRK(unsigned Opcode) {
4888 return Opcode == XSUSLDTRK;
4889}
4890
4891bool isLFENCE(unsigned Opcode) {
4892 return Opcode == LFENCE;
4893}
4894
4895bool isCRC32(unsigned Opcode) {
4896 switch (Opcode) {
4897 case CRC32r32m16:
4898 case CRC32r32m16_EVEX:
4899 case CRC32r32m32:
4900 case CRC32r32m32_EVEX:
4901 case CRC32r32m8:
4902 case CRC32r32m8_EVEX:
4903 case CRC32r32r16:
4904 case CRC32r32r16_EVEX:
4905 case CRC32r32r32:
4906 case CRC32r32r32_EVEX:
4907 case CRC32r32r8:
4908 case CRC32r32r8_EVEX:
4909 case CRC32r64m64:
4910 case CRC32r64m64_EVEX:
4911 case CRC32r64m8:
4912 case CRC32r64m8_EVEX:
4913 case CRC32r64r64:
4914 case CRC32r64r64_EVEX:
4915 case CRC32r64r8:
4916 case CRC32r64r8_EVEX:
4917 return true;
4918 }
4919 return false;
4920}
4921
4922bool isAESENCWIDE256KL(unsigned Opcode) {
4923 return Opcode == AESENCWIDE256KL;
4924}
4925
4926bool isMOVAPD(unsigned Opcode) {
4927 switch (Opcode) {
4928 case MOVAPDmr:
4929 case MOVAPDrm:
4930 case MOVAPDrr:
4931 case MOVAPDrr_REV:
4932 return true;
4933 }
4934 return false;
4935}
4936
4937bool isVFMADD213PS(unsigned Opcode) {
4938 switch (Opcode) {
4939 case VFMADD213PSYm:
4940 case VFMADD213PSYr:
4941 case VFMADD213PSZ128m:
4942 case VFMADD213PSZ128mb:
4943 case VFMADD213PSZ128mbk:
4944 case VFMADD213PSZ128mbkz:
4945 case VFMADD213PSZ128mk:
4946 case VFMADD213PSZ128mkz:
4947 case VFMADD213PSZ128r:
4948 case VFMADD213PSZ128rk:
4949 case VFMADD213PSZ128rkz:
4950 case VFMADD213PSZ256m:
4951 case VFMADD213PSZ256mb:
4952 case VFMADD213PSZ256mbk:
4953 case VFMADD213PSZ256mbkz:
4954 case VFMADD213PSZ256mk:
4955 case VFMADD213PSZ256mkz:
4956 case VFMADD213PSZ256r:
4957 case VFMADD213PSZ256rk:
4958 case VFMADD213PSZ256rkz:
4959 case VFMADD213PSZm:
4960 case VFMADD213PSZmb:
4961 case VFMADD213PSZmbk:
4962 case VFMADD213PSZmbkz:
4963 case VFMADD213PSZmk:
4964 case VFMADD213PSZmkz:
4965 case VFMADD213PSZr:
4966 case VFMADD213PSZrb:
4967 case VFMADD213PSZrbk:
4968 case VFMADD213PSZrbkz:
4969 case VFMADD213PSZrk:
4970 case VFMADD213PSZrkz:
4971 case VFMADD213PSm:
4972 case VFMADD213PSr:
4973 return true;
4974 }
4975 return false;
4976}
4977
4978bool isVPDPWUUDS(unsigned Opcode) {
4979 switch (Opcode) {
4980 case VPDPWUUDSYrm:
4981 case VPDPWUUDSYrr:
4982 case VPDPWUUDSrm:
4983 case VPDPWUUDSrr:
4984 return true;
4985 }
4986 return false;
4987}
4988
4989bool isMOVSLDUP(unsigned Opcode) {
4990 switch (Opcode) {
4991 case MOVSLDUPrm:
4992 case MOVSLDUPrr:
4993 return true;
4994 }
4995 return false;
4996}
4997
4998bool isCLDEMOTE(unsigned Opcode) {
4999 return Opcode == CLDEMOTE;
5000}
5001
5002bool isVFNMADD231PS(unsigned Opcode) {
5003 switch (Opcode) {
5004 case VFNMADD231PSYm:
5005 case VFNMADD231PSYr:
5006 case VFNMADD231PSZ128m:
5007 case VFNMADD231PSZ128mb:
5008 case VFNMADD231PSZ128mbk:
5009 case VFNMADD231PSZ128mbkz:
5010 case VFNMADD231PSZ128mk:
5011 case VFNMADD231PSZ128mkz:
5012 case VFNMADD231PSZ128r:
5013 case VFNMADD231PSZ128rk:
5014 case VFNMADD231PSZ128rkz:
5015 case VFNMADD231PSZ256m:
5016 case VFNMADD231PSZ256mb:
5017 case VFNMADD231PSZ256mbk:
5018 case VFNMADD231PSZ256mbkz:
5019 case VFNMADD231PSZ256mk:
5020 case VFNMADD231PSZ256mkz:
5021 case VFNMADD231PSZ256r:
5022 case VFNMADD231PSZ256rk:
5023 case VFNMADD231PSZ256rkz:
5024 case VFNMADD231PSZm:
5025 case VFNMADD231PSZmb:
5026 case VFNMADD231PSZmbk:
5027 case VFNMADD231PSZmbkz:
5028 case VFNMADD231PSZmk:
5029 case VFNMADD231PSZmkz:
5030 case VFNMADD231PSZr:
5031 case VFNMADD231PSZrb:
5032 case VFNMADD231PSZrbk:
5033 case VFNMADD231PSZrbkz:
5034 case VFNMADD231PSZrk:
5035 case VFNMADD231PSZrkz:
5036 case VFNMADD231PSm:
5037 case VFNMADD231PSr:
5038 return true;
5039 }
5040 return false;
5041}
5042
5043bool isVMOVMSKPD(unsigned Opcode) {
5044 switch (Opcode) {
5045 case VMOVMSKPDYrr:
5046 case VMOVMSKPDrr:
5047 return true;
5048 }
5049 return false;
5050}
5051
5052bool isPREFETCHT0(unsigned Opcode) {
5053 return Opcode == PREFETCHT0;
5054}
5055
5056bool isVCVTNEOBF162PS(unsigned Opcode) {
5057 switch (Opcode) {
5058 case VCVTNEOBF162PSYrm:
5059 case VCVTNEOBF162PSrm:
5060 return true;
5061 }
5062 return false;
5063}
5064
5065bool isVPCMPUD(unsigned Opcode) {
5066 switch (Opcode) {
5067 case VPCMPUDZ128rmi:
5068 case VPCMPUDZ128rmib:
5069 case VPCMPUDZ128rmibk:
5070 case VPCMPUDZ128rmik:
5071 case VPCMPUDZ128rri:
5072 case VPCMPUDZ128rrik:
5073 case VPCMPUDZ256rmi:
5074 case VPCMPUDZ256rmib:
5075 case VPCMPUDZ256rmibk:
5076 case VPCMPUDZ256rmik:
5077 case VPCMPUDZ256rri:
5078 case VPCMPUDZ256rrik:
5079 case VPCMPUDZrmi:
5080 case VPCMPUDZrmib:
5081 case VPCMPUDZrmibk:
5082 case VPCMPUDZrmik:
5083 case VPCMPUDZrri:
5084 case VPCMPUDZrrik:
5085 return true;
5086 }
5087 return false;
5088}
5089
5090bool isVMAXSD(unsigned Opcode) {
5091 switch (Opcode) {
5092 case VMAXSDZrm_Int:
5093 case VMAXSDZrm_Intk:
5094 case VMAXSDZrm_Intkz:
5095 case VMAXSDZrr_Int:
5096 case VMAXSDZrr_Intk:
5097 case VMAXSDZrr_Intkz:
5098 case VMAXSDZrrb_Int:
5099 case VMAXSDZrrb_Intk:
5100 case VMAXSDZrrb_Intkz:
5101 case VMAXSDrm_Int:
5102 case VMAXSDrr_Int:
5103 return true;
5104 }
5105 return false;
5106}
5107
5108bool isVRCP28SD(unsigned Opcode) {
5109 switch (Opcode) {
5110 case VRCP28SDZm:
5111 case VRCP28SDZmk:
5112 case VRCP28SDZmkz:
5113 case VRCP28SDZr:
5114 case VRCP28SDZrb:
5115 case VRCP28SDZrbk:
5116 case VRCP28SDZrbkz:
5117 case VRCP28SDZrk:
5118 case VRCP28SDZrkz:
5119 return true;
5120 }
5121 return false;
5122}
5123
5124bool isVMAXPS(unsigned Opcode) {
5125 switch (Opcode) {
5126 case VMAXPSYrm:
5127 case VMAXPSYrr:
5128 case VMAXPSZ128rm:
5129 case VMAXPSZ128rmb:
5130 case VMAXPSZ128rmbk:
5131 case VMAXPSZ128rmbkz:
5132 case VMAXPSZ128rmk:
5133 case VMAXPSZ128rmkz:
5134 case VMAXPSZ128rr:
5135 case VMAXPSZ128rrk:
5136 case VMAXPSZ128rrkz:
5137 case VMAXPSZ256rm:
5138 case VMAXPSZ256rmb:
5139 case VMAXPSZ256rmbk:
5140 case VMAXPSZ256rmbkz:
5141 case VMAXPSZ256rmk:
5142 case VMAXPSZ256rmkz:
5143 case VMAXPSZ256rr:
5144 case VMAXPSZ256rrk:
5145 case VMAXPSZ256rrkz:
5146 case VMAXPSZrm:
5147 case VMAXPSZrmb:
5148 case VMAXPSZrmbk:
5149 case VMAXPSZrmbkz:
5150 case VMAXPSZrmk:
5151 case VMAXPSZrmkz:
5152 case VMAXPSZrr:
5153 case VMAXPSZrrb:
5154 case VMAXPSZrrbk:
5155 case VMAXPSZrrbkz:
5156 case VMAXPSZrrk:
5157 case VMAXPSZrrkz:
5158 case VMAXPSrm:
5159 case VMAXPSrr:
5160 return true;
5161 }
5162 return false;
5163}
5164
5165bool isVPMOVD2M(unsigned Opcode) {
5166 switch (Opcode) {
5167 case VPMOVD2MZ128rr:
5168 case VPMOVD2MZ256rr:
5169 case VPMOVD2MZrr:
5170 return true;
5171 }
5172 return false;
5173}
5174
5175bool isVPMACSSWD(unsigned Opcode) {
5176 switch (Opcode) {
5177 case VPMACSSWDrm:
5178 case VPMACSSWDrr:
5179 return true;
5180 }
5181 return false;
5182}
5183
5184bool isVUCOMISD(unsigned Opcode) {
5185 switch (Opcode) {
5186 case VUCOMISDZrm:
5187 case VUCOMISDZrr:
5188 case VUCOMISDZrrb:
5189 case VUCOMISDrm:
5190 case VUCOMISDrr:
5191 return true;
5192 }
5193 return false;
5194}
5195
5196bool isLTR(unsigned Opcode) {
5197 switch (Opcode) {
5198 case LTRm:
5199 case LTRr:
5200 return true;
5201 }
5202 return false;
5203}
5204
5205bool isVCVTUSI2SH(unsigned Opcode) {
5206 switch (Opcode) {
5207 case VCVTUSI2SHZrm_Int:
5208 case VCVTUSI2SHZrr_Int:
5209 case VCVTUSI2SHZrrb_Int:
5210 case VCVTUSI642SHZrm_Int:
5211 case VCVTUSI642SHZrr_Int:
5212 case VCVTUSI642SHZrrb_Int:
5213 return true;
5214 }
5215 return false;
5216}
5217
5218bool isVSCATTERPF1QPS(unsigned Opcode) {
5219 return Opcode == VSCATTERPF1QPSm;
5220}
5221
5222bool isWRGSBASE(unsigned Opcode) {
5223 switch (Opcode) {
5224 case WRGSBASE:
5225 case WRGSBASE64:
5226 return true;
5227 }
5228 return false;
5229}
5230
5231bool isSTOSQ(unsigned Opcode) {
5232 return Opcode == STOSQ;
5233}
5234
5235bool isVSQRTSD(unsigned Opcode) {
5236 switch (Opcode) {
5237 case VSQRTSDZm_Int:
5238 case VSQRTSDZm_Intk:
5239 case VSQRTSDZm_Intkz:
5240 case VSQRTSDZr_Int:
5241 case VSQRTSDZr_Intk:
5242 case VSQRTSDZr_Intkz:
5243 case VSQRTSDZrb_Int:
5244 case VSQRTSDZrb_Intk:
5245 case VSQRTSDZrb_Intkz:
5246 case VSQRTSDm_Int:
5247 case VSQRTSDr_Int:
5248 return true;
5249 }
5250 return false;
5251}
5252
5253bool isVPERMIL2PD(unsigned Opcode) {
5254 switch (Opcode) {
5255 case VPERMIL2PDYmr:
5256 case VPERMIL2PDYrm:
5257 case VPERMIL2PDYrr:
5258 case VPERMIL2PDYrr_REV:
5259 case VPERMIL2PDmr:
5260 case VPERMIL2PDrm:
5261 case VPERMIL2PDrr:
5262 case VPERMIL2PDrr_REV:
5263 return true;
5264 }
5265 return false;
5266}
5267
5268bool isVFCMADDCSH(unsigned Opcode) {
5269 switch (Opcode) {
5270 case VFCMADDCSHZm:
5271 case VFCMADDCSHZmk:
5272 case VFCMADDCSHZmkz:
5273 case VFCMADDCSHZr:
5274 case VFCMADDCSHZrb:
5275 case VFCMADDCSHZrbk:
5276 case VFCMADDCSHZrbkz:
5277 case VFCMADDCSHZrk:
5278 case VFCMADDCSHZrkz:
5279 return true;
5280 }
5281 return false;
5282}
5283
5284bool isVFMADDSUB213PS(unsigned Opcode) {
5285 switch (Opcode) {
5286 case VFMADDSUB213PSYm:
5287 case VFMADDSUB213PSYr:
5288 case VFMADDSUB213PSZ128m:
5289 case VFMADDSUB213PSZ128mb:
5290 case VFMADDSUB213PSZ128mbk:
5291 case VFMADDSUB213PSZ128mbkz:
5292 case VFMADDSUB213PSZ128mk:
5293 case VFMADDSUB213PSZ128mkz:
5294 case VFMADDSUB213PSZ128r:
5295 case VFMADDSUB213PSZ128rk:
5296 case VFMADDSUB213PSZ128rkz:
5297 case VFMADDSUB213PSZ256m:
5298 case VFMADDSUB213PSZ256mb:
5299 case VFMADDSUB213PSZ256mbk:
5300 case VFMADDSUB213PSZ256mbkz:
5301 case VFMADDSUB213PSZ256mk:
5302 case VFMADDSUB213PSZ256mkz:
5303 case VFMADDSUB213PSZ256r:
5304 case VFMADDSUB213PSZ256rk:
5305 case VFMADDSUB213PSZ256rkz:
5306 case VFMADDSUB213PSZm:
5307 case VFMADDSUB213PSZmb:
5308 case VFMADDSUB213PSZmbk:
5309 case VFMADDSUB213PSZmbkz:
5310 case VFMADDSUB213PSZmk:
5311 case VFMADDSUB213PSZmkz:
5312 case VFMADDSUB213PSZr:
5313 case VFMADDSUB213PSZrb:
5314 case VFMADDSUB213PSZrbk:
5315 case VFMADDSUB213PSZrbkz:
5316 case VFMADDSUB213PSZrk:
5317 case VFMADDSUB213PSZrkz:
5318 case VFMADDSUB213PSm:
5319 case VFMADDSUB213PSr:
5320 return true;
5321 }
5322 return false;
5323}
5324
5325bool isPFSUB(unsigned Opcode) {
5326 switch (Opcode) {
5327 case PFSUBrm:
5328 case PFSUBrr:
5329 return true;
5330 }
5331 return false;
5332}
5333
5334bool isVSQRTSS(unsigned Opcode) {
5335 switch (Opcode) {
5336 case VSQRTSSZm_Int:
5337 case VSQRTSSZm_Intk:
5338 case VSQRTSSZm_Intkz:
5339 case VSQRTSSZr_Int:
5340 case VSQRTSSZr_Intk:
5341 case VSQRTSSZr_Intkz:
5342 case VSQRTSSZrb_Int:
5343 case VSQRTSSZrb_Intk:
5344 case VSQRTSSZrb_Intkz:
5345 case VSQRTSSm_Int:
5346 case VSQRTSSr_Int:
5347 return true;
5348 }
5349 return false;
5350}
5351
5352bool isVEXPANDPS(unsigned Opcode) {
5353 switch (Opcode) {
5354 case VEXPANDPSZ128rm:
5355 case VEXPANDPSZ128rmk:
5356 case VEXPANDPSZ128rmkz:
5357 case VEXPANDPSZ128rr:
5358 case VEXPANDPSZ128rrk:
5359 case VEXPANDPSZ128rrkz:
5360 case VEXPANDPSZ256rm:
5361 case VEXPANDPSZ256rmk:
5362 case VEXPANDPSZ256rmkz:
5363 case VEXPANDPSZ256rr:
5364 case VEXPANDPSZ256rrk:
5365 case VEXPANDPSZ256rrkz:
5366 case VEXPANDPSZrm:
5367 case VEXPANDPSZrmk:
5368 case VEXPANDPSZrmkz:
5369 case VEXPANDPSZrr:
5370 case VEXPANDPSZrrk:
5371 case VEXPANDPSZrrkz:
5372 return true;
5373 }
5374 return false;
5375}
5376
5377bool isVPCOMPRESSW(unsigned Opcode) {
5378 switch (Opcode) {
5379 case VPCOMPRESSWZ128mr:
5380 case VPCOMPRESSWZ128mrk:
5381 case VPCOMPRESSWZ128rr:
5382 case VPCOMPRESSWZ128rrk:
5383 case VPCOMPRESSWZ128rrkz:
5384 case VPCOMPRESSWZ256mr:
5385 case VPCOMPRESSWZ256mrk:
5386 case VPCOMPRESSWZ256rr:
5387 case VPCOMPRESSWZ256rrk:
5388 case VPCOMPRESSWZ256rrkz:
5389 case VPCOMPRESSWZmr:
5390 case VPCOMPRESSWZmrk:
5391 case VPCOMPRESSWZrr:
5392 case VPCOMPRESSWZrrk:
5393 case VPCOMPRESSWZrrkz:
5394 return true;
5395 }
5396 return false;
5397}
5398
5399bool isPEXTRD(unsigned Opcode) {
5400 switch (Opcode) {
5401 case PEXTRDmr:
5402 case PEXTRDrr:
5403 return true;
5404 }
5405 return false;
5406}
5407
5408bool isSYSEXITQ(unsigned Opcode) {
5409 return Opcode == SYSEXIT64;
5410}
5411
5412bool isROUNDSD(unsigned Opcode) {
5413 switch (Opcode) {
5414 case ROUNDSDmi_Int:
5415 case ROUNDSDri_Int:
5416 return true;
5417 }
5418 return false;
5419}
5420
5421bool isFCOM(unsigned Opcode) {
5422 switch (Opcode) {
5423 case COM_FST0r:
5424 case FCOM32m:
5425 case FCOM64m:
5426 return true;
5427 }
5428 return false;
5429}
5430
5431bool isVFNMSUBSS(unsigned Opcode) {
5432 switch (Opcode) {
5433 case VFNMSUBSS4mr:
5434 case VFNMSUBSS4rm:
5435 case VFNMSUBSS4rr:
5436 case VFNMSUBSS4rr_REV:
5437 return true;
5438 }
5439 return false;
5440}
5441
5442bool isKSHIFTLW(unsigned Opcode) {
5443 return Opcode == KSHIFTLWri;
5444}
5445
5446bool isSCASD(unsigned Opcode) {
5447 return Opcode == SCASL;
5448}
5449
5450bool isVMPTRLD(unsigned Opcode) {
5451 return Opcode == VMPTRLDm;
5452}
5453
5454bool isVAESDECLAST(unsigned Opcode) {
5455 switch (Opcode) {
5456 case VAESDECLASTYrm:
5457 case VAESDECLASTYrr:
5458 case VAESDECLASTZ128rm:
5459 case VAESDECLASTZ128rr:
5460 case VAESDECLASTZ256rm:
5461 case VAESDECLASTZ256rr:
5462 case VAESDECLASTZrm:
5463 case VAESDECLASTZrr:
5464 case VAESDECLASTrm:
5465 case VAESDECLASTrr:
5466 return true;
5467 }
5468 return false;
5469}
5470
5471bool isVFMADDSUBPS(unsigned Opcode) {
5472 switch (Opcode) {
5473 case VFMADDSUBPS4Ymr:
5474 case VFMADDSUBPS4Yrm:
5475 case VFMADDSUBPS4Yrr:
5476 case VFMADDSUBPS4Yrr_REV:
5477 case VFMADDSUBPS4mr:
5478 case VFMADDSUBPS4rm:
5479 case VFMADDSUBPS4rr:
5480 case VFMADDSUBPS4rr_REV:
5481 return true;
5482 }
5483 return false;
5484}
5485
5486bool isVCVTUQQ2PS(unsigned Opcode) {
5487 switch (Opcode) {
5488 case VCVTUQQ2PSZ128rm:
5489 case VCVTUQQ2PSZ128rmb:
5490 case VCVTUQQ2PSZ128rmbk:
5491 case VCVTUQQ2PSZ128rmbkz:
5492 case VCVTUQQ2PSZ128rmk:
5493 case VCVTUQQ2PSZ128rmkz:
5494 case VCVTUQQ2PSZ128rr:
5495 case VCVTUQQ2PSZ128rrk:
5496 case VCVTUQQ2PSZ128rrkz:
5497 case VCVTUQQ2PSZ256rm:
5498 case VCVTUQQ2PSZ256rmb:
5499 case VCVTUQQ2PSZ256rmbk:
5500 case VCVTUQQ2PSZ256rmbkz:
5501 case VCVTUQQ2PSZ256rmk:
5502 case VCVTUQQ2PSZ256rmkz:
5503 case VCVTUQQ2PSZ256rr:
5504 case VCVTUQQ2PSZ256rrk:
5505 case VCVTUQQ2PSZ256rrkz:
5506 case VCVTUQQ2PSZrm:
5507 case VCVTUQQ2PSZrmb:
5508 case VCVTUQQ2PSZrmbk:
5509 case VCVTUQQ2PSZrmbkz:
5510 case VCVTUQQ2PSZrmk:
5511 case VCVTUQQ2PSZrmkz:
5512 case VCVTUQQ2PSZrr:
5513 case VCVTUQQ2PSZrrb:
5514 case VCVTUQQ2PSZrrbk:
5515 case VCVTUQQ2PSZrrbkz:
5516 case VCVTUQQ2PSZrrk:
5517 case VCVTUQQ2PSZrrkz:
5518 return true;
5519 }
5520 return false;
5521}
5522
5523bool isVPMOVUSDB(unsigned Opcode) {
5524 switch (Opcode) {
5525 case VPMOVUSDBZ128mr:
5526 case VPMOVUSDBZ128mrk:
5527 case VPMOVUSDBZ128rr:
5528 case VPMOVUSDBZ128rrk:
5529 case VPMOVUSDBZ128rrkz:
5530 case VPMOVUSDBZ256mr:
5531 case VPMOVUSDBZ256mrk:
5532 case VPMOVUSDBZ256rr:
5533 case VPMOVUSDBZ256rrk:
5534 case VPMOVUSDBZ256rrkz:
5535 case VPMOVUSDBZmr:
5536 case VPMOVUSDBZmrk:
5537 case VPMOVUSDBZrr:
5538 case VPMOVUSDBZrrk:
5539 case VPMOVUSDBZrrkz:
5540 return true;
5541 }
5542 return false;
5543}
5544
5545bool isVPROTW(unsigned Opcode) {
5546 switch (Opcode) {
5547 case VPROTWmi:
5548 case VPROTWmr:
5549 case VPROTWri:
5550 case VPROTWrm:
5551 case VPROTWrr:
5552 case VPROTWrr_REV:
5553 return true;
5554 }
5555 return false;
5556}
5557
5558bool isVDPPS(unsigned Opcode) {
5559 switch (Opcode) {
5560 case VDPPSYrmi:
5561 case VDPPSYrri:
5562 case VDPPSrmi:
5563 case VDPPSrri:
5564 return true;
5565 }
5566 return false;
5567}
5568
5569bool isVRSQRT14PD(unsigned Opcode) {
5570 switch (Opcode) {
5571 case VRSQRT14PDZ128m:
5572 case VRSQRT14PDZ128mb:
5573 case VRSQRT14PDZ128mbk:
5574 case VRSQRT14PDZ128mbkz:
5575 case VRSQRT14PDZ128mk:
5576 case VRSQRT14PDZ128mkz:
5577 case VRSQRT14PDZ128r:
5578 case VRSQRT14PDZ128rk:
5579 case VRSQRT14PDZ128rkz:
5580 case VRSQRT14PDZ256m:
5581 case VRSQRT14PDZ256mb:
5582 case VRSQRT14PDZ256mbk:
5583 case VRSQRT14PDZ256mbkz:
5584 case VRSQRT14PDZ256mk:
5585 case VRSQRT14PDZ256mkz:
5586 case VRSQRT14PDZ256r:
5587 case VRSQRT14PDZ256rk:
5588 case VRSQRT14PDZ256rkz:
5589 case VRSQRT14PDZm:
5590 case VRSQRT14PDZmb:
5591 case VRSQRT14PDZmbk:
5592 case VRSQRT14PDZmbkz:
5593 case VRSQRT14PDZmk:
5594 case VRSQRT14PDZmkz:
5595 case VRSQRT14PDZr:
5596 case VRSQRT14PDZrk:
5597 case VRSQRT14PDZrkz:
5598 return true;
5599 }
5600 return false;
5601}
5602
5603bool isVTESTPD(unsigned Opcode) {
5604 switch (Opcode) {
5605 case VTESTPDYrm:
5606 case VTESTPDYrr:
5607 case VTESTPDrm:
5608 case VTESTPDrr:
5609 return true;
5610 }
5611 return false;
5612}
5613
5614bool isVFNMADD231SH(unsigned Opcode) {
5615 switch (Opcode) {
5616 case VFNMADD231SHZm_Int:
5617 case VFNMADD231SHZm_Intk:
5618 case VFNMADD231SHZm_Intkz:
5619 case VFNMADD231SHZr_Int:
5620 case VFNMADD231SHZr_Intk:
5621 case VFNMADD231SHZr_Intkz:
5622 case VFNMADD231SHZrb_Int:
5623 case VFNMADD231SHZrb_Intk:
5624 case VFNMADD231SHZrb_Intkz:
5625 return true;
5626 }
5627 return false;
5628}
5629
5630bool isENDBR64(unsigned Opcode) {
5631 return Opcode == ENDBR64;
5632}
5633
5634bool isMULSD(unsigned Opcode) {
5635 switch (Opcode) {
5636 case MULSDrm_Int:
5637 case MULSDrr_Int:
5638 return true;
5639 }
5640 return false;
5641}
5642
5643bool isXRSTORS(unsigned Opcode) {
5644 return Opcode == XRSTORS;
5645}
5646
5647bool isPREFETCHNTA(unsigned Opcode) {
5648 return Opcode == PREFETCHNTA;
5649}
5650
5651bool isVPCOMD(unsigned Opcode) {
5652 switch (Opcode) {
5653 case VPCOMDmi:
5654 case VPCOMDri:
5655 return true;
5656 }
5657 return false;
5658}
5659
5660bool isVPCOMUB(unsigned Opcode) {
5661 switch (Opcode) {
5662 case VPCOMUBmi:
5663 case VPCOMUBri:
5664 return true;
5665 }
5666 return false;
5667}
5668
5669bool isVPHSUBD(unsigned Opcode) {
5670 switch (Opcode) {
5671 case VPHSUBDYrm:
5672 case VPHSUBDYrr:
5673 case VPHSUBDrm:
5674 case VPHSUBDrr:
5675 return true;
5676 }
5677 return false;
5678}
5679
5680bool isVBROADCASTI64X2(unsigned Opcode) {
5681 switch (Opcode) {
5682 case VBROADCASTI64X2Z128rm:
5683 case VBROADCASTI64X2Z128rmk:
5684 case VBROADCASTI64X2Z128rmkz:
5685 case VBROADCASTI64X2rm:
5686 case VBROADCASTI64X2rmk:
5687 case VBROADCASTI64X2rmkz:
5688 return true;
5689 }
5690 return false;
5691}
5692
5693bool isFPATAN(unsigned Opcode) {
5694 return Opcode == FPATAN;
5695}
5696
5697bool isLOOPE(unsigned Opcode) {
5698 return Opcode == LOOPE;
5699}
5700
5701bool isPCMPEQW(unsigned Opcode) {
5702 switch (Opcode) {
5703 case MMX_PCMPEQWrm:
5704 case MMX_PCMPEQWrr:
5705 case PCMPEQWrm:
5706 case PCMPEQWrr:
5707 return true;
5708 }
5709 return false;
5710}
5711
5712bool isVFMADDCSH(unsigned Opcode) {
5713 switch (Opcode) {
5714 case VFMADDCSHZm:
5715 case VFMADDCSHZmk:
5716 case VFMADDCSHZmkz:
5717 case VFMADDCSHZr:
5718 case VFMADDCSHZrb:
5719 case VFMADDCSHZrbk:
5720 case VFMADDCSHZrbkz:
5721 case VFMADDCSHZrk:
5722 case VFMADDCSHZrkz:
5723 return true;
5724 }
5725 return false;
5726}
5727
5728bool isVPDPBSSD(unsigned Opcode) {
5729 switch (Opcode) {
5730 case VPDPBSSDYrm:
5731 case VPDPBSSDYrr:
5732 case VPDPBSSDrm:
5733 case VPDPBSSDrr:
5734 return true;
5735 }
5736 return false;
5737}
5738
5739bool isVFMSUBADD132PH(unsigned Opcode) {
5740 switch (Opcode) {
5741 case VFMSUBADD132PHZ128m:
5742 case VFMSUBADD132PHZ128mb:
5743 case VFMSUBADD132PHZ128mbk:
5744 case VFMSUBADD132PHZ128mbkz:
5745 case VFMSUBADD132PHZ128mk:
5746 case VFMSUBADD132PHZ128mkz:
5747 case VFMSUBADD132PHZ128r:
5748 case VFMSUBADD132PHZ128rk:
5749 case VFMSUBADD132PHZ128rkz:
5750 case VFMSUBADD132PHZ256m:
5751 case VFMSUBADD132PHZ256mb:
5752 case VFMSUBADD132PHZ256mbk:
5753 case VFMSUBADD132PHZ256mbkz:
5754 case VFMSUBADD132PHZ256mk:
5755 case VFMSUBADD132PHZ256mkz:
5756 case VFMSUBADD132PHZ256r:
5757 case VFMSUBADD132PHZ256rk:
5758 case VFMSUBADD132PHZ256rkz:
5759 case VFMSUBADD132PHZm:
5760 case VFMSUBADD132PHZmb:
5761 case VFMSUBADD132PHZmbk:
5762 case VFMSUBADD132PHZmbkz:
5763 case VFMSUBADD132PHZmk:
5764 case VFMSUBADD132PHZmkz:
5765 case VFMSUBADD132PHZr:
5766 case VFMSUBADD132PHZrb:
5767 case VFMSUBADD132PHZrbk:
5768 case VFMSUBADD132PHZrbkz:
5769 case VFMSUBADD132PHZrk:
5770 case VFMSUBADD132PHZrkz:
5771 return true;
5772 }
5773 return false;
5774}
5775
5776bool isVPADDSB(unsigned Opcode) {
5777 switch (Opcode) {
5778 case VPADDSBYrm:
5779 case VPADDSBYrr:
5780 case VPADDSBZ128rm:
5781 case VPADDSBZ128rmk:
5782 case VPADDSBZ128rmkz:
5783 case VPADDSBZ128rr:
5784 case VPADDSBZ128rrk:
5785 case VPADDSBZ128rrkz:
5786 case VPADDSBZ256rm:
5787 case VPADDSBZ256rmk:
5788 case VPADDSBZ256rmkz:
5789 case VPADDSBZ256rr:
5790 case VPADDSBZ256rrk:
5791 case VPADDSBZ256rrkz:
5792 case VPADDSBZrm:
5793 case VPADDSBZrmk:
5794 case VPADDSBZrmkz:
5795 case VPADDSBZrr:
5796 case VPADDSBZrrk:
5797 case VPADDSBZrrkz:
5798 case VPADDSBrm:
5799 case VPADDSBrr:
5800 return true;
5801 }
5802 return false;
5803}
5804
5805bool isKADDW(unsigned Opcode) {
5806 return Opcode == KADDWrr;
5807}
5808
5809bool isPTEST(unsigned Opcode) {
5810 switch (Opcode) {
5811 case PTESTrm:
5812 case PTESTrr:
5813 return true;
5814 }
5815 return false;
5816}
5817
5818bool isVRSQRT28PS(unsigned Opcode) {
5819 switch (Opcode) {
5820 case VRSQRT28PSZm:
5821 case VRSQRT28PSZmb:
5822 case VRSQRT28PSZmbk:
5823 case VRSQRT28PSZmbkz:
5824 case VRSQRT28PSZmk:
5825 case VRSQRT28PSZmkz:
5826 case VRSQRT28PSZr:
5827 case VRSQRT28PSZrb:
5828 case VRSQRT28PSZrbk:
5829 case VRSQRT28PSZrbkz:
5830 case VRSQRT28PSZrk:
5831 case VRSQRT28PSZrkz:
5832 return true;
5833 }
5834 return false;
5835}
5836
5837bool isVGF2P8AFFINEINVQB(unsigned Opcode) {
5838 switch (Opcode) {
5839 case VGF2P8AFFINEINVQBYrmi:
5840 case VGF2P8AFFINEINVQBYrri:
5841 case VGF2P8AFFINEINVQBZ128rmbi:
5842 case VGF2P8AFFINEINVQBZ128rmbik:
5843 case VGF2P8AFFINEINVQBZ128rmbikz:
5844 case VGF2P8AFFINEINVQBZ128rmi:
5845 case VGF2P8AFFINEINVQBZ128rmik:
5846 case VGF2P8AFFINEINVQBZ128rmikz:
5847 case VGF2P8AFFINEINVQBZ128rri:
5848 case VGF2P8AFFINEINVQBZ128rrik:
5849 case VGF2P8AFFINEINVQBZ128rrikz:
5850 case VGF2P8AFFINEINVQBZ256rmbi:
5851 case VGF2P8AFFINEINVQBZ256rmbik:
5852 case VGF2P8AFFINEINVQBZ256rmbikz:
5853 case VGF2P8AFFINEINVQBZ256rmi:
5854 case VGF2P8AFFINEINVQBZ256rmik:
5855 case VGF2P8AFFINEINVQBZ256rmikz:
5856 case VGF2P8AFFINEINVQBZ256rri:
5857 case VGF2P8AFFINEINVQBZ256rrik:
5858 case VGF2P8AFFINEINVQBZ256rrikz:
5859 case VGF2P8AFFINEINVQBZrmbi:
5860 case VGF2P8AFFINEINVQBZrmbik:
5861 case VGF2P8AFFINEINVQBZrmbikz:
5862 case VGF2P8AFFINEINVQBZrmi:
5863 case VGF2P8AFFINEINVQBZrmik:
5864 case VGF2P8AFFINEINVQBZrmikz:
5865 case VGF2P8AFFINEINVQBZrri:
5866 case VGF2P8AFFINEINVQBZrrik:
5867 case VGF2P8AFFINEINVQBZrrikz:
5868 case VGF2P8AFFINEINVQBrmi:
5869 case VGF2P8AFFINEINVQBrri:
5870 return true;
5871 }
5872 return false;
5873}
5874
5875bool isSERIALIZE(unsigned Opcode) {
5876 return Opcode == SERIALIZE;
5877}
5878
5879bool isVPHADDWQ(unsigned Opcode) {
5880 switch (Opcode) {
5881 case VPHADDWQrm:
5882 case VPHADDWQrr:
5883 return true;
5884 }
5885 return false;
5886}
5887
5888bool isVRNDSCALESH(unsigned Opcode) {
5889 switch (Opcode) {
5890 case VRNDSCALESHZm_Int:
5891 case VRNDSCALESHZm_Intk:
5892 case VRNDSCALESHZm_Intkz:
5893 case VRNDSCALESHZr_Int:
5894 case VRNDSCALESHZr_Intk:
5895 case VRNDSCALESHZr_Intkz:
5896 case VRNDSCALESHZrb_Int:
5897 case VRNDSCALESHZrb_Intk:
5898 case VRNDSCALESHZrb_Intkz:
5899 return true;
5900 }
5901 return false;
5902}
5903
5904bool isAAA(unsigned Opcode) {
5905 return Opcode == AAA;
5906}
5907
5908bool isWRMSRLIST(unsigned Opcode) {
5909 return Opcode == WRMSRLIST;
5910}
5911
5912bool isXORPS(unsigned Opcode) {
5913 switch (Opcode) {
5914 case XORPSrm:
5915 case XORPSrr:
5916 return true;
5917 }
5918 return false;
5919}
5920
5921bool isVCVTPH2PSX(unsigned Opcode) {
5922 switch (Opcode) {
5923 case VCVTPH2PSXZ128rm:
5924 case VCVTPH2PSXZ128rmb:
5925 case VCVTPH2PSXZ128rmbk:
5926 case VCVTPH2PSXZ128rmbkz:
5927 case VCVTPH2PSXZ128rmk:
5928 case VCVTPH2PSXZ128rmkz:
5929 case VCVTPH2PSXZ128rr:
5930 case VCVTPH2PSXZ128rrk:
5931 case VCVTPH2PSXZ128rrkz:
5932 case VCVTPH2PSXZ256rm:
5933 case VCVTPH2PSXZ256rmb:
5934 case VCVTPH2PSXZ256rmbk:
5935 case VCVTPH2PSXZ256rmbkz:
5936 case VCVTPH2PSXZ256rmk:
5937 case VCVTPH2PSXZ256rmkz:
5938 case VCVTPH2PSXZ256rr:
5939 case VCVTPH2PSXZ256rrk:
5940 case VCVTPH2PSXZ256rrkz:
5941 case VCVTPH2PSXZrm:
5942 case VCVTPH2PSXZrmb:
5943 case VCVTPH2PSXZrmbk:
5944 case VCVTPH2PSXZrmbkz:
5945 case VCVTPH2PSXZrmk:
5946 case VCVTPH2PSXZrmkz:
5947 case VCVTPH2PSXZrr:
5948 case VCVTPH2PSXZrrb:
5949 case VCVTPH2PSXZrrbk:
5950 case VCVTPH2PSXZrrbkz:
5951 case VCVTPH2PSXZrrk:
5952 case VCVTPH2PSXZrrkz:
5953 return true;
5954 }
5955 return false;
5956}
5957
5958bool isVFMSUB231PH(unsigned Opcode) {
5959 switch (Opcode) {
5960 case VFMSUB231PHZ128m:
5961 case VFMSUB231PHZ128mb:
5962 case VFMSUB231PHZ128mbk:
5963 case VFMSUB231PHZ128mbkz:
5964 case VFMSUB231PHZ128mk:
5965 case VFMSUB231PHZ128mkz:
5966 case VFMSUB231PHZ128r:
5967 case VFMSUB231PHZ128rk:
5968 case VFMSUB231PHZ128rkz:
5969 case VFMSUB231PHZ256m:
5970 case VFMSUB231PHZ256mb:
5971 case VFMSUB231PHZ256mbk:
5972 case VFMSUB231PHZ256mbkz:
5973 case VFMSUB231PHZ256mk:
5974 case VFMSUB231PHZ256mkz:
5975 case VFMSUB231PHZ256r:
5976 case VFMSUB231PHZ256rk:
5977 case VFMSUB231PHZ256rkz:
5978 case VFMSUB231PHZm:
5979 case VFMSUB231PHZmb:
5980 case VFMSUB231PHZmbk:
5981 case VFMSUB231PHZmbkz:
5982 case VFMSUB231PHZmk:
5983 case VFMSUB231PHZmkz:
5984 case VFMSUB231PHZr:
5985 case VFMSUB231PHZrb:
5986 case VFMSUB231PHZrbk:
5987 case VFMSUB231PHZrbkz:
5988 case VFMSUB231PHZrk:
5989 case VFMSUB231PHZrkz:
5990 return true;
5991 }
5992 return false;
5993}
5994
5995bool isVGATHERQPD(unsigned Opcode) {
5996 switch (Opcode) {
5997 case VGATHERQPDYrm:
5998 case VGATHERQPDZ128rm:
5999 case VGATHERQPDZ256rm:
6000 case VGATHERQPDZrm:
6001 case VGATHERQPDrm:
6002 return true;
6003 }
6004 return false;
6005}
6006
6007bool isKADDB(unsigned Opcode) {
6008 return Opcode == KADDBrr;
6009}
6010
6011bool isCVTPD2PI(unsigned Opcode) {
6012 switch (Opcode) {
6013 case MMX_CVTPD2PIrm:
6014 case MMX_CVTPD2PIrr:
6015 return true;
6016 }
6017 return false;
6018}
6019
6020bool isVFNMSUB213PH(unsigned Opcode) {
6021 switch (Opcode) {
6022 case VFNMSUB213PHZ128m:
6023 case VFNMSUB213PHZ128mb:
6024 case VFNMSUB213PHZ128mbk:
6025 case VFNMSUB213PHZ128mbkz:
6026 case VFNMSUB213PHZ128mk:
6027 case VFNMSUB213PHZ128mkz:
6028 case VFNMSUB213PHZ128r:
6029 case VFNMSUB213PHZ128rk:
6030 case VFNMSUB213PHZ128rkz:
6031 case VFNMSUB213PHZ256m:
6032 case VFNMSUB213PHZ256mb:
6033 case VFNMSUB213PHZ256mbk:
6034 case VFNMSUB213PHZ256mbkz:
6035 case VFNMSUB213PHZ256mk:
6036 case VFNMSUB213PHZ256mkz:
6037 case VFNMSUB213PHZ256r:
6038 case VFNMSUB213PHZ256rk:
6039 case VFNMSUB213PHZ256rkz:
6040 case VFNMSUB213PHZm:
6041 case VFNMSUB213PHZmb:
6042 case VFNMSUB213PHZmbk:
6043 case VFNMSUB213PHZmbkz:
6044 case VFNMSUB213PHZmk:
6045 case VFNMSUB213PHZmkz:
6046 case VFNMSUB213PHZr:
6047 case VFNMSUB213PHZrb:
6048 case VFNMSUB213PHZrbk:
6049 case VFNMSUB213PHZrbkz:
6050 case VFNMSUB213PHZrk:
6051 case VFNMSUB213PHZrkz:
6052 return true;
6053 }
6054 return false;
6055}
6056
6057bool isVPCMPESTRI(unsigned Opcode) {
6058 switch (Opcode) {
6059 case VPCMPESTRIrmi:
6060 case VPCMPESTRIrri:
6061 return true;
6062 }
6063 return false;
6064}
6065
6066bool isVPSHRDW(unsigned Opcode) {
6067 switch (Opcode) {
6068 case VPSHRDWZ128rmi:
6069 case VPSHRDWZ128rmik:
6070 case VPSHRDWZ128rmikz:
6071 case VPSHRDWZ128rri:
6072 case VPSHRDWZ128rrik:
6073 case VPSHRDWZ128rrikz:
6074 case VPSHRDWZ256rmi:
6075 case VPSHRDWZ256rmik:
6076 case VPSHRDWZ256rmikz:
6077 case VPSHRDWZ256rri:
6078 case VPSHRDWZ256rrik:
6079 case VPSHRDWZ256rrikz:
6080 case VPSHRDWZrmi:
6081 case VPSHRDWZrmik:
6082 case VPSHRDWZrmikz:
6083 case VPSHRDWZrri:
6084 case VPSHRDWZrrik:
6085 case VPSHRDWZrrikz:
6086 return true;
6087 }
6088 return false;
6089}
6090
6091bool isPOP2(unsigned Opcode) {
6092 return Opcode == POP2;
6093}
6094
6095bool isRDMSRLIST(unsigned Opcode) {
6096 return Opcode == RDMSRLIST;
6097}
6098
6099bool isVPDPBUSD(unsigned Opcode) {
6100 switch (Opcode) {
6101 case VPDPBUSDYrm:
6102 case VPDPBUSDYrr:
6103 case VPDPBUSDZ128m:
6104 case VPDPBUSDZ128mb:
6105 case VPDPBUSDZ128mbk:
6106 case VPDPBUSDZ128mbkz:
6107 case VPDPBUSDZ128mk:
6108 case VPDPBUSDZ128mkz:
6109 case VPDPBUSDZ128r:
6110 case VPDPBUSDZ128rk:
6111 case VPDPBUSDZ128rkz:
6112 case VPDPBUSDZ256m:
6113 case VPDPBUSDZ256mb:
6114 case VPDPBUSDZ256mbk:
6115 case VPDPBUSDZ256mbkz:
6116 case VPDPBUSDZ256mk:
6117 case VPDPBUSDZ256mkz:
6118 case VPDPBUSDZ256r:
6119 case VPDPBUSDZ256rk:
6120 case VPDPBUSDZ256rkz:
6121 case VPDPBUSDZm:
6122 case VPDPBUSDZmb:
6123 case VPDPBUSDZmbk:
6124 case VPDPBUSDZmbkz:
6125 case VPDPBUSDZmk:
6126 case VPDPBUSDZmkz:
6127 case VPDPBUSDZr:
6128 case VPDPBUSDZrk:
6129 case VPDPBUSDZrkz:
6130 case VPDPBUSDrm:
6131 case VPDPBUSDrr:
6132 return true;
6133 }
6134 return false;
6135}
6136
6137bool isVCMPPH(unsigned Opcode) {
6138 switch (Opcode) {
6139 case VCMPPHZ128rmbi:
6140 case VCMPPHZ128rmbik:
6141 case VCMPPHZ128rmi:
6142 case VCMPPHZ128rmik:
6143 case VCMPPHZ128rri:
6144 case VCMPPHZ128rrik:
6145 case VCMPPHZ256rmbi:
6146 case VCMPPHZ256rmbik:
6147 case VCMPPHZ256rmi:
6148 case VCMPPHZ256rmik:
6149 case VCMPPHZ256rri:
6150 case VCMPPHZ256rrik:
6151 case VCMPPHZrmbi:
6152 case VCMPPHZrmbik:
6153 case VCMPPHZrmi:
6154 case VCMPPHZrmik:
6155 case VCMPPHZrri:
6156 case VCMPPHZrrib:
6157 case VCMPPHZrribk:
6158 case VCMPPHZrrik:
6159 return true;
6160 }
6161 return false;
6162}
6163
6164bool isVANDNPD(unsigned Opcode) {
6165 switch (Opcode) {
6166 case VANDNPDYrm:
6167 case VANDNPDYrr:
6168 case VANDNPDZ128rm:
6169 case VANDNPDZ128rmb:
6170 case VANDNPDZ128rmbk:
6171 case VANDNPDZ128rmbkz:
6172 case VANDNPDZ128rmk:
6173 case VANDNPDZ128rmkz:
6174 case VANDNPDZ128rr:
6175 case VANDNPDZ128rrk:
6176 case VANDNPDZ128rrkz:
6177 case VANDNPDZ256rm:
6178 case VANDNPDZ256rmb:
6179 case VANDNPDZ256rmbk:
6180 case VANDNPDZ256rmbkz:
6181 case VANDNPDZ256rmk:
6182 case VANDNPDZ256rmkz:
6183 case VANDNPDZ256rr:
6184 case VANDNPDZ256rrk:
6185 case VANDNPDZ256rrkz:
6186 case VANDNPDZrm:
6187 case VANDNPDZrmb:
6188 case VANDNPDZrmbk:
6189 case VANDNPDZrmbkz:
6190 case VANDNPDZrmk:
6191 case VANDNPDZrmkz:
6192 case VANDNPDZrr:
6193 case VANDNPDZrrk:
6194 case VANDNPDZrrkz:
6195 case VANDNPDrm:
6196 case VANDNPDrr:
6197 return true;
6198 }
6199 return false;
6200}
6201
6202bool isSUB(unsigned Opcode) {
6203 switch (Opcode) {
6204 case SUB16i16:
6205 case SUB16mi:
6206 case SUB16mi8:
6207 case SUB16mi8_EVEX:
6208 case SUB16mi8_ND:
6209 case SUB16mi8_NF:
6210 case SUB16mi8_NF_ND:
6211 case SUB16mi_EVEX:
6212 case SUB16mi_ND:
6213 case SUB16mi_NF:
6214 case SUB16mi_NF_ND:
6215 case SUB16mr:
6216 case SUB16mr_EVEX:
6217 case SUB16mr_ND:
6218 case SUB16mr_NF:
6219 case SUB16mr_NF_ND:
6220 case SUB16ri:
6221 case SUB16ri8:
6222 case SUB16ri8_EVEX:
6223 case SUB16ri8_ND:
6224 case SUB16ri8_NF:
6225 case SUB16ri8_NF_ND:
6226 case SUB16ri_EVEX:
6227 case SUB16ri_ND:
6228 case SUB16ri_NF:
6229 case SUB16ri_NF_ND:
6230 case SUB16rm:
6231 case SUB16rm_EVEX:
6232 case SUB16rm_ND:
6233 case SUB16rm_NF:
6234 case SUB16rm_NF_ND:
6235 case SUB16rr:
6236 case SUB16rr_EVEX:
6237 case SUB16rr_EVEX_REV:
6238 case SUB16rr_ND:
6239 case SUB16rr_ND_REV:
6240 case SUB16rr_NF:
6241 case SUB16rr_NF_ND:
6242 case SUB16rr_NF_ND_REV:
6243 case SUB16rr_NF_REV:
6244 case SUB16rr_REV:
6245 case SUB32i32:
6246 case SUB32mi:
6247 case SUB32mi8:
6248 case SUB32mi8_EVEX:
6249 case SUB32mi8_ND:
6250 case SUB32mi8_NF:
6251 case SUB32mi8_NF_ND:
6252 case SUB32mi_EVEX:
6253 case SUB32mi_ND:
6254 case SUB32mi_NF:
6255 case SUB32mi_NF_ND:
6256 case SUB32mr:
6257 case SUB32mr_EVEX:
6258 case SUB32mr_ND:
6259 case SUB32mr_NF:
6260 case SUB32mr_NF_ND:
6261 case SUB32ri:
6262 case SUB32ri8:
6263 case SUB32ri8_EVEX:
6264 case SUB32ri8_ND:
6265 case SUB32ri8_NF:
6266 case SUB32ri8_NF_ND:
6267 case SUB32ri_EVEX:
6268 case SUB32ri_ND:
6269 case SUB32ri_NF:
6270 case SUB32ri_NF_ND:
6271 case SUB32rm:
6272 case SUB32rm_EVEX:
6273 case SUB32rm_ND:
6274 case SUB32rm_NF:
6275 case SUB32rm_NF_ND:
6276 case SUB32rr:
6277 case SUB32rr_EVEX:
6278 case SUB32rr_EVEX_REV:
6279 case SUB32rr_ND:
6280 case SUB32rr_ND_REV:
6281 case SUB32rr_NF:
6282 case SUB32rr_NF_ND:
6283 case SUB32rr_NF_ND_REV:
6284 case SUB32rr_NF_REV:
6285 case SUB32rr_REV:
6286 case SUB64i32:
6287 case SUB64mi32:
6288 case SUB64mi32_EVEX:
6289 case SUB64mi32_ND:
6290 case SUB64mi32_NF:
6291 case SUB64mi32_NF_ND:
6292 case SUB64mi8:
6293 case SUB64mi8_EVEX:
6294 case SUB64mi8_ND:
6295 case SUB64mi8_NF:
6296 case SUB64mi8_NF_ND:
6297 case SUB64mr:
6298 case SUB64mr_EVEX:
6299 case SUB64mr_ND:
6300 case SUB64mr_NF:
6301 case SUB64mr_NF_ND:
6302 case SUB64ri32:
6303 case SUB64ri32_EVEX:
6304 case SUB64ri32_ND:
6305 case SUB64ri32_NF:
6306 case SUB64ri32_NF_ND:
6307 case SUB64ri8:
6308 case SUB64ri8_EVEX:
6309 case SUB64ri8_ND:
6310 case SUB64ri8_NF:
6311 case SUB64ri8_NF_ND:
6312 case SUB64rm:
6313 case SUB64rm_EVEX:
6314 case SUB64rm_ND:
6315 case SUB64rm_NF:
6316 case SUB64rm_NF_ND:
6317 case SUB64rr:
6318 case SUB64rr_EVEX:
6319 case SUB64rr_EVEX_REV:
6320 case SUB64rr_ND:
6321 case SUB64rr_ND_REV:
6322 case SUB64rr_NF:
6323 case SUB64rr_NF_ND:
6324 case SUB64rr_NF_ND_REV:
6325 case SUB64rr_NF_REV:
6326 case SUB64rr_REV:
6327 case SUB8i8:
6328 case SUB8mi:
6329 case SUB8mi8:
6330 case SUB8mi_EVEX:
6331 case SUB8mi_ND:
6332 case SUB8mi_NF:
6333 case SUB8mi_NF_ND:
6334 case SUB8mr:
6335 case SUB8mr_EVEX:
6336 case SUB8mr_ND:
6337 case SUB8mr_NF:
6338 case SUB8mr_NF_ND:
6339 case SUB8ri:
6340 case SUB8ri8:
6341 case SUB8ri_EVEX:
6342 case SUB8ri_ND:
6343 case SUB8ri_NF:
6344 case SUB8ri_NF_ND:
6345 case SUB8rm:
6346 case SUB8rm_EVEX:
6347 case SUB8rm_ND:
6348 case SUB8rm_NF:
6349 case SUB8rm_NF_ND:
6350 case SUB8rr:
6351 case SUB8rr_EVEX:
6352 case SUB8rr_EVEX_REV:
6353 case SUB8rr_ND:
6354 case SUB8rr_ND_REV:
6355 case SUB8rr_NF:
6356 case SUB8rr_NF_ND:
6357 case SUB8rr_NF_ND_REV:
6358 case SUB8rr_NF_REV:
6359 case SUB8rr_REV:
6360 return true;
6361 }
6362 return false;
6363}
6364
6365bool isVRSQRT28PD(unsigned Opcode) {
6366 switch (Opcode) {
6367 case VRSQRT28PDZm:
6368 case VRSQRT28PDZmb:
6369 case VRSQRT28PDZmbk:
6370 case VRSQRT28PDZmbkz:
6371 case VRSQRT28PDZmk:
6372 case VRSQRT28PDZmkz:
6373 case VRSQRT28PDZr:
6374 case VRSQRT28PDZrb:
6375 case VRSQRT28PDZrbk:
6376 case VRSQRT28PDZrbkz:
6377 case VRSQRT28PDZrk:
6378 case VRSQRT28PDZrkz:
6379 return true;
6380 }
6381 return false;
6382}
6383
6384bool isVFNMADD132PH(unsigned Opcode) {
6385 switch (Opcode) {
6386 case VFNMADD132PHZ128m:
6387 case VFNMADD132PHZ128mb:
6388 case VFNMADD132PHZ128mbk:
6389 case VFNMADD132PHZ128mbkz:
6390 case VFNMADD132PHZ128mk:
6391 case VFNMADD132PHZ128mkz:
6392 case VFNMADD132PHZ128r:
6393 case VFNMADD132PHZ128rk:
6394 case VFNMADD132PHZ128rkz:
6395 case VFNMADD132PHZ256m:
6396 case VFNMADD132PHZ256mb:
6397 case VFNMADD132PHZ256mbk:
6398 case VFNMADD132PHZ256mbkz:
6399 case VFNMADD132PHZ256mk:
6400 case VFNMADD132PHZ256mkz:
6401 case VFNMADD132PHZ256r:
6402 case VFNMADD132PHZ256rk:
6403 case VFNMADD132PHZ256rkz:
6404 case VFNMADD132PHZm:
6405 case VFNMADD132PHZmb:
6406 case VFNMADD132PHZmbk:
6407 case VFNMADD132PHZmbkz:
6408 case VFNMADD132PHZmk:
6409 case VFNMADD132PHZmkz:
6410 case VFNMADD132PHZr:
6411 case VFNMADD132PHZrb:
6412 case VFNMADD132PHZrbk:
6413 case VFNMADD132PHZrbkz:
6414 case VFNMADD132PHZrk:
6415 case VFNMADD132PHZrkz:
6416 return true;
6417 }
6418 return false;
6419}
6420
6421bool isVPMACSSWW(unsigned Opcode) {
6422 switch (Opcode) {
6423 case VPMACSSWWrm:
6424 case VPMACSSWWrr:
6425 return true;
6426 }
6427 return false;
6428}
6429
6430bool isXSTORE(unsigned Opcode) {
6431 return Opcode == XSTORE;
6432}
6433
6434bool isVPROTQ(unsigned Opcode) {
6435 switch (Opcode) {
6436 case VPROTQmi:
6437 case VPROTQmr:
6438 case VPROTQri:
6439 case VPROTQrm:
6440 case VPROTQrr:
6441 case VPROTQrr_REV:
6442 return true;
6443 }
6444 return false;
6445}
6446
6447bool isVPHADDBD(unsigned Opcode) {
6448 switch (Opcode) {
6449 case VPHADDBDrm:
6450 case VPHADDBDrr:
6451 return true;
6452 }
6453 return false;
6454}
6455
6456bool isVPMAXSB(unsigned Opcode) {
6457 switch (Opcode) {
6458 case VPMAXSBYrm:
6459 case VPMAXSBYrr:
6460 case VPMAXSBZ128rm:
6461 case VPMAXSBZ128rmk:
6462 case VPMAXSBZ128rmkz:
6463 case VPMAXSBZ128rr:
6464 case VPMAXSBZ128rrk:
6465 case VPMAXSBZ128rrkz:
6466 case VPMAXSBZ256rm:
6467 case VPMAXSBZ256rmk:
6468 case VPMAXSBZ256rmkz:
6469 case VPMAXSBZ256rr:
6470 case VPMAXSBZ256rrk:
6471 case VPMAXSBZ256rrkz:
6472 case VPMAXSBZrm:
6473 case VPMAXSBZrmk:
6474 case VPMAXSBZrmkz:
6475 case VPMAXSBZrr:
6476 case VPMAXSBZrrk:
6477 case VPMAXSBZrrkz:
6478 case VPMAXSBrm:
6479 case VPMAXSBrr:
6480 return true;
6481 }
6482 return false;
6483}
6484
6485bool isVMOVDQU8(unsigned Opcode) {
6486 switch (Opcode) {
6487 case VMOVDQU8Z128mr:
6488 case VMOVDQU8Z128mrk:
6489 case VMOVDQU8Z128rm:
6490 case VMOVDQU8Z128rmk:
6491 case VMOVDQU8Z128rmkz:
6492 case VMOVDQU8Z128rr:
6493 case VMOVDQU8Z128rr_REV:
6494 case VMOVDQU8Z128rrk:
6495 case VMOVDQU8Z128rrk_REV:
6496 case VMOVDQU8Z128rrkz:
6497 case VMOVDQU8Z128rrkz_REV:
6498 case VMOVDQU8Z256mr:
6499 case VMOVDQU8Z256mrk:
6500 case VMOVDQU8Z256rm:
6501 case VMOVDQU8Z256rmk:
6502 case VMOVDQU8Z256rmkz:
6503 case VMOVDQU8Z256rr:
6504 case VMOVDQU8Z256rr_REV:
6505 case VMOVDQU8Z256rrk:
6506 case VMOVDQU8Z256rrk_REV:
6507 case VMOVDQU8Z256rrkz:
6508 case VMOVDQU8Z256rrkz_REV:
6509 case VMOVDQU8Zmr:
6510 case VMOVDQU8Zmrk:
6511 case VMOVDQU8Zrm:
6512 case VMOVDQU8Zrmk:
6513 case VMOVDQU8Zrmkz:
6514 case VMOVDQU8Zrr:
6515 case VMOVDQU8Zrr_REV:
6516 case VMOVDQU8Zrrk:
6517 case VMOVDQU8Zrrk_REV:
6518 case VMOVDQU8Zrrkz:
6519 case VMOVDQU8Zrrkz_REV:
6520 return true;
6521 }
6522 return false;
6523}
6524
6525bool isVPMOVSXWD(unsigned Opcode) {
6526 switch (Opcode) {
6527 case VPMOVSXWDYrm:
6528 case VPMOVSXWDYrr:
6529 case VPMOVSXWDZ128rm:
6530 case VPMOVSXWDZ128rmk:
6531 case VPMOVSXWDZ128rmkz:
6532 case VPMOVSXWDZ128rr:
6533 case VPMOVSXWDZ128rrk:
6534 case VPMOVSXWDZ128rrkz:
6535 case VPMOVSXWDZ256rm:
6536 case VPMOVSXWDZ256rmk:
6537 case VPMOVSXWDZ256rmkz:
6538 case VPMOVSXWDZ256rr:
6539 case VPMOVSXWDZ256rrk:
6540 case VPMOVSXWDZ256rrkz:
6541 case VPMOVSXWDZrm:
6542 case VPMOVSXWDZrmk:
6543 case VPMOVSXWDZrmkz:
6544 case VPMOVSXWDZrr:
6545 case VPMOVSXWDZrrk:
6546 case VPMOVSXWDZrrkz:
6547 case VPMOVSXWDrm:
6548 case VPMOVSXWDrr:
6549 return true;
6550 }
6551 return false;
6552}
6553
6554bool isSHA256RNDS2(unsigned Opcode) {
6555 switch (Opcode) {
6556 case SHA256RNDS2rm:
6557 case SHA256RNDS2rr:
6558 return true;
6559 }
6560 return false;
6561}
6562
6563bool isKANDB(unsigned Opcode) {
6564 return Opcode == KANDBrr;
6565}
6566
6567bool isTPAUSE(unsigned Opcode) {
6568 return Opcode == TPAUSE;
6569}
6570
6571bool isPUSH(unsigned Opcode) {
6572 switch (Opcode) {
6573 case PUSH16i:
6574 case PUSH16i8:
6575 case PUSH16r:
6576 case PUSH16rmm:
6577 case PUSH16rmr:
6578 case PUSH32i:
6579 case PUSH32i8:
6580 case PUSH32r:
6581 case PUSH32rmm:
6582 case PUSH32rmr:
6583 case PUSH64i32:
6584 case PUSH64i8:
6585 case PUSH64r:
6586 case PUSH64rmm:
6587 case PUSH64rmr:
6588 case PUSHCS16:
6589 case PUSHCS32:
6590 case PUSHDS16:
6591 case PUSHDS32:
6592 case PUSHES16:
6593 case PUSHES32:
6594 case PUSHFS16:
6595 case PUSHFS32:
6596 case PUSHFS64:
6597 case PUSHGS16:
6598 case PUSHGS32:
6599 case PUSHGS64:
6600 case PUSHSS16:
6601 case PUSHSS32:
6602 return true;
6603 }
6604 return false;
6605}
6606
6607bool isVRNDSCALESS(unsigned Opcode) {
6608 switch (Opcode) {
6609 case VRNDSCALESSZm_Int:
6610 case VRNDSCALESSZm_Intk:
6611 case VRNDSCALESSZm_Intkz:
6612 case VRNDSCALESSZr_Int:
6613 case VRNDSCALESSZr_Intk:
6614 case VRNDSCALESSZr_Intkz:
6615 case VRNDSCALESSZrb_Int:
6616 case VRNDSCALESSZrb_Intk:
6617 case VRNDSCALESSZrb_Intkz:
6618 return true;
6619 }
6620 return false;
6621}
6622
6623bool isVPCMPISTRI(unsigned Opcode) {
6624 switch (Opcode) {
6625 case VPCMPISTRIrmi:
6626 case VPCMPISTRIrri:
6627 return true;
6628 }
6629 return false;
6630}
6631
6632bool isSTGI(unsigned Opcode) {
6633 return Opcode == STGI;
6634}
6635
6636bool isSBB(unsigned Opcode) {
6637 switch (Opcode) {
6638 case SBB16i16:
6639 case SBB16mi:
6640 case SBB16mi8:
6641 case SBB16mi8_EVEX:
6642 case SBB16mi8_ND:
6643 case SBB16mi_EVEX:
6644 case SBB16mi_ND:
6645 case SBB16mr:
6646 case SBB16mr_EVEX:
6647 case SBB16mr_ND:
6648 case SBB16ri:
6649 case SBB16ri8:
6650 case SBB16ri8_EVEX:
6651 case SBB16ri8_ND:
6652 case SBB16ri_EVEX:
6653 case SBB16ri_ND:
6654 case SBB16rm:
6655 case SBB16rm_EVEX:
6656 case SBB16rm_ND:
6657 case SBB16rr:
6658 case SBB16rr_EVEX:
6659 case SBB16rr_EVEX_REV:
6660 case SBB16rr_ND:
6661 case SBB16rr_ND_REV:
6662 case SBB16rr_REV:
6663 case SBB32i32:
6664 case SBB32mi:
6665 case SBB32mi8:
6666 case SBB32mi8_EVEX:
6667 case SBB32mi8_ND:
6668 case SBB32mi_EVEX:
6669 case SBB32mi_ND:
6670 case SBB32mr:
6671 case SBB32mr_EVEX:
6672 case SBB32mr_ND:
6673 case SBB32ri:
6674 case SBB32ri8:
6675 case SBB32ri8_EVEX:
6676 case SBB32ri8_ND:
6677 case SBB32ri_EVEX:
6678 case SBB32ri_ND:
6679 case SBB32rm:
6680 case SBB32rm_EVEX:
6681 case SBB32rm_ND:
6682 case SBB32rr:
6683 case SBB32rr_EVEX:
6684 case SBB32rr_EVEX_REV:
6685 case SBB32rr_ND:
6686 case SBB32rr_ND_REV:
6687 case SBB32rr_REV:
6688 case SBB64i32:
6689 case SBB64mi32:
6690 case SBB64mi32_EVEX:
6691 case SBB64mi32_ND:
6692 case SBB64mi8:
6693 case SBB64mi8_EVEX:
6694 case SBB64mi8_ND:
6695 case SBB64mr:
6696 case SBB64mr_EVEX:
6697 case SBB64mr_ND:
6698 case SBB64ri32:
6699 case SBB64ri32_EVEX:
6700 case SBB64ri32_ND:
6701 case SBB64ri8:
6702 case SBB64ri8_EVEX:
6703 case SBB64ri8_ND:
6704 case SBB64rm:
6705 case SBB64rm_EVEX:
6706 case SBB64rm_ND:
6707 case SBB64rr:
6708 case SBB64rr_EVEX:
6709 case SBB64rr_EVEX_REV:
6710 case SBB64rr_ND:
6711 case SBB64rr_ND_REV:
6712 case SBB64rr_REV:
6713 case SBB8i8:
6714 case SBB8mi:
6715 case SBB8mi8:
6716 case SBB8mi_EVEX:
6717 case SBB8mi_ND:
6718 case SBB8mr:
6719 case SBB8mr_EVEX:
6720 case SBB8mr_ND:
6721 case SBB8ri:
6722 case SBB8ri8:
6723 case SBB8ri_EVEX:
6724 case SBB8ri_ND:
6725 case SBB8rm:
6726 case SBB8rm_EVEX:
6727 case SBB8rm_ND:
6728 case SBB8rr:
6729 case SBB8rr_EVEX:
6730 case SBB8rr_EVEX_REV:
6731 case SBB8rr_ND:
6732 case SBB8rr_ND_REV:
6733 case SBB8rr_REV:
6734 return true;
6735 }
6736 return false;
6737}
6738
6739bool isBLCS(unsigned Opcode) {
6740 switch (Opcode) {
6741 case BLCS32rm:
6742 case BLCS32rr:
6743 case BLCS64rm:
6744 case BLCS64rr:
6745 return true;
6746 }
6747 return false;
6748}
6749
6750bool isVCVTSD2SH(unsigned Opcode) {
6751 switch (Opcode) {
6752 case VCVTSD2SHZrm_Int:
6753 case VCVTSD2SHZrm_Intk:
6754 case VCVTSD2SHZrm_Intkz:
6755 case VCVTSD2SHZrr_Int:
6756 case VCVTSD2SHZrr_Intk:
6757 case VCVTSD2SHZrr_Intkz:
6758 case VCVTSD2SHZrrb_Int:
6759 case VCVTSD2SHZrrb_Intk:
6760 case VCVTSD2SHZrrb_Intkz:
6761 return true;
6762 }
6763 return false;
6764}
6765
6766bool isVPERMW(unsigned Opcode) {
6767 switch (Opcode) {
6768 case VPERMWZ128rm:
6769 case VPERMWZ128rmk:
6770 case VPERMWZ128rmkz:
6771 case VPERMWZ128rr:
6772 case VPERMWZ128rrk:
6773 case VPERMWZ128rrkz:
6774 case VPERMWZ256rm:
6775 case VPERMWZ256rmk:
6776 case VPERMWZ256rmkz:
6777 case VPERMWZ256rr:
6778 case VPERMWZ256rrk:
6779 case VPERMWZ256rrkz:
6780 case VPERMWZrm:
6781 case VPERMWZrmk:
6782 case VPERMWZrmkz:
6783 case VPERMWZrr:
6784 case VPERMWZrrk:
6785 case VPERMWZrrkz:
6786 return true;
6787 }
6788 return false;
6789}
6790
6791bool isXRESLDTRK(unsigned Opcode) {
6792 return Opcode == XRESLDTRK;
6793}
6794
6795bool isAESENC256KL(unsigned Opcode) {
6796 return Opcode == AESENC256KL;
6797}
6798
6799bool isVGATHERDPD(unsigned Opcode) {
6800 switch (Opcode) {
6801 case VGATHERDPDYrm:
6802 case VGATHERDPDZ128rm:
6803 case VGATHERDPDZ256rm:
6804 case VGATHERDPDZrm:
6805 case VGATHERDPDrm:
6806 return true;
6807 }
6808 return false;
6809}
6810
6811bool isHRESET(unsigned Opcode) {
6812 return Opcode == HRESET;
6813}
6814
6815bool isVFMSUBADD231PD(unsigned Opcode) {
6816 switch (Opcode) {
6817 case VFMSUBADD231PDYm:
6818 case VFMSUBADD231PDYr:
6819 case VFMSUBADD231PDZ128m:
6820 case VFMSUBADD231PDZ128mb:
6821 case VFMSUBADD231PDZ128mbk:
6822 case VFMSUBADD231PDZ128mbkz:
6823 case VFMSUBADD231PDZ128mk:
6824 case VFMSUBADD231PDZ128mkz:
6825 case VFMSUBADD231PDZ128r:
6826 case VFMSUBADD231PDZ128rk:
6827 case VFMSUBADD231PDZ128rkz:
6828 case VFMSUBADD231PDZ256m:
6829 case VFMSUBADD231PDZ256mb:
6830 case VFMSUBADD231PDZ256mbk:
6831 case VFMSUBADD231PDZ256mbkz:
6832 case VFMSUBADD231PDZ256mk:
6833 case VFMSUBADD231PDZ256mkz:
6834 case VFMSUBADD231PDZ256r:
6835 case VFMSUBADD231PDZ256rk:
6836 case VFMSUBADD231PDZ256rkz:
6837 case VFMSUBADD231PDZm:
6838 case VFMSUBADD231PDZmb:
6839 case VFMSUBADD231PDZmbk:
6840 case VFMSUBADD231PDZmbkz:
6841 case VFMSUBADD231PDZmk:
6842 case VFMSUBADD231PDZmkz:
6843 case VFMSUBADD231PDZr:
6844 case VFMSUBADD231PDZrb:
6845 case VFMSUBADD231PDZrbk:
6846 case VFMSUBADD231PDZrbkz:
6847 case VFMSUBADD231PDZrk:
6848 case VFMSUBADD231PDZrkz:
6849 case VFMSUBADD231PDm:
6850 case VFMSUBADD231PDr:
6851 return true;
6852 }
6853 return false;
6854}
6855
6856bool isVFRCZSS(unsigned Opcode) {
6857 switch (Opcode) {
6858 case VFRCZSSrm:
6859 case VFRCZSSrr:
6860 return true;
6861 }
6862 return false;
6863}
6864
6865bool isMINPS(unsigned Opcode) {
6866 switch (Opcode) {
6867 case MINPSrm:
6868 case MINPSrr:
6869 return true;
6870 }
6871 return false;
6872}
6873
6874bool isFPREM1(unsigned Opcode) {
6875 return Opcode == FPREM1;
6876}
6877
6878bool isVPCMPUB(unsigned Opcode) {
6879 switch (Opcode) {
6880 case VPCMPUBZ128rmi:
6881 case VPCMPUBZ128rmik:
6882 case VPCMPUBZ128rri:
6883 case VPCMPUBZ128rrik:
6884 case VPCMPUBZ256rmi:
6885 case VPCMPUBZ256rmik:
6886 case VPCMPUBZ256rri:
6887 case VPCMPUBZ256rrik:
6888 case VPCMPUBZrmi:
6889 case VPCMPUBZrmik:
6890 case VPCMPUBZrri:
6891 case VPCMPUBZrrik:
6892 return true;
6893 }
6894 return false;
6895}
6896
6897bool isVSQRTPD(unsigned Opcode) {
6898 switch (Opcode) {
6899 case VSQRTPDYm:
6900 case VSQRTPDYr:
6901 case VSQRTPDZ128m:
6902 case VSQRTPDZ128mb:
6903 case VSQRTPDZ128mbk:
6904 case VSQRTPDZ128mbkz:
6905 case VSQRTPDZ128mk:
6906 case VSQRTPDZ128mkz:
6907 case VSQRTPDZ128r:
6908 case VSQRTPDZ128rk:
6909 case VSQRTPDZ128rkz:
6910 case VSQRTPDZ256m:
6911 case VSQRTPDZ256mb:
6912 case VSQRTPDZ256mbk:
6913 case VSQRTPDZ256mbkz:
6914 case VSQRTPDZ256mk:
6915 case VSQRTPDZ256mkz:
6916 case VSQRTPDZ256r:
6917 case VSQRTPDZ256rk:
6918 case VSQRTPDZ256rkz:
6919 case VSQRTPDZm:
6920 case VSQRTPDZmb:
6921 case VSQRTPDZmbk:
6922 case VSQRTPDZmbkz:
6923 case VSQRTPDZmk:
6924 case VSQRTPDZmkz:
6925 case VSQRTPDZr:
6926 case VSQRTPDZrb:
6927 case VSQRTPDZrbk:
6928 case VSQRTPDZrbkz:
6929 case VSQRTPDZrk:
6930 case VSQRTPDZrkz:
6931 case VSQRTPDm:
6932 case VSQRTPDr:
6933 return true;
6934 }
6935 return false;
6936}
6937
6938bool isVFRCZPS(unsigned Opcode) {
6939 switch (Opcode) {
6940 case VFRCZPSYrm:
6941 case VFRCZPSYrr:
6942 case VFRCZPSrm:
6943 case VFRCZPSrr:
6944 return true;
6945 }
6946 return false;
6947}
6948
6949bool isVFNMADD213SS(unsigned Opcode) {
6950 switch (Opcode) {
6951 case VFNMADD213SSZm_Int:
6952 case VFNMADD213SSZm_Intk:
6953 case VFNMADD213SSZm_Intkz:
6954 case VFNMADD213SSZr_Int:
6955 case VFNMADD213SSZr_Intk:
6956 case VFNMADD213SSZr_Intkz:
6957 case VFNMADD213SSZrb_Int:
6958 case VFNMADD213SSZrb_Intk:
6959 case VFNMADD213SSZrb_Intkz:
6960 case VFNMADD213SSm_Int:
6961 case VFNMADD213SSr_Int:
6962 return true;
6963 }
6964 return false;
6965}
6966
6967bool isVPMOVDW(unsigned Opcode) {
6968 switch (Opcode) {
6969 case VPMOVDWZ128mr:
6970 case VPMOVDWZ128mrk:
6971 case VPMOVDWZ128rr:
6972 case VPMOVDWZ128rrk:
6973 case VPMOVDWZ128rrkz:
6974 case VPMOVDWZ256mr:
6975 case VPMOVDWZ256mrk:
6976 case VPMOVDWZ256rr:
6977 case VPMOVDWZ256rrk:
6978 case VPMOVDWZ256rrkz:
6979 case VPMOVDWZmr:
6980 case VPMOVDWZmrk:
6981 case VPMOVDWZrr:
6982 case VPMOVDWZrrk:
6983 case VPMOVDWZrrkz:
6984 return true;
6985 }
6986 return false;
6987}
6988
6989bool isVPSHRDVQ(unsigned Opcode) {
6990 switch (Opcode) {
6991 case VPSHRDVQZ128m:
6992 case VPSHRDVQZ128mb:
6993 case VPSHRDVQZ128mbk:
6994 case VPSHRDVQZ128mbkz:
6995 case VPSHRDVQZ128mk:
6996 case VPSHRDVQZ128mkz:
6997 case VPSHRDVQZ128r:
6998 case VPSHRDVQZ128rk:
6999 case VPSHRDVQZ128rkz:
7000 case VPSHRDVQZ256m:
7001 case VPSHRDVQZ256mb:
7002 case VPSHRDVQZ256mbk:
7003 case VPSHRDVQZ256mbkz:
7004 case VPSHRDVQZ256mk:
7005 case VPSHRDVQZ256mkz:
7006 case VPSHRDVQZ256r:
7007 case VPSHRDVQZ256rk:
7008 case VPSHRDVQZ256rkz:
7009 case VPSHRDVQZm:
7010 case VPSHRDVQZmb:
7011 case VPSHRDVQZmbk:
7012 case VPSHRDVQZmbkz:
7013 case VPSHRDVQZmk:
7014 case VPSHRDVQZmkz:
7015 case VPSHRDVQZr:
7016 case VPSHRDVQZrk:
7017 case VPSHRDVQZrkz:
7018 return true;
7019 }
7020 return false;
7021}
7022
7023bool isVBROADCASTSD(unsigned Opcode) {
7024 switch (Opcode) {
7025 case VBROADCASTSDYrm:
7026 case VBROADCASTSDYrr:
7027 case VBROADCASTSDZ256rm:
7028 case VBROADCASTSDZ256rmk:
7029 case VBROADCASTSDZ256rmkz:
7030 case VBROADCASTSDZ256rr:
7031 case VBROADCASTSDZ256rrk:
7032 case VBROADCASTSDZ256rrkz:
7033 case VBROADCASTSDZrm:
7034 case VBROADCASTSDZrmk:
7035 case VBROADCASTSDZrmkz:
7036 case VBROADCASTSDZrr:
7037 case VBROADCASTSDZrrk:
7038 case VBROADCASTSDZrrkz:
7039 return true;
7040 }
7041 return false;
7042}
7043
7044bool isVSHUFPD(unsigned Opcode) {
7045 switch (Opcode) {
7046 case VSHUFPDYrmi:
7047 case VSHUFPDYrri:
7048 case VSHUFPDZ128rmbi:
7049 case VSHUFPDZ128rmbik:
7050 case VSHUFPDZ128rmbikz:
7051 case VSHUFPDZ128rmi:
7052 case VSHUFPDZ128rmik:
7053 case VSHUFPDZ128rmikz:
7054 case VSHUFPDZ128rri:
7055 case VSHUFPDZ128rrik:
7056 case VSHUFPDZ128rrikz:
7057 case VSHUFPDZ256rmbi:
7058 case VSHUFPDZ256rmbik:
7059 case VSHUFPDZ256rmbikz:
7060 case VSHUFPDZ256rmi:
7061 case VSHUFPDZ256rmik:
7062 case VSHUFPDZ256rmikz:
7063 case VSHUFPDZ256rri:
7064 case VSHUFPDZ256rrik:
7065 case VSHUFPDZ256rrikz:
7066 case VSHUFPDZrmbi:
7067 case VSHUFPDZrmbik:
7068 case VSHUFPDZrmbikz:
7069 case VSHUFPDZrmi:
7070 case VSHUFPDZrmik:
7071 case VSHUFPDZrmikz:
7072 case VSHUFPDZrri:
7073 case VSHUFPDZrrik:
7074 case VSHUFPDZrrikz:
7075 case VSHUFPDrmi:
7076 case VSHUFPDrri:
7077 return true;
7078 }
7079 return false;
7080}
7081
7082bool isVPSUBSW(unsigned Opcode) {
7083 switch (Opcode) {
7084 case VPSUBSWYrm:
7085 case VPSUBSWYrr:
7086 case VPSUBSWZ128rm:
7087 case VPSUBSWZ128rmk:
7088 case VPSUBSWZ128rmkz:
7089 case VPSUBSWZ128rr:
7090 case VPSUBSWZ128rrk:
7091 case VPSUBSWZ128rrkz:
7092 case VPSUBSWZ256rm:
7093 case VPSUBSWZ256rmk:
7094 case VPSUBSWZ256rmkz:
7095 case VPSUBSWZ256rr:
7096 case VPSUBSWZ256rrk:
7097 case VPSUBSWZ256rrkz:
7098 case VPSUBSWZrm:
7099 case VPSUBSWZrmk:
7100 case VPSUBSWZrmkz:
7101 case VPSUBSWZrr:
7102 case VPSUBSWZrrk:
7103 case VPSUBSWZrrkz:
7104 case VPSUBSWrm:
7105 case VPSUBSWrr:
7106 return true;
7107 }
7108 return false;
7109}
7110
7111bool isKUNPCKBW(unsigned Opcode) {
7112 return Opcode == KUNPCKBWrr;
7113}
7114
7115bool isVPBLENDD(unsigned Opcode) {
7116 switch (Opcode) {
7117 case VPBLENDDYrmi:
7118 case VPBLENDDYrri:
7119 case VPBLENDDrmi:
7120 case VPBLENDDrri:
7121 return true;
7122 }
7123 return false;
7124}
7125
7126bool isUNPCKHPD(unsigned Opcode) {
7127 switch (Opcode) {
7128 case UNPCKHPDrm:
7129 case UNPCKHPDrr:
7130 return true;
7131 }
7132 return false;
7133}
7134
7135bool isVFNMADD231SD(unsigned Opcode) {
7136 switch (Opcode) {
7137 case VFNMADD231SDZm_Int:
7138 case VFNMADD231SDZm_Intk:
7139 case VFNMADD231SDZm_Intkz:
7140 case VFNMADD231SDZr_Int:
7141 case VFNMADD231SDZr_Intk:
7142 case VFNMADD231SDZr_Intkz:
7143 case VFNMADD231SDZrb_Int:
7144 case VFNMADD231SDZrb_Intk:
7145 case VFNMADD231SDZrb_Intkz:
7146 case VFNMADD231SDm_Int:
7147 case VFNMADD231SDr_Int:
7148 return true;
7149 }
7150 return false;
7151}
7152
7153bool isVPBROADCASTMW2D(unsigned Opcode) {
7154 switch (Opcode) {
7155 case VPBROADCASTMW2DZ128rr:
7156 case VPBROADCASTMW2DZ256rr:
7157 case VPBROADCASTMW2DZrr:
7158 return true;
7159 }
7160 return false;
7161}
7162
7163bool isVPMULTISHIFTQB(unsigned Opcode) {
7164 switch (Opcode) {
7165 case VPMULTISHIFTQBZ128rm:
7166 case VPMULTISHIFTQBZ128rmb:
7167 case VPMULTISHIFTQBZ128rmbk:
7168 case VPMULTISHIFTQBZ128rmbkz:
7169 case VPMULTISHIFTQBZ128rmk:
7170 case VPMULTISHIFTQBZ128rmkz:
7171 case VPMULTISHIFTQBZ128rr:
7172 case VPMULTISHIFTQBZ128rrk:
7173 case VPMULTISHIFTQBZ128rrkz:
7174 case VPMULTISHIFTQBZ256rm:
7175 case VPMULTISHIFTQBZ256rmb:
7176 case VPMULTISHIFTQBZ256rmbk:
7177 case VPMULTISHIFTQBZ256rmbkz:
7178 case VPMULTISHIFTQBZ256rmk:
7179 case VPMULTISHIFTQBZ256rmkz:
7180 case VPMULTISHIFTQBZ256rr:
7181 case VPMULTISHIFTQBZ256rrk:
7182 case VPMULTISHIFTQBZ256rrkz:
7183 case VPMULTISHIFTQBZrm:
7184 case VPMULTISHIFTQBZrmb:
7185 case VPMULTISHIFTQBZrmbk:
7186 case VPMULTISHIFTQBZrmbkz:
7187 case VPMULTISHIFTQBZrmk:
7188 case VPMULTISHIFTQBZrmkz:
7189 case VPMULTISHIFTQBZrr:
7190 case VPMULTISHIFTQBZrrk:
7191 case VPMULTISHIFTQBZrrkz:
7192 return true;
7193 }
7194 return false;
7195}
7196
7197bool isVP2INTERSECTQ(unsigned Opcode) {
7198 switch (Opcode) {
7199 case VP2INTERSECTQZ128rm:
7200 case VP2INTERSECTQZ128rmb:
7201 case VP2INTERSECTQZ128rr:
7202 case VP2INTERSECTQZ256rm:
7203 case VP2INTERSECTQZ256rmb:
7204 case VP2INTERSECTQZ256rr:
7205 case VP2INTERSECTQZrm:
7206 case VP2INTERSECTQZrmb:
7207 case VP2INTERSECTQZrr:
7208 return true;
7209 }
7210 return false;
7211}
7212
7213bool isVPUNPCKHWD(unsigned Opcode) {
7214 switch (Opcode) {
7215 case VPUNPCKHWDYrm:
7216 case VPUNPCKHWDYrr:
7217 case VPUNPCKHWDZ128rm:
7218 case VPUNPCKHWDZ128rmk:
7219 case VPUNPCKHWDZ128rmkz:
7220 case VPUNPCKHWDZ128rr:
7221 case VPUNPCKHWDZ128rrk:
7222 case VPUNPCKHWDZ128rrkz:
7223 case VPUNPCKHWDZ256rm:
7224 case VPUNPCKHWDZ256rmk:
7225 case VPUNPCKHWDZ256rmkz:
7226 case VPUNPCKHWDZ256rr:
7227 case VPUNPCKHWDZ256rrk:
7228 case VPUNPCKHWDZ256rrkz:
7229 case VPUNPCKHWDZrm:
7230 case VPUNPCKHWDZrmk:
7231 case VPUNPCKHWDZrmkz:
7232 case VPUNPCKHWDZrr:
7233 case VPUNPCKHWDZrrk:
7234 case VPUNPCKHWDZrrkz:
7235 case VPUNPCKHWDrm:
7236 case VPUNPCKHWDrr:
7237 return true;
7238 }
7239 return false;
7240}
7241
7242bool isVPERM2F128(unsigned Opcode) {
7243 switch (Opcode) {
7244 case VPERM2F128rm:
7245 case VPERM2F128rr:
7246 return true;
7247 }
7248 return false;
7249}
7250
7251bool isINSD(unsigned Opcode) {
7252 return Opcode == INSL;
7253}
7254
7255bool isLFS(unsigned Opcode) {
7256 switch (Opcode) {
7257 case LFS16rm:
7258 case LFS32rm:
7259 case LFS64rm:
7260 return true;
7261 }
7262 return false;
7263}
7264
7265bool isFMULP(unsigned Opcode) {
7266 return Opcode == MUL_FPrST0;
7267}
7268
7269bool isCWD(unsigned Opcode) {
7270 return Opcode == CWD;
7271}
7272
7273bool isVDIVSS(unsigned Opcode) {
7274 switch (Opcode) {
7275 case VDIVSSZrm_Int:
7276 case VDIVSSZrm_Intk:
7277 case VDIVSSZrm_Intkz:
7278 case VDIVSSZrr_Int:
7279 case VDIVSSZrr_Intk:
7280 case VDIVSSZrr_Intkz:
7281 case VDIVSSZrrb_Int:
7282 case VDIVSSZrrb_Intk:
7283 case VDIVSSZrrb_Intkz:
7284 case VDIVSSrm_Int:
7285 case VDIVSSrr_Int:
7286 return true;
7287 }
7288 return false;
7289}
7290
7291bool isVPSRLQ(unsigned Opcode) {
7292 switch (Opcode) {
7293 case VPSRLQYri:
7294 case VPSRLQYrm:
7295 case VPSRLQYrr:
7296 case VPSRLQZ128mbi:
7297 case VPSRLQZ128mbik:
7298 case VPSRLQZ128mbikz:
7299 case VPSRLQZ128mi:
7300 case VPSRLQZ128mik:
7301 case VPSRLQZ128mikz:
7302 case VPSRLQZ128ri:
7303 case VPSRLQZ128rik:
7304 case VPSRLQZ128rikz:
7305 case VPSRLQZ128rm:
7306 case VPSRLQZ128rmk:
7307 case VPSRLQZ128rmkz:
7308 case VPSRLQZ128rr:
7309 case VPSRLQZ128rrk:
7310 case VPSRLQZ128rrkz:
7311 case VPSRLQZ256mbi:
7312 case VPSRLQZ256mbik:
7313 case VPSRLQZ256mbikz:
7314 case VPSRLQZ256mi:
7315 case VPSRLQZ256mik:
7316 case VPSRLQZ256mikz:
7317 case VPSRLQZ256ri:
7318 case VPSRLQZ256rik:
7319 case VPSRLQZ256rikz:
7320 case VPSRLQZ256rm:
7321 case VPSRLQZ256rmk:
7322 case VPSRLQZ256rmkz:
7323 case VPSRLQZ256rr:
7324 case VPSRLQZ256rrk:
7325 case VPSRLQZ256rrkz:
7326 case VPSRLQZmbi:
7327 case VPSRLQZmbik:
7328 case VPSRLQZmbikz:
7329 case VPSRLQZmi:
7330 case VPSRLQZmik:
7331 case VPSRLQZmikz:
7332 case VPSRLQZri:
7333 case VPSRLQZrik:
7334 case VPSRLQZrikz:
7335 case VPSRLQZrm:
7336 case VPSRLQZrmk:
7337 case VPSRLQZrmkz:
7338 case VPSRLQZrr:
7339 case VPSRLQZrrk:
7340 case VPSRLQZrrkz:
7341 case VPSRLQri:
7342 case VPSRLQrm:
7343 case VPSRLQrr:
7344 return true;
7345 }
7346 return false;
7347}
7348
7349bool isFSQRT(unsigned Opcode) {
7350 return Opcode == SQRT_F;
7351}
7352
7353bool isJRCXZ(unsigned Opcode) {
7354 return Opcode == JRCXZ;
7355}
7356
7357bool isVPMOVMSKB(unsigned Opcode) {
7358 switch (Opcode) {
7359 case VPMOVMSKBYrr:
7360 case VPMOVMSKBrr:
7361 return true;
7362 }
7363 return false;
7364}
7365
7366bool isAESDEC256KL(unsigned Opcode) {
7367 return Opcode == AESDEC256KL;
7368}
7369
7370bool isFLDENV(unsigned Opcode) {
7371 return Opcode == FLDENVm;
7372}
7373
7374bool isVPHSUBWD(unsigned Opcode) {
7375 switch (Opcode) {
7376 case VPHSUBWDrm:
7377 case VPHSUBWDrr:
7378 return true;
7379 }
7380 return false;
7381}
7382
7383bool isWBNOINVD(unsigned Opcode) {
7384 return Opcode == WBNOINVD;
7385}
7386
7387bool isVEXPANDPD(unsigned Opcode) {
7388 switch (Opcode) {
7389 case VEXPANDPDZ128rm:
7390 case VEXPANDPDZ128rmk:
7391 case VEXPANDPDZ128rmkz:
7392 case VEXPANDPDZ128rr:
7393 case VEXPANDPDZ128rrk:
7394 case VEXPANDPDZ128rrkz:
7395 case VEXPANDPDZ256rm:
7396 case VEXPANDPDZ256rmk:
7397 case VEXPANDPDZ256rmkz:
7398 case VEXPANDPDZ256rr:
7399 case VEXPANDPDZ256rrk:
7400 case VEXPANDPDZ256rrkz:
7401 case VEXPANDPDZrm:
7402 case VEXPANDPDZrmk:
7403 case VEXPANDPDZrmkz:
7404 case VEXPANDPDZrr:
7405 case VEXPANDPDZrrk:
7406 case VEXPANDPDZrrkz:
7407 return true;
7408 }
7409 return false;
7410}
7411
7412bool isFYL2XP1(unsigned Opcode) {
7413 return Opcode == FYL2XP1;
7414}
7415
7416bool isPREFETCHT2(unsigned Opcode) {
7417 return Opcode == PREFETCHT2;
7418}
7419
7420bool isVPDPBSUDS(unsigned Opcode) {
7421 switch (Opcode) {
7422 case VPDPBSUDSYrm:
7423 case VPDPBSUDSYrr:
7424 case VPDPBSUDSrm:
7425 case VPDPBSUDSrr:
7426 return true;
7427 }
7428 return false;
7429}
7430
7431bool isVSHA512MSG2(unsigned Opcode) {
7432 return Opcode == VSHA512MSG2rr;
7433}
7434
7435bool isPMULHUW(unsigned Opcode) {
7436 switch (Opcode) {
7437 case MMX_PMULHUWrm:
7438 case MMX_PMULHUWrr:
7439 case PMULHUWrm:
7440 case PMULHUWrr:
7441 return true;
7442 }
7443 return false;
7444}
7445
7446bool isKANDNB(unsigned Opcode) {
7447 return Opcode == KANDNBrr;
7448}
7449
7450bool isVCVTUW2PH(unsigned Opcode) {
7451 switch (Opcode) {
7452 case VCVTUW2PHZ128rm:
7453 case VCVTUW2PHZ128rmb:
7454 case VCVTUW2PHZ128rmbk:
7455 case VCVTUW2PHZ128rmbkz:
7456 case VCVTUW2PHZ128rmk:
7457 case VCVTUW2PHZ128rmkz:
7458 case VCVTUW2PHZ128rr:
7459 case VCVTUW2PHZ128rrk:
7460 case VCVTUW2PHZ128rrkz:
7461 case VCVTUW2PHZ256rm:
7462 case VCVTUW2PHZ256rmb:
7463 case VCVTUW2PHZ256rmbk:
7464 case VCVTUW2PHZ256rmbkz:
7465 case VCVTUW2PHZ256rmk:
7466 case VCVTUW2PHZ256rmkz:
7467 case VCVTUW2PHZ256rr:
7468 case VCVTUW2PHZ256rrk:
7469 case VCVTUW2PHZ256rrkz:
7470 case VCVTUW2PHZrm:
7471 case VCVTUW2PHZrmb:
7472 case VCVTUW2PHZrmbk:
7473 case VCVTUW2PHZrmbkz:
7474 case VCVTUW2PHZrmk:
7475 case VCVTUW2PHZrmkz:
7476 case VCVTUW2PHZrr:
7477 case VCVTUW2PHZrrb:
7478 case VCVTUW2PHZrrbk:
7479 case VCVTUW2PHZrrbkz:
7480 case VCVTUW2PHZrrk:
7481 case VCVTUW2PHZrrkz:
7482 return true;
7483 }
7484 return false;
7485}
7486
7487bool isAESDECWIDE256KL(unsigned Opcode) {
7488 return Opcode == AESDECWIDE256KL;
7489}
7490
7491bool isVPGATHERDD(unsigned Opcode) {
7492 switch (Opcode) {
7493 case VPGATHERDDYrm:
7494 case VPGATHERDDZ128rm:
7495 case VPGATHERDDZ256rm:
7496 case VPGATHERDDZrm:
7497 case VPGATHERDDrm:
7498 return true;
7499 }
7500 return false;
7501}
7502
7503bool isVREDUCESH(unsigned Opcode) {
7504 switch (Opcode) {
7505 case VREDUCESHZrmi:
7506 case VREDUCESHZrmik:
7507 case VREDUCESHZrmikz:
7508 case VREDUCESHZrri:
7509 case VREDUCESHZrrib:
7510 case VREDUCESHZrribk:
7511 case VREDUCESHZrribkz:
7512 case VREDUCESHZrrik:
7513 case VREDUCESHZrrikz:
7514 return true;
7515 }
7516 return false;
7517}
7518
7519bool isPOPFQ(unsigned Opcode) {
7520 return Opcode == POPF64;
7521}
7522
7523bool isPAVGUSB(unsigned Opcode) {
7524 switch (Opcode) {
7525 case PAVGUSBrm:
7526 case PAVGUSBrr:
7527 return true;
7528 }
7529 return false;
7530}
7531
7532bool isVALIGND(unsigned Opcode) {
7533 switch (Opcode) {
7534 case VALIGNDZ128rmbi:
7535 case VALIGNDZ128rmbik:
7536 case VALIGNDZ128rmbikz:
7537 case VALIGNDZ128rmi:
7538 case VALIGNDZ128rmik:
7539 case VALIGNDZ128rmikz:
7540 case VALIGNDZ128rri:
7541 case VALIGNDZ128rrik:
7542 case VALIGNDZ128rrikz:
7543 case VALIGNDZ256rmbi:
7544 case VALIGNDZ256rmbik:
7545 case VALIGNDZ256rmbikz:
7546 case VALIGNDZ256rmi:
7547 case VALIGNDZ256rmik:
7548 case VALIGNDZ256rmikz:
7549 case VALIGNDZ256rri:
7550 case VALIGNDZ256rrik:
7551 case VALIGNDZ256rrikz:
7552 case VALIGNDZrmbi:
7553 case VALIGNDZrmbik:
7554 case VALIGNDZrmbikz:
7555 case VALIGNDZrmi:
7556 case VALIGNDZrmik:
7557 case VALIGNDZrmikz:
7558 case VALIGNDZrri:
7559 case VALIGNDZrrik:
7560 case VALIGNDZrrikz:
7561 return true;
7562 }
7563 return false;
7564}
7565
7566bool isVPHMINPOSUW(unsigned Opcode) {
7567 switch (Opcode) {
7568 case VPHMINPOSUWrm:
7569 case VPHMINPOSUWrr:
7570 return true;
7571 }
7572 return false;
7573}
7574
7575bool isLIDTD(unsigned Opcode) {
7576 return Opcode == LIDT32m;
7577}
7578
7579bool isVPERMT2PD(unsigned Opcode) {
7580 switch (Opcode) {
7581 case VPERMT2PDZ128rm:
7582 case VPERMT2PDZ128rmb:
7583 case VPERMT2PDZ128rmbk:
7584 case VPERMT2PDZ128rmbkz:
7585 case VPERMT2PDZ128rmk:
7586 case VPERMT2PDZ128rmkz:
7587 case VPERMT2PDZ128rr:
7588 case VPERMT2PDZ128rrk:
7589 case VPERMT2PDZ128rrkz:
7590 case VPERMT2PDZ256rm:
7591 case VPERMT2PDZ256rmb:
7592 case VPERMT2PDZ256rmbk:
7593 case VPERMT2PDZ256rmbkz:
7594 case VPERMT2PDZ256rmk:
7595 case VPERMT2PDZ256rmkz:
7596 case VPERMT2PDZ256rr:
7597 case VPERMT2PDZ256rrk:
7598 case VPERMT2PDZ256rrkz:
7599 case VPERMT2PDZrm:
7600 case VPERMT2PDZrmb:
7601 case VPERMT2PDZrmbk:
7602 case VPERMT2PDZrmbkz:
7603 case VPERMT2PDZrmk:
7604 case VPERMT2PDZrmkz:
7605 case VPERMT2PDZrr:
7606 case VPERMT2PDZrrk:
7607 case VPERMT2PDZrrkz:
7608 return true;
7609 }
7610 return false;
7611}
7612
7613bool isVMLAUNCH(unsigned Opcode) {
7614 return Opcode == VMLAUNCH;
7615}
7616
7617bool isVPXORQ(unsigned Opcode) {
7618 switch (Opcode) {
7619 case VPXORQZ128rm:
7620 case VPXORQZ128rmb:
7621 case VPXORQZ128rmbk:
7622 case VPXORQZ128rmbkz:
7623 case VPXORQZ128rmk:
7624 case VPXORQZ128rmkz:
7625 case VPXORQZ128rr:
7626 case VPXORQZ128rrk:
7627 case VPXORQZ128rrkz:
7628 case VPXORQZ256rm:
7629 case VPXORQZ256rmb:
7630 case VPXORQZ256rmbk:
7631 case VPXORQZ256rmbkz:
7632 case VPXORQZ256rmk:
7633 case VPXORQZ256rmkz:
7634 case VPXORQZ256rr:
7635 case VPXORQZ256rrk:
7636 case VPXORQZ256rrkz:
7637 case VPXORQZrm:
7638 case VPXORQZrmb:
7639 case VPXORQZrmbk:
7640 case VPXORQZrmbkz:
7641 case VPXORQZrmk:
7642 case VPXORQZrmkz:
7643 case VPXORQZrr:
7644 case VPXORQZrrk:
7645 case VPXORQZrrkz:
7646 return true;
7647 }
7648 return false;
7649}
7650
7651bool isMOVNTDQ(unsigned Opcode) {
7652 return Opcode == MOVNTDQmr;
7653}
7654
7655bool isPOP2P(unsigned Opcode) {
7656 return Opcode == POP2P;
7657}
7658
7659bool isVADDPD(unsigned Opcode) {
7660 switch (Opcode) {
7661 case VADDPDYrm:
7662 case VADDPDYrr:
7663 case VADDPDZ128rm:
7664 case VADDPDZ128rmb:
7665 case VADDPDZ128rmbk:
7666 case VADDPDZ128rmbkz:
7667 case VADDPDZ128rmk:
7668 case VADDPDZ128rmkz:
7669 case VADDPDZ128rr:
7670 case VADDPDZ128rrk:
7671 case VADDPDZ128rrkz:
7672 case VADDPDZ256rm:
7673 case VADDPDZ256rmb:
7674 case VADDPDZ256rmbk:
7675 case VADDPDZ256rmbkz:
7676 case VADDPDZ256rmk:
7677 case VADDPDZ256rmkz:
7678 case VADDPDZ256rr:
7679 case VADDPDZ256rrk:
7680 case VADDPDZ256rrkz:
7681 case VADDPDZrm:
7682 case VADDPDZrmb:
7683 case VADDPDZrmbk:
7684 case VADDPDZrmbkz:
7685 case VADDPDZrmk:
7686 case VADDPDZrmkz:
7687 case VADDPDZrr:
7688 case VADDPDZrrb:
7689 case VADDPDZrrbk:
7690 case VADDPDZrrbkz:
7691 case VADDPDZrrk:
7692 case VADDPDZrrkz:
7693 case VADDPDrm:
7694 case VADDPDrr:
7695 return true;
7696 }
7697 return false;
7698}
7699
7700bool isSMSW(unsigned Opcode) {
7701 switch (Opcode) {
7702 case SMSW16m:
7703 case SMSW16r:
7704 case SMSW32r:
7705 case SMSW64r:
7706 return true;
7707 }
7708 return false;
7709}
7710
7711bool isVEXP2PD(unsigned Opcode) {
7712 switch (Opcode) {
7713 case VEXP2PDZm:
7714 case VEXP2PDZmb:
7715 case VEXP2PDZmbk:
7716 case VEXP2PDZmbkz:
7717 case VEXP2PDZmk:
7718 case VEXP2PDZmkz:
7719 case VEXP2PDZr:
7720 case VEXP2PDZrb:
7721 case VEXP2PDZrbk:
7722 case VEXP2PDZrbkz:
7723 case VEXP2PDZrk:
7724 case VEXP2PDZrkz:
7725 return true;
7726 }
7727 return false;
7728}
7729
7730bool isPMULUDQ(unsigned Opcode) {
7731 switch (Opcode) {
7732 case MMX_PMULUDQrm:
7733 case MMX_PMULUDQrr:
7734 case PMULUDQrm:
7735 case PMULUDQrr:
7736 return true;
7737 }
7738 return false;
7739}
7740
7741bool isIRET(unsigned Opcode) {
7742 return Opcode == IRET16;
7743}
7744
7745bool isMULPS(unsigned Opcode) {
7746 switch (Opcode) {
7747 case MULPSrm:
7748 case MULPSrr:
7749 return true;
7750 }
7751 return false;
7752}
7753
7754bool isVFNMSUBPD(unsigned Opcode) {
7755 switch (Opcode) {
7756 case VFNMSUBPD4Ymr:
7757 case VFNMSUBPD4Yrm:
7758 case VFNMSUBPD4Yrr:
7759 case VFNMSUBPD4Yrr_REV:
7760 case VFNMSUBPD4mr:
7761 case VFNMSUBPD4rm:
7762 case VFNMSUBPD4rr:
7763 case VFNMSUBPD4rr_REV:
7764 return true;
7765 }
7766 return false;
7767}
7768
7769bool isPHADDW(unsigned Opcode) {
7770 switch (Opcode) {
7771 case MMX_PHADDWrm:
7772 case MMX_PHADDWrr:
7773 case PHADDWrm:
7774 case PHADDWrr:
7775 return true;
7776 }
7777 return false;
7778}
7779
7780bool isRDSEED(unsigned Opcode) {
7781 switch (Opcode) {
7782 case RDSEED16r:
7783 case RDSEED32r:
7784 case RDSEED64r:
7785 return true;
7786 }
7787 return false;
7788}
7789
7790bool isVPSHLW(unsigned Opcode) {
7791 switch (Opcode) {
7792 case VPSHLWmr:
7793 case VPSHLWrm:
7794 case VPSHLWrr:
7795 case VPSHLWrr_REV:
7796 return true;
7797 }
7798 return false;
7799}
7800
7801bool isRMPUPDATE(unsigned Opcode) {
7802 return Opcode == RMPUPDATE;
7803}
7804
7805bool isVFMADD231PH(unsigned Opcode) {
7806 switch (Opcode) {
7807 case VFMADD231PHZ128m:
7808 case VFMADD231PHZ128mb:
7809 case VFMADD231PHZ128mbk:
7810 case VFMADD231PHZ128mbkz:
7811 case VFMADD231PHZ128mk:
7812 case VFMADD231PHZ128mkz:
7813 case VFMADD231PHZ128r:
7814 case VFMADD231PHZ128rk:
7815 case VFMADD231PHZ128rkz:
7816 case VFMADD231PHZ256m:
7817 case VFMADD231PHZ256mb:
7818 case VFMADD231PHZ256mbk:
7819 case VFMADD231PHZ256mbkz:
7820 case VFMADD231PHZ256mk:
7821 case VFMADD231PHZ256mkz:
7822 case VFMADD231PHZ256r:
7823 case VFMADD231PHZ256rk:
7824 case VFMADD231PHZ256rkz:
7825 case VFMADD231PHZm:
7826 case VFMADD231PHZmb:
7827 case VFMADD231PHZmbk:
7828 case VFMADD231PHZmbkz:
7829 case VFMADD231PHZmk:
7830 case VFMADD231PHZmkz:
7831 case VFMADD231PHZr:
7832 case VFMADD231PHZrb:
7833 case VFMADD231PHZrbk:
7834 case VFMADD231PHZrbkz:
7835 case VFMADD231PHZrk:
7836 case VFMADD231PHZrkz:
7837 return true;
7838 }
7839 return false;
7840}
7841
7842bool isVPSHAD(unsigned Opcode) {
7843 switch (Opcode) {
7844 case VPSHADmr:
7845 case VPSHADrm:
7846 case VPSHADrr:
7847 case VPSHADrr_REV:
7848 return true;
7849 }
7850 return false;
7851}
7852
7853bool isCLWB(unsigned Opcode) {
7854 return Opcode == CLWB;
7855}
7856
7857bool isPSUBUSB(unsigned Opcode) {
7858 switch (Opcode) {
7859 case MMX_PSUBUSBrm:
7860 case MMX_PSUBUSBrr:
7861 case PSUBUSBrm:
7862 case PSUBUSBrr:
7863 return true;
7864 }
7865 return false;
7866}
7867
7868bool isVCVTTSD2USI(unsigned Opcode) {
7869 switch (Opcode) {
7870 case VCVTTSD2USI64Zrm_Int:
7871 case VCVTTSD2USI64Zrr_Int:
7872 case VCVTTSD2USI64Zrrb_Int:
7873 case VCVTTSD2USIZrm_Int:
7874 case VCVTTSD2USIZrr_Int:
7875 case VCVTTSD2USIZrrb_Int:
7876 return true;
7877 }
7878 return false;
7879}
7880
7881bool isVEXTRACTPS(unsigned Opcode) {
7882 switch (Opcode) {
7883 case VEXTRACTPSZmr:
7884 case VEXTRACTPSZrr:
7885 case VEXTRACTPSmr:
7886 case VEXTRACTPSrr:
7887 return true;
7888 }
7889 return false;
7890}
7891
7892bool isMOVLPD(unsigned Opcode) {
7893 switch (Opcode) {
7894 case MOVLPDmr:
7895 case MOVLPDrm:
7896 return true;
7897 }
7898 return false;
7899}
7900
7901bool isLGDTD(unsigned Opcode) {
7902 return Opcode == LGDT32m;
7903}
7904
7905bool isVPBROADCASTMB2Q(unsigned Opcode) {
7906 switch (Opcode) {
7907 case VPBROADCASTMB2QZ128rr:
7908 case VPBROADCASTMB2QZ256rr:
7909 case VPBROADCASTMB2QZrr:
7910 return true;
7911 }
7912 return false;
7913}
7914
7915bool isOUT(unsigned Opcode) {
7916 switch (Opcode) {
7917 case OUT16ir:
7918 case OUT16rr:
7919 case OUT32ir:
7920 case OUT32rr:
7921 case OUT8ir:
7922 case OUT8rr:
7923 return true;
7924 }
7925 return false;
7926}
7927
7928bool isVMSAVE(unsigned Opcode) {
7929 switch (Opcode) {
7930 case VMSAVE32:
7931 case VMSAVE64:
7932 return true;
7933 }
7934 return false;
7935}
7936
7937bool isVCVTQQ2PD(unsigned Opcode) {
7938 switch (Opcode) {
7939 case VCVTQQ2PDZ128rm:
7940 case VCVTQQ2PDZ128rmb:
7941 case VCVTQQ2PDZ128rmbk:
7942 case VCVTQQ2PDZ128rmbkz:
7943 case VCVTQQ2PDZ128rmk:
7944 case VCVTQQ2PDZ128rmkz:
7945 case VCVTQQ2PDZ128rr:
7946 case VCVTQQ2PDZ128rrk:
7947 case VCVTQQ2PDZ128rrkz:
7948 case VCVTQQ2PDZ256rm:
7949 case VCVTQQ2PDZ256rmb:
7950 case VCVTQQ2PDZ256rmbk:
7951 case VCVTQQ2PDZ256rmbkz:
7952 case VCVTQQ2PDZ256rmk:
7953 case VCVTQQ2PDZ256rmkz:
7954 case VCVTQQ2PDZ256rr:
7955 case VCVTQQ2PDZ256rrk:
7956 case VCVTQQ2PDZ256rrkz:
7957 case VCVTQQ2PDZrm:
7958 case VCVTQQ2PDZrmb:
7959 case VCVTQQ2PDZrmbk:
7960 case VCVTQQ2PDZrmbkz:
7961 case VCVTQQ2PDZrmk:
7962 case VCVTQQ2PDZrmkz:
7963 case VCVTQQ2PDZrr:
7964 case VCVTQQ2PDZrrb:
7965 case VCVTQQ2PDZrrbk:
7966 case VCVTQQ2PDZrrbkz:
7967 case VCVTQQ2PDZrrk:
7968 case VCVTQQ2PDZrrkz:
7969 return true;
7970 }
7971 return false;
7972}
7973
7974bool isVFMADD213PH(unsigned Opcode) {
7975 switch (Opcode) {
7976 case VFMADD213PHZ128m:
7977 case VFMADD213PHZ128mb:
7978 case VFMADD213PHZ128mbk:
7979 case VFMADD213PHZ128mbkz:
7980 case VFMADD213PHZ128mk:
7981 case VFMADD213PHZ128mkz:
7982 case VFMADD213PHZ128r:
7983 case VFMADD213PHZ128rk:
7984 case VFMADD213PHZ128rkz:
7985 case VFMADD213PHZ256m:
7986 case VFMADD213PHZ256mb:
7987 case VFMADD213PHZ256mbk:
7988 case VFMADD213PHZ256mbkz:
7989 case VFMADD213PHZ256mk:
7990 case VFMADD213PHZ256mkz:
7991 case VFMADD213PHZ256r:
7992 case VFMADD213PHZ256rk:
7993 case VFMADD213PHZ256rkz:
7994 case VFMADD213PHZm:
7995 case VFMADD213PHZmb:
7996 case VFMADD213PHZmbk:
7997 case VFMADD213PHZmbkz:
7998 case VFMADD213PHZmk:
7999 case VFMADD213PHZmkz:
8000 case VFMADD213PHZr:
8001 case VFMADD213PHZrb:
8002 case VFMADD213PHZrbk:
8003 case VFMADD213PHZrbkz:
8004 case VFMADD213PHZrk:
8005 case VFMADD213PHZrkz:
8006 return true;
8007 }
8008 return false;
8009}
8010
8011bool isFCMOVBE(unsigned Opcode) {
8012 return Opcode == CMOVBE_F;
8013}
8014
8015bool isMOVSHDUP(unsigned Opcode) {
8016 switch (Opcode) {
8017 case MOVSHDUPrm:
8018 case MOVSHDUPrr:
8019 return true;
8020 }
8021 return false;
8022}
8023
8024bool isVPMOVUSQB(unsigned Opcode) {
8025 switch (Opcode) {
8026 case VPMOVUSQBZ128mr:
8027 case VPMOVUSQBZ128mrk:
8028 case VPMOVUSQBZ128rr:
8029 case VPMOVUSQBZ128rrk:
8030 case VPMOVUSQBZ128rrkz:
8031 case VPMOVUSQBZ256mr:
8032 case VPMOVUSQBZ256mrk:
8033 case VPMOVUSQBZ256rr:
8034 case VPMOVUSQBZ256rrk:
8035 case VPMOVUSQBZ256rrkz:
8036 case VPMOVUSQBZmr:
8037 case VPMOVUSQBZmrk:
8038 case VPMOVUSQBZrr:
8039 case VPMOVUSQBZrrk:
8040 case VPMOVUSQBZrrkz:
8041 return true;
8042 }
8043 return false;
8044}
8045
8046bool isFIST(unsigned Opcode) {
8047 switch (Opcode) {
8048 case IST_F16m:
8049 case IST_F32m:
8050 return true;
8051 }
8052 return false;
8053}
8054
8055bool isHADDPD(unsigned Opcode) {
8056 switch (Opcode) {
8057 case HADDPDrm:
8058 case HADDPDrr:
8059 return true;
8060 }
8061 return false;
8062}
8063
8064bool isPACKSSWB(unsigned Opcode) {
8065 switch (Opcode) {
8066 case MMX_PACKSSWBrm:
8067 case MMX_PACKSSWBrr:
8068 case PACKSSWBrm:
8069 case PACKSSWBrr:
8070 return true;
8071 }
8072 return false;
8073}
8074
8075bool isVPMACSSDQH(unsigned Opcode) {
8076 switch (Opcode) {
8077 case VPMACSSDQHrm:
8078 case VPMACSSDQHrr:
8079 return true;
8080 }
8081 return false;
8082}
8083
8084bool isVFNMSUB132SD(unsigned Opcode) {
8085 switch (Opcode) {
8086 case VFNMSUB132SDZm_Int:
8087 case VFNMSUB132SDZm_Intk:
8088 case VFNMSUB132SDZm_Intkz:
8089 case VFNMSUB132SDZr_Int:
8090 case VFNMSUB132SDZr_Intk:
8091 case VFNMSUB132SDZr_Intkz:
8092 case VFNMSUB132SDZrb_Int:
8093 case VFNMSUB132SDZrb_Intk:
8094 case VFNMSUB132SDZrb_Intkz:
8095 case VFNMSUB132SDm_Int:
8096 case VFNMSUB132SDr_Int:
8097 return true;
8098 }
8099 return false;
8100}
8101
8102bool isVPMASKMOVQ(unsigned Opcode) {
8103 switch (Opcode) {
8104 case VPMASKMOVQYmr:
8105 case VPMASKMOVQYrm:
8106 case VPMASKMOVQmr:
8107 case VPMASKMOVQrm:
8108 return true;
8109 }
8110 return false;
8111}
8112
8113bool isVCOMPRESSPD(unsigned Opcode) {
8114 switch (Opcode) {
8115 case VCOMPRESSPDZ128mr:
8116 case VCOMPRESSPDZ128mrk:
8117 case VCOMPRESSPDZ128rr:
8118 case VCOMPRESSPDZ128rrk:
8119 case VCOMPRESSPDZ128rrkz:
8120 case VCOMPRESSPDZ256mr:
8121 case VCOMPRESSPDZ256mrk:
8122 case VCOMPRESSPDZ256rr:
8123 case VCOMPRESSPDZ256rrk:
8124 case VCOMPRESSPDZ256rrkz:
8125 case VCOMPRESSPDZmr:
8126 case VCOMPRESSPDZmrk:
8127 case VCOMPRESSPDZrr:
8128 case VCOMPRESSPDZrrk:
8129 case VCOMPRESSPDZrrkz:
8130 return true;
8131 }
8132 return false;
8133}
8134
8135bool isVFMADD213SS(unsigned Opcode) {
8136 switch (Opcode) {
8137 case VFMADD213SSZm_Int:
8138 case VFMADD213SSZm_Intk:
8139 case VFMADD213SSZm_Intkz:
8140 case VFMADD213SSZr_Int:
8141 case VFMADD213SSZr_Intk:
8142 case VFMADD213SSZr_Intkz:
8143 case VFMADD213SSZrb_Int:
8144 case VFMADD213SSZrb_Intk:
8145 case VFMADD213SSZrb_Intkz:
8146 case VFMADD213SSm_Int:
8147 case VFMADD213SSr_Int:
8148 return true;
8149 }
8150 return false;
8151}
8152
8153bool isVPCMPQ(unsigned Opcode) {
8154 switch (Opcode) {
8155 case VPCMPQZ128rmi:
8156 case VPCMPQZ128rmib:
8157 case VPCMPQZ128rmibk:
8158 case VPCMPQZ128rmik:
8159 case VPCMPQZ128rri:
8160 case VPCMPQZ128rrik:
8161 case VPCMPQZ256rmi:
8162 case VPCMPQZ256rmib:
8163 case VPCMPQZ256rmibk:
8164 case VPCMPQZ256rmik:
8165 case VPCMPQZ256rri:
8166 case VPCMPQZ256rrik:
8167 case VPCMPQZrmi:
8168 case VPCMPQZrmib:
8169 case VPCMPQZrmibk:
8170 case VPCMPQZrmik:
8171 case VPCMPQZrri:
8172 case VPCMPQZrrik:
8173 return true;
8174 }
8175 return false;
8176}
8177
8178bool isVADDSH(unsigned Opcode) {
8179 switch (Opcode) {
8180 case VADDSHZrm_Int:
8181 case VADDSHZrm_Intk:
8182 case VADDSHZrm_Intkz:
8183 case VADDSHZrr_Int:
8184 case VADDSHZrr_Intk:
8185 case VADDSHZrr_Intkz:
8186 case VADDSHZrrb_Int:
8187 case VADDSHZrrb_Intk:
8188 case VADDSHZrrb_Intkz:
8189 return true;
8190 }
8191 return false;
8192}
8193
8194bool isVFNMADDSD(unsigned Opcode) {
8195 switch (Opcode) {
8196 case VFNMADDSD4mr:
8197 case VFNMADDSD4rm:
8198 case VFNMADDSD4rr:
8199 case VFNMADDSD4rr_REV:
8200 return true;
8201 }
8202 return false;
8203}
8204
8205bool isUMWAIT(unsigned Opcode) {
8206 return Opcode == UMWAIT;
8207}
8208
8209bool isVPUNPCKHDQ(unsigned Opcode) {
8210 switch (Opcode) {
8211 case VPUNPCKHDQYrm:
8212 case VPUNPCKHDQYrr:
8213 case VPUNPCKHDQZ128rm:
8214 case VPUNPCKHDQZ128rmb:
8215 case VPUNPCKHDQZ128rmbk:
8216 case VPUNPCKHDQZ128rmbkz:
8217 case VPUNPCKHDQZ128rmk:
8218 case VPUNPCKHDQZ128rmkz:
8219 case VPUNPCKHDQZ128rr:
8220 case VPUNPCKHDQZ128rrk:
8221 case VPUNPCKHDQZ128rrkz:
8222 case VPUNPCKHDQZ256rm:
8223 case VPUNPCKHDQZ256rmb:
8224 case VPUNPCKHDQZ256rmbk:
8225 case VPUNPCKHDQZ256rmbkz:
8226 case VPUNPCKHDQZ256rmk:
8227 case VPUNPCKHDQZ256rmkz:
8228 case VPUNPCKHDQZ256rr:
8229 case VPUNPCKHDQZ256rrk:
8230 case VPUNPCKHDQZ256rrkz:
8231 case VPUNPCKHDQZrm:
8232 case VPUNPCKHDQZrmb:
8233 case VPUNPCKHDQZrmbk:
8234 case VPUNPCKHDQZrmbkz:
8235 case VPUNPCKHDQZrmk:
8236 case VPUNPCKHDQZrmkz:
8237 case VPUNPCKHDQZrr:
8238 case VPUNPCKHDQZrrk:
8239 case VPUNPCKHDQZrrkz:
8240 case VPUNPCKHDQrm:
8241 case VPUNPCKHDQrr:
8242 return true;
8243 }
8244 return false;
8245}
8246
8247bool isLCALL(unsigned Opcode) {
8248 switch (Opcode) {
8249 case FARCALL16i:
8250 case FARCALL16m:
8251 case FARCALL32i:
8252 case FARCALL64m:
8253 return true;
8254 }
8255 return false;
8256}
8257
8258bool isAESDEC128KL(unsigned Opcode) {
8259 return Opcode == AESDEC128KL;
8260}
8261
8262bool isVSUBPS(unsigned Opcode) {
8263 switch (Opcode) {
8264 case VSUBPSYrm:
8265 case VSUBPSYrr:
8266 case VSUBPSZ128rm:
8267 case VSUBPSZ128rmb:
8268 case VSUBPSZ128rmbk:
8269 case VSUBPSZ128rmbkz:
8270 case VSUBPSZ128rmk:
8271 case VSUBPSZ128rmkz:
8272 case VSUBPSZ128rr:
8273 case VSUBPSZ128rrk:
8274 case VSUBPSZ128rrkz:
8275 case VSUBPSZ256rm:
8276 case VSUBPSZ256rmb:
8277 case VSUBPSZ256rmbk:
8278 case VSUBPSZ256rmbkz:
8279 case VSUBPSZ256rmk:
8280 case VSUBPSZ256rmkz:
8281 case VSUBPSZ256rr:
8282 case VSUBPSZ256rrk:
8283 case VSUBPSZ256rrkz:
8284 case VSUBPSZrm:
8285 case VSUBPSZrmb:
8286 case VSUBPSZrmbk:
8287 case VSUBPSZrmbkz:
8288 case VSUBPSZrmk:
8289 case VSUBPSZrmkz:
8290 case VSUBPSZrr:
8291 case VSUBPSZrrb:
8292 case VSUBPSZrrbk:
8293 case VSUBPSZrrbkz:
8294 case VSUBPSZrrk:
8295 case VSUBPSZrrkz:
8296 case VSUBPSrm:
8297 case VSUBPSrr:
8298 return true;
8299 }
8300 return false;
8301}
8302
8303bool isFSTP(unsigned Opcode) {
8304 switch (Opcode) {
8305 case ST_FP32m:
8306 case ST_FP64m:
8307 case ST_FP80m:
8308 case ST_FPrr:
8309 return true;
8310 }
8311 return false;
8312}
8313
8314bool isVCVTUDQ2PD(unsigned Opcode) {
8315 switch (Opcode) {
8316 case VCVTUDQ2PDZ128rm:
8317 case VCVTUDQ2PDZ128rmb:
8318 case VCVTUDQ2PDZ128rmbk:
8319 case VCVTUDQ2PDZ128rmbkz:
8320 case VCVTUDQ2PDZ128rmk:
8321 case VCVTUDQ2PDZ128rmkz:
8322 case VCVTUDQ2PDZ128rr:
8323 case VCVTUDQ2PDZ128rrk:
8324 case VCVTUDQ2PDZ128rrkz:
8325 case VCVTUDQ2PDZ256rm:
8326 case VCVTUDQ2PDZ256rmb:
8327 case VCVTUDQ2PDZ256rmbk:
8328 case VCVTUDQ2PDZ256rmbkz:
8329 case VCVTUDQ2PDZ256rmk:
8330 case VCVTUDQ2PDZ256rmkz:
8331 case VCVTUDQ2PDZ256rr:
8332 case VCVTUDQ2PDZ256rrk:
8333 case VCVTUDQ2PDZ256rrkz:
8334 case VCVTUDQ2PDZrm:
8335 case VCVTUDQ2PDZrmb:
8336 case VCVTUDQ2PDZrmbk:
8337 case VCVTUDQ2PDZrmbkz:
8338 case VCVTUDQ2PDZrmk:
8339 case VCVTUDQ2PDZrmkz:
8340 case VCVTUDQ2PDZrr:
8341 case VCVTUDQ2PDZrrk:
8342 case VCVTUDQ2PDZrrkz:
8343 return true;
8344 }
8345 return false;
8346}
8347
8348bool isVPMOVSWB(unsigned Opcode) {
8349 switch (Opcode) {
8350 case VPMOVSWBZ128mr:
8351 case VPMOVSWBZ128mrk:
8352 case VPMOVSWBZ128rr:
8353 case VPMOVSWBZ128rrk:
8354 case VPMOVSWBZ128rrkz:
8355 case VPMOVSWBZ256mr:
8356 case VPMOVSWBZ256mrk:
8357 case VPMOVSWBZ256rr:
8358 case VPMOVSWBZ256rrk:
8359 case VPMOVSWBZ256rrkz:
8360 case VPMOVSWBZmr:
8361 case VPMOVSWBZmrk:
8362 case VPMOVSWBZrr:
8363 case VPMOVSWBZrrk:
8364 case VPMOVSWBZrrkz:
8365 return true;
8366 }
8367 return false;
8368}
8369
8370bool isVPANDNQ(unsigned Opcode) {
8371 switch (Opcode) {
8372 case VPANDNQZ128rm:
8373 case VPANDNQZ128rmb:
8374 case VPANDNQZ128rmbk:
8375 case VPANDNQZ128rmbkz:
8376 case VPANDNQZ128rmk:
8377 case VPANDNQZ128rmkz:
8378 case VPANDNQZ128rr:
8379 case VPANDNQZ128rrk:
8380 case VPANDNQZ128rrkz:
8381 case VPANDNQZ256rm:
8382 case VPANDNQZ256rmb:
8383 case VPANDNQZ256rmbk:
8384 case VPANDNQZ256rmbkz:
8385 case VPANDNQZ256rmk:
8386 case VPANDNQZ256rmkz:
8387 case VPANDNQZ256rr:
8388 case VPANDNQZ256rrk:
8389 case VPANDNQZ256rrkz:
8390 case VPANDNQZrm:
8391 case VPANDNQZrmb:
8392 case VPANDNQZrmbk:
8393 case VPANDNQZrmbkz:
8394 case VPANDNQZrmk:
8395 case VPANDNQZrmkz:
8396 case VPANDNQZrr:
8397 case VPANDNQZrrk:
8398 case VPANDNQZrrkz:
8399 return true;
8400 }
8401 return false;
8402}
8403
8404bool isSYSENTER(unsigned Opcode) {
8405 return Opcode == SYSENTER;
8406}
8407
8408bool isVPHADDWD(unsigned Opcode) {
8409 switch (Opcode) {
8410 case VPHADDWDrm:
8411 case VPHADDWDrr:
8412 return true;
8413 }
8414 return false;
8415}
8416
8417bool isVMOVHPD(unsigned Opcode) {
8418 switch (Opcode) {
8419 case VMOVHPDZ128mr:
8420 case VMOVHPDZ128rm:
8421 case VMOVHPDmr:
8422 case VMOVHPDrm:
8423 return true;
8424 }
8425 return false;
8426}
8427
8428bool isMOVHPD(unsigned Opcode) {
8429 switch (Opcode) {
8430 case MOVHPDmr:
8431 case MOVHPDrm:
8432 return true;
8433 }
8434 return false;
8435}
8436
8437bool isVDIVPH(unsigned Opcode) {
8438 switch (Opcode) {
8439 case VDIVPHZ128rm:
8440 case VDIVPHZ128rmb:
8441 case VDIVPHZ128rmbk:
8442 case VDIVPHZ128rmbkz:
8443 case VDIVPHZ128rmk:
8444 case VDIVPHZ128rmkz:
8445 case VDIVPHZ128rr:
8446 case VDIVPHZ128rrk:
8447 case VDIVPHZ128rrkz:
8448 case VDIVPHZ256rm:
8449 case VDIVPHZ256rmb:
8450 case VDIVPHZ256rmbk:
8451 case VDIVPHZ256rmbkz:
8452 case VDIVPHZ256rmk:
8453 case VDIVPHZ256rmkz:
8454 case VDIVPHZ256rr:
8455 case VDIVPHZ256rrk:
8456 case VDIVPHZ256rrkz:
8457 case VDIVPHZrm:
8458 case VDIVPHZrmb:
8459 case VDIVPHZrmbk:
8460 case VDIVPHZrmbkz:
8461 case VDIVPHZrmk:
8462 case VDIVPHZrmkz:
8463 case VDIVPHZrr:
8464 case VDIVPHZrrb:
8465 case VDIVPHZrrbk:
8466 case VDIVPHZrrbkz:
8467 case VDIVPHZrrk:
8468 case VDIVPHZrrkz:
8469 return true;
8470 }
8471 return false;
8472}
8473
8474bool isFFREE(unsigned Opcode) {
8475 return Opcode == FFREE;
8476}
8477
8478bool isVGATHERPF1DPS(unsigned Opcode) {
8479 return Opcode == VGATHERPF1DPSm;
8480}
8481
8482bool isVFNMADD231PD(unsigned Opcode) {
8483 switch (Opcode) {
8484 case VFNMADD231PDYm:
8485 case VFNMADD231PDYr:
8486 case VFNMADD231PDZ128m:
8487 case VFNMADD231PDZ128mb:
8488 case VFNMADD231PDZ128mbk:
8489 case VFNMADD231PDZ128mbkz:
8490 case VFNMADD231PDZ128mk:
8491 case VFNMADD231PDZ128mkz:
8492 case VFNMADD231PDZ128r:
8493 case VFNMADD231PDZ128rk:
8494 case VFNMADD231PDZ128rkz:
8495 case VFNMADD231PDZ256m:
8496 case VFNMADD231PDZ256mb:
8497 case VFNMADD231PDZ256mbk:
8498 case VFNMADD231PDZ256mbkz:
8499 case VFNMADD231PDZ256mk:
8500 case VFNMADD231PDZ256mkz:
8501 case VFNMADD231PDZ256r:
8502 case VFNMADD231PDZ256rk:
8503 case VFNMADD231PDZ256rkz:
8504 case VFNMADD231PDZm:
8505 case VFNMADD231PDZmb:
8506 case VFNMADD231PDZmbk:
8507 case VFNMADD231PDZmbkz:
8508 case VFNMADD231PDZmk:
8509 case VFNMADD231PDZmkz:
8510 case VFNMADD231PDZr:
8511 case VFNMADD231PDZrb:
8512 case VFNMADD231PDZrbk:
8513 case VFNMADD231PDZrbkz:
8514 case VFNMADD231PDZrk:
8515 case VFNMADD231PDZrkz:
8516 case VFNMADD231PDm:
8517 case VFNMADD231PDr:
8518 return true;
8519 }
8520 return false;
8521}
8522
8523bool isVFCMULCPH(unsigned Opcode) {
8524 switch (Opcode) {
8525 case VFCMULCPHZ128rm:
8526 case VFCMULCPHZ128rmb:
8527 case VFCMULCPHZ128rmbk:
8528 case VFCMULCPHZ128rmbkz:
8529 case VFCMULCPHZ128rmk:
8530 case VFCMULCPHZ128rmkz:
8531 case VFCMULCPHZ128rr:
8532 case VFCMULCPHZ128rrk:
8533 case VFCMULCPHZ128rrkz:
8534 case VFCMULCPHZ256rm:
8535 case VFCMULCPHZ256rmb:
8536 case VFCMULCPHZ256rmbk:
8537 case VFCMULCPHZ256rmbkz:
8538 case VFCMULCPHZ256rmk:
8539 case VFCMULCPHZ256rmkz:
8540 case VFCMULCPHZ256rr:
8541 case VFCMULCPHZ256rrk:
8542 case VFCMULCPHZ256rrkz:
8543 case VFCMULCPHZrm:
8544 case VFCMULCPHZrmb:
8545 case VFCMULCPHZrmbk:
8546 case VFCMULCPHZrmbkz:
8547 case VFCMULCPHZrmk:
8548 case VFCMULCPHZrmkz:
8549 case VFCMULCPHZrr:
8550 case VFCMULCPHZrrb:
8551 case VFCMULCPHZrrbk:
8552 case VFCMULCPHZrrbkz:
8553 case VFCMULCPHZrrk:
8554 case VFCMULCPHZrrkz:
8555 return true;
8556 }
8557 return false;
8558}
8559
8560bool isVPADDD(unsigned Opcode) {
8561 switch (Opcode) {
8562 case VPADDDYrm:
8563 case VPADDDYrr:
8564 case VPADDDZ128rm:
8565 case VPADDDZ128rmb:
8566 case VPADDDZ128rmbk:
8567 case VPADDDZ128rmbkz:
8568 case VPADDDZ128rmk:
8569 case VPADDDZ128rmkz:
8570 case VPADDDZ128rr:
8571 case VPADDDZ128rrk:
8572 case VPADDDZ128rrkz:
8573 case VPADDDZ256rm:
8574 case VPADDDZ256rmb:
8575 case VPADDDZ256rmbk:
8576 case VPADDDZ256rmbkz:
8577 case VPADDDZ256rmk:
8578 case VPADDDZ256rmkz:
8579 case VPADDDZ256rr:
8580 case VPADDDZ256rrk:
8581 case VPADDDZ256rrkz:
8582 case VPADDDZrm:
8583 case VPADDDZrmb:
8584 case VPADDDZrmbk:
8585 case VPADDDZrmbkz:
8586 case VPADDDZrmk:
8587 case VPADDDZrmkz:
8588 case VPADDDZrr:
8589 case VPADDDZrrk:
8590 case VPADDDZrrkz:
8591 case VPADDDrm:
8592 case VPADDDrr:
8593 return true;
8594 }
8595 return false;
8596}
8597
8598bool isVSM3MSG2(unsigned Opcode) {
8599 switch (Opcode) {
8600 case VSM3MSG2rm:
8601 case VSM3MSG2rr:
8602 return true;
8603 }
8604 return false;
8605}
8606
8607bool isVPCOMUQ(unsigned Opcode) {
8608 switch (Opcode) {
8609 case VPCOMUQmi:
8610 case VPCOMUQri:
8611 return true;
8612 }
8613 return false;
8614}
8615
8616bool isVERR(unsigned Opcode) {
8617 switch (Opcode) {
8618 case VERRm:
8619 case VERRr:
8620 return true;
8621 }
8622 return false;
8623}
8624
8625bool isKORTESTQ(unsigned Opcode) {
8626 return Opcode == KORTESTQrr;
8627}
8628
8629bool isVFMSUB132SD(unsigned Opcode) {
8630 switch (Opcode) {
8631 case VFMSUB132SDZm_Int:
8632 case VFMSUB132SDZm_Intk:
8633 case VFMSUB132SDZm_Intkz:
8634 case VFMSUB132SDZr_Int:
8635 case VFMSUB132SDZr_Intk:
8636 case VFMSUB132SDZr_Intkz:
8637 case VFMSUB132SDZrb_Int:
8638 case VFMSUB132SDZrb_Intk:
8639 case VFMSUB132SDZrb_Intkz:
8640 case VFMSUB132SDm_Int:
8641 case VFMSUB132SDr_Int:
8642 return true;
8643 }
8644 return false;
8645}
8646
8647bool isTILEZERO(unsigned Opcode) {
8648 return Opcode == TILEZERO;
8649}
8650
8651bool isPFADD(unsigned Opcode) {
8652 switch (Opcode) {
8653 case PFADDrm:
8654 case PFADDrr:
8655 return true;
8656 }
8657 return false;
8658}
8659
8660bool isVCVTSI2SD(unsigned Opcode) {
8661 switch (Opcode) {
8662 case VCVTSI2SDZrm_Int:
8663 case VCVTSI2SDZrr_Int:
8664 case VCVTSI2SDrm_Int:
8665 case VCVTSI2SDrr_Int:
8666 case VCVTSI642SDZrm_Int:
8667 case VCVTSI642SDZrr_Int:
8668 case VCVTSI642SDZrrb_Int:
8669 case VCVTSI642SDrm_Int:
8670 case VCVTSI642SDrr_Int:
8671 return true;
8672 }
8673 return false;
8674}
8675
8676bool isVSTMXCSR(unsigned Opcode) {
8677 return Opcode == VSTMXCSR;
8678}
8679
8680bool isVCVTTSH2SI(unsigned Opcode) {
8681 switch (Opcode) {
8682 case VCVTTSH2SI64Zrm_Int:
8683 case VCVTTSH2SI64Zrr_Int:
8684 case VCVTTSH2SI64Zrrb_Int:
8685 case VCVTTSH2SIZrm_Int:
8686 case VCVTTSH2SIZrr_Int:
8687 case VCVTTSH2SIZrrb_Int:
8688 return true;
8689 }
8690 return false;
8691}
8692
8693bool isRET(unsigned Opcode) {
8694 switch (Opcode) {
8695 case RET16:
8696 case RET32:
8697 case RET64:
8698 case RETI16:
8699 case RETI32:
8700 case RETI64:
8701 return true;
8702 }
8703 return false;
8704}
8705
8706bool isLZCNT(unsigned Opcode) {
8707 switch (Opcode) {
8708 case LZCNT16rm:
8709 case LZCNT16rm_EVEX:
8710 case LZCNT16rm_NF:
8711 case LZCNT16rr:
8712 case LZCNT16rr_EVEX:
8713 case LZCNT16rr_NF:
8714 case LZCNT32rm:
8715 case LZCNT32rm_EVEX:
8716 case LZCNT32rm_NF:
8717 case LZCNT32rr:
8718 case LZCNT32rr_EVEX:
8719 case LZCNT32rr_NF:
8720 case LZCNT64rm:
8721 case LZCNT64rm_EVEX:
8722 case LZCNT64rm_NF:
8723 case LZCNT64rr:
8724 case LZCNT64rr_EVEX:
8725 case LZCNT64rr_NF:
8726 return true;
8727 }
8728 return false;
8729}
8730
8731bool isMULPD(unsigned Opcode) {
8732 switch (Opcode) {
8733 case MULPDrm:
8734 case MULPDrr:
8735 return true;
8736 }
8737 return false;
8738}
8739
8740bool isVBROADCASTI32X2(unsigned Opcode) {
8741 switch (Opcode) {
8742 case VBROADCASTI32X2Z128rm:
8743 case VBROADCASTI32X2Z128rmk:
8744 case VBROADCASTI32X2Z128rmkz:
8745 case VBROADCASTI32X2Z128rr:
8746 case VBROADCASTI32X2Z128rrk:
8747 case VBROADCASTI32X2Z128rrkz:
8748 case VBROADCASTI32X2Z256rm:
8749 case VBROADCASTI32X2Z256rmk:
8750 case VBROADCASTI32X2Z256rmkz:
8751 case VBROADCASTI32X2Z256rr:
8752 case VBROADCASTI32X2Z256rrk:
8753 case VBROADCASTI32X2Z256rrkz:
8754 case VBROADCASTI32X2Zrm:
8755 case VBROADCASTI32X2Zrmk:
8756 case VBROADCASTI32X2Zrmkz:
8757 case VBROADCASTI32X2Zrr:
8758 case VBROADCASTI32X2Zrrk:
8759 case VBROADCASTI32X2Zrrkz:
8760 return true;
8761 }
8762 return false;
8763}
8764
8765bool isVCVTPH2W(unsigned Opcode) {
8766 switch (Opcode) {
8767 case VCVTPH2WZ128rm:
8768 case VCVTPH2WZ128rmb:
8769 case VCVTPH2WZ128rmbk:
8770 case VCVTPH2WZ128rmbkz:
8771 case VCVTPH2WZ128rmk:
8772 case VCVTPH2WZ128rmkz:
8773 case VCVTPH2WZ128rr:
8774 case VCVTPH2WZ128rrk:
8775 case VCVTPH2WZ128rrkz:
8776 case VCVTPH2WZ256rm:
8777 case VCVTPH2WZ256rmb:
8778 case VCVTPH2WZ256rmbk:
8779 case VCVTPH2WZ256rmbkz:
8780 case VCVTPH2WZ256rmk:
8781 case VCVTPH2WZ256rmkz:
8782 case VCVTPH2WZ256rr:
8783 case VCVTPH2WZ256rrk:
8784 case VCVTPH2WZ256rrkz:
8785 case VCVTPH2WZrm:
8786 case VCVTPH2WZrmb:
8787 case VCVTPH2WZrmbk:
8788 case VCVTPH2WZrmbkz:
8789 case VCVTPH2WZrmk:
8790 case VCVTPH2WZrmkz:
8791 case VCVTPH2WZrr:
8792 case VCVTPH2WZrrb:
8793 case VCVTPH2WZrrbk:
8794 case VCVTPH2WZrrbkz:
8795 case VCVTPH2WZrrk:
8796 case VCVTPH2WZrrkz:
8797 return true;
8798 }
8799 return false;
8800}
8801
8802bool isCQO(unsigned Opcode) {
8803 return Opcode == CQO;
8804}
8805
8806bool isFSUBR(unsigned Opcode) {
8807 switch (Opcode) {
8808 case SUBR_F32m:
8809 case SUBR_F64m:
8810 case SUBR_FST0r:
8811 case SUBR_FrST0:
8812 return true;
8813 }
8814 return false;
8815}
8816
8817bool isDPPD(unsigned Opcode) {
8818 switch (Opcode) {
8819 case DPPDrmi:
8820 case DPPDrri:
8821 return true;
8822 }
8823 return false;
8824}
8825
8826bool isFCOS(unsigned Opcode) {
8827 return Opcode == FCOS;
8828}
8829
8830bool isXSAVES(unsigned Opcode) {
8831 return Opcode == XSAVES;
8832}
8833
8834bool isTZCNT(unsigned Opcode) {
8835 switch (Opcode) {
8836 case TZCNT16rm:
8837 case TZCNT16rm_EVEX:
8838 case TZCNT16rm_NF:
8839 case TZCNT16rr:
8840 case TZCNT16rr_EVEX:
8841 case TZCNT16rr_NF:
8842 case TZCNT32rm:
8843 case TZCNT32rm_EVEX:
8844 case TZCNT32rm_NF:
8845 case TZCNT32rr:
8846 case TZCNT32rr_EVEX:
8847 case TZCNT32rr_NF:
8848 case TZCNT64rm:
8849 case TZCNT64rm_EVEX:
8850 case TZCNT64rm_NF:
8851 case TZCNT64rr:
8852 case TZCNT64rr_EVEX:
8853 case TZCNT64rr_NF:
8854 return true;
8855 }
8856 return false;
8857}
8858
8859bool isLJMP(unsigned Opcode) {
8860 switch (Opcode) {
8861 case FARJMP16i:
8862 case FARJMP16m:
8863 case FARJMP32i:
8864 case FARJMP64m:
8865 return true;
8866 }
8867 return false;
8868}
8869
8870bool isCMOVCC(unsigned Opcode) {
8871 switch (Opcode) {
8872 case CMOV16rm:
8873 case CMOV16rm_ND:
8874 case CMOV16rr:
8875 case CMOV16rr_ND:
8876 case CMOV32rm:
8877 case CMOV32rm_ND:
8878 case CMOV32rr:
8879 case CMOV32rr_ND:
8880 case CMOV64rm:
8881 case CMOV64rm_ND:
8882 case CMOV64rr:
8883 case CMOV64rr_ND:
8884 return true;
8885 }
8886 return false;
8887}
8888
8889bool isVCVTSS2SD(unsigned Opcode) {
8890 switch (Opcode) {
8891 case VCVTSS2SDZrm_Int:
8892 case VCVTSS2SDZrm_Intk:
8893 case VCVTSS2SDZrm_Intkz:
8894 case VCVTSS2SDZrr_Int:
8895 case VCVTSS2SDZrr_Intk:
8896 case VCVTSS2SDZrr_Intkz:
8897 case VCVTSS2SDZrrb_Int:
8898 case VCVTSS2SDZrrb_Intk:
8899 case VCVTSS2SDZrrb_Intkz:
8900 case VCVTSS2SDrm_Int:
8901 case VCVTSS2SDrr_Int:
8902 return true;
8903 }
8904 return false;
8905}
8906
8907bool isINVEPT(unsigned Opcode) {
8908 switch (Opcode) {
8909 case INVEPT32:
8910 case INVEPT64:
8911 case INVEPT64_EVEX:
8912 return true;
8913 }
8914 return false;
8915}
8916
8917bool isADDSUBPD(unsigned Opcode) {
8918 switch (Opcode) {
8919 case ADDSUBPDrm:
8920 case ADDSUBPDrr:
8921 return true;
8922 }
8923 return false;
8924}
8925
8926bool isVMOVSHDUP(unsigned Opcode) {
8927 switch (Opcode) {
8928 case VMOVSHDUPYrm:
8929 case VMOVSHDUPYrr:
8930 case VMOVSHDUPZ128rm:
8931 case VMOVSHDUPZ128rmk:
8932 case VMOVSHDUPZ128rmkz:
8933 case VMOVSHDUPZ128rr:
8934 case VMOVSHDUPZ128rrk:
8935 case VMOVSHDUPZ128rrkz:
8936 case VMOVSHDUPZ256rm:
8937 case VMOVSHDUPZ256rmk:
8938 case VMOVSHDUPZ256rmkz:
8939 case VMOVSHDUPZ256rr:
8940 case VMOVSHDUPZ256rrk:
8941 case VMOVSHDUPZ256rrkz:
8942 case VMOVSHDUPZrm:
8943 case VMOVSHDUPZrmk:
8944 case VMOVSHDUPZrmkz:
8945 case VMOVSHDUPZrr:
8946 case VMOVSHDUPZrrk:
8947 case VMOVSHDUPZrrkz:
8948 case VMOVSHDUPrm:
8949 case VMOVSHDUPrr:
8950 return true;
8951 }
8952 return false;
8953}
8954
8955bool isKSHIFTRD(unsigned Opcode) {
8956 return Opcode == KSHIFTRDri;
8957}
8958
8959bool isVPTERNLOGD(unsigned Opcode) {
8960 switch (Opcode) {
8961 case VPTERNLOGDZ128rmbi:
8962 case VPTERNLOGDZ128rmbik:
8963 case VPTERNLOGDZ128rmbikz:
8964 case VPTERNLOGDZ128rmi:
8965 case VPTERNLOGDZ128rmik:
8966 case VPTERNLOGDZ128rmikz:
8967 case VPTERNLOGDZ128rri:
8968 case VPTERNLOGDZ128rrik:
8969 case VPTERNLOGDZ128rrikz:
8970 case VPTERNLOGDZ256rmbi:
8971 case VPTERNLOGDZ256rmbik:
8972 case VPTERNLOGDZ256rmbikz:
8973 case VPTERNLOGDZ256rmi:
8974 case VPTERNLOGDZ256rmik:
8975 case VPTERNLOGDZ256rmikz:
8976 case VPTERNLOGDZ256rri:
8977 case VPTERNLOGDZ256rrik:
8978 case VPTERNLOGDZ256rrikz:
8979 case VPTERNLOGDZrmbi:
8980 case VPTERNLOGDZrmbik:
8981 case VPTERNLOGDZrmbikz:
8982 case VPTERNLOGDZrmi:
8983 case VPTERNLOGDZrmik:
8984 case VPTERNLOGDZrmikz:
8985 case VPTERNLOGDZrri:
8986 case VPTERNLOGDZrrik:
8987 case VPTERNLOGDZrrikz:
8988 return true;
8989 }
8990 return false;
8991}
8992
8993bool isPADDQ(unsigned Opcode) {
8994 switch (Opcode) {
8995 case MMX_PADDQrm:
8996 case MMX_PADDQrr:
8997 case PADDQrm:
8998 case PADDQrr:
8999 return true;
9000 }
9001 return false;
9002}
9003
9004bool isVEXTRACTI64X4(unsigned Opcode) {
9005 switch (Opcode) {
9006 case VEXTRACTI64x4Zmr:
9007 case VEXTRACTI64x4Zmrk:
9008 case VEXTRACTI64x4Zrr:
9009 case VEXTRACTI64x4Zrrk:
9010 case VEXTRACTI64x4Zrrkz:
9011 return true;
9012 }
9013 return false;
9014}
9015
9016bool isVFMSUB231SS(unsigned Opcode) {
9017 switch (Opcode) {
9018 case VFMSUB231SSZm_Int:
9019 case VFMSUB231SSZm_Intk:
9020 case VFMSUB231SSZm_Intkz:
9021 case VFMSUB231SSZr_Int:
9022 case VFMSUB231SSZr_Intk:
9023 case VFMSUB231SSZr_Intkz:
9024 case VFMSUB231SSZrb_Int:
9025 case VFMSUB231SSZrb_Intk:
9026 case VFMSUB231SSZrb_Intkz:
9027 case VFMSUB231SSm_Int:
9028 case VFMSUB231SSr_Int:
9029 return true;
9030 }
9031 return false;
9032}
9033
9034bool isVPCMPEQB(unsigned Opcode) {
9035 switch (Opcode) {
9036 case VPCMPEQBYrm:
9037 case VPCMPEQBYrr:
9038 case VPCMPEQBZ128rm:
9039 case VPCMPEQBZ128rmk:
9040 case VPCMPEQBZ128rr:
9041 case VPCMPEQBZ128rrk:
9042 case VPCMPEQBZ256rm:
9043 case VPCMPEQBZ256rmk:
9044 case VPCMPEQBZ256rr:
9045 case VPCMPEQBZ256rrk:
9046 case VPCMPEQBZrm:
9047 case VPCMPEQBZrmk:
9048 case VPCMPEQBZrr:
9049 case VPCMPEQBZrrk:
9050 case VPCMPEQBrm:
9051 case VPCMPEQBrr:
9052 return true;
9053 }
9054 return false;
9055}
9056
9057bool isLEA(unsigned Opcode) {
9058 switch (Opcode) {
9059 case LEA16r:
9060 case LEA32r:
9061 case LEA64_32r:
9062 case LEA64r:
9063 return true;
9064 }
9065 return false;
9066}
9067
9068bool isPSUBB(unsigned Opcode) {
9069 switch (Opcode) {
9070 case MMX_PSUBBrm:
9071 case MMX_PSUBBrr:
9072 case PSUBBrm:
9073 case PSUBBrr:
9074 return true;
9075 }
9076 return false;
9077}
9078
9079bool isKADDQ(unsigned Opcode) {
9080 return Opcode == KADDQrr;
9081}
9082
9083bool isMOVSX(unsigned Opcode) {
9084 switch (Opcode) {
9085 case MOVSX16rm16:
9086 case MOVSX16rm8:
9087 case MOVSX16rr16:
9088 case MOVSX16rr8:
9089 case MOVSX32rm16:
9090 case MOVSX32rm8:
9091 case MOVSX32rr16:
9092 case MOVSX32rr8:
9093 case MOVSX64rm16:
9094 case MOVSX64rm8:
9095 case MOVSX64rr16:
9096 case MOVSX64rr8:
9097 return true;
9098 }
9099 return false;
9100}
9101
9102bool isVALIGNQ(unsigned Opcode) {
9103 switch (Opcode) {
9104 case VALIGNQZ128rmbi:
9105 case VALIGNQZ128rmbik:
9106 case VALIGNQZ128rmbikz:
9107 case VALIGNQZ128rmi:
9108 case VALIGNQZ128rmik:
9109 case VALIGNQZ128rmikz:
9110 case VALIGNQZ128rri:
9111 case VALIGNQZ128rrik:
9112 case VALIGNQZ128rrikz:
9113 case VALIGNQZ256rmbi:
9114 case VALIGNQZ256rmbik:
9115 case VALIGNQZ256rmbikz:
9116 case VALIGNQZ256rmi:
9117 case VALIGNQZ256rmik:
9118 case VALIGNQZ256rmikz:
9119 case VALIGNQZ256rri:
9120 case VALIGNQZ256rrik:
9121 case VALIGNQZ256rrikz:
9122 case VALIGNQZrmbi:
9123 case VALIGNQZrmbik:
9124 case VALIGNQZrmbikz:
9125 case VALIGNQZrmi:
9126 case VALIGNQZrmik:
9127 case VALIGNQZrmikz:
9128 case VALIGNQZrri:
9129 case VALIGNQZrrik:
9130 case VALIGNQZrrikz:
9131 return true;
9132 }
9133 return false;
9134}
9135
9136bool isVCVTNE2PS2BF16(unsigned Opcode) {
9137 switch (Opcode) {
9138 case VCVTNE2PS2BF16Z128rm:
9139 case VCVTNE2PS2BF16Z128rmb:
9140 case VCVTNE2PS2BF16Z128rmbk:
9141 case VCVTNE2PS2BF16Z128rmbkz:
9142 case VCVTNE2PS2BF16Z128rmk:
9143 case VCVTNE2PS2BF16Z128rmkz:
9144 case VCVTNE2PS2BF16Z128rr:
9145 case VCVTNE2PS2BF16Z128rrk:
9146 case VCVTNE2PS2BF16Z128rrkz:
9147 case VCVTNE2PS2BF16Z256rm:
9148 case VCVTNE2PS2BF16Z256rmb:
9149 case VCVTNE2PS2BF16Z256rmbk:
9150 case VCVTNE2PS2BF16Z256rmbkz:
9151 case VCVTNE2PS2BF16Z256rmk:
9152 case VCVTNE2PS2BF16Z256rmkz:
9153 case VCVTNE2PS2BF16Z256rr:
9154 case VCVTNE2PS2BF16Z256rrk:
9155 case VCVTNE2PS2BF16Z256rrkz:
9156 case VCVTNE2PS2BF16Zrm:
9157 case VCVTNE2PS2BF16Zrmb:
9158 case VCVTNE2PS2BF16Zrmbk:
9159 case VCVTNE2PS2BF16Zrmbkz:
9160 case VCVTNE2PS2BF16Zrmk:
9161 case VCVTNE2PS2BF16Zrmkz:
9162 case VCVTNE2PS2BF16Zrr:
9163 case VCVTNE2PS2BF16Zrrk:
9164 case VCVTNE2PS2BF16Zrrkz:
9165 return true;
9166 }
9167 return false;
9168}
9169
9170bool isVPSRAW(unsigned Opcode) {
9171 switch (Opcode) {
9172 case VPSRAWYri:
9173 case VPSRAWYrm:
9174 case VPSRAWYrr:
9175 case VPSRAWZ128mi:
9176 case VPSRAWZ128mik:
9177 case VPSRAWZ128mikz:
9178 case VPSRAWZ128ri:
9179 case VPSRAWZ128rik:
9180 case VPSRAWZ128rikz:
9181 case VPSRAWZ128rm:
9182 case VPSRAWZ128rmk:
9183 case VPSRAWZ128rmkz:
9184 case VPSRAWZ128rr:
9185 case VPSRAWZ128rrk:
9186 case VPSRAWZ128rrkz:
9187 case VPSRAWZ256mi:
9188 case VPSRAWZ256mik:
9189 case VPSRAWZ256mikz:
9190 case VPSRAWZ256ri:
9191 case VPSRAWZ256rik:
9192 case VPSRAWZ256rikz:
9193 case VPSRAWZ256rm:
9194 case VPSRAWZ256rmk:
9195 case VPSRAWZ256rmkz:
9196 case VPSRAWZ256rr:
9197 case VPSRAWZ256rrk:
9198 case VPSRAWZ256rrkz:
9199 case VPSRAWZmi:
9200 case VPSRAWZmik:
9201 case VPSRAWZmikz:
9202 case VPSRAWZri:
9203 case VPSRAWZrik:
9204 case VPSRAWZrikz:
9205 case VPSRAWZrm:
9206 case VPSRAWZrmk:
9207 case VPSRAWZrmkz:
9208 case VPSRAWZrr:
9209 case VPSRAWZrrk:
9210 case VPSRAWZrrkz:
9211 case VPSRAWri:
9212 case VPSRAWrm:
9213 case VPSRAWrr:
9214 return true;
9215 }
9216 return false;
9217}
9218
9219bool isVFMSUBADD231PH(unsigned Opcode) {
9220 switch (Opcode) {
9221 case VFMSUBADD231PHZ128m:
9222 case VFMSUBADD231PHZ128mb:
9223 case VFMSUBADD231PHZ128mbk:
9224 case VFMSUBADD231PHZ128mbkz:
9225 case VFMSUBADD231PHZ128mk:
9226 case VFMSUBADD231PHZ128mkz:
9227 case VFMSUBADD231PHZ128r:
9228 case VFMSUBADD231PHZ128rk:
9229 case VFMSUBADD231PHZ128rkz:
9230 case VFMSUBADD231PHZ256m:
9231 case VFMSUBADD231PHZ256mb:
9232 case VFMSUBADD231PHZ256mbk:
9233 case VFMSUBADD231PHZ256mbkz:
9234 case VFMSUBADD231PHZ256mk:
9235 case VFMSUBADD231PHZ256mkz:
9236 case VFMSUBADD231PHZ256r:
9237 case VFMSUBADD231PHZ256rk:
9238 case VFMSUBADD231PHZ256rkz:
9239 case VFMSUBADD231PHZm:
9240 case VFMSUBADD231PHZmb:
9241 case VFMSUBADD231PHZmbk:
9242 case VFMSUBADD231PHZmbkz:
9243 case VFMSUBADD231PHZmk:
9244 case VFMSUBADD231PHZmkz:
9245 case VFMSUBADD231PHZr:
9246 case VFMSUBADD231PHZrb:
9247 case VFMSUBADD231PHZrbk:
9248 case VFMSUBADD231PHZrbkz:
9249 case VFMSUBADD231PHZrk:
9250 case VFMSUBADD231PHZrkz:
9251 return true;
9252 }
9253 return false;
9254}
9255
9256bool isCVTDQ2PS(unsigned Opcode) {
9257 switch (Opcode) {
9258 case CVTDQ2PSrm:
9259 case CVTDQ2PSrr:
9260 return true;
9261 }
9262 return false;
9263}
9264
9265bool isFBLD(unsigned Opcode) {
9266 return Opcode == FBLDm;
9267}
9268
9269bool isLMSW(unsigned Opcode) {
9270 switch (Opcode) {
9271 case LMSW16m:
9272 case LMSW16r:
9273 return true;
9274 }
9275 return false;
9276}
9277
9278bool isWRMSR(unsigned Opcode) {
9279 return Opcode == WRMSR;
9280}
9281
9282bool isMINSS(unsigned Opcode) {
9283 switch (Opcode) {
9284 case MINSSrm_Int:
9285 case MINSSrr_Int:
9286 return true;
9287 }
9288 return false;
9289}
9290
9291bool isFSCALE(unsigned Opcode) {
9292 return Opcode == FSCALE;
9293}
9294
9295bool isVFNMADD213SH(unsigned Opcode) {
9296 switch (Opcode) {
9297 case VFNMADD213SHZm_Int:
9298 case VFNMADD213SHZm_Intk:
9299 case VFNMADD213SHZm_Intkz:
9300 case VFNMADD213SHZr_Int:
9301 case VFNMADD213SHZr_Intk:
9302 case VFNMADD213SHZr_Intkz:
9303 case VFNMADD213SHZrb_Int:
9304 case VFNMADD213SHZrb_Intk:
9305 case VFNMADD213SHZrb_Intkz:
9306 return true;
9307 }
9308 return false;
9309}
9310
9311bool isIMULZU(unsigned Opcode) {
9312 switch (Opcode) {
9313 case IMULZU16rmi:
9314 case IMULZU16rmi8:
9315 case IMULZU16rri:
9316 case IMULZU16rri8:
9317 case IMULZU32rmi:
9318 case IMULZU32rmi8:
9319 case IMULZU32rri:
9320 case IMULZU32rri8:
9321 case IMULZU64rmi32:
9322 case IMULZU64rmi8:
9323 case IMULZU64rri32:
9324 case IMULZU64rri8:
9325 return true;
9326 }
9327 return false;
9328}
9329
9330bool isVPHADDUBD(unsigned Opcode) {
9331 switch (Opcode) {
9332 case VPHADDUBDrm:
9333 case VPHADDUBDrr:
9334 return true;
9335 }
9336 return false;
9337}
9338
9339bool isRDSSPQ(unsigned Opcode) {
9340 return Opcode == RDSSPQ;
9341}
9342
9343bool isLGDT(unsigned Opcode) {
9344 return Opcode == LGDT64m;
9345}
9346
9347bool isVPSHLDVD(unsigned Opcode) {
9348 switch (Opcode) {
9349 case VPSHLDVDZ128m:
9350 case VPSHLDVDZ128mb:
9351 case VPSHLDVDZ128mbk:
9352 case VPSHLDVDZ128mbkz:
9353 case VPSHLDVDZ128mk:
9354 case VPSHLDVDZ128mkz:
9355 case VPSHLDVDZ128r:
9356 case VPSHLDVDZ128rk:
9357 case VPSHLDVDZ128rkz:
9358 case VPSHLDVDZ256m:
9359 case VPSHLDVDZ256mb:
9360 case VPSHLDVDZ256mbk:
9361 case VPSHLDVDZ256mbkz:
9362 case VPSHLDVDZ256mk:
9363 case VPSHLDVDZ256mkz:
9364 case VPSHLDVDZ256r:
9365 case VPSHLDVDZ256rk:
9366 case VPSHLDVDZ256rkz:
9367 case VPSHLDVDZm:
9368 case VPSHLDVDZmb:
9369 case VPSHLDVDZmbk:
9370 case VPSHLDVDZmbkz:
9371 case VPSHLDVDZmk:
9372 case VPSHLDVDZmkz:
9373 case VPSHLDVDZr:
9374 case VPSHLDVDZrk:
9375 case VPSHLDVDZrkz:
9376 return true;
9377 }
9378 return false;
9379}
9380
9381bool isPFCMPGT(unsigned Opcode) {
9382 switch (Opcode) {
9383 case PFCMPGTrm:
9384 case PFCMPGTrr:
9385 return true;
9386 }
9387 return false;
9388}
9389
9390bool isVRNDSCALEPH(unsigned Opcode) {
9391 switch (Opcode) {
9392 case VRNDSCALEPHZ128rmbi:
9393 case VRNDSCALEPHZ128rmbik:
9394 case VRNDSCALEPHZ128rmbikz:
9395 case VRNDSCALEPHZ128rmi:
9396 case VRNDSCALEPHZ128rmik:
9397 case VRNDSCALEPHZ128rmikz:
9398 case VRNDSCALEPHZ128rri:
9399 case VRNDSCALEPHZ128rrik:
9400 case VRNDSCALEPHZ128rrikz:
9401 case VRNDSCALEPHZ256rmbi:
9402 case VRNDSCALEPHZ256rmbik:
9403 case VRNDSCALEPHZ256rmbikz:
9404 case VRNDSCALEPHZ256rmi:
9405 case VRNDSCALEPHZ256rmik:
9406 case VRNDSCALEPHZ256rmikz:
9407 case VRNDSCALEPHZ256rri:
9408 case VRNDSCALEPHZ256rrik:
9409 case VRNDSCALEPHZ256rrikz:
9410 case VRNDSCALEPHZrmbi:
9411 case VRNDSCALEPHZrmbik:
9412 case VRNDSCALEPHZrmbikz:
9413 case VRNDSCALEPHZrmi:
9414 case VRNDSCALEPHZrmik:
9415 case VRNDSCALEPHZrmikz:
9416 case VRNDSCALEPHZrri:
9417 case VRNDSCALEPHZrrib:
9418 case VRNDSCALEPHZrribk:
9419 case VRNDSCALEPHZrribkz:
9420 case VRNDSCALEPHZrrik:
9421 case VRNDSCALEPHZrrikz:
9422 return true;
9423 }
9424 return false;
9425}
9426
9427bool isJCXZ(unsigned Opcode) {
9428 return Opcode == JCXZ;
9429}
9430
9431bool isVPMOVZXBW(unsigned Opcode) {
9432 switch (Opcode) {
9433 case VPMOVZXBWYrm:
9434 case VPMOVZXBWYrr:
9435 case VPMOVZXBWZ128rm:
9436 case VPMOVZXBWZ128rmk:
9437 case VPMOVZXBWZ128rmkz:
9438 case VPMOVZXBWZ128rr:
9439 case VPMOVZXBWZ128rrk:
9440 case VPMOVZXBWZ128rrkz:
9441 case VPMOVZXBWZ256rm:
9442 case VPMOVZXBWZ256rmk:
9443 case VPMOVZXBWZ256rmkz:
9444 case VPMOVZXBWZ256rr:
9445 case VPMOVZXBWZ256rrk:
9446 case VPMOVZXBWZ256rrkz:
9447 case VPMOVZXBWZrm:
9448 case VPMOVZXBWZrmk:
9449 case VPMOVZXBWZrmkz:
9450 case VPMOVZXBWZrr:
9451 case VPMOVZXBWZrrk:
9452 case VPMOVZXBWZrrkz:
9453 case VPMOVZXBWrm:
9454 case VPMOVZXBWrr:
9455 return true;
9456 }
9457 return false;
9458}
9459
9460bool isVFMADDSUB231PD(unsigned Opcode) {
9461 switch (Opcode) {
9462 case VFMADDSUB231PDYm:
9463 case VFMADDSUB231PDYr:
9464 case VFMADDSUB231PDZ128m:
9465 case VFMADDSUB231PDZ128mb:
9466 case VFMADDSUB231PDZ128mbk:
9467 case VFMADDSUB231PDZ128mbkz:
9468 case VFMADDSUB231PDZ128mk:
9469 case VFMADDSUB231PDZ128mkz:
9470 case VFMADDSUB231PDZ128r:
9471 case VFMADDSUB231PDZ128rk:
9472 case VFMADDSUB231PDZ128rkz:
9473 case VFMADDSUB231PDZ256m:
9474 case VFMADDSUB231PDZ256mb:
9475 case VFMADDSUB231PDZ256mbk:
9476 case VFMADDSUB231PDZ256mbkz:
9477 case VFMADDSUB231PDZ256mk:
9478 case VFMADDSUB231PDZ256mkz:
9479 case VFMADDSUB231PDZ256r:
9480 case VFMADDSUB231PDZ256rk:
9481 case VFMADDSUB231PDZ256rkz:
9482 case VFMADDSUB231PDZm:
9483 case VFMADDSUB231PDZmb:
9484 case VFMADDSUB231PDZmbk:
9485 case VFMADDSUB231PDZmbkz:
9486 case VFMADDSUB231PDZmk:
9487 case VFMADDSUB231PDZmkz:
9488 case VFMADDSUB231PDZr:
9489 case VFMADDSUB231PDZrb:
9490 case VFMADDSUB231PDZrbk:
9491 case VFMADDSUB231PDZrbkz:
9492 case VFMADDSUB231PDZrk:
9493 case VFMADDSUB231PDZrkz:
9494 case VFMADDSUB231PDm:
9495 case VFMADDSUB231PDr:
9496 return true;
9497 }
9498 return false;
9499}
9500
9501bool isVBLENDMPD(unsigned Opcode) {
9502 switch (Opcode) {
9503 case VBLENDMPDZ128rm:
9504 case VBLENDMPDZ128rmb:
9505 case VBLENDMPDZ128rmbk:
9506 case VBLENDMPDZ128rmbkz:
9507 case VBLENDMPDZ128rmk:
9508 case VBLENDMPDZ128rmkz:
9509 case VBLENDMPDZ128rr:
9510 case VBLENDMPDZ128rrk:
9511 case VBLENDMPDZ128rrkz:
9512 case VBLENDMPDZ256rm:
9513 case VBLENDMPDZ256rmb:
9514 case VBLENDMPDZ256rmbk:
9515 case VBLENDMPDZ256rmbkz:
9516 case VBLENDMPDZ256rmk:
9517 case VBLENDMPDZ256rmkz:
9518 case VBLENDMPDZ256rr:
9519 case VBLENDMPDZ256rrk:
9520 case VBLENDMPDZ256rrkz:
9521 case VBLENDMPDZrm:
9522 case VBLENDMPDZrmb:
9523 case VBLENDMPDZrmbk:
9524 case VBLENDMPDZrmbkz:
9525 case VBLENDMPDZrmk:
9526 case VBLENDMPDZrmkz:
9527 case VBLENDMPDZrr:
9528 case VBLENDMPDZrrk:
9529 case VBLENDMPDZrrkz:
9530 return true;
9531 }
9532 return false;
9533}
9534
9535bool isHSUBPS(unsigned Opcode) {
9536 switch (Opcode) {
9537 case HSUBPSrm:
9538 case HSUBPSrr:
9539 return true;
9540 }
9541 return false;
9542}
9543
9544bool isPREFETCHIT0(unsigned Opcode) {
9545 return Opcode == PREFETCHIT0;
9546}
9547
9548bool isKTESTD(unsigned Opcode) {
9549 return Opcode == KTESTDrr;
9550}
9551
9552bool isVCVTNEOPH2PS(unsigned Opcode) {
9553 switch (Opcode) {
9554 case VCVTNEOPH2PSYrm:
9555 case VCVTNEOPH2PSrm:
9556 return true;
9557 }
9558 return false;
9559}
9560
9561bool isVBLENDVPD(unsigned Opcode) {
9562 switch (Opcode) {
9563 case VBLENDVPDYrmr:
9564 case VBLENDVPDYrrr:
9565 case VBLENDVPDrmr:
9566 case VBLENDVPDrrr:
9567 return true;
9568 }
9569 return false;
9570}
9571
9572bool isVCVTSS2USI(unsigned Opcode) {
9573 switch (Opcode) {
9574 case VCVTSS2USI64Zrm_Int:
9575 case VCVTSS2USI64Zrr_Int:
9576 case VCVTSS2USI64Zrrb_Int:
9577 case VCVTSS2USIZrm_Int:
9578 case VCVTSS2USIZrr_Int:
9579 case VCVTSS2USIZrrb_Int:
9580 return true;
9581 }
9582 return false;
9583}
9584
9585bool isVPANDD(unsigned Opcode) {
9586 switch (Opcode) {
9587 case VPANDDZ128rm:
9588 case VPANDDZ128rmb:
9589 case VPANDDZ128rmbk:
9590 case VPANDDZ128rmbkz:
9591 case VPANDDZ128rmk:
9592 case VPANDDZ128rmkz:
9593 case VPANDDZ128rr:
9594 case VPANDDZ128rrk:
9595 case VPANDDZ128rrkz:
9596 case VPANDDZ256rm:
9597 case VPANDDZ256rmb:
9598 case VPANDDZ256rmbk:
9599 case VPANDDZ256rmbkz:
9600 case VPANDDZ256rmk:
9601 case VPANDDZ256rmkz:
9602 case VPANDDZ256rr:
9603 case VPANDDZ256rrk:
9604 case VPANDDZ256rrkz:
9605 case VPANDDZrm:
9606 case VPANDDZrmb:
9607 case VPANDDZrmbk:
9608 case VPANDDZrmbkz:
9609 case VPANDDZrmk:
9610 case VPANDDZrmkz:
9611 case VPANDDZrr:
9612 case VPANDDZrrk:
9613 case VPANDDZrrkz:
9614 return true;
9615 }
9616 return false;
9617}
9618
9619bool isPMINSW(unsigned Opcode) {
9620 switch (Opcode) {
9621 case MMX_PMINSWrm:
9622 case MMX_PMINSWrr:
9623 case PMINSWrm:
9624 case PMINSWrr:
9625 return true;
9626 }
9627 return false;
9628}
9629
9630bool isSTAC(unsigned Opcode) {
9631 return Opcode == STAC;
9632}
9633
9634bool isVFMSUB213PS(unsigned Opcode) {
9635 switch (Opcode) {
9636 case VFMSUB213PSYm:
9637 case VFMSUB213PSYr:
9638 case VFMSUB213PSZ128m:
9639 case VFMSUB213PSZ128mb:
9640 case VFMSUB213PSZ128mbk:
9641 case VFMSUB213PSZ128mbkz:
9642 case VFMSUB213PSZ128mk:
9643 case VFMSUB213PSZ128mkz:
9644 case VFMSUB213PSZ128r:
9645 case VFMSUB213PSZ128rk:
9646 case VFMSUB213PSZ128rkz:
9647 case VFMSUB213PSZ256m:
9648 case VFMSUB213PSZ256mb:
9649 case VFMSUB213PSZ256mbk:
9650 case VFMSUB213PSZ256mbkz:
9651 case VFMSUB213PSZ256mk:
9652 case VFMSUB213PSZ256mkz:
9653 case VFMSUB213PSZ256r:
9654 case VFMSUB213PSZ256rk:
9655 case VFMSUB213PSZ256rkz:
9656 case VFMSUB213PSZm:
9657 case VFMSUB213PSZmb:
9658 case VFMSUB213PSZmbk:
9659 case VFMSUB213PSZmbkz:
9660 case VFMSUB213PSZmk:
9661 case VFMSUB213PSZmkz:
9662 case VFMSUB213PSZr:
9663 case VFMSUB213PSZrb:
9664 case VFMSUB213PSZrbk:
9665 case VFMSUB213PSZrbkz:
9666 case VFMSUB213PSZrk:
9667 case VFMSUB213PSZrkz:
9668 case VFMSUB213PSm:
9669 case VFMSUB213PSr:
9670 return true;
9671 }
9672 return false;
9673}
9674
9675bool isPOPAL(unsigned Opcode) {
9676 return Opcode == POPA32;
9677}
9678
9679bool isVCVTPS2UQQ(unsigned Opcode) {
9680 switch (Opcode) {
9681 case VCVTPS2UQQZ128rm:
9682 case VCVTPS2UQQZ128rmb:
9683 case VCVTPS2UQQZ128rmbk:
9684 case VCVTPS2UQQZ128rmbkz:
9685 case VCVTPS2UQQZ128rmk:
9686 case VCVTPS2UQQZ128rmkz:
9687 case VCVTPS2UQQZ128rr:
9688 case VCVTPS2UQQZ128rrk:
9689 case VCVTPS2UQQZ128rrkz:
9690 case VCVTPS2UQQZ256rm:
9691 case VCVTPS2UQQZ256rmb:
9692 case VCVTPS2UQQZ256rmbk:
9693 case VCVTPS2UQQZ256rmbkz:
9694 case VCVTPS2UQQZ256rmk:
9695 case VCVTPS2UQQZ256rmkz:
9696 case VCVTPS2UQQZ256rr:
9697 case VCVTPS2UQQZ256rrk:
9698 case VCVTPS2UQQZ256rrkz:
9699 case VCVTPS2UQQZrm:
9700 case VCVTPS2UQQZrmb:
9701 case VCVTPS2UQQZrmbk:
9702 case VCVTPS2UQQZrmbkz:
9703 case VCVTPS2UQQZrmk:
9704 case VCVTPS2UQQZrmkz:
9705 case VCVTPS2UQQZrr:
9706 case VCVTPS2UQQZrrb:
9707 case VCVTPS2UQQZrrbk:
9708 case VCVTPS2UQQZrrbkz:
9709 case VCVTPS2UQQZrrk:
9710 case VCVTPS2UQQZrrkz:
9711 return true;
9712 }
9713 return false;
9714}
9715
9716bool isRDRAND(unsigned Opcode) {
9717 switch (Opcode) {
9718 case RDRAND16r:
9719 case RDRAND32r:
9720 case RDRAND64r:
9721 return true;
9722 }
9723 return false;
9724}
9725
9726bool isJCC(unsigned Opcode) {
9727 switch (Opcode) {
9728 case JCC_1:
9729 case JCC_2:
9730 case JCC_4:
9731 return true;
9732 }
9733 return false;
9734}
9735
9736bool isVPMINSQ(unsigned Opcode) {
9737 switch (Opcode) {
9738 case VPMINSQZ128rm:
9739 case VPMINSQZ128rmb:
9740 case VPMINSQZ128rmbk:
9741 case VPMINSQZ128rmbkz:
9742 case VPMINSQZ128rmk:
9743 case VPMINSQZ128rmkz:
9744 case VPMINSQZ128rr:
9745 case VPMINSQZ128rrk:
9746 case VPMINSQZ128rrkz:
9747 case VPMINSQZ256rm:
9748 case VPMINSQZ256rmb:
9749 case VPMINSQZ256rmbk:
9750 case VPMINSQZ256rmbkz:
9751 case VPMINSQZ256rmk:
9752 case VPMINSQZ256rmkz:
9753 case VPMINSQZ256rr:
9754 case VPMINSQZ256rrk:
9755 case VPMINSQZ256rrkz:
9756 case VPMINSQZrm:
9757 case VPMINSQZrmb:
9758 case VPMINSQZrmbk:
9759 case VPMINSQZrmbkz:
9760 case VPMINSQZrmk:
9761 case VPMINSQZrmkz:
9762 case VPMINSQZrr:
9763 case VPMINSQZrrk:
9764 case VPMINSQZrrkz:
9765 return true;
9766 }
9767 return false;
9768}
9769
9770bool isVADDSD(unsigned Opcode) {
9771 switch (Opcode) {
9772 case VADDSDZrm_Int:
9773 case VADDSDZrm_Intk:
9774 case VADDSDZrm_Intkz:
9775 case VADDSDZrr_Int:
9776 case VADDSDZrr_Intk:
9777 case VADDSDZrr_Intkz:
9778 case VADDSDZrrb_Int:
9779 case VADDSDZrrb_Intk:
9780 case VADDSDZrrb_Intkz:
9781 case VADDSDrm_Int:
9782 case VADDSDrr_Int:
9783 return true;
9784 }
9785 return false;
9786}
9787
9788bool isDPPS(unsigned Opcode) {
9789 switch (Opcode) {
9790 case DPPSrmi:
9791 case DPPSrri:
9792 return true;
9793 }
9794 return false;
9795}
9796
9797bool isPINSRQ(unsigned Opcode) {
9798 switch (Opcode) {
9799 case PINSRQrm:
9800 case PINSRQrr:
9801 return true;
9802 }
9803 return false;
9804}
9805
9806bool isVUCOMISS(unsigned Opcode) {
9807 switch (Opcode) {
9808 case VUCOMISSZrm:
9809 case VUCOMISSZrr:
9810 case VUCOMISSZrrb:
9811 case VUCOMISSrm:
9812 case VUCOMISSrr:
9813 return true;
9814 }
9815 return false;
9816}
9817
9818bool isVPDPWSUD(unsigned Opcode) {
9819 switch (Opcode) {
9820 case VPDPWSUDYrm:
9821 case VPDPWSUDYrr:
9822 case VPDPWSUDrm:
9823 case VPDPWSUDrr:
9824 return true;
9825 }
9826 return false;
9827}
9828
9829bool isKANDNW(unsigned Opcode) {
9830 return Opcode == KANDNWrr;
9831}
9832
9833bool isAOR(unsigned Opcode) {
9834 switch (Opcode) {
9835 case AOR32mr:
9836 case AOR32mr_EVEX:
9837 case AOR64mr:
9838 case AOR64mr_EVEX:
9839 return true;
9840 }
9841 return false;
9842}
9843
9844bool isPMAXUB(unsigned Opcode) {
9845 switch (Opcode) {
9846 case MMX_PMAXUBrm:
9847 case MMX_PMAXUBrr:
9848 case PMAXUBrm:
9849 case PMAXUBrr:
9850 return true;
9851 }
9852 return false;
9853}
9854
9855bool isANDNPD(unsigned Opcode) {
9856 switch (Opcode) {
9857 case ANDNPDrm:
9858 case ANDNPDrr:
9859 return true;
9860 }
9861 return false;
9862}
9863
9864bool isINVPCID(unsigned Opcode) {
9865 switch (Opcode) {
9866 case INVPCID32:
9867 case INVPCID64:
9868 case INVPCID64_EVEX:
9869 return true;
9870 }
9871 return false;
9872}
9873
9874bool isRDGSBASE(unsigned Opcode) {
9875 switch (Opcode) {
9876 case RDGSBASE:
9877 case RDGSBASE64:
9878 return true;
9879 }
9880 return false;
9881}
9882
9883bool isVPMOVSQD(unsigned Opcode) {
9884 switch (Opcode) {
9885 case VPMOVSQDZ128mr:
9886 case VPMOVSQDZ128mrk:
9887 case VPMOVSQDZ128rr:
9888 case VPMOVSQDZ128rrk:
9889 case VPMOVSQDZ128rrkz:
9890 case VPMOVSQDZ256mr:
9891 case VPMOVSQDZ256mrk:
9892 case VPMOVSQDZ256rr:
9893 case VPMOVSQDZ256rrk:
9894 case VPMOVSQDZ256rrkz:
9895 case VPMOVSQDZmr:
9896 case VPMOVSQDZmrk:
9897 case VPMOVSQDZrr:
9898 case VPMOVSQDZrrk:
9899 case VPMOVSQDZrrkz:
9900 return true;
9901 }
9902 return false;
9903}
9904
9905bool isBT(unsigned Opcode) {
9906 switch (Opcode) {
9907 case BT16mi8:
9908 case BT16mr:
9909 case BT16ri8:
9910 case BT16rr:
9911 case BT32mi8:
9912 case BT32mr:
9913 case BT32ri8:
9914 case BT32rr:
9915 case BT64mi8:
9916 case BT64mr:
9917 case BT64ri8:
9918 case BT64rr:
9919 return true;
9920 }
9921 return false;
9922}
9923
9924bool isVPROLVQ(unsigned Opcode) {
9925 switch (Opcode) {
9926 case VPROLVQZ128rm:
9927 case VPROLVQZ128rmb:
9928 case VPROLVQZ128rmbk:
9929 case VPROLVQZ128rmbkz:
9930 case VPROLVQZ128rmk:
9931 case VPROLVQZ128rmkz:
9932 case VPROLVQZ128rr:
9933 case VPROLVQZ128rrk:
9934 case VPROLVQZ128rrkz:
9935 case VPROLVQZ256rm:
9936 case VPROLVQZ256rmb:
9937 case VPROLVQZ256rmbk:
9938 case VPROLVQZ256rmbkz:
9939 case VPROLVQZ256rmk:
9940 case VPROLVQZ256rmkz:
9941 case VPROLVQZ256rr:
9942 case VPROLVQZ256rrk:
9943 case VPROLVQZ256rrkz:
9944 case VPROLVQZrm:
9945 case VPROLVQZrmb:
9946 case VPROLVQZrmbk:
9947 case VPROLVQZrmbkz:
9948 case VPROLVQZrmk:
9949 case VPROLVQZrmkz:
9950 case VPROLVQZrr:
9951 case VPROLVQZrrk:
9952 case VPROLVQZrrkz:
9953 return true;
9954 }
9955 return false;
9956}
9957
9958bool isVFMADDSUB132PD(unsigned Opcode) {
9959 switch (Opcode) {
9960 case VFMADDSUB132PDYm:
9961 case VFMADDSUB132PDYr:
9962 case VFMADDSUB132PDZ128m:
9963 case VFMADDSUB132PDZ128mb:
9964 case VFMADDSUB132PDZ128mbk:
9965 case VFMADDSUB132PDZ128mbkz:
9966 case VFMADDSUB132PDZ128mk:
9967 case VFMADDSUB132PDZ128mkz:
9968 case VFMADDSUB132PDZ128r:
9969 case VFMADDSUB132PDZ128rk:
9970 case VFMADDSUB132PDZ128rkz:
9971 case VFMADDSUB132PDZ256m:
9972 case VFMADDSUB132PDZ256mb:
9973 case VFMADDSUB132PDZ256mbk:
9974 case VFMADDSUB132PDZ256mbkz:
9975 case VFMADDSUB132PDZ256mk:
9976 case VFMADDSUB132PDZ256mkz:
9977 case VFMADDSUB132PDZ256r:
9978 case VFMADDSUB132PDZ256rk:
9979 case VFMADDSUB132PDZ256rkz:
9980 case VFMADDSUB132PDZm:
9981 case VFMADDSUB132PDZmb:
9982 case VFMADDSUB132PDZmbk:
9983 case VFMADDSUB132PDZmbkz:
9984 case VFMADDSUB132PDZmk:
9985 case VFMADDSUB132PDZmkz:
9986 case VFMADDSUB132PDZr:
9987 case VFMADDSUB132PDZrb:
9988 case VFMADDSUB132PDZrbk:
9989 case VFMADDSUB132PDZrbkz:
9990 case VFMADDSUB132PDZrk:
9991 case VFMADDSUB132PDZrkz:
9992 case VFMADDSUB132PDm:
9993 case VFMADDSUB132PDr:
9994 return true;
9995 }
9996 return false;
9997}
9998
9999bool isRORX(unsigned Opcode) {
10000 switch (Opcode) {
10001 case RORX32mi:
10002 case RORX32mi_EVEX:
10003 case RORX32ri:
10004 case RORX32ri_EVEX:
10005 case RORX64mi:
10006 case RORX64mi_EVEX:
10007 case RORX64ri:
10008 case RORX64ri_EVEX:
10009 return true;
10010 }
10011 return false;
10012}
10013
10014bool isPADDUSW(unsigned Opcode) {
10015 switch (Opcode) {
10016 case MMX_PADDUSWrm:
10017 case MMX_PADDUSWrr:
10018 case PADDUSWrm:
10019 case PADDUSWrr:
10020 return true;
10021 }
10022 return false;
10023}
10024
10025bool isPFNACC(unsigned Opcode) {
10026 switch (Opcode) {
10027 case PFNACCrm:
10028 case PFNACCrr:
10029 return true;
10030 }
10031 return false;
10032}
10033
10034bool isAND(unsigned Opcode) {
10035 switch (Opcode) {
10036 case AND16i16:
10037 case AND16mi:
10038 case AND16mi8:
10039 case AND16mi8_EVEX:
10040 case AND16mi8_ND:
10041 case AND16mi8_NF:
10042 case AND16mi8_NF_ND:
10043 case AND16mi_EVEX:
10044 case AND16mi_ND:
10045 case AND16mi_NF:
10046 case AND16mi_NF_ND:
10047 case AND16mr:
10048 case AND16mr_EVEX:
10049 case AND16mr_ND:
10050 case AND16mr_NF:
10051 case AND16mr_NF_ND:
10052 case AND16ri:
10053 case AND16ri8:
10054 case AND16ri8_EVEX:
10055 case AND16ri8_ND:
10056 case AND16ri8_NF:
10057 case AND16ri8_NF_ND:
10058 case AND16ri_EVEX:
10059 case AND16ri_ND:
10060 case AND16ri_NF:
10061 case AND16ri_NF_ND:
10062 case AND16rm:
10063 case AND16rm_EVEX:
10064 case AND16rm_ND:
10065 case AND16rm_NF:
10066 case AND16rm_NF_ND:
10067 case AND16rr:
10068 case AND16rr_EVEX:
10069 case AND16rr_EVEX_REV:
10070 case AND16rr_ND:
10071 case AND16rr_ND_REV:
10072 case AND16rr_NF:
10073 case AND16rr_NF_ND:
10074 case AND16rr_NF_ND_REV:
10075 case AND16rr_NF_REV:
10076 case AND16rr_REV:
10077 case AND32i32:
10078 case AND32mi:
10079 case AND32mi8:
10080 case AND32mi8_EVEX:
10081 case AND32mi8_ND:
10082 case AND32mi8_NF:
10083 case AND32mi8_NF_ND:
10084 case AND32mi_EVEX:
10085 case AND32mi_ND:
10086 case AND32mi_NF:
10087 case AND32mi_NF_ND:
10088 case AND32mr:
10089 case AND32mr_EVEX:
10090 case AND32mr_ND:
10091 case AND32mr_NF:
10092 case AND32mr_NF_ND:
10093 case AND32ri:
10094 case AND32ri8:
10095 case AND32ri8_EVEX:
10096 case AND32ri8_ND:
10097 case AND32ri8_NF:
10098 case AND32ri8_NF_ND:
10099 case AND32ri_EVEX:
10100 case AND32ri_ND:
10101 case AND32ri_NF:
10102 case AND32ri_NF_ND:
10103 case AND32rm:
10104 case AND32rm_EVEX:
10105 case AND32rm_ND:
10106 case AND32rm_NF:
10107 case AND32rm_NF_ND:
10108 case AND32rr:
10109 case AND32rr_EVEX:
10110 case AND32rr_EVEX_REV:
10111 case AND32rr_ND:
10112 case AND32rr_ND_REV:
10113 case AND32rr_NF:
10114 case AND32rr_NF_ND:
10115 case AND32rr_NF_ND_REV:
10116 case AND32rr_NF_REV:
10117 case AND32rr_REV:
10118 case AND64i32:
10119 case AND64mi32:
10120 case AND64mi32_EVEX:
10121 case AND64mi32_ND:
10122 case AND64mi32_NF:
10123 case AND64mi32_NF_ND:
10124 case AND64mi8:
10125 case AND64mi8_EVEX:
10126 case AND64mi8_ND:
10127 case AND64mi8_NF:
10128 case AND64mi8_NF_ND:
10129 case AND64mr:
10130 case AND64mr_EVEX:
10131 case AND64mr_ND:
10132 case AND64mr_NF:
10133 case AND64mr_NF_ND:
10134 case AND64ri32:
10135 case AND64ri32_EVEX:
10136 case AND64ri32_ND:
10137 case AND64ri32_NF:
10138 case AND64ri32_NF_ND:
10139 case AND64ri8:
10140 case AND64ri8_EVEX:
10141 case AND64ri8_ND:
10142 case AND64ri8_NF:
10143 case AND64ri8_NF_ND:
10144 case AND64rm:
10145 case AND64rm_EVEX:
10146 case AND64rm_ND:
10147 case AND64rm_NF:
10148 case AND64rm_NF_ND:
10149 case AND64rr:
10150 case AND64rr_EVEX:
10151 case AND64rr_EVEX_REV:
10152 case AND64rr_ND:
10153 case AND64rr_ND_REV:
10154 case AND64rr_NF:
10155 case AND64rr_NF_ND:
10156 case AND64rr_NF_ND_REV:
10157 case AND64rr_NF_REV:
10158 case AND64rr_REV:
10159 case AND8i8:
10160 case AND8mi:
10161 case AND8mi8:
10162 case AND8mi_EVEX:
10163 case AND8mi_ND:
10164 case AND8mi_NF:
10165 case AND8mi_NF_ND:
10166 case AND8mr:
10167 case AND8mr_EVEX:
10168 case AND8mr_ND:
10169 case AND8mr_NF:
10170 case AND8mr_NF_ND:
10171 case AND8ri:
10172 case AND8ri8:
10173 case AND8ri_EVEX:
10174 case AND8ri_ND:
10175 case AND8ri_NF:
10176 case AND8ri_NF_ND:
10177 case AND8rm:
10178 case AND8rm_EVEX:
10179 case AND8rm_ND:
10180 case AND8rm_NF:
10181 case AND8rm_NF_ND:
10182 case AND8rr:
10183 case AND8rr_EVEX:
10184 case AND8rr_EVEX_REV:
10185 case AND8rr_ND:
10186 case AND8rr_ND_REV:
10187 case AND8rr_NF:
10188 case AND8rr_NF_ND:
10189 case AND8rr_NF_ND_REV:
10190 case AND8rr_NF_REV:
10191 case AND8rr_REV:
10192 return true;
10193 }
10194 return false;
10195}
10196
10197bool isPSLLQ(unsigned Opcode) {
10198 switch (Opcode) {
10199 case MMX_PSLLQri:
10200 case MMX_PSLLQrm:
10201 case MMX_PSLLQrr:
10202 case PSLLQri:
10203 case PSLLQrm:
10204 case PSLLQrr:
10205 return true;
10206 }
10207 return false;
10208}
10209
10210bool isVFMSUB132PH(unsigned Opcode) {
10211 switch (Opcode) {
10212 case VFMSUB132PHZ128m:
10213 case VFMSUB132PHZ128mb:
10214 case VFMSUB132PHZ128mbk:
10215 case VFMSUB132PHZ128mbkz:
10216 case VFMSUB132PHZ128mk:
10217 case VFMSUB132PHZ128mkz:
10218 case VFMSUB132PHZ128r:
10219 case VFMSUB132PHZ128rk:
10220 case VFMSUB132PHZ128rkz:
10221 case VFMSUB132PHZ256m:
10222 case VFMSUB132PHZ256mb:
10223 case VFMSUB132PHZ256mbk:
10224 case VFMSUB132PHZ256mbkz:
10225 case VFMSUB132PHZ256mk:
10226 case VFMSUB132PHZ256mkz:
10227 case VFMSUB132PHZ256r:
10228 case VFMSUB132PHZ256rk:
10229 case VFMSUB132PHZ256rkz:
10230 case VFMSUB132PHZm:
10231 case VFMSUB132PHZmb:
10232 case VFMSUB132PHZmbk:
10233 case VFMSUB132PHZmbkz:
10234 case VFMSUB132PHZmk:
10235 case VFMSUB132PHZmkz:
10236 case VFMSUB132PHZr:
10237 case VFMSUB132PHZrb:
10238 case VFMSUB132PHZrbk:
10239 case VFMSUB132PHZrbkz:
10240 case VFMSUB132PHZrk:
10241 case VFMSUB132PHZrkz:
10242 return true;
10243 }
10244 return false;
10245}
10246
10247bool isXSAVE(unsigned Opcode) {
10248 return Opcode == XSAVE;
10249}
10250
10251bool isKNOTQ(unsigned Opcode) {
10252 return Opcode == KNOTQrr;
10253}
10254
10255bool isXTEST(unsigned Opcode) {
10256 return Opcode == XTEST;
10257}
10258
10259bool isVINSERTPS(unsigned Opcode) {
10260 switch (Opcode) {
10261 case VINSERTPSZrm:
10262 case VINSERTPSZrr:
10263 case VINSERTPSrm:
10264 case VINSERTPSrr:
10265 return true;
10266 }
10267 return false;
10268}
10269
10270bool isXSAVEOPT(unsigned Opcode) {
10271 return Opcode == XSAVEOPT;
10272}
10273
10274bool isLDS(unsigned Opcode) {
10275 switch (Opcode) {
10276 case LDS16rm:
10277 case LDS32rm:
10278 return true;
10279 }
10280 return false;
10281}
10282
10283bool isVFMADDSUB213PD(unsigned Opcode) {
10284 switch (Opcode) {
10285 case VFMADDSUB213PDYm:
10286 case VFMADDSUB213PDYr:
10287 case VFMADDSUB213PDZ128m:
10288 case VFMADDSUB213PDZ128mb:
10289 case VFMADDSUB213PDZ128mbk:
10290 case VFMADDSUB213PDZ128mbkz:
10291 case VFMADDSUB213PDZ128mk:
10292 case VFMADDSUB213PDZ128mkz:
10293 case VFMADDSUB213PDZ128r:
10294 case VFMADDSUB213PDZ128rk:
10295 case VFMADDSUB213PDZ128rkz:
10296 case VFMADDSUB213PDZ256m:
10297 case VFMADDSUB213PDZ256mb:
10298 case VFMADDSUB213PDZ256mbk:
10299 case VFMADDSUB213PDZ256mbkz:
10300 case VFMADDSUB213PDZ256mk:
10301 case VFMADDSUB213PDZ256mkz:
10302 case VFMADDSUB213PDZ256r:
10303 case VFMADDSUB213PDZ256rk:
10304 case VFMADDSUB213PDZ256rkz:
10305 case VFMADDSUB213PDZm:
10306 case VFMADDSUB213PDZmb:
10307 case VFMADDSUB213PDZmbk:
10308 case VFMADDSUB213PDZmbkz:
10309 case VFMADDSUB213PDZmk:
10310 case VFMADDSUB213PDZmkz:
10311 case VFMADDSUB213PDZr:
10312 case VFMADDSUB213PDZrb:
10313 case VFMADDSUB213PDZrbk:
10314 case VFMADDSUB213PDZrbkz:
10315 case VFMADDSUB213PDZrk:
10316 case VFMADDSUB213PDZrkz:
10317 case VFMADDSUB213PDm:
10318 case VFMADDSUB213PDr:
10319 return true;
10320 }
10321 return false;
10322}
10323
10324bool isVINSERTF32X4(unsigned Opcode) {
10325 switch (Opcode) {
10326 case VINSERTF32x4Z256rm:
10327 case VINSERTF32x4Z256rmk:
10328 case VINSERTF32x4Z256rmkz:
10329 case VINSERTF32x4Z256rr:
10330 case VINSERTF32x4Z256rrk:
10331 case VINSERTF32x4Z256rrkz:
10332 case VINSERTF32x4Zrm:
10333 case VINSERTF32x4Zrmk:
10334 case VINSERTF32x4Zrmkz:
10335 case VINSERTF32x4Zrr:
10336 case VINSERTF32x4Zrrk:
10337 case VINSERTF32x4Zrrkz:
10338 return true;
10339 }
10340 return false;
10341}
10342
10343bool isVRSQRTPS(unsigned Opcode) {
10344 switch (Opcode) {
10345 case VRSQRTPSYm:
10346 case VRSQRTPSYr:
10347 case VRSQRTPSm:
10348 case VRSQRTPSr:
10349 return true;
10350 }
10351 return false;
10352}
10353
10354bool isVSUBPH(unsigned Opcode) {
10355 switch (Opcode) {
10356 case VSUBPHZ128rm:
10357 case VSUBPHZ128rmb:
10358 case VSUBPHZ128rmbk:
10359 case VSUBPHZ128rmbkz:
10360 case VSUBPHZ128rmk:
10361 case VSUBPHZ128rmkz:
10362 case VSUBPHZ128rr:
10363 case VSUBPHZ128rrk:
10364 case VSUBPHZ128rrkz:
10365 case VSUBPHZ256rm:
10366 case VSUBPHZ256rmb:
10367 case VSUBPHZ256rmbk:
10368 case VSUBPHZ256rmbkz:
10369 case VSUBPHZ256rmk:
10370 case VSUBPHZ256rmkz:
10371 case VSUBPHZ256rr:
10372 case VSUBPHZ256rrk:
10373 case VSUBPHZ256rrkz:
10374 case VSUBPHZrm:
10375 case VSUBPHZrmb:
10376 case VSUBPHZrmbk:
10377 case VSUBPHZrmbkz:
10378 case VSUBPHZrmk:
10379 case VSUBPHZrmkz:
10380 case VSUBPHZrr:
10381 case VSUBPHZrrb:
10382 case VSUBPHZrrbk:
10383 case VSUBPHZrrbkz:
10384 case VSUBPHZrrk:
10385 case VSUBPHZrrkz:
10386 return true;
10387 }
10388 return false;
10389}
10390
10391bool isPMOVSXBW(unsigned Opcode) {
10392 switch (Opcode) {
10393 case PMOVSXBWrm:
10394 case PMOVSXBWrr:
10395 return true;
10396 }
10397 return false;
10398}
10399
10400bool isVPSRLDQ(unsigned Opcode) {
10401 switch (Opcode) {
10402 case VPSRLDQYri:
10403 case VPSRLDQZ128mi:
10404 case VPSRLDQZ128ri:
10405 case VPSRLDQZ256mi:
10406 case VPSRLDQZ256ri:
10407 case VPSRLDQZmi:
10408 case VPSRLDQZri:
10409 case VPSRLDQri:
10410 return true;
10411 }
10412 return false;
10413}
10414
10415bool isADC(unsigned Opcode) {
10416 switch (Opcode) {
10417 case ADC16i16:
10418 case ADC16mi:
10419 case ADC16mi8:
10420 case ADC16mi8_EVEX:
10421 case ADC16mi8_ND:
10422 case ADC16mi_EVEX:
10423 case ADC16mi_ND:
10424 case ADC16mr:
10425 case ADC16mr_EVEX:
10426 case ADC16mr_ND:
10427 case ADC16ri:
10428 case ADC16ri8:
10429 case ADC16ri8_EVEX:
10430 case ADC16ri8_ND:
10431 case ADC16ri_EVEX:
10432 case ADC16ri_ND:
10433 case ADC16rm:
10434 case ADC16rm_EVEX:
10435 case ADC16rm_ND:
10436 case ADC16rr:
10437 case ADC16rr_EVEX:
10438 case ADC16rr_EVEX_REV:
10439 case ADC16rr_ND:
10440 case ADC16rr_ND_REV:
10441 case ADC16rr_REV:
10442 case ADC32i32:
10443 case ADC32mi:
10444 case ADC32mi8:
10445 case ADC32mi8_EVEX:
10446 case ADC32mi8_ND:
10447 case ADC32mi_EVEX:
10448 case ADC32mi_ND:
10449 case ADC32mr:
10450 case ADC32mr_EVEX:
10451 case ADC32mr_ND:
10452 case ADC32ri:
10453 case ADC32ri8:
10454 case ADC32ri8_EVEX:
10455 case ADC32ri8_ND:
10456 case ADC32ri_EVEX:
10457 case ADC32ri_ND:
10458 case ADC32rm:
10459 case ADC32rm_EVEX:
10460 case ADC32rm_ND:
10461 case ADC32rr:
10462 case ADC32rr_EVEX:
10463 case ADC32rr_EVEX_REV:
10464 case ADC32rr_ND:
10465 case ADC32rr_ND_REV:
10466 case ADC32rr_REV:
10467 case ADC64i32:
10468 case ADC64mi32:
10469 case ADC64mi32_EVEX:
10470 case ADC64mi32_ND:
10471 case ADC64mi8:
10472 case ADC64mi8_EVEX:
10473 case ADC64mi8_ND:
10474 case ADC64mr:
10475 case ADC64mr_EVEX:
10476 case ADC64mr_ND:
10477 case ADC64ri32:
10478 case ADC64ri32_EVEX:
10479 case ADC64ri32_ND:
10480 case ADC64ri8:
10481 case ADC64ri8_EVEX:
10482 case ADC64ri8_ND:
10483 case ADC64rm:
10484 case ADC64rm_EVEX:
10485 case ADC64rm_ND:
10486 case ADC64rr:
10487 case ADC64rr_EVEX:
10488 case ADC64rr_EVEX_REV:
10489 case ADC64rr_ND:
10490 case ADC64rr_ND_REV:
10491 case ADC64rr_REV:
10492 case ADC8i8:
10493 case ADC8mi:
10494 case ADC8mi8:
10495 case ADC8mi_EVEX:
10496 case ADC8mi_ND:
10497 case ADC8mr:
10498 case ADC8mr_EVEX:
10499 case ADC8mr_ND:
10500 case ADC8ri:
10501 case ADC8ri8:
10502 case ADC8ri_EVEX:
10503 case ADC8ri_ND:
10504 case ADC8rm:
10505 case ADC8rm_EVEX:
10506 case ADC8rm_ND:
10507 case ADC8rr:
10508 case ADC8rr_EVEX:
10509 case ADC8rr_EVEX_REV:
10510 case ADC8rr_ND:
10511 case ADC8rr_ND_REV:
10512 case ADC8rr_REV:
10513 return true;
10514 }
10515 return false;
10516}
10517
10518bool isPHADDD(unsigned Opcode) {
10519 switch (Opcode) {
10520 case MMX_PHADDDrm:
10521 case MMX_PHADDDrr:
10522 case PHADDDrm:
10523 case PHADDDrr:
10524 return true;
10525 }
10526 return false;
10527}
10528
10529bool isVMINPH(unsigned Opcode) {
10530 switch (Opcode) {
10531 case VMINPHZ128rm:
10532 case VMINPHZ128rmb:
10533 case VMINPHZ128rmbk:
10534 case VMINPHZ128rmbkz:
10535 case VMINPHZ128rmk:
10536 case VMINPHZ128rmkz:
10537 case VMINPHZ128rr:
10538 case VMINPHZ128rrk:
10539 case VMINPHZ128rrkz:
10540 case VMINPHZ256rm:
10541 case VMINPHZ256rmb:
10542 case VMINPHZ256rmbk:
10543 case VMINPHZ256rmbkz:
10544 case VMINPHZ256rmk:
10545 case VMINPHZ256rmkz:
10546 case VMINPHZ256rr:
10547 case VMINPHZ256rrk:
10548 case VMINPHZ256rrkz:
10549 case VMINPHZrm:
10550 case VMINPHZrmb:
10551 case VMINPHZrmbk:
10552 case VMINPHZrmbkz:
10553 case VMINPHZrmk:
10554 case VMINPHZrmkz:
10555 case VMINPHZrr:
10556 case VMINPHZrrb:
10557 case VMINPHZrrbk:
10558 case VMINPHZrrbkz:
10559 case VMINPHZrrk:
10560 case VMINPHZrrkz:
10561 return true;
10562 }
10563 return false;
10564}
10565
10566bool isVMINSD(unsigned Opcode) {
10567 switch (Opcode) {
10568 case VMINSDZrm_Int:
10569 case VMINSDZrm_Intk:
10570 case VMINSDZrm_Intkz:
10571 case VMINSDZrr_Int:
10572 case VMINSDZrr_Intk:
10573 case VMINSDZrr_Intkz:
10574 case VMINSDZrrb_Int:
10575 case VMINSDZrrb_Intk:
10576 case VMINSDZrrb_Intkz:
10577 case VMINSDrm_Int:
10578 case VMINSDrr_Int:
10579 return true;
10580 }
10581 return false;
10582}
10583
10584bool isVROUNDPD(unsigned Opcode) {
10585 switch (Opcode) {
10586 case VROUNDPDYmi:
10587 case VROUNDPDYri:
10588 case VROUNDPDmi:
10589 case VROUNDPDri:
10590 return true;
10591 }
10592 return false;
10593}
10594
10595bool isVFCMADDCPH(unsigned Opcode) {
10596 switch (Opcode) {
10597 case VFCMADDCPHZ128m:
10598 case VFCMADDCPHZ128mb:
10599 case VFCMADDCPHZ128mbk:
10600 case VFCMADDCPHZ128mbkz:
10601 case VFCMADDCPHZ128mk:
10602 case VFCMADDCPHZ128mkz:
10603 case VFCMADDCPHZ128r:
10604 case VFCMADDCPHZ128rk:
10605 case VFCMADDCPHZ128rkz:
10606 case VFCMADDCPHZ256m:
10607 case VFCMADDCPHZ256mb:
10608 case VFCMADDCPHZ256mbk:
10609 case VFCMADDCPHZ256mbkz:
10610 case VFCMADDCPHZ256mk:
10611 case VFCMADDCPHZ256mkz:
10612 case VFCMADDCPHZ256r:
10613 case VFCMADDCPHZ256rk:
10614 case VFCMADDCPHZ256rkz:
10615 case VFCMADDCPHZm:
10616 case VFCMADDCPHZmb:
10617 case VFCMADDCPHZmbk:
10618 case VFCMADDCPHZmbkz:
10619 case VFCMADDCPHZmk:
10620 case VFCMADDCPHZmkz:
10621 case VFCMADDCPHZr:
10622 case VFCMADDCPHZrb:
10623 case VFCMADDCPHZrbk:
10624 case VFCMADDCPHZrbkz:
10625 case VFCMADDCPHZrk:
10626 case VFCMADDCPHZrkz:
10627 return true;
10628 }
10629 return false;
10630}
10631
10632bool isINCSSPQ(unsigned Opcode) {
10633 return Opcode == INCSSPQ;
10634}
10635
10636bool isVPUNPCKLDQ(unsigned Opcode) {
10637 switch (Opcode) {
10638 case VPUNPCKLDQYrm:
10639 case VPUNPCKLDQYrr:
10640 case VPUNPCKLDQZ128rm:
10641 case VPUNPCKLDQZ128rmb:
10642 case VPUNPCKLDQZ128rmbk:
10643 case VPUNPCKLDQZ128rmbkz:
10644 case VPUNPCKLDQZ128rmk:
10645 case VPUNPCKLDQZ128rmkz:
10646 case VPUNPCKLDQZ128rr:
10647 case VPUNPCKLDQZ128rrk:
10648 case VPUNPCKLDQZ128rrkz:
10649 case VPUNPCKLDQZ256rm:
10650 case VPUNPCKLDQZ256rmb:
10651 case VPUNPCKLDQZ256rmbk:
10652 case VPUNPCKLDQZ256rmbkz:
10653 case VPUNPCKLDQZ256rmk:
10654 case VPUNPCKLDQZ256rmkz:
10655 case VPUNPCKLDQZ256rr:
10656 case VPUNPCKLDQZ256rrk:
10657 case VPUNPCKLDQZ256rrkz:
10658 case VPUNPCKLDQZrm:
10659 case VPUNPCKLDQZrmb:
10660 case VPUNPCKLDQZrmbk:
10661 case VPUNPCKLDQZrmbkz:
10662 case VPUNPCKLDQZrmk:
10663 case VPUNPCKLDQZrmkz:
10664 case VPUNPCKLDQZrr:
10665 case VPUNPCKLDQZrrk:
10666 case VPUNPCKLDQZrrkz:
10667 case VPUNPCKLDQrm:
10668 case VPUNPCKLDQrr:
10669 return true;
10670 }
10671 return false;
10672}
10673
10674bool isVMINSH(unsigned Opcode) {
10675 switch (Opcode) {
10676 case VMINSHZrm_Int:
10677 case VMINSHZrm_Intk:
10678 case VMINSHZrm_Intkz:
10679 case VMINSHZrr_Int:
10680 case VMINSHZrr_Intk:
10681 case VMINSHZrr_Intkz:
10682 case VMINSHZrrb_Int:
10683 case VMINSHZrrb_Intk:
10684 case VMINSHZrrb_Intkz:
10685 return true;
10686 }
10687 return false;
10688}
10689
10690bool isINSERTQ(unsigned Opcode) {
10691 switch (Opcode) {
10692 case INSERTQ:
10693 case INSERTQI:
10694 return true;
10695 }
10696 return false;
10697}
10698
10699bool isBLCI(unsigned Opcode) {
10700 switch (Opcode) {
10701 case BLCI32rm:
10702 case BLCI32rr:
10703 case BLCI64rm:
10704 case BLCI64rr:
10705 return true;
10706 }
10707 return false;
10708}
10709
10710bool isHLT(unsigned Opcode) {
10711 return Opcode == HLT;
10712}
10713
10714bool isVPCOMUW(unsigned Opcode) {
10715 switch (Opcode) {
10716 case VPCOMUWmi:
10717 case VPCOMUWri:
10718 return true;
10719 }
10720 return false;
10721}
10722
10723bool isVPMOVSXDQ(unsigned Opcode) {
10724 switch (Opcode) {
10725 case VPMOVSXDQYrm:
10726 case VPMOVSXDQYrr:
10727 case VPMOVSXDQZ128rm:
10728 case VPMOVSXDQZ128rmk:
10729 case VPMOVSXDQZ128rmkz:
10730 case VPMOVSXDQZ128rr:
10731 case VPMOVSXDQZ128rrk:
10732 case VPMOVSXDQZ128rrkz:
10733 case VPMOVSXDQZ256rm:
10734 case VPMOVSXDQZ256rmk:
10735 case VPMOVSXDQZ256rmkz:
10736 case VPMOVSXDQZ256rr:
10737 case VPMOVSXDQZ256rrk:
10738 case VPMOVSXDQZ256rrkz:
10739 case VPMOVSXDQZrm:
10740 case VPMOVSXDQZrmk:
10741 case VPMOVSXDQZrmkz:
10742 case VPMOVSXDQZrr:
10743 case VPMOVSXDQZrrk:
10744 case VPMOVSXDQZrrkz:
10745 case VPMOVSXDQrm:
10746 case VPMOVSXDQrr:
10747 return true;
10748 }
10749 return false;
10750}
10751
10752bool isVFNMSUB231PS(unsigned Opcode) {
10753 switch (Opcode) {
10754 case VFNMSUB231PSYm:
10755 case VFNMSUB231PSYr:
10756 case VFNMSUB231PSZ128m:
10757 case VFNMSUB231PSZ128mb:
10758 case VFNMSUB231PSZ128mbk:
10759 case VFNMSUB231PSZ128mbkz:
10760 case VFNMSUB231PSZ128mk:
10761 case VFNMSUB231PSZ128mkz:
10762 case VFNMSUB231PSZ128r:
10763 case VFNMSUB231PSZ128rk:
10764 case VFNMSUB231PSZ128rkz:
10765 case VFNMSUB231PSZ256m:
10766 case VFNMSUB231PSZ256mb:
10767 case VFNMSUB231PSZ256mbk:
10768 case VFNMSUB231PSZ256mbkz:
10769 case VFNMSUB231PSZ256mk:
10770 case VFNMSUB231PSZ256mkz:
10771 case VFNMSUB231PSZ256r:
10772 case VFNMSUB231PSZ256rk:
10773 case VFNMSUB231PSZ256rkz:
10774 case VFNMSUB231PSZm:
10775 case VFNMSUB231PSZmb:
10776 case VFNMSUB231PSZmbk:
10777 case VFNMSUB231PSZmbkz:
10778 case VFNMSUB231PSZmk:
10779 case VFNMSUB231PSZmkz:
10780 case VFNMSUB231PSZr:
10781 case VFNMSUB231PSZrb:
10782 case VFNMSUB231PSZrbk:
10783 case VFNMSUB231PSZrbkz:
10784 case VFNMSUB231PSZrk:
10785 case VFNMSUB231PSZrkz:
10786 case VFNMSUB231PSm:
10787 case VFNMSUB231PSr:
10788 return true;
10789 }
10790 return false;
10791}
10792
10793bool isVFNMSUB213SH(unsigned Opcode) {
10794 switch (Opcode) {
10795 case VFNMSUB213SHZm_Int:
10796 case VFNMSUB213SHZm_Intk:
10797 case VFNMSUB213SHZm_Intkz:
10798 case VFNMSUB213SHZr_Int:
10799 case VFNMSUB213SHZr_Intk:
10800 case VFNMSUB213SHZr_Intkz:
10801 case VFNMSUB213SHZrb_Int:
10802 case VFNMSUB213SHZrb_Intk:
10803 case VFNMSUB213SHZrb_Intkz:
10804 return true;
10805 }
10806 return false;
10807}
10808
10809bool isVCVTTPD2UQQ(unsigned Opcode) {
10810 switch (Opcode) {
10811 case VCVTTPD2UQQZ128rm:
10812 case VCVTTPD2UQQZ128rmb:
10813 case VCVTTPD2UQQZ128rmbk:
10814 case VCVTTPD2UQQZ128rmbkz:
10815 case VCVTTPD2UQQZ128rmk:
10816 case VCVTTPD2UQQZ128rmkz:
10817 case VCVTTPD2UQQZ128rr:
10818 case VCVTTPD2UQQZ128rrk:
10819 case VCVTTPD2UQQZ128rrkz:
10820 case VCVTTPD2UQQZ256rm:
10821 case VCVTTPD2UQQZ256rmb:
10822 case VCVTTPD2UQQZ256rmbk:
10823 case VCVTTPD2UQQZ256rmbkz:
10824 case VCVTTPD2UQQZ256rmk:
10825 case VCVTTPD2UQQZ256rmkz:
10826 case VCVTTPD2UQQZ256rr:
10827 case VCVTTPD2UQQZ256rrk:
10828 case VCVTTPD2UQQZ256rrkz:
10829 case VCVTTPD2UQQZrm:
10830 case VCVTTPD2UQQZrmb:
10831 case VCVTTPD2UQQZrmbk:
10832 case VCVTTPD2UQQZrmbkz:
10833 case VCVTTPD2UQQZrmk:
10834 case VCVTTPD2UQQZrmkz:
10835 case VCVTTPD2UQQZrr:
10836 case VCVTTPD2UQQZrrb:
10837 case VCVTTPD2UQQZrrbk:
10838 case VCVTTPD2UQQZrrbkz:
10839 case VCVTTPD2UQQZrrk:
10840 case VCVTTPD2UQQZrrkz:
10841 return true;
10842 }
10843 return false;
10844}
10845
10846bool isSQRTSS(unsigned Opcode) {
10847 switch (Opcode) {
10848 case SQRTSSm_Int:
10849 case SQRTSSr_Int:
10850 return true;
10851 }
10852 return false;
10853}
10854
10855bool isIMUL(unsigned Opcode) {
10856 switch (Opcode) {
10857 case IMUL16m:
10858 case IMUL16m_EVEX:
10859 case IMUL16m_NF:
10860 case IMUL16r:
10861 case IMUL16r_EVEX:
10862 case IMUL16r_NF:
10863 case IMUL16rm:
10864 case IMUL16rm_EVEX:
10865 case IMUL16rm_ND:
10866 case IMUL16rm_NF:
10867 case IMUL16rm_NF_ND:
10868 case IMUL16rmi:
10869 case IMUL16rmi8:
10870 case IMUL16rmi8_EVEX:
10871 case IMUL16rmi8_NF:
10872 case IMUL16rmi_EVEX:
10873 case IMUL16rmi_NF:
10874 case IMUL16rr:
10875 case IMUL16rr_EVEX:
10876 case IMUL16rr_ND:
10877 case IMUL16rr_NF:
10878 case IMUL16rr_NF_ND:
10879 case IMUL16rri:
10880 case IMUL16rri8:
10881 case IMUL16rri8_EVEX:
10882 case IMUL16rri8_NF:
10883 case IMUL16rri_EVEX:
10884 case IMUL16rri_NF:
10885 case IMUL32m:
10886 case IMUL32m_EVEX:
10887 case IMUL32m_NF:
10888 case IMUL32r:
10889 case IMUL32r_EVEX:
10890 case IMUL32r_NF:
10891 case IMUL32rm:
10892 case IMUL32rm_EVEX:
10893 case IMUL32rm_ND:
10894 case IMUL32rm_NF:
10895 case IMUL32rm_NF_ND:
10896 case IMUL32rmi:
10897 case IMUL32rmi8:
10898 case IMUL32rmi8_EVEX:
10899 case IMUL32rmi8_NF:
10900 case IMUL32rmi_EVEX:
10901 case IMUL32rmi_NF:
10902 case IMUL32rr:
10903 case IMUL32rr_EVEX:
10904 case IMUL32rr_ND:
10905 case IMUL32rr_NF:
10906 case IMUL32rr_NF_ND:
10907 case IMUL32rri:
10908 case IMUL32rri8:
10909 case IMUL32rri8_EVEX:
10910 case IMUL32rri8_NF:
10911 case IMUL32rri_EVEX:
10912 case IMUL32rri_NF:
10913 case IMUL64m:
10914 case IMUL64m_EVEX:
10915 case IMUL64m_NF:
10916 case IMUL64r:
10917 case IMUL64r_EVEX:
10918 case IMUL64r_NF:
10919 case IMUL64rm:
10920 case IMUL64rm_EVEX:
10921 case IMUL64rm_ND:
10922 case IMUL64rm_NF:
10923 case IMUL64rm_NF_ND:
10924 case IMUL64rmi32:
10925 case IMUL64rmi32_EVEX:
10926 case IMUL64rmi32_NF:
10927 case IMUL64rmi8:
10928 case IMUL64rmi8_EVEX:
10929 case IMUL64rmi8_NF:
10930 case IMUL64rr:
10931 case IMUL64rr_EVEX:
10932 case IMUL64rr_ND:
10933 case IMUL64rr_NF:
10934 case IMUL64rr_NF_ND:
10935 case IMUL64rri32:
10936 case IMUL64rri32_EVEX:
10937 case IMUL64rri32_NF:
10938 case IMUL64rri8:
10939 case IMUL64rri8_EVEX:
10940 case IMUL64rri8_NF:
10941 case IMUL8m:
10942 case IMUL8m_EVEX:
10943 case IMUL8m_NF:
10944 case IMUL8r:
10945 case IMUL8r_EVEX:
10946 case IMUL8r_NF:
10947 return true;
10948 }
10949 return false;
10950}
10951
10952bool isVCVTSS2SI(unsigned Opcode) {
10953 switch (Opcode) {
10954 case VCVTSS2SI64Zrm_Int:
10955 case VCVTSS2SI64Zrr_Int:
10956 case VCVTSS2SI64Zrrb_Int:
10957 case VCVTSS2SI64rm_Int:
10958 case VCVTSS2SI64rr_Int:
10959 case VCVTSS2SIZrm_Int:
10960 case VCVTSS2SIZrr_Int:
10961 case VCVTSS2SIZrrb_Int:
10962 case VCVTSS2SIrm_Int:
10963 case VCVTSS2SIrr_Int:
10964 return true;
10965 }
10966 return false;
10967}
10968
10969bool isPUSHAW(unsigned Opcode) {
10970 return Opcode == PUSHA16;
10971}
10972
10973bool isSTOSD(unsigned Opcode) {
10974 return Opcode == STOSL;
10975}
10976
10977bool isPSRLDQ(unsigned Opcode) {
10978 return Opcode == PSRLDQri;
10979}
10980
10981bool isVSCATTERQPS(unsigned Opcode) {
10982 switch (Opcode) {
10983 case VSCATTERQPSZ128mr:
10984 case VSCATTERQPSZ256mr:
10985 case VSCATTERQPSZmr:
10986 return true;
10987 }
10988 return false;
10989}
10990
10991bool isFIDIV(unsigned Opcode) {
10992 switch (Opcode) {
10993 case DIV_FI16m:
10994 case DIV_FI32m:
10995 return true;
10996 }
10997 return false;
10998}
10999
11000bool isVFMSUB213PD(unsigned Opcode) {
11001 switch (Opcode) {
11002 case VFMSUB213PDYm:
11003 case VFMSUB213PDYr:
11004 case VFMSUB213PDZ128m:
11005 case VFMSUB213PDZ128mb:
11006 case VFMSUB213PDZ128mbk:
11007 case VFMSUB213PDZ128mbkz:
11008 case VFMSUB213PDZ128mk:
11009 case VFMSUB213PDZ128mkz:
11010 case VFMSUB213PDZ128r:
11011 case VFMSUB213PDZ128rk:
11012 case VFMSUB213PDZ128rkz:
11013 case VFMSUB213PDZ256m:
11014 case VFMSUB213PDZ256mb:
11015 case VFMSUB213PDZ256mbk:
11016 case VFMSUB213PDZ256mbkz:
11017 case VFMSUB213PDZ256mk:
11018 case VFMSUB213PDZ256mkz:
11019 case VFMSUB213PDZ256r:
11020 case VFMSUB213PDZ256rk:
11021 case VFMSUB213PDZ256rkz:
11022 case VFMSUB213PDZm:
11023 case VFMSUB213PDZmb:
11024 case VFMSUB213PDZmbk:
11025 case VFMSUB213PDZmbkz:
11026 case VFMSUB213PDZmk:
11027 case VFMSUB213PDZmkz:
11028 case VFMSUB213PDZr:
11029 case VFMSUB213PDZrb:
11030 case VFMSUB213PDZrbk:
11031 case VFMSUB213PDZrbkz:
11032 case VFMSUB213PDZrk:
11033 case VFMSUB213PDZrkz:
11034 case VFMSUB213PDm:
11035 case VFMSUB213PDr:
11036 return true;
11037 }
11038 return false;
11039}
11040
11041bool isVFMADDSUB231PH(unsigned Opcode) {
11042 switch (Opcode) {
11043 case VFMADDSUB231PHZ128m:
11044 case VFMADDSUB231PHZ128mb:
11045 case VFMADDSUB231PHZ128mbk:
11046 case VFMADDSUB231PHZ128mbkz:
11047 case VFMADDSUB231PHZ128mk:
11048 case VFMADDSUB231PHZ128mkz:
11049 case VFMADDSUB231PHZ128r:
11050 case VFMADDSUB231PHZ128rk:
11051 case VFMADDSUB231PHZ128rkz:
11052 case VFMADDSUB231PHZ256m:
11053 case VFMADDSUB231PHZ256mb:
11054 case VFMADDSUB231PHZ256mbk:
11055 case VFMADDSUB231PHZ256mbkz:
11056 case VFMADDSUB231PHZ256mk:
11057 case VFMADDSUB231PHZ256mkz:
11058 case VFMADDSUB231PHZ256r:
11059 case VFMADDSUB231PHZ256rk:
11060 case VFMADDSUB231PHZ256rkz:
11061 case VFMADDSUB231PHZm:
11062 case VFMADDSUB231PHZmb:
11063 case VFMADDSUB231PHZmbk:
11064 case VFMADDSUB231PHZmbkz:
11065 case VFMADDSUB231PHZmk:
11066 case VFMADDSUB231PHZmkz:
11067 case VFMADDSUB231PHZr:
11068 case VFMADDSUB231PHZrb:
11069 case VFMADDSUB231PHZrbk:
11070 case VFMADDSUB231PHZrbkz:
11071 case VFMADDSUB231PHZrk:
11072 case VFMADDSUB231PHZrkz:
11073 return true;
11074 }
11075 return false;
11076}
11077
11078bool isTDCALL(unsigned Opcode) {
11079 return Opcode == TDCALL;
11080}
11081
11082bool isPVALIDATE(unsigned Opcode) {
11083 switch (Opcode) {
11084 case PVALIDATE32:
11085 case PVALIDATE64:
11086 return true;
11087 }
11088 return false;
11089}
11090
11091bool isVPSHUFLW(unsigned Opcode) {
11092 switch (Opcode) {
11093 case VPSHUFLWYmi:
11094 case VPSHUFLWYri:
11095 case VPSHUFLWZ128mi:
11096 case VPSHUFLWZ128mik:
11097 case VPSHUFLWZ128mikz:
11098 case VPSHUFLWZ128ri:
11099 case VPSHUFLWZ128rik:
11100 case VPSHUFLWZ128rikz:
11101 case VPSHUFLWZ256mi:
11102 case VPSHUFLWZ256mik:
11103 case VPSHUFLWZ256mikz:
11104 case VPSHUFLWZ256ri:
11105 case VPSHUFLWZ256rik:
11106 case VPSHUFLWZ256rikz:
11107 case VPSHUFLWZmi:
11108 case VPSHUFLWZmik:
11109 case VPSHUFLWZmikz:
11110 case VPSHUFLWZri:
11111 case VPSHUFLWZrik:
11112 case VPSHUFLWZrikz:
11113 case VPSHUFLWmi:
11114 case VPSHUFLWri:
11115 return true;
11116 }
11117 return false;
11118}
11119
11120bool isPCLMULQDQ(unsigned Opcode) {
11121 switch (Opcode) {
11122 case PCLMULQDQrmi:
11123 case PCLMULQDQrri:
11124 return true;
11125 }
11126 return false;
11127}
11128
11129bool isCMPXCHG8B(unsigned Opcode) {
11130 return Opcode == CMPXCHG8B;
11131}
11132
11133bool isVPMOVM2B(unsigned Opcode) {
11134 switch (Opcode) {
11135 case VPMOVM2BZ128rr:
11136 case VPMOVM2BZ256rr:
11137 case VPMOVM2BZrr:
11138 return true;
11139 }
11140 return false;
11141}
11142
11143bool isVCVTUDQ2PH(unsigned Opcode) {
11144 switch (Opcode) {
11145 case VCVTUDQ2PHZ128rm:
11146 case VCVTUDQ2PHZ128rmb:
11147 case VCVTUDQ2PHZ128rmbk:
11148 case VCVTUDQ2PHZ128rmbkz:
11149 case VCVTUDQ2PHZ128rmk:
11150 case VCVTUDQ2PHZ128rmkz:
11151 case VCVTUDQ2PHZ128rr:
11152 case VCVTUDQ2PHZ128rrk:
11153 case VCVTUDQ2PHZ128rrkz:
11154 case VCVTUDQ2PHZ256rm:
11155 case VCVTUDQ2PHZ256rmb:
11156 case VCVTUDQ2PHZ256rmbk:
11157 case VCVTUDQ2PHZ256rmbkz:
11158 case VCVTUDQ2PHZ256rmk:
11159 case VCVTUDQ2PHZ256rmkz:
11160 case VCVTUDQ2PHZ256rr:
11161 case VCVTUDQ2PHZ256rrk:
11162 case VCVTUDQ2PHZ256rrkz:
11163 case VCVTUDQ2PHZrm:
11164 case VCVTUDQ2PHZrmb:
11165 case VCVTUDQ2PHZrmbk:
11166 case VCVTUDQ2PHZrmbkz:
11167 case VCVTUDQ2PHZrmk:
11168 case VCVTUDQ2PHZrmkz:
11169 case VCVTUDQ2PHZrr:
11170 case VCVTUDQ2PHZrrb:
11171 case VCVTUDQ2PHZrrbk:
11172 case VCVTUDQ2PHZrrbkz:
11173 case VCVTUDQ2PHZrrk:
11174 case VCVTUDQ2PHZrrkz:
11175 return true;
11176 }
11177 return false;
11178}
11179
11180bool isPEXTRQ(unsigned Opcode) {
11181 switch (Opcode) {
11182 case PEXTRQmr:
11183 case PEXTRQrr:
11184 return true;
11185 }
11186 return false;
11187}
11188
11189bool isXCRYPTCTR(unsigned Opcode) {
11190 return Opcode == XCRYPTCTR;
11191}
11192
11193bool isVREDUCEPH(unsigned Opcode) {
11194 switch (Opcode) {
11195 case VREDUCEPHZ128rmbi:
11196 case VREDUCEPHZ128rmbik:
11197 case VREDUCEPHZ128rmbikz:
11198 case VREDUCEPHZ128rmi:
11199 case VREDUCEPHZ128rmik:
11200 case VREDUCEPHZ128rmikz:
11201 case VREDUCEPHZ128rri:
11202 case VREDUCEPHZ128rrik:
11203 case VREDUCEPHZ128rrikz:
11204 case VREDUCEPHZ256rmbi:
11205 case VREDUCEPHZ256rmbik:
11206 case VREDUCEPHZ256rmbikz:
11207 case VREDUCEPHZ256rmi:
11208 case VREDUCEPHZ256rmik:
11209 case VREDUCEPHZ256rmikz:
11210 case VREDUCEPHZ256rri:
11211 case VREDUCEPHZ256rrik:
11212 case VREDUCEPHZ256rrikz:
11213 case VREDUCEPHZrmbi:
11214 case VREDUCEPHZrmbik:
11215 case VREDUCEPHZrmbikz:
11216 case VREDUCEPHZrmi:
11217 case VREDUCEPHZrmik:
11218 case VREDUCEPHZrmikz:
11219 case VREDUCEPHZrri:
11220 case VREDUCEPHZrrib:
11221 case VREDUCEPHZrribk:
11222 case VREDUCEPHZrribkz:
11223 case VREDUCEPHZrrik:
11224 case VREDUCEPHZrrikz:
11225 return true;
11226 }
11227 return false;
11228}
11229
11230bool isUCOMISD(unsigned Opcode) {
11231 switch (Opcode) {
11232 case UCOMISDrm:
11233 case UCOMISDrr:
11234 return true;
11235 }
11236 return false;
11237}
11238
11239bool isOUTSD(unsigned Opcode) {
11240 return Opcode == OUTSL;
11241}
11242
11243bool isSUBSS(unsigned Opcode) {
11244 switch (Opcode) {
11245 case SUBSSrm_Int:
11246 case SUBSSrr_Int:
11247 return true;
11248 }
11249 return false;
11250}
11251
11252bool isVFMSUBPS(unsigned Opcode) {
11253 switch (Opcode) {
11254 case VFMSUBPS4Ymr:
11255 case VFMSUBPS4Yrm:
11256 case VFMSUBPS4Yrr:
11257 case VFMSUBPS4Yrr_REV:
11258 case VFMSUBPS4mr:
11259 case VFMSUBPS4rm:
11260 case VFMSUBPS4rr:
11261 case VFMSUBPS4rr_REV:
11262 return true;
11263 }
11264 return false;
11265}
11266
11267bool isVPBLENDW(unsigned Opcode) {
11268 switch (Opcode) {
11269 case VPBLENDWYrmi:
11270 case VPBLENDWYrri:
11271 case VPBLENDWrmi:
11272 case VPBLENDWrri:
11273 return true;
11274 }
11275 return false;
11276}
11277
11278bool isBZHI(unsigned Opcode) {
11279 switch (Opcode) {
11280 case BZHI32rm:
11281 case BZHI32rm_EVEX:
11282 case BZHI32rm_NF:
11283 case BZHI32rr:
11284 case BZHI32rr_EVEX:
11285 case BZHI32rr_NF:
11286 case BZHI64rm:
11287 case BZHI64rm_EVEX:
11288 case BZHI64rm_NF:
11289 case BZHI64rr:
11290 case BZHI64rr_EVEX:
11291 case BZHI64rr_NF:
11292 return true;
11293 }
11294 return false;
11295}
11296
11297bool isVPRORVD(unsigned Opcode) {
11298 switch (Opcode) {
11299 case VPRORVDZ128rm:
11300 case VPRORVDZ128rmb:
11301 case VPRORVDZ128rmbk:
11302 case VPRORVDZ128rmbkz:
11303 case VPRORVDZ128rmk:
11304 case VPRORVDZ128rmkz:
11305 case VPRORVDZ128rr:
11306 case VPRORVDZ128rrk:
11307 case VPRORVDZ128rrkz:
11308 case VPRORVDZ256rm:
11309 case VPRORVDZ256rmb:
11310 case VPRORVDZ256rmbk:
11311 case VPRORVDZ256rmbkz:
11312 case VPRORVDZ256rmk:
11313 case VPRORVDZ256rmkz:
11314 case VPRORVDZ256rr:
11315 case VPRORVDZ256rrk:
11316 case VPRORVDZ256rrkz:
11317 case VPRORVDZrm:
11318 case VPRORVDZrmb:
11319 case VPRORVDZrmbk:
11320 case VPRORVDZrmbkz:
11321 case VPRORVDZrmk:
11322 case VPRORVDZrmkz:
11323 case VPRORVDZrr:
11324 case VPRORVDZrrk:
11325 case VPRORVDZrrkz:
11326 return true;
11327 }
11328 return false;
11329}
11330
11331bool isRMPQUERY(unsigned Opcode) {
11332 return Opcode == RMPQUERY;
11333}
11334
11335bool isVPEXPANDB(unsigned Opcode) {
11336 switch (Opcode) {
11337 case VPEXPANDBZ128rm:
11338 case VPEXPANDBZ128rmk:
11339 case VPEXPANDBZ128rmkz:
11340 case VPEXPANDBZ128rr:
11341 case VPEXPANDBZ128rrk:
11342 case VPEXPANDBZ128rrkz:
11343 case VPEXPANDBZ256rm:
11344 case VPEXPANDBZ256rmk:
11345 case VPEXPANDBZ256rmkz:
11346 case VPEXPANDBZ256rr:
11347 case VPEXPANDBZ256rrk:
11348 case VPEXPANDBZ256rrkz:
11349 case VPEXPANDBZrm:
11350 case VPEXPANDBZrmk:
11351 case VPEXPANDBZrmkz:
11352 case VPEXPANDBZrr:
11353 case VPEXPANDBZrrk:
11354 case VPEXPANDBZrrkz:
11355 return true;
11356 }
11357 return false;
11358}
11359
11360bool isVPSCATTERDQ(unsigned Opcode) {
11361 switch (Opcode) {
11362 case VPSCATTERDQZ128mr:
11363 case VPSCATTERDQZ256mr:
11364 case VPSCATTERDQZmr:
11365 return true;
11366 }
11367 return false;
11368}
11369
11370bool isPSMASH(unsigned Opcode) {
11371 return Opcode == PSMASH;
11372}
11373
11374bool isVPSHLDQ(unsigned Opcode) {
11375 switch (Opcode) {
11376 case VPSHLDQZ128rmbi:
11377 case VPSHLDQZ128rmbik:
11378 case VPSHLDQZ128rmbikz:
11379 case VPSHLDQZ128rmi:
11380 case VPSHLDQZ128rmik:
11381 case VPSHLDQZ128rmikz:
11382 case VPSHLDQZ128rri:
11383 case VPSHLDQZ128rrik:
11384 case VPSHLDQZ128rrikz:
11385 case VPSHLDQZ256rmbi:
11386 case VPSHLDQZ256rmbik:
11387 case VPSHLDQZ256rmbikz:
11388 case VPSHLDQZ256rmi:
11389 case VPSHLDQZ256rmik:
11390 case VPSHLDQZ256rmikz:
11391 case VPSHLDQZ256rri:
11392 case VPSHLDQZ256rrik:
11393 case VPSHLDQZ256rrikz:
11394 case VPSHLDQZrmbi:
11395 case VPSHLDQZrmbik:
11396 case VPSHLDQZrmbikz:
11397 case VPSHLDQZrmi:
11398 case VPSHLDQZrmik:
11399 case VPSHLDQZrmikz:
11400 case VPSHLDQZrri:
11401 case VPSHLDQZrrik:
11402 case VPSHLDQZrrikz:
11403 return true;
11404 }
11405 return false;
11406}
11407
11408bool isVSCATTERPF1DPD(unsigned Opcode) {
11409 return Opcode == VSCATTERPF1DPDm;
11410}
11411
11412bool isMONTMUL(unsigned Opcode) {
11413 return Opcode == MONTMUL;
11414}
11415
11416bool isVCVTPH2UQQ(unsigned Opcode) {
11417 switch (Opcode) {
11418 case VCVTPH2UQQZ128rm:
11419 case VCVTPH2UQQZ128rmb:
11420 case VCVTPH2UQQZ128rmbk:
11421 case VCVTPH2UQQZ128rmbkz:
11422 case VCVTPH2UQQZ128rmk:
11423 case VCVTPH2UQQZ128rmkz:
11424 case VCVTPH2UQQZ128rr:
11425 case VCVTPH2UQQZ128rrk:
11426 case VCVTPH2UQQZ128rrkz:
11427 case VCVTPH2UQQZ256rm:
11428 case VCVTPH2UQQZ256rmb:
11429 case VCVTPH2UQQZ256rmbk:
11430 case VCVTPH2UQQZ256rmbkz:
11431 case VCVTPH2UQQZ256rmk:
11432 case VCVTPH2UQQZ256rmkz:
11433 case VCVTPH2UQQZ256rr:
11434 case VCVTPH2UQQZ256rrk:
11435 case VCVTPH2UQQZ256rrkz:
11436 case VCVTPH2UQQZrm:
11437 case VCVTPH2UQQZrmb:
11438 case VCVTPH2UQQZrmbk:
11439 case VCVTPH2UQQZrmbkz:
11440 case VCVTPH2UQQZrmk:
11441 case VCVTPH2UQQZrmkz:
11442 case VCVTPH2UQQZrr:
11443 case VCVTPH2UQQZrrb:
11444 case VCVTPH2UQQZrrbk:
11445 case VCVTPH2UQQZrrbkz:
11446 case VCVTPH2UQQZrrk:
11447 case VCVTPH2UQQZrrkz:
11448 return true;
11449 }
11450 return false;
11451}
11452
11453bool isPSLLD(unsigned Opcode) {
11454 switch (Opcode) {
11455 case MMX_PSLLDri:
11456 case MMX_PSLLDrm:
11457 case MMX_PSLLDrr:
11458 case PSLLDri:
11459 case PSLLDrm:
11460 case PSLLDrr:
11461 return true;
11462 }
11463 return false;
11464}
11465
11466bool isSAR(unsigned Opcode) {
11467 switch (Opcode) {
11468 case SAR16m1:
11469 case SAR16m1_EVEX:
11470 case SAR16m1_ND:
11471 case SAR16m1_NF:
11472 case SAR16m1_NF_ND:
11473 case SAR16mCL:
11474 case SAR16mCL_EVEX:
11475 case SAR16mCL_ND:
11476 case SAR16mCL_NF:
11477 case SAR16mCL_NF_ND:
11478 case SAR16mi:
11479 case SAR16mi_EVEX:
11480 case SAR16mi_ND:
11481 case SAR16mi_NF:
11482 case SAR16mi_NF_ND:
11483 case SAR16r1:
11484 case SAR16r1_EVEX:
11485 case SAR16r1_ND:
11486 case SAR16r1_NF:
11487 case SAR16r1_NF_ND:
11488 case SAR16rCL:
11489 case SAR16rCL_EVEX:
11490 case SAR16rCL_ND:
11491 case SAR16rCL_NF:
11492 case SAR16rCL_NF_ND:
11493 case SAR16ri:
11494 case SAR16ri_EVEX:
11495 case SAR16ri_ND:
11496 case SAR16ri_NF:
11497 case SAR16ri_NF_ND:
11498 case SAR32m1:
11499 case SAR32m1_EVEX:
11500 case SAR32m1_ND:
11501 case SAR32m1_NF:
11502 case SAR32m1_NF_ND:
11503 case SAR32mCL:
11504 case SAR32mCL_EVEX:
11505 case SAR32mCL_ND:
11506 case SAR32mCL_NF:
11507 case SAR32mCL_NF_ND:
11508 case SAR32mi:
11509 case SAR32mi_EVEX:
11510 case SAR32mi_ND:
11511 case SAR32mi_NF:
11512 case SAR32mi_NF_ND:
11513 case SAR32r1:
11514 case SAR32r1_EVEX:
11515 case SAR32r1_ND:
11516 case SAR32r1_NF:
11517 case SAR32r1_NF_ND:
11518 case SAR32rCL:
11519 case SAR32rCL_EVEX:
11520 case SAR32rCL_ND:
11521 case SAR32rCL_NF:
11522 case SAR32rCL_NF_ND:
11523 case SAR32ri:
11524 case SAR32ri_EVEX:
11525 case SAR32ri_ND:
11526 case SAR32ri_NF:
11527 case SAR32ri_NF_ND:
11528 case SAR64m1:
11529 case SAR64m1_EVEX:
11530 case SAR64m1_ND:
11531 case SAR64m1_NF:
11532 case SAR64m1_NF_ND:
11533 case SAR64mCL:
11534 case SAR64mCL_EVEX:
11535 case SAR64mCL_ND:
11536 case SAR64mCL_NF:
11537 case SAR64mCL_NF_ND:
11538 case SAR64mi:
11539 case SAR64mi_EVEX:
11540 case SAR64mi_ND:
11541 case SAR64mi_NF:
11542 case SAR64mi_NF_ND:
11543 case SAR64r1:
11544 case SAR64r1_EVEX:
11545 case SAR64r1_ND:
11546 case SAR64r1_NF:
11547 case SAR64r1_NF_ND:
11548 case SAR64rCL:
11549 case SAR64rCL_EVEX:
11550 case SAR64rCL_ND:
11551 case SAR64rCL_NF:
11552 case SAR64rCL_NF_ND:
11553 case SAR64ri:
11554 case SAR64ri_EVEX:
11555 case SAR64ri_ND:
11556 case SAR64ri_NF:
11557 case SAR64ri_NF_ND:
11558 case SAR8m1:
11559 case SAR8m1_EVEX:
11560 case SAR8m1_ND:
11561 case SAR8m1_NF:
11562 case SAR8m1_NF_ND:
11563 case SAR8mCL:
11564 case SAR8mCL_EVEX:
11565 case SAR8mCL_ND:
11566 case SAR8mCL_NF:
11567 case SAR8mCL_NF_ND:
11568 case SAR8mi:
11569 case SAR8mi_EVEX:
11570 case SAR8mi_ND:
11571 case SAR8mi_NF:
11572 case SAR8mi_NF_ND:
11573 case SAR8r1:
11574 case SAR8r1_EVEX:
11575 case SAR8r1_ND:
11576 case SAR8r1_NF:
11577 case SAR8r1_NF_ND:
11578 case SAR8rCL:
11579 case SAR8rCL_EVEX:
11580 case SAR8rCL_ND:
11581 case SAR8rCL_NF:
11582 case SAR8rCL_NF_ND:
11583 case SAR8ri:
11584 case SAR8ri_EVEX:
11585 case SAR8ri_ND:
11586 case SAR8ri_NF:
11587 case SAR8ri_NF_ND:
11588 return true;
11589 }
11590 return false;
11591}
11592
11593bool isLDTILECFG(unsigned Opcode) {
11594 switch (Opcode) {
11595 case LDTILECFG:
11596 case LDTILECFG_EVEX:
11597 return true;
11598 }
11599 return false;
11600}
11601
11602bool isPMINUB(unsigned Opcode) {
11603 switch (Opcode) {
11604 case MMX_PMINUBrm:
11605 case MMX_PMINUBrr:
11606 case PMINUBrm:
11607 case PMINUBrr:
11608 return true;
11609 }
11610 return false;
11611}
11612
11613bool isVCVTNEEBF162PS(unsigned Opcode) {
11614 switch (Opcode) {
11615 case VCVTNEEBF162PSYrm:
11616 case VCVTNEEBF162PSrm:
11617 return true;
11618 }
11619 return false;
11620}
11621
11622bool isMOVDIR64B(unsigned Opcode) {
11623 switch (Opcode) {
11624 case MOVDIR64B16:
11625 case MOVDIR64B32:
11626 case MOVDIR64B32_EVEX:
11627 case MOVDIR64B64:
11628 case MOVDIR64B64_EVEX:
11629 return true;
11630 }
11631 return false;
11632}
11633
11634bool isSTR(unsigned Opcode) {
11635 switch (Opcode) {
11636 case STR16r:
11637 case STR32r:
11638 case STR64r:
11639 case STRm:
11640 return true;
11641 }
11642 return false;
11643}
11644
11645bool isKANDNQ(unsigned Opcode) {
11646 return Opcode == KANDNQrr;
11647}
11648
11649bool isBSF(unsigned Opcode) {
11650 switch (Opcode) {
11651 case BSF16rm:
11652 case BSF16rr:
11653 case BSF32rm:
11654 case BSF32rr:
11655 case BSF64rm:
11656 case BSF64rr:
11657 return true;
11658 }
11659 return false;
11660}
11661
11662bool isVPDPBUUDS(unsigned Opcode) {
11663 switch (Opcode) {
11664 case VPDPBUUDSYrm:
11665 case VPDPBUUDSYrr:
11666 case VPDPBUUDSrm:
11667 case VPDPBUUDSrr:
11668 return true;
11669 }
11670 return false;
11671}
11672
11673bool isINCSSPD(unsigned Opcode) {
11674 return Opcode == INCSSPD;
11675}
11676
11677bool isSQRTPS(unsigned Opcode) {
11678 switch (Opcode) {
11679 case SQRTPSm:
11680 case SQRTPSr:
11681 return true;
11682 }
11683 return false;
11684}
11685
11686bool isCMPXCHG(unsigned Opcode) {
11687 switch (Opcode) {
11688 case CMPXCHG16rm:
11689 case CMPXCHG16rr:
11690 case CMPXCHG32rm:
11691 case CMPXCHG32rr:
11692 case CMPXCHG64rm:
11693 case CMPXCHG64rr:
11694 case CMPXCHG8rm:
11695 case CMPXCHG8rr:
11696 return true;
11697 }
11698 return false;
11699}
11700
11701bool isVPSIGNW(unsigned Opcode) {
11702 switch (Opcode) {
11703 case VPSIGNWYrm:
11704 case VPSIGNWYrr:
11705 case VPSIGNWrm:
11706 case VPSIGNWrr:
11707 return true;
11708 }
11709 return false;
11710}
11711
11712bool isLES(unsigned Opcode) {
11713 switch (Opcode) {
11714 case LES16rm:
11715 case LES32rm:
11716 return true;
11717 }
11718 return false;
11719}
11720
11721bool isCVTSS2SI(unsigned Opcode) {
11722 switch (Opcode) {
11723 case CVTSS2SI64rm_Int:
11724 case CVTSS2SI64rr_Int:
11725 case CVTSS2SIrm_Int:
11726 case CVTSS2SIrr_Int:
11727 return true;
11728 }
11729 return false;
11730}
11731
11732bool isVPMOVUSWB(unsigned Opcode) {
11733 switch (Opcode) {
11734 case VPMOVUSWBZ128mr:
11735 case VPMOVUSWBZ128mrk:
11736 case VPMOVUSWBZ128rr:
11737 case VPMOVUSWBZ128rrk:
11738 case VPMOVUSWBZ128rrkz:
11739 case VPMOVUSWBZ256mr:
11740 case VPMOVUSWBZ256mrk:
11741 case VPMOVUSWBZ256rr:
11742 case VPMOVUSWBZ256rrk:
11743 case VPMOVUSWBZ256rrkz:
11744 case VPMOVUSWBZmr:
11745 case VPMOVUSWBZmrk:
11746 case VPMOVUSWBZrr:
11747 case VPMOVUSWBZrrk:
11748 case VPMOVUSWBZrrkz:
11749 return true;
11750 }
11751 return false;
11752}
11753
11754bool isFCOMPI(unsigned Opcode) {
11755 return Opcode == COM_FIPr;
11756}
11757
11758bool isPUNPCKHWD(unsigned Opcode) {
11759 switch (Opcode) {
11760 case MMX_PUNPCKHWDrm:
11761 case MMX_PUNPCKHWDrr:
11762 case PUNPCKHWDrm:
11763 case PUNPCKHWDrr:
11764 return true;
11765 }
11766 return false;
11767}
11768
11769bool isPFACC(unsigned Opcode) {
11770 switch (Opcode) {
11771 case PFACCrm:
11772 case PFACCrr:
11773 return true;
11774 }
11775 return false;
11776}
11777
11778bool isVPTESTNMW(unsigned Opcode) {
11779 switch (Opcode) {
11780 case VPTESTNMWZ128rm:
11781 case VPTESTNMWZ128rmk:
11782 case VPTESTNMWZ128rr:
11783 case VPTESTNMWZ128rrk:
11784 case VPTESTNMWZ256rm:
11785 case VPTESTNMWZ256rmk:
11786 case VPTESTNMWZ256rr:
11787 case VPTESTNMWZ256rrk:
11788 case VPTESTNMWZrm:
11789 case VPTESTNMWZrmk:
11790 case VPTESTNMWZrr:
11791 case VPTESTNMWZrrk:
11792 return true;
11793 }
11794 return false;
11795}
11796
11797bool isVPMULDQ(unsigned Opcode) {
11798 switch (Opcode) {
11799 case VPMULDQYrm:
11800 case VPMULDQYrr:
11801 case VPMULDQZ128rm:
11802 case VPMULDQZ128rmb:
11803 case VPMULDQZ128rmbk:
11804 case VPMULDQZ128rmbkz:
11805 case VPMULDQZ128rmk:
11806 case VPMULDQZ128rmkz:
11807 case VPMULDQZ128rr:
11808 case VPMULDQZ128rrk:
11809 case VPMULDQZ128rrkz:
11810 case VPMULDQZ256rm:
11811 case VPMULDQZ256rmb:
11812 case VPMULDQZ256rmbk:
11813 case VPMULDQZ256rmbkz:
11814 case VPMULDQZ256rmk:
11815 case VPMULDQZ256rmkz:
11816 case VPMULDQZ256rr:
11817 case VPMULDQZ256rrk:
11818 case VPMULDQZ256rrkz:
11819 case VPMULDQZrm:
11820 case VPMULDQZrmb:
11821 case VPMULDQZrmbk:
11822 case VPMULDQZrmbkz:
11823 case VPMULDQZrmk:
11824 case VPMULDQZrmkz:
11825 case VPMULDQZrr:
11826 case VPMULDQZrrk:
11827 case VPMULDQZrrkz:
11828 case VPMULDQrm:
11829 case VPMULDQrr:
11830 return true;
11831 }
11832 return false;
11833}
11834
11835bool isSHRX(unsigned Opcode) {
11836 switch (Opcode) {
11837 case SHRX32rm:
11838 case SHRX32rm_EVEX:
11839 case SHRX32rr:
11840 case SHRX32rr_EVEX:
11841 case SHRX64rm:
11842 case SHRX64rm_EVEX:
11843 case SHRX64rr:
11844 case SHRX64rr_EVEX:
11845 return true;
11846 }
11847 return false;
11848}
11849
11850bool isKXORQ(unsigned Opcode) {
11851 return Opcode == KXORQrr;
11852}
11853
11854bool isVGETEXPSD(unsigned Opcode) {
11855 switch (Opcode) {
11856 case VGETEXPSDZm:
11857 case VGETEXPSDZmk:
11858 case VGETEXPSDZmkz:
11859 case VGETEXPSDZr:
11860 case VGETEXPSDZrb:
11861 case VGETEXPSDZrbk:
11862 case VGETEXPSDZrbkz:
11863 case VGETEXPSDZrk:
11864 case VGETEXPSDZrkz:
11865 return true;
11866 }
11867 return false;
11868}
11869
11870bool isV4FNMADDPS(unsigned Opcode) {
11871 switch (Opcode) {
11872 case V4FNMADDPSrm:
11873 case V4FNMADDPSrmk:
11874 case V4FNMADDPSrmkz:
11875 return true;
11876 }
11877 return false;
11878}
11879
11880bool isVFNMSUB231SD(unsigned Opcode) {
11881 switch (Opcode) {
11882 case VFNMSUB231SDZm_Int:
11883 case VFNMSUB231SDZm_Intk:
11884 case VFNMSUB231SDZm_Intkz:
11885 case VFNMSUB231SDZr_Int:
11886 case VFNMSUB231SDZr_Intk:
11887 case VFNMSUB231SDZr_Intkz:
11888 case VFNMSUB231SDZrb_Int:
11889 case VFNMSUB231SDZrb_Intk:
11890 case VFNMSUB231SDZrb_Intkz:
11891 case VFNMSUB231SDm_Int:
11892 case VFNMSUB231SDr_Int:
11893 return true;
11894 }
11895 return false;
11896}
11897
11898bool isVPSHLD(unsigned Opcode) {
11899 switch (Opcode) {
11900 case VPSHLDmr:
11901 case VPSHLDrm:
11902 case VPSHLDrr:
11903 case VPSHLDrr_REV:
11904 return true;
11905 }
11906 return false;
11907}
11908
11909bool isPAVGB(unsigned Opcode) {
11910 switch (Opcode) {
11911 case MMX_PAVGBrm:
11912 case MMX_PAVGBrr:
11913 case PAVGBrm:
11914 case PAVGBrr:
11915 return true;
11916 }
11917 return false;
11918}
11919
11920bool isPMOVZXBD(unsigned Opcode) {
11921 switch (Opcode) {
11922 case PMOVZXBDrm:
11923 case PMOVZXBDrr:
11924 return true;
11925 }
11926 return false;
11927}
11928
11929bool isKORTESTW(unsigned Opcode) {
11930 return Opcode == KORTESTWrr;
11931}
11932
11933bool isVSHUFPS(unsigned Opcode) {
11934 switch (Opcode) {
11935 case VSHUFPSYrmi:
11936 case VSHUFPSYrri:
11937 case VSHUFPSZ128rmbi:
11938 case VSHUFPSZ128rmbik:
11939 case VSHUFPSZ128rmbikz:
11940 case VSHUFPSZ128rmi:
11941 case VSHUFPSZ128rmik:
11942 case VSHUFPSZ128rmikz:
11943 case VSHUFPSZ128rri:
11944 case VSHUFPSZ128rrik:
11945 case VSHUFPSZ128rrikz:
11946 case VSHUFPSZ256rmbi:
11947 case VSHUFPSZ256rmbik:
11948 case VSHUFPSZ256rmbikz:
11949 case VSHUFPSZ256rmi:
11950 case VSHUFPSZ256rmik:
11951 case VSHUFPSZ256rmikz:
11952 case VSHUFPSZ256rri:
11953 case VSHUFPSZ256rrik:
11954 case VSHUFPSZ256rrikz:
11955 case VSHUFPSZrmbi:
11956 case VSHUFPSZrmbik:
11957 case VSHUFPSZrmbikz:
11958 case VSHUFPSZrmi:
11959 case VSHUFPSZrmik:
11960 case VSHUFPSZrmikz:
11961 case VSHUFPSZrri:
11962 case VSHUFPSZrrik:
11963 case VSHUFPSZrrikz:
11964 case VSHUFPSrmi:
11965 case VSHUFPSrri:
11966 return true;
11967 }
11968 return false;
11969}
11970
11971bool isAESENCWIDE128KL(unsigned Opcode) {
11972 return Opcode == AESENCWIDE128KL;
11973}
11974
11975bool isVPXORD(unsigned Opcode) {
11976 switch (Opcode) {
11977 case VPXORDZ128rm:
11978 case VPXORDZ128rmb:
11979 case VPXORDZ128rmbk:
11980 case VPXORDZ128rmbkz:
11981 case VPXORDZ128rmk:
11982 case VPXORDZ128rmkz:
11983 case VPXORDZ128rr:
11984 case VPXORDZ128rrk:
11985 case VPXORDZ128rrkz:
11986 case VPXORDZ256rm:
11987 case VPXORDZ256rmb:
11988 case VPXORDZ256rmbk:
11989 case VPXORDZ256rmbkz:
11990 case VPXORDZ256rmk:
11991 case VPXORDZ256rmkz:
11992 case VPXORDZ256rr:
11993 case VPXORDZ256rrk:
11994 case VPXORDZ256rrkz:
11995 case VPXORDZrm:
11996 case VPXORDZrmb:
11997 case VPXORDZrmbk:
11998 case VPXORDZrmbkz:
11999 case VPXORDZrmk:
12000 case VPXORDZrmkz:
12001 case VPXORDZrr:
12002 case VPXORDZrrk:
12003 case VPXORDZrrkz:
12004 return true;
12005 }
12006 return false;
12007}
12008
12009bool isVPSHAW(unsigned Opcode) {
12010 switch (Opcode) {
12011 case VPSHAWmr:
12012 case VPSHAWrm:
12013 case VPSHAWrr:
12014 case VPSHAWrr_REV:
12015 return true;
12016 }
12017 return false;
12018}
12019
12020bool isVPERMT2B(unsigned Opcode) {
12021 switch (Opcode) {
12022 case VPERMT2BZ128rm:
12023 case VPERMT2BZ128rmk:
12024 case VPERMT2BZ128rmkz:
12025 case VPERMT2BZ128rr:
12026 case VPERMT2BZ128rrk:
12027 case VPERMT2BZ128rrkz:
12028 case VPERMT2BZ256rm:
12029 case VPERMT2BZ256rmk:
12030 case VPERMT2BZ256rmkz:
12031 case VPERMT2BZ256rr:
12032 case VPERMT2BZ256rrk:
12033 case VPERMT2BZ256rrkz:
12034 case VPERMT2BZrm:
12035 case VPERMT2BZrmk:
12036 case VPERMT2BZrmkz:
12037 case VPERMT2BZrr:
12038 case VPERMT2BZrrk:
12039 case VPERMT2BZrrkz:
12040 return true;
12041 }
12042 return false;
12043}
12044
12045bool isVFMADD213PD(unsigned Opcode) {
12046 switch (Opcode) {
12047 case VFMADD213PDYm:
12048 case VFMADD213PDYr:
12049 case VFMADD213PDZ128m:
12050 case VFMADD213PDZ128mb:
12051 case VFMADD213PDZ128mbk:
12052 case VFMADD213PDZ128mbkz:
12053 case VFMADD213PDZ128mk:
12054 case VFMADD213PDZ128mkz:
12055 case VFMADD213PDZ128r:
12056 case VFMADD213PDZ128rk:
12057 case VFMADD213PDZ128rkz:
12058 case VFMADD213PDZ256m:
12059 case VFMADD213PDZ256mb:
12060 case VFMADD213PDZ256mbk:
12061 case VFMADD213PDZ256mbkz:
12062 case VFMADD213PDZ256mk:
12063 case VFMADD213PDZ256mkz:
12064 case VFMADD213PDZ256r:
12065 case VFMADD213PDZ256rk:
12066 case VFMADD213PDZ256rkz:
12067 case VFMADD213PDZm:
12068 case VFMADD213PDZmb:
12069 case VFMADD213PDZmbk:
12070 case VFMADD213PDZmbkz:
12071 case VFMADD213PDZmk:
12072 case VFMADD213PDZmkz:
12073 case VFMADD213PDZr:
12074 case VFMADD213PDZrb:
12075 case VFMADD213PDZrbk:
12076 case VFMADD213PDZrbkz:
12077 case VFMADD213PDZrk:
12078 case VFMADD213PDZrkz:
12079 case VFMADD213PDm:
12080 case VFMADD213PDr:
12081 return true;
12082 }
12083 return false;
12084}
12085
12086bool isVPGATHERQD(unsigned Opcode) {
12087 switch (Opcode) {
12088 case VPGATHERQDYrm:
12089 case VPGATHERQDZ128rm:
12090 case VPGATHERQDZ256rm:
12091 case VPGATHERQDZrm:
12092 case VPGATHERQDrm:
12093 return true;
12094 }
12095 return false;
12096}
12097
12098bool isVPCMPGTW(unsigned Opcode) {
12099 switch (Opcode) {
12100 case VPCMPGTWYrm:
12101 case VPCMPGTWYrr:
12102 case VPCMPGTWZ128rm:
12103 case VPCMPGTWZ128rmk:
12104 case VPCMPGTWZ128rr:
12105 case VPCMPGTWZ128rrk:
12106 case VPCMPGTWZ256rm:
12107 case VPCMPGTWZ256rmk:
12108 case VPCMPGTWZ256rr:
12109 case VPCMPGTWZ256rrk:
12110 case VPCMPGTWZrm:
12111 case VPCMPGTWZrmk:
12112 case VPCMPGTWZrr:
12113 case VPCMPGTWZrrk:
12114 case VPCMPGTWrm:
12115 case VPCMPGTWrr:
12116 return true;
12117 }
12118 return false;
12119}
12120
12121bool isVGETMANTSH(unsigned Opcode) {
12122 switch (Opcode) {
12123 case VGETMANTSHZrmi:
12124 case VGETMANTSHZrmik:
12125 case VGETMANTSHZrmikz:
12126 case VGETMANTSHZrri:
12127 case VGETMANTSHZrrib:
12128 case VGETMANTSHZrribk:
12129 case VGETMANTSHZrribkz:
12130 case VGETMANTSHZrrik:
12131 case VGETMANTSHZrrikz:
12132 return true;
12133 }
12134 return false;
12135}
12136
12137bool isVANDPS(unsigned Opcode) {
12138 switch (Opcode) {
12139 case VANDPSYrm:
12140 case VANDPSYrr:
12141 case VANDPSZ128rm:
12142 case VANDPSZ128rmb:
12143 case VANDPSZ128rmbk:
12144 case VANDPSZ128rmbkz:
12145 case VANDPSZ128rmk:
12146 case VANDPSZ128rmkz:
12147 case VANDPSZ128rr:
12148 case VANDPSZ128rrk:
12149 case VANDPSZ128rrkz:
12150 case VANDPSZ256rm:
12151 case VANDPSZ256rmb:
12152 case VANDPSZ256rmbk:
12153 case VANDPSZ256rmbkz:
12154 case VANDPSZ256rmk:
12155 case VANDPSZ256rmkz:
12156 case VANDPSZ256rr:
12157 case VANDPSZ256rrk:
12158 case VANDPSZ256rrkz:
12159 case VANDPSZrm:
12160 case VANDPSZrmb:
12161 case VANDPSZrmbk:
12162 case VANDPSZrmbkz:
12163 case VANDPSZrmk:
12164 case VANDPSZrmkz:
12165 case VANDPSZrr:
12166 case VANDPSZrrk:
12167 case VANDPSZrrkz:
12168 case VANDPSrm:
12169 case VANDPSrr:
12170 return true;
12171 }
12172 return false;
12173}
12174
12175bool isVDIVPS(unsigned Opcode) {
12176 switch (Opcode) {
12177 case VDIVPSYrm:
12178 case VDIVPSYrr:
12179 case VDIVPSZ128rm:
12180 case VDIVPSZ128rmb:
12181 case VDIVPSZ128rmbk:
12182 case VDIVPSZ128rmbkz:
12183 case VDIVPSZ128rmk:
12184 case VDIVPSZ128rmkz:
12185 case VDIVPSZ128rr:
12186 case VDIVPSZ128rrk:
12187 case VDIVPSZ128rrkz:
12188 case VDIVPSZ256rm:
12189 case VDIVPSZ256rmb:
12190 case VDIVPSZ256rmbk:
12191 case VDIVPSZ256rmbkz:
12192 case VDIVPSZ256rmk:
12193 case VDIVPSZ256rmkz:
12194 case VDIVPSZ256rr:
12195 case VDIVPSZ256rrk:
12196 case VDIVPSZ256rrkz:
12197 case VDIVPSZrm:
12198 case VDIVPSZrmb:
12199 case VDIVPSZrmbk:
12200 case VDIVPSZrmbkz:
12201 case VDIVPSZrmk:
12202 case VDIVPSZrmkz:
12203 case VDIVPSZrr:
12204 case VDIVPSZrrb:
12205 case VDIVPSZrrbk:
12206 case VDIVPSZrrbkz:
12207 case VDIVPSZrrk:
12208 case VDIVPSZrrkz:
12209 case VDIVPSrm:
12210 case VDIVPSrr:
12211 return true;
12212 }
12213 return false;
12214}
12215
12216bool isVANDNPS(unsigned Opcode) {
12217 switch (Opcode) {
12218 case VANDNPSYrm:
12219 case VANDNPSYrr:
12220 case VANDNPSZ128rm:
12221 case VANDNPSZ128rmb:
12222 case VANDNPSZ128rmbk:
12223 case VANDNPSZ128rmbkz:
12224 case VANDNPSZ128rmk:
12225 case VANDNPSZ128rmkz:
12226 case VANDNPSZ128rr:
12227 case VANDNPSZ128rrk:
12228 case VANDNPSZ128rrkz:
12229 case VANDNPSZ256rm:
12230 case VANDNPSZ256rmb:
12231 case VANDNPSZ256rmbk:
12232 case VANDNPSZ256rmbkz:
12233 case VANDNPSZ256rmk:
12234 case VANDNPSZ256rmkz:
12235 case VANDNPSZ256rr:
12236 case VANDNPSZ256rrk:
12237 case VANDNPSZ256rrkz:
12238 case VANDNPSZrm:
12239 case VANDNPSZrmb:
12240 case VANDNPSZrmbk:
12241 case VANDNPSZrmbkz:
12242 case VANDNPSZrmk:
12243 case VANDNPSZrmkz:
12244 case VANDNPSZrr:
12245 case VANDNPSZrrk:
12246 case VANDNPSZrrkz:
12247 case VANDNPSrm:
12248 case VANDNPSrr:
12249 return true;
12250 }
12251 return false;
12252}
12253
12254bool isVPBROADCASTW(unsigned Opcode) {
12255 switch (Opcode) {
12256 case VPBROADCASTWYrm:
12257 case VPBROADCASTWYrr:
12258 case VPBROADCASTWZ128rm:
12259 case VPBROADCASTWZ128rmk:
12260 case VPBROADCASTWZ128rmkz:
12261 case VPBROADCASTWZ128rr:
12262 case VPBROADCASTWZ128rrk:
12263 case VPBROADCASTWZ128rrkz:
12264 case VPBROADCASTWZ256rm:
12265 case VPBROADCASTWZ256rmk:
12266 case VPBROADCASTWZ256rmkz:
12267 case VPBROADCASTWZ256rr:
12268 case VPBROADCASTWZ256rrk:
12269 case VPBROADCASTWZ256rrkz:
12270 case VPBROADCASTWZrm:
12271 case VPBROADCASTWZrmk:
12272 case VPBROADCASTWZrmkz:
12273 case VPBROADCASTWZrr:
12274 case VPBROADCASTWZrrk:
12275 case VPBROADCASTWZrrkz:
12276 case VPBROADCASTWrZ128rr:
12277 case VPBROADCASTWrZ128rrk:
12278 case VPBROADCASTWrZ128rrkz:
12279 case VPBROADCASTWrZ256rr:
12280 case VPBROADCASTWrZ256rrk:
12281 case VPBROADCASTWrZ256rrkz:
12282 case VPBROADCASTWrZrr:
12283 case VPBROADCASTWrZrrk:
12284 case VPBROADCASTWrZrrkz:
12285 case VPBROADCASTWrm:
12286 case VPBROADCASTWrr:
12287 return true;
12288 }
12289 return false;
12290}
12291
12292bool isFLDL2T(unsigned Opcode) {
12293 return Opcode == FLDL2T;
12294}
12295
12296bool isVPERMB(unsigned Opcode) {
12297 switch (Opcode) {
12298 case VPERMBZ128rm:
12299 case VPERMBZ128rmk:
12300 case VPERMBZ128rmkz:
12301 case VPERMBZ128rr:
12302 case VPERMBZ128rrk:
12303 case VPERMBZ128rrkz:
12304 case VPERMBZ256rm:
12305 case VPERMBZ256rmk:
12306 case VPERMBZ256rmkz:
12307 case VPERMBZ256rr:
12308 case VPERMBZ256rrk:
12309 case VPERMBZ256rrkz:
12310 case VPERMBZrm:
12311 case VPERMBZrmk:
12312 case VPERMBZrmkz:
12313 case VPERMBZrr:
12314 case VPERMBZrrk:
12315 case VPERMBZrrkz:
12316 return true;
12317 }
12318 return false;
12319}
12320
12321bool isFCMOVNBE(unsigned Opcode) {
12322 return Opcode == CMOVNBE_F;
12323}
12324
12325bool isVCVTTPH2W(unsigned Opcode) {
12326 switch (Opcode) {
12327 case VCVTTPH2WZ128rm:
12328 case VCVTTPH2WZ128rmb:
12329 case VCVTTPH2WZ128rmbk:
12330 case VCVTTPH2WZ128rmbkz:
12331 case VCVTTPH2WZ128rmk:
12332 case VCVTTPH2WZ128rmkz:
12333 case VCVTTPH2WZ128rr:
12334 case VCVTTPH2WZ128rrk:
12335 case VCVTTPH2WZ128rrkz:
12336 case VCVTTPH2WZ256rm:
12337 case VCVTTPH2WZ256rmb:
12338 case VCVTTPH2WZ256rmbk:
12339 case VCVTTPH2WZ256rmbkz:
12340 case VCVTTPH2WZ256rmk:
12341 case VCVTTPH2WZ256rmkz:
12342 case VCVTTPH2WZ256rr:
12343 case VCVTTPH2WZ256rrk:
12344 case VCVTTPH2WZ256rrkz:
12345 case VCVTTPH2WZrm:
12346 case VCVTTPH2WZrmb:
12347 case VCVTTPH2WZrmbk:
12348 case VCVTTPH2WZrmbkz:
12349 case VCVTTPH2WZrmk:
12350 case VCVTTPH2WZrmkz:
12351 case VCVTTPH2WZrr:
12352 case VCVTTPH2WZrrb:
12353 case VCVTTPH2WZrrbk:
12354 case VCVTTPH2WZrrbkz:
12355 case VCVTTPH2WZrrk:
12356 case VCVTTPH2WZrrkz:
12357 return true;
12358 }
12359 return false;
12360}
12361
12362bool isPMOVZXBQ(unsigned Opcode) {
12363 switch (Opcode) {
12364 case PMOVZXBQrm:
12365 case PMOVZXBQrr:
12366 return true;
12367 }
12368 return false;
12369}
12370
12371bool isPF2ID(unsigned Opcode) {
12372 switch (Opcode) {
12373 case PF2IDrm:
12374 case PF2IDrr:
12375 return true;
12376 }
12377 return false;
12378}
12379
12380bool isVFNMADD132PD(unsigned Opcode) {
12381 switch (Opcode) {
12382 case VFNMADD132PDYm:
12383 case VFNMADD132PDYr:
12384 case VFNMADD132PDZ128m:
12385 case VFNMADD132PDZ128mb:
12386 case VFNMADD132PDZ128mbk:
12387 case VFNMADD132PDZ128mbkz:
12388 case VFNMADD132PDZ128mk:
12389 case VFNMADD132PDZ128mkz:
12390 case VFNMADD132PDZ128r:
12391 case VFNMADD132PDZ128rk:
12392 case VFNMADD132PDZ128rkz:
12393 case VFNMADD132PDZ256m:
12394 case VFNMADD132PDZ256mb:
12395 case VFNMADD132PDZ256mbk:
12396 case VFNMADD132PDZ256mbkz:
12397 case VFNMADD132PDZ256mk:
12398 case VFNMADD132PDZ256mkz:
12399 case VFNMADD132PDZ256r:
12400 case VFNMADD132PDZ256rk:
12401 case VFNMADD132PDZ256rkz:
12402 case VFNMADD132PDZm:
12403 case VFNMADD132PDZmb:
12404 case VFNMADD132PDZmbk:
12405 case VFNMADD132PDZmbkz:
12406 case VFNMADD132PDZmk:
12407 case VFNMADD132PDZmkz:
12408 case VFNMADD132PDZr:
12409 case VFNMADD132PDZrb:
12410 case VFNMADD132PDZrbk:
12411 case VFNMADD132PDZrbkz:
12412 case VFNMADD132PDZrk:
12413 case VFNMADD132PDZrkz:
12414 case VFNMADD132PDm:
12415 case VFNMADD132PDr:
12416 return true;
12417 }
12418 return false;
12419}
12420
12421bool isPMULHRSW(unsigned Opcode) {
12422 switch (Opcode) {
12423 case MMX_PMULHRSWrm:
12424 case MMX_PMULHRSWrr:
12425 case PMULHRSWrm:
12426 case PMULHRSWrr:
12427 return true;
12428 }
12429 return false;
12430}
12431
12432bool isKADDD(unsigned Opcode) {
12433 return Opcode == KADDDrr;
12434}
12435
12436bool isVFNMSUB132SH(unsigned Opcode) {
12437 switch (Opcode) {
12438 case VFNMSUB132SHZm_Int:
12439 case VFNMSUB132SHZm_Intk:
12440 case VFNMSUB132SHZm_Intkz:
12441 case VFNMSUB132SHZr_Int:
12442 case VFNMSUB132SHZr_Intk:
12443 case VFNMSUB132SHZr_Intkz:
12444 case VFNMSUB132SHZrb_Int:
12445 case VFNMSUB132SHZrb_Intk:
12446 case VFNMSUB132SHZrb_Intkz:
12447 return true;
12448 }
12449 return false;
12450}
12451
12452bool isUIRET(unsigned Opcode) {
12453 return Opcode == UIRET;
12454}
12455
12456bool isBSR(unsigned Opcode) {
12457 switch (Opcode) {
12458 case BSR16rm:
12459 case BSR16rr:
12460 case BSR32rm:
12461 case BSR32rr:
12462 case BSR64rm:
12463 case BSR64rr:
12464 return true;
12465 }
12466 return false;
12467}
12468
12469bool isPCMPEQQ(unsigned Opcode) {
12470 switch (Opcode) {
12471 case PCMPEQQrm:
12472 case PCMPEQQrr:
12473 return true;
12474 }
12475 return false;
12476}
12477
12478bool isCDQ(unsigned Opcode) {
12479 return Opcode == CDQ;
12480}
12481
12482bool isPMAXSW(unsigned Opcode) {
12483 switch (Opcode) {
12484 case MMX_PMAXSWrm:
12485 case MMX_PMAXSWrr:
12486 case PMAXSWrm:
12487 case PMAXSWrr:
12488 return true;
12489 }
12490 return false;
12491}
12492
12493bool isSIDTD(unsigned Opcode) {
12494 return Opcode == SIDT32m;
12495}
12496
12497bool isVCVTPS2PHX(unsigned Opcode) {
12498 switch (Opcode) {
12499 case VCVTPS2PHXZ128rm:
12500 case VCVTPS2PHXZ128rmb:
12501 case VCVTPS2PHXZ128rmbk:
12502 case VCVTPS2PHXZ128rmbkz:
12503 case VCVTPS2PHXZ128rmk:
12504 case VCVTPS2PHXZ128rmkz:
12505 case VCVTPS2PHXZ128rr:
12506 case VCVTPS2PHXZ128rrk:
12507 case VCVTPS2PHXZ128rrkz:
12508 case VCVTPS2PHXZ256rm:
12509 case VCVTPS2PHXZ256rmb:
12510 case VCVTPS2PHXZ256rmbk:
12511 case VCVTPS2PHXZ256rmbkz:
12512 case VCVTPS2PHXZ256rmk:
12513 case VCVTPS2PHXZ256rmkz:
12514 case VCVTPS2PHXZ256rr:
12515 case VCVTPS2PHXZ256rrk:
12516 case VCVTPS2PHXZ256rrkz:
12517 case VCVTPS2PHXZrm:
12518 case VCVTPS2PHXZrmb:
12519 case VCVTPS2PHXZrmbk:
12520 case VCVTPS2PHXZrmbkz:
12521 case VCVTPS2PHXZrmk:
12522 case VCVTPS2PHXZrmkz:
12523 case VCVTPS2PHXZrr:
12524 case VCVTPS2PHXZrrb:
12525 case VCVTPS2PHXZrrbk:
12526 case VCVTPS2PHXZrrbkz:
12527 case VCVTPS2PHXZrrk:
12528 case VCVTPS2PHXZrrkz:
12529 return true;
12530 }
12531 return false;
12532}
12533
12534bool isVPSLLVQ(unsigned Opcode) {
12535 switch (Opcode) {
12536 case VPSLLVQYrm:
12537 case VPSLLVQYrr:
12538 case VPSLLVQZ128rm:
12539 case VPSLLVQZ128rmb:
12540 case VPSLLVQZ128rmbk:
12541 case VPSLLVQZ128rmbkz:
12542 case VPSLLVQZ128rmk:
12543 case VPSLLVQZ128rmkz:
12544 case VPSLLVQZ128rr:
12545 case VPSLLVQZ128rrk:
12546 case VPSLLVQZ128rrkz:
12547 case VPSLLVQZ256rm:
12548 case VPSLLVQZ256rmb:
12549 case VPSLLVQZ256rmbk:
12550 case VPSLLVQZ256rmbkz:
12551 case VPSLLVQZ256rmk:
12552 case VPSLLVQZ256rmkz:
12553 case VPSLLVQZ256rr:
12554 case VPSLLVQZ256rrk:
12555 case VPSLLVQZ256rrkz:
12556 case VPSLLVQZrm:
12557 case VPSLLVQZrmb:
12558 case VPSLLVQZrmbk:
12559 case VPSLLVQZrmbkz:
12560 case VPSLLVQZrmk:
12561 case VPSLLVQZrmkz:
12562 case VPSLLVQZrr:
12563 case VPSLLVQZrrk:
12564 case VPSLLVQZrrkz:
12565 case VPSLLVQrm:
12566 case VPSLLVQrr:
12567 return true;
12568 }
12569 return false;
12570}
12571
12572bool isMOVQ(unsigned Opcode) {
12573 switch (Opcode) {
12574 case MMX_MOVD64from64mr:
12575 case MMX_MOVD64from64rr:
12576 case MMX_MOVD64to64rm:
12577 case MMX_MOVD64to64rr:
12578 case MMX_MOVQ64mr:
12579 case MMX_MOVQ64rm:
12580 case MMX_MOVQ64rr:
12581 case MMX_MOVQ64rr_REV:
12582 case MOV64toPQIrm:
12583 case MOV64toPQIrr:
12584 case MOVPQI2QImr:
12585 case MOVPQI2QIrr:
12586 case MOVPQIto64mr:
12587 case MOVPQIto64rr:
12588 case MOVQI2PQIrm:
12589 case MOVZPQILo2PQIrr:
12590 return true;
12591 }
12592 return false;
12593}
12594
12595bool isPREFETCH(unsigned Opcode) {
12596 return Opcode == PREFETCH;
12597}
12598
12599bool isCLRSSBSY(unsigned Opcode) {
12600 return Opcode == CLRSSBSY;
12601}
12602
12603bool isPSHUFW(unsigned Opcode) {
12604 switch (Opcode) {
12605 case MMX_PSHUFWmi:
12606 case MMX_PSHUFWri:
12607 return true;
12608 }
12609 return false;
12610}
12611
12612bool isVPDPWSUDS(unsigned Opcode) {
12613 switch (Opcode) {
12614 case VPDPWSUDSYrm:
12615 case VPDPWSUDSYrr:
12616 case VPDPWSUDSrm:
12617 case VPDPWSUDSrr:
12618 return true;
12619 }
12620 return false;
12621}
12622
12623bool isVPMOVSXBQ(unsigned Opcode) {
12624 switch (Opcode) {
12625 case VPMOVSXBQYrm:
12626 case VPMOVSXBQYrr:
12627 case VPMOVSXBQZ128rm:
12628 case VPMOVSXBQZ128rmk:
12629 case VPMOVSXBQZ128rmkz:
12630 case VPMOVSXBQZ128rr:
12631 case VPMOVSXBQZ128rrk:
12632 case VPMOVSXBQZ128rrkz:
12633 case VPMOVSXBQZ256rm:
12634 case VPMOVSXBQZ256rmk:
12635 case VPMOVSXBQZ256rmkz:
12636 case VPMOVSXBQZ256rr:
12637 case VPMOVSXBQZ256rrk:
12638 case VPMOVSXBQZ256rrkz:
12639 case VPMOVSXBQZrm:
12640 case VPMOVSXBQZrmk:
12641 case VPMOVSXBQZrmkz:
12642 case VPMOVSXBQZrr:
12643 case VPMOVSXBQZrrk:
12644 case VPMOVSXBQZrrkz:
12645 case VPMOVSXBQrm:
12646 case VPMOVSXBQrr:
12647 return true;
12648 }
12649 return false;
12650}
12651
12652bool isFICOMP(unsigned Opcode) {
12653 switch (Opcode) {
12654 case FICOMP16m:
12655 case FICOMP32m:
12656 return true;
12657 }
12658 return false;
12659}
12660
12661bool isVLDMXCSR(unsigned Opcode) {
12662 return Opcode == VLDMXCSR;
12663}
12664
12665bool isVPSUBUSW(unsigned Opcode) {
12666 switch (Opcode) {
12667 case VPSUBUSWYrm:
12668 case VPSUBUSWYrr:
12669 case VPSUBUSWZ128rm:
12670 case VPSUBUSWZ128rmk:
12671 case VPSUBUSWZ128rmkz:
12672 case VPSUBUSWZ128rr:
12673 case VPSUBUSWZ128rrk:
12674 case VPSUBUSWZ128rrkz:
12675 case VPSUBUSWZ256rm:
12676 case VPSUBUSWZ256rmk:
12677 case VPSUBUSWZ256rmkz:
12678 case VPSUBUSWZ256rr:
12679 case VPSUBUSWZ256rrk:
12680 case VPSUBUSWZ256rrkz:
12681 case VPSUBUSWZrm:
12682 case VPSUBUSWZrmk:
12683 case VPSUBUSWZrmkz:
12684 case VPSUBUSWZrr:
12685 case VPSUBUSWZrrk:
12686 case VPSUBUSWZrrkz:
12687 case VPSUBUSWrm:
12688 case VPSUBUSWrr:
12689 return true;
12690 }
12691 return false;
12692}
12693
12694bool isVFNMSUB132SS(unsigned Opcode) {
12695 switch (Opcode) {
12696 case VFNMSUB132SSZm_Int:
12697 case VFNMSUB132SSZm_Intk:
12698 case VFNMSUB132SSZm_Intkz:
12699 case VFNMSUB132SSZr_Int:
12700 case VFNMSUB132SSZr_Intk:
12701 case VFNMSUB132SSZr_Intkz:
12702 case VFNMSUB132SSZrb_Int:
12703 case VFNMSUB132SSZrb_Intk:
12704 case VFNMSUB132SSZrb_Intkz:
12705 case VFNMSUB132SSm_Int:
12706 case VFNMSUB132SSr_Int:
12707 return true;
12708 }
12709 return false;
12710}
12711
12712bool isRETF(unsigned Opcode) {
12713 switch (Opcode) {
12714 case LRET16:
12715 case LRET32:
12716 case LRETI16:
12717 case LRETI32:
12718 return true;
12719 }
12720 return false;
12721}
12722
12723bool isKMOVQ(unsigned Opcode) {
12724 switch (Opcode) {
12725 case KMOVQkk:
12726 case KMOVQkk_EVEX:
12727 case KMOVQkm:
12728 case KMOVQkm_EVEX:
12729 case KMOVQkr:
12730 case KMOVQkr_EVEX:
12731 case KMOVQmk:
12732 case KMOVQmk_EVEX:
12733 case KMOVQrk:
12734 case KMOVQrk_EVEX:
12735 return true;
12736 }
12737 return false;
12738}
12739
12740bool isVPADDUSW(unsigned Opcode) {
12741 switch (Opcode) {
12742 case VPADDUSWYrm:
12743 case VPADDUSWYrr:
12744 case VPADDUSWZ128rm:
12745 case VPADDUSWZ128rmk:
12746 case VPADDUSWZ128rmkz:
12747 case VPADDUSWZ128rr:
12748 case VPADDUSWZ128rrk:
12749 case VPADDUSWZ128rrkz:
12750 case VPADDUSWZ256rm:
12751 case VPADDUSWZ256rmk:
12752 case VPADDUSWZ256rmkz:
12753 case VPADDUSWZ256rr:
12754 case VPADDUSWZ256rrk:
12755 case VPADDUSWZ256rrkz:
12756 case VPADDUSWZrm:
12757 case VPADDUSWZrmk:
12758 case VPADDUSWZrmkz:
12759 case VPADDUSWZrr:
12760 case VPADDUSWZrrk:
12761 case VPADDUSWZrrkz:
12762 case VPADDUSWrm:
12763 case VPADDUSWrr:
12764 return true;
12765 }
12766 return false;
12767}
12768
12769bool isPACKSSDW(unsigned Opcode) {
12770 switch (Opcode) {
12771 case MMX_PACKSSDWrm:
12772 case MMX_PACKSSDWrr:
12773 case PACKSSDWrm:
12774 case PACKSSDWrr:
12775 return true;
12776 }
12777 return false;
12778}
12779
12780bool isUMONITOR(unsigned Opcode) {
12781 switch (Opcode) {
12782 case UMONITOR16:
12783 case UMONITOR32:
12784 case UMONITOR64:
12785 return true;
12786 }
12787 return false;
12788}
12789
12790bool isENQCMDS(unsigned Opcode) {
12791 switch (Opcode) {
12792 case ENQCMDS16:
12793 case ENQCMDS32:
12794 case ENQCMDS32_EVEX:
12795 case ENQCMDS64:
12796 case ENQCMDS64_EVEX:
12797 return true;
12798 }
12799 return false;
12800}
12801
12802bool isVPMAXSQ(unsigned Opcode) {
12803 switch (Opcode) {
12804 case VPMAXSQZ128rm:
12805 case VPMAXSQZ128rmb:
12806 case VPMAXSQZ128rmbk:
12807 case VPMAXSQZ128rmbkz:
12808 case VPMAXSQZ128rmk:
12809 case VPMAXSQZ128rmkz:
12810 case VPMAXSQZ128rr:
12811 case VPMAXSQZ128rrk:
12812 case VPMAXSQZ128rrkz:
12813 case VPMAXSQZ256rm:
12814 case VPMAXSQZ256rmb:
12815 case VPMAXSQZ256rmbk:
12816 case VPMAXSQZ256rmbkz:
12817 case VPMAXSQZ256rmk:
12818 case VPMAXSQZ256rmkz:
12819 case VPMAXSQZ256rr:
12820 case VPMAXSQZ256rrk:
12821 case VPMAXSQZ256rrkz:
12822 case VPMAXSQZrm:
12823 case VPMAXSQZrmb:
12824 case VPMAXSQZrmbk:
12825 case VPMAXSQZrmbkz:
12826 case VPMAXSQZrmk:
12827 case VPMAXSQZrmkz:
12828 case VPMAXSQZrr:
12829 case VPMAXSQZrrk:
12830 case VPMAXSQZrrkz:
12831 return true;
12832 }
12833 return false;
12834}
12835
12836bool isVPERMT2Q(unsigned Opcode) {
12837 switch (Opcode) {
12838 case VPERMT2QZ128rm:
12839 case VPERMT2QZ128rmb:
12840 case VPERMT2QZ128rmbk:
12841 case VPERMT2QZ128rmbkz:
12842 case VPERMT2QZ128rmk:
12843 case VPERMT2QZ128rmkz:
12844 case VPERMT2QZ128rr:
12845 case VPERMT2QZ128rrk:
12846 case VPERMT2QZ128rrkz:
12847 case VPERMT2QZ256rm:
12848 case VPERMT2QZ256rmb:
12849 case VPERMT2QZ256rmbk:
12850 case VPERMT2QZ256rmbkz:
12851 case VPERMT2QZ256rmk:
12852 case VPERMT2QZ256rmkz:
12853 case VPERMT2QZ256rr:
12854 case VPERMT2QZ256rrk:
12855 case VPERMT2QZ256rrkz:
12856 case VPERMT2QZrm:
12857 case VPERMT2QZrmb:
12858 case VPERMT2QZrmbk:
12859 case VPERMT2QZrmbkz:
12860 case VPERMT2QZrmk:
12861 case VPERMT2QZrmkz:
12862 case VPERMT2QZrr:
12863 case VPERMT2QZrrk:
12864 case VPERMT2QZrrkz:
12865 return true;
12866 }
12867 return false;
12868}
12869
12870bool isFDECSTP(unsigned Opcode) {
12871 return Opcode == FDECSTP;
12872}
12873
12874bool isVPTESTMQ(unsigned Opcode) {
12875 switch (Opcode) {
12876 case VPTESTMQZ128rm:
12877 case VPTESTMQZ128rmb:
12878 case VPTESTMQZ128rmbk:
12879 case VPTESTMQZ128rmk:
12880 case VPTESTMQZ128rr:
12881 case VPTESTMQZ128rrk:
12882 case VPTESTMQZ256rm:
12883 case VPTESTMQZ256rmb:
12884 case VPTESTMQZ256rmbk:
12885 case VPTESTMQZ256rmk:
12886 case VPTESTMQZ256rr:
12887 case VPTESTMQZ256rrk:
12888 case VPTESTMQZrm:
12889 case VPTESTMQZrmb:
12890 case VPTESTMQZrmbk:
12891 case VPTESTMQZrmk:
12892 case VPTESTMQZrr:
12893 case VPTESTMQZrrk:
12894 return true;
12895 }
12896 return false;
12897}
12898
12899bool isVRCP14PD(unsigned Opcode) {
12900 switch (Opcode) {
12901 case VRCP14PDZ128m:
12902 case VRCP14PDZ128mb:
12903 case VRCP14PDZ128mbk:
12904 case VRCP14PDZ128mbkz:
12905 case VRCP14PDZ128mk:
12906 case VRCP14PDZ128mkz:
12907 case VRCP14PDZ128r:
12908 case VRCP14PDZ128rk:
12909 case VRCP14PDZ128rkz:
12910 case VRCP14PDZ256m:
12911 case VRCP14PDZ256mb:
12912 case VRCP14PDZ256mbk:
12913 case VRCP14PDZ256mbkz:
12914 case VRCP14PDZ256mk:
12915 case VRCP14PDZ256mkz:
12916 case VRCP14PDZ256r:
12917 case VRCP14PDZ256rk:
12918 case VRCP14PDZ256rkz:
12919 case VRCP14PDZm:
12920 case VRCP14PDZmb:
12921 case VRCP14PDZmbk:
12922 case VRCP14PDZmbkz:
12923 case VRCP14PDZmk:
12924 case VRCP14PDZmkz:
12925 case VRCP14PDZr:
12926 case VRCP14PDZrk:
12927 case VRCP14PDZrkz:
12928 return true;
12929 }
12930 return false;
12931}
12932
12933bool isARPL(unsigned Opcode) {
12934 switch (Opcode) {
12935 case ARPL16mr:
12936 case ARPL16rr:
12937 return true;
12938 }
12939 return false;
12940}
12941
12942bool isVFMSUB213SD(unsigned Opcode) {
12943 switch (Opcode) {
12944 case VFMSUB213SDZm_Int:
12945 case VFMSUB213SDZm_Intk:
12946 case VFMSUB213SDZm_Intkz:
12947 case VFMSUB213SDZr_Int:
12948 case VFMSUB213SDZr_Intk:
12949 case VFMSUB213SDZr_Intkz:
12950 case VFMSUB213SDZrb_Int:
12951 case VFMSUB213SDZrb_Intk:
12952 case VFMSUB213SDZrb_Intkz:
12953 case VFMSUB213SDm_Int:
12954 case VFMSUB213SDr_Int:
12955 return true;
12956 }
12957 return false;
12958}
12959
12960bool isJMPABS(unsigned Opcode) {
12961 return Opcode == JMPABS64i;
12962}
12963
12964bool isVUNPCKHPS(unsigned Opcode) {
12965 switch (Opcode) {
12966 case VUNPCKHPSYrm:
12967 case VUNPCKHPSYrr:
12968 case VUNPCKHPSZ128rm:
12969 case VUNPCKHPSZ128rmb:
12970 case VUNPCKHPSZ128rmbk:
12971 case VUNPCKHPSZ128rmbkz:
12972 case VUNPCKHPSZ128rmk:
12973 case VUNPCKHPSZ128rmkz:
12974 case VUNPCKHPSZ128rr:
12975 case VUNPCKHPSZ128rrk:
12976 case VUNPCKHPSZ128rrkz:
12977 case VUNPCKHPSZ256rm:
12978 case VUNPCKHPSZ256rmb:
12979 case VUNPCKHPSZ256rmbk:
12980 case VUNPCKHPSZ256rmbkz:
12981 case VUNPCKHPSZ256rmk:
12982 case VUNPCKHPSZ256rmkz:
12983 case VUNPCKHPSZ256rr:
12984 case VUNPCKHPSZ256rrk:
12985 case VUNPCKHPSZ256rrkz:
12986 case VUNPCKHPSZrm:
12987 case VUNPCKHPSZrmb:
12988 case VUNPCKHPSZrmbk:
12989 case VUNPCKHPSZrmbkz:
12990 case VUNPCKHPSZrmk:
12991 case VUNPCKHPSZrmkz:
12992 case VUNPCKHPSZrr:
12993 case VUNPCKHPSZrrk:
12994 case VUNPCKHPSZrrkz:
12995 case VUNPCKHPSrm:
12996 case VUNPCKHPSrr:
12997 return true;
12998 }
12999 return false;
13000}
13001
13002bool isVFNMADDSS(unsigned Opcode) {
13003 switch (Opcode) {
13004 case VFNMADDSS4mr:
13005 case VFNMADDSS4rm:
13006 case VFNMADDSS4rr:
13007 case VFNMADDSS4rr_REV:
13008 return true;
13009 }
13010 return false;
13011}
13012
13013bool isSIDT(unsigned Opcode) {
13014 return Opcode == SIDT64m;
13015}
13016
13017bool isVPCMPGTB(unsigned Opcode) {
13018 switch (Opcode) {
13019 case VPCMPGTBYrm:
13020 case VPCMPGTBYrr:
13021 case VPCMPGTBZ128rm:
13022 case VPCMPGTBZ128rmk:
13023 case VPCMPGTBZ128rr:
13024 case VPCMPGTBZ128rrk:
13025 case VPCMPGTBZ256rm:
13026 case VPCMPGTBZ256rmk:
13027 case VPCMPGTBZ256rr:
13028 case VPCMPGTBZ256rrk:
13029 case VPCMPGTBZrm:
13030 case VPCMPGTBZrmk:
13031 case VPCMPGTBZrr:
13032 case VPCMPGTBZrrk:
13033 case VPCMPGTBrm:
13034 case VPCMPGTBrr:
13035 return true;
13036 }
13037 return false;
13038}
13039
13040bool isVPRORD(unsigned Opcode) {
13041 switch (Opcode) {
13042 case VPRORDZ128mbi:
13043 case VPRORDZ128mbik:
13044 case VPRORDZ128mbikz:
13045 case VPRORDZ128mi:
13046 case VPRORDZ128mik:
13047 case VPRORDZ128mikz:
13048 case VPRORDZ128ri:
13049 case VPRORDZ128rik:
13050 case VPRORDZ128rikz:
13051 case VPRORDZ256mbi:
13052 case VPRORDZ256mbik:
13053 case VPRORDZ256mbikz:
13054 case VPRORDZ256mi:
13055 case VPRORDZ256mik:
13056 case VPRORDZ256mikz:
13057 case VPRORDZ256ri:
13058 case VPRORDZ256rik:
13059 case VPRORDZ256rikz:
13060 case VPRORDZmbi:
13061 case VPRORDZmbik:
13062 case VPRORDZmbikz:
13063 case VPRORDZmi:
13064 case VPRORDZmik:
13065 case VPRORDZmikz:
13066 case VPRORDZri:
13067 case VPRORDZrik:
13068 case VPRORDZrikz:
13069 return true;
13070 }
13071 return false;
13072}
13073
13074bool isVSUBSS(unsigned Opcode) {
13075 switch (Opcode) {
13076 case VSUBSSZrm_Int:
13077 case VSUBSSZrm_Intk:
13078 case VSUBSSZrm_Intkz:
13079 case VSUBSSZrr_Int:
13080 case VSUBSSZrr_Intk:
13081 case VSUBSSZrr_Intkz:
13082 case VSUBSSZrrb_Int:
13083 case VSUBSSZrrb_Intk:
13084 case VSUBSSZrrb_Intkz:
13085 case VSUBSSrm_Int:
13086 case VSUBSSrr_Int:
13087 return true;
13088 }
13089 return false;
13090}
13091
13092bool isPUSHFQ(unsigned Opcode) {
13093 return Opcode == PUSHF64;
13094}
13095
13096bool isVPCLMULQDQ(unsigned Opcode) {
13097 switch (Opcode) {
13098 case VPCLMULQDQYrmi:
13099 case VPCLMULQDQYrri:
13100 case VPCLMULQDQZ128rmi:
13101 case VPCLMULQDQZ128rri:
13102 case VPCLMULQDQZ256rmi:
13103 case VPCLMULQDQZ256rri:
13104 case VPCLMULQDQZrmi:
13105 case VPCLMULQDQZrri:
13106 case VPCLMULQDQrmi:
13107 case VPCLMULQDQrri:
13108 return true;
13109 }
13110 return false;
13111}
13112
13113bool isVPADDUSB(unsigned Opcode) {
13114 switch (Opcode) {
13115 case VPADDUSBYrm:
13116 case VPADDUSBYrr:
13117 case VPADDUSBZ128rm:
13118 case VPADDUSBZ128rmk:
13119 case VPADDUSBZ128rmkz:
13120 case VPADDUSBZ128rr:
13121 case VPADDUSBZ128rrk:
13122 case VPADDUSBZ128rrkz:
13123 case VPADDUSBZ256rm:
13124 case VPADDUSBZ256rmk:
13125 case VPADDUSBZ256rmkz:
13126 case VPADDUSBZ256rr:
13127 case VPADDUSBZ256rrk:
13128 case VPADDUSBZ256rrkz:
13129 case VPADDUSBZrm:
13130 case VPADDUSBZrmk:
13131 case VPADDUSBZrmkz:
13132 case VPADDUSBZrr:
13133 case VPADDUSBZrrk:
13134 case VPADDUSBZrrkz:
13135 case VPADDUSBrm:
13136 case VPADDUSBrr:
13137 return true;
13138 }
13139 return false;
13140}
13141
13142bool isVPCMPD(unsigned Opcode) {
13143 switch (Opcode) {
13144 case VPCMPDZ128rmi:
13145 case VPCMPDZ128rmib:
13146 case VPCMPDZ128rmibk:
13147 case VPCMPDZ128rmik:
13148 case VPCMPDZ128rri:
13149 case VPCMPDZ128rrik:
13150 case VPCMPDZ256rmi:
13151 case VPCMPDZ256rmib:
13152 case VPCMPDZ256rmibk:
13153 case VPCMPDZ256rmik:
13154 case VPCMPDZ256rri:
13155 case VPCMPDZ256rrik:
13156 case VPCMPDZrmi:
13157 case VPCMPDZrmib:
13158 case VPCMPDZrmibk:
13159 case VPCMPDZrmik:
13160 case VPCMPDZrri:
13161 case VPCMPDZrrik:
13162 return true;
13163 }
13164 return false;
13165}
13166
13167bool isMOVSD(unsigned Opcode) {
13168 switch (Opcode) {
13169 case MOVSDmr:
13170 case MOVSDrm:
13171 case MOVSDrr:
13172 case MOVSDrr_REV:
13173 case MOVSL:
13174 return true;
13175 }
13176 return false;
13177}
13178
13179bool isPSUBUSW(unsigned Opcode) {
13180 switch (Opcode) {
13181 case MMX_PSUBUSWrm:
13182 case MMX_PSUBUSWrr:
13183 case PSUBUSWrm:
13184 case PSUBUSWrr:
13185 return true;
13186 }
13187 return false;
13188}
13189
13190bool isVFMSUBADD132PS(unsigned Opcode) {
13191 switch (Opcode) {
13192 case VFMSUBADD132PSYm:
13193 case VFMSUBADD132PSYr:
13194 case VFMSUBADD132PSZ128m:
13195 case VFMSUBADD132PSZ128mb:
13196 case VFMSUBADD132PSZ128mbk:
13197 case VFMSUBADD132PSZ128mbkz:
13198 case VFMSUBADD132PSZ128mk:
13199 case VFMSUBADD132PSZ128mkz:
13200 case VFMSUBADD132PSZ128r:
13201 case VFMSUBADD132PSZ128rk:
13202 case VFMSUBADD132PSZ128rkz:
13203 case VFMSUBADD132PSZ256m:
13204 case VFMSUBADD132PSZ256mb:
13205 case VFMSUBADD132PSZ256mbk:
13206 case VFMSUBADD132PSZ256mbkz:
13207 case VFMSUBADD132PSZ256mk:
13208 case VFMSUBADD132PSZ256mkz:
13209 case VFMSUBADD132PSZ256r:
13210 case VFMSUBADD132PSZ256rk:
13211 case VFMSUBADD132PSZ256rkz:
13212 case VFMSUBADD132PSZm:
13213 case VFMSUBADD132PSZmb:
13214 case VFMSUBADD132PSZmbk:
13215 case VFMSUBADD132PSZmbkz:
13216 case VFMSUBADD132PSZmk:
13217 case VFMSUBADD132PSZmkz:
13218 case VFMSUBADD132PSZr:
13219 case VFMSUBADD132PSZrb:
13220 case VFMSUBADD132PSZrbk:
13221 case VFMSUBADD132PSZrbkz:
13222 case VFMSUBADD132PSZrk:
13223 case VFMSUBADD132PSZrkz:
13224 case VFMSUBADD132PSm:
13225 case VFMSUBADD132PSr:
13226 return true;
13227 }
13228 return false;
13229}
13230
13231bool isMOVMSKPS(unsigned Opcode) {
13232 return Opcode == MOVMSKPSrr;
13233}
13234
13235bool isVFIXUPIMMSS(unsigned Opcode) {
13236 switch (Opcode) {
13237 case VFIXUPIMMSSZrmi:
13238 case VFIXUPIMMSSZrmik:
13239 case VFIXUPIMMSSZrmikz:
13240 case VFIXUPIMMSSZrri:
13241 case VFIXUPIMMSSZrrib:
13242 case VFIXUPIMMSSZrribk:
13243 case VFIXUPIMMSSZrribkz:
13244 case VFIXUPIMMSSZrrik:
13245 case VFIXUPIMMSSZrrikz:
13246 return true;
13247 }
13248 return false;
13249}
13250
13251bool isMFENCE(unsigned Opcode) {
13252 return Opcode == MFENCE;
13253}
13254
13255bool isFTST(unsigned Opcode) {
13256 return Opcode == TST_F;
13257}
13258
13259bool isVPMADDWD(unsigned Opcode) {
13260 switch (Opcode) {
13261 case VPMADDWDYrm:
13262 case VPMADDWDYrr:
13263 case VPMADDWDZ128rm:
13264 case VPMADDWDZ128rmk:
13265 case VPMADDWDZ128rmkz:
13266 case VPMADDWDZ128rr:
13267 case VPMADDWDZ128rrk:
13268 case VPMADDWDZ128rrkz:
13269 case VPMADDWDZ256rm:
13270 case VPMADDWDZ256rmk:
13271 case VPMADDWDZ256rmkz:
13272 case VPMADDWDZ256rr:
13273 case VPMADDWDZ256rrk:
13274 case VPMADDWDZ256rrkz:
13275 case VPMADDWDZrm:
13276 case VPMADDWDZrmk:
13277 case VPMADDWDZrmkz:
13278 case VPMADDWDZrr:
13279 case VPMADDWDZrrk:
13280 case VPMADDWDZrrkz:
13281 case VPMADDWDrm:
13282 case VPMADDWDrr:
13283 return true;
13284 }
13285 return false;
13286}
13287
13288bool isPOP(unsigned Opcode) {
13289 switch (Opcode) {
13290 case POP16r:
13291 case POP16rmm:
13292 case POP16rmr:
13293 case POP32r:
13294 case POP32rmm:
13295 case POP32rmr:
13296 case POP64r:
13297 case POP64rmm:
13298 case POP64rmr:
13299 case POPDS16:
13300 case POPDS32:
13301 case POPES16:
13302 case POPES32:
13303 case POPFS16:
13304 case POPFS32:
13305 case POPFS64:
13306 case POPGS16:
13307 case POPGS32:
13308 case POPGS64:
13309 case POPSS16:
13310 case POPSS32:
13311 return true;
13312 }
13313 return false;
13314}
13315
13316bool isPSUBW(unsigned Opcode) {
13317 switch (Opcode) {
13318 case MMX_PSUBWrm:
13319 case MMX_PSUBWrr:
13320 case PSUBWrm:
13321 case PSUBWrr:
13322 return true;
13323 }
13324 return false;
13325}
13326
13327bool isBSWAP(unsigned Opcode) {
13328 switch (Opcode) {
13329 case BSWAP16r_BAD:
13330 case BSWAP32r:
13331 case BSWAP64r:
13332 return true;
13333 }
13334 return false;
13335}
13336
13337bool isPFMIN(unsigned Opcode) {
13338 switch (Opcode) {
13339 case PFMINrm:
13340 case PFMINrr:
13341 return true;
13342 }
13343 return false;
13344}
13345
13346bool isVFPCLASSPD(unsigned Opcode) {
13347 switch (Opcode) {
13348 case VFPCLASSPDZ128rm:
13349 case VFPCLASSPDZ128rmb:
13350 case VFPCLASSPDZ128rmbk:
13351 case VFPCLASSPDZ128rmk:
13352 case VFPCLASSPDZ128rr:
13353 case VFPCLASSPDZ128rrk:
13354 case VFPCLASSPDZ256rm:
13355 case VFPCLASSPDZ256rmb:
13356 case VFPCLASSPDZ256rmbk:
13357 case VFPCLASSPDZ256rmk:
13358 case VFPCLASSPDZ256rr:
13359 case VFPCLASSPDZ256rrk:
13360 case VFPCLASSPDZrm:
13361 case VFPCLASSPDZrmb:
13362 case VFPCLASSPDZrmbk:
13363 case VFPCLASSPDZrmk:
13364 case VFPCLASSPDZrr:
13365 case VFPCLASSPDZrrk:
13366 return true;
13367 }
13368 return false;
13369}
13370
13371bool isVPSHRDVD(unsigned Opcode) {
13372 switch (Opcode) {
13373 case VPSHRDVDZ128m:
13374 case VPSHRDVDZ128mb:
13375 case VPSHRDVDZ128mbk:
13376 case VPSHRDVDZ128mbkz:
13377 case VPSHRDVDZ128mk:
13378 case VPSHRDVDZ128mkz:
13379 case VPSHRDVDZ128r:
13380 case VPSHRDVDZ128rk:
13381 case VPSHRDVDZ128rkz:
13382 case VPSHRDVDZ256m:
13383 case VPSHRDVDZ256mb:
13384 case VPSHRDVDZ256mbk:
13385 case VPSHRDVDZ256mbkz:
13386 case VPSHRDVDZ256mk:
13387 case VPSHRDVDZ256mkz:
13388 case VPSHRDVDZ256r:
13389 case VPSHRDVDZ256rk:
13390 case VPSHRDVDZ256rkz:
13391 case VPSHRDVDZm:
13392 case VPSHRDVDZmb:
13393 case VPSHRDVDZmbk:
13394 case VPSHRDVDZmbkz:
13395 case VPSHRDVDZmk:
13396 case VPSHRDVDZmkz:
13397 case VPSHRDVDZr:
13398 case VPSHRDVDZrk:
13399 case VPSHRDVDZrkz:
13400 return true;
13401 }
13402 return false;
13403}
13404
13405bool isPADDW(unsigned Opcode) {
13406 switch (Opcode) {
13407 case MMX_PADDWrm:
13408 case MMX_PADDWrr:
13409 case PADDWrm:
13410 case PADDWrr:
13411 return true;
13412 }
13413 return false;
13414}
13415
13416bool isCVTSI2SD(unsigned Opcode) {
13417 switch (Opcode) {
13418 case CVTSI2SDrm_Int:
13419 case CVTSI2SDrr_Int:
13420 case CVTSI642SDrm_Int:
13421 case CVTSI642SDrr_Int:
13422 return true;
13423 }
13424 return false;
13425}
13426
13427bool isENQCMD(unsigned Opcode) {
13428 switch (Opcode) {
13429 case ENQCMD16:
13430 case ENQCMD32:
13431 case ENQCMD32_EVEX:
13432 case ENQCMD64:
13433 case ENQCMD64_EVEX:
13434 return true;
13435 }
13436 return false;
13437}
13438
13439bool isXSHA1(unsigned Opcode) {
13440 return Opcode == XSHA1;
13441}
13442
13443bool isVFNMADD132SD(unsigned Opcode) {
13444 switch (Opcode) {
13445 case VFNMADD132SDZm_Int:
13446 case VFNMADD132SDZm_Intk:
13447 case VFNMADD132SDZm_Intkz:
13448 case VFNMADD132SDZr_Int:
13449 case VFNMADD132SDZr_Intk:
13450 case VFNMADD132SDZr_Intkz:
13451 case VFNMADD132SDZrb_Int:
13452 case VFNMADD132SDZrb_Intk:
13453 case VFNMADD132SDZrb_Intkz:
13454 case VFNMADD132SDm_Int:
13455 case VFNMADD132SDr_Int:
13456 return true;
13457 }
13458 return false;
13459}
13460
13461bool isMOVZX(unsigned Opcode) {
13462 switch (Opcode) {
13463 case MOVZX16rm16:
13464 case MOVZX16rm8:
13465 case MOVZX16rr16:
13466 case MOVZX16rr8:
13467 case MOVZX32rm16:
13468 case MOVZX32rm8:
13469 case MOVZX32rr16:
13470 case MOVZX32rr8:
13471 case MOVZX64rm16:
13472 case MOVZX64rm8:
13473 case MOVZX64rr16:
13474 case MOVZX64rr8:
13475 return true;
13476 }
13477 return false;
13478}
13479
13480bool isVFIXUPIMMSD(unsigned Opcode) {
13481 switch (Opcode) {
13482 case VFIXUPIMMSDZrmi:
13483 case VFIXUPIMMSDZrmik:
13484 case VFIXUPIMMSDZrmikz:
13485 case VFIXUPIMMSDZrri:
13486 case VFIXUPIMMSDZrrib:
13487 case VFIXUPIMMSDZrribk:
13488 case VFIXUPIMMSDZrribkz:
13489 case VFIXUPIMMSDZrrik:
13490 case VFIXUPIMMSDZrrikz:
13491 return true;
13492 }
13493 return false;
13494}
13495
13496bool isINVD(unsigned Opcode) {
13497 return Opcode == INVD;
13498}
13499
13500bool isVFIXUPIMMPS(unsigned Opcode) {
13501 switch (Opcode) {
13502 case VFIXUPIMMPSZ128rmbi:
13503 case VFIXUPIMMPSZ128rmbik:
13504 case VFIXUPIMMPSZ128rmbikz:
13505 case VFIXUPIMMPSZ128rmi:
13506 case VFIXUPIMMPSZ128rmik:
13507 case VFIXUPIMMPSZ128rmikz:
13508 case VFIXUPIMMPSZ128rri:
13509 case VFIXUPIMMPSZ128rrik:
13510 case VFIXUPIMMPSZ128rrikz:
13511 case VFIXUPIMMPSZ256rmbi:
13512 case VFIXUPIMMPSZ256rmbik:
13513 case VFIXUPIMMPSZ256rmbikz:
13514 case VFIXUPIMMPSZ256rmi:
13515 case VFIXUPIMMPSZ256rmik:
13516 case VFIXUPIMMPSZ256rmikz:
13517 case VFIXUPIMMPSZ256rri:
13518 case VFIXUPIMMPSZ256rrik:
13519 case VFIXUPIMMPSZ256rrikz:
13520 case VFIXUPIMMPSZrmbi:
13521 case VFIXUPIMMPSZrmbik:
13522 case VFIXUPIMMPSZrmbikz:
13523 case VFIXUPIMMPSZrmi:
13524 case VFIXUPIMMPSZrmik:
13525 case VFIXUPIMMPSZrmikz:
13526 case VFIXUPIMMPSZrri:
13527 case VFIXUPIMMPSZrrib:
13528 case VFIXUPIMMPSZrribk:
13529 case VFIXUPIMMPSZrribkz:
13530 case VFIXUPIMMPSZrrik:
13531 case VFIXUPIMMPSZrrikz:
13532 return true;
13533 }
13534 return false;
13535}
13536
13537bool isMOVDQU(unsigned Opcode) {
13538 switch (Opcode) {
13539 case MOVDQUmr:
13540 case MOVDQUrm:
13541 case MOVDQUrr:
13542 case MOVDQUrr_REV:
13543 return true;
13544 }
13545 return false;
13546}
13547
13548bool isVFPCLASSPS(unsigned Opcode) {
13549 switch (Opcode) {
13550 case VFPCLASSPSZ128rm:
13551 case VFPCLASSPSZ128rmb:
13552 case VFPCLASSPSZ128rmbk:
13553 case VFPCLASSPSZ128rmk:
13554 case VFPCLASSPSZ128rr:
13555 case VFPCLASSPSZ128rrk:
13556 case VFPCLASSPSZ256rm:
13557 case VFPCLASSPSZ256rmb:
13558 case VFPCLASSPSZ256rmbk:
13559 case VFPCLASSPSZ256rmk:
13560 case VFPCLASSPSZ256rr:
13561 case VFPCLASSPSZ256rrk:
13562 case VFPCLASSPSZrm:
13563 case VFPCLASSPSZrmb:
13564 case VFPCLASSPSZrmbk:
13565 case VFPCLASSPSZrmk:
13566 case VFPCLASSPSZrr:
13567 case VFPCLASSPSZrrk:
13568 return true;
13569 }
13570 return false;
13571}
13572
13573bool isMOVSQ(unsigned Opcode) {
13574 return Opcode == MOVSQ;
13575}
13576
13577bool isAESDECWIDE128KL(unsigned Opcode) {
13578 return Opcode == AESDECWIDE128KL;
13579}
13580
13581bool isROUNDSS(unsigned Opcode) {
13582 switch (Opcode) {
13583 case ROUNDSSmi_Int:
13584 case ROUNDSSri_Int:
13585 return true;
13586 }
13587 return false;
13588}
13589
13590bool isVPERMILPS(unsigned Opcode) {
13591 switch (Opcode) {
13592 case VPERMILPSYmi:
13593 case VPERMILPSYri:
13594 case VPERMILPSYrm:
13595 case VPERMILPSYrr:
13596 case VPERMILPSZ128mbi:
13597 case VPERMILPSZ128mbik:
13598 case VPERMILPSZ128mbikz:
13599 case VPERMILPSZ128mi:
13600 case VPERMILPSZ128mik:
13601 case VPERMILPSZ128mikz:
13602 case VPERMILPSZ128ri:
13603 case VPERMILPSZ128rik:
13604 case VPERMILPSZ128rikz:
13605 case VPERMILPSZ128rm:
13606 case VPERMILPSZ128rmb:
13607 case VPERMILPSZ128rmbk:
13608 case VPERMILPSZ128rmbkz:
13609 case VPERMILPSZ128rmk:
13610 case VPERMILPSZ128rmkz:
13611 case VPERMILPSZ128rr:
13612 case VPERMILPSZ128rrk:
13613 case VPERMILPSZ128rrkz:
13614 case VPERMILPSZ256mbi:
13615 case VPERMILPSZ256mbik:
13616 case VPERMILPSZ256mbikz:
13617 case VPERMILPSZ256mi:
13618 case VPERMILPSZ256mik:
13619 case VPERMILPSZ256mikz:
13620 case VPERMILPSZ256ri:
13621 case VPERMILPSZ256rik:
13622 case VPERMILPSZ256rikz:
13623 case VPERMILPSZ256rm:
13624 case VPERMILPSZ256rmb:
13625 case VPERMILPSZ256rmbk:
13626 case VPERMILPSZ256rmbkz:
13627 case VPERMILPSZ256rmk:
13628 case VPERMILPSZ256rmkz:
13629 case VPERMILPSZ256rr:
13630 case VPERMILPSZ256rrk:
13631 case VPERMILPSZ256rrkz:
13632 case VPERMILPSZmbi:
13633 case VPERMILPSZmbik:
13634 case VPERMILPSZmbikz:
13635 case VPERMILPSZmi:
13636 case VPERMILPSZmik:
13637 case VPERMILPSZmikz:
13638 case VPERMILPSZri:
13639 case VPERMILPSZrik:
13640 case VPERMILPSZrikz:
13641 case VPERMILPSZrm:
13642 case VPERMILPSZrmb:
13643 case VPERMILPSZrmbk:
13644 case VPERMILPSZrmbkz:
13645 case VPERMILPSZrmk:
13646 case VPERMILPSZrmkz:
13647 case VPERMILPSZrr:
13648 case VPERMILPSZrrk:
13649 case VPERMILPSZrrkz:
13650 case VPERMILPSmi:
13651 case VPERMILPSri:
13652 case VPERMILPSrm:
13653 case VPERMILPSrr:
13654 return true;
13655 }
13656 return false;
13657}
13658
13659bool isVPMOVW2M(unsigned Opcode) {
13660 switch (Opcode) {
13661 case VPMOVW2MZ128rr:
13662 case VPMOVW2MZ256rr:
13663 case VPMOVW2MZrr:
13664 return true;
13665 }
13666 return false;
13667}
13668
13669bool isVMULSD(unsigned Opcode) {
13670 switch (Opcode) {
13671 case VMULSDZrm_Int:
13672 case VMULSDZrm_Intk:
13673 case VMULSDZrm_Intkz:
13674 case VMULSDZrr_Int:
13675 case VMULSDZrr_Intk:
13676 case VMULSDZrr_Intkz:
13677 case VMULSDZrrb_Int:
13678 case VMULSDZrrb_Intk:
13679 case VMULSDZrrb_Intkz:
13680 case VMULSDrm_Int:
13681 case VMULSDrr_Int:
13682 return true;
13683 }
13684 return false;
13685}
13686
13687bool isVPERMI2W(unsigned Opcode) {
13688 switch (Opcode) {
13689 case VPERMI2WZ128rm:
13690 case VPERMI2WZ128rmk:
13691 case VPERMI2WZ128rmkz:
13692 case VPERMI2WZ128rr:
13693 case VPERMI2WZ128rrk:
13694 case VPERMI2WZ128rrkz:
13695 case VPERMI2WZ256rm:
13696 case VPERMI2WZ256rmk:
13697 case VPERMI2WZ256rmkz:
13698 case VPERMI2WZ256rr:
13699 case VPERMI2WZ256rrk:
13700 case VPERMI2WZ256rrkz:
13701 case VPERMI2WZrm:
13702 case VPERMI2WZrmk:
13703 case VPERMI2WZrmkz:
13704 case VPERMI2WZrr:
13705 case VPERMI2WZrrk:
13706 case VPERMI2WZrrkz:
13707 return true;
13708 }
13709 return false;
13710}
13711
13712bool isVPSHUFB(unsigned Opcode) {
13713 switch (Opcode) {
13714 case VPSHUFBYrm:
13715 case VPSHUFBYrr:
13716 case VPSHUFBZ128rm:
13717 case VPSHUFBZ128rmk:
13718 case VPSHUFBZ128rmkz:
13719 case VPSHUFBZ128rr:
13720 case VPSHUFBZ128rrk:
13721 case VPSHUFBZ128rrkz:
13722 case VPSHUFBZ256rm:
13723 case VPSHUFBZ256rmk:
13724 case VPSHUFBZ256rmkz:
13725 case VPSHUFBZ256rr:
13726 case VPSHUFBZ256rrk:
13727 case VPSHUFBZ256rrkz:
13728 case VPSHUFBZrm:
13729 case VPSHUFBZrmk:
13730 case VPSHUFBZrmkz:
13731 case VPSHUFBZrr:
13732 case VPSHUFBZrrk:
13733 case VPSHUFBZrrkz:
13734 case VPSHUFBrm:
13735 case VPSHUFBrr:
13736 return true;
13737 }
13738 return false;
13739}
13740
13741bool isFST(unsigned Opcode) {
13742 switch (Opcode) {
13743 case ST_F32m:
13744 case ST_F64m:
13745 case ST_Frr:
13746 return true;
13747 }
13748 return false;
13749}
13750
13751bool isVPHSUBW(unsigned Opcode) {
13752 switch (Opcode) {
13753 case VPHSUBWYrm:
13754 case VPHSUBWYrr:
13755 case VPHSUBWrm:
13756 case VPHSUBWrr:
13757 return true;
13758 }
13759 return false;
13760}
13761
13762bool isVREDUCESS(unsigned Opcode) {
13763 switch (Opcode) {
13764 case VREDUCESSZrmi:
13765 case VREDUCESSZrmik:
13766 case VREDUCESSZrmikz:
13767 case VREDUCESSZrri:
13768 case VREDUCESSZrrib:
13769 case VREDUCESSZrribk:
13770 case VREDUCESSZrribkz:
13771 case VREDUCESSZrrik:
13772 case VREDUCESSZrrikz:
13773 return true;
13774 }
13775 return false;
13776}
13777
13778bool isFRNDINT(unsigned Opcode) {
13779 return Opcode == FRNDINT;
13780}
13781
13782bool isSHR(unsigned Opcode) {
13783 switch (Opcode) {
13784 case SHR16m1:
13785 case SHR16m1_EVEX:
13786 case SHR16m1_ND:
13787 case SHR16m1_NF:
13788 case SHR16m1_NF_ND:
13789 case SHR16mCL:
13790 case SHR16mCL_EVEX:
13791 case SHR16mCL_ND:
13792 case SHR16mCL_NF:
13793 case SHR16mCL_NF_ND:
13794 case SHR16mi:
13795 case SHR16mi_EVEX:
13796 case SHR16mi_ND:
13797 case SHR16mi_NF:
13798 case SHR16mi_NF_ND:
13799 case SHR16r1:
13800 case SHR16r1_EVEX:
13801 case SHR16r1_ND:
13802 case SHR16r1_NF:
13803 case SHR16r1_NF_ND:
13804 case SHR16rCL:
13805 case SHR16rCL_EVEX:
13806 case SHR16rCL_ND:
13807 case SHR16rCL_NF:
13808 case SHR16rCL_NF_ND:
13809 case SHR16ri:
13810 case SHR16ri_EVEX:
13811 case SHR16ri_ND:
13812 case SHR16ri_NF:
13813 case SHR16ri_NF_ND:
13814 case SHR32m1:
13815 case SHR32m1_EVEX:
13816 case SHR32m1_ND:
13817 case SHR32m1_NF:
13818 case SHR32m1_NF_ND:
13819 case SHR32mCL:
13820 case SHR32mCL_EVEX:
13821 case SHR32mCL_ND:
13822 case SHR32mCL_NF:
13823 case SHR32mCL_NF_ND:
13824 case SHR32mi:
13825 case SHR32mi_EVEX:
13826 case SHR32mi_ND:
13827 case SHR32mi_NF:
13828 case SHR32mi_NF_ND:
13829 case SHR32r1:
13830 case SHR32r1_EVEX:
13831 case SHR32r1_ND:
13832 case SHR32r1_NF:
13833 case SHR32r1_NF_ND:
13834 case SHR32rCL:
13835 case SHR32rCL_EVEX:
13836 case SHR32rCL_ND:
13837 case SHR32rCL_NF:
13838 case SHR32rCL_NF_ND:
13839 case SHR32ri:
13840 case SHR32ri_EVEX:
13841 case SHR32ri_ND:
13842 case SHR32ri_NF:
13843 case SHR32ri_NF_ND:
13844 case SHR64m1:
13845 case SHR64m1_EVEX:
13846 case SHR64m1_ND:
13847 case SHR64m1_NF:
13848 case SHR64m1_NF_ND:
13849 case SHR64mCL:
13850 case SHR64mCL_EVEX:
13851 case SHR64mCL_ND:
13852 case SHR64mCL_NF:
13853 case SHR64mCL_NF_ND:
13854 case SHR64mi:
13855 case SHR64mi_EVEX:
13856 case SHR64mi_ND:
13857 case SHR64mi_NF:
13858 case SHR64mi_NF_ND:
13859 case SHR64r1:
13860 case SHR64r1_EVEX:
13861 case SHR64r1_ND:
13862 case SHR64r1_NF:
13863 case SHR64r1_NF_ND:
13864 case SHR64rCL:
13865 case SHR64rCL_EVEX:
13866 case SHR64rCL_ND:
13867 case SHR64rCL_NF:
13868 case SHR64rCL_NF_ND:
13869 case SHR64ri:
13870 case SHR64ri_EVEX:
13871 case SHR64ri_ND:
13872 case SHR64ri_NF:
13873 case SHR64ri_NF_ND:
13874 case SHR8m1:
13875 case SHR8m1_EVEX:
13876 case SHR8m1_ND:
13877 case SHR8m1_NF:
13878 case SHR8m1_NF_ND:
13879 case SHR8mCL:
13880 case SHR8mCL_EVEX:
13881 case SHR8mCL_ND:
13882 case SHR8mCL_NF:
13883 case SHR8mCL_NF_ND:
13884 case SHR8mi:
13885 case SHR8mi_EVEX:
13886 case SHR8mi_ND:
13887 case SHR8mi_NF:
13888 case SHR8mi_NF_ND:
13889 case SHR8r1:
13890 case SHR8r1_EVEX:
13891 case SHR8r1_ND:
13892 case SHR8r1_NF:
13893 case SHR8r1_NF_ND:
13894 case SHR8rCL:
13895 case SHR8rCL_EVEX:
13896 case SHR8rCL_ND:
13897 case SHR8rCL_NF:
13898 case SHR8rCL_NF_ND:
13899 case SHR8ri:
13900 case SHR8ri_EVEX:
13901 case SHR8ri_ND:
13902 case SHR8ri_NF:
13903 case SHR8ri_NF_ND:
13904 return true;
13905 }
13906 return false;
13907}
13908
13909bool isLOOPNE(unsigned Opcode) {
13910 return Opcode == LOOPNE;
13911}
13912
13913bool isVCVTTPH2UQQ(unsigned Opcode) {
13914 switch (Opcode) {
13915 case VCVTTPH2UQQZ128rm:
13916 case VCVTTPH2UQQZ128rmb:
13917 case VCVTTPH2UQQZ128rmbk:
13918 case VCVTTPH2UQQZ128rmbkz:
13919 case VCVTTPH2UQQZ128rmk:
13920 case VCVTTPH2UQQZ128rmkz:
13921 case VCVTTPH2UQQZ128rr:
13922 case VCVTTPH2UQQZ128rrk:
13923 case VCVTTPH2UQQZ128rrkz:
13924 case VCVTTPH2UQQZ256rm:
13925 case VCVTTPH2UQQZ256rmb:
13926 case VCVTTPH2UQQZ256rmbk:
13927 case VCVTTPH2UQQZ256rmbkz:
13928 case VCVTTPH2UQQZ256rmk:
13929 case VCVTTPH2UQQZ256rmkz:
13930 case VCVTTPH2UQQZ256rr:
13931 case VCVTTPH2UQQZ256rrk:
13932 case VCVTTPH2UQQZ256rrkz:
13933 case VCVTTPH2UQQZrm:
13934 case VCVTTPH2UQQZrmb:
13935 case VCVTTPH2UQQZrmbk:
13936 case VCVTTPH2UQQZrmbkz:
13937 case VCVTTPH2UQQZrmk:
13938 case VCVTTPH2UQQZrmkz:
13939 case VCVTTPH2UQQZrr:
13940 case VCVTTPH2UQQZrrb:
13941 case VCVTTPH2UQQZrrbk:
13942 case VCVTTPH2UQQZrrbkz:
13943 case VCVTTPH2UQQZrrk:
13944 case VCVTTPH2UQQZrrkz:
13945 return true;
13946 }
13947 return false;
13948}
13949
13950bool isSHA1NEXTE(unsigned Opcode) {
13951 switch (Opcode) {
13952 case SHA1NEXTErm:
13953 case SHA1NEXTErr:
13954 return true;
13955 }
13956 return false;
13957}
13958
13959bool isVFMADD132SD(unsigned Opcode) {
13960 switch (Opcode) {
13961 case VFMADD132SDZm_Int:
13962 case VFMADD132SDZm_Intk:
13963 case VFMADD132SDZm_Intkz:
13964 case VFMADD132SDZr_Int:
13965 case VFMADD132SDZr_Intk:
13966 case VFMADD132SDZr_Intkz:
13967 case VFMADD132SDZrb_Int:
13968 case VFMADD132SDZrb_Intk:
13969 case VFMADD132SDZrb_Intkz:
13970 case VFMADD132SDm_Int:
13971 case VFMADD132SDr_Int:
13972 return true;
13973 }
13974 return false;
13975}
13976
13977bool isPSRAW(unsigned Opcode) {
13978 switch (Opcode) {
13979 case MMX_PSRAWri:
13980 case MMX_PSRAWrm:
13981 case MMX_PSRAWrr:
13982 case PSRAWri:
13983 case PSRAWrm:
13984 case PSRAWrr:
13985 return true;
13986 }
13987 return false;
13988}
13989
13990bool isVPBROADCASTQ(unsigned Opcode) {
13991 switch (Opcode) {
13992 case VPBROADCASTQYrm:
13993 case VPBROADCASTQYrr:
13994 case VPBROADCASTQZ128rm:
13995 case VPBROADCASTQZ128rmk:
13996 case VPBROADCASTQZ128rmkz:
13997 case VPBROADCASTQZ128rr:
13998 case VPBROADCASTQZ128rrk:
13999 case VPBROADCASTQZ128rrkz:
14000 case VPBROADCASTQZ256rm:
14001 case VPBROADCASTQZ256rmk:
14002 case VPBROADCASTQZ256rmkz:
14003 case VPBROADCASTQZ256rr:
14004 case VPBROADCASTQZ256rrk:
14005 case VPBROADCASTQZ256rrkz:
14006 case VPBROADCASTQZrm:
14007 case VPBROADCASTQZrmk:
14008 case VPBROADCASTQZrmkz:
14009 case VPBROADCASTQZrr:
14010 case VPBROADCASTQZrrk:
14011 case VPBROADCASTQZrrkz:
14012 case VPBROADCASTQrZ128rr:
14013 case VPBROADCASTQrZ128rrk:
14014 case VPBROADCASTQrZ128rrkz:
14015 case VPBROADCASTQrZ256rr:
14016 case VPBROADCASTQrZ256rrk:
14017 case VPBROADCASTQrZ256rrkz:
14018 case VPBROADCASTQrZrr:
14019 case VPBROADCASTQrZrrk:
14020 case VPBROADCASTQrZrrkz:
14021 case VPBROADCASTQrm:
14022 case VPBROADCASTQrr:
14023 return true;
14024 }
14025 return false;
14026}
14027
14028bool isCLC(unsigned Opcode) {
14029 return Opcode == CLC;
14030}
14031
14032bool isPOPAW(unsigned Opcode) {
14033 return Opcode == POPA16;
14034}
14035
14036bool isTCMMIMFP16PS(unsigned Opcode) {
14037 return Opcode == TCMMIMFP16PS;
14038}
14039
14040bool isVCVTTPS2UQQ(unsigned Opcode) {
14041 switch (Opcode) {
14042 case VCVTTPS2UQQZ128rm:
14043 case VCVTTPS2UQQZ128rmb:
14044 case VCVTTPS2UQQZ128rmbk:
14045 case VCVTTPS2UQQZ128rmbkz:
14046 case VCVTTPS2UQQZ128rmk:
14047 case VCVTTPS2UQQZ128rmkz:
14048 case VCVTTPS2UQQZ128rr:
14049 case VCVTTPS2UQQZ128rrk:
14050 case VCVTTPS2UQQZ128rrkz:
14051 case VCVTTPS2UQQZ256rm:
14052 case VCVTTPS2UQQZ256rmb:
14053 case VCVTTPS2UQQZ256rmbk:
14054 case VCVTTPS2UQQZ256rmbkz:
14055 case VCVTTPS2UQQZ256rmk:
14056 case VCVTTPS2UQQZ256rmkz:
14057 case VCVTTPS2UQQZ256rr:
14058 case VCVTTPS2UQQZ256rrk:
14059 case VCVTTPS2UQQZ256rrkz:
14060 case VCVTTPS2UQQZrm:
14061 case VCVTTPS2UQQZrmb:
14062 case VCVTTPS2UQQZrmbk:
14063 case VCVTTPS2UQQZrmbkz:
14064 case VCVTTPS2UQQZrmk:
14065 case VCVTTPS2UQQZrmkz:
14066 case VCVTTPS2UQQZrr:
14067 case VCVTTPS2UQQZrrb:
14068 case VCVTTPS2UQQZrrbk:
14069 case VCVTTPS2UQQZrrbkz:
14070 case VCVTTPS2UQQZrrk:
14071 case VCVTTPS2UQQZrrkz:
14072 return true;
14073 }
14074 return false;
14075}
14076
14077bool isVCVTQQ2PH(unsigned Opcode) {
14078 switch (Opcode) {
14079 case VCVTQQ2PHZ128rm:
14080 case VCVTQQ2PHZ128rmb:
14081 case VCVTQQ2PHZ128rmbk:
14082 case VCVTQQ2PHZ128rmbkz:
14083 case VCVTQQ2PHZ128rmk:
14084 case VCVTQQ2PHZ128rmkz:
14085 case VCVTQQ2PHZ128rr:
14086 case VCVTQQ2PHZ128rrk:
14087 case VCVTQQ2PHZ128rrkz:
14088 case VCVTQQ2PHZ256rm:
14089 case VCVTQQ2PHZ256rmb:
14090 case VCVTQQ2PHZ256rmbk:
14091 case VCVTQQ2PHZ256rmbkz:
14092 case VCVTQQ2PHZ256rmk:
14093 case VCVTQQ2PHZ256rmkz:
14094 case VCVTQQ2PHZ256rr:
14095 case VCVTQQ2PHZ256rrk:
14096 case VCVTQQ2PHZ256rrkz:
14097 case VCVTQQ2PHZrm:
14098 case VCVTQQ2PHZrmb:
14099 case VCVTQQ2PHZrmbk:
14100 case VCVTQQ2PHZrmbkz:
14101 case VCVTQQ2PHZrmk:
14102 case VCVTQQ2PHZrmkz:
14103 case VCVTQQ2PHZrr:
14104 case VCVTQQ2PHZrrb:
14105 case VCVTQQ2PHZrrbk:
14106 case VCVTQQ2PHZrrbkz:
14107 case VCVTQQ2PHZrrk:
14108 case VCVTQQ2PHZrrkz:
14109 return true;
14110 }
14111 return false;
14112}
14113
14114bool isVMOVUPD(unsigned Opcode) {
14115 switch (Opcode) {
14116 case VMOVUPDYmr:
14117 case VMOVUPDYrm:
14118 case VMOVUPDYrr:
14119 case VMOVUPDYrr_REV:
14120 case VMOVUPDZ128mr:
14121 case VMOVUPDZ128mrk:
14122 case VMOVUPDZ128rm:
14123 case VMOVUPDZ128rmk:
14124 case VMOVUPDZ128rmkz:
14125 case VMOVUPDZ128rr:
14126 case VMOVUPDZ128rr_REV:
14127 case VMOVUPDZ128rrk:
14128 case VMOVUPDZ128rrk_REV:
14129 case VMOVUPDZ128rrkz:
14130 case VMOVUPDZ128rrkz_REV:
14131 case VMOVUPDZ256mr:
14132 case VMOVUPDZ256mrk:
14133 case VMOVUPDZ256rm:
14134 case VMOVUPDZ256rmk:
14135 case VMOVUPDZ256rmkz:
14136 case VMOVUPDZ256rr:
14137 case VMOVUPDZ256rr_REV:
14138 case VMOVUPDZ256rrk:
14139 case VMOVUPDZ256rrk_REV:
14140 case VMOVUPDZ256rrkz:
14141 case VMOVUPDZ256rrkz_REV:
14142 case VMOVUPDZmr:
14143 case VMOVUPDZmrk:
14144 case VMOVUPDZrm:
14145 case VMOVUPDZrmk:
14146 case VMOVUPDZrmkz:
14147 case VMOVUPDZrr:
14148 case VMOVUPDZrr_REV:
14149 case VMOVUPDZrrk:
14150 case VMOVUPDZrrk_REV:
14151 case VMOVUPDZrrkz:
14152 case VMOVUPDZrrkz_REV:
14153 case VMOVUPDmr:
14154 case VMOVUPDrm:
14155 case VMOVUPDrr:
14156 case VMOVUPDrr_REV:
14157 return true;
14158 }
14159 return false;
14160}
14161
14162bool isFPTAN(unsigned Opcode) {
14163 return Opcode == FPTAN;
14164}
14165
14166bool isVMASKMOVPD(unsigned Opcode) {
14167 switch (Opcode) {
14168 case VMASKMOVPDYmr:
14169 case VMASKMOVPDYrm:
14170 case VMASKMOVPDmr:
14171 case VMASKMOVPDrm:
14172 return true;
14173 }
14174 return false;
14175}
14176
14177bool isVMOVLHPS(unsigned Opcode) {
14178 switch (Opcode) {
14179 case VMOVLHPSZrr:
14180 case VMOVLHPSrr:
14181 return true;
14182 }
14183 return false;
14184}
14185
14186bool isAESKEYGENASSIST(unsigned Opcode) {
14187 switch (Opcode) {
14188 case AESKEYGENASSIST128rm:
14189 case AESKEYGENASSIST128rr:
14190 return true;
14191 }
14192 return false;
14193}
14194
14195bool isXSAVEOPT64(unsigned Opcode) {
14196 return Opcode == XSAVEOPT64;
14197}
14198
14199bool isXSAVEC(unsigned Opcode) {
14200 return Opcode == XSAVEC;
14201}
14202
14203bool isVPLZCNTQ(unsigned Opcode) {
14204 switch (Opcode) {
14205 case VPLZCNTQZ128rm:
14206 case VPLZCNTQZ128rmb:
14207 case VPLZCNTQZ128rmbk:
14208 case VPLZCNTQZ128rmbkz:
14209 case VPLZCNTQZ128rmk:
14210 case VPLZCNTQZ128rmkz:
14211 case VPLZCNTQZ128rr:
14212 case VPLZCNTQZ128rrk:
14213 case VPLZCNTQZ128rrkz:
14214 case VPLZCNTQZ256rm:
14215 case VPLZCNTQZ256rmb:
14216 case VPLZCNTQZ256rmbk:
14217 case VPLZCNTQZ256rmbkz:
14218 case VPLZCNTQZ256rmk:
14219 case VPLZCNTQZ256rmkz:
14220 case VPLZCNTQZ256rr:
14221 case VPLZCNTQZ256rrk:
14222 case VPLZCNTQZ256rrkz:
14223 case VPLZCNTQZrm:
14224 case VPLZCNTQZrmb:
14225 case VPLZCNTQZrmbk:
14226 case VPLZCNTQZrmbkz:
14227 case VPLZCNTQZrmk:
14228 case VPLZCNTQZrmkz:
14229 case VPLZCNTQZrr:
14230 case VPLZCNTQZrrk:
14231 case VPLZCNTQZrrkz:
14232 return true;
14233 }
14234 return false;
14235}
14236
14237bool isVPSUBW(unsigned Opcode) {
14238 switch (Opcode) {
14239 case VPSUBWYrm:
14240 case VPSUBWYrr:
14241 case VPSUBWZ128rm:
14242 case VPSUBWZ128rmk:
14243 case VPSUBWZ128rmkz:
14244 case VPSUBWZ128rr:
14245 case VPSUBWZ128rrk:
14246 case VPSUBWZ128rrkz:
14247 case VPSUBWZ256rm:
14248 case VPSUBWZ256rmk:
14249 case VPSUBWZ256rmkz:
14250 case VPSUBWZ256rr:
14251 case VPSUBWZ256rrk:
14252 case VPSUBWZ256rrkz:
14253 case VPSUBWZrm:
14254 case VPSUBWZrmk:
14255 case VPSUBWZrmkz:
14256 case VPSUBWZrr:
14257 case VPSUBWZrrk:
14258 case VPSUBWZrrkz:
14259 case VPSUBWrm:
14260 case VPSUBWrr:
14261 return true;
14262 }
14263 return false;
14264}
14265
14266bool isCMPCCXADD(unsigned Opcode) {
14267 switch (Opcode) {
14268 case CMPCCXADDmr32:
14269 case CMPCCXADDmr32_EVEX:
14270 case CMPCCXADDmr64:
14271 case CMPCCXADDmr64_EVEX:
14272 return true;
14273 }
14274 return false;
14275}
14276
14277bool isVFMSUBADD213PH(unsigned Opcode) {
14278 switch (Opcode) {
14279 case VFMSUBADD213PHZ128m:
14280 case VFMSUBADD213PHZ128mb:
14281 case VFMSUBADD213PHZ128mbk:
14282 case VFMSUBADD213PHZ128mbkz:
14283 case VFMSUBADD213PHZ128mk:
14284 case VFMSUBADD213PHZ128mkz:
14285 case VFMSUBADD213PHZ128r:
14286 case VFMSUBADD213PHZ128rk:
14287 case VFMSUBADD213PHZ128rkz:
14288 case VFMSUBADD213PHZ256m:
14289 case VFMSUBADD213PHZ256mb:
14290 case VFMSUBADD213PHZ256mbk:
14291 case VFMSUBADD213PHZ256mbkz:
14292 case VFMSUBADD213PHZ256mk:
14293 case VFMSUBADD213PHZ256mkz:
14294 case VFMSUBADD213PHZ256r:
14295 case VFMSUBADD213PHZ256rk:
14296 case VFMSUBADD213PHZ256rkz:
14297 case VFMSUBADD213PHZm:
14298 case VFMSUBADD213PHZmb:
14299 case VFMSUBADD213PHZmbk:
14300 case VFMSUBADD213PHZmbkz:
14301 case VFMSUBADD213PHZmk:
14302 case VFMSUBADD213PHZmkz:
14303 case VFMSUBADD213PHZr:
14304 case VFMSUBADD213PHZrb:
14305 case VFMSUBADD213PHZrbk:
14306 case VFMSUBADD213PHZrbkz:
14307 case VFMSUBADD213PHZrk:
14308 case VFMSUBADD213PHZrkz:
14309 return true;
14310 }
14311 return false;
14312}
14313
14314bool isVFMADDSUBPD(unsigned Opcode) {
14315 switch (Opcode) {
14316 case VFMADDSUBPD4Ymr:
14317 case VFMADDSUBPD4Yrm:
14318 case VFMADDSUBPD4Yrr:
14319 case VFMADDSUBPD4Yrr_REV:
14320 case VFMADDSUBPD4mr:
14321 case VFMADDSUBPD4rm:
14322 case VFMADDSUBPD4rr:
14323 case VFMADDSUBPD4rr_REV:
14324 return true;
14325 }
14326 return false;
14327}
14328
14329bool isVPMINSW(unsigned Opcode) {
14330 switch (Opcode) {
14331 case VPMINSWYrm:
14332 case VPMINSWYrr:
14333 case VPMINSWZ128rm:
14334 case VPMINSWZ128rmk:
14335 case VPMINSWZ128rmkz:
14336 case VPMINSWZ128rr:
14337 case VPMINSWZ128rrk:
14338 case VPMINSWZ128rrkz:
14339 case VPMINSWZ256rm:
14340 case VPMINSWZ256rmk:
14341 case VPMINSWZ256rmkz:
14342 case VPMINSWZ256rr:
14343 case VPMINSWZ256rrk:
14344 case VPMINSWZ256rrkz:
14345 case VPMINSWZrm:
14346 case VPMINSWZrmk:
14347 case VPMINSWZrmkz:
14348 case VPMINSWZrr:
14349 case VPMINSWZrrk:
14350 case VPMINSWZrrkz:
14351 case VPMINSWrm:
14352 case VPMINSWrr:
14353 return true;
14354 }
14355 return false;
14356}
14357
14358bool isVFNMSUB132PS(unsigned Opcode) {
14359 switch (Opcode) {
14360 case VFNMSUB132PSYm:
14361 case VFNMSUB132PSYr:
14362 case VFNMSUB132PSZ128m:
14363 case VFNMSUB132PSZ128mb:
14364 case VFNMSUB132PSZ128mbk:
14365 case VFNMSUB132PSZ128mbkz:
14366 case VFNMSUB132PSZ128mk:
14367 case VFNMSUB132PSZ128mkz:
14368 case VFNMSUB132PSZ128r:
14369 case VFNMSUB132PSZ128rk:
14370 case VFNMSUB132PSZ128rkz:
14371 case VFNMSUB132PSZ256m:
14372 case VFNMSUB132PSZ256mb:
14373 case VFNMSUB132PSZ256mbk:
14374 case VFNMSUB132PSZ256mbkz:
14375 case VFNMSUB132PSZ256mk:
14376 case VFNMSUB132PSZ256mkz:
14377 case VFNMSUB132PSZ256r:
14378 case VFNMSUB132PSZ256rk:
14379 case VFNMSUB132PSZ256rkz:
14380 case VFNMSUB132PSZm:
14381 case VFNMSUB132PSZmb:
14382 case VFNMSUB132PSZmbk:
14383 case VFNMSUB132PSZmbkz:
14384 case VFNMSUB132PSZmk:
14385 case VFNMSUB132PSZmkz:
14386 case VFNMSUB132PSZr:
14387 case VFNMSUB132PSZrb:
14388 case VFNMSUB132PSZrbk:
14389 case VFNMSUB132PSZrbkz:
14390 case VFNMSUB132PSZrk:
14391 case VFNMSUB132PSZrkz:
14392 case VFNMSUB132PSm:
14393 case VFNMSUB132PSr:
14394 return true;
14395 }
14396 return false;
14397}
14398
14399bool isVMOVAPS(unsigned Opcode) {
14400 switch (Opcode) {
14401 case VMOVAPSYmr:
14402 case VMOVAPSYrm:
14403 case VMOVAPSYrr:
14404 case VMOVAPSYrr_REV:
14405 case VMOVAPSZ128mr:
14406 case VMOVAPSZ128mrk:
14407 case VMOVAPSZ128rm:
14408 case VMOVAPSZ128rmk:
14409 case VMOVAPSZ128rmkz:
14410 case VMOVAPSZ128rr:
14411 case VMOVAPSZ128rr_REV:
14412 case VMOVAPSZ128rrk:
14413 case VMOVAPSZ128rrk_REV:
14414 case VMOVAPSZ128rrkz:
14415 case VMOVAPSZ128rrkz_REV:
14416 case VMOVAPSZ256mr:
14417 case VMOVAPSZ256mrk:
14418 case VMOVAPSZ256rm:
14419 case VMOVAPSZ256rmk:
14420 case VMOVAPSZ256rmkz:
14421 case VMOVAPSZ256rr:
14422 case VMOVAPSZ256rr_REV:
14423 case VMOVAPSZ256rrk:
14424 case VMOVAPSZ256rrk_REV:
14425 case VMOVAPSZ256rrkz:
14426 case VMOVAPSZ256rrkz_REV:
14427 case VMOVAPSZmr:
14428 case VMOVAPSZmrk:
14429 case VMOVAPSZrm:
14430 case VMOVAPSZrmk:
14431 case VMOVAPSZrmkz:
14432 case VMOVAPSZrr:
14433 case VMOVAPSZrr_REV:
14434 case VMOVAPSZrrk:
14435 case VMOVAPSZrrk_REV:
14436 case VMOVAPSZrrkz:
14437 case VMOVAPSZrrkz_REV:
14438 case VMOVAPSmr:
14439 case VMOVAPSrm:
14440 case VMOVAPSrr:
14441 case VMOVAPSrr_REV:
14442 return true;
14443 }
14444 return false;
14445}
14446
14447bool isVPEXTRQ(unsigned Opcode) {
14448 switch (Opcode) {
14449 case VPEXTRQZmr:
14450 case VPEXTRQZrr:
14451 case VPEXTRQmr:
14452 case VPEXTRQrr:
14453 return true;
14454 }
14455 return false;
14456}
14457
14458bool isVSCALEFSH(unsigned Opcode) {
14459 switch (Opcode) {
14460 case VSCALEFSHZrm:
14461 case VSCALEFSHZrmk:
14462 case VSCALEFSHZrmkz:
14463 case VSCALEFSHZrr:
14464 case VSCALEFSHZrrb_Int:
14465 case VSCALEFSHZrrb_Intk:
14466 case VSCALEFSHZrrb_Intkz:
14467 case VSCALEFSHZrrk:
14468 case VSCALEFSHZrrkz:
14469 return true;
14470 }
14471 return false;
14472}
14473
14474bool isVCVTPD2PS(unsigned Opcode) {
14475 switch (Opcode) {
14476 case VCVTPD2PSYrm:
14477 case VCVTPD2PSYrr:
14478 case VCVTPD2PSZ128rm:
14479 case VCVTPD2PSZ128rmb:
14480 case VCVTPD2PSZ128rmbk:
14481 case VCVTPD2PSZ128rmbkz:
14482 case VCVTPD2PSZ128rmk:
14483 case VCVTPD2PSZ128rmkz:
14484 case VCVTPD2PSZ128rr:
14485 case VCVTPD2PSZ128rrk:
14486 case VCVTPD2PSZ128rrkz:
14487 case VCVTPD2PSZ256rm:
14488 case VCVTPD2PSZ256rmb:
14489 case VCVTPD2PSZ256rmbk:
14490 case VCVTPD2PSZ256rmbkz:
14491 case VCVTPD2PSZ256rmk:
14492 case VCVTPD2PSZ256rmkz:
14493 case VCVTPD2PSZ256rr:
14494 case VCVTPD2PSZ256rrk:
14495 case VCVTPD2PSZ256rrkz:
14496 case VCVTPD2PSZrm:
14497 case VCVTPD2PSZrmb:
14498 case VCVTPD2PSZrmbk:
14499 case VCVTPD2PSZrmbkz:
14500 case VCVTPD2PSZrmk:
14501 case VCVTPD2PSZrmkz:
14502 case VCVTPD2PSZrr:
14503 case VCVTPD2PSZrrb:
14504 case VCVTPD2PSZrrbk:
14505 case VCVTPD2PSZrrbkz:
14506 case VCVTPD2PSZrrk:
14507 case VCVTPD2PSZrrkz:
14508 case VCVTPD2PSrm:
14509 case VCVTPD2PSrr:
14510 return true;
14511 }
14512 return false;
14513}
14514
14515bool isCLGI(unsigned Opcode) {
14516 return Opcode == CLGI;
14517}
14518
14519bool isVAESDEC(unsigned Opcode) {
14520 switch (Opcode) {
14521 case VAESDECYrm:
14522 case VAESDECYrr:
14523 case VAESDECZ128rm:
14524 case VAESDECZ128rr:
14525 case VAESDECZ256rm:
14526 case VAESDECZ256rr:
14527 case VAESDECZrm:
14528 case VAESDECZrr:
14529 case VAESDECrm:
14530 case VAESDECrr:
14531 return true;
14532 }
14533 return false;
14534}
14535
14536bool isPFMUL(unsigned Opcode) {
14537 switch (Opcode) {
14538 case PFMULrm:
14539 case PFMULrr:
14540 return true;
14541 }
14542 return false;
14543}
14544
14545bool isMOVDIRI(unsigned Opcode) {
14546 switch (Opcode) {
14547 case MOVDIRI32:
14548 case MOVDIRI32_EVEX:
14549 case MOVDIRI64:
14550 case MOVDIRI64_EVEX:
14551 return true;
14552 }
14553 return false;
14554}
14555
14556bool isSHUFPS(unsigned Opcode) {
14557 switch (Opcode) {
14558 case SHUFPSrmi:
14559 case SHUFPSrri:
14560 return true;
14561 }
14562 return false;
14563}
14564
14565bool isVFNMSUB231SS(unsigned Opcode) {
14566 switch (Opcode) {
14567 case VFNMSUB231SSZm_Int:
14568 case VFNMSUB231SSZm_Intk:
14569 case VFNMSUB231SSZm_Intkz:
14570 case VFNMSUB231SSZr_Int:
14571 case VFNMSUB231SSZr_Intk:
14572 case VFNMSUB231SSZr_Intkz:
14573 case VFNMSUB231SSZrb_Int:
14574 case VFNMSUB231SSZrb_Intk:
14575 case VFNMSUB231SSZrb_Intkz:
14576 case VFNMSUB231SSm_Int:
14577 case VFNMSUB231SSr_Int:
14578 return true;
14579 }
14580 return false;
14581}
14582
14583bool isVMWRITE(unsigned Opcode) {
14584 switch (Opcode) {
14585 case VMWRITE32rm:
14586 case VMWRITE32rr:
14587 case VMWRITE64rm:
14588 case VMWRITE64rr:
14589 return true;
14590 }
14591 return false;
14592}
14593
14594bool isVINSERTF128(unsigned Opcode) {
14595 switch (Opcode) {
14596 case VINSERTF128rm:
14597 case VINSERTF128rr:
14598 return true;
14599 }
14600 return false;
14601}
14602
14603bool isFISUBR(unsigned Opcode) {
14604 switch (Opcode) {
14605 case SUBR_FI16m:
14606 case SUBR_FI32m:
14607 return true;
14608 }
14609 return false;
14610}
14611
14612bool isVINSERTI32X4(unsigned Opcode) {
14613 switch (Opcode) {
14614 case VINSERTI32x4Z256rm:
14615 case VINSERTI32x4Z256rmk:
14616 case VINSERTI32x4Z256rmkz:
14617 case VINSERTI32x4Z256rr:
14618 case VINSERTI32x4Z256rrk:
14619 case VINSERTI32x4Z256rrkz:
14620 case VINSERTI32x4Zrm:
14621 case VINSERTI32x4Zrmk:
14622 case VINSERTI32x4Zrmkz:
14623 case VINSERTI32x4Zrr:
14624 case VINSERTI32x4Zrrk:
14625 case VINSERTI32x4Zrrkz:
14626 return true;
14627 }
14628 return false;
14629}
14630
14631bool isVPSLLDQ(unsigned Opcode) {
14632 switch (Opcode) {
14633 case VPSLLDQYri:
14634 case VPSLLDQZ128mi:
14635 case VPSLLDQZ128ri:
14636 case VPSLLDQZ256mi:
14637 case VPSLLDQZ256ri:
14638 case VPSLLDQZmi:
14639 case VPSLLDQZri:
14640 case VPSLLDQri:
14641 return true;
14642 }
14643 return false;
14644}
14645
14646bool isPOPCNT(unsigned Opcode) {
14647 switch (Opcode) {
14648 case POPCNT16rm:
14649 case POPCNT16rm_EVEX:
14650 case POPCNT16rm_NF:
14651 case POPCNT16rr:
14652 case POPCNT16rr_EVEX:
14653 case POPCNT16rr_NF:
14654 case POPCNT32rm:
14655 case POPCNT32rm_EVEX:
14656 case POPCNT32rm_NF:
14657 case POPCNT32rr:
14658 case POPCNT32rr_EVEX:
14659 case POPCNT32rr_NF:
14660 case POPCNT64rm:
14661 case POPCNT64rm_EVEX:
14662 case POPCNT64rm_NF:
14663 case POPCNT64rr:
14664 case POPCNT64rr_EVEX:
14665 case POPCNT64rr_NF:
14666 return true;
14667 }
14668 return false;
14669}
14670
14671bool isVXORPD(unsigned Opcode) {
14672 switch (Opcode) {
14673 case VXORPDYrm:
14674 case VXORPDYrr:
14675 case VXORPDZ128rm:
14676 case VXORPDZ128rmb:
14677 case VXORPDZ128rmbk:
14678 case VXORPDZ128rmbkz:
14679 case VXORPDZ128rmk:
14680 case VXORPDZ128rmkz:
14681 case VXORPDZ128rr:
14682 case VXORPDZ128rrk:
14683 case VXORPDZ128rrkz:
14684 case VXORPDZ256rm:
14685 case VXORPDZ256rmb:
14686 case VXORPDZ256rmbk:
14687 case VXORPDZ256rmbkz:
14688 case VXORPDZ256rmk:
14689 case VXORPDZ256rmkz:
14690 case VXORPDZ256rr:
14691 case VXORPDZ256rrk:
14692 case VXORPDZ256rrkz:
14693 case VXORPDZrm:
14694 case VXORPDZrmb:
14695 case VXORPDZrmbk:
14696 case VXORPDZrmbkz:
14697 case VXORPDZrmk:
14698 case VXORPDZrmkz:
14699 case VXORPDZrr:
14700 case VXORPDZrrk:
14701 case VXORPDZrrkz:
14702 case VXORPDrm:
14703 case VXORPDrr:
14704 return true;
14705 }
14706 return false;
14707}
14708
14709bool isXLATB(unsigned Opcode) {
14710 return Opcode == XLAT;
14711}
14712
14713bool isDIV(unsigned Opcode) {
14714 switch (Opcode) {
14715 case DIV16m:
14716 case DIV16m_EVEX:
14717 case DIV16m_NF:
14718 case DIV16r:
14719 case DIV16r_EVEX:
14720 case DIV16r_NF:
14721 case DIV32m:
14722 case DIV32m_EVEX:
14723 case DIV32m_NF:
14724 case DIV32r:
14725 case DIV32r_EVEX:
14726 case DIV32r_NF:
14727 case DIV64m:
14728 case DIV64m_EVEX:
14729 case DIV64m_NF:
14730 case DIV64r:
14731 case DIV64r_EVEX:
14732 case DIV64r_NF:
14733 case DIV8m:
14734 case DIV8m_EVEX:
14735 case DIV8m_NF:
14736 case DIV8r:
14737 case DIV8r_EVEX:
14738 case DIV8r_NF:
14739 return true;
14740 }
14741 return false;
14742}
14743
14744bool isVPSHLDVQ(unsigned Opcode) {
14745 switch (Opcode) {
14746 case VPSHLDVQZ128m:
14747 case VPSHLDVQZ128mb:
14748 case VPSHLDVQZ128mbk:
14749 case VPSHLDVQZ128mbkz:
14750 case VPSHLDVQZ128mk:
14751 case VPSHLDVQZ128mkz:
14752 case VPSHLDVQZ128r:
14753 case VPSHLDVQZ128rk:
14754 case VPSHLDVQZ128rkz:
14755 case VPSHLDVQZ256m:
14756 case VPSHLDVQZ256mb:
14757 case VPSHLDVQZ256mbk:
14758 case VPSHLDVQZ256mbkz:
14759 case VPSHLDVQZ256mk:
14760 case VPSHLDVQZ256mkz:
14761 case VPSHLDVQZ256r:
14762 case VPSHLDVQZ256rk:
14763 case VPSHLDVQZ256rkz:
14764 case VPSHLDVQZm:
14765 case VPSHLDVQZmb:
14766 case VPSHLDVQZmbk:
14767 case VPSHLDVQZmbkz:
14768 case VPSHLDVQZmk:
14769 case VPSHLDVQZmkz:
14770 case VPSHLDVQZr:
14771 case VPSHLDVQZrk:
14772 case VPSHLDVQZrkz:
14773 return true;
14774 }
14775 return false;
14776}
14777
14778bool isMOVDDUP(unsigned Opcode) {
14779 switch (Opcode) {
14780 case MOVDDUPrm:
14781 case MOVDDUPrr:
14782 return true;
14783 }
14784 return false;
14785}
14786
14787bool isVMOVDQU64(unsigned Opcode) {
14788 switch (Opcode) {
14789 case VMOVDQU64Z128mr:
14790 case VMOVDQU64Z128mrk:
14791 case VMOVDQU64Z128rm:
14792 case VMOVDQU64Z128rmk:
14793 case VMOVDQU64Z128rmkz:
14794 case VMOVDQU64Z128rr:
14795 case VMOVDQU64Z128rr_REV:
14796 case VMOVDQU64Z128rrk:
14797 case VMOVDQU64Z128rrk_REV:
14798 case VMOVDQU64Z128rrkz:
14799 case VMOVDQU64Z128rrkz_REV:
14800 case VMOVDQU64Z256mr:
14801 case VMOVDQU64Z256mrk:
14802 case VMOVDQU64Z256rm:
14803 case VMOVDQU64Z256rmk:
14804 case VMOVDQU64Z256rmkz:
14805 case VMOVDQU64Z256rr:
14806 case VMOVDQU64Z256rr_REV:
14807 case VMOVDQU64Z256rrk:
14808 case VMOVDQU64Z256rrk_REV:
14809 case VMOVDQU64Z256rrkz:
14810 case VMOVDQU64Z256rrkz_REV:
14811 case VMOVDQU64Zmr:
14812 case VMOVDQU64Zmrk:
14813 case VMOVDQU64Zrm:
14814 case VMOVDQU64Zrmk:
14815 case VMOVDQU64Zrmkz:
14816 case VMOVDQU64Zrr:
14817 case VMOVDQU64Zrr_REV:
14818 case VMOVDQU64Zrrk:
14819 case VMOVDQU64Zrrk_REV:
14820 case VMOVDQU64Zrrkz:
14821 case VMOVDQU64Zrrkz_REV:
14822 return true;
14823 }
14824 return false;
14825}
14826
14827bool isVPCOMPRESSQ(unsigned Opcode) {
14828 switch (Opcode) {
14829 case VPCOMPRESSQZ128mr:
14830 case VPCOMPRESSQZ128mrk:
14831 case VPCOMPRESSQZ128rr:
14832 case VPCOMPRESSQZ128rrk:
14833 case VPCOMPRESSQZ128rrkz:
14834 case VPCOMPRESSQZ256mr:
14835 case VPCOMPRESSQZ256mrk:
14836 case VPCOMPRESSQZ256rr:
14837 case VPCOMPRESSQZ256rrk:
14838 case VPCOMPRESSQZ256rrkz:
14839 case VPCOMPRESSQZmr:
14840 case VPCOMPRESSQZmrk:
14841 case VPCOMPRESSQZrr:
14842 case VPCOMPRESSQZrrk:
14843 case VPCOMPRESSQZrrkz:
14844 return true;
14845 }
14846 return false;
14847}
14848
14849bool isVFMSUBADD132PD(unsigned Opcode) {
14850 switch (Opcode) {
14851 case VFMSUBADD132PDYm:
14852 case VFMSUBADD132PDYr:
14853 case VFMSUBADD132PDZ128m:
14854 case VFMSUBADD132PDZ128mb:
14855 case VFMSUBADD132PDZ128mbk:
14856 case VFMSUBADD132PDZ128mbkz:
14857 case VFMSUBADD132PDZ128mk:
14858 case VFMSUBADD132PDZ128mkz:
14859 case VFMSUBADD132PDZ128r:
14860 case VFMSUBADD132PDZ128rk:
14861 case VFMSUBADD132PDZ128rkz:
14862 case VFMSUBADD132PDZ256m:
14863 case VFMSUBADD132PDZ256mb:
14864 case VFMSUBADD132PDZ256mbk:
14865 case VFMSUBADD132PDZ256mbkz:
14866 case VFMSUBADD132PDZ256mk:
14867 case VFMSUBADD132PDZ256mkz:
14868 case VFMSUBADD132PDZ256r:
14869 case VFMSUBADD132PDZ256rk:
14870 case VFMSUBADD132PDZ256rkz:
14871 case VFMSUBADD132PDZm:
14872 case VFMSUBADD132PDZmb:
14873 case VFMSUBADD132PDZmbk:
14874 case VFMSUBADD132PDZmbkz:
14875 case VFMSUBADD132PDZmk:
14876 case VFMSUBADD132PDZmkz:
14877 case VFMSUBADD132PDZr:
14878 case VFMSUBADD132PDZrb:
14879 case VFMSUBADD132PDZrbk:
14880 case VFMSUBADD132PDZrbkz:
14881 case VFMSUBADD132PDZrk:
14882 case VFMSUBADD132PDZrkz:
14883 case VFMSUBADD132PDm:
14884 case VFMSUBADD132PDr:
14885 return true;
14886 }
14887 return false;
14888}
14889
14890bool isADDSD(unsigned Opcode) {
14891 switch (Opcode) {
14892 case ADDSDrm_Int:
14893 case ADDSDrr_Int:
14894 return true;
14895 }
14896 return false;
14897}
14898
14899bool isBLENDPD(unsigned Opcode) {
14900 switch (Opcode) {
14901 case BLENDPDrmi:
14902 case BLENDPDrri:
14903 return true;
14904 }
14905 return false;
14906}
14907
14908bool isVPERMILPD(unsigned Opcode) {
14909 switch (Opcode) {
14910 case VPERMILPDYmi:
14911 case VPERMILPDYri:
14912 case VPERMILPDYrm:
14913 case VPERMILPDYrr:
14914 case VPERMILPDZ128mbi:
14915 case VPERMILPDZ128mbik:
14916 case VPERMILPDZ128mbikz:
14917 case VPERMILPDZ128mi:
14918 case VPERMILPDZ128mik:
14919 case VPERMILPDZ128mikz:
14920 case VPERMILPDZ128ri:
14921 case VPERMILPDZ128rik:
14922 case VPERMILPDZ128rikz:
14923 case VPERMILPDZ128rm:
14924 case VPERMILPDZ128rmb:
14925 case VPERMILPDZ128rmbk:
14926 case VPERMILPDZ128rmbkz:
14927 case VPERMILPDZ128rmk:
14928 case VPERMILPDZ128rmkz:
14929 case VPERMILPDZ128rr:
14930 case VPERMILPDZ128rrk:
14931 case VPERMILPDZ128rrkz:
14932 case VPERMILPDZ256mbi:
14933 case VPERMILPDZ256mbik:
14934 case VPERMILPDZ256mbikz:
14935 case VPERMILPDZ256mi:
14936 case VPERMILPDZ256mik:
14937 case VPERMILPDZ256mikz:
14938 case VPERMILPDZ256ri:
14939 case VPERMILPDZ256rik:
14940 case VPERMILPDZ256rikz:
14941 case VPERMILPDZ256rm:
14942 case VPERMILPDZ256rmb:
14943 case VPERMILPDZ256rmbk:
14944 case VPERMILPDZ256rmbkz:
14945 case VPERMILPDZ256rmk:
14946 case VPERMILPDZ256rmkz:
14947 case VPERMILPDZ256rr:
14948 case VPERMILPDZ256rrk:
14949 case VPERMILPDZ256rrkz:
14950 case VPERMILPDZmbi:
14951 case VPERMILPDZmbik:
14952 case VPERMILPDZmbikz:
14953 case VPERMILPDZmi:
14954 case VPERMILPDZmik:
14955 case VPERMILPDZmikz:
14956 case VPERMILPDZri:
14957 case VPERMILPDZrik:
14958 case VPERMILPDZrikz:
14959 case VPERMILPDZrm:
14960 case VPERMILPDZrmb:
14961 case VPERMILPDZrmbk:
14962 case VPERMILPDZrmbkz:
14963 case VPERMILPDZrmk:
14964 case VPERMILPDZrmkz:
14965 case VPERMILPDZrr:
14966 case VPERMILPDZrrk:
14967 case VPERMILPDZrrkz:
14968 case VPERMILPDmi:
14969 case VPERMILPDri:
14970 case VPERMILPDrm:
14971 case VPERMILPDrr:
14972 return true;
14973 }
14974 return false;
14975}
14976
14977bool isPMADDUBSW(unsigned Opcode) {
14978 switch (Opcode) {
14979 case MMX_PMADDUBSWrm:
14980 case MMX_PMADDUBSWrr:
14981 case PMADDUBSWrm:
14982 case PMADDUBSWrr:
14983 return true;
14984 }
14985 return false;
14986}
14987
14988bool isPOPFD(unsigned Opcode) {
14989 return Opcode == POPF32;
14990}
14991
14992bool isCMPSW(unsigned Opcode) {
14993 return Opcode == CMPSW;
14994}
14995
14996bool isLDMXCSR(unsigned Opcode) {
14997 return Opcode == LDMXCSR;
14998}
14999
15000bool isVMULPS(unsigned Opcode) {
15001 switch (Opcode) {
15002 case VMULPSYrm:
15003 case VMULPSYrr:
15004 case VMULPSZ128rm:
15005 case VMULPSZ128rmb:
15006 case VMULPSZ128rmbk:
15007 case VMULPSZ128rmbkz:
15008 case VMULPSZ128rmk:
15009 case VMULPSZ128rmkz:
15010 case VMULPSZ128rr:
15011 case VMULPSZ128rrk:
15012 case VMULPSZ128rrkz:
15013 case VMULPSZ256rm:
15014 case VMULPSZ256rmb:
15015 case VMULPSZ256rmbk:
15016 case VMULPSZ256rmbkz:
15017 case VMULPSZ256rmk:
15018 case VMULPSZ256rmkz:
15019 case VMULPSZ256rr:
15020 case VMULPSZ256rrk:
15021 case VMULPSZ256rrkz:
15022 case VMULPSZrm:
15023 case VMULPSZrmb:
15024 case VMULPSZrmbk:
15025 case VMULPSZrmbkz:
15026 case VMULPSZrmk:
15027 case VMULPSZrmkz:
15028 case VMULPSZrr:
15029 case VMULPSZrrb:
15030 case VMULPSZrrbk:
15031 case VMULPSZrrbkz:
15032 case VMULPSZrrk:
15033 case VMULPSZrrkz:
15034 case VMULPSrm:
15035 case VMULPSrr:
15036 return true;
15037 }
15038 return false;
15039}
15040
15041bool isVROUNDSD(unsigned Opcode) {
15042 switch (Opcode) {
15043 case VROUNDSDmi_Int:
15044 case VROUNDSDri_Int:
15045 return true;
15046 }
15047 return false;
15048}
15049
15050bool isVFMADD132PD(unsigned Opcode) {
15051 switch (Opcode) {
15052 case VFMADD132PDYm:
15053 case VFMADD132PDYr:
15054 case VFMADD132PDZ128m:
15055 case VFMADD132PDZ128mb:
15056 case VFMADD132PDZ128mbk:
15057 case VFMADD132PDZ128mbkz:
15058 case VFMADD132PDZ128mk:
15059 case VFMADD132PDZ128mkz:
15060 case VFMADD132PDZ128r:
15061 case VFMADD132PDZ128rk:
15062 case VFMADD132PDZ128rkz:
15063 case VFMADD132PDZ256m:
15064 case VFMADD132PDZ256mb:
15065 case VFMADD132PDZ256mbk:
15066 case VFMADD132PDZ256mbkz:
15067 case VFMADD132PDZ256mk:
15068 case VFMADD132PDZ256mkz:
15069 case VFMADD132PDZ256r:
15070 case VFMADD132PDZ256rk:
15071 case VFMADD132PDZ256rkz:
15072 case VFMADD132PDZm:
15073 case VFMADD132PDZmb:
15074 case VFMADD132PDZmbk:
15075 case VFMADD132PDZmbkz:
15076 case VFMADD132PDZmk:
15077 case VFMADD132PDZmkz:
15078 case VFMADD132PDZr:
15079 case VFMADD132PDZrb:
15080 case VFMADD132PDZrbk:
15081 case VFMADD132PDZrbkz:
15082 case VFMADD132PDZrk:
15083 case VFMADD132PDZrkz:
15084 case VFMADD132PDm:
15085 case VFMADD132PDr:
15086 return true;
15087 }
15088 return false;
15089}
15090
15091bool isVPANDQ(unsigned Opcode) {
15092 switch (Opcode) {
15093 case VPANDQZ128rm:
15094 case VPANDQZ128rmb:
15095 case VPANDQZ128rmbk:
15096 case VPANDQZ128rmbkz:
15097 case VPANDQZ128rmk:
15098 case VPANDQZ128rmkz:
15099 case VPANDQZ128rr:
15100 case VPANDQZ128rrk:
15101 case VPANDQZ128rrkz:
15102 case VPANDQZ256rm:
15103 case VPANDQZ256rmb:
15104 case VPANDQZ256rmbk:
15105 case VPANDQZ256rmbkz:
15106 case VPANDQZ256rmk:
15107 case VPANDQZ256rmkz:
15108 case VPANDQZ256rr:
15109 case VPANDQZ256rrk:
15110 case VPANDQZ256rrkz:
15111 case VPANDQZrm:
15112 case VPANDQZrmb:
15113 case VPANDQZrmbk:
15114 case VPANDQZrmbkz:
15115 case VPANDQZrmk:
15116 case VPANDQZrmkz:
15117 case VPANDQZrr:
15118 case VPANDQZrrk:
15119 case VPANDQZrrkz:
15120 return true;
15121 }
15122 return false;
15123}
15124
15125bool isVPSRAQ(unsigned Opcode) {
15126 switch (Opcode) {
15127 case VPSRAQZ128mbi:
15128 case VPSRAQZ128mbik:
15129 case VPSRAQZ128mbikz:
15130 case VPSRAQZ128mi:
15131 case VPSRAQZ128mik:
15132 case VPSRAQZ128mikz:
15133 case VPSRAQZ128ri:
15134 case VPSRAQZ128rik:
15135 case VPSRAQZ128rikz:
15136 case VPSRAQZ128rm:
15137 case VPSRAQZ128rmk:
15138 case VPSRAQZ128rmkz:
15139 case VPSRAQZ128rr:
15140 case VPSRAQZ128rrk:
15141 case VPSRAQZ128rrkz:
15142 case VPSRAQZ256mbi:
15143 case VPSRAQZ256mbik:
15144 case VPSRAQZ256mbikz:
15145 case VPSRAQZ256mi:
15146 case VPSRAQZ256mik:
15147 case VPSRAQZ256mikz:
15148 case VPSRAQZ256ri:
15149 case VPSRAQZ256rik:
15150 case VPSRAQZ256rikz:
15151 case VPSRAQZ256rm:
15152 case VPSRAQZ256rmk:
15153 case VPSRAQZ256rmkz:
15154 case VPSRAQZ256rr:
15155 case VPSRAQZ256rrk:
15156 case VPSRAQZ256rrkz:
15157 case VPSRAQZmbi:
15158 case VPSRAQZmbik:
15159 case VPSRAQZmbikz:
15160 case VPSRAQZmi:
15161 case VPSRAQZmik:
15162 case VPSRAQZmikz:
15163 case VPSRAQZri:
15164 case VPSRAQZrik:
15165 case VPSRAQZrikz:
15166 case VPSRAQZrm:
15167 case VPSRAQZrmk:
15168 case VPSRAQZrmkz:
15169 case VPSRAQZrr:
15170 case VPSRAQZrrk:
15171 case VPSRAQZrrkz:
15172 return true;
15173 }
15174 return false;
15175}
15176
15177bool isVCOMISD(unsigned Opcode) {
15178 switch (Opcode) {
15179 case VCOMISDZrm:
15180 case VCOMISDZrr:
15181 case VCOMISDZrrb:
15182 case VCOMISDrm:
15183 case VCOMISDrr:
15184 return true;
15185 }
15186 return false;
15187}
15188
15189bool isFFREEP(unsigned Opcode) {
15190 return Opcode == FFREEP;
15191}
15192
15193bool isVFNMADD213PD(unsigned Opcode) {
15194 switch (Opcode) {
15195 case VFNMADD213PDYm:
15196 case VFNMADD213PDYr:
15197 case VFNMADD213PDZ128m:
15198 case VFNMADD213PDZ128mb:
15199 case VFNMADD213PDZ128mbk:
15200 case VFNMADD213PDZ128mbkz:
15201 case VFNMADD213PDZ128mk:
15202 case VFNMADD213PDZ128mkz:
15203 case VFNMADD213PDZ128r:
15204 case VFNMADD213PDZ128rk:
15205 case VFNMADD213PDZ128rkz:
15206 case VFNMADD213PDZ256m:
15207 case VFNMADD213PDZ256mb:
15208 case VFNMADD213PDZ256mbk:
15209 case VFNMADD213PDZ256mbkz:
15210 case VFNMADD213PDZ256mk:
15211 case VFNMADD213PDZ256mkz:
15212 case VFNMADD213PDZ256r:
15213 case VFNMADD213PDZ256rk:
15214 case VFNMADD213PDZ256rkz:
15215 case VFNMADD213PDZm:
15216 case VFNMADD213PDZmb:
15217 case VFNMADD213PDZmbk:
15218 case VFNMADD213PDZmbkz:
15219 case VFNMADD213PDZmk:
15220 case VFNMADD213PDZmkz:
15221 case VFNMADD213PDZr:
15222 case VFNMADD213PDZrb:
15223 case VFNMADD213PDZrbk:
15224 case VFNMADD213PDZrbkz:
15225 case VFNMADD213PDZrk:
15226 case VFNMADD213PDZrkz:
15227 case VFNMADD213PDm:
15228 case VFNMADD213PDr:
15229 return true;
15230 }
15231 return false;
15232}
15233
15234bool isVCMPPD(unsigned Opcode) {
15235 switch (Opcode) {
15236 case VCMPPDYrmi:
15237 case VCMPPDYrri:
15238 case VCMPPDZ128rmbi:
15239 case VCMPPDZ128rmbik:
15240 case VCMPPDZ128rmi:
15241 case VCMPPDZ128rmik:
15242 case VCMPPDZ128rri:
15243 case VCMPPDZ128rrik:
15244 case VCMPPDZ256rmbi:
15245 case VCMPPDZ256rmbik:
15246 case VCMPPDZ256rmi:
15247 case VCMPPDZ256rmik:
15248 case VCMPPDZ256rri:
15249 case VCMPPDZ256rrik:
15250 case VCMPPDZrmbi:
15251 case VCMPPDZrmbik:
15252 case VCMPPDZrmi:
15253 case VCMPPDZrmik:
15254 case VCMPPDZrri:
15255 case VCMPPDZrrib:
15256 case VCMPPDZrribk:
15257 case VCMPPDZrrik:
15258 case VCMPPDrmi:
15259 case VCMPPDrri:
15260 return true;
15261 }
15262 return false;
15263}
15264
15265bool isVFNMSUB132PH(unsigned Opcode) {
15266 switch (Opcode) {
15267 case VFNMSUB132PHZ128m:
15268 case VFNMSUB132PHZ128mb:
15269 case VFNMSUB132PHZ128mbk:
15270 case VFNMSUB132PHZ128mbkz:
15271 case VFNMSUB132PHZ128mk:
15272 case VFNMSUB132PHZ128mkz:
15273 case VFNMSUB132PHZ128r:
15274 case VFNMSUB132PHZ128rk:
15275 case VFNMSUB132PHZ128rkz:
15276 case VFNMSUB132PHZ256m:
15277 case VFNMSUB132PHZ256mb:
15278 case VFNMSUB132PHZ256mbk:
15279 case VFNMSUB132PHZ256mbkz:
15280 case VFNMSUB132PHZ256mk:
15281 case VFNMSUB132PHZ256mkz:
15282 case VFNMSUB132PHZ256r:
15283 case VFNMSUB132PHZ256rk:
15284 case VFNMSUB132PHZ256rkz:
15285 case VFNMSUB132PHZm:
15286 case VFNMSUB132PHZmb:
15287 case VFNMSUB132PHZmbk:
15288 case VFNMSUB132PHZmbkz:
15289 case VFNMSUB132PHZmk:
15290 case VFNMSUB132PHZmkz:
15291 case VFNMSUB132PHZr:
15292 case VFNMSUB132PHZrb:
15293 case VFNMSUB132PHZrbk:
15294 case VFNMSUB132PHZrbkz:
15295 case VFNMSUB132PHZrk:
15296 case VFNMSUB132PHZrkz:
15297 return true;
15298 }
15299 return false;
15300}
15301
15302bool isVPHADDBW(unsigned Opcode) {
15303 switch (Opcode) {
15304 case VPHADDBWrm:
15305 case VPHADDBWrr:
15306 return true;
15307 }
15308 return false;
15309}
15310
15311bool isVPPERM(unsigned Opcode) {
15312 switch (Opcode) {
15313 case VPPERMrmr:
15314 case VPPERMrrm:
15315 case VPPERMrrr:
15316 case VPPERMrrr_REV:
15317 return true;
15318 }
15319 return false;
15320}
15321
15322bool isVCVTPS2PD(unsigned Opcode) {
15323 switch (Opcode) {
15324 case VCVTPS2PDYrm:
15325 case VCVTPS2PDYrr:
15326 case VCVTPS2PDZ128rm:
15327 case VCVTPS2PDZ128rmb:
15328 case VCVTPS2PDZ128rmbk:
15329 case VCVTPS2PDZ128rmbkz:
15330 case VCVTPS2PDZ128rmk:
15331 case VCVTPS2PDZ128rmkz:
15332 case VCVTPS2PDZ128rr:
15333 case VCVTPS2PDZ128rrk:
15334 case VCVTPS2PDZ128rrkz:
15335 case VCVTPS2PDZ256rm:
15336 case VCVTPS2PDZ256rmb:
15337 case VCVTPS2PDZ256rmbk:
15338 case VCVTPS2PDZ256rmbkz:
15339 case VCVTPS2PDZ256rmk:
15340 case VCVTPS2PDZ256rmkz:
15341 case VCVTPS2PDZ256rr:
15342 case VCVTPS2PDZ256rrk:
15343 case VCVTPS2PDZ256rrkz:
15344 case VCVTPS2PDZrm:
15345 case VCVTPS2PDZrmb:
15346 case VCVTPS2PDZrmbk:
15347 case VCVTPS2PDZrmbkz:
15348 case VCVTPS2PDZrmk:
15349 case VCVTPS2PDZrmkz:
15350 case VCVTPS2PDZrr:
15351 case VCVTPS2PDZrrb:
15352 case VCVTPS2PDZrrbk:
15353 case VCVTPS2PDZrrbkz:
15354 case VCVTPS2PDZrrk:
15355 case VCVTPS2PDZrrkz:
15356 case VCVTPS2PDrm:
15357 case VCVTPS2PDrr:
15358 return true;
15359 }
15360 return false;
15361}
15362
15363bool isCBW(unsigned Opcode) {
15364 return Opcode == CBW;
15365}
15366
15367bool isVMOVUPS(unsigned Opcode) {
15368 switch (Opcode) {
15369 case VMOVUPSYmr:
15370 case VMOVUPSYrm:
15371 case VMOVUPSYrr:
15372 case VMOVUPSYrr_REV:
15373 case VMOVUPSZ128mr:
15374 case VMOVUPSZ128mrk:
15375 case VMOVUPSZ128rm:
15376 case VMOVUPSZ128rmk:
15377 case VMOVUPSZ128rmkz:
15378 case VMOVUPSZ128rr:
15379 case VMOVUPSZ128rr_REV:
15380 case VMOVUPSZ128rrk:
15381 case VMOVUPSZ128rrk_REV:
15382 case VMOVUPSZ128rrkz:
15383 case VMOVUPSZ128rrkz_REV:
15384 case VMOVUPSZ256mr:
15385 case VMOVUPSZ256mrk:
15386 case VMOVUPSZ256rm:
15387 case VMOVUPSZ256rmk:
15388 case VMOVUPSZ256rmkz:
15389 case VMOVUPSZ256rr:
15390 case VMOVUPSZ256rr_REV:
15391 case VMOVUPSZ256rrk:
15392 case VMOVUPSZ256rrk_REV:
15393 case VMOVUPSZ256rrkz:
15394 case VMOVUPSZ256rrkz_REV:
15395 case VMOVUPSZmr:
15396 case VMOVUPSZmrk:
15397 case VMOVUPSZrm:
15398 case VMOVUPSZrmk:
15399 case VMOVUPSZrmkz:
15400 case VMOVUPSZrr:
15401 case VMOVUPSZrr_REV:
15402 case VMOVUPSZrrk:
15403 case VMOVUPSZrrk_REV:
15404 case VMOVUPSZrrkz:
15405 case VMOVUPSZrrkz_REV:
15406 case VMOVUPSmr:
15407 case VMOVUPSrm:
15408 case VMOVUPSrr:
15409 case VMOVUPSrr_REV:
15410 return true;
15411 }
15412 return false;
15413}
15414
15415bool isVPMAXUQ(unsigned Opcode) {
15416 switch (Opcode) {
15417 case VPMAXUQZ128rm:
15418 case VPMAXUQZ128rmb:
15419 case VPMAXUQZ128rmbk:
15420 case VPMAXUQZ128rmbkz:
15421 case VPMAXUQZ128rmk:
15422 case VPMAXUQZ128rmkz:
15423 case VPMAXUQZ128rr:
15424 case VPMAXUQZ128rrk:
15425 case VPMAXUQZ128rrkz:
15426 case VPMAXUQZ256rm:
15427 case VPMAXUQZ256rmb:
15428 case VPMAXUQZ256rmbk:
15429 case VPMAXUQZ256rmbkz:
15430 case VPMAXUQZ256rmk:
15431 case VPMAXUQZ256rmkz:
15432 case VPMAXUQZ256rr:
15433 case VPMAXUQZ256rrk:
15434 case VPMAXUQZ256rrkz:
15435 case VPMAXUQZrm:
15436 case VPMAXUQZrmb:
15437 case VPMAXUQZrmbk:
15438 case VPMAXUQZrmbkz:
15439 case VPMAXUQZrmk:
15440 case VPMAXUQZrmkz:
15441 case VPMAXUQZrr:
15442 case VPMAXUQZrrk:
15443 case VPMAXUQZrrkz:
15444 return true;
15445 }
15446 return false;
15447}
15448
15449bool isWRSSQ(unsigned Opcode) {
15450 switch (Opcode) {
15451 case WRSSQ:
15452 case WRSSQ_EVEX:
15453 return true;
15454 }
15455 return false;
15456}
15457
15458bool isPACKUSDW(unsigned Opcode) {
15459 switch (Opcode) {
15460 case PACKUSDWrm:
15461 case PACKUSDWrr:
15462 return true;
15463 }
15464 return false;
15465}
15466
15467bool isXBEGIN(unsigned Opcode) {
15468 switch (Opcode) {
15469 case XBEGIN_2:
15470 case XBEGIN_4:
15471 return true;
15472 }
15473 return false;
15474}
15475
15476bool isVCVTPD2UQQ(unsigned Opcode) {
15477 switch (Opcode) {
15478 case VCVTPD2UQQZ128rm:
15479 case VCVTPD2UQQZ128rmb:
15480 case VCVTPD2UQQZ128rmbk:
15481 case VCVTPD2UQQZ128rmbkz:
15482 case VCVTPD2UQQZ128rmk:
15483 case VCVTPD2UQQZ128rmkz:
15484 case VCVTPD2UQQZ128rr:
15485 case VCVTPD2UQQZ128rrk:
15486 case VCVTPD2UQQZ128rrkz:
15487 case VCVTPD2UQQZ256rm:
15488 case VCVTPD2UQQZ256rmb:
15489 case VCVTPD2UQQZ256rmbk:
15490 case VCVTPD2UQQZ256rmbkz:
15491 case VCVTPD2UQQZ256rmk:
15492 case VCVTPD2UQQZ256rmkz:
15493 case VCVTPD2UQQZ256rr:
15494 case VCVTPD2UQQZ256rrk:
15495 case VCVTPD2UQQZ256rrkz:
15496 case VCVTPD2UQQZrm:
15497 case VCVTPD2UQQZrmb:
15498 case VCVTPD2UQQZrmbk:
15499 case VCVTPD2UQQZrmbkz:
15500 case VCVTPD2UQQZrmk:
15501 case VCVTPD2UQQZrmkz:
15502 case VCVTPD2UQQZrr:
15503 case VCVTPD2UQQZrrb:
15504 case VCVTPD2UQQZrrbk:
15505 case VCVTPD2UQQZrrbkz:
15506 case VCVTPD2UQQZrrk:
15507 case VCVTPD2UQQZrrkz:
15508 return true;
15509 }
15510 return false;
15511}
15512
15513bool isFCMOVB(unsigned Opcode) {
15514 return Opcode == CMOVB_F;
15515}
15516
15517bool isNOP(unsigned Opcode) {
15518 switch (Opcode) {
15519 case NOOP:
15520 case NOOPL:
15521 case NOOPLr:
15522 case NOOPQ:
15523 case NOOPQr:
15524 case NOOPW:
15525 case NOOPWr:
15526 return true;
15527 }
15528 return false;
15529}
15530
15531bool isVPABSQ(unsigned Opcode) {
15532 switch (Opcode) {
15533 case VPABSQZ128rm:
15534 case VPABSQZ128rmb:
15535 case VPABSQZ128rmbk:
15536 case VPABSQZ128rmbkz:
15537 case VPABSQZ128rmk:
15538 case VPABSQZ128rmkz:
15539 case VPABSQZ128rr:
15540 case VPABSQZ128rrk:
15541 case VPABSQZ128rrkz:
15542 case VPABSQZ256rm:
15543 case VPABSQZ256rmb:
15544 case VPABSQZ256rmbk:
15545 case VPABSQZ256rmbkz:
15546 case VPABSQZ256rmk:
15547 case VPABSQZ256rmkz:
15548 case VPABSQZ256rr:
15549 case VPABSQZ256rrk:
15550 case VPABSQZ256rrkz:
15551 case VPABSQZrm:
15552 case VPABSQZrmb:
15553 case VPABSQZrmbk:
15554 case VPABSQZrmbkz:
15555 case VPABSQZrmk:
15556 case VPABSQZrmkz:
15557 case VPABSQZrr:
15558 case VPABSQZrrk:
15559 case VPABSQZrrkz:
15560 return true;
15561 }
15562 return false;
15563}
15564
15565bool isVTESTPS(unsigned Opcode) {
15566 switch (Opcode) {
15567 case VTESTPSYrm:
15568 case VTESTPSYrr:
15569 case VTESTPSrm:
15570 case VTESTPSrr:
15571 return true;
15572 }
15573 return false;
15574}
15575
15576bool isPHSUBW(unsigned Opcode) {
15577 switch (Opcode) {
15578 case MMX_PHSUBWrm:
15579 case MMX_PHSUBWrr:
15580 case PHSUBWrm:
15581 case PHSUBWrr:
15582 return true;
15583 }
15584 return false;
15585}
15586
15587bool isPUSH2P(unsigned Opcode) {
15588 return Opcode == PUSH2P;
15589}
15590
15591bool isFISTTP(unsigned Opcode) {
15592 switch (Opcode) {
15593 case ISTT_FP16m:
15594 case ISTT_FP32m:
15595 case ISTT_FP64m:
15596 return true;
15597 }
15598 return false;
15599}
15600
15601bool isCFCMOVCC(unsigned Opcode) {
15602 switch (Opcode) {
15603 case CFCMOV16mr:
15604 case CFCMOV16rm:
15605 case CFCMOV16rm_ND:
15606 case CFCMOV16rr:
15607 case CFCMOV16rr_ND:
15608 case CFCMOV16rr_REV:
15609 case CFCMOV32mr:
15610 case CFCMOV32rm:
15611 case CFCMOV32rm_ND:
15612 case CFCMOV32rr:
15613 case CFCMOV32rr_ND:
15614 case CFCMOV32rr_REV:
15615 case CFCMOV64mr:
15616 case CFCMOV64rm:
15617 case CFCMOV64rm_ND:
15618 case CFCMOV64rr:
15619 case CFCMOV64rr_ND:
15620 case CFCMOV64rr_REV:
15621 return true;
15622 }
15623 return false;
15624}
15625
15626bool isVPINSRD(unsigned Opcode) {
15627 switch (Opcode) {
15628 case VPINSRDZrm:
15629 case VPINSRDZrr:
15630 case VPINSRDrm:
15631 case VPINSRDrr:
15632 return true;
15633 }
15634 return false;
15635}
15636
15637bool isPCMPESTRM(unsigned Opcode) {
15638 switch (Opcode) {
15639 case PCMPESTRMrmi:
15640 case PCMPESTRMrri:
15641 return true;
15642 }
15643 return false;
15644}
15645
15646bool isVFNMSUB213PS(unsigned Opcode) {
15647 switch (Opcode) {
15648 case VFNMSUB213PSYm:
15649 case VFNMSUB213PSYr:
15650 case VFNMSUB213PSZ128m:
15651 case VFNMSUB213PSZ128mb:
15652 case VFNMSUB213PSZ128mbk:
15653 case VFNMSUB213PSZ128mbkz:
15654 case VFNMSUB213PSZ128mk:
15655 case VFNMSUB213PSZ128mkz:
15656 case VFNMSUB213PSZ128r:
15657 case VFNMSUB213PSZ128rk:
15658 case VFNMSUB213PSZ128rkz:
15659 case VFNMSUB213PSZ256m:
15660 case VFNMSUB213PSZ256mb:
15661 case VFNMSUB213PSZ256mbk:
15662 case VFNMSUB213PSZ256mbkz:
15663 case VFNMSUB213PSZ256mk:
15664 case VFNMSUB213PSZ256mkz:
15665 case VFNMSUB213PSZ256r:
15666 case VFNMSUB213PSZ256rk:
15667 case VFNMSUB213PSZ256rkz:
15668 case VFNMSUB213PSZm:
15669 case VFNMSUB213PSZmb:
15670 case VFNMSUB213PSZmbk:
15671 case VFNMSUB213PSZmbkz:
15672 case VFNMSUB213PSZmk:
15673 case VFNMSUB213PSZmkz:
15674 case VFNMSUB213PSZr:
15675 case VFNMSUB213PSZrb:
15676 case VFNMSUB213PSZrbk:
15677 case VFNMSUB213PSZrbkz:
15678 case VFNMSUB213PSZrk:
15679 case VFNMSUB213PSZrkz:
15680 case VFNMSUB213PSm:
15681 case VFNMSUB213PSr:
15682 return true;
15683 }
15684 return false;
15685}
15686
15687bool isPHSUBD(unsigned Opcode) {
15688 switch (Opcode) {
15689 case MMX_PHSUBDrm:
15690 case MMX_PHSUBDrr:
15691 case PHSUBDrm:
15692 case PHSUBDrr:
15693 return true;
15694 }
15695 return false;
15696}
15697
15698bool isSLDT(unsigned Opcode) {
15699 switch (Opcode) {
15700 case SLDT16m:
15701 case SLDT16r:
15702 case SLDT32r:
15703 case SLDT64r:
15704 return true;
15705 }
15706 return false;
15707}
15708
15709bool isVPMINSD(unsigned Opcode) {
15710 switch (Opcode) {
15711 case VPMINSDYrm:
15712 case VPMINSDYrr:
15713 case VPMINSDZ128rm:
15714 case VPMINSDZ128rmb:
15715 case VPMINSDZ128rmbk:
15716 case VPMINSDZ128rmbkz:
15717 case VPMINSDZ128rmk:
15718 case VPMINSDZ128rmkz:
15719 case VPMINSDZ128rr:
15720 case VPMINSDZ128rrk:
15721 case VPMINSDZ128rrkz:
15722 case VPMINSDZ256rm:
15723 case VPMINSDZ256rmb:
15724 case VPMINSDZ256rmbk:
15725 case VPMINSDZ256rmbkz:
15726 case VPMINSDZ256rmk:
15727 case VPMINSDZ256rmkz:
15728 case VPMINSDZ256rr:
15729 case VPMINSDZ256rrk:
15730 case VPMINSDZ256rrkz:
15731 case VPMINSDZrm:
15732 case VPMINSDZrmb:
15733 case VPMINSDZrmbk:
15734 case VPMINSDZrmbkz:
15735 case VPMINSDZrmk:
15736 case VPMINSDZrmkz:
15737 case VPMINSDZrr:
15738 case VPMINSDZrrk:
15739 case VPMINSDZrrkz:
15740 case VPMINSDrm:
15741 case VPMINSDrr:
15742 return true;
15743 }
15744 return false;
15745}
15746
15747bool isVHADDPS(unsigned Opcode) {
15748 switch (Opcode) {
15749 case VHADDPSYrm:
15750 case VHADDPSYrr:
15751 case VHADDPSrm:
15752 case VHADDPSrr:
15753 return true;
15754 }
15755 return false;
15756}
15757
15758bool isVMOVNTDQ(unsigned Opcode) {
15759 switch (Opcode) {
15760 case VMOVNTDQYmr:
15761 case VMOVNTDQZ128mr:
15762 case VMOVNTDQZ256mr:
15763 case VMOVNTDQZmr:
15764 case VMOVNTDQmr:
15765 return true;
15766 }
15767 return false;
15768}
15769
15770bool isVFRCZSD(unsigned Opcode) {
15771 switch (Opcode) {
15772 case VFRCZSDrm:
15773 case VFRCZSDrr:
15774 return true;
15775 }
15776 return false;
15777}
15778
15779bool isVPTESTMW(unsigned Opcode) {
15780 switch (Opcode) {
15781 case VPTESTMWZ128rm:
15782 case VPTESTMWZ128rmk:
15783 case VPTESTMWZ128rr:
15784 case VPTESTMWZ128rrk:
15785 case VPTESTMWZ256rm:
15786 case VPTESTMWZ256rmk:
15787 case VPTESTMWZ256rr:
15788 case VPTESTMWZ256rrk:
15789 case VPTESTMWZrm:
15790 case VPTESTMWZrmk:
15791 case VPTESTMWZrr:
15792 case VPTESTMWZrrk:
15793 return true;
15794 }
15795 return false;
15796}
15797
15798bool isVPMOVZXWD(unsigned Opcode) {
15799 switch (Opcode) {
15800 case VPMOVZXWDYrm:
15801 case VPMOVZXWDYrr:
15802 case VPMOVZXWDZ128rm:
15803 case VPMOVZXWDZ128rmk:
15804 case VPMOVZXWDZ128rmkz:
15805 case VPMOVZXWDZ128rr:
15806 case VPMOVZXWDZ128rrk:
15807 case VPMOVZXWDZ128rrkz:
15808 case VPMOVZXWDZ256rm:
15809 case VPMOVZXWDZ256rmk:
15810 case VPMOVZXWDZ256rmkz:
15811 case VPMOVZXWDZ256rr:
15812 case VPMOVZXWDZ256rrk:
15813 case VPMOVZXWDZ256rrkz:
15814 case VPMOVZXWDZrm:
15815 case VPMOVZXWDZrmk:
15816 case VPMOVZXWDZrmkz:
15817 case VPMOVZXWDZrr:
15818 case VPMOVZXWDZrrk:
15819 case VPMOVZXWDZrrkz:
15820 case VPMOVZXWDrm:
15821 case VPMOVZXWDrr:
15822 return true;
15823 }
15824 return false;
15825}
15826
15827bool isPSADBW(unsigned Opcode) {
15828 switch (Opcode) {
15829 case MMX_PSADBWrm:
15830 case MMX_PSADBWrr:
15831 case PSADBWrm:
15832 case PSADBWrr:
15833 return true;
15834 }
15835 return false;
15836}
15837
15838bool isVCVTSD2SI(unsigned Opcode) {
15839 switch (Opcode) {
15840 case VCVTSD2SI64Zrm_Int:
15841 case VCVTSD2SI64Zrr_Int:
15842 case VCVTSD2SI64Zrrb_Int:
15843 case VCVTSD2SI64rm_Int:
15844 case VCVTSD2SI64rr_Int:
15845 case VCVTSD2SIZrm_Int:
15846 case VCVTSD2SIZrr_Int:
15847 case VCVTSD2SIZrrb_Int:
15848 case VCVTSD2SIrm_Int:
15849 case VCVTSD2SIrr_Int:
15850 return true;
15851 }
15852 return false;
15853}
15854
15855bool isVMAXPH(unsigned Opcode) {
15856 switch (Opcode) {
15857 case VMAXPHZ128rm:
15858 case VMAXPHZ128rmb:
15859 case VMAXPHZ128rmbk:
15860 case VMAXPHZ128rmbkz:
15861 case VMAXPHZ128rmk:
15862 case VMAXPHZ128rmkz:
15863 case VMAXPHZ128rr:
15864 case VMAXPHZ128rrk:
15865 case VMAXPHZ128rrkz:
15866 case VMAXPHZ256rm:
15867 case VMAXPHZ256rmb:
15868 case VMAXPHZ256rmbk:
15869 case VMAXPHZ256rmbkz:
15870 case VMAXPHZ256rmk:
15871 case VMAXPHZ256rmkz:
15872 case VMAXPHZ256rr:
15873 case VMAXPHZ256rrk:
15874 case VMAXPHZ256rrkz:
15875 case VMAXPHZrm:
15876 case VMAXPHZrmb:
15877 case VMAXPHZrmbk:
15878 case VMAXPHZrmbkz:
15879 case VMAXPHZrmk:
15880 case VMAXPHZrmkz:
15881 case VMAXPHZrr:
15882 case VMAXPHZrrb:
15883 case VMAXPHZrrbk:
15884 case VMAXPHZrrbkz:
15885 case VMAXPHZrrk:
15886 case VMAXPHZrrkz:
15887 return true;
15888 }
15889 return false;
15890}
15891
15892bool isLODSB(unsigned Opcode) {
15893 return Opcode == LODSB;
15894}
15895
15896bool isPHMINPOSUW(unsigned Opcode) {
15897 switch (Opcode) {
15898 case PHMINPOSUWrm:
15899 case PHMINPOSUWrr:
15900 return true;
15901 }
15902 return false;
15903}
15904
15905bool isVPROLVD(unsigned Opcode) {
15906 switch (Opcode) {
15907 case VPROLVDZ128rm:
15908 case VPROLVDZ128rmb:
15909 case VPROLVDZ128rmbk:
15910 case VPROLVDZ128rmbkz:
15911 case VPROLVDZ128rmk:
15912 case VPROLVDZ128rmkz:
15913 case VPROLVDZ128rr:
15914 case VPROLVDZ128rrk:
15915 case VPROLVDZ128rrkz:
15916 case VPROLVDZ256rm:
15917 case VPROLVDZ256rmb:
15918 case VPROLVDZ256rmbk:
15919 case VPROLVDZ256rmbkz:
15920 case VPROLVDZ256rmk:
15921 case VPROLVDZ256rmkz:
15922 case VPROLVDZ256rr:
15923 case VPROLVDZ256rrk:
15924 case VPROLVDZ256rrkz:
15925 case VPROLVDZrm:
15926 case VPROLVDZrmb:
15927 case VPROLVDZrmbk:
15928 case VPROLVDZrmbkz:
15929 case VPROLVDZrmk:
15930 case VPROLVDZrmkz:
15931 case VPROLVDZrr:
15932 case VPROLVDZrrk:
15933 case VPROLVDZrrkz:
15934 return true;
15935 }
15936 return false;
15937}
15938
15939bool isWRFSBASE(unsigned Opcode) {
15940 switch (Opcode) {
15941 case WRFSBASE:
15942 case WRFSBASE64:
15943 return true;
15944 }
15945 return false;
15946}
15947
15948bool isVRSQRT14PS(unsigned Opcode) {
15949 switch (Opcode) {
15950 case VRSQRT14PSZ128m:
15951 case VRSQRT14PSZ128mb:
15952 case VRSQRT14PSZ128mbk:
15953 case VRSQRT14PSZ128mbkz:
15954 case VRSQRT14PSZ128mk:
15955 case VRSQRT14PSZ128mkz:
15956 case VRSQRT14PSZ128r:
15957 case VRSQRT14PSZ128rk:
15958 case VRSQRT14PSZ128rkz:
15959 case VRSQRT14PSZ256m:
15960 case VRSQRT14PSZ256mb:
15961 case VRSQRT14PSZ256mbk:
15962 case VRSQRT14PSZ256mbkz:
15963 case VRSQRT14PSZ256mk:
15964 case VRSQRT14PSZ256mkz:
15965 case VRSQRT14PSZ256r:
15966 case VRSQRT14PSZ256rk:
15967 case VRSQRT14PSZ256rkz:
15968 case VRSQRT14PSZm:
15969 case VRSQRT14PSZmb:
15970 case VRSQRT14PSZmbk:
15971 case VRSQRT14PSZmbkz:
15972 case VRSQRT14PSZmk:
15973 case VRSQRT14PSZmkz:
15974 case VRSQRT14PSZr:
15975 case VRSQRT14PSZrk:
15976 case VRSQRT14PSZrkz:
15977 return true;
15978 }
15979 return false;
15980}
15981
15982bool isVPHSUBDQ(unsigned Opcode) {
15983 switch (Opcode) {
15984 case VPHSUBDQrm:
15985 case VPHSUBDQrr:
15986 return true;
15987 }
15988 return false;
15989}
15990
15991bool isIRETD(unsigned Opcode) {
15992 return Opcode == IRET32;
15993}
15994
15995bool isCVTSI2SS(unsigned Opcode) {
15996 switch (Opcode) {
15997 case CVTSI2SSrm_Int:
15998 case CVTSI2SSrr_Int:
15999 case CVTSI642SSrm_Int:
16000 case CVTSI642SSrr_Int:
16001 return true;
16002 }
16003 return false;
16004}
16005
16006bool isVPMULHRSW(unsigned Opcode) {
16007 switch (Opcode) {
16008 case VPMULHRSWYrm:
16009 case VPMULHRSWYrr:
16010 case VPMULHRSWZ128rm:
16011 case VPMULHRSWZ128rmk:
16012 case VPMULHRSWZ128rmkz:
16013 case VPMULHRSWZ128rr:
16014 case VPMULHRSWZ128rrk:
16015 case VPMULHRSWZ128rrkz:
16016 case VPMULHRSWZ256rm:
16017 case VPMULHRSWZ256rmk:
16018 case VPMULHRSWZ256rmkz:
16019 case VPMULHRSWZ256rr:
16020 case VPMULHRSWZ256rrk:
16021 case VPMULHRSWZ256rrkz:
16022 case VPMULHRSWZrm:
16023 case VPMULHRSWZrmk:
16024 case VPMULHRSWZrmkz:
16025 case VPMULHRSWZrr:
16026 case VPMULHRSWZrrk:
16027 case VPMULHRSWZrrkz:
16028 case VPMULHRSWrm:
16029 case VPMULHRSWrr:
16030 return true;
16031 }
16032 return false;
16033}
16034
16035bool isPI2FD(unsigned Opcode) {
16036 switch (Opcode) {
16037 case PI2FDrm:
16038 case PI2FDrr:
16039 return true;
16040 }
16041 return false;
16042}
16043
16044bool isGF2P8AFFINEQB(unsigned Opcode) {
16045 switch (Opcode) {
16046 case GF2P8AFFINEQBrmi:
16047 case GF2P8AFFINEQBrri:
16048 return true;
16049 }
16050 return false;
16051}
16052
16053bool isPAND(unsigned Opcode) {
16054 switch (Opcode) {
16055 case MMX_PANDrm:
16056 case MMX_PANDrr:
16057 case PANDrm:
16058 case PANDrr:
16059 return true;
16060 }
16061 return false;
16062}
16063
16064bool isVFNMSUB231SH(unsigned Opcode) {
16065 switch (Opcode) {
16066 case VFNMSUB231SHZm_Int:
16067 case VFNMSUB231SHZm_Intk:
16068 case VFNMSUB231SHZm_Intkz:
16069 case VFNMSUB231SHZr_Int:
16070 case VFNMSUB231SHZr_Intk:
16071 case VFNMSUB231SHZr_Intkz:
16072 case VFNMSUB231SHZrb_Int:
16073 case VFNMSUB231SHZrb_Intk:
16074 case VFNMSUB231SHZrb_Intkz:
16075 return true;
16076 }
16077 return false;
16078}
16079
16080bool isVMOVHLPS(unsigned Opcode) {
16081 switch (Opcode) {
16082 case VMOVHLPSZrr:
16083 case VMOVHLPSrr:
16084 return true;
16085 }
16086 return false;
16087}
16088
16089bool isPEXTRB(unsigned Opcode) {
16090 switch (Opcode) {
16091 case PEXTRBmr:
16092 case PEXTRBrr:
16093 return true;
16094 }
16095 return false;
16096}
16097
16098bool isKNOTD(unsigned Opcode) {
16099 return Opcode == KNOTDrr;
16100}
16101
16102bool isVPUNPCKLQDQ(unsigned Opcode) {
16103 switch (Opcode) {
16104 case VPUNPCKLQDQYrm:
16105 case VPUNPCKLQDQYrr:
16106 case VPUNPCKLQDQZ128rm:
16107 case VPUNPCKLQDQZ128rmb:
16108 case VPUNPCKLQDQZ128rmbk:
16109 case VPUNPCKLQDQZ128rmbkz:
16110 case VPUNPCKLQDQZ128rmk:
16111 case VPUNPCKLQDQZ128rmkz:
16112 case VPUNPCKLQDQZ128rr:
16113 case VPUNPCKLQDQZ128rrk:
16114 case VPUNPCKLQDQZ128rrkz:
16115 case VPUNPCKLQDQZ256rm:
16116 case VPUNPCKLQDQZ256rmb:
16117 case VPUNPCKLQDQZ256rmbk:
16118 case VPUNPCKLQDQZ256rmbkz:
16119 case VPUNPCKLQDQZ256rmk:
16120 case VPUNPCKLQDQZ256rmkz:
16121 case VPUNPCKLQDQZ256rr:
16122 case VPUNPCKLQDQZ256rrk:
16123 case VPUNPCKLQDQZ256rrkz:
16124 case VPUNPCKLQDQZrm:
16125 case VPUNPCKLQDQZrmb:
16126 case VPUNPCKLQDQZrmbk:
16127 case VPUNPCKLQDQZrmbkz:
16128 case VPUNPCKLQDQZrmk:
16129 case VPUNPCKLQDQZrmkz:
16130 case VPUNPCKLQDQZrr:
16131 case VPUNPCKLQDQZrrk:
16132 case VPUNPCKLQDQZrrkz:
16133 case VPUNPCKLQDQrm:
16134 case VPUNPCKLQDQrr:
16135 return true;
16136 }
16137 return false;
16138}
16139
16140bool isVMMCALL(unsigned Opcode) {
16141 return Opcode == VMMCALL;
16142}
16143
16144bool isVCVTSH2SS(unsigned Opcode) {
16145 switch (Opcode) {
16146 case VCVTSH2SSZrm_Int:
16147 case VCVTSH2SSZrm_Intk:
16148 case VCVTSH2SSZrm_Intkz:
16149 case VCVTSH2SSZrr_Int:
16150 case VCVTSH2SSZrr_Intk:
16151 case VCVTSH2SSZrr_Intkz:
16152 case VCVTSH2SSZrrb_Int:
16153 case VCVTSH2SSZrrb_Intk:
16154 case VCVTSH2SSZrrb_Intkz:
16155 return true;
16156 }
16157 return false;
16158}
16159
16160bool isVPERMIL2PS(unsigned Opcode) {
16161 switch (Opcode) {
16162 case VPERMIL2PSYmr:
16163 case VPERMIL2PSYrm:
16164 case VPERMIL2PSYrr:
16165 case VPERMIL2PSYrr_REV:
16166 case VPERMIL2PSmr:
16167 case VPERMIL2PSrm:
16168 case VPERMIL2PSrr:
16169 case VPERMIL2PSrr_REV:
16170 return true;
16171 }
16172 return false;
16173}
16174
16175bool isVPCMPGTD(unsigned Opcode) {
16176 switch (Opcode) {
16177 case VPCMPGTDYrm:
16178 case VPCMPGTDYrr:
16179 case VPCMPGTDZ128rm:
16180 case VPCMPGTDZ128rmb:
16181 case VPCMPGTDZ128rmbk:
16182 case VPCMPGTDZ128rmk:
16183 case VPCMPGTDZ128rr:
16184 case VPCMPGTDZ128rrk:
16185 case VPCMPGTDZ256rm:
16186 case VPCMPGTDZ256rmb:
16187 case VPCMPGTDZ256rmbk:
16188 case VPCMPGTDZ256rmk:
16189 case VPCMPGTDZ256rr:
16190 case VPCMPGTDZ256rrk:
16191 case VPCMPGTDZrm:
16192 case VPCMPGTDZrmb:
16193 case VPCMPGTDZrmbk:
16194 case VPCMPGTDZrmk:
16195 case VPCMPGTDZrr:
16196 case VPCMPGTDZrrk:
16197 case VPCMPGTDrm:
16198 case VPCMPGTDrr:
16199 return true;
16200 }
16201 return false;
16202}
16203
16204bool isCMPXCHG16B(unsigned Opcode) {
16205 return Opcode == CMPXCHG16B;
16206}
16207
16208bool isVZEROUPPER(unsigned Opcode) {
16209 return Opcode == VZEROUPPER;
16210}
16211
16212bool isMOVAPS(unsigned Opcode) {
16213 switch (Opcode) {
16214 case MOVAPSmr:
16215 case MOVAPSrm:
16216 case MOVAPSrr:
16217 case MOVAPSrr_REV:
16218 return true;
16219 }
16220 return false;
16221}
16222
16223bool isVPCMPW(unsigned Opcode) {
16224 switch (Opcode) {
16225 case VPCMPWZ128rmi:
16226 case VPCMPWZ128rmik:
16227 case VPCMPWZ128rri:
16228 case VPCMPWZ128rrik:
16229 case VPCMPWZ256rmi:
16230 case VPCMPWZ256rmik:
16231 case VPCMPWZ256rri:
16232 case VPCMPWZ256rrik:
16233 case VPCMPWZrmi:
16234 case VPCMPWZrmik:
16235 case VPCMPWZrri:
16236 case VPCMPWZrrik:
16237 return true;
16238 }
16239 return false;
16240}
16241
16242bool isFUCOMPP(unsigned Opcode) {
16243 return Opcode == UCOM_FPPr;
16244}
16245
16246bool isXSETBV(unsigned Opcode) {
16247 return Opcode == XSETBV;
16248}
16249
16250bool isSLWPCB(unsigned Opcode) {
16251 switch (Opcode) {
16252 case SLWPCB:
16253 case SLWPCB64:
16254 return true;
16255 }
16256 return false;
16257}
16258
16259bool isSCASW(unsigned Opcode) {
16260 return Opcode == SCASW;
16261}
16262
16263bool isFCMOVNE(unsigned Opcode) {
16264 return Opcode == CMOVNE_F;
16265}
16266
16267bool isPBNDKB(unsigned Opcode) {
16268 return Opcode == PBNDKB;
16269}
16270
16271bool isVPMULLD(unsigned Opcode) {
16272 switch (Opcode) {
16273 case VPMULLDYrm:
16274 case VPMULLDYrr:
16275 case VPMULLDZ128rm:
16276 case VPMULLDZ128rmb:
16277 case VPMULLDZ128rmbk:
16278 case VPMULLDZ128rmbkz:
16279 case VPMULLDZ128rmk:
16280 case VPMULLDZ128rmkz:
16281 case VPMULLDZ128rr:
16282 case VPMULLDZ128rrk:
16283 case VPMULLDZ128rrkz:
16284 case VPMULLDZ256rm:
16285 case VPMULLDZ256rmb:
16286 case VPMULLDZ256rmbk:
16287 case VPMULLDZ256rmbkz:
16288 case VPMULLDZ256rmk:
16289 case VPMULLDZ256rmkz:
16290 case VPMULLDZ256rr:
16291 case VPMULLDZ256rrk:
16292 case VPMULLDZ256rrkz:
16293 case VPMULLDZrm:
16294 case VPMULLDZrmb:
16295 case VPMULLDZrmbk:
16296 case VPMULLDZrmbkz:
16297 case VPMULLDZrmk:
16298 case VPMULLDZrmkz:
16299 case VPMULLDZrr:
16300 case VPMULLDZrrk:
16301 case VPMULLDZrrkz:
16302 case VPMULLDrm:
16303 case VPMULLDrr:
16304 return true;
16305 }
16306 return false;
16307}
16308
16309bool isVP4DPWSSDS(unsigned Opcode) {
16310 switch (Opcode) {
16311 case VP4DPWSSDSrm:
16312 case VP4DPWSSDSrmk:
16313 case VP4DPWSSDSrmkz:
16314 return true;
16315 }
16316 return false;
16317}
16318
16319bool isPINSRW(unsigned Opcode) {
16320 switch (Opcode) {
16321 case MMX_PINSRWrm:
16322 case MMX_PINSRWrr:
16323 case PINSRWrm:
16324 case PINSRWrr:
16325 return true;
16326 }
16327 return false;
16328}
16329
16330bool isVCVTSI2SH(unsigned Opcode) {
16331 switch (Opcode) {
16332 case VCVTSI2SHZrm_Int:
16333 case VCVTSI2SHZrr_Int:
16334 case VCVTSI2SHZrrb_Int:
16335 case VCVTSI642SHZrm_Int:
16336 case VCVTSI642SHZrr_Int:
16337 case VCVTSI642SHZrrb_Int:
16338 return true;
16339 }
16340 return false;
16341}
16342
16343bool isVINSERTF32X8(unsigned Opcode) {
16344 switch (Opcode) {
16345 case VINSERTF32x8Zrm:
16346 case VINSERTF32x8Zrmk:
16347 case VINSERTF32x8Zrmkz:
16348 case VINSERTF32x8Zrr:
16349 case VINSERTF32x8Zrrk:
16350 case VINSERTF32x8Zrrkz:
16351 return true;
16352 }
16353 return false;
16354}
16355
16356bool isKSHIFTLB(unsigned Opcode) {
16357 return Opcode == KSHIFTLBri;
16358}
16359
16360bool isSEAMOPS(unsigned Opcode) {
16361 return Opcode == SEAMOPS;
16362}
16363
16364bool isVPMULUDQ(unsigned Opcode) {
16365 switch (Opcode) {
16366 case VPMULUDQYrm:
16367 case VPMULUDQYrr:
16368 case VPMULUDQZ128rm:
16369 case VPMULUDQZ128rmb:
16370 case VPMULUDQZ128rmbk:
16371 case VPMULUDQZ128rmbkz:
16372 case VPMULUDQZ128rmk:
16373 case VPMULUDQZ128rmkz:
16374 case VPMULUDQZ128rr:
16375 case VPMULUDQZ128rrk:
16376 case VPMULUDQZ128rrkz:
16377 case VPMULUDQZ256rm:
16378 case VPMULUDQZ256rmb:
16379 case VPMULUDQZ256rmbk:
16380 case VPMULUDQZ256rmbkz:
16381 case VPMULUDQZ256rmk:
16382 case VPMULUDQZ256rmkz:
16383 case VPMULUDQZ256rr:
16384 case VPMULUDQZ256rrk:
16385 case VPMULUDQZ256rrkz:
16386 case VPMULUDQZrm:
16387 case VPMULUDQZrmb:
16388 case VPMULUDQZrmbk:
16389 case VPMULUDQZrmbkz:
16390 case VPMULUDQZrmk:
16391 case VPMULUDQZrmkz:
16392 case VPMULUDQZrr:
16393 case VPMULUDQZrrk:
16394 case VPMULUDQZrrkz:
16395 case VPMULUDQrm:
16396 case VPMULUDQrr:
16397 return true;
16398 }
16399 return false;
16400}
16401
16402bool isVPMOVSQB(unsigned Opcode) {
16403 switch (Opcode) {
16404 case VPMOVSQBZ128mr:
16405 case VPMOVSQBZ128mrk:
16406 case VPMOVSQBZ128rr:
16407 case VPMOVSQBZ128rrk:
16408 case VPMOVSQBZ128rrkz:
16409 case VPMOVSQBZ256mr:
16410 case VPMOVSQBZ256mrk:
16411 case VPMOVSQBZ256rr:
16412 case VPMOVSQBZ256rrk:
16413 case VPMOVSQBZ256rrkz:
16414 case VPMOVSQBZmr:
16415 case VPMOVSQBZmrk:
16416 case VPMOVSQBZrr:
16417 case VPMOVSQBZrrk:
16418 case VPMOVSQBZrrkz:
16419 return true;
16420 }
16421 return false;
16422}
16423
16424bool isVPTESTMD(unsigned Opcode) {
16425 switch (Opcode) {
16426 case VPTESTMDZ128rm:
16427 case VPTESTMDZ128rmb:
16428 case VPTESTMDZ128rmbk:
16429 case VPTESTMDZ128rmk:
16430 case VPTESTMDZ128rr:
16431 case VPTESTMDZ128rrk:
16432 case VPTESTMDZ256rm:
16433 case VPTESTMDZ256rmb:
16434 case VPTESTMDZ256rmbk:
16435 case VPTESTMDZ256rmk:
16436 case VPTESTMDZ256rr:
16437 case VPTESTMDZ256rrk:
16438 case VPTESTMDZrm:
16439 case VPTESTMDZrmb:
16440 case VPTESTMDZrmbk:
16441 case VPTESTMDZrmk:
16442 case VPTESTMDZrr:
16443 case VPTESTMDZrrk:
16444 return true;
16445 }
16446 return false;
16447}
16448
16449bool isVPHADDDQ(unsigned Opcode) {
16450 switch (Opcode) {
16451 case VPHADDDQrm:
16452 case VPHADDDQrr:
16453 return true;
16454 }
16455 return false;
16456}
16457
16458bool isKUNPCKDQ(unsigned Opcode) {
16459 return Opcode == KUNPCKDQrr;
16460}
16461
16462bool isT1MSKC(unsigned Opcode) {
16463 switch (Opcode) {
16464 case T1MSKC32rm:
16465 case T1MSKC32rr:
16466 case T1MSKC64rm:
16467 case T1MSKC64rr:
16468 return true;
16469 }
16470 return false;
16471}
16472
16473bool isVPCOMB(unsigned Opcode) {
16474 switch (Opcode) {
16475 case VPCOMBmi:
16476 case VPCOMBri:
16477 return true;
16478 }
16479 return false;
16480}
16481
16482bool isVBLENDPS(unsigned Opcode) {
16483 switch (Opcode) {
16484 case VBLENDPSYrmi:
16485 case VBLENDPSYrri:
16486 case VBLENDPSrmi:
16487 case VBLENDPSrri:
16488 return true;
16489 }
16490 return false;
16491}
16492
16493bool isPTWRITE(unsigned Opcode) {
16494 switch (Opcode) {
16495 case PTWRITE64m:
16496 case PTWRITE64r:
16497 case PTWRITEm:
16498 case PTWRITEr:
16499 return true;
16500 }
16501 return false;
16502}
16503
16504bool isCVTPS2PI(unsigned Opcode) {
16505 switch (Opcode) {
16506 case MMX_CVTPS2PIrm:
16507 case MMX_CVTPS2PIrr:
16508 return true;
16509 }
16510 return false;
16511}
16512
16513bool isVPROTD(unsigned Opcode) {
16514 switch (Opcode) {
16515 case VPROTDmi:
16516 case VPROTDmr:
16517 case VPROTDri:
16518 case VPROTDrm:
16519 case VPROTDrr:
16520 case VPROTDrr_REV:
16521 return true;
16522 }
16523 return false;
16524}
16525
16526bool isCALL(unsigned Opcode) {
16527 switch (Opcode) {
16528 case CALL16m:
16529 case CALL16r:
16530 case CALL32m:
16531 case CALL32r:
16532 case CALL64m:
16533 case CALL64pcrel32:
16534 case CALL64r:
16535 case CALLpcrel16:
16536 case CALLpcrel32:
16537 case FARCALL32m:
16538 return true;
16539 }
16540 return false;
16541}
16542
16543bool isVPERMPS(unsigned Opcode) {
16544 switch (Opcode) {
16545 case VPERMPSYrm:
16546 case VPERMPSYrr:
16547 case VPERMPSZ256rm:
16548 case VPERMPSZ256rmb:
16549 case VPERMPSZ256rmbk:
16550 case VPERMPSZ256rmbkz:
16551 case VPERMPSZ256rmk:
16552 case VPERMPSZ256rmkz:
16553 case VPERMPSZ256rr:
16554 case VPERMPSZ256rrk:
16555 case VPERMPSZ256rrkz:
16556 case VPERMPSZrm:
16557 case VPERMPSZrmb:
16558 case VPERMPSZrmbk:
16559 case VPERMPSZrmbkz:
16560 case VPERMPSZrmk:
16561 case VPERMPSZrmkz:
16562 case VPERMPSZrr:
16563 case VPERMPSZrrk:
16564 case VPERMPSZrrkz:
16565 return true;
16566 }
16567 return false;
16568}
16569
16570bool isVPSHUFBITQMB(unsigned Opcode) {
16571 switch (Opcode) {
16572 case VPSHUFBITQMBZ128rm:
16573 case VPSHUFBITQMBZ128rmk:
16574 case VPSHUFBITQMBZ128rr:
16575 case VPSHUFBITQMBZ128rrk:
16576 case VPSHUFBITQMBZ256rm:
16577 case VPSHUFBITQMBZ256rmk:
16578 case VPSHUFBITQMBZ256rr:
16579 case VPSHUFBITQMBZ256rrk:
16580 case VPSHUFBITQMBZrm:
16581 case VPSHUFBITQMBZrmk:
16582 case VPSHUFBITQMBZrr:
16583 case VPSHUFBITQMBZrrk:
16584 return true;
16585 }
16586 return false;
16587}
16588
16589bool isVMOVSLDUP(unsigned Opcode) {
16590 switch (Opcode) {
16591 case VMOVSLDUPYrm:
16592 case VMOVSLDUPYrr:
16593 case VMOVSLDUPZ128rm:
16594 case VMOVSLDUPZ128rmk:
16595 case VMOVSLDUPZ128rmkz:
16596 case VMOVSLDUPZ128rr:
16597 case VMOVSLDUPZ128rrk:
16598 case VMOVSLDUPZ128rrkz:
16599 case VMOVSLDUPZ256rm:
16600 case VMOVSLDUPZ256rmk:
16601 case VMOVSLDUPZ256rmkz:
16602 case VMOVSLDUPZ256rr:
16603 case VMOVSLDUPZ256rrk:
16604 case VMOVSLDUPZ256rrkz:
16605 case VMOVSLDUPZrm:
16606 case VMOVSLDUPZrmk:
16607 case VMOVSLDUPZrmkz:
16608 case VMOVSLDUPZrr:
16609 case VMOVSLDUPZrrk:
16610 case VMOVSLDUPZrrkz:
16611 case VMOVSLDUPrm:
16612 case VMOVSLDUPrr:
16613 return true;
16614 }
16615 return false;
16616}
16617
16618bool isINVLPGA(unsigned Opcode) {
16619 switch (Opcode) {
16620 case INVLPGA32:
16621 case INVLPGA64:
16622 return true;
16623 }
16624 return false;
16625}
16626
16627bool isVCVTPH2QQ(unsigned Opcode) {
16628 switch (Opcode) {
16629 case VCVTPH2QQZ128rm:
16630 case VCVTPH2QQZ128rmb:
16631 case VCVTPH2QQZ128rmbk:
16632 case VCVTPH2QQZ128rmbkz:
16633 case VCVTPH2QQZ128rmk:
16634 case VCVTPH2QQZ128rmkz:
16635 case VCVTPH2QQZ128rr:
16636 case VCVTPH2QQZ128rrk:
16637 case VCVTPH2QQZ128rrkz:
16638 case VCVTPH2QQZ256rm:
16639 case VCVTPH2QQZ256rmb:
16640 case VCVTPH2QQZ256rmbk:
16641 case VCVTPH2QQZ256rmbkz:
16642 case VCVTPH2QQZ256rmk:
16643 case VCVTPH2QQZ256rmkz:
16644 case VCVTPH2QQZ256rr:
16645 case VCVTPH2QQZ256rrk:
16646 case VCVTPH2QQZ256rrkz:
16647 case VCVTPH2QQZrm:
16648 case VCVTPH2QQZrmb:
16649 case VCVTPH2QQZrmbk:
16650 case VCVTPH2QQZrmbkz:
16651 case VCVTPH2QQZrmk:
16652 case VCVTPH2QQZrmkz:
16653 case VCVTPH2QQZrr:
16654 case VCVTPH2QQZrrb:
16655 case VCVTPH2QQZrrbk:
16656 case VCVTPH2QQZrrbkz:
16657 case VCVTPH2QQZrrk:
16658 case VCVTPH2QQZrrkz:
16659 return true;
16660 }
16661 return false;
16662}
16663
16664bool isADD(unsigned Opcode) {
16665 switch (Opcode) {
16666 case ADD16i16:
16667 case ADD16mi:
16668 case ADD16mi8:
16669 case ADD16mi8_EVEX:
16670 case ADD16mi8_ND:
16671 case ADD16mi8_NF:
16672 case ADD16mi8_NF_ND:
16673 case ADD16mi_EVEX:
16674 case ADD16mi_ND:
16675 case ADD16mi_NF:
16676 case ADD16mi_NF_ND:
16677 case ADD16mr:
16678 case ADD16mr_EVEX:
16679 case ADD16mr_ND:
16680 case ADD16mr_NF:
16681 case ADD16mr_NF_ND:
16682 case ADD16ri:
16683 case ADD16ri8:
16684 case ADD16ri8_EVEX:
16685 case ADD16ri8_ND:
16686 case ADD16ri8_NF:
16687 case ADD16ri8_NF_ND:
16688 case ADD16ri_EVEX:
16689 case ADD16ri_ND:
16690 case ADD16ri_NF:
16691 case ADD16ri_NF_ND:
16692 case ADD16rm:
16693 case ADD16rm_EVEX:
16694 case ADD16rm_ND:
16695 case ADD16rm_NF:
16696 case ADD16rm_NF_ND:
16697 case ADD16rr:
16698 case ADD16rr_EVEX:
16699 case ADD16rr_EVEX_REV:
16700 case ADD16rr_ND:
16701 case ADD16rr_ND_REV:
16702 case ADD16rr_NF:
16703 case ADD16rr_NF_ND:
16704 case ADD16rr_NF_ND_REV:
16705 case ADD16rr_NF_REV:
16706 case ADD16rr_REV:
16707 case ADD32i32:
16708 case ADD32mi:
16709 case ADD32mi8:
16710 case ADD32mi8_EVEX:
16711 case ADD32mi8_ND:
16712 case ADD32mi8_NF:
16713 case ADD32mi8_NF_ND:
16714 case ADD32mi_EVEX:
16715 case ADD32mi_ND:
16716 case ADD32mi_NF:
16717 case ADD32mi_NF_ND:
16718 case ADD32mr:
16719 case ADD32mr_EVEX:
16720 case ADD32mr_ND:
16721 case ADD32mr_NF:
16722 case ADD32mr_NF_ND:
16723 case ADD32ri:
16724 case ADD32ri8:
16725 case ADD32ri8_EVEX:
16726 case ADD32ri8_ND:
16727 case ADD32ri8_NF:
16728 case ADD32ri8_NF_ND:
16729 case ADD32ri_EVEX:
16730 case ADD32ri_ND:
16731 case ADD32ri_NF:
16732 case ADD32ri_NF_ND:
16733 case ADD32rm:
16734 case ADD32rm_EVEX:
16735 case ADD32rm_ND:
16736 case ADD32rm_NF:
16737 case ADD32rm_NF_ND:
16738 case ADD32rr:
16739 case ADD32rr_EVEX:
16740 case ADD32rr_EVEX_REV:
16741 case ADD32rr_ND:
16742 case ADD32rr_ND_REV:
16743 case ADD32rr_NF:
16744 case ADD32rr_NF_ND:
16745 case ADD32rr_NF_ND_REV:
16746 case ADD32rr_NF_REV:
16747 case ADD32rr_REV:
16748 case ADD64i32:
16749 case ADD64mi32:
16750 case ADD64mi32_EVEX:
16751 case ADD64mi32_ND:
16752 case ADD64mi32_NF:
16753 case ADD64mi32_NF_ND:
16754 case ADD64mi8:
16755 case ADD64mi8_EVEX:
16756 case ADD64mi8_ND:
16757 case ADD64mi8_NF:
16758 case ADD64mi8_NF_ND:
16759 case ADD64mr:
16760 case ADD64mr_EVEX:
16761 case ADD64mr_ND:
16762 case ADD64mr_NF:
16763 case ADD64mr_NF_ND:
16764 case ADD64ri32:
16765 case ADD64ri32_EVEX:
16766 case ADD64ri32_ND:
16767 case ADD64ri32_NF:
16768 case ADD64ri32_NF_ND:
16769 case ADD64ri8:
16770 case ADD64ri8_EVEX:
16771 case ADD64ri8_ND:
16772 case ADD64ri8_NF:
16773 case ADD64ri8_NF_ND:
16774 case ADD64rm:
16775 case ADD64rm_EVEX:
16776 case ADD64rm_ND:
16777 case ADD64rm_NF:
16778 case ADD64rm_NF_ND:
16779 case ADD64rr:
16780 case ADD64rr_EVEX:
16781 case ADD64rr_EVEX_REV:
16782 case ADD64rr_ND:
16783 case ADD64rr_ND_REV:
16784 case ADD64rr_NF:
16785 case ADD64rr_NF_ND:
16786 case ADD64rr_NF_ND_REV:
16787 case ADD64rr_NF_REV:
16788 case ADD64rr_REV:
16789 case ADD8i8:
16790 case ADD8mi:
16791 case ADD8mi8:
16792 case ADD8mi_EVEX:
16793 case ADD8mi_ND:
16794 case ADD8mi_NF:
16795 case ADD8mi_NF_ND:
16796 case ADD8mr:
16797 case ADD8mr_EVEX:
16798 case ADD8mr_ND:
16799 case ADD8mr_NF:
16800 case ADD8mr_NF_ND:
16801 case ADD8ri:
16802 case ADD8ri8:
16803 case ADD8ri_EVEX:
16804 case ADD8ri_ND:
16805 case ADD8ri_NF:
16806 case ADD8ri_NF_ND:
16807 case ADD8rm:
16808 case ADD8rm_EVEX:
16809 case ADD8rm_ND:
16810 case ADD8rm_NF:
16811 case ADD8rm_NF_ND:
16812 case ADD8rr:
16813 case ADD8rr_EVEX:
16814 case ADD8rr_EVEX_REV:
16815 case ADD8rr_ND:
16816 case ADD8rr_ND_REV:
16817 case ADD8rr_NF:
16818 case ADD8rr_NF_ND:
16819 case ADD8rr_NF_ND_REV:
16820 case ADD8rr_NF_REV:
16821 case ADD8rr_REV:
16822 return true;
16823 }
16824 return false;
16825}
16826
16827bool isPSUBSW(unsigned Opcode) {
16828 switch (Opcode) {
16829 case MMX_PSUBSWrm:
16830 case MMX_PSUBSWrr:
16831 case PSUBSWrm:
16832 case PSUBSWrr:
16833 return true;
16834 }
16835 return false;
16836}
16837
16838bool isSIDTW(unsigned Opcode) {
16839 return Opcode == SIDT16m;
16840}
16841
16842bool isVFNMADD231PH(unsigned Opcode) {
16843 switch (Opcode) {
16844 case VFNMADD231PHZ128m:
16845 case VFNMADD231PHZ128mb:
16846 case VFNMADD231PHZ128mbk:
16847 case VFNMADD231PHZ128mbkz:
16848 case VFNMADD231PHZ128mk:
16849 case VFNMADD231PHZ128mkz:
16850 case VFNMADD231PHZ128r:
16851 case VFNMADD231PHZ128rk:
16852 case VFNMADD231PHZ128rkz:
16853 case VFNMADD231PHZ256m:
16854 case VFNMADD231PHZ256mb:
16855 case VFNMADD231PHZ256mbk:
16856 case VFNMADD231PHZ256mbkz:
16857 case VFNMADD231PHZ256mk:
16858 case VFNMADD231PHZ256mkz:
16859 case VFNMADD231PHZ256r:
16860 case VFNMADD231PHZ256rk:
16861 case VFNMADD231PHZ256rkz:
16862 case VFNMADD231PHZm:
16863 case VFNMADD231PHZmb:
16864 case VFNMADD231PHZmbk:
16865 case VFNMADD231PHZmbkz:
16866 case VFNMADD231PHZmk:
16867 case VFNMADD231PHZmkz:
16868 case VFNMADD231PHZr:
16869 case VFNMADD231PHZrb:
16870 case VFNMADD231PHZrbk:
16871 case VFNMADD231PHZrbkz:
16872 case VFNMADD231PHZrk:
16873 case VFNMADD231PHZrkz:
16874 return true;
16875 }
16876 return false;
16877}
16878
16879bool isVEXTRACTF64X2(unsigned Opcode) {
16880 switch (Opcode) {
16881 case VEXTRACTF64x2Z256mr:
16882 case VEXTRACTF64x2Z256mrk:
16883 case VEXTRACTF64x2Z256rr:
16884 case VEXTRACTF64x2Z256rrk:
16885 case VEXTRACTF64x2Z256rrkz:
16886 case VEXTRACTF64x2Zmr:
16887 case VEXTRACTF64x2Zmrk:
16888 case VEXTRACTF64x2Zrr:
16889 case VEXTRACTF64x2Zrrk:
16890 case VEXTRACTF64x2Zrrkz:
16891 return true;
16892 }
16893 return false;
16894}
16895
16896bool isFCOMI(unsigned Opcode) {
16897 return Opcode == COM_FIr;
16898}
16899
16900bool isRSM(unsigned Opcode) {
16901 return Opcode == RSM;
16902}
16903
16904bool isVPCOMUD(unsigned Opcode) {
16905 switch (Opcode) {
16906 case VPCOMUDmi:
16907 case VPCOMUDri:
16908 return true;
16909 }
16910 return false;
16911}
16912
16913bool isVPMOVZXBQ(unsigned Opcode) {
16914 switch (Opcode) {
16915 case VPMOVZXBQYrm:
16916 case VPMOVZXBQYrr:
16917 case VPMOVZXBQZ128rm:
16918 case VPMOVZXBQZ128rmk:
16919 case VPMOVZXBQZ128rmkz:
16920 case VPMOVZXBQZ128rr:
16921 case VPMOVZXBQZ128rrk:
16922 case VPMOVZXBQZ128rrkz:
16923 case VPMOVZXBQZ256rm:
16924 case VPMOVZXBQZ256rmk:
16925 case VPMOVZXBQZ256rmkz:
16926 case VPMOVZXBQZ256rr:
16927 case VPMOVZXBQZ256rrk:
16928 case VPMOVZXBQZ256rrkz:
16929 case VPMOVZXBQZrm:
16930 case VPMOVZXBQZrmk:
16931 case VPMOVZXBQZrmkz:
16932 case VPMOVZXBQZrr:
16933 case VPMOVZXBQZrrk:
16934 case VPMOVZXBQZrrkz:
16935 case VPMOVZXBQrm:
16936 case VPMOVZXBQrr:
16937 return true;
16938 }
16939 return false;
16940}
16941
16942bool isUWRMSR(unsigned Opcode) {
16943 switch (Opcode) {
16944 case UWRMSRir:
16945 case UWRMSRir_EVEX:
16946 case UWRMSRrr:
16947 case UWRMSRrr_EVEX:
16948 return true;
16949 }
16950 return false;
16951}
16952
16953bool isLGS(unsigned Opcode) {
16954 switch (Opcode) {
16955 case LGS16rm:
16956 case LGS32rm:
16957 case LGS64rm:
16958 return true;
16959 }
16960 return false;
16961}
16962
16963bool isVMOVNTPD(unsigned Opcode) {
16964 switch (Opcode) {
16965 case VMOVNTPDYmr:
16966 case VMOVNTPDZ128mr:
16967 case VMOVNTPDZ256mr:
16968 case VMOVNTPDZmr:
16969 case VMOVNTPDmr:
16970 return true;
16971 }
16972 return false;
16973}
16974
16975bool isRDPRU(unsigned Opcode) {
16976 return Opcode == RDPRU;
16977}
16978
16979bool isVPUNPCKHBW(unsigned Opcode) {
16980 switch (Opcode) {
16981 case VPUNPCKHBWYrm:
16982 case VPUNPCKHBWYrr:
16983 case VPUNPCKHBWZ128rm:
16984 case VPUNPCKHBWZ128rmk:
16985 case VPUNPCKHBWZ128rmkz:
16986 case VPUNPCKHBWZ128rr:
16987 case VPUNPCKHBWZ128rrk:
16988 case VPUNPCKHBWZ128rrkz:
16989 case VPUNPCKHBWZ256rm:
16990 case VPUNPCKHBWZ256rmk:
16991 case VPUNPCKHBWZ256rmkz:
16992 case VPUNPCKHBWZ256rr:
16993 case VPUNPCKHBWZ256rrk:
16994 case VPUNPCKHBWZ256rrkz:
16995 case VPUNPCKHBWZrm:
16996 case VPUNPCKHBWZrmk:
16997 case VPUNPCKHBWZrmkz:
16998 case VPUNPCKHBWZrr:
16999 case VPUNPCKHBWZrrk:
17000 case VPUNPCKHBWZrrkz:
17001 case VPUNPCKHBWrm:
17002 case VPUNPCKHBWrr:
17003 return true;
17004 }
17005 return false;
17006}
17007
17008bool isANDN(unsigned Opcode) {
17009 switch (Opcode) {
17010 case ANDN32rm:
17011 case ANDN32rm_EVEX:
17012 case ANDN32rm_NF:
17013 case ANDN32rr:
17014 case ANDN32rr_EVEX:
17015 case ANDN32rr_NF:
17016 case ANDN64rm:
17017 case ANDN64rm_EVEX:
17018 case ANDN64rm_NF:
17019 case ANDN64rr:
17020 case ANDN64rr_EVEX:
17021 case ANDN64rr_NF:
17022 return true;
17023 }
17024 return false;
17025}
17026
17027bool isVCVTTPH2UW(unsigned Opcode) {
17028 switch (Opcode) {
17029 case VCVTTPH2UWZ128rm:
17030 case VCVTTPH2UWZ128rmb:
17031 case VCVTTPH2UWZ128rmbk:
17032 case VCVTTPH2UWZ128rmbkz:
17033 case VCVTTPH2UWZ128rmk:
17034 case VCVTTPH2UWZ128rmkz:
17035 case VCVTTPH2UWZ128rr:
17036 case VCVTTPH2UWZ128rrk:
17037 case VCVTTPH2UWZ128rrkz:
17038 case VCVTTPH2UWZ256rm:
17039 case VCVTTPH2UWZ256rmb:
17040 case VCVTTPH2UWZ256rmbk:
17041 case VCVTTPH2UWZ256rmbkz:
17042 case VCVTTPH2UWZ256rmk:
17043 case VCVTTPH2UWZ256rmkz:
17044 case VCVTTPH2UWZ256rr:
17045 case VCVTTPH2UWZ256rrk:
17046 case VCVTTPH2UWZ256rrkz:
17047 case VCVTTPH2UWZrm:
17048 case VCVTTPH2UWZrmb:
17049 case VCVTTPH2UWZrmbk:
17050 case VCVTTPH2UWZrmbkz:
17051 case VCVTTPH2UWZrmk:
17052 case VCVTTPH2UWZrmkz:
17053 case VCVTTPH2UWZrr:
17054 case VCVTTPH2UWZrrb:
17055 case VCVTTPH2UWZrrbk:
17056 case VCVTTPH2UWZrrbkz:
17057 case VCVTTPH2UWZrrk:
17058 case VCVTTPH2UWZrrkz:
17059 return true;
17060 }
17061 return false;
17062}
17063
17064bool isVMFUNC(unsigned Opcode) {
17065 return Opcode == VMFUNC;
17066}
17067
17068bool isFIMUL(unsigned Opcode) {
17069 switch (Opcode) {
17070 case MUL_FI16m:
17071 case MUL_FI32m:
17072 return true;
17073 }
17074 return false;
17075}
17076
17077bool isBLCFILL(unsigned Opcode) {
17078 switch (Opcode) {
17079 case BLCFILL32rm:
17080 case BLCFILL32rr:
17081 case BLCFILL64rm:
17082 case BLCFILL64rr:
17083 return true;
17084 }
17085 return false;
17086}
17087
17088bool isVGATHERPF0DPS(unsigned Opcode) {
17089 return Opcode == VGATHERPF0DPSm;
17090}
17091
17092bool isVFMSUBADD231PS(unsigned Opcode) {
17093 switch (Opcode) {
17094 case VFMSUBADD231PSYm:
17095 case VFMSUBADD231PSYr:
17096 case VFMSUBADD231PSZ128m:
17097 case VFMSUBADD231PSZ128mb:
17098 case VFMSUBADD231PSZ128mbk:
17099 case VFMSUBADD231PSZ128mbkz:
17100 case VFMSUBADD231PSZ128mk:
17101 case VFMSUBADD231PSZ128mkz:
17102 case VFMSUBADD231PSZ128r:
17103 case VFMSUBADD231PSZ128rk:
17104 case VFMSUBADD231PSZ128rkz:
17105 case VFMSUBADD231PSZ256m:
17106 case VFMSUBADD231PSZ256mb:
17107 case VFMSUBADD231PSZ256mbk:
17108 case VFMSUBADD231PSZ256mbkz:
17109 case VFMSUBADD231PSZ256mk:
17110 case VFMSUBADD231PSZ256mkz:
17111 case VFMSUBADD231PSZ256r:
17112 case VFMSUBADD231PSZ256rk:
17113 case VFMSUBADD231PSZ256rkz:
17114 case VFMSUBADD231PSZm:
17115 case VFMSUBADD231PSZmb:
17116 case VFMSUBADD231PSZmbk:
17117 case VFMSUBADD231PSZmbkz:
17118 case VFMSUBADD231PSZmk:
17119 case VFMSUBADD231PSZmkz:
17120 case VFMSUBADD231PSZr:
17121 case VFMSUBADD231PSZrb:
17122 case VFMSUBADD231PSZrbk:
17123 case VFMSUBADD231PSZrbkz:
17124 case VFMSUBADD231PSZrk:
17125 case VFMSUBADD231PSZrkz:
17126 case VFMSUBADD231PSm:
17127 case VFMSUBADD231PSr:
17128 return true;
17129 }
17130 return false;
17131}
17132
17133bool isVREDUCESD(unsigned Opcode) {
17134 switch (Opcode) {
17135 case VREDUCESDZrmi:
17136 case VREDUCESDZrmik:
17137 case VREDUCESDZrmikz:
17138 case VREDUCESDZrri:
17139 case VREDUCESDZrrib:
17140 case VREDUCESDZrribk:
17141 case VREDUCESDZrribkz:
17142 case VREDUCESDZrrik:
17143 case VREDUCESDZrrikz:
17144 return true;
17145 }
17146 return false;
17147}
17148
17149bool isVXORPS(unsigned Opcode) {
17150 switch (Opcode) {
17151 case VXORPSYrm:
17152 case VXORPSYrr:
17153 case VXORPSZ128rm:
17154 case VXORPSZ128rmb:
17155 case VXORPSZ128rmbk:
17156 case VXORPSZ128rmbkz:
17157 case VXORPSZ128rmk:
17158 case VXORPSZ128rmkz:
17159 case VXORPSZ128rr:
17160 case VXORPSZ128rrk:
17161 case VXORPSZ128rrkz:
17162 case VXORPSZ256rm:
17163 case VXORPSZ256rmb:
17164 case VXORPSZ256rmbk:
17165 case VXORPSZ256rmbkz:
17166 case VXORPSZ256rmk:
17167 case VXORPSZ256rmkz:
17168 case VXORPSZ256rr:
17169 case VXORPSZ256rrk:
17170 case VXORPSZ256rrkz:
17171 case VXORPSZrm:
17172 case VXORPSZrmb:
17173 case VXORPSZrmbk:
17174 case VXORPSZrmbkz:
17175 case VXORPSZrmk:
17176 case VXORPSZrmkz:
17177 case VXORPSZrr:
17178 case VXORPSZrrk:
17179 case VXORPSZrrkz:
17180 case VXORPSrm:
17181 case VXORPSrr:
17182 return true;
17183 }
17184 return false;
17185}
17186
17187bool isPSWAPD(unsigned Opcode) {
17188 switch (Opcode) {
17189 case PSWAPDrm:
17190 case PSWAPDrr:
17191 return true;
17192 }
17193 return false;
17194}
17195
17196bool isPMAXSD(unsigned Opcode) {
17197 switch (Opcode) {
17198 case PMAXSDrm:
17199 case PMAXSDrr:
17200 return true;
17201 }
17202 return false;
17203}
17204
17205bool isVCMPSS(unsigned Opcode) {
17206 switch (Opcode) {
17207 case VCMPSSZrmi_Int:
17208 case VCMPSSZrmi_Intk:
17209 case VCMPSSZrri_Int:
17210 case VCMPSSZrri_Intk:
17211 case VCMPSSZrrib_Int:
17212 case VCMPSSZrrib_Intk:
17213 case VCMPSSrmi_Int:
17214 case VCMPSSrri_Int:
17215 return true;
17216 }
17217 return false;
17218}
17219
17220bool isEXTRACTPS(unsigned Opcode) {
17221 switch (Opcode) {
17222 case EXTRACTPSmr:
17223 case EXTRACTPSrr:
17224 return true;
17225 }
17226 return false;
17227}
17228
17229bool isVPMOVZXBD(unsigned Opcode) {
17230 switch (Opcode) {
17231 case VPMOVZXBDYrm:
17232 case VPMOVZXBDYrr:
17233 case VPMOVZXBDZ128rm:
17234 case VPMOVZXBDZ128rmk:
17235 case VPMOVZXBDZ128rmkz:
17236 case VPMOVZXBDZ128rr:
17237 case VPMOVZXBDZ128rrk:
17238 case VPMOVZXBDZ128rrkz:
17239 case VPMOVZXBDZ256rm:
17240 case VPMOVZXBDZ256rmk:
17241 case VPMOVZXBDZ256rmkz:
17242 case VPMOVZXBDZ256rr:
17243 case VPMOVZXBDZ256rrk:
17244 case VPMOVZXBDZ256rrkz:
17245 case VPMOVZXBDZrm:
17246 case VPMOVZXBDZrmk:
17247 case VPMOVZXBDZrmkz:
17248 case VPMOVZXBDZrr:
17249 case VPMOVZXBDZrrk:
17250 case VPMOVZXBDZrrkz:
17251 case VPMOVZXBDrm:
17252 case VPMOVZXBDrr:
17253 return true;
17254 }
17255 return false;
17256}
17257
17258bool isOUTSW(unsigned Opcode) {
17259 return Opcode == OUTSW;
17260}
17261
17262bool isKORTESTB(unsigned Opcode) {
17263 return Opcode == KORTESTBrr;
17264}
17265
17266bool isVREDUCEPS(unsigned Opcode) {
17267 switch (Opcode) {
17268 case VREDUCEPSZ128rmbi:
17269 case VREDUCEPSZ128rmbik:
17270 case VREDUCEPSZ128rmbikz:
17271 case VREDUCEPSZ128rmi:
17272 case VREDUCEPSZ128rmik:
17273 case VREDUCEPSZ128rmikz:
17274 case VREDUCEPSZ128rri:
17275 case VREDUCEPSZ128rrik:
17276 case VREDUCEPSZ128rrikz:
17277 case VREDUCEPSZ256rmbi:
17278 case VREDUCEPSZ256rmbik:
17279 case VREDUCEPSZ256rmbikz:
17280 case VREDUCEPSZ256rmi:
17281 case VREDUCEPSZ256rmik:
17282 case VREDUCEPSZ256rmikz:
17283 case VREDUCEPSZ256rri:
17284 case VREDUCEPSZ256rrik:
17285 case VREDUCEPSZ256rrikz:
17286 case VREDUCEPSZrmbi:
17287 case VREDUCEPSZrmbik:
17288 case VREDUCEPSZrmbikz:
17289 case VREDUCEPSZrmi:
17290 case VREDUCEPSZrmik:
17291 case VREDUCEPSZrmikz:
17292 case VREDUCEPSZrri:
17293 case VREDUCEPSZrrib:
17294 case VREDUCEPSZrribk:
17295 case VREDUCEPSZrribkz:
17296 case VREDUCEPSZrrik:
17297 case VREDUCEPSZrrikz:
17298 return true;
17299 }
17300 return false;
17301}
17302
17303bool isPEXTRW(unsigned Opcode) {
17304 switch (Opcode) {
17305 case MMX_PEXTRWrr:
17306 case PEXTRWmr:
17307 case PEXTRWrr:
17308 case PEXTRWrr_REV:
17309 return true;
17310 }
17311 return false;
17312}
17313
17314bool isFNINIT(unsigned Opcode) {
17315 return Opcode == FNINIT;
17316}
17317
17318bool isROL(unsigned Opcode) {
17319 switch (Opcode) {
17320 case ROL16m1:
17321 case ROL16m1_EVEX:
17322 case ROL16m1_ND:
17323 case ROL16m1_NF:
17324 case ROL16m1_NF_ND:
17325 case ROL16mCL:
17326 case ROL16mCL_EVEX:
17327 case ROL16mCL_ND:
17328 case ROL16mCL_NF:
17329 case ROL16mCL_NF_ND:
17330 case ROL16mi:
17331 case ROL16mi_EVEX:
17332 case ROL16mi_ND:
17333 case ROL16mi_NF:
17334 case ROL16mi_NF_ND:
17335 case ROL16r1:
17336 case ROL16r1_EVEX:
17337 case ROL16r1_ND:
17338 case ROL16r1_NF:
17339 case ROL16r1_NF_ND:
17340 case ROL16rCL:
17341 case ROL16rCL_EVEX:
17342 case ROL16rCL_ND:
17343 case ROL16rCL_NF:
17344 case ROL16rCL_NF_ND:
17345 case ROL16ri:
17346 case ROL16ri_EVEX:
17347 case ROL16ri_ND:
17348 case ROL16ri_NF:
17349 case ROL16ri_NF_ND:
17350 case ROL32m1:
17351 case ROL32m1_EVEX:
17352 case ROL32m1_ND:
17353 case ROL32m1_NF:
17354 case ROL32m1_NF_ND:
17355 case ROL32mCL:
17356 case ROL32mCL_EVEX:
17357 case ROL32mCL_ND:
17358 case ROL32mCL_NF:
17359 case ROL32mCL_NF_ND:
17360 case ROL32mi:
17361 case ROL32mi_EVEX:
17362 case ROL32mi_ND:
17363 case ROL32mi_NF:
17364 case ROL32mi_NF_ND:
17365 case ROL32r1:
17366 case ROL32r1_EVEX:
17367 case ROL32r1_ND:
17368 case ROL32r1_NF:
17369 case ROL32r1_NF_ND:
17370 case ROL32rCL:
17371 case ROL32rCL_EVEX:
17372 case ROL32rCL_ND:
17373 case ROL32rCL_NF:
17374 case ROL32rCL_NF_ND:
17375 case ROL32ri:
17376 case ROL32ri_EVEX:
17377 case ROL32ri_ND:
17378 case ROL32ri_NF:
17379 case ROL32ri_NF_ND:
17380 case ROL64m1:
17381 case ROL64m1_EVEX:
17382 case ROL64m1_ND:
17383 case ROL64m1_NF:
17384 case ROL64m1_NF_ND:
17385 case ROL64mCL:
17386 case ROL64mCL_EVEX:
17387 case ROL64mCL_ND:
17388 case ROL64mCL_NF:
17389 case ROL64mCL_NF_ND:
17390 case ROL64mi:
17391 case ROL64mi_EVEX:
17392 case ROL64mi_ND:
17393 case ROL64mi_NF:
17394 case ROL64mi_NF_ND:
17395 case ROL64r1:
17396 case ROL64r1_EVEX:
17397 case ROL64r1_ND:
17398 case ROL64r1_NF:
17399 case ROL64r1_NF_ND:
17400 case ROL64rCL:
17401 case ROL64rCL_EVEX:
17402 case ROL64rCL_ND:
17403 case ROL64rCL_NF:
17404 case ROL64rCL_NF_ND:
17405 case ROL64ri:
17406 case ROL64ri_EVEX:
17407 case ROL64ri_ND:
17408 case ROL64ri_NF:
17409 case ROL64ri_NF_ND:
17410 case ROL8m1:
17411 case ROL8m1_EVEX:
17412 case ROL8m1_ND:
17413 case ROL8m1_NF:
17414 case ROL8m1_NF_ND:
17415 case ROL8mCL:
17416 case ROL8mCL_EVEX:
17417 case ROL8mCL_ND:
17418 case ROL8mCL_NF:
17419 case ROL8mCL_NF_ND:
17420 case ROL8mi:
17421 case ROL8mi_EVEX:
17422 case ROL8mi_ND:
17423 case ROL8mi_NF:
17424 case ROL8mi_NF_ND:
17425 case ROL8r1:
17426 case ROL8r1_EVEX:
17427 case ROL8r1_ND:
17428 case ROL8r1_NF:
17429 case ROL8r1_NF_ND:
17430 case ROL8rCL:
17431 case ROL8rCL_EVEX:
17432 case ROL8rCL_ND:
17433 case ROL8rCL_NF:
17434 case ROL8rCL_NF_ND:
17435 case ROL8ri:
17436 case ROL8ri_EVEX:
17437 case ROL8ri_ND:
17438 case ROL8ri_NF:
17439 case ROL8ri_NF_ND:
17440 return true;
17441 }
17442 return false;
17443}
17444
17445bool isVCVTPS2QQ(unsigned Opcode) {
17446 switch (Opcode) {
17447 case VCVTPS2QQZ128rm:
17448 case VCVTPS2QQZ128rmb:
17449 case VCVTPS2QQZ128rmbk:
17450 case VCVTPS2QQZ128rmbkz:
17451 case VCVTPS2QQZ128rmk:
17452 case VCVTPS2QQZ128rmkz:
17453 case VCVTPS2QQZ128rr:
17454 case VCVTPS2QQZ128rrk:
17455 case VCVTPS2QQZ128rrkz:
17456 case VCVTPS2QQZ256rm:
17457 case VCVTPS2QQZ256rmb:
17458 case VCVTPS2QQZ256rmbk:
17459 case VCVTPS2QQZ256rmbkz:
17460 case VCVTPS2QQZ256rmk:
17461 case VCVTPS2QQZ256rmkz:
17462 case VCVTPS2QQZ256rr:
17463 case VCVTPS2QQZ256rrk:
17464 case VCVTPS2QQZ256rrkz:
17465 case VCVTPS2QQZrm:
17466 case VCVTPS2QQZrmb:
17467 case VCVTPS2QQZrmbk:
17468 case VCVTPS2QQZrmbkz:
17469 case VCVTPS2QQZrmk:
17470 case VCVTPS2QQZrmkz:
17471 case VCVTPS2QQZrr:
17472 case VCVTPS2QQZrrb:
17473 case VCVTPS2QQZrrbk:
17474 case VCVTPS2QQZrrbkz:
17475 case VCVTPS2QQZrrk:
17476 case VCVTPS2QQZrrkz:
17477 return true;
17478 }
17479 return false;
17480}
17481
17482bool isVGETMANTPH(unsigned Opcode) {
17483 switch (Opcode) {
17484 case VGETMANTPHZ128rmbi:
17485 case VGETMANTPHZ128rmbik:
17486 case VGETMANTPHZ128rmbikz:
17487 case VGETMANTPHZ128rmi:
17488 case VGETMANTPHZ128rmik:
17489 case VGETMANTPHZ128rmikz:
17490 case VGETMANTPHZ128rri:
17491 case VGETMANTPHZ128rrik:
17492 case VGETMANTPHZ128rrikz:
17493 case VGETMANTPHZ256rmbi:
17494 case VGETMANTPHZ256rmbik:
17495 case VGETMANTPHZ256rmbikz:
17496 case VGETMANTPHZ256rmi:
17497 case VGETMANTPHZ256rmik:
17498 case VGETMANTPHZ256rmikz:
17499 case VGETMANTPHZ256rri:
17500 case VGETMANTPHZ256rrik:
17501 case VGETMANTPHZ256rrikz:
17502 case VGETMANTPHZrmbi:
17503 case VGETMANTPHZrmbik:
17504 case VGETMANTPHZrmbikz:
17505 case VGETMANTPHZrmi:
17506 case VGETMANTPHZrmik:
17507 case VGETMANTPHZrmikz:
17508 case VGETMANTPHZrri:
17509 case VGETMANTPHZrrib:
17510 case VGETMANTPHZrribk:
17511 case VGETMANTPHZrribkz:
17512 case VGETMANTPHZrrik:
17513 case VGETMANTPHZrrikz:
17514 return true;
17515 }
17516 return false;
17517}
17518
17519bool isPUNPCKLDQ(unsigned Opcode) {
17520 switch (Opcode) {
17521 case MMX_PUNPCKLDQrm:
17522 case MMX_PUNPCKLDQrr:
17523 case PUNPCKLDQrm:
17524 case PUNPCKLDQrr:
17525 return true;
17526 }
17527 return false;
17528}
17529
17530bool isPADDD(unsigned Opcode) {
17531 switch (Opcode) {
17532 case MMX_PADDDrm:
17533 case MMX_PADDDrr:
17534 case PADDDrm:
17535 case PADDDrr:
17536 return true;
17537 }
17538 return false;
17539}
17540
17541bool isVPSLLD(unsigned Opcode) {
17542 switch (Opcode) {
17543 case VPSLLDYri:
17544 case VPSLLDYrm:
17545 case VPSLLDYrr:
17546 case VPSLLDZ128mbi:
17547 case VPSLLDZ128mbik:
17548 case VPSLLDZ128mbikz:
17549 case VPSLLDZ128mi:
17550 case VPSLLDZ128mik:
17551 case VPSLLDZ128mikz:
17552 case VPSLLDZ128ri:
17553 case VPSLLDZ128rik:
17554 case VPSLLDZ128rikz:
17555 case VPSLLDZ128rm:
17556 case VPSLLDZ128rmk:
17557 case VPSLLDZ128rmkz:
17558 case VPSLLDZ128rr:
17559 case VPSLLDZ128rrk:
17560 case VPSLLDZ128rrkz:
17561 case VPSLLDZ256mbi:
17562 case VPSLLDZ256mbik:
17563 case VPSLLDZ256mbikz:
17564 case VPSLLDZ256mi:
17565 case VPSLLDZ256mik:
17566 case VPSLLDZ256mikz:
17567 case VPSLLDZ256ri:
17568 case VPSLLDZ256rik:
17569 case VPSLLDZ256rikz:
17570 case VPSLLDZ256rm:
17571 case VPSLLDZ256rmk:
17572 case VPSLLDZ256rmkz:
17573 case VPSLLDZ256rr:
17574 case VPSLLDZ256rrk:
17575 case VPSLLDZ256rrkz:
17576 case VPSLLDZmbi:
17577 case VPSLLDZmbik:
17578 case VPSLLDZmbikz:
17579 case VPSLLDZmi:
17580 case VPSLLDZmik:
17581 case VPSLLDZmikz:
17582 case VPSLLDZri:
17583 case VPSLLDZrik:
17584 case VPSLLDZrikz:
17585 case VPSLLDZrm:
17586 case VPSLLDZrmk:
17587 case VPSLLDZrmkz:
17588 case VPSLLDZrr:
17589 case VPSLLDZrrk:
17590 case VPSLLDZrrkz:
17591 case VPSLLDri:
17592 case VPSLLDrm:
17593 case VPSLLDrr:
17594 return true;
17595 }
17596 return false;
17597}
17598
17599bool isPFCMPGE(unsigned Opcode) {
17600 switch (Opcode) {
17601 case PFCMPGErm:
17602 case PFCMPGErr:
17603 return true;
17604 }
17605 return false;
17606}
17607
17608bool isVPMOVM2D(unsigned Opcode) {
17609 switch (Opcode) {
17610 case VPMOVM2DZ128rr:
17611 case VPMOVM2DZ256rr:
17612 case VPMOVM2DZrr:
17613 return true;
17614 }
17615 return false;
17616}
17617
17618bool isVHSUBPS(unsigned Opcode) {
17619 switch (Opcode) {
17620 case VHSUBPSYrm:
17621 case VHSUBPSYrr:
17622 case VHSUBPSrm:
17623 case VHSUBPSrr:
17624 return true;
17625 }
17626 return false;
17627}
17628
17629bool isENDBR32(unsigned Opcode) {
17630 return Opcode == ENDBR32;
17631}
17632
17633bool isMOVSXD(unsigned Opcode) {
17634 switch (Opcode) {
17635 case MOVSX16rm32:
17636 case MOVSX16rr32:
17637 case MOVSX32rm32:
17638 case MOVSX32rr32:
17639 case MOVSX64rm32:
17640 case MOVSX64rr32:
17641 return true;
17642 }
17643 return false;
17644}
17645
17646bool isPSIGND(unsigned Opcode) {
17647 switch (Opcode) {
17648 case MMX_PSIGNDrm:
17649 case MMX_PSIGNDrr:
17650 case PSIGNDrm:
17651 case PSIGNDrr:
17652 return true;
17653 }
17654 return false;
17655}
17656
17657bool isVPTEST(unsigned Opcode) {
17658 switch (Opcode) {
17659 case VPTESTYrm:
17660 case VPTESTYrr:
17661 case VPTESTrm:
17662 case VPTESTrr:
17663 return true;
17664 }
17665 return false;
17666}
17667
17668bool isVPDPWUSD(unsigned Opcode) {
17669 switch (Opcode) {
17670 case VPDPWUSDYrm:
17671 case VPDPWUSDYrr:
17672 case VPDPWUSDrm:
17673 case VPDPWUSDrr:
17674 return true;
17675 }
17676 return false;
17677}
17678
17679bool isHSUBPD(unsigned Opcode) {
17680 switch (Opcode) {
17681 case HSUBPDrm:
17682 case HSUBPDrr:
17683 return true;
17684 }
17685 return false;
17686}
17687
17688bool isADCX(unsigned Opcode) {
17689 switch (Opcode) {
17690 case ADCX32rm:
17691 case ADCX32rm_EVEX:
17692 case ADCX32rm_ND:
17693 case ADCX32rr:
17694 case ADCX32rr_EVEX:
17695 case ADCX32rr_ND:
17696 case ADCX64rm:
17697 case ADCX64rm_EVEX:
17698 case ADCX64rm_ND:
17699 case ADCX64rr:
17700 case ADCX64rr_EVEX:
17701 case ADCX64rr_ND:
17702 return true;
17703 }
17704 return false;
17705}
17706
17707bool isCVTTPD2PI(unsigned Opcode) {
17708 switch (Opcode) {
17709 case MMX_CVTTPD2PIrm:
17710 case MMX_CVTTPD2PIrr:
17711 return true;
17712 }
17713 return false;
17714}
17715
17716bool isPDEP(unsigned Opcode) {
17717 switch (Opcode) {
17718 case PDEP32rm:
17719 case PDEP32rm_EVEX:
17720 case PDEP32rr:
17721 case PDEP32rr_EVEX:
17722 case PDEP64rm:
17723 case PDEP64rm_EVEX:
17724 case PDEP64rr:
17725 case PDEP64rr_EVEX:
17726 return true;
17727 }
17728 return false;
17729}
17730
17731bool isTDPBUSD(unsigned Opcode) {
17732 return Opcode == TDPBUSD;
17733}
17734
17735bool isVBROADCASTI32X4(unsigned Opcode) {
17736 switch (Opcode) {
17737 case VBROADCASTI32X4Z256rm:
17738 case VBROADCASTI32X4Z256rmk:
17739 case VBROADCASTI32X4Z256rmkz:
17740 case VBROADCASTI32X4rm:
17741 case VBROADCASTI32X4rmk:
17742 case VBROADCASTI32X4rmkz:
17743 return true;
17744 }
17745 return false;
17746}
17747
17748bool isVCVTPH2UDQ(unsigned Opcode) {
17749 switch (Opcode) {
17750 case VCVTPH2UDQZ128rm:
17751 case VCVTPH2UDQZ128rmb:
17752 case VCVTPH2UDQZ128rmbk:
17753 case VCVTPH2UDQZ128rmbkz:
17754 case VCVTPH2UDQZ128rmk:
17755 case VCVTPH2UDQZ128rmkz:
17756 case VCVTPH2UDQZ128rr:
17757 case VCVTPH2UDQZ128rrk:
17758 case VCVTPH2UDQZ128rrkz:
17759 case VCVTPH2UDQZ256rm:
17760 case VCVTPH2UDQZ256rmb:
17761 case VCVTPH2UDQZ256rmbk:
17762 case VCVTPH2UDQZ256rmbkz:
17763 case VCVTPH2UDQZ256rmk:
17764 case VCVTPH2UDQZ256rmkz:
17765 case VCVTPH2UDQZ256rr:
17766 case VCVTPH2UDQZ256rrk:
17767 case VCVTPH2UDQZ256rrkz:
17768 case VCVTPH2UDQZrm:
17769 case VCVTPH2UDQZrmb:
17770 case VCVTPH2UDQZrmbk:
17771 case VCVTPH2UDQZrmbkz:
17772 case VCVTPH2UDQZrmk:
17773 case VCVTPH2UDQZrmkz:
17774 case VCVTPH2UDQZrr:
17775 case VCVTPH2UDQZrrb:
17776 case VCVTPH2UDQZrrbk:
17777 case VCVTPH2UDQZrrbkz:
17778 case VCVTPH2UDQZrrk:
17779 case VCVTPH2UDQZrrkz:
17780 return true;
17781 }
17782 return false;
17783}
17784
17785bool isVPHADDW(unsigned Opcode) {
17786 switch (Opcode) {
17787 case VPHADDWYrm:
17788 case VPHADDWYrr:
17789 case VPHADDWrm:
17790 case VPHADDWrr:
17791 return true;
17792 }
17793 return false;
17794}
17795
17796bool isFLDL2E(unsigned Opcode) {
17797 return Opcode == FLDL2E;
17798}
17799
17800bool isCLZERO(unsigned Opcode) {
17801 switch (Opcode) {
17802 case CLZERO32r:
17803 case CLZERO64r:
17804 return true;
17805 }
17806 return false;
17807}
17808
17809bool isPBLENDW(unsigned Opcode) {
17810 switch (Opcode) {
17811 case PBLENDWrmi:
17812 case PBLENDWrri:
17813 return true;
17814 }
17815 return false;
17816}
17817
17818bool isVCVTSH2USI(unsigned Opcode) {
17819 switch (Opcode) {
17820 case VCVTSH2USI64Zrm_Int:
17821 case VCVTSH2USI64Zrr_Int:
17822 case VCVTSH2USI64Zrrb_Int:
17823 case VCVTSH2USIZrm_Int:
17824 case VCVTSH2USIZrr_Int:
17825 case VCVTSH2USIZrrb_Int:
17826 return true;
17827 }
17828 return false;
17829}
17830
17831bool isVANDPD(unsigned Opcode) {
17832 switch (Opcode) {
17833 case VANDPDYrm:
17834 case VANDPDYrr:
17835 case VANDPDZ128rm:
17836 case VANDPDZ128rmb:
17837 case VANDPDZ128rmbk:
17838 case VANDPDZ128rmbkz:
17839 case VANDPDZ128rmk:
17840 case VANDPDZ128rmkz:
17841 case VANDPDZ128rr:
17842 case VANDPDZ128rrk:
17843 case VANDPDZ128rrkz:
17844 case VANDPDZ256rm:
17845 case VANDPDZ256rmb:
17846 case VANDPDZ256rmbk:
17847 case VANDPDZ256rmbkz:
17848 case VANDPDZ256rmk:
17849 case VANDPDZ256rmkz:
17850 case VANDPDZ256rr:
17851 case VANDPDZ256rrk:
17852 case VANDPDZ256rrkz:
17853 case VANDPDZrm:
17854 case VANDPDZrmb:
17855 case VANDPDZrmbk:
17856 case VANDPDZrmbkz:
17857 case VANDPDZrmk:
17858 case VANDPDZrmkz:
17859 case VANDPDZrr:
17860 case VANDPDZrrk:
17861 case VANDPDZrrkz:
17862 case VANDPDrm:
17863 case VANDPDrr:
17864 return true;
17865 }
17866 return false;
17867}
17868
17869bool isBEXTR(unsigned Opcode) {
17870 switch (Opcode) {
17871 case BEXTR32rm:
17872 case BEXTR32rm_EVEX:
17873 case BEXTR32rm_NF:
17874 case BEXTR32rr:
17875 case BEXTR32rr_EVEX:
17876 case BEXTR32rr_NF:
17877 case BEXTR64rm:
17878 case BEXTR64rm_EVEX:
17879 case BEXTR64rm_NF:
17880 case BEXTR64rr:
17881 case BEXTR64rr_EVEX:
17882 case BEXTR64rr_NF:
17883 case BEXTRI32mi:
17884 case BEXTRI32ri:
17885 case BEXTRI64mi:
17886 case BEXTRI64ri:
17887 return true;
17888 }
17889 return false;
17890}
17891
17892bool isSTD(unsigned Opcode) {
17893 return Opcode == STD;
17894}
17895
17896bool isVAESKEYGENASSIST(unsigned Opcode) {
17897 switch (Opcode) {
17898 case VAESKEYGENASSIST128rm:
17899 case VAESKEYGENASSIST128rr:
17900 return true;
17901 }
17902 return false;
17903}
17904
17905bool isCMPSD(unsigned Opcode) {
17906 switch (Opcode) {
17907 case CMPSDrmi_Int:
17908 case CMPSDrri_Int:
17909 case CMPSL:
17910 return true;
17911 }
17912 return false;
17913}
17914
17915bool isMOVSS(unsigned Opcode) {
17916 switch (Opcode) {
17917 case MOVSSmr:
17918 case MOVSSrm:
17919 case MOVSSrr:
17920 case MOVSSrr_REV:
17921 return true;
17922 }
17923 return false;
17924}
17925
17926bool isVCVTUQQ2PD(unsigned Opcode) {
17927 switch (Opcode) {
17928 case VCVTUQQ2PDZ128rm:
17929 case VCVTUQQ2PDZ128rmb:
17930 case VCVTUQQ2PDZ128rmbk:
17931 case VCVTUQQ2PDZ128rmbkz:
17932 case VCVTUQQ2PDZ128rmk:
17933 case VCVTUQQ2PDZ128rmkz:
17934 case VCVTUQQ2PDZ128rr:
17935 case VCVTUQQ2PDZ128rrk:
17936 case VCVTUQQ2PDZ128rrkz:
17937 case VCVTUQQ2PDZ256rm:
17938 case VCVTUQQ2PDZ256rmb:
17939 case VCVTUQQ2PDZ256rmbk:
17940 case VCVTUQQ2PDZ256rmbkz:
17941 case VCVTUQQ2PDZ256rmk:
17942 case VCVTUQQ2PDZ256rmkz:
17943 case VCVTUQQ2PDZ256rr:
17944 case VCVTUQQ2PDZ256rrk:
17945 case VCVTUQQ2PDZ256rrkz:
17946 case VCVTUQQ2PDZrm:
17947 case VCVTUQQ2PDZrmb:
17948 case VCVTUQQ2PDZrmbk:
17949 case VCVTUQQ2PDZrmbkz:
17950 case VCVTUQQ2PDZrmk:
17951 case VCVTUQQ2PDZrmkz:
17952 case VCVTUQQ2PDZrr:
17953 case VCVTUQQ2PDZrrb:
17954 case VCVTUQQ2PDZrrbk:
17955 case VCVTUQQ2PDZrrbkz:
17956 case VCVTUQQ2PDZrrk:
17957 case VCVTUQQ2PDZrrkz:
17958 return true;
17959 }
17960 return false;
17961}
17962
17963bool isVEXTRACTI32X4(unsigned Opcode) {
17964 switch (Opcode) {
17965 case VEXTRACTI32x4Z256mr:
17966 case VEXTRACTI32x4Z256mrk:
17967 case VEXTRACTI32x4Z256rr:
17968 case VEXTRACTI32x4Z256rrk:
17969 case VEXTRACTI32x4Z256rrkz:
17970 case VEXTRACTI32x4Zmr:
17971 case VEXTRACTI32x4Zmrk:
17972 case VEXTRACTI32x4Zrr:
17973 case VEXTRACTI32x4Zrrk:
17974 case VEXTRACTI32x4Zrrkz:
17975 return true;
17976 }
17977 return false;
17978}
17979
17980bool isFLDCW(unsigned Opcode) {
17981 return Opcode == FLDCW16m;
17982}
17983
17984bool isINSW(unsigned Opcode) {
17985 return Opcode == INSW;
17986}
17987
17988bool isRDPID(unsigned Opcode) {
17989 switch (Opcode) {
17990 case RDPID32:
17991 case RDPID64:
17992 return true;
17993 }
17994 return false;
17995}
17996
17997bool isKANDQ(unsigned Opcode) {
17998 return Opcode == KANDQrr;
17999}
18000
18001bool isV4FMADDPS(unsigned Opcode) {
18002 switch (Opcode) {
18003 case V4FMADDPSrm:
18004 case V4FMADDPSrmk:
18005 case V4FMADDPSrmkz:
18006 return true;
18007 }
18008 return false;
18009}
18010
18011bool isPMOVZXWQ(unsigned Opcode) {
18012 switch (Opcode) {
18013 case PMOVZXWQrm:
18014 case PMOVZXWQrr:
18015 return true;
18016 }
18017 return false;
18018}
18019
18020bool isVFPCLASSSD(unsigned Opcode) {
18021 switch (Opcode) {
18022 case VFPCLASSSDZrm:
18023 case VFPCLASSSDZrmk:
18024 case VFPCLASSSDZrr:
18025 case VFPCLASSSDZrrk:
18026 return true;
18027 }
18028 return false;
18029}
18030
18031bool isBLENDPS(unsigned Opcode) {
18032 switch (Opcode) {
18033 case BLENDPSrmi:
18034 case BLENDPSrri:
18035 return true;
18036 }
18037 return false;
18038}
18039
18040bool isVPACKSSDW(unsigned Opcode) {
18041 switch (Opcode) {
18042 case VPACKSSDWYrm:
18043 case VPACKSSDWYrr:
18044 case VPACKSSDWZ128rm:
18045 case VPACKSSDWZ128rmb:
18046 case VPACKSSDWZ128rmbk:
18047 case VPACKSSDWZ128rmbkz:
18048 case VPACKSSDWZ128rmk:
18049 case VPACKSSDWZ128rmkz:
18050 case VPACKSSDWZ128rr:
18051 case VPACKSSDWZ128rrk:
18052 case VPACKSSDWZ128rrkz:
18053 case VPACKSSDWZ256rm:
18054 case VPACKSSDWZ256rmb:
18055 case VPACKSSDWZ256rmbk:
18056 case VPACKSSDWZ256rmbkz:
18057 case VPACKSSDWZ256rmk:
18058 case VPACKSSDWZ256rmkz:
18059 case VPACKSSDWZ256rr:
18060 case VPACKSSDWZ256rrk:
18061 case VPACKSSDWZ256rrkz:
18062 case VPACKSSDWZrm:
18063 case VPACKSSDWZrmb:
18064 case VPACKSSDWZrmbk:
18065 case VPACKSSDWZrmbkz:
18066 case VPACKSSDWZrmk:
18067 case VPACKSSDWZrmkz:
18068 case VPACKSSDWZrr:
18069 case VPACKSSDWZrrk:
18070 case VPACKSSDWZrrkz:
18071 case VPACKSSDWrm:
18072 case VPACKSSDWrr:
18073 return true;
18074 }
18075 return false;
18076}
18077
18078bool isVPINSRW(unsigned Opcode) {
18079 switch (Opcode) {
18080 case VPINSRWZrm:
18081 case VPINSRWZrr:
18082 case VPINSRWrm:
18083 case VPINSRWrr:
18084 return true;
18085 }
18086 return false;
18087}
18088
18089bool isFXAM(unsigned Opcode) {
18090 return Opcode == XAM_F;
18091}
18092
18093bool isVPHSUBBW(unsigned Opcode) {
18094 switch (Opcode) {
18095 case VPHSUBBWrm:
18096 case VPHSUBBWrr:
18097 return true;
18098 }
18099 return false;
18100}
18101
18102bool isVSHUFF64X2(unsigned Opcode) {
18103 switch (Opcode) {
18104 case VSHUFF64X2Z256rmbi:
18105 case VSHUFF64X2Z256rmbik:
18106 case VSHUFF64X2Z256rmbikz:
18107 case VSHUFF64X2Z256rmi:
18108 case VSHUFF64X2Z256rmik:
18109 case VSHUFF64X2Z256rmikz:
18110 case VSHUFF64X2Z256rri:
18111 case VSHUFF64X2Z256rrik:
18112 case VSHUFF64X2Z256rrikz:
18113 case VSHUFF64X2Zrmbi:
18114 case VSHUFF64X2Zrmbik:
18115 case VSHUFF64X2Zrmbikz:
18116 case VSHUFF64X2Zrmi:
18117 case VSHUFF64X2Zrmik:
18118 case VSHUFF64X2Zrmikz:
18119 case VSHUFF64X2Zrri:
18120 case VSHUFF64X2Zrrik:
18121 case VSHUFF64X2Zrrikz:
18122 return true;
18123 }
18124 return false;
18125}
18126
18127bool isVPACKUSWB(unsigned Opcode) {
18128 switch (Opcode) {
18129 case VPACKUSWBYrm:
18130 case VPACKUSWBYrr:
18131 case VPACKUSWBZ128rm:
18132 case VPACKUSWBZ128rmk:
18133 case VPACKUSWBZ128rmkz:
18134 case VPACKUSWBZ128rr:
18135 case VPACKUSWBZ128rrk:
18136 case VPACKUSWBZ128rrkz:
18137 case VPACKUSWBZ256rm:
18138 case VPACKUSWBZ256rmk:
18139 case VPACKUSWBZ256rmkz:
18140 case VPACKUSWBZ256rr:
18141 case VPACKUSWBZ256rrk:
18142 case VPACKUSWBZ256rrkz:
18143 case VPACKUSWBZrm:
18144 case VPACKUSWBZrmk:
18145 case VPACKUSWBZrmkz:
18146 case VPACKUSWBZrr:
18147 case VPACKUSWBZrrk:
18148 case VPACKUSWBZrrkz:
18149 case VPACKUSWBrm:
18150 case VPACKUSWBrr:
18151 return true;
18152 }
18153 return false;
18154}
18155
18156bool isVRSQRT28SS(unsigned Opcode) {
18157 switch (Opcode) {
18158 case VRSQRT28SSZm:
18159 case VRSQRT28SSZmk:
18160 case VRSQRT28SSZmkz:
18161 case VRSQRT28SSZr:
18162 case VRSQRT28SSZrb:
18163 case VRSQRT28SSZrbk:
18164 case VRSQRT28SSZrbkz:
18165 case VRSQRT28SSZrk:
18166 case VRSQRT28SSZrkz:
18167 return true;
18168 }
18169 return false;
18170}
18171
18172bool isGETSEC(unsigned Opcode) {
18173 return Opcode == GETSEC;
18174}
18175
18176bool isVEXTRACTF64X4(unsigned Opcode) {
18177 switch (Opcode) {
18178 case VEXTRACTF64x4Zmr:
18179 case VEXTRACTF64x4Zmrk:
18180 case VEXTRACTF64x4Zrr:
18181 case VEXTRACTF64x4Zrrk:
18182 case VEXTRACTF64x4Zrrkz:
18183 return true;
18184 }
18185 return false;
18186}
18187
18188bool isBLSR(unsigned Opcode) {
18189 switch (Opcode) {
18190 case BLSR32rm:
18191 case BLSR32rm_EVEX:
18192 case BLSR32rm_NF:
18193 case BLSR32rr:
18194 case BLSR32rr_EVEX:
18195 case BLSR32rr_NF:
18196 case BLSR64rm:
18197 case BLSR64rm_EVEX:
18198 case BLSR64rm_NF:
18199 case BLSR64rr:
18200 case BLSR64rr_EVEX:
18201 case BLSR64rr_NF:
18202 return true;
18203 }
18204 return false;
18205}
18206
18207bool isFILD(unsigned Opcode) {
18208 switch (Opcode) {
18209 case ILD_F16m:
18210 case ILD_F32m:
18211 case ILD_F64m:
18212 return true;
18213 }
18214 return false;
18215}
18216
18217bool isRETFQ(unsigned Opcode) {
18218 switch (Opcode) {
18219 case LRET64:
18220 case LRETI64:
18221 return true;
18222 }
18223 return false;
18224}
18225
18226bool isVADDSS(unsigned Opcode) {
18227 switch (Opcode) {
18228 case VADDSSZrm_Int:
18229 case VADDSSZrm_Intk:
18230 case VADDSSZrm_Intkz:
18231 case VADDSSZrr_Int:
18232 case VADDSSZrr_Intk:
18233 case VADDSSZrr_Intkz:
18234 case VADDSSZrrb_Int:
18235 case VADDSSZrrb_Intk:
18236 case VADDSSZrrb_Intkz:
18237 case VADDSSrm_Int:
18238 case VADDSSrr_Int:
18239 return true;
18240 }
18241 return false;
18242}
18243
18244bool isCOMISS(unsigned Opcode) {
18245 switch (Opcode) {
18246 case COMISSrm:
18247 case COMISSrr:
18248 return true;
18249 }
18250 return false;
18251}
18252
18253bool isCLI(unsigned Opcode) {
18254 return Opcode == CLI;
18255}
18256
18257bool isVERW(unsigned Opcode) {
18258 switch (Opcode) {
18259 case VERWm:
18260 case VERWr:
18261 return true;
18262 }
18263 return false;
18264}
18265
18266bool isBTC(unsigned Opcode) {
18267 switch (Opcode) {
18268 case BTC16mi8:
18269 case BTC16mr:
18270 case BTC16ri8:
18271 case BTC16rr:
18272 case BTC32mi8:
18273 case BTC32mr:
18274 case BTC32ri8:
18275 case BTC32rr:
18276 case BTC64mi8:
18277 case BTC64mr:
18278 case BTC64ri8:
18279 case BTC64rr:
18280 return true;
18281 }
18282 return false;
18283}
18284
18285bool isVPHADDUBQ(unsigned Opcode) {
18286 switch (Opcode) {
18287 case VPHADDUBQrm:
18288 case VPHADDUBQrr:
18289 return true;
18290 }
18291 return false;
18292}
18293
18294bool isVPORQ(unsigned Opcode) {
18295 switch (Opcode) {
18296 case VPORQZ128rm:
18297 case VPORQZ128rmb:
18298 case VPORQZ128rmbk:
18299 case VPORQZ128rmbkz:
18300 case VPORQZ128rmk:
18301 case VPORQZ128rmkz:
18302 case VPORQZ128rr:
18303 case VPORQZ128rrk:
18304 case VPORQZ128rrkz:
18305 case VPORQZ256rm:
18306 case VPORQZ256rmb:
18307 case VPORQZ256rmbk:
18308 case VPORQZ256rmbkz:
18309 case VPORQZ256rmk:
18310 case VPORQZ256rmkz:
18311 case VPORQZ256rr:
18312 case VPORQZ256rrk:
18313 case VPORQZ256rrkz:
18314 case VPORQZrm:
18315 case VPORQZrmb:
18316 case VPORQZrmbk:
18317 case VPORQZrmbkz:
18318 case VPORQZrmk:
18319 case VPORQZrmkz:
18320 case VPORQZrr:
18321 case VPORQZrrk:
18322 case VPORQZrrkz:
18323 return true;
18324 }
18325 return false;
18326}
18327
18328bool isORPD(unsigned Opcode) {
18329 switch (Opcode) {
18330 case ORPDrm:
18331 case ORPDrr:
18332 return true;
18333 }
18334 return false;
18335}
18336
18337bool isVMOVSS(unsigned Opcode) {
18338 switch (Opcode) {
18339 case VMOVSSZmr:
18340 case VMOVSSZmrk:
18341 case VMOVSSZrm:
18342 case VMOVSSZrmk:
18343 case VMOVSSZrmkz:
18344 case VMOVSSZrr:
18345 case VMOVSSZrr_REV:
18346 case VMOVSSZrrk:
18347 case VMOVSSZrrk_REV:
18348 case VMOVSSZrrkz:
18349 case VMOVSSZrrkz_REV:
18350 case VMOVSSmr:
18351 case VMOVSSrm:
18352 case VMOVSSrr:
18353 case VMOVSSrr_REV:
18354 return true;
18355 }
18356 return false;
18357}
18358
18359bool isVPSUBD(unsigned Opcode) {
18360 switch (Opcode) {
18361 case VPSUBDYrm:
18362 case VPSUBDYrr:
18363 case VPSUBDZ128rm:
18364 case VPSUBDZ128rmb:
18365 case VPSUBDZ128rmbk:
18366 case VPSUBDZ128rmbkz:
18367 case VPSUBDZ128rmk:
18368 case VPSUBDZ128rmkz:
18369 case VPSUBDZ128rr:
18370 case VPSUBDZ128rrk:
18371 case VPSUBDZ128rrkz:
18372 case VPSUBDZ256rm:
18373 case VPSUBDZ256rmb:
18374 case VPSUBDZ256rmbk:
18375 case VPSUBDZ256rmbkz:
18376 case VPSUBDZ256rmk:
18377 case VPSUBDZ256rmkz:
18378 case VPSUBDZ256rr:
18379 case VPSUBDZ256rrk:
18380 case VPSUBDZ256rrkz:
18381 case VPSUBDZrm:
18382 case VPSUBDZrmb:
18383 case VPSUBDZrmbk:
18384 case VPSUBDZrmbkz:
18385 case VPSUBDZrmk:
18386 case VPSUBDZrmkz:
18387 case VPSUBDZrr:
18388 case VPSUBDZrrk:
18389 case VPSUBDZrrkz:
18390 case VPSUBDrm:
18391 case VPSUBDrr:
18392 return true;
18393 }
18394 return false;
18395}
18396
18397bool isVGATHERPF1QPD(unsigned Opcode) {
18398 return Opcode == VGATHERPF1QPDm;
18399}
18400
18401bool isENCODEKEY256(unsigned Opcode) {
18402 return Opcode == ENCODEKEY256;
18403}
18404
18405bool isGF2P8AFFINEINVQB(unsigned Opcode) {
18406 switch (Opcode) {
18407 case GF2P8AFFINEINVQBrmi:
18408 case GF2P8AFFINEINVQBrri:
18409 return true;
18410 }
18411 return false;
18412}
18413
18414bool isXRSTOR64(unsigned Opcode) {
18415 return Opcode == XRSTOR64;
18416}
18417
18418bool isKANDW(unsigned Opcode) {
18419 return Opcode == KANDWrr;
18420}
18421
18422bool isLODSQ(unsigned Opcode) {
18423 return Opcode == LODSQ;
18424}
18425
18426bool isVSUBSH(unsigned Opcode) {
18427 switch (Opcode) {
18428 case VSUBSHZrm_Int:
18429 case VSUBSHZrm_Intk:
18430 case VSUBSHZrm_Intkz:
18431 case VSUBSHZrr_Int:
18432 case VSUBSHZrr_Intk:
18433 case VSUBSHZrr_Intkz:
18434 case VSUBSHZrrb_Int:
18435 case VSUBSHZrrb_Intk:
18436 case VSUBSHZrrb_Intkz:
18437 return true;
18438 }
18439 return false;
18440}
18441
18442bool isLSS(unsigned Opcode) {
18443 switch (Opcode) {
18444 case LSS16rm:
18445 case LSS32rm:
18446 case LSS64rm:
18447 return true;
18448 }
18449 return false;
18450}
18451
18452bool isPMOVSXBQ(unsigned Opcode) {
18453 switch (Opcode) {
18454 case PMOVSXBQrm:
18455 case PMOVSXBQrr:
18456 return true;
18457 }
18458 return false;
18459}
18460
18461bool isVCMPSH(unsigned Opcode) {
18462 switch (Opcode) {
18463 case VCMPSHZrmi_Int:
18464 case VCMPSHZrmi_Intk:
18465 case VCMPSHZrri_Int:
18466 case VCMPSHZrri_Intk:
18467 case VCMPSHZrrib_Int:
18468 case VCMPSHZrrib_Intk:
18469 return true;
18470 }
18471 return false;
18472}
18473
18474bool isVFMADD132PS(unsigned Opcode) {
18475 switch (Opcode) {
18476 case VFMADD132PSYm:
18477 case VFMADD132PSYr:
18478 case VFMADD132PSZ128m:
18479 case VFMADD132PSZ128mb:
18480 case VFMADD132PSZ128mbk:
18481 case VFMADD132PSZ128mbkz:
18482 case VFMADD132PSZ128mk:
18483 case VFMADD132PSZ128mkz:
18484 case VFMADD132PSZ128r:
18485 case VFMADD132PSZ128rk:
18486 case VFMADD132PSZ128rkz:
18487 case VFMADD132PSZ256m:
18488 case VFMADD132PSZ256mb:
18489 case VFMADD132PSZ256mbk:
18490 case VFMADD132PSZ256mbkz:
18491 case VFMADD132PSZ256mk:
18492 case VFMADD132PSZ256mkz:
18493 case VFMADD132PSZ256r:
18494 case VFMADD132PSZ256rk:
18495 case VFMADD132PSZ256rkz:
18496 case VFMADD132PSZm:
18497 case VFMADD132PSZmb:
18498 case VFMADD132PSZmbk:
18499 case VFMADD132PSZmbkz:
18500 case VFMADD132PSZmk:
18501 case VFMADD132PSZmkz:
18502 case VFMADD132PSZr:
18503 case VFMADD132PSZrb:
18504 case VFMADD132PSZrbk:
18505 case VFMADD132PSZrbkz:
18506 case VFMADD132PSZrk:
18507 case VFMADD132PSZrkz:
18508 case VFMADD132PSm:
18509 case VFMADD132PSr:
18510 return true;
18511 }
18512 return false;
18513}
18514
18515bool isVPACKSSWB(unsigned Opcode) {
18516 switch (Opcode) {
18517 case VPACKSSWBYrm:
18518 case VPACKSSWBYrr:
18519 case VPACKSSWBZ128rm:
18520 case VPACKSSWBZ128rmk:
18521 case VPACKSSWBZ128rmkz:
18522 case VPACKSSWBZ128rr:
18523 case VPACKSSWBZ128rrk:
18524 case VPACKSSWBZ128rrkz:
18525 case VPACKSSWBZ256rm:
18526 case VPACKSSWBZ256rmk:
18527 case VPACKSSWBZ256rmkz:
18528 case VPACKSSWBZ256rr:
18529 case VPACKSSWBZ256rrk:
18530 case VPACKSSWBZ256rrkz:
18531 case VPACKSSWBZrm:
18532 case VPACKSSWBZrmk:
18533 case VPACKSSWBZrmkz:
18534 case VPACKSSWBZrr:
18535 case VPACKSSWBZrrk:
18536 case VPACKSSWBZrrkz:
18537 case VPACKSSWBrm:
18538 case VPACKSSWBrr:
18539 return true;
18540 }
18541 return false;
18542}
18543
18544bool isPCMPGTQ(unsigned Opcode) {
18545 switch (Opcode) {
18546 case PCMPGTQrm:
18547 case PCMPGTQrr:
18548 return true;
18549 }
18550 return false;
18551}
18552
18553bool isVFMADD132SH(unsigned Opcode) {
18554 switch (Opcode) {
18555 case VFMADD132SHZm_Int:
18556 case VFMADD132SHZm_Intk:
18557 case VFMADD132SHZm_Intkz:
18558 case VFMADD132SHZr_Int:
18559 case VFMADD132SHZr_Intk:
18560 case VFMADD132SHZr_Intkz:
18561 case VFMADD132SHZrb_Int:
18562 case VFMADD132SHZrb_Intk:
18563 case VFMADD132SHZrb_Intkz:
18564 return true;
18565 }
18566 return false;
18567}
18568
18569bool isVCVTUQQ2PH(unsigned Opcode) {
18570 switch (Opcode) {
18571 case VCVTUQQ2PHZ128rm:
18572 case VCVTUQQ2PHZ128rmb:
18573 case VCVTUQQ2PHZ128rmbk:
18574 case VCVTUQQ2PHZ128rmbkz:
18575 case VCVTUQQ2PHZ128rmk:
18576 case VCVTUQQ2PHZ128rmkz:
18577 case VCVTUQQ2PHZ128rr:
18578 case VCVTUQQ2PHZ128rrk:
18579 case VCVTUQQ2PHZ128rrkz:
18580 case VCVTUQQ2PHZ256rm:
18581 case VCVTUQQ2PHZ256rmb:
18582 case VCVTUQQ2PHZ256rmbk:
18583 case VCVTUQQ2PHZ256rmbkz:
18584 case VCVTUQQ2PHZ256rmk:
18585 case VCVTUQQ2PHZ256rmkz:
18586 case VCVTUQQ2PHZ256rr:
18587 case VCVTUQQ2PHZ256rrk:
18588 case VCVTUQQ2PHZ256rrkz:
18589 case VCVTUQQ2PHZrm:
18590 case VCVTUQQ2PHZrmb:
18591 case VCVTUQQ2PHZrmbk:
18592 case VCVTUQQ2PHZrmbkz:
18593 case VCVTUQQ2PHZrmk:
18594 case VCVTUQQ2PHZrmkz:
18595 case VCVTUQQ2PHZrr:
18596 case VCVTUQQ2PHZrrb:
18597 case VCVTUQQ2PHZrrbk:
18598 case VCVTUQQ2PHZrrbkz:
18599 case VCVTUQQ2PHZrrk:
18600 case VCVTUQQ2PHZrrkz:
18601 return true;
18602 }
18603 return false;
18604}
18605
18606bool isVCVTQQ2PS(unsigned Opcode) {
18607 switch (Opcode) {
18608 case VCVTQQ2PSZ128rm:
18609 case VCVTQQ2PSZ128rmb:
18610 case VCVTQQ2PSZ128rmbk:
18611 case VCVTQQ2PSZ128rmbkz:
18612 case VCVTQQ2PSZ128rmk:
18613 case VCVTQQ2PSZ128rmkz:
18614 case VCVTQQ2PSZ128rr:
18615 case VCVTQQ2PSZ128rrk:
18616 case VCVTQQ2PSZ128rrkz:
18617 case VCVTQQ2PSZ256rm:
18618 case VCVTQQ2PSZ256rmb:
18619 case VCVTQQ2PSZ256rmbk:
18620 case VCVTQQ2PSZ256rmbkz:
18621 case VCVTQQ2PSZ256rmk:
18622 case VCVTQQ2PSZ256rmkz:
18623 case VCVTQQ2PSZ256rr:
18624 case VCVTQQ2PSZ256rrk:
18625 case VCVTQQ2PSZ256rrkz:
18626 case VCVTQQ2PSZrm:
18627 case VCVTQQ2PSZrmb:
18628 case VCVTQQ2PSZrmbk:
18629 case VCVTQQ2PSZrmbkz:
18630 case VCVTQQ2PSZrmk:
18631 case VCVTQQ2PSZrmkz:
18632 case VCVTQQ2PSZrr:
18633 case VCVTQQ2PSZrrb:
18634 case VCVTQQ2PSZrrbk:
18635 case VCVTQQ2PSZrrbkz:
18636 case VCVTQQ2PSZrrk:
18637 case VCVTQQ2PSZrrkz:
18638 return true;
18639 }
18640 return false;
18641}
18642
18643bool isVCVTTSS2USI(unsigned Opcode) {
18644 switch (Opcode) {
18645 case VCVTTSS2USI64Zrm_Int:
18646 case VCVTTSS2USI64Zrr_Int:
18647 case VCVTTSS2USI64Zrrb_Int:
18648 case VCVTTSS2USIZrm_Int:
18649 case VCVTTSS2USIZrr_Int:
18650 case VCVTTSS2USIZrrb_Int:
18651 return true;
18652 }
18653 return false;
18654}
18655
18656bool isVPMOVM2Q(unsigned Opcode) {
18657 switch (Opcode) {
18658 case VPMOVM2QZ128rr:
18659 case VPMOVM2QZ256rr:
18660 case VPMOVM2QZrr:
18661 return true;
18662 }
18663 return false;
18664}
18665
18666bool isVMOVD(unsigned Opcode) {
18667 switch (Opcode) {
18668 case VMOVDI2PDIZrm:
18669 case VMOVDI2PDIZrr:
18670 case VMOVDI2PDIrm:
18671 case VMOVDI2PDIrr:
18672 case VMOVPDI2DIZmr:
18673 case VMOVPDI2DIZrr:
18674 case VMOVPDI2DImr:
18675 case VMOVPDI2DIrr:
18676 return true;
18677 }
18678 return false;
18679}
18680
18681bool isVFPCLASSPH(unsigned Opcode) {
18682 switch (Opcode) {
18683 case VFPCLASSPHZ128rm:
18684 case VFPCLASSPHZ128rmb:
18685 case VFPCLASSPHZ128rmbk:
18686 case VFPCLASSPHZ128rmk:
18687 case VFPCLASSPHZ128rr:
18688 case VFPCLASSPHZ128rrk:
18689 case VFPCLASSPHZ256rm:
18690 case VFPCLASSPHZ256rmb:
18691 case VFPCLASSPHZ256rmbk:
18692 case VFPCLASSPHZ256rmk:
18693 case VFPCLASSPHZ256rr:
18694 case VFPCLASSPHZ256rrk:
18695 case VFPCLASSPHZrm:
18696 case VFPCLASSPHZrmb:
18697 case VFPCLASSPHZrmbk:
18698 case VFPCLASSPHZrmk:
18699 case VFPCLASSPHZrr:
18700 case VFPCLASSPHZrrk:
18701 return true;
18702 }
18703 return false;
18704}
18705
18706bool isVCVTSS2SH(unsigned Opcode) {
18707 switch (Opcode) {
18708 case VCVTSS2SHZrm_Int:
18709 case VCVTSS2SHZrm_Intk:
18710 case VCVTSS2SHZrm_Intkz:
18711 case VCVTSS2SHZrr_Int:
18712 case VCVTSS2SHZrr_Intk:
18713 case VCVTSS2SHZrr_Intkz:
18714 case VCVTSS2SHZrrb_Int:
18715 case VCVTSS2SHZrrb_Intk:
18716 case VCVTSS2SHZrrb_Intkz:
18717 return true;
18718 }
18719 return false;
18720}
18721
18722bool isSCASB(unsigned Opcode) {
18723 return Opcode == SCASB;
18724}
18725
18726bool isPSRLD(unsigned Opcode) {
18727 switch (Opcode) {
18728 case MMX_PSRLDri:
18729 case MMX_PSRLDrm:
18730 case MMX_PSRLDrr:
18731 case PSRLDri:
18732 case PSRLDrm:
18733 case PSRLDrr:
18734 return true;
18735 }
18736 return false;
18737}
18738
18739bool isVADDPH(unsigned Opcode) {
18740 switch (Opcode) {
18741 case VADDPHZ128rm:
18742 case VADDPHZ128rmb:
18743 case VADDPHZ128rmbk:
18744 case VADDPHZ128rmbkz:
18745 case VADDPHZ128rmk:
18746 case VADDPHZ128rmkz:
18747 case VADDPHZ128rr:
18748 case VADDPHZ128rrk:
18749 case VADDPHZ128rrkz:
18750 case VADDPHZ256rm:
18751 case VADDPHZ256rmb:
18752 case VADDPHZ256rmbk:
18753 case VADDPHZ256rmbkz:
18754 case VADDPHZ256rmk:
18755 case VADDPHZ256rmkz:
18756 case VADDPHZ256rr:
18757 case VADDPHZ256rrk:
18758 case VADDPHZ256rrkz:
18759 case VADDPHZrm:
18760 case VADDPHZrmb:
18761 case VADDPHZrmbk:
18762 case VADDPHZrmbkz:
18763 case VADDPHZrmk:
18764 case VADDPHZrmkz:
18765 case VADDPHZrr:
18766 case VADDPHZrrb:
18767 case VADDPHZrrbk:
18768 case VADDPHZrrbkz:
18769 case VADDPHZrrk:
18770 case VADDPHZrrkz:
18771 return true;
18772 }
18773 return false;
18774}
18775
18776bool isFSUB(unsigned Opcode) {
18777 switch (Opcode) {
18778 case SUB_F32m:
18779 case SUB_F64m:
18780 case SUB_FST0r:
18781 case SUB_FrST0:
18782 return true;
18783 }
18784 return false;
18785}
18786
18787bool isVEXTRACTI64X2(unsigned Opcode) {
18788 switch (Opcode) {
18789 case VEXTRACTI64x2Z256mr:
18790 case VEXTRACTI64x2Z256mrk:
18791 case VEXTRACTI64x2Z256rr:
18792 case VEXTRACTI64x2Z256rrk:
18793 case VEXTRACTI64x2Z256rrkz:
18794 case VEXTRACTI64x2Zmr:
18795 case VEXTRACTI64x2Zmrk:
18796 case VEXTRACTI64x2Zrr:
18797 case VEXTRACTI64x2Zrrk:
18798 case VEXTRACTI64x2Zrrkz:
18799 return true;
18800 }
18801 return false;
18802}
18803
18804bool isPMINUW(unsigned Opcode) {
18805 switch (Opcode) {
18806 case PMINUWrm:
18807 case PMINUWrr:
18808 return true;
18809 }
18810 return false;
18811}
18812
18813bool isPSUBSB(unsigned Opcode) {
18814 switch (Opcode) {
18815 case MMX_PSUBSBrm:
18816 case MMX_PSUBSBrr:
18817 case PSUBSBrm:
18818 case PSUBSBrr:
18819 return true;
18820 }
18821 return false;
18822}
18823
18824bool isVPSHLDD(unsigned Opcode) {
18825 switch (Opcode) {
18826 case VPSHLDDZ128rmbi:
18827 case VPSHLDDZ128rmbik:
18828 case VPSHLDDZ128rmbikz:
18829 case VPSHLDDZ128rmi:
18830 case VPSHLDDZ128rmik:
18831 case VPSHLDDZ128rmikz:
18832 case VPSHLDDZ128rri:
18833 case VPSHLDDZ128rrik:
18834 case VPSHLDDZ128rrikz:
18835 case VPSHLDDZ256rmbi:
18836 case VPSHLDDZ256rmbik:
18837 case VPSHLDDZ256rmbikz:
18838 case VPSHLDDZ256rmi:
18839 case VPSHLDDZ256rmik:
18840 case VPSHLDDZ256rmikz:
18841 case VPSHLDDZ256rri:
18842 case VPSHLDDZ256rrik:
18843 case VPSHLDDZ256rrikz:
18844 case VPSHLDDZrmbi:
18845 case VPSHLDDZrmbik:
18846 case VPSHLDDZrmbikz:
18847 case VPSHLDDZrmi:
18848 case VPSHLDDZrmik:
18849 case VPSHLDDZrmikz:
18850 case VPSHLDDZrri:
18851 case VPSHLDDZrrik:
18852 case VPSHLDDZrrikz:
18853 return true;
18854 }
18855 return false;
18856}
18857
18858bool isVPCMPEQD(unsigned Opcode) {
18859 switch (Opcode) {
18860 case VPCMPEQDYrm:
18861 case VPCMPEQDYrr:
18862 case VPCMPEQDZ128rm:
18863 case VPCMPEQDZ128rmb:
18864 case VPCMPEQDZ128rmbk:
18865 case VPCMPEQDZ128rmk:
18866 case VPCMPEQDZ128rr:
18867 case VPCMPEQDZ128rrk:
18868 case VPCMPEQDZ256rm:
18869 case VPCMPEQDZ256rmb:
18870 case VPCMPEQDZ256rmbk:
18871 case VPCMPEQDZ256rmk:
18872 case VPCMPEQDZ256rr:
18873 case VPCMPEQDZ256rrk:
18874 case VPCMPEQDZrm:
18875 case VPCMPEQDZrmb:
18876 case VPCMPEQDZrmbk:
18877 case VPCMPEQDZrmk:
18878 case VPCMPEQDZrr:
18879 case VPCMPEQDZrrk:
18880 case VPCMPEQDrm:
18881 case VPCMPEQDrr:
18882 return true;
18883 }
18884 return false;
18885}
18886
18887bool isVPSCATTERQD(unsigned Opcode) {
18888 switch (Opcode) {
18889 case VPSCATTERQDZ128mr:
18890 case VPSCATTERQDZ256mr:
18891 case VPSCATTERQDZmr:
18892 return true;
18893 }
18894 return false;
18895}
18896
18897bool isKXNORB(unsigned Opcode) {
18898 return Opcode == KXNORBrr;
18899}
18900
18901bool isLDDQU(unsigned Opcode) {
18902 return Opcode == LDDQUrm;
18903}
18904
18905bool isMASKMOVQ(unsigned Opcode) {
18906 switch (Opcode) {
18907 case MMX_MASKMOVQ:
18908 case MMX_MASKMOVQ64:
18909 return true;
18910 }
18911 return false;
18912}
18913
18914bool isPABSW(unsigned Opcode) {
18915 switch (Opcode) {
18916 case MMX_PABSWrm:
18917 case MMX_PABSWrr:
18918 case PABSWrm:
18919 case PABSWrr:
18920 return true;
18921 }
18922 return false;
18923}
18924
18925bool isVPROLD(unsigned Opcode) {
18926 switch (Opcode) {
18927 case VPROLDZ128mbi:
18928 case VPROLDZ128mbik:
18929 case VPROLDZ128mbikz:
18930 case VPROLDZ128mi:
18931 case VPROLDZ128mik:
18932 case VPROLDZ128mikz:
18933 case VPROLDZ128ri:
18934 case VPROLDZ128rik:
18935 case VPROLDZ128rikz:
18936 case VPROLDZ256mbi:
18937 case VPROLDZ256mbik:
18938 case VPROLDZ256mbikz:
18939 case VPROLDZ256mi:
18940 case VPROLDZ256mik:
18941 case VPROLDZ256mikz:
18942 case VPROLDZ256ri:
18943 case VPROLDZ256rik:
18944 case VPROLDZ256rikz:
18945 case VPROLDZmbi:
18946 case VPROLDZmbik:
18947 case VPROLDZmbikz:
18948 case VPROLDZmi:
18949 case VPROLDZmik:
18950 case VPROLDZmikz:
18951 case VPROLDZri:
18952 case VPROLDZrik:
18953 case VPROLDZrikz:
18954 return true;
18955 }
18956 return false;
18957}
18958
18959bool isVPCOMQ(unsigned Opcode) {
18960 switch (Opcode) {
18961 case VPCOMQmi:
18962 case VPCOMQri:
18963 return true;
18964 }
18965 return false;
18966}
18967
18968bool isVSCATTERDPD(unsigned Opcode) {
18969 switch (Opcode) {
18970 case VSCATTERDPDZ128mr:
18971 case VSCATTERDPDZ256mr:
18972 case VSCATTERDPDZmr:
18973 return true;
18974 }
18975 return false;
18976}
18977
18978bool isFXRSTOR(unsigned Opcode) {
18979 return Opcode == FXRSTOR;
18980}
18981
18982bool isVPCMPUW(unsigned Opcode) {
18983 switch (Opcode) {
18984 case VPCMPUWZ128rmi:
18985 case VPCMPUWZ128rmik:
18986 case VPCMPUWZ128rri:
18987 case VPCMPUWZ128rrik:
18988 case VPCMPUWZ256rmi:
18989 case VPCMPUWZ256rmik:
18990 case VPCMPUWZ256rri:
18991 case VPCMPUWZ256rrik:
18992 case VPCMPUWZrmi:
18993 case VPCMPUWZrmik:
18994 case VPCMPUWZrri:
18995 case VPCMPUWZrrik:
18996 return true;
18997 }
18998 return false;
18999}
19000
19001bool isWBINVD(unsigned Opcode) {
19002 return Opcode == WBINVD;
19003}
19004
19005bool isVCVTTPD2UDQ(unsigned Opcode) {
19006 switch (Opcode) {
19007 case VCVTTPD2UDQZ128rm:
19008 case VCVTTPD2UDQZ128rmb:
19009 case VCVTTPD2UDQZ128rmbk:
19010 case VCVTTPD2UDQZ128rmbkz:
19011 case VCVTTPD2UDQZ128rmk:
19012 case VCVTTPD2UDQZ128rmkz:
19013 case VCVTTPD2UDQZ128rr:
19014 case VCVTTPD2UDQZ128rrk:
19015 case VCVTTPD2UDQZ128rrkz:
19016 case VCVTTPD2UDQZ256rm:
19017 case VCVTTPD2UDQZ256rmb:
19018 case VCVTTPD2UDQZ256rmbk:
19019 case VCVTTPD2UDQZ256rmbkz:
19020 case VCVTTPD2UDQZ256rmk:
19021 case VCVTTPD2UDQZ256rmkz:
19022 case VCVTTPD2UDQZ256rr:
19023 case VCVTTPD2UDQZ256rrk:
19024 case VCVTTPD2UDQZ256rrkz:
19025 case VCVTTPD2UDQZrm:
19026 case VCVTTPD2UDQZrmb:
19027 case VCVTTPD2UDQZrmbk:
19028 case VCVTTPD2UDQZrmbkz:
19029 case VCVTTPD2UDQZrmk:
19030 case VCVTTPD2UDQZrmkz:
19031 case VCVTTPD2UDQZrr:
19032 case VCVTTPD2UDQZrrb:
19033 case VCVTTPD2UDQZrrbk:
19034 case VCVTTPD2UDQZrrbkz:
19035 case VCVTTPD2UDQZrrk:
19036 case VCVTTPD2UDQZrrkz:
19037 return true;
19038 }
19039 return false;
19040}
19041
19042bool isERETU(unsigned Opcode) {
19043 return Opcode == ERETU;
19044}
19045
19046bool isPFRCPIT2(unsigned Opcode) {
19047 switch (Opcode) {
19048 case PFRCPIT2rm:
19049 case PFRCPIT2rr:
19050 return true;
19051 }
19052 return false;
19053}
19054
19055bool isVPERMT2W(unsigned Opcode) {
19056 switch (Opcode) {
19057 case VPERMT2WZ128rm:
19058 case VPERMT2WZ128rmk:
19059 case VPERMT2WZ128rmkz:
19060 case VPERMT2WZ128rr:
19061 case VPERMT2WZ128rrk:
19062 case VPERMT2WZ128rrkz:
19063 case VPERMT2WZ256rm:
19064 case VPERMT2WZ256rmk:
19065 case VPERMT2WZ256rmkz:
19066 case VPERMT2WZ256rr:
19067 case VPERMT2WZ256rrk:
19068 case VPERMT2WZ256rrkz:
19069 case VPERMT2WZrm:
19070 case VPERMT2WZrmk:
19071 case VPERMT2WZrmkz:
19072 case VPERMT2WZrr:
19073 case VPERMT2WZrrk:
19074 case VPERMT2WZrrkz:
19075 return true;
19076 }
19077 return false;
19078}
19079
19080bool isVEXTRACTF32X4(unsigned Opcode) {
19081 switch (Opcode) {
19082 case VEXTRACTF32x4Z256mr:
19083 case VEXTRACTF32x4Z256mrk:
19084 case VEXTRACTF32x4Z256rr:
19085 case VEXTRACTF32x4Z256rrk:
19086 case VEXTRACTF32x4Z256rrkz:
19087 case VEXTRACTF32x4Zmr:
19088 case VEXTRACTF32x4Zmrk:
19089 case VEXTRACTF32x4Zrr:
19090 case VEXTRACTF32x4Zrrk:
19091 case VEXTRACTF32x4Zrrkz:
19092 return true;
19093 }
19094 return false;
19095}
19096
19097bool isVGATHERPF0DPD(unsigned Opcode) {
19098 return Opcode == VGATHERPF0DPDm;
19099}
19100
19101bool isVBROADCASTF32X2(unsigned Opcode) {
19102 switch (Opcode) {
19103 case VBROADCASTF32X2Z256rm:
19104 case VBROADCASTF32X2Z256rmk:
19105 case VBROADCASTF32X2Z256rmkz:
19106 case VBROADCASTF32X2Z256rr:
19107 case VBROADCASTF32X2Z256rrk:
19108 case VBROADCASTF32X2Z256rrkz:
19109 case VBROADCASTF32X2Zrm:
19110 case VBROADCASTF32X2Zrmk:
19111 case VBROADCASTF32X2Zrmkz:
19112 case VBROADCASTF32X2Zrr:
19113 case VBROADCASTF32X2Zrrk:
19114 case VBROADCASTF32X2Zrrkz:
19115 return true;
19116 }
19117 return false;
19118}
19119
19120bool isVRCP14SD(unsigned Opcode) {
19121 switch (Opcode) {
19122 case VRCP14SDZrm:
19123 case VRCP14SDZrmk:
19124 case VRCP14SDZrmkz:
19125 case VRCP14SDZrr:
19126 case VRCP14SDZrrk:
19127 case VRCP14SDZrrkz:
19128 return true;
19129 }
19130 return false;
19131}
19132
19133bool isPABSD(unsigned Opcode) {
19134 switch (Opcode) {
19135 case MMX_PABSDrm:
19136 case MMX_PABSDrr:
19137 case PABSDrm:
19138 case PABSDrr:
19139 return true;
19140 }
19141 return false;
19142}
19143
19144bool isLAHF(unsigned Opcode) {
19145 return Opcode == LAHF;
19146}
19147
19148bool isPINSRB(unsigned Opcode) {
19149 switch (Opcode) {
19150 case PINSRBrm:
19151 case PINSRBrr:
19152 return true;
19153 }
19154 return false;
19155}
19156
19157bool isSKINIT(unsigned Opcode) {
19158 return Opcode == SKINIT;
19159}
19160
19161bool isENTER(unsigned Opcode) {
19162 return Opcode == ENTER;
19163}
19164
19165bool isVCVTSI2SS(unsigned Opcode) {
19166 switch (Opcode) {
19167 case VCVTSI2SSZrm_Int:
19168 case VCVTSI2SSZrr_Int:
19169 case VCVTSI2SSZrrb_Int:
19170 case VCVTSI2SSrm_Int:
19171 case VCVTSI2SSrr_Int:
19172 case VCVTSI642SSZrm_Int:
19173 case VCVTSI642SSZrr_Int:
19174 case VCVTSI642SSZrrb_Int:
19175 case VCVTSI642SSrm_Int:
19176 case VCVTSI642SSrr_Int:
19177 return true;
19178 }
19179 return false;
19180}
19181
19182bool isVFMADD231PD(unsigned Opcode) {
19183 switch (Opcode) {
19184 case VFMADD231PDYm:
19185 case VFMADD231PDYr:
19186 case VFMADD231PDZ128m:
19187 case VFMADD231PDZ128mb:
19188 case VFMADD231PDZ128mbk:
19189 case VFMADD231PDZ128mbkz:
19190 case VFMADD231PDZ128mk:
19191 case VFMADD231PDZ128mkz:
19192 case VFMADD231PDZ128r:
19193 case VFMADD231PDZ128rk:
19194 case VFMADD231PDZ128rkz:
19195 case VFMADD231PDZ256m:
19196 case VFMADD231PDZ256mb:
19197 case VFMADD231PDZ256mbk:
19198 case VFMADD231PDZ256mbkz:
19199 case VFMADD231PDZ256mk:
19200 case VFMADD231PDZ256mkz:
19201 case VFMADD231PDZ256r:
19202 case VFMADD231PDZ256rk:
19203 case VFMADD231PDZ256rkz:
19204 case VFMADD231PDZm:
19205 case VFMADD231PDZmb:
19206 case VFMADD231PDZmbk:
19207 case VFMADD231PDZmbkz:
19208 case VFMADD231PDZmk:
19209 case VFMADD231PDZmkz:
19210 case VFMADD231PDZr:
19211 case VFMADD231PDZrb:
19212 case VFMADD231PDZrbk:
19213 case VFMADD231PDZrbkz:
19214 case VFMADD231PDZrk:
19215 case VFMADD231PDZrkz:
19216 case VFMADD231PDm:
19217 case VFMADD231PDr:
19218 return true;
19219 }
19220 return false;
19221}
19222
19223bool isLOADIWKEY(unsigned Opcode) {
19224 return Opcode == LOADIWKEY;
19225}
19226
19227bool isVMOVNTDQA(unsigned Opcode) {
19228 switch (Opcode) {
19229 case VMOVNTDQAYrm:
19230 case VMOVNTDQAZ128rm:
19231 case VMOVNTDQAZ256rm:
19232 case VMOVNTDQAZrm:
19233 case VMOVNTDQArm:
19234 return true;
19235 }
19236 return false;
19237}
19238
19239bool isVPERMT2PS(unsigned Opcode) {
19240 switch (Opcode) {
19241 case VPERMT2PSZ128rm:
19242 case VPERMT2PSZ128rmb:
19243 case VPERMT2PSZ128rmbk:
19244 case VPERMT2PSZ128rmbkz:
19245 case VPERMT2PSZ128rmk:
19246 case VPERMT2PSZ128rmkz:
19247 case VPERMT2PSZ128rr:
19248 case VPERMT2PSZ128rrk:
19249 case VPERMT2PSZ128rrkz:
19250 case VPERMT2PSZ256rm:
19251 case VPERMT2PSZ256rmb:
19252 case VPERMT2PSZ256rmbk:
19253 case VPERMT2PSZ256rmbkz:
19254 case VPERMT2PSZ256rmk:
19255 case VPERMT2PSZ256rmkz:
19256 case VPERMT2PSZ256rr:
19257 case VPERMT2PSZ256rrk:
19258 case VPERMT2PSZ256rrkz:
19259 case VPERMT2PSZrm:
19260 case VPERMT2PSZrmb:
19261 case VPERMT2PSZrmbk:
19262 case VPERMT2PSZrmbkz:
19263 case VPERMT2PSZrmk:
19264 case VPERMT2PSZrmkz:
19265 case VPERMT2PSZrr:
19266 case VPERMT2PSZrrk:
19267 case VPERMT2PSZrrkz:
19268 return true;
19269 }
19270 return false;
19271}
19272
19273bool isPUSHF(unsigned Opcode) {
19274 return Opcode == PUSHF16;
19275}
19276
19277bool isMPSADBW(unsigned Opcode) {
19278 switch (Opcode) {
19279 case MPSADBWrmi:
19280 case MPSADBWrri:
19281 return true;
19282 }
19283 return false;
19284}
19285
19286bool isVRSQRT14SS(unsigned Opcode) {
19287 switch (Opcode) {
19288 case VRSQRT14SSZrm:
19289 case VRSQRT14SSZrmk:
19290 case VRSQRT14SSZrmkz:
19291 case VRSQRT14SSZrr:
19292 case VRSQRT14SSZrrk:
19293 case VRSQRT14SSZrrkz:
19294 return true;
19295 }
19296 return false;
19297}
19298
19299bool isVCVTDQ2PD(unsigned Opcode) {
19300 switch (Opcode) {
19301 case VCVTDQ2PDYrm:
19302 case VCVTDQ2PDYrr:
19303 case VCVTDQ2PDZ128rm:
19304 case VCVTDQ2PDZ128rmb:
19305 case VCVTDQ2PDZ128rmbk:
19306 case VCVTDQ2PDZ128rmbkz:
19307 case VCVTDQ2PDZ128rmk:
19308 case VCVTDQ2PDZ128rmkz:
19309 case VCVTDQ2PDZ128rr:
19310 case VCVTDQ2PDZ128rrk:
19311 case VCVTDQ2PDZ128rrkz:
19312 case VCVTDQ2PDZ256rm:
19313 case VCVTDQ2PDZ256rmb:
19314 case VCVTDQ2PDZ256rmbk:
19315 case VCVTDQ2PDZ256rmbkz:
19316 case VCVTDQ2PDZ256rmk:
19317 case VCVTDQ2PDZ256rmkz:
19318 case VCVTDQ2PDZ256rr:
19319 case VCVTDQ2PDZ256rrk:
19320 case VCVTDQ2PDZ256rrkz:
19321 case VCVTDQ2PDZrm:
19322 case VCVTDQ2PDZrmb:
19323 case VCVTDQ2PDZrmbk:
19324 case VCVTDQ2PDZrmbkz:
19325 case VCVTDQ2PDZrmk:
19326 case VCVTDQ2PDZrmkz:
19327 case VCVTDQ2PDZrr:
19328 case VCVTDQ2PDZrrk:
19329 case VCVTDQ2PDZrrkz:
19330 case VCVTDQ2PDrm:
19331 case VCVTDQ2PDrr:
19332 return true;
19333 }
19334 return false;
19335}
19336
19337bool isVORPS(unsigned Opcode) {
19338 switch (Opcode) {
19339 case VORPSYrm:
19340 case VORPSYrr:
19341 case VORPSZ128rm:
19342 case VORPSZ128rmb:
19343 case VORPSZ128rmbk:
19344 case VORPSZ128rmbkz:
19345 case VORPSZ128rmk:
19346 case VORPSZ128rmkz:
19347 case VORPSZ128rr:
19348 case VORPSZ128rrk:
19349 case VORPSZ128rrkz:
19350 case VORPSZ256rm:
19351 case VORPSZ256rmb:
19352 case VORPSZ256rmbk:
19353 case VORPSZ256rmbkz:
19354 case VORPSZ256rmk:
19355 case VORPSZ256rmkz:
19356 case VORPSZ256rr:
19357 case VORPSZ256rrk:
19358 case VORPSZ256rrkz:
19359 case VORPSZrm:
19360 case VORPSZrmb:
19361 case VORPSZrmbk:
19362 case VORPSZrmbkz:
19363 case VORPSZrmk:
19364 case VORPSZrmkz:
19365 case VORPSZrr:
19366 case VORPSZrrk:
19367 case VORPSZrrkz:
19368 case VORPSrm:
19369 case VORPSrr:
19370 return true;
19371 }
19372 return false;
19373}
19374
19375bool isVPEXPANDQ(unsigned Opcode) {
19376 switch (Opcode) {
19377 case VPEXPANDQZ128rm:
19378 case VPEXPANDQZ128rmk:
19379 case VPEXPANDQZ128rmkz:
19380 case VPEXPANDQZ128rr:
19381 case VPEXPANDQZ128rrk:
19382 case VPEXPANDQZ128rrkz:
19383 case VPEXPANDQZ256rm:
19384 case VPEXPANDQZ256rmk:
19385 case VPEXPANDQZ256rmkz:
19386 case VPEXPANDQZ256rr:
19387 case VPEXPANDQZ256rrk:
19388 case VPEXPANDQZ256rrkz:
19389 case VPEXPANDQZrm:
19390 case VPEXPANDQZrmk:
19391 case VPEXPANDQZrmkz:
19392 case VPEXPANDQZrr:
19393 case VPEXPANDQZrrk:
19394 case VPEXPANDQZrrkz:
19395 return true;
19396 }
19397 return false;
19398}
19399
19400bool isVPSHRDD(unsigned Opcode) {
19401 switch (Opcode) {
19402 case VPSHRDDZ128rmbi:
19403 case VPSHRDDZ128rmbik:
19404 case VPSHRDDZ128rmbikz:
19405 case VPSHRDDZ128rmi:
19406 case VPSHRDDZ128rmik:
19407 case VPSHRDDZ128rmikz:
19408 case VPSHRDDZ128rri:
19409 case VPSHRDDZ128rrik:
19410 case VPSHRDDZ128rrikz:
19411 case VPSHRDDZ256rmbi:
19412 case VPSHRDDZ256rmbik:
19413 case VPSHRDDZ256rmbikz:
19414 case VPSHRDDZ256rmi:
19415 case VPSHRDDZ256rmik:
19416 case VPSHRDDZ256rmikz:
19417 case VPSHRDDZ256rri:
19418 case VPSHRDDZ256rrik:
19419 case VPSHRDDZ256rrikz:
19420 case VPSHRDDZrmbi:
19421 case VPSHRDDZrmbik:
19422 case VPSHRDDZrmbikz:
19423 case VPSHRDDZrmi:
19424 case VPSHRDDZrmik:
19425 case VPSHRDDZrmikz:
19426 case VPSHRDDZrri:
19427 case VPSHRDDZrrik:
19428 case VPSHRDDZrrikz:
19429 return true;
19430 }
19431 return false;
19432}
19433
19434bool isTDPBSSD(unsigned Opcode) {
19435 return Opcode == TDPBSSD;
19436}
19437
19438bool isTESTUI(unsigned Opcode) {
19439 return Opcode == TESTUI;
19440}
19441
19442bool isVFMADDPD(unsigned Opcode) {
19443 switch (Opcode) {
19444 case VFMADDPD4Ymr:
19445 case VFMADDPD4Yrm:
19446 case VFMADDPD4Yrr:
19447 case VFMADDPD4Yrr_REV:
19448 case VFMADDPD4mr:
19449 case VFMADDPD4rm:
19450 case VFMADDPD4rr:
19451 case VFMADDPD4rr_REV:
19452 return true;
19453 }
19454 return false;
19455}
19456
19457bool isVPANDND(unsigned Opcode) {
19458 switch (Opcode) {
19459 case VPANDNDZ128rm:
19460 case VPANDNDZ128rmb:
19461 case VPANDNDZ128rmbk:
19462 case VPANDNDZ128rmbkz:
19463 case VPANDNDZ128rmk:
19464 case VPANDNDZ128rmkz:
19465 case VPANDNDZ128rr:
19466 case VPANDNDZ128rrk:
19467 case VPANDNDZ128rrkz:
19468 case VPANDNDZ256rm:
19469 case VPANDNDZ256rmb:
19470 case VPANDNDZ256rmbk:
19471 case VPANDNDZ256rmbkz:
19472 case VPANDNDZ256rmk:
19473 case VPANDNDZ256rmkz:
19474 case VPANDNDZ256rr:
19475 case VPANDNDZ256rrk:
19476 case VPANDNDZ256rrkz:
19477 case VPANDNDZrm:
19478 case VPANDNDZrmb:
19479 case VPANDNDZrmbk:
19480 case VPANDNDZrmbkz:
19481 case VPANDNDZrmk:
19482 case VPANDNDZrmkz:
19483 case VPANDNDZrr:
19484 case VPANDNDZrrk:
19485 case VPANDNDZrrkz:
19486 return true;
19487 }
19488 return false;
19489}
19490
19491bool isVPMOVSDB(unsigned Opcode) {
19492 switch (Opcode) {
19493 case VPMOVSDBZ128mr:
19494 case VPMOVSDBZ128mrk:
19495 case VPMOVSDBZ128rr:
19496 case VPMOVSDBZ128rrk:
19497 case VPMOVSDBZ128rrkz:
19498 case VPMOVSDBZ256mr:
19499 case VPMOVSDBZ256mrk:
19500 case VPMOVSDBZ256rr:
19501 case VPMOVSDBZ256rrk:
19502 case VPMOVSDBZ256rrkz:
19503 case VPMOVSDBZmr:
19504 case VPMOVSDBZmrk:
19505 case VPMOVSDBZrr:
19506 case VPMOVSDBZrrk:
19507 case VPMOVSDBZrrkz:
19508 return true;
19509 }
19510 return false;
19511}
19512
19513bool isVPBROADCASTB(unsigned Opcode) {
19514 switch (Opcode) {
19515 case VPBROADCASTBYrm:
19516 case VPBROADCASTBYrr:
19517 case VPBROADCASTBZ128rm:
19518 case VPBROADCASTBZ128rmk:
19519 case VPBROADCASTBZ128rmkz:
19520 case VPBROADCASTBZ128rr:
19521 case VPBROADCASTBZ128rrk:
19522 case VPBROADCASTBZ128rrkz:
19523 case VPBROADCASTBZ256rm:
19524 case VPBROADCASTBZ256rmk:
19525 case VPBROADCASTBZ256rmkz:
19526 case VPBROADCASTBZ256rr:
19527 case VPBROADCASTBZ256rrk:
19528 case VPBROADCASTBZ256rrkz:
19529 case VPBROADCASTBZrm:
19530 case VPBROADCASTBZrmk:
19531 case VPBROADCASTBZrmkz:
19532 case VPBROADCASTBZrr:
19533 case VPBROADCASTBZrrk:
19534 case VPBROADCASTBZrrkz:
19535 case VPBROADCASTBrZ128rr:
19536 case VPBROADCASTBrZ128rrk:
19537 case VPBROADCASTBrZ128rrkz:
19538 case VPBROADCASTBrZ256rr:
19539 case VPBROADCASTBrZ256rrk:
19540 case VPBROADCASTBrZ256rrkz:
19541 case VPBROADCASTBrZrr:
19542 case VPBROADCASTBrZrrk:
19543 case VPBROADCASTBrZrrkz:
19544 case VPBROADCASTBrm:
19545 case VPBROADCASTBrr:
19546 return true;
19547 }
19548 return false;
19549}
19550
19551bool isCVTPI2PD(unsigned Opcode) {
19552 switch (Opcode) {
19553 case MMX_CVTPI2PDrm:
19554 case MMX_CVTPI2PDrr:
19555 return true;
19556 }
19557 return false;
19558}
19559
19560bool isVPERMI2B(unsigned Opcode) {
19561 switch (Opcode) {
19562 case VPERMI2BZ128rm:
19563 case VPERMI2BZ128rmk:
19564 case VPERMI2BZ128rmkz:
19565 case VPERMI2BZ128rr:
19566 case VPERMI2BZ128rrk:
19567 case VPERMI2BZ128rrkz:
19568 case VPERMI2BZ256rm:
19569 case VPERMI2BZ256rmk:
19570 case VPERMI2BZ256rmkz:
19571 case VPERMI2BZ256rr:
19572 case VPERMI2BZ256rrk:
19573 case VPERMI2BZ256rrkz:
19574 case VPERMI2BZrm:
19575 case VPERMI2BZrmk:
19576 case VPERMI2BZrmkz:
19577 case VPERMI2BZrr:
19578 case VPERMI2BZrrk:
19579 case VPERMI2BZrrkz:
19580 return true;
19581 }
19582 return false;
19583}
19584
19585bool isVPMINSB(unsigned Opcode) {
19586 switch (Opcode) {
19587 case VPMINSBYrm:
19588 case VPMINSBYrr:
19589 case VPMINSBZ128rm:
19590 case VPMINSBZ128rmk:
19591 case VPMINSBZ128rmkz:
19592 case VPMINSBZ128rr:
19593 case VPMINSBZ128rrk:
19594 case VPMINSBZ128rrkz:
19595 case VPMINSBZ256rm:
19596 case VPMINSBZ256rmk:
19597 case VPMINSBZ256rmkz:
19598 case VPMINSBZ256rr:
19599 case VPMINSBZ256rrk:
19600 case VPMINSBZ256rrkz:
19601 case VPMINSBZrm:
19602 case VPMINSBZrmk:
19603 case VPMINSBZrmkz:
19604 case VPMINSBZrr:
19605 case VPMINSBZrrk:
19606 case VPMINSBZrrkz:
19607 case VPMINSBrm:
19608 case VPMINSBrr:
19609 return true;
19610 }
19611 return false;
19612}
19613
19614bool isLAR(unsigned Opcode) {
19615 switch (Opcode) {
19616 case LAR16rm:
19617 case LAR16rr:
19618 case LAR32rm:
19619 case LAR32rr:
19620 case LAR64rm:
19621 case LAR64rr:
19622 return true;
19623 }
19624 return false;
19625}
19626
19627bool isINVLPGB(unsigned Opcode) {
19628 switch (Opcode) {
19629 case INVLPGB32:
19630 case INVLPGB64:
19631 return true;
19632 }
19633 return false;
19634}
19635
19636bool isTLBSYNC(unsigned Opcode) {
19637 return Opcode == TLBSYNC;
19638}
19639
19640bool isFDIVP(unsigned Opcode) {
19641 return Opcode == DIV_FPrST0;
19642}
19643
19644bool isVPSRLW(unsigned Opcode) {
19645 switch (Opcode) {
19646 case VPSRLWYri:
19647 case VPSRLWYrm:
19648 case VPSRLWYrr:
19649 case VPSRLWZ128mi:
19650 case VPSRLWZ128mik:
19651 case VPSRLWZ128mikz:
19652 case VPSRLWZ128ri:
19653 case VPSRLWZ128rik:
19654 case VPSRLWZ128rikz:
19655 case VPSRLWZ128rm:
19656 case VPSRLWZ128rmk:
19657 case VPSRLWZ128rmkz:
19658 case VPSRLWZ128rr:
19659 case VPSRLWZ128rrk:
19660 case VPSRLWZ128rrkz:
19661 case VPSRLWZ256mi:
19662 case VPSRLWZ256mik:
19663 case VPSRLWZ256mikz:
19664 case VPSRLWZ256ri:
19665 case VPSRLWZ256rik:
19666 case VPSRLWZ256rikz:
19667 case VPSRLWZ256rm:
19668 case VPSRLWZ256rmk:
19669 case VPSRLWZ256rmkz:
19670 case VPSRLWZ256rr:
19671 case VPSRLWZ256rrk:
19672 case VPSRLWZ256rrkz:
19673 case VPSRLWZmi:
19674 case VPSRLWZmik:
19675 case VPSRLWZmikz:
19676 case VPSRLWZri:
19677 case VPSRLWZrik:
19678 case VPSRLWZrikz:
19679 case VPSRLWZrm:
19680 case VPSRLWZrmk:
19681 case VPSRLWZrmkz:
19682 case VPSRLWZrr:
19683 case VPSRLWZrrk:
19684 case VPSRLWZrrkz:
19685 case VPSRLWri:
19686 case VPSRLWrm:
19687 case VPSRLWrr:
19688 return true;
19689 }
19690 return false;
19691}
19692
19693bool isVRCP28SS(unsigned Opcode) {
19694 switch (Opcode) {
19695 case VRCP28SSZm:
19696 case VRCP28SSZmk:
19697 case VRCP28SSZmkz:
19698 case VRCP28SSZr:
19699 case VRCP28SSZrb:
19700 case VRCP28SSZrbk:
19701 case VRCP28SSZrbkz:
19702 case VRCP28SSZrk:
19703 case VRCP28SSZrkz:
19704 return true;
19705 }
19706 return false;
19707}
19708
19709bool isVMOVHPS(unsigned Opcode) {
19710 switch (Opcode) {
19711 case VMOVHPSZ128mr:
19712 case VMOVHPSZ128rm:
19713 case VMOVHPSmr:
19714 case VMOVHPSrm:
19715 return true;
19716 }
19717 return false;
19718}
19719
19720bool isVPMACSSDD(unsigned Opcode) {
19721 switch (Opcode) {
19722 case VPMACSSDDrm:
19723 case VPMACSSDDrr:
19724 return true;
19725 }
19726 return false;
19727}
19728
19729bool isPEXT(unsigned Opcode) {
19730 switch (Opcode) {
19731 case PEXT32rm:
19732 case PEXT32rm_EVEX:
19733 case PEXT32rr:
19734 case PEXT32rr_EVEX:
19735 case PEXT64rm:
19736 case PEXT64rm_EVEX:
19737 case PEXT64rr:
19738 case PEXT64rr_EVEX:
19739 return true;
19740 }
19741 return false;
19742}
19743
19744bool isVRSQRT14SD(unsigned Opcode) {
19745 switch (Opcode) {
19746 case VRSQRT14SDZrm:
19747 case VRSQRT14SDZrmk:
19748 case VRSQRT14SDZrmkz:
19749 case VRSQRT14SDZrr:
19750 case VRSQRT14SDZrrk:
19751 case VRSQRT14SDZrrkz:
19752 return true;
19753 }
19754 return false;
19755}
19756
19757bool isVPDPWSSD(unsigned Opcode) {
19758 switch (Opcode) {
19759 case VPDPWSSDYrm:
19760 case VPDPWSSDYrr:
19761 case VPDPWSSDZ128m:
19762 case VPDPWSSDZ128mb:
19763 case VPDPWSSDZ128mbk:
19764 case VPDPWSSDZ128mbkz:
19765 case VPDPWSSDZ128mk:
19766 case VPDPWSSDZ128mkz:
19767 case VPDPWSSDZ128r:
19768 case VPDPWSSDZ128rk:
19769 case VPDPWSSDZ128rkz:
19770 case VPDPWSSDZ256m:
19771 case VPDPWSSDZ256mb:
19772 case VPDPWSSDZ256mbk:
19773 case VPDPWSSDZ256mbkz:
19774 case VPDPWSSDZ256mk:
19775 case VPDPWSSDZ256mkz:
19776 case VPDPWSSDZ256r:
19777 case VPDPWSSDZ256rk:
19778 case VPDPWSSDZ256rkz:
19779 case VPDPWSSDZm:
19780 case VPDPWSSDZmb:
19781 case VPDPWSSDZmbk:
19782 case VPDPWSSDZmbkz:
19783 case VPDPWSSDZmk:
19784 case VPDPWSSDZmkz:
19785 case VPDPWSSDZr:
19786 case VPDPWSSDZrk:
19787 case VPDPWSSDZrkz:
19788 case VPDPWSSDrm:
19789 case VPDPWSSDrr:
19790 return true;
19791 }
19792 return false;
19793}
19794
19795bool isVFMSUB231SD(unsigned Opcode) {
19796 switch (Opcode) {
19797 case VFMSUB231SDZm_Int:
19798 case VFMSUB231SDZm_Intk:
19799 case VFMSUB231SDZm_Intkz:
19800 case VFMSUB231SDZr_Int:
19801 case VFMSUB231SDZr_Intk:
19802 case VFMSUB231SDZr_Intkz:
19803 case VFMSUB231SDZrb_Int:
19804 case VFMSUB231SDZrb_Intk:
19805 case VFMSUB231SDZrb_Intkz:
19806 case VFMSUB231SDm_Int:
19807 case VFMSUB231SDr_Int:
19808 return true;
19809 }
19810 return false;
19811}
19812
19813bool isVPMOVZXWQ(unsigned Opcode) {
19814 switch (Opcode) {
19815 case VPMOVZXWQYrm:
19816 case VPMOVZXWQYrr:
19817 case VPMOVZXWQZ128rm:
19818 case VPMOVZXWQZ128rmk:
19819 case VPMOVZXWQZ128rmkz:
19820 case VPMOVZXWQZ128rr:
19821 case VPMOVZXWQZ128rrk:
19822 case VPMOVZXWQZ128rrkz:
19823 case VPMOVZXWQZ256rm:
19824 case VPMOVZXWQZ256rmk:
19825 case VPMOVZXWQZ256rmkz:
19826 case VPMOVZXWQZ256rr:
19827 case VPMOVZXWQZ256rrk:
19828 case VPMOVZXWQZ256rrkz:
19829 case VPMOVZXWQZrm:
19830 case VPMOVZXWQZrmk:
19831 case VPMOVZXWQZrmkz:
19832 case VPMOVZXWQZrr:
19833 case VPMOVZXWQZrrk:
19834 case VPMOVZXWQZrrkz:
19835 case VPMOVZXWQrm:
19836 case VPMOVZXWQrr:
19837 return true;
19838 }
19839 return false;
19840}
19841
19842bool isVMOVDQA(unsigned Opcode) {
19843 switch (Opcode) {
19844 case VMOVDQAYmr:
19845 case VMOVDQAYrm:
19846 case VMOVDQAYrr:
19847 case VMOVDQAYrr_REV:
19848 case VMOVDQAmr:
19849 case VMOVDQArm:
19850 case VMOVDQArr:
19851 case VMOVDQArr_REV:
19852 return true;
19853 }
19854 return false;
19855}
19856
19857bool isVFNMSUB213SD(unsigned Opcode) {
19858 switch (Opcode) {
19859 case VFNMSUB213SDZm_Int:
19860 case VFNMSUB213SDZm_Intk:
19861 case VFNMSUB213SDZm_Intkz:
19862 case VFNMSUB213SDZr_Int:
19863 case VFNMSUB213SDZr_Intk:
19864 case VFNMSUB213SDZr_Intkz:
19865 case VFNMSUB213SDZrb_Int:
19866 case VFNMSUB213SDZrb_Intk:
19867 case VFNMSUB213SDZrb_Intkz:
19868 case VFNMSUB213SDm_Int:
19869 case VFNMSUB213SDr_Int:
19870 return true;
19871 }
19872 return false;
19873}
19874
19875bool isVMINPS(unsigned Opcode) {
19876 switch (Opcode) {
19877 case VMINPSYrm:
19878 case VMINPSYrr:
19879 case VMINPSZ128rm:
19880 case VMINPSZ128rmb:
19881 case VMINPSZ128rmbk:
19882 case VMINPSZ128rmbkz:
19883 case VMINPSZ128rmk:
19884 case VMINPSZ128rmkz:
19885 case VMINPSZ128rr:
19886 case VMINPSZ128rrk:
19887 case VMINPSZ128rrkz:
19888 case VMINPSZ256rm:
19889 case VMINPSZ256rmb:
19890 case VMINPSZ256rmbk:
19891 case VMINPSZ256rmbkz:
19892 case VMINPSZ256rmk:
19893 case VMINPSZ256rmkz:
19894 case VMINPSZ256rr:
19895 case VMINPSZ256rrk:
19896 case VMINPSZ256rrkz:
19897 case VMINPSZrm:
19898 case VMINPSZrmb:
19899 case VMINPSZrmbk:
19900 case VMINPSZrmbkz:
19901 case VMINPSZrmk:
19902 case VMINPSZrmkz:
19903 case VMINPSZrr:
19904 case VMINPSZrrb:
19905 case VMINPSZrrbk:
19906 case VMINPSZrrbkz:
19907 case VMINPSZrrk:
19908 case VMINPSZrrkz:
19909 case VMINPSrm:
19910 case VMINPSrr:
19911 return true;
19912 }
19913 return false;
19914}
19915
19916bool isVFMSUB231PS(unsigned Opcode) {
19917 switch (Opcode) {
19918 case VFMSUB231PSYm:
19919 case VFMSUB231PSYr:
19920 case VFMSUB231PSZ128m:
19921 case VFMSUB231PSZ128mb:
19922 case VFMSUB231PSZ128mbk:
19923 case VFMSUB231PSZ128mbkz:
19924 case VFMSUB231PSZ128mk:
19925 case VFMSUB231PSZ128mkz:
19926 case VFMSUB231PSZ128r:
19927 case VFMSUB231PSZ128rk:
19928 case VFMSUB231PSZ128rkz:
19929 case VFMSUB231PSZ256m:
19930 case VFMSUB231PSZ256mb:
19931 case VFMSUB231PSZ256mbk:
19932 case VFMSUB231PSZ256mbkz:
19933 case VFMSUB231PSZ256mk:
19934 case VFMSUB231PSZ256mkz:
19935 case VFMSUB231PSZ256r:
19936 case VFMSUB231PSZ256rk:
19937 case VFMSUB231PSZ256rkz:
19938 case VFMSUB231PSZm:
19939 case VFMSUB231PSZmb:
19940 case VFMSUB231PSZmbk:
19941 case VFMSUB231PSZmbkz:
19942 case VFMSUB231PSZmk:
19943 case VFMSUB231PSZmkz:
19944 case VFMSUB231PSZr:
19945 case VFMSUB231PSZrb:
19946 case VFMSUB231PSZrbk:
19947 case VFMSUB231PSZrbkz:
19948 case VFMSUB231PSZrk:
19949 case VFMSUB231PSZrkz:
19950 case VFMSUB231PSm:
19951 case VFMSUB231PSr:
19952 return true;
19953 }
19954 return false;
19955}
19956
19957bool isVPCOMPRESSB(unsigned Opcode) {
19958 switch (Opcode) {
19959 case VPCOMPRESSBZ128mr:
19960 case VPCOMPRESSBZ128mrk:
19961 case VPCOMPRESSBZ128rr:
19962 case VPCOMPRESSBZ128rrk:
19963 case VPCOMPRESSBZ128rrkz:
19964 case VPCOMPRESSBZ256mr:
19965 case VPCOMPRESSBZ256mrk:
19966 case VPCOMPRESSBZ256rr:
19967 case VPCOMPRESSBZ256rrk:
19968 case VPCOMPRESSBZ256rrkz:
19969 case VPCOMPRESSBZmr:
19970 case VPCOMPRESSBZmrk:
19971 case VPCOMPRESSBZrr:
19972 case VPCOMPRESSBZrrk:
19973 case VPCOMPRESSBZrrkz:
19974 return true;
19975 }
19976 return false;
19977}
19978
19979bool isVPCMPEQQ(unsigned Opcode) {
19980 switch (Opcode) {
19981 case VPCMPEQQYrm:
19982 case VPCMPEQQYrr:
19983 case VPCMPEQQZ128rm:
19984 case VPCMPEQQZ128rmb:
19985 case VPCMPEQQZ128rmbk:
19986 case VPCMPEQQZ128rmk:
19987 case VPCMPEQQZ128rr:
19988 case VPCMPEQQZ128rrk:
19989 case VPCMPEQQZ256rm:
19990 case VPCMPEQQZ256rmb:
19991 case VPCMPEQQZ256rmbk:
19992 case VPCMPEQQZ256rmk:
19993 case VPCMPEQQZ256rr:
19994 case VPCMPEQQZ256rrk:
19995 case VPCMPEQQZrm:
19996 case VPCMPEQQZrmb:
19997 case VPCMPEQQZrmbk:
19998 case VPCMPEQQZrmk:
19999 case VPCMPEQQZrr:
20000 case VPCMPEQQZrrk:
20001 case VPCMPEQQrm:
20002 case VPCMPEQQrr:
20003 return true;
20004 }
20005 return false;
20006}
20007
20008bool isVRCPSS(unsigned Opcode) {
20009 switch (Opcode) {
20010 case VRCPSSm_Int:
20011 case VRCPSSr_Int:
20012 return true;
20013 }
20014 return false;
20015}
20016
20017bool isVSCATTERPF1DPS(unsigned Opcode) {
20018 return Opcode == VSCATTERPF1DPSm;
20019}
20020
20021bool isVPHADDUBW(unsigned Opcode) {
20022 switch (Opcode) {
20023 case VPHADDUBWrm:
20024 case VPHADDUBWrr:
20025 return true;
20026 }
20027 return false;
20028}
20029
20030bool isXORPD(unsigned Opcode) {
20031 switch (Opcode) {
20032 case XORPDrm:
20033 case XORPDrr:
20034 return true;
20035 }
20036 return false;
20037}
20038
20039bool isVPSCATTERQQ(unsigned Opcode) {
20040 switch (Opcode) {
20041 case VPSCATTERQQZ128mr:
20042 case VPSCATTERQQZ256mr:
20043 case VPSCATTERQQZmr:
20044 return true;
20045 }
20046 return false;
20047}
20048
20049bool isVCVTW2PH(unsigned Opcode) {
20050 switch (Opcode) {
20051 case VCVTW2PHZ128rm:
20052 case VCVTW2PHZ128rmb:
20053 case VCVTW2PHZ128rmbk:
20054 case VCVTW2PHZ128rmbkz:
20055 case VCVTW2PHZ128rmk:
20056 case VCVTW2PHZ128rmkz:
20057 case VCVTW2PHZ128rr:
20058 case VCVTW2PHZ128rrk:
20059 case VCVTW2PHZ128rrkz:
20060 case VCVTW2PHZ256rm:
20061 case VCVTW2PHZ256rmb:
20062 case VCVTW2PHZ256rmbk:
20063 case VCVTW2PHZ256rmbkz:
20064 case VCVTW2PHZ256rmk:
20065 case VCVTW2PHZ256rmkz:
20066 case VCVTW2PHZ256rr:
20067 case VCVTW2PHZ256rrk:
20068 case VCVTW2PHZ256rrkz:
20069 case VCVTW2PHZrm:
20070 case VCVTW2PHZrmb:
20071 case VCVTW2PHZrmbk:
20072 case VCVTW2PHZrmbkz:
20073 case VCVTW2PHZrmk:
20074 case VCVTW2PHZrmkz:
20075 case VCVTW2PHZrr:
20076 case VCVTW2PHZrrb:
20077 case VCVTW2PHZrrbk:
20078 case VCVTW2PHZrrbkz:
20079 case VCVTW2PHZrrk:
20080 case VCVTW2PHZrrkz:
20081 return true;
20082 }
20083 return false;
20084}
20085
20086bool isVFMADDCPH(unsigned Opcode) {
20087 switch (Opcode) {
20088 case VFMADDCPHZ128m:
20089 case VFMADDCPHZ128mb:
20090 case VFMADDCPHZ128mbk:
20091 case VFMADDCPHZ128mbkz:
20092 case VFMADDCPHZ128mk:
20093 case VFMADDCPHZ128mkz:
20094 case VFMADDCPHZ128r:
20095 case VFMADDCPHZ128rk:
20096 case VFMADDCPHZ128rkz:
20097 case VFMADDCPHZ256m:
20098 case VFMADDCPHZ256mb:
20099 case VFMADDCPHZ256mbk:
20100 case VFMADDCPHZ256mbkz:
20101 case VFMADDCPHZ256mk:
20102 case VFMADDCPHZ256mkz:
20103 case VFMADDCPHZ256r:
20104 case VFMADDCPHZ256rk:
20105 case VFMADDCPHZ256rkz:
20106 case VFMADDCPHZm:
20107 case VFMADDCPHZmb:
20108 case VFMADDCPHZmbk:
20109 case VFMADDCPHZmbkz:
20110 case VFMADDCPHZmk:
20111 case VFMADDCPHZmkz:
20112 case VFMADDCPHZr:
20113 case VFMADDCPHZrb:
20114 case VFMADDCPHZrbk:
20115 case VFMADDCPHZrbkz:
20116 case VFMADDCPHZrk:
20117 case VFMADDCPHZrkz:
20118 return true;
20119 }
20120 return false;
20121}
20122
20123bool isVSUBPD(unsigned Opcode) {
20124 switch (Opcode) {
20125 case VSUBPDYrm:
20126 case VSUBPDYrr:
20127 case VSUBPDZ128rm:
20128 case VSUBPDZ128rmb:
20129 case VSUBPDZ128rmbk:
20130 case VSUBPDZ128rmbkz:
20131 case VSUBPDZ128rmk:
20132 case VSUBPDZ128rmkz:
20133 case VSUBPDZ128rr:
20134 case VSUBPDZ128rrk:
20135 case VSUBPDZ128rrkz:
20136 case VSUBPDZ256rm:
20137 case VSUBPDZ256rmb:
20138 case VSUBPDZ256rmbk:
20139 case VSUBPDZ256rmbkz:
20140 case VSUBPDZ256rmk:
20141 case VSUBPDZ256rmkz:
20142 case VSUBPDZ256rr:
20143 case VSUBPDZ256rrk:
20144 case VSUBPDZ256rrkz:
20145 case VSUBPDZrm:
20146 case VSUBPDZrmb:
20147 case VSUBPDZrmbk:
20148 case VSUBPDZrmbkz:
20149 case VSUBPDZrmk:
20150 case VSUBPDZrmkz:
20151 case VSUBPDZrr:
20152 case VSUBPDZrrb:
20153 case VSUBPDZrrbk:
20154 case VSUBPDZrrbkz:
20155 case VSUBPDZrrk:
20156 case VSUBPDZrrkz:
20157 case VSUBPDrm:
20158 case VSUBPDrr:
20159 return true;
20160 }
20161 return false;
20162}
20163
20164bool isVPACKUSDW(unsigned Opcode) {
20165 switch (Opcode) {
20166 case VPACKUSDWYrm:
20167 case VPACKUSDWYrr:
20168 case VPACKUSDWZ128rm:
20169 case VPACKUSDWZ128rmb:
20170 case VPACKUSDWZ128rmbk:
20171 case VPACKUSDWZ128rmbkz:
20172 case VPACKUSDWZ128rmk:
20173 case VPACKUSDWZ128rmkz:
20174 case VPACKUSDWZ128rr:
20175 case VPACKUSDWZ128rrk:
20176 case VPACKUSDWZ128rrkz:
20177 case VPACKUSDWZ256rm:
20178 case VPACKUSDWZ256rmb:
20179 case VPACKUSDWZ256rmbk:
20180 case VPACKUSDWZ256rmbkz:
20181 case VPACKUSDWZ256rmk:
20182 case VPACKUSDWZ256rmkz:
20183 case VPACKUSDWZ256rr:
20184 case VPACKUSDWZ256rrk:
20185 case VPACKUSDWZ256rrkz:
20186 case VPACKUSDWZrm:
20187 case VPACKUSDWZrmb:
20188 case VPACKUSDWZrmbk:
20189 case VPACKUSDWZrmbkz:
20190 case VPACKUSDWZrmk:
20191 case VPACKUSDWZrmkz:
20192 case VPACKUSDWZrr:
20193 case VPACKUSDWZrrk:
20194 case VPACKUSDWZrrkz:
20195 case VPACKUSDWrm:
20196 case VPACKUSDWrr:
20197 return true;
20198 }
20199 return false;
20200}
20201
20202bool isVSCALEFSS(unsigned Opcode) {
20203 switch (Opcode) {
20204 case VSCALEFSSZrm:
20205 case VSCALEFSSZrmk:
20206 case VSCALEFSSZrmkz:
20207 case VSCALEFSSZrr:
20208 case VSCALEFSSZrrb_Int:
20209 case VSCALEFSSZrrb_Intk:
20210 case VSCALEFSSZrrb_Intkz:
20211 case VSCALEFSSZrrk:
20212 case VSCALEFSSZrrkz:
20213 return true;
20214 }
20215 return false;
20216}
20217
20218bool isAESIMC(unsigned Opcode) {
20219 switch (Opcode) {
20220 case AESIMCrm:
20221 case AESIMCrr:
20222 return true;
20223 }
20224 return false;
20225}
20226
20227bool isVRCP28PS(unsigned Opcode) {
20228 switch (Opcode) {
20229 case VRCP28PSZm:
20230 case VRCP28PSZmb:
20231 case VRCP28PSZmbk:
20232 case VRCP28PSZmbkz:
20233 case VRCP28PSZmk:
20234 case VRCP28PSZmkz:
20235 case VRCP28PSZr:
20236 case VRCP28PSZrb:
20237 case VRCP28PSZrbk:
20238 case VRCP28PSZrbkz:
20239 case VRCP28PSZrk:
20240 case VRCP28PSZrkz:
20241 return true;
20242 }
20243 return false;
20244}
20245
20246bool isAAND(unsigned Opcode) {
20247 switch (Opcode) {
20248 case AAND32mr:
20249 case AAND32mr_EVEX:
20250 case AAND64mr:
20251 case AAND64mr_EVEX:
20252 return true;
20253 }
20254 return false;
20255}
20256
20257bool isDAA(unsigned Opcode) {
20258 return Opcode == DAA;
20259}
20260
20261bool isVCVTPD2UDQ(unsigned Opcode) {
20262 switch (Opcode) {
20263 case VCVTPD2UDQZ128rm:
20264 case VCVTPD2UDQZ128rmb:
20265 case VCVTPD2UDQZ128rmbk:
20266 case VCVTPD2UDQZ128rmbkz:
20267 case VCVTPD2UDQZ128rmk:
20268 case VCVTPD2UDQZ128rmkz:
20269 case VCVTPD2UDQZ128rr:
20270 case VCVTPD2UDQZ128rrk:
20271 case VCVTPD2UDQZ128rrkz:
20272 case VCVTPD2UDQZ256rm:
20273 case VCVTPD2UDQZ256rmb:
20274 case VCVTPD2UDQZ256rmbk:
20275 case VCVTPD2UDQZ256rmbkz:
20276 case VCVTPD2UDQZ256rmk:
20277 case VCVTPD2UDQZ256rmkz:
20278 case VCVTPD2UDQZ256rr:
20279 case VCVTPD2UDQZ256rrk:
20280 case VCVTPD2UDQZ256rrkz:
20281 case VCVTPD2UDQZrm:
20282 case VCVTPD2UDQZrmb:
20283 case VCVTPD2UDQZrmbk:
20284 case VCVTPD2UDQZrmbkz:
20285 case VCVTPD2UDQZrmk:
20286 case VCVTPD2UDQZrmkz:
20287 case VCVTPD2UDQZrr:
20288 case VCVTPD2UDQZrrb:
20289 case VCVTPD2UDQZrrbk:
20290 case VCVTPD2UDQZrrbkz:
20291 case VCVTPD2UDQZrrk:
20292 case VCVTPD2UDQZrrkz:
20293 return true;
20294 }
20295 return false;
20296}
20297
20298bool isKTESTW(unsigned Opcode) {
20299 return Opcode == KTESTWrr;
20300}
20301
20302bool isVPADDQ(unsigned Opcode) {
20303 switch (Opcode) {
20304 case VPADDQYrm:
20305 case VPADDQYrr:
20306 case VPADDQZ128rm:
20307 case VPADDQZ128rmb:
20308 case VPADDQZ128rmbk:
20309 case VPADDQZ128rmbkz:
20310 case VPADDQZ128rmk:
20311 case VPADDQZ128rmkz:
20312 case VPADDQZ128rr:
20313 case VPADDQZ128rrk:
20314 case VPADDQZ128rrkz:
20315 case VPADDQZ256rm:
20316 case VPADDQZ256rmb:
20317 case VPADDQZ256rmbk:
20318 case VPADDQZ256rmbkz:
20319 case VPADDQZ256rmk:
20320 case VPADDQZ256rmkz:
20321 case VPADDQZ256rr:
20322 case VPADDQZ256rrk:
20323 case VPADDQZ256rrkz:
20324 case VPADDQZrm:
20325 case VPADDQZrmb:
20326 case VPADDQZrmbk:
20327 case VPADDQZrmbkz:
20328 case VPADDQZrmk:
20329 case VPADDQZrmkz:
20330 case VPADDQZrr:
20331 case VPADDQZrrk:
20332 case VPADDQZrrkz:
20333 case VPADDQrm:
20334 case VPADDQrr:
20335 return true;
20336 }
20337 return false;
20338}
20339
20340bool isPALIGNR(unsigned Opcode) {
20341 switch (Opcode) {
20342 case MMX_PALIGNRrmi:
20343 case MMX_PALIGNRrri:
20344 case PALIGNRrmi:
20345 case PALIGNRrri:
20346 return true;
20347 }
20348 return false;
20349}
20350
20351bool isPMAXUW(unsigned Opcode) {
20352 switch (Opcode) {
20353 case PMAXUWrm:
20354 case PMAXUWrr:
20355 return true;
20356 }
20357 return false;
20358}
20359
20360bool isVFMADDSD(unsigned Opcode) {
20361 switch (Opcode) {
20362 case VFMADDSD4mr:
20363 case VFMADDSD4rm:
20364 case VFMADDSD4rr:
20365 case VFMADDSD4rr_REV:
20366 return true;
20367 }
20368 return false;
20369}
20370
20371bool isPFMAX(unsigned Opcode) {
20372 switch (Opcode) {
20373 case PFMAXrm:
20374 case PFMAXrr:
20375 return true;
20376 }
20377 return false;
20378}
20379
20380bool isVPOR(unsigned Opcode) {
20381 switch (Opcode) {
20382 case VPORYrm:
20383 case VPORYrr:
20384 case VPORrm:
20385 case VPORrr:
20386 return true;
20387 }
20388 return false;
20389}
20390
20391bool isVPSUBB(unsigned Opcode) {
20392 switch (Opcode) {
20393 case VPSUBBYrm:
20394 case VPSUBBYrr:
20395 case VPSUBBZ128rm:
20396 case VPSUBBZ128rmk:
20397 case VPSUBBZ128rmkz:
20398 case VPSUBBZ128rr:
20399 case VPSUBBZ128rrk:
20400 case VPSUBBZ128rrkz:
20401 case VPSUBBZ256rm:
20402 case VPSUBBZ256rmk:
20403 case VPSUBBZ256rmkz:
20404 case VPSUBBZ256rr:
20405 case VPSUBBZ256rrk:
20406 case VPSUBBZ256rrkz:
20407 case VPSUBBZrm:
20408 case VPSUBBZrmk:
20409 case VPSUBBZrmkz:
20410 case VPSUBBZrr:
20411 case VPSUBBZrrk:
20412 case VPSUBBZrrkz:
20413 case VPSUBBrm:
20414 case VPSUBBrr:
20415 return true;
20416 }
20417 return false;
20418}
20419
20420bool isVPAVGB(unsigned Opcode) {
20421 switch (Opcode) {
20422 case VPAVGBYrm:
20423 case VPAVGBYrr:
20424 case VPAVGBZ128rm:
20425 case VPAVGBZ128rmk:
20426 case VPAVGBZ128rmkz:
20427 case VPAVGBZ128rr:
20428 case VPAVGBZ128rrk:
20429 case VPAVGBZ128rrkz:
20430 case VPAVGBZ256rm:
20431 case VPAVGBZ256rmk:
20432 case VPAVGBZ256rmkz:
20433 case VPAVGBZ256rr:
20434 case VPAVGBZ256rrk:
20435 case VPAVGBZ256rrkz:
20436 case VPAVGBZrm:
20437 case VPAVGBZrmk:
20438 case VPAVGBZrmkz:
20439 case VPAVGBZrr:
20440 case VPAVGBZrrk:
20441 case VPAVGBZrrkz:
20442 case VPAVGBrm:
20443 case VPAVGBrr:
20444 return true;
20445 }
20446 return false;
20447}
20448
20449bool isINSB(unsigned Opcode) {
20450 return Opcode == INSB;
20451}
20452
20453bool isFYL2X(unsigned Opcode) {
20454 return Opcode == FYL2X;
20455}
20456
20457bool isVFNMSUB132PD(unsigned Opcode) {
20458 switch (Opcode) {
20459 case VFNMSUB132PDYm:
20460 case VFNMSUB132PDYr:
20461 case VFNMSUB132PDZ128m:
20462 case VFNMSUB132PDZ128mb:
20463 case VFNMSUB132PDZ128mbk:
20464 case VFNMSUB132PDZ128mbkz:
20465 case VFNMSUB132PDZ128mk:
20466 case VFNMSUB132PDZ128mkz:
20467 case VFNMSUB132PDZ128r:
20468 case VFNMSUB132PDZ128rk:
20469 case VFNMSUB132PDZ128rkz:
20470 case VFNMSUB132PDZ256m:
20471 case VFNMSUB132PDZ256mb:
20472 case VFNMSUB132PDZ256mbk:
20473 case VFNMSUB132PDZ256mbkz:
20474 case VFNMSUB132PDZ256mk:
20475 case VFNMSUB132PDZ256mkz:
20476 case VFNMSUB132PDZ256r:
20477 case VFNMSUB132PDZ256rk:
20478 case VFNMSUB132PDZ256rkz:
20479 case VFNMSUB132PDZm:
20480 case VFNMSUB132PDZmb:
20481 case VFNMSUB132PDZmbk:
20482 case VFNMSUB132PDZmbkz:
20483 case VFNMSUB132PDZmk:
20484 case VFNMSUB132PDZmkz:
20485 case VFNMSUB132PDZr:
20486 case VFNMSUB132PDZrb:
20487 case VFNMSUB132PDZrbk:
20488 case VFNMSUB132PDZrbkz:
20489 case VFNMSUB132PDZrk:
20490 case VFNMSUB132PDZrkz:
20491 case VFNMSUB132PDm:
20492 case VFNMSUB132PDr:
20493 return true;
20494 }
20495 return false;
20496}
20497
20498bool isVFNMSUBPS(unsigned Opcode) {
20499 switch (Opcode) {
20500 case VFNMSUBPS4Ymr:
20501 case VFNMSUBPS4Yrm:
20502 case VFNMSUBPS4Yrr:
20503 case VFNMSUBPS4Yrr_REV:
20504 case VFNMSUBPS4mr:
20505 case VFNMSUBPS4rm:
20506 case VFNMSUBPS4rr:
20507 case VFNMSUBPS4rr_REV:
20508 return true;
20509 }
20510 return false;
20511}
20512
20513bool isVFMADD231PS(unsigned Opcode) {
20514 switch (Opcode) {
20515 case VFMADD231PSYm:
20516 case VFMADD231PSYr:
20517 case VFMADD231PSZ128m:
20518 case VFMADD231PSZ128mb:
20519 case VFMADD231PSZ128mbk:
20520 case VFMADD231PSZ128mbkz:
20521 case VFMADD231PSZ128mk:
20522 case VFMADD231PSZ128mkz:
20523 case VFMADD231PSZ128r:
20524 case VFMADD231PSZ128rk:
20525 case VFMADD231PSZ128rkz:
20526 case VFMADD231PSZ256m:
20527 case VFMADD231PSZ256mb:
20528 case VFMADD231PSZ256mbk:
20529 case VFMADD231PSZ256mbkz:
20530 case VFMADD231PSZ256mk:
20531 case VFMADD231PSZ256mkz:
20532 case VFMADD231PSZ256r:
20533 case VFMADD231PSZ256rk:
20534 case VFMADD231PSZ256rkz:
20535 case VFMADD231PSZm:
20536 case VFMADD231PSZmb:
20537 case VFMADD231PSZmbk:
20538 case VFMADD231PSZmbkz:
20539 case VFMADD231PSZmk:
20540 case VFMADD231PSZmkz:
20541 case VFMADD231PSZr:
20542 case VFMADD231PSZrb:
20543 case VFMADD231PSZrbk:
20544 case VFMADD231PSZrbkz:
20545 case VFMADD231PSZrk:
20546 case VFMADD231PSZrkz:
20547 case VFMADD231PSm:
20548 case VFMADD231PSr:
20549 return true;
20550 }
20551 return false;
20552}
20553
20554bool isVCVTTSS2SI(unsigned Opcode) {
20555 switch (Opcode) {
20556 case VCVTTSS2SI64Zrm_Int:
20557 case VCVTTSS2SI64Zrr_Int:
20558 case VCVTTSS2SI64Zrrb_Int:
20559 case VCVTTSS2SI64rm_Int:
20560 case VCVTTSS2SI64rr_Int:
20561 case VCVTTSS2SIZrm_Int:
20562 case VCVTTSS2SIZrr_Int:
20563 case VCVTTSS2SIZrrb_Int:
20564 case VCVTTSS2SIrm_Int:
20565 case VCVTTSS2SIrr_Int:
20566 return true;
20567 }
20568 return false;
20569}
20570
20571bool isTCMMRLFP16PS(unsigned Opcode) {
20572 return Opcode == TCMMRLFP16PS;
20573}
20574
20575bool isFCOMPP(unsigned Opcode) {
20576 return Opcode == FCOMPP;
20577}
20578
20579bool isMOVD(unsigned Opcode) {
20580 switch (Opcode) {
20581 case MMX_MOVD64grr:
20582 case MMX_MOVD64mr:
20583 case MMX_MOVD64rm:
20584 case MMX_MOVD64rr:
20585 case MOVDI2PDIrm:
20586 case MOVDI2PDIrr:
20587 case MOVPDI2DImr:
20588 case MOVPDI2DIrr:
20589 return true;
20590 }
20591 return false;
20592}
20593
20594bool isMOVBE(unsigned Opcode) {
20595 switch (Opcode) {
20596 case MOVBE16mr:
20597 case MOVBE16mr_EVEX:
20598 case MOVBE16rm:
20599 case MOVBE16rm_EVEX:
20600 case MOVBE16rr:
20601 case MOVBE16rr_REV:
20602 case MOVBE32mr:
20603 case MOVBE32mr_EVEX:
20604 case MOVBE32rm:
20605 case MOVBE32rm_EVEX:
20606 case MOVBE32rr:
20607 case MOVBE32rr_REV:
20608 case MOVBE64mr:
20609 case MOVBE64mr_EVEX:
20610 case MOVBE64rm:
20611 case MOVBE64rm_EVEX:
20612 case MOVBE64rr:
20613 case MOVBE64rr_REV:
20614 return true;
20615 }
20616 return false;
20617}
20618
20619bool isVP2INTERSECTD(unsigned Opcode) {
20620 switch (Opcode) {
20621 case VP2INTERSECTDZ128rm:
20622 case VP2INTERSECTDZ128rmb:
20623 case VP2INTERSECTDZ128rr:
20624 case VP2INTERSECTDZ256rm:
20625 case VP2INTERSECTDZ256rmb:
20626 case VP2INTERSECTDZ256rr:
20627 case VP2INTERSECTDZrm:
20628 case VP2INTERSECTDZrmb:
20629 case VP2INTERSECTDZrr:
20630 return true;
20631 }
20632 return false;
20633}
20634
20635bool isVPMULLQ(unsigned Opcode) {
20636 switch (Opcode) {
20637 case VPMULLQZ128rm:
20638 case VPMULLQZ128rmb:
20639 case VPMULLQZ128rmbk:
20640 case VPMULLQZ128rmbkz:
20641 case VPMULLQZ128rmk:
20642 case VPMULLQZ128rmkz:
20643 case VPMULLQZ128rr:
20644 case VPMULLQZ128rrk:
20645 case VPMULLQZ128rrkz:
20646 case VPMULLQZ256rm:
20647 case VPMULLQZ256rmb:
20648 case VPMULLQZ256rmbk:
20649 case VPMULLQZ256rmbkz:
20650 case VPMULLQZ256rmk:
20651 case VPMULLQZ256rmkz:
20652 case VPMULLQZ256rr:
20653 case VPMULLQZ256rrk:
20654 case VPMULLQZ256rrkz:
20655 case VPMULLQZrm:
20656 case VPMULLQZrmb:
20657 case VPMULLQZrmbk:
20658 case VPMULLQZrmbkz:
20659 case VPMULLQZrmk:
20660 case VPMULLQZrmkz:
20661 case VPMULLQZrr:
20662 case VPMULLQZrrk:
20663 case VPMULLQZrrkz:
20664 return true;
20665 }
20666 return false;
20667}
20668
20669bool isVSCALEFPS(unsigned Opcode) {
20670 switch (Opcode) {
20671 case VSCALEFPSZ128rm:
20672 case VSCALEFPSZ128rmb:
20673 case VSCALEFPSZ128rmbk:
20674 case VSCALEFPSZ128rmbkz:
20675 case VSCALEFPSZ128rmk:
20676 case VSCALEFPSZ128rmkz:
20677 case VSCALEFPSZ128rr:
20678 case VSCALEFPSZ128rrk:
20679 case VSCALEFPSZ128rrkz:
20680 case VSCALEFPSZ256rm:
20681 case VSCALEFPSZ256rmb:
20682 case VSCALEFPSZ256rmbk:
20683 case VSCALEFPSZ256rmbkz:
20684 case VSCALEFPSZ256rmk:
20685 case VSCALEFPSZ256rmkz:
20686 case VSCALEFPSZ256rr:
20687 case VSCALEFPSZ256rrk:
20688 case VSCALEFPSZ256rrkz:
20689 case VSCALEFPSZrm:
20690 case VSCALEFPSZrmb:
20691 case VSCALEFPSZrmbk:
20692 case VSCALEFPSZrmbkz:
20693 case VSCALEFPSZrmk:
20694 case VSCALEFPSZrmkz:
20695 case VSCALEFPSZrr:
20696 case VSCALEFPSZrrb:
20697 case VSCALEFPSZrrbk:
20698 case VSCALEFPSZrrbkz:
20699 case VSCALEFPSZrrk:
20700 case VSCALEFPSZrrkz:
20701 return true;
20702 }
20703 return false;
20704}
20705
20706bool isVPMACSDQH(unsigned Opcode) {
20707 switch (Opcode) {
20708 case VPMACSDQHrm:
20709 case VPMACSDQHrr:
20710 return true;
20711 }
20712 return false;
20713}
20714
20715bool isVPTESTNMD(unsigned Opcode) {
20716 switch (Opcode) {
20717 case VPTESTNMDZ128rm:
20718 case VPTESTNMDZ128rmb:
20719 case VPTESTNMDZ128rmbk:
20720 case VPTESTNMDZ128rmk:
20721 case VPTESTNMDZ128rr:
20722 case VPTESTNMDZ128rrk:
20723 case VPTESTNMDZ256rm:
20724 case VPTESTNMDZ256rmb:
20725 case VPTESTNMDZ256rmbk:
20726 case VPTESTNMDZ256rmk:
20727 case VPTESTNMDZ256rr:
20728 case VPTESTNMDZ256rrk:
20729 case VPTESTNMDZrm:
20730 case VPTESTNMDZrmb:
20731 case VPTESTNMDZrmbk:
20732 case VPTESTNMDZrmk:
20733 case VPTESTNMDZrr:
20734 case VPTESTNMDZrrk:
20735 return true;
20736 }
20737 return false;
20738}
20739
20740bool isFCOMP(unsigned Opcode) {
20741 switch (Opcode) {
20742 case COMP_FST0r:
20743 case FCOMP32m:
20744 case FCOMP64m:
20745 return true;
20746 }
20747 return false;
20748}
20749
20750bool isPREFETCHWT1(unsigned Opcode) {
20751 return Opcode == PREFETCHWT1;
20752}
20753
20754bool isVCMPSD(unsigned Opcode) {
20755 switch (Opcode) {
20756 case VCMPSDZrmi_Int:
20757 case VCMPSDZrmi_Intk:
20758 case VCMPSDZrri_Int:
20759 case VCMPSDZrri_Intk:
20760 case VCMPSDZrrib_Int:
20761 case VCMPSDZrrib_Intk:
20762 case VCMPSDrmi_Int:
20763 case VCMPSDrri_Int:
20764 return true;
20765 }
20766 return false;
20767}
20768
20769bool isSGDTD(unsigned Opcode) {
20770 return Opcode == SGDT32m;
20771}
20772
20773bool isWRUSSD(unsigned Opcode) {
20774 switch (Opcode) {
20775 case WRUSSD:
20776 case WRUSSD_EVEX:
20777 return true;
20778 }
20779 return false;
20780}
20781
20782bool isFSUBP(unsigned Opcode) {
20783 return Opcode == SUB_FPrST0;
20784}
20785
20786bool isVUNPCKLPS(unsigned Opcode) {
20787 switch (Opcode) {
20788 case VUNPCKLPSYrm:
20789 case VUNPCKLPSYrr:
20790 case VUNPCKLPSZ128rm:
20791 case VUNPCKLPSZ128rmb:
20792 case VUNPCKLPSZ128rmbk:
20793 case VUNPCKLPSZ128rmbkz:
20794 case VUNPCKLPSZ128rmk:
20795 case VUNPCKLPSZ128rmkz:
20796 case VUNPCKLPSZ128rr:
20797 case VUNPCKLPSZ128rrk:
20798 case VUNPCKLPSZ128rrkz:
20799 case VUNPCKLPSZ256rm:
20800 case VUNPCKLPSZ256rmb:
20801 case VUNPCKLPSZ256rmbk:
20802 case VUNPCKLPSZ256rmbkz:
20803 case VUNPCKLPSZ256rmk:
20804 case VUNPCKLPSZ256rmkz:
20805 case VUNPCKLPSZ256rr:
20806 case VUNPCKLPSZ256rrk:
20807 case VUNPCKLPSZ256rrkz:
20808 case VUNPCKLPSZrm:
20809 case VUNPCKLPSZrmb:
20810 case VUNPCKLPSZrmbk:
20811 case VUNPCKLPSZrmbkz:
20812 case VUNPCKLPSZrmk:
20813 case VUNPCKLPSZrmkz:
20814 case VUNPCKLPSZrr:
20815 case VUNPCKLPSZrrk:
20816 case VUNPCKLPSZrrkz:
20817 case VUNPCKLPSrm:
20818 case VUNPCKLPSrr:
20819 return true;
20820 }
20821 return false;
20822}
20823
20824bool isVFNMSUB213SS(unsigned Opcode) {
20825 switch (Opcode) {
20826 case VFNMSUB213SSZm_Int:
20827 case VFNMSUB213SSZm_Intk:
20828 case VFNMSUB213SSZm_Intkz:
20829 case VFNMSUB213SSZr_Int:
20830 case VFNMSUB213SSZr_Intk:
20831 case VFNMSUB213SSZr_Intkz:
20832 case VFNMSUB213SSZrb_Int:
20833 case VFNMSUB213SSZrb_Intk:
20834 case VFNMSUB213SSZrb_Intkz:
20835 case VFNMSUB213SSm_Int:
20836 case VFNMSUB213SSr_Int:
20837 return true;
20838 }
20839 return false;
20840}
20841
20842bool isROUNDPD(unsigned Opcode) {
20843 switch (Opcode) {
20844 case ROUNDPDmi:
20845 case ROUNDPDri:
20846 return true;
20847 }
20848 return false;
20849}
20850
20851bool isVPMAXSW(unsigned Opcode) {
20852 switch (Opcode) {
20853 case VPMAXSWYrm:
20854 case VPMAXSWYrr:
20855 case VPMAXSWZ128rm:
20856 case VPMAXSWZ128rmk:
20857 case VPMAXSWZ128rmkz:
20858 case VPMAXSWZ128rr:
20859 case VPMAXSWZ128rrk:
20860 case VPMAXSWZ128rrkz:
20861 case VPMAXSWZ256rm:
20862 case VPMAXSWZ256rmk:
20863 case VPMAXSWZ256rmkz:
20864 case VPMAXSWZ256rr:
20865 case VPMAXSWZ256rrk:
20866 case VPMAXSWZ256rrkz:
20867 case VPMAXSWZrm:
20868 case VPMAXSWZrmk:
20869 case VPMAXSWZrmkz:
20870 case VPMAXSWZrr:
20871 case VPMAXSWZrrk:
20872 case VPMAXSWZrrkz:
20873 case VPMAXSWrm:
20874 case VPMAXSWrr:
20875 return true;
20876 }
20877 return false;
20878}
20879
20880bool isVCVTTPH2DQ(unsigned Opcode) {
20881 switch (Opcode) {
20882 case VCVTTPH2DQZ128rm:
20883 case VCVTTPH2DQZ128rmb:
20884 case VCVTTPH2DQZ128rmbk:
20885 case VCVTTPH2DQZ128rmbkz:
20886 case VCVTTPH2DQZ128rmk:
20887 case VCVTTPH2DQZ128rmkz:
20888 case VCVTTPH2DQZ128rr:
20889 case VCVTTPH2DQZ128rrk:
20890 case VCVTTPH2DQZ128rrkz:
20891 case VCVTTPH2DQZ256rm:
20892 case VCVTTPH2DQZ256rmb:
20893 case VCVTTPH2DQZ256rmbk:
20894 case VCVTTPH2DQZ256rmbkz:
20895 case VCVTTPH2DQZ256rmk:
20896 case VCVTTPH2DQZ256rmkz:
20897 case VCVTTPH2DQZ256rr:
20898 case VCVTTPH2DQZ256rrk:
20899 case VCVTTPH2DQZ256rrkz:
20900 case VCVTTPH2DQZrm:
20901 case VCVTTPH2DQZrmb:
20902 case VCVTTPH2DQZrmbk:
20903 case VCVTTPH2DQZrmbkz:
20904 case VCVTTPH2DQZrmk:
20905 case VCVTTPH2DQZrmkz:
20906 case VCVTTPH2DQZrr:
20907 case VCVTTPH2DQZrrb:
20908 case VCVTTPH2DQZrrbk:
20909 case VCVTTPH2DQZrrbkz:
20910 case VCVTTPH2DQZrrk:
20911 case VCVTTPH2DQZrrkz:
20912 return true;
20913 }
20914 return false;
20915}
20916
20917bool isVPUNPCKLWD(unsigned Opcode) {
20918 switch (Opcode) {
20919 case VPUNPCKLWDYrm:
20920 case VPUNPCKLWDYrr:
20921 case VPUNPCKLWDZ128rm:
20922 case VPUNPCKLWDZ128rmk:
20923 case VPUNPCKLWDZ128rmkz:
20924 case VPUNPCKLWDZ128rr:
20925 case VPUNPCKLWDZ128rrk:
20926 case VPUNPCKLWDZ128rrkz:
20927 case VPUNPCKLWDZ256rm:
20928 case VPUNPCKLWDZ256rmk:
20929 case VPUNPCKLWDZ256rmkz:
20930 case VPUNPCKLWDZ256rr:
20931 case VPUNPCKLWDZ256rrk:
20932 case VPUNPCKLWDZ256rrkz:
20933 case VPUNPCKLWDZrm:
20934 case VPUNPCKLWDZrmk:
20935 case VPUNPCKLWDZrmkz:
20936 case VPUNPCKLWDZrr:
20937 case VPUNPCKLWDZrrk:
20938 case VPUNPCKLWDZrrkz:
20939 case VPUNPCKLWDrm:
20940 case VPUNPCKLWDrr:
20941 return true;
20942 }
20943 return false;
20944}
20945
20946bool isKSHIFTLD(unsigned Opcode) {
20947 return Opcode == KSHIFTLDri;
20948}
20949
20950bool isVFMADD231SD(unsigned Opcode) {
20951 switch (Opcode) {
20952 case VFMADD231SDZm_Int:
20953 case VFMADD231SDZm_Intk:
20954 case VFMADD231SDZm_Intkz:
20955 case VFMADD231SDZr_Int:
20956 case VFMADD231SDZr_Intk:
20957 case VFMADD231SDZr_Intkz:
20958 case VFMADD231SDZrb_Int:
20959 case VFMADD231SDZrb_Intk:
20960 case VFMADD231SDZrb_Intkz:
20961 case VFMADD231SDm_Int:
20962 case VFMADD231SDr_Int:
20963 return true;
20964 }
20965 return false;
20966}
20967
20968bool isADDPS(unsigned Opcode) {
20969 switch (Opcode) {
20970 case ADDPSrm:
20971 case ADDPSrr:
20972 return true;
20973 }
20974 return false;
20975}
20976
20977bool isVPSLLVD(unsigned Opcode) {
20978 switch (Opcode) {
20979 case VPSLLVDYrm:
20980 case VPSLLVDYrr:
20981 case VPSLLVDZ128rm:
20982 case VPSLLVDZ128rmb:
20983 case VPSLLVDZ128rmbk:
20984 case VPSLLVDZ128rmbkz:
20985 case VPSLLVDZ128rmk:
20986 case VPSLLVDZ128rmkz:
20987 case VPSLLVDZ128rr:
20988 case VPSLLVDZ128rrk:
20989 case VPSLLVDZ128rrkz:
20990 case VPSLLVDZ256rm:
20991 case VPSLLVDZ256rmb:
20992 case VPSLLVDZ256rmbk:
20993 case VPSLLVDZ256rmbkz:
20994 case VPSLLVDZ256rmk:
20995 case VPSLLVDZ256rmkz:
20996 case VPSLLVDZ256rr:
20997 case VPSLLVDZ256rrk:
20998 case VPSLLVDZ256rrkz:
20999 case VPSLLVDZrm:
21000 case VPSLLVDZrmb:
21001 case VPSLLVDZrmbk:
21002 case VPSLLVDZrmbkz:
21003 case VPSLLVDZrmk:
21004 case VPSLLVDZrmkz:
21005 case VPSLLVDZrr:
21006 case VPSLLVDZrrk:
21007 case VPSLLVDZrrkz:
21008 case VPSLLVDrm:
21009 case VPSLLVDrr:
21010 return true;
21011 }
21012 return false;
21013}
21014
21015bool isVFNMADD132SH(unsigned Opcode) {
21016 switch (Opcode) {
21017 case VFNMADD132SHZm_Int:
21018 case VFNMADD132SHZm_Intk:
21019 case VFNMADD132SHZm_Intkz:
21020 case VFNMADD132SHZr_Int:
21021 case VFNMADD132SHZr_Intk:
21022 case VFNMADD132SHZr_Intkz:
21023 case VFNMADD132SHZrb_Int:
21024 case VFNMADD132SHZrb_Intk:
21025 case VFNMADD132SHZrb_Intkz:
21026 return true;
21027 }
21028 return false;
21029}
21030
21031bool isVMOVNTPS(unsigned Opcode) {
21032 switch (Opcode) {
21033 case VMOVNTPSYmr:
21034 case VMOVNTPSZ128mr:
21035 case VMOVNTPSZ256mr:
21036 case VMOVNTPSZmr:
21037 case VMOVNTPSmr:
21038 return true;
21039 }
21040 return false;
21041}
21042
21043bool isVCVTPD2DQ(unsigned Opcode) {
21044 switch (Opcode) {
21045 case VCVTPD2DQYrm:
21046 case VCVTPD2DQYrr:
21047 case VCVTPD2DQZ128rm:
21048 case VCVTPD2DQZ128rmb:
21049 case VCVTPD2DQZ128rmbk:
21050 case VCVTPD2DQZ128rmbkz:
21051 case VCVTPD2DQZ128rmk:
21052 case VCVTPD2DQZ128rmkz:
21053 case VCVTPD2DQZ128rr:
21054 case VCVTPD2DQZ128rrk:
21055 case VCVTPD2DQZ128rrkz:
21056 case VCVTPD2DQZ256rm:
21057 case VCVTPD2DQZ256rmb:
21058 case VCVTPD2DQZ256rmbk:
21059 case VCVTPD2DQZ256rmbkz:
21060 case VCVTPD2DQZ256rmk:
21061 case VCVTPD2DQZ256rmkz:
21062 case VCVTPD2DQZ256rr:
21063 case VCVTPD2DQZ256rrk:
21064 case VCVTPD2DQZ256rrkz:
21065 case VCVTPD2DQZrm:
21066 case VCVTPD2DQZrmb:
21067 case VCVTPD2DQZrmbk:
21068 case VCVTPD2DQZrmbkz:
21069 case VCVTPD2DQZrmk:
21070 case VCVTPD2DQZrmkz:
21071 case VCVTPD2DQZrr:
21072 case VCVTPD2DQZrrb:
21073 case VCVTPD2DQZrrbk:
21074 case VCVTPD2DQZrrbkz:
21075 case VCVTPD2DQZrrk:
21076 case VCVTPD2DQZrrkz:
21077 case VCVTPD2DQrm:
21078 case VCVTPD2DQrr:
21079 return true;
21080 }
21081 return false;
21082}
21083
21084bool isVPXOR(unsigned Opcode) {
21085 switch (Opcode) {
21086 case VPXORYrm:
21087 case VPXORYrr:
21088 case VPXORrm:
21089 case VPXORrr:
21090 return true;
21091 }
21092 return false;
21093}
21094
21095bool isSTMXCSR(unsigned Opcode) {
21096 return Opcode == STMXCSR;
21097}
21098
21099bool isVRCP14SS(unsigned Opcode) {
21100 switch (Opcode) {
21101 case VRCP14SSZrm:
21102 case VRCP14SSZrmk:
21103 case VRCP14SSZrmkz:
21104 case VRCP14SSZrr:
21105 case VRCP14SSZrrk:
21106 case VRCP14SSZrrkz:
21107 return true;
21108 }
21109 return false;
21110}
21111
21112bool isUD2(unsigned Opcode) {
21113 return Opcode == TRAP;
21114}
21115
21116bool isVPOPCNTW(unsigned Opcode) {
21117 switch (Opcode) {
21118 case VPOPCNTWZ128rm:
21119 case VPOPCNTWZ128rmk:
21120 case VPOPCNTWZ128rmkz:
21121 case VPOPCNTWZ128rr:
21122 case VPOPCNTWZ128rrk:
21123 case VPOPCNTWZ128rrkz:
21124 case VPOPCNTWZ256rm:
21125 case VPOPCNTWZ256rmk:
21126 case VPOPCNTWZ256rmkz:
21127 case VPOPCNTWZ256rr:
21128 case VPOPCNTWZ256rrk:
21129 case VPOPCNTWZ256rrkz:
21130 case VPOPCNTWZrm:
21131 case VPOPCNTWZrmk:
21132 case VPOPCNTWZrmkz:
21133 case VPOPCNTWZrr:
21134 case VPOPCNTWZrrk:
21135 case VPOPCNTWZrrkz:
21136 return true;
21137 }
21138 return false;
21139}
21140
21141bool isVRSQRTSH(unsigned Opcode) {
21142 switch (Opcode) {
21143 case VRSQRTSHZrm:
21144 case VRSQRTSHZrmk:
21145 case VRSQRTSHZrmkz:
21146 case VRSQRTSHZrr:
21147 case VRSQRTSHZrrk:
21148 case VRSQRTSHZrrkz:
21149 return true;
21150 }
21151 return false;
21152}
21153
21154bool isVSCATTERPF0DPD(unsigned Opcode) {
21155 return Opcode == VSCATTERPF0DPDm;
21156}
21157
21158bool isVFMADDPS(unsigned Opcode) {
21159 switch (Opcode) {
21160 case VFMADDPS4Ymr:
21161 case VFMADDPS4Yrm:
21162 case VFMADDPS4Yrr:
21163 case VFMADDPS4Yrr_REV:
21164 case VFMADDPS4mr:
21165 case VFMADDPS4rm:
21166 case VFMADDPS4rr:
21167 case VFMADDPS4rr_REV:
21168 return true;
21169 }
21170 return false;
21171}
21172
21173bool isXSAVEC64(unsigned Opcode) {
21174 return Opcode == XSAVEC64;
21175}
21176
21177bool isVPMADDUBSW(unsigned Opcode) {
21178 switch (Opcode) {
21179 case VPMADDUBSWYrm:
21180 case VPMADDUBSWYrr:
21181 case VPMADDUBSWZ128rm:
21182 case VPMADDUBSWZ128rmk:
21183 case VPMADDUBSWZ128rmkz:
21184 case VPMADDUBSWZ128rr:
21185 case VPMADDUBSWZ128rrk:
21186 case VPMADDUBSWZ128rrkz:
21187 case VPMADDUBSWZ256rm:
21188 case VPMADDUBSWZ256rmk:
21189 case VPMADDUBSWZ256rmkz:
21190 case VPMADDUBSWZ256rr:
21191 case VPMADDUBSWZ256rrk:
21192 case VPMADDUBSWZ256rrkz:
21193 case VPMADDUBSWZrm:
21194 case VPMADDUBSWZrmk:
21195 case VPMADDUBSWZrmkz:
21196 case VPMADDUBSWZrr:
21197 case VPMADDUBSWZrrk:
21198 case VPMADDUBSWZrrkz:
21199 case VPMADDUBSWrm:
21200 case VPMADDUBSWrr:
21201 return true;
21202 }
21203 return false;
21204}
21205
21206bool isVPMOVZXDQ(unsigned Opcode) {
21207 switch (Opcode) {
21208 case VPMOVZXDQYrm:
21209 case VPMOVZXDQYrr:
21210 case VPMOVZXDQZ128rm:
21211 case VPMOVZXDQZ128rmk:
21212 case VPMOVZXDQZ128rmkz:
21213 case VPMOVZXDQZ128rr:
21214 case VPMOVZXDQZ128rrk:
21215 case VPMOVZXDQZ128rrkz:
21216 case VPMOVZXDQZ256rm:
21217 case VPMOVZXDQZ256rmk:
21218 case VPMOVZXDQZ256rmkz:
21219 case VPMOVZXDQZ256rr:
21220 case VPMOVZXDQZ256rrk:
21221 case VPMOVZXDQZ256rrkz:
21222 case VPMOVZXDQZrm:
21223 case VPMOVZXDQZrmk:
21224 case VPMOVZXDQZrmkz:
21225 case VPMOVZXDQZrr:
21226 case VPMOVZXDQZrrk:
21227 case VPMOVZXDQZrrkz:
21228 case VPMOVZXDQrm:
21229 case VPMOVZXDQrr:
21230 return true;
21231 }
21232 return false;
21233}
21234
21235bool isVRCP14PS(unsigned Opcode) {
21236 switch (Opcode) {
21237 case VRCP14PSZ128m:
21238 case VRCP14PSZ128mb:
21239 case VRCP14PSZ128mbk:
21240 case VRCP14PSZ128mbkz:
21241 case VRCP14PSZ128mk:
21242 case VRCP14PSZ128mkz:
21243 case VRCP14PSZ128r:
21244 case VRCP14PSZ128rk:
21245 case VRCP14PSZ128rkz:
21246 case VRCP14PSZ256m:
21247 case VRCP14PSZ256mb:
21248 case VRCP14PSZ256mbk:
21249 case VRCP14PSZ256mbkz:
21250 case VRCP14PSZ256mk:
21251 case VRCP14PSZ256mkz:
21252 case VRCP14PSZ256r:
21253 case VRCP14PSZ256rk:
21254 case VRCP14PSZ256rkz:
21255 case VRCP14PSZm:
21256 case VRCP14PSZmb:
21257 case VRCP14PSZmbk:
21258 case VRCP14PSZmbkz:
21259 case VRCP14PSZmk:
21260 case VRCP14PSZmkz:
21261 case VRCP14PSZr:
21262 case VRCP14PSZrk:
21263 case VRCP14PSZrkz:
21264 return true;
21265 }
21266 return false;
21267}
21268
21269bool isVSQRTSH(unsigned Opcode) {
21270 switch (Opcode) {
21271 case VSQRTSHZm_Int:
21272 case VSQRTSHZm_Intk:
21273 case VSQRTSHZm_Intkz:
21274 case VSQRTSHZr_Int:
21275 case VSQRTSHZr_Intk:
21276 case VSQRTSHZr_Intkz:
21277 case VSQRTSHZrb_Int:
21278 case VSQRTSHZrb_Intk:
21279 case VSQRTSHZrb_Intkz:
21280 return true;
21281 }
21282 return false;
21283}
21284
21285bool isLOOP(unsigned Opcode) {
21286 return Opcode == LOOP;
21287}
21288
21289bool isSTUI(unsigned Opcode) {
21290 return Opcode == STUI;
21291}
21292
21293bool isVCVTTPS2UDQ(unsigned Opcode) {
21294 switch (Opcode) {
21295 case VCVTTPS2UDQZ128rm:
21296 case VCVTTPS2UDQZ128rmb:
21297 case VCVTTPS2UDQZ128rmbk:
21298 case VCVTTPS2UDQZ128rmbkz:
21299 case VCVTTPS2UDQZ128rmk:
21300 case VCVTTPS2UDQZ128rmkz:
21301 case VCVTTPS2UDQZ128rr:
21302 case VCVTTPS2UDQZ128rrk:
21303 case VCVTTPS2UDQZ128rrkz:
21304 case VCVTTPS2UDQZ256rm:
21305 case VCVTTPS2UDQZ256rmb:
21306 case VCVTTPS2UDQZ256rmbk:
21307 case VCVTTPS2UDQZ256rmbkz:
21308 case VCVTTPS2UDQZ256rmk:
21309 case VCVTTPS2UDQZ256rmkz:
21310 case VCVTTPS2UDQZ256rr:
21311 case VCVTTPS2UDQZ256rrk:
21312 case VCVTTPS2UDQZ256rrkz:
21313 case VCVTTPS2UDQZrm:
21314 case VCVTTPS2UDQZrmb:
21315 case VCVTTPS2UDQZrmbk:
21316 case VCVTTPS2UDQZrmbkz:
21317 case VCVTTPS2UDQZrmk:
21318 case VCVTTPS2UDQZrmkz:
21319 case VCVTTPS2UDQZrr:
21320 case VCVTTPS2UDQZrrb:
21321 case VCVTTPS2UDQZrrbk:
21322 case VCVTTPS2UDQZrrbkz:
21323 case VCVTTPS2UDQZrrk:
21324 case VCVTTPS2UDQZrrkz:
21325 return true;
21326 }
21327 return false;
21328}
21329
21330bool isVCOMPRESSPS(unsigned Opcode) {
21331 switch (Opcode) {
21332 case VCOMPRESSPSZ128mr:
21333 case VCOMPRESSPSZ128mrk:
21334 case VCOMPRESSPSZ128rr:
21335 case VCOMPRESSPSZ128rrk:
21336 case VCOMPRESSPSZ128rrkz:
21337 case VCOMPRESSPSZ256mr:
21338 case VCOMPRESSPSZ256mrk:
21339 case VCOMPRESSPSZ256rr:
21340 case VCOMPRESSPSZ256rrk:
21341 case VCOMPRESSPSZ256rrkz:
21342 case VCOMPRESSPSZmr:
21343 case VCOMPRESSPSZmrk:
21344 case VCOMPRESSPSZrr:
21345 case VCOMPRESSPSZrrk:
21346 case VCOMPRESSPSZrrkz:
21347 return true;
21348 }
21349 return false;
21350}
21351
21352bool isXABORT(unsigned Opcode) {
21353 return Opcode == XABORT;
21354}
21355
21356bool isVPADDW(unsigned Opcode) {
21357 switch (Opcode) {
21358 case VPADDWYrm:
21359 case VPADDWYrr:
21360 case VPADDWZ128rm:
21361 case VPADDWZ128rmk:
21362 case VPADDWZ128rmkz:
21363 case VPADDWZ128rr:
21364 case VPADDWZ128rrk:
21365 case VPADDWZ128rrkz:
21366 case VPADDWZ256rm:
21367 case VPADDWZ256rmk:
21368 case VPADDWZ256rmkz:
21369 case VPADDWZ256rr:
21370 case VPADDWZ256rrk:
21371 case VPADDWZ256rrkz:
21372 case VPADDWZrm:
21373 case VPADDWZrmk:
21374 case VPADDWZrmkz:
21375 case VPADDWZrr:
21376 case VPADDWZrrk:
21377 case VPADDWZrrkz:
21378 case VPADDWrm:
21379 case VPADDWrr:
21380 return true;
21381 }
21382 return false;
21383}
21384
21385bool isVPSIGND(unsigned Opcode) {
21386 switch (Opcode) {
21387 case VPSIGNDYrm:
21388 case VPSIGNDYrr:
21389 case VPSIGNDrm:
21390 case VPSIGNDrr:
21391 return true;
21392 }
21393 return false;
21394}
21395
21396bool isVRNDSCALEPS(unsigned Opcode) {
21397 switch (Opcode) {
21398 case VRNDSCALEPSZ128rmbi:
21399 case VRNDSCALEPSZ128rmbik:
21400 case VRNDSCALEPSZ128rmbikz:
21401 case VRNDSCALEPSZ128rmi:
21402 case VRNDSCALEPSZ128rmik:
21403 case VRNDSCALEPSZ128rmikz:
21404 case VRNDSCALEPSZ128rri:
21405 case VRNDSCALEPSZ128rrik:
21406 case VRNDSCALEPSZ128rrikz:
21407 case VRNDSCALEPSZ256rmbi:
21408 case VRNDSCALEPSZ256rmbik:
21409 case VRNDSCALEPSZ256rmbikz:
21410 case VRNDSCALEPSZ256rmi:
21411 case VRNDSCALEPSZ256rmik:
21412 case VRNDSCALEPSZ256rmikz:
21413 case VRNDSCALEPSZ256rri:
21414 case VRNDSCALEPSZ256rrik:
21415 case VRNDSCALEPSZ256rrikz:
21416 case VRNDSCALEPSZrmbi:
21417 case VRNDSCALEPSZrmbik:
21418 case VRNDSCALEPSZrmbikz:
21419 case VRNDSCALEPSZrmi:
21420 case VRNDSCALEPSZrmik:
21421 case VRNDSCALEPSZrmikz:
21422 case VRNDSCALEPSZrri:
21423 case VRNDSCALEPSZrrib:
21424 case VRNDSCALEPSZrribk:
21425 case VRNDSCALEPSZrribkz:
21426 case VRNDSCALEPSZrrik:
21427 case VRNDSCALEPSZrrikz:
21428 return true;
21429 }
21430 return false;
21431}
21432
21433bool isVPHADDUWD(unsigned Opcode) {
21434 switch (Opcode) {
21435 case VPHADDUWDrm:
21436 case VPHADDUWDrr:
21437 return true;
21438 }
21439 return false;
21440}
21441
21442bool isVDBPSADBW(unsigned Opcode) {
21443 switch (Opcode) {
21444 case VDBPSADBWZ128rmi:
21445 case VDBPSADBWZ128rmik:
21446 case VDBPSADBWZ128rmikz:
21447 case VDBPSADBWZ128rri:
21448 case VDBPSADBWZ128rrik:
21449 case VDBPSADBWZ128rrikz:
21450 case VDBPSADBWZ256rmi:
21451 case VDBPSADBWZ256rmik:
21452 case VDBPSADBWZ256rmikz:
21453 case VDBPSADBWZ256rri:
21454 case VDBPSADBWZ256rrik:
21455 case VDBPSADBWZ256rrikz:
21456 case VDBPSADBWZrmi:
21457 case VDBPSADBWZrmik:
21458 case VDBPSADBWZrmikz:
21459 case VDBPSADBWZrri:
21460 case VDBPSADBWZrrik:
21461 case VDBPSADBWZrrikz:
21462 return true;
21463 }
21464 return false;
21465}
21466
21467bool isPSLLW(unsigned Opcode) {
21468 switch (Opcode) {
21469 case MMX_PSLLWri:
21470 case MMX_PSLLWrm:
21471 case MMX_PSLLWrr:
21472 case PSLLWri:
21473 case PSLLWrm:
21474 case PSLLWrr:
21475 return true;
21476 }
21477 return false;
21478}
21479
21480bool isVPMOVQD(unsigned Opcode) {
21481 switch (Opcode) {
21482 case VPMOVQDZ128mr:
21483 case VPMOVQDZ128mrk:
21484 case VPMOVQDZ128rr:
21485 case VPMOVQDZ128rrk:
21486 case VPMOVQDZ128rrkz:
21487 case VPMOVQDZ256mr:
21488 case VPMOVQDZ256mrk:
21489 case VPMOVQDZ256rr:
21490 case VPMOVQDZ256rrk:
21491 case VPMOVQDZ256rrkz:
21492 case VPMOVQDZmr:
21493 case VPMOVQDZmrk:
21494 case VPMOVQDZrr:
21495 case VPMOVQDZrrk:
21496 case VPMOVQDZrrkz:
21497 return true;
21498 }
21499 return false;
21500}
21501
21502bool isVINSERTI64X4(unsigned Opcode) {
21503 switch (Opcode) {
21504 case VINSERTI64x4Zrm:
21505 case VINSERTI64x4Zrmk:
21506 case VINSERTI64x4Zrmkz:
21507 case VINSERTI64x4Zrr:
21508 case VINSERTI64x4Zrrk:
21509 case VINSERTI64x4Zrrkz:
21510 return true;
21511 }
21512 return false;
21513}
21514
21515bool isVPERMI2PS(unsigned Opcode) {
21516 switch (Opcode) {
21517 case VPERMI2PSZ128rm:
21518 case VPERMI2PSZ128rmb:
21519 case VPERMI2PSZ128rmbk:
21520 case VPERMI2PSZ128rmbkz:
21521 case VPERMI2PSZ128rmk:
21522 case VPERMI2PSZ128rmkz:
21523 case VPERMI2PSZ128rr:
21524 case VPERMI2PSZ128rrk:
21525 case VPERMI2PSZ128rrkz:
21526 case VPERMI2PSZ256rm:
21527 case VPERMI2PSZ256rmb:
21528 case VPERMI2PSZ256rmbk:
21529 case VPERMI2PSZ256rmbkz:
21530 case VPERMI2PSZ256rmk:
21531 case VPERMI2PSZ256rmkz:
21532 case VPERMI2PSZ256rr:
21533 case VPERMI2PSZ256rrk:
21534 case VPERMI2PSZ256rrkz:
21535 case VPERMI2PSZrm:
21536 case VPERMI2PSZrmb:
21537 case VPERMI2PSZrmbk:
21538 case VPERMI2PSZrmbkz:
21539 case VPERMI2PSZrmk:
21540 case VPERMI2PSZrmkz:
21541 case VPERMI2PSZrr:
21542 case VPERMI2PSZrrk:
21543 case VPERMI2PSZrrkz:
21544 return true;
21545 }
21546 return false;
21547}
21548
21549bool isVMULPH(unsigned Opcode) {
21550 switch (Opcode) {
21551 case VMULPHZ128rm:
21552 case VMULPHZ128rmb:
21553 case VMULPHZ128rmbk:
21554 case VMULPHZ128rmbkz:
21555 case VMULPHZ128rmk:
21556 case VMULPHZ128rmkz:
21557 case VMULPHZ128rr:
21558 case VMULPHZ128rrk:
21559 case VMULPHZ128rrkz:
21560 case VMULPHZ256rm:
21561 case VMULPHZ256rmb:
21562 case VMULPHZ256rmbk:
21563 case VMULPHZ256rmbkz:
21564 case VMULPHZ256rmk:
21565 case VMULPHZ256rmkz:
21566 case VMULPHZ256rr:
21567 case VMULPHZ256rrk:
21568 case VMULPHZ256rrkz:
21569 case VMULPHZrm:
21570 case VMULPHZrmb:
21571 case VMULPHZrmbk:
21572 case VMULPHZrmbkz:
21573 case VMULPHZrmk:
21574 case VMULPHZrmkz:
21575 case VMULPHZrr:
21576 case VMULPHZrrb:
21577 case VMULPHZrrbk:
21578 case VMULPHZrrbkz:
21579 case VMULPHZrrk:
21580 case VMULPHZrrkz:
21581 return true;
21582 }
21583 return false;
21584}
21585
21586bool isVPCMPUQ(unsigned Opcode) {
21587 switch (Opcode) {
21588 case VPCMPUQZ128rmi:
21589 case VPCMPUQZ128rmib:
21590 case VPCMPUQZ128rmibk:
21591 case VPCMPUQZ128rmik:
21592 case VPCMPUQZ128rri:
21593 case VPCMPUQZ128rrik:
21594 case VPCMPUQZ256rmi:
21595 case VPCMPUQZ256rmib:
21596 case VPCMPUQZ256rmibk:
21597 case VPCMPUQZ256rmik:
21598 case VPCMPUQZ256rri:
21599 case VPCMPUQZ256rrik:
21600 case VPCMPUQZrmi:
21601 case VPCMPUQZrmib:
21602 case VPCMPUQZrmibk:
21603 case VPCMPUQZrmik:
21604 case VPCMPUQZrri:
21605 case VPCMPUQZrrik:
21606 return true;
21607 }
21608 return false;
21609}
21610
21611bool isVCVTUSI2SD(unsigned Opcode) {
21612 switch (Opcode) {
21613 case VCVTUSI2SDZrm_Int:
21614 case VCVTUSI2SDZrr_Int:
21615 case VCVTUSI642SDZrm_Int:
21616 case VCVTUSI642SDZrr_Int:
21617 case VCVTUSI642SDZrrb_Int:
21618 return true;
21619 }
21620 return false;
21621}
21622
21623bool isKXNORW(unsigned Opcode) {
21624 return Opcode == KXNORWrr;
21625}
21626
21627bool isBLCIC(unsigned Opcode) {
21628 switch (Opcode) {
21629 case BLCIC32rm:
21630 case BLCIC32rr:
21631 case BLCIC64rm:
21632 case BLCIC64rr:
21633 return true;
21634 }
21635 return false;
21636}
21637
21638bool isVFNMADD213SD(unsigned Opcode) {
21639 switch (Opcode) {
21640 case VFNMADD213SDZm_Int:
21641 case VFNMADD213SDZm_Intk:
21642 case VFNMADD213SDZm_Intkz:
21643 case VFNMADD213SDZr_Int:
21644 case VFNMADD213SDZr_Intk:
21645 case VFNMADD213SDZr_Intkz:
21646 case VFNMADD213SDZrb_Int:
21647 case VFNMADD213SDZrb_Intk:
21648 case VFNMADD213SDZrb_Intkz:
21649 case VFNMADD213SDm_Int:
21650 case VFNMADD213SDr_Int:
21651 return true;
21652 }
21653 return false;
21654}
21655
21656bool isVPMACSWW(unsigned Opcode) {
21657 switch (Opcode) {
21658 case VPMACSWWrm:
21659 case VPMACSWWrr:
21660 return true;
21661 }
21662 return false;
21663}
21664
21665bool isVMOVLPS(unsigned Opcode) {
21666 switch (Opcode) {
21667 case VMOVLPSZ128mr:
21668 case VMOVLPSZ128rm:
21669 case VMOVLPSmr:
21670 case VMOVLPSrm:
21671 return true;
21672 }
21673 return false;
21674}
21675
21676bool isPCONFIG(unsigned Opcode) {
21677 return Opcode == PCONFIG;
21678}
21679
21680bool isPANDN(unsigned Opcode) {
21681 switch (Opcode) {
21682 case MMX_PANDNrm:
21683 case MMX_PANDNrr:
21684 case PANDNrm:
21685 case PANDNrr:
21686 return true;
21687 }
21688 return false;
21689}
21690
21691bool isVGETEXPPD(unsigned Opcode) {
21692 switch (Opcode) {
21693 case VGETEXPPDZ128m:
21694 case VGETEXPPDZ128mb:
21695 case VGETEXPPDZ128mbk:
21696 case VGETEXPPDZ128mbkz:
21697 case VGETEXPPDZ128mk:
21698 case VGETEXPPDZ128mkz:
21699 case VGETEXPPDZ128r:
21700 case VGETEXPPDZ128rk:
21701 case VGETEXPPDZ128rkz:
21702 case VGETEXPPDZ256m:
21703 case VGETEXPPDZ256mb:
21704 case VGETEXPPDZ256mbk:
21705 case VGETEXPPDZ256mbkz:
21706 case VGETEXPPDZ256mk:
21707 case VGETEXPPDZ256mkz:
21708 case VGETEXPPDZ256r:
21709 case VGETEXPPDZ256rk:
21710 case VGETEXPPDZ256rkz:
21711 case VGETEXPPDZm:
21712 case VGETEXPPDZmb:
21713 case VGETEXPPDZmbk:
21714 case VGETEXPPDZmbkz:
21715 case VGETEXPPDZmk:
21716 case VGETEXPPDZmkz:
21717 case VGETEXPPDZr:
21718 case VGETEXPPDZrb:
21719 case VGETEXPPDZrbk:
21720 case VGETEXPPDZrbkz:
21721 case VGETEXPPDZrk:
21722 case VGETEXPPDZrkz:
21723 return true;
21724 }
21725 return false;
21726}
21727
21728bool isVPSRLVQ(unsigned Opcode) {
21729 switch (Opcode) {
21730 case VPSRLVQYrm:
21731 case VPSRLVQYrr:
21732 case VPSRLVQZ128rm:
21733 case VPSRLVQZ128rmb:
21734 case VPSRLVQZ128rmbk:
21735 case VPSRLVQZ128rmbkz:
21736 case VPSRLVQZ128rmk:
21737 case VPSRLVQZ128rmkz:
21738 case VPSRLVQZ128rr:
21739 case VPSRLVQZ128rrk:
21740 case VPSRLVQZ128rrkz:
21741 case VPSRLVQZ256rm:
21742 case VPSRLVQZ256rmb:
21743 case VPSRLVQZ256rmbk:
21744 case VPSRLVQZ256rmbkz:
21745 case VPSRLVQZ256rmk:
21746 case VPSRLVQZ256rmkz:
21747 case VPSRLVQZ256rr:
21748 case VPSRLVQZ256rrk:
21749 case VPSRLVQZ256rrkz:
21750 case VPSRLVQZrm:
21751 case VPSRLVQZrmb:
21752 case VPSRLVQZrmbk:
21753 case VPSRLVQZrmbkz:
21754 case VPSRLVQZrmk:
21755 case VPSRLVQZrmkz:
21756 case VPSRLVQZrr:
21757 case VPSRLVQZrrk:
21758 case VPSRLVQZrrkz:
21759 case VPSRLVQrm:
21760 case VPSRLVQrr:
21761 return true;
21762 }
21763 return false;
21764}
21765
21766bool isUD1(unsigned Opcode) {
21767 switch (Opcode) {
21768 case UD1Lm:
21769 case UD1Lr:
21770 case UD1Qm:
21771 case UD1Qr:
21772 case UD1Wm:
21773 case UD1Wr:
21774 return true;
21775 }
21776 return false;
21777}
21778
21779bool isPMAXSB(unsigned Opcode) {
21780 switch (Opcode) {
21781 case PMAXSBrm:
21782 case PMAXSBrr:
21783 return true;
21784 }
21785 return false;
21786}
21787
21788bool isVPROLQ(unsigned Opcode) {
21789 switch (Opcode) {
21790 case VPROLQZ128mbi:
21791 case VPROLQZ128mbik:
21792 case VPROLQZ128mbikz:
21793 case VPROLQZ128mi:
21794 case VPROLQZ128mik:
21795 case VPROLQZ128mikz:
21796 case VPROLQZ128ri:
21797 case VPROLQZ128rik:
21798 case VPROLQZ128rikz:
21799 case VPROLQZ256mbi:
21800 case VPROLQZ256mbik:
21801 case VPROLQZ256mbikz:
21802 case VPROLQZ256mi:
21803 case VPROLQZ256mik:
21804 case VPROLQZ256mikz:
21805 case VPROLQZ256ri:
21806 case VPROLQZ256rik:
21807 case VPROLQZ256rikz:
21808 case VPROLQZmbi:
21809 case VPROLQZmbik:
21810 case VPROLQZmbikz:
21811 case VPROLQZmi:
21812 case VPROLQZmik:
21813 case VPROLQZmikz:
21814 case VPROLQZri:
21815 case VPROLQZrik:
21816 case VPROLQZrikz:
21817 return true;
21818 }
21819 return false;
21820}
21821
21822bool isVSCATTERPF1QPD(unsigned Opcode) {
21823 return Opcode == VSCATTERPF1QPDm;
21824}
21825
21826bool isVPSRLD(unsigned Opcode) {
21827 switch (Opcode) {
21828 case VPSRLDYri:
21829 case VPSRLDYrm:
21830 case VPSRLDYrr:
21831 case VPSRLDZ128mbi:
21832 case VPSRLDZ128mbik:
21833 case VPSRLDZ128mbikz:
21834 case VPSRLDZ128mi:
21835 case VPSRLDZ128mik:
21836 case VPSRLDZ128mikz:
21837 case VPSRLDZ128ri:
21838 case VPSRLDZ128rik:
21839 case VPSRLDZ128rikz:
21840 case VPSRLDZ128rm:
21841 case VPSRLDZ128rmk:
21842 case VPSRLDZ128rmkz:
21843 case VPSRLDZ128rr:
21844 case VPSRLDZ128rrk:
21845 case VPSRLDZ128rrkz:
21846 case VPSRLDZ256mbi:
21847 case VPSRLDZ256mbik:
21848 case VPSRLDZ256mbikz:
21849 case VPSRLDZ256mi:
21850 case VPSRLDZ256mik:
21851 case VPSRLDZ256mikz:
21852 case VPSRLDZ256ri:
21853 case VPSRLDZ256rik:
21854 case VPSRLDZ256rikz:
21855 case VPSRLDZ256rm:
21856 case VPSRLDZ256rmk:
21857 case VPSRLDZ256rmkz:
21858 case VPSRLDZ256rr:
21859 case VPSRLDZ256rrk:
21860 case VPSRLDZ256rrkz:
21861 case VPSRLDZmbi:
21862 case VPSRLDZmbik:
21863 case VPSRLDZmbikz:
21864 case VPSRLDZmi:
21865 case VPSRLDZmik:
21866 case VPSRLDZmikz:
21867 case VPSRLDZri:
21868 case VPSRLDZrik:
21869 case VPSRLDZrikz:
21870 case VPSRLDZrm:
21871 case VPSRLDZrmk:
21872 case VPSRLDZrmkz:
21873 case VPSRLDZrr:
21874 case VPSRLDZrrk:
21875 case VPSRLDZrrkz:
21876 case VPSRLDri:
21877 case VPSRLDrm:
21878 case VPSRLDrr:
21879 return true;
21880 }
21881 return false;
21882}
21883
21884bool isINT3(unsigned Opcode) {
21885 return Opcode == INT3;
21886}
21887
21888bool isXRSTORS64(unsigned Opcode) {
21889 return Opcode == XRSTORS64;
21890}
21891
21892bool isCVTSD2SI(unsigned Opcode) {
21893 switch (Opcode) {
21894 case CVTSD2SI64rm_Int:
21895 case CVTSD2SI64rr_Int:
21896 case CVTSD2SIrm_Int:
21897 case CVTSD2SIrr_Int:
21898 return true;
21899 }
21900 return false;
21901}
21902
21903bool isVMAXSS(unsigned Opcode) {
21904 switch (Opcode) {
21905 case VMAXSSZrm_Int:
21906 case VMAXSSZrm_Intk:
21907 case VMAXSSZrm_Intkz:
21908 case VMAXSSZrr_Int:
21909 case VMAXSSZrr_Intk:
21910 case VMAXSSZrr_Intkz:
21911 case VMAXSSZrrb_Int:
21912 case VMAXSSZrrb_Intk:
21913 case VMAXSSZrrb_Intkz:
21914 case VMAXSSrm_Int:
21915 case VMAXSSrr_Int:
21916 return true;
21917 }
21918 return false;
21919}
21920
21921bool isVPMINUB(unsigned Opcode) {
21922 switch (Opcode) {
21923 case VPMINUBYrm:
21924 case VPMINUBYrr:
21925 case VPMINUBZ128rm:
21926 case VPMINUBZ128rmk:
21927 case VPMINUBZ128rmkz:
21928 case VPMINUBZ128rr:
21929 case VPMINUBZ128rrk:
21930 case VPMINUBZ128rrkz:
21931 case VPMINUBZ256rm:
21932 case VPMINUBZ256rmk:
21933 case VPMINUBZ256rmkz:
21934 case VPMINUBZ256rr:
21935 case VPMINUBZ256rrk:
21936 case VPMINUBZ256rrkz:
21937 case VPMINUBZrm:
21938 case VPMINUBZrmk:
21939 case VPMINUBZrmkz:
21940 case VPMINUBZrr:
21941 case VPMINUBZrrk:
21942 case VPMINUBZrrkz:
21943 case VPMINUBrm:
21944 case VPMINUBrr:
21945 return true;
21946 }
21947 return false;
21948}
21949
21950bool isKXNORQ(unsigned Opcode) {
21951 return Opcode == KXNORQrr;
21952}
21953
21954bool isFLD(unsigned Opcode) {
21955 switch (Opcode) {
21956 case LD_F32m:
21957 case LD_F64m:
21958 case LD_F80m:
21959 case LD_Frr:
21960 return true;
21961 }
21962 return false;
21963}
21964
21965bool isVSHUFI32X4(unsigned Opcode) {
21966 switch (Opcode) {
21967 case VSHUFI32X4Z256rmbi:
21968 case VSHUFI32X4Z256rmbik:
21969 case VSHUFI32X4Z256rmbikz:
21970 case VSHUFI32X4Z256rmi:
21971 case VSHUFI32X4Z256rmik:
21972 case VSHUFI32X4Z256rmikz:
21973 case VSHUFI32X4Z256rri:
21974 case VSHUFI32X4Z256rrik:
21975 case VSHUFI32X4Z256rrikz:
21976 case VSHUFI32X4Zrmbi:
21977 case VSHUFI32X4Zrmbik:
21978 case VSHUFI32X4Zrmbikz:
21979 case VSHUFI32X4Zrmi:
21980 case VSHUFI32X4Zrmik:
21981 case VSHUFI32X4Zrmikz:
21982 case VSHUFI32X4Zrri:
21983 case VSHUFI32X4Zrrik:
21984 case VSHUFI32X4Zrrikz:
21985 return true;
21986 }
21987 return false;
21988}
21989
21990bool isSAHF(unsigned Opcode) {
21991 return Opcode == SAHF;
21992}
21993
21994bool isPFRSQRT(unsigned Opcode) {
21995 switch (Opcode) {
21996 case PFRSQRTrm:
21997 case PFRSQRTrr:
21998 return true;
21999 }
22000 return false;
22001}
22002
22003bool isSHRD(unsigned Opcode) {
22004 switch (Opcode) {
22005 case SHRD16mrCL:
22006 case SHRD16mrCL_EVEX:
22007 case SHRD16mrCL_ND:
22008 case SHRD16mrCL_NF:
22009 case SHRD16mrCL_NF_ND:
22010 case SHRD16mri8:
22011 case SHRD16mri8_EVEX:
22012 case SHRD16mri8_ND:
22013 case SHRD16mri8_NF:
22014 case SHRD16mri8_NF_ND:
22015 case SHRD16rrCL:
22016 case SHRD16rrCL_EVEX:
22017 case SHRD16rrCL_ND:
22018 case SHRD16rrCL_NF:
22019 case SHRD16rrCL_NF_ND:
22020 case SHRD16rri8:
22021 case SHRD16rri8_EVEX:
22022 case SHRD16rri8_ND:
22023 case SHRD16rri8_NF:
22024 case SHRD16rri8_NF_ND:
22025 case SHRD32mrCL:
22026 case SHRD32mrCL_EVEX:
22027 case SHRD32mrCL_ND:
22028 case SHRD32mrCL_NF:
22029 case SHRD32mrCL_NF_ND:
22030 case SHRD32mri8:
22031 case SHRD32mri8_EVEX:
22032 case SHRD32mri8_ND:
22033 case SHRD32mri8_NF:
22034 case SHRD32mri8_NF_ND:
22035 case SHRD32rrCL:
22036 case SHRD32rrCL_EVEX:
22037 case SHRD32rrCL_ND:
22038 case SHRD32rrCL_NF:
22039 case SHRD32rrCL_NF_ND:
22040 case SHRD32rri8:
22041 case SHRD32rri8_EVEX:
22042 case SHRD32rri8_ND:
22043 case SHRD32rri8_NF:
22044 case SHRD32rri8_NF_ND:
22045 case SHRD64mrCL:
22046 case SHRD64mrCL_EVEX:
22047 case SHRD64mrCL_ND:
22048 case SHRD64mrCL_NF:
22049 case SHRD64mrCL_NF_ND:
22050 case SHRD64mri8:
22051 case SHRD64mri8_EVEX:
22052 case SHRD64mri8_ND:
22053 case SHRD64mri8_NF:
22054 case SHRD64mri8_NF_ND:
22055 case SHRD64rrCL:
22056 case SHRD64rrCL_EVEX:
22057 case SHRD64rrCL_ND:
22058 case SHRD64rrCL_NF:
22059 case SHRD64rrCL_NF_ND:
22060 case SHRD64rri8:
22061 case SHRD64rri8_EVEX:
22062 case SHRD64rri8_ND:
22063 case SHRD64rri8_NF:
22064 case SHRD64rri8_NF_ND:
22065 return true;
22066 }
22067 return false;
22068}
22069
22070bool isSYSEXIT(unsigned Opcode) {
22071 return Opcode == SYSEXIT;
22072}
22073
22074bool isXSAVE64(unsigned Opcode) {
22075 return Opcode == XSAVE64;
22076}
22077
22078bool isVPMAXSD(unsigned Opcode) {
22079 switch (Opcode) {
22080 case VPMAXSDYrm:
22081 case VPMAXSDYrr:
22082 case VPMAXSDZ128rm:
22083 case VPMAXSDZ128rmb:
22084 case VPMAXSDZ128rmbk:
22085 case VPMAXSDZ128rmbkz:
22086 case VPMAXSDZ128rmk:
22087 case VPMAXSDZ128rmkz:
22088 case VPMAXSDZ128rr:
22089 case VPMAXSDZ128rrk:
22090 case VPMAXSDZ128rrkz:
22091 case VPMAXSDZ256rm:
22092 case VPMAXSDZ256rmb:
22093 case VPMAXSDZ256rmbk:
22094 case VPMAXSDZ256rmbkz:
22095 case VPMAXSDZ256rmk:
22096 case VPMAXSDZ256rmkz:
22097 case VPMAXSDZ256rr:
22098 case VPMAXSDZ256rrk:
22099 case VPMAXSDZ256rrkz:
22100 case VPMAXSDZrm:
22101 case VPMAXSDZrmb:
22102 case VPMAXSDZrmbk:
22103 case VPMAXSDZrmbkz:
22104 case VPMAXSDZrmk:
22105 case VPMAXSDZrmkz:
22106 case VPMAXSDZrr:
22107 case VPMAXSDZrrk:
22108 case VPMAXSDZrrkz:
22109 case VPMAXSDrm:
22110 case VPMAXSDrr:
22111 return true;
22112 }
22113 return false;
22114}
22115
22116bool isCVTTSD2SI(unsigned Opcode) {
22117 switch (Opcode) {
22118 case CVTTSD2SI64rm_Int:
22119 case CVTTSD2SI64rr_Int:
22120 case CVTTSD2SIrm_Int:
22121 case CVTTSD2SIrr_Int:
22122 return true;
22123 }
22124 return false;
22125}
22126
22127bool isPMOVMSKB(unsigned Opcode) {
22128 switch (Opcode) {
22129 case MMX_PMOVMSKBrr:
22130 case PMOVMSKBrr:
22131 return true;
22132 }
22133 return false;
22134}
22135
22136bool isVRANGEPS(unsigned Opcode) {
22137 switch (Opcode) {
22138 case VRANGEPSZ128rmbi:
22139 case VRANGEPSZ128rmbik:
22140 case VRANGEPSZ128rmbikz:
22141 case VRANGEPSZ128rmi:
22142 case VRANGEPSZ128rmik:
22143 case VRANGEPSZ128rmikz:
22144 case VRANGEPSZ128rri:
22145 case VRANGEPSZ128rrik:
22146 case VRANGEPSZ128rrikz:
22147 case VRANGEPSZ256rmbi:
22148 case VRANGEPSZ256rmbik:
22149 case VRANGEPSZ256rmbikz:
22150 case VRANGEPSZ256rmi:
22151 case VRANGEPSZ256rmik:
22152 case VRANGEPSZ256rmikz:
22153 case VRANGEPSZ256rri:
22154 case VRANGEPSZ256rrik:
22155 case VRANGEPSZ256rrikz:
22156 case VRANGEPSZrmbi:
22157 case VRANGEPSZrmbik:
22158 case VRANGEPSZrmbikz:
22159 case VRANGEPSZrmi:
22160 case VRANGEPSZrmik:
22161 case VRANGEPSZrmikz:
22162 case VRANGEPSZrri:
22163 case VRANGEPSZrrib:
22164 case VRANGEPSZrribk:
22165 case VRANGEPSZrribkz:
22166 case VRANGEPSZrrik:
22167 case VRANGEPSZrrikz:
22168 return true;
22169 }
22170 return false;
22171}
22172
22173bool isVADDSUBPS(unsigned Opcode) {
22174 switch (Opcode) {
22175 case VADDSUBPSYrm:
22176 case VADDSUBPSYrr:
22177 case VADDSUBPSrm:
22178 case VADDSUBPSrr:
22179 return true;
22180 }
22181 return false;
22182}
22183
22184bool isVBROADCASTI128(unsigned Opcode) {
22185 return Opcode == VBROADCASTI128rm;
22186}
22187
22188bool isPADDUSB(unsigned Opcode) {
22189 switch (Opcode) {
22190 case MMX_PADDUSBrm:
22191 case MMX_PADDUSBrr:
22192 case PADDUSBrm:
22193 case PADDUSBrr:
22194 return true;
22195 }
22196 return false;
22197}
22198
22199bool isENCODEKEY128(unsigned Opcode) {
22200 return Opcode == ENCODEKEY128;
22201}
22202
22203bool isOR(unsigned Opcode) {
22204 switch (Opcode) {
22205 case OR16i16:
22206 case OR16mi:
22207 case OR16mi8:
22208 case OR16mi8_EVEX:
22209 case OR16mi8_ND:
22210 case OR16mi8_NF:
22211 case OR16mi8_NF_ND:
22212 case OR16mi_EVEX:
22213 case OR16mi_ND:
22214 case OR16mi_NF:
22215 case OR16mi_NF_ND:
22216 case OR16mr:
22217 case OR16mr_EVEX:
22218 case OR16mr_ND:
22219 case OR16mr_NF:
22220 case OR16mr_NF_ND:
22221 case OR16ri:
22222 case OR16ri8:
22223 case OR16ri8_EVEX:
22224 case OR16ri8_ND:
22225 case OR16ri8_NF:
22226 case OR16ri8_NF_ND:
22227 case OR16ri_EVEX:
22228 case OR16ri_ND:
22229 case OR16ri_NF:
22230 case OR16ri_NF_ND:
22231 case OR16rm:
22232 case OR16rm_EVEX:
22233 case OR16rm_ND:
22234 case OR16rm_NF:
22235 case OR16rm_NF_ND:
22236 case OR16rr:
22237 case OR16rr_EVEX:
22238 case OR16rr_EVEX_REV:
22239 case OR16rr_ND:
22240 case OR16rr_ND_REV:
22241 case OR16rr_NF:
22242 case OR16rr_NF_ND:
22243 case OR16rr_NF_ND_REV:
22244 case OR16rr_NF_REV:
22245 case OR16rr_REV:
22246 case OR32i32:
22247 case OR32mi:
22248 case OR32mi8:
22249 case OR32mi8_EVEX:
22250 case OR32mi8_ND:
22251 case OR32mi8_NF:
22252 case OR32mi8_NF_ND:
22253 case OR32mi_EVEX:
22254 case OR32mi_ND:
22255 case OR32mi_NF:
22256 case OR32mi_NF_ND:
22257 case OR32mr:
22258 case OR32mr_EVEX:
22259 case OR32mr_ND:
22260 case OR32mr_NF:
22261 case OR32mr_NF_ND:
22262 case OR32ri:
22263 case OR32ri8:
22264 case OR32ri8_EVEX:
22265 case OR32ri8_ND:
22266 case OR32ri8_NF:
22267 case OR32ri8_NF_ND:
22268 case OR32ri_EVEX:
22269 case OR32ri_ND:
22270 case OR32ri_NF:
22271 case OR32ri_NF_ND:
22272 case OR32rm:
22273 case OR32rm_EVEX:
22274 case OR32rm_ND:
22275 case OR32rm_NF:
22276 case OR32rm_NF_ND:
22277 case OR32rr:
22278 case OR32rr_EVEX:
22279 case OR32rr_EVEX_REV:
22280 case OR32rr_ND:
22281 case OR32rr_ND_REV:
22282 case OR32rr_NF:
22283 case OR32rr_NF_ND:
22284 case OR32rr_NF_ND_REV:
22285 case OR32rr_NF_REV:
22286 case OR32rr_REV:
22287 case OR64i32:
22288 case OR64mi32:
22289 case OR64mi32_EVEX:
22290 case OR64mi32_ND:
22291 case OR64mi32_NF:
22292 case OR64mi32_NF_ND:
22293 case OR64mi8:
22294 case OR64mi8_EVEX:
22295 case OR64mi8_ND:
22296 case OR64mi8_NF:
22297 case OR64mi8_NF_ND:
22298 case OR64mr:
22299 case OR64mr_EVEX:
22300 case OR64mr_ND:
22301 case OR64mr_NF:
22302 case OR64mr_NF_ND:
22303 case OR64ri32:
22304 case OR64ri32_EVEX:
22305 case OR64ri32_ND:
22306 case OR64ri32_NF:
22307 case OR64ri32_NF_ND:
22308 case OR64ri8:
22309 case OR64ri8_EVEX:
22310 case OR64ri8_ND:
22311 case OR64ri8_NF:
22312 case OR64ri8_NF_ND:
22313 case OR64rm:
22314 case OR64rm_EVEX:
22315 case OR64rm_ND:
22316 case OR64rm_NF:
22317 case OR64rm_NF_ND:
22318 case OR64rr:
22319 case OR64rr_EVEX:
22320 case OR64rr_EVEX_REV:
22321 case OR64rr_ND:
22322 case OR64rr_ND_REV:
22323 case OR64rr_NF:
22324 case OR64rr_NF_ND:
22325 case OR64rr_NF_ND_REV:
22326 case OR64rr_NF_REV:
22327 case OR64rr_REV:
22328 case OR8i8:
22329 case OR8mi:
22330 case OR8mi8:
22331 case OR8mi_EVEX:
22332 case OR8mi_ND:
22333 case OR8mi_NF:
22334 case OR8mi_NF_ND:
22335 case OR8mr:
22336 case OR8mr_EVEX:
22337 case OR8mr_ND:
22338 case OR8mr_NF:
22339 case OR8mr_NF_ND:
22340 case OR8ri:
22341 case OR8ri8:
22342 case OR8ri_EVEX:
22343 case OR8ri_ND:
22344 case OR8ri_NF:
22345 case OR8ri_NF_ND:
22346 case OR8rm:
22347 case OR8rm_EVEX:
22348 case OR8rm_ND:
22349 case OR8rm_NF:
22350 case OR8rm_NF_ND:
22351 case OR8rr:
22352 case OR8rr_EVEX:
22353 case OR8rr_EVEX_REV:
22354 case OR8rr_ND:
22355 case OR8rr_ND_REV:
22356 case OR8rr_NF:
22357 case OR8rr_NF_ND:
22358 case OR8rr_NF_ND_REV:
22359 case OR8rr_NF_REV:
22360 case OR8rr_REV:
22361 return true;
22362 }
22363 return false;
22364}
22365
22366bool isSTOSW(unsigned Opcode) {
22367 return Opcode == STOSW;
22368}
22369
22370bool isPAVGW(unsigned Opcode) {
22371 switch (Opcode) {
22372 case MMX_PAVGWrm:
22373 case MMX_PAVGWrr:
22374 case PAVGWrm:
22375 case PAVGWrr:
22376 return true;
22377 }
22378 return false;
22379}
22380
22381bool isVCVTPD2PH(unsigned Opcode) {
22382 switch (Opcode) {
22383 case VCVTPD2PHZ128rm:
22384 case VCVTPD2PHZ128rmb:
22385 case VCVTPD2PHZ128rmbk:
22386 case VCVTPD2PHZ128rmbkz:
22387 case VCVTPD2PHZ128rmk:
22388 case VCVTPD2PHZ128rmkz:
22389 case VCVTPD2PHZ128rr:
22390 case VCVTPD2PHZ128rrk:
22391 case VCVTPD2PHZ128rrkz:
22392 case VCVTPD2PHZ256rm:
22393 case VCVTPD2PHZ256rmb:
22394 case VCVTPD2PHZ256rmbk:
22395 case VCVTPD2PHZ256rmbkz:
22396 case VCVTPD2PHZ256rmk:
22397 case VCVTPD2PHZ256rmkz:
22398 case VCVTPD2PHZ256rr:
22399 case VCVTPD2PHZ256rrk:
22400 case VCVTPD2PHZ256rrkz:
22401 case VCVTPD2PHZrm:
22402 case VCVTPD2PHZrmb:
22403 case VCVTPD2PHZrmbk:
22404 case VCVTPD2PHZrmbkz:
22405 case VCVTPD2PHZrmk:
22406 case VCVTPD2PHZrmkz:
22407 case VCVTPD2PHZrr:
22408 case VCVTPD2PHZrrb:
22409 case VCVTPD2PHZrrbk:
22410 case VCVTPD2PHZrrbkz:
22411 case VCVTPD2PHZrrk:
22412 case VCVTPD2PHZrrkz:
22413 return true;
22414 }
22415 return false;
22416}
22417
22418bool isSHLX(unsigned Opcode) {
22419 switch (Opcode) {
22420 case SHLX32rm:
22421 case SHLX32rm_EVEX:
22422 case SHLX32rr:
22423 case SHLX32rr_EVEX:
22424 case SHLX64rm:
22425 case SHLX64rm_EVEX:
22426 case SHLX64rr:
22427 case SHLX64rr_EVEX:
22428 return true;
22429 }
22430 return false;
22431}
22432
22433bool isVCVTSH2SD(unsigned Opcode) {
22434 switch (Opcode) {
22435 case VCVTSH2SDZrm_Int:
22436 case VCVTSH2SDZrm_Intk:
22437 case VCVTSH2SDZrm_Intkz:
22438 case VCVTSH2SDZrr_Int:
22439 case VCVTSH2SDZrr_Intk:
22440 case VCVTSH2SDZrr_Intkz:
22441 case VCVTSH2SDZrrb_Int:
22442 case VCVTSH2SDZrrb_Intk:
22443 case VCVTSH2SDZrrb_Intkz:
22444 return true;
22445 }
22446 return false;
22447}
22448
22449bool isVFMADD231SS(unsigned Opcode) {
22450 switch (Opcode) {
22451 case VFMADD231SSZm_Int:
22452 case VFMADD231SSZm_Intk:
22453 case VFMADD231SSZm_Intkz:
22454 case VFMADD231SSZr_Int:
22455 case VFMADD231SSZr_Intk:
22456 case VFMADD231SSZr_Intkz:
22457 case VFMADD231SSZrb_Int:
22458 case VFMADD231SSZrb_Intk:
22459 case VFMADD231SSZrb_Intkz:
22460 case VFMADD231SSm_Int:
22461 case VFMADD231SSr_Int:
22462 return true;
22463 }
22464 return false;
22465}
22466
22467bool isMOVNTSD(unsigned Opcode) {
22468 return Opcode == MOVNTSD;
22469}
22470
22471bool isFLDPI(unsigned Opcode) {
22472 return Opcode == FLDPI;
22473}
22474
22475bool isVCVTUSI2SS(unsigned Opcode) {
22476 switch (Opcode) {
22477 case VCVTUSI2SSZrm_Int:
22478 case VCVTUSI2SSZrr_Int:
22479 case VCVTUSI2SSZrrb_Int:
22480 case VCVTUSI642SSZrm_Int:
22481 case VCVTUSI642SSZrr_Int:
22482 case VCVTUSI642SSZrrb_Int:
22483 return true;
22484 }
22485 return false;
22486}
22487
22488bool isPMOVSXBD(unsigned Opcode) {
22489 switch (Opcode) {
22490 case PMOVSXBDrm:
22491 case PMOVSXBDrr:
22492 return true;
22493 }
22494 return false;
22495}
22496
22497bool isVPRORVQ(unsigned Opcode) {
22498 switch (Opcode) {
22499 case VPRORVQZ128rm:
22500 case VPRORVQZ128rmb:
22501 case VPRORVQZ128rmbk:
22502 case VPRORVQZ128rmbkz:
22503 case VPRORVQZ128rmk:
22504 case VPRORVQZ128rmkz:
22505 case VPRORVQZ128rr:
22506 case VPRORVQZ128rrk:
22507 case VPRORVQZ128rrkz:
22508 case VPRORVQZ256rm:
22509 case VPRORVQZ256rmb:
22510 case VPRORVQZ256rmbk:
22511 case VPRORVQZ256rmbkz:
22512 case VPRORVQZ256rmk:
22513 case VPRORVQZ256rmkz:
22514 case VPRORVQZ256rr:
22515 case VPRORVQZ256rrk:
22516 case VPRORVQZ256rrkz:
22517 case VPRORVQZrm:
22518 case VPRORVQZrmb:
22519 case VPRORVQZrmbk:
22520 case VPRORVQZrmbkz:
22521 case VPRORVQZrmk:
22522 case VPRORVQZrmkz:
22523 case VPRORVQZrr:
22524 case VPRORVQZrrk:
22525 case VPRORVQZrrkz:
22526 return true;
22527 }
22528 return false;
22529}
22530
22531bool isVPERMT2D(unsigned Opcode) {
22532 switch (Opcode) {
22533 case VPERMT2DZ128rm:
22534 case VPERMT2DZ128rmb:
22535 case VPERMT2DZ128rmbk:
22536 case VPERMT2DZ128rmbkz:
22537 case VPERMT2DZ128rmk:
22538 case VPERMT2DZ128rmkz:
22539 case VPERMT2DZ128rr:
22540 case VPERMT2DZ128rrk:
22541 case VPERMT2DZ128rrkz:
22542 case VPERMT2DZ256rm:
22543 case VPERMT2DZ256rmb:
22544 case VPERMT2DZ256rmbk:
22545 case VPERMT2DZ256rmbkz:
22546 case VPERMT2DZ256rmk:
22547 case VPERMT2DZ256rmkz:
22548 case VPERMT2DZ256rr:
22549 case VPERMT2DZ256rrk:
22550 case VPERMT2DZ256rrkz:
22551 case VPERMT2DZrm:
22552 case VPERMT2DZrmb:
22553 case VPERMT2DZrmbk:
22554 case VPERMT2DZrmbkz:
22555 case VPERMT2DZrmk:
22556 case VPERMT2DZrmkz:
22557 case VPERMT2DZrr:
22558 case VPERMT2DZrrk:
22559 case VPERMT2DZrrkz:
22560 return true;
22561 }
22562 return false;
22563}
22564
22565bool isADDSS(unsigned Opcode) {
22566 switch (Opcode) {
22567 case ADDSSrm_Int:
22568 case ADDSSrr_Int:
22569 return true;
22570 }
22571 return false;
22572}
22573
22574bool isAADD(unsigned Opcode) {
22575 switch (Opcode) {
22576 case AADD32mr:
22577 case AADD32mr_EVEX:
22578 case AADD64mr:
22579 case AADD64mr_EVEX:
22580 return true;
22581 }
22582 return false;
22583}
22584
22585bool isVPSRLVW(unsigned Opcode) {
22586 switch (Opcode) {
22587 case VPSRLVWZ128rm:
22588 case VPSRLVWZ128rmk:
22589 case VPSRLVWZ128rmkz:
22590 case VPSRLVWZ128rr:
22591 case VPSRLVWZ128rrk:
22592 case VPSRLVWZ128rrkz:
22593 case VPSRLVWZ256rm:
22594 case VPSRLVWZ256rmk:
22595 case VPSRLVWZ256rmkz:
22596 case VPSRLVWZ256rr:
22597 case VPSRLVWZ256rrk:
22598 case VPSRLVWZ256rrkz:
22599 case VPSRLVWZrm:
22600 case VPSRLVWZrmk:
22601 case VPSRLVWZrmkz:
22602 case VPSRLVWZrr:
22603 case VPSRLVWZrrk:
22604 case VPSRLVWZrrkz:
22605 return true;
22606 }
22607 return false;
22608}
22609
22610bool isVRSQRTPH(unsigned Opcode) {
22611 switch (Opcode) {
22612 case VRSQRTPHZ128m:
22613 case VRSQRTPHZ128mb:
22614 case VRSQRTPHZ128mbk:
22615 case VRSQRTPHZ128mbkz:
22616 case VRSQRTPHZ128mk:
22617 case VRSQRTPHZ128mkz:
22618 case VRSQRTPHZ128r:
22619 case VRSQRTPHZ128rk:
22620 case VRSQRTPHZ128rkz:
22621 case VRSQRTPHZ256m:
22622 case VRSQRTPHZ256mb:
22623 case VRSQRTPHZ256mbk:
22624 case VRSQRTPHZ256mbkz:
22625 case VRSQRTPHZ256mk:
22626 case VRSQRTPHZ256mkz:
22627 case VRSQRTPHZ256r:
22628 case VRSQRTPHZ256rk:
22629 case VRSQRTPHZ256rkz:
22630 case VRSQRTPHZm:
22631 case VRSQRTPHZmb:
22632 case VRSQRTPHZmbk:
22633 case VRSQRTPHZmbkz:
22634 case VRSQRTPHZmk:
22635 case VRSQRTPHZmkz:
22636 case VRSQRTPHZr:
22637 case VRSQRTPHZrk:
22638 case VRSQRTPHZrkz:
22639 return true;
22640 }
22641 return false;
22642}
22643
22644bool isVLDDQU(unsigned Opcode) {
22645 switch (Opcode) {
22646 case VLDDQUYrm:
22647 case VLDDQUrm:
22648 return true;
22649 }
22650 return false;
22651}
22652
22653bool isKMOVD(unsigned Opcode) {
22654 switch (Opcode) {
22655 case KMOVDkk:
22656 case KMOVDkk_EVEX:
22657 case KMOVDkm:
22658 case KMOVDkm_EVEX:
22659 case KMOVDkr:
22660 case KMOVDkr_EVEX:
22661 case KMOVDmk:
22662 case KMOVDmk_EVEX:
22663 case KMOVDrk:
22664 case KMOVDrk_EVEX:
22665 return true;
22666 }
22667 return false;
22668}
22669
22670bool isENCLV(unsigned Opcode) {
22671 return Opcode == ENCLV;
22672}
22673
22674bool isENCLU(unsigned Opcode) {
22675 return Opcode == ENCLU;
22676}
22677
22678bool isPREFETCHT1(unsigned Opcode) {
22679 return Opcode == PREFETCHT1;
22680}
22681
22682bool isRSQRTPS(unsigned Opcode) {
22683 switch (Opcode) {
22684 case RSQRTPSm:
22685 case RSQRTPSr:
22686 return true;
22687 }
22688 return false;
22689}
22690
22691bool isVCVTTSH2USI(unsigned Opcode) {
22692 switch (Opcode) {
22693 case VCVTTSH2USI64Zrm_Int:
22694 case VCVTTSH2USI64Zrr_Int:
22695 case VCVTTSH2USI64Zrrb_Int:
22696 case VCVTTSH2USIZrm_Int:
22697 case VCVTTSH2USIZrr_Int:
22698 case VCVTTSH2USIZrrb_Int:
22699 return true;
22700 }
22701 return false;
22702}
22703
22704bool isPADDB(unsigned Opcode) {
22705 switch (Opcode) {
22706 case MMX_PADDBrm:
22707 case MMX_PADDBrr:
22708 case PADDBrm:
22709 case PADDBrr:
22710 return true;
22711 }
22712 return false;
22713}
22714
22715bool isVMASKMOVDQU(unsigned Opcode) {
22716 return Opcode == VMASKMOVDQU64;
22717}
22718
22719bool isPUNPCKLBW(unsigned Opcode) {
22720 switch (Opcode) {
22721 case MMX_PUNPCKLBWrm:
22722 case MMX_PUNPCKLBWrr:
22723 case PUNPCKLBWrm:
22724 case PUNPCKLBWrr:
22725 return true;
22726 }
22727 return false;
22728}
22729
22730bool isMOV(unsigned Opcode) {
22731 switch (Opcode) {
22732 case MOV16ao16:
22733 case MOV16ao32:
22734 case MOV16mi:
22735 case MOV16mr:
22736 case MOV16ms:
22737 case MOV16o16a:
22738 case MOV16o32a:
22739 case MOV16ri:
22740 case MOV16ri_alt:
22741 case MOV16rm:
22742 case MOV16rr:
22743 case MOV16rr_REV:
22744 case MOV16rs:
22745 case MOV16sm:
22746 case MOV16sr:
22747 case MOV32ao16:
22748 case MOV32ao32:
22749 case MOV32cr:
22750 case MOV32dr:
22751 case MOV32mi:
22752 case MOV32mr:
22753 case MOV32o16a:
22754 case MOV32o32a:
22755 case MOV32rc:
22756 case MOV32rd:
22757 case MOV32ri:
22758 case MOV32ri_alt:
22759 case MOV32rm:
22760 case MOV32rr:
22761 case MOV32rr_REV:
22762 case MOV32rs:
22763 case MOV32sr:
22764 case MOV64ao32:
22765 case MOV64cr:
22766 case MOV64dr:
22767 case MOV64mi32:
22768 case MOV64mr:
22769 case MOV64o32a:
22770 case MOV64rc:
22771 case MOV64rd:
22772 case MOV64ri32:
22773 case MOV64rm:
22774 case MOV64rr:
22775 case MOV64rr_REV:
22776 case MOV64rs:
22777 case MOV64sr:
22778 case MOV8ao16:
22779 case MOV8ao32:
22780 case MOV8mi:
22781 case MOV8mr:
22782 case MOV8o16a:
22783 case MOV8o32a:
22784 case MOV8ri:
22785 case MOV8ri_alt:
22786 case MOV8rm:
22787 case MOV8rr:
22788 case MOV8rr_REV:
22789 return true;
22790 }
22791 return false;
22792}
22793
22794bool isMUL(unsigned Opcode) {
22795 switch (Opcode) {
22796 case MUL16m:
22797 case MUL16m_EVEX:
22798 case MUL16m_NF:
22799 case MUL16r:
22800 case MUL16r_EVEX:
22801 case MUL16r_NF:
22802 case MUL32m:
22803 case MUL32m_EVEX:
22804 case MUL32m_NF:
22805 case MUL32r:
22806 case MUL32r_EVEX:
22807 case MUL32r_NF:
22808 case MUL64m:
22809 case MUL64m_EVEX:
22810 case MUL64m_NF:
22811 case MUL64r:
22812 case MUL64r_EVEX:
22813 case MUL64r_NF:
22814 case MUL8m:
22815 case MUL8m_EVEX:
22816 case MUL8m_NF:
22817 case MUL8r:
22818 case MUL8r_EVEX:
22819 case MUL8r_NF:
22820 return true;
22821 }
22822 return false;
22823}
22824
22825bool isRCL(unsigned Opcode) {
22826 switch (Opcode) {
22827 case RCL16m1:
22828 case RCL16m1_EVEX:
22829 case RCL16m1_ND:
22830 case RCL16mCL:
22831 case RCL16mCL_EVEX:
22832 case RCL16mCL_ND:
22833 case RCL16mi:
22834 case RCL16mi_EVEX:
22835 case RCL16mi_ND:
22836 case RCL16r1:
22837 case RCL16r1_EVEX:
22838 case RCL16r1_ND:
22839 case RCL16rCL:
22840 case RCL16rCL_EVEX:
22841 case RCL16rCL_ND:
22842 case RCL16ri:
22843 case RCL16ri_EVEX:
22844 case RCL16ri_ND:
22845 case RCL32m1:
22846 case RCL32m1_EVEX:
22847 case RCL32m1_ND:
22848 case RCL32mCL:
22849 case RCL32mCL_EVEX:
22850 case RCL32mCL_ND:
22851 case RCL32mi:
22852 case RCL32mi_EVEX:
22853 case RCL32mi_ND:
22854 case RCL32r1:
22855 case RCL32r1_EVEX:
22856 case RCL32r1_ND:
22857 case RCL32rCL:
22858 case RCL32rCL_EVEX:
22859 case RCL32rCL_ND:
22860 case RCL32ri:
22861 case RCL32ri_EVEX:
22862 case RCL32ri_ND:
22863 case RCL64m1:
22864 case RCL64m1_EVEX:
22865 case RCL64m1_ND:
22866 case RCL64mCL:
22867 case RCL64mCL_EVEX:
22868 case RCL64mCL_ND:
22869 case RCL64mi:
22870 case RCL64mi_EVEX:
22871 case RCL64mi_ND:
22872 case RCL64r1:
22873 case RCL64r1_EVEX:
22874 case RCL64r1_ND:
22875 case RCL64rCL:
22876 case RCL64rCL_EVEX:
22877 case RCL64rCL_ND:
22878 case RCL64ri:
22879 case RCL64ri_EVEX:
22880 case RCL64ri_ND:
22881 case RCL8m1:
22882 case RCL8m1_EVEX:
22883 case RCL8m1_ND:
22884 case RCL8mCL:
22885 case RCL8mCL_EVEX:
22886 case RCL8mCL_ND:
22887 case RCL8mi:
22888 case RCL8mi_EVEX:
22889 case RCL8mi_ND:
22890 case RCL8r1:
22891 case RCL8r1_EVEX:
22892 case RCL8r1_ND:
22893 case RCL8rCL:
22894 case RCL8rCL_EVEX:
22895 case RCL8rCL_ND:
22896 case RCL8ri:
22897 case RCL8ri_EVEX:
22898 case RCL8ri_ND:
22899 return true;
22900 }
22901 return false;
22902}
22903
22904bool isVRCPSH(unsigned Opcode) {
22905 switch (Opcode) {
22906 case VRCPSHZrm:
22907 case VRCPSHZrmk:
22908 case VRCPSHZrmkz:
22909 case VRCPSHZrr:
22910 case VRCPSHZrrk:
22911 case VRCPSHZrrkz:
22912 return true;
22913 }
22914 return false;
22915}
22916
22917bool isPFCMPEQ(unsigned Opcode) {
22918 switch (Opcode) {
22919 case PFCMPEQrm:
22920 case PFCMPEQrr:
22921 return true;
22922 }
22923 return false;
22924}
22925
22926bool isMONITOR(unsigned Opcode) {
22927 switch (Opcode) {
22928 case MONITOR32rrr:
22929 case MONITOR64rrr:
22930 return true;
22931 }
22932 return false;
22933}
22934
22935bool isFDIVR(unsigned Opcode) {
22936 switch (Opcode) {
22937 case DIVR_F32m:
22938 case DIVR_F64m:
22939 case DIVR_FST0r:
22940 case DIVR_FrST0:
22941 return true;
22942 }
22943 return false;
22944}
22945
22946bool isPMINSD(unsigned Opcode) {
22947 switch (Opcode) {
22948 case PMINSDrm:
22949 case PMINSDrr:
22950 return true;
22951 }
22952 return false;
22953}
22954
22955bool isPFRCP(unsigned Opcode) {
22956 switch (Opcode) {
22957 case PFRCPrm:
22958 case PFRCPrr:
22959 return true;
22960 }
22961 return false;
22962}
22963
22964bool isKTESTQ(unsigned Opcode) {
22965 return Opcode == KTESTQrr;
22966}
22967
22968bool isVCVTTPD2DQ(unsigned Opcode) {
22969 switch (Opcode) {
22970 case VCVTTPD2DQYrm:
22971 case VCVTTPD2DQYrr:
22972 case VCVTTPD2DQZ128rm:
22973 case VCVTTPD2DQZ128rmb:
22974 case VCVTTPD2DQZ128rmbk:
22975 case VCVTTPD2DQZ128rmbkz:
22976 case VCVTTPD2DQZ128rmk:
22977 case VCVTTPD2DQZ128rmkz:
22978 case VCVTTPD2DQZ128rr:
22979 case VCVTTPD2DQZ128rrk:
22980 case VCVTTPD2DQZ128rrkz:
22981 case VCVTTPD2DQZ256rm:
22982 case VCVTTPD2DQZ256rmb:
22983 case VCVTTPD2DQZ256rmbk:
22984 case VCVTTPD2DQZ256rmbkz:
22985 case VCVTTPD2DQZ256rmk:
22986 case VCVTTPD2DQZ256rmkz:
22987 case VCVTTPD2DQZ256rr:
22988 case VCVTTPD2DQZ256rrk:
22989 case VCVTTPD2DQZ256rrkz:
22990 case VCVTTPD2DQZrm:
22991 case VCVTTPD2DQZrmb:
22992 case VCVTTPD2DQZrmbk:
22993 case VCVTTPD2DQZrmbkz:
22994 case VCVTTPD2DQZrmk:
22995 case VCVTTPD2DQZrmkz:
22996 case VCVTTPD2DQZrr:
22997 case VCVTTPD2DQZrrb:
22998 case VCVTTPD2DQZrrbk:
22999 case VCVTTPD2DQZrrbkz:
23000 case VCVTTPD2DQZrrk:
23001 case VCVTTPD2DQZrrkz:
23002 case VCVTTPD2DQrm:
23003 case VCVTTPD2DQrr:
23004 return true;
23005 }
23006 return false;
23007}
23008
23009bool isVSHUFF32X4(unsigned Opcode) {
23010 switch (Opcode) {
23011 case VSHUFF32X4Z256rmbi:
23012 case VSHUFF32X4Z256rmbik:
23013 case VSHUFF32X4Z256rmbikz:
23014 case VSHUFF32X4Z256rmi:
23015 case VSHUFF32X4Z256rmik:
23016 case VSHUFF32X4Z256rmikz:
23017 case VSHUFF32X4Z256rri:
23018 case VSHUFF32X4Z256rrik:
23019 case VSHUFF32X4Z256rrikz:
23020 case VSHUFF32X4Zrmbi:
23021 case VSHUFF32X4Zrmbik:
23022 case VSHUFF32X4Zrmbikz:
23023 case VSHUFF32X4Zrmi:
23024 case VSHUFF32X4Zrmik:
23025 case VSHUFF32X4Zrmikz:
23026 case VSHUFF32X4Zrri:
23027 case VSHUFF32X4Zrrik:
23028 case VSHUFF32X4Zrrikz:
23029 return true;
23030 }
23031 return false;
23032}
23033
23034bool isVPSLLVW(unsigned Opcode) {
23035 switch (Opcode) {
23036 case VPSLLVWZ128rm:
23037 case VPSLLVWZ128rmk:
23038 case VPSLLVWZ128rmkz:
23039 case VPSLLVWZ128rr:
23040 case VPSLLVWZ128rrk:
23041 case VPSLLVWZ128rrkz:
23042 case VPSLLVWZ256rm:
23043 case VPSLLVWZ256rmk:
23044 case VPSLLVWZ256rmkz:
23045 case VPSLLVWZ256rr:
23046 case VPSLLVWZ256rrk:
23047 case VPSLLVWZ256rrkz:
23048 case VPSLLVWZrm:
23049 case VPSLLVWZrmk:
23050 case VPSLLVWZrmkz:
23051 case VPSLLVWZrr:
23052 case VPSLLVWZrrk:
23053 case VPSLLVWZrrkz:
23054 return true;
23055 }
23056 return false;
23057}
23058
23059bool isTDPBSUD(unsigned Opcode) {
23060 return Opcode == TDPBSUD;
23061}
23062
23063bool isVPMINUQ(unsigned Opcode) {
23064 switch (Opcode) {
23065 case VPMINUQZ128rm:
23066 case VPMINUQZ128rmb:
23067 case VPMINUQZ128rmbk:
23068 case VPMINUQZ128rmbkz:
23069 case VPMINUQZ128rmk:
23070 case VPMINUQZ128rmkz:
23071 case VPMINUQZ128rr:
23072 case VPMINUQZ128rrk:
23073 case VPMINUQZ128rrkz:
23074 case VPMINUQZ256rm:
23075 case VPMINUQZ256rmb:
23076 case VPMINUQZ256rmbk:
23077 case VPMINUQZ256rmbkz:
23078 case VPMINUQZ256rmk:
23079 case VPMINUQZ256rmkz:
23080 case VPMINUQZ256rr:
23081 case VPMINUQZ256rrk:
23082 case VPMINUQZ256rrkz:
23083 case VPMINUQZrm:
23084 case VPMINUQZrmb:
23085 case VPMINUQZrmbk:
23086 case VPMINUQZrmbkz:
23087 case VPMINUQZrmk:
23088 case VPMINUQZrmkz:
23089 case VPMINUQZrr:
23090 case VPMINUQZrrk:
23091 case VPMINUQZrrkz:
23092 return true;
23093 }
23094 return false;
23095}
23096
23097bool isFIADD(unsigned Opcode) {
23098 switch (Opcode) {
23099 case ADD_FI16m:
23100 case ADD_FI32m:
23101 return true;
23102 }
23103 return false;
23104}
23105
23106bool isFCMOVNU(unsigned Opcode) {
23107 return Opcode == CMOVNP_F;
23108}
23109
23110bool isVHSUBPD(unsigned Opcode) {
23111 switch (Opcode) {
23112 case VHSUBPDYrm:
23113 case VHSUBPDYrr:
23114 case VHSUBPDrm:
23115 case VHSUBPDrr:
23116 return true;
23117 }
23118 return false;
23119}
23120
23121bool isKSHIFTRQ(unsigned Opcode) {
23122 return Opcode == KSHIFTRQri;
23123}
23124
23125bool isMOVUPS(unsigned Opcode) {
23126 switch (Opcode) {
23127 case MOVUPSmr:
23128 case MOVUPSrm:
23129 case MOVUPSrr:
23130 case MOVUPSrr_REV:
23131 return true;
23132 }
23133 return false;
23134}
23135
23136bool isVMCALL(unsigned Opcode) {
23137 return Opcode == VMCALL;
23138}
23139
23140bool isXADD(unsigned Opcode) {
23141 switch (Opcode) {
23142 case XADD16rm:
23143 case XADD16rr:
23144 case XADD32rm:
23145 case XADD32rr:
23146 case XADD64rm:
23147 case XADD64rr:
23148 case XADD8rm:
23149 case XADD8rr:
23150 return true;
23151 }
23152 return false;
23153}
23154
23155bool isXRSTOR(unsigned Opcode) {
23156 return Opcode == XRSTOR;
23157}
23158
23159bool isVGATHERPF1DPD(unsigned Opcode) {
23160 return Opcode == VGATHERPF1DPDm;
23161}
23162
23163bool isRCR(unsigned Opcode) {
23164 switch (Opcode) {
23165 case RCR16m1:
23166 case RCR16m1_EVEX:
23167 case RCR16m1_ND:
23168 case RCR16mCL:
23169 case RCR16mCL_EVEX:
23170 case RCR16mCL_ND:
23171 case RCR16mi:
23172 case RCR16mi_EVEX:
23173 case RCR16mi_ND:
23174 case RCR16r1:
23175 case RCR16r1_EVEX:
23176 case RCR16r1_ND:
23177 case RCR16rCL:
23178 case RCR16rCL_EVEX:
23179 case RCR16rCL_ND:
23180 case RCR16ri:
23181 case RCR16ri_EVEX:
23182 case RCR16ri_ND:
23183 case RCR32m1:
23184 case RCR32m1_EVEX:
23185 case RCR32m1_ND:
23186 case RCR32mCL:
23187 case RCR32mCL_EVEX:
23188 case RCR32mCL_ND:
23189 case RCR32mi:
23190 case RCR32mi_EVEX:
23191 case RCR32mi_ND:
23192 case RCR32r1:
23193 case RCR32r1_EVEX:
23194 case RCR32r1_ND:
23195 case RCR32rCL:
23196 case RCR32rCL_EVEX:
23197 case RCR32rCL_ND:
23198 case RCR32ri:
23199 case RCR32ri_EVEX:
23200 case RCR32ri_ND:
23201 case RCR64m1:
23202 case RCR64m1_EVEX:
23203 case RCR64m1_ND:
23204 case RCR64mCL:
23205 case RCR64mCL_EVEX:
23206 case RCR64mCL_ND:
23207 case RCR64mi:
23208 case RCR64mi_EVEX:
23209 case RCR64mi_ND:
23210 case RCR64r1:
23211 case RCR64r1_EVEX:
23212 case RCR64r1_ND:
23213 case RCR64rCL:
23214 case RCR64rCL_EVEX:
23215 case RCR64rCL_ND:
23216 case RCR64ri:
23217 case RCR64ri_EVEX:
23218 case RCR64ri_ND:
23219 case RCR8m1:
23220 case RCR8m1_EVEX:
23221 case RCR8m1_ND:
23222 case RCR8mCL:
23223 case RCR8mCL_EVEX:
23224 case RCR8mCL_ND:
23225 case RCR8mi:
23226 case RCR8mi_EVEX:
23227 case RCR8mi_ND:
23228 case RCR8r1:
23229 case RCR8r1_EVEX:
23230 case RCR8r1_ND:
23231 case RCR8rCL:
23232 case RCR8rCL_EVEX:
23233 case RCR8rCL_ND:
23234 case RCR8ri:
23235 case RCR8ri_EVEX:
23236 case RCR8ri_ND:
23237 return true;
23238 }
23239 return false;
23240}
23241
23242bool isFNSTCW(unsigned Opcode) {
23243 return Opcode == FNSTCW16m;
23244}
23245
23246bool isVPMOVSDW(unsigned Opcode) {
23247 switch (Opcode) {
23248 case VPMOVSDWZ128mr:
23249 case VPMOVSDWZ128mrk:
23250 case VPMOVSDWZ128rr:
23251 case VPMOVSDWZ128rrk:
23252 case VPMOVSDWZ128rrkz:
23253 case VPMOVSDWZ256mr:
23254 case VPMOVSDWZ256mrk:
23255 case VPMOVSDWZ256rr:
23256 case VPMOVSDWZ256rrk:
23257 case VPMOVSDWZ256rrkz:
23258 case VPMOVSDWZmr:
23259 case VPMOVSDWZmrk:
23260 case VPMOVSDWZrr:
23261 case VPMOVSDWZrrk:
23262 case VPMOVSDWZrrkz:
23263 return true;
23264 }
23265 return false;
23266}
23267
23268bool isVFMSUB132SH(unsigned Opcode) {
23269 switch (Opcode) {
23270 case VFMSUB132SHZm_Int:
23271 case VFMSUB132SHZm_Intk:
23272 case VFMSUB132SHZm_Intkz:
23273 case VFMSUB132SHZr_Int:
23274 case VFMSUB132SHZr_Intk:
23275 case VFMSUB132SHZr_Intkz:
23276 case VFMSUB132SHZrb_Int:
23277 case VFMSUB132SHZrb_Intk:
23278 case VFMSUB132SHZrb_Intkz:
23279 return true;
23280 }
23281 return false;
23282}
23283
23284bool isVPCONFLICTQ(unsigned Opcode) {
23285 switch (Opcode) {
23286 case VPCONFLICTQZ128rm:
23287 case VPCONFLICTQZ128rmb:
23288 case VPCONFLICTQZ128rmbk:
23289 case VPCONFLICTQZ128rmbkz:
23290 case VPCONFLICTQZ128rmk:
23291 case VPCONFLICTQZ128rmkz:
23292 case VPCONFLICTQZ128rr:
23293 case VPCONFLICTQZ128rrk:
23294 case VPCONFLICTQZ128rrkz:
23295 case VPCONFLICTQZ256rm:
23296 case VPCONFLICTQZ256rmb:
23297 case VPCONFLICTQZ256rmbk:
23298 case VPCONFLICTQZ256rmbkz:
23299 case VPCONFLICTQZ256rmk:
23300 case VPCONFLICTQZ256rmkz:
23301 case VPCONFLICTQZ256rr:
23302 case VPCONFLICTQZ256rrk:
23303 case VPCONFLICTQZ256rrkz:
23304 case VPCONFLICTQZrm:
23305 case VPCONFLICTQZrmb:
23306 case VPCONFLICTQZrmbk:
23307 case VPCONFLICTQZrmbkz:
23308 case VPCONFLICTQZrmk:
23309 case VPCONFLICTQZrmkz:
23310 case VPCONFLICTQZrr:
23311 case VPCONFLICTQZrrk:
23312 case VPCONFLICTQZrrkz:
23313 return true;
23314 }
23315 return false;
23316}
23317
23318bool isSWAPGS(unsigned Opcode) {
23319 return Opcode == SWAPGS;
23320}
23321
23322bool isVPMOVQ2M(unsigned Opcode) {
23323 switch (Opcode) {
23324 case VPMOVQ2MZ128rr:
23325 case VPMOVQ2MZ256rr:
23326 case VPMOVQ2MZrr:
23327 return true;
23328 }
23329 return false;
23330}
23331
23332bool isVPSRAVW(unsigned Opcode) {
23333 switch (Opcode) {
23334 case VPSRAVWZ128rm:
23335 case VPSRAVWZ128rmk:
23336 case VPSRAVWZ128rmkz:
23337 case VPSRAVWZ128rr:
23338 case VPSRAVWZ128rrk:
23339 case VPSRAVWZ128rrkz:
23340 case VPSRAVWZ256rm:
23341 case VPSRAVWZ256rmk:
23342 case VPSRAVWZ256rmkz:
23343 case VPSRAVWZ256rr:
23344 case VPSRAVWZ256rrk:
23345 case VPSRAVWZ256rrkz:
23346 case VPSRAVWZrm:
23347 case VPSRAVWZrmk:
23348 case VPSRAVWZrmkz:
23349 case VPSRAVWZrr:
23350 case VPSRAVWZrrk:
23351 case VPSRAVWZrrkz:
23352 return true;
23353 }
23354 return false;
23355}
23356
23357bool isMOVDQA(unsigned Opcode) {
23358 switch (Opcode) {
23359 case MOVDQAmr:
23360 case MOVDQArm:
23361 case MOVDQArr:
23362 case MOVDQArr_REV:
23363 return true;
23364 }
23365 return false;
23366}
23367
23368bool isDIVSD(unsigned Opcode) {
23369 switch (Opcode) {
23370 case DIVSDrm_Int:
23371 case DIVSDrr_Int:
23372 return true;
23373 }
23374 return false;
23375}
23376
23377bool isPCMPGTB(unsigned Opcode) {
23378 switch (Opcode) {
23379 case MMX_PCMPGTBrm:
23380 case MMX_PCMPGTBrr:
23381 case PCMPGTBrm:
23382 case PCMPGTBrr:
23383 return true;
23384 }
23385 return false;
23386}
23387
23388bool isSHA256MSG2(unsigned Opcode) {
23389 switch (Opcode) {
23390 case SHA256MSG2rm:
23391 case SHA256MSG2rr:
23392 return true;
23393 }
23394 return false;
23395}
23396
23397bool isKXORW(unsigned Opcode) {
23398 return Opcode == KXORWrr;
23399}
23400
23401bool isLIDTW(unsigned Opcode) {
23402 return Opcode == LIDT16m;
23403}
23404
23405bool isPMULHW(unsigned Opcode) {
23406 switch (Opcode) {
23407 case MMX_PMULHWrm:
23408 case MMX_PMULHWrr:
23409 case PMULHWrm:
23410 case PMULHWrr:
23411 return true;
23412 }
23413 return false;
23414}
23415
23416bool isVAESENCLAST(unsigned Opcode) {
23417 switch (Opcode) {
23418 case VAESENCLASTYrm:
23419 case VAESENCLASTYrr:
23420 case VAESENCLASTZ128rm:
23421 case VAESENCLASTZ128rr:
23422 case VAESENCLASTZ256rm:
23423 case VAESENCLASTZ256rr:
23424 case VAESENCLASTZrm:
23425 case VAESENCLASTZrr:
23426 case VAESENCLASTrm:
23427 case VAESENCLASTrr:
23428 return true;
23429 }
23430 return false;
23431}
23432
23433bool isVINSERTI32X8(unsigned Opcode) {
23434 switch (Opcode) {
23435 case VINSERTI32x8Zrm:
23436 case VINSERTI32x8Zrmk:
23437 case VINSERTI32x8Zrmkz:
23438 case VINSERTI32x8Zrr:
23439 case VINSERTI32x8Zrrk:
23440 case VINSERTI32x8Zrrkz:
23441 return true;
23442 }
23443 return false;
23444}
23445
23446bool isVRCPPS(unsigned Opcode) {
23447 switch (Opcode) {
23448 case VRCPPSYm:
23449 case VRCPPSYr:
23450 case VRCPPSm:
23451 case VRCPPSr:
23452 return true;
23453 }
23454 return false;
23455}
23456
23457bool isVGATHERQPS(unsigned Opcode) {
23458 switch (Opcode) {
23459 case VGATHERQPSYrm:
23460 case VGATHERQPSZ128rm:
23461 case VGATHERQPSZ256rm:
23462 case VGATHERQPSZrm:
23463 case VGATHERQPSrm:
23464 return true;
23465 }
23466 return false;
23467}
23468
23469bool isCTESTCC(unsigned Opcode) {
23470 switch (Opcode) {
23471 case CTEST16mi:
23472 case CTEST16mr:
23473 case CTEST16ri:
23474 case CTEST16rr:
23475 case CTEST32mi:
23476 case CTEST32mr:
23477 case CTEST32ri:
23478 case CTEST32rr:
23479 case CTEST64mi32:
23480 case CTEST64mr:
23481 case CTEST64ri32:
23482 case CTEST64rr:
23483 case CTEST8mi:
23484 case CTEST8mr:
23485 case CTEST8ri:
23486 case CTEST8rr:
23487 return true;
23488 }
23489 return false;
23490}
23491
23492bool isPMADDWD(unsigned Opcode) {
23493 switch (Opcode) {
23494 case MMX_PMADDWDrm:
23495 case MMX_PMADDWDrr:
23496 case PMADDWDrm:
23497 case PMADDWDrr:
23498 return true;
23499 }
23500 return false;
23501}
23502
23503bool isUCOMISS(unsigned Opcode) {
23504 switch (Opcode) {
23505 case UCOMISSrm:
23506 case UCOMISSrr:
23507 return true;
23508 }
23509 return false;
23510}
23511
23512bool isXGETBV(unsigned Opcode) {
23513 return Opcode == XGETBV;
23514}
23515
23516bool isVCVTPD2QQ(unsigned Opcode) {
23517 switch (Opcode) {
23518 case VCVTPD2QQZ128rm:
23519 case VCVTPD2QQZ128rmb:
23520 case VCVTPD2QQZ128rmbk:
23521 case VCVTPD2QQZ128rmbkz:
23522 case VCVTPD2QQZ128rmk:
23523 case VCVTPD2QQZ128rmkz:
23524 case VCVTPD2QQZ128rr:
23525 case VCVTPD2QQZ128rrk:
23526 case VCVTPD2QQZ128rrkz:
23527 case VCVTPD2QQZ256rm:
23528 case VCVTPD2QQZ256rmb:
23529 case VCVTPD2QQZ256rmbk:
23530 case VCVTPD2QQZ256rmbkz:
23531 case VCVTPD2QQZ256rmk:
23532 case VCVTPD2QQZ256rmkz:
23533 case VCVTPD2QQZ256rr:
23534 case VCVTPD2QQZ256rrk:
23535 case VCVTPD2QQZ256rrkz:
23536 case VCVTPD2QQZrm:
23537 case VCVTPD2QQZrmb:
23538 case VCVTPD2QQZrmbk:
23539 case VCVTPD2QQZrmbkz:
23540 case VCVTPD2QQZrmk:
23541 case VCVTPD2QQZrmkz:
23542 case VCVTPD2QQZrr:
23543 case VCVTPD2QQZrrb:
23544 case VCVTPD2QQZrrbk:
23545 case VCVTPD2QQZrrbkz:
23546 case VCVTPD2QQZrrk:
23547 case VCVTPD2QQZrrkz:
23548 return true;
23549 }
23550 return false;
23551}
23552
23553bool isVGETEXPPS(unsigned Opcode) {
23554 switch (Opcode) {
23555 case VGETEXPPSZ128m:
23556 case VGETEXPPSZ128mb:
23557 case VGETEXPPSZ128mbk:
23558 case VGETEXPPSZ128mbkz:
23559 case VGETEXPPSZ128mk:
23560 case VGETEXPPSZ128mkz:
23561 case VGETEXPPSZ128r:
23562 case VGETEXPPSZ128rk:
23563 case VGETEXPPSZ128rkz:
23564 case VGETEXPPSZ256m:
23565 case VGETEXPPSZ256mb:
23566 case VGETEXPPSZ256mbk:
23567 case VGETEXPPSZ256mbkz:
23568 case VGETEXPPSZ256mk:
23569 case VGETEXPPSZ256mkz:
23570 case VGETEXPPSZ256r:
23571 case VGETEXPPSZ256rk:
23572 case VGETEXPPSZ256rkz:
23573 case VGETEXPPSZm:
23574 case VGETEXPPSZmb:
23575 case VGETEXPPSZmbk:
23576 case VGETEXPPSZmbkz:
23577 case VGETEXPPSZmk:
23578 case VGETEXPPSZmkz:
23579 case VGETEXPPSZr:
23580 case VGETEXPPSZrb:
23581 case VGETEXPPSZrbk:
23582 case VGETEXPPSZrbkz:
23583 case VGETEXPPSZrk:
23584 case VGETEXPPSZrkz:
23585 return true;
23586 }
23587 return false;
23588}
23589
23590bool isFISTP(unsigned Opcode) {
23591 switch (Opcode) {
23592 case IST_FP16m:
23593 case IST_FP32m:
23594 case IST_FP64m:
23595 return true;
23596 }
23597 return false;
23598}
23599
23600bool isVINSERTF64X4(unsigned Opcode) {
23601 switch (Opcode) {
23602 case VINSERTF64x4Zrm:
23603 case VINSERTF64x4Zrmk:
23604 case VINSERTF64x4Zrmkz:
23605 case VINSERTF64x4Zrr:
23606 case VINSERTF64x4Zrrk:
23607 case VINSERTF64x4Zrrkz:
23608 return true;
23609 }
23610 return false;
23611}
23612
23613bool isVMOVDQU16(unsigned Opcode) {
23614 switch (Opcode) {
23615 case VMOVDQU16Z128mr:
23616 case VMOVDQU16Z128mrk:
23617 case VMOVDQU16Z128rm:
23618 case VMOVDQU16Z128rmk:
23619 case VMOVDQU16Z128rmkz:
23620 case VMOVDQU16Z128rr:
23621 case VMOVDQU16Z128rr_REV:
23622 case VMOVDQU16Z128rrk:
23623 case VMOVDQU16Z128rrk_REV:
23624 case VMOVDQU16Z128rrkz:
23625 case VMOVDQU16Z128rrkz_REV:
23626 case VMOVDQU16Z256mr:
23627 case VMOVDQU16Z256mrk:
23628 case VMOVDQU16Z256rm:
23629 case VMOVDQU16Z256rmk:
23630 case VMOVDQU16Z256rmkz:
23631 case VMOVDQU16Z256rr:
23632 case VMOVDQU16Z256rr_REV:
23633 case VMOVDQU16Z256rrk:
23634 case VMOVDQU16Z256rrk_REV:
23635 case VMOVDQU16Z256rrkz:
23636 case VMOVDQU16Z256rrkz_REV:
23637 case VMOVDQU16Zmr:
23638 case VMOVDQU16Zmrk:
23639 case VMOVDQU16Zrm:
23640 case VMOVDQU16Zrmk:
23641 case VMOVDQU16Zrmkz:
23642 case VMOVDQU16Zrr:
23643 case VMOVDQU16Zrr_REV:
23644 case VMOVDQU16Zrrk:
23645 case VMOVDQU16Zrrk_REV:
23646 case VMOVDQU16Zrrkz:
23647 case VMOVDQU16Zrrkz_REV:
23648 return true;
23649 }
23650 return false;
23651}
23652
23653bool isVFMADD132PH(unsigned Opcode) {
23654 switch (Opcode) {
23655 case VFMADD132PHZ128m:
23656 case VFMADD132PHZ128mb:
23657 case VFMADD132PHZ128mbk:
23658 case VFMADD132PHZ128mbkz:
23659 case VFMADD132PHZ128mk:
23660 case VFMADD132PHZ128mkz:
23661 case VFMADD132PHZ128r:
23662 case VFMADD132PHZ128rk:
23663 case VFMADD132PHZ128rkz:
23664 case VFMADD132PHZ256m:
23665 case VFMADD132PHZ256mb:
23666 case VFMADD132PHZ256mbk:
23667 case VFMADD132PHZ256mbkz:
23668 case VFMADD132PHZ256mk:
23669 case VFMADD132PHZ256mkz:
23670 case VFMADD132PHZ256r:
23671 case VFMADD132PHZ256rk:
23672 case VFMADD132PHZ256rkz:
23673 case VFMADD132PHZm:
23674 case VFMADD132PHZmb:
23675 case VFMADD132PHZmbk:
23676 case VFMADD132PHZmbkz:
23677 case VFMADD132PHZmk:
23678 case VFMADD132PHZmkz:
23679 case VFMADD132PHZr:
23680 case VFMADD132PHZrb:
23681 case VFMADD132PHZrbk:
23682 case VFMADD132PHZrbkz:
23683 case VFMADD132PHZrk:
23684 case VFMADD132PHZrkz:
23685 return true;
23686 }
23687 return false;
23688}
23689
23690bool isVFMSUBADD213PS(unsigned Opcode) {
23691 switch (Opcode) {
23692 case VFMSUBADD213PSYm:
23693 case VFMSUBADD213PSYr:
23694 case VFMSUBADD213PSZ128m:
23695 case VFMSUBADD213PSZ128mb:
23696 case VFMSUBADD213PSZ128mbk:
23697 case VFMSUBADD213PSZ128mbkz:
23698 case VFMSUBADD213PSZ128mk:
23699 case VFMSUBADD213PSZ128mkz:
23700 case VFMSUBADD213PSZ128r:
23701 case VFMSUBADD213PSZ128rk:
23702 case VFMSUBADD213PSZ128rkz:
23703 case VFMSUBADD213PSZ256m:
23704 case VFMSUBADD213PSZ256mb:
23705 case VFMSUBADD213PSZ256mbk:
23706 case VFMSUBADD213PSZ256mbkz:
23707 case VFMSUBADD213PSZ256mk:
23708 case VFMSUBADD213PSZ256mkz:
23709 case VFMSUBADD213PSZ256r:
23710 case VFMSUBADD213PSZ256rk:
23711 case VFMSUBADD213PSZ256rkz:
23712 case VFMSUBADD213PSZm:
23713 case VFMSUBADD213PSZmb:
23714 case VFMSUBADD213PSZmbk:
23715 case VFMSUBADD213PSZmbkz:
23716 case VFMSUBADD213PSZmk:
23717 case VFMSUBADD213PSZmkz:
23718 case VFMSUBADD213PSZr:
23719 case VFMSUBADD213PSZrb:
23720 case VFMSUBADD213PSZrbk:
23721 case VFMSUBADD213PSZrbkz:
23722 case VFMSUBADD213PSZrk:
23723 case VFMSUBADD213PSZrkz:
23724 case VFMSUBADD213PSm:
23725 case VFMSUBADD213PSr:
23726 return true;
23727 }
23728 return false;
23729}
23730
23731bool isVMOVDQU32(unsigned Opcode) {
23732 switch (Opcode) {
23733 case VMOVDQU32Z128mr:
23734 case VMOVDQU32Z128mrk:
23735 case VMOVDQU32Z128rm:
23736 case VMOVDQU32Z128rmk:
23737 case VMOVDQU32Z128rmkz:
23738 case VMOVDQU32Z128rr:
23739 case VMOVDQU32Z128rr_REV:
23740 case VMOVDQU32Z128rrk:
23741 case VMOVDQU32Z128rrk_REV:
23742 case VMOVDQU32Z128rrkz:
23743 case VMOVDQU32Z128rrkz_REV:
23744 case VMOVDQU32Z256mr:
23745 case VMOVDQU32Z256mrk:
23746 case VMOVDQU32Z256rm:
23747 case VMOVDQU32Z256rmk:
23748 case VMOVDQU32Z256rmkz:
23749 case VMOVDQU32Z256rr:
23750 case VMOVDQU32Z256rr_REV:
23751 case VMOVDQU32Z256rrk:
23752 case VMOVDQU32Z256rrk_REV:
23753 case VMOVDQU32Z256rrkz:
23754 case VMOVDQU32Z256rrkz_REV:
23755 case VMOVDQU32Zmr:
23756 case VMOVDQU32Zmrk:
23757 case VMOVDQU32Zrm:
23758 case VMOVDQU32Zrmk:
23759 case VMOVDQU32Zrmkz:
23760 case VMOVDQU32Zrr:
23761 case VMOVDQU32Zrr_REV:
23762 case VMOVDQU32Zrrk:
23763 case VMOVDQU32Zrrk_REV:
23764 case VMOVDQU32Zrrkz:
23765 case VMOVDQU32Zrrkz_REV:
23766 return true;
23767 }
23768 return false;
23769}
23770
23771bool isFUCOM(unsigned Opcode) {
23772 return Opcode == UCOM_Fr;
23773}
23774
23775bool isHADDPS(unsigned Opcode) {
23776 switch (Opcode) {
23777 case HADDPSrm:
23778 case HADDPSrr:
23779 return true;
23780 }
23781 return false;
23782}
23783
23784bool isCMP(unsigned Opcode) {
23785 switch (Opcode) {
23786 case CMP16i16:
23787 case CMP16mi:
23788 case CMP16mi8:
23789 case CMP16mr:
23790 case CMP16ri:
23791 case CMP16ri8:
23792 case CMP16rm:
23793 case CMP16rr:
23794 case CMP16rr_REV:
23795 case CMP32i32:
23796 case CMP32mi:
23797 case CMP32mi8:
23798 case CMP32mr:
23799 case CMP32ri:
23800 case CMP32ri8:
23801 case CMP32rm:
23802 case CMP32rr:
23803 case CMP32rr_REV:
23804 case CMP64i32:
23805 case CMP64mi32:
23806 case CMP64mi8:
23807 case CMP64mr:
23808 case CMP64ri32:
23809 case CMP64ri8:
23810 case CMP64rm:
23811 case CMP64rr:
23812 case CMP64rr_REV:
23813 case CMP8i8:
23814 case CMP8mi:
23815 case CMP8mi8:
23816 case CMP8mr:
23817 case CMP8ri:
23818 case CMP8ri8:
23819 case CMP8rm:
23820 case CMP8rr:
23821 case CMP8rr_REV:
23822 return true;
23823 }
23824 return false;
23825}
23826
23827bool isCVTTPS2PI(unsigned Opcode) {
23828 switch (Opcode) {
23829 case MMX_CVTTPS2PIrm:
23830 case MMX_CVTTPS2PIrr:
23831 return true;
23832 }
23833 return false;
23834}
23835
23836bool isIRETQ(unsigned Opcode) {
23837 return Opcode == IRET64;
23838}
23839
23840bool isPF2IW(unsigned Opcode) {
23841 switch (Opcode) {
23842 case PF2IWrm:
23843 case PF2IWrr:
23844 return true;
23845 }
23846 return false;
23847}
23848
23849bool isPSHUFD(unsigned Opcode) {
23850 switch (Opcode) {
23851 case PSHUFDmi:
23852 case PSHUFDri:
23853 return true;
23854 }
23855 return false;
23856}
23857
23858bool isVDPPD(unsigned Opcode) {
23859 switch (Opcode) {
23860 case VDPPDrmi:
23861 case VDPPDrri:
23862 return true;
23863 }
23864 return false;
23865}
23866
23867bool isPSHUFHW(unsigned Opcode) {
23868 switch (Opcode) {
23869 case PSHUFHWmi:
23870 case PSHUFHWri:
23871 return true;
23872 }
23873 return false;
23874}
23875
23876bool isRMPADJUST(unsigned Opcode) {
23877 return Opcode == RMPADJUST;
23878}
23879
23880bool isPI2FW(unsigned Opcode) {
23881 switch (Opcode) {
23882 case PI2FWrm:
23883 case PI2FWrr:
23884 return true;
23885 }
23886 return false;
23887}
23888
23889bool isVCVTTPH2QQ(unsigned Opcode) {
23890 switch (Opcode) {
23891 case VCVTTPH2QQZ128rm:
23892 case VCVTTPH2QQZ128rmb:
23893 case VCVTTPH2QQZ128rmbk:
23894 case VCVTTPH2QQZ128rmbkz:
23895 case VCVTTPH2QQZ128rmk:
23896 case VCVTTPH2QQZ128rmkz:
23897 case VCVTTPH2QQZ128rr:
23898 case VCVTTPH2QQZ128rrk:
23899 case VCVTTPH2QQZ128rrkz:
23900 case VCVTTPH2QQZ256rm:
23901 case VCVTTPH2QQZ256rmb:
23902 case VCVTTPH2QQZ256rmbk:
23903 case VCVTTPH2QQZ256rmbkz:
23904 case VCVTTPH2QQZ256rmk:
23905 case VCVTTPH2QQZ256rmkz:
23906 case VCVTTPH2QQZ256rr:
23907 case VCVTTPH2QQZ256rrk:
23908 case VCVTTPH2QQZ256rrkz:
23909 case VCVTTPH2QQZrm:
23910 case VCVTTPH2QQZrmb:
23911 case VCVTTPH2QQZrmbk:
23912 case VCVTTPH2QQZrmbkz:
23913 case VCVTTPH2QQZrmk:
23914 case VCVTTPH2QQZrmkz:
23915 case VCVTTPH2QQZrr:
23916 case VCVTTPH2QQZrrb:
23917 case VCVTTPH2QQZrrbk:
23918 case VCVTTPH2QQZrrbkz:
23919 case VCVTTPH2QQZrrk:
23920 case VCVTTPH2QQZrrkz:
23921 return true;
23922 }
23923 return false;
23924}
23925
23926bool isDIVPD(unsigned Opcode) {
23927 switch (Opcode) {
23928 case DIVPDrm:
23929 case DIVPDrr:
23930 return true;
23931 }
23932 return false;
23933}
23934
23935bool isCLFLUSH(unsigned Opcode) {
23936 return Opcode == CLFLUSH;
23937}
23938
23939bool isVPMINUW(unsigned Opcode) {
23940 switch (Opcode) {
23941 case VPMINUWYrm:
23942 case VPMINUWYrr:
23943 case VPMINUWZ128rm:
23944 case VPMINUWZ128rmk:
23945 case VPMINUWZ128rmkz:
23946 case VPMINUWZ128rr:
23947 case VPMINUWZ128rrk:
23948 case VPMINUWZ128rrkz:
23949 case VPMINUWZ256rm:
23950 case VPMINUWZ256rmk:
23951 case VPMINUWZ256rmkz:
23952 case VPMINUWZ256rr:
23953 case VPMINUWZ256rrk:
23954 case VPMINUWZ256rrkz:
23955 case VPMINUWZrm:
23956 case VPMINUWZrmk:
23957 case VPMINUWZrmkz:
23958 case VPMINUWZrr:
23959 case VPMINUWZrrk:
23960 case VPMINUWZrrkz:
23961 case VPMINUWrm:
23962 case VPMINUWrr:
23963 return true;
23964 }
23965 return false;
23966}
23967
23968bool isIN(unsigned Opcode) {
23969 switch (Opcode) {
23970 case IN16ri:
23971 case IN16rr:
23972 case IN32ri:
23973 case IN32rr:
23974 case IN8ri:
23975 case IN8rr:
23976 return true;
23977 }
23978 return false;
23979}
23980
23981bool isWRPKRU(unsigned Opcode) {
23982 return Opcode == WRPKRUr;
23983}
23984
23985bool isINSERTPS(unsigned Opcode) {
23986 switch (Opcode) {
23987 case INSERTPSrm:
23988 case INSERTPSrr:
23989 return true;
23990 }
23991 return false;
23992}
23993
23994bool isAAM(unsigned Opcode) {
23995 return Opcode == AAM8i8;
23996}
23997
23998bool isVPHADDUDQ(unsigned Opcode) {
23999 switch (Opcode) {
24000 case VPHADDUDQrm:
24001 case VPHADDUDQrr:
24002 return true;
24003 }
24004 return false;
24005}
24006
24007bool isVSHA512MSG1(unsigned Opcode) {
24008 return Opcode == VSHA512MSG1rr;
24009}
24010
24011bool isDIVPS(unsigned Opcode) {
24012 switch (Opcode) {
24013 case DIVPSrm:
24014 case DIVPSrr:
24015 return true;
24016 }
24017 return false;
24018}
24019
24020bool isKNOTB(unsigned Opcode) {
24021 return Opcode == KNOTBrr;
24022}
24023
24024bool isBLSFILL(unsigned Opcode) {
24025 switch (Opcode) {
24026 case BLSFILL32rm:
24027 case BLSFILL32rr:
24028 case BLSFILL64rm:
24029 case BLSFILL64rr:
24030 return true;
24031 }
24032 return false;
24033}
24034
24035bool isVPCMPGTQ(unsigned Opcode) {
24036 switch (Opcode) {
24037 case VPCMPGTQYrm:
24038 case VPCMPGTQYrr:
24039 case VPCMPGTQZ128rm:
24040 case VPCMPGTQZ128rmb:
24041 case VPCMPGTQZ128rmbk:
24042 case VPCMPGTQZ128rmk:
24043 case VPCMPGTQZ128rr:
24044 case VPCMPGTQZ128rrk:
24045 case VPCMPGTQZ256rm:
24046 case VPCMPGTQZ256rmb:
24047 case VPCMPGTQZ256rmbk:
24048 case VPCMPGTQZ256rmk:
24049 case VPCMPGTQZ256rr:
24050 case VPCMPGTQZ256rrk:
24051 case VPCMPGTQZrm:
24052 case VPCMPGTQZrmb:
24053 case VPCMPGTQZrmbk:
24054 case VPCMPGTQZrmk:
24055 case VPCMPGTQZrr:
24056 case VPCMPGTQZrrk:
24057 case VPCMPGTQrm:
24058 case VPCMPGTQrr:
24059 return true;
24060 }
24061 return false;
24062}
24063
24064bool isMINSD(unsigned Opcode) {
24065 switch (Opcode) {
24066 case MINSDrm_Int:
24067 case MINSDrr_Int:
24068 return true;
24069 }
24070 return false;
24071}
24072
24073bool isFPREM(unsigned Opcode) {
24074 return Opcode == FPREM;
24075}
24076
24077bool isVPUNPCKHQDQ(unsigned Opcode) {
24078 switch (Opcode) {
24079 case VPUNPCKHQDQYrm:
24080 case VPUNPCKHQDQYrr:
24081 case VPUNPCKHQDQZ128rm:
24082 case VPUNPCKHQDQZ128rmb:
24083 case VPUNPCKHQDQZ128rmbk:
24084 case VPUNPCKHQDQZ128rmbkz:
24085 case VPUNPCKHQDQZ128rmk:
24086 case VPUNPCKHQDQZ128rmkz:
24087 case VPUNPCKHQDQZ128rr:
24088 case VPUNPCKHQDQZ128rrk:
24089 case VPUNPCKHQDQZ128rrkz:
24090 case VPUNPCKHQDQZ256rm:
24091 case VPUNPCKHQDQZ256rmb:
24092 case VPUNPCKHQDQZ256rmbk:
24093 case VPUNPCKHQDQZ256rmbkz:
24094 case VPUNPCKHQDQZ256rmk:
24095 case VPUNPCKHQDQZ256rmkz:
24096 case VPUNPCKHQDQZ256rr:
24097 case VPUNPCKHQDQZ256rrk:
24098 case VPUNPCKHQDQZ256rrkz:
24099 case VPUNPCKHQDQZrm:
24100 case VPUNPCKHQDQZrmb:
24101 case VPUNPCKHQDQZrmbk:
24102 case VPUNPCKHQDQZrmbkz:
24103 case VPUNPCKHQDQZrmk:
24104 case VPUNPCKHQDQZrmkz:
24105 case VPUNPCKHQDQZrr:
24106 case VPUNPCKHQDQZrrk:
24107 case VPUNPCKHQDQZrrkz:
24108 case VPUNPCKHQDQrm:
24109 case VPUNPCKHQDQrr:
24110 return true;
24111 }
24112 return false;
24113}
24114
24115bool isMINPD(unsigned Opcode) {
24116 switch (Opcode) {
24117 case MINPDrm:
24118 case MINPDrr:
24119 return true;
24120 }
24121 return false;
24122}
24123
24124bool isVCVTTPD2QQ(unsigned Opcode) {
24125 switch (Opcode) {
24126 case VCVTTPD2QQZ128rm:
24127 case VCVTTPD2QQZ128rmb:
24128 case VCVTTPD2QQZ128rmbk:
24129 case VCVTTPD2QQZ128rmbkz:
24130 case VCVTTPD2QQZ128rmk:
24131 case VCVTTPD2QQZ128rmkz:
24132 case VCVTTPD2QQZ128rr:
24133 case VCVTTPD2QQZ128rrk:
24134 case VCVTTPD2QQZ128rrkz:
24135 case VCVTTPD2QQZ256rm:
24136 case VCVTTPD2QQZ256rmb:
24137 case VCVTTPD2QQZ256rmbk:
24138 case VCVTTPD2QQZ256rmbkz:
24139 case VCVTTPD2QQZ256rmk:
24140 case VCVTTPD2QQZ256rmkz:
24141 case VCVTTPD2QQZ256rr:
24142 case VCVTTPD2QQZ256rrk:
24143 case VCVTTPD2QQZ256rrkz:
24144 case VCVTTPD2QQZrm:
24145 case VCVTTPD2QQZrmb:
24146 case VCVTTPD2QQZrmbk:
24147 case VCVTTPD2QQZrmbkz:
24148 case VCVTTPD2QQZrmk:
24149 case VCVTTPD2QQZrmkz:
24150 case VCVTTPD2QQZrr:
24151 case VCVTTPD2QQZrrb:
24152 case VCVTTPD2QQZrrbk:
24153 case VCVTTPD2QQZrrbkz:
24154 case VCVTTPD2QQZrrk:
24155 case VCVTTPD2QQZrrkz:
24156 return true;
24157 }
24158 return false;
24159}
24160
24161bool isVFMSUBPD(unsigned Opcode) {
24162 switch (Opcode) {
24163 case VFMSUBPD4Ymr:
24164 case VFMSUBPD4Yrm:
24165 case VFMSUBPD4Yrr:
24166 case VFMSUBPD4Yrr_REV:
24167 case VFMSUBPD4mr:
24168 case VFMSUBPD4rm:
24169 case VFMSUBPD4rr:
24170 case VFMSUBPD4rr_REV:
24171 return true;
24172 }
24173 return false;
24174}
24175
24176bool isV4FMADDSS(unsigned Opcode) {
24177 switch (Opcode) {
24178 case V4FMADDSSrm:
24179 case V4FMADDSSrmk:
24180 case V4FMADDSSrmkz:
24181 return true;
24182 }
24183 return false;
24184}
24185
24186bool isCPUID(unsigned Opcode) {
24187 return Opcode == CPUID;
24188}
24189
24190bool isSETCC(unsigned Opcode) {
24191 switch (Opcode) {
24192 case SETCCm:
24193 case SETCCm_EVEX:
24194 case SETCCr:
24195 case SETCCr_EVEX:
24196 return true;
24197 }
24198 return false;
24199}
24200
24201bool isVPDPWUUD(unsigned Opcode) {
24202 switch (Opcode) {
24203 case VPDPWUUDYrm:
24204 case VPDPWUUDYrr:
24205 case VPDPWUUDrm:
24206 case VPDPWUUDrr:
24207 return true;
24208 }
24209 return false;
24210}
24211
24212bool isPMOVSXDQ(unsigned Opcode) {
24213 switch (Opcode) {
24214 case PMOVSXDQrm:
24215 case PMOVSXDQrr:
24216 return true;
24217 }
24218 return false;
24219}
24220
24221bool isMWAIT(unsigned Opcode) {
24222 return Opcode == MWAITrr;
24223}
24224
24225bool isVPEXTRB(unsigned Opcode) {
24226 switch (Opcode) {
24227 case VPEXTRBZmr:
24228 case VPEXTRBZrr:
24229 case VPEXTRBmr:
24230 case VPEXTRBrr:
24231 return true;
24232 }
24233 return false;
24234}
24235
24236bool isINVVPID(unsigned Opcode) {
24237 switch (Opcode) {
24238 case INVVPID32:
24239 case INVVPID64:
24240 case INVVPID64_EVEX:
24241 return true;
24242 }
24243 return false;
24244}
24245
24246bool isVPSHUFD(unsigned Opcode) {
24247 switch (Opcode) {
24248 case VPSHUFDYmi:
24249 case VPSHUFDYri:
24250 case VPSHUFDZ128mbi:
24251 case VPSHUFDZ128mbik:
24252 case VPSHUFDZ128mbikz:
24253 case VPSHUFDZ128mi:
24254 case VPSHUFDZ128mik:
24255 case VPSHUFDZ128mikz:
24256 case VPSHUFDZ128ri:
24257 case VPSHUFDZ128rik:
24258 case VPSHUFDZ128rikz:
24259 case VPSHUFDZ256mbi:
24260 case VPSHUFDZ256mbik:
24261 case VPSHUFDZ256mbikz:
24262 case VPSHUFDZ256mi:
24263 case VPSHUFDZ256mik:
24264 case VPSHUFDZ256mikz:
24265 case VPSHUFDZ256ri:
24266 case VPSHUFDZ256rik:
24267 case VPSHUFDZ256rikz:
24268 case VPSHUFDZmbi:
24269 case VPSHUFDZmbik:
24270 case VPSHUFDZmbikz:
24271 case VPSHUFDZmi:
24272 case VPSHUFDZmik:
24273 case VPSHUFDZmikz:
24274 case VPSHUFDZri:
24275 case VPSHUFDZrik:
24276 case VPSHUFDZrikz:
24277 case VPSHUFDmi:
24278 case VPSHUFDri:
24279 return true;
24280 }
24281 return false;
24282}
24283
24284bool isMOVLPS(unsigned Opcode) {
24285 switch (Opcode) {
24286 case MOVLPSmr:
24287 case MOVLPSrm:
24288 return true;
24289 }
24290 return false;
24291}
24292
24293bool isVBLENDMPS(unsigned Opcode) {
24294 switch (Opcode) {
24295 case VBLENDMPSZ128rm:
24296 case VBLENDMPSZ128rmb:
24297 case VBLENDMPSZ128rmbk:
24298 case VBLENDMPSZ128rmbkz:
24299 case VBLENDMPSZ128rmk:
24300 case VBLENDMPSZ128rmkz:
24301 case VBLENDMPSZ128rr:
24302 case VBLENDMPSZ128rrk:
24303 case VBLENDMPSZ128rrkz:
24304 case VBLENDMPSZ256rm:
24305 case VBLENDMPSZ256rmb:
24306 case VBLENDMPSZ256rmbk:
24307 case VBLENDMPSZ256rmbkz:
24308 case VBLENDMPSZ256rmk:
24309 case VBLENDMPSZ256rmkz:
24310 case VBLENDMPSZ256rr:
24311 case VBLENDMPSZ256rrk:
24312 case VBLENDMPSZ256rrkz:
24313 case VBLENDMPSZrm:
24314 case VBLENDMPSZrmb:
24315 case VBLENDMPSZrmbk:
24316 case VBLENDMPSZrmbkz:
24317 case VBLENDMPSZrmk:
24318 case VBLENDMPSZrmkz:
24319 case VBLENDMPSZrr:
24320 case VBLENDMPSZrrk:
24321 case VBLENDMPSZrrkz:
24322 return true;
24323 }
24324 return false;
24325}
24326
24327bool isPMULLW(unsigned Opcode) {
24328 switch (Opcode) {
24329 case MMX_PMULLWrm:
24330 case MMX_PMULLWrr:
24331 case PMULLWrm:
24332 case PMULLWrr:
24333 return true;
24334 }
24335 return false;
24336}
24337
24338bool isVCVTSH2SI(unsigned Opcode) {
24339 switch (Opcode) {
24340 case VCVTSH2SI64Zrm_Int:
24341 case VCVTSH2SI64Zrr_Int:
24342 case VCVTSH2SI64Zrrb_Int:
24343 case VCVTSH2SIZrm_Int:
24344 case VCVTSH2SIZrr_Int:
24345 case VCVTSH2SIZrrb_Int:
24346 return true;
24347 }
24348 return false;
24349}
24350
24351bool isVPMOVSXWQ(unsigned Opcode) {
24352 switch (Opcode) {
24353 case VPMOVSXWQYrm:
24354 case VPMOVSXWQYrr:
24355 case VPMOVSXWQZ128rm:
24356 case VPMOVSXWQZ128rmk:
24357 case VPMOVSXWQZ128rmkz:
24358 case VPMOVSXWQZ128rr:
24359 case VPMOVSXWQZ128rrk:
24360 case VPMOVSXWQZ128rrkz:
24361 case VPMOVSXWQZ256rm:
24362 case VPMOVSXWQZ256rmk:
24363 case VPMOVSXWQZ256rmkz:
24364 case VPMOVSXWQZ256rr:
24365 case VPMOVSXWQZ256rrk:
24366 case VPMOVSXWQZ256rrkz:
24367 case VPMOVSXWQZrm:
24368 case VPMOVSXWQZrmk:
24369 case VPMOVSXWQZrmkz:
24370 case VPMOVSXWQZrr:
24371 case VPMOVSXWQZrrk:
24372 case VPMOVSXWQZrrkz:
24373 case VPMOVSXWQrm:
24374 case VPMOVSXWQrr:
24375 return true;
24376 }
24377 return false;
24378}
24379
24380bool isFNSTENV(unsigned Opcode) {
24381 return Opcode == FSTENVm;
24382}
24383
24384bool isVPERMI2PD(unsigned Opcode) {
24385 switch (Opcode) {
24386 case VPERMI2PDZ128rm:
24387 case VPERMI2PDZ128rmb:
24388 case VPERMI2PDZ128rmbk:
24389 case VPERMI2PDZ128rmbkz:
24390 case VPERMI2PDZ128rmk:
24391 case VPERMI2PDZ128rmkz:
24392 case VPERMI2PDZ128rr:
24393 case VPERMI2PDZ128rrk:
24394 case VPERMI2PDZ128rrkz:
24395 case VPERMI2PDZ256rm:
24396 case VPERMI2PDZ256rmb:
24397 case VPERMI2PDZ256rmbk:
24398 case VPERMI2PDZ256rmbkz:
24399 case VPERMI2PDZ256rmk:
24400 case VPERMI2PDZ256rmkz:
24401 case VPERMI2PDZ256rr:
24402 case VPERMI2PDZ256rrk:
24403 case VPERMI2PDZ256rrkz:
24404 case VPERMI2PDZrm:
24405 case VPERMI2PDZrmb:
24406 case VPERMI2PDZrmbk:
24407 case VPERMI2PDZrmbkz:
24408 case VPERMI2PDZrmk:
24409 case VPERMI2PDZrmkz:
24410 case VPERMI2PDZrr:
24411 case VPERMI2PDZrrk:
24412 case VPERMI2PDZrrkz:
24413 return true;
24414 }
24415 return false;
24416}
24417
24418bool isMAXSS(unsigned Opcode) {
24419 switch (Opcode) {
24420 case MAXSSrm_Int:
24421 case MAXSSrr_Int:
24422 return true;
24423 }
24424 return false;
24425}
24426
24427bool isCWDE(unsigned Opcode) {
24428 return Opcode == CWDE;
24429}
24430
24431bool isVBROADCASTI32X8(unsigned Opcode) {
24432 switch (Opcode) {
24433 case VBROADCASTI32X8rm:
24434 case VBROADCASTI32X8rmk:
24435 case VBROADCASTI32X8rmkz:
24436 return true;
24437 }
24438 return false;
24439}
24440
24441bool isINT(unsigned Opcode) {
24442 return Opcode == INT;
24443}
24444
24445bool isENCLS(unsigned Opcode) {
24446 return Opcode == ENCLS;
24447}
24448
24449bool isMOVNTQ(unsigned Opcode) {
24450 return Opcode == MMX_MOVNTQmr;
24451}
24452
24453bool isVDIVSH(unsigned Opcode) {
24454 switch (Opcode) {
24455 case VDIVSHZrm_Int:
24456 case VDIVSHZrm_Intk:
24457 case VDIVSHZrm_Intkz:
24458 case VDIVSHZrr_Int:
24459 case VDIVSHZrr_Intk:
24460 case VDIVSHZrr_Intkz:
24461 case VDIVSHZrrb_Int:
24462 case VDIVSHZrrb_Intk:
24463 case VDIVSHZrrb_Intkz:
24464 return true;
24465 }
24466 return false;
24467}
24468
24469bool isMOVHLPS(unsigned Opcode) {
24470 return Opcode == MOVHLPSrr;
24471}
24472
24473bool isVPMASKMOVD(unsigned Opcode) {
24474 switch (Opcode) {
24475 case VPMASKMOVDYmr:
24476 case VPMASKMOVDYrm:
24477 case VPMASKMOVDmr:
24478 case VPMASKMOVDrm:
24479 return true;
24480 }
24481 return false;
24482}
24483
24484bool isVMOVSD(unsigned Opcode) {
24485 switch (Opcode) {
24486 case VMOVSDZmr:
24487 case VMOVSDZmrk:
24488 case VMOVSDZrm:
24489 case VMOVSDZrmk:
24490 case VMOVSDZrmkz:
24491 case VMOVSDZrr:
24492 case VMOVSDZrr_REV:
24493 case VMOVSDZrrk:
24494 case VMOVSDZrrk_REV:
24495 case VMOVSDZrrkz:
24496 case VMOVSDZrrkz_REV:
24497 case VMOVSDmr:
24498 case VMOVSDrm:
24499 case VMOVSDrr:
24500 case VMOVSDrr_REV:
24501 return true;
24502 }
24503 return false;
24504}
24505
24506bool isVPMINUD(unsigned Opcode) {
24507 switch (Opcode) {
24508 case VPMINUDYrm:
24509 case VPMINUDYrr:
24510 case VPMINUDZ128rm:
24511 case VPMINUDZ128rmb:
24512 case VPMINUDZ128rmbk:
24513 case VPMINUDZ128rmbkz:
24514 case VPMINUDZ128rmk:
24515 case VPMINUDZ128rmkz:
24516 case VPMINUDZ128rr:
24517 case VPMINUDZ128rrk:
24518 case VPMINUDZ128rrkz:
24519 case VPMINUDZ256rm:
24520 case VPMINUDZ256rmb:
24521 case VPMINUDZ256rmbk:
24522 case VPMINUDZ256rmbkz:
24523 case VPMINUDZ256rmk:
24524 case VPMINUDZ256rmkz:
24525 case VPMINUDZ256rr:
24526 case VPMINUDZ256rrk:
24527 case VPMINUDZ256rrkz:
24528 case VPMINUDZrm:
24529 case VPMINUDZrmb:
24530 case VPMINUDZrmbk:
24531 case VPMINUDZrmbkz:
24532 case VPMINUDZrmk:
24533 case VPMINUDZrmkz:
24534 case VPMINUDZrr:
24535 case VPMINUDZrrk:
24536 case VPMINUDZrrkz:
24537 case VPMINUDrm:
24538 case VPMINUDrr:
24539 return true;
24540 }
24541 return false;
24542}
24543
24544bool isVPCMPISTRM(unsigned Opcode) {
24545 switch (Opcode) {
24546 case VPCMPISTRMrmi:
24547 case VPCMPISTRMrri:
24548 return true;
24549 }
24550 return false;
24551}
24552
24553bool isVGETMANTSD(unsigned Opcode) {
24554 switch (Opcode) {
24555 case VGETMANTSDZrmi:
24556 case VGETMANTSDZrmik:
24557 case VGETMANTSDZrmikz:
24558 case VGETMANTSDZrri:
24559 case VGETMANTSDZrrib:
24560 case VGETMANTSDZrribk:
24561 case VGETMANTSDZrribkz:
24562 case VGETMANTSDZrrik:
24563 case VGETMANTSDZrrikz:
24564 return true;
24565 }
24566 return false;
24567}
24568
24569bool isKSHIFTRW(unsigned Opcode) {
24570 return Opcode == KSHIFTRWri;
24571}
24572
24573bool isAESDECLAST(unsigned Opcode) {
24574 switch (Opcode) {
24575 case AESDECLASTrm:
24576 case AESDECLASTrr:
24577 return true;
24578 }
24579 return false;
24580}
24581
24582bool isVPTESTMB(unsigned Opcode) {
24583 switch (Opcode) {
24584 case VPTESTMBZ128rm:
24585 case VPTESTMBZ128rmk:
24586 case VPTESTMBZ128rr:
24587 case VPTESTMBZ128rrk:
24588 case VPTESTMBZ256rm:
24589 case VPTESTMBZ256rmk:
24590 case VPTESTMBZ256rr:
24591 case VPTESTMBZ256rrk:
24592 case VPTESTMBZrm:
24593 case VPTESTMBZrmk:
24594 case VPTESTMBZrr:
24595 case VPTESTMBZrrk:
24596 return true;
24597 }
24598 return false;
24599}
24600
24601bool isVMPTRST(unsigned Opcode) {
24602 return Opcode == VMPTRSTm;
24603}
24604
24605bool isLLDT(unsigned Opcode) {
24606 switch (Opcode) {
24607 case LLDT16m:
24608 case LLDT16r:
24609 return true;
24610 }
24611 return false;
24612}
24613
24614bool isMOVSB(unsigned Opcode) {
24615 return Opcode == MOVSB;
24616}
24617
24618bool isTILELOADD(unsigned Opcode) {
24619 switch (Opcode) {
24620 case TILELOADD:
24621 case TILELOADD_EVEX:
24622 return true;
24623 }
24624 return false;
24625}
24626
24627bool isKTESTB(unsigned Opcode) {
24628 return Opcode == KTESTBrr;
24629}
24630
24631bool isMOVUPD(unsigned Opcode) {
24632 switch (Opcode) {
24633 case MOVUPDmr:
24634 case MOVUPDrm:
24635 case MOVUPDrr:
24636 case MOVUPDrr_REV:
24637 return true;
24638 }
24639 return false;
24640}
24641
24642bool isLKGS(unsigned Opcode) {
24643 switch (Opcode) {
24644 case LKGS16m:
24645 case LKGS16r:
24646 return true;
24647 }
24648 return false;
24649}
24650
24651bool isSGDTW(unsigned Opcode) {
24652 return Opcode == SGDT16m;
24653}
24654
24655bool isDIVSS(unsigned Opcode) {
24656 switch (Opcode) {
24657 case DIVSSrm_Int:
24658 case DIVSSrr_Int:
24659 return true;
24660 }
24661 return false;
24662}
24663
24664bool isPUNPCKHQDQ(unsigned Opcode) {
24665 switch (Opcode) {
24666 case PUNPCKHQDQrm:
24667 case PUNPCKHQDQrr:
24668 return true;
24669 }
24670 return false;
24671}
24672
24673bool isVFMADD213SD(unsigned Opcode) {
24674 switch (Opcode) {
24675 case VFMADD213SDZm_Int:
24676 case VFMADD213SDZm_Intk:
24677 case VFMADD213SDZm_Intkz:
24678 case VFMADD213SDZr_Int:
24679 case VFMADD213SDZr_Intk:
24680 case VFMADD213SDZr_Intkz:
24681 case VFMADD213SDZrb_Int:
24682 case VFMADD213SDZrb_Intk:
24683 case VFMADD213SDZrb_Intkz:
24684 case VFMADD213SDm_Int:
24685 case VFMADD213SDr_Int:
24686 return true;
24687 }
24688 return false;
24689}
24690
24691bool isKXORD(unsigned Opcode) {
24692 return Opcode == KXORDrr;
24693}
24694
24695bool isVPMOVB2M(unsigned Opcode) {
24696 switch (Opcode) {
24697 case VPMOVB2MZ128rr:
24698 case VPMOVB2MZ256rr:
24699 case VPMOVB2MZrr:
24700 return true;
24701 }
24702 return false;
24703}
24704
24705bool isVMREAD(unsigned Opcode) {
24706 switch (Opcode) {
24707 case VMREAD32mr:
24708 case VMREAD32rr:
24709 case VMREAD64mr:
24710 case VMREAD64rr:
24711 return true;
24712 }
24713 return false;
24714}
24715
24716bool isVPDPWSSDS(unsigned Opcode) {
24717 switch (Opcode) {
24718 case VPDPWSSDSYrm:
24719 case VPDPWSSDSYrr:
24720 case VPDPWSSDSZ128m:
24721 case VPDPWSSDSZ128mb:
24722 case VPDPWSSDSZ128mbk:
24723 case VPDPWSSDSZ128mbkz:
24724 case VPDPWSSDSZ128mk:
24725 case VPDPWSSDSZ128mkz:
24726 case VPDPWSSDSZ128r:
24727 case VPDPWSSDSZ128rk:
24728 case VPDPWSSDSZ128rkz:
24729 case VPDPWSSDSZ256m:
24730 case VPDPWSSDSZ256mb:
24731 case VPDPWSSDSZ256mbk:
24732 case VPDPWSSDSZ256mbkz:
24733 case VPDPWSSDSZ256mk:
24734 case VPDPWSSDSZ256mkz:
24735 case VPDPWSSDSZ256r:
24736 case VPDPWSSDSZ256rk:
24737 case VPDPWSSDSZ256rkz:
24738 case VPDPWSSDSZm:
24739 case VPDPWSSDSZmb:
24740 case VPDPWSSDSZmbk:
24741 case VPDPWSSDSZmbkz:
24742 case VPDPWSSDSZmk:
24743 case VPDPWSSDSZmkz:
24744 case VPDPWSSDSZr:
24745 case VPDPWSSDSZrk:
24746 case VPDPWSSDSZrkz:
24747 case VPDPWSSDSrm:
24748 case VPDPWSSDSrr:
24749 return true;
24750 }
24751 return false;
24752}
24753
24754bool isTILERELEASE(unsigned Opcode) {
24755 return Opcode == TILERELEASE;
24756}
24757
24758bool isCLFLUSHOPT(unsigned Opcode) {
24759 return Opcode == CLFLUSHOPT;
24760}
24761
24762bool isDAS(unsigned Opcode) {
24763 return Opcode == DAS;
24764}
24765
24766bool isVSCALEFPH(unsigned Opcode) {
24767 switch (Opcode) {
24768 case VSCALEFPHZ128rm:
24769 case VSCALEFPHZ128rmb:
24770 case VSCALEFPHZ128rmbk:
24771 case VSCALEFPHZ128rmbkz:
24772 case VSCALEFPHZ128rmk:
24773 case VSCALEFPHZ128rmkz:
24774 case VSCALEFPHZ128rr:
24775 case VSCALEFPHZ128rrk:
24776 case VSCALEFPHZ128rrkz:
24777 case VSCALEFPHZ256rm:
24778 case VSCALEFPHZ256rmb:
24779 case VSCALEFPHZ256rmbk:
24780 case VSCALEFPHZ256rmbkz:
24781 case VSCALEFPHZ256rmk:
24782 case VSCALEFPHZ256rmkz:
24783 case VSCALEFPHZ256rr:
24784 case VSCALEFPHZ256rrk:
24785 case VSCALEFPHZ256rrkz:
24786 case VSCALEFPHZrm:
24787 case VSCALEFPHZrmb:
24788 case VSCALEFPHZrmbk:
24789 case VSCALEFPHZrmbkz:
24790 case VSCALEFPHZrmk:
24791 case VSCALEFPHZrmkz:
24792 case VSCALEFPHZrr:
24793 case VSCALEFPHZrrb:
24794 case VSCALEFPHZrrbk:
24795 case VSCALEFPHZrrbkz:
24796 case VSCALEFPHZrrk:
24797 case VSCALEFPHZrrkz:
24798 return true;
24799 }
24800 return false;
24801}
24802
24803bool isVSUBSD(unsigned Opcode) {
24804 switch (Opcode) {
24805 case VSUBSDZrm_Int:
24806 case VSUBSDZrm_Intk:
24807 case VSUBSDZrm_Intkz:
24808 case VSUBSDZrr_Int:
24809 case VSUBSDZrr_Intk:
24810 case VSUBSDZrr_Intkz:
24811 case VSUBSDZrrb_Int:
24812 case VSUBSDZrrb_Intk:
24813 case VSUBSDZrrb_Intkz:
24814 case VSUBSDrm_Int:
24815 case VSUBSDrr_Int:
24816 return true;
24817 }
24818 return false;
24819}
24820
24821bool isVCOMISS(unsigned Opcode) {
24822 switch (Opcode) {
24823 case VCOMISSZrm:
24824 case VCOMISSZrr:
24825 case VCOMISSZrrb:
24826 case VCOMISSrm:
24827 case VCOMISSrr:
24828 return true;
24829 }
24830 return false;
24831}
24832
24833bool isORPS(unsigned Opcode) {
24834 switch (Opcode) {
24835 case ORPSrm:
24836 case ORPSrr:
24837 return true;
24838 }
24839 return false;
24840}
24841
24842bool isTDPFP16PS(unsigned Opcode) {
24843 return Opcode == TDPFP16PS;
24844}
24845
24846bool isVMAXPD(unsigned Opcode) {
24847 switch (Opcode) {
24848 case VMAXPDYrm:
24849 case VMAXPDYrr:
24850 case VMAXPDZ128rm:
24851 case VMAXPDZ128rmb:
24852 case VMAXPDZ128rmbk:
24853 case VMAXPDZ128rmbkz:
24854 case VMAXPDZ128rmk:
24855 case VMAXPDZ128rmkz:
24856 case VMAXPDZ128rr:
24857 case VMAXPDZ128rrk:
24858 case VMAXPDZ128rrkz:
24859 case VMAXPDZ256rm:
24860 case VMAXPDZ256rmb:
24861 case VMAXPDZ256rmbk:
24862 case VMAXPDZ256rmbkz:
24863 case VMAXPDZ256rmk:
24864 case VMAXPDZ256rmkz:
24865 case VMAXPDZ256rr:
24866 case VMAXPDZ256rrk:
24867 case VMAXPDZ256rrkz:
24868 case VMAXPDZrm:
24869 case VMAXPDZrmb:
24870 case VMAXPDZrmbk:
24871 case VMAXPDZrmbkz:
24872 case VMAXPDZrmk:
24873 case VMAXPDZrmkz:
24874 case VMAXPDZrr:
24875 case VMAXPDZrrb:
24876 case VMAXPDZrrbk:
24877 case VMAXPDZrrbkz:
24878 case VMAXPDZrrk:
24879 case VMAXPDZrrkz:
24880 case VMAXPDrm:
24881 case VMAXPDrr:
24882 return true;
24883 }
24884 return false;
24885}
24886
24887bool isVPMOVWB(unsigned Opcode) {
24888 switch (Opcode) {
24889 case VPMOVWBZ128mr:
24890 case VPMOVWBZ128mrk:
24891 case VPMOVWBZ128rr:
24892 case VPMOVWBZ128rrk:
24893 case VPMOVWBZ128rrkz:
24894 case VPMOVWBZ256mr:
24895 case VPMOVWBZ256mrk:
24896 case VPMOVWBZ256rr:
24897 case VPMOVWBZ256rrk:
24898 case VPMOVWBZ256rrkz:
24899 case VPMOVWBZmr:
24900 case VPMOVWBZmrk:
24901 case VPMOVWBZrr:
24902 case VPMOVWBZrrk:
24903 case VPMOVWBZrrkz:
24904 return true;
24905 }
24906 return false;
24907}
24908
24909bool isVEXP2PS(unsigned Opcode) {
24910 switch (Opcode) {
24911 case VEXP2PSZm:
24912 case VEXP2PSZmb:
24913 case VEXP2PSZmbk:
24914 case VEXP2PSZmbkz:
24915 case VEXP2PSZmk:
24916 case VEXP2PSZmkz:
24917 case VEXP2PSZr:
24918 case VEXP2PSZrb:
24919 case VEXP2PSZrbk:
24920 case VEXP2PSZrbkz:
24921 case VEXP2PSZrk:
24922 case VEXP2PSZrkz:
24923 return true;
24924 }
24925 return false;
24926}
24927
24928bool isVPGATHERDQ(unsigned Opcode) {
24929 switch (Opcode) {
24930 case VPGATHERDQYrm:
24931 case VPGATHERDQZ128rm:
24932 case VPGATHERDQZ256rm:
24933 case VPGATHERDQZrm:
24934 case VPGATHERDQrm:
24935 return true;
24936 }
24937 return false;
24938}
24939
24940bool isVPSRAVQ(unsigned Opcode) {
24941 switch (Opcode) {
24942 case VPSRAVQZ128rm:
24943 case VPSRAVQZ128rmb:
24944 case VPSRAVQZ128rmbk:
24945 case VPSRAVQZ128rmbkz:
24946 case VPSRAVQZ128rmk:
24947 case VPSRAVQZ128rmkz:
24948 case VPSRAVQZ128rr:
24949 case VPSRAVQZ128rrk:
24950 case VPSRAVQZ128rrkz:
24951 case VPSRAVQZ256rm:
24952 case VPSRAVQZ256rmb:
24953 case VPSRAVQZ256rmbk:
24954 case VPSRAVQZ256rmbkz:
24955 case VPSRAVQZ256rmk:
24956 case VPSRAVQZ256rmkz:
24957 case VPSRAVQZ256rr:
24958 case VPSRAVQZ256rrk:
24959 case VPSRAVQZ256rrkz:
24960 case VPSRAVQZrm:
24961 case VPSRAVQZrmb:
24962 case VPSRAVQZrmbk:
24963 case VPSRAVQZrmbkz:
24964 case VPSRAVQZrmk:
24965 case VPSRAVQZrmkz:
24966 case VPSRAVQZrr:
24967 case VPSRAVQZrrk:
24968 case VPSRAVQZrrkz:
24969 return true;
24970 }
24971 return false;
24972}
24973
24974bool isPCMPISTRI(unsigned Opcode) {
24975 switch (Opcode) {
24976 case PCMPISTRIrmi:
24977 case PCMPISTRIrri:
24978 return true;
24979 }
24980 return false;
24981}
24982
24983bool isVFMSUB231PD(unsigned Opcode) {
24984 switch (Opcode) {
24985 case VFMSUB231PDYm:
24986 case VFMSUB231PDYr:
24987 case VFMSUB231PDZ128m:
24988 case VFMSUB231PDZ128mb:
24989 case VFMSUB231PDZ128mbk:
24990 case VFMSUB231PDZ128mbkz:
24991 case VFMSUB231PDZ128mk:
24992 case VFMSUB231PDZ128mkz:
24993 case VFMSUB231PDZ128r:
24994 case VFMSUB231PDZ128rk:
24995 case VFMSUB231PDZ128rkz:
24996 case VFMSUB231PDZ256m:
24997 case VFMSUB231PDZ256mb:
24998 case VFMSUB231PDZ256mbk:
24999 case VFMSUB231PDZ256mbkz:
25000 case VFMSUB231PDZ256mk:
25001 case VFMSUB231PDZ256mkz:
25002 case VFMSUB231PDZ256r:
25003 case VFMSUB231PDZ256rk:
25004 case VFMSUB231PDZ256rkz:
25005 case VFMSUB231PDZm:
25006 case VFMSUB231PDZmb:
25007 case VFMSUB231PDZmbk:
25008 case VFMSUB231PDZmbkz:
25009 case VFMSUB231PDZmk:
25010 case VFMSUB231PDZmkz:
25011 case VFMSUB231PDZr:
25012 case VFMSUB231PDZrb:
25013 case VFMSUB231PDZrbk:
25014 case VFMSUB231PDZrbkz:
25015 case VFMSUB231PDZrk:
25016 case VFMSUB231PDZrkz:
25017 case VFMSUB231PDm:
25018 case VFMSUB231PDr:
25019 return true;
25020 }
25021 return false;
25022}
25023
25024bool isRDMSR(unsigned Opcode) {
25025 return Opcode == RDMSR;
25026}
25027
25028bool isKORTESTD(unsigned Opcode) {
25029 return Opcode == KORTESTDrr;
25030}
25031
25032bool isVPBLENDMW(unsigned Opcode) {
25033 switch (Opcode) {
25034 case VPBLENDMWZ128rm:
25035 case VPBLENDMWZ128rmk:
25036 case VPBLENDMWZ128rmkz:
25037 case VPBLENDMWZ128rr:
25038 case VPBLENDMWZ128rrk:
25039 case VPBLENDMWZ128rrkz:
25040 case VPBLENDMWZ256rm:
25041 case VPBLENDMWZ256rmk:
25042 case VPBLENDMWZ256rmkz:
25043 case VPBLENDMWZ256rr:
25044 case VPBLENDMWZ256rrk:
25045 case VPBLENDMWZ256rrkz:
25046 case VPBLENDMWZrm:
25047 case VPBLENDMWZrmk:
25048 case VPBLENDMWZrmkz:
25049 case VPBLENDMWZrr:
25050 case VPBLENDMWZrrk:
25051 case VPBLENDMWZrrkz:
25052 return true;
25053 }
25054 return false;
25055}
25056
25057bool isPSHUFB(unsigned Opcode) {
25058 switch (Opcode) {
25059 case MMX_PSHUFBrm:
25060 case MMX_PSHUFBrr:
25061 case PSHUFBrm:
25062 case PSHUFBrr:
25063 return true;
25064 }
25065 return false;
25066}
25067
25068bool isVDPBF16PS(unsigned Opcode) {
25069 switch (Opcode) {
25070 case VDPBF16PSZ128m:
25071 case VDPBF16PSZ128mb:
25072 case VDPBF16PSZ128mbk:
25073 case VDPBF16PSZ128mbkz:
25074 case VDPBF16PSZ128mk:
25075 case VDPBF16PSZ128mkz:
25076 case VDPBF16PSZ128r:
25077 case VDPBF16PSZ128rk:
25078 case VDPBF16PSZ128rkz:
25079 case VDPBF16PSZ256m:
25080 case VDPBF16PSZ256mb:
25081 case VDPBF16PSZ256mbk:
25082 case VDPBF16PSZ256mbkz:
25083 case VDPBF16PSZ256mk:
25084 case VDPBF16PSZ256mkz:
25085 case VDPBF16PSZ256r:
25086 case VDPBF16PSZ256rk:
25087 case VDPBF16PSZ256rkz:
25088 case VDPBF16PSZm:
25089 case VDPBF16PSZmb:
25090 case VDPBF16PSZmbk:
25091 case VDPBF16PSZmbkz:
25092 case VDPBF16PSZmk:
25093 case VDPBF16PSZmkz:
25094 case VDPBF16PSZr:
25095 case VDPBF16PSZrk:
25096 case VDPBF16PSZrkz:
25097 return true;
25098 }
25099 return false;
25100}
25101
25102bool isTDPBF16PS(unsigned Opcode) {
25103 return Opcode == TDPBF16PS;
25104}
25105
25106bool isFCMOVE(unsigned Opcode) {
25107 return Opcode == CMOVE_F;
25108}
25109
25110bool isCMPSS(unsigned Opcode) {
25111 switch (Opcode) {
25112 case CMPSSrmi_Int:
25113 case CMPSSrri_Int:
25114 return true;
25115 }
25116 return false;
25117}
25118
25119bool isMASKMOVDQU(unsigned Opcode) {
25120 switch (Opcode) {
25121 case MASKMOVDQU:
25122 case MASKMOVDQU64:
25123 return true;
25124 }
25125 return false;
25126}
25127
25128bool isVPDPWUSDS(unsigned Opcode) {
25129 switch (Opcode) {
25130 case VPDPWUSDSYrm:
25131 case VPDPWUSDSYrr:
25132 case VPDPWUSDSrm:
25133 case VPDPWUSDSrr:
25134 return true;
25135 }
25136 return false;
25137}
25138
25139bool isSARX(unsigned Opcode) {
25140 switch (Opcode) {
25141 case SARX32rm:
25142 case SARX32rm_EVEX:
25143 case SARX32rr:
25144 case SARX32rr_EVEX:
25145 case SARX64rm:
25146 case SARX64rm_EVEX:
25147 case SARX64rr:
25148 case SARX64rr_EVEX:
25149 return true;
25150 }
25151 return false;
25152}
25153
25154bool isSGDT(unsigned Opcode) {
25155 return Opcode == SGDT64m;
25156}
25157
25158bool isVFMULCPH(unsigned Opcode) {
25159 switch (Opcode) {
25160 case VFMULCPHZ128rm:
25161 case VFMULCPHZ128rmb:
25162 case VFMULCPHZ128rmbk:
25163 case VFMULCPHZ128rmbkz:
25164 case VFMULCPHZ128rmk:
25165 case VFMULCPHZ128rmkz:
25166 case VFMULCPHZ128rr:
25167 case VFMULCPHZ128rrk:
25168 case VFMULCPHZ128rrkz:
25169 case VFMULCPHZ256rm:
25170 case VFMULCPHZ256rmb:
25171 case VFMULCPHZ256rmbk:
25172 case VFMULCPHZ256rmbkz:
25173 case VFMULCPHZ256rmk:
25174 case VFMULCPHZ256rmkz:
25175 case VFMULCPHZ256rr:
25176 case VFMULCPHZ256rrk:
25177 case VFMULCPHZ256rrkz:
25178 case VFMULCPHZrm:
25179 case VFMULCPHZrmb:
25180 case VFMULCPHZrmbk:
25181 case VFMULCPHZrmbkz:
25182 case VFMULCPHZrmk:
25183 case VFMULCPHZrmkz:
25184 case VFMULCPHZrr:
25185 case VFMULCPHZrrb:
25186 case VFMULCPHZrrbk:
25187 case VFMULCPHZrrbkz:
25188 case VFMULCPHZrrk:
25189 case VFMULCPHZrrkz:
25190 return true;
25191 }
25192 return false;
25193}
25194
25195bool isURDMSR(unsigned Opcode) {
25196 switch (Opcode) {
25197 case URDMSRri:
25198 case URDMSRri_EVEX:
25199 case URDMSRrr:
25200 case URDMSRrr_EVEX:
25201 return true;
25202 }
25203 return false;
25204}
25205
25206bool isKUNPCKWD(unsigned Opcode) {
25207 return Opcode == KUNPCKWDrr;
25208}
25209
25210bool isCVTPS2PD(unsigned Opcode) {
25211 switch (Opcode) {
25212 case CVTPS2PDrm:
25213 case CVTPS2PDrr:
25214 return true;
25215 }
25216 return false;
25217}
25218
25219bool isFBSTP(unsigned Opcode) {
25220 return Opcode == FBSTPm;
25221}
25222
25223bool isPSUBQ(unsigned Opcode) {
25224 switch (Opcode) {
25225 case MMX_PSUBQrm:
25226 case MMX_PSUBQrr:
25227 case PSUBQrm:
25228 case PSUBQrr:
25229 return true;
25230 }
25231 return false;
25232}
25233
25234bool isFXSAVE64(unsigned Opcode) {
25235 return Opcode == FXSAVE64;
25236}
25237
25238bool isKMOVW(unsigned Opcode) {
25239 switch (Opcode) {
25240 case KMOVWkk:
25241 case KMOVWkk_EVEX:
25242 case KMOVWkm:
25243 case KMOVWkm_EVEX:
25244 case KMOVWkr:
25245 case KMOVWkr_EVEX:
25246 case KMOVWmk:
25247 case KMOVWmk_EVEX:
25248 case KMOVWrk:
25249 case KMOVWrk_EVEX:
25250 return true;
25251 }
25252 return false;
25253}
25254
25255bool isBTS(unsigned Opcode) {
25256 switch (Opcode) {
25257 case BTS16mi8:
25258 case BTS16mr:
25259 case BTS16ri8:
25260 case BTS16rr:
25261 case BTS32mi8:
25262 case BTS32mr:
25263 case BTS32ri8:
25264 case BTS32rr:
25265 case BTS64mi8:
25266 case BTS64mr:
25267 case BTS64ri8:
25268 case BTS64rr:
25269 return true;
25270 }
25271 return false;
25272}
25273
25274bool isVPHADDBQ(unsigned Opcode) {
25275 switch (Opcode) {
25276 case VPHADDBQrm:
25277 case VPHADDBQrr:
25278 return true;
25279 }
25280 return false;
25281}
25282
25283bool isFRSTOR(unsigned Opcode) {
25284 return Opcode == FRSTORm;
25285}
25286
25287bool isVFMSUB132PD(unsigned Opcode) {
25288 switch (Opcode) {
25289 case VFMSUB132PDYm:
25290 case VFMSUB132PDYr:
25291 case VFMSUB132PDZ128m:
25292 case VFMSUB132PDZ128mb:
25293 case VFMSUB132PDZ128mbk:
25294 case VFMSUB132PDZ128mbkz:
25295 case VFMSUB132PDZ128mk:
25296 case VFMSUB132PDZ128mkz:
25297 case VFMSUB132PDZ128r:
25298 case VFMSUB132PDZ128rk:
25299 case VFMSUB132PDZ128rkz:
25300 case VFMSUB132PDZ256m:
25301 case VFMSUB132PDZ256mb:
25302 case VFMSUB132PDZ256mbk:
25303 case VFMSUB132PDZ256mbkz:
25304 case VFMSUB132PDZ256mk:
25305 case VFMSUB132PDZ256mkz:
25306 case VFMSUB132PDZ256r:
25307 case VFMSUB132PDZ256rk:
25308 case VFMSUB132PDZ256rkz:
25309 case VFMSUB132PDZm:
25310 case VFMSUB132PDZmb:
25311 case VFMSUB132PDZmbk:
25312 case VFMSUB132PDZmbkz:
25313 case VFMSUB132PDZmk:
25314 case VFMSUB132PDZmkz:
25315 case VFMSUB132PDZr:
25316 case VFMSUB132PDZrb:
25317 case VFMSUB132PDZrbk:
25318 case VFMSUB132PDZrbkz:
25319 case VFMSUB132PDZrk:
25320 case VFMSUB132PDZrkz:
25321 case VFMSUB132PDm:
25322 case VFMSUB132PDr:
25323 return true;
25324 }
25325 return false;
25326}
25327
25328bool isPMULLD(unsigned Opcode) {
25329 switch (Opcode) {
25330 case PMULLDrm:
25331 case PMULLDrr:
25332 return true;
25333 }
25334 return false;
25335}
25336
25337bool isSHA1MSG2(unsigned Opcode) {
25338 switch (Opcode) {
25339 case SHA1MSG2rm:
25340 case SHA1MSG2rr:
25341 return true;
25342 }
25343 return false;
25344}
25345
25346bool isJECXZ(unsigned Opcode) {
25347 return Opcode == JECXZ;
25348}
25349
25350bool isVCVTUDQ2PS(unsigned Opcode) {
25351 switch (Opcode) {
25352 case VCVTUDQ2PSZ128rm:
25353 case VCVTUDQ2PSZ128rmb:
25354 case VCVTUDQ2PSZ128rmbk:
25355 case VCVTUDQ2PSZ128rmbkz:
25356 case VCVTUDQ2PSZ128rmk:
25357 case VCVTUDQ2PSZ128rmkz:
25358 case VCVTUDQ2PSZ128rr:
25359 case VCVTUDQ2PSZ128rrk:
25360 case VCVTUDQ2PSZ128rrkz:
25361 case VCVTUDQ2PSZ256rm:
25362 case VCVTUDQ2PSZ256rmb:
25363 case VCVTUDQ2PSZ256rmbk:
25364 case VCVTUDQ2PSZ256rmbkz:
25365 case VCVTUDQ2PSZ256rmk:
25366 case VCVTUDQ2PSZ256rmkz:
25367 case VCVTUDQ2PSZ256rr:
25368 case VCVTUDQ2PSZ256rrk:
25369 case VCVTUDQ2PSZ256rrkz:
25370 case VCVTUDQ2PSZrm:
25371 case VCVTUDQ2PSZrmb:
25372 case VCVTUDQ2PSZrmbk:
25373 case VCVTUDQ2PSZrmbkz:
25374 case VCVTUDQ2PSZrmk:
25375 case VCVTUDQ2PSZrmkz:
25376 case VCVTUDQ2PSZrr:
25377 case VCVTUDQ2PSZrrb:
25378 case VCVTUDQ2PSZrrbk:
25379 case VCVTUDQ2PSZrrbkz:
25380 case VCVTUDQ2PSZrrk:
25381 case VCVTUDQ2PSZrrkz:
25382 return true;
25383 }
25384 return false;
25385}
25386
25387bool isAESENC(unsigned Opcode) {
25388 switch (Opcode) {
25389 case AESENCrm:
25390 case AESENCrr:
25391 return true;
25392 }
25393 return false;
25394}
25395
25396bool isPSIGNW(unsigned Opcode) {
25397 switch (Opcode) {
25398 case MMX_PSIGNWrm:
25399 case MMX_PSIGNWrr:
25400 case PSIGNWrm:
25401 case PSIGNWrr:
25402 return true;
25403 }
25404 return false;
25405}
25406
25407bool isUNPCKLPD(unsigned Opcode) {
25408 switch (Opcode) {
25409 case UNPCKLPDrm:
25410 case UNPCKLPDrr:
25411 return true;
25412 }
25413 return false;
25414}
25415
25416bool isPUSHP(unsigned Opcode) {
25417 return Opcode == PUSHP64r;
25418}
25419
25420bool isBLSI(unsigned Opcode) {
25421 switch (Opcode) {
25422 case BLSI32rm:
25423 case BLSI32rm_EVEX:
25424 case BLSI32rm_NF:
25425 case BLSI32rr:
25426 case BLSI32rr_EVEX:
25427 case BLSI32rr_NF:
25428 case BLSI64rm:
25429 case BLSI64rm_EVEX:
25430 case BLSI64rm_NF:
25431 case BLSI64rr:
25432 case BLSI64rr_EVEX:
25433 case BLSI64rr_NF:
25434 return true;
25435 }
25436 return false;
25437}
25438
25439bool isVPTESTNMB(unsigned Opcode) {
25440 switch (Opcode) {
25441 case VPTESTNMBZ128rm:
25442 case VPTESTNMBZ128rmk:
25443 case VPTESTNMBZ128rr:
25444 case VPTESTNMBZ128rrk:
25445 case VPTESTNMBZ256rm:
25446 case VPTESTNMBZ256rmk:
25447 case VPTESTNMBZ256rr:
25448 case VPTESTNMBZ256rrk:
25449 case VPTESTNMBZrm:
25450 case VPTESTNMBZrmk:
25451 case VPTESTNMBZrr:
25452 case VPTESTNMBZrrk:
25453 return true;
25454 }
25455 return false;
25456}
25457
25458bool isWRUSSQ(unsigned Opcode) {
25459 switch (Opcode) {
25460 case WRUSSQ:
25461 case WRUSSQ_EVEX:
25462 return true;
25463 }
25464 return false;
25465}
25466
25467bool isVGF2P8MULB(unsigned Opcode) {
25468 switch (Opcode) {
25469 case VGF2P8MULBYrm:
25470 case VGF2P8MULBYrr:
25471 case VGF2P8MULBZ128rm:
25472 case VGF2P8MULBZ128rmk:
25473 case VGF2P8MULBZ128rmkz:
25474 case VGF2P8MULBZ128rr:
25475 case VGF2P8MULBZ128rrk:
25476 case VGF2P8MULBZ128rrkz:
25477 case VGF2P8MULBZ256rm:
25478 case VGF2P8MULBZ256rmk:
25479 case VGF2P8MULBZ256rmkz:
25480 case VGF2P8MULBZ256rr:
25481 case VGF2P8MULBZ256rrk:
25482 case VGF2P8MULBZ256rrkz:
25483 case VGF2P8MULBZrm:
25484 case VGF2P8MULBZrmk:
25485 case VGF2P8MULBZrmkz:
25486 case VGF2P8MULBZrr:
25487 case VGF2P8MULBZrrk:
25488 case VGF2P8MULBZrrkz:
25489 case VGF2P8MULBrm:
25490 case VGF2P8MULBrr:
25491 return true;
25492 }
25493 return false;
25494}
25495
25496bool isVPUNPCKLBW(unsigned Opcode) {
25497 switch (Opcode) {
25498 case VPUNPCKLBWYrm:
25499 case VPUNPCKLBWYrr:
25500 case VPUNPCKLBWZ128rm:
25501 case VPUNPCKLBWZ128rmk:
25502 case VPUNPCKLBWZ128rmkz:
25503 case VPUNPCKLBWZ128rr:
25504 case VPUNPCKLBWZ128rrk:
25505 case VPUNPCKLBWZ128rrkz:
25506 case VPUNPCKLBWZ256rm:
25507 case VPUNPCKLBWZ256rmk:
25508 case VPUNPCKLBWZ256rmkz:
25509 case VPUNPCKLBWZ256rr:
25510 case VPUNPCKLBWZ256rrk:
25511 case VPUNPCKLBWZ256rrkz:
25512 case VPUNPCKLBWZrm:
25513 case VPUNPCKLBWZrmk:
25514 case VPUNPCKLBWZrmkz:
25515 case VPUNPCKLBWZrr:
25516 case VPUNPCKLBWZrrk:
25517 case VPUNPCKLBWZrrkz:
25518 case VPUNPCKLBWrm:
25519 case VPUNPCKLBWrr:
25520 return true;
25521 }
25522 return false;
25523}
25524
25525bool isVRANGESD(unsigned Opcode) {
25526 switch (Opcode) {
25527 case VRANGESDZrmi:
25528 case VRANGESDZrmik:
25529 case VRANGESDZrmikz:
25530 case VRANGESDZrri:
25531 case VRANGESDZrrib:
25532 case VRANGESDZrribk:
25533 case VRANGESDZrribkz:
25534 case VRANGESDZrrik:
25535 case VRANGESDZrrikz:
25536 return true;
25537 }
25538 return false;
25539}
25540
25541bool isCLD(unsigned Opcode) {
25542 return Opcode == CLD;
25543}
25544
25545bool isVSCALEFPD(unsigned Opcode) {
25546 switch (Opcode) {
25547 case VSCALEFPDZ128rm:
25548 case VSCALEFPDZ128rmb:
25549 case VSCALEFPDZ128rmbk:
25550 case VSCALEFPDZ128rmbkz:
25551 case VSCALEFPDZ128rmk:
25552 case VSCALEFPDZ128rmkz:
25553 case VSCALEFPDZ128rr:
25554 case VSCALEFPDZ128rrk:
25555 case VSCALEFPDZ128rrkz:
25556 case VSCALEFPDZ256rm:
25557 case VSCALEFPDZ256rmb:
25558 case VSCALEFPDZ256rmbk:
25559 case VSCALEFPDZ256rmbkz:
25560 case VSCALEFPDZ256rmk:
25561 case VSCALEFPDZ256rmkz:
25562 case VSCALEFPDZ256rr:
25563 case VSCALEFPDZ256rrk:
25564 case VSCALEFPDZ256rrkz:
25565 case VSCALEFPDZrm:
25566 case VSCALEFPDZrmb:
25567 case VSCALEFPDZrmbk:
25568 case VSCALEFPDZrmbkz:
25569 case VSCALEFPDZrmk:
25570 case VSCALEFPDZrmkz:
25571 case VSCALEFPDZrr:
25572 case VSCALEFPDZrrb:
25573 case VSCALEFPDZrrbk:
25574 case VSCALEFPDZrrbkz:
25575 case VSCALEFPDZrrk:
25576 case VSCALEFPDZrrkz:
25577 return true;
25578 }
25579 return false;
25580}
25581
25582bool isVPERMQ(unsigned Opcode) {
25583 switch (Opcode) {
25584 case VPERMQYmi:
25585 case VPERMQYri:
25586 case VPERMQZ256mbi:
25587 case VPERMQZ256mbik:
25588 case VPERMQZ256mbikz:
25589 case VPERMQZ256mi:
25590 case VPERMQZ256mik:
25591 case VPERMQZ256mikz:
25592 case VPERMQZ256ri:
25593 case VPERMQZ256rik:
25594 case VPERMQZ256rikz:
25595 case VPERMQZ256rm:
25596 case VPERMQZ256rmb:
25597 case VPERMQZ256rmbk:
25598 case VPERMQZ256rmbkz:
25599 case VPERMQZ256rmk:
25600 case VPERMQZ256rmkz:
25601 case VPERMQZ256rr:
25602 case VPERMQZ256rrk:
25603 case VPERMQZ256rrkz:
25604 case VPERMQZmbi:
25605 case VPERMQZmbik:
25606 case VPERMQZmbikz:
25607 case VPERMQZmi:
25608 case VPERMQZmik:
25609 case VPERMQZmikz:
25610 case VPERMQZri:
25611 case VPERMQZrik:
25612 case VPERMQZrikz:
25613 case VPERMQZrm:
25614 case VPERMQZrmb:
25615 case VPERMQZrmbk:
25616 case VPERMQZrmbkz:
25617 case VPERMQZrmk:
25618 case VPERMQZrmkz:
25619 case VPERMQZrr:
25620 case VPERMQZrrk:
25621 case VPERMQZrrkz:
25622 return true;
25623 }
25624 return false;
25625}
25626
25627bool isVPSHLDVW(unsigned Opcode) {
25628 switch (Opcode) {
25629 case VPSHLDVWZ128m:
25630 case VPSHLDVWZ128mk:
25631 case VPSHLDVWZ128mkz:
25632 case VPSHLDVWZ128r:
25633 case VPSHLDVWZ128rk:
25634 case VPSHLDVWZ128rkz:
25635 case VPSHLDVWZ256m:
25636 case VPSHLDVWZ256mk:
25637 case VPSHLDVWZ256mkz:
25638 case VPSHLDVWZ256r:
25639 case VPSHLDVWZ256rk:
25640 case VPSHLDVWZ256rkz:
25641 case VPSHLDVWZm:
25642 case VPSHLDVWZmk:
25643 case VPSHLDVWZmkz:
25644 case VPSHLDVWZr:
25645 case VPSHLDVWZrk:
25646 case VPSHLDVWZrkz:
25647 return true;
25648 }
25649 return false;
25650}
25651
25652bool isROR(unsigned Opcode) {
25653 switch (Opcode) {
25654 case ROR16m1:
25655 case ROR16m1_EVEX:
25656 case ROR16m1_ND:
25657 case ROR16m1_NF:
25658 case ROR16m1_NF_ND:
25659 case ROR16mCL:
25660 case ROR16mCL_EVEX:
25661 case ROR16mCL_ND:
25662 case ROR16mCL_NF:
25663 case ROR16mCL_NF_ND:
25664 case ROR16mi:
25665 case ROR16mi_EVEX:
25666 case ROR16mi_ND:
25667 case ROR16mi_NF:
25668 case ROR16mi_NF_ND:
25669 case ROR16r1:
25670 case ROR16r1_EVEX:
25671 case ROR16r1_ND:
25672 case ROR16r1_NF:
25673 case ROR16r1_NF_ND:
25674 case ROR16rCL:
25675 case ROR16rCL_EVEX:
25676 case ROR16rCL_ND:
25677 case ROR16rCL_NF:
25678 case ROR16rCL_NF_ND:
25679 case ROR16ri:
25680 case ROR16ri_EVEX:
25681 case ROR16ri_ND:
25682 case ROR16ri_NF:
25683 case ROR16ri_NF_ND:
25684 case ROR32m1:
25685 case ROR32m1_EVEX:
25686 case ROR32m1_ND:
25687 case ROR32m1_NF:
25688 case ROR32m1_NF_ND:
25689 case ROR32mCL:
25690 case ROR32mCL_EVEX:
25691 case ROR32mCL_ND:
25692 case ROR32mCL_NF:
25693 case ROR32mCL_NF_ND:
25694 case ROR32mi:
25695 case ROR32mi_EVEX:
25696 case ROR32mi_ND:
25697 case ROR32mi_NF:
25698 case ROR32mi_NF_ND:
25699 case ROR32r1:
25700 case ROR32r1_EVEX:
25701 case ROR32r1_ND:
25702 case ROR32r1_NF:
25703 case ROR32r1_NF_ND:
25704 case ROR32rCL:
25705 case ROR32rCL_EVEX:
25706 case ROR32rCL_ND:
25707 case ROR32rCL_NF:
25708 case ROR32rCL_NF_ND:
25709 case ROR32ri:
25710 case ROR32ri_EVEX:
25711 case ROR32ri_ND:
25712 case ROR32ri_NF:
25713 case ROR32ri_NF_ND:
25714 case ROR64m1:
25715 case ROR64m1_EVEX:
25716 case ROR64m1_ND:
25717 case ROR64m1_NF:
25718 case ROR64m1_NF_ND:
25719 case ROR64mCL:
25720 case ROR64mCL_EVEX:
25721 case ROR64mCL_ND:
25722 case ROR64mCL_NF:
25723 case ROR64mCL_NF_ND:
25724 case ROR64mi:
25725 case ROR64mi_EVEX:
25726 case ROR64mi_ND:
25727 case ROR64mi_NF:
25728 case ROR64mi_NF_ND:
25729 case ROR64r1:
25730 case ROR64r1_EVEX:
25731 case ROR64r1_ND:
25732 case ROR64r1_NF:
25733 case ROR64r1_NF_ND:
25734 case ROR64rCL:
25735 case ROR64rCL_EVEX:
25736 case ROR64rCL_ND:
25737 case ROR64rCL_NF:
25738 case ROR64rCL_NF_ND:
25739 case ROR64ri:
25740 case ROR64ri_EVEX:
25741 case ROR64ri_ND:
25742 case ROR64ri_NF:
25743 case ROR64ri_NF_ND:
25744 case ROR8m1:
25745 case ROR8m1_EVEX:
25746 case ROR8m1_ND:
25747 case ROR8m1_NF:
25748 case ROR8m1_NF_ND:
25749 case ROR8mCL:
25750 case ROR8mCL_EVEX:
25751 case ROR8mCL_ND:
25752 case ROR8mCL_NF:
25753 case ROR8mCL_NF_ND:
25754 case ROR8mi:
25755 case ROR8mi_EVEX:
25756 case ROR8mi_ND:
25757 case ROR8mi_NF:
25758 case ROR8mi_NF_ND:
25759 case ROR8r1:
25760 case ROR8r1_EVEX:
25761 case ROR8r1_ND:
25762 case ROR8r1_NF:
25763 case ROR8r1_NF_ND:
25764 case ROR8rCL:
25765 case ROR8rCL_EVEX:
25766 case ROR8rCL_ND:
25767 case ROR8rCL_NF:
25768 case ROR8rCL_NF_ND:
25769 case ROR8ri:
25770 case ROR8ri_EVEX:
25771 case ROR8ri_ND:
25772 case ROR8ri_NF:
25773 case ROR8ri_NF_ND:
25774 return true;
25775 }
25776 return false;
25777}
25778
25779bool isVFMADDSUB132PH(unsigned Opcode) {
25780 switch (Opcode) {
25781 case VFMADDSUB132PHZ128m:
25782 case VFMADDSUB132PHZ128mb:
25783 case VFMADDSUB132PHZ128mbk:
25784 case VFMADDSUB132PHZ128mbkz:
25785 case VFMADDSUB132PHZ128mk:
25786 case VFMADDSUB132PHZ128mkz:
25787 case VFMADDSUB132PHZ128r:
25788 case VFMADDSUB132PHZ128rk:
25789 case VFMADDSUB132PHZ128rkz:
25790 case VFMADDSUB132PHZ256m:
25791 case VFMADDSUB132PHZ256mb:
25792 case VFMADDSUB132PHZ256mbk:
25793 case VFMADDSUB132PHZ256mbkz:
25794 case VFMADDSUB132PHZ256mk:
25795 case VFMADDSUB132PHZ256mkz:
25796 case VFMADDSUB132PHZ256r:
25797 case VFMADDSUB132PHZ256rk:
25798 case VFMADDSUB132PHZ256rkz:
25799 case VFMADDSUB132PHZm:
25800 case VFMADDSUB132PHZmb:
25801 case VFMADDSUB132PHZmbk:
25802 case VFMADDSUB132PHZmbkz:
25803 case VFMADDSUB132PHZmk:
25804 case VFMADDSUB132PHZmkz:
25805 case VFMADDSUB132PHZr:
25806 case VFMADDSUB132PHZrb:
25807 case VFMADDSUB132PHZrbk:
25808 case VFMADDSUB132PHZrbkz:
25809 case VFMADDSUB132PHZrk:
25810 case VFMADDSUB132PHZrkz:
25811 return true;
25812 }
25813 return false;
25814}
25815
25816bool isDEC(unsigned Opcode) {
25817 switch (Opcode) {
25818 case DEC16m:
25819 case DEC16m_EVEX:
25820 case DEC16m_ND:
25821 case DEC16m_NF:
25822 case DEC16m_NF_ND:
25823 case DEC16r:
25824 case DEC16r_EVEX:
25825 case DEC16r_ND:
25826 case DEC16r_NF:
25827 case DEC16r_NF_ND:
25828 case DEC16r_alt:
25829 case DEC32m:
25830 case DEC32m_EVEX:
25831 case DEC32m_ND:
25832 case DEC32m_NF:
25833 case DEC32m_NF_ND:
25834 case DEC32r:
25835 case DEC32r_EVEX:
25836 case DEC32r_ND:
25837 case DEC32r_NF:
25838 case DEC32r_NF_ND:
25839 case DEC32r_alt:
25840 case DEC64m:
25841 case DEC64m_EVEX:
25842 case DEC64m_ND:
25843 case DEC64m_NF:
25844 case DEC64m_NF_ND:
25845 case DEC64r:
25846 case DEC64r_EVEX:
25847 case DEC64r_ND:
25848 case DEC64r_NF:
25849 case DEC64r_NF_ND:
25850 case DEC8m:
25851 case DEC8m_EVEX:
25852 case DEC8m_ND:
25853 case DEC8m_NF:
25854 case DEC8m_NF_ND:
25855 case DEC8r:
25856 case DEC8r_EVEX:
25857 case DEC8r_ND:
25858 case DEC8r_NF:
25859 case DEC8r_NF_ND:
25860 return true;
25861 }
25862 return false;
25863}
25864
25865bool isVGETEXPSH(unsigned Opcode) {
25866 switch (Opcode) {
25867 case VGETEXPSHZm:
25868 case VGETEXPSHZmk:
25869 case VGETEXPSHZmkz:
25870 case VGETEXPSHZr:
25871 case VGETEXPSHZrb:
25872 case VGETEXPSHZrbk:
25873 case VGETEXPSHZrbkz:
25874 case VGETEXPSHZrk:
25875 case VGETEXPSHZrkz:
25876 return true;
25877 }
25878 return false;
25879}
25880
25881bool isAESDEC(unsigned Opcode) {
25882 switch (Opcode) {
25883 case AESDECrm:
25884 case AESDECrr:
25885 return true;
25886 }
25887 return false;
25888}
25889
25890bool isKORD(unsigned Opcode) {
25891 return Opcode == KORDrr;
25892}
25893
25894bool isVPMULHW(unsigned Opcode) {
25895 switch (Opcode) {
25896 case VPMULHWYrm:
25897 case VPMULHWYrr:
25898 case VPMULHWZ128rm:
25899 case VPMULHWZ128rmk:
25900 case VPMULHWZ128rmkz:
25901 case VPMULHWZ128rr:
25902 case VPMULHWZ128rrk:
25903 case VPMULHWZ128rrkz:
25904 case VPMULHWZ256rm:
25905 case VPMULHWZ256rmk:
25906 case VPMULHWZ256rmkz:
25907 case VPMULHWZ256rr:
25908 case VPMULHWZ256rrk:
25909 case VPMULHWZ256rrkz:
25910 case VPMULHWZrm:
25911 case VPMULHWZrmk:
25912 case VPMULHWZrmkz:
25913 case VPMULHWZrr:
25914 case VPMULHWZrrk:
25915 case VPMULHWZrrkz:
25916 case VPMULHWrm:
25917 case VPMULHWrr:
25918 return true;
25919 }
25920 return false;
25921}
25922
25923bool isTILELOADDT1(unsigned Opcode) {
25924 switch (Opcode) {
25925 case TILELOADDT1:
25926 case TILELOADDT1_EVEX:
25927 return true;
25928 }
25929 return false;
25930}
25931
25932bool isVMASKMOVPS(unsigned Opcode) {
25933 switch (Opcode) {
25934 case VMASKMOVPSYmr:
25935 case VMASKMOVPSYrm:
25936 case VMASKMOVPSmr:
25937 case VMASKMOVPSrm:
25938 return true;
25939 }
25940 return false;
25941}
25942
25943bool isPMOVZXDQ(unsigned Opcode) {
25944 switch (Opcode) {
25945 case PMOVZXDQrm:
25946 case PMOVZXDQrr:
25947 return true;
25948 }
25949 return false;
25950}
25951
25952bool isVCVTPS2PH(unsigned Opcode) {
25953 switch (Opcode) {
25954 case VCVTPS2PHYmr:
25955 case VCVTPS2PHYrr:
25956 case VCVTPS2PHZ128mr:
25957 case VCVTPS2PHZ128mrk:
25958 case VCVTPS2PHZ128rr:
25959 case VCVTPS2PHZ128rrk:
25960 case VCVTPS2PHZ128rrkz:
25961 case VCVTPS2PHZ256mr:
25962 case VCVTPS2PHZ256mrk:
25963 case VCVTPS2PHZ256rr:
25964 case VCVTPS2PHZ256rrk:
25965 case VCVTPS2PHZ256rrkz:
25966 case VCVTPS2PHZmr:
25967 case VCVTPS2PHZmrk:
25968 case VCVTPS2PHZrr:
25969 case VCVTPS2PHZrrb:
25970 case VCVTPS2PHZrrbk:
25971 case VCVTPS2PHZrrbkz:
25972 case VCVTPS2PHZrrk:
25973 case VCVTPS2PHZrrkz:
25974 case VCVTPS2PHmr:
25975 case VCVTPS2PHrr:
25976 return true;
25977 }
25978 return false;
25979}
25980
25981bool isCVTDQ2PD(unsigned Opcode) {
25982 switch (Opcode) {
25983 case CVTDQ2PDrm:
25984 case CVTDQ2PDrr:
25985 return true;
25986 }
25987 return false;
25988}
25989
25990bool isVCVTSD2SS(unsigned Opcode) {
25991 switch (Opcode) {
25992 case VCVTSD2SSZrm_Int:
25993 case VCVTSD2SSZrm_Intk:
25994 case VCVTSD2SSZrm_Intkz:
25995 case VCVTSD2SSZrr_Int:
25996 case VCVTSD2SSZrr_Intk:
25997 case VCVTSD2SSZrr_Intkz:
25998 case VCVTSD2SSZrrb_Int:
25999 case VCVTSD2SSZrrb_Intk:
26000 case VCVTSD2SSZrrb_Intkz:
26001 case VCVTSD2SSrm_Int:
26002 case VCVTSD2SSrr_Int:
26003 return true;
26004 }
26005 return false;
26006}
26007
26008bool isVFMSUB213PH(unsigned Opcode) {
26009 switch (Opcode) {
26010 case VFMSUB213PHZ128m:
26011 case VFMSUB213PHZ128mb:
26012 case VFMSUB213PHZ128mbk:
26013 case VFMSUB213PHZ128mbkz:
26014 case VFMSUB213PHZ128mk:
26015 case VFMSUB213PHZ128mkz:
26016 case VFMSUB213PHZ128r:
26017 case VFMSUB213PHZ128rk:
26018 case VFMSUB213PHZ128rkz:
26019 case VFMSUB213PHZ256m:
26020 case VFMSUB213PHZ256mb:
26021 case VFMSUB213PHZ256mbk:
26022 case VFMSUB213PHZ256mbkz:
26023 case VFMSUB213PHZ256mk:
26024 case VFMSUB213PHZ256mkz:
26025 case VFMSUB213PHZ256r:
26026 case VFMSUB213PHZ256rk:
26027 case VFMSUB213PHZ256rkz:
26028 case VFMSUB213PHZm:
26029 case VFMSUB213PHZmb:
26030 case VFMSUB213PHZmbk:
26031 case VFMSUB213PHZmbkz:
26032 case VFMSUB213PHZmk:
26033 case VFMSUB213PHZmkz:
26034 case VFMSUB213PHZr:
26035 case VFMSUB213PHZrb:
26036 case VFMSUB213PHZrbk:
26037 case VFMSUB213PHZrbkz:
26038 case VFMSUB213PHZrk:
26039 case VFMSUB213PHZrkz:
26040 return true;
26041 }
26042 return false;
26043}
26044
26045bool isVPROTB(unsigned Opcode) {
26046 switch (Opcode) {
26047 case VPROTBmi:
26048 case VPROTBmr:
26049 case VPROTBri:
26050 case VPROTBrm:
26051 case VPROTBrr:
26052 case VPROTBrr_REV:
26053 return true;
26054 }
26055 return false;
26056}
26057
26058bool isPINSRD(unsigned Opcode) {
26059 switch (Opcode) {
26060 case PINSRDrm:
26061 case PINSRDrr:
26062 return true;
26063 }
26064 return false;
26065}
26066
26067bool isVMXON(unsigned Opcode) {
26068 return Opcode == VMXON;
26069}
26070
26071bool isVFCMULCSH(unsigned Opcode) {
26072 switch (Opcode) {
26073 case VFCMULCSHZrm:
26074 case VFCMULCSHZrmk:
26075 case VFCMULCSHZrmkz:
26076 case VFCMULCSHZrr:
26077 case VFCMULCSHZrrb:
26078 case VFCMULCSHZrrbk:
26079 case VFCMULCSHZrrbkz:
26080 case VFCMULCSHZrrk:
26081 case VFCMULCSHZrrkz:
26082 return true;
26083 }
26084 return false;
26085}
26086
26087bool isVFMULCSH(unsigned Opcode) {
26088 switch (Opcode) {
26089 case VFMULCSHZrm:
26090 case VFMULCSHZrmk:
26091 case VFMULCSHZrmkz:
26092 case VFMULCSHZrr:
26093 case VFMULCSHZrrb:
26094 case VFMULCSHZrrbk:
26095 case VFMULCSHZrrbkz:
26096 case VFMULCSHZrrk:
26097 case VFMULCSHZrrkz:
26098 return true;
26099 }
26100 return false;
26101}
26102
26103bool isVRANGEPD(unsigned Opcode) {
26104 switch (Opcode) {
26105 case VRANGEPDZ128rmbi:
26106 case VRANGEPDZ128rmbik:
26107 case VRANGEPDZ128rmbikz:
26108 case VRANGEPDZ128rmi:
26109 case VRANGEPDZ128rmik:
26110 case VRANGEPDZ128rmikz:
26111 case VRANGEPDZ128rri:
26112 case VRANGEPDZ128rrik:
26113 case VRANGEPDZ128rrikz:
26114 case VRANGEPDZ256rmbi:
26115 case VRANGEPDZ256rmbik:
26116 case VRANGEPDZ256rmbikz:
26117 case VRANGEPDZ256rmi:
26118 case VRANGEPDZ256rmik:
26119 case VRANGEPDZ256rmikz:
26120 case VRANGEPDZ256rri:
26121 case VRANGEPDZ256rrik:
26122 case VRANGEPDZ256rrikz:
26123 case VRANGEPDZrmbi:
26124 case VRANGEPDZrmbik:
26125 case VRANGEPDZrmbikz:
26126 case VRANGEPDZrmi:
26127 case VRANGEPDZrmik:
26128 case VRANGEPDZrmikz:
26129 case VRANGEPDZrri:
26130 case VRANGEPDZrrib:
26131 case VRANGEPDZrribk:
26132 case VRANGEPDZrribkz:
26133 case VRANGEPDZrrik:
26134 case VRANGEPDZrrikz:
26135 return true;
26136 }
26137 return false;
26138}
26139
26140bool isCMC(unsigned Opcode) {
26141 return Opcode == CMC;
26142}
26143
26144bool isSHA256MSG1(unsigned Opcode) {
26145 switch (Opcode) {
26146 case SHA256MSG1rm:
26147 case SHA256MSG1rr:
26148 return true;
26149 }
26150 return false;
26151}
26152
26153bool isFLD1(unsigned Opcode) {
26154 return Opcode == LD_F1;
26155}
26156
26157bool isCMPPS(unsigned Opcode) {
26158 switch (Opcode) {
26159 case CMPPSrmi:
26160 case CMPPSrri:
26161 return true;
26162 }
26163 return false;
26164}
26165
26166bool isVPAVGW(unsigned Opcode) {
26167 switch (Opcode) {
26168 case VPAVGWYrm:
26169 case VPAVGWYrr:
26170 case VPAVGWZ128rm:
26171 case VPAVGWZ128rmk:
26172 case VPAVGWZ128rmkz:
26173 case VPAVGWZ128rr:
26174 case VPAVGWZ128rrk:
26175 case VPAVGWZ128rrkz:
26176 case VPAVGWZ256rm:
26177 case VPAVGWZ256rmk:
26178 case VPAVGWZ256rmkz:
26179 case VPAVGWZ256rr:
26180 case VPAVGWZ256rrk:
26181 case VPAVGWZ256rrkz:
26182 case VPAVGWZrm:
26183 case VPAVGWZrmk:
26184 case VPAVGWZrmkz:
26185 case VPAVGWZrr:
26186 case VPAVGWZrrk:
26187 case VPAVGWZrrkz:
26188 case VPAVGWrm:
26189 case VPAVGWrr:
26190 return true;
26191 }
26192 return false;
26193}
26194
26195bool isVFMADD213SH(unsigned Opcode) {
26196 switch (Opcode) {
26197 case VFMADD213SHZm_Int:
26198 case VFMADD213SHZm_Intk:
26199 case VFMADD213SHZm_Intkz:
26200 case VFMADD213SHZr_Int:
26201 case VFMADD213SHZr_Intk:
26202 case VFMADD213SHZr_Intkz:
26203 case VFMADD213SHZrb_Int:
26204 case VFMADD213SHZrb_Intk:
26205 case VFMADD213SHZrb_Intkz:
26206 return true;
26207 }
26208 return false;
26209}
26210
26211bool isVPINSRQ(unsigned Opcode) {
26212 switch (Opcode) {
26213 case VPINSRQZrm:
26214 case VPINSRQZrr:
26215 case VPINSRQrm:
26216 case VPINSRQrr:
26217 return true;
26218 }
26219 return false;
26220}
26221
26222bool isMOVABS(unsigned Opcode) {
26223 switch (Opcode) {
26224 case MOV16ao64:
26225 case MOV16o64a:
26226 case MOV32ao64:
26227 case MOV32o64a:
26228 case MOV64ao64:
26229 case MOV64o64a:
26230 case MOV64ri:
26231 case MOV8ao64:
26232 case MOV8o64a:
26233 return true;
26234 }
26235 return false;
26236}
26237
26238bool isVPSHAQ(unsigned Opcode) {
26239 switch (Opcode) {
26240 case VPSHAQmr:
26241 case VPSHAQrm:
26242 case VPSHAQrr:
26243 case VPSHAQrr_REV:
26244 return true;
26245 }
26246 return false;
26247}
26248
26249bool isRDTSCP(unsigned Opcode) {
26250 return Opcode == RDTSCP;
26251}
26252
26253bool isVFNMADD231SS(unsigned Opcode) {
26254 switch (Opcode) {
26255 case VFNMADD231SSZm_Int:
26256 case VFNMADD231SSZm_Intk:
26257 case VFNMADD231SSZm_Intkz:
26258 case VFNMADD231SSZr_Int:
26259 case VFNMADD231SSZr_Intk:
26260 case VFNMADD231SSZr_Intkz:
26261 case VFNMADD231SSZrb_Int:
26262 case VFNMADD231SSZrb_Intk:
26263 case VFNMADD231SSZrb_Intkz:
26264 case VFNMADD231SSm_Int:
26265 case VFNMADD231SSr_Int:
26266 return true;
26267 }
26268 return false;
26269}
26270
26271bool isTEST(unsigned Opcode) {
26272 switch (Opcode) {
26273 case TEST16i16:
26274 case TEST16mi:
26275 case TEST16mr:
26276 case TEST16ri:
26277 case TEST16rr:
26278 case TEST32i32:
26279 case TEST32mi:
26280 case TEST32mr:
26281 case TEST32ri:
26282 case TEST32rr:
26283 case TEST64i32:
26284 case TEST64mi32:
26285 case TEST64mr:
26286 case TEST64ri32:
26287 case TEST64rr:
26288 case TEST8i8:
26289 case TEST8mi:
26290 case TEST8mr:
26291 case TEST8ri:
26292 case TEST8rr:
26293 return true;
26294 }
26295 return false;
26296}
26297
26298bool isVPERMD(unsigned Opcode) {
26299 switch (Opcode) {
26300 case VPERMDYrm:
26301 case VPERMDYrr:
26302 case VPERMDZ256rm:
26303 case VPERMDZ256rmb:
26304 case VPERMDZ256rmbk:
26305 case VPERMDZ256rmbkz:
26306 case VPERMDZ256rmk:
26307 case VPERMDZ256rmkz:
26308 case VPERMDZ256rr:
26309 case VPERMDZ256rrk:
26310 case VPERMDZ256rrkz:
26311 case VPERMDZrm:
26312 case VPERMDZrmb:
26313 case VPERMDZrmbk:
26314 case VPERMDZrmbkz:
26315 case VPERMDZrmk:
26316 case VPERMDZrmkz:
26317 case VPERMDZrr:
26318 case VPERMDZrrk:
26319 case VPERMDZrrkz:
26320 return true;
26321 }
26322 return false;
26323}
26324
26325bool isVBCSTNESH2PS(unsigned Opcode) {
26326 switch (Opcode) {
26327 case VBCSTNESH2PSYrm:
26328 case VBCSTNESH2PSrm:
26329 return true;
26330 }
26331 return false;
26332}
26333
26334bool isVGATHERPF0QPD(unsigned Opcode) {
26335 return Opcode == VGATHERPF0QPDm;
26336}
26337
26338bool isVPERM2I128(unsigned Opcode) {
26339 switch (Opcode) {
26340 case VPERM2I128rm:
26341 case VPERM2I128rr:
26342 return true;
26343 }
26344 return false;
26345}
26346
26347bool isVMPSADBW(unsigned Opcode) {
26348 switch (Opcode) {
26349 case VMPSADBWYrmi:
26350 case VMPSADBWYrri:
26351 case VMPSADBWrmi:
26352 case VMPSADBWrri:
26353 return true;
26354 }
26355 return false;
26356}
26357
26358bool isVFNMSUB231PD(unsigned Opcode) {
26359 switch (Opcode) {
26360 case VFNMSUB231PDYm:
26361 case VFNMSUB231PDYr:
26362 case VFNMSUB231PDZ128m:
26363 case VFNMSUB231PDZ128mb:
26364 case VFNMSUB231PDZ128mbk:
26365 case VFNMSUB231PDZ128mbkz:
26366 case VFNMSUB231PDZ128mk:
26367 case VFNMSUB231PDZ128mkz:
26368 case VFNMSUB231PDZ128r:
26369 case VFNMSUB231PDZ128rk:
26370 case VFNMSUB231PDZ128rkz:
26371 case VFNMSUB231PDZ256m:
26372 case VFNMSUB231PDZ256mb:
26373 case VFNMSUB231PDZ256mbk:
26374 case VFNMSUB231PDZ256mbkz:
26375 case VFNMSUB231PDZ256mk:
26376 case VFNMSUB231PDZ256mkz:
26377 case VFNMSUB231PDZ256r:
26378 case VFNMSUB231PDZ256rk:
26379 case VFNMSUB231PDZ256rkz:
26380 case VFNMSUB231PDZm:
26381 case VFNMSUB231PDZmb:
26382 case VFNMSUB231PDZmbk:
26383 case VFNMSUB231PDZmbkz:
26384 case VFNMSUB231PDZmk:
26385 case VFNMSUB231PDZmkz:
26386 case VFNMSUB231PDZr:
26387 case VFNMSUB231PDZrb:
26388 case VFNMSUB231PDZrbk:
26389 case VFNMSUB231PDZrbkz:
26390 case VFNMSUB231PDZrk:
26391 case VFNMSUB231PDZrkz:
26392 case VFNMSUB231PDm:
26393 case VFNMSUB231PDr:
26394 return true;
26395 }
26396 return false;
26397}
26398
26399bool isPADDSB(unsigned Opcode) {
26400 switch (Opcode) {
26401 case MMX_PADDSBrm:
26402 case MMX_PADDSBrr:
26403 case PADDSBrm:
26404 case PADDSBrr:
26405 return true;
26406 }
26407 return false;
26408}
26409
26410bool isMWAITX(unsigned Opcode) {
26411 return Opcode == MWAITXrrr;
26412}
26413
26414bool isMONITORX(unsigned Opcode) {
26415 switch (Opcode) {
26416 case MONITORX32rrr:
26417 case MONITORX64rrr:
26418 return true;
26419 }
26420 return false;
26421}
26422
26423bool isVPEXPANDD(unsigned Opcode) {
26424 switch (Opcode) {
26425 case VPEXPANDDZ128rm:
26426 case VPEXPANDDZ128rmk:
26427 case VPEXPANDDZ128rmkz:
26428 case VPEXPANDDZ128rr:
26429 case VPEXPANDDZ128rrk:
26430 case VPEXPANDDZ128rrkz:
26431 case VPEXPANDDZ256rm:
26432 case VPEXPANDDZ256rmk:
26433 case VPEXPANDDZ256rmkz:
26434 case VPEXPANDDZ256rr:
26435 case VPEXPANDDZ256rrk:
26436 case VPEXPANDDZ256rrkz:
26437 case VPEXPANDDZrm:
26438 case VPEXPANDDZrmk:
26439 case VPEXPANDDZrmkz:
26440 case VPEXPANDDZrr:
26441 case VPEXPANDDZrrk:
26442 case VPEXPANDDZrrkz:
26443 return true;
26444 }
26445 return false;
26446}
26447
26448bool isVFRCZPD(unsigned Opcode) {
26449 switch (Opcode) {
26450 case VFRCZPDYrm:
26451 case VFRCZPDYrr:
26452 case VFRCZPDrm:
26453 case VFRCZPDrr:
26454 return true;
26455 }
26456 return false;
26457}
26458
26459bool isVRCPPH(unsigned Opcode) {
26460 switch (Opcode) {
26461 case VRCPPHZ128m:
26462 case VRCPPHZ128mb:
26463 case VRCPPHZ128mbk:
26464 case VRCPPHZ128mbkz:
26465 case VRCPPHZ128mk:
26466 case VRCPPHZ128mkz:
26467 case VRCPPHZ128r:
26468 case VRCPPHZ128rk:
26469 case VRCPPHZ128rkz:
26470 case VRCPPHZ256m:
26471 case VRCPPHZ256mb:
26472 case VRCPPHZ256mbk:
26473 case VRCPPHZ256mbkz:
26474 case VRCPPHZ256mk:
26475 case VRCPPHZ256mkz:
26476 case VRCPPHZ256r:
26477 case VRCPPHZ256rk:
26478 case VRCPPHZ256rkz:
26479 case VRCPPHZm:
26480 case VRCPPHZmb:
26481 case VRCPPHZmbk:
26482 case VRCPPHZmbkz:
26483 case VRCPPHZmk:
26484 case VRCPPHZmkz:
26485 case VRCPPHZr:
26486 case VRCPPHZrk:
26487 case VRCPPHZrkz:
26488 return true;
26489 }
26490 return false;
26491}
26492
26493bool isFEMMS(unsigned Opcode) {
26494 return Opcode == FEMMS;
26495}
26496
26497bool isVSCATTERQPD(unsigned Opcode) {
26498 switch (Opcode) {
26499 case VSCATTERQPDZ128mr:
26500 case VSCATTERQPDZ256mr:
26501 case VSCATTERQPDZmr:
26502 return true;
26503 }
26504 return false;
26505}
26506
26507bool isVMOVW(unsigned Opcode) {
26508 switch (Opcode) {
26509 case VMOVSH2Wrr:
26510 case VMOVSHtoW64rr:
26511 case VMOVW2SHrr:
26512 case VMOVW64toSHrr:
26513 case VMOVWmr:
26514 case VMOVWrm:
26515 return true;
26516 }
26517 return false;
26518}
26519
26520bool isVPBROADCASTD(unsigned Opcode) {
26521 switch (Opcode) {
26522 case VPBROADCASTDYrm:
26523 case VPBROADCASTDYrr:
26524 case VPBROADCASTDZ128rm:
26525 case VPBROADCASTDZ128rmk:
26526 case VPBROADCASTDZ128rmkz:
26527 case VPBROADCASTDZ128rr:
26528 case VPBROADCASTDZ128rrk:
26529 case VPBROADCASTDZ128rrkz:
26530 case VPBROADCASTDZ256rm:
26531 case VPBROADCASTDZ256rmk:
26532 case VPBROADCASTDZ256rmkz:
26533 case VPBROADCASTDZ256rr:
26534 case VPBROADCASTDZ256rrk:
26535 case VPBROADCASTDZ256rrkz:
26536 case VPBROADCASTDZrm:
26537 case VPBROADCASTDZrmk:
26538 case VPBROADCASTDZrmkz:
26539 case VPBROADCASTDZrr:
26540 case VPBROADCASTDZrrk:
26541 case VPBROADCASTDZrrkz:
26542 case VPBROADCASTDrZ128rr:
26543 case VPBROADCASTDrZ128rrk:
26544 case VPBROADCASTDrZ128rrkz:
26545 case VPBROADCASTDrZ256rr:
26546 case VPBROADCASTDrZ256rrk:
26547 case VPBROADCASTDrZ256rrkz:
26548 case VPBROADCASTDrZrr:
26549 case VPBROADCASTDrZrrk:
26550 case VPBROADCASTDrZrrkz:
26551 case VPBROADCASTDrm:
26552 case VPBROADCASTDrr:
26553 return true;
26554 }
26555 return false;
26556}
26557
26558bool isSTOSB(unsigned Opcode) {
26559 return Opcode == STOSB;
26560}
26561
26562bool isFUCOMI(unsigned Opcode) {
26563 return Opcode == UCOM_FIr;
26564}
26565
26566bool isVBROADCASTI64X4(unsigned Opcode) {
26567 switch (Opcode) {
26568 case VBROADCASTI64X4rm:
26569 case VBROADCASTI64X4rmk:
26570 case VBROADCASTI64X4rmkz:
26571 return true;
26572 }
26573 return false;
26574}
26575
26576bool isFCMOVU(unsigned Opcode) {
26577 return Opcode == CMOVP_F;
26578}
26579
26580bool isPSHUFLW(unsigned Opcode) {
26581 switch (Opcode) {
26582 case PSHUFLWmi:
26583 case PSHUFLWri:
26584 return true;
26585 }
26586 return false;
26587}
26588
26589bool isCVTPI2PS(unsigned Opcode) {
26590 switch (Opcode) {
26591 case MMX_CVTPI2PSrm:
26592 case MMX_CVTPI2PSrr:
26593 return true;
26594 }
26595 return false;
26596}
26597
26598bool isVFMADD231SH(unsigned Opcode) {
26599 switch (Opcode) {
26600 case VFMADD231SHZm_Int:
26601 case VFMADD231SHZm_Intk:
26602 case VFMADD231SHZm_Intkz:
26603 case VFMADD231SHZr_Int:
26604 case VFMADD231SHZr_Intk:
26605 case VFMADD231SHZr_Intkz:
26606 case VFMADD231SHZrb_Int:
26607 case VFMADD231SHZrb_Intk:
26608 case VFMADD231SHZrb_Intkz:
26609 return true;
26610 }
26611 return false;
26612}
26613
26614bool isSYSCALL(unsigned Opcode) {
26615 return Opcode == SYSCALL;
26616}
26617
26618bool isVPOPCNTB(unsigned Opcode) {
26619 switch (Opcode) {
26620 case VPOPCNTBZ128rm:
26621 case VPOPCNTBZ128rmk:
26622 case VPOPCNTBZ128rmkz:
26623 case VPOPCNTBZ128rr:
26624 case VPOPCNTBZ128rrk:
26625 case VPOPCNTBZ128rrkz:
26626 case VPOPCNTBZ256rm:
26627 case VPOPCNTBZ256rmk:
26628 case VPOPCNTBZ256rmkz:
26629 case VPOPCNTBZ256rr:
26630 case VPOPCNTBZ256rrk:
26631 case VPOPCNTBZ256rrkz:
26632 case VPOPCNTBZrm:
26633 case VPOPCNTBZrmk:
26634 case VPOPCNTBZrmkz:
26635 case VPOPCNTBZrr:
26636 case VPOPCNTBZrrk:
26637 case VPOPCNTBZrrkz:
26638 return true;
26639 }
26640 return false;
26641}
26642
26643bool isPMOVZXBW(unsigned Opcode) {
26644 switch (Opcode) {
26645 case PMOVZXBWrm:
26646 case PMOVZXBWrr:
26647 return true;
26648 }
26649 return false;
26650}
26651
26652bool isVCVTDQ2PS(unsigned Opcode) {
26653 switch (Opcode) {
26654 case VCVTDQ2PSYrm:
26655 case VCVTDQ2PSYrr:
26656 case VCVTDQ2PSZ128rm:
26657 case VCVTDQ2PSZ128rmb:
26658 case VCVTDQ2PSZ128rmbk:
26659 case VCVTDQ2PSZ128rmbkz:
26660 case VCVTDQ2PSZ128rmk:
26661 case VCVTDQ2PSZ128rmkz:
26662 case VCVTDQ2PSZ128rr:
26663 case VCVTDQ2PSZ128rrk:
26664 case VCVTDQ2PSZ128rrkz:
26665 case VCVTDQ2PSZ256rm:
26666 case VCVTDQ2PSZ256rmb:
26667 case VCVTDQ2PSZ256rmbk:
26668 case VCVTDQ2PSZ256rmbkz:
26669 case VCVTDQ2PSZ256rmk:
26670 case VCVTDQ2PSZ256rmkz:
26671 case VCVTDQ2PSZ256rr:
26672 case VCVTDQ2PSZ256rrk:
26673 case VCVTDQ2PSZ256rrkz:
26674 case VCVTDQ2PSZrm:
26675 case VCVTDQ2PSZrmb:
26676 case VCVTDQ2PSZrmbk:
26677 case VCVTDQ2PSZrmbkz:
26678 case VCVTDQ2PSZrmk:
26679 case VCVTDQ2PSZrmkz:
26680 case VCVTDQ2PSZrr:
26681 case VCVTDQ2PSZrrb:
26682 case VCVTDQ2PSZrrbk:
26683 case VCVTDQ2PSZrrbkz:
26684 case VCVTDQ2PSZrrk:
26685 case VCVTDQ2PSZrrkz:
26686 case VCVTDQ2PSrm:
26687 case VCVTDQ2PSrr:
26688 return true;
26689 }
26690 return false;
26691}
26692
26693bool isPSUBD(unsigned Opcode) {
26694 switch (Opcode) {
26695 case MMX_PSUBDrm:
26696 case MMX_PSUBDrr:
26697 case PSUBDrm:
26698 case PSUBDrr:
26699 return true;
26700 }
26701 return false;
26702}
26703
26704bool isVPCMPEQW(unsigned Opcode) {
26705 switch (Opcode) {
26706 case VPCMPEQWYrm:
26707 case VPCMPEQWYrr:
26708 case VPCMPEQWZ128rm:
26709 case VPCMPEQWZ128rmk:
26710 case VPCMPEQWZ128rr:
26711 case VPCMPEQWZ128rrk:
26712 case VPCMPEQWZ256rm:
26713 case VPCMPEQWZ256rmk:
26714 case VPCMPEQWZ256rr:
26715 case VPCMPEQWZ256rrk:
26716 case VPCMPEQWZrm:
26717 case VPCMPEQWZrmk:
26718 case VPCMPEQWZrr:
26719 case VPCMPEQWZrrk:
26720 case VPCMPEQWrm:
26721 case VPCMPEQWrr:
26722 return true;
26723 }
26724 return false;
26725}
26726
26727bool isMOVSW(unsigned Opcode) {
26728 return Opcode == MOVSW;
26729}
26730
26731bool isVSM3RNDS2(unsigned Opcode) {
26732 switch (Opcode) {
26733 case VSM3RNDS2rm:
26734 case VSM3RNDS2rr:
26735 return true;
26736 }
26737 return false;
26738}
26739
26740bool isVPMOVUSQD(unsigned Opcode) {
26741 switch (Opcode) {
26742 case VPMOVUSQDZ128mr:
26743 case VPMOVUSQDZ128mrk:
26744 case VPMOVUSQDZ128rr:
26745 case VPMOVUSQDZ128rrk:
26746 case VPMOVUSQDZ128rrkz:
26747 case VPMOVUSQDZ256mr:
26748 case VPMOVUSQDZ256mrk:
26749 case VPMOVUSQDZ256rr:
26750 case VPMOVUSQDZ256rrk:
26751 case VPMOVUSQDZ256rrkz:
26752 case VPMOVUSQDZmr:
26753 case VPMOVUSQDZmrk:
26754 case VPMOVUSQDZrr:
26755 case VPMOVUSQDZrrk:
26756 case VPMOVUSQDZrrkz:
26757 return true;
26758 }
26759 return false;
26760}
26761
26762bool isCVTTPD2DQ(unsigned Opcode) {
26763 switch (Opcode) {
26764 case CVTTPD2DQrm:
26765 case CVTTPD2DQrr:
26766 return true;
26767 }
26768 return false;
26769}
26770
26771bool isVPEXPANDW(unsigned Opcode) {
26772 switch (Opcode) {
26773 case VPEXPANDWZ128rm:
26774 case VPEXPANDWZ128rmk:
26775 case VPEXPANDWZ128rmkz:
26776 case VPEXPANDWZ128rr:
26777 case VPEXPANDWZ128rrk:
26778 case VPEXPANDWZ128rrkz:
26779 case VPEXPANDWZ256rm:
26780 case VPEXPANDWZ256rmk:
26781 case VPEXPANDWZ256rmkz:
26782 case VPEXPANDWZ256rr:
26783 case VPEXPANDWZ256rrk:
26784 case VPEXPANDWZ256rrkz:
26785 case VPEXPANDWZrm:
26786 case VPEXPANDWZrmk:
26787 case VPEXPANDWZrmkz:
26788 case VPEXPANDWZrr:
26789 case VPEXPANDWZrrk:
26790 case VPEXPANDWZrrkz:
26791 return true;
26792 }
26793 return false;
26794}
26795
26796bool isVUCOMISH(unsigned Opcode) {
26797 switch (Opcode) {
26798 case VUCOMISHZrm:
26799 case VUCOMISHZrr:
26800 case VUCOMISHZrrb:
26801 return true;
26802 }
26803 return false;
26804}
26805
26806bool isVZEROALL(unsigned Opcode) {
26807 return Opcode == VZEROALL;
26808}
26809
26810bool isVPAND(unsigned Opcode) {
26811 switch (Opcode) {
26812 case VPANDYrm:
26813 case VPANDYrr:
26814 case VPANDrm:
26815 case VPANDrr:
26816 return true;
26817 }
26818 return false;
26819}
26820
26821bool isPMULDQ(unsigned Opcode) {
26822 switch (Opcode) {
26823 case PMULDQrm:
26824 case PMULDQrr:
26825 return true;
26826 }
26827 return false;
26828}
26829
26830bool isVPSHUFHW(unsigned Opcode) {
26831 switch (Opcode) {
26832 case VPSHUFHWYmi:
26833 case VPSHUFHWYri:
26834 case VPSHUFHWZ128mi:
26835 case VPSHUFHWZ128mik:
26836 case VPSHUFHWZ128mikz:
26837 case VPSHUFHWZ128ri:
26838 case VPSHUFHWZ128rik:
26839 case VPSHUFHWZ128rikz:
26840 case VPSHUFHWZ256mi:
26841 case VPSHUFHWZ256mik:
26842 case VPSHUFHWZ256mikz:
26843 case VPSHUFHWZ256ri:
26844 case VPSHUFHWZ256rik:
26845 case VPSHUFHWZ256rikz:
26846 case VPSHUFHWZmi:
26847 case VPSHUFHWZmik:
26848 case VPSHUFHWZmikz:
26849 case VPSHUFHWZri:
26850 case VPSHUFHWZrik:
26851 case VPSHUFHWZrikz:
26852 case VPSHUFHWmi:
26853 case VPSHUFHWri:
26854 return true;
26855 }
26856 return false;
26857}
26858
26859bool isVPALIGNR(unsigned Opcode) {
26860 switch (Opcode) {
26861 case VPALIGNRYrmi:
26862 case VPALIGNRYrri:
26863 case VPALIGNRZ128rmi:
26864 case VPALIGNRZ128rmik:
26865 case VPALIGNRZ128rmikz:
26866 case VPALIGNRZ128rri:
26867 case VPALIGNRZ128rrik:
26868 case VPALIGNRZ128rrikz:
26869 case VPALIGNRZ256rmi:
26870 case VPALIGNRZ256rmik:
26871 case VPALIGNRZ256rmikz:
26872 case VPALIGNRZ256rri:
26873 case VPALIGNRZ256rrik:
26874 case VPALIGNRZ256rrikz:
26875 case VPALIGNRZrmi:
26876 case VPALIGNRZrmik:
26877 case VPALIGNRZrmikz:
26878 case VPALIGNRZrri:
26879 case VPALIGNRZrrik:
26880 case VPALIGNRZrrikz:
26881 case VPALIGNRrmi:
26882 case VPALIGNRrri:
26883 return true;
26884 }
26885 return false;
26886}
26887
26888bool isSQRTSD(unsigned Opcode) {
26889 switch (Opcode) {
26890 case SQRTSDm_Int:
26891 case SQRTSDr_Int:
26892 return true;
26893 }
26894 return false;
26895}
26896
26897bool isVCVTTPH2UDQ(unsigned Opcode) {
26898 switch (Opcode) {
26899 case VCVTTPH2UDQZ128rm:
26900 case VCVTTPH2UDQZ128rmb:
26901 case VCVTTPH2UDQZ128rmbk:
26902 case VCVTTPH2UDQZ128rmbkz:
26903 case VCVTTPH2UDQZ128rmk:
26904 case VCVTTPH2UDQZ128rmkz:
26905 case VCVTTPH2UDQZ128rr:
26906 case VCVTTPH2UDQZ128rrk:
26907 case VCVTTPH2UDQZ128rrkz:
26908 case VCVTTPH2UDQZ256rm:
26909 case VCVTTPH2UDQZ256rmb:
26910 case VCVTTPH2UDQZ256rmbk:
26911 case VCVTTPH2UDQZ256rmbkz:
26912 case VCVTTPH2UDQZ256rmk:
26913 case VCVTTPH2UDQZ256rmkz:
26914 case VCVTTPH2UDQZ256rr:
26915 case VCVTTPH2UDQZ256rrk:
26916 case VCVTTPH2UDQZ256rrkz:
26917 case VCVTTPH2UDQZrm:
26918 case VCVTTPH2UDQZrmb:
26919 case VCVTTPH2UDQZrmbk:
26920 case VCVTTPH2UDQZrmbkz:
26921 case VCVTTPH2UDQZrmk:
26922 case VCVTTPH2UDQZrmkz:
26923 case VCVTTPH2UDQZrr:
26924 case VCVTTPH2UDQZrrb:
26925 case VCVTTPH2UDQZrrbk:
26926 case VCVTTPH2UDQZrrbkz:
26927 case VCVTTPH2UDQZrrk:
26928 case VCVTTPH2UDQZrrkz:
26929 return true;
26930 }
26931 return false;
26932}
26933
26934bool isVGETEXPPH(unsigned Opcode) {
26935 switch (Opcode) {
26936 case VGETEXPPHZ128m:
26937 case VGETEXPPHZ128mb:
26938 case VGETEXPPHZ128mbk:
26939 case VGETEXPPHZ128mbkz:
26940 case VGETEXPPHZ128mk:
26941 case VGETEXPPHZ128mkz:
26942 case VGETEXPPHZ128r:
26943 case VGETEXPPHZ128rk:
26944 case VGETEXPPHZ128rkz:
26945 case VGETEXPPHZ256m:
26946 case VGETEXPPHZ256mb:
26947 case VGETEXPPHZ256mbk:
26948 case VGETEXPPHZ256mbkz:
26949 case VGETEXPPHZ256mk:
26950 case VGETEXPPHZ256mkz:
26951 case VGETEXPPHZ256r:
26952 case VGETEXPPHZ256rk:
26953 case VGETEXPPHZ256rkz:
26954 case VGETEXPPHZm:
26955 case VGETEXPPHZmb:
26956 case VGETEXPPHZmbk:
26957 case VGETEXPPHZmbkz:
26958 case VGETEXPPHZmk:
26959 case VGETEXPPHZmkz:
26960 case VGETEXPPHZr:
26961 case VGETEXPPHZrb:
26962 case VGETEXPPHZrbk:
26963 case VGETEXPPHZrbkz:
26964 case VGETEXPPHZrk:
26965 case VGETEXPPHZrkz:
26966 return true;
26967 }
26968 return false;
26969}
26970
26971bool isADDPD(unsigned Opcode) {
26972 switch (Opcode) {
26973 case ADDPDrm:
26974 case ADDPDrr:
26975 return true;
26976 }
26977 return false;
26978}
26979
26980bool isVFNMADDPD(unsigned Opcode) {
26981 switch (Opcode) {
26982 case VFNMADDPD4Ymr:
26983 case VFNMADDPD4Yrm:
26984 case VFNMADDPD4Yrr:
26985 case VFNMADDPD4Yrr_REV:
26986 case VFNMADDPD4mr:
26987 case VFNMADDPD4rm:
26988 case VFNMADDPD4rr:
26989 case VFNMADDPD4rr_REV:
26990 return true;
26991 }
26992 return false;
26993}
26994
26995bool isSTTILECFG(unsigned Opcode) {
26996 switch (Opcode) {
26997 case STTILECFG:
26998 case STTILECFG_EVEX:
26999 return true;
27000 }
27001 return false;
27002}
27003
27004bool isVMINPD(unsigned Opcode) {
27005 switch (Opcode) {
27006 case VMINPDYrm:
27007 case VMINPDYrr:
27008 case VMINPDZ128rm:
27009 case VMINPDZ128rmb:
27010 case VMINPDZ128rmbk:
27011 case VMINPDZ128rmbkz:
27012 case VMINPDZ128rmk:
27013 case VMINPDZ128rmkz:
27014 case VMINPDZ128rr:
27015 case VMINPDZ128rrk:
27016 case VMINPDZ128rrkz:
27017 case VMINPDZ256rm:
27018 case VMINPDZ256rmb:
27019 case VMINPDZ256rmbk:
27020 case VMINPDZ256rmbkz:
27021 case VMINPDZ256rmk:
27022 case VMINPDZ256rmkz:
27023 case VMINPDZ256rr:
27024 case VMINPDZ256rrk:
27025 case VMINPDZ256rrkz:
27026 case VMINPDZrm:
27027 case VMINPDZrmb:
27028 case VMINPDZrmbk:
27029 case VMINPDZrmbkz:
27030 case VMINPDZrmk:
27031 case VMINPDZrmkz:
27032 case VMINPDZrr:
27033 case VMINPDZrrb:
27034 case VMINPDZrrbk:
27035 case VMINPDZrrbkz:
27036 case VMINPDZrrk:
27037 case VMINPDZrrkz:
27038 case VMINPDrm:
27039 case VMINPDrr:
27040 return true;
27041 }
27042 return false;
27043}
27044
27045bool isSHA1RNDS4(unsigned Opcode) {
27046 switch (Opcode) {
27047 case SHA1RNDS4rmi:
27048 case SHA1RNDS4rri:
27049 return true;
27050 }
27051 return false;
27052}
27053
27054bool isPBLENDVB(unsigned Opcode) {
27055 switch (Opcode) {
27056 case PBLENDVBrm0:
27057 case PBLENDVBrr0:
27058 return true;
27059 }
27060 return false;
27061}
27062
27063bool isVBROADCASTF128(unsigned Opcode) {
27064 return Opcode == VBROADCASTF128rm;
27065}
27066
27067bool isVPSHRDQ(unsigned Opcode) {
27068 switch (Opcode) {
27069 case VPSHRDQZ128rmbi:
27070 case VPSHRDQZ128rmbik:
27071 case VPSHRDQZ128rmbikz:
27072 case VPSHRDQZ128rmi:
27073 case VPSHRDQZ128rmik:
27074 case VPSHRDQZ128rmikz:
27075 case VPSHRDQZ128rri:
27076 case VPSHRDQZ128rrik:
27077 case VPSHRDQZ128rrikz:
27078 case VPSHRDQZ256rmbi:
27079 case VPSHRDQZ256rmbik:
27080 case VPSHRDQZ256rmbikz:
27081 case VPSHRDQZ256rmi:
27082 case VPSHRDQZ256rmik:
27083 case VPSHRDQZ256rmikz:
27084 case VPSHRDQZ256rri:
27085 case VPSHRDQZ256rrik:
27086 case VPSHRDQZ256rrikz:
27087 case VPSHRDQZrmbi:
27088 case VPSHRDQZrmbik:
27089 case VPSHRDQZrmbikz:
27090 case VPSHRDQZrmi:
27091 case VPSHRDQZrmik:
27092 case VPSHRDQZrmikz:
27093 case VPSHRDQZrri:
27094 case VPSHRDQZrrik:
27095 case VPSHRDQZrrikz:
27096 return true;
27097 }
27098 return false;
27099}
27100
27101bool isVAESIMC(unsigned Opcode) {
27102 switch (Opcode) {
27103 case VAESIMCrm:
27104 case VAESIMCrr:
27105 return true;
27106 }
27107 return false;
27108}
27109
27110bool isCOMISD(unsigned Opcode) {
27111 switch (Opcode) {
27112 case COMISDrm:
27113 case COMISDrr:
27114 return true;
27115 }
27116 return false;
27117}
27118
27119bool isVMOVSH(unsigned Opcode) {
27120 switch (Opcode) {
27121 case VMOVSHZmr:
27122 case VMOVSHZmrk:
27123 case VMOVSHZrm:
27124 case VMOVSHZrmk:
27125 case VMOVSHZrmkz:
27126 case VMOVSHZrr:
27127 case VMOVSHZrr_REV:
27128 case VMOVSHZrrk:
27129 case VMOVSHZrrk_REV:
27130 case VMOVSHZrrkz:
27131 case VMOVSHZrrkz_REV:
27132 return true;
27133 }
27134 return false;
27135}
27136
27137bool isPFSUBR(unsigned Opcode) {
27138 switch (Opcode) {
27139 case PFSUBRrm:
27140 case PFSUBRrr:
27141 return true;
27142 }
27143 return false;
27144}
27145
27146bool isRDSSPD(unsigned Opcode) {
27147 return Opcode == RDSSPD;
27148}
27149
27150bool isWAIT(unsigned Opcode) {
27151 return Opcode == WAIT;
27152}
27153
27154bool isVFPCLASSSS(unsigned Opcode) {
27155 switch (Opcode) {
27156 case VFPCLASSSSZrm:
27157 case VFPCLASSSSZrmk:
27158 case VFPCLASSSSZrr:
27159 case VFPCLASSSSZrrk:
27160 return true;
27161 }
27162 return false;
27163}
27164
27165bool isPCMPGTD(unsigned Opcode) {
27166 switch (Opcode) {
27167 case MMX_PCMPGTDrm:
27168 case MMX_PCMPGTDrr:
27169 case PCMPGTDrm:
27170 case PCMPGTDrr:
27171 return true;
27172 }
27173 return false;
27174}
27175
27176bool isVGATHERPF0QPS(unsigned Opcode) {
27177 return Opcode == VGATHERPF0QPSm;
27178}
27179
27180bool isBLENDVPS(unsigned Opcode) {
27181 switch (Opcode) {
27182 case BLENDVPSrm0:
27183 case BLENDVPSrr0:
27184 return true;
27185 }
27186 return false;
27187}
27188
27189bool isVBROADCASTF32X4(unsigned Opcode) {
27190 switch (Opcode) {
27191 case VBROADCASTF32X4Z256rm:
27192 case VBROADCASTF32X4Z256rmk:
27193 case VBROADCASTF32X4Z256rmkz:
27194 case VBROADCASTF32X4rm:
27195 case VBROADCASTF32X4rmk:
27196 case VBROADCASTF32X4rmkz:
27197 return true;
27198 }
27199 return false;
27200}
27201
27202bool isVPMADD52LUQ(unsigned Opcode) {
27203 switch (Opcode) {
27204 case VPMADD52LUQYrm:
27205 case VPMADD52LUQYrr:
27206 case VPMADD52LUQZ128m:
27207 case VPMADD52LUQZ128mb:
27208 case VPMADD52LUQZ128mbk:
27209 case VPMADD52LUQZ128mbkz:
27210 case VPMADD52LUQZ128mk:
27211 case VPMADD52LUQZ128mkz:
27212 case VPMADD52LUQZ128r:
27213 case VPMADD52LUQZ128rk:
27214 case VPMADD52LUQZ128rkz:
27215 case VPMADD52LUQZ256m:
27216 case VPMADD52LUQZ256mb:
27217 case VPMADD52LUQZ256mbk:
27218 case VPMADD52LUQZ256mbkz:
27219 case VPMADD52LUQZ256mk:
27220 case VPMADD52LUQZ256mkz:
27221 case VPMADD52LUQZ256r:
27222 case VPMADD52LUQZ256rk:
27223 case VPMADD52LUQZ256rkz:
27224 case VPMADD52LUQZm:
27225 case VPMADD52LUQZmb:
27226 case VPMADD52LUQZmbk:
27227 case VPMADD52LUQZmbkz:
27228 case VPMADD52LUQZmk:
27229 case VPMADD52LUQZmkz:
27230 case VPMADD52LUQZr:
27231 case VPMADD52LUQZrk:
27232 case VPMADD52LUQZrkz:
27233 case VPMADD52LUQrm:
27234 case VPMADD52LUQrr:
27235 return true;
27236 }
27237 return false;
27238}
27239
27240bool isVMOVLPD(unsigned Opcode) {
27241 switch (Opcode) {
27242 case VMOVLPDZ128mr:
27243 case VMOVLPDZ128rm:
27244 case VMOVLPDmr:
27245 case VMOVLPDrm:
27246 return true;
27247 }
27248 return false;
27249}
27250
27251bool isVMOVQ(unsigned Opcode) {
27252 switch (Opcode) {
27253 case VMOV64toPQIZrm:
27254 case VMOV64toPQIZrr:
27255 case VMOV64toPQIrm:
27256 case VMOV64toPQIrr:
27257 case VMOVPQI2QIZmr:
27258 case VMOVPQI2QIZrr:
27259 case VMOVPQI2QImr:
27260 case VMOVPQI2QIrr:
27261 case VMOVPQIto64Zmr:
27262 case VMOVPQIto64Zrr:
27263 case VMOVPQIto64mr:
27264 case VMOVPQIto64rr:
27265 case VMOVQI2PQIZrm:
27266 case VMOVQI2PQIrm:
27267 case VMOVZPQILo2PQIZrr:
27268 case VMOVZPQILo2PQIrr:
27269 return true;
27270 }
27271 return false;
27272}
27273
27274bool isVMOVDQU(unsigned Opcode) {
27275 switch (Opcode) {
27276 case VMOVDQUYmr:
27277 case VMOVDQUYrm:
27278 case VMOVDQUYrr:
27279 case VMOVDQUYrr_REV:
27280 case VMOVDQUmr:
27281 case VMOVDQUrm:
27282 case VMOVDQUrr:
27283 case VMOVDQUrr_REV:
27284 return true;
27285 }
27286 return false;
27287}
27288
27289bool isAESENC128KL(unsigned Opcode) {
27290 return Opcode == AESENC128KL;
27291}
27292
27293bool isVFMADDSUB231PS(unsigned Opcode) {
27294 switch (Opcode) {
27295 case VFMADDSUB231PSYm:
27296 case VFMADDSUB231PSYr:
27297 case VFMADDSUB231PSZ128m:
27298 case VFMADDSUB231PSZ128mb:
27299 case VFMADDSUB231PSZ128mbk:
27300 case VFMADDSUB231PSZ128mbkz:
27301 case VFMADDSUB231PSZ128mk:
27302 case VFMADDSUB231PSZ128mkz:
27303 case VFMADDSUB231PSZ128r:
27304 case VFMADDSUB231PSZ128rk:
27305 case VFMADDSUB231PSZ128rkz:
27306 case VFMADDSUB231PSZ256m:
27307 case VFMADDSUB231PSZ256mb:
27308 case VFMADDSUB231PSZ256mbk:
27309 case VFMADDSUB231PSZ256mbkz:
27310 case VFMADDSUB231PSZ256mk:
27311 case VFMADDSUB231PSZ256mkz:
27312 case VFMADDSUB231PSZ256r:
27313 case VFMADDSUB231PSZ256rk:
27314 case VFMADDSUB231PSZ256rkz:
27315 case VFMADDSUB231PSZm:
27316 case VFMADDSUB231PSZmb:
27317 case VFMADDSUB231PSZmbk:
27318 case VFMADDSUB231PSZmbkz:
27319 case VFMADDSUB231PSZmk:
27320 case VFMADDSUB231PSZmkz:
27321 case VFMADDSUB231PSZr:
27322 case VFMADDSUB231PSZrb:
27323 case VFMADDSUB231PSZrbk:
27324 case VFMADDSUB231PSZrbkz:
27325 case VFMADDSUB231PSZrk:
27326 case VFMADDSUB231PSZrkz:
27327 case VFMADDSUB231PSm:
27328 case VFMADDSUB231PSr:
27329 return true;
27330 }
27331 return false;
27332}
27333
27334bool isVFNMSUB213PD(unsigned Opcode) {
27335 switch (Opcode) {
27336 case VFNMSUB213PDYm:
27337 case VFNMSUB213PDYr:
27338 case VFNMSUB213PDZ128m:
27339 case VFNMSUB213PDZ128mb:
27340 case VFNMSUB213PDZ128mbk:
27341 case VFNMSUB213PDZ128mbkz:
27342 case VFNMSUB213PDZ128mk:
27343 case VFNMSUB213PDZ128mkz:
27344 case VFNMSUB213PDZ128r:
27345 case VFNMSUB213PDZ128rk:
27346 case VFNMSUB213PDZ128rkz:
27347 case VFNMSUB213PDZ256m:
27348 case VFNMSUB213PDZ256mb:
27349 case VFNMSUB213PDZ256mbk:
27350 case VFNMSUB213PDZ256mbkz:
27351 case VFNMSUB213PDZ256mk:
27352 case VFNMSUB213PDZ256mkz:
27353 case VFNMSUB213PDZ256r:
27354 case VFNMSUB213PDZ256rk:
27355 case VFNMSUB213PDZ256rkz:
27356 case VFNMSUB213PDZm:
27357 case VFNMSUB213PDZmb:
27358 case VFNMSUB213PDZmbk:
27359 case VFNMSUB213PDZmbkz:
27360 case VFNMSUB213PDZmk:
27361 case VFNMSUB213PDZmkz:
27362 case VFNMSUB213PDZr:
27363 case VFNMSUB213PDZrb:
27364 case VFNMSUB213PDZrbk:
27365 case VFNMSUB213PDZrbkz:
27366 case VFNMSUB213PDZrk:
27367 case VFNMSUB213PDZrkz:
27368 case VFNMSUB213PDm:
27369 case VFNMSUB213PDr:
27370 return true;
27371 }
27372 return false;
27373}
27374
27375bool isVPCONFLICTD(unsigned Opcode) {
27376 switch (Opcode) {
27377 case VPCONFLICTDZ128rm:
27378 case VPCONFLICTDZ128rmb:
27379 case VPCONFLICTDZ128rmbk:
27380 case VPCONFLICTDZ128rmbkz:
27381 case VPCONFLICTDZ128rmk:
27382 case VPCONFLICTDZ128rmkz:
27383 case VPCONFLICTDZ128rr:
27384 case VPCONFLICTDZ128rrk:
27385 case VPCONFLICTDZ128rrkz:
27386 case VPCONFLICTDZ256rm:
27387 case VPCONFLICTDZ256rmb:
27388 case VPCONFLICTDZ256rmbk:
27389 case VPCONFLICTDZ256rmbkz:
27390 case VPCONFLICTDZ256rmk:
27391 case VPCONFLICTDZ256rmkz:
27392 case VPCONFLICTDZ256rr:
27393 case VPCONFLICTDZ256rrk:
27394 case VPCONFLICTDZ256rrkz:
27395 case VPCONFLICTDZrm:
27396 case VPCONFLICTDZrmb:
27397 case VPCONFLICTDZrmbk:
27398 case VPCONFLICTDZrmbkz:
27399 case VPCONFLICTDZrmk:
27400 case VPCONFLICTDZrmkz:
27401 case VPCONFLICTDZrr:
27402 case VPCONFLICTDZrrk:
27403 case VPCONFLICTDZrrkz:
27404 return true;
27405 }
27406 return false;
27407}
27408
27409bool isVFMADDSUB213PH(unsigned Opcode) {
27410 switch (Opcode) {
27411 case VFMADDSUB213PHZ128m:
27412 case VFMADDSUB213PHZ128mb:
27413 case VFMADDSUB213PHZ128mbk:
27414 case VFMADDSUB213PHZ128mbkz:
27415 case VFMADDSUB213PHZ128mk:
27416 case VFMADDSUB213PHZ128mkz:
27417 case VFMADDSUB213PHZ128r:
27418 case VFMADDSUB213PHZ128rk:
27419 case VFMADDSUB213PHZ128rkz:
27420 case VFMADDSUB213PHZ256m:
27421 case VFMADDSUB213PHZ256mb:
27422 case VFMADDSUB213PHZ256mbk:
27423 case VFMADDSUB213PHZ256mbkz:
27424 case VFMADDSUB213PHZ256mk:
27425 case VFMADDSUB213PHZ256mkz:
27426 case VFMADDSUB213PHZ256r:
27427 case VFMADDSUB213PHZ256rk:
27428 case VFMADDSUB213PHZ256rkz:
27429 case VFMADDSUB213PHZm:
27430 case VFMADDSUB213PHZmb:
27431 case VFMADDSUB213PHZmbk:
27432 case VFMADDSUB213PHZmbkz:
27433 case VFMADDSUB213PHZmk:
27434 case VFMADDSUB213PHZmkz:
27435 case VFMADDSUB213PHZr:
27436 case VFMADDSUB213PHZrb:
27437 case VFMADDSUB213PHZrbk:
27438 case VFMADDSUB213PHZrbkz:
27439 case VFMADDSUB213PHZrk:
27440 case VFMADDSUB213PHZrkz:
27441 return true;
27442 }
27443 return false;
27444}
27445
27446bool isVPHSUBSW(unsigned Opcode) {
27447 switch (Opcode) {
27448 case VPHSUBSWYrm:
27449 case VPHSUBSWYrr:
27450 case VPHSUBSWrm:
27451 case VPHSUBSWrr:
27452 return true;
27453 }
27454 return false;
27455}
27456
27457bool isPUNPCKHDQ(unsigned Opcode) {
27458 switch (Opcode) {
27459 case MMX_PUNPCKHDQrm:
27460 case MMX_PUNPCKHDQrr:
27461 case PUNPCKHDQrm:
27462 case PUNPCKHDQrr:
27463 return true;
27464 }
27465 return false;
27466}
27467
27468bool isVSHUFI64X2(unsigned Opcode) {
27469 switch (Opcode) {
27470 case VSHUFI64X2Z256rmbi:
27471 case VSHUFI64X2Z256rmbik:
27472 case VSHUFI64X2Z256rmbikz:
27473 case VSHUFI64X2Z256rmi:
27474 case VSHUFI64X2Z256rmik:
27475 case VSHUFI64X2Z256rmikz:
27476 case VSHUFI64X2Z256rri:
27477 case VSHUFI64X2Z256rrik:
27478 case VSHUFI64X2Z256rrikz:
27479 case VSHUFI64X2Zrmbi:
27480 case VSHUFI64X2Zrmbik:
27481 case VSHUFI64X2Zrmbikz:
27482 case VSHUFI64X2Zrmi:
27483 case VSHUFI64X2Zrmik:
27484 case VSHUFI64X2Zrmikz:
27485 case VSHUFI64X2Zrri:
27486 case VSHUFI64X2Zrrik:
27487 case VSHUFI64X2Zrrikz:
27488 return true;
27489 }
27490 return false;
27491}
27492
27493bool isVFMSUBSD(unsigned Opcode) {
27494 switch (Opcode) {
27495 case VFMSUBSD4mr:
27496 case VFMSUBSD4rm:
27497 case VFMSUBSD4rr:
27498 case VFMSUBSD4rr_REV:
27499 return true;
27500 }
27501 return false;
27502}
27503
27504bool isVPORD(unsigned Opcode) {
27505 switch (Opcode) {
27506 case VPORDZ128rm:
27507 case VPORDZ128rmb:
27508 case VPORDZ128rmbk:
27509 case VPORDZ128rmbkz:
27510 case VPORDZ128rmk:
27511 case VPORDZ128rmkz:
27512 case VPORDZ128rr:
27513 case VPORDZ128rrk:
27514 case VPORDZ128rrkz:
27515 case VPORDZ256rm:
27516 case VPORDZ256rmb:
27517 case VPORDZ256rmbk:
27518 case VPORDZ256rmbkz:
27519 case VPORDZ256rmk:
27520 case VPORDZ256rmkz:
27521 case VPORDZ256rr:
27522 case VPORDZ256rrk:
27523 case VPORDZ256rrkz:
27524 case VPORDZrm:
27525 case VPORDZrmb:
27526 case VPORDZrmbk:
27527 case VPORDZrmbkz:
27528 case VPORDZrmk:
27529 case VPORDZrmkz:
27530 case VPORDZrr:
27531 case VPORDZrrk:
27532 case VPORDZrrkz:
27533 return true;
27534 }
27535 return false;
27536}
27537
27538bool isRCPPS(unsigned Opcode) {
27539 switch (Opcode) {
27540 case RCPPSm:
27541 case RCPPSr:
27542 return true;
27543 }
27544 return false;
27545}
27546
27547bool isVEXTRACTI128(unsigned Opcode) {
27548 switch (Opcode) {
27549 case VEXTRACTI128mr:
27550 case VEXTRACTI128rr:
27551 return true;
27552 }
27553 return false;
27554}
27555
27556bool isVPSHRDVW(unsigned Opcode) {
27557 switch (Opcode) {
27558 case VPSHRDVWZ128m:
27559 case VPSHRDVWZ128mk:
27560 case VPSHRDVWZ128mkz:
27561 case VPSHRDVWZ128r:
27562 case VPSHRDVWZ128rk:
27563 case VPSHRDVWZ128rkz:
27564 case VPSHRDVWZ256m:
27565 case VPSHRDVWZ256mk:
27566 case VPSHRDVWZ256mkz:
27567 case VPSHRDVWZ256r:
27568 case VPSHRDVWZ256rk:
27569 case VPSHRDVWZ256rkz:
27570 case VPSHRDVWZm:
27571 case VPSHRDVWZmk:
27572 case VPSHRDVWZmkz:
27573 case VPSHRDVWZr:
27574 case VPSHRDVWZrk:
27575 case VPSHRDVWZrkz:
27576 return true;
27577 }
27578 return false;
27579}
27580
27581bool isVUNPCKLPD(unsigned Opcode) {
27582 switch (Opcode) {
27583 case VUNPCKLPDYrm:
27584 case VUNPCKLPDYrr:
27585 case VUNPCKLPDZ128rm:
27586 case VUNPCKLPDZ128rmb:
27587 case VUNPCKLPDZ128rmbk:
27588 case VUNPCKLPDZ128rmbkz:
27589 case VUNPCKLPDZ128rmk:
27590 case VUNPCKLPDZ128rmkz:
27591 case VUNPCKLPDZ128rr:
27592 case VUNPCKLPDZ128rrk:
27593 case VUNPCKLPDZ128rrkz:
27594 case VUNPCKLPDZ256rm:
27595 case VUNPCKLPDZ256rmb:
27596 case VUNPCKLPDZ256rmbk:
27597 case VUNPCKLPDZ256rmbkz:
27598 case VUNPCKLPDZ256rmk:
27599 case VUNPCKLPDZ256rmkz:
27600 case VUNPCKLPDZ256rr:
27601 case VUNPCKLPDZ256rrk:
27602 case VUNPCKLPDZ256rrkz:
27603 case VUNPCKLPDZrm:
27604 case VUNPCKLPDZrmb:
27605 case VUNPCKLPDZrmbk:
27606 case VUNPCKLPDZrmbkz:
27607 case VUNPCKLPDZrmk:
27608 case VUNPCKLPDZrmkz:
27609 case VUNPCKLPDZrr:
27610 case VUNPCKLPDZrrk:
27611 case VUNPCKLPDZrrkz:
27612 case VUNPCKLPDrm:
27613 case VUNPCKLPDrr:
27614 return true;
27615 }
27616 return false;
27617}
27618
27619bool isVPSRAVD(unsigned Opcode) {
27620 switch (Opcode) {
27621 case VPSRAVDYrm:
27622 case VPSRAVDYrr:
27623 case VPSRAVDZ128rm:
27624 case VPSRAVDZ128rmb:
27625 case VPSRAVDZ128rmbk:
27626 case VPSRAVDZ128rmbkz:
27627 case VPSRAVDZ128rmk:
27628 case VPSRAVDZ128rmkz:
27629 case VPSRAVDZ128rr:
27630 case VPSRAVDZ128rrk:
27631 case VPSRAVDZ128rrkz:
27632 case VPSRAVDZ256rm:
27633 case VPSRAVDZ256rmb:
27634 case VPSRAVDZ256rmbk:
27635 case VPSRAVDZ256rmbkz:
27636 case VPSRAVDZ256rmk:
27637 case VPSRAVDZ256rmkz:
27638 case VPSRAVDZ256rr:
27639 case VPSRAVDZ256rrk:
27640 case VPSRAVDZ256rrkz:
27641 case VPSRAVDZrm:
27642 case VPSRAVDZrmb:
27643 case VPSRAVDZrmbk:
27644 case VPSRAVDZrmbkz:
27645 case VPSRAVDZrmk:
27646 case VPSRAVDZrmkz:
27647 case VPSRAVDZrr:
27648 case VPSRAVDZrrk:
27649 case VPSRAVDZrrkz:
27650 case VPSRAVDrm:
27651 case VPSRAVDrr:
27652 return true;
27653 }
27654 return false;
27655}
27656
27657bool isVMULSH(unsigned Opcode) {
27658 switch (Opcode) {
27659 case VMULSHZrm_Int:
27660 case VMULSHZrm_Intk:
27661 case VMULSHZrm_Intkz:
27662 case VMULSHZrr_Int:
27663 case VMULSHZrr_Intk:
27664 case VMULSHZrr_Intkz:
27665 case VMULSHZrrb_Int:
27666 case VMULSHZrrb_Intk:
27667 case VMULSHZrrb_Intkz:
27668 return true;
27669 }
27670 return false;
27671}
27672
27673bool isMOVNTSS(unsigned Opcode) {
27674 return Opcode == MOVNTSS;
27675}
27676
27677bool isSTI(unsigned Opcode) {
27678 return Opcode == STI;
27679}
27680
27681bool isVSM4RNDS4(unsigned Opcode) {
27682 switch (Opcode) {
27683 case VSM4RNDS4Yrm:
27684 case VSM4RNDS4Yrr:
27685 case VSM4RNDS4rm:
27686 case VSM4RNDS4rr:
27687 return true;
27688 }
27689 return false;
27690}
27691
27692bool isVMCLEAR(unsigned Opcode) {
27693 return Opcode == VMCLEARm;
27694}
27695
27696bool isVPMADD52HUQ(unsigned Opcode) {
27697 switch (Opcode) {
27698 case VPMADD52HUQYrm:
27699 case VPMADD52HUQYrr:
27700 case VPMADD52HUQZ128m:
27701 case VPMADD52HUQZ128mb:
27702 case VPMADD52HUQZ128mbk:
27703 case VPMADD52HUQZ128mbkz:
27704 case VPMADD52HUQZ128mk:
27705 case VPMADD52HUQZ128mkz:
27706 case VPMADD52HUQZ128r:
27707 case VPMADD52HUQZ128rk:
27708 case VPMADD52HUQZ128rkz:
27709 case VPMADD52HUQZ256m:
27710 case VPMADD52HUQZ256mb:
27711 case VPMADD52HUQZ256mbk:
27712 case VPMADD52HUQZ256mbkz:
27713 case VPMADD52HUQZ256mk:
27714 case VPMADD52HUQZ256mkz:
27715 case VPMADD52HUQZ256r:
27716 case VPMADD52HUQZ256rk:
27717 case VPMADD52HUQZ256rkz:
27718 case VPMADD52HUQZm:
27719 case VPMADD52HUQZmb:
27720 case VPMADD52HUQZmbk:
27721 case VPMADD52HUQZmbkz:
27722 case VPMADD52HUQZmk:
27723 case VPMADD52HUQZmkz:
27724 case VPMADD52HUQZr:
27725 case VPMADD52HUQZrk:
27726 case VPMADD52HUQZrkz:
27727 case VPMADD52HUQrm:
27728 case VPMADD52HUQrr:
27729 return true;
27730 }
27731 return false;
27732}
27733
27734bool isLIDT(unsigned Opcode) {
27735 return Opcode == LIDT64m;
27736}
27737
27738bool isPUSH2(unsigned Opcode) {
27739 return Opcode == PUSH2;
27740}
27741
27742bool isRDPKRU(unsigned Opcode) {
27743 return Opcode == RDPKRUr;
27744}
27745
27746bool isVPCMPB(unsigned Opcode) {
27747 switch (Opcode) {
27748 case VPCMPBZ128rmi:
27749 case VPCMPBZ128rmik:
27750 case VPCMPBZ128rri:
27751 case VPCMPBZ128rrik:
27752 case VPCMPBZ256rmi:
27753 case VPCMPBZ256rmik:
27754 case VPCMPBZ256rri:
27755 case VPCMPBZ256rrik:
27756 case VPCMPBZrmi:
27757 case VPCMPBZrmik:
27758 case VPCMPBZrri:
27759 case VPCMPBZrrik:
27760 return true;
27761 }
27762 return false;
27763}
27764
27765bool isFINCSTP(unsigned Opcode) {
27766 return Opcode == FINCSTP;
27767}
27768
27769bool isKORQ(unsigned Opcode) {
27770 return Opcode == KORQrr;
27771}
27772
27773bool isXCRYPTCBC(unsigned Opcode) {
27774 return Opcode == XCRYPTCBC;
27775}
27776
27777bool isRDPMC(unsigned Opcode) {
27778 return Opcode == RDPMC;
27779}
27780
27781bool isMOVMSKPD(unsigned Opcode) {
27782 return Opcode == MOVMSKPDrr;
27783}
27784
27785bool isVFMSUB231SH(unsigned Opcode) {
27786 switch (Opcode) {
27787 case VFMSUB231SHZm_Int:
27788 case VFMSUB231SHZm_Intk:
27789 case VFMSUB231SHZm_Intkz:
27790 case VFMSUB231SHZr_Int:
27791 case VFMSUB231SHZr_Intk:
27792 case VFMSUB231SHZr_Intkz:
27793 case VFMSUB231SHZrb_Int:
27794 case VFMSUB231SHZrb_Intk:
27795 case VFMSUB231SHZrb_Intkz:
27796 return true;
27797 }
27798 return false;
27799}
27800
27801bool isVEXTRACTF128(unsigned Opcode) {
27802 switch (Opcode) {
27803 case VEXTRACTF128mr:
27804 case VEXTRACTF128rr:
27805 return true;
27806 }
27807 return false;
27808}
27809
27810bool isVPSHLB(unsigned Opcode) {
27811 switch (Opcode) {
27812 case VPSHLBmr:
27813 case VPSHLBrm:
27814 case VPSHLBrr:
27815 case VPSHLBrr_REV:
27816 return true;
27817 }
27818 return false;
27819}
27820
27821bool isXSAVES64(unsigned Opcode) {
27822 return Opcode == XSAVES64;
27823}
27824
27825bool isSHL(unsigned Opcode) {
27826 switch (Opcode) {
27827 case SHL16m1:
27828 case SHL16m1_EVEX:
27829 case SHL16m1_ND:
27830 case SHL16m1_NF:
27831 case SHL16m1_NF_ND:
27832 case SHL16mCL:
27833 case SHL16mCL_EVEX:
27834 case SHL16mCL_ND:
27835 case SHL16mCL_NF:
27836 case SHL16mCL_NF_ND:
27837 case SHL16mi:
27838 case SHL16mi_EVEX:
27839 case SHL16mi_ND:
27840 case SHL16mi_NF:
27841 case SHL16mi_NF_ND:
27842 case SHL16r1:
27843 case SHL16r1_EVEX:
27844 case SHL16r1_ND:
27845 case SHL16r1_NF:
27846 case SHL16r1_NF_ND:
27847 case SHL16rCL:
27848 case SHL16rCL_EVEX:
27849 case SHL16rCL_ND:
27850 case SHL16rCL_NF:
27851 case SHL16rCL_NF_ND:
27852 case SHL16ri:
27853 case SHL16ri_EVEX:
27854 case SHL16ri_ND:
27855 case SHL16ri_NF:
27856 case SHL16ri_NF_ND:
27857 case SHL32m1:
27858 case SHL32m1_EVEX:
27859 case SHL32m1_ND:
27860 case SHL32m1_NF:
27861 case SHL32m1_NF_ND:
27862 case SHL32mCL:
27863 case SHL32mCL_EVEX:
27864 case SHL32mCL_ND:
27865 case SHL32mCL_NF:
27866 case SHL32mCL_NF_ND:
27867 case SHL32mi:
27868 case SHL32mi_EVEX:
27869 case SHL32mi_ND:
27870 case SHL32mi_NF:
27871 case SHL32mi_NF_ND:
27872 case SHL32r1:
27873 case SHL32r1_EVEX:
27874 case SHL32r1_ND:
27875 case SHL32r1_NF:
27876 case SHL32r1_NF_ND:
27877 case SHL32rCL:
27878 case SHL32rCL_EVEX:
27879 case SHL32rCL_ND:
27880 case SHL32rCL_NF:
27881 case SHL32rCL_NF_ND:
27882 case SHL32ri:
27883 case SHL32ri_EVEX:
27884 case SHL32ri_ND:
27885 case SHL32ri_NF:
27886 case SHL32ri_NF_ND:
27887 case SHL64m1:
27888 case SHL64m1_EVEX:
27889 case SHL64m1_ND:
27890 case SHL64m1_NF:
27891 case SHL64m1_NF_ND:
27892 case SHL64mCL:
27893 case SHL64mCL_EVEX:
27894 case SHL64mCL_ND:
27895 case SHL64mCL_NF:
27896 case SHL64mCL_NF_ND:
27897 case SHL64mi:
27898 case SHL64mi_EVEX:
27899 case SHL64mi_ND:
27900 case SHL64mi_NF:
27901 case SHL64mi_NF_ND:
27902 case SHL64r1:
27903 case SHL64r1_EVEX:
27904 case SHL64r1_ND:
27905 case SHL64r1_NF:
27906 case SHL64r1_NF_ND:
27907 case SHL64rCL:
27908 case SHL64rCL_EVEX:
27909 case SHL64rCL_ND:
27910 case SHL64rCL_NF:
27911 case SHL64rCL_NF_ND:
27912 case SHL64ri:
27913 case SHL64ri_EVEX:
27914 case SHL64ri_ND:
27915 case SHL64ri_NF:
27916 case SHL64ri_NF_ND:
27917 case SHL8m1:
27918 case SHL8m1_EVEX:
27919 case SHL8m1_ND:
27920 case SHL8m1_NF:
27921 case SHL8m1_NF_ND:
27922 case SHL8mCL:
27923 case SHL8mCL_EVEX:
27924 case SHL8mCL_ND:
27925 case SHL8mCL_NF:
27926 case SHL8mCL_NF_ND:
27927 case SHL8mi:
27928 case SHL8mi_EVEX:
27929 case SHL8mi_ND:
27930 case SHL8mi_NF:
27931 case SHL8mi_NF_ND:
27932 case SHL8r1:
27933 case SHL8r1_EVEX:
27934 case SHL8r1_ND:
27935 case SHL8r1_NF:
27936 case SHL8r1_NF_ND:
27937 case SHL8rCL:
27938 case SHL8rCL_EVEX:
27939 case SHL8rCL_ND:
27940 case SHL8rCL_NF:
27941 case SHL8rCL_NF_ND:
27942 case SHL8ri:
27943 case SHL8ri_EVEX:
27944 case SHL8ri_ND:
27945 case SHL8ri_NF:
27946 case SHL8ri_NF_ND:
27947 return true;
27948 }
27949 return false;
27950}
27951
27952bool isAXOR(unsigned Opcode) {
27953 switch (Opcode) {
27954 case AXOR32mr:
27955 case AXOR32mr_EVEX:
27956 case AXOR64mr:
27957 case AXOR64mr_EVEX:
27958 return true;
27959 }
27960 return false;
27961}
27962
27963bool isVINSERTI64X2(unsigned Opcode) {
27964 switch (Opcode) {
27965 case VINSERTI64x2Z256rm:
27966 case VINSERTI64x2Z256rmk:
27967 case VINSERTI64x2Z256rmkz:
27968 case VINSERTI64x2Z256rr:
27969 case VINSERTI64x2Z256rrk:
27970 case VINSERTI64x2Z256rrkz:
27971 case VINSERTI64x2Zrm:
27972 case VINSERTI64x2Zrmk:
27973 case VINSERTI64x2Zrmkz:
27974 case VINSERTI64x2Zrr:
27975 case VINSERTI64x2Zrrk:
27976 case VINSERTI64x2Zrrkz:
27977 return true;
27978 }
27979 return false;
27980}
27981
27982bool isSYSRETQ(unsigned Opcode) {
27983 return Opcode == SYSRET64;
27984}
27985
27986bool isVSCATTERPF0QPD(unsigned Opcode) {
27987 return Opcode == VSCATTERPF0QPDm;
27988}
27989
27990bool isVFMSUB213SH(unsigned Opcode) {
27991 switch (Opcode) {
27992 case VFMSUB213SHZm_Int:
27993 case VFMSUB213SHZm_Intk:
27994 case VFMSUB213SHZm_Intkz:
27995 case VFMSUB213SHZr_Int:
27996 case VFMSUB213SHZr_Intk:
27997 case VFMSUB213SHZr_Intkz:
27998 case VFMSUB213SHZrb_Int:
27999 case VFMSUB213SHZrb_Intk:
28000 case VFMSUB213SHZrb_Intkz:
28001 return true;
28002 }
28003 return false;
28004}
28005
28006bool isVPMOVQW(unsigned Opcode) {
28007 switch (Opcode) {
28008 case VPMOVQWZ128mr:
28009 case VPMOVQWZ128mrk:
28010 case VPMOVQWZ128rr:
28011 case VPMOVQWZ128rrk:
28012 case VPMOVQWZ128rrkz:
28013 case VPMOVQWZ256mr:
28014 case VPMOVQWZ256mrk:
28015 case VPMOVQWZ256rr:
28016 case VPMOVQWZ256rrk:
28017 case VPMOVQWZ256rrkz:
28018 case VPMOVQWZmr:
28019 case VPMOVQWZmrk:
28020 case VPMOVQWZrr:
28021 case VPMOVQWZrrk:
28022 case VPMOVQWZrrkz:
28023 return true;
28024 }
28025 return false;
28026}
28027
28028bool isVREDUCEPD(unsigned Opcode) {
28029 switch (Opcode) {
28030 case VREDUCEPDZ128rmbi:
28031 case VREDUCEPDZ128rmbik:
28032 case VREDUCEPDZ128rmbikz:
28033 case VREDUCEPDZ128rmi:
28034 case VREDUCEPDZ128rmik:
28035 case VREDUCEPDZ128rmikz:
28036 case VREDUCEPDZ128rri:
28037 case VREDUCEPDZ128rrik:
28038 case VREDUCEPDZ128rrikz:
28039 case VREDUCEPDZ256rmbi:
28040 case VREDUCEPDZ256rmbik:
28041 case VREDUCEPDZ256rmbikz:
28042 case VREDUCEPDZ256rmi:
28043 case VREDUCEPDZ256rmik:
28044 case VREDUCEPDZ256rmikz:
28045 case VREDUCEPDZ256rri:
28046 case VREDUCEPDZ256rrik:
28047 case VREDUCEPDZ256rrikz:
28048 case VREDUCEPDZrmbi:
28049 case VREDUCEPDZrmbik:
28050 case VREDUCEPDZrmbikz:
28051 case VREDUCEPDZrmi:
28052 case VREDUCEPDZrmik:
28053 case VREDUCEPDZrmikz:
28054 case VREDUCEPDZrri:
28055 case VREDUCEPDZrrib:
28056 case VREDUCEPDZrribk:
28057 case VREDUCEPDZrribkz:
28058 case VREDUCEPDZrrik:
28059 case VREDUCEPDZrrikz:
28060 return true;
28061 }
28062 return false;
28063}
28064
28065bool isNOT(unsigned Opcode) {
28066 switch (Opcode) {
28067 case NOT16m:
28068 case NOT16m_EVEX:
28069 case NOT16m_ND:
28070 case NOT16r:
28071 case NOT16r_EVEX:
28072 case NOT16r_ND:
28073 case NOT32m:
28074 case NOT32m_EVEX:
28075 case NOT32m_ND:
28076 case NOT32r:
28077 case NOT32r_EVEX:
28078 case NOT32r_ND:
28079 case NOT64m:
28080 case NOT64m_EVEX:
28081 case NOT64m_ND:
28082 case NOT64r:
28083 case NOT64r_EVEX:
28084 case NOT64r_ND:
28085 case NOT8m:
28086 case NOT8m_EVEX:
28087 case NOT8m_ND:
28088 case NOT8r:
28089 case NOT8r_EVEX:
28090 case NOT8r_ND:
28091 return true;
28092 }
28093 return false;
28094}
28095
28096bool isLWPINS(unsigned Opcode) {
28097 switch (Opcode) {
28098 case LWPINS32rmi:
28099 case LWPINS32rri:
28100 case LWPINS64rmi:
28101 case LWPINS64rri:
28102 return true;
28103 }
28104 return false;
28105}
28106
28107bool isVSCATTERDPS(unsigned Opcode) {
28108 switch (Opcode) {
28109 case VSCATTERDPSZ128mr:
28110 case VSCATTERDPSZ256mr:
28111 case VSCATTERDPSZmr:
28112 return true;
28113 }
28114 return false;
28115}
28116
28117bool isVPMOVM2W(unsigned Opcode) {
28118 switch (Opcode) {
28119 case VPMOVM2WZ128rr:
28120 case VPMOVM2WZ256rr:
28121 case VPMOVM2WZrr:
28122 return true;
28123 }
28124 return false;
28125}
28126
28127bool isVFNMADD132PS(unsigned Opcode) {
28128 switch (Opcode) {
28129 case VFNMADD132PSYm:
28130 case VFNMADD132PSYr:
28131 case VFNMADD132PSZ128m:
28132 case VFNMADD132PSZ128mb:
28133 case VFNMADD132PSZ128mbk:
28134 case VFNMADD132PSZ128mbkz:
28135 case VFNMADD132PSZ128mk:
28136 case VFNMADD132PSZ128mkz:
28137 case VFNMADD132PSZ128r:
28138 case VFNMADD132PSZ128rk:
28139 case VFNMADD132PSZ128rkz:
28140 case VFNMADD132PSZ256m:
28141 case VFNMADD132PSZ256mb:
28142 case VFNMADD132PSZ256mbk:
28143 case VFNMADD132PSZ256mbkz:
28144 case VFNMADD132PSZ256mk:
28145 case VFNMADD132PSZ256mkz:
28146 case VFNMADD132PSZ256r:
28147 case VFNMADD132PSZ256rk:
28148 case VFNMADD132PSZ256rkz:
28149 case VFNMADD132PSZm:
28150 case VFNMADD132PSZmb:
28151 case VFNMADD132PSZmbk:
28152 case VFNMADD132PSZmbkz:
28153 case VFNMADD132PSZmk:
28154 case VFNMADD132PSZmkz:
28155 case VFNMADD132PSZr:
28156 case VFNMADD132PSZrb:
28157 case VFNMADD132PSZrbk:
28158 case VFNMADD132PSZrbkz:
28159 case VFNMADD132PSZrk:
28160 case VFNMADD132PSZrkz:
28161 case VFNMADD132PSm:
28162 case VFNMADD132PSr:
28163 return true;
28164 }
28165 return false;
28166}
28167
28168bool isMOVNTPS(unsigned Opcode) {
28169 return Opcode == MOVNTPSmr;
28170}
28171
28172bool isVRSQRTSS(unsigned Opcode) {
28173 switch (Opcode) {
28174 case VRSQRTSSm_Int:
28175 case VRSQRTSSr_Int:
28176 return true;
28177 }
28178 return false;
28179}
28180
28181bool isKMOVB(unsigned Opcode) {
28182 switch (Opcode) {
28183 case KMOVBkk:
28184 case KMOVBkk_EVEX:
28185 case KMOVBkm:
28186 case KMOVBkm_EVEX:
28187 case KMOVBkr:
28188 case KMOVBkr_EVEX:
28189 case KMOVBmk:
28190 case KMOVBmk_EVEX:
28191 case KMOVBrk:
28192 case KMOVBrk_EVEX:
28193 return true;
28194 }
28195 return false;
28196}
28197
28198bool isCVTSD2SS(unsigned Opcode) {
28199 switch (Opcode) {
28200 case CVTSD2SSrm_Int:
28201 case CVTSD2SSrr_Int:
28202 return true;
28203 }
28204 return false;
28205}
28206
28207bool isVBROADCASTF64X2(unsigned Opcode) {
28208 switch (Opcode) {
28209 case VBROADCASTF64X2Z128rm:
28210 case VBROADCASTF64X2Z128rmk:
28211 case VBROADCASTF64X2Z128rmkz:
28212 case VBROADCASTF64X2rm:
28213 case VBROADCASTF64X2rmk:
28214 case VBROADCASTF64X2rmkz:
28215 return true;
28216 }
28217 return false;
28218}
28219
28220bool isMOVNTPD(unsigned Opcode) {
28221 return Opcode == MOVNTPDmr;
28222}
28223
28224bool isMAXSD(unsigned Opcode) {
28225 switch (Opcode) {
28226 case MAXSDrm_Int:
28227 case MAXSDrr_Int:
28228 return true;
28229 }
28230 return false;
28231}
28232
28233bool isCMPPD(unsigned Opcode) {
28234 switch (Opcode) {
28235 case CMPPDrmi:
28236 case CMPPDrri:
28237 return true;
28238 }
28239 return false;
28240}
28241
28242bool isVPCMPESTRM(unsigned Opcode) {
28243 switch (Opcode) {
28244 case VPCMPESTRMrmi:
28245 case VPCMPESTRMrri:
28246 return true;
28247 }
28248 return false;
28249}
28250
28251bool isVFMSUB132PS(unsigned Opcode) {
28252 switch (Opcode) {
28253 case VFMSUB132PSYm:
28254 case VFMSUB132PSYr:
28255 case VFMSUB132PSZ128m:
28256 case VFMSUB132PSZ128mb:
28257 case VFMSUB132PSZ128mbk:
28258 case VFMSUB132PSZ128mbkz:
28259 case VFMSUB132PSZ128mk:
28260 case VFMSUB132PSZ128mkz:
28261 case VFMSUB132PSZ128r:
28262 case VFMSUB132PSZ128rk:
28263 case VFMSUB132PSZ128rkz:
28264 case VFMSUB132PSZ256m:
28265 case VFMSUB132PSZ256mb:
28266 case VFMSUB132PSZ256mbk:
28267 case VFMSUB132PSZ256mbkz:
28268 case VFMSUB132PSZ256mk:
28269 case VFMSUB132PSZ256mkz:
28270 case VFMSUB132PSZ256r:
28271 case VFMSUB132PSZ256rk:
28272 case VFMSUB132PSZ256rkz:
28273 case VFMSUB132PSZm:
28274 case VFMSUB132PSZmb:
28275 case VFMSUB132PSZmbk:
28276 case VFMSUB132PSZmbkz:
28277 case VFMSUB132PSZmk:
28278 case VFMSUB132PSZmkz:
28279 case VFMSUB132PSZr:
28280 case VFMSUB132PSZrb:
28281 case VFMSUB132PSZrbk:
28282 case VFMSUB132PSZrbkz:
28283 case VFMSUB132PSZrk:
28284 case VFMSUB132PSZrkz:
28285 case VFMSUB132PSm:
28286 case VFMSUB132PSr:
28287 return true;
28288 }
28289 return false;
28290}
28291
28292bool isVCOMISH(unsigned Opcode) {
28293 switch (Opcode) {
28294 case VCOMISHZrm:
28295 case VCOMISHZrr:
28296 case VCOMISHZrrb:
28297 return true;
28298 }
28299 return false;
28300}
28301
28302bool isF2XM1(unsigned Opcode) {
28303 return Opcode == F2XM1;
28304}
28305
28306bool isSQRTPD(unsigned Opcode) {
28307 switch (Opcode) {
28308 case SQRTPDm:
28309 case SQRTPDr:
28310 return true;
28311 }
28312 return false;
28313}
28314
28315bool isVFMSUBADDPS(unsigned Opcode) {
28316 switch (Opcode) {
28317 case VFMSUBADDPS4Ymr:
28318 case VFMSUBADDPS4Yrm:
28319 case VFMSUBADDPS4Yrr:
28320 case VFMSUBADDPS4Yrr_REV:
28321 case VFMSUBADDPS4mr:
28322 case VFMSUBADDPS4rm:
28323 case VFMSUBADDPS4rr:
28324 case VFMSUBADDPS4rr_REV:
28325 return true;
28326 }
28327 return false;
28328}
28329
28330bool isFXTRACT(unsigned Opcode) {
28331 return Opcode == FXTRACT;
28332}
28333
28334bool isVP4DPWSSD(unsigned Opcode) {
28335 switch (Opcode) {
28336 case VP4DPWSSDrm:
28337 case VP4DPWSSDrmk:
28338 case VP4DPWSSDrmkz:
28339 return true;
28340 }
28341 return false;
28342}
28343
28344bool isVFMSUBADDPD(unsigned Opcode) {
28345 switch (Opcode) {
28346 case VFMSUBADDPD4Ymr:
28347 case VFMSUBADDPD4Yrm:
28348 case VFMSUBADDPD4Yrr:
28349 case VFMSUBADDPD4Yrr_REV:
28350 case VFMSUBADDPD4mr:
28351 case VFMSUBADDPD4rm:
28352 case VFMSUBADDPD4rr:
28353 case VFMSUBADDPD4rr_REV:
28354 return true;
28355 }
28356 return false;
28357}
28358
28359bool isVBCSTNEBF162PS(unsigned Opcode) {
28360 switch (Opcode) {
28361 case VBCSTNEBF162PSYrm:
28362 case VBCSTNEBF162PSrm:
28363 return true;
28364 }
28365 return false;
28366}
28367
28368bool isVPGATHERQQ(unsigned Opcode) {
28369 switch (Opcode) {
28370 case VPGATHERQQYrm:
28371 case VPGATHERQQZ128rm:
28372 case VPGATHERQQZ256rm:
28373 case VPGATHERQQZrm:
28374 case VPGATHERQQrm:
28375 return true;
28376 }
28377 return false;
28378}
28379
28380bool isPCMPEQB(unsigned Opcode) {
28381 switch (Opcode) {
28382 case MMX_PCMPEQBrm:
28383 case MMX_PCMPEQBrr:
28384 case PCMPEQBrm:
28385 case PCMPEQBrr:
28386 return true;
28387 }
28388 return false;
28389}
28390
28391bool isTILESTORED(unsigned Opcode) {
28392 switch (Opcode) {
28393 case TILESTORED:
28394 case TILESTORED_EVEX:
28395 return true;
28396 }
28397 return false;
28398}
28399
28400bool isBLSMSK(unsigned Opcode) {
28401 switch (Opcode) {
28402 case BLSMSK32rm:
28403 case BLSMSK32rm_EVEX:
28404 case BLSMSK32rm_NF:
28405 case BLSMSK32rr:
28406 case BLSMSK32rr_EVEX:
28407 case BLSMSK32rr_NF:
28408 case BLSMSK64rm:
28409 case BLSMSK64rm_EVEX:
28410 case BLSMSK64rm_NF:
28411 case BLSMSK64rr:
28412 case BLSMSK64rr_EVEX:
28413 case BLSMSK64rr_NF:
28414 return true;
28415 }
28416 return false;
28417}
28418
28419bool isVCVTTPS2DQ(unsigned Opcode) {
28420 switch (Opcode) {
28421 case VCVTTPS2DQYrm:
28422 case VCVTTPS2DQYrr:
28423 case VCVTTPS2DQZ128rm:
28424 case VCVTTPS2DQZ128rmb:
28425 case VCVTTPS2DQZ128rmbk:
28426 case VCVTTPS2DQZ128rmbkz:
28427 case VCVTTPS2DQZ128rmk:
28428 case VCVTTPS2DQZ128rmkz:
28429 case VCVTTPS2DQZ128rr:
28430 case VCVTTPS2DQZ128rrk:
28431 case VCVTTPS2DQZ128rrkz:
28432 case VCVTTPS2DQZ256rm:
28433 case VCVTTPS2DQZ256rmb:
28434 case VCVTTPS2DQZ256rmbk:
28435 case VCVTTPS2DQZ256rmbkz:
28436 case VCVTTPS2DQZ256rmk:
28437 case VCVTTPS2DQZ256rmkz:
28438 case VCVTTPS2DQZ256rr:
28439 case VCVTTPS2DQZ256rrk:
28440 case VCVTTPS2DQZ256rrkz:
28441 case VCVTTPS2DQZrm:
28442 case VCVTTPS2DQZrmb:
28443 case VCVTTPS2DQZrmbk:
28444 case VCVTTPS2DQZrmbkz:
28445 case VCVTTPS2DQZrmk:
28446 case VCVTTPS2DQZrmkz:
28447 case VCVTTPS2DQZrr:
28448 case VCVTTPS2DQZrrb:
28449 case VCVTTPS2DQZrrbk:
28450 case VCVTTPS2DQZrrbkz:
28451 case VCVTTPS2DQZrrk:
28452 case VCVTTPS2DQZrrkz:
28453 case VCVTTPS2DQrm:
28454 case VCVTTPS2DQrr:
28455 return true;
28456 }
28457 return false;
28458}
28459
28460bool isVRNDSCALEPD(unsigned Opcode) {
28461 switch (Opcode) {
28462 case VRNDSCALEPDZ128rmbi:
28463 case VRNDSCALEPDZ128rmbik:
28464 case VRNDSCALEPDZ128rmbikz:
28465 case VRNDSCALEPDZ128rmi:
28466 case VRNDSCALEPDZ128rmik:
28467 case VRNDSCALEPDZ128rmikz:
28468 case VRNDSCALEPDZ128rri:
28469 case VRNDSCALEPDZ128rrik:
28470 case VRNDSCALEPDZ128rrikz:
28471 case VRNDSCALEPDZ256rmbi:
28472 case VRNDSCALEPDZ256rmbik:
28473 case VRNDSCALEPDZ256rmbikz:
28474 case VRNDSCALEPDZ256rmi:
28475 case VRNDSCALEPDZ256rmik:
28476 case VRNDSCALEPDZ256rmikz:
28477 case VRNDSCALEPDZ256rri:
28478 case VRNDSCALEPDZ256rrik:
28479 case VRNDSCALEPDZ256rrikz:
28480 case VRNDSCALEPDZrmbi:
28481 case VRNDSCALEPDZrmbik:
28482 case VRNDSCALEPDZrmbikz:
28483 case VRNDSCALEPDZrmi:
28484 case VRNDSCALEPDZrmik:
28485 case VRNDSCALEPDZrmikz:
28486 case VRNDSCALEPDZrri:
28487 case VRNDSCALEPDZrrib:
28488 case VRNDSCALEPDZrribk:
28489 case VRNDSCALEPDZrribkz:
28490 case VRNDSCALEPDZrrik:
28491 case VRNDSCALEPDZrrikz:
28492 return true;
28493 }
28494 return false;
28495}
28496
28497bool isVMLOAD(unsigned Opcode) {
28498 switch (Opcode) {
28499 case VMLOAD32:
28500 case VMLOAD64:
28501 return true;
28502 }
28503 return false;
28504}
28505
28506bool isVPTERNLOGQ(unsigned Opcode) {
28507 switch (Opcode) {
28508 case VPTERNLOGQZ128rmbi:
28509 case VPTERNLOGQZ128rmbik:
28510 case VPTERNLOGQZ128rmbikz:
28511 case VPTERNLOGQZ128rmi:
28512 case VPTERNLOGQZ128rmik:
28513 case VPTERNLOGQZ128rmikz:
28514 case VPTERNLOGQZ128rri:
28515 case VPTERNLOGQZ128rrik:
28516 case VPTERNLOGQZ128rrikz:
28517 case VPTERNLOGQZ256rmbi:
28518 case VPTERNLOGQZ256rmbik:
28519 case VPTERNLOGQZ256rmbikz:
28520 case VPTERNLOGQZ256rmi:
28521 case VPTERNLOGQZ256rmik:
28522 case VPTERNLOGQZ256rmikz:
28523 case VPTERNLOGQZ256rri:
28524 case VPTERNLOGQZ256rrik:
28525 case VPTERNLOGQZ256rrikz:
28526 case VPTERNLOGQZrmbi:
28527 case VPTERNLOGQZrmbik:
28528 case VPTERNLOGQZrmbikz:
28529 case VPTERNLOGQZrmi:
28530 case VPTERNLOGQZrmik:
28531 case VPTERNLOGQZrmikz:
28532 case VPTERNLOGQZrri:
28533 case VPTERNLOGQZrrik:
28534 case VPTERNLOGQZrrikz:
28535 return true;
28536 }
28537 return false;
28538}
28539
28540bool isKXNORD(unsigned Opcode) {
28541 return Opcode == KXNORDrr;
28542}
28543
28544bool isFXSAVE(unsigned Opcode) {
28545 return Opcode == FXSAVE;
28546}
28547
28548bool isVUNPCKHPD(unsigned Opcode) {
28549 switch (Opcode) {
28550 case VUNPCKHPDYrm:
28551 case VUNPCKHPDYrr:
28552 case VUNPCKHPDZ128rm:
28553 case VUNPCKHPDZ128rmb:
28554 case VUNPCKHPDZ128rmbk:
28555 case VUNPCKHPDZ128rmbkz:
28556 case VUNPCKHPDZ128rmk:
28557 case VUNPCKHPDZ128rmkz:
28558 case VUNPCKHPDZ128rr:
28559 case VUNPCKHPDZ128rrk:
28560 case VUNPCKHPDZ128rrkz:
28561 case VUNPCKHPDZ256rm:
28562 case VUNPCKHPDZ256rmb:
28563 case VUNPCKHPDZ256rmbk:
28564 case VUNPCKHPDZ256rmbkz:
28565 case VUNPCKHPDZ256rmk:
28566 case VUNPCKHPDZ256rmkz:
28567 case VUNPCKHPDZ256rr:
28568 case VUNPCKHPDZ256rrk:
28569 case VUNPCKHPDZ256rrkz:
28570 case VUNPCKHPDZrm:
28571 case VUNPCKHPDZrmb:
28572 case VUNPCKHPDZrmbk:
28573 case VUNPCKHPDZrmbkz:
28574 case VUNPCKHPDZrmk:
28575 case VUNPCKHPDZrmkz:
28576 case VUNPCKHPDZrr:
28577 case VUNPCKHPDZrrk:
28578 case VUNPCKHPDZrrkz:
28579 case VUNPCKHPDrm:
28580 case VUNPCKHPDrr:
28581 return true;
28582 }
28583 return false;
28584}
28585
28586bool isCVTPS2DQ(unsigned Opcode) {
28587 switch (Opcode) {
28588 case CVTPS2DQrm:
28589 case CVTPS2DQrr:
28590 return true;
28591 }
28592 return false;
28593}
28594
28595bool isVFMSUB213SS(unsigned Opcode) {
28596 switch (Opcode) {
28597 case VFMSUB213SSZm_Int:
28598 case VFMSUB213SSZm_Intk:
28599 case VFMSUB213SSZm_Intkz:
28600 case VFMSUB213SSZr_Int:
28601 case VFMSUB213SSZr_Intk:
28602 case VFMSUB213SSZr_Intkz:
28603 case VFMSUB213SSZrb_Int:
28604 case VFMSUB213SSZrb_Intk:
28605 case VFMSUB213SSZrb_Intkz:
28606 case VFMSUB213SSm_Int:
28607 case VFMSUB213SSr_Int:
28608 return true;
28609 }
28610 return false;
28611}
28612
28613bool isVPOPCNTD(unsigned Opcode) {
28614 switch (Opcode) {
28615 case VPOPCNTDZ128rm:
28616 case VPOPCNTDZ128rmb:
28617 case VPOPCNTDZ128rmbk:
28618 case VPOPCNTDZ128rmbkz:
28619 case VPOPCNTDZ128rmk:
28620 case VPOPCNTDZ128rmkz:
28621 case VPOPCNTDZ128rr:
28622 case VPOPCNTDZ128rrk:
28623 case VPOPCNTDZ128rrkz:
28624 case VPOPCNTDZ256rm:
28625 case VPOPCNTDZ256rmb:
28626 case VPOPCNTDZ256rmbk:
28627 case VPOPCNTDZ256rmbkz:
28628 case VPOPCNTDZ256rmk:
28629 case VPOPCNTDZ256rmkz:
28630 case VPOPCNTDZ256rr:
28631 case VPOPCNTDZ256rrk:
28632 case VPOPCNTDZ256rrkz:
28633 case VPOPCNTDZrm:
28634 case VPOPCNTDZrmb:
28635 case VPOPCNTDZrmbk:
28636 case VPOPCNTDZrmbkz:
28637 case VPOPCNTDZrmk:
28638 case VPOPCNTDZrmkz:
28639 case VPOPCNTDZrr:
28640 case VPOPCNTDZrrk:
28641 case VPOPCNTDZrrkz:
28642 return true;
28643 }
28644 return false;
28645}
28646
28647bool isSALC(unsigned Opcode) {
28648 return Opcode == SALC;
28649}
28650
28651bool isV4FNMADDSS(unsigned Opcode) {
28652 switch (Opcode) {
28653 case V4FNMADDSSrm:
28654 case V4FNMADDSSrmk:
28655 case V4FNMADDSSrmkz:
28656 return true;
28657 }
28658 return false;
28659}
28660
28661bool isXCRYPTOFB(unsigned Opcode) {
28662 return Opcode == XCRYPTOFB;
28663}
28664
28665bool isVORPD(unsigned Opcode) {
28666 switch (Opcode) {
28667 case VORPDYrm:
28668 case VORPDYrr:
28669 case VORPDZ128rm:
28670 case VORPDZ128rmb:
28671 case VORPDZ128rmbk:
28672 case VORPDZ128rmbkz:
28673 case VORPDZ128rmk:
28674 case VORPDZ128rmkz:
28675 case VORPDZ128rr:
28676 case VORPDZ128rrk:
28677 case VORPDZ128rrkz:
28678 case VORPDZ256rm:
28679 case VORPDZ256rmb:
28680 case VORPDZ256rmbk:
28681 case VORPDZ256rmbkz:
28682 case VORPDZ256rmk:
28683 case VORPDZ256rmkz:
28684 case VORPDZ256rr:
28685 case VORPDZ256rrk:
28686 case VORPDZ256rrkz:
28687 case VORPDZrm:
28688 case VORPDZrmb:
28689 case VORPDZrmbk:
28690 case VORPDZrmbkz:
28691 case VORPDZrmk:
28692 case VORPDZrmkz:
28693 case VORPDZrr:
28694 case VORPDZrrk:
28695 case VORPDZrrkz:
28696 case VORPDrm:
28697 case VORPDrr:
28698 return true;
28699 }
28700 return false;
28701}
28702
28703bool isLSL(unsigned Opcode) {
28704 switch (Opcode) {
28705 case LSL16rm:
28706 case LSL16rr:
28707 case LSL32rm:
28708 case LSL32rr:
28709 case LSL64rm:
28710 case LSL64rr:
28711 return true;
28712 }
28713 return false;
28714}
28715
28716bool isXCRYPTCFB(unsigned Opcode) {
28717 return Opcode == XCRYPTCFB;
28718}
28719
28720bool isVGETEXPSS(unsigned Opcode) {
28721 switch (Opcode) {
28722 case VGETEXPSSZm:
28723 case VGETEXPSSZmk:
28724 case VGETEXPSSZmkz:
28725 case VGETEXPSSZr:
28726 case VGETEXPSSZrb:
28727 case VGETEXPSSZrbk:
28728 case VGETEXPSSZrbkz:
28729 case VGETEXPSSZrk:
28730 case VGETEXPSSZrkz:
28731 return true;
28732 }
28733 return false;
28734}
28735
28736bool isPSLLDQ(unsigned Opcode) {
28737 return Opcode == PSLLDQri;
28738}
28739
28740bool isVPDPBUUD(unsigned Opcode) {
28741 switch (Opcode) {
28742 case VPDPBUUDYrm:
28743 case VPDPBUUDYrr:
28744 case VPDPBUUDrm:
28745 case VPDPBUUDrr:
28746 return true;
28747 }
28748 return false;
28749}
28750
28751bool isVMXOFF(unsigned Opcode) {
28752 return Opcode == VMXOFF;
28753}
28754
28755bool isBLSIC(unsigned Opcode) {
28756 switch (Opcode) {
28757 case BLSIC32rm:
28758 case BLSIC32rr:
28759 case BLSIC64rm:
28760 case BLSIC64rr:
28761 return true;
28762 }
28763 return false;
28764}
28765
28766bool isMOVLHPS(unsigned Opcode) {
28767 return Opcode == MOVLHPSrr;
28768}
28769
28770bool isVFNMSUBSD(unsigned Opcode) {
28771 switch (Opcode) {
28772 case VFNMSUBSD4mr:
28773 case VFNMSUBSD4rm:
28774 case VFNMSUBSD4rr:
28775 case VFNMSUBSD4rr_REV:
28776 return true;
28777 }
28778 return false;
28779}
28780
28781bool isVFPCLASSSH(unsigned Opcode) {
28782 switch (Opcode) {
28783 case VFPCLASSSHZrm:
28784 case VFPCLASSSHZrmk:
28785 case VFPCLASSSHZrr:
28786 case VFPCLASSSHZrrk:
28787 return true;
28788 }
28789 return false;
28790}
28791
28792bool isVPSHLQ(unsigned Opcode) {
28793 switch (Opcode) {
28794 case VPSHLQmr:
28795 case VPSHLQrm:
28796 case VPSHLQrr:
28797 case VPSHLQrr_REV:
28798 return true;
28799 }
28800 return false;
28801}
28802
28803bool isVROUNDPS(unsigned Opcode) {
28804 switch (Opcode) {
28805 case VROUNDPSYmi:
28806 case VROUNDPSYri:
28807 case VROUNDPSmi:
28808 case VROUNDPSri:
28809 return true;
28810 }
28811 return false;
28812}
28813
28814bool isVSCATTERPF0QPS(unsigned Opcode) {
28815 return Opcode == VSCATTERPF0QPSm;
28816}
28817
28818bool isERETS(unsigned Opcode) {
28819 return Opcode == ERETS;
28820}
28821
28822bool isVPERMI2D(unsigned Opcode) {
28823 switch (Opcode) {
28824 case VPERMI2DZ128rm:
28825 case VPERMI2DZ128rmb:
28826 case VPERMI2DZ128rmbk:
28827 case VPERMI2DZ128rmbkz:
28828 case VPERMI2DZ128rmk:
28829 case VPERMI2DZ128rmkz:
28830 case VPERMI2DZ128rr:
28831 case VPERMI2DZ128rrk:
28832 case VPERMI2DZ128rrkz:
28833 case VPERMI2DZ256rm:
28834 case VPERMI2DZ256rmb:
28835 case VPERMI2DZ256rmbk:
28836 case VPERMI2DZ256rmbkz:
28837 case VPERMI2DZ256rmk:
28838 case VPERMI2DZ256rmkz:
28839 case VPERMI2DZ256rr:
28840 case VPERMI2DZ256rrk:
28841 case VPERMI2DZ256rrkz:
28842 case VPERMI2DZrm:
28843 case VPERMI2DZrmb:
28844 case VPERMI2DZrmbk:
28845 case VPERMI2DZrmbkz:
28846 case VPERMI2DZrmk:
28847 case VPERMI2DZrmkz:
28848 case VPERMI2DZrr:
28849 case VPERMI2DZrrk:
28850 case VPERMI2DZrrkz:
28851 return true;
28852 }
28853 return false;
28854}
28855
28856bool isFUCOMP(unsigned Opcode) {
28857 return Opcode == UCOM_FPr;
28858}
28859
28860bool isVCVTTPS2QQ(unsigned Opcode) {
28861 switch (Opcode) {
28862 case VCVTTPS2QQZ128rm:
28863 case VCVTTPS2QQZ128rmb:
28864 case VCVTTPS2QQZ128rmbk:
28865 case VCVTTPS2QQZ128rmbkz:
28866 case VCVTTPS2QQZ128rmk:
28867 case VCVTTPS2QQZ128rmkz:
28868 case VCVTTPS2QQZ128rr:
28869 case VCVTTPS2QQZ128rrk:
28870 case VCVTTPS2QQZ128rrkz:
28871 case VCVTTPS2QQZ256rm:
28872 case VCVTTPS2QQZ256rmb:
28873 case VCVTTPS2QQZ256rmbk:
28874 case VCVTTPS2QQZ256rmbkz:
28875 case VCVTTPS2QQZ256rmk:
28876 case VCVTTPS2QQZ256rmkz:
28877 case VCVTTPS2QQZ256rr:
28878 case VCVTTPS2QQZ256rrk:
28879 case VCVTTPS2QQZ256rrkz:
28880 case VCVTTPS2QQZrm:
28881 case VCVTTPS2QQZrmb:
28882 case VCVTTPS2QQZrmbk:
28883 case VCVTTPS2QQZrmbkz:
28884 case VCVTTPS2QQZrmk:
28885 case VCVTTPS2QQZrmkz:
28886 case VCVTTPS2QQZrr:
28887 case VCVTTPS2QQZrrb:
28888 case VCVTTPS2QQZrrbk:
28889 case VCVTTPS2QQZrrbkz:
28890 case VCVTTPS2QQZrrk:
28891 case VCVTTPS2QQZrrkz:
28892 return true;
28893 }
28894 return false;
28895}
28896
28897bool isPUSHFD(unsigned Opcode) {
28898 return Opcode == PUSHF32;
28899}
28900
28901bool isKORB(unsigned Opcode) {
28902 return Opcode == KORBrr;
28903}
28904
28905bool isVRCP28PD(unsigned Opcode) {
28906 switch (Opcode) {
28907 case VRCP28PDZm:
28908 case VRCP28PDZmb:
28909 case VRCP28PDZmbk:
28910 case VRCP28PDZmbkz:
28911 case VRCP28PDZmk:
28912 case VRCP28PDZmkz:
28913 case VRCP28PDZr:
28914 case VRCP28PDZrb:
28915 case VRCP28PDZrbk:
28916 case VRCP28PDZrbkz:
28917 case VRCP28PDZrk:
28918 case VRCP28PDZrkz:
28919 return true;
28920 }
28921 return false;
28922}
28923
28924bool isVPABSD(unsigned Opcode) {
28925 switch (Opcode) {
28926 case VPABSDYrm:
28927 case VPABSDYrr:
28928 case VPABSDZ128rm:
28929 case VPABSDZ128rmb:
28930 case VPABSDZ128rmbk:
28931 case VPABSDZ128rmbkz:
28932 case VPABSDZ128rmk:
28933 case VPABSDZ128rmkz:
28934 case VPABSDZ128rr:
28935 case VPABSDZ128rrk:
28936 case VPABSDZ128rrkz:
28937 case VPABSDZ256rm:
28938 case VPABSDZ256rmb:
28939 case VPABSDZ256rmbk:
28940 case VPABSDZ256rmbkz:
28941 case VPABSDZ256rmk:
28942 case VPABSDZ256rmkz:
28943 case VPABSDZ256rr:
28944 case VPABSDZ256rrk:
28945 case VPABSDZ256rrkz:
28946 case VPABSDZrm:
28947 case VPABSDZrmb:
28948 case VPABSDZrmbk:
28949 case VPABSDZrmbkz:
28950 case VPABSDZrmk:
28951 case VPABSDZrmkz:
28952 case VPABSDZrr:
28953 case VPABSDZrrk:
28954 case VPABSDZrrkz:
28955 case VPABSDrm:
28956 case VPABSDrr:
28957 return true;
28958 }
28959 return false;
28960}
28961
28962bool isVROUNDSS(unsigned Opcode) {
28963 switch (Opcode) {
28964 case VROUNDSSmi_Int:
28965 case VROUNDSSri_Int:
28966 return true;
28967 }
28968 return false;
28969}
28970
28971bool isVCVTSD2USI(unsigned Opcode) {
28972 switch (Opcode) {
28973 case VCVTSD2USI64Zrm_Int:
28974 case VCVTSD2USI64Zrr_Int:
28975 case VCVTSD2USI64Zrrb_Int:
28976 case VCVTSD2USIZrm_Int:
28977 case VCVTSD2USIZrr_Int:
28978 case VCVTSD2USIZrrb_Int:
28979 return true;
28980 }
28981 return false;
28982}
28983
28984bool isVPABSB(unsigned Opcode) {
28985 switch (Opcode) {
28986 case VPABSBYrm:
28987 case VPABSBYrr:
28988 case VPABSBZ128rm:
28989 case VPABSBZ128rmk:
28990 case VPABSBZ128rmkz:
28991 case VPABSBZ128rr:
28992 case VPABSBZ128rrk:
28993 case VPABSBZ128rrkz:
28994 case VPABSBZ256rm:
28995 case VPABSBZ256rmk:
28996 case VPABSBZ256rmkz:
28997 case VPABSBZ256rr:
28998 case VPABSBZ256rrk:
28999 case VPABSBZ256rrkz:
29000 case VPABSBZrm:
29001 case VPABSBZrmk:
29002 case VPABSBZrmkz:
29003 case VPABSBZrr:
29004 case VPABSBZrrk:
29005 case VPABSBZrrkz:
29006 case VPABSBrm:
29007 case VPABSBrr:
29008 return true;
29009 }
29010 return false;
29011}
29012
29013bool isPMAXUD(unsigned Opcode) {
29014 switch (Opcode) {
29015 case PMAXUDrm:
29016 case PMAXUDrr:
29017 return true;
29018 }
29019 return false;
29020}
29021
29022bool isVPMULHUW(unsigned Opcode) {
29023 switch (Opcode) {
29024 case VPMULHUWYrm:
29025 case VPMULHUWYrr:
29026 case VPMULHUWZ128rm:
29027 case VPMULHUWZ128rmk:
29028 case VPMULHUWZ128rmkz:
29029 case VPMULHUWZ128rr:
29030 case VPMULHUWZ128rrk:
29031 case VPMULHUWZ128rrkz:
29032 case VPMULHUWZ256rm:
29033 case VPMULHUWZ256rmk:
29034 case VPMULHUWZ256rmkz:
29035 case VPMULHUWZ256rr:
29036 case VPMULHUWZ256rrk:
29037 case VPMULHUWZ256rrkz:
29038 case VPMULHUWZrm:
29039 case VPMULHUWZrmk:
29040 case VPMULHUWZrmkz:
29041 case VPMULHUWZrr:
29042 case VPMULHUWZrrk:
29043 case VPMULHUWZrrkz:
29044 case VPMULHUWrm:
29045 case VPMULHUWrr:
29046 return true;
29047 }
29048 return false;
29049}
29050
29051bool isVPERMPD(unsigned Opcode) {
29052 switch (Opcode) {
29053 case VPERMPDYmi:
29054 case VPERMPDYri:
29055 case VPERMPDZ256mbi:
29056 case VPERMPDZ256mbik:
29057 case VPERMPDZ256mbikz:
29058 case VPERMPDZ256mi:
29059 case VPERMPDZ256mik:
29060 case VPERMPDZ256mikz:
29061 case VPERMPDZ256ri:
29062 case VPERMPDZ256rik:
29063 case VPERMPDZ256rikz:
29064 case VPERMPDZ256rm:
29065 case VPERMPDZ256rmb:
29066 case VPERMPDZ256rmbk:
29067 case VPERMPDZ256rmbkz:
29068 case VPERMPDZ256rmk:
29069 case VPERMPDZ256rmkz:
29070 case VPERMPDZ256rr:
29071 case VPERMPDZ256rrk:
29072 case VPERMPDZ256rrkz:
29073 case VPERMPDZmbi:
29074 case VPERMPDZmbik:
29075 case VPERMPDZmbikz:
29076 case VPERMPDZmi:
29077 case VPERMPDZmik:
29078 case VPERMPDZmikz:
29079 case VPERMPDZri:
29080 case VPERMPDZrik:
29081 case VPERMPDZrikz:
29082 case VPERMPDZrm:
29083 case VPERMPDZrmb:
29084 case VPERMPDZrmbk:
29085 case VPERMPDZrmbkz:
29086 case VPERMPDZrmk:
29087 case VPERMPDZrmkz:
29088 case VPERMPDZrr:
29089 case VPERMPDZrrk:
29090 case VPERMPDZrrkz:
29091 return true;
29092 }
29093 return false;
29094}
29095
29096bool isFCHS(unsigned Opcode) {
29097 return Opcode == CHS_F;
29098}
29099
29100bool isVPBLENDMB(unsigned Opcode) {
29101 switch (Opcode) {
29102 case VPBLENDMBZ128rm:
29103 case VPBLENDMBZ128rmk:
29104 case VPBLENDMBZ128rmkz:
29105 case VPBLENDMBZ128rr:
29106 case VPBLENDMBZ128rrk:
29107 case VPBLENDMBZ128rrkz:
29108 case VPBLENDMBZ256rm:
29109 case VPBLENDMBZ256rmk:
29110 case VPBLENDMBZ256rmkz:
29111 case VPBLENDMBZ256rr:
29112 case VPBLENDMBZ256rrk:
29113 case VPBLENDMBZ256rrkz:
29114 case VPBLENDMBZrm:
29115 case VPBLENDMBZrmk:
29116 case VPBLENDMBZrmkz:
29117 case VPBLENDMBZrr:
29118 case VPBLENDMBZrrk:
29119 case VPBLENDMBZrrkz:
29120 return true;
29121 }
29122 return false;
29123}
29124
29125bool isVGETMANTSS(unsigned Opcode) {
29126 switch (Opcode) {
29127 case VGETMANTSSZrmi:
29128 case VGETMANTSSZrmik:
29129 case VGETMANTSSZrmikz:
29130 case VGETMANTSSZrri:
29131 case VGETMANTSSZrrib:
29132 case VGETMANTSSZrribk:
29133 case VGETMANTSSZrribkz:
29134 case VGETMANTSSZrrik:
29135 case VGETMANTSSZrrikz:
29136 return true;
29137 }
29138 return false;
29139}
29140
29141bool isVPSLLW(unsigned Opcode) {
29142 switch (Opcode) {
29143 case VPSLLWYri:
29144 case VPSLLWYrm:
29145 case VPSLLWYrr:
29146 case VPSLLWZ128mi:
29147 case VPSLLWZ128mik:
29148 case VPSLLWZ128mikz:
29149 case VPSLLWZ128ri:
29150 case VPSLLWZ128rik:
29151 case VPSLLWZ128rikz:
29152 case VPSLLWZ128rm:
29153 case VPSLLWZ128rmk:
29154 case VPSLLWZ128rmkz:
29155 case VPSLLWZ128rr:
29156 case VPSLLWZ128rrk:
29157 case VPSLLWZ128rrkz:
29158 case VPSLLWZ256mi:
29159 case VPSLLWZ256mik:
29160 case VPSLLWZ256mikz:
29161 case VPSLLWZ256ri:
29162 case VPSLLWZ256rik:
29163 case VPSLLWZ256rikz:
29164 case VPSLLWZ256rm:
29165 case VPSLLWZ256rmk:
29166 case VPSLLWZ256rmkz:
29167 case VPSLLWZ256rr:
29168 case VPSLLWZ256rrk:
29169 case VPSLLWZ256rrkz:
29170 case VPSLLWZmi:
29171 case VPSLLWZmik:
29172 case VPSLLWZmikz:
29173 case VPSLLWZri:
29174 case VPSLLWZrik:
29175 case VPSLLWZrikz:
29176 case VPSLLWZrm:
29177 case VPSLLWZrmk:
29178 case VPSLLWZrmkz:
29179 case VPSLLWZrr:
29180 case VPSLLWZrrk:
29181 case VPSLLWZrrkz:
29182 case VPSLLWri:
29183 case VPSLLWrm:
29184 case VPSLLWrr:
29185 return true;
29186 }
29187 return false;
29188}
29189
29190bool isVDIVPD(unsigned Opcode) {
29191 switch (Opcode) {
29192 case VDIVPDYrm:
29193 case VDIVPDYrr:
29194 case VDIVPDZ128rm:
29195 case VDIVPDZ128rmb:
29196 case VDIVPDZ128rmbk:
29197 case VDIVPDZ128rmbkz:
29198 case VDIVPDZ128rmk:
29199 case VDIVPDZ128rmkz:
29200 case VDIVPDZ128rr:
29201 case VDIVPDZ128rrk:
29202 case VDIVPDZ128rrkz:
29203 case VDIVPDZ256rm:
29204 case VDIVPDZ256rmb:
29205 case VDIVPDZ256rmbk:
29206 case VDIVPDZ256rmbkz:
29207 case VDIVPDZ256rmk:
29208 case VDIVPDZ256rmkz:
29209 case VDIVPDZ256rr:
29210 case VDIVPDZ256rrk:
29211 case VDIVPDZ256rrkz:
29212 case VDIVPDZrm:
29213 case VDIVPDZrmb:
29214 case VDIVPDZrmbk:
29215 case VDIVPDZrmbkz:
29216 case VDIVPDZrmk:
29217 case VDIVPDZrmkz:
29218 case VDIVPDZrr:
29219 case VDIVPDZrrb:
29220 case VDIVPDZrrbk:
29221 case VDIVPDZrrbkz:
29222 case VDIVPDZrrk:
29223 case VDIVPDZrrkz:
29224 case VDIVPDrm:
29225 case VDIVPDrr:
29226 return true;
29227 }
29228 return false;
29229}
29230
29231bool isBLCMSK(unsigned Opcode) {
29232 switch (Opcode) {
29233 case BLCMSK32rm:
29234 case BLCMSK32rr:
29235 case BLCMSK64rm:
29236 case BLCMSK64rr:
29237 return true;
29238 }
29239 return false;
29240}
29241
29242bool isFDIV(unsigned Opcode) {
29243 switch (Opcode) {
29244 case DIV_F32m:
29245 case DIV_F64m:
29246 case DIV_FST0r:
29247 case DIV_FrST0:
29248 return true;
29249 }
29250 return false;
29251}
29252
29253bool isRSQRTSS(unsigned Opcode) {
29254 switch (Opcode) {
29255 case RSQRTSSm_Int:
29256 case RSQRTSSr_Int:
29257 return true;
29258 }
29259 return false;
29260}
29261
29262bool isPOR(unsigned Opcode) {
29263 switch (Opcode) {
29264 case MMX_PORrm:
29265 case MMX_PORrr:
29266 case PORrm:
29267 case PORrr:
29268 return true;
29269 }
29270 return false;
29271}
29272
29273bool isVMOVDQA32(unsigned Opcode) {
29274 switch (Opcode) {
29275 case VMOVDQA32Z128mr:
29276 case VMOVDQA32Z128mrk:
29277 case VMOVDQA32Z128rm:
29278 case VMOVDQA32Z128rmk:
29279 case VMOVDQA32Z128rmkz:
29280 case VMOVDQA32Z128rr:
29281 case VMOVDQA32Z128rr_REV:
29282 case VMOVDQA32Z128rrk:
29283 case VMOVDQA32Z128rrk_REV:
29284 case VMOVDQA32Z128rrkz:
29285 case VMOVDQA32Z128rrkz_REV:
29286 case VMOVDQA32Z256mr:
29287 case VMOVDQA32Z256mrk:
29288 case VMOVDQA32Z256rm:
29289 case VMOVDQA32Z256rmk:
29290 case VMOVDQA32Z256rmkz:
29291 case VMOVDQA32Z256rr:
29292 case VMOVDQA32Z256rr_REV:
29293 case VMOVDQA32Z256rrk:
29294 case VMOVDQA32Z256rrk_REV:
29295 case VMOVDQA32Z256rrkz:
29296 case VMOVDQA32Z256rrkz_REV:
29297 case VMOVDQA32Zmr:
29298 case VMOVDQA32Zmrk:
29299 case VMOVDQA32Zrm:
29300 case VMOVDQA32Zrmk:
29301 case VMOVDQA32Zrmkz:
29302 case VMOVDQA32Zrr:
29303 case VMOVDQA32Zrr_REV:
29304 case VMOVDQA32Zrrk:
29305 case VMOVDQA32Zrrk_REV:
29306 case VMOVDQA32Zrrkz:
29307 case VMOVDQA32Zrrkz_REV:
29308 return true;
29309 }
29310 return false;
29311}
29312
29313bool isVPHADDUWQ(unsigned Opcode) {
29314 switch (Opcode) {
29315 case VPHADDUWQrm:
29316 case VPHADDUWQrr:
29317 return true;
29318 }
29319 return false;
29320}
29321
29322bool isPSRAD(unsigned Opcode) {
29323 switch (Opcode) {
29324 case MMX_PSRADri:
29325 case MMX_PSRADrm:
29326 case MMX_PSRADrr:
29327 case PSRADri:
29328 case PSRADrm:
29329 case PSRADrr:
29330 return true;
29331 }
29332 return false;
29333}
29334
29335bool isPREFETCHW(unsigned Opcode) {
29336 return Opcode == PREFETCHW;
29337}
29338
29339bool isFIDIVR(unsigned Opcode) {
29340 switch (Opcode) {
29341 case DIVR_FI16m:
29342 case DIVR_FI32m:
29343 return true;
29344 }
29345 return false;
29346}
29347
29348bool isMOVHPS(unsigned Opcode) {
29349 switch (Opcode) {
29350 case MOVHPSmr:
29351 case MOVHPSrm:
29352 return true;
29353 }
29354 return false;
29355}
29356
29357bool isVFNMSUB231PH(unsigned Opcode) {
29358 switch (Opcode) {
29359 case VFNMSUB231PHZ128m:
29360 case VFNMSUB231PHZ128mb:
29361 case VFNMSUB231PHZ128mbk:
29362 case VFNMSUB231PHZ128mbkz:
29363 case VFNMSUB231PHZ128mk:
29364 case VFNMSUB231PHZ128mkz:
29365 case VFNMSUB231PHZ128r:
29366 case VFNMSUB231PHZ128rk:
29367 case VFNMSUB231PHZ128rkz:
29368 case VFNMSUB231PHZ256m:
29369 case VFNMSUB231PHZ256mb:
29370 case VFNMSUB231PHZ256mbk:
29371 case VFNMSUB231PHZ256mbkz:
29372 case VFNMSUB231PHZ256mk:
29373 case VFNMSUB231PHZ256mkz:
29374 case VFNMSUB231PHZ256r:
29375 case VFNMSUB231PHZ256rk:
29376 case VFNMSUB231PHZ256rkz:
29377 case VFNMSUB231PHZm:
29378 case VFNMSUB231PHZmb:
29379 case VFNMSUB231PHZmbk:
29380 case VFNMSUB231PHZmbkz:
29381 case VFNMSUB231PHZmk:
29382 case VFNMSUB231PHZmkz:
29383 case VFNMSUB231PHZr:
29384 case VFNMSUB231PHZrb:
29385 case VFNMSUB231PHZrbk:
29386 case VFNMSUB231PHZrbkz:
29387 case VFNMSUB231PHZrk:
29388 case VFNMSUB231PHZrkz:
29389 return true;
29390 }
29391 return false;
29392}
29393
29394bool isUNPCKLPS(unsigned Opcode) {
29395 switch (Opcode) {
29396 case UNPCKLPSrm:
29397 case UNPCKLPSrr:
29398 return true;
29399 }
29400 return false;
29401}
29402
29403bool isVPSIGNB(unsigned Opcode) {
29404 switch (Opcode) {
29405 case VPSIGNBYrm:
29406 case VPSIGNBYrr:
29407 case VPSIGNBrm:
29408 case VPSIGNBrr:
29409 return true;
29410 }
29411 return false;
29412}
29413
29414bool isSAVEPREVSSP(unsigned Opcode) {
29415 return Opcode == SAVEPREVSSP;
29416}
29417
29418bool isVSCALEFSD(unsigned Opcode) {
29419 switch (Opcode) {
29420 case VSCALEFSDZrm:
29421 case VSCALEFSDZrmk:
29422 case VSCALEFSDZrmkz:
29423 case VSCALEFSDZrr:
29424 case VSCALEFSDZrrb_Int:
29425 case VSCALEFSDZrrb_Intk:
29426 case VSCALEFSDZrrb_Intkz:
29427 case VSCALEFSDZrrk:
29428 case VSCALEFSDZrrkz:
29429 return true;
29430 }
29431 return false;
29432}
29433
29434bool isFSIN(unsigned Opcode) {
29435 return Opcode == FSIN;
29436}
29437
29438bool isSCASQ(unsigned Opcode) {
29439 return Opcode == SCASQ;
29440}
29441
29442bool isPCMPGTW(unsigned Opcode) {
29443 switch (Opcode) {
29444 case MMX_PCMPGTWrm:
29445 case MMX_PCMPGTWrr:
29446 case PCMPGTWrm:
29447 case PCMPGTWrr:
29448 return true;
29449 }
29450 return false;
29451}
29452
29453bool isMULX(unsigned Opcode) {
29454 switch (Opcode) {
29455 case MULX32rm:
29456 case MULX32rm_EVEX:
29457 case MULX32rr:
29458 case MULX32rr_EVEX:
29459 case MULX64rm:
29460 case MULX64rm_EVEX:
29461 case MULX64rr:
29462 case MULX64rr_EVEX:
29463 return true;
29464 }
29465 return false;
29466}
29467
29468bool isVPMAXUW(unsigned Opcode) {
29469 switch (Opcode) {
29470 case VPMAXUWYrm:
29471 case VPMAXUWYrr:
29472 case VPMAXUWZ128rm:
29473 case VPMAXUWZ128rmk:
29474 case VPMAXUWZ128rmkz:
29475 case VPMAXUWZ128rr:
29476 case VPMAXUWZ128rrk:
29477 case VPMAXUWZ128rrkz:
29478 case VPMAXUWZ256rm:
29479 case VPMAXUWZ256rmk:
29480 case VPMAXUWZ256rmkz:
29481 case VPMAXUWZ256rr:
29482 case VPMAXUWZ256rrk:
29483 case VPMAXUWZ256rrkz:
29484 case VPMAXUWZrm:
29485 case VPMAXUWZrmk:
29486 case VPMAXUWZrmkz:
29487 case VPMAXUWZrr:
29488 case VPMAXUWZrrk:
29489 case VPMAXUWZrrkz:
29490 case VPMAXUWrm:
29491 case VPMAXUWrr:
29492 return true;
29493 }
29494 return false;
29495}
29496
29497bool isPAUSE(unsigned Opcode) {
29498 return Opcode == PAUSE;
29499}
29500
29501bool isMOVQ2DQ(unsigned Opcode) {
29502 return Opcode == MMX_MOVQ2DQrr;
29503}
29504
29505bool isVPSUBQ(unsigned Opcode) {
29506 switch (Opcode) {
29507 case VPSUBQYrm:
29508 case VPSUBQYrr:
29509 case VPSUBQZ128rm:
29510 case VPSUBQZ128rmb:
29511 case VPSUBQZ128rmbk:
29512 case VPSUBQZ128rmbkz:
29513 case VPSUBQZ128rmk:
29514 case VPSUBQZ128rmkz:
29515 case VPSUBQZ128rr:
29516 case VPSUBQZ128rrk:
29517 case VPSUBQZ128rrkz:
29518 case VPSUBQZ256rm:
29519 case VPSUBQZ256rmb:
29520 case VPSUBQZ256rmbk:
29521 case VPSUBQZ256rmbkz:
29522 case VPSUBQZ256rmk:
29523 case VPSUBQZ256rmkz:
29524 case VPSUBQZ256rr:
29525 case VPSUBQZ256rrk:
29526 case VPSUBQZ256rrkz:
29527 case VPSUBQZrm:
29528 case VPSUBQZrmb:
29529 case VPSUBQZrmbk:
29530 case VPSUBQZrmbkz:
29531 case VPSUBQZrmk:
29532 case VPSUBQZrmkz:
29533 case VPSUBQZrr:
29534 case VPSUBQZrrk:
29535 case VPSUBQZrrkz:
29536 case VPSUBQrm:
29537 case VPSUBQrr:
29538 return true;
29539 }
29540 return false;
29541}
29542
29543bool isVPABSW(unsigned Opcode) {
29544 switch (Opcode) {
29545 case VPABSWYrm:
29546 case VPABSWYrr:
29547 case VPABSWZ128rm:
29548 case VPABSWZ128rmk:
29549 case VPABSWZ128rmkz:
29550 case VPABSWZ128rr:
29551 case VPABSWZ128rrk:
29552 case VPABSWZ128rrkz:
29553 case VPABSWZ256rm:
29554 case VPABSWZ256rmk:
29555 case VPABSWZ256rmkz:
29556 case VPABSWZ256rr:
29557 case VPABSWZ256rrk:
29558 case VPABSWZ256rrkz:
29559 case VPABSWZrm:
29560 case VPABSWZrmk:
29561 case VPABSWZrmkz:
29562 case VPABSWZrr:
29563 case VPABSWZrrk:
29564 case VPABSWZrrkz:
29565 case VPABSWrm:
29566 case VPABSWrr:
29567 return true;
29568 }
29569 return false;
29570}
29571
29572bool isVPCOMPRESSD(unsigned Opcode) {
29573 switch (Opcode) {
29574 case VPCOMPRESSDZ128mr:
29575 case VPCOMPRESSDZ128mrk:
29576 case VPCOMPRESSDZ128rr:
29577 case VPCOMPRESSDZ128rrk:
29578 case VPCOMPRESSDZ128rrkz:
29579 case VPCOMPRESSDZ256mr:
29580 case VPCOMPRESSDZ256mrk:
29581 case VPCOMPRESSDZ256rr:
29582 case VPCOMPRESSDZ256rrk:
29583 case VPCOMPRESSDZ256rrkz:
29584 case VPCOMPRESSDZmr:
29585 case VPCOMPRESSDZmrk:
29586 case VPCOMPRESSDZrr:
29587 case VPCOMPRESSDZrrk:
29588 case VPCOMPRESSDZrrkz:
29589 return true;
29590 }
29591 return false;
29592}
29593
29594bool isVPMOVUSQW(unsigned Opcode) {
29595 switch (Opcode) {
29596 case VPMOVUSQWZ128mr:
29597 case VPMOVUSQWZ128mrk:
29598 case VPMOVUSQWZ128rr:
29599 case VPMOVUSQWZ128rrk:
29600 case VPMOVUSQWZ128rrkz:
29601 case VPMOVUSQWZ256mr:
29602 case VPMOVUSQWZ256mrk:
29603 case VPMOVUSQWZ256rr:
29604 case VPMOVUSQWZ256rrk:
29605 case VPMOVUSQWZ256rrkz:
29606 case VPMOVUSQWZmr:
29607 case VPMOVUSQWZmrk:
29608 case VPMOVUSQWZrr:
29609 case VPMOVUSQWZrrk:
29610 case VPMOVUSQWZrrkz:
29611 return true;
29612 }
29613 return false;
29614}
29615
29616bool isBLENDVPD(unsigned Opcode) {
29617 switch (Opcode) {
29618 case BLENDVPDrm0:
29619 case BLENDVPDrr0:
29620 return true;
29621 }
29622 return false;
29623}
29624
29625bool isVPMOVQB(unsigned Opcode) {
29626 switch (Opcode) {
29627 case VPMOVQBZ128mr:
29628 case VPMOVQBZ128mrk:
29629 case VPMOVQBZ128rr:
29630 case VPMOVQBZ128rrk:
29631 case VPMOVQBZ128rrkz:
29632 case VPMOVQBZ256mr:
29633 case VPMOVQBZ256mrk:
29634 case VPMOVQBZ256rr:
29635 case VPMOVQBZ256rrk:
29636 case VPMOVQBZ256rrkz:
29637 case VPMOVQBZmr:
29638 case VPMOVQBZmrk:
29639 case VPMOVQBZrr:
29640 case VPMOVQBZrrk:
29641 case VPMOVQBZrrkz:
29642 return true;
29643 }
29644 return false;
29645}
29646
29647bool isVBLENDVPS(unsigned Opcode) {
29648 switch (Opcode) {
29649 case VBLENDVPSYrmr:
29650 case VBLENDVPSYrrr:
29651 case VBLENDVPSrmr:
29652 case VBLENDVPSrrr:
29653 return true;
29654 }
29655 return false;
29656}
29657
29658bool isKSHIFTLQ(unsigned Opcode) {
29659 return Opcode == KSHIFTLQri;
29660}
29661
29662bool isPMOVSXWD(unsigned Opcode) {
29663 switch (Opcode) {
29664 case PMOVSXWDrm:
29665 case PMOVSXWDrr:
29666 return true;
29667 }
29668 return false;
29669}
29670
29671bool isPHSUBSW(unsigned Opcode) {
29672 switch (Opcode) {
29673 case MMX_PHSUBSWrm:
29674 case MMX_PHSUBSWrr:
29675 case PHSUBSWrm:
29676 case PHSUBSWrr:
29677 return true;
29678 }
29679 return false;
29680}
29681
29682bool isPSRLQ(unsigned Opcode) {
29683 switch (Opcode) {
29684 case MMX_PSRLQri:
29685 case MMX_PSRLQrm:
29686 case MMX_PSRLQrr:
29687 case PSRLQri:
29688 case PSRLQrm:
29689 case PSRLQrr:
29690 return true;
29691 }
29692 return false;
29693}
29694
29695bool isVCVTPH2DQ(unsigned Opcode) {
29696 switch (Opcode) {
29697 case VCVTPH2DQZ128rm:
29698 case VCVTPH2DQZ128rmb:
29699 case VCVTPH2DQZ128rmbk:
29700 case VCVTPH2DQZ128rmbkz:
29701 case VCVTPH2DQZ128rmk:
29702 case VCVTPH2DQZ128rmkz:
29703 case VCVTPH2DQZ128rr:
29704 case VCVTPH2DQZ128rrk:
29705 case VCVTPH2DQZ128rrkz:
29706 case VCVTPH2DQZ256rm:
29707 case VCVTPH2DQZ256rmb:
29708 case VCVTPH2DQZ256rmbk:
29709 case VCVTPH2DQZ256rmbkz:
29710 case VCVTPH2DQZ256rmk:
29711 case VCVTPH2DQZ256rmkz:
29712 case VCVTPH2DQZ256rr:
29713 case VCVTPH2DQZ256rrk:
29714 case VCVTPH2DQZ256rrkz:
29715 case VCVTPH2DQZrm:
29716 case VCVTPH2DQZrmb:
29717 case VCVTPH2DQZrmbk:
29718 case VCVTPH2DQZrmbkz:
29719 case VCVTPH2DQZrmk:
29720 case VCVTPH2DQZrmkz:
29721 case VCVTPH2DQZrr:
29722 case VCVTPH2DQZrrb:
29723 case VCVTPH2DQZrrbk:
29724 case VCVTPH2DQZrrbkz:
29725 case VCVTPH2DQZrrk:
29726 case VCVTPH2DQZrrkz:
29727 return true;
29728 }
29729 return false;
29730}
29731
29732bool isFISUB(unsigned Opcode) {
29733 switch (Opcode) {
29734 case SUB_FI16m:
29735 case SUB_FI32m:
29736 return true;
29737 }
29738 return false;
29739}
29740
29741bool isVCVTPS2UDQ(unsigned Opcode) {
29742 switch (Opcode) {
29743 case VCVTPS2UDQZ128rm:
29744 case VCVTPS2UDQZ128rmb:
29745 case VCVTPS2UDQZ128rmbk:
29746 case VCVTPS2UDQZ128rmbkz:
29747 case VCVTPS2UDQZ128rmk:
29748 case VCVTPS2UDQZ128rmkz:
29749 case VCVTPS2UDQZ128rr:
29750 case VCVTPS2UDQZ128rrk:
29751 case VCVTPS2UDQZ128rrkz:
29752 case VCVTPS2UDQZ256rm:
29753 case VCVTPS2UDQZ256rmb:
29754 case VCVTPS2UDQZ256rmbk:
29755 case VCVTPS2UDQZ256rmbkz:
29756 case VCVTPS2UDQZ256rmk:
29757 case VCVTPS2UDQZ256rmkz:
29758 case VCVTPS2UDQZ256rr:
29759 case VCVTPS2UDQZ256rrk:
29760 case VCVTPS2UDQZ256rrkz:
29761 case VCVTPS2UDQZrm:
29762 case VCVTPS2UDQZrmb:
29763 case VCVTPS2UDQZrmbk:
29764 case VCVTPS2UDQZrmbkz:
29765 case VCVTPS2UDQZrmk:
29766 case VCVTPS2UDQZrmkz:
29767 case VCVTPS2UDQZrr:
29768 case VCVTPS2UDQZrrb:
29769 case VCVTPS2UDQZrrbk:
29770 case VCVTPS2UDQZrrbkz:
29771 case VCVTPS2UDQZrrk:
29772 case VCVTPS2UDQZrrkz:
29773 return true;
29774 }
29775 return false;
29776}
29777
29778bool isVMOVDDUP(unsigned Opcode) {
29779 switch (Opcode) {
29780 case VMOVDDUPYrm:
29781 case VMOVDDUPYrr:
29782 case VMOVDDUPZ128rm:
29783 case VMOVDDUPZ128rmk:
29784 case VMOVDDUPZ128rmkz:
29785 case VMOVDDUPZ128rr:
29786 case VMOVDDUPZ128rrk:
29787 case VMOVDDUPZ128rrkz:
29788 case VMOVDDUPZ256rm:
29789 case VMOVDDUPZ256rmk:
29790 case VMOVDDUPZ256rmkz:
29791 case VMOVDDUPZ256rr:
29792 case VMOVDDUPZ256rrk:
29793 case VMOVDDUPZ256rrkz:
29794 case VMOVDDUPZrm:
29795 case VMOVDDUPZrmk:
29796 case VMOVDDUPZrmkz:
29797 case VMOVDDUPZrr:
29798 case VMOVDDUPZrrk:
29799 case VMOVDDUPZrrkz:
29800 case VMOVDDUPrm:
29801 case VMOVDDUPrr:
29802 return true;
29803 }
29804 return false;
29805}
29806
29807bool isPCMPEQD(unsigned Opcode) {
29808 switch (Opcode) {
29809 case MMX_PCMPEQDrm:
29810 case MMX_PCMPEQDrr:
29811 case PCMPEQDrm:
29812 case PCMPEQDrr:
29813 return true;
29814 }
29815 return false;
29816}
29817
29818bool isVRSQRT28SD(unsigned Opcode) {
29819 switch (Opcode) {
29820 case VRSQRT28SDZm:
29821 case VRSQRT28SDZmk:
29822 case VRSQRT28SDZmkz:
29823 case VRSQRT28SDZr:
29824 case VRSQRT28SDZrb:
29825 case VRSQRT28SDZrbk:
29826 case VRSQRT28SDZrbkz:
29827 case VRSQRT28SDZrk:
29828 case VRSQRT28SDZrkz:
29829 return true;
29830 }
29831 return false;
29832}
29833
29834bool isLODSW(unsigned Opcode) {
29835 return Opcode == LODSW;
29836}
29837
29838bool isVPOPCNTQ(unsigned Opcode) {
29839 switch (Opcode) {
29840 case VPOPCNTQZ128rm:
29841 case VPOPCNTQZ128rmb:
29842 case VPOPCNTQZ128rmbk:
29843 case VPOPCNTQZ128rmbkz:
29844 case VPOPCNTQZ128rmk:
29845 case VPOPCNTQZ128rmkz:
29846 case VPOPCNTQZ128rr:
29847 case VPOPCNTQZ128rrk:
29848 case VPOPCNTQZ128rrkz:
29849 case VPOPCNTQZ256rm:
29850 case VPOPCNTQZ256rmb:
29851 case VPOPCNTQZ256rmbk:
29852 case VPOPCNTQZ256rmbkz:
29853 case VPOPCNTQZ256rmk:
29854 case VPOPCNTQZ256rmkz:
29855 case VPOPCNTQZ256rr:
29856 case VPOPCNTQZ256rrk:
29857 case VPOPCNTQZ256rrkz:
29858 case VPOPCNTQZrm:
29859 case VPOPCNTQZrmb:
29860 case VPOPCNTQZrmbk:
29861 case VPOPCNTQZrmbkz:
29862 case VPOPCNTQZrmk:
29863 case VPOPCNTQZrmkz:
29864 case VPOPCNTQZrr:
29865 case VPOPCNTQZrrk:
29866 case VPOPCNTQZrrkz:
29867 return true;
29868 }
29869 return false;
29870}
29871
29872bool isKSHIFTRB(unsigned Opcode) {
29873 return Opcode == KSHIFTRBri;
29874}
29875
29876bool isVFNMADDPS(unsigned Opcode) {
29877 switch (Opcode) {
29878 case VFNMADDPS4Ymr:
29879 case VFNMADDPS4Yrm:
29880 case VFNMADDPS4Yrr:
29881 case VFNMADDPS4Yrr_REV:
29882 case VFNMADDPS4mr:
29883 case VFNMADDPS4rm:
29884 case VFNMADDPS4rr:
29885 case VFNMADDPS4rr_REV:
29886 return true;
29887 }
29888 return false;
29889}
29890
29891bool isCCMPCC(unsigned Opcode) {
29892 switch (Opcode) {
29893 case CCMP16mi:
29894 case CCMP16mi8:
29895 case CCMP16mr:
29896 case CCMP16ri:
29897 case CCMP16ri8:
29898 case CCMP16rm:
29899 case CCMP16rr:
29900 case CCMP16rr_REV:
29901 case CCMP32mi:
29902 case CCMP32mi8:
29903 case CCMP32mr:
29904 case CCMP32ri:
29905 case CCMP32ri8:
29906 case CCMP32rm:
29907 case CCMP32rr:
29908 case CCMP32rr_REV:
29909 case CCMP64mi32:
29910 case CCMP64mi8:
29911 case CCMP64mr:
29912 case CCMP64ri32:
29913 case CCMP64ri8:
29914 case CCMP64rm:
29915 case CCMP64rr:
29916 case CCMP64rr_REV:
29917 case CCMP8mi:
29918 case CCMP8mr:
29919 case CCMP8ri:
29920 case CCMP8rm:
29921 case CCMP8rr:
29922 case CCMP8rr_REV:
29923 return true;
29924 }
29925 return false;
29926}
29927
29928bool isFXRSTOR64(unsigned Opcode) {
29929 return Opcode == FXRSTOR64;
29930}
29931
29932bool isVFMSUBADD213PD(unsigned Opcode) {
29933 switch (Opcode) {
29934 case VFMSUBADD213PDYm:
29935 case VFMSUBADD213PDYr:
29936 case VFMSUBADD213PDZ128m:
29937 case VFMSUBADD213PDZ128mb:
29938 case VFMSUBADD213PDZ128mbk:
29939 case VFMSUBADD213PDZ128mbkz:
29940 case VFMSUBADD213PDZ128mk:
29941 case VFMSUBADD213PDZ128mkz:
29942 case VFMSUBADD213PDZ128r:
29943 case VFMSUBADD213PDZ128rk:
29944 case VFMSUBADD213PDZ128rkz:
29945 case VFMSUBADD213PDZ256m:
29946 case VFMSUBADD213PDZ256mb:
29947 case VFMSUBADD213PDZ256mbk:
29948 case VFMSUBADD213PDZ256mbkz:
29949 case VFMSUBADD213PDZ256mk:
29950 case VFMSUBADD213PDZ256mkz:
29951 case VFMSUBADD213PDZ256r:
29952 case VFMSUBADD213PDZ256rk:
29953 case VFMSUBADD213PDZ256rkz:
29954 case VFMSUBADD213PDZm:
29955 case VFMSUBADD213PDZmb:
29956 case VFMSUBADD213PDZmbk:
29957 case VFMSUBADD213PDZmbkz:
29958 case VFMSUBADD213PDZmk:
29959 case VFMSUBADD213PDZmkz:
29960 case VFMSUBADD213PDZr:
29961 case VFMSUBADD213PDZrb:
29962 case VFMSUBADD213PDZrbk:
29963 case VFMSUBADD213PDZrbkz:
29964 case VFMSUBADD213PDZrk:
29965 case VFMSUBADD213PDZrkz:
29966 case VFMSUBADD213PDm:
29967 case VFMSUBADD213PDr:
29968 return true;
29969 }
29970 return false;
29971}
29972
29973bool isVSQRTPH(unsigned Opcode) {
29974 switch (Opcode) {
29975 case VSQRTPHZ128m:
29976 case VSQRTPHZ128mb:
29977 case VSQRTPHZ128mbk:
29978 case VSQRTPHZ128mbkz:
29979 case VSQRTPHZ128mk:
29980 case VSQRTPHZ128mkz:
29981 case VSQRTPHZ128r:
29982 case VSQRTPHZ128rk:
29983 case VSQRTPHZ128rkz:
29984 case VSQRTPHZ256m:
29985 case VSQRTPHZ256mb:
29986 case VSQRTPHZ256mbk:
29987 case VSQRTPHZ256mbkz:
29988 case VSQRTPHZ256mk:
29989 case VSQRTPHZ256mkz:
29990 case VSQRTPHZ256r:
29991 case VSQRTPHZ256rk:
29992 case VSQRTPHZ256rkz:
29993 case VSQRTPHZm:
29994 case VSQRTPHZmb:
29995 case VSQRTPHZmbk:
29996 case VSQRTPHZmbkz:
29997 case VSQRTPHZmk:
29998 case VSQRTPHZmkz:
29999 case VSQRTPHZr:
30000 case VSQRTPHZrb:
30001 case VSQRTPHZrbk:
30002 case VSQRTPHZrbkz:
30003 case VSQRTPHZrk:
30004 case VSQRTPHZrkz:
30005 return true;
30006 }
30007 return false;
30008}
30009
30010bool isPOPF(unsigned Opcode) {
30011 return Opcode == POPF16;
30012}
30013
30014bool isVPSUBUSB(unsigned Opcode) {
30015 switch (Opcode) {
30016 case VPSUBUSBYrm:
30017 case VPSUBUSBYrr:
30018 case VPSUBUSBZ128rm:
30019 case VPSUBUSBZ128rmk:
30020 case VPSUBUSBZ128rmkz:
30021 case VPSUBUSBZ128rr:
30022 case VPSUBUSBZ128rrk:
30023 case VPSUBUSBZ128rrkz:
30024 case VPSUBUSBZ256rm:
30025 case VPSUBUSBZ256rmk:
30026 case VPSUBUSBZ256rmkz:
30027 case VPSUBUSBZ256rr:
30028 case VPSUBUSBZ256rrk:
30029 case VPSUBUSBZ256rrkz:
30030 case VPSUBUSBZrm:
30031 case VPSUBUSBZrmk:
30032 case VPSUBUSBZrmkz:
30033 case VPSUBUSBZrr:
30034 case VPSUBUSBZrrk:
30035 case VPSUBUSBZrrkz:
30036 case VPSUBUSBrm:
30037 case VPSUBUSBrr:
30038 return true;
30039 }
30040 return false;
30041}
30042
30043bool isPREFETCHIT1(unsigned Opcode) {
30044 return Opcode == PREFETCHIT1;
30045}
30046
30047bool isVPADDSW(unsigned Opcode) {
30048 switch (Opcode) {
30049 case VPADDSWYrm:
30050 case VPADDSWYrr:
30051 case VPADDSWZ128rm:
30052 case VPADDSWZ128rmk:
30053 case VPADDSWZ128rmkz:
30054 case VPADDSWZ128rr:
30055 case VPADDSWZ128rrk:
30056 case VPADDSWZ128rrkz:
30057 case VPADDSWZ256rm:
30058 case VPADDSWZ256rmk:
30059 case VPADDSWZ256rmkz:
30060 case VPADDSWZ256rr:
30061 case VPADDSWZ256rrk:
30062 case VPADDSWZ256rrkz:
30063 case VPADDSWZrm:
30064 case VPADDSWZrmk:
30065 case VPADDSWZrmkz:
30066 case VPADDSWZrr:
30067 case VPADDSWZrrk:
30068 case VPADDSWZrrkz:
30069 case VPADDSWrm:
30070 case VPADDSWrr:
30071 return true;
30072 }
30073 return false;
30074}
30075
30076bool isVADDSUBPD(unsigned Opcode) {
30077 switch (Opcode) {
30078 case VADDSUBPDYrm:
30079 case VADDSUBPDYrr:
30080 case VADDSUBPDrm:
30081 case VADDSUBPDrr:
30082 return true;
30083 }
30084 return false;
30085}
30086
30087bool isKANDD(unsigned Opcode) {
30088 return Opcode == KANDDrr;
30089}
30090
30091bool isOUTSB(unsigned Opcode) {
30092 return Opcode == OUTSB;
30093}
30094
30095bool isFNSTSW(unsigned Opcode) {
30096 switch (Opcode) {
30097 case FNSTSW16r:
30098 case FNSTSWm:
30099 return true;
30100 }
30101 return false;
30102}
30103
30104bool isPMINSB(unsigned Opcode) {
30105 switch (Opcode) {
30106 case PMINSBrm:
30107 case PMINSBrr:
30108 return true;
30109 }
30110 return false;
30111}
30112
30113#endif // GET_X86_MNEMONIC_TABLES_CPP
30114
30115} // end namespace X86
30116} // end namespace llvm