1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace X86 {
13enum : unsigned {
14 InvalidRegBankID = ~0u,
15 GPRRegBankID = 0,
16 PSRRegBankID = 1,
17 VECRRegBankID = 2,
18 NumRegisterBanks,
19};
20} // end namespace X86
21} // end namespace llvm
22#endif // GET_REGBANK_DECLARATIONS
23
24#ifdef GET_TARGET_REGBANK_CLASS
25#undef GET_TARGET_REGBANK_CLASS
26private:
27 static const RegisterBank *RegBanks[];
28 static const unsigned Sizes[];
29
30protected:
31 X86GenRegisterBankInfo(unsigned HwMode = 0);
32
33#endif // GET_TARGET_REGBANK_CLASS
34
35#ifdef GET_TARGET_REGBANK_IMPL
36#undef GET_TARGET_REGBANK_IMPL
37namespace llvm {
38namespace X86 {
39const uint32_t GPRRegBankCoverageData[] = {
40 // 0-31
41 (1u << (X86::GR8RegClassID - 0)) |
42 (1u << (X86::GR16RegClassID - 0)) |
43 (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) |
44 (1u << (X86::GR8_NOREX2RegClassID - 0)) |
45 (1u << (X86::GR16_NOREX2RegClassID - 0)) |
46 (1u << (X86::GR8_NOREXRegClassID - 0)) |
47 (1u << (X86::GR8_ABCD_HRegClassID - 0)) |
48 (1u << (X86::GR8_ABCD_LRegClassID - 0)) |
49 (1u << (X86::GR16_NOREXRegClassID - 0)) |
50 (1u << (X86::GR16_ABCDRegClassID - 0)) |
51 0,
52 // 32-63
53 (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 32)) |
54 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 32)) |
55 (1u << (X86::GR32RegClassID - 32)) |
56 (1u << (X86::GR32_NOSPRegClassID - 32)) |
57 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID - 32)) |
58 (1u << (X86::GR32_NOREX2RegClassID - 32)) |
59 (1u << (X86::GR32_NOREX2_NOSPRegClassID - 32)) |
60 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID - 32)) |
61 (1u << (X86::GR32_NOREXRegClassID - 32)) |
62 (1u << (X86::GR32_NOREX_NOSPRegClassID - 32)) |
63 (1u << (X86::GR32_ABCDRegClassID - 32)) |
64 (1u << (X86::GR32_TCRegClassID - 32)) |
65 (1u << (X86::GR32_ABCD_and_GR32_TCRegClassID - 32)) |
66 (1u << (X86::GR32_ADRegClassID - 32)) |
67 (1u << (X86::GR32_ArgRefRegClassID - 32)) |
68 (1u << (X86::GR32_DCRegClassID - 32)) |
69 (1u << (X86::GR32_AD_and_GR32_ArgRefRegClassID - 32)) |
70 (1u << (X86::GR32_CBRegClassID - 32)) |
71 (1u << (X86::GR32_SIDIRegClassID - 32)) |
72 (1u << (X86::GR32_BSIRegClassID - 32)) |
73 (1u << (X86::GR32_DIBPRegClassID - 32)) |
74 (1u << (X86::GR32_ABCD_and_GR32_BSIRegClassID - 32)) |
75 (1u << (X86::GR32_BPSPRegClassID - 32)) |
76 0,
77 // 64-95
78 (1u << (X86::GR64RegClassID - 64)) |
79 (1u << (X86::GR64_with_sub_8bitRegClassID - 64)) |
80 (1u << (X86::GR64_NOSPRegClassID - 64)) |
81 (1u << (X86::GR64_NOREX2_NOSPRegClassID - 64)) |
82 (1u << (X86::GR64PLTSafeRegClassID - 64)) |
83 (1u << (X86::GR64PLTSafe_and_GR64_TCRegClassID - 64)) |
84 (1u << (X86::GR32_ArgRef_and_GR32_CBRegClassID - 64)) |
85 (1u << (X86::GR32_BSI_and_GR32_SIDIRegClassID - 64)) |
86 (1u << (X86::GR32_DIBP_and_GR32_SIDIRegClassID - 64)) |
87 (1u << (X86::GR64_NOREX_NOSPRegClassID - 64)) |
88 (1u << (X86::GR32_BPSP_and_GR32_DIBPRegClassID - 64)) |
89 (1u << (X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID - 64)) |
90 (1u << (X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID - 64)) |
91 (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID - 64)) |
92 (1u << (X86::GR64_TC_with_sub_8bitRegClassID - 64)) |
93 (1u << (X86::GR32_BPSP_and_GR32_TCRegClassID - 64)) |
94 (1u << (X86::GR64_TCW64_with_sub_8bitRegClassID - 64)) |
95 (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 64)) |
96 (1u << (X86::GR64_NOREX2RegClassID - 64)) |
97 (1u << (X86::GR64_TCRegClassID - 64)) |
98 (1u << (X86::GR64_TC_and_GR64_TCW64RegClassID - 64)) |
99 (1u << (X86::GR64_NOREX_and_GR64_TCRegClassID - 64)) |
100 (1u << (X86::GR64_NOREXRegClassID - 64)) |
101 (1u << (X86::GR64_TCW64RegClassID - 64)) |
102 0,
103 // 96-127
104 (1u << (X86::GR64PLTSafe_and_GR64_TCW64RegClassID - 96)) |
105 (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID - 96)) |
106 (1u << (X86::GR64_ADRegClassID - 96)) |
107 (1u << (X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID - 96)) |
108 (1u << (X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID - 96)) |
109 (1u << (X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID - 96)) |
110 (1u << (X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID - 96)) |
111 (1u << (X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID - 96)) |
112 (1u << (X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID - 96)) |
113 (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID - 96)) |
114 (1u << (X86::GR64_ABCDRegClassID - 96)) |
115 (1u << (X86::GR64_with_sub_32bit_in_GR32_CBRegClassID - 96)) |
116 (1u << (X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID - 96)) |
117 (1u << (X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID - 96)) |
118 (1u << (X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID - 96)) |
119 (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID - 96)) |
120 (1u << (X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID - 96)) |
121 (1u << (X86::GR64_ArgRef_and_GR64_TCRegClassID - 96)) |
122 (1u << (X86::GR64_ArgRefRegClassID - 96)) |
123 (1u << (X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID - 96)) |
124 (1u << (X86::GR64_with_sub_32bit_in_GR32_TCRegClassID - 96)) |
125 (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID - 96)) |
126 (1u << (X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 96)) |
127 (1u << (X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID - 96)) |
128 (1u << (X86::GR64_NOREX_and_GR64_TCW64RegClassID - 96)) |
129 (1u << (X86::GR64_and_LOW32_ADDR_ACCESSRegClassID - 96)) |
130 (1u << (X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID - 96)) |
131 0,
132 // 128-159
133 0,
134};
135const uint32_t PSRRegBankCoverageData[] = {
136 // 0-31
137 0,
138 // 32-63
139 (1u << (X86::RFP32RegClassID - 32)) |
140 0,
141 // 64-95
142 (1u << (X86::RFP64RegClassID - 64)) |
143 0,
144 // 96-127
145 (1u << (X86::RFP80RegClassID - 96)) |
146 0,
147 // 128-159
148 0,
149};
150const uint32_t VECRRegBankCoverageData[] = {
151 // 0-31
152 (1u << (X86::FR16XRegClassID - 0)) |
153 (1u << (X86::FR16RegClassID - 0)) |
154 0,
155 // 32-63
156 (1u << (X86::FR32XRegClassID - 32)) |
157 (1u << (X86::FR32RegClassID - 32)) |
158 0,
159 // 64-95
160 (1u << (X86::FR64XRegClassID - 64)) |
161 (1u << (X86::FR64RegClassID - 64)) |
162 0,
163 // 96-127
164 (1u << (X86::VR128XRegClassID - 96)) |
165 0,
166 // 128-159
167 (1u << (X86::VR512RegClassID - 128)) |
168 (1u << (X86::VR256XRegClassID - 128)) |
169 (1u << (X86::VR512_0_15RegClassID - 128)) |
170 (1u << (X86::VR128RegClassID - 128)) |
171 (1u << (X86::VR256RegClassID - 128)) |
172 0,
173};
174
175constexpr RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 134);
176constexpr RegisterBank PSRRegBank(/* ID */ X86::PSRRegBankID, /* Name */ "PSR", /* CoveredRegClasses */ PSRRegBankCoverageData, /* NumRegClasses */ 134);
177constexpr RegisterBank VECRRegBank(/* ID */ X86::VECRRegBankID, /* Name */ "VECR", /* CoveredRegClasses */ VECRRegBankCoverageData, /* NumRegClasses */ 134);
178} // end namespace X86
179
180const RegisterBank *X86GenRegisterBankInfo::RegBanks[] = {
181 &X86::GPRRegBank,
182 &X86::PSRRegBank,
183 &X86::VECRRegBank,
184};
185
186const unsigned X86GenRegisterBankInfo::Sizes[] = {
187 // Mode = 0 (Default)
188 64,
189 80,
190 512,
191};
192
193X86GenRegisterBankInfo::X86GenRegisterBankInfo(unsigned HwMode)
194 : RegisterBankInfo(RegBanks, X86::NumRegisterBanks, Sizes, HwMode) {
195 // Assert that RegBank indices match their ID's
196#ifndef NDEBUG
197 for (auto RB : enumerate(RegBanks))
198 assert(RB.index() == RB.value()->getID() && "Index != ID");
199#endif // NDEBUG
200}
201} // end namespace llvm
202#endif // GET_TARGET_REGBANK_IMPL
203