1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass X86MCRegisterClasses[];
17
18namespace X86 {
19enum {
20 NoRegister,
21 AH = 1,
22 AL = 2,
23 AX = 3,
24 BH = 4,
25 BL = 5,
26 BP = 6,
27 BPH = 7,
28 BPL = 8,
29 BX = 9,
30 CH = 10,
31 CL = 11,
32 CS = 12,
33 CX = 13,
34 DF = 14,
35 DH = 15,
36 DI = 16,
37 DIH = 17,
38 DIL = 18,
39 DL = 19,
40 DS = 20,
41 DX = 21,
42 EAX = 22,
43 EBP = 23,
44 EBX = 24,
45 ECX = 25,
46 EDI = 26,
47 EDX = 27,
48 EFLAGS = 28,
49 EIP = 29,
50 EIZ = 30,
51 ES = 31,
52 ESI = 32,
53 ESP = 33,
54 FPCW = 34,
55 FPSW = 35,
56 FS = 36,
57 FS_BASE = 37,
58 GS = 38,
59 GS_BASE = 39,
60 HAX = 40,
61 HBP = 41,
62 HBX = 42,
63 HCX = 43,
64 HDI = 44,
65 HDX = 45,
66 HIP = 46,
67 HSI = 47,
68 HSP = 48,
69 IP = 49,
70 MXCSR = 50,
71 RAX = 51,
72 RBP = 52,
73 RBX = 53,
74 RCX = 54,
75 RDI = 55,
76 RDX = 56,
77 RFLAGS = 57,
78 RIP = 58,
79 RIZ = 59,
80 RSI = 60,
81 RSP = 61,
82 SI = 62,
83 SIH = 63,
84 SIL = 64,
85 SP = 65,
86 SPH = 66,
87 SPL = 67,
88 SS = 68,
89 SSP = 69,
90 _EFLAGS = 70,
91 CR0 = 71,
92 CR1 = 72,
93 CR2 = 73,
94 CR3 = 74,
95 CR4 = 75,
96 CR5 = 76,
97 CR6 = 77,
98 CR7 = 78,
99 CR8 = 79,
100 CR9 = 80,
101 CR10 = 81,
102 CR11 = 82,
103 CR12 = 83,
104 CR13 = 84,
105 CR14 = 85,
106 CR15 = 86,
107 DR0 = 87,
108 DR1 = 88,
109 DR2 = 89,
110 DR3 = 90,
111 DR4 = 91,
112 DR5 = 92,
113 DR6 = 93,
114 DR7 = 94,
115 DR8 = 95,
116 DR9 = 96,
117 DR10 = 97,
118 DR11 = 98,
119 DR12 = 99,
120 DR13 = 100,
121 DR14 = 101,
122 DR15 = 102,
123 FP0 = 103,
124 FP1 = 104,
125 FP2 = 105,
126 FP3 = 106,
127 FP4 = 107,
128 FP5 = 108,
129 FP6 = 109,
130 FP7 = 110,
131 MM0 = 111,
132 MM1 = 112,
133 MM2 = 113,
134 MM3 = 114,
135 MM4 = 115,
136 MM5 = 116,
137 MM6 = 117,
138 MM7 = 118,
139 R8 = 119,
140 R9 = 120,
141 R10 = 121,
142 R11 = 122,
143 R12 = 123,
144 R13 = 124,
145 R14 = 125,
146 R15 = 126,
147 ST0 = 127,
148 ST1 = 128,
149 ST2 = 129,
150 ST3 = 130,
151 ST4 = 131,
152 ST5 = 132,
153 ST6 = 133,
154 ST7 = 134,
155 XMM0 = 135,
156 XMM1 = 136,
157 XMM2 = 137,
158 XMM3 = 138,
159 XMM4 = 139,
160 XMM5 = 140,
161 XMM6 = 141,
162 XMM7 = 142,
163 XMM8 = 143,
164 XMM9 = 144,
165 XMM10 = 145,
166 XMM11 = 146,
167 XMM12 = 147,
168 XMM13 = 148,
169 XMM14 = 149,
170 XMM15 = 150,
171 R8B = 151,
172 R9B = 152,
173 R10B = 153,
174 R11B = 154,
175 R12B = 155,
176 R13B = 156,
177 R14B = 157,
178 R15B = 158,
179 R8BH = 159,
180 R9BH = 160,
181 R10BH = 161,
182 R11BH = 162,
183 R12BH = 163,
184 R13BH = 164,
185 R14BH = 165,
186 R15BH = 166,
187 R8D = 167,
188 R9D = 168,
189 R10D = 169,
190 R11D = 170,
191 R12D = 171,
192 R13D = 172,
193 R14D = 173,
194 R15D = 174,
195 R8W = 175,
196 R9W = 176,
197 R10W = 177,
198 R11W = 178,
199 R12W = 179,
200 R13W = 180,
201 R14W = 181,
202 R15W = 182,
203 R8WH = 183,
204 R9WH = 184,
205 R10WH = 185,
206 R11WH = 186,
207 R12WH = 187,
208 R13WH = 188,
209 R14WH = 189,
210 R15WH = 190,
211 YMM0 = 191,
212 YMM1 = 192,
213 YMM2 = 193,
214 YMM3 = 194,
215 YMM4 = 195,
216 YMM5 = 196,
217 YMM6 = 197,
218 YMM7 = 198,
219 YMM8 = 199,
220 YMM9 = 200,
221 YMM10 = 201,
222 YMM11 = 202,
223 YMM12 = 203,
224 YMM13 = 204,
225 YMM14 = 205,
226 YMM15 = 206,
227 K0 = 207,
228 K1 = 208,
229 K2 = 209,
230 K3 = 210,
231 K4 = 211,
232 K5 = 212,
233 K6 = 213,
234 K7 = 214,
235 XMM16 = 215,
236 XMM17 = 216,
237 XMM18 = 217,
238 XMM19 = 218,
239 XMM20 = 219,
240 XMM21 = 220,
241 XMM22 = 221,
242 XMM23 = 222,
243 XMM24 = 223,
244 XMM25 = 224,
245 XMM26 = 225,
246 XMM27 = 226,
247 XMM28 = 227,
248 XMM29 = 228,
249 XMM30 = 229,
250 XMM31 = 230,
251 YMM16 = 231,
252 YMM17 = 232,
253 YMM18 = 233,
254 YMM19 = 234,
255 YMM20 = 235,
256 YMM21 = 236,
257 YMM22 = 237,
258 YMM23 = 238,
259 YMM24 = 239,
260 YMM25 = 240,
261 YMM26 = 241,
262 YMM27 = 242,
263 YMM28 = 243,
264 YMM29 = 244,
265 YMM30 = 245,
266 YMM31 = 246,
267 ZMM0 = 247,
268 ZMM1 = 248,
269 ZMM2 = 249,
270 ZMM3 = 250,
271 ZMM4 = 251,
272 ZMM5 = 252,
273 ZMM6 = 253,
274 ZMM7 = 254,
275 ZMM8 = 255,
276 ZMM9 = 256,
277 ZMM10 = 257,
278 ZMM11 = 258,
279 ZMM12 = 259,
280 ZMM13 = 260,
281 ZMM14 = 261,
282 ZMM15 = 262,
283 ZMM16 = 263,
284 ZMM17 = 264,
285 ZMM18 = 265,
286 ZMM19 = 266,
287 ZMM20 = 267,
288 ZMM21 = 268,
289 ZMM22 = 269,
290 ZMM23 = 270,
291 ZMM24 = 271,
292 ZMM25 = 272,
293 ZMM26 = 273,
294 ZMM27 = 274,
295 ZMM28 = 275,
296 ZMM29 = 276,
297 ZMM30 = 277,
298 ZMM31 = 278,
299 K0_K1 = 279,
300 K2_K3 = 280,
301 K4_K5 = 281,
302 K6_K7 = 282,
303 TMMCFG = 283,
304 TMM0 = 284,
305 TMM1 = 285,
306 TMM2 = 286,
307 TMM3 = 287,
308 TMM4 = 288,
309 TMM5 = 289,
310 TMM6 = 290,
311 TMM7 = 291,
312 R16 = 292,
313 R17 = 293,
314 R18 = 294,
315 R19 = 295,
316 R20 = 296,
317 R21 = 297,
318 R22 = 298,
319 R23 = 299,
320 R24 = 300,
321 R25 = 301,
322 R26 = 302,
323 R27 = 303,
324 R28 = 304,
325 R29 = 305,
326 R30 = 306,
327 R31 = 307,
328 R16B = 308,
329 R17B = 309,
330 R18B = 310,
331 R19B = 311,
332 R20B = 312,
333 R21B = 313,
334 R22B = 314,
335 R23B = 315,
336 R24B = 316,
337 R25B = 317,
338 R26B = 318,
339 R27B = 319,
340 R28B = 320,
341 R29B = 321,
342 R30B = 322,
343 R31B = 323,
344 R16BH = 324,
345 R17BH = 325,
346 R18BH = 326,
347 R19BH = 327,
348 R20BH = 328,
349 R21BH = 329,
350 R22BH = 330,
351 R23BH = 331,
352 R24BH = 332,
353 R25BH = 333,
354 R26BH = 334,
355 R27BH = 335,
356 R28BH = 336,
357 R29BH = 337,
358 R30BH = 338,
359 R31BH = 339,
360 R16D = 340,
361 R17D = 341,
362 R18D = 342,
363 R19D = 343,
364 R20D = 344,
365 R21D = 345,
366 R22D = 346,
367 R23D = 347,
368 R24D = 348,
369 R25D = 349,
370 R26D = 350,
371 R27D = 351,
372 R28D = 352,
373 R29D = 353,
374 R30D = 354,
375 R31D = 355,
376 R16W = 356,
377 R17W = 357,
378 R18W = 358,
379 R19W = 359,
380 R20W = 360,
381 R21W = 361,
382 R22W = 362,
383 R23W = 363,
384 R24W = 364,
385 R25W = 365,
386 R26W = 366,
387 R27W = 367,
388 R28W = 368,
389 R29W = 369,
390 R30W = 370,
391 R31W = 371,
392 R16WH = 372,
393 R17WH = 373,
394 R18WH = 374,
395 R19WH = 375,
396 R20WH = 376,
397 R21WH = 377,
398 R22WH = 378,
399 R23WH = 379,
400 R24WH = 380,
401 R25WH = 381,
402 R26WH = 382,
403 R27WH = 383,
404 R28WH = 384,
405 R29WH = 385,
406 R30WH = 386,
407 R31WH = 387,
408 NUM_TARGET_REGS // 388
409};
410} // end namespace X86
411
412// Register classes
413
414namespace X86 {
415enum {
416 GR8RegClassID = 0,
417 GRH8RegClassID = 1,
418 GR8_NOREX2RegClassID = 2,
419 GR8_NOREXRegClassID = 3,
420 GR8_ABCD_HRegClassID = 4,
421 GR8_ABCD_LRegClassID = 5,
422 GRH16RegClassID = 6,
423 GR16RegClassID = 7,
424 GR16_NOREX2RegClassID = 8,
425 GR16_NOREXRegClassID = 9,
426 VK1RegClassID = 10,
427 VK16RegClassID = 11,
428 VK2RegClassID = 12,
429 VK4RegClassID = 13,
430 VK8RegClassID = 14,
431 VK16WMRegClassID = 15,
432 VK1WMRegClassID = 16,
433 VK2WMRegClassID = 17,
434 VK4WMRegClassID = 18,
435 VK8WMRegClassID = 19,
436 SEGMENT_REGRegClassID = 20,
437 GR16_ABCDRegClassID = 21,
438 FPCCRRegClassID = 22,
439 FR16XRegClassID = 23,
440 FR16RegClassID = 24,
441 VK16PAIRRegClassID = 25,
442 VK1PAIRRegClassID = 26,
443 VK2PAIRRegClassID = 27,
444 VK4PAIRRegClassID = 28,
445 VK8PAIRRegClassID = 29,
446 VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID = 30,
447 LOW32_ADDR_ACCESS_RBPRegClassID = 31,
448 LOW32_ADDR_ACCESSRegClassID = 32,
449 LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 33,
450 FR32XRegClassID = 34,
451 GR32RegClassID = 35,
452 GR32_NOSPRegClassID = 36,
453 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID = 37,
454 DEBUG_REGRegClassID = 38,
455 FR32RegClassID = 39,
456 GR32_NOREX2RegClassID = 40,
457 GR32_NOREX2_NOSPRegClassID = 41,
458 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 42,
459 GR32_NOREXRegClassID = 43,
460 VK32RegClassID = 44,
461 GR32_NOREX_NOSPRegClassID = 45,
462 RFP32RegClassID = 46,
463 VK32WMRegClassID = 47,
464 GR32_ABCDRegClassID = 48,
465 GR32_TCRegClassID = 49,
466 GR32_ABCD_and_GR32_TCRegClassID = 50,
467 GR32_ADRegClassID = 51,
468 GR32_ArgRefRegClassID = 52,
469 GR32_BPSPRegClassID = 53,
470 GR32_BSIRegClassID = 54,
471 GR32_CBRegClassID = 55,
472 GR32_DCRegClassID = 56,
473 GR32_DIBPRegClassID = 57,
474 GR32_SIDIRegClassID = 58,
475 LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 59,
476 CCRRegClassID = 60,
477 DFCCRRegClassID = 61,
478 GR32_ABCD_and_GR32_BSIRegClassID = 62,
479 GR32_AD_and_GR32_ArgRefRegClassID = 63,
480 GR32_ArgRef_and_GR32_CBRegClassID = 64,
481 GR32_BPSP_and_GR32_DIBPRegClassID = 65,
482 GR32_BPSP_and_GR32_TCRegClassID = 66,
483 GR32_BSI_and_GR32_SIDIRegClassID = 67,
484 GR32_DIBP_and_GR32_SIDIRegClassID = 68,
485 LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 69,
486 LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 70,
487 RFP64RegClassID = 71,
488 GR64RegClassID = 72,
489 FR64XRegClassID = 73,
490 GR64_with_sub_8bitRegClassID = 74,
491 GR64_NOSPRegClassID = 75,
492 GR64_NOREX2RegClassID = 76,
493 CONTROL_REGRegClassID = 77,
494 FR64RegClassID = 78,
495 GR64_with_sub_16bit_in_GR16_NOREX2RegClassID = 79,
496 GR64_NOREX2_NOSPRegClassID = 80,
497 GR64PLTSafeRegClassID = 81,
498 GR64_TCRegClassID = 82,
499 GR64_NOREXRegClassID = 83,
500 GR64_TCW64RegClassID = 84,
501 GR64_TC_with_sub_8bitRegClassID = 85,
502 GR64_NOREX2_NOSP_and_GR64_TCRegClassID = 86,
503 GR64_TCW64_with_sub_8bitRegClassID = 87,
504 GR64_TC_and_GR64_TCW64RegClassID = 88,
505 GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 89,
506 VK64RegClassID = 90,
507 VR64RegClassID = 91,
508 GR64PLTSafe_and_GR64_TCRegClassID = 92,
509 GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID = 93,
510 GR64_NOREX_NOSPRegClassID = 94,
511 GR64_NOREX_and_GR64_TCRegClassID = 95,
512 GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID = 96,
513 VK64WMRegClassID = 97,
514 GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID = 98,
515 GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 99,
516 GR64PLTSafe_and_GR64_TCW64RegClassID = 100,
517 GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID = 101,
518 GR64_NOREX_and_GR64_TCW64RegClassID = 102,
519 GR64_ABCDRegClassID = 103,
520 GR64_with_sub_32bit_in_GR32_TCRegClassID = 104,
521 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID = 105,
522 GR64_ADRegClassID = 106,
523 GR64_ArgRefRegClassID = 107,
524 GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 108,
525 GR64_with_sub_32bit_in_GR32_ArgRefRegClassID = 109,
526 GR64_with_sub_32bit_in_GR32_BPSPRegClassID = 110,
527 GR64_with_sub_32bit_in_GR32_BSIRegClassID = 111,
528 GR64_with_sub_32bit_in_GR32_CBRegClassID = 112,
529 GR64_with_sub_32bit_in_GR32_DIBPRegClassID = 113,
530 GR64_with_sub_32bit_in_GR32_SIDIRegClassID = 114,
531 GR64_ArgRef_and_GR64_TCRegClassID = 115,
532 GR64_and_LOW32_ADDR_ACCESSRegClassID = 116,
533 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID = 117,
534 GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID = 118,
535 GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID = 119,
536 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID = 120,
537 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID = 121,
538 GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID = 122,
539 GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID = 123,
540 RSTRegClassID = 124,
541 RFP80RegClassID = 125,
542 RFP80_7RegClassID = 126,
543 VR128XRegClassID = 127,
544 VR128RegClassID = 128,
545 VR256XRegClassID = 129,
546 VR256RegClassID = 130,
547 VR512RegClassID = 131,
548 VR512_0_15RegClassID = 132,
549 TILERegClassID = 133,
550
551};
552} // end namespace X86
553
554
555// Subregister indices
556
557namespace X86 {
558enum : uint16_t {
559 NoSubRegister,
560 sub_8bit, // 1
561 sub_8bit_hi, // 2
562 sub_8bit_hi_phony, // 3
563 sub_16bit, // 4
564 sub_16bit_hi, // 5
565 sub_32bit, // 6
566 sub_mask_0, // 7
567 sub_mask_1, // 8
568 sub_xmm, // 9
569 sub_ymm, // 10
570 NUM_TARGET_SUBREGS
571};
572} // end namespace X86
573
574// Register pressure sets enum.
575namespace X86 {
576enum RegisterPressureSets {
577 SEGMENT_REG = 0,
578 GR32_BPSP = 1,
579 LOW32_ADDR_ACCESS_with_sub_32bit = 2,
580 GR32_BSI = 3,
581 GR32_SIDI = 4,
582 GR32_DIBP_with_GR32_SIDI = 5,
583 GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit = 6,
584 RFP32 = 7,
585 GR8_ABCD_H_with_GR32_BSI = 8,
586 GR8_ABCD_L_with_GR32_BSI = 9,
587 VK1 = 10,
588 VR64 = 11,
589 TILE = 12,
590 GR8_NOREX = 13,
591 GR32_TC = 14,
592 GR32_BPSP_with_GR32_TC = 15,
593 FR16 = 16,
594 DEBUG_REG = 17,
595 CONTROL_REG = 18,
596 GR64_NOREX = 19,
597 GR64_TCW64 = 20,
598 GR32_BPSP_with_GR64_TCW64 = 21,
599 GR64_TC_with_GR64_TCW64 = 22,
600 GR64_TC = 23,
601 FR16X = 24,
602 GR64PLTSafe_with_GR64_TC = 25,
603 GR8 = 26,
604 GR8_with_GR32_DIBP = 27,
605 GR8_with_GR32_BSI = 28,
606 GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit = 29,
607 GR8_with_GR64_NOREX = 30,
608 GR8_with_GR64_TCW64 = 31,
609 GR8_with_GR64_TC = 32,
610 GR8_with_GR64PLTSafe = 33,
611 GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 = 34,
612 GR16 = 35,
613};
614} // end namespace X86
615
616} // end namespace llvm
617
618#endif // GET_REGINFO_ENUM
619
620/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
621|* *|
622|* MC Register Information *|
623|* *|
624|* Automatically generated file, do not edit! *|
625|* *|
626\*===----------------------------------------------------------------------===*/
627
628
629#ifdef GET_REGINFO_MC_DESC
630#undef GET_REGINFO_MC_DESC
631
632namespace llvm {
633
634extern const int16_t X86RegDiffLists[] = {
635 /* 0 */ -56, -56, 0,
636 /* 3 */ -32, -48, 0,
637 /* 6 */ 32, -16, -48, 0,
638 /* 10 */ 48, -16, -48, 0,
639 /* 14 */ 16, -8, -48, 0,
640 /* 18 */ 24, -8, -48, 0,
641 /* 22 */ -28, 32, 2, -1, -18, 0,
642 /* 28 */ -32, -16, 0,
643 /* 31 */ -28, 30, 2, -1, -16, 0,
644 /* 37 */ -2, -4, 0,
645 /* 40 */ -29, 20, -3, 0,
646 /* 44 */ -4, -1, 0,
647 /* 47 */ -2, -1, 0,
648 /* 50 */ -1, -1, 0,
649 /* 53 */ 2, -1, 0,
650 /* 56 */ -72, 1, 0,
651 /* 59 */ -71, 1, 0,
652 /* 62 */ -70, 1, 0,
653 /* 65 */ -69, 1, 0,
654 /* 68 */ 1, 1, 0,
655 /* 71 */ 3, 0,
656 /* 73 */ 1, 7, 0,
657 /* 76 */ 3, 7, 0,
658 /* 79 */ -24, 8, 0,
659 /* 82 */ 1, 11, 0,
660 /* 85 */ 1, 14, 0,
661 /* 88 */ -48, 16, 0,
662 /* 91 */ 48, 8, -24, 8, 24, 0,
663 /* 97 */ -29, -10, 2, -1, 27, 0,
664 /* 103 */ -2, -32, 28, 0,
665 /* 107 */ -1, -32, 28, 0,
666 /* 111 */ -2, -30, 28, 0,
667 /* 115 */ -1, -30, 28, 0,
668 /* 119 */ -15, 28, 0,
669 /* 122 */ -20, 29, 0,
670 /* 125 */ -18, 29, 0,
671 /* 128 */ -17, 29, 0,
672 /* 131 */ 2, 6, 29, 0,
673 /* 135 */ 6, 6, 29, 0,
674 /* 139 */ -2, 10, 29, 0,
675 /* 143 */ -1, 10, 29, 0,
676 /* 147 */ 2, 12, 29, 0,
677 /* 151 */ 3, 12, 29, 0,
678 /* 155 */ 4, 15, 29, 0,
679 /* 159 */ 5, 15, 29, 0,
680 /* 163 */ -2, 17, 29, 0,
681 /* 167 */ -1, 17, 29, 0,
682 /* 171 */ 1, 19, 29, 0,
683 /* 175 */ 2, 19, 29, 0,
684 /* 179 */ -29, -6, -2, -4, 30, 0,
685 /* 185 */ 16, 32, 0,
686 /* 188 */ -29, -12, -2, -1, 33, 0,
687 /* 194 */ -29, -17, 2, -1, 34, 0,
688 /* 200 */ -29, -15, -4, -1, 38, 0,
689 /* 206 */ -29, -19, -1, -1, 39, 0,
690 /* 212 */ 48, 16, -48, 16, 48, 0,
691 /* 218 */ 56, 56, 0,
692 /* 221 */ 68, 0,
693 /* 223 */ 69, 0,
694 /* 225 */ 70, 0,
695 /* 227 */ 71, 0,
696 /* 229 */ 72, 0,
697};
698
699extern const LaneBitmask X86LaneMaskLists[] = {
700 /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
701 /* 3 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask::getAll(),
702 /* 6 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
703 /* 10 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
704 /* 14 */ LaneBitmask(0x0000000000000007), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
705 /* 17 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),
706 /* 20 */ LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),
707 /* 22 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
708};
709
710extern const uint16_t X86SubRegIdxLists[] = {
711 /* 0 */ 1, 2, 0,
712 /* 3 */ 1, 3, 0,
713 /* 6 */ 6, 4, 1, 2, 5, 0,
714 /* 12 */ 6, 4, 1, 3, 5, 0,
715 /* 18 */ 6, 4, 5, 0,
716 /* 22 */ 7, 8, 0,
717 /* 25 */ 10, 9, 0,
718};
719
720
721#ifdef __GNUC__
722#pragma GCC diagnostic push
723#pragma GCC diagnostic ignored "-Woverlength-strings"
724#endif
725extern const char X86RegStrings[] = {
726 /* 0 */ "XMM10\0"
727 /* 6 */ "YMM10\0"
728 /* 12 */ "ZMM10\0"
729 /* 18 */ "CR10\0"
730 /* 23 */ "DR10\0"
731 /* 28 */ "XMM20\0"
732 /* 34 */ "YMM20\0"
733 /* 40 */ "ZMM20\0"
734 /* 46 */ "R20\0"
735 /* 50 */ "XMM30\0"
736 /* 56 */ "YMM30\0"
737 /* 62 */ "ZMM30\0"
738 /* 68 */ "R30\0"
739 /* 72 */ "K0\0"
740 /* 75 */ "TMM0\0"
741 /* 80 */ "XMM0\0"
742 /* 85 */ "YMM0\0"
743 /* 90 */ "ZMM0\0"
744 /* 95 */ "FP0\0"
745 /* 99 */ "CR0\0"
746 /* 103 */ "DR0\0"
747 /* 107 */ "ST0\0"
748 /* 111 */ "XMM11\0"
749 /* 117 */ "YMM11\0"
750 /* 123 */ "ZMM11\0"
751 /* 129 */ "CR11\0"
752 /* 134 */ "DR11\0"
753 /* 139 */ "XMM21\0"
754 /* 145 */ "YMM21\0"
755 /* 151 */ "ZMM21\0"
756 /* 157 */ "R21\0"
757 /* 161 */ "XMM31\0"
758 /* 167 */ "YMM31\0"
759 /* 173 */ "ZMM31\0"
760 /* 179 */ "R31\0"
761 /* 183 */ "K0_K1\0"
762 /* 189 */ "TMM1\0"
763 /* 194 */ "XMM1\0"
764 /* 199 */ "YMM1\0"
765 /* 204 */ "ZMM1\0"
766 /* 209 */ "FP1\0"
767 /* 213 */ "CR1\0"
768 /* 217 */ "DR1\0"
769 /* 221 */ "ST1\0"
770 /* 225 */ "XMM12\0"
771 /* 231 */ "YMM12\0"
772 /* 237 */ "ZMM12\0"
773 /* 243 */ "CR12\0"
774 /* 248 */ "DR12\0"
775 /* 253 */ "XMM22\0"
776 /* 259 */ "YMM22\0"
777 /* 265 */ "ZMM22\0"
778 /* 271 */ "R22\0"
779 /* 275 */ "K2\0"
780 /* 278 */ "TMM2\0"
781 /* 283 */ "XMM2\0"
782 /* 288 */ "YMM2\0"
783 /* 293 */ "ZMM2\0"
784 /* 298 */ "FP2\0"
785 /* 302 */ "CR2\0"
786 /* 306 */ "DR2\0"
787 /* 310 */ "ST2\0"
788 /* 314 */ "XMM13\0"
789 /* 320 */ "YMM13\0"
790 /* 326 */ "ZMM13\0"
791 /* 332 */ "CR13\0"
792 /* 337 */ "DR13\0"
793 /* 342 */ "XMM23\0"
794 /* 348 */ "YMM23\0"
795 /* 354 */ "ZMM23\0"
796 /* 360 */ "R23\0"
797 /* 364 */ "K2_K3\0"
798 /* 370 */ "TMM3\0"
799 /* 375 */ "XMM3\0"
800 /* 380 */ "YMM3\0"
801 /* 385 */ "ZMM3\0"
802 /* 390 */ "FP3\0"
803 /* 394 */ "CR3\0"
804 /* 398 */ "DR3\0"
805 /* 402 */ "ST3\0"
806 /* 406 */ "XMM14\0"
807 /* 412 */ "YMM14\0"
808 /* 418 */ "ZMM14\0"
809 /* 424 */ "CR14\0"
810 /* 429 */ "DR14\0"
811 /* 434 */ "XMM24\0"
812 /* 440 */ "YMM24\0"
813 /* 446 */ "ZMM24\0"
814 /* 452 */ "R24\0"
815 /* 456 */ "K4\0"
816 /* 459 */ "TMM4\0"
817 /* 464 */ "XMM4\0"
818 /* 469 */ "YMM4\0"
819 /* 474 */ "ZMM4\0"
820 /* 479 */ "FP4\0"
821 /* 483 */ "CR4\0"
822 /* 487 */ "DR4\0"
823 /* 491 */ "ST4\0"
824 /* 495 */ "XMM15\0"
825 /* 501 */ "YMM15\0"
826 /* 507 */ "ZMM15\0"
827 /* 513 */ "CR15\0"
828 /* 518 */ "DR15\0"
829 /* 523 */ "XMM25\0"
830 /* 529 */ "YMM25\0"
831 /* 535 */ "ZMM25\0"
832 /* 541 */ "R25\0"
833 /* 545 */ "K4_K5\0"
834 /* 551 */ "TMM5\0"
835 /* 556 */ "XMM5\0"
836 /* 561 */ "YMM5\0"
837 /* 566 */ "ZMM5\0"
838 /* 571 */ "FP5\0"
839 /* 575 */ "CR5\0"
840 /* 579 */ "DR5\0"
841 /* 583 */ "ST5\0"
842 /* 587 */ "XMM16\0"
843 /* 593 */ "YMM16\0"
844 /* 599 */ "ZMM16\0"
845 /* 605 */ "R16\0"
846 /* 609 */ "XMM26\0"
847 /* 615 */ "YMM26\0"
848 /* 621 */ "ZMM26\0"
849 /* 627 */ "R26\0"
850 /* 631 */ "K6\0"
851 /* 634 */ "TMM6\0"
852 /* 639 */ "XMM6\0"
853 /* 644 */ "YMM6\0"
854 /* 649 */ "ZMM6\0"
855 /* 654 */ "FP6\0"
856 /* 658 */ "CR6\0"
857 /* 662 */ "DR6\0"
858 /* 666 */ "ST6\0"
859 /* 670 */ "XMM17\0"
860 /* 676 */ "YMM17\0"
861 /* 682 */ "ZMM17\0"
862 /* 688 */ "R17\0"
863 /* 692 */ "XMM27\0"
864 /* 698 */ "YMM27\0"
865 /* 704 */ "ZMM27\0"
866 /* 710 */ "R27\0"
867 /* 714 */ "K6_K7\0"
868 /* 720 */ "TMM7\0"
869 /* 725 */ "XMM7\0"
870 /* 730 */ "YMM7\0"
871 /* 735 */ "ZMM7\0"
872 /* 740 */ "FP7\0"
873 /* 744 */ "CR7\0"
874 /* 748 */ "DR7\0"
875 /* 752 */ "ST7\0"
876 /* 756 */ "XMM18\0"
877 /* 762 */ "YMM18\0"
878 /* 768 */ "ZMM18\0"
879 /* 774 */ "R18\0"
880 /* 778 */ "XMM28\0"
881 /* 784 */ "YMM28\0"
882 /* 790 */ "ZMM28\0"
883 /* 796 */ "R28\0"
884 /* 800 */ "XMM8\0"
885 /* 805 */ "YMM8\0"
886 /* 810 */ "ZMM8\0"
887 /* 815 */ "CR8\0"
888 /* 819 */ "DR8\0"
889 /* 823 */ "XMM19\0"
890 /* 829 */ "YMM19\0"
891 /* 835 */ "ZMM19\0"
892 /* 841 */ "R19\0"
893 /* 845 */ "XMM29\0"
894 /* 851 */ "YMM29\0"
895 /* 857 */ "ZMM29\0"
896 /* 863 */ "R29\0"
897 /* 867 */ "XMM9\0"
898 /* 872 */ "YMM9\0"
899 /* 877 */ "ZMM9\0"
900 /* 882 */ "CR9\0"
901 /* 886 */ "DR9\0"
902 /* 890 */ "R10B\0"
903 /* 895 */ "R20B\0"
904 /* 900 */ "R30B\0"
905 /* 905 */ "R11B\0"
906 /* 910 */ "R21B\0"
907 /* 915 */ "R31B\0"
908 /* 920 */ "R12B\0"
909 /* 925 */ "R22B\0"
910 /* 930 */ "R13B\0"
911 /* 935 */ "R23B\0"
912 /* 940 */ "R14B\0"
913 /* 945 */ "R24B\0"
914 /* 950 */ "R15B\0"
915 /* 955 */ "R25B\0"
916 /* 960 */ "R16B\0"
917 /* 965 */ "R26B\0"
918 /* 970 */ "R17B\0"
919 /* 975 */ "R27B\0"
920 /* 980 */ "R18B\0"
921 /* 985 */ "R28B\0"
922 /* 990 */ "R8B\0"
923 /* 994 */ "R19B\0"
924 /* 999 */ "R29B\0"
925 /* 1004 */ "R9B\0"
926 /* 1008 */ "R10D\0"
927 /* 1013 */ "R20D\0"
928 /* 1018 */ "R30D\0"
929 /* 1023 */ "R11D\0"
930 /* 1028 */ "R21D\0"
931 /* 1033 */ "R31D\0"
932 /* 1038 */ "R12D\0"
933 /* 1043 */ "R22D\0"
934 /* 1048 */ "R13D\0"
935 /* 1053 */ "R23D\0"
936 /* 1058 */ "R14D\0"
937 /* 1063 */ "R24D\0"
938 /* 1068 */ "R15D\0"
939 /* 1073 */ "R25D\0"
940 /* 1078 */ "R16D\0"
941 /* 1083 */ "R26D\0"
942 /* 1088 */ "R17D\0"
943 /* 1093 */ "R27D\0"
944 /* 1098 */ "R18D\0"
945 /* 1103 */ "R28D\0"
946 /* 1108 */ "R8D\0"
947 /* 1112 */ "R19D\0"
948 /* 1117 */ "R29D\0"
949 /* 1122 */ "R9D\0"
950 /* 1126 */ "FS_BASE\0"
951 /* 1134 */ "GS_BASE\0"
952 /* 1142 */ "DF\0"
953 /* 1145 */ "TMMCFG\0"
954 /* 1152 */ "AH\0"
955 /* 1155 */ "R10BH\0"
956 /* 1161 */ "R20BH\0"
957 /* 1167 */ "R30BH\0"
958 /* 1173 */ "R11BH\0"
959 /* 1179 */ "R21BH\0"
960 /* 1185 */ "R31BH\0"
961 /* 1191 */ "R12BH\0"
962 /* 1197 */ "R22BH\0"
963 /* 1203 */ "R13BH\0"
964 /* 1209 */ "R23BH\0"
965 /* 1215 */ "R14BH\0"
966 /* 1221 */ "R24BH\0"
967 /* 1227 */ "R15BH\0"
968 /* 1233 */ "R25BH\0"
969 /* 1239 */ "R16BH\0"
970 /* 1245 */ "R26BH\0"
971 /* 1251 */ "R17BH\0"
972 /* 1257 */ "R27BH\0"
973 /* 1263 */ "R18BH\0"
974 /* 1269 */ "R28BH\0"
975 /* 1275 */ "R8BH\0"
976 /* 1280 */ "R19BH\0"
977 /* 1286 */ "R29BH\0"
978 /* 1292 */ "R9BH\0"
979 /* 1297 */ "CH\0"
980 /* 1300 */ "DH\0"
981 /* 1303 */ "DIH\0"
982 /* 1307 */ "SIH\0"
983 /* 1311 */ "BPH\0"
984 /* 1315 */ "SPH\0"
985 /* 1319 */ "R10WH\0"
986 /* 1325 */ "R20WH\0"
987 /* 1331 */ "R30WH\0"
988 /* 1337 */ "R11WH\0"
989 /* 1343 */ "R21WH\0"
990 /* 1349 */ "R31WH\0"
991 /* 1355 */ "R12WH\0"
992 /* 1361 */ "R22WH\0"
993 /* 1367 */ "R13WH\0"
994 /* 1373 */ "R23WH\0"
995 /* 1379 */ "R14WH\0"
996 /* 1385 */ "R24WH\0"
997 /* 1391 */ "R15WH\0"
998 /* 1397 */ "R25WH\0"
999 /* 1403 */ "R16WH\0"
1000 /* 1409 */ "R26WH\0"
1001 /* 1415 */ "R17WH\0"
1002 /* 1421 */ "R27WH\0"
1003 /* 1427 */ "R18WH\0"
1004 /* 1433 */ "R28WH\0"
1005 /* 1439 */ "R8WH\0"
1006 /* 1444 */ "R19WH\0"
1007 /* 1450 */ "R29WH\0"
1008 /* 1456 */ "R9WH\0"
1009 /* 1461 */ "EDI\0"
1010 /* 1465 */ "HDI\0"
1011 /* 1469 */ "RDI\0"
1012 /* 1473 */ "ESI\0"
1013 /* 1477 */ "HSI\0"
1014 /* 1481 */ "RSI\0"
1015 /* 1485 */ "AL\0"
1016 /* 1488 */ "BL\0"
1017 /* 1491 */ "CL\0"
1018 /* 1494 */ "DL\0"
1019 /* 1497 */ "DIL\0"
1020 /* 1501 */ "SIL\0"
1021 /* 1505 */ "BPL\0"
1022 /* 1509 */ "SPL\0"
1023 /* 1513 */ "EBP\0"
1024 /* 1517 */ "HBP\0"
1025 /* 1521 */ "RBP\0"
1026 /* 1525 */ "EIP\0"
1027 /* 1529 */ "HIP\0"
1028 /* 1533 */ "RIP\0"
1029 /* 1537 */ "ESP\0"
1030 /* 1541 */ "HSP\0"
1031 /* 1545 */ "RSP\0"
1032 /* 1549 */ "SSP\0"
1033 /* 1553 */ "MXCSR\0"
1034 /* 1559 */ "CS\0"
1035 /* 1562 */ "DS\0"
1036 /* 1565 */ "ES\0"
1037 /* 1568 */ "FS\0"
1038 /* 1571 */ "_EFLAGS\0"
1039 /* 1579 */ "RFLAGS\0"
1040 /* 1586 */ "SS\0"
1041 /* 1589 */ "R10W\0"
1042 /* 1594 */ "R20W\0"
1043 /* 1599 */ "R30W\0"
1044 /* 1604 */ "R11W\0"
1045 /* 1609 */ "R21W\0"
1046 /* 1614 */ "R31W\0"
1047 /* 1619 */ "R12W\0"
1048 /* 1624 */ "R22W\0"
1049 /* 1629 */ "R13W\0"
1050 /* 1634 */ "R23W\0"
1051 /* 1639 */ "R14W\0"
1052 /* 1644 */ "R24W\0"
1053 /* 1649 */ "R15W\0"
1054 /* 1654 */ "R25W\0"
1055 /* 1659 */ "R16W\0"
1056 /* 1664 */ "R26W\0"
1057 /* 1669 */ "R17W\0"
1058 /* 1674 */ "R27W\0"
1059 /* 1679 */ "R18W\0"
1060 /* 1684 */ "R28W\0"
1061 /* 1689 */ "R8W\0"
1062 /* 1693 */ "R19W\0"
1063 /* 1698 */ "R29W\0"
1064 /* 1703 */ "R9W\0"
1065 /* 1707 */ "FPCW\0"
1066 /* 1712 */ "FPSW\0"
1067 /* 1717 */ "EAX\0"
1068 /* 1721 */ "HAX\0"
1069 /* 1725 */ "RAX\0"
1070 /* 1729 */ "EBX\0"
1071 /* 1733 */ "HBX\0"
1072 /* 1737 */ "RBX\0"
1073 /* 1741 */ "ECX\0"
1074 /* 1745 */ "HCX\0"
1075 /* 1749 */ "RCX\0"
1076 /* 1753 */ "EDX\0"
1077 /* 1757 */ "HDX\0"
1078 /* 1761 */ "RDX\0"
1079 /* 1765 */ "EIZ\0"
1080 /* 1769 */ "RIZ\0"
1081};
1082#ifdef __GNUC__
1083#pragma GCC diagnostic pop
1084#endif
1085
1086extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
1087 { 5, 0, 0, 0, 0, 0, 0 },
1088 { 1152, 2, 175, 2, 8192, 22, 0 },
1089 { 1485, 2, 171, 2, 8193, 22, 0 },
1090 { 1718, 50, 172, 0, 233472, 0, 0 },
1091 { 1158, 2, 159, 2, 8194, 22, 0 },
1092 { 1488, 2, 155, 2, 8195, 22, 0 },
1093 { 1514, 53, 164, 3, 233476, 3, 0 },
1094 { 1311, 2, 167, 2, 8197, 22, 0 },
1095 { 1505, 2, 163, 2, 8196, 22, 0 },
1096 { 1730, 44, 156, 0, 233474, 0, 0 },
1097 { 1297, 2, 151, 2, 8198, 22, 0 },
1098 { 1491, 2, 147, 2, 8199, 22, 0 },
1099 { 1559, 2, 2, 2, 8200, 22, 0 },
1100 { 1742, 47, 148, 0, 233478, 0, 0 },
1101 { 1142, 2, 2, 2, 8201, 22, 0 },
1102 { 1300, 2, 135, 2, 8202, 22, 0 },
1103 { 1462, 53, 140, 3, 233483, 3, 0 },
1104 { 1303, 2, 143, 2, 8204, 22, 0 },
1105 { 1497, 2, 139, 2, 8203, 22, 0 },
1106 { 1494, 2, 131, 2, 8205, 22, 0 },
1107 { 1562, 2, 2, 2, 8206, 22, 0 },
1108 { 1754, 37, 132, 0, 290826, 0, 0 },
1109 { 1717, 207, 123, 7, 348160, 6, 0 },
1110 { 1513, 195, 123, 13, 335876, 10, 0 },
1111 { 1729, 201, 123, 7, 348162, 6, 0 },
1112 { 1741, 189, 123, 7, 335878, 6, 0 },
1113 { 1461, 98, 123, 13, 299019, 10, 0 },
1114 { 1753, 180, 123, 7, 311306, 6, 0 },
1115 { 1572, 2, 2, 2, 8213, 22, 0 },
1116 { 1525, 41, 123, 19, 233494, 14, 0 },
1117 { 1765, 2, 2, 2, 8216, 22, 0 },
1118 { 1565, 2, 2, 2, 8217, 22, 0 },
1119 { 1473, 32, 105, 13, 278554, 10, 0 },
1120 { 1537, 23, 105, 13, 278557, 10, 0 },
1121 { 1707, 2, 2, 2, 8224, 22, 0 },
1122 { 1712, 2, 2, 2, 8225, 22, 0 },
1123 { 1568, 2, 2, 2, 8226, 22, 0 },
1124 { 1126, 2, 2, 2, 8227, 22, 0 },
1125 { 1576, 2, 2, 2, 8228, 22, 0 },
1126 { 1134, 2, 2, 2, 8229, 22, 0 },
1127 { 1721, 2, 125, 2, 8207, 22, 0 },
1128 { 1517, 2, 125, 2, 8208, 22, 0 },
1129 { 1733, 2, 125, 2, 8209, 22, 0 },
1130 { 1745, 2, 125, 2, 8210, 22, 0 },
1131 { 1465, 2, 125, 2, 8211, 22, 0 },
1132 { 1757, 2, 125, 2, 8212, 22, 0 },
1133 { 1529, 2, 128, 2, 8215, 22, 0 },
1134 { 1477, 2, 119, 2, 8220, 22, 0 },
1135 { 1541, 2, 119, 2, 8223, 22, 0 },
1136 { 1526, 2, 122, 2, 8214, 22, 0 },
1137 { 1553, 2, 2, 2, 8230, 22, 0 },
1138 { 1725, 206, 2, 6, 348160, 6, 0 },
1139 { 1521, 194, 2, 12, 335876, 10, 0 },
1140 { 1737, 200, 2, 6, 348162, 6, 0 },
1141 { 1749, 188, 2, 6, 335878, 6, 0 },
1142 { 1469, 97, 2, 12, 299019, 10, 0 },
1143 { 1761, 179, 2, 6, 311306, 6, 0 },
1144 { 1579, 2, 2, 2, 8231, 22, 0 },
1145 { 1533, 40, 2, 18, 233494, 14, 0 },
1146 { 1769, 2, 2, 2, 8232, 22, 0 },
1147 { 1481, 31, 2, 12, 278554, 10, 0 },
1148 { 1545, 22, 2, 12, 278557, 10, 0 },
1149 { 1474, 53, 112, 3, 233498, 3, 0 },
1150 { 1307, 2, 115, 2, 8219, 22, 0 },
1151 { 1501, 2, 111, 2, 8218, 22, 0 },
1152 { 1538, 53, 104, 3, 233501, 3, 0 },
1153 { 1315, 2, 107, 2, 8222, 22, 0 },
1154 { 1509, 2, 103, 2, 8221, 22, 0 },
1155 { 1586, 2, 2, 2, 8233, 22, 0 },
1156 { 1549, 2, 2, 2, 8234, 22, 0 },
1157 { 1571, 2, 2, 2, 8235, 22, 0 },
1158 { 99, 2, 2, 2, 8236, 22, 0 },
1159 { 213, 2, 2, 2, 8237, 22, 0 },
1160 { 302, 2, 2, 2, 8238, 22, 0 },
1161 { 394, 2, 2, 2, 8239, 22, 0 },
1162 { 483, 2, 2, 2, 8240, 22, 0 },
1163 { 575, 2, 2, 2, 8241, 22, 0 },
1164 { 658, 2, 2, 2, 8242, 22, 0 },
1165 { 744, 2, 2, 2, 8243, 22, 0 },
1166 { 815, 2, 2, 2, 8244, 22, 0 },
1167 { 882, 2, 2, 2, 8245, 22, 0 },
1168 { 18, 2, 2, 2, 8246, 22, 0 },
1169 { 129, 2, 2, 2, 8247, 22, 0 },
1170 { 243, 2, 2, 2, 8248, 22, 0 },
1171 { 332, 2, 2, 2, 8249, 22, 0 },
1172 { 424, 2, 2, 2, 8250, 22, 0 },
1173 { 513, 2, 2, 2, 8251, 22, 0 },
1174 { 103, 2, 2, 2, 8252, 22, 0 },
1175 { 217, 2, 2, 2, 8253, 22, 0 },
1176 { 306, 2, 2, 2, 8254, 22, 0 },
1177 { 398, 2, 2, 2, 8255, 22, 0 },
1178 { 487, 2, 2, 2, 8256, 22, 0 },
1179 { 579, 2, 2, 2, 8257, 22, 0 },
1180 { 662, 2, 2, 2, 8258, 22, 0 },
1181 { 748, 2, 2, 2, 8259, 22, 0 },
1182 { 819, 2, 2, 2, 8260, 22, 0 },
1183 { 886, 2, 2, 2, 8261, 22, 0 },
1184 { 23, 2, 2, 2, 8262, 22, 0 },
1185 { 134, 2, 2, 2, 8263, 22, 0 },
1186 { 248, 2, 2, 2, 8264, 22, 0 },
1187 { 337, 2, 2, 2, 8265, 22, 0 },
1188 { 429, 2, 2, 2, 8266, 22, 0 },
1189 { 518, 2, 2, 2, 8267, 22, 0 },
1190 { 95, 2, 2, 2, 8268, 22, 0 },
1191 { 209, 2, 2, 2, 8269, 22, 0 },
1192 { 298, 2, 2, 2, 8270, 22, 0 },
1193 { 390, 2, 2, 2, 8271, 22, 0 },
1194 { 479, 2, 2, 2, 8272, 22, 0 },
1195 { 571, 2, 2, 2, 8273, 22, 0 },
1196 { 654, 2, 2, 2, 8274, 22, 0 },
1197 { 740, 2, 2, 2, 8275, 22, 0 },
1198 { 76, 2, 2, 2, 8276, 22, 0 },
1199 { 190, 2, 2, 2, 8277, 22, 0 },
1200 { 279, 2, 2, 2, 8278, 22, 0 },
1201 { 371, 2, 2, 2, 8279, 22, 0 },
1202 { 460, 2, 2, 2, 8280, 22, 0 },
1203 { 552, 2, 2, 2, 8281, 22, 0 },
1204 { 635, 2, 2, 2, 8282, 22, 0 },
1205 { 721, 2, 2, 2, 8283, 22, 0 },
1206 { 816, 91, 2, 12, 278620, 10, 0 },
1207 { 883, 91, 2, 12, 278623, 10, 0 },
1208 { 19, 91, 2, 12, 278626, 10, 0 },
1209 { 130, 91, 2, 12, 278629, 10, 0 },
1210 { 244, 91, 2, 12, 278632, 10, 0 },
1211 { 333, 91, 2, 12, 278635, 10, 0 },
1212 { 425, 91, 2, 12, 278638, 10, 0 },
1213 { 514, 91, 2, 12, 278641, 10, 0 },
1214 { 107, 2, 2, 2, 8308, 22, 0 },
1215 { 221, 2, 2, 2, 8309, 22, 0 },
1216 { 310, 2, 2, 2, 8310, 22, 0 },
1217 { 402, 2, 2, 2, 8311, 22, 0 },
1218 { 491, 2, 2, 2, 8312, 22, 0 },
1219 { 583, 2, 2, 2, 8313, 22, 0 },
1220 { 666, 2, 2, 2, 8314, 22, 0 },
1221 { 752, 2, 2, 2, 8315, 22, 0 },
1222 { 80, 2, 218, 2, 8316, 22, 0 },
1223 { 194, 2, 218, 2, 8317, 22, 0 },
1224 { 283, 2, 218, 2, 8318, 22, 0 },
1225 { 375, 2, 218, 2, 8319, 22, 0 },
1226 { 464, 2, 218, 2, 8320, 22, 0 },
1227 { 556, 2, 218, 2, 8321, 22, 0 },
1228 { 639, 2, 218, 2, 8322, 22, 0 },
1229 { 725, 2, 218, 2, 8323, 22, 0 },
1230 { 800, 2, 218, 2, 8324, 22, 0 },
1231 { 867, 2, 218, 2, 8325, 22, 0 },
1232 { 0, 2, 218, 2, 8326, 22, 0 },
1233 { 111, 2, 218, 2, 8327, 22, 0 },
1234 { 225, 2, 218, 2, 8328, 22, 0 },
1235 { 314, 2, 218, 2, 8329, 22, 0 },
1236 { 406, 2, 218, 2, 8330, 22, 0 },
1237 { 495, 2, 218, 2, 8331, 22, 0 },
1238 { 990, 2, 18, 2, 8284, 22, 0 },
1239 { 1004, 2, 18, 2, 8287, 22, 0 },
1240 { 890, 2, 18, 2, 8290, 22, 0 },
1241 { 905, 2, 18, 2, 8293, 22, 0 },
1242 { 920, 2, 18, 2, 8296, 22, 0 },
1243 { 930, 2, 18, 2, 8299, 22, 0 },
1244 { 940, 2, 18, 2, 8302, 22, 0 },
1245 { 950, 2, 18, 2, 8305, 22, 0 },
1246 { 1275, 2, 14, 2, 8285, 22, 0 },
1247 { 1292, 2, 14, 2, 8288, 22, 0 },
1248 { 1155, 2, 14, 2, 8291, 22, 0 },
1249 { 1173, 2, 14, 2, 8294, 22, 0 },
1250 { 1191, 2, 14, 2, 8297, 22, 0 },
1251 { 1203, 2, 14, 2, 8300, 22, 0 },
1252 { 1215, 2, 14, 2, 8303, 22, 0 },
1253 { 1227, 2, 14, 2, 8306, 22, 0 },
1254 { 1108, 92, 4, 13, 278620, 10, 0 },
1255 { 1122, 92, 4, 13, 278623, 10, 0 },
1256 { 1008, 92, 4, 13, 278626, 10, 0 },
1257 { 1023, 92, 4, 13, 278629, 10, 0 },
1258 { 1038, 92, 4, 13, 278632, 10, 0 },
1259 { 1048, 92, 4, 13, 278635, 10, 0 },
1260 { 1058, 92, 4, 13, 278638, 10, 0 },
1261 { 1068, 92, 4, 13, 278641, 10, 0 },
1262 { 1689, 79, 15, 3, 233564, 3, 0 },
1263 { 1703, 79, 15, 3, 233567, 3, 0 },
1264 { 1589, 79, 15, 3, 233570, 3, 0 },
1265 { 1604, 79, 15, 3, 233573, 3, 0 },
1266 { 1619, 79, 15, 3, 233576, 3, 0 },
1267 { 1629, 79, 15, 3, 233579, 3, 0 },
1268 { 1639, 79, 15, 3, 233582, 3, 0 },
1269 { 1649, 79, 15, 3, 233585, 3, 0 },
1270 { 1439, 2, 7, 2, 8286, 22, 0 },
1271 { 1456, 2, 7, 2, 8289, 22, 0 },
1272 { 1319, 2, 7, 2, 8292, 22, 0 },
1273 { 1337, 2, 7, 2, 8295, 22, 0 },
1274 { 1355, 2, 7, 2, 8298, 22, 0 },
1275 { 1367, 2, 7, 2, 8301, 22, 0 },
1276 { 1379, 2, 7, 2, 8304, 22, 0 },
1277 { 1391, 2, 7, 2, 8307, 22, 0 },
1278 { 85, 1, 219, 26, 8316, 20, 0 },
1279 { 199, 1, 219, 26, 8317, 20, 0 },
1280 { 288, 1, 219, 26, 8318, 20, 0 },
1281 { 380, 1, 219, 26, 8319, 20, 0 },
1282 { 469, 1, 219, 26, 8320, 20, 0 },
1283 { 561, 1, 219, 26, 8321, 20, 0 },
1284 { 644, 1, 219, 26, 8322, 20, 0 },
1285 { 730, 1, 219, 26, 8323, 20, 0 },
1286 { 805, 1, 219, 26, 8324, 20, 0 },
1287 { 872, 1, 219, 26, 8325, 20, 0 },
1288 { 6, 1, 219, 26, 8326, 20, 0 },
1289 { 117, 1, 219, 26, 8327, 20, 0 },
1290 { 231, 1, 219, 26, 8328, 20, 0 },
1291 { 320, 1, 219, 26, 8329, 20, 0 },
1292 { 412, 1, 219, 26, 8330, 20, 0 },
1293 { 501, 1, 219, 26, 8331, 20, 0 },
1294 { 72, 2, 229, 2, 8332, 22, 0 },
1295 { 186, 2, 227, 2, 8333, 22, 0 },
1296 { 275, 2, 227, 2, 8334, 22, 0 },
1297 { 367, 2, 225, 2, 8335, 22, 0 },
1298 { 456, 2, 225, 2, 8336, 22, 0 },
1299 { 548, 2, 223, 2, 8337, 22, 0 },
1300 { 631, 2, 223, 2, 8338, 22, 0 },
1301 { 717, 2, 221, 2, 8339, 22, 0 },
1302 { 587, 2, 185, 2, 8340, 22, 0 },
1303 { 670, 2, 185, 2, 8341, 22, 0 },
1304 { 756, 2, 185, 2, 8342, 22, 0 },
1305 { 823, 2, 185, 2, 8343, 22, 0 },
1306 { 28, 2, 185, 2, 8344, 22, 0 },
1307 { 139, 2, 185, 2, 8345, 22, 0 },
1308 { 253, 2, 185, 2, 8346, 22, 0 },
1309 { 342, 2, 185, 2, 8347, 22, 0 },
1310 { 434, 2, 185, 2, 8348, 22, 0 },
1311 { 523, 2, 185, 2, 8349, 22, 0 },
1312 { 609, 2, 185, 2, 8350, 22, 0 },
1313 { 692, 2, 185, 2, 8351, 22, 0 },
1314 { 778, 2, 185, 2, 8352, 22, 0 },
1315 { 845, 2, 185, 2, 8353, 22, 0 },
1316 { 50, 2, 185, 2, 8354, 22, 0 },
1317 { 161, 2, 185, 2, 8355, 22, 0 },
1318 { 593, 29, 186, 26, 8340, 20, 0 },
1319 { 676, 29, 186, 26, 8341, 20, 0 },
1320 { 762, 29, 186, 26, 8342, 20, 0 },
1321 { 829, 29, 186, 26, 8343, 20, 0 },
1322 { 34, 29, 186, 26, 8344, 20, 0 },
1323 { 145, 29, 186, 26, 8345, 20, 0 },
1324 { 259, 29, 186, 26, 8346, 20, 0 },
1325 { 348, 29, 186, 26, 8347, 20, 0 },
1326 { 440, 29, 186, 26, 8348, 20, 0 },
1327 { 529, 29, 186, 26, 8349, 20, 0 },
1328 { 615, 29, 186, 26, 8350, 20, 0 },
1329 { 698, 29, 186, 26, 8351, 20, 0 },
1330 { 784, 29, 186, 26, 8352, 20, 0 },
1331 { 851, 29, 186, 26, 8353, 20, 0 },
1332 { 56, 29, 186, 26, 8354, 20, 0 },
1333 { 167, 29, 186, 26, 8355, 20, 0 },
1334 { 90, 0, 2, 25, 8316, 20, 0 },
1335 { 204, 0, 2, 25, 8317, 20, 0 },
1336 { 293, 0, 2, 25, 8318, 20, 0 },
1337 { 385, 0, 2, 25, 8319, 20, 0 },
1338 { 474, 0, 2, 25, 8320, 20, 0 },
1339 { 566, 0, 2, 25, 8321, 20, 0 },
1340 { 649, 0, 2, 25, 8322, 20, 0 },
1341 { 735, 0, 2, 25, 8323, 20, 0 },
1342 { 810, 0, 2, 25, 8324, 20, 0 },
1343 { 877, 0, 2, 25, 8325, 20, 0 },
1344 { 12, 0, 2, 25, 8326, 20, 0 },
1345 { 123, 0, 2, 25, 8327, 20, 0 },
1346 { 237, 0, 2, 25, 8328, 20, 0 },
1347 { 326, 0, 2, 25, 8329, 20, 0 },
1348 { 418, 0, 2, 25, 8330, 20, 0 },
1349 { 507, 0, 2, 25, 8331, 20, 0 },
1350 { 599, 28, 2, 25, 8340, 20, 0 },
1351 { 682, 28, 2, 25, 8341, 20, 0 },
1352 { 768, 28, 2, 25, 8342, 20, 0 },
1353 { 835, 28, 2, 25, 8343, 20, 0 },
1354 { 40, 28, 2, 25, 8344, 20, 0 },
1355 { 151, 28, 2, 25, 8345, 20, 0 },
1356 { 265, 28, 2, 25, 8346, 20, 0 },
1357 { 354, 28, 2, 25, 8347, 20, 0 },
1358 { 446, 28, 2, 25, 8348, 20, 0 },
1359 { 535, 28, 2, 25, 8349, 20, 0 },
1360 { 621, 28, 2, 25, 8350, 20, 0 },
1361 { 704, 28, 2, 25, 8351, 20, 0 },
1362 { 790, 28, 2, 25, 8352, 20, 0 },
1363 { 857, 28, 2, 25, 8353, 20, 0 },
1364 { 62, 28, 2, 25, 8354, 20, 0 },
1365 { 173, 28, 2, 25, 8355, 20, 0 },
1366 { 183, 56, 2, 22, 233612, 17, 0 },
1367 { 364, 59, 2, 22, 233614, 17, 0 },
1368 { 545, 62, 2, 22, 233616, 17, 0 },
1369 { 714, 65, 2, 22, 233618, 17, 0 },
1370 { 1145, 2, 2, 2, 8356, 22, 0 },
1371 { 75, 2, 2, 2, 8357, 22, 0 },
1372 { 189, 2, 2, 2, 8358, 22, 0 },
1373 { 278, 2, 2, 2, 8359, 22, 0 },
1374 { 370, 2, 2, 2, 8360, 22, 0 },
1375 { 459, 2, 2, 2, 8361, 22, 0 },
1376 { 551, 2, 2, 2, 8362, 22, 0 },
1377 { 634, 2, 2, 2, 8363, 22, 0 },
1378 { 720, 2, 2, 2, 8364, 22, 0 },
1379 { 605, 212, 2, 12, 278701, 10, 0 },
1380 { 688, 212, 2, 12, 278704, 10, 0 },
1381 { 774, 212, 2, 12, 278707, 10, 0 },
1382 { 841, 212, 2, 12, 278710, 10, 0 },
1383 { 46, 212, 2, 12, 278713, 10, 0 },
1384 { 157, 212, 2, 12, 278716, 10, 0 },
1385 { 271, 212, 2, 12, 278719, 10, 0 },
1386 { 360, 212, 2, 12, 278722, 10, 0 },
1387 { 452, 212, 2, 12, 278725, 10, 0 },
1388 { 541, 212, 2, 12, 278728, 10, 0 },
1389 { 627, 212, 2, 12, 278731, 10, 0 },
1390 { 710, 212, 2, 12, 278734, 10, 0 },
1391 { 796, 212, 2, 12, 278737, 10, 0 },
1392 { 863, 212, 2, 12, 278740, 10, 0 },
1393 { 68, 212, 2, 12, 278743, 10, 0 },
1394 { 179, 212, 2, 12, 278746, 10, 0 },
1395 { 960, 2, 10, 2, 8365, 22, 0 },
1396 { 970, 2, 10, 2, 8368, 22, 0 },
1397 { 980, 2, 10, 2, 8371, 22, 0 },
1398 { 994, 2, 10, 2, 8374, 22, 0 },
1399 { 895, 2, 10, 2, 8377, 22, 0 },
1400 { 910, 2, 10, 2, 8380, 22, 0 },
1401 { 925, 2, 10, 2, 8383, 22, 0 },
1402 { 935, 2, 10, 2, 8386, 22, 0 },
1403 { 945, 2, 10, 2, 8389, 22, 0 },
1404 { 955, 2, 10, 2, 8392, 22, 0 },
1405 { 965, 2, 10, 2, 8395, 22, 0 },
1406 { 975, 2, 10, 2, 8398, 22, 0 },
1407 { 985, 2, 10, 2, 8401, 22, 0 },
1408 { 999, 2, 10, 2, 8404, 22, 0 },
1409 { 900, 2, 10, 2, 8407, 22, 0 },
1410 { 915, 2, 10, 2, 8410, 22, 0 },
1411 { 1239, 2, 6, 2, 8366, 22, 0 },
1412 { 1251, 2, 6, 2, 8369, 22, 0 },
1413 { 1263, 2, 6, 2, 8372, 22, 0 },
1414 { 1280, 2, 6, 2, 8375, 22, 0 },
1415 { 1161, 2, 6, 2, 8378, 22, 0 },
1416 { 1179, 2, 6, 2, 8381, 22, 0 },
1417 { 1197, 2, 6, 2, 8384, 22, 0 },
1418 { 1209, 2, 6, 2, 8387, 22, 0 },
1419 { 1221, 2, 6, 2, 8390, 22, 0 },
1420 { 1233, 2, 6, 2, 8393, 22, 0 },
1421 { 1245, 2, 6, 2, 8396, 22, 0 },
1422 { 1257, 2, 6, 2, 8399, 22, 0 },
1423 { 1269, 2, 6, 2, 8402, 22, 0 },
1424 { 1286, 2, 6, 2, 8405, 22, 0 },
1425 { 1167, 2, 6, 2, 8408, 22, 0 },
1426 { 1185, 2, 6, 2, 8411, 22, 0 },
1427 { 1078, 213, 4, 13, 278701, 10, 0 },
1428 { 1088, 213, 4, 13, 278704, 10, 0 },
1429 { 1098, 213, 4, 13, 278707, 10, 0 },
1430 { 1112, 213, 4, 13, 278710, 10, 0 },
1431 { 1013, 213, 4, 13, 278713, 10, 0 },
1432 { 1028, 213, 4, 13, 278716, 10, 0 },
1433 { 1043, 213, 4, 13, 278719, 10, 0 },
1434 { 1053, 213, 4, 13, 278722, 10, 0 },
1435 { 1063, 213, 4, 13, 278725, 10, 0 },
1436 { 1073, 213, 4, 13, 278728, 10, 0 },
1437 { 1083, 213, 4, 13, 278731, 10, 0 },
1438 { 1093, 213, 4, 13, 278734, 10, 0 },
1439 { 1103, 213, 4, 13, 278737, 10, 0 },
1440 { 1117, 213, 4, 13, 278740, 10, 0 },
1441 { 1018, 213, 4, 13, 278743, 10, 0 },
1442 { 1033, 213, 4, 13, 278746, 10, 0 },
1443 { 1659, 88, 7, 3, 233645, 3, 0 },
1444 { 1669, 88, 7, 3, 233648, 3, 0 },
1445 { 1679, 88, 7, 3, 233651, 3, 0 },
1446 { 1693, 88, 7, 3, 233654, 3, 0 },
1447 { 1594, 88, 7, 3, 233657, 3, 0 },
1448 { 1609, 88, 7, 3, 233660, 3, 0 },
1449 { 1624, 88, 7, 3, 233663, 3, 0 },
1450 { 1634, 88, 7, 3, 233666, 3, 0 },
1451 { 1644, 88, 7, 3, 233669, 3, 0 },
1452 { 1654, 88, 7, 3, 233672, 3, 0 },
1453 { 1664, 88, 7, 3, 233675, 3, 0 },
1454 { 1674, 88, 7, 3, 233678, 3, 0 },
1455 { 1684, 88, 7, 3, 233681, 3, 0 },
1456 { 1698, 88, 7, 3, 233684, 3, 0 },
1457 { 1599, 88, 7, 3, 233687, 3, 0 },
1458 { 1614, 88, 7, 3, 233690, 3, 0 },
1459 { 1403, 2, 3, 2, 8367, 22, 0 },
1460 { 1415, 2, 3, 2, 8370, 22, 0 },
1461 { 1427, 2, 3, 2, 8373, 22, 0 },
1462 { 1444, 2, 3, 2, 8376, 22, 0 },
1463 { 1325, 2, 3, 2, 8379, 22, 0 },
1464 { 1343, 2, 3, 2, 8382, 22, 0 },
1465 { 1361, 2, 3, 2, 8385, 22, 0 },
1466 { 1373, 2, 3, 2, 8388, 22, 0 },
1467 { 1385, 2, 3, 2, 8391, 22, 0 },
1468 { 1397, 2, 3, 2, 8394, 22, 0 },
1469 { 1409, 2, 3, 2, 8397, 22, 0 },
1470 { 1421, 2, 3, 2, 8400, 22, 0 },
1471 { 1433, 2, 3, 2, 8403, 22, 0 },
1472 { 1450, 2, 3, 2, 8406, 22, 0 },
1473 { 1331, 2, 3, 2, 8409, 22, 0 },
1474 { 1349, 2, 3, 2, 8412, 22, 0 },
1475};
1476
1477extern const MCPhysReg X86RegUnitRoots[][2] = {
1478 { X86::AH },
1479 { X86::AL },
1480 { X86::BH },
1481 { X86::BL },
1482 { X86::BPL },
1483 { X86::BPH },
1484 { X86::CH },
1485 { X86::CL },
1486 { X86::CS },
1487 { X86::DF },
1488 { X86::DH },
1489 { X86::DIL },
1490 { X86::DIH },
1491 { X86::DL },
1492 { X86::DS },
1493 { X86::HAX },
1494 { X86::HBP },
1495 { X86::HBX },
1496 { X86::HCX },
1497 { X86::HDI },
1498 { X86::HDX },
1499 { X86::EFLAGS },
1500 { X86::IP },
1501 { X86::HIP },
1502 { X86::EIZ },
1503 { X86::ES },
1504 { X86::SIL },
1505 { X86::SIH },
1506 { X86::HSI },
1507 { X86::SPL },
1508 { X86::SPH },
1509 { X86::HSP },
1510 { X86::FPCW },
1511 { X86::FPSW },
1512 { X86::FS },
1513 { X86::FS_BASE },
1514 { X86::GS },
1515 { X86::GS_BASE },
1516 { X86::MXCSR },
1517 { X86::RFLAGS },
1518 { X86::RIZ },
1519 { X86::SS },
1520 { X86::SSP },
1521 { X86::_EFLAGS },
1522 { X86::CR0 },
1523 { X86::CR1 },
1524 { X86::CR2 },
1525 { X86::CR3 },
1526 { X86::CR4 },
1527 { X86::CR5 },
1528 { X86::CR6 },
1529 { X86::CR7 },
1530 { X86::CR8 },
1531 { X86::CR9 },
1532 { X86::CR10 },
1533 { X86::CR11 },
1534 { X86::CR12 },
1535 { X86::CR13 },
1536 { X86::CR14 },
1537 { X86::CR15 },
1538 { X86::DR0 },
1539 { X86::DR1 },
1540 { X86::DR2 },
1541 { X86::DR3 },
1542 { X86::DR4 },
1543 { X86::DR5 },
1544 { X86::DR6 },
1545 { X86::DR7 },
1546 { X86::DR8 },
1547 { X86::DR9 },
1548 { X86::DR10 },
1549 { X86::DR11 },
1550 { X86::DR12 },
1551 { X86::DR13 },
1552 { X86::DR14 },
1553 { X86::DR15 },
1554 { X86::FP0 },
1555 { X86::FP1 },
1556 { X86::FP2 },
1557 { X86::FP3 },
1558 { X86::FP4 },
1559 { X86::FP5 },
1560 { X86::FP6 },
1561 { X86::FP7 },
1562 { X86::MM0 },
1563 { X86::MM1 },
1564 { X86::MM2 },
1565 { X86::MM3 },
1566 { X86::MM4 },
1567 { X86::MM5 },
1568 { X86::MM6 },
1569 { X86::MM7 },
1570 { X86::R8B },
1571 { X86::R8BH },
1572 { X86::R8WH },
1573 { X86::R9B },
1574 { X86::R9BH },
1575 { X86::R9WH },
1576 { X86::R10B },
1577 { X86::R10BH },
1578 { X86::R10WH },
1579 { X86::R11B },
1580 { X86::R11BH },
1581 { X86::R11WH },
1582 { X86::R12B },
1583 { X86::R12BH },
1584 { X86::R12WH },
1585 { X86::R13B },
1586 { X86::R13BH },
1587 { X86::R13WH },
1588 { X86::R14B },
1589 { X86::R14BH },
1590 { X86::R14WH },
1591 { X86::R15B },
1592 { X86::R15BH },
1593 { X86::R15WH },
1594 { X86::ST0 },
1595 { X86::ST1 },
1596 { X86::ST2 },
1597 { X86::ST3 },
1598 { X86::ST4 },
1599 { X86::ST5 },
1600 { X86::ST6 },
1601 { X86::ST7 },
1602 { X86::XMM0 },
1603 { X86::XMM1 },
1604 { X86::XMM2 },
1605 { X86::XMM3 },
1606 { X86::XMM4 },
1607 { X86::XMM5 },
1608 { X86::XMM6 },
1609 { X86::XMM7 },
1610 { X86::XMM8 },
1611 { X86::XMM9 },
1612 { X86::XMM10 },
1613 { X86::XMM11 },
1614 { X86::XMM12 },
1615 { X86::XMM13 },
1616 { X86::XMM14 },
1617 { X86::XMM15 },
1618 { X86::K0 },
1619 { X86::K1 },
1620 { X86::K2 },
1621 { X86::K3 },
1622 { X86::K4 },
1623 { X86::K5 },
1624 { X86::K6 },
1625 { X86::K7 },
1626 { X86::XMM16 },
1627 { X86::XMM17 },
1628 { X86::XMM18 },
1629 { X86::XMM19 },
1630 { X86::XMM20 },
1631 { X86::XMM21 },
1632 { X86::XMM22 },
1633 { X86::XMM23 },
1634 { X86::XMM24 },
1635 { X86::XMM25 },
1636 { X86::XMM26 },
1637 { X86::XMM27 },
1638 { X86::XMM28 },
1639 { X86::XMM29 },
1640 { X86::XMM30 },
1641 { X86::XMM31 },
1642 { X86::TMMCFG },
1643 { X86::TMM0 },
1644 { X86::TMM1 },
1645 { X86::TMM2 },
1646 { X86::TMM3 },
1647 { X86::TMM4 },
1648 { X86::TMM5 },
1649 { X86::TMM6 },
1650 { X86::TMM7 },
1651 { X86::R16B },
1652 { X86::R16BH },
1653 { X86::R16WH },
1654 { X86::R17B },
1655 { X86::R17BH },
1656 { X86::R17WH },
1657 { X86::R18B },
1658 { X86::R18BH },
1659 { X86::R18WH },
1660 { X86::R19B },
1661 { X86::R19BH },
1662 { X86::R19WH },
1663 { X86::R20B },
1664 { X86::R20BH },
1665 { X86::R20WH },
1666 { X86::R21B },
1667 { X86::R21BH },
1668 { X86::R21WH },
1669 { X86::R22B },
1670 { X86::R22BH },
1671 { X86::R22WH },
1672 { X86::R23B },
1673 { X86::R23BH },
1674 { X86::R23WH },
1675 { X86::R24B },
1676 { X86::R24BH },
1677 { X86::R24WH },
1678 { X86::R25B },
1679 { X86::R25BH },
1680 { X86::R25WH },
1681 { X86::R26B },
1682 { X86::R26BH },
1683 { X86::R26WH },
1684 { X86::R27B },
1685 { X86::R27BH },
1686 { X86::R27WH },
1687 { X86::R28B },
1688 { X86::R28BH },
1689 { X86::R28WH },
1690 { X86::R29B },
1691 { X86::R29BH },
1692 { X86::R29WH },
1693 { X86::R30B },
1694 { X86::R30BH },
1695 { X86::R30WH },
1696 { X86::R31B },
1697 { X86::R31BH },
1698 { X86::R31WH },
1699};
1700
1701namespace { // Register classes...
1702 // GR8 Register Class...
1703 const MCPhysReg GR8[] = {
1704 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R20B, X86::R21B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R28B, X86::R29B, X86::R30B, X86::R31B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
1705 };
1706
1707 // GR8 Bit set.
1708 const uint8_t GR8Bits[] = {
1709 0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1710 };
1711
1712 // GRH8 Register Class...
1713 const MCPhysReg GRH8[] = {
1714 X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH, X86::R16BH, X86::R17BH, X86::R18BH, X86::R19BH, X86::R20BH, X86::R21BH, X86::R22BH, X86::R23BH, X86::R24BH, X86::R25BH, X86::R26BH, X86::R27BH, X86::R28BH, X86::R29BH, X86::R30BH, X86::R31BH,
1715 };
1716
1717 // GRH8 Bit set.
1718 const uint8_t GRH8Bits[] = {
1719 0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1720 };
1721
1722 // GR8_NOREX2 Register Class...
1723 const MCPhysReg GR8_NOREX2[] = {
1724 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
1725 };
1726
1727 // GR8_NOREX2 Bit set.
1728 const uint8_t GR8_NOREX2Bits[] = {
1729 0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1730 };
1731
1732 // GR8_NOREX Register Class...
1733 const MCPhysReg GR8_NOREX[] = {
1734 X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
1735 };
1736
1737 // GR8_NOREX Bit set.
1738 const uint8_t GR8_NOREXBits[] = {
1739 0x36, 0x8c, 0x08,
1740 };
1741
1742 // GR8_ABCD_H Register Class...
1743 const MCPhysReg GR8_ABCD_H[] = {
1744 X86::AH, X86::CH, X86::DH, X86::BH,
1745 };
1746
1747 // GR8_ABCD_H Bit set.
1748 const uint8_t GR8_ABCD_HBits[] = {
1749 0x12, 0x84,
1750 };
1751
1752 // GR8_ABCD_L Register Class...
1753 const MCPhysReg GR8_ABCD_L[] = {
1754 X86::AL, X86::CL, X86::DL, X86::BL,
1755 };
1756
1757 // GR8_ABCD_L Bit set.
1758 const uint8_t GR8_ABCD_LBits[] = {
1759 0x24, 0x08, 0x08,
1760 };
1761
1762 // GRH16 Register Class...
1763 const MCPhysReg GRH16[] = {
1764 X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH, X86::R16WH, X86::R17WH, X86::R18WH, X86::R19WH, X86::R20WH, X86::R21WH, X86::R22WH, X86::R23WH, X86::R24WH, X86::R25WH, X86::R26WH, X86::R27WH, X86::R28WH, X86::R29WH, X86::R30WH, X86::R31WH,
1765 };
1766
1767 // GRH16 Bit set.
1768 const uint8_t GRH16Bits[] = {
1769 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1770 };
1771
1772 // GR16 Register Class...
1773 const MCPhysReg GR16[] = {
1774 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R16W, X86::R17W, X86::R18W, X86::R19W, X86::R20W, X86::R21W, X86::R22W, X86::R23W, X86::R24W, X86::R25W, X86::R26W, X86::R27W, X86::R28W, X86::R29W, X86::R30W, X86::R31W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
1775 };
1776
1777 // GR16 Bit set.
1778 const uint8_t GR16Bits[] = {
1779 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
1780 };
1781
1782 // GR16_NOREX2 Register Class...
1783 const MCPhysReg GR16_NOREX2[] = {
1784 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
1785 };
1786
1787 // GR16_NOREX2 Bit set.
1788 const uint8_t GR16_NOREX2Bits[] = {
1789 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1790 };
1791
1792 // GR16_NOREX Register Class...
1793 const MCPhysReg GR16_NOREX[] = {
1794 X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP,
1795 };
1796
1797 // GR16_NOREX Bit set.
1798 const uint8_t GR16_NOREXBits[] = {
1799 0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02,
1800 };
1801
1802 // VK1 Register Class...
1803 const MCPhysReg VK1[] = {
1804 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1805 };
1806
1807 // VK1 Bit set.
1808 const uint8_t VK1Bits[] = {
1809 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1810 };
1811
1812 // VK16 Register Class...
1813 const MCPhysReg VK16[] = {
1814 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1815 };
1816
1817 // VK16 Bit set.
1818 const uint8_t VK16Bits[] = {
1819 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1820 };
1821
1822 // VK2 Register Class...
1823 const MCPhysReg VK2[] = {
1824 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1825 };
1826
1827 // VK2 Bit set.
1828 const uint8_t VK2Bits[] = {
1829 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1830 };
1831
1832 // VK4 Register Class...
1833 const MCPhysReg VK4[] = {
1834 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1835 };
1836
1837 // VK4 Bit set.
1838 const uint8_t VK4Bits[] = {
1839 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1840 };
1841
1842 // VK8 Register Class...
1843 const MCPhysReg VK8[] = {
1844 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1845 };
1846
1847 // VK8 Bit set.
1848 const uint8_t VK8Bits[] = {
1849 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
1850 };
1851
1852 // VK16WM Register Class...
1853 const MCPhysReg VK16WM[] = {
1854 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1855 };
1856
1857 // VK16WM Bit set.
1858 const uint8_t VK16WMBits[] = {
1859 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1860 };
1861
1862 // VK1WM Register Class...
1863 const MCPhysReg VK1WM[] = {
1864 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1865 };
1866
1867 // VK1WM Bit set.
1868 const uint8_t VK1WMBits[] = {
1869 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1870 };
1871
1872 // VK2WM Register Class...
1873 const MCPhysReg VK2WM[] = {
1874 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1875 };
1876
1877 // VK2WM Bit set.
1878 const uint8_t VK2WMBits[] = {
1879 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1880 };
1881
1882 // VK4WM Register Class...
1883 const MCPhysReg VK4WM[] = {
1884 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1885 };
1886
1887 // VK4WM Bit set.
1888 const uint8_t VK4WMBits[] = {
1889 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1890 };
1891
1892 // VK8WM Register Class...
1893 const MCPhysReg VK8WM[] = {
1894 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
1895 };
1896
1897 // VK8WM Bit set.
1898 const uint8_t VK8WMBits[] = {
1899 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
1900 };
1901
1902 // SEGMENT_REG Register Class...
1903 const MCPhysReg SEGMENT_REG[] = {
1904 X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS,
1905 };
1906
1907 // SEGMENT_REG Bit set.
1908 const uint8_t SEGMENT_REGBits[] = {
1909 0x00, 0x10, 0x10, 0x80, 0x50, 0x00, 0x00, 0x00, 0x10,
1910 };
1911
1912 // GR16_ABCD Register Class...
1913 const MCPhysReg GR16_ABCD[] = {
1914 X86::AX, X86::CX, X86::DX, X86::BX,
1915 };
1916
1917 // GR16_ABCD Bit set.
1918 const uint8_t GR16_ABCDBits[] = {
1919 0x08, 0x22, 0x20,
1920 };
1921
1922 // FPCCR Register Class...
1923 const MCPhysReg FPCCR[] = {
1924 X86::FPSW,
1925 };
1926
1927 // FPCCR Bit set.
1928 const uint8_t FPCCRBits[] = {
1929 0x00, 0x00, 0x00, 0x00, 0x08,
1930 };
1931
1932 // FR16X Register Class...
1933 const MCPhysReg FR16X[] = {
1934 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
1935 };
1936
1937 // FR16X Bit set.
1938 const uint8_t FR16XBits[] = {
1939 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1940 };
1941
1942 // FR16 Register Class...
1943 const MCPhysReg FR16[] = {
1944 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
1945 };
1946
1947 // FR16 Bit set.
1948 const uint8_t FR16Bits[] = {
1949 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1950 };
1951
1952 // VK16PAIR Register Class...
1953 const MCPhysReg VK16PAIR[] = {
1954 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1955 };
1956
1957 // VK16PAIR Bit set.
1958 const uint8_t VK16PAIRBits[] = {
1959 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1960 };
1961
1962 // VK1PAIR Register Class...
1963 const MCPhysReg VK1PAIR[] = {
1964 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1965 };
1966
1967 // VK1PAIR Bit set.
1968 const uint8_t VK1PAIRBits[] = {
1969 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1970 };
1971
1972 // VK2PAIR Register Class...
1973 const MCPhysReg VK2PAIR[] = {
1974 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1975 };
1976
1977 // VK2PAIR Bit set.
1978 const uint8_t VK2PAIRBits[] = {
1979 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1980 };
1981
1982 // VK4PAIR Register Class...
1983 const MCPhysReg VK4PAIR[] = {
1984 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1985 };
1986
1987 // VK4PAIR Bit set.
1988 const uint8_t VK4PAIRBits[] = {
1989 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
1990 };
1991
1992 // VK8PAIR Register Class...
1993 const MCPhysReg VK8PAIR[] = {
1994 X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
1995 };
1996
1997 // VK8PAIR Bit set.
1998 const uint8_t VK8PAIRBits[] = {
1999 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
2000 };
2001
2002 // VK1PAIR_with_sub_mask_0_in_VK1WM Register Class...
2003 const MCPhysReg VK1PAIR_with_sub_mask_0_in_VK1WM[] = {
2004 X86::K2_K3, X86::K4_K5, X86::K6_K7,
2005 };
2006
2007 // VK1PAIR_with_sub_mask_0_in_VK1WM Bit set.
2008 const uint8_t VK1PAIR_with_sub_mask_0_in_VK1WMBits[] = {
2009 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
2010 };
2011
2012 // LOW32_ADDR_ACCESS_RBP Register Class...
2013 const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
2014 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R20D, X86::R21D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R28D, X86::R29D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, X86::RBP,
2015 };
2016
2017 // LOW32_ADDR_ACCESS_RBP Bit set.
2018 const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
2019 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
2020 };
2021
2022 // LOW32_ADDR_ACCESS Register Class...
2023 const MCPhysReg LOW32_ADDR_ACCESS[] = {
2024 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R20D, X86::R21D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R28D, X86::R29D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP,
2025 };
2026
2027 // LOW32_ADDR_ACCESS Bit set.
2028 const uint8_t LOW32_ADDR_ACCESSBits[] = {
2029 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
2030 };
2031
2032 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
2033 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
2034 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R20D, X86::R21D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R28D, X86::R29D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP,
2035 };
2036
2037 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
2038 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
2039 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
2040 };
2041
2042 // FR32X Register Class...
2043 const MCPhysReg FR32X[] = {
2044 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
2045 };
2046
2047 // FR32X Bit set.
2048 const uint8_t FR32XBits[] = {
2049 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2050 };
2051
2052 // GR32 Register Class...
2053 const MCPhysReg GR32[] = {
2054 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R20D, X86::R21D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R28D, X86::R29D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
2055 };
2056
2057 // GR32 Bit set.
2058 const uint8_t GR32Bits[] = {
2059 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
2060 };
2061
2062 // GR32_NOSP Register Class...
2063 const MCPhysReg GR32_NOSP[] = {
2064 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R16D, X86::R17D, X86::R18D, X86::R19D, X86::R20D, X86::R21D, X86::R22D, X86::R23D, X86::R24D, X86::R25D, X86::R26D, X86::R27D, X86::R28D, X86::R29D, X86::R30D, X86::R31D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
2065 };
2066
2067 // GR32_NOSP Bit set.
2068 const uint8_t GR32_NOSPBits[] = {
2069 0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
2070 };
2071
2072 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 Register Class...
2073 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2[] = {
2074 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP,
2075 };
2076
2077 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 Bit set.
2078 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits[] = {
2079 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2080 };
2081
2082 // DEBUG_REG Register Class...
2083 const MCPhysReg DEBUG_REG[] = {
2084 X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15,
2085 };
2086
2087 // DEBUG_REG Bit set.
2088 const uint8_t DEBUG_REGBits[] = {
2089 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2090 };
2091
2092 // FR32 Register Class...
2093 const MCPhysReg FR32[] = {
2094 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
2095 };
2096
2097 // FR32 Bit set.
2098 const uint8_t FR32Bits[] = {
2099 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2100 };
2101
2102 // GR32_NOREX2 Register Class...
2103 const MCPhysReg GR32_NOREX2[] = {
2104 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
2105 };
2106
2107 // GR32_NOREX2 Bit set.
2108 const uint8_t GR32_NOREX2Bits[] = {
2109 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2110 };
2111
2112 // GR32_NOREX2_NOSP Register Class...
2113 const MCPhysReg GR32_NOREX2_NOSP[] = {
2114 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
2115 };
2116
2117 // GR32_NOREX2_NOSP Bit set.
2118 const uint8_t GR32_NOREX2_NOSPBits[] = {
2119 0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2120 };
2121
2122 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
2123 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
2124 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP,
2125 };
2126
2127 // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
2128 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
2129 0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10,
2130 };
2131
2132 // GR32_NOREX Register Class...
2133 const MCPhysReg GR32_NOREX[] = {
2134 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP,
2135 };
2136
2137 // GR32_NOREX Bit set.
2138 const uint8_t GR32_NOREXBits[] = {
2139 0x00, 0x00, 0xc0, 0x0f, 0x03,
2140 };
2141
2142 // VK32 Register Class...
2143 const MCPhysReg VK32[] = {
2144 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
2145 };
2146
2147 // VK32 Bit set.
2148 const uint8_t VK32Bits[] = {
2149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2150 };
2151
2152 // GR32_NOREX_NOSP Register Class...
2153 const MCPhysReg GR32_NOREX_NOSP[] = {
2154 X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,
2155 };
2156
2157 // GR32_NOREX_NOSP Bit set.
2158 const uint8_t GR32_NOREX_NOSPBits[] = {
2159 0x00, 0x00, 0xc0, 0x0f, 0x01,
2160 };
2161
2162 // RFP32 Register Class...
2163 const MCPhysReg RFP32[] = {
2164 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
2165 };
2166
2167 // RFP32 Bit set.
2168 const uint8_t RFP32Bits[] = {
2169 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
2170 };
2171
2172 // VK32WM Register Class...
2173 const MCPhysReg VK32WM[] = {
2174 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
2175 };
2176
2177 // VK32WM Bit set.
2178 const uint8_t VK32WMBits[] = {
2179 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
2180 };
2181
2182 // GR32_ABCD Register Class...
2183 const MCPhysReg GR32_ABCD[] = {
2184 X86::EAX, X86::ECX, X86::EDX, X86::EBX,
2185 };
2186
2187 // GR32_ABCD Bit set.
2188 const uint8_t GR32_ABCDBits[] = {
2189 0x00, 0x00, 0x40, 0x0b,
2190 };
2191
2192 // GR32_TC Register Class...
2193 const MCPhysReg GR32_TC[] = {
2194 X86::EAX, X86::ECX, X86::EDX, X86::ESP,
2195 };
2196
2197 // GR32_TC Bit set.
2198 const uint8_t GR32_TCBits[] = {
2199 0x00, 0x00, 0x40, 0x0a, 0x02,
2200 };
2201
2202 // GR32_ABCD_and_GR32_TC Register Class...
2203 const MCPhysReg GR32_ABCD_and_GR32_TC[] = {
2204 X86::EAX, X86::ECX, X86::EDX,
2205 };
2206
2207 // GR32_ABCD_and_GR32_TC Bit set.
2208 const uint8_t GR32_ABCD_and_GR32_TCBits[] = {
2209 0x00, 0x00, 0x40, 0x0a,
2210 };
2211
2212 // GR32_AD Register Class...
2213 const MCPhysReg GR32_AD[] = {
2214 X86::EAX, X86::EDX,
2215 };
2216
2217 // GR32_AD Bit set.
2218 const uint8_t GR32_ADBits[] = {
2219 0x00, 0x00, 0x40, 0x08,
2220 };
2221
2222 // GR32_ArgRef Register Class...
2223 const MCPhysReg GR32_ArgRef[] = {
2224 X86::ECX, X86::EDX,
2225 };
2226
2227 // GR32_ArgRef Bit set.
2228 const uint8_t GR32_ArgRefBits[] = {
2229 0x00, 0x00, 0x00, 0x0a,
2230 };
2231
2232 // GR32_BPSP Register Class...
2233 const MCPhysReg GR32_BPSP[] = {
2234 X86::EBP, X86::ESP,
2235 };
2236
2237 // GR32_BPSP Bit set.
2238 const uint8_t GR32_BPSPBits[] = {
2239 0x00, 0x00, 0x80, 0x00, 0x02,
2240 };
2241
2242 // GR32_BSI Register Class...
2243 const MCPhysReg GR32_BSI[] = {
2244 X86::EBX, X86::ESI,
2245 };
2246
2247 // GR32_BSI Bit set.
2248 const uint8_t GR32_BSIBits[] = {
2249 0x00, 0x00, 0x00, 0x01, 0x01,
2250 };
2251
2252 // GR32_CB Register Class...
2253 const MCPhysReg GR32_CB[] = {
2254 X86::ECX, X86::EBX,
2255 };
2256
2257 // GR32_CB Bit set.
2258 const uint8_t GR32_CBBits[] = {
2259 0x00, 0x00, 0x00, 0x03,
2260 };
2261
2262 // GR32_DC Register Class...
2263 const MCPhysReg GR32_DC[] = {
2264 X86::EDX, X86::ECX,
2265 };
2266
2267 // GR32_DC Bit set.
2268 const uint8_t GR32_DCBits[] = {
2269 0x00, 0x00, 0x00, 0x0a,
2270 };
2271
2272 // GR32_DIBP Register Class...
2273 const MCPhysReg GR32_DIBP[] = {
2274 X86::EDI, X86::EBP,
2275 };
2276
2277 // GR32_DIBP Bit set.
2278 const uint8_t GR32_DIBPBits[] = {
2279 0x00, 0x00, 0x80, 0x04,
2280 };
2281
2282 // GR32_SIDI Register Class...
2283 const MCPhysReg GR32_SIDI[] = {
2284 X86::ESI, X86::EDI,
2285 };
2286
2287 // GR32_SIDI Bit set.
2288 const uint8_t GR32_SIDIBits[] = {
2289 0x00, 0x00, 0x00, 0x04, 0x01,
2290 };
2291
2292 // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
2293 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
2294 X86::RIP, X86::RBP,
2295 };
2296
2297 // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
2298 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
2299 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
2300 };
2301
2302 // CCR Register Class...
2303 const MCPhysReg CCR[] = {
2304 X86::EFLAGS,
2305 };
2306
2307 // CCR Bit set.
2308 const uint8_t CCRBits[] = {
2309 0x00, 0x00, 0x00, 0x10,
2310 };
2311
2312 // DFCCR Register Class...
2313 const MCPhysReg DFCCR[] = {
2314 X86::DF,
2315 };
2316
2317 // DFCCR Bit set.
2318 const uint8_t DFCCRBits[] = {
2319 0x00, 0x40,
2320 };
2321
2322 // GR32_ABCD_and_GR32_BSI Register Class...
2323 const MCPhysReg GR32_ABCD_and_GR32_BSI[] = {
2324 X86::EBX,
2325 };
2326
2327 // GR32_ABCD_and_GR32_BSI Bit set.
2328 const uint8_t GR32_ABCD_and_GR32_BSIBits[] = {
2329 0x00, 0x00, 0x00, 0x01,
2330 };
2331
2332 // GR32_AD_and_GR32_ArgRef Register Class...
2333 const MCPhysReg GR32_AD_and_GR32_ArgRef[] = {
2334 X86::EDX,
2335 };
2336
2337 // GR32_AD_and_GR32_ArgRef Bit set.
2338 const uint8_t GR32_AD_and_GR32_ArgRefBits[] = {
2339 0x00, 0x00, 0x00, 0x08,
2340 };
2341
2342 // GR32_ArgRef_and_GR32_CB Register Class...
2343 const MCPhysReg GR32_ArgRef_and_GR32_CB[] = {
2344 X86::ECX,
2345 };
2346
2347 // GR32_ArgRef_and_GR32_CB Bit set.
2348 const uint8_t GR32_ArgRef_and_GR32_CBBits[] = {
2349 0x00, 0x00, 0x00, 0x02,
2350 };
2351
2352 // GR32_BPSP_and_GR32_DIBP Register Class...
2353 const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = {
2354 X86::EBP,
2355 };
2356
2357 // GR32_BPSP_and_GR32_DIBP Bit set.
2358 const uint8_t GR32_BPSP_and_GR32_DIBPBits[] = {
2359 0x00, 0x00, 0x80,
2360 };
2361
2362 // GR32_BPSP_and_GR32_TC Register Class...
2363 const MCPhysReg GR32_BPSP_and_GR32_TC[] = {
2364 X86::ESP,
2365 };
2366
2367 // GR32_BPSP_and_GR32_TC Bit set.
2368 const uint8_t GR32_BPSP_and_GR32_TCBits[] = {
2369 0x00, 0x00, 0x00, 0x00, 0x02,
2370 };
2371
2372 // GR32_BSI_and_GR32_SIDI Register Class...
2373 const MCPhysReg GR32_BSI_and_GR32_SIDI[] = {
2374 X86::ESI,
2375 };
2376
2377 // GR32_BSI_and_GR32_SIDI Bit set.
2378 const uint8_t GR32_BSI_and_GR32_SIDIBits[] = {
2379 0x00, 0x00, 0x00, 0x00, 0x01,
2380 };
2381
2382 // GR32_DIBP_and_GR32_SIDI Register Class...
2383 const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = {
2384 X86::EDI,
2385 };
2386
2387 // GR32_DIBP_and_GR32_SIDI Bit set.
2388 const uint8_t GR32_DIBP_and_GR32_SIDIBits[] = {
2389 0x00, 0x00, 0x00, 0x04,
2390 };
2391
2392 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
2393 const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
2394 X86::RBP,
2395 };
2396
2397 // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
2398 const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
2399 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2400 };
2401
2402 // LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
2403 const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
2404 X86::RIP,
2405 };
2406
2407 // LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
2408 const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
2409 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2410 };
2411
2412 // RFP64 Register Class...
2413 const MCPhysReg RFP64[] = {
2414 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
2415 };
2416
2417 // RFP64 Bit set.
2418 const uint8_t RFP64Bits[] = {
2419 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
2420 };
2421
2422 // GR64 Register Class...
2423 const MCPhysReg GR64[] = {
2424 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R20, X86::R21, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R28, X86::R29, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
2425 };
2426
2427 // GR64 Bit set.
2428 const uint8_t GR64Bits[] = {
2429 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
2430 };
2431
2432 // FR64X Register Class...
2433 const MCPhysReg FR64X[] = {
2434 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
2435 };
2436
2437 // FR64X Bit set.
2438 const uint8_t FR64XBits[] = {
2439 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2440 };
2441
2442 // GR64_with_sub_8bit Register Class...
2443 const MCPhysReg GR64_with_sub_8bit[] = {
2444 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R20, X86::R21, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R28, X86::R29, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
2445 };
2446
2447 // GR64_with_sub_8bit Bit set.
2448 const uint8_t GR64_with_sub_8bitBits[] = {
2449 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
2450 };
2451
2452 // GR64_NOSP Register Class...
2453 const MCPhysReg GR64_NOSP[] = {
2454 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R16, X86::R17, X86::R18, X86::R19, X86::R20, X86::R21, X86::R22, X86::R23, X86::R24, X86::R25, X86::R26, X86::R27, X86::R28, X86::R29, X86::R30, X86::R31, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
2455 };
2456
2457 // GR64_NOSP Bit set.
2458 const uint8_t GR64_NOSPBits[] = {
2459 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
2460 };
2461
2462 // GR64_NOREX2 Register Class...
2463 const MCPhysReg GR64_NOREX2[] = {
2464 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
2465 };
2466
2467 // GR64_NOREX2 Bit set.
2468 const uint8_t GR64_NOREX2Bits[] = {
2469 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2470 };
2471
2472 // CONTROL_REG Register Class...
2473 const MCPhysReg CONTROL_REG[] = {
2474 X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15,
2475 };
2476
2477 // CONTROL_REG Bit set.
2478 const uint8_t CONTROL_REGBits[] = {
2479 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2480 };
2481
2482 // FR64 Register Class...
2483 const MCPhysReg FR64[] = {
2484 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
2485 };
2486
2487 // FR64 Bit set.
2488 const uint8_t FR64Bits[] = {
2489 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2490 };
2491
2492 // GR64_with_sub_16bit_in_GR16_NOREX2 Register Class...
2493 const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX2[] = {
2494 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
2495 };
2496
2497 // GR64_with_sub_16bit_in_GR16_NOREX2 Bit set.
2498 const uint8_t GR64_with_sub_16bit_in_GR16_NOREX2Bits[] = {
2499 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2500 };
2501
2502 // GR64_NOREX2_NOSP Register Class...
2503 const MCPhysReg GR64_NOREX2_NOSP[] = {
2504 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
2505 };
2506
2507 // GR64_NOREX2_NOSP Bit set.
2508 const uint8_t GR64_NOREX2_NOSPBits[] = {
2509 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2510 };
2511
2512 // GR64PLTSafe Register Class...
2513 const MCPhysReg GR64PLTSafe[] = {
2514 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
2515 };
2516
2517 // GR64PLTSafe Bit set.
2518 const uint8_t GR64PLTSafeBits[] = {
2519 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x79,
2520 };
2521
2522 // GR64_TC Register Class...
2523 const MCPhysReg GR64_TC[] = {
2524 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
2525 };
2526
2527 // GR64_TC Bit set.
2528 const uint8_t GR64_TCBits[] = {
2529 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2530 };
2531
2532 // GR64_NOREX Register Class...
2533 const MCPhysReg GR64_NOREX[] = {
2534 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
2535 };
2536
2537 // GR64_NOREX Bit set.
2538 const uint8_t GR64_NOREXBits[] = {
2539 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35,
2540 };
2541
2542 // GR64_TCW64 Register Class...
2543 const MCPhysReg GR64_TCW64[] = {
2544 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP,
2545 };
2546
2547 // GR64_TCW64 Bit set.
2548 const uint8_t GR64_TCW64Bits[] = {
2549 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
2550 };
2551
2552 // GR64_TC_with_sub_8bit Register Class...
2553 const MCPhysReg GR64_TC_with_sub_8bit[] = {
2554 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP,
2555 };
2556
2557 // GR64_TC_with_sub_8bit Bit set.
2558 const uint8_t GR64_TC_with_sub_8bitBits[] = {
2559 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2560 };
2561
2562 // GR64_NOREX2_NOSP_and_GR64_TC Register Class...
2563 const MCPhysReg GR64_NOREX2_NOSP_and_GR64_TC[] = {
2564 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11,
2565 };
2566
2567 // GR64_NOREX2_NOSP_and_GR64_TC Bit set.
2568 const uint8_t GR64_NOREX2_NOSP_and_GR64_TCBits[] = {
2569 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2570 };
2571
2572 // GR64_TCW64_with_sub_8bit Register Class...
2573 const MCPhysReg GR64_TCW64_with_sub_8bit[] = {
2574 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP,
2575 };
2576
2577 // GR64_TCW64_with_sub_8bit Bit set.
2578 const uint8_t GR64_TCW64_with_sub_8bitBits[] = {
2579 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
2580 };
2581
2582 // GR64_TC_and_GR64_TCW64 Register Class...
2583 const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
2584 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
2585 };
2586
2587 // GR64_TC_and_GR64_TCW64 Bit set.
2588 const uint8_t GR64_TC_and_GR64_TCW64Bits[] = {
2589 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2590 };
2591
2592 // GR64_with_sub_16bit_in_GR16_NOREX Register Class...
2593 const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
2594 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP,
2595 };
2596
2597 // GR64_with_sub_16bit_in_GR16_NOREX Bit set.
2598 const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
2599 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31,
2600 };
2601
2602 // VK64 Register Class...
2603 const MCPhysReg VK64[] = {
2604 X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
2605 };
2606
2607 // VK64 Bit set.
2608 const uint8_t VK64Bits[] = {
2609 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2610 };
2611
2612 // VR64 Register Class...
2613 const MCPhysReg VR64[] = {
2614 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
2615 };
2616
2617 // VR64 Bit set.
2618 const uint8_t VR64Bits[] = {
2619 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2620 };
2621
2622 // GR64PLTSafe_and_GR64_TC Register Class...
2623 const MCPhysReg GR64PLTSafe_and_GR64_TC[] = {
2624 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9,
2625 };
2626
2627 // GR64PLTSafe_and_GR64_TC Bit set.
2628 const uint8_t GR64PLTSafe_and_GR64_TCBits[] = {
2629 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
2630 };
2631
2632 // GR64_NOREX2_NOSP_and_GR64_TCW64 Register Class...
2633 const MCPhysReg GR64_NOREX2_NOSP_and_GR64_TCW64[] = {
2634 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11,
2635 };
2636
2637 // GR64_NOREX2_NOSP_and_GR64_TCW64 Bit set.
2638 const uint8_t GR64_NOREX2_NOSP_and_GR64_TCW64Bits[] = {
2639 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07,
2640 };
2641
2642 // GR64_NOREX_NOSP Register Class...
2643 const MCPhysReg GR64_NOREX_NOSP[] = {
2644 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP,
2645 };
2646
2647 // GR64_NOREX_NOSP Bit set.
2648 const uint8_t GR64_NOREX_NOSPBits[] = {
2649 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11,
2650 };
2651
2652 // GR64_NOREX_and_GR64_TC Register Class...
2653 const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
2654 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP,
2655 };
2656
2657 // GR64_NOREX_and_GR64_TC Bit set.
2658 const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
2659 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35,
2660 };
2661
2662 // GR64_TCW64_and_GR64_TC_with_sub_8bit Register Class...
2663 const MCPhysReg GR64_TCW64_and_GR64_TC_with_sub_8bit[] = {
2664 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP,
2665 };
2666
2667 // GR64_TCW64_and_GR64_TC_with_sub_8bit Bit set.
2668 const uint8_t GR64_TCW64_and_GR64_TC_with_sub_8bitBits[] = {
2669 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2670 };
2671
2672 // VK64WM Register Class...
2673 const MCPhysReg VK64WM[] = {
2674 X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
2675 };
2676
2677 // VK64WM Bit set.
2678 const uint8_t VK64WMBits[] = {
2679 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
2680 };
2681
2682 // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 Register Class...
2683 const MCPhysReg GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64[] = {
2684 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11,
2685 };
2686
2687 // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 Bit set.
2688 const uint8_t GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits[] = {
2689 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05,
2690 };
2691
2692 // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Register Class...
2693 const MCPhysReg GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX[] = {
2694 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP,
2695 };
2696
2697 // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Bit set.
2698 const uint8_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
2699 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31,
2700 };
2701
2702 // GR64PLTSafe_and_GR64_TCW64 Register Class...
2703 const MCPhysReg GR64PLTSafe_and_GR64_TCW64[] = {
2704 X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9,
2705 };
2706
2707 // GR64PLTSafe_and_GR64_TCW64 Bit set.
2708 const uint8_t GR64PLTSafe_and_GR64_TCW64Bits[] = {
2709 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01,
2710 };
2711
2712 // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Register Class...
2713 const MCPhysReg GR64_NOREX_and_GR64PLTSafe_and_GR64_TC[] = {
2714 X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI,
2715 };
2716
2717 // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Bit set.
2718 const uint8_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits[] = {
2719 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11,
2720 };
2721
2722 // GR64_NOREX_and_GR64_TCW64 Register Class...
2723 const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
2724 X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP,
2725 };
2726
2727 // GR64_NOREX_and_GR64_TCW64 Bit set.
2728 const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = {
2729 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25,
2730 };
2731
2732 // GR64_ABCD Register Class...
2733 const MCPhysReg GR64_ABCD[] = {
2734 X86::RAX, X86::RCX, X86::RDX, X86::RBX,
2735 };
2736
2737 // GR64_ABCD Bit set.
2738 const uint8_t GR64_ABCDBits[] = {
2739 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0x01,
2740 };
2741
2742 // GR64_with_sub_32bit_in_GR32_TC Register Class...
2743 const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
2744 X86::RAX, X86::RCX, X86::RDX, X86::RSP,
2745 };
2746
2747 // GR64_with_sub_32bit_in_GR32_TC Bit set.
2748 const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
2749 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21,
2750 };
2751
2752 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Register Class...
2753 const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC[] = {
2754 X86::RAX, X86::RCX, X86::RDX,
2755 };
2756
2757 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Bit set.
2758 const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits[] = {
2759 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01,
2760 };
2761
2762 // GR64_AD Register Class...
2763 const MCPhysReg GR64_AD[] = {
2764 X86::RAX, X86::RDX,
2765 };
2766
2767 // GR64_AD Bit set.
2768 const uint8_t GR64_ADBits[] = {
2769 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01,
2770 };
2771
2772 // GR64_ArgRef Register Class...
2773 const MCPhysReg GR64_ArgRef[] = {
2774 X86::R10, X86::R11,
2775 };
2776
2777 // GR64_ArgRef Bit set.
2778 const uint8_t GR64_ArgRefBits[] = {
2779 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06,
2780 };
2781
2782 // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class...
2783 const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
2784 X86::RBP, X86::RIP,
2785 };
2786
2787 // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set.
2788 const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = {
2789 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
2790 };
2791
2792 // GR64_with_sub_32bit_in_GR32_ArgRef Register Class...
2793 const MCPhysReg GR64_with_sub_32bit_in_GR32_ArgRef[] = {
2794 X86::RCX, X86::RDX,
2795 };
2796
2797 // GR64_with_sub_32bit_in_GR32_ArgRef Bit set.
2798 const uint8_t GR64_with_sub_32bit_in_GR32_ArgRefBits[] = {
2799 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01,
2800 };
2801
2802 // GR64_with_sub_32bit_in_GR32_BPSP Register Class...
2803 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP[] = {
2804 X86::RBP, X86::RSP,
2805 };
2806
2807 // GR64_with_sub_32bit_in_GR32_BPSP Bit set.
2808 const uint8_t GR64_with_sub_32bit_in_GR32_BPSPBits[] = {
2809 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x20,
2810 };
2811
2812 // GR64_with_sub_32bit_in_GR32_BSI Register Class...
2813 const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI[] = {
2814 X86::RSI, X86::RBX,
2815 };
2816
2817 // GR64_with_sub_32bit_in_GR32_BSI Bit set.
2818 const uint8_t GR64_with_sub_32bit_in_GR32_BSIBits[] = {
2819 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x10,
2820 };
2821
2822 // GR64_with_sub_32bit_in_GR32_CB Register Class...
2823 const MCPhysReg GR64_with_sub_32bit_in_GR32_CB[] = {
2824 X86::RCX, X86::RBX,
2825 };
2826
2827 // GR64_with_sub_32bit_in_GR32_CB Bit set.
2828 const uint8_t GR64_with_sub_32bit_in_GR32_CBBits[] = {
2829 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
2830 };
2831
2832 // GR64_with_sub_32bit_in_GR32_DIBP Register Class...
2833 const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP[] = {
2834 X86::RDI, X86::RBP,
2835 };
2836
2837 // GR64_with_sub_32bit_in_GR32_DIBP Bit set.
2838 const uint8_t GR64_with_sub_32bit_in_GR32_DIBPBits[] = {
2839 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90,
2840 };
2841
2842 // GR64_with_sub_32bit_in_GR32_SIDI Register Class...
2843 const MCPhysReg GR64_with_sub_32bit_in_GR32_SIDI[] = {
2844 X86::RSI, X86::RDI,
2845 };
2846
2847 // GR64_with_sub_32bit_in_GR32_SIDI Bit set.
2848 const uint8_t GR64_with_sub_32bit_in_GR32_SIDIBits[] = {
2849 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10,
2850 };
2851
2852 // GR64_ArgRef_and_GR64_TC Register Class...
2853 const MCPhysReg GR64_ArgRef_and_GR64_TC[] = {
2854 X86::R11,
2855 };
2856
2857 // GR64_ArgRef_and_GR64_TC Bit set.
2858 const uint8_t GR64_ArgRef_and_GR64_TCBits[] = {
2859 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2860 };
2861
2862 // GR64_and_LOW32_ADDR_ACCESS Register Class...
2863 const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
2864 X86::RIP,
2865 };
2866
2867 // GR64_and_LOW32_ADDR_ACCESS Bit set.
2868 const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = {
2869 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2870 };
2871
2872 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Register Class...
2873 const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI[] = {
2874 X86::RBX,
2875 };
2876
2877 // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Bit set.
2878 const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits[] = {
2879 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2880 };
2881
2882 // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef Register Class...
2883 const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef[] = {
2884 X86::RDX,
2885 };
2886
2887 // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef Bit set.
2888 const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits[] = {
2889 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
2890 };
2891
2892 // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB Register Class...
2893 const MCPhysReg GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB[] = {
2894 X86::RCX,
2895 };
2896
2897 // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB Bit set.
2898 const uint8_t GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits[] = {
2899 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2900 };
2901
2902 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Register Class...
2903 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP[] = {
2904 X86::RBP,
2905 };
2906
2907 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Bit set.
2908 const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits[] = {
2909 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2910 };
2911
2912 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Register Class...
2913 const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC[] = {
2914 X86::RSP,
2915 };
2916
2917 // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Bit set.
2918 const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits[] = {
2919 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2920 };
2921
2922 // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Register Class...
2923 const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI[] = {
2924 X86::RSI,
2925 };
2926
2927 // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Bit set.
2928 const uint8_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits[] = {
2929 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2930 };
2931
2932 // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Register Class...
2933 const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI[] = {
2934 X86::RDI,
2935 };
2936
2937 // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Bit set.
2938 const uint8_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits[] = {
2939 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
2940 };
2941
2942 // RST Register Class...
2943 const MCPhysReg RST[] = {
2944 X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
2945 };
2946
2947 // RST Bit set.
2948 const uint8_t RSTBits[] = {
2949 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
2950 };
2951
2952 // RFP80 Register Class...
2953 const MCPhysReg RFP80[] = {
2954 X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
2955 };
2956
2957 // RFP80 Bit set.
2958 const uint8_t RFP80Bits[] = {
2959 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
2960 };
2961
2962 // RFP80_7 Register Class...
2963 const MCPhysReg RFP80_7[] = {
2964 X86::FP7,
2965 };
2966
2967 // RFP80_7 Bit set.
2968 const uint8_t RFP80_7Bits[] = {
2969 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2970 };
2971
2972 // VR128X Register Class...
2973 const MCPhysReg VR128X[] = {
2974 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
2975 };
2976
2977 // VR128X Bit set.
2978 const uint8_t VR128XBits[] = {
2979 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2980 };
2981
2982 // VR128 Register Class...
2983 const MCPhysReg VR128[] = {
2984 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
2985 };
2986
2987 // VR128 Bit set.
2988 const uint8_t VR128Bits[] = {
2989 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2990 };
2991
2992 // VR256X Register Class...
2993 const MCPhysReg VR256X[] = {
2994 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31,
2995 };
2996
2997 // VR256X Bit set.
2998 const uint8_t VR256XBits[] = {
2999 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x80, 0xff, 0x7f,
3000 };
3001
3002 // VR256 Register Class...
3003 const MCPhysReg VR256[] = {
3004 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15,
3005 };
3006
3007 // VR256 Bit set.
3008 const uint8_t VR256Bits[] = {
3009 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
3010 };
3011
3012 // VR512 Register Class...
3013 const MCPhysReg VR512[] = {
3014 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31,
3015 };
3016
3017 // VR512 Bit set.
3018 const uint8_t VR512Bits[] = {
3019 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
3020 };
3021
3022 // VR512_0_15 Register Class...
3023 const MCPhysReg VR512_0_15[] = {
3024 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15,
3025 };
3026
3027 // VR512_0_15 Bit set.
3028 const uint8_t VR512_0_15Bits[] = {
3029 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
3030 };
3031
3032 // TILE Register Class...
3033 const MCPhysReg TILE[] = {
3034 X86::TMM0, X86::TMM1, X86::TMM2, X86::TMM3, X86::TMM4, X86::TMM5, X86::TMM6, X86::TMM7,
3035 };
3036
3037 // TILE Bit set.
3038 const uint8_t TILEBits[] = {
3039 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
3040 };
3041
3042} // end anonymous namespace
3043
3044
3045#ifdef __GNUC__
3046#pragma GCC diagnostic push
3047#pragma GCC diagnostic ignored "-Woverlength-strings"
3048#endif
3049extern const char X86RegClassStrings[] = {
3050 /* 0 */ "RFP80\0"
3051 /* 6 */ "VK1\0"
3052 /* 10 */ "VR512\0"
3053 /* 16 */ "VK32\0"
3054 /* 21 */ "RFP32\0"
3055 /* 27 */ "FR32\0"
3056 /* 32 */ "GR32\0"
3057 /* 37 */ "VK2\0"
3058 /* 41 */ "GR32_NOREX2\0"
3059 /* 53 */ "GR64_NOREX2\0"
3060 /* 65 */ "GR64_with_sub_16bit_in_GR16_NOREX2\0"
3061 /* 100 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2\0"
3062 /* 152 */ "GR8_NOREX2\0"
3063 /* 163 */ "VK64\0"
3064 /* 168 */ "RFP64\0"
3065 /* 174 */ "FR64\0"
3066 /* 179 */ "GR64\0"
3067 /* 184 */ "VR64\0"
3068 /* 189 */ "GR64_TC_and_GR64_TCW64\0"
3069 /* 212 */ "GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64\0"
3070 /* 256 */ "GR64_NOREX_and_GR64_TCW64\0"
3071 /* 282 */ "GR64PLTSafe_and_GR64_TCW64\0"
3072 /* 309 */ "VK4\0"
3073 /* 313 */ "VR512_0_15\0"
3074 /* 324 */ "GRH16\0"
3075 /* 330 */ "VK16\0"
3076 /* 335 */ "FR16\0"
3077 /* 340 */ "GR16\0"
3078 /* 345 */ "VR256\0"
3079 /* 351 */ "RFP80_7\0"
3080 /* 359 */ "VR128\0"
3081 /* 365 */ "GRH8\0"
3082 /* 370 */ "VK8\0"
3083 /* 374 */ "GR8\0"
3084 /* 378 */ "GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB\0"
3085 /* 425 */ "GR64_with_sub_32bit_in_GR32_CB\0"
3086 /* 456 */ "GR32_DC\0"
3087 /* 464 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC\0"
3088 /* 509 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC\0"
3089 /* 554 */ "GR64_with_sub_32bit_in_GR32_TC\0"
3090 /* 585 */ "GR64_NOREX2_NOSP_and_GR64_TC\0"
3091 /* 614 */ "GR64_NOREX_and_GR64_TC\0"
3092 /* 637 */ "GR64_NOREX_and_GR64PLTSafe_and_GR64_TC\0"
3093 /* 676 */ "GR64_ArgRef_and_GR64_TC\0"
3094 /* 700 */ "GR32_AD\0"
3095 /* 708 */ "GR64_AD\0"
3096 /* 716 */ "GR32_ABCD\0"
3097 /* 726 */ "GR64_ABCD\0"
3098 /* 736 */ "GR16_ABCD\0"
3099 /* 746 */ "TILE\0"
3100 /* 751 */ "DEBUG_REG\0"
3101 /* 761 */ "CONTROL_REG\0"
3102 /* 773 */ "SEGMENT_REG\0"
3103 /* 785 */ "GR8_ABCD_H\0"
3104 /* 796 */ "GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI\0"
3105 /* 842 */ "GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI\0"
3106 /* 889 */ "GR64_with_sub_32bit_in_GR32_SIDI\0"
3107 /* 922 */ "GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI\0"
3108 /* 968 */ "GR64_with_sub_32bit_in_GR32_BSI\0"
3109 /* 1000 */ "GR8_ABCD_L\0"
3110 /* 1011 */ "VK1PAIR_with_sub_mask_0_in_VK1WM\0"
3111 /* 1044 */ "VK32WM\0"
3112 /* 1051 */ "VK2WM\0"
3113 /* 1057 */ "VK64WM\0"
3114 /* 1064 */ "VK4WM\0"
3115 /* 1070 */ "VK16WM\0"
3116 /* 1077 */ "VK8WM\0"
3117 /* 1083 */ "GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP\0"
3118 /* 1130 */ "GR64_with_sub_32bit_in_GR32_DIBP\0"
3119 /* 1163 */ "GR64_and_LOW32_ADDR_ACCESS_RBP\0"
3120 /* 1194 */ "GR32_NOSP\0"
3121 /* 1204 */ "GR32_NOREX2_NOSP\0"
3122 /* 1221 */ "GR64_NOREX2_NOSP\0"
3123 /* 1238 */ "GR64_NOSP\0"
3124 /* 1248 */ "GR32_NOREX_NOSP\0"
3125 /* 1264 */ "GR64_NOREX_NOSP\0"
3126 /* 1280 */ "GR64_with_sub_32bit_in_GR32_BPSP\0"
3127 /* 1313 */ "DFCCR\0"
3128 /* 1319 */ "FPCCR\0"
3129 /* 1325 */ "VK1PAIR\0"
3130 /* 1333 */ "VK2PAIR\0"
3131 /* 1341 */ "VK4PAIR\0"
3132 /* 1349 */ "VK16PAIR\0"
3133 /* 1358 */ "VK8PAIR\0"
3134 /* 1366 */ "GR64_and_LOW32_ADDR_ACCESS\0"
3135 /* 1393 */ "RST\0"
3136 /* 1397 */ "FR32X\0"
3137 /* 1403 */ "FR64X\0"
3138 /* 1409 */ "FR16X\0"
3139 /* 1415 */ "VR256X\0"
3140 /* 1422 */ "VR128X\0"
3141 /* 1429 */ "GR32_NOREX\0"
3142 /* 1440 */ "GR64_NOREX\0"
3143 /* 1451 */ "GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX\0"
3144 /* 1497 */ "LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX\0"
3145 /* 1548 */ "GR8_NOREX\0"
3146 /* 1558 */ "GR64PLTSafe\0"
3147 /* 1570 */ "GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef\0"
3148 /* 1617 */ "GR64_with_sub_32bit_in_GR32_ArgRef\0"
3149 /* 1652 */ "GR64_ArgRef\0"
3150 /* 1664 */ "LOW32_ADDR_ACCESS_RBP_with_sub_32bit\0"
3151 /* 1701 */ "LOW32_ADDR_ACCESS_with_sub_32bit\0"
3152 /* 1734 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit\0"
3153 /* 1785 */ "GR64_with_sub_8bit\0"
3154 /* 1804 */ "GR64_TCW64_with_sub_8bit\0"
3155 /* 1829 */ "GR64_TCW64_and_GR64_TC_with_sub_8bit\0"
3156 /* 1866 */ "LOW32_ADDR_ACCESS_RBP_with_sub_8bit\0"
3157};
3158#ifdef __GNUC__
3159#pragma GCC diagnostic pop
3160#endif
3161
3162extern const MCRegisterClass X86MCRegisterClasses[] = {
3163 { GR8, GR8Bits, 374, 36, sizeof(GR8Bits), X86::GR8RegClassID, 8, 1, true, false },
3164 { GRH8, GRH8Bits, 365, 28, sizeof(GRH8Bits), X86::GRH8RegClassID, 8, 1, false, false },
3165 { GR8_NOREX2, GR8_NOREX2Bits, 152, 20, sizeof(GR8_NOREX2Bits), X86::GR8_NOREX2RegClassID, 8, 1, true, false },
3166 { GR8_NOREX, GR8_NOREXBits, 1548, 8, sizeof(GR8_NOREXBits), X86::GR8_NOREXRegClassID, 8, 1, true, false },
3167 { GR8_ABCD_H, GR8_ABCD_HBits, 785, 4, sizeof(GR8_ABCD_HBits), X86::GR8_ABCD_HRegClassID, 8, 1, true, false },
3168 { GR8_ABCD_L, GR8_ABCD_LBits, 1000, 4, sizeof(GR8_ABCD_LBits), X86::GR8_ABCD_LRegClassID, 8, 1, true, false },
3169 { GRH16, GRH16Bits, 324, 33, sizeof(GRH16Bits), X86::GRH16RegClassID, 16, 1, false, false },
3170 { GR16, GR16Bits, 340, 32, sizeof(GR16Bits), X86::GR16RegClassID, 16, 1, true, false },
3171 { GR16_NOREX2, GR16_NOREX2Bits, 88, 16, sizeof(GR16_NOREX2Bits), X86::GR16_NOREX2RegClassID, 16, 1, true, false },
3172 { GR16_NOREX, GR16_NOREXBits, 1486, 8, sizeof(GR16_NOREXBits), X86::GR16_NOREXRegClassID, 16, 1, true, false },
3173 { VK1, VK1Bits, 6, 8, sizeof(VK1Bits), X86::VK1RegClassID, 16, 1, true, false },
3174 { VK16, VK16Bits, 330, 8, sizeof(VK16Bits), X86::VK16RegClassID, 16, 1, true, false },
3175 { VK2, VK2Bits, 37, 8, sizeof(VK2Bits), X86::VK2RegClassID, 16, 1, true, false },
3176 { VK4, VK4Bits, 309, 8, sizeof(VK4Bits), X86::VK4RegClassID, 16, 1, true, false },
3177 { VK8, VK8Bits, 370, 8, sizeof(VK8Bits), X86::VK8RegClassID, 16, 1, true, false },
3178 { VK16WM, VK16WMBits, 1070, 7, sizeof(VK16WMBits), X86::VK16WMRegClassID, 16, 1, true, false },
3179 { VK1WM, VK1WMBits, 1038, 7, sizeof(VK1WMBits), X86::VK1WMRegClassID, 16, 1, true, false },
3180 { VK2WM, VK2WMBits, 1051, 7, sizeof(VK2WMBits), X86::VK2WMRegClassID, 16, 1, true, false },
3181 { VK4WM, VK4WMBits, 1064, 7, sizeof(VK4WMBits), X86::VK4WMRegClassID, 16, 1, true, false },
3182 { VK8WM, VK8WMBits, 1077, 7, sizeof(VK8WMBits), X86::VK8WMRegClassID, 16, 1, true, false },
3183 { SEGMENT_REG, SEGMENT_REGBits, 773, 6, sizeof(SEGMENT_REGBits), X86::SEGMENT_REGRegClassID, 16, 1, true, false },
3184 { GR16_ABCD, GR16_ABCDBits, 736, 4, sizeof(GR16_ABCDBits), X86::GR16_ABCDRegClassID, 16, 1, true, false },
3185 { FPCCR, FPCCRBits, 1319, 1, sizeof(FPCCRBits), X86::FPCCRRegClassID, 16, -1, false, false },
3186 { FR16X, FR16XBits, 1409, 32, sizeof(FR16XBits), X86::FR16XRegClassID, 32, 1, true, false },
3187 { FR16, FR16Bits, 335, 16, sizeof(FR16Bits), X86::FR16RegClassID, 32, 1, true, false },
3188 { VK16PAIR, VK16PAIRBits, 1349, 4, sizeof(VK16PAIRBits), X86::VK16PAIRRegClassID, 32, 1, true, false },
3189 { VK1PAIR, VK1PAIRBits, 1325, 4, sizeof(VK1PAIRBits), X86::VK1PAIRRegClassID, 32, 1, true, false },
3190 { VK2PAIR, VK2PAIRBits, 1333, 4, sizeof(VK2PAIRBits), X86::VK2PAIRRegClassID, 32, 1, true, false },
3191 { VK4PAIR, VK4PAIRBits, 1341, 4, sizeof(VK4PAIRBits), X86::VK4PAIRRegClassID, 32, 1, true, false },
3192 { VK8PAIR, VK8PAIRBits, 1358, 4, sizeof(VK8PAIRBits), X86::VK8PAIRRegClassID, 32, 1, true, false },
3193 { VK1PAIR_with_sub_mask_0_in_VK1WM, VK1PAIR_with_sub_mask_0_in_VK1WMBits, 1011, 3, sizeof(VK1PAIR_with_sub_mask_0_in_VK1WMBits), X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID, 32, 1, true, false },
3194 { LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, 1172, 34, sizeof(LOW32_ADDR_ACCESS_RBPBits), X86::LOW32_ADDR_ACCESS_RBPRegClassID, 32, 1, true, false },
3195 { LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, 1375, 33, sizeof(LOW32_ADDR_ACCESSBits), X86::LOW32_ADDR_ACCESSRegClassID, 32, 1, true, false },
3196 { LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, 1866, 33, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 32, 1, true, false },
3197 { FR32X, FR32XBits, 1397, 32, sizeof(FR32XBits), X86::FR32XRegClassID, 32, 1, true, false },
3198 { GR32, GR32Bits, 32, 32, sizeof(GR32Bits), X86::GR32RegClassID, 32, 1, true, false },
3199 { GR32_NOSP, GR32_NOSPBits, 1194, 31, sizeof(GR32_NOSPBits), X86::GR32_NOSPRegClassID, 32, 1, true, false },
3200 { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits, 100, 17, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Bits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID, 32, 1, true, false },
3201 { DEBUG_REG, DEBUG_REGBits, 751, 16, sizeof(DEBUG_REGBits), X86::DEBUG_REGRegClassID, 32, 1, true, false },
3202 { FR32, FR32Bits, 27, 16, sizeof(FR32Bits), X86::FR32RegClassID, 32, 1, true, false },
3203 { GR32_NOREX2, GR32_NOREX2Bits, 41, 16, sizeof(GR32_NOREX2Bits), X86::GR32_NOREX2RegClassID, 32, 1, true, false },
3204 { GR32_NOREX2_NOSP, GR32_NOREX2_NOSPBits, 1204, 15, sizeof(GR32_NOREX2_NOSPBits), X86::GR32_NOREX2_NOSPRegClassID, 32, 1, true, false },
3205 { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, 1497, 9, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, 32, 1, true, false },
3206 { GR32_NOREX, GR32_NOREXBits, 1429, 8, sizeof(GR32_NOREXBits), X86::GR32_NOREXRegClassID, 32, 1, true, false },
3207 { VK32, VK32Bits, 16, 8, sizeof(VK32Bits), X86::VK32RegClassID, 32, 1, true, false },
3208 { GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, 1248, 7, sizeof(GR32_NOREX_NOSPBits), X86::GR32_NOREX_NOSPRegClassID, 32, 1, true, false },
3209 { RFP32, RFP32Bits, 21, 7, sizeof(RFP32Bits), X86::RFP32RegClassID, 32, 1, true, false },
3210 { VK32WM, VK32WMBits, 1044, 7, sizeof(VK32WMBits), X86::VK32WMRegClassID, 32, 1, true, false },
3211 { GR32_ABCD, GR32_ABCDBits, 716, 4, sizeof(GR32_ABCDBits), X86::GR32_ABCDRegClassID, 32, 1, true, false },
3212 { GR32_TC, GR32_TCBits, 501, 4, sizeof(GR32_TCBits), X86::GR32_TCRegClassID, 32, 1, true, false },
3213 { GR32_ABCD_and_GR32_TC, GR32_ABCD_and_GR32_TCBits, 487, 3, sizeof(GR32_ABCD_and_GR32_TCBits), X86::GR32_ABCD_and_GR32_TCRegClassID, 32, 1, true, false },
3214 { GR32_AD, GR32_ADBits, 700, 2, sizeof(GR32_ADBits), X86::GR32_ADRegClassID, 32, 1, true, false },
3215 { GR32_ArgRef, GR32_ArgRefBits, 1605, 2, sizeof(GR32_ArgRefBits), X86::GR32_ArgRefRegClassID, 32, 1, true, false },
3216 { GR32_BPSP, GR32_BPSPBits, 1303, 2, sizeof(GR32_BPSPBits), X86::GR32_BPSPRegClassID, 32, 1, true, false },
3217 { GR32_BSI, GR32_BSIBits, 959, 2, sizeof(GR32_BSIBits), X86::GR32_BSIRegClassID, 32, 1, true, false },
3218 { GR32_CB, GR32_CBBits, 417, 2, sizeof(GR32_CBBits), X86::GR32_CBRegClassID, 32, 1, true, false },
3219 { GR32_DC, GR32_DCBits, 456, 2, sizeof(GR32_DCBits), X86::GR32_DCRegClassID, 32, 1, true, false },
3220 { GR32_DIBP, GR32_DIBPBits, 1120, 2, sizeof(GR32_DIBPBits), X86::GR32_DIBPRegClassID, 32, 1, true, false },
3221 { GR32_SIDI, GR32_SIDIBits, 832, 2, sizeof(GR32_SIDIBits), X86::GR32_SIDIRegClassID, 32, 1, true, false },
3222 { LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, 1664, 2, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, 32, 1, true, false },
3223 { CCR, CCRBits, 1315, 1, sizeof(CCRBits), X86::CCRRegClassID, 32, -1, false, false },
3224 { DFCCR, DFCCRBits, 1313, 1, sizeof(DFCCRBits), X86::DFCCRRegClassID, 32, -1, false, false },
3225 { GR32_ABCD_and_GR32_BSI, GR32_ABCD_and_GR32_BSIBits, 945, 1, sizeof(GR32_ABCD_and_GR32_BSIBits), X86::GR32_ABCD_and_GR32_BSIRegClassID, 32, 1, true, false },
3226 { GR32_AD_and_GR32_ArgRef, GR32_AD_and_GR32_ArgRefBits, 1593, 1, sizeof(GR32_AD_and_GR32_ArgRefBits), X86::GR32_AD_and_GR32_ArgRefRegClassID, 32, 1, true, false },
3227 { GR32_ArgRef_and_GR32_CB, GR32_ArgRef_and_GR32_CBBits, 401, 1, sizeof(GR32_ArgRef_and_GR32_CBBits), X86::GR32_ArgRef_and_GR32_CBRegClassID, 32, 1, true, false },
3228 { GR32_BPSP_and_GR32_DIBP, GR32_BPSP_and_GR32_DIBPBits, 1106, 1, sizeof(GR32_BPSP_and_GR32_DIBPBits), X86::GR32_BPSP_and_GR32_DIBPRegClassID, 32, 1, true, false },
3229 { GR32_BPSP_and_GR32_TC, GR32_BPSP_and_GR32_TCBits, 532, 1, sizeof(GR32_BPSP_and_GR32_TCBits), X86::GR32_BPSP_and_GR32_TCRegClassID, 32, 1, true, false },
3230 { GR32_BSI_and_GR32_SIDI, GR32_BSI_and_GR32_SIDIBits, 819, 1, sizeof(GR32_BSI_and_GR32_SIDIBits), X86::GR32_BSI_and_GR32_SIDIRegClassID, 32, 1, true, false },
3231 { GR32_DIBP_and_GR32_SIDI, GR32_DIBP_and_GR32_SIDIBits, 865, 1, sizeof(GR32_DIBP_and_GR32_SIDIBits), X86::GR32_DIBP_and_GR32_SIDIRegClassID, 32, 1, true, false },
3232 { LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, 1734, 1, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, 32, 1, true, false },
3233 { LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, 1701, 1, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, 32, 1, true, false },
3234 { RFP64, RFP64Bits, 168, 7, sizeof(RFP64Bits), X86::RFP64RegClassID, 64, 1, true, false },
3235 { GR64, GR64Bits, 179, 33, sizeof(GR64Bits), X86::GR64RegClassID, 64, 1, true, false },
3236 { FR64X, FR64XBits, 1403, 32, sizeof(FR64XBits), X86::FR64XRegClassID, 64, 1, true, false },
3237 { GR64_with_sub_8bit, GR64_with_sub_8bitBits, 1785, 32, sizeof(GR64_with_sub_8bitBits), X86::GR64_with_sub_8bitRegClassID, 64, 1, true, false },
3238 { GR64_NOSP, GR64_NOSPBits, 1238, 31, sizeof(GR64_NOSPBits), X86::GR64_NOSPRegClassID, 64, 1, true, false },
3239 { GR64_NOREX2, GR64_NOREX2Bits, 53, 17, sizeof(GR64_NOREX2Bits), X86::GR64_NOREX2RegClassID, 64, 1, true, false },
3240 { CONTROL_REG, CONTROL_REGBits, 761, 16, sizeof(CONTROL_REGBits), X86::CONTROL_REGRegClassID, 64, 1, true, false },
3241 { FR64, FR64Bits, 174, 16, sizeof(FR64Bits), X86::FR64RegClassID, 64, 1, true, false },
3242 { GR64_with_sub_16bit_in_GR16_NOREX2, GR64_with_sub_16bit_in_GR16_NOREX2Bits, 65, 16, sizeof(GR64_with_sub_16bit_in_GR16_NOREX2Bits), X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClassID, 64, 1, true, false },
3243 { GR64_NOREX2_NOSP, GR64_NOREX2_NOSPBits, 1221, 15, sizeof(GR64_NOREX2_NOSPBits), X86::GR64_NOREX2_NOSPRegClassID, 64, 1, true, false },
3244 { GR64PLTSafe, GR64PLTSafeBits, 1558, 13, sizeof(GR64PLTSafeBits), X86::GR64PLTSafeRegClassID, 64, 1, true, false },
3245 { GR64_TC, GR64_TCBits, 606, 10, sizeof(GR64_TCBits), X86::GR64_TCRegClassID, 64, 1, true, false },
3246 { GR64_NOREX, GR64_NOREXBits, 1440, 9, sizeof(GR64_NOREXBits), X86::GR64_NOREXRegClassID, 64, 1, true, false },
3247 { GR64_TCW64, GR64_TCW64Bits, 201, 9, sizeof(GR64_TCW64Bits), X86::GR64_TCW64RegClassID, 64, 1, true, false },
3248 { GR64_TC_with_sub_8bit, GR64_TC_with_sub_8bitBits, 1844, 9, sizeof(GR64_TC_with_sub_8bitBits), X86::GR64_TC_with_sub_8bitRegClassID, 64, 1, true, false },
3249 { GR64_NOREX2_NOSP_and_GR64_TC, GR64_NOREX2_NOSP_and_GR64_TCBits, 585, 8, sizeof(GR64_NOREX2_NOSP_and_GR64_TCBits), X86::GR64_NOREX2_NOSP_and_GR64_TCRegClassID, 64, 1, true, false },
3250 { GR64_TCW64_with_sub_8bit, GR64_TCW64_with_sub_8bitBits, 1804, 8, sizeof(GR64_TCW64_with_sub_8bitBits), X86::GR64_TCW64_with_sub_8bitRegClassID, 64, 1, true, false },
3251 { GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, 189, 8, sizeof(GR64_TC_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_TCW64RegClassID, 64, 1, true, false },
3252 { GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, 1463, 8, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 64, 1, true, false },
3253 { VK64, VK64Bits, 163, 8, sizeof(VK64Bits), X86::VK64RegClassID, 64, 1, true, false },
3254 { VR64, VR64Bits, 184, 8, sizeof(VR64Bits), X86::VR64RegClassID, 64, 1, true, false },
3255 { GR64PLTSafe_and_GR64_TC, GR64PLTSafe_and_GR64_TCBits, 652, 7, sizeof(GR64PLTSafe_and_GR64_TCBits), X86::GR64PLTSafe_and_GR64_TCRegClassID, 64, 1, true, false },
3256 { GR64_NOREX2_NOSP_and_GR64_TCW64, GR64_NOREX2_NOSP_and_GR64_TCW64Bits, 224, 7, sizeof(GR64_NOREX2_NOSP_and_GR64_TCW64Bits), X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, 64, 1, true, false },
3257 { GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, 1264, 7, sizeof(GR64_NOREX_NOSPBits), X86::GR64_NOREX_NOSPRegClassID, 64, 1, true, false },
3258 { GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, 614, 7, sizeof(GR64_NOREX_and_GR64_TCBits), X86::GR64_NOREX_and_GR64_TCRegClassID, 64, 1, true, false },
3259 { GR64_TCW64_and_GR64_TC_with_sub_8bit, GR64_TCW64_and_GR64_TC_with_sub_8bitBits, 1829, 7, sizeof(GR64_TCW64_and_GR64_TC_with_sub_8bitBits), X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, 64, 1, true, false },
3260 { VK64WM, VK64WMBits, 1057, 7, sizeof(VK64WMBits), X86::VK64WMRegClassID, 64, 1, true, false },
3261 { GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits, 212, 6, sizeof(GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID, 64, 1, true, false },
3262 { GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX, GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits, 1451, 6, sizeof(GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 64, 1, true, false },
3263 { GR64PLTSafe_and_GR64_TCW64, GR64PLTSafe_and_GR64_TCW64Bits, 282, 5, sizeof(GR64PLTSafe_and_GR64_TCW64Bits), X86::GR64PLTSafe_and_GR64_TCW64RegClassID, 64, 1, true, false },
3264 { GR64_NOREX_and_GR64PLTSafe_and_GR64_TC, GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits, 637, 5, sizeof(GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits), X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, 64, 1, true, false },
3265 { GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, 256, 5, sizeof(GR64_NOREX_and_GR64_TCW64Bits), X86::GR64_NOREX_and_GR64_TCW64RegClassID, 64, 1, true, false },
3266 { GR64_ABCD, GR64_ABCDBits, 726, 4, sizeof(GR64_ABCDBits), X86::GR64_ABCDRegClassID, 64, 1, true, false },
3267 { GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, 554, 4, sizeof(GR64_with_sub_32bit_in_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, 64, 1, true, false },
3268 { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits, 464, 3, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, 64, 1, true, false },
3269 { GR64_AD, GR64_ADBits, 708, 2, sizeof(GR64_ADBits), X86::GR64_ADRegClassID, 64, 1, true, false },
3270 { GR64_ArgRef, GR64_ArgRefBits, 1652, 2, sizeof(GR64_ArgRefBits), X86::GR64_ArgRefRegClassID, 64, 1, true, false },
3271 { GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, 1163, 2, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits), X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, 64, 1, true, false },
3272 { GR64_with_sub_32bit_in_GR32_ArgRef, GR64_with_sub_32bit_in_GR32_ArgRefBits, 1617, 2, sizeof(GR64_with_sub_32bit_in_GR32_ArgRefBits), X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClassID, 64, 1, true, false },
3273 { GR64_with_sub_32bit_in_GR32_BPSP, GR64_with_sub_32bit_in_GR32_BPSPBits, 1280, 2, sizeof(GR64_with_sub_32bit_in_GR32_BPSPBits), X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, 64, 1, true, false },
3274 { GR64_with_sub_32bit_in_GR32_BSI, GR64_with_sub_32bit_in_GR32_BSIBits, 968, 2, sizeof(GR64_with_sub_32bit_in_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, 64, 1, true, false },
3275 { GR64_with_sub_32bit_in_GR32_CB, GR64_with_sub_32bit_in_GR32_CBBits, 425, 2, sizeof(GR64_with_sub_32bit_in_GR32_CBBits), X86::GR64_with_sub_32bit_in_GR32_CBRegClassID, 64, 1, true, false },
3276 { GR64_with_sub_32bit_in_GR32_DIBP, GR64_with_sub_32bit_in_GR32_DIBPBits, 1130, 2, sizeof(GR64_with_sub_32bit_in_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, 64, 1, true, false },
3277 { GR64_with_sub_32bit_in_GR32_SIDI, GR64_with_sub_32bit_in_GR32_SIDIBits, 889, 2, sizeof(GR64_with_sub_32bit_in_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID, 64, 1, true, false },
3278 { GR64_ArgRef_and_GR64_TC, GR64_ArgRef_and_GR64_TCBits, 676, 1, sizeof(GR64_ArgRef_and_GR64_TCBits), X86::GR64_ArgRef_and_GR64_TCRegClassID, 64, 1, true, false },
3279 { GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, 1366, 1, sizeof(GR64_and_LOW32_ADDR_ACCESSBits), X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, 64, 1, true, false },
3280 { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits, 922, 1, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, 64, 1, true, false },
3281 { GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef, GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits, 1570, 1, sizeof(GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefBits), X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID, 64, 1, true, false },
3282 { GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB, GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits, 378, 1, sizeof(GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBBits), X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID, 64, 1, true, false },
3283 { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits, 1083, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, 64, 1, true, false },
3284 { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits, 509, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID, 64, 1, true, false },
3285 { GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits, 796, 1, sizeof(GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, 64, 1, true, false },
3286 { GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits, 842, 1, sizeof(GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 64, 1, true, false },
3287 { RST, RSTBits, 1393, 8, sizeof(RSTBits), X86::RSTRegClassID, 80, 1, false, false },
3288 { RFP80, RFP80Bits, 0, 7, sizeof(RFP80Bits), X86::RFP80RegClassID, 80, 1, true, false },
3289 { RFP80_7, RFP80_7Bits, 351, 1, sizeof(RFP80_7Bits), X86::RFP80_7RegClassID, 80, 1, false, false },
3290 { VR128X, VR128XBits, 1422, 32, sizeof(VR128XBits), X86::VR128XRegClassID, 128, 1, true, false },
3291 { VR128, VR128Bits, 359, 16, sizeof(VR128Bits), X86::VR128RegClassID, 128, 1, true, false },
3292 { VR256X, VR256XBits, 1415, 32, sizeof(VR256XBits), X86::VR256XRegClassID, 256, 1, true, false },
3293 { VR256, VR256Bits, 345, 16, sizeof(VR256Bits), X86::VR256RegClassID, 256, 1, true, false },
3294 { VR512, VR512Bits, 10, 32, sizeof(VR512Bits), X86::VR512RegClassID, 512, 1, true, false },
3295 { VR512_0_15, VR512_0_15Bits, 313, 16, sizeof(VR512_0_15Bits), X86::VR512_0_15RegClassID, 512, 1, true, false },
3296 { TILE, TILEBits, 746, 8, sizeof(TILEBits), X86::TILERegClassID, 8192, -1, true, false },
3297};
3298
3299// X86 Dwarf<->LLVM register mappings.
3300extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
3301 { 0U, X86::RAX },
3302 { 1U, X86::RDX },
3303 { 2U, X86::RCX },
3304 { 3U, X86::RBX },
3305 { 4U, X86::RSI },
3306 { 5U, X86::RDI },
3307 { 6U, X86::RBP },
3308 { 7U, X86::RSP },
3309 { 8U, X86::R8 },
3310 { 9U, X86::R9 },
3311 { 10U, X86::R10 },
3312 { 11U, X86::R11 },
3313 { 12U, X86::R12 },
3314 { 13U, X86::R13 },
3315 { 14U, X86::R14 },
3316 { 15U, X86::R15 },
3317 { 16U, X86::RIP },
3318 { 17U, X86::XMM0 },
3319 { 18U, X86::XMM1 },
3320 { 19U, X86::XMM2 },
3321 { 20U, X86::XMM3 },
3322 { 21U, X86::XMM4 },
3323 { 22U, X86::XMM5 },
3324 { 23U, X86::XMM6 },
3325 { 24U, X86::XMM7 },
3326 { 25U, X86::XMM8 },
3327 { 26U, X86::XMM9 },
3328 { 27U, X86::XMM10 },
3329 { 28U, X86::XMM11 },
3330 { 29U, X86::XMM12 },
3331 { 30U, X86::XMM13 },
3332 { 31U, X86::XMM14 },
3333 { 32U, X86::XMM15 },
3334 { 33U, X86::ST0 },
3335 { 34U, X86::ST1 },
3336 { 35U, X86::ST2 },
3337 { 36U, X86::ST3 },
3338 { 37U, X86::ST4 },
3339 { 38U, X86::ST5 },
3340 { 39U, X86::ST6 },
3341 { 40U, X86::ST7 },
3342 { 41U, X86::MM0 },
3343 { 42U, X86::MM1 },
3344 { 43U, X86::MM2 },
3345 { 44U, X86::MM3 },
3346 { 45U, X86::MM4 },
3347 { 46U, X86::MM5 },
3348 { 47U, X86::MM6 },
3349 { 48U, X86::MM7 },
3350 { 49U, X86::RFLAGS },
3351 { 50U, X86::ES },
3352 { 51U, X86::CS },
3353 { 52U, X86::SS },
3354 { 53U, X86::DS },
3355 { 54U, X86::FS },
3356 { 55U, X86::GS },
3357 { 58U, X86::FS_BASE },
3358 { 59U, X86::GS_BASE },
3359 { 67U, X86::XMM16 },
3360 { 68U, X86::XMM17 },
3361 { 69U, X86::XMM18 },
3362 { 70U, X86::XMM19 },
3363 { 71U, X86::XMM20 },
3364 { 72U, X86::XMM21 },
3365 { 73U, X86::XMM22 },
3366 { 74U, X86::XMM23 },
3367 { 75U, X86::XMM24 },
3368 { 76U, X86::XMM25 },
3369 { 77U, X86::XMM26 },
3370 { 78U, X86::XMM27 },
3371 { 79U, X86::XMM28 },
3372 { 80U, X86::XMM29 },
3373 { 81U, X86::XMM30 },
3374 { 82U, X86::XMM31 },
3375 { 118U, X86::K0 },
3376 { 119U, X86::K1 },
3377 { 120U, X86::K2 },
3378 { 121U, X86::K3 },
3379 { 122U, X86::K4 },
3380 { 123U, X86::K5 },
3381 { 124U, X86::K6 },
3382 { 125U, X86::K7 },
3383 { 130U, X86::R16 },
3384 { 131U, X86::R17 },
3385 { 132U, X86::R18 },
3386 { 133U, X86::R19 },
3387 { 134U, X86::R20 },
3388 { 135U, X86::R21 },
3389 { 136U, X86::R22 },
3390 { 137U, X86::R23 },
3391 { 138U, X86::R24 },
3392 { 139U, X86::R25 },
3393 { 140U, X86::R26 },
3394 { 141U, X86::R27 },
3395 { 142U, X86::R28 },
3396 { 143U, X86::R29 },
3397 { 144U, X86::R30 },
3398 { 145U, X86::R31 },
3399};
3400extern const unsigned X86DwarfFlavour0Dwarf2LSize = std::size(X86DwarfFlavour0Dwarf2L);
3401
3402extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
3403 { 0U, X86::EAX },
3404 { 1U, X86::ECX },
3405 { 2U, X86::EDX },
3406 { 3U, X86::EBX },
3407 { 4U, X86::EBP },
3408 { 5U, X86::ESP },
3409 { 6U, X86::ESI },
3410 { 7U, X86::EDI },
3411 { 8U, X86::EIP },
3412 { 9U, X86::EFLAGS },
3413 { 12U, X86::ST0 },
3414 { 13U, X86::ST1 },
3415 { 14U, X86::ST2 },
3416 { 15U, X86::ST3 },
3417 { 16U, X86::ST4 },
3418 { 17U, X86::ST5 },
3419 { 18U, X86::ST6 },
3420 { 19U, X86::ST7 },
3421 { 21U, X86::XMM0 },
3422 { 22U, X86::XMM1 },
3423 { 23U, X86::XMM2 },
3424 { 24U, X86::XMM3 },
3425 { 25U, X86::XMM4 },
3426 { 26U, X86::XMM5 },
3427 { 27U, X86::XMM6 },
3428 { 28U, X86::XMM7 },
3429 { 29U, X86::MM0 },
3430 { 30U, X86::MM1 },
3431 { 31U, X86::MM2 },
3432 { 32U, X86::MM3 },
3433 { 33U, X86::MM4 },
3434 { 34U, X86::MM5 },
3435 { 35U, X86::MM6 },
3436 { 36U, X86::MM7 },
3437 { 93U, X86::K0 },
3438 { 94U, X86::K1 },
3439 { 95U, X86::K2 },
3440 { 96U, X86::K3 },
3441 { 97U, X86::K4 },
3442 { 98U, X86::K5 },
3443 { 99U, X86::K6 },
3444 { 100U, X86::K7 },
3445};
3446extern const unsigned X86DwarfFlavour1Dwarf2LSize = std::size(X86DwarfFlavour1Dwarf2L);
3447
3448extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
3449 { 0U, X86::EAX },
3450 { 1U, X86::ECX },
3451 { 2U, X86::EDX },
3452 { 3U, X86::EBX },
3453 { 4U, X86::ESP },
3454 { 5U, X86::EBP },
3455 { 6U, X86::ESI },
3456 { 7U, X86::EDI },
3457 { 8U, X86::EIP },
3458 { 9U, X86::EFLAGS },
3459 { 11U, X86::ST0 },
3460 { 12U, X86::ST1 },
3461 { 13U, X86::ST2 },
3462 { 14U, X86::ST3 },
3463 { 15U, X86::ST4 },
3464 { 16U, X86::ST5 },
3465 { 17U, X86::ST6 },
3466 { 18U, X86::ST7 },
3467 { 21U, X86::XMM0 },
3468 { 22U, X86::XMM1 },
3469 { 23U, X86::XMM2 },
3470 { 24U, X86::XMM3 },
3471 { 25U, X86::XMM4 },
3472 { 26U, X86::XMM5 },
3473 { 27U, X86::XMM6 },
3474 { 28U, X86::XMM7 },
3475 { 29U, X86::MM0 },
3476 { 30U, X86::MM1 },
3477 { 31U, X86::MM2 },
3478 { 32U, X86::MM3 },
3479 { 33U, X86::MM4 },
3480 { 34U, X86::MM5 },
3481 { 35U, X86::MM6 },
3482 { 36U, X86::MM7 },
3483 { 40U, X86::ES },
3484 { 41U, X86::CS },
3485 { 42U, X86::SS },
3486 { 43U, X86::DS },
3487 { 44U, X86::FS },
3488 { 45U, X86::GS },
3489 { 93U, X86::K0 },
3490 { 94U, X86::K1 },
3491 { 95U, X86::K2 },
3492 { 96U, X86::K3 },
3493 { 97U, X86::K4 },
3494 { 98U, X86::K5 },
3495 { 99U, X86::K6 },
3496 { 100U, X86::K7 },
3497};
3498extern const unsigned X86DwarfFlavour2Dwarf2LSize = std::size(X86DwarfFlavour2Dwarf2L);
3499
3500extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
3501 { 0U, X86::RAX },
3502 { 1U, X86::RDX },
3503 { 2U, X86::RCX },
3504 { 3U, X86::RBX },
3505 { 4U, X86::RSI },
3506 { 5U, X86::RDI },
3507 { 6U, X86::RBP },
3508 { 7U, X86::RSP },
3509 { 8U, X86::R8 },
3510 { 9U, X86::R9 },
3511 { 10U, X86::R10 },
3512 { 11U, X86::R11 },
3513 { 12U, X86::R12 },
3514 { 13U, X86::R13 },
3515 { 14U, X86::R14 },
3516 { 15U, X86::R15 },
3517 { 16U, X86::RIP },
3518 { 17U, X86::XMM0 },
3519 { 18U, X86::XMM1 },
3520 { 19U, X86::XMM2 },
3521 { 20U, X86::XMM3 },
3522 { 21U, X86::XMM4 },
3523 { 22U, X86::XMM5 },
3524 { 23U, X86::XMM6 },
3525 { 24U, X86::XMM7 },
3526 { 25U, X86::XMM8 },
3527 { 26U, X86::XMM9 },
3528 { 27U, X86::XMM10 },
3529 { 28U, X86::XMM11 },
3530 { 29U, X86::XMM12 },
3531 { 30U, X86::XMM13 },
3532 { 31U, X86::XMM14 },
3533 { 32U, X86::XMM15 },
3534 { 33U, X86::ST0 },
3535 { 34U, X86::ST1 },
3536 { 35U, X86::ST2 },
3537 { 36U, X86::ST3 },
3538 { 37U, X86::ST4 },
3539 { 38U, X86::ST5 },
3540 { 39U, X86::ST6 },
3541 { 40U, X86::ST7 },
3542 { 41U, X86::MM0 },
3543 { 42U, X86::MM1 },
3544 { 43U, X86::MM2 },
3545 { 44U, X86::MM3 },
3546 { 45U, X86::MM4 },
3547 { 46U, X86::MM5 },
3548 { 47U, X86::MM6 },
3549 { 48U, X86::MM7 },
3550 { 49U, X86::RFLAGS },
3551 { 50U, X86::ES },
3552 { 51U, X86::CS },
3553 { 52U, X86::SS },
3554 { 53U, X86::DS },
3555 { 54U, X86::FS },
3556 { 55U, X86::GS },
3557 { 58U, X86::FS_BASE },
3558 { 59U, X86::GS_BASE },
3559 { 67U, X86::XMM16 },
3560 { 68U, X86::XMM17 },
3561 { 69U, X86::XMM18 },
3562 { 70U, X86::XMM19 },
3563 { 71U, X86::XMM20 },
3564 { 72U, X86::XMM21 },
3565 { 73U, X86::XMM22 },
3566 { 74U, X86::XMM23 },
3567 { 75U, X86::XMM24 },
3568 { 76U, X86::XMM25 },
3569 { 77U, X86::XMM26 },
3570 { 78U, X86::XMM27 },
3571 { 79U, X86::XMM28 },
3572 { 80U, X86::XMM29 },
3573 { 81U, X86::XMM30 },
3574 { 82U, X86::XMM31 },
3575 { 118U, X86::K0 },
3576 { 119U, X86::K1 },
3577 { 120U, X86::K2 },
3578 { 121U, X86::K3 },
3579 { 122U, X86::K4 },
3580 { 123U, X86::K5 },
3581 { 124U, X86::K6 },
3582 { 125U, X86::K7 },
3583 { 130U, X86::R16 },
3584 { 131U, X86::R17 },
3585 { 132U, X86::R18 },
3586 { 133U, X86::R19 },
3587 { 134U, X86::R20 },
3588 { 135U, X86::R21 },
3589 { 136U, X86::R22 },
3590 { 137U, X86::R23 },
3591 { 138U, X86::R24 },
3592 { 139U, X86::R25 },
3593 { 140U, X86::R26 },
3594 { 141U, X86::R27 },
3595 { 142U, X86::R28 },
3596 { 143U, X86::R29 },
3597 { 144U, X86::R30 },
3598 { 145U, X86::R31 },
3599};
3600extern const unsigned X86EHFlavour0Dwarf2LSize = std::size(X86EHFlavour0Dwarf2L);
3601
3602extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
3603 { 0U, X86::EAX },
3604 { 1U, X86::ECX },
3605 { 2U, X86::EDX },
3606 { 3U, X86::EBX },
3607 { 4U, X86::EBP },
3608 { 5U, X86::ESP },
3609 { 6U, X86::ESI },
3610 { 7U, X86::EDI },
3611 { 8U, X86::EIP },
3612 { 9U, X86::EFLAGS },
3613 { 12U, X86::ST0 },
3614 { 13U, X86::ST1 },
3615 { 14U, X86::ST2 },
3616 { 15U, X86::ST3 },
3617 { 16U, X86::ST4 },
3618 { 17U, X86::ST5 },
3619 { 18U, X86::ST6 },
3620 { 19U, X86::ST7 },
3621 { 21U, X86::XMM0 },
3622 { 22U, X86::XMM1 },
3623 { 23U, X86::XMM2 },
3624 { 24U, X86::XMM3 },
3625 { 25U, X86::XMM4 },
3626 { 26U, X86::XMM5 },
3627 { 27U, X86::XMM6 },
3628 { 28U, X86::XMM7 },
3629 { 29U, X86::MM0 },
3630 { 30U, X86::MM1 },
3631 { 31U, X86::MM2 },
3632 { 32U, X86::MM3 },
3633 { 33U, X86::MM4 },
3634 { 34U, X86::MM5 },
3635 { 35U, X86::MM6 },
3636 { 36U, X86::MM7 },
3637 { 93U, X86::K0 },
3638 { 94U, X86::K1 },
3639 { 95U, X86::K2 },
3640 { 96U, X86::K3 },
3641 { 97U, X86::K4 },
3642 { 98U, X86::K5 },
3643 { 99U, X86::K6 },
3644 { 100U, X86::K7 },
3645};
3646extern const unsigned X86EHFlavour1Dwarf2LSize = std::size(X86EHFlavour1Dwarf2L);
3647
3648extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
3649 { 0U, X86::EAX },
3650 { 1U, X86::ECX },
3651 { 2U, X86::EDX },
3652 { 3U, X86::EBX },
3653 { 4U, X86::ESP },
3654 { 5U, X86::EBP },
3655 { 6U, X86::ESI },
3656 { 7U, X86::EDI },
3657 { 8U, X86::EIP },
3658 { 9U, X86::EFLAGS },
3659 { 11U, X86::ST0 },
3660 { 12U, X86::ST1 },
3661 { 13U, X86::ST2 },
3662 { 14U, X86::ST3 },
3663 { 15U, X86::ST4 },
3664 { 16U, X86::ST5 },
3665 { 17U, X86::ST6 },
3666 { 18U, X86::ST7 },
3667 { 21U, X86::XMM0 },
3668 { 22U, X86::XMM1 },
3669 { 23U, X86::XMM2 },
3670 { 24U, X86::XMM3 },
3671 { 25U, X86::XMM4 },
3672 { 26U, X86::XMM5 },
3673 { 27U, X86::XMM6 },
3674 { 28U, X86::XMM7 },
3675 { 29U, X86::MM0 },
3676 { 30U, X86::MM1 },
3677 { 31U, X86::MM2 },
3678 { 32U, X86::MM3 },
3679 { 33U, X86::MM4 },
3680 { 34U, X86::MM5 },
3681 { 35U, X86::MM6 },
3682 { 36U, X86::MM7 },
3683 { 40U, X86::ES },
3684 { 41U, X86::CS },
3685 { 42U, X86::SS },
3686 { 43U, X86::DS },
3687 { 44U, X86::FS },
3688 { 45U, X86::GS },
3689 { 93U, X86::K0 },
3690 { 94U, X86::K1 },
3691 { 95U, X86::K2 },
3692 { 96U, X86::K3 },
3693 { 97U, X86::K4 },
3694 { 98U, X86::K5 },
3695 { 99U, X86::K6 },
3696 { 100U, X86::K7 },
3697};
3698extern const unsigned X86EHFlavour2Dwarf2LSize = std::size(X86EHFlavour2Dwarf2L);
3699
3700extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
3701 { X86::CS, 51U },
3702 { X86::DS, 53U },
3703 { X86::EAX, -2U },
3704 { X86::EBP, -2U },
3705 { X86::EBX, -2U },
3706 { X86::ECX, -2U },
3707 { X86::EDI, -2U },
3708 { X86::EDX, -2U },
3709 { X86::EFLAGS, 49U },
3710 { X86::EIP, -2U },
3711 { X86::ES, 50U },
3712 { X86::ESI, -2U },
3713 { X86::ESP, -2U },
3714 { X86::FS, 54U },
3715 { X86::FS_BASE, 58U },
3716 { X86::GS, 55U },
3717 { X86::GS_BASE, 59U },
3718 { X86::RAX, 0U },
3719 { X86::RBP, 6U },
3720 { X86::RBX, 3U },
3721 { X86::RCX, 2U },
3722 { X86::RDI, 5U },
3723 { X86::RDX, 1U },
3724 { X86::RFLAGS, 49U },
3725 { X86::RIP, 16U },
3726 { X86::RSI, 4U },
3727 { X86::RSP, 7U },
3728 { X86::SS, 52U },
3729 { X86::_EFLAGS, 49U },
3730 { X86::MM0, 41U },
3731 { X86::MM1, 42U },
3732 { X86::MM2, 43U },
3733 { X86::MM3, 44U },
3734 { X86::MM4, 45U },
3735 { X86::MM5, 46U },
3736 { X86::MM6, 47U },
3737 { X86::MM7, 48U },
3738 { X86::R8, 8U },
3739 { X86::R9, 9U },
3740 { X86::R10, 10U },
3741 { X86::R11, 11U },
3742 { X86::R12, 12U },
3743 { X86::R13, 13U },
3744 { X86::R14, 14U },
3745 { X86::R15, 15U },
3746 { X86::ST0, 33U },
3747 { X86::ST1, 34U },
3748 { X86::ST2, 35U },
3749 { X86::ST3, 36U },
3750 { X86::ST4, 37U },
3751 { X86::ST5, 38U },
3752 { X86::ST6, 39U },
3753 { X86::ST7, 40U },
3754 { X86::XMM0, 17U },
3755 { X86::XMM1, 18U },
3756 { X86::XMM2, 19U },
3757 { X86::XMM3, 20U },
3758 { X86::XMM4, 21U },
3759 { X86::XMM5, 22U },
3760 { X86::XMM6, 23U },
3761 { X86::XMM7, 24U },
3762 { X86::XMM8, 25U },
3763 { X86::XMM9, 26U },
3764 { X86::XMM10, 27U },
3765 { X86::XMM11, 28U },
3766 { X86::XMM12, 29U },
3767 { X86::XMM13, 30U },
3768 { X86::XMM14, 31U },
3769 { X86::XMM15, 32U },
3770 { X86::YMM0, 17U },
3771 { X86::YMM1, 18U },
3772 { X86::YMM2, 19U },
3773 { X86::YMM3, 20U },
3774 { X86::YMM4, 21U },
3775 { X86::YMM5, 22U },
3776 { X86::YMM6, 23U },
3777 { X86::YMM7, 24U },
3778 { X86::YMM8, 25U },
3779 { X86::YMM9, 26U },
3780 { X86::YMM10, 27U },
3781 { X86::YMM11, 28U },
3782 { X86::YMM12, 29U },
3783 { X86::YMM13, 30U },
3784 { X86::YMM14, 31U },
3785 { X86::YMM15, 32U },
3786 { X86::K0, 118U },
3787 { X86::K1, 119U },
3788 { X86::K2, 120U },
3789 { X86::K3, 121U },
3790 { X86::K4, 122U },
3791 { X86::K5, 123U },
3792 { X86::K6, 124U },
3793 { X86::K7, 125U },
3794 { X86::XMM16, 67U },
3795 { X86::XMM17, 68U },
3796 { X86::XMM18, 69U },
3797 { X86::XMM19, 70U },
3798 { X86::XMM20, 71U },
3799 { X86::XMM21, 72U },
3800 { X86::XMM22, 73U },
3801 { X86::XMM23, 74U },
3802 { X86::XMM24, 75U },
3803 { X86::XMM25, 76U },
3804 { X86::XMM26, 77U },
3805 { X86::XMM27, 78U },
3806 { X86::XMM28, 79U },
3807 { X86::XMM29, 80U },
3808 { X86::XMM30, 81U },
3809 { X86::XMM31, 82U },
3810 { X86::YMM16, 67U },
3811 { X86::YMM17, 68U },
3812 { X86::YMM18, 69U },
3813 { X86::YMM19, 70U },
3814 { X86::YMM20, 71U },
3815 { X86::YMM21, 72U },
3816 { X86::YMM22, 73U },
3817 { X86::YMM23, 74U },
3818 { X86::YMM24, 75U },
3819 { X86::YMM25, 76U },
3820 { X86::YMM26, 77U },
3821 { X86::YMM27, 78U },
3822 { X86::YMM28, 79U },
3823 { X86::YMM29, 80U },
3824 { X86::YMM30, 81U },
3825 { X86::YMM31, 82U },
3826 { X86::ZMM0, 17U },
3827 { X86::ZMM1, 18U },
3828 { X86::ZMM2, 19U },
3829 { X86::ZMM3, 20U },
3830 { X86::ZMM4, 21U },
3831 { X86::ZMM5, 22U },
3832 { X86::ZMM6, 23U },
3833 { X86::ZMM7, 24U },
3834 { X86::ZMM8, 25U },
3835 { X86::ZMM9, 26U },
3836 { X86::ZMM10, 27U },
3837 { X86::ZMM11, 28U },
3838 { X86::ZMM12, 29U },
3839 { X86::ZMM13, 30U },
3840 { X86::ZMM14, 31U },
3841 { X86::ZMM15, 32U },
3842 { X86::ZMM16, 67U },
3843 { X86::ZMM17, 68U },
3844 { X86::ZMM18, 69U },
3845 { X86::ZMM19, 70U },
3846 { X86::ZMM20, 71U },
3847 { X86::ZMM21, 72U },
3848 { X86::ZMM22, 73U },
3849 { X86::ZMM23, 74U },
3850 { X86::ZMM24, 75U },
3851 { X86::ZMM25, 76U },
3852 { X86::ZMM26, 77U },
3853 { X86::ZMM27, 78U },
3854 { X86::ZMM28, 79U },
3855 { X86::ZMM29, 80U },
3856 { X86::ZMM30, 81U },
3857 { X86::ZMM31, 82U },
3858 { X86::R16, 130U },
3859 { X86::R17, 131U },
3860 { X86::R18, 132U },
3861 { X86::R19, 133U },
3862 { X86::R20, 134U },
3863 { X86::R21, 135U },
3864 { X86::R22, 136U },
3865 { X86::R23, 137U },
3866 { X86::R24, 138U },
3867 { X86::R25, 139U },
3868 { X86::R26, 140U },
3869 { X86::R27, 141U },
3870 { X86::R28, 142U },
3871 { X86::R29, 143U },
3872 { X86::R30, 144U },
3873 { X86::R31, 145U },
3874};
3875extern const unsigned X86DwarfFlavour0L2DwarfSize = std::size(X86DwarfFlavour0L2Dwarf);
3876
3877extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
3878 { X86::CS, -2U },
3879 { X86::DS, -2U },
3880 { X86::EAX, 0U },
3881 { X86::EBP, 4U },
3882 { X86::EBX, 3U },
3883 { X86::ECX, 1U },
3884 { X86::EDI, 7U },
3885 { X86::EDX, 2U },
3886 { X86::EFLAGS, 9U },
3887 { X86::EIP, 8U },
3888 { X86::ES, -2U },
3889 { X86::ESI, 6U },
3890 { X86::ESP, 5U },
3891 { X86::FS, -2U },
3892 { X86::FS_BASE, -2U },
3893 { X86::GS, -2U },
3894 { X86::GS_BASE, -2U },
3895 { X86::RAX, -2U },
3896 { X86::RBP, -2U },
3897 { X86::RBX, -2U },
3898 { X86::RCX, -2U },
3899 { X86::RDI, -2U },
3900 { X86::RDX, -2U },
3901 { X86::RFLAGS, -2U },
3902 { X86::RIP, -2U },
3903 { X86::RSI, -2U },
3904 { X86::RSP, -2U },
3905 { X86::SS, -2U },
3906 { X86::_EFLAGS, 9U },
3907 { X86::MM0, 29U },
3908 { X86::MM1, 30U },
3909 { X86::MM2, 31U },
3910 { X86::MM3, 32U },
3911 { X86::MM4, 33U },
3912 { X86::MM5, 34U },
3913 { X86::MM6, 35U },
3914 { X86::MM7, 36U },
3915 { X86::R8, -2U },
3916 { X86::R9, -2U },
3917 { X86::R10, -2U },
3918 { X86::R11, -2U },
3919 { X86::R12, -2U },
3920 { X86::R13, -2U },
3921 { X86::R14, -2U },
3922 { X86::R15, -2U },
3923 { X86::ST0, 12U },
3924 { X86::ST1, 13U },
3925 { X86::ST2, 14U },
3926 { X86::ST3, 15U },
3927 { X86::ST4, 16U },
3928 { X86::ST5, 17U },
3929 { X86::ST6, 18U },
3930 { X86::ST7, 19U },
3931 { X86::XMM0, 21U },
3932 { X86::XMM1, 22U },
3933 { X86::XMM2, 23U },
3934 { X86::XMM3, 24U },
3935 { X86::XMM4, 25U },
3936 { X86::XMM5, 26U },
3937 { X86::XMM6, 27U },
3938 { X86::XMM7, 28U },
3939 { X86::XMM8, -2U },
3940 { X86::XMM9, -2U },
3941 { X86::XMM10, -2U },
3942 { X86::XMM11, -2U },
3943 { X86::XMM12, -2U },
3944 { X86::XMM13, -2U },
3945 { X86::XMM14, -2U },
3946 { X86::XMM15, -2U },
3947 { X86::YMM0, 21U },
3948 { X86::YMM1, 22U },
3949 { X86::YMM2, 23U },
3950 { X86::YMM3, 24U },
3951 { X86::YMM4, 25U },
3952 { X86::YMM5, 26U },
3953 { X86::YMM6, 27U },
3954 { X86::YMM7, 28U },
3955 { X86::YMM8, -2U },
3956 { X86::YMM9, -2U },
3957 { X86::YMM10, -2U },
3958 { X86::YMM11, -2U },
3959 { X86::YMM12, -2U },
3960 { X86::YMM13, -2U },
3961 { X86::YMM14, -2U },
3962 { X86::YMM15, -2U },
3963 { X86::K0, 93U },
3964 { X86::K1, 94U },
3965 { X86::K2, 95U },
3966 { X86::K3, 96U },
3967 { X86::K4, 97U },
3968 { X86::K5, 98U },
3969 { X86::K6, 99U },
3970 { X86::K7, 100U },
3971 { X86::XMM16, -2U },
3972 { X86::XMM17, -2U },
3973 { X86::XMM18, -2U },
3974 { X86::XMM19, -2U },
3975 { X86::XMM20, -2U },
3976 { X86::XMM21, -2U },
3977 { X86::XMM22, -2U },
3978 { X86::XMM23, -2U },
3979 { X86::XMM24, -2U },
3980 { X86::XMM25, -2U },
3981 { X86::XMM26, -2U },
3982 { X86::XMM27, -2U },
3983 { X86::XMM28, -2U },
3984 { X86::XMM29, -2U },
3985 { X86::XMM30, -2U },
3986 { X86::XMM31, -2U },
3987 { X86::YMM16, -2U },
3988 { X86::YMM17, -2U },
3989 { X86::YMM18, -2U },
3990 { X86::YMM19, -2U },
3991 { X86::YMM20, -2U },
3992 { X86::YMM21, -2U },
3993 { X86::YMM22, -2U },
3994 { X86::YMM23, -2U },
3995 { X86::YMM24, -2U },
3996 { X86::YMM25, -2U },
3997 { X86::YMM26, -2U },
3998 { X86::YMM27, -2U },
3999 { X86::YMM28, -2U },
4000 { X86::YMM29, -2U },
4001 { X86::YMM30, -2U },
4002 { X86::YMM31, -2U },
4003 { X86::ZMM0, 21U },
4004 { X86::ZMM1, 22U },
4005 { X86::ZMM2, 23U },
4006 { X86::ZMM3, 24U },
4007 { X86::ZMM4, 25U },
4008 { X86::ZMM5, 26U },
4009 { X86::ZMM6, 27U },
4010 { X86::ZMM7, 28U },
4011 { X86::ZMM8, -2U },
4012 { X86::ZMM9, -2U },
4013 { X86::ZMM10, -2U },
4014 { X86::ZMM11, -2U },
4015 { X86::ZMM12, -2U },
4016 { X86::ZMM13, -2U },
4017 { X86::ZMM14, -2U },
4018 { X86::ZMM15, -2U },
4019 { X86::ZMM16, -2U },
4020 { X86::ZMM17, -2U },
4021 { X86::ZMM18, -2U },
4022 { X86::ZMM19, -2U },
4023 { X86::ZMM20, -2U },
4024 { X86::ZMM21, -2U },
4025 { X86::ZMM22, -2U },
4026 { X86::ZMM23, -2U },
4027 { X86::ZMM24, -2U },
4028 { X86::ZMM25, -2U },
4029 { X86::ZMM26, -2U },
4030 { X86::ZMM27, -2U },
4031 { X86::ZMM28, -2U },
4032 { X86::ZMM29, -2U },
4033 { X86::ZMM30, -2U },
4034 { X86::ZMM31, -2U },
4035 { X86::R16, -2U },
4036 { X86::R17, -2U },
4037 { X86::R18, -2U },
4038 { X86::R19, -2U },
4039 { X86::R20, -2U },
4040 { X86::R21, -2U },
4041 { X86::R22, -2U },
4042 { X86::R23, -2U },
4043 { X86::R24, -2U },
4044 { X86::R25, -2U },
4045 { X86::R26, -2U },
4046 { X86::R27, -2U },
4047 { X86::R28, -2U },
4048 { X86::R29, -2U },
4049 { X86::R30, -2U },
4050 { X86::R31, -2U },
4051};
4052extern const unsigned X86DwarfFlavour1L2DwarfSize = std::size(X86DwarfFlavour1L2Dwarf);
4053
4054extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
4055 { X86::CS, 41U },
4056 { X86::DS, 43U },
4057 { X86::EAX, 0U },
4058 { X86::EBP, 5U },
4059 { X86::EBX, 3U },
4060 { X86::ECX, 1U },
4061 { X86::EDI, 7U },
4062 { X86::EDX, 2U },
4063 { X86::EFLAGS, 9U },
4064 { X86::EIP, 8U },
4065 { X86::ES, 40U },
4066 { X86::ESI, 6U },
4067 { X86::ESP, 4U },
4068 { X86::FS, 44U },
4069 { X86::FS_BASE, -2U },
4070 { X86::GS, 45U },
4071 { X86::GS_BASE, -2U },
4072 { X86::RAX, -2U },
4073 { X86::RBP, -2U },
4074 { X86::RBX, -2U },
4075 { X86::RCX, -2U },
4076 { X86::RDI, -2U },
4077 { X86::RDX, -2U },
4078 { X86::RFLAGS, -2U },
4079 { X86::RIP, -2U },
4080 { X86::RSI, -2U },
4081 { X86::RSP, -2U },
4082 { X86::SS, 42U },
4083 { X86::_EFLAGS, 9U },
4084 { X86::MM0, 29U },
4085 { X86::MM1, 30U },
4086 { X86::MM2, 31U },
4087 { X86::MM3, 32U },
4088 { X86::MM4, 33U },
4089 { X86::MM5, 34U },
4090 { X86::MM6, 35U },
4091 { X86::MM7, 36U },
4092 { X86::R8, -2U },
4093 { X86::R9, -2U },
4094 { X86::R10, -2U },
4095 { X86::R11, -2U },
4096 { X86::R12, -2U },
4097 { X86::R13, -2U },
4098 { X86::R14, -2U },
4099 { X86::R15, -2U },
4100 { X86::ST0, 11U },
4101 { X86::ST1, 12U },
4102 { X86::ST2, 13U },
4103 { X86::ST3, 14U },
4104 { X86::ST4, 15U },
4105 { X86::ST5, 16U },
4106 { X86::ST6, 17U },
4107 { X86::ST7, 18U },
4108 { X86::XMM0, 21U },
4109 { X86::XMM1, 22U },
4110 { X86::XMM2, 23U },
4111 { X86::XMM3, 24U },
4112 { X86::XMM4, 25U },
4113 { X86::XMM5, 26U },
4114 { X86::XMM6, 27U },
4115 { X86::XMM7, 28U },
4116 { X86::XMM8, -2U },
4117 { X86::XMM9, -2U },
4118 { X86::XMM10, -2U },
4119 { X86::XMM11, -2U },
4120 { X86::XMM12, -2U },
4121 { X86::XMM13, -2U },
4122 { X86::XMM14, -2U },
4123 { X86::XMM15, -2U },
4124 { X86::YMM0, 21U },
4125 { X86::YMM1, 22U },
4126 { X86::YMM2, 23U },
4127 { X86::YMM3, 24U },
4128 { X86::YMM4, 25U },
4129 { X86::YMM5, 26U },
4130 { X86::YMM6, 27U },
4131 { X86::YMM7, 28U },
4132 { X86::YMM8, -2U },
4133 { X86::YMM9, -2U },
4134 { X86::YMM10, -2U },
4135 { X86::YMM11, -2U },
4136 { X86::YMM12, -2U },
4137 { X86::YMM13, -2U },
4138 { X86::YMM14, -2U },
4139 { X86::YMM15, -2U },
4140 { X86::K0, 93U },
4141 { X86::K1, 94U },
4142 { X86::K2, 95U },
4143 { X86::K3, 96U },
4144 { X86::K4, 97U },
4145 { X86::K5, 98U },
4146 { X86::K6, 99U },
4147 { X86::K7, 100U },
4148 { X86::XMM16, -2U },
4149 { X86::XMM17, -2U },
4150 { X86::XMM18, -2U },
4151 { X86::XMM19, -2U },
4152 { X86::XMM20, -2U },
4153 { X86::XMM21, -2U },
4154 { X86::XMM22, -2U },
4155 { X86::XMM23, -2U },
4156 { X86::XMM24, -2U },
4157 { X86::XMM25, -2U },
4158 { X86::XMM26, -2U },
4159 { X86::XMM27, -2U },
4160 { X86::XMM28, -2U },
4161 { X86::XMM29, -2U },
4162 { X86::XMM30, -2U },
4163 { X86::XMM31, -2U },
4164 { X86::YMM16, -2U },
4165 { X86::YMM17, -2U },
4166 { X86::YMM18, -2U },
4167 { X86::YMM19, -2U },
4168 { X86::YMM20, -2U },
4169 { X86::YMM21, -2U },
4170 { X86::YMM22, -2U },
4171 { X86::YMM23, -2U },
4172 { X86::YMM24, -2U },
4173 { X86::YMM25, -2U },
4174 { X86::YMM26, -2U },
4175 { X86::YMM27, -2U },
4176 { X86::YMM28, -2U },
4177 { X86::YMM29, -2U },
4178 { X86::YMM30, -2U },
4179 { X86::YMM31, -2U },
4180 { X86::ZMM0, 21U },
4181 { X86::ZMM1, 22U },
4182 { X86::ZMM2, 23U },
4183 { X86::ZMM3, 24U },
4184 { X86::ZMM4, 25U },
4185 { X86::ZMM5, 26U },
4186 { X86::ZMM6, 27U },
4187 { X86::ZMM7, 28U },
4188 { X86::ZMM8, -2U },
4189 { X86::ZMM9, -2U },
4190 { X86::ZMM10, -2U },
4191 { X86::ZMM11, -2U },
4192 { X86::ZMM12, -2U },
4193 { X86::ZMM13, -2U },
4194 { X86::ZMM14, -2U },
4195 { X86::ZMM15, -2U },
4196 { X86::ZMM16, -2U },
4197 { X86::ZMM17, -2U },
4198 { X86::ZMM18, -2U },
4199 { X86::ZMM19, -2U },
4200 { X86::ZMM20, -2U },
4201 { X86::ZMM21, -2U },
4202 { X86::ZMM22, -2U },
4203 { X86::ZMM23, -2U },
4204 { X86::ZMM24, -2U },
4205 { X86::ZMM25, -2U },
4206 { X86::ZMM26, -2U },
4207 { X86::ZMM27, -2U },
4208 { X86::ZMM28, -2U },
4209 { X86::ZMM29, -2U },
4210 { X86::ZMM30, -2U },
4211 { X86::ZMM31, -2U },
4212 { X86::R16, -2U },
4213 { X86::R17, -2U },
4214 { X86::R18, -2U },
4215 { X86::R19, -2U },
4216 { X86::R20, -2U },
4217 { X86::R21, -2U },
4218 { X86::R22, -2U },
4219 { X86::R23, -2U },
4220 { X86::R24, -2U },
4221 { X86::R25, -2U },
4222 { X86::R26, -2U },
4223 { X86::R27, -2U },
4224 { X86::R28, -2U },
4225 { X86::R29, -2U },
4226 { X86::R30, -2U },
4227 { X86::R31, -2U },
4228};
4229extern const unsigned X86DwarfFlavour2L2DwarfSize = std::size(X86DwarfFlavour2L2Dwarf);
4230
4231extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
4232 { X86::CS, 51U },
4233 { X86::DS, 53U },
4234 { X86::EAX, -2U },
4235 { X86::EBP, -2U },
4236 { X86::EBX, -2U },
4237 { X86::ECX, -2U },
4238 { X86::EDI, -2U },
4239 { X86::EDX, -2U },
4240 { X86::EFLAGS, 49U },
4241 { X86::EIP, -2U },
4242 { X86::ES, 50U },
4243 { X86::ESI, -2U },
4244 { X86::ESP, -2U },
4245 { X86::FS, 54U },
4246 { X86::FS_BASE, 58U },
4247 { X86::GS, 55U },
4248 { X86::GS_BASE, 59U },
4249 { X86::RAX, 0U },
4250 { X86::RBP, 6U },
4251 { X86::RBX, 3U },
4252 { X86::RCX, 2U },
4253 { X86::RDI, 5U },
4254 { X86::RDX, 1U },
4255 { X86::RFLAGS, 49U },
4256 { X86::RIP, 16U },
4257 { X86::RSI, 4U },
4258 { X86::RSP, 7U },
4259 { X86::SS, 52U },
4260 { X86::_EFLAGS, 49U },
4261 { X86::MM0, 41U },
4262 { X86::MM1, 42U },
4263 { X86::MM2, 43U },
4264 { X86::MM3, 44U },
4265 { X86::MM4, 45U },
4266 { X86::MM5, 46U },
4267 { X86::MM6, 47U },
4268 { X86::MM7, 48U },
4269 { X86::R8, 8U },
4270 { X86::R9, 9U },
4271 { X86::R10, 10U },
4272 { X86::R11, 11U },
4273 { X86::R12, 12U },
4274 { X86::R13, 13U },
4275 { X86::R14, 14U },
4276 { X86::R15, 15U },
4277 { X86::ST0, 33U },
4278 { X86::ST1, 34U },
4279 { X86::ST2, 35U },
4280 { X86::ST3, 36U },
4281 { X86::ST4, 37U },
4282 { X86::ST5, 38U },
4283 { X86::ST6, 39U },
4284 { X86::ST7, 40U },
4285 { X86::XMM0, 17U },
4286 { X86::XMM1, 18U },
4287 { X86::XMM2, 19U },
4288 { X86::XMM3, 20U },
4289 { X86::XMM4, 21U },
4290 { X86::XMM5, 22U },
4291 { X86::XMM6, 23U },
4292 { X86::XMM7, 24U },
4293 { X86::XMM8, 25U },
4294 { X86::XMM9, 26U },
4295 { X86::XMM10, 27U },
4296 { X86::XMM11, 28U },
4297 { X86::XMM12, 29U },
4298 { X86::XMM13, 30U },
4299 { X86::XMM14, 31U },
4300 { X86::XMM15, 32U },
4301 { X86::YMM0, 17U },
4302 { X86::YMM1, 18U },
4303 { X86::YMM2, 19U },
4304 { X86::YMM3, 20U },
4305 { X86::YMM4, 21U },
4306 { X86::YMM5, 22U },
4307 { X86::YMM6, 23U },
4308 { X86::YMM7, 24U },
4309 { X86::YMM8, 25U },
4310 { X86::YMM9, 26U },
4311 { X86::YMM10, 27U },
4312 { X86::YMM11, 28U },
4313 { X86::YMM12, 29U },
4314 { X86::YMM13, 30U },
4315 { X86::YMM14, 31U },
4316 { X86::YMM15, 32U },
4317 { X86::K0, 118U },
4318 { X86::K1, 119U },
4319 { X86::K2, 120U },
4320 { X86::K3, 121U },
4321 { X86::K4, 122U },
4322 { X86::K5, 123U },
4323 { X86::K6, 124U },
4324 { X86::K7, 125U },
4325 { X86::XMM16, 67U },
4326 { X86::XMM17, 68U },
4327 { X86::XMM18, 69U },
4328 { X86::XMM19, 70U },
4329 { X86::XMM20, 71U },
4330 { X86::XMM21, 72U },
4331 { X86::XMM22, 73U },
4332 { X86::XMM23, 74U },
4333 { X86::XMM24, 75U },
4334 { X86::XMM25, 76U },
4335 { X86::XMM26, 77U },
4336 { X86::XMM27, 78U },
4337 { X86::XMM28, 79U },
4338 { X86::XMM29, 80U },
4339 { X86::XMM30, 81U },
4340 { X86::XMM31, 82U },
4341 { X86::YMM16, 67U },
4342 { X86::YMM17, 68U },
4343 { X86::YMM18, 69U },
4344 { X86::YMM19, 70U },
4345 { X86::YMM20, 71U },
4346 { X86::YMM21, 72U },
4347 { X86::YMM22, 73U },
4348 { X86::YMM23, 74U },
4349 { X86::YMM24, 75U },
4350 { X86::YMM25, 76U },
4351 { X86::YMM26, 77U },
4352 { X86::YMM27, 78U },
4353 { X86::YMM28, 79U },
4354 { X86::YMM29, 80U },
4355 { X86::YMM30, 81U },
4356 { X86::YMM31, 82U },
4357 { X86::ZMM0, 17U },
4358 { X86::ZMM1, 18U },
4359 { X86::ZMM2, 19U },
4360 { X86::ZMM3, 20U },
4361 { X86::ZMM4, 21U },
4362 { X86::ZMM5, 22U },
4363 { X86::ZMM6, 23U },
4364 { X86::ZMM7, 24U },
4365 { X86::ZMM8, 25U },
4366 { X86::ZMM9, 26U },
4367 { X86::ZMM10, 27U },
4368 { X86::ZMM11, 28U },
4369 { X86::ZMM12, 29U },
4370 { X86::ZMM13, 30U },
4371 { X86::ZMM14, 31U },
4372 { X86::ZMM15, 32U },
4373 { X86::ZMM16, 67U },
4374 { X86::ZMM17, 68U },
4375 { X86::ZMM18, 69U },
4376 { X86::ZMM19, 70U },
4377 { X86::ZMM20, 71U },
4378 { X86::ZMM21, 72U },
4379 { X86::ZMM22, 73U },
4380 { X86::ZMM23, 74U },
4381 { X86::ZMM24, 75U },
4382 { X86::ZMM25, 76U },
4383 { X86::ZMM26, 77U },
4384 { X86::ZMM27, 78U },
4385 { X86::ZMM28, 79U },
4386 { X86::ZMM29, 80U },
4387 { X86::ZMM30, 81U },
4388 { X86::ZMM31, 82U },
4389 { X86::R16, 130U },
4390 { X86::R17, 131U },
4391 { X86::R18, 132U },
4392 { X86::R19, 133U },
4393 { X86::R20, 134U },
4394 { X86::R21, 135U },
4395 { X86::R22, 136U },
4396 { X86::R23, 137U },
4397 { X86::R24, 138U },
4398 { X86::R25, 139U },
4399 { X86::R26, 140U },
4400 { X86::R27, 141U },
4401 { X86::R28, 142U },
4402 { X86::R29, 143U },
4403 { X86::R30, 144U },
4404 { X86::R31, 145U },
4405};
4406extern const unsigned X86EHFlavour0L2DwarfSize = std::size(X86EHFlavour0L2Dwarf);
4407
4408extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
4409 { X86::CS, -2U },
4410 { X86::DS, -2U },
4411 { X86::EAX, 0U },
4412 { X86::EBP, 4U },
4413 { X86::EBX, 3U },
4414 { X86::ECX, 1U },
4415 { X86::EDI, 7U },
4416 { X86::EDX, 2U },
4417 { X86::EFLAGS, 9U },
4418 { X86::EIP, 8U },
4419 { X86::ES, -2U },
4420 { X86::ESI, 6U },
4421 { X86::ESP, 5U },
4422 { X86::FS, -2U },
4423 { X86::FS_BASE, -2U },
4424 { X86::GS, -2U },
4425 { X86::GS_BASE, -2U },
4426 { X86::RAX, -2U },
4427 { X86::RBP, -2U },
4428 { X86::RBX, -2U },
4429 { X86::RCX, -2U },
4430 { X86::RDI, -2U },
4431 { X86::RDX, -2U },
4432 { X86::RFLAGS, -2U },
4433 { X86::RIP, -2U },
4434 { X86::RSI, -2U },
4435 { X86::RSP, -2U },
4436 { X86::SS, -2U },
4437 { X86::_EFLAGS, 9U },
4438 { X86::MM0, 29U },
4439 { X86::MM1, 30U },
4440 { X86::MM2, 31U },
4441 { X86::MM3, 32U },
4442 { X86::MM4, 33U },
4443 { X86::MM5, 34U },
4444 { X86::MM6, 35U },
4445 { X86::MM7, 36U },
4446 { X86::R8, -2U },
4447 { X86::R9, -2U },
4448 { X86::R10, -2U },
4449 { X86::R11, -2U },
4450 { X86::R12, -2U },
4451 { X86::R13, -2U },
4452 { X86::R14, -2U },
4453 { X86::R15, -2U },
4454 { X86::ST0, 12U },
4455 { X86::ST1, 13U },
4456 { X86::ST2, 14U },
4457 { X86::ST3, 15U },
4458 { X86::ST4, 16U },
4459 { X86::ST5, 17U },
4460 { X86::ST6, 18U },
4461 { X86::ST7, 19U },
4462 { X86::XMM0, 21U },
4463 { X86::XMM1, 22U },
4464 { X86::XMM2, 23U },
4465 { X86::XMM3, 24U },
4466 { X86::XMM4, 25U },
4467 { X86::XMM5, 26U },
4468 { X86::XMM6, 27U },
4469 { X86::XMM7, 28U },
4470 { X86::XMM8, -2U },
4471 { X86::XMM9, -2U },
4472 { X86::XMM10, -2U },
4473 { X86::XMM11, -2U },
4474 { X86::XMM12, -2U },
4475 { X86::XMM13, -2U },
4476 { X86::XMM14, -2U },
4477 { X86::XMM15, -2U },
4478 { X86::YMM0, 21U },
4479 { X86::YMM1, 22U },
4480 { X86::YMM2, 23U },
4481 { X86::YMM3, 24U },
4482 { X86::YMM4, 25U },
4483 { X86::YMM5, 26U },
4484 { X86::YMM6, 27U },
4485 { X86::YMM7, 28U },
4486 { X86::YMM8, -2U },
4487 { X86::YMM9, -2U },
4488 { X86::YMM10, -2U },
4489 { X86::YMM11, -2U },
4490 { X86::YMM12, -2U },
4491 { X86::YMM13, -2U },
4492 { X86::YMM14, -2U },
4493 { X86::YMM15, -2U },
4494 { X86::K0, 93U },
4495 { X86::K1, 94U },
4496 { X86::K2, 95U },
4497 { X86::K3, 96U },
4498 { X86::K4, 97U },
4499 { X86::K5, 98U },
4500 { X86::K6, 99U },
4501 { X86::K7, 100U },
4502 { X86::XMM16, -2U },
4503 { X86::XMM17, -2U },
4504 { X86::XMM18, -2U },
4505 { X86::XMM19, -2U },
4506 { X86::XMM20, -2U },
4507 { X86::XMM21, -2U },
4508 { X86::XMM22, -2U },
4509 { X86::XMM23, -2U },
4510 { X86::XMM24, -2U },
4511 { X86::XMM25, -2U },
4512 { X86::XMM26, -2U },
4513 { X86::XMM27, -2U },
4514 { X86::XMM28, -2U },
4515 { X86::XMM29, -2U },
4516 { X86::XMM30, -2U },
4517 { X86::XMM31, -2U },
4518 { X86::YMM16, -2U },
4519 { X86::YMM17, -2U },
4520 { X86::YMM18, -2U },
4521 { X86::YMM19, -2U },
4522 { X86::YMM20, -2U },
4523 { X86::YMM21, -2U },
4524 { X86::YMM22, -2U },
4525 { X86::YMM23, -2U },
4526 { X86::YMM24, -2U },
4527 { X86::YMM25, -2U },
4528 { X86::YMM26, -2U },
4529 { X86::YMM27, -2U },
4530 { X86::YMM28, -2U },
4531 { X86::YMM29, -2U },
4532 { X86::YMM30, -2U },
4533 { X86::YMM31, -2U },
4534 { X86::ZMM0, 21U },
4535 { X86::ZMM1, 22U },
4536 { X86::ZMM2, 23U },
4537 { X86::ZMM3, 24U },
4538 { X86::ZMM4, 25U },
4539 { X86::ZMM5, 26U },
4540 { X86::ZMM6, 27U },
4541 { X86::ZMM7, 28U },
4542 { X86::ZMM8, -2U },
4543 { X86::ZMM9, -2U },
4544 { X86::ZMM10, -2U },
4545 { X86::ZMM11, -2U },
4546 { X86::ZMM12, -2U },
4547 { X86::ZMM13, -2U },
4548 { X86::ZMM14, -2U },
4549 { X86::ZMM15, -2U },
4550 { X86::ZMM16, -2U },
4551 { X86::ZMM17, -2U },
4552 { X86::ZMM18, -2U },
4553 { X86::ZMM19, -2U },
4554 { X86::ZMM20, -2U },
4555 { X86::ZMM21, -2U },
4556 { X86::ZMM22, -2U },
4557 { X86::ZMM23, -2U },
4558 { X86::ZMM24, -2U },
4559 { X86::ZMM25, -2U },
4560 { X86::ZMM26, -2U },
4561 { X86::ZMM27, -2U },
4562 { X86::ZMM28, -2U },
4563 { X86::ZMM29, -2U },
4564 { X86::ZMM30, -2U },
4565 { X86::ZMM31, -2U },
4566 { X86::R16, -2U },
4567 { X86::R17, -2U },
4568 { X86::R18, -2U },
4569 { X86::R19, -2U },
4570 { X86::R20, -2U },
4571 { X86::R21, -2U },
4572 { X86::R22, -2U },
4573 { X86::R23, -2U },
4574 { X86::R24, -2U },
4575 { X86::R25, -2U },
4576 { X86::R26, -2U },
4577 { X86::R27, -2U },
4578 { X86::R28, -2U },
4579 { X86::R29, -2U },
4580 { X86::R30, -2U },
4581 { X86::R31, -2U },
4582};
4583extern const unsigned X86EHFlavour1L2DwarfSize = std::size(X86EHFlavour1L2Dwarf);
4584
4585extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
4586 { X86::CS, 41U },
4587 { X86::DS, 43U },
4588 { X86::EAX, 0U },
4589 { X86::EBP, 5U },
4590 { X86::EBX, 3U },
4591 { X86::ECX, 1U },
4592 { X86::EDI, 7U },
4593 { X86::EDX, 2U },
4594 { X86::EFLAGS, 9U },
4595 { X86::EIP, 8U },
4596 { X86::ES, 40U },
4597 { X86::ESI, 6U },
4598 { X86::ESP, 4U },
4599 { X86::FS, 44U },
4600 { X86::FS_BASE, -2U },
4601 { X86::GS, 45U },
4602 { X86::GS_BASE, -2U },
4603 { X86::RAX, -2U },
4604 { X86::RBP, -2U },
4605 { X86::RBX, -2U },
4606 { X86::RCX, -2U },
4607 { X86::RDI, -2U },
4608 { X86::RDX, -2U },
4609 { X86::RFLAGS, -2U },
4610 { X86::RIP, -2U },
4611 { X86::RSI, -2U },
4612 { X86::RSP, -2U },
4613 { X86::SS, 42U },
4614 { X86::_EFLAGS, 9U },
4615 { X86::MM0, 29U },
4616 { X86::MM1, 30U },
4617 { X86::MM2, 31U },
4618 { X86::MM3, 32U },
4619 { X86::MM4, 33U },
4620 { X86::MM5, 34U },
4621 { X86::MM6, 35U },
4622 { X86::MM7, 36U },
4623 { X86::R8, -2U },
4624 { X86::R9, -2U },
4625 { X86::R10, -2U },
4626 { X86::R11, -2U },
4627 { X86::R12, -2U },
4628 { X86::R13, -2U },
4629 { X86::R14, -2U },
4630 { X86::R15, -2U },
4631 { X86::ST0, 11U },
4632 { X86::ST1, 12U },
4633 { X86::ST2, 13U },
4634 { X86::ST3, 14U },
4635 { X86::ST4, 15U },
4636 { X86::ST5, 16U },
4637 { X86::ST6, 17U },
4638 { X86::ST7, 18U },
4639 { X86::XMM0, 21U },
4640 { X86::XMM1, 22U },
4641 { X86::XMM2, 23U },
4642 { X86::XMM3, 24U },
4643 { X86::XMM4, 25U },
4644 { X86::XMM5, 26U },
4645 { X86::XMM6, 27U },
4646 { X86::XMM7, 28U },
4647 { X86::XMM8, -2U },
4648 { X86::XMM9, -2U },
4649 { X86::XMM10, -2U },
4650 { X86::XMM11, -2U },
4651 { X86::XMM12, -2U },
4652 { X86::XMM13, -2U },
4653 { X86::XMM14, -2U },
4654 { X86::XMM15, -2U },
4655 { X86::YMM0, 21U },
4656 { X86::YMM1, 22U },
4657 { X86::YMM2, 23U },
4658 { X86::YMM3, 24U },
4659 { X86::YMM4, 25U },
4660 { X86::YMM5, 26U },
4661 { X86::YMM6, 27U },
4662 { X86::YMM7, 28U },
4663 { X86::YMM8, -2U },
4664 { X86::YMM9, -2U },
4665 { X86::YMM10, -2U },
4666 { X86::YMM11, -2U },
4667 { X86::YMM12, -2U },
4668 { X86::YMM13, -2U },
4669 { X86::YMM14, -2U },
4670 { X86::YMM15, -2U },
4671 { X86::K0, 93U },
4672 { X86::K1, 94U },
4673 { X86::K2, 95U },
4674 { X86::K3, 96U },
4675 { X86::K4, 97U },
4676 { X86::K5, 98U },
4677 { X86::K6, 99U },
4678 { X86::K7, 100U },
4679 { X86::XMM16, -2U },
4680 { X86::XMM17, -2U },
4681 { X86::XMM18, -2U },
4682 { X86::XMM19, -2U },
4683 { X86::XMM20, -2U },
4684 { X86::XMM21, -2U },
4685 { X86::XMM22, -2U },
4686 { X86::XMM23, -2U },
4687 { X86::XMM24, -2U },
4688 { X86::XMM25, -2U },
4689 { X86::XMM26, -2U },
4690 { X86::XMM27, -2U },
4691 { X86::XMM28, -2U },
4692 { X86::XMM29, -2U },
4693 { X86::XMM30, -2U },
4694 { X86::XMM31, -2U },
4695 { X86::YMM16, -2U },
4696 { X86::YMM17, -2U },
4697 { X86::YMM18, -2U },
4698 { X86::YMM19, -2U },
4699 { X86::YMM20, -2U },
4700 { X86::YMM21, -2U },
4701 { X86::YMM22, -2U },
4702 { X86::YMM23, -2U },
4703 { X86::YMM24, -2U },
4704 { X86::YMM25, -2U },
4705 { X86::YMM26, -2U },
4706 { X86::YMM27, -2U },
4707 { X86::YMM28, -2U },
4708 { X86::YMM29, -2U },
4709 { X86::YMM30, -2U },
4710 { X86::YMM31, -2U },
4711 { X86::ZMM0, 21U },
4712 { X86::ZMM1, 22U },
4713 { X86::ZMM2, 23U },
4714 { X86::ZMM3, 24U },
4715 { X86::ZMM4, 25U },
4716 { X86::ZMM5, 26U },
4717 { X86::ZMM6, 27U },
4718 { X86::ZMM7, 28U },
4719 { X86::ZMM8, -2U },
4720 { X86::ZMM9, -2U },
4721 { X86::ZMM10, -2U },
4722 { X86::ZMM11, -2U },
4723 { X86::ZMM12, -2U },
4724 { X86::ZMM13, -2U },
4725 { X86::ZMM14, -2U },
4726 { X86::ZMM15, -2U },
4727 { X86::ZMM16, -2U },
4728 { X86::ZMM17, -2U },
4729 { X86::ZMM18, -2U },
4730 { X86::ZMM19, -2U },
4731 { X86::ZMM20, -2U },
4732 { X86::ZMM21, -2U },
4733 { X86::ZMM22, -2U },
4734 { X86::ZMM23, -2U },
4735 { X86::ZMM24, -2U },
4736 { X86::ZMM25, -2U },
4737 { X86::ZMM26, -2U },
4738 { X86::ZMM27, -2U },
4739 { X86::ZMM28, -2U },
4740 { X86::ZMM29, -2U },
4741 { X86::ZMM30, -2U },
4742 { X86::ZMM31, -2U },
4743 { X86::R16, -2U },
4744 { X86::R17, -2U },
4745 { X86::R18, -2U },
4746 { X86::R19, -2U },
4747 { X86::R20, -2U },
4748 { X86::R21, -2U },
4749 { X86::R22, -2U },
4750 { X86::R23, -2U },
4751 { X86::R24, -2U },
4752 { X86::R25, -2U },
4753 { X86::R26, -2U },
4754 { X86::R27, -2U },
4755 { X86::R28, -2U },
4756 { X86::R29, -2U },
4757 { X86::R30, -2U },
4758 { X86::R31, -2U },
4759};
4760extern const unsigned X86EHFlavour2L2DwarfSize = std::size(X86EHFlavour2L2Dwarf);
4761
4762extern const uint16_t X86RegEncodingTable[] = {
4763 0,
4764 4,
4765 0,
4766 0,
4767 7,
4768 3,
4769 5,
4770 65535,
4771 5,
4772 3,
4773 5,
4774 1,
4775 1,
4776 1,
4777 0,
4778 6,
4779 7,
4780 65535,
4781 7,
4782 2,
4783 3,
4784 2,
4785 0,
4786 5,
4787 3,
4788 1,
4789 7,
4790 2,
4791 0,
4792 0,
4793 4,
4794 0,
4795 6,
4796 4,
4797 0,
4798 0,
4799 4,
4800 0,
4801 5,
4802 0,
4803 65535,
4804 65535,
4805 65535,
4806 65535,
4807 65535,
4808 65535,
4809 65535,
4810 65535,
4811 65535,
4812 0,
4813 0,
4814 0,
4815 5,
4816 3,
4817 1,
4818 7,
4819 2,
4820 0,
4821 0,
4822 4,
4823 6,
4824 4,
4825 6,
4826 65535,
4827 6,
4828 4,
4829 65535,
4830 4,
4831 2,
4832 0,
4833 0,
4834 0,
4835 1,
4836 2,
4837 3,
4838 4,
4839 5,
4840 6,
4841 7,
4842 8,
4843 9,
4844 10,
4845 11,
4846 12,
4847 13,
4848 14,
4849 15,
4850 0,
4851 1,
4852 2,
4853 3,
4854 4,
4855 5,
4856 6,
4857 7,
4858 8,
4859 9,
4860 10,
4861 11,
4862 12,
4863 13,
4864 14,
4865 15,
4866 0,
4867 0,
4868 0,
4869 0,
4870 0,
4871 0,
4872 0,
4873 0,
4874 0,
4875 1,
4876 2,
4877 3,
4878 4,
4879 5,
4880 6,
4881 7,
4882 8,
4883 9,
4884 10,
4885 11,
4886 12,
4887 13,
4888 14,
4889 15,
4890 0,
4891 1,
4892 2,
4893 3,
4894 4,
4895 5,
4896 6,
4897 7,
4898 0,
4899 1,
4900 2,
4901 3,
4902 4,
4903 5,
4904 6,
4905 7,
4906 8,
4907 9,
4908 10,
4909 11,
4910 12,
4911 13,
4912 14,
4913 15,
4914 8,
4915 9,
4916 10,
4917 11,
4918 12,
4919 13,
4920 14,
4921 15,
4922 65535,
4923 65535,
4924 65535,
4925 65535,
4926 65535,
4927 65535,
4928 65535,
4929 65535,
4930 8,
4931 9,
4932 10,
4933 11,
4934 12,
4935 13,
4936 14,
4937 15,
4938 8,
4939 9,
4940 10,
4941 11,
4942 12,
4943 13,
4944 14,
4945 15,
4946 65535,
4947 65535,
4948 65535,
4949 65535,
4950 65535,
4951 65535,
4952 65535,
4953 65535,
4954 0,
4955 1,
4956 2,
4957 3,
4958 4,
4959 5,
4960 6,
4961 7,
4962 8,
4963 9,
4964 10,
4965 11,
4966 12,
4967 13,
4968 14,
4969 15,
4970 0,
4971 1,
4972 2,
4973 3,
4974 4,
4975 5,
4976 6,
4977 7,
4978 16,
4979 17,
4980 18,
4981 19,
4982 20,
4983 21,
4984 22,
4985 23,
4986 24,
4987 25,
4988 26,
4989 27,
4990 28,
4991 29,
4992 30,
4993 31,
4994 16,
4995 17,
4996 18,
4997 19,
4998 20,
4999 21,
5000 22,
5001 23,
5002 24,
5003 25,
5004 26,
5005 27,
5006 28,
5007 29,
5008 30,
5009 31,
5010 0,
5011 1,
5012 2,
5013 3,
5014 4,
5015 5,
5016 6,
5017 7,
5018 8,
5019 9,
5020 10,
5021 11,
5022 12,
5023 13,
5024 14,
5025 15,
5026 16,
5027 17,
5028 18,
5029 19,
5030 20,
5031 21,
5032 22,
5033 23,
5034 24,
5035 25,
5036 26,
5037 27,
5038 28,
5039 29,
5040 30,
5041 31,
5042 0,
5043 2,
5044 4,
5045 6,
5046 0,
5047 0,
5048 1,
5049 2,
5050 3,
5051 4,
5052 5,
5053 6,
5054 7,
5055 16,
5056 17,
5057 18,
5058 19,
5059 20,
5060 21,
5061 22,
5062 23,
5063 24,
5064 25,
5065 26,
5066 27,
5067 28,
5068 29,
5069 30,
5070 31,
5071 16,
5072 17,
5073 18,
5074 19,
5075 20,
5076 21,
5077 22,
5078 23,
5079 24,
5080 25,
5081 26,
5082 27,
5083 28,
5084 29,
5085 30,
5086 31,
5087 65535,
5088 65535,
5089 65535,
5090 65535,
5091 65535,
5092 65535,
5093 65535,
5094 65535,
5095 65535,
5096 65535,
5097 65535,
5098 65535,
5099 65535,
5100 65535,
5101 65535,
5102 65535,
5103 16,
5104 17,
5105 18,
5106 19,
5107 20,
5108 21,
5109 22,
5110 23,
5111 24,
5112 25,
5113 26,
5114 27,
5115 28,
5116 29,
5117 30,
5118 31,
5119 16,
5120 17,
5121 18,
5122 19,
5123 20,
5124 21,
5125 22,
5126 23,
5127 24,
5128 25,
5129 26,
5130 27,
5131 28,
5132 29,
5133 30,
5134 31,
5135 65535,
5136 65535,
5137 65535,
5138 65535,
5139 65535,
5140 65535,
5141 65535,
5142 65535,
5143 65535,
5144 65535,
5145 65535,
5146 65535,
5147 65535,
5148 65535,
5149 65535,
5150 65535,
5151};
5152static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
5153 RI->InitMCRegisterInfo(X86RegDesc, 388, RA, PC, X86MCRegisterClasses, 134, X86RegUnitRoots, 221, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, X86RegClassStrings, X86SubRegIdxLists, 11,
5154X86RegEncodingTable);
5155
5156 switch (DwarfFlavour) {
5157 default:
5158 llvm_unreachable("Unknown DWARF flavour");
5159 case 0:
5160 RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
5161 break;
5162 case 1:
5163 RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
5164 break;
5165 case 2:
5166 RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
5167 break;
5168 }
5169 switch (EHFlavour) {
5170 default:
5171 llvm_unreachable("Unknown DWARF flavour");
5172 case 0:
5173 RI->mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
5174 break;
5175 case 1:
5176 RI->mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
5177 break;
5178 case 2:
5179 RI->mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
5180 break;
5181 }
5182 switch (DwarfFlavour) {
5183 default:
5184 llvm_unreachable("Unknown DWARF flavour");
5185 case 0:
5186 RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
5187 break;
5188 case 1:
5189 RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
5190 break;
5191 case 2:
5192 RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
5193 break;
5194 }
5195 switch (EHFlavour) {
5196 default:
5197 llvm_unreachable("Unknown DWARF flavour");
5198 case 0:
5199 RI->mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
5200 break;
5201 case 1:
5202 RI->mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
5203 break;
5204 case 2:
5205 RI->mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
5206 break;
5207 }
5208}
5209
5210} // end namespace llvm
5211
5212#endif // GET_REGINFO_MC_DESC
5213
5214/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5215|* *|
5216|* Register Information Header Fragment *|
5217|* *|
5218|* Automatically generated file, do not edit! *|
5219|* *|
5220\*===----------------------------------------------------------------------===*/
5221
5222
5223#ifdef GET_REGINFO_HEADER
5224#undef GET_REGINFO_HEADER
5225
5226#include "llvm/CodeGen/TargetRegisterInfo.h"
5227
5228namespace llvm {
5229
5230class X86FrameLowering;
5231
5232struct X86GenRegisterInfo : public TargetRegisterInfo {
5233 explicit X86GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
5234 unsigned PC = 0, unsigned HwMode = 0);
5235 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
5236 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5237 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
5238 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
5239 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
5240 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
5241 unsigned getRegUnitWeight(unsigned RegUnit) const override;
5242 unsigned getNumRegPressureSets() const override;
5243 const char *getRegPressureSetName(unsigned Idx) const override;
5244 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
5245 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
5246 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
5247 ArrayRef<const char *> getRegMaskNames() const override;
5248 ArrayRef<const uint32_t *> getRegMasks() const override;
5249 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
5250 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
5251 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
5252 bool isConstantPhysReg(MCRegister PhysReg) const override final;
5253 /// Devirtualized TargetFrameLowering.
5254 static const X86FrameLowering *getFrameLowering(
5255 const MachineFunction &MF);
5256};
5257
5258namespace X86 { // Register classes
5259 extern const TargetRegisterClass GR8RegClass;
5260 extern const TargetRegisterClass GRH8RegClass;
5261 extern const TargetRegisterClass GR8_NOREX2RegClass;
5262 extern const TargetRegisterClass GR8_NOREXRegClass;
5263 extern const TargetRegisterClass GR8_ABCD_HRegClass;
5264 extern const TargetRegisterClass GR8_ABCD_LRegClass;
5265 extern const TargetRegisterClass GRH16RegClass;
5266 extern const TargetRegisterClass GR16RegClass;
5267 extern const TargetRegisterClass GR16_NOREX2RegClass;
5268 extern const TargetRegisterClass GR16_NOREXRegClass;
5269 extern const TargetRegisterClass VK1RegClass;
5270 extern const TargetRegisterClass VK16RegClass;
5271 extern const TargetRegisterClass VK2RegClass;
5272 extern const TargetRegisterClass VK4RegClass;
5273 extern const TargetRegisterClass VK8RegClass;
5274 extern const TargetRegisterClass VK16WMRegClass;
5275 extern const TargetRegisterClass VK1WMRegClass;
5276 extern const TargetRegisterClass VK2WMRegClass;
5277 extern const TargetRegisterClass VK4WMRegClass;
5278 extern const TargetRegisterClass VK8WMRegClass;
5279 extern const TargetRegisterClass SEGMENT_REGRegClass;
5280 extern const TargetRegisterClass GR16_ABCDRegClass;
5281 extern const TargetRegisterClass FPCCRRegClass;
5282 extern const TargetRegisterClass FR16XRegClass;
5283 extern const TargetRegisterClass FR16RegClass;
5284 extern const TargetRegisterClass VK16PAIRRegClass;
5285 extern const TargetRegisterClass VK1PAIRRegClass;
5286 extern const TargetRegisterClass VK2PAIRRegClass;
5287 extern const TargetRegisterClass VK4PAIRRegClass;
5288 extern const TargetRegisterClass VK8PAIRRegClass;
5289 extern const TargetRegisterClass VK1PAIR_with_sub_mask_0_in_VK1WMRegClass;
5290 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass;
5291 extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass;
5292 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass;
5293 extern const TargetRegisterClass FR32XRegClass;
5294 extern const TargetRegisterClass GR32RegClass;
5295 extern const TargetRegisterClass GR32_NOSPRegClass;
5296 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass;
5297 extern const TargetRegisterClass DEBUG_REGRegClass;
5298 extern const TargetRegisterClass FR32RegClass;
5299 extern const TargetRegisterClass GR32_NOREX2RegClass;
5300 extern const TargetRegisterClass GR32_NOREX2_NOSPRegClass;
5301 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass;
5302 extern const TargetRegisterClass GR32_NOREXRegClass;
5303 extern const TargetRegisterClass VK32RegClass;
5304 extern const TargetRegisterClass GR32_NOREX_NOSPRegClass;
5305 extern const TargetRegisterClass RFP32RegClass;
5306 extern const TargetRegisterClass VK32WMRegClass;
5307 extern const TargetRegisterClass GR32_ABCDRegClass;
5308 extern const TargetRegisterClass GR32_TCRegClass;
5309 extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass;
5310 extern const TargetRegisterClass GR32_ADRegClass;
5311 extern const TargetRegisterClass GR32_ArgRefRegClass;
5312 extern const TargetRegisterClass GR32_BPSPRegClass;
5313 extern const TargetRegisterClass GR32_BSIRegClass;
5314 extern const TargetRegisterClass GR32_CBRegClass;
5315 extern const TargetRegisterClass GR32_DCRegClass;
5316 extern const TargetRegisterClass GR32_DIBPRegClass;
5317 extern const TargetRegisterClass GR32_SIDIRegClass;
5318 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass;
5319 extern const TargetRegisterClass CCRRegClass;
5320 extern const TargetRegisterClass DFCCRRegClass;
5321 extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass;
5322 extern const TargetRegisterClass GR32_AD_and_GR32_ArgRefRegClass;
5323 extern const TargetRegisterClass GR32_ArgRef_and_GR32_CBRegClass;
5324 extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass;
5325 extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass;
5326 extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass;
5327 extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass;
5328 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass;
5329 extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass;
5330 extern const TargetRegisterClass RFP64RegClass;
5331 extern const TargetRegisterClass GR64RegClass;
5332 extern const TargetRegisterClass FR64XRegClass;
5333 extern const TargetRegisterClass GR64_with_sub_8bitRegClass;
5334 extern const TargetRegisterClass GR64_NOSPRegClass;
5335 extern const TargetRegisterClass GR64_NOREX2RegClass;
5336 extern const TargetRegisterClass CONTROL_REGRegClass;
5337 extern const TargetRegisterClass FR64RegClass;
5338 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREX2RegClass;
5339 extern const TargetRegisterClass GR64_NOREX2_NOSPRegClass;
5340 extern const TargetRegisterClass GR64PLTSafeRegClass;
5341 extern const TargetRegisterClass GR64_TCRegClass;
5342 extern const TargetRegisterClass GR64_NOREXRegClass;
5343 extern const TargetRegisterClass GR64_TCW64RegClass;
5344 extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass;
5345 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCRegClass;
5346 extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass;
5347 extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass;
5348 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass;
5349 extern const TargetRegisterClass VK64RegClass;
5350 extern const TargetRegisterClass VR64RegClass;
5351 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCRegClass;
5352 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCW64RegClass;
5353 extern const TargetRegisterClass GR64_NOREX_NOSPRegClass;
5354 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass;
5355 extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass;
5356 extern const TargetRegisterClass VK64WMRegClass;
5357 extern const TargetRegisterClass GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass;
5358 extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass;
5359 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCW64RegClass;
5360 extern const TargetRegisterClass GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass;
5361 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass;
5362 extern const TargetRegisterClass GR64_ABCDRegClass;
5363 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass;
5364 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass;
5365 extern const TargetRegisterClass GR64_ADRegClass;
5366 extern const TargetRegisterClass GR64_ArgRefRegClass;
5367 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass;
5368 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRefRegClass;
5369 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass;
5370 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass;
5371 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass;
5372 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass;
5373 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass;
5374 extern const TargetRegisterClass GR64_ArgRef_and_GR64_TCRegClass;
5375 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass;
5376 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass;
5377 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass;
5378 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass;
5379 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass;
5380 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass;
5381 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass;
5382 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass;
5383 extern const TargetRegisterClass RSTRegClass;
5384 extern const TargetRegisterClass RFP80RegClass;
5385 extern const TargetRegisterClass RFP80_7RegClass;
5386 extern const TargetRegisterClass VR128XRegClass;
5387 extern const TargetRegisterClass VR128RegClass;
5388 extern const TargetRegisterClass VR256XRegClass;
5389 extern const TargetRegisterClass VR256RegClass;
5390 extern const TargetRegisterClass VR512RegClass;
5391 extern const TargetRegisterClass VR512_0_15RegClass;
5392 extern const TargetRegisterClass TILERegClass;
5393} // end namespace X86
5394
5395} // end namespace llvm
5396
5397#endif // GET_REGINFO_HEADER
5398
5399/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
5400|* *|
5401|* Target Register and Register Classes Information *|
5402|* *|
5403|* Automatically generated file, do not edit! *|
5404|* *|
5405\*===----------------------------------------------------------------------===*/
5406
5407
5408#ifdef GET_REGINFO_TARGET_DESC
5409#undef GET_REGINFO_TARGET_DESC
5410
5411namespace llvm {
5412
5413extern const MCRegisterClass X86MCRegisterClasses[];
5414
5415static const MVT::SimpleValueType VTLists[] = {
5416 /* 0 */ MVT::i8, MVT::Other,
5417 /* 2 */ MVT::i16, MVT::Other,
5418 /* 4 */ MVT::i32, MVT::Other,
5419 /* 6 */ MVT::i64, MVT::Other,
5420 /* 8 */ MVT::f16, MVT::Other,
5421 /* 10 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
5422 /* 14 */ MVT::f64, MVT::Other,
5423 /* 16 */ MVT::f80, MVT::Other,
5424 /* 18 */ MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::v8bf16, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
5425 /* 28 */ MVT::v1i1, MVT::Other,
5426 /* 30 */ MVT::v2i1, MVT::Other,
5427 /* 32 */ MVT::v4i1, MVT::Other,
5428 /* 34 */ MVT::v8i1, MVT::Other,
5429 /* 36 */ MVT::v16i1, MVT::Other,
5430 /* 38 */ MVT::v32i1, MVT::Other,
5431 /* 40 */ MVT::v64i1, MVT::Other,
5432 /* 42 */ MVT::v8f32, MVT::v4f64, MVT::v16f16, MVT::v16bf16, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
5433 /* 51 */ MVT::v16f32, MVT::v8f64, MVT::v32f16, MVT::v32bf16, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
5434 /* 60 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
5435 /* 67 */ MVT::x86mmx, MVT::Other,
5436 /* 69 */ MVT::Untyped, MVT::Other,
5437 /* 71 */ MVT::x86amx, MVT::Other,
5438};
5439
5440static const char *SubRegIndexNameTable[] = { "sub_8bit", "sub_8bit_hi", "sub_8bit_hi_phony", "sub_16bit", "sub_16bit_hi", "sub_32bit", "sub_mask_0", "sub_mask_1", "sub_xmm", "sub_ymm", "" };
5441
5442static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
5443 { 65535, 65535 },
5444 { 0, 8 }, // sub_8bit
5445 { 8, 8 }, // sub_8bit_hi
5446 { 8, 8 }, // sub_8bit_hi_phony
5447 { 0, 16 }, // sub_16bit
5448 { 16, 16 }, // sub_16bit_hi
5449 { 0, 32 }, // sub_32bit
5450 { 0, 65535 }, // sub_mask_0
5451 { 65535, 65535 }, // sub_mask_1
5452 { 0, 128 }, // sub_xmm
5453 { 0, 256 }, // sub_ymm
5454};
5455
5456
5457static const LaneBitmask SubRegIndexLaneMaskTable[] = {
5458 LaneBitmask::getAll(),
5459 LaneBitmask(0x0000000000000001), // sub_8bit
5460 LaneBitmask(0x0000000000000002), // sub_8bit_hi
5461 LaneBitmask(0x0000000000000004), // sub_8bit_hi_phony
5462 LaneBitmask(0x0000000000000007), // sub_16bit
5463 LaneBitmask(0x0000000000000008), // sub_16bit_hi
5464 LaneBitmask(0x000000000000000F), // sub_32bit
5465 LaneBitmask(0x0000000000000010), // sub_mask_0
5466 LaneBitmask(0x0000000000000020), // sub_mask_1
5467 LaneBitmask(0x0000000000000040), // sub_xmm
5468 LaneBitmask(0x0000000000000040), // sub_ymm
5469 };
5470
5471
5472
5473static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
5474 // Mode = 0 (Default)
5475 { 8, 8, 8, /*VTLists+*/0 }, // GR8
5476 { 8, 8, 8, /*VTLists+*/0 }, // GRH8
5477 { 8, 8, 8, /*VTLists+*/0 }, // GR8_NOREX2
5478 { 8, 8, 8, /*VTLists+*/0 }, // GR8_NOREX
5479 { 8, 8, 8, /*VTLists+*/0 }, // GR8_ABCD_H
5480 { 8, 8, 8, /*VTLists+*/0 }, // GR8_ABCD_L
5481 { 16, 16, 16, /*VTLists+*/2 }, // GRH16
5482 { 16, 16, 16, /*VTLists+*/2 }, // GR16
5483 { 16, 16, 16, /*VTLists+*/2 }, // GR16_NOREX2
5484 { 16, 16, 16, /*VTLists+*/2 }, // GR16_NOREX
5485 { 16, 16, 16, /*VTLists+*/28 }, // VK1
5486 { 16, 16, 16, /*VTLists+*/36 }, // VK16
5487 { 16, 16, 16, /*VTLists+*/30 }, // VK2
5488 { 16, 16, 16, /*VTLists+*/32 }, // VK4
5489 { 16, 16, 16, /*VTLists+*/34 }, // VK8
5490 { 16, 16, 16, /*VTLists+*/36 }, // VK16WM
5491 { 16, 16, 16, /*VTLists+*/28 }, // VK1WM
5492 { 16, 16, 16, /*VTLists+*/30 }, // VK2WM
5493 { 16, 16, 16, /*VTLists+*/32 }, // VK4WM
5494 { 16, 16, 16, /*VTLists+*/34 }, // VK8WM
5495 { 16, 16, 16, /*VTLists+*/2 }, // SEGMENT_REG
5496 { 16, 16, 16, /*VTLists+*/2 }, // GR16_ABCD
5497 { 16, 16, 16, /*VTLists+*/2 }, // FPCCR
5498 { 32, 32, 16, /*VTLists+*/8 }, // FR16X
5499 { 32, 32, 16, /*VTLists+*/8 }, // FR16
5500 { 32, 32, 16, /*VTLists+*/69 }, // VK16PAIR
5501 { 32, 32, 16, /*VTLists+*/69 }, // VK1PAIR
5502 { 32, 32, 16, /*VTLists+*/69 }, // VK2PAIR
5503 { 32, 32, 16, /*VTLists+*/69 }, // VK4PAIR
5504 { 32, 32, 16, /*VTLists+*/69 }, // VK8PAIR
5505 { 32, 32, 16, /*VTLists+*/69 }, // VK1PAIR_with_sub_mask_0_in_VK1WM
5506 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP
5507 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS
5508 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
5509 { 32, 32, 32, /*VTLists+*/12 }, // FR32X
5510 { 32, 32, 32, /*VTLists+*/4 }, // GR32
5511 { 32, 32, 32, /*VTLists+*/4 }, // GR32_NOSP
5512 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
5513 { 32, 32, 32, /*VTLists+*/4 }, // DEBUG_REG
5514 { 32, 32, 32, /*VTLists+*/12 }, // FR32
5515 { 32, 32, 32, /*VTLists+*/4 }, // GR32_NOREX2
5516 { 32, 32, 32, /*VTLists+*/4 }, // GR32_NOREX2_NOSP
5517 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
5518 { 32, 32, 32, /*VTLists+*/4 }, // GR32_NOREX
5519 { 32, 32, 32, /*VTLists+*/38 }, // VK32
5520 { 32, 32, 32, /*VTLists+*/4 }, // GR32_NOREX_NOSP
5521 { 32, 32, 32, /*VTLists+*/12 }, // RFP32
5522 { 32, 32, 32, /*VTLists+*/38 }, // VK32WM
5523 { 32, 32, 32, /*VTLists+*/4 }, // GR32_ABCD
5524 { 32, 32, 32, /*VTLists+*/4 }, // GR32_TC
5525 { 32, 32, 32, /*VTLists+*/4 }, // GR32_ABCD_and_GR32_TC
5526 { 32, 32, 32, /*VTLists+*/4 }, // GR32_AD
5527 { 32, 32, 32, /*VTLists+*/4 }, // GR32_ArgRef
5528 { 32, 32, 32, /*VTLists+*/4 }, // GR32_BPSP
5529 { 32, 32, 32, /*VTLists+*/4 }, // GR32_BSI
5530 { 32, 32, 32, /*VTLists+*/4 }, // GR32_CB
5531 { 32, 32, 32, /*VTLists+*/4 }, // GR32_DC
5532 { 32, 32, 32, /*VTLists+*/4 }, // GR32_DIBP
5533 { 32, 32, 32, /*VTLists+*/4 }, // GR32_SIDI
5534 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
5535 { 32, 32, 32, /*VTLists+*/4 }, // CCR
5536 { 32, 32, 32, /*VTLists+*/4 }, // DFCCR
5537 { 32, 32, 32, /*VTLists+*/4 }, // GR32_ABCD_and_GR32_BSI
5538 { 32, 32, 32, /*VTLists+*/4 }, // GR32_AD_and_GR32_ArgRef
5539 { 32, 32, 32, /*VTLists+*/4 }, // GR32_ArgRef_and_GR32_CB
5540 { 32, 32, 32, /*VTLists+*/4 }, // GR32_BPSP_and_GR32_DIBP
5541 { 32, 32, 32, /*VTLists+*/4 }, // GR32_BPSP_and_GR32_TC
5542 { 32, 32, 32, /*VTLists+*/4 }, // GR32_BSI_and_GR32_SIDI
5543 { 32, 32, 32, /*VTLists+*/4 }, // GR32_DIBP_and_GR32_SIDI
5544 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
5545 { 32, 32, 32, /*VTLists+*/4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
5546 { 64, 64, 32, /*VTLists+*/14 }, // RFP64
5547 { 64, 64, 64, /*VTLists+*/6 }, // GR64
5548 { 64, 64, 64, /*VTLists+*/14 }, // FR64X
5549 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_8bit
5550 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOSP
5551 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX2
5552 { 64, 64, 64, /*VTLists+*/6 }, // CONTROL_REG
5553 { 64, 64, 64, /*VTLists+*/14 }, // FR64
5554 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_16bit_in_GR16_NOREX2
5555 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX2_NOSP
5556 { 64, 64, 64, /*VTLists+*/6 }, // GR64PLTSafe
5557 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TC
5558 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX
5559 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TCW64
5560 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TC_with_sub_8bit
5561 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX2_NOSP_and_GR64_TC
5562 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TCW64_with_sub_8bit
5563 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TC_and_GR64_TCW64
5564 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_16bit_in_GR16_NOREX
5565 { 64, 64, 64, /*VTLists+*/40 }, // VK64
5566 { 64, 64, 64, /*VTLists+*/67 }, // VR64
5567 { 64, 64, 64, /*VTLists+*/6 }, // GR64PLTSafe_and_GR64_TC
5568 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX2_NOSP_and_GR64_TCW64
5569 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX_NOSP
5570 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX_and_GR64_TC
5571 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
5572 { 64, 64, 64, /*VTLists+*/40 }, // VK64WM
5573 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
5574 { 64, 64, 64, /*VTLists+*/6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
5575 { 64, 64, 64, /*VTLists+*/6 }, // GR64PLTSafe_and_GR64_TCW64
5576 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
5577 { 64, 64, 64, /*VTLists+*/6 }, // GR64_NOREX_and_GR64_TCW64
5578 { 64, 64, 64, /*VTLists+*/6 }, // GR64_ABCD
5579 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_TC
5580 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5581 { 64, 64, 64, /*VTLists+*/6 }, // GR64_AD
5582 { 64, 64, 64, /*VTLists+*/6 }, // GR64_ArgRef
5583 { 64, 64, 64, /*VTLists+*/6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
5584 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_ArgRef
5585 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BPSP
5586 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BSI
5587 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_CB
5588 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_DIBP
5589 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_SIDI
5590 { 64, 64, 64, /*VTLists+*/6 }, // GR64_ArgRef_and_GR64_TC
5591 { 64, 64, 64, /*VTLists+*/6 }, // GR64_and_LOW32_ADDR_ACCESS
5592 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
5593 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
5594 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
5595 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
5596 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
5597 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
5598 { 64, 64, 64, /*VTLists+*/6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
5599 { 80, 80, 32, /*VTLists+*/10 }, // RST
5600 { 80, 80, 32, /*VTLists+*/16 }, // RFP80
5601 { 80, 80, 32, /*VTLists+*/16 }, // RFP80_7
5602 { 128, 128, 128, /*VTLists+*/18 }, // VR128X
5603 { 128, 128, 128, /*VTLists+*/18 }, // VR128
5604 { 256, 256, 256, /*VTLists+*/42 }, // VR256X
5605 { 256, 256, 256, /*VTLists+*/42 }, // VR256
5606 { 512, 512, 512, /*VTLists+*/51 }, // VR512
5607 { 512, 512, 512, /*VTLists+*/60 }, // VR512_0_15
5608 { 8192, 8192, 8192, /*VTLists+*/71 }, // TILE
5609};
5610
5611static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
5612
5613static const uint32_t GR8SubClassMask[] = {
5614 0x0000003d, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5615 0x00200380, 0xc7ff2f3a, 0x72e38c3f, 0x0fefefbd, 0x00000000, // sub_8bit
5616 0x00200000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_8bit_hi
5617};
5618
5619static const uint32_t GRH8SubClassMask[] = {
5620 0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5621};
5622
5623static const uint32_t GR8_NOREX2SubClassMask[] = {
5624 0x0000003c, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5625 0x00200300, 0xc7ff2f20, 0x72e3803f, 0x0fefefbd, 0x00000000, // sub_8bit
5626 0x00200000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_8bit_hi
5627};
5628
5629static const uint32_t GR8_NOREXSubClassMask[] = {
5630 0x00000038, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5631 0x00200000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_8bit
5632 0x00200000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_8bit_hi
5633};
5634
5635static const uint32_t GR8_ABCD_HSubClassMask[] = {
5636 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5637 0x00200000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_8bit_hi
5638};
5639
5640static const uint32_t GR8_ABCD_LSubClassMask[] = {
5641 0x00000020, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5642 0x00200000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_8bit
5643};
5644
5645static const uint32_t GRH16SubClassMask[] = {
5646 0x00000040, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5647};
5648
5649static const uint32_t GR16SubClassMask[] = {
5650 0x00200380, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5651 0x00000000, 0xc7ff2f3a, 0x72e38c3f, 0x0fefefbd, 0x00000000, // sub_16bit
5652};
5653
5654static const uint32_t GR16_NOREX2SubClassMask[] = {
5655 0x00200300, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5656 0x00000000, 0xc7ff2f20, 0x72e3803f, 0x0fefefbd, 0x00000000, // sub_16bit
5657};
5658
5659static const uint32_t GR16_NOREXSubClassMask[] = {
5660 0x00200200, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5661 0x00000000, 0xc7ff2c00, 0x4200003f, 0x0fe7e7a8, 0x00000000, // sub_16bit
5662};
5663
5664static const uint32_t VK1SubClassMask[] = {
5665 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
5666 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5667 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5668};
5669
5670static const uint32_t VK16SubClassMask[] = {
5671 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
5672 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5673 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5674};
5675
5676static const uint32_t VK2SubClassMask[] = {
5677 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
5678 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5679 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5680};
5681
5682static const uint32_t VK4SubClassMask[] = {
5683 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
5684 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5685 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5686};
5687
5688static const uint32_t VK8SubClassMask[] = {
5689 0x000ffc00, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
5690 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5691 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5692};
5693
5694static const uint32_t VK16WMSubClassMask[] = {
5695 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
5696 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5697 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5698};
5699
5700static const uint32_t VK1WMSubClassMask[] = {
5701 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
5702 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5703 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5704};
5705
5706static const uint32_t VK2WMSubClassMask[] = {
5707 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
5708 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5709 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5710};
5711
5712static const uint32_t VK4WMSubClassMask[] = {
5713 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
5714 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5715 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5716};
5717
5718static const uint32_t VK8WMSubClassMask[] = {
5719 0x000f8000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
5720 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5721 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5722};
5723
5724static const uint32_t SEGMENT_REGSubClassMask[] = {
5725 0x00100000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5726};
5727
5728static const uint32_t GR16_ABCDSubClassMask[] = {
5729 0x00200000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5730 0x00000000, 0xc19d0000, 0x00000001, 0x00e12680, 0x00000000, // sub_16bit
5731};
5732
5733static const uint32_t FPCCRSubClassMask[] = {
5734 0x00400000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5735};
5736
5737static const uint32_t FR16XSubClassMask[] = {
5738 0x01800000, 0x00000084, 0x00004200, 0x80000000, 0x00000001,
5739 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000001e, // sub_xmm
5740};
5741
5742static const uint32_t FR16SubClassMask[] = {
5743 0x01000000, 0x00000080, 0x00004000, 0x00000000, 0x00000001,
5744 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000014, // sub_xmm
5745};
5746
5747static const uint32_t VK16PAIRSubClassMask[] = {
5748 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5749};
5750
5751static const uint32_t VK1PAIRSubClassMask[] = {
5752 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5753};
5754
5755static const uint32_t VK2PAIRSubClassMask[] = {
5756 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5757};
5758
5759static const uint32_t VK4PAIRSubClassMask[] = {
5760 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5761};
5762
5763static const uint32_t VK8PAIRSubClassMask[] = {
5764 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5765};
5766
5767static const uint32_t VK1PAIR_with_sub_mask_0_in_VK1WMSubClassMask[] = {
5768 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5769};
5770
5771static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
5772 0x80000000, 0xcfff2f3b, 0x0000007f, 0x01101000, 0x00000000,
5773 0x00000000, 0x00000000, 0x72e38c20, 0x0fefefbd, 0x00000000, // sub_32bit
5774};
5775
5776static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = {
5777 0x00000000, 0xc7ff2b19, 0x0000005f, 0x00100000, 0x00000000,
5778 0x00000000, 0x00000000, 0x72e38c20, 0x0fefefbd, 0x00000000, // sub_32bit
5779};
5780
5781static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = {
5782 0x00000000, 0xc7ff2f3a, 0x0000003f, 0x01000000, 0x00000000,
5783 0x00000000, 0x00000000, 0x72e38c20, 0x0fefefbd, 0x00000000, // sub_32bit
5784};
5785
5786static const uint32_t FR32XSubClassMask[] = {
5787 0x00000000, 0x00000084, 0x00004200, 0x80000000, 0x00000001,
5788 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000001e, // sub_xmm
5789};
5790
5791static const uint32_t GR32SubClassMask[] = {
5792 0x00000000, 0xc7ff2b18, 0x0000001f, 0x00000000, 0x00000000,
5793 0x00000000, 0x00000000, 0x72e38c20, 0x0fefefbd, 0x00000000, // sub_32bit
5794};
5795
5796static const uint32_t GR32_NOSPSubClassMask[] = {
5797 0x00000000, 0xc7dd2210, 0x0000001b, 0x00000000, 0x00000000,
5798 0x00000000, 0x00000000, 0x70430820, 0x0defaeb4, 0x00000000, // sub_32bit
5799};
5800
5801static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2SubClassMask[] = {
5802 0x00000000, 0xc7ff2f20, 0x0000003f, 0x01000000, 0x00000000,
5803 0x00000000, 0x00000000, 0x72e38020, 0x0fefefbd, 0x00000000, // sub_32bit
5804};
5805
5806static const uint32_t DEBUG_REGSubClassMask[] = {
5807 0x00000000, 0x00000040, 0x00000000, 0x00000000, 0x00000000,
5808};
5809
5810static const uint32_t FR32SubClassMask[] = {
5811 0x00000000, 0x00000080, 0x00004000, 0x00000000, 0x00000001,
5812 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000014, // sub_xmm
5813};
5814
5815static const uint32_t GR32_NOREX2SubClassMask[] = {
5816 0x00000000, 0xc7ff2b00, 0x0000001f, 0x00000000, 0x00000000,
5817 0x00000000, 0x00000000, 0x72e38020, 0x0fefefbd, 0x00000000, // sub_32bit
5818};
5819
5820static const uint32_t GR32_NOREX2_NOSPSubClassMask[] = {
5821 0x00000000, 0xc7dd2200, 0x0000001b, 0x00000000, 0x00000000,
5822 0x00000000, 0x00000000, 0x70430020, 0x0defaeb4, 0x00000000, // sub_32bit
5823};
5824
5825static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
5826 0x00000000, 0xc7ff2c00, 0x0000003f, 0x01000000, 0x00000000,
5827 0x00000000, 0x00000000, 0x42000020, 0x0fe7e7a8, 0x00000000, // sub_32bit
5828};
5829
5830static const uint32_t GR32_NOREXSubClassMask[] = {
5831 0x00000000, 0xc7ff2800, 0x0000001f, 0x00000000, 0x00000000,
5832 0x00000000, 0x00000000, 0x42000020, 0x0fe7e7a8, 0x00000000, // sub_32bit
5833};
5834
5835static const uint32_t VK32SubClassMask[] = {
5836 0x00000000, 0x00009000, 0x04000000, 0x00000002, 0x00000000,
5837 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5838 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5839};
5840
5841static const uint32_t GR32_NOREX_NOSPSubClassMask[] = {
5842 0x00000000, 0xc7dd2000, 0x0000001b, 0x00000000, 0x00000000,
5843 0x00000000, 0x00000000, 0x40000020, 0x0de7a6a0, 0x00000000, // sub_32bit
5844};
5845
5846static const uint32_t RFP32SubClassMask[] = {
5847 0x00000000, 0x00004000, 0x00000080, 0x20000000, 0x00000000,
5848};
5849
5850static const uint32_t VK32WMSubClassMask[] = {
5851 0x00000000, 0x00008000, 0x00000000, 0x00000002, 0x00000000,
5852 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
5853 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
5854};
5855
5856static const uint32_t GR32_ABCDSubClassMask[] = {
5857 0x00000000, 0xc19d0000, 0x00000001, 0x00000000, 0x00000000,
5858 0x00000000, 0x00000000, 0x00000000, 0x00e12680, 0x00000000, // sub_32bit
5859};
5860
5861static const uint32_t GR32_TCSubClassMask[] = {
5862 0x00000000, 0x811e0000, 0x00000005, 0x00000000, 0x00000000,
5863 0x00000000, 0x00000000, 0x00000000, 0x02c02700, 0x00000000, // sub_32bit
5864};
5865
5866static const uint32_t GR32_ABCD_and_GR32_TCSubClassMask[] = {
5867 0x00000000, 0x811c0000, 0x00000001, 0x00000000, 0x00000000,
5868 0x00000000, 0x00000000, 0x00000000, 0x00c02600, 0x00000000, // sub_32bit
5869};
5870
5871static const uint32_t GR32_ADSubClassMask[] = {
5872 0x00000000, 0x80080000, 0x00000000, 0x00000000, 0x00000000,
5873 0x00000000, 0x00000000, 0x00000000, 0x00400400, 0x00000000, // sub_32bit
5874};
5875
5876static const uint32_t GR32_ArgRefSubClassMask[] = {
5877 0x00000000, 0x81100000, 0x00000001, 0x00000000, 0x00000000,
5878 0x00000000, 0x00000000, 0x00000000, 0x00c02000, 0x00000000, // sub_32bit
5879};
5880
5881static const uint32_t GR32_BPSPSubClassMask[] = {
5882 0x00000000, 0x00200000, 0x00000006, 0x00000000, 0x00000000,
5883 0x00000000, 0x00000000, 0x00000020, 0x03004000, 0x00000000, // sub_32bit
5884};
5885
5886static const uint32_t GR32_BSISubClassMask[] = {
5887 0x00000000, 0x40400000, 0x00000008, 0x00000000, 0x00000000,
5888 0x00000000, 0x00000000, 0x00000000, 0x04208000, 0x00000000, // sub_32bit
5889};
5890
5891static const uint32_t GR32_CBSubClassMask[] = {
5892 0x00000000, 0x40800000, 0x00000001, 0x00000000, 0x00000000,
5893 0x00000000, 0x00000000, 0x00000000, 0x00a10000, 0x00000000, // sub_32bit
5894};
5895
5896static const uint32_t GR32_DCSubClassMask[] = {
5897 0x00000000, 0x81000000, 0x00000001, 0x00000000, 0x00000000,
5898 0x00000000, 0x00000000, 0x00000000, 0x00c02000, 0x00000000, // sub_32bit
5899};
5900
5901static const uint32_t GR32_DIBPSubClassMask[] = {
5902 0x00000000, 0x02000000, 0x00000012, 0x00000000, 0x00000000,
5903 0x00000000, 0x00000000, 0x00000020, 0x09020000, 0x00000000, // sub_32bit
5904};
5905
5906static const uint32_t GR32_SIDISubClassMask[] = {
5907 0x00000000, 0x04000000, 0x00000018, 0x00000000, 0x00000000,
5908 0x00000000, 0x00000000, 0x00000000, 0x0c040000, 0x00000000, // sub_32bit
5909};
5910
5911static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = {
5912 0x00000000, 0x08000000, 0x00000060, 0x01101000, 0x00000000,
5913};
5914
5915static const uint32_t CCRSubClassMask[] = {
5916 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000,
5917};
5918
5919static const uint32_t DFCCRSubClassMask[] = {
5920 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000,
5921};
5922
5923static const uint32_t GR32_ABCD_and_GR32_BSISubClassMask[] = {
5924 0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000,
5925 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00000000, // sub_32bit
5926};
5927
5928static const uint32_t GR32_AD_and_GR32_ArgRefSubClassMask[] = {
5929 0x00000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000,
5930 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000, // sub_32bit
5931};
5932
5933static const uint32_t GR32_ArgRef_and_GR32_CBSubClassMask[] = {
5934 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000,
5935 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000, // sub_32bit
5936};
5937
5938static const uint32_t GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
5939 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000,
5940 0x00000000, 0x00000000, 0x00000020, 0x01000000, 0x00000000, // sub_32bit
5941};
5942
5943static const uint32_t GR32_BPSP_and_GR32_TCSubClassMask[] = {
5944 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000,
5945 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x00000000, // sub_32bit
5946};
5947
5948static const uint32_t GR32_BSI_and_GR32_SIDISubClassMask[] = {
5949 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000,
5950 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000, // sub_32bit
5951};
5952
5953static const uint32_t GR32_DIBP_and_GR32_SIDISubClassMask[] = {
5954 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000,
5955 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000, // sub_32bit
5956};
5957
5958static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = {
5959 0x00000000, 0x00000000, 0x00000020, 0x01000000, 0x00000000,
5960};
5961
5962static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = {
5963 0x00000000, 0x00000000, 0x00000040, 0x00100000, 0x00000000,
5964};
5965
5966static const uint32_t RFP64SubClassMask[] = {
5967 0x00000000, 0x00000000, 0x00000080, 0x20000000, 0x00000000,
5968};
5969
5970static const uint32_t GR64SubClassMask[] = {
5971 0x00000000, 0x00000000, 0xf3ff9d00, 0x0ffffffd, 0x00000000,
5972};
5973
5974static const uint32_t FR64XSubClassMask[] = {
5975 0x00000000, 0x00000000, 0x00004200, 0x80000000, 0x00000001,
5976 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000001e, // sub_xmm
5977};
5978
5979static const uint32_t GR64_with_sub_8bitSubClassMask[] = {
5980 0x00000000, 0x00000000, 0x72e38c00, 0x0fefefbd, 0x00000000,
5981};
5982
5983static const uint32_t GR64_NOSPSubClassMask[] = {
5984 0x00000000, 0x00000000, 0x70430800, 0x0defaeb4, 0x00000000,
5985};
5986
5987static const uint32_t GR64_NOREX2SubClassMask[] = {
5988 0x00000000, 0x00000000, 0xf3ff9000, 0x0ffffffd, 0x00000000,
5989};
5990
5991static const uint32_t CONTROL_REGSubClassMask[] = {
5992 0x00000000, 0x00000000, 0x00002000, 0x00000000, 0x00000000,
5993};
5994
5995static const uint32_t FR64SubClassMask[] = {
5996 0x00000000, 0x00000000, 0x00004000, 0x00000000, 0x00000001,
5997 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000014, // sub_xmm
5998};
5999
6000static const uint32_t GR64_with_sub_16bit_in_GR16_NOREX2SubClassMask[] = {
6001 0x00000000, 0x00000000, 0x72e38000, 0x0fefefbd, 0x00000000,
6002};
6003
6004static const uint32_t GR64_NOREX2_NOSPSubClassMask[] = {
6005 0x00000000, 0x00000000, 0x70430000, 0x0defaeb4, 0x00000000,
6006};
6007
6008static const uint32_t GR64PLTSafeSubClassMask[] = {
6009 0x00000000, 0x00000000, 0x50020000, 0x0de7a6b0, 0x00000000,
6010};
6011
6012static const uint32_t GR64_TCSubClassMask[] = {
6013 0x00000000, 0x00000000, 0x91640000, 0x0edc277d, 0x00000000,
6014};
6015
6016static const uint32_t GR64_NOREXSubClassMask[] = {
6017 0x00000000, 0x00000000, 0xc2080000, 0x0ff7f7e8, 0x00000000,
6018};
6019
6020static const uint32_t GR64_TCW64SubClassMask[] = {
6021 0x00000000, 0x00000000, 0x21900000, 0x02d82f55, 0x00000000,
6022};
6023
6024static const uint32_t GR64_TC_with_sub_8bitSubClassMask[] = {
6025 0x00000000, 0x00000000, 0x10600000, 0x0ecc273d, 0x00000000,
6026};
6027
6028static const uint32_t GR64_NOREX2_NOSP_and_GR64_TCSubClassMask[] = {
6029 0x00000000, 0x00000000, 0x10400000, 0x0ccc2634, 0x00000000,
6030};
6031
6032static const uint32_t GR64_TCW64_with_sub_8bitSubClassMask[] = {
6033 0x00000000, 0x00000000, 0x20800000, 0x02c82f15, 0x00000000,
6034};
6035
6036static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = {
6037 0x00000000, 0x00000000, 0x01000000, 0x02d82755, 0x00000000,
6038};
6039
6040static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
6041 0x00000000, 0x00000000, 0x42000000, 0x0fe7e7a8, 0x00000000,
6042};
6043
6044static const uint32_t VK64SubClassMask[] = {
6045 0x00000000, 0x00000000, 0x04000000, 0x00000002, 0x00000000,
6046 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
6047 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
6048};
6049
6050static const uint32_t VR64SubClassMask[] = {
6051 0x00000000, 0x00000000, 0x08000000, 0x00000000, 0x00000000,
6052};
6053
6054static const uint32_t GR64PLTSafe_and_GR64_TCSubClassMask[] = {
6055 0x00000000, 0x00000000, 0x10000000, 0x0cc42630, 0x00000000,
6056};
6057
6058static const uint32_t GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask[] = {
6059 0x00000000, 0x00000000, 0x20000000, 0x00c82e14, 0x00000000,
6060};
6061
6062static const uint32_t GR64_NOREX_NOSPSubClassMask[] = {
6063 0x00000000, 0x00000000, 0x40000000, 0x0de7a6a0, 0x00000000,
6064};
6065
6066static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = {
6067 0x00000000, 0x00000000, 0x80000000, 0x0ed42768, 0x00000000,
6068};
6069
6070static const uint32_t GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask[] = {
6071 0x00000000, 0x00000000, 0x00000000, 0x02c82715, 0x00000000,
6072};
6073
6074static const uint32_t VK64WMSubClassMask[] = {
6075 0x00000000, 0x00000000, 0x00000000, 0x00000002, 0x00000000,
6076 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
6077 0x7e000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
6078};
6079
6080static const uint32_t GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask[] = {
6081 0x00000000, 0x00000000, 0x00000000, 0x00c82614, 0x00000000,
6082};
6083
6084static const uint32_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
6085 0x00000000, 0x00000000, 0x00000000, 0x0ec42728, 0x00000000,
6086};
6087
6088static const uint32_t GR64PLTSafe_and_GR64_TCW64SubClassMask[] = {
6089 0x00000000, 0x00000000, 0x00000000, 0x00c02610, 0x00000000,
6090};
6091
6092static const uint32_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask[] = {
6093 0x00000000, 0x00000000, 0x00000000, 0x0cc42620, 0x00000000,
6094};
6095
6096static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = {
6097 0x00000000, 0x00000000, 0x00000000, 0x02d02740, 0x00000000,
6098};
6099
6100static const uint32_t GR64_ABCDSubClassMask[] = {
6101 0x00000000, 0x00000000, 0x00000000, 0x00e12680, 0x00000000,
6102};
6103
6104static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = {
6105 0x00000000, 0x00000000, 0x00000000, 0x02c02700, 0x00000000,
6106};
6107
6108static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask[] = {
6109 0x00000000, 0x00000000, 0x00000000, 0x00c02600, 0x00000000,
6110};
6111
6112static const uint32_t GR64_ADSubClassMask[] = {
6113 0x00000000, 0x00000000, 0x00000000, 0x00400400, 0x00000000,
6114};
6115
6116static const uint32_t GR64_ArgRefSubClassMask[] = {
6117 0x00000000, 0x00000000, 0x00000000, 0x00080800, 0x00000000,
6118};
6119
6120static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
6121 0x00000000, 0x00000000, 0x00000000, 0x01101000, 0x00000000,
6122};
6123
6124static const uint32_t GR64_with_sub_32bit_in_GR32_ArgRefSubClassMask[] = {
6125 0x00000000, 0x00000000, 0x00000000, 0x00c02000, 0x00000000,
6126};
6127
6128static const uint32_t GR64_with_sub_32bit_in_GR32_BPSPSubClassMask[] = {
6129 0x00000000, 0x00000000, 0x00000000, 0x03004000, 0x00000000,
6130};
6131
6132static const uint32_t GR64_with_sub_32bit_in_GR32_BSISubClassMask[] = {
6133 0x00000000, 0x00000000, 0x00000000, 0x04208000, 0x00000000,
6134};
6135
6136static const uint32_t GR64_with_sub_32bit_in_GR32_CBSubClassMask[] = {
6137 0x00000000, 0x00000000, 0x00000000, 0x00a10000, 0x00000000,
6138};
6139
6140static const uint32_t GR64_with_sub_32bit_in_GR32_DIBPSubClassMask[] = {
6141 0x00000000, 0x00000000, 0x00000000, 0x09020000, 0x00000000,
6142};
6143
6144static const uint32_t GR64_with_sub_32bit_in_GR32_SIDISubClassMask[] = {
6145 0x00000000, 0x00000000, 0x00000000, 0x0c040000, 0x00000000,
6146};
6147
6148static const uint32_t GR64_ArgRef_and_GR64_TCSubClassMask[] = {
6149 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000,
6150};
6151
6152static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = {
6153 0x00000000, 0x00000000, 0x00000000, 0x00100000, 0x00000000,
6154};
6155
6156static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask[] = {
6157 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00000000,
6158};
6159
6160static const uint32_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSubClassMask[] = {
6161 0x00000000, 0x00000000, 0x00000000, 0x00400000, 0x00000000,
6162};
6163
6164static const uint32_t GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSubClassMask[] = {
6165 0x00000000, 0x00000000, 0x00000000, 0x00800000, 0x00000000,
6166};
6167
6168static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
6169 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000,
6170};
6171
6172static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask[] = {
6173 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x00000000,
6174};
6175
6176static const uint32_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask[] = {
6177 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000,
6178};
6179
6180static const uint32_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask[] = {
6181 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000,
6182};
6183
6184static const uint32_t RSTSubClassMask[] = {
6185 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00000000,
6186};
6187
6188static const uint32_t RFP80SubClassMask[] = {
6189 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000,
6190};
6191
6192static const uint32_t RFP80_7SubClassMask[] = {
6193 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00000000,
6194};
6195
6196static const uint32_t VR128XSubClassMask[] = {
6197 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00000001,
6198 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000001e, // sub_xmm
6199};
6200
6201static const uint32_t VR128SubClassMask[] = {
6202 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
6203 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000014, // sub_xmm
6204};
6205
6206static const uint32_t VR256XSubClassMask[] = {
6207 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000006,
6208 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000018, // sub_ymm
6209};
6210
6211static const uint32_t VR256SubClassMask[] = {
6212 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000004,
6213 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000010, // sub_ymm
6214};
6215
6216static const uint32_t VR512SubClassMask[] = {
6217 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000018,
6218};
6219
6220static const uint32_t VR512_0_15SubClassMask[] = {
6221 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000010,
6222};
6223
6224static const uint32_t TILESubClassMask[] = {
6225 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020,
6226};
6227
6228static const uint16_t SuperRegIdxSeqs[] = {
6229 /* 0 */ 1, 0,
6230 /* 2 */ 1, 2, 0,
6231 /* 5 */ 4, 0,
6232 /* 7 */ 6, 0,
6233 /* 9 */ 7, 8, 0,
6234 /* 12 */ 9, 0,
6235 /* 14 */ 10, 0,
6236};
6237
6238static const TargetRegisterClass *const GR8_NOREX2Superclasses[] = {
6239 &X86::GR8RegClass,
6240 nullptr
6241};
6242
6243static const TargetRegisterClass *const GR8_NOREXSuperclasses[] = {
6244 &X86::GR8RegClass,
6245 &X86::GR8_NOREX2RegClass,
6246 nullptr
6247};
6248
6249static const TargetRegisterClass *const GR8_ABCD_HSuperclasses[] = {
6250 &X86::GR8RegClass,
6251 &X86::GR8_NOREX2RegClass,
6252 &X86::GR8_NOREXRegClass,
6253 nullptr
6254};
6255
6256static const TargetRegisterClass *const GR8_ABCD_LSuperclasses[] = {
6257 &X86::GR8RegClass,
6258 &X86::GR8_NOREX2RegClass,
6259 &X86::GR8_NOREXRegClass,
6260 nullptr
6261};
6262
6263static const TargetRegisterClass *const GR16_NOREX2Superclasses[] = {
6264 &X86::GR16RegClass,
6265 nullptr
6266};
6267
6268static const TargetRegisterClass *const GR16_NOREXSuperclasses[] = {
6269 &X86::GR16RegClass,
6270 &X86::GR16_NOREX2RegClass,
6271 nullptr
6272};
6273
6274static const TargetRegisterClass *const VK1Superclasses[] = {
6275 &X86::VK16RegClass,
6276 &X86::VK2RegClass,
6277 &X86::VK4RegClass,
6278 &X86::VK8RegClass,
6279 nullptr
6280};
6281
6282static const TargetRegisterClass *const VK16Superclasses[] = {
6283 &X86::VK1RegClass,
6284 &X86::VK2RegClass,
6285 &X86::VK4RegClass,
6286 &X86::VK8RegClass,
6287 nullptr
6288};
6289
6290static const TargetRegisterClass *const VK2Superclasses[] = {
6291 &X86::VK1RegClass,
6292 &X86::VK16RegClass,
6293 &X86::VK4RegClass,
6294 &X86::VK8RegClass,
6295 nullptr
6296};
6297
6298static const TargetRegisterClass *const VK4Superclasses[] = {
6299 &X86::VK1RegClass,
6300 &X86::VK16RegClass,
6301 &X86::VK2RegClass,
6302 &X86::VK8RegClass,
6303 nullptr
6304};
6305
6306static const TargetRegisterClass *const VK8Superclasses[] = {
6307 &X86::VK1RegClass,
6308 &X86::VK16RegClass,
6309 &X86::VK2RegClass,
6310 &X86::VK4RegClass,
6311 nullptr
6312};
6313
6314static const TargetRegisterClass *const VK16WMSuperclasses[] = {
6315 &X86::VK1RegClass,
6316 &X86::VK16RegClass,
6317 &X86::VK2RegClass,
6318 &X86::VK4RegClass,
6319 &X86::VK8RegClass,
6320 &X86::VK1WMRegClass,
6321 &X86::VK2WMRegClass,
6322 &X86::VK4WMRegClass,
6323 &X86::VK8WMRegClass,
6324 nullptr
6325};
6326
6327static const TargetRegisterClass *const VK1WMSuperclasses[] = {
6328 &X86::VK1RegClass,
6329 &X86::VK16RegClass,
6330 &X86::VK2RegClass,
6331 &X86::VK4RegClass,
6332 &X86::VK8RegClass,
6333 &X86::VK16WMRegClass,
6334 &X86::VK2WMRegClass,
6335 &X86::VK4WMRegClass,
6336 &X86::VK8WMRegClass,
6337 nullptr
6338};
6339
6340static const TargetRegisterClass *const VK2WMSuperclasses[] = {
6341 &X86::VK1RegClass,
6342 &X86::VK16RegClass,
6343 &X86::VK2RegClass,
6344 &X86::VK4RegClass,
6345 &X86::VK8RegClass,
6346 &X86::VK16WMRegClass,
6347 &X86::VK1WMRegClass,
6348 &X86::VK4WMRegClass,
6349 &X86::VK8WMRegClass,
6350 nullptr
6351};
6352
6353static const TargetRegisterClass *const VK4WMSuperclasses[] = {
6354 &X86::VK1RegClass,
6355 &X86::VK16RegClass,
6356 &X86::VK2RegClass,
6357 &X86::VK4RegClass,
6358 &X86::VK8RegClass,
6359 &X86::VK16WMRegClass,
6360 &X86::VK1WMRegClass,
6361 &X86::VK2WMRegClass,
6362 &X86::VK8WMRegClass,
6363 nullptr
6364};
6365
6366static const TargetRegisterClass *const VK8WMSuperclasses[] = {
6367 &X86::VK1RegClass,
6368 &X86::VK16RegClass,
6369 &X86::VK2RegClass,
6370 &X86::VK4RegClass,
6371 &X86::VK8RegClass,
6372 &X86::VK16WMRegClass,
6373 &X86::VK1WMRegClass,
6374 &X86::VK2WMRegClass,
6375 &X86::VK4WMRegClass,
6376 nullptr
6377};
6378
6379static const TargetRegisterClass *const GR16_ABCDSuperclasses[] = {
6380 &X86::GR16RegClass,
6381 &X86::GR16_NOREX2RegClass,
6382 &X86::GR16_NOREXRegClass,
6383 nullptr
6384};
6385
6386static const TargetRegisterClass *const FR16Superclasses[] = {
6387 &X86::FR16XRegClass,
6388 nullptr
6389};
6390
6391static const TargetRegisterClass *const VK16PAIRSuperclasses[] = {
6392 &X86::VK1PAIRRegClass,
6393 &X86::VK2PAIRRegClass,
6394 &X86::VK4PAIRRegClass,
6395 &X86::VK8PAIRRegClass,
6396 nullptr
6397};
6398
6399static const TargetRegisterClass *const VK1PAIRSuperclasses[] = {
6400 &X86::VK16PAIRRegClass,
6401 &X86::VK2PAIRRegClass,
6402 &X86::VK4PAIRRegClass,
6403 &X86::VK8PAIRRegClass,
6404 nullptr
6405};
6406
6407static const TargetRegisterClass *const VK2PAIRSuperclasses[] = {
6408 &X86::VK16PAIRRegClass,
6409 &X86::VK1PAIRRegClass,
6410 &X86::VK4PAIRRegClass,
6411 &X86::VK8PAIRRegClass,
6412 nullptr
6413};
6414
6415static const TargetRegisterClass *const VK4PAIRSuperclasses[] = {
6416 &X86::VK16PAIRRegClass,
6417 &X86::VK1PAIRRegClass,
6418 &X86::VK2PAIRRegClass,
6419 &X86::VK8PAIRRegClass,
6420 nullptr
6421};
6422
6423static const TargetRegisterClass *const VK8PAIRSuperclasses[] = {
6424 &X86::VK16PAIRRegClass,
6425 &X86::VK1PAIRRegClass,
6426 &X86::VK2PAIRRegClass,
6427 &X86::VK4PAIRRegClass,
6428 nullptr
6429};
6430
6431static const TargetRegisterClass *const VK1PAIR_with_sub_mask_0_in_VK1WMSuperclasses[] = {
6432 &X86::VK16PAIRRegClass,
6433 &X86::VK1PAIRRegClass,
6434 &X86::VK2PAIRRegClass,
6435 &X86::VK4PAIRRegClass,
6436 &X86::VK8PAIRRegClass,
6437 nullptr
6438};
6439
6440static const TargetRegisterClass *const LOW32_ADDR_ACCESSSuperclasses[] = {
6441 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6442 nullptr
6443};
6444
6445static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
6446 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6447 nullptr
6448};
6449
6450static const TargetRegisterClass *const FR32XSuperclasses[] = {
6451 &X86::FR16XRegClass,
6452 nullptr
6453};
6454
6455static const TargetRegisterClass *const GR32Superclasses[] = {
6456 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6457 &X86::LOW32_ADDR_ACCESSRegClass,
6458 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6459 nullptr
6460};
6461
6462static const TargetRegisterClass *const GR32_NOSPSuperclasses[] = {
6463 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6464 &X86::LOW32_ADDR_ACCESSRegClass,
6465 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6466 &X86::GR32RegClass,
6467 nullptr
6468};
6469
6470static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Superclasses[] = {
6471 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6472 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6473 nullptr
6474};
6475
6476static const TargetRegisterClass *const FR32Superclasses[] = {
6477 &X86::FR16XRegClass,
6478 &X86::FR16RegClass,
6479 &X86::FR32XRegClass,
6480 nullptr
6481};
6482
6483static const TargetRegisterClass *const GR32_NOREX2Superclasses[] = {
6484 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6485 &X86::LOW32_ADDR_ACCESSRegClass,
6486 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6487 &X86::GR32RegClass,
6488 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6489 nullptr
6490};
6491
6492static const TargetRegisterClass *const GR32_NOREX2_NOSPSuperclasses[] = {
6493 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6494 &X86::LOW32_ADDR_ACCESSRegClass,
6495 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6496 &X86::GR32RegClass,
6497 &X86::GR32_NOSPRegClass,
6498 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6499 &X86::GR32_NOREX2RegClass,
6500 nullptr
6501};
6502
6503static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
6504 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6505 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6506 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6507 nullptr
6508};
6509
6510static const TargetRegisterClass *const GR32_NOREXSuperclasses[] = {
6511 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6512 &X86::LOW32_ADDR_ACCESSRegClass,
6513 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6514 &X86::GR32RegClass,
6515 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6516 &X86::GR32_NOREX2RegClass,
6517 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6518 nullptr
6519};
6520
6521static const TargetRegisterClass *const VK32Superclasses[] = {
6522 &X86::VK1RegClass,
6523 &X86::VK16RegClass,
6524 &X86::VK2RegClass,
6525 &X86::VK4RegClass,
6526 &X86::VK8RegClass,
6527 nullptr
6528};
6529
6530static const TargetRegisterClass *const GR32_NOREX_NOSPSuperclasses[] = {
6531 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6532 &X86::LOW32_ADDR_ACCESSRegClass,
6533 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6534 &X86::GR32RegClass,
6535 &X86::GR32_NOSPRegClass,
6536 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6537 &X86::GR32_NOREX2RegClass,
6538 &X86::GR32_NOREX2_NOSPRegClass,
6539 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6540 &X86::GR32_NOREXRegClass,
6541 nullptr
6542};
6543
6544static const TargetRegisterClass *const VK32WMSuperclasses[] = {
6545 &X86::VK1RegClass,
6546 &X86::VK16RegClass,
6547 &X86::VK2RegClass,
6548 &X86::VK4RegClass,
6549 &X86::VK8RegClass,
6550 &X86::VK16WMRegClass,
6551 &X86::VK1WMRegClass,
6552 &X86::VK2WMRegClass,
6553 &X86::VK4WMRegClass,
6554 &X86::VK8WMRegClass,
6555 &X86::VK32RegClass,
6556 nullptr
6557};
6558
6559static const TargetRegisterClass *const GR32_ABCDSuperclasses[] = {
6560 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6561 &X86::LOW32_ADDR_ACCESSRegClass,
6562 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6563 &X86::GR32RegClass,
6564 &X86::GR32_NOSPRegClass,
6565 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6566 &X86::GR32_NOREX2RegClass,
6567 &X86::GR32_NOREX2_NOSPRegClass,
6568 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6569 &X86::GR32_NOREXRegClass,
6570 &X86::GR32_NOREX_NOSPRegClass,
6571 nullptr
6572};
6573
6574static const TargetRegisterClass *const GR32_TCSuperclasses[] = {
6575 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6576 &X86::LOW32_ADDR_ACCESSRegClass,
6577 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6578 &X86::GR32RegClass,
6579 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6580 &X86::GR32_NOREX2RegClass,
6581 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6582 &X86::GR32_NOREXRegClass,
6583 nullptr
6584};
6585
6586static const TargetRegisterClass *const GR32_ABCD_and_GR32_TCSuperclasses[] = {
6587 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6588 &X86::LOW32_ADDR_ACCESSRegClass,
6589 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6590 &X86::GR32RegClass,
6591 &X86::GR32_NOSPRegClass,
6592 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6593 &X86::GR32_NOREX2RegClass,
6594 &X86::GR32_NOREX2_NOSPRegClass,
6595 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6596 &X86::GR32_NOREXRegClass,
6597 &X86::GR32_NOREX_NOSPRegClass,
6598 &X86::GR32_ABCDRegClass,
6599 &X86::GR32_TCRegClass,
6600 nullptr
6601};
6602
6603static const TargetRegisterClass *const GR32_ADSuperclasses[] = {
6604 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6605 &X86::LOW32_ADDR_ACCESSRegClass,
6606 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6607 &X86::GR32RegClass,
6608 &X86::GR32_NOSPRegClass,
6609 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6610 &X86::GR32_NOREX2RegClass,
6611 &X86::GR32_NOREX2_NOSPRegClass,
6612 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6613 &X86::GR32_NOREXRegClass,
6614 &X86::GR32_NOREX_NOSPRegClass,
6615 &X86::GR32_ABCDRegClass,
6616 &X86::GR32_TCRegClass,
6617 &X86::GR32_ABCD_and_GR32_TCRegClass,
6618 nullptr
6619};
6620
6621static const TargetRegisterClass *const GR32_ArgRefSuperclasses[] = {
6622 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6623 &X86::LOW32_ADDR_ACCESSRegClass,
6624 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6625 &X86::GR32RegClass,
6626 &X86::GR32_NOSPRegClass,
6627 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6628 &X86::GR32_NOREX2RegClass,
6629 &X86::GR32_NOREX2_NOSPRegClass,
6630 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6631 &X86::GR32_NOREXRegClass,
6632 &X86::GR32_NOREX_NOSPRegClass,
6633 &X86::GR32_ABCDRegClass,
6634 &X86::GR32_TCRegClass,
6635 &X86::GR32_ABCD_and_GR32_TCRegClass,
6636 nullptr
6637};
6638
6639static const TargetRegisterClass *const GR32_BPSPSuperclasses[] = {
6640 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6641 &X86::LOW32_ADDR_ACCESSRegClass,
6642 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6643 &X86::GR32RegClass,
6644 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6645 &X86::GR32_NOREX2RegClass,
6646 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6647 &X86::GR32_NOREXRegClass,
6648 nullptr
6649};
6650
6651static const TargetRegisterClass *const GR32_BSISuperclasses[] = {
6652 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6653 &X86::LOW32_ADDR_ACCESSRegClass,
6654 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6655 &X86::GR32RegClass,
6656 &X86::GR32_NOSPRegClass,
6657 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6658 &X86::GR32_NOREX2RegClass,
6659 &X86::GR32_NOREX2_NOSPRegClass,
6660 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6661 &X86::GR32_NOREXRegClass,
6662 &X86::GR32_NOREX_NOSPRegClass,
6663 nullptr
6664};
6665
6666static const TargetRegisterClass *const GR32_CBSuperclasses[] = {
6667 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6668 &X86::LOW32_ADDR_ACCESSRegClass,
6669 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6670 &X86::GR32RegClass,
6671 &X86::GR32_NOSPRegClass,
6672 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6673 &X86::GR32_NOREX2RegClass,
6674 &X86::GR32_NOREX2_NOSPRegClass,
6675 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6676 &X86::GR32_NOREXRegClass,
6677 &X86::GR32_NOREX_NOSPRegClass,
6678 &X86::GR32_ABCDRegClass,
6679 nullptr
6680};
6681
6682static const TargetRegisterClass *const GR32_DCSuperclasses[] = {
6683 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6684 &X86::LOW32_ADDR_ACCESSRegClass,
6685 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6686 &X86::GR32RegClass,
6687 &X86::GR32_NOSPRegClass,
6688 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6689 &X86::GR32_NOREX2RegClass,
6690 &X86::GR32_NOREX2_NOSPRegClass,
6691 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6692 &X86::GR32_NOREXRegClass,
6693 &X86::GR32_NOREX_NOSPRegClass,
6694 &X86::GR32_ABCDRegClass,
6695 &X86::GR32_TCRegClass,
6696 &X86::GR32_ABCD_and_GR32_TCRegClass,
6697 &X86::GR32_ArgRefRegClass,
6698 nullptr
6699};
6700
6701static const TargetRegisterClass *const GR32_DIBPSuperclasses[] = {
6702 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6703 &X86::LOW32_ADDR_ACCESSRegClass,
6704 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6705 &X86::GR32RegClass,
6706 &X86::GR32_NOSPRegClass,
6707 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6708 &X86::GR32_NOREX2RegClass,
6709 &X86::GR32_NOREX2_NOSPRegClass,
6710 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6711 &X86::GR32_NOREXRegClass,
6712 &X86::GR32_NOREX_NOSPRegClass,
6713 nullptr
6714};
6715
6716static const TargetRegisterClass *const GR32_SIDISuperclasses[] = {
6717 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6718 &X86::LOW32_ADDR_ACCESSRegClass,
6719 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6720 &X86::GR32RegClass,
6721 &X86::GR32_NOSPRegClass,
6722 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6723 &X86::GR32_NOREX2RegClass,
6724 &X86::GR32_NOREX2_NOSPRegClass,
6725 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6726 &X86::GR32_NOREXRegClass,
6727 &X86::GR32_NOREX_NOSPRegClass,
6728 nullptr
6729};
6730
6731static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
6732 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6733 nullptr
6734};
6735
6736static const TargetRegisterClass *const GR32_ABCD_and_GR32_BSISuperclasses[] = {
6737 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6738 &X86::LOW32_ADDR_ACCESSRegClass,
6739 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6740 &X86::GR32RegClass,
6741 &X86::GR32_NOSPRegClass,
6742 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6743 &X86::GR32_NOREX2RegClass,
6744 &X86::GR32_NOREX2_NOSPRegClass,
6745 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6746 &X86::GR32_NOREXRegClass,
6747 &X86::GR32_NOREX_NOSPRegClass,
6748 &X86::GR32_ABCDRegClass,
6749 &X86::GR32_BSIRegClass,
6750 &X86::GR32_CBRegClass,
6751 nullptr
6752};
6753
6754static const TargetRegisterClass *const GR32_AD_and_GR32_ArgRefSuperclasses[] = {
6755 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6756 &X86::LOW32_ADDR_ACCESSRegClass,
6757 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6758 &X86::GR32RegClass,
6759 &X86::GR32_NOSPRegClass,
6760 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6761 &X86::GR32_NOREX2RegClass,
6762 &X86::GR32_NOREX2_NOSPRegClass,
6763 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6764 &X86::GR32_NOREXRegClass,
6765 &X86::GR32_NOREX_NOSPRegClass,
6766 &X86::GR32_ABCDRegClass,
6767 &X86::GR32_TCRegClass,
6768 &X86::GR32_ABCD_and_GR32_TCRegClass,
6769 &X86::GR32_ADRegClass,
6770 &X86::GR32_ArgRefRegClass,
6771 &X86::GR32_DCRegClass,
6772 nullptr
6773};
6774
6775static const TargetRegisterClass *const GR32_ArgRef_and_GR32_CBSuperclasses[] = {
6776 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6777 &X86::LOW32_ADDR_ACCESSRegClass,
6778 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6779 &X86::GR32RegClass,
6780 &X86::GR32_NOSPRegClass,
6781 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6782 &X86::GR32_NOREX2RegClass,
6783 &X86::GR32_NOREX2_NOSPRegClass,
6784 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6785 &X86::GR32_NOREXRegClass,
6786 &X86::GR32_NOREX_NOSPRegClass,
6787 &X86::GR32_ABCDRegClass,
6788 &X86::GR32_TCRegClass,
6789 &X86::GR32_ABCD_and_GR32_TCRegClass,
6790 &X86::GR32_ArgRefRegClass,
6791 &X86::GR32_CBRegClass,
6792 &X86::GR32_DCRegClass,
6793 nullptr
6794};
6795
6796static const TargetRegisterClass *const GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
6797 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6798 &X86::LOW32_ADDR_ACCESSRegClass,
6799 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6800 &X86::GR32RegClass,
6801 &X86::GR32_NOSPRegClass,
6802 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6803 &X86::GR32_NOREX2RegClass,
6804 &X86::GR32_NOREX2_NOSPRegClass,
6805 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6806 &X86::GR32_NOREXRegClass,
6807 &X86::GR32_NOREX_NOSPRegClass,
6808 &X86::GR32_BPSPRegClass,
6809 &X86::GR32_DIBPRegClass,
6810 nullptr
6811};
6812
6813static const TargetRegisterClass *const GR32_BPSP_and_GR32_TCSuperclasses[] = {
6814 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6815 &X86::LOW32_ADDR_ACCESSRegClass,
6816 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6817 &X86::GR32RegClass,
6818 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6819 &X86::GR32_NOREX2RegClass,
6820 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6821 &X86::GR32_NOREXRegClass,
6822 &X86::GR32_TCRegClass,
6823 &X86::GR32_BPSPRegClass,
6824 nullptr
6825};
6826
6827static const TargetRegisterClass *const GR32_BSI_and_GR32_SIDISuperclasses[] = {
6828 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6829 &X86::LOW32_ADDR_ACCESSRegClass,
6830 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6831 &X86::GR32RegClass,
6832 &X86::GR32_NOSPRegClass,
6833 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6834 &X86::GR32_NOREX2RegClass,
6835 &X86::GR32_NOREX2_NOSPRegClass,
6836 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6837 &X86::GR32_NOREXRegClass,
6838 &X86::GR32_NOREX_NOSPRegClass,
6839 &X86::GR32_BSIRegClass,
6840 &X86::GR32_SIDIRegClass,
6841 nullptr
6842};
6843
6844static const TargetRegisterClass *const GR32_DIBP_and_GR32_SIDISuperclasses[] = {
6845 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6846 &X86::LOW32_ADDR_ACCESSRegClass,
6847 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6848 &X86::GR32RegClass,
6849 &X86::GR32_NOSPRegClass,
6850 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6851 &X86::GR32_NOREX2RegClass,
6852 &X86::GR32_NOREX2_NOSPRegClass,
6853 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6854 &X86::GR32_NOREXRegClass,
6855 &X86::GR32_NOREX_NOSPRegClass,
6856 &X86::GR32_DIBPRegClass,
6857 &X86::GR32_SIDIRegClass,
6858 nullptr
6859};
6860
6861static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
6862 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6863 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
6864 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
6865 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
6866 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
6867 nullptr
6868};
6869
6870static const TargetRegisterClass *const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
6871 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
6872 &X86::LOW32_ADDR_ACCESSRegClass,
6873 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
6874 nullptr
6875};
6876
6877static const TargetRegisterClass *const RFP64Superclasses[] = {
6878 &X86::RFP32RegClass,
6879 nullptr
6880};
6881
6882static const TargetRegisterClass *const FR64XSuperclasses[] = {
6883 &X86::FR16XRegClass,
6884 &X86::FR32XRegClass,
6885 nullptr
6886};
6887
6888static const TargetRegisterClass *const GR64_with_sub_8bitSuperclasses[] = {
6889 &X86::GR64RegClass,
6890 nullptr
6891};
6892
6893static const TargetRegisterClass *const GR64_NOSPSuperclasses[] = {
6894 &X86::GR64RegClass,
6895 &X86::GR64_with_sub_8bitRegClass,
6896 nullptr
6897};
6898
6899static const TargetRegisterClass *const GR64_NOREX2Superclasses[] = {
6900 &X86::GR64RegClass,
6901 nullptr
6902};
6903
6904static const TargetRegisterClass *const FR64Superclasses[] = {
6905 &X86::FR16XRegClass,
6906 &X86::FR16RegClass,
6907 &X86::FR32XRegClass,
6908 &X86::FR32RegClass,
6909 &X86::FR64XRegClass,
6910 nullptr
6911};
6912
6913static const TargetRegisterClass *const GR64_with_sub_16bit_in_GR16_NOREX2Superclasses[] = {
6914 &X86::GR64RegClass,
6915 &X86::GR64_with_sub_8bitRegClass,
6916 &X86::GR64_NOREX2RegClass,
6917 nullptr
6918};
6919
6920static const TargetRegisterClass *const GR64_NOREX2_NOSPSuperclasses[] = {
6921 &X86::GR64RegClass,
6922 &X86::GR64_with_sub_8bitRegClass,
6923 &X86::GR64_NOSPRegClass,
6924 &X86::GR64_NOREX2RegClass,
6925 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
6926 nullptr
6927};
6928
6929static const TargetRegisterClass *const GR64PLTSafeSuperclasses[] = {
6930 &X86::GR64RegClass,
6931 &X86::GR64_with_sub_8bitRegClass,
6932 &X86::GR64_NOSPRegClass,
6933 &X86::GR64_NOREX2RegClass,
6934 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
6935 &X86::GR64_NOREX2_NOSPRegClass,
6936 nullptr
6937};
6938
6939static const TargetRegisterClass *const GR64_TCSuperclasses[] = {
6940 &X86::GR64RegClass,
6941 &X86::GR64_NOREX2RegClass,
6942 nullptr
6943};
6944
6945static const TargetRegisterClass *const GR64_NOREXSuperclasses[] = {
6946 &X86::GR64RegClass,
6947 &X86::GR64_NOREX2RegClass,
6948 nullptr
6949};
6950
6951static const TargetRegisterClass *const GR64_TCW64Superclasses[] = {
6952 &X86::GR64RegClass,
6953 &X86::GR64_NOREX2RegClass,
6954 nullptr
6955};
6956
6957static const TargetRegisterClass *const GR64_TC_with_sub_8bitSuperclasses[] = {
6958 &X86::GR64RegClass,
6959 &X86::GR64_with_sub_8bitRegClass,
6960 &X86::GR64_NOREX2RegClass,
6961 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
6962 &X86::GR64_TCRegClass,
6963 nullptr
6964};
6965
6966static const TargetRegisterClass *const GR64_NOREX2_NOSP_and_GR64_TCSuperclasses[] = {
6967 &X86::GR64RegClass,
6968 &X86::GR64_with_sub_8bitRegClass,
6969 &X86::GR64_NOSPRegClass,
6970 &X86::GR64_NOREX2RegClass,
6971 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
6972 &X86::GR64_NOREX2_NOSPRegClass,
6973 &X86::GR64_TCRegClass,
6974 &X86::GR64_TC_with_sub_8bitRegClass,
6975 nullptr
6976};
6977
6978static const TargetRegisterClass *const GR64_TCW64_with_sub_8bitSuperclasses[] = {
6979 &X86::GR64RegClass,
6980 &X86::GR64_with_sub_8bitRegClass,
6981 &X86::GR64_NOREX2RegClass,
6982 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
6983 &X86::GR64_TCW64RegClass,
6984 nullptr
6985};
6986
6987static const TargetRegisterClass *const GR64_TC_and_GR64_TCW64Superclasses[] = {
6988 &X86::GR64RegClass,
6989 &X86::GR64_NOREX2RegClass,
6990 &X86::GR64_TCRegClass,
6991 &X86::GR64_TCW64RegClass,
6992 nullptr
6993};
6994
6995static const TargetRegisterClass *const GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
6996 &X86::GR64RegClass,
6997 &X86::GR64_with_sub_8bitRegClass,
6998 &X86::GR64_NOREX2RegClass,
6999 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7000 &X86::GR64_NOREXRegClass,
7001 nullptr
7002};
7003
7004static const TargetRegisterClass *const VK64Superclasses[] = {
7005 &X86::VK1RegClass,
7006 &X86::VK16RegClass,
7007 &X86::VK2RegClass,
7008 &X86::VK4RegClass,
7009 &X86::VK8RegClass,
7010 &X86::VK32RegClass,
7011 nullptr
7012};
7013
7014static const TargetRegisterClass *const GR64PLTSafe_and_GR64_TCSuperclasses[] = {
7015 &X86::GR64RegClass,
7016 &X86::GR64_with_sub_8bitRegClass,
7017 &X86::GR64_NOSPRegClass,
7018 &X86::GR64_NOREX2RegClass,
7019 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7020 &X86::GR64_NOREX2_NOSPRegClass,
7021 &X86::GR64PLTSafeRegClass,
7022 &X86::GR64_TCRegClass,
7023 &X86::GR64_TC_with_sub_8bitRegClass,
7024 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
7025 nullptr
7026};
7027
7028static const TargetRegisterClass *const GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses[] = {
7029 &X86::GR64RegClass,
7030 &X86::GR64_with_sub_8bitRegClass,
7031 &X86::GR64_NOSPRegClass,
7032 &X86::GR64_NOREX2RegClass,
7033 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7034 &X86::GR64_NOREX2_NOSPRegClass,
7035 &X86::GR64_TCW64RegClass,
7036 &X86::GR64_TCW64_with_sub_8bitRegClass,
7037 nullptr
7038};
7039
7040static const TargetRegisterClass *const GR64_NOREX_NOSPSuperclasses[] = {
7041 &X86::GR64RegClass,
7042 &X86::GR64_with_sub_8bitRegClass,
7043 &X86::GR64_NOSPRegClass,
7044 &X86::GR64_NOREX2RegClass,
7045 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7046 &X86::GR64_NOREX2_NOSPRegClass,
7047 &X86::GR64PLTSafeRegClass,
7048 &X86::GR64_NOREXRegClass,
7049 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7050 nullptr
7051};
7052
7053static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCSuperclasses[] = {
7054 &X86::GR64RegClass,
7055 &X86::GR64_NOREX2RegClass,
7056 &X86::GR64_TCRegClass,
7057 &X86::GR64_NOREXRegClass,
7058 nullptr
7059};
7060
7061static const TargetRegisterClass *const GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses[] = {
7062 &X86::GR64RegClass,
7063 &X86::GR64_with_sub_8bitRegClass,
7064 &X86::GR64_NOREX2RegClass,
7065 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7066 &X86::GR64_TCRegClass,
7067 &X86::GR64_TCW64RegClass,
7068 &X86::GR64_TC_with_sub_8bitRegClass,
7069 &X86::GR64_TCW64_with_sub_8bitRegClass,
7070 &X86::GR64_TC_and_GR64_TCW64RegClass,
7071 nullptr
7072};
7073
7074static const TargetRegisterClass *const VK64WMSuperclasses[] = {
7075 &X86::VK1RegClass,
7076 &X86::VK16RegClass,
7077 &X86::VK2RegClass,
7078 &X86::VK4RegClass,
7079 &X86::VK8RegClass,
7080 &X86::VK16WMRegClass,
7081 &X86::VK1WMRegClass,
7082 &X86::VK2WMRegClass,
7083 &X86::VK4WMRegClass,
7084 &X86::VK8WMRegClass,
7085 &X86::VK32RegClass,
7086 &X86::VK32WMRegClass,
7087 &X86::VK64RegClass,
7088 nullptr
7089};
7090
7091static const TargetRegisterClass *const GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses[] = {
7092 &X86::GR64RegClass,
7093 &X86::GR64_with_sub_8bitRegClass,
7094 &X86::GR64_NOSPRegClass,
7095 &X86::GR64_NOREX2RegClass,
7096 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7097 &X86::GR64_NOREX2_NOSPRegClass,
7098 &X86::GR64_TCRegClass,
7099 &X86::GR64_TCW64RegClass,
7100 &X86::GR64_TC_with_sub_8bitRegClass,
7101 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
7102 &X86::GR64_TCW64_with_sub_8bitRegClass,
7103 &X86::GR64_TC_and_GR64_TCW64RegClass,
7104 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7105 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
7106 nullptr
7107};
7108
7109static const TargetRegisterClass *const GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
7110 &X86::GR64RegClass,
7111 &X86::GR64_with_sub_8bitRegClass,
7112 &X86::GR64_NOREX2RegClass,
7113 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7114 &X86::GR64_TCRegClass,
7115 &X86::GR64_NOREXRegClass,
7116 &X86::GR64_TC_with_sub_8bitRegClass,
7117 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7118 &X86::GR64_NOREX_and_GR64_TCRegClass,
7119 nullptr
7120};
7121
7122static const TargetRegisterClass *const GR64PLTSafe_and_GR64_TCW64Superclasses[] = {
7123 &X86::GR64RegClass,
7124 &X86::GR64_with_sub_8bitRegClass,
7125 &X86::GR64_NOSPRegClass,
7126 &X86::GR64_NOREX2RegClass,
7127 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7128 &X86::GR64_NOREX2_NOSPRegClass,
7129 &X86::GR64PLTSafeRegClass,
7130 &X86::GR64_TCRegClass,
7131 &X86::GR64_TCW64RegClass,
7132 &X86::GR64_TC_with_sub_8bitRegClass,
7133 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
7134 &X86::GR64_TCW64_with_sub_8bitRegClass,
7135 &X86::GR64_TC_and_GR64_TCW64RegClass,
7136 &X86::GR64PLTSafe_and_GR64_TCRegClass,
7137 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7138 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
7139 &X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7140 nullptr
7141};
7142
7143static const TargetRegisterClass *const GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses[] = {
7144 &X86::GR64RegClass,
7145 &X86::GR64_with_sub_8bitRegClass,
7146 &X86::GR64_NOSPRegClass,
7147 &X86::GR64_NOREX2RegClass,
7148 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7149 &X86::GR64_NOREX2_NOSPRegClass,
7150 &X86::GR64PLTSafeRegClass,
7151 &X86::GR64_TCRegClass,
7152 &X86::GR64_NOREXRegClass,
7153 &X86::GR64_TC_with_sub_8bitRegClass,
7154 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
7155 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7156 &X86::GR64PLTSafe_and_GR64_TCRegClass,
7157 &X86::GR64_NOREX_NOSPRegClass,
7158 &X86::GR64_NOREX_and_GR64_TCRegClass,
7159 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7160 nullptr
7161};
7162
7163static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCW64Superclasses[] = {
7164 &X86::GR64RegClass,
7165 &X86::GR64_NOREX2RegClass,
7166 &X86::GR64_TCRegClass,
7167 &X86::GR64_NOREXRegClass,
7168 &X86::GR64_TCW64RegClass,
7169 &X86::GR64_TC_and_GR64_TCW64RegClass,
7170 &X86::GR64_NOREX_and_GR64_TCRegClass,
7171 nullptr
7172};
7173
7174static const TargetRegisterClass *const GR64_ABCDSuperclasses[] = {
7175 &X86::GR64RegClass,
7176 &X86::GR64_with_sub_8bitRegClass,
7177 &X86::GR64_NOSPRegClass,
7178 &X86::GR64_NOREX2RegClass,
7179 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7180 &X86::GR64_NOREX2_NOSPRegClass,
7181 &X86::GR64PLTSafeRegClass,
7182 &X86::GR64_NOREXRegClass,
7183 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7184 &X86::GR64_NOREX_NOSPRegClass,
7185 nullptr
7186};
7187
7188static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_TCSuperclasses[] = {
7189 &X86::GR64RegClass,
7190 &X86::GR64_with_sub_8bitRegClass,
7191 &X86::GR64_NOREX2RegClass,
7192 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7193 &X86::GR64_TCRegClass,
7194 &X86::GR64_NOREXRegClass,
7195 &X86::GR64_TCW64RegClass,
7196 &X86::GR64_TC_with_sub_8bitRegClass,
7197 &X86::GR64_TCW64_with_sub_8bitRegClass,
7198 &X86::GR64_TC_and_GR64_TCW64RegClass,
7199 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7200 &X86::GR64_NOREX_and_GR64_TCRegClass,
7201 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
7202 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7203 &X86::GR64_NOREX_and_GR64_TCW64RegClass,
7204 nullptr
7205};
7206
7207static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses[] = {
7208 &X86::GR64RegClass,
7209 &X86::GR64_with_sub_8bitRegClass,
7210 &X86::GR64_NOSPRegClass,
7211 &X86::GR64_NOREX2RegClass,
7212 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7213 &X86::GR64_NOREX2_NOSPRegClass,
7214 &X86::GR64PLTSafeRegClass,
7215 &X86::GR64_TCRegClass,
7216 &X86::GR64_NOREXRegClass,
7217 &X86::GR64_TCW64RegClass,
7218 &X86::GR64_TC_with_sub_8bitRegClass,
7219 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
7220 &X86::GR64_TCW64_with_sub_8bitRegClass,
7221 &X86::GR64_TC_and_GR64_TCW64RegClass,
7222 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7223 &X86::GR64PLTSafe_and_GR64_TCRegClass,
7224 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7225 &X86::GR64_NOREX_NOSPRegClass,
7226 &X86::GR64_NOREX_and_GR64_TCRegClass,
7227 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
7228 &X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7229 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7230 &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
7231 &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
7232 &X86::GR64_NOREX_and_GR64_TCW64RegClass,
7233 &X86::GR64_ABCDRegClass,
7234 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
7235 nullptr
7236};
7237
7238static const TargetRegisterClass *const GR64_ADSuperclasses[] = {
7239 &X86::GR64RegClass,
7240 &X86::GR64_with_sub_8bitRegClass,
7241 &X86::GR64_NOSPRegClass,
7242 &X86::GR64_NOREX2RegClass,
7243 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7244 &X86::GR64_NOREX2_NOSPRegClass,
7245 &X86::GR64PLTSafeRegClass,
7246 &X86::GR64_TCRegClass,
7247 &X86::GR64_NOREXRegClass,
7248 &X86::GR64_TCW64RegClass,
7249 &X86::GR64_TC_with_sub_8bitRegClass,
7250 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
7251 &X86::GR64_TCW64_with_sub_8bitRegClass,
7252 &X86::GR64_TC_and_GR64_TCW64RegClass,
7253 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7254 &X86::GR64PLTSafe_and_GR64_TCRegClass,
7255 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7256 &X86::GR64_NOREX_NOSPRegClass,
7257 &X86::GR64_NOREX_and_GR64_TCRegClass,
7258 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
7259 &X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7260 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7261 &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
7262 &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
7263 &X86::GR64_NOREX_and_GR64_TCW64RegClass,
7264 &X86::GR64_ABCDRegClass,
7265 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
7266 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
7267 nullptr
7268};
7269
7270static const TargetRegisterClass *const GR64_ArgRefSuperclasses[] = {
7271 &X86::GR64RegClass,
7272 &X86::GR64_with_sub_8bitRegClass,
7273 &X86::GR64_NOSPRegClass,
7274 &X86::GR64_NOREX2RegClass,
7275 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7276 &X86::GR64_NOREX2_NOSPRegClass,
7277 &X86::GR64_TCW64RegClass,
7278 &X86::GR64_TCW64_with_sub_8bitRegClass,
7279 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7280 nullptr
7281};
7282
7283static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = {
7284 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
7285 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
7286 &X86::GR64RegClass,
7287 &X86::GR64_NOREX2RegClass,
7288 &X86::GR64_NOREXRegClass,
7289 nullptr
7290};
7291
7292static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ArgRefSuperclasses[] = {
7293 &X86::GR64RegClass,
7294 &X86::GR64_with_sub_8bitRegClass,
7295 &X86::GR64_NOSPRegClass,
7296 &X86::GR64_NOREX2RegClass,
7297 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7298 &X86::GR64_NOREX2_NOSPRegClass,
7299 &X86::GR64PLTSafeRegClass,
7300 &X86::GR64_TCRegClass,
7301 &X86::GR64_NOREXRegClass,
7302 &X86::GR64_TCW64RegClass,
7303 &X86::GR64_TC_with_sub_8bitRegClass,
7304 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
7305 &X86::GR64_TCW64_with_sub_8bitRegClass,
7306 &X86::GR64_TC_and_GR64_TCW64RegClass,
7307 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7308 &X86::GR64PLTSafe_and_GR64_TCRegClass,
7309 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7310 &X86::GR64_NOREX_NOSPRegClass,
7311 &X86::GR64_NOREX_and_GR64_TCRegClass,
7312 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
7313 &X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7314 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7315 &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
7316 &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
7317 &X86::GR64_NOREX_and_GR64_TCW64RegClass,
7318 &X86::GR64_ABCDRegClass,
7319 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
7320 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
7321 nullptr
7322};
7323
7324static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSPSuperclasses[] = {
7325 &X86::GR64RegClass,
7326 &X86::GR64_with_sub_8bitRegClass,
7327 &X86::GR64_NOREX2RegClass,
7328 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7329 &X86::GR64_NOREXRegClass,
7330 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7331 nullptr
7332};
7333
7334static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BSISuperclasses[] = {
7335 &X86::GR64RegClass,
7336 &X86::GR64_with_sub_8bitRegClass,
7337 &X86::GR64_NOSPRegClass,
7338 &X86::GR64_NOREX2RegClass,
7339 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7340 &X86::GR64_NOREX2_NOSPRegClass,
7341 &X86::GR64PLTSafeRegClass,
7342 &X86::GR64_NOREXRegClass,
7343 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7344 &X86::GR64_NOREX_NOSPRegClass,
7345 nullptr
7346};
7347
7348static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_CBSuperclasses[] = {
7349 &X86::GR64RegClass,
7350 &X86::GR64_with_sub_8bitRegClass,
7351 &X86::GR64_NOSPRegClass,
7352 &X86::GR64_NOREX2RegClass,
7353 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7354 &X86::GR64_NOREX2_NOSPRegClass,
7355 &X86::GR64PLTSafeRegClass,
7356 &X86::GR64_NOREXRegClass,
7357 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7358 &X86::GR64_NOREX_NOSPRegClass,
7359 &X86::GR64_ABCDRegClass,
7360 nullptr
7361};
7362
7363static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DIBPSuperclasses[] = {
7364 &X86::GR64RegClass,
7365 &X86::GR64_with_sub_8bitRegClass,
7366 &X86::GR64_NOSPRegClass,
7367 &X86::GR64_NOREX2RegClass,
7368 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7369 &X86::GR64_NOREX2_NOSPRegClass,
7370 &X86::GR64PLTSafeRegClass,
7371 &X86::GR64_NOREXRegClass,
7372 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7373 &X86::GR64_NOREX_NOSPRegClass,
7374 nullptr
7375};
7376
7377static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_SIDISuperclasses[] = {
7378 &X86::GR64RegClass,
7379 &X86::GR64_with_sub_8bitRegClass,
7380 &X86::GR64_NOSPRegClass,
7381 &X86::GR64_NOREX2RegClass,
7382 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7383 &X86::GR64_NOREX2_NOSPRegClass,
7384 &X86::GR64PLTSafeRegClass,
7385 &X86::GR64_TCRegClass,
7386 &X86::GR64_NOREXRegClass,
7387 &X86::GR64_TC_with_sub_8bitRegClass,
7388 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
7389 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7390 &X86::GR64PLTSafe_and_GR64_TCRegClass,
7391 &X86::GR64_NOREX_NOSPRegClass,
7392 &X86::GR64_NOREX_and_GR64_TCRegClass,
7393 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7394 &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
7395 nullptr
7396};
7397
7398static const TargetRegisterClass *const GR64_ArgRef_and_GR64_TCSuperclasses[] = {
7399 &X86::GR64RegClass,
7400 &X86::GR64_with_sub_8bitRegClass,
7401 &X86::GR64_NOSPRegClass,
7402 &X86::GR64_NOREX2RegClass,
7403 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7404 &X86::GR64_NOREX2_NOSPRegClass,
7405 &X86::GR64_TCRegClass,
7406 &X86::GR64_TCW64RegClass,
7407 &X86::GR64_TC_with_sub_8bitRegClass,
7408 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
7409 &X86::GR64_TCW64_with_sub_8bitRegClass,
7410 &X86::GR64_TC_and_GR64_TCW64RegClass,
7411 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7412 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
7413 &X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7414 &X86::GR64_ArgRefRegClass,
7415 nullptr
7416};
7417
7418static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESSSuperclasses[] = {
7419 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
7420 &X86::LOW32_ADDR_ACCESSRegClass,
7421 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
7422 &X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
7423 &X86::GR64RegClass,
7424 &X86::GR64_NOREX2RegClass,
7425 &X86::GR64_TCRegClass,
7426 &X86::GR64_NOREXRegClass,
7427 &X86::GR64_TCW64RegClass,
7428 &X86::GR64_TC_and_GR64_TCW64RegClass,
7429 &X86::GR64_NOREX_and_GR64_TCRegClass,
7430 &X86::GR64_NOREX_and_GR64_TCW64RegClass,
7431 &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
7432 nullptr
7433};
7434
7435static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses[] = {
7436 &X86::GR64RegClass,
7437 &X86::GR64_with_sub_8bitRegClass,
7438 &X86::GR64_NOSPRegClass,
7439 &X86::GR64_NOREX2RegClass,
7440 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7441 &X86::GR64_NOREX2_NOSPRegClass,
7442 &X86::GR64PLTSafeRegClass,
7443 &X86::GR64_NOREXRegClass,
7444 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7445 &X86::GR64_NOREX_NOSPRegClass,
7446 &X86::GR64_ABCDRegClass,
7447 &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
7448 &X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
7449 nullptr
7450};
7451
7452static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSuperclasses[] = {
7453 &X86::GR64RegClass,
7454 &X86::GR64_with_sub_8bitRegClass,
7455 &X86::GR64_NOSPRegClass,
7456 &X86::GR64_NOREX2RegClass,
7457 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7458 &X86::GR64_NOREX2_NOSPRegClass,
7459 &X86::GR64PLTSafeRegClass,
7460 &X86::GR64_TCRegClass,
7461 &X86::GR64_NOREXRegClass,
7462 &X86::GR64_TCW64RegClass,
7463 &X86::GR64_TC_with_sub_8bitRegClass,
7464 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
7465 &X86::GR64_TCW64_with_sub_8bitRegClass,
7466 &X86::GR64_TC_and_GR64_TCW64RegClass,
7467 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7468 &X86::GR64PLTSafe_and_GR64_TCRegClass,
7469 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7470 &X86::GR64_NOREX_NOSPRegClass,
7471 &X86::GR64_NOREX_and_GR64_TCRegClass,
7472 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
7473 &X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7474 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7475 &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
7476 &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
7477 &X86::GR64_NOREX_and_GR64_TCW64RegClass,
7478 &X86::GR64_ABCDRegClass,
7479 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
7480 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
7481 &X86::GR64_ADRegClass,
7482 &X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClass,
7483 nullptr
7484};
7485
7486static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSuperclasses[] = {
7487 &X86::GR64RegClass,
7488 &X86::GR64_with_sub_8bitRegClass,
7489 &X86::GR64_NOSPRegClass,
7490 &X86::GR64_NOREX2RegClass,
7491 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7492 &X86::GR64_NOREX2_NOSPRegClass,
7493 &X86::GR64PLTSafeRegClass,
7494 &X86::GR64_TCRegClass,
7495 &X86::GR64_NOREXRegClass,
7496 &X86::GR64_TCW64RegClass,
7497 &X86::GR64_TC_with_sub_8bitRegClass,
7498 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
7499 &X86::GR64_TCW64_with_sub_8bitRegClass,
7500 &X86::GR64_TC_and_GR64_TCW64RegClass,
7501 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7502 &X86::GR64PLTSafe_and_GR64_TCRegClass,
7503 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7504 &X86::GR64_NOREX_NOSPRegClass,
7505 &X86::GR64_NOREX_and_GR64_TCRegClass,
7506 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
7507 &X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
7508 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7509 &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
7510 &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
7511 &X86::GR64_NOREX_and_GR64_TCW64RegClass,
7512 &X86::GR64_ABCDRegClass,
7513 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
7514 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
7515 &X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClass,
7516 &X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
7517 nullptr
7518};
7519
7520static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
7521 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
7522 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
7523 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
7524 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
7525 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
7526 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
7527 &X86::GR64RegClass,
7528 &X86::GR64_with_sub_8bitRegClass,
7529 &X86::GR64_NOSPRegClass,
7530 &X86::GR64_NOREX2RegClass,
7531 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7532 &X86::GR64_NOREX2_NOSPRegClass,
7533 &X86::GR64PLTSafeRegClass,
7534 &X86::GR64_NOREXRegClass,
7535 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7536 &X86::GR64_NOREX_NOSPRegClass,
7537 &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
7538 &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
7539 &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
7540 nullptr
7541};
7542
7543static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses[] = {
7544 &X86::GR64RegClass,
7545 &X86::GR64_with_sub_8bitRegClass,
7546 &X86::GR64_NOREX2RegClass,
7547 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7548 &X86::GR64_TCRegClass,
7549 &X86::GR64_NOREXRegClass,
7550 &X86::GR64_TCW64RegClass,
7551 &X86::GR64_TC_with_sub_8bitRegClass,
7552 &X86::GR64_TCW64_with_sub_8bitRegClass,
7553 &X86::GR64_TC_and_GR64_TCW64RegClass,
7554 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7555 &X86::GR64_NOREX_and_GR64_TCRegClass,
7556 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
7557 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7558 &X86::GR64_NOREX_and_GR64_TCW64RegClass,
7559 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
7560 &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
7561 nullptr
7562};
7563
7564static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses[] = {
7565 &X86::GR64RegClass,
7566 &X86::GR64_with_sub_8bitRegClass,
7567 &X86::GR64_NOSPRegClass,
7568 &X86::GR64_NOREX2RegClass,
7569 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7570 &X86::GR64_NOREX2_NOSPRegClass,
7571 &X86::GR64PLTSafeRegClass,
7572 &X86::GR64_TCRegClass,
7573 &X86::GR64_NOREXRegClass,
7574 &X86::GR64_TC_with_sub_8bitRegClass,
7575 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
7576 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7577 &X86::GR64PLTSafe_and_GR64_TCRegClass,
7578 &X86::GR64_NOREX_NOSPRegClass,
7579 &X86::GR64_NOREX_and_GR64_TCRegClass,
7580 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7581 &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
7582 &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
7583 &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
7584 nullptr
7585};
7586
7587static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses[] = {
7588 &X86::GR64RegClass,
7589 &X86::GR64_with_sub_8bitRegClass,
7590 &X86::GR64_NOSPRegClass,
7591 &X86::GR64_NOREX2RegClass,
7592 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
7593 &X86::GR64_NOREX2_NOSPRegClass,
7594 &X86::GR64PLTSafeRegClass,
7595 &X86::GR64_TCRegClass,
7596 &X86::GR64_NOREXRegClass,
7597 &X86::GR64_TC_with_sub_8bitRegClass,
7598 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
7599 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7600 &X86::GR64PLTSafe_and_GR64_TCRegClass,
7601 &X86::GR64_NOREX_NOSPRegClass,
7602 &X86::GR64_NOREX_and_GR64_TCRegClass,
7603 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
7604 &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
7605 &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
7606 &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
7607 nullptr
7608};
7609
7610static const TargetRegisterClass *const RFP80Superclasses[] = {
7611 &X86::RFP32RegClass,
7612 &X86::RFP64RegClass,
7613 nullptr
7614};
7615
7616static const TargetRegisterClass *const VR128XSuperclasses[] = {
7617 &X86::FR16XRegClass,
7618 &X86::FR32XRegClass,
7619 &X86::FR64XRegClass,
7620 nullptr
7621};
7622
7623static const TargetRegisterClass *const VR128Superclasses[] = {
7624 &X86::FR16XRegClass,
7625 &X86::FR16RegClass,
7626 &X86::FR32XRegClass,
7627 &X86::FR32RegClass,
7628 &X86::FR64XRegClass,
7629 &X86::FR64RegClass,
7630 &X86::VR128XRegClass,
7631 nullptr
7632};
7633
7634static const TargetRegisterClass *const VR256Superclasses[] = {
7635 &X86::VR256XRegClass,
7636 nullptr
7637};
7638
7639static const TargetRegisterClass *const VR512_0_15Superclasses[] = {
7640 &X86::VR512RegClass,
7641 nullptr
7642};
7643
7644
7645static inline unsigned GR8AltOrderSelect(const MachineFunction &MF) {
7646 return MF.getSubtarget<X86Subtarget>().is64Bit();
7647 }
7648
7649static ArrayRef<MCPhysReg> GR8GetRawAllocationOrder(const MachineFunction &MF) {
7650 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R16B, X86::R17B, X86::R18B, X86::R19B, X86::R20B, X86::R21B, X86::R22B, X86::R23B, X86::R24B, X86::R25B, X86::R26B, X86::R27B, X86::R28B, X86::R29B, X86::R30B, X86::R31B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
7651 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];
7652 const ArrayRef<MCPhysReg> Order[] = {
7653 ArrayRef(MCR.begin(), MCR.getNumRegs()),
7654 ArrayRef(AltOrder1)
7655 };
7656 const unsigned Select = GR8AltOrderSelect(MF);
7657 assert(Select < 2);
7658 return Order[Select];
7659}
7660
7661static inline unsigned GR8_NOREX2AltOrderSelect(const MachineFunction &MF) {
7662 return MF.getSubtarget<X86Subtarget>().is64Bit();
7663 }
7664
7665static ArrayRef<MCPhysReg> GR8_NOREX2GetRawAllocationOrder(const MachineFunction &MF) {
7666 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
7667 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREX2RegClassID];
7668 const ArrayRef<MCPhysReg> Order[] = {
7669 ArrayRef(MCR.begin(), MCR.getNumRegs()),
7670 ArrayRef(AltOrder1)
7671 };
7672 const unsigned Select = GR8_NOREX2AltOrderSelect(MF);
7673 assert(Select < 2);
7674 return Order[Select];
7675}
7676
7677static inline unsigned GR8_NOREXAltOrderSelect(const MachineFunction &MF) {
7678 return MF.getSubtarget<X86Subtarget>().is64Bit();
7679 }
7680
7681static ArrayRef<MCPhysReg> GR8_NOREXGetRawAllocationOrder(const MachineFunction &MF) {
7682 static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL };
7683 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID];
7684 const ArrayRef<MCPhysReg> Order[] = {
7685 ArrayRef(MCR.begin(), MCR.getNumRegs()),
7686 ArrayRef(AltOrder1)
7687 };
7688 const unsigned Select = GR8_NOREXAltOrderSelect(MF);
7689 assert(Select < 2);
7690 return Order[Select];
7691}
7692
7693namespace X86 { // Register class instances
7694 extern const TargetRegisterClass GR8RegClass = {
7695 &X86MCRegisterClasses[GR8RegClassID],
7696 GR8SubClassMask,
7697 SuperRegIdxSeqs + 2,
7698 LaneBitmask(0x0000000000000001),
7699 0,
7700 false,
7701 0x00, /* TSFlags */
7702 false, /* HasDisjunctSubRegs */
7703 false, /* CoveredBySubRegs */
7704 NullRegClasses,
7705 GR8GetRawAllocationOrder
7706 };
7707
7708 extern const TargetRegisterClass GRH8RegClass = {
7709 &X86MCRegisterClasses[GRH8RegClassID],
7710 GRH8SubClassMask,
7711 SuperRegIdxSeqs + 1,
7712 LaneBitmask(0x0000000000000001),
7713 0,
7714 false,
7715 0x00, /* TSFlags */
7716 false, /* HasDisjunctSubRegs */
7717 false, /* CoveredBySubRegs */
7718 NullRegClasses,
7719 nullptr
7720 };
7721
7722 extern const TargetRegisterClass GR8_NOREX2RegClass = {
7723 &X86MCRegisterClasses[GR8_NOREX2RegClassID],
7724 GR8_NOREX2SubClassMask,
7725 SuperRegIdxSeqs + 2,
7726 LaneBitmask(0x0000000000000001),
7727 0,
7728 false,
7729 0x00, /* TSFlags */
7730 false, /* HasDisjunctSubRegs */
7731 false, /* CoveredBySubRegs */
7732 GR8_NOREX2Superclasses,
7733 GR8_NOREX2GetRawAllocationOrder
7734 };
7735
7736 extern const TargetRegisterClass GR8_NOREXRegClass = {
7737 &X86MCRegisterClasses[GR8_NOREXRegClassID],
7738 GR8_NOREXSubClassMask,
7739 SuperRegIdxSeqs + 2,
7740 LaneBitmask(0x0000000000000001),
7741 0,
7742 false,
7743 0x00, /* TSFlags */
7744 false, /* HasDisjunctSubRegs */
7745 false, /* CoveredBySubRegs */
7746 GR8_NOREXSuperclasses,
7747 GR8_NOREXGetRawAllocationOrder
7748 };
7749
7750 extern const TargetRegisterClass GR8_ABCD_HRegClass = {
7751 &X86MCRegisterClasses[GR8_ABCD_HRegClassID],
7752 GR8_ABCD_HSubClassMask,
7753 SuperRegIdxSeqs + 3,
7754 LaneBitmask(0x0000000000000001),
7755 0,
7756 false,
7757 0x00, /* TSFlags */
7758 false, /* HasDisjunctSubRegs */
7759 false, /* CoveredBySubRegs */
7760 GR8_ABCD_HSuperclasses,
7761 nullptr
7762 };
7763
7764 extern const TargetRegisterClass GR8_ABCD_LRegClass = {
7765 &X86MCRegisterClasses[GR8_ABCD_LRegClassID],
7766 GR8_ABCD_LSubClassMask,
7767 SuperRegIdxSeqs + 0,
7768 LaneBitmask(0x0000000000000001),
7769 0,
7770 false,
7771 0x00, /* TSFlags */
7772 false, /* HasDisjunctSubRegs */
7773 false, /* CoveredBySubRegs */
7774 GR8_ABCD_LSuperclasses,
7775 nullptr
7776 };
7777
7778 extern const TargetRegisterClass GRH16RegClass = {
7779 &X86MCRegisterClasses[GRH16RegClassID],
7780 GRH16SubClassMask,
7781 SuperRegIdxSeqs + 1,
7782 LaneBitmask(0x0000000000000001),
7783 0,
7784 false,
7785 0x00, /* TSFlags */
7786 false, /* HasDisjunctSubRegs */
7787 false, /* CoveredBySubRegs */
7788 NullRegClasses,
7789 nullptr
7790 };
7791
7792 extern const TargetRegisterClass GR16RegClass = {
7793 &X86MCRegisterClasses[GR16RegClassID],
7794 GR16SubClassMask,
7795 SuperRegIdxSeqs + 5,
7796 LaneBitmask(0x0000000000000003),
7797 0,
7798 false,
7799 0x00, /* TSFlags */
7800 true, /* HasDisjunctSubRegs */
7801 true, /* CoveredBySubRegs */
7802 NullRegClasses,
7803 nullptr
7804 };
7805
7806 extern const TargetRegisterClass GR16_NOREX2RegClass = {
7807 &X86MCRegisterClasses[GR16_NOREX2RegClassID],
7808 GR16_NOREX2SubClassMask,
7809 SuperRegIdxSeqs + 5,
7810 LaneBitmask(0x0000000000000003),
7811 0,
7812 false,
7813 0x00, /* TSFlags */
7814 true, /* HasDisjunctSubRegs */
7815 true, /* CoveredBySubRegs */
7816 GR16_NOREX2Superclasses,
7817 nullptr
7818 };
7819
7820 extern const TargetRegisterClass GR16_NOREXRegClass = {
7821 &X86MCRegisterClasses[GR16_NOREXRegClassID],
7822 GR16_NOREXSubClassMask,
7823 SuperRegIdxSeqs + 5,
7824 LaneBitmask(0x0000000000000003),
7825 0,
7826 false,
7827 0x00, /* TSFlags */
7828 true, /* HasDisjunctSubRegs */
7829 true, /* CoveredBySubRegs */
7830 GR16_NOREXSuperclasses,
7831 nullptr
7832 };
7833
7834 extern const TargetRegisterClass VK1RegClass = {
7835 &X86MCRegisterClasses[VK1RegClassID],
7836 VK1SubClassMask,
7837 SuperRegIdxSeqs + 9,
7838 LaneBitmask(0x0000000000000001),
7839 0,
7840 false,
7841 0x00, /* TSFlags */
7842 false, /* HasDisjunctSubRegs */
7843 false, /* CoveredBySubRegs */
7844 VK1Superclasses,
7845 nullptr
7846 };
7847
7848 extern const TargetRegisterClass VK16RegClass = {
7849 &X86MCRegisterClasses[VK16RegClassID],
7850 VK16SubClassMask,
7851 SuperRegIdxSeqs + 9,
7852 LaneBitmask(0x0000000000000001),
7853 0,
7854 false,
7855 0x00, /* TSFlags */
7856 false, /* HasDisjunctSubRegs */
7857 false, /* CoveredBySubRegs */
7858 VK16Superclasses,
7859 nullptr
7860 };
7861
7862 extern const TargetRegisterClass VK2RegClass = {
7863 &X86MCRegisterClasses[VK2RegClassID],
7864 VK2SubClassMask,
7865 SuperRegIdxSeqs + 9,
7866 LaneBitmask(0x0000000000000001),
7867 0,
7868 false,
7869 0x00, /* TSFlags */
7870 false, /* HasDisjunctSubRegs */
7871 false, /* CoveredBySubRegs */
7872 VK2Superclasses,
7873 nullptr
7874 };
7875
7876 extern const TargetRegisterClass VK4RegClass = {
7877 &X86MCRegisterClasses[VK4RegClassID],
7878 VK4SubClassMask,
7879 SuperRegIdxSeqs + 9,
7880 LaneBitmask(0x0000000000000001),
7881 0,
7882 false,
7883 0x00, /* TSFlags */
7884 false, /* HasDisjunctSubRegs */
7885 false, /* CoveredBySubRegs */
7886 VK4Superclasses,
7887 nullptr
7888 };
7889
7890 extern const TargetRegisterClass VK8RegClass = {
7891 &X86MCRegisterClasses[VK8RegClassID],
7892 VK8SubClassMask,
7893 SuperRegIdxSeqs + 9,
7894 LaneBitmask(0x0000000000000001),
7895 0,
7896 false,
7897 0x00, /* TSFlags */
7898 false, /* HasDisjunctSubRegs */
7899 false, /* CoveredBySubRegs */
7900 VK8Superclasses,
7901 nullptr
7902 };
7903
7904 extern const TargetRegisterClass VK16WMRegClass = {
7905 &X86MCRegisterClasses[VK16WMRegClassID],
7906 VK16WMSubClassMask,
7907 SuperRegIdxSeqs + 9,
7908 LaneBitmask(0x0000000000000001),
7909 0,
7910 false,
7911 0x00, /* TSFlags */
7912 false, /* HasDisjunctSubRegs */
7913 false, /* CoveredBySubRegs */
7914 VK16WMSuperclasses,
7915 nullptr
7916 };
7917
7918 extern const TargetRegisterClass VK1WMRegClass = {
7919 &X86MCRegisterClasses[VK1WMRegClassID],
7920 VK1WMSubClassMask,
7921 SuperRegIdxSeqs + 9,
7922 LaneBitmask(0x0000000000000001),
7923 0,
7924 false,
7925 0x00, /* TSFlags */
7926 false, /* HasDisjunctSubRegs */
7927 false, /* CoveredBySubRegs */
7928 VK1WMSuperclasses,
7929 nullptr
7930 };
7931
7932 extern const TargetRegisterClass VK2WMRegClass = {
7933 &X86MCRegisterClasses[VK2WMRegClassID],
7934 VK2WMSubClassMask,
7935 SuperRegIdxSeqs + 9,
7936 LaneBitmask(0x0000000000000001),
7937 0,
7938 false,
7939 0x00, /* TSFlags */
7940 false, /* HasDisjunctSubRegs */
7941 false, /* CoveredBySubRegs */
7942 VK2WMSuperclasses,
7943 nullptr
7944 };
7945
7946 extern const TargetRegisterClass VK4WMRegClass = {
7947 &X86MCRegisterClasses[VK4WMRegClassID],
7948 VK4WMSubClassMask,
7949 SuperRegIdxSeqs + 9,
7950 LaneBitmask(0x0000000000000001),
7951 0,
7952 false,
7953 0x00, /* TSFlags */
7954 false, /* HasDisjunctSubRegs */
7955 false, /* CoveredBySubRegs */
7956 VK4WMSuperclasses,
7957 nullptr
7958 };
7959
7960 extern const TargetRegisterClass VK8WMRegClass = {
7961 &X86MCRegisterClasses[VK8WMRegClassID],
7962 VK8WMSubClassMask,
7963 SuperRegIdxSeqs + 9,
7964 LaneBitmask(0x0000000000000001),
7965 0,
7966 false,
7967 0x00, /* TSFlags */
7968 false, /* HasDisjunctSubRegs */
7969 false, /* CoveredBySubRegs */
7970 VK8WMSuperclasses,
7971 nullptr
7972 };
7973
7974 extern const TargetRegisterClass SEGMENT_REGRegClass = {
7975 &X86MCRegisterClasses[SEGMENT_REGRegClassID],
7976 SEGMENT_REGSubClassMask,
7977 SuperRegIdxSeqs + 1,
7978 LaneBitmask(0x0000000000000001),
7979 0,
7980 false,
7981 0x00, /* TSFlags */
7982 false, /* HasDisjunctSubRegs */
7983 false, /* CoveredBySubRegs */
7984 NullRegClasses,
7985 nullptr
7986 };
7987
7988 extern const TargetRegisterClass GR16_ABCDRegClass = {
7989 &X86MCRegisterClasses[GR16_ABCDRegClassID],
7990 GR16_ABCDSubClassMask,
7991 SuperRegIdxSeqs + 5,
7992 LaneBitmask(0x0000000000000003),
7993 0,
7994 false,
7995 0x00, /* TSFlags */
7996 true, /* HasDisjunctSubRegs */
7997 true, /* CoveredBySubRegs */
7998 GR16_ABCDSuperclasses,
7999 nullptr
8000 };
8001
8002 extern const TargetRegisterClass FPCCRRegClass = {
8003 &X86MCRegisterClasses[FPCCRRegClassID],
8004 FPCCRSubClassMask,
8005 SuperRegIdxSeqs + 1,
8006 LaneBitmask(0x0000000000000001),
8007 0,
8008 false,
8009 0x00, /* TSFlags */
8010 false, /* HasDisjunctSubRegs */
8011 false, /* CoveredBySubRegs */
8012 NullRegClasses,
8013 nullptr
8014 };
8015
8016 extern const TargetRegisterClass FR16XRegClass = {
8017 &X86MCRegisterClasses[FR16XRegClassID],
8018 FR16XSubClassMask,
8019 SuperRegIdxSeqs + 12,
8020 LaneBitmask(0x0000000000000001),
8021 0,
8022 false,
8023 0x00, /* TSFlags */
8024 false, /* HasDisjunctSubRegs */
8025 false, /* CoveredBySubRegs */
8026 NullRegClasses,
8027 nullptr
8028 };
8029
8030 extern const TargetRegisterClass FR16RegClass = {
8031 &X86MCRegisterClasses[FR16RegClassID],
8032 FR16SubClassMask,
8033 SuperRegIdxSeqs + 12,
8034 LaneBitmask(0x0000000000000001),
8035 0,
8036 false,
8037 0x00, /* TSFlags */
8038 false, /* HasDisjunctSubRegs */
8039 false, /* CoveredBySubRegs */
8040 FR16Superclasses,
8041 nullptr
8042 };
8043
8044 extern const TargetRegisterClass VK16PAIRRegClass = {
8045 &X86MCRegisterClasses[VK16PAIRRegClassID],
8046 VK16PAIRSubClassMask,
8047 SuperRegIdxSeqs + 1,
8048 LaneBitmask(0x0000000000000030),
8049 0,
8050 false,
8051 0x00, /* TSFlags */
8052 true, /* HasDisjunctSubRegs */
8053 true, /* CoveredBySubRegs */
8054 VK16PAIRSuperclasses,
8055 nullptr
8056 };
8057
8058 extern const TargetRegisterClass VK1PAIRRegClass = {
8059 &X86MCRegisterClasses[VK1PAIRRegClassID],
8060 VK1PAIRSubClassMask,
8061 SuperRegIdxSeqs + 1,
8062 LaneBitmask(0x0000000000000030),
8063 0,
8064 false,
8065 0x00, /* TSFlags */
8066 true, /* HasDisjunctSubRegs */
8067 true, /* CoveredBySubRegs */
8068 VK1PAIRSuperclasses,
8069 nullptr
8070 };
8071
8072 extern const TargetRegisterClass VK2PAIRRegClass = {
8073 &X86MCRegisterClasses[VK2PAIRRegClassID],
8074 VK2PAIRSubClassMask,
8075 SuperRegIdxSeqs + 1,
8076 LaneBitmask(0x0000000000000030),
8077 0,
8078 false,
8079 0x00, /* TSFlags */
8080 true, /* HasDisjunctSubRegs */
8081 true, /* CoveredBySubRegs */
8082 VK2PAIRSuperclasses,
8083 nullptr
8084 };
8085
8086 extern const TargetRegisterClass VK4PAIRRegClass = {
8087 &X86MCRegisterClasses[VK4PAIRRegClassID],
8088 VK4PAIRSubClassMask,
8089 SuperRegIdxSeqs + 1,
8090 LaneBitmask(0x0000000000000030),
8091 0,
8092 false,
8093 0x00, /* TSFlags */
8094 true, /* HasDisjunctSubRegs */
8095 true, /* CoveredBySubRegs */
8096 VK4PAIRSuperclasses,
8097 nullptr
8098 };
8099
8100 extern const TargetRegisterClass VK8PAIRRegClass = {
8101 &X86MCRegisterClasses[VK8PAIRRegClassID],
8102 VK8PAIRSubClassMask,
8103 SuperRegIdxSeqs + 1,
8104 LaneBitmask(0x0000000000000030),
8105 0,
8106 false,
8107 0x00, /* TSFlags */
8108 true, /* HasDisjunctSubRegs */
8109 true, /* CoveredBySubRegs */
8110 VK8PAIRSuperclasses,
8111 nullptr
8112 };
8113
8114 extern const TargetRegisterClass VK1PAIR_with_sub_mask_0_in_VK1WMRegClass = {
8115 &X86MCRegisterClasses[VK1PAIR_with_sub_mask_0_in_VK1WMRegClassID],
8116 VK1PAIR_with_sub_mask_0_in_VK1WMSubClassMask,
8117 SuperRegIdxSeqs + 1,
8118 LaneBitmask(0x0000000000000030),
8119 0,
8120 false,
8121 0x00, /* TSFlags */
8122 true, /* HasDisjunctSubRegs */
8123 true, /* CoveredBySubRegs */
8124 VK1PAIR_with_sub_mask_0_in_VK1WMSuperclasses,
8125 nullptr
8126 };
8127
8128 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass = {
8129 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBPRegClassID],
8130 LOW32_ADDR_ACCESS_RBPSubClassMask,
8131 SuperRegIdxSeqs + 7,
8132 LaneBitmask(0x000000000000000F),
8133 0,
8134 false,
8135 0x00, /* TSFlags */
8136 true, /* HasDisjunctSubRegs */
8137 false, /* CoveredBySubRegs */
8138 NullRegClasses,
8139 nullptr
8140 };
8141
8142 extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass = {
8143 &X86MCRegisterClasses[LOW32_ADDR_ACCESSRegClassID],
8144 LOW32_ADDR_ACCESSSubClassMask,
8145 SuperRegIdxSeqs + 7,
8146 LaneBitmask(0x000000000000000F),
8147 0,
8148 false,
8149 0x00, /* TSFlags */
8150 true, /* HasDisjunctSubRegs */
8151 false, /* CoveredBySubRegs */
8152 LOW32_ADDR_ACCESSSuperclasses,
8153 nullptr
8154 };
8155
8156 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass = {
8157 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID],
8158 LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask,
8159 SuperRegIdxSeqs + 7,
8160 LaneBitmask(0x000000000000000F),
8161 0,
8162 false,
8163 0x00, /* TSFlags */
8164 true, /* HasDisjunctSubRegs */
8165 false, /* CoveredBySubRegs */
8166 LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses,
8167 nullptr
8168 };
8169
8170 extern const TargetRegisterClass FR32XRegClass = {
8171 &X86MCRegisterClasses[FR32XRegClassID],
8172 FR32XSubClassMask,
8173 SuperRegIdxSeqs + 12,
8174 LaneBitmask(0x0000000000000001),
8175 0,
8176 false,
8177 0x00, /* TSFlags */
8178 false, /* HasDisjunctSubRegs */
8179 false, /* CoveredBySubRegs */
8180 FR32XSuperclasses,
8181 nullptr
8182 };
8183
8184 extern const TargetRegisterClass GR32RegClass = {
8185 &X86MCRegisterClasses[GR32RegClassID],
8186 GR32SubClassMask,
8187 SuperRegIdxSeqs + 7,
8188 LaneBitmask(0x0000000000000007),
8189 0,
8190 false,
8191 0x00, /* TSFlags */
8192 true, /* HasDisjunctSubRegs */
8193 true, /* CoveredBySubRegs */
8194 GR32Superclasses,
8195 nullptr
8196 };
8197
8198 extern const TargetRegisterClass GR32_NOSPRegClass = {
8199 &X86MCRegisterClasses[GR32_NOSPRegClassID],
8200 GR32_NOSPSubClassMask,
8201 SuperRegIdxSeqs + 7,
8202 LaneBitmask(0x0000000000000007),
8203 0,
8204 false,
8205 0x00, /* TSFlags */
8206 true, /* HasDisjunctSubRegs */
8207 true, /* CoveredBySubRegs */
8208 GR32_NOSPSuperclasses,
8209 nullptr
8210 };
8211
8212 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass = {
8213 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClassID],
8214 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2SubClassMask,
8215 SuperRegIdxSeqs + 7,
8216 LaneBitmask(0x000000000000000F),
8217 0,
8218 false,
8219 0x00, /* TSFlags */
8220 true, /* HasDisjunctSubRegs */
8221 false, /* CoveredBySubRegs */
8222 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2Superclasses,
8223 nullptr
8224 };
8225
8226 extern const TargetRegisterClass DEBUG_REGRegClass = {
8227 &X86MCRegisterClasses[DEBUG_REGRegClassID],
8228 DEBUG_REGSubClassMask,
8229 SuperRegIdxSeqs + 1,
8230 LaneBitmask(0x0000000000000001),
8231 0,
8232 false,
8233 0x00, /* TSFlags */
8234 false, /* HasDisjunctSubRegs */
8235 false, /* CoveredBySubRegs */
8236 NullRegClasses,
8237 nullptr
8238 };
8239
8240 extern const TargetRegisterClass FR32RegClass = {
8241 &X86MCRegisterClasses[FR32RegClassID],
8242 FR32SubClassMask,
8243 SuperRegIdxSeqs + 12,
8244 LaneBitmask(0x0000000000000001),
8245 0,
8246 false,
8247 0x00, /* TSFlags */
8248 false, /* HasDisjunctSubRegs */
8249 false, /* CoveredBySubRegs */
8250 FR32Superclasses,
8251 nullptr
8252 };
8253
8254 extern const TargetRegisterClass GR32_NOREX2RegClass = {
8255 &X86MCRegisterClasses[GR32_NOREX2RegClassID],
8256 GR32_NOREX2SubClassMask,
8257 SuperRegIdxSeqs + 7,
8258 LaneBitmask(0x0000000000000007),
8259 0,
8260 false,
8261 0x00, /* TSFlags */
8262 true, /* HasDisjunctSubRegs */
8263 true, /* CoveredBySubRegs */
8264 GR32_NOREX2Superclasses,
8265 nullptr
8266 };
8267
8268 extern const TargetRegisterClass GR32_NOREX2_NOSPRegClass = {
8269 &X86MCRegisterClasses[GR32_NOREX2_NOSPRegClassID],
8270 GR32_NOREX2_NOSPSubClassMask,
8271 SuperRegIdxSeqs + 7,
8272 LaneBitmask(0x0000000000000007),
8273 0,
8274 false,
8275 0x00, /* TSFlags */
8276 true, /* HasDisjunctSubRegs */
8277 true, /* CoveredBySubRegs */
8278 GR32_NOREX2_NOSPSuperclasses,
8279 nullptr
8280 };
8281
8282 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass = {
8283 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID],
8284 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask,
8285 SuperRegIdxSeqs + 7,
8286 LaneBitmask(0x000000000000000F),
8287 0,
8288 false,
8289 0x00, /* TSFlags */
8290 true, /* HasDisjunctSubRegs */
8291 false, /* CoveredBySubRegs */
8292 LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses,
8293 nullptr
8294 };
8295
8296 extern const TargetRegisterClass GR32_NOREXRegClass = {
8297 &X86MCRegisterClasses[GR32_NOREXRegClassID],
8298 GR32_NOREXSubClassMask,
8299 SuperRegIdxSeqs + 7,
8300 LaneBitmask(0x0000000000000007),
8301 0,
8302 false,
8303 0x00, /* TSFlags */
8304 true, /* HasDisjunctSubRegs */
8305 true, /* CoveredBySubRegs */
8306 GR32_NOREXSuperclasses,
8307 nullptr
8308 };
8309
8310 extern const TargetRegisterClass VK32RegClass = {
8311 &X86MCRegisterClasses[VK32RegClassID],
8312 VK32SubClassMask,
8313 SuperRegIdxSeqs + 9,
8314 LaneBitmask(0x0000000000000001),
8315 0,
8316 false,
8317 0x00, /* TSFlags */
8318 false, /* HasDisjunctSubRegs */
8319 false, /* CoveredBySubRegs */
8320 VK32Superclasses,
8321 nullptr
8322 };
8323
8324 extern const TargetRegisterClass GR32_NOREX_NOSPRegClass = {
8325 &X86MCRegisterClasses[GR32_NOREX_NOSPRegClassID],
8326 GR32_NOREX_NOSPSubClassMask,
8327 SuperRegIdxSeqs + 7,
8328 LaneBitmask(0x0000000000000007),
8329 0,
8330 false,
8331 0x00, /* TSFlags */
8332 true, /* HasDisjunctSubRegs */
8333 true, /* CoveredBySubRegs */
8334 GR32_NOREX_NOSPSuperclasses,
8335 nullptr
8336 };
8337
8338 extern const TargetRegisterClass RFP32RegClass = {
8339 &X86MCRegisterClasses[RFP32RegClassID],
8340 RFP32SubClassMask,
8341 SuperRegIdxSeqs + 1,
8342 LaneBitmask(0x0000000000000001),
8343 0,
8344 false,
8345 0x00, /* TSFlags */
8346 false, /* HasDisjunctSubRegs */
8347 false, /* CoveredBySubRegs */
8348 NullRegClasses,
8349 nullptr
8350 };
8351
8352 extern const TargetRegisterClass VK32WMRegClass = {
8353 &X86MCRegisterClasses[VK32WMRegClassID],
8354 VK32WMSubClassMask,
8355 SuperRegIdxSeqs + 9,
8356 LaneBitmask(0x0000000000000001),
8357 0,
8358 false,
8359 0x00, /* TSFlags */
8360 false, /* HasDisjunctSubRegs */
8361 false, /* CoveredBySubRegs */
8362 VK32WMSuperclasses,
8363 nullptr
8364 };
8365
8366 extern const TargetRegisterClass GR32_ABCDRegClass = {
8367 &X86MCRegisterClasses[GR32_ABCDRegClassID],
8368 GR32_ABCDSubClassMask,
8369 SuperRegIdxSeqs + 7,
8370 LaneBitmask(0x0000000000000007),
8371 0,
8372 false,
8373 0x00, /* TSFlags */
8374 true, /* HasDisjunctSubRegs */
8375 true, /* CoveredBySubRegs */
8376 GR32_ABCDSuperclasses,
8377 nullptr
8378 };
8379
8380 extern const TargetRegisterClass GR32_TCRegClass = {
8381 &X86MCRegisterClasses[GR32_TCRegClassID],
8382 GR32_TCSubClassMask,
8383 SuperRegIdxSeqs + 7,
8384 LaneBitmask(0x0000000000000007),
8385 0,
8386 false,
8387 0x00, /* TSFlags */
8388 true, /* HasDisjunctSubRegs */
8389 true, /* CoveredBySubRegs */
8390 GR32_TCSuperclasses,
8391 nullptr
8392 };
8393
8394 extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass = {
8395 &X86MCRegisterClasses[GR32_ABCD_and_GR32_TCRegClassID],
8396 GR32_ABCD_and_GR32_TCSubClassMask,
8397 SuperRegIdxSeqs + 7,
8398 LaneBitmask(0x0000000000000007),
8399 0,
8400 false,
8401 0x00, /* TSFlags */
8402 true, /* HasDisjunctSubRegs */
8403 true, /* CoveredBySubRegs */
8404 GR32_ABCD_and_GR32_TCSuperclasses,
8405 nullptr
8406 };
8407
8408 extern const TargetRegisterClass GR32_ADRegClass = {
8409 &X86MCRegisterClasses[GR32_ADRegClassID],
8410 GR32_ADSubClassMask,
8411 SuperRegIdxSeqs + 7,
8412 LaneBitmask(0x0000000000000007),
8413 0,
8414 false,
8415 0x00, /* TSFlags */
8416 true, /* HasDisjunctSubRegs */
8417 true, /* CoveredBySubRegs */
8418 GR32_ADSuperclasses,
8419 nullptr
8420 };
8421
8422 extern const TargetRegisterClass GR32_ArgRefRegClass = {
8423 &X86MCRegisterClasses[GR32_ArgRefRegClassID],
8424 GR32_ArgRefSubClassMask,
8425 SuperRegIdxSeqs + 7,
8426 LaneBitmask(0x0000000000000007),
8427 0,
8428 false,
8429 0x00, /* TSFlags */
8430 true, /* HasDisjunctSubRegs */
8431 true, /* CoveredBySubRegs */
8432 GR32_ArgRefSuperclasses,
8433 nullptr
8434 };
8435
8436 extern const TargetRegisterClass GR32_BPSPRegClass = {
8437 &X86MCRegisterClasses[GR32_BPSPRegClassID],
8438 GR32_BPSPSubClassMask,
8439 SuperRegIdxSeqs + 7,
8440 LaneBitmask(0x0000000000000007),
8441 0,
8442 false,
8443 0x00, /* TSFlags */
8444 true, /* HasDisjunctSubRegs */
8445 true, /* CoveredBySubRegs */
8446 GR32_BPSPSuperclasses,
8447 nullptr
8448 };
8449
8450 extern const TargetRegisterClass GR32_BSIRegClass = {
8451 &X86MCRegisterClasses[GR32_BSIRegClassID],
8452 GR32_BSISubClassMask,
8453 SuperRegIdxSeqs + 7,
8454 LaneBitmask(0x0000000000000007),
8455 0,
8456 false,
8457 0x00, /* TSFlags */
8458 true, /* HasDisjunctSubRegs */
8459 true, /* CoveredBySubRegs */
8460 GR32_BSISuperclasses,
8461 nullptr
8462 };
8463
8464 extern const TargetRegisterClass GR32_CBRegClass = {
8465 &X86MCRegisterClasses[GR32_CBRegClassID],
8466 GR32_CBSubClassMask,
8467 SuperRegIdxSeqs + 7,
8468 LaneBitmask(0x0000000000000007),
8469 0,
8470 false,
8471 0x00, /* TSFlags */
8472 true, /* HasDisjunctSubRegs */
8473 true, /* CoveredBySubRegs */
8474 GR32_CBSuperclasses,
8475 nullptr
8476 };
8477
8478 extern const TargetRegisterClass GR32_DCRegClass = {
8479 &X86MCRegisterClasses[GR32_DCRegClassID],
8480 GR32_DCSubClassMask,
8481 SuperRegIdxSeqs + 7,
8482 LaneBitmask(0x0000000000000007),
8483 0,
8484 false,
8485 0x00, /* TSFlags */
8486 true, /* HasDisjunctSubRegs */
8487 true, /* CoveredBySubRegs */
8488 GR32_DCSuperclasses,
8489 nullptr
8490 };
8491
8492 extern const TargetRegisterClass GR32_DIBPRegClass = {
8493 &X86MCRegisterClasses[GR32_DIBPRegClassID],
8494 GR32_DIBPSubClassMask,
8495 SuperRegIdxSeqs + 7,
8496 LaneBitmask(0x0000000000000007),
8497 0,
8498 false,
8499 0x00, /* TSFlags */
8500 true, /* HasDisjunctSubRegs */
8501 true, /* CoveredBySubRegs */
8502 GR32_DIBPSuperclasses,
8503 nullptr
8504 };
8505
8506 extern const TargetRegisterClass GR32_SIDIRegClass = {
8507 &X86MCRegisterClasses[GR32_SIDIRegClassID],
8508 GR32_SIDISubClassMask,
8509 SuperRegIdxSeqs + 7,
8510 LaneBitmask(0x0000000000000007),
8511 0,
8512 false,
8513 0x00, /* TSFlags */
8514 true, /* HasDisjunctSubRegs */
8515 true, /* CoveredBySubRegs */
8516 GR32_SIDISuperclasses,
8517 nullptr
8518 };
8519
8520 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass = {
8521 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID],
8522 LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask,
8523 SuperRegIdxSeqs + 1,
8524 LaneBitmask(0x000000000000000F),
8525 0,
8526 false,
8527 0x00, /* TSFlags */
8528 true, /* HasDisjunctSubRegs */
8529 false, /* CoveredBySubRegs */
8530 LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses,
8531 nullptr
8532 };
8533
8534 extern const TargetRegisterClass CCRRegClass = {
8535 &X86MCRegisterClasses[CCRRegClassID],
8536 CCRSubClassMask,
8537 SuperRegIdxSeqs + 1,
8538 LaneBitmask(0x0000000000000001),
8539 0,
8540 false,
8541 0x00, /* TSFlags */
8542 false, /* HasDisjunctSubRegs */
8543 false, /* CoveredBySubRegs */
8544 NullRegClasses,
8545 nullptr
8546 };
8547
8548 extern const TargetRegisterClass DFCCRRegClass = {
8549 &X86MCRegisterClasses[DFCCRRegClassID],
8550 DFCCRSubClassMask,
8551 SuperRegIdxSeqs + 1,
8552 LaneBitmask(0x0000000000000001),
8553 0,
8554 false,
8555 0x00, /* TSFlags */
8556 false, /* HasDisjunctSubRegs */
8557 false, /* CoveredBySubRegs */
8558 NullRegClasses,
8559 nullptr
8560 };
8561
8562 extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass = {
8563 &X86MCRegisterClasses[GR32_ABCD_and_GR32_BSIRegClassID],
8564 GR32_ABCD_and_GR32_BSISubClassMask,
8565 SuperRegIdxSeqs + 7,
8566 LaneBitmask(0x0000000000000007),
8567 0,
8568 false,
8569 0x00, /* TSFlags */
8570 true, /* HasDisjunctSubRegs */
8571 true, /* CoveredBySubRegs */
8572 GR32_ABCD_and_GR32_BSISuperclasses,
8573 nullptr
8574 };
8575
8576 extern const TargetRegisterClass GR32_AD_and_GR32_ArgRefRegClass = {
8577 &X86MCRegisterClasses[GR32_AD_and_GR32_ArgRefRegClassID],
8578 GR32_AD_and_GR32_ArgRefSubClassMask,
8579 SuperRegIdxSeqs + 7,
8580 LaneBitmask(0x0000000000000007),
8581 0,
8582 false,
8583 0x00, /* TSFlags */
8584 true, /* HasDisjunctSubRegs */
8585 true, /* CoveredBySubRegs */
8586 GR32_AD_and_GR32_ArgRefSuperclasses,
8587 nullptr
8588 };
8589
8590 extern const TargetRegisterClass GR32_ArgRef_and_GR32_CBRegClass = {
8591 &X86MCRegisterClasses[GR32_ArgRef_and_GR32_CBRegClassID],
8592 GR32_ArgRef_and_GR32_CBSubClassMask,
8593 SuperRegIdxSeqs + 7,
8594 LaneBitmask(0x0000000000000007),
8595 0,
8596 false,
8597 0x00, /* TSFlags */
8598 true, /* HasDisjunctSubRegs */
8599 true, /* CoveredBySubRegs */
8600 GR32_ArgRef_and_GR32_CBSuperclasses,
8601 nullptr
8602 };
8603
8604 extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass = {
8605 &X86MCRegisterClasses[GR32_BPSP_and_GR32_DIBPRegClassID],
8606 GR32_BPSP_and_GR32_DIBPSubClassMask,
8607 SuperRegIdxSeqs + 7,
8608 LaneBitmask(0x0000000000000007),
8609 0,
8610 false,
8611 0x00, /* TSFlags */
8612 true, /* HasDisjunctSubRegs */
8613 true, /* CoveredBySubRegs */
8614 GR32_BPSP_and_GR32_DIBPSuperclasses,
8615 nullptr
8616 };
8617
8618 extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass = {
8619 &X86MCRegisterClasses[GR32_BPSP_and_GR32_TCRegClassID],
8620 GR32_BPSP_and_GR32_TCSubClassMask,
8621 SuperRegIdxSeqs + 7,
8622 LaneBitmask(0x0000000000000007),
8623 0,
8624 false,
8625 0x00, /* TSFlags */
8626 true, /* HasDisjunctSubRegs */
8627 true, /* CoveredBySubRegs */
8628 GR32_BPSP_and_GR32_TCSuperclasses,
8629 nullptr
8630 };
8631
8632 extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass = {
8633 &X86MCRegisterClasses[GR32_BSI_and_GR32_SIDIRegClassID],
8634 GR32_BSI_and_GR32_SIDISubClassMask,
8635 SuperRegIdxSeqs + 7,
8636 LaneBitmask(0x0000000000000007),
8637 0,
8638 false,
8639 0x00, /* TSFlags */
8640 true, /* HasDisjunctSubRegs */
8641 true, /* CoveredBySubRegs */
8642 GR32_BSI_and_GR32_SIDISuperclasses,
8643 nullptr
8644 };
8645
8646 extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass = {
8647 &X86MCRegisterClasses[GR32_DIBP_and_GR32_SIDIRegClassID],
8648 GR32_DIBP_and_GR32_SIDISubClassMask,
8649 SuperRegIdxSeqs + 7,
8650 LaneBitmask(0x0000000000000007),
8651 0,
8652 false,
8653 0x00, /* TSFlags */
8654 true, /* HasDisjunctSubRegs */
8655 true, /* CoveredBySubRegs */
8656 GR32_DIBP_and_GR32_SIDISuperclasses,
8657 nullptr
8658 };
8659
8660 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass = {
8661 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID],
8662 LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask,
8663 SuperRegIdxSeqs + 1,
8664 LaneBitmask(0x000000000000000F),
8665 0,
8666 false,
8667 0x00, /* TSFlags */
8668 true, /* HasDisjunctSubRegs */
8669 false, /* CoveredBySubRegs */
8670 LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses,
8671 nullptr
8672 };
8673
8674 extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass = {
8675 &X86MCRegisterClasses[LOW32_ADDR_ACCESS_with_sub_32bitRegClassID],
8676 LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask,
8677 SuperRegIdxSeqs + 1,
8678 LaneBitmask(0x000000000000000F),
8679 0,
8680 false,
8681 0x00, /* TSFlags */
8682 true, /* HasDisjunctSubRegs */
8683 false, /* CoveredBySubRegs */
8684 LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses,
8685 nullptr
8686 };
8687
8688 extern const TargetRegisterClass RFP64RegClass = {
8689 &X86MCRegisterClasses[RFP64RegClassID],
8690 RFP64SubClassMask,
8691 SuperRegIdxSeqs + 1,
8692 LaneBitmask(0x0000000000000001),
8693 0,
8694 false,
8695 0x00, /* TSFlags */
8696 false, /* HasDisjunctSubRegs */
8697 false, /* CoveredBySubRegs */
8698 RFP64Superclasses,
8699 nullptr
8700 };
8701
8702 extern const TargetRegisterClass GR64RegClass = {
8703 &X86MCRegisterClasses[GR64RegClassID],
8704 GR64SubClassMask,
8705 SuperRegIdxSeqs + 1,
8706 LaneBitmask(0x000000000000000F),
8707 0,
8708 false,
8709 0x00, /* TSFlags */
8710 true, /* HasDisjunctSubRegs */
8711 false, /* CoveredBySubRegs */
8712 NullRegClasses,
8713 nullptr
8714 };
8715
8716 extern const TargetRegisterClass FR64XRegClass = {
8717 &X86MCRegisterClasses[FR64XRegClassID],
8718 FR64XSubClassMask,
8719 SuperRegIdxSeqs + 12,
8720 LaneBitmask(0x0000000000000001),
8721 0,
8722 false,
8723 0x00, /* TSFlags */
8724 false, /* HasDisjunctSubRegs */
8725 false, /* CoveredBySubRegs */
8726 FR64XSuperclasses,
8727 nullptr
8728 };
8729
8730 extern const TargetRegisterClass GR64_with_sub_8bitRegClass = {
8731 &X86MCRegisterClasses[GR64_with_sub_8bitRegClassID],
8732 GR64_with_sub_8bitSubClassMask,
8733 SuperRegIdxSeqs + 1,
8734 LaneBitmask(0x000000000000000F),
8735 0,
8736 false,
8737 0x00, /* TSFlags */
8738 true, /* HasDisjunctSubRegs */
8739 false, /* CoveredBySubRegs */
8740 GR64_with_sub_8bitSuperclasses,
8741 nullptr
8742 };
8743
8744 extern const TargetRegisterClass GR64_NOSPRegClass = {
8745 &X86MCRegisterClasses[GR64_NOSPRegClassID],
8746 GR64_NOSPSubClassMask,
8747 SuperRegIdxSeqs + 1,
8748 LaneBitmask(0x000000000000000F),
8749 0,
8750 false,
8751 0x00, /* TSFlags */
8752 true, /* HasDisjunctSubRegs */
8753 false, /* CoveredBySubRegs */
8754 GR64_NOSPSuperclasses,
8755 nullptr
8756 };
8757
8758 extern const TargetRegisterClass GR64_NOREX2RegClass = {
8759 &X86MCRegisterClasses[GR64_NOREX2RegClassID],
8760 GR64_NOREX2SubClassMask,
8761 SuperRegIdxSeqs + 1,
8762 LaneBitmask(0x000000000000000F),
8763 0,
8764 false,
8765 0x00, /* TSFlags */
8766 true, /* HasDisjunctSubRegs */
8767 false, /* CoveredBySubRegs */
8768 GR64_NOREX2Superclasses,
8769 nullptr
8770 };
8771
8772 extern const TargetRegisterClass CONTROL_REGRegClass = {
8773 &X86MCRegisterClasses[CONTROL_REGRegClassID],
8774 CONTROL_REGSubClassMask,
8775 SuperRegIdxSeqs + 1,
8776 LaneBitmask(0x0000000000000001),
8777 0,
8778 false,
8779 0x00, /* TSFlags */
8780 false, /* HasDisjunctSubRegs */
8781 false, /* CoveredBySubRegs */
8782 NullRegClasses,
8783 nullptr
8784 };
8785
8786 extern const TargetRegisterClass FR64RegClass = {
8787 &X86MCRegisterClasses[FR64RegClassID],
8788 FR64SubClassMask,
8789 SuperRegIdxSeqs + 12,
8790 LaneBitmask(0x0000000000000001),
8791 0,
8792 false,
8793 0x00, /* TSFlags */
8794 false, /* HasDisjunctSubRegs */
8795 false, /* CoveredBySubRegs */
8796 FR64Superclasses,
8797 nullptr
8798 };
8799
8800 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREX2RegClass = {
8801 &X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREX2RegClassID],
8802 GR64_with_sub_16bit_in_GR16_NOREX2SubClassMask,
8803 SuperRegIdxSeqs + 1,
8804 LaneBitmask(0x000000000000000F),
8805 0,
8806 false,
8807 0x00, /* TSFlags */
8808 true, /* HasDisjunctSubRegs */
8809 false, /* CoveredBySubRegs */
8810 GR64_with_sub_16bit_in_GR16_NOREX2Superclasses,
8811 nullptr
8812 };
8813
8814 extern const TargetRegisterClass GR64_NOREX2_NOSPRegClass = {
8815 &X86MCRegisterClasses[GR64_NOREX2_NOSPRegClassID],
8816 GR64_NOREX2_NOSPSubClassMask,
8817 SuperRegIdxSeqs + 1,
8818 LaneBitmask(0x000000000000000F),
8819 0,
8820 false,
8821 0x00, /* TSFlags */
8822 true, /* HasDisjunctSubRegs */
8823 false, /* CoveredBySubRegs */
8824 GR64_NOREX2_NOSPSuperclasses,
8825 nullptr
8826 };
8827
8828 extern const TargetRegisterClass GR64PLTSafeRegClass = {
8829 &X86MCRegisterClasses[GR64PLTSafeRegClassID],
8830 GR64PLTSafeSubClassMask,
8831 SuperRegIdxSeqs + 1,
8832 LaneBitmask(0x000000000000000F),
8833 0,
8834 false,
8835 0x00, /* TSFlags */
8836 true, /* HasDisjunctSubRegs */
8837 false, /* CoveredBySubRegs */
8838 GR64PLTSafeSuperclasses,
8839 nullptr
8840 };
8841
8842 extern const TargetRegisterClass GR64_TCRegClass = {
8843 &X86MCRegisterClasses[GR64_TCRegClassID],
8844 GR64_TCSubClassMask,
8845 SuperRegIdxSeqs + 1,
8846 LaneBitmask(0x000000000000000F),
8847 0,
8848 false,
8849 0x00, /* TSFlags */
8850 true, /* HasDisjunctSubRegs */
8851 false, /* CoveredBySubRegs */
8852 GR64_TCSuperclasses,
8853 nullptr
8854 };
8855
8856 extern const TargetRegisterClass GR64_NOREXRegClass = {
8857 &X86MCRegisterClasses[GR64_NOREXRegClassID],
8858 GR64_NOREXSubClassMask,
8859 SuperRegIdxSeqs + 1,
8860 LaneBitmask(0x000000000000000F),
8861 0,
8862 false,
8863 0x00, /* TSFlags */
8864 true, /* HasDisjunctSubRegs */
8865 false, /* CoveredBySubRegs */
8866 GR64_NOREXSuperclasses,
8867 nullptr
8868 };
8869
8870 extern const TargetRegisterClass GR64_TCW64RegClass = {
8871 &X86MCRegisterClasses[GR64_TCW64RegClassID],
8872 GR64_TCW64SubClassMask,
8873 SuperRegIdxSeqs + 1,
8874 LaneBitmask(0x000000000000000F),
8875 0,
8876 false,
8877 0x00, /* TSFlags */
8878 true, /* HasDisjunctSubRegs */
8879 false, /* CoveredBySubRegs */
8880 GR64_TCW64Superclasses,
8881 nullptr
8882 };
8883
8884 extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass = {
8885 &X86MCRegisterClasses[GR64_TC_with_sub_8bitRegClassID],
8886 GR64_TC_with_sub_8bitSubClassMask,
8887 SuperRegIdxSeqs + 1,
8888 LaneBitmask(0x000000000000000F),
8889 0,
8890 false,
8891 0x00, /* TSFlags */
8892 true, /* HasDisjunctSubRegs */
8893 false, /* CoveredBySubRegs */
8894 GR64_TC_with_sub_8bitSuperclasses,
8895 nullptr
8896 };
8897
8898 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCRegClass = {
8899 &X86MCRegisterClasses[GR64_NOREX2_NOSP_and_GR64_TCRegClassID],
8900 GR64_NOREX2_NOSP_and_GR64_TCSubClassMask,
8901 SuperRegIdxSeqs + 1,
8902 LaneBitmask(0x000000000000000F),
8903 0,
8904 false,
8905 0x00, /* TSFlags */
8906 true, /* HasDisjunctSubRegs */
8907 false, /* CoveredBySubRegs */
8908 GR64_NOREX2_NOSP_and_GR64_TCSuperclasses,
8909 nullptr
8910 };
8911
8912 extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass = {
8913 &X86MCRegisterClasses[GR64_TCW64_with_sub_8bitRegClassID],
8914 GR64_TCW64_with_sub_8bitSubClassMask,
8915 SuperRegIdxSeqs + 1,
8916 LaneBitmask(0x000000000000000F),
8917 0,
8918 false,
8919 0x00, /* TSFlags */
8920 true, /* HasDisjunctSubRegs */
8921 false, /* CoveredBySubRegs */
8922 GR64_TCW64_with_sub_8bitSuperclasses,
8923 nullptr
8924 };
8925
8926 extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass = {
8927 &X86MCRegisterClasses[GR64_TC_and_GR64_TCW64RegClassID],
8928 GR64_TC_and_GR64_TCW64SubClassMask,
8929 SuperRegIdxSeqs + 1,
8930 LaneBitmask(0x000000000000000F),
8931 0,
8932 false,
8933 0x00, /* TSFlags */
8934 true, /* HasDisjunctSubRegs */
8935 false, /* CoveredBySubRegs */
8936 GR64_TC_and_GR64_TCW64Superclasses,
8937 nullptr
8938 };
8939
8940 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
8941 &X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
8942 GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
8943 SuperRegIdxSeqs + 1,
8944 LaneBitmask(0x000000000000000F),
8945 0,
8946 false,
8947 0x00, /* TSFlags */
8948 true, /* HasDisjunctSubRegs */
8949 false, /* CoveredBySubRegs */
8950 GR64_with_sub_16bit_in_GR16_NOREXSuperclasses,
8951 nullptr
8952 };
8953
8954 extern const TargetRegisterClass VK64RegClass = {
8955 &X86MCRegisterClasses[VK64RegClassID],
8956 VK64SubClassMask,
8957 SuperRegIdxSeqs + 9,
8958 LaneBitmask(0x0000000000000001),
8959 0,
8960 false,
8961 0x00, /* TSFlags */
8962 false, /* HasDisjunctSubRegs */
8963 false, /* CoveredBySubRegs */
8964 VK64Superclasses,
8965 nullptr
8966 };
8967
8968 extern const TargetRegisterClass VR64RegClass = {
8969 &X86MCRegisterClasses[VR64RegClassID],
8970 VR64SubClassMask,
8971 SuperRegIdxSeqs + 1,
8972 LaneBitmask(0x0000000000000001),
8973 0,
8974 false,
8975 0x00, /* TSFlags */
8976 false, /* HasDisjunctSubRegs */
8977 false, /* CoveredBySubRegs */
8978 NullRegClasses,
8979 nullptr
8980 };
8981
8982 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCRegClass = {
8983 &X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCRegClassID],
8984 GR64PLTSafe_and_GR64_TCSubClassMask,
8985 SuperRegIdxSeqs + 1,
8986 LaneBitmask(0x000000000000000F),
8987 0,
8988 false,
8989 0x00, /* TSFlags */
8990 true, /* HasDisjunctSubRegs */
8991 false, /* CoveredBySubRegs */
8992 GR64PLTSafe_and_GR64_TCSuperclasses,
8993 nullptr
8994 };
8995
8996 extern const TargetRegisterClass GR64_NOREX2_NOSP_and_GR64_TCW64RegClass = {
8997 &X86MCRegisterClasses[GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID],
8998 GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask,
8999 SuperRegIdxSeqs + 1,
9000 LaneBitmask(0x000000000000000F),
9001 0,
9002 false,
9003 0x00, /* TSFlags */
9004 true, /* HasDisjunctSubRegs */
9005 false, /* CoveredBySubRegs */
9006 GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses,
9007 nullptr
9008 };
9009
9010 extern const TargetRegisterClass GR64_NOREX_NOSPRegClass = {
9011 &X86MCRegisterClasses[GR64_NOREX_NOSPRegClassID],
9012 GR64_NOREX_NOSPSubClassMask,
9013 SuperRegIdxSeqs + 1,
9014 LaneBitmask(0x000000000000000F),
9015 0,
9016 false,
9017 0x00, /* TSFlags */
9018 true, /* HasDisjunctSubRegs */
9019 false, /* CoveredBySubRegs */
9020 GR64_NOREX_NOSPSuperclasses,
9021 nullptr
9022 };
9023
9024 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass = {
9025 &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCRegClassID],
9026 GR64_NOREX_and_GR64_TCSubClassMask,
9027 SuperRegIdxSeqs + 1,
9028 LaneBitmask(0x000000000000000F),
9029 0,
9030 false,
9031 0x00, /* TSFlags */
9032 true, /* HasDisjunctSubRegs */
9033 false, /* CoveredBySubRegs */
9034 GR64_NOREX_and_GR64_TCSuperclasses,
9035 nullptr
9036 };
9037
9038 extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass = {
9039 &X86MCRegisterClasses[GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID],
9040 GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask,
9041 SuperRegIdxSeqs + 1,
9042 LaneBitmask(0x000000000000000F),
9043 0,
9044 false,
9045 0x00, /* TSFlags */
9046 true, /* HasDisjunctSubRegs */
9047 false, /* CoveredBySubRegs */
9048 GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses,
9049 nullptr
9050 };
9051
9052 extern const TargetRegisterClass VK64WMRegClass = {
9053 &X86MCRegisterClasses[VK64WMRegClassID],
9054 VK64WMSubClassMask,
9055 SuperRegIdxSeqs + 9,
9056 LaneBitmask(0x0000000000000001),
9057 0,
9058 false,
9059 0x00, /* TSFlags */
9060 false, /* HasDisjunctSubRegs */
9061 false, /* CoveredBySubRegs */
9062 VK64WMSuperclasses,
9063 nullptr
9064 };
9065
9066 extern const TargetRegisterClass GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass = {
9067 &X86MCRegisterClasses[GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClassID],
9068 GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64SubClassMask,
9069 SuperRegIdxSeqs + 1,
9070 LaneBitmask(0x000000000000000F),
9071 0,
9072 false,
9073 0x00, /* TSFlags */
9074 true, /* HasDisjunctSubRegs */
9075 false, /* CoveredBySubRegs */
9076 GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64Superclasses,
9077 nullptr
9078 };
9079
9080 extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
9081 &X86MCRegisterClasses[GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
9082 GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
9083 SuperRegIdxSeqs + 1,
9084 LaneBitmask(0x000000000000000F),
9085 0,
9086 false,
9087 0x00, /* TSFlags */
9088 true, /* HasDisjunctSubRegs */
9089 false, /* CoveredBySubRegs */
9090 GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses,
9091 nullptr
9092 };
9093
9094 extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCW64RegClass = {
9095 &X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCW64RegClassID],
9096 GR64PLTSafe_and_GR64_TCW64SubClassMask,
9097 SuperRegIdxSeqs + 1,
9098 LaneBitmask(0x000000000000000F),
9099 0,
9100 false,
9101 0x00, /* TSFlags */
9102 true, /* HasDisjunctSubRegs */
9103 false, /* CoveredBySubRegs */
9104 GR64PLTSafe_and_GR64_TCW64Superclasses,
9105 nullptr
9106 };
9107
9108 extern const TargetRegisterClass GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass = {
9109 &X86MCRegisterClasses[GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID],
9110 GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask,
9111 SuperRegIdxSeqs + 1,
9112 LaneBitmask(0x000000000000000F),
9113 0,
9114 false,
9115 0x00, /* TSFlags */
9116 true, /* HasDisjunctSubRegs */
9117 false, /* CoveredBySubRegs */
9118 GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses,
9119 nullptr
9120 };
9121
9122 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass = {
9123 &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCW64RegClassID],
9124 GR64_NOREX_and_GR64_TCW64SubClassMask,
9125 SuperRegIdxSeqs + 1,
9126 LaneBitmask(0x000000000000000F),
9127 0,
9128 false,
9129 0x00, /* TSFlags */
9130 true, /* HasDisjunctSubRegs */
9131 false, /* CoveredBySubRegs */
9132 GR64_NOREX_and_GR64_TCW64Superclasses,
9133 nullptr
9134 };
9135
9136 extern const TargetRegisterClass GR64_ABCDRegClass = {
9137 &X86MCRegisterClasses[GR64_ABCDRegClassID],
9138 GR64_ABCDSubClassMask,
9139 SuperRegIdxSeqs + 1,
9140 LaneBitmask(0x000000000000000F),
9141 0,
9142 false,
9143 0x00, /* TSFlags */
9144 true, /* HasDisjunctSubRegs */
9145 false, /* CoveredBySubRegs */
9146 GR64_ABCDSuperclasses,
9147 nullptr
9148 };
9149
9150 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass = {
9151 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_TCRegClassID],
9152 GR64_with_sub_32bit_in_GR32_TCSubClassMask,
9153 SuperRegIdxSeqs + 1,
9154 LaneBitmask(0x000000000000000F),
9155 0,
9156 false,
9157 0x00, /* TSFlags */
9158 true, /* HasDisjunctSubRegs */
9159 false, /* CoveredBySubRegs */
9160 GR64_with_sub_32bit_in_GR32_TCSuperclasses,
9161 nullptr
9162 };
9163
9164 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass = {
9165 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID],
9166 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask,
9167 SuperRegIdxSeqs + 1,
9168 LaneBitmask(0x000000000000000F),
9169 0,
9170 false,
9171 0x00, /* TSFlags */
9172 true, /* HasDisjunctSubRegs */
9173 false, /* CoveredBySubRegs */
9174 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses,
9175 nullptr
9176 };
9177
9178 extern const TargetRegisterClass GR64_ADRegClass = {
9179 &X86MCRegisterClasses[GR64_ADRegClassID],
9180 GR64_ADSubClassMask,
9181 SuperRegIdxSeqs + 1,
9182 LaneBitmask(0x000000000000000F),
9183 0,
9184 false,
9185 0x00, /* TSFlags */
9186 true, /* HasDisjunctSubRegs */
9187 false, /* CoveredBySubRegs */
9188 GR64_ADSuperclasses,
9189 nullptr
9190 };
9191
9192 extern const TargetRegisterClass GR64_ArgRefRegClass = {
9193 &X86MCRegisterClasses[GR64_ArgRefRegClassID],
9194 GR64_ArgRefSubClassMask,
9195 SuperRegIdxSeqs + 1,
9196 LaneBitmask(0x000000000000000F),
9197 0,
9198 false,
9199 0x00, /* TSFlags */
9200 true, /* HasDisjunctSubRegs */
9201 false, /* CoveredBySubRegs */
9202 GR64_ArgRefSuperclasses,
9203 nullptr
9204 };
9205
9206 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass = {
9207 &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID],
9208 GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask,
9209 SuperRegIdxSeqs + 1,
9210 LaneBitmask(0x000000000000000F),
9211 0,
9212 false,
9213 0x00, /* TSFlags */
9214 true, /* HasDisjunctSubRegs */
9215 false, /* CoveredBySubRegs */
9216 GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses,
9217 nullptr
9218 };
9219
9220 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRefRegClass = {
9221 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ArgRefRegClassID],
9222 GR64_with_sub_32bit_in_GR32_ArgRefSubClassMask,
9223 SuperRegIdxSeqs + 1,
9224 LaneBitmask(0x000000000000000F),
9225 0,
9226 false,
9227 0x00, /* TSFlags */
9228 true, /* HasDisjunctSubRegs */
9229 false, /* CoveredBySubRegs */
9230 GR64_with_sub_32bit_in_GR32_ArgRefSuperclasses,
9231 nullptr
9232 };
9233
9234 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass = {
9235 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSPRegClassID],
9236 GR64_with_sub_32bit_in_GR32_BPSPSubClassMask,
9237 SuperRegIdxSeqs + 1,
9238 LaneBitmask(0x000000000000000F),
9239 0,
9240 false,
9241 0x00, /* TSFlags */
9242 true, /* HasDisjunctSubRegs */
9243 false, /* CoveredBySubRegs */
9244 GR64_with_sub_32bit_in_GR32_BPSPSuperclasses,
9245 nullptr
9246 };
9247
9248 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass = {
9249 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSIRegClassID],
9250 GR64_with_sub_32bit_in_GR32_BSISubClassMask,
9251 SuperRegIdxSeqs + 1,
9252 LaneBitmask(0x000000000000000F),
9253 0,
9254 false,
9255 0x00, /* TSFlags */
9256 true, /* HasDisjunctSubRegs */
9257 false, /* CoveredBySubRegs */
9258 GR64_with_sub_32bit_in_GR32_BSISuperclasses,
9259 nullptr
9260 };
9261
9262 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass = {
9263 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CBRegClassID],
9264 GR64_with_sub_32bit_in_GR32_CBSubClassMask,
9265 SuperRegIdxSeqs + 1,
9266 LaneBitmask(0x000000000000000F),
9267 0,
9268 false,
9269 0x00, /* TSFlags */
9270 true, /* HasDisjunctSubRegs */
9271 false, /* CoveredBySubRegs */
9272 GR64_with_sub_32bit_in_GR32_CBSuperclasses,
9273 nullptr
9274 };
9275
9276 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass = {
9277 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBPRegClassID],
9278 GR64_with_sub_32bit_in_GR32_DIBPSubClassMask,
9279 SuperRegIdxSeqs + 1,
9280 LaneBitmask(0x000000000000000F),
9281 0,
9282 false,
9283 0x00, /* TSFlags */
9284 true, /* HasDisjunctSubRegs */
9285 false, /* CoveredBySubRegs */
9286 GR64_with_sub_32bit_in_GR32_DIBPSuperclasses,
9287 nullptr
9288 };
9289
9290 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass = {
9291 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_SIDIRegClassID],
9292 GR64_with_sub_32bit_in_GR32_SIDISubClassMask,
9293 SuperRegIdxSeqs + 1,
9294 LaneBitmask(0x000000000000000F),
9295 0,
9296 false,
9297 0x00, /* TSFlags */
9298 true, /* HasDisjunctSubRegs */
9299 false, /* CoveredBySubRegs */
9300 GR64_with_sub_32bit_in_GR32_SIDISuperclasses,
9301 nullptr
9302 };
9303
9304 extern const TargetRegisterClass GR64_ArgRef_and_GR64_TCRegClass = {
9305 &X86MCRegisterClasses[GR64_ArgRef_and_GR64_TCRegClassID],
9306 GR64_ArgRef_and_GR64_TCSubClassMask,
9307 SuperRegIdxSeqs + 1,
9308 LaneBitmask(0x000000000000000F),
9309 0,
9310 false,
9311 0x00, /* TSFlags */
9312 true, /* HasDisjunctSubRegs */
9313 false, /* CoveredBySubRegs */
9314 GR64_ArgRef_and_GR64_TCSuperclasses,
9315 nullptr
9316 };
9317
9318 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass = {
9319 &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESSRegClassID],
9320 GR64_and_LOW32_ADDR_ACCESSSubClassMask,
9321 SuperRegIdxSeqs + 1,
9322 LaneBitmask(0x000000000000000F),
9323 0,
9324 false,
9325 0x00, /* TSFlags */
9326 true, /* HasDisjunctSubRegs */
9327 false, /* CoveredBySubRegs */
9328 GR64_and_LOW32_ADDR_ACCESSSuperclasses,
9329 nullptr
9330 };
9331
9332 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass = {
9333 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID],
9334 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask,
9335 SuperRegIdxSeqs + 1,
9336 LaneBitmask(0x000000000000000F),
9337 0,
9338 false,
9339 0x00, /* TSFlags */
9340 true, /* HasDisjunctSubRegs */
9341 false, /* CoveredBySubRegs */
9342 GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses,
9343 nullptr
9344 };
9345
9346 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass = {
9347 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClassID],
9348 GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSubClassMask,
9349 SuperRegIdxSeqs + 1,
9350 LaneBitmask(0x000000000000000F),
9351 0,
9352 false,
9353 0x00, /* TSFlags */
9354 true, /* HasDisjunctSubRegs */
9355 false, /* CoveredBySubRegs */
9356 GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefSuperclasses,
9357 nullptr
9358 };
9359
9360 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass = {
9361 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClassID],
9362 GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSubClassMask,
9363 SuperRegIdxSeqs + 1,
9364 LaneBitmask(0x000000000000000F),
9365 0,
9366 false,
9367 0x00, /* TSFlags */
9368 true, /* HasDisjunctSubRegs */
9369 false, /* CoveredBySubRegs */
9370 GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBSuperclasses,
9371 nullptr
9372 };
9373
9374 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass = {
9375 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID],
9376 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask,
9377 SuperRegIdxSeqs + 1,
9378 LaneBitmask(0x000000000000000F),
9379 0,
9380 false,
9381 0x00, /* TSFlags */
9382 true, /* HasDisjunctSubRegs */
9383 false, /* CoveredBySubRegs */
9384 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses,
9385 nullptr
9386 };
9387
9388 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass = {
9389 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID],
9390 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask,
9391 SuperRegIdxSeqs + 1,
9392 LaneBitmask(0x000000000000000F),
9393 0,
9394 false,
9395 0x00, /* TSFlags */
9396 true, /* HasDisjunctSubRegs */
9397 false, /* CoveredBySubRegs */
9398 GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses,
9399 nullptr
9400 };
9401
9402 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass = {
9403 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID],
9404 GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask,
9405 SuperRegIdxSeqs + 1,
9406 LaneBitmask(0x000000000000000F),
9407 0,
9408 false,
9409 0x00, /* TSFlags */
9410 true, /* HasDisjunctSubRegs */
9411 false, /* CoveredBySubRegs */
9412 GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses,
9413 nullptr
9414 };
9415
9416 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass = {
9417 &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID],
9418 GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask,
9419 SuperRegIdxSeqs + 1,
9420 LaneBitmask(0x000000000000000F),
9421 0,
9422 false,
9423 0x00, /* TSFlags */
9424 true, /* HasDisjunctSubRegs */
9425 false, /* CoveredBySubRegs */
9426 GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses,
9427 nullptr
9428 };
9429
9430 extern const TargetRegisterClass RSTRegClass = {
9431 &X86MCRegisterClasses[RSTRegClassID],
9432 RSTSubClassMask,
9433 SuperRegIdxSeqs + 1,
9434 LaneBitmask(0x0000000000000001),
9435 0,
9436 false,
9437 0x00, /* TSFlags */
9438 false, /* HasDisjunctSubRegs */
9439 false, /* CoveredBySubRegs */
9440 NullRegClasses,
9441 nullptr
9442 };
9443
9444 extern const TargetRegisterClass RFP80RegClass = {
9445 &X86MCRegisterClasses[RFP80RegClassID],
9446 RFP80SubClassMask,
9447 SuperRegIdxSeqs + 1,
9448 LaneBitmask(0x0000000000000001),
9449 0,
9450 false,
9451 0x00, /* TSFlags */
9452 false, /* HasDisjunctSubRegs */
9453 false, /* CoveredBySubRegs */
9454 RFP80Superclasses,
9455 nullptr
9456 };
9457
9458 extern const TargetRegisterClass RFP80_7RegClass = {
9459 &X86MCRegisterClasses[RFP80_7RegClassID],
9460 RFP80_7SubClassMask,
9461 SuperRegIdxSeqs + 1,
9462 LaneBitmask(0x0000000000000001),
9463 0,
9464 false,
9465 0x00, /* TSFlags */
9466 false, /* HasDisjunctSubRegs */
9467 false, /* CoveredBySubRegs */
9468 NullRegClasses,
9469 nullptr
9470 };
9471
9472 extern const TargetRegisterClass VR128XRegClass = {
9473 &X86MCRegisterClasses[VR128XRegClassID],
9474 VR128XSubClassMask,
9475 SuperRegIdxSeqs + 12,
9476 LaneBitmask(0x0000000000000001),
9477 0,
9478 false,
9479 0x00, /* TSFlags */
9480 false, /* HasDisjunctSubRegs */
9481 false, /* CoveredBySubRegs */
9482 VR128XSuperclasses,
9483 nullptr
9484 };
9485
9486 extern const TargetRegisterClass VR128RegClass = {
9487 &X86MCRegisterClasses[VR128RegClassID],
9488 VR128SubClassMask,
9489 SuperRegIdxSeqs + 12,
9490 LaneBitmask(0x0000000000000001),
9491 0,
9492 false,
9493 0x00, /* TSFlags */
9494 false, /* HasDisjunctSubRegs */
9495 false, /* CoveredBySubRegs */
9496 VR128Superclasses,
9497 nullptr
9498 };
9499
9500 extern const TargetRegisterClass VR256XRegClass = {
9501 &X86MCRegisterClasses[VR256XRegClassID],
9502 VR256XSubClassMask,
9503 SuperRegIdxSeqs + 14,
9504 LaneBitmask(0x0000000000000040),
9505 0,
9506 false,
9507 0x00, /* TSFlags */
9508 false, /* HasDisjunctSubRegs */
9509 false, /* CoveredBySubRegs */
9510 NullRegClasses,
9511 nullptr
9512 };
9513
9514 extern const TargetRegisterClass VR256RegClass = {
9515 &X86MCRegisterClasses[VR256RegClassID],
9516 VR256SubClassMask,
9517 SuperRegIdxSeqs + 14,
9518 LaneBitmask(0x0000000000000040),
9519 0,
9520 false,
9521 0x00, /* TSFlags */
9522 false, /* HasDisjunctSubRegs */
9523 false, /* CoveredBySubRegs */
9524 VR256Superclasses,
9525 nullptr
9526 };
9527
9528 extern const TargetRegisterClass VR512RegClass = {
9529 &X86MCRegisterClasses[VR512RegClassID],
9530 VR512SubClassMask,
9531 SuperRegIdxSeqs + 1,
9532 LaneBitmask(0x0000000000000040),
9533 0,
9534 false,
9535 0x00, /* TSFlags */
9536 false, /* HasDisjunctSubRegs */
9537 false, /* CoveredBySubRegs */
9538 NullRegClasses,
9539 nullptr
9540 };
9541
9542 extern const TargetRegisterClass VR512_0_15RegClass = {
9543 &X86MCRegisterClasses[VR512_0_15RegClassID],
9544 VR512_0_15SubClassMask,
9545 SuperRegIdxSeqs + 1,
9546 LaneBitmask(0x0000000000000040),
9547 0,
9548 false,
9549 0x00, /* TSFlags */
9550 false, /* HasDisjunctSubRegs */
9551 false, /* CoveredBySubRegs */
9552 VR512_0_15Superclasses,
9553 nullptr
9554 };
9555
9556 extern const TargetRegisterClass TILERegClass = {
9557 &X86MCRegisterClasses[TILERegClassID],
9558 TILESubClassMask,
9559 SuperRegIdxSeqs + 1,
9560 LaneBitmask(0x0000000000000001),
9561 0,
9562 false,
9563 0x00, /* TSFlags */
9564 false, /* HasDisjunctSubRegs */
9565 false, /* CoveredBySubRegs */
9566 NullRegClasses,
9567 nullptr
9568 };
9569
9570} // end namespace X86
9571
9572namespace {
9573 const TargetRegisterClass *const RegisterClasses[] = {
9574 &X86::GR8RegClass,
9575 &X86::GRH8RegClass,
9576 &X86::GR8_NOREX2RegClass,
9577 &X86::GR8_NOREXRegClass,
9578 &X86::GR8_ABCD_HRegClass,
9579 &X86::GR8_ABCD_LRegClass,
9580 &X86::GRH16RegClass,
9581 &X86::GR16RegClass,
9582 &X86::GR16_NOREX2RegClass,
9583 &X86::GR16_NOREXRegClass,
9584 &X86::VK1RegClass,
9585 &X86::VK16RegClass,
9586 &X86::VK2RegClass,
9587 &X86::VK4RegClass,
9588 &X86::VK8RegClass,
9589 &X86::VK16WMRegClass,
9590 &X86::VK1WMRegClass,
9591 &X86::VK2WMRegClass,
9592 &X86::VK4WMRegClass,
9593 &X86::VK8WMRegClass,
9594 &X86::SEGMENT_REGRegClass,
9595 &X86::GR16_ABCDRegClass,
9596 &X86::FPCCRRegClass,
9597 &X86::FR16XRegClass,
9598 &X86::FR16RegClass,
9599 &X86::VK16PAIRRegClass,
9600 &X86::VK1PAIRRegClass,
9601 &X86::VK2PAIRRegClass,
9602 &X86::VK4PAIRRegClass,
9603 &X86::VK8PAIRRegClass,
9604 &X86::VK1PAIR_with_sub_mask_0_in_VK1WMRegClass,
9605 &X86::LOW32_ADDR_ACCESS_RBPRegClass,
9606 &X86::LOW32_ADDR_ACCESSRegClass,
9607 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
9608 &X86::FR32XRegClass,
9609 &X86::GR32RegClass,
9610 &X86::GR32_NOSPRegClass,
9611 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2RegClass,
9612 &X86::DEBUG_REGRegClass,
9613 &X86::FR32RegClass,
9614 &X86::GR32_NOREX2RegClass,
9615 &X86::GR32_NOREX2_NOSPRegClass,
9616 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
9617 &X86::GR32_NOREXRegClass,
9618 &X86::VK32RegClass,
9619 &X86::GR32_NOREX_NOSPRegClass,
9620 &X86::RFP32RegClass,
9621 &X86::VK32WMRegClass,
9622 &X86::GR32_ABCDRegClass,
9623 &X86::GR32_TCRegClass,
9624 &X86::GR32_ABCD_and_GR32_TCRegClass,
9625 &X86::GR32_ADRegClass,
9626 &X86::GR32_ArgRefRegClass,
9627 &X86::GR32_BPSPRegClass,
9628 &X86::GR32_BSIRegClass,
9629 &X86::GR32_CBRegClass,
9630 &X86::GR32_DCRegClass,
9631 &X86::GR32_DIBPRegClass,
9632 &X86::GR32_SIDIRegClass,
9633 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
9634 &X86::CCRRegClass,
9635 &X86::DFCCRRegClass,
9636 &X86::GR32_ABCD_and_GR32_BSIRegClass,
9637 &X86::GR32_AD_and_GR32_ArgRefRegClass,
9638 &X86::GR32_ArgRef_and_GR32_CBRegClass,
9639 &X86::GR32_BPSP_and_GR32_DIBPRegClass,
9640 &X86::GR32_BPSP_and_GR32_TCRegClass,
9641 &X86::GR32_BSI_and_GR32_SIDIRegClass,
9642 &X86::GR32_DIBP_and_GR32_SIDIRegClass,
9643 &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
9644 &X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
9645 &X86::RFP64RegClass,
9646 &X86::GR64RegClass,
9647 &X86::FR64XRegClass,
9648 &X86::GR64_with_sub_8bitRegClass,
9649 &X86::GR64_NOSPRegClass,
9650 &X86::GR64_NOREX2RegClass,
9651 &X86::CONTROL_REGRegClass,
9652 &X86::FR64RegClass,
9653 &X86::GR64_with_sub_16bit_in_GR16_NOREX2RegClass,
9654 &X86::GR64_NOREX2_NOSPRegClass,
9655 &X86::GR64PLTSafeRegClass,
9656 &X86::GR64_TCRegClass,
9657 &X86::GR64_NOREXRegClass,
9658 &X86::GR64_TCW64RegClass,
9659 &X86::GR64_TC_with_sub_8bitRegClass,
9660 &X86::GR64_NOREX2_NOSP_and_GR64_TCRegClass,
9661 &X86::GR64_TCW64_with_sub_8bitRegClass,
9662 &X86::GR64_TC_and_GR64_TCW64RegClass,
9663 &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
9664 &X86::VK64RegClass,
9665 &X86::VR64RegClass,
9666 &X86::GR64PLTSafe_and_GR64_TCRegClass,
9667 &X86::GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
9668 &X86::GR64_NOREX_NOSPRegClass,
9669 &X86::GR64_NOREX_and_GR64_TCRegClass,
9670 &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
9671 &X86::VK64WMRegClass,
9672 &X86::GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64RegClass,
9673 &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
9674 &X86::GR64PLTSafe_and_GR64_TCW64RegClass,
9675 &X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
9676 &X86::GR64_NOREX_and_GR64_TCW64RegClass,
9677 &X86::GR64_ABCDRegClass,
9678 &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
9679 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
9680 &X86::GR64_ADRegClass,
9681 &X86::GR64_ArgRefRegClass,
9682 &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
9683 &X86::GR64_with_sub_32bit_in_GR32_ArgRefRegClass,
9684 &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
9685 &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
9686 &X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
9687 &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
9688 &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
9689 &X86::GR64_ArgRef_and_GR64_TCRegClass,
9690 &X86::GR64_and_LOW32_ADDR_ACCESSRegClass,
9691 &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass,
9692 &X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRefRegClass,
9693 &X86::GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CBRegClass,
9694 &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass,
9695 &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass,
9696 &X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass,
9697 &X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass,
9698 &X86::RSTRegClass,
9699 &X86::RFP80RegClass,
9700 &X86::RFP80_7RegClass,
9701 &X86::VR128XRegClass,
9702 &X86::VR128RegClass,
9703 &X86::VR256XRegClass,
9704 &X86::VR256RegClass,
9705 &X86::VR512RegClass,
9706 &X86::VR512_0_15RegClass,
9707 &X86::TILERegClass,
9708 };
9709} // end anonymous namespace
9710
9711static const uint8_t CostPerUseTable[] = {
97120, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
9713
9714
9715static const bool InAllocatableClassTable[] = {
9716false, true, true, true, true, true, true, false, true, true, true, true, true, true, false, true, true, false, true, true, true, true, true, true, true, true, true, true, false, false, false, true, true, true, false, false, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, true, false, true, true, true, false, true, true, false, true, true, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };
9717
9718
9719static const TargetRegisterInfoDesc X86RegInfoDesc = { // Extra Descriptors
9720CostPerUseTable, 1, InAllocatableClassTable};
9721
9722unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
9723 static const uint8_t Rows[1][10] = {
9724 { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
9725 };
9726
9727 --IdxA; assert(IdxA < 10); (void) IdxA;
9728 --IdxB; assert(IdxB < 10);
9729 return Rows[0][IdxB];
9730}
9731
9732 struct MaskRolOp {
9733 LaneBitmask Mask;
9734 uint8_t RotateLeft;
9735 };
9736 static const MaskRolOp LaneMaskComposeSequences[] = {
9737 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
9738 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
9739 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
9740 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
9741 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
9742 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10
9743 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 12
9744 };
9745 static const uint8_t CompositeSequences[] = {
9746 0, // to sub_8bit
9747 2, // to sub_8bit_hi
9748 4, // to sub_8bit_hi_phony
9749 0, // to sub_16bit
9750 6, // to sub_16bit_hi
9751 0, // to sub_32bit
9752 8, // to sub_mask_0
9753 10, // to sub_mask_1
9754 12, // to sub_xmm
9755 0 // to sub_ymm
9756 };
9757
9758LaneBitmask X86GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
9759 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
9760 LaneBitmask Result;
9761 for (const MaskRolOp *Ops =
9762 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
9763 Ops->Mask.any(); ++Ops) {
9764 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
9765 if (unsigned S = Ops->RotateLeft)
9766 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
9767 else
9768 Result |= LaneBitmask(M);
9769 }
9770 return Result;
9771}
9772
9773LaneBitmask X86GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
9774 LaneMask &= getSubRegIndexLaneMask(IdxA);
9775 --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
9776 LaneBitmask Result;
9777 for (const MaskRolOp *Ops =
9778 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
9779 Ops->Mask.any(); ++Ops) {
9780 LaneBitmask::Type M = LaneMask.getAsInteger();
9781 if (unsigned S = Ops->RotateLeft)
9782 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
9783 else
9784 Result |= LaneBitmask(M);
9785 }
9786 return Result;
9787}
9788
9789const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
9790 static const uint8_t Table[134][10] = {
9791 { // GR8
9792 0, // sub_8bit
9793 0, // sub_8bit_hi
9794 0, // sub_8bit_hi_phony
9795 0, // sub_16bit
9796 0, // sub_16bit_hi
9797 0, // sub_32bit
9798 0, // sub_mask_0
9799 0, // sub_mask_1
9800 0, // sub_xmm
9801 0, // sub_ymm
9802 },
9803 { // GRH8
9804 0, // sub_8bit
9805 0, // sub_8bit_hi
9806 0, // sub_8bit_hi_phony
9807 0, // sub_16bit
9808 0, // sub_16bit_hi
9809 0, // sub_32bit
9810 0, // sub_mask_0
9811 0, // sub_mask_1
9812 0, // sub_xmm
9813 0, // sub_ymm
9814 },
9815 { // GR8_NOREX2
9816 0, // sub_8bit
9817 0, // sub_8bit_hi
9818 0, // sub_8bit_hi_phony
9819 0, // sub_16bit
9820 0, // sub_16bit_hi
9821 0, // sub_32bit
9822 0, // sub_mask_0
9823 0, // sub_mask_1
9824 0, // sub_xmm
9825 0, // sub_ymm
9826 },
9827 { // GR8_NOREX
9828 0, // sub_8bit
9829 0, // sub_8bit_hi
9830 0, // sub_8bit_hi_phony
9831 0, // sub_16bit
9832 0, // sub_16bit_hi
9833 0, // sub_32bit
9834 0, // sub_mask_0
9835 0, // sub_mask_1
9836 0, // sub_xmm
9837 0, // sub_ymm
9838 },
9839 { // GR8_ABCD_H
9840 0, // sub_8bit
9841 0, // sub_8bit_hi
9842 0, // sub_8bit_hi_phony
9843 0, // sub_16bit
9844 0, // sub_16bit_hi
9845 0, // sub_32bit
9846 0, // sub_mask_0
9847 0, // sub_mask_1
9848 0, // sub_xmm
9849 0, // sub_ymm
9850 },
9851 { // GR8_ABCD_L
9852 0, // sub_8bit
9853 0, // sub_8bit_hi
9854 0, // sub_8bit_hi_phony
9855 0, // sub_16bit
9856 0, // sub_16bit_hi
9857 0, // sub_32bit
9858 0, // sub_mask_0
9859 0, // sub_mask_1
9860 0, // sub_xmm
9861 0, // sub_ymm
9862 },
9863 { // GRH16
9864 0, // sub_8bit
9865 0, // sub_8bit_hi
9866 0, // sub_8bit_hi_phony
9867 0, // sub_16bit
9868 0, // sub_16bit_hi
9869 0, // sub_32bit
9870 0, // sub_mask_0
9871 0, // sub_mask_1
9872 0, // sub_xmm
9873 0, // sub_ymm
9874 },
9875 { // GR16
9876 8, // sub_8bit -> GR16
9877 22, // sub_8bit_hi -> GR16_ABCD
9878 0, // sub_8bit_hi_phony
9879 0, // sub_16bit
9880 0, // sub_16bit_hi
9881 0, // sub_32bit
9882 0, // sub_mask_0
9883 0, // sub_mask_1
9884 0, // sub_xmm
9885 0, // sub_ymm
9886 },
9887 { // GR16_NOREX2
9888 9, // sub_8bit -> GR16_NOREX2
9889 22, // sub_8bit_hi -> GR16_ABCD
9890 0, // sub_8bit_hi_phony
9891 0, // sub_16bit
9892 0, // sub_16bit_hi
9893 0, // sub_32bit
9894 0, // sub_mask_0
9895 0, // sub_mask_1
9896 0, // sub_xmm
9897 0, // sub_ymm
9898 },
9899 { // GR16_NOREX
9900 10, // sub_8bit -> GR16_NOREX
9901 22, // sub_8bit_hi -> GR16_ABCD
9902 0, // sub_8bit_hi_phony
9903 0, // sub_16bit
9904 0, // sub_16bit_hi
9905 0, // sub_32bit
9906 0, // sub_mask_0
9907 0, // sub_mask_1
9908 0, // sub_xmm
9909 0, // sub_ymm
9910 },
9911 { // VK1
9912 0, // sub_8bit
9913 0, // sub_8bit_hi
9914 0, // sub_8bit_hi_phony
9915 0, // sub_16bit
9916 0, // sub_16bit_hi
9917 0, // sub_32bit
9918 0, // sub_mask_0
9919 0, // sub_mask_1
9920 0, // sub_xmm
9921 0, // sub_ymm
9922 },
9923 { // VK16
9924 0, // sub_8bit
9925 0, // sub_8bit_hi
9926 0, // sub_8bit_hi_phony
9927 0, // sub_16bit
9928 0, // sub_16bit_hi
9929 0, // sub_32bit
9930 0, // sub_mask_0
9931 0, // sub_mask_1
9932 0, // sub_xmm
9933 0, // sub_ymm
9934 },
9935 { // VK2
9936 0, // sub_8bit
9937 0, // sub_8bit_hi
9938 0, // sub_8bit_hi_phony
9939 0, // sub_16bit
9940 0, // sub_16bit_hi
9941 0, // sub_32bit
9942 0, // sub_mask_0
9943 0, // sub_mask_1
9944 0, // sub_xmm
9945 0, // sub_ymm
9946 },
9947 { // VK4
9948 0, // sub_8bit
9949 0, // sub_8bit_hi
9950 0, // sub_8bit_hi_phony
9951 0, // sub_16bit
9952 0, // sub_16bit_hi
9953 0, // sub_32bit
9954 0, // sub_mask_0
9955 0, // sub_mask_1
9956 0, // sub_xmm
9957 0, // sub_ymm
9958 },
9959 { // VK8
9960 0, // sub_8bit
9961 0, // sub_8bit_hi
9962 0, // sub_8bit_hi_phony
9963 0, // sub_16bit
9964 0, // sub_16bit_hi
9965 0, // sub_32bit
9966 0, // sub_mask_0
9967 0, // sub_mask_1
9968 0, // sub_xmm
9969 0, // sub_ymm
9970 },
9971 { // VK16WM
9972 0, // sub_8bit
9973 0, // sub_8bit_hi
9974 0, // sub_8bit_hi_phony
9975 0, // sub_16bit
9976 0, // sub_16bit_hi
9977 0, // sub_32bit
9978 0, // sub_mask_0
9979 0, // sub_mask_1
9980 0, // sub_xmm
9981 0, // sub_ymm
9982 },
9983 { // VK1WM
9984 0, // sub_8bit
9985 0, // sub_8bit_hi
9986 0, // sub_8bit_hi_phony
9987 0, // sub_16bit
9988 0, // sub_16bit_hi
9989 0, // sub_32bit
9990 0, // sub_mask_0
9991 0, // sub_mask_1
9992 0, // sub_xmm
9993 0, // sub_ymm
9994 },
9995 { // VK2WM
9996 0, // sub_8bit
9997 0, // sub_8bit_hi
9998 0, // sub_8bit_hi_phony
9999 0, // sub_16bit
10000 0, // sub_16bit_hi
10001 0, // sub_32bit
10002 0, // sub_mask_0
10003 0, // sub_mask_1
10004 0, // sub_xmm
10005 0, // sub_ymm
10006 },
10007 { // VK4WM
10008 0, // sub_8bit
10009 0, // sub_8bit_hi
10010 0, // sub_8bit_hi_phony
10011 0, // sub_16bit
10012 0, // sub_16bit_hi
10013 0, // sub_32bit
10014 0, // sub_mask_0
10015 0, // sub_mask_1
10016 0, // sub_xmm
10017 0, // sub_ymm
10018 },
10019 { // VK8WM
10020 0, // sub_8bit
10021 0, // sub_8bit_hi
10022 0, // sub_8bit_hi_phony
10023 0, // sub_16bit
10024 0, // sub_16bit_hi
10025 0, // sub_32bit
10026 0, // sub_mask_0
10027 0, // sub_mask_1
10028 0, // sub_xmm
10029 0, // sub_ymm
10030 },
10031 { // SEGMENT_REG
10032 0, // sub_8bit
10033 0, // sub_8bit_hi
10034 0, // sub_8bit_hi_phony
10035 0, // sub_16bit
10036 0, // sub_16bit_hi
10037 0, // sub_32bit
10038 0, // sub_mask_0
10039 0, // sub_mask_1
10040 0, // sub_xmm
10041 0, // sub_ymm
10042 },
10043 { // GR16_ABCD
10044 22, // sub_8bit -> GR16_ABCD
10045 22, // sub_8bit_hi -> GR16_ABCD
10046 0, // sub_8bit_hi_phony
10047 0, // sub_16bit
10048 0, // sub_16bit_hi
10049 0, // sub_32bit
10050 0, // sub_mask_0
10051 0, // sub_mask_1
10052 0, // sub_xmm
10053 0, // sub_ymm
10054 },
10055 { // FPCCR
10056 0, // sub_8bit
10057 0, // sub_8bit_hi
10058 0, // sub_8bit_hi_phony
10059 0, // sub_16bit
10060 0, // sub_16bit_hi
10061 0, // sub_32bit
10062 0, // sub_mask_0
10063 0, // sub_mask_1
10064 0, // sub_xmm
10065 0, // sub_ymm
10066 },
10067 { // FR16X
10068 0, // sub_8bit
10069 0, // sub_8bit_hi
10070 0, // sub_8bit_hi_phony
10071 0, // sub_16bit
10072 0, // sub_16bit_hi
10073 0, // sub_32bit
10074 0, // sub_mask_0
10075 0, // sub_mask_1
10076 0, // sub_xmm
10077 0, // sub_ymm
10078 },
10079 { // FR16
10080 0, // sub_8bit
10081 0, // sub_8bit_hi
10082 0, // sub_8bit_hi_phony
10083 0, // sub_16bit
10084 0, // sub_16bit_hi
10085 0, // sub_32bit
10086 0, // sub_mask_0
10087 0, // sub_mask_1
10088 0, // sub_xmm
10089 0, // sub_ymm
10090 },
10091 { // VK16PAIR
10092 0, // sub_8bit
10093 0, // sub_8bit_hi
10094 0, // sub_8bit_hi_phony
10095 0, // sub_16bit
10096 0, // sub_16bit_hi
10097 0, // sub_32bit
10098 26, // sub_mask_0 -> VK16PAIR
10099 26, // sub_mask_1 -> VK16PAIR
10100 0, // sub_xmm
10101 0, // sub_ymm
10102 },
10103 { // VK1PAIR
10104 0, // sub_8bit
10105 0, // sub_8bit_hi
10106 0, // sub_8bit_hi_phony
10107 0, // sub_16bit
10108 0, // sub_16bit_hi
10109 0, // sub_32bit
10110 27, // sub_mask_0 -> VK1PAIR
10111 27, // sub_mask_1 -> VK1PAIR
10112 0, // sub_xmm
10113 0, // sub_ymm
10114 },
10115 { // VK2PAIR
10116 0, // sub_8bit
10117 0, // sub_8bit_hi
10118 0, // sub_8bit_hi_phony
10119 0, // sub_16bit
10120 0, // sub_16bit_hi
10121 0, // sub_32bit
10122 28, // sub_mask_0 -> VK2PAIR
10123 28, // sub_mask_1 -> VK2PAIR
10124 0, // sub_xmm
10125 0, // sub_ymm
10126 },
10127 { // VK4PAIR
10128 0, // sub_8bit
10129 0, // sub_8bit_hi
10130 0, // sub_8bit_hi_phony
10131 0, // sub_16bit
10132 0, // sub_16bit_hi
10133 0, // sub_32bit
10134 29, // sub_mask_0 -> VK4PAIR
10135 29, // sub_mask_1 -> VK4PAIR
10136 0, // sub_xmm
10137 0, // sub_ymm
10138 },
10139 { // VK8PAIR
10140 0, // sub_8bit
10141 0, // sub_8bit_hi
10142 0, // sub_8bit_hi_phony
10143 0, // sub_16bit
10144 0, // sub_16bit_hi
10145 0, // sub_32bit
10146 30, // sub_mask_0 -> VK8PAIR
10147 30, // sub_mask_1 -> VK8PAIR
10148 0, // sub_xmm
10149 0, // sub_ymm
10150 },
10151 { // VK1PAIR_with_sub_mask_0_in_VK1WM
10152 0, // sub_8bit
10153 0, // sub_8bit_hi
10154 0, // sub_8bit_hi_phony
10155 0, // sub_16bit
10156 0, // sub_16bit_hi
10157 0, // sub_32bit
10158 31, // sub_mask_0 -> VK1PAIR_with_sub_mask_0_in_VK1WM
10159 31, // sub_mask_1 -> VK1PAIR_with_sub_mask_0_in_VK1WM
10160 0, // sub_xmm
10161 0, // sub_ymm
10162 },
10163 { // LOW32_ADDR_ACCESS_RBP
10164 34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
10165 49, // sub_8bit_hi -> GR32_ABCD
10166 0, // sub_8bit_hi_phony
10167 32, // sub_16bit -> LOW32_ADDR_ACCESS_RBP
10168 0, // sub_16bit_hi
10169 60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
10170 0, // sub_mask_0
10171 0, // sub_mask_1
10172 0, // sub_xmm
10173 0, // sub_ymm
10174 },
10175 { // LOW32_ADDR_ACCESS
10176 36, // sub_8bit -> GR32
10177 49, // sub_8bit_hi -> GR32_ABCD
10178 0, // sub_8bit_hi_phony
10179 33, // sub_16bit -> LOW32_ADDR_ACCESS
10180 0, // sub_16bit_hi
10181 71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
10182 0, // sub_mask_0
10183 0, // sub_mask_1
10184 0, // sub_xmm
10185 0, // sub_ymm
10186 },
10187 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
10188 34, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
10189 49, // sub_8bit_hi -> GR32_ABCD
10190 0, // sub_8bit_hi_phony
10191 34, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
10192 0, // sub_16bit_hi
10193 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10194 0, // sub_mask_0
10195 0, // sub_mask_1
10196 0, // sub_xmm
10197 0, // sub_ymm
10198 },
10199 { // FR32X
10200 0, // sub_8bit
10201 0, // sub_8bit_hi
10202 0, // sub_8bit_hi_phony
10203 0, // sub_16bit
10204 0, // sub_16bit_hi
10205 0, // sub_32bit
10206 0, // sub_mask_0
10207 0, // sub_mask_1
10208 0, // sub_xmm
10209 0, // sub_ymm
10210 },
10211 { // GR32
10212 36, // sub_8bit -> GR32
10213 49, // sub_8bit_hi -> GR32_ABCD
10214 0, // sub_8bit_hi_phony
10215 36, // sub_16bit -> GR32
10216 0, // sub_16bit_hi
10217 0, // sub_32bit
10218 0, // sub_mask_0
10219 0, // sub_mask_1
10220 0, // sub_xmm
10221 0, // sub_ymm
10222 },
10223 { // GR32_NOSP
10224 37, // sub_8bit -> GR32_NOSP
10225 49, // sub_8bit_hi -> GR32_ABCD
10226 0, // sub_8bit_hi_phony
10227 37, // sub_16bit -> GR32_NOSP
10228 0, // sub_16bit_hi
10229 0, // sub_32bit
10230 0, // sub_mask_0
10231 0, // sub_mask_1
10232 0, // sub_xmm
10233 0, // sub_ymm
10234 },
10235 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
10236 38, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
10237 49, // sub_8bit_hi -> GR32_ABCD
10238 0, // sub_8bit_hi_phony
10239 38, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
10240 0, // sub_16bit_hi
10241 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10242 0, // sub_mask_0
10243 0, // sub_mask_1
10244 0, // sub_xmm
10245 0, // sub_ymm
10246 },
10247 { // DEBUG_REG
10248 0, // sub_8bit
10249 0, // sub_8bit_hi
10250 0, // sub_8bit_hi_phony
10251 0, // sub_16bit
10252 0, // sub_16bit_hi
10253 0, // sub_32bit
10254 0, // sub_mask_0
10255 0, // sub_mask_1
10256 0, // sub_xmm
10257 0, // sub_ymm
10258 },
10259 { // FR32
10260 0, // sub_8bit
10261 0, // sub_8bit_hi
10262 0, // sub_8bit_hi_phony
10263 0, // sub_16bit
10264 0, // sub_16bit_hi
10265 0, // sub_32bit
10266 0, // sub_mask_0
10267 0, // sub_mask_1
10268 0, // sub_xmm
10269 0, // sub_ymm
10270 },
10271 { // GR32_NOREX2
10272 41, // sub_8bit -> GR32_NOREX2
10273 49, // sub_8bit_hi -> GR32_ABCD
10274 0, // sub_8bit_hi_phony
10275 41, // sub_16bit -> GR32_NOREX2
10276 0, // sub_16bit_hi
10277 0, // sub_32bit
10278 0, // sub_mask_0
10279 0, // sub_mask_1
10280 0, // sub_xmm
10281 0, // sub_ymm
10282 },
10283 { // GR32_NOREX2_NOSP
10284 42, // sub_8bit -> GR32_NOREX2_NOSP
10285 49, // sub_8bit_hi -> GR32_ABCD
10286 0, // sub_8bit_hi_phony
10287 42, // sub_16bit -> GR32_NOREX2_NOSP
10288 0, // sub_16bit_hi
10289 0, // sub_32bit
10290 0, // sub_mask_0
10291 0, // sub_mask_1
10292 0, // sub_xmm
10293 0, // sub_ymm
10294 },
10295 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
10296 43, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
10297 49, // sub_8bit_hi -> GR32_ABCD
10298 0, // sub_8bit_hi_phony
10299 43, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
10300 0, // sub_16bit_hi
10301 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10302 0, // sub_mask_0
10303 0, // sub_mask_1
10304 0, // sub_xmm
10305 0, // sub_ymm
10306 },
10307 { // GR32_NOREX
10308 44, // sub_8bit -> GR32_NOREX
10309 49, // sub_8bit_hi -> GR32_ABCD
10310 0, // sub_8bit_hi_phony
10311 44, // sub_16bit -> GR32_NOREX
10312 0, // sub_16bit_hi
10313 0, // sub_32bit
10314 0, // sub_mask_0
10315 0, // sub_mask_1
10316 0, // sub_xmm
10317 0, // sub_ymm
10318 },
10319 { // VK32
10320 0, // sub_8bit
10321 0, // sub_8bit_hi
10322 0, // sub_8bit_hi_phony
10323 0, // sub_16bit
10324 0, // sub_16bit_hi
10325 0, // sub_32bit
10326 0, // sub_mask_0
10327 0, // sub_mask_1
10328 0, // sub_xmm
10329 0, // sub_ymm
10330 },
10331 { // GR32_NOREX_NOSP
10332 46, // sub_8bit -> GR32_NOREX_NOSP
10333 49, // sub_8bit_hi -> GR32_ABCD
10334 0, // sub_8bit_hi_phony
10335 46, // sub_16bit -> GR32_NOREX_NOSP
10336 0, // sub_16bit_hi
10337 0, // sub_32bit
10338 0, // sub_mask_0
10339 0, // sub_mask_1
10340 0, // sub_xmm
10341 0, // sub_ymm
10342 },
10343 { // RFP32
10344 0, // sub_8bit
10345 0, // sub_8bit_hi
10346 0, // sub_8bit_hi_phony
10347 0, // sub_16bit
10348 0, // sub_16bit_hi
10349 0, // sub_32bit
10350 0, // sub_mask_0
10351 0, // sub_mask_1
10352 0, // sub_xmm
10353 0, // sub_ymm
10354 },
10355 { // VK32WM
10356 0, // sub_8bit
10357 0, // sub_8bit_hi
10358 0, // sub_8bit_hi_phony
10359 0, // sub_16bit
10360 0, // sub_16bit_hi
10361 0, // sub_32bit
10362 0, // sub_mask_0
10363 0, // sub_mask_1
10364 0, // sub_xmm
10365 0, // sub_ymm
10366 },
10367 { // GR32_ABCD
10368 49, // sub_8bit -> GR32_ABCD
10369 49, // sub_8bit_hi -> GR32_ABCD
10370 0, // sub_8bit_hi_phony
10371 49, // sub_16bit -> GR32_ABCD
10372 0, // sub_16bit_hi
10373 0, // sub_32bit
10374 0, // sub_mask_0
10375 0, // sub_mask_1
10376 0, // sub_xmm
10377 0, // sub_ymm
10378 },
10379 { // GR32_TC
10380 50, // sub_8bit -> GR32_TC
10381 51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
10382 0, // sub_8bit_hi_phony
10383 50, // sub_16bit -> GR32_TC
10384 0, // sub_16bit_hi
10385 0, // sub_32bit
10386 0, // sub_mask_0
10387 0, // sub_mask_1
10388 0, // sub_xmm
10389 0, // sub_ymm
10390 },
10391 { // GR32_ABCD_and_GR32_TC
10392 51, // sub_8bit -> GR32_ABCD_and_GR32_TC
10393 51, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
10394 0, // sub_8bit_hi_phony
10395 51, // sub_16bit -> GR32_ABCD_and_GR32_TC
10396 0, // sub_16bit_hi
10397 0, // sub_32bit
10398 0, // sub_mask_0
10399 0, // sub_mask_1
10400 0, // sub_xmm
10401 0, // sub_ymm
10402 },
10403 { // GR32_AD
10404 52, // sub_8bit -> GR32_AD
10405 52, // sub_8bit_hi -> GR32_AD
10406 0, // sub_8bit_hi_phony
10407 52, // sub_16bit -> GR32_AD
10408 0, // sub_16bit_hi
10409 0, // sub_32bit
10410 0, // sub_mask_0
10411 0, // sub_mask_1
10412 0, // sub_xmm
10413 0, // sub_ymm
10414 },
10415 { // GR32_ArgRef
10416 53, // sub_8bit -> GR32_ArgRef
10417 53, // sub_8bit_hi -> GR32_ArgRef
10418 0, // sub_8bit_hi_phony
10419 53, // sub_16bit -> GR32_ArgRef
10420 0, // sub_16bit_hi
10421 0, // sub_32bit
10422 0, // sub_mask_0
10423 0, // sub_mask_1
10424 0, // sub_xmm
10425 0, // sub_ymm
10426 },
10427 { // GR32_BPSP
10428 54, // sub_8bit -> GR32_BPSP
10429 0, // sub_8bit_hi
10430 0, // sub_8bit_hi_phony
10431 54, // sub_16bit -> GR32_BPSP
10432 0, // sub_16bit_hi
10433 0, // sub_32bit
10434 0, // sub_mask_0
10435 0, // sub_mask_1
10436 0, // sub_xmm
10437 0, // sub_ymm
10438 },
10439 { // GR32_BSI
10440 55, // sub_8bit -> GR32_BSI
10441 63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
10442 0, // sub_8bit_hi_phony
10443 55, // sub_16bit -> GR32_BSI
10444 0, // sub_16bit_hi
10445 0, // sub_32bit
10446 0, // sub_mask_0
10447 0, // sub_mask_1
10448 0, // sub_xmm
10449 0, // sub_ymm
10450 },
10451 { // GR32_CB
10452 56, // sub_8bit -> GR32_CB
10453 56, // sub_8bit_hi -> GR32_CB
10454 0, // sub_8bit_hi_phony
10455 56, // sub_16bit -> GR32_CB
10456 0, // sub_16bit_hi
10457 0, // sub_32bit
10458 0, // sub_mask_0
10459 0, // sub_mask_1
10460 0, // sub_xmm
10461 0, // sub_ymm
10462 },
10463 { // GR32_DC
10464 57, // sub_8bit -> GR32_DC
10465 57, // sub_8bit_hi -> GR32_DC
10466 0, // sub_8bit_hi_phony
10467 57, // sub_16bit -> GR32_DC
10468 0, // sub_16bit_hi
10469 0, // sub_32bit
10470 0, // sub_mask_0
10471 0, // sub_mask_1
10472 0, // sub_xmm
10473 0, // sub_ymm
10474 },
10475 { // GR32_DIBP
10476 58, // sub_8bit -> GR32_DIBP
10477 0, // sub_8bit_hi
10478 0, // sub_8bit_hi_phony
10479 58, // sub_16bit -> GR32_DIBP
10480 0, // sub_16bit_hi
10481 0, // sub_32bit
10482 0, // sub_mask_0
10483 0, // sub_mask_1
10484 0, // sub_xmm
10485 0, // sub_ymm
10486 },
10487 { // GR32_SIDI
10488 59, // sub_8bit -> GR32_SIDI
10489 0, // sub_8bit_hi
10490 0, // sub_8bit_hi_phony
10491 59, // sub_16bit -> GR32_SIDI
10492 0, // sub_16bit_hi
10493 0, // sub_32bit
10494 0, // sub_mask_0
10495 0, // sub_mask_1
10496 0, // sub_xmm
10497 0, // sub_ymm
10498 },
10499 { // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
10500 70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10501 0, // sub_8bit_hi
10502 0, // sub_8bit_hi_phony
10503 60, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
10504 0, // sub_16bit_hi
10505 60, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
10506 0, // sub_mask_0
10507 0, // sub_mask_1
10508 0, // sub_xmm
10509 0, // sub_ymm
10510 },
10511 { // CCR
10512 0, // sub_8bit
10513 0, // sub_8bit_hi
10514 0, // sub_8bit_hi_phony
10515 0, // sub_16bit
10516 0, // sub_16bit_hi
10517 0, // sub_32bit
10518 0, // sub_mask_0
10519 0, // sub_mask_1
10520 0, // sub_xmm
10521 0, // sub_ymm
10522 },
10523 { // DFCCR
10524 0, // sub_8bit
10525 0, // sub_8bit_hi
10526 0, // sub_8bit_hi_phony
10527 0, // sub_16bit
10528 0, // sub_16bit_hi
10529 0, // sub_32bit
10530 0, // sub_mask_0
10531 0, // sub_mask_1
10532 0, // sub_xmm
10533 0, // sub_ymm
10534 },
10535 { // GR32_ABCD_and_GR32_BSI
10536 63, // sub_8bit -> GR32_ABCD_and_GR32_BSI
10537 63, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
10538 0, // sub_8bit_hi_phony
10539 63, // sub_16bit -> GR32_ABCD_and_GR32_BSI
10540 0, // sub_16bit_hi
10541 0, // sub_32bit
10542 0, // sub_mask_0
10543 0, // sub_mask_1
10544 0, // sub_xmm
10545 0, // sub_ymm
10546 },
10547 { // GR32_AD_and_GR32_ArgRef
10548 64, // sub_8bit -> GR32_AD_and_GR32_ArgRef
10549 64, // sub_8bit_hi -> GR32_AD_and_GR32_ArgRef
10550 0, // sub_8bit_hi_phony
10551 64, // sub_16bit -> GR32_AD_and_GR32_ArgRef
10552 0, // sub_16bit_hi
10553 0, // sub_32bit
10554 0, // sub_mask_0
10555 0, // sub_mask_1
10556 0, // sub_xmm
10557 0, // sub_ymm
10558 },
10559 { // GR32_ArgRef_and_GR32_CB
10560 65, // sub_8bit -> GR32_ArgRef_and_GR32_CB
10561 65, // sub_8bit_hi -> GR32_ArgRef_and_GR32_CB
10562 0, // sub_8bit_hi_phony
10563 65, // sub_16bit -> GR32_ArgRef_and_GR32_CB
10564 0, // sub_16bit_hi
10565 0, // sub_32bit
10566 0, // sub_mask_0
10567 0, // sub_mask_1
10568 0, // sub_xmm
10569 0, // sub_ymm
10570 },
10571 { // GR32_BPSP_and_GR32_DIBP
10572 66, // sub_8bit -> GR32_BPSP_and_GR32_DIBP
10573 0, // sub_8bit_hi
10574 0, // sub_8bit_hi_phony
10575 66, // sub_16bit -> GR32_BPSP_and_GR32_DIBP
10576 0, // sub_16bit_hi
10577 0, // sub_32bit
10578 0, // sub_mask_0
10579 0, // sub_mask_1
10580 0, // sub_xmm
10581 0, // sub_ymm
10582 },
10583 { // GR32_BPSP_and_GR32_TC
10584 67, // sub_8bit -> GR32_BPSP_and_GR32_TC
10585 0, // sub_8bit_hi
10586 0, // sub_8bit_hi_phony
10587 67, // sub_16bit -> GR32_BPSP_and_GR32_TC
10588 0, // sub_16bit_hi
10589 0, // sub_32bit
10590 0, // sub_mask_0
10591 0, // sub_mask_1
10592 0, // sub_xmm
10593 0, // sub_ymm
10594 },
10595 { // GR32_BSI_and_GR32_SIDI
10596 68, // sub_8bit -> GR32_BSI_and_GR32_SIDI
10597 0, // sub_8bit_hi
10598 0, // sub_8bit_hi_phony
10599 68, // sub_16bit -> GR32_BSI_and_GR32_SIDI
10600 0, // sub_16bit_hi
10601 0, // sub_32bit
10602 0, // sub_mask_0
10603 0, // sub_mask_1
10604 0, // sub_xmm
10605 0, // sub_ymm
10606 },
10607 { // GR32_DIBP_and_GR32_SIDI
10608 69, // sub_8bit -> GR32_DIBP_and_GR32_SIDI
10609 0, // sub_8bit_hi
10610 0, // sub_8bit_hi_phony
10611 69, // sub_16bit -> GR32_DIBP_and_GR32_SIDI
10612 0, // sub_16bit_hi
10613 0, // sub_32bit
10614 0, // sub_mask_0
10615 0, // sub_mask_1
10616 0, // sub_xmm
10617 0, // sub_ymm
10618 },
10619 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10620 70, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10621 0, // sub_8bit_hi
10622 0, // sub_8bit_hi_phony
10623 70, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10624 0, // sub_16bit_hi
10625 70, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
10626 0, // sub_mask_0
10627 0, // sub_mask_1
10628 0, // sub_xmm
10629 0, // sub_ymm
10630 },
10631 { // LOW32_ADDR_ACCESS_with_sub_32bit
10632 0, // sub_8bit
10633 0, // sub_8bit_hi
10634 0, // sub_8bit_hi_phony
10635 71, // sub_16bit -> LOW32_ADDR_ACCESS_with_sub_32bit
10636 0, // sub_16bit_hi
10637 71, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
10638 0, // sub_mask_0
10639 0, // sub_mask_1
10640 0, // sub_xmm
10641 0, // sub_ymm
10642 },
10643 { // RFP64
10644 0, // sub_8bit
10645 0, // sub_8bit_hi
10646 0, // sub_8bit_hi_phony
10647 0, // sub_16bit
10648 0, // sub_16bit_hi
10649 0, // sub_32bit
10650 0, // sub_mask_0
10651 0, // sub_mask_1
10652 0, // sub_xmm
10653 0, // sub_ymm
10654 },
10655 { // GR64
10656 75, // sub_8bit -> GR64_with_sub_8bit
10657 104, // sub_8bit_hi -> GR64_ABCD
10658 0, // sub_8bit_hi_phony
10659 73, // sub_16bit -> GR64
10660 0, // sub_16bit_hi
10661 73, // sub_32bit -> GR64
10662 0, // sub_mask_0
10663 0, // sub_mask_1
10664 0, // sub_xmm
10665 0, // sub_ymm
10666 },
10667 { // FR64X
10668 0, // sub_8bit
10669 0, // sub_8bit_hi
10670 0, // sub_8bit_hi_phony
10671 0, // sub_16bit
10672 0, // sub_16bit_hi
10673 0, // sub_32bit
10674 0, // sub_mask_0
10675 0, // sub_mask_1
10676 0, // sub_xmm
10677 0, // sub_ymm
10678 },
10679 { // GR64_with_sub_8bit
10680 75, // sub_8bit -> GR64_with_sub_8bit
10681 104, // sub_8bit_hi -> GR64_ABCD
10682 0, // sub_8bit_hi_phony
10683 75, // sub_16bit -> GR64_with_sub_8bit
10684 0, // sub_16bit_hi
10685 75, // sub_32bit -> GR64_with_sub_8bit
10686 0, // sub_mask_0
10687 0, // sub_mask_1
10688 0, // sub_xmm
10689 0, // sub_ymm
10690 },
10691 { // GR64_NOSP
10692 76, // sub_8bit -> GR64_NOSP
10693 104, // sub_8bit_hi -> GR64_ABCD
10694 0, // sub_8bit_hi_phony
10695 76, // sub_16bit -> GR64_NOSP
10696 0, // sub_16bit_hi
10697 76, // sub_32bit -> GR64_NOSP
10698 0, // sub_mask_0
10699 0, // sub_mask_1
10700 0, // sub_xmm
10701 0, // sub_ymm
10702 },
10703 { // GR64_NOREX2
10704 80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
10705 104, // sub_8bit_hi -> GR64_ABCD
10706 0, // sub_8bit_hi_phony
10707 77, // sub_16bit -> GR64_NOREX2
10708 0, // sub_16bit_hi
10709 77, // sub_32bit -> GR64_NOREX2
10710 0, // sub_mask_0
10711 0, // sub_mask_1
10712 0, // sub_xmm
10713 0, // sub_ymm
10714 },
10715 { // CONTROL_REG
10716 0, // sub_8bit
10717 0, // sub_8bit_hi
10718 0, // sub_8bit_hi_phony
10719 0, // sub_16bit
10720 0, // sub_16bit_hi
10721 0, // sub_32bit
10722 0, // sub_mask_0
10723 0, // sub_mask_1
10724 0, // sub_xmm
10725 0, // sub_ymm
10726 },
10727 { // FR64
10728 0, // sub_8bit
10729 0, // sub_8bit_hi
10730 0, // sub_8bit_hi_phony
10731 0, // sub_16bit
10732 0, // sub_16bit_hi
10733 0, // sub_32bit
10734 0, // sub_mask_0
10735 0, // sub_mask_1
10736 0, // sub_xmm
10737 0, // sub_ymm
10738 },
10739 { // GR64_with_sub_16bit_in_GR16_NOREX2
10740 80, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX2
10741 104, // sub_8bit_hi -> GR64_ABCD
10742 0, // sub_8bit_hi_phony
10743 80, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX2
10744 0, // sub_16bit_hi
10745 80, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX2
10746 0, // sub_mask_0
10747 0, // sub_mask_1
10748 0, // sub_xmm
10749 0, // sub_ymm
10750 },
10751 { // GR64_NOREX2_NOSP
10752 81, // sub_8bit -> GR64_NOREX2_NOSP
10753 104, // sub_8bit_hi -> GR64_ABCD
10754 0, // sub_8bit_hi_phony
10755 81, // sub_16bit -> GR64_NOREX2_NOSP
10756 0, // sub_16bit_hi
10757 81, // sub_32bit -> GR64_NOREX2_NOSP
10758 0, // sub_mask_0
10759 0, // sub_mask_1
10760 0, // sub_xmm
10761 0, // sub_ymm
10762 },
10763 { // GR64PLTSafe
10764 82, // sub_8bit -> GR64PLTSafe
10765 104, // sub_8bit_hi -> GR64_ABCD
10766 0, // sub_8bit_hi_phony
10767 82, // sub_16bit -> GR64PLTSafe
10768 0, // sub_16bit_hi
10769 82, // sub_32bit -> GR64PLTSafe
10770 0, // sub_mask_0
10771 0, // sub_mask_1
10772 0, // sub_xmm
10773 0, // sub_ymm
10774 },
10775 { // GR64_TC
10776 86, // sub_8bit -> GR64_TC_with_sub_8bit
10777 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
10778 0, // sub_8bit_hi_phony
10779 83, // sub_16bit -> GR64_TC
10780 0, // sub_16bit_hi
10781 83, // sub_32bit -> GR64_TC
10782 0, // sub_mask_0
10783 0, // sub_mask_1
10784 0, // sub_xmm
10785 0, // sub_ymm
10786 },
10787 { // GR64_NOREX
10788 90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
10789 104, // sub_8bit_hi -> GR64_ABCD
10790 0, // sub_8bit_hi_phony
10791 84, // sub_16bit -> GR64_NOREX
10792 0, // sub_16bit_hi
10793 84, // sub_32bit -> GR64_NOREX
10794 0, // sub_mask_0
10795 0, // sub_mask_1
10796 0, // sub_xmm
10797 0, // sub_ymm
10798 },
10799 { // GR64_TCW64
10800 88, // sub_8bit -> GR64_TCW64_with_sub_8bit
10801 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
10802 0, // sub_8bit_hi_phony
10803 85, // sub_16bit -> GR64_TCW64
10804 0, // sub_16bit_hi
10805 85, // sub_32bit -> GR64_TCW64
10806 0, // sub_mask_0
10807 0, // sub_mask_1
10808 0, // sub_xmm
10809 0, // sub_ymm
10810 },
10811 { // GR64_TC_with_sub_8bit
10812 86, // sub_8bit -> GR64_TC_with_sub_8bit
10813 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
10814 0, // sub_8bit_hi_phony
10815 86, // sub_16bit -> GR64_TC_with_sub_8bit
10816 0, // sub_16bit_hi
10817 86, // sub_32bit -> GR64_TC_with_sub_8bit
10818 0, // sub_mask_0
10819 0, // sub_mask_1
10820 0, // sub_xmm
10821 0, // sub_ymm
10822 },
10823 { // GR64_NOREX2_NOSP_and_GR64_TC
10824 87, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TC
10825 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
10826 0, // sub_8bit_hi_phony
10827 87, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TC
10828 0, // sub_16bit_hi
10829 87, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TC
10830 0, // sub_mask_0
10831 0, // sub_mask_1
10832 0, // sub_xmm
10833 0, // sub_ymm
10834 },
10835 { // GR64_TCW64_with_sub_8bit
10836 88, // sub_8bit -> GR64_TCW64_with_sub_8bit
10837 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
10838 0, // sub_8bit_hi_phony
10839 88, // sub_16bit -> GR64_TCW64_with_sub_8bit
10840 0, // sub_16bit_hi
10841 88, // sub_32bit -> GR64_TCW64_with_sub_8bit
10842 0, // sub_mask_0
10843 0, // sub_mask_1
10844 0, // sub_xmm
10845 0, // sub_ymm
10846 },
10847 { // GR64_TC_and_GR64_TCW64
10848 97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
10849 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
10850 0, // sub_8bit_hi_phony
10851 89, // sub_16bit -> GR64_TC_and_GR64_TCW64
10852 0, // sub_16bit_hi
10853 89, // sub_32bit -> GR64_TC_and_GR64_TCW64
10854 0, // sub_mask_0
10855 0, // sub_mask_1
10856 0, // sub_xmm
10857 0, // sub_ymm
10858 },
10859 { // GR64_with_sub_16bit_in_GR16_NOREX
10860 90, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
10861 104, // sub_8bit_hi -> GR64_ABCD
10862 0, // sub_8bit_hi_phony
10863 90, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX
10864 0, // sub_16bit_hi
10865 90, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX
10866 0, // sub_mask_0
10867 0, // sub_mask_1
10868 0, // sub_xmm
10869 0, // sub_ymm
10870 },
10871 { // VK64
10872 0, // sub_8bit
10873 0, // sub_8bit_hi
10874 0, // sub_8bit_hi_phony
10875 0, // sub_16bit
10876 0, // sub_16bit_hi
10877 0, // sub_32bit
10878 0, // sub_mask_0
10879 0, // sub_mask_1
10880 0, // sub_xmm
10881 0, // sub_ymm
10882 },
10883 { // VR64
10884 0, // sub_8bit
10885 0, // sub_8bit_hi
10886 0, // sub_8bit_hi_phony
10887 0, // sub_16bit
10888 0, // sub_16bit_hi
10889 0, // sub_32bit
10890 0, // sub_mask_0
10891 0, // sub_mask_1
10892 0, // sub_xmm
10893 0, // sub_ymm
10894 },
10895 { // GR64PLTSafe_and_GR64_TC
10896 93, // sub_8bit -> GR64PLTSafe_and_GR64_TC
10897 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
10898 0, // sub_8bit_hi_phony
10899 93, // sub_16bit -> GR64PLTSafe_and_GR64_TC
10900 0, // sub_16bit_hi
10901 93, // sub_32bit -> GR64PLTSafe_and_GR64_TC
10902 0, // sub_mask_0
10903 0, // sub_mask_1
10904 0, // sub_xmm
10905 0, // sub_ymm
10906 },
10907 { // GR64_NOREX2_NOSP_and_GR64_TCW64
10908 94, // sub_8bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
10909 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
10910 0, // sub_8bit_hi_phony
10911 94, // sub_16bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
10912 0, // sub_16bit_hi
10913 94, // sub_32bit -> GR64_NOREX2_NOSP_and_GR64_TCW64
10914 0, // sub_mask_0
10915 0, // sub_mask_1
10916 0, // sub_xmm
10917 0, // sub_ymm
10918 },
10919 { // GR64_NOREX_NOSP
10920 95, // sub_8bit -> GR64_NOREX_NOSP
10921 104, // sub_8bit_hi -> GR64_ABCD
10922 0, // sub_8bit_hi_phony
10923 95, // sub_16bit -> GR64_NOREX_NOSP
10924 0, // sub_16bit_hi
10925 95, // sub_32bit -> GR64_NOREX_NOSP
10926 0, // sub_mask_0
10927 0, // sub_mask_1
10928 0, // sub_xmm
10929 0, // sub_ymm
10930 },
10931 { // GR64_NOREX_and_GR64_TC
10932 100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
10933 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
10934 0, // sub_8bit_hi_phony
10935 96, // sub_16bit -> GR64_NOREX_and_GR64_TC
10936 0, // sub_16bit_hi
10937 96, // sub_32bit -> GR64_NOREX_and_GR64_TC
10938 0, // sub_mask_0
10939 0, // sub_mask_1
10940 0, // sub_xmm
10941 0, // sub_ymm
10942 },
10943 { // GR64_TCW64_and_GR64_TC_with_sub_8bit
10944 97, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
10945 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
10946 0, // sub_8bit_hi_phony
10947 97, // sub_16bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
10948 0, // sub_16bit_hi
10949 97, // sub_32bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
10950 0, // sub_mask_0
10951 0, // sub_mask_1
10952 0, // sub_xmm
10953 0, // sub_ymm
10954 },
10955 { // VK64WM
10956 0, // sub_8bit
10957 0, // sub_8bit_hi
10958 0, // sub_8bit_hi_phony
10959 0, // sub_16bit
10960 0, // sub_16bit_hi
10961 0, // sub_32bit
10962 0, // sub_mask_0
10963 0, // sub_mask_1
10964 0, // sub_xmm
10965 0, // sub_ymm
10966 },
10967 { // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
10968 99, // sub_8bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
10969 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
10970 0, // sub_8bit_hi_phony
10971 99, // sub_16bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
10972 0, // sub_16bit_hi
10973 99, // sub_32bit -> GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
10974 0, // sub_mask_0
10975 0, // sub_mask_1
10976 0, // sub_xmm
10977 0, // sub_ymm
10978 },
10979 { // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
10980 100, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
10981 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
10982 0, // sub_8bit_hi_phony
10983 100, // sub_16bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
10984 0, // sub_16bit_hi
10985 100, // sub_32bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
10986 0, // sub_mask_0
10987 0, // sub_mask_1
10988 0, // sub_xmm
10989 0, // sub_ymm
10990 },
10991 { // GR64PLTSafe_and_GR64_TCW64
10992 101, // sub_8bit -> GR64PLTSafe_and_GR64_TCW64
10993 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
10994 0, // sub_8bit_hi_phony
10995 101, // sub_16bit -> GR64PLTSafe_and_GR64_TCW64
10996 0, // sub_16bit_hi
10997 101, // sub_32bit -> GR64PLTSafe_and_GR64_TCW64
10998 0, // sub_mask_0
10999 0, // sub_mask_1
11000 0, // sub_xmm
11001 0, // sub_ymm
11002 },
11003 { // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
11004 102, // sub_8bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
11005 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11006 0, // sub_8bit_hi_phony
11007 102, // sub_16bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
11008 0, // sub_16bit_hi
11009 102, // sub_32bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
11010 0, // sub_mask_0
11011 0, // sub_mask_1
11012 0, // sub_xmm
11013 0, // sub_ymm
11014 },
11015 { // GR64_NOREX_and_GR64_TCW64
11016 105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
11017 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11018 0, // sub_8bit_hi_phony
11019 103, // sub_16bit -> GR64_NOREX_and_GR64_TCW64
11020 0, // sub_16bit_hi
11021 103, // sub_32bit -> GR64_NOREX_and_GR64_TCW64
11022 0, // sub_mask_0
11023 0, // sub_mask_1
11024 0, // sub_xmm
11025 0, // sub_ymm
11026 },
11027 { // GR64_ABCD
11028 104, // sub_8bit -> GR64_ABCD
11029 104, // sub_8bit_hi -> GR64_ABCD
11030 0, // sub_8bit_hi_phony
11031 104, // sub_16bit -> GR64_ABCD
11032 0, // sub_16bit_hi
11033 104, // sub_32bit -> GR64_ABCD
11034 0, // sub_mask_0
11035 0, // sub_mask_1
11036 0, // sub_xmm
11037 0, // sub_ymm
11038 },
11039 { // GR64_with_sub_32bit_in_GR32_TC
11040 105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
11041 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11042 0, // sub_8bit_hi_phony
11043 105, // sub_16bit -> GR64_with_sub_32bit_in_GR32_TC
11044 0, // sub_16bit_hi
11045 105, // sub_32bit -> GR64_with_sub_32bit_in_GR32_TC
11046 0, // sub_mask_0
11047 0, // sub_mask_1
11048 0, // sub_xmm
11049 0, // sub_ymm
11050 },
11051 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11052 106, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11053 106, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11054 0, // sub_8bit_hi_phony
11055 106, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11056 0, // sub_16bit_hi
11057 106, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
11058 0, // sub_mask_0
11059 0, // sub_mask_1
11060 0, // sub_xmm
11061 0, // sub_ymm
11062 },
11063 { // GR64_AD
11064 107, // sub_8bit -> GR64_AD
11065 107, // sub_8bit_hi -> GR64_AD
11066 0, // sub_8bit_hi_phony
11067 107, // sub_16bit -> GR64_AD
11068 0, // sub_16bit_hi
11069 107, // sub_32bit -> GR64_AD
11070 0, // sub_mask_0
11071 0, // sub_mask_1
11072 0, // sub_xmm
11073 0, // sub_ymm
11074 },
11075 { // GR64_ArgRef
11076 108, // sub_8bit -> GR64_ArgRef
11077 0, // sub_8bit_hi
11078 0, // sub_8bit_hi_phony
11079 108, // sub_16bit -> GR64_ArgRef
11080 0, // sub_16bit_hi
11081 108, // sub_32bit -> GR64_ArgRef
11082 0, // sub_mask_0
11083 0, // sub_mask_1
11084 0, // sub_xmm
11085 0, // sub_ymm
11086 },
11087 { // GR64_and_LOW32_ADDR_ACCESS_RBP
11088 121, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11089 0, // sub_8bit_hi
11090 0, // sub_8bit_hi_phony
11091 109, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
11092 0, // sub_16bit_hi
11093 109, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
11094 0, // sub_mask_0
11095 0, // sub_mask_1
11096 0, // sub_xmm
11097 0, // sub_ymm
11098 },
11099 { // GR64_with_sub_32bit_in_GR32_ArgRef
11100 110, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef
11101 110, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef
11102 0, // sub_8bit_hi_phony
11103 110, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef
11104 0, // sub_16bit_hi
11105 110, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef
11106 0, // sub_mask_0
11107 0, // sub_mask_1
11108 0, // sub_xmm
11109 0, // sub_ymm
11110 },
11111 { // GR64_with_sub_32bit_in_GR32_BPSP
11112 111, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP
11113 0, // sub_8bit_hi
11114 0, // sub_8bit_hi_phony
11115 111, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP
11116 0, // sub_16bit_hi
11117 111, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP
11118 0, // sub_mask_0
11119 0, // sub_mask_1
11120 0, // sub_xmm
11121 0, // sub_ymm
11122 },
11123 { // GR64_with_sub_32bit_in_GR32_BSI
11124 112, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI
11125 118, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11126 0, // sub_8bit_hi_phony
11127 112, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI
11128 0, // sub_16bit_hi
11129 112, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI
11130 0, // sub_mask_0
11131 0, // sub_mask_1
11132 0, // sub_xmm
11133 0, // sub_ymm
11134 },
11135 { // GR64_with_sub_32bit_in_GR32_CB
11136 113, // sub_8bit -> GR64_with_sub_32bit_in_GR32_CB
11137 113, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB
11138 0, // sub_8bit_hi_phony
11139 113, // sub_16bit -> GR64_with_sub_32bit_in_GR32_CB
11140 0, // sub_16bit_hi
11141 113, // sub_32bit -> GR64_with_sub_32bit_in_GR32_CB
11142 0, // sub_mask_0
11143 0, // sub_mask_1
11144 0, // sub_xmm
11145 0, // sub_ymm
11146 },
11147 { // GR64_with_sub_32bit_in_GR32_DIBP
11148 114, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP
11149 0, // sub_8bit_hi
11150 0, // sub_8bit_hi_phony
11151 114, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP
11152 0, // sub_16bit_hi
11153 114, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP
11154 0, // sub_mask_0
11155 0, // sub_mask_1
11156 0, // sub_xmm
11157 0, // sub_ymm
11158 },
11159 { // GR64_with_sub_32bit_in_GR32_SIDI
11160 115, // sub_8bit -> GR64_with_sub_32bit_in_GR32_SIDI
11161 0, // sub_8bit_hi
11162 0, // sub_8bit_hi_phony
11163 115, // sub_16bit -> GR64_with_sub_32bit_in_GR32_SIDI
11164 0, // sub_16bit_hi
11165 115, // sub_32bit -> GR64_with_sub_32bit_in_GR32_SIDI
11166 0, // sub_mask_0
11167 0, // sub_mask_1
11168 0, // sub_xmm
11169 0, // sub_ymm
11170 },
11171 { // GR64_ArgRef_and_GR64_TC
11172 116, // sub_8bit -> GR64_ArgRef_and_GR64_TC
11173 0, // sub_8bit_hi
11174 0, // sub_8bit_hi_phony
11175 116, // sub_16bit -> GR64_ArgRef_and_GR64_TC
11176 0, // sub_16bit_hi
11177 116, // sub_32bit -> GR64_ArgRef_and_GR64_TC
11178 0, // sub_mask_0
11179 0, // sub_mask_1
11180 0, // sub_xmm
11181 0, // sub_ymm
11182 },
11183 { // GR64_and_LOW32_ADDR_ACCESS
11184 0, // sub_8bit
11185 0, // sub_8bit_hi
11186 0, // sub_8bit_hi_phony
11187 117, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS
11188 0, // sub_16bit_hi
11189 117, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS
11190 0, // sub_mask_0
11191 0, // sub_mask_1
11192 0, // sub_xmm
11193 0, // sub_ymm
11194 },
11195 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11196 118, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11197 118, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11198 0, // sub_8bit_hi_phony
11199 118, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11200 0, // sub_16bit_hi
11201 118, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
11202 0, // sub_mask_0
11203 0, // sub_mask_1
11204 0, // sub_xmm
11205 0, // sub_ymm
11206 },
11207 { // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
11208 119, // sub_8bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
11209 119, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
11210 0, // sub_8bit_hi_phony
11211 119, // sub_16bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
11212 0, // sub_16bit_hi
11213 119, // sub_32bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
11214 0, // sub_mask_0
11215 0, // sub_mask_1
11216 0, // sub_xmm
11217 0, // sub_ymm
11218 },
11219 { // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
11220 120, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
11221 120, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
11222 0, // sub_8bit_hi_phony
11223 120, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
11224 0, // sub_16bit_hi
11225 120, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
11226 0, // sub_mask_0
11227 0, // sub_mask_1
11228 0, // sub_xmm
11229 0, // sub_ymm
11230 },
11231 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11232 121, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11233 0, // sub_8bit_hi
11234 0, // sub_8bit_hi_phony
11235 121, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11236 0, // sub_16bit_hi
11237 121, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
11238 0, // sub_mask_0
11239 0, // sub_mask_1
11240 0, // sub_xmm
11241 0, // sub_ymm
11242 },
11243 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
11244 122, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
11245 0, // sub_8bit_hi
11246 0, // sub_8bit_hi_phony
11247 122, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
11248 0, // sub_16bit_hi
11249 122, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
11250 0, // sub_mask_0
11251 0, // sub_mask_1
11252 0, // sub_xmm
11253 0, // sub_ymm
11254 },
11255 { // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
11256 123, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
11257 0, // sub_8bit_hi
11258 0, // sub_8bit_hi_phony
11259 123, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
11260 0, // sub_16bit_hi
11261 123, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
11262 0, // sub_mask_0
11263 0, // sub_mask_1
11264 0, // sub_xmm
11265 0, // sub_ymm
11266 },
11267 { // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
11268 124, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
11269 0, // sub_8bit_hi
11270 0, // sub_8bit_hi_phony
11271 124, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
11272 0, // sub_16bit_hi
11273 124, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
11274 0, // sub_mask_0
11275 0, // sub_mask_1
11276 0, // sub_xmm
11277 0, // sub_ymm
11278 },
11279 { // RST
11280 0, // sub_8bit
11281 0, // sub_8bit_hi
11282 0, // sub_8bit_hi_phony
11283 0, // sub_16bit
11284 0, // sub_16bit_hi
11285 0, // sub_32bit
11286 0, // sub_mask_0
11287 0, // sub_mask_1
11288 0, // sub_xmm
11289 0, // sub_ymm
11290 },
11291 { // RFP80
11292 0, // sub_8bit
11293 0, // sub_8bit_hi
11294 0, // sub_8bit_hi_phony
11295 0, // sub_16bit
11296 0, // sub_16bit_hi
11297 0, // sub_32bit
11298 0, // sub_mask_0
11299 0, // sub_mask_1
11300 0, // sub_xmm
11301 0, // sub_ymm
11302 },
11303 { // RFP80_7
11304 0, // sub_8bit
11305 0, // sub_8bit_hi
11306 0, // sub_8bit_hi_phony
11307 0, // sub_16bit
11308 0, // sub_16bit_hi
11309 0, // sub_32bit
11310 0, // sub_mask_0
11311 0, // sub_mask_1
11312 0, // sub_xmm
11313 0, // sub_ymm
11314 },
11315 { // VR128X
11316 0, // sub_8bit
11317 0, // sub_8bit_hi
11318 0, // sub_8bit_hi_phony
11319 0, // sub_16bit
11320 0, // sub_16bit_hi
11321 0, // sub_32bit
11322 0, // sub_mask_0
11323 0, // sub_mask_1
11324 0, // sub_xmm
11325 0, // sub_ymm
11326 },
11327 { // VR128
11328 0, // sub_8bit
11329 0, // sub_8bit_hi
11330 0, // sub_8bit_hi_phony
11331 0, // sub_16bit
11332 0, // sub_16bit_hi
11333 0, // sub_32bit
11334 0, // sub_mask_0
11335 0, // sub_mask_1
11336 0, // sub_xmm
11337 0, // sub_ymm
11338 },
11339 { // VR256X
11340 0, // sub_8bit
11341 0, // sub_8bit_hi
11342 0, // sub_8bit_hi_phony
11343 0, // sub_16bit
11344 0, // sub_16bit_hi
11345 0, // sub_32bit
11346 0, // sub_mask_0
11347 0, // sub_mask_1
11348 130, // sub_xmm -> VR256X
11349 0, // sub_ymm
11350 },
11351 { // VR256
11352 0, // sub_8bit
11353 0, // sub_8bit_hi
11354 0, // sub_8bit_hi_phony
11355 0, // sub_16bit
11356 0, // sub_16bit_hi
11357 0, // sub_32bit
11358 0, // sub_mask_0
11359 0, // sub_mask_1
11360 131, // sub_xmm -> VR256
11361 0, // sub_ymm
11362 },
11363 { // VR512
11364 0, // sub_8bit
11365 0, // sub_8bit_hi
11366 0, // sub_8bit_hi_phony
11367 0, // sub_16bit
11368 0, // sub_16bit_hi
11369 0, // sub_32bit
11370 0, // sub_mask_0
11371 0, // sub_mask_1
11372 132, // sub_xmm -> VR512
11373 132, // sub_ymm -> VR512
11374 },
11375 { // VR512_0_15
11376 0, // sub_8bit
11377 0, // sub_8bit_hi
11378 0, // sub_8bit_hi_phony
11379 0, // sub_16bit
11380 0, // sub_16bit_hi
11381 0, // sub_32bit
11382 0, // sub_mask_0
11383 0, // sub_mask_1
11384 133, // sub_xmm -> VR512_0_15
11385 133, // sub_ymm -> VR512_0_15
11386 },
11387 { // TILE
11388 0, // sub_8bit
11389 0, // sub_8bit_hi
11390 0, // sub_8bit_hi_phony
11391 0, // sub_16bit
11392 0, // sub_16bit_hi
11393 0, // sub_32bit
11394 0, // sub_mask_0
11395 0, // sub_mask_1
11396 0, // sub_xmm
11397 0, // sub_ymm
11398 },
11399 };
11400 assert(RC && "Missing regclass");
11401 if (!Idx) return RC;
11402 --Idx;
11403 assert(Idx < 10 && "Bad subreg");
11404 unsigned TV = Table[RC->getID()][Idx];
11405 return TV ? getRegClass(TV - 1) : nullptr;
11406}
11407
11408const TargetRegisterClass *X86GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
11409 static const uint8_t Table[134][10] = {
11410 { // GR8
11411 0, // GR8:sub_8bit
11412 0, // GR8:sub_8bit_hi
11413 0, // GR8:sub_8bit_hi_phony
11414 0, // GR8:sub_16bit
11415 0, // GR8:sub_16bit_hi
11416 0, // GR8:sub_32bit
11417 0, // GR8:sub_mask_0
11418 0, // GR8:sub_mask_1
11419 0, // GR8:sub_xmm
11420 0, // GR8:sub_ymm
11421 },
11422 { // GRH8
11423 0, // GRH8:sub_8bit
11424 0, // GRH8:sub_8bit_hi
11425 0, // GRH8:sub_8bit_hi_phony
11426 0, // GRH8:sub_16bit
11427 0, // GRH8:sub_16bit_hi
11428 0, // GRH8:sub_32bit
11429 0, // GRH8:sub_mask_0
11430 0, // GRH8:sub_mask_1
11431 0, // GRH8:sub_xmm
11432 0, // GRH8:sub_ymm
11433 },
11434 { // GR8_NOREX2
11435 0, // GR8_NOREX2:sub_8bit
11436 0, // GR8_NOREX2:sub_8bit_hi
11437 0, // GR8_NOREX2:sub_8bit_hi_phony
11438 0, // GR8_NOREX2:sub_16bit
11439 0, // GR8_NOREX2:sub_16bit_hi
11440 0, // GR8_NOREX2:sub_32bit
11441 0, // GR8_NOREX2:sub_mask_0
11442 0, // GR8_NOREX2:sub_mask_1
11443 0, // GR8_NOREX2:sub_xmm
11444 0, // GR8_NOREX2:sub_ymm
11445 },
11446 { // GR8_NOREX
11447 0, // GR8_NOREX:sub_8bit
11448 0, // GR8_NOREX:sub_8bit_hi
11449 0, // GR8_NOREX:sub_8bit_hi_phony
11450 0, // GR8_NOREX:sub_16bit
11451 0, // GR8_NOREX:sub_16bit_hi
11452 0, // GR8_NOREX:sub_32bit
11453 0, // GR8_NOREX:sub_mask_0
11454 0, // GR8_NOREX:sub_mask_1
11455 0, // GR8_NOREX:sub_xmm
11456 0, // GR8_NOREX:sub_ymm
11457 },
11458 { // GR8_ABCD_H
11459 0, // GR8_ABCD_H:sub_8bit
11460 0, // GR8_ABCD_H:sub_8bit_hi
11461 0, // GR8_ABCD_H:sub_8bit_hi_phony
11462 0, // GR8_ABCD_H:sub_16bit
11463 0, // GR8_ABCD_H:sub_16bit_hi
11464 0, // GR8_ABCD_H:sub_32bit
11465 0, // GR8_ABCD_H:sub_mask_0
11466 0, // GR8_ABCD_H:sub_mask_1
11467 0, // GR8_ABCD_H:sub_xmm
11468 0, // GR8_ABCD_H:sub_ymm
11469 },
11470 { // GR8_ABCD_L
11471 0, // GR8_ABCD_L:sub_8bit
11472 0, // GR8_ABCD_L:sub_8bit_hi
11473 0, // GR8_ABCD_L:sub_8bit_hi_phony
11474 0, // GR8_ABCD_L:sub_16bit
11475 0, // GR8_ABCD_L:sub_16bit_hi
11476 0, // GR8_ABCD_L:sub_32bit
11477 0, // GR8_ABCD_L:sub_mask_0
11478 0, // GR8_ABCD_L:sub_mask_1
11479 0, // GR8_ABCD_L:sub_xmm
11480 0, // GR8_ABCD_L:sub_ymm
11481 },
11482 { // GRH16
11483 0, // GRH16:sub_8bit
11484 0, // GRH16:sub_8bit_hi
11485 0, // GRH16:sub_8bit_hi_phony
11486 0, // GRH16:sub_16bit
11487 0, // GRH16:sub_16bit_hi
11488 0, // GRH16:sub_32bit
11489 0, // GRH16:sub_mask_0
11490 0, // GRH16:sub_mask_1
11491 0, // GRH16:sub_xmm
11492 0, // GRH16:sub_ymm
11493 },
11494 { // GR16
11495 1, // GR16:sub_8bit -> GR8
11496 5, // GR16:sub_8bit_hi -> GR8_ABCD_H
11497 0, // GR16:sub_8bit_hi_phony
11498 0, // GR16:sub_16bit
11499 0, // GR16:sub_16bit_hi
11500 0, // GR16:sub_32bit
11501 0, // GR16:sub_mask_0
11502 0, // GR16:sub_mask_1
11503 0, // GR16:sub_xmm
11504 0, // GR16:sub_ymm
11505 },
11506 { // GR16_NOREX2
11507 3, // GR16_NOREX2:sub_8bit -> GR8_NOREX2
11508 5, // GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
11509 0, // GR16_NOREX2:sub_8bit_hi_phony
11510 0, // GR16_NOREX2:sub_16bit
11511 0, // GR16_NOREX2:sub_16bit_hi
11512 0, // GR16_NOREX2:sub_32bit
11513 0, // GR16_NOREX2:sub_mask_0
11514 0, // GR16_NOREX2:sub_mask_1
11515 0, // GR16_NOREX2:sub_xmm
11516 0, // GR16_NOREX2:sub_ymm
11517 },
11518 { // GR16_NOREX
11519 3, // GR16_NOREX:sub_8bit -> GR8_NOREX2
11520 5, // GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
11521 0, // GR16_NOREX:sub_8bit_hi_phony
11522 0, // GR16_NOREX:sub_16bit
11523 0, // GR16_NOREX:sub_16bit_hi
11524 0, // GR16_NOREX:sub_32bit
11525 0, // GR16_NOREX:sub_mask_0
11526 0, // GR16_NOREX:sub_mask_1
11527 0, // GR16_NOREX:sub_xmm
11528 0, // GR16_NOREX:sub_ymm
11529 },
11530 { // VK1
11531 0, // VK1:sub_8bit
11532 0, // VK1:sub_8bit_hi
11533 0, // VK1:sub_8bit_hi_phony
11534 0, // VK1:sub_16bit
11535 0, // VK1:sub_16bit_hi
11536 0, // VK1:sub_32bit
11537 0, // VK1:sub_mask_0
11538 0, // VK1:sub_mask_1
11539 0, // VK1:sub_xmm
11540 0, // VK1:sub_ymm
11541 },
11542 { // VK16
11543 0, // VK16:sub_8bit
11544 0, // VK16:sub_8bit_hi
11545 0, // VK16:sub_8bit_hi_phony
11546 0, // VK16:sub_16bit
11547 0, // VK16:sub_16bit_hi
11548 0, // VK16:sub_32bit
11549 0, // VK16:sub_mask_0
11550 0, // VK16:sub_mask_1
11551 0, // VK16:sub_xmm
11552 0, // VK16:sub_ymm
11553 },
11554 { // VK2
11555 0, // VK2:sub_8bit
11556 0, // VK2:sub_8bit_hi
11557 0, // VK2:sub_8bit_hi_phony
11558 0, // VK2:sub_16bit
11559 0, // VK2:sub_16bit_hi
11560 0, // VK2:sub_32bit
11561 0, // VK2:sub_mask_0
11562 0, // VK2:sub_mask_1
11563 0, // VK2:sub_xmm
11564 0, // VK2:sub_ymm
11565 },
11566 { // VK4
11567 0, // VK4:sub_8bit
11568 0, // VK4:sub_8bit_hi
11569 0, // VK4:sub_8bit_hi_phony
11570 0, // VK4:sub_16bit
11571 0, // VK4:sub_16bit_hi
11572 0, // VK4:sub_32bit
11573 0, // VK4:sub_mask_0
11574 0, // VK4:sub_mask_1
11575 0, // VK4:sub_xmm
11576 0, // VK4:sub_ymm
11577 },
11578 { // VK8
11579 0, // VK8:sub_8bit
11580 0, // VK8:sub_8bit_hi
11581 0, // VK8:sub_8bit_hi_phony
11582 0, // VK8:sub_16bit
11583 0, // VK8:sub_16bit_hi
11584 0, // VK8:sub_32bit
11585 0, // VK8:sub_mask_0
11586 0, // VK8:sub_mask_1
11587 0, // VK8:sub_xmm
11588 0, // VK8:sub_ymm
11589 },
11590 { // VK16WM
11591 0, // VK16WM:sub_8bit
11592 0, // VK16WM:sub_8bit_hi
11593 0, // VK16WM:sub_8bit_hi_phony
11594 0, // VK16WM:sub_16bit
11595 0, // VK16WM:sub_16bit_hi
11596 0, // VK16WM:sub_32bit
11597 0, // VK16WM:sub_mask_0
11598 0, // VK16WM:sub_mask_1
11599 0, // VK16WM:sub_xmm
11600 0, // VK16WM:sub_ymm
11601 },
11602 { // VK1WM
11603 0, // VK1WM:sub_8bit
11604 0, // VK1WM:sub_8bit_hi
11605 0, // VK1WM:sub_8bit_hi_phony
11606 0, // VK1WM:sub_16bit
11607 0, // VK1WM:sub_16bit_hi
11608 0, // VK1WM:sub_32bit
11609 0, // VK1WM:sub_mask_0
11610 0, // VK1WM:sub_mask_1
11611 0, // VK1WM:sub_xmm
11612 0, // VK1WM:sub_ymm
11613 },
11614 { // VK2WM
11615 0, // VK2WM:sub_8bit
11616 0, // VK2WM:sub_8bit_hi
11617 0, // VK2WM:sub_8bit_hi_phony
11618 0, // VK2WM:sub_16bit
11619 0, // VK2WM:sub_16bit_hi
11620 0, // VK2WM:sub_32bit
11621 0, // VK2WM:sub_mask_0
11622 0, // VK2WM:sub_mask_1
11623 0, // VK2WM:sub_xmm
11624 0, // VK2WM:sub_ymm
11625 },
11626 { // VK4WM
11627 0, // VK4WM:sub_8bit
11628 0, // VK4WM:sub_8bit_hi
11629 0, // VK4WM:sub_8bit_hi_phony
11630 0, // VK4WM:sub_16bit
11631 0, // VK4WM:sub_16bit_hi
11632 0, // VK4WM:sub_32bit
11633 0, // VK4WM:sub_mask_0
11634 0, // VK4WM:sub_mask_1
11635 0, // VK4WM:sub_xmm
11636 0, // VK4WM:sub_ymm
11637 },
11638 { // VK8WM
11639 0, // VK8WM:sub_8bit
11640 0, // VK8WM:sub_8bit_hi
11641 0, // VK8WM:sub_8bit_hi_phony
11642 0, // VK8WM:sub_16bit
11643 0, // VK8WM:sub_16bit_hi
11644 0, // VK8WM:sub_32bit
11645 0, // VK8WM:sub_mask_0
11646 0, // VK8WM:sub_mask_1
11647 0, // VK8WM:sub_xmm
11648 0, // VK8WM:sub_ymm
11649 },
11650 { // SEGMENT_REG
11651 0, // SEGMENT_REG:sub_8bit
11652 0, // SEGMENT_REG:sub_8bit_hi
11653 0, // SEGMENT_REG:sub_8bit_hi_phony
11654 0, // SEGMENT_REG:sub_16bit
11655 0, // SEGMENT_REG:sub_16bit_hi
11656 0, // SEGMENT_REG:sub_32bit
11657 0, // SEGMENT_REG:sub_mask_0
11658 0, // SEGMENT_REG:sub_mask_1
11659 0, // SEGMENT_REG:sub_xmm
11660 0, // SEGMENT_REG:sub_ymm
11661 },
11662 { // GR16_ABCD
11663 6, // GR16_ABCD:sub_8bit -> GR8_ABCD_L
11664 5, // GR16_ABCD:sub_8bit_hi -> GR8_ABCD_H
11665 0, // GR16_ABCD:sub_8bit_hi_phony
11666 0, // GR16_ABCD:sub_16bit
11667 0, // GR16_ABCD:sub_16bit_hi
11668 0, // GR16_ABCD:sub_32bit
11669 0, // GR16_ABCD:sub_mask_0
11670 0, // GR16_ABCD:sub_mask_1
11671 0, // GR16_ABCD:sub_xmm
11672 0, // GR16_ABCD:sub_ymm
11673 },
11674 { // FPCCR
11675 0, // FPCCR:sub_8bit
11676 0, // FPCCR:sub_8bit_hi
11677 0, // FPCCR:sub_8bit_hi_phony
11678 0, // FPCCR:sub_16bit
11679 0, // FPCCR:sub_16bit_hi
11680 0, // FPCCR:sub_32bit
11681 0, // FPCCR:sub_mask_0
11682 0, // FPCCR:sub_mask_1
11683 0, // FPCCR:sub_xmm
11684 0, // FPCCR:sub_ymm
11685 },
11686 { // FR16X
11687 0, // FR16X:sub_8bit
11688 0, // FR16X:sub_8bit_hi
11689 0, // FR16X:sub_8bit_hi_phony
11690 0, // FR16X:sub_16bit
11691 0, // FR16X:sub_16bit_hi
11692 0, // FR16X:sub_32bit
11693 0, // FR16X:sub_mask_0
11694 0, // FR16X:sub_mask_1
11695 0, // FR16X:sub_xmm
11696 0, // FR16X:sub_ymm
11697 },
11698 { // FR16
11699 0, // FR16:sub_8bit
11700 0, // FR16:sub_8bit_hi
11701 0, // FR16:sub_8bit_hi_phony
11702 0, // FR16:sub_16bit
11703 0, // FR16:sub_16bit_hi
11704 0, // FR16:sub_32bit
11705 0, // FR16:sub_mask_0
11706 0, // FR16:sub_mask_1
11707 0, // FR16:sub_xmm
11708 0, // FR16:sub_ymm
11709 },
11710 { // VK16PAIR
11711 0, // VK16PAIR:sub_8bit
11712 0, // VK16PAIR:sub_8bit_hi
11713 0, // VK16PAIR:sub_8bit_hi_phony
11714 0, // VK16PAIR:sub_16bit
11715 0, // VK16PAIR:sub_16bit_hi
11716 0, // VK16PAIR:sub_32bit
11717 91, // VK16PAIR:sub_mask_0 -> VK64
11718 98, // VK16PAIR:sub_mask_1 -> VK64WM
11719 0, // VK16PAIR:sub_xmm
11720 0, // VK16PAIR:sub_ymm
11721 },
11722 { // VK1PAIR
11723 0, // VK1PAIR:sub_8bit
11724 0, // VK1PAIR:sub_8bit_hi
11725 0, // VK1PAIR:sub_8bit_hi_phony
11726 0, // VK1PAIR:sub_16bit
11727 0, // VK1PAIR:sub_16bit_hi
11728 0, // VK1PAIR:sub_32bit
11729 91, // VK1PAIR:sub_mask_0 -> VK64
11730 98, // VK1PAIR:sub_mask_1 -> VK64WM
11731 0, // VK1PAIR:sub_xmm
11732 0, // VK1PAIR:sub_ymm
11733 },
11734 { // VK2PAIR
11735 0, // VK2PAIR:sub_8bit
11736 0, // VK2PAIR:sub_8bit_hi
11737 0, // VK2PAIR:sub_8bit_hi_phony
11738 0, // VK2PAIR:sub_16bit
11739 0, // VK2PAIR:sub_16bit_hi
11740 0, // VK2PAIR:sub_32bit
11741 91, // VK2PAIR:sub_mask_0 -> VK64
11742 98, // VK2PAIR:sub_mask_1 -> VK64WM
11743 0, // VK2PAIR:sub_xmm
11744 0, // VK2PAIR:sub_ymm
11745 },
11746 { // VK4PAIR
11747 0, // VK4PAIR:sub_8bit
11748 0, // VK4PAIR:sub_8bit_hi
11749 0, // VK4PAIR:sub_8bit_hi_phony
11750 0, // VK4PAIR:sub_16bit
11751 0, // VK4PAIR:sub_16bit_hi
11752 0, // VK4PAIR:sub_32bit
11753 91, // VK4PAIR:sub_mask_0 -> VK64
11754 98, // VK4PAIR:sub_mask_1 -> VK64WM
11755 0, // VK4PAIR:sub_xmm
11756 0, // VK4PAIR:sub_ymm
11757 },
11758 { // VK8PAIR
11759 0, // VK8PAIR:sub_8bit
11760 0, // VK8PAIR:sub_8bit_hi
11761 0, // VK8PAIR:sub_8bit_hi_phony
11762 0, // VK8PAIR:sub_16bit
11763 0, // VK8PAIR:sub_16bit_hi
11764 0, // VK8PAIR:sub_32bit
11765 91, // VK8PAIR:sub_mask_0 -> VK64
11766 98, // VK8PAIR:sub_mask_1 -> VK64WM
11767 0, // VK8PAIR:sub_xmm
11768 0, // VK8PAIR:sub_ymm
11769 },
11770 { // VK1PAIR_with_sub_mask_0_in_VK1WM
11771 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit
11772 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi
11773 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_8bit_hi_phony
11774 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit
11775 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_16bit_hi
11776 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_32bit
11777 98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_0 -> VK64WM
11778 98, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_mask_1 -> VK64WM
11779 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_xmm
11780 0, // VK1PAIR_with_sub_mask_0_in_VK1WM:sub_ymm
11781 },
11782 { // LOW32_ADDR_ACCESS_RBP
11783 1, // LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8
11784 5, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi -> GR8_ABCD_H
11785 0, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
11786 8, // LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16
11787 0, // LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
11788 66, // LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
11789 0, // LOW32_ADDR_ACCESS_RBP:sub_mask_0
11790 0, // LOW32_ADDR_ACCESS_RBP:sub_mask_1
11791 0, // LOW32_ADDR_ACCESS_RBP:sub_xmm
11792 0, // LOW32_ADDR_ACCESS_RBP:sub_ymm
11793 },
11794 { // LOW32_ADDR_ACCESS
11795 1, // LOW32_ADDR_ACCESS:sub_8bit -> GR8
11796 5, // LOW32_ADDR_ACCESS:sub_8bit_hi -> GR8_ABCD_H
11797 0, // LOW32_ADDR_ACCESS:sub_8bit_hi_phony
11798 8, // LOW32_ADDR_ACCESS:sub_16bit -> GR16
11799 0, // LOW32_ADDR_ACCESS:sub_16bit_hi
11800 0, // LOW32_ADDR_ACCESS:sub_32bit
11801 0, // LOW32_ADDR_ACCESS:sub_mask_0
11802 0, // LOW32_ADDR_ACCESS:sub_mask_1
11803 0, // LOW32_ADDR_ACCESS:sub_xmm
11804 0, // LOW32_ADDR_ACCESS:sub_ymm
11805 },
11806 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
11807 1, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit -> GR8
11808 5, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
11809 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi_phony
11810 8, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit -> GR16
11811 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit_hi
11812 66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
11813 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_0
11814 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_1
11815 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_xmm
11816 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_ymm
11817 },
11818 { // FR32X
11819 0, // FR32X:sub_8bit
11820 0, // FR32X:sub_8bit_hi
11821 0, // FR32X:sub_8bit_hi_phony
11822 0, // FR32X:sub_16bit
11823 0, // FR32X:sub_16bit_hi
11824 0, // FR32X:sub_32bit
11825 0, // FR32X:sub_mask_0
11826 0, // FR32X:sub_mask_1
11827 0, // FR32X:sub_xmm
11828 0, // FR32X:sub_ymm
11829 },
11830 { // GR32
11831 1, // GR32:sub_8bit -> GR8
11832 5, // GR32:sub_8bit_hi -> GR8_ABCD_H
11833 0, // GR32:sub_8bit_hi_phony
11834 8, // GR32:sub_16bit -> GR16
11835 0, // GR32:sub_16bit_hi
11836 0, // GR32:sub_32bit
11837 0, // GR32:sub_mask_0
11838 0, // GR32:sub_mask_1
11839 0, // GR32:sub_xmm
11840 0, // GR32:sub_ymm
11841 },
11842 { // GR32_NOSP
11843 1, // GR32_NOSP:sub_8bit -> GR8
11844 5, // GR32_NOSP:sub_8bit_hi -> GR8_ABCD_H
11845 0, // GR32_NOSP:sub_8bit_hi_phony
11846 8, // GR32_NOSP:sub_16bit -> GR16
11847 0, // GR32_NOSP:sub_16bit_hi
11848 0, // GR32_NOSP:sub_32bit
11849 0, // GR32_NOSP:sub_mask_0
11850 0, // GR32_NOSP:sub_mask_1
11851 0, // GR32_NOSP:sub_xmm
11852 0, // GR32_NOSP:sub_ymm
11853 },
11854 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
11855 3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
11856 5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
11857 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
11858 9, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
11859 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
11860 66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_BPSP_and_GR32_DIBP
11861 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
11862 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
11863 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_xmm
11864 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2:sub_ymm
11865 },
11866 { // DEBUG_REG
11867 0, // DEBUG_REG:sub_8bit
11868 0, // DEBUG_REG:sub_8bit_hi
11869 0, // DEBUG_REG:sub_8bit_hi_phony
11870 0, // DEBUG_REG:sub_16bit
11871 0, // DEBUG_REG:sub_16bit_hi
11872 0, // DEBUG_REG:sub_32bit
11873 0, // DEBUG_REG:sub_mask_0
11874 0, // DEBUG_REG:sub_mask_1
11875 0, // DEBUG_REG:sub_xmm
11876 0, // DEBUG_REG:sub_ymm
11877 },
11878 { // FR32
11879 0, // FR32:sub_8bit
11880 0, // FR32:sub_8bit_hi
11881 0, // FR32:sub_8bit_hi_phony
11882 0, // FR32:sub_16bit
11883 0, // FR32:sub_16bit_hi
11884 0, // FR32:sub_32bit
11885 0, // FR32:sub_mask_0
11886 0, // FR32:sub_mask_1
11887 0, // FR32:sub_xmm
11888 0, // FR32:sub_ymm
11889 },
11890 { // GR32_NOREX2
11891 3, // GR32_NOREX2:sub_8bit -> GR8_NOREX2
11892 5, // GR32_NOREX2:sub_8bit_hi -> GR8_ABCD_H
11893 0, // GR32_NOREX2:sub_8bit_hi_phony
11894 9, // GR32_NOREX2:sub_16bit -> GR16_NOREX2
11895 0, // GR32_NOREX2:sub_16bit_hi
11896 0, // GR32_NOREX2:sub_32bit
11897 0, // GR32_NOREX2:sub_mask_0
11898 0, // GR32_NOREX2:sub_mask_1
11899 0, // GR32_NOREX2:sub_xmm
11900 0, // GR32_NOREX2:sub_ymm
11901 },
11902 { // GR32_NOREX2_NOSP
11903 3, // GR32_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
11904 5, // GR32_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
11905 0, // GR32_NOREX2_NOSP:sub_8bit_hi_phony
11906 9, // GR32_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
11907 0, // GR32_NOREX2_NOSP:sub_16bit_hi
11908 0, // GR32_NOREX2_NOSP:sub_32bit
11909 0, // GR32_NOREX2_NOSP:sub_mask_0
11910 0, // GR32_NOREX2_NOSP:sub_mask_1
11911 0, // GR32_NOREX2_NOSP:sub_xmm
11912 0, // GR32_NOREX2_NOSP:sub_ymm
11913 },
11914 { // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
11915 3, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
11916 5, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
11917 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
11918 10, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
11919 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
11920 66, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_BPSP_and_GR32_DIBP
11921 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_0
11922 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_1
11923 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_xmm
11924 0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_ymm
11925 },
11926 { // GR32_NOREX
11927 3, // GR32_NOREX:sub_8bit -> GR8_NOREX2
11928 5, // GR32_NOREX:sub_8bit_hi -> GR8_ABCD_H
11929 0, // GR32_NOREX:sub_8bit_hi_phony
11930 10, // GR32_NOREX:sub_16bit -> GR16_NOREX
11931 0, // GR32_NOREX:sub_16bit_hi
11932 0, // GR32_NOREX:sub_32bit
11933 0, // GR32_NOREX:sub_mask_0
11934 0, // GR32_NOREX:sub_mask_1
11935 0, // GR32_NOREX:sub_xmm
11936 0, // GR32_NOREX:sub_ymm
11937 },
11938 { // VK32
11939 0, // VK32:sub_8bit
11940 0, // VK32:sub_8bit_hi
11941 0, // VK32:sub_8bit_hi_phony
11942 0, // VK32:sub_16bit
11943 0, // VK32:sub_16bit_hi
11944 0, // VK32:sub_32bit
11945 0, // VK32:sub_mask_0
11946 0, // VK32:sub_mask_1
11947 0, // VK32:sub_xmm
11948 0, // VK32:sub_ymm
11949 },
11950 { // GR32_NOREX_NOSP
11951 3, // GR32_NOREX_NOSP:sub_8bit -> GR8_NOREX2
11952 5, // GR32_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
11953 0, // GR32_NOREX_NOSP:sub_8bit_hi_phony
11954 10, // GR32_NOREX_NOSP:sub_16bit -> GR16_NOREX
11955 0, // GR32_NOREX_NOSP:sub_16bit_hi
11956 0, // GR32_NOREX_NOSP:sub_32bit
11957 0, // GR32_NOREX_NOSP:sub_mask_0
11958 0, // GR32_NOREX_NOSP:sub_mask_1
11959 0, // GR32_NOREX_NOSP:sub_xmm
11960 0, // GR32_NOREX_NOSP:sub_ymm
11961 },
11962 { // RFP32
11963 0, // RFP32:sub_8bit
11964 0, // RFP32:sub_8bit_hi
11965 0, // RFP32:sub_8bit_hi_phony
11966 0, // RFP32:sub_16bit
11967 0, // RFP32:sub_16bit_hi
11968 0, // RFP32:sub_32bit
11969 0, // RFP32:sub_mask_0
11970 0, // RFP32:sub_mask_1
11971 0, // RFP32:sub_xmm
11972 0, // RFP32:sub_ymm
11973 },
11974 { // VK32WM
11975 0, // VK32WM:sub_8bit
11976 0, // VK32WM:sub_8bit_hi
11977 0, // VK32WM:sub_8bit_hi_phony
11978 0, // VK32WM:sub_16bit
11979 0, // VK32WM:sub_16bit_hi
11980 0, // VK32WM:sub_32bit
11981 0, // VK32WM:sub_mask_0
11982 0, // VK32WM:sub_mask_1
11983 0, // VK32WM:sub_xmm
11984 0, // VK32WM:sub_ymm
11985 },
11986 { // GR32_ABCD
11987 6, // GR32_ABCD:sub_8bit -> GR8_ABCD_L
11988 5, // GR32_ABCD:sub_8bit_hi -> GR8_ABCD_H
11989 0, // GR32_ABCD:sub_8bit_hi_phony
11990 22, // GR32_ABCD:sub_16bit -> GR16_ABCD
11991 0, // GR32_ABCD:sub_16bit_hi
11992 0, // GR32_ABCD:sub_32bit
11993 0, // GR32_ABCD:sub_mask_0
11994 0, // GR32_ABCD:sub_mask_1
11995 0, // GR32_ABCD:sub_xmm
11996 0, // GR32_ABCD:sub_ymm
11997 },
11998 { // GR32_TC
11999 3, // GR32_TC:sub_8bit -> GR8_NOREX2
12000 5, // GR32_TC:sub_8bit_hi -> GR8_ABCD_H
12001 0, // GR32_TC:sub_8bit_hi_phony
12002 10, // GR32_TC:sub_16bit -> GR16_NOREX
12003 0, // GR32_TC:sub_16bit_hi
12004 0, // GR32_TC:sub_32bit
12005 0, // GR32_TC:sub_mask_0
12006 0, // GR32_TC:sub_mask_1
12007 0, // GR32_TC:sub_xmm
12008 0, // GR32_TC:sub_ymm
12009 },
12010 { // GR32_ABCD_and_GR32_TC
12011 6, // GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
12012 5, // GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
12013 0, // GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
12014 22, // GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
12015 0, // GR32_ABCD_and_GR32_TC:sub_16bit_hi
12016 0, // GR32_ABCD_and_GR32_TC:sub_32bit
12017 0, // GR32_ABCD_and_GR32_TC:sub_mask_0
12018 0, // GR32_ABCD_and_GR32_TC:sub_mask_1
12019 0, // GR32_ABCD_and_GR32_TC:sub_xmm
12020 0, // GR32_ABCD_and_GR32_TC:sub_ymm
12021 },
12022 { // GR32_AD
12023 6, // GR32_AD:sub_8bit -> GR8_ABCD_L
12024 5, // GR32_AD:sub_8bit_hi -> GR8_ABCD_H
12025 0, // GR32_AD:sub_8bit_hi_phony
12026 22, // GR32_AD:sub_16bit -> GR16_ABCD
12027 0, // GR32_AD:sub_16bit_hi
12028 0, // GR32_AD:sub_32bit
12029 0, // GR32_AD:sub_mask_0
12030 0, // GR32_AD:sub_mask_1
12031 0, // GR32_AD:sub_xmm
12032 0, // GR32_AD:sub_ymm
12033 },
12034 { // GR32_ArgRef
12035 6, // GR32_ArgRef:sub_8bit -> GR8_ABCD_L
12036 5, // GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
12037 0, // GR32_ArgRef:sub_8bit_hi_phony
12038 22, // GR32_ArgRef:sub_16bit -> GR16_ABCD
12039 0, // GR32_ArgRef:sub_16bit_hi
12040 0, // GR32_ArgRef:sub_32bit
12041 0, // GR32_ArgRef:sub_mask_0
12042 0, // GR32_ArgRef:sub_mask_1
12043 0, // GR32_ArgRef:sub_xmm
12044 0, // GR32_ArgRef:sub_ymm
12045 },
12046 { // GR32_BPSP
12047 3, // GR32_BPSP:sub_8bit -> GR8_NOREX2
12048 0, // GR32_BPSP:sub_8bit_hi
12049 0, // GR32_BPSP:sub_8bit_hi_phony
12050 10, // GR32_BPSP:sub_16bit -> GR16_NOREX
12051 0, // GR32_BPSP:sub_16bit_hi
12052 0, // GR32_BPSP:sub_32bit
12053 0, // GR32_BPSP:sub_mask_0
12054 0, // GR32_BPSP:sub_mask_1
12055 0, // GR32_BPSP:sub_xmm
12056 0, // GR32_BPSP:sub_ymm
12057 },
12058 { // GR32_BSI
12059 3, // GR32_BSI:sub_8bit -> GR8_NOREX2
12060 5, // GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
12061 0, // GR32_BSI:sub_8bit_hi_phony
12062 10, // GR32_BSI:sub_16bit -> GR16_NOREX
12063 0, // GR32_BSI:sub_16bit_hi
12064 0, // GR32_BSI:sub_32bit
12065 0, // GR32_BSI:sub_mask_0
12066 0, // GR32_BSI:sub_mask_1
12067 0, // GR32_BSI:sub_xmm
12068 0, // GR32_BSI:sub_ymm
12069 },
12070 { // GR32_CB
12071 6, // GR32_CB:sub_8bit -> GR8_ABCD_L
12072 5, // GR32_CB:sub_8bit_hi -> GR8_ABCD_H
12073 0, // GR32_CB:sub_8bit_hi_phony
12074 22, // GR32_CB:sub_16bit -> GR16_ABCD
12075 0, // GR32_CB:sub_16bit_hi
12076 0, // GR32_CB:sub_32bit
12077 0, // GR32_CB:sub_mask_0
12078 0, // GR32_CB:sub_mask_1
12079 0, // GR32_CB:sub_xmm
12080 0, // GR32_CB:sub_ymm
12081 },
12082 { // GR32_DC
12083 6, // GR32_DC:sub_8bit -> GR8_ABCD_L
12084 5, // GR32_DC:sub_8bit_hi -> GR8_ABCD_H
12085 0, // GR32_DC:sub_8bit_hi_phony
12086 22, // GR32_DC:sub_16bit -> GR16_ABCD
12087 0, // GR32_DC:sub_16bit_hi
12088 0, // GR32_DC:sub_32bit
12089 0, // GR32_DC:sub_mask_0
12090 0, // GR32_DC:sub_mask_1
12091 0, // GR32_DC:sub_xmm
12092 0, // GR32_DC:sub_ymm
12093 },
12094 { // GR32_DIBP
12095 3, // GR32_DIBP:sub_8bit -> GR8_NOREX2
12096 0, // GR32_DIBP:sub_8bit_hi
12097 0, // GR32_DIBP:sub_8bit_hi_phony
12098 10, // GR32_DIBP:sub_16bit -> GR16_NOREX
12099 0, // GR32_DIBP:sub_16bit_hi
12100 0, // GR32_DIBP:sub_32bit
12101 0, // GR32_DIBP:sub_mask_0
12102 0, // GR32_DIBP:sub_mask_1
12103 0, // GR32_DIBP:sub_xmm
12104 0, // GR32_DIBP:sub_ymm
12105 },
12106 { // GR32_SIDI
12107 3, // GR32_SIDI:sub_8bit -> GR8_NOREX2
12108 0, // GR32_SIDI:sub_8bit_hi
12109 0, // GR32_SIDI:sub_8bit_hi_phony
12110 10, // GR32_SIDI:sub_16bit -> GR16_NOREX
12111 0, // GR32_SIDI:sub_16bit_hi
12112 0, // GR32_SIDI:sub_32bit
12113 0, // GR32_SIDI:sub_mask_0
12114 0, // GR32_SIDI:sub_mask_1
12115 0, // GR32_SIDI:sub_xmm
12116 0, // GR32_SIDI:sub_ymm
12117 },
12118 { // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
12119 3, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit -> GR8_NOREX2
12120 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi
12121 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi_phony
12122 10, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit -> GR16_NOREX
12123 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit_hi
12124 66, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
12125 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_0
12126 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_1
12127 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_xmm
12128 0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_ymm
12129 },
12130 { // CCR
12131 0, // CCR:sub_8bit
12132 0, // CCR:sub_8bit_hi
12133 0, // CCR:sub_8bit_hi_phony
12134 0, // CCR:sub_16bit
12135 0, // CCR:sub_16bit_hi
12136 0, // CCR:sub_32bit
12137 0, // CCR:sub_mask_0
12138 0, // CCR:sub_mask_1
12139 0, // CCR:sub_xmm
12140 0, // CCR:sub_ymm
12141 },
12142 { // DFCCR
12143 0, // DFCCR:sub_8bit
12144 0, // DFCCR:sub_8bit_hi
12145 0, // DFCCR:sub_8bit_hi_phony
12146 0, // DFCCR:sub_16bit
12147 0, // DFCCR:sub_16bit_hi
12148 0, // DFCCR:sub_32bit
12149 0, // DFCCR:sub_mask_0
12150 0, // DFCCR:sub_mask_1
12151 0, // DFCCR:sub_xmm
12152 0, // DFCCR:sub_ymm
12153 },
12154 { // GR32_ABCD_and_GR32_BSI
12155 6, // GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
12156 5, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
12157 0, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
12158 22, // GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
12159 0, // GR32_ABCD_and_GR32_BSI:sub_16bit_hi
12160 0, // GR32_ABCD_and_GR32_BSI:sub_32bit
12161 0, // GR32_ABCD_and_GR32_BSI:sub_mask_0
12162 0, // GR32_ABCD_and_GR32_BSI:sub_mask_1
12163 0, // GR32_ABCD_and_GR32_BSI:sub_xmm
12164 0, // GR32_ABCD_and_GR32_BSI:sub_ymm
12165 },
12166 { // GR32_AD_and_GR32_ArgRef
12167 6, // GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
12168 5, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
12169 0, // GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
12170 22, // GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
12171 0, // GR32_AD_and_GR32_ArgRef:sub_16bit_hi
12172 0, // GR32_AD_and_GR32_ArgRef:sub_32bit
12173 0, // GR32_AD_and_GR32_ArgRef:sub_mask_0
12174 0, // GR32_AD_and_GR32_ArgRef:sub_mask_1
12175 0, // GR32_AD_and_GR32_ArgRef:sub_xmm
12176 0, // GR32_AD_and_GR32_ArgRef:sub_ymm
12177 },
12178 { // GR32_ArgRef_and_GR32_CB
12179 6, // GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
12180 5, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
12181 0, // GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
12182 22, // GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
12183 0, // GR32_ArgRef_and_GR32_CB:sub_16bit_hi
12184 0, // GR32_ArgRef_and_GR32_CB:sub_32bit
12185 0, // GR32_ArgRef_and_GR32_CB:sub_mask_0
12186 0, // GR32_ArgRef_and_GR32_CB:sub_mask_1
12187 0, // GR32_ArgRef_and_GR32_CB:sub_xmm
12188 0, // GR32_ArgRef_and_GR32_CB:sub_ymm
12189 },
12190 { // GR32_BPSP_and_GR32_DIBP
12191 3, // GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
12192 0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
12193 0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
12194 10, // GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
12195 0, // GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
12196 0, // GR32_BPSP_and_GR32_DIBP:sub_32bit
12197 0, // GR32_BPSP_and_GR32_DIBP:sub_mask_0
12198 0, // GR32_BPSP_and_GR32_DIBP:sub_mask_1
12199 0, // GR32_BPSP_and_GR32_DIBP:sub_xmm
12200 0, // GR32_BPSP_and_GR32_DIBP:sub_ymm
12201 },
12202 { // GR32_BPSP_and_GR32_TC
12203 3, // GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
12204 0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi
12205 0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
12206 10, // GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
12207 0, // GR32_BPSP_and_GR32_TC:sub_16bit_hi
12208 0, // GR32_BPSP_and_GR32_TC:sub_32bit
12209 0, // GR32_BPSP_and_GR32_TC:sub_mask_0
12210 0, // GR32_BPSP_and_GR32_TC:sub_mask_1
12211 0, // GR32_BPSP_and_GR32_TC:sub_xmm
12212 0, // GR32_BPSP_and_GR32_TC:sub_ymm
12213 },
12214 { // GR32_BSI_and_GR32_SIDI
12215 3, // GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
12216 0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi
12217 0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
12218 10, // GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
12219 0, // GR32_BSI_and_GR32_SIDI:sub_16bit_hi
12220 0, // GR32_BSI_and_GR32_SIDI:sub_32bit
12221 0, // GR32_BSI_and_GR32_SIDI:sub_mask_0
12222 0, // GR32_BSI_and_GR32_SIDI:sub_mask_1
12223 0, // GR32_BSI_and_GR32_SIDI:sub_xmm
12224 0, // GR32_BSI_and_GR32_SIDI:sub_ymm
12225 },
12226 { // GR32_DIBP_and_GR32_SIDI
12227 3, // GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
12228 0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
12229 0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
12230 10, // GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
12231 0, // GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
12232 0, // GR32_DIBP_and_GR32_SIDI:sub_32bit
12233 0, // GR32_DIBP_and_GR32_SIDI:sub_mask_0
12234 0, // GR32_DIBP_and_GR32_SIDI:sub_mask_1
12235 0, // GR32_DIBP_and_GR32_SIDI:sub_xmm
12236 0, // GR32_DIBP_and_GR32_SIDI:sub_ymm
12237 },
12238 { // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
12239 3, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit -> GR8_NOREX2
12240 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi
12241 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi_phony
12242 10, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit -> GR16_NOREX
12243 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit_hi
12244 66, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
12245 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_0
12246 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_1
12247 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_xmm
12248 0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_ymm
12249 },
12250 { // LOW32_ADDR_ACCESS_with_sub_32bit
12251 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit
12252 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi
12253 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi_phony
12254 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit
12255 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit_hi
12256 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_32bit
12257 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_0
12258 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_1
12259 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_xmm
12260 0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_ymm
12261 },
12262 { // RFP64
12263 0, // RFP64:sub_8bit
12264 0, // RFP64:sub_8bit_hi
12265 0, // RFP64:sub_8bit_hi_phony
12266 0, // RFP64:sub_16bit
12267 0, // RFP64:sub_16bit_hi
12268 0, // RFP64:sub_32bit
12269 0, // RFP64:sub_mask_0
12270 0, // RFP64:sub_mask_1
12271 0, // RFP64:sub_xmm
12272 0, // RFP64:sub_ymm
12273 },
12274 { // GR64
12275 1, // GR64:sub_8bit -> GR8
12276 5, // GR64:sub_8bit_hi -> GR8_ABCD_H
12277 0, // GR64:sub_8bit_hi_phony
12278 8, // GR64:sub_16bit -> GR16
12279 0, // GR64:sub_16bit_hi
12280 36, // GR64:sub_32bit -> GR32
12281 0, // GR64:sub_mask_0
12282 0, // GR64:sub_mask_1
12283 0, // GR64:sub_xmm
12284 0, // GR64:sub_ymm
12285 },
12286 { // FR64X
12287 0, // FR64X:sub_8bit
12288 0, // FR64X:sub_8bit_hi
12289 0, // FR64X:sub_8bit_hi_phony
12290 0, // FR64X:sub_16bit
12291 0, // FR64X:sub_16bit_hi
12292 0, // FR64X:sub_32bit
12293 0, // FR64X:sub_mask_0
12294 0, // FR64X:sub_mask_1
12295 0, // FR64X:sub_xmm
12296 0, // FR64X:sub_ymm
12297 },
12298 { // GR64_with_sub_8bit
12299 1, // GR64_with_sub_8bit:sub_8bit -> GR8
12300 5, // GR64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
12301 0, // GR64_with_sub_8bit:sub_8bit_hi_phony
12302 8, // GR64_with_sub_8bit:sub_16bit -> GR16
12303 0, // GR64_with_sub_8bit:sub_16bit_hi
12304 36, // GR64_with_sub_8bit:sub_32bit -> GR32
12305 0, // GR64_with_sub_8bit:sub_mask_0
12306 0, // GR64_with_sub_8bit:sub_mask_1
12307 0, // GR64_with_sub_8bit:sub_xmm
12308 0, // GR64_with_sub_8bit:sub_ymm
12309 },
12310 { // GR64_NOSP
12311 1, // GR64_NOSP:sub_8bit -> GR8
12312 5, // GR64_NOSP:sub_8bit_hi -> GR8_ABCD_H
12313 0, // GR64_NOSP:sub_8bit_hi_phony
12314 8, // GR64_NOSP:sub_16bit -> GR16
12315 0, // GR64_NOSP:sub_16bit_hi
12316 37, // GR64_NOSP:sub_32bit -> GR32_NOSP
12317 0, // GR64_NOSP:sub_mask_0
12318 0, // GR64_NOSP:sub_mask_1
12319 0, // GR64_NOSP:sub_xmm
12320 0, // GR64_NOSP:sub_ymm
12321 },
12322 { // GR64_NOREX2
12323 3, // GR64_NOREX2:sub_8bit -> GR8_NOREX2
12324 5, // GR64_NOREX2:sub_8bit_hi -> GR8_ABCD_H
12325 0, // GR64_NOREX2:sub_8bit_hi_phony
12326 9, // GR64_NOREX2:sub_16bit -> GR16_NOREX2
12327 0, // GR64_NOREX2:sub_16bit_hi
12328 41, // GR64_NOREX2:sub_32bit -> GR32_NOREX2
12329 0, // GR64_NOREX2:sub_mask_0
12330 0, // GR64_NOREX2:sub_mask_1
12331 0, // GR64_NOREX2:sub_xmm
12332 0, // GR64_NOREX2:sub_ymm
12333 },
12334 { // CONTROL_REG
12335 0, // CONTROL_REG:sub_8bit
12336 0, // CONTROL_REG:sub_8bit_hi
12337 0, // CONTROL_REG:sub_8bit_hi_phony
12338 0, // CONTROL_REG:sub_16bit
12339 0, // CONTROL_REG:sub_16bit_hi
12340 0, // CONTROL_REG:sub_32bit
12341 0, // CONTROL_REG:sub_mask_0
12342 0, // CONTROL_REG:sub_mask_1
12343 0, // CONTROL_REG:sub_xmm
12344 0, // CONTROL_REG:sub_ymm
12345 },
12346 { // FR64
12347 0, // FR64:sub_8bit
12348 0, // FR64:sub_8bit_hi
12349 0, // FR64:sub_8bit_hi_phony
12350 0, // FR64:sub_16bit
12351 0, // FR64:sub_16bit_hi
12352 0, // FR64:sub_32bit
12353 0, // FR64:sub_mask_0
12354 0, // FR64:sub_mask_1
12355 0, // FR64:sub_xmm
12356 0, // FR64:sub_ymm
12357 },
12358 { // GR64_with_sub_16bit_in_GR16_NOREX2
12359 3, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit -> GR8_NOREX2
12360 5, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi -> GR8_ABCD_H
12361 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_8bit_hi_phony
12362 9, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit -> GR16_NOREX2
12363 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_16bit_hi
12364 41, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_32bit -> GR32_NOREX2
12365 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_0
12366 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_mask_1
12367 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_xmm
12368 0, // GR64_with_sub_16bit_in_GR16_NOREX2:sub_ymm
12369 },
12370 { // GR64_NOREX2_NOSP
12371 3, // GR64_NOREX2_NOSP:sub_8bit -> GR8_NOREX2
12372 5, // GR64_NOREX2_NOSP:sub_8bit_hi -> GR8_ABCD_H
12373 0, // GR64_NOREX2_NOSP:sub_8bit_hi_phony
12374 9, // GR64_NOREX2_NOSP:sub_16bit -> GR16_NOREX2
12375 0, // GR64_NOREX2_NOSP:sub_16bit_hi
12376 42, // GR64_NOREX2_NOSP:sub_32bit -> GR32_NOREX2_NOSP
12377 0, // GR64_NOREX2_NOSP:sub_mask_0
12378 0, // GR64_NOREX2_NOSP:sub_mask_1
12379 0, // GR64_NOREX2_NOSP:sub_xmm
12380 0, // GR64_NOREX2_NOSP:sub_ymm
12381 },
12382 { // GR64PLTSafe
12383 3, // GR64PLTSafe:sub_8bit -> GR8_NOREX2
12384 5, // GR64PLTSafe:sub_8bit_hi -> GR8_ABCD_H
12385 0, // GR64PLTSafe:sub_8bit_hi_phony
12386 9, // GR64PLTSafe:sub_16bit -> GR16_NOREX2
12387 0, // GR64PLTSafe:sub_16bit_hi
12388 42, // GR64PLTSafe:sub_32bit -> GR32_NOREX2_NOSP
12389 0, // GR64PLTSafe:sub_mask_0
12390 0, // GR64PLTSafe:sub_mask_1
12391 0, // GR64PLTSafe:sub_xmm
12392 0, // GR64PLTSafe:sub_ymm
12393 },
12394 { // GR64_TC
12395 3, // GR64_TC:sub_8bit -> GR8_NOREX2
12396 5, // GR64_TC:sub_8bit_hi -> GR8_ABCD_H
12397 0, // GR64_TC:sub_8bit_hi_phony
12398 9, // GR64_TC:sub_16bit -> GR16_NOREX2
12399 0, // GR64_TC:sub_16bit_hi
12400 41, // GR64_TC:sub_32bit -> GR32_NOREX2
12401 0, // GR64_TC:sub_mask_0
12402 0, // GR64_TC:sub_mask_1
12403 0, // GR64_TC:sub_xmm
12404 0, // GR64_TC:sub_ymm
12405 },
12406 { // GR64_NOREX
12407 3, // GR64_NOREX:sub_8bit -> GR8_NOREX2
12408 5, // GR64_NOREX:sub_8bit_hi -> GR8_ABCD_H
12409 0, // GR64_NOREX:sub_8bit_hi_phony
12410 10, // GR64_NOREX:sub_16bit -> GR16_NOREX
12411 0, // GR64_NOREX:sub_16bit_hi
12412 44, // GR64_NOREX:sub_32bit -> GR32_NOREX
12413 0, // GR64_NOREX:sub_mask_0
12414 0, // GR64_NOREX:sub_mask_1
12415 0, // GR64_NOREX:sub_xmm
12416 0, // GR64_NOREX:sub_ymm
12417 },
12418 { // GR64_TCW64
12419 3, // GR64_TCW64:sub_8bit -> GR8_NOREX2
12420 5, // GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
12421 0, // GR64_TCW64:sub_8bit_hi_phony
12422 9, // GR64_TCW64:sub_16bit -> GR16_NOREX2
12423 0, // GR64_TCW64:sub_16bit_hi
12424 41, // GR64_TCW64:sub_32bit -> GR32_NOREX2
12425 0, // GR64_TCW64:sub_mask_0
12426 0, // GR64_TCW64:sub_mask_1
12427 0, // GR64_TCW64:sub_xmm
12428 0, // GR64_TCW64:sub_ymm
12429 },
12430 { // GR64_TC_with_sub_8bit
12431 3, // GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
12432 5, // GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
12433 0, // GR64_TC_with_sub_8bit:sub_8bit_hi_phony
12434 9, // GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
12435 0, // GR64_TC_with_sub_8bit:sub_16bit_hi
12436 41, // GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
12437 0, // GR64_TC_with_sub_8bit:sub_mask_0
12438 0, // GR64_TC_with_sub_8bit:sub_mask_1
12439 0, // GR64_TC_with_sub_8bit:sub_xmm
12440 0, // GR64_TC_with_sub_8bit:sub_ymm
12441 },
12442 { // GR64_NOREX2_NOSP_and_GR64_TC
12443 3, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit -> GR8_NOREX2
12444 5, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
12445 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_8bit_hi_phony
12446 9, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit -> GR16_NOREX2
12447 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_16bit_hi
12448 42, // GR64_NOREX2_NOSP_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
12449 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_0
12450 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_mask_1
12451 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_xmm
12452 0, // GR64_NOREX2_NOSP_and_GR64_TC:sub_ymm
12453 },
12454 { // GR64_TCW64_with_sub_8bit
12455 3, // GR64_TCW64_with_sub_8bit:sub_8bit -> GR8_NOREX2
12456 5, // GR64_TCW64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
12457 0, // GR64_TCW64_with_sub_8bit:sub_8bit_hi_phony
12458 9, // GR64_TCW64_with_sub_8bit:sub_16bit -> GR16_NOREX2
12459 0, // GR64_TCW64_with_sub_8bit:sub_16bit_hi
12460 41, // GR64_TCW64_with_sub_8bit:sub_32bit -> GR32_NOREX2
12461 0, // GR64_TCW64_with_sub_8bit:sub_mask_0
12462 0, // GR64_TCW64_with_sub_8bit:sub_mask_1
12463 0, // GR64_TCW64_with_sub_8bit:sub_xmm
12464 0, // GR64_TCW64_with_sub_8bit:sub_ymm
12465 },
12466 { // GR64_TC_and_GR64_TCW64
12467 3, // GR64_TC_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
12468 5, // GR64_TC_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
12469 0, // GR64_TC_and_GR64_TCW64:sub_8bit_hi_phony
12470 9, // GR64_TC_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
12471 0, // GR64_TC_and_GR64_TCW64:sub_16bit_hi
12472 41, // GR64_TC_and_GR64_TCW64:sub_32bit -> GR32_NOREX2
12473 0, // GR64_TC_and_GR64_TCW64:sub_mask_0
12474 0, // GR64_TC_and_GR64_TCW64:sub_mask_1
12475 0, // GR64_TC_and_GR64_TCW64:sub_xmm
12476 0, // GR64_TC_and_GR64_TCW64:sub_ymm
12477 },
12478 { // GR64_with_sub_16bit_in_GR16_NOREX
12479 3, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
12480 5, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
12481 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
12482 10, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
12483 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
12484 44, // GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
12485 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
12486 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
12487 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
12488 0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
12489 },
12490 { // VK64
12491 0, // VK64:sub_8bit
12492 0, // VK64:sub_8bit_hi
12493 0, // VK64:sub_8bit_hi_phony
12494 0, // VK64:sub_16bit
12495 0, // VK64:sub_16bit_hi
12496 0, // VK64:sub_32bit
12497 0, // VK64:sub_mask_0
12498 0, // VK64:sub_mask_1
12499 0, // VK64:sub_xmm
12500 0, // VK64:sub_ymm
12501 },
12502 { // VR64
12503 0, // VR64:sub_8bit
12504 0, // VR64:sub_8bit_hi
12505 0, // VR64:sub_8bit_hi_phony
12506 0, // VR64:sub_16bit
12507 0, // VR64:sub_16bit_hi
12508 0, // VR64:sub_32bit
12509 0, // VR64:sub_mask_0
12510 0, // VR64:sub_mask_1
12511 0, // VR64:sub_xmm
12512 0, // VR64:sub_ymm
12513 },
12514 { // GR64PLTSafe_and_GR64_TC
12515 3, // GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
12516 5, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
12517 0, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
12518 9, // GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX2
12519 0, // GR64PLTSafe_and_GR64_TC:sub_16bit_hi
12520 42, // GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
12521 0, // GR64PLTSafe_and_GR64_TC:sub_mask_0
12522 0, // GR64PLTSafe_and_GR64_TC:sub_mask_1
12523 0, // GR64PLTSafe_and_GR64_TC:sub_xmm
12524 0, // GR64PLTSafe_and_GR64_TC:sub_ymm
12525 },
12526 { // GR64_NOREX2_NOSP_and_GR64_TCW64
12527 3, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
12528 5, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
12529 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
12530 9, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
12531 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
12532 42, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
12533 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
12534 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
12535 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
12536 0, // GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
12537 },
12538 { // GR64_NOREX_NOSP
12539 3, // GR64_NOREX_NOSP:sub_8bit -> GR8_NOREX2
12540 5, // GR64_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
12541 0, // GR64_NOREX_NOSP:sub_8bit_hi_phony
12542 10, // GR64_NOREX_NOSP:sub_16bit -> GR16_NOREX
12543 0, // GR64_NOREX_NOSP:sub_16bit_hi
12544 46, // GR64_NOREX_NOSP:sub_32bit -> GR32_NOREX_NOSP
12545 0, // GR64_NOREX_NOSP:sub_mask_0
12546 0, // GR64_NOREX_NOSP:sub_mask_1
12547 0, // GR64_NOREX_NOSP:sub_xmm
12548 0, // GR64_NOREX_NOSP:sub_ymm
12549 },
12550 { // GR64_NOREX_and_GR64_TC
12551 3, // GR64_NOREX_and_GR64_TC:sub_8bit -> GR8_NOREX2
12552 5, // GR64_NOREX_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
12553 0, // GR64_NOREX_and_GR64_TC:sub_8bit_hi_phony
12554 10, // GR64_NOREX_and_GR64_TC:sub_16bit -> GR16_NOREX
12555 0, // GR64_NOREX_and_GR64_TC:sub_16bit_hi
12556 44, // GR64_NOREX_and_GR64_TC:sub_32bit -> GR32_NOREX
12557 0, // GR64_NOREX_and_GR64_TC:sub_mask_0
12558 0, // GR64_NOREX_and_GR64_TC:sub_mask_1
12559 0, // GR64_NOREX_and_GR64_TC:sub_xmm
12560 0, // GR64_NOREX_and_GR64_TC:sub_ymm
12561 },
12562 { // GR64_TCW64_and_GR64_TC_with_sub_8bit
12563 3, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit -> GR8_NOREX2
12564 5, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
12565 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi_phony
12566 9, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit -> GR16_NOREX2
12567 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit_hi
12568 41, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_32bit -> GR32_NOREX2
12569 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_0
12570 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_1
12571 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_xmm
12572 0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_ymm
12573 },
12574 { // VK64WM
12575 0, // VK64WM:sub_8bit
12576 0, // VK64WM:sub_8bit_hi
12577 0, // VK64WM:sub_8bit_hi_phony
12578 0, // VK64WM:sub_16bit
12579 0, // VK64WM:sub_16bit_hi
12580 0, // VK64WM:sub_32bit
12581 0, // VK64WM:sub_mask_0
12582 0, // VK64WM:sub_mask_1
12583 0, // VK64WM:sub_xmm
12584 0, // VK64WM:sub_ymm
12585 },
12586 { // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
12587 3, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
12588 5, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
12589 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
12590 9, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
12591 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_16bit_hi
12592 42, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
12593 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_0
12594 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_mask_1
12595 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_xmm
12596 0, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64:sub_ymm
12597 },
12598 { // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
12599 3, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8_NOREX2
12600 5, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
12601 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
12602 10, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
12603 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
12604 44, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
12605 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
12606 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
12607 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
12608 0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
12609 },
12610 { // GR64PLTSafe_and_GR64_TCW64
12611 3, // GR64PLTSafe_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
12612 5, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
12613 0, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi_phony
12614 9, // GR64PLTSafe_and_GR64_TCW64:sub_16bit -> GR16_NOREX2
12615 0, // GR64PLTSafe_and_GR64_TCW64:sub_16bit_hi
12616 42, // GR64PLTSafe_and_GR64_TCW64:sub_32bit -> GR32_NOREX2_NOSP
12617 0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_0
12618 0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_1
12619 0, // GR64PLTSafe_and_GR64_TCW64:sub_xmm
12620 0, // GR64PLTSafe_and_GR64_TCW64:sub_ymm
12621 },
12622 { // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
12623 3, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8_NOREX2
12624 5, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
12625 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
12626 10, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX
12627 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit_hi
12628 46, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX_NOSP
12629 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_0
12630 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_1
12631 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_xmm
12632 0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_ymm
12633 },
12634 { // GR64_NOREX_and_GR64_TCW64
12635 3, // GR64_NOREX_and_GR64_TCW64:sub_8bit -> GR8_NOREX2
12636 5, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
12637 0, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi_phony
12638 10, // GR64_NOREX_and_GR64_TCW64:sub_16bit -> GR16_NOREX
12639 0, // GR64_NOREX_and_GR64_TCW64:sub_16bit_hi
12640 50, // GR64_NOREX_and_GR64_TCW64:sub_32bit -> GR32_TC
12641 0, // GR64_NOREX_and_GR64_TCW64:sub_mask_0
12642 0, // GR64_NOREX_and_GR64_TCW64:sub_mask_1
12643 0, // GR64_NOREX_and_GR64_TCW64:sub_xmm
12644 0, // GR64_NOREX_and_GR64_TCW64:sub_ymm
12645 },
12646 { // GR64_ABCD
12647 6, // GR64_ABCD:sub_8bit -> GR8_ABCD_L
12648 5, // GR64_ABCD:sub_8bit_hi -> GR8_ABCD_H
12649 0, // GR64_ABCD:sub_8bit_hi_phony
12650 22, // GR64_ABCD:sub_16bit -> GR16_ABCD
12651 0, // GR64_ABCD:sub_16bit_hi
12652 49, // GR64_ABCD:sub_32bit -> GR32_ABCD
12653 0, // GR64_ABCD:sub_mask_0
12654 0, // GR64_ABCD:sub_mask_1
12655 0, // GR64_ABCD:sub_xmm
12656 0, // GR64_ABCD:sub_ymm
12657 },
12658 { // GR64_with_sub_32bit_in_GR32_TC
12659 3, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit -> GR8_NOREX2
12660 5, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
12661 0, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi_phony
12662 10, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit -> GR16_NOREX
12663 0, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit_hi
12664 50, // GR64_with_sub_32bit_in_GR32_TC:sub_32bit -> GR32_TC
12665 0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_0
12666 0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_1
12667 0, // GR64_with_sub_32bit_in_GR32_TC:sub_xmm
12668 0, // GR64_with_sub_32bit_in_GR32_TC:sub_ymm
12669 },
12670 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
12671 6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
12672 5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
12673 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
12674 22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
12675 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit_hi
12676 51, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_32bit -> GR32_ABCD_and_GR32_TC
12677 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_0
12678 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_1
12679 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_xmm
12680 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_ymm
12681 },
12682 { // GR64_AD
12683 6, // GR64_AD:sub_8bit -> GR8_ABCD_L
12684 5, // GR64_AD:sub_8bit_hi -> GR8_ABCD_H
12685 0, // GR64_AD:sub_8bit_hi_phony
12686 22, // GR64_AD:sub_16bit -> GR16_ABCD
12687 0, // GR64_AD:sub_16bit_hi
12688 52, // GR64_AD:sub_32bit -> GR32_AD
12689 0, // GR64_AD:sub_mask_0
12690 0, // GR64_AD:sub_mask_1
12691 0, // GR64_AD:sub_xmm
12692 0, // GR64_AD:sub_ymm
12693 },
12694 { // GR64_ArgRef
12695 3, // GR64_ArgRef:sub_8bit -> GR8_NOREX2
12696 0, // GR64_ArgRef:sub_8bit_hi
12697 0, // GR64_ArgRef:sub_8bit_hi_phony
12698 9, // GR64_ArgRef:sub_16bit -> GR16_NOREX2
12699 0, // GR64_ArgRef:sub_16bit_hi
12700 42, // GR64_ArgRef:sub_32bit -> GR32_NOREX2_NOSP
12701 0, // GR64_ArgRef:sub_mask_0
12702 0, // GR64_ArgRef:sub_mask_1
12703 0, // GR64_ArgRef:sub_xmm
12704 0, // GR64_ArgRef:sub_ymm
12705 },
12706 { // GR64_and_LOW32_ADDR_ACCESS_RBP
12707 3, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8_NOREX2
12708 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi
12709 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
12710 10, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16_NOREX
12711 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
12712 66, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
12713 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_0
12714 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_1
12715 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_xmm
12716 0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_ymm
12717 },
12718 { // GR64_with_sub_32bit_in_GR32_ArgRef
12719 6, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
12720 5, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
12721 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_8bit_hi_phony
12722 22, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit -> GR16_ABCD
12723 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_16bit_hi
12724 53, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_32bit -> GR32_ArgRef
12725 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_0
12726 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_mask_1
12727 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_xmm
12728 0, // GR64_with_sub_32bit_in_GR32_ArgRef:sub_ymm
12729 },
12730 { // GR64_with_sub_32bit_in_GR32_BPSP
12731 3, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit -> GR8_NOREX2
12732 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi
12733 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi_phony
12734 10, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit -> GR16_NOREX
12735 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit_hi
12736 54, // GR64_with_sub_32bit_in_GR32_BPSP:sub_32bit -> GR32_BPSP
12737 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_0
12738 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_1
12739 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_xmm
12740 0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_ymm
12741 },
12742 { // GR64_with_sub_32bit_in_GR32_BSI
12743 3, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit -> GR8_NOREX2
12744 5, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
12745 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi_phony
12746 10, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit -> GR16_NOREX
12747 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit_hi
12748 55, // GR64_with_sub_32bit_in_GR32_BSI:sub_32bit -> GR32_BSI
12749 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_0
12750 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_1
12751 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_xmm
12752 0, // GR64_with_sub_32bit_in_GR32_BSI:sub_ymm
12753 },
12754 { // GR64_with_sub_32bit_in_GR32_CB
12755 6, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit -> GR8_ABCD_L
12756 5, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
12757 0, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi_phony
12758 22, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit -> GR16_ABCD
12759 0, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit_hi
12760 56, // GR64_with_sub_32bit_in_GR32_CB:sub_32bit -> GR32_CB
12761 0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_0
12762 0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_1
12763 0, // GR64_with_sub_32bit_in_GR32_CB:sub_xmm
12764 0, // GR64_with_sub_32bit_in_GR32_CB:sub_ymm
12765 },
12766 { // GR64_with_sub_32bit_in_GR32_DIBP
12767 3, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit -> GR8_NOREX2
12768 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi
12769 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi_phony
12770 10, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit -> GR16_NOREX
12771 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit_hi
12772 58, // GR64_with_sub_32bit_in_GR32_DIBP:sub_32bit -> GR32_DIBP
12773 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_0
12774 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_1
12775 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_xmm
12776 0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_ymm
12777 },
12778 { // GR64_with_sub_32bit_in_GR32_SIDI
12779 3, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit -> GR8_NOREX2
12780 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi
12781 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi_phony
12782 10, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit -> GR16_NOREX
12783 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit_hi
12784 59, // GR64_with_sub_32bit_in_GR32_SIDI:sub_32bit -> GR32_SIDI
12785 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_0
12786 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_1
12787 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_xmm
12788 0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_ymm
12789 },
12790 { // GR64_ArgRef_and_GR64_TC
12791 3, // GR64_ArgRef_and_GR64_TC:sub_8bit -> GR8_NOREX2
12792 0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi
12793 0, // GR64_ArgRef_and_GR64_TC:sub_8bit_hi_phony
12794 9, // GR64_ArgRef_and_GR64_TC:sub_16bit -> GR16_NOREX2
12795 0, // GR64_ArgRef_and_GR64_TC:sub_16bit_hi
12796 42, // GR64_ArgRef_and_GR64_TC:sub_32bit -> GR32_NOREX2_NOSP
12797 0, // GR64_ArgRef_and_GR64_TC:sub_mask_0
12798 0, // GR64_ArgRef_and_GR64_TC:sub_mask_1
12799 0, // GR64_ArgRef_and_GR64_TC:sub_xmm
12800 0, // GR64_ArgRef_and_GR64_TC:sub_ymm
12801 },
12802 { // GR64_and_LOW32_ADDR_ACCESS
12803 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit
12804 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi
12805 0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi_phony
12806 0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit
12807 0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit_hi
12808 0, // GR64_and_LOW32_ADDR_ACCESS:sub_32bit
12809 0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_0
12810 0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_1
12811 0, // GR64_and_LOW32_ADDR_ACCESS:sub_xmm
12812 0, // GR64_and_LOW32_ADDR_ACCESS:sub_ymm
12813 },
12814 { // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
12815 6, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
12816 5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
12817 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
12818 22, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
12819 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit_hi
12820 63, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_32bit -> GR32_ABCD_and_GR32_BSI
12821 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_0
12822 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_1
12823 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_xmm
12824 0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_ymm
12825 },
12826 { // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
12827 6, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit -> GR8_ABCD_L
12828 5, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi -> GR8_ABCD_H
12829 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_8bit_hi_phony
12830 22, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit -> GR16_ABCD
12831 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_16bit_hi
12832 64, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_32bit -> GR32_AD_and_GR32_ArgRef
12833 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_0
12834 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_mask_1
12835 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_xmm
12836 0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef:sub_ymm
12837 },
12838 { // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
12839 6, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit -> GR8_ABCD_L
12840 5, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
12841 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_8bit_hi_phony
12842 22, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit -> GR16_ABCD
12843 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_16bit_hi
12844 65, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_32bit -> GR32_ArgRef_and_GR32_CB
12845 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_0
12846 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_mask_1
12847 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_xmm
12848 0, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB:sub_ymm
12849 },
12850 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
12851 3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8_NOREX2
12852 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
12853 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
12854 10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
12855 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
12856 66, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
12857 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_0
12858 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_1
12859 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_xmm
12860 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_ymm
12861 },
12862 { // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
12863 3, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit -> GR8_NOREX2
12864 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi
12865 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
12866 10, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
12867 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit_hi
12868 67, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_32bit -> GR32_BPSP_and_GR32_TC
12869 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_0
12870 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_1
12871 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_xmm
12872 0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_ymm
12873 },
12874 { // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
12875 3, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
12876 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi
12877 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
12878 10, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
12879 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit_hi
12880 68, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_32bit -> GR32_BSI_and_GR32_SIDI
12881 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_0
12882 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_1
12883 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_xmm
12884 0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_ymm
12885 },
12886 { // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
12887 3, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8_NOREX2
12888 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
12889 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
12890 10, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
12891 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
12892 69, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_32bit -> GR32_DIBP_and_GR32_SIDI
12893 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_0
12894 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_1
12895 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_xmm
12896 0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_ymm
12897 },
12898 { // RST
12899 0, // RST:sub_8bit
12900 0, // RST:sub_8bit_hi
12901 0, // RST:sub_8bit_hi_phony
12902 0, // RST:sub_16bit
12903 0, // RST:sub_16bit_hi
12904 0, // RST:sub_32bit
12905 0, // RST:sub_mask_0
12906 0, // RST:sub_mask_1
12907 0, // RST:sub_xmm
12908 0, // RST:sub_ymm
12909 },
12910 { // RFP80
12911 0, // RFP80:sub_8bit
12912 0, // RFP80:sub_8bit_hi
12913 0, // RFP80:sub_8bit_hi_phony
12914 0, // RFP80:sub_16bit
12915 0, // RFP80:sub_16bit_hi
12916 0, // RFP80:sub_32bit
12917 0, // RFP80:sub_mask_0
12918 0, // RFP80:sub_mask_1
12919 0, // RFP80:sub_xmm
12920 0, // RFP80:sub_ymm
12921 },
12922 { // RFP80_7
12923 0, // RFP80_7:sub_8bit
12924 0, // RFP80_7:sub_8bit_hi
12925 0, // RFP80_7:sub_8bit_hi_phony
12926 0, // RFP80_7:sub_16bit
12927 0, // RFP80_7:sub_16bit_hi
12928 0, // RFP80_7:sub_32bit
12929 0, // RFP80_7:sub_mask_0
12930 0, // RFP80_7:sub_mask_1
12931 0, // RFP80_7:sub_xmm
12932 0, // RFP80_7:sub_ymm
12933 },
12934 { // VR128X
12935 0, // VR128X:sub_8bit
12936 0, // VR128X:sub_8bit_hi
12937 0, // VR128X:sub_8bit_hi_phony
12938 0, // VR128X:sub_16bit
12939 0, // VR128X:sub_16bit_hi
12940 0, // VR128X:sub_32bit
12941 0, // VR128X:sub_mask_0
12942 0, // VR128X:sub_mask_1
12943 0, // VR128X:sub_xmm
12944 0, // VR128X:sub_ymm
12945 },
12946 { // VR128
12947 0, // VR128:sub_8bit
12948 0, // VR128:sub_8bit_hi
12949 0, // VR128:sub_8bit_hi_phony
12950 0, // VR128:sub_16bit
12951 0, // VR128:sub_16bit_hi
12952 0, // VR128:sub_32bit
12953 0, // VR128:sub_mask_0
12954 0, // VR128:sub_mask_1
12955 0, // VR128:sub_xmm
12956 0, // VR128:sub_ymm
12957 },
12958 { // VR256X
12959 0, // VR256X:sub_8bit
12960 0, // VR256X:sub_8bit_hi
12961 0, // VR256X:sub_8bit_hi_phony
12962 0, // VR256X:sub_16bit
12963 0, // VR256X:sub_16bit_hi
12964 0, // VR256X:sub_32bit
12965 0, // VR256X:sub_mask_0
12966 0, // VR256X:sub_mask_1
12967 24, // VR256X:sub_xmm -> FR16X
12968 0, // VR256X:sub_ymm
12969 },
12970 { // VR256
12971 0, // VR256:sub_8bit
12972 0, // VR256:sub_8bit_hi
12973 0, // VR256:sub_8bit_hi_phony
12974 0, // VR256:sub_16bit
12975 0, // VR256:sub_16bit_hi
12976 0, // VR256:sub_32bit
12977 0, // VR256:sub_mask_0
12978 0, // VR256:sub_mask_1
12979 25, // VR256:sub_xmm -> FR16
12980 0, // VR256:sub_ymm
12981 },
12982 { // VR512
12983 0, // VR512:sub_8bit
12984 0, // VR512:sub_8bit_hi
12985 0, // VR512:sub_8bit_hi_phony
12986 0, // VR512:sub_16bit
12987 0, // VR512:sub_16bit_hi
12988 0, // VR512:sub_32bit
12989 0, // VR512:sub_mask_0
12990 0, // VR512:sub_mask_1
12991 24, // VR512:sub_xmm -> FR16X
12992 130, // VR512:sub_ymm -> VR256X
12993 },
12994 { // VR512_0_15
12995 0, // VR512_0_15:sub_8bit
12996 0, // VR512_0_15:sub_8bit_hi
12997 0, // VR512_0_15:sub_8bit_hi_phony
12998 0, // VR512_0_15:sub_16bit
12999 0, // VR512_0_15:sub_16bit_hi
13000 0, // VR512_0_15:sub_32bit
13001 0, // VR512_0_15:sub_mask_0
13002 0, // VR512_0_15:sub_mask_1
13003 25, // VR512_0_15:sub_xmm -> FR16
13004 131, // VR512_0_15:sub_ymm -> VR256
13005 },
13006 { // TILE
13007 0, // TILE:sub_8bit
13008 0, // TILE:sub_8bit_hi
13009 0, // TILE:sub_8bit_hi_phony
13010 0, // TILE:sub_16bit
13011 0, // TILE:sub_16bit_hi
13012 0, // TILE:sub_32bit
13013 0, // TILE:sub_mask_0
13014 0, // TILE:sub_mask_1
13015 0, // TILE:sub_xmm
13016 0, // TILE:sub_ymm
13017 },
13018 };
13019 assert(RC && "Missing regclass");
13020 if (!Idx) return RC;
13021 --Idx;
13022 assert(Idx < 10 && "Bad subreg");
13023 unsigned TV = Table[RC->getID()][Idx];
13024 return TV ? getRegClass(TV - 1) : nullptr;
13025}
13026
13027/// Get the weight in units of pressure for this register class.
13028const RegClassWeight &X86GenRegisterInfo::
13029getRegClassWeight(const TargetRegisterClass *RC) const {
13030 static const RegClassWeight RCWeightTable[] = {
13031 {1, 36}, // GR8
13032 {0, 0}, // GRH8
13033 {1, 20}, // GR8_NOREX2
13034 {1, 8}, // GR8_NOREX
13035 {1, 4}, // GR8_ABCD_H
13036 {1, 4}, // GR8_ABCD_L
13037 {0, 0}, // GRH16
13038 {2, 64}, // GR16
13039 {2, 32}, // GR16_NOREX2
13040 {2, 16}, // GR16_NOREX
13041 {1, 8}, // VK1
13042 {1, 8}, // VK16
13043 {1, 8}, // VK2
13044 {1, 8}, // VK4
13045 {1, 8}, // VK8
13046 {1, 7}, // VK16WM
13047 {1, 7}, // VK1WM
13048 {1, 7}, // VK2WM
13049 {1, 7}, // VK4WM
13050 {1, 7}, // VK8WM
13051 {1, 6}, // SEGMENT_REG
13052 {2, 8}, // GR16_ABCD
13053 {0, 0}, // FPCCR
13054 {1, 32}, // FR16X
13055 {1, 16}, // FR16
13056 {2, 8}, // VK16PAIR
13057 {2, 8}, // VK1PAIR
13058 {2, 8}, // VK2PAIR
13059 {2, 8}, // VK4PAIR
13060 {2, 8}, // VK8PAIR
13061 {2, 6}, // VK1PAIR_with_sub_mask_0_in_VK1WM
13062 {2, 66}, // LOW32_ADDR_ACCESS_RBP
13063 {2, 66}, // LOW32_ADDR_ACCESS
13064 {2, 64}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
13065 {1, 32}, // FR32X
13066 {2, 64}, // GR32
13067 {2, 62}, // GR32_NOSP
13068 {2, 32}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
13069 {1, 16}, // DEBUG_REG
13070 {1, 16}, // FR32
13071 {2, 32}, // GR32_NOREX2
13072 {2, 30}, // GR32_NOREX2_NOSP
13073 {2, 16}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
13074 {2, 16}, // GR32_NOREX
13075 {1, 8}, // VK32
13076 {2, 14}, // GR32_NOREX_NOSP
13077 {1, 7}, // RFP32
13078 {1, 7}, // VK32WM
13079 {2, 8}, // GR32_ABCD
13080 {2, 8}, // GR32_TC
13081 {2, 6}, // GR32_ABCD_and_GR32_TC
13082 {2, 4}, // GR32_AD
13083 {2, 4}, // GR32_ArgRef
13084 {2, 4}, // GR32_BPSP
13085 {2, 4}, // GR32_BSI
13086 {2, 4}, // GR32_CB
13087 {2, 4}, // GR32_DC
13088 {2, 4}, // GR32_DIBP
13089 {2, 4}, // GR32_SIDI
13090 {2, 4}, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
13091 {0, 0}, // CCR
13092 {0, 0}, // DFCCR
13093 {2, 2}, // GR32_ABCD_and_GR32_BSI
13094 {2, 2}, // GR32_AD_and_GR32_ArgRef
13095 {2, 2}, // GR32_ArgRef_and_GR32_CB
13096 {2, 2}, // GR32_BPSP_and_GR32_DIBP
13097 {2, 2}, // GR32_BPSP_and_GR32_TC
13098 {2, 2}, // GR32_BSI_and_GR32_SIDI
13099 {2, 2}, // GR32_DIBP_and_GR32_SIDI
13100 {2, 2}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
13101 {2, 2}, // LOW32_ADDR_ACCESS_with_sub_32bit
13102 {1, 7}, // RFP64
13103 {2, 66}, // GR64
13104 {1, 32}, // FR64X
13105 {2, 64}, // GR64_with_sub_8bit
13106 {2, 62}, // GR64_NOSP
13107 {2, 34}, // GR64_NOREX2
13108 {1, 16}, // CONTROL_REG
13109 {1, 16}, // FR64
13110 {2, 32}, // GR64_with_sub_16bit_in_GR16_NOREX2
13111 {2, 30}, // GR64_NOREX2_NOSP
13112 {2, 26}, // GR64PLTSafe
13113 {2, 20}, // GR64_TC
13114 {2, 18}, // GR64_NOREX
13115 {2, 18}, // GR64_TCW64
13116 {2, 18}, // GR64_TC_with_sub_8bit
13117 {2, 16}, // GR64_NOREX2_NOSP_and_GR64_TC
13118 {2, 16}, // GR64_TCW64_with_sub_8bit
13119 {2, 16}, // GR64_TC_and_GR64_TCW64
13120 {2, 16}, // GR64_with_sub_16bit_in_GR16_NOREX
13121 {1, 8}, // VK64
13122 {1, 8}, // VR64
13123 {2, 14}, // GR64PLTSafe_and_GR64_TC
13124 {2, 14}, // GR64_NOREX2_NOSP_and_GR64_TCW64
13125 {2, 14}, // GR64_NOREX_NOSP
13126 {2, 14}, // GR64_NOREX_and_GR64_TC
13127 {2, 14}, // GR64_TCW64_and_GR64_TC_with_sub_8bit
13128 {1, 7}, // VK64WM
13129 {2, 12}, // GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64
13130 {2, 12}, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
13131 {2, 10}, // GR64PLTSafe_and_GR64_TCW64
13132 {2, 10}, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
13133 {2, 10}, // GR64_NOREX_and_GR64_TCW64
13134 {2, 8}, // GR64_ABCD
13135 {2, 8}, // GR64_with_sub_32bit_in_GR32_TC
13136 {2, 6}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
13137 {2, 4}, // GR64_AD
13138 {2, 4}, // GR64_ArgRef
13139 {2, 4}, // GR64_and_LOW32_ADDR_ACCESS_RBP
13140 {2, 4}, // GR64_with_sub_32bit_in_GR32_ArgRef
13141 {2, 4}, // GR64_with_sub_32bit_in_GR32_BPSP
13142 {2, 4}, // GR64_with_sub_32bit_in_GR32_BSI
13143 {2, 4}, // GR64_with_sub_32bit_in_GR32_CB
13144 {2, 4}, // GR64_with_sub_32bit_in_GR32_DIBP
13145 {2, 4}, // GR64_with_sub_32bit_in_GR32_SIDI
13146 {2, 2}, // GR64_ArgRef_and_GR64_TC
13147 {2, 2}, // GR64_and_LOW32_ADDR_ACCESS
13148 {2, 2}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
13149 {2, 2}, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef
13150 {2, 2}, // GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB
13151 {2, 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
13152 {2, 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
13153 {2, 2}, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
13154 {2, 2}, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
13155 {0, 0}, // RST
13156 {1, 7}, // RFP80
13157 {0, 0}, // RFP80_7
13158 {1, 32}, // VR128X
13159 {1, 16}, // VR128
13160 {1, 32}, // VR256X
13161 {1, 16}, // VR256
13162 {1, 32}, // VR512
13163 {1, 16}, // VR512_0_15
13164 {1, 8}, // TILE
13165 };
13166 return RCWeightTable[RC->getID()];
13167}
13168
13169/// Get the weight in units of pressure for this register unit.
13170unsigned X86GenRegisterInfo::
13171getRegUnitWeight(unsigned RegUnit) const {
13172 assert(RegUnit < 221 && "invalid register unit");
13173 // All register units have unit weight.
13174 return 1;
13175}
13176
13177
13178// Get the number of dimensions of register pressure.
13179unsigned X86GenRegisterInfo::getNumRegPressureSets() const {
13180 return 36;
13181}
13182
13183// Get the name of this register unit pressure set.
13184const char *X86GenRegisterInfo::
13185getRegPressureSetName(unsigned Idx) const {
13186 static const char *PressureNameTable[] = {
13187 "SEGMENT_REG",
13188 "GR32_BPSP",
13189 "LOW32_ADDR_ACCESS_with_sub_32bit",
13190 "GR32_BSI",
13191 "GR32_SIDI",
13192 "GR32_DIBP_with_GR32_SIDI",
13193 "GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit",
13194 "RFP32",
13195 "GR8_ABCD_H_with_GR32_BSI",
13196 "GR8_ABCD_L_with_GR32_BSI",
13197 "VK1",
13198 "VR64",
13199 "TILE",
13200 "GR8_NOREX",
13201 "GR32_TC",
13202 "GR32_BPSP_with_GR32_TC",
13203 "FR16",
13204 "DEBUG_REG",
13205 "CONTROL_REG",
13206 "GR64_NOREX",
13207 "GR64_TCW64",
13208 "GR32_BPSP_with_GR64_TCW64",
13209 "GR64_TC_with_GR64_TCW64",
13210 "GR64_TC",
13211 "FR16X",
13212 "GR64PLTSafe_with_GR64_TC",
13213 "GR8",
13214 "GR8_with_GR32_DIBP",
13215 "GR8_with_GR32_BSI",
13216 "GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit",
13217 "GR8_with_GR64_NOREX",
13218 "GR8_with_GR64_TCW64",
13219 "GR8_with_GR64_TC",
13220 "GR8_with_GR64PLTSafe",
13221 "GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2",
13222 "GR16",
13223 };
13224 return PressureNameTable[Idx];
13225}
13226
13227// Get the register unit pressure limit for this dimension.
13228// This limit must be adjusted dynamically for reserved registers.
13229unsigned X86GenRegisterInfo::
13230getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
13231 static const uint8_t PressureLimitTable[] = {
13232 6, // 0: SEGMENT_REG
13233 6, // 1: GR32_BPSP
13234 6, // 2: LOW32_ADDR_ACCESS_with_sub_32bit
13235 6, // 3: GR32_BSI
13236 6, // 4: GR32_SIDI
13237 6, // 5: GR32_DIBP_with_GR32_SIDI
13238 6, // 6: GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit
13239 7, // 7: RFP32
13240 7, // 8: GR8_ABCD_H_with_GR32_BSI
13241 7, // 9: GR8_ABCD_L_with_GR32_BSI
13242 8, // 10: VK1
13243 8, // 11: VR64
13244 8, // 12: TILE
13245 10, // 13: GR8_NOREX
13246 12, // 14: GR32_TC
13247 12, // 15: GR32_BPSP_with_GR32_TC
13248 16, // 16: FR16
13249 16, // 17: DEBUG_REG
13250 16, // 18: CONTROL_REG
13251 18, // 19: GR64_NOREX
13252 20, // 20: GR64_TCW64
13253 20, // 21: GR32_BPSP_with_GR64_TCW64
13254 22, // 22: GR64_TC_with_GR64_TCW64
13255 26, // 23: GR64_TC
13256 32, // 24: FR16X
13257 34, // 25: GR64PLTSafe_with_GR64_TC
13258 38, // 26: GR8
13259 38, // 27: GR8_with_GR32_DIBP
13260 38, // 28: GR8_with_GR32_BSI
13261 39, // 29: GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit
13262 42, // 30: GR8_with_GR64_NOREX
13263 43, // 31: GR8_with_GR64_TCW64
13264 44, // 32: GR8_with_GR64_TC
13265 45, // 33: GR8_with_GR64PLTSafe
13266 48, // 34: GR8_with_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2
13267 66, // 35: GR16
13268 };
13269 return PressureLimitTable[Idx];
13270}
13271
13272/// Table of pressure sets per register class or unit.
13273static const int RCSetsTable[] = {
13274 /* 0 */ 0, -1,
13275 /* 2 */ 7, -1,
13276 /* 4 */ 10, -1,
13277 /* 6 */ 11, -1,
13278 /* 8 */ 12, -1,
13279 /* 10 */ 17, -1,
13280 /* 12 */ 18, -1,
13281 /* 14 */ 16, 24, -1,
13282 /* 17 */ 25, 35, -1,
13283 /* 20 */ 19, 23, 25, 30, 35, -1,
13284 /* 26 */ 2, 6, 15, 19, 21, 23, 25, 29, 30, 35, -1,
13285 /* 37 */ 20, 21, 22, 23, 25, 31, 35, -1,
13286 /* 45 */ 22, 23, 25, 32, 35, -1,
13287 /* 51 */ 19, 22, 23, 25, 30, 32, 35, -1,
13288 /* 59 */ 20, 21, 22, 23, 25, 31, 32, 35, -1,
13289 /* 68 */ 14, 15, 19, 20, 21, 22, 23, 25, 30, 31, 32, 35, -1,
13290 /* 81 */ 2, 6, 14, 15, 19, 20, 21, 22, 23, 25, 29, 30, 31, 32, 35, -1,
13291 /* 97 */ 25, 34, 35, -1,
13292 /* 101 */ 19, 23, 25, 30, 34, 35, -1,
13293 /* 108 */ 1, 2, 15, 19, 21, 23, 25, 26, 30, 34, 35, -1,
13294 /* 120 */ 20, 21, 22, 23, 25, 31, 34, 35, -1,
13295 /* 129 */ 22, 23, 25, 32, 34, 35, -1,
13296 /* 136 */ 19, 22, 23, 25, 30, 32, 34, 35, -1,
13297 /* 145 */ 20, 21, 22, 23, 25, 31, 32, 34, 35, -1,
13298 /* 155 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 30, 31, 32, 34, 35, -1,
13299 /* 172 */ 25, 33, 34, 35, -1,
13300 /* 177 */ 19, 23, 25, 30, 33, 34, 35, -1,
13301 /* 185 */ 1, 5, 6, 19, 23, 25, 27, 30, 33, 34, 35, -1,
13302 /* 197 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 29, 30, 33, 34, 35, -1,
13303 /* 214 */ 22, 23, 25, 32, 33, 34, 35, -1,
13304 /* 222 */ 3, 4, 8, 9, 13, 19, 23, 25, 28, 30, 32, 33, 34, 35, -1,
13305 /* 237 */ 4, 5, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
13306 /* 250 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 28, 30, 32, 33, 34, 35, -1,
13307 /* 267 */ 1, 4, 5, 6, 19, 22, 23, 25, 27, 28, 30, 32, 33, 34, 35, -1,
13308 /* 283 */ 20, 21, 22, 23, 25, 31, 32, 33, 34, 35, -1,
13309 /* 294 */ 3, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
13310 /* 312 */ 8, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
13311 /* 330 */ 3, 4, 8, 9, 13, 14, 19, 20, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
13312 /* 351 */ 1, 2, 5, 6, 15, 19, 21, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
13313 /* 371 */ 1, 4, 5, 6, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
13314 /* 390 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
13315 /* 411 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
13316 /* 432 */ 3, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
13317 /* 453 */ 3, 8, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
13318 /* 475 */ 3, 9, 13, 14, 15, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, -1,
13319};
13320
13321/// Get the dimensions of register pressure impacted by this register class.
13322/// Returns a -1 terminated array of pressure set IDs
13323const int *X86GenRegisterInfo::
13324getRegClassPressureSets(const TargetRegisterClass *RC) const {
13325 static const uint16_t RCSetStartTable[] = {
13326 301,1,300,295,312,333,1,18,97,101,4,4,4,4,4,4,4,4,4,4,0,295,1,15,14,4,4,4,4,4,4,18,18,18,15,18,18,97,10,14,97,97,101,101,4,177,2,4,295,157,433,433,433,108,222,294,433,185,237,26,1,1,330,433,432,197,155,250,267,197,81,2,18,15,18,18,17,12,14,97,97,172,45,20,37,129,129,120,59,101,4,6,214,120,177,51,145,4,145,136,283,239,68,295,157,433,433,120,26,433,108,222,294,185,237,145,81,330,433,432,197,155,250,267,1,2,1,15,14,15,14,15,14,8,};
13327 return &RCSetsTable[RCSetStartTable[RC->getID()]];
13328}
13329
13330/// Get the dimensions of register pressure impacted by this register unit.
13331/// Returns a -1 terminated array of pressure set IDs
13332const int *X86GenRegisterInfo::
13333getRegUnitPressureSets(unsigned RegUnit) const {
13334 assert(RegUnit < 221 && "invalid register unit");
13335 static const uint16_t RUSetStartTable[] = {
13336 454,476,330,330,351,1,453,475,0,1,454,371,1,476,0,1,1,1,1,1,1,1,81,1,1,0,390,1,1,411,1,1,1,1,0,1,0,1,1,1,1,0,1,1,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,2,2,2,2,2,2,2,1,6,6,6,6,6,6,6,6,416,1,1,416,1,1,416,1,1,416,1,1,300,1,1,300,1,1,300,1,1,300,1,1,1,1,1,1,1,1,1,1,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,4,4,4,4,4,4,4,4,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,1,8,8,8,8,8,8,8,8,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,301,1,1,};
13337 return &RCSetsTable[RUSetStartTable[RegUnit]];
13338}
13339
13340extern const MCRegisterDesc X86RegDesc[];
13341extern const int16_t X86RegDiffLists[];
13342extern const LaneBitmask X86LaneMaskLists[];
13343extern const char X86RegStrings[];
13344extern const char X86RegClassStrings[];
13345extern const MCPhysReg X86RegUnitRoots[][2];
13346extern const uint16_t X86SubRegIdxLists[];
13347extern const uint16_t X86RegEncodingTable[];
13348// X86 Dwarf<->LLVM register mappings.
13349extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[];
13350extern const unsigned X86DwarfFlavour0Dwarf2LSize;
13351
13352extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[];
13353extern const unsigned X86DwarfFlavour1Dwarf2LSize;
13354
13355extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[];
13356extern const unsigned X86DwarfFlavour2Dwarf2LSize;
13357
13358extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[];
13359extern const unsigned X86EHFlavour0Dwarf2LSize;
13360
13361extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[];
13362extern const unsigned X86EHFlavour1Dwarf2LSize;
13363
13364extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[];
13365extern const unsigned X86EHFlavour2Dwarf2LSize;
13366
13367extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[];
13368extern const unsigned X86DwarfFlavour0L2DwarfSize;
13369
13370extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[];
13371extern const unsigned X86DwarfFlavour1L2DwarfSize;
13372
13373extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[];
13374extern const unsigned X86DwarfFlavour2L2DwarfSize;
13375
13376extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[];
13377extern const unsigned X86EHFlavour0L2DwarfSize;
13378
13379extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[];
13380extern const unsigned X86EHFlavour1L2DwarfSize;
13381
13382extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[];
13383extern const unsigned X86EHFlavour2L2DwarfSize;
13384
13385X86GenRegisterInfo::
13386X86GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
13387 unsigned PC, unsigned HwMode)
13388 : TargetRegisterInfo(&X86RegInfoDesc, RegisterClasses, RegisterClasses+134,
13389 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
13390 LaneBitmask(0xFFFFFFFFFFFFFFB0), RegClassInfos, VTLists, HwMode) {
13391 InitMCRegisterInfo(X86RegDesc, 388, RA, PC,
13392 X86MCRegisterClasses, 134,
13393 X86RegUnitRoots,
13394 221,
13395 X86RegDiffLists,
13396 X86LaneMaskLists,
13397 X86RegStrings,
13398 X86RegClassStrings,
13399 X86SubRegIdxLists,
13400 11,
13401 X86RegEncodingTable);
13402
13403 switch (DwarfFlavour) {
13404 default:
13405 llvm_unreachable("Unknown DWARF flavour");
13406 case 0:
13407 mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
13408 break;
13409 case 1:
13410 mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
13411 break;
13412 case 2:
13413 mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
13414 break;
13415 }
13416 switch (EHFlavour) {
13417 default:
13418 llvm_unreachable("Unknown DWARF flavour");
13419 case 0:
13420 mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
13421 break;
13422 case 1:
13423 mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
13424 break;
13425 case 2:
13426 mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
13427 break;
13428 }
13429 switch (DwarfFlavour) {
13430 default:
13431 llvm_unreachable("Unknown DWARF flavour");
13432 case 0:
13433 mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
13434 break;
13435 case 1:
13436 mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
13437 break;
13438 case 2:
13439 mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
13440 break;
13441 }
13442 switch (EHFlavour) {
13443 default:
13444 llvm_unreachable("Unknown DWARF flavour");
13445 case 0:
13446 mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
13447 break;
13448 case 1:
13449 mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
13450 break;
13451 case 2:
13452 mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
13453 break;
13454 }
13455}
13456
13457static const MCPhysReg CSR_32_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
13458static const uint32_t CSR_32_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13459static const MCPhysReg CSR_32EHRet_SaveList[] = { X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
13460static const uint32_t CSR_32EHRet_RegMask[] = { 0x0def83fe, 0xc000b701, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13461static const MCPhysReg CSR_32_AllRegs_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, 0 };
13462static const uint32_t CSR_32_AllRegs_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13463static const MCPhysReg CSR_32_AllRegs_AVX_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 0 };
13464static const uint32_t CSR_32_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x0000007f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13465static const MCPhysReg CSR_32_AllRegs_AVX512_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
13466static const uint32_t CSR_32_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x80000000, 0x007f807f, 0x7f800000, 0x07800000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13467static const MCPhysReg CSR_32_AllRegs_SSE_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
13468static const uint32_t CSR_32_AllRegs_SSE_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13469static const MCPhysReg CSR_32_RegCall_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
13470static const uint32_t CSR_32_RegCall_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13471static const MCPhysReg CSR_32_RegCall_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
13472static const uint32_t CSR_32_RegCall_NoSSE_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13473static const MCPhysReg CSR_64_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
13474static const uint32_t CSR_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13475static const MCPhysReg CSR_64EHRet_SaveList[] = { X86::RAX, X86::RDX, X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
13476static const uint32_t CSR_64EHRet_RegMask[] = { 0x09e883fe, 0x01382700, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13477static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 };
13478static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13479static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
13480static const uint32_t CSR_64_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13481static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
13482static const uint32_t CSR_64_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xffffff80, 0xffffffff, 0xffffffff, 0xffffffff, 0x07ffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13483static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
13484static const uint32_t CSR_64_AllRegs_NoSSE_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13485static const MCPhysReg CSR_64_CXX_TLS_Darwin_PE_SaveList[] = { X86::RBP, 0 };
13486static const uint32_t CSR_64_CXX_TLS_Darwin_PE_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13487static const MCPhysReg CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
13488static const uint32_t CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0x0b28ae30, 0xd160ac01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13489static const MCPhysReg CSR_64_Intel_OCL_BI_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
13490static const uint32_t CSR_64_Intel_OCL_BI_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13491static const MCPhysReg CSR_64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
13492static const uint32_t CSR_64_Intel_OCL_BI_AVX_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00007f80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13493static const MCPhysReg CSR_64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RSI, X86::R14, X86::R15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
13494static const uint32_t CSR_64_Intel_OCL_BI_AVX512_RegMask[] = { 0x01000230, 0xd0208401, 0x00000001, 0x60000000, 0x60000000, 0x60606060, 0xfff80000, 0x007fffff, 0x067fff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13495static const MCPhysReg CSR_64_MostRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
13496static const uint32_t CSR_64_MostRegs_RegMask[] = { 0x0fafaff0, 0xd1f0be01, 0x00000001, 0x7f800000, 0xffffff80, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13497static const MCPhysReg CSR_64_NoneRegs_SaveList[] = { X86::RBP, 0 };
13498static const uint32_t CSR_64_NoneRegs_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13499static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
13500static const uint32_t CSR_64_RT_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13501static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
13502static const uint32_t CSR_64_RT_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffff80, 0xfbfbfbfb, 0x00007fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13503static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, 0 };
13504static const uint32_t CSR_64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfb800000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13505static const MCPhysReg CSR_64_SwiftError_SaveList[] = { X86::RBX, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
13506static const uint32_t CSR_64_SwiftError_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x70000000, 0x70000000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13507static const MCPhysReg CSR_64_SwiftTail_SaveList[] = { X86::RBX, X86::R12, X86::R15, X86::RBP, 0 };
13508static const uint32_t CSR_64_SwiftTail_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x48000000, 0x48000000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13509static const MCPhysReg CSR_64_TLS_Darwin_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
13510static const uint32_t CSR_64_TLS_Darwin_RegMask[] = { 0x0ba8aff0, 0xd170ae01, 0x00000001, 0x7f800000, 0xff800000, 0x7fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13511static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
13512static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13513static const MCPhysReg CSR_SysV64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
13514static const uint32_t CSR_SysV64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x787f8000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13515static const MCPhysReg CSR_SysV64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
13516static const uint32_t CSR_SysV64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13517static const MCPhysReg CSR_Win32_CFGuard_Check_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::ECX, 0 };
13518static const uint32_t CSR_Win32_CFGuard_Check_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00007800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13519static const MCPhysReg CSR_Win32_CFGuard_Check_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ECX, 0 };
13520static const uint32_t CSR_Win32_CFGuard_Check_NoSSE_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13521static const MCPhysReg CSR_Win64_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
13522static const uint32_t CSR_Win64_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13523static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
13524static const uint32_t CSR_Win64_Intel_OCL_BI_AVX_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x00007fe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13525static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
13526static const uint32_t CSR_Win64_Intel_OCL_BI_AVX512_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x787fe000, 0x78787878, 0x1ff87fe0, 0xe0001f80, 0x06001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13527static const MCPhysReg CSR_Win64_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
13528static const uint32_t CSR_Win64_NoSSE_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x78000000, 0x78000000, 0x78787878, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13529static const MCPhysReg CSR_Win64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
13530static const uint32_t CSR_Win64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x7b800000, 0xfbffe000, 0x7bfbfbfb, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13531static const MCPhysReg CSR_Win64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
13532static const uint32_t CSR_Win64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e7f8000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13533static const MCPhysReg CSR_Win64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
13534static const uint32_t CSR_Win64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x7e000000, 0x7e000000, 0x7e7e7e7e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13535static const MCPhysReg CSR_Win64_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
13536static const uint32_t CSR_Win64_SwiftError_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x70000000, 0x707fe000, 0x70707070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13537static const MCPhysReg CSR_Win64_SwiftTail_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
13538static const uint32_t CSR_Win64_SwiftTail_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x48000000, 0x487fe000, 0x48484848, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
13539
13540
13541ArrayRef<const uint32_t *> X86GenRegisterInfo::getRegMasks() const {
13542 static const uint32_t *const Masks[] = {
13543 CSR_32_RegMask,
13544 CSR_32EHRet_RegMask,
13545 CSR_32_AllRegs_RegMask,
13546 CSR_32_AllRegs_AVX_RegMask,
13547 CSR_32_AllRegs_AVX512_RegMask,
13548 CSR_32_AllRegs_SSE_RegMask,
13549 CSR_32_RegCall_RegMask,
13550 CSR_32_RegCall_NoSSE_RegMask,
13551 CSR_64_RegMask,
13552 CSR_64EHRet_RegMask,
13553 CSR_64_AllRegs_RegMask,
13554 CSR_64_AllRegs_AVX_RegMask,
13555 CSR_64_AllRegs_AVX512_RegMask,
13556 CSR_64_AllRegs_NoSSE_RegMask,
13557 CSR_64_CXX_TLS_Darwin_PE_RegMask,
13558 CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask,
13559 CSR_64_Intel_OCL_BI_RegMask,
13560 CSR_64_Intel_OCL_BI_AVX_RegMask,
13561 CSR_64_Intel_OCL_BI_AVX512_RegMask,
13562 CSR_64_MostRegs_RegMask,
13563 CSR_64_NoneRegs_RegMask,
13564 CSR_64_RT_AllRegs_RegMask,
13565 CSR_64_RT_AllRegs_AVX_RegMask,
13566 CSR_64_RT_MostRegs_RegMask,
13567 CSR_64_SwiftError_RegMask,
13568 CSR_64_SwiftTail_RegMask,
13569 CSR_64_TLS_Darwin_RegMask,
13570 CSR_NoRegs_RegMask,
13571 CSR_SysV64_RegCall_RegMask,
13572 CSR_SysV64_RegCall_NoSSE_RegMask,
13573 CSR_Win32_CFGuard_Check_RegMask,
13574 CSR_Win32_CFGuard_Check_NoSSE_RegMask,
13575 CSR_Win64_RegMask,
13576 CSR_Win64_Intel_OCL_BI_AVX_RegMask,
13577 CSR_Win64_Intel_OCL_BI_AVX512_RegMask,
13578 CSR_Win64_NoSSE_RegMask,
13579 CSR_Win64_RT_MostRegs_RegMask,
13580 CSR_Win64_RegCall_RegMask,
13581 CSR_Win64_RegCall_NoSSE_RegMask,
13582 CSR_Win64_SwiftError_RegMask,
13583 CSR_Win64_SwiftTail_RegMask,
13584 };
13585 return ArrayRef(Masks);
13586}
13587
13588bool X86GenRegisterInfo::
13589isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
13590 return
13591 X86::GR64RegClass.contains(PhysReg) ||
13592 X86::GR32RegClass.contains(PhysReg) ||
13593 X86::GR16RegClass.contains(PhysReg) ||
13594 X86::GR8RegClass.contains(PhysReg) ||
13595 false;
13596}
13597
13598bool X86GenRegisterInfo::
13599isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
13600 return
13601 X86::DEBUG_REGRegClass.contains(PhysReg) ||
13602 X86::CONTROL_REGRegClass.contains(PhysReg) ||
13603 X86::CCRRegClass.contains(PhysReg) ||
13604 X86::FPCCRRegClass.contains(PhysReg) ||
13605 X86::DFCCRRegClass.contains(PhysReg) ||
13606 X86::TILERegClass.contains(PhysReg) ||
13607 X86::VK1PAIRRegClass.contains(PhysReg) ||
13608 X86::VK2PAIRRegClass.contains(PhysReg) ||
13609 X86::VK4PAIRRegClass.contains(PhysReg) ||
13610 X86::VK8PAIRRegClass.contains(PhysReg) ||
13611 X86::VK16PAIRRegClass.contains(PhysReg) ||
13612 false;
13613}
13614
13615bool X86GenRegisterInfo::
13616isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
13617 return
13618 false;
13619}
13620
13621bool X86GenRegisterInfo::
13622isConstantPhysReg(MCRegister PhysReg) const {
13623 return
13624 false;
13625}
13626
13627ArrayRef<const char *> X86GenRegisterInfo::getRegMaskNames() const {
13628 static const char *Names[] = {
13629 "CSR_32",
13630 "CSR_32EHRet",
13631 "CSR_32_AllRegs",
13632 "CSR_32_AllRegs_AVX",
13633 "CSR_32_AllRegs_AVX512",
13634 "CSR_32_AllRegs_SSE",
13635 "CSR_32_RegCall",
13636 "CSR_32_RegCall_NoSSE",
13637 "CSR_64",
13638 "CSR_64EHRet",
13639 "CSR_64_AllRegs",
13640 "CSR_64_AllRegs_AVX",
13641 "CSR_64_AllRegs_AVX512",
13642 "CSR_64_AllRegs_NoSSE",
13643 "CSR_64_CXX_TLS_Darwin_PE",
13644 "CSR_64_CXX_TLS_Darwin_ViaCopy",
13645 "CSR_64_Intel_OCL_BI",
13646 "CSR_64_Intel_OCL_BI_AVX",
13647 "CSR_64_Intel_OCL_BI_AVX512",
13648 "CSR_64_MostRegs",
13649 "CSR_64_NoneRegs",
13650 "CSR_64_RT_AllRegs",
13651 "CSR_64_RT_AllRegs_AVX",
13652 "CSR_64_RT_MostRegs",
13653 "CSR_64_SwiftError",
13654 "CSR_64_SwiftTail",
13655 "CSR_64_TLS_Darwin",
13656 "CSR_NoRegs",
13657 "CSR_SysV64_RegCall",
13658 "CSR_SysV64_RegCall_NoSSE",
13659 "CSR_Win32_CFGuard_Check",
13660 "CSR_Win32_CFGuard_Check_NoSSE",
13661 "CSR_Win64",
13662 "CSR_Win64_Intel_OCL_BI_AVX",
13663 "CSR_Win64_Intel_OCL_BI_AVX512",
13664 "CSR_Win64_NoSSE",
13665 "CSR_Win64_RT_MostRegs",
13666 "CSR_Win64_RegCall",
13667 "CSR_Win64_RegCall_NoSSE",
13668 "CSR_Win64_SwiftError",
13669 "CSR_Win64_SwiftTail",
13670 };
13671 return ArrayRef(Names);
13672}
13673
13674const X86FrameLowering *
13675X86GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
13676 return static_cast<const X86FrameLowering *>(
13677 MF.getSubtarget().getFrameLowering());
13678}
13679
13680} // end namespace llvm
13681
13682#endif // GET_REGINFO_TARGET_DESC
13683
13684