1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm {
12
13namespace XCore {
14 enum {
15 PHI = 0,
16 INLINEASM = 1,
17 INLINEASM_BR = 2,
18 CFI_INSTRUCTION = 3,
19 EH_LABEL = 4,
20 GC_LABEL = 5,
21 ANNOTATION_LABEL = 6,
22 KILL = 7,
23 EXTRACT_SUBREG = 8,
24 INSERT_SUBREG = 9,
25 IMPLICIT_DEF = 10,
26 SUBREG_TO_REG = 11,
27 COPY_TO_REGCLASS = 12,
28 DBG_VALUE = 13,
29 DBG_VALUE_LIST = 14,
30 DBG_INSTR_REF = 15,
31 DBG_PHI = 16,
32 DBG_LABEL = 17,
33 REG_SEQUENCE = 18,
34 COPY = 19,
35 BUNDLE = 20,
36 LIFETIME_START = 21,
37 LIFETIME_END = 22,
38 PSEUDO_PROBE = 23,
39 ARITH_FENCE = 24,
40 STACKMAP = 25,
41 FENTRY_CALL = 26,
42 PATCHPOINT = 27,
43 LOAD_STACK_GUARD = 28,
44 PREALLOCATED_SETUP = 29,
45 PREALLOCATED_ARG = 30,
46 STATEPOINT = 31,
47 LOCAL_ESCAPE = 32,
48 FAULTING_OP = 33,
49 PATCHABLE_OP = 34,
50 PATCHABLE_FUNCTION_ENTER = 35,
51 PATCHABLE_RET = 36,
52 PATCHABLE_FUNCTION_EXIT = 37,
53 PATCHABLE_TAIL_CALL = 38,
54 PATCHABLE_EVENT_CALL = 39,
55 PATCHABLE_TYPED_EVENT_CALL = 40,
56 ICALL_BRANCH_FUNNEL = 41,
57 MEMBARRIER = 42,
58 JUMP_TABLE_DEBUG_INFO = 43,
59 CONVERGENCECTRL_ENTRY = 44,
60 CONVERGENCECTRL_ANCHOR = 45,
61 CONVERGENCECTRL_LOOP = 46,
62 CONVERGENCECTRL_GLUE = 47,
63 G_ASSERT_SEXT = 48,
64 G_ASSERT_ZEXT = 49,
65 G_ASSERT_ALIGN = 50,
66 G_ADD = 51,
67 G_SUB = 52,
68 G_MUL = 53,
69 G_SDIV = 54,
70 G_UDIV = 55,
71 G_SREM = 56,
72 G_UREM = 57,
73 G_SDIVREM = 58,
74 G_UDIVREM = 59,
75 G_AND = 60,
76 G_OR = 61,
77 G_XOR = 62,
78 G_IMPLICIT_DEF = 63,
79 G_PHI = 64,
80 G_FRAME_INDEX = 65,
81 G_GLOBAL_VALUE = 66,
82 G_PTRAUTH_GLOBAL_VALUE = 67,
83 G_CONSTANT_POOL = 68,
84 G_EXTRACT = 69,
85 G_UNMERGE_VALUES = 70,
86 G_INSERT = 71,
87 G_MERGE_VALUES = 72,
88 G_BUILD_VECTOR = 73,
89 G_BUILD_VECTOR_TRUNC = 74,
90 G_CONCAT_VECTORS = 75,
91 G_PTRTOINT = 76,
92 G_INTTOPTR = 77,
93 G_BITCAST = 78,
94 G_FREEZE = 79,
95 G_CONSTANT_FOLD_BARRIER = 80,
96 G_INTRINSIC_FPTRUNC_ROUND = 81,
97 G_INTRINSIC_TRUNC = 82,
98 G_INTRINSIC_ROUND = 83,
99 G_INTRINSIC_LRINT = 84,
100 G_INTRINSIC_LLRINT = 85,
101 G_INTRINSIC_ROUNDEVEN = 86,
102 G_READCYCLECOUNTER = 87,
103 G_READSTEADYCOUNTER = 88,
104 G_LOAD = 89,
105 G_SEXTLOAD = 90,
106 G_ZEXTLOAD = 91,
107 G_INDEXED_LOAD = 92,
108 G_INDEXED_SEXTLOAD = 93,
109 G_INDEXED_ZEXTLOAD = 94,
110 G_STORE = 95,
111 G_INDEXED_STORE = 96,
112 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97,
113 G_ATOMIC_CMPXCHG = 98,
114 G_ATOMICRMW_XCHG = 99,
115 G_ATOMICRMW_ADD = 100,
116 G_ATOMICRMW_SUB = 101,
117 G_ATOMICRMW_AND = 102,
118 G_ATOMICRMW_NAND = 103,
119 G_ATOMICRMW_OR = 104,
120 G_ATOMICRMW_XOR = 105,
121 G_ATOMICRMW_MAX = 106,
122 G_ATOMICRMW_MIN = 107,
123 G_ATOMICRMW_UMAX = 108,
124 G_ATOMICRMW_UMIN = 109,
125 G_ATOMICRMW_FADD = 110,
126 G_ATOMICRMW_FSUB = 111,
127 G_ATOMICRMW_FMAX = 112,
128 G_ATOMICRMW_FMIN = 113,
129 G_ATOMICRMW_UINC_WRAP = 114,
130 G_ATOMICRMW_UDEC_WRAP = 115,
131 G_FENCE = 116,
132 G_PREFETCH = 117,
133 G_BRCOND = 118,
134 G_BRINDIRECT = 119,
135 G_INVOKE_REGION_START = 120,
136 G_INTRINSIC = 121,
137 G_INTRINSIC_W_SIDE_EFFECTS = 122,
138 G_INTRINSIC_CONVERGENT = 123,
139 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124,
140 G_ANYEXT = 125,
141 G_TRUNC = 126,
142 G_CONSTANT = 127,
143 G_FCONSTANT = 128,
144 G_VASTART = 129,
145 G_VAARG = 130,
146 G_SEXT = 131,
147 G_SEXT_INREG = 132,
148 G_ZEXT = 133,
149 G_SHL = 134,
150 G_LSHR = 135,
151 G_ASHR = 136,
152 G_FSHL = 137,
153 G_FSHR = 138,
154 G_ROTR = 139,
155 G_ROTL = 140,
156 G_ICMP = 141,
157 G_FCMP = 142,
158 G_SCMP = 143,
159 G_UCMP = 144,
160 G_SELECT = 145,
161 G_UADDO = 146,
162 G_UADDE = 147,
163 G_USUBO = 148,
164 G_USUBE = 149,
165 G_SADDO = 150,
166 G_SADDE = 151,
167 G_SSUBO = 152,
168 G_SSUBE = 153,
169 G_UMULO = 154,
170 G_SMULO = 155,
171 G_UMULH = 156,
172 G_SMULH = 157,
173 G_UADDSAT = 158,
174 G_SADDSAT = 159,
175 G_USUBSAT = 160,
176 G_SSUBSAT = 161,
177 G_USHLSAT = 162,
178 G_SSHLSAT = 163,
179 G_SMULFIX = 164,
180 G_UMULFIX = 165,
181 G_SMULFIXSAT = 166,
182 G_UMULFIXSAT = 167,
183 G_SDIVFIX = 168,
184 G_UDIVFIX = 169,
185 G_SDIVFIXSAT = 170,
186 G_UDIVFIXSAT = 171,
187 G_FADD = 172,
188 G_FSUB = 173,
189 G_FMUL = 174,
190 G_FMA = 175,
191 G_FMAD = 176,
192 G_FDIV = 177,
193 G_FREM = 178,
194 G_FPOW = 179,
195 G_FPOWI = 180,
196 G_FEXP = 181,
197 G_FEXP2 = 182,
198 G_FEXP10 = 183,
199 G_FLOG = 184,
200 G_FLOG2 = 185,
201 G_FLOG10 = 186,
202 G_FLDEXP = 187,
203 G_FFREXP = 188,
204 G_FNEG = 189,
205 G_FPEXT = 190,
206 G_FPTRUNC = 191,
207 G_FPTOSI = 192,
208 G_FPTOUI = 193,
209 G_SITOFP = 194,
210 G_UITOFP = 195,
211 G_FABS = 196,
212 G_FCOPYSIGN = 197,
213 G_IS_FPCLASS = 198,
214 G_FCANONICALIZE = 199,
215 G_FMINNUM = 200,
216 G_FMAXNUM = 201,
217 G_FMINNUM_IEEE = 202,
218 G_FMAXNUM_IEEE = 203,
219 G_FMINIMUM = 204,
220 G_FMAXIMUM = 205,
221 G_GET_FPENV = 206,
222 G_SET_FPENV = 207,
223 G_RESET_FPENV = 208,
224 G_GET_FPMODE = 209,
225 G_SET_FPMODE = 210,
226 G_RESET_FPMODE = 211,
227 G_PTR_ADD = 212,
228 G_PTRMASK = 213,
229 G_SMIN = 214,
230 G_SMAX = 215,
231 G_UMIN = 216,
232 G_UMAX = 217,
233 G_ABS = 218,
234 G_LROUND = 219,
235 G_LLROUND = 220,
236 G_BR = 221,
237 G_BRJT = 222,
238 G_VSCALE = 223,
239 G_INSERT_SUBVECTOR = 224,
240 G_EXTRACT_SUBVECTOR = 225,
241 G_INSERT_VECTOR_ELT = 226,
242 G_EXTRACT_VECTOR_ELT = 227,
243 G_SHUFFLE_VECTOR = 228,
244 G_SPLAT_VECTOR = 229,
245 G_VECTOR_COMPRESS = 230,
246 G_CTTZ = 231,
247 G_CTTZ_ZERO_UNDEF = 232,
248 G_CTLZ = 233,
249 G_CTLZ_ZERO_UNDEF = 234,
250 G_CTPOP = 235,
251 G_BSWAP = 236,
252 G_BITREVERSE = 237,
253 G_FCEIL = 238,
254 G_FCOS = 239,
255 G_FSIN = 240,
256 G_FTAN = 241,
257 G_FACOS = 242,
258 G_FASIN = 243,
259 G_FATAN = 244,
260 G_FCOSH = 245,
261 G_FSINH = 246,
262 G_FTANH = 247,
263 G_FSQRT = 248,
264 G_FFLOOR = 249,
265 G_FRINT = 250,
266 G_FNEARBYINT = 251,
267 G_ADDRSPACE_CAST = 252,
268 G_BLOCK_ADDR = 253,
269 G_JUMP_TABLE = 254,
270 G_DYN_STACKALLOC = 255,
271 G_STACKSAVE = 256,
272 G_STACKRESTORE = 257,
273 G_STRICT_FADD = 258,
274 G_STRICT_FSUB = 259,
275 G_STRICT_FMUL = 260,
276 G_STRICT_FDIV = 261,
277 G_STRICT_FREM = 262,
278 G_STRICT_FMA = 263,
279 G_STRICT_FSQRT = 264,
280 G_STRICT_FLDEXP = 265,
281 G_READ_REGISTER = 266,
282 G_WRITE_REGISTER = 267,
283 G_MEMCPY = 268,
284 G_MEMCPY_INLINE = 269,
285 G_MEMMOVE = 270,
286 G_MEMSET = 271,
287 G_BZERO = 272,
288 G_TRAP = 273,
289 G_DEBUGTRAP = 274,
290 G_UBSANTRAP = 275,
291 G_VECREDUCE_SEQ_FADD = 276,
292 G_VECREDUCE_SEQ_FMUL = 277,
293 G_VECREDUCE_FADD = 278,
294 G_VECREDUCE_FMUL = 279,
295 G_VECREDUCE_FMAX = 280,
296 G_VECREDUCE_FMIN = 281,
297 G_VECREDUCE_FMAXIMUM = 282,
298 G_VECREDUCE_FMINIMUM = 283,
299 G_VECREDUCE_ADD = 284,
300 G_VECREDUCE_MUL = 285,
301 G_VECREDUCE_AND = 286,
302 G_VECREDUCE_OR = 287,
303 G_VECREDUCE_XOR = 288,
304 G_VECREDUCE_SMAX = 289,
305 G_VECREDUCE_SMIN = 290,
306 G_VECREDUCE_UMAX = 291,
307 G_VECREDUCE_UMIN = 292,
308 G_SBFX = 293,
309 G_UBFX = 294,
310 ADJCALLSTACKDOWN = 295,
311 ADJCALLSTACKUP = 296,
312 BR_JT = 297,
313 BR_JT32 = 298,
314 EH_RETURN = 299,
315 FRAME_TO_ARGS_OFFSET = 300,
316 LDAWFI = 301,
317 LDWFI = 302,
318 SELECT_CC = 303,
319 STWFI = 304,
320 ADD_2rus = 305,
321 ADD_3r = 306,
322 ANDNOT_2r = 307,
323 AND_3r = 308,
324 ASHR_l2rus = 309,
325 ASHR_l3r = 310,
326 BAU_1r = 311,
327 BITREV_l2r = 312,
328 BLACP_lu10 = 313,
329 BLACP_u10 = 314,
330 BLAT_lu6 = 315,
331 BLAT_u6 = 316,
332 BLA_1r = 317,
333 BLRB_lu10 = 318,
334 BLRB_u10 = 319,
335 BLRF_lu10 = 320,
336 BLRF_u10 = 321,
337 BRBF_lru6 = 322,
338 BRBF_ru6 = 323,
339 BRBT_lru6 = 324,
340 BRBT_ru6 = 325,
341 BRBU_lu6 = 326,
342 BRBU_u6 = 327,
343 BRFF_lru6 = 328,
344 BRFF_ru6 = 329,
345 BRFT_lru6 = 330,
346 BRFT_ru6 = 331,
347 BRFU_lu6 = 332,
348 BRFU_u6 = 333,
349 BRU_1r = 334,
350 BYTEREV_l2r = 335,
351 CHKCT_2r = 336,
352 CHKCT_rus = 337,
353 CLRE_0R = 338,
354 CLRPT_1R = 339,
355 CLRSR_branch_lu6 = 340,
356 CLRSR_branch_u6 = 341,
357 CLRSR_lu6 = 342,
358 CLRSR_u6 = 343,
359 CLZ_l2r = 344,
360 CRC8_l4r = 345,
361 CRC_l3r = 346,
362 DCALL_0R = 347,
363 DENTSP_0R = 348,
364 DGETREG_1r = 349,
365 DIVS_l3r = 350,
366 DIVU_l3r = 351,
367 DRESTSP_0R = 352,
368 DRET_0R = 353,
369 ECALLF_1r = 354,
370 ECALLT_1r = 355,
371 EDU_1r = 356,
372 EEF_2r = 357,
373 EET_2r = 358,
374 EEU_1r = 359,
375 ENDIN_2r = 360,
376 ENTSP_lu6 = 361,
377 ENTSP_u6 = 362,
378 EQ_2rus = 363,
379 EQ_3r = 364,
380 EXTDP_lu6 = 365,
381 EXTDP_u6 = 366,
382 EXTSP_lu6 = 367,
383 EXTSP_u6 = 368,
384 FREER_1r = 369,
385 FREET_0R = 370,
386 GETD_l2r = 371,
387 GETED_0R = 372,
388 GETET_0R = 373,
389 GETID_0R = 374,
390 GETKEP_0R = 375,
391 GETKSP_0R = 376,
392 GETN_l2r = 377,
393 GETPS_l2r = 378,
394 GETR_rus = 379,
395 GETSR_lu6 = 380,
396 GETSR_u6 = 381,
397 GETST_2r = 382,
398 GETTS_2r = 383,
399 INCT_2r = 384,
400 INITCP_2r = 385,
401 INITDP_2r = 386,
402 INITLR_l2r = 387,
403 INITPC_2r = 388,
404 INITSP_2r = 389,
405 INPW_l2rus = 390,
406 INSHR_2r = 391,
407 INT_2r = 392,
408 IN_2r = 393,
409 KCALL_1r = 394,
410 KCALL_lu6 = 395,
411 KCALL_u6 = 396,
412 KENTSP_lu6 = 397,
413 KENTSP_u6 = 398,
414 KRESTSP_lu6 = 399,
415 KRESTSP_u6 = 400,
416 KRET_0R = 401,
417 LADD_l5r = 402,
418 LD16S_3r = 403,
419 LD8U_3r = 404,
420 LDA16B_l3r = 405,
421 LDA16F_l3r = 406,
422 LDAPB_lu10 = 407,
423 LDAPB_u10 = 408,
424 LDAPF_lu10 = 409,
425 LDAPF_lu10_ba = 410,
426 LDAPF_u10 = 411,
427 LDAWB_l2rus = 412,
428 LDAWB_l3r = 413,
429 LDAWCP_lu6 = 414,
430 LDAWCP_u6 = 415,
431 LDAWDP_lru6 = 416,
432 LDAWDP_ru6 = 417,
433 LDAWF_l2rus = 418,
434 LDAWF_l3r = 419,
435 LDAWSP_lru6 = 420,
436 LDAWSP_ru6 = 421,
437 LDC_lru6 = 422,
438 LDC_ru6 = 423,
439 LDET_0R = 424,
440 LDIVU_l5r = 425,
441 LDSED_0R = 426,
442 LDSPC_0R = 427,
443 LDSSR_0R = 428,
444 LDWCP_lru6 = 429,
445 LDWCP_lu10 = 430,
446 LDWCP_ru6 = 431,
447 LDWCP_u10 = 432,
448 LDWDP_lru6 = 433,
449 LDWDP_ru6 = 434,
450 LDWSP_lru6 = 435,
451 LDWSP_ru6 = 436,
452 LDW_2rus = 437,
453 LDW_3r = 438,
454 LMUL_l6r = 439,
455 LSS_3r = 440,
456 LSUB_l5r = 441,
457 LSU_3r = 442,
458 MACCS_l4r = 443,
459 MACCU_l4r = 444,
460 MJOIN_1r = 445,
461 MKMSK_2r = 446,
462 MKMSK_rus = 447,
463 MSYNC_1r = 448,
464 MUL_l3r = 449,
465 NEG = 450,
466 NOT = 451,
467 OR_3r = 452,
468 OUTCT_2r = 453,
469 OUTCT_rus = 454,
470 OUTPW_l2rus = 455,
471 OUTSHR_2r = 456,
472 OUTT_2r = 457,
473 OUT_2r = 458,
474 PEEK_2r = 459,
475 REMS_l3r = 460,
476 REMU_l3r = 461,
477 RETSP_lu6 = 462,
478 RETSP_u6 = 463,
479 SETCLK_l2r = 464,
480 SETCP_1r = 465,
481 SETC_l2r = 466,
482 SETC_lru6 = 467,
483 SETC_ru6 = 468,
484 SETDP_1r = 469,
485 SETD_2r = 470,
486 SETEV_1r = 471,
487 SETKEP_0R = 472,
488 SETN_l2r = 473,
489 SETPSC_2r = 474,
490 SETPS_l2r = 475,
491 SETPT_2r = 476,
492 SETRDY_l2r = 477,
493 SETSP_1r = 478,
494 SETSR_branch_lu6 = 479,
495 SETSR_branch_u6 = 480,
496 SETSR_lu6 = 481,
497 SETSR_u6 = 482,
498 SETTW_l2r = 483,
499 SETV_1r = 484,
500 SEXT_2r = 485,
501 SEXT_rus = 486,
502 SHL_2rus = 487,
503 SHL_3r = 488,
504 SHR_2rus = 489,
505 SHR_3r = 490,
506 SSYNC_0r = 491,
507 ST16_l3r = 492,
508 ST8_l3r = 493,
509 STET_0R = 494,
510 STSED_0R = 495,
511 STSPC_0R = 496,
512 STSSR_0R = 497,
513 STWDP_lru6 = 498,
514 STWDP_ru6 = 499,
515 STWSP_lru6 = 500,
516 STWSP_ru6 = 501,
517 STW_2rus = 502,
518 STW_l3r = 503,
519 SUB_2rus = 504,
520 SUB_3r = 505,
521 SYNCR_1r = 506,
522 TESTCT_2r = 507,
523 TESTLCL_l2r = 508,
524 TESTWCT_2r = 509,
525 TSETMR_2r = 510,
526 TSETR_3r = 511,
527 TSTART_1R = 512,
528 WAITEF_1R = 513,
529 WAITET_1R = 514,
530 WAITEU_0R = 515,
531 XOR_l3r = 516,
532 ZEXT_2r = 517,
533 ZEXT_rus = 518,
534 INSTRUCTION_LIST_END = 519
535 };
536
537} // end namespace XCore
538} // end namespace llvm
539#endif // GET_INSTRINFO_ENUM
540
541#ifdef GET_INSTRINFO_SCHED_ENUM
542#undef GET_INSTRINFO_SCHED_ENUM
543namespace llvm {
544
545namespace XCore {
546namespace Sched {
547 enum {
548 NoInstrModel = 0,
549 SCHED_LIST_END = 1
550 };
551} // end namespace Sched
552} // end namespace XCore
553} // end namespace llvm
554#endif // GET_INSTRINFO_SCHED_ENUM
555
556#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
557namespace llvm {
558
559struct XCoreInstrTable {
560 MCInstrDesc Insts[519];
561 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
562 MCOperandInfo OperandInfo[213];
563 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
564 MCPhysReg ImplicitOps[11];
565};
566
567} // end namespace llvm
568#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
569
570#ifdef GET_INSTRINFO_MC_DESC
571#undef GET_INSTRINFO_MC_DESC
572namespace llvm {
573
574static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
575static constexpr unsigned XCoreImpOpBase = sizeof XCoreInstrTable::OperandInfo / (sizeof(MCPhysReg));
576
577extern const XCoreInstrTable XCoreDescs = {
578 {
579 { 518, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 205, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #518 = ZEXT_rus
580 { 517, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #517 = ZEXT_2r
581 { 516, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #516 = XOR_l3r
582 { 515, 0, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #515 = WAITEU_0R
583 { 514, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #514 = WAITET_1R
584 { 513, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #513 = WAITEF_1R
585 { 512, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #512 = TSTART_1R
586 { 511, 3, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 210, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #511 = TSETR_3r
587 { 510, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 208, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #510 = TSETMR_2r
588 { 509, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #509 = TESTWCT_2r
589 { 508, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #508 = TESTLCL_l2r
590 { 507, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #507 = TESTCT_2r
591 { 506, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #506 = SYNCR_1r
592 { 505, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #505 = SUB_3r
593 { 504, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #504 = SUB_2rus
594 { 503, 3, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #503 = STW_l3r
595 { 502, 3, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #502 = STW_2rus
596 { 501, 2, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 191, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #501 = STWSP_ru6
597 { 500, 2, 0, 4, 0, 1, 0, XCoreImpOpBase + 10, 191, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #500 = STWSP_lru6
598 { 499, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #499 = STWDP_ru6
599 { 498, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #498 = STWDP_lru6
600 { 497, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #497 = STSSR_0R
601 { 496, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #496 = STSPC_0R
602 { 495, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #495 = STSED_0R
603 { 494, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #494 = STET_0R
604 { 493, 3, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #493 = ST8_l3r
605 { 492, 3, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #492 = ST16_l3r
606 { 491, 0, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #491 = SSYNC_0r
607 { 490, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #490 = SHR_3r
608 { 489, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #489 = SHR_2rus
609 { 488, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #488 = SHL_3r
610 { 487, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #487 = SHL_2rus
611 { 486, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 205, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #486 = SEXT_rus
612 { 485, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #485 = SEXT_2r
613 { 484, 1, 0, 2, 0, 1, 0, XCoreImpOpBase + 9, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #484 = SETV_1r
614 { 483, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #483 = SETTW_l2r
615 { 482, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #482 = SETSR_u6
616 { 481, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #481 = SETSR_lu6
617 { 480, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #480 = SETSR_branch_u6
618 { 479, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #479 = SETSR_branch_lu6
619 { 478, 1, 0, 2, 0, 0, 1, XCoreImpOpBase + 10, 156, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #478 = SETSP_1r
620 { 477, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #477 = SETRDY_l2r
621 { 476, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #476 = SETPT_2r
622 { 475, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #475 = SETPS_l2r
623 { 474, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #474 = SETPSC_2r
624 { 473, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #473 = SETN_l2r
625 { 472, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #472 = SETKEP_0R
626 { 471, 1, 0, 2, 0, 1, 0, XCoreImpOpBase + 9, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #471 = SETEV_1r
627 { 470, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #470 = SETD_2r
628 { 469, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #469 = SETDP_1r
629 { 468, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #468 = SETC_ru6
630 { 467, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #467 = SETC_lru6
631 { 466, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #466 = SETC_l2r
632 { 465, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #465 = SETCP_1r
633 { 464, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #464 = SETCLK_l2r
634 { 463, 1, 0, 2, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #463 = RETSP_u6
635 { 462, 1, 0, 4, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #462 = RETSP_lu6
636 { 461, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #461 = REMU_l3r
637 { 460, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #460 = REMS_l3r
638 { 459, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #459 = PEEK_2r
639 { 458, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #458 = OUT_2r
640 { 457, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #457 = OUTT_2r
641 { 456, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 170, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #456 = OUTSHR_2r
642 { 455, 3, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #455 = OUTPW_l2rus
643 { 454, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #454 = OUTCT_rus
644 { 453, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = OUTCT_2r
645 { 452, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = OR_3r
646 { 451, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #451 = NOT
647 { 450, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #450 = NEG
648 { 449, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = MUL_l3r
649 { 448, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = MSYNC_1r
650 { 447, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 175, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #447 = MKMSK_rus
651 { 446, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #446 = MKMSK_2r
652 { 445, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = MJOIN_1r
653 { 444, 6, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 199, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = MACCU_l4r
654 { 443, 6, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 199, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #443 = MACCS_l4r
655 { 442, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #442 = LSU_3r
656 { 441, 5, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 186, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = LSUB_l5r
657 { 440, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = LSS_3r
658 { 439, 6, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 193, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #439 = LMUL_l6r
659 { 438, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #438 = LDW_3r
660 { 437, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #437 = LDW_2rus
661 { 436, 2, 1, 2, 0, 1, 0, XCoreImpOpBase + 10, 191, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #436 = LDWSP_ru6
662 { 435, 2, 1, 4, 0, 1, 0, XCoreImpOpBase + 10, 191, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #435 = LDWSP_lru6
663 { 434, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #434 = LDWDP_ru6
664 { 433, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #433 = LDWDP_lru6
665 { 432, 1, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #432 = LDWCP_u10
666 { 431, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #431 = LDWCP_ru6
667 { 430, 1, 0, 4, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #430 = LDWCP_lu10
668 { 429, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #429 = LDWCP_lru6
669 { 428, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #428 = LDSSR_0R
670 { 427, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #427 = LDSPC_0R
671 { 426, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #426 = LDSED_0R
672 { 425, 5, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 186, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #425 = LDIVU_l5r
673 { 424, 0, 0, 2, 0, 1, 0, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #424 = LDET_0R
674 { 423, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #423 = LDC_ru6
675 { 422, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #422 = LDC_lru6
676 { 421, 2, 1, 2, 0, 1, 0, XCoreImpOpBase + 10, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #421 = LDAWSP_ru6
677 { 420, 2, 1, 4, 0, 1, 0, XCoreImpOpBase + 10, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #420 = LDAWSP_lru6
678 { 419, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #419 = LDAWF_l3r
679 { 418, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #418 = LDAWF_l2rus
680 { 417, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #417 = LDAWDP_ru6
681 { 416, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 191, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #416 = LDAWDP_lru6
682 { 415, 1, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #415 = LDAWCP_u6
683 { 414, 1, 0, 4, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #414 = LDAWCP_lu6
684 { 413, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #413 = LDAWB_l3r
685 { 412, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #412 = LDAWB_l2rus
686 { 411, 1, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #411 = LDAPF_u10
687 { 410, 1, 0, 4, 0, 0, 1, XCoreImpOpBase + 9, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #410 = LDAPF_lu10_ba
688 { 409, 1, 0, 4, 0, 0, 1, XCoreImpOpBase + 9, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #409 = LDAPF_lu10
689 { 408, 1, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #408 = LDAPB_u10
690 { 407, 1, 0, 4, 0, 0, 1, XCoreImpOpBase + 9, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #407 = LDAPB_lu10
691 { 406, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #406 = LDA16F_l3r
692 { 405, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #405 = LDA16B_l3r
693 { 404, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #404 = LD8U_3r
694 { 403, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #403 = LD16S_3r
695 { 402, 5, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 186, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #402 = LADD_l5r
696 { 401, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #401 = KRET_0R
697 { 400, 1, 0, 2, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #400 = KRESTSP_u6
698 { 399, 1, 0, 4, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #399 = KRESTSP_lu6
699 { 398, 1, 0, 2, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #398 = KENTSP_u6
700 { 397, 1, 0, 4, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #397 = KENTSP_lu6
701 { 396, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #396 = KCALL_u6
702 { 395, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #395 = KCALL_lu6
703 { 394, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #394 = KCALL_1r
704 { 393, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = IN_2r
705 { 392, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = INT_2r
706 { 391, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 170, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = INSHR_2r
707 { 390, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = INPW_l2rus
708 { 389, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = INITSP_2r
709 { 388, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = INITPC_2r
710 { 387, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = INITLR_l2r
711 { 386, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = INITDP_2r
712 { 385, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = INITCP_2r
713 { 384, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = INCT_2r
714 { 383, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = GETTS_2r
715 { 382, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = GETST_2r
716 { 381, 1, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = GETSR_u6
717 { 380, 1, 0, 4, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = GETSR_lu6
718 { 379, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = GETR_rus
719 { 378, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = GETPS_l2r
720 { 377, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = GETN_l2r
721 { 376, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = GETKSP_0R
722 { 375, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = GETKEP_0R
723 { 374, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = GETID_0R
724 { 373, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = GETET_0R
725 { 372, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = GETED_0R
726 { 371, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = GETD_l2r
727 { 370, 0, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = FREET_0R
728 { 369, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = FREER_1r
729 { 368, 1, 0, 2, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = EXTSP_u6
730 { 367, 1, 0, 4, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = EXTSP_lu6
731 { 366, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = EXTDP_u6
732 { 365, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = EXTDP_lu6
733 { 364, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = EQ_3r
734 { 363, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = EQ_2rus
735 { 362, 1, 0, 2, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = ENTSP_u6
736 { 361, 1, 0, 4, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = ENTSP_lu6
737 { 360, 2, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = ENDIN_2r
738 { 359, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = EEU_1r
739 { 358, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = EET_2r
740 { 357, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = EEF_2r
741 { 356, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = EDU_1r
742 { 355, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = ECALLT_1r
743 { 354, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = ECALLF_1r
744 { 353, 0, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = DRET_0R
745 { 352, 0, 0, 2, 0, 0, 1, XCoreImpOpBase + 10, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = DRESTSP_0R
746 { 351, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = DIVU_l3r
747 { 350, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = DIVS_l3r
748 { 349, 1, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = DGETREG_1r
749 { 348, 0, 0, 2, 0, 1, 1, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = DENTSP_0R
750 { 347, 0, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = DCALL_0R
751 { 346, 4, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 182, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = CRC_l3r
752 { 345, 5, 2, 4, 0, 0, 0, XCoreImpOpBase + 0, 177, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = CRC8_l4r
753 { 344, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = CLZ_l2r
754 { 343, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = CLRSR_u6
755 { 342, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = CLRSR_lu6
756 { 341, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = CLRSR_branch_u6
757 { 340, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = CLRSR_branch_lu6
758 { 339, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = CLRPT_1R
759 { 338, 0, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = CLRE_0R
760 { 337, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = CHKCT_rus
761 { 336, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = CHKCT_2r
762 { 335, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = BYTEREV_l2r
763 { 334, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = BRU_1r
764 { 333, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = BRFU_u6
765 { 332, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = BRFU_lu6
766 { 331, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = BRFT_ru6
767 { 330, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = BRFT_lru6
768 { 329, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = BRFF_ru6
769 { 328, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = BRFF_lru6
770 { 327, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = BRBU_u6
771 { 326, 1, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = BRBU_lu6
772 { 325, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = BRBT_ru6
773 { 324, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = BRBT_lru6
774 { 323, 2, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = BRBF_ru6
775 { 322, 2, 0, 4, 0, 0, 0, XCoreImpOpBase + 0, 173, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = BRBF_lru6
776 { 321, 1, 0, 2, 0, 1, 6, XCoreImpOpBase + 2, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #321 = BLRF_u10
777 { 320, 1, 0, 4, 0, 1, 6, XCoreImpOpBase + 2, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #320 = BLRF_lu10
778 { 319, 1, 0, 2, 0, 1, 6, XCoreImpOpBase + 2, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = BLRB_u10
779 { 318, 1, 0, 4, 0, 1, 6, XCoreImpOpBase + 2, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = BLRB_lu10
780 { 317, 1, 0, 2, 0, 1, 6, XCoreImpOpBase + 2, 156, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = BLA_1r
781 { 316, 1, 0, 2, 0, 1, 0, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = BLAT_u6
782 { 315, 1, 0, 4, 0, 1, 0, XCoreImpOpBase + 9, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = BLAT_lu6
783 { 314, 1, 0, 2, 0, 1, 6, XCoreImpOpBase + 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = BLACP_u10
784 { 313, 1, 0, 4, 0, 1, 6, XCoreImpOpBase + 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #313 = BLACP_lu10
785 { 312, 2, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #312 = BITREV_l2r
786 { 311, 1, 0, 2, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #311 = BAU_1r
787 { 310, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = ASHR_l3r
788 { 309, 3, 1, 4, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = ASHR_l2rus
789 { 308, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = AND_3r
790 { 307, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 170, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #307 = ANDNOT_2r
791 { 306, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 167, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #306 = ADD_3r
792 { 305, 3, 1, 2, 0, 0, 0, XCoreImpOpBase + 0, 164, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #305 = ADD_2rus
793 { 304, 3, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #304 = STWFI
794 { 303, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 160, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #303 = SELECT_CC
795 { 302, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = LDWFI
796 { 301, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 157, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = LDAWFI
797 { 300, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = FRAME_TO_ARGS_OFFSET
798 { 299, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 154, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #299 = EH_RETURN
799 { 298, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #298 = BR_JT32
800 { 297, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #297 = BR_JT
801 { 296, 2, 0, 0, 0, 1, 1, XCoreImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = ADJCALLSTACKUP
802 { 295, 2, 0, 0, 0, 1, 1, XCoreImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = ADJCALLSTACKDOWN
803 { 294, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_UBFX
804 { 293, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_SBFX
805 { 292, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMIN
806 { 291, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_UMAX
807 { 290, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMIN
808 { 289, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_VECREDUCE_SMAX
809 { 288, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_VECREDUCE_XOR
810 { 287, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_VECREDUCE_OR
811 { 286, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_VECREDUCE_AND
812 { 285, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_VECREDUCE_MUL
813 { 284, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_VECREDUCE_ADD
814 { 283, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMINIMUM
815 { 282, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMAXIMUM
816 { 281, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMIN
817 { 280, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMAX
818 { 279, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_VECREDUCE_FMUL
819 { 278, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_VECREDUCE_FADD
820 { 277, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FMUL
821 { 276, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_VECREDUCE_SEQ_FADD
822 { 275, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_UBSANTRAP
823 { 274, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #274 = G_DEBUGTRAP
824 { 273, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #273 = G_TRAP
825 { 272, 3, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #272 = G_BZERO
826 { 271, 4, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_MEMSET
827 { 270, 4, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_MEMMOVE
828 { 269, 3, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_MEMCPY_INLINE
829 { 268, 4, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #268 = G_MEMCPY
830 { 267, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_WRITE_REGISTER
831 { 266, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #266 = G_READ_REGISTER
832 { 265, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_STRICT_FLDEXP
833 { 264, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_STRICT_FSQRT
834 { 263, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_STRICT_FMA
835 { 262, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_STRICT_FREM
836 { 261, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_STRICT_FDIV
837 { 260, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_STRICT_FMUL
838 { 259, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_STRICT_FSUB
839 { 258, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_STRICT_FADD
840 { 257, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_STACKRESTORE
841 { 256, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_STACKSAVE
842 { 255, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_DYN_STACKALLOC
843 { 254, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_JUMP_TABLE
844 { 253, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_BLOCK_ADDR
845 { 252, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_ADDRSPACE_CAST
846 { 251, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FNEARBYINT
847 { 250, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_FRINT
848 { 249, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_FFLOOR
849 { 248, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_FSQRT
850 { 247, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_FTANH
851 { 246, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_FSINH
852 { 245, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_FCOSH
853 { 244, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_FATAN
854 { 243, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_FASIN
855 { 242, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_FACOS
856 { 241, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_FTAN
857 { 240, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_FSIN
858 { 239, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_FCOS
859 { 238, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_FCEIL
860 { 237, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_BITREVERSE
861 { 236, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_BSWAP
862 { 235, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_CTPOP
863 { 234, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_CTLZ_ZERO_UNDEF
864 { 233, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_CTLZ
865 { 232, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_CTTZ_ZERO_UNDEF
866 { 231, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_CTTZ
867 { 230, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_VECTOR_COMPRESS
868 { 229, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_SPLAT_VECTOR
869 { 228, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_SHUFFLE_VECTOR
870 { 227, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_EXTRACT_VECTOR_ELT
871 { 226, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_INSERT_VECTOR_ELT
872 { 225, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_EXTRACT_SUBVECTOR
873 { 224, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_INSERT_SUBVECTOR
874 { 223, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_VSCALE
875 { 222, 3, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_BRJT
876 { 221, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_BR
877 { 220, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_LLROUND
878 { 219, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_LROUND
879 { 218, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_ABS
880 { 217, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_UMAX
881 { 216, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_UMIN
882 { 215, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_SMAX
883 { 214, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_SMIN
884 { 213, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_PTRMASK
885 { 212, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_PTR_ADD
886 { 211, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_RESET_FPMODE
887 { 210, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_SET_FPMODE
888 { 209, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_GET_FPMODE
889 { 208, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_RESET_FPENV
890 { 207, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_SET_FPENV
891 { 206, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_GET_FPENV
892 { 205, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FMAXIMUM
893 { 204, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_FMINIMUM
894 { 203, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_FMAXNUM_IEEE
895 { 202, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_FMINNUM_IEEE
896 { 201, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FMAXNUM
897 { 200, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FMINNUM
898 { 199, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_FCANONICALIZE
899 { 198, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_IS_FPCLASS
900 { 197, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FCOPYSIGN
901 { 196, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_FABS
902 { 195, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_UITOFP
903 { 194, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_SITOFP
904 { 193, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FPTOUI
905 { 192, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FPTOSI
906 { 191, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FPTRUNC
907 { 190, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FPEXT
908 { 189, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FNEG
909 { 188, 3, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FFREXP
910 { 187, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FLDEXP
911 { 186, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FLOG10
912 { 185, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FLOG2
913 { 184, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FLOG
914 { 183, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FEXP10
915 { 182, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FEXP2
916 { 181, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FEXP
917 { 180, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FPOWI
918 { 179, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #179 = G_FPOW
919 { 178, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #178 = G_FREM
920 { 177, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #177 = G_FDIV
921 { 176, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #176 = G_FMAD
922 { 175, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #175 = G_FMA
923 { 174, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #174 = G_FMUL
924 { 173, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #173 = G_FSUB
925 { 172, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #172 = G_FADD
926 { 171, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #171 = G_UDIVFIXSAT
927 { 170, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #170 = G_SDIVFIXSAT
928 { 169, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #169 = G_UDIVFIX
929 { 168, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #168 = G_SDIVFIX
930 { 167, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #167 = G_UMULFIXSAT
931 { 166, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #166 = G_SMULFIXSAT
932 { 165, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #165 = G_UMULFIX
933 { 164, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #164 = G_SMULFIX
934 { 163, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #163 = G_SSHLSAT
935 { 162, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #162 = G_USHLSAT
936 { 161, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #161 = G_SSUBSAT
937 { 160, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #160 = G_USUBSAT
938 { 159, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #159 = G_SADDSAT
939 { 158, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #158 = G_UADDSAT
940 { 157, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #157 = G_SMULH
941 { 156, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #156 = G_UMULH
942 { 155, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #155 = G_SMULO
943 { 154, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #154 = G_UMULO
944 { 153, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #153 = G_SSUBE
945 { 152, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #152 = G_SSUBO
946 { 151, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #151 = G_SADDE
947 { 150, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #150 = G_SADDO
948 { 149, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #149 = G_USUBE
949 { 148, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #148 = G_USUBO
950 { 147, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #147 = G_UADDE
951 { 146, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #146 = G_UADDO
952 { 145, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #145 = G_SELECT
953 { 144, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #144 = G_UCMP
954 { 143, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #143 = G_SCMP
955 { 142, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #142 = G_FCMP
956 { 141, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #141 = G_ICMP
957 { 140, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #140 = G_ROTL
958 { 139, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #139 = G_ROTR
959 { 138, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #138 = G_FSHR
960 { 137, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #137 = G_FSHL
961 { 136, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #136 = G_ASHR
962 { 135, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #135 = G_LSHR
963 { 134, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #134 = G_SHL
964 { 133, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #133 = G_ZEXT
965 { 132, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #132 = G_SEXT_INREG
966 { 131, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #131 = G_SEXT
967 { 130, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #130 = G_VAARG
968 { 129, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #129 = G_VASTART
969 { 128, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #128 = G_FCONSTANT
970 { 127, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #127 = G_CONSTANT
971 { 126, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #126 = G_TRUNC
972 { 125, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #125 = G_ANYEXT
973 { 124, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
974 { 123, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #123 = G_INTRINSIC_CONVERGENT
975 { 122, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #122 = G_INTRINSIC_W_SIDE_EFFECTS
976 { 121, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #121 = G_INTRINSIC
977 { 120, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #120 = G_INVOKE_REGION_START
978 { 119, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #119 = G_BRINDIRECT
979 { 118, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #118 = G_BRCOND
980 { 117, 4, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #117 = G_PREFETCH
981 { 116, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #116 = G_FENCE
982 { 115, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UDEC_WRAP
983 { 114, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #114 = G_ATOMICRMW_UINC_WRAP
984 { 113, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMIN
985 { 112, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FMAX
986 { 111, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FSUB
987 { 110, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #110 = G_ATOMICRMW_FADD
988 { 109, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMIN
989 { 108, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #108 = G_ATOMICRMW_UMAX
990 { 107, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MIN
991 { 106, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #106 = G_ATOMICRMW_MAX
992 { 105, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #105 = G_ATOMICRMW_XOR
993 { 104, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #104 = G_ATOMICRMW_OR
994 { 103, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #103 = G_ATOMICRMW_NAND
995 { 102, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #102 = G_ATOMICRMW_AND
996 { 101, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #101 = G_ATOMICRMW_SUB
997 { 100, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #100 = G_ATOMICRMW_ADD
998 { 99, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #99 = G_ATOMICRMW_XCHG
999 { 98, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG
1000 { 97, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #97 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1001 { 96, 5, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #96 = G_INDEXED_STORE
1002 { 95, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #95 = G_STORE
1003 { 94, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #94 = G_INDEXED_ZEXTLOAD
1004 { 93, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #93 = G_INDEXED_SEXTLOAD
1005 { 92, 5, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #92 = G_INDEXED_LOAD
1006 { 91, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #91 = G_ZEXTLOAD
1007 { 90, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #90 = G_SEXTLOAD
1008 { 89, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #89 = G_LOAD
1009 { 88, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #88 = G_READSTEADYCOUNTER
1010 { 87, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #87 = G_READCYCLECOUNTER
1011 { 86, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #86 = G_INTRINSIC_ROUNDEVEN
1012 { 85, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #85 = G_INTRINSIC_LLRINT
1013 { 84, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #84 = G_INTRINSIC_LRINT
1014 { 83, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #83 = G_INTRINSIC_ROUND
1015 { 82, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #82 = G_INTRINSIC_TRUNC
1016 { 81, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #81 = G_INTRINSIC_FPTRUNC_ROUND
1017 { 80, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #80 = G_CONSTANT_FOLD_BARRIER
1018 { 79, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #79 = G_FREEZE
1019 { 78, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #78 = G_BITCAST
1020 { 77, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #77 = G_INTTOPTR
1021 { 76, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #76 = G_PTRTOINT
1022 { 75, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #75 = G_CONCAT_VECTORS
1023 { 74, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR_TRUNC
1024 { 73, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #73 = G_BUILD_VECTOR
1025 { 72, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #72 = G_MERGE_VALUES
1026 { 71, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #71 = G_INSERT
1027 { 70, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #70 = G_UNMERGE_VALUES
1028 { 69, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #69 = G_EXTRACT
1029 { 68, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #68 = G_CONSTANT_POOL
1030 { 67, 5, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #67 = G_PTRAUTH_GLOBAL_VALUE
1031 { 66, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #66 = G_GLOBAL_VALUE
1032 { 65, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #65 = G_FRAME_INDEX
1033 { 64, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #64 = G_PHI
1034 { 63, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #63 = G_IMPLICIT_DEF
1035 { 62, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #62 = G_XOR
1036 { 61, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #61 = G_OR
1037 { 60, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #60 = G_AND
1038 { 59, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #59 = G_UDIVREM
1039 { 58, 4, 2, 0, 0, 0, 0, XCoreImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #58 = G_SDIVREM
1040 { 57, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #57 = G_UREM
1041 { 56, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #56 = G_SREM
1042 { 55, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #55 = G_UDIV
1043 { 54, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #54 = G_SDIV
1044 { 53, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #53 = G_MUL
1045 { 52, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #52 = G_SUB
1046 { 51, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #51 = G_ADD
1047 { 50, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #50 = G_ASSERT_ALIGN
1048 { 49, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #49 = G_ASSERT_ZEXT
1049 { 48, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #48 = G_ASSERT_SEXT
1050 { 47, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_GLUE
1051 { 46, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_LOOP
1052 { 45, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ANCHOR
1053 { 44, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #44 = CONVERGENCECTRL_ENTRY
1054 { 43, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #43 = JUMP_TABLE_DEBUG_INFO
1055 { 42, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #42 = MEMBARRIER
1056 { 41, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL
1057 { 40, 3, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
1058 { 39, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL
1059 { 38, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL
1060 { 37, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT
1061 { 36, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #36 = PATCHABLE_RET
1062 { 35, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER
1063 { 34, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #34 = PATCHABLE_OP
1064 { 33, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #33 = FAULTING_OP
1065 { 32, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE
1066 { 31, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #31 = STATEPOINT
1067 { 30, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG
1068 { 29, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP
1069 { 28, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD
1070 { 27, 6, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #27 = PATCHPOINT
1071 { 26, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #26 = FENTRY_CALL
1072 { 25, 2, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #25 = STACKMAP
1073 { 24, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #24 = ARITH_FENCE
1074 { 23, 4, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #23 = PSEUDO_PROBE
1075 { 22, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #22 = LIFETIME_END
1076 { 21, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #21 = LIFETIME_START
1077 { 20, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #20 = BUNDLE
1078 { 19, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #19 = COPY
1079 { 18, 2, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #18 = REG_SEQUENCE
1080 { 17, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #17 = DBG_LABEL
1081 { 16, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #16 = DBG_PHI
1082 { 15, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #15 = DBG_INSTR_REF
1083 { 14, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST
1084 { 13, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #13 = DBG_VALUE
1085 { 12, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS
1086 { 11, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #11 = SUBREG_TO_REG
1087 { 10, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
1088 { 9, 4, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #9 = INSERT_SUBREG
1089 { 8, 3, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
1090 { 7, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #7 = KILL
1091 { 6, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
1092 { 5, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #5 = GC_LABEL
1093 { 4, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #4 = EH_LABEL
1094 { 3, 1, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
1095 { 2, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #2 = INLINEASM_BR
1096 { 1, 0, 0, 0, 0, 0, 0, XCoreImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1 = INLINEASM
1097 { 0, 1, 1, 0, 0, 0, 0, XCoreImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #0 = PHI
1098 }, {
1099 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1100 /* 1 */
1101 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1102 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1103 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1104 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1105 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1106 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1107 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1108 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1109 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1110 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1111 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1112 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1113 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1114 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1115 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1116 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1117 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1118 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1119 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1120 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1121 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1122 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1123 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1124 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1125 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1126 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1127 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1128 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1129 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1130 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1131 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1132 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1133 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1134 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1135 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1136 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1137 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1138 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1139 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1140 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1141 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1142 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1143 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1144 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1145 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1146 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1147 /* 152 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1148 /* 154 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1149 /* 156 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1150 /* 157 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1151 /* 160 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1152 /* 164 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1153 /* 167 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1154 /* 170 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1155 /* 173 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1156 /* 175 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1157 /* 177 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1158 /* 182 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1159 /* 186 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1160 /* 191 */ { XCore::RRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1161 /* 193 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1162 /* 199 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1163 /* 205 */ { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1164 /* 208 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1165 /* 210 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { XCore::GRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1166 }, {
1167 /* 0 */
1168 /* 0 */ XCore::SP, XCore::SP,
1169 /* 2 */ XCore::SP, XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R11, XCore::LR,
1170 /* 9 */ XCore::R11,
1171 /* 10 */ XCore::SP,
1172 }
1173};
1174
1175
1176#ifdef __GNUC__
1177#pragma GCC diagnostic push
1178#pragma GCC diagnostic ignored "-Woverlength-strings"
1179#endif
1180extern const char XCoreInstrNameData[] = {
1181 /* 0 */ "G_FLOG10\0"
1182 /* 9 */ "G_FEXP10\0"
1183 /* 18 */ "LDAPB_u10\0"
1184 /* 28 */ "BLRB_u10\0"
1185 /* 37 */ "LDAPF_u10\0"
1186 /* 47 */ "BLRF_u10\0"
1187 /* 56 */ "BLACP_u10\0"
1188 /* 66 */ "LDWCP_u10\0"
1189 /* 76 */ "LDAPB_lu10\0"
1190 /* 87 */ "BLRB_lu10\0"
1191 /* 97 */ "LDAPF_lu10\0"
1192 /* 108 */ "BLRF_lu10\0"
1193 /* 118 */ "BLACP_lu10\0"
1194 /* 129 */ "LDWCP_lu10\0"
1195 /* 140 */ "BR_JT32\0"
1196 /* 148 */ "G_FLOG2\0"
1197 /* 156 */ "G_FEXP2\0"
1198 /* 164 */ "KCALL_u6\0"
1199 /* 173 */ "LDAWCP_u6\0"
1200 /* 183 */ "EXTDP_u6\0"
1201 /* 192 */ "RETSP_u6\0"
1202 /* 201 */ "KENTSP_u6\0"
1203 /* 211 */ "KRESTSP_u6\0"
1204 /* 222 */ "EXTSP_u6\0"
1205 /* 231 */ "CLRSR_u6\0"
1206 /* 240 */ "GETSR_u6\0"
1207 /* 249 */ "SETSR_u6\0"
1208 /* 258 */ "BLAT_u6\0"
1209 /* 266 */ "BRBU_u6\0"
1210 /* 274 */ "BRFU_u6\0"
1211 /* 282 */ "CLRSR_branch_u6\0"
1212 /* 298 */ "SETSR_branch_u6\0"
1213 /* 314 */ "KCALL_lu6\0"
1214 /* 324 */ "LDAWCP_lu6\0"
1215 /* 335 */ "EXTDP_lu6\0"
1216 /* 345 */ "RETSP_lu6\0"
1217 /* 355 */ "KENTSP_lu6\0"
1218 /* 366 */ "KRESTSP_lu6\0"
1219 /* 378 */ "EXTSP_lu6\0"
1220 /* 388 */ "CLRSR_lu6\0"
1221 /* 398 */ "GETSR_lu6\0"
1222 /* 408 */ "SETSR_lu6\0"
1223 /* 418 */ "BLAT_lu6\0"
1224 /* 427 */ "BRBU_lu6\0"
1225 /* 436 */ "BRFU_lu6\0"
1226 /* 445 */ "CLRSR_branch_lu6\0"
1227 /* 462 */ "SETSR_branch_lu6\0"
1228 /* 479 */ "LDC_ru6\0"
1229 /* 487 */ "SETC_ru6\0"
1230 /* 496 */ "BRBF_ru6\0"
1231 /* 505 */ "BRFF_ru6\0"
1232 /* 514 */ "LDWCP_ru6\0"
1233 /* 524 */ "LDAWDP_ru6\0"
1234 /* 535 */ "LDWDP_ru6\0"
1235 /* 545 */ "STWDP_ru6\0"
1236 /* 555 */ "LDAWSP_ru6\0"
1237 /* 566 */ "LDWSP_ru6\0"
1238 /* 576 */ "STWSP_ru6\0"
1239 /* 586 */ "BRBT_ru6\0"
1240 /* 595 */ "BRFT_ru6\0"
1241 /* 604 */ "LDC_lru6\0"
1242 /* 613 */ "SETC_lru6\0"
1243 /* 623 */ "BRBF_lru6\0"
1244 /* 633 */ "BRFF_lru6\0"
1245 /* 643 */ "LDWCP_lru6\0"
1246 /* 654 */ "LDAWDP_lru6\0"
1247 /* 666 */ "LDWDP_lru6\0"
1248 /* 677 */ "STWDP_lru6\0"
1249 /* 688 */ "LDAWSP_lru6\0"
1250 /* 700 */ "LDWSP_lru6\0"
1251 /* 711 */ "STWSP_lru6\0"
1252 /* 722 */ "BRBT_lru6\0"
1253 /* 732 */ "BRFT_lru6\0"
1254 /* 742 */ "G_FMA\0"
1255 /* 748 */ "G_STRICT_FMA\0"
1256 /* 761 */ "G_FSUB\0"
1257 /* 768 */ "G_STRICT_FSUB\0"
1258 /* 782 */ "G_ATOMICRMW_FSUB\0"
1259 /* 799 */ "G_SUB\0"
1260 /* 805 */ "G_ATOMICRMW_SUB\0"
1261 /* 821 */ "SELECT_CC\0"
1262 /* 831 */ "G_INTRINSIC\0"
1263 /* 843 */ "G_FPTRUNC\0"
1264 /* 853 */ "G_INTRINSIC_TRUNC\0"
1265 /* 871 */ "G_TRUNC\0"
1266 /* 879 */ "G_BUILD_VECTOR_TRUNC\0"
1267 /* 900 */ "G_DYN_STACKALLOC\0"
1268 /* 917 */ "G_FMAD\0"
1269 /* 924 */ "G_INDEXED_SEXTLOAD\0"
1270 /* 943 */ "G_SEXTLOAD\0"
1271 /* 954 */ "G_INDEXED_ZEXTLOAD\0"
1272 /* 973 */ "G_ZEXTLOAD\0"
1273 /* 984 */ "G_INDEXED_LOAD\0"
1274 /* 999 */ "G_LOAD\0"
1275 /* 1006 */ "G_VECREDUCE_FADD\0"
1276 /* 1023 */ "G_FADD\0"
1277 /* 1030 */ "G_VECREDUCE_SEQ_FADD\0"
1278 /* 1051 */ "G_STRICT_FADD\0"
1279 /* 1065 */ "G_ATOMICRMW_FADD\0"
1280 /* 1082 */ "G_VECREDUCE_ADD\0"
1281 /* 1098 */ "G_ADD\0"
1282 /* 1104 */ "G_PTR_ADD\0"
1283 /* 1114 */ "G_ATOMICRMW_ADD\0"
1284 /* 1130 */ "G_ATOMICRMW_NAND\0"
1285 /* 1147 */ "G_VECREDUCE_AND\0"
1286 /* 1163 */ "G_AND\0"
1287 /* 1169 */ "G_ATOMICRMW_AND\0"
1288 /* 1185 */ "LIFETIME_END\0"
1289 /* 1198 */ "G_BRCOND\0"
1290 /* 1207 */ "G_LLROUND\0"
1291 /* 1217 */ "G_LROUND\0"
1292 /* 1226 */ "G_INTRINSIC_ROUND\0"
1293 /* 1244 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
1294 /* 1270 */ "LOAD_STACK_GUARD\0"
1295 /* 1287 */ "PSEUDO_PROBE\0"
1296 /* 1300 */ "G_SSUBE\0"
1297 /* 1308 */ "G_USUBE\0"
1298 /* 1316 */ "G_FENCE\0"
1299 /* 1324 */ "ARITH_FENCE\0"
1300 /* 1336 */ "REG_SEQUENCE\0"
1301 /* 1349 */ "G_SADDE\0"
1302 /* 1357 */ "G_UADDE\0"
1303 /* 1365 */ "G_GET_FPMODE\0"
1304 /* 1378 */ "G_RESET_FPMODE\0"
1305 /* 1393 */ "G_SET_FPMODE\0"
1306 /* 1406 */ "G_FMINNUM_IEEE\0"
1307 /* 1421 */ "G_FMAXNUM_IEEE\0"
1308 /* 1436 */ "G_VSCALE\0"
1309 /* 1445 */ "G_JUMP_TABLE\0"
1310 /* 1458 */ "BUNDLE\0"
1311 /* 1465 */ "G_MEMCPY_INLINE\0"
1312 /* 1481 */ "LOCAL_ESCAPE\0"
1313 /* 1494 */ "G_STACKRESTORE\0"
1314 /* 1509 */ "G_INDEXED_STORE\0"
1315 /* 1525 */ "G_STORE\0"
1316 /* 1533 */ "G_BITREVERSE\0"
1317 /* 1546 */ "DBG_VALUE\0"
1318 /* 1556 */ "G_GLOBAL_VALUE\0"
1319 /* 1571 */ "G_PTRAUTH_GLOBAL_VALUE\0"
1320 /* 1594 */ "CONVERGENCECTRL_GLUE\0"
1321 /* 1615 */ "G_STACKSAVE\0"
1322 /* 1627 */ "G_MEMMOVE\0"
1323 /* 1637 */ "G_FREEZE\0"
1324 /* 1646 */ "G_FCANONICALIZE\0"
1325 /* 1662 */ "G_CTLZ_ZERO_UNDEF\0"
1326 /* 1680 */ "G_CTTZ_ZERO_UNDEF\0"
1327 /* 1698 */ "G_IMPLICIT_DEF\0"
1328 /* 1713 */ "DBG_INSTR_REF\0"
1329 /* 1727 */ "G_FNEG\0"
1330 /* 1734 */ "EXTRACT_SUBREG\0"
1331 /* 1749 */ "INSERT_SUBREG\0"
1332 /* 1763 */ "G_SEXT_INREG\0"
1333 /* 1776 */ "SUBREG_TO_REG\0"
1334 /* 1790 */ "G_ATOMIC_CMPXCHG\0"
1335 /* 1807 */ "G_ATOMICRMW_XCHG\0"
1336 /* 1824 */ "G_FLOG\0"
1337 /* 1831 */ "G_VAARG\0"
1338 /* 1839 */ "PREALLOCATED_ARG\0"
1339 /* 1856 */ "G_PREFETCH\0"
1340 /* 1867 */ "G_SMULH\0"
1341 /* 1875 */ "G_UMULH\0"
1342 /* 1883 */ "G_FTANH\0"
1343 /* 1891 */ "G_FSINH\0"
1344 /* 1899 */ "G_FCOSH\0"
1345 /* 1907 */ "LDAWFI\0"
1346 /* 1914 */ "LDWFI\0"
1347 /* 1920 */ "STWFI\0"
1348 /* 1926 */ "DBG_PHI\0"
1349 /* 1934 */ "G_FPTOSI\0"
1350 /* 1943 */ "G_FPTOUI\0"
1351 /* 1952 */ "G_FPOWI\0"
1352 /* 1960 */ "G_PTRMASK\0"
1353 /* 1970 */ "GC_LABEL\0"
1354 /* 1979 */ "DBG_LABEL\0"
1355 /* 1989 */ "EH_LABEL\0"
1356 /* 1998 */ "ANNOTATION_LABEL\0"
1357 /* 2015 */ "ICALL_BRANCH_FUNNEL\0"
1358 /* 2035 */ "G_FSHL\0"
1359 /* 2042 */ "G_SHL\0"
1360 /* 2048 */ "G_FCEIL\0"
1361 /* 2056 */ "PATCHABLE_TAIL_CALL\0"
1362 /* 2076 */ "PATCHABLE_TYPED_EVENT_CALL\0"
1363 /* 2103 */ "PATCHABLE_EVENT_CALL\0"
1364 /* 2124 */ "FENTRY_CALL\0"
1365 /* 2136 */ "KILL\0"
1366 /* 2141 */ "G_CONSTANT_POOL\0"
1367 /* 2157 */ "G_ROTL\0"
1368 /* 2164 */ "G_VECREDUCE_FMUL\0"
1369 /* 2181 */ "G_FMUL\0"
1370 /* 2188 */ "G_VECREDUCE_SEQ_FMUL\0"
1371 /* 2209 */ "G_STRICT_FMUL\0"
1372 /* 2223 */ "G_VECREDUCE_MUL\0"
1373 /* 2239 */ "G_MUL\0"
1374 /* 2245 */ "G_FREM\0"
1375 /* 2252 */ "G_STRICT_FREM\0"
1376 /* 2266 */ "G_SREM\0"
1377 /* 2273 */ "G_UREM\0"
1378 /* 2280 */ "G_SDIVREM\0"
1379 /* 2290 */ "G_UDIVREM\0"
1380 /* 2300 */ "INLINEASM\0"
1381 /* 2310 */ "G_VECREDUCE_FMINIMUM\0"
1382 /* 2331 */ "G_FMINIMUM\0"
1383 /* 2342 */ "G_VECREDUCE_FMAXIMUM\0"
1384 /* 2363 */ "G_FMAXIMUM\0"
1385 /* 2374 */ "G_FMINNUM\0"
1386 /* 2384 */ "G_FMAXNUM\0"
1387 /* 2394 */ "G_FATAN\0"
1388 /* 2402 */ "G_FTAN\0"
1389 /* 2409 */ "G_INTRINSIC_ROUNDEVEN\0"
1390 /* 2431 */ "G_ASSERT_ALIGN\0"
1391 /* 2446 */ "G_FCOPYSIGN\0"
1392 /* 2458 */ "G_VECREDUCE_FMIN\0"
1393 /* 2475 */ "G_ATOMICRMW_FMIN\0"
1394 /* 2492 */ "G_VECREDUCE_SMIN\0"
1395 /* 2509 */ "G_SMIN\0"
1396 /* 2516 */ "G_VECREDUCE_UMIN\0"
1397 /* 2533 */ "G_UMIN\0"
1398 /* 2540 */ "G_ATOMICRMW_UMIN\0"
1399 /* 2557 */ "G_ATOMICRMW_MIN\0"
1400 /* 2573 */ "G_FASIN\0"
1401 /* 2581 */ "G_FSIN\0"
1402 /* 2588 */ "CFI_INSTRUCTION\0"
1403 /* 2604 */ "EH_RETURN\0"
1404 /* 2614 */ "ADJCALLSTACKDOWN\0"
1405 /* 2631 */ "G_SSUBO\0"
1406 /* 2639 */ "G_USUBO\0"
1407 /* 2647 */ "G_SADDO\0"
1408 /* 2655 */ "G_UADDO\0"
1409 /* 2663 */ "JUMP_TABLE_DEBUG_INFO\0"
1410 /* 2685 */ "G_SMULO\0"
1411 /* 2693 */ "G_UMULO\0"
1412 /* 2701 */ "G_BZERO\0"
1413 /* 2709 */ "STACKMAP\0"
1414 /* 2718 */ "G_DEBUGTRAP\0"
1415 /* 2730 */ "G_UBSANTRAP\0"
1416 /* 2742 */ "G_TRAP\0"
1417 /* 2749 */ "G_ATOMICRMW_UDEC_WRAP\0"
1418 /* 2771 */ "G_ATOMICRMW_UINC_WRAP\0"
1419 /* 2793 */ "G_BSWAP\0"
1420 /* 2801 */ "G_SITOFP\0"
1421 /* 2810 */ "G_UITOFP\0"
1422 /* 2819 */ "G_FCMP\0"
1423 /* 2826 */ "G_ICMP\0"
1424 /* 2833 */ "G_SCMP\0"
1425 /* 2840 */ "G_UCMP\0"
1426 /* 2847 */ "CONVERGENCECTRL_LOOP\0"
1427 /* 2868 */ "G_CTPOP\0"
1428 /* 2876 */ "PATCHABLE_OP\0"
1429 /* 2889 */ "FAULTING_OP\0"
1430 /* 2901 */ "ADJCALLSTACKUP\0"
1431 /* 2916 */ "PREALLOCATED_SETUP\0"
1432 /* 2935 */ "G_FLDEXP\0"
1433 /* 2944 */ "G_STRICT_FLDEXP\0"
1434 /* 2960 */ "G_FEXP\0"
1435 /* 2967 */ "G_FFREXP\0"
1436 /* 2976 */ "LDSPC_0R\0"
1437 /* 2985 */ "STSPC_0R\0"
1438 /* 2994 */ "LDSED_0R\0"
1439 /* 3003 */ "STSED_0R\0"
1440 /* 3012 */ "GETED_0R\0"
1441 /* 3021 */ "GETID_0R\0"
1442 /* 3030 */ "CLRE_0R\0"
1443 /* 3038 */ "DCALL_0R\0"
1444 /* 3047 */ "GETKEP_0R\0"
1445 /* 3057 */ "SETKEP_0R\0"
1446 /* 3067 */ "GETKSP_0R\0"
1447 /* 3077 */ "DENTSP_0R\0"
1448 /* 3087 */ "DRESTSP_0R\0"
1449 /* 3098 */ "LDSSR_0R\0"
1450 /* 3107 */ "STSSR_0R\0"
1451 /* 3116 */ "LDET_0R\0"
1452 /* 3124 */ "FREET_0R\0"
1453 /* 3133 */ "DRET_0R\0"
1454 /* 3141 */ "KRET_0R\0"
1455 /* 3149 */ "GETET_0R\0"
1456 /* 3158 */ "STET_0R\0"
1457 /* 3166 */ "WAITEU_0R\0"
1458 /* 3176 */ "WAITEF_1R\0"
1459 /* 3186 */ "WAITET_1R\0"
1460 /* 3196 */ "CLRPT_1R\0"
1461 /* 3205 */ "TSTART_1R\0"
1462 /* 3215 */ "G_BR\0"
1463 /* 3220 */ "INLINEASM_BR\0"
1464 /* 3233 */ "G_BLOCK_ADDR\0"
1465 /* 3246 */ "MEMBARRIER\0"
1466 /* 3257 */ "G_CONSTANT_FOLD_BARRIER\0"
1467 /* 3281 */ "PATCHABLE_FUNCTION_ENTER\0"
1468 /* 3306 */ "G_READCYCLECOUNTER\0"
1469 /* 3325 */ "G_READSTEADYCOUNTER\0"
1470 /* 3345 */ "G_READ_REGISTER\0"
1471 /* 3361 */ "G_WRITE_REGISTER\0"
1472 /* 3378 */ "G_ASHR\0"
1473 /* 3385 */ "G_FSHR\0"
1474 /* 3392 */ "G_LSHR\0"
1475 /* 3399 */ "CONVERGENCECTRL_ANCHOR\0"
1476 /* 3422 */ "G_FFLOOR\0"
1477 /* 3431 */ "G_EXTRACT_SUBVECTOR\0"
1478 /* 3451 */ "G_INSERT_SUBVECTOR\0"
1479 /* 3470 */ "G_BUILD_VECTOR\0"
1480 /* 3485 */ "G_SHUFFLE_VECTOR\0"
1481 /* 3502 */ "G_SPLAT_VECTOR\0"
1482 /* 3517 */ "G_VECREDUCE_XOR\0"
1483 /* 3533 */ "G_XOR\0"
1484 /* 3539 */ "G_ATOMICRMW_XOR\0"
1485 /* 3555 */ "G_VECREDUCE_OR\0"
1486 /* 3570 */ "G_OR\0"
1487 /* 3575 */ "G_ATOMICRMW_OR\0"
1488 /* 3590 */ "G_ROTR\0"
1489 /* 3597 */ "G_INTTOPTR\0"
1490 /* 3608 */ "G_FABS\0"
1491 /* 3615 */ "G_ABS\0"
1492 /* 3621 */ "G_UNMERGE_VALUES\0"
1493 /* 3638 */ "G_MERGE_VALUES\0"
1494 /* 3653 */ "G_FACOS\0"
1495 /* 3661 */ "G_FCOS\0"
1496 /* 3668 */ "G_CONCAT_VECTORS\0"
1497 /* 3685 */ "COPY_TO_REGCLASS\0"
1498 /* 3702 */ "G_IS_FPCLASS\0"
1499 /* 3715 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
1500 /* 3745 */ "G_VECTOR_COMPRESS\0"
1501 /* 3763 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
1502 /* 3790 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
1503 /* 3828 */ "G_SSUBSAT\0"
1504 /* 3838 */ "G_USUBSAT\0"
1505 /* 3848 */ "G_SADDSAT\0"
1506 /* 3858 */ "G_UADDSAT\0"
1507 /* 3868 */ "G_SSHLSAT\0"
1508 /* 3878 */ "G_USHLSAT\0"
1509 /* 3888 */ "G_SMULFIXSAT\0"
1510 /* 3901 */ "G_UMULFIXSAT\0"
1511 /* 3914 */ "G_SDIVFIXSAT\0"
1512 /* 3927 */ "G_UDIVFIXSAT\0"
1513 /* 3940 */ "G_EXTRACT\0"
1514 /* 3950 */ "G_SELECT\0"
1515 /* 3959 */ "G_BRINDIRECT\0"
1516 /* 3972 */ "PATCHABLE_RET\0"
1517 /* 3986 */ "FRAME_TO_ARGS_OFFSET\0"
1518 /* 4007 */ "G_MEMSET\0"
1519 /* 4016 */ "PATCHABLE_FUNCTION_EXIT\0"
1520 /* 4040 */ "G_BRJT\0"
1521 /* 4047 */ "BR_JT\0"
1522 /* 4053 */ "G_EXTRACT_VECTOR_ELT\0"
1523 /* 4074 */ "G_INSERT_VECTOR_ELT\0"
1524 /* 4094 */ "G_FCONSTANT\0"
1525 /* 4106 */ "G_CONSTANT\0"
1526 /* 4117 */ "G_INTRINSIC_CONVERGENT\0"
1527 /* 4140 */ "STATEPOINT\0"
1528 /* 4151 */ "PATCHPOINT\0"
1529 /* 4162 */ "G_PTRTOINT\0"
1530 /* 4173 */ "G_FRINT\0"
1531 /* 4181 */ "G_INTRINSIC_LLRINT\0"
1532 /* 4200 */ "G_INTRINSIC_LRINT\0"
1533 /* 4218 */ "G_FNEARBYINT\0"
1534 /* 4231 */ "NOT\0"
1535 /* 4235 */ "G_VASTART\0"
1536 /* 4245 */ "LIFETIME_START\0"
1537 /* 4260 */ "G_INVOKE_REGION_START\0"
1538 /* 4282 */ "G_INSERT\0"
1539 /* 4291 */ "G_FSQRT\0"
1540 /* 4299 */ "G_STRICT_FSQRT\0"
1541 /* 4314 */ "G_BITCAST\0"
1542 /* 4324 */ "G_ADDRSPACE_CAST\0"
1543 /* 4341 */ "DBG_VALUE_LIST\0"
1544 /* 4356 */ "G_FPEXT\0"
1545 /* 4364 */ "G_SEXT\0"
1546 /* 4371 */ "G_ASSERT_SEXT\0"
1547 /* 4385 */ "G_ANYEXT\0"
1548 /* 4394 */ "G_ZEXT\0"
1549 /* 4401 */ "G_ASSERT_ZEXT\0"
1550 /* 4415 */ "G_FDIV\0"
1551 /* 4422 */ "G_STRICT_FDIV\0"
1552 /* 4436 */ "G_SDIV\0"
1553 /* 4443 */ "G_UDIV\0"
1554 /* 4450 */ "G_GET_FPENV\0"
1555 /* 4462 */ "G_RESET_FPENV\0"
1556 /* 4476 */ "G_SET_FPENV\0"
1557 /* 4488 */ "G_FPOW\0"
1558 /* 4495 */ "G_VECREDUCE_FMAX\0"
1559 /* 4512 */ "G_ATOMICRMW_FMAX\0"
1560 /* 4529 */ "G_VECREDUCE_SMAX\0"
1561 /* 4546 */ "G_SMAX\0"
1562 /* 4553 */ "G_VECREDUCE_UMAX\0"
1563 /* 4570 */ "G_UMAX\0"
1564 /* 4577 */ "G_ATOMICRMW_UMAX\0"
1565 /* 4594 */ "G_ATOMICRMW_MAX\0"
1566 /* 4610 */ "G_FRAME_INDEX\0"
1567 /* 4624 */ "G_SBFX\0"
1568 /* 4631 */ "G_UBFX\0"
1569 /* 4638 */ "G_SMULFIX\0"
1570 /* 4648 */ "G_UMULFIX\0"
1571 /* 4658 */ "G_SDIVFIX\0"
1572 /* 4668 */ "G_UDIVFIX\0"
1573 /* 4678 */ "G_MEMCPY\0"
1574 /* 4687 */ "COPY\0"
1575 /* 4692 */ "CONVERGENCECTRL_ENTRY\0"
1576 /* 4714 */ "G_CTLZ\0"
1577 /* 4721 */ "G_CTTZ\0"
1578 /* 4728 */ "LDAPF_lu10_ba\0"
1579 /* 4742 */ "SSYNC_0r\0"
1580 /* 4751 */ "BLA_1r\0"
1581 /* 4758 */ "MSYNC_1r\0"
1582 /* 4767 */ "ECALLF_1r\0"
1583 /* 4777 */ "DGETREG_1r\0"
1584 /* 4788 */ "KCALL_1r\0"
1585 /* 4797 */ "MJOIN_1r\0"
1586 /* 4806 */ "SETCP_1r\0"
1587 /* 4815 */ "SETDP_1r\0"
1588 /* 4824 */ "SETSP_1r\0"
1589 /* 4833 */ "SYNCR_1r\0"
1590 /* 4842 */ "FREER_1r\0"
1591 /* 4851 */ "ECALLT_1r\0"
1592 /* 4861 */ "BAU_1r\0"
1593 /* 4868 */ "EDU_1r\0"
1594 /* 4875 */ "EEU_1r\0"
1595 /* 4882 */ "BRU_1r\0"
1596 /* 4889 */ "SETEV_1r\0"
1597 /* 4898 */ "SETV_1r\0"
1598 /* 4906 */ "INITPC_2r\0"
1599 /* 4916 */ "SETPSC_2r\0"
1600 /* 4926 */ "SETD_2r\0"
1601 /* 4934 */ "EEF_2r\0"
1602 /* 4941 */ "PEEK_2r\0"
1603 /* 4949 */ "MKMSK_2r\0"
1604 /* 4958 */ "ENDIN_2r\0"
1605 /* 4967 */ "INITCP_2r\0"
1606 /* 4977 */ "INITDP_2r\0"
1607 /* 4987 */ "INITSP_2r\0"
1608 /* 4997 */ "INSHR_2r\0"
1609 /* 5006 */ "OUTSHR_2r\0"
1610 /* 5016 */ "TSETMR_2r\0"
1611 /* 5026 */ "GETTS_2r\0"
1612 /* 5035 */ "CHKCT_2r\0"
1613 /* 5044 */ "INCT_2r\0"
1614 /* 5052 */ "TESTCT_2r\0"
1615 /* 5062 */ "OUTCT_2r\0"
1616 /* 5071 */ "TESTWCT_2r\0"
1617 /* 5082 */ "EET_2r\0"
1618 /* 5089 */ "INT_2r\0"
1619 /* 5096 */ "ANDNOT_2r\0"
1620 /* 5106 */ "SETPT_2r\0"
1621 /* 5115 */ "GETST_2r\0"
1622 /* 5124 */ "OUTT_2r\0"
1623 /* 5132 */ "OUT_2r\0"
1624 /* 5139 */ "SEXT_2r\0"
1625 /* 5147 */ "ZEXT_2r\0"
1626 /* 5155 */ "SETC_l2r\0"
1627 /* 5164 */ "GETD_l2r\0"
1628 /* 5173 */ "SETCLK_l2r\0"
1629 /* 5184 */ "TESTLCL_l2r\0"
1630 /* 5196 */ "GETN_l2r\0"
1631 /* 5205 */ "SETN_l2r\0"
1632 /* 5214 */ "INITLR_l2r\0"
1633 /* 5225 */ "GETPS_l2r\0"
1634 /* 5235 */ "SETPS_l2r\0"
1635 /* 5245 */ "BYTEREV_l2r\0"
1636 /* 5257 */ "BITREV_l2r\0"
1637 /* 5268 */ "SETTW_l2r\0"
1638 /* 5278 */ "SETRDY_l2r\0"
1639 /* 5289 */ "CLZ_l2r\0"
1640 /* 5297 */ "SUB_3r\0"
1641 /* 5304 */ "ADD_3r\0"
1642 /* 5311 */ "AND_3r\0"
1643 /* 5318 */ "SHL_3r\0"
1644 /* 5325 */ "EQ_3r\0"
1645 /* 5331 */ "SHR_3r\0"
1646 /* 5338 */ "OR_3r\0"
1647 /* 5344 */ "TSETR_3r\0"
1648 /* 5353 */ "LD16S_3r\0"
1649 /* 5362 */ "LSS_3r\0"
1650 /* 5369 */ "LD8U_3r\0"
1651 /* 5377 */ "LSU_3r\0"
1652 /* 5384 */ "LDW_3r\0"
1653 /* 5391 */ "ST16_l3r\0"
1654 /* 5400 */ "ST8_l3r\0"
1655 /* 5408 */ "LDA16B_l3r\0"
1656 /* 5419 */ "LDAWB_l3r\0"
1657 /* 5429 */ "CRC_l3r\0"
1658 /* 5437 */ "LDA16F_l3r\0"
1659 /* 5448 */ "LDAWF_l3r\0"
1660 /* 5458 */ "MUL_l3r\0"
1661 /* 5466 */ "ASHR_l3r\0"
1662 /* 5475 */ "XOR_l3r\0"
1663 /* 5483 */ "REMS_l3r\0"
1664 /* 5492 */ "DIVS_l3r\0"
1665 /* 5501 */ "REMU_l3r\0"
1666 /* 5510 */ "DIVU_l3r\0"
1667 /* 5519 */ "STW_l3r\0"
1668 /* 5527 */ "CRC8_l4r\0"
1669 /* 5536 */ "MACCS_l4r\0"
1670 /* 5546 */ "MACCU_l4r\0"
1671 /* 5556 */ "LSUB_l5r\0"
1672 /* 5565 */ "LADD_l5r\0"
1673 /* 5574 */ "LDIVU_l5r\0"
1674 /* 5584 */ "LMUL_l6r\0"
1675 /* 5593 */ "SUB_2rus\0"
1676 /* 5602 */ "ADD_2rus\0"
1677 /* 5611 */ "SHL_2rus\0"
1678 /* 5620 */ "EQ_2rus\0"
1679 /* 5628 */ "SHR_2rus\0"
1680 /* 5637 */ "LDW_2rus\0"
1681 /* 5646 */ "STW_2rus\0"
1682 /* 5655 */ "LDAWB_l2rus\0"
1683 /* 5667 */ "LDAWF_l2rus\0"
1684 /* 5679 */ "ASHR_l2rus\0"
1685 /* 5690 */ "INPW_l2rus\0"
1686 /* 5701 */ "OUTPW_l2rus\0"
1687 /* 5713 */ "MKMSK_rus\0"
1688 /* 5723 */ "GETR_rus\0"
1689 /* 5732 */ "CHKCT_rus\0"
1690 /* 5742 */ "OUTCT_rus\0"
1691 /* 5752 */ "SEXT_rus\0"
1692 /* 5761 */ "ZEXT_rus\0"
1693};
1694#ifdef __GNUC__
1695#pragma GCC diagnostic pop
1696#endif
1697
1698extern const unsigned XCoreInstrNameIndices[] = {
1699 1930U, 2300U, 3220U, 2588U, 1989U, 1970U, 1998U, 2136U,
1700 1734U, 1749U, 1700U, 1776U, 3685U, 1546U, 4341U, 1713U,
1701 1926U, 1979U, 1336U, 4687U, 1458U, 4245U, 1185U, 1287U,
1702 1324U, 2709U, 2124U, 4151U, 1270U, 2916U, 1839U, 4140U,
1703 1481U, 2889U, 2876U, 3281U, 3972U, 4016U, 2056U, 2103U,
1704 2076U, 2015U, 3246U, 2663U, 4692U, 3399U, 2847U, 1594U,
1705 4371U, 4401U, 2431U, 1098U, 799U, 2239U, 4436U, 4443U,
1706 2266U, 2273U, 2280U, 2290U, 1163U, 3570U, 3533U, 1698U,
1707 1928U, 4610U, 1556U, 1571U, 2141U, 3940U, 3621U, 4282U,
1708 3638U, 3470U, 879U, 3668U, 4162U, 3597U, 4314U, 1637U,
1709 3257U, 1244U, 853U, 1226U, 4200U, 4181U, 2409U, 3306U,
1710 3325U, 999U, 943U, 973U, 984U, 924U, 954U, 1525U,
1711 1509U, 3715U, 1790U, 1807U, 1114U, 805U, 1169U, 1130U,
1712 3575U, 3539U, 4594U, 2557U, 4577U, 2540U, 1065U, 782U,
1713 4512U, 2475U, 2771U, 2749U, 1316U, 1856U, 1198U, 3959U,
1714 4260U, 831U, 3763U, 4117U, 3790U, 4385U, 871U, 4106U,
1715 4094U, 4235U, 1831U, 4364U, 1763U, 4394U, 2042U, 3392U,
1716 3378U, 2035U, 3385U, 3590U, 2157U, 2826U, 2819U, 2833U,
1717 2840U, 3950U, 2655U, 1357U, 2639U, 1308U, 2647U, 1349U,
1718 2631U, 1300U, 2693U, 2685U, 1875U, 1867U, 3858U, 3848U,
1719 3838U, 3828U, 3878U, 3868U, 4638U, 4648U, 3888U, 3901U,
1720 4658U, 4668U, 3914U, 3927U, 1023U, 761U, 2181U, 742U,
1721 917U, 4415U, 2245U, 4488U, 1952U, 2960U, 156U, 9U,
1722 1824U, 148U, 0U, 2935U, 2967U, 1727U, 4356U, 843U,
1723 1934U, 1943U, 2801U, 2810U, 3608U, 2446U, 3702U, 1646U,
1724 2374U, 2384U, 1406U, 1421U, 2331U, 2363U, 4450U, 4476U,
1725 4462U, 1365U, 1393U, 1378U, 1104U, 1960U, 2509U, 4546U,
1726 2533U, 4570U, 3615U, 1217U, 1207U, 3215U, 4040U, 1436U,
1727 3451U, 3431U, 4074U, 4053U, 3485U, 3502U, 3745U, 4721U,
1728 1680U, 4714U, 1662U, 2868U, 2793U, 1533U, 2048U, 3661U,
1729 2581U, 2402U, 3653U, 2573U, 2394U, 1899U, 1891U, 1883U,
1730 4291U, 3422U, 4173U, 4218U, 4324U, 3233U, 1445U, 900U,
1731 1615U, 1494U, 1051U, 768U, 2209U, 4422U, 2252U, 748U,
1732 4299U, 2944U, 3345U, 3361U, 4678U, 1465U, 1627U, 4007U,
1733 2701U, 2742U, 2718U, 2730U, 1030U, 2188U, 1006U, 2164U,
1734 4495U, 2458U, 2342U, 2310U, 1082U, 2223U, 1147U, 3555U,
1735 3517U, 4529U, 2492U, 4553U, 2516U, 4624U, 4631U, 2614U,
1736 2901U, 4047U, 140U, 2604U, 3986U, 1907U, 1914U, 821U,
1737 1920U, 5602U, 5304U, 5096U, 5311U, 5679U, 5466U, 4861U,
1738 5257U, 118U, 56U, 418U, 258U, 4751U, 87U, 28U,
1739 108U, 47U, 623U, 496U, 722U, 586U, 427U, 266U,
1740 633U, 505U, 732U, 595U, 436U, 274U, 4882U, 5245U,
1741 5035U, 5732U, 3030U, 3196U, 445U, 282U, 388U, 231U,
1742 5289U, 5527U, 5429U, 3038U, 3077U, 4777U, 5492U, 5510U,
1743 3087U, 3133U, 4767U, 4851U, 4868U, 4934U, 5082U, 4875U,
1744 4958U, 356U, 202U, 5620U, 5325U, 335U, 183U, 378U,
1745 222U, 4842U, 3124U, 5164U, 3012U, 3149U, 3021U, 3047U,
1746 3067U, 5196U, 5225U, 5723U, 398U, 240U, 5115U, 5026U,
1747 5044U, 4967U, 4977U, 5214U, 4906U, 4987U, 5690U, 4997U,
1748 5089U, 4961U, 4788U, 314U, 164U, 355U, 201U, 366U,
1749 211U, 3141U, 5565U, 5353U, 5369U, 5408U, 5437U, 76U,
1750 18U, 97U, 4728U, 37U, 5655U, 5419U, 324U, 173U,
1751 654U, 524U, 5667U, 5448U, 688U, 555U, 604U, 479U,
1752 3116U, 5574U, 2994U, 2976U, 3098U, 643U, 129U, 514U,
1753 66U, 666U, 535U, 700U, 566U, 5637U, 5384U, 5584U,
1754 5362U, 5556U, 5377U, 5536U, 5546U, 4797U, 4949U, 5713U,
1755 4758U, 5458U, 1730U, 4231U, 5338U, 5062U, 5742U, 5701U,
1756 5006U, 5124U, 5132U, 4941U, 5483U, 5501U, 345U, 192U,
1757 5173U, 4806U, 5155U, 613U, 487U, 4815U, 4926U, 4889U,
1758 3057U, 5205U, 4916U, 5235U, 5106U, 5278U, 4824U, 462U,
1759 298U, 408U, 249U, 5268U, 4898U, 5139U, 5752U, 5611U,
1760 5318U, 5628U, 5331U, 4742U, 5391U, 5400U, 3158U, 3003U,
1761 2985U, 3107U, 677U, 545U, 711U, 576U, 5646U, 5519U,
1762 5593U, 5297U, 4833U, 5052U, 5184U, 5071U, 5016U, 5344U,
1763 3205U, 3176U, 3186U, 3166U, 5475U, 5147U, 5761U,
1764};
1765
1766static inline void InitXCoreMCInstrInfo(MCInstrInfo *II) {
1767 II->InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 519);
1768}
1769
1770} // end namespace llvm
1771#endif // GET_INSTRINFO_MC_DESC
1772
1773#ifdef GET_INSTRINFO_HEADER
1774#undef GET_INSTRINFO_HEADER
1775namespace llvm {
1776struct XCoreGenInstrInfo : public TargetInstrInfo {
1777 explicit XCoreGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1778 ~XCoreGenInstrInfo() override = default;
1779
1780};
1781} // end namespace llvm
1782#endif // GET_INSTRINFO_HEADER
1783
1784#ifdef GET_INSTRINFO_HELPER_DECLS
1785#undef GET_INSTRINFO_HELPER_DECLS
1786
1787
1788#endif // GET_INSTRINFO_HELPER_DECLS
1789
1790#ifdef GET_INSTRINFO_HELPERS
1791#undef GET_INSTRINFO_HELPERS
1792
1793#endif // GET_INSTRINFO_HELPERS
1794
1795#ifdef GET_INSTRINFO_CTOR_DTOR
1796#undef GET_INSTRINFO_CTOR_DTOR
1797namespace llvm {
1798extern const XCoreInstrTable XCoreDescs;
1799extern const unsigned XCoreInstrNameIndices[];
1800extern const char XCoreInstrNameData[];
1801XCoreGenInstrInfo::XCoreGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1802 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1803 InitMCInstrInfo(XCoreDescs.Insts, XCoreInstrNameIndices, XCoreInstrNameData, nullptr, nullptr, 519);
1804}
1805} // end namespace llvm
1806#endif // GET_INSTRINFO_CTOR_DTOR
1807
1808#ifdef GET_INSTRINFO_OPERAND_ENUM
1809#undef GET_INSTRINFO_OPERAND_ENUM
1810namespace llvm {
1811namespace XCore {
1812namespace OpName {
1813enum {
1814 OPERAND_LAST
1815};
1816} // end namespace OpName
1817} // end namespace XCore
1818} // end namespace llvm
1819#endif //GET_INSTRINFO_OPERAND_ENUM
1820
1821#ifdef GET_INSTRINFO_NAMED_OPS
1822#undef GET_INSTRINFO_NAMED_OPS
1823namespace llvm {
1824namespace XCore {
1825LLVM_READONLY
1826int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1827 return -1;
1828}
1829} // end namespace XCore
1830} // end namespace llvm
1831#endif //GET_INSTRINFO_NAMED_OPS
1832
1833#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1834#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1835namespace llvm {
1836namespace XCore {
1837namespace OpTypes {
1838enum OperandType {
1839 InlineJT = 0,
1840 InlineJT32 = 1,
1841 MEMii = 2,
1842 brtarget = 3,
1843 brtarget_neg = 4,
1844 f32imm = 5,
1845 f64imm = 6,
1846 i1imm = 7,
1847 i8imm = 8,
1848 i16imm = 9,
1849 i32imm = 10,
1850 i64imm = 11,
1851 pcrel_imm = 12,
1852 pcrel_imm_neg = 13,
1853 ptype0 = 14,
1854 ptype1 = 15,
1855 ptype2 = 16,
1856 ptype3 = 17,
1857 ptype4 = 18,
1858 ptype5 = 19,
1859 type0 = 20,
1860 type1 = 21,
1861 type2 = 22,
1862 type3 = 23,
1863 type4 = 24,
1864 type5 = 25,
1865 untyped_imm_0 = 26,
1866 GRRegs = 27,
1867 RRegs = 28,
1868 OPERAND_TYPE_LIST_END
1869};
1870} // end namespace OpTypes
1871} // end namespace XCore
1872} // end namespace llvm
1873#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1874
1875#ifdef GET_INSTRINFO_OPERAND_TYPE
1876#undef GET_INSTRINFO_OPERAND_TYPE
1877namespace llvm {
1878namespace XCore {
1879LLVM_READONLY
1880static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
1881 static const uint16_t Offsets[] = {
1882 /* PHI */
1883 0,
1884 /* INLINEASM */
1885 1,
1886 /* INLINEASM_BR */
1887 1,
1888 /* CFI_INSTRUCTION */
1889 1,
1890 /* EH_LABEL */
1891 2,
1892 /* GC_LABEL */
1893 3,
1894 /* ANNOTATION_LABEL */
1895 4,
1896 /* KILL */
1897 5,
1898 /* EXTRACT_SUBREG */
1899 5,
1900 /* INSERT_SUBREG */
1901 8,
1902 /* IMPLICIT_DEF */
1903 12,
1904 /* SUBREG_TO_REG */
1905 13,
1906 /* COPY_TO_REGCLASS */
1907 17,
1908 /* DBG_VALUE */
1909 20,
1910 /* DBG_VALUE_LIST */
1911 20,
1912 /* DBG_INSTR_REF */
1913 20,
1914 /* DBG_PHI */
1915 20,
1916 /* DBG_LABEL */
1917 20,
1918 /* REG_SEQUENCE */
1919 21,
1920 /* COPY */
1921 23,
1922 /* BUNDLE */
1923 25,
1924 /* LIFETIME_START */
1925 25,
1926 /* LIFETIME_END */
1927 26,
1928 /* PSEUDO_PROBE */
1929 27,
1930 /* ARITH_FENCE */
1931 31,
1932 /* STACKMAP */
1933 33,
1934 /* FENTRY_CALL */
1935 35,
1936 /* PATCHPOINT */
1937 35,
1938 /* LOAD_STACK_GUARD */
1939 41,
1940 /* PREALLOCATED_SETUP */
1941 42,
1942 /* PREALLOCATED_ARG */
1943 43,
1944 /* STATEPOINT */
1945 46,
1946 /* LOCAL_ESCAPE */
1947 46,
1948 /* FAULTING_OP */
1949 48,
1950 /* PATCHABLE_OP */
1951 49,
1952 /* PATCHABLE_FUNCTION_ENTER */
1953 49,
1954 /* PATCHABLE_RET */
1955 49,
1956 /* PATCHABLE_FUNCTION_EXIT */
1957 49,
1958 /* PATCHABLE_TAIL_CALL */
1959 49,
1960 /* PATCHABLE_EVENT_CALL */
1961 49,
1962 /* PATCHABLE_TYPED_EVENT_CALL */
1963 51,
1964 /* ICALL_BRANCH_FUNNEL */
1965 54,
1966 /* MEMBARRIER */
1967 54,
1968 /* JUMP_TABLE_DEBUG_INFO */
1969 54,
1970 /* CONVERGENCECTRL_ENTRY */
1971 55,
1972 /* CONVERGENCECTRL_ANCHOR */
1973 56,
1974 /* CONVERGENCECTRL_LOOP */
1975 57,
1976 /* CONVERGENCECTRL_GLUE */
1977 59,
1978 /* G_ASSERT_SEXT */
1979 60,
1980 /* G_ASSERT_ZEXT */
1981 63,
1982 /* G_ASSERT_ALIGN */
1983 66,
1984 /* G_ADD */
1985 69,
1986 /* G_SUB */
1987 72,
1988 /* G_MUL */
1989 75,
1990 /* G_SDIV */
1991 78,
1992 /* G_UDIV */
1993 81,
1994 /* G_SREM */
1995 84,
1996 /* G_UREM */
1997 87,
1998 /* G_SDIVREM */
1999 90,
2000 /* G_UDIVREM */
2001 94,
2002 /* G_AND */
2003 98,
2004 /* G_OR */
2005 101,
2006 /* G_XOR */
2007 104,
2008 /* G_IMPLICIT_DEF */
2009 107,
2010 /* G_PHI */
2011 108,
2012 /* G_FRAME_INDEX */
2013 109,
2014 /* G_GLOBAL_VALUE */
2015 111,
2016 /* G_PTRAUTH_GLOBAL_VALUE */
2017 113,
2018 /* G_CONSTANT_POOL */
2019 118,
2020 /* G_EXTRACT */
2021 120,
2022 /* G_UNMERGE_VALUES */
2023 123,
2024 /* G_INSERT */
2025 125,
2026 /* G_MERGE_VALUES */
2027 129,
2028 /* G_BUILD_VECTOR */
2029 131,
2030 /* G_BUILD_VECTOR_TRUNC */
2031 133,
2032 /* G_CONCAT_VECTORS */
2033 135,
2034 /* G_PTRTOINT */
2035 137,
2036 /* G_INTTOPTR */
2037 139,
2038 /* G_BITCAST */
2039 141,
2040 /* G_FREEZE */
2041 143,
2042 /* G_CONSTANT_FOLD_BARRIER */
2043 145,
2044 /* G_INTRINSIC_FPTRUNC_ROUND */
2045 147,
2046 /* G_INTRINSIC_TRUNC */
2047 150,
2048 /* G_INTRINSIC_ROUND */
2049 152,
2050 /* G_INTRINSIC_LRINT */
2051 154,
2052 /* G_INTRINSIC_LLRINT */
2053 156,
2054 /* G_INTRINSIC_ROUNDEVEN */
2055 158,
2056 /* G_READCYCLECOUNTER */
2057 160,
2058 /* G_READSTEADYCOUNTER */
2059 161,
2060 /* G_LOAD */
2061 162,
2062 /* G_SEXTLOAD */
2063 164,
2064 /* G_ZEXTLOAD */
2065 166,
2066 /* G_INDEXED_LOAD */
2067 168,
2068 /* G_INDEXED_SEXTLOAD */
2069 173,
2070 /* G_INDEXED_ZEXTLOAD */
2071 178,
2072 /* G_STORE */
2073 183,
2074 /* G_INDEXED_STORE */
2075 185,
2076 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
2077 190,
2078 /* G_ATOMIC_CMPXCHG */
2079 195,
2080 /* G_ATOMICRMW_XCHG */
2081 199,
2082 /* G_ATOMICRMW_ADD */
2083 202,
2084 /* G_ATOMICRMW_SUB */
2085 205,
2086 /* G_ATOMICRMW_AND */
2087 208,
2088 /* G_ATOMICRMW_NAND */
2089 211,
2090 /* G_ATOMICRMW_OR */
2091 214,
2092 /* G_ATOMICRMW_XOR */
2093 217,
2094 /* G_ATOMICRMW_MAX */
2095 220,
2096 /* G_ATOMICRMW_MIN */
2097 223,
2098 /* G_ATOMICRMW_UMAX */
2099 226,
2100 /* G_ATOMICRMW_UMIN */
2101 229,
2102 /* G_ATOMICRMW_FADD */
2103 232,
2104 /* G_ATOMICRMW_FSUB */
2105 235,
2106 /* G_ATOMICRMW_FMAX */
2107 238,
2108 /* G_ATOMICRMW_FMIN */
2109 241,
2110 /* G_ATOMICRMW_UINC_WRAP */
2111 244,
2112 /* G_ATOMICRMW_UDEC_WRAP */
2113 247,
2114 /* G_FENCE */
2115 250,
2116 /* G_PREFETCH */
2117 252,
2118 /* G_BRCOND */
2119 256,
2120 /* G_BRINDIRECT */
2121 258,
2122 /* G_INVOKE_REGION_START */
2123 259,
2124 /* G_INTRINSIC */
2125 259,
2126 /* G_INTRINSIC_W_SIDE_EFFECTS */
2127 260,
2128 /* G_INTRINSIC_CONVERGENT */
2129 261,
2130 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
2131 262,
2132 /* G_ANYEXT */
2133 263,
2134 /* G_TRUNC */
2135 265,
2136 /* G_CONSTANT */
2137 267,
2138 /* G_FCONSTANT */
2139 269,
2140 /* G_VASTART */
2141 271,
2142 /* G_VAARG */
2143 272,
2144 /* G_SEXT */
2145 275,
2146 /* G_SEXT_INREG */
2147 277,
2148 /* G_ZEXT */
2149 280,
2150 /* G_SHL */
2151 282,
2152 /* G_LSHR */
2153 285,
2154 /* G_ASHR */
2155 288,
2156 /* G_FSHL */
2157 291,
2158 /* G_FSHR */
2159 295,
2160 /* G_ROTR */
2161 299,
2162 /* G_ROTL */
2163 302,
2164 /* G_ICMP */
2165 305,
2166 /* G_FCMP */
2167 309,
2168 /* G_SCMP */
2169 313,
2170 /* G_UCMP */
2171 316,
2172 /* G_SELECT */
2173 319,
2174 /* G_UADDO */
2175 323,
2176 /* G_UADDE */
2177 327,
2178 /* G_USUBO */
2179 332,
2180 /* G_USUBE */
2181 336,
2182 /* G_SADDO */
2183 341,
2184 /* G_SADDE */
2185 345,
2186 /* G_SSUBO */
2187 350,
2188 /* G_SSUBE */
2189 354,
2190 /* G_UMULO */
2191 359,
2192 /* G_SMULO */
2193 363,
2194 /* G_UMULH */
2195 367,
2196 /* G_SMULH */
2197 370,
2198 /* G_UADDSAT */
2199 373,
2200 /* G_SADDSAT */
2201 376,
2202 /* G_USUBSAT */
2203 379,
2204 /* G_SSUBSAT */
2205 382,
2206 /* G_USHLSAT */
2207 385,
2208 /* G_SSHLSAT */
2209 388,
2210 /* G_SMULFIX */
2211 391,
2212 /* G_UMULFIX */
2213 395,
2214 /* G_SMULFIXSAT */
2215 399,
2216 /* G_UMULFIXSAT */
2217 403,
2218 /* G_SDIVFIX */
2219 407,
2220 /* G_UDIVFIX */
2221 411,
2222 /* G_SDIVFIXSAT */
2223 415,
2224 /* G_UDIVFIXSAT */
2225 419,
2226 /* G_FADD */
2227 423,
2228 /* G_FSUB */
2229 426,
2230 /* G_FMUL */
2231 429,
2232 /* G_FMA */
2233 432,
2234 /* G_FMAD */
2235 436,
2236 /* G_FDIV */
2237 440,
2238 /* G_FREM */
2239 443,
2240 /* G_FPOW */
2241 446,
2242 /* G_FPOWI */
2243 449,
2244 /* G_FEXP */
2245 452,
2246 /* G_FEXP2 */
2247 454,
2248 /* G_FEXP10 */
2249 456,
2250 /* G_FLOG */
2251 458,
2252 /* G_FLOG2 */
2253 460,
2254 /* G_FLOG10 */
2255 462,
2256 /* G_FLDEXP */
2257 464,
2258 /* G_FFREXP */
2259 467,
2260 /* G_FNEG */
2261 470,
2262 /* G_FPEXT */
2263 472,
2264 /* G_FPTRUNC */
2265 474,
2266 /* G_FPTOSI */
2267 476,
2268 /* G_FPTOUI */
2269 478,
2270 /* G_SITOFP */
2271 480,
2272 /* G_UITOFP */
2273 482,
2274 /* G_FABS */
2275 484,
2276 /* G_FCOPYSIGN */
2277 486,
2278 /* G_IS_FPCLASS */
2279 489,
2280 /* G_FCANONICALIZE */
2281 492,
2282 /* G_FMINNUM */
2283 494,
2284 /* G_FMAXNUM */
2285 497,
2286 /* G_FMINNUM_IEEE */
2287 500,
2288 /* G_FMAXNUM_IEEE */
2289 503,
2290 /* G_FMINIMUM */
2291 506,
2292 /* G_FMAXIMUM */
2293 509,
2294 /* G_GET_FPENV */
2295 512,
2296 /* G_SET_FPENV */
2297 513,
2298 /* G_RESET_FPENV */
2299 514,
2300 /* G_GET_FPMODE */
2301 514,
2302 /* G_SET_FPMODE */
2303 515,
2304 /* G_RESET_FPMODE */
2305 516,
2306 /* G_PTR_ADD */
2307 516,
2308 /* G_PTRMASK */
2309 519,
2310 /* G_SMIN */
2311 522,
2312 /* G_SMAX */
2313 525,
2314 /* G_UMIN */
2315 528,
2316 /* G_UMAX */
2317 531,
2318 /* G_ABS */
2319 534,
2320 /* G_LROUND */
2321 536,
2322 /* G_LLROUND */
2323 538,
2324 /* G_BR */
2325 540,
2326 /* G_BRJT */
2327 541,
2328 /* G_VSCALE */
2329 544,
2330 /* G_INSERT_SUBVECTOR */
2331 546,
2332 /* G_EXTRACT_SUBVECTOR */
2333 550,
2334 /* G_INSERT_VECTOR_ELT */
2335 553,
2336 /* G_EXTRACT_VECTOR_ELT */
2337 557,
2338 /* G_SHUFFLE_VECTOR */
2339 560,
2340 /* G_SPLAT_VECTOR */
2341 564,
2342 /* G_VECTOR_COMPRESS */
2343 566,
2344 /* G_CTTZ */
2345 570,
2346 /* G_CTTZ_ZERO_UNDEF */
2347 572,
2348 /* G_CTLZ */
2349 574,
2350 /* G_CTLZ_ZERO_UNDEF */
2351 576,
2352 /* G_CTPOP */
2353 578,
2354 /* G_BSWAP */
2355 580,
2356 /* G_BITREVERSE */
2357 582,
2358 /* G_FCEIL */
2359 584,
2360 /* G_FCOS */
2361 586,
2362 /* G_FSIN */
2363 588,
2364 /* G_FTAN */
2365 590,
2366 /* G_FACOS */
2367 592,
2368 /* G_FASIN */
2369 594,
2370 /* G_FATAN */
2371 596,
2372 /* G_FCOSH */
2373 598,
2374 /* G_FSINH */
2375 600,
2376 /* G_FTANH */
2377 602,
2378 /* G_FSQRT */
2379 604,
2380 /* G_FFLOOR */
2381 606,
2382 /* G_FRINT */
2383 608,
2384 /* G_FNEARBYINT */
2385 610,
2386 /* G_ADDRSPACE_CAST */
2387 612,
2388 /* G_BLOCK_ADDR */
2389 614,
2390 /* G_JUMP_TABLE */
2391 616,
2392 /* G_DYN_STACKALLOC */
2393 618,
2394 /* G_STACKSAVE */
2395 621,
2396 /* G_STACKRESTORE */
2397 622,
2398 /* G_STRICT_FADD */
2399 623,
2400 /* G_STRICT_FSUB */
2401 626,
2402 /* G_STRICT_FMUL */
2403 629,
2404 /* G_STRICT_FDIV */
2405 632,
2406 /* G_STRICT_FREM */
2407 635,
2408 /* G_STRICT_FMA */
2409 638,
2410 /* G_STRICT_FSQRT */
2411 642,
2412 /* G_STRICT_FLDEXP */
2413 644,
2414 /* G_READ_REGISTER */
2415 647,
2416 /* G_WRITE_REGISTER */
2417 649,
2418 /* G_MEMCPY */
2419 651,
2420 /* G_MEMCPY_INLINE */
2421 655,
2422 /* G_MEMMOVE */
2423 658,
2424 /* G_MEMSET */
2425 662,
2426 /* G_BZERO */
2427 666,
2428 /* G_TRAP */
2429 669,
2430 /* G_DEBUGTRAP */
2431 669,
2432 /* G_UBSANTRAP */
2433 669,
2434 /* G_VECREDUCE_SEQ_FADD */
2435 670,
2436 /* G_VECREDUCE_SEQ_FMUL */
2437 673,
2438 /* G_VECREDUCE_FADD */
2439 676,
2440 /* G_VECREDUCE_FMUL */
2441 678,
2442 /* G_VECREDUCE_FMAX */
2443 680,
2444 /* G_VECREDUCE_FMIN */
2445 682,
2446 /* G_VECREDUCE_FMAXIMUM */
2447 684,
2448 /* G_VECREDUCE_FMINIMUM */
2449 686,
2450 /* G_VECREDUCE_ADD */
2451 688,
2452 /* G_VECREDUCE_MUL */
2453 690,
2454 /* G_VECREDUCE_AND */
2455 692,
2456 /* G_VECREDUCE_OR */
2457 694,
2458 /* G_VECREDUCE_XOR */
2459 696,
2460 /* G_VECREDUCE_SMAX */
2461 698,
2462 /* G_VECREDUCE_SMIN */
2463 700,
2464 /* G_VECREDUCE_UMAX */
2465 702,
2466 /* G_VECREDUCE_UMIN */
2467 704,
2468 /* G_SBFX */
2469 706,
2470 /* G_UBFX */
2471 710,
2472 /* ADJCALLSTACKDOWN */
2473 714,
2474 /* ADJCALLSTACKUP */
2475 716,
2476 /* BR_JT */
2477 718,
2478 /* BR_JT32 */
2479 720,
2480 /* EH_RETURN */
2481 722,
2482 /* FRAME_TO_ARGS_OFFSET */
2483 724,
2484 /* LDAWFI */
2485 725,
2486 /* LDWFI */
2487 728,
2488 /* SELECT_CC */
2489 731,
2490 /* STWFI */
2491 735,
2492 /* ADD_2rus */
2493 738,
2494 /* ADD_3r */
2495 741,
2496 /* ANDNOT_2r */
2497 744,
2498 /* AND_3r */
2499 747,
2500 /* ASHR_l2rus */
2501 750,
2502 /* ASHR_l3r */
2503 753,
2504 /* BAU_1r */
2505 756,
2506 /* BITREV_l2r */
2507 757,
2508 /* BLACP_lu10 */
2509 759,
2510 /* BLACP_u10 */
2511 760,
2512 /* BLAT_lu6 */
2513 761,
2514 /* BLAT_u6 */
2515 762,
2516 /* BLA_1r */
2517 763,
2518 /* BLRB_lu10 */
2519 764,
2520 /* BLRB_u10 */
2521 765,
2522 /* BLRF_lu10 */
2523 766,
2524 /* BLRF_u10 */
2525 767,
2526 /* BRBF_lru6 */
2527 768,
2528 /* BRBF_ru6 */
2529 770,
2530 /* BRBT_lru6 */
2531 772,
2532 /* BRBT_ru6 */
2533 774,
2534 /* BRBU_lu6 */
2535 776,
2536 /* BRBU_u6 */
2537 777,
2538 /* BRFF_lru6 */
2539 778,
2540 /* BRFF_ru6 */
2541 780,
2542 /* BRFT_lru6 */
2543 782,
2544 /* BRFT_ru6 */
2545 784,
2546 /* BRFU_lu6 */
2547 786,
2548 /* BRFU_u6 */
2549 787,
2550 /* BRU_1r */
2551 788,
2552 /* BYTEREV_l2r */
2553 789,
2554 /* CHKCT_2r */
2555 791,
2556 /* CHKCT_rus */
2557 793,
2558 /* CLRE_0R */
2559 795,
2560 /* CLRPT_1R */
2561 795,
2562 /* CLRSR_branch_lu6 */
2563 796,
2564 /* CLRSR_branch_u6 */
2565 797,
2566 /* CLRSR_lu6 */
2567 798,
2568 /* CLRSR_u6 */
2569 799,
2570 /* CLZ_l2r */
2571 800,
2572 /* CRC8_l4r */
2573 802,
2574 /* CRC_l3r */
2575 807,
2576 /* DCALL_0R */
2577 811,
2578 /* DENTSP_0R */
2579 811,
2580 /* DGETREG_1r */
2581 811,
2582 /* DIVS_l3r */
2583 812,
2584 /* DIVU_l3r */
2585 815,
2586 /* DRESTSP_0R */
2587 818,
2588 /* DRET_0R */
2589 818,
2590 /* ECALLF_1r */
2591 818,
2592 /* ECALLT_1r */
2593 819,
2594 /* EDU_1r */
2595 820,
2596 /* EEF_2r */
2597 821,
2598 /* EET_2r */
2599 823,
2600 /* EEU_1r */
2601 825,
2602 /* ENDIN_2r */
2603 826,
2604 /* ENTSP_lu6 */
2605 828,
2606 /* ENTSP_u6 */
2607 829,
2608 /* EQ_2rus */
2609 830,
2610 /* EQ_3r */
2611 833,
2612 /* EXTDP_lu6 */
2613 836,
2614 /* EXTDP_u6 */
2615 837,
2616 /* EXTSP_lu6 */
2617 838,
2618 /* EXTSP_u6 */
2619 839,
2620 /* FREER_1r */
2621 840,
2622 /* FREET_0R */
2623 841,
2624 /* GETD_l2r */
2625 841,
2626 /* GETED_0R */
2627 843,
2628 /* GETET_0R */
2629 843,
2630 /* GETID_0R */
2631 843,
2632 /* GETKEP_0R */
2633 843,
2634 /* GETKSP_0R */
2635 843,
2636 /* GETN_l2r */
2637 843,
2638 /* GETPS_l2r */
2639 845,
2640 /* GETR_rus */
2641 847,
2642 /* GETSR_lu6 */
2643 849,
2644 /* GETSR_u6 */
2645 850,
2646 /* GETST_2r */
2647 851,
2648 /* GETTS_2r */
2649 853,
2650 /* INCT_2r */
2651 855,
2652 /* INITCP_2r */
2653 857,
2654 /* INITDP_2r */
2655 859,
2656 /* INITLR_l2r */
2657 861,
2658 /* INITPC_2r */
2659 863,
2660 /* INITSP_2r */
2661 865,
2662 /* INPW_l2rus */
2663 867,
2664 /* INSHR_2r */
2665 870,
2666 /* INT_2r */
2667 873,
2668 /* IN_2r */
2669 875,
2670 /* KCALL_1r */
2671 877,
2672 /* KCALL_lu6 */
2673 878,
2674 /* KCALL_u6 */
2675 879,
2676 /* KENTSP_lu6 */
2677 880,
2678 /* KENTSP_u6 */
2679 881,
2680 /* KRESTSP_lu6 */
2681 882,
2682 /* KRESTSP_u6 */
2683 883,
2684 /* KRET_0R */
2685 884,
2686 /* LADD_l5r */
2687 884,
2688 /* LD16S_3r */
2689 889,
2690 /* LD8U_3r */
2691 892,
2692 /* LDA16B_l3r */
2693 895,
2694 /* LDA16F_l3r */
2695 898,
2696 /* LDAPB_lu10 */
2697 901,
2698 /* LDAPB_u10 */
2699 902,
2700 /* LDAPF_lu10 */
2701 903,
2702 /* LDAPF_lu10_ba */
2703 904,
2704 /* LDAPF_u10 */
2705 905,
2706 /* LDAWB_l2rus */
2707 906,
2708 /* LDAWB_l3r */
2709 909,
2710 /* LDAWCP_lu6 */
2711 912,
2712 /* LDAWCP_u6 */
2713 913,
2714 /* LDAWDP_lru6 */
2715 914,
2716 /* LDAWDP_ru6 */
2717 916,
2718 /* LDAWF_l2rus */
2719 918,
2720 /* LDAWF_l3r */
2721 921,
2722 /* LDAWSP_lru6 */
2723 924,
2724 /* LDAWSP_ru6 */
2725 926,
2726 /* LDC_lru6 */
2727 928,
2728 /* LDC_ru6 */
2729 930,
2730 /* LDET_0R */
2731 932,
2732 /* LDIVU_l5r */
2733 932,
2734 /* LDSED_0R */
2735 937,
2736 /* LDSPC_0R */
2737 937,
2738 /* LDSSR_0R */
2739 937,
2740 /* LDWCP_lru6 */
2741 937,
2742 /* LDWCP_lu10 */
2743 939,
2744 /* LDWCP_ru6 */
2745 940,
2746 /* LDWCP_u10 */
2747 942,
2748 /* LDWDP_lru6 */
2749 943,
2750 /* LDWDP_ru6 */
2751 945,
2752 /* LDWSP_lru6 */
2753 947,
2754 /* LDWSP_ru6 */
2755 949,
2756 /* LDW_2rus */
2757 951,
2758 /* LDW_3r */
2759 954,
2760 /* LMUL_l6r */
2761 957,
2762 /* LSS_3r */
2763 963,
2764 /* LSUB_l5r */
2765 966,
2766 /* LSU_3r */
2767 971,
2768 /* MACCS_l4r */
2769 974,
2770 /* MACCU_l4r */
2771 980,
2772 /* MJOIN_1r */
2773 986,
2774 /* MKMSK_2r */
2775 987,
2776 /* MKMSK_rus */
2777 989,
2778 /* MSYNC_1r */
2779 991,
2780 /* MUL_l3r */
2781 992,
2782 /* NEG */
2783 995,
2784 /* NOT */
2785 997,
2786 /* OR_3r */
2787 999,
2788 /* OUTCT_2r */
2789 1002,
2790 /* OUTCT_rus */
2791 1004,
2792 /* OUTPW_l2rus */
2793 1006,
2794 /* OUTSHR_2r */
2795 1009,
2796 /* OUTT_2r */
2797 1012,
2798 /* OUT_2r */
2799 1014,
2800 /* PEEK_2r */
2801 1016,
2802 /* REMS_l3r */
2803 1018,
2804 /* REMU_l3r */
2805 1021,
2806 /* RETSP_lu6 */
2807 1024,
2808 /* RETSP_u6 */
2809 1025,
2810 /* SETCLK_l2r */
2811 1026,
2812 /* SETCP_1r */
2813 1028,
2814 /* SETC_l2r */
2815 1029,
2816 /* SETC_lru6 */
2817 1031,
2818 /* SETC_ru6 */
2819 1033,
2820 /* SETDP_1r */
2821 1035,
2822 /* SETD_2r */
2823 1036,
2824 /* SETEV_1r */
2825 1038,
2826 /* SETKEP_0R */
2827 1039,
2828 /* SETN_l2r */
2829 1039,
2830 /* SETPSC_2r */
2831 1041,
2832 /* SETPS_l2r */
2833 1043,
2834 /* SETPT_2r */
2835 1045,
2836 /* SETRDY_l2r */
2837 1047,
2838 /* SETSP_1r */
2839 1049,
2840 /* SETSR_branch_lu6 */
2841 1050,
2842 /* SETSR_branch_u6 */
2843 1051,
2844 /* SETSR_lu6 */
2845 1052,
2846 /* SETSR_u6 */
2847 1053,
2848 /* SETTW_l2r */
2849 1054,
2850 /* SETV_1r */
2851 1056,
2852 /* SEXT_2r */
2853 1057,
2854 /* SEXT_rus */
2855 1060,
2856 /* SHL_2rus */
2857 1063,
2858 /* SHL_3r */
2859 1066,
2860 /* SHR_2rus */
2861 1069,
2862 /* SHR_3r */
2863 1072,
2864 /* SSYNC_0r */
2865 1075,
2866 /* ST16_l3r */
2867 1075,
2868 /* ST8_l3r */
2869 1078,
2870 /* STET_0R */
2871 1081,
2872 /* STSED_0R */
2873 1081,
2874 /* STSPC_0R */
2875 1081,
2876 /* STSSR_0R */
2877 1081,
2878 /* STWDP_lru6 */
2879 1081,
2880 /* STWDP_ru6 */
2881 1083,
2882 /* STWSP_lru6 */
2883 1085,
2884 /* STWSP_ru6 */
2885 1087,
2886 /* STW_2rus */
2887 1089,
2888 /* STW_l3r */
2889 1092,
2890 /* SUB_2rus */
2891 1095,
2892 /* SUB_3r */
2893 1098,
2894 /* SYNCR_1r */
2895 1101,
2896 /* TESTCT_2r */
2897 1102,
2898 /* TESTLCL_l2r */
2899 1104,
2900 /* TESTWCT_2r */
2901 1106,
2902 /* TSETMR_2r */
2903 1108,
2904 /* TSETR_3r */
2905 1110,
2906 /* TSTART_1R */
2907 1113,
2908 /* WAITEF_1R */
2909 1114,
2910 /* WAITET_1R */
2911 1115,
2912 /* WAITEU_0R */
2913 1116,
2914 /* XOR_l3r */
2915 1116,
2916 /* ZEXT_2r */
2917 1119,
2918 /* ZEXT_rus */
2919 1122,
2920 };
2921
2922 using namespace OpTypes;
2923 static const int8_t OpcodeOperandTypes[] = {
2924
2925 /* PHI */
2926 -1,
2927 /* INLINEASM */
2928 /* INLINEASM_BR */
2929 /* CFI_INSTRUCTION */
2930 i32imm,
2931 /* EH_LABEL */
2932 i32imm,
2933 /* GC_LABEL */
2934 i32imm,
2935 /* ANNOTATION_LABEL */
2936 i32imm,
2937 /* KILL */
2938 /* EXTRACT_SUBREG */
2939 -1, -1, i32imm,
2940 /* INSERT_SUBREG */
2941 -1, -1, -1, i32imm,
2942 /* IMPLICIT_DEF */
2943 -1,
2944 /* SUBREG_TO_REG */
2945 -1, -1, -1, i32imm,
2946 /* COPY_TO_REGCLASS */
2947 -1, -1, i32imm,
2948 /* DBG_VALUE */
2949 /* DBG_VALUE_LIST */
2950 /* DBG_INSTR_REF */
2951 /* DBG_PHI */
2952 /* DBG_LABEL */
2953 -1,
2954 /* REG_SEQUENCE */
2955 -1, -1,
2956 /* COPY */
2957 -1, -1,
2958 /* BUNDLE */
2959 /* LIFETIME_START */
2960 i32imm,
2961 /* LIFETIME_END */
2962 i32imm,
2963 /* PSEUDO_PROBE */
2964 i64imm, i64imm, i8imm, i32imm,
2965 /* ARITH_FENCE */
2966 -1, -1,
2967 /* STACKMAP */
2968 i64imm, i32imm,
2969 /* FENTRY_CALL */
2970 /* PATCHPOINT */
2971 -1, i64imm, i32imm, -1, i32imm, i32imm,
2972 /* LOAD_STACK_GUARD */
2973 -1,
2974 /* PREALLOCATED_SETUP */
2975 i32imm,
2976 /* PREALLOCATED_ARG */
2977 -1, i32imm, i32imm,
2978 /* STATEPOINT */
2979 /* LOCAL_ESCAPE */
2980 -1, i32imm,
2981 /* FAULTING_OP */
2982 -1,
2983 /* PATCHABLE_OP */
2984 /* PATCHABLE_FUNCTION_ENTER */
2985 /* PATCHABLE_RET */
2986 /* PATCHABLE_FUNCTION_EXIT */
2987 /* PATCHABLE_TAIL_CALL */
2988 /* PATCHABLE_EVENT_CALL */
2989 -1, -1,
2990 /* PATCHABLE_TYPED_EVENT_CALL */
2991 -1, -1, -1,
2992 /* ICALL_BRANCH_FUNNEL */
2993 /* MEMBARRIER */
2994 /* JUMP_TABLE_DEBUG_INFO */
2995 i64imm,
2996 /* CONVERGENCECTRL_ENTRY */
2997 -1,
2998 /* CONVERGENCECTRL_ANCHOR */
2999 -1,
3000 /* CONVERGENCECTRL_LOOP */
3001 -1, -1,
3002 /* CONVERGENCECTRL_GLUE */
3003 -1,
3004 /* G_ASSERT_SEXT */
3005 type0, type0, untyped_imm_0,
3006 /* G_ASSERT_ZEXT */
3007 type0, type0, untyped_imm_0,
3008 /* G_ASSERT_ALIGN */
3009 type0, type0, untyped_imm_0,
3010 /* G_ADD */
3011 type0, type0, type0,
3012 /* G_SUB */
3013 type0, type0, type0,
3014 /* G_MUL */
3015 type0, type0, type0,
3016 /* G_SDIV */
3017 type0, type0, type0,
3018 /* G_UDIV */
3019 type0, type0, type0,
3020 /* G_SREM */
3021 type0, type0, type0,
3022 /* G_UREM */
3023 type0, type0, type0,
3024 /* G_SDIVREM */
3025 type0, type0, type0, type0,
3026 /* G_UDIVREM */
3027 type0, type0, type0, type0,
3028 /* G_AND */
3029 type0, type0, type0,
3030 /* G_OR */
3031 type0, type0, type0,
3032 /* G_XOR */
3033 type0, type0, type0,
3034 /* G_IMPLICIT_DEF */
3035 type0,
3036 /* G_PHI */
3037 type0,
3038 /* G_FRAME_INDEX */
3039 type0, -1,
3040 /* G_GLOBAL_VALUE */
3041 type0, -1,
3042 /* G_PTRAUTH_GLOBAL_VALUE */
3043 type0, -1, i32imm, type1, i64imm,
3044 /* G_CONSTANT_POOL */
3045 type0, -1,
3046 /* G_EXTRACT */
3047 type0, type1, untyped_imm_0,
3048 /* G_UNMERGE_VALUES */
3049 type0, type1,
3050 /* G_INSERT */
3051 type0, type0, type1, untyped_imm_0,
3052 /* G_MERGE_VALUES */
3053 type0, type1,
3054 /* G_BUILD_VECTOR */
3055 type0, type1,
3056 /* G_BUILD_VECTOR_TRUNC */
3057 type0, type1,
3058 /* G_CONCAT_VECTORS */
3059 type0, type1,
3060 /* G_PTRTOINT */
3061 type0, type1,
3062 /* G_INTTOPTR */
3063 type0, type1,
3064 /* G_BITCAST */
3065 type0, type1,
3066 /* G_FREEZE */
3067 type0, type0,
3068 /* G_CONSTANT_FOLD_BARRIER */
3069 type0, type0,
3070 /* G_INTRINSIC_FPTRUNC_ROUND */
3071 type0, type1, i32imm,
3072 /* G_INTRINSIC_TRUNC */
3073 type0, type0,
3074 /* G_INTRINSIC_ROUND */
3075 type0, type0,
3076 /* G_INTRINSIC_LRINT */
3077 type0, type1,
3078 /* G_INTRINSIC_LLRINT */
3079 type0, type1,
3080 /* G_INTRINSIC_ROUNDEVEN */
3081 type0, type0,
3082 /* G_READCYCLECOUNTER */
3083 type0,
3084 /* G_READSTEADYCOUNTER */
3085 type0,
3086 /* G_LOAD */
3087 type0, ptype1,
3088 /* G_SEXTLOAD */
3089 type0, ptype1,
3090 /* G_ZEXTLOAD */
3091 type0, ptype1,
3092 /* G_INDEXED_LOAD */
3093 type0, ptype1, ptype1, type2, -1,
3094 /* G_INDEXED_SEXTLOAD */
3095 type0, ptype1, ptype1, type2, -1,
3096 /* G_INDEXED_ZEXTLOAD */
3097 type0, ptype1, ptype1, type2, -1,
3098 /* G_STORE */
3099 type0, ptype1,
3100 /* G_INDEXED_STORE */
3101 ptype0, type1, ptype0, ptype2, -1,
3102 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
3103 type0, type1, type2, type0, type0,
3104 /* G_ATOMIC_CMPXCHG */
3105 type0, ptype1, type0, type0,
3106 /* G_ATOMICRMW_XCHG */
3107 type0, ptype1, type0,
3108 /* G_ATOMICRMW_ADD */
3109 type0, ptype1, type0,
3110 /* G_ATOMICRMW_SUB */
3111 type0, ptype1, type0,
3112 /* G_ATOMICRMW_AND */
3113 type0, ptype1, type0,
3114 /* G_ATOMICRMW_NAND */
3115 type0, ptype1, type0,
3116 /* G_ATOMICRMW_OR */
3117 type0, ptype1, type0,
3118 /* G_ATOMICRMW_XOR */
3119 type0, ptype1, type0,
3120 /* G_ATOMICRMW_MAX */
3121 type0, ptype1, type0,
3122 /* G_ATOMICRMW_MIN */
3123 type0, ptype1, type0,
3124 /* G_ATOMICRMW_UMAX */
3125 type0, ptype1, type0,
3126 /* G_ATOMICRMW_UMIN */
3127 type0, ptype1, type0,
3128 /* G_ATOMICRMW_FADD */
3129 type0, ptype1, type0,
3130 /* G_ATOMICRMW_FSUB */
3131 type0, ptype1, type0,
3132 /* G_ATOMICRMW_FMAX */
3133 type0, ptype1, type0,
3134 /* G_ATOMICRMW_FMIN */
3135 type0, ptype1, type0,
3136 /* G_ATOMICRMW_UINC_WRAP */
3137 type0, ptype1, type0,
3138 /* G_ATOMICRMW_UDEC_WRAP */
3139 type0, ptype1, type0,
3140 /* G_FENCE */
3141 i32imm, i32imm,
3142 /* G_PREFETCH */
3143 ptype0, i32imm, i32imm, i32imm,
3144 /* G_BRCOND */
3145 type0, -1,
3146 /* G_BRINDIRECT */
3147 type0,
3148 /* G_INVOKE_REGION_START */
3149 /* G_INTRINSIC */
3150 -1,
3151 /* G_INTRINSIC_W_SIDE_EFFECTS */
3152 -1,
3153 /* G_INTRINSIC_CONVERGENT */
3154 -1,
3155 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
3156 -1,
3157 /* G_ANYEXT */
3158 type0, type1,
3159 /* G_TRUNC */
3160 type0, type1,
3161 /* G_CONSTANT */
3162 type0, -1,
3163 /* G_FCONSTANT */
3164 type0, -1,
3165 /* G_VASTART */
3166 type0,
3167 /* G_VAARG */
3168 type0, type1, -1,
3169 /* G_SEXT */
3170 type0, type1,
3171 /* G_SEXT_INREG */
3172 type0, type0, untyped_imm_0,
3173 /* G_ZEXT */
3174 type0, type1,
3175 /* G_SHL */
3176 type0, type0, type1,
3177 /* G_LSHR */
3178 type0, type0, type1,
3179 /* G_ASHR */
3180 type0, type0, type1,
3181 /* G_FSHL */
3182 type0, type0, type0, type1,
3183 /* G_FSHR */
3184 type0, type0, type0, type1,
3185 /* G_ROTR */
3186 type0, type0, type1,
3187 /* G_ROTL */
3188 type0, type0, type1,
3189 /* G_ICMP */
3190 type0, -1, type1, type1,
3191 /* G_FCMP */
3192 type0, -1, type1, type1,
3193 /* G_SCMP */
3194 type0, type1, type1,
3195 /* G_UCMP */
3196 type0, type1, type1,
3197 /* G_SELECT */
3198 type0, type1, type0, type0,
3199 /* G_UADDO */
3200 type0, type1, type0, type0,
3201 /* G_UADDE */
3202 type0, type1, type0, type0, type1,
3203 /* G_USUBO */
3204 type0, type1, type0, type0,
3205 /* G_USUBE */
3206 type0, type1, type0, type0, type1,
3207 /* G_SADDO */
3208 type0, type1, type0, type0,
3209 /* G_SADDE */
3210 type0, type1, type0, type0, type1,
3211 /* G_SSUBO */
3212 type0, type1, type0, type0,
3213 /* G_SSUBE */
3214 type0, type1, type0, type0, type1,
3215 /* G_UMULO */
3216 type0, type1, type0, type0,
3217 /* G_SMULO */
3218 type0, type1, type0, type0,
3219 /* G_UMULH */
3220 type0, type0, type0,
3221 /* G_SMULH */
3222 type0, type0, type0,
3223 /* G_UADDSAT */
3224 type0, type0, type0,
3225 /* G_SADDSAT */
3226 type0, type0, type0,
3227 /* G_USUBSAT */
3228 type0, type0, type0,
3229 /* G_SSUBSAT */
3230 type0, type0, type0,
3231 /* G_USHLSAT */
3232 type0, type0, type1,
3233 /* G_SSHLSAT */
3234 type0, type0, type1,
3235 /* G_SMULFIX */
3236 type0, type0, type0, untyped_imm_0,
3237 /* G_UMULFIX */
3238 type0, type0, type0, untyped_imm_0,
3239 /* G_SMULFIXSAT */
3240 type0, type0, type0, untyped_imm_0,
3241 /* G_UMULFIXSAT */
3242 type0, type0, type0, untyped_imm_0,
3243 /* G_SDIVFIX */
3244 type0, type0, type0, untyped_imm_0,
3245 /* G_UDIVFIX */
3246 type0, type0, type0, untyped_imm_0,
3247 /* G_SDIVFIXSAT */
3248 type0, type0, type0, untyped_imm_0,
3249 /* G_UDIVFIXSAT */
3250 type0, type0, type0, untyped_imm_0,
3251 /* G_FADD */
3252 type0, type0, type0,
3253 /* G_FSUB */
3254 type0, type0, type0,
3255 /* G_FMUL */
3256 type0, type0, type0,
3257 /* G_FMA */
3258 type0, type0, type0, type0,
3259 /* G_FMAD */
3260 type0, type0, type0, type0,
3261 /* G_FDIV */
3262 type0, type0, type0,
3263 /* G_FREM */
3264 type0, type0, type0,
3265 /* G_FPOW */
3266 type0, type0, type0,
3267 /* G_FPOWI */
3268 type0, type0, type1,
3269 /* G_FEXP */
3270 type0, type0,
3271 /* G_FEXP2 */
3272 type0, type0,
3273 /* G_FEXP10 */
3274 type0, type0,
3275 /* G_FLOG */
3276 type0, type0,
3277 /* G_FLOG2 */
3278 type0, type0,
3279 /* G_FLOG10 */
3280 type0, type0,
3281 /* G_FLDEXP */
3282 type0, type0, type1,
3283 /* G_FFREXP */
3284 type0, type1, type0,
3285 /* G_FNEG */
3286 type0, type0,
3287 /* G_FPEXT */
3288 type0, type1,
3289 /* G_FPTRUNC */
3290 type0, type1,
3291 /* G_FPTOSI */
3292 type0, type1,
3293 /* G_FPTOUI */
3294 type0, type1,
3295 /* G_SITOFP */
3296 type0, type1,
3297 /* G_UITOFP */
3298 type0, type1,
3299 /* G_FABS */
3300 type0, type0,
3301 /* G_FCOPYSIGN */
3302 type0, type0, type1,
3303 /* G_IS_FPCLASS */
3304 type0, type1, -1,
3305 /* G_FCANONICALIZE */
3306 type0, type0,
3307 /* G_FMINNUM */
3308 type0, type0, type0,
3309 /* G_FMAXNUM */
3310 type0, type0, type0,
3311 /* G_FMINNUM_IEEE */
3312 type0, type0, type0,
3313 /* G_FMAXNUM_IEEE */
3314 type0, type0, type0,
3315 /* G_FMINIMUM */
3316 type0, type0, type0,
3317 /* G_FMAXIMUM */
3318 type0, type0, type0,
3319 /* G_GET_FPENV */
3320 type0,
3321 /* G_SET_FPENV */
3322 type0,
3323 /* G_RESET_FPENV */
3324 /* G_GET_FPMODE */
3325 type0,
3326 /* G_SET_FPMODE */
3327 type0,
3328 /* G_RESET_FPMODE */
3329 /* G_PTR_ADD */
3330 ptype0, ptype0, type1,
3331 /* G_PTRMASK */
3332 ptype0, ptype0, type1,
3333 /* G_SMIN */
3334 type0, type0, type0,
3335 /* G_SMAX */
3336 type0, type0, type0,
3337 /* G_UMIN */
3338 type0, type0, type0,
3339 /* G_UMAX */
3340 type0, type0, type0,
3341 /* G_ABS */
3342 type0, type0,
3343 /* G_LROUND */
3344 type0, type1,
3345 /* G_LLROUND */
3346 type0, type1,
3347 /* G_BR */
3348 -1,
3349 /* G_BRJT */
3350 ptype0, -1, type1,
3351 /* G_VSCALE */
3352 type0, -1,
3353 /* G_INSERT_SUBVECTOR */
3354 type0, type0, type1, untyped_imm_0,
3355 /* G_EXTRACT_SUBVECTOR */
3356 type0, type0, untyped_imm_0,
3357 /* G_INSERT_VECTOR_ELT */
3358 type0, type0, type1, type2,
3359 /* G_EXTRACT_VECTOR_ELT */
3360 type0, type1, type2,
3361 /* G_SHUFFLE_VECTOR */
3362 type0, type1, type1, -1,
3363 /* G_SPLAT_VECTOR */
3364 type0, type1,
3365 /* G_VECTOR_COMPRESS */
3366 type0, type0, type1, type0,
3367 /* G_CTTZ */
3368 type0, type1,
3369 /* G_CTTZ_ZERO_UNDEF */
3370 type0, type1,
3371 /* G_CTLZ */
3372 type0, type1,
3373 /* G_CTLZ_ZERO_UNDEF */
3374 type0, type1,
3375 /* G_CTPOP */
3376 type0, type1,
3377 /* G_BSWAP */
3378 type0, type0,
3379 /* G_BITREVERSE */
3380 type0, type0,
3381 /* G_FCEIL */
3382 type0, type0,
3383 /* G_FCOS */
3384 type0, type0,
3385 /* G_FSIN */
3386 type0, type0,
3387 /* G_FTAN */
3388 type0, type0,
3389 /* G_FACOS */
3390 type0, type0,
3391 /* G_FASIN */
3392 type0, type0,
3393 /* G_FATAN */
3394 type0, type0,
3395 /* G_FCOSH */
3396 type0, type0,
3397 /* G_FSINH */
3398 type0, type0,
3399 /* G_FTANH */
3400 type0, type0,
3401 /* G_FSQRT */
3402 type0, type0,
3403 /* G_FFLOOR */
3404 type0, type0,
3405 /* G_FRINT */
3406 type0, type0,
3407 /* G_FNEARBYINT */
3408 type0, type0,
3409 /* G_ADDRSPACE_CAST */
3410 type0, type1,
3411 /* G_BLOCK_ADDR */
3412 type0, -1,
3413 /* G_JUMP_TABLE */
3414 type0, -1,
3415 /* G_DYN_STACKALLOC */
3416 ptype0, type1, i32imm,
3417 /* G_STACKSAVE */
3418 ptype0,
3419 /* G_STACKRESTORE */
3420 ptype0,
3421 /* G_STRICT_FADD */
3422 type0, type0, type0,
3423 /* G_STRICT_FSUB */
3424 type0, type0, type0,
3425 /* G_STRICT_FMUL */
3426 type0, type0, type0,
3427 /* G_STRICT_FDIV */
3428 type0, type0, type0,
3429 /* G_STRICT_FREM */
3430 type0, type0, type0,
3431 /* G_STRICT_FMA */
3432 type0, type0, type0, type0,
3433 /* G_STRICT_FSQRT */
3434 type0, type0,
3435 /* G_STRICT_FLDEXP */
3436 type0, type0, type1,
3437 /* G_READ_REGISTER */
3438 type0, -1,
3439 /* G_WRITE_REGISTER */
3440 -1, type0,
3441 /* G_MEMCPY */
3442 ptype0, ptype1, type2, untyped_imm_0,
3443 /* G_MEMCPY_INLINE */
3444 ptype0, ptype1, type2,
3445 /* G_MEMMOVE */
3446 ptype0, ptype1, type2, untyped_imm_0,
3447 /* G_MEMSET */
3448 ptype0, type1, type2, untyped_imm_0,
3449 /* G_BZERO */
3450 ptype0, type1, untyped_imm_0,
3451 /* G_TRAP */
3452 /* G_DEBUGTRAP */
3453 /* G_UBSANTRAP */
3454 i8imm,
3455 /* G_VECREDUCE_SEQ_FADD */
3456 type0, type1, type2,
3457 /* G_VECREDUCE_SEQ_FMUL */
3458 type0, type1, type2,
3459 /* G_VECREDUCE_FADD */
3460 type0, type1,
3461 /* G_VECREDUCE_FMUL */
3462 type0, type1,
3463 /* G_VECREDUCE_FMAX */
3464 type0, type1,
3465 /* G_VECREDUCE_FMIN */
3466 type0, type1,
3467 /* G_VECREDUCE_FMAXIMUM */
3468 type0, type1,
3469 /* G_VECREDUCE_FMINIMUM */
3470 type0, type1,
3471 /* G_VECREDUCE_ADD */
3472 type0, type1,
3473 /* G_VECREDUCE_MUL */
3474 type0, type1,
3475 /* G_VECREDUCE_AND */
3476 type0, type1,
3477 /* G_VECREDUCE_OR */
3478 type0, type1,
3479 /* G_VECREDUCE_XOR */
3480 type0, type1,
3481 /* G_VECREDUCE_SMAX */
3482 type0, type1,
3483 /* G_VECREDUCE_SMIN */
3484 type0, type1,
3485 /* G_VECREDUCE_UMAX */
3486 type0, type1,
3487 /* G_VECREDUCE_UMIN */
3488 type0, type1,
3489 /* G_SBFX */
3490 type0, type0, type1, type1,
3491 /* G_UBFX */
3492 type0, type0, type1, type1,
3493 /* ADJCALLSTACKDOWN */
3494 i32imm, i32imm,
3495 /* ADJCALLSTACKUP */
3496 i32imm, i32imm,
3497 /* BR_JT */
3498 InlineJT, GRRegs,
3499 /* BR_JT32 */
3500 InlineJT32, GRRegs,
3501 /* EH_RETURN */
3502 GRRegs, GRRegs,
3503 /* FRAME_TO_ARGS_OFFSET */
3504 GRRegs,
3505 /* LDAWFI */
3506 GRRegs, i32imm, i32imm,
3507 /* LDWFI */
3508 GRRegs, i32imm, i32imm,
3509 /* SELECT_CC */
3510 GRRegs, GRRegs, GRRegs, GRRegs,
3511 /* STWFI */
3512 GRRegs, i32imm, i32imm,
3513 /* ADD_2rus */
3514 GRRegs, GRRegs, i32imm,
3515 /* ADD_3r */
3516 GRRegs, GRRegs, GRRegs,
3517 /* ANDNOT_2r */
3518 GRRegs, GRRegs, GRRegs,
3519 /* AND_3r */
3520 GRRegs, GRRegs, GRRegs,
3521 /* ASHR_l2rus */
3522 GRRegs, GRRegs, i32imm,
3523 /* ASHR_l3r */
3524 GRRegs, GRRegs, GRRegs,
3525 /* BAU_1r */
3526 GRRegs,
3527 /* BITREV_l2r */
3528 GRRegs, GRRegs,
3529 /* BLACP_lu10 */
3530 i32imm,
3531 /* BLACP_u10 */
3532 i32imm,
3533 /* BLAT_lu6 */
3534 i32imm,
3535 /* BLAT_u6 */
3536 i32imm,
3537 /* BLA_1r */
3538 GRRegs,
3539 /* BLRB_lu10 */
3540 pcrel_imm_neg,
3541 /* BLRB_u10 */
3542 pcrel_imm_neg,
3543 /* BLRF_lu10 */
3544 pcrel_imm,
3545 /* BLRF_u10 */
3546 pcrel_imm,
3547 /* BRBF_lru6 */
3548 GRRegs, brtarget_neg,
3549 /* BRBF_ru6 */
3550 GRRegs, brtarget_neg,
3551 /* BRBT_lru6 */
3552 GRRegs, brtarget_neg,
3553 /* BRBT_ru6 */
3554 GRRegs, brtarget_neg,
3555 /* BRBU_lu6 */
3556 brtarget_neg,
3557 /* BRBU_u6 */
3558 brtarget_neg,
3559 /* BRFF_lru6 */
3560 GRRegs, brtarget,
3561 /* BRFF_ru6 */
3562 GRRegs, brtarget,
3563 /* BRFT_lru6 */
3564 GRRegs, brtarget,
3565 /* BRFT_ru6 */
3566 GRRegs, brtarget,
3567 /* BRFU_lu6 */
3568 brtarget,
3569 /* BRFU_u6 */
3570 brtarget,
3571 /* BRU_1r */
3572 GRRegs,
3573 /* BYTEREV_l2r */
3574 GRRegs, GRRegs,
3575 /* CHKCT_2r */
3576 GRRegs, GRRegs,
3577 /* CHKCT_rus */
3578 GRRegs, i32imm,
3579 /* CLRE_0R */
3580 /* CLRPT_1R */
3581 GRRegs,
3582 /* CLRSR_branch_lu6 */
3583 i32imm,
3584 /* CLRSR_branch_u6 */
3585 i32imm,
3586 /* CLRSR_lu6 */
3587 i32imm,
3588 /* CLRSR_u6 */
3589 i32imm,
3590 /* CLZ_l2r */
3591 GRRegs, GRRegs,
3592 /* CRC8_l4r */
3593 GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
3594 /* CRC_l3r */
3595 GRRegs, GRRegs, GRRegs, GRRegs,
3596 /* DCALL_0R */
3597 /* DENTSP_0R */
3598 /* DGETREG_1r */
3599 GRRegs,
3600 /* DIVS_l3r */
3601 GRRegs, GRRegs, GRRegs,
3602 /* DIVU_l3r */
3603 GRRegs, GRRegs, GRRegs,
3604 /* DRESTSP_0R */
3605 /* DRET_0R */
3606 /* ECALLF_1r */
3607 GRRegs,
3608 /* ECALLT_1r */
3609 GRRegs,
3610 /* EDU_1r */
3611 GRRegs,
3612 /* EEF_2r */
3613 GRRegs, GRRegs,
3614 /* EET_2r */
3615 GRRegs, GRRegs,
3616 /* EEU_1r */
3617 GRRegs,
3618 /* ENDIN_2r */
3619 GRRegs, GRRegs,
3620 /* ENTSP_lu6 */
3621 i32imm,
3622 /* ENTSP_u6 */
3623 i32imm,
3624 /* EQ_2rus */
3625 GRRegs, GRRegs, i32imm,
3626 /* EQ_3r */
3627 GRRegs, GRRegs, GRRegs,
3628 /* EXTDP_lu6 */
3629 i32imm,
3630 /* EXTDP_u6 */
3631 i32imm,
3632 /* EXTSP_lu6 */
3633 i32imm,
3634 /* EXTSP_u6 */
3635 i32imm,
3636 /* FREER_1r */
3637 GRRegs,
3638 /* FREET_0R */
3639 /* GETD_l2r */
3640 GRRegs, GRRegs,
3641 /* GETED_0R */
3642 /* GETET_0R */
3643 /* GETID_0R */
3644 /* GETKEP_0R */
3645 /* GETKSP_0R */
3646 /* GETN_l2r */
3647 GRRegs, GRRegs,
3648 /* GETPS_l2r */
3649 GRRegs, GRRegs,
3650 /* GETR_rus */
3651 GRRegs, i32imm,
3652 /* GETSR_lu6 */
3653 i32imm,
3654 /* GETSR_u6 */
3655 i32imm,
3656 /* GETST_2r */
3657 GRRegs, GRRegs,
3658 /* GETTS_2r */
3659 GRRegs, GRRegs,
3660 /* INCT_2r */
3661 GRRegs, GRRegs,
3662 /* INITCP_2r */
3663 GRRegs, GRRegs,
3664 /* INITDP_2r */
3665 GRRegs, GRRegs,
3666 /* INITLR_l2r */
3667 GRRegs, GRRegs,
3668 /* INITPC_2r */
3669 GRRegs, GRRegs,
3670 /* INITSP_2r */
3671 GRRegs, GRRegs,
3672 /* INPW_l2rus */
3673 GRRegs, GRRegs, i32imm,
3674 /* INSHR_2r */
3675 GRRegs, GRRegs, GRRegs,
3676 /* INT_2r */
3677 GRRegs, GRRegs,
3678 /* IN_2r */
3679 GRRegs, GRRegs,
3680 /* KCALL_1r */
3681 GRRegs,
3682 /* KCALL_lu6 */
3683 i32imm,
3684 /* KCALL_u6 */
3685 i32imm,
3686 /* KENTSP_lu6 */
3687 i32imm,
3688 /* KENTSP_u6 */
3689 i32imm,
3690 /* KRESTSP_lu6 */
3691 i32imm,
3692 /* KRESTSP_u6 */
3693 i32imm,
3694 /* KRET_0R */
3695 /* LADD_l5r */
3696 GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
3697 /* LD16S_3r */
3698 GRRegs, GRRegs, GRRegs,
3699 /* LD8U_3r */
3700 GRRegs, GRRegs, GRRegs,
3701 /* LDA16B_l3r */
3702 GRRegs, GRRegs, GRRegs,
3703 /* LDA16F_l3r */
3704 GRRegs, GRRegs, GRRegs,
3705 /* LDAPB_lu10 */
3706 pcrel_imm_neg,
3707 /* LDAPB_u10 */
3708 pcrel_imm_neg,
3709 /* LDAPF_lu10 */
3710 pcrel_imm,
3711 /* LDAPF_lu10_ba */
3712 pcrel_imm,
3713 /* LDAPF_u10 */
3714 pcrel_imm,
3715 /* LDAWB_l2rus */
3716 GRRegs, GRRegs, i32imm,
3717 /* LDAWB_l3r */
3718 GRRegs, GRRegs, GRRegs,
3719 /* LDAWCP_lu6 */
3720 i32imm,
3721 /* LDAWCP_u6 */
3722 i32imm,
3723 /* LDAWDP_lru6 */
3724 RRegs, i32imm,
3725 /* LDAWDP_ru6 */
3726 RRegs, i32imm,
3727 /* LDAWF_l2rus */
3728 GRRegs, GRRegs, i32imm,
3729 /* LDAWF_l3r */
3730 GRRegs, GRRegs, GRRegs,
3731 /* LDAWSP_lru6 */
3732 RRegs, i32imm,
3733 /* LDAWSP_ru6 */
3734 RRegs, i32imm,
3735 /* LDC_lru6 */
3736 RRegs, i32imm,
3737 /* LDC_ru6 */
3738 RRegs, i32imm,
3739 /* LDET_0R */
3740 /* LDIVU_l5r */
3741 GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
3742 /* LDSED_0R */
3743 /* LDSPC_0R */
3744 /* LDSSR_0R */
3745 /* LDWCP_lru6 */
3746 RRegs, i32imm,
3747 /* LDWCP_lu10 */
3748 i32imm,
3749 /* LDWCP_ru6 */
3750 RRegs, i32imm,
3751 /* LDWCP_u10 */
3752 i32imm,
3753 /* LDWDP_lru6 */
3754 RRegs, i32imm,
3755 /* LDWDP_ru6 */
3756 RRegs, i32imm,
3757 /* LDWSP_lru6 */
3758 RRegs, i32imm,
3759 /* LDWSP_ru6 */
3760 RRegs, i32imm,
3761 /* LDW_2rus */
3762 GRRegs, GRRegs, i32imm,
3763 /* LDW_3r */
3764 GRRegs, GRRegs, GRRegs,
3765 /* LMUL_l6r */
3766 GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
3767 /* LSS_3r */
3768 GRRegs, GRRegs, GRRegs,
3769 /* LSUB_l5r */
3770 GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
3771 /* LSU_3r */
3772 GRRegs, GRRegs, GRRegs,
3773 /* MACCS_l4r */
3774 GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
3775 /* MACCU_l4r */
3776 GRRegs, GRRegs, GRRegs, GRRegs, GRRegs, GRRegs,
3777 /* MJOIN_1r */
3778 GRRegs,
3779 /* MKMSK_2r */
3780 GRRegs, GRRegs,
3781 /* MKMSK_rus */
3782 GRRegs, i32imm,
3783 /* MSYNC_1r */
3784 GRRegs,
3785 /* MUL_l3r */
3786 GRRegs, GRRegs, GRRegs,
3787 /* NEG */
3788 GRRegs, GRRegs,
3789 /* NOT */
3790 GRRegs, GRRegs,
3791 /* OR_3r */
3792 GRRegs, GRRegs, GRRegs,
3793 /* OUTCT_2r */
3794 GRRegs, GRRegs,
3795 /* OUTCT_rus */
3796 GRRegs, i32imm,
3797 /* OUTPW_l2rus */
3798 GRRegs, GRRegs, i32imm,
3799 /* OUTSHR_2r */
3800 GRRegs, GRRegs, GRRegs,
3801 /* OUTT_2r */
3802 GRRegs, GRRegs,
3803 /* OUT_2r */
3804 GRRegs, GRRegs,
3805 /* PEEK_2r */
3806 GRRegs, GRRegs,
3807 /* REMS_l3r */
3808 GRRegs, GRRegs, GRRegs,
3809 /* REMU_l3r */
3810 GRRegs, GRRegs, GRRegs,
3811 /* RETSP_lu6 */
3812 i32imm,
3813 /* RETSP_u6 */
3814 i32imm,
3815 /* SETCLK_l2r */
3816 GRRegs, GRRegs,
3817 /* SETCP_1r */
3818 GRRegs,
3819 /* SETC_l2r */
3820 GRRegs, GRRegs,
3821 /* SETC_lru6 */
3822 GRRegs, i32imm,
3823 /* SETC_ru6 */
3824 GRRegs, i32imm,
3825 /* SETDP_1r */
3826 GRRegs,
3827 /* SETD_2r */
3828 GRRegs, GRRegs,
3829 /* SETEV_1r */
3830 GRRegs,
3831 /* SETKEP_0R */
3832 /* SETN_l2r */
3833 GRRegs, GRRegs,
3834 /* SETPSC_2r */
3835 GRRegs, GRRegs,
3836 /* SETPS_l2r */
3837 GRRegs, GRRegs,
3838 /* SETPT_2r */
3839 GRRegs, GRRegs,
3840 /* SETRDY_l2r */
3841 GRRegs, GRRegs,
3842 /* SETSP_1r */
3843 GRRegs,
3844 /* SETSR_branch_lu6 */
3845 i32imm,
3846 /* SETSR_branch_u6 */
3847 i32imm,
3848 /* SETSR_lu6 */
3849 i32imm,
3850 /* SETSR_u6 */
3851 i32imm,
3852 /* SETTW_l2r */
3853 GRRegs, GRRegs,
3854 /* SETV_1r */
3855 GRRegs,
3856 /* SEXT_2r */
3857 GRRegs, GRRegs, GRRegs,
3858 /* SEXT_rus */
3859 GRRegs, GRRegs, i32imm,
3860 /* SHL_2rus */
3861 GRRegs, GRRegs, i32imm,
3862 /* SHL_3r */
3863 GRRegs, GRRegs, GRRegs,
3864 /* SHR_2rus */
3865 GRRegs, GRRegs, i32imm,
3866 /* SHR_3r */
3867 GRRegs, GRRegs, GRRegs,
3868 /* SSYNC_0r */
3869 /* ST16_l3r */
3870 GRRegs, GRRegs, GRRegs,
3871 /* ST8_l3r */
3872 GRRegs, GRRegs, GRRegs,
3873 /* STET_0R */
3874 /* STSED_0R */
3875 /* STSPC_0R */
3876 /* STSSR_0R */
3877 /* STWDP_lru6 */
3878 RRegs, i32imm,
3879 /* STWDP_ru6 */
3880 RRegs, i32imm,
3881 /* STWSP_lru6 */
3882 RRegs, i32imm,
3883 /* STWSP_ru6 */
3884 RRegs, i32imm,
3885 /* STW_2rus */
3886 GRRegs, GRRegs, i32imm,
3887 /* STW_l3r */
3888 GRRegs, GRRegs, GRRegs,
3889 /* SUB_2rus */
3890 GRRegs, GRRegs, i32imm,
3891 /* SUB_3r */
3892 GRRegs, GRRegs, GRRegs,
3893 /* SYNCR_1r */
3894 GRRegs,
3895 /* TESTCT_2r */
3896 GRRegs, GRRegs,
3897 /* TESTLCL_l2r */
3898 GRRegs, GRRegs,
3899 /* TESTWCT_2r */
3900 GRRegs, GRRegs,
3901 /* TSETMR_2r */
3902 i32imm, GRRegs,
3903 /* TSETR_3r */
3904 i32imm, GRRegs, GRRegs,
3905 /* TSTART_1R */
3906 GRRegs,
3907 /* WAITEF_1R */
3908 GRRegs,
3909 /* WAITET_1R */
3910 GRRegs,
3911 /* WAITEU_0R */
3912 /* XOR_l3r */
3913 GRRegs, GRRegs, GRRegs,
3914 /* ZEXT_2r */
3915 GRRegs, GRRegs, GRRegs,
3916 /* ZEXT_rus */
3917 GRRegs, GRRegs, i32imm,
3918 };
3919 return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
3920}
3921} // end namespace XCore
3922} // end namespace llvm
3923#endif // GET_INSTRINFO_OPERAND_TYPE
3924
3925#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
3926#undef GET_INSTRINFO_MEM_OPERAND_SIZE
3927namespace llvm {
3928namespace XCore {
3929LLVM_READONLY
3930static int getMemOperandSize(int OpType) {
3931 switch (OpType) {
3932 default: return 0;
3933 }
3934}
3935} // end namespace XCore
3936} // end namespace llvm
3937#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
3938
3939#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3940#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3941namespace llvm {
3942namespace XCore {
3943LLVM_READONLY static unsigned
3944getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
3945 return LogicalOpIdx;
3946}
3947LLVM_READONLY static inline unsigned
3948getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
3949 auto S = 0U;
3950 for (auto i = 0U; i < LogicalOpIdx; ++i)
3951 S += getLogicalOperandSize(Opcode, i);
3952 return S;
3953}
3954} // end namespace XCore
3955} // end namespace llvm
3956#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
3957
3958#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3959#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3960namespace llvm {
3961namespace XCore {
3962LLVM_READONLY static int
3963getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
3964 return -1;
3965}
3966} // end namespace XCore
3967} // end namespace llvm
3968#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
3969
3970#ifdef GET_INSTRINFO_MC_HELPER_DECLS
3971#undef GET_INSTRINFO_MC_HELPER_DECLS
3972
3973namespace llvm {
3974class MCInst;
3975class FeatureBitset;
3976
3977namespace XCore_MC {
3978
3979void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
3980
3981} // end namespace XCore_MC
3982} // end namespace llvm
3983
3984#endif // GET_INSTRINFO_MC_HELPER_DECLS
3985
3986#ifdef GET_INSTRINFO_MC_HELPERS
3987#undef GET_INSTRINFO_MC_HELPERS
3988
3989namespace llvm {
3990namespace XCore_MC {
3991
3992} // end namespace XCore_MC
3993} // end namespace llvm
3994
3995#endif // GET_GENISTRINFO_MC_HELPERS
3996
3997#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
3998 defined(GET_AVAILABLE_OPCODE_CHECKER)
3999#define GET_COMPUTE_FEATURES
4000#endif
4001#ifdef GET_COMPUTE_FEATURES
4002#undef GET_COMPUTE_FEATURES
4003namespace llvm {
4004namespace XCore_MC {
4005
4006// Bits for subtarget features that participate in instruction matching.
4007enum SubtargetFeatureBits : uint8_t {
4008};
4009
4010inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
4011 FeatureBitset Features;
4012 return Features;
4013}
4014
4015inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
4016 enum : uint8_t {
4017 CEFBS_None,
4018 };
4019
4020 static constexpr FeatureBitset FeatureBitsets[] = {
4021 {}, // CEFBS_None
4022 };
4023 static constexpr uint8_t RequiredFeaturesRefs[] = {
4024 CEFBS_None, // PHI = 0
4025 CEFBS_None, // INLINEASM = 1
4026 CEFBS_None, // INLINEASM_BR = 2
4027 CEFBS_None, // CFI_INSTRUCTION = 3
4028 CEFBS_None, // EH_LABEL = 4
4029 CEFBS_None, // GC_LABEL = 5
4030 CEFBS_None, // ANNOTATION_LABEL = 6
4031 CEFBS_None, // KILL = 7
4032 CEFBS_None, // EXTRACT_SUBREG = 8
4033 CEFBS_None, // INSERT_SUBREG = 9
4034 CEFBS_None, // IMPLICIT_DEF = 10
4035 CEFBS_None, // SUBREG_TO_REG = 11
4036 CEFBS_None, // COPY_TO_REGCLASS = 12
4037 CEFBS_None, // DBG_VALUE = 13
4038 CEFBS_None, // DBG_VALUE_LIST = 14
4039 CEFBS_None, // DBG_INSTR_REF = 15
4040 CEFBS_None, // DBG_PHI = 16
4041 CEFBS_None, // DBG_LABEL = 17
4042 CEFBS_None, // REG_SEQUENCE = 18
4043 CEFBS_None, // COPY = 19
4044 CEFBS_None, // BUNDLE = 20
4045 CEFBS_None, // LIFETIME_START = 21
4046 CEFBS_None, // LIFETIME_END = 22
4047 CEFBS_None, // PSEUDO_PROBE = 23
4048 CEFBS_None, // ARITH_FENCE = 24
4049 CEFBS_None, // STACKMAP = 25
4050 CEFBS_None, // FENTRY_CALL = 26
4051 CEFBS_None, // PATCHPOINT = 27
4052 CEFBS_None, // LOAD_STACK_GUARD = 28
4053 CEFBS_None, // PREALLOCATED_SETUP = 29
4054 CEFBS_None, // PREALLOCATED_ARG = 30
4055 CEFBS_None, // STATEPOINT = 31
4056 CEFBS_None, // LOCAL_ESCAPE = 32
4057 CEFBS_None, // FAULTING_OP = 33
4058 CEFBS_None, // PATCHABLE_OP = 34
4059 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
4060 CEFBS_None, // PATCHABLE_RET = 36
4061 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
4062 CEFBS_None, // PATCHABLE_TAIL_CALL = 38
4063 CEFBS_None, // PATCHABLE_EVENT_CALL = 39
4064 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
4065 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
4066 CEFBS_None, // MEMBARRIER = 42
4067 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
4068 CEFBS_None, // CONVERGENCECTRL_ENTRY = 44
4069 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 45
4070 CEFBS_None, // CONVERGENCECTRL_LOOP = 46
4071 CEFBS_None, // CONVERGENCECTRL_GLUE = 47
4072 CEFBS_None, // G_ASSERT_SEXT = 48
4073 CEFBS_None, // G_ASSERT_ZEXT = 49
4074 CEFBS_None, // G_ASSERT_ALIGN = 50
4075 CEFBS_None, // G_ADD = 51
4076 CEFBS_None, // G_SUB = 52
4077 CEFBS_None, // G_MUL = 53
4078 CEFBS_None, // G_SDIV = 54
4079 CEFBS_None, // G_UDIV = 55
4080 CEFBS_None, // G_SREM = 56
4081 CEFBS_None, // G_UREM = 57
4082 CEFBS_None, // G_SDIVREM = 58
4083 CEFBS_None, // G_UDIVREM = 59
4084 CEFBS_None, // G_AND = 60
4085 CEFBS_None, // G_OR = 61
4086 CEFBS_None, // G_XOR = 62
4087 CEFBS_None, // G_IMPLICIT_DEF = 63
4088 CEFBS_None, // G_PHI = 64
4089 CEFBS_None, // G_FRAME_INDEX = 65
4090 CEFBS_None, // G_GLOBAL_VALUE = 66
4091 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 67
4092 CEFBS_None, // G_CONSTANT_POOL = 68
4093 CEFBS_None, // G_EXTRACT = 69
4094 CEFBS_None, // G_UNMERGE_VALUES = 70
4095 CEFBS_None, // G_INSERT = 71
4096 CEFBS_None, // G_MERGE_VALUES = 72
4097 CEFBS_None, // G_BUILD_VECTOR = 73
4098 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 74
4099 CEFBS_None, // G_CONCAT_VECTORS = 75
4100 CEFBS_None, // G_PTRTOINT = 76
4101 CEFBS_None, // G_INTTOPTR = 77
4102 CEFBS_None, // G_BITCAST = 78
4103 CEFBS_None, // G_FREEZE = 79
4104 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 80
4105 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 81
4106 CEFBS_None, // G_INTRINSIC_TRUNC = 82
4107 CEFBS_None, // G_INTRINSIC_ROUND = 83
4108 CEFBS_None, // G_INTRINSIC_LRINT = 84
4109 CEFBS_None, // G_INTRINSIC_LLRINT = 85
4110 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 86
4111 CEFBS_None, // G_READCYCLECOUNTER = 87
4112 CEFBS_None, // G_READSTEADYCOUNTER = 88
4113 CEFBS_None, // G_LOAD = 89
4114 CEFBS_None, // G_SEXTLOAD = 90
4115 CEFBS_None, // G_ZEXTLOAD = 91
4116 CEFBS_None, // G_INDEXED_LOAD = 92
4117 CEFBS_None, // G_INDEXED_SEXTLOAD = 93
4118 CEFBS_None, // G_INDEXED_ZEXTLOAD = 94
4119 CEFBS_None, // G_STORE = 95
4120 CEFBS_None, // G_INDEXED_STORE = 96
4121 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97
4122 CEFBS_None, // G_ATOMIC_CMPXCHG = 98
4123 CEFBS_None, // G_ATOMICRMW_XCHG = 99
4124 CEFBS_None, // G_ATOMICRMW_ADD = 100
4125 CEFBS_None, // G_ATOMICRMW_SUB = 101
4126 CEFBS_None, // G_ATOMICRMW_AND = 102
4127 CEFBS_None, // G_ATOMICRMW_NAND = 103
4128 CEFBS_None, // G_ATOMICRMW_OR = 104
4129 CEFBS_None, // G_ATOMICRMW_XOR = 105
4130 CEFBS_None, // G_ATOMICRMW_MAX = 106
4131 CEFBS_None, // G_ATOMICRMW_MIN = 107
4132 CEFBS_None, // G_ATOMICRMW_UMAX = 108
4133 CEFBS_None, // G_ATOMICRMW_UMIN = 109
4134 CEFBS_None, // G_ATOMICRMW_FADD = 110
4135 CEFBS_None, // G_ATOMICRMW_FSUB = 111
4136 CEFBS_None, // G_ATOMICRMW_FMAX = 112
4137 CEFBS_None, // G_ATOMICRMW_FMIN = 113
4138 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 114
4139 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 115
4140 CEFBS_None, // G_FENCE = 116
4141 CEFBS_None, // G_PREFETCH = 117
4142 CEFBS_None, // G_BRCOND = 118
4143 CEFBS_None, // G_BRINDIRECT = 119
4144 CEFBS_None, // G_INVOKE_REGION_START = 120
4145 CEFBS_None, // G_INTRINSIC = 121
4146 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 122
4147 CEFBS_None, // G_INTRINSIC_CONVERGENT = 123
4148 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124
4149 CEFBS_None, // G_ANYEXT = 125
4150 CEFBS_None, // G_TRUNC = 126
4151 CEFBS_None, // G_CONSTANT = 127
4152 CEFBS_None, // G_FCONSTANT = 128
4153 CEFBS_None, // G_VASTART = 129
4154 CEFBS_None, // G_VAARG = 130
4155 CEFBS_None, // G_SEXT = 131
4156 CEFBS_None, // G_SEXT_INREG = 132
4157 CEFBS_None, // G_ZEXT = 133
4158 CEFBS_None, // G_SHL = 134
4159 CEFBS_None, // G_LSHR = 135
4160 CEFBS_None, // G_ASHR = 136
4161 CEFBS_None, // G_FSHL = 137
4162 CEFBS_None, // G_FSHR = 138
4163 CEFBS_None, // G_ROTR = 139
4164 CEFBS_None, // G_ROTL = 140
4165 CEFBS_None, // G_ICMP = 141
4166 CEFBS_None, // G_FCMP = 142
4167 CEFBS_None, // G_SCMP = 143
4168 CEFBS_None, // G_UCMP = 144
4169 CEFBS_None, // G_SELECT = 145
4170 CEFBS_None, // G_UADDO = 146
4171 CEFBS_None, // G_UADDE = 147
4172 CEFBS_None, // G_USUBO = 148
4173 CEFBS_None, // G_USUBE = 149
4174 CEFBS_None, // G_SADDO = 150
4175 CEFBS_None, // G_SADDE = 151
4176 CEFBS_None, // G_SSUBO = 152
4177 CEFBS_None, // G_SSUBE = 153
4178 CEFBS_None, // G_UMULO = 154
4179 CEFBS_None, // G_SMULO = 155
4180 CEFBS_None, // G_UMULH = 156
4181 CEFBS_None, // G_SMULH = 157
4182 CEFBS_None, // G_UADDSAT = 158
4183 CEFBS_None, // G_SADDSAT = 159
4184 CEFBS_None, // G_USUBSAT = 160
4185 CEFBS_None, // G_SSUBSAT = 161
4186 CEFBS_None, // G_USHLSAT = 162
4187 CEFBS_None, // G_SSHLSAT = 163
4188 CEFBS_None, // G_SMULFIX = 164
4189 CEFBS_None, // G_UMULFIX = 165
4190 CEFBS_None, // G_SMULFIXSAT = 166
4191 CEFBS_None, // G_UMULFIXSAT = 167
4192 CEFBS_None, // G_SDIVFIX = 168
4193 CEFBS_None, // G_UDIVFIX = 169
4194 CEFBS_None, // G_SDIVFIXSAT = 170
4195 CEFBS_None, // G_UDIVFIXSAT = 171
4196 CEFBS_None, // G_FADD = 172
4197 CEFBS_None, // G_FSUB = 173
4198 CEFBS_None, // G_FMUL = 174
4199 CEFBS_None, // G_FMA = 175
4200 CEFBS_None, // G_FMAD = 176
4201 CEFBS_None, // G_FDIV = 177
4202 CEFBS_None, // G_FREM = 178
4203 CEFBS_None, // G_FPOW = 179
4204 CEFBS_None, // G_FPOWI = 180
4205 CEFBS_None, // G_FEXP = 181
4206 CEFBS_None, // G_FEXP2 = 182
4207 CEFBS_None, // G_FEXP10 = 183
4208 CEFBS_None, // G_FLOG = 184
4209 CEFBS_None, // G_FLOG2 = 185
4210 CEFBS_None, // G_FLOG10 = 186
4211 CEFBS_None, // G_FLDEXP = 187
4212 CEFBS_None, // G_FFREXP = 188
4213 CEFBS_None, // G_FNEG = 189
4214 CEFBS_None, // G_FPEXT = 190
4215 CEFBS_None, // G_FPTRUNC = 191
4216 CEFBS_None, // G_FPTOSI = 192
4217 CEFBS_None, // G_FPTOUI = 193
4218 CEFBS_None, // G_SITOFP = 194
4219 CEFBS_None, // G_UITOFP = 195
4220 CEFBS_None, // G_FABS = 196
4221 CEFBS_None, // G_FCOPYSIGN = 197
4222 CEFBS_None, // G_IS_FPCLASS = 198
4223 CEFBS_None, // G_FCANONICALIZE = 199
4224 CEFBS_None, // G_FMINNUM = 200
4225 CEFBS_None, // G_FMAXNUM = 201
4226 CEFBS_None, // G_FMINNUM_IEEE = 202
4227 CEFBS_None, // G_FMAXNUM_IEEE = 203
4228 CEFBS_None, // G_FMINIMUM = 204
4229 CEFBS_None, // G_FMAXIMUM = 205
4230 CEFBS_None, // G_GET_FPENV = 206
4231 CEFBS_None, // G_SET_FPENV = 207
4232 CEFBS_None, // G_RESET_FPENV = 208
4233 CEFBS_None, // G_GET_FPMODE = 209
4234 CEFBS_None, // G_SET_FPMODE = 210
4235 CEFBS_None, // G_RESET_FPMODE = 211
4236 CEFBS_None, // G_PTR_ADD = 212
4237 CEFBS_None, // G_PTRMASK = 213
4238 CEFBS_None, // G_SMIN = 214
4239 CEFBS_None, // G_SMAX = 215
4240 CEFBS_None, // G_UMIN = 216
4241 CEFBS_None, // G_UMAX = 217
4242 CEFBS_None, // G_ABS = 218
4243 CEFBS_None, // G_LROUND = 219
4244 CEFBS_None, // G_LLROUND = 220
4245 CEFBS_None, // G_BR = 221
4246 CEFBS_None, // G_BRJT = 222
4247 CEFBS_None, // G_VSCALE = 223
4248 CEFBS_None, // G_INSERT_SUBVECTOR = 224
4249 CEFBS_None, // G_EXTRACT_SUBVECTOR = 225
4250 CEFBS_None, // G_INSERT_VECTOR_ELT = 226
4251 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 227
4252 CEFBS_None, // G_SHUFFLE_VECTOR = 228
4253 CEFBS_None, // G_SPLAT_VECTOR = 229
4254 CEFBS_None, // G_VECTOR_COMPRESS = 230
4255 CEFBS_None, // G_CTTZ = 231
4256 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 232
4257 CEFBS_None, // G_CTLZ = 233
4258 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 234
4259 CEFBS_None, // G_CTPOP = 235
4260 CEFBS_None, // G_BSWAP = 236
4261 CEFBS_None, // G_BITREVERSE = 237
4262 CEFBS_None, // G_FCEIL = 238
4263 CEFBS_None, // G_FCOS = 239
4264 CEFBS_None, // G_FSIN = 240
4265 CEFBS_None, // G_FTAN = 241
4266 CEFBS_None, // G_FACOS = 242
4267 CEFBS_None, // G_FASIN = 243
4268 CEFBS_None, // G_FATAN = 244
4269 CEFBS_None, // G_FCOSH = 245
4270 CEFBS_None, // G_FSINH = 246
4271 CEFBS_None, // G_FTANH = 247
4272 CEFBS_None, // G_FSQRT = 248
4273 CEFBS_None, // G_FFLOOR = 249
4274 CEFBS_None, // G_FRINT = 250
4275 CEFBS_None, // G_FNEARBYINT = 251
4276 CEFBS_None, // G_ADDRSPACE_CAST = 252
4277 CEFBS_None, // G_BLOCK_ADDR = 253
4278 CEFBS_None, // G_JUMP_TABLE = 254
4279 CEFBS_None, // G_DYN_STACKALLOC = 255
4280 CEFBS_None, // G_STACKSAVE = 256
4281 CEFBS_None, // G_STACKRESTORE = 257
4282 CEFBS_None, // G_STRICT_FADD = 258
4283 CEFBS_None, // G_STRICT_FSUB = 259
4284 CEFBS_None, // G_STRICT_FMUL = 260
4285 CEFBS_None, // G_STRICT_FDIV = 261
4286 CEFBS_None, // G_STRICT_FREM = 262
4287 CEFBS_None, // G_STRICT_FMA = 263
4288 CEFBS_None, // G_STRICT_FSQRT = 264
4289 CEFBS_None, // G_STRICT_FLDEXP = 265
4290 CEFBS_None, // G_READ_REGISTER = 266
4291 CEFBS_None, // G_WRITE_REGISTER = 267
4292 CEFBS_None, // G_MEMCPY = 268
4293 CEFBS_None, // G_MEMCPY_INLINE = 269
4294 CEFBS_None, // G_MEMMOVE = 270
4295 CEFBS_None, // G_MEMSET = 271
4296 CEFBS_None, // G_BZERO = 272
4297 CEFBS_None, // G_TRAP = 273
4298 CEFBS_None, // G_DEBUGTRAP = 274
4299 CEFBS_None, // G_UBSANTRAP = 275
4300 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 276
4301 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 277
4302 CEFBS_None, // G_VECREDUCE_FADD = 278
4303 CEFBS_None, // G_VECREDUCE_FMUL = 279
4304 CEFBS_None, // G_VECREDUCE_FMAX = 280
4305 CEFBS_None, // G_VECREDUCE_FMIN = 281
4306 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 282
4307 CEFBS_None, // G_VECREDUCE_FMINIMUM = 283
4308 CEFBS_None, // G_VECREDUCE_ADD = 284
4309 CEFBS_None, // G_VECREDUCE_MUL = 285
4310 CEFBS_None, // G_VECREDUCE_AND = 286
4311 CEFBS_None, // G_VECREDUCE_OR = 287
4312 CEFBS_None, // G_VECREDUCE_XOR = 288
4313 CEFBS_None, // G_VECREDUCE_SMAX = 289
4314 CEFBS_None, // G_VECREDUCE_SMIN = 290
4315 CEFBS_None, // G_VECREDUCE_UMAX = 291
4316 CEFBS_None, // G_VECREDUCE_UMIN = 292
4317 CEFBS_None, // G_SBFX = 293
4318 CEFBS_None, // G_UBFX = 294
4319 CEFBS_None, // ADJCALLSTACKDOWN = 295
4320 CEFBS_None, // ADJCALLSTACKUP = 296
4321 CEFBS_None, // BR_JT = 297
4322 CEFBS_None, // BR_JT32 = 298
4323 CEFBS_None, // EH_RETURN = 299
4324 CEFBS_None, // FRAME_TO_ARGS_OFFSET = 300
4325 CEFBS_None, // LDAWFI = 301
4326 CEFBS_None, // LDWFI = 302
4327 CEFBS_None, // SELECT_CC = 303
4328 CEFBS_None, // STWFI = 304
4329 CEFBS_None, // ADD_2rus = 305
4330 CEFBS_None, // ADD_3r = 306
4331 CEFBS_None, // ANDNOT_2r = 307
4332 CEFBS_None, // AND_3r = 308
4333 CEFBS_None, // ASHR_l2rus = 309
4334 CEFBS_None, // ASHR_l3r = 310
4335 CEFBS_None, // BAU_1r = 311
4336 CEFBS_None, // BITREV_l2r = 312
4337 CEFBS_None, // BLACP_lu10 = 313
4338 CEFBS_None, // BLACP_u10 = 314
4339 CEFBS_None, // BLAT_lu6 = 315
4340 CEFBS_None, // BLAT_u6 = 316
4341 CEFBS_None, // BLA_1r = 317
4342 CEFBS_None, // BLRB_lu10 = 318
4343 CEFBS_None, // BLRB_u10 = 319
4344 CEFBS_None, // BLRF_lu10 = 320
4345 CEFBS_None, // BLRF_u10 = 321
4346 CEFBS_None, // BRBF_lru6 = 322
4347 CEFBS_None, // BRBF_ru6 = 323
4348 CEFBS_None, // BRBT_lru6 = 324
4349 CEFBS_None, // BRBT_ru6 = 325
4350 CEFBS_None, // BRBU_lu6 = 326
4351 CEFBS_None, // BRBU_u6 = 327
4352 CEFBS_None, // BRFF_lru6 = 328
4353 CEFBS_None, // BRFF_ru6 = 329
4354 CEFBS_None, // BRFT_lru6 = 330
4355 CEFBS_None, // BRFT_ru6 = 331
4356 CEFBS_None, // BRFU_lu6 = 332
4357 CEFBS_None, // BRFU_u6 = 333
4358 CEFBS_None, // BRU_1r = 334
4359 CEFBS_None, // BYTEREV_l2r = 335
4360 CEFBS_None, // CHKCT_2r = 336
4361 CEFBS_None, // CHKCT_rus = 337
4362 CEFBS_None, // CLRE_0R = 338
4363 CEFBS_None, // CLRPT_1R = 339
4364 CEFBS_None, // CLRSR_branch_lu6 = 340
4365 CEFBS_None, // CLRSR_branch_u6 = 341
4366 CEFBS_None, // CLRSR_lu6 = 342
4367 CEFBS_None, // CLRSR_u6 = 343
4368 CEFBS_None, // CLZ_l2r = 344
4369 CEFBS_None, // CRC8_l4r = 345
4370 CEFBS_None, // CRC_l3r = 346
4371 CEFBS_None, // DCALL_0R = 347
4372 CEFBS_None, // DENTSP_0R = 348
4373 CEFBS_None, // DGETREG_1r = 349
4374 CEFBS_None, // DIVS_l3r = 350
4375 CEFBS_None, // DIVU_l3r = 351
4376 CEFBS_None, // DRESTSP_0R = 352
4377 CEFBS_None, // DRET_0R = 353
4378 CEFBS_None, // ECALLF_1r = 354
4379 CEFBS_None, // ECALLT_1r = 355
4380 CEFBS_None, // EDU_1r = 356
4381 CEFBS_None, // EEF_2r = 357
4382 CEFBS_None, // EET_2r = 358
4383 CEFBS_None, // EEU_1r = 359
4384 CEFBS_None, // ENDIN_2r = 360
4385 CEFBS_None, // ENTSP_lu6 = 361
4386 CEFBS_None, // ENTSP_u6 = 362
4387 CEFBS_None, // EQ_2rus = 363
4388 CEFBS_None, // EQ_3r = 364
4389 CEFBS_None, // EXTDP_lu6 = 365
4390 CEFBS_None, // EXTDP_u6 = 366
4391 CEFBS_None, // EXTSP_lu6 = 367
4392 CEFBS_None, // EXTSP_u6 = 368
4393 CEFBS_None, // FREER_1r = 369
4394 CEFBS_None, // FREET_0R = 370
4395 CEFBS_None, // GETD_l2r = 371
4396 CEFBS_None, // GETED_0R = 372
4397 CEFBS_None, // GETET_0R = 373
4398 CEFBS_None, // GETID_0R = 374
4399 CEFBS_None, // GETKEP_0R = 375
4400 CEFBS_None, // GETKSP_0R = 376
4401 CEFBS_None, // GETN_l2r = 377
4402 CEFBS_None, // GETPS_l2r = 378
4403 CEFBS_None, // GETR_rus = 379
4404 CEFBS_None, // GETSR_lu6 = 380
4405 CEFBS_None, // GETSR_u6 = 381
4406 CEFBS_None, // GETST_2r = 382
4407 CEFBS_None, // GETTS_2r = 383
4408 CEFBS_None, // INCT_2r = 384
4409 CEFBS_None, // INITCP_2r = 385
4410 CEFBS_None, // INITDP_2r = 386
4411 CEFBS_None, // INITLR_l2r = 387
4412 CEFBS_None, // INITPC_2r = 388
4413 CEFBS_None, // INITSP_2r = 389
4414 CEFBS_None, // INPW_l2rus = 390
4415 CEFBS_None, // INSHR_2r = 391
4416 CEFBS_None, // INT_2r = 392
4417 CEFBS_None, // IN_2r = 393
4418 CEFBS_None, // KCALL_1r = 394
4419 CEFBS_None, // KCALL_lu6 = 395
4420 CEFBS_None, // KCALL_u6 = 396
4421 CEFBS_None, // KENTSP_lu6 = 397
4422 CEFBS_None, // KENTSP_u6 = 398
4423 CEFBS_None, // KRESTSP_lu6 = 399
4424 CEFBS_None, // KRESTSP_u6 = 400
4425 CEFBS_None, // KRET_0R = 401
4426 CEFBS_None, // LADD_l5r = 402
4427 CEFBS_None, // LD16S_3r = 403
4428 CEFBS_None, // LD8U_3r = 404
4429 CEFBS_None, // LDA16B_l3r = 405
4430 CEFBS_None, // LDA16F_l3r = 406
4431 CEFBS_None, // LDAPB_lu10 = 407
4432 CEFBS_None, // LDAPB_u10 = 408
4433 CEFBS_None, // LDAPF_lu10 = 409
4434 CEFBS_None, // LDAPF_lu10_ba = 410
4435 CEFBS_None, // LDAPF_u10 = 411
4436 CEFBS_None, // LDAWB_l2rus = 412
4437 CEFBS_None, // LDAWB_l3r = 413
4438 CEFBS_None, // LDAWCP_lu6 = 414
4439 CEFBS_None, // LDAWCP_u6 = 415
4440 CEFBS_None, // LDAWDP_lru6 = 416
4441 CEFBS_None, // LDAWDP_ru6 = 417
4442 CEFBS_None, // LDAWF_l2rus = 418
4443 CEFBS_None, // LDAWF_l3r = 419
4444 CEFBS_None, // LDAWSP_lru6 = 420
4445 CEFBS_None, // LDAWSP_ru6 = 421
4446 CEFBS_None, // LDC_lru6 = 422
4447 CEFBS_None, // LDC_ru6 = 423
4448 CEFBS_None, // LDET_0R = 424
4449 CEFBS_None, // LDIVU_l5r = 425
4450 CEFBS_None, // LDSED_0R = 426
4451 CEFBS_None, // LDSPC_0R = 427
4452 CEFBS_None, // LDSSR_0R = 428
4453 CEFBS_None, // LDWCP_lru6 = 429
4454 CEFBS_None, // LDWCP_lu10 = 430
4455 CEFBS_None, // LDWCP_ru6 = 431
4456 CEFBS_None, // LDWCP_u10 = 432
4457 CEFBS_None, // LDWDP_lru6 = 433
4458 CEFBS_None, // LDWDP_ru6 = 434
4459 CEFBS_None, // LDWSP_lru6 = 435
4460 CEFBS_None, // LDWSP_ru6 = 436
4461 CEFBS_None, // LDW_2rus = 437
4462 CEFBS_None, // LDW_3r = 438
4463 CEFBS_None, // LMUL_l6r = 439
4464 CEFBS_None, // LSS_3r = 440
4465 CEFBS_None, // LSUB_l5r = 441
4466 CEFBS_None, // LSU_3r = 442
4467 CEFBS_None, // MACCS_l4r = 443
4468 CEFBS_None, // MACCU_l4r = 444
4469 CEFBS_None, // MJOIN_1r = 445
4470 CEFBS_None, // MKMSK_2r = 446
4471 CEFBS_None, // MKMSK_rus = 447
4472 CEFBS_None, // MSYNC_1r = 448
4473 CEFBS_None, // MUL_l3r = 449
4474 CEFBS_None, // NEG = 450
4475 CEFBS_None, // NOT = 451
4476 CEFBS_None, // OR_3r = 452
4477 CEFBS_None, // OUTCT_2r = 453
4478 CEFBS_None, // OUTCT_rus = 454
4479 CEFBS_None, // OUTPW_l2rus = 455
4480 CEFBS_None, // OUTSHR_2r = 456
4481 CEFBS_None, // OUTT_2r = 457
4482 CEFBS_None, // OUT_2r = 458
4483 CEFBS_None, // PEEK_2r = 459
4484 CEFBS_None, // REMS_l3r = 460
4485 CEFBS_None, // REMU_l3r = 461
4486 CEFBS_None, // RETSP_lu6 = 462
4487 CEFBS_None, // RETSP_u6 = 463
4488 CEFBS_None, // SETCLK_l2r = 464
4489 CEFBS_None, // SETCP_1r = 465
4490 CEFBS_None, // SETC_l2r = 466
4491 CEFBS_None, // SETC_lru6 = 467
4492 CEFBS_None, // SETC_ru6 = 468
4493 CEFBS_None, // SETDP_1r = 469
4494 CEFBS_None, // SETD_2r = 470
4495 CEFBS_None, // SETEV_1r = 471
4496 CEFBS_None, // SETKEP_0R = 472
4497 CEFBS_None, // SETN_l2r = 473
4498 CEFBS_None, // SETPSC_2r = 474
4499 CEFBS_None, // SETPS_l2r = 475
4500 CEFBS_None, // SETPT_2r = 476
4501 CEFBS_None, // SETRDY_l2r = 477
4502 CEFBS_None, // SETSP_1r = 478
4503 CEFBS_None, // SETSR_branch_lu6 = 479
4504 CEFBS_None, // SETSR_branch_u6 = 480
4505 CEFBS_None, // SETSR_lu6 = 481
4506 CEFBS_None, // SETSR_u6 = 482
4507 CEFBS_None, // SETTW_l2r = 483
4508 CEFBS_None, // SETV_1r = 484
4509 CEFBS_None, // SEXT_2r = 485
4510 CEFBS_None, // SEXT_rus = 486
4511 CEFBS_None, // SHL_2rus = 487
4512 CEFBS_None, // SHL_3r = 488
4513 CEFBS_None, // SHR_2rus = 489
4514 CEFBS_None, // SHR_3r = 490
4515 CEFBS_None, // SSYNC_0r = 491
4516 CEFBS_None, // ST16_l3r = 492
4517 CEFBS_None, // ST8_l3r = 493
4518 CEFBS_None, // STET_0R = 494
4519 CEFBS_None, // STSED_0R = 495
4520 CEFBS_None, // STSPC_0R = 496
4521 CEFBS_None, // STSSR_0R = 497
4522 CEFBS_None, // STWDP_lru6 = 498
4523 CEFBS_None, // STWDP_ru6 = 499
4524 CEFBS_None, // STWSP_lru6 = 500
4525 CEFBS_None, // STWSP_ru6 = 501
4526 CEFBS_None, // STW_2rus = 502
4527 CEFBS_None, // STW_l3r = 503
4528 CEFBS_None, // SUB_2rus = 504
4529 CEFBS_None, // SUB_3r = 505
4530 CEFBS_None, // SYNCR_1r = 506
4531 CEFBS_None, // TESTCT_2r = 507
4532 CEFBS_None, // TESTLCL_l2r = 508
4533 CEFBS_None, // TESTWCT_2r = 509
4534 CEFBS_None, // TSETMR_2r = 510
4535 CEFBS_None, // TSETR_3r = 511
4536 CEFBS_None, // TSTART_1R = 512
4537 CEFBS_None, // WAITEF_1R = 513
4538 CEFBS_None, // WAITET_1R = 514
4539 CEFBS_None, // WAITEU_0R = 515
4540 CEFBS_None, // XOR_l3r = 516
4541 CEFBS_None, // ZEXT_2r = 517
4542 CEFBS_None, // ZEXT_rus = 518
4543 };
4544
4545 assert(Opcode < 519);
4546 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
4547}
4548
4549} // end namespace XCore_MC
4550} // end namespace llvm
4551#endif // GET_COMPUTE_FEATURES
4552
4553#ifdef GET_AVAILABLE_OPCODE_CHECKER
4554#undef GET_AVAILABLE_OPCODE_CHECKER
4555namespace llvm {
4556namespace XCore_MC {
4557bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
4558 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4559 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4560 FeatureBitset MissingFeatures =
4561 (AvailableFeatures & RequiredFeatures) ^
4562 RequiredFeatures;
4563 return !MissingFeatures.any();
4564}
4565} // end namespace XCore_MC
4566} // end namespace llvm
4567#endif // GET_AVAILABLE_OPCODE_CHECKER
4568
4569#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
4570#undef ENABLE_INSTR_PREDICATE_VERIFIER
4571#include <sstream>
4572
4573namespace llvm {
4574namespace XCore_MC {
4575
4576#ifndef NDEBUG
4577static const char *SubtargetFeatureNames[] = {
4578 nullptr
4579};
4580
4581#endif // NDEBUG
4582
4583void verifyInstructionPredicates(
4584 unsigned Opcode, const FeatureBitset &Features) {
4585#ifndef NDEBUG
4586 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
4587 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
4588 FeatureBitset MissingFeatures =
4589 (AvailableFeatures & RequiredFeatures) ^
4590 RequiredFeatures;
4591 if (MissingFeatures.any()) {
4592 std::ostringstream Msg;
4593 Msg << "Attempting to emit " << &XCoreInstrNameData[XCoreInstrNameIndices[Opcode]]
4594 << " instruction but the ";
4595 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
4596 if (MissingFeatures.test(i))
4597 Msg << SubtargetFeatureNames[i] << " ";
4598 Msg << "predicate(s) are not met";
4599 report_fatal_error(Msg.str().c_str());
4600 }
4601#endif // NDEBUG
4602}
4603} // end namespace XCore_MC
4604} // end namespace llvm
4605#endif // ENABLE_INSTR_PREDICATE_VERIFIER
4606
4607