1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass XCoreMCRegisterClasses[];
17
18namespace XCore {
19enum {
20 NoRegister,
21 CP = 1,
22 DP = 2,
23 LR = 3,
24 SP = 4,
25 R0 = 5,
26 R1 = 6,
27 R2 = 7,
28 R3 = 8,
29 R4 = 9,
30 R5 = 10,
31 R6 = 11,
32 R7 = 12,
33 R8 = 13,
34 R9 = 14,
35 R10 = 15,
36 R11 = 16,
37 NUM_TARGET_REGS // 17
38};
39} // end namespace XCore
40
41// Register classes
42
43namespace XCore {
44enum {
45 RRegsRegClassID = 0,
46 GRRegsRegClassID = 1,
47
48};
49} // end namespace XCore
50
51// Register pressure sets enum.
52namespace XCore {
53enum RegisterPressureSets {
54 GRRegs = 0,
55};
56} // end namespace XCore
57
58} // end namespace llvm
59
60#endif // GET_REGINFO_ENUM
61
62/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
63|* *|
64|* MC Register Information *|
65|* *|
66|* Automatically generated file, do not edit! *|
67|* *|
68\*===----------------------------------------------------------------------===*/
69
70
71#ifdef GET_REGINFO_MC_DESC
72#undef GET_REGINFO_MC_DESC
73
74namespace llvm {
75
76extern const int16_t XCoreRegDiffLists[] = {
77 /* 0 */ 0,
78};
79
80extern const LaneBitmask XCoreLaneMaskLists[] = {
81 /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
82};
83
84extern const uint16_t XCoreSubRegIdxLists[] = {
85 /* 0 */ 0,
86};
87
88
89#ifdef __GNUC__
90#pragma GCC diagnostic push
91#pragma GCC diagnostic ignored "-Woverlength-strings"
92#endif
93extern const char XCoreRegStrings[] = {
94 /* 0 */ "R10\0"
95 /* 4 */ "R0\0"
96 /* 7 */ "R11\0"
97 /* 11 */ "R1\0"
98 /* 14 */ "R2\0"
99 /* 17 */ "R3\0"
100 /* 20 */ "R4\0"
101 /* 23 */ "R5\0"
102 /* 26 */ "R6\0"
103 /* 29 */ "R7\0"
104 /* 32 */ "R8\0"
105 /* 35 */ "R9\0"
106 /* 38 */ "CP\0"
107 /* 41 */ "DP\0"
108 /* 44 */ "SP\0"
109 /* 47 */ "LR\0"
110};
111#ifdef __GNUC__
112#pragma GCC diagnostic pop
113#endif
114
115extern const MCRegisterDesc XCoreRegDesc[] = { // Descriptors
116 { 3, 0, 0, 0, 0, 0, 0 },
117 { 38, 0, 0, 0, 0, 0, 0 },
118 { 41, 0, 0, 0, 1, 0, 0 },
119 { 47, 0, 0, 0, 2, 0, 0 },
120 { 44, 0, 0, 0, 3, 0, 0 },
121 { 4, 0, 0, 0, 4, 0, 0 },
122 { 11, 0, 0, 0, 5, 0, 0 },
123 { 14, 0, 0, 0, 6, 0, 0 },
124 { 17, 0, 0, 0, 7, 0, 0 },
125 { 20, 0, 0, 0, 8, 0, 0 },
126 { 23, 0, 0, 0, 9, 0, 0 },
127 { 26, 0, 0, 0, 10, 0, 0 },
128 { 29, 0, 0, 0, 11, 0, 0 },
129 { 32, 0, 0, 0, 12, 0, 0 },
130 { 35, 0, 0, 0, 13, 0, 0 },
131 { 0, 0, 0, 0, 14, 0, 0 },
132 { 7, 0, 0, 0, 15, 0, 0 },
133};
134
135extern const MCPhysReg XCoreRegUnitRoots[][2] = {
136 { XCore::CP },
137 { XCore::DP },
138 { XCore::LR },
139 { XCore::SP },
140 { XCore::R0 },
141 { XCore::R1 },
142 { XCore::R2 },
143 { XCore::R3 },
144 { XCore::R4 },
145 { XCore::R5 },
146 { XCore::R6 },
147 { XCore::R7 },
148 { XCore::R8 },
149 { XCore::R9 },
150 { XCore::R10 },
151 { XCore::R11 },
152};
153
154namespace { // Register classes...
155 // RRegs Register Class...
156 const MCPhysReg RRegs[] = {
157 XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11, XCore::CP, XCore::DP, XCore::SP, XCore::LR,
158 };
159
160 // RRegs Bit set.
161 const uint8_t RRegsBits[] = {
162 0xfe, 0xff, 0x01,
163 };
164
165 // GRRegs Register Class...
166 const MCPhysReg GRRegs[] = {
167 XCore::R0, XCore::R1, XCore::R2, XCore::R3, XCore::R4, XCore::R5, XCore::R6, XCore::R7, XCore::R8, XCore::R9, XCore::R10, XCore::R11,
168 };
169
170 // GRRegs Bit set.
171 const uint8_t GRRegsBits[] = {
172 0xe0, 0xff, 0x01,
173 };
174
175} // end anonymous namespace
176
177
178#ifdef __GNUC__
179#pragma GCC diagnostic push
180#pragma GCC diagnostic ignored "-Woverlength-strings"
181#endif
182extern const char XCoreRegClassStrings[] = {
183 /* 0 */ "GRRegs\0"
184};
185#ifdef __GNUC__
186#pragma GCC diagnostic pop
187#endif
188
189extern const MCRegisterClass XCoreMCRegisterClasses[] = {
190 { RRegs, RRegsBits, 1, 16, sizeof(RRegsBits), XCore::RRegsRegClassID, 32, 1, false, false },
191 { GRRegs, GRRegsBits, 0, 12, sizeof(GRRegsBits), XCore::GRRegsRegClassID, 32, 1, true, false },
192};
193
194// XCore Dwarf<->LLVM register mappings.
195extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[] = {
196 { 0U, XCore::R0 },
197 { 1U, XCore::R1 },
198 { 2U, XCore::R2 },
199 { 3U, XCore::R3 },
200 { 4U, XCore::R4 },
201 { 5U, XCore::R5 },
202 { 6U, XCore::R6 },
203 { 7U, XCore::R7 },
204 { 8U, XCore::R8 },
205 { 9U, XCore::R9 },
206 { 10U, XCore::R10 },
207 { 11U, XCore::R11 },
208 { 12U, XCore::CP },
209 { 13U, XCore::DP },
210 { 14U, XCore::SP },
211 { 15U, XCore::LR },
212};
213extern const unsigned XCoreDwarfFlavour0Dwarf2LSize = std::size(XCoreDwarfFlavour0Dwarf2L);
214
215extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[] = {
216 { 0U, XCore::R0 },
217 { 1U, XCore::R1 },
218 { 2U, XCore::R2 },
219 { 3U, XCore::R3 },
220 { 4U, XCore::R4 },
221 { 5U, XCore::R5 },
222 { 6U, XCore::R6 },
223 { 7U, XCore::R7 },
224 { 8U, XCore::R8 },
225 { 9U, XCore::R9 },
226 { 10U, XCore::R10 },
227 { 11U, XCore::R11 },
228 { 12U, XCore::CP },
229 { 13U, XCore::DP },
230 { 14U, XCore::SP },
231 { 15U, XCore::LR },
232};
233extern const unsigned XCoreEHFlavour0Dwarf2LSize = std::size(XCoreEHFlavour0Dwarf2L);
234
235extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[] = {
236 { XCore::CP, 12U },
237 { XCore::DP, 13U },
238 { XCore::LR, 15U },
239 { XCore::SP, 14U },
240 { XCore::R0, 0U },
241 { XCore::R1, 1U },
242 { XCore::R2, 2U },
243 { XCore::R3, 3U },
244 { XCore::R4, 4U },
245 { XCore::R5, 5U },
246 { XCore::R6, 6U },
247 { XCore::R7, 7U },
248 { XCore::R8, 8U },
249 { XCore::R9, 9U },
250 { XCore::R10, 10U },
251 { XCore::R11, 11U },
252};
253extern const unsigned XCoreDwarfFlavour0L2DwarfSize = std::size(XCoreDwarfFlavour0L2Dwarf);
254
255extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[] = {
256 { XCore::CP, 12U },
257 { XCore::DP, 13U },
258 { XCore::LR, 15U },
259 { XCore::SP, 14U },
260 { XCore::R0, 0U },
261 { XCore::R1, 1U },
262 { XCore::R2, 2U },
263 { XCore::R3, 3U },
264 { XCore::R4, 4U },
265 { XCore::R5, 5U },
266 { XCore::R6, 6U },
267 { XCore::R7, 7U },
268 { XCore::R8, 8U },
269 { XCore::R9, 9U },
270 { XCore::R10, 10U },
271 { XCore::R11, 11U },
272};
273extern const unsigned XCoreEHFlavour0L2DwarfSize = std::size(XCoreEHFlavour0L2Dwarf);
274
275extern const uint16_t XCoreRegEncodingTable[] = {
276 0,
277 0,
278 0,
279 0,
280 0,
281 0,
282 0,
283 0,
284 0,
285 0,
286 0,
287 0,
288 0,
289 0,
290 0,
291 0,
292 0,
293};
294static inline void InitXCoreMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
295 RI->InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC, XCoreMCRegisterClasses, 2, XCoreRegUnitRoots, 16, XCoreRegDiffLists, XCoreLaneMaskLists, XCoreRegStrings, XCoreRegClassStrings, XCoreSubRegIdxLists, 1,
296XCoreRegEncodingTable);
297
298 switch (DwarfFlavour) {
299 default:
300 llvm_unreachable("Unknown DWARF flavour");
301 case 0:
302 RI->mapDwarfRegsToLLVMRegs(XCoreDwarfFlavour0Dwarf2L, XCoreDwarfFlavour0Dwarf2LSize, false);
303 break;
304 }
305 switch (EHFlavour) {
306 default:
307 llvm_unreachable("Unknown DWARF flavour");
308 case 0:
309 RI->mapDwarfRegsToLLVMRegs(XCoreEHFlavour0Dwarf2L, XCoreEHFlavour0Dwarf2LSize, true);
310 break;
311 }
312 switch (DwarfFlavour) {
313 default:
314 llvm_unreachable("Unknown DWARF flavour");
315 case 0:
316 RI->mapLLVMRegsToDwarfRegs(XCoreDwarfFlavour0L2Dwarf, XCoreDwarfFlavour0L2DwarfSize, false);
317 break;
318 }
319 switch (EHFlavour) {
320 default:
321 llvm_unreachable("Unknown DWARF flavour");
322 case 0:
323 RI->mapLLVMRegsToDwarfRegs(XCoreEHFlavour0L2Dwarf, XCoreEHFlavour0L2DwarfSize, true);
324 break;
325 }
326}
327
328} // end namespace llvm
329
330#endif // GET_REGINFO_MC_DESC
331
332/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
333|* *|
334|* Register Information Header Fragment *|
335|* *|
336|* Automatically generated file, do not edit! *|
337|* *|
338\*===----------------------------------------------------------------------===*/
339
340
341#ifdef GET_REGINFO_HEADER
342#undef GET_REGINFO_HEADER
343
344#include "llvm/CodeGen/TargetRegisterInfo.h"
345
346namespace llvm {
347
348class XCoreFrameLowering;
349
350struct XCoreGenRegisterInfo : public TargetRegisterInfo {
351 explicit XCoreGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
352 unsigned PC = 0, unsigned HwMode = 0);
353 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
354 unsigned getRegUnitWeight(unsigned RegUnit) const override;
355 unsigned getNumRegPressureSets() const override;
356 const char *getRegPressureSetName(unsigned Idx) const override;
357 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
358 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
359 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
360 ArrayRef<const char *> getRegMaskNames() const override;
361 ArrayRef<const uint32_t *> getRegMasks() const override;
362 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
363 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
364 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
365 bool isConstantPhysReg(MCRegister PhysReg) const override final;
366 /// Devirtualized TargetFrameLowering.
367 static const XCoreFrameLowering *getFrameLowering(
368 const MachineFunction &MF);
369};
370
371namespace XCore { // Register classes
372 extern const TargetRegisterClass RRegsRegClass;
373 extern const TargetRegisterClass GRRegsRegClass;
374} // end namespace XCore
375
376} // end namespace llvm
377
378#endif // GET_REGINFO_HEADER
379
380/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
381|* *|
382|* Target Register and Register Classes Information *|
383|* *|
384|* Automatically generated file, do not edit! *|
385|* *|
386\*===----------------------------------------------------------------------===*/
387
388
389#ifdef GET_REGINFO_TARGET_DESC
390#undef GET_REGINFO_TARGET_DESC
391
392namespace llvm {
393
394extern const MCRegisterClass XCoreMCRegisterClasses[];
395
396static const MVT::SimpleValueType VTLists[] = {
397 /* 0 */ MVT::i32, MVT::Other,
398};
399
400static const char *SubRegIndexNameTable[] = { "" };
401
402static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
403 { 65535, 65535 },
404};
405
406
407static const LaneBitmask SubRegIndexLaneMaskTable[] = {
408 LaneBitmask::getAll(),
409 };
410
411
412
413static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
414 // Mode = 0 (Default)
415 { 32, 32, 32, /*VTLists+*/0 }, // RRegs
416 { 32, 32, 32, /*VTLists+*/0 }, // GRRegs
417};
418
419static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
420
421static const uint32_t RRegsSubClassMask[] = {
422 0x00000003,
423};
424
425static const uint32_t GRRegsSubClassMask[] = {
426 0x00000002,
427};
428
429static const uint16_t SuperRegIdxSeqs[] = {
430 /* 0 */ 0,
431};
432
433static const TargetRegisterClass *const GRRegsSuperclasses[] = {
434 &XCore::RRegsRegClass,
435 nullptr
436};
437
438
439namespace XCore { // Register class instances
440 extern const TargetRegisterClass RRegsRegClass = {
441 &XCoreMCRegisterClasses[RRegsRegClassID],
442 RRegsSubClassMask,
443 SuperRegIdxSeqs + 0,
444 LaneBitmask(0x0000000000000001),
445 0,
446 false,
447 0x00, /* TSFlags */
448 false, /* HasDisjunctSubRegs */
449 false, /* CoveredBySubRegs */
450 NullRegClasses,
451 nullptr
452 };
453
454 extern const TargetRegisterClass GRRegsRegClass = {
455 &XCoreMCRegisterClasses[GRRegsRegClassID],
456 GRRegsSubClassMask,
457 SuperRegIdxSeqs + 0,
458 LaneBitmask(0x0000000000000001),
459 0,
460 false,
461 0x00, /* TSFlags */
462 false, /* HasDisjunctSubRegs */
463 false, /* CoveredBySubRegs */
464 GRRegsSuperclasses,
465 nullptr
466 };
467
468} // end namespace XCore
469
470namespace {
471 const TargetRegisterClass *const RegisterClasses[] = {
472 &XCore::RRegsRegClass,
473 &XCore::GRRegsRegClass,
474 };
475} // end anonymous namespace
476
477static const uint8_t CostPerUseTable[] = {
4780, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
479
480
481static const bool InAllocatableClassTable[] = {
482false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, };
483
484
485static const TargetRegisterInfoDesc XCoreRegInfoDesc = { // Extra Descriptors
486CostPerUseTable, 1, InAllocatableClassTable};
487
488/// Get the weight in units of pressure for this register class.
489const RegClassWeight &XCoreGenRegisterInfo::
490getRegClassWeight(const TargetRegisterClass *RC) const {
491 static const RegClassWeight RCWeightTable[] = {
492 {0, 12}, // RRegs
493 {1, 12}, // GRRegs
494 };
495 return RCWeightTable[RC->getID()];
496}
497
498/// Get the weight in units of pressure for this register unit.
499unsigned XCoreGenRegisterInfo::
500getRegUnitWeight(unsigned RegUnit) const {
501 assert(RegUnit < 16 && "invalid register unit");
502 // All register units have unit weight.
503 return 1;
504}
505
506
507// Get the number of dimensions of register pressure.
508unsigned XCoreGenRegisterInfo::getNumRegPressureSets() const {
509 return 1;
510}
511
512// Get the name of this register unit pressure set.
513const char *XCoreGenRegisterInfo::
514getRegPressureSetName(unsigned Idx) const {
515 static const char *PressureNameTable[] = {
516 "GRRegs",
517 };
518 return PressureNameTable[Idx];
519}
520
521// Get the register unit pressure limit for this dimension.
522// This limit must be adjusted dynamically for reserved registers.
523unsigned XCoreGenRegisterInfo::
524getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
525 static const uint8_t PressureLimitTable[] = {
526 12, // 0: GRRegs
527 };
528 return PressureLimitTable[Idx];
529}
530
531/// Table of pressure sets per register class or unit.
532static const int RCSetsTable[] = {
533 /* 0 */ 0, -1,
534};
535
536/// Get the dimensions of register pressure impacted by this register class.
537/// Returns a -1 terminated array of pressure set IDs
538const int *XCoreGenRegisterInfo::
539getRegClassPressureSets(const TargetRegisterClass *RC) const {
540 static const uint8_t RCSetStartTable[] = {
541 1,0,};
542 return &RCSetsTable[RCSetStartTable[RC->getID()]];
543}
544
545/// Get the dimensions of register pressure impacted by this register unit.
546/// Returns a -1 terminated array of pressure set IDs
547const int *XCoreGenRegisterInfo::
548getRegUnitPressureSets(unsigned RegUnit) const {
549 assert(RegUnit < 16 && "invalid register unit");
550 static const uint8_t RUSetStartTable[] = {
551 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,};
552 return &RCSetsTable[RUSetStartTable[RegUnit]];
553}
554
555extern const MCRegisterDesc XCoreRegDesc[];
556extern const int16_t XCoreRegDiffLists[];
557extern const LaneBitmask XCoreLaneMaskLists[];
558extern const char XCoreRegStrings[];
559extern const char XCoreRegClassStrings[];
560extern const MCPhysReg XCoreRegUnitRoots[][2];
561extern const uint16_t XCoreSubRegIdxLists[];
562extern const uint16_t XCoreRegEncodingTable[];
563// XCore Dwarf<->LLVM register mappings.
564extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0Dwarf2L[];
565extern const unsigned XCoreDwarfFlavour0Dwarf2LSize;
566
567extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0Dwarf2L[];
568extern const unsigned XCoreEHFlavour0Dwarf2LSize;
569
570extern const MCRegisterInfo::DwarfLLVMRegPair XCoreDwarfFlavour0L2Dwarf[];
571extern const unsigned XCoreDwarfFlavour0L2DwarfSize;
572
573extern const MCRegisterInfo::DwarfLLVMRegPair XCoreEHFlavour0L2Dwarf[];
574extern const unsigned XCoreEHFlavour0L2DwarfSize;
575
576XCoreGenRegisterInfo::
577XCoreGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
578 unsigned PC, unsigned HwMode)
579 : TargetRegisterInfo(&XCoreRegInfoDesc, RegisterClasses, RegisterClasses+2,
580 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
581 LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
582 InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC,
583 XCoreMCRegisterClasses, 2,
584 XCoreRegUnitRoots,
585 16,
586 XCoreRegDiffLists,
587 XCoreLaneMaskLists,
588 XCoreRegStrings,
589 XCoreRegClassStrings,
590 XCoreSubRegIdxLists,
591 1,
592 XCoreRegEncodingTable);
593
594 switch (DwarfFlavour) {
595 default:
596 llvm_unreachable("Unknown DWARF flavour");
597 case 0:
598 mapDwarfRegsToLLVMRegs(XCoreDwarfFlavour0Dwarf2L, XCoreDwarfFlavour0Dwarf2LSize, false);
599 break;
600 }
601 switch (EHFlavour) {
602 default:
603 llvm_unreachable("Unknown DWARF flavour");
604 case 0:
605 mapDwarfRegsToLLVMRegs(XCoreEHFlavour0Dwarf2L, XCoreEHFlavour0Dwarf2LSize, true);
606 break;
607 }
608 switch (DwarfFlavour) {
609 default:
610 llvm_unreachable("Unknown DWARF flavour");
611 case 0:
612 mapLLVMRegsToDwarfRegs(XCoreDwarfFlavour0L2Dwarf, XCoreDwarfFlavour0L2DwarfSize, false);
613 break;
614 }
615 switch (EHFlavour) {
616 default:
617 llvm_unreachable("Unknown DWARF flavour");
618 case 0:
619 mapLLVMRegsToDwarfRegs(XCoreEHFlavour0L2Dwarf, XCoreEHFlavour0L2DwarfSize, true);
620 break;
621 }
622}
623
624
625
626ArrayRef<const uint32_t *> XCoreGenRegisterInfo::getRegMasks() const {
627 return std::nullopt;
628}
629
630bool XCoreGenRegisterInfo::
631isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
632 return
633 false;
634}
635
636bool XCoreGenRegisterInfo::
637isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
638 return
639 false;
640}
641
642bool XCoreGenRegisterInfo::
643isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
644 return
645 false;
646}
647
648bool XCoreGenRegisterInfo::
649isConstantPhysReg(MCRegister PhysReg) const {
650 return
651 false;
652}
653
654ArrayRef<const char *> XCoreGenRegisterInfo::getRegMaskNames() const {
655 return std::nullopt;
656}
657
658const XCoreFrameLowering *
659XCoreGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
660 return static_cast<const XCoreFrameLowering *>(
661 MF.getSubtarget().getFrameLowering());
662}
663
664} // end namespace llvm
665
666#endif // GET_REGINFO_TARGET_DESC
667
668