1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14} // end namespace llvm
15
16#endif // GET_SUBTARGETINFO_ENUM
17
18
19#ifdef GET_SUBTARGETINFO_MACRO
20#undef GET_SUBTARGETINFO_MACRO
21#endif // GET_SUBTARGETINFO_MACRO
22
23
24#ifdef GET_SUBTARGETINFO_MC_DESC
25#undef GET_SUBTARGETINFO_MC_DESC
26
27namespace llvm {
28
29#ifdef DBGFIELD
30#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
31#endif
32#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
33#define DBGFIELD(x) x,
34#else
35#define DBGFIELD(x)
36#endif
37
38// ===============================================================
39// Data tables for the new per-operand machine model.
40
41// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
42extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[] = {
43 { 0, 0, 0 }, // Invalid
44}; // XCoreWriteProcResTable
45
46// {Cycles, WriteResourceID}
47extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[] = {
48 { 0, 0}, // Invalid
49}; // XCoreWriteLatencyTable
50
51// {UseIdx, WriteResourceID, Cycles}
52extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[] = {
53 {0, 0, 0}, // Invalid
54}; // XCoreReadAdvanceTable
55
56#undef DBGFIELD
57
58static const llvm::MCSchedModel NoSchedModel = {
59 MCSchedModel::DefaultIssueWidth,
60 MCSchedModel::DefaultMicroOpBufferSize,
61 MCSchedModel::DefaultLoopMicroOpBufferSize,
62 MCSchedModel::DefaultLoadLatency,
63 MCSchedModel::DefaultHighLatency,
64 MCSchedModel::DefaultMispredictPenalty,
65 false, // PostRAScheduler
66 false, // CompleteModel
67 false, // EnableIntervals
68 0, // Processor ID
69 nullptr, nullptr, 0, 0, // No instruction-level machine model.
70 nullptr, // No Itinerary
71 nullptr // No extra processor descriptor
72};
73
74// Sorted (by key) array of values for CPU subtype.
75extern const llvm::SubtargetSubTypeKV XCoreSubTypeKV[] = {
76 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
77 { "xs1b-generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
78};
79
80namespace XCore_MC {
81unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
82 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
83 // Don't know how to resolve this scheduling class.
84 return 0;
85}
86} // end namespace XCore_MC
87
88struct XCoreGenMCSubtargetInfo : public MCSubtargetInfo {
89 XCoreGenMCSubtargetInfo(const Triple &TT,
90 StringRef CPU, StringRef TuneCPU, StringRef FS,
91 ArrayRef<SubtargetFeatureKV> PF,
92 ArrayRef<SubtargetSubTypeKV> PD,
93 const MCWriteProcResEntry *WPR,
94 const MCWriteLatencyEntry *WL,
95 const MCReadAdvanceEntry *RA, const InstrStage *IS,
96 const unsigned *OC, const unsigned *FP) :
97 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
98 WPR, WL, RA, IS, OC, FP) { }
99
100 unsigned resolveVariantSchedClass(unsigned SchedClass,
101 const MCInst *MI, const MCInstrInfo *MCII,
102 unsigned CPUID) const override {
103 return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
104 }
105};
106
107static inline MCSubtargetInfo *createXCoreMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
108 return new XCoreGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, std::nullopt, XCoreSubTypeKV,
109 XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
110 nullptr, nullptr, nullptr);
111}
112
113} // end namespace llvm
114
115#endif // GET_SUBTARGETINFO_MC_DESC
116
117
118#ifdef GET_SUBTARGETINFO_TARGET_DESC
119#undef GET_SUBTARGETINFO_TARGET_DESC
120
121#include "llvm/Support/Debug.h"
122#include "llvm/Support/raw_ostream.h"
123
124// ParseSubtargetFeatures - Parses features string setting specified
125// subtarget options.
126void llvm::XCoreSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
127 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
128 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
129 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
130}
131#endif // GET_SUBTARGETINFO_TARGET_DESC
132
133
134#ifdef GET_SUBTARGETINFO_HEADER
135#undef GET_SUBTARGETINFO_HEADER
136
137namespace llvm {
138class DFAPacketizer;
139namespace XCore_MC {
140unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
141} // end namespace XCore_MC
142
143struct XCoreGenSubtargetInfo : public TargetSubtargetInfo {
144 explicit XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
145public:
146 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
147 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
148 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
149};
150} // end namespace llvm
151
152#endif // GET_SUBTARGETINFO_HEADER
153
154
155#ifdef GET_SUBTARGETINFO_CTOR
156#undef GET_SUBTARGETINFO_CTOR
157
158#include "llvm/CodeGen/TargetSchedule.h"
159
160namespace llvm {
161extern const llvm::SubtargetFeatureKV XCoreFeatureKV[];
162extern const llvm::SubtargetSubTypeKV XCoreSubTypeKV[];
163extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[];
164extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[];
165extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[];
166XCoreGenSubtargetInfo::XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
167 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, std::nullopt, ArrayRef(XCoreSubTypeKV, 2),
168 XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
169 nullptr, nullptr, nullptr) {}
170
171unsigned XCoreGenSubtargetInfo
172::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
173 report_fatal_error("Expected a variant SchedClass");
174} // XCoreGenSubtargetInfo::resolveSchedClass
175
176unsigned XCoreGenSubtargetInfo
177::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
178 return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
179} // XCoreGenSubtargetInfo::resolveVariantSchedClass
180
181} // end namespace llvm
182
183#endif // GET_SUBTARGETINFO_CTOR
184
185
186#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
187#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
188
189#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
190
191
192#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
193#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
194
195#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
196
197