1//===--- SystemZ.cpp - Implement SystemZ target feature support -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements SystemZ TargetInfo objects.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SystemZ.h"
14#include "clang/Basic/Builtins.h"
15#include "clang/Basic/LangOptions.h"
16#include "clang/Basic/MacroBuilder.h"
17#include "clang/Basic/TargetBuiltins.h"
18#include "llvm/ADT/StringSwitch.h"
19
20using namespace clang;
21using namespace clang::targets;
22
23static constexpr Builtin::Info BuiltinInfo[] = {
24#define BUILTIN(ID, TYPE, ATTRS) \
25 {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
26#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
27 {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
28#include "clang/Basic/BuiltinsSystemZ.def"
29};
30
31const char *const SystemZTargetInfo::GCCRegNames[] = {
32 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
33 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
34 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
35 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15",
36 /*ap*/"", "cc", /*fp*/"", /*rp*/"", "a0", "a1",
37 "v16", "v18", "v20", "v22", "v17", "v19", "v21", "v23",
38 "v24", "v26", "v28", "v30", "v25", "v27", "v29", "v31"
39};
40
41const TargetInfo::AddlRegName GCCAddlRegNames[] = {
42 {.Names: {"v0"}, .RegNum: 16}, {.Names: {"v2"}, .RegNum: 17}, {.Names: {"v4"}, .RegNum: 18}, {.Names: {"v6"}, .RegNum: 19},
43 {.Names: {"v1"}, .RegNum: 20}, {.Names: {"v3"}, .RegNum: 21}, {.Names: {"v5"}, .RegNum: 22}, {.Names: {"v7"}, .RegNum: 23},
44 {.Names: {"v8"}, .RegNum: 24}, {.Names: {"v10"}, .RegNum: 25}, {.Names: {"v12"}, .RegNum: 26}, {.Names: {"v14"}, .RegNum: 27},
45 {.Names: {"v9"}, .RegNum: 28}, {.Names: {"v11"}, .RegNum: 29}, {.Names: {"v13"}, .RegNum: 30}, {.Names: {"v15"}, .RegNum: 31}
46};
47
48ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
49 return llvm::ArrayRef(GCCRegNames);
50}
51
52ArrayRef<TargetInfo::AddlRegName> SystemZTargetInfo::getGCCAddlRegNames() const {
53 return llvm::ArrayRef(GCCAddlRegNames);
54}
55
56bool SystemZTargetInfo::validateAsmConstraint(
57 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
58 switch (*Name) {
59 default:
60 return false;
61
62 case 'Z':
63 switch (Name[1]) {
64 default:
65 return false;
66 case 'Q': // Address with base and unsigned 12-bit displacement
67 case 'R': // Likewise, plus an index
68 case 'S': // Address with base and signed 20-bit displacement
69 case 'T': // Likewise, plus an index
70 break;
71 }
72 [[fallthrough]];
73 case 'a': // Address register
74 case 'd': // Data register (equivalent to 'r')
75 case 'f': // Floating-point register
76 case 'v': // Vector register
77 Info.setAllowsRegister();
78 return true;
79
80 case 'I': // Unsigned 8-bit constant
81 case 'J': // Unsigned 12-bit constant
82 case 'K': // Signed 16-bit constant
83 case 'L': // Signed 20-bit displacement (on all targets we support)
84 case 'M': // 0x7fffffff
85 return true;
86
87 case 'Q': // Memory with base and unsigned 12-bit displacement
88 case 'R': // Likewise, plus an index
89 case 'S': // Memory with base and signed 20-bit displacement
90 case 'T': // Likewise, plus an index
91 Info.setAllowsMemory();
92 return true;
93 }
94}
95
96struct ISANameRevision {
97 llvm::StringLiteral Name;
98 int ISARevisionID;
99};
100static constexpr ISANameRevision ISARevisions[] = {
101 {.Name: {"arch8"}, .ISARevisionID: 8}, {.Name: {"z10"}, .ISARevisionID: 8},
102 {.Name: {"arch9"}, .ISARevisionID: 9}, {.Name: {"z196"}, .ISARevisionID: 9},
103 {.Name: {"arch10"}, .ISARevisionID: 10}, {.Name: {"zEC12"}, .ISARevisionID: 10},
104 {.Name: {"arch11"}, .ISARevisionID: 11}, {.Name: {"z13"}, .ISARevisionID: 11},
105 {.Name: {"arch12"}, .ISARevisionID: 12}, {.Name: {"z14"}, .ISARevisionID: 12},
106 {.Name: {"arch13"}, .ISARevisionID: 13}, {.Name: {"z15"}, .ISARevisionID: 13},
107 {.Name: {"arch14"}, .ISARevisionID: 14}, {.Name: {"z16"}, .ISARevisionID: 14},
108};
109
110int SystemZTargetInfo::getISARevision(StringRef Name) const {
111 const auto Rev =
112 llvm::find_if(Range: ISARevisions, P: [Name](const ISANameRevision &CR) {
113 return CR.Name == Name;
114 });
115 if (Rev == std::end(arr: ISARevisions))
116 return -1;
117 return Rev->ISARevisionID;
118}
119
120void SystemZTargetInfo::fillValidCPUList(
121 SmallVectorImpl<StringRef> &Values) const {
122 for (const ISANameRevision &Rev : ISARevisions)
123 Values.push_back(Elt: Rev.Name);
124}
125
126bool SystemZTargetInfo::hasFeature(StringRef Feature) const {
127 return llvm::StringSwitch<bool>(Feature)
128 .Case(S: "systemz", Value: true)
129 .Case(S: "arch8", Value: ISARevision >= 8)
130 .Case(S: "arch9", Value: ISARevision >= 9)
131 .Case(S: "arch10", Value: ISARevision >= 10)
132 .Case(S: "arch11", Value: ISARevision >= 11)
133 .Case(S: "arch12", Value: ISARevision >= 12)
134 .Case(S: "arch13", Value: ISARevision >= 13)
135 .Case(S: "arch14", Value: ISARevision >= 14)
136 .Case(S: "htm", Value: HasTransactionalExecution)
137 .Case(S: "vx", Value: HasVector)
138 .Default(Value: false);
139}
140
141unsigned SystemZTargetInfo::getMinGlobalAlign(uint64_t Size,
142 bool HasNonWeakDef) const {
143 // Don't enforce the minimum alignment on an external or weak symbol if
144 // -munaligned-symbols is passed.
145 if (UnalignedSymbols && !HasNonWeakDef)
146 return 0;
147
148 return MinGlobalAlign;
149}
150
151void SystemZTargetInfo::getTargetDefines(const LangOptions &Opts,
152 MacroBuilder &Builder) const {
153 Builder.defineMacro(Name: "__s390__");
154 Builder.defineMacro(Name: "__s390x__");
155 Builder.defineMacro(Name: "__zarch__");
156 Builder.defineMacro(Name: "__LONG_DOUBLE_128__");
157
158 Builder.defineMacro(Name: "__ARCH__", Value: Twine(ISARevision));
159
160 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
161 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
162 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
163 Builder.defineMacro(Name: "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
164
165 if (HasTransactionalExecution)
166 Builder.defineMacro(Name: "__HTM__");
167 if (HasVector)
168 Builder.defineMacro(Name: "__VX__");
169 if (Opts.ZVector)
170 Builder.defineMacro(Name: "__VEC__", Value: "10304");
171}
172
173ArrayRef<Builtin::Info> SystemZTargetInfo::getTargetBuiltins() const {
174 return llvm::ArrayRef(BuiltinInfo, clang::SystemZ::LastTSBuiltin -
175 Builtin::FirstTSBuiltin);
176}
177