1//===--- ARM.cpp - ARM (not AArch64) Helpers for Tools ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ARM.h"
10#include "clang/Driver/Driver.h"
11#include "clang/Driver/DriverDiagnostic.h"
12#include "clang/Driver/Options.h"
13#include "llvm/ADT/StringSwitch.h"
14#include "llvm/Option/ArgList.h"
15#include "llvm/TargetParser/ARMTargetParser.h"
16#include "llvm/TargetParser/Host.h"
17
18using namespace clang::driver;
19using namespace clang::driver::tools;
20using namespace clang;
21using namespace llvm::opt;
22
23// Get SubArch (vN).
24int arm::getARMSubArchVersionNumber(const llvm::Triple &Triple) {
25 llvm::StringRef Arch = Triple.getArchName();
26 return llvm::ARM::parseArchVersion(Arch);
27}
28
29// True if M-profile.
30bool arm::isARMMProfile(const llvm::Triple &Triple) {
31 llvm::StringRef Arch = Triple.getArchName();
32 return llvm::ARM::parseArchProfile(Arch) == llvm::ARM::ProfileKind::M;
33}
34
35// On Arm the endianness of the output file is determined by the target and
36// can be overridden by the pseudo-target flags '-mlittle-endian'/'-EL' and
37// '-mbig-endian'/'-EB'. Unlike other targets the flag does not result in a
38// normalized triple so we must handle the flag here.
39bool arm::isARMBigEndian(const llvm::Triple &Triple, const ArgList &Args) {
40 if (Arg *A = Args.getLastArg(Ids: options::OPT_mlittle_endian,
41 Ids: options::OPT_mbig_endian)) {
42 return !A->getOption().matches(ID: options::OPT_mlittle_endian);
43 }
44
45 return Triple.getArch() == llvm::Triple::armeb ||
46 Triple.getArch() == llvm::Triple::thumbeb;
47}
48
49// True if A-profile.
50bool arm::isARMAProfile(const llvm::Triple &Triple) {
51 llvm::StringRef Arch = Triple.getArchName();
52 return llvm::ARM::parseArchProfile(Arch) == llvm::ARM::ProfileKind::A;
53}
54
55// Get Arch/CPU from args.
56void arm::getARMArchCPUFromArgs(const ArgList &Args, llvm::StringRef &Arch,
57 llvm::StringRef &CPU, bool FromAs) {
58 if (const Arg *A = Args.getLastArg(Ids: clang::driver::options::OPT_mcpu_EQ))
59 CPU = A->getValue();
60 if (const Arg *A = Args.getLastArg(Ids: options::OPT_march_EQ))
61 Arch = A->getValue();
62 if (!FromAs)
63 return;
64
65 for (const Arg *A :
66 Args.filtered(Ids: options::OPT_Wa_COMMA, Ids: options::OPT_Xassembler)) {
67 // Use getValues because -Wa can have multiple arguments
68 // e.g. -Wa,-mcpu=foo,-mcpu=bar
69 for (StringRef Value : A->getValues()) {
70 if (Value.starts_with(Prefix: "-mcpu="))
71 CPU = Value.substr(Start: 6);
72 if (Value.starts_with(Prefix: "-march="))
73 Arch = Value.substr(Start: 7);
74 }
75 }
76}
77
78// Handle -mhwdiv=.
79// FIXME: Use ARMTargetParser.
80static void getARMHWDivFeatures(const Driver &D, const Arg *A,
81 const ArgList &Args, StringRef HWDiv,
82 std::vector<StringRef> &Features) {
83 uint64_t HWDivID = llvm::ARM::parseHWDiv(HWDiv);
84 if (!llvm::ARM::getHWDivFeatures(HWDivKind: HWDivID, Features))
85 D.Diag(DiagID: clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
86}
87
88// Handle -mfpu=.
89static llvm::ARM::FPUKind getARMFPUFeatures(const Driver &D, const Arg *A,
90 const ArgList &Args, StringRef FPU,
91 std::vector<StringRef> &Features) {
92 llvm::ARM::FPUKind FPUKind = llvm::ARM::parseFPU(FPU);
93 if (!llvm::ARM::getFPUFeatures(FPUKind, Features))
94 D.Diag(DiagID: clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
95 return FPUKind;
96}
97
98// Decode ARM features from string like +[no]featureA+[no]featureB+...
99static bool DecodeARMFeatures(const Driver &D, StringRef text, StringRef CPU,
100 llvm::ARM::ArchKind ArchKind,
101 std::vector<StringRef> &Features,
102 llvm::ARM::FPUKind &ArgFPUKind) {
103 SmallVector<StringRef, 8> Split;
104 text.split(A&: Split, Separator: StringRef("+"), MaxSplit: -1, KeepEmpty: false);
105
106 for (StringRef Feature : Split) {
107 if (!appendArchExtFeatures(CPU, AK: ArchKind, ArchExt: Feature, Features, ArgFPUKind))
108 return false;
109 }
110 return true;
111}
112
113static void DecodeARMFeaturesFromCPU(const Driver &D, StringRef CPU,
114 std::vector<StringRef> &Features) {
115 CPU = CPU.split(Separator: "+").first;
116 if (CPU != "generic") {
117 llvm::ARM::ArchKind ArchKind = llvm::ARM::parseCPUArch(CPU);
118 uint64_t Extension = llvm::ARM::getDefaultExtensions(CPU, AK: ArchKind);
119 llvm::ARM::getExtensionFeatures(Extensions: Extension, Features);
120 }
121}
122
123// Check if -march is valid by checking if it can be canonicalised and parsed.
124// getARMArch is used here instead of just checking the -march value in order
125// to handle -march=native correctly.
126static void checkARMArchName(const Driver &D, const Arg *A, const ArgList &Args,
127 llvm::StringRef ArchName, llvm::StringRef CPUName,
128 std::vector<StringRef> &Features,
129 const llvm::Triple &Triple,
130 llvm::ARM::FPUKind &ArgFPUKind) {
131 std::pair<StringRef, StringRef> Split = ArchName.split(Separator: "+");
132
133 std::string MArch = arm::getARMArch(Arch: ArchName, Triple);
134 llvm::ARM::ArchKind ArchKind = llvm::ARM::parseArch(Arch: MArch);
135 if (ArchKind == llvm::ARM::ArchKind::INVALID ||
136 (Split.second.size() &&
137 !DecodeARMFeatures(D, text: Split.second, CPU: CPUName, ArchKind, Features,
138 ArgFPUKind)))
139 D.Diag(DiagID: clang::diag::err_drv_unsupported_option_argument)
140 << A->getSpelling() << A->getValue();
141}
142
143// Check -mcpu=. Needs ArchName to handle -mcpu=generic.
144static void checkARMCPUName(const Driver &D, const Arg *A, const ArgList &Args,
145 llvm::StringRef CPUName, llvm::StringRef ArchName,
146 std::vector<StringRef> &Features,
147 const llvm::Triple &Triple,
148 llvm::ARM::FPUKind &ArgFPUKind) {
149 std::pair<StringRef, StringRef> Split = CPUName.split(Separator: "+");
150
151 std::string CPU = arm::getARMTargetCPU(CPU: CPUName, Arch: ArchName, Triple);
152 llvm::ARM::ArchKind ArchKind =
153 arm::getLLVMArchKindForARM(CPU, Arch: ArchName, Triple);
154 if (ArchKind == llvm::ARM::ArchKind::INVALID ||
155 (Split.second.size() && !DecodeARMFeatures(D, text: Split.second, CPU, ArchKind,
156 Features, ArgFPUKind)))
157 D.Diag(DiagID: clang::diag::err_drv_unsupported_option_argument)
158 << A->getSpelling() << A->getValue();
159}
160
161// If -mfloat-abi=hard or -mhard-float are specified explicitly then check that
162// floating point registers are available on the target CPU.
163static void checkARMFloatABI(const Driver &D, const ArgList &Args,
164 bool HasFPRegs) {
165 if (HasFPRegs)
166 return;
167 const Arg *A =
168 Args.getLastArg(Ids: options::OPT_msoft_float, Ids: options::OPT_mhard_float,
169 Ids: options::OPT_mfloat_abi_EQ);
170 if (A && (A->getOption().matches(ID: options::OPT_mhard_float) ||
171 (A->getOption().matches(ID: options::OPT_mfloat_abi_EQ) &&
172 A->getValue() == StringRef("hard"))))
173 D.Diag(DiagID: clang::diag::warn_drv_no_floating_point_registers)
174 << A->getAsString(Args);
175}
176
177bool arm::useAAPCSForMachO(const llvm::Triple &T) {
178 // The backend is hardwired to assume AAPCS for M-class processors, ensure
179 // the frontend matches that.
180 return T.getEnvironment() == llvm::Triple::EABI ||
181 T.getEnvironment() == llvm::Triple::EABIHF ||
182 T.getOS() == llvm::Triple::UnknownOS || isARMMProfile(Triple: T);
183}
184
185// We follow GCC and support when the backend has support for the MRC/MCR
186// instructions that are used to set the hard thread pointer ("CP15 C13
187// Thread id").
188bool arm::isHardTPSupported(const llvm::Triple &Triple) {
189 int Ver = getARMSubArchVersionNumber(Triple);
190 llvm::ARM::ArchKind AK = llvm::ARM::parseArch(Arch: Triple.getArchName());
191 return Triple.isARM() || AK == llvm::ARM::ArchKind::ARMV6T2 ||
192 (Ver >= 7 && AK != llvm::ARM::ArchKind::ARMV8MBaseline);
193}
194
195// Select mode for reading thread pointer (-mtp=soft/cp15).
196arm::ReadTPMode arm::getReadTPMode(const Driver &D, const ArgList &Args,
197 const llvm::Triple &Triple, bool ForAS) {
198 if (Arg *A = Args.getLastArg(Ids: options::OPT_mtp_mode_EQ)) {
199 arm::ReadTPMode ThreadPointer =
200 llvm::StringSwitch<arm::ReadTPMode>(A->getValue())
201 .Case(S: "cp15", Value: ReadTPMode::TPIDRURO)
202 .Case(S: "tpidrurw", Value: ReadTPMode::TPIDRURW)
203 .Case(S: "tpidruro", Value: ReadTPMode::TPIDRURO)
204 .Case(S: "tpidrprw", Value: ReadTPMode::TPIDRPRW)
205 .Case(S: "soft", Value: ReadTPMode::Soft)
206 .Default(Value: ReadTPMode::Invalid);
207 if ((ThreadPointer == ReadTPMode::TPIDRURW ||
208 ThreadPointer == ReadTPMode::TPIDRURO ||
209 ThreadPointer == ReadTPMode::TPIDRPRW) &&
210 !isHardTPSupported(Triple) && !ForAS) {
211 D.Diag(DiagID: diag::err_target_unsupported_tp_hard) << Triple.getArchName();
212 return ReadTPMode::Invalid;
213 }
214 if (ThreadPointer != ReadTPMode::Invalid)
215 return ThreadPointer;
216 if (StringRef(A->getValue()).empty())
217 D.Diag(DiagID: diag::err_drv_missing_arg_mtp) << A->getAsString(Args);
218 else
219 D.Diag(DiagID: diag::err_drv_invalid_mtp) << A->getAsString(Args);
220 return ReadTPMode::Invalid;
221 }
222 return ReadTPMode::Soft;
223}
224
225void arm::setArchNameInTriple(const Driver &D, const ArgList &Args,
226 types::ID InputType, llvm::Triple &Triple) {
227 StringRef MCPU, MArch;
228 if (const Arg *A = Args.getLastArg(Ids: options::OPT_mcpu_EQ))
229 MCPU = A->getValue();
230 if (const Arg *A = Args.getLastArg(Ids: options::OPT_march_EQ))
231 MArch = A->getValue();
232
233 std::string CPU = Triple.isOSBinFormatMachO()
234 ? tools::arm::getARMCPUForMArch(Arch: MArch, Triple).str()
235 : tools::arm::getARMTargetCPU(CPU: MCPU, Arch: MArch, Triple);
236 StringRef Suffix = tools::arm::getLLVMArchSuffixForARM(CPU, Arch: MArch, Triple);
237
238 bool IsBigEndian = Triple.getArch() == llvm::Triple::armeb ||
239 Triple.getArch() == llvm::Triple::thumbeb;
240 // Handle pseudo-target flags '-mlittle-endian'/'-EL' and
241 // '-mbig-endian'/'-EB'.
242 if (Arg *A = Args.getLastArg(Ids: options::OPT_mlittle_endian,
243 Ids: options::OPT_mbig_endian)) {
244 IsBigEndian = !A->getOption().matches(ID: options::OPT_mlittle_endian);
245 }
246 std::string ArchName = IsBigEndian ? "armeb" : "arm";
247
248 // FIXME: Thumb should just be another -target-feaure, not in the triple.
249 bool IsMProfile =
250 llvm::ARM::parseArchProfile(Arch: Suffix) == llvm::ARM::ProfileKind::M;
251 bool ThumbDefault = IsMProfile ||
252 // Thumb2 is the default for V7 on Darwin.
253 (llvm::ARM::parseArchVersion(Arch: Suffix) == 7 &&
254 Triple.isOSBinFormatMachO()) ||
255 // FIXME: this is invalid for WindowsCE
256 Triple.isOSWindows();
257
258 // Check if ARM ISA was explicitly selected (using -mno-thumb or -marm) for
259 // M-Class CPUs/architecture variants, which is not supported.
260 bool ARMModeRequested =
261 !Args.hasFlag(Pos: options::OPT_mthumb, Neg: options::OPT_mno_thumb, Default: ThumbDefault);
262 if (IsMProfile && ARMModeRequested) {
263 if (MCPU.size())
264 D.Diag(DiagID: diag::err_cpu_unsupported_isa) << CPU << "ARM";
265 else
266 D.Diag(DiagID: diag::err_arch_unsupported_isa)
267 << tools::arm::getARMArch(Arch: MArch, Triple) << "ARM";
268 }
269
270 // Check to see if an explicit choice to use thumb has been made via
271 // -mthumb. For assembler files we must check for -mthumb in the options
272 // passed to the assembler via -Wa or -Xassembler.
273 bool IsThumb = false;
274 if (InputType != types::TY_PP_Asm)
275 IsThumb =
276 Args.hasFlag(Pos: options::OPT_mthumb, Neg: options::OPT_mno_thumb, Default: ThumbDefault);
277 else {
278 // Ideally we would check for these flags in
279 // CollectArgsForIntegratedAssembler but we can't change the ArchName at
280 // that point.
281 llvm::StringRef WaMArch, WaMCPU;
282 for (const auto *A :
283 Args.filtered(Ids: options::OPT_Wa_COMMA, Ids: options::OPT_Xassembler)) {
284 for (StringRef Value : A->getValues()) {
285 // There is no assembler equivalent of -mno-thumb, -marm, or -mno-arm.
286 if (Value == "-mthumb")
287 IsThumb = true;
288 else if (Value.starts_with(Prefix: "-march="))
289 WaMArch = Value.substr(Start: 7);
290 else if (Value.starts_with(Prefix: "-mcpu="))
291 WaMCPU = Value.substr(Start: 6);
292 }
293 }
294
295 if (WaMCPU.size() || WaMArch.size()) {
296 // The way this works means that we prefer -Wa,-mcpu's architecture
297 // over -Wa,-march. Which matches the compiler behaviour.
298 Suffix = tools::arm::getLLVMArchSuffixForARM(CPU: WaMCPU, Arch: WaMArch, Triple);
299 }
300 }
301
302 // Assembly files should start in ARM mode, unless arch is M-profile, or
303 // -mthumb has been passed explicitly to the assembler. Windows is always
304 // thumb.
305 if (IsThumb || IsMProfile || Triple.isOSWindows()) {
306 if (IsBigEndian)
307 ArchName = "thumbeb";
308 else
309 ArchName = "thumb";
310 }
311 Triple.setArchName(ArchName + Suffix.str());
312}
313
314void arm::setFloatABIInTriple(const Driver &D, const ArgList &Args,
315 llvm::Triple &Triple) {
316 if (Triple.isOSLiteOS()) {
317 Triple.setEnvironment(llvm::Triple::OpenHOS);
318 return;
319 }
320
321 bool isHardFloat =
322 (arm::getARMFloatABI(D, Triple, Args) == arm::FloatABI::Hard);
323
324 switch (Triple.getEnvironment()) {
325 case llvm::Triple::GNUEABI:
326 case llvm::Triple::GNUEABIHF:
327 Triple.setEnvironment(isHardFloat ? llvm::Triple::GNUEABIHF
328 : llvm::Triple::GNUEABI);
329 break;
330 case llvm::Triple::EABI:
331 case llvm::Triple::EABIHF:
332 Triple.setEnvironment(isHardFloat ? llvm::Triple::EABIHF
333 : llvm::Triple::EABI);
334 break;
335 case llvm::Triple::MuslEABI:
336 case llvm::Triple::MuslEABIHF:
337 Triple.setEnvironment(isHardFloat ? llvm::Triple::MuslEABIHF
338 : llvm::Triple::MuslEABI);
339 break;
340 case llvm::Triple::OpenHOS:
341 break;
342 default: {
343 arm::FloatABI DefaultABI = arm::getDefaultFloatABI(Triple);
344 if (DefaultABI != arm::FloatABI::Invalid &&
345 isHardFloat != (DefaultABI == arm::FloatABI::Hard)) {
346 Arg *ABIArg =
347 Args.getLastArg(Ids: options::OPT_msoft_float, Ids: options::OPT_mhard_float,
348 Ids: options::OPT_mfloat_abi_EQ);
349 assert(ABIArg && "Non-default float abi expected to be from arg");
350 D.Diag(DiagID: diag::err_drv_unsupported_opt_for_target)
351 << ABIArg->getAsString(Args) << Triple.getTriple();
352 }
353 break;
354 }
355 }
356}
357
358arm::FloatABI arm::getARMFloatABI(const ToolChain &TC, const ArgList &Args) {
359 return arm::getARMFloatABI(D: TC.getDriver(), Triple: TC.getEffectiveTriple(), Args);
360}
361
362arm::FloatABI arm::getDefaultFloatABI(const llvm::Triple &Triple) {
363 auto SubArch = getARMSubArchVersionNumber(Triple);
364 switch (Triple.getOS()) {
365 case llvm::Triple::Darwin:
366 case llvm::Triple::MacOSX:
367 case llvm::Triple::IOS:
368 case llvm::Triple::TvOS:
369 case llvm::Triple::DriverKit:
370 case llvm::Triple::XROS:
371 // Darwin defaults to "softfp" for v6 and v7.
372 if (Triple.isWatchABI())
373 return FloatABI::Hard;
374 else
375 return (SubArch == 6 || SubArch == 7) ? FloatABI::SoftFP : FloatABI::Soft;
376
377 case llvm::Triple::WatchOS:
378 return FloatABI::Hard;
379
380 // FIXME: this is invalid for WindowsCE
381 case llvm::Triple::Win32:
382 // It is incorrect to select hard float ABI on MachO platforms if the ABI is
383 // "apcs-gnu".
384 if (Triple.isOSBinFormatMachO() && !useAAPCSForMachO(T: Triple))
385 return FloatABI::Soft;
386 return FloatABI::Hard;
387
388 case llvm::Triple::NetBSD:
389 switch (Triple.getEnvironment()) {
390 case llvm::Triple::EABIHF:
391 case llvm::Triple::GNUEABIHF:
392 return FloatABI::Hard;
393 default:
394 return FloatABI::Soft;
395 }
396 break;
397
398 case llvm::Triple::FreeBSD:
399 switch (Triple.getEnvironment()) {
400 case llvm::Triple::GNUEABIHF:
401 return FloatABI::Hard;
402 default:
403 // FreeBSD defaults to soft float
404 return FloatABI::Soft;
405 }
406 break;
407
408 case llvm::Triple::Haiku:
409 case llvm::Triple::OpenBSD:
410 return FloatABI::SoftFP;
411
412 default:
413 if (Triple.isOHOSFamily())
414 return FloatABI::Soft;
415 switch (Triple.getEnvironment()) {
416 case llvm::Triple::GNUEABIHF:
417 case llvm::Triple::MuslEABIHF:
418 case llvm::Triple::EABIHF:
419 return FloatABI::Hard;
420 case llvm::Triple::GNUEABI:
421 case llvm::Triple::MuslEABI:
422 case llvm::Triple::EABI:
423 // EABI is always AAPCS, and if it was not marked 'hard', it's softfp
424 return FloatABI::SoftFP;
425 case llvm::Triple::Android:
426 return (SubArch >= 7) ? FloatABI::SoftFP : FloatABI::Soft;
427 default:
428 return FloatABI::Invalid;
429 }
430 }
431 return FloatABI::Invalid;
432}
433
434// Select the float ABI as determined by -msoft-float, -mhard-float, and
435// -mfloat-abi=.
436arm::FloatABI arm::getARMFloatABI(const Driver &D, const llvm::Triple &Triple,
437 const ArgList &Args) {
438 arm::FloatABI ABI = FloatABI::Invalid;
439 if (Arg *A =
440 Args.getLastArg(Ids: options::OPT_msoft_float, Ids: options::OPT_mhard_float,
441 Ids: options::OPT_mfloat_abi_EQ)) {
442 if (A->getOption().matches(ID: options::OPT_msoft_float)) {
443 ABI = FloatABI::Soft;
444 } else if (A->getOption().matches(ID: options::OPT_mhard_float)) {
445 ABI = FloatABI::Hard;
446 } else {
447 ABI = llvm::StringSwitch<arm::FloatABI>(A->getValue())
448 .Case(S: "soft", Value: FloatABI::Soft)
449 .Case(S: "softfp", Value: FloatABI::SoftFP)
450 .Case(S: "hard", Value: FloatABI::Hard)
451 .Default(Value: FloatABI::Invalid);
452 if (ABI == FloatABI::Invalid && !StringRef(A->getValue()).empty()) {
453 D.Diag(DiagID: diag::err_drv_invalid_mfloat_abi) << A->getAsString(Args);
454 ABI = FloatABI::Soft;
455 }
456 }
457 }
458
459 // If unspecified, choose the default based on the platform.
460 if (ABI == FloatABI::Invalid)
461 ABI = arm::getDefaultFloatABI(Triple);
462
463 if (ABI == FloatABI::Invalid) {
464 // Assume "soft", but warn the user we are guessing.
465 if (Triple.isOSBinFormatMachO() &&
466 Triple.getSubArch() == llvm::Triple::ARMSubArch_v7em)
467 ABI = FloatABI::Hard;
468 else
469 ABI = FloatABI::Soft;
470
471 if (Triple.getOS() != llvm::Triple::UnknownOS ||
472 !Triple.isOSBinFormatMachO())
473 D.Diag(DiagID: diag::warn_drv_assuming_mfloat_abi_is) << "soft";
474 }
475
476 assert(ABI != FloatABI::Invalid && "must select an ABI");
477 return ABI;
478}
479
480static bool hasIntegerMVE(const std::vector<StringRef> &F) {
481 auto MVE = llvm::find(Range: llvm::reverse(C: F), Val: "+mve");
482 auto NoMVE = llvm::find(Range: llvm::reverse(C: F), Val: "-mve");
483 return MVE != F.rend() &&
484 (NoMVE == F.rend() || std::distance(first: MVE, last: NoMVE) > 0);
485}
486
487llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver &D,
488 const llvm::Triple &Triple,
489 const ArgList &Args,
490 std::vector<StringRef> &Features,
491 bool ForAS, bool ForMultilib) {
492 bool KernelOrKext =
493 Args.hasArg(Ids: options::OPT_mkernel, Ids: options::OPT_fapple_kext);
494 arm::FloatABI ABI = arm::getARMFloatABI(D, Triple, Args);
495 std::optional<std::pair<const Arg *, StringRef>> WaCPU, WaFPU, WaHDiv, WaArch;
496
497 // This vector will accumulate features from the architecture
498 // extension suffixes on -mcpu and -march (e.g. the 'bar' in
499 // -mcpu=foo+bar). We want to apply those after the features derived
500 // from the FPU, in case -mfpu generates a negative feature which
501 // the +bar is supposed to override.
502 std::vector<StringRef> ExtensionFeatures;
503
504 if (!ForAS) {
505 // FIXME: Note, this is a hack, the LLVM backend doesn't actually use these
506 // yet (it uses the -mfloat-abi and -msoft-float options), and it is
507 // stripped out by the ARM target. We should probably pass this a new
508 // -target-option, which is handled by the -cc1/-cc1as invocation.
509 //
510 // FIXME2: For consistency, it would be ideal if we set up the target
511 // machine state the same when using the frontend or the assembler. We don't
512 // currently do that for the assembler, we pass the options directly to the
513 // backend and never even instantiate the frontend TargetInfo. If we did,
514 // and used its handleTargetFeatures hook, then we could ensure the
515 // assembler and the frontend behave the same.
516
517 // Use software floating point operations?
518 if (ABI == arm::FloatABI::Soft)
519 Features.push_back(x: "+soft-float");
520
521 // Use software floating point argument passing?
522 if (ABI != arm::FloatABI::Hard)
523 Features.push_back(x: "+soft-float-abi");
524 } else {
525 // Here, we make sure that -Wa,-mfpu/cpu/arch/hwdiv will be passed down
526 // to the assembler correctly.
527 for (const Arg *A :
528 Args.filtered(Ids: options::OPT_Wa_COMMA, Ids: options::OPT_Xassembler)) {
529 // We use getValues here because you can have many options per -Wa
530 // We will keep the last one we find for each of these
531 for (StringRef Value : A->getValues()) {
532 if (Value.starts_with(Prefix: "-mfpu=")) {
533 WaFPU = std::make_pair(x&: A, y: Value.substr(Start: 6));
534 } else if (Value.starts_with(Prefix: "-mcpu=")) {
535 WaCPU = std::make_pair(x&: A, y: Value.substr(Start: 6));
536 } else if (Value.starts_with(Prefix: "-mhwdiv=")) {
537 WaHDiv = std::make_pair(x&: A, y: Value.substr(Start: 8));
538 } else if (Value.starts_with(Prefix: "-march=")) {
539 WaArch = std::make_pair(x&: A, y: Value.substr(Start: 7));
540 }
541 }
542 }
543
544 // The integrated assembler doesn't implement e_flags setting behavior for
545 // -meabi=gnu (gcc -mabi={apcs-gnu,atpcs} passes -meabi=gnu to gas). For
546 // compatibility we accept but warn.
547 if (Arg *A = Args.getLastArgNoClaim(Ids: options::OPT_mabi_EQ))
548 A->ignoreTargetSpecific();
549 }
550
551 if (getReadTPMode(D, Args, Triple, ForAS) == ReadTPMode::TPIDRURW)
552 Features.push_back(x: "+read-tp-tpidrurw");
553 if (getReadTPMode(D, Args, Triple, ForAS) == ReadTPMode::TPIDRURO)
554 Features.push_back(x: "+read-tp-tpidruro");
555 if (getReadTPMode(D, Args, Triple, ForAS) == ReadTPMode::TPIDRPRW)
556 Features.push_back(x: "+read-tp-tpidrprw");
557
558 const Arg *ArchArg = Args.getLastArg(Ids: options::OPT_march_EQ);
559 const Arg *CPUArg = Args.getLastArg(Ids: options::OPT_mcpu_EQ);
560 StringRef ArchName;
561 StringRef CPUName;
562 llvm::ARM::FPUKind ArchArgFPUKind = llvm::ARM::FK_INVALID;
563 llvm::ARM::FPUKind CPUArgFPUKind = llvm::ARM::FK_INVALID;
564
565 // Check -mcpu. ClangAs gives preference to -Wa,-mcpu=.
566 if (WaCPU) {
567 if (CPUArg)
568 D.Diag(DiagID: clang::diag::warn_drv_unused_argument)
569 << CPUArg->getAsString(Args);
570 CPUName = WaCPU->second;
571 CPUArg = WaCPU->first;
572 } else if (CPUArg)
573 CPUName = CPUArg->getValue();
574
575 // Check -march. ClangAs gives preference to -Wa,-march=.
576 if (WaArch) {
577 if (ArchArg)
578 D.Diag(DiagID: clang::diag::warn_drv_unused_argument)
579 << ArchArg->getAsString(Args);
580 ArchName = WaArch->second;
581 // This will set any features after the base architecture.
582 checkARMArchName(D, A: WaArch->first, Args, ArchName, CPUName,
583 Features&: ExtensionFeatures, Triple, ArgFPUKind&: ArchArgFPUKind);
584 // The base architecture was handled in ToolChain::ComputeLLVMTriple because
585 // triple is read only by this point.
586 } else if (ArchArg) {
587 ArchName = ArchArg->getValue();
588 checkARMArchName(D, A: ArchArg, Args, ArchName, CPUName, Features&: ExtensionFeatures,
589 Triple, ArgFPUKind&: ArchArgFPUKind);
590 }
591
592 // Add CPU features for generic CPUs
593 if (CPUName == "native") {
594 for (auto &F : llvm::sys::getHostCPUFeatures())
595 Features.push_back(
596 x: Args.MakeArgString(Str: (F.second ? "+" : "-") + F.first()));
597 } else if (!CPUName.empty()) {
598 // This sets the default features for the specified CPU. We certainly don't
599 // want to override the features that have been explicitly specified on the
600 // command line. Therefore, process them directly instead of appending them
601 // at the end later.
602 DecodeARMFeaturesFromCPU(D, CPU: CPUName, Features);
603 }
604
605 if (CPUArg)
606 checkARMCPUName(D, A: CPUArg, Args, CPUName, ArchName, Features&: ExtensionFeatures,
607 Triple, ArgFPUKind&: CPUArgFPUKind);
608
609 // TODO Handle -mtune=. Suppress -Wunused-command-line-argument as a
610 // longstanding behavior.
611 (void)Args.getLastArg(Ids: options::OPT_mtune_EQ);
612
613 // Honor -mfpu=. ClangAs gives preference to -Wa,-mfpu=.
614 llvm::ARM::FPUKind FPUKind = llvm::ARM::FK_INVALID;
615 const Arg *FPUArg = Args.getLastArg(Ids: options::OPT_mfpu_EQ);
616 if (WaFPU) {
617 if (FPUArg)
618 D.Diag(DiagID: clang::diag::warn_drv_unused_argument)
619 << FPUArg->getAsString(Args);
620 (void)getARMFPUFeatures(D, A: WaFPU->first, Args, FPU: WaFPU->second, Features);
621 } else if (FPUArg) {
622 FPUKind = getARMFPUFeatures(D, A: FPUArg, Args, FPU: FPUArg->getValue(), Features);
623 } else if (Triple.isAndroid() && getARMSubArchVersionNumber(Triple) >= 7) {
624 const char *AndroidFPU = "neon";
625 FPUKind = llvm::ARM::parseFPU(FPU: AndroidFPU);
626 if (!llvm::ARM::getFPUFeatures(FPUKind, Features))
627 D.Diag(DiagID: clang::diag::err_drv_clang_unsupported)
628 << std::string("-mfpu=") + AndroidFPU;
629 } else if (ArchArgFPUKind != llvm::ARM::FK_INVALID ||
630 CPUArgFPUKind != llvm::ARM::FK_INVALID) {
631 FPUKind =
632 CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind : ArchArgFPUKind;
633 (void)llvm::ARM::getFPUFeatures(FPUKind, Features);
634 } else {
635 if (!ForAS) {
636 std::string CPU = arm::getARMTargetCPU(CPU: CPUName, Arch: ArchName, Triple);
637 llvm::ARM::ArchKind ArchKind =
638 arm::getLLVMArchKindForARM(CPU, Arch: ArchName, Triple);
639 FPUKind = llvm::ARM::getDefaultFPU(CPU, AK: ArchKind);
640 (void)llvm::ARM::getFPUFeatures(FPUKind, Features);
641 }
642 }
643
644 // Now we've finished accumulating features from arch, cpu and fpu,
645 // we can append the ones for architecture extensions that we
646 // collected separately.
647 Features.insert(position: std::end(cont&: Features),
648 first: std::begin(cont&: ExtensionFeatures), last: std::end(cont&: ExtensionFeatures));
649
650 // Honor -mhwdiv=. ClangAs gives preference to -Wa,-mhwdiv=.
651 const Arg *HDivArg = Args.getLastArg(Ids: options::OPT_mhwdiv_EQ);
652 if (WaHDiv) {
653 if (HDivArg)
654 D.Diag(DiagID: clang::diag::warn_drv_unused_argument)
655 << HDivArg->getAsString(Args);
656 getARMHWDivFeatures(D, A: WaHDiv->first, Args, HWDiv: WaHDiv->second, Features);
657 } else if (HDivArg)
658 getARMHWDivFeatures(D, A: HDivArg, Args, HWDiv: HDivArg->getValue(), Features);
659
660 // Handle (arch-dependent) fp16fml/fullfp16 relationship.
661 // Must happen before any features are disabled due to soft-float.
662 // FIXME: this fp16fml option handling will be reimplemented after the
663 // TargetParser rewrite.
664 const auto ItRNoFullFP16 = std::find(first: Features.rbegin(), last: Features.rend(), val: "-fullfp16");
665 const auto ItRFP16FML = std::find(first: Features.rbegin(), last: Features.rend(), val: "+fp16fml");
666 if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v8_4a) {
667 const auto ItRFullFP16 = std::find(first: Features.rbegin(), last: Features.rend(), val: "+fullfp16");
668 if (ItRFullFP16 < ItRNoFullFP16 && ItRFullFP16 < ItRFP16FML) {
669 // Only entangled feature that can be to the right of this +fullfp16 is -fp16fml.
670 // Only append the +fp16fml if there is no -fp16fml after the +fullfp16.
671 if (std::find(first: Features.rbegin(), last: ItRFullFP16, val: "-fp16fml") == ItRFullFP16)
672 Features.push_back(x: "+fp16fml");
673 }
674 else
675 goto fp16_fml_fallthrough;
676 }
677 else {
678fp16_fml_fallthrough:
679 // In both of these cases, putting the 'other' feature on the end of the vector will
680 // result in the same effect as placing it immediately after the current feature.
681 if (ItRNoFullFP16 < ItRFP16FML)
682 Features.push_back(x: "-fp16fml");
683 else if (ItRNoFullFP16 > ItRFP16FML)
684 Features.push_back(x: "+fullfp16");
685 }
686
687 // Setting -msoft-float/-mfloat-abi=soft, -mfpu=none, or adding +nofp to
688 // -march/-mcpu effectively disables the FPU (GCC ignores the -mfpu options in
689 // this case). Note that the ABI can also be set implicitly by the target
690 // selected.
691 bool HasFPRegs = true;
692 if (ABI == arm::FloatABI::Soft) {
693 llvm::ARM::getFPUFeatures(FPUKind: llvm::ARM::FK_NONE, Features);
694
695 // Disable all features relating to hardware FP, not already disabled by the
696 // above call.
697 Features.insert(position: Features.end(),
698 l: {"-dotprod", "-fp16fml", "-bf16", "-mve", "-mve.fp"});
699 HasFPRegs = false;
700 FPUKind = llvm::ARM::FK_NONE;
701 } else if (FPUKind == llvm::ARM::FK_NONE ||
702 ArchArgFPUKind == llvm::ARM::FK_NONE ||
703 CPUArgFPUKind == llvm::ARM::FK_NONE) {
704 // -mfpu=none, -march=armvX+nofp or -mcpu=X+nofp is *very* similar to
705 // -mfloat-abi=soft, only that it should not disable MVE-I. They disable the
706 // FPU, but not the FPU registers, thus MVE-I, which depends only on the
707 // latter, is still supported.
708 Features.insert(position: Features.end(),
709 l: {"-dotprod", "-fp16fml", "-bf16", "-mve.fp"});
710 HasFPRegs = hasIntegerMVE(F: Features);
711 FPUKind = llvm::ARM::FK_NONE;
712 }
713 if (!HasFPRegs)
714 Features.emplace_back(args: "-fpregs");
715
716 // En/disable crc code generation.
717 if (Arg *A = Args.getLastArg(Ids: options::OPT_mcrc, Ids: options::OPT_mnocrc)) {
718 if (A->getOption().matches(ID: options::OPT_mcrc))
719 Features.push_back(x: "+crc");
720 else
721 Features.push_back(x: "-crc");
722 }
723
724 // For Arch >= ARMv8.0 && A or R profile: crypto = sha2 + aes
725 // Rather than replace within the feature vector, determine whether each
726 // algorithm is enabled and append this to the end of the vector.
727 // The algorithms can be controlled by their specific feature or the crypto
728 // feature, so their status can be determined by the last occurance of
729 // either in the vector. This allows one to supercede the other.
730 // e.g. +crypto+noaes in -march/-mcpu should enable sha2, but not aes
731 // FIXME: this needs reimplementation after the TargetParser rewrite
732 bool HasSHA2 = false;
733 bool HasAES = false;
734 const auto ItCrypto =
735 llvm::find_if(Range: llvm::reverse(C&: Features), P: [](const StringRef F) {
736 return F.contains(Other: "crypto");
737 });
738 const auto ItSHA2 =
739 llvm::find_if(Range: llvm::reverse(C&: Features), P: [](const StringRef F) {
740 return F.contains(Other: "crypto") || F.contains(Other: "sha2");
741 });
742 const auto ItAES =
743 llvm::find_if(Range: llvm::reverse(C&: Features), P: [](const StringRef F) {
744 return F.contains(Other: "crypto") || F.contains(Other: "aes");
745 });
746 const bool FoundSHA2 = ItSHA2 != Features.rend();
747 const bool FoundAES = ItAES != Features.rend();
748 if (FoundSHA2)
749 HasSHA2 = ItSHA2->take_front() == "+";
750 if (FoundAES)
751 HasAES = ItAES->take_front() == "+";
752 if (ItCrypto != Features.rend()) {
753 if (HasSHA2 && HasAES)
754 Features.push_back(x: "+crypto");
755 else
756 Features.push_back(x: "-crypto");
757 if (HasSHA2)
758 Features.push_back(x: "+sha2");
759 else
760 Features.push_back(x: "-sha2");
761 if (HasAES)
762 Features.push_back(x: "+aes");
763 else
764 Features.push_back(x: "-aes");
765 }
766
767 if (HasSHA2 || HasAES) {
768 StringRef ArchSuffix = arm::getLLVMArchSuffixForARM(
769 CPU: arm::getARMTargetCPU(CPU: CPUName, Arch: ArchName, Triple), Arch: ArchName, Triple);
770 llvm::ARM::ProfileKind ArchProfile =
771 llvm::ARM::parseArchProfile(Arch: ArchSuffix);
772 if (!((llvm::ARM::parseArchVersion(Arch: ArchSuffix) >= 8) &&
773 (ArchProfile == llvm::ARM::ProfileKind::A ||
774 ArchProfile == llvm::ARM::ProfileKind::R))) {
775 if (HasSHA2)
776 D.Diag(DiagID: clang::diag::warn_target_unsupported_extension)
777 << "sha2"
778 << llvm::ARM::getArchName(AK: llvm::ARM::parseArch(Arch: ArchSuffix));
779 if (HasAES)
780 D.Diag(DiagID: clang::diag::warn_target_unsupported_extension)
781 << "aes"
782 << llvm::ARM::getArchName(AK: llvm::ARM::parseArch(Arch: ArchSuffix));
783 // With -fno-integrated-as -mfpu=crypto-neon-fp-armv8 some assemblers such
784 // as the GNU assembler will permit the use of crypto instructions as the
785 // fpu will override the architecture. We keep the crypto feature in this
786 // case to preserve compatibility. In all other cases we remove the crypto
787 // feature.
788 if (!Args.hasArg(Ids: options::OPT_fno_integrated_as)) {
789 Features.push_back(x: "-sha2");
790 Features.push_back(x: "-aes");
791 }
792 }
793 }
794
795 // Propagate frame-chain model selection
796 if (Arg *A = Args.getLastArg(Ids: options::OPT_mframe_chain)) {
797 StringRef FrameChainOption = A->getValue();
798 if (FrameChainOption.starts_with(Prefix: "aapcs"))
799 Features.push_back(x: "+aapcs-frame-chain");
800 }
801
802 // CMSE: Check for target 8M (for -mcmse to be applicable) is performed later.
803 if (Args.getLastArg(Ids: options::OPT_mcmse))
804 Features.push_back(x: "+8msecext");
805
806 if (Arg *A = Args.getLastArg(Ids: options::OPT_mfix_cmse_cve_2021_35465,
807 Ids: options::OPT_mno_fix_cmse_cve_2021_35465)) {
808 if (!Args.getLastArg(Ids: options::OPT_mcmse))
809 D.Diag(DiagID: diag::err_opt_not_valid_without_opt)
810 << A->getOption().getName() << "-mcmse";
811
812 if (A->getOption().matches(ID: options::OPT_mfix_cmse_cve_2021_35465))
813 Features.push_back(x: "+fix-cmse-cve-2021-35465");
814 else
815 Features.push_back(x: "-fix-cmse-cve-2021-35465");
816 }
817
818 // This also handles the -m(no-)fix-cortex-a72-1655431 arguments via aliases.
819 if (Arg *A = Args.getLastArg(Ids: options::OPT_mfix_cortex_a57_aes_1742098,
820 Ids: options::OPT_mno_fix_cortex_a57_aes_1742098)) {
821 if (A->getOption().matches(ID: options::OPT_mfix_cortex_a57_aes_1742098)) {
822 Features.push_back(x: "+fix-cortex-a57-aes-1742098");
823 } else {
824 Features.push_back(x: "-fix-cortex-a57-aes-1742098");
825 }
826 }
827
828 // Look for the last occurrence of -mlong-calls or -mno-long-calls. If
829 // neither options are specified, see if we are compiling for kernel/kext and
830 // decide whether to pass "+long-calls" based on the OS and its version.
831 if (Arg *A = Args.getLastArg(Ids: options::OPT_mlong_calls,
832 Ids: options::OPT_mno_long_calls)) {
833 if (A->getOption().matches(ID: options::OPT_mlong_calls))
834 Features.push_back(x: "+long-calls");
835 } else if (KernelOrKext && (!Triple.isiOS() || Triple.isOSVersionLT(Major: 6)) &&
836 !Triple.isWatchOS() && !Triple.isXROS()) {
837 Features.push_back(x: "+long-calls");
838 }
839
840 // Generate execute-only output (no data access to code sections).
841 // This only makes sense for the compiler, not for the assembler.
842 // It's not needed for multilib selection and may hide an unused
843 // argument diagnostic if the code is always run.
844 if (!ForAS && !ForMultilib) {
845 // Supported only on ARMv6T2 and ARMv7 and above.
846 // Cannot be combined with -mno-movt.
847 if (Arg *A = Args.getLastArg(Ids: options::OPT_mexecute_only, Ids: options::OPT_mno_execute_only)) {
848 if (A->getOption().matches(ID: options::OPT_mexecute_only)) {
849 if (getARMSubArchVersionNumber(Triple) < 7 &&
850 llvm::ARM::parseArch(Arch: Triple.getArchName()) != llvm::ARM::ArchKind::ARMV6T2 &&
851 llvm::ARM::parseArch(Arch: Triple.getArchName()) != llvm::ARM::ArchKind::ARMV6M)
852 D.Diag(DiagID: diag::err_target_unsupported_execute_only) << Triple.getArchName();
853 else if (llvm::ARM::parseArch(Arch: Triple.getArchName()) == llvm::ARM::ArchKind::ARMV6M) {
854 if (Arg *PIArg = Args.getLastArg(Ids: options::OPT_fropi, Ids: options::OPT_frwpi,
855 Ids: options::OPT_fpic, Ids: options::OPT_fpie,
856 Ids: options::OPT_fPIC, Ids: options::OPT_fPIE))
857 D.Diag(DiagID: diag::err_opt_not_valid_with_opt_on_target)
858 << A->getAsString(Args) << PIArg->getAsString(Args) << Triple.getArchName();
859 } else if (Arg *B = Args.getLastArg(Ids: options::OPT_mno_movt))
860 D.Diag(DiagID: diag::err_opt_not_valid_with_opt)
861 << A->getAsString(Args) << B->getAsString(Args);
862 Features.push_back(x: "+execute-only");
863 }
864 }
865 }
866
867 if (Arg *A = Args.getLastArg(Ids: options::OPT_mno_unaligned_access,
868 Ids: options::OPT_munaligned_access,
869 Ids: options::OPT_mstrict_align,
870 Ids: options::OPT_mno_strict_align)) {
871 // Kernel code has more strict alignment requirements.
872 if (KernelOrKext ||
873 A->getOption().matches(ID: options::OPT_mno_unaligned_access) ||
874 A->getOption().matches(ID: options::OPT_mstrict_align)) {
875 Features.push_back(x: "+strict-align");
876 } else {
877 // No v6M core supports unaligned memory access (v6M ARM ARM A3.2).
878 if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
879 D.Diag(DiagID: diag::err_target_unsupported_unaligned) << "v6m";
880 // v8M Baseline follows on from v6M, so doesn't support unaligned memory
881 // access either.
882 else if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v8m_baseline)
883 D.Diag(DiagID: diag::err_target_unsupported_unaligned) << "v8m.base";
884 }
885 } else {
886 // Assume pre-ARMv6 doesn't support unaligned accesses.
887 //
888 // ARMv6 may or may not support unaligned accesses depending on the
889 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
890 // Darwin and NetBSD targets support unaligned accesses, and others don't.
891 //
892 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit which
893 // raises an alignment fault on unaligned accesses. Assume ARMv7+ supports
894 // unaligned accesses, except ARMv6-M, and ARMv8-M without the Main
895 // Extension. This aligns with the default behavior of ARM's downstream
896 // versions of GCC and Clang.
897 //
898 // Users can change the default behavior via -m[no-]unaliged-access.
899 int VersionNum = getARMSubArchVersionNumber(Triple);
900 if (Triple.isOSDarwin() || Triple.isOSNetBSD()) {
901 if (VersionNum < 6 ||
902 Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
903 Features.push_back(x: "+strict-align");
904 } else if (VersionNum < 7 ||
905 Triple.getSubArch() ==
906 llvm::Triple::SubArchType::ARMSubArch_v6m ||
907 Triple.getSubArch() ==
908 llvm::Triple::SubArchType::ARMSubArch_v8m_baseline) {
909 Features.push_back(x: "+strict-align");
910 }
911 }
912
913 // llvm does not support reserving registers in general. There is support
914 // for reserving r9 on ARM though (defined as a platform-specific register
915 // in ARM EABI).
916 if (Args.hasArg(Ids: options::OPT_ffixed_r9))
917 Features.push_back(x: "+reserve-r9");
918
919 // The kext linker doesn't know how to deal with movw/movt.
920 if (KernelOrKext || Args.hasArg(Ids: options::OPT_mno_movt))
921 Features.push_back(x: "+no-movt");
922
923 if (Args.hasArg(Ids: options::OPT_mno_neg_immediates))
924 Features.push_back(x: "+no-neg-immediates");
925
926 // Enable/disable straight line speculation hardening.
927 if (Arg *A = Args.getLastArg(Ids: options::OPT_mharden_sls_EQ)) {
928 StringRef Scope = A->getValue();
929 bool EnableRetBr = false;
930 bool EnableBlr = false;
931 bool DisableComdat = false;
932 if (Scope != "none") {
933 SmallVector<StringRef, 4> Opts;
934 Scope.split(A&: Opts, Separator: ",");
935 for (auto Opt : Opts) {
936 Opt = Opt.trim();
937 if (Opt == "all") {
938 EnableBlr = true;
939 EnableRetBr = true;
940 continue;
941 }
942 if (Opt == "retbr") {
943 EnableRetBr = true;
944 continue;
945 }
946 if (Opt == "blr") {
947 EnableBlr = true;
948 continue;
949 }
950 if (Opt == "comdat") {
951 DisableComdat = false;
952 continue;
953 }
954 if (Opt == "nocomdat") {
955 DisableComdat = true;
956 continue;
957 }
958 D.Diag(DiagID: diag::err_drv_unsupported_option_argument)
959 << A->getSpelling() << Scope;
960 break;
961 }
962 }
963
964 if (EnableRetBr || EnableBlr)
965 if (!(isARMAProfile(Triple) && getARMSubArchVersionNumber(Triple) >= 7))
966 D.Diag(DiagID: diag::err_sls_hardening_arm_not_supported)
967 << Scope << A->getAsString(Args);
968
969 if (EnableRetBr)
970 Features.push_back(x: "+harden-sls-retbr");
971 if (EnableBlr)
972 Features.push_back(x: "+harden-sls-blr");
973 if (DisableComdat) {
974 Features.push_back(x: "+harden-sls-nocomdat");
975 }
976 }
977
978 if (Args.getLastArg(Ids: options::OPT_mno_bti_at_return_twice))
979 Features.push_back(x: "+no-bti-at-return-twice");
980
981 checkARMFloatABI(D, Args, HasFPRegs);
982
983 return FPUKind;
984}
985
986std::string arm::getARMArch(StringRef Arch, const llvm::Triple &Triple) {
987 std::string MArch;
988 if (!Arch.empty())
989 MArch = std::string(Arch);
990 else
991 MArch = std::string(Triple.getArchName());
992 MArch = StringRef(MArch).split(Separator: "+").first.lower();
993
994 // Handle -march=native.
995 if (MArch == "native") {
996 std::string CPU = std::string(llvm::sys::getHostCPUName());
997 if (CPU != "generic") {
998 // Translate the native cpu into the architecture suffix for that CPU.
999 StringRef Suffix = arm::getLLVMArchSuffixForARM(CPU, Arch: MArch, Triple);
1000 // If there is no valid architecture suffix for this CPU we don't know how
1001 // to handle it, so return no architecture.
1002 if (Suffix.empty())
1003 MArch = "";
1004 else
1005 MArch = std::string("arm") + Suffix.str();
1006 }
1007 }
1008
1009 return MArch;
1010}
1011
1012/// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
1013StringRef arm::getARMCPUForMArch(StringRef Arch, const llvm::Triple &Triple) {
1014 std::string MArch = getARMArch(Arch, Triple);
1015 // getARMCPUForArch defaults to the triple if MArch is empty, but empty MArch
1016 // here means an -march=native that we can't handle, so instead return no CPU.
1017 if (MArch.empty())
1018 return StringRef();
1019
1020 // We need to return an empty string here on invalid MArch values as the
1021 // various places that call this function can't cope with a null result.
1022 return llvm::ARM::getARMCPUForArch(Triple, MArch);
1023}
1024
1025/// getARMTargetCPU - Get the (LLVM) name of the ARM cpu we are targeting.
1026std::string arm::getARMTargetCPU(StringRef CPU, StringRef Arch,
1027 const llvm::Triple &Triple) {
1028 // FIXME: Warn on inconsistent use of -mcpu and -march.
1029 // If we have -mcpu=, use that.
1030 if (!CPU.empty()) {
1031 std::string MCPU = StringRef(CPU).split(Separator: "+").first.lower();
1032 // Handle -mcpu=native.
1033 if (MCPU == "native")
1034 return std::string(llvm::sys::getHostCPUName());
1035 else
1036 return MCPU;
1037 }
1038
1039 return std::string(getARMCPUForMArch(Arch, Triple));
1040}
1041
1042/// getLLVMArchSuffixForARM - Get the LLVM ArchKind value to use for a
1043/// particular CPU (or Arch, if CPU is generic). This is needed to
1044/// pass to functions like llvm::ARM::getDefaultFPU which need an
1045/// ArchKind as well as a CPU name.
1046llvm::ARM::ArchKind arm::getLLVMArchKindForARM(StringRef CPU, StringRef Arch,
1047 const llvm::Triple &Triple) {
1048 llvm::ARM::ArchKind ArchKind;
1049 if (CPU == "generic" || CPU.empty()) {
1050 std::string ARMArch = tools::arm::getARMArch(Arch, Triple);
1051 ArchKind = llvm::ARM::parseArch(Arch: ARMArch);
1052 if (ArchKind == llvm::ARM::ArchKind::INVALID)
1053 // In case of generic Arch, i.e. "arm",
1054 // extract arch from default cpu of the Triple
1055 ArchKind =
1056 llvm::ARM::parseCPUArch(CPU: llvm::ARM::getARMCPUForArch(Triple, MArch: ARMArch));
1057 } else {
1058 // FIXME: horrible hack to get around the fact that Cortex-A7 is only an
1059 // armv7k triple if it's actually been specified via "-arch armv7k".
1060 ArchKind = (Arch == "armv7k" || Arch == "thumbv7k")
1061 ? llvm::ARM::ArchKind::ARMV7K
1062 : llvm::ARM::parseCPUArch(CPU);
1063 }
1064 return ArchKind;
1065}
1066
1067/// getLLVMArchSuffixForARM - Get the LLVM arch name to use for a particular
1068/// CPU (or Arch, if CPU is generic).
1069// FIXME: This is redundant with -mcpu, why does LLVM use this.
1070StringRef arm::getLLVMArchSuffixForARM(StringRef CPU, StringRef Arch,
1071 const llvm::Triple &Triple) {
1072 llvm::ARM::ArchKind ArchKind = getLLVMArchKindForARM(CPU, Arch, Triple);
1073 if (ArchKind == llvm::ARM::ArchKind::INVALID)
1074 return "";
1075 return llvm::ARM::getSubArch(AK: ArchKind);
1076}
1077
1078void arm::appendBE8LinkFlag(const ArgList &Args, ArgStringList &CmdArgs,
1079 const llvm::Triple &Triple) {
1080 if (Args.hasArg(Ids: options::OPT_r))
1081 return;
1082
1083 // ARMv7 (and later) and ARMv6-M do not support BE-32, so instruct the linker
1084 // to generate BE-8 executables.
1085 if (arm::getARMSubArchVersionNumber(Triple) >= 7 || arm::isARMMProfile(Triple))
1086 CmdArgs.push_back(Elt: "--be8");
1087}
1088