1//===-- Hexagon.cpp -------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "InputFiles.h"
10#include "Symbols.h"
11#include "SyntheticSections.h"
12#include "Target.h"
13#include "lld/Common/ErrorHandler.h"
14#include "llvm/BinaryFormat/ELF.h"
15#include "llvm/Support/Endian.h"
16
17using namespace llvm;
18using namespace llvm::object;
19using namespace llvm::support::endian;
20using namespace llvm::ELF;
21using namespace lld;
22using namespace lld::elf;
23
24namespace {
25class Hexagon final : public TargetInfo {
26public:
27 Hexagon();
28 uint32_t calcEFlags() const override;
29 RelExpr getRelExpr(RelType type, const Symbol &s,
30 const uint8_t *loc) const override;
31 RelType getDynRel(RelType type) const override;
32 int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
33 void relocate(uint8_t *loc, const Relocation &rel,
34 uint64_t val) const override;
35 void writePltHeader(uint8_t *buf) const override;
36 void writePlt(uint8_t *buf, const Symbol &sym,
37 uint64_t pltEntryAddr) const override;
38};
39} // namespace
40
41Hexagon::Hexagon() {
42 pltRel = R_HEX_JMP_SLOT;
43 relativeRel = R_HEX_RELATIVE;
44 gotRel = R_HEX_GLOB_DAT;
45 symbolicRel = R_HEX_32;
46
47 gotBaseSymInGotPlt = true;
48 // The zero'th GOT entry is reserved for the address of _DYNAMIC. The
49 // next 3 are reserved for the dynamic loader.
50 gotPltHeaderEntriesNum = 4;
51
52 pltEntrySize = 16;
53 pltHeaderSize = 32;
54
55 // Hexagon Linux uses 64K pages by default.
56 defaultMaxPageSize = 0x10000;
57 tlsGotRel = R_HEX_TPREL_32;
58 tlsModuleIndexRel = R_HEX_DTPMOD_32;
59 tlsOffsetRel = R_HEX_DTPREL_32;
60}
61
62uint32_t Hexagon::calcEFlags() const {
63 // The architecture revision must always be equal to or greater than
64 // greatest revision in the list of inputs.
65 std::optional<uint32_t> ret;
66 for (InputFile *f : ctx.objectFiles) {
67 uint32_t eflags = cast<ObjFile<ELF32LE>>(Val: f)->getObj().getHeader().e_flags;
68 if (!ret || eflags > *ret)
69 ret = eflags;
70 }
71 return ret.value_or(/* Default Arch Rev: */ u: 0x60);
72}
73
74static uint32_t applyMask(uint32_t mask, uint32_t data) {
75 uint32_t result = 0;
76 size_t off = 0;
77
78 for (size_t bit = 0; bit != 32; ++bit) {
79 uint32_t valBit = (data >> off) & 1;
80 uint32_t maskBit = (mask >> bit) & 1;
81 if (maskBit) {
82 result |= (valBit << bit);
83 ++off;
84 }
85 }
86 return result;
87}
88
89RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s,
90 const uint8_t *loc) const {
91 switch (type) {
92 case R_HEX_NONE:
93 return R_NONE;
94 case R_HEX_6_X:
95 case R_HEX_8_X:
96 case R_HEX_9_X:
97 case R_HEX_10_X:
98 case R_HEX_11_X:
99 case R_HEX_12_X:
100 case R_HEX_16_X:
101 case R_HEX_32:
102 case R_HEX_32_6_X:
103 case R_HEX_HI16:
104 case R_HEX_LO16:
105 case R_HEX_DTPREL_32:
106 return R_ABS;
107 case R_HEX_B9_PCREL:
108 case R_HEX_B13_PCREL:
109 case R_HEX_B15_PCREL:
110 case R_HEX_6_PCREL_X:
111 case R_HEX_32_PCREL:
112 return R_PC;
113 case R_HEX_B9_PCREL_X:
114 case R_HEX_B15_PCREL_X:
115 case R_HEX_B22_PCREL:
116 case R_HEX_PLT_B22_PCREL:
117 case R_HEX_B22_PCREL_X:
118 case R_HEX_B32_PCREL_X:
119 case R_HEX_GD_PLT_B22_PCREL:
120 case R_HEX_GD_PLT_B22_PCREL_X:
121 case R_HEX_GD_PLT_B32_PCREL_X:
122 return R_PLT_PC;
123 case R_HEX_IE_32_6_X:
124 case R_HEX_IE_16_X:
125 case R_HEX_IE_HI16:
126 case R_HEX_IE_LO16:
127 return R_GOT;
128 case R_HEX_GD_GOT_11_X:
129 case R_HEX_GD_GOT_16_X:
130 case R_HEX_GD_GOT_32_6_X:
131 return R_TLSGD_GOTPLT;
132 case R_HEX_GOTREL_11_X:
133 case R_HEX_GOTREL_16_X:
134 case R_HEX_GOTREL_32_6_X:
135 case R_HEX_GOTREL_HI16:
136 case R_HEX_GOTREL_LO16:
137 return R_GOTPLTREL;
138 case R_HEX_GOT_11_X:
139 case R_HEX_GOT_16_X:
140 case R_HEX_GOT_32_6_X:
141 return R_GOTPLT;
142 case R_HEX_IE_GOT_11_X:
143 case R_HEX_IE_GOT_16_X:
144 case R_HEX_IE_GOT_32_6_X:
145 case R_HEX_IE_GOT_HI16:
146 case R_HEX_IE_GOT_LO16:
147 return R_GOTPLT;
148 case R_HEX_TPREL_11_X:
149 case R_HEX_TPREL_16:
150 case R_HEX_TPREL_16_X:
151 case R_HEX_TPREL_32_6_X:
152 case R_HEX_TPREL_HI16:
153 case R_HEX_TPREL_LO16:
154 return R_TPREL;
155 default:
156 error(msg: getErrorLocation(loc) + "unknown relocation (" + Twine(type) +
157 ") against symbol " + toString(s));
158 return R_NONE;
159 }
160}
161
162// There are (arguably too) many relocation masks for the DSP's
163// R_HEX_6_X type. The table below is used to select the correct mask
164// for the given instruction.
165struct InstructionMask {
166 uint32_t cmpMask;
167 uint32_t relocMask;
168};
169static const InstructionMask r6[] = {
170 {.cmpMask: 0x38000000, .relocMask: 0x0000201f}, {.cmpMask: 0x39000000, .relocMask: 0x0000201f},
171 {.cmpMask: 0x3e000000, .relocMask: 0x00001f80}, {.cmpMask: 0x3f000000, .relocMask: 0x00001f80},
172 {.cmpMask: 0x40000000, .relocMask: 0x000020f8}, {.cmpMask: 0x41000000, .relocMask: 0x000007e0},
173 {.cmpMask: 0x42000000, .relocMask: 0x000020f8}, {.cmpMask: 0x43000000, .relocMask: 0x000007e0},
174 {.cmpMask: 0x44000000, .relocMask: 0x000020f8}, {.cmpMask: 0x45000000, .relocMask: 0x000007e0},
175 {.cmpMask: 0x46000000, .relocMask: 0x000020f8}, {.cmpMask: 0x47000000, .relocMask: 0x000007e0},
176 {.cmpMask: 0x6a000000, .relocMask: 0x00001f80}, {.cmpMask: 0x7c000000, .relocMask: 0x001f2000},
177 {.cmpMask: 0x9a000000, .relocMask: 0x00000f60}, {.cmpMask: 0x9b000000, .relocMask: 0x00000f60},
178 {.cmpMask: 0x9c000000, .relocMask: 0x00000f60}, {.cmpMask: 0x9d000000, .relocMask: 0x00000f60},
179 {.cmpMask: 0x9f000000, .relocMask: 0x001f0100}, {.cmpMask: 0xab000000, .relocMask: 0x0000003f},
180 {.cmpMask: 0xad000000, .relocMask: 0x0000003f}, {.cmpMask: 0xaf000000, .relocMask: 0x00030078},
181 {.cmpMask: 0xd7000000, .relocMask: 0x006020e0}, {.cmpMask: 0xd8000000, .relocMask: 0x006020e0},
182 {.cmpMask: 0xdb000000, .relocMask: 0x006020e0}, {.cmpMask: 0xdf000000, .relocMask: 0x006020e0}};
183
184static bool isDuplex(uint32_t insn) {
185 // Duplex forms have a fixed mask and parse bits 15:14 are always
186 // zero. Non-duplex insns will always have at least one bit set in the
187 // parse field.
188 return (0xC000 & insn) == 0;
189}
190
191static uint32_t findMaskR6(uint32_t insn) {
192 if (isDuplex(insn))
193 return 0x03f00000;
194
195 for (InstructionMask i : r6)
196 if ((0xff000000 & insn) == i.cmpMask)
197 return i.relocMask;
198
199 error(msg: "unrecognized instruction for 6_X relocation: 0x" +
200 utohexstr(X: insn));
201 return 0;
202}
203
204static uint32_t findMaskR8(uint32_t insn) {
205 if ((0xff000000 & insn) == 0xde000000)
206 return 0x00e020e8;
207 if ((0xff000000 & insn) == 0x3c000000)
208 return 0x0000207f;
209 return 0x00001fe0;
210}
211
212static uint32_t findMaskR11(uint32_t insn) {
213 if ((0xff000000 & insn) == 0xa1000000)
214 return 0x060020ff;
215 return 0x06003fe0;
216}
217
218static uint32_t findMaskR16(uint32_t insn) {
219 if ((0xff000000 & insn) == 0x48000000)
220 return 0x061f20ff;
221 if ((0xff000000 & insn) == 0x49000000)
222 return 0x061f3fe0;
223 if ((0xff000000 & insn) == 0x78000000)
224 return 0x00df3fe0;
225 if ((0xff000000 & insn) == 0xb0000000)
226 return 0x0fe03fe0;
227
228 if (isDuplex(insn))
229 return 0x03f00000;
230
231 for (InstructionMask i : r6)
232 if ((0xff000000 & insn) == i.cmpMask)
233 return i.relocMask;
234
235 error(msg: "unrecognized instruction for 16_X type: 0x" +
236 utohexstr(X: insn));
237 return 0;
238}
239
240static void or32le(uint8_t *p, int32_t v) { write32le(P: p, V: read32le(P: p) | v); }
241
242void Hexagon::relocate(uint8_t *loc, const Relocation &rel,
243 uint64_t val) const {
244 switch (rel.type) {
245 case R_HEX_NONE:
246 break;
247 case R_HEX_6_PCREL_X:
248 case R_HEX_6_X:
249 or32le(p: loc, v: applyMask(mask: findMaskR6(insn: read32le(P: loc)), data: val));
250 break;
251 case R_HEX_8_X:
252 or32le(p: loc, v: applyMask(mask: findMaskR8(insn: read32le(P: loc)), data: val));
253 break;
254 case R_HEX_9_X:
255 or32le(p: loc, v: applyMask(mask: 0x00003fe0, data: val & 0x3f));
256 break;
257 case R_HEX_10_X:
258 or32le(p: loc, v: applyMask(mask: 0x00203fe0, data: val & 0x3f));
259 break;
260 case R_HEX_11_X:
261 case R_HEX_GD_GOT_11_X:
262 case R_HEX_IE_GOT_11_X:
263 case R_HEX_GOT_11_X:
264 case R_HEX_GOTREL_11_X:
265 case R_HEX_TPREL_11_X:
266 or32le(p: loc, v: applyMask(mask: findMaskR11(insn: read32le(P: loc)), data: val & 0x3f));
267 break;
268 case R_HEX_12_X:
269 or32le(p: loc, v: applyMask(mask: 0x000007e0, data: val));
270 break;
271 case R_HEX_16_X: // These relocs only have 6 effective bits.
272 case R_HEX_IE_16_X:
273 case R_HEX_IE_GOT_16_X:
274 case R_HEX_GD_GOT_16_X:
275 case R_HEX_GOT_16_X:
276 case R_HEX_GOTREL_16_X:
277 case R_HEX_TPREL_16_X:
278 or32le(p: loc, v: applyMask(mask: findMaskR16(insn: read32le(P: loc)), data: val & 0x3f));
279 break;
280 case R_HEX_TPREL_16:
281 or32le(p: loc, v: applyMask(mask: findMaskR16(insn: read32le(P: loc)), data: val & 0xffff));
282 break;
283 case R_HEX_32:
284 case R_HEX_32_PCREL:
285 case R_HEX_DTPREL_32:
286 or32le(p: loc, v: val);
287 break;
288 case R_HEX_32_6_X:
289 case R_HEX_GD_GOT_32_6_X:
290 case R_HEX_GOT_32_6_X:
291 case R_HEX_GOTREL_32_6_X:
292 case R_HEX_IE_GOT_32_6_X:
293 case R_HEX_IE_32_6_X:
294 case R_HEX_TPREL_32_6_X:
295 or32le(p: loc, v: applyMask(mask: 0x0fff3fff, data: val >> 6));
296 break;
297 case R_HEX_B9_PCREL:
298 checkInt(loc, v: val, n: 11, rel);
299 or32le(p: loc, v: applyMask(mask: 0x003000fe, data: val >> 2));
300 break;
301 case R_HEX_B9_PCREL_X:
302 or32le(p: loc, v: applyMask(mask: 0x003000fe, data: val & 0x3f));
303 break;
304 case R_HEX_B13_PCREL:
305 checkInt(loc, v: val, n: 15, rel);
306 or32le(p: loc, v: applyMask(mask: 0x00202ffe, data: val >> 2));
307 break;
308 case R_HEX_B15_PCREL:
309 checkInt(loc, v: val, n: 17, rel);
310 or32le(p: loc, v: applyMask(mask: 0x00df20fe, data: val >> 2));
311 break;
312 case R_HEX_B15_PCREL_X:
313 or32le(p: loc, v: applyMask(mask: 0x00df20fe, data: val & 0x3f));
314 break;
315 case R_HEX_B22_PCREL:
316 case R_HEX_GD_PLT_B22_PCREL:
317 case R_HEX_PLT_B22_PCREL:
318 checkInt(loc, v: val, n: 22, rel);
319 or32le(p: loc, v: applyMask(mask: 0x1ff3ffe, data: val >> 2));
320 break;
321 case R_HEX_B22_PCREL_X:
322 case R_HEX_GD_PLT_B22_PCREL_X:
323 or32le(p: loc, v: applyMask(mask: 0x1ff3ffe, data: val & 0x3f));
324 break;
325 case R_HEX_B32_PCREL_X:
326 case R_HEX_GD_PLT_B32_PCREL_X:
327 or32le(p: loc, v: applyMask(mask: 0x0fff3fff, data: val >> 6));
328 break;
329 case R_HEX_GOTREL_HI16:
330 case R_HEX_HI16:
331 case R_HEX_IE_GOT_HI16:
332 case R_HEX_IE_HI16:
333 case R_HEX_TPREL_HI16:
334 or32le(p: loc, v: applyMask(mask: 0x00c03fff, data: val >> 16));
335 break;
336 case R_HEX_GOTREL_LO16:
337 case R_HEX_LO16:
338 case R_HEX_IE_GOT_LO16:
339 case R_HEX_IE_LO16:
340 case R_HEX_TPREL_LO16:
341 or32le(p: loc, v: applyMask(mask: 0x00c03fff, data: val));
342 break;
343 default:
344 llvm_unreachable("unknown relocation");
345 }
346}
347
348void Hexagon::writePltHeader(uint8_t *buf) const {
349 const uint8_t pltData[] = {
350 0x00, 0x40, 0x00, 0x00, // { immext (#0)
351 0x1c, 0xc0, 0x49, 0x6a, // r28 = add (pc, ##GOT0@PCREL) } # @GOT0
352 0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16) # offset of GOTn
353 0x4f, 0x40, 0x9c, 0x91, // r15 = memw (r28 + #8) # object ID at GOT2
354 0x3c, 0xc0, 0x9c, 0x91, // r28 = memw (r28 + #4) }# dynamic link at GOT1
355 0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2) # index of PLTn
356 0x00, 0xc0, 0x9c, 0x52, // jumpr r28 } # call dynamic linker
357 0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment
358 };
359 memcpy(dest: buf, src: pltData, n: sizeof(pltData));
360
361 // Offset from PLT0 to the GOT.
362 uint64_t off = in.gotPlt->getVA() - in.plt->getVA();
363 relocateNoSym(loc: buf, type: R_HEX_B32_PCREL_X, val: off);
364 relocateNoSym(loc: buf + 4, type: R_HEX_6_PCREL_X, val: off);
365}
366
367void Hexagon::writePlt(uint8_t *buf, const Symbol &sym,
368 uint64_t pltEntryAddr) const {
369 const uint8_t inst[] = {
370 0x00, 0x40, 0x00, 0x00, // { immext (#0)
371 0x0e, 0xc0, 0x49, 0x6a, // r14 = add (pc, ##GOTn@PCREL) }
372 0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14)
373 0x00, 0xc0, 0x9c, 0x52, // jumpr r28
374 };
375 memcpy(dest: buf, src: inst, n: sizeof(inst));
376
377 uint64_t gotPltEntryAddr = sym.getGotPltVA();
378 relocateNoSym(loc: buf, type: R_HEX_B32_PCREL_X, val: gotPltEntryAddr - pltEntryAddr);
379 relocateNoSym(loc: buf + 4, type: R_HEX_6_PCREL_X, val: gotPltEntryAddr - pltEntryAddr);
380}
381
382RelType Hexagon::getDynRel(RelType type) const {
383 if (type == R_HEX_32)
384 return type;
385 return R_HEX_NONE;
386}
387
388int64_t Hexagon::getImplicitAddend(const uint8_t *buf, RelType type) const {
389 switch (type) {
390 case R_HEX_NONE:
391 case R_HEX_GLOB_DAT:
392 case R_HEX_JMP_SLOT:
393 return 0;
394 case R_HEX_32:
395 case R_HEX_RELATIVE:
396 case R_HEX_DTPMOD_32:
397 case R_HEX_DTPREL_32:
398 case R_HEX_TPREL_32:
399 return SignExtend64<32>(x: read32(p: buf));
400 default:
401 internalLinkerError(loc: getErrorLocation(loc: buf),
402 msg: "cannot read addend for relocation " + toString(type));
403 return 0;
404 }
405}
406
407TargetInfo *elf::getHexagonTargetInfo() {
408 static Hexagon target;
409 return &target;
410}
411