1//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the MachineIRBuilder class.
10/// This is a helper class to build MachineInstr.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14#define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15
16#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
17#include "llvm/CodeGen/MachineBasicBlock.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/TargetLowering.h"
21#include "llvm/CodeGen/TargetOpcodes.h"
22#include "llvm/IR/DebugLoc.h"
23#include "llvm/IR/Module.h"
24
25namespace llvm {
26
27// Forward declarations.
28class APInt;
29class BlockAddress;
30class Constant;
31class ConstantFP;
32class ConstantInt;
33class DataLayout;
34class GISelCSEInfo;
35class GlobalValue;
36class TargetRegisterClass;
37class MachineFunction;
38class MachineInstr;
39class TargetInstrInfo;
40class GISelChangeObserver;
41
42/// Class which stores all the state required in a MachineIRBuilder.
43/// Since MachineIRBuilders will only store state in this object, it allows
44/// to transfer BuilderState between different kinds of MachineIRBuilders.
45struct MachineIRBuilderState {
46 /// MachineFunction under construction.
47 MachineFunction *MF = nullptr;
48 /// Information used to access the description of the opcodes.
49 const TargetInstrInfo *TII = nullptr;
50 /// Information used to verify types are consistent and to create virtual registers.
51 MachineRegisterInfo *MRI = nullptr;
52 /// Debug location to be set to any instruction we create.
53 DebugLoc DL;
54 /// PC sections metadata to be set to any instruction we create.
55 MDNode *PCSections = nullptr;
56 /// MMRA Metadata to be set on any instruction we create.
57 MDNode *MMRA = nullptr;
58
59 /// \name Fields describing the insertion point.
60 /// @{
61 MachineBasicBlock *MBB = nullptr;
62 MachineBasicBlock::iterator II;
63 /// @}
64
65 GISelChangeObserver *Observer = nullptr;
66
67 GISelCSEInfo *CSEInfo = nullptr;
68};
69
70class DstOp {
71 union {
72 LLT LLTTy;
73 Register Reg;
74 const TargetRegisterClass *RC;
75 };
76
77public:
78 enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
79 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
80 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
81 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
82 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
83 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
84
85 void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const {
86 switch (Ty) {
87 case DstType::Ty_Reg:
88 MIB.addDef(RegNo: Reg);
89 break;
90 case DstType::Ty_LLT:
91 MIB.addDef(RegNo: MRI.createGenericVirtualRegister(Ty: LLTTy));
92 break;
93 case DstType::Ty_RC:
94 MIB.addDef(RegNo: MRI.createVirtualRegister(RegClass: RC));
95 break;
96 }
97 }
98
99 LLT getLLTTy(const MachineRegisterInfo &MRI) const {
100 switch (Ty) {
101 case DstType::Ty_RC:
102 return LLT{};
103 case DstType::Ty_LLT:
104 return LLTTy;
105 case DstType::Ty_Reg:
106 return MRI.getType(Reg: Reg);
107 }
108 llvm_unreachable("Unrecognised DstOp::DstType enum");
109 }
110
111 Register getReg() const {
112 assert(Ty == DstType::Ty_Reg && "Not a register");
113 return Reg;
114 }
115
116 const TargetRegisterClass *getRegClass() const {
117 switch (Ty) {
118 case DstType::Ty_RC:
119 return RC;
120 default:
121 llvm_unreachable("Not a RC Operand");
122 }
123 }
124
125 DstType getDstOpKind() const { return Ty; }
126
127private:
128 DstType Ty;
129};
130
131class SrcOp {
132 union {
133 MachineInstrBuilder SrcMIB;
134 Register Reg;
135 CmpInst::Predicate Pred;
136 int64_t Imm;
137 };
138
139public:
140 enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate, Ty_Imm };
141 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
142 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
143 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
144 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
145 /// Use of registers held in unsigned integer variables (or more rarely signed
146 /// integers) is no longer permitted to avoid ambiguity with upcoming support
147 /// for immediates.
148 SrcOp(unsigned) = delete;
149 SrcOp(int) = delete;
150 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
151 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
152
153 void addSrcToMIB(MachineInstrBuilder &MIB) const {
154 switch (Ty) {
155 case SrcType::Ty_Predicate:
156 MIB.addPredicate(Pred: Pred);
157 break;
158 case SrcType::Ty_Reg:
159 MIB.addUse(RegNo: Reg);
160 break;
161 case SrcType::Ty_MIB:
162 MIB.addUse(RegNo: SrcMIB->getOperand(i: 0).getReg());
163 break;
164 case SrcType::Ty_Imm:
165 MIB.addImm(Val: Imm);
166 break;
167 }
168 }
169
170 LLT getLLTTy(const MachineRegisterInfo &MRI) const {
171 switch (Ty) {
172 case SrcType::Ty_Predicate:
173 case SrcType::Ty_Imm:
174 llvm_unreachable("Not a register operand");
175 case SrcType::Ty_Reg:
176 return MRI.getType(Reg: Reg);
177 case SrcType::Ty_MIB:
178 return MRI.getType(Reg: SrcMIB->getOperand(i: 0).getReg());
179 }
180 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
181 }
182
183 Register getReg() const {
184 switch (Ty) {
185 case SrcType::Ty_Predicate:
186 case SrcType::Ty_Imm:
187 llvm_unreachable("Not a register operand");
188 case SrcType::Ty_Reg:
189 return Reg;
190 case SrcType::Ty_MIB:
191 return SrcMIB->getOperand(i: 0).getReg();
192 }
193 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
194 }
195
196 CmpInst::Predicate getPredicate() const {
197 switch (Ty) {
198 case SrcType::Ty_Predicate:
199 return Pred;
200 default:
201 llvm_unreachable("Not a register operand");
202 }
203 }
204
205 int64_t getImm() const {
206 switch (Ty) {
207 case SrcType::Ty_Imm:
208 return Imm;
209 default:
210 llvm_unreachable("Not an immediate");
211 }
212 }
213
214 SrcType getSrcOpKind() const { return Ty; }
215
216private:
217 SrcType Ty;
218};
219
220/// Helper class to build MachineInstr.
221/// It keeps internally the insertion point and debug location for all
222/// the new instructions we want to create.
223/// This information can be modified via the related setters.
224class MachineIRBuilder {
225
226 MachineIRBuilderState State;
227
228 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;
229
230protected:
231 void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
232
233 void validateUnaryOp(const LLT Res, const LLT Op0);
234 void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
235 void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
236
237 void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,
238 const LLT Op1Ty);
239
240 void recordInsertion(MachineInstr *InsertedInstr) const {
241 if (State.Observer)
242 State.Observer->createdInstr(MI&: *InsertedInstr);
243 }
244
245public:
246 /// Some constructors for easy use.
247 MachineIRBuilder() = default;
248 MachineIRBuilder(MachineFunction &MF) { setMF(MF); }
249
250 MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt) {
251 setMF(*MBB.getParent());
252 setInsertPt(MBB, II: InsPt);
253 }
254
255 MachineIRBuilder(MachineInstr &MI) :
256 MachineIRBuilder(*MI.getParent(), MI.getIterator()) {
257 setInstr(MI);
258 setDebugLoc(MI.getDebugLoc());
259 }
260
261 MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer) :
262 MachineIRBuilder(MI) {
263 setChangeObserver(Observer);
264 }
265
266 virtual ~MachineIRBuilder() = default;
267
268 MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
269
270 const TargetInstrInfo &getTII() {
271 assert(State.TII && "TargetInstrInfo is not set");
272 return *State.TII;
273 }
274
275 /// Getter for the function we currently build.
276 MachineFunction &getMF() {
277 assert(State.MF && "MachineFunction is not set");
278 return *State.MF;
279 }
280
281 const MachineFunction &getMF() const {
282 assert(State.MF && "MachineFunction is not set");
283 return *State.MF;
284 }
285
286 const DataLayout &getDataLayout() const {
287 return getMF().getFunction().getDataLayout();
288 }
289
290 LLVMContext &getContext() const {
291 return getMF().getFunction().getContext();
292 }
293
294 /// Getter for DebugLoc
295 const DebugLoc &getDL() { return State.DL; }
296
297 /// Getter for MRI
298 MachineRegisterInfo *getMRI() { return State.MRI; }
299 const MachineRegisterInfo *getMRI() const { return State.MRI; }
300
301 /// Getter for the State
302 MachineIRBuilderState &getState() { return State; }
303
304 /// Setter for the State
305 void setState(const MachineIRBuilderState &NewState) { State = NewState; }
306
307 /// Getter for the basic block we currently build.
308 const MachineBasicBlock &getMBB() const {
309 assert(State.MBB && "MachineBasicBlock is not set");
310 return *State.MBB;
311 }
312
313 MachineBasicBlock &getMBB() {
314 return const_cast<MachineBasicBlock &>(
315 const_cast<const MachineIRBuilder *>(this)->getMBB());
316 }
317
318 GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
319 const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
320
321 /// Current insertion point for new instructions.
322 MachineBasicBlock::iterator getInsertPt() { return State.II; }
323
324 /// Set the insertion point before the specified position.
325 /// \pre MBB must be in getMF().
326 /// \pre II must be a valid iterator in MBB.
327 void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II) {
328 assert(MBB.getParent() == &getMF() &&
329 "Basic block is in a different function");
330 State.MBB = &MBB;
331 State.II = II;
332 }
333
334 /// @}
335
336 void setCSEInfo(GISelCSEInfo *Info) { State.CSEInfo = Info; }
337
338 /// \name Setters for the insertion point.
339 /// @{
340 /// Set the MachineFunction where to build instructions.
341 void setMF(MachineFunction &MF);
342
343 /// Set the insertion point to the end of \p MBB.
344 /// \pre \p MBB must be contained by getMF().
345 void setMBB(MachineBasicBlock &MBB) {
346 State.MBB = &MBB;
347 State.II = MBB.end();
348 assert(&getMF() == MBB.getParent() &&
349 "Basic block is in a different function");
350 }
351
352 /// Set the insertion point to before MI.
353 /// \pre MI must be in getMF().
354 void setInstr(MachineInstr &MI) {
355 assert(MI.getParent() && "Instruction is not part of a basic block");
356 setMBB(*MI.getParent());
357 State.II = MI.getIterator();
358 setPCSections(MI.getPCSections());
359 setMMRAMetadata(MI.getMMRAMetadata());
360 }
361 /// @}
362
363 /// Set the insertion point to before MI, and set the debug loc to MI's loc.
364 /// \pre MI must be in getMF().
365 void setInstrAndDebugLoc(MachineInstr &MI) {
366 setInstr(MI);
367 setDebugLoc(MI.getDebugLoc());
368 }
369
370 void setChangeObserver(GISelChangeObserver &Observer) {
371 State.Observer = &Observer;
372 }
373
374 GISelChangeObserver *getObserver() { return State.Observer; }
375
376 void stopObservingChanges() { State.Observer = nullptr; }
377
378 bool isObservingChanges() const { return State.Observer != nullptr; }
379 /// @}
380
381 /// Set the debug location to \p DL for all the next build instructions.
382 void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
383
384 /// Get the current instruction's debug location.
385 const DebugLoc &getDebugLoc() { return State.DL; }
386
387 /// Set the PC sections metadata to \p MD for all the next build instructions.
388 void setPCSections(MDNode *MD) { State.PCSections = MD; }
389
390 /// Get the current instruction's PC sections metadata.
391 MDNode *getPCSections() { return State.PCSections; }
392
393 /// Set the PC sections metadata to \p MD for all the next build instructions.
394 void setMMRAMetadata(MDNode *MMRA) { State.MMRA = MMRA; }
395
396 /// Get the current instruction's MMRA metadata.
397 MDNode *getMMRAMetadata() { return State.MMRA; }
398
399 /// Build and insert <empty> = \p Opcode <empty>.
400 /// The insertion point is the one set by the last call of either
401 /// setBasicBlock or setMI.
402 ///
403 /// \pre setBasicBlock or setMI must have been called.
404 ///
405 /// \return a MachineInstrBuilder for the newly created instruction.
406 MachineInstrBuilder buildInstr(unsigned Opcode) {
407 return insertInstr(MIB: buildInstrNoInsert(Opcode));
408 }
409
410 /// Build but don't insert <empty> = \p Opcode <empty>.
411 ///
412 /// \pre setMF, setBasicBlock or setMI must have been called.
413 ///
414 /// \return a MachineInstrBuilder for the newly created instruction.
415 MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
416
417 /// Insert an existing instruction at the insertion point.
418 MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
419
420 /// Build and insert a DBG_VALUE instruction expressing the fact that the
421 /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
422 MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable,
423 const MDNode *Expr);
424
425 /// Build and insert a DBG_VALUE instruction expressing the fact that the
426 /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
427 /// Expr).
428 MachineInstrBuilder buildIndirectDbgValue(Register Reg,
429 const MDNode *Variable,
430 const MDNode *Expr);
431
432 /// Build and insert a DBG_VALUE instruction expressing the fact that the
433 /// associated \p Variable lives in the stack slot specified by \p FI
434 /// (suitably modified by \p Expr).
435 MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
436 const MDNode *Expr);
437
438 /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
439 /// given by \p C (suitably modified by \p Expr).
440 MachineInstrBuilder buildConstDbgValue(const Constant &C,
441 const MDNode *Variable,
442 const MDNode *Expr);
443
444 /// Build and insert a DBG_LABEL instructions specifying that \p Label is
445 /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
446 MachineInstrBuilder buildDbgLabel(const MDNode *Label);
447
448 /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
449 ///
450 /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
451 /// the allocated memory into \p Res.
452 /// \pre setBasicBlock or setMI must have been called.
453 /// \pre \p Res must be a generic virtual register with pointer type.
454 ///
455 /// \return a MachineInstrBuilder for the newly created instruction.
456 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
457 Align Alignment);
458
459 /// Build and insert \p Res = G_FRAME_INDEX \p Idx
460 ///
461 /// G_FRAME_INDEX materializes the address of an alloca value or other
462 /// stack-based object.
463 ///
464 /// \pre setBasicBlock or setMI must have been called.
465 /// \pre \p Res must be a generic virtual register with pointer type.
466 ///
467 /// \return a MachineInstrBuilder for the newly created instruction.
468 MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
469
470 /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
471 ///
472 /// G_GLOBAL_VALUE materializes the address of the specified global
473 /// into \p Res.
474 ///
475 /// \pre setBasicBlock or setMI must have been called.
476 /// \pre \p Res must be a generic virtual register with pointer type
477 /// in the same address space as \p GV.
478 ///
479 /// \return a MachineInstrBuilder for the newly created instruction.
480 MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
481
482 /// Build and insert \p Res = G_CONSTANT_POOL \p Idx
483 ///
484 /// G_CONSTANT_POOL materializes the address of an object in the constant
485 /// pool.
486 ///
487 /// \pre setBasicBlock or setMI must have been called.
488 /// \pre \p Res must be a generic virtual register with pointer type.
489 ///
490 /// \return a MachineInstrBuilder for the newly created instruction.
491 MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx);
492
493 /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
494 ///
495 /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
496 /// storing the resulting pointer in \p Res. Addressible units are typically
497 /// bytes but this can vary between targets.
498 ///
499 /// \pre setBasicBlock or setMI must have been called.
500 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
501 /// type.
502 /// \pre \p Op1 must be a generic virtual register with scalar type.
503 ///
504 /// \return a MachineInstrBuilder for the newly created instruction.
505 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
506 const SrcOp &Op1,
507 std::optional<unsigned> Flags = std::nullopt);
508
509 /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)
510 ///
511 /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,
512 /// storing the resulting pointer in \p Res. If \p Value is zero then no
513 /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to
514 /// \p Res.
515 ///
516 /// \pre setBasicBlock or setMI must have been called.
517 /// \pre \p Op0 must be a generic virtual register with pointer type.
518 /// \pre \p ValueTy must be a scalar type.
519 /// \pre \p Res must be 0. This is to detect confusion between
520 /// materializePtrAdd() and buildPtrAdd().
521 /// \post \p Res will either be a new generic virtual register of the same
522 /// type as \p Op0 or \p Op0 itself.
523 ///
524 /// \return a MachineInstrBuilder for the newly created instruction.
525 std::optional<MachineInstrBuilder> materializePtrAdd(Register &Res,
526 Register Op0,
527 const LLT ValueTy,
528 uint64_t Value);
529
530 /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
531 MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,
532 const SrcOp &Op1) {
533 return buildInstr(Opc: TargetOpcode::G_PTRMASK, DstOps: {Res}, SrcOps: {Op0, Op1});
534 }
535
536 /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
537 ///
538 /// This clears the low bits of a pointer operand without destroying its
539 /// pointer properties. This has the effect of rounding the address *down* to
540 /// a specified alignment in bits.
541 ///
542 /// \pre setBasicBlock or setMI must have been called.
543 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
544 /// type.
545 /// \pre \p NumBits must be an integer representing the number of low bits to
546 /// be cleared in \p Op0.
547 ///
548 /// \return a MachineInstrBuilder for the newly created instruction.
549 MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
550 uint32_t NumBits);
551
552 /// Build and insert
553 /// a, b, ..., x = G_UNMERGE_VALUES \p Op0
554 /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef
555 ///
556 /// Pad \p Op0 with undef elements to match number of elements in \p Res.
557 ///
558 /// \pre setBasicBlock or setMI must have been called.
559 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
560 /// same vector element type and Op0 must have fewer elements then Res.
561 ///
562 /// \return a MachineInstrBuilder for the newly created build vector instr.
563 MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res,
564 const SrcOp &Op0);
565
566 /// Build and insert
567 /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0
568 /// \p Res = G_BUILD_VECTOR a, b, ..., x
569 ///
570 /// Delete trailing elements in \p Op0 to match number of elements in \p Res.
571 ///
572 /// \pre setBasicBlock or setMI must have been called.
573 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
574 /// same vector element type and Op0 must have more elements then Res.
575 ///
576 /// \return a MachineInstrBuilder for the newly created build vector instr.
577 MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res,
578 const SrcOp &Op0);
579
580 /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
581 ///
582 /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
583 /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
584 ///
585 /// \pre setBasicBlock or setMI must have been called.
586 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
587 /// same scalar type.
588 ////\pre \p CarryOut must be generic virtual register with scalar type
589 ///(typically s1)
590 ///
591 /// \return The newly created instruction.
592 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
593 const SrcOp &Op0, const SrcOp &Op1) {
594 return buildInstr(Opc: TargetOpcode::G_UADDO, DstOps: {Res, CarryOut}, SrcOps: {Op0, Op1});
595 }
596
597 /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1
598 MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,
599 const SrcOp &Op0, const SrcOp &Op1) {
600 return buildInstr(Opc: TargetOpcode::G_USUBO, DstOps: {Res, CarryOut}, SrcOps: {Op0, Op1});
601 }
602
603 /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1
604 MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,
605 const SrcOp &Op0, const SrcOp &Op1) {
606 return buildInstr(Opc: TargetOpcode::G_SADDO, DstOps: {Res, CarryOut}, SrcOps: {Op0, Op1});
607 }
608
609 /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1
610 MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,
611 const SrcOp &Op0, const SrcOp &Op1) {
612 return buildInstr(Opc: TargetOpcode::G_SSUBO, DstOps: {Res, CarryOut}, SrcOps: {Op0, Op1});
613 }
614
615 /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
616 /// \p Op1, \p CarryIn
617 ///
618 /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
619 /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
620 /// arithmetic.
621 ///
622 /// \pre setBasicBlock or setMI must have been called.
623 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
624 /// with the same scalar type.
625 /// \pre \p CarryOut and \p CarryIn must be generic virtual
626 /// registers with the same scalar type (typically s1)
627 ///
628 /// \return The newly created instruction.
629 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
630 const SrcOp &Op0, const SrcOp &Op1,
631 const SrcOp &CarryIn) {
632 return buildInstr(Opc: TargetOpcode::G_UADDE, DstOps: {Res, CarryOut},
633 SrcOps: {Op0, Op1, CarryIn});
634 }
635
636 /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp
637 MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,
638 const SrcOp &Op0, const SrcOp &Op1,
639 const SrcOp &CarryIn) {
640 return buildInstr(Opc: TargetOpcode::G_USUBE, DstOps: {Res, CarryOut},
641 SrcOps: {Op0, Op1, CarryIn});
642 }
643
644 /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp
645 MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,
646 const SrcOp &Op0, const SrcOp &Op1,
647 const SrcOp &CarryIn) {
648 return buildInstr(Opc: TargetOpcode::G_SADDE, DstOps: {Res, CarryOut},
649 SrcOps: {Op0, Op1, CarryIn});
650 }
651
652 /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp
653 MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,
654 const SrcOp &Op0, const SrcOp &Op1,
655 const SrcOp &CarryIn) {
656 return buildInstr(Opc: TargetOpcode::G_SSUBE, DstOps: {Res, CarryOut},
657 SrcOps: {Op0, Op1, CarryIn});
658 }
659
660 /// Build and insert \p Res = G_ANYEXT \p Op0
661 ///
662 /// G_ANYEXT produces a register of the specified width, with bits 0 to
663 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
664 /// (i.e. this is neither zero nor sign-extension). For a vector register,
665 /// each element is extended individually.
666 ///
667 /// \pre setBasicBlock or setMI must have been called.
668 /// \pre \p Res must be a generic virtual register with scalar or vector type.
669 /// \pre \p Op must be a generic virtual register with scalar or vector type.
670 /// \pre \p Op must be smaller than \p Res
671 ///
672 /// \return The newly created instruction.
673
674 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
675
676 /// Build and insert \p Res = G_SEXT \p Op
677 ///
678 /// G_SEXT produces a register of the specified width, with bits 0 to
679 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
680 /// high bit of \p Op (i.e. 2s-complement sign extended).
681 ///
682 /// \pre setBasicBlock or setMI must have been called.
683 /// \pre \p Res must be a generic virtual register with scalar or vector type.
684 /// \pre \p Op must be a generic virtual register with scalar or vector type.
685 /// \pre \p Op must be smaller than \p Res
686 ///
687 /// \return The newly created instruction.
688 MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
689
690 /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
691 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
692 return buildInstr(Opc: TargetOpcode::G_SEXT_INREG, DstOps: {Res}, SrcOps: {Op, SrcOp(ImmOp)});
693 }
694
695 /// Build and insert \p Res = G_FPEXT \p Op
696 MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op,
697 std::optional<unsigned> Flags = std::nullopt) {
698 return buildInstr(Opc: TargetOpcode::G_FPEXT, DstOps: {Res}, SrcOps: {Op}, Flags);
699 }
700
701 /// Build and insert a G_PTRTOINT instruction.
702 MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
703 return buildInstr(Opc: TargetOpcode::G_PTRTOINT, DstOps: {Dst}, SrcOps: {Src});
704 }
705
706 /// Build and insert a G_INTTOPTR instruction.
707 MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) {
708 return buildInstr(Opc: TargetOpcode::G_INTTOPTR, DstOps: {Dst}, SrcOps: {Src});
709 }
710
711 /// Build and insert \p Dst = G_BITCAST \p Src
712 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
713 return buildInstr(Opc: TargetOpcode::G_BITCAST, DstOps: {Dst}, SrcOps: {Src});
714 }
715
716 /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
717 MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src) {
718 return buildInstr(Opc: TargetOpcode::G_ADDRSPACE_CAST, DstOps: {Dst}, SrcOps: {Src});
719 }
720
721 /// \return The opcode of the extension the target wants to use for boolean
722 /// values.
723 unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
724
725 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
726 // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
727 MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
728 bool IsFP);
729
730 // Build and insert \p Res = G_SEXT_INREG \p Op, 1 or \p Res = G_AND \p Op, 1,
731 // or COPY depending on how the target wants to extend boolean values, using
732 // the original register size.
733 MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op,
734 bool IsVector,
735 bool IsFP);
736
737 /// Build and insert \p Res = G_ZEXT \p Op
738 ///
739 /// G_ZEXT produces a register of the specified width, with bits 0 to
740 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
741 /// register, each element is extended individually.
742 ///
743 /// \pre setBasicBlock or setMI must have been called.
744 /// \pre \p Res must be a generic virtual register with scalar or vector type.
745 /// \pre \p Op must be a generic virtual register with scalar or vector type.
746 /// \pre \p Op must be smaller than \p Res
747 ///
748 /// \return The newly created instruction.
749 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op,
750 std::optional<unsigned> Flags = std::nullopt);
751
752 /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
753 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
754 /// ///
755 /// \pre setBasicBlock or setMI must have been called.
756 /// \pre \p Res must be a generic virtual register with scalar or vector type.
757 /// \pre \p Op must be a generic virtual register with scalar or vector type.
758 ///
759 /// \return The newly created instruction.
760 MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
761
762 /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
763 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
764 /// ///
765 /// \pre setBasicBlock or setMI must have been called.
766 /// \pre \p Res must be a generic virtual register with scalar or vector type.
767 /// \pre \p Op must be a generic virtual register with scalar or vector type.
768 ///
769 /// \return The newly created instruction.
770 MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
771
772 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
773 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
774 /// ///
775 /// \pre setBasicBlock or setMI must have been called.
776 /// \pre \p Res must be a generic virtual register with scalar or vector type.
777 /// \pre \p Op must be a generic virtual register with scalar or vector type.
778 ///
779 /// \return The newly created instruction.
780 MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
781
782 /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
783 /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
784 /// \p Op.
785 /// ///
786 /// \pre setBasicBlock or setMI must have been called.
787 /// \pre \p Res must be a generic virtual register with scalar or vector type.
788 /// \pre \p Op must be a generic virtual register with scalar or vector type.
789 ///
790 /// \return The newly created instruction.
791 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
792 const SrcOp &Op);
793
794 /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)
795 /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is
796 /// emulated using G_AND.
797 MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op,
798 int64_t ImmOp);
799
800 /// Build and insert an appropriate cast between two registers of equal size.
801 MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
802
803 /// Build and insert G_BR \p Dest
804 ///
805 /// G_BR is an unconditional branch to \p Dest.
806 ///
807 /// \pre setBasicBlock or setMI must have been called.
808 ///
809 /// \return a MachineInstrBuilder for the newly created instruction.
810 MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
811
812 /// Build and insert G_BRCOND \p Tst, \p Dest
813 ///
814 /// G_BRCOND is a conditional branch to \p Dest.
815 ///
816 /// \pre setBasicBlock or setMI must have been called.
817 /// \pre \p Tst must be a generic virtual register with scalar
818 /// type. At the beginning of legalization, this will be a single
819 /// bit (s1). Targets with interesting flags registers may change
820 /// this. For a wider type, whether the branch is taken must only
821 /// depend on bit 0 (for now).
822 ///
823 /// \return The newly created instruction.
824 MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest);
825
826 /// Build and insert G_BRINDIRECT \p Tgt
827 ///
828 /// G_BRINDIRECT is an indirect branch to \p Tgt.
829 ///
830 /// \pre setBasicBlock or setMI must have been called.
831 /// \pre \p Tgt must be a generic virtual register with pointer type.
832 ///
833 /// \return a MachineInstrBuilder for the newly created instruction.
834 MachineInstrBuilder buildBrIndirect(Register Tgt);
835
836 /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
837 ///
838 /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
839 /// jump table index \p JTI and index \p IndexReg
840 ///
841 /// \pre setBasicBlock or setMI must have been called.
842 /// \pre \p TablePtr must be a generic virtual register with pointer type.
843 /// \pre \p JTI must be a jump table index.
844 /// \pre \p IndexReg must be a generic virtual register with pointer type.
845 ///
846 /// \return a MachineInstrBuilder for the newly created instruction.
847 MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
848 Register IndexReg);
849
850 /// Build and insert \p Res = G_CONSTANT \p Val
851 ///
852 /// G_CONSTANT is an integer constant with the specified size and value. \p
853 /// Val will be extended or truncated to the size of \p Reg.
854 ///
855 /// \pre setBasicBlock or setMI must have been called.
856 /// \pre \p Res must be a generic virtual register with scalar or pointer
857 /// type.
858 ///
859 /// \return The newly created instruction.
860 virtual MachineInstrBuilder buildConstant(const DstOp &Res,
861 const ConstantInt &Val);
862
863 /// Build and insert \p Res = G_CONSTANT \p Val
864 ///
865 /// G_CONSTANT is an integer constant with the specified size and value.
866 ///
867 /// \pre setBasicBlock or setMI must have been called.
868 /// \pre \p Res must be a generic virtual register with scalar type.
869 ///
870 /// \return The newly created instruction.
871 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
872 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
873
874 /// Build and insert \p Res = G_FCONSTANT \p Val
875 ///
876 /// G_FCONSTANT is a floating-point constant with the specified size and
877 /// value.
878 ///
879 /// \pre setBasicBlock or setMI must have been called.
880 /// \pre \p Res must be a generic virtual register with scalar type.
881 ///
882 /// \return The newly created instruction.
883 virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
884 const ConstantFP &Val);
885
886 MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
887 MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
888
889 /// Build and insert G_PTRAUTH_GLOBAL_VALUE
890 ///
891 /// \return a MachineInstrBuilder for the newly created instruction.
892 MachineInstrBuilder buildConstantPtrAuth(const DstOp &Res,
893 const ConstantPtrAuth *CPA,
894 Register Addr, Register AddrDisc);
895
896 /// Build and insert \p Res = COPY Op
897 ///
898 /// Register-to-register COPY sets \p Res to \p Op.
899 ///
900 /// \pre setBasicBlock or setMI must have been called.
901 ///
902 /// \return a MachineInstrBuilder for the newly created instruction.
903 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
904
905
906 /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN
907 ///
908 /// \return a MachineInstrBuilder for the newly created instruction.
909 MachineInstrBuilder buildAssertInstr(unsigned Opc, const DstOp &Res,
910 const SrcOp &Op, unsigned Val) {
911 return buildInstr(Opc, DstOps: Res, SrcOps: Op).addImm(Val);
912 }
913
914 /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
915 ///
916 /// \return a MachineInstrBuilder for the newly created instruction.
917 MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op,
918 unsigned Size) {
919 return buildAssertInstr(Opc: TargetOpcode::G_ASSERT_ZEXT, Res, Op, Val: Size);
920 }
921
922 /// Build and insert \p Res = G_ASSERT_SEXT Op, Size
923 ///
924 /// \return a MachineInstrBuilder for the newly created instruction.
925 MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op,
926 unsigned Size) {
927 return buildAssertInstr(Opc: TargetOpcode::G_ASSERT_SEXT, Res, Op, Val: Size);
928 }
929
930 /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal
931 ///
932 /// \return a MachineInstrBuilder for the newly created instruction.
933 MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op,
934 Align AlignVal) {
935 return buildAssertInstr(Opc: TargetOpcode::G_ASSERT_ALIGN, Res, Op,
936 Val: AlignVal.value());
937 }
938
939 /// Build and insert `Res = G_LOAD Addr, MMO`.
940 ///
941 /// Loads the value stored at \p Addr. Puts the result in \p Res.
942 ///
943 /// \pre setBasicBlock or setMI must have been called.
944 /// \pre \p Res must be a generic virtual register.
945 /// \pre \p Addr must be a generic virtual register with pointer type.
946 ///
947 /// \return a MachineInstrBuilder for the newly created instruction.
948 MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr,
949 MachineMemOperand &MMO) {
950 return buildLoadInstr(Opcode: TargetOpcode::G_LOAD, Res, Addr, MMO);
951 }
952
953 /// Build and insert a G_LOAD instruction, while constructing the
954 /// MachineMemOperand.
955 MachineInstrBuilder
956 buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo,
957 Align Alignment,
958 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
959 const AAMDNodes &AAInfo = AAMDNodes());
960
961 /// Build and insert `Res = <opcode> Addr, MMO`.
962 ///
963 /// Loads the value stored at \p Addr. Puts the result in \p Res.
964 ///
965 /// \pre setBasicBlock or setMI must have been called.
966 /// \pre \p Res must be a generic virtual register.
967 /// \pre \p Addr must be a generic virtual register with pointer type.
968 ///
969 /// \return a MachineInstrBuilder for the newly created instruction.
970 MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
971 const SrcOp &Addr, MachineMemOperand &MMO);
972
973 /// Helper to create a load from a constant offset given a base address. Load
974 /// the type of \p Dst from \p Offset from the given base address and memory
975 /// operand.
976 MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst,
977 const SrcOp &BasePtr,
978 MachineMemOperand &BaseMMO,
979 int64_t Offset);
980
981 /// Build and insert `G_STORE Val, Addr, MMO`.
982 ///
983 /// Stores the value \p Val to \p Addr.
984 ///
985 /// \pre setBasicBlock or setMI must have been called.
986 /// \pre \p Val must be a generic virtual register.
987 /// \pre \p Addr must be a generic virtual register with pointer type.
988 ///
989 /// \return a MachineInstrBuilder for the newly created instruction.
990 MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
991 MachineMemOperand &MMO);
992
993 /// Build and insert a G_STORE instruction, while constructing the
994 /// MachineMemOperand.
995 MachineInstrBuilder
996 buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo,
997 Align Alignment,
998 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
999 const AAMDNodes &AAInfo = AAMDNodes());
1000
1001 /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
1002 ///
1003 /// \pre setBasicBlock or setMI must have been called.
1004 /// \pre \p Res and \p Src must be generic virtual registers.
1005 ///
1006 /// \return a MachineInstrBuilder for the newly created instruction.
1007 MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
1008
1009 /// Build and insert \p Res = IMPLICIT_DEF.
1010 MachineInstrBuilder buildUndef(const DstOp &Res);
1011
1012 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
1013 ///
1014 /// G_MERGE_VALUES combines the input elements contiguously into a larger
1015 /// register. It should only be used when the destination register is not a
1016 /// vector.
1017 ///
1018 /// \pre setBasicBlock or setMI must have been called.
1019 /// \pre The entire register \p Res (and no more) must be covered by the input
1020 /// registers.
1021 /// \pre The type of all \p Ops registers must be identical.
1022 ///
1023 /// \return a MachineInstrBuilder for the newly created instruction.
1024 MachineInstrBuilder buildMergeValues(const DstOp &Res,
1025 ArrayRef<Register> Ops);
1026
1027 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
1028 /// or \p Res = G_BUILD_VECTOR \p Op0, ...
1029 /// or \p Res = G_CONCAT_VECTORS \p Op0, ...
1030 ///
1031 /// G_MERGE_VALUES combines the input elements contiguously into a larger
1032 /// register. It is used when the destination register is not a vector.
1033 /// G_BUILD_VECTOR combines scalar inputs into a vector register.
1034 /// G_CONCAT_VECTORS combines vector inputs into a vector register.
1035 ///
1036 /// \pre setBasicBlock or setMI must have been called.
1037 /// \pre The entire register \p Res (and no more) must be covered by the input
1038 /// registers.
1039 /// \pre The type of all \p Ops registers must be identical.
1040 ///
1041 /// \return a MachineInstrBuilder for the newly created instruction. The
1042 /// opcode of the new instruction will depend on the types of both
1043 /// the destination and the sources.
1044 MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res,
1045 ArrayRef<Register> Ops);
1046 MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res,
1047 std::initializer_list<SrcOp> Ops);
1048
1049 /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
1050 ///
1051 /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
1052 ///
1053 /// \pre setBasicBlock or setMI must have been called.
1054 /// \pre The entire register \p Res (and no more) must be covered by the input
1055 /// registers.
1056 /// \pre The type of all \p Res registers must be identical.
1057 ///
1058 /// \return a MachineInstrBuilder for the newly created instruction.
1059 MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op);
1060 MachineInstrBuilder buildUnmerge(ArrayRef<Register> Res, const SrcOp &Op);
1061
1062 /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
1063 MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op);
1064
1065 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
1066 ///
1067 /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
1068 /// \pre setBasicBlock or setMI must have been called.
1069 /// \pre The entire register \p Res (and no more) must be covered by the
1070 /// input scalar registers.
1071 /// \pre The type of all \p Ops registers must be identical.
1072 ///
1073 /// \return a MachineInstrBuilder for the newly created instruction.
1074 MachineInstrBuilder buildBuildVector(const DstOp &Res,
1075 ArrayRef<Register> Ops);
1076
1077 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... where each OpN is
1078 /// built with G_CONSTANT.
1079 MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res,
1080 ArrayRef<APInt> Ops);
1081
1082 /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
1083 /// the number of elements
1084 MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src);
1085
1086 /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
1087 ///
1088 /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
1089 /// which have types larger than the destination vector element type, and
1090 /// truncates the values to fit.
1091 ///
1092 /// If the operands given are already the same size as the vector elt type,
1093 /// then this method will instead create a G_BUILD_VECTOR instruction.
1094 ///
1095 /// \pre setBasicBlock or setMI must have been called.
1096 /// \pre The type of all \p Ops registers must be identical.
1097 ///
1098 /// \return a MachineInstrBuilder for the newly created instruction.
1099 MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res,
1100 ArrayRef<Register> Ops);
1101
1102 /// Build and insert a vector splat of a scalar \p Src using a
1103 /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom.
1104 ///
1105 /// \pre setBasicBlock or setMI must have been called.
1106 /// \pre \p Src must have the same type as the element type of \p Dst
1107 ///
1108 /// \return a MachineInstrBuilder for the newly created instruction.
1109 MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src);
1110
1111 /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
1112 ///
1113 /// \pre setBasicBlock or setMI must have been called.
1114 ///
1115 /// \return a MachineInstrBuilder for the newly created instruction.
1116 MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
1117 const SrcOp &Src2, ArrayRef<int> Mask);
1118
1119 /// Build and insert \p Res = G_SPLAT_VECTOR \p Val
1120 ///
1121 /// \pre setBasicBlock or setMI must have been called.
1122 /// \pre \p Res must be a generic virtual register with vector type.
1123 /// \pre \p Val must be a generic virtual register with scalar type.
1124 ///
1125 /// \return a MachineInstrBuilder for the newly created instruction.
1126 MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Val);
1127
1128 /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
1129 ///
1130 /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
1131 /// vectors.
1132 ///
1133 /// \pre setBasicBlock or setMI must have been called.
1134 /// \pre The entire register \p Res (and no more) must be covered by the input
1135 /// registers.
1136 /// \pre The type of all source operands must be identical.
1137 ///
1138 /// \return a MachineInstrBuilder for the newly created instruction.
1139 MachineInstrBuilder buildConcatVectors(const DstOp &Res,
1140 ArrayRef<Register> Ops);
1141
1142 /// Build and insert `Res = G_INSERT_SUBVECTOR Src0, Src1, Idx`.
1143 ///
1144 /// \pre setBasicBlock or setMI must have been called.
1145 /// \pre \p Res, \p Src0, and \p Src1 must be generic virtual registers with
1146 /// vector type.
1147 ///
1148 /// \return a MachineInstrBuilder for the newly created instruction.
1149 MachineInstrBuilder buildInsertSubvector(const DstOp &Res, const SrcOp &Src0,
1150 const SrcOp &Src1, unsigned Index);
1151
1152 /// Build and insert `Res = G_EXTRACT_SUBVECTOR Src, Idx0`.
1153 ///
1154 /// \pre setBasicBlock or setMI must have been called.
1155 /// \pre \p Res and \p Src must be generic virtual registers with vector type.
1156 ///
1157 /// \return a MachineInstrBuilder for the newly created instruction.
1158 MachineInstrBuilder buildExtractSubvector(const DstOp &Res, const SrcOp &Src,
1159 unsigned Index);
1160
1161 MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
1162 const SrcOp &Op, unsigned Index);
1163
1164 /// Build and insert \p Res = G_VSCALE \p MinElts
1165 ///
1166 /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
1167 /// into \p Res.
1168 ///
1169 /// \pre setBasicBlock or setMI must have been called.
1170 /// \pre \p Res must be a generic virtual register with scalar type.
1171 ///
1172 /// \return a MachineInstrBuilder for the newly created instruction.
1173 MachineInstrBuilder buildVScale(const DstOp &Res, unsigned MinElts);
1174
1175 /// Build and insert \p Res = G_VSCALE \p MinElts
1176 ///
1177 /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
1178 /// into \p Res.
1179 ///
1180 /// \pre setBasicBlock or setMI must have been called.
1181 /// \pre \p Res must be a generic virtual register with scalar type.
1182 ///
1183 /// \return a MachineInstrBuilder for the newly created instruction.
1184 MachineInstrBuilder buildVScale(const DstOp &Res, const ConstantInt &MinElts);
1185
1186 /// Build and insert \p Res = G_VSCALE \p MinElts
1187 ///
1188 /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
1189 /// into \p Res.
1190 ///
1191 /// \pre setBasicBlock or setMI must have been called.
1192 /// \pre \p Res must be a generic virtual register with scalar type.
1193 ///
1194 /// \return a MachineInstrBuilder for the newly created instruction.
1195 MachineInstrBuilder buildVScale(const DstOp &Res, const APInt &MinElts);
1196
1197 /// Build and insert a G_INTRINSIC instruction.
1198 ///
1199 /// There are four different opcodes based on combinations of whether the
1200 /// intrinsic has side effects and whether it is convergent. These properties
1201 /// can be specified as explicit parameters, or else they are retrieved from
1202 /// the MCID for the intrinsic.
1203 ///
1204 /// The parameter \p Res provides the Registers or MOs that will be defined by
1205 /// this instruction.
1206 ///
1207 /// \pre setBasicBlock or setMI must have been called.
1208 ///
1209 /// \return a MachineInstrBuilder for the newly created instruction.
1210 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<Register> Res,
1211 bool HasSideEffects, bool isConvergent);
1212 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<Register> Res);
1213 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res,
1214 bool HasSideEffects, bool isConvergent);
1215 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res);
1216
1217 /// Build and insert \p Res = G_FPTRUNC \p Op
1218 ///
1219 /// G_FPTRUNC converts a floating-point value into one with a smaller type.
1220 ///
1221 /// \pre setBasicBlock or setMI must have been called.
1222 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1223 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1224 /// \pre \p Res must be smaller than \p Op
1225 ///
1226 /// \return The newly created instruction.
1227 MachineInstrBuilder
1228 buildFPTrunc(const DstOp &Res, const SrcOp &Op,
1229 std::optional<unsigned> Flags = std::nullopt);
1230
1231 /// Build and insert \p Res = G_TRUNC \p Op
1232 ///
1233 /// G_TRUNC extracts the low bits of a type. For a vector type each element is
1234 /// truncated independently before being packed into the destination.
1235 ///
1236 /// \pre setBasicBlock or setMI must have been called.
1237 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1238 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1239 /// \pre \p Res must be smaller than \p Op
1240 ///
1241 /// \return The newly created instruction.
1242 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op,
1243 std::optional<unsigned> Flags = std::nullopt);
1244
1245 /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
1246 ///
1247 /// \pre setBasicBlock or setMI must have been called.
1248
1249 /// \pre \p Res must be a generic virtual register with scalar or
1250 /// vector type. Typically this starts as s1 or <N x s1>.
1251 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1252 /// same number of elements as \p Res. If \p Res is a scalar,
1253 /// \p Op0 must be either a scalar or pointer.
1254 /// \pre \p Pred must be an integer predicate.
1255 ///
1256 /// \return a MachineInstrBuilder for the newly created instruction.
1257 MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
1258 const SrcOp &Op0, const SrcOp &Op1);
1259
1260 /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
1261 ///
1262 /// \pre setBasicBlock or setMI must have been called.
1263
1264 /// \pre \p Res must be a generic virtual register with scalar or
1265 /// vector type. Typically this starts as s1 or <N x s1>.
1266 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1267 /// same number of elements as \p Res (or scalar, if \p Res is
1268 /// scalar).
1269 /// \pre \p Pred must be a floating-point predicate.
1270 ///
1271 /// \return a MachineInstrBuilder for the newly created instruction.
1272 MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
1273 const SrcOp &Op0, const SrcOp &Op1,
1274 std::optional<unsigned> Flags = std::nullopt);
1275
1276 /// Build and insert a \p Res = G_SCMP \p Op0, \p Op1
1277 ///
1278 /// \pre setBasicBlock or setMI must have been called.
1279
1280 /// \pre \p Res must be a generic virtual register with scalar or
1281 /// vector type. Typically this starts as s2 or <N x s2>.
1282 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1283 /// same number of elements as \p Res. If \p Res is a scalar,
1284 /// \p Op0 must be a scalar.
1285 ///
1286 /// \return a MachineInstrBuilder for the newly created instruction.
1287 MachineInstrBuilder buildSCmp(const DstOp &Res, const SrcOp &Op0,
1288 const SrcOp &Op1);
1289
1290 /// Build and insert a \p Res = G_UCMP \p Op0, \p Op1
1291 ///
1292 /// \pre setBasicBlock or setMI must have been called.
1293
1294 /// \pre \p Res must be a generic virtual register with scalar or
1295 /// vector type. Typically this starts as s2 or <N x s2>.
1296 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1297 /// same number of elements as \p Res. If \p Res is a scalar,
1298 /// \p Op0 must be a scalar.
1299 ///
1300 /// \return a MachineInstrBuilder for the newly created instruction.
1301 MachineInstrBuilder buildUCmp(const DstOp &Res, const SrcOp &Op0,
1302 const SrcOp &Op1);
1303
1304 /// Build and insert a \p Res = G_IS_FPCLASS \p Src, \p Mask
1305 MachineInstrBuilder buildIsFPClass(const DstOp &Res, const SrcOp &Src,
1306 unsigned Mask) {
1307 return buildInstr(Opc: TargetOpcode::G_IS_FPCLASS, DstOps: {Res},
1308 SrcOps: {Src, SrcOp(static_cast<int64_t>(Mask))});
1309 }
1310
1311 /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
1312 ///
1313 /// \pre setBasicBlock or setMI must have been called.
1314 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1315 /// with the same type.
1316 /// \pre \p Tst must be a generic virtual register with scalar, pointer or
1317 /// vector type. If vector then it must have the same number of
1318 /// elements as the other parameters.
1319 ///
1320 /// \return a MachineInstrBuilder for the newly created instruction.
1321 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
1322 const SrcOp &Op0, const SrcOp &Op1,
1323 std::optional<unsigned> Flags = std::nullopt);
1324
1325 /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
1326 /// \p Elt, \p Idx
1327 ///
1328 /// \pre setBasicBlock or setMI must have been called.
1329 /// \pre \p Res and \p Val must be a generic virtual register
1330 // with the same vector type.
1331 /// \pre \p Elt and \p Idx must be a generic virtual register
1332 /// with scalar type.
1333 ///
1334 /// \return The newly created instruction.
1335 MachineInstrBuilder buildInsertVectorElement(const DstOp &Res,
1336 const SrcOp &Val,
1337 const SrcOp &Elt,
1338 const SrcOp &Idx);
1339
1340 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1341 ///
1342 /// \pre setBasicBlock or setMI must have been called.
1343 /// \pre \p Res must be a generic virtual register with scalar type.
1344 /// \pre \p Val must be a generic virtual register with vector type.
1345 ///
1346 /// \return The newly created instruction.
1347 MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res,
1348 const SrcOp &Val,
1349 const int Idx) {
1350 auto TLI = getMF().getSubtarget().getTargetLowering();
1351 unsigned VecIdxWidth = TLI->getVectorIdxTy(DL: getDataLayout()).getSizeInBits();
1352 return buildExtractVectorElement(
1353 Res, Val, Idx: buildConstant(Res: LLT::scalar(SizeInBits: VecIdxWidth), Val: Idx));
1354 }
1355
1356 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1357 ///
1358 /// \pre setBasicBlock or setMI must have been called.
1359 /// \pre \p Res must be a generic virtual register with scalar type.
1360 /// \pre \p Val must be a generic virtual register with vector type.
1361 /// \pre \p Idx must be a generic virtual register with scalar type.
1362 ///
1363 /// \return The newly created instruction.
1364 MachineInstrBuilder buildExtractVectorElement(const DstOp &Res,
1365 const SrcOp &Val,
1366 const SrcOp &Idx);
1367
1368 /// Build and insert `OldValRes<def>, SuccessRes<def> =
1369 /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
1370 ///
1371 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1372 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1373 /// Addr in \p Res, along with an s1 indicating whether it was replaced.
1374 ///
1375 /// \pre setBasicBlock or setMI must have been called.
1376 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1377 /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
1378 /// will be assigned 0 on failure and 1 on success.
1379 /// \pre \p Addr must be a generic virtual register with pointer type.
1380 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1381 /// registers of the same type.
1382 ///
1383 /// \return a MachineInstrBuilder for the newly created instruction.
1384 MachineInstrBuilder
1385 buildAtomicCmpXchgWithSuccess(const DstOp &OldValRes, const DstOp &SuccessRes,
1386 const SrcOp &Addr, const SrcOp &CmpVal,
1387 const SrcOp &NewVal, MachineMemOperand &MMO);
1388
1389 /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
1390 /// MMO`.
1391 ///
1392 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1393 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1394 /// Addr in \p Res.
1395 ///
1396 /// \pre setBasicBlock or setMI must have been called.
1397 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1398 /// \pre \p Addr must be a generic virtual register with pointer type.
1399 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1400 /// registers of the same type.
1401 ///
1402 /// \return a MachineInstrBuilder for the newly created instruction.
1403 MachineInstrBuilder buildAtomicCmpXchg(const DstOp &OldValRes,
1404 const SrcOp &Addr, const SrcOp &CmpVal,
1405 const SrcOp &NewVal,
1406 MachineMemOperand &MMO);
1407
1408 /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
1409 ///
1410 /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
1411 /// original value from \p Addr in \p OldValRes. The modification is
1412 /// determined by the opcode.
1413 ///
1414 /// \pre setBasicBlock or setMI must have been called.
1415 /// \pre \p OldValRes must be a generic virtual register.
1416 /// \pre \p Addr must be a generic virtual register with pointer type.
1417 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1418 /// same type.
1419 ///
1420 /// \return a MachineInstrBuilder for the newly created instruction.
1421 MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1422 const SrcOp &Addr, const SrcOp &Val,
1423 MachineMemOperand &MMO);
1424
1425 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1426 ///
1427 /// Atomically replace the value at \p Addr with \p Val. Puts the original
1428 /// value from \p Addr in \p OldValRes.
1429 ///
1430 /// \pre setBasicBlock or setMI must have been called.
1431 /// \pre \p OldValRes must be a generic virtual register.
1432 /// \pre \p Addr must be a generic virtual register with pointer type.
1433 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1434 /// same type.
1435 ///
1436 /// \return a MachineInstrBuilder for the newly created instruction.
1437 MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr,
1438 Register Val, MachineMemOperand &MMO);
1439
1440 /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1441 ///
1442 /// Atomically replace the value at \p Addr with the addition of \p Val and
1443 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1444 ///
1445 /// \pre setBasicBlock or setMI must have been called.
1446 /// \pre \p OldValRes must be a generic virtual register.
1447 /// \pre \p Addr must be a generic virtual register with pointer type.
1448 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1449 /// same type.
1450 ///
1451 /// \return a MachineInstrBuilder for the newly created instruction.
1452 MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr,
1453 Register Val, MachineMemOperand &MMO);
1454
1455 /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1456 ///
1457 /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1458 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1459 ///
1460 /// \pre setBasicBlock or setMI must have been called.
1461 /// \pre \p OldValRes must be a generic virtual register.
1462 /// \pre \p Addr must be a generic virtual register with pointer type.
1463 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1464 /// same type.
1465 ///
1466 /// \return a MachineInstrBuilder for the newly created instruction.
1467 MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr,
1468 Register Val, MachineMemOperand &MMO);
1469
1470 /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1471 ///
1472 /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1473 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1474 ///
1475 /// \pre setBasicBlock or setMI must have been called.
1476 /// \pre \p OldValRes must be a generic virtual register.
1477 /// \pre \p Addr must be a generic virtual register with pointer type.
1478 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1479 /// same type.
1480 ///
1481 /// \return a MachineInstrBuilder for the newly created instruction.
1482 MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr,
1483 Register Val, MachineMemOperand &MMO);
1484
1485 /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1486 ///
1487 /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1488 /// and the original value. Puts the original value from \p Addr in \p
1489 /// OldValRes.
1490 ///
1491 /// \pre setBasicBlock or setMI must have been called.
1492 /// \pre \p OldValRes must be a generic virtual register.
1493 /// \pre \p Addr must be a generic virtual register with pointer type.
1494 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1495 /// same type.
1496 ///
1497 /// \return a MachineInstrBuilder for the newly created instruction.
1498 MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr,
1499 Register Val, MachineMemOperand &MMO);
1500
1501 /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1502 ///
1503 /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1504 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1505 ///
1506 /// \pre setBasicBlock or setMI must have been called.
1507 /// \pre \p OldValRes must be a generic virtual register.
1508 /// \pre \p Addr must be a generic virtual register with pointer type.
1509 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1510 /// same type.
1511 ///
1512 /// \return a MachineInstrBuilder for the newly created instruction.
1513 MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr,
1514 Register Val, MachineMemOperand &MMO);
1515
1516 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1517 ///
1518 /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1519 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1520 ///
1521 /// \pre setBasicBlock or setMI must have been called.
1522 /// \pre \p OldValRes must be a generic virtual register.
1523 /// \pre \p Addr must be a generic virtual register with pointer type.
1524 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1525 /// same type.
1526 ///
1527 /// \return a MachineInstrBuilder for the newly created instruction.
1528 MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr,
1529 Register Val, MachineMemOperand &MMO);
1530
1531 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1532 ///
1533 /// Atomically replace the value at \p Addr with the signed maximum of \p
1534 /// Val and the original value. Puts the original value from \p Addr in \p
1535 /// OldValRes.
1536 ///
1537 /// \pre setBasicBlock or setMI must have been called.
1538 /// \pre \p OldValRes must be a generic virtual register.
1539 /// \pre \p Addr must be a generic virtual register with pointer type.
1540 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1541 /// same type.
1542 ///
1543 /// \return a MachineInstrBuilder for the newly created instruction.
1544 MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr,
1545 Register Val, MachineMemOperand &MMO);
1546
1547 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1548 ///
1549 /// Atomically replace the value at \p Addr with the signed minimum of \p
1550 /// Val and the original value. Puts the original value from \p Addr in \p
1551 /// OldValRes.
1552 ///
1553 /// \pre setBasicBlock or setMI must have been called.
1554 /// \pre \p OldValRes must be a generic virtual register.
1555 /// \pre \p Addr must be a generic virtual register with pointer type.
1556 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1557 /// same type.
1558 ///
1559 /// \return a MachineInstrBuilder for the newly created instruction.
1560 MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr,
1561 Register Val, MachineMemOperand &MMO);
1562
1563 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1564 ///
1565 /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1566 /// Val and the original value. Puts the original value from \p Addr in \p
1567 /// OldValRes.
1568 ///
1569 /// \pre setBasicBlock or setMI must have been called.
1570 /// \pre \p OldValRes must be a generic virtual register.
1571 /// \pre \p Addr must be a generic virtual register with pointer type.
1572 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1573 /// same type.
1574 ///
1575 /// \return a MachineInstrBuilder for the newly created instruction.
1576 MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr,
1577 Register Val, MachineMemOperand &MMO);
1578
1579 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1580 ///
1581 /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1582 /// Val and the original value. Puts the original value from \p Addr in \p
1583 /// OldValRes.
1584 ///
1585 /// \pre setBasicBlock or setMI must have been called.
1586 /// \pre \p OldValRes must be a generic virtual register.
1587 /// \pre \p Addr must be a generic virtual register with pointer type.
1588 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1589 /// same type.
1590 ///
1591 /// \return a MachineInstrBuilder for the newly created instruction.
1592 MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr,
1593 Register Val, MachineMemOperand &MMO);
1594
1595 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1596 MachineInstrBuilder buildAtomicRMWFAdd(
1597 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1598 MachineMemOperand &MMO);
1599
1600 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1601 MachineInstrBuilder buildAtomicRMWFSub(
1602 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1603 MachineMemOperand &MMO);
1604
1605 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO`.
1606 ///
1607 /// Atomically replace the value at \p Addr with the floating point maximum of
1608 /// \p Val and the original value. Puts the original value from \p Addr in \p
1609 /// OldValRes.
1610 ///
1611 /// \pre setBasicBlock or setMI must have been called.
1612 /// \pre \p OldValRes must be a generic virtual register.
1613 /// \pre \p Addr must be a generic virtual register with pointer type.
1614 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1615 /// same type.
1616 ///
1617 /// \return a MachineInstrBuilder for the newly created instruction.
1618 MachineInstrBuilder buildAtomicRMWFMax(
1619 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1620 MachineMemOperand &MMO);
1621
1622 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO`.
1623 ///
1624 /// Atomically replace the value at \p Addr with the floating point minimum of
1625 /// \p Val and the original value. Puts the original value from \p Addr in \p
1626 /// OldValRes.
1627 ///
1628 /// \pre setBasicBlock or setMI must have been called.
1629 /// \pre \p OldValRes must be a generic virtual register.
1630 /// \pre \p Addr must be a generic virtual register with pointer type.
1631 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1632 /// same type.
1633 ///
1634 /// \return a MachineInstrBuilder for the newly created instruction.
1635 MachineInstrBuilder buildAtomicRMWFMin(
1636 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1637 MachineMemOperand &MMO);
1638
1639 /// Build and insert `G_FENCE Ordering, Scope`.
1640 MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1641
1642 /// Build and insert G_PREFETCH \p Addr, \p RW, \p Locality, \p CacheType
1643 MachineInstrBuilder buildPrefetch(const SrcOp &Addr, unsigned RW,
1644 unsigned Locality, unsigned CacheType,
1645 MachineMemOperand &MMO);
1646
1647 /// Build and insert \p Dst = G_FREEZE \p Src
1648 MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
1649 return buildInstr(Opc: TargetOpcode::G_FREEZE, DstOps: {Dst}, SrcOps: {Src});
1650 }
1651
1652 /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1653 ///
1654 /// G_BLOCK_ADDR computes the address of a basic block.
1655 ///
1656 /// \pre setBasicBlock or setMI must have been called.
1657 /// \pre \p Res must be a generic virtual register of a pointer type.
1658 ///
1659 /// \return The newly created instruction.
1660 MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA);
1661
1662 /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1663 ///
1664 /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1665 /// truncated to their width.
1666 ///
1667 /// \pre setBasicBlock or setMI must have been called.
1668 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1669 /// with the same (scalar or vector) type).
1670 ///
1671 /// \return a MachineInstrBuilder for the newly created instruction.
1672
1673 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1674 const SrcOp &Src1,
1675 std::optional<unsigned> Flags = std::nullopt) {
1676 return buildInstr(Opc: TargetOpcode::G_ADD, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1677 }
1678
1679 /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1680 ///
1681 /// G_SUB sets \p Res to the difference of integer parameters \p Op0 and
1682 /// \p Op1, truncated to their width.
1683 ///
1684 /// \pre setBasicBlock or setMI must have been called.
1685 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1686 /// with the same (scalar or vector) type).
1687 ///
1688 /// \return a MachineInstrBuilder for the newly created instruction.
1689
1690 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1691 const SrcOp &Src1,
1692 std::optional<unsigned> Flags = std::nullopt) {
1693 return buildInstr(Opc: TargetOpcode::G_SUB, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1694 }
1695
1696 /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1697 ///
1698 /// G_MUL sets \p Res to the product of integer parameters \p Op0 and \p Op1,
1699 /// truncated to their width.
1700 ///
1701 /// \pre setBasicBlock or setMI must have been called.
1702 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1703 /// with the same (scalar or vector) type).
1704 ///
1705 /// \return a MachineInstrBuilder for the newly created instruction.
1706 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1707 const SrcOp &Src1,
1708 std::optional<unsigned> Flags = std::nullopt) {
1709 return buildInstr(Opc: TargetOpcode::G_MUL, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1710 }
1711
1712 MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1713 const SrcOp &Src1,
1714 std::optional<unsigned> Flags = std::nullopt) {
1715 return buildInstr(Opc: TargetOpcode::G_UMULH, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1716 }
1717
1718 MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1719 const SrcOp &Src1,
1720 std::optional<unsigned> Flags = std::nullopt) {
1721 return buildInstr(Opc: TargetOpcode::G_SMULH, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1722 }
1723
1724 /// Build and insert \p Res = G_UREM \p Op0, \p Op1
1725 MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0,
1726 const SrcOp &Src1,
1727 std::optional<unsigned> Flags = std::nullopt) {
1728 return buildInstr(Opc: TargetOpcode::G_UREM, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1729 }
1730
1731 MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1732 const SrcOp &Src1,
1733 std::optional<unsigned> Flags = std::nullopt) {
1734 return buildInstr(Opc: TargetOpcode::G_FMUL, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1735 }
1736
1737 MachineInstrBuilder
1738 buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1739 std::optional<unsigned> Flags = std::nullopt) {
1740 return buildInstr(Opc: TargetOpcode::G_FMINNUM, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1741 }
1742
1743 MachineInstrBuilder
1744 buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1745 std::optional<unsigned> Flags = std::nullopt) {
1746 return buildInstr(Opc: TargetOpcode::G_FMAXNUM, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1747 }
1748
1749 MachineInstrBuilder
1750 buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1751 std::optional<unsigned> Flags = std::nullopt) {
1752 return buildInstr(Opc: TargetOpcode::G_FMINNUM_IEEE, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1753 }
1754
1755 MachineInstrBuilder
1756 buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1757 std::optional<unsigned> Flags = std::nullopt) {
1758 return buildInstr(Opc: TargetOpcode::G_FMAXNUM_IEEE, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1759 }
1760
1761 MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1762 const SrcOp &Src1,
1763 std::optional<unsigned> Flags = std::nullopt) {
1764 return buildInstr(Opc: TargetOpcode::G_SHL, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1765 }
1766
1767 MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1768 const SrcOp &Src1,
1769 std::optional<unsigned> Flags = std::nullopt) {
1770 return buildInstr(Opc: TargetOpcode::G_LSHR, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1771 }
1772
1773 MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1774 const SrcOp &Src1,
1775 std::optional<unsigned> Flags = std::nullopt) {
1776 return buildInstr(Opc: TargetOpcode::G_ASHR, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1777 }
1778
1779 /// Build and insert \p Res = G_AND \p Op0, \p Op1
1780 ///
1781 /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1782 /// Op1.
1783 ///
1784 /// \pre setBasicBlock or setMI must have been called.
1785 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1786 /// with the same (scalar or vector) type).
1787 ///
1788 /// \return a MachineInstrBuilder for the newly created instruction.
1789
1790 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1791 const SrcOp &Src1) {
1792 return buildInstr(Opc: TargetOpcode::G_AND, DstOps: {Dst}, SrcOps: {Src0, Src1});
1793 }
1794
1795 /// Build and insert \p Res = G_OR \p Op0, \p Op1
1796 ///
1797 /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1798 /// Op1.
1799 ///
1800 /// \pre setBasicBlock or setMI must have been called.
1801 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1802 /// with the same (scalar or vector) type).
1803 ///
1804 /// \return a MachineInstrBuilder for the newly created instruction.
1805 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1806 const SrcOp &Src1,
1807 std::optional<unsigned> Flags = std::nullopt) {
1808 return buildInstr(Opc: TargetOpcode::G_OR, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1809 }
1810
1811 /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1812 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1813 const SrcOp &Src1) {
1814 return buildInstr(Opc: TargetOpcode::G_XOR, DstOps: {Dst}, SrcOps: {Src0, Src1});
1815 }
1816
1817 /// Build and insert a bitwise not,
1818 /// \p NegOne = G_CONSTANT -1
1819 /// \p Res = G_OR \p Op0, NegOne
1820 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1821 auto NegOne = buildConstant(Res: Dst.getLLTTy(MRI: *getMRI()), Val: -1);
1822 return buildInstr(Opc: TargetOpcode::G_XOR, DstOps: {Dst}, SrcOps: {Src0, NegOne});
1823 }
1824
1825 /// Build and insert integer negation
1826 /// \p Zero = G_CONSTANT 0
1827 /// \p Res = G_SUB Zero, \p Op0
1828 MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) {
1829 auto Zero = buildConstant(Res: Dst.getLLTTy(MRI: *getMRI()), Val: 0);
1830 return buildInstr(Opc: TargetOpcode::G_SUB, DstOps: {Dst}, SrcOps: {Zero, Src0});
1831 }
1832
1833 /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1834 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1835 return buildInstr(Opc: TargetOpcode::G_CTPOP, DstOps: {Dst}, SrcOps: {Src0});
1836 }
1837
1838 /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1839 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1840 return buildInstr(Opc: TargetOpcode::G_CTLZ, DstOps: {Dst}, SrcOps: {Src0});
1841 }
1842
1843 /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1844 MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) {
1845 return buildInstr(Opc: TargetOpcode::G_CTLZ_ZERO_UNDEF, DstOps: {Dst}, SrcOps: {Src0});
1846 }
1847
1848 /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1849 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1850 return buildInstr(Opc: TargetOpcode::G_CTTZ, DstOps: {Dst}, SrcOps: {Src0});
1851 }
1852
1853 /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1854 MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) {
1855 return buildInstr(Opc: TargetOpcode::G_CTTZ_ZERO_UNDEF, DstOps: {Dst}, SrcOps: {Src0});
1856 }
1857
1858 /// Build and insert \p Dst = G_BSWAP \p Src0
1859 MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
1860 return buildInstr(Opc: TargetOpcode::G_BSWAP, DstOps: {Dst}, SrcOps: {Src0});
1861 }
1862
1863 /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1864 MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1865 const SrcOp &Src1,
1866 std::optional<unsigned> Flags = std::nullopt) {
1867 return buildInstr(Opc: TargetOpcode::G_FADD, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1868 }
1869
1870 /// Build and insert \p Res = G_STRICT_FADD \p Op0, \p Op1
1871 MachineInstrBuilder
1872 buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1873 std::optional<unsigned> Flags = std::nullopt) {
1874 return buildInstr(Opc: TargetOpcode::G_STRICT_FADD, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1875 }
1876
1877 /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1878 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1879 const SrcOp &Src1,
1880 std::optional<unsigned> Flags = std::nullopt) {
1881 return buildInstr(Opc: TargetOpcode::G_FSUB, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1882 }
1883
1884 /// Build and insert \p Res = G_FDIV \p Op0, \p Op1
1885 MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0,
1886 const SrcOp &Src1,
1887 std::optional<unsigned> Flags = std::nullopt) {
1888 return buildInstr(Opc: TargetOpcode::G_FDIV, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1889 }
1890
1891 /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1892 MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1893 const SrcOp &Src1, const SrcOp &Src2,
1894 std::optional<unsigned> Flags = std::nullopt) {
1895 return buildInstr(Opc: TargetOpcode::G_FMA, DstOps: {Dst}, SrcOps: {Src0, Src1, Src2}, Flags);
1896 }
1897
1898 /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1899 MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1900 const SrcOp &Src1, const SrcOp &Src2,
1901 std::optional<unsigned> Flags = std::nullopt) {
1902 return buildInstr(Opc: TargetOpcode::G_FMAD, DstOps: {Dst}, SrcOps: {Src0, Src1, Src2}, Flags);
1903 }
1904
1905 /// Build and insert \p Res = G_FNEG \p Op0
1906 MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1907 std::optional<unsigned> Flags = std::nullopt) {
1908 return buildInstr(Opc: TargetOpcode::G_FNEG, DstOps: {Dst}, SrcOps: {Src0}, Flags);
1909 }
1910
1911 /// Build and insert \p Res = G_FABS \p Op0
1912 MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1913 std::optional<unsigned> Flags = std::nullopt) {
1914 return buildInstr(Opc: TargetOpcode::G_FABS, DstOps: {Dst}, SrcOps: {Src0}, Flags);
1915 }
1916
1917 /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1918 MachineInstrBuilder
1919 buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0,
1920 std::optional<unsigned> Flags = std::nullopt) {
1921 return buildInstr(Opc: TargetOpcode::G_FCANONICALIZE, DstOps: {Dst}, SrcOps: {Src0}, Flags);
1922 }
1923
1924 /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0
1925 MachineInstrBuilder
1926 buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0,
1927 std::optional<unsigned> Flags = std::nullopt) {
1928 return buildInstr(Opc: TargetOpcode::G_INTRINSIC_TRUNC, DstOps: {Dst}, SrcOps: {Src0}, Flags);
1929 }
1930
1931 /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
1932 MachineInstrBuilder
1933 buildFFloor(const DstOp &Dst, const SrcOp &Src0,
1934 std::optional<unsigned> Flags = std::nullopt) {
1935 return buildInstr(Opc: TargetOpcode::G_FFLOOR, DstOps: {Dst}, SrcOps: {Src0}, Flags);
1936 }
1937
1938 /// Build and insert \p Dst = G_FLOG \p Src
1939 MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src,
1940 std::optional<unsigned> Flags = std::nullopt) {
1941 return buildInstr(Opc: TargetOpcode::G_FLOG, DstOps: {Dst}, SrcOps: {Src}, Flags);
1942 }
1943
1944 /// Build and insert \p Dst = G_FLOG2 \p Src
1945 MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src,
1946 std::optional<unsigned> Flags = std::nullopt) {
1947 return buildInstr(Opc: TargetOpcode::G_FLOG2, DstOps: {Dst}, SrcOps: {Src}, Flags);
1948 }
1949
1950 /// Build and insert \p Dst = G_FEXP2 \p Src
1951 MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src,
1952 std::optional<unsigned> Flags = std::nullopt) {
1953 return buildInstr(Opc: TargetOpcode::G_FEXP2, DstOps: {Dst}, SrcOps: {Src}, Flags);
1954 }
1955
1956 /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1
1957 MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0,
1958 const SrcOp &Src1,
1959 std::optional<unsigned> Flags = std::nullopt) {
1960 return buildInstr(Opc: TargetOpcode::G_FPOW, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1961 }
1962
1963 /// Build and insert \p Dst = G_FLDEXP \p Src0, \p Src1
1964 MachineInstrBuilder
1965 buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1966 std::optional<unsigned> Flags = std::nullopt) {
1967 return buildInstr(Opc: TargetOpcode::G_FLDEXP, DstOps: {Dst}, SrcOps: {Src0, Src1}, Flags);
1968 }
1969
1970 /// Build and insert \p Fract, \p Exp = G_FFREXP \p Src
1971 MachineInstrBuilder
1972 buildFFrexp(const DstOp &Fract, const DstOp &Exp, const SrcOp &Src,
1973 std::optional<unsigned> Flags = std::nullopt) {
1974 return buildInstr(Opc: TargetOpcode::G_FFREXP, DstOps: {Fract, Exp}, SrcOps: {Src}, Flags);
1975 }
1976
1977 /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1978 MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0,
1979 const SrcOp &Src1) {
1980 return buildInstr(Opc: TargetOpcode::G_FCOPYSIGN, DstOps: {Dst}, SrcOps: {Src0, Src1});
1981 }
1982
1983 /// Build and insert \p Res = G_UITOFP \p Src0
1984 MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1985 return buildInstr(Opc: TargetOpcode::G_UITOFP, DstOps: {Dst}, SrcOps: {Src0});
1986 }
1987
1988 /// Build and insert \p Res = G_SITOFP \p Src0
1989 MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1990 return buildInstr(Opc: TargetOpcode::G_SITOFP, DstOps: {Dst}, SrcOps: {Src0});
1991 }
1992
1993 /// Build and insert \p Res = G_FPTOUI \p Src0
1994 MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1995 return buildInstr(Opc: TargetOpcode::G_FPTOUI, DstOps: {Dst}, SrcOps: {Src0});
1996 }
1997
1998 /// Build and insert \p Res = G_FPTOSI \p Src0
1999 MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
2000 return buildInstr(Opc: TargetOpcode::G_FPTOSI, DstOps: {Dst}, SrcOps: {Src0});
2001 }
2002
2003 /// Build and insert \p Dst = G_INTRINSIC_ROUNDEVEN \p Src0, \p Src1
2004 MachineInstrBuilder
2005 buildIntrinsicRoundeven(const DstOp &Dst, const SrcOp &Src0,
2006 std::optional<unsigned> Flags = std::nullopt) {
2007 return buildInstr(Opc: TargetOpcode::G_INTRINSIC_ROUNDEVEN, DstOps: {Dst}, SrcOps: {Src0},
2008 Flags);
2009 }
2010
2011 /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
2012 MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
2013 const SrcOp &Src1) {
2014 return buildInstr(Opc: TargetOpcode::G_SMIN, DstOps: {Dst}, SrcOps: {Src0, Src1});
2015 }
2016
2017 /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
2018 MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
2019 const SrcOp &Src1) {
2020 return buildInstr(Opc: TargetOpcode::G_SMAX, DstOps: {Dst}, SrcOps: {Src0, Src1});
2021 }
2022
2023 /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
2024 MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
2025 const SrcOp &Src1) {
2026 return buildInstr(Opc: TargetOpcode::G_UMIN, DstOps: {Dst}, SrcOps: {Src0, Src1});
2027 }
2028
2029 /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
2030 MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
2031 const SrcOp &Src1) {
2032 return buildInstr(Opc: TargetOpcode::G_UMAX, DstOps: {Dst}, SrcOps: {Src0, Src1});
2033 }
2034
2035 /// Build and insert \p Dst = G_ABS \p Src
2036 MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) {
2037 return buildInstr(Opc: TargetOpcode::G_ABS, DstOps: {Dst}, SrcOps: {Src});
2038 }
2039
2040 /// Build and insert \p Res = G_JUMP_TABLE \p JTI
2041 ///
2042 /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
2043 /// the jump table index \p JTI.
2044 ///
2045 /// \return a MachineInstrBuilder for the newly created instruction.
2046 MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
2047
2048 /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn
2049 ///
2050 /// \p ScalarIn is the scalar accumulator input to start the sequential
2051 /// reduction operation of \p VecIn.
2052 MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst,
2053 const SrcOp &ScalarIn,
2054 const SrcOp &VecIn) {
2055 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_SEQ_FADD, DstOps: {Dst},
2056 SrcOps: {ScalarIn, {VecIn}});
2057 }
2058
2059 /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn
2060 ///
2061 /// \p ScalarIn is the scalar accumulator input to start the sequential
2062 /// reduction operation of \p VecIn.
2063 MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst,
2064 const SrcOp &ScalarIn,
2065 const SrcOp &VecIn) {
2066 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_SEQ_FMUL, DstOps: {Dst},
2067 SrcOps: {ScalarIn, {VecIn}});
2068 }
2069
2070 /// Build and insert \p Res = G_VECREDUCE_FADD \p Src
2071 ///
2072 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
2073 /// \p VecIn.
2074 MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst,
2075 const SrcOp &ScalarIn,
2076 const SrcOp &VecIn) {
2077 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FADD, DstOps: {Dst}, SrcOps: {ScalarIn, VecIn});
2078 }
2079
2080 /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src
2081 ///
2082 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
2083 /// \p VecIn.
2084 MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst,
2085 const SrcOp &ScalarIn,
2086 const SrcOp &VecIn) {
2087 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMUL, DstOps: {Dst}, SrcOps: {ScalarIn, VecIn});
2088 }
2089
2090 /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src
2091 MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src) {
2092 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMAX, DstOps: {Dst}, SrcOps: {Src});
2093 }
2094
2095 /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src
2096 MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src) {
2097 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMIN, DstOps: {Dst}, SrcOps: {Src});
2098 }
2099
2100 /// Build and insert \p Res = G_VECREDUCE_FMAXIMUM \p Src
2101 MachineInstrBuilder buildVecReduceFMaximum(const DstOp &Dst,
2102 const SrcOp &Src) {
2103 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMAXIMUM, DstOps: {Dst}, SrcOps: {Src});
2104 }
2105
2106 /// Build and insert \p Res = G_VECREDUCE_FMINIMUM \p Src
2107 MachineInstrBuilder buildVecReduceFMinimum(const DstOp &Dst,
2108 const SrcOp &Src) {
2109 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_FMINIMUM, DstOps: {Dst}, SrcOps: {Src});
2110 }
2111
2112 /// Build and insert \p Res = G_VECREDUCE_ADD \p Src
2113 MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src) {
2114 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_ADD, DstOps: {Dst}, SrcOps: {Src});
2115 }
2116
2117 /// Build and insert \p Res = G_VECREDUCE_MUL \p Src
2118 MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src) {
2119 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_MUL, DstOps: {Dst}, SrcOps: {Src});
2120 }
2121
2122 /// Build and insert \p Res = G_VECREDUCE_AND \p Src
2123 MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src) {
2124 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_AND, DstOps: {Dst}, SrcOps: {Src});
2125 }
2126
2127 /// Build and insert \p Res = G_VECREDUCE_OR \p Src
2128 MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src) {
2129 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_OR, DstOps: {Dst}, SrcOps: {Src});
2130 }
2131
2132 /// Build and insert \p Res = G_VECREDUCE_XOR \p Src
2133 MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src) {
2134 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_XOR, DstOps: {Dst}, SrcOps: {Src});
2135 }
2136
2137 /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src
2138 MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src) {
2139 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_SMAX, DstOps: {Dst}, SrcOps: {Src});
2140 }
2141
2142 /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src
2143 MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src) {
2144 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_SMIN, DstOps: {Dst}, SrcOps: {Src});
2145 }
2146
2147 /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src
2148 MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src) {
2149 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_UMAX, DstOps: {Dst}, SrcOps: {Src});
2150 }
2151
2152 /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src
2153 MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src) {
2154 return buildInstr(Opc: TargetOpcode::G_VECREDUCE_UMIN, DstOps: {Dst}, SrcOps: {Src});
2155 }
2156
2157 /// Build and insert G_MEMCPY or G_MEMMOVE
2158 MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr,
2159 const SrcOp &SrcPtr,
2160 const SrcOp &Size,
2161 MachineMemOperand &DstMMO,
2162 MachineMemOperand &SrcMMO) {
2163 auto MIB = buildInstr(
2164 Opc: Opcode, DstOps: {}, SrcOps: {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)});
2165 MIB.addMemOperand(MMO: &DstMMO);
2166 MIB.addMemOperand(MMO: &SrcMMO);
2167 return MIB;
2168 }
2169
2170 MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr,
2171 const SrcOp &Size, MachineMemOperand &DstMMO,
2172 MachineMemOperand &SrcMMO) {
2173 return buildMemTransferInst(Opcode: TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size,
2174 DstMMO, SrcMMO);
2175 }
2176
2177 /// Build and insert G_TRAP or G_DEBUGTRAP
2178 MachineInstrBuilder buildTrap(bool Debug = false) {
2179 return buildInstr(Opcode: Debug ? TargetOpcode::G_DEBUGTRAP : TargetOpcode::G_TRAP);
2180 }
2181
2182 /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width.
2183 MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src,
2184 const SrcOp &LSB, const SrcOp &Width) {
2185 return buildInstr(Opc: TargetOpcode::G_SBFX, DstOps: {Dst}, SrcOps: {Src, LSB, Width});
2186 }
2187
2188 /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.
2189 MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src,
2190 const SrcOp &LSB, const SrcOp &Width) {
2191 return buildInstr(Opc: TargetOpcode::G_UBFX, DstOps: {Dst}, SrcOps: {Src, LSB, Width});
2192 }
2193
2194 /// Build and insert \p Dst = G_ROTR \p Src, \p Amt
2195 MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src,
2196 const SrcOp &Amt) {
2197 return buildInstr(Opc: TargetOpcode::G_ROTR, DstOps: {Dst}, SrcOps: {Src, Amt});
2198 }
2199
2200 /// Build and insert \p Dst = G_ROTL \p Src, \p Amt
2201 MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src,
2202 const SrcOp &Amt) {
2203 return buildInstr(Opc: TargetOpcode::G_ROTL, DstOps: {Dst}, SrcOps: {Src, Amt});
2204 }
2205
2206 /// Build and insert \p Dst = G_BITREVERSE \p Src
2207 MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src) {
2208 return buildInstr(Opc: TargetOpcode::G_BITREVERSE, DstOps: {Dst}, SrcOps: {Src});
2209 }
2210
2211 /// Build and insert \p Dst = G_GET_FPENV
2212 MachineInstrBuilder buildGetFPEnv(const DstOp &Dst) {
2213 return buildInstr(Opc: TargetOpcode::G_GET_FPENV, DstOps: {Dst}, SrcOps: {});
2214 }
2215
2216 /// Build and insert G_SET_FPENV \p Src
2217 MachineInstrBuilder buildSetFPEnv(const SrcOp &Src) {
2218 return buildInstr(Opc: TargetOpcode::G_SET_FPENV, DstOps: {}, SrcOps: {Src});
2219 }
2220
2221 /// Build and insert G_RESET_FPENV
2222 MachineInstrBuilder buildResetFPEnv() {
2223 return buildInstr(Opc: TargetOpcode::G_RESET_FPENV, DstOps: {}, SrcOps: {});
2224 }
2225
2226 /// Build and insert \p Dst = G_GET_FPMODE
2227 MachineInstrBuilder buildGetFPMode(const DstOp &Dst) {
2228 return buildInstr(Opc: TargetOpcode::G_GET_FPMODE, DstOps: {Dst}, SrcOps: {});
2229 }
2230
2231 /// Build and insert G_SET_FPMODE \p Src
2232 MachineInstrBuilder buildSetFPMode(const SrcOp &Src) {
2233 return buildInstr(Opc: TargetOpcode::G_SET_FPMODE, DstOps: {}, SrcOps: {Src});
2234 }
2235
2236 /// Build and insert G_RESET_FPMODE
2237 MachineInstrBuilder buildResetFPMode() {
2238 return buildInstr(Opc: TargetOpcode::G_RESET_FPMODE, DstOps: {}, SrcOps: {});
2239 }
2240
2241 virtual MachineInstrBuilder
2242 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
2243 std::optional<unsigned> Flags = std::nullopt);
2244};
2245
2246} // End namespace llvm.
2247#endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
2248