1//===- Construction of codegen pass pipelines ------------------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// Interfaces for producing common pass manager configurations.
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_PASSES_CODEGENPASSBUILDER_H
15#define LLVM_PASSES_CODEGENPASSBUILDER_H
16
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/Analysis/AliasAnalysis.h"
20#include "llvm/Analysis/BasicAliasAnalysis.h"
21#include "llvm/Analysis/ProfileSummaryInfo.h"
22#include "llvm/Analysis/ScopedNoAliasAA.h"
23#include "llvm/Analysis/TargetTransformInfo.h"
24#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
25#include "llvm/CodeGen/AssignmentTrackingAnalysis.h"
26#include "llvm/CodeGen/CallBrPrepare.h"
27#include "llvm/CodeGen/CodeGenPrepare.h"
28#include "llvm/CodeGen/DeadMachineInstructionElim.h"
29#include "llvm/CodeGen/DwarfEHPrepare.h"
30#include "llvm/CodeGen/ExpandMemCmp.h"
31#include "llvm/CodeGen/ExpandReductions.h"
32#include "llvm/CodeGen/FinalizeISel.h"
33#include "llvm/CodeGen/GCMetadata.h"
34#include "llvm/CodeGen/GlobalMerge.h"
35#include "llvm/CodeGen/IndirectBrExpand.h"
36#include "llvm/CodeGen/InterleavedAccess.h"
37#include "llvm/CodeGen/InterleavedLoadCombine.h"
38#include "llvm/CodeGen/JMCInstrumenter.h"
39#include "llvm/CodeGen/LiveIntervals.h"
40#include "llvm/CodeGen/LocalStackSlotAllocation.h"
41#include "llvm/CodeGen/LowerEmuTLS.h"
42#include "llvm/CodeGen/MIRPrinter.h"
43#include "llvm/CodeGen/MachineFunctionAnalysis.h"
44#include "llvm/CodeGen/MachineModuleInfo.h"
45#include "llvm/CodeGen/MachinePassManager.h"
46#include "llvm/CodeGen/PHIElimination.h"
47#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
48#include "llvm/CodeGen/RegAllocFast.h"
49#include "llvm/CodeGen/ReplaceWithVeclib.h"
50#include "llvm/CodeGen/SafeStack.h"
51#include "llvm/CodeGen/SelectOptimize.h"
52#include "llvm/CodeGen/ShadowStackGCLowering.h"
53#include "llvm/CodeGen/SjLjEHPrepare.h"
54#include "llvm/CodeGen/StackProtector.h"
55#include "llvm/CodeGen/TargetPassConfig.h"
56#include "llvm/CodeGen/TwoAddressInstructionPass.h"
57#include "llvm/CodeGen/UnreachableBlockElim.h"
58#include "llvm/CodeGen/WasmEHPrepare.h"
59#include "llvm/CodeGen/WinEHPrepare.h"
60#include "llvm/IR/PassManager.h"
61#include "llvm/IR/Verifier.h"
62#include "llvm/IRPrinter/IRPrintingPasses.h"
63#include "llvm/MC/MCAsmInfo.h"
64#include "llvm/MC/MCTargetOptions.h"
65#include "llvm/Support/CodeGen.h"
66#include "llvm/Support/Debug.h"
67#include "llvm/Support/Error.h"
68#include "llvm/Support/ErrorHandling.h"
69#include "llvm/Target/CGPassBuilderOption.h"
70#include "llvm/Target/TargetMachine.h"
71#include "llvm/Transforms/CFGuard.h"
72#include "llvm/Transforms/Scalar/ConstantHoisting.h"
73#include "llvm/Transforms/Scalar/LoopPassManager.h"
74#include "llvm/Transforms/Scalar/LoopStrengthReduce.h"
75#include "llvm/Transforms/Scalar/LowerConstantIntrinsics.h"
76#include "llvm/Transforms/Scalar/MergeICmps.h"
77#include "llvm/Transforms/Scalar/PartiallyInlineLibCalls.h"
78#include "llvm/Transforms/Scalar/ScalarizeMaskedMemIntrin.h"
79#include "llvm/Transforms/Utils/EntryExitInstrumenter.h"
80#include "llvm/Transforms/Utils/LowerInvoke.h"
81#include <cassert>
82#include <type_traits>
83#include <utility>
84
85namespace llvm {
86
87// FIXME: Dummy target independent passes definitions that have not yet been
88// ported to new pass manager. Once they do, remove these.
89#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME) \
90 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
91 template <typename... Ts> PASS_NAME(Ts &&...) {} \
92 PreservedAnalyses run(Function &, FunctionAnalysisManager &) { \
93 return PreservedAnalyses::all(); \
94 } \
95 };
96#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME) \
97 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
98 template <typename... Ts> PASS_NAME(Ts &&...) {} \
99 PreservedAnalyses run(Module &, ModuleAnalysisManager &) { \
100 return PreservedAnalyses::all(); \
101 } \
102 };
103#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME) \
104 struct PASS_NAME : public PassInfoMixin<PASS_NAME> { \
105 template <typename... Ts> PASS_NAME(Ts &&...) {} \
106 PreservedAnalyses run(MachineFunction &, \
107 MachineFunctionAnalysisManager &) { \
108 return PreservedAnalyses::all(); \
109 } \
110 };
111#include "llvm/Passes/MachinePassRegistry.def"
112
113/// This class provides access to building LLVM's passes.
114///
115/// Its members provide the baseline state available to passes during their
116/// construction. The \c MachinePassRegistry.def file specifies how to construct
117/// all of the built-in passes, and those may reference these members during
118/// construction.
119template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
120public:
121 explicit CodeGenPassBuilder(TargetMachineT &TM,
122 const CGPassBuilderOption &Opts,
123 PassInstrumentationCallbacks *PIC)
124 : TM(TM), Opt(Opts), PIC(PIC) {
125 // Target could set CGPassBuilderOption::MISchedPostRA to true to achieve
126 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID)
127
128 // Target should override TM.Options.EnableIPRA in their target-specific
129 // LLVMTM ctor. See TargetMachine::setGlobalISel for example.
130 if (Opt.EnableIPRA)
131 TM.Options.EnableIPRA = *Opt.EnableIPRA;
132
133 if (Opt.EnableGlobalISelAbort)
134 TM.Options.GlobalISelAbort = *Opt.EnableGlobalISelAbort;
135
136 if (!Opt.OptimizeRegAlloc)
137 Opt.OptimizeRegAlloc = getOptLevel() != CodeGenOptLevel::None;
138 }
139
140 Error buildPipeline(ModulePassManager &MPM, raw_pwrite_stream &Out,
141 raw_pwrite_stream *DwoOut,
142 CodeGenFileType FileType) const;
143
144 PassInstrumentationCallbacks *getPassInstrumentationCallbacks() const {
145 return PIC;
146 }
147
148protected:
149 template <typename PassT>
150 using has_required_t = decltype(std::declval<PassT &>().isRequired());
151
152 template <typename PassT>
153 using is_module_pass_t = decltype(std::declval<PassT &>().run(
154 std::declval<Module &>(), std::declval<ModuleAnalysisManager &>()));
155
156 template <typename PassT>
157 using is_function_pass_t = decltype(std::declval<PassT &>().run(
158 std::declval<Function &>(), std::declval<FunctionAnalysisManager &>()));
159
160 template <typename PassT>
161 using is_machine_function_pass_t = decltype(std::declval<PassT &>().run(
162 std::declval<MachineFunction &>(),
163 std::declval<MachineFunctionAnalysisManager &>()));
164
165 // Function object to maintain state while adding codegen IR passes.
166 // TODO: add a Function -> MachineFunction adaptor and merge
167 // AddIRPass/AddMachinePass so we can have a function pipeline that runs both
168 // function passes and machine function passes.
169 class AddIRPass {
170 public:
171 AddIRPass(ModulePassManager &MPM, const DerivedT &PB) : MPM(MPM), PB(PB) {}
172 ~AddIRPass() {
173 if (!FPM.isEmpty())
174 MPM.addPass(Pass: createModuleToFunctionPassAdaptor(Pass: std::move(FPM)));
175 }
176
177 template <typename PassT>
178 void operator()(PassT &&Pass, StringRef Name = PassT::name()) {
179 static_assert((is_detected<is_function_pass_t, PassT>::value ||
180 is_detected<is_module_pass_t, PassT>::value) &&
181 "Only module pass and function pass are supported.");
182 bool Required = false;
183 if constexpr (is_detected<has_required_t, PassT>::value)
184 Required = PassT::isRequired();
185 if (!PB.runBeforeAdding(Name) && !Required)
186 return;
187
188 // Add Function Pass
189 if constexpr (is_detected<is_function_pass_t, PassT>::value) {
190 FPM.addPass(std::forward<PassT>(Pass));
191 } else {
192 // Add Module Pass
193 if (!FPM.isEmpty()) {
194 MPM.addPass(Pass: createModuleToFunctionPassAdaptor(Pass: std::move(FPM)));
195 FPM = FunctionPassManager();
196 }
197
198 MPM.addPass(std::forward<PassT>(Pass));
199 }
200 }
201
202 private:
203 ModulePassManager &MPM;
204 FunctionPassManager FPM;
205 const DerivedT &PB;
206 };
207
208 // Function object to maintain state while adding codegen machine passes.
209 class AddMachinePass {
210 public:
211 AddMachinePass(ModulePassManager &MPM, const DerivedT &PB)
212 : MPM(MPM), PB(PB) {}
213 ~AddMachinePass() {
214 if (!MFPM.isEmpty()) {
215 FunctionPassManager FPM;
216 FPM.addPass(
217 Pass: createFunctionToMachineFunctionPassAdaptor(Pass: std::move(MFPM)));
218 FPM.addPass(Pass: InvalidateAnalysisPass<MachineFunctionAnalysis>());
219 MPM.addPass(Pass: createModuleToFunctionPassAdaptor(Pass: std::move(FPM)));
220 }
221 }
222
223 template <typename PassT>
224 void operator()(PassT &&Pass, bool Force = false,
225 StringRef Name = PassT::name()) {
226 static_assert((is_detected<is_machine_function_pass_t, PassT>::value ||
227 is_detected<is_module_pass_t, PassT>::value) &&
228 "Only module pass and function pass are supported.");
229
230 if (!Force && !PB.runBeforeAdding(Name))
231 return;
232
233 // Add Function Pass
234 if constexpr (is_detected<is_machine_function_pass_t, PassT>::value) {
235 MFPM.addPass(std::forward<PassT>(Pass));
236 } else {
237 // Add Module Pass
238 if (!MFPM.isEmpty()) {
239 MPM.addPass(Pass: createModuleToFunctionPassAdaptor(
240 Pass: createFunctionToMachineFunctionPassAdaptor(Pass: std::move(MFPM))));
241 MFPM = MachineFunctionPassManager();
242 }
243
244 MPM.addPass(std::forward<PassT>(Pass));
245 }
246
247 for (auto &C : PB.AfterCallbacks)
248 C(Name, MFPM);
249 }
250
251 private:
252 ModulePassManager &MPM;
253 MachineFunctionPassManager MFPM;
254 const DerivedT &PB;
255 };
256
257 TargetMachineT &TM;
258 CGPassBuilderOption Opt;
259 PassInstrumentationCallbacks *PIC;
260
261 template <typename TMC> TMC &getTM() const { return static_cast<TMC &>(TM); }
262 CodeGenOptLevel getOptLevel() const { return TM.getOptLevel(); }
263
264 /// Check whether or not GlobalISel should abort on error.
265 /// When this is disabled, GlobalISel will fall back on SDISel instead of
266 /// erroring out.
267 bool isGlobalISelAbortEnabled() const {
268 return TM.Options.GlobalISelAbort == GlobalISelAbortMode::Enable;
269 }
270
271 /// Check whether or not a diagnostic should be emitted when GlobalISel
272 /// uses the fallback path. In other words, it will emit a diagnostic
273 /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
274 bool reportDiagnosticWhenGlobalISelFallback() const {
275 return TM.Options.GlobalISelAbort == GlobalISelAbortMode::DisableWithDiag;
276 }
277
278 /// addInstSelector - This method should install an instruction selector pass,
279 /// which converts from LLVM code to machine instructions.
280 Error addInstSelector(AddMachinePass &) const {
281 return make_error<StringError>(Args: "addInstSelector is not overridden",
282 Args: inconvertibleErrorCode());
283 }
284
285 /// Target can override this to add GlobalMergePass before all IR passes.
286 void addGlobalMergePass(AddIRPass &) const {}
287
288 /// Add passes that optimize instruction level parallelism for out-of-order
289 /// targets. These passes are run while the machine code is still in SSA
290 /// form, so they can use MachineTraceMetrics to control their heuristics.
291 ///
292 /// All passes added here should preserve the MachineDominatorTree,
293 /// MachineLoopInfo, and MachineTraceMetrics analyses.
294 void addILPOpts(AddMachinePass &) const {}
295
296 /// This method may be implemented by targets that want to run passes
297 /// immediately before register allocation.
298 void addPreRegAlloc(AddMachinePass &) const {}
299
300 /// addPreRewrite - Add passes to the optimized register allocation pipeline
301 /// after register allocation is complete, but before virtual registers are
302 /// rewritten to physical registers.
303 ///
304 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
305 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
306 /// When these passes run, VirtRegMap contains legal physreg assignments for
307 /// all virtual registers.
308 ///
309 /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
310 /// be honored. This is also not generally used for the fast variant,
311 /// where the allocation and rewriting are done in one pass.
312 void addPreRewrite(AddMachinePass &) const {}
313
314 /// Add passes to be run immediately after virtual registers are rewritten
315 /// to physical registers.
316 void addPostRewrite(AddMachinePass &) const {}
317
318 /// This method may be implemented by targets that want to run passes after
319 /// register allocation pass pipeline but before prolog-epilog insertion.
320 void addPostRegAlloc(AddMachinePass &) const {}
321
322 /// This method may be implemented by targets that want to run passes after
323 /// prolog-epilog insertion and before the second instruction scheduling pass.
324 void addPreSched2(AddMachinePass &) const {}
325
326 /// This pass may be implemented by targets that want to run passes
327 /// immediately before machine code is emitted.
328 void addPreEmitPass(AddMachinePass &) const {}
329
330 /// Targets may add passes immediately before machine code is emitted in this
331 /// callback. This is called even later than `addPreEmitPass`.
332 // FIXME: Rename `addPreEmitPass` to something more sensible given its actual
333 // position and remove the `2` suffix here as this callback is what
334 // `addPreEmitPass` *should* be but in reality isn't.
335 void addPreEmitPass2(AddMachinePass &) const {}
336
337 /// {{@ For GlobalISel
338 ///
339
340 /// addPreISel - This method should add any "last minute" LLVM->LLVM
341 /// passes (which are run just before instruction selector).
342 void addPreISel(AddIRPass &) const {
343 llvm_unreachable("addPreISel is not overridden");
344 }
345
346 /// This method should install an IR translator pass, which converts from
347 /// LLVM code to machine instructions with possibly generic opcodes.
348 Error addIRTranslator(AddMachinePass &) const {
349 return make_error<StringError>(Args: "addIRTranslator is not overridden",
350 Args: inconvertibleErrorCode());
351 }
352
353 /// This method may be implemented by targets that want to run passes
354 /// immediately before legalization.
355 void addPreLegalizeMachineIR(AddMachinePass &) const {}
356
357 /// This method should install a legalize pass, which converts the instruction
358 /// sequence into one that can be selected by the target.
359 Error addLegalizeMachineIR(AddMachinePass &) const {
360 return make_error<StringError>(Args: "addLegalizeMachineIR is not overridden",
361 Args: inconvertibleErrorCode());
362 }
363
364 /// This method may be implemented by targets that want to run passes
365 /// immediately before the register bank selection.
366 void addPreRegBankSelect(AddMachinePass &) const {}
367
368 /// This method should install a register bank selector pass, which
369 /// assigns register banks to virtual registers without a register
370 /// class or register banks.
371 Error addRegBankSelect(AddMachinePass &) const {
372 return make_error<StringError>(Args: "addRegBankSelect is not overridden",
373 Args: inconvertibleErrorCode());
374 }
375
376 /// This method may be implemented by targets that want to run passes
377 /// immediately before the (global) instruction selection.
378 void addPreGlobalInstructionSelect(AddMachinePass &) const {}
379
380 /// This method should install a (global) instruction selector pass, which
381 /// converts possibly generic instructions to fully target-specific
382 /// instructions, thereby constraining all generic virtual registers to
383 /// register classes.
384 Error addGlobalInstructionSelect(AddMachinePass &) const {
385 return make_error<StringError>(
386 Args: "addGlobalInstructionSelect is not overridden",
387 Args: inconvertibleErrorCode());
388 }
389 /// @}}
390
391 /// High level function that adds all passes necessary to go from llvm IR
392 /// representation to the MI representation.
393 /// Adds IR based lowering and target specific optimization passes and finally
394 /// the core instruction selection passes.
395 void addISelPasses(AddIRPass &) const;
396
397 /// Add the actual instruction selection passes. This does not include
398 /// preparation passes on IR.
399 Error addCoreISelPasses(AddMachinePass &) const;
400
401 /// Add the complete, standard set of LLVM CodeGen passes.
402 /// Fully developed targets will not generally override this.
403 Error addMachinePasses(AddMachinePass &) const;
404
405 /// Add passes to lower exception handling for the code generator.
406 void addPassesToHandleExceptions(AddIRPass &) const;
407
408 /// Add common target configurable passes that perform LLVM IR to IR
409 /// transforms following machine independent optimization.
410 void addIRPasses(AddIRPass &) const;
411
412 /// Add pass to prepare the LLVM IR for code generation. This should be done
413 /// before exception handling preparation passes.
414 void addCodeGenPrepare(AddIRPass &) const;
415
416 /// Add common passes that perform LLVM IR to IR transforms in preparation for
417 /// instruction selection.
418 void addISelPrepare(AddIRPass &) const;
419
420 /// Methods with trivial inline returns are convenient points in the common
421 /// codegen pass pipeline where targets may insert passes. Methods with
422 /// out-of-line standard implementations are major CodeGen stages called by
423 /// addMachinePasses. Some targets may override major stages when inserting
424 /// passes is insufficient, but maintaining overriden stages is more work.
425 ///
426
427 /// addMachineSSAOptimization - Add standard passes that optimize machine
428 /// instructions in SSA form.
429 void addMachineSSAOptimization(AddMachinePass &) const;
430
431 /// addFastRegAlloc - Add the minimum set of target-independent passes that
432 /// are required for fast register allocation.
433 Error addFastRegAlloc(AddMachinePass &) const;
434
435 /// addOptimizedRegAlloc - Add passes related to register allocation.
436 /// LLVMTargetMachine provides standard regalloc passes for most targets.
437 void addOptimizedRegAlloc(AddMachinePass &) const;
438
439 /// Add passes that optimize machine instructions after register allocation.
440 void addMachineLateOptimization(AddMachinePass &) const;
441
442 /// addGCPasses - Add late codegen passes that analyze code for garbage
443 /// collection. This should return true if GC info should be printed after
444 /// these passes.
445 void addGCPasses(AddMachinePass &) const {}
446
447 /// Add standard basic block placement passes.
448 void addBlockPlacement(AddMachinePass &) const;
449
450 using CreateMCStreamer =
451 std::function<Expected<std::unique_ptr<MCStreamer>>(MCContext &)>;
452 void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const {
453 llvm_unreachable("addAsmPrinter is not overridden");
454 }
455
456 /// Utilities for targets to add passes to the pass manager.
457 ///
458
459 /// createTargetRegisterAllocator - Create the register allocator pass for
460 /// this target at the current optimization level.
461 void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const;
462
463 /// addMachinePasses helper to create the target-selected or overriden
464 /// regalloc pass.
465 void addRegAllocPass(AddMachinePass &, bool Optimized) const;
466
467 /// Add core register alloator passes which do the actual register assignment
468 /// and rewriting. \returns true if any passes were added.
469 Error addRegAssignmentFast(AddMachinePass &) const;
470 Error addRegAssignmentOptimized(AddMachinePass &) const;
471
472 /// Allow the target to disable a specific pass by default.
473 /// Backend can declare unwanted passes in constructor.
474 template <typename... PassTs> void disablePass() {
475 BeforeCallbacks.emplace_back(
476 [](StringRef Name) { return ((Name != PassTs::name()) && ...); });
477 }
478
479 /// Insert InsertedPass pass after TargetPass pass.
480 /// Only machine function passes are supported.
481 template <typename TargetPassT, typename InsertedPassT>
482 void insertPass(InsertedPassT &&Pass) {
483 AfterCallbacks.emplace_back(
484 [&](StringRef Name, MachineFunctionPassManager &MFPM) mutable {
485 if (Name == TargetPassT::name())
486 MFPM.addPass(std::forward<InsertedPassT>(Pass));
487 });
488 }
489
490private:
491 DerivedT &derived() { return static_cast<DerivedT &>(*this); }
492 const DerivedT &derived() const {
493 return static_cast<const DerivedT &>(*this);
494 }
495
496 bool runBeforeAdding(StringRef Name) const {
497 bool ShouldAdd = true;
498 for (auto &C : BeforeCallbacks)
499 ShouldAdd &= C(Name);
500 return ShouldAdd;
501 }
502
503 void setStartStopPasses(const TargetPassConfig::StartStopInfo &Info) const;
504
505 Error verifyStartStop(const TargetPassConfig::StartStopInfo &Info) const;
506
507 mutable SmallVector<llvm::unique_function<bool(StringRef)>, 4>
508 BeforeCallbacks;
509 mutable SmallVector<
510 llvm::unique_function<void(StringRef, MachineFunctionPassManager &)>, 4>
511 AfterCallbacks;
512
513 /// Helper variable for `-start-before/-start-after/-stop-before/-stop-after`
514 mutable bool Started = true;
515 mutable bool Stopped = true;
516};
517
518template <typename Derived, typename TargetMachineT>
519Error CodeGenPassBuilder<Derived, TargetMachineT>::buildPipeline(
520 ModulePassManager &MPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
521 CodeGenFileType FileType) const {
522 auto StartStopInfo = TargetPassConfig::getStartStopInfo(PIC&: *PIC);
523 if (!StartStopInfo)
524 return StartStopInfo.takeError();
525 setStartStopPasses(*StartStopInfo);
526
527 bool PrintAsm = TargetPassConfig::willCompleteCodeGenPipeline();
528 bool PrintMIR = !PrintAsm && FileType != CodeGenFileType::Null;
529
530 {
531 AddIRPass addIRPass(MPM, derived());
532 addIRPass(RequireAnalysisPass<MachineModuleAnalysis, Module>());
533 addIRPass(RequireAnalysisPass<ProfileSummaryAnalysis, Module>());
534 addIRPass(RequireAnalysisPass<CollectorMetadataAnalysis, Module>());
535 addISelPasses(addIRPass);
536 }
537
538 AddMachinePass addPass(MPM, derived());
539
540 if (PrintMIR)
541 addPass(PrintMIRPreparePass(Out), /*Force=*/true);
542
543 if (auto Err = addCoreISelPasses(addPass))
544 return std::move(Err);
545
546 if (auto Err = derived().addMachinePasses(addPass))
547 return std::move(Err);
548
549 if (PrintAsm) {
550 derived().addAsmPrinter(
551 addPass, [this, &Out, DwoOut, FileType](MCContext &Ctx) {
552 return this->TM.createMCStreamer(Out, DwoOut, FileType, Ctx);
553 });
554 }
555
556 if (PrintMIR)
557 addPass(PrintMIRPass(Out), /*Force=*/true);
558
559 return verifyStartStop(Info: *StartStopInfo);
560}
561
562template <typename Derived, typename TargetMachineT>
563void CodeGenPassBuilder<Derived, TargetMachineT>::setStartStopPasses(
564 const TargetPassConfig::StartStopInfo &Info) const {
565 if (!Info.StartPass.empty()) {
566 Started = false;
567 BeforeCallbacks.emplace_back([this, &Info, AfterFlag = Info.StartAfter,
568 Count = 0u](StringRef ClassName) mutable {
569 if (Count == Info.StartInstanceNum) {
570 if (AfterFlag) {
571 AfterFlag = false;
572 Started = true;
573 }
574 return Started;
575 }
576
577 auto PassName = PIC->getPassNameForClassName(ClassName);
578 if (Info.StartPass == PassName && ++Count == Info.StartInstanceNum)
579 Started = !Info.StartAfter;
580
581 return Started;
582 });
583 }
584
585 if (!Info.StopPass.empty()) {
586 Stopped = false;
587 BeforeCallbacks.emplace_back([this, &Info, AfterFlag = Info.StopAfter,
588 Count = 0u](StringRef ClassName) mutable {
589 if (Count == Info.StopInstanceNum) {
590 if (AfterFlag) {
591 AfterFlag = false;
592 Stopped = true;
593 }
594 return !Stopped;
595 }
596
597 auto PassName = PIC->getPassNameForClassName(ClassName);
598 if (Info.StopPass == PassName && ++Count == Info.StopInstanceNum)
599 Stopped = !Info.StopAfter;
600 return !Stopped;
601 });
602 }
603}
604
605template <typename Derived, typename TargetMachineT>
606Error CodeGenPassBuilder<Derived, TargetMachineT>::verifyStartStop(
607 const TargetPassConfig::StartStopInfo &Info) const {
608 if (Started && Stopped)
609 return Error::success();
610
611 if (!Started)
612 return make_error<StringError>(
613 Args: "Can't find start pass \"" +
614 PIC->getPassNameForClassName(ClassName: Info.StartPass) + "\".",
615 Args: std::make_error_code(e: std::errc::invalid_argument));
616 if (!Stopped)
617 return make_error<StringError>(
618 Args: "Can't find stop pass \"" +
619 PIC->getPassNameForClassName(ClassName: Info.StopPass) + "\".",
620 Args: std::make_error_code(e: std::errc::invalid_argument));
621 return Error::success();
622}
623
624template <typename Derived, typename TargetMachineT>
625void CodeGenPassBuilder<Derived, TargetMachineT>::addISelPasses(
626 AddIRPass &addPass) const {
627 derived().addGlobalMergePass(addPass);
628 if (TM.useEmulatedTLS())
629 addPass(LowerEmuTLSPass());
630
631 addPass(PreISelIntrinsicLoweringPass(TM));
632
633 derived().addIRPasses(addPass);
634 derived().addCodeGenPrepare(addPass);
635 addPassesToHandleExceptions(addPass);
636 derived().addISelPrepare(addPass);
637}
638
639/// Add common target configurable passes that perform LLVM IR to IR transforms
640/// following machine independent optimization.
641template <typename Derived, typename TargetMachineT>
642void CodeGenPassBuilder<Derived, TargetMachineT>::addIRPasses(
643 AddIRPass &addPass) const {
644 // Before running any passes, run the verifier to determine if the input
645 // coming from the front-end and/or optimizer is valid.
646 if (!Opt.DisableVerify)
647 addPass(VerifierPass());
648
649 // Run loop strength reduction before anything else.
650 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableLSR) {
651 addPass(createFunctionToLoopPassAdaptor(Pass: LoopStrengthReducePass(),
652 /*UseMemorySSA=*/UseMemorySSA: true));
653 // FIXME: use -stop-after so we could remove PrintLSR
654 if (Opt.PrintLSR)
655 addPass(PrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
656 }
657
658 if (getOptLevel() != CodeGenOptLevel::None) {
659 // The MergeICmpsPass tries to create memcmp calls by grouping sequences of
660 // loads and compares. ExpandMemCmpPass then tries to expand those calls
661 // into optimally-sized loads and compares. The transforms are enabled by a
662 // target lowering hook.
663 if (!Opt.DisableMergeICmps)
664 addPass(MergeICmpsPass());
665 addPass(ExpandMemCmpPass(&TM));
666 }
667
668 // Run GC lowering passes for builtin collectors
669 // TODO: add a pass insertion point here
670 addPass(GCLoweringPass());
671 addPass(ShadowStackGCLoweringPass());
672 addPass(LowerConstantIntrinsicsPass());
673
674 // Make sure that no unreachable blocks are instruction selected.
675 addPass(UnreachableBlockElimPass());
676
677 // Prepare expensive constants for SelectionDAG.
678 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableConstantHoisting)
679 addPass(ConstantHoistingPass());
680
681 // Replace calls to LLVM intrinsics (e.g., exp, log) operating on vector
682 // operands with calls to the corresponding functions in a vector library.
683 if (getOptLevel() != CodeGenOptLevel::None)
684 addPass(ReplaceWithVeclib());
685
686 if (getOptLevel() != CodeGenOptLevel::None &&
687 !Opt.DisablePartialLibcallInlining)
688 addPass(PartiallyInlineLibCallsPass());
689
690 // Instrument function entry and exit, e.g. with calls to mcount().
691 addPass(EntryExitInstrumenterPass(/*PostInlining=*/true));
692
693 // Add scalarization of target's unsupported masked memory intrinsics pass.
694 // the unsupported intrinsic will be replaced with a chain of basic blocks,
695 // that stores/loads element one-by-one if the appropriate mask bit is set.
696 addPass(ScalarizeMaskedMemIntrinPass());
697
698 // Expand reduction intrinsics into shuffle sequences if the target wants to.
699 addPass(ExpandReductionsPass());
700
701 // Convert conditional moves to conditional jumps when profitable.
702 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableSelectOptimize)
703 addPass(SelectOptimizePass(&TM));
704}
705
706/// Turn exception handling constructs into something the code generators can
707/// handle.
708template <typename Derived, typename TargetMachineT>
709void CodeGenPassBuilder<Derived, TargetMachineT>::addPassesToHandleExceptions(
710 AddIRPass &addPass) const {
711 const MCAsmInfo *MCAI = TM.getMCAsmInfo();
712 assert(MCAI && "No MCAsmInfo");
713 switch (MCAI->getExceptionHandlingType()) {
714 case ExceptionHandling::SjLj:
715 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
716 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
717 // catch info can get misplaced when a selector ends up more than one block
718 // removed from the parent invoke(s). This could happen when a landing
719 // pad is shared by multiple invokes and is also a target of a normal
720 // edge from elsewhere.
721 addPass(SjLjEHPreparePass(&TM));
722 [[fallthrough]];
723 case ExceptionHandling::DwarfCFI:
724 case ExceptionHandling::ARM:
725 case ExceptionHandling::AIX:
726 case ExceptionHandling::ZOS:
727 addPass(DwarfEHPreparePass(&TM));
728 break;
729 case ExceptionHandling::WinEH:
730 // We support using both GCC-style and MSVC-style exceptions on Windows, so
731 // add both preparation passes. Each pass will only actually run if it
732 // recognizes the personality function.
733 addPass(WinEHPreparePass());
734 addPass(DwarfEHPreparePass(&TM));
735 break;
736 case ExceptionHandling::Wasm:
737 // Wasm EH uses Windows EH instructions, but it does not need to demote PHIs
738 // on catchpads and cleanuppads because it does not outline them into
739 // funclets. Catchswitch blocks are not lowered in SelectionDAG, so we
740 // should remove PHIs there.
741 addPass(WinEHPreparePass(/*DemoteCatchSwitchPHIOnly=*/false));
742 addPass(WasmEHPreparePass());
743 break;
744 case ExceptionHandling::None:
745 addPass(LowerInvokePass());
746
747 // The lower invoke pass may create unreachable code. Remove it.
748 addPass(UnreachableBlockElimPass());
749 break;
750 }
751}
752
753/// Add pass to prepare the LLVM IR for code generation. This should be done
754/// before exception handling preparation passes.
755template <typename Derived, typename TargetMachineT>
756void CodeGenPassBuilder<Derived, TargetMachineT>::addCodeGenPrepare(
757 AddIRPass &addPass) const {
758 if (getOptLevel() != CodeGenOptLevel::None && !Opt.DisableCGP)
759 addPass(CodeGenPreparePass(&TM));
760 // TODO: Default ctor'd RewriteSymbolPass is no-op.
761 // addPass(RewriteSymbolPass());
762}
763
764/// Add common passes that perform LLVM IR to IR transforms in preparation for
765/// instruction selection.
766template <typename Derived, typename TargetMachineT>
767void CodeGenPassBuilder<Derived, TargetMachineT>::addISelPrepare(
768 AddIRPass &addPass) const {
769 derived().addPreISel(addPass);
770
771 addPass(CallBrPreparePass());
772 // Add both the safe stack and the stack protection passes: each of them will
773 // only protect functions that have corresponding attributes.
774 addPass(SafeStackPass(&TM));
775 addPass(StackProtectorPass(&TM));
776
777 if (Opt.PrintISelInput)
778 addPass(PrintFunctionPass(dbgs(),
779 "\n\n*** Final LLVM Code input to ISel ***\n"));
780
781 // All passes which modify the LLVM IR are now complete; run the verifier
782 // to ensure that the IR is valid.
783 if (!Opt.DisableVerify)
784 addPass(VerifierPass());
785}
786
787template <typename Derived, typename TargetMachineT>
788Error CodeGenPassBuilder<Derived, TargetMachineT>::addCoreISelPasses(
789 AddMachinePass &addPass) const {
790 // Enable FastISel with -fast-isel, but allow that to be overridden.
791 TM.setO0WantsFastISel(Opt.EnableFastISelOption.value_or(u: true));
792
793 // Determine an instruction selector.
794 enum class SelectorType { SelectionDAG, FastISel, GlobalISel };
795 SelectorType Selector;
796
797 if (Opt.EnableFastISelOption && *Opt.EnableFastISelOption == true)
798 Selector = SelectorType::FastISel;
799 else if ((Opt.EnableGlobalISelOption &&
800 *Opt.EnableGlobalISelOption == true) ||
801 (TM.Options.EnableGlobalISel &&
802 (!Opt.EnableGlobalISelOption ||
803 *Opt.EnableGlobalISelOption == false)))
804 Selector = SelectorType::GlobalISel;
805 else if (TM.getOptLevel() == CodeGenOptLevel::None && TM.getO0WantsFastISel())
806 Selector = SelectorType::FastISel;
807 else
808 Selector = SelectorType::SelectionDAG;
809
810 // Set consistently TM.Options.EnableFastISel and EnableGlobalISel.
811 if (Selector == SelectorType::FastISel) {
812 TM.setFastISel(true);
813 TM.setGlobalISel(false);
814 } else if (Selector == SelectorType::GlobalISel) {
815 TM.setFastISel(false);
816 TM.setGlobalISel(true);
817 }
818
819 // Add instruction selector passes.
820 if (Selector == SelectorType::GlobalISel) {
821 if (auto Err = derived().addIRTranslator(addPass))
822 return std::move(Err);
823
824 derived().addPreLegalizeMachineIR(addPass);
825
826 if (auto Err = derived().addLegalizeMachineIR(addPass))
827 return std::move(Err);
828
829 // Before running the register bank selector, ask the target if it
830 // wants to run some passes.
831 derived().addPreRegBankSelect(addPass);
832
833 if (auto Err = derived().addRegBankSelect(addPass))
834 return std::move(Err);
835
836 derived().addPreGlobalInstructionSelect(addPass);
837
838 if (auto Err = derived().addGlobalInstructionSelect(addPass))
839 return std::move(Err);
840
841 // Pass to reset the MachineFunction if the ISel failed.
842 addPass(ResetMachineFunctionPass(reportDiagnosticWhenGlobalISelFallback(),
843 isGlobalISelAbortEnabled()));
844
845 // Provide a fallback path when we do not want to abort on
846 // not-yet-supported input.
847 if (!isGlobalISelAbortEnabled())
848 if (auto Err = derived().addInstSelector(addPass))
849 return std::move(Err);
850
851 } else if (auto Err = derived().addInstSelector(addPass))
852 return std::move(Err);
853
854 // Expand pseudo-instructions emitted by ISel. Don't run the verifier before
855 // FinalizeISel.
856 addPass(FinalizeISelPass());
857
858 // // Print the instruction selected machine code...
859 // printAndVerify("After Instruction Selection");
860
861 return Error::success();
862}
863
864/// Add the complete set of target-independent postISel code generator passes.
865///
866/// This can be read as the standard order of major LLVM CodeGen stages. Stages
867/// with nontrivial configuration or multiple passes are broken out below in
868/// add%Stage routines.
869///
870/// Any CodeGenPassBuilder<Derived, TargetMachine>::addXX routine may be
871/// overriden by the Target. The addPre/Post methods with empty header
872/// implementations allow injecting target-specific fixups just before or after
873/// major stages. Additionally, targets have the flexibility to change pass
874/// order within a stage by overriding default implementation of add%Stage
875/// routines below. Each technique has maintainability tradeoffs because
876/// alternate pass orders are not well supported. addPre/Post works better if
877/// the target pass is easily tied to a common pass. But if it has subtle
878/// dependencies on multiple passes, the target should override the stage
879/// instead.
880template <typename Derived, typename TargetMachineT>
881Error CodeGenPassBuilder<Derived, TargetMachineT>::addMachinePasses(
882 AddMachinePass &addPass) const {
883 // Add passes that optimize machine instructions in SSA form.
884 if (getOptLevel() != CodeGenOptLevel::None) {
885 derived().addMachineSSAOptimization(addPass);
886 } else {
887 // If the target requests it, assign local variables to stack slots relative
888 // to one another and simplify frame index references where possible.
889 addPass(LocalStackSlotAllocationPass());
890 }
891
892 if (TM.Options.EnableIPRA)
893 addPass(RegUsageInfoPropagationPass());
894
895 // Run pre-ra passes.
896 derived().addPreRegAlloc(addPass);
897
898 // Run register allocation and passes that are tightly coupled with it,
899 // including phi elimination and scheduling.
900 if (*Opt.OptimizeRegAlloc) {
901 derived().addOptimizedRegAlloc(addPass);
902 } else {
903 if (auto Err = derived().addFastRegAlloc(addPass))
904 return Err;
905 }
906
907 // Run post-ra passes.
908 derived().addPostRegAlloc(addPass);
909
910 addPass(RemoveRedundantDebugValuesPass());
911
912 // Insert prolog/epilog code. Eliminate abstract frame index references...
913 if (getOptLevel() != CodeGenOptLevel::None) {
914 addPass(PostRAMachineSinkingPass());
915 addPass(ShrinkWrapPass());
916 }
917
918 addPass(PrologEpilogInserterPass());
919
920 /// Add passes that optimize machine instructions after register allocation.
921 if (getOptLevel() != CodeGenOptLevel::None)
922 derived().addMachineLateOptimization(addPass);
923
924 // Expand pseudo instructions before second scheduling pass.
925 addPass(ExpandPostRAPseudosPass());
926
927 // Run pre-sched2 passes.
928 derived().addPreSched2(addPass);
929
930 if (Opt.EnableImplicitNullChecks)
931 addPass(ImplicitNullChecksPass());
932
933 // Second pass scheduler.
934 // Let Target optionally insert this pass by itself at some other
935 // point.
936 if (getOptLevel() != CodeGenOptLevel::None &&
937 !TM.targetSchedulesPostRAScheduling()) {
938 if (Opt.MISchedPostRA)
939 addPass(PostMachineSchedulerPass());
940 else
941 addPass(PostRASchedulerPass());
942 }
943
944 // GC
945 derived().addGCPasses(addPass);
946
947 // Basic block placement.
948 if (getOptLevel() != CodeGenOptLevel::None)
949 derived().addBlockPlacement(addPass);
950
951 // Insert before XRay Instrumentation.
952 addPass(FEntryInserterPass());
953
954 addPass(XRayInstrumentationPass());
955 addPass(PatchableFunctionPass());
956
957 derived().addPreEmitPass(addPass);
958
959 if (TM.Options.EnableIPRA)
960 // Collect register usage information and produce a register mask of
961 // clobbered registers, to be used to optimize call sites.
962 addPass(RegUsageInfoCollectorPass());
963
964 addPass(FuncletLayoutPass());
965
966 addPass(StackMapLivenessPass());
967 addPass(LiveDebugValuesPass());
968 addPass(MachineSanitizerBinaryMetadata());
969
970 if (TM.Options.EnableMachineOutliner &&
971 getOptLevel() != CodeGenOptLevel::None &&
972 Opt.EnableMachineOutliner != RunOutliner::NeverOutline) {
973 bool RunOnAllFunctions =
974 (Opt.EnableMachineOutliner == RunOutliner::AlwaysOutline);
975 bool AddOutliner = RunOnAllFunctions || TM.Options.SupportsDefaultOutlining;
976 if (AddOutliner)
977 addPass(MachineOutlinerPass(RunOnAllFunctions));
978 }
979
980 // Add passes that directly emit MI after all other MI passes.
981 derived().addPreEmitPass2(addPass);
982
983 return Error::success();
984}
985
986/// Add passes that optimize machine instructions in SSA form.
987template <typename Derived, typename TargetMachineT>
988void CodeGenPassBuilder<Derived, TargetMachineT>::addMachineSSAOptimization(
989 AddMachinePass &addPass) const {
990 // Pre-ra tail duplication.
991 addPass(EarlyTailDuplicatePass());
992
993 // Optimize PHIs before DCE: removing dead PHI cycles may make more
994 // instructions dead.
995 addPass(OptimizePHIsPass());
996
997 // This pass merges large allocas. StackSlotColoring is a different pass
998 // which merges spill slots.
999 addPass(StackColoringPass());
1000
1001 // If the target requests it, assign local variables to stack slots relative
1002 // to one another and simplify frame index references where possible.
1003 addPass(LocalStackSlotAllocationPass());
1004
1005 // With optimization, dead code should already be eliminated. However
1006 // there is one known exception: lowered code for arguments that are only
1007 // used by tail calls, where the tail calls reuse the incoming stack
1008 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
1009 addPass(DeadMachineInstructionElimPass());
1010
1011 // Allow targets to insert passes that improve instruction level parallelism,
1012 // like if-conversion. Such passes will typically need dominator trees and
1013 // loop info, just like LICM and CSE below.
1014 derived().addILPOpts(addPass);
1015
1016 addPass(EarlyMachineLICMPass());
1017 addPass(MachineCSEPass());
1018
1019 addPass(MachineSinkingPass());
1020
1021 addPass(PeepholeOptimizerPass());
1022 // Clean-up the dead code that may have been generated by peephole
1023 // rewriting.
1024 addPass(DeadMachineInstructionElimPass());
1025}
1026
1027//===---------------------------------------------------------------------===//
1028/// Register Allocation Pass Configuration
1029//===---------------------------------------------------------------------===//
1030
1031/// Instantiate the default register allocator pass for this target for either
1032/// the optimized or unoptimized allocation path. This will be added to the pass
1033/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
1034/// in the optimized case.
1035///
1036/// A target that uses the standard regalloc pass order for fast or optimized
1037/// allocation may still override this for per-target regalloc
1038/// selection. But -regalloc=... always takes precedence.
1039template <typename Derived, typename TargetMachineT>
1040void CodeGenPassBuilder<Derived, TargetMachineT>::addTargetRegisterAllocator(
1041 AddMachinePass &addPass, bool Optimized) const {
1042 if (Optimized)
1043 addPass(RAGreedyPass());
1044 else
1045 addPass(RegAllocFastPass());
1046}
1047
1048/// Find and instantiate the register allocation pass requested by this target
1049/// at the current optimization level. Different register allocators are
1050/// defined as separate passes because they may require different analysis.
1051template <typename Derived, typename TargetMachineT>
1052void CodeGenPassBuilder<Derived, TargetMachineT>::addRegAllocPass(
1053 AddMachinePass &addPass, bool Optimized) const {
1054 // TODO: Parse Opt.RegAlloc to add register allocator.
1055}
1056
1057template <typename Derived, typename TargetMachineT>
1058Error CodeGenPassBuilder<Derived, TargetMachineT>::addRegAssignmentFast(
1059 AddMachinePass &addPass) const {
1060 // TODO: Ensure allocator is default or fast.
1061 addRegAllocPass(addPass, Optimized: false);
1062 return Error::success();
1063}
1064
1065template <typename Derived, typename TargetMachineT>
1066Error CodeGenPassBuilder<Derived, TargetMachineT>::addRegAssignmentOptimized(
1067 AddMachinePass &addPass) const {
1068 // Add the selected register allocation pass.
1069 addRegAllocPass(addPass, Optimized: true);
1070
1071 // Allow targets to change the register assignments before rewriting.
1072 derived().addPreRewrite(addPass);
1073
1074 // Finally rewrite virtual registers.
1075 addPass(VirtRegRewriterPass());
1076 // Perform stack slot coloring and post-ra machine LICM.
1077 //
1078 // FIXME: Re-enable coloring with register when it's capable of adding
1079 // kill markers.
1080 addPass(StackSlotColoringPass());
1081
1082 return Error::success();
1083}
1084
1085/// Add the minimum set of target-independent passes that are required for
1086/// register allocation. No coalescing or scheduling.
1087template <typename Derived, typename TargetMachineT>
1088Error CodeGenPassBuilder<Derived, TargetMachineT>::addFastRegAlloc(
1089 AddMachinePass &addPass) const {
1090 addPass(PHIEliminationPass());
1091 addPass(TwoAddressInstructionPass());
1092 return derived().addRegAssignmentFast(addPass);
1093}
1094
1095/// Add standard target-independent passes that are tightly coupled with
1096/// optimized register allocation, including coalescing, machine instruction
1097/// scheduling, and register allocation itself.
1098template <typename Derived, typename TargetMachineT>
1099void CodeGenPassBuilder<Derived, TargetMachineT>::addOptimizedRegAlloc(
1100 AddMachinePass &addPass) const {
1101 addPass(DetectDeadLanesPass());
1102
1103 addPass(InitUndefPass());
1104
1105 addPass(ProcessImplicitDefsPass());
1106
1107 // Edge splitting is smarter with machine loop info.
1108 addPass(PHIEliminationPass());
1109
1110 // Eventually, we want to run LiveIntervals before PHI elimination.
1111 if (Opt.EarlyLiveIntervals)
1112 addPass(RequireAnalysisPass<LiveIntervalsAnalysis, MachineFunction>());
1113
1114 addPass(TwoAddressInstructionPass());
1115 addPass(RegisterCoalescerPass());
1116
1117 // The machine scheduler may accidentally create disconnected components
1118 // when moving subregister definitions around, avoid this by splitting them to
1119 // separate vregs before. Splitting can also improve reg. allocation quality.
1120 addPass(RenameIndependentSubregsPass());
1121
1122 // PreRA instruction scheduling.
1123 addPass(MachineSchedulerPass());
1124
1125 if (derived().addRegAssignmentOptimized(addPass)) {
1126 // Allow targets to expand pseudo instructions depending on the choice of
1127 // registers before MachineCopyPropagation.
1128 derived().addPostRewrite(addPass);
1129
1130 // Copy propagate to forward register uses and try to eliminate COPYs that
1131 // were not coalesced.
1132 addPass(MachineCopyPropagationPass());
1133
1134 // Run post-ra machine LICM to hoist reloads / remats.
1135 //
1136 // FIXME: can this move into MachineLateOptimization?
1137 addPass(MachineLICMPass());
1138 }
1139}
1140
1141//===---------------------------------------------------------------------===//
1142/// Post RegAlloc Pass Configuration
1143//===---------------------------------------------------------------------===//
1144
1145/// Add passes that optimize machine instructions after register allocation.
1146template <typename Derived, typename TargetMachineT>
1147void CodeGenPassBuilder<Derived, TargetMachineT>::addMachineLateOptimization(
1148 AddMachinePass &addPass) const {
1149 // Branch folding must be run after regalloc and prolog/epilog insertion.
1150 addPass(BranchFolderPass());
1151
1152 // Tail duplication.
1153 // Note that duplicating tail just increases code size and degrades
1154 // performance for targets that require Structured Control Flow.
1155 // In addition it can also make CFG irreducible. Thus we disable it.
1156 if (!TM.requiresStructuredCFG())
1157 addPass(TailDuplicatePass());
1158
1159 // Cleanup of redundant (identical) address/immediate loads.
1160 addPass(MachineLateInstrsCleanupPass());
1161
1162 // Copy propagation.
1163 addPass(MachineCopyPropagationPass());
1164}
1165
1166/// Add standard basic block placement passes.
1167template <typename Derived, typename TargetMachineT>
1168void CodeGenPassBuilder<Derived, TargetMachineT>::addBlockPlacement(
1169 AddMachinePass &addPass) const {
1170 addPass(MachineBlockPlacementPass());
1171 // Run a separate pass to collect block placement statistics.
1172 if (Opt.EnableBlockPlacementStats)
1173 addPass(MachineBlockPlacementStatsPass());
1174}
1175
1176} // namespace llvm
1177
1178#endif // LLVM_PASSES_CODEGENPASSBUILDER_H
1179