1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Methods common to all machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineInstr.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/ADT/Hashing.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallBitVector.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/Analysis/AliasAnalysis.h"
20#include "llvm/Analysis/MemoryLocation.h"
21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineInstrBundle.h"
26#include "llvm/CodeGen/MachineMemOperand.h"
27#include "llvm/CodeGen/MachineModuleInfo.h"
28#include "llvm/CodeGen/MachineOperand.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/PseudoSourceValue.h"
31#include "llvm/CodeGen/Register.h"
32#include "llvm/CodeGen/StackMaps.h"
33#include "llvm/CodeGen/TargetInstrInfo.h"
34#include "llvm/CodeGen/TargetRegisterInfo.h"
35#include "llvm/CodeGen/TargetSubtargetInfo.h"
36#include "llvm/CodeGenTypes/LowLevelType.h"
37#include "llvm/IR/Constants.h"
38#include "llvm/IR/DebugInfoMetadata.h"
39#include "llvm/IR/DebugLoc.h"
40#include "llvm/IR/Function.h"
41#include "llvm/IR/InlineAsm.h"
42#include "llvm/IR/Instructions.h"
43#include "llvm/IR/LLVMContext.h"
44#include "llvm/IR/Metadata.h"
45#include "llvm/IR/Module.h"
46#include "llvm/IR/ModuleSlotTracker.h"
47#include "llvm/IR/Operator.h"
48#include "llvm/MC/MCInstrDesc.h"
49#include "llvm/MC/MCRegisterInfo.h"
50#include "llvm/Support/Casting.h"
51#include "llvm/Support/Compiler.h"
52#include "llvm/Support/Debug.h"
53#include "llvm/Support/ErrorHandling.h"
54#include "llvm/Support/FormattedStream.h"
55#include "llvm/Support/raw_ostream.h"
56#include "llvm/Target/TargetMachine.h"
57#include <algorithm>
58#include <cassert>
59#include <cstdint>
60#include <cstring>
61#include <utility>
62
63using namespace llvm;
64
65static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
66 if (const MachineBasicBlock *MBB = MI.getParent())
67 if (const MachineFunction *MF = MBB->getParent())
68 return MF;
69 return nullptr;
70}
71
72// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
73// it.
74static void tryToGetTargetInfo(const MachineInstr &MI,
75 const TargetRegisterInfo *&TRI,
76 const MachineRegisterInfo *&MRI,
77 const TargetIntrinsicInfo *&IntrinsicInfo,
78 const TargetInstrInfo *&TII) {
79
80 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
81 TRI = MF->getSubtarget().getRegisterInfo();
82 MRI = &MF->getRegInfo();
83 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
84 TII = MF->getSubtarget().getInstrInfo();
85 }
86}
87
88void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
89 for (MCPhysReg ImpDef : MCID->implicit_defs())
90 addOperand(MF, Op: MachineOperand::CreateReg(Reg: ImpDef, isDef: true, isImp: true));
91 for (MCPhysReg ImpUse : MCID->implicit_uses())
92 addOperand(MF, Op: MachineOperand::CreateReg(Reg: ImpUse, isDef: false, isImp: true));
93}
94
95/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
96/// implicit operands. It reserves space for the number of operands specified by
97/// the MCInstrDesc.
98MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,
99 DebugLoc DL, bool NoImp)
100 : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0),
101 DbgLoc(std::move(DL)), DebugInstrNum(0), Opcode(TID.Opcode) {
102 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
103
104 // Reserve space for the expected number of operands.
105 if (unsigned NumOps = MCID->getNumOperands() + MCID->implicit_defs().size() +
106 MCID->implicit_uses().size()) {
107 CapOperands = OperandCapacity::get(N: NumOps);
108 Operands = MF.allocateOperandArray(Cap: CapOperands);
109 }
110
111 if (!NoImp)
112 addImplicitDefUseOperands(MF);
113}
114
115/// MachineInstr ctor - Copies MachineInstr arg exactly.
116/// Does not copy the number from debug instruction numbering, to preserve
117/// uniqueness.
118MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
119 : MCID(&MI.getDesc()), NumOperands(0), Flags(0), AsmPrinterFlags(0),
120 Info(MI.Info), DbgLoc(MI.getDebugLoc()), DebugInstrNum(0),
121 Opcode(MI.getOpcode()) {
122 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
123
124 CapOperands = OperandCapacity::get(N: MI.getNumOperands());
125 Operands = MF.allocateOperandArray(Cap: CapOperands);
126
127 // Copy operands.
128 for (const MachineOperand &MO : MI.operands())
129 addOperand(MF, Op: MO);
130
131 // Replicate ties between the operands, which addOperand was not
132 // able to do reliably.
133 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
134 MachineOperand &NewMO = getOperand(i);
135 const MachineOperand &OrigMO = MI.getOperand(i);
136 NewMO.TiedTo = OrigMO.TiedTo;
137 }
138
139 // Copy all the sensible flags.
140 setFlags(MI.Flags);
141}
142
143void MachineInstr::setDesc(const MCInstrDesc &TID) {
144 if (getParent())
145 getMF()->handleChangeDesc(MI&: *this, TID);
146 MCID = &TID;
147 Opcode = TID.Opcode;
148}
149
150void MachineInstr::moveBefore(MachineInstr *MovePos) {
151 MovePos->getParent()->splice(Where: MovePos, Other: getParent(), From: getIterator());
152}
153
154/// getRegInfo - If this instruction is embedded into a MachineFunction,
155/// return the MachineRegisterInfo object for the current function, otherwise
156/// return null.
157MachineRegisterInfo *MachineInstr::getRegInfo() {
158 if (MachineBasicBlock *MBB = getParent())
159 return &MBB->getParent()->getRegInfo();
160 return nullptr;
161}
162
163const MachineRegisterInfo *MachineInstr::getRegInfo() const {
164 if (const MachineBasicBlock *MBB = getParent())
165 return &MBB->getParent()->getRegInfo();
166 return nullptr;
167}
168
169void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
170 for (MachineOperand &MO : operands())
171 if (MO.isReg())
172 MRI.removeRegOperandFromUseList(MO: &MO);
173}
174
175void MachineInstr::addRegOperandsToUseLists(MachineRegisterInfo &MRI) {
176 for (MachineOperand &MO : operands())
177 if (MO.isReg())
178 MRI.addRegOperandToUseList(MO: &MO);
179}
180
181void MachineInstr::addOperand(const MachineOperand &Op) {
182 MachineBasicBlock *MBB = getParent();
183 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
184 MachineFunction *MF = MBB->getParent();
185 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
186 addOperand(MF&: *MF, Op);
187}
188
189/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
190/// ranges. If MRI is non-null also update use-def chains.
191static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
192 unsigned NumOps, MachineRegisterInfo *MRI) {
193 if (MRI)
194 return MRI->moveOperands(Dst, Src, NumOps);
195 // MachineOperand is a trivially copyable type so we can just use memmove.
196 assert(Dst && Src && "Unknown operands");
197 std::memmove(dest: Dst, src: Src, n: NumOps * sizeof(MachineOperand));
198}
199
200/// addOperand - Add the specified operand to the instruction. If it is an
201/// implicit operand, it is added to the end of the operand list. If it is
202/// an explicit operand it is added at the end of the explicit operand list
203/// (before the first implicit operand).
204void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
205 assert(isUInt<LLVM_MI_NUMOPERANDS_BITS>(NumOperands + 1) &&
206 "Cannot add more operands.");
207 assert(MCID && "Cannot add operands before providing an instr descriptor");
208
209 // Check if we're adding one of our existing operands.
210 if (&Op >= Operands && &Op < Operands + NumOperands) {
211 // This is unusual: MI->addOperand(MI->getOperand(i)).
212 // If adding Op requires reallocating or moving existing operands around,
213 // the Op reference could go stale. Support it by copying Op.
214 MachineOperand CopyOp(Op);
215 return addOperand(MF, Op: CopyOp);
216 }
217
218 // Find the insert location for the new operand. Implicit registers go at
219 // the end, everything else goes before the implicit regs.
220 //
221 // FIXME: Allow mixed explicit and implicit operands on inline asm.
222 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
223 // implicit-defs, but they must not be moved around. See the FIXME in
224 // InstrEmitter.cpp.
225 unsigned OpNo = getNumOperands();
226 bool isImpReg = Op.isReg() && Op.isImplicit();
227 if (!isImpReg && !isInlineAsm()) {
228 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
229 --OpNo;
230 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
231 }
232 }
233
234 // OpNo now points as the desired insertion point. Unless this is a variadic
235 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
236 // RegMask operands go between the explicit and implicit operands.
237 MachineRegisterInfo *MRI = getRegInfo();
238
239 // Determine if the Operands array needs to be reallocated.
240 // Save the old capacity and operand array.
241 OperandCapacity OldCap = CapOperands;
242 MachineOperand *OldOperands = Operands;
243 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
244 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(N: 1);
245 Operands = MF.allocateOperandArray(Cap: CapOperands);
246 // Move the operands before the insertion point.
247 if (OpNo)
248 moveOperands(Dst: Operands, Src: OldOperands, NumOps: OpNo, MRI);
249 }
250
251 // Move the operands following the insertion point.
252 if (OpNo != NumOperands)
253 moveOperands(Dst: Operands + OpNo + 1, Src: OldOperands + OpNo, NumOps: NumOperands - OpNo,
254 MRI);
255 ++NumOperands;
256
257 // Deallocate the old operand array.
258 if (OldOperands != Operands && OldOperands)
259 MF.deallocateOperandArray(Cap: OldCap, Array: OldOperands);
260
261 // Copy Op into place. It still needs to be inserted into the MRI use lists.
262 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
263 NewMO->ParentMI = this;
264
265 // When adding a register operand, tell MRI about it.
266 if (NewMO->isReg()) {
267 // Ensure isOnRegUseList() returns false, regardless of Op's status.
268 NewMO->Contents.Reg.Prev = nullptr;
269 // Ignore existing ties. This is not a property that can be copied.
270 NewMO->TiedTo = 0;
271 // Add the new operand to MRI, but only for instructions in an MBB.
272 if (MRI)
273 MRI->addRegOperandToUseList(MO: NewMO);
274 // The MCID operand information isn't accurate until we start adding
275 // explicit operands. The implicit operands are added first, then the
276 // explicits are inserted before them.
277 if (!isImpReg) {
278 // Tie uses to defs as indicated in MCInstrDesc.
279 if (NewMO->isUse()) {
280 int DefIdx = MCID->getOperandConstraint(OpNum: OpNo, Constraint: MCOI::TIED_TO);
281 if (DefIdx != -1)
282 tieOperands(DefIdx, UseIdx: OpNo);
283 }
284 // If the register operand is flagged as early, mark the operand as such.
285 if (MCID->getOperandConstraint(OpNum: OpNo, Constraint: MCOI::EARLY_CLOBBER) != -1)
286 NewMO->setIsEarlyClobber(true);
287 }
288 // Ensure debug instructions set debug flag on register uses.
289 if (NewMO->isUse() && isDebugInstr())
290 NewMO->setIsDebug();
291 }
292}
293
294void MachineInstr::removeOperand(unsigned OpNo) {
295 assert(OpNo < getNumOperands() && "Invalid operand number");
296 untieRegOperand(OpIdx: OpNo);
297
298#ifndef NDEBUG
299 // Moving tied operands would break the ties.
300 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
301 if (Operands[i].isReg())
302 assert(!Operands[i].isTied() && "Cannot move tied operands");
303#endif
304
305 MachineRegisterInfo *MRI = getRegInfo();
306 if (MRI && Operands[OpNo].isReg())
307 MRI->removeRegOperandFromUseList(MO: Operands + OpNo);
308
309 // Don't call the MachineOperand destructor. A lot of this code depends on
310 // MachineOperand having a trivial destructor anyway, and adding a call here
311 // wouldn't make it 'destructor-correct'.
312
313 if (unsigned N = NumOperands - 1 - OpNo)
314 moveOperands(Dst: Operands + OpNo, Src: Operands + OpNo + 1, NumOps: N, MRI);
315 --NumOperands;
316}
317
318void MachineInstr::setExtraInfo(MachineFunction &MF,
319 ArrayRef<MachineMemOperand *> MMOs,
320 MCSymbol *PreInstrSymbol,
321 MCSymbol *PostInstrSymbol,
322 MDNode *HeapAllocMarker, MDNode *PCSections,
323 uint32_t CFIType, MDNode *MMRAs) {
324 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
325 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
326 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
327 bool HasPCSections = PCSections != nullptr;
328 bool HasCFIType = CFIType != 0;
329 bool HasMMRAs = MMRAs != nullptr;
330 int NumPointers = MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol +
331 HasHeapAllocMarker + HasPCSections + HasCFIType + HasMMRAs;
332
333 // Drop all extra info if there is none.
334 if (NumPointers <= 0) {
335 Info.clear();
336 return;
337 }
338
339 // If more than one pointer, then store out of line. Store heap alloc markers
340 // out of line because PointerSumType cannot hold more than 4 tag types with
341 // 32-bit pointers.
342 // FIXME: Maybe we should make the symbols in the extra info mutable?
343 else if (NumPointers > 1 || HasMMRAs || HasHeapAllocMarker || HasPCSections ||
344 HasCFIType) {
345 Info.set<EIIK_OutOfLine>(
346 MF.createMIExtraInfo(MMOs, PreInstrSymbol, PostInstrSymbol,
347 HeapAllocMarker, PCSections, CFIType, MMRAs));
348 return;
349 }
350
351 // Otherwise store the single pointer inline.
352 if (HasPreInstrSymbol)
353 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
354 else if (HasPostInstrSymbol)
355 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
356 else
357 Info.set<EIIK_MMO>(MMOs[0]);
358}
359
360void MachineInstr::dropMemRefs(MachineFunction &MF) {
361 if (memoperands_empty())
362 return;
363
364 setExtraInfo(MF, MMOs: {}, PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
365 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
366 MMRAs: getMMRAMetadata());
367}
368
369void MachineInstr::setMemRefs(MachineFunction &MF,
370 ArrayRef<MachineMemOperand *> MMOs) {
371 if (MMOs.empty()) {
372 dropMemRefs(MF);
373 return;
374 }
375
376 setExtraInfo(MF, MMOs, PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
377 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
378 MMRAs: getMMRAMetadata());
379}
380
381void MachineInstr::addMemOperand(MachineFunction &MF,
382 MachineMemOperand *MO) {
383 SmallVector<MachineMemOperand *, 2> MMOs;
384 MMOs.append(in_start: memoperands_begin(), in_end: memoperands_end());
385 MMOs.push_back(Elt: MO);
386 setMemRefs(MF, MMOs);
387}
388
389void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
390 if (this == &MI)
391 // Nothing to do for a self-clone!
392 return;
393
394 assert(&MF == MI.getMF() &&
395 "Invalid machine functions when cloning memory refrences!");
396 // See if we can just steal the extra info already allocated for the
397 // instruction. We can do this whenever the pre- and post-instruction symbols
398 // are the same (including null).
399 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
400 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
401 getHeapAllocMarker() == MI.getHeapAllocMarker() &&
402 getPCSections() == MI.getPCSections() && getMMRAMetadata() &&
403 MI.getMMRAMetadata()) {
404 Info = MI.Info;
405 return;
406 }
407
408 // Otherwise, fall back on a copy-based clone.
409 setMemRefs(MF, MMOs: MI.memoperands());
410}
411
412/// Check to see if the MMOs pointed to by the two MemRefs arrays are
413/// identical.
414static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
415 ArrayRef<MachineMemOperand *> RHS) {
416 if (LHS.size() != RHS.size())
417 return false;
418
419 auto LHSPointees = make_pointee_range(Range&: LHS);
420 auto RHSPointees = make_pointee_range(Range&: RHS);
421 return std::equal(LHSPointees.begin(), LHSPointees.end(),
422 RHSPointees.begin());
423}
424
425void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
426 ArrayRef<const MachineInstr *> MIs) {
427 // Try handling easy numbers of MIs with simpler mechanisms.
428 if (MIs.empty()) {
429 dropMemRefs(MF);
430 return;
431 }
432 if (MIs.size() == 1) {
433 cloneMemRefs(MF, MI: *MIs[0]);
434 return;
435 }
436 // Because an empty memoperands list provides *no* information and must be
437 // handled conservatively (assuming the instruction can do anything), the only
438 // way to merge with it is to drop all other memoperands.
439 if (MIs[0]->memoperands_empty()) {
440 dropMemRefs(MF);
441 return;
442 }
443
444 // Handle the general case.
445 SmallVector<MachineMemOperand *, 2> MergedMMOs;
446 // Start with the first instruction.
447 assert(&MF == MIs[0]->getMF() &&
448 "Invalid machine functions when cloning memory references!");
449 MergedMMOs.append(in_start: MIs[0]->memoperands_begin(), in_end: MIs[0]->memoperands_end());
450 // Now walk all the other instructions and accumulate any different MMOs.
451 for (const MachineInstr &MI : make_pointee_range(Range: MIs.slice(N: 1))) {
452 assert(&MF == MI.getMF() &&
453 "Invalid machine functions when cloning memory references!");
454
455 // Skip MIs with identical operands to the first. This is a somewhat
456 // arbitrary hack but will catch common cases without being quadratic.
457 // TODO: We could fully implement merge semantics here if needed.
458 if (hasIdenticalMMOs(LHS: MIs[0]->memoperands(), RHS: MI.memoperands()))
459 continue;
460
461 // Because an empty memoperands list provides *no* information and must be
462 // handled conservatively (assuming the instruction can do anything), the
463 // only way to merge with it is to drop all other memoperands.
464 if (MI.memoperands_empty()) {
465 dropMemRefs(MF);
466 return;
467 }
468
469 // Otherwise accumulate these into our temporary buffer of the merged state.
470 MergedMMOs.append(in_start: MI.memoperands_begin(), in_end: MI.memoperands_end());
471 }
472
473 setMemRefs(MF, MMOs: MergedMMOs);
474}
475
476void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
477 // Do nothing if old and new symbols are the same.
478 if (Symbol == getPreInstrSymbol())
479 return;
480
481 // If there was only one symbol and we're removing it, just clear info.
482 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
483 Info.clear();
484 return;
485 }
486
487 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: Symbol, PostInstrSymbol: getPostInstrSymbol(),
488 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
489 MMRAs: getMMRAMetadata());
490}
491
492void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
493 // Do nothing if old and new symbols are the same.
494 if (Symbol == getPostInstrSymbol())
495 return;
496
497 // If there was only one symbol and we're removing it, just clear info.
498 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
499 Info.clear();
500 return;
501 }
502
503 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: Symbol,
504 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(),
505 MMRAs: getMMRAMetadata());
506}
507
508void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {
509 // Do nothing if old and new symbols are the same.
510 if (Marker == getHeapAllocMarker())
511 return;
512
513 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
514 HeapAllocMarker: Marker, PCSections: getPCSections(), CFIType: getCFIType(), MMRAs: getMMRAMetadata());
515}
516
517void MachineInstr::setPCSections(MachineFunction &MF, MDNode *PCSections) {
518 // Do nothing if old and new symbols are the same.
519 if (PCSections == getPCSections())
520 return;
521
522 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
523 HeapAllocMarker: getHeapAllocMarker(), PCSections, CFIType: getCFIType(),
524 MMRAs: getMMRAMetadata());
525}
526
527void MachineInstr::setCFIType(MachineFunction &MF, uint32_t Type) {
528 // Do nothing if old and new types are the same.
529 if (Type == getCFIType())
530 return;
531
532 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
533 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: Type, MMRAs: getMMRAMetadata());
534}
535
536void MachineInstr::setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs) {
537 // Do nothing if old and new symbols are the same.
538 if (MMRAs == getMMRAMetadata())
539 return;
540
541 setExtraInfo(MF, MMOs: memoperands(), PreInstrSymbol: getPreInstrSymbol(), PostInstrSymbol: getPostInstrSymbol(),
542 HeapAllocMarker: getHeapAllocMarker(), PCSections: getPCSections(), CFIType: getCFIType(), MMRAs);
543}
544
545void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
546 const MachineInstr &MI) {
547 if (this == &MI)
548 // Nothing to do for a self-clone!
549 return;
550
551 assert(&MF == MI.getMF() &&
552 "Invalid machine functions when cloning instruction symbols!");
553
554 setPreInstrSymbol(MF, Symbol: MI.getPreInstrSymbol());
555 setPostInstrSymbol(MF, Symbol: MI.getPostInstrSymbol());
556 setHeapAllocMarker(MF, Marker: MI.getHeapAllocMarker());
557 setPCSections(MF, PCSections: MI.getPCSections());
558 setMMRAMetadata(MF, MMRAs: MI.getMMRAMetadata());
559}
560
561uint32_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
562 // For now, the just return the union of the flags. If the flags get more
563 // complicated over time, we might need more logic here.
564 return getFlags() | Other.getFlags();
565}
566
567uint32_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
568 uint32_t MIFlags = 0;
569 // Copy the wrapping flags.
570 if (const OverflowingBinaryOperator *OB =
571 dyn_cast<OverflowingBinaryOperator>(Val: &I)) {
572 if (OB->hasNoSignedWrap())
573 MIFlags |= MachineInstr::MIFlag::NoSWrap;
574 if (OB->hasNoUnsignedWrap())
575 MIFlags |= MachineInstr::MIFlag::NoUWrap;
576 } else if (const TruncInst *TI = dyn_cast<TruncInst>(Val: &I)) {
577 if (TI->hasNoSignedWrap())
578 MIFlags |= MachineInstr::MIFlag::NoSWrap;
579 if (TI->hasNoUnsignedWrap())
580 MIFlags |= MachineInstr::MIFlag::NoUWrap;
581 } else if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Val: &I)) {
582 if (GEP->hasNoUnsignedSignedWrap())
583 MIFlags |= MachineInstr::MIFlag::NoUSWrap;
584 if (GEP->hasNoUnsignedWrap())
585 MIFlags |= MachineInstr::MIFlag::NoUWrap;
586 }
587
588 // Copy the nonneg flag.
589 if (const PossiblyNonNegInst *PNI = dyn_cast<PossiblyNonNegInst>(Val: &I)) {
590 if (PNI->hasNonNeg())
591 MIFlags |= MachineInstr::MIFlag::NonNeg;
592 // Copy the disjoint flag.
593 } else if (const PossiblyDisjointInst *PD =
594 dyn_cast<PossiblyDisjointInst>(Val: &I)) {
595 if (PD->isDisjoint())
596 MIFlags |= MachineInstr::MIFlag::Disjoint;
597 }
598
599 // Copy the exact flag.
600 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(Val: &I))
601 if (PE->isExact())
602 MIFlags |= MachineInstr::MIFlag::IsExact;
603
604 // Copy the fast-math flags.
605 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(Val: &I)) {
606 const FastMathFlags Flags = FP->getFastMathFlags();
607 if (Flags.noNaNs())
608 MIFlags |= MachineInstr::MIFlag::FmNoNans;
609 if (Flags.noInfs())
610 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
611 if (Flags.noSignedZeros())
612 MIFlags |= MachineInstr::MIFlag::FmNsz;
613 if (Flags.allowReciprocal())
614 MIFlags |= MachineInstr::MIFlag::FmArcp;
615 if (Flags.allowContract())
616 MIFlags |= MachineInstr::MIFlag::FmContract;
617 if (Flags.approxFunc())
618 MIFlags |= MachineInstr::MIFlag::FmAfn;
619 if (Flags.allowReassoc())
620 MIFlags |= MachineInstr::MIFlag::FmReassoc;
621 }
622
623 if (I.getMetadata(KindID: LLVMContext::MD_unpredictable))
624 MIFlags |= MachineInstr::MIFlag::Unpredictable;
625
626 return MIFlags;
627}
628
629void MachineInstr::copyIRFlags(const Instruction &I) {
630 Flags = copyFlagsFromInstruction(I);
631}
632
633bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
634 assert(!isBundledWithPred() && "Must be called on bundle header");
635 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
636 if (MII->getDesc().getFlags() & Mask) {
637 if (Type == AnyInBundle)
638 return true;
639 } else {
640 if (Type == AllInBundle && !MII->isBundle())
641 return false;
642 }
643 // This was the last instruction in the bundle.
644 if (!MII->isBundledWithSucc())
645 return Type == AllInBundle;
646 }
647}
648
649bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
650 MICheckType Check) const {
651 // If opcodes or number of operands are not the same then the two
652 // instructions are obviously not identical.
653 if (Other.getOpcode() != getOpcode() ||
654 Other.getNumOperands() != getNumOperands())
655 return false;
656
657 if (isBundle()) {
658 // We have passed the test above that both instructions have the same
659 // opcode, so we know that both instructions are bundles here. Let's compare
660 // MIs inside the bundle.
661 assert(Other.isBundle() && "Expected that both instructions are bundles.");
662 MachineBasicBlock::const_instr_iterator I1 = getIterator();
663 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
664 // Loop until we analysed the last intruction inside at least one of the
665 // bundles.
666 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
667 ++I1;
668 ++I2;
669 if (!I1->isIdenticalTo(Other: *I2, Check))
670 return false;
671 }
672 // If we've reached the end of just one of the two bundles, but not both,
673 // the instructions are not identical.
674 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
675 return false;
676 }
677
678 // Check operands to make sure they match.
679 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
680 const MachineOperand &MO = getOperand(i);
681 const MachineOperand &OMO = Other.getOperand(i);
682 if (!MO.isReg()) {
683 if (!MO.isIdenticalTo(Other: OMO))
684 return false;
685 continue;
686 }
687
688 // Clients may or may not want to ignore defs when testing for equality.
689 // For example, machine CSE pass only cares about finding common
690 // subexpressions, so it's safe to ignore virtual register defs.
691 if (MO.isDef()) {
692 if (Check == IgnoreDefs)
693 continue;
694 else if (Check == IgnoreVRegDefs) {
695 if (!MO.getReg().isVirtual() || !OMO.getReg().isVirtual())
696 if (!MO.isIdenticalTo(Other: OMO))
697 return false;
698 } else {
699 if (!MO.isIdenticalTo(Other: OMO))
700 return false;
701 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
702 return false;
703 }
704 } else {
705 if (!MO.isIdenticalTo(Other: OMO))
706 return false;
707 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
708 return false;
709 }
710 }
711 // If DebugLoc does not match then two debug instructions are not identical.
712 if (isDebugInstr())
713 if (getDebugLoc() && Other.getDebugLoc() &&
714 getDebugLoc() != Other.getDebugLoc())
715 return false;
716 // If pre- or post-instruction symbols do not match then the two instructions
717 // are not identical.
718 if (getPreInstrSymbol() != Other.getPreInstrSymbol() ||
719 getPostInstrSymbol() != Other.getPostInstrSymbol())
720 return false;
721 // Call instructions with different CFI types are not identical.
722 if (isCall() && getCFIType() != Other.getCFIType())
723 return false;
724
725 return true;
726}
727
728bool MachineInstr::isEquivalentDbgInstr(const MachineInstr &Other) const {
729 if (!isDebugValueLike() || !Other.isDebugValueLike())
730 return false;
731 if (getDebugLoc() != Other.getDebugLoc())
732 return false;
733 if (getDebugVariable() != Other.getDebugVariable())
734 return false;
735 if (getNumDebugOperands() != Other.getNumDebugOperands())
736 return false;
737 for (unsigned OpIdx = 0; OpIdx < getNumDebugOperands(); ++OpIdx)
738 if (!getDebugOperand(Index: OpIdx).isIdenticalTo(Other: Other.getDebugOperand(Index: OpIdx)))
739 return false;
740 if (!DIExpression::isEqualExpression(
741 FirstExpr: getDebugExpression(), FirstIndirect: isIndirectDebugValue(),
742 SecondExpr: Other.getDebugExpression(), SecondIndirect: Other.isIndirectDebugValue()))
743 return false;
744 return true;
745}
746
747const MachineFunction *MachineInstr::getMF() const {
748 return getParent()->getParent();
749}
750
751MachineInstr *MachineInstr::removeFromParent() {
752 assert(getParent() && "Not embedded in a basic block!");
753 return getParent()->remove(I: this);
754}
755
756MachineInstr *MachineInstr::removeFromBundle() {
757 assert(getParent() && "Not embedded in a basic block!");
758 return getParent()->remove_instr(I: this);
759}
760
761void MachineInstr::eraseFromParent() {
762 assert(getParent() && "Not embedded in a basic block!");
763 getParent()->erase(I: this);
764}
765
766void MachineInstr::eraseFromBundle() {
767 assert(getParent() && "Not embedded in a basic block!");
768 getParent()->erase_instr(I: this);
769}
770
771bool MachineInstr::isCandidateForCallSiteEntry(QueryType Type) const {
772 if (!isCall(Type))
773 return false;
774 switch (getOpcode()) {
775 case TargetOpcode::PATCHPOINT:
776 case TargetOpcode::STACKMAP:
777 case TargetOpcode::STATEPOINT:
778 case TargetOpcode::FENTRY_CALL:
779 return false;
780 }
781 return true;
782}
783
784bool MachineInstr::shouldUpdateCallSiteInfo() const {
785 if (isBundle())
786 return isCandidateForCallSiteEntry(Type: MachineInstr::AnyInBundle);
787 return isCandidateForCallSiteEntry();
788}
789
790unsigned MachineInstr::getNumExplicitOperands() const {
791 unsigned NumOperands = MCID->getNumOperands();
792 if (!MCID->isVariadic())
793 return NumOperands;
794
795 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
796 const MachineOperand &MO = getOperand(i: I);
797 // The operands must always be in the following order:
798 // - explicit reg defs,
799 // - other explicit operands (reg uses, immediates, etc.),
800 // - implicit reg defs
801 // - implicit reg uses
802 if (MO.isReg() && MO.isImplicit())
803 break;
804 ++NumOperands;
805 }
806 return NumOperands;
807}
808
809unsigned MachineInstr::getNumExplicitDefs() const {
810 unsigned NumDefs = MCID->getNumDefs();
811 if (!MCID->isVariadic())
812 return NumDefs;
813
814 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
815 const MachineOperand &MO = getOperand(i: I);
816 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
817 break;
818 ++NumDefs;
819 }
820 return NumDefs;
821}
822
823void MachineInstr::bundleWithPred() {
824 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
825 setFlag(BundledPred);
826 MachineBasicBlock::instr_iterator Pred = getIterator();
827 --Pred;
828 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
829 Pred->setFlag(BundledSucc);
830}
831
832void MachineInstr::bundleWithSucc() {
833 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
834 setFlag(BundledSucc);
835 MachineBasicBlock::instr_iterator Succ = getIterator();
836 ++Succ;
837 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
838 Succ->setFlag(BundledPred);
839}
840
841void MachineInstr::unbundleFromPred() {
842 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
843 clearFlag(Flag: BundledPred);
844 MachineBasicBlock::instr_iterator Pred = getIterator();
845 --Pred;
846 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
847 Pred->clearFlag(Flag: BundledSucc);
848}
849
850void MachineInstr::unbundleFromSucc() {
851 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
852 clearFlag(Flag: BundledSucc);
853 MachineBasicBlock::instr_iterator Succ = getIterator();
854 ++Succ;
855 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
856 Succ->clearFlag(Flag: BundledPred);
857}
858
859bool MachineInstr::isStackAligningInlineAsm() const {
860 if (isInlineAsm()) {
861 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
862 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
863 return true;
864 }
865 return false;
866}
867
868InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
869 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
870 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
871 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
872}
873
874int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
875 unsigned *GroupNo) const {
876 assert(isInlineAsm() && "Expected an inline asm instruction");
877 assert(OpIdx < getNumOperands() && "OpIdx out of range");
878
879 // Ignore queries about the initial operands.
880 if (OpIdx < InlineAsm::MIOp_FirstOperand)
881 return -1;
882
883 unsigned Group = 0;
884 unsigned NumOps;
885 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
886 i += NumOps) {
887 const MachineOperand &FlagMO = getOperand(i);
888 // If we reach the implicit register operands, stop looking.
889 if (!FlagMO.isImm())
890 return -1;
891 const InlineAsm::Flag F(FlagMO.getImm());
892 NumOps = 1 + F.getNumOperandRegisters();
893 if (i + NumOps > OpIdx) {
894 if (GroupNo)
895 *GroupNo = Group;
896 return i;
897 }
898 ++Group;
899 }
900 return -1;
901}
902
903const DILabel *MachineInstr::getDebugLabel() const {
904 assert(isDebugLabel() && "not a DBG_LABEL");
905 return cast<DILabel>(Val: getOperand(i: 0).getMetadata());
906}
907
908const MachineOperand &MachineInstr::getDebugVariableOp() const {
909 assert((isDebugValueLike()) && "not a DBG_VALUE*");
910 unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
911 return getOperand(i: VariableOp);
912}
913
914MachineOperand &MachineInstr::getDebugVariableOp() {
915 assert((isDebugValueLike()) && "not a DBG_VALUE*");
916 unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
917 return getOperand(i: VariableOp);
918}
919
920const DILocalVariable *MachineInstr::getDebugVariable() const {
921 return cast<DILocalVariable>(Val: getDebugVariableOp().getMetadata());
922}
923
924const MachineOperand &MachineInstr::getDebugExpressionOp() const {
925 assert((isDebugValueLike()) && "not a DBG_VALUE*");
926 unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
927 return getOperand(i: ExpressionOp);
928}
929
930MachineOperand &MachineInstr::getDebugExpressionOp() {
931 assert((isDebugValueLike()) && "not a DBG_VALUE*");
932 unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
933 return getOperand(i: ExpressionOp);
934}
935
936const DIExpression *MachineInstr::getDebugExpression() const {
937 return cast<DIExpression>(Val: getDebugExpressionOp().getMetadata());
938}
939
940bool MachineInstr::isDebugEntryValue() const {
941 return isDebugValue() && getDebugExpression()->isEntryValue();
942}
943
944const TargetRegisterClass*
945MachineInstr::getRegClassConstraint(unsigned OpIdx,
946 const TargetInstrInfo *TII,
947 const TargetRegisterInfo *TRI) const {
948 assert(getParent() && "Can't have an MBB reference here!");
949 assert(getMF() && "Can't have an MF reference here!");
950 const MachineFunction &MF = *getMF();
951
952 // Most opcodes have fixed constraints in their MCInstrDesc.
953 if (!isInlineAsm())
954 return TII->getRegClass(MCID: getDesc(), OpNum: OpIdx, TRI, MF);
955
956 if (!getOperand(i: OpIdx).isReg())
957 return nullptr;
958
959 // For tied uses on inline asm, get the constraint from the def.
960 unsigned DefIdx;
961 if (getOperand(i: OpIdx).isUse() && isRegTiedToDefOperand(UseOpIdx: OpIdx, DefOpIdx: &DefIdx))
962 OpIdx = DefIdx;
963
964 // Inline asm stores register class constraints in the flag word.
965 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
966 if (FlagIdx < 0)
967 return nullptr;
968
969 const InlineAsm::Flag F(getOperand(i: FlagIdx).getImm());
970 unsigned RCID;
971 if ((F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind()) &&
972 F.hasRegClassConstraint(RC&: RCID))
973 return TRI->getRegClass(i: RCID);
974
975 // Assume that all registers in a memory operand are pointers.
976 if (F.isMemKind())
977 return TRI->getPointerRegClass(MF);
978
979 return nullptr;
980}
981
982const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
983 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
984 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
985 // Check every operands inside the bundle if we have
986 // been asked to.
987 if (ExploreBundle)
988 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
989 ++OpndIt)
990 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
991 OpIdx: OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
992 else
993 // Otherwise, just check the current operands.
994 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
995 CurRC = getRegClassConstraintEffectForVRegImpl(OpIdx: i, Reg, CurRC, TII, TRI);
996 return CurRC;
997}
998
999const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
1000 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1001 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1002 assert(CurRC && "Invalid initial register class");
1003 // Check if Reg is constrained by some of its use/def from MI.
1004 const MachineOperand &MO = getOperand(i: OpIdx);
1005 if (!MO.isReg() || MO.getReg() != Reg)
1006 return CurRC;
1007 // If yes, accumulate the constraints through the operand.
1008 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
1009}
1010
1011const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
1012 unsigned OpIdx, const TargetRegisterClass *CurRC,
1013 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1014 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
1015 const MachineOperand &MO = getOperand(i: OpIdx);
1016 assert(MO.isReg() &&
1017 "Cannot get register constraints for non-register operand");
1018 assert(CurRC && "Invalid initial register class");
1019 if (unsigned SubIdx = MO.getSubReg()) {
1020 if (OpRC)
1021 CurRC = TRI->getMatchingSuperRegClass(A: CurRC, B: OpRC, Idx: SubIdx);
1022 else
1023 CurRC = TRI->getSubClassWithSubReg(RC: CurRC, Idx: SubIdx);
1024 } else if (OpRC)
1025 CurRC = TRI->getCommonSubClass(A: CurRC, B: OpRC);
1026 return CurRC;
1027}
1028
1029/// Return the number of instructions inside the MI bundle, not counting the
1030/// header instruction.
1031unsigned MachineInstr::getBundleSize() const {
1032 MachineBasicBlock::const_instr_iterator I = getIterator();
1033 unsigned Size = 0;
1034 while (I->isBundledWithSucc()) {
1035 ++Size;
1036 ++I;
1037 }
1038 return Size;
1039}
1040
1041/// Returns true if the MachineInstr has an implicit-use operand of exactly
1042/// the given register (not considering sub/super-registers).
1043bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
1044 for (const MachineOperand &MO : operands()) {
1045 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
1046 return true;
1047 }
1048 return false;
1049}
1050
1051/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1052/// the specific register or -1 if it is not found. It further tightens
1053/// the search criteria to a use that kills the register if isKill is true.
1054int MachineInstr::findRegisterUseOperandIdx(Register Reg,
1055 const TargetRegisterInfo *TRI,
1056 bool isKill) const {
1057 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1058 const MachineOperand &MO = getOperand(i);
1059 if (!MO.isReg() || !MO.isUse())
1060 continue;
1061 Register MOReg = MO.getReg();
1062 if (!MOReg)
1063 continue;
1064 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(RegA: MOReg, RegB: Reg)))
1065 if (!isKill || MO.isKill())
1066 return i;
1067 }
1068 return -1;
1069}
1070
1071/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1072/// indicating if this instruction reads or writes Reg. This also considers
1073/// partial defines.
1074std::pair<bool,bool>
1075MachineInstr::readsWritesVirtualRegister(Register Reg,
1076 SmallVectorImpl<unsigned> *Ops) const {
1077 bool PartDef = false; // Partial redefine.
1078 bool FullDef = false; // Full define.
1079 bool Use = false;
1080
1081 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1082 const MachineOperand &MO = getOperand(i);
1083 if (!MO.isReg() || MO.getReg() != Reg)
1084 continue;
1085 if (Ops)
1086 Ops->push_back(Elt: i);
1087 if (MO.isUse())
1088 Use |= !MO.isUndef();
1089 else if (MO.getSubReg() && !MO.isUndef())
1090 // A partial def undef doesn't count as reading the register.
1091 PartDef = true;
1092 else
1093 FullDef = true;
1094 }
1095 // A partial redefine uses Reg unless there is also a full define.
1096 return std::make_pair(x: Use || (PartDef && !FullDef), y: PartDef || FullDef);
1097}
1098
1099/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1100/// the specified register or -1 if it is not found. If isDead is true, defs
1101/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1102/// also checks if there is a def of a super-register.
1103int MachineInstr::findRegisterDefOperandIdx(Register Reg,
1104 const TargetRegisterInfo *TRI,
1105 bool isDead, bool Overlap) const {
1106 bool isPhys = Reg.isPhysical();
1107 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1108 const MachineOperand &MO = getOperand(i);
1109 // Accept regmask operands when Overlap is set.
1110 // Ignore them when looking for a specific def operand (Overlap == false).
1111 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(PhysReg: Reg))
1112 return i;
1113 if (!MO.isReg() || !MO.isDef())
1114 continue;
1115 Register MOReg = MO.getReg();
1116 bool Found = (MOReg == Reg);
1117 if (!Found && TRI && isPhys && MOReg.isPhysical()) {
1118 if (Overlap)
1119 Found = TRI->regsOverlap(RegA: MOReg, RegB: Reg);
1120 else
1121 Found = TRI->isSubRegister(RegA: MOReg, RegB: Reg);
1122 }
1123 if (Found && (!isDead || MO.isDead()))
1124 return i;
1125 }
1126 return -1;
1127}
1128
1129/// findFirstPredOperandIdx() - Find the index of the first operand in the
1130/// operand list that is used to represent the predicate. It returns -1 if
1131/// none is found.
1132int MachineInstr::findFirstPredOperandIdx() const {
1133 // Don't call MCID.findFirstPredOperandIdx() because this variant
1134 // is sometimes called on an instruction that's not yet complete, and
1135 // so the number of operands is less than the MCID indicates. In
1136 // particular, the PTX target does this.
1137 const MCInstrDesc &MCID = getDesc();
1138 if (MCID.isPredicable()) {
1139 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1140 if (MCID.operands()[i].isPredicate())
1141 return i;
1142 }
1143
1144 return -1;
1145}
1146
1147// MachineOperand::TiedTo is 4 bits wide.
1148const unsigned TiedMax = 15;
1149
1150/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1151///
1152/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1153/// field. TiedTo can have these values:
1154///
1155/// 0: Operand is not tied to anything.
1156/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1157/// TiedMax: Tied to an operand >= TiedMax-1.
1158///
1159/// The tied def must be one of the first TiedMax operands on a normal
1160/// instruction. INLINEASM instructions allow more tied defs.
1161///
1162void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1163 MachineOperand &DefMO = getOperand(i: DefIdx);
1164 MachineOperand &UseMO = getOperand(i: UseIdx);
1165 assert(DefMO.isDef() && "DefIdx must be a def operand");
1166 assert(UseMO.isUse() && "UseIdx must be a use operand");
1167 assert(!DefMO.isTied() && "Def is already tied to another use");
1168 assert(!UseMO.isTied() && "Use is already tied to another def");
1169
1170 if (DefIdx < TiedMax)
1171 UseMO.TiedTo = DefIdx + 1;
1172 else {
1173 // Inline asm can use the group descriptors to find tied operands,
1174 // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1175 // but on normal instruction, the tied def must be within the first TiedMax
1176 // operands.
1177 assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
1178 "DefIdx out of range");
1179 UseMO.TiedTo = TiedMax;
1180 }
1181
1182 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1183 DefMO.TiedTo = std::min(a: UseIdx + 1, b: TiedMax);
1184}
1185
1186/// Given the index of a tied register operand, find the operand it is tied to.
1187/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1188/// which must exist.
1189unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1190 const MachineOperand &MO = getOperand(i: OpIdx);
1191 assert(MO.isTied() && "Operand isn't tied");
1192
1193 // Normally TiedTo is in range.
1194 if (MO.TiedTo < TiedMax)
1195 return MO.TiedTo - 1;
1196
1197 // Uses on normal instructions can be out of range.
1198 if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1199 // Normal tied defs must be in the 0..TiedMax-1 range.
1200 if (MO.isUse())
1201 return TiedMax - 1;
1202 // MO is a def. Search for the tied use.
1203 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1204 const MachineOperand &UseMO = getOperand(i);
1205 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1206 return i;
1207 }
1208 llvm_unreachable("Can't find tied use");
1209 }
1210
1211 if (getOpcode() == TargetOpcode::STATEPOINT) {
1212 // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1213 // on registers.
1214 StatepointOpers SO(this);
1215 unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1216 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");
1217 unsigned NumDefs = getNumDefs();
1218 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1219 while (!getOperand(i: CurUseIdx).isReg())
1220 CurUseIdx = StackMaps::getNextMetaArgIdx(MI: this, CurIdx: CurUseIdx);
1221 if (OpIdx == CurDefIdx)
1222 return CurUseIdx;
1223 if (OpIdx == CurUseIdx)
1224 return CurDefIdx;
1225 CurUseIdx = StackMaps::getNextMetaArgIdx(MI: this, CurIdx: CurUseIdx);
1226 }
1227 llvm_unreachable("Can't find tied use");
1228 }
1229
1230 // Now deal with inline asm by parsing the operand group descriptor flags.
1231 // Find the beginning of each operand group.
1232 SmallVector<unsigned, 8> GroupIdx;
1233 unsigned OpIdxGroup = ~0u;
1234 unsigned NumOps;
1235 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1236 i += NumOps) {
1237 const MachineOperand &FlagMO = getOperand(i);
1238 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1239 unsigned CurGroup = GroupIdx.size();
1240 GroupIdx.push_back(Elt: i);
1241 const InlineAsm::Flag F(FlagMO.getImm());
1242 NumOps = 1 + F.getNumOperandRegisters();
1243 // OpIdx belongs to this operand group.
1244 if (OpIdx > i && OpIdx < i + NumOps)
1245 OpIdxGroup = CurGroup;
1246 unsigned TiedGroup;
1247 if (!F.isUseOperandTiedToDef(Idx&: TiedGroup))
1248 continue;
1249 // Operands in this group are tied to operands in TiedGroup which must be
1250 // earlier. Find the number of operands between the two groups.
1251 unsigned Delta = i - GroupIdx[TiedGroup];
1252
1253 // OpIdx is a use tied to TiedGroup.
1254 if (OpIdxGroup == CurGroup)
1255 return OpIdx - Delta;
1256
1257 // OpIdx is a def tied to this use group.
1258 if (OpIdxGroup == TiedGroup)
1259 return OpIdx + Delta;
1260 }
1261 llvm_unreachable("Invalid tied operand on inline asm");
1262}
1263
1264/// clearKillInfo - Clears kill flags on all operands.
1265///
1266void MachineInstr::clearKillInfo() {
1267 for (MachineOperand &MO : operands()) {
1268 if (MO.isReg() && MO.isUse())
1269 MO.setIsKill(false);
1270 }
1271}
1272
1273void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1274 unsigned SubIdx,
1275 const TargetRegisterInfo &RegInfo) {
1276 if (ToReg.isPhysical()) {
1277 if (SubIdx)
1278 ToReg = RegInfo.getSubReg(Reg: ToReg, Idx: SubIdx);
1279 for (MachineOperand &MO : operands()) {
1280 if (!MO.isReg() || MO.getReg() != FromReg)
1281 continue;
1282 MO.substPhysReg(Reg: ToReg, RegInfo);
1283 }
1284 } else {
1285 for (MachineOperand &MO : operands()) {
1286 if (!MO.isReg() || MO.getReg() != FromReg)
1287 continue;
1288 MO.substVirtReg(Reg: ToReg, SubIdx, RegInfo);
1289 }
1290 }
1291}
1292
1293/// isSafeToMove - Return true if it is safe to move this instruction. If
1294/// SawStore is set to true, it means that there is a store (or call) between
1295/// the instruction's location and its intended destination.
1296bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1297 // Ignore stuff that we obviously can't move.
1298 //
1299 // Treat volatile loads as stores. This is not strictly necessary for
1300 // volatiles, but it is required for atomic loads. It is not allowed to move
1301 // a load across an atomic load with Ordering > Monotonic.
1302 if (mayStore() || isCall() || isPHI() ||
1303 (mayLoad() && hasOrderedMemoryRef())) {
1304 SawStore = true;
1305 return false;
1306 }
1307
1308 if (isPosition() || isDebugInstr() || isTerminator() ||
1309 mayRaiseFPException() || hasUnmodeledSideEffects() ||
1310 isJumpTableDebugInfo())
1311 return false;
1312
1313 // See if this instruction does a load. If so, we have to guarantee that the
1314 // loaded value doesn't change between the load and the its intended
1315 // destination. The check for isInvariantLoad gives the target the chance to
1316 // classify the load as always returning a constant, e.g. a constant pool
1317 // load.
1318 if (mayLoad() && !isDereferenceableInvariantLoad())
1319 // Otherwise, this is a real load. If there is a store between the load and
1320 // end of block, we can't move it.
1321 return !SawStore;
1322
1323 return true;
1324}
1325
1326static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
1327 bool UseTBAA, const MachineMemOperand *MMOa,
1328 const MachineMemOperand *MMOb) {
1329 // The following interface to AA is fashioned after DAGCombiner::isAlias and
1330 // operates with MachineMemOperand offset with some important assumptions:
1331 // - LLVM fundamentally assumes flat address spaces.
1332 // - MachineOperand offset can *only* result from legalization and cannot
1333 // affect queries other than the trivial case of overlap checking.
1334 // - These offsets never wrap and never step outside of allocated objects.
1335 // - There should never be any negative offsets here.
1336 //
1337 // FIXME: Modify API to hide this math from "user"
1338 // Even before we go to AA we can reason locally about some memory objects. It
1339 // can save compile time, and possibly catch some corner cases not currently
1340 // covered.
1341
1342 int64_t OffsetA = MMOa->getOffset();
1343 int64_t OffsetB = MMOb->getOffset();
1344 int64_t MinOffset = std::min(a: OffsetA, b: OffsetB);
1345
1346 LocationSize WidthA = MMOa->getSize();
1347 LocationSize WidthB = MMOb->getSize();
1348 bool KnownWidthA = WidthA.hasValue();
1349 bool KnownWidthB = WidthB.hasValue();
1350 bool BothMMONonScalable = !WidthA.isScalable() && !WidthB.isScalable();
1351
1352 const Value *ValA = MMOa->getValue();
1353 const Value *ValB = MMOb->getValue();
1354 bool SameVal = (ValA && ValB && (ValA == ValB));
1355 if (!SameVal) {
1356 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1357 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1358 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1359 return false;
1360 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1361 return false;
1362 if (PSVa && PSVb && (PSVa == PSVb))
1363 SameVal = true;
1364 }
1365
1366 if (SameVal && BothMMONonScalable) {
1367 if (!KnownWidthA || !KnownWidthB)
1368 return true;
1369 int64_t MaxOffset = std::max(a: OffsetA, b: OffsetB);
1370 int64_t LowWidth = (MinOffset == OffsetA)
1371 ? WidthA.getValue().getKnownMinValue()
1372 : WidthB.getValue().getKnownMinValue();
1373 return (MinOffset + LowWidth > MaxOffset);
1374 }
1375
1376 if (!AA)
1377 return true;
1378
1379 if (!ValA || !ValB)
1380 return true;
1381
1382 assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1383 assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1384
1385 // If Scalable Location Size has non-zero offset, Width + Offset does not work
1386 // at the moment
1387 if ((WidthA.isScalable() && OffsetA > 0) ||
1388 (WidthB.isScalable() && OffsetB > 0))
1389 return true;
1390
1391 int64_t OverlapA =
1392 KnownWidthA ? WidthA.getValue().getKnownMinValue() + OffsetA - MinOffset
1393 : MemoryLocation::UnknownSize;
1394 int64_t OverlapB =
1395 KnownWidthB ? WidthB.getValue().getKnownMinValue() + OffsetB - MinOffset
1396 : MemoryLocation::UnknownSize;
1397
1398 LocationSize LocA = (WidthA.isScalable() || !KnownWidthA)
1399 ? WidthA
1400 : LocationSize::precise(Value: OverlapA);
1401 LocationSize LocB = (WidthB.isScalable() || !KnownWidthB)
1402 ? WidthB
1403 : LocationSize::precise(Value: OverlapB);
1404
1405 return !AA->isNoAlias(
1406 LocA: MemoryLocation(ValA, LocA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1407 LocB: MemoryLocation(ValB, LocB, UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1408}
1409
1410bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1411 bool UseTBAA) const {
1412 const MachineFunction *MF = getMF();
1413 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1414 const MachineFrameInfo &MFI = MF->getFrameInfo();
1415
1416 // Exclude call instruction which may alter the memory but can not be handled
1417 // by this function.
1418 if (isCall() || Other.isCall())
1419 return true;
1420
1421 // If neither instruction stores to memory, they can't alias in any
1422 // meaningful way, even if they read from the same address.
1423 if (!mayStore() && !Other.mayStore())
1424 return false;
1425
1426 // Both instructions must be memory operations to be able to alias.
1427 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1428 return false;
1429
1430 // Let the target decide if memory accesses cannot possibly overlap.
1431 if (TII->areMemAccessesTriviallyDisjoint(MIa: *this, MIb: Other))
1432 return false;
1433
1434 // Memory operations without memory operands may access anything. Be
1435 // conservative and assume `MayAlias`.
1436 if (memoperands_empty() || Other.memoperands_empty())
1437 return true;
1438
1439 // Skip if there are too many memory operands.
1440 auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1441 if (NumChecks > TII->getMemOperandAACheckLimit())
1442 return true;
1443
1444 // Check each pair of memory operands from both instructions, which can't
1445 // alias only if all pairs won't alias.
1446 for (auto *MMOa : memoperands())
1447 for (auto *MMOb : Other.memoperands())
1448 if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1449 return true;
1450
1451 return false;
1452}
1453
1454/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1455/// or volatile memory reference, or if the information describing the memory
1456/// reference is not available. Return false if it is known to have no ordered
1457/// memory references.
1458bool MachineInstr::hasOrderedMemoryRef() const {
1459 // An instruction known never to access memory won't have a volatile access.
1460 if (!mayStore() &&
1461 !mayLoad() &&
1462 !isCall() &&
1463 !hasUnmodeledSideEffects())
1464 return false;
1465
1466 // Otherwise, if the instruction has no memory reference information,
1467 // conservatively assume it wasn't preserved.
1468 if (memoperands_empty())
1469 return true;
1470
1471 // Check if any of our memory operands are ordered.
1472 return llvm::any_of(Range: memoperands(), P: [](const MachineMemOperand *MMO) {
1473 return !MMO->isUnordered();
1474 });
1475}
1476
1477/// isDereferenceableInvariantLoad - Return true if this instruction will never
1478/// trap and is loading from a location whose value is invariant across a run of
1479/// this function.
1480bool MachineInstr::isDereferenceableInvariantLoad() const {
1481 // If the instruction doesn't load at all, it isn't an invariant load.
1482 if (!mayLoad())
1483 return false;
1484
1485 // If the instruction has lost its memoperands, conservatively assume that
1486 // it may not be an invariant load.
1487 if (memoperands_empty())
1488 return false;
1489
1490 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1491
1492 for (MachineMemOperand *MMO : memoperands()) {
1493 if (!MMO->isUnordered())
1494 // If the memory operand has ordering side effects, we can't move the
1495 // instruction. Such an instruction is technically an invariant load,
1496 // but the caller code would need updated to expect that.
1497 return false;
1498 if (MMO->isStore()) return false;
1499 if (MMO->isInvariant() && MMO->isDereferenceable())
1500 continue;
1501
1502 // A load from a constant PseudoSourceValue is invariant.
1503 if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
1504 if (PSV->isConstant(&MFI))
1505 continue;
1506 }
1507
1508 // Otherwise assume conservatively.
1509 return false;
1510 }
1511
1512 // Everything checks out.
1513 return true;
1514}
1515
1516/// isConstantValuePHI - If the specified instruction is a PHI that always
1517/// merges together the same virtual register, return the register, otherwise
1518/// return 0.
1519unsigned MachineInstr::isConstantValuePHI() const {
1520 if (!isPHI())
1521 return 0;
1522 assert(getNumOperands() >= 3 &&
1523 "It's illegal to have a PHI without source operands");
1524
1525 Register Reg = getOperand(i: 1).getReg();
1526 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1527 if (getOperand(i).getReg() != Reg)
1528 return 0;
1529 return Reg;
1530}
1531
1532bool MachineInstr::hasUnmodeledSideEffects() const {
1533 if (hasProperty(MCFlag: MCID::UnmodeledSideEffects))
1534 return true;
1535 if (isInlineAsm()) {
1536 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1537 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1538 return true;
1539 }
1540
1541 return false;
1542}
1543
1544bool MachineInstr::isLoadFoldBarrier() const {
1545 return mayStore() || isCall() ||
1546 (hasUnmodeledSideEffects() && !isPseudoProbe());
1547}
1548
1549/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1550///
1551bool MachineInstr::allDefsAreDead() const {
1552 for (const MachineOperand &MO : operands()) {
1553 if (!MO.isReg() || MO.isUse())
1554 continue;
1555 if (!MO.isDead())
1556 return false;
1557 }
1558 return true;
1559}
1560
1561bool MachineInstr::allImplicitDefsAreDead() const {
1562 for (const MachineOperand &MO : implicit_operands()) {
1563 if (!MO.isReg() || MO.isUse())
1564 continue;
1565 if (!MO.isDead())
1566 return false;
1567 }
1568 return true;
1569}
1570
1571/// copyImplicitOps - Copy implicit register operands from specified
1572/// instruction to this instruction.
1573void MachineInstr::copyImplicitOps(MachineFunction &MF,
1574 const MachineInstr &MI) {
1575 for (const MachineOperand &MO :
1576 llvm::drop_begin(RangeOrContainer: MI.operands(), N: MI.getDesc().getNumOperands()))
1577 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1578 addOperand(MF, Op: MO);
1579}
1580
1581bool MachineInstr::hasComplexRegisterTies() const {
1582 const MCInstrDesc &MCID = getDesc();
1583 if (MCID.Opcode == TargetOpcode::STATEPOINT)
1584 return true;
1585 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1586 const auto &Operand = getOperand(i: I);
1587 if (!Operand.isReg() || Operand.isDef())
1588 // Ignore the defined registers as MCID marks only the uses as tied.
1589 continue;
1590 int ExpectedTiedIdx = MCID.getOperandConstraint(OpNum: I, Constraint: MCOI::TIED_TO);
1591 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(OpIdx: I)) : -1;
1592 if (ExpectedTiedIdx != TiedIdx)
1593 return true;
1594 }
1595 return false;
1596}
1597
1598LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1599 const MachineRegisterInfo &MRI) const {
1600 const MachineOperand &Op = getOperand(i: OpIdx);
1601 if (!Op.isReg())
1602 return LLT{};
1603
1604 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1605 return MRI.getType(Reg: Op.getReg());
1606
1607 auto &OpInfo = getDesc().operands()[OpIdx];
1608 if (!OpInfo.isGenericType())
1609 return MRI.getType(Reg: Op.getReg());
1610
1611 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1612 return LLT{};
1613
1614 LLT TypeToPrint = MRI.getType(Reg: Op.getReg());
1615 // Don't mark the type index printed if it wasn't actually printed: maybe
1616 // another operand with the same type index has an actual type attached:
1617 if (TypeToPrint.isValid())
1618 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1619 return TypeToPrint;
1620}
1621
1622#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1623LLVM_DUMP_METHOD void MachineInstr::dump() const {
1624 dbgs() << " ";
1625 print(dbgs());
1626}
1627
1628LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1629 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1630 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1631 if (Depth >= MaxDepth)
1632 return;
1633 if (!AlreadySeenInstrs.insert(this).second)
1634 return;
1635 // PadToColumn always inserts at least one space.
1636 // Don't mess up the alignment if we don't want any space.
1637 if (Depth)
1638 fdbgs().PadToColumn(Depth * 2);
1639 print(fdbgs());
1640 for (const MachineOperand &MO : operands()) {
1641 if (!MO.isReg() || MO.isDef())
1642 continue;
1643 Register Reg = MO.getReg();
1644 if (Reg.isPhysical())
1645 continue;
1646 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1647 if (NewMI == nullptr)
1648 continue;
1649 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1650 }
1651}
1652
1653LLVM_DUMP_METHOD void MachineInstr::dumpr(const MachineRegisterInfo &MRI,
1654 unsigned MaxDepth) const {
1655 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1656 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1657}
1658#endif
1659
1660void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1661 bool SkipDebugLoc, bool AddNewLine,
1662 const TargetInstrInfo *TII) const {
1663 const Module *M = nullptr;
1664 const Function *F = nullptr;
1665 if (const MachineFunction *MF = getMFIfAvailable(MI: *this)) {
1666 F = &MF->getFunction();
1667 M = F->getParent();
1668 if (!TII)
1669 TII = MF->getSubtarget().getInstrInfo();
1670 }
1671
1672 ModuleSlotTracker MST(M);
1673 if (F)
1674 MST.incorporateFunction(F: *F);
1675 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1676}
1677
1678void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1679 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1680 bool AddNewLine, const TargetInstrInfo *TII) const {
1681 // We can be a bit tidier if we know the MachineFunction.
1682 const TargetRegisterInfo *TRI = nullptr;
1683 const MachineRegisterInfo *MRI = nullptr;
1684 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1685 tryToGetTargetInfo(MI: *this, TRI, MRI, IntrinsicInfo, TII);
1686
1687 if (isCFIInstruction())
1688 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1689
1690 SmallBitVector PrintedTypes(8);
1691 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1692 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1693 if (!ShouldPrintRegisterTies)
1694 return 0U;
1695 const MachineOperand &MO = getOperand(i: OpIdx);
1696 if (MO.isReg() && MO.isTied() && !MO.isDef())
1697 return findTiedOperandIdx(OpIdx);
1698 return 0U;
1699 };
1700 unsigned StartOp = 0;
1701 unsigned e = getNumOperands();
1702
1703 // Print explicitly defined operands on the left of an assignment syntax.
1704 while (StartOp < e) {
1705 const MachineOperand &MO = getOperand(i: StartOp);
1706 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1707 break;
1708
1709 if (StartOp != 0)
1710 OS << ", ";
1711
1712 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: StartOp, PrintedTypes, MRI: *MRI) : LLT{};
1713 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1714 MO.print(os&: OS, MST, TypeToPrint, OpIdx: StartOp, /*PrintDef=*/false, IsStandalone,
1715 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1716 ++StartOp;
1717 }
1718
1719 if (StartOp != 0)
1720 OS << " = ";
1721
1722 if (getFlag(Flag: MachineInstr::FrameSetup))
1723 OS << "frame-setup ";
1724 if (getFlag(Flag: MachineInstr::FrameDestroy))
1725 OS << "frame-destroy ";
1726 if (getFlag(Flag: MachineInstr::FmNoNans))
1727 OS << "nnan ";
1728 if (getFlag(Flag: MachineInstr::FmNoInfs))
1729 OS << "ninf ";
1730 if (getFlag(Flag: MachineInstr::FmNsz))
1731 OS << "nsz ";
1732 if (getFlag(Flag: MachineInstr::FmArcp))
1733 OS << "arcp ";
1734 if (getFlag(Flag: MachineInstr::FmContract))
1735 OS << "contract ";
1736 if (getFlag(Flag: MachineInstr::FmAfn))
1737 OS << "afn ";
1738 if (getFlag(Flag: MachineInstr::FmReassoc))
1739 OS << "reassoc ";
1740 if (getFlag(Flag: MachineInstr::NoUWrap))
1741 OS << "nuw ";
1742 if (getFlag(Flag: MachineInstr::NoSWrap))
1743 OS << "nsw ";
1744 if (getFlag(Flag: MachineInstr::IsExact))
1745 OS << "exact ";
1746 if (getFlag(Flag: MachineInstr::NoFPExcept))
1747 OS << "nofpexcept ";
1748 if (getFlag(Flag: MachineInstr::NoMerge))
1749 OS << "nomerge ";
1750 if (getFlag(Flag: MachineInstr::NonNeg))
1751 OS << "nneg ";
1752 if (getFlag(Flag: MachineInstr::Disjoint))
1753 OS << "disjoint ";
1754
1755 // Print the opcode name.
1756 if (TII)
1757 OS << TII->getName(Opcode: getOpcode());
1758 else
1759 OS << "UNKNOWN";
1760
1761 if (SkipOpers)
1762 return;
1763
1764 // Print the rest of the operands.
1765 bool FirstOp = true;
1766 unsigned AsmDescOp = ~0u;
1767 unsigned AsmOpCount = 0;
1768
1769 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1770 // Print asm string.
1771 OS << " ";
1772 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1773 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, MRI: *MRI) : LLT{};
1774 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1775 getOperand(i: OpIdx).print(os&: OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1776 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1777 IntrinsicInfo);
1778
1779 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1780 unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1781 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1782 OS << " [sideeffect]";
1783 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1784 OS << " [mayload]";
1785 if (ExtraInfo & InlineAsm::Extra_MayStore)
1786 OS << " [maystore]";
1787 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1788 OS << " [isconvergent]";
1789 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1790 OS << " [alignstack]";
1791 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1792 OS << " [attdialect]";
1793 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1794 OS << " [inteldialect]";
1795
1796 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1797 FirstOp = false;
1798 }
1799
1800 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1801 const MachineOperand &MO = getOperand(i);
1802
1803 if (FirstOp) FirstOp = false; else OS << ",";
1804 OS << " ";
1805
1806 if (isDebugValueLike() && MO.isMetadata()) {
1807 // Pretty print DBG_VALUE* instructions.
1808 auto *DIV = dyn_cast<DILocalVariable>(Val: MO.getMetadata());
1809 if (DIV && !DIV->getName().empty())
1810 OS << "!\"" << DIV->getName() << '\"';
1811 else {
1812 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: i, PrintedTypes, MRI: *MRI) : LLT{};
1813 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1814 MO.print(os&: OS, MST, TypeToPrint, OpIdx: i, /*PrintDef=*/true, IsStandalone,
1815 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1816 }
1817 } else if (isDebugLabel() && MO.isMetadata()) {
1818 // Pretty print DBG_LABEL instructions.
1819 auto *DIL = dyn_cast<DILabel>(Val: MO.getMetadata());
1820 if (DIL && !DIL->getName().empty())
1821 OS << "\"" << DIL->getName() << '\"';
1822 else {
1823 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: i, PrintedTypes, MRI: *MRI) : LLT{};
1824 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1825 MO.print(os&: OS, MST, TypeToPrint, OpIdx: i, /*PrintDef=*/true, IsStandalone,
1826 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1827 }
1828 } else if (i == AsmDescOp && MO.isImm()) {
1829 // Pretty print the inline asm operand descriptor.
1830 OS << '$' << AsmOpCount++;
1831 unsigned Flag = MO.getImm();
1832 const InlineAsm::Flag F(Flag);
1833 OS << ":[";
1834 OS << F.getKindName();
1835
1836 unsigned RCID;
1837 if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RC&: RCID)) {
1838 if (TRI) {
1839 OS << ':' << TRI->getRegClassName(Class: TRI->getRegClass(i: RCID));
1840 } else
1841 OS << ":RC" << RCID;
1842 }
1843
1844 if (F.isMemKind()) {
1845 const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
1846 OS << ":" << InlineAsm::getMemConstraintName(C: MCID);
1847 }
1848
1849 unsigned TiedTo;
1850 if (F.isUseOperandTiedToDef(Idx&: TiedTo))
1851 OS << " tiedto:$" << TiedTo;
1852
1853 if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() ||
1854 F.isRegUseKind()) &&
1855 F.getRegMayBeFolded()) {
1856 OS << " foldable";
1857 }
1858
1859 OS << ']';
1860
1861 // Compute the index of the next operand descriptor.
1862 AsmDescOp += 1 + F.getNumOperandRegisters();
1863 } else {
1864 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx: i, PrintedTypes, MRI: *MRI) : LLT{};
1865 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1866 if (MO.isImm() && isOperandSubregIdx(OpIdx: i))
1867 MachineOperand::printSubRegIdx(OS, Index: MO.getImm(), TRI);
1868 else
1869 MO.print(os&: OS, MST, TypeToPrint, OpIdx: i, /*PrintDef=*/true, IsStandalone,
1870 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1871 }
1872 }
1873
1874 // Print any optional symbols attached to this instruction as-if they were
1875 // operands.
1876 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1877 if (!FirstOp) {
1878 FirstOp = false;
1879 OS << ',';
1880 }
1881 OS << " pre-instr-symbol ";
1882 MachineOperand::printSymbol(OS, Sym&: *PreInstrSymbol);
1883 }
1884 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1885 if (!FirstOp) {
1886 FirstOp = false;
1887 OS << ',';
1888 }
1889 OS << " post-instr-symbol ";
1890 MachineOperand::printSymbol(OS, Sym&: *PostInstrSymbol);
1891 }
1892 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1893 if (!FirstOp) {
1894 FirstOp = false;
1895 OS << ',';
1896 }
1897 OS << " heap-alloc-marker ";
1898 HeapAllocMarker->printAsOperand(OS, MST);
1899 }
1900 if (MDNode *PCSections = getPCSections()) {
1901 if (!FirstOp) {
1902 FirstOp = false;
1903 OS << ',';
1904 }
1905 OS << " pcsections ";
1906 PCSections->printAsOperand(OS, MST);
1907 }
1908 if (MDNode *MMRA = getMMRAMetadata()) {
1909 if (!FirstOp) {
1910 FirstOp = false;
1911 OS << ',';
1912 }
1913 OS << " mmra ";
1914 MMRA->printAsOperand(OS, MST);
1915 }
1916 if (uint32_t CFIType = getCFIType()) {
1917 if (!FirstOp)
1918 OS << ',';
1919 OS << " cfi-type " << CFIType;
1920 }
1921
1922 if (DebugInstrNum) {
1923 if (!FirstOp)
1924 OS << ",";
1925 OS << " debug-instr-number " << DebugInstrNum;
1926 }
1927
1928 if (!SkipDebugLoc) {
1929 if (const DebugLoc &DL = getDebugLoc()) {
1930 if (!FirstOp)
1931 OS << ',';
1932 OS << " debug-location ";
1933 DL->printAsOperand(OS, MST);
1934 }
1935 }
1936
1937 if (!memoperands_empty()) {
1938 SmallVector<StringRef, 0> SSNs;
1939 const LLVMContext *Context = nullptr;
1940 std::unique_ptr<LLVMContext> CtxPtr;
1941 const MachineFrameInfo *MFI = nullptr;
1942 if (const MachineFunction *MF = getMFIfAvailable(MI: *this)) {
1943 MFI = &MF->getFrameInfo();
1944 Context = &MF->getFunction().getContext();
1945 } else {
1946 CtxPtr = std::make_unique<LLVMContext>();
1947 Context = CtxPtr.get();
1948 }
1949
1950 OS << " :: ";
1951 bool NeedComma = false;
1952 for (const MachineMemOperand *Op : memoperands()) {
1953 if (NeedComma)
1954 OS << ", ";
1955 Op->print(OS, MST, SSNs, Context: *Context, MFI, TII);
1956 NeedComma = true;
1957 }
1958 }
1959
1960 if (SkipDebugLoc)
1961 return;
1962
1963 bool HaveSemi = false;
1964
1965 // Print debug location information.
1966 if (const DebugLoc &DL = getDebugLoc()) {
1967 if (!HaveSemi) {
1968 OS << ';';
1969 HaveSemi = true;
1970 }
1971 OS << ' ';
1972 DL.print(OS);
1973 }
1974
1975 // Print extra comments for DEBUG_VALUE and friends if they are well-formed.
1976 if ((isNonListDebugValue() && getNumOperands() >= 4) ||
1977 (isDebugValueList() && getNumOperands() >= 2) ||
1978 (isDebugRef() && getNumOperands() >= 3)) {
1979 if (getDebugVariableOp().isMetadata()) {
1980 if (!HaveSemi) {
1981 OS << ";";
1982 HaveSemi = true;
1983 }
1984 auto *DV = getDebugVariable();
1985 OS << " line no:" << DV->getLine();
1986 if (isIndirectDebugValue())
1987 OS << " indirect";
1988 }
1989 }
1990 // TODO: DBG_LABEL
1991
1992 if (AddNewLine)
1993 OS << '\n';
1994}
1995
1996bool MachineInstr::addRegisterKilled(Register IncomingReg,
1997 const TargetRegisterInfo *RegInfo,
1998 bool AddIfNotFound) {
1999 bool isPhysReg = IncomingReg.isPhysical();
2000 bool hasAliases = isPhysReg &&
2001 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
2002 bool Found = false;
2003 SmallVector<unsigned,4> DeadOps;
2004 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2005 MachineOperand &MO = getOperand(i);
2006 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
2007 continue;
2008
2009 // DEBUG_VALUE nodes do not contribute to code generation and should
2010 // always be ignored. Failure to do so may result in trying to modify
2011 // KILL flags on DEBUG_VALUE nodes.
2012 if (MO.isDebug())
2013 continue;
2014
2015 Register Reg = MO.getReg();
2016 if (!Reg)
2017 continue;
2018
2019 if (Reg == IncomingReg) {
2020 if (!Found) {
2021 if (MO.isKill())
2022 // The register is already marked kill.
2023 return true;
2024 if (isPhysReg && isRegTiedToDefOperand(UseOpIdx: i))
2025 // Two-address uses of physregs must not be marked kill.
2026 return true;
2027 MO.setIsKill();
2028 Found = true;
2029 }
2030 } else if (hasAliases && MO.isKill() && Reg.isPhysical()) {
2031 // A super-register kill already exists.
2032 if (RegInfo->isSuperRegister(RegA: IncomingReg, RegB: Reg))
2033 return true;
2034 if (RegInfo->isSubRegister(RegA: IncomingReg, RegB: Reg))
2035 DeadOps.push_back(Elt: i);
2036 }
2037 }
2038
2039 // Trim unneeded kill operands.
2040 while (!DeadOps.empty()) {
2041 unsigned OpIdx = DeadOps.back();
2042 if (getOperand(i: OpIdx).isImplicit() &&
2043 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
2044 removeOperand(OpNo: OpIdx);
2045 else
2046 getOperand(i: OpIdx).setIsKill(false);
2047 DeadOps.pop_back();
2048 }
2049
2050 // If not found, this means an alias of one of the operands is killed. Add a
2051 // new implicit operand if required.
2052 if (!Found && AddIfNotFound) {
2053 addOperand(Op: MachineOperand::CreateReg(Reg: IncomingReg,
2054 isDef: false /*IsDef*/,
2055 isImp: true /*IsImp*/,
2056 isKill: true /*IsKill*/));
2057 return true;
2058 }
2059 return Found;
2060}
2061
2062void MachineInstr::clearRegisterKills(Register Reg,
2063 const TargetRegisterInfo *RegInfo) {
2064 if (!Reg.isPhysical())
2065 RegInfo = nullptr;
2066 for (MachineOperand &MO : operands()) {
2067 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
2068 continue;
2069 Register OpReg = MO.getReg();
2070 if ((RegInfo && RegInfo->regsOverlap(RegA: Reg, RegB: OpReg)) || Reg == OpReg)
2071 MO.setIsKill(false);
2072 }
2073}
2074
2075bool MachineInstr::addRegisterDead(Register Reg,
2076 const TargetRegisterInfo *RegInfo,
2077 bool AddIfNotFound) {
2078 bool isPhysReg = Reg.isPhysical();
2079 bool hasAliases = isPhysReg &&
2080 MCRegAliasIterator(Reg, RegInfo, false).isValid();
2081 bool Found = false;
2082 SmallVector<unsigned,4> DeadOps;
2083 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2084 MachineOperand &MO = getOperand(i);
2085 if (!MO.isReg() || !MO.isDef())
2086 continue;
2087 Register MOReg = MO.getReg();
2088 if (!MOReg)
2089 continue;
2090
2091 if (MOReg == Reg) {
2092 MO.setIsDead();
2093 Found = true;
2094 } else if (hasAliases && MO.isDead() && MOReg.isPhysical()) {
2095 // There exists a super-register that's marked dead.
2096 if (RegInfo->isSuperRegister(RegA: Reg, RegB: MOReg))
2097 return true;
2098 if (RegInfo->isSubRegister(RegA: Reg, RegB: MOReg))
2099 DeadOps.push_back(Elt: i);
2100 }
2101 }
2102
2103 // Trim unneeded dead operands.
2104 while (!DeadOps.empty()) {
2105 unsigned OpIdx = DeadOps.back();
2106 if (getOperand(i: OpIdx).isImplicit() &&
2107 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
2108 removeOperand(OpNo: OpIdx);
2109 else
2110 getOperand(i: OpIdx).setIsDead(false);
2111 DeadOps.pop_back();
2112 }
2113
2114 // If not found, this means an alias of one of the operands is dead. Add a
2115 // new implicit operand if required.
2116 if (Found || !AddIfNotFound)
2117 return Found;
2118
2119 addOperand(Op: MachineOperand::CreateReg(Reg,
2120 isDef: true /*IsDef*/,
2121 isImp: true /*IsImp*/,
2122 isKill: false /*IsKill*/,
2123 isDead: true /*IsDead*/));
2124 return true;
2125}
2126
2127void MachineInstr::clearRegisterDeads(Register Reg) {
2128 for (MachineOperand &MO : operands()) {
2129 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2130 continue;
2131 MO.setIsDead(false);
2132 }
2133}
2134
2135void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
2136 for (MachineOperand &MO : operands()) {
2137 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2138 continue;
2139 MO.setIsUndef(IsUndef);
2140 }
2141}
2142
2143void MachineInstr::addRegisterDefined(Register Reg,
2144 const TargetRegisterInfo *RegInfo) {
2145 if (Reg.isPhysical()) {
2146 MachineOperand *MO = findRegisterDefOperand(Reg, TRI: RegInfo, isDead: false, Overlap: false);
2147 if (MO)
2148 return;
2149 } else {
2150 for (const MachineOperand &MO : operands()) {
2151 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2152 MO.getSubReg() == 0)
2153 return;
2154 }
2155 }
2156 addOperand(Op: MachineOperand::CreateReg(Reg,
2157 isDef: true /*IsDef*/,
2158 isImp: true /*IsImp*/));
2159}
2160
2161void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
2162 const TargetRegisterInfo &TRI) {
2163 bool HasRegMask = false;
2164 for (MachineOperand &MO : operands()) {
2165 if (MO.isRegMask()) {
2166 HasRegMask = true;
2167 continue;
2168 }
2169 if (!MO.isReg() || !MO.isDef()) continue;
2170 Register Reg = MO.getReg();
2171 if (!Reg.isPhysical())
2172 continue;
2173 // If there are no uses, including partial uses, the def is dead.
2174 if (llvm::none_of(Range&: UsedRegs,
2175 P: [&](MCRegister Use) { return TRI.regsOverlap(RegA: Use, RegB: Reg); }))
2176 MO.setIsDead();
2177 }
2178
2179 // This is a call with a register mask operand.
2180 // Mask clobbers are always dead, so add defs for the non-dead defines.
2181 if (HasRegMask)
2182 for (const Register &UsedReg : UsedRegs)
2183 addRegisterDefined(Reg: UsedReg, RegInfo: &TRI);
2184}
2185
2186unsigned
2187MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
2188 // Build up a buffer of hash code components.
2189 SmallVector<size_t, 16> HashComponents;
2190 HashComponents.reserve(N: MI->getNumOperands() + 1);
2191 HashComponents.push_back(Elt: MI->getOpcode());
2192 for (const MachineOperand &MO : MI->operands()) {
2193 if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())
2194 continue; // Skip virtual register defs.
2195
2196 HashComponents.push_back(Elt: hash_value(MO));
2197 }
2198 return hash_combine_range(first: HashComponents.begin(), last: HashComponents.end());
2199}
2200
2201void MachineInstr::emitError(StringRef Msg) const {
2202 // Find the source location cookie.
2203 uint64_t LocCookie = 0;
2204 const MDNode *LocMD = nullptr;
2205 for (unsigned i = getNumOperands(); i != 0; --i) {
2206 if (getOperand(i: i-1).isMetadata() &&
2207 (LocMD = getOperand(i: i-1).getMetadata()) &&
2208 LocMD->getNumOperands() != 0) {
2209 if (const ConstantInt *CI =
2210 mdconst::dyn_extract<ConstantInt>(MD: LocMD->getOperand(I: 0))) {
2211 LocCookie = CI->getZExtValue();
2212 break;
2213 }
2214 }
2215 }
2216
2217 if (const MachineBasicBlock *MBB = getParent())
2218 if (const MachineFunction *MF = MBB->getParent())
2219 return MF->getFunction().getContext().emitError(LocCookie, ErrorStr: Msg);
2220 report_fatal_error(reason: Msg);
2221}
2222
2223MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2224 const MCInstrDesc &MCID, bool IsIndirect,
2225 Register Reg, const MDNode *Variable,
2226 const MDNode *Expr) {
2227 assert(isa<DILocalVariable>(Variable) && "not a variable");
2228 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2229 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2230 "Expected inlined-at fields to agree");
2231 auto MIB = BuildMI(MF, MIMD: DL, MCID).addReg(RegNo: Reg);
2232 if (IsIndirect)
2233 MIB.addImm(Val: 0U);
2234 else
2235 MIB.addReg(RegNo: 0U);
2236 return MIB.addMetadata(MD: Variable).addMetadata(MD: Expr);
2237}
2238
2239MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2240 const MCInstrDesc &MCID, bool IsIndirect,
2241 ArrayRef<MachineOperand> DebugOps,
2242 const MDNode *Variable, const MDNode *Expr) {
2243 assert(isa<DILocalVariable>(Variable) && "not a variable");
2244 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2245 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2246 "Expected inlined-at fields to agree");
2247 if (MCID.Opcode == TargetOpcode::DBG_VALUE) {
2248 assert(DebugOps.size() == 1 &&
2249 "DBG_VALUE must contain exactly one debug operand");
2250 MachineOperand DebugOp = DebugOps[0];
2251 if (DebugOp.isReg())
2252 return BuildMI(MF, DL, MCID, IsIndirect, Reg: DebugOp.getReg(), Variable,
2253 Expr);
2254
2255 auto MIB = BuildMI(MF, MIMD: DL, MCID).add(MO: DebugOp);
2256 if (IsIndirect)
2257 MIB.addImm(Val: 0U);
2258 else
2259 MIB.addReg(RegNo: 0U);
2260 return MIB.addMetadata(MD: Variable).addMetadata(MD: Expr);
2261 }
2262
2263 auto MIB = BuildMI(MF, MIMD: DL, MCID);
2264 MIB.addMetadata(MD: Variable).addMetadata(MD: Expr);
2265 for (const MachineOperand &DebugOp : DebugOps)
2266 if (DebugOp.isReg())
2267 MIB.addReg(RegNo: DebugOp.getReg());
2268 else
2269 MIB.add(MO: DebugOp);
2270 return MIB;
2271}
2272
2273MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2274 MachineBasicBlock::iterator I,
2275 const DebugLoc &DL, const MCInstrDesc &MCID,
2276 bool IsIndirect, Register Reg,
2277 const MDNode *Variable, const MDNode *Expr) {
2278 MachineFunction &MF = *BB.getParent();
2279 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2280 BB.insert(I, MI);
2281 return MachineInstrBuilder(MF, MI);
2282}
2283
2284MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2285 MachineBasicBlock::iterator I,
2286 const DebugLoc &DL, const MCInstrDesc &MCID,
2287 bool IsIndirect,
2288 ArrayRef<MachineOperand> DebugOps,
2289 const MDNode *Variable, const MDNode *Expr) {
2290 MachineFunction &MF = *BB.getParent();
2291 MachineInstr *MI =
2292 BuildMI(MF, DL, MCID, IsIndirect, DebugOps, Variable, Expr);
2293 BB.insert(I, MI);
2294 return MachineInstrBuilder(MF, *MI);
2295}
2296
2297/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2298/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2299static const DIExpression *
2300computeExprForSpill(const MachineInstr &MI,
2301 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2302 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2303 "Expected inlined-at fields to agree");
2304
2305 const DIExpression *Expr = MI.getDebugExpression();
2306 if (MI.isIndirectDebugValue()) {
2307 assert(MI.getDebugOffset().getImm() == 0 &&
2308 "DBG_VALUE with nonzero offset");
2309 Expr = DIExpression::prepend(Expr, Flags: DIExpression::DerefBefore);
2310 } else if (MI.isDebugValueList()) {
2311 // We will replace the spilled register with a frame index, so
2312 // immediately deref all references to the spilled register.
2313 std::array<uint64_t, 1> Ops{._M_elems: {dwarf::DW_OP_deref}};
2314 for (const MachineOperand *Op : SpilledOperands) {
2315 unsigned OpIdx = MI.getDebugOperandIndex(Op);
2316 Expr = DIExpression::appendOpsToArg(Expr, Ops, ArgNo: OpIdx);
2317 }
2318 }
2319 return Expr;
2320}
2321static const DIExpression *computeExprForSpill(const MachineInstr &MI,
2322 Register SpillReg) {
2323 assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");
2324 SmallVector<const MachineOperand *> SpillOperands;
2325 for (const MachineOperand &Op : MI.getDebugOperandsForReg(Reg: SpillReg))
2326 SpillOperands.push_back(Elt: &Op);
2327 return computeExprForSpill(MI, SpilledOperands&: SpillOperands);
2328}
2329
2330MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2331 MachineBasicBlock::iterator I,
2332 const MachineInstr &Orig,
2333 int FrameIndex, Register SpillReg) {
2334 assert(!Orig.isDebugRef() &&
2335 "DBG_INSTR_REF should not reference a virtual register.");
2336 const DIExpression *Expr = computeExprForSpill(MI: Orig, SpillReg);
2337 MachineInstrBuilder NewMI =
2338 BuildMI(BB, I, MIMD: Orig.getDebugLoc(), MCID: Orig.getDesc());
2339 // Non-Variadic Operands: Location, Offset, Variable, Expression
2340 // Variadic Operands: Variable, Expression, Locations...
2341 if (Orig.isNonListDebugValue())
2342 NewMI.addFrameIndex(Idx: FrameIndex).addImm(Val: 0U);
2343 NewMI.addMetadata(MD: Orig.getDebugVariable()).addMetadata(MD: Expr);
2344 if (Orig.isDebugValueList()) {
2345 for (const MachineOperand &Op : Orig.debug_operands())
2346 if (Op.isReg() && Op.getReg() == SpillReg)
2347 NewMI.addFrameIndex(Idx: FrameIndex);
2348 else
2349 NewMI.add(MO: MachineOperand(Op));
2350 }
2351 return NewMI;
2352}
2353MachineInstr *llvm::buildDbgValueForSpill(
2354 MachineBasicBlock &BB, MachineBasicBlock::iterator I,
2355 const MachineInstr &Orig, int FrameIndex,
2356 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2357 const DIExpression *Expr = computeExprForSpill(MI: Orig, SpilledOperands);
2358 MachineInstrBuilder NewMI =
2359 BuildMI(BB, I, MIMD: Orig.getDebugLoc(), MCID: Orig.getDesc());
2360 // Non-Variadic Operands: Location, Offset, Variable, Expression
2361 // Variadic Operands: Variable, Expression, Locations...
2362 if (Orig.isNonListDebugValue())
2363 NewMI.addFrameIndex(Idx: FrameIndex).addImm(Val: 0U);
2364 NewMI.addMetadata(MD: Orig.getDebugVariable()).addMetadata(MD: Expr);
2365 if (Orig.isDebugValueList()) {
2366 for (const MachineOperand &Op : Orig.debug_operands())
2367 if (is_contained(Range&: SpilledOperands, Element: &Op))
2368 NewMI.addFrameIndex(Idx: FrameIndex);
2369 else
2370 NewMI.add(MO: MachineOperand(Op));
2371 }
2372 return NewMI;
2373}
2374
2375void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex,
2376 Register Reg) {
2377 const DIExpression *Expr = computeExprForSpill(MI: Orig, SpillReg: Reg);
2378 if (Orig.isNonListDebugValue())
2379 Orig.getDebugOffset().ChangeToImmediate(ImmVal: 0U);
2380 for (MachineOperand &Op : Orig.getDebugOperandsForReg(Reg))
2381 Op.ChangeToFrameIndex(Idx: FrameIndex);
2382 Orig.getDebugExpressionOp().setMetadata(Expr);
2383}
2384
2385void MachineInstr::collectDebugValues(
2386 SmallVectorImpl<MachineInstr *> &DbgValues) {
2387 MachineInstr &MI = *this;
2388 if (!MI.getOperand(i: 0).isReg())
2389 return;
2390
2391 MachineBasicBlock::iterator DI = MI; ++DI;
2392 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2393 DI != DE; ++DI) {
2394 if (!DI->isDebugValue())
2395 return;
2396 if (DI->hasDebugOperandForReg(Reg: MI.getOperand(i: 0).getReg()))
2397 DbgValues.push_back(Elt: &*DI);
2398 }
2399}
2400
2401void MachineInstr::changeDebugValuesDefReg(Register Reg) {
2402 // Collect matching debug values.
2403 SmallVector<MachineInstr *, 2> DbgValues;
2404
2405 if (!getOperand(i: 0).isReg())
2406 return;
2407
2408 Register DefReg = getOperand(i: 0).getReg();
2409 auto *MRI = getRegInfo();
2410 for (auto &MO : MRI->use_operands(Reg: DefReg)) {
2411 auto *DI = MO.getParent();
2412 if (!DI->isDebugValue())
2413 continue;
2414 if (DI->hasDebugOperandForReg(Reg: DefReg)) {
2415 DbgValues.push_back(Elt: DI);
2416 }
2417 }
2418
2419 // Propagate Reg to debug value instructions.
2420 for (auto *DBI : DbgValues)
2421 for (MachineOperand &Op : DBI->getDebugOperandsForReg(Reg: DefReg))
2422 Op.setReg(Reg);
2423}
2424
2425using MMOList = SmallVector<const MachineMemOperand *, 2>;
2426
2427static LocationSize getSpillSlotSize(const MMOList &Accesses,
2428 const MachineFrameInfo &MFI) {
2429 uint64_t Size = 0;
2430 for (const auto *A : Accesses) {
2431 if (MFI.isSpillSlotObjectIndex(
2432 ObjectIdx: cast<FixedStackPseudoSourceValue>(Val: A->getPseudoValue())
2433 ->getFrameIndex())) {
2434 LocationSize S = A->getSize();
2435 if (!S.hasValue())
2436 return LocationSize::beforeOrAfterPointer();
2437 Size += S.getValue();
2438 }
2439 }
2440 return Size;
2441}
2442
2443std::optional<LocationSize>
2444MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2445 int FI;
2446 if (TII->isStoreToStackSlotPostFE(MI: *this, FrameIndex&: FI)) {
2447 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2448 if (MFI.isSpillSlotObjectIndex(ObjectIdx: FI))
2449 return (*memoperands_begin())->getSize();
2450 }
2451 return std::nullopt;
2452}
2453
2454std::optional<LocationSize>
2455MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2456 MMOList Accesses;
2457 if (TII->hasStoreToStackSlot(MI: *this, Accesses))
2458 return getSpillSlotSize(Accesses, MFI: getMF()->getFrameInfo());
2459 return std::nullopt;
2460}
2461
2462std::optional<LocationSize>
2463MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2464 int FI;
2465 if (TII->isLoadFromStackSlotPostFE(MI: *this, FrameIndex&: FI)) {
2466 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2467 if (MFI.isSpillSlotObjectIndex(ObjectIdx: FI))
2468 return (*memoperands_begin())->getSize();
2469 }
2470 return std::nullopt;
2471}
2472
2473std::optional<LocationSize>
2474MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2475 MMOList Accesses;
2476 if (TII->hasLoadFromStackSlot(MI: *this, Accesses))
2477 return getSpillSlotSize(Accesses, MFI: getMF()->getFrameInfo());
2478 return std::nullopt;
2479}
2480
2481unsigned MachineInstr::getDebugInstrNum() {
2482 if (DebugInstrNum == 0)
2483 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2484 return DebugInstrNum;
2485}
2486
2487unsigned MachineInstr::getDebugInstrNum(MachineFunction &MF) {
2488 if (DebugInstrNum == 0)
2489 DebugInstrNum = MF.getNewDebugInstrNum();
2490 return DebugInstrNum;
2491}
2492
2493std::tuple<LLT, LLT> MachineInstr::getFirst2LLTs() const {
2494 return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()),
2495 getRegInfo()->getType(Reg: getOperand(i: 1).getReg()));
2496}
2497
2498std::tuple<LLT, LLT, LLT> MachineInstr::getFirst3LLTs() const {
2499 return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()),
2500 getRegInfo()->getType(Reg: getOperand(i: 1).getReg()),
2501 getRegInfo()->getType(Reg: getOperand(i: 2).getReg()));
2502}
2503
2504std::tuple<LLT, LLT, LLT, LLT> MachineInstr::getFirst4LLTs() const {
2505 return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()),
2506 getRegInfo()->getType(Reg: getOperand(i: 1).getReg()),
2507 getRegInfo()->getType(Reg: getOperand(i: 2).getReg()),
2508 getRegInfo()->getType(Reg: getOperand(i: 3).getReg()));
2509}
2510
2511std::tuple<LLT, LLT, LLT, LLT, LLT> MachineInstr::getFirst5LLTs() const {
2512 return std::tuple(getRegInfo()->getType(Reg: getOperand(i: 0).getReg()),
2513 getRegInfo()->getType(Reg: getOperand(i: 1).getReg()),
2514 getRegInfo()->getType(Reg: getOperand(i: 2).getReg()),
2515 getRegInfo()->getType(Reg: getOperand(i: 3).getReg()),
2516 getRegInfo()->getType(Reg: getOperand(i: 4).getReg()));
2517}
2518
2519std::tuple<Register, LLT, Register, LLT>
2520MachineInstr::getFirst2RegLLTs() const {
2521 Register Reg0 = getOperand(i: 0).getReg();
2522 Register Reg1 = getOperand(i: 1).getReg();
2523 return std::tuple(Reg0, getRegInfo()->getType(Reg: Reg0), Reg1,
2524 getRegInfo()->getType(Reg: Reg1));
2525}
2526
2527std::tuple<Register, LLT, Register, LLT, Register, LLT>
2528MachineInstr::getFirst3RegLLTs() const {
2529 Register Reg0 = getOperand(i: 0).getReg();
2530 Register Reg1 = getOperand(i: 1).getReg();
2531 Register Reg2 = getOperand(i: 2).getReg();
2532 return std::tuple(Reg0, getRegInfo()->getType(Reg: Reg0), Reg1,
2533 getRegInfo()->getType(Reg: Reg1), Reg2,
2534 getRegInfo()->getType(Reg: Reg2));
2535}
2536
2537std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2538MachineInstr::getFirst4RegLLTs() const {
2539 Register Reg0 = getOperand(i: 0).getReg();
2540 Register Reg1 = getOperand(i: 1).getReg();
2541 Register Reg2 = getOperand(i: 2).getReg();
2542 Register Reg3 = getOperand(i: 3).getReg();
2543 return std::tuple(
2544 Reg0, getRegInfo()->getType(Reg: Reg0), Reg1, getRegInfo()->getType(Reg: Reg1),
2545 Reg2, getRegInfo()->getType(Reg: Reg2), Reg3, getRegInfo()->getType(Reg: Reg3));
2546}
2547
2548std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register,
2549 LLT>
2550MachineInstr::getFirst5RegLLTs() const {
2551 Register Reg0 = getOperand(i: 0).getReg();
2552 Register Reg1 = getOperand(i: 1).getReg();
2553 Register Reg2 = getOperand(i: 2).getReg();
2554 Register Reg3 = getOperand(i: 3).getReg();
2555 Register Reg4 = getOperand(i: 4).getReg();
2556 return std::tuple(
2557 Reg0, getRegInfo()->getType(Reg: Reg0), Reg1, getRegInfo()->getType(Reg: Reg1),
2558 Reg2, getRegInfo()->getType(Reg: Reg2), Reg3, getRegInfo()->getType(Reg: Reg3),
2559 Reg4, getRegInfo()->getType(Reg: Reg4));
2560}
2561
2562void MachineInstr::insert(mop_iterator InsertBefore,
2563 ArrayRef<MachineOperand> Ops) {
2564 assert(InsertBefore != nullptr && "invalid iterator");
2565 assert(InsertBefore->getParent() == this &&
2566 "iterator points to operand of other inst");
2567 if (Ops.empty())
2568 return;
2569
2570 // Do one pass to untie operands.
2571 SmallDenseMap<unsigned, unsigned> TiedOpIndices;
2572 for (const MachineOperand &MO : operands()) {
2573 if (MO.isReg() && MO.isTied()) {
2574 unsigned OpNo = getOperandNo(I: &MO);
2575 unsigned TiedTo = findTiedOperandIdx(OpIdx: OpNo);
2576 TiedOpIndices[OpNo] = TiedTo;
2577 untieRegOperand(OpIdx: OpNo);
2578 }
2579 }
2580
2581 unsigned OpIdx = getOperandNo(I: InsertBefore);
2582 unsigned NumOperands = getNumOperands();
2583 unsigned OpsToMove = NumOperands - OpIdx;
2584
2585 SmallVector<MachineOperand> MovingOps;
2586 MovingOps.reserve(N: OpsToMove);
2587
2588 for (unsigned I = 0; I < OpsToMove; ++I) {
2589 MovingOps.emplace_back(Args&: getOperand(i: OpIdx));
2590 removeOperand(OpNo: OpIdx);
2591 }
2592 for (const MachineOperand &MO : Ops)
2593 addOperand(Op: MO);
2594 for (const MachineOperand &OpMoved : MovingOps)
2595 addOperand(Op: OpMoved);
2596
2597 // Re-tie operands.
2598 for (auto [Tie1, Tie2] : TiedOpIndices) {
2599 if (Tie1 >= OpIdx)
2600 Tie1 += Ops.size();
2601 if (Tie2 >= OpIdx)
2602 Tie2 += Ops.size();
2603 tieOperands(DefIdx: Tie1, UseIdx: Tie2);
2604 }
2605}
2606
2607bool MachineInstr::mayFoldInlineAsmRegOp(unsigned OpId) const {
2608 assert(OpId && "expected non-zero operand id");
2609 assert(isInlineAsm() && "should only be used on inline asm");
2610
2611 if (!getOperand(i: OpId).isReg())
2612 return false;
2613
2614 const MachineOperand &MD = getOperand(i: OpId - 1);
2615 if (!MD.isImm())
2616 return false;
2617
2618 InlineAsm::Flag F(MD.getImm());
2619 if (F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind())
2620 return F.getRegMayBeFolded();
2621 return false;
2622}
2623