1//===- RegAllocBase.h - basic regalloc interface and driver -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the RegAllocBase class, which is the skeleton of a basic
10// register allocation algorithm and interface for extending it. It provides the
11// building blocks on which to construct other experimental allocators and test
12// the validity of two principles:
13//
14// - If virtual and physical register liveness is modeled using intervals, then
15// on-the-fly interference checking is cheap. Furthermore, interferences can be
16// lazily cached and reused.
17//
18// - Register allocation complexity, and generated code performance is
19// determined by the effectiveness of live range splitting rather than optimal
20// coloring.
21//
22// Following the first principle, interfering checking revolves around the
23// LiveIntervalUnion data structure.
24//
25// To fulfill the second principle, the basic allocator provides a driver for
26// incremental splitting. It essentially punts on the problem of register
27// coloring, instead driving the assignment of virtual to physical registers by
28// the cost of splitting. The basic allocator allows for heuristic reassignment
29// of registers, if a more sophisticated allocator chooses to do that.
30//
31// This framework provides a way to engineer the compile time vs. code
32// quality trade-off without relying on a particular theoretical solver.
33//
34//===----------------------------------------------------------------------===//
35
36#ifndef LLVM_LIB_CODEGEN_REGALLOCBASE_H
37#define LLVM_LIB_CODEGEN_REGALLOCBASE_H
38
39#include "llvm/ADT/SmallPtrSet.h"
40#include "llvm/CodeGen/MachineRegisterInfo.h"
41#include "llvm/CodeGen/RegAllocCommon.h"
42#include "llvm/CodeGen/RegisterClassInfo.h"
43
44namespace llvm {
45
46class LiveInterval;
47class LiveIntervals;
48class LiveRegMatrix;
49class MachineInstr;
50class MachineRegisterInfo;
51template<typename T> class SmallVectorImpl;
52class Spiller;
53class TargetRegisterInfo;
54class VirtRegMap;
55
56/// RegAllocBase provides the register allocation driver and interface that can
57/// be extended to add interesting heuristics.
58///
59/// Register allocators must override the selectOrSplit() method to implement
60/// live range splitting. They must also override enqueue/dequeue to provide an
61/// assignment order.
62class RegAllocBase {
63 virtual void anchor();
64
65protected:
66 const TargetRegisterInfo *TRI = nullptr;
67 MachineRegisterInfo *MRI = nullptr;
68 VirtRegMap *VRM = nullptr;
69 LiveIntervals *LIS = nullptr;
70 LiveRegMatrix *Matrix = nullptr;
71 RegisterClassInfo RegClassInfo;
72
73private:
74 /// Private, callees should go through shouldAllocateRegister
75 const RegAllocFilterFunc shouldAllocateRegisterImpl;
76
77protected:
78 /// Inst which is a def of an original reg and whose defs are already all
79 /// dead after remat is saved in DeadRemats. The deletion of such inst is
80 /// postponed till all the allocations are done, so its remat expr is
81 /// always available for the remat of all the siblings of the original reg.
82 SmallPtrSet<MachineInstr *, 32> DeadRemats;
83
84 RegAllocBase(const RegAllocFilterFunc F = nullptr)
85 : shouldAllocateRegisterImpl(F) {}
86
87 virtual ~RegAllocBase() = default;
88
89 // A RegAlloc pass should call this before allocatePhysRegs.
90 void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat);
91
92 /// Get whether a given register should be allocated
93 bool shouldAllocateRegister(Register Reg) {
94 if (!shouldAllocateRegisterImpl)
95 return true;
96 return shouldAllocateRegisterImpl(*TRI, *MRI, Reg);
97 }
98
99 // The top-level driver. The output is a VirtRegMap that us updated with
100 // physical register assignments.
101 void allocatePhysRegs();
102
103 // Include spiller post optimization and removing dead defs left because of
104 // rematerialization.
105 virtual void postOptimization();
106
107 // Get a temporary reference to a Spiller instance.
108 virtual Spiller &spiller() = 0;
109
110 /// enqueue - Add VirtReg to the priority queue of unassigned registers.
111 virtual void enqueueImpl(const LiveInterval *LI) = 0;
112
113 /// enqueue - Add VirtReg to the priority queue of unassigned registers.
114 void enqueue(const LiveInterval *LI);
115
116 /// dequeue - Return the next unassigned register, or NULL.
117 virtual const LiveInterval *dequeue() = 0;
118
119 // A RegAlloc pass should override this to provide the allocation heuristics.
120 // Each call must guarantee forward progess by returning an available PhysReg
121 // or new set of split live virtual registers. It is up to the splitter to
122 // converge quickly toward fully spilled live ranges.
123 virtual MCRegister selectOrSplit(const LiveInterval &VirtReg,
124 SmallVectorImpl<Register> &splitLVRs) = 0;
125
126 // Use this group name for NamedRegionTimer.
127 static const char TimerGroupName[];
128 static const char TimerGroupDescription[];
129
130 /// Method called when the allocator is about to remove a LiveInterval.
131 virtual void aboutToRemoveInterval(const LiveInterval &LI) {}
132
133public:
134 /// VerifyEnabled - True when -verify-regalloc is given.
135 static bool VerifyEnabled;
136
137private:
138 void seedLiveRegs();
139};
140
141} // end namespace llvm
142
143#endif // LLVM_LIB_CODEGEN_REGALLOCBASE_H
144