1//===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the SelectionDAG::Legalize method.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/APFloat.h"
14#include "llvm/ADT/APInt.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/ADT/FloatingPointMode.h"
17#include "llvm/ADT/SetVector.h"
18#include "llvm/ADT/SmallPtrSet.h"
19#include "llvm/ADT/SmallSet.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/Analysis/ConstantFolding.h"
22#include "llvm/Analysis/TargetLibraryInfo.h"
23#include "llvm/CodeGen/ISDOpcodes.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineJumpTableInfo.h"
27#include "llvm/CodeGen/MachineMemOperand.h"
28#include "llvm/CodeGen/RuntimeLibcallUtil.h"
29#include "llvm/CodeGen/SelectionDAG.h"
30#include "llvm/CodeGen/SelectionDAGNodes.h"
31#include "llvm/CodeGen/TargetFrameLowering.h"
32#include "llvm/CodeGen/TargetLowering.h"
33#include "llvm/CodeGen/TargetSubtargetInfo.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/CodeGenTypes/MachineValueType.h"
36#include "llvm/IR/CallingConv.h"
37#include "llvm/IR/Constants.h"
38#include "llvm/IR/DataLayout.h"
39#include "llvm/IR/DerivedTypes.h"
40#include "llvm/IR/Function.h"
41#include "llvm/IR/Metadata.h"
42#include "llvm/IR/Type.h"
43#include "llvm/Support/Casting.h"
44#include "llvm/Support/Compiler.h"
45#include "llvm/Support/Debug.h"
46#include "llvm/Support/ErrorHandling.h"
47#include "llvm/Support/MathExtras.h"
48#include "llvm/Support/raw_ostream.h"
49#include "llvm/Target/TargetMachine.h"
50#include "llvm/Target/TargetOptions.h"
51#include <cassert>
52#include <cstdint>
53#include <tuple>
54#include <utility>
55
56using namespace llvm;
57
58#define DEBUG_TYPE "legalizedag"
59
60namespace {
61
62/// Keeps track of state when getting the sign of a floating-point value as an
63/// integer.
64struct FloatSignAsInt {
65 EVT FloatVT;
66 SDValue Chain;
67 SDValue FloatPtr;
68 SDValue IntPtr;
69 MachinePointerInfo IntPointerInfo;
70 MachinePointerInfo FloatPointerInfo;
71 SDValue IntValue;
72 APInt SignMask;
73 uint8_t SignBit;
74};
75
76//===----------------------------------------------------------------------===//
77/// This takes an arbitrary SelectionDAG as input and
78/// hacks on it until the target machine can handle it. This involves
79/// eliminating value sizes the machine cannot handle (promoting small sizes to
80/// large sizes or splitting up large values into small values) as well as
81/// eliminating operations the machine cannot handle.
82///
83/// This code also does a small amount of optimization and recognition of idioms
84/// as part of its processing. For example, if a target does not support a
85/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
86/// will attempt merge setcc and brc instructions into brcc's.
87class SelectionDAGLegalize {
88 const TargetMachine &TM;
89 const TargetLowering &TLI;
90 SelectionDAG &DAG;
91
92 /// The set of nodes which have already been legalized. We hold a
93 /// reference to it in order to update as necessary on node deletion.
94 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
95
96 /// A set of all the nodes updated during legalization.
97 SmallSetVector<SDNode *, 16> *UpdatedNodes;
98
99 EVT getSetCCResultType(EVT VT) const {
100 return TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(), VT);
101 }
102
103 // Libcall insertion helpers.
104
105public:
106 SelectionDAGLegalize(SelectionDAG &DAG,
107 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
108 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
109 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
110 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
111
112 /// Legalizes the given operation.
113 void LegalizeOp(SDNode *Node);
114
115private:
116 SDValue OptimizeFloatStore(StoreSDNode *ST);
117
118 void LegalizeLoadOps(SDNode *Node);
119 void LegalizeStoreOps(SDNode *Node);
120
121 SDValue ExpandINSERT_VECTOR_ELT(SDValue Op);
122
123 /// Return a vector shuffle operation which
124 /// performs the same shuffe in terms of order or result bytes, but on a type
125 /// whose vector element type is narrower than the original shuffle type.
126 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
127 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
128 SDValue N1, SDValue N2,
129 ArrayRef<int> Mask) const;
130
131 std::pair<SDValue, SDValue> ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
132 TargetLowering::ArgListTy &&Args, bool isSigned);
133 std::pair<SDValue, SDValue> ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
134
135 void ExpandFrexpLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
136 void ExpandFPLibCall(SDNode *Node, RTLIB::Libcall LC,
137 SmallVectorImpl<SDValue> &Results);
138 void ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
139 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
140 RTLIB::Libcall Call_F128,
141 RTLIB::Libcall Call_PPCF128,
142 SmallVectorImpl<SDValue> &Results);
143 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
144 RTLIB::Libcall Call_I8,
145 RTLIB::Libcall Call_I16,
146 RTLIB::Libcall Call_I32,
147 RTLIB::Libcall Call_I64,
148 RTLIB::Libcall Call_I128);
149 void ExpandArgFPLibCall(SDNode *Node,
150 RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64,
151 RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128,
152 RTLIB::Libcall Call_PPCF128,
153 SmallVectorImpl<SDValue> &Results);
154 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
155 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
156
157 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
158 const SDLoc &dl);
159 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
160 const SDLoc &dl, SDValue ChainIn);
161 SDValue ExpandBUILD_VECTOR(SDNode *Node);
162 SDValue ExpandSPLAT_VECTOR(SDNode *Node);
163 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
164 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
165 SmallVectorImpl<SDValue> &Results);
166 void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
167 SDValue Value) const;
168 SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
169 SDValue NewIntValue) const;
170 SDValue ExpandFCOPYSIGN(SDNode *Node) const;
171 SDValue ExpandFABS(SDNode *Node) const;
172 SDValue ExpandFNEG(SDNode *Node) const;
173 SDValue expandLdexp(SDNode *Node) const;
174 SDValue expandFrexp(SDNode *Node) const;
175
176 SDValue ExpandLegalINT_TO_FP(SDNode *Node, SDValue &Chain);
177 void PromoteLegalINT_TO_FP(SDNode *N, const SDLoc &dl,
178 SmallVectorImpl<SDValue> &Results);
179 void PromoteLegalFP_TO_INT(SDNode *N, const SDLoc &dl,
180 SmallVectorImpl<SDValue> &Results);
181 SDValue PromoteLegalFP_TO_INT_SAT(SDNode *Node, const SDLoc &dl);
182
183 /// Implements vector reduce operation promotion.
184 ///
185 /// All vector operands are promoted to a vector type with larger element
186 /// type, and the start value is promoted to a larger scalar type. Then the
187 /// result is truncated back to the original scalar type.
188 SDValue PromoteReduction(SDNode *Node);
189
190 SDValue ExpandPARITY(SDValue Op, const SDLoc &dl);
191
192 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
193 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
194 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
195
196 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
197 SDValue ExpandConstant(ConstantSDNode *CP);
198
199 // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
200 bool ExpandNode(SDNode *Node);
201 void ConvertNodeToLibcall(SDNode *Node);
202 void PromoteNode(SDNode *Node);
203
204public:
205 // Node replacement helpers
206
207 void ReplacedNode(SDNode *N) {
208 LegalizedNodes.erase(Ptr: N);
209 if (UpdatedNodes)
210 UpdatedNodes->insert(X: N);
211 }
212
213 void ReplaceNode(SDNode *Old, SDNode *New) {
214 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
215 dbgs() << " with: "; New->dump(&DAG));
216
217 assert(Old->getNumValues() == New->getNumValues() &&
218 "Replacing one node with another that produces a different number "
219 "of values!");
220 DAG.ReplaceAllUsesWith(From: Old, To: New);
221 if (UpdatedNodes)
222 UpdatedNodes->insert(X: New);
223 ReplacedNode(N: Old);
224 }
225
226 void ReplaceNode(SDValue Old, SDValue New) {
227 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
228 dbgs() << " with: "; New->dump(&DAG));
229
230 DAG.ReplaceAllUsesWith(From: Old, To: New);
231 if (UpdatedNodes)
232 UpdatedNodes->insert(X: New.getNode());
233 ReplacedNode(N: Old.getNode());
234 }
235
236 void ReplaceNode(SDNode *Old, const SDValue *New) {
237 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
238
239 DAG.ReplaceAllUsesWith(From: Old, To: New);
240 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
241 LLVM_DEBUG(dbgs() << (i == 0 ? " with: " : " and: ");
242 New[i]->dump(&DAG));
243 if (UpdatedNodes)
244 UpdatedNodes->insert(X: New[i].getNode());
245 }
246 ReplacedNode(N: Old);
247 }
248
249 void ReplaceNodeWithValue(SDValue Old, SDValue New) {
250 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
251 dbgs() << " with: "; New->dump(&DAG));
252
253 DAG.ReplaceAllUsesOfValueWith(From: Old, To: New);
254 if (UpdatedNodes)
255 UpdatedNodes->insert(X: New.getNode());
256 ReplacedNode(N: Old.getNode());
257 }
258};
259
260} // end anonymous namespace
261
262// Helper function that generates an MMO that considers the alignment of the
263// stack, and the size of the stack object
264static MachineMemOperand *getStackAlignedMMO(SDValue StackPtr,
265 MachineFunction &MF,
266 bool isObjectScalable) {
267 auto &MFI = MF.getFrameInfo();
268 int FI = cast<FrameIndexSDNode>(Val&: StackPtr)->getIndex();
269 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
270 LocationSize ObjectSize = isObjectScalable
271 ? LocationSize::beforeOrAfterPointer()
272 : LocationSize::precise(Value: MFI.getObjectSize(ObjectIdx: FI));
273 return MF.getMachineMemOperand(PtrInfo, F: MachineMemOperand::MOStore,
274 Size: ObjectSize, BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
275}
276
277/// Return a vector shuffle operation which
278/// performs the same shuffle in terms of order or result bytes, but on a type
279/// whose vector element type is narrower than the original shuffle type.
280/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
281SDValue SelectionDAGLegalize::ShuffleWithNarrowerEltType(
282 EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
283 ArrayRef<int> Mask) const {
284 unsigned NumMaskElts = VT.getVectorNumElements();
285 unsigned NumDestElts = NVT.getVectorNumElements();
286 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
287
288 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
289
290 if (NumEltsGrowth == 1)
291 return DAG.getVectorShuffle(VT: NVT, dl, N1, N2, Mask);
292
293 SmallVector<int, 8> NewMask;
294 for (unsigned i = 0; i != NumMaskElts; ++i) {
295 int Idx = Mask[i];
296 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
297 if (Idx < 0)
298 NewMask.push_back(Elt: -1);
299 else
300 NewMask.push_back(Elt: Idx * NumEltsGrowth + j);
301 }
302 }
303 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
304 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
305 return DAG.getVectorShuffle(VT: NVT, dl, N1, N2, Mask: NewMask);
306}
307
308/// Expands the ConstantFP node to an integer constant or
309/// a load from the constant pool.
310SDValue
311SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
312 bool Extend = false;
313 SDLoc dl(CFP);
314
315 // If a FP immediate is precise when represented as a float and if the
316 // target can do an extending load from float to double, we put it into
317 // the constant pool as a float, even if it's is statically typed as a
318 // double. This shrinks FP constants and canonicalizes them for targets where
319 // an FP extending load is the same cost as a normal load (such as on the x87
320 // fp stack or PPC FP unit).
321 EVT VT = CFP->getValueType(ResNo: 0);
322 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
323 if (!UseCP) {
324 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
325 return DAG.getConstant(Val: LLVMC->getValueAPF().bitcastToAPInt(), DL: dl,
326 VT: (VT == MVT::f64) ? MVT::i64 : MVT::i32);
327 }
328
329 APFloat APF = CFP->getValueAPF();
330 EVT OrigVT = VT;
331 EVT SVT = VT;
332
333 // We don't want to shrink SNaNs. Converting the SNaN back to its real type
334 // can cause it to be changed into a QNaN on some platforms (e.g. on SystemZ).
335 if (!APF.isSignaling()) {
336 while (SVT != MVT::f32 && SVT != MVT::f16 && SVT != MVT::bf16) {
337 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
338 if (ConstantFPSDNode::isValueValidForType(VT: SVT, Val: APF) &&
339 // Only do this if the target has a native EXTLOAD instruction from
340 // smaller type.
341 TLI.isLoadExtLegal(ExtType: ISD::EXTLOAD, ValVT: OrigVT, MemVT: SVT) &&
342 TLI.ShouldShrinkFPConstant(OrigVT)) {
343 Type *SType = SVT.getTypeForEVT(Context&: *DAG.getContext());
344 LLVMC = cast<ConstantFP>(Val: ConstantFoldCastOperand(
345 Opcode: Instruction::FPTrunc, C: LLVMC, DestTy: SType, DL: DAG.getDataLayout()));
346 VT = SVT;
347 Extend = true;
348 }
349 }
350 }
351
352 SDValue CPIdx =
353 DAG.getConstantPool(C: LLVMC, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
354 Align Alignment = cast<ConstantPoolSDNode>(Val&: CPIdx)->getAlign();
355 if (Extend) {
356 SDValue Result = DAG.getExtLoad(
357 ExtType: ISD::EXTLOAD, dl, VT: OrigVT, Chain: DAG.getEntryNode(), Ptr: CPIdx,
358 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()), MemVT: VT,
359 Alignment);
360 return Result;
361 }
362 SDValue Result = DAG.getLoad(
363 VT: OrigVT, dl, Chain: DAG.getEntryNode(), Ptr: CPIdx,
364 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()), Alignment);
365 return Result;
366}
367
368/// Expands the Constant node to a load from the constant pool.
369SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
370 SDLoc dl(CP);
371 EVT VT = CP->getValueType(ResNo: 0);
372 SDValue CPIdx = DAG.getConstantPool(C: CP->getConstantIntValue(),
373 VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
374 Align Alignment = cast<ConstantPoolSDNode>(Val&: CPIdx)->getAlign();
375 SDValue Result = DAG.getLoad(
376 VT, dl, Chain: DAG.getEntryNode(), Ptr: CPIdx,
377 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()), Alignment);
378 return Result;
379}
380
381SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Op) {
382 SDValue Vec = Op.getOperand(i: 0);
383 SDValue Val = Op.getOperand(i: 1);
384 SDValue Idx = Op.getOperand(i: 2);
385 SDLoc dl(Op);
386
387 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Val&: Idx)) {
388 // SCALAR_TO_VECTOR requires that the type of the value being inserted
389 // match the element type of the vector being created, except for
390 // integers in which case the inserted value can be over width.
391 EVT EltVT = Vec.getValueType().getVectorElementType();
392 if (Val.getValueType() == EltVT ||
393 (EltVT.isInteger() && Val.getValueType().bitsGE(VT: EltVT))) {
394 SDValue ScVec = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl,
395 VT: Vec.getValueType(), Operand: Val);
396
397 unsigned NumElts = Vec.getValueType().getVectorNumElements();
398 // We generate a shuffle of InVec and ScVec, so the shuffle mask
399 // should be 0,1,2,3,4,5... with the appropriate element replaced with
400 // elt 0 of the RHS.
401 SmallVector<int, 8> ShufOps;
402 for (unsigned i = 0; i != NumElts; ++i)
403 ShufOps.push_back(Elt: i != InsertPos->getZExtValue() ? i : NumElts);
404
405 return DAG.getVectorShuffle(VT: Vec.getValueType(), dl, N1: Vec, N2: ScVec, Mask: ShufOps);
406 }
407 }
408 return ExpandInsertToVectorThroughStack(Op);
409}
410
411SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
412 if (!ISD::isNormalStore(N: ST))
413 return SDValue();
414
415 LLVM_DEBUG(dbgs() << "Optimizing float store operations\n");
416 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
417 // FIXME: move this to the DAG Combiner! Note that we can't regress due
418 // to phase ordering between legalized code and the dag combiner. This
419 // probably means that we need to integrate dag combiner and legalizer
420 // together.
421 // We generally can't do this one for long doubles.
422 SDValue Chain = ST->getChain();
423 SDValue Ptr = ST->getBasePtr();
424 SDValue Value = ST->getValue();
425 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
426 AAMDNodes AAInfo = ST->getAAInfo();
427 SDLoc dl(ST);
428
429 // Don't optimise TargetConstantFP
430 if (Value.getOpcode() == ISD::TargetConstantFP)
431 return SDValue();
432
433 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Val&: Value)) {
434 if (CFP->getValueType(ResNo: 0) == MVT::f32 &&
435 TLI.isTypeLegal(VT: MVT::i32)) {
436 SDValue Con = DAG.getConstant(Val: CFP->getValueAPF().
437 bitcastToAPInt().zextOrTrunc(width: 32),
438 DL: SDLoc(CFP), VT: MVT::i32);
439 return DAG.getStore(Chain, dl, Val: Con, Ptr, PtrInfo: ST->getPointerInfo(),
440 Alignment: ST->getOriginalAlign(), MMOFlags, AAInfo);
441 }
442
443 if (CFP->getValueType(ResNo: 0) == MVT::f64 &&
444 !TLI.isFPImmLegal(CFP->getValueAPF(), MVT::f64)) {
445 // If this target supports 64-bit registers, do a single 64-bit store.
446 if (TLI.isTypeLegal(VT: MVT::i64)) {
447 SDValue Con = DAG.getConstant(Val: CFP->getValueAPF().bitcastToAPInt().
448 zextOrTrunc(width: 64), DL: SDLoc(CFP), VT: MVT::i64);
449 return DAG.getStore(Chain, dl, Val: Con, Ptr, PtrInfo: ST->getPointerInfo(),
450 Alignment: ST->getOriginalAlign(), MMOFlags, AAInfo);
451 }
452
453 if (TLI.isTypeLegal(VT: MVT::i32) && !ST->isVolatile()) {
454 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
455 // stores. If the target supports neither 32- nor 64-bits, this
456 // xform is certainly not worth it.
457 const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
458 SDValue Lo = DAG.getConstant(Val: IntVal.trunc(width: 32), DL: dl, VT: MVT::i32);
459 SDValue Hi = DAG.getConstant(Val: IntVal.lshr(shiftAmt: 32).trunc(width: 32), DL: dl, VT: MVT::i32);
460 if (DAG.getDataLayout().isBigEndian())
461 std::swap(a&: Lo, b&: Hi);
462
463 Lo = DAG.getStore(Chain, dl, Val: Lo, Ptr, PtrInfo: ST->getPointerInfo(),
464 Alignment: ST->getOriginalAlign(), MMOFlags, AAInfo);
465 Ptr = DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: 4), DL: dl);
466 Hi = DAG.getStore(Chain, dl, Val: Hi, Ptr,
467 PtrInfo: ST->getPointerInfo().getWithOffset(O: 4),
468 Alignment: ST->getOriginalAlign(), MMOFlags, AAInfo);
469
470 return DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
471 }
472 }
473 }
474 return SDValue();
475}
476
477void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
478 StoreSDNode *ST = cast<StoreSDNode>(Val: Node);
479 SDValue Chain = ST->getChain();
480 SDValue Ptr = ST->getBasePtr();
481 SDLoc dl(Node);
482
483 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
484 AAMDNodes AAInfo = ST->getAAInfo();
485
486 if (!ST->isTruncatingStore()) {
487 LLVM_DEBUG(dbgs() << "Legalizing store operation\n");
488 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
489 ReplaceNode(Old: ST, New: OptStore);
490 return;
491 }
492
493 SDValue Value = ST->getValue();
494 MVT VT = Value.getSimpleValueType();
495 switch (TLI.getOperationAction(Op: ISD::STORE, VT)) {
496 default: llvm_unreachable("This action is not supported yet!");
497 case TargetLowering::Legal: {
498 // If this is an unaligned store and the target doesn't support it,
499 // expand it.
500 EVT MemVT = ST->getMemoryVT();
501 const DataLayout &DL = DAG.getDataLayout();
502 if (!TLI.allowsMemoryAccessForAlignment(Context&: *DAG.getContext(), DL, VT: MemVT,
503 MMO: *ST->getMemOperand())) {
504 LLVM_DEBUG(dbgs() << "Expanding unsupported unaligned store\n");
505 SDValue Result = TLI.expandUnalignedStore(ST, DAG);
506 ReplaceNode(Old: SDValue(ST, 0), New: Result);
507 } else
508 LLVM_DEBUG(dbgs() << "Legal store\n");
509 break;
510 }
511 case TargetLowering::Custom: {
512 LLVM_DEBUG(dbgs() << "Trying custom lowering\n");
513 SDValue Res = TLI.LowerOperation(Op: SDValue(Node, 0), DAG);
514 if (Res && Res != SDValue(Node, 0))
515 ReplaceNode(Old: SDValue(Node, 0), New: Res);
516 return;
517 }
518 case TargetLowering::Promote: {
519 MVT NVT = TLI.getTypeToPromoteTo(Op: ISD::STORE, VT);
520 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
521 "Can only promote stores to same size type");
522 Value = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NVT, Operand: Value);
523 SDValue Result = DAG.getStore(Chain, dl, Val: Value, Ptr, PtrInfo: ST->getPointerInfo(),
524 Alignment: ST->getOriginalAlign(), MMOFlags, AAInfo);
525 ReplaceNode(Old: SDValue(Node, 0), New: Result);
526 break;
527 }
528 }
529 return;
530 }
531
532 LLVM_DEBUG(dbgs() << "Legalizing truncating store operations\n");
533 SDValue Value = ST->getValue();
534 EVT StVT = ST->getMemoryVT();
535 TypeSize StWidth = StVT.getSizeInBits();
536 TypeSize StSize = StVT.getStoreSizeInBits();
537 auto &DL = DAG.getDataLayout();
538
539 if (StWidth != StSize) {
540 // Promote to a byte-sized store with upper bits zero if not
541 // storing an integral number of bytes. For example, promote
542 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
543 EVT NVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: StSize.getFixedValue());
544 Value = DAG.getZeroExtendInReg(Op: Value, DL: dl, VT: StVT);
545 SDValue Result =
546 DAG.getTruncStore(Chain, dl, Val: Value, Ptr, PtrInfo: ST->getPointerInfo(), SVT: NVT,
547 Alignment: ST->getOriginalAlign(), MMOFlags, AAInfo);
548 ReplaceNode(Old: SDValue(Node, 0), New: Result);
549 } else if (!StVT.isVector() && !isPowerOf2_64(Value: StWidth.getFixedValue())) {
550 // If not storing a power-of-2 number of bits, expand as two stores.
551 assert(!StVT.isVector() && "Unsupported truncstore!");
552 unsigned StWidthBits = StWidth.getFixedValue();
553 unsigned LogStWidth = Log2_32(Value: StWidthBits);
554 assert(LogStWidth < 32);
555 unsigned RoundWidth = 1 << LogStWidth;
556 assert(RoundWidth < StWidthBits);
557 unsigned ExtraWidth = StWidthBits - RoundWidth;
558 assert(ExtraWidth < RoundWidth);
559 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
560 "Store size not an integral number of bytes!");
561 EVT RoundVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: RoundWidth);
562 EVT ExtraVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExtraWidth);
563 SDValue Lo, Hi;
564 unsigned IncrementSize;
565
566 if (DL.isLittleEndian()) {
567 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
568 // Store the bottom RoundWidth bits.
569 Lo = DAG.getTruncStore(Chain, dl, Val: Value, Ptr, PtrInfo: ST->getPointerInfo(),
570 SVT: RoundVT, Alignment: ST->getOriginalAlign(), MMOFlags, AAInfo);
571
572 // Store the remaining ExtraWidth bits.
573 IncrementSize = RoundWidth / 8;
574 Ptr =
575 DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
576 Hi = DAG.getNode(
577 Opcode: ISD::SRL, DL: dl, VT: Value.getValueType(), N1: Value,
578 N2: DAG.getConstant(Val: RoundWidth, DL: dl,
579 VT: TLI.getShiftAmountTy(LHSTy: Value.getValueType(), DL)));
580 Hi = DAG.getTruncStore(Chain, dl, Val: Hi, Ptr,
581 PtrInfo: ST->getPointerInfo().getWithOffset(O: IncrementSize),
582 SVT: ExtraVT, Alignment: ST->getOriginalAlign(), MMOFlags, AAInfo);
583 } else {
584 // Big endian - avoid unaligned stores.
585 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
586 // Store the top RoundWidth bits.
587 Hi = DAG.getNode(
588 Opcode: ISD::SRL, DL: dl, VT: Value.getValueType(), N1: Value,
589 N2: DAG.getConstant(Val: ExtraWidth, DL: dl,
590 VT: TLI.getShiftAmountTy(LHSTy: Value.getValueType(), DL)));
591 Hi = DAG.getTruncStore(Chain, dl, Val: Hi, Ptr, PtrInfo: ST->getPointerInfo(), SVT: RoundVT,
592 Alignment: ST->getOriginalAlign(), MMOFlags, AAInfo);
593
594 // Store the remaining ExtraWidth bits.
595 IncrementSize = RoundWidth / 8;
596 Ptr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: Ptr.getValueType(), N1: Ptr,
597 N2: DAG.getConstant(Val: IncrementSize, DL: dl,
598 VT: Ptr.getValueType()));
599 Lo = DAG.getTruncStore(Chain, dl, Val: Value, Ptr,
600 PtrInfo: ST->getPointerInfo().getWithOffset(O: IncrementSize),
601 SVT: ExtraVT, Alignment: ST->getOriginalAlign(), MMOFlags, AAInfo);
602 }
603
604 // The order of the stores doesn't matter.
605 SDValue Result = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo, N2: Hi);
606 ReplaceNode(Old: SDValue(Node, 0), New: Result);
607 } else {
608 switch (TLI.getTruncStoreAction(ValVT: ST->getValue().getValueType(), MemVT: StVT)) {
609 default: llvm_unreachable("This action is not supported yet!");
610 case TargetLowering::Legal: {
611 EVT MemVT = ST->getMemoryVT();
612 // If this is an unaligned store and the target doesn't support it,
613 // expand it.
614 if (!TLI.allowsMemoryAccessForAlignment(Context&: *DAG.getContext(), DL, VT: MemVT,
615 MMO: *ST->getMemOperand())) {
616 SDValue Result = TLI.expandUnalignedStore(ST, DAG);
617 ReplaceNode(Old: SDValue(ST, 0), New: Result);
618 }
619 break;
620 }
621 case TargetLowering::Custom: {
622 SDValue Res = TLI.LowerOperation(Op: SDValue(Node, 0), DAG);
623 if (Res && Res != SDValue(Node, 0))
624 ReplaceNode(Old: SDValue(Node, 0), New: Res);
625 return;
626 }
627 case TargetLowering::Expand:
628 assert(!StVT.isVector() &&
629 "Vector Stores are handled in LegalizeVectorOps");
630
631 SDValue Result;
632
633 // TRUNCSTORE:i16 i32 -> STORE i16
634 if (TLI.isTypeLegal(VT: StVT)) {
635 Value = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: StVT, Operand: Value);
636 Result = DAG.getStore(Chain, dl, Val: Value, Ptr, PtrInfo: ST->getPointerInfo(),
637 Alignment: ST->getOriginalAlign(), MMOFlags, AAInfo);
638 } else {
639 // The in-memory type isn't legal. Truncate to the type it would promote
640 // to, and then do a truncstore.
641 Value = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl,
642 VT: TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: StVT),
643 Operand: Value);
644 Result =
645 DAG.getTruncStore(Chain, dl, Val: Value, Ptr, PtrInfo: ST->getPointerInfo(), SVT: StVT,
646 Alignment: ST->getOriginalAlign(), MMOFlags, AAInfo);
647 }
648
649 ReplaceNode(Old: SDValue(Node, 0), New: Result);
650 break;
651 }
652 }
653}
654
655void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
656 LoadSDNode *LD = cast<LoadSDNode>(Val: Node);
657 SDValue Chain = LD->getChain(); // The chain.
658 SDValue Ptr = LD->getBasePtr(); // The base pointer.
659 SDValue Value; // The value returned by the load op.
660 SDLoc dl(Node);
661
662 ISD::LoadExtType ExtType = LD->getExtensionType();
663 if (ExtType == ISD::NON_EXTLOAD) {
664 LLVM_DEBUG(dbgs() << "Legalizing non-extending load operation\n");
665 MVT VT = Node->getSimpleValueType(ResNo: 0);
666 SDValue RVal = SDValue(Node, 0);
667 SDValue RChain = SDValue(Node, 1);
668
669 switch (TLI.getOperationAction(Op: Node->getOpcode(), VT)) {
670 default: llvm_unreachable("This action is not supported yet!");
671 case TargetLowering::Legal: {
672 EVT MemVT = LD->getMemoryVT();
673 const DataLayout &DL = DAG.getDataLayout();
674 // If this is an unaligned load and the target doesn't support it,
675 // expand it.
676 if (!TLI.allowsMemoryAccessForAlignment(Context&: *DAG.getContext(), DL, VT: MemVT,
677 MMO: *LD->getMemOperand())) {
678 std::tie(args&: RVal, args&: RChain) = TLI.expandUnalignedLoad(LD, DAG);
679 }
680 break;
681 }
682 case TargetLowering::Custom:
683 if (SDValue Res = TLI.LowerOperation(Op: RVal, DAG)) {
684 RVal = Res;
685 RChain = Res.getValue(R: 1);
686 }
687 break;
688
689 case TargetLowering::Promote: {
690 MVT NVT = TLI.getTypeToPromoteTo(Op: Node->getOpcode(), VT);
691 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
692 "Can only promote loads to same size type");
693
694 SDValue Res = DAG.getLoad(VT: NVT, dl, Chain, Ptr, MMO: LD->getMemOperand());
695 RVal = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT, Operand: Res);
696 RChain = Res.getValue(R: 1);
697 break;
698 }
699 }
700 if (RChain.getNode() != Node) {
701 assert(RVal.getNode() != Node && "Load must be completely replaced");
702 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node, 0), To: RVal);
703 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node, 1), To: RChain);
704 if (UpdatedNodes) {
705 UpdatedNodes->insert(X: RVal.getNode());
706 UpdatedNodes->insert(X: RChain.getNode());
707 }
708 ReplacedNode(N: Node);
709 }
710 return;
711 }
712
713 LLVM_DEBUG(dbgs() << "Legalizing extending load operation\n");
714 EVT SrcVT = LD->getMemoryVT();
715 TypeSize SrcWidth = SrcVT.getSizeInBits();
716 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
717 AAMDNodes AAInfo = LD->getAAInfo();
718
719 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
720 // Some targets pretend to have an i1 loading operation, and actually
721 // load an i8. This trick is correct for ZEXTLOAD because the top 7
722 // bits are guaranteed to be zero; it helps the optimizers understand
723 // that these bits are zero. It is also useful for EXTLOAD, since it
724 // tells the optimizers that those bits are undefined. It would be
725 // nice to have an effective generic way of getting these benefits...
726 // Until such a way is found, don't insist on promoting i1 here.
727 (SrcVT != MVT::i1 ||
728 TLI.getLoadExtAction(ExtType, ValVT: Node->getValueType(ResNo: 0), MemVT: MVT::i1) ==
729 TargetLowering::Promote)) {
730 // Promote to a byte-sized load if not loading an integral number of
731 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
732 unsigned NewWidth = SrcVT.getStoreSizeInBits();
733 EVT NVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NewWidth);
734 SDValue Ch;
735
736 // The extra bits are guaranteed to be zero, since we stored them that
737 // way. A zext load from NVT thus automatically gives zext from SrcVT.
738
739 ISD::LoadExtType NewExtType =
740 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
741
742 SDValue Result = DAG.getExtLoad(ExtType: NewExtType, dl, VT: Node->getValueType(ResNo: 0),
743 Chain, Ptr, PtrInfo: LD->getPointerInfo(), MemVT: NVT,
744 Alignment: LD->getOriginalAlign(), MMOFlags, AAInfo);
745
746 Ch = Result.getValue(R: 1); // The chain.
747
748 if (ExtType == ISD::SEXTLOAD)
749 // Having the top bits zero doesn't help when sign extending.
750 Result = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl,
751 VT: Result.getValueType(),
752 N1: Result, N2: DAG.getValueType(SrcVT));
753 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
754 // All the top bits are guaranteed to be zero - inform the optimizers.
755 Result = DAG.getNode(Opcode: ISD::AssertZext, DL: dl,
756 VT: Result.getValueType(), N1: Result,
757 N2: DAG.getValueType(SrcVT));
758
759 Value = Result;
760 Chain = Ch;
761 } else if (!isPowerOf2_64(Value: SrcWidth.getKnownMinValue())) {
762 // If not loading a power-of-2 number of bits, expand as two loads.
763 assert(!SrcVT.isVector() && "Unsupported extload!");
764 unsigned SrcWidthBits = SrcWidth.getFixedValue();
765 unsigned LogSrcWidth = Log2_32(Value: SrcWidthBits);
766 assert(LogSrcWidth < 32);
767 unsigned RoundWidth = 1 << LogSrcWidth;
768 assert(RoundWidth < SrcWidthBits);
769 unsigned ExtraWidth = SrcWidthBits - RoundWidth;
770 assert(ExtraWidth < RoundWidth);
771 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
772 "Load size not an integral number of bytes!");
773 EVT RoundVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: RoundWidth);
774 EVT ExtraVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ExtraWidth);
775 SDValue Lo, Hi, Ch;
776 unsigned IncrementSize;
777 auto &DL = DAG.getDataLayout();
778
779 if (DL.isLittleEndian()) {
780 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
781 // Load the bottom RoundWidth bits.
782 Lo = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl, VT: Node->getValueType(ResNo: 0), Chain, Ptr,
783 PtrInfo: LD->getPointerInfo(), MemVT: RoundVT, Alignment: LD->getOriginalAlign(),
784 MMOFlags, AAInfo);
785
786 // Load the remaining ExtraWidth bits.
787 IncrementSize = RoundWidth / 8;
788 Ptr =
789 DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
790 Hi = DAG.getExtLoad(ExtType, dl, VT: Node->getValueType(ResNo: 0), Chain, Ptr,
791 PtrInfo: LD->getPointerInfo().getWithOffset(O: IncrementSize),
792 MemVT: ExtraVT, Alignment: LD->getOriginalAlign(), MMOFlags, AAInfo);
793
794 // Build a factor node to remember that this load is independent of
795 // the other one.
796 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
797 N2: Hi.getValue(R: 1));
798
799 // Move the top bits to the right place.
800 Hi = DAG.getNode(
801 Opcode: ISD::SHL, DL: dl, VT: Hi.getValueType(), N1: Hi,
802 N2: DAG.getConstant(Val: RoundWidth, DL: dl,
803 VT: TLI.getShiftAmountTy(LHSTy: Hi.getValueType(), DL)));
804
805 // Join the hi and lo parts.
806 Value = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Lo, N2: Hi);
807 } else {
808 // Big endian - avoid unaligned loads.
809 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
810 // Load the top RoundWidth bits.
811 Hi = DAG.getExtLoad(ExtType, dl, VT: Node->getValueType(ResNo: 0), Chain, Ptr,
812 PtrInfo: LD->getPointerInfo(), MemVT: RoundVT, Alignment: LD->getOriginalAlign(),
813 MMOFlags, AAInfo);
814
815 // Load the remaining ExtraWidth bits.
816 IncrementSize = RoundWidth / 8;
817 Ptr =
818 DAG.getMemBasePlusOffset(Base: Ptr, Offset: TypeSize::getFixed(ExactSize: IncrementSize), DL: dl);
819 Lo = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl, VT: Node->getValueType(ResNo: 0), Chain, Ptr,
820 PtrInfo: LD->getPointerInfo().getWithOffset(O: IncrementSize),
821 MemVT: ExtraVT, Alignment: LD->getOriginalAlign(), MMOFlags, AAInfo);
822
823 // Build a factor node to remember that this load is independent of
824 // the other one.
825 Ch = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Lo.getValue(R: 1),
826 N2: Hi.getValue(R: 1));
827
828 // Move the top bits to the right place.
829 Hi = DAG.getNode(
830 Opcode: ISD::SHL, DL: dl, VT: Hi.getValueType(), N1: Hi,
831 N2: DAG.getConstant(Val: ExtraWidth, DL: dl,
832 VT: TLI.getShiftAmountTy(LHSTy: Hi.getValueType(), DL)));
833
834 // Join the hi and lo parts.
835 Value = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Lo, N2: Hi);
836 }
837
838 Chain = Ch;
839 } else {
840 bool isCustom = false;
841 switch (TLI.getLoadExtAction(ExtType, ValVT: Node->getValueType(ResNo: 0),
842 MemVT: SrcVT.getSimpleVT())) {
843 default: llvm_unreachable("This action is not supported yet!");
844 case TargetLowering::Custom:
845 isCustom = true;
846 [[fallthrough]];
847 case TargetLowering::Legal:
848 Value = SDValue(Node, 0);
849 Chain = SDValue(Node, 1);
850
851 if (isCustom) {
852 if (SDValue Res = TLI.LowerOperation(Op: SDValue(Node, 0), DAG)) {
853 Value = Res;
854 Chain = Res.getValue(R: 1);
855 }
856 } else {
857 // If this is an unaligned load and the target doesn't support it,
858 // expand it.
859 EVT MemVT = LD->getMemoryVT();
860 const DataLayout &DL = DAG.getDataLayout();
861 if (!TLI.allowsMemoryAccess(Context&: *DAG.getContext(), DL, VT: MemVT,
862 MMO: *LD->getMemOperand())) {
863 std::tie(args&: Value, args&: Chain) = TLI.expandUnalignedLoad(LD, DAG);
864 }
865 }
866 break;
867
868 case TargetLowering::Expand: {
869 EVT DestVT = Node->getValueType(ResNo: 0);
870 if (!TLI.isLoadExtLegal(ExtType: ISD::EXTLOAD, ValVT: DestVT, MemVT: SrcVT)) {
871 // If the source type is not legal, see if there is a legal extload to
872 // an intermediate type that we can then extend further.
873 EVT LoadVT = TLI.getRegisterType(VT: SrcVT.getSimpleVT());
874 if ((LoadVT.isFloatingPoint() == SrcVT.isFloatingPoint()) &&
875 (TLI.isTypeLegal(VT: SrcVT) || // Same as SrcVT == LoadVT?
876 TLI.isLoadExtLegal(ExtType, ValVT: LoadVT, MemVT: SrcVT))) {
877 // If we are loading a legal type, this is a non-extload followed by a
878 // full extend.
879 ISD::LoadExtType MidExtType =
880 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
881
882 SDValue Load = DAG.getExtLoad(ExtType: MidExtType, dl, VT: LoadVT, Chain, Ptr,
883 MemVT: SrcVT, MMO: LD->getMemOperand());
884 unsigned ExtendOp =
885 ISD::getExtForLoadExtType(IsFP: SrcVT.isFloatingPoint(), ExtType);
886 Value = DAG.getNode(Opcode: ExtendOp, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Load);
887 Chain = Load.getValue(R: 1);
888 break;
889 }
890
891 // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
892 // normal undefined upper bits behavior to allow using an in-reg extend
893 // with the illegal FP type, so load as an integer and do the
894 // from-integer conversion.
895 EVT SVT = SrcVT.getScalarType();
896 if (SVT == MVT::f16 || SVT == MVT::bf16) {
897 EVT ISrcVT = SrcVT.changeTypeToInteger();
898 EVT IDestVT = DestVT.changeTypeToInteger();
899 EVT ILoadVT = TLI.getRegisterType(VT: IDestVT.getSimpleVT());
900
901 SDValue Result = DAG.getExtLoad(ExtType: ISD::ZEXTLOAD, dl, VT: ILoadVT, Chain,
902 Ptr, MemVT: ISrcVT, MMO: LD->getMemOperand());
903 Value =
904 DAG.getNode(Opcode: SVT == MVT::f16 ? ISD::FP16_TO_FP : ISD::BF16_TO_FP,
905 DL: dl, VT: DestVT, Operand: Result);
906 Chain = Result.getValue(R: 1);
907 break;
908 }
909 }
910
911 assert(!SrcVT.isVector() &&
912 "Vector Loads are handled in LegalizeVectorOps");
913
914 // FIXME: This does not work for vectors on most targets. Sign-
915 // and zero-extend operations are currently folded into extending
916 // loads, whether they are legal or not, and then we end up here
917 // without any support for legalizing them.
918 assert(ExtType != ISD::EXTLOAD &&
919 "EXTLOAD should always be supported!");
920 // Turn the unsupported load into an EXTLOAD followed by an
921 // explicit zero/sign extend inreg.
922 SDValue Result = DAG.getExtLoad(ExtType: ISD::EXTLOAD, dl,
923 VT: Node->getValueType(ResNo: 0),
924 Chain, Ptr, MemVT: SrcVT,
925 MMO: LD->getMemOperand());
926 SDValue ValRes;
927 if (ExtType == ISD::SEXTLOAD)
928 ValRes = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl,
929 VT: Result.getValueType(),
930 N1: Result, N2: DAG.getValueType(SrcVT));
931 else
932 ValRes = DAG.getZeroExtendInReg(Op: Result, DL: dl, VT: SrcVT);
933 Value = ValRes;
934 Chain = Result.getValue(R: 1);
935 break;
936 }
937 }
938 }
939
940 // Since loads produce two values, make sure to remember that we legalized
941 // both of them.
942 if (Chain.getNode() != Node) {
943 assert(Value.getNode() != Node && "Load must be completely replaced");
944 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node, 0), To: Value);
945 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node, 1), To: Chain);
946 if (UpdatedNodes) {
947 UpdatedNodes->insert(X: Value.getNode());
948 UpdatedNodes->insert(X: Chain.getNode());
949 }
950 ReplacedNode(N: Node);
951 }
952}
953
954/// Return a legal replacement for the given operation, with all legal operands.
955void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
956 LLVM_DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
957
958 // Allow illegal target nodes and illegal registers.
959 if (Node->getOpcode() == ISD::TargetConstant ||
960 Node->getOpcode() == ISD::Register)
961 return;
962
963#ifndef NDEBUG
964 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
965 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
966 TargetLowering::TypeLegal &&
967 "Unexpected illegal type!");
968
969 for (const SDValue &Op : Node->op_values())
970 assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
971 TargetLowering::TypeLegal ||
972 Op.getOpcode() == ISD::TargetConstant ||
973 Op.getOpcode() == ISD::Register) &&
974 "Unexpected illegal type!");
975#endif
976
977 // Figure out the correct action; the way to query this varies by opcode
978 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
979 bool SimpleFinishLegalizing = true;
980 switch (Node->getOpcode()) {
981 case ISD::INTRINSIC_W_CHAIN:
982 case ISD::INTRINSIC_WO_CHAIN:
983 case ISD::INTRINSIC_VOID:
984 case ISD::STACKSAVE:
985 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: MVT::Other);
986 break;
987 case ISD::GET_DYNAMIC_AREA_OFFSET:
988 Action = TLI.getOperationAction(Op: Node->getOpcode(),
989 VT: Node->getValueType(ResNo: 0));
990 break;
991 case ISD::VAARG:
992 Action = TLI.getOperationAction(Op: Node->getOpcode(),
993 VT: Node->getValueType(ResNo: 0));
994 if (Action != TargetLowering::Promote)
995 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: MVT::Other);
996 break;
997 case ISD::SET_FPENV:
998 case ISD::SET_FPMODE:
999 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1000 VT: Node->getOperand(Num: 1).getValueType());
1001 break;
1002 case ISD::FP_TO_FP16:
1003 case ISD::FP_TO_BF16:
1004 case ISD::SINT_TO_FP:
1005 case ISD::UINT_TO_FP:
1006 case ISD::EXTRACT_VECTOR_ELT:
1007 case ISD::LROUND:
1008 case ISD::LLROUND:
1009 case ISD::LRINT:
1010 case ISD::LLRINT:
1011 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1012 VT: Node->getOperand(Num: 0).getValueType());
1013 break;
1014 case ISD::STRICT_FP_TO_FP16:
1015 case ISD::STRICT_FP_TO_BF16:
1016 case ISD::STRICT_SINT_TO_FP:
1017 case ISD::STRICT_UINT_TO_FP:
1018 case ISD::STRICT_LRINT:
1019 case ISD::STRICT_LLRINT:
1020 case ISD::STRICT_LROUND:
1021 case ISD::STRICT_LLROUND:
1022 // These pseudo-ops are the same as the other STRICT_ ops except
1023 // they are registered with setOperationAction() using the input type
1024 // instead of the output type.
1025 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1026 VT: Node->getOperand(Num: 1).getValueType());
1027 break;
1028 case ISD::SIGN_EXTEND_INREG: {
1029 EVT InnerType = cast<VTSDNode>(Val: Node->getOperand(Num: 1))->getVT();
1030 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: InnerType);
1031 break;
1032 }
1033 case ISD::ATOMIC_STORE:
1034 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1035 VT: Node->getOperand(Num: 1).getValueType());
1036 break;
1037 case ISD::SELECT_CC:
1038 case ISD::STRICT_FSETCC:
1039 case ISD::STRICT_FSETCCS:
1040 case ISD::SETCC:
1041 case ISD::SETCCCARRY:
1042 case ISD::VP_SETCC:
1043 case ISD::BR_CC: {
1044 unsigned Opc = Node->getOpcode();
1045 unsigned CCOperand = Opc == ISD::SELECT_CC ? 4
1046 : Opc == ISD::STRICT_FSETCC ? 3
1047 : Opc == ISD::STRICT_FSETCCS ? 3
1048 : Opc == ISD::SETCCCARRY ? 3
1049 : (Opc == ISD::SETCC || Opc == ISD::VP_SETCC) ? 2
1050 : 1;
1051 unsigned CompareOperand = Opc == ISD::BR_CC ? 2
1052 : Opc == ISD::STRICT_FSETCC ? 1
1053 : Opc == ISD::STRICT_FSETCCS ? 1
1054 : 0;
1055 MVT OpVT = Node->getOperand(Num: CompareOperand).getSimpleValueType();
1056 ISD::CondCode CCCode =
1057 cast<CondCodeSDNode>(Val: Node->getOperand(Num: CCOperand))->get();
1058 Action = TLI.getCondCodeAction(CC: CCCode, VT: OpVT);
1059 if (Action == TargetLowering::Legal) {
1060 if (Node->getOpcode() == ISD::SELECT_CC)
1061 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1062 VT: Node->getValueType(ResNo: 0));
1063 else
1064 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: OpVT);
1065 }
1066 break;
1067 }
1068 case ISD::LOAD:
1069 case ISD::STORE:
1070 // FIXME: Model these properly. LOAD and STORE are complicated, and
1071 // STORE expects the unlegalized operand in some cases.
1072 SimpleFinishLegalizing = false;
1073 break;
1074 case ISD::CALLSEQ_START:
1075 case ISD::CALLSEQ_END:
1076 // FIXME: This shouldn't be necessary. These nodes have special properties
1077 // dealing with the recursive nature of legalization. Removing this
1078 // special case should be done as part of making LegalizeDAG non-recursive.
1079 SimpleFinishLegalizing = false;
1080 break;
1081 case ISD::EXTRACT_ELEMENT:
1082 case ISD::GET_ROUNDING:
1083 case ISD::MERGE_VALUES:
1084 case ISD::EH_RETURN:
1085 case ISD::FRAME_TO_ARGS_OFFSET:
1086 case ISD::EH_DWARF_CFA:
1087 case ISD::EH_SJLJ_SETJMP:
1088 case ISD::EH_SJLJ_LONGJMP:
1089 case ISD::EH_SJLJ_SETUP_DISPATCH:
1090 // These operations lie about being legal: when they claim to be legal,
1091 // they should actually be expanded.
1092 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1093 if (Action == TargetLowering::Legal)
1094 Action = TargetLowering::Expand;
1095 break;
1096 case ISD::INIT_TRAMPOLINE:
1097 case ISD::ADJUST_TRAMPOLINE:
1098 case ISD::FRAMEADDR:
1099 case ISD::RETURNADDR:
1100 case ISD::ADDROFRETURNADDR:
1101 case ISD::SPONENTRY:
1102 // These operations lie about being legal: when they claim to be legal,
1103 // they should actually be custom-lowered.
1104 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1105 if (Action == TargetLowering::Legal)
1106 Action = TargetLowering::Custom;
1107 break;
1108 case ISD::CLEAR_CACHE:
1109 // This operation is typically going to be LibCall unless the target wants
1110 // something differrent.
1111 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1112 break;
1113 case ISD::READCYCLECOUNTER:
1114 case ISD::READSTEADYCOUNTER:
1115 // READCYCLECOUNTER and READSTEADYCOUNTER return a i64, even if type
1116 // legalization might have expanded that to several smaller types.
1117 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: MVT::i64);
1118 break;
1119 case ISD::READ_REGISTER:
1120 case ISD::WRITE_REGISTER:
1121 // Named register is legal in the DAG, but blocked by register name
1122 // selection if not implemented by target (to chose the correct register)
1123 // They'll be converted to Copy(To/From)Reg.
1124 Action = TargetLowering::Legal;
1125 break;
1126 case ISD::UBSANTRAP:
1127 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1128 if (Action == TargetLowering::Expand) {
1129 // replace ISD::UBSANTRAP with ISD::TRAP
1130 SDValue NewVal;
1131 NewVal = DAG.getNode(Opcode: ISD::TRAP, DL: SDLoc(Node), VTList: Node->getVTList(),
1132 N: Node->getOperand(Num: 0));
1133 ReplaceNode(Old: Node, New: NewVal.getNode());
1134 LegalizeOp(Node: NewVal.getNode());
1135 return;
1136 }
1137 break;
1138 case ISD::DEBUGTRAP:
1139 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1140 if (Action == TargetLowering::Expand) {
1141 // replace ISD::DEBUGTRAP with ISD::TRAP
1142 SDValue NewVal;
1143 NewVal = DAG.getNode(Opcode: ISD::TRAP, DL: SDLoc(Node), VTList: Node->getVTList(),
1144 N: Node->getOperand(Num: 0));
1145 ReplaceNode(Old: Node, New: NewVal.getNode());
1146 LegalizeOp(Node: NewVal.getNode());
1147 return;
1148 }
1149 break;
1150 case ISD::SADDSAT:
1151 case ISD::UADDSAT:
1152 case ISD::SSUBSAT:
1153 case ISD::USUBSAT:
1154 case ISD::SSHLSAT:
1155 case ISD::USHLSAT:
1156 case ISD::SCMP:
1157 case ISD::UCMP:
1158 case ISD::FP_TO_SINT_SAT:
1159 case ISD::FP_TO_UINT_SAT:
1160 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1161 break;
1162 case ISD::SMULFIX:
1163 case ISD::SMULFIXSAT:
1164 case ISD::UMULFIX:
1165 case ISD::UMULFIXSAT:
1166 case ISD::SDIVFIX:
1167 case ISD::SDIVFIXSAT:
1168 case ISD::UDIVFIX:
1169 case ISD::UDIVFIXSAT: {
1170 unsigned Scale = Node->getConstantOperandVal(Num: 2);
1171 Action = TLI.getFixedPointOperationAction(Op: Node->getOpcode(),
1172 VT: Node->getValueType(ResNo: 0), Scale);
1173 break;
1174 }
1175 case ISD::MSCATTER:
1176 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1177 VT: cast<MaskedScatterSDNode>(Val: Node)->getValue().getValueType());
1178 break;
1179 case ISD::MSTORE:
1180 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1181 VT: cast<MaskedStoreSDNode>(Val: Node)->getValue().getValueType());
1182 break;
1183 case ISD::VP_SCATTER:
1184 Action = TLI.getOperationAction(
1185 Op: Node->getOpcode(),
1186 VT: cast<VPScatterSDNode>(Val: Node)->getValue().getValueType());
1187 break;
1188 case ISD::VP_STORE:
1189 Action = TLI.getOperationAction(
1190 Op: Node->getOpcode(),
1191 VT: cast<VPStoreSDNode>(Val: Node)->getValue().getValueType());
1192 break;
1193 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
1194 Action = TLI.getOperationAction(
1195 Op: Node->getOpcode(),
1196 VT: cast<VPStridedStoreSDNode>(Val: Node)->getValue().getValueType());
1197 break;
1198 case ISD::VECREDUCE_FADD:
1199 case ISD::VECREDUCE_FMUL:
1200 case ISD::VECREDUCE_ADD:
1201 case ISD::VECREDUCE_MUL:
1202 case ISD::VECREDUCE_AND:
1203 case ISD::VECREDUCE_OR:
1204 case ISD::VECREDUCE_XOR:
1205 case ISD::VECREDUCE_SMAX:
1206 case ISD::VECREDUCE_SMIN:
1207 case ISD::VECREDUCE_UMAX:
1208 case ISD::VECREDUCE_UMIN:
1209 case ISD::VECREDUCE_FMAX:
1210 case ISD::VECREDUCE_FMIN:
1211 case ISD::VECREDUCE_FMAXIMUM:
1212 case ISD::VECREDUCE_FMINIMUM:
1213 case ISD::IS_FPCLASS:
1214 Action = TLI.getOperationAction(
1215 Op: Node->getOpcode(), VT: Node->getOperand(Num: 0).getValueType());
1216 break;
1217 case ISD::VECREDUCE_SEQ_FADD:
1218 case ISD::VECREDUCE_SEQ_FMUL:
1219 case ISD::VP_REDUCE_FADD:
1220 case ISD::VP_REDUCE_FMUL:
1221 case ISD::VP_REDUCE_ADD:
1222 case ISD::VP_REDUCE_MUL:
1223 case ISD::VP_REDUCE_AND:
1224 case ISD::VP_REDUCE_OR:
1225 case ISD::VP_REDUCE_XOR:
1226 case ISD::VP_REDUCE_SMAX:
1227 case ISD::VP_REDUCE_SMIN:
1228 case ISD::VP_REDUCE_UMAX:
1229 case ISD::VP_REDUCE_UMIN:
1230 case ISD::VP_REDUCE_FMAX:
1231 case ISD::VP_REDUCE_FMIN:
1232 case ISD::VP_REDUCE_FMAXIMUM:
1233 case ISD::VP_REDUCE_FMINIMUM:
1234 case ISD::VP_REDUCE_SEQ_FADD:
1235 case ISD::VP_REDUCE_SEQ_FMUL:
1236 Action = TLI.getOperationAction(
1237 Op: Node->getOpcode(), VT: Node->getOperand(Num: 1).getValueType());
1238 break;
1239 case ISD::VP_CTTZ_ELTS:
1240 case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
1241 Action = TLI.getOperationAction(Op: Node->getOpcode(),
1242 VT: Node->getOperand(Num: 0).getValueType());
1243 break;
1244 default:
1245 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1246 Action = TLI.getCustomOperationAction(Op&: *Node);
1247 } else {
1248 Action = TLI.getOperationAction(Op: Node->getOpcode(), VT: Node->getValueType(ResNo: 0));
1249 }
1250 break;
1251 }
1252
1253 if (SimpleFinishLegalizing) {
1254 SDNode *NewNode = Node;
1255 switch (Node->getOpcode()) {
1256 default: break;
1257 case ISD::SHL:
1258 case ISD::SRL:
1259 case ISD::SRA:
1260 case ISD::ROTL:
1261 case ISD::ROTR: {
1262 // Legalizing shifts/rotates requires adjusting the shift amount
1263 // to the appropriate width.
1264 SDValue Op0 = Node->getOperand(Num: 0);
1265 SDValue Op1 = Node->getOperand(Num: 1);
1266 if (!Op1.getValueType().isVector()) {
1267 SDValue SAO = DAG.getShiftAmountOperand(LHSTy: Op0.getValueType(), Op: Op1);
1268 // The getShiftAmountOperand() may create a new operand node or
1269 // return the existing one. If new operand is created we need
1270 // to update the parent node.
1271 // Do not try to legalize SAO here! It will be automatically legalized
1272 // in the next round.
1273 if (SAO != Op1)
1274 NewNode = DAG.UpdateNodeOperands(N: Node, Op1: Op0, Op2: SAO);
1275 }
1276 }
1277 break;
1278 case ISD::FSHL:
1279 case ISD::FSHR:
1280 case ISD::SRL_PARTS:
1281 case ISD::SRA_PARTS:
1282 case ISD::SHL_PARTS: {
1283 // Legalizing shifts/rotates requires adjusting the shift amount
1284 // to the appropriate width.
1285 SDValue Op0 = Node->getOperand(Num: 0);
1286 SDValue Op1 = Node->getOperand(Num: 1);
1287 SDValue Op2 = Node->getOperand(Num: 2);
1288 if (!Op2.getValueType().isVector()) {
1289 SDValue SAO = DAG.getShiftAmountOperand(LHSTy: Op0.getValueType(), Op: Op2);
1290 // The getShiftAmountOperand() may create a new operand node or
1291 // return the existing one. If new operand is created we need
1292 // to update the parent node.
1293 if (SAO != Op2)
1294 NewNode = DAG.UpdateNodeOperands(N: Node, Op1: Op0, Op2: Op1, Op3: SAO);
1295 }
1296 break;
1297 }
1298 }
1299
1300 if (NewNode != Node) {
1301 ReplaceNode(Old: Node, New: NewNode);
1302 Node = NewNode;
1303 }
1304 switch (Action) {
1305 case TargetLowering::Legal:
1306 LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
1307 return;
1308 case TargetLowering::Custom:
1309 LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
1310 // FIXME: The handling for custom lowering with multiple results is
1311 // a complete mess.
1312 if (SDValue Res = TLI.LowerOperation(Op: SDValue(Node, 0), DAG)) {
1313 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1314 return;
1315
1316 if (Node->getNumValues() == 1) {
1317 // Verify the new types match the original. Glue is waived because
1318 // ISD::ADDC can be legalized by replacing Glue with an integer type.
1319 assert((Res.getValueType() == Node->getValueType(0) ||
1320 Node->getValueType(0) == MVT::Glue) &&
1321 "Type mismatch for custom legalized operation");
1322 LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1323 // We can just directly replace this node with the lowered value.
1324 ReplaceNode(Old: SDValue(Node, 0), New: Res);
1325 return;
1326 }
1327
1328 SmallVector<SDValue, 8> ResultVals;
1329 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1330 // Verify the new types match the original. Glue is waived because
1331 // ISD::ADDC can be legalized by replacing Glue with an integer type.
1332 assert((Res->getValueType(i) == Node->getValueType(i) ||
1333 Node->getValueType(i) == MVT::Glue) &&
1334 "Type mismatch for custom legalized operation");
1335 ResultVals.push_back(Elt: Res.getValue(R: i));
1336 }
1337 LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1338 ReplaceNode(Old: Node, New: ResultVals.data());
1339 return;
1340 }
1341 LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
1342 [[fallthrough]];
1343 case TargetLowering::Expand:
1344 if (ExpandNode(Node))
1345 return;
1346 [[fallthrough]];
1347 case TargetLowering::LibCall:
1348 ConvertNodeToLibcall(Node);
1349 return;
1350 case TargetLowering::Promote:
1351 PromoteNode(Node);
1352 return;
1353 }
1354 }
1355
1356 switch (Node->getOpcode()) {
1357 default:
1358#ifndef NDEBUG
1359 dbgs() << "NODE: ";
1360 Node->dump( &DAG);
1361 dbgs() << "\n";
1362#endif
1363 llvm_unreachable("Do not know how to legalize this operator!");
1364
1365 case ISD::CALLSEQ_START:
1366 case ISD::CALLSEQ_END:
1367 break;
1368 case ISD::LOAD:
1369 return LegalizeLoadOps(Node);
1370 case ISD::STORE:
1371 return LegalizeStoreOps(Node);
1372 }
1373}
1374
1375SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1376 SDValue Vec = Op.getOperand(i: 0);
1377 SDValue Idx = Op.getOperand(i: 1);
1378 SDLoc dl(Op);
1379
1380 // Before we generate a new store to a temporary stack slot, see if there is
1381 // already one that we can use. There often is because when we scalarize
1382 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1383 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1384 // the vector. If all are expanded here, we don't want one store per vector
1385 // element.
1386
1387 // Caches for hasPredecessorHelper
1388 SmallPtrSet<const SDNode *, 32> Visited;
1389 SmallVector<const SDNode *, 16> Worklist;
1390 Visited.insert(Ptr: Op.getNode());
1391 Worklist.push_back(Elt: Idx.getNode());
1392 SDValue StackPtr, Ch;
1393 for (SDNode *User : Vec.getNode()->uses()) {
1394 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Val: User)) {
1395 if (ST->isIndexed() || ST->isTruncatingStore() ||
1396 ST->getValue() != Vec)
1397 continue;
1398
1399 // Make sure that nothing else could have stored into the destination of
1400 // this store.
1401 if (!ST->getChain().reachesChainWithoutSideEffects(Dest: DAG.getEntryNode()))
1402 continue;
1403
1404 // If the index is dependent on the store we will introduce a cycle when
1405 // creating the load (the load uses the index, and by replacing the chain
1406 // we will make the index dependent on the load). Also, the store might be
1407 // dependent on the extractelement and introduce a cycle when creating
1408 // the load.
1409 if (SDNode::hasPredecessorHelper(N: ST, Visited, Worklist) ||
1410 ST->hasPredecessor(N: Op.getNode()))
1411 continue;
1412
1413 StackPtr = ST->getBasePtr();
1414 Ch = SDValue(ST, 0);
1415 break;
1416 }
1417 }
1418
1419 EVT VecVT = Vec.getValueType();
1420
1421 if (!Ch.getNode()) {
1422 // Store the value to a temporary stack slot, then LOAD the returned part.
1423 StackPtr = DAG.CreateStackTemporary(VT: VecVT);
1424 MachineMemOperand *StoreMMO = getStackAlignedMMO(
1425 StackPtr, MF&: DAG.getMachineFunction(), isObjectScalable: VecVT.isScalableVector());
1426 Ch = DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: Vec, Ptr: StackPtr, MMO: StoreMMO);
1427 }
1428
1429 SDValue NewLoad;
1430 Align ElementAlignment =
1431 std::min(a: cast<StoreSDNode>(Val&: Ch)->getAlign(),
1432 b: DAG.getDataLayout().getPrefTypeAlign(
1433 Ty: Op.getValueType().getTypeForEVT(Context&: *DAG.getContext())));
1434
1435 if (Op.getValueType().isVector()) {
1436 StackPtr = TLI.getVectorSubVecPointer(DAG, VecPtr: StackPtr, VecVT,
1437 SubVecVT: Op.getValueType(), Index: Idx);
1438 NewLoad = DAG.getLoad(VT: Op.getValueType(), dl, Chain: Ch, Ptr: StackPtr,
1439 PtrInfo: MachinePointerInfo(), Alignment: ElementAlignment);
1440 } else {
1441 StackPtr = TLI.getVectorElementPointer(DAG, VecPtr: StackPtr, VecVT, Index: Idx);
1442 NewLoad = DAG.getExtLoad(ExtType: ISD::EXTLOAD, dl, VT: Op.getValueType(), Chain: Ch, Ptr: StackPtr,
1443 PtrInfo: MachinePointerInfo(), MemVT: VecVT.getVectorElementType(),
1444 Alignment: ElementAlignment);
1445 }
1446
1447 // Replace the chain going out of the store, by the one out of the load.
1448 DAG.ReplaceAllUsesOfValueWith(From: Ch, To: SDValue(NewLoad.getNode(), 1));
1449
1450 // We introduced a cycle though, so update the loads operands, making sure
1451 // to use the original store's chain as an incoming chain.
1452 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1453 NewLoad->op_end());
1454 NewLoadOperands[0] = Ch;
1455 NewLoad =
1456 SDValue(DAG.UpdateNodeOperands(N: NewLoad.getNode(), Ops: NewLoadOperands), 0);
1457 return NewLoad;
1458}
1459
1460SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1461 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1462
1463 SDValue Vec = Op.getOperand(i: 0);
1464 SDValue Part = Op.getOperand(i: 1);
1465 SDValue Idx = Op.getOperand(i: 2);
1466 SDLoc dl(Op);
1467
1468 // Store the value to a temporary stack slot, then LOAD the returned part.
1469 EVT VecVT = Vec.getValueType();
1470 EVT PartVT = Part.getValueType();
1471 SDValue StackPtr = DAG.CreateStackTemporary(VT: VecVT);
1472 int FI = cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex();
1473 MachinePointerInfo PtrInfo =
1474 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI);
1475
1476 // First store the whole vector.
1477 SDValue Ch = DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: Vec, Ptr: StackPtr, PtrInfo);
1478
1479 // Freeze the index so we don't poison the clamping code we're about to emit.
1480 Idx = DAG.getFreeze(V: Idx);
1481
1482 // Then store the inserted part.
1483 if (PartVT.isVector()) {
1484 SDValue SubStackPtr =
1485 TLI.getVectorSubVecPointer(DAG, VecPtr: StackPtr, VecVT, SubVecVT: PartVT, Index: Idx);
1486
1487 // Store the subvector.
1488 Ch = DAG.getStore(
1489 Chain: Ch, dl, Val: Part, Ptr: SubStackPtr,
1490 PtrInfo: MachinePointerInfo::getUnknownStack(MF&: DAG.getMachineFunction()));
1491 } else {
1492 SDValue SubStackPtr =
1493 TLI.getVectorElementPointer(DAG, VecPtr: StackPtr, VecVT, Index: Idx);
1494
1495 // Store the scalar value.
1496 Ch = DAG.getTruncStore(
1497 Chain: Ch, dl, Val: Part, Ptr: SubStackPtr,
1498 PtrInfo: MachinePointerInfo::getUnknownStack(MF&: DAG.getMachineFunction()),
1499 SVT: VecVT.getVectorElementType());
1500 }
1501
1502 // Finally, load the updated vector.
1503 return DAG.getLoad(VT: Op.getValueType(), dl, Chain: Ch, Ptr: StackPtr, PtrInfo);
1504}
1505
1506SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1507 assert((Node->getOpcode() == ISD::BUILD_VECTOR ||
1508 Node->getOpcode() == ISD::CONCAT_VECTORS) &&
1509 "Unexpected opcode!");
1510
1511 // We can't handle this case efficiently. Allocate a sufficiently
1512 // aligned object on the stack, store each operand into it, then load
1513 // the result as a vector.
1514 // Create the stack frame object.
1515 EVT VT = Node->getValueType(ResNo: 0);
1516 EVT MemVT = isa<BuildVectorSDNode>(Val: Node) ? VT.getVectorElementType()
1517 : Node->getOperand(Num: 0).getValueType();
1518 SDLoc dl(Node);
1519 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1520 int FI = cast<FrameIndexSDNode>(Val: FIPtr.getNode())->getIndex();
1521 MachinePointerInfo PtrInfo =
1522 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI);
1523
1524 // Emit a store of each element to the stack slot.
1525 SmallVector<SDValue, 8> Stores;
1526 unsigned TypeByteSize = MemVT.getSizeInBits() / 8;
1527 assert(TypeByteSize > 0 && "Vector element type too small for stack store!");
1528
1529 // If the destination vector element type of a BUILD_VECTOR is narrower than
1530 // the source element type, only store the bits necessary.
1531 bool Truncate = isa<BuildVectorSDNode>(Val: Node) &&
1532 MemVT.bitsLT(VT: Node->getOperand(Num: 0).getValueType());
1533
1534 // Store (in the right endianness) the elements to memory.
1535 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1536 // Ignore undef elements.
1537 if (Node->getOperand(Num: i).isUndef()) continue;
1538
1539 unsigned Offset = TypeByteSize*i;
1540
1541 SDValue Idx =
1542 DAG.getMemBasePlusOffset(Base: FIPtr, Offset: TypeSize::getFixed(ExactSize: Offset), DL: dl);
1543
1544 if (Truncate)
1545 Stores.push_back(Elt: DAG.getTruncStore(Chain: DAG.getEntryNode(), dl,
1546 Val: Node->getOperand(Num: i), Ptr: Idx,
1547 PtrInfo: PtrInfo.getWithOffset(O: Offset), SVT: MemVT));
1548 else
1549 Stores.push_back(Elt: DAG.getStore(Chain: DAG.getEntryNode(), dl, Val: Node->getOperand(Num: i),
1550 Ptr: Idx, PtrInfo: PtrInfo.getWithOffset(O: Offset)));
1551 }
1552
1553 SDValue StoreChain;
1554 if (!Stores.empty()) // Not all undef elements?
1555 StoreChain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: Stores);
1556 else
1557 StoreChain = DAG.getEntryNode();
1558
1559 // Result is a load from the stack slot.
1560 return DAG.getLoad(VT, dl, Chain: StoreChain, Ptr: FIPtr, PtrInfo);
1561}
1562
1563/// Bitcast a floating-point value to an integer value. Only bitcast the part
1564/// containing the sign bit if the target has no integer value capable of
1565/// holding all bits of the floating-point value.
1566void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1567 const SDLoc &DL,
1568 SDValue Value) const {
1569 EVT FloatVT = Value.getValueType();
1570 unsigned NumBits = FloatVT.getScalarSizeInBits();
1571 State.FloatVT = FloatVT;
1572 EVT IVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: NumBits);
1573 // Convert to an integer of the same size.
1574 if (TLI.isTypeLegal(VT: IVT)) {
1575 State.IntValue = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: IVT, Operand: Value);
1576 State.SignMask = APInt::getSignMask(BitWidth: NumBits);
1577 State.SignBit = NumBits - 1;
1578 return;
1579 }
1580
1581 auto &DataLayout = DAG.getDataLayout();
1582 // Store the float to memory, then load the sign part out as an integer.
1583 MVT LoadTy = TLI.getRegisterType(VT: MVT::i8);
1584 // First create a temporary that is aligned for both the load and store.
1585 SDValue StackPtr = DAG.CreateStackTemporary(VT1: FloatVT, VT2: LoadTy);
1586 int FI = cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex();
1587 // Then store the float to it.
1588 State.FloatPtr = StackPtr;
1589 MachineFunction &MF = DAG.getMachineFunction();
1590 State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1591 State.Chain = DAG.getStore(Chain: DAG.getEntryNode(), dl: DL, Val: Value, Ptr: State.FloatPtr,
1592 PtrInfo: State.FloatPointerInfo);
1593
1594 SDValue IntPtr;
1595 if (DataLayout.isBigEndian()) {
1596 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1597 // Load out a legal integer with the same sign bit as the float.
1598 IntPtr = StackPtr;
1599 State.IntPointerInfo = State.FloatPointerInfo;
1600 } else {
1601 // Advance the pointer so that the loaded byte will contain the sign bit.
1602 unsigned ByteOffset = (NumBits / 8) - 1;
1603 IntPtr =
1604 DAG.getMemBasePlusOffset(Base: StackPtr, Offset: TypeSize::getFixed(ExactSize: ByteOffset), DL);
1605 State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1606 Offset: ByteOffset);
1607 }
1608
1609 State.IntPtr = IntPtr;
1610 State.IntValue = DAG.getExtLoad(ExtType: ISD::EXTLOAD, dl: DL, VT: LoadTy, Chain: State.Chain, Ptr: IntPtr,
1611 PtrInfo: State.IntPointerInfo, MemVT: MVT::i8);
1612 State.SignMask = APInt::getOneBitSet(numBits: LoadTy.getScalarSizeInBits(), BitNo: 7);
1613 State.SignBit = 7;
1614}
1615
1616/// Replace the integer value produced by getSignAsIntValue() with a new value
1617/// and cast the result back to a floating-point type.
1618SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1619 const SDLoc &DL,
1620 SDValue NewIntValue) const {
1621 if (!State.Chain)
1622 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: State.FloatVT, Operand: NewIntValue);
1623
1624 // Override the part containing the sign bit in the value stored on the stack.
1625 SDValue Chain = DAG.getTruncStore(Chain: State.Chain, dl: DL, Val: NewIntValue, Ptr: State.IntPtr,
1626 PtrInfo: State.IntPointerInfo, SVT: MVT::i8);
1627 return DAG.getLoad(VT: State.FloatVT, dl: DL, Chain, Ptr: State.FloatPtr,
1628 PtrInfo: State.FloatPointerInfo);
1629}
1630
1631SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1632 SDLoc DL(Node);
1633 SDValue Mag = Node->getOperand(Num: 0);
1634 SDValue Sign = Node->getOperand(Num: 1);
1635
1636 // Get sign bit into an integer value.
1637 FloatSignAsInt SignAsInt;
1638 getSignAsIntValue(State&: SignAsInt, DL, Value: Sign);
1639
1640 EVT IntVT = SignAsInt.IntValue.getValueType();
1641 SDValue SignMask = DAG.getConstant(Val: SignAsInt.SignMask, DL, VT: IntVT);
1642 SDValue SignBit = DAG.getNode(Opcode: ISD::AND, DL, VT: IntVT, N1: SignAsInt.IntValue,
1643 N2: SignMask);
1644
1645 // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1646 EVT FloatVT = Mag.getValueType();
1647 if (TLI.isOperationLegalOrCustom(Op: ISD::FABS, VT: FloatVT) &&
1648 TLI.isOperationLegalOrCustom(Op: ISD::FNEG, VT: FloatVT)) {
1649 SDValue AbsValue = DAG.getNode(Opcode: ISD::FABS, DL, VT: FloatVT, Operand: Mag);
1650 SDValue NegValue = DAG.getNode(Opcode: ISD::FNEG, DL, VT: FloatVT, Operand: AbsValue);
1651 SDValue Cond = DAG.getSetCC(DL, VT: getSetCCResultType(VT: IntVT), LHS: SignBit,
1652 RHS: DAG.getConstant(Val: 0, DL, VT: IntVT), Cond: ISD::SETNE);
1653 return DAG.getSelect(DL, VT: FloatVT, Cond, LHS: NegValue, RHS: AbsValue);
1654 }
1655
1656 // Transform Mag value to integer, and clear the sign bit.
1657 FloatSignAsInt MagAsInt;
1658 getSignAsIntValue(State&: MagAsInt, DL, Value: Mag);
1659 EVT MagVT = MagAsInt.IntValue.getValueType();
1660 SDValue ClearSignMask = DAG.getConstant(Val: ~MagAsInt.SignMask, DL, VT: MagVT);
1661 SDValue ClearedSign = DAG.getNode(Opcode: ISD::AND, DL, VT: MagVT, N1: MagAsInt.IntValue,
1662 N2: ClearSignMask);
1663
1664 // Get the signbit at the right position for MagAsInt.
1665 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1666 EVT ShiftVT = IntVT;
1667 if (SignBit.getScalarValueSizeInBits() <
1668 ClearedSign.getScalarValueSizeInBits()) {
1669 SignBit = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MagVT, Operand: SignBit);
1670 ShiftVT = MagVT;
1671 }
1672 if (ShiftAmount > 0) {
1673 SDValue ShiftCnst = DAG.getConstant(Val: ShiftAmount, DL, VT: ShiftVT);
1674 SignBit = DAG.getNode(Opcode: ISD::SRL, DL, VT: ShiftVT, N1: SignBit, N2: ShiftCnst);
1675 } else if (ShiftAmount < 0) {
1676 SDValue ShiftCnst = DAG.getConstant(Val: -ShiftAmount, DL, VT: ShiftVT);
1677 SignBit = DAG.getNode(Opcode: ISD::SHL, DL, VT: ShiftVT, N1: SignBit, N2: ShiftCnst);
1678 }
1679 if (SignBit.getScalarValueSizeInBits() >
1680 ClearedSign.getScalarValueSizeInBits()) {
1681 SignBit = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MagVT, Operand: SignBit);
1682 }
1683
1684 SDNodeFlags Flags;
1685 Flags.setDisjoint(true);
1686
1687 // Store the part with the modified sign and convert back to float.
1688 SDValue CopiedSign =
1689 DAG.getNode(Opcode: ISD::OR, DL, VT: MagVT, N1: ClearedSign, N2: SignBit, Flags);
1690
1691 return modifySignAsInt(State: MagAsInt, DL, NewIntValue: CopiedSign);
1692}
1693
1694SDValue SelectionDAGLegalize::ExpandFNEG(SDNode *Node) const {
1695 // Get the sign bit as an integer.
1696 SDLoc DL(Node);
1697 FloatSignAsInt SignAsInt;
1698 getSignAsIntValue(State&: SignAsInt, DL, Value: Node->getOperand(Num: 0));
1699 EVT IntVT = SignAsInt.IntValue.getValueType();
1700
1701 // Flip the sign.
1702 SDValue SignMask = DAG.getConstant(Val: SignAsInt.SignMask, DL, VT: IntVT);
1703 SDValue SignFlip =
1704 DAG.getNode(Opcode: ISD::XOR, DL, VT: IntVT, N1: SignAsInt.IntValue, N2: SignMask);
1705
1706 // Convert back to float.
1707 return modifySignAsInt(State: SignAsInt, DL, NewIntValue: SignFlip);
1708}
1709
1710SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1711 SDLoc DL(Node);
1712 SDValue Value = Node->getOperand(Num: 0);
1713
1714 // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1715 EVT FloatVT = Value.getValueType();
1716 if (TLI.isOperationLegalOrCustom(Op: ISD::FCOPYSIGN, VT: FloatVT)) {
1717 SDValue Zero = DAG.getConstantFP(Val: 0.0, DL, VT: FloatVT);
1718 return DAG.getNode(Opcode: ISD::FCOPYSIGN, DL, VT: FloatVT, N1: Value, N2: Zero);
1719 }
1720
1721 // Transform value to integer, clear the sign bit and transform back.
1722 FloatSignAsInt ValueAsInt;
1723 getSignAsIntValue(State&: ValueAsInt, DL, Value);
1724 EVT IntVT = ValueAsInt.IntValue.getValueType();
1725 SDValue ClearSignMask = DAG.getConstant(Val: ~ValueAsInt.SignMask, DL, VT: IntVT);
1726 SDValue ClearedSign = DAG.getNode(Opcode: ISD::AND, DL, VT: IntVT, N1: ValueAsInt.IntValue,
1727 N2: ClearSignMask);
1728 return modifySignAsInt(State: ValueAsInt, DL, NewIntValue: ClearedSign);
1729}
1730
1731void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1732 SmallVectorImpl<SDValue> &Results) {
1733 Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
1734 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1735 " not tell us which reg is the stack pointer!");
1736 SDLoc dl(Node);
1737 EVT VT = Node->getValueType(ResNo: 0);
1738 SDValue Tmp1 = SDValue(Node, 0);
1739 SDValue Tmp2 = SDValue(Node, 1);
1740 SDValue Tmp3 = Node->getOperand(Num: 2);
1741 SDValue Chain = Tmp1.getOperand(i: 0);
1742
1743 // Chain the dynamic stack allocation so that it doesn't modify the stack
1744 // pointer when other instructions are using the stack.
1745 Chain = DAG.getCALLSEQ_START(Chain, InSize: 0, OutSize: 0, DL: dl);
1746
1747 SDValue Size = Tmp2.getOperand(i: 1);
1748 SDValue SP = DAG.getCopyFromReg(Chain, dl, Reg: SPReg, VT);
1749 Chain = SP.getValue(R: 1);
1750 Align Alignment = cast<ConstantSDNode>(Val&: Tmp3)->getAlignValue();
1751 const TargetFrameLowering *TFL = DAG.getSubtarget().getFrameLowering();
1752 unsigned Opc =
1753 TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp ?
1754 ISD::ADD : ISD::SUB;
1755
1756 Align StackAlign = TFL->getStackAlign();
1757 Tmp1 = DAG.getNode(Opcode: Opc, DL: dl, VT, N1: SP, N2: Size); // Value
1758 if (Alignment > StackAlign)
1759 Tmp1 = DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: Tmp1,
1760 N2: DAG.getConstant(Val: -Alignment.value(), DL: dl, VT));
1761 Chain = DAG.getCopyToReg(Chain, dl, Reg: SPReg, N: Tmp1); // Output chain
1762
1763 Tmp2 = DAG.getCALLSEQ_END(Chain, Size1: 0, Size2: 0, Glue: SDValue(), DL: dl);
1764
1765 Results.push_back(Elt: Tmp1);
1766 Results.push_back(Elt: Tmp2);
1767}
1768
1769/// Emit a store/load combination to the stack. This stores
1770/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1771/// a load from the stack slot to DestVT, extending it if needed.
1772/// The resultant code need not be legal.
1773SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1774 EVT DestVT, const SDLoc &dl) {
1775 return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, ChainIn: DAG.getEntryNode());
1776}
1777
1778SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1779 EVT DestVT, const SDLoc &dl,
1780 SDValue Chain) {
1781 EVT SrcVT = SrcOp.getValueType();
1782 Type *DestType = DestVT.getTypeForEVT(Context&: *DAG.getContext());
1783 Align DestAlign = DAG.getDataLayout().getPrefTypeAlign(Ty: DestType);
1784
1785 // Don't convert with stack if the load/store is expensive.
1786 if ((SrcVT.bitsGT(VT: SlotVT) &&
1787 !TLI.isTruncStoreLegalOrCustom(ValVT: SrcOp.getValueType(), MemVT: SlotVT)) ||
1788 (SlotVT.bitsLT(VT: DestVT) &&
1789 !TLI.isLoadExtLegalOrCustom(ExtType: ISD::EXTLOAD, ValVT: DestVT, MemVT: SlotVT)))
1790 return SDValue();
1791
1792 // Create the stack frame object.
1793 Align SrcAlign = DAG.getDataLayout().getPrefTypeAlign(
1794 Ty: SrcOp.getValueType().getTypeForEVT(Context&: *DAG.getContext()));
1795 SDValue FIPtr = DAG.CreateStackTemporary(Bytes: SlotVT.getStoreSize(), Alignment: SrcAlign);
1796
1797 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(Val&: FIPtr);
1798 int SPFI = StackPtrFI->getIndex();
1799 MachinePointerInfo PtrInfo =
1800 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI);
1801
1802 // Emit a store to the stack slot. Use a truncstore if the input value is
1803 // later than DestVT.
1804 SDValue Store;
1805
1806 if (SrcVT.bitsGT(VT: SlotVT))
1807 Store = DAG.getTruncStore(Chain, dl, Val: SrcOp, Ptr: FIPtr, PtrInfo,
1808 SVT: SlotVT, Alignment: SrcAlign);
1809 else {
1810 assert(SrcVT.bitsEq(SlotVT) && "Invalid store");
1811 Store = DAG.getStore(Chain, dl, Val: SrcOp, Ptr: FIPtr, PtrInfo, Alignment: SrcAlign);
1812 }
1813
1814 // Result is a load from the stack slot.
1815 if (SlotVT.bitsEq(VT: DestVT))
1816 return DAG.getLoad(VT: DestVT, dl, Chain: Store, Ptr: FIPtr, PtrInfo, Alignment: DestAlign);
1817
1818 assert(SlotVT.bitsLT(DestVT) && "Unknown extension!");
1819 return DAG.getExtLoad(ExtType: ISD::EXTLOAD, dl, VT: DestVT, Chain: Store, Ptr: FIPtr, PtrInfo, MemVT: SlotVT,
1820 Alignment: DestAlign);
1821}
1822
1823SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1824 SDLoc dl(Node);
1825 // Create a vector sized/aligned stack slot, store the value to element #0,
1826 // then load the whole vector back out.
1827 SDValue StackPtr = DAG.CreateStackTemporary(VT: Node->getValueType(ResNo: 0));
1828
1829 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(Val&: StackPtr);
1830 int SPFI = StackPtrFI->getIndex();
1831
1832 SDValue Ch = DAG.getTruncStore(
1833 Chain: DAG.getEntryNode(), dl, Val: Node->getOperand(Num: 0), Ptr: StackPtr,
1834 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI),
1835 SVT: Node->getValueType(ResNo: 0).getVectorElementType());
1836 return DAG.getLoad(
1837 VT: Node->getValueType(ResNo: 0), dl, Chain: Ch, Ptr: StackPtr,
1838 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI));
1839}
1840
1841static bool
1842ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1843 const TargetLowering &TLI, SDValue &Res) {
1844 unsigned NumElems = Node->getNumOperands();
1845 SDLoc dl(Node);
1846 EVT VT = Node->getValueType(ResNo: 0);
1847
1848 // Try to group the scalars into pairs, shuffle the pairs together, then
1849 // shuffle the pairs of pairs together, etc. until the vector has
1850 // been built. This will work only if all of the necessary shuffle masks
1851 // are legal.
1852
1853 // We do this in two phases; first to check the legality of the shuffles,
1854 // and next, assuming that all shuffles are legal, to create the new nodes.
1855 for (int Phase = 0; Phase < 2; ++Phase) {
1856 SmallVector<std::pair<SDValue, SmallVector<int, 16>>, 16> IntermedVals,
1857 NewIntermedVals;
1858 for (unsigned i = 0; i < NumElems; ++i) {
1859 SDValue V = Node->getOperand(Num: i);
1860 if (V.isUndef())
1861 continue;
1862
1863 SDValue Vec;
1864 if (Phase)
1865 Vec = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT, Operand: V);
1866 IntermedVals.push_back(Elt: std::make_pair(x&: Vec, y: SmallVector<int, 16>(1, i)));
1867 }
1868
1869 while (IntermedVals.size() > 2) {
1870 NewIntermedVals.clear();
1871 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1872 // This vector and the next vector are shuffled together (simply to
1873 // append the one to the other).
1874 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1875
1876 SmallVector<int, 16> FinalIndices;
1877 FinalIndices.reserve(N: IntermedVals[i].second.size() +
1878 IntermedVals[i+1].second.size());
1879
1880 int k = 0;
1881 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1882 ++j, ++k) {
1883 ShuffleVec[k] = j;
1884 FinalIndices.push_back(Elt: IntermedVals[i].second[j]);
1885 }
1886 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1887 ++j, ++k) {
1888 ShuffleVec[k] = NumElems + j;
1889 FinalIndices.push_back(Elt: IntermedVals[i+1].second[j]);
1890 }
1891
1892 SDValue Shuffle;
1893 if (Phase)
1894 Shuffle = DAG.getVectorShuffle(VT, dl, N1: IntermedVals[i].first,
1895 N2: IntermedVals[i+1].first,
1896 Mask: ShuffleVec);
1897 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1898 return false;
1899 NewIntermedVals.push_back(
1900 Elt: std::make_pair(x&: Shuffle, y: std::move(FinalIndices)));
1901 }
1902
1903 // If we had an odd number of defined values, then append the last
1904 // element to the array of new vectors.
1905 if ((IntermedVals.size() & 1) != 0)
1906 NewIntermedVals.push_back(Elt: IntermedVals.back());
1907
1908 IntermedVals.swap(RHS&: NewIntermedVals);
1909 }
1910
1911 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1912 "Invalid number of intermediate vectors");
1913 SDValue Vec1 = IntermedVals[0].first;
1914 SDValue Vec2;
1915 if (IntermedVals.size() > 1)
1916 Vec2 = IntermedVals[1].first;
1917 else if (Phase)
1918 Vec2 = DAG.getUNDEF(VT);
1919
1920 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1921 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1922 ShuffleVec[IntermedVals[0].second[i]] = i;
1923 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1924 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1925
1926 if (Phase)
1927 Res = DAG.getVectorShuffle(VT, dl, N1: Vec1, N2: Vec2, Mask: ShuffleVec);
1928 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1929 return false;
1930 }
1931
1932 return true;
1933}
1934
1935/// Expand a BUILD_VECTOR node on targets that don't
1936/// support the operation, but do support the resultant vector type.
1937SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1938 unsigned NumElems = Node->getNumOperands();
1939 SDValue Value1, Value2;
1940 SDLoc dl(Node);
1941 EVT VT = Node->getValueType(ResNo: 0);
1942 EVT OpVT = Node->getOperand(Num: 0).getValueType();
1943 EVT EltVT = VT.getVectorElementType();
1944
1945 // If the only non-undef value is the low element, turn this into a
1946 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1947 bool isOnlyLowElement = true;
1948 bool MoreThanTwoValues = false;
1949 bool isConstant = true;
1950 for (unsigned i = 0; i < NumElems; ++i) {
1951 SDValue V = Node->getOperand(Num: i);
1952 if (V.isUndef())
1953 continue;
1954 if (i > 0)
1955 isOnlyLowElement = false;
1956 if (!isa<ConstantFPSDNode>(Val: V) && !isa<ConstantSDNode>(Val: V))
1957 isConstant = false;
1958
1959 if (!Value1.getNode()) {
1960 Value1 = V;
1961 } else if (!Value2.getNode()) {
1962 if (V != Value1)
1963 Value2 = V;
1964 } else if (V != Value1 && V != Value2) {
1965 MoreThanTwoValues = true;
1966 }
1967 }
1968
1969 if (!Value1.getNode())
1970 return DAG.getUNDEF(VT);
1971
1972 if (isOnlyLowElement)
1973 return DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT, Operand: Node->getOperand(Num: 0));
1974
1975 // If all elements are constants, create a load from the constant pool.
1976 if (isConstant) {
1977 SmallVector<Constant*, 16> CV;
1978 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1979 if (ConstantFPSDNode *V =
1980 dyn_cast<ConstantFPSDNode>(Val: Node->getOperand(Num: i))) {
1981 CV.push_back(Elt: const_cast<ConstantFP *>(V->getConstantFPValue()));
1982 } else if (ConstantSDNode *V =
1983 dyn_cast<ConstantSDNode>(Val: Node->getOperand(Num: i))) {
1984 if (OpVT==EltVT)
1985 CV.push_back(Elt: const_cast<ConstantInt *>(V->getConstantIntValue()));
1986 else {
1987 // If OpVT and EltVT don't match, EltVT is not legal and the
1988 // element values have been promoted/truncated earlier. Undo this;
1989 // we don't want a v16i8 to become a v16i32 for example.
1990 const ConstantInt *CI = V->getConstantIntValue();
1991 CV.push_back(Elt: ConstantInt::get(Ty: EltVT.getTypeForEVT(Context&: *DAG.getContext()),
1992 V: CI->getZExtValue()));
1993 }
1994 } else {
1995 assert(Node->getOperand(i).isUndef());
1996 Type *OpNTy = EltVT.getTypeForEVT(Context&: *DAG.getContext());
1997 CV.push_back(Elt: UndefValue::get(T: OpNTy));
1998 }
1999 }
2000 Constant *CP = ConstantVector::get(V: CV);
2001 SDValue CPIdx =
2002 DAG.getConstantPool(C: CP, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
2003 Align Alignment = cast<ConstantPoolSDNode>(Val&: CPIdx)->getAlign();
2004 return DAG.getLoad(
2005 VT, dl, Chain: DAG.getEntryNode(), Ptr: CPIdx,
2006 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()),
2007 Alignment);
2008 }
2009
2010 SmallSet<SDValue, 16> DefinedValues;
2011 for (unsigned i = 0; i < NumElems; ++i) {
2012 if (Node->getOperand(Num: i).isUndef())
2013 continue;
2014 DefinedValues.insert(V: Node->getOperand(Num: i));
2015 }
2016
2017 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues: DefinedValues.size())) {
2018 if (!MoreThanTwoValues) {
2019 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2020 for (unsigned i = 0; i < NumElems; ++i) {
2021 SDValue V = Node->getOperand(Num: i);
2022 if (V.isUndef())
2023 continue;
2024 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2025 }
2026 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(ResNo: 0))) {
2027 // Get the splatted value into the low element of a vector register.
2028 SDValue Vec1 = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT, Operand: Value1);
2029 SDValue Vec2;
2030 if (Value2.getNode())
2031 Vec2 = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT, Operand: Value2);
2032 else
2033 Vec2 = DAG.getUNDEF(VT);
2034
2035 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2036 return DAG.getVectorShuffle(VT, dl, N1: Vec1, N2: Vec2, Mask: ShuffleVec);
2037 }
2038 } else {
2039 SDValue Res;
2040 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2041 return Res;
2042 }
2043 }
2044
2045 // Otherwise, we can't handle this case efficiently.
2046 return ExpandVectorBuildThroughStack(Node);
2047}
2048
2049SDValue SelectionDAGLegalize::ExpandSPLAT_VECTOR(SDNode *Node) {
2050 SDLoc DL(Node);
2051 EVT VT = Node->getValueType(ResNo: 0);
2052 SDValue SplatVal = Node->getOperand(Num: 0);
2053
2054 return DAG.getSplatBuildVector(VT, DL, Op: SplatVal);
2055}
2056
2057// Expand a node into a call to a libcall, returning the value as the first
2058// result and the chain as the second. If the result value does not fit into a
2059// register, return the lo part and set the hi part to the by-reg argument in
2060// the first. If it does fit into a single register, return the result and
2061// leave the Hi part unset.
2062std::pair<SDValue, SDValue> SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2063 TargetLowering::ArgListTy &&Args,
2064 bool isSigned) {
2065 EVT CodePtrTy = TLI.getPointerTy(DL: DAG.getDataLayout());
2066 SDValue Callee;
2067 if (const char *LibcallName = TLI.getLibcallName(Call: LC))
2068 Callee = DAG.getExternalSymbol(Sym: LibcallName, VT: CodePtrTy);
2069 else {
2070 Callee = DAG.getUNDEF(VT: CodePtrTy);
2071 DAG.getContext()->emitError(ErrorStr: Twine("no libcall available for ") +
2072 Node->getOperationName(G: &DAG));
2073 }
2074
2075 EVT RetVT = Node->getValueType(ResNo: 0);
2076 Type *RetTy = RetVT.getTypeForEVT(Context&: *DAG.getContext());
2077
2078 // By default, the input chain to this libcall is the entry node of the
2079 // function. If the libcall is going to be emitted as a tail call then
2080 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2081 // node which is being folded has a non-entry input chain.
2082 SDValue InChain = DAG.getEntryNode();
2083
2084 // isTailCall may be true since the callee does not reference caller stack
2085 // frame. Check if it's in the right position and that the return types match.
2086 SDValue TCChain = InChain;
2087 const Function &F = DAG.getMachineFunction().getFunction();
2088 bool isTailCall =
2089 TLI.isInTailCallPosition(DAG, Node, Chain&: TCChain) &&
2090 (RetTy == F.getReturnType() || F.getReturnType()->isVoidTy());
2091 if (isTailCall)
2092 InChain = TCChain;
2093
2094 TargetLowering::CallLoweringInfo CLI(DAG);
2095 bool signExtend = TLI.shouldSignExtendTypeInLibCall(Type: RetVT, IsSigned: isSigned);
2096 CLI.setDebugLoc(SDLoc(Node))
2097 .setChain(InChain)
2098 .setLibCallee(CC: TLI.getLibcallCallingConv(Call: LC), ResultType: RetTy, Target: Callee,
2099 ArgsList: std::move(Args))
2100 .setTailCall(isTailCall)
2101 .setSExtResult(signExtend)
2102 .setZExtResult(!signExtend)
2103 .setIsPostTypeLegalization(true);
2104
2105 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2106
2107 if (!CallInfo.second.getNode()) {
2108 LLVM_DEBUG(dbgs() << "Created tailcall: "; DAG.getRoot().dump(&DAG));
2109 // It's a tailcall, return the chain (which is the DAG root).
2110 return {DAG.getRoot(), DAG.getRoot()};
2111 }
2112
2113 LLVM_DEBUG(dbgs() << "Created libcall: "; CallInfo.first.dump(&DAG));
2114 return CallInfo;
2115}
2116
2117std::pair<SDValue, SDValue> SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2118 bool isSigned) {
2119 TargetLowering::ArgListTy Args;
2120 TargetLowering::ArgListEntry Entry;
2121 for (const SDValue &Op : Node->op_values()) {
2122 EVT ArgVT = Op.getValueType();
2123 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
2124 Entry.Node = Op;
2125 Entry.Ty = ArgTy;
2126 Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(Type: ArgVT, IsSigned: isSigned);
2127 Entry.IsZExt = !Entry.IsSExt;
2128 Args.push_back(x: Entry);
2129 }
2130
2131 return ExpandLibCall(LC, Node, Args: std::move(Args), isSigned);
2132}
2133
2134void SelectionDAGLegalize::ExpandFrexpLibCall(
2135 SDNode *Node, SmallVectorImpl<SDValue> &Results) {
2136 SDLoc dl(Node);
2137 EVT VT = Node->getValueType(ResNo: 0);
2138 EVT ExpVT = Node->getValueType(ResNo: 1);
2139
2140 SDValue FPOp = Node->getOperand(Num: 0);
2141
2142 EVT ArgVT = FPOp.getValueType();
2143 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
2144
2145 TargetLowering::ArgListEntry FPArgEntry;
2146 FPArgEntry.Node = FPOp;
2147 FPArgEntry.Ty = ArgTy;
2148
2149 SDValue StackSlot = DAG.CreateStackTemporary(VT: ExpVT);
2150 TargetLowering::ArgListEntry PtrArgEntry;
2151 PtrArgEntry.Node = StackSlot;
2152 PtrArgEntry.Ty = PointerType::get(C&: *DAG.getContext(),
2153 AddressSpace: DAG.getDataLayout().getAllocaAddrSpace());
2154
2155 TargetLowering::ArgListTy Args = {FPArgEntry, PtrArgEntry};
2156
2157 RTLIB::Libcall LC = RTLIB::getFREXP(RetVT: VT);
2158 auto [Call, Chain] = ExpandLibCall(LC, Node, Args: std::move(Args), isSigned: false);
2159
2160 // FIXME: Get type of int for libcall declaration and cast
2161
2162 int FrameIdx = cast<FrameIndexSDNode>(Val&: StackSlot)->getIndex();
2163 auto PtrInfo =
2164 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: FrameIdx);
2165
2166 SDValue LoadExp = DAG.getLoad(VT: ExpVT, dl, Chain, Ptr: StackSlot, PtrInfo);
2167 SDValue OutputChain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other,
2168 N1: LoadExp.getValue(R: 1), N2: DAG.getRoot());
2169 DAG.setRoot(OutputChain);
2170
2171 Results.push_back(Elt: Call);
2172 Results.push_back(Elt: LoadExp);
2173}
2174
2175void SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2176 RTLIB::Libcall LC,
2177 SmallVectorImpl<SDValue> &Results) {
2178 if (LC == RTLIB::UNKNOWN_LIBCALL)
2179 llvm_unreachable("Can't create an unknown libcall!");
2180
2181 if (Node->isStrictFPOpcode()) {
2182 EVT RetVT = Node->getValueType(ResNo: 0);
2183 SmallVector<SDValue, 4> Ops(drop_begin(RangeOrContainer: Node->ops()));
2184 TargetLowering::MakeLibCallOptions CallOptions;
2185 // FIXME: This doesn't support tail calls.
2186 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
2187 Ops, CallOptions,
2188 dl: SDLoc(Node),
2189 Chain: Node->getOperand(Num: 0));
2190 Results.push_back(Elt: Tmp.first);
2191 Results.push_back(Elt: Tmp.second);
2192 } else {
2193 SDValue Tmp = ExpandLibCall(LC, Node, isSigned: false).first;
2194 Results.push_back(Elt: Tmp);
2195 }
2196}
2197
2198/// Expand the node to a libcall based on the result type.
2199void SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2200 RTLIB::Libcall Call_F32,
2201 RTLIB::Libcall Call_F64,
2202 RTLIB::Libcall Call_F80,
2203 RTLIB::Libcall Call_F128,
2204 RTLIB::Libcall Call_PPCF128,
2205 SmallVectorImpl<SDValue> &Results) {
2206 RTLIB::Libcall LC = RTLIB::getFPLibCall(VT: Node->getSimpleValueType(ResNo: 0),
2207 Call_F32, Call_F64, Call_F80,
2208 Call_F128, Call_PPCF128);
2209 ExpandFPLibCall(Node, LC, Results);
2210}
2211
2212SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2213 RTLIB::Libcall Call_I8,
2214 RTLIB::Libcall Call_I16,
2215 RTLIB::Libcall Call_I32,
2216 RTLIB::Libcall Call_I64,
2217 RTLIB::Libcall Call_I128) {
2218 RTLIB::Libcall LC;
2219 switch (Node->getSimpleValueType(ResNo: 0).SimpleTy) {
2220 default: llvm_unreachable("Unexpected request for libcall!");
2221 case MVT::i8: LC = Call_I8; break;
2222 case MVT::i16: LC = Call_I16; break;
2223 case MVT::i32: LC = Call_I32; break;
2224 case MVT::i64: LC = Call_I64; break;
2225 case MVT::i128: LC = Call_I128; break;
2226 }
2227 return ExpandLibCall(LC, Node, isSigned).first;
2228}
2229
2230/// Expand the node to a libcall based on first argument type (for instance
2231/// lround and its variant).
2232void SelectionDAGLegalize::ExpandArgFPLibCall(SDNode* Node,
2233 RTLIB::Libcall Call_F32,
2234 RTLIB::Libcall Call_F64,
2235 RTLIB::Libcall Call_F80,
2236 RTLIB::Libcall Call_F128,
2237 RTLIB::Libcall Call_PPCF128,
2238 SmallVectorImpl<SDValue> &Results) {
2239 EVT InVT = Node->getOperand(Num: Node->isStrictFPOpcode() ? 1 : 0).getValueType();
2240 RTLIB::Libcall LC = RTLIB::getFPLibCall(VT: InVT.getSimpleVT(),
2241 Call_F32, Call_F64, Call_F80,
2242 Call_F128, Call_PPCF128);
2243 ExpandFPLibCall(Node, LC, Results);
2244}
2245
2246/// Issue libcalls to __{u}divmod to compute div / rem pairs.
2247void
2248SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2249 SmallVectorImpl<SDValue> &Results) {
2250 unsigned Opcode = Node->getOpcode();
2251 bool isSigned = Opcode == ISD::SDIVREM;
2252
2253 RTLIB::Libcall LC;
2254 switch (Node->getSimpleValueType(ResNo: 0).SimpleTy) {
2255 default: llvm_unreachable("Unexpected request for libcall!");
2256 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2257 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2258 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2259 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2260 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2261 }
2262
2263 // The input chain to this libcall is the entry node of the function.
2264 // Legalizing the call will automatically add the previous call to the
2265 // dependence.
2266 SDValue InChain = DAG.getEntryNode();
2267
2268 EVT RetVT = Node->getValueType(ResNo: 0);
2269 Type *RetTy = RetVT.getTypeForEVT(Context&: *DAG.getContext());
2270
2271 TargetLowering::ArgListTy Args;
2272 TargetLowering::ArgListEntry Entry;
2273 for (const SDValue &Op : Node->op_values()) {
2274 EVT ArgVT = Op.getValueType();
2275 Type *ArgTy = ArgVT.getTypeForEVT(Context&: *DAG.getContext());
2276 Entry.Node = Op;
2277 Entry.Ty = ArgTy;
2278 Entry.IsSExt = isSigned;
2279 Entry.IsZExt = !isSigned;
2280 Args.push_back(x: Entry);
2281 }
2282
2283 // Also pass the return address of the remainder.
2284 SDValue FIPtr = DAG.CreateStackTemporary(VT: RetVT);
2285 Entry.Node = FIPtr;
2286 Entry.Ty = PointerType::getUnqual(C&: RetTy->getContext());
2287 Entry.IsSExt = isSigned;
2288 Entry.IsZExt = !isSigned;
2289 Args.push_back(x: Entry);
2290
2291 SDValue Callee = DAG.getExternalSymbol(Sym: TLI.getLibcallName(Call: LC),
2292 VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
2293
2294 SDLoc dl(Node);
2295 TargetLowering::CallLoweringInfo CLI(DAG);
2296 CLI.setDebugLoc(dl)
2297 .setChain(InChain)
2298 .setLibCallee(CC: TLI.getLibcallCallingConv(Call: LC), ResultType: RetTy, Target: Callee,
2299 ArgsList: std::move(Args))
2300 .setSExtResult(isSigned)
2301 .setZExtResult(!isSigned);
2302
2303 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2304
2305 // Remainder is loaded back from the stack frame.
2306 SDValue Rem =
2307 DAG.getLoad(VT: RetVT, dl, Chain: CallInfo.second, Ptr: FIPtr, PtrInfo: MachinePointerInfo());
2308 Results.push_back(Elt: CallInfo.first);
2309 Results.push_back(Elt: Rem);
2310}
2311
2312/// Return true if sincos libcall is available.
2313static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2314 RTLIB::Libcall LC;
2315 switch (Node->getSimpleValueType(ResNo: 0).SimpleTy) {
2316 default: llvm_unreachable("Unexpected request for libcall!");
2317 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2318 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2319 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2320 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2321 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2322 }
2323 return TLI.getLibcallName(Call: LC) != nullptr;
2324}
2325
2326/// Only issue sincos libcall if both sin and cos are needed.
2327static bool useSinCos(SDNode *Node) {
2328 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2329 ? ISD::FCOS : ISD::FSIN;
2330
2331 SDValue Op0 = Node->getOperand(Num: 0);
2332 for (const SDNode *User : Op0.getNode()->uses()) {
2333 if (User == Node)
2334 continue;
2335 // The other user might have been turned into sincos already.
2336 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2337 return true;
2338 }
2339 return false;
2340}
2341
2342/// Issue libcalls to sincos to compute sin / cos pairs.
2343void
2344SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2345 SmallVectorImpl<SDValue> &Results) {
2346 RTLIB::Libcall LC;
2347 switch (Node->getSimpleValueType(ResNo: 0).SimpleTy) {
2348 default: llvm_unreachable("Unexpected request for libcall!");
2349 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2350 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2351 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2352 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2353 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2354 }
2355
2356 // The input chain to this libcall is the entry node of the function.
2357 // Legalizing the call will automatically add the previous call to the
2358 // dependence.
2359 SDValue InChain = DAG.getEntryNode();
2360
2361 EVT RetVT = Node->getValueType(ResNo: 0);
2362 Type *RetTy = RetVT.getTypeForEVT(Context&: *DAG.getContext());
2363
2364 TargetLowering::ArgListTy Args;
2365 TargetLowering::ArgListEntry Entry;
2366
2367 // Pass the argument.
2368 Entry.Node = Node->getOperand(Num: 0);
2369 Entry.Ty = RetTy;
2370 Entry.IsSExt = false;
2371 Entry.IsZExt = false;
2372 Args.push_back(x: Entry);
2373
2374 // Pass the return address of sin.
2375 SDValue SinPtr = DAG.CreateStackTemporary(VT: RetVT);
2376 Entry.Node = SinPtr;
2377 Entry.Ty = PointerType::getUnqual(C&: RetTy->getContext());
2378 Entry.IsSExt = false;
2379 Entry.IsZExt = false;
2380 Args.push_back(x: Entry);
2381
2382 // Also pass the return address of the cos.
2383 SDValue CosPtr = DAG.CreateStackTemporary(VT: RetVT);
2384 Entry.Node = CosPtr;
2385 Entry.Ty = PointerType::getUnqual(C&: RetTy->getContext());
2386 Entry.IsSExt = false;
2387 Entry.IsZExt = false;
2388 Args.push_back(x: Entry);
2389
2390 SDValue Callee = DAG.getExternalSymbol(Sym: TLI.getLibcallName(Call: LC),
2391 VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
2392
2393 SDLoc dl(Node);
2394 TargetLowering::CallLoweringInfo CLI(DAG);
2395 CLI.setDebugLoc(dl).setChain(InChain).setLibCallee(
2396 CC: TLI.getLibcallCallingConv(Call: LC), ResultType: Type::getVoidTy(C&: *DAG.getContext()), Target: Callee,
2397 ArgsList: std::move(Args));
2398
2399 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2400
2401 Results.push_back(
2402 Elt: DAG.getLoad(VT: RetVT, dl, Chain: CallInfo.second, Ptr: SinPtr, PtrInfo: MachinePointerInfo()));
2403 Results.push_back(
2404 Elt: DAG.getLoad(VT: RetVT, dl, Chain: CallInfo.second, Ptr: CosPtr, PtrInfo: MachinePointerInfo()));
2405}
2406
2407SDValue SelectionDAGLegalize::expandLdexp(SDNode *Node) const {
2408 SDLoc dl(Node);
2409 EVT VT = Node->getValueType(ResNo: 0);
2410 SDValue X = Node->getOperand(Num: 0);
2411 SDValue N = Node->getOperand(Num: 1);
2412 EVT ExpVT = N.getValueType();
2413 EVT AsIntVT = VT.changeTypeToInteger();
2414 if (AsIntVT == EVT()) // TODO: How to handle f80?
2415 return SDValue();
2416
2417 if (Node->getOpcode() == ISD::STRICT_FLDEXP) // TODO
2418 return SDValue();
2419
2420 SDNodeFlags NSW;
2421 NSW.setNoSignedWrap(true);
2422 SDNodeFlags NUW_NSW;
2423 NUW_NSW.setNoUnsignedWrap(true);
2424 NUW_NSW.setNoSignedWrap(true);
2425
2426 EVT SetCCVT =
2427 TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(), VT: ExpVT);
2428 const fltSemantics &FltSem = SelectionDAG::EVTToAPFloatSemantics(VT);
2429
2430 const APFloat::ExponentType MaxExpVal = APFloat::semanticsMaxExponent(FltSem);
2431 const APFloat::ExponentType MinExpVal = APFloat::semanticsMinExponent(FltSem);
2432 const int Precision = APFloat::semanticsPrecision(FltSem);
2433
2434 const SDValue MaxExp = DAG.getConstant(Val: MaxExpVal, DL: dl, VT: ExpVT);
2435 const SDValue MinExp = DAG.getConstant(Val: MinExpVal, DL: dl, VT: ExpVT);
2436
2437 const SDValue DoubleMaxExp = DAG.getConstant(Val: 2 * MaxExpVal, DL: dl, VT: ExpVT);
2438
2439 const APFloat One(FltSem, "1.0");
2440 APFloat ScaleUpK = scalbn(X: One, Exp: MaxExpVal, RM: APFloat::rmNearestTiesToEven);
2441
2442 // Offset by precision to avoid denormal range.
2443 APFloat ScaleDownK =
2444 scalbn(X: One, Exp: MinExpVal + Precision, RM: APFloat::rmNearestTiesToEven);
2445
2446 // TODO: Should really introduce control flow and use a block for the >
2447 // MaxExp, < MinExp cases
2448
2449 // First, handle exponents Exp > MaxExp and scale down.
2450 SDValue NGtMaxExp = DAG.getSetCC(DL: dl, VT: SetCCVT, LHS: N, RHS: MaxExp, Cond: ISD::SETGT);
2451
2452 SDValue DecN0 = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ExpVT, N1: N, N2: MaxExp, Flags: NSW);
2453 SDValue ClampMaxVal = DAG.getConstant(Val: 3 * MaxExpVal, DL: dl, VT: ExpVT);
2454 SDValue ClampN_Big = DAG.getNode(Opcode: ISD::SMIN, DL: dl, VT: ExpVT, N1: N, N2: ClampMaxVal);
2455 SDValue DecN1 =
2456 DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: ExpVT, N1: ClampN_Big, N2: DoubleMaxExp, Flags: NSW);
2457
2458 SDValue ScaleUpTwice =
2459 DAG.getSetCC(DL: dl, VT: SetCCVT, LHS: N, RHS: DoubleMaxExp, Cond: ISD::SETUGT);
2460
2461 const SDValue ScaleUpVal = DAG.getConstantFP(Val: ScaleUpK, DL: dl, VT);
2462 SDValue ScaleUp0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: X, N2: ScaleUpVal);
2463 SDValue ScaleUp1 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: ScaleUp0, N2: ScaleUpVal);
2464
2465 SDValue SelectN_Big =
2466 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: ExpVT, N1: ScaleUpTwice, N2: DecN1, N3: DecN0);
2467 SDValue SelectX_Big =
2468 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT, N1: ScaleUpTwice, N2: ScaleUp1, N3: ScaleUp0);
2469
2470 // Now handle exponents Exp < MinExp
2471 SDValue NLtMinExp = DAG.getSetCC(DL: dl, VT: SetCCVT, LHS: N, RHS: MinExp, Cond: ISD::SETLT);
2472
2473 SDValue Increment0 = DAG.getConstant(Val: -(MinExpVal + Precision), DL: dl, VT: ExpVT);
2474 SDValue Increment1 = DAG.getConstant(Val: -2 * (MinExpVal + Precision), DL: dl, VT: ExpVT);
2475
2476 SDValue IncN0 = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: ExpVT, N1: N, N2: Increment0, Flags: NUW_NSW);
2477
2478 SDValue ClampMinVal =
2479 DAG.getConstant(Val: 3 * MinExpVal + 2 * Precision, DL: dl, VT: ExpVT);
2480 SDValue ClampN_Small = DAG.getNode(Opcode: ISD::SMAX, DL: dl, VT: ExpVT, N1: N, N2: ClampMinVal);
2481 SDValue IncN1 =
2482 DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: ExpVT, N1: ClampN_Small, N2: Increment1, Flags: NSW);
2483
2484 const SDValue ScaleDownVal = DAG.getConstantFP(Val: ScaleDownK, DL: dl, VT);
2485 SDValue ScaleDown0 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: X, N2: ScaleDownVal);
2486 SDValue ScaleDown1 = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: ScaleDown0, N2: ScaleDownVal);
2487
2488 SDValue ScaleDownTwice = DAG.getSetCC(
2489 DL: dl, VT: SetCCVT, LHS: N, RHS: DAG.getConstant(Val: 2 * MinExpVal + Precision, DL: dl, VT: ExpVT),
2490 Cond: ISD::SETULT);
2491
2492 SDValue SelectN_Small =
2493 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: ExpVT, N1: ScaleDownTwice, N2: IncN1, N3: IncN0);
2494 SDValue SelectX_Small =
2495 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT, N1: ScaleDownTwice, N2: ScaleDown1, N3: ScaleDown0);
2496
2497 // Now combine the two out of range exponent handling cases with the base
2498 // case.
2499 SDValue NewX = DAG.getNode(
2500 Opcode: ISD::SELECT, DL: dl, VT, N1: NGtMaxExp, N2: SelectX_Big,
2501 N3: DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT, N1: NLtMinExp, N2: SelectX_Small, N3: X));
2502
2503 SDValue NewN = DAG.getNode(
2504 Opcode: ISD::SELECT, DL: dl, VT: ExpVT, N1: NGtMaxExp, N2: SelectN_Big,
2505 N3: DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: ExpVT, N1: NLtMinExp, N2: SelectN_Small, N3: N));
2506
2507 SDValue BiasedN = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: ExpVT, N1: NewN, N2: MaxExp, Flags: NSW);
2508
2509 SDValue ExponentShiftAmt =
2510 DAG.getShiftAmountConstant(Val: Precision - 1, VT: ExpVT, DL: dl);
2511 SDValue CastExpToValTy = DAG.getZExtOrTrunc(Op: BiasedN, DL: dl, VT: AsIntVT);
2512
2513 SDValue AsInt = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: AsIntVT, N1: CastExpToValTy,
2514 N2: ExponentShiftAmt, Flags: NUW_NSW);
2515 SDValue AsFP = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT, Operand: AsInt);
2516 return DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: NewX, N2: AsFP);
2517}
2518
2519SDValue SelectionDAGLegalize::expandFrexp(SDNode *Node) const {
2520 SDLoc dl(Node);
2521 SDValue Val = Node->getOperand(Num: 0);
2522 EVT VT = Val.getValueType();
2523 EVT ExpVT = Node->getValueType(ResNo: 1);
2524 EVT AsIntVT = VT.changeTypeToInteger();
2525 if (AsIntVT == EVT()) // TODO: How to handle f80?
2526 return SDValue();
2527
2528 const fltSemantics &FltSem = SelectionDAG::EVTToAPFloatSemantics(VT);
2529 const APFloat::ExponentType MinExpVal = APFloat::semanticsMinExponent(FltSem);
2530 const unsigned Precision = APFloat::semanticsPrecision(FltSem);
2531 const unsigned BitSize = VT.getScalarSizeInBits();
2532
2533 // TODO: Could introduce control flow and skip over the denormal handling.
2534
2535 // scale_up = fmul value, scalbn(1.0, precision + 1)
2536 // extracted_exp = (bitcast value to uint) >> precision - 1
2537 // biased_exp = extracted_exp + min_exp
2538 // extracted_fract = (bitcast value to uint) & (fract_mask | sign_mask)
2539 //
2540 // is_denormal = val < smallest_normalized
2541 // computed_fract = is_denormal ? scale_up : extracted_fract
2542 // computed_exp = is_denormal ? biased_exp + (-precision - 1) : biased_exp
2543 //
2544 // result_0 = (!isfinite(val) || iszero(val)) ? val : computed_fract
2545 // result_1 = (!isfinite(val) || iszero(val)) ? 0 : computed_exp
2546
2547 SDValue NegSmallestNormalizedInt = DAG.getConstant(
2548 Val: APFloat::getSmallestNormalized(Sem: FltSem, Negative: true).bitcastToAPInt(), DL: dl,
2549 VT: AsIntVT);
2550
2551 SDValue SmallestNormalizedInt = DAG.getConstant(
2552 Val: APFloat::getSmallestNormalized(Sem: FltSem, Negative: false).bitcastToAPInt(), DL: dl,
2553 VT: AsIntVT);
2554
2555 // Masks out the exponent bits.
2556 SDValue ExpMask =
2557 DAG.getConstant(Val: APFloat::getInf(Sem: FltSem).bitcastToAPInt(), DL: dl, VT: AsIntVT);
2558
2559 // Mask out the exponent part of the value.
2560 //
2561 // e.g, for f32 FractSignMaskVal = 0x807fffff
2562 APInt FractSignMaskVal = APInt::getBitsSet(numBits: BitSize, loBit: 0, hiBit: Precision - 1);
2563 FractSignMaskVal.setBit(BitSize - 1); // Set the sign bit
2564
2565 APInt SignMaskVal = APInt::getSignedMaxValue(numBits: BitSize);
2566 SDValue SignMask = DAG.getConstant(Val: SignMaskVal, DL: dl, VT: AsIntVT);
2567
2568 SDValue FractSignMask = DAG.getConstant(Val: FractSignMaskVal, DL: dl, VT: AsIntVT);
2569
2570 const APFloat One(FltSem, "1.0");
2571 // Scale a possible denormal input.
2572 // e.g., for f64, 0x1p+54
2573 APFloat ScaleUpKVal =
2574 scalbn(X: One, Exp: Precision + 1, RM: APFloat::rmNearestTiesToEven);
2575
2576 SDValue ScaleUpK = DAG.getConstantFP(Val: ScaleUpKVal, DL: dl, VT);
2577 SDValue ScaleUp = DAG.getNode(Opcode: ISD::FMUL, DL: dl, VT, N1: Val, N2: ScaleUpK);
2578
2579 EVT SetCCVT =
2580 TLI.getSetCCResultType(DL: DAG.getDataLayout(), Context&: *DAG.getContext(), VT);
2581
2582 SDValue AsInt = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: AsIntVT, Operand: Val);
2583
2584 SDValue Abs = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AsIntVT, N1: AsInt, N2: SignMask);
2585
2586 SDValue AddNegSmallestNormal =
2587 DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: AsIntVT, N1: Abs, N2: NegSmallestNormalizedInt);
2588 SDValue DenormOrZero = DAG.getSetCC(DL: dl, VT: SetCCVT, LHS: AddNegSmallestNormal,
2589 RHS: NegSmallestNormalizedInt, Cond: ISD::SETULE);
2590
2591 SDValue IsDenormal =
2592 DAG.getSetCC(DL: dl, VT: SetCCVT, LHS: Abs, RHS: SmallestNormalizedInt, Cond: ISD::SETULT);
2593
2594 SDValue MinExp = DAG.getConstant(Val: MinExpVal, DL: dl, VT: ExpVT);
2595 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT: ExpVT);
2596
2597 SDValue ScaledAsInt = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: AsIntVT, Operand: ScaleUp);
2598 SDValue ScaledSelect =
2599 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: AsIntVT, N1: IsDenormal, N2: ScaledAsInt, N3: AsInt);
2600
2601 SDValue ExpMaskScaled =
2602 DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AsIntVT, N1: ScaledAsInt, N2: ExpMask);
2603
2604 SDValue ScaledValue =
2605 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: AsIntVT, N1: IsDenormal, N2: ExpMaskScaled, N3: Abs);
2606
2607 // Extract the exponent bits.
2608 SDValue ExponentShiftAmt =
2609 DAG.getShiftAmountConstant(Val: Precision - 1, VT: AsIntVT, DL: dl);
2610 SDValue ShiftedExp =
2611 DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: AsIntVT, N1: ScaledValue, N2: ExponentShiftAmt);
2612 SDValue Exp = DAG.getSExtOrTrunc(Op: ShiftedExp, DL: dl, VT: ExpVT);
2613
2614 SDValue NormalBiasedExp = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: ExpVT, N1: Exp, N2: MinExp);
2615 SDValue DenormalOffset = DAG.getConstant(Val: -Precision - 1, DL: dl, VT: ExpVT);
2616 SDValue DenormalExpBias =
2617 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: ExpVT, N1: IsDenormal, N2: DenormalOffset, N3: Zero);
2618
2619 SDValue MaskedFractAsInt =
2620 DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AsIntVT, N1: ScaledSelect, N2: FractSignMask);
2621 const APFloat Half(FltSem, "0.5");
2622 SDValue FPHalf = DAG.getConstant(Val: Half.bitcastToAPInt(), DL: dl, VT: AsIntVT);
2623 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: AsIntVT, N1: MaskedFractAsInt, N2: FPHalf);
2624 SDValue MaskedFract = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT, Operand: Or);
2625
2626 SDValue ComputedExp =
2627 DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: ExpVT, N1: NormalBiasedExp, N2: DenormalExpBias);
2628
2629 SDValue Result0 =
2630 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT, N1: DenormOrZero, N2: Val, N3: MaskedFract);
2631
2632 SDValue Result1 =
2633 DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: ExpVT, N1: DenormOrZero, N2: Zero, N3: ComputedExp);
2634
2635 return DAG.getMergeValues(Ops: {Result0, Result1}, dl);
2636}
2637
2638/// This function is responsible for legalizing a
2639/// INT_TO_FP operation of the specified operand when the target requests that
2640/// we expand it. At this point, we know that the result and operand types are
2641/// legal for the target.
2642SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(SDNode *Node,
2643 SDValue &Chain) {
2644 bool isSigned = (Node->getOpcode() == ISD::STRICT_SINT_TO_FP ||
2645 Node->getOpcode() == ISD::SINT_TO_FP);
2646 EVT DestVT = Node->getValueType(ResNo: 0);
2647 SDLoc dl(Node);
2648 unsigned OpNo = Node->isStrictFPOpcode() ? 1 : 0;
2649 SDValue Op0 = Node->getOperand(Num: OpNo);
2650 EVT SrcVT = Op0.getValueType();
2651
2652 // TODO: Should any fast-math-flags be set for the created nodes?
2653 LLVM_DEBUG(dbgs() << "Legalizing INT_TO_FP\n");
2654 if (SrcVT == MVT::i32 && TLI.isTypeLegal(VT: MVT::f64) &&
2655 (DestVT.bitsLE(VT: MVT::f64) ||
2656 TLI.isOperationLegal(Op: Node->isStrictFPOpcode() ? ISD::STRICT_FP_EXTEND
2657 : ISD::FP_EXTEND,
2658 VT: DestVT))) {
2659 LLVM_DEBUG(dbgs() << "32-bit [signed|unsigned] integer to float/double "
2660 "expansion\n");
2661
2662 // Get the stack frame index of a 8 byte buffer.
2663 SDValue StackSlot = DAG.CreateStackTemporary(VT: MVT::f64);
2664
2665 SDValue Lo = Op0;
2666 // if signed map to unsigned space
2667 if (isSigned) {
2668 // Invert sign bit (signed to unsigned mapping).
2669 Lo = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: MVT::i32, N1: Lo,
2670 N2: DAG.getConstant(Val: 0x80000000u, DL: dl, VT: MVT::i32));
2671 }
2672 // Initial hi portion of constructed double.
2673 SDValue Hi = DAG.getConstant(Val: 0x43300000u, DL: dl, VT: MVT::i32);
2674
2675 // If this a big endian target, swap the lo and high data.
2676 if (DAG.getDataLayout().isBigEndian())
2677 std::swap(a&: Lo, b&: Hi);
2678
2679 SDValue MemChain = DAG.getEntryNode();
2680
2681 // Store the lo of the constructed double.
2682 SDValue Store1 = DAG.getStore(Chain: MemChain, dl, Val: Lo, Ptr: StackSlot,
2683 PtrInfo: MachinePointerInfo());
2684 // Store the hi of the constructed double.
2685 SDValue HiPtr =
2686 DAG.getMemBasePlusOffset(Base: StackSlot, Offset: TypeSize::getFixed(ExactSize: 4), DL: dl);
2687 SDValue Store2 =
2688 DAG.getStore(Chain: MemChain, dl, Val: Hi, Ptr: HiPtr, PtrInfo: MachinePointerInfo());
2689 MemChain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Store1, N2: Store2);
2690
2691 // load the constructed double
2692 SDValue Load =
2693 DAG.getLoad(VT: MVT::f64, dl, Chain: MemChain, Ptr: StackSlot, PtrInfo: MachinePointerInfo());
2694 // FP constant to bias correct the final result
2695 SDValue Bias = DAG.getConstantFP(
2696 Val: isSigned ? llvm::bit_cast<double>(from: 0x4330000080000000ULL)
2697 : llvm::bit_cast<double>(from: 0x4330000000000000ULL),
2698 DL: dl, VT: MVT::f64);
2699 // Subtract the bias and get the final result.
2700 SDValue Sub;
2701 SDValue Result;
2702 if (Node->isStrictFPOpcode()) {
2703 Sub = DAG.getNode(Opcode: ISD::STRICT_FSUB, DL: dl, ResultTys: {MVT::f64, MVT::Other},
2704 Ops: {Node->getOperand(Num: 0), Load, Bias});
2705 Chain = Sub.getValue(R: 1);
2706 if (DestVT != Sub.getValueType()) {
2707 std::pair<SDValue, SDValue> ResultPair;
2708 ResultPair =
2709 DAG.getStrictFPExtendOrRound(Op: Sub, Chain, DL: dl, VT: DestVT);
2710 Result = ResultPair.first;
2711 Chain = ResultPair.second;
2712 }
2713 else
2714 Result = Sub;
2715 } else {
2716 Sub = DAG.getNode(Opcode: ISD::FSUB, DL: dl, VT: MVT::f64, N1: Load, N2: Bias);
2717 Result = DAG.getFPExtendOrRound(Op: Sub, DL: dl, VT: DestVT);
2718 }
2719 return Result;
2720 }
2721
2722 if (isSigned)
2723 return SDValue();
2724
2725 // TODO: Generalize this for use with other types.
2726 if (((SrcVT == MVT::i32 || SrcVT == MVT::i64) && DestVT == MVT::f32) ||
2727 (SrcVT == MVT::i64 && DestVT == MVT::f64)) {
2728 LLVM_DEBUG(dbgs() << "Converting unsigned i32/i64 to f32/f64\n");
2729 // For unsigned conversions, convert them to signed conversions using the
2730 // algorithm from the x86_64 __floatundisf in compiler_rt. That method
2731 // should be valid for i32->f32 as well.
2732
2733 // More generally this transform should be valid if there are 3 more bits
2734 // in the integer type than the significand. Rounding uses the first bit
2735 // after the width of the significand and the OR of all bits after that. So
2736 // we need to be able to OR the shifted out bit into one of the bits that
2737 // participate in the OR.
2738
2739 // TODO: This really should be implemented using a branch rather than a
2740 // select. We happen to get lucky and machinesink does the right
2741 // thing most of the time. This would be a good candidate for a
2742 // pseudo-op, or, even better, for whole-function isel.
2743 EVT SetCCVT = getSetCCResultType(VT: SrcVT);
2744
2745 SDValue SignBitTest = DAG.getSetCC(
2746 DL: dl, VT: SetCCVT, LHS: Op0, RHS: DAG.getConstant(Val: 0, DL: dl, VT: SrcVT), Cond: ISD::SETLT);
2747
2748 EVT ShiftVT = TLI.getShiftAmountTy(LHSTy: SrcVT, DL: DAG.getDataLayout());
2749 SDValue ShiftConst = DAG.getConstant(Val: 1, DL: dl, VT: ShiftVT);
2750 SDValue Shr = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: SrcVT, N1: Op0, N2: ShiftConst);
2751 SDValue AndConst = DAG.getConstant(Val: 1, DL: dl, VT: SrcVT);
2752 SDValue And = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: SrcVT, N1: Op0, N2: AndConst);
2753 SDValue Or = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: SrcVT, N1: And, N2: Shr);
2754
2755 SDValue Slow, Fast;
2756 if (Node->isStrictFPOpcode()) {
2757 // In strict mode, we must avoid spurious exceptions, and therefore
2758 // must make sure to only emit a single STRICT_SINT_TO_FP.
2759 SDValue InCvt = DAG.getSelect(DL: dl, VT: SrcVT, Cond: SignBitTest, LHS: Or, RHS: Op0);
2760 Fast = DAG.getNode(Opcode: ISD::STRICT_SINT_TO_FP, DL: dl, ResultTys: { DestVT, MVT::Other },
2761 Ops: { Node->getOperand(Num: 0), InCvt });
2762 Slow = DAG.getNode(Opcode: ISD::STRICT_FADD, DL: dl, ResultTys: { DestVT, MVT::Other },
2763 Ops: { Fast.getValue(R: 1), Fast, Fast });
2764 Chain = Slow.getValue(R: 1);
2765 // The STRICT_SINT_TO_FP inherits the exception mode from the
2766 // incoming STRICT_UINT_TO_FP node; the STRICT_FADD node can
2767 // never raise any exception.
2768 SDNodeFlags Flags;
2769 Flags.setNoFPExcept(Node->getFlags().hasNoFPExcept());
2770 Fast->setFlags(Flags);
2771 Flags.setNoFPExcept(true);
2772 Slow->setFlags(Flags);
2773 } else {
2774 SDValue SignCvt = DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: dl, VT: DestVT, Operand: Or);
2775 Slow = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: DestVT, N1: SignCvt, N2: SignCvt);
2776 Fast = DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: dl, VT: DestVT, Operand: Op0);
2777 }
2778
2779 return DAG.getSelect(DL: dl, VT: DestVT, Cond: SignBitTest, LHS: Slow, RHS: Fast);
2780 }
2781
2782 // Don't expand it if there isn't cheap fadd.
2783 if (!TLI.isOperationLegalOrCustom(
2784 Op: Node->isStrictFPOpcode() ? ISD::STRICT_FADD : ISD::FADD, VT: DestVT))
2785 return SDValue();
2786
2787 // The following optimization is valid only if every value in SrcVT (when
2788 // treated as signed) is representable in DestVT. Check that the mantissa
2789 // size of DestVT is >= than the number of bits in SrcVT -1.
2790 assert(APFloat::semanticsPrecision(DAG.EVTToAPFloatSemantics(DestVT)) >=
2791 SrcVT.getSizeInBits() - 1 &&
2792 "Cannot perform lossless SINT_TO_FP!");
2793
2794 SDValue Tmp1;
2795 if (Node->isStrictFPOpcode()) {
2796 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_SINT_TO_FP, DL: dl, ResultTys: { DestVT, MVT::Other },
2797 Ops: { Node->getOperand(Num: 0), Op0 });
2798 } else
2799 Tmp1 = DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: dl, VT: DestVT, Operand: Op0);
2800
2801 SDValue SignSet = DAG.getSetCC(DL: dl, VT: getSetCCResultType(VT: SrcVT), LHS: Op0,
2802 RHS: DAG.getConstant(Val: 0, DL: dl, VT: SrcVT), Cond: ISD::SETLT);
2803 SDValue Zero = DAG.getIntPtrConstant(Val: 0, DL: dl),
2804 Four = DAG.getIntPtrConstant(Val: 4, DL: dl);
2805 SDValue CstOffset = DAG.getSelect(DL: dl, VT: Zero.getValueType(),
2806 Cond: SignSet, LHS: Four, RHS: Zero);
2807
2808 // If the sign bit of the integer is set, the large number will be treated
2809 // as a negative number. To counteract this, the dynamic code adds an
2810 // offset depending on the data type.
2811 uint64_t FF;
2812 switch (SrcVT.getSimpleVT().SimpleTy) {
2813 default:
2814 return SDValue();
2815 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2816 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2817 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2818 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2819 }
2820 if (DAG.getDataLayout().isLittleEndian())
2821 FF <<= 32;
2822 Constant *FudgeFactor = ConstantInt::get(
2823 Ty: Type::getInt64Ty(C&: *DAG.getContext()), V: FF);
2824
2825 SDValue CPIdx =
2826 DAG.getConstantPool(C: FudgeFactor, VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
2827 Align Alignment = cast<ConstantPoolSDNode>(Val&: CPIdx)->getAlign();
2828 CPIdx = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: CPIdx.getValueType(), N1: CPIdx, N2: CstOffset);
2829 Alignment = commonAlignment(A: Alignment, Offset: 4);
2830 SDValue FudgeInReg;
2831 if (DestVT == MVT::f32)
2832 FudgeInReg = DAG.getLoad(
2833 VT: MVT::f32, dl, Chain: DAG.getEntryNode(), Ptr: CPIdx,
2834 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()),
2835 Alignment);
2836 else {
2837 SDValue Load = DAG.getExtLoad(
2838 ExtType: ISD::EXTLOAD, dl, VT: DestVT, Chain: DAG.getEntryNode(), Ptr: CPIdx,
2839 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()), MemVT: MVT::f32,
2840 Alignment);
2841 HandleSDNode Handle(Load);
2842 LegalizeOp(Node: Load.getNode());
2843 FudgeInReg = Handle.getValue();
2844 }
2845
2846 if (Node->isStrictFPOpcode()) {
2847 SDValue Result = DAG.getNode(Opcode: ISD::STRICT_FADD, DL: dl, ResultTys: { DestVT, MVT::Other },
2848 Ops: { Tmp1.getValue(R: 1), Tmp1, FudgeInReg });
2849 Chain = Result.getValue(R: 1);
2850 return Result;
2851 }
2852
2853 return DAG.getNode(Opcode: ISD::FADD, DL: dl, VT: DestVT, N1: Tmp1, N2: FudgeInReg);
2854}
2855
2856/// This function is responsible for legalizing a
2857/// *INT_TO_FP operation of the specified operand when the target requests that
2858/// we promote it. At this point, we know that the result and operand types are
2859/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2860/// operation that takes a larger input.
2861void SelectionDAGLegalize::PromoteLegalINT_TO_FP(
2862 SDNode *N, const SDLoc &dl, SmallVectorImpl<SDValue> &Results) {
2863 bool IsStrict = N->isStrictFPOpcode();
2864 bool IsSigned = N->getOpcode() == ISD::SINT_TO_FP ||
2865 N->getOpcode() == ISD::STRICT_SINT_TO_FP;
2866 EVT DestVT = N->getValueType(ResNo: 0);
2867 SDValue LegalOp = N->getOperand(Num: IsStrict ? 1 : 0);
2868 unsigned UIntOp = IsStrict ? ISD::STRICT_UINT_TO_FP : ISD::UINT_TO_FP;
2869 unsigned SIntOp = IsStrict ? ISD::STRICT_SINT_TO_FP : ISD::SINT_TO_FP;
2870
2871 // First step, figure out the appropriate *INT_TO_FP operation to use.
2872 EVT NewInTy = LegalOp.getValueType();
2873
2874 unsigned OpToUse = 0;
2875
2876 // Scan for the appropriate larger type to use.
2877 while (true) {
2878 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2879 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2880
2881 // If the target supports SINT_TO_FP of this type, use it.
2882 if (TLI.isOperationLegalOrCustom(Op: SIntOp, VT: NewInTy)) {
2883 OpToUse = SIntOp;
2884 break;
2885 }
2886 if (IsSigned)
2887 continue;
2888
2889 // If the target supports UINT_TO_FP of this type, use it.
2890 if (TLI.isOperationLegalOrCustom(Op: UIntOp, VT: NewInTy)) {
2891 OpToUse = UIntOp;
2892 break;
2893 }
2894
2895 // Otherwise, try a larger type.
2896 }
2897
2898 // Okay, we found the operation and type to use. Zero extend our input to the
2899 // desired type then run the operation on it.
2900 if (IsStrict) {
2901 SDValue Res =
2902 DAG.getNode(Opcode: OpToUse, DL: dl, ResultTys: {DestVT, MVT::Other},
2903 Ops: {N->getOperand(Num: 0),
2904 DAG.getNode(Opcode: IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2905 DL: dl, VT: NewInTy, Operand: LegalOp)});
2906 Results.push_back(Elt: Res);
2907 Results.push_back(Elt: Res.getValue(R: 1));
2908 return;
2909 }
2910
2911 Results.push_back(
2912 Elt: DAG.getNode(Opcode: OpToUse, DL: dl, VT: DestVT,
2913 Operand: DAG.getNode(Opcode: IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2914 DL: dl, VT: NewInTy, Operand: LegalOp)));
2915}
2916
2917/// This function is responsible for legalizing a
2918/// FP_TO_*INT operation of the specified operand when the target requests that
2919/// we promote it. At this point, we know that the result and operand types are
2920/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2921/// operation that returns a larger result.
2922void SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDNode *N, const SDLoc &dl,
2923 SmallVectorImpl<SDValue> &Results) {
2924 bool IsStrict = N->isStrictFPOpcode();
2925 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT ||
2926 N->getOpcode() == ISD::STRICT_FP_TO_SINT;
2927 EVT DestVT = N->getValueType(ResNo: 0);
2928 SDValue LegalOp = N->getOperand(Num: IsStrict ? 1 : 0);
2929 // First step, figure out the appropriate FP_TO*INT operation to use.
2930 EVT NewOutTy = DestVT;
2931
2932 unsigned OpToUse = 0;
2933
2934 // Scan for the appropriate larger type to use.
2935 while (true) {
2936 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2937 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2938
2939 // A larger signed type can hold all unsigned values of the requested type,
2940 // so using FP_TO_SINT is valid
2941 OpToUse = IsStrict ? ISD::STRICT_FP_TO_SINT : ISD::FP_TO_SINT;
2942 if (TLI.isOperationLegalOrCustom(Op: OpToUse, VT: NewOutTy))
2943 break;
2944
2945 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2946 OpToUse = IsStrict ? ISD::STRICT_FP_TO_UINT : ISD::FP_TO_UINT;
2947 if (!IsSigned && TLI.isOperationLegalOrCustom(Op: OpToUse, VT: NewOutTy))
2948 break;
2949
2950 // Otherwise, try a larger type.
2951 }
2952
2953 // Okay, we found the operation and type to use.
2954 SDValue Operation;
2955 if (IsStrict) {
2956 SDVTList VTs = DAG.getVTList(VT1: NewOutTy, VT2: MVT::Other);
2957 Operation = DAG.getNode(Opcode: OpToUse, DL: dl, VTList: VTs, N1: N->getOperand(Num: 0), N2: LegalOp);
2958 } else
2959 Operation = DAG.getNode(Opcode: OpToUse, DL: dl, VT: NewOutTy, Operand: LegalOp);
2960
2961 // Truncate the result of the extended FP_TO_*INT operation to the desired
2962 // size.
2963 SDValue Trunc = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: DestVT, Operand: Operation);
2964 Results.push_back(Elt: Trunc);
2965 if (IsStrict)
2966 Results.push_back(Elt: Operation.getValue(R: 1));
2967}
2968
2969/// Promote FP_TO_*INT_SAT operation to a larger result type. At this point
2970/// the result and operand types are legal and there must be a legal
2971/// FP_TO_*INT_SAT operation for a larger result type.
2972SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT_SAT(SDNode *Node,
2973 const SDLoc &dl) {
2974 unsigned Opcode = Node->getOpcode();
2975
2976 // Scan for the appropriate larger type to use.
2977 EVT NewOutTy = Node->getValueType(ResNo: 0);
2978 while (true) {
2979 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy + 1);
2980 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2981
2982 if (TLI.isOperationLegalOrCustom(Op: Opcode, VT: NewOutTy))
2983 break;
2984 }
2985
2986 // Saturation width is determined by second operand, so we don't have to
2987 // perform any fixup and can directly truncate the result.
2988 SDValue Result = DAG.getNode(Opcode, DL: dl, VT: NewOutTy, N1: Node->getOperand(Num: 0),
2989 N2: Node->getOperand(Num: 1));
2990 return DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Result);
2991}
2992
2993/// Open code the operations for PARITY of the specified operation.
2994SDValue SelectionDAGLegalize::ExpandPARITY(SDValue Op, const SDLoc &dl) {
2995 EVT VT = Op.getValueType();
2996 EVT ShVT = TLI.getShiftAmountTy(LHSTy: VT, DL: DAG.getDataLayout());
2997 unsigned Sz = VT.getScalarSizeInBits();
2998
2999 // If CTPOP is legal, use it. Otherwise use shifts and xor.
3000 SDValue Result;
3001 if (TLI.isOperationLegalOrPromote(Op: ISD::CTPOP, VT)) {
3002 Result = DAG.getNode(Opcode: ISD::CTPOP, DL: dl, VT, Operand: Op);
3003 } else {
3004 Result = Op;
3005 for (unsigned i = Log2_32_Ceil(Value: Sz); i != 0;) {
3006 SDValue Shift = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT, N1: Result,
3007 N2: DAG.getConstant(Val: 1ULL << (--i), DL: dl, VT: ShVT));
3008 Result = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT, N1: Result, N2: Shift);
3009 }
3010 }
3011
3012 return DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: Result, N2: DAG.getConstant(Val: 1, DL: dl, VT));
3013}
3014
3015SDValue SelectionDAGLegalize::PromoteReduction(SDNode *Node) {
3016 MVT VecVT = Node->getOperand(Num: 1).getSimpleValueType();
3017 MVT NewVecVT = TLI.getTypeToPromoteTo(Op: Node->getOpcode(), VT: VecVT);
3018 MVT ScalarVT = Node->getSimpleValueType(ResNo: 0);
3019 MVT NewScalarVT = NewVecVT.getVectorElementType();
3020
3021 SDLoc DL(Node);
3022 SmallVector<SDValue, 4> Operands(Node->getNumOperands());
3023
3024 // promote the initial value.
3025 // FIXME: Support integer.
3026 assert(Node->getOperand(0).getValueType().isFloatingPoint() &&
3027 "Only FP promotion is supported");
3028 Operands[0] =
3029 DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT: NewScalarVT, Operand: Node->getOperand(Num: 0));
3030
3031 for (unsigned j = 1; j != Node->getNumOperands(); ++j)
3032 if (Node->getOperand(Num: j).getValueType().isVector() &&
3033 !(ISD::isVPOpcode(Opcode: Node->getOpcode()) &&
3034 ISD::getVPMaskIdx(Opcode: Node->getOpcode()) == j)) { // Skip mask operand.
3035 // promote the vector operand.
3036 // FIXME: Support integer.
3037 assert(Node->getOperand(j).getValueType().isFloatingPoint() &&
3038 "Only FP promotion is supported");
3039 Operands[j] =
3040 DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT: NewVecVT, Operand: Node->getOperand(Num: j));
3041 } else {
3042 Operands[j] = Node->getOperand(Num: j); // Skip VL operand.
3043 }
3044
3045 SDValue Res = DAG.getNode(Opcode: Node->getOpcode(), DL, VT: NewScalarVT, Ops: Operands,
3046 Flags: Node->getFlags());
3047
3048 assert(ScalarVT.isFloatingPoint() && "Only FP promotion is supported");
3049 return DAG.getNode(Opcode: ISD::FP_ROUND, DL, VT: ScalarVT, N1: Res,
3050 N2: DAG.getIntPtrConstant(Val: 0, DL, /*isTarget=*/true));
3051}
3052
3053bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
3054 LLVM_DEBUG(dbgs() << "Trying to expand node\n");
3055 SmallVector<SDValue, 8> Results;
3056 SDLoc dl(Node);
3057 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
3058 bool NeedInvert;
3059 switch (Node->getOpcode()) {
3060 case ISD::ABS:
3061 if ((Tmp1 = TLI.expandABS(N: Node, DAG)))
3062 Results.push_back(Elt: Tmp1);
3063 break;
3064 case ISD::ABDS:
3065 case ISD::ABDU:
3066 if ((Tmp1 = TLI.expandABD(N: Node, DAG)))
3067 Results.push_back(Elt: Tmp1);
3068 break;
3069 case ISD::AVGCEILS:
3070 case ISD::AVGCEILU:
3071 case ISD::AVGFLOORS:
3072 case ISD::AVGFLOORU:
3073 if ((Tmp1 = TLI.expandAVG(N: Node, DAG)))
3074 Results.push_back(Elt: Tmp1);
3075 break;
3076 case ISD::CTPOP:
3077 if ((Tmp1 = TLI.expandCTPOP(N: Node, DAG)))
3078 Results.push_back(Elt: Tmp1);
3079 break;
3080 case ISD::CTLZ:
3081 case ISD::CTLZ_ZERO_UNDEF:
3082 if ((Tmp1 = TLI.expandCTLZ(N: Node, DAG)))
3083 Results.push_back(Elt: Tmp1);
3084 break;
3085 case ISD::CTTZ:
3086 case ISD::CTTZ_ZERO_UNDEF:
3087 if ((Tmp1 = TLI.expandCTTZ(N: Node, DAG)))
3088 Results.push_back(Elt: Tmp1);
3089 break;
3090 case ISD::BITREVERSE:
3091 if ((Tmp1 = TLI.expandBITREVERSE(N: Node, DAG)))
3092 Results.push_back(Elt: Tmp1);
3093 break;
3094 case ISD::BSWAP:
3095 if ((Tmp1 = TLI.expandBSWAP(N: Node, DAG)))
3096 Results.push_back(Elt: Tmp1);
3097 break;
3098 case ISD::PARITY:
3099 Results.push_back(Elt: ExpandPARITY(Op: Node->getOperand(Num: 0), dl));
3100 break;
3101 case ISD::FRAMEADDR:
3102 case ISD::RETURNADDR:
3103 case ISD::FRAME_TO_ARGS_OFFSET:
3104 Results.push_back(Elt: DAG.getConstant(Val: 0, DL: dl, VT: Node->getValueType(ResNo: 0)));
3105 break;
3106 case ISD::EH_DWARF_CFA: {
3107 SDValue CfaArg = DAG.getSExtOrTrunc(Op: Node->getOperand(Num: 0), DL: dl,
3108 VT: TLI.getPointerTy(DL: DAG.getDataLayout()));
3109 SDValue Offset = DAG.getNode(Opcode: ISD::ADD, DL: dl,
3110 VT: CfaArg.getValueType(),
3111 N1: DAG.getNode(Opcode: ISD::FRAME_TO_ARGS_OFFSET, DL: dl,
3112 VT: CfaArg.getValueType()),
3113 N2: CfaArg);
3114 SDValue FA = DAG.getNode(
3115 Opcode: ISD::FRAMEADDR, DL: dl, VT: TLI.getPointerTy(DL: DAG.getDataLayout()),
3116 Operand: DAG.getConstant(Val: 0, DL: dl, VT: TLI.getPointerTy(DL: DAG.getDataLayout())));
3117 Results.push_back(Elt: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: FA.getValueType(),
3118 N1: FA, N2: Offset));
3119 break;
3120 }
3121 case ISD::GET_ROUNDING:
3122 Results.push_back(Elt: DAG.getConstant(Val: 1, DL: dl, VT: Node->getValueType(ResNo: 0)));
3123 Results.push_back(Elt: Node->getOperand(Num: 0));
3124 break;
3125 case ISD::EH_RETURN:
3126 case ISD::EH_LABEL:
3127 case ISD::PREFETCH:
3128 case ISD::VAEND:
3129 case ISD::EH_SJLJ_LONGJMP:
3130 // If the target didn't expand these, there's nothing to do, so just
3131 // preserve the chain and be done.
3132 Results.push_back(Elt: Node->getOperand(Num: 0));
3133 break;
3134 case ISD::READCYCLECOUNTER:
3135 case ISD::READSTEADYCOUNTER:
3136 // If the target didn't expand this, just return 'zero' and preserve the
3137 // chain.
3138 Results.append(NumInputs: Node->getNumValues() - 1,
3139 Elt: DAG.getConstant(Val: 0, DL: dl, VT: Node->getValueType(ResNo: 0)));
3140 Results.push_back(Elt: Node->getOperand(Num: 0));
3141 break;
3142 case ISD::EH_SJLJ_SETJMP:
3143 // If the target didn't expand this, just return 'zero' and preserve the
3144 // chain.
3145 Results.push_back(Elt: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i32));
3146 Results.push_back(Elt: Node->getOperand(Num: 0));
3147 break;
3148 case ISD::ATOMIC_LOAD: {
3149 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
3150 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT: Node->getValueType(ResNo: 0));
3151 SDVTList VTs = DAG.getVTList(VT1: Node->getValueType(ResNo: 0), VT2: MVT::Other);
3152 SDValue Swap = DAG.getAtomicCmpSwap(
3153 Opcode: ISD::ATOMIC_CMP_SWAP, dl, MemVT: cast<AtomicSDNode>(Val: Node)->getMemoryVT(), VTs,
3154 Chain: Node->getOperand(Num: 0), Ptr: Node->getOperand(Num: 1), Cmp: Zero, Swp: Zero,
3155 MMO: cast<AtomicSDNode>(Val: Node)->getMemOperand());
3156 Results.push_back(Elt: Swap.getValue(R: 0));
3157 Results.push_back(Elt: Swap.getValue(R: 1));
3158 break;
3159 }
3160 case ISD::ATOMIC_STORE: {
3161 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
3162 SDValue Swap = DAG.getAtomic(
3163 Opcode: ISD::ATOMIC_SWAP, dl, MemVT: cast<AtomicSDNode>(Val: Node)->getMemoryVT(),
3164 Chain: Node->getOperand(Num: 0), Ptr: Node->getOperand(Num: 2), Val: Node->getOperand(Num: 1),
3165 MMO: cast<AtomicSDNode>(Val: Node)->getMemOperand());
3166 Results.push_back(Elt: Swap.getValue(R: 1));
3167 break;
3168 }
3169 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3170 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
3171 // splits out the success value as a comparison. Expanding the resulting
3172 // ATOMIC_CMP_SWAP will produce a libcall.
3173 SDVTList VTs = DAG.getVTList(VT1: Node->getValueType(ResNo: 0), VT2: MVT::Other);
3174 SDValue Res = DAG.getAtomicCmpSwap(
3175 Opcode: ISD::ATOMIC_CMP_SWAP, dl, MemVT: cast<AtomicSDNode>(Val: Node)->getMemoryVT(), VTs,
3176 Chain: Node->getOperand(Num: 0), Ptr: Node->getOperand(Num: 1), Cmp: Node->getOperand(Num: 2),
3177 Swp: Node->getOperand(Num: 3), MMO: cast<MemSDNode>(Val: Node)->getMemOperand());
3178
3179 SDValue ExtRes = Res;
3180 SDValue LHS = Res;
3181 SDValue RHS = Node->getOperand(Num: 1);
3182
3183 EVT AtomicType = cast<AtomicSDNode>(Val: Node)->getMemoryVT();
3184 EVT OuterType = Node->getValueType(ResNo: 0);
3185 switch (TLI.getExtendForAtomicOps()) {
3186 case ISD::SIGN_EXTEND:
3187 LHS = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: OuterType, N1: Res,
3188 N2: DAG.getValueType(AtomicType));
3189 RHS = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL: dl, VT: OuterType,
3190 N1: Node->getOperand(Num: 2), N2: DAG.getValueType(AtomicType));
3191 ExtRes = LHS;
3192 break;
3193 case ISD::ZERO_EXTEND:
3194 LHS = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: OuterType, N1: Res,
3195 N2: DAG.getValueType(AtomicType));
3196 RHS = DAG.getZeroExtendInReg(Op: Node->getOperand(Num: 2), DL: dl, VT: AtomicType);
3197 ExtRes = LHS;
3198 break;
3199 case ISD::ANY_EXTEND:
3200 LHS = DAG.getZeroExtendInReg(Op: Res, DL: dl, VT: AtomicType);
3201 RHS = DAG.getZeroExtendInReg(Op: Node->getOperand(Num: 2), DL: dl, VT: AtomicType);
3202 break;
3203 default:
3204 llvm_unreachable("Invalid atomic op extension");
3205 }
3206
3207 SDValue Success =
3208 DAG.getSetCC(DL: dl, VT: Node->getValueType(ResNo: 1), LHS, RHS, Cond: ISD::SETEQ);
3209
3210 Results.push_back(Elt: ExtRes.getValue(R: 0));
3211 Results.push_back(Elt: Success);
3212 Results.push_back(Elt: Res.getValue(R: 1));
3213 break;
3214 }
3215 case ISD::ATOMIC_LOAD_SUB: {
3216 SDLoc DL(Node);
3217 EVT VT = Node->getValueType(ResNo: 0);
3218 SDValue RHS = Node->getOperand(Num: 2);
3219 AtomicSDNode *AN = cast<AtomicSDNode>(Val: Node);
3220 if (RHS->getOpcode() == ISD::SIGN_EXTEND_INREG &&
3221 cast<VTSDNode>(Val: RHS->getOperand(Num: 1))->getVT() == AN->getMemoryVT())
3222 RHS = RHS->getOperand(Num: 0);
3223 SDValue NewRHS =
3224 DAG.getNode(Opcode: ISD::SUB, DL, VT, N1: DAG.getConstant(Val: 0, DL, VT), N2: RHS);
3225 SDValue Res = DAG.getAtomic(Opcode: ISD::ATOMIC_LOAD_ADD, dl: DL, MemVT: AN->getMemoryVT(),
3226 Chain: Node->getOperand(Num: 0), Ptr: Node->getOperand(Num: 1),
3227 Val: NewRHS, MMO: AN->getMemOperand());
3228 Results.push_back(Elt: Res);
3229 Results.push_back(Elt: Res.getValue(R: 1));
3230 break;
3231 }
3232 case ISD::DYNAMIC_STACKALLOC:
3233 ExpandDYNAMIC_STACKALLOC(Node, Results);
3234 break;
3235 case ISD::MERGE_VALUES:
3236 for (unsigned i = 0; i < Node->getNumValues(); i++)
3237 Results.push_back(Elt: Node->getOperand(Num: i));
3238 break;
3239 case ISD::UNDEF: {
3240 EVT VT = Node->getValueType(ResNo: 0);
3241 if (VT.isInteger())
3242 Results.push_back(Elt: DAG.getConstant(Val: 0, DL: dl, VT));
3243 else {
3244 assert(VT.isFloatingPoint() && "Unknown value type!");
3245 Results.push_back(Elt: DAG.getConstantFP(Val: 0, DL: dl, VT));
3246 }
3247 break;
3248 }
3249 case ISD::STRICT_FP_ROUND:
3250 // When strict mode is enforced we can't do expansion because it
3251 // does not honor the "strict" properties. Only libcall is allowed.
3252 if (TLI.isStrictFPEnabled())
3253 break;
3254 // We might as well mutate to FP_ROUND when FP_ROUND operation is legal
3255 // since this operation is more efficient than stack operation.
3256 if (TLI.getStrictFPOperationAction(Op: Node->getOpcode(),
3257 VT: Node->getValueType(ResNo: 0))
3258 == TargetLowering::Legal)
3259 break;
3260 // We fall back to use stack operation when the FP_ROUND operation
3261 // isn't available.
3262 if ((Tmp1 = EmitStackConvert(SrcOp: Node->getOperand(Num: 1), SlotVT: Node->getValueType(ResNo: 0),
3263 DestVT: Node->getValueType(ResNo: 0), dl,
3264 Chain: Node->getOperand(Num: 0)))) {
3265 ReplaceNode(Old: Node, New: Tmp1.getNode());
3266 LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_ROUND node\n");
3267 return true;
3268 }
3269 break;
3270 case ISD::FP_ROUND: {
3271 if ((Tmp1 = TLI.expandFP_ROUND(Node, DAG))) {
3272 Results.push_back(Elt: Tmp1);
3273 break;
3274 }
3275
3276 [[fallthrough]];
3277 }
3278 case ISD::BITCAST:
3279 if ((Tmp1 = EmitStackConvert(SrcOp: Node->getOperand(Num: 0), SlotVT: Node->getValueType(ResNo: 0),
3280 DestVT: Node->getValueType(ResNo: 0), dl)))
3281 Results.push_back(Elt: Tmp1);
3282 break;
3283 case ISD::STRICT_FP_EXTEND:
3284 // When strict mode is enforced we can't do expansion because it
3285 // does not honor the "strict" properties. Only libcall is allowed.
3286 if (TLI.isStrictFPEnabled())
3287 break;
3288 // We might as well mutate to FP_EXTEND when FP_EXTEND operation is legal
3289 // since this operation is more efficient than stack operation.
3290 if (TLI.getStrictFPOperationAction(Op: Node->getOpcode(),
3291 VT: Node->getValueType(ResNo: 0))
3292 == TargetLowering::Legal)
3293 break;
3294 // We fall back to use stack operation when the FP_EXTEND operation
3295 // isn't available.
3296 if ((Tmp1 = EmitStackConvert(
3297 SrcOp: Node->getOperand(Num: 1), SlotVT: Node->getOperand(Num: 1).getValueType(),
3298 DestVT: Node->getValueType(ResNo: 0), dl, Chain: Node->getOperand(Num: 0)))) {
3299 ReplaceNode(Old: Node, New: Tmp1.getNode());
3300 LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_EXTEND node\n");
3301 return true;
3302 }
3303 break;
3304 case ISD::FP_EXTEND: {
3305 SDValue Op = Node->getOperand(Num: 0);
3306 EVT SrcVT = Op.getValueType();
3307 EVT DstVT = Node->getValueType(ResNo: 0);
3308 if (SrcVT.getScalarType() == MVT::bf16) {
3309 Results.push_back(Elt: DAG.getNode(Opcode: ISD::BF16_TO_FP, DL: SDLoc(Node), VT: DstVT, Operand: Op));
3310 break;
3311 }
3312
3313 if ((Tmp1 = EmitStackConvert(SrcOp: Op, SlotVT: SrcVT, DestVT: DstVT, dl)))
3314 Results.push_back(Elt: Tmp1);
3315 break;
3316 }
3317 case ISD::BF16_TO_FP: {
3318 // Always expand bf16 to f32 casts, they lower to ext + shift.
3319 //
3320 // Note that the operand of this code can be bf16 or an integer type in case
3321 // bf16 is not supported on the target and was softened.
3322 SDValue Op = Node->getOperand(Num: 0);
3323 if (Op.getValueType() == MVT::bf16) {
3324 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: MVT::i32,
3325 Operand: DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i16, Operand: Op));
3326 } else {
3327 Op = DAG.getAnyExtOrTrunc(Op, DL: dl, VT: MVT::i32);
3328 }
3329 Op = DAG.getNode(
3330 Opcode: ISD::SHL, DL: dl, VT: MVT::i32, N1: Op,
3331 N2: DAG.getConstant(Val: 16, DL: dl,
3332 VT: TLI.getShiftAmountTy(LHSTy: MVT::i32, DL: DAG.getDataLayout())));
3333 Op = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::f32, Operand: Op);
3334 // Add fp_extend in case the output is bigger than f32.
3335 if (Node->getValueType(ResNo: 0) != MVT::f32)
3336 Op = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Op);
3337 Results.push_back(Elt: Op);
3338 break;
3339 }
3340 case ISD::FP_TO_BF16: {
3341 SDValue Op = Node->getOperand(Num: 0);
3342 if (Op.getValueType() != MVT::f32)
3343 Op = DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: MVT::f32, N1: Op,
3344 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true));
3345 // Certain SNaNs will turn into infinities if we do a simple shift right.
3346 if (!DAG.isKnownNeverSNaN(Op)) {
3347 Op = DAG.getNode(Opcode: ISD::FCANONICALIZE, DL: dl, VT: MVT::f32, Operand: Op, Flags: Node->getFlags());
3348 }
3349 Op = DAG.getNode(
3350 Opcode: ISD::SRL, DL: dl, VT: MVT::i32, N1: DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::i32, Operand: Op),
3351 N2: DAG.getConstant(Val: 16, DL: dl,
3352 VT: TLI.getShiftAmountTy(LHSTy: MVT::i32, DL: DAG.getDataLayout())));
3353 // The result of this node can be bf16 or an integer type in case bf16 is
3354 // not supported on the target and was softened to i16 for storage.
3355 if (Node->getValueType(ResNo: 0) == MVT::bf16) {
3356 Op = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: MVT::bf16,
3357 Operand: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: MVT::i16, Operand: Op));
3358 } else {
3359 Op = DAG.getAnyExtOrTrunc(Op, DL: dl, VT: Node->getValueType(ResNo: 0));
3360 }
3361 Results.push_back(Elt: Op);
3362 break;
3363 }
3364 case ISD::SIGN_EXTEND_INREG: {
3365 EVT ExtraVT = cast<VTSDNode>(Val: Node->getOperand(Num: 1))->getVT();
3366 EVT VT = Node->getValueType(ResNo: 0);
3367
3368 // An in-register sign-extend of a boolean is a negation:
3369 // 'true' (1) sign-extended is -1.
3370 // 'false' (0) sign-extended is 0.
3371 // However, we must mask the high bits of the source operand because the
3372 // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
3373
3374 // TODO: Do this for vectors too?
3375 if (ExtraVT.isScalarInteger() && ExtraVT.getSizeInBits() == 1) {
3376 SDValue One = DAG.getConstant(Val: 1, DL: dl, VT);
3377 SDValue And = DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: Node->getOperand(Num: 0), N2: One);
3378 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
3379 SDValue Neg = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT, N1: Zero, N2: And);
3380 Results.push_back(Elt: Neg);
3381 break;
3382 }
3383
3384 // NOTE: we could fall back on load/store here too for targets without
3385 // SRA. However, it is doubtful that any exist.
3386 EVT ShiftAmountTy = TLI.getShiftAmountTy(LHSTy: VT, DL: DAG.getDataLayout());
3387 unsigned BitsDiff = VT.getScalarSizeInBits() -
3388 ExtraVT.getScalarSizeInBits();
3389 SDValue ShiftCst = DAG.getConstant(Val: BitsDiff, DL: dl, VT: ShiftAmountTy);
3390 Tmp1 = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: Node->getValueType(ResNo: 0),
3391 N1: Node->getOperand(Num: 0), N2: ShiftCst);
3392 Tmp1 = DAG.getNode(Opcode: ISD::SRA, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1, N2: ShiftCst);
3393 Results.push_back(Elt: Tmp1);
3394 break;
3395 }
3396 case ISD::UINT_TO_FP:
3397 case ISD::STRICT_UINT_TO_FP:
3398 if (TLI.expandUINT_TO_FP(N: Node, Result&: Tmp1, Chain&: Tmp2, DAG)) {
3399 Results.push_back(Elt: Tmp1);
3400 if (Node->isStrictFPOpcode())
3401 Results.push_back(Elt: Tmp2);
3402 break;
3403 }
3404 [[fallthrough]];
3405 case ISD::SINT_TO_FP:
3406 case ISD::STRICT_SINT_TO_FP:
3407 if ((Tmp1 = ExpandLegalINT_TO_FP(Node, Chain&: Tmp2))) {
3408 Results.push_back(Elt: Tmp1);
3409 if (Node->isStrictFPOpcode())
3410 Results.push_back(Elt: Tmp2);
3411 }
3412 break;
3413 case ISD::FP_TO_SINT:
3414 if (TLI.expandFP_TO_SINT(N: Node, Result&: Tmp1, DAG))
3415 Results.push_back(Elt: Tmp1);
3416 break;
3417 case ISD::STRICT_FP_TO_SINT:
3418 if (TLI.expandFP_TO_SINT(N: Node, Result&: Tmp1, DAG)) {
3419 ReplaceNode(Old: Node, New: Tmp1.getNode());
3420 LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_TO_SINT node\n");
3421 return true;
3422 }
3423 break;
3424 case ISD::FP_TO_UINT:
3425 if (TLI.expandFP_TO_UINT(N: Node, Result&: Tmp1, Chain&: Tmp2, DAG))
3426 Results.push_back(Elt: Tmp1);
3427 break;
3428 case ISD::STRICT_FP_TO_UINT:
3429 if (TLI.expandFP_TO_UINT(N: Node, Result&: Tmp1, Chain&: Tmp2, DAG)) {
3430 // Relink the chain.
3431 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node,1), To: Tmp2);
3432 // Replace the new UINT result.
3433 ReplaceNodeWithValue(Old: SDValue(Node, 0), New: Tmp1);
3434 LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_TO_UINT node\n");
3435 return true;
3436 }
3437 break;
3438 case ISD::FP_TO_SINT_SAT:
3439 case ISD::FP_TO_UINT_SAT:
3440 Results.push_back(Elt: TLI.expandFP_TO_INT_SAT(N: Node, DAG));
3441 break;
3442 case ISD::VAARG:
3443 Results.push_back(Elt: DAG.expandVAArg(Node));
3444 Results.push_back(Elt: Results[0].getValue(R: 1));
3445 break;
3446 case ISD::VACOPY:
3447 Results.push_back(Elt: DAG.expandVACopy(Node));
3448 break;
3449 case ISD::EXTRACT_VECTOR_ELT:
3450 if (Node->getOperand(Num: 0).getValueType().getVectorElementCount().isScalar())
3451 // This must be an access of the only element. Return it.
3452 Tmp1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: Node->getValueType(ResNo: 0),
3453 Operand: Node->getOperand(Num: 0));
3454 else
3455 Tmp1 = ExpandExtractFromVectorThroughStack(Op: SDValue(Node, 0));
3456 Results.push_back(Elt: Tmp1);
3457 break;
3458 case ISD::EXTRACT_SUBVECTOR:
3459 Results.push_back(Elt: ExpandExtractFromVectorThroughStack(Op: SDValue(Node, 0)));
3460 break;
3461 case ISD::INSERT_SUBVECTOR:
3462 Results.push_back(Elt: ExpandInsertToVectorThroughStack(Op: SDValue(Node, 0)));
3463 break;
3464 case ISD::CONCAT_VECTORS:
3465 Results.push_back(Elt: ExpandVectorBuildThroughStack(Node));
3466 break;
3467 case ISD::SCALAR_TO_VECTOR:
3468 Results.push_back(Elt: ExpandSCALAR_TO_VECTOR(Node));
3469 break;
3470 case ISD::INSERT_VECTOR_ELT:
3471 Results.push_back(Elt: ExpandINSERT_VECTOR_ELT(Op: SDValue(Node, 0)));
3472 break;
3473 case ISD::VECTOR_SHUFFLE: {
3474 SmallVector<int, 32> NewMask;
3475 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Val: Node)->getMask();
3476
3477 EVT VT = Node->getValueType(ResNo: 0);
3478 EVT EltVT = VT.getVectorElementType();
3479 SDValue Op0 = Node->getOperand(Num: 0);
3480 SDValue Op1 = Node->getOperand(Num: 1);
3481 if (!TLI.isTypeLegal(VT: EltVT)) {
3482 EVT NewEltVT = TLI.getTypeToTransformTo(Context&: *DAG.getContext(), VT: EltVT);
3483
3484 // BUILD_VECTOR operands are allowed to be wider than the element type.
3485 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3486 // it.
3487 if (NewEltVT.bitsLT(VT: EltVT)) {
3488 // Convert shuffle node.
3489 // If original node was v4i64 and the new EltVT is i32,
3490 // cast operands to v8i32 and re-build the mask.
3491
3492 // Calculate new VT, the size of the new VT should be equal to original.
3493 EVT NewVT =
3494 EVT::getVectorVT(Context&: *DAG.getContext(), VT: NewEltVT,
3495 NumElements: VT.getSizeInBits() / NewEltVT.getSizeInBits());
3496 assert(NewVT.bitsEq(VT));
3497
3498 // cast operands to new VT
3499 Op0 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NewVT, Operand: Op0);
3500 Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NewVT, Operand: Op1);
3501
3502 // Convert the shuffle mask
3503 unsigned int factor =
3504 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3505
3506 // EltVT gets smaller
3507 assert(factor > 0);
3508
3509 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3510 if (Mask[i] < 0) {
3511 for (unsigned fi = 0; fi < factor; ++fi)
3512 NewMask.push_back(Elt: Mask[i]);
3513 }
3514 else {
3515 for (unsigned fi = 0; fi < factor; ++fi)
3516 NewMask.push_back(Elt: Mask[i]*factor+fi);
3517 }
3518 }
3519 Mask = NewMask;
3520 VT = NewVT;
3521 }
3522 EltVT = NewEltVT;
3523 }
3524 unsigned NumElems = VT.getVectorNumElements();
3525 SmallVector<SDValue, 16> Ops;
3526 for (unsigned i = 0; i != NumElems; ++i) {
3527 if (Mask[i] < 0) {
3528 Ops.push_back(Elt: DAG.getUNDEF(VT: EltVT));
3529 continue;
3530 }
3531 unsigned Idx = Mask[i];
3532 if (Idx < NumElems)
3533 Ops.push_back(Elt: DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: EltVT, N1: Op0,
3534 N2: DAG.getVectorIdxConstant(Val: Idx, DL: dl)));
3535 else
3536 Ops.push_back(
3537 Elt: DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: EltVT, N1: Op1,
3538 N2: DAG.getVectorIdxConstant(Val: Idx - NumElems, DL: dl)));
3539 }
3540
3541 Tmp1 = DAG.getBuildVector(VT, DL: dl, Ops);
3542 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3543 Tmp1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Tmp1);
3544 Results.push_back(Elt: Tmp1);
3545 break;
3546 }
3547 case ISD::VECTOR_SPLICE: {
3548 Results.push_back(Elt: TLI.expandVectorSplice(Node, DAG));
3549 break;
3550 }
3551 case ISD::EXTRACT_ELEMENT: {
3552 EVT OpTy = Node->getOperand(Num: 0).getValueType();
3553 if (Node->getConstantOperandVal(Num: 1)) {
3554 // 1 -> Hi
3555 Tmp1 = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: OpTy, N1: Node->getOperand(Num: 0),
3556 N2: DAG.getConstant(Val: OpTy.getSizeInBits() / 2, DL: dl,
3557 VT: TLI.getShiftAmountTy(
3558 LHSTy: Node->getOperand(Num: 0).getValueType(),
3559 DL: DAG.getDataLayout())));
3560 Tmp1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Tmp1);
3561 } else {
3562 // 0 -> Lo
3563 Tmp1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: Node->getValueType(ResNo: 0),
3564 Operand: Node->getOperand(Num: 0));
3565 }
3566 Results.push_back(Elt: Tmp1);
3567 break;
3568 }
3569 case ISD::STACKSAVE:
3570 // Expand to CopyFromReg if the target set
3571 // StackPointerRegisterToSaveRestore.
3572 if (Register SP = TLI.getStackPointerRegisterToSaveRestore()) {
3573 Results.push_back(Elt: DAG.getCopyFromReg(Chain: Node->getOperand(Num: 0), dl, Reg: SP,
3574 VT: Node->getValueType(ResNo: 0)));
3575 Results.push_back(Elt: Results[0].getValue(R: 1));
3576 } else {
3577 Results.push_back(Elt: DAG.getUNDEF(VT: Node->getValueType(ResNo: 0)));
3578 Results.push_back(Elt: Node->getOperand(Num: 0));
3579 }
3580 break;
3581 case ISD::STACKRESTORE:
3582 // Expand to CopyToReg if the target set
3583 // StackPointerRegisterToSaveRestore.
3584 if (Register SP = TLI.getStackPointerRegisterToSaveRestore()) {
3585 Results.push_back(Elt: DAG.getCopyToReg(Chain: Node->getOperand(Num: 0), dl, Reg: SP,
3586 N: Node->getOperand(Num: 1)));
3587 } else {
3588 Results.push_back(Elt: Node->getOperand(Num: 0));
3589 }
3590 break;
3591 case ISD::GET_DYNAMIC_AREA_OFFSET:
3592 Results.push_back(Elt: DAG.getConstant(Val: 0, DL: dl, VT: Node->getValueType(ResNo: 0)));
3593 Results.push_back(Elt: Results[0].getValue(R: 0));
3594 break;
3595 case ISD::FCOPYSIGN:
3596 Results.push_back(Elt: ExpandFCOPYSIGN(Node));
3597 break;
3598 case ISD::FNEG:
3599 Results.push_back(Elt: ExpandFNEG(Node));
3600 break;
3601 case ISD::FABS:
3602 Results.push_back(Elt: ExpandFABS(Node));
3603 break;
3604 case ISD::IS_FPCLASS: {
3605 auto Test = static_cast<FPClassTest>(Node->getConstantOperandVal(Num: 1));
3606 if (SDValue Expanded =
3607 TLI.expandIS_FPCLASS(ResultVT: Node->getValueType(ResNo: 0), Op: Node->getOperand(Num: 0),
3608 Test, Flags: Node->getFlags(), DL: SDLoc(Node), DAG))
3609 Results.push_back(Elt: Expanded);
3610 break;
3611 }
3612 case ISD::SMIN:
3613 case ISD::SMAX:
3614 case ISD::UMIN:
3615 case ISD::UMAX: {
3616 // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3617 ISD::CondCode Pred;
3618 switch (Node->getOpcode()) {
3619 default: llvm_unreachable("How did we get here?");
3620 case ISD::SMAX: Pred = ISD::SETGT; break;
3621 case ISD::SMIN: Pred = ISD::SETLT; break;
3622 case ISD::UMAX: Pred = ISD::SETUGT; break;
3623 case ISD::UMIN: Pred = ISD::SETULT; break;
3624 }
3625 Tmp1 = Node->getOperand(Num: 0);
3626 Tmp2 = Node->getOperand(Num: 1);
3627 Tmp1 = DAG.getSelectCC(DL: dl, LHS: Tmp1, RHS: Tmp2, True: Tmp1, False: Tmp2, Cond: Pred);
3628 Results.push_back(Elt: Tmp1);
3629 break;
3630 }
3631 case ISD::FMINNUM:
3632 case ISD::FMAXNUM: {
3633 if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(N: Node, DAG))
3634 Results.push_back(Elt: Expanded);
3635 break;
3636 }
3637 case ISD::FMINIMUM:
3638 case ISD::FMAXIMUM: {
3639 if (SDValue Expanded = TLI.expandFMINIMUM_FMAXIMUM(N: Node, DAG))
3640 Results.push_back(Elt: Expanded);
3641 break;
3642 }
3643 case ISD::FSIN:
3644 case ISD::FCOS: {
3645 EVT VT = Node->getValueType(ResNo: 0);
3646 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3647 // fcos which share the same operand and both are used.
3648 if ((TLI.isOperationLegalOrCustom(Op: ISD::FSINCOS, VT) ||
3649 isSinCosLibcallAvailable(Node, TLI))
3650 && useSinCos(Node)) {
3651 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: VT);
3652 Tmp1 = DAG.getNode(Opcode: ISD::FSINCOS, DL: dl, VTList: VTs, N: Node->getOperand(Num: 0));
3653 if (Node->getOpcode() == ISD::FCOS)
3654 Tmp1 = Tmp1.getValue(R: 1);
3655 Results.push_back(Elt: Tmp1);
3656 }
3657 break;
3658 }
3659 case ISD::FLDEXP:
3660 case ISD::STRICT_FLDEXP: {
3661 EVT VT = Node->getValueType(ResNo: 0);
3662 RTLIB::Libcall LC = RTLIB::getLDEXP(RetVT: VT);
3663 // Use the LibCall instead, it is very likely faster
3664 // FIXME: Use separate LibCall action.
3665 if (TLI.getLibcallName(Call: LC))
3666 break;
3667
3668 if (SDValue Expanded = expandLdexp(Node)) {
3669 Results.push_back(Elt: Expanded);
3670 if (Node->getOpcode() == ISD::STRICT_FLDEXP)
3671 Results.push_back(Elt: Expanded.getValue(R: 1));
3672 }
3673
3674 break;
3675 }
3676 case ISD::FFREXP: {
3677 RTLIB::Libcall LC = RTLIB::getFREXP(RetVT: Node->getValueType(ResNo: 0));
3678 // Use the LibCall instead, it is very likely faster
3679 // FIXME: Use separate LibCall action.
3680 if (TLI.getLibcallName(Call: LC))
3681 break;
3682
3683 if (SDValue Expanded = expandFrexp(Node)) {
3684 Results.push_back(Elt: Expanded);
3685 Results.push_back(Elt: Expanded.getValue(R: 1));
3686 }
3687 break;
3688 }
3689 case ISD::FMAD:
3690 llvm_unreachable("Illegal fmad should never be formed");
3691
3692 case ISD::FP16_TO_FP:
3693 if (Node->getValueType(ResNo: 0) != MVT::f32) {
3694 // We can extend to types bigger than f32 in two steps without changing
3695 // the result. Since "f16 -> f32" is much more commonly available, give
3696 // CodeGen the option of emitting that before resorting to a libcall.
3697 SDValue Res =
3698 DAG.getNode(Opcode: ISD::FP16_TO_FP, DL: dl, VT: MVT::f32, Operand: Node->getOperand(Num: 0));
3699 Results.push_back(
3700 Elt: DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Res));
3701 }
3702 break;
3703 case ISD::STRICT_BF16_TO_FP:
3704 case ISD::STRICT_FP16_TO_FP:
3705 if (Node->getValueType(ResNo: 0) != MVT::f32) {
3706 // We can extend to types bigger than f32 in two steps without changing
3707 // the result. Since "f16 -> f32" is much more commonly available, give
3708 // CodeGen the option of emitting that before resorting to a libcall.
3709 SDValue Res = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, ResultTys: {MVT::f32, MVT::Other},
3710 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1)});
3711 Res = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl,
3712 ResultTys: {Node->getValueType(ResNo: 0), MVT::Other},
3713 Ops: {Res.getValue(R: 1), Res});
3714 Results.push_back(Elt: Res);
3715 Results.push_back(Elt: Res.getValue(R: 1));
3716 }
3717 break;
3718 case ISD::FP_TO_FP16:
3719 LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n");
3720 if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3721 SDValue Op = Node->getOperand(Num: 0);
3722 MVT SVT = Op.getSimpleValueType();
3723 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3724 TLI.isOperationLegalOrCustom(Op: ISD::FP_TO_FP16, VT: MVT::f32)) {
3725 // Under fastmath, we can expand this node into a fround followed by
3726 // a float-half conversion.
3727 SDValue FloatVal =
3728 DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: MVT::f32, N1: Op,
3729 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true));
3730 Results.push_back(
3731 Elt: DAG.getNode(Opcode: ISD::FP_TO_FP16, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: FloatVal));
3732 }
3733 }
3734 break;
3735 case ISD::ConstantFP: {
3736 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Val: Node);
3737 // Check to see if this FP immediate is already legal.
3738 // If this is a legal constant, turn it into a TargetConstantFP node.
3739 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(ResNo: 0),
3740 ForCodeSize: DAG.shouldOptForSize()))
3741 Results.push_back(Elt: ExpandConstantFP(CFP, UseCP: true));
3742 break;
3743 }
3744 case ISD::Constant: {
3745 ConstantSDNode *CP = cast<ConstantSDNode>(Val: Node);
3746 Results.push_back(Elt: ExpandConstant(CP));
3747 break;
3748 }
3749 case ISD::FSUB: {
3750 EVT VT = Node->getValueType(ResNo: 0);
3751 if (TLI.isOperationLegalOrCustom(Op: ISD::FADD, VT) &&
3752 TLI.isOperationLegalOrCustom(Op: ISD::FNEG, VT)) {
3753 const SDNodeFlags Flags = Node->getFlags();
3754 Tmp1 = DAG.getNode(Opcode: ISD::FNEG, DL: dl, VT, Operand: Node->getOperand(Num: 1));
3755 Tmp1 = DAG.getNode(Opcode: ISD::FADD, DL: dl, VT, N1: Node->getOperand(Num: 0), N2: Tmp1, Flags);
3756 Results.push_back(Elt: Tmp1);
3757 }
3758 break;
3759 }
3760 case ISD::SUB: {
3761 EVT VT = Node->getValueType(ResNo: 0);
3762 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3763 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3764 "Don't know how to expand this subtraction!");
3765 Tmp1 = DAG.getNOT(DL: dl, Val: Node->getOperand(Num: 1), VT);
3766 Tmp1 = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: Tmp1, N2: DAG.getConstant(Val: 1, DL: dl, VT));
3767 Results.push_back(Elt: DAG.getNode(Opcode: ISD::ADD, DL: dl, VT, N1: Node->getOperand(Num: 0), N2: Tmp1));
3768 break;
3769 }
3770 case ISD::UREM:
3771 case ISD::SREM:
3772 if (TLI.expandREM(Node, Result&: Tmp1, DAG))
3773 Results.push_back(Elt: Tmp1);
3774 break;
3775 case ISD::UDIV:
3776 case ISD::SDIV: {
3777 bool isSigned = Node->getOpcode() == ISD::SDIV;
3778 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3779 EVT VT = Node->getValueType(ResNo: 0);
3780 if (TLI.isOperationLegalOrCustom(Op: DivRemOpc, VT)) {
3781 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: VT);
3782 Tmp1 = DAG.getNode(Opcode: DivRemOpc, DL: dl, VTList: VTs, N1: Node->getOperand(Num: 0),
3783 N2: Node->getOperand(Num: 1));
3784 Results.push_back(Elt: Tmp1);
3785 }
3786 break;
3787 }
3788 case ISD::MULHU:
3789 case ISD::MULHS: {
3790 unsigned ExpandOpcode =
3791 Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI;
3792 EVT VT = Node->getValueType(ResNo: 0);
3793 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: VT);
3794
3795 Tmp1 = DAG.getNode(Opcode: ExpandOpcode, DL: dl, VTList: VTs, N1: Node->getOperand(Num: 0),
3796 N2: Node->getOperand(Num: 1));
3797 Results.push_back(Elt: Tmp1.getValue(R: 1));
3798 break;
3799 }
3800 case ISD::UMUL_LOHI:
3801 case ISD::SMUL_LOHI: {
3802 SDValue LHS = Node->getOperand(Num: 0);
3803 SDValue RHS = Node->getOperand(Num: 1);
3804 MVT VT = LHS.getSimpleValueType();
3805 unsigned MULHOpcode =
3806 Node->getOpcode() == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS;
3807
3808 if (TLI.isOperationLegalOrCustom(Op: MULHOpcode, VT)) {
3809 Results.push_back(Elt: DAG.getNode(Opcode: ISD::MUL, DL: dl, VT, N1: LHS, N2: RHS));
3810 Results.push_back(Elt: DAG.getNode(Opcode: MULHOpcode, DL: dl, VT, N1: LHS, N2: RHS));
3811 break;
3812 }
3813
3814 SmallVector<SDValue, 4> Halves;
3815 EVT HalfType = EVT(VT).getHalfSizedIntegerVT(Context&: *DAG.getContext());
3816 assert(TLI.isTypeLegal(HalfType));
3817 if (TLI.expandMUL_LOHI(Opcode: Node->getOpcode(), VT, dl, LHS, RHS, Result&: Halves,
3818 HiLoVT: HalfType, DAG,
3819 Kind: TargetLowering::MulExpansionKind::Always)) {
3820 for (unsigned i = 0; i < 2; ++i) {
3821 SDValue Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: Halves[2 * i]);
3822 SDValue Hi = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT, Operand: Halves[2 * i + 1]);
3823 SDValue Shift = DAG.getConstant(
3824 Val: HalfType.getScalarSizeInBits(), DL: dl,
3825 VT: TLI.getShiftAmountTy(LHSTy: HalfType, DL: DAG.getDataLayout()));
3826 Hi = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT, N1: Hi, N2: Shift);
3827 Results.push_back(Elt: DAG.getNode(Opcode: ISD::OR, DL: dl, VT, N1: Lo, N2: Hi));
3828 }
3829 break;
3830 }
3831 break;
3832 }
3833 case ISD::MUL: {
3834 EVT VT = Node->getValueType(ResNo: 0);
3835 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: VT);
3836 // See if multiply or divide can be lowered using two-result operations.
3837 // We just need the low half of the multiply; try both the signed
3838 // and unsigned forms. If the target supports both SMUL_LOHI and
3839 // UMUL_LOHI, form a preference by checking which forms of plain
3840 // MULH it supports.
3841 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(Op: ISD::SMUL_LOHI, VT);
3842 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(Op: ISD::UMUL_LOHI, VT);
3843 bool HasMULHS = TLI.isOperationLegalOrCustom(Op: ISD::MULHS, VT);
3844 bool HasMULHU = TLI.isOperationLegalOrCustom(Op: ISD::MULHU, VT);
3845 unsigned OpToUse = 0;
3846 if (HasSMUL_LOHI && !HasMULHS) {
3847 OpToUse = ISD::SMUL_LOHI;
3848 } else if (HasUMUL_LOHI && !HasMULHU) {
3849 OpToUse = ISD::UMUL_LOHI;
3850 } else if (HasSMUL_LOHI) {
3851 OpToUse = ISD::SMUL_LOHI;
3852 } else if (HasUMUL_LOHI) {
3853 OpToUse = ISD::UMUL_LOHI;
3854 }
3855 if (OpToUse) {
3856 Results.push_back(Elt: DAG.getNode(Opcode: OpToUse, DL: dl, VTList: VTs, N1: Node->getOperand(Num: 0),
3857 N2: Node->getOperand(Num: 1)));
3858 break;
3859 }
3860
3861 SDValue Lo, Hi;
3862 EVT HalfType = VT.getHalfSizedIntegerVT(Context&: *DAG.getContext());
3863 if (TLI.isOperationLegalOrCustom(Op: ISD::ZERO_EXTEND, VT) &&
3864 TLI.isOperationLegalOrCustom(Op: ISD::ANY_EXTEND, VT) &&
3865 TLI.isOperationLegalOrCustom(Op: ISD::SHL, VT) &&
3866 TLI.isOperationLegalOrCustom(Op: ISD::OR, VT) &&
3867 TLI.expandMUL(N: Node, Lo, Hi, HiLoVT: HalfType, DAG,
3868 Kind: TargetLowering::MulExpansionKind::OnlyLegalOrCustom)) {
3869 Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT, Operand: Lo);
3870 Hi = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT, Operand: Hi);
3871 SDValue Shift =
3872 DAG.getConstant(Val: HalfType.getSizeInBits(), DL: dl,
3873 VT: TLI.getShiftAmountTy(LHSTy: HalfType, DL: DAG.getDataLayout()));
3874 Hi = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT, N1: Hi, N2: Shift);
3875 Results.push_back(Elt: DAG.getNode(Opcode: ISD::OR, DL: dl, VT, N1: Lo, N2: Hi));
3876 }
3877 break;
3878 }
3879 case ISD::FSHL:
3880 case ISD::FSHR:
3881 if (SDValue Expanded = TLI.expandFunnelShift(N: Node, DAG))
3882 Results.push_back(Elt: Expanded);
3883 break;
3884 case ISD::ROTL:
3885 case ISD::ROTR:
3886 if (SDValue Expanded = TLI.expandROT(N: Node, AllowVectorOps: true /*AllowVectorOps*/, DAG))
3887 Results.push_back(Elt: Expanded);
3888 break;
3889 case ISD::SADDSAT:
3890 case ISD::UADDSAT:
3891 case ISD::SSUBSAT:
3892 case ISD::USUBSAT:
3893 Results.push_back(Elt: TLI.expandAddSubSat(Node, DAG));
3894 break;
3895 case ISD::SCMP:
3896 case ISD::UCMP:
3897 Results.push_back(Elt: TLI.expandCMP(Node, DAG));
3898 break;
3899 case ISD::SSHLSAT:
3900 case ISD::USHLSAT:
3901 Results.push_back(Elt: TLI.expandShlSat(Node, DAG));
3902 break;
3903 case ISD::SMULFIX:
3904 case ISD::SMULFIXSAT:
3905 case ISD::UMULFIX:
3906 case ISD::UMULFIXSAT:
3907 Results.push_back(Elt: TLI.expandFixedPointMul(Node, DAG));
3908 break;
3909 case ISD::SDIVFIX:
3910 case ISD::SDIVFIXSAT:
3911 case ISD::UDIVFIX:
3912 case ISD::UDIVFIXSAT:
3913 if (SDValue V = TLI.expandFixedPointDiv(Opcode: Node->getOpcode(), dl: SDLoc(Node),
3914 LHS: Node->getOperand(Num: 0),
3915 RHS: Node->getOperand(Num: 1),
3916 Scale: Node->getConstantOperandVal(Num: 2),
3917 DAG)) {
3918 Results.push_back(Elt: V);
3919 break;
3920 }
3921 // FIXME: We might want to retry here with a wider type if we fail, if that
3922 // type is legal.
3923 // FIXME: Technically, so long as we only have sdivfixes where BW+Scale is
3924 // <= 128 (which is the case for all of the default Embedded-C types),
3925 // we will only get here with types and scales that we could always expand
3926 // if we were allowed to generate libcalls to division functions of illegal
3927 // type. But we cannot do that.
3928 llvm_unreachable("Cannot expand DIVFIX!");
3929 case ISD::UADDO_CARRY:
3930 case ISD::USUBO_CARRY: {
3931 SDValue LHS = Node->getOperand(Num: 0);
3932 SDValue RHS = Node->getOperand(Num: 1);
3933 SDValue Carry = Node->getOperand(Num: 2);
3934
3935 bool IsAdd = Node->getOpcode() == ISD::UADDO_CARRY;
3936
3937 // Initial add of the 2 operands.
3938 unsigned Op = IsAdd ? ISD::ADD : ISD::SUB;
3939 EVT VT = LHS.getValueType();
3940 SDValue Sum = DAG.getNode(Opcode: Op, DL: dl, VT, N1: LHS, N2: RHS);
3941
3942 // Initial check for overflow.
3943 EVT CarryType = Node->getValueType(ResNo: 1);
3944 EVT SetCCType = getSetCCResultType(VT: Node->getValueType(ResNo: 0));
3945 ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
3946 SDValue Overflow = DAG.getSetCC(DL: dl, VT: SetCCType, LHS: Sum, RHS: LHS, Cond: CC);
3947
3948 // Add of the sum and the carry.
3949 SDValue One = DAG.getConstant(Val: 1, DL: dl, VT);
3950 SDValue CarryExt =
3951 DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: DAG.getZExtOrTrunc(Op: Carry, DL: dl, VT), N2: One);
3952 SDValue Sum2 = DAG.getNode(Opcode: Op, DL: dl, VT, N1: Sum, N2: CarryExt);
3953
3954 // Second check for overflow. If we are adding, we can only overflow if the
3955 // initial sum is all 1s ang the carry is set, resulting in a new sum of 0.
3956 // If we are subtracting, we can only overflow if the initial sum is 0 and
3957 // the carry is set, resulting in a new sum of all 1s.
3958 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT);
3959 SDValue Overflow2 =
3960 IsAdd ? DAG.getSetCC(DL: dl, VT: SetCCType, LHS: Sum2, RHS: Zero, Cond: ISD::SETEQ)
3961 : DAG.getSetCC(DL: dl, VT: SetCCType, LHS: Sum, RHS: Zero, Cond: ISD::SETEQ);
3962 Overflow2 = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: SetCCType, N1: Overflow2,
3963 N2: DAG.getZExtOrTrunc(Op: Carry, DL: dl, VT: SetCCType));
3964
3965 SDValue ResultCarry =
3966 DAG.getNode(Opcode: ISD::OR, DL: dl, VT: SetCCType, N1: Overflow, N2: Overflow2);
3967
3968 Results.push_back(Elt: Sum2);
3969 Results.push_back(Elt: DAG.getBoolExtOrTrunc(Op: ResultCarry, SL: dl, VT: CarryType, OpVT: VT));
3970 break;
3971 }
3972 case ISD::SADDO:
3973 case ISD::SSUBO: {
3974 SDValue Result, Overflow;
3975 TLI.expandSADDSUBO(Node, Result, Overflow, DAG);
3976 Results.push_back(Elt: Result);
3977 Results.push_back(Elt: Overflow);
3978 break;
3979 }
3980 case ISD::UADDO:
3981 case ISD::USUBO: {
3982 SDValue Result, Overflow;
3983 TLI.expandUADDSUBO(Node, Result, Overflow, DAG);
3984 Results.push_back(Elt: Result);
3985 Results.push_back(Elt: Overflow);
3986 break;
3987 }
3988 case ISD::UMULO:
3989 case ISD::SMULO: {
3990 SDValue Result, Overflow;
3991 if (TLI.expandMULO(Node, Result, Overflow, DAG)) {
3992 Results.push_back(Elt: Result);
3993 Results.push_back(Elt: Overflow);
3994 }
3995 break;
3996 }
3997 case ISD::BUILD_PAIR: {
3998 EVT PairTy = Node->getValueType(ResNo: 0);
3999 Tmp1 = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: PairTy, Operand: Node->getOperand(Num: 0));
4000 Tmp2 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: PairTy, Operand: Node->getOperand(Num: 1));
4001 Tmp2 = DAG.getNode(
4002 Opcode: ISD::SHL, DL: dl, VT: PairTy, N1: Tmp2,
4003 N2: DAG.getConstant(Val: PairTy.getSizeInBits() / 2, DL: dl,
4004 VT: TLI.getShiftAmountTy(LHSTy: PairTy, DL: DAG.getDataLayout())));
4005 Results.push_back(Elt: DAG.getNode(Opcode: ISD::OR, DL: dl, VT: PairTy, N1: Tmp1, N2: Tmp2));
4006 break;
4007 }
4008 case ISD::SELECT:
4009 Tmp1 = Node->getOperand(Num: 0);
4010 Tmp2 = Node->getOperand(Num: 1);
4011 Tmp3 = Node->getOperand(Num: 2);
4012 if (Tmp1.getOpcode() == ISD::SETCC) {
4013 Tmp1 = DAG.getSelectCC(DL: dl, LHS: Tmp1.getOperand(i: 0), RHS: Tmp1.getOperand(i: 1),
4014 True: Tmp2, False: Tmp3,
4015 Cond: cast<CondCodeSDNode>(Val: Tmp1.getOperand(i: 2))->get());
4016 } else {
4017 Tmp1 = DAG.getSelectCC(DL: dl, LHS: Tmp1,
4018 RHS: DAG.getConstant(Val: 0, DL: dl, VT: Tmp1.getValueType()),
4019 True: Tmp2, False: Tmp3, Cond: ISD::SETNE);
4020 }
4021 Tmp1->setFlags(Node->getFlags());
4022 Results.push_back(Elt: Tmp1);
4023 break;
4024 case ISD::BR_JT: {
4025 SDValue Chain = Node->getOperand(Num: 0);
4026 SDValue Table = Node->getOperand(Num: 1);
4027 SDValue Index = Node->getOperand(Num: 2);
4028 int JTI = cast<JumpTableSDNode>(Val: Table.getNode())->getIndex();
4029
4030 const DataLayout &TD = DAG.getDataLayout();
4031 EVT PTy = TLI.getPointerTy(DL: TD);
4032
4033 unsigned EntrySize =
4034 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
4035
4036 // For power-of-two jumptable entry sizes convert multiplication to a shift.
4037 // This transformation needs to be done here since otherwise the MIPS
4038 // backend will end up emitting a three instruction multiply sequence
4039 // instead of a single shift and MSP430 will call a runtime function.
4040 if (llvm::isPowerOf2_32(Value: EntrySize))
4041 Index = DAG.getNode(
4042 Opcode: ISD::SHL, DL: dl, VT: Index.getValueType(), N1: Index,
4043 N2: DAG.getConstant(Val: llvm::Log2_32(Value: EntrySize), DL: dl, VT: Index.getValueType()));
4044 else
4045 Index = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT: Index.getValueType(), N1: Index,
4046 N2: DAG.getConstant(Val: EntrySize, DL: dl, VT: Index.getValueType()));
4047 SDValue Addr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: Index.getValueType(),
4048 N1: Index, N2: Table);
4049
4050 EVT MemVT = EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: EntrySize * 8);
4051 SDValue LD = DAG.getExtLoad(
4052 ExtType: ISD::SEXTLOAD, dl, VT: PTy, Chain, Ptr: Addr,
4053 PtrInfo: MachinePointerInfo::getJumpTable(MF&: DAG.getMachineFunction()), MemVT);
4054 Addr = LD;
4055 if (TLI.isJumpTableRelative()) {
4056 // For PIC, the sequence is:
4057 // BRIND(load(Jumptable + index) + RelocBase)
4058 // RelocBase can be JumpTable, GOT or some sort of global base.
4059 Addr = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: PTy, N1: Addr,
4060 N2: TLI.getPICJumpTableRelocBase(Table, DAG));
4061 }
4062
4063 Tmp1 = TLI.expandIndirectJTBranch(dl, Value: LD.getValue(R: 1), Addr, JTI, DAG);
4064 Results.push_back(Elt: Tmp1);
4065 break;
4066 }
4067 case ISD::BRCOND:
4068 // Expand brcond's setcc into its constituent parts and create a BR_CC
4069 // Node.
4070 Tmp1 = Node->getOperand(Num: 0);
4071 Tmp2 = Node->getOperand(Num: 1);
4072 if (Tmp2.getOpcode() == ISD::SETCC &&
4073 TLI.isOperationLegalOrCustom(Op: ISD::BR_CC,
4074 VT: Tmp2.getOperand(i: 0).getValueType())) {
4075 Tmp1 = DAG.getNode(Opcode: ISD::BR_CC, DL: dl, VT: MVT::Other, N1: Tmp1, N2: Tmp2.getOperand(i: 2),
4076 N3: Tmp2.getOperand(i: 0), N4: Tmp2.getOperand(i: 1),
4077 N5: Node->getOperand(Num: 2));
4078 } else {
4079 // We test only the i1 bit. Skip the AND if UNDEF or another AND.
4080 if (Tmp2.isUndef() ||
4081 (Tmp2.getOpcode() == ISD::AND && isOneConstant(V: Tmp2.getOperand(i: 1))))
4082 Tmp3 = Tmp2;
4083 else
4084 Tmp3 = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: Tmp2.getValueType(), N1: Tmp2,
4085 N2: DAG.getConstant(Val: 1, DL: dl, VT: Tmp2.getValueType()));
4086 Tmp1 = DAG.getNode(Opcode: ISD::BR_CC, DL: dl, VT: MVT::Other, N1: Tmp1,
4087 N2: DAG.getCondCode(Cond: ISD::SETNE), N3: Tmp3,
4088 N4: DAG.getConstant(Val: 0, DL: dl, VT: Tmp3.getValueType()),
4089 N5: Node->getOperand(Num: 2));
4090 }
4091 Results.push_back(Elt: Tmp1);
4092 break;
4093 case ISD::SETCC:
4094 case ISD::VP_SETCC:
4095 case ISD::STRICT_FSETCC:
4096 case ISD::STRICT_FSETCCS: {
4097 bool IsVP = Node->getOpcode() == ISD::VP_SETCC;
4098 bool IsStrict = Node->getOpcode() == ISD::STRICT_FSETCC ||
4099 Node->getOpcode() == ISD::STRICT_FSETCCS;
4100 bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS;
4101 SDValue Chain = IsStrict ? Node->getOperand(Num: 0) : SDValue();
4102 unsigned Offset = IsStrict ? 1 : 0;
4103 Tmp1 = Node->getOperand(Num: 0 + Offset);
4104 Tmp2 = Node->getOperand(Num: 1 + Offset);
4105 Tmp3 = Node->getOperand(Num: 2 + Offset);
4106 SDValue Mask, EVL;
4107 if (IsVP) {
4108 Mask = Node->getOperand(Num: 3 + Offset);
4109 EVL = Node->getOperand(Num: 4 + Offset);
4110 }
4111 bool Legalized = TLI.LegalizeSetCCCondCode(
4112 DAG, VT: Node->getValueType(ResNo: 0), LHS&: Tmp1, RHS&: Tmp2, CC&: Tmp3, Mask, EVL, NeedInvert, dl,
4113 Chain, IsSignaling);
4114
4115 if (Legalized) {
4116 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
4117 // condition code, create a new SETCC node.
4118 if (Tmp3.getNode()) {
4119 if (IsStrict) {
4120 Tmp1 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VTList: Node->getVTList(),
4121 Ops: {Chain, Tmp1, Tmp2, Tmp3}, Flags: Node->getFlags());
4122 Chain = Tmp1.getValue(R: 1);
4123 } else if (IsVP) {
4124 Tmp1 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: Node->getValueType(ResNo: 0),
4125 Ops: {Tmp1, Tmp2, Tmp3, Mask, EVL}, Flags: Node->getFlags());
4126 } else {
4127 Tmp1 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1,
4128 N2: Tmp2, N3: Tmp3, Flags: Node->getFlags());
4129 }
4130 }
4131
4132 // If we expanded the SETCC by inverting the condition code, then wrap
4133 // the existing SETCC in a NOT to restore the intended condition.
4134 if (NeedInvert) {
4135 if (!IsVP)
4136 Tmp1 = DAG.getLogicalNOT(DL: dl, Val: Tmp1, VT: Tmp1->getValueType(ResNo: 0));
4137 else
4138 Tmp1 =
4139 DAG.getVPLogicalNOT(DL: dl, Val: Tmp1, Mask, EVL, VT: Tmp1->getValueType(ResNo: 0));
4140 }
4141
4142 Results.push_back(Elt: Tmp1);
4143 if (IsStrict)
4144 Results.push_back(Elt: Chain);
4145
4146 break;
4147 }
4148
4149 // FIXME: It seems Legalized is false iff CCCode is Legal. I don't
4150 // understand if this code is useful for strict nodes.
4151 assert(!IsStrict && "Don't know how to expand for strict nodes.");
4152
4153 // Otherwise, SETCC for the given comparison type must be completely
4154 // illegal; expand it into a SELECT_CC.
4155 // FIXME: This drops the mask/evl for VP_SETCC.
4156 EVT VT = Node->getValueType(ResNo: 0);
4157 EVT Tmp1VT = Tmp1.getValueType();
4158 Tmp1 = DAG.getNode(Opcode: ISD::SELECT_CC, DL: dl, VT, N1: Tmp1, N2: Tmp2,
4159 N3: DAG.getBoolConstant(V: true, DL: dl, VT, OpVT: Tmp1VT),
4160 N4: DAG.getBoolConstant(V: false, DL: dl, VT, OpVT: Tmp1VT), N5: Tmp3);
4161 Tmp1->setFlags(Node->getFlags());
4162 Results.push_back(Elt: Tmp1);
4163 break;
4164 }
4165 case ISD::SELECT_CC: {
4166 // TODO: need to add STRICT_SELECT_CC and STRICT_SELECT_CCS
4167 Tmp1 = Node->getOperand(Num: 0); // LHS
4168 Tmp2 = Node->getOperand(Num: 1); // RHS
4169 Tmp3 = Node->getOperand(Num: 2); // True
4170 Tmp4 = Node->getOperand(Num: 3); // False
4171 EVT VT = Node->getValueType(ResNo: 0);
4172 SDValue Chain;
4173 SDValue CC = Node->getOperand(Num: 4);
4174 ISD::CondCode CCOp = cast<CondCodeSDNode>(Val&: CC)->get();
4175
4176 if (TLI.isCondCodeLegalOrCustom(CC: CCOp, VT: Tmp1.getSimpleValueType())) {
4177 // If the condition code is legal, then we need to expand this
4178 // node using SETCC and SELECT.
4179 EVT CmpVT = Tmp1.getValueType();
4180 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
4181 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
4182 "expanded.");
4183 EVT CCVT = getSetCCResultType(VT: CmpVT);
4184 SDValue Cond = DAG.getNode(Opcode: ISD::SETCC, DL: dl, VT: CCVT, N1: Tmp1, N2: Tmp2, N3: CC, Flags: Node->getFlags());
4185 Results.push_back(
4186 Elt: DAG.getSelect(DL: dl, VT, Cond, LHS: Tmp3, RHS: Tmp4, Flags: Node->getFlags()));
4187 break;
4188 }
4189
4190 // SELECT_CC is legal, so the condition code must not be.
4191 bool Legalized = false;
4192 // Try to legalize by inverting the condition. This is for targets that
4193 // might support an ordered version of a condition, but not the unordered
4194 // version (or vice versa).
4195 ISD::CondCode InvCC = ISD::getSetCCInverse(Operation: CCOp, Type: Tmp1.getValueType());
4196 if (TLI.isCondCodeLegalOrCustom(CC: InvCC, VT: Tmp1.getSimpleValueType())) {
4197 // Use the new condition code and swap true and false
4198 Legalized = true;
4199 Tmp1 = DAG.getSelectCC(DL: dl, LHS: Tmp1, RHS: Tmp2, True: Tmp4, False: Tmp3, Cond: InvCC);
4200 Tmp1->setFlags(Node->getFlags());
4201 } else {
4202 // If The inverse is not legal, then try to swap the arguments using
4203 // the inverse condition code.
4204 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(Operation: InvCC);
4205 if (TLI.isCondCodeLegalOrCustom(CC: SwapInvCC, VT: Tmp1.getSimpleValueType())) {
4206 // The swapped inverse condition is legal, so swap true and false,
4207 // lhs and rhs.
4208 Legalized = true;
4209 Tmp1 = DAG.getSelectCC(DL: dl, LHS: Tmp2, RHS: Tmp1, True: Tmp4, False: Tmp3, Cond: SwapInvCC);
4210 Tmp1->setFlags(Node->getFlags());
4211 }
4212 }
4213
4214 if (!Legalized) {
4215 Legalized = TLI.LegalizeSetCCCondCode(
4216 DAG, VT: getSetCCResultType(VT: Tmp1.getValueType()), LHS&: Tmp1, RHS&: Tmp2, CC,
4217 /*Mask*/ SDValue(), /*EVL*/ SDValue(), NeedInvert, dl, Chain);
4218
4219 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
4220
4221 // If we expanded the SETCC by inverting the condition code, then swap
4222 // the True/False operands to match.
4223 if (NeedInvert)
4224 std::swap(a&: Tmp3, b&: Tmp4);
4225
4226 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
4227 // condition code, create a new SELECT_CC node.
4228 if (CC.getNode()) {
4229 Tmp1 = DAG.getNode(Opcode: ISD::SELECT_CC, DL: dl, VT: Node->getValueType(ResNo: 0),
4230 N1: Tmp1, N2: Tmp2, N3: Tmp3, N4: Tmp4, N5: CC);
4231 } else {
4232 Tmp2 = DAG.getConstant(Val: 0, DL: dl, VT: Tmp1.getValueType());
4233 CC = DAG.getCondCode(Cond: ISD::SETNE);
4234 Tmp1 = DAG.getNode(Opcode: ISD::SELECT_CC, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1,
4235 N2: Tmp2, N3: Tmp3, N4: Tmp4, N5: CC);
4236 }
4237 Tmp1->setFlags(Node->getFlags());
4238 }
4239 Results.push_back(Elt: Tmp1);
4240 break;
4241 }
4242 case ISD::BR_CC: {
4243 // TODO: need to add STRICT_BR_CC and STRICT_BR_CCS
4244 SDValue Chain;
4245 Tmp1 = Node->getOperand(Num: 0); // Chain
4246 Tmp2 = Node->getOperand(Num: 2); // LHS
4247 Tmp3 = Node->getOperand(Num: 3); // RHS
4248 Tmp4 = Node->getOperand(Num: 1); // CC
4249
4250 bool Legalized = TLI.LegalizeSetCCCondCode(
4251 DAG, VT: getSetCCResultType(VT: Tmp2.getValueType()), LHS&: Tmp2, RHS&: Tmp3, CC&: Tmp4,
4252 /*Mask*/ SDValue(), /*EVL*/ SDValue(), NeedInvert, dl, Chain);
4253 (void)Legalized;
4254 assert(Legalized && "Can't legalize BR_CC with legal condition!");
4255
4256 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
4257 // node.
4258 if (Tmp4.getNode()) {
4259 assert(!NeedInvert && "Don't know how to invert BR_CC!");
4260
4261 Tmp1 = DAG.getNode(Opcode: ISD::BR_CC, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1,
4262 N2: Tmp4, N3: Tmp2, N4: Tmp3, N5: Node->getOperand(Num: 4));
4263 } else {
4264 Tmp3 = DAG.getConstant(Val: 0, DL: dl, VT: Tmp2.getValueType());
4265 Tmp4 = DAG.getCondCode(Cond: NeedInvert ? ISD::SETEQ : ISD::SETNE);
4266 Tmp1 = DAG.getNode(Opcode: ISD::BR_CC, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1, N2: Tmp4,
4267 N3: Tmp2, N4: Tmp3, N5: Node->getOperand(Num: 4));
4268 }
4269 Results.push_back(Elt: Tmp1);
4270 break;
4271 }
4272 case ISD::BUILD_VECTOR:
4273 Results.push_back(Elt: ExpandBUILD_VECTOR(Node));
4274 break;
4275 case ISD::SPLAT_VECTOR:
4276 Results.push_back(Elt: ExpandSPLAT_VECTOR(Node));
4277 break;
4278 case ISD::SRA:
4279 case ISD::SRL:
4280 case ISD::SHL: {
4281 // Scalarize vector SRA/SRL/SHL.
4282 EVT VT = Node->getValueType(ResNo: 0);
4283 assert(VT.isVector() && "Unable to legalize non-vector shift");
4284 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
4285 unsigned NumElem = VT.getVectorNumElements();
4286
4287 SmallVector<SDValue, 8> Scalars;
4288 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
4289 SDValue Ex =
4290 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: VT.getScalarType(),
4291 N1: Node->getOperand(Num: 0), N2: DAG.getVectorIdxConstant(Val: Idx, DL: dl));
4292 SDValue Sh =
4293 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: dl, VT: VT.getScalarType(),
4294 N1: Node->getOperand(Num: 1), N2: DAG.getVectorIdxConstant(Val: Idx, DL: dl));
4295 Scalars.push_back(Elt: DAG.getNode(Opcode: Node->getOpcode(), DL: dl,
4296 VT: VT.getScalarType(), N1: Ex, N2: Sh));
4297 }
4298
4299 SDValue Result = DAG.getBuildVector(VT: Node->getValueType(ResNo: 0), DL: dl, Ops: Scalars);
4300 Results.push_back(Elt: Result);
4301 break;
4302 }
4303 case ISD::VECREDUCE_FADD:
4304 case ISD::VECREDUCE_FMUL:
4305 case ISD::VECREDUCE_ADD:
4306 case ISD::VECREDUCE_MUL:
4307 case ISD::VECREDUCE_AND:
4308 case ISD::VECREDUCE_OR:
4309 case ISD::VECREDUCE_XOR:
4310 case ISD::VECREDUCE_SMAX:
4311 case ISD::VECREDUCE_SMIN:
4312 case ISD::VECREDUCE_UMAX:
4313 case ISD::VECREDUCE_UMIN:
4314 case ISD::VECREDUCE_FMAX:
4315 case ISD::VECREDUCE_FMIN:
4316 case ISD::VECREDUCE_FMAXIMUM:
4317 case ISD::VECREDUCE_FMINIMUM:
4318 Results.push_back(Elt: TLI.expandVecReduce(Node, DAG));
4319 break;
4320 case ISD::VP_CTTZ_ELTS:
4321 case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
4322 Results.push_back(Elt: TLI.expandVPCTTZElements(N: Node, DAG));
4323 break;
4324 case ISD::CLEAR_CACHE:
4325 // The default expansion of llvm.clear_cache is simply a no-op for those
4326 // targets where it is not needed.
4327 Results.push_back(Elt: Node->getOperand(Num: 0));
4328 break;
4329 case ISD::GLOBAL_OFFSET_TABLE:
4330 case ISD::GlobalAddress:
4331 case ISD::GlobalTLSAddress:
4332 case ISD::ExternalSymbol:
4333 case ISD::ConstantPool:
4334 case ISD::JumpTable:
4335 case ISD::INTRINSIC_W_CHAIN:
4336 case ISD::INTRINSIC_WO_CHAIN:
4337 case ISD::INTRINSIC_VOID:
4338 // FIXME: Custom lowering for these operations shouldn't return null!
4339 // Return true so that we don't call ConvertNodeToLibcall which also won't
4340 // do anything.
4341 return true;
4342 }
4343
4344 if (!TLI.isStrictFPEnabled() && Results.empty() && Node->isStrictFPOpcode()) {
4345 // FIXME: We were asked to expand a strict floating-point operation,
4346 // but there is currently no expansion implemented that would preserve
4347 // the "strict" properties. For now, we just fall back to the non-strict
4348 // version if that is legal on the target. The actual mutation of the
4349 // operation will happen in SelectionDAGISel::DoInstructionSelection.
4350 switch (Node->getOpcode()) {
4351 default:
4352 if (TLI.getStrictFPOperationAction(Op: Node->getOpcode(),
4353 VT: Node->getValueType(ResNo: 0))
4354 == TargetLowering::Legal)
4355 return true;
4356 break;
4357 case ISD::STRICT_FSUB: {
4358 if (TLI.getStrictFPOperationAction(
4359 Op: ISD::STRICT_FSUB, VT: Node->getValueType(ResNo: 0)) == TargetLowering::Legal)
4360 return true;
4361 if (TLI.getStrictFPOperationAction(
4362 Op: ISD::STRICT_FADD, VT: Node->getValueType(ResNo: 0)) != TargetLowering::Legal)
4363 break;
4364
4365 EVT VT = Node->getValueType(ResNo: 0);
4366 const SDNodeFlags Flags = Node->getFlags();
4367 SDValue Neg = DAG.getNode(Opcode: ISD::FNEG, DL: dl, VT, Operand: Node->getOperand(Num: 2), Flags);
4368 SDValue Fadd = DAG.getNode(Opcode: ISD::STRICT_FADD, DL: dl, VTList: Node->getVTList(),
4369 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1), Neg},
4370 Flags);
4371
4372 Results.push_back(Elt: Fadd);
4373 Results.push_back(Elt: Fadd.getValue(R: 1));
4374 break;
4375 }
4376 case ISD::STRICT_SINT_TO_FP:
4377 case ISD::STRICT_UINT_TO_FP:
4378 case ISD::STRICT_LRINT:
4379 case ISD::STRICT_LLRINT:
4380 case ISD::STRICT_LROUND:
4381 case ISD::STRICT_LLROUND:
4382 // These are registered by the operand type instead of the value
4383 // type. Reflect that here.
4384 if (TLI.getStrictFPOperationAction(Op: Node->getOpcode(),
4385 VT: Node->getOperand(Num: 1).getValueType())
4386 == TargetLowering::Legal)
4387 return true;
4388 break;
4389 }
4390 }
4391
4392 // Replace the original node with the legalized result.
4393 if (Results.empty()) {
4394 LLVM_DEBUG(dbgs() << "Cannot expand node\n");
4395 return false;
4396 }
4397
4398 LLVM_DEBUG(dbgs() << "Successfully expanded node\n");
4399 ReplaceNode(Old: Node, New: Results.data());
4400 return true;
4401}
4402
4403void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
4404 LLVM_DEBUG(dbgs() << "Trying to convert node to libcall\n");
4405 SmallVector<SDValue, 8> Results;
4406 SDLoc dl(Node);
4407 // FIXME: Check flags on the node to see if we can use a finite call.
4408 unsigned Opc = Node->getOpcode();
4409 switch (Opc) {
4410 case ISD::ATOMIC_FENCE: {
4411 // If the target didn't lower this, lower it to '__sync_synchronize()' call
4412 // FIXME: handle "fence singlethread" more efficiently.
4413 TargetLowering::ArgListTy Args;
4414
4415 TargetLowering::CallLoweringInfo CLI(DAG);
4416 CLI.setDebugLoc(dl)
4417 .setChain(Node->getOperand(Num: 0))
4418 .setLibCallee(
4419 CC: CallingConv::C, ResultType: Type::getVoidTy(C&: *DAG.getContext()),
4420 Target: DAG.getExternalSymbol(Sym: "__sync_synchronize",
4421 VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
4422 ArgsList: std::move(Args));
4423
4424 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
4425
4426 Results.push_back(Elt: CallResult.second);
4427 break;
4428 }
4429 // By default, atomic intrinsics are marked Legal and lowered. Targets
4430 // which don't support them directly, however, may want libcalls, in which
4431 // case they mark them Expand, and we get here.
4432 case ISD::ATOMIC_SWAP:
4433 case ISD::ATOMIC_LOAD_ADD:
4434 case ISD::ATOMIC_LOAD_SUB:
4435 case ISD::ATOMIC_LOAD_AND:
4436 case ISD::ATOMIC_LOAD_CLR:
4437 case ISD::ATOMIC_LOAD_OR:
4438 case ISD::ATOMIC_LOAD_XOR:
4439 case ISD::ATOMIC_LOAD_NAND:
4440 case ISD::ATOMIC_LOAD_MIN:
4441 case ISD::ATOMIC_LOAD_MAX:
4442 case ISD::ATOMIC_LOAD_UMIN:
4443 case ISD::ATOMIC_LOAD_UMAX:
4444 case ISD::ATOMIC_CMP_SWAP: {
4445 MVT VT = cast<AtomicSDNode>(Val: Node)->getMemoryVT().getSimpleVT();
4446 AtomicOrdering Order = cast<AtomicSDNode>(Val: Node)->getMergedOrdering();
4447 RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, Order, VT);
4448 EVT RetVT = Node->getValueType(ResNo: 0);
4449 TargetLowering::MakeLibCallOptions CallOptions;
4450 SmallVector<SDValue, 4> Ops;
4451 if (TLI.getLibcallName(Call: LC)) {
4452 // If outline atomic available, prepare its arguments and expand.
4453 Ops.append(in_start: Node->op_begin() + 2, in_end: Node->op_end());
4454 Ops.push_back(Elt: Node->getOperand(Num: 1));
4455
4456 } else {
4457 LC = RTLIB::getSYNC(Opc, VT);
4458 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
4459 "Unexpected atomic op or value type!");
4460 // Arguments for expansion to sync libcall
4461 Ops.append(in_start: Node->op_begin() + 1, in_end: Node->op_end());
4462 }
4463 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
4464 Ops, CallOptions,
4465 dl: SDLoc(Node),
4466 Chain: Node->getOperand(Num: 0));
4467 Results.push_back(Elt: Tmp.first);
4468 Results.push_back(Elt: Tmp.second);
4469 break;
4470 }
4471 case ISD::TRAP: {
4472 // If this operation is not supported, lower it to 'abort()' call
4473 TargetLowering::ArgListTy Args;
4474 TargetLowering::CallLoweringInfo CLI(DAG);
4475 CLI.setDebugLoc(dl)
4476 .setChain(Node->getOperand(Num: 0))
4477 .setLibCallee(CC: CallingConv::C, ResultType: Type::getVoidTy(C&: *DAG.getContext()),
4478 Target: DAG.getExternalSymbol(
4479 Sym: "abort", VT: TLI.getPointerTy(DL: DAG.getDataLayout())),
4480 ArgsList: std::move(Args));
4481 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
4482
4483 Results.push_back(Elt: CallResult.second);
4484 break;
4485 }
4486 case ISD::CLEAR_CACHE: {
4487 TargetLowering::MakeLibCallOptions CallOptions;
4488 SDValue InputChain = Node->getOperand(Num: 0);
4489 SDValue StartVal = Node->getOperand(Num: 1);
4490 SDValue EndVal = Node->getOperand(Num: 2);
4491 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
4492 DAG, LC: RTLIB::CLEAR_CACHE, RetVT: MVT::isVoid, Ops: {StartVal, EndVal}, CallOptions,
4493 dl: SDLoc(Node), Chain: InputChain);
4494 Results.push_back(Elt: Tmp.second);
4495 break;
4496 }
4497 case ISD::FMINNUM:
4498 case ISD::STRICT_FMINNUM:
4499 ExpandFPLibCall(Node, Call_F32: RTLIB::FMIN_F32, Call_F64: RTLIB::FMIN_F64,
4500 Call_F80: RTLIB::FMIN_F80, Call_F128: RTLIB::FMIN_F128,
4501 Call_PPCF128: RTLIB::FMIN_PPCF128, Results);
4502 break;
4503 // FIXME: We do not have libcalls for FMAXIMUM and FMINIMUM. So, we cannot use
4504 // libcall legalization for these nodes, but there is no default expasion for
4505 // these nodes either (see PR63267 for example).
4506 case ISD::FMAXNUM:
4507 case ISD::STRICT_FMAXNUM:
4508 ExpandFPLibCall(Node, Call_F32: RTLIB::FMAX_F32, Call_F64: RTLIB::FMAX_F64,
4509 Call_F80: RTLIB::FMAX_F80, Call_F128: RTLIB::FMAX_F128,
4510 Call_PPCF128: RTLIB::FMAX_PPCF128, Results);
4511 break;
4512 case ISD::FSQRT:
4513 case ISD::STRICT_FSQRT:
4514 ExpandFPLibCall(Node, Call_F32: RTLIB::SQRT_F32, Call_F64: RTLIB::SQRT_F64,
4515 Call_F80: RTLIB::SQRT_F80, Call_F128: RTLIB::SQRT_F128,
4516 Call_PPCF128: RTLIB::SQRT_PPCF128, Results);
4517 break;
4518 case ISD::FCBRT:
4519 ExpandFPLibCall(Node, Call_F32: RTLIB::CBRT_F32, Call_F64: RTLIB::CBRT_F64,
4520 Call_F80: RTLIB::CBRT_F80, Call_F128: RTLIB::CBRT_F128,
4521 Call_PPCF128: RTLIB::CBRT_PPCF128, Results);
4522 break;
4523 case ISD::FSIN:
4524 case ISD::STRICT_FSIN:
4525 ExpandFPLibCall(Node, Call_F32: RTLIB::SIN_F32, Call_F64: RTLIB::SIN_F64,
4526 Call_F80: RTLIB::SIN_F80, Call_F128: RTLIB::SIN_F128,
4527 Call_PPCF128: RTLIB::SIN_PPCF128, Results);
4528 break;
4529 case ISD::FCOS:
4530 case ISD::STRICT_FCOS:
4531 ExpandFPLibCall(Node, Call_F32: RTLIB::COS_F32, Call_F64: RTLIB::COS_F64,
4532 Call_F80: RTLIB::COS_F80, Call_F128: RTLIB::COS_F128,
4533 Call_PPCF128: RTLIB::COS_PPCF128, Results);
4534 break;
4535 case ISD::FTAN:
4536 case ISD::STRICT_FTAN:
4537 ExpandFPLibCall(Node, Call_F32: RTLIB::TAN_F32, Call_F64: RTLIB::TAN_F64, Call_F80: RTLIB::TAN_F80,
4538 Call_F128: RTLIB::TAN_F128, Call_PPCF128: RTLIB::TAN_PPCF128, Results);
4539 break;
4540 case ISD::FASIN:
4541 case ISD::STRICT_FASIN:
4542 ExpandFPLibCall(Node, Call_F32: RTLIB::ASIN_F32, Call_F64: RTLIB::ASIN_F64, Call_F80: RTLIB::ASIN_F80,
4543 Call_F128: RTLIB::ASIN_F128, Call_PPCF128: RTLIB::ASIN_PPCF128, Results);
4544 break;
4545 case ISD::FACOS:
4546 case ISD::STRICT_FACOS:
4547 ExpandFPLibCall(Node, Call_F32: RTLIB::ACOS_F32, Call_F64: RTLIB::ACOS_F64, Call_F80: RTLIB::ACOS_F80,
4548 Call_F128: RTLIB::ACOS_F128, Call_PPCF128: RTLIB::ACOS_PPCF128, Results);
4549 break;
4550 case ISD::FATAN:
4551 case ISD::STRICT_FATAN:
4552 ExpandFPLibCall(Node, Call_F32: RTLIB::ATAN_F32, Call_F64: RTLIB::ATAN_F64, Call_F80: RTLIB::ATAN_F80,
4553 Call_F128: RTLIB::ATAN_F128, Call_PPCF128: RTLIB::ATAN_PPCF128, Results);
4554 break;
4555 case ISD::FSINH:
4556 case ISD::STRICT_FSINH:
4557 ExpandFPLibCall(Node, Call_F32: RTLIB::SINH_F32, Call_F64: RTLIB::SINH_F64, Call_F80: RTLIB::SINH_F80,
4558 Call_F128: RTLIB::SINH_F128, Call_PPCF128: RTLIB::SINH_PPCF128, Results);
4559 break;
4560 case ISD::FCOSH:
4561 case ISD::STRICT_FCOSH:
4562 ExpandFPLibCall(Node, Call_F32: RTLIB::COSH_F32, Call_F64: RTLIB::COSH_F64, Call_F80: RTLIB::COSH_F80,
4563 Call_F128: RTLIB::COSH_F128, Call_PPCF128: RTLIB::COSH_PPCF128, Results);
4564 break;
4565 case ISD::FTANH:
4566 case ISD::STRICT_FTANH:
4567 ExpandFPLibCall(Node, Call_F32: RTLIB::TANH_F32, Call_F64: RTLIB::TANH_F64, Call_F80: RTLIB::TANH_F80,
4568 Call_F128: RTLIB::TANH_F128, Call_PPCF128: RTLIB::TANH_PPCF128, Results);
4569 break;
4570 case ISD::FSINCOS:
4571 // Expand into sincos libcall.
4572 ExpandSinCosLibCall(Node, Results);
4573 break;
4574 case ISD::FLOG:
4575 case ISD::STRICT_FLOG:
4576 ExpandFPLibCall(Node, Call_F32: RTLIB::LOG_F32, Call_F64: RTLIB::LOG_F64, Call_F80: RTLIB::LOG_F80,
4577 Call_F128: RTLIB::LOG_F128, Call_PPCF128: RTLIB::LOG_PPCF128, Results);
4578 break;
4579 case ISD::FLOG2:
4580 case ISD::STRICT_FLOG2:
4581 ExpandFPLibCall(Node, Call_F32: RTLIB::LOG2_F32, Call_F64: RTLIB::LOG2_F64, Call_F80: RTLIB::LOG2_F80,
4582 Call_F128: RTLIB::LOG2_F128, Call_PPCF128: RTLIB::LOG2_PPCF128, Results);
4583 break;
4584 case ISD::FLOG10:
4585 case ISD::STRICT_FLOG10:
4586 ExpandFPLibCall(Node, Call_F32: RTLIB::LOG10_F32, Call_F64: RTLIB::LOG10_F64, Call_F80: RTLIB::LOG10_F80,
4587 Call_F128: RTLIB::LOG10_F128, Call_PPCF128: RTLIB::LOG10_PPCF128, Results);
4588 break;
4589 case ISD::FEXP:
4590 case ISD::STRICT_FEXP:
4591 ExpandFPLibCall(Node, Call_F32: RTLIB::EXP_F32, Call_F64: RTLIB::EXP_F64, Call_F80: RTLIB::EXP_F80,
4592 Call_F128: RTLIB::EXP_F128, Call_PPCF128: RTLIB::EXP_PPCF128, Results);
4593 break;
4594 case ISD::FEXP2:
4595 case ISD::STRICT_FEXP2:
4596 ExpandFPLibCall(Node, Call_F32: RTLIB::EXP2_F32, Call_F64: RTLIB::EXP2_F64, Call_F80: RTLIB::EXP2_F80,
4597 Call_F128: RTLIB::EXP2_F128, Call_PPCF128: RTLIB::EXP2_PPCF128, Results);
4598 break;
4599 case ISD::FEXP10:
4600 ExpandFPLibCall(Node, Call_F32: RTLIB::EXP10_F32, Call_F64: RTLIB::EXP10_F64, Call_F80: RTLIB::EXP10_F80,
4601 Call_F128: RTLIB::EXP10_F128, Call_PPCF128: RTLIB::EXP10_PPCF128, Results);
4602 break;
4603 case ISD::FTRUNC:
4604 case ISD::STRICT_FTRUNC:
4605 ExpandFPLibCall(Node, Call_F32: RTLIB::TRUNC_F32, Call_F64: RTLIB::TRUNC_F64,
4606 Call_F80: RTLIB::TRUNC_F80, Call_F128: RTLIB::TRUNC_F128,
4607 Call_PPCF128: RTLIB::TRUNC_PPCF128, Results);
4608 break;
4609 case ISD::FFLOOR:
4610 case ISD::STRICT_FFLOOR:
4611 ExpandFPLibCall(Node, Call_F32: RTLIB::FLOOR_F32, Call_F64: RTLIB::FLOOR_F64,
4612 Call_F80: RTLIB::FLOOR_F80, Call_F128: RTLIB::FLOOR_F128,
4613 Call_PPCF128: RTLIB::FLOOR_PPCF128, Results);
4614 break;
4615 case ISD::FCEIL:
4616 case ISD::STRICT_FCEIL:
4617 ExpandFPLibCall(Node, Call_F32: RTLIB::CEIL_F32, Call_F64: RTLIB::CEIL_F64,
4618 Call_F80: RTLIB::CEIL_F80, Call_F128: RTLIB::CEIL_F128,
4619 Call_PPCF128: RTLIB::CEIL_PPCF128, Results);
4620 break;
4621 case ISD::FRINT:
4622 case ISD::STRICT_FRINT:
4623 ExpandFPLibCall(Node, Call_F32: RTLIB::RINT_F32, Call_F64: RTLIB::RINT_F64,
4624 Call_F80: RTLIB::RINT_F80, Call_F128: RTLIB::RINT_F128,
4625 Call_PPCF128: RTLIB::RINT_PPCF128, Results);
4626 break;
4627 case ISD::FNEARBYINT:
4628 case ISD::STRICT_FNEARBYINT:
4629 ExpandFPLibCall(Node, Call_F32: RTLIB::NEARBYINT_F32,
4630 Call_F64: RTLIB::NEARBYINT_F64,
4631 Call_F80: RTLIB::NEARBYINT_F80,
4632 Call_F128: RTLIB::NEARBYINT_F128,
4633 Call_PPCF128: RTLIB::NEARBYINT_PPCF128, Results);
4634 break;
4635 case ISD::FROUND:
4636 case ISD::STRICT_FROUND:
4637 ExpandFPLibCall(Node, Call_F32: RTLIB::ROUND_F32,
4638 Call_F64: RTLIB::ROUND_F64,
4639 Call_F80: RTLIB::ROUND_F80,
4640 Call_F128: RTLIB::ROUND_F128,
4641 Call_PPCF128: RTLIB::ROUND_PPCF128, Results);
4642 break;
4643 case ISD::FROUNDEVEN:
4644 case ISD::STRICT_FROUNDEVEN:
4645 ExpandFPLibCall(Node, Call_F32: RTLIB::ROUNDEVEN_F32,
4646 Call_F64: RTLIB::ROUNDEVEN_F64,
4647 Call_F80: RTLIB::ROUNDEVEN_F80,
4648 Call_F128: RTLIB::ROUNDEVEN_F128,
4649 Call_PPCF128: RTLIB::ROUNDEVEN_PPCF128, Results);
4650 break;
4651 case ISD::FLDEXP:
4652 case ISD::STRICT_FLDEXP:
4653 ExpandFPLibCall(Node, Call_F32: RTLIB::LDEXP_F32, Call_F64: RTLIB::LDEXP_F64, Call_F80: RTLIB::LDEXP_F80,
4654 Call_F128: RTLIB::LDEXP_F128, Call_PPCF128: RTLIB::LDEXP_PPCF128, Results);
4655 break;
4656 case ISD::FFREXP: {
4657 ExpandFrexpLibCall(Node, Results);
4658 break;
4659 }
4660 case ISD::FPOWI:
4661 case ISD::STRICT_FPOWI: {
4662 RTLIB::Libcall LC = RTLIB::getPOWI(RetVT: Node->getSimpleValueType(ResNo: 0));
4663 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fpowi.");
4664 if (!TLI.getLibcallName(Call: LC)) {
4665 // Some targets don't have a powi libcall; use pow instead.
4666 if (Node->isStrictFPOpcode()) {
4667 SDValue Exponent =
4668 DAG.getNode(Opcode: ISD::STRICT_SINT_TO_FP, DL: SDLoc(Node),
4669 ResultTys: {Node->getValueType(ResNo: 0), Node->getValueType(ResNo: 1)},
4670 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 2)});
4671 SDValue FPOW =
4672 DAG.getNode(Opcode: ISD::STRICT_FPOW, DL: SDLoc(Node),
4673 ResultTys: {Node->getValueType(ResNo: 0), Node->getValueType(ResNo: 1)},
4674 Ops: {Exponent.getValue(R: 1), Node->getOperand(Num: 1), Exponent});
4675 Results.push_back(Elt: FPOW);
4676 Results.push_back(Elt: FPOW.getValue(R: 1));
4677 } else {
4678 SDValue Exponent =
4679 DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: SDLoc(Node), VT: Node->getValueType(ResNo: 0),
4680 Operand: Node->getOperand(Num: 1));
4681 Results.push_back(Elt: DAG.getNode(Opcode: ISD::FPOW, DL: SDLoc(Node),
4682 VT: Node->getValueType(ResNo: 0),
4683 N1: Node->getOperand(Num: 0), N2: Exponent));
4684 }
4685 break;
4686 }
4687 unsigned Offset = Node->isStrictFPOpcode() ? 1 : 0;
4688 bool ExponentHasSizeOfInt =
4689 DAG.getLibInfo().getIntSize() ==
4690 Node->getOperand(Num: 1 + Offset).getValueType().getSizeInBits();
4691 if (!ExponentHasSizeOfInt) {
4692 // If the exponent does not match with sizeof(int) a libcall to
4693 // RTLIB::POWI would use the wrong type for the argument.
4694 DAG.getContext()->emitError(ErrorStr: "POWI exponent does not match sizeof(int)");
4695 Results.push_back(Elt: DAG.getUNDEF(VT: Node->getValueType(ResNo: 0)));
4696 break;
4697 }
4698 ExpandFPLibCall(Node, LC, Results);
4699 break;
4700 }
4701 case ISD::FPOW:
4702 case ISD::STRICT_FPOW:
4703 ExpandFPLibCall(Node, Call_F32: RTLIB::POW_F32, Call_F64: RTLIB::POW_F64, Call_F80: RTLIB::POW_F80,
4704 Call_F128: RTLIB::POW_F128, Call_PPCF128: RTLIB::POW_PPCF128, Results);
4705 break;
4706 case ISD::LROUND:
4707 case ISD::STRICT_LROUND:
4708 ExpandArgFPLibCall(Node, Call_F32: RTLIB::LROUND_F32,
4709 Call_F64: RTLIB::LROUND_F64, Call_F80: RTLIB::LROUND_F80,
4710 Call_F128: RTLIB::LROUND_F128,
4711 Call_PPCF128: RTLIB::LROUND_PPCF128, Results);
4712 break;
4713 case ISD::LLROUND:
4714 case ISD::STRICT_LLROUND:
4715 ExpandArgFPLibCall(Node, Call_F32: RTLIB::LLROUND_F32,
4716 Call_F64: RTLIB::LLROUND_F64, Call_F80: RTLIB::LLROUND_F80,
4717 Call_F128: RTLIB::LLROUND_F128,
4718 Call_PPCF128: RTLIB::LLROUND_PPCF128, Results);
4719 break;
4720 case ISD::LRINT:
4721 case ISD::STRICT_LRINT:
4722 ExpandArgFPLibCall(Node, Call_F32: RTLIB::LRINT_F32,
4723 Call_F64: RTLIB::LRINT_F64, Call_F80: RTLIB::LRINT_F80,
4724 Call_F128: RTLIB::LRINT_F128,
4725 Call_PPCF128: RTLIB::LRINT_PPCF128, Results);
4726 break;
4727 case ISD::LLRINT:
4728 case ISD::STRICT_LLRINT:
4729 ExpandArgFPLibCall(Node, Call_F32: RTLIB::LLRINT_F32,
4730 Call_F64: RTLIB::LLRINT_F64, Call_F80: RTLIB::LLRINT_F80,
4731 Call_F128: RTLIB::LLRINT_F128,
4732 Call_PPCF128: RTLIB::LLRINT_PPCF128, Results);
4733 break;
4734 case ISD::FDIV:
4735 case ISD::STRICT_FDIV:
4736 ExpandFPLibCall(Node, Call_F32: RTLIB::DIV_F32, Call_F64: RTLIB::DIV_F64,
4737 Call_F80: RTLIB::DIV_F80, Call_F128: RTLIB::DIV_F128,
4738 Call_PPCF128: RTLIB::DIV_PPCF128, Results);
4739 break;
4740 case ISD::FREM:
4741 case ISD::STRICT_FREM:
4742 ExpandFPLibCall(Node, Call_F32: RTLIB::REM_F32, Call_F64: RTLIB::REM_F64,
4743 Call_F80: RTLIB::REM_F80, Call_F128: RTLIB::REM_F128,
4744 Call_PPCF128: RTLIB::REM_PPCF128, Results);
4745 break;
4746 case ISD::FMA:
4747 case ISD::STRICT_FMA:
4748 ExpandFPLibCall(Node, Call_F32: RTLIB::FMA_F32, Call_F64: RTLIB::FMA_F64,
4749 Call_F80: RTLIB::FMA_F80, Call_F128: RTLIB::FMA_F128,
4750 Call_PPCF128: RTLIB::FMA_PPCF128, Results);
4751 break;
4752 case ISD::FADD:
4753 case ISD::STRICT_FADD:
4754 ExpandFPLibCall(Node, Call_F32: RTLIB::ADD_F32, Call_F64: RTLIB::ADD_F64,
4755 Call_F80: RTLIB::ADD_F80, Call_F128: RTLIB::ADD_F128,
4756 Call_PPCF128: RTLIB::ADD_PPCF128, Results);
4757 break;
4758 case ISD::FMUL:
4759 case ISD::STRICT_FMUL:
4760 ExpandFPLibCall(Node, Call_F32: RTLIB::MUL_F32, Call_F64: RTLIB::MUL_F64,
4761 Call_F80: RTLIB::MUL_F80, Call_F128: RTLIB::MUL_F128,
4762 Call_PPCF128: RTLIB::MUL_PPCF128, Results);
4763 break;
4764 case ISD::FP16_TO_FP:
4765 if (Node->getValueType(ResNo: 0) == MVT::f32) {
4766 Results.push_back(Elt: ExpandLibCall(LC: RTLIB::FPEXT_F16_F32, Node, isSigned: false).first);
4767 }
4768 break;
4769 case ISD::STRICT_BF16_TO_FP:
4770 if (Node->getValueType(ResNo: 0) == MVT::f32) {
4771 TargetLowering::MakeLibCallOptions CallOptions;
4772 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
4773 DAG, LC: RTLIB::FPEXT_BF16_F32, RetVT: MVT::f32, Ops: Node->getOperand(Num: 1),
4774 CallOptions, dl: SDLoc(Node), Chain: Node->getOperand(Num: 0));
4775 Results.push_back(Elt: Tmp.first);
4776 Results.push_back(Elt: Tmp.second);
4777 }
4778 break;
4779 case ISD::STRICT_FP16_TO_FP: {
4780 if (Node->getValueType(ResNo: 0) == MVT::f32) {
4781 TargetLowering::MakeLibCallOptions CallOptions;
4782 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
4783 DAG, LC: RTLIB::FPEXT_F16_F32, RetVT: MVT::f32, Ops: Node->getOperand(Num: 1), CallOptions,
4784 dl: SDLoc(Node), Chain: Node->getOperand(Num: 0));
4785 Results.push_back(Elt: Tmp.first);
4786 Results.push_back(Elt: Tmp.second);
4787 }
4788 break;
4789 }
4790 case ISD::FP_TO_FP16: {
4791 RTLIB::Libcall LC =
4792 RTLIB::getFPROUND(OpVT: Node->getOperand(Num: 0).getValueType(), RetVT: MVT::f16);
4793 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
4794 Results.push_back(Elt: ExpandLibCall(LC, Node, isSigned: false).first);
4795 break;
4796 }
4797 case ISD::FP_TO_BF16: {
4798 RTLIB::Libcall LC =
4799 RTLIB::getFPROUND(OpVT: Node->getOperand(Num: 0).getValueType(), RetVT: MVT::bf16);
4800 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_bf16");
4801 Results.push_back(Elt: ExpandLibCall(LC, Node, isSigned: false).first);
4802 break;
4803 }
4804 case ISD::STRICT_SINT_TO_FP:
4805 case ISD::STRICT_UINT_TO_FP:
4806 case ISD::SINT_TO_FP:
4807 case ISD::UINT_TO_FP: {
4808 // TODO - Common the code with DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP
4809 bool IsStrict = Node->isStrictFPOpcode();
4810 bool Signed = Node->getOpcode() == ISD::SINT_TO_FP ||
4811 Node->getOpcode() == ISD::STRICT_SINT_TO_FP;
4812 EVT SVT = Node->getOperand(Num: IsStrict ? 1 : 0).getValueType();
4813 EVT RVT = Node->getValueType(ResNo: 0);
4814 EVT NVT = EVT();
4815 SDLoc dl(Node);
4816
4817 // Even if the input is legal, no libcall may exactly match, eg. we don't
4818 // have i1 -> fp conversions. So, it needs to be promoted to a larger type,
4819 // eg: i13 -> fp. Then, look for an appropriate libcall.
4820 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4821 for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
4822 t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL;
4823 ++t) {
4824 NVT = (MVT::SimpleValueType)t;
4825 // The source needs to big enough to hold the operand.
4826 if (NVT.bitsGE(VT: SVT))
4827 LC = Signed ? RTLIB::getSINTTOFP(OpVT: NVT, RetVT: RVT)
4828 : RTLIB::getUINTTOFP(OpVT: NVT, RetVT: RVT);
4829 }
4830 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to legalize as libcall");
4831
4832 SDValue Chain = IsStrict ? Node->getOperand(Num: 0) : SDValue();
4833 // Sign/zero extend the argument if the libcall takes a larger type.
4834 SDValue Op = DAG.getNode(Opcode: Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL: dl,
4835 VT: NVT, Operand: Node->getOperand(Num: IsStrict ? 1 : 0));
4836 TargetLowering::MakeLibCallOptions CallOptions;
4837 CallOptions.setSExt(Signed);
4838 std::pair<SDValue, SDValue> Tmp =
4839 TLI.makeLibCall(DAG, LC, RetVT: RVT, Ops: Op, CallOptions, dl, Chain);
4840 Results.push_back(Elt: Tmp.first);
4841 if (IsStrict)
4842 Results.push_back(Elt: Tmp.second);
4843 break;
4844 }
4845 case ISD::FP_TO_SINT:
4846 case ISD::FP_TO_UINT:
4847 case ISD::STRICT_FP_TO_SINT:
4848 case ISD::STRICT_FP_TO_UINT: {
4849 // TODO - Common the code with DAGTypeLegalizer::SoftenFloatOp_FP_TO_XINT.
4850 bool IsStrict = Node->isStrictFPOpcode();
4851 bool Signed = Node->getOpcode() == ISD::FP_TO_SINT ||
4852 Node->getOpcode() == ISD::STRICT_FP_TO_SINT;
4853
4854 SDValue Op = Node->getOperand(Num: IsStrict ? 1 : 0);
4855 EVT SVT = Op.getValueType();
4856 EVT RVT = Node->getValueType(ResNo: 0);
4857 EVT NVT = EVT();
4858 SDLoc dl(Node);
4859
4860 // Even if the result is legal, no libcall may exactly match, eg. we don't
4861 // have fp -> i1 conversions. So, it needs to be promoted to a larger type,
4862 // eg: fp -> i32. Then, look for an appropriate libcall.
4863 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4864 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE;
4865 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL;
4866 ++IntVT) {
4867 NVT = (MVT::SimpleValueType)IntVT;
4868 // The type needs to big enough to hold the result.
4869 if (NVT.bitsGE(VT: RVT))
4870 LC = Signed ? RTLIB::getFPTOSINT(OpVT: SVT, RetVT: NVT)
4871 : RTLIB::getFPTOUINT(OpVT: SVT, RetVT: NVT);
4872 }
4873 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to legalize as libcall");
4874
4875 SDValue Chain = IsStrict ? Node->getOperand(Num: 0) : SDValue();
4876 TargetLowering::MakeLibCallOptions CallOptions;
4877 std::pair<SDValue, SDValue> Tmp =
4878 TLI.makeLibCall(DAG, LC, RetVT: NVT, Ops: Op, CallOptions, dl, Chain);
4879
4880 // Truncate the result if the libcall returns a larger type.
4881 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: RVT, Operand: Tmp.first));
4882 if (IsStrict)
4883 Results.push_back(Elt: Tmp.second);
4884 break;
4885 }
4886
4887 case ISD::FP_ROUND:
4888 case ISD::STRICT_FP_ROUND: {
4889 // X = FP_ROUND(Y, TRUNC)
4890 // TRUNC is a flag, which is always an integer that is zero or one.
4891 // If TRUNC is 0, this is a normal rounding, if it is 1, this FP_ROUND
4892 // is known to not change the value of Y.
4893 // We can only expand it into libcall if the TRUNC is 0.
4894 bool IsStrict = Node->isStrictFPOpcode();
4895 SDValue Op = Node->getOperand(Num: IsStrict ? 1 : 0);
4896 SDValue Chain = IsStrict ? Node->getOperand(Num: 0) : SDValue();
4897 EVT VT = Node->getValueType(ResNo: 0);
4898 assert(cast<ConstantSDNode>(Node->getOperand(IsStrict ? 2 : 1))->isZero() &&
4899 "Unable to expand as libcall if it is not normal rounding");
4900
4901 RTLIB::Libcall LC = RTLIB::getFPROUND(OpVT: Op.getValueType(), RetVT: VT);
4902 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to legalize as libcall");
4903
4904 TargetLowering::MakeLibCallOptions CallOptions;
4905 std::pair<SDValue, SDValue> Tmp =
4906 TLI.makeLibCall(DAG, LC, RetVT: VT, Ops: Op, CallOptions, dl: SDLoc(Node), Chain);
4907 Results.push_back(Elt: Tmp.first);
4908 if (IsStrict)
4909 Results.push_back(Elt: Tmp.second);
4910 break;
4911 }
4912 case ISD::FP_EXTEND: {
4913 Results.push_back(
4914 Elt: ExpandLibCall(LC: RTLIB::getFPEXT(OpVT: Node->getOperand(Num: 0).getValueType(),
4915 RetVT: Node->getValueType(ResNo: 0)),
4916 Node, isSigned: false).first);
4917 break;
4918 }
4919 case ISD::STRICT_FP_EXTEND:
4920 case ISD::STRICT_FP_TO_FP16:
4921 case ISD::STRICT_FP_TO_BF16: {
4922 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4923 if (Node->getOpcode() == ISD::STRICT_FP_TO_FP16)
4924 LC = RTLIB::getFPROUND(OpVT: Node->getOperand(Num: 1).getValueType(), RetVT: MVT::f16);
4925 else if (Node->getOpcode() == ISD::STRICT_FP_TO_BF16)
4926 LC = RTLIB::getFPROUND(OpVT: Node->getOperand(Num: 1).getValueType(), RetVT: MVT::bf16);
4927 else
4928 LC = RTLIB::getFPEXT(OpVT: Node->getOperand(Num: 1).getValueType(),
4929 RetVT: Node->getValueType(ResNo: 0));
4930
4931 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to legalize as libcall");
4932
4933 TargetLowering::MakeLibCallOptions CallOptions;
4934 std::pair<SDValue, SDValue> Tmp =
4935 TLI.makeLibCall(DAG, LC, RetVT: Node->getValueType(ResNo: 0), Ops: Node->getOperand(Num: 1),
4936 CallOptions, dl: SDLoc(Node), Chain: Node->getOperand(Num: 0));
4937 Results.push_back(Elt: Tmp.first);
4938 Results.push_back(Elt: Tmp.second);
4939 break;
4940 }
4941 case ISD::FSUB:
4942 case ISD::STRICT_FSUB:
4943 ExpandFPLibCall(Node, Call_F32: RTLIB::SUB_F32, Call_F64: RTLIB::SUB_F64,
4944 Call_F80: RTLIB::SUB_F80, Call_F128: RTLIB::SUB_F128,
4945 Call_PPCF128: RTLIB::SUB_PPCF128, Results);
4946 break;
4947 case ISD::SREM:
4948 Results.push_back(Elt: ExpandIntLibCall(Node, isSigned: true,
4949 Call_I8: RTLIB::SREM_I8,
4950 Call_I16: RTLIB::SREM_I16, Call_I32: RTLIB::SREM_I32,
4951 Call_I64: RTLIB::SREM_I64, Call_I128: RTLIB::SREM_I128));
4952 break;
4953 case ISD::UREM:
4954 Results.push_back(Elt: ExpandIntLibCall(Node, isSigned: false,
4955 Call_I8: RTLIB::UREM_I8,
4956 Call_I16: RTLIB::UREM_I16, Call_I32: RTLIB::UREM_I32,
4957 Call_I64: RTLIB::UREM_I64, Call_I128: RTLIB::UREM_I128));
4958 break;
4959 case ISD::SDIV:
4960 Results.push_back(Elt: ExpandIntLibCall(Node, isSigned: true,
4961 Call_I8: RTLIB::SDIV_I8,
4962 Call_I16: RTLIB::SDIV_I16, Call_I32: RTLIB::SDIV_I32,
4963 Call_I64: RTLIB::SDIV_I64, Call_I128: RTLIB::SDIV_I128));
4964 break;
4965 case ISD::UDIV:
4966 Results.push_back(Elt: ExpandIntLibCall(Node, isSigned: false,
4967 Call_I8: RTLIB::UDIV_I8,
4968 Call_I16: RTLIB::UDIV_I16, Call_I32: RTLIB::UDIV_I32,
4969 Call_I64: RTLIB::UDIV_I64, Call_I128: RTLIB::UDIV_I128));
4970 break;
4971 case ISD::SDIVREM:
4972 case ISD::UDIVREM:
4973 // Expand into divrem libcall
4974 ExpandDivRemLibCall(Node, Results);
4975 break;
4976 case ISD::MUL:
4977 Results.push_back(Elt: ExpandIntLibCall(Node, isSigned: false,
4978 Call_I8: RTLIB::MUL_I8,
4979 Call_I16: RTLIB::MUL_I16, Call_I32: RTLIB::MUL_I32,
4980 Call_I64: RTLIB::MUL_I64, Call_I128: RTLIB::MUL_I128));
4981 break;
4982 case ISD::CTLZ_ZERO_UNDEF:
4983 switch (Node->getSimpleValueType(ResNo: 0).SimpleTy) {
4984 default:
4985 llvm_unreachable("LibCall explicitly requested, but not available");
4986 case MVT::i32:
4987 Results.push_back(Elt: ExpandLibCall(LC: RTLIB::CTLZ_I32, Node, isSigned: false).first);
4988 break;
4989 case MVT::i64:
4990 Results.push_back(Elt: ExpandLibCall(LC: RTLIB::CTLZ_I64, Node, isSigned: false).first);
4991 break;
4992 case MVT::i128:
4993 Results.push_back(Elt: ExpandLibCall(LC: RTLIB::CTLZ_I128, Node, isSigned: false).first);
4994 break;
4995 }
4996 break;
4997 case ISD::RESET_FPENV: {
4998 // It is legalized to call 'fesetenv(FE_DFL_ENV)'. On most targets
4999 // FE_DFL_ENV is defined as '((const fenv_t *) -1)' in glibc.
5000 SDValue Ptr = DAG.getIntPtrConstant(Val: -1LL, DL: dl);
5001 SDValue Chain = Node->getOperand(Num: 0);
5002 Results.push_back(
5003 Elt: DAG.makeStateFunctionCall(LibFunc: RTLIB::FESETENV, Ptr, InChain: Chain, DLoc: dl));
5004 break;
5005 }
5006 case ISD::GET_FPENV_MEM: {
5007 SDValue Chain = Node->getOperand(Num: 0);
5008 SDValue EnvPtr = Node->getOperand(Num: 1);
5009 Results.push_back(
5010 Elt: DAG.makeStateFunctionCall(LibFunc: RTLIB::FEGETENV, Ptr: EnvPtr, InChain: Chain, DLoc: dl));
5011 break;
5012 }
5013 case ISD::SET_FPENV_MEM: {
5014 SDValue Chain = Node->getOperand(Num: 0);
5015 SDValue EnvPtr = Node->getOperand(Num: 1);
5016 Results.push_back(
5017 Elt: DAG.makeStateFunctionCall(LibFunc: RTLIB::FESETENV, Ptr: EnvPtr, InChain: Chain, DLoc: dl));
5018 break;
5019 }
5020 case ISD::GET_FPMODE: {
5021 // Call fegetmode, which saves control modes into a stack slot. Then load
5022 // the value to return from the stack.
5023 EVT ModeVT = Node->getValueType(ResNo: 0);
5024 SDValue StackPtr = DAG.CreateStackTemporary(VT: ModeVT);
5025 int SPFI = cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex();
5026 SDValue Chain = DAG.makeStateFunctionCall(LibFunc: RTLIB::FEGETMODE, Ptr: StackPtr,
5027 InChain: Node->getOperand(Num: 0), DLoc: dl);
5028 SDValue LdInst = DAG.getLoad(
5029 VT: ModeVT, dl, Chain, Ptr: StackPtr,
5030 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI));
5031 Results.push_back(Elt: LdInst);
5032 Results.push_back(Elt: LdInst.getValue(R: 1));
5033 break;
5034 }
5035 case ISD::SET_FPMODE: {
5036 // Move control modes to stack slot and then call fesetmode with the pointer
5037 // to the slot as argument.
5038 SDValue Mode = Node->getOperand(Num: 1);
5039 EVT ModeVT = Mode.getValueType();
5040 SDValue StackPtr = DAG.CreateStackTemporary(VT: ModeVT);
5041 int SPFI = cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex();
5042 SDValue StInst = DAG.getStore(
5043 Chain: Node->getOperand(Num: 0), dl, Val: Mode, Ptr: StackPtr,
5044 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI));
5045 Results.push_back(
5046 Elt: DAG.makeStateFunctionCall(LibFunc: RTLIB::FESETMODE, Ptr: StackPtr, InChain: StInst, DLoc: dl));
5047 break;
5048 }
5049 case ISD::RESET_FPMODE: {
5050 // It is legalized to a call 'fesetmode(FE_DFL_MODE)'. On most targets
5051 // FE_DFL_MODE is defined as '((const femode_t *) -1)' in glibc. If not, the
5052 // target must provide custom lowering.
5053 const DataLayout &DL = DAG.getDataLayout();
5054 EVT PtrTy = TLI.getPointerTy(DL);
5055 SDValue Mode = DAG.getConstant(Val: -1LL, DL: dl, VT: PtrTy);
5056 Results.push_back(Elt: DAG.makeStateFunctionCall(LibFunc: RTLIB::FESETMODE, Ptr: Mode,
5057 InChain: Node->getOperand(Num: 0), DLoc: dl));
5058 break;
5059 }
5060 }
5061
5062 // Replace the original node with the legalized result.
5063 if (!Results.empty()) {
5064 LLVM_DEBUG(dbgs() << "Successfully converted node to libcall\n");
5065 ReplaceNode(Old: Node, New: Results.data());
5066 } else
5067 LLVM_DEBUG(dbgs() << "Could not convert node to libcall\n");
5068}
5069
5070// Determine the vector type to use in place of an original scalar element when
5071// promoting equally sized vectors.
5072static MVT getPromotedVectorElementType(const TargetLowering &TLI,
5073 MVT EltVT, MVT NewEltVT) {
5074 unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
5075 MVT MidVT = OldEltsPerNewElt == 1
5076 ? NewEltVT
5077 : MVT::getVectorVT(VT: NewEltVT, NumElements: OldEltsPerNewElt);
5078 assert(TLI.isTypeLegal(MidVT) && "unexpected");
5079 return MidVT;
5080}
5081
5082void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
5083 LLVM_DEBUG(dbgs() << "Trying to promote node\n");
5084 SmallVector<SDValue, 8> Results;
5085 MVT OVT = Node->getSimpleValueType(ResNo: 0);
5086 if (Node->getOpcode() == ISD::UINT_TO_FP ||
5087 Node->getOpcode() == ISD::SINT_TO_FP ||
5088 Node->getOpcode() == ISD::SETCC ||
5089 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
5090 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
5091 OVT = Node->getOperand(Num: 0).getSimpleValueType();
5092 }
5093 if (Node->getOpcode() == ISD::ATOMIC_STORE ||
5094 Node->getOpcode() == ISD::STRICT_UINT_TO_FP ||
5095 Node->getOpcode() == ISD::STRICT_SINT_TO_FP ||
5096 Node->getOpcode() == ISD::STRICT_FSETCC ||
5097 Node->getOpcode() == ISD::STRICT_FSETCCS ||
5098 Node->getOpcode() == ISD::VP_REDUCE_FADD ||
5099 Node->getOpcode() == ISD::VP_REDUCE_FMUL ||
5100 Node->getOpcode() == ISD::VP_REDUCE_FMAX ||
5101 Node->getOpcode() == ISD::VP_REDUCE_FMIN ||
5102 Node->getOpcode() == ISD::VP_REDUCE_FMAXIMUM ||
5103 Node->getOpcode() == ISD::VP_REDUCE_FMINIMUM ||
5104 Node->getOpcode() == ISD::VP_REDUCE_SEQ_FADD)
5105 OVT = Node->getOperand(Num: 1).getSimpleValueType();
5106 if (Node->getOpcode() == ISD::BR_CC ||
5107 Node->getOpcode() == ISD::SELECT_CC)
5108 OVT = Node->getOperand(Num: 2).getSimpleValueType();
5109 MVT NVT = TLI.getTypeToPromoteTo(Op: Node->getOpcode(), VT: OVT);
5110 SDLoc dl(Node);
5111 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
5112 switch (Node->getOpcode()) {
5113 case ISD::CTTZ:
5114 case ISD::CTTZ_ZERO_UNDEF:
5115 case ISD::CTLZ:
5116 case ISD::CTPOP: {
5117 // Zero extend the argument unless its cttz, then use any_extend.
5118 if (Node->getOpcode() == ISD::CTTZ ||
5119 Node->getOpcode() == ISD::CTTZ_ZERO_UNDEF)
5120 Tmp1 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5121 else
5122 Tmp1 = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5123
5124 unsigned NewOpc = Node->getOpcode();
5125 if (NewOpc == ISD::CTTZ) {
5126 // The count is the same in the promoted type except if the original
5127 // value was zero. This can be handled by setting the bit just off
5128 // the top of the original type.
5129 auto TopBit = APInt::getOneBitSet(numBits: NVT.getSizeInBits(),
5130 BitNo: OVT.getSizeInBits());
5131 Tmp1 = DAG.getNode(Opcode: ISD::OR, DL: dl, VT: NVT, N1: Tmp1,
5132 N2: DAG.getConstant(Val: TopBit, DL: dl, VT: NVT));
5133 NewOpc = ISD::CTTZ_ZERO_UNDEF;
5134 }
5135 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
5136 // already the correct result.
5137 Tmp1 = DAG.getNode(Opcode: NewOpc, DL: dl, VT: NVT, Operand: Tmp1);
5138 if (NewOpc == ISD::CTLZ) {
5139 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
5140 Tmp1 = DAG.getNode(Opcode: ISD::SUB, DL: dl, VT: NVT, N1: Tmp1,
5141 N2: DAG.getConstant(Val: NVT.getSizeInBits() -
5142 OVT.getSizeInBits(), DL: dl, VT: NVT));
5143 }
5144 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp1));
5145 break;
5146 }
5147 case ISD::CTLZ_ZERO_UNDEF: {
5148 // We know that the argument is unlikely to be zero, hence we can take a
5149 // different approach as compared to ISD::CTLZ
5150
5151 // Any Extend the argument
5152 auto AnyExtendedNode =
5153 DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5154
5155 // Tmp1 = Tmp1 << (sizeinbits(NVT) - sizeinbits(Old VT))
5156 auto ShiftConstant = DAG.getShiftAmountConstant(
5157 Val: NVT.getSizeInBits() - OVT.getSizeInBits(), VT: NVT, DL: dl);
5158 auto LeftShiftResult =
5159 DAG.getNode(Opcode: ISD::SHL, DL: dl, VT: NVT, N1: AnyExtendedNode, N2: ShiftConstant);
5160
5161 // Perform the larger operation
5162 auto CTLZResult = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, Operand: LeftShiftResult);
5163 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: CTLZResult));
5164 break;
5165 }
5166 case ISD::BITREVERSE:
5167 case ISD::BSWAP: {
5168 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
5169 Tmp1 = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5170 Tmp1 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, Operand: Tmp1);
5171 Tmp1 = DAG.getNode(
5172 Opcode: ISD::SRL, DL: dl, VT: NVT, N1: Tmp1,
5173 N2: DAG.getConstant(Val: DiffBits, DL: dl,
5174 VT: TLI.getShiftAmountTy(LHSTy: NVT, DL: DAG.getDataLayout())));
5175
5176 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp1));
5177 break;
5178 }
5179 case ISD::FP_TO_UINT:
5180 case ISD::STRICT_FP_TO_UINT:
5181 case ISD::FP_TO_SINT:
5182 case ISD::STRICT_FP_TO_SINT:
5183 PromoteLegalFP_TO_INT(N: Node, dl, Results);
5184 break;
5185 case ISD::FP_TO_UINT_SAT:
5186 case ISD::FP_TO_SINT_SAT:
5187 Results.push_back(Elt: PromoteLegalFP_TO_INT_SAT(Node, dl));
5188 break;
5189 case ISD::UINT_TO_FP:
5190 case ISD::STRICT_UINT_TO_FP:
5191 case ISD::SINT_TO_FP:
5192 case ISD::STRICT_SINT_TO_FP:
5193 PromoteLegalINT_TO_FP(N: Node, dl, Results);
5194 break;
5195 case ISD::VAARG: {
5196 SDValue Chain = Node->getOperand(Num: 0); // Get the chain.
5197 SDValue Ptr = Node->getOperand(Num: 1); // Get the pointer.
5198
5199 unsigned TruncOp;
5200 if (OVT.isVector()) {
5201 TruncOp = ISD::BITCAST;
5202 } else {
5203 assert(OVT.isInteger()
5204 && "VAARG promotion is supported only for vectors or integer types");
5205 TruncOp = ISD::TRUNCATE;
5206 }
5207
5208 // Perform the larger operation, then convert back
5209 Tmp1 = DAG.getVAArg(VT: NVT, dl, Chain, Ptr, SV: Node->getOperand(Num: 2),
5210 Align: Node->getConstantOperandVal(Num: 3));
5211 Chain = Tmp1.getValue(R: 1);
5212
5213 Tmp2 = DAG.getNode(Opcode: TruncOp, DL: dl, VT: OVT, Operand: Tmp1);
5214
5215 // Modified the chain result - switch anything that used the old chain to
5216 // use the new one.
5217 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node, 0), To: Tmp2);
5218 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Node, 1), To: Chain);
5219 if (UpdatedNodes) {
5220 UpdatedNodes->insert(X: Tmp2.getNode());
5221 UpdatedNodes->insert(X: Chain.getNode());
5222 }
5223 ReplacedNode(N: Node);
5224 break;
5225 }
5226 case ISD::MUL:
5227 case ISD::SDIV:
5228 case ISD::SREM:
5229 case ISD::UDIV:
5230 case ISD::UREM:
5231 case ISD::SMIN:
5232 case ISD::SMAX:
5233 case ISD::UMIN:
5234 case ISD::UMAX:
5235 case ISD::AND:
5236 case ISD::OR:
5237 case ISD::XOR: {
5238 unsigned ExtOp, TruncOp;
5239 if (OVT.isVector()) {
5240 ExtOp = ISD::BITCAST;
5241 TruncOp = ISD::BITCAST;
5242 } else {
5243 assert(OVT.isInteger() && "Cannot promote logic operation");
5244
5245 switch (Node->getOpcode()) {
5246 default:
5247 ExtOp = ISD::ANY_EXTEND;
5248 break;
5249 case ISD::SDIV:
5250 case ISD::SREM:
5251 case ISD::SMIN:
5252 case ISD::SMAX:
5253 ExtOp = ISD::SIGN_EXTEND;
5254 break;
5255 case ISD::UDIV:
5256 case ISD::UREM:
5257 ExtOp = ISD::ZERO_EXTEND;
5258 break;
5259 case ISD::UMIN:
5260 case ISD::UMAX:
5261 if (TLI.isSExtCheaperThanZExt(FromTy: OVT, ToTy: NVT))
5262 ExtOp = ISD::SIGN_EXTEND;
5263 else
5264 ExtOp = ISD::ZERO_EXTEND;
5265 break;
5266 }
5267 TruncOp = ISD::TRUNCATE;
5268 }
5269 // Promote each of the values to the new type.
5270 Tmp1 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5271 Tmp2 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5272 // Perform the larger operation, then convert back
5273 Tmp1 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2);
5274 Results.push_back(Elt: DAG.getNode(Opcode: TruncOp, DL: dl, VT: OVT, Operand: Tmp1));
5275 break;
5276 }
5277 case ISD::UMUL_LOHI:
5278 case ISD::SMUL_LOHI: {
5279 // Promote to a multiply in a wider integer type.
5280 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
5281 : ISD::SIGN_EXTEND;
5282 Tmp1 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5283 Tmp2 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5284 Tmp1 = DAG.getNode(Opcode: ISD::MUL, DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2);
5285
5286 auto &DL = DAG.getDataLayout();
5287 unsigned OriginalSize = OVT.getScalarSizeInBits();
5288 Tmp2 = DAG.getNode(
5289 Opcode: ISD::SRL, DL: dl, VT: NVT, N1: Tmp1,
5290 N2: DAG.getConstant(Val: OriginalSize, DL: dl, VT: TLI.getScalarShiftAmountTy(DL, NVT)));
5291 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp1));
5292 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp2));
5293 break;
5294 }
5295 case ISD::SELECT: {
5296 unsigned ExtOp, TruncOp;
5297 if (Node->getValueType(ResNo: 0).isVector() ||
5298 Node->getValueType(ResNo: 0).getSizeInBits() == NVT.getSizeInBits()) {
5299 ExtOp = ISD::BITCAST;
5300 TruncOp = ISD::BITCAST;
5301 } else if (Node->getValueType(ResNo: 0).isInteger()) {
5302 ExtOp = ISD::ANY_EXTEND;
5303 TruncOp = ISD::TRUNCATE;
5304 } else {
5305 ExtOp = ISD::FP_EXTEND;
5306 TruncOp = ISD::FP_ROUND;
5307 }
5308 Tmp1 = Node->getOperand(Num: 0);
5309 // Promote each of the values to the new type.
5310 Tmp2 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5311 Tmp3 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 2));
5312 // Perform the larger operation, then round down.
5313 Tmp1 = DAG.getSelect(DL: dl, VT: NVT, Cond: Tmp1, LHS: Tmp2, RHS: Tmp3);
5314 Tmp1->setFlags(Node->getFlags());
5315 if (TruncOp != ISD::FP_ROUND)
5316 Tmp1 = DAG.getNode(Opcode: TruncOp, DL: dl, VT: Node->getValueType(ResNo: 0), Operand: Tmp1);
5317 else
5318 Tmp1 = DAG.getNode(Opcode: TruncOp, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1,
5319 N2: DAG.getIntPtrConstant(Val: 0, DL: dl));
5320 Results.push_back(Elt: Tmp1);
5321 break;
5322 }
5323 case ISD::VECTOR_SHUFFLE: {
5324 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Val: Node)->getMask();
5325
5326 // Cast the two input vectors.
5327 Tmp1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5328 Tmp2 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5329
5330 // Convert the shuffle mask to the right # elements.
5331 Tmp1 = ShuffleWithNarrowerEltType(NVT, VT: OVT, dl, N1: Tmp1, N2: Tmp2, Mask);
5332 Tmp1 = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: OVT, Operand: Tmp1);
5333 Results.push_back(Elt: Tmp1);
5334 break;
5335 }
5336 case ISD::VECTOR_SPLICE: {
5337 Tmp1 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5338 Tmp2 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5339 Tmp3 = DAG.getNode(Opcode: ISD::VECTOR_SPLICE, DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2,
5340 N3: Node->getOperand(Num: 2));
5341 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp3));
5342 break;
5343 }
5344 case ISD::SELECT_CC: {
5345 SDValue Cond = Node->getOperand(Num: 4);
5346 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val&: Cond)->get();
5347 // Type of the comparison operands.
5348 MVT CVT = Node->getSimpleValueType(ResNo: 0);
5349 assert(CVT == OVT && "not handled");
5350
5351 unsigned ExtOp = ISD::FP_EXTEND;
5352 if (NVT.isInteger()) {
5353 ExtOp = isSignedIntSetCC(Code: CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5354 }
5355
5356 // Promote the comparison operands, if needed.
5357 if (TLI.isCondCodeLegal(CC: CCCode, VT: CVT)) {
5358 Tmp1 = Node->getOperand(Num: 0);
5359 Tmp2 = Node->getOperand(Num: 1);
5360 } else {
5361 Tmp1 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5362 Tmp2 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5363 }
5364 // Cast the true/false operands.
5365 Tmp3 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 2));
5366 Tmp4 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 3));
5367
5368 Tmp1 = DAG.getNode(Opcode: ISD::SELECT_CC, DL: dl, VT: NVT, Ops: {Tmp1, Tmp2, Tmp3, Tmp4, Cond},
5369 Flags: Node->getFlags());
5370
5371 // Cast the result back to the original type.
5372 if (ExtOp != ISD::FP_EXTEND)
5373 Tmp1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp1);
5374 else
5375 Tmp1 = DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT, N1: Tmp1,
5376 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true));
5377
5378 Results.push_back(Elt: Tmp1);
5379 break;
5380 }
5381 case ISD::SETCC:
5382 case ISD::STRICT_FSETCC:
5383 case ISD::STRICT_FSETCCS: {
5384 unsigned ExtOp = ISD::FP_EXTEND;
5385 if (NVT.isInteger()) {
5386 ISD::CondCode CCCode = cast<CondCodeSDNode>(Val: Node->getOperand(Num: 2))->get();
5387 if (isSignedIntSetCC(Code: CCCode) ||
5388 TLI.isSExtCheaperThanZExt(FromTy: Node->getOperand(Num: 0).getValueType(), ToTy: NVT))
5389 ExtOp = ISD::SIGN_EXTEND;
5390 else
5391 ExtOp = ISD::ZERO_EXTEND;
5392 }
5393 if (Node->isStrictFPOpcode()) {
5394 SDValue InChain = Node->getOperand(Num: 0);
5395 std::tie(args&: Tmp1, args: std::ignore) =
5396 DAG.getStrictFPExtendOrRound(Op: Node->getOperand(Num: 1), Chain: InChain, DL: dl, VT: NVT);
5397 std::tie(args&: Tmp2, args: std::ignore) =
5398 DAG.getStrictFPExtendOrRound(Op: Node->getOperand(Num: 2), Chain: InChain, DL: dl, VT: NVT);
5399 SmallVector<SDValue, 2> TmpChains = {Tmp1.getValue(R: 1), Tmp2.getValue(R: 1)};
5400 SDValue OutChain = DAG.getTokenFactor(DL: dl, Vals&: TmpChains);
5401 SDVTList VTs = DAG.getVTList(VT1: Node->getValueType(ResNo: 0), VT2: MVT::Other);
5402 Results.push_back(Elt: DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VTList: VTs,
5403 Ops: {OutChain, Tmp1, Tmp2, Node->getOperand(Num: 3)},
5404 Flags: Node->getFlags()));
5405 Results.push_back(Elt: Results.back().getValue(R: 1));
5406 break;
5407 }
5408 Tmp1 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5409 Tmp2 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5410 Results.push_back(Elt: DAG.getNode(Opcode: ISD::SETCC, DL: dl, VT: Node->getValueType(ResNo: 0), N1: Tmp1,
5411 N2: Tmp2, N3: Node->getOperand(Num: 2), Flags: Node->getFlags()));
5412 break;
5413 }
5414 case ISD::BR_CC: {
5415 unsigned ExtOp = ISD::FP_EXTEND;
5416 if (NVT.isInteger()) {
5417 ISD::CondCode CCCode =
5418 cast<CondCodeSDNode>(Val: Node->getOperand(Num: 1))->get();
5419 ExtOp = isSignedIntSetCC(Code: CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5420 }
5421 Tmp1 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 2));
5422 Tmp2 = DAG.getNode(Opcode: ExtOp, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 3));
5423 Results.push_back(Elt: DAG.getNode(Opcode: ISD::BR_CC, DL: dl, VT: Node->getValueType(ResNo: 0),
5424 N1: Node->getOperand(Num: 0), N2: Node->getOperand(Num: 1),
5425 N3: Tmp1, N4: Tmp2, N5: Node->getOperand(Num: 4)));
5426 break;
5427 }
5428 case ISD::FADD:
5429 case ISD::FSUB:
5430 case ISD::FMUL:
5431 case ISD::FDIV:
5432 case ISD::FREM:
5433 case ISD::FMINNUM:
5434 case ISD::FMAXNUM:
5435 case ISD::FMINIMUM:
5436 case ISD::FMAXIMUM:
5437 case ISD::FPOW:
5438 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5439 Tmp2 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5440 Tmp3 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2,
5441 Flags: Node->getFlags());
5442 Results.push_back(
5443 Elt: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT, N1: Tmp3,
5444 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)));
5445 break;
5446 case ISD::STRICT_FADD:
5447 case ISD::STRICT_FSUB:
5448 case ISD::STRICT_FMUL:
5449 case ISD::STRICT_FDIV:
5450 case ISD::STRICT_FMINNUM:
5451 case ISD::STRICT_FMAXNUM:
5452 case ISD::STRICT_FREM:
5453 case ISD::STRICT_FPOW:
5454 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5455 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1)});
5456 Tmp2 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5457 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 2)});
5458 Tmp3 = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Tmp1.getValue(R: 1),
5459 N2: Tmp2.getValue(R: 1));
5460 Tmp1 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other},
5461 Ops: {Tmp3, Tmp1, Tmp2});
5462 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_FP_ROUND, DL: dl, ResultTys: {OVT, MVT::Other},
5463 Ops: {Tmp1.getValue(R: 1), Tmp1, DAG.getIntPtrConstant(Val: 0, DL: dl)});
5464 Results.push_back(Elt: Tmp1);
5465 Results.push_back(Elt: Tmp1.getValue(R: 1));
5466 break;
5467 case ISD::FMA:
5468 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5469 Tmp2 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 1));
5470 Tmp3 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 2));
5471 Results.push_back(
5472 Elt: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT,
5473 N1: DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2, N3: Tmp3),
5474 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)));
5475 break;
5476 case ISD::STRICT_FMA:
5477 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5478 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1)});
5479 Tmp2 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5480 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 2)});
5481 Tmp3 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5482 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 3)});
5483 Tmp4 = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Tmp1.getValue(R: 1),
5484 N2: Tmp2.getValue(R: 1), N3: Tmp3.getValue(R: 1));
5485 Tmp4 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other},
5486 Ops: {Tmp4, Tmp1, Tmp2, Tmp3});
5487 Tmp4 = DAG.getNode(Opcode: ISD::STRICT_FP_ROUND, DL: dl, ResultTys: {OVT, MVT::Other},
5488 Ops: {Tmp4.getValue(R: 1), Tmp4, DAG.getIntPtrConstant(Val: 0, DL: dl)});
5489 Results.push_back(Elt: Tmp4);
5490 Results.push_back(Elt: Tmp4.getValue(R: 1));
5491 break;
5492 case ISD::FCOPYSIGN:
5493 case ISD::FLDEXP:
5494 case ISD::FPOWI: {
5495 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5496 Tmp2 = Node->getOperand(Num: 1);
5497 Tmp3 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, N1: Tmp1, N2: Tmp2);
5498
5499 // fcopysign doesn't change anything but the sign bit, so
5500 // (fp_round (fcopysign (fpext a), b))
5501 // is as precise as
5502 // (fp_round (fpext a))
5503 // which is a no-op. Mark it as a TRUNCating FP_ROUND.
5504 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
5505 Results.push_back(
5506 Elt: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT, N1: Tmp3,
5507 N2: DAG.getIntPtrConstant(Val: isTrunc, DL: dl, /*isTarget=*/true)));
5508 break;
5509 }
5510 case ISD::STRICT_FPOWI:
5511 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5512 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1)});
5513 Tmp2 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other},
5514 Ops: {Tmp1.getValue(R: 1), Tmp1, Node->getOperand(Num: 2)});
5515 Tmp3 = DAG.getNode(Opcode: ISD::STRICT_FP_ROUND, DL: dl, ResultTys: {OVT, MVT::Other},
5516 Ops: {Tmp2.getValue(R: 1), Tmp2, DAG.getIntPtrConstant(Val: 0, DL: dl)});
5517 Results.push_back(Elt: Tmp3);
5518 Results.push_back(Elt: Tmp3.getValue(R: 1));
5519 break;
5520 case ISD::FFREXP: {
5521 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5522 Tmp2 = DAG.getNode(Opcode: ISD::FFREXP, DL: dl, ResultTys: {NVT, Node->getValueType(ResNo: 1)}, Ops: Tmp1);
5523
5524 Results.push_back(
5525 Elt: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT, N1: Tmp2,
5526 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)));
5527
5528 Results.push_back(Elt: Tmp2.getValue(R: 1));
5529 break;
5530 }
5531 case ISD::FFLOOR:
5532 case ISD::FCEIL:
5533 case ISD::FRINT:
5534 case ISD::FNEARBYINT:
5535 case ISD::FROUND:
5536 case ISD::FROUNDEVEN:
5537 case ISD::FTRUNC:
5538 case ISD::FNEG:
5539 case ISD::FSQRT:
5540 case ISD::FSIN:
5541 case ISD::FCOS:
5542 case ISD::FTAN:
5543 case ISD::FASIN:
5544 case ISD::FACOS:
5545 case ISD::FATAN:
5546 case ISD::FSINH:
5547 case ISD::FCOSH:
5548 case ISD::FTANH:
5549 case ISD::FLOG:
5550 case ISD::FLOG2:
5551 case ISD::FLOG10:
5552 case ISD::FABS:
5553 case ISD::FEXP:
5554 case ISD::FEXP2:
5555 case ISD::FEXP10:
5556 case ISD::FCANONICALIZE:
5557 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NVT, Operand: Node->getOperand(Num: 0));
5558 Tmp2 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, Operand: Tmp1);
5559 Results.push_back(
5560 Elt: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT, N1: Tmp2,
5561 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)));
5562 break;
5563 case ISD::STRICT_FFLOOR:
5564 case ISD::STRICT_FCEIL:
5565 case ISD::STRICT_FRINT:
5566 case ISD::STRICT_FNEARBYINT:
5567 case ISD::STRICT_FROUND:
5568 case ISD::STRICT_FROUNDEVEN:
5569 case ISD::STRICT_FTRUNC:
5570 case ISD::STRICT_FSQRT:
5571 case ISD::STRICT_FSIN:
5572 case ISD::STRICT_FCOS:
5573 case ISD::STRICT_FTAN:
5574 case ISD::STRICT_FASIN:
5575 case ISD::STRICT_FACOS:
5576 case ISD::STRICT_FATAN:
5577 case ISD::STRICT_FSINH:
5578 case ISD::STRICT_FCOSH:
5579 case ISD::STRICT_FTANH:
5580 case ISD::STRICT_FLOG:
5581 case ISD::STRICT_FLOG2:
5582 case ISD::STRICT_FLOG10:
5583 case ISD::STRICT_FEXP:
5584 case ISD::STRICT_FEXP2:
5585 Tmp1 = DAG.getNode(Opcode: ISD::STRICT_FP_EXTEND, DL: dl, ResultTys: {NVT, MVT::Other},
5586 Ops: {Node->getOperand(Num: 0), Node->getOperand(Num: 1)});
5587 Tmp2 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, ResultTys: {NVT, MVT::Other},
5588 Ops: {Tmp1.getValue(R: 1), Tmp1});
5589 Tmp3 = DAG.getNode(Opcode: ISD::STRICT_FP_ROUND, DL: dl, ResultTys: {OVT, MVT::Other},
5590 Ops: {Tmp2.getValue(R: 1), Tmp2, DAG.getIntPtrConstant(Val: 0, DL: dl)});
5591 Results.push_back(Elt: Tmp3);
5592 Results.push_back(Elt: Tmp3.getValue(R: 1));
5593 break;
5594 case ISD::BUILD_VECTOR: {
5595 MVT EltVT = OVT.getVectorElementType();
5596 MVT NewEltVT = NVT.getVectorElementType();
5597
5598 // Handle bitcasts to a different vector type with the same total bit size
5599 //
5600 // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
5601 // =>
5602 // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
5603
5604 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
5605 "Invalid promote type for build_vector");
5606 assert(NewEltVT.bitsLE(EltVT) && "not handled");
5607
5608 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
5609
5610 SmallVector<SDValue, 8> NewOps;
5611 for (const SDValue &Op : Node->op_values())
5612 NewOps.push_back(Elt: DAG.getNode(Opcode: ISD::BITCAST, DL: SDLoc(Op), VT: MidVT, Operand: Op));
5613
5614 SDLoc SL(Node);
5615 SDValue Concat =
5616 DAG.getNode(Opcode: MidVT == NewEltVT ? ISD::BUILD_VECTOR : ISD::CONCAT_VECTORS,
5617 DL: SL, VT: NVT, Ops: NewOps);
5618 SDValue CvtVec = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: OVT, Operand: Concat);
5619 Results.push_back(Elt: CvtVec);
5620 break;
5621 }
5622 case ISD::EXTRACT_VECTOR_ELT: {
5623 MVT EltVT = OVT.getVectorElementType();
5624 MVT NewEltVT = NVT.getVectorElementType();
5625
5626 // Handle bitcasts to a different vector type with the same total bit size.
5627 //
5628 // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
5629 // =>
5630 // v4i32:castx = bitcast x:v2i64
5631 //
5632 // i64 = bitcast
5633 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
5634 // (i32 (extract_vector_elt castx, (2 * y + 1)))
5635 //
5636
5637 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
5638 "Invalid promote type for extract_vector_elt");
5639 assert(NewEltVT.bitsLT(EltVT) && "not handled");
5640
5641 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
5642 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
5643
5644 SDValue Idx = Node->getOperand(Num: 1);
5645 EVT IdxVT = Idx.getValueType();
5646 SDLoc SL(Node);
5647 SDValue Factor = DAG.getConstant(Val: NewEltsPerOldElt, DL: SL, VT: IdxVT);
5648 SDValue NewBaseIdx = DAG.getNode(Opcode: ISD::MUL, DL: SL, VT: IdxVT, N1: Idx, N2: Factor);
5649
5650 SDValue CastVec = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: NVT, Operand: Node->getOperand(Num: 0));
5651
5652 SmallVector<SDValue, 8> NewOps;
5653 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
5654 SDValue IdxOffset = DAG.getConstant(Val: I, DL: SL, VT: IdxVT);
5655 SDValue TmpIdx = DAG.getNode(Opcode: ISD::ADD, DL: SL, VT: IdxVT, N1: NewBaseIdx, N2: IdxOffset);
5656
5657 SDValue Elt = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: SL, VT: NewEltVT,
5658 N1: CastVec, N2: TmpIdx);
5659 NewOps.push_back(Elt);
5660 }
5661
5662 SDValue NewVec = DAG.getBuildVector(VT: MidVT, DL: SL, Ops: NewOps);
5663 Results.push_back(Elt: DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: EltVT, Operand: NewVec));
5664 break;
5665 }
5666 case ISD::INSERT_VECTOR_ELT: {
5667 MVT EltVT = OVT.getVectorElementType();
5668 MVT NewEltVT = NVT.getVectorElementType();
5669
5670 // Handle bitcasts to a different vector type with the same total bit size
5671 //
5672 // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
5673 // =>
5674 // v4i32:castx = bitcast x:v2i64
5675 // v2i32:casty = bitcast y:i64
5676 //
5677 // v2i64 = bitcast
5678 // (v4i32 insert_vector_elt
5679 // (v4i32 insert_vector_elt v4i32:castx,
5680 // (extract_vector_elt casty, 0), 2 * z),
5681 // (extract_vector_elt casty, 1), (2 * z + 1))
5682
5683 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
5684 "Invalid promote type for insert_vector_elt");
5685 assert(NewEltVT.bitsLT(EltVT) && "not handled");
5686
5687 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
5688 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
5689
5690 SDValue Val = Node->getOperand(Num: 1);
5691 SDValue Idx = Node->getOperand(Num: 2);
5692 EVT IdxVT = Idx.getValueType();
5693 SDLoc SL(Node);
5694
5695 SDValue Factor = DAG.getConstant(Val: NewEltsPerOldElt, DL: SDLoc(), VT: IdxVT);
5696 SDValue NewBaseIdx = DAG.getNode(Opcode: ISD::MUL, DL: SL, VT: IdxVT, N1: Idx, N2: Factor);
5697
5698 SDValue CastVec = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: NVT, Operand: Node->getOperand(Num: 0));
5699 SDValue CastVal = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: MidVT, Operand: Val);
5700
5701 SDValue NewVec = CastVec;
5702 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
5703 SDValue IdxOffset = DAG.getConstant(Val: I, DL: SL, VT: IdxVT);
5704 SDValue InEltIdx = DAG.getNode(Opcode: ISD::ADD, DL: SL, VT: IdxVT, N1: NewBaseIdx, N2: IdxOffset);
5705
5706 SDValue Elt = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: SL, VT: NewEltVT,
5707 N1: CastVal, N2: IdxOffset);
5708
5709 NewVec = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: SL, VT: NVT,
5710 N1: NewVec, N2: Elt, N3: InEltIdx);
5711 }
5712
5713 Results.push_back(Elt: DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: OVT, Operand: NewVec));
5714 break;
5715 }
5716 case ISD::SCALAR_TO_VECTOR: {
5717 MVT EltVT = OVT.getVectorElementType();
5718 MVT NewEltVT = NVT.getVectorElementType();
5719
5720 // Handle bitcasts to different vector type with the same total bit size.
5721 //
5722 // e.g. v2i64 = scalar_to_vector x:i64
5723 // =>
5724 // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
5725 //
5726
5727 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
5728 SDValue Val = Node->getOperand(Num: 0);
5729 SDLoc SL(Node);
5730
5731 SDValue CastVal = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: MidVT, Operand: Val);
5732 SDValue Undef = DAG.getUNDEF(VT: MidVT);
5733
5734 SmallVector<SDValue, 8> NewElts;
5735 NewElts.push_back(Elt: CastVal);
5736 for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
5737 NewElts.push_back(Elt: Undef);
5738
5739 SDValue Concat = DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL: SL, VT: NVT, Ops: NewElts);
5740 SDValue CvtVec = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: OVT, Operand: Concat);
5741 Results.push_back(Elt: CvtVec);
5742 break;
5743 }
5744 case ISD::ATOMIC_SWAP:
5745 case ISD::ATOMIC_STORE: {
5746 AtomicSDNode *AM = cast<AtomicSDNode>(Val: Node);
5747 SDLoc SL(Node);
5748 SDValue CastVal = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: NVT, Operand: AM->getVal());
5749 assert(NVT.getSizeInBits() == OVT.getSizeInBits() &&
5750 "unexpected promotion type");
5751 assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() &&
5752 "unexpected atomic_swap with illegal type");
5753
5754 SDValue Op0 = AM->getBasePtr();
5755 SDValue Op1 = CastVal;
5756
5757 // ATOMIC_STORE uses a swapped operand order from every other AtomicSDNode,
5758 // but really it should merge with ISD::STORE.
5759 if (AM->getOpcode() == ISD::ATOMIC_STORE)
5760 std::swap(a&: Op0, b&: Op1);
5761
5762 SDValue NewAtomic = DAG.getAtomic(Opcode: AM->getOpcode(), dl: SL, MemVT: NVT, Chain: AM->getChain(),
5763 Ptr: Op0, Val: Op1, MMO: AM->getMemOperand());
5764
5765 if (AM->getOpcode() != ISD::ATOMIC_STORE) {
5766 Results.push_back(Elt: DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: OVT, Operand: NewAtomic));
5767 Results.push_back(Elt: NewAtomic.getValue(R: 1));
5768 } else
5769 Results.push_back(Elt: NewAtomic);
5770 break;
5771 }
5772 case ISD::ATOMIC_LOAD: {
5773 AtomicSDNode *AM = cast<AtomicSDNode>(Val: Node);
5774 SDLoc SL(Node);
5775 assert(NVT.getSizeInBits() == OVT.getSizeInBits() &&
5776 "unexpected promotion type");
5777 assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() &&
5778 "unexpected atomic_load with illegal type");
5779
5780 SDValue NewAtomic =
5781 DAG.getAtomic(Opcode: ISD::ATOMIC_LOAD, dl: SL, MemVT: NVT, VTList: DAG.getVTList(VT1: NVT, VT2: MVT::Other),
5782 Ops: {AM->getChain(), AM->getBasePtr()}, MMO: AM->getMemOperand());
5783 Results.push_back(Elt: DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: OVT, Operand: NewAtomic));
5784 Results.push_back(Elt: NewAtomic.getValue(R: 1));
5785 break;
5786 }
5787 case ISD::SPLAT_VECTOR: {
5788 SDValue Scalar = Node->getOperand(Num: 0);
5789 MVT ScalarType = Scalar.getSimpleValueType();
5790 MVT NewScalarType = NVT.getVectorElementType();
5791 if (ScalarType.isInteger()) {
5792 Tmp1 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: NewScalarType, Operand: Scalar);
5793 Tmp2 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, Operand: Tmp1);
5794 Results.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: OVT, Operand: Tmp2));
5795 break;
5796 }
5797 Tmp1 = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: NewScalarType, Operand: Scalar);
5798 Tmp2 = DAG.getNode(Opcode: Node->getOpcode(), DL: dl, VT: NVT, Operand: Tmp1);
5799 Results.push_back(
5800 Elt: DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: OVT, N1: Tmp2,
5801 N2: DAG.getIntPtrConstant(Val: 0, DL: dl, /*isTarget=*/true)));
5802 break;
5803 }
5804 case ISD::VP_REDUCE_FADD:
5805 case ISD::VP_REDUCE_FMUL:
5806 case ISD::VP_REDUCE_FMAX:
5807 case ISD::VP_REDUCE_FMIN:
5808 case ISD::VP_REDUCE_FMAXIMUM:
5809 case ISD::VP_REDUCE_FMINIMUM:
5810 case ISD::VP_REDUCE_SEQ_FADD:
5811 Results.push_back(Elt: PromoteReduction(Node));
5812 break;
5813 }
5814
5815 // Replace the original node with the legalized result.
5816 if (!Results.empty()) {
5817 LLVM_DEBUG(dbgs() << "Successfully promoted node\n");
5818 ReplaceNode(Old: Node, New: Results.data());
5819 } else
5820 LLVM_DEBUG(dbgs() << "Could not promote node\n");
5821}
5822
5823/// This is the entry point for the file.
5824void SelectionDAG::Legalize() {
5825 AssignTopologicalOrder();
5826
5827 SmallPtrSet<SDNode *, 16> LegalizedNodes;
5828 // Use a delete listener to remove nodes which were deleted during
5829 // legalization from LegalizeNodes. This is needed to handle the situation
5830 // where a new node is allocated by the object pool to the same address of a
5831 // previously deleted node.
5832 DAGNodeDeletedListener DeleteListener(
5833 *this,
5834 [&LegalizedNodes](SDNode *N, SDNode *E) { LegalizedNodes.erase(Ptr: N); });
5835
5836 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
5837
5838 // Visit all the nodes. We start in topological order, so that we see
5839 // nodes with their original operands intact. Legalization can produce
5840 // new nodes which may themselves need to be legalized. Iterate until all
5841 // nodes have been legalized.
5842 while (true) {
5843 bool AnyLegalized = false;
5844 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
5845 --NI;
5846
5847 SDNode *N = &*NI;
5848 if (N->use_empty() && N != getRoot().getNode()) {
5849 ++NI;
5850 DeleteNode(N);
5851 continue;
5852 }
5853
5854 if (LegalizedNodes.insert(Ptr: N).second) {
5855 AnyLegalized = true;
5856 Legalizer.LegalizeOp(Node: N);
5857
5858 if (N->use_empty() && N != getRoot().getNode()) {
5859 ++NI;
5860 DeleteNode(N);
5861 }
5862 }
5863 }
5864 if (!AnyLegalized)
5865 break;
5866
5867 }
5868
5869 // Remove dead nodes now.
5870 RemoveDeadNodes();
5871}
5872
5873bool SelectionDAG::LegalizeOp(SDNode *N,
5874 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
5875 SmallPtrSet<SDNode *, 16> LegalizedNodes;
5876 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
5877
5878 // Directly insert the node in question, and legalize it. This will recurse
5879 // as needed through operands.
5880 LegalizedNodes.insert(Ptr: N);
5881 Legalizer.LegalizeOp(Node: N);
5882
5883 return LegalizedNodes.count(Ptr: N);
5884}
5885