1//===- TailDuplicator.cpp - Duplicate blocks into predecessors' tails -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This utility class duplicates basic blocks ending in unconditional branches
10// into the tails of their predecessors.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/TailDuplicator.h"
15#include "llvm/ADT/DenseMap.h"
16#include "llvm/ADT/DenseSet.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/ADT/SetVector.h"
19#include "llvm/ADT/SmallPtrSet.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/ADT/Statistic.h"
22#include "llvm/CodeGen/MachineBasicBlock.h"
23#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstr.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineOperand.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/MachineSSAUpdater.h"
30#include "llvm/CodeGen/MachineSizeOpts.h"
31#include "llvm/CodeGen/TargetInstrInfo.h"
32#include "llvm/CodeGen/TargetRegisterInfo.h"
33#include "llvm/CodeGen/TargetSubtargetInfo.h"
34#include "llvm/IR/DebugLoc.h"
35#include "llvm/IR/Function.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/Target/TargetMachine.h"
41#include <algorithm>
42#include <cassert>
43#include <iterator>
44#include <utility>
45
46using namespace llvm;
47
48#define DEBUG_TYPE "tailduplication"
49
50STATISTIC(NumTails, "Number of tails duplicated");
51STATISTIC(NumTailDups, "Number of tail duplicated blocks");
52STATISTIC(NumTailDupAdded,
53 "Number of instructions added due to tail duplication");
54STATISTIC(NumTailDupRemoved,
55 "Number of instructions removed due to tail duplication");
56STATISTIC(NumDeadBlocks, "Number of dead blocks removed");
57STATISTIC(NumAddedPHIs, "Number of phis added");
58
59// Heuristic for tail duplication.
60static cl::opt<unsigned> TailDuplicateSize(
61 "tail-dup-size",
62 cl::desc("Maximum instructions to consider tail duplicating"), cl::init(Val: 2),
63 cl::Hidden);
64
65static cl::opt<unsigned> TailDupIndirectBranchSize(
66 "tail-dup-indirect-size",
67 cl::desc("Maximum instructions to consider tail duplicating blocks that "
68 "end with indirect branches."), cl::init(Val: 20),
69 cl::Hidden);
70
71static cl::opt<unsigned>
72 TailDupPredSize("tail-dup-pred-size",
73 cl::desc("Maximum predecessors (maximum successors at the "
74 "same time) to consider tail duplicating blocks."),
75 cl::init(Val: 16), cl::Hidden);
76
77static cl::opt<unsigned>
78 TailDupSuccSize("tail-dup-succ-size",
79 cl::desc("Maximum successors (maximum predecessors at the "
80 "same time) to consider tail duplicating blocks."),
81 cl::init(Val: 16), cl::Hidden);
82
83static cl::opt<bool>
84 TailDupVerify("tail-dup-verify",
85 cl::desc("Verify sanity of PHI instructions during taildup"),
86 cl::init(Val: false), cl::Hidden);
87
88static cl::opt<unsigned> TailDupLimit("tail-dup-limit", cl::init(Val: ~0U),
89 cl::Hidden);
90
91void TailDuplicator::initMF(MachineFunction &MFin, bool PreRegAlloc,
92 const MachineBranchProbabilityInfo *MBPIin,
93 MBFIWrapper *MBFIin,
94 ProfileSummaryInfo *PSIin,
95 bool LayoutModeIn, unsigned TailDupSizeIn) {
96 MF = &MFin;
97 TII = MF->getSubtarget().getInstrInfo();
98 TRI = MF->getSubtarget().getRegisterInfo();
99 MRI = &MF->getRegInfo();
100 MBPI = MBPIin;
101 MBFI = MBFIin;
102 PSI = PSIin;
103 TailDupSize = TailDupSizeIn;
104
105 assert(MBPI != nullptr && "Machine Branch Probability Info required");
106
107 LayoutMode = LayoutModeIn;
108 this->PreRegAlloc = PreRegAlloc;
109}
110
111static void VerifyPHIs(MachineFunction &MF, bool CheckExtra) {
112 for (MachineBasicBlock &MBB : llvm::drop_begin(RangeOrContainer&: MF)) {
113 SmallSetVector<MachineBasicBlock *, 8> Preds(MBB.pred_begin(),
114 MBB.pred_end());
115 MachineBasicBlock::iterator MI = MBB.begin();
116 while (MI != MBB.end()) {
117 if (!MI->isPHI())
118 break;
119 for (MachineBasicBlock *PredBB : Preds) {
120 bool Found = false;
121 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
122 MachineBasicBlock *PHIBB = MI->getOperand(i: i + 1).getMBB();
123 if (PHIBB == PredBB) {
124 Found = true;
125 break;
126 }
127 }
128 if (!Found) {
129 dbgs() << "Malformed PHI in " << printMBBReference(MBB) << ": "
130 << *MI;
131 dbgs() << " missing input from predecessor "
132 << printMBBReference(MBB: *PredBB) << '\n';
133 llvm_unreachable(nullptr);
134 }
135 }
136
137 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
138 MachineBasicBlock *PHIBB = MI->getOperand(i: i + 1).getMBB();
139 if (CheckExtra && !Preds.count(key: PHIBB)) {
140 dbgs() << "Warning: malformed PHI in " << printMBBReference(MBB)
141 << ": " << *MI;
142 dbgs() << " extra input from predecessor "
143 << printMBBReference(MBB: *PHIBB) << '\n';
144 llvm_unreachable(nullptr);
145 }
146 if (PHIBB->getNumber() < 0) {
147 dbgs() << "Malformed PHI in " << printMBBReference(MBB) << ": "
148 << *MI;
149 dbgs() << " non-existing " << printMBBReference(MBB: *PHIBB) << '\n';
150 llvm_unreachable(nullptr);
151 }
152 }
153 ++MI;
154 }
155 }
156}
157
158/// Tail duplicate the block and cleanup.
159/// \p IsSimple - return value of isSimpleBB
160/// \p MBB - block to be duplicated
161/// \p ForcedLayoutPred - If non-null, treat this block as the layout
162/// predecessor, instead of using the ordering in MF
163/// \p DuplicatedPreds - if non-null, \p DuplicatedPreds will contain a list of
164/// all Preds that received a copy of \p MBB.
165/// \p RemovalCallback - if non-null, called just before MBB is deleted.
166bool TailDuplicator::tailDuplicateAndUpdate(
167 bool IsSimple, MachineBasicBlock *MBB,
168 MachineBasicBlock *ForcedLayoutPred,
169 SmallVectorImpl<MachineBasicBlock*> *DuplicatedPreds,
170 function_ref<void(MachineBasicBlock *)> *RemovalCallback,
171 SmallVectorImpl<MachineBasicBlock *> *CandidatePtr) {
172 // Save the successors list.
173 SmallSetVector<MachineBasicBlock *, 8> Succs(MBB->succ_begin(),
174 MBB->succ_end());
175
176 SmallVector<MachineBasicBlock *, 8> TDBBs;
177 SmallVector<MachineInstr *, 16> Copies;
178 if (!tailDuplicate(IsSimple, TailBB: MBB, ForcedLayoutPred,
179 TDBBs, Copies, CandidatePtr))
180 return false;
181
182 ++NumTails;
183
184 SmallVector<MachineInstr *, 8> NewPHIs;
185 MachineSSAUpdater SSAUpdate(*MF, &NewPHIs);
186
187 // TailBB's immediate successors are now successors of those predecessors
188 // which duplicated TailBB. Add the predecessors as sources to the PHI
189 // instructions.
190 bool isDead = MBB->pred_empty() && !MBB->hasAddressTaken();
191 if (PreRegAlloc)
192 updateSuccessorsPHIs(FromBB: MBB, isDead, TDBBs, Succs);
193
194 // If it is dead, remove it.
195 if (isDead) {
196 NumTailDupRemoved += MBB->size();
197 removeDeadBlock(MBB, RemovalCallback);
198 ++NumDeadBlocks;
199 }
200
201 // Update SSA form.
202 if (!SSAUpdateVRs.empty()) {
203 for (unsigned VReg : SSAUpdateVRs) {
204 SSAUpdate.Initialize(V: VReg);
205
206 // If the original definition is still around, add it as an available
207 // value.
208 MachineInstr *DefMI = MRI->getVRegDef(Reg: VReg);
209 MachineBasicBlock *DefBB = nullptr;
210 if (DefMI) {
211 DefBB = DefMI->getParent();
212 SSAUpdate.AddAvailableValue(BB: DefBB, V: VReg);
213 }
214
215 // Add the new vregs as available values.
216 DenseMap<Register, AvailableValsTy>::iterator LI =
217 SSAUpdateVals.find(Val: VReg);
218 for (std::pair<MachineBasicBlock *, Register> &J : LI->second) {
219 MachineBasicBlock *SrcBB = J.first;
220 Register SrcReg = J.second;
221 SSAUpdate.AddAvailableValue(BB: SrcBB, V: SrcReg);
222 }
223
224 SmallVector<MachineOperand *> DebugUses;
225 // Rewrite uses that are outside of the original def's block.
226 for (MachineOperand &UseMO :
227 llvm::make_early_inc_range(Range: MRI->use_operands(Reg: VReg))) {
228 MachineInstr *UseMI = UseMO.getParent();
229 // Rewrite debug uses last so that they can take advantage of any
230 // register mappings introduced by other users in its BB, since we
231 // cannot create new register definitions specifically for the debug
232 // instruction (as debug instructions should not affect CodeGen).
233 if (UseMI->isDebugValue()) {
234 DebugUses.push_back(Elt: &UseMO);
235 continue;
236 }
237 if (UseMI->getParent() == DefBB && !UseMI->isPHI())
238 continue;
239 SSAUpdate.RewriteUse(U&: UseMO);
240 }
241 for (auto *UseMO : DebugUses) {
242 MachineInstr *UseMI = UseMO->getParent();
243 UseMO->setReg(
244 SSAUpdate.GetValueInMiddleOfBlock(BB: UseMI->getParent(), ExistingValueOnly: true));
245 }
246 }
247
248 SSAUpdateVRs.clear();
249 SSAUpdateVals.clear();
250 }
251
252 // Eliminate some of the copies inserted by tail duplication to maintain
253 // SSA form.
254 for (MachineInstr *Copy : Copies) {
255 if (!Copy->isCopy())
256 continue;
257 Register Dst = Copy->getOperand(i: 0).getReg();
258 Register Src = Copy->getOperand(i: 1).getReg();
259 if (MRI->hasOneNonDBGUse(RegNo: Src) &&
260 MRI->constrainRegClass(Reg: Src, RC: MRI->getRegClass(Reg: Dst))) {
261 // Copy is the only use. Do trivial copy propagation here.
262 MRI->replaceRegWith(FromReg: Dst, ToReg: Src);
263 Copy->eraseFromParent();
264 }
265 }
266
267 if (NewPHIs.size())
268 NumAddedPHIs += NewPHIs.size();
269
270 if (DuplicatedPreds)
271 *DuplicatedPreds = std::move(TDBBs);
272
273 return true;
274}
275
276/// Look for small blocks that are unconditionally branched to and do not fall
277/// through. Tail-duplicate their instructions into their predecessors to
278/// eliminate (dynamic) branches.
279bool TailDuplicator::tailDuplicateBlocks() {
280 bool MadeChange = false;
281
282 if (PreRegAlloc && TailDupVerify) {
283 LLVM_DEBUG(dbgs() << "\n*** Before tail-duplicating\n");
284 VerifyPHIs(MF&: *MF, CheckExtra: true);
285 }
286
287 for (MachineBasicBlock &MBB :
288 llvm::make_early_inc_range(Range: llvm::drop_begin(RangeOrContainer&: *MF))) {
289 if (NumTails == TailDupLimit)
290 break;
291
292 bool IsSimple = isSimpleBB(TailBB: &MBB);
293
294 if (!shouldTailDuplicate(IsSimple, TailBB&: MBB))
295 continue;
296
297 MadeChange |= tailDuplicateAndUpdate(IsSimple, MBB: &MBB, ForcedLayoutPred: nullptr);
298 }
299
300 if (PreRegAlloc && TailDupVerify)
301 VerifyPHIs(MF&: *MF, CheckExtra: false);
302
303 return MadeChange;
304}
305
306static bool isDefLiveOut(Register Reg, MachineBasicBlock *BB,
307 const MachineRegisterInfo *MRI) {
308 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
309 if (UseMI.isDebugValue())
310 continue;
311 if (UseMI.getParent() != BB)
312 return true;
313 }
314 return false;
315}
316
317static unsigned getPHISrcRegOpIdx(MachineInstr *MI, MachineBasicBlock *SrcBB) {
318 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2)
319 if (MI->getOperand(i: i + 1).getMBB() == SrcBB)
320 return i;
321 return 0;
322}
323
324// Remember which registers are used by phis in this block. This is
325// used to determine which registers are liveout while modifying the
326// block (which is why we need to copy the information).
327static void getRegsUsedByPHIs(const MachineBasicBlock &BB,
328 DenseSet<Register> *UsedByPhi) {
329 for (const auto &MI : BB) {
330 if (!MI.isPHI())
331 break;
332 for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
333 Register SrcReg = MI.getOperand(i).getReg();
334 UsedByPhi->insert(V: SrcReg);
335 }
336 }
337}
338
339/// Add a definition and source virtual registers pair for SSA update.
340void TailDuplicator::addSSAUpdateEntry(Register OrigReg, Register NewReg,
341 MachineBasicBlock *BB) {
342 DenseMap<Register, AvailableValsTy>::iterator LI =
343 SSAUpdateVals.find(Val: OrigReg);
344 if (LI != SSAUpdateVals.end())
345 LI->second.push_back(x: std::make_pair(x&: BB, y&: NewReg));
346 else {
347 AvailableValsTy Vals;
348 Vals.push_back(x: std::make_pair(x&: BB, y&: NewReg));
349 SSAUpdateVals.insert(KV: std::make_pair(x&: OrigReg, y&: Vals));
350 SSAUpdateVRs.push_back(Elt: OrigReg);
351 }
352}
353
354/// Process PHI node in TailBB by turning it into a copy in PredBB. Remember the
355/// source register that's contributed by PredBB and update SSA update map.
356void TailDuplicator::processPHI(
357 MachineInstr *MI, MachineBasicBlock *TailBB, MachineBasicBlock *PredBB,
358 DenseMap<Register, RegSubRegPair> &LocalVRMap,
359 SmallVectorImpl<std::pair<Register, RegSubRegPair>> &Copies,
360 const DenseSet<Register> &RegsUsedByPhi, bool Remove) {
361 Register DefReg = MI->getOperand(i: 0).getReg();
362 unsigned SrcOpIdx = getPHISrcRegOpIdx(MI, SrcBB: PredBB);
363 assert(SrcOpIdx && "Unable to find matching PHI source?");
364 Register SrcReg = MI->getOperand(i: SrcOpIdx).getReg();
365 unsigned SrcSubReg = MI->getOperand(i: SrcOpIdx).getSubReg();
366 const TargetRegisterClass *RC = MRI->getRegClass(Reg: DefReg);
367 LocalVRMap.insert(KV: std::make_pair(x&: DefReg, y: RegSubRegPair(SrcReg, SrcSubReg)));
368
369 // Insert a copy from source to the end of the block. The def register is the
370 // available value liveout of the block.
371 Register NewDef = MRI->createVirtualRegister(RegClass: RC);
372 Copies.push_back(Elt: std::make_pair(x&: NewDef, y: RegSubRegPair(SrcReg, SrcSubReg)));
373 if (isDefLiveOut(Reg: DefReg, BB: TailBB, MRI) || RegsUsedByPhi.count(V: DefReg))
374 addSSAUpdateEntry(OrigReg: DefReg, NewReg: NewDef, BB: PredBB);
375
376 if (!Remove)
377 return;
378
379 // Remove PredBB from the PHI node.
380 MI->removeOperand(OpNo: SrcOpIdx + 1);
381 MI->removeOperand(OpNo: SrcOpIdx);
382 if (MI->getNumOperands() == 1 && !TailBB->hasAddressTaken())
383 MI->eraseFromParent();
384 else if (MI->getNumOperands() == 1)
385 MI->setDesc(TII->get(Opcode: TargetOpcode::IMPLICIT_DEF));
386}
387
388/// Duplicate a TailBB instruction to PredBB and update
389/// the source operands due to earlier PHI translation.
390void TailDuplicator::duplicateInstruction(
391 MachineInstr *MI, MachineBasicBlock *TailBB, MachineBasicBlock *PredBB,
392 DenseMap<Register, RegSubRegPair> &LocalVRMap,
393 const DenseSet<Register> &UsedByPhi) {
394 // Allow duplication of CFI instructions.
395 if (MI->isCFIInstruction()) {
396 BuildMI(BB&: *PredBB, I: PredBB->end(), MIMD: PredBB->findDebugLoc(MBBI: PredBB->begin()),
397 MCID: TII->get(Opcode: TargetOpcode::CFI_INSTRUCTION))
398 .addCFIIndex(CFIIndex: MI->getOperand(i: 0).getCFIIndex())
399 .setMIFlags(MI->getFlags());
400 return;
401 }
402 MachineInstr &NewMI = TII->duplicate(MBB&: *PredBB, InsertBefore: PredBB->end(), Orig: *MI);
403 if (PreRegAlloc) {
404 for (unsigned i = 0, e = NewMI.getNumOperands(); i != e; ++i) {
405 MachineOperand &MO = NewMI.getOperand(i);
406 if (!MO.isReg())
407 continue;
408 Register Reg = MO.getReg();
409 if (!Reg.isVirtual())
410 continue;
411 if (MO.isDef()) {
412 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
413 Register NewReg = MRI->createVirtualRegister(RegClass: RC);
414 MO.setReg(NewReg);
415 LocalVRMap.insert(KV: std::make_pair(x&: Reg, y: RegSubRegPair(NewReg, 0)));
416 if (isDefLiveOut(Reg, BB: TailBB, MRI) || UsedByPhi.count(V: Reg))
417 addSSAUpdateEntry(OrigReg: Reg, NewReg, BB: PredBB);
418 } else {
419 auto VI = LocalVRMap.find(Val: Reg);
420 if (VI != LocalVRMap.end()) {
421 // Need to make sure that the register class of the mapped register
422 // will satisfy the constraints of the class of the register being
423 // replaced.
424 auto *OrigRC = MRI->getRegClass(Reg);
425 auto *MappedRC = MRI->getRegClass(Reg: VI->second.Reg);
426 const TargetRegisterClass *ConstrRC;
427 if (VI->second.SubReg != 0) {
428 ConstrRC = TRI->getMatchingSuperRegClass(A: MappedRC, B: OrigRC,
429 Idx: VI->second.SubReg);
430 if (ConstrRC) {
431 // The actual constraining (as in "find appropriate new class")
432 // is done by getMatchingSuperRegClass, so now we only need to
433 // change the class of the mapped register.
434 MRI->setRegClass(Reg: VI->second.Reg, RC: ConstrRC);
435 }
436 } else {
437 // For mapped registers that do not have sub-registers, simply
438 // restrict their class to match the original one.
439
440 // We don't want debug instructions affecting the resulting code so
441 // if we're cloning a debug instruction then just use MappedRC
442 // rather than constraining the register class further.
443 ConstrRC = NewMI.isDebugInstr()
444 ? MappedRC
445 : MRI->constrainRegClass(Reg: VI->second.Reg, RC: OrigRC);
446 }
447
448 if (ConstrRC) {
449 // If the class constraining succeeded, we can simply replace
450 // the old register with the mapped one.
451 MO.setReg(VI->second.Reg);
452 // We have Reg -> VI.Reg:VI.SubReg, so if Reg is used with a
453 // sub-register, we need to compose the sub-register indices.
454 MO.setSubReg(
455 TRI->composeSubRegIndices(a: VI->second.SubReg, b: MO.getSubReg()));
456 } else {
457 // The direct replacement is not possible, due to failing register
458 // class constraints. An explicit COPY is necessary. Create one
459 // that can be reused.
460 Register NewReg = MRI->createVirtualRegister(RegClass: OrigRC);
461 BuildMI(BB&: *PredBB, I&: NewMI, MIMD: NewMI.getDebugLoc(),
462 MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: NewReg)
463 .addReg(RegNo: VI->second.Reg, flags: 0, SubReg: VI->second.SubReg);
464 LocalVRMap.erase(I: VI);
465 LocalVRMap.insert(KV: std::make_pair(x&: Reg, y: RegSubRegPair(NewReg, 0)));
466 MO.setReg(NewReg);
467 // The composed VI.Reg:VI.SubReg is replaced with NewReg, which
468 // is equivalent to the whole register Reg. Hence, Reg:subreg
469 // is same as NewReg:subreg, so keep the sub-register index
470 // unchanged.
471 }
472 // Clear any kill flags from this operand. The new register could
473 // have uses after this one, so kills are not valid here.
474 MO.setIsKill(false);
475 }
476 }
477 }
478 }
479}
480
481/// After FromBB is tail duplicated into its predecessor blocks, the successors
482/// have gained new predecessors. Update the PHI instructions in them
483/// accordingly.
484void TailDuplicator::updateSuccessorsPHIs(
485 MachineBasicBlock *FromBB, bool isDead,
486 SmallVectorImpl<MachineBasicBlock *> &TDBBs,
487 SmallSetVector<MachineBasicBlock *, 8> &Succs) {
488 for (MachineBasicBlock *SuccBB : Succs) {
489 for (MachineInstr &MI : *SuccBB) {
490 if (!MI.isPHI())
491 break;
492 MachineInstrBuilder MIB(*FromBB->getParent(), MI);
493 unsigned Idx = 0;
494 for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
495 MachineOperand &MO = MI.getOperand(i: i + 1);
496 if (MO.getMBB() == FromBB) {
497 Idx = i;
498 break;
499 }
500 }
501
502 assert(Idx != 0);
503 MachineOperand &MO0 = MI.getOperand(i: Idx);
504 Register Reg = MO0.getReg();
505 if (isDead) {
506 // Folded into the previous BB.
507 // There could be duplicate phi source entries. FIXME: Should sdisel
508 // or earlier pass fixed this?
509 for (unsigned i = MI.getNumOperands() - 2; i != Idx; i -= 2) {
510 MachineOperand &MO = MI.getOperand(i: i + 1);
511 if (MO.getMBB() == FromBB) {
512 MI.removeOperand(OpNo: i + 1);
513 MI.removeOperand(OpNo: i);
514 }
515 }
516 } else
517 Idx = 0;
518
519 // If Idx is set, the operands at Idx and Idx+1 must be removed.
520 // We reuse the location to avoid expensive removeOperand calls.
521
522 DenseMap<Register, AvailableValsTy>::iterator LI =
523 SSAUpdateVals.find(Val: Reg);
524 if (LI != SSAUpdateVals.end()) {
525 // This register is defined in the tail block.
526 for (const std::pair<MachineBasicBlock *, Register> &J : LI->second) {
527 MachineBasicBlock *SrcBB = J.first;
528 // If we didn't duplicate a bb into a particular predecessor, we
529 // might still have added an entry to SSAUpdateVals to correcly
530 // recompute SSA. If that case, avoid adding a dummy extra argument
531 // this PHI.
532 if (!SrcBB->isSuccessor(MBB: SuccBB))
533 continue;
534
535 Register SrcReg = J.second;
536 if (Idx != 0) {
537 MI.getOperand(i: Idx).setReg(SrcReg);
538 MI.getOperand(i: Idx + 1).setMBB(SrcBB);
539 Idx = 0;
540 } else {
541 MIB.addReg(RegNo: SrcReg).addMBB(MBB: SrcBB);
542 }
543 }
544 } else {
545 // Live in tail block, must also be live in predecessors.
546 for (MachineBasicBlock *SrcBB : TDBBs) {
547 if (Idx != 0) {
548 MI.getOperand(i: Idx).setReg(Reg);
549 MI.getOperand(i: Idx + 1).setMBB(SrcBB);
550 Idx = 0;
551 } else {
552 MIB.addReg(RegNo: Reg).addMBB(MBB: SrcBB);
553 }
554 }
555 }
556 if (Idx != 0) {
557 MI.removeOperand(OpNo: Idx + 1);
558 MI.removeOperand(OpNo: Idx);
559 }
560 }
561 }
562}
563
564/// Determine if it is profitable to duplicate this block.
565bool TailDuplicator::shouldTailDuplicate(bool IsSimple,
566 MachineBasicBlock &TailBB) {
567 // When doing tail-duplication during layout, the block ordering is in flux,
568 // so canFallThrough returns a result based on incorrect information and
569 // should just be ignored.
570 if (!LayoutMode && TailBB.canFallThrough())
571 return false;
572
573 // Don't try to tail-duplicate single-block loops.
574 if (TailBB.isSuccessor(MBB: &TailBB))
575 return false;
576
577 // Duplicating a BB which has both multiple predecessors and successors will
578 // result in a complex CFG and also may cause huge amount of PHI nodes. If we
579 // want to remove this limitation, we have to address
580 // https://github.com/llvm/llvm-project/issues/78578.
581 if (TailBB.pred_size() > TailDupPredSize &&
582 TailBB.succ_size() > TailDupSuccSize)
583 return false;
584
585 // Set the limit on the cost to duplicate. When optimizing for size,
586 // duplicate only one, because one branch instruction can be eliminated to
587 // compensate for the duplication.
588 unsigned MaxDuplicateCount;
589 bool OptForSize = MF->getFunction().hasOptSize() ||
590 llvm::shouldOptimizeForSize(MBB: &TailBB, PSI, MBFIWrapper: MBFI);
591 if (TailDupSize == 0)
592 MaxDuplicateCount = TailDuplicateSize;
593 else
594 MaxDuplicateCount = TailDupSize;
595 if (OptForSize)
596 MaxDuplicateCount = 1;
597
598 // If the block to be duplicated ends in an unanalyzable fallthrough, don't
599 // duplicate it.
600 // A similar check is necessary in MachineBlockPlacement to make sure pairs of
601 // blocks with unanalyzable fallthrough get layed out contiguously.
602 MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
603 SmallVector<MachineOperand, 4> PredCond;
604 if (TII->analyzeBranch(MBB&: TailBB, TBB&: PredTBB, FBB&: PredFBB, Cond&: PredCond) &&
605 TailBB.canFallThrough())
606 return false;
607
608 // If the target has hardware branch prediction that can handle indirect
609 // branches, duplicating them can often make them predictable when there
610 // are common paths through the code. The limit needs to be high enough
611 // to allow undoing the effects of tail merging and other optimizations
612 // that rearrange the predecessors of the indirect branch.
613
614 bool HasIndirectbr = false;
615 if (!TailBB.empty())
616 HasIndirectbr = TailBB.back().isIndirectBranch();
617
618 if (HasIndirectbr && PreRegAlloc)
619 MaxDuplicateCount = TailDupIndirectBranchSize;
620
621 // Check the instructions in the block to determine whether tail-duplication
622 // is invalid or unlikely to be profitable.
623 unsigned InstrCount = 0;
624 for (MachineInstr &MI : TailBB) {
625 // Non-duplicable things shouldn't be tail-duplicated.
626 // CFI instructions are marked as non-duplicable, because Darwin compact
627 // unwind info emission can't handle multiple prologue setups. In case of
628 // DWARF, allow them be duplicated, so that their existence doesn't prevent
629 // tail duplication of some basic blocks, that would be duplicated otherwise.
630 if (MI.isNotDuplicable() &&
631 (TailBB.getParent()->getTarget().getTargetTriple().isOSDarwin() ||
632 !MI.isCFIInstruction()))
633 return false;
634
635 // Convergent instructions can be duplicated only if doing so doesn't add
636 // new control dependencies, which is what we're going to do here.
637 if (MI.isConvergent())
638 return false;
639
640 // Do not duplicate 'return' instructions if this is a pre-regalloc run.
641 // A return may expand into a lot more instructions (e.g. reload of callee
642 // saved registers) after PEI.
643 if (PreRegAlloc && MI.isReturn())
644 return false;
645
646 // Avoid duplicating calls before register allocation. Calls presents a
647 // barrier to register allocation so duplicating them may end up increasing
648 // spills.
649 if (PreRegAlloc && MI.isCall())
650 return false;
651
652 // TailDuplicator::appendCopies will erroneously place COPYs after
653 // INLINEASM_BR instructions after 4b0aa5724fea, which demonstrates the same
654 // bug that was fixed in f7a53d82c090.
655 // FIXME: Use findPHICopyInsertPoint() to find the correct insertion point
656 // for the COPY when replacing PHIs.
657 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
658 return false;
659
660 if (MI.isBundle())
661 InstrCount += MI.getBundleSize();
662 else if (!MI.isPHI() && !MI.isMetaInstruction())
663 InstrCount += 1;
664
665 if (InstrCount > MaxDuplicateCount)
666 return false;
667 }
668
669 // Check if any of the successors of TailBB has a PHI node in which the
670 // value corresponding to TailBB uses a subregister.
671 // If a phi node uses a register paired with a subregister, the actual
672 // "value type" of the phi may differ from the type of the register without
673 // any subregisters. Due to a bug, tail duplication may add a new operand
674 // without a necessary subregister, producing an invalid code. This is
675 // demonstrated by test/CodeGen/Hexagon/tail-dup-subreg-abort.ll.
676 // Disable tail duplication for this case for now, until the problem is
677 // fixed.
678 for (auto *SB : TailBB.successors()) {
679 for (auto &I : *SB) {
680 if (!I.isPHI())
681 break;
682 unsigned Idx = getPHISrcRegOpIdx(MI: &I, SrcBB: &TailBB);
683 assert(Idx != 0);
684 MachineOperand &PU = I.getOperand(i: Idx);
685 if (PU.getSubReg() != 0)
686 return false;
687 }
688 }
689
690 if (HasIndirectbr && PreRegAlloc)
691 return true;
692
693 if (IsSimple)
694 return true;
695
696 if (!PreRegAlloc)
697 return true;
698
699 return canCompletelyDuplicateBB(BB&: TailBB);
700}
701
702/// True if this BB has only one unconditional jump.
703bool TailDuplicator::isSimpleBB(MachineBasicBlock *TailBB) {
704 if (TailBB->succ_size() != 1)
705 return false;
706 if (TailBB->pred_empty())
707 return false;
708 MachineBasicBlock::iterator I = TailBB->getFirstNonDebugInstr(SkipPseudoOp: true);
709 if (I == TailBB->end())
710 return true;
711 return I->isUnconditionalBranch();
712}
713
714static bool bothUsedInPHI(const MachineBasicBlock &A,
715 const SmallPtrSet<MachineBasicBlock *, 8> &SuccsB) {
716 for (MachineBasicBlock *BB : A.successors())
717 if (SuccsB.count(Ptr: BB) && !BB->empty() && BB->begin()->isPHI())
718 return true;
719
720 return false;
721}
722
723bool TailDuplicator::canCompletelyDuplicateBB(MachineBasicBlock &BB) {
724 for (MachineBasicBlock *PredBB : BB.predecessors()) {
725 if (PredBB->succ_size() > 1)
726 return false;
727
728 MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
729 SmallVector<MachineOperand, 4> PredCond;
730 if (TII->analyzeBranch(MBB&: *PredBB, TBB&: PredTBB, FBB&: PredFBB, Cond&: PredCond))
731 return false;
732
733 if (!PredCond.empty())
734 return false;
735 }
736 return true;
737}
738
739bool TailDuplicator::duplicateSimpleBB(
740 MachineBasicBlock *TailBB, SmallVectorImpl<MachineBasicBlock *> &TDBBs,
741 const DenseSet<Register> &UsedByPhi) {
742 SmallPtrSet<MachineBasicBlock *, 8> Succs(TailBB->succ_begin(),
743 TailBB->succ_end());
744 SmallVector<MachineBasicBlock *, 8> Preds(TailBB->predecessors());
745 bool Changed = false;
746 for (MachineBasicBlock *PredBB : Preds) {
747 if (PredBB->hasEHPadSuccessor() || PredBB->mayHaveInlineAsmBr())
748 continue;
749
750 if (bothUsedInPHI(A: *PredBB, SuccsB: Succs))
751 continue;
752
753 MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
754 SmallVector<MachineOperand, 4> PredCond;
755 if (TII->analyzeBranch(MBB&: *PredBB, TBB&: PredTBB, FBB&: PredFBB, Cond&: PredCond))
756 continue;
757
758 Changed = true;
759 LLVM_DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB
760 << "From simple Succ: " << *TailBB);
761
762 MachineBasicBlock *NewTarget = *TailBB->succ_begin();
763 MachineBasicBlock *NextBB = PredBB->getNextNode();
764
765 // Make PredFBB explicit.
766 if (PredCond.empty())
767 PredFBB = PredTBB;
768
769 // Make fall through explicit.
770 if (!PredTBB)
771 PredTBB = NextBB;
772 if (!PredFBB)
773 PredFBB = NextBB;
774
775 // Redirect
776 if (PredFBB == TailBB)
777 PredFBB = NewTarget;
778 if (PredTBB == TailBB)
779 PredTBB = NewTarget;
780
781 // Make the branch unconditional if possible
782 if (PredTBB == PredFBB) {
783 PredCond.clear();
784 PredFBB = nullptr;
785 }
786
787 // Avoid adding fall through branches.
788 if (PredFBB == NextBB)
789 PredFBB = nullptr;
790 if (PredTBB == NextBB && PredFBB == nullptr)
791 PredTBB = nullptr;
792
793 auto DL = PredBB->findBranchDebugLoc();
794 TII->removeBranch(MBB&: *PredBB);
795
796 if (!PredBB->isSuccessor(MBB: NewTarget))
797 PredBB->replaceSuccessor(Old: TailBB, New: NewTarget);
798 else {
799 PredBB->removeSuccessor(Succ: TailBB, NormalizeSuccProbs: true);
800 assert(PredBB->succ_size() <= 1);
801 }
802
803 if (PredTBB)
804 TII->insertBranch(MBB&: *PredBB, TBB: PredTBB, FBB: PredFBB, Cond: PredCond, DL);
805
806 TDBBs.push_back(Elt: PredBB);
807 }
808 return Changed;
809}
810
811bool TailDuplicator::canTailDuplicate(MachineBasicBlock *TailBB,
812 MachineBasicBlock *PredBB) {
813 // EH edges are ignored by analyzeBranch.
814 if (PredBB->succ_size() > 1)
815 return false;
816
817 MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
818 SmallVector<MachineOperand, 4> PredCond;
819 if (TII->analyzeBranch(MBB&: *PredBB, TBB&: PredTBB, FBB&: PredFBB, Cond&: PredCond))
820 return false;
821 if (!PredCond.empty())
822 return false;
823 // FIXME: This is overly conservative; it may be ok to relax this in the
824 // future under more specific conditions. If TailBB is an INLINEASM_BR
825 // indirect target, we need to see if the edge from PredBB to TailBB is from
826 // an INLINEASM_BR in PredBB, and then also if that edge was from the
827 // indirect target list, fallthrough/default target, or potentially both. If
828 // it's both, TailDuplicator::tailDuplicate will remove the edge, corrupting
829 // the successor list in PredBB and predecessor list in TailBB.
830 if (TailBB->isInlineAsmBrIndirectTarget())
831 return false;
832 return true;
833}
834
835/// If it is profitable, duplicate TailBB's contents in each
836/// of its predecessors.
837/// \p IsSimple result of isSimpleBB
838/// \p TailBB Block to be duplicated.
839/// \p ForcedLayoutPred When non-null, use this block as the layout predecessor
840/// instead of the previous block in MF's order.
841/// \p TDBBs A vector to keep track of all blocks tail-duplicated
842/// into.
843/// \p Copies A vector of copy instructions inserted. Used later to
844/// walk all the inserted copies and remove redundant ones.
845bool TailDuplicator::tailDuplicate(bool IsSimple, MachineBasicBlock *TailBB,
846 MachineBasicBlock *ForcedLayoutPred,
847 SmallVectorImpl<MachineBasicBlock *> &TDBBs,
848 SmallVectorImpl<MachineInstr *> &Copies,
849 SmallVectorImpl<MachineBasicBlock *> *CandidatePtr) {
850 LLVM_DEBUG(dbgs() << "\n*** Tail-duplicating " << printMBBReference(*TailBB)
851 << '\n');
852
853 bool ShouldUpdateTerminators = TailBB->canFallThrough();
854
855 DenseSet<Register> UsedByPhi;
856 getRegsUsedByPHIs(BB: *TailBB, UsedByPhi: &UsedByPhi);
857
858 if (IsSimple)
859 return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi);
860
861 // Iterate through all the unique predecessors and tail-duplicate this
862 // block into them, if possible. Copying the list ahead of time also
863 // avoids trouble with the predecessor list reallocating.
864 bool Changed = false;
865 SmallSetVector<MachineBasicBlock *, 8> Preds;
866 if (CandidatePtr)
867 Preds.insert(Start: CandidatePtr->begin(), End: CandidatePtr->end());
868 else
869 Preds.insert(Start: TailBB->pred_begin(), End: TailBB->pred_end());
870
871 for (MachineBasicBlock *PredBB : Preds) {
872 assert(TailBB != PredBB &&
873 "Single-block loop should have been rejected earlier!");
874
875 if (!canTailDuplicate(TailBB, PredBB))
876 continue;
877
878 // Don't duplicate into a fall-through predecessor (at least for now).
879 // If profile is available, findDuplicateCandidates can choose better
880 // fall-through predecessor.
881 if (!(MF->getFunction().hasProfileData() && LayoutMode)) {
882 bool IsLayoutSuccessor = false;
883 if (ForcedLayoutPred)
884 IsLayoutSuccessor = (ForcedLayoutPred == PredBB);
885 else if (PredBB->isLayoutSuccessor(MBB: TailBB) && PredBB->canFallThrough())
886 IsLayoutSuccessor = true;
887 if (IsLayoutSuccessor)
888 continue;
889 }
890
891 LLVM_DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB
892 << "From Succ: " << *TailBB);
893
894 TDBBs.push_back(Elt: PredBB);
895
896 // Remove PredBB's unconditional branch.
897 TII->removeBranch(MBB&: *PredBB);
898
899 // Clone the contents of TailBB into PredBB.
900 DenseMap<Register, RegSubRegPair> LocalVRMap;
901 SmallVector<std::pair<Register, RegSubRegPair>, 4> CopyInfos;
902 for (MachineInstr &MI : llvm::make_early_inc_range(Range&: *TailBB)) {
903 if (MI.isPHI()) {
904 // Replace the uses of the def of the PHI with the register coming
905 // from PredBB.
906 processPHI(MI: &MI, TailBB, PredBB, LocalVRMap, Copies&: CopyInfos, RegsUsedByPhi: UsedByPhi, Remove: true);
907 } else {
908 // Replace def of virtual registers with new registers, and update
909 // uses with PHI source register or the new registers.
910 duplicateInstruction(MI: &MI, TailBB, PredBB, LocalVRMap, UsedByPhi);
911 }
912 }
913 appendCopies(MBB: PredBB, CopyInfos, Copies);
914
915 NumTailDupAdded += TailBB->size() - 1; // subtract one for removed branch
916
917 // Update the CFG.
918 PredBB->removeSuccessor(I: PredBB->succ_begin());
919 assert(PredBB->succ_empty() &&
920 "TailDuplicate called on block with multiple successors!");
921 for (MachineBasicBlock *Succ : TailBB->successors())
922 PredBB->addSuccessor(Succ, Prob: MBPI->getEdgeProbability(Src: TailBB, Dst: Succ));
923
924 // Update branches in pred to jump to tail's layout successor if needed.
925 if (ShouldUpdateTerminators)
926 PredBB->updateTerminator(PreviousLayoutSuccessor: TailBB->getNextNode());
927
928 Changed = true;
929 ++NumTailDups;
930 }
931
932 // If TailBB was duplicated into all its predecessors except for the prior
933 // block, which falls through unconditionally, move the contents of this
934 // block into the prior block.
935 MachineBasicBlock *PrevBB = ForcedLayoutPred;
936 if (!PrevBB)
937 PrevBB = &*std::prev(x: TailBB->getIterator());
938 MachineBasicBlock *PriorTBB = nullptr, *PriorFBB = nullptr;
939 SmallVector<MachineOperand, 4> PriorCond;
940 // This has to check PrevBB->succ_size() because EH edges are ignored by
941 // analyzeBranch.
942 if (PrevBB->succ_size() == 1 &&
943 // Layout preds are not always CFG preds. Check.
944 *PrevBB->succ_begin() == TailBB &&
945 !TII->analyzeBranch(MBB&: *PrevBB, TBB&: PriorTBB, FBB&: PriorFBB, Cond&: PriorCond) &&
946 PriorCond.empty() &&
947 (!PriorTBB || PriorTBB == TailBB) &&
948 TailBB->pred_size() == 1 &&
949 !TailBB->hasAddressTaken()) {
950 LLVM_DEBUG(dbgs() << "\nMerging into block: " << *PrevBB
951 << "From MBB: " << *TailBB);
952 // There may be a branch to the layout successor. This is unlikely but it
953 // happens. The correct thing to do is to remove the branch before
954 // duplicating the instructions in all cases.
955 bool RemovedBranches = TII->removeBranch(MBB&: *PrevBB) != 0;
956
957 // If there are still tail instructions, abort the merge
958 if (PrevBB->getFirstTerminator() == PrevBB->end()) {
959 if (PreRegAlloc) {
960 DenseMap<Register, RegSubRegPair> LocalVRMap;
961 SmallVector<std::pair<Register, RegSubRegPair>, 4> CopyInfos;
962 MachineBasicBlock::iterator I = TailBB->begin();
963 // Process PHI instructions first.
964 while (I != TailBB->end() && I->isPHI()) {
965 // Replace the uses of the def of the PHI with the register coming
966 // from PredBB.
967 MachineInstr *MI = &*I++;
968 processPHI(MI, TailBB, PredBB: PrevBB, LocalVRMap, Copies&: CopyInfos, RegsUsedByPhi: UsedByPhi,
969 Remove: true);
970 }
971
972 // Now copy the non-PHI instructions.
973 while (I != TailBB->end()) {
974 // Replace def of virtual registers with new registers, and update
975 // uses with PHI source register or the new registers.
976 MachineInstr *MI = &*I++;
977 assert(!MI->isBundle() && "Not expecting bundles before regalloc!");
978 duplicateInstruction(MI, TailBB, PredBB: PrevBB, LocalVRMap, UsedByPhi);
979 MI->eraseFromParent();
980 }
981 appendCopies(MBB: PrevBB, CopyInfos, Copies);
982 } else {
983 TII->removeBranch(MBB&: *PrevBB);
984 // No PHIs to worry about, just splice the instructions over.
985 PrevBB->splice(Where: PrevBB->end(), Other: TailBB, From: TailBB->begin(), To: TailBB->end());
986 }
987 PrevBB->removeSuccessor(I: PrevBB->succ_begin());
988 assert(PrevBB->succ_empty());
989 PrevBB->transferSuccessors(FromMBB: TailBB);
990
991 // Update branches in PrevBB based on Tail's layout successor.
992 if (ShouldUpdateTerminators)
993 PrevBB->updateTerminator(PreviousLayoutSuccessor: TailBB->getNextNode());
994
995 TDBBs.push_back(Elt: PrevBB);
996 Changed = true;
997 } else {
998 LLVM_DEBUG(dbgs() << "Abort merging blocks, the predecessor still "
999 "contains terminator instructions");
1000 // Return early if no changes were made
1001 if (!Changed)
1002 return RemovedBranches;
1003 }
1004 Changed |= RemovedBranches;
1005 }
1006
1007 // If this is after register allocation, there are no phis to fix.
1008 if (!PreRegAlloc)
1009 return Changed;
1010
1011 // If we made no changes so far, we are safe.
1012 if (!Changed)
1013 return Changed;
1014
1015 // Handle the nasty case in that we duplicated a block that is part of a loop
1016 // into some but not all of its predecessors. For example:
1017 // 1 -> 2 <-> 3 |
1018 // \ |
1019 // \---> rest |
1020 // if we duplicate 2 into 1 but not into 3, we end up with
1021 // 12 -> 3 <-> 2 -> rest |
1022 // \ / |
1023 // \----->-----/ |
1024 // If there was a "var = phi(1, 3)" in 2, it has to be ultimately replaced
1025 // with a phi in 3 (which now dominates 2).
1026 // What we do here is introduce a copy in 3 of the register defined by the
1027 // phi, just like when we are duplicating 2 into 3, but we don't copy any
1028 // real instructions or remove the 3 -> 2 edge from the phi in 2.
1029 for (MachineBasicBlock *PredBB : Preds) {
1030 if (is_contained(Range&: TDBBs, Element: PredBB))
1031 continue;
1032
1033 // EH edges
1034 if (PredBB->succ_size() != 1)
1035 continue;
1036
1037 DenseMap<Register, RegSubRegPair> LocalVRMap;
1038 SmallVector<std::pair<Register, RegSubRegPair>, 4> CopyInfos;
1039 // Process PHI instructions first.
1040 for (MachineInstr &MI : make_early_inc_range(Range: TailBB->phis())) {
1041 // Replace the uses of the def of the PHI with the register coming
1042 // from PredBB.
1043 processPHI(MI: &MI, TailBB, PredBB, LocalVRMap, Copies&: CopyInfos, RegsUsedByPhi: UsedByPhi, Remove: false);
1044 }
1045 appendCopies(MBB: PredBB, CopyInfos, Copies);
1046 }
1047
1048 return Changed;
1049}
1050
1051/// At the end of the block \p MBB generate COPY instructions between registers
1052/// described by \p CopyInfos. Append resulting instructions to \p Copies.
1053void TailDuplicator::appendCopies(MachineBasicBlock *MBB,
1054 SmallVectorImpl<std::pair<Register, RegSubRegPair>> &CopyInfos,
1055 SmallVectorImpl<MachineInstr*> &Copies) {
1056 MachineBasicBlock::iterator Loc = MBB->getFirstTerminator();
1057 const MCInstrDesc &CopyD = TII->get(Opcode: TargetOpcode::COPY);
1058 for (auto &CI : CopyInfos) {
1059 auto C = BuildMI(BB&: *MBB, I: Loc, MIMD: DebugLoc(), MCID: CopyD, DestReg: CI.first)
1060 .addReg(RegNo: CI.second.Reg, flags: 0, SubReg: CI.second.SubReg);
1061 Copies.push_back(Elt: C);
1062 }
1063}
1064
1065/// Remove the specified dead machine basic block from the function, updating
1066/// the CFG.
1067void TailDuplicator::removeDeadBlock(
1068 MachineBasicBlock *MBB,
1069 function_ref<void(MachineBasicBlock *)> *RemovalCallback) {
1070 assert(MBB->pred_empty() && "MBB must be dead!");
1071 LLVM_DEBUG(dbgs() << "\nRemoving MBB: " << *MBB);
1072
1073 MachineFunction *MF = MBB->getParent();
1074 // Update the call site info.
1075 for (const MachineInstr &MI : *MBB)
1076 if (MI.shouldUpdateCallSiteInfo())
1077 MF->eraseCallSiteInfo(MI: &MI);
1078
1079 if (RemovalCallback)
1080 (*RemovalCallback)(MBB);
1081
1082 // Remove all successors.
1083 while (!MBB->succ_empty())
1084 MBB->removeSuccessor(I: MBB->succ_end() - 1);
1085
1086 // Remove the block.
1087 MBB->eraseFromParent();
1088}
1089