1//===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AArch64 specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "AArch64MCTargetDesc.h"
14#include "AArch64ELFStreamer.h"
15#include "AArch64MCAsmInfo.h"
16#include "AArch64WinCOFFStreamer.h"
17#include "MCTargetDesc/AArch64AddressingModes.h"
18#include "MCTargetDesc/AArch64InstPrinter.h"
19#include "TargetInfo/AArch64TargetInfo.h"
20#include "llvm/DebugInfo/CodeView/CodeView.h"
21#include "llvm/MC/MCAsmBackend.h"
22#include "llvm/MC/MCCodeEmitter.h"
23#include "llvm/MC/MCInstrAnalysis.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCObjectWriter.h"
26#include "llvm/MC/MCRegisterInfo.h"
27#include "llvm/MC/MCStreamer.h"
28#include "llvm/MC/MCSubtargetInfo.h"
29#include "llvm/MC/TargetRegistry.h"
30#include "llvm/Support/Endian.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/TargetParser/AArch64TargetParser.h"
33
34using namespace llvm;
35
36#define GET_INSTRINFO_MC_DESC
37#define GET_INSTRINFO_MC_HELPERS
38#define ENABLE_INSTR_PREDICATE_VERIFIER
39#include "AArch64GenInstrInfo.inc"
40
41#define GET_SUBTARGETINFO_MC_DESC
42#include "AArch64GenSubtargetInfo.inc"
43
44#define GET_REGINFO_MC_DESC
45#include "AArch64GenRegisterInfo.inc"
46
47static MCInstrInfo *createAArch64MCInstrInfo() {
48 MCInstrInfo *X = new MCInstrInfo();
49 InitAArch64MCInstrInfo(II: X);
50 return X;
51}
52
53static MCSubtargetInfo *
54createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
55 CPU = AArch64::resolveCPUAlias(CPU);
56
57 if (CPU.empty()) {
58 CPU = "generic";
59 if (FS.empty())
60 FS = "+v8a";
61
62 if (TT.isArm64e())
63 CPU = "apple-a12";
64 }
65
66 return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
67}
68
69void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
70 // Mapping from CodeView to MC register id.
71 static const struct {
72 codeview::RegisterId CVReg;
73 MCPhysReg Reg;
74 } RegMap[] = {
75 {.CVReg: codeview::RegisterId::ARM64_W0, .Reg: AArch64::W0},
76 {.CVReg: codeview::RegisterId::ARM64_W1, .Reg: AArch64::W1},
77 {.CVReg: codeview::RegisterId::ARM64_W2, .Reg: AArch64::W2},
78 {.CVReg: codeview::RegisterId::ARM64_W3, .Reg: AArch64::W3},
79 {.CVReg: codeview::RegisterId::ARM64_W4, .Reg: AArch64::W4},
80 {.CVReg: codeview::RegisterId::ARM64_W5, .Reg: AArch64::W5},
81 {.CVReg: codeview::RegisterId::ARM64_W6, .Reg: AArch64::W6},
82 {.CVReg: codeview::RegisterId::ARM64_W7, .Reg: AArch64::W7},
83 {.CVReg: codeview::RegisterId::ARM64_W8, .Reg: AArch64::W8},
84 {.CVReg: codeview::RegisterId::ARM64_W9, .Reg: AArch64::W9},
85 {.CVReg: codeview::RegisterId::ARM64_W10, .Reg: AArch64::W10},
86 {.CVReg: codeview::RegisterId::ARM64_W11, .Reg: AArch64::W11},
87 {.CVReg: codeview::RegisterId::ARM64_W12, .Reg: AArch64::W12},
88 {.CVReg: codeview::RegisterId::ARM64_W13, .Reg: AArch64::W13},
89 {.CVReg: codeview::RegisterId::ARM64_W14, .Reg: AArch64::W14},
90 {.CVReg: codeview::RegisterId::ARM64_W15, .Reg: AArch64::W15},
91 {.CVReg: codeview::RegisterId::ARM64_W16, .Reg: AArch64::W16},
92 {.CVReg: codeview::RegisterId::ARM64_W17, .Reg: AArch64::W17},
93 {.CVReg: codeview::RegisterId::ARM64_W18, .Reg: AArch64::W18},
94 {.CVReg: codeview::RegisterId::ARM64_W19, .Reg: AArch64::W19},
95 {.CVReg: codeview::RegisterId::ARM64_W20, .Reg: AArch64::W20},
96 {.CVReg: codeview::RegisterId::ARM64_W21, .Reg: AArch64::W21},
97 {.CVReg: codeview::RegisterId::ARM64_W22, .Reg: AArch64::W22},
98 {.CVReg: codeview::RegisterId::ARM64_W23, .Reg: AArch64::W23},
99 {.CVReg: codeview::RegisterId::ARM64_W24, .Reg: AArch64::W24},
100 {.CVReg: codeview::RegisterId::ARM64_W25, .Reg: AArch64::W25},
101 {.CVReg: codeview::RegisterId::ARM64_W26, .Reg: AArch64::W26},
102 {.CVReg: codeview::RegisterId::ARM64_W27, .Reg: AArch64::W27},
103 {.CVReg: codeview::RegisterId::ARM64_W28, .Reg: AArch64::W28},
104 {.CVReg: codeview::RegisterId::ARM64_W29, .Reg: AArch64::W29},
105 {.CVReg: codeview::RegisterId::ARM64_W30, .Reg: AArch64::W30},
106 {.CVReg: codeview::RegisterId::ARM64_WZR, .Reg: AArch64::WZR},
107 {.CVReg: codeview::RegisterId::ARM64_X0, .Reg: AArch64::X0},
108 {.CVReg: codeview::RegisterId::ARM64_X1, .Reg: AArch64::X1},
109 {.CVReg: codeview::RegisterId::ARM64_X2, .Reg: AArch64::X2},
110 {.CVReg: codeview::RegisterId::ARM64_X3, .Reg: AArch64::X3},
111 {.CVReg: codeview::RegisterId::ARM64_X4, .Reg: AArch64::X4},
112 {.CVReg: codeview::RegisterId::ARM64_X5, .Reg: AArch64::X5},
113 {.CVReg: codeview::RegisterId::ARM64_X6, .Reg: AArch64::X6},
114 {.CVReg: codeview::RegisterId::ARM64_X7, .Reg: AArch64::X7},
115 {.CVReg: codeview::RegisterId::ARM64_X8, .Reg: AArch64::X8},
116 {.CVReg: codeview::RegisterId::ARM64_X9, .Reg: AArch64::X9},
117 {.CVReg: codeview::RegisterId::ARM64_X10, .Reg: AArch64::X10},
118 {.CVReg: codeview::RegisterId::ARM64_X11, .Reg: AArch64::X11},
119 {.CVReg: codeview::RegisterId::ARM64_X12, .Reg: AArch64::X12},
120 {.CVReg: codeview::RegisterId::ARM64_X13, .Reg: AArch64::X13},
121 {.CVReg: codeview::RegisterId::ARM64_X14, .Reg: AArch64::X14},
122 {.CVReg: codeview::RegisterId::ARM64_X15, .Reg: AArch64::X15},
123 {.CVReg: codeview::RegisterId::ARM64_X16, .Reg: AArch64::X16},
124 {.CVReg: codeview::RegisterId::ARM64_X17, .Reg: AArch64::X17},
125 {.CVReg: codeview::RegisterId::ARM64_X18, .Reg: AArch64::X18},
126 {.CVReg: codeview::RegisterId::ARM64_X19, .Reg: AArch64::X19},
127 {.CVReg: codeview::RegisterId::ARM64_X20, .Reg: AArch64::X20},
128 {.CVReg: codeview::RegisterId::ARM64_X21, .Reg: AArch64::X21},
129 {.CVReg: codeview::RegisterId::ARM64_X22, .Reg: AArch64::X22},
130 {.CVReg: codeview::RegisterId::ARM64_X23, .Reg: AArch64::X23},
131 {.CVReg: codeview::RegisterId::ARM64_X24, .Reg: AArch64::X24},
132 {.CVReg: codeview::RegisterId::ARM64_X25, .Reg: AArch64::X25},
133 {.CVReg: codeview::RegisterId::ARM64_X26, .Reg: AArch64::X26},
134 {.CVReg: codeview::RegisterId::ARM64_X27, .Reg: AArch64::X27},
135 {.CVReg: codeview::RegisterId::ARM64_X28, .Reg: AArch64::X28},
136 {.CVReg: codeview::RegisterId::ARM64_FP, .Reg: AArch64::FP},
137 {.CVReg: codeview::RegisterId::ARM64_LR, .Reg: AArch64::LR},
138 {.CVReg: codeview::RegisterId::ARM64_SP, .Reg: AArch64::SP},
139 {.CVReg: codeview::RegisterId::ARM64_ZR, .Reg: AArch64::XZR},
140 {.CVReg: codeview::RegisterId::ARM64_NZCV, .Reg: AArch64::NZCV},
141 {.CVReg: codeview::RegisterId::ARM64_S0, .Reg: AArch64::S0},
142 {.CVReg: codeview::RegisterId::ARM64_S1, .Reg: AArch64::S1},
143 {.CVReg: codeview::RegisterId::ARM64_S2, .Reg: AArch64::S2},
144 {.CVReg: codeview::RegisterId::ARM64_S3, .Reg: AArch64::S3},
145 {.CVReg: codeview::RegisterId::ARM64_S4, .Reg: AArch64::S4},
146 {.CVReg: codeview::RegisterId::ARM64_S5, .Reg: AArch64::S5},
147 {.CVReg: codeview::RegisterId::ARM64_S6, .Reg: AArch64::S6},
148 {.CVReg: codeview::RegisterId::ARM64_S7, .Reg: AArch64::S7},
149 {.CVReg: codeview::RegisterId::ARM64_S8, .Reg: AArch64::S8},
150 {.CVReg: codeview::RegisterId::ARM64_S9, .Reg: AArch64::S9},
151 {.CVReg: codeview::RegisterId::ARM64_S10, .Reg: AArch64::S10},
152 {.CVReg: codeview::RegisterId::ARM64_S11, .Reg: AArch64::S11},
153 {.CVReg: codeview::RegisterId::ARM64_S12, .Reg: AArch64::S12},
154 {.CVReg: codeview::RegisterId::ARM64_S13, .Reg: AArch64::S13},
155 {.CVReg: codeview::RegisterId::ARM64_S14, .Reg: AArch64::S14},
156 {.CVReg: codeview::RegisterId::ARM64_S15, .Reg: AArch64::S15},
157 {.CVReg: codeview::RegisterId::ARM64_S16, .Reg: AArch64::S16},
158 {.CVReg: codeview::RegisterId::ARM64_S17, .Reg: AArch64::S17},
159 {.CVReg: codeview::RegisterId::ARM64_S18, .Reg: AArch64::S18},
160 {.CVReg: codeview::RegisterId::ARM64_S19, .Reg: AArch64::S19},
161 {.CVReg: codeview::RegisterId::ARM64_S20, .Reg: AArch64::S20},
162 {.CVReg: codeview::RegisterId::ARM64_S21, .Reg: AArch64::S21},
163 {.CVReg: codeview::RegisterId::ARM64_S22, .Reg: AArch64::S22},
164 {.CVReg: codeview::RegisterId::ARM64_S23, .Reg: AArch64::S23},
165 {.CVReg: codeview::RegisterId::ARM64_S24, .Reg: AArch64::S24},
166 {.CVReg: codeview::RegisterId::ARM64_S25, .Reg: AArch64::S25},
167 {.CVReg: codeview::RegisterId::ARM64_S26, .Reg: AArch64::S26},
168 {.CVReg: codeview::RegisterId::ARM64_S27, .Reg: AArch64::S27},
169 {.CVReg: codeview::RegisterId::ARM64_S28, .Reg: AArch64::S28},
170 {.CVReg: codeview::RegisterId::ARM64_S29, .Reg: AArch64::S29},
171 {.CVReg: codeview::RegisterId::ARM64_S30, .Reg: AArch64::S30},
172 {.CVReg: codeview::RegisterId::ARM64_S31, .Reg: AArch64::S31},
173 {.CVReg: codeview::RegisterId::ARM64_D0, .Reg: AArch64::D0},
174 {.CVReg: codeview::RegisterId::ARM64_D1, .Reg: AArch64::D1},
175 {.CVReg: codeview::RegisterId::ARM64_D2, .Reg: AArch64::D2},
176 {.CVReg: codeview::RegisterId::ARM64_D3, .Reg: AArch64::D3},
177 {.CVReg: codeview::RegisterId::ARM64_D4, .Reg: AArch64::D4},
178 {.CVReg: codeview::RegisterId::ARM64_D5, .Reg: AArch64::D5},
179 {.CVReg: codeview::RegisterId::ARM64_D6, .Reg: AArch64::D6},
180 {.CVReg: codeview::RegisterId::ARM64_D7, .Reg: AArch64::D7},
181 {.CVReg: codeview::RegisterId::ARM64_D8, .Reg: AArch64::D8},
182 {.CVReg: codeview::RegisterId::ARM64_D9, .Reg: AArch64::D9},
183 {.CVReg: codeview::RegisterId::ARM64_D10, .Reg: AArch64::D10},
184 {.CVReg: codeview::RegisterId::ARM64_D11, .Reg: AArch64::D11},
185 {.CVReg: codeview::RegisterId::ARM64_D12, .Reg: AArch64::D12},
186 {.CVReg: codeview::RegisterId::ARM64_D13, .Reg: AArch64::D13},
187 {.CVReg: codeview::RegisterId::ARM64_D14, .Reg: AArch64::D14},
188 {.CVReg: codeview::RegisterId::ARM64_D15, .Reg: AArch64::D15},
189 {.CVReg: codeview::RegisterId::ARM64_D16, .Reg: AArch64::D16},
190 {.CVReg: codeview::RegisterId::ARM64_D17, .Reg: AArch64::D17},
191 {.CVReg: codeview::RegisterId::ARM64_D18, .Reg: AArch64::D18},
192 {.CVReg: codeview::RegisterId::ARM64_D19, .Reg: AArch64::D19},
193 {.CVReg: codeview::RegisterId::ARM64_D20, .Reg: AArch64::D20},
194 {.CVReg: codeview::RegisterId::ARM64_D21, .Reg: AArch64::D21},
195 {.CVReg: codeview::RegisterId::ARM64_D22, .Reg: AArch64::D22},
196 {.CVReg: codeview::RegisterId::ARM64_D23, .Reg: AArch64::D23},
197 {.CVReg: codeview::RegisterId::ARM64_D24, .Reg: AArch64::D24},
198 {.CVReg: codeview::RegisterId::ARM64_D25, .Reg: AArch64::D25},
199 {.CVReg: codeview::RegisterId::ARM64_D26, .Reg: AArch64::D26},
200 {.CVReg: codeview::RegisterId::ARM64_D27, .Reg: AArch64::D27},
201 {.CVReg: codeview::RegisterId::ARM64_D28, .Reg: AArch64::D28},
202 {.CVReg: codeview::RegisterId::ARM64_D29, .Reg: AArch64::D29},
203 {.CVReg: codeview::RegisterId::ARM64_D30, .Reg: AArch64::D30},
204 {.CVReg: codeview::RegisterId::ARM64_D31, .Reg: AArch64::D31},
205 {.CVReg: codeview::RegisterId::ARM64_Q0, .Reg: AArch64::Q0},
206 {.CVReg: codeview::RegisterId::ARM64_Q1, .Reg: AArch64::Q1},
207 {.CVReg: codeview::RegisterId::ARM64_Q2, .Reg: AArch64::Q2},
208 {.CVReg: codeview::RegisterId::ARM64_Q3, .Reg: AArch64::Q3},
209 {.CVReg: codeview::RegisterId::ARM64_Q4, .Reg: AArch64::Q4},
210 {.CVReg: codeview::RegisterId::ARM64_Q5, .Reg: AArch64::Q5},
211 {.CVReg: codeview::RegisterId::ARM64_Q6, .Reg: AArch64::Q6},
212 {.CVReg: codeview::RegisterId::ARM64_Q7, .Reg: AArch64::Q7},
213 {.CVReg: codeview::RegisterId::ARM64_Q8, .Reg: AArch64::Q8},
214 {.CVReg: codeview::RegisterId::ARM64_Q9, .Reg: AArch64::Q9},
215 {.CVReg: codeview::RegisterId::ARM64_Q10, .Reg: AArch64::Q10},
216 {.CVReg: codeview::RegisterId::ARM64_Q11, .Reg: AArch64::Q11},
217 {.CVReg: codeview::RegisterId::ARM64_Q12, .Reg: AArch64::Q12},
218 {.CVReg: codeview::RegisterId::ARM64_Q13, .Reg: AArch64::Q13},
219 {.CVReg: codeview::RegisterId::ARM64_Q14, .Reg: AArch64::Q14},
220 {.CVReg: codeview::RegisterId::ARM64_Q15, .Reg: AArch64::Q15},
221 {.CVReg: codeview::RegisterId::ARM64_Q16, .Reg: AArch64::Q16},
222 {.CVReg: codeview::RegisterId::ARM64_Q17, .Reg: AArch64::Q17},
223 {.CVReg: codeview::RegisterId::ARM64_Q18, .Reg: AArch64::Q18},
224 {.CVReg: codeview::RegisterId::ARM64_Q19, .Reg: AArch64::Q19},
225 {.CVReg: codeview::RegisterId::ARM64_Q20, .Reg: AArch64::Q20},
226 {.CVReg: codeview::RegisterId::ARM64_Q21, .Reg: AArch64::Q21},
227 {.CVReg: codeview::RegisterId::ARM64_Q22, .Reg: AArch64::Q22},
228 {.CVReg: codeview::RegisterId::ARM64_Q23, .Reg: AArch64::Q23},
229 {.CVReg: codeview::RegisterId::ARM64_Q24, .Reg: AArch64::Q24},
230 {.CVReg: codeview::RegisterId::ARM64_Q25, .Reg: AArch64::Q25},
231 {.CVReg: codeview::RegisterId::ARM64_Q26, .Reg: AArch64::Q26},
232 {.CVReg: codeview::RegisterId::ARM64_Q27, .Reg: AArch64::Q27},
233 {.CVReg: codeview::RegisterId::ARM64_Q28, .Reg: AArch64::Q28},
234 {.CVReg: codeview::RegisterId::ARM64_Q29, .Reg: AArch64::Q29},
235 {.CVReg: codeview::RegisterId::ARM64_Q30, .Reg: AArch64::Q30},
236 {.CVReg: codeview::RegisterId::ARM64_Q31, .Reg: AArch64::Q31},
237 {.CVReg: codeview::RegisterId::ARM64_B0, .Reg: AArch64::B0},
238 {.CVReg: codeview::RegisterId::ARM64_B1, .Reg: AArch64::B1},
239 {.CVReg: codeview::RegisterId::ARM64_B2, .Reg: AArch64::B2},
240 {.CVReg: codeview::RegisterId::ARM64_B3, .Reg: AArch64::B3},
241 {.CVReg: codeview::RegisterId::ARM64_B4, .Reg: AArch64::B4},
242 {.CVReg: codeview::RegisterId::ARM64_B5, .Reg: AArch64::B5},
243 {.CVReg: codeview::RegisterId::ARM64_B6, .Reg: AArch64::B6},
244 {.CVReg: codeview::RegisterId::ARM64_B7, .Reg: AArch64::B7},
245 {.CVReg: codeview::RegisterId::ARM64_B8, .Reg: AArch64::B8},
246 {.CVReg: codeview::RegisterId::ARM64_B9, .Reg: AArch64::B9},
247 {.CVReg: codeview::RegisterId::ARM64_B10, .Reg: AArch64::B10},
248 {.CVReg: codeview::RegisterId::ARM64_B11, .Reg: AArch64::B11},
249 {.CVReg: codeview::RegisterId::ARM64_B12, .Reg: AArch64::B12},
250 {.CVReg: codeview::RegisterId::ARM64_B13, .Reg: AArch64::B13},
251 {.CVReg: codeview::RegisterId::ARM64_B14, .Reg: AArch64::B14},
252 {.CVReg: codeview::RegisterId::ARM64_B15, .Reg: AArch64::B15},
253 {.CVReg: codeview::RegisterId::ARM64_B16, .Reg: AArch64::B16},
254 {.CVReg: codeview::RegisterId::ARM64_B17, .Reg: AArch64::B17},
255 {.CVReg: codeview::RegisterId::ARM64_B18, .Reg: AArch64::B18},
256 {.CVReg: codeview::RegisterId::ARM64_B19, .Reg: AArch64::B19},
257 {.CVReg: codeview::RegisterId::ARM64_B20, .Reg: AArch64::B20},
258 {.CVReg: codeview::RegisterId::ARM64_B21, .Reg: AArch64::B21},
259 {.CVReg: codeview::RegisterId::ARM64_B22, .Reg: AArch64::B22},
260 {.CVReg: codeview::RegisterId::ARM64_B23, .Reg: AArch64::B23},
261 {.CVReg: codeview::RegisterId::ARM64_B24, .Reg: AArch64::B24},
262 {.CVReg: codeview::RegisterId::ARM64_B25, .Reg: AArch64::B25},
263 {.CVReg: codeview::RegisterId::ARM64_B26, .Reg: AArch64::B26},
264 {.CVReg: codeview::RegisterId::ARM64_B27, .Reg: AArch64::B27},
265 {.CVReg: codeview::RegisterId::ARM64_B28, .Reg: AArch64::B28},
266 {.CVReg: codeview::RegisterId::ARM64_B29, .Reg: AArch64::B29},
267 {.CVReg: codeview::RegisterId::ARM64_B30, .Reg: AArch64::B30},
268 {.CVReg: codeview::RegisterId::ARM64_B31, .Reg: AArch64::B31},
269 {.CVReg: codeview::RegisterId::ARM64_H0, .Reg: AArch64::H0},
270 {.CVReg: codeview::RegisterId::ARM64_H1, .Reg: AArch64::H1},
271 {.CVReg: codeview::RegisterId::ARM64_H2, .Reg: AArch64::H2},
272 {.CVReg: codeview::RegisterId::ARM64_H3, .Reg: AArch64::H3},
273 {.CVReg: codeview::RegisterId::ARM64_H4, .Reg: AArch64::H4},
274 {.CVReg: codeview::RegisterId::ARM64_H5, .Reg: AArch64::H5},
275 {.CVReg: codeview::RegisterId::ARM64_H6, .Reg: AArch64::H6},
276 {.CVReg: codeview::RegisterId::ARM64_H7, .Reg: AArch64::H7},
277 {.CVReg: codeview::RegisterId::ARM64_H8, .Reg: AArch64::H8},
278 {.CVReg: codeview::RegisterId::ARM64_H9, .Reg: AArch64::H9},
279 {.CVReg: codeview::RegisterId::ARM64_H10, .Reg: AArch64::H10},
280 {.CVReg: codeview::RegisterId::ARM64_H11, .Reg: AArch64::H11},
281 {.CVReg: codeview::RegisterId::ARM64_H12, .Reg: AArch64::H12},
282 {.CVReg: codeview::RegisterId::ARM64_H13, .Reg: AArch64::H13},
283 {.CVReg: codeview::RegisterId::ARM64_H14, .Reg: AArch64::H14},
284 {.CVReg: codeview::RegisterId::ARM64_H15, .Reg: AArch64::H15},
285 {.CVReg: codeview::RegisterId::ARM64_H16, .Reg: AArch64::H16},
286 {.CVReg: codeview::RegisterId::ARM64_H17, .Reg: AArch64::H17},
287 {.CVReg: codeview::RegisterId::ARM64_H18, .Reg: AArch64::H18},
288 {.CVReg: codeview::RegisterId::ARM64_H19, .Reg: AArch64::H19},
289 {.CVReg: codeview::RegisterId::ARM64_H20, .Reg: AArch64::H20},
290 {.CVReg: codeview::RegisterId::ARM64_H21, .Reg: AArch64::H21},
291 {.CVReg: codeview::RegisterId::ARM64_H22, .Reg: AArch64::H22},
292 {.CVReg: codeview::RegisterId::ARM64_H23, .Reg: AArch64::H23},
293 {.CVReg: codeview::RegisterId::ARM64_H24, .Reg: AArch64::H24},
294 {.CVReg: codeview::RegisterId::ARM64_H25, .Reg: AArch64::H25},
295 {.CVReg: codeview::RegisterId::ARM64_H26, .Reg: AArch64::H26},
296 {.CVReg: codeview::RegisterId::ARM64_H27, .Reg: AArch64::H27},
297 {.CVReg: codeview::RegisterId::ARM64_H28, .Reg: AArch64::H28},
298 {.CVReg: codeview::RegisterId::ARM64_H29, .Reg: AArch64::H29},
299 {.CVReg: codeview::RegisterId::ARM64_H30, .Reg: AArch64::H30},
300 {.CVReg: codeview::RegisterId::ARM64_H31, .Reg: AArch64::H31},
301 };
302 for (const auto &I : RegMap)
303 MRI->mapLLVMRegToCVReg(LLVMReg: I.Reg, CVReg: static_cast<int>(I.CVReg));
304}
305
306bool AArch64_MC::isHForm(const MCInst &MI, const MCInstrInfo *MCII) {
307 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID];
308 return llvm::any_of(Range: MI, P: [&](const MCOperand &Op) {
309 return Op.isReg() && FPR16.contains(Reg: Op.getReg());
310 });
311}
312
313bool AArch64_MC::isQForm(const MCInst &MI, const MCInstrInfo *MCII) {
314 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID];
315 return llvm::any_of(Range: MI, P: [&](const MCOperand &Op) {
316 return Op.isReg() && FPR128.contains(Reg: Op.getReg());
317 });
318}
319
320bool AArch64_MC::isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII) {
321 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID];
322 const auto &FPR64 = AArch64MCRegisterClasses[AArch64::FPR64RegClassID];
323 const auto &FPR32 = AArch64MCRegisterClasses[AArch64::FPR32RegClassID];
324 const auto &FPR16 = AArch64MCRegisterClasses[AArch64::FPR16RegClassID];
325 const auto &FPR8 = AArch64MCRegisterClasses[AArch64::FPR8RegClassID];
326
327 auto IsFPR = [&](const MCOperand &Op) {
328 if (!Op.isReg())
329 return false;
330 auto Reg = Op.getReg();
331 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) ||
332 FPR16.contains(Reg) || FPR8.contains(Reg);
333 };
334
335 return llvm::any_of(Range: MI, P: IsFPR);
336}
337
338static MCRegisterInfo *createAArch64MCRegisterInfo(const Triple &Triple) {
339 MCRegisterInfo *X = new MCRegisterInfo();
340 InitAArch64MCRegisterInfo(RI: X, RA: AArch64::LR);
341 AArch64_MC::initLLVMToCVRegMapping(MRI: X);
342 return X;
343}
344
345static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI,
346 const Triple &TheTriple,
347 const MCTargetOptions &Options) {
348 MCAsmInfo *MAI;
349 if (TheTriple.isOSBinFormatMachO())
350 MAI = new AArch64MCAsmInfoDarwin(TheTriple.getArch() == Triple::aarch64_32);
351 else if (TheTriple.isWindowsMSVCEnvironment())
352 MAI = new AArch64MCAsmInfoMicrosoftCOFF();
353 else if (TheTriple.isOSBinFormatCOFF())
354 MAI = new AArch64MCAsmInfoGNUCOFF();
355 else {
356 assert(TheTriple.isOSBinFormatELF() && "Invalid target");
357 MAI = new AArch64MCAsmInfoELF(TheTriple);
358 }
359
360 // Initial state of the frame pointer is SP.
361 unsigned Reg = MRI.getDwarfRegNum(RegNum: AArch64::SP, isEH: true);
362 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(L: nullptr, Register: Reg, Offset: 0);
363 MAI->addInitialFrameState(Inst);
364
365 return MAI;
366}
367
368static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
369 unsigned SyntaxVariant,
370 const MCAsmInfo &MAI,
371 const MCInstrInfo &MII,
372 const MCRegisterInfo &MRI) {
373 if (SyntaxVariant == 0)
374 return new AArch64InstPrinter(MAI, MII, MRI);
375 if (SyntaxVariant == 1)
376 return new AArch64AppleInstPrinter(MAI, MII, MRI);
377
378 return nullptr;
379}
380
381static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
382 std::unique_ptr<MCAsmBackend> &&TAB,
383 std::unique_ptr<MCObjectWriter> &&OW,
384 std::unique_ptr<MCCodeEmitter> &&Emitter) {
385 return createAArch64ELFStreamer(Context&: Ctx, TAB: std::move(TAB), OW: std::move(OW),
386 Emitter: std::move(Emitter));
387}
388
389static MCStreamer *
390createMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
391 std::unique_ptr<MCObjectWriter> &&OW,
392 std::unique_ptr<MCCodeEmitter> &&Emitter) {
393 return createMachOStreamer(Ctx, TAB: std::move(TAB), OW: std::move(OW),
394 CE: std::move(Emitter), /*ignore=*/DWARFMustBeAtTheEnd: false,
395 /*LabelSections*/ true);
396}
397
398static MCStreamer *
399createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
400 std::unique_ptr<MCObjectWriter> &&OW,
401 std::unique_ptr<MCCodeEmitter> &&Emitter) {
402 return createAArch64WinCOFFStreamer(Context&: Ctx, TAB: std::move(TAB), OW: std::move(OW),
403 Emitter: std::move(Emitter));
404}
405
406namespace {
407
408class AArch64MCInstrAnalysis : public MCInstrAnalysis {
409public:
410 AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
411
412 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
413 uint64_t &Target) const override {
414 // Search for a PC-relative argument.
415 // This will handle instructions like bcc (where the first argument is the
416 // condition code) and cbz (where it is a register).
417 const auto &Desc = Info->get(Opcode: Inst.getOpcode());
418 for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) {
419 if (Desc.operands()[i].OperandType == MCOI::OPERAND_PCREL) {
420 int64_t Imm = Inst.getOperand(i).getImm();
421 if (Inst.getOpcode() == AArch64::ADR)
422 Target = Addr + Imm;
423 else if (Inst.getOpcode() == AArch64::ADRP)
424 Target = (Addr & -4096) + Imm * 4096;
425 else
426 Target = Addr + Imm * 4;
427 return true;
428 }
429 }
430 return false;
431 }
432
433 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
434 APInt &Mask) const override {
435 const MCInstrDesc &Desc = Info->get(Opcode: Inst.getOpcode());
436 unsigned NumDefs = Desc.getNumDefs();
437 unsigned NumImplicitDefs = Desc.implicit_defs().size();
438 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
439 "Unexpected number of bits in the mask!");
440 // 32-bit General Purpose Register class.
441 const MCRegisterClass &GPR32RC = MRI.getRegClass(i: AArch64::GPR32RegClassID);
442 // Floating Point Register classes.
443 const MCRegisterClass &FPR8RC = MRI.getRegClass(i: AArch64::FPR8RegClassID);
444 const MCRegisterClass &FPR16RC = MRI.getRegClass(i: AArch64::FPR16RegClassID);
445 const MCRegisterClass &FPR32RC = MRI.getRegClass(i: AArch64::FPR32RegClassID);
446 const MCRegisterClass &FPR64RC = MRI.getRegClass(i: AArch64::FPR64RegClassID);
447 const MCRegisterClass &FPR128RC =
448 MRI.getRegClass(i: AArch64::FPR128RegClassID);
449
450 auto ClearsSuperReg = [=](unsigned RegID) {
451 // An update to the lower 32 bits of a 64 bit integer register is
452 // architecturally defined to zero extend the upper 32 bits on a write.
453 if (GPR32RC.contains(Reg: RegID))
454 return true;
455 // SIMD&FP instructions operating on scalar data only acccess the lower
456 // bits of a register, the upper bits are zero extended on a write. For
457 // SIMD vector registers smaller than 128-bits, the upper 64-bits of the
458 // register are zero extended on a write.
459 // When VL is higher than 128 bits, any write to a SIMD&FP register sets
460 // bits higher than 128 to zero.
461 return FPR8RC.contains(Reg: RegID) || FPR16RC.contains(Reg: RegID) ||
462 FPR32RC.contains(Reg: RegID) || FPR64RC.contains(Reg: RegID) ||
463 FPR128RC.contains(Reg: RegID);
464 };
465
466 Mask.clearAllBits();
467 for (unsigned I = 0, E = NumDefs; I < E; ++I) {
468 const MCOperand &Op = Inst.getOperand(i: I);
469 if (ClearsSuperReg(Op.getReg()))
470 Mask.setBit(I);
471 }
472
473 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
474 const MCPhysReg Reg = Desc.implicit_defs()[I];
475 if (ClearsSuperReg(Reg))
476 Mask.setBit(NumDefs + I);
477 }
478
479 return Mask.getBoolValue();
480 }
481
482 std::vector<std::pair<uint64_t, uint64_t>>
483 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
484 const Triple &TargetTriple) const override {
485 // Do a lightweight parsing of PLT entries.
486 std::vector<std::pair<uint64_t, uint64_t>> Result;
487 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End;
488 Byte += 4) {
489 uint32_t Insn = support::endian::read32le(P: PltContents.data() + Byte);
490 uint64_t Off = 0;
491 // Check for optional bti c that prefixes adrp in BTI enabled entries
492 if (Insn == 0xd503245f) {
493 Off = 4;
494 Insn = support::endian::read32le(P: PltContents.data() + Byte + Off);
495 }
496 // Check for adrp.
497 if ((Insn & 0x9f000000) != 0x90000000)
498 continue;
499 Off += 4;
500 uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) +
501 (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
502 uint32_t Insn2 =
503 support::endian::read32le(P: PltContents.data() + Byte + Off);
504 // Check for: ldr Xt, [Xn, #pimm].
505 if (Insn2 >> 22 == 0x3e5) {
506 Imm += ((Insn2 >> 10) & 0xfff) << 3;
507 Result.push_back(x: std::make_pair(x: PltSectionVA + Byte, y&: Imm));
508 Byte += 4;
509 }
510 }
511 return Result;
512 }
513};
514
515} // end anonymous namespace
516
517static MCInstrAnalysis *createAArch64InstrAnalysis(const MCInstrInfo *Info) {
518 return new AArch64MCInstrAnalysis(Info);
519}
520
521// Force static initialization.
522extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64TargetMC() {
523 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64beTarget(),
524 &getTheAArch64_32Target(), &getTheARM64Target(),
525 &getTheARM64_32Target()}) {
526 // Register the MC asm info.
527 RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo);
528
529 // Register the MC instruction info.
530 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createAArch64MCInstrInfo);
531
532 // Register the MC register info.
533 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createAArch64MCRegisterInfo);
534
535 // Register the MC subtarget info.
536 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createAArch64MCSubtargetInfo);
537
538 // Register the MC instruction analyzer.
539 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createAArch64InstrAnalysis);
540
541 // Register the MC Code Emitter
542 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createAArch64MCCodeEmitter);
543
544 // Register the obj streamers.
545 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createELFStreamer);
546 TargetRegistry::RegisterMachOStreamer(T&: *T, Fn: createMachOStreamer);
547 TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createWinCOFFStreamer);
548
549 // Register the obj target streamer.
550 TargetRegistry::RegisterObjectTargetStreamer(
551 T&: *T, Fn: createAArch64ObjectTargetStreamer);
552
553 // Register the asm streamer.
554 TargetRegistry::RegisterAsmTargetStreamer(T&: *T,
555 Fn: createAArch64AsmTargetStreamer);
556 // Register the null streamer.
557 TargetRegistry::RegisterNullTargetStreamer(T&: *T,
558 Fn: createAArch64NullTargetStreamer);
559
560 // Register the MCInstPrinter.
561 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createAArch64MCInstPrinter);
562 }
563
564 // Register the asm backend.
565 for (Target *T : {&getTheAArch64leTarget(), &getTheAArch64_32Target(),
566 &getTheARM64Target(), &getTheARM64_32Target()})
567 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createAArch64leAsmBackend);
568 TargetRegistry::RegisterMCAsmBackend(T&: getTheAArch64beTarget(),
569 Fn: createAArch64beAsmBackend);
570}
571