1 | //===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===// |
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2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | /// \file |
10 | /// Add implicit use of exec to vector register copies. |
11 | /// |
12 | //===----------------------------------------------------------------------===// |
13 | |
14 | #include "AMDGPU.h" |
15 | #include "GCNSubtarget.h" |
16 | #include "MCTargetDesc/AMDGPUMCTargetDesc.h" |
17 | #include "llvm/CodeGen/MachineFunctionPass.h" |
18 | |
19 | using namespace llvm; |
20 | |
21 | #define DEBUG_TYPE "si-fix-vgpr-copies" |
22 | |
23 | namespace { |
24 | |
25 | class SIFixVGPRCopies : public MachineFunctionPass { |
26 | public: |
27 | static char ID; |
28 | |
29 | public: |
30 | SIFixVGPRCopies() : MachineFunctionPass(ID) { |
31 | initializeSIFixVGPRCopiesPass(*PassRegistry::getPassRegistry()); |
32 | } |
33 | |
34 | void getAnalysisUsage(AnalysisUsage &AU) const override { |
35 | AU.setPreservesAll(); |
36 | MachineFunctionPass::getAnalysisUsage(AU); |
37 | } |
38 | |
39 | bool runOnMachineFunction(MachineFunction &MF) override; |
40 | |
41 | StringRef getPassName() const override { return "SI Fix VGPR copies"; } |
42 | }; |
43 | |
44 | } // End anonymous namespace. |
45 | |
46 | INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false) |
47 | |
48 | char SIFixVGPRCopies::ID = 0; |
49 | |
50 | char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID; |
51 | |
52 | bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) { |
53 | const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); |
54 | const SIRegisterInfo *TRI = ST.getRegisterInfo(); |
55 | const SIInstrInfo *TII = ST.getInstrInfo(); |
56 | bool Changed = false; |
57 | |
58 | for (MachineBasicBlock &MBB : MF) { |
59 | for (MachineInstr &MI : MBB) { |
60 | switch (MI.getOpcode()) { |
61 | case AMDGPU::COPY: |
62 | if (TII->isVGPRCopy(MI) && !MI.readsRegister(Reg: AMDGPU::EXEC, TRI)) { |
63 | MI.addOperand(MF, |
64 | Op: MachineOperand::CreateReg(Reg: AMDGPU::EXEC, isDef: false, isImp: true)); |
65 | LLVM_DEBUG(dbgs() << "Add exec use to "<< MI); |
66 | Changed = true; |
67 | } |
68 | break; |
69 | default: |
70 | break; |
71 | } |
72 | } |
73 | } |
74 | |
75 | return Changed; |
76 | } |
77 |