1//===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips32/64 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
15
16#include "MipsInstrInfo.h"
17#include "MipsSERegisterInfo.h"
18
19namespace llvm {
20
21class MipsSEInstrInfo : public MipsInstrInfo {
22 const MipsSERegisterInfo RI;
23
24public:
25 explicit MipsSEInstrInfo(const MipsSubtarget &STI);
26
27 const MipsRegisterInfo &getRegisterInfo() const override;
28
29 /// isLoadFromStackSlot - If the specified machine instruction is a direct
30 /// load from a stack slot, return the virtual or physical register number of
31 /// the destination along with the FrameIndex of the loaded stack slot. If
32 /// not, return 0. This predicate must return 0 if the instruction has
33 /// any side effects other than loading from the stack slot.
34 Register isLoadFromStackSlot(const MachineInstr &MI,
35 int &FrameIndex) const override;
36
37 /// isStoreToStackSlot - If the specified machine instruction is a direct
38 /// store to a stack slot, return the virtual or physical register number of
39 /// the source reg along with the FrameIndex of the loaded stack slot. If
40 /// not, return 0. This predicate must return 0 if the instruction has
41 /// any side effects other than storing to the stack slot.
42 Register isStoreToStackSlot(const MachineInstr &MI,
43 int &FrameIndex) const override;
44
45 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
46 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
47 bool KillSrc) const override;
48
49 void storeRegToStack(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MI,
51 Register SrcReg, bool isKill, int FrameIndex,
52 const TargetRegisterClass *RC,
53 const TargetRegisterInfo *TRI,
54 int64_t Offset) const override;
55
56 void loadRegFromStack(MachineBasicBlock &MBB,
57 MachineBasicBlock::iterator MI,
58 Register DestReg, int FrameIndex,
59 const TargetRegisterClass *RC,
60 const TargetRegisterInfo *TRI,
61 int64_t Offset) const override;
62
63 bool expandPostRAPseudo(MachineInstr &MI) const override;
64
65 bool isBranchWithImm(unsigned Opc) const override;
66
67 unsigned getOppositeBranchOpc(unsigned Opc) const override;
68
69 /// Adjust SP by Amount bytes.
70 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator I) const override;
72
73 /// Emit a series of instructions to load an immediate. If NewImm is a
74 /// non-NULL parameter, the last instruction is not emitted, but instead
75 /// its immediate operand is returned in NewImm.
76 unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator II, const DebugLoc &DL,
78 unsigned *NewImm) const;
79
80protected:
81 /// If the specific machine instruction is a instruction that moves/copies
82 /// value from one register to another register return destination and source
83 /// registers as machine operands.
84 std::optional<DestSourcePair>
85 isCopyInstrImpl(const MachineInstr &MI) const override;
86
87private:
88 unsigned getAnalyzableBrOpc(unsigned Opc) const override;
89
90 void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
91
92 void expandERet(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
93
94 std::pair<bool, bool> compareOpndSize(unsigned Opc,
95 const MachineFunction &MF) const;
96
97 void expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
98 unsigned NewOpc) const;
99
100 void expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
101 unsigned LoOpc, unsigned HiOpc,
102 bool HasExplicitDef) const;
103
104 /// Expand pseudo Int-to-FP conversion instructions.
105 ///
106 /// For example, the following pseudo instruction
107 /// PseudoCVT_D32_W D2, A5
108 /// gets expanded into these two instructions:
109 /// MTC1 F4, A5
110 /// CVT_D32_W D2, F4
111 ///
112 /// We do this expansion post-RA to avoid inserting a floating point copy
113 /// instruction between MTC1 and CVT_D32_W.
114 void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
115 unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
116
117 void expandExtractElementF64(MachineBasicBlock &MBB,
118 MachineBasicBlock::iterator I, bool isMicroMips,
119 bool FP64) const;
120 void expandBuildPairF64(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator I, bool isMicroMips,
122 bool FP64) const;
123 void expandEhReturn(MachineBasicBlock &MBB,
124 MachineBasicBlock::iterator I) const;
125};
126
127}
128
129#endif
130