1//===- PPCLegalizerInfo.h ----------------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the Machinelegalizer class for PowerPC
10//===----------------------------------------------------------------------===//
11
12#include "PPCLegalizerInfo.h"
13#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
14#include "llvm/Support/Debug.h"
15
16#define DEBUG_TYPE "ppc-legalinfo"
17
18using namespace llvm;
19using namespace LegalizeActions;
20using namespace LegalizeMutations;
21using namespace LegalityPredicates;
22
23static LegalityPredicate isRegisterType(unsigned TypeIdx) {
24 return [=](const LegalityQuery &Query) {
25 const LLT QueryTy = Query.Types[TypeIdx];
26 unsigned TypeSize = QueryTy.getSizeInBits();
27
28 if (TypeSize % 32 == 1 || TypeSize > 128)
29 return false;
30
31 // Check if this is a legal PowerPC vector type.
32 if (QueryTy.isVector()) {
33 const int EltSize = QueryTy.getElementType().getSizeInBits();
34 return (EltSize == 8 || EltSize == 16 || EltSize == 32 || EltSize == 64);
35 }
36
37 return true;
38 };
39}
40
41PPCLegalizerInfo::PPCLegalizerInfo(const PPCSubtarget &ST) {
42 using namespace TargetOpcode;
43 const LLT P0 = LLT::pointer(AddressSpace: 0, SizeInBits: 64);
44 const LLT S1 = LLT::scalar(SizeInBits: 1);
45 const LLT S8 = LLT::scalar(SizeInBits: 8);
46 const LLT S16 = LLT::scalar(SizeInBits: 16);
47 const LLT S32 = LLT::scalar(SizeInBits: 32);
48 const LLT S64 = LLT::scalar(SizeInBits: 64);
49 const LLT V16S8 = LLT::fixed_vector(NumElements: 16, ScalarSizeInBits: 8);
50 const LLT V8S16 = LLT::fixed_vector(NumElements: 8, ScalarSizeInBits: 16);
51 const LLT V4S32 = LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 32);
52 const LLT V2S64 = LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 64);
53 getActionDefinitionsBuilder(Opcode: G_IMPLICIT_DEF).legalFor(Types: {S64});
54 getActionDefinitionsBuilder(Opcode: G_CONSTANT)
55 .legalFor(Types: {S32, S64})
56 .clampScalar(TypeIdx: 0, MinTy: S64, MaxTy: S64);
57 getActionDefinitionsBuilder(Opcodes: {G_ZEXT, G_SEXT, G_ANYEXT})
58 .legalForCartesianProduct(Types0: {S64}, Types1: {S1, S8, S16, S32})
59 .clampScalar(TypeIdx: 0, MinTy: S64, MaxTy: S64);
60 getActionDefinitionsBuilder(Opcodes: {G_AND, G_OR, G_XOR})
61 .legalFor(Types: {S64, V4S32})
62 .clampScalar(TypeIdx: 0, MinTy: S64, MaxTy: S64)
63 .bitcastIf(Predicate: typeIsNot(TypeIdx: 0, Type: V4S32), Mutation: changeTo(TypeIdx: 0, Ty: V4S32));
64 getActionDefinitionsBuilder(Opcodes: {G_ADD, G_SUB})
65 .legalFor(Types: {S64, V16S8, V8S16, V4S32, V2S64})
66 .clampScalar(TypeIdx: 0, MinTy: S64, MaxTy: S64);
67 getActionDefinitionsBuilder(Opcode: G_BITCAST)
68 .legalIf(Predicate: all(P0: isRegisterType(TypeIdx: 0), P1: isRegisterType(TypeIdx: 1)))
69 .lower();
70
71 getActionDefinitionsBuilder(Opcodes: {G_FADD, G_FSUB, G_FMUL, G_FDIV})
72 .legalFor(Types: {S32, S64, V4S32, V2S64});
73
74 getActionDefinitionsBuilder(Opcode: G_FCMP).legalForCartesianProduct(Types0: {S1},
75 Types1: {S32, S64});
76
77 getActionDefinitionsBuilder(Opcodes: {G_FPTOSI, G_FPTOUI})
78 .legalForCartesianProduct(Types0: {S64}, Types1: {S32, S64});
79
80 getActionDefinitionsBuilder(Opcodes: {G_SITOFP, G_UITOFP})
81 .legalForCartesianProduct(Types0: {S32, S64}, Types1: {S64});
82
83 getActionDefinitionsBuilder(Opcodes: {G_LOAD, G_STORE})
84 .legalForTypesWithMemDesc(TypesAndMemDesc: {{.Type0: S64, .Type1: P0, .MemTy: S64, .Align: 8}, {.Type0: S32, .Type1: P0, .MemTy: S32, .Align: 4}});
85
86 getActionDefinitionsBuilder(Opcode: G_FCONSTANT).lowerFor(Types: {S32, S64});
87 getActionDefinitionsBuilder(Opcode: G_CONSTANT_POOL).legalFor(Types: {P0});
88
89 getLegacyLegalizerInfo().computeTables();
90}
91