1//===-- RISCVAsmBackend.h - RISC-V Assembler Backend ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
10#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
11
12#include "MCTargetDesc/RISCVBaseInfo.h"
13#include "MCTargetDesc/RISCVFixupKinds.h"
14#include "MCTargetDesc/RISCVMCTargetDesc.h"
15#include "llvm/MC/MCAsmBackend.h"
16#include "llvm/MC/MCFixupKindInfo.h"
17#include "llvm/MC/MCSubtargetInfo.h"
18
19namespace llvm {
20class MCAssembler;
21class MCObjectTargetWriter;
22class raw_ostream;
23
24class RISCVAsmBackend : public MCAsmBackend {
25 const MCSubtargetInfo &STI;
26 uint8_t OSABI;
27 bool Is64Bit;
28 bool ForceRelocs = false;
29 const MCTargetOptions &TargetOptions;
30
31public:
32 RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
33 const MCTargetOptions &Options)
34 : MCAsmBackend(llvm::endianness::little, RISCV::fixup_riscv_relax),
35 STI(STI), OSABI(OSABI), Is64Bit(Is64Bit), TargetOptions(Options) {
36 RISCVFeatures::validate(TT: STI.getTargetTriple(), FeatureBits: STI.getFeatureBits());
37 }
38 ~RISCVAsmBackend() override = default;
39
40 void setForceRelocs() { ForceRelocs = true; }
41
42 // Return Size with extra Nop Bytes for alignment directive in code section.
43 bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF,
44 unsigned &Size) override;
45
46 // Insert target specific fixup type for alignment directive in code section.
47 bool shouldInsertFixupForCodeAlign(MCAssembler &Asm,
48 MCAlignFragment &AF) override;
49
50 bool evaluateTargetFixup(const MCAssembler &Asm, const MCFixup &Fixup,
51 const MCFragment *DF, const MCValue &Target,
52 const MCSubtargetInfo *STI, uint64_t &Value,
53 bool &WasForced) override;
54
55 bool handleAddSubRelocations(const MCAssembler &Asm, const MCFragment &F,
56 const MCFixup &Fixup, const MCValue &Target,
57 uint64_t &FixedValue) const override;
58
59 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
60 const MCValue &Target, MutableArrayRef<char> Data,
61 uint64_t Value, bool IsResolved,
62 const MCSubtargetInfo *STI) const override;
63
64 std::unique_ptr<MCObjectTargetWriter>
65 createObjectTargetWriter() const override;
66
67 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
68 const MCValue &Target,
69 const MCSubtargetInfo *STI) override;
70
71 bool fixupNeedsRelaxationAdvanced(const MCAssembler &Asm,
72 const MCFixup &Fixup, bool Resolved,
73 uint64_t Value,
74 const MCRelaxableFragment *DF,
75 const bool WasForced) const override;
76
77 unsigned getNumFixupKinds() const override {
78 return RISCV::NumTargetFixupKinds;
79 }
80
81 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
82
83 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
84
85 bool mayNeedRelaxation(const MCInst &Inst,
86 const MCSubtargetInfo &STI) const override;
87 unsigned getRelaxedOpcode(unsigned Op) const;
88
89 void relaxInstruction(MCInst &Inst,
90 const MCSubtargetInfo &STI) const override;
91
92 bool relaxDwarfLineAddr(const MCAssembler &Asm, MCDwarfLineAddrFragment &DF,
93 bool &WasRelaxed) const override;
94 bool relaxDwarfCFA(const MCAssembler &Asm, MCDwarfCallFrameFragment &DF,
95 bool &WasRelaxed) const override;
96 std::pair<bool, bool> relaxLEB128(const MCAssembler &Asm, MCLEBFragment &LF,
97 int64_t &Value) const override;
98
99 bool writeNopData(raw_ostream &OS, uint64_t Count,
100 const MCSubtargetInfo *STI) const override;
101
102 const MCTargetOptions &getTargetOptions() const { return TargetOptions; }
103};
104}
105
106#endif
107