1//=- RISCVMachineFunctionInfo.cpp - RISC-V machine function info --*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares RISCV-specific per-machine-function information.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVMachineFunctionInfo.h"
14
15using namespace llvm;
16
17yaml::RISCVMachineFunctionInfo::RISCVMachineFunctionInfo(
18 const llvm::RISCVMachineFunctionInfo &MFI)
19 : VarArgsFrameIndex(MFI.getVarArgsFrameIndex()),
20 VarArgsSaveSize(MFI.getVarArgsSaveSize()) {}
21
22MachineFunctionInfo *RISCVMachineFunctionInfo::clone(
23 BumpPtrAllocator &Allocator, MachineFunction &DestMF,
24 const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
25 const {
26 return DestMF.cloneInfo<RISCVMachineFunctionInfo>(Old: *this);
27}
28
29void yaml::RISCVMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
30 MappingTraits<RISCVMachineFunctionInfo>::mapping(YamlIO, MFI&: *this);
31}
32
33void RISCVMachineFunctionInfo::initializeBaseYamlFields(
34 const yaml::RISCVMachineFunctionInfo &YamlMFI) {
35 VarArgsFrameIndex = YamlMFI.VarArgsFrameIndex;
36 VarArgsSaveSize = YamlMFI.VarArgsSaveSize;
37}
38
39void RISCVMachineFunctionInfo::addSExt32Register(Register Reg) {
40 SExt32Registers.push_back(Elt: Reg);
41}
42
43bool RISCVMachineFunctionInfo::isSExt32Register(Register Reg) const {
44 return is_contained(Range: SExt32Registers, Element: Reg);
45}
46