1//===- X86GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file defines all the static objects used by X86RegisterBankInfo.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#ifdef GET_TARGET_REGBANK_INFO_IMPL
14RegisterBankInfo::PartialMapping X86GenRegisterBankInfo::PartMappings[]{
15 /* StartIdx, Length, RegBank */
16 // GPR value
17 {0, 8, X86::GPRRegBank}, // :0
18 {0, 16, X86::GPRRegBank}, // :1
19 {0, 32, X86::GPRRegBank}, // :2
20 {0, 64, X86::GPRRegBank}, // :3
21 // FR32/64 , xmm registers
22 {0, 32, X86::VECRRegBank}, // :4
23 {0, 64, X86::VECRRegBank}, // :5
24 // VR128/256/512
25 {0, 128, X86::VECRRegBank}, // :6
26 {0, 256, X86::VECRRegBank}, // :7
27 {0, 512, X86::VECRRegBank}, // :8
28 // RFP32/64/80
29 {0, 32, X86::PSRRegBank}, // :9
30 {0, 64, X86::PSRRegBank}, // :10
31 {0, 80, X86::PSRRegBank}, // :11
32};
33#endif // GET_TARGET_REGBANK_INFO_IMPL
34
35#ifdef GET_TARGET_REGBANK_INFO_CLASS
36enum PartialMappingIdx {
37 PMI_None = -1,
38 PMI_GPR8,
39 PMI_GPR16,
40 PMI_GPR32,
41 PMI_GPR64,
42 PMI_FP32,
43 PMI_FP64,
44 PMI_VEC128,
45 PMI_VEC256,
46 PMI_VEC512,
47 PMI_PSR32,
48 PMI_PSR64,
49 PMI_PSR80
50};
51#endif // GET_TARGET_REGBANK_INFO_CLASS
52
53#ifdef GET_TARGET_REGBANK_INFO_IMPL
54#define INSTR_3OP(INFO) INFO, INFO, INFO,
55#define BREAKDOWN(INDEX, NUM) \
56 { &X86GenRegisterBankInfo::PartMappings[INDEX], NUM }
57// ValueMappings.
58RegisterBankInfo::ValueMapping X86GenRegisterBankInfo::ValMappings[]{
59 /* BreakDown, NumBreakDowns */
60 // 3-operands instructions (all binary operations should end up with one of
61 // those mapping).
62 INSTR_3OP(BREAKDOWN(PMI_GPR8, 1)) // 0: GPR_8
63 INSTR_3OP(BREAKDOWN(PMI_GPR16, 1)) // 3: GPR_16
64 INSTR_3OP(BREAKDOWN(PMI_GPR32, 1)) // 6: GPR_32
65 INSTR_3OP(BREAKDOWN(PMI_GPR64, 1)) // 9: GPR_64
66 INSTR_3OP(BREAKDOWN(PMI_FP32, 1)) // 12: Fp32
67 INSTR_3OP(BREAKDOWN(PMI_FP64, 1)) // 15: Fp64
68 INSTR_3OP(BREAKDOWN(PMI_VEC128, 1)) // 18: Vec128
69 INSTR_3OP(BREAKDOWN(PMI_VEC256, 1)) // 21: Vec256
70 INSTR_3OP(BREAKDOWN(PMI_VEC512, 1)) // 24: Vec512
71 INSTR_3OP(BREAKDOWN(PMI_PSR32, 1)) // 25: Rfp32
72 INSTR_3OP(BREAKDOWN(PMI_PSR64, 1)) // 26: Rfp64
73 INSTR_3OP(BREAKDOWN(PMI_PSR80, 1)) // 27: Rfp80
74};
75#undef INSTR_3OP
76#undef BREAKDOWN
77#endif // GET_TARGET_REGBANK_INFO_IMPL
78
79#ifdef GET_TARGET_REGBANK_INFO_CLASS
80enum ValueMappingIdx {
81 VMI_None = -1,
82 VMI_3OpsGpr8Idx = PMI_GPR8 * 3,
83 VMI_3OpsGpr16Idx = PMI_GPR16 * 3,
84 VMI_3OpsGpr32Idx = PMI_GPR32 * 3,
85 VMI_3OpsGpr64Idx = PMI_GPR64 * 3,
86 VMI_3OpsFp32Idx = PMI_FP32 * 3,
87 VMI_3OpsFp64Idx = PMI_FP64 * 3,
88 VMI_3OpsVec128Idx = PMI_VEC128 * 3,
89 VMI_3OpsVec256Idx = PMI_VEC256 * 3,
90 VMI_3OpsVec512Idx = PMI_VEC512 * 3,
91 VMI_3OpsPs32Idx = PMI_PSR32 * 3,
92 VMI_3OpsPs64Idx = PMI_PSR64 * 3,
93 VMI_3OpsPs80Idx = PMI_PSR80 * 3,
94};
95#undef GET_TARGET_REGBANK_INFO_CLASS
96#endif // GET_TARGET_REGBANK_INFO_CLASS
97
98#ifdef GET_TARGET_REGBANK_INFO_IMPL
99#undef GET_TARGET_REGBANK_INFO_IMPL
100const RegisterBankInfo::ValueMapping *
101X86GenRegisterBankInfo::getValueMapping(PartialMappingIdx Idx,
102 unsigned NumOperands) {
103
104 // We can use VMI_3Ops Mapping for all the cases.
105 if (NumOperands <= 3 && (Idx >= PMI_GPR8 && Idx <= PMI_PSR80))
106 return &ValMappings[(unsigned)Idx * 3];
107
108 llvm_unreachable("Unsupported PartialMappingIdx.");
109}
110
111#endif // GET_TARGET_REGBANK_INFO_IMPL
112
113