1//===- RegisterClassInfo.h - Dynamic Register Class Info --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RegisterClassInfo class which provides dynamic
10// information about target register classes. Callee saved and reserved
11// registers depends on calling conventions and other dynamic information, so
12// some things cannot be determined statically.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
17#define LLVM_CODEGEN_REGISTERCLASSINFO_H
18
19#include "llvm/ADT/ArrayRef.h"
20#include "llvm/ADT/BitVector.h"
21#include "llvm/ADT/SmallVector.h"
22#include "llvm/CodeGen/TargetRegisterInfo.h"
23#include "llvm/MC/MCRegister.h"
24#include <cstdint>
25#include <memory>
26
27namespace llvm {
28
29class RegisterClassInfo {
30 struct RCInfo {
31 unsigned Tag = 0;
32 unsigned NumRegs = 0;
33 bool ProperSubClass = false;
34 uint8_t MinCost = 0;
35 uint16_t LastCostChange = 0;
36 std::unique_ptr<MCPhysReg[]> Order;
37
38 RCInfo() = default;
39
40 operator ArrayRef<MCPhysReg>() const {
41 return ArrayRef(Order.get(), NumRegs);
42 }
43 };
44
45 // Brief cached information for each register class.
46 std::unique_ptr<RCInfo[]> RegClass;
47
48 // Tag changes whenever cached information needs to be recomputed. An RCInfo
49 // entry is valid when its tag matches.
50 unsigned Tag = 0;
51
52 const MachineFunction *MF = nullptr;
53 const TargetRegisterInfo *TRI = nullptr;
54
55 // Callee saved registers of last MF.
56 // Used only to determine if an update for CalleeSavedAliases is necessary.
57 SmallVector<MCPhysReg, 16> LastCalleeSavedRegs;
58
59 // Map regunit to the callee saved Register.
60 SmallVector<MCPhysReg> CalleeSavedAliases;
61
62 // Indicate if a specified callee saved register be in the allocation order
63 // exactly as written in the tablegen descriptions or listed later.
64 BitVector IgnoreCSRForAllocOrder;
65
66 // Reserved registers in the current MF.
67 BitVector Reserved;
68
69 std::unique_ptr<unsigned[]> PSetLimits;
70
71 // The register cost values.
72 ArrayRef<uint8_t> RegCosts;
73
74 // Compute all information about RC.
75 void compute(const TargetRegisterClass *RC) const;
76
77 // Return an up-to-date RCInfo for RC.
78 const RCInfo &get(const TargetRegisterClass *RC) const {
79 const RCInfo &RCI = RegClass[RC->getID()];
80 if (Tag != RCI.Tag)
81 compute(RC);
82 return RCI;
83 }
84
85public:
86 RegisterClassInfo();
87
88 /// runOnFunction - Prepare to answer questions about MF. This must be called
89 /// before any other methods are used.
90 void runOnMachineFunction(const MachineFunction &MF);
91
92 /// getNumAllocatableRegs - Returns the number of actually allocatable
93 /// registers in RC in the current function.
94 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
95 return get(RC).NumRegs;
96 }
97
98 /// getOrder - Returns the preferred allocation order for RC. The order
99 /// contains no reserved registers, and registers that alias callee saved
100 /// registers come last.
101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
102 return get(RC);
103 }
104
105 /// isProperSubClass - Returns true if RC has a legal super-class with more
106 /// allocatable registers.
107 ///
108 /// Register classes like GR32_NOSP are not proper sub-classes because %esp
109 /// is not allocatable. Similarly, tGPR is not a proper sub-class in Thumb
110 /// mode because the GPR super-class is not legal.
111 bool isProperSubClass(const TargetRegisterClass *RC) const {
112 return get(RC).ProperSubClass;
113 }
114
115 /// getLastCalleeSavedAlias - Returns the last callee saved register that
116 /// overlaps PhysReg, or NoRegister if PhysReg doesn't overlap a
117 /// CalleeSavedAliases.
118 MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const {
119 MCRegister CSR;
120 for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) {
121 CSR = CalleeSavedAliases[*UI];
122 if (CSR)
123 break;
124 }
125 return CSR;
126 }
127
128 /// Get the minimum register cost in RC's allocation order.
129 /// This is the smallest value in RegCosts[Reg] for all
130 /// the registers in getOrder(RC).
131 uint8_t getMinCost(const TargetRegisterClass *RC) const {
132 return get(RC).MinCost;
133 }
134
135 /// Get the position of the last cost change in getOrder(RC).
136 ///
137 /// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the
138 /// same cost according to RegCosts[Reg].
139 unsigned getLastCostChange(const TargetRegisterClass *RC) const {
140 return get(RC).LastCostChange;
141 }
142
143 /// Get the register unit limit for the given pressure set index.
144 ///
145 /// RegisterClassInfo adjusts this limit for reserved registers.
146 unsigned getRegPressureSetLimit(unsigned Idx) const {
147 if (!PSetLimits[Idx])
148 PSetLimits[Idx] = computePSetLimit(Idx);
149 return PSetLimits[Idx];
150 }
151
152protected:
153 unsigned computePSetLimit(unsigned Idx) const;
154};
155
156} // end namespace llvm
157
158#endif // LLVM_CODEGEN_REGISTERCLASSINFO_H
159