1//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the MCOperandInfo and MCInstrDesc classes, which
10// are used to describe target instructions and their operands.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_MC_MCINSTRDESC_H
15#define LLVM_MC_MCINSTRDESC_H
16
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/iterator_range.h"
19#include "llvm/MC/MCRegister.h"
20
21namespace llvm {
22class MCRegisterInfo;
23
24class MCInst;
25
26//===----------------------------------------------------------------------===//
27// Machine Operand Flags and Description
28//===----------------------------------------------------------------------===//
29
30namespace MCOI {
31/// Operand constraints. These are encoded in 16 bits with one of the
32/// low-order 3 bits specifying that a constraint is present and the
33/// corresponding high-order hex digit specifying the constraint value.
34/// This allows for a maximum of 3 constraints.
35enum OperandConstraint {
36 TIED_TO = 0, // Must be allocated the same register as specified value.
37 EARLY_CLOBBER // If present, operand is an early clobber register.
38};
39
40// Define a macro to produce each constraint value.
41#define MCOI_TIED_TO(op) \
42 ((1 << MCOI::TIED_TO) | ((op) << (4 + MCOI::TIED_TO * 4)))
43
44#define MCOI_EARLY_CLOBBER \
45 (1 << MCOI::EARLY_CLOBBER)
46
47/// These are flags set on operands, but should be considered
48/// private, all access should go through the MCOperandInfo accessors.
49/// See the accessors for a description of what these are.
50enum OperandFlags {
51 LookupPtrRegClass = 0,
52 Predicate,
53 OptionalDef,
54 BranchTarget
55};
56
57/// Operands are tagged with one of the values of this enum.
58enum OperandType {
59 OPERAND_UNKNOWN = 0,
60 OPERAND_IMMEDIATE = 1,
61 OPERAND_REGISTER = 2,
62 OPERAND_MEMORY = 3,
63 OPERAND_PCREL = 4,
64
65 OPERAND_FIRST_GENERIC = 6,
66 OPERAND_GENERIC_0 = 6,
67 OPERAND_GENERIC_1 = 7,
68 OPERAND_GENERIC_2 = 8,
69 OPERAND_GENERIC_3 = 9,
70 OPERAND_GENERIC_4 = 10,
71 OPERAND_GENERIC_5 = 11,
72 OPERAND_LAST_GENERIC = 11,
73
74 OPERAND_FIRST_GENERIC_IMM = 12,
75 OPERAND_GENERIC_IMM_0 = 12,
76 OPERAND_LAST_GENERIC_IMM = 12,
77
78 OPERAND_FIRST_TARGET = 13,
79};
80
81} // namespace MCOI
82
83/// This holds information about one operand of a machine instruction,
84/// indicating the register class for register operands, etc.
85class MCOperandInfo {
86public:
87 /// This specifies the register class enumeration of the operand
88 /// if the operand is a register. If isLookupPtrRegClass is set, then this is
89 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
90 /// get a dynamic register class.
91 int16_t RegClass;
92
93 /// These are flags from the MCOI::OperandFlags enum.
94 uint8_t Flags;
95
96 /// Information about the type of the operand.
97 uint8_t OperandType;
98
99 /// Operand constraints (see OperandConstraint enum).
100 uint16_t Constraints;
101
102 /// Set if this operand is a pointer value and it requires a callback
103 /// to look up its register class.
104 bool isLookupPtrRegClass() const {
105 return Flags & (1 << MCOI::LookupPtrRegClass);
106 }
107
108 /// Set if this is one of the operands that made up of the predicate
109 /// operand that controls an isPredicable() instruction.
110 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
111
112 /// Set if this operand is a optional def.
113 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
114
115 /// Set if this operand is a branch target.
116 bool isBranchTarget() const { return Flags & (1 << MCOI::BranchTarget); }
117
118 bool isGenericType() const {
119 return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
120 OperandType <= MCOI::OPERAND_LAST_GENERIC;
121 }
122
123 unsigned getGenericTypeIndex() const {
124 assert(isGenericType() && "non-generic types don't have an index");
125 return OperandType - MCOI::OPERAND_FIRST_GENERIC;
126 }
127
128 bool isGenericImm() const {
129 return OperandType >= MCOI::OPERAND_FIRST_GENERIC_IMM &&
130 OperandType <= MCOI::OPERAND_LAST_GENERIC_IMM;
131 }
132
133 unsigned getGenericImmIndex() const {
134 assert(isGenericImm() && "non-generic immediates don't have an index");
135 return OperandType - MCOI::OPERAND_FIRST_GENERIC_IMM;
136 }
137};
138
139//===----------------------------------------------------------------------===//
140// Machine Instruction Flags and Description
141//===----------------------------------------------------------------------===//
142
143namespace MCID {
144/// These should be considered private to the implementation of the
145/// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc,
146/// not use these directly. These all correspond to bitfields in the
147/// MCInstrDesc::Flags field.
148enum Flag {
149 PreISelOpcode = 0,
150 Variadic,
151 HasOptionalDef,
152 Pseudo,
153 Meta,
154 Return,
155 EHScopeReturn,
156 Call,
157 Barrier,
158 Terminator,
159 Branch,
160 IndirectBranch,
161 Compare,
162 MoveImm,
163 MoveReg,
164 Bitcast,
165 Select,
166 DelaySlot,
167 FoldableAsLoad,
168 MayLoad,
169 MayStore,
170 MayRaiseFPException,
171 Predicable,
172 NotDuplicable,
173 UnmodeledSideEffects,
174 Commutable,
175 ConvertibleTo3Addr,
176 UsesCustomInserter,
177 HasPostISelHook,
178 Rematerializable,
179 CheapAsAMove,
180 ExtraSrcRegAllocReq,
181 ExtraDefRegAllocReq,
182 RegSequence,
183 ExtractSubreg,
184 InsertSubreg,
185 Convergent,
186 Add,
187 Trap,
188 VariadicOpsAreDefs,
189 Authenticated,
190};
191} // namespace MCID
192
193/// Describe properties that are true of each instruction in the target
194/// description file. This captures information about side effects, register
195/// use and many other things. There is one instance of this struct for each
196/// target instruction class, and the MachineInstr class points to this struct
197/// directly to describe itself.
198class MCInstrDesc {
199public:
200 // FIXME: Disable copies and moves.
201 // Do not allow MCInstrDescs to be copied or moved. They should only exist in
202 // the <Target>Insts table because they rely on knowing their own address to
203 // find other information elsewhere in the same table.
204
205 unsigned short Opcode; // The opcode number
206 unsigned short NumOperands; // Num of args (may be more if variable_ops)
207 unsigned char NumDefs; // Num of args that are definitions
208 unsigned char Size; // Number of bytes in encoding.
209 unsigned short SchedClass; // enum identifying instr sched class
210 unsigned char NumImplicitUses; // Num of regs implicitly used
211 unsigned char NumImplicitDefs; // Num of regs implicitly defined
212 unsigned short ImplicitOffset; // Offset to start of implicit op list
213 unsigned short OpInfoOffset; // Offset to info about operands
214 uint64_t Flags; // Flags identifying machine instr class
215 uint64_t TSFlags; // Target Specific Flag values
216
217 /// Returns the value of the specified operand constraint if
218 /// it is present. Returns -1 if it is not present.
219 int getOperandConstraint(unsigned OpNum,
220 MCOI::OperandConstraint Constraint) const {
221 if (OpNum < NumOperands &&
222 (operands()[OpNum].Constraints & (1 << Constraint))) {
223 unsigned ValuePos = 4 + Constraint * 4;
224 return (int)(operands()[OpNum].Constraints >> ValuePos) & 0x0f;
225 }
226 return -1;
227 }
228
229 /// Return the opcode number for this descriptor.
230 unsigned getOpcode() const { return Opcode; }
231
232 /// Return the number of declared MachineOperands for this
233 /// MachineInstruction. Note that variadic (isVariadic() returns true)
234 /// instructions may have additional operands at the end of the list, and note
235 /// that the machine instruction may include implicit register def/uses as
236 /// well.
237 unsigned getNumOperands() const { return NumOperands; }
238
239 ArrayRef<MCOperandInfo> operands() const {
240 auto OpInfo = reinterpret_cast<const MCOperandInfo *>(this + Opcode + 1);
241 return ArrayRef(OpInfo + OpInfoOffset, NumOperands);
242 }
243
244 /// Return the number of MachineOperands that are register
245 /// definitions. Register definitions always occur at the start of the
246 /// machine operand list. This is the number of "outs" in the .td file,
247 /// and does not include implicit defs.
248 unsigned getNumDefs() const { return NumDefs; }
249
250 /// Return flags of this instruction.
251 uint64_t getFlags() const { return Flags; }
252
253 /// \returns true if this instruction is emitted before instruction selection
254 /// and should be legalized/regbankselected/selected.
255 bool isPreISelOpcode() const { return Flags & (1ULL << MCID::PreISelOpcode); }
256
257 /// Return true if this instruction can have a variable number of
258 /// operands. In this case, the variable operands will be after the normal
259 /// operands but before the implicit definitions and uses (if any are
260 /// present).
261 bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); }
262
263 /// Set if this instruction has an optional definition, e.g.
264 /// ARM instructions which can set condition code if 's' bit is set.
265 bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
266
267 /// Return true if this is a pseudo instruction that doesn't
268 /// correspond to a real machine instruction.
269 bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); }
270
271 /// Return true if this is a meta instruction that doesn't
272 /// produce any output in the form of executable instructions.
273 bool isMetaInstruction() const { return Flags & (1ULL << MCID::Meta); }
274
275 /// Return true if the instruction is a return.
276 bool isReturn() const { return Flags & (1ULL << MCID::Return); }
277
278 /// Return true if the instruction is an add instruction.
279 bool isAdd() const { return Flags & (1ULL << MCID::Add); }
280
281 /// Return true if this instruction is a trap.
282 bool isTrap() const { return Flags & (1ULL << MCID::Trap); }
283
284 /// Return true if the instruction is a register to register move.
285 bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); }
286
287 /// Return true if the instruction is a call.
288 bool isCall() const { return Flags & (1ULL << MCID::Call); }
289
290 /// Returns true if the specified instruction stops control flow
291 /// from executing the instruction immediately following it. Examples include
292 /// unconditional branches and return instructions.
293 bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); }
294
295 /// Returns true if this instruction part of the terminator for
296 /// a basic block. Typically this is things like return and branch
297 /// instructions.
298 ///
299 /// Various passes use this to insert code into the bottom of a basic block,
300 /// but before control flow occurs.
301 bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); }
302
303 /// Returns true if this is a conditional, unconditional, or
304 /// indirect branch. Predicates below can be used to discriminate between
305 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
306 /// get more information.
307 bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
308
309 /// Return true if this is an indirect branch, such as a
310 /// branch through a register.
311 bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }
312
313 /// Return true if this is a branch which may fall
314 /// through to the next instruction or may transfer control flow to some other
315 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
316 /// information about this branch.
317 bool isConditionalBranch() const {
318 return isBranch() && !isBarrier() && !isIndirectBranch();
319 }
320
321 /// Return true if this is a branch which always
322 /// transfers control flow to some other block. The
323 /// TargetInstrInfo::analyzeBranch method can be used to get more information
324 /// about this branch.
325 bool isUnconditionalBranch() const {
326 return isBranch() && isBarrier() && !isIndirectBranch();
327 }
328
329 /// Return true if this is a branch or an instruction which directly
330 /// writes to the program counter. Considered 'may' affect rather than
331 /// 'does' affect as things like predication are not taken into account.
332 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
333
334 /// Return true if this instruction has a predicate operand
335 /// that controls execution. It may be set to 'always', or may be set to other
336 /// values. There are various methods in TargetInstrInfo that can be used to
337 /// control and modify the predicate in this instruction.
338 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); }
339
340 /// Return true if this instruction is a comparison.
341 bool isCompare() const { return Flags & (1ULL << MCID::Compare); }
342
343 /// Return true if this instruction is a move immediate
344 /// (including conditional moves) instruction.
345 bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }
346
347 /// Return true if this instruction is a bitcast instruction.
348 bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }
349
350 /// Return true if this is a select instruction.
351 bool isSelect() const { return Flags & (1ULL << MCID::Select); }
352
353 /// Return true if this instruction cannot be safely
354 /// duplicated. For example, if the instruction has a unique labels attached
355 /// to it, duplicating it would cause multiple definition errors.
356 bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); }
357
358 /// Returns true if the specified instruction has a delay slot which
359 /// must be filled by the code generator.
360 bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }
361
362 /// Return true for instructions that can be folded as memory operands
363 /// in other instructions. The most common use for this is instructions that
364 /// are simple loads from memory that don't modify the loaded value in any
365 /// way, but it can also be used for instructions that can be expressed as
366 /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be
367 /// folded when it is beneficial. This should only be set on instructions
368 /// that return a value in their only virtual register definition.
369 bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }
370
371 /// Return true if this instruction behaves
372 /// the same way as the generic REG_SEQUENCE instructions.
373 /// E.g., on ARM,
374 /// dX VMOVDRR rY, rZ
375 /// is equivalent to
376 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
377 ///
378 /// Note that for the optimizers to be able to take advantage of
379 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
380 /// override accordingly.
381 bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); }
382
383 /// Return true if this instruction behaves
384 /// the same way as the generic EXTRACT_SUBREG instructions.
385 /// E.g., on ARM,
386 /// rX, rY VMOVRRD dZ
387 /// is equivalent to two EXTRACT_SUBREG:
388 /// rX = EXTRACT_SUBREG dZ, ssub_0
389 /// rY = EXTRACT_SUBREG dZ, ssub_1
390 ///
391 /// Note that for the optimizers to be able to take advantage of
392 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
393 /// override accordingly.
394 bool isExtractSubregLike() const {
395 return Flags & (1ULL << MCID::ExtractSubreg);
396 }
397
398 /// Return true if this instruction behaves
399 /// the same way as the generic INSERT_SUBREG instructions.
400 /// E.g., on ARM,
401 /// dX = VSETLNi32 dY, rZ, Imm
402 /// is equivalent to a INSERT_SUBREG:
403 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
404 ///
405 /// Note that for the optimizers to be able to take advantage of
406 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
407 /// override accordingly.
408 bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); }
409
410
411 /// Return true if this instruction is convergent.
412 ///
413 /// Convergent instructions may not be made control-dependent on any
414 /// additional values.
415 bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); }
416
417 /// Return true if variadic operands of this instruction are definitions.
418 bool variadicOpsAreDefs() const {
419 return Flags & (1ULL << MCID::VariadicOpsAreDefs);
420 }
421
422 /// Return true if this instruction authenticates a pointer (e.g. LDRAx/BRAx
423 /// from ARMv8.3, which perform loads/branches with authentication).
424 ///
425 /// An authenticated instruction may fail in an ABI-defined manner when
426 /// operating on an invalid signed pointer.
427 bool isAuthenticated() const {
428 return Flags & (1ULL << MCID::Authenticated);
429 }
430
431 //===--------------------------------------------------------------------===//
432 // Side Effect Analysis
433 //===--------------------------------------------------------------------===//
434
435 /// Return true if this instruction could possibly read memory.
436 /// Instructions with this flag set are not necessarily simple load
437 /// instructions, they may load a value and modify it, for example.
438 bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); }
439
440 /// Return true if this instruction could possibly modify memory.
441 /// Instructions with this flag set are not necessarily simple store
442 /// instructions, they may store a modified value based on their operands, or
443 /// may not actually modify anything, for example.
444 bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }
445
446 /// Return true if this instruction may raise a floating-point exception.
447 bool mayRaiseFPException() const {
448 return Flags & (1ULL << MCID::MayRaiseFPException);
449 }
450
451 /// Return true if this instruction has side
452 /// effects that are not modeled by other flags. This does not return true
453 /// for instructions whose effects are captured by:
454 ///
455 /// 1. Their operand list and implicit definition/use list. Register use/def
456 /// info is explicit for instructions.
457 /// 2. Memory accesses. Use mayLoad/mayStore.
458 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.
459 ///
460 /// Examples of side effects would be modifying 'invisible' machine state like
461 /// a control register, flushing a cache, modifying a register invisible to
462 /// LLVM, etc.
463 bool hasUnmodeledSideEffects() const {
464 return Flags & (1ULL << MCID::UnmodeledSideEffects);
465 }
466
467 //===--------------------------------------------------------------------===//
468 // Flags that indicate whether an instruction can be modified by a method.
469 //===--------------------------------------------------------------------===//
470
471 /// Return true if this may be a 2- or 3-address instruction (of the
472 /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are
473 /// exchanged. If this flag is set, then the
474 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
475 /// instruction.
476 ///
477 /// Note that this flag may be set on instructions that are only commutable
478 /// sometimes. In these cases, the call to commuteInstruction will fail.
479 /// Also note that some instructions require non-trivial modification to
480 /// commute them.
481 bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); }
482
483 /// Return true if this is a 2-address instruction which can be changed
484 /// into a 3-address instruction if needed. Doing this transformation can be
485 /// profitable in the register allocator, because it means that the
486 /// instruction can use a 2-address form if possible, but degrade into a less
487 /// efficient form if the source and dest register cannot be assigned to the
488 /// same register. For example, this allows the x86 backend to turn a "shl
489 /// reg, 3" instruction into an LEA instruction, which is the same speed as
490 /// the shift but has bigger code size.
491 ///
492 /// If this returns true, then the target must implement the
493 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
494 /// is allowed to fail if the transformation isn't valid for this specific
495 /// instruction (e.g. shl reg, 4 on x86).
496 ///
497 bool isConvertibleTo3Addr() const {
498 return Flags & (1ULL << MCID::ConvertibleTo3Addr);
499 }
500
501 /// Return true if this instruction requires custom insertion support
502 /// when the DAG scheduler is inserting it into a machine basic block. If
503 /// this is true for the instruction, it basically means that it is a pseudo
504 /// instruction used at SelectionDAG time that is expanded out into magic code
505 /// by the target when MachineInstrs are formed.
506 ///
507 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
508 /// is used to insert this into the MachineBasicBlock.
509 bool usesCustomInsertionHook() const {
510 return Flags & (1ULL << MCID::UsesCustomInserter);
511 }
512
513 /// Return true if this instruction requires *adjustment* after
514 /// instruction selection by calling a target hook. For example, this can be
515 /// used to fill in ARM 's' optional operand depending on whether the
516 /// conditional flag register is used.
517 bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); }
518
519 /// Returns true if this instruction is a candidate for remat. This
520 /// flag is only used in TargetInstrInfo method isTriviallyRematerializable.
521 ///
522 /// If this flag is set, the isReallyTriviallyReMaterializable() method is
523 /// called to verify the instruction is really rematerializable.
524 bool isRematerializable() const {
525 return Flags & (1ULL << MCID::Rematerializable);
526 }
527
528 /// Returns true if this instruction has the same cost (or less) than a
529 /// move instruction. This is useful during certain types of optimizations
530 /// (e.g., remat during two-address conversion or machine licm) where we would
531 /// like to remat or hoist the instruction, but not if it costs more than
532 /// moving the instruction into the appropriate register. Note, we are not
533 /// marking copies from and to the same register class with this flag.
534 ///
535 /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove
536 /// for different subtargets.
537 bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); }
538
539 /// Returns true if this instruction source operands have special
540 /// register allocation requirements that are not captured by the operand
541 /// register classes. e.g. ARM::STRD's two source registers must be an even /
542 /// odd pair, ARM::STM registers have to be in ascending order. Post-register
543 /// allocation passes should not attempt to change allocations for sources of
544 /// instructions with this flag.
545 bool hasExtraSrcRegAllocReq() const {
546 return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);
547 }
548
549 /// Returns true if this instruction def operands have special register
550 /// allocation requirements that are not captured by the operand register
551 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
552 /// ARM::LDM registers have to be in ascending order. Post-register
553 /// allocation passes should not attempt to change allocations for definitions
554 /// of instructions with this flag.
555 bool hasExtraDefRegAllocReq() const {
556 return Flags & (1ULL << MCID::ExtraDefRegAllocReq);
557 }
558
559 /// Return a list of registers that are potentially read by any
560 /// instance of this machine instruction. For example, on X86, the "adc"
561 /// instruction adds two register operands and adds the carry bit in from the
562 /// flags register. In this case, the instruction is marked as implicitly
563 /// reading the flags. Likewise, the variable shift instruction on X86 is
564 /// marked as implicitly reading the 'CL' register, which it always does.
565 ArrayRef<MCPhysReg> implicit_uses() const {
566 auto ImplicitOps =
567 reinterpret_cast<const MCPhysReg *>(this + Opcode + 1) + ImplicitOffset;
568 return {ImplicitOps, NumImplicitUses};
569 }
570
571 /// Return a list of registers that are potentially written by any
572 /// instance of this machine instruction. For example, on X86, many
573 /// instructions implicitly set the flags register. In this case, they are
574 /// marked as setting the FLAGS. Likewise, many instructions always deposit
575 /// their result in a physical register. For example, the X86 divide
576 /// instruction always deposits the quotient and remainder in the EAX/EDX
577 /// registers. For that instruction, this will return a list containing the
578 /// EAX/EDX/EFLAGS registers.
579 ArrayRef<MCPhysReg> implicit_defs() const {
580 auto ImplicitOps =
581 reinterpret_cast<const MCPhysReg *>(this + Opcode + 1) + ImplicitOffset;
582 return {ImplicitOps + NumImplicitUses, NumImplicitDefs};
583 }
584
585 /// Return true if this instruction implicitly
586 /// uses the specified physical register.
587 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
588 return is_contained(Range: implicit_uses(), Element: Reg);
589 }
590
591 /// Return true if this instruction implicitly
592 /// defines the specified physical register.
593 bool hasImplicitDefOfPhysReg(unsigned Reg,
594 const MCRegisterInfo *MRI = nullptr) const;
595
596 /// Return the scheduling class for this instruction. The
597 /// scheduling class is an index into the InstrItineraryData table. This
598 /// returns zero if there is no known scheduling information for the
599 /// instruction.
600 unsigned getSchedClass() const { return SchedClass; }
601
602 /// Return the number of bytes in the encoding of this instruction,
603 /// or zero if the encoding size cannot be known from the opcode.
604 unsigned getSize() const { return Size; }
605
606 /// Find the index of the first operand in the
607 /// operand list that is used to represent the predicate. It returns -1 if
608 /// none is found.
609 int findFirstPredOperandIdx() const {
610 if (isPredicable()) {
611 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
612 if (operands()[i].isPredicate())
613 return i;
614 }
615 return -1;
616 }
617
618 /// Return true if this instruction defines the specified physical
619 /// register, either explicitly or implicitly.
620 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
621 const MCRegisterInfo &RI) const;
622};
623
624} // end namespace llvm
625
626#endif
627