| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Machine Code Emitter *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | uint64_t AArch64MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
| 10 | SmallVectorImpl<MCFixup> &Fixups, |
| 11 | const MCSubtargetInfo &STI) const { |
| 12 | static const uint64_t InstBits[] = { |
| 13 | UINT64_C(1522540544), // ABSWr |
| 14 | UINT64_C(3670024192), // ABSXr |
| 15 | UINT64_C(68591616), // ABS_ZPmZ_B |
| 16 | UINT64_C(81174528), // ABS_ZPmZ_D |
| 17 | UINT64_C(72785920), // ABS_ZPmZ_H |
| 18 | UINT64_C(76980224), // ABS_ZPmZ_S |
| 19 | UINT64_C(67543040), // ABS_ZPzZ_B |
| 20 | UINT64_C(80125952), // ABS_ZPzZ_D |
| 21 | UINT64_C(71737344), // ABS_ZPzZ_H |
| 22 | UINT64_C(75931648), // ABS_ZPzZ_S |
| 23 | UINT64_C(1310767104), // ABSv16i8 |
| 24 | UINT64_C(1591785472), // ABSv1i64 |
| 25 | UINT64_C(245413888), // ABSv2i32 |
| 26 | UINT64_C(1323350016), // ABSv2i64 |
| 27 | UINT64_C(241219584), // ABSv4i16 |
| 28 | UINT64_C(1319155712), // ABSv4i32 |
| 29 | UINT64_C(1314961408), // ABSv8i16 |
| 30 | UINT64_C(237025280), // ABSv8i8 |
| 31 | UINT64_C(1161875456), // ADCLB_ZZZ_D |
| 32 | UINT64_C(1157681152), // ADCLB_ZZZ_S |
| 33 | UINT64_C(1161876480), // ADCLT_ZZZ_D |
| 34 | UINT64_C(1157682176), // ADCLT_ZZZ_S |
| 35 | UINT64_C(973078528), // ADCSWr |
| 36 | UINT64_C(3120562176), // ADCSXr |
| 37 | UINT64_C(436207616), // ADCWr |
| 38 | UINT64_C(2583691264), // ADCXr |
| 39 | UINT64_C(2441084928), // ADDG |
| 40 | UINT64_C(3234856960), // ADDHA_MPPZ_D |
| 41 | UINT64_C(3230662656), // ADDHA_MPPZ_S |
| 42 | UINT64_C(1163943936), // ADDHNB_ZZZ_B |
| 43 | UINT64_C(1168138240), // ADDHNB_ZZZ_H |
| 44 | UINT64_C(1172332544), // ADDHNB_ZZZ_S |
| 45 | UINT64_C(1163944960), // ADDHNT_ZZZ_B |
| 46 | UINT64_C(1168139264), // ADDHNT_ZZZ_H |
| 47 | UINT64_C(1172333568), // ADDHNT_ZZZ_S |
| 48 | UINT64_C(245383168), // ADDHNv2i64_v2i32 |
| 49 | UINT64_C(1319124992), // ADDHNv2i64_v4i32 |
| 50 | UINT64_C(241188864), // ADDHNv4i32_v4i16 |
| 51 | UINT64_C(1314930688), // ADDHNv4i32_v8i16 |
| 52 | UINT64_C(1310736384), // ADDHNv8i16_v16i8 |
| 53 | UINT64_C(236994560), // ADDHNv8i16_v8i8 |
| 54 | UINT64_C(73420800), // ADDPL_XXI |
| 55 | UINT64_C(2583699456), // ADDPT_shift |
| 56 | UINT64_C(1142005760), // ADDP_ZPmZ_B |
| 57 | UINT64_C(1154588672), // ADDP_ZPmZ_D |
| 58 | UINT64_C(1146200064), // ADDP_ZPmZ_H |
| 59 | UINT64_C(1150394368), // ADDP_ZPmZ_S |
| 60 | UINT64_C(1310768128), // ADDPv16i8 |
| 61 | UINT64_C(245414912), // ADDPv2i32 |
| 62 | UINT64_C(1323351040), // ADDPv2i64 |
| 63 | UINT64_C(1592899584), // ADDPv2i64p |
| 64 | UINT64_C(241220608), // ADDPv4i16 |
| 65 | UINT64_C(1319156736), // ADDPv4i32 |
| 66 | UINT64_C(1314962432), // ADDPv8i16 |
| 67 | UINT64_C(237026304), // ADDPv8i8 |
| 68 | UINT64_C(69236736), // ADDQP_ZZZ_B |
| 69 | UINT64_C(81819648), // ADDQP_ZZZ_D |
| 70 | UINT64_C(73431040), // ADDQP_ZZZ_H |
| 71 | UINT64_C(77625344), // ADDQP_ZZZ_S |
| 72 | UINT64_C(67444736), // ADDQV_VPZ_B |
| 73 | UINT64_C(80027648), // ADDQV_VPZ_D |
| 74 | UINT64_C(71639040), // ADDQV_VPZ_H |
| 75 | UINT64_C(75833344), // ADDQV_VPZ_S |
| 76 | UINT64_C(73422848), // ADDSPL_XXI |
| 77 | UINT64_C(69237760), // ADDSUBP_ZZZ_B |
| 78 | UINT64_C(81820672), // ADDSUBP_ZZZ_D |
| 79 | UINT64_C(73432064), // ADDSUBP_ZZZ_H |
| 80 | UINT64_C(77626368), // ADDSUBP_ZZZ_S |
| 81 | UINT64_C(69228544), // ADDSVL_XXI |
| 82 | UINT64_C(822083584), // ADDSWri |
| 83 | UINT64_C(721420288), // ADDSWrs |
| 84 | UINT64_C(723517440), // ADDSWrx |
| 85 | UINT64_C(2969567232), // ADDSXri |
| 86 | UINT64_C(2868903936), // ADDSXrs |
| 87 | UINT64_C(2871001088), // ADDSXrx |
| 88 | UINT64_C(2871025664), // ADDSXrx64 |
| 89 | UINT64_C(3234922496), // ADDVA_MPPZ_D |
| 90 | UINT64_C(3230728192), // ADDVA_MPPZ_S |
| 91 | UINT64_C(69226496), // ADDVL_XXI |
| 92 | UINT64_C(1311881216), // ADDVv16i8v |
| 93 | UINT64_C(242333696), // ADDVv4i16v |
| 94 | UINT64_C(1320269824), // ADDVv4i32v |
| 95 | UINT64_C(1316075520), // ADDVv8i16v |
| 96 | UINT64_C(238139392), // ADDVv8i8v |
| 97 | UINT64_C(285212672), // ADDWri |
| 98 | UINT64_C(184549376), // ADDWrs |
| 99 | UINT64_C(186646528), // ADDWrx |
| 100 | UINT64_C(2432696320), // ADDXri |
| 101 | UINT64_C(2332033024), // ADDXrs |
| 102 | UINT64_C(2334130176), // ADDXrx |
| 103 | UINT64_C(2334154752), // ADDXrx64 |
| 104 | UINT64_C(3240141568), // ADD_VG2_2ZZ_B |
| 105 | UINT64_C(3252724480), // ADD_VG2_2ZZ_D |
| 106 | UINT64_C(3244335872), // ADD_VG2_2ZZ_H |
| 107 | UINT64_C(3248530176), // ADD_VG2_2ZZ_S |
| 108 | UINT64_C(3252688912), // ADD_VG2_M2Z2Z_D |
| 109 | UINT64_C(3248494608), // ADD_VG2_M2Z2Z_S |
| 110 | UINT64_C(3244300304), // ADD_VG2_M2ZZ_D |
| 111 | UINT64_C(3240106000), // ADD_VG2_M2ZZ_S |
| 112 | UINT64_C(3252689936), // ADD_VG2_M2Z_D |
| 113 | UINT64_C(3248495632), // ADD_VG2_M2Z_S |
| 114 | UINT64_C(3240143616), // ADD_VG4_4ZZ_B |
| 115 | UINT64_C(3252726528), // ADD_VG4_4ZZ_D |
| 116 | UINT64_C(3244337920), // ADD_VG4_4ZZ_H |
| 117 | UINT64_C(3248532224), // ADD_VG4_4ZZ_S |
| 118 | UINT64_C(3252754448), // ADD_VG4_M4Z4Z_D |
| 119 | UINT64_C(3248560144), // ADD_VG4_M4Z4Z_S |
| 120 | UINT64_C(3245348880), // ADD_VG4_M4ZZ_D |
| 121 | UINT64_C(3241154576), // ADD_VG4_M4ZZ_S |
| 122 | UINT64_C(3252755472), // ADD_VG4_M4Z_D |
| 123 | UINT64_C(3248561168), // ADD_VG4_M4Z_S |
| 124 | UINT64_C(622903296), // ADD_ZI_B |
| 125 | UINT64_C(635486208), // ADD_ZI_D |
| 126 | UINT64_C(627097600), // ADD_ZI_H |
| 127 | UINT64_C(631291904), // ADD_ZI_S |
| 128 | UINT64_C(67108864), // ADD_ZPmZ_B |
| 129 | UINT64_C(79953920), // ADD_ZPmZ_CPA |
| 130 | UINT64_C(79691776), // ADD_ZPmZ_D |
| 131 | UINT64_C(71303168), // ADD_ZPmZ_H |
| 132 | UINT64_C(75497472), // ADD_ZPmZ_S |
| 133 | UINT64_C(69206016), // ADD_ZZZ_B |
| 134 | UINT64_C(81790976), // ADD_ZZZ_CPA |
| 135 | UINT64_C(81788928), // ADD_ZZZ_D |
| 136 | UINT64_C(73400320), // ADD_ZZZ_H |
| 137 | UINT64_C(77594624), // ADD_ZZZ_S |
| 138 | UINT64_C(1310753792), // ADDv16i8 |
| 139 | UINT64_C(1591772160), // ADDv1i64 |
| 140 | UINT64_C(245400576), // ADDv2i32 |
| 141 | UINT64_C(1323336704), // ADDv2i64 |
| 142 | UINT64_C(241206272), // ADDv4i16 |
| 143 | UINT64_C(1319142400), // ADDv4i32 |
| 144 | UINT64_C(1314948096), // ADDv8i16 |
| 145 | UINT64_C(237011968), // ADDv8i8 |
| 146 | UINT64_C(268435456), // ADR |
| 147 | UINT64_C(2415919104), // ADRP |
| 148 | UINT64_C(81829888), // ADR_LSL_ZZZ_D_0 |
| 149 | UINT64_C(81830912), // ADR_LSL_ZZZ_D_1 |
| 150 | UINT64_C(81831936), // ADR_LSL_ZZZ_D_2 |
| 151 | UINT64_C(81832960), // ADR_LSL_ZZZ_D_3 |
| 152 | UINT64_C(77635584), // ADR_LSL_ZZZ_S_0 |
| 153 | UINT64_C(77636608), // ADR_LSL_ZZZ_S_1 |
| 154 | UINT64_C(77637632), // ADR_LSL_ZZZ_S_2 |
| 155 | UINT64_C(77638656), // ADR_LSL_ZZZ_S_3 |
| 156 | UINT64_C(69246976), // ADR_SXTW_ZZZ_D_0 |
| 157 | UINT64_C(69248000), // ADR_SXTW_ZZZ_D_1 |
| 158 | UINT64_C(69249024), // ADR_SXTW_ZZZ_D_2 |
| 159 | UINT64_C(69250048), // ADR_SXTW_ZZZ_D_3 |
| 160 | UINT64_C(73441280), // ADR_UXTW_ZZZ_D_0 |
| 161 | UINT64_C(73442304), // ADR_UXTW_ZZZ_D_1 |
| 162 | UINT64_C(73443328), // ADR_UXTW_ZZZ_D_2 |
| 163 | UINT64_C(73444352), // ADR_UXTW_ZZZ_D_3 |
| 164 | UINT64_C(1159982080), // AESDIMC_2ZZI_B |
| 165 | UINT64_C(1160244224), // AESDIMC_4ZZI_B |
| 166 | UINT64_C(1159916544), // AESD_2ZZI_B |
| 167 | UINT64_C(1160178688), // AESD_4ZZI_B |
| 168 | UINT64_C(1159914496), // AESD_ZZZ_B |
| 169 | UINT64_C(1311266816), // AESDrr |
| 170 | UINT64_C(1159981056), // AESEMC_2ZZI_B |
| 171 | UINT64_C(1160243200), // AESEMC_4ZZI_B |
| 172 | UINT64_C(1159915520), // AESE_2ZZI_B |
| 173 | UINT64_C(1160177664), // AESE_4ZZI_B |
| 174 | UINT64_C(1159913472), // AESE_ZZZ_B |
| 175 | UINT64_C(1311262720), // AESErr |
| 176 | UINT64_C(1159783424), // AESIMC_ZZ_B |
| 177 | UINT64_C(1311275008), // AESIMCrr |
| 178 | UINT64_C(1159782400), // AESMC_ZZ_B |
| 179 | UINT64_C(1311270912), // AESMCrr |
| 180 | UINT64_C(69083136), // ANDQV_VPZ_B |
| 181 | UINT64_C(81666048), // ANDQV_VPZ_D |
| 182 | UINT64_C(73277440), // ANDQV_VPZ_H |
| 183 | UINT64_C(77471744), // ANDQV_VPZ_S |
| 184 | UINT64_C(1912602624), // ANDSWri |
| 185 | UINT64_C(1778384896), // ANDSWrs |
| 186 | UINT64_C(4060086272), // ANDSXri |
| 187 | UINT64_C(3925868544), // ANDSXrs |
| 188 | UINT64_C(624967680), // ANDS_PPzPP |
| 189 | UINT64_C(68820992), // ANDV_VPZ_B |
| 190 | UINT64_C(81403904), // ANDV_VPZ_D |
| 191 | UINT64_C(73015296), // ANDV_VPZ_H |
| 192 | UINT64_C(77209600), // ANDV_VPZ_S |
| 193 | UINT64_C(301989888), // ANDWri |
| 194 | UINT64_C(167772160), // ANDWrs |
| 195 | UINT64_C(2449473536), // ANDXri |
| 196 | UINT64_C(2315255808), // ANDXrs |
| 197 | UINT64_C(620773376), // AND_PPzPP |
| 198 | UINT64_C(92274688), // AND_ZI |
| 199 | UINT64_C(68812800), // AND_ZPmZ_B |
| 200 | UINT64_C(81395712), // AND_ZPmZ_D |
| 201 | UINT64_C(73007104), // AND_ZPmZ_H |
| 202 | UINT64_C(77201408), // AND_ZPmZ_S |
| 203 | UINT64_C(69218304), // AND_ZZZ |
| 204 | UINT64_C(1310727168), // ANDv16i8 |
| 205 | UINT64_C(236985344), // ANDv8i8 |
| 206 | UINT64_C(67404032), // ASRD_ZPmI_B |
| 207 | UINT64_C(75792384), // ASRD_ZPmI_D |
| 208 | UINT64_C(67404288), // ASRD_ZPmI_H |
| 209 | UINT64_C(71598080), // ASRD_ZPmI_S |
| 210 | UINT64_C(68452352), // ASRR_ZPmZ_B |
| 211 | UINT64_C(81035264), // ASRR_ZPmZ_D |
| 212 | UINT64_C(72646656), // ASRR_ZPmZ_H |
| 213 | UINT64_C(76840960), // ASRR_ZPmZ_S |
| 214 | UINT64_C(448800768), // ASRVWr |
| 215 | UINT64_C(2596284416), // ASRVXr |
| 216 | UINT64_C(68714496), // ASR_WIDE_ZPmZ_B |
| 217 | UINT64_C(72908800), // ASR_WIDE_ZPmZ_H |
| 218 | UINT64_C(77103104), // ASR_WIDE_ZPmZ_S |
| 219 | UINT64_C(69238784), // ASR_WIDE_ZZZ_B |
| 220 | UINT64_C(73433088), // ASR_WIDE_ZZZ_H |
| 221 | UINT64_C(77627392), // ASR_WIDE_ZZZ_S |
| 222 | UINT64_C(67141888), // ASR_ZPmI_B |
| 223 | UINT64_C(75530240), // ASR_ZPmI_D |
| 224 | UINT64_C(67142144), // ASR_ZPmI_H |
| 225 | UINT64_C(71335936), // ASR_ZPmI_S |
| 226 | UINT64_C(68190208), // ASR_ZPmZ_B |
| 227 | UINT64_C(80773120), // ASR_ZPmZ_D |
| 228 | UINT64_C(72384512), // ASR_ZPmZ_H |
| 229 | UINT64_C(76578816), // ASR_ZPmZ_S |
| 230 | UINT64_C(69767168), // ASR_ZZI_B |
| 231 | UINT64_C(77631488), // ASR_ZZI_D |
| 232 | UINT64_C(70291456), // ASR_ZZI_H |
| 233 | UINT64_C(73437184), // ASR_ZZI_S |
| 234 | UINT64_C(3670087680), // AUTDA |
| 235 | UINT64_C(3670088704), // AUTDB |
| 236 | UINT64_C(3670096864), // AUTDZA |
| 237 | UINT64_C(3670097888), // AUTDZB |
| 238 | UINT64_C(3670085632), // AUTIA |
| 239 | UINT64_C(3573752223), // AUTIA1716 |
| 240 | UINT64_C(3670129662), // AUTIA171615 |
| 241 | UINT64_C(3573752767), // AUTIASP |
| 242 | UINT64_C(4085252127), // AUTIASPPCi |
| 243 | UINT64_C(3670118430), // AUTIASPPCr |
| 244 | UINT64_C(3573752735), // AUTIAZ |
| 245 | UINT64_C(3670086656), // AUTIB |
| 246 | UINT64_C(3573752287), // AUTIB1716 |
| 247 | UINT64_C(3670130686), // AUTIB171615 |
| 248 | UINT64_C(3573752831), // AUTIBSP |
| 249 | UINT64_C(4087349279), // AUTIBSPPCi |
| 250 | UINT64_C(3670119454), // AUTIBSPPCr |
| 251 | UINT64_C(3573752799), // AUTIBZ |
| 252 | UINT64_C(3670094816), // AUTIZA |
| 253 | UINT64_C(3670095840), // AUTIZB |
| 254 | UINT64_C(3573563487), // AXFLAG |
| 255 | UINT64_C(335544320), // B |
| 256 | UINT64_C(3458203648), // BCAX |
| 257 | UINT64_C(73414656), // BCAX_ZZZZ |
| 258 | UINT64_C(1409286160), // BCcc |
| 259 | UINT64_C(1157673984), // BDEP_ZZZ_B |
| 260 | UINT64_C(1170256896), // BDEP_ZZZ_D |
| 261 | UINT64_C(1161868288), // BDEP_ZZZ_H |
| 262 | UINT64_C(1166062592), // BDEP_ZZZ_S |
| 263 | UINT64_C(1157672960), // BEXT_ZZZ_B |
| 264 | UINT64_C(1170255872), // BEXT_ZZZ_D |
| 265 | UINT64_C(1161867264), // BEXT_ZZZ_H |
| 266 | UINT64_C(1166061568), // BEXT_ZZZ_S |
| 267 | UINT64_C(255913984), // BF16DOTlanev4bf16 |
| 268 | UINT64_C(1329655808), // BF16DOTlanev8bf16 |
| 269 | UINT64_C(782333952), // BF1CVTL |
| 270 | UINT64_C(1856075776), // BF1CVTL2 |
| 271 | UINT64_C(1695102976), // BF1CVTLT_ZZ_BtoH |
| 272 | UINT64_C(3244744705), // BF1CVTL_2ZZ_BtoH |
| 273 | UINT64_C(3244744704), // BF1CVT_2ZZ_BtoH |
| 274 | UINT64_C(1695037440), // BF1CVT_ZZ_BtoH |
| 275 | UINT64_C(786528256), // BF2CVTL |
| 276 | UINT64_C(1860270080), // BF2CVTL2 |
| 277 | UINT64_C(1695104000), // BF2CVTLT_ZZ_BtoH |
| 278 | UINT64_C(3253133313), // BF2CVTL_2ZZ_BtoH |
| 279 | UINT64_C(3253133312), // BF2CVT_2ZZ_BtoH |
| 280 | UINT64_C(1695038464), // BF2CVT_ZZ_BtoH |
| 281 | UINT64_C(3252952064), // BFADD_VG2_M2Z_H |
| 282 | UINT64_C(3253017600), // BFADD_VG4_M4Z_H |
| 283 | UINT64_C(1694531584), // BFADD_ZPmZ |
| 284 | UINT64_C(1694498816), // BFADD_ZZZ |
| 285 | UINT64_C(3240148992), // BFCLAMP_VG2_2ZZZ_H |
| 286 | UINT64_C(3240151040), // BFCLAMP_VG4_4ZZZ_H |
| 287 | UINT64_C(1679827968), // BFCLAMP_ZZZ |
| 288 | UINT64_C(509820928), // BFCVT |
| 289 | UINT64_C(245458944), // BFCVTN |
| 290 | UINT64_C(1319200768), // BFCVTN2 |
| 291 | UINT64_C(1686806528), // BFCVTNT_ZPmZ |
| 292 | UINT64_C(1686282240), // BFCVTNT_ZPzZ_StoH |
| 293 | UINT64_C(1695168512), // BFCVTN_Z2Z_HtoB |
| 294 | UINT64_C(3244351520), // BFCVTN_Z2Z_StoH |
| 295 | UINT64_C(3244613632), // BFCVT_Z2Z_HtoB |
| 296 | UINT64_C(3244351488), // BFCVT_Z2Z_StoH |
| 297 | UINT64_C(1703583744), // BFCVT_ZPmZ |
| 298 | UINT64_C(1687863296), // BFCVT_ZPzZ_StoH |
| 299 | UINT64_C(3248492560), // BFDOT_VG2_M2Z2Z_HtoS |
| 300 | UINT64_C(3243249688), // BFDOT_VG2_M2ZZI_HtoS |
| 301 | UINT64_C(3240103952), // BFDOT_VG2_M2ZZ_HtoS |
| 302 | UINT64_C(3248558096), // BFDOT_VG4_M4Z4Z_HtoS |
| 303 | UINT64_C(3243282456), // BFDOT_VG4_M4ZZI_HtoS |
| 304 | UINT64_C(3241152528), // BFDOT_VG4_M4ZZ_HtoS |
| 305 | UINT64_C(1684029440), // BFDOT_ZZI |
| 306 | UINT64_C(1684045824), // BFDOT_ZZZ |
| 307 | UINT64_C(776010752), // BFDOTv4bf16 |
| 308 | UINT64_C(1849752576), // BFDOTv8bf16 |
| 309 | UINT64_C(3240145184), // BFMAXNM_VG2_2Z2Z_H |
| 310 | UINT64_C(3240141088), // BFMAXNM_VG2_2ZZ_H |
| 311 | UINT64_C(3240147232), // BFMAXNM_VG4_4Z2Z_H |
| 312 | UINT64_C(3240143136), // BFMAXNM_VG4_4ZZ_H |
| 313 | UINT64_C(1694793728), // BFMAXNM_ZPmZ |
| 314 | UINT64_C(3240145152), // BFMAX_VG2_2Z2Z_H |
| 315 | UINT64_C(3240141056), // BFMAX_VG2_2ZZ_H |
| 316 | UINT64_C(3240147200), // BFMAX_VG4_4Z2Z_H |
| 317 | UINT64_C(3240143104), // BFMAX_VG4_4ZZ_H |
| 318 | UINT64_C(1694924800), // BFMAX_ZPmZ |
| 319 | UINT64_C(3240145185), // BFMINNM_VG2_2Z2Z_H |
| 320 | UINT64_C(3240141089), // BFMINNM_VG2_2ZZ_H |
| 321 | UINT64_C(3240147233), // BFMINNM_VG4_4Z2Z_H |
| 322 | UINT64_C(3240143137), // BFMINNM_VG4_4ZZ_H |
| 323 | UINT64_C(1694859264), // BFMINNM_ZPmZ |
| 324 | UINT64_C(3240145153), // BFMIN_VG2_2Z2Z_H |
| 325 | UINT64_C(3240141057), // BFMIN_VG2_2ZZ_H |
| 326 | UINT64_C(3240147201), // BFMIN_VG4_4Z2Z_H |
| 327 | UINT64_C(3240143105), // BFMIN_VG4_4ZZ_H |
| 328 | UINT64_C(1694990336), // BFMIN_ZPmZ |
| 329 | UINT64_C(784399360), // BFMLALB |
| 330 | UINT64_C(264302592), // BFMLALBIdx |
| 331 | UINT64_C(1692434432), // BFMLALB_ZZZ |
| 332 | UINT64_C(1692418048), // BFMLALB_ZZZI |
| 333 | UINT64_C(1858141184), // BFMLALT |
| 334 | UINT64_C(1338044416), // BFMLALTIdx |
| 335 | UINT64_C(1692435456), // BFMLALT_ZZZ |
| 336 | UINT64_C(1692419072), // BFMLALT_ZZZI |
| 337 | UINT64_C(3246395408), // BFMLAL_MZZI_HtoS |
| 338 | UINT64_C(3240102928), // BFMLAL_MZZ_HtoS |
| 339 | UINT64_C(3248490512), // BFMLAL_VG2_M2Z2Z_HtoS |
| 340 | UINT64_C(3247443984), // BFMLAL_VG2_M2ZZI_HtoS |
| 341 | UINT64_C(3240101904), // BFMLAL_VG2_M2ZZ_HtoS |
| 342 | UINT64_C(3248556048), // BFMLAL_VG4_M4Z4Z_HtoS |
| 343 | UINT64_C(3247476752), // BFMLAL_VG4_M4ZZI_HtoS |
| 344 | UINT64_C(3241150480), // BFMLAL_VG4_M4ZZ_HtoS |
| 345 | UINT64_C(3252686856), // BFMLA_VG2_M2Z2Z |
| 346 | UINT64_C(3244301312), // BFMLA_VG2_M2ZZ |
| 347 | UINT64_C(3239055392), // BFMLA_VG2_M2ZZI |
| 348 | UINT64_C(3252752392), // BFMLA_VG4_M4Z4Z |
| 349 | UINT64_C(3245349888), // BFMLA_VG4_M4ZZ |
| 350 | UINT64_C(3239088160), // BFMLA_VG4_M4ZZI |
| 351 | UINT64_C(1696595968), // BFMLA_ZPmZZ |
| 352 | UINT64_C(1679820800), // BFMLA_ZZZI |
| 353 | UINT64_C(1692426240), // BFMLSLB_ZZZI_S |
| 354 | UINT64_C(1692442624), // BFMLSLB_ZZZ_S |
| 355 | UINT64_C(1692427264), // BFMLSLT_ZZZI_S |
| 356 | UINT64_C(1692443648), // BFMLSLT_ZZZ_S |
| 357 | UINT64_C(3246395416), // BFMLSL_MZZI_HtoS |
| 358 | UINT64_C(3240102936), // BFMLSL_MZZ_HtoS |
| 359 | UINT64_C(3248490520), // BFMLSL_VG2_M2Z2Z_HtoS |
| 360 | UINT64_C(3247443992), // BFMLSL_VG2_M2ZZI_HtoS |
| 361 | UINT64_C(3240101912), // BFMLSL_VG2_M2ZZ_HtoS |
| 362 | UINT64_C(3248556056), // BFMLSL_VG4_M4Z4Z_HtoS |
| 363 | UINT64_C(3247476760), // BFMLSL_VG4_M4ZZI_HtoS |
| 364 | UINT64_C(3241150488), // BFMLSL_VG4_M4ZZ_HtoS |
| 365 | UINT64_C(3252686872), // BFMLS_VG2_M2Z2Z |
| 366 | UINT64_C(3244301320), // BFMLS_VG2_M2ZZ |
| 367 | UINT64_C(3239055408), // BFMLS_VG2_M2ZZI |
| 368 | UINT64_C(3252752408), // BFMLS_VG4_M4Z4Z |
| 369 | UINT64_C(3245349896), // BFMLS_VG4_M4ZZ |
| 370 | UINT64_C(3239088176), // BFMLS_VG4_M4ZZI |
| 371 | UINT64_C(1696604160), // BFMLS_ZPmZZ |
| 372 | UINT64_C(1679821824), // BFMLS_ZZZI |
| 373 | UINT64_C(1849748480), // BFMMLA |
| 374 | UINT64_C(1692459008), // BFMMLA_ZZZ_H |
| 375 | UINT64_C(1684071424), // BFMMLA_ZZZ_HtoS |
| 376 | UINT64_C(2167407112), // BFMOP4A_M2Z2Z_H |
| 377 | UINT64_C(2165309952), // BFMOP4A_M2Z2Z_S |
| 378 | UINT64_C(2166358536), // BFMOP4A_M2ZZ_H |
| 379 | UINT64_C(2164261376), // BFMOP4A_M2ZZ_S |
| 380 | UINT64_C(2167406600), // BFMOP4A_MZ2Z_H |
| 381 | UINT64_C(2165309440), // BFMOP4A_MZ2Z_S |
| 382 | UINT64_C(2166358024), // BFMOP4A_MZZ_H |
| 383 | UINT64_C(2164260864), // BFMOP4A_MZZ_S |
| 384 | UINT64_C(2167407128), // BFMOP4S_M2Z2Z_H |
| 385 | UINT64_C(2165309968), // BFMOP4S_M2Z2Z_S |
| 386 | UINT64_C(2166358552), // BFMOP4S_M2ZZ_H |
| 387 | UINT64_C(2164261392), // BFMOP4S_M2ZZ_S |
| 388 | UINT64_C(2167406616), // BFMOP4S_MZ2Z_H |
| 389 | UINT64_C(2165309456), // BFMOP4S_MZ2Z_S |
| 390 | UINT64_C(2166358040), // BFMOP4S_MZZ_H |
| 391 | UINT64_C(2164260880), // BFMOP4S_MZZ_S |
| 392 | UINT64_C(2172649472), // BFMOPA_MPPZZ |
| 393 | UINT64_C(2174746632), // BFMOPA_MPPZZ_H |
| 394 | UINT64_C(2172649488), // BFMOPS_MPPZZ |
| 395 | UINT64_C(2174746648), // BFMOPS_MPPZZ_H |
| 396 | UINT64_C(3240158208), // BFMUL_2Z2Z |
| 397 | UINT64_C(3240159232), // BFMUL_2ZZ |
| 398 | UINT64_C(3240223744), // BFMUL_4Z4Z |
| 399 | UINT64_C(3240224768), // BFMUL_4ZZ |
| 400 | UINT64_C(1694662656), // BFMUL_ZPmZ |
| 401 | UINT64_C(1694500864), // BFMUL_ZZZ |
| 402 | UINT64_C(1679828992), // BFMUL_ZZZI |
| 403 | UINT64_C(855638016), // BFMWri |
| 404 | UINT64_C(3007315968), // BFMXri |
| 405 | UINT64_C(3240145280), // BFSCALE_2Z2Z |
| 406 | UINT64_C(3240141184), // BFSCALE_2ZZ |
| 407 | UINT64_C(3240147328), // BFSCALE_4Z4Z |
| 408 | UINT64_C(3240143232), // BFSCALE_4ZZ |
| 409 | UINT64_C(1695121408), // BFSCALE_ZPmZ |
| 410 | UINT64_C(3252952072), // BFSUB_VG2_M2Z_H |
| 411 | UINT64_C(3253017608), // BFSUB_VG4_M4Z_H |
| 412 | UINT64_C(1694597120), // BFSUB_ZPmZ |
| 413 | UINT64_C(1694499840), // BFSUB_ZZZ |
| 414 | UINT64_C(2170552328), // BFTMOPA_M2ZZZI_HtoH |
| 415 | UINT64_C(2168455168), // BFTMOPA_M2ZZZI_HtoS |
| 416 | UINT64_C(3243245592), // BFVDOT_VG2_M2ZZI_HtoS |
| 417 | UINT64_C(1157675008), // BGRP_ZZZ_B |
| 418 | UINT64_C(1170257920), // BGRP_ZZZ_D |
| 419 | UINT64_C(1161869312), // BGRP_ZZZ_H |
| 420 | UINT64_C(1166063616), // BGRP_ZZZ_S |
| 421 | UINT64_C(1780482048), // BICSWrs |
| 422 | UINT64_C(3927965696), // BICSXrs |
| 423 | UINT64_C(624967696), // BICS_PPzPP |
| 424 | UINT64_C(169869312), // BICWrs |
| 425 | UINT64_C(2317352960), // BICXrs |
| 426 | UINT64_C(620773392), // BIC_PPzPP |
| 427 | UINT64_C(68878336), // BIC_ZPmZ_B |
| 428 | UINT64_C(81461248), // BIC_ZPmZ_D |
| 429 | UINT64_C(73072640), // BIC_ZPmZ_H |
| 430 | UINT64_C(77266944), // BIC_ZPmZ_S |
| 431 | UINT64_C(81801216), // BIC_ZZZ |
| 432 | UINT64_C(1314921472), // BICv16i8 |
| 433 | UINT64_C(788534272), // BICv2i32 |
| 434 | UINT64_C(788567040), // BICv4i16 |
| 435 | UINT64_C(1862276096), // BICv4i32 |
| 436 | UINT64_C(1862308864), // BICv8i16 |
| 437 | UINT64_C(241179648), // BICv8i8 |
| 438 | UINT64_C(1860180992), // BIFv16i8 |
| 439 | UINT64_C(786439168), // BIFv8i8 |
| 440 | UINT64_C(1855986688), // BITv16i8 |
| 441 | UINT64_C(782244864), // BITv8i8 |
| 442 | UINT64_C(2483027968), // BL |
| 443 | UINT64_C(3594452992), // BLR |
| 444 | UINT64_C(3611232256), // BLRAA |
| 445 | UINT64_C(3594455071), // BLRAAZ |
| 446 | UINT64_C(3611233280), // BLRAB |
| 447 | UINT64_C(3594456095), // BLRABZ |
| 448 | UINT64_C(2155872264), // BMOPA_MPPZZ_S |
| 449 | UINT64_C(2155872280), // BMOPS_MPPZZ_S |
| 450 | UINT64_C(3592355840), // BR |
| 451 | UINT64_C(3609135104), // BRAA |
| 452 | UINT64_C(3592357919), // BRAAZ |
| 453 | UINT64_C(3609136128), // BRAB |
| 454 | UINT64_C(3592358943), // BRABZ |
| 455 | UINT64_C(3558866944), // BRK |
| 456 | UINT64_C(626016256), // BRKAS_PPzP |
| 457 | UINT64_C(621821968), // BRKA_PPmP |
| 458 | UINT64_C(621821952), // BRKA_PPzP |
| 459 | UINT64_C(634404864), // BRKBS_PPzP |
| 460 | UINT64_C(630210576), // BRKB_PPmP |
| 461 | UINT64_C(630210560), // BRKB_PPzP |
| 462 | UINT64_C(626540544), // BRKNS_PPzP |
| 463 | UINT64_C(622346240), // BRKN_PPzP |
| 464 | UINT64_C(625000448), // BRKPAS_PPzPP |
| 465 | UINT64_C(620806144), // BRKPA_PPzPP |
| 466 | UINT64_C(625000464), // BRKPBS_PPzPP |
| 467 | UINT64_C(620806160), // BRKPB_PPzPP |
| 468 | UINT64_C(73415680), // BSL1N_ZZZZ |
| 469 | UINT64_C(77609984), // BSL2N_ZZZZ |
| 470 | UINT64_C(69221376), // BSL_ZZZZ |
| 471 | UINT64_C(1851792384), // BSLv16i8 |
| 472 | UINT64_C(778050560), // BSLv8i8 |
| 473 | UINT64_C(1409286144), // Bcc |
| 474 | UINT64_C(1157683200), // CADD_ZZI_B |
| 475 | UINT64_C(1170266112), // CADD_ZZI_D |
| 476 | UINT64_C(1161877504), // CADD_ZZI_H |
| 477 | UINT64_C(1166071808), // CADD_ZZI_S |
| 478 | UINT64_C(148929536), // CASAB |
| 479 | UINT64_C(1222671360), // CASAH |
| 480 | UINT64_C(148962304), // CASALB |
| 481 | UINT64_C(1222704128), // CASALH |
| 482 | UINT64_C(3384867840), // CASALTX |
| 483 | UINT64_C(2296445952), // CASALW |
| 484 | UINT64_C(3370187776), // CASALX |
| 485 | UINT64_C(3384835072), // CASATX |
| 486 | UINT64_C(2296413184), // CASAW |
| 487 | UINT64_C(3370155008), // CASAX |
| 488 | UINT64_C(144735232), // CASB |
| 489 | UINT64_C(1218477056), // CASH |
| 490 | UINT64_C(144768000), // CASLB |
| 491 | UINT64_C(1218509824), // CASLH |
| 492 | UINT64_C(3380673536), // CASLTX |
| 493 | UINT64_C(2292251648), // CASLW |
| 494 | UINT64_C(3365993472), // CASLX |
| 495 | UINT64_C(1237384192), // CASPALTX |
| 496 | UINT64_C(140573696), // CASPALW |
| 497 | UINT64_C(1214315520), // CASPALX |
| 498 | UINT64_C(1237351424), // CASPATX |
| 499 | UINT64_C(140540928), // CASPAW |
| 500 | UINT64_C(1214282752), // CASPAX |
| 501 | UINT64_C(1233189888), // CASPLTX |
| 502 | UINT64_C(136379392), // CASPLW |
| 503 | UINT64_C(1210121216), // CASPLX |
| 504 | UINT64_C(1233157120), // CASPTX |
| 505 | UINT64_C(136346624), // CASPW |
| 506 | UINT64_C(1210088448), // CASPX |
| 507 | UINT64_C(3380640768), // CASTX |
| 508 | UINT64_C(2292218880), // CASW |
| 509 | UINT64_C(3365960704), // CASX |
| 510 | UINT64_C(1958772736), // CBBEQWrr |
| 511 | UINT64_C(1948286976), // CBBGEWrr |
| 512 | UINT64_C(1946189824), // CBBGTWrr |
| 513 | UINT64_C(1950384128), // CBBHIWrr |
| 514 | UINT64_C(1952481280), // CBBHSWrr |
| 515 | UINT64_C(1960869888), // CBBNEWrr |
| 516 | UINT64_C(1975517184), // CBEQWri |
| 517 | UINT64_C(1958739968), // CBEQWrr |
| 518 | UINT64_C(4123000832), // CBEQXri |
| 519 | UINT64_C(4106223616), // CBEQXrr |
| 520 | UINT64_C(1948254208), // CBGEWrr |
| 521 | UINT64_C(4095737856), // CBGEXrr |
| 522 | UINT64_C(1962934272), // CBGTWri |
| 523 | UINT64_C(1946157056), // CBGTWrr |
| 524 | UINT64_C(4110417920), // CBGTXri |
| 525 | UINT64_C(4093640704), // CBGTXrr |
| 526 | UINT64_C(1958789120), // CBHEQWrr |
| 527 | UINT64_C(1948303360), // CBHGEWrr |
| 528 | UINT64_C(1946206208), // CBHGTWrr |
| 529 | UINT64_C(1950400512), // CBHHIWrr |
| 530 | UINT64_C(1952497664), // CBHHSWrr |
| 531 | UINT64_C(1967128576), // CBHIWri |
| 532 | UINT64_C(1950351360), // CBHIWrr |
| 533 | UINT64_C(4114612224), // CBHIXri |
| 534 | UINT64_C(4097835008), // CBHIXrr |
| 535 | UINT64_C(1960886272), // CBHNEWrr |
| 536 | UINT64_C(1952448512), // CBHSWrr |
| 537 | UINT64_C(4099932160), // CBHSXrr |
| 538 | UINT64_C(1969225728), // CBLOWri |
| 539 | UINT64_C(4116709376), // CBLOXri |
| 540 | UINT64_C(1965031424), // CBLTWri |
| 541 | UINT64_C(4112515072), // CBLTXri |
| 542 | UINT64_C(1977614336), // CBNEWri |
| 543 | UINT64_C(1960837120), // CBNEWrr |
| 544 | UINT64_C(4125097984), // CBNEXri |
| 545 | UINT64_C(4108320768), // CBNEXrr |
| 546 | UINT64_C(889192448), // CBNZW |
| 547 | UINT64_C(3036676096), // CBNZX |
| 548 | UINT64_C(872415232), // CBZW |
| 549 | UINT64_C(3019898880), // CBZX |
| 550 | UINT64_C(977274880), // CCMNWi |
| 551 | UINT64_C(977272832), // CCMNWr |
| 552 | UINT64_C(3124758528), // CCMNXi |
| 553 | UINT64_C(3124756480), // CCMNXr |
| 554 | UINT64_C(2051016704), // CCMPWi |
| 555 | UINT64_C(2051014656), // CCMPWr |
| 556 | UINT64_C(4198500352), // CCMPXi |
| 557 | UINT64_C(4198498304), // CCMPXr |
| 558 | UINT64_C(1155547136), // CDOT_ZZZI_D |
| 559 | UINT64_C(1151352832), // CDOT_ZZZI_S |
| 560 | UINT64_C(1153437696), // CDOT_ZZZ_D |
| 561 | UINT64_C(1149243392), // CDOT_ZZZ_S |
| 562 | UINT64_C(3573563423), // CFINV |
| 563 | UINT64_C(1988100096), // CFLTEQWi |
| 564 | UINT64_C(1992294912), // CFLTEQWr |
| 565 | UINT64_C(4135583744), // CFLTEQXi |
| 566 | UINT64_C(4139778560), // CFLTEQXr |
| 567 | UINT64_C(1981809152), // CFLTGEWr |
| 568 | UINT64_C(4129292800), // CFLTGEXr |
| 569 | UINT64_C(1979711488), // CFLTGTWi |
| 570 | UINT64_C(1979712000), // CFLTGTWr |
| 571 | UINT64_C(4127195136), // CFLTGTXi |
| 572 | UINT64_C(4127195648), // CFLTGTXr |
| 573 | UINT64_C(1983905792), // CFLTHIWi |
| 574 | UINT64_C(1983906304), // CFLTHIWr |
| 575 | UINT64_C(4131389440), // CFLTHIXi |
| 576 | UINT64_C(4131389952), // CFLTHIXr |
| 577 | UINT64_C(1986003456), // CFLTHSWr |
| 578 | UINT64_C(4133487104), // CFLTHSXr |
| 579 | UINT64_C(1986002944), // CFLTLOWi |
| 580 | UINT64_C(4133486592), // CFLTLOXi |
| 581 | UINT64_C(1981808640), // CFLTLTWi |
| 582 | UINT64_C(4129292288), // CFLTLTXi |
| 583 | UINT64_C(1990197248), // CFLTNEWi |
| 584 | UINT64_C(1994392064), // CFLTNEWr |
| 585 | UINT64_C(4137680896), // CFLTNEXi |
| 586 | UINT64_C(4141875712), // CFLTNEXr |
| 587 | UINT64_C(3573753119), // CHKFEAT |
| 588 | UINT64_C(87072768), // CLASTA_RPZ_B |
| 589 | UINT64_C(99655680), // CLASTA_RPZ_D |
| 590 | UINT64_C(91267072), // CLASTA_RPZ_H |
| 591 | UINT64_C(95461376), // CLASTA_RPZ_S |
| 592 | UINT64_C(86671360), // CLASTA_VPZ_B |
| 593 | UINT64_C(99254272), // CLASTA_VPZ_D |
| 594 | UINT64_C(90865664), // CLASTA_VPZ_H |
| 595 | UINT64_C(95059968), // CLASTA_VPZ_S |
| 596 | UINT64_C(86540288), // CLASTA_ZPZ_B |
| 597 | UINT64_C(99123200), // CLASTA_ZPZ_D |
| 598 | UINT64_C(90734592), // CLASTA_ZPZ_H |
| 599 | UINT64_C(94928896), // CLASTA_ZPZ_S |
| 600 | UINT64_C(87138304), // CLASTB_RPZ_B |
| 601 | UINT64_C(99721216), // CLASTB_RPZ_D |
| 602 | UINT64_C(91332608), // CLASTB_RPZ_H |
| 603 | UINT64_C(95526912), // CLASTB_RPZ_S |
| 604 | UINT64_C(86736896), // CLASTB_VPZ_B |
| 605 | UINT64_C(99319808), // CLASTB_VPZ_D |
| 606 | UINT64_C(90931200), // CLASTB_VPZ_H |
| 607 | UINT64_C(95125504), // CLASTB_VPZ_S |
| 608 | UINT64_C(86605824), // CLASTB_ZPZ_B |
| 609 | UINT64_C(99188736), // CLASTB_ZPZ_D |
| 610 | UINT64_C(90800128), // CLASTB_ZPZ_H |
| 611 | UINT64_C(94994432), // CLASTB_ZPZ_S |
| 612 | UINT64_C(3573755999), // CLREX |
| 613 | UINT64_C(1522537472), // CLSWr |
| 614 | UINT64_C(3670021120), // CLSXr |
| 615 | UINT64_C(68722688), // CLS_ZPmZ_B |
| 616 | UINT64_C(81305600), // CLS_ZPmZ_D |
| 617 | UINT64_C(72916992), // CLS_ZPmZ_H |
| 618 | UINT64_C(77111296), // CLS_ZPmZ_S |
| 619 | UINT64_C(67674112), // CLS_ZPzZ_B |
| 620 | UINT64_C(80257024), // CLS_ZPzZ_D |
| 621 | UINT64_C(71868416), // CLS_ZPzZ_H |
| 622 | UINT64_C(76062720), // CLS_ZPzZ_S |
| 623 | UINT64_C(1310738432), // CLSv16i8 |
| 624 | UINT64_C(245385216), // CLSv2i32 |
| 625 | UINT64_C(241190912), // CLSv4i16 |
| 626 | UINT64_C(1319127040), // CLSv4i32 |
| 627 | UINT64_C(1314932736), // CLSv8i16 |
| 628 | UINT64_C(236996608), // CLSv8i8 |
| 629 | UINT64_C(1522536448), // CLZWr |
| 630 | UINT64_C(3670020096), // CLZXr |
| 631 | UINT64_C(68788224), // CLZ_ZPmZ_B |
| 632 | UINT64_C(81371136), // CLZ_ZPmZ_D |
| 633 | UINT64_C(72982528), // CLZ_ZPmZ_H |
| 634 | UINT64_C(77176832), // CLZ_ZPmZ_S |
| 635 | UINT64_C(67739648), // CLZ_ZPzZ_B |
| 636 | UINT64_C(80322560), // CLZ_ZPzZ_D |
| 637 | UINT64_C(71933952), // CLZ_ZPzZ_H |
| 638 | UINT64_C(76128256), // CLZ_ZPzZ_S |
| 639 | UINT64_C(1847609344), // CLZv16i8 |
| 640 | UINT64_C(782256128), // CLZv2i32 |
| 641 | UINT64_C(778061824), // CLZv4i16 |
| 642 | UINT64_C(1855997952), // CLZv4i32 |
| 643 | UINT64_C(1851803648), // CLZv8i16 |
| 644 | UINT64_C(773867520), // CLZv8i8 |
| 645 | UINT64_C(1847626752), // CMEQv16i8 |
| 646 | UINT64_C(1310758912), // CMEQv16i8rz |
| 647 | UINT64_C(2128645120), // CMEQv1i64 |
| 648 | UINT64_C(1591777280), // CMEQv1i64rz |
| 649 | UINT64_C(782273536), // CMEQv2i32 |
| 650 | UINT64_C(245405696), // CMEQv2i32rz |
| 651 | UINT64_C(1860209664), // CMEQv2i64 |
| 652 | UINT64_C(1323341824), // CMEQv2i64rz |
| 653 | UINT64_C(778079232), // CMEQv4i16 |
| 654 | UINT64_C(241211392), // CMEQv4i16rz |
| 655 | UINT64_C(1856015360), // CMEQv4i32 |
| 656 | UINT64_C(1319147520), // CMEQv4i32rz |
| 657 | UINT64_C(1851821056), // CMEQv8i16 |
| 658 | UINT64_C(1314953216), // CMEQv8i16rz |
| 659 | UINT64_C(773884928), // CMEQv8i8 |
| 660 | UINT64_C(237017088), // CMEQv8i8rz |
| 661 | UINT64_C(1310735360), // CMGEv16i8 |
| 662 | UINT64_C(1847625728), // CMGEv16i8rz |
| 663 | UINT64_C(1591753728), // CMGEv1i64 |
| 664 | UINT64_C(2128644096), // CMGEv1i64rz |
| 665 | UINT64_C(245382144), // CMGEv2i32 |
| 666 | UINT64_C(782272512), // CMGEv2i32rz |
| 667 | UINT64_C(1323318272), // CMGEv2i64 |
| 668 | UINT64_C(1860208640), // CMGEv2i64rz |
| 669 | UINT64_C(241187840), // CMGEv4i16 |
| 670 | UINT64_C(778078208), // CMGEv4i16rz |
| 671 | UINT64_C(1319123968), // CMGEv4i32 |
| 672 | UINT64_C(1856014336), // CMGEv4i32rz |
| 673 | UINT64_C(1314929664), // CMGEv8i16 |
| 674 | UINT64_C(1851820032), // CMGEv8i16rz |
| 675 | UINT64_C(236993536), // CMGEv8i8 |
| 676 | UINT64_C(773883904), // CMGEv8i8rz |
| 677 | UINT64_C(1310733312), // CMGTv16i8 |
| 678 | UINT64_C(1310754816), // CMGTv16i8rz |
| 679 | UINT64_C(1591751680), // CMGTv1i64 |
| 680 | UINT64_C(1591773184), // CMGTv1i64rz |
| 681 | UINT64_C(245380096), // CMGTv2i32 |
| 682 | UINT64_C(245401600), // CMGTv2i32rz |
| 683 | UINT64_C(1323316224), // CMGTv2i64 |
| 684 | UINT64_C(1323337728), // CMGTv2i64rz |
| 685 | UINT64_C(241185792), // CMGTv4i16 |
| 686 | UINT64_C(241207296), // CMGTv4i16rz |
| 687 | UINT64_C(1319121920), // CMGTv4i32 |
| 688 | UINT64_C(1319143424), // CMGTv4i32rz |
| 689 | UINT64_C(1314927616), // CMGTv8i16 |
| 690 | UINT64_C(1314949120), // CMGTv8i16rz |
| 691 | UINT64_C(236991488), // CMGTv8i8 |
| 692 | UINT64_C(237012992), // CMGTv8i8rz |
| 693 | UINT64_C(1847604224), // CMHIv16i8 |
| 694 | UINT64_C(2128622592), // CMHIv1i64 |
| 695 | UINT64_C(782251008), // CMHIv2i32 |
| 696 | UINT64_C(1860187136), // CMHIv2i64 |
| 697 | UINT64_C(778056704), // CMHIv4i16 |
| 698 | UINT64_C(1855992832), // CMHIv4i32 |
| 699 | UINT64_C(1851798528), // CMHIv8i16 |
| 700 | UINT64_C(773862400), // CMHIv8i8 |
| 701 | UINT64_C(1847606272), // CMHSv16i8 |
| 702 | UINT64_C(2128624640), // CMHSv1i64 |
| 703 | UINT64_C(782253056), // CMHSv2i32 |
| 704 | UINT64_C(1860189184), // CMHSv2i64 |
| 705 | UINT64_C(778058752), // CMHSv4i16 |
| 706 | UINT64_C(1855994880), // CMHSv4i32 |
| 707 | UINT64_C(1851800576), // CMHSv8i16 |
| 708 | UINT64_C(773864448), // CMHSv8i8 |
| 709 | UINT64_C(1151361024), // CMLA_ZZZI_H |
| 710 | UINT64_C(1155555328), // CMLA_ZZZI_S |
| 711 | UINT64_C(1140858880), // CMLA_ZZZ_B |
| 712 | UINT64_C(1153441792), // CMLA_ZZZ_D |
| 713 | UINT64_C(1145053184), // CMLA_ZZZ_H |
| 714 | UINT64_C(1149247488), // CMLA_ZZZ_S |
| 715 | UINT64_C(1847629824), // CMLEv16i8rz |
| 716 | UINT64_C(2128648192), // CMLEv1i64rz |
| 717 | UINT64_C(782276608), // CMLEv2i32rz |
| 718 | UINT64_C(1860212736), // CMLEv2i64rz |
| 719 | UINT64_C(778082304), // CMLEv4i16rz |
| 720 | UINT64_C(1856018432), // CMLEv4i32rz |
| 721 | UINT64_C(1851824128), // CMLEv8i16rz |
| 722 | UINT64_C(773888000), // CMLEv8i8rz |
| 723 | UINT64_C(1310763008), // CMLTv16i8rz |
| 724 | UINT64_C(1591781376), // CMLTv1i64rz |
| 725 | UINT64_C(245409792), // CMLTv2i32rz |
| 726 | UINT64_C(1323345920), // CMLTv2i64rz |
| 727 | UINT64_C(241215488), // CMLTv4i16rz |
| 728 | UINT64_C(1319151616), // CMLTv4i32rz |
| 729 | UINT64_C(1314957312), // CMLTv8i16rz |
| 730 | UINT64_C(237021184), // CMLTv8i8rz |
| 731 | UINT64_C(620789760), // CMPEQ_PPzZI_B |
| 732 | UINT64_C(633372672), // CMPEQ_PPzZI_D |
| 733 | UINT64_C(624984064), // CMPEQ_PPzZI_H |
| 734 | UINT64_C(629178368), // CMPEQ_PPzZI_S |
| 735 | UINT64_C(604020736), // CMPEQ_PPzZZ_B |
| 736 | UINT64_C(616603648), // CMPEQ_PPzZZ_D |
| 737 | UINT64_C(608215040), // CMPEQ_PPzZZ_H |
| 738 | UINT64_C(612409344), // CMPEQ_PPzZZ_S |
| 739 | UINT64_C(603987968), // CMPEQ_WIDE_PPzZZ_B |
| 740 | UINT64_C(608182272), // CMPEQ_WIDE_PPzZZ_H |
| 741 | UINT64_C(612376576), // CMPEQ_WIDE_PPzZZ_S |
| 742 | UINT64_C(620756992), // CMPGE_PPzZI_B |
| 743 | UINT64_C(633339904), // CMPGE_PPzZI_D |
| 744 | UINT64_C(624951296), // CMPGE_PPzZI_H |
| 745 | UINT64_C(629145600), // CMPGE_PPzZI_S |
| 746 | UINT64_C(604012544), // CMPGE_PPzZZ_B |
| 747 | UINT64_C(616595456), // CMPGE_PPzZZ_D |
| 748 | UINT64_C(608206848), // CMPGE_PPzZZ_H |
| 749 | UINT64_C(612401152), // CMPGE_PPzZZ_S |
| 750 | UINT64_C(603996160), // CMPGE_WIDE_PPzZZ_B |
| 751 | UINT64_C(608190464), // CMPGE_WIDE_PPzZZ_H |
| 752 | UINT64_C(612384768), // CMPGE_WIDE_PPzZZ_S |
| 753 | UINT64_C(620757008), // CMPGT_PPzZI_B |
| 754 | UINT64_C(633339920), // CMPGT_PPzZI_D |
| 755 | UINT64_C(624951312), // CMPGT_PPzZI_H |
| 756 | UINT64_C(629145616), // CMPGT_PPzZI_S |
| 757 | UINT64_C(604012560), // CMPGT_PPzZZ_B |
| 758 | UINT64_C(616595472), // CMPGT_PPzZZ_D |
| 759 | UINT64_C(608206864), // CMPGT_PPzZZ_H |
| 760 | UINT64_C(612401168), // CMPGT_PPzZZ_S |
| 761 | UINT64_C(603996176), // CMPGT_WIDE_PPzZZ_B |
| 762 | UINT64_C(608190480), // CMPGT_WIDE_PPzZZ_H |
| 763 | UINT64_C(612384784), // CMPGT_WIDE_PPzZZ_S |
| 764 | UINT64_C(606076944), // CMPHI_PPzZI_B |
| 765 | UINT64_C(618659856), // CMPHI_PPzZI_D |
| 766 | UINT64_C(610271248), // CMPHI_PPzZI_H |
| 767 | UINT64_C(614465552), // CMPHI_PPzZI_S |
| 768 | UINT64_C(603979792), // CMPHI_PPzZZ_B |
| 769 | UINT64_C(616562704), // CMPHI_PPzZZ_D |
| 770 | UINT64_C(608174096), // CMPHI_PPzZZ_H |
| 771 | UINT64_C(612368400), // CMPHI_PPzZZ_S |
| 772 | UINT64_C(604028944), // CMPHI_WIDE_PPzZZ_B |
| 773 | UINT64_C(608223248), // CMPHI_WIDE_PPzZZ_H |
| 774 | UINT64_C(612417552), // CMPHI_WIDE_PPzZZ_S |
| 775 | UINT64_C(606076928), // CMPHS_PPzZI_B |
| 776 | UINT64_C(618659840), // CMPHS_PPzZI_D |
| 777 | UINT64_C(610271232), // CMPHS_PPzZI_H |
| 778 | UINT64_C(614465536), // CMPHS_PPzZI_S |
| 779 | UINT64_C(603979776), // CMPHS_PPzZZ_B |
| 780 | UINT64_C(616562688), // CMPHS_PPzZZ_D |
| 781 | UINT64_C(608174080), // CMPHS_PPzZZ_H |
| 782 | UINT64_C(612368384), // CMPHS_PPzZZ_S |
| 783 | UINT64_C(604028928), // CMPHS_WIDE_PPzZZ_B |
| 784 | UINT64_C(608223232), // CMPHS_WIDE_PPzZZ_H |
| 785 | UINT64_C(612417536), // CMPHS_WIDE_PPzZZ_S |
| 786 | UINT64_C(620765200), // CMPLE_PPzZI_B |
| 787 | UINT64_C(633348112), // CMPLE_PPzZI_D |
| 788 | UINT64_C(624959504), // CMPLE_PPzZI_H |
| 789 | UINT64_C(629153808), // CMPLE_PPzZI_S |
| 790 | UINT64_C(604004368), // CMPLE_WIDE_PPzZZ_B |
| 791 | UINT64_C(608198672), // CMPLE_WIDE_PPzZZ_H |
| 792 | UINT64_C(612392976), // CMPLE_WIDE_PPzZZ_S |
| 793 | UINT64_C(606085120), // CMPLO_PPzZI_B |
| 794 | UINT64_C(618668032), // CMPLO_PPzZI_D |
| 795 | UINT64_C(610279424), // CMPLO_PPzZI_H |
| 796 | UINT64_C(614473728), // CMPLO_PPzZI_S |
| 797 | UINT64_C(604037120), // CMPLO_WIDE_PPzZZ_B |
| 798 | UINT64_C(608231424), // CMPLO_WIDE_PPzZZ_H |
| 799 | UINT64_C(612425728), // CMPLO_WIDE_PPzZZ_S |
| 800 | UINT64_C(606085136), // CMPLS_PPzZI_B |
| 801 | UINT64_C(618668048), // CMPLS_PPzZI_D |
| 802 | UINT64_C(610279440), // CMPLS_PPzZI_H |
| 803 | UINT64_C(614473744), // CMPLS_PPzZI_S |
| 804 | UINT64_C(604037136), // CMPLS_WIDE_PPzZZ_B |
| 805 | UINT64_C(608231440), // CMPLS_WIDE_PPzZZ_H |
| 806 | UINT64_C(612425744), // CMPLS_WIDE_PPzZZ_S |
| 807 | UINT64_C(620765184), // CMPLT_PPzZI_B |
| 808 | UINT64_C(633348096), // CMPLT_PPzZI_D |
| 809 | UINT64_C(624959488), // CMPLT_PPzZI_H |
| 810 | UINT64_C(629153792), // CMPLT_PPzZI_S |
| 811 | UINT64_C(604004352), // CMPLT_WIDE_PPzZZ_B |
| 812 | UINT64_C(608198656), // CMPLT_WIDE_PPzZZ_H |
| 813 | UINT64_C(612392960), // CMPLT_WIDE_PPzZZ_S |
| 814 | UINT64_C(620789776), // CMPNE_PPzZI_B |
| 815 | UINT64_C(633372688), // CMPNE_PPzZI_D |
| 816 | UINT64_C(624984080), // CMPNE_PPzZI_H |
| 817 | UINT64_C(629178384), // CMPNE_PPzZI_S |
| 818 | UINT64_C(604020752), // CMPNE_PPzZZ_B |
| 819 | UINT64_C(616603664), // CMPNE_PPzZZ_D |
| 820 | UINT64_C(608215056), // CMPNE_PPzZZ_H |
| 821 | UINT64_C(612409360), // CMPNE_PPzZZ_S |
| 822 | UINT64_C(603987984), // CMPNE_WIDE_PPzZZ_B |
| 823 | UINT64_C(608182288), // CMPNE_WIDE_PPzZZ_H |
| 824 | UINT64_C(612376592), // CMPNE_WIDE_PPzZZ_S |
| 825 | UINT64_C(1310755840), // CMTSTv16i8 |
| 826 | UINT64_C(1591774208), // CMTSTv1i64 |
| 827 | UINT64_C(245402624), // CMTSTv2i32 |
| 828 | UINT64_C(1323338752), // CMTSTv2i64 |
| 829 | UINT64_C(241208320), // CMTSTv4i16 |
| 830 | UINT64_C(1319144448), // CMTSTv4i32 |
| 831 | UINT64_C(1314950144), // CMTSTv8i16 |
| 832 | UINT64_C(237014016), // CMTSTv8i8 |
| 833 | UINT64_C(68919296), // CNOT_ZPmZ_B |
| 834 | UINT64_C(81502208), // CNOT_ZPmZ_D |
| 835 | UINT64_C(73113600), // CNOT_ZPmZ_H |
| 836 | UINT64_C(77307904), // CNOT_ZPmZ_S |
| 837 | UINT64_C(67870720), // CNOT_ZPzZ_B |
| 838 | UINT64_C(80453632), // CNOT_ZPzZ_D |
| 839 | UINT64_C(72065024), // CNOT_ZPzZ_H |
| 840 | UINT64_C(76259328), // CNOT_ZPzZ_S |
| 841 | UINT64_C(69263360), // CNTB_XPiI |
| 842 | UINT64_C(81846272), // CNTD_XPiI |
| 843 | UINT64_C(73457664), // CNTH_XPiI |
| 844 | UINT64_C(622887424), // CNTP_XCI_B |
| 845 | UINT64_C(635470336), // CNTP_XCI_D |
| 846 | UINT64_C(627081728), // CNTP_XCI_H |
| 847 | UINT64_C(631276032), // CNTP_XCI_S |
| 848 | UINT64_C(622886912), // CNTP_XPP_B |
| 849 | UINT64_C(635469824), // CNTP_XPP_D |
| 850 | UINT64_C(627081216), // CNTP_XPP_H |
| 851 | UINT64_C(631275520), // CNTP_XPP_S |
| 852 | UINT64_C(77651968), // CNTW_XPiI |
| 853 | UINT64_C(1522539520), // CNTWr |
| 854 | UINT64_C(3670023168), // CNTXr |
| 855 | UINT64_C(68853760), // CNT_ZPmZ_B |
| 856 | UINT64_C(81436672), // CNT_ZPmZ_D |
| 857 | UINT64_C(73048064), // CNT_ZPmZ_H |
| 858 | UINT64_C(77242368), // CNT_ZPmZ_S |
| 859 | UINT64_C(67805184), // CNT_ZPzZ_B |
| 860 | UINT64_C(80388096), // CNT_ZPzZ_D |
| 861 | UINT64_C(71999488), // CNT_ZPzZ_H |
| 862 | UINT64_C(76193792), // CNT_ZPzZ_S |
| 863 | UINT64_C(1310742528), // CNTv16i8 |
| 864 | UINT64_C(237000704), // CNTv8i8 |
| 865 | UINT64_C(86081536), // COMPACT_ZPZ_B |
| 866 | UINT64_C(98664448), // COMPACT_ZPZ_D |
| 867 | UINT64_C(90275840), // COMPACT_ZPZ_H |
| 868 | UINT64_C(94470144), // COMPACT_ZPZ_S |
| 869 | UINT64_C(494928896), // CPYE |
| 870 | UINT64_C(494978048), // CPYEN |
| 871 | UINT64_C(494961664), // CPYERN |
| 872 | UINT64_C(494937088), // CPYERT |
| 873 | UINT64_C(494986240), // CPYERTN |
| 874 | UINT64_C(494969856), // CPYERTRN |
| 875 | UINT64_C(494953472), // CPYERTWN |
| 876 | UINT64_C(494941184), // CPYET |
| 877 | UINT64_C(494990336), // CPYETN |
| 878 | UINT64_C(494973952), // CPYETRN |
| 879 | UINT64_C(494957568), // CPYETWN |
| 880 | UINT64_C(494945280), // CPYEWN |
| 881 | UINT64_C(494932992), // CPYEWT |
| 882 | UINT64_C(494982144), // CPYEWTN |
| 883 | UINT64_C(494965760), // CPYEWTRN |
| 884 | UINT64_C(494949376), // CPYEWTWN |
| 885 | UINT64_C(427820032), // CPYFE |
| 886 | UINT64_C(427869184), // CPYFEN |
| 887 | UINT64_C(427852800), // CPYFERN |
| 888 | UINT64_C(427828224), // CPYFERT |
| 889 | UINT64_C(427877376), // CPYFERTN |
| 890 | UINT64_C(427860992), // CPYFERTRN |
| 891 | UINT64_C(427844608), // CPYFERTWN |
| 892 | UINT64_C(427832320), // CPYFET |
| 893 | UINT64_C(427881472), // CPYFETN |
| 894 | UINT64_C(427865088), // CPYFETRN |
| 895 | UINT64_C(427848704), // CPYFETWN |
| 896 | UINT64_C(427836416), // CPYFEWN |
| 897 | UINT64_C(427824128), // CPYFEWT |
| 898 | UINT64_C(427873280), // CPYFEWTN |
| 899 | UINT64_C(427856896), // CPYFEWTRN |
| 900 | UINT64_C(427840512), // CPYFEWTWN |
| 901 | UINT64_C(423625728), // CPYFM |
| 902 | UINT64_C(423674880), // CPYFMN |
| 903 | UINT64_C(423658496), // CPYFMRN |
| 904 | UINT64_C(423633920), // CPYFMRT |
| 905 | UINT64_C(423683072), // CPYFMRTN |
| 906 | UINT64_C(423666688), // CPYFMRTRN |
| 907 | UINT64_C(423650304), // CPYFMRTWN |
| 908 | UINT64_C(423638016), // CPYFMT |
| 909 | UINT64_C(423687168), // CPYFMTN |
| 910 | UINT64_C(423670784), // CPYFMTRN |
| 911 | UINT64_C(423654400), // CPYFMTWN |
| 912 | UINT64_C(423642112), // CPYFMWN |
| 913 | UINT64_C(423629824), // CPYFMWT |
| 914 | UINT64_C(423678976), // CPYFMWTN |
| 915 | UINT64_C(423662592), // CPYFMWTRN |
| 916 | UINT64_C(423646208), // CPYFMWTWN |
| 917 | UINT64_C(419431424), // CPYFP |
| 918 | UINT64_C(419480576), // CPYFPN |
| 919 | UINT64_C(419464192), // CPYFPRN |
| 920 | UINT64_C(419439616), // CPYFPRT |
| 921 | UINT64_C(419488768), // CPYFPRTN |
| 922 | UINT64_C(419472384), // CPYFPRTRN |
| 923 | UINT64_C(419456000), // CPYFPRTWN |
| 924 | UINT64_C(419443712), // CPYFPT |
| 925 | UINT64_C(419492864), // CPYFPTN |
| 926 | UINT64_C(419476480), // CPYFPTRN |
| 927 | UINT64_C(419460096), // CPYFPTWN |
| 928 | UINT64_C(419447808), // CPYFPWN |
| 929 | UINT64_C(419435520), // CPYFPWT |
| 930 | UINT64_C(419484672), // CPYFPWTN |
| 931 | UINT64_C(419468288), // CPYFPWTRN |
| 932 | UINT64_C(419451904), // CPYFPWTWN |
| 933 | UINT64_C(490734592), // CPYM |
| 934 | UINT64_C(490783744), // CPYMN |
| 935 | UINT64_C(490767360), // CPYMRN |
| 936 | UINT64_C(490742784), // CPYMRT |
| 937 | UINT64_C(490791936), // CPYMRTN |
| 938 | UINT64_C(490775552), // CPYMRTRN |
| 939 | UINT64_C(490759168), // CPYMRTWN |
| 940 | UINT64_C(490746880), // CPYMT |
| 941 | UINT64_C(490796032), // CPYMTN |
| 942 | UINT64_C(490779648), // CPYMTRN |
| 943 | UINT64_C(490763264), // CPYMTWN |
| 944 | UINT64_C(490750976), // CPYMWN |
| 945 | UINT64_C(490738688), // CPYMWT |
| 946 | UINT64_C(490787840), // CPYMWTN |
| 947 | UINT64_C(490771456), // CPYMWTRN |
| 948 | UINT64_C(490755072), // CPYMWTWN |
| 949 | UINT64_C(486540288), // CPYP |
| 950 | UINT64_C(486589440), // CPYPN |
| 951 | UINT64_C(486573056), // CPYPRN |
| 952 | UINT64_C(486548480), // CPYPRT |
| 953 | UINT64_C(486597632), // CPYPRTN |
| 954 | UINT64_C(486581248), // CPYPRTRN |
| 955 | UINT64_C(486564864), // CPYPRTWN |
| 956 | UINT64_C(486552576), // CPYPT |
| 957 | UINT64_C(486601728), // CPYPTN |
| 958 | UINT64_C(486585344), // CPYPTRN |
| 959 | UINT64_C(486568960), // CPYPTWN |
| 960 | UINT64_C(486556672), // CPYPWN |
| 961 | UINT64_C(486544384), // CPYPWT |
| 962 | UINT64_C(486593536), // CPYPWTN |
| 963 | UINT64_C(486577152), // CPYPWTRN |
| 964 | UINT64_C(486560768), // CPYPWTWN |
| 965 | UINT64_C(84951040), // CPY_ZPmI_B |
| 966 | UINT64_C(97533952), // CPY_ZPmI_D |
| 967 | UINT64_C(89145344), // CPY_ZPmI_H |
| 968 | UINT64_C(93339648), // CPY_ZPmI_S |
| 969 | UINT64_C(86548480), // CPY_ZPmR_B |
| 970 | UINT64_C(99131392), // CPY_ZPmR_D |
| 971 | UINT64_C(90742784), // CPY_ZPmR_H |
| 972 | UINT64_C(94937088), // CPY_ZPmR_S |
| 973 | UINT64_C(86016000), // CPY_ZPmV_B |
| 974 | UINT64_C(98598912), // CPY_ZPmV_D |
| 975 | UINT64_C(90210304), // CPY_ZPmV_H |
| 976 | UINT64_C(94404608), // CPY_ZPmV_S |
| 977 | UINT64_C(84934656), // CPY_ZPzI_B |
| 978 | UINT64_C(97517568), // CPY_ZPzI_D |
| 979 | UINT64_C(89128960), // CPY_ZPzI_H |
| 980 | UINT64_C(93323264), // CPY_ZPzI_S |
| 981 | UINT64_C(448806912), // CRC32Brr |
| 982 | UINT64_C(448811008), // CRC32CBrr |
| 983 | UINT64_C(448812032), // CRC32CHrr |
| 984 | UINT64_C(448813056), // CRC32CWrr |
| 985 | UINT64_C(2596297728), // CRC32CXrr |
| 986 | UINT64_C(448807936), // CRC32Hrr |
| 987 | UINT64_C(448808960), // CRC32Wrr |
| 988 | UINT64_C(2596293632), // CRC32Xrr |
| 989 | UINT64_C(444596224), // CSELWr |
| 990 | UINT64_C(2592079872), // CSELXr |
| 991 | UINT64_C(444597248), // CSINCWr |
| 992 | UINT64_C(2592080896), // CSINCXr |
| 993 | UINT64_C(1518338048), // CSINVWr |
| 994 | UINT64_C(3665821696), // CSINVXr |
| 995 | UINT64_C(1518339072), // CSNEGWr |
| 996 | UINT64_C(3665822720), // CSNEGXr |
| 997 | UINT64_C(631250944), // CTERMEQ_WW |
| 998 | UINT64_C(635445248), // CTERMEQ_XX |
| 999 | UINT64_C(631250960), // CTERMNE_WW |
| 1000 | UINT64_C(635445264), // CTERMNE_XX |
| 1001 | UINT64_C(1522538496), // CTZWr |
| 1002 | UINT64_C(3670022144), // CTZXr |
| 1003 | UINT64_C(3567255553), // DCPS1 |
| 1004 | UINT64_C(3567255554), // DCPS2 |
| 1005 | UINT64_C(3567255555), // DCPS3 |
| 1006 | UINT64_C(70312960), // DECB_XPiI |
| 1007 | UINT64_C(82895872), // DECD_XPiI |
| 1008 | UINT64_C(82887680), // DECD_ZPiI |
| 1009 | UINT64_C(74507264), // DECH_XPiI |
| 1010 | UINT64_C(74499072), // DECH_ZPiI |
| 1011 | UINT64_C(623740928), // DECP_XP_B |
| 1012 | UINT64_C(636323840), // DECP_XP_D |
| 1013 | UINT64_C(627935232), // DECP_XP_H |
| 1014 | UINT64_C(632129536), // DECP_XP_S |
| 1015 | UINT64_C(636321792), // DECP_ZP_D |
| 1016 | UINT64_C(627933184), // DECP_ZP_H |
| 1017 | UINT64_C(632127488), // DECP_ZP_S |
| 1018 | UINT64_C(78701568), // DECW_XPiI |
| 1019 | UINT64_C(78693376), // DECW_ZPiI |
| 1020 | UINT64_C(3573756095), // DMB |
| 1021 | UINT64_C(3602842592), // DRPS |
| 1022 | UINT64_C(3573756063), // DSB |
| 1023 | UINT64_C(3573756479), // DSBnXS |
| 1024 | UINT64_C(96468992), // DUPM_ZI |
| 1025 | UINT64_C(86057984), // DUPQ_ZZI_B |
| 1026 | UINT64_C(86516736), // DUPQ_ZZI_D |
| 1027 | UINT64_C(86123520), // DUPQ_ZZI_H |
| 1028 | UINT64_C(86254592), // DUPQ_ZZI_S |
| 1029 | UINT64_C(624476160), // DUP_ZI_B |
| 1030 | UINT64_C(637059072), // DUP_ZI_D |
| 1031 | UINT64_C(628670464), // DUP_ZI_H |
| 1032 | UINT64_C(632864768), // DUP_ZI_S |
| 1033 | UINT64_C(85997568), // DUP_ZR_B |
| 1034 | UINT64_C(98580480), // DUP_ZR_D |
| 1035 | UINT64_C(90191872), // DUP_ZR_H |
| 1036 | UINT64_C(94386176), // DUP_ZR_S |
| 1037 | UINT64_C(86056960), // DUP_ZZI_B |
| 1038 | UINT64_C(86515712), // DUP_ZZI_D |
| 1039 | UINT64_C(86122496), // DUP_ZZI_H |
| 1040 | UINT64_C(87040000), // DUP_ZZI_Q |
| 1041 | UINT64_C(86253568), // DUP_ZZI_S |
| 1042 | UINT64_C(1577190400), // DUPi16 |
| 1043 | UINT64_C(1577321472), // DUPi32 |
| 1044 | UINT64_C(1577583616), // DUPi64 |
| 1045 | UINT64_C(1577124864), // DUPi8 |
| 1046 | UINT64_C(1308691456), // DUPv16i8gpr |
| 1047 | UINT64_C(1308689408), // DUPv16i8lane |
| 1048 | UINT64_C(235146240), // DUPv2i32gpr |
| 1049 | UINT64_C(235144192), // DUPv2i32lane |
| 1050 | UINT64_C(1309150208), // DUPv2i64gpr |
| 1051 | UINT64_C(1309148160), // DUPv2i64lane |
| 1052 | UINT64_C(235015168), // DUPv4i16gpr |
| 1053 | UINT64_C(235013120), // DUPv4i16lane |
| 1054 | UINT64_C(1308888064), // DUPv4i32gpr |
| 1055 | UINT64_C(1308886016), // DUPv4i32lane |
| 1056 | UINT64_C(1308756992), // DUPv8i16gpr |
| 1057 | UINT64_C(1308754944), // DUPv8i16lane |
| 1058 | UINT64_C(234949632), // DUPv8i8gpr |
| 1059 | UINT64_C(234947584), // DUPv8i8lane |
| 1060 | UINT64_C(1243611136), // EONWrs |
| 1061 | UINT64_C(3391094784), // EONXrs |
| 1062 | UINT64_C(3456106496), // EOR3 |
| 1063 | UINT64_C(69220352), // EOR3_ZZZZ |
| 1064 | UINT64_C(1157664768), // EORBT_ZZZ_B |
| 1065 | UINT64_C(1170247680), // EORBT_ZZZ_D |
| 1066 | UINT64_C(1161859072), // EORBT_ZZZ_H |
| 1067 | UINT64_C(1166053376), // EORBT_ZZZ_S |
| 1068 | UINT64_C(69017600), // EORQV_VPZ_B |
| 1069 | UINT64_C(81600512), // EORQV_VPZ_D |
| 1070 | UINT64_C(73211904), // EORQV_VPZ_H |
| 1071 | UINT64_C(77406208), // EORQV_VPZ_S |
| 1072 | UINT64_C(624968192), // EORS_PPzPP |
| 1073 | UINT64_C(1157665792), // EORTB_ZZZ_B |
| 1074 | UINT64_C(1170248704), // EORTB_ZZZ_D |
| 1075 | UINT64_C(1161860096), // EORTB_ZZZ_H |
| 1076 | UINT64_C(1166054400), // EORTB_ZZZ_S |
| 1077 | UINT64_C(68755456), // EORV_VPZ_B |
| 1078 | UINT64_C(81338368), // EORV_VPZ_D |
| 1079 | UINT64_C(72949760), // EORV_VPZ_H |
| 1080 | UINT64_C(77144064), // EORV_VPZ_S |
| 1081 | UINT64_C(1375731712), // EORWri |
| 1082 | UINT64_C(1241513984), // EORWrs |
| 1083 | UINT64_C(3523215360), // EORXri |
| 1084 | UINT64_C(3388997632), // EORXrs |
| 1085 | UINT64_C(620773888), // EOR_PPzPP |
| 1086 | UINT64_C(88080384), // EOR_ZI |
| 1087 | UINT64_C(68747264), // EOR_ZPmZ_B |
| 1088 | UINT64_C(81330176), // EOR_ZPmZ_D |
| 1089 | UINT64_C(72941568), // EOR_ZPmZ_H |
| 1090 | UINT64_C(77135872), // EOR_ZPmZ_S |
| 1091 | UINT64_C(77606912), // EOR_ZZZ |
| 1092 | UINT64_C(1847598080), // EORv16i8 |
| 1093 | UINT64_C(773856256), // EORv8i8 |
| 1094 | UINT64_C(3600745440), // ERET |
| 1095 | UINT64_C(3600747519), // ERETAA |
| 1096 | UINT64_C(3600748543), // ERETAB |
| 1097 | UINT64_C(87130112), // EXPAND_ZPZ_B |
| 1098 | UINT64_C(99713024), // EXPAND_ZPZ_D |
| 1099 | UINT64_C(91324416), // EXPAND_ZPZ_H |
| 1100 | UINT64_C(95518720), // EXPAND_ZPZ_S |
| 1101 | UINT64_C(90186752), // EXTQ_ZZI |
| 1102 | UINT64_C(3221356544), // EXTRACT_ZPMXI_H_B |
| 1103 | UINT64_C(3233939456), // EXTRACT_ZPMXI_H_D |
| 1104 | UINT64_C(3225550848), // EXTRACT_ZPMXI_H_H |
| 1105 | UINT64_C(3234004992), // EXTRACT_ZPMXI_H_Q |
| 1106 | UINT64_C(3229745152), // EXTRACT_ZPMXI_H_S |
| 1107 | UINT64_C(3221389312), // EXTRACT_ZPMXI_V_B |
| 1108 | UINT64_C(3233972224), // EXTRACT_ZPMXI_V_D |
| 1109 | UINT64_C(3225583616), // EXTRACT_ZPMXI_V_H |
| 1110 | UINT64_C(3234037760), // EXTRACT_ZPMXI_V_Q |
| 1111 | UINT64_C(3229777920), // EXTRACT_ZPMXI_V_S |
| 1112 | UINT64_C(327155712), // EXTRWrri |
| 1113 | UINT64_C(2478833664), // EXTRXrri |
| 1114 | UINT64_C(85983232), // EXT_ZZI |
| 1115 | UINT64_C(90177536), // EXT_ZZI_B |
| 1116 | UINT64_C(1845493760), // EXTv16i8 |
| 1117 | UINT64_C(771751936), // EXTv8i8 |
| 1118 | UINT64_C(773945344), // F1CVTL |
| 1119 | UINT64_C(1847687168), // F1CVTL2 |
| 1120 | UINT64_C(1695100928), // F1CVTLT_ZZ_BtoH |
| 1121 | UINT64_C(3240550401), // F1CVTL_2ZZ_BtoH |
| 1122 | UINT64_C(3240550400), // F1CVT_2ZZ_BtoH |
| 1123 | UINT64_C(1695035392), // F1CVT_ZZ_BtoH |
| 1124 | UINT64_C(778139648), // F2CVTL |
| 1125 | UINT64_C(1851881472), // F2CVTL2 |
| 1126 | UINT64_C(1695101952), // F2CVTLT_ZZ_BtoH |
| 1127 | UINT64_C(3248939009), // F2CVTL_2ZZ_BtoH |
| 1128 | UINT64_C(3248939008), // F2CVT_2ZZ_BtoH |
| 1129 | UINT64_C(1695036416), // F2CVT_ZZ_BtoH |
| 1130 | UINT64_C(2126517248), // FABD16 |
| 1131 | UINT64_C(2124469248), // FABD32 |
| 1132 | UINT64_C(2128663552), // FABD64 |
| 1133 | UINT64_C(1707638784), // FABD_ZPmZ_D |
| 1134 | UINT64_C(1699250176), // FABD_ZPmZ_H |
| 1135 | UINT64_C(1703444480), // FABD_ZPmZ_S |
| 1136 | UINT64_C(782291968), // FABDv2f32 |
| 1137 | UINT64_C(1860228096), // FABDv2f64 |
| 1138 | UINT64_C(784339968), // FABDv4f16 |
| 1139 | UINT64_C(1856033792), // FABDv4f32 |
| 1140 | UINT64_C(1858081792), // FABDv8f16 |
| 1141 | UINT64_C(509657088), // FABSDr |
| 1142 | UINT64_C(518045696), // FABSHr |
| 1143 | UINT64_C(505462784), // FABSSr |
| 1144 | UINT64_C(81567744), // FABS_ZPmZ_D |
| 1145 | UINT64_C(73179136), // FABS_ZPmZ_H |
| 1146 | UINT64_C(77373440), // FABS_ZPmZ_S |
| 1147 | UINT64_C(80519168), // FABS_ZPzZ_D |
| 1148 | UINT64_C(72130560), // FABS_ZPzZ_H |
| 1149 | UINT64_C(76324864), // FABS_ZPzZ_S |
| 1150 | UINT64_C(245430272), // FABSv2f32 |
| 1151 | UINT64_C(1323366400), // FABSv2f64 |
| 1152 | UINT64_C(251197440), // FABSv4f16 |
| 1153 | UINT64_C(1319172096), // FABSv4f32 |
| 1154 | UINT64_C(1324939264), // FABSv8f16 |
| 1155 | UINT64_C(2118134784), // FACGE16 |
| 1156 | UINT64_C(2116086784), // FACGE32 |
| 1157 | UINT64_C(2120281088), // FACGE64 |
| 1158 | UINT64_C(1707130896), // FACGE_PPzZZ_D |
| 1159 | UINT64_C(1698742288), // FACGE_PPzZZ_H |
| 1160 | UINT64_C(1702936592), // FACGE_PPzZZ_S |
| 1161 | UINT64_C(773909504), // FACGEv2f32 |
| 1162 | UINT64_C(1851845632), // FACGEv2f64 |
| 1163 | UINT64_C(775957504), // FACGEv4f16 |
| 1164 | UINT64_C(1847651328), // FACGEv4f32 |
| 1165 | UINT64_C(1849699328), // FACGEv8f16 |
| 1166 | UINT64_C(2126523392), // FACGT16 |
| 1167 | UINT64_C(2124475392), // FACGT32 |
| 1168 | UINT64_C(2128669696), // FACGT64 |
| 1169 | UINT64_C(1707139088), // FACGT_PPzZZ_D |
| 1170 | UINT64_C(1698750480), // FACGT_PPzZZ_H |
| 1171 | UINT64_C(1702944784), // FACGT_PPzZZ_S |
| 1172 | UINT64_C(782298112), // FACGTv2f32 |
| 1173 | UINT64_C(1860234240), // FACGTv2f64 |
| 1174 | UINT64_C(784346112), // FACGTv4f16 |
| 1175 | UINT64_C(1856039936), // FACGTv4f32 |
| 1176 | UINT64_C(1858087936), // FACGTv8f16 |
| 1177 | UINT64_C(1708662784), // FADDA_VPZ_D |
| 1178 | UINT64_C(1700274176), // FADDA_VPZ_H |
| 1179 | UINT64_C(1704468480), // FADDA_VPZ_S |
| 1180 | UINT64_C(509618176), // FADDDrr |
| 1181 | UINT64_C(518006784), // FADDHrr |
| 1182 | UINT64_C(1691385856), // FADDP_ZPmZZ_D |
| 1183 | UINT64_C(1682997248), // FADDP_ZPmZZ_H |
| 1184 | UINT64_C(1687191552), // FADDP_ZPmZZ_S |
| 1185 | UINT64_C(773903360), // FADDPv2f32 |
| 1186 | UINT64_C(1851839488), // FADDPv2f64 |
| 1187 | UINT64_C(1580259328), // FADDPv2i16p |
| 1188 | UINT64_C(2117130240), // FADDPv2i32p |
| 1189 | UINT64_C(2121324544), // FADDPv2i64p |
| 1190 | UINT64_C(775951360), // FADDPv4f16 |
| 1191 | UINT64_C(1847645184), // FADDPv4f32 |
| 1192 | UINT64_C(1849693184), // FADDPv8f16 |
| 1193 | UINT64_C(1691394048), // FADDQV_D |
| 1194 | UINT64_C(1683005440), // FADDQV_H |
| 1195 | UINT64_C(1687199744), // FADDQV_S |
| 1196 | UINT64_C(505423872), // FADDSrr |
| 1197 | UINT64_C(1707089920), // FADDV_VPZ_D |
| 1198 | UINT64_C(1698701312), // FADDV_VPZ_H |
| 1199 | UINT64_C(1702895616), // FADDV_VPZ_S |
| 1200 | UINT64_C(3252689920), // FADD_VG2_M2Z_D |
| 1201 | UINT64_C(3248757760), // FADD_VG2_M2Z_H |
| 1202 | UINT64_C(3248495616), // FADD_VG2_M2Z_S |
| 1203 | UINT64_C(3252755456), // FADD_VG4_M4Z_D |
| 1204 | UINT64_C(3248823296), // FADD_VG4_M4Z_H |
| 1205 | UINT64_C(3248561152), // FADD_VG4_M4Z_S |
| 1206 | UINT64_C(1708687360), // FADD_ZPmI_D |
| 1207 | UINT64_C(1700298752), // FADD_ZPmI_H |
| 1208 | UINT64_C(1704493056), // FADD_ZPmI_S |
| 1209 | UINT64_C(1707114496), // FADD_ZPmZ_D |
| 1210 | UINT64_C(1698725888), // FADD_ZPmZ_H |
| 1211 | UINT64_C(1702920192), // FADD_ZPmZ_S |
| 1212 | UINT64_C(1707081728), // FADD_ZZZ_D |
| 1213 | UINT64_C(1698693120), // FADD_ZZZ_H |
| 1214 | UINT64_C(1702887424), // FADD_ZZZ_S |
| 1215 | UINT64_C(237032448), // FADDv2f32 |
| 1216 | UINT64_C(1314968576), // FADDv2f64 |
| 1217 | UINT64_C(239080448), // FADDv4f16 |
| 1218 | UINT64_C(1310774272), // FADDv4f32 |
| 1219 | UINT64_C(1312822272), // FADDv8f16 |
| 1220 | UINT64_C(3252728128), // FAMAX_2Z2Z_D |
| 1221 | UINT64_C(3244339520), // FAMAX_2Z2Z_H |
| 1222 | UINT64_C(3248533824), // FAMAX_2Z2Z_S |
| 1223 | UINT64_C(3252730176), // FAMAX_4Z4Z_D |
| 1224 | UINT64_C(3244341568), // FAMAX_4Z4Z_H |
| 1225 | UINT64_C(3248535872), // FAMAX_4Z4Z_S |
| 1226 | UINT64_C(1708032000), // FAMAX_ZPmZ_D |
| 1227 | UINT64_C(1699643392), // FAMAX_ZPmZ_H |
| 1228 | UINT64_C(1703837696), // FAMAX_ZPmZ_S |
| 1229 | UINT64_C(245423104), // FAMAXv2f32 |
| 1230 | UINT64_C(1323359232), // FAMAXv2f64 |
| 1231 | UINT64_C(247471104), // FAMAXv4f16 |
| 1232 | UINT64_C(1319164928), // FAMAXv4f32 |
| 1233 | UINT64_C(1321212928), // FAMAXv8f16 |
| 1234 | UINT64_C(3252728129), // FAMIN_2Z2Z_D |
| 1235 | UINT64_C(3244339521), // FAMIN_2Z2Z_H |
| 1236 | UINT64_C(3248533825), // FAMIN_2Z2Z_S |
| 1237 | UINT64_C(3252730177), // FAMIN_4Z4Z_D |
| 1238 | UINT64_C(3244341569), // FAMIN_4Z4Z_H |
| 1239 | UINT64_C(3248535873), // FAMIN_4Z4Z_S |
| 1240 | UINT64_C(1708097536), // FAMIN_ZPmZ_D |
| 1241 | UINT64_C(1699708928), // FAMIN_ZPmZ_H |
| 1242 | UINT64_C(1703903232), // FAMIN_ZPmZ_S |
| 1243 | UINT64_C(782294016), // FAMINv2f32 |
| 1244 | UINT64_C(1860230144), // FAMINv2f64 |
| 1245 | UINT64_C(784342016), // FAMINv4f16 |
| 1246 | UINT64_C(1856035840), // FAMINv4f32 |
| 1247 | UINT64_C(1858083840), // FAMINv8f16 |
| 1248 | UINT64_C(1690337280), // FCADD_ZPmZ_D |
| 1249 | UINT64_C(1681948672), // FCADD_ZPmZ_H |
| 1250 | UINT64_C(1686142976), // FCADD_ZPmZ_S |
| 1251 | UINT64_C(780198912), // FCADDv2f32 |
| 1252 | UINT64_C(1858135040), // FCADDv2f64 |
| 1253 | UINT64_C(776004608), // FCADDv4f16 |
| 1254 | UINT64_C(1853940736), // FCADDv4f32 |
| 1255 | UINT64_C(1849746432), // FCADDv8f16 |
| 1256 | UINT64_C(509608960), // FCCMPDrr |
| 1257 | UINT64_C(509608976), // FCCMPEDrr |
| 1258 | UINT64_C(517997584), // FCCMPEHrr |
| 1259 | UINT64_C(505414672), // FCCMPESrr |
| 1260 | UINT64_C(517997568), // FCCMPHrr |
| 1261 | UINT64_C(505414656), // FCCMPSrr |
| 1262 | UINT64_C(3252731904), // FCLAMP_VG2_2Z2Z_D |
| 1263 | UINT64_C(3244343296), // FCLAMP_VG2_2Z2Z_H |
| 1264 | UINT64_C(3248537600), // FCLAMP_VG2_2Z2Z_S |
| 1265 | UINT64_C(3252733952), // FCLAMP_VG4_4Z4Z_D |
| 1266 | UINT64_C(3244345344), // FCLAMP_VG4_4Z4Z_H |
| 1267 | UINT64_C(3248539648), // FCLAMP_VG4_4Z4Z_S |
| 1268 | UINT64_C(1692410880), // FCLAMP_ZZZ_D |
| 1269 | UINT64_C(1684022272), // FCLAMP_ZZZ_H |
| 1270 | UINT64_C(1688216576), // FCLAMP_ZZZ_S |
| 1271 | UINT64_C(1581261824), // FCMEQ16 |
| 1272 | UINT64_C(1579213824), // FCMEQ32 |
| 1273 | UINT64_C(1583408128), // FCMEQ64 |
| 1274 | UINT64_C(1708269568), // FCMEQ_PPzZ0_D |
| 1275 | UINT64_C(1699880960), // FCMEQ_PPzZ0_H |
| 1276 | UINT64_C(1704075264), // FCMEQ_PPzZ0_S |
| 1277 | UINT64_C(1707106304), // FCMEQ_PPzZZ_D |
| 1278 | UINT64_C(1698717696), // FCMEQ_PPzZZ_H |
| 1279 | UINT64_C(1702912000), // FCMEQ_PPzZZ_S |
| 1280 | UINT64_C(1593366528), // FCMEQv1i16rz |
| 1281 | UINT64_C(1587599360), // FCMEQv1i32rz |
| 1282 | UINT64_C(1591793664), // FCMEQv1i64rz |
| 1283 | UINT64_C(237036544), // FCMEQv2f32 |
| 1284 | UINT64_C(1314972672), // FCMEQv2f64 |
| 1285 | UINT64_C(245422080), // FCMEQv2i32rz |
| 1286 | UINT64_C(1323358208), // FCMEQv2i64rz |
| 1287 | UINT64_C(239084544), // FCMEQv4f16 |
| 1288 | UINT64_C(1310778368), // FCMEQv4f32 |
| 1289 | UINT64_C(251189248), // FCMEQv4i16rz |
| 1290 | UINT64_C(1319163904), // FCMEQv4i32rz |
| 1291 | UINT64_C(1312826368), // FCMEQv8f16 |
| 1292 | UINT64_C(1324931072), // FCMEQv8i16rz |
| 1293 | UINT64_C(2118132736), // FCMGE16 |
| 1294 | UINT64_C(2116084736), // FCMGE32 |
| 1295 | UINT64_C(2120279040), // FCMGE64 |
| 1296 | UINT64_C(1708138496), // FCMGE_PPzZ0_D |
| 1297 | UINT64_C(1699749888), // FCMGE_PPzZ0_H |
| 1298 | UINT64_C(1703944192), // FCMGE_PPzZ0_S |
| 1299 | UINT64_C(1707098112), // FCMGE_PPzZZ_D |
| 1300 | UINT64_C(1698709504), // FCMGE_PPzZZ_H |
| 1301 | UINT64_C(1702903808), // FCMGE_PPzZZ_S |
| 1302 | UINT64_C(2130233344), // FCMGEv1i16rz |
| 1303 | UINT64_C(2124466176), // FCMGEv1i32rz |
| 1304 | UINT64_C(2128660480), // FCMGEv1i64rz |
| 1305 | UINT64_C(773907456), // FCMGEv2f32 |
| 1306 | UINT64_C(1851843584), // FCMGEv2f64 |
| 1307 | UINT64_C(782288896), // FCMGEv2i32rz |
| 1308 | UINT64_C(1860225024), // FCMGEv2i64rz |
| 1309 | UINT64_C(775955456), // FCMGEv4f16 |
| 1310 | UINT64_C(1847649280), // FCMGEv4f32 |
| 1311 | UINT64_C(788056064), // FCMGEv4i16rz |
| 1312 | UINT64_C(1856030720), // FCMGEv4i32rz |
| 1313 | UINT64_C(1849697280), // FCMGEv8f16 |
| 1314 | UINT64_C(1861797888), // FCMGEv8i16rz |
| 1315 | UINT64_C(2126521344), // FCMGT16 |
| 1316 | UINT64_C(2124473344), // FCMGT32 |
| 1317 | UINT64_C(2128667648), // FCMGT64 |
| 1318 | UINT64_C(1708138512), // FCMGT_PPzZ0_D |
| 1319 | UINT64_C(1699749904), // FCMGT_PPzZ0_H |
| 1320 | UINT64_C(1703944208), // FCMGT_PPzZ0_S |
| 1321 | UINT64_C(1707098128), // FCMGT_PPzZZ_D |
| 1322 | UINT64_C(1698709520), // FCMGT_PPzZZ_H |
| 1323 | UINT64_C(1702903824), // FCMGT_PPzZZ_S |
| 1324 | UINT64_C(1593362432), // FCMGTv1i16rz |
| 1325 | UINT64_C(1587595264), // FCMGTv1i32rz |
| 1326 | UINT64_C(1591789568), // FCMGTv1i64rz |
| 1327 | UINT64_C(782296064), // FCMGTv2f32 |
| 1328 | UINT64_C(1860232192), // FCMGTv2f64 |
| 1329 | UINT64_C(245417984), // FCMGTv2i32rz |
| 1330 | UINT64_C(1323354112), // FCMGTv2i64rz |
| 1331 | UINT64_C(784344064), // FCMGTv4f16 |
| 1332 | UINT64_C(1856037888), // FCMGTv4f32 |
| 1333 | UINT64_C(251185152), // FCMGTv4i16rz |
| 1334 | UINT64_C(1319159808), // FCMGTv4i32rz |
| 1335 | UINT64_C(1858085888), // FCMGTv8f16 |
| 1336 | UINT64_C(1324926976), // FCMGTv8i16rz |
| 1337 | UINT64_C(1690304512), // FCMLA_ZPmZZ_D |
| 1338 | UINT64_C(1681915904), // FCMLA_ZPmZZ_H |
| 1339 | UINT64_C(1686110208), // FCMLA_ZPmZZ_S |
| 1340 | UINT64_C(1688211456), // FCMLA_ZZZI_H |
| 1341 | UINT64_C(1692405760), // FCMLA_ZZZI_S |
| 1342 | UINT64_C(780190720), // FCMLAv2f32 |
| 1343 | UINT64_C(1858126848), // FCMLAv2f64 |
| 1344 | UINT64_C(775996416), // FCMLAv4f16 |
| 1345 | UINT64_C(792727552), // FCMLAv4f16_indexed |
| 1346 | UINT64_C(1853932544), // FCMLAv4f32 |
| 1347 | UINT64_C(1870663680), // FCMLAv4f32_indexed |
| 1348 | UINT64_C(1849738240), // FCMLAv8f16 |
| 1349 | UINT64_C(1866469376), // FCMLAv8f16_indexed |
| 1350 | UINT64_C(1708204048), // FCMLE_PPzZ0_D |
| 1351 | UINT64_C(1699815440), // FCMLE_PPzZ0_H |
| 1352 | UINT64_C(1704009744), // FCMLE_PPzZ0_S |
| 1353 | UINT64_C(2130237440), // FCMLEv1i16rz |
| 1354 | UINT64_C(2124470272), // FCMLEv1i32rz |
| 1355 | UINT64_C(2128664576), // FCMLEv1i64rz |
| 1356 | UINT64_C(782292992), // FCMLEv2i32rz |
| 1357 | UINT64_C(1860229120), // FCMLEv2i64rz |
| 1358 | UINT64_C(788060160), // FCMLEv4i16rz |
| 1359 | UINT64_C(1856034816), // FCMLEv4i32rz |
| 1360 | UINT64_C(1861801984), // FCMLEv8i16rz |
| 1361 | UINT64_C(1708204032), // FCMLT_PPzZ0_D |
| 1362 | UINT64_C(1699815424), // FCMLT_PPzZ0_H |
| 1363 | UINT64_C(1704009728), // FCMLT_PPzZ0_S |
| 1364 | UINT64_C(1593370624), // FCMLTv1i16rz |
| 1365 | UINT64_C(1587603456), // FCMLTv1i32rz |
| 1366 | UINT64_C(1591797760), // FCMLTv1i64rz |
| 1367 | UINT64_C(245426176), // FCMLTv2i32rz |
| 1368 | UINT64_C(1323362304), // FCMLTv2i64rz |
| 1369 | UINT64_C(251193344), // FCMLTv4i16rz |
| 1370 | UINT64_C(1319168000), // FCMLTv4i32rz |
| 1371 | UINT64_C(1324935168), // FCMLTv8i16rz |
| 1372 | UINT64_C(1708335104), // FCMNE_PPzZ0_D |
| 1373 | UINT64_C(1699946496), // FCMNE_PPzZ0_H |
| 1374 | UINT64_C(1704140800), // FCMNE_PPzZ0_S |
| 1375 | UINT64_C(1707106320), // FCMNE_PPzZZ_D |
| 1376 | UINT64_C(1698717712), // FCMNE_PPzZZ_H |
| 1377 | UINT64_C(1702912016), // FCMNE_PPzZZ_S |
| 1378 | UINT64_C(509616136), // FCMPDri |
| 1379 | UINT64_C(509616128), // FCMPDrr |
| 1380 | UINT64_C(509616152), // FCMPEDri |
| 1381 | UINT64_C(509616144), // FCMPEDrr |
| 1382 | UINT64_C(518004760), // FCMPEHri |
| 1383 | UINT64_C(518004752), // FCMPEHrr |
| 1384 | UINT64_C(505421848), // FCMPESri |
| 1385 | UINT64_C(505421840), // FCMPESrr |
| 1386 | UINT64_C(518004744), // FCMPHri |
| 1387 | UINT64_C(518004736), // FCMPHrr |
| 1388 | UINT64_C(505421832), // FCMPSri |
| 1389 | UINT64_C(505421824), // FCMPSrr |
| 1390 | UINT64_C(1707130880), // FCMUO_PPzZZ_D |
| 1391 | UINT64_C(1698742272), // FCMUO_PPzZZ_H |
| 1392 | UINT64_C(1702936576), // FCMUO_PPzZZ_S |
| 1393 | UINT64_C(97566720), // FCPY_ZPmI_D |
| 1394 | UINT64_C(89178112), // FCPY_ZPmI_H |
| 1395 | UINT64_C(93372416), // FCPY_ZPmI_S |
| 1396 | UINT64_C(509611008), // FCSELDrrr |
| 1397 | UINT64_C(517999616), // FCSELHrrr |
| 1398 | UINT64_C(505416704), // FCSELSrrr |
| 1399 | UINT64_C(2667184128), // FCVTASDHr |
| 1400 | UINT64_C(2654601216), // FCVTASDSr |
| 1401 | UINT64_C(511311872), // FCVTASSDr |
| 1402 | UINT64_C(519700480), // FCVTASSHr |
| 1403 | UINT64_C(509870080), // FCVTASUWDr |
| 1404 | UINT64_C(518258688), // FCVTASUWHr |
| 1405 | UINT64_C(505675776), // FCVTASUWSr |
| 1406 | UINT64_C(2657353728), // FCVTASUXDr |
| 1407 | UINT64_C(2665742336), // FCVTASUXHr |
| 1408 | UINT64_C(2653159424), // FCVTASUXSr |
| 1409 | UINT64_C(1585039360), // FCVTASv1f16 |
| 1410 | UINT64_C(1579272192), // FCVTASv1i32 |
| 1411 | UINT64_C(1583466496), // FCVTASv1i64 |
| 1412 | UINT64_C(237094912), // FCVTASv2f32 |
| 1413 | UINT64_C(1315031040), // FCVTASv2f64 |
| 1414 | UINT64_C(242862080), // FCVTASv4f16 |
| 1415 | UINT64_C(1310836736), // FCVTASv4f32 |
| 1416 | UINT64_C(1316603904), // FCVTASv8f16 |
| 1417 | UINT64_C(2667249664), // FCVTAUDHr |
| 1418 | UINT64_C(2654666752), // FCVTAUDSr |
| 1419 | UINT64_C(511377408), // FCVTAUSDr |
| 1420 | UINT64_C(519766016), // FCVTAUSHr |
| 1421 | UINT64_C(509935616), // FCVTAUUWDr |
| 1422 | UINT64_C(518324224), // FCVTAUUWHr |
| 1423 | UINT64_C(505741312), // FCVTAUUWSr |
| 1424 | UINT64_C(2657419264), // FCVTAUUXDr |
| 1425 | UINT64_C(2665807872), // FCVTAUUXHr |
| 1426 | UINT64_C(2653224960), // FCVTAUUXSr |
| 1427 | UINT64_C(2121910272), // FCVTAUv1f16 |
| 1428 | UINT64_C(2116143104), // FCVTAUv1i32 |
| 1429 | UINT64_C(2120337408), // FCVTAUv1i64 |
| 1430 | UINT64_C(773965824), // FCVTAUv2f32 |
| 1431 | UINT64_C(1851901952), // FCVTAUv2f64 |
| 1432 | UINT64_C(779732992), // FCVTAUv4f16 |
| 1433 | UINT64_C(1847707648), // FCVTAUv4f32 |
| 1434 | UINT64_C(1853474816), // FCVTAUv8f16 |
| 1435 | UINT64_C(518176768), // FCVTDHr |
| 1436 | UINT64_C(505593856), // FCVTDSr |
| 1437 | UINT64_C(509853696), // FCVTHDr |
| 1438 | UINT64_C(505659392), // FCVTHSr |
| 1439 | UINT64_C(1686740992), // FCVTLT_ZPmZ_HtoS |
| 1440 | UINT64_C(1691066368), // FCVTLT_ZPmZ_StoD |
| 1441 | UINT64_C(1686216704), // FCVTLT_ZPzZ_HtoS |
| 1442 | UINT64_C(1690542080), // FCVTLT_ZPzZ_StoD |
| 1443 | UINT64_C(3248545793), // FCVTL_2ZZ_H_S |
| 1444 | UINT64_C(241268736), // FCVTLv2i32 |
| 1445 | UINT64_C(237074432), // FCVTLv4i16 |
| 1446 | UINT64_C(1315010560), // FCVTLv4i32 |
| 1447 | UINT64_C(1310816256), // FCVTLv8i16 |
| 1448 | UINT64_C(2666790912), // FCVTMSDHr |
| 1449 | UINT64_C(2654208000), // FCVTMSDSr |
| 1450 | UINT64_C(510918656), // FCVTMSSDr |
| 1451 | UINT64_C(519307264), // FCVTMSSHr |
| 1452 | UINT64_C(510656512), // FCVTMSUWDr |
| 1453 | UINT64_C(519045120), // FCVTMSUWHr |
| 1454 | UINT64_C(506462208), // FCVTMSUWSr |
| 1455 | UINT64_C(2658140160), // FCVTMSUXDr |
| 1456 | UINT64_C(2666528768), // FCVTMSUXHr |
| 1457 | UINT64_C(2653945856), // FCVTMSUXSr |
| 1458 | UINT64_C(1585035264), // FCVTMSv1f16 |
| 1459 | UINT64_C(1579268096), // FCVTMSv1i32 |
| 1460 | UINT64_C(1583462400), // FCVTMSv1i64 |
| 1461 | UINT64_C(237090816), // FCVTMSv2f32 |
| 1462 | UINT64_C(1315026944), // FCVTMSv2f64 |
| 1463 | UINT64_C(242857984), // FCVTMSv4f16 |
| 1464 | UINT64_C(1310832640), // FCVTMSv4f32 |
| 1465 | UINT64_C(1316599808), // FCVTMSv8f16 |
| 1466 | UINT64_C(2666856448), // FCVTMUDHr |
| 1467 | UINT64_C(2654273536), // FCVTMUDSr |
| 1468 | UINT64_C(510984192), // FCVTMUSDr |
| 1469 | UINT64_C(519372800), // FCVTMUSHr |
| 1470 | UINT64_C(510722048), // FCVTMUUWDr |
| 1471 | UINT64_C(519110656), // FCVTMUUWHr |
| 1472 | UINT64_C(506527744), // FCVTMUUWSr |
| 1473 | UINT64_C(2658205696), // FCVTMUUXDr |
| 1474 | UINT64_C(2666594304), // FCVTMUUXHr |
| 1475 | UINT64_C(2654011392), // FCVTMUUXSr |
| 1476 | UINT64_C(2121906176), // FCVTMUv1f16 |
| 1477 | UINT64_C(2116139008), // FCVTMUv1i32 |
| 1478 | UINT64_C(2120333312), // FCVTMUv1i64 |
| 1479 | UINT64_C(773961728), // FCVTMUv2f32 |
| 1480 | UINT64_C(1851897856), // FCVTMUv2f64 |
| 1481 | UINT64_C(779728896), // FCVTMUv4f16 |
| 1482 | UINT64_C(1847703552), // FCVTMUv4f32 |
| 1483 | UINT64_C(1853470720), // FCVTMUv8f16 |
| 1484 | UINT64_C(1695167488), // FCVTNB_Z2Z_StoB |
| 1485 | UINT64_C(2666135552), // FCVTNSDHr |
| 1486 | UINT64_C(2653552640), // FCVTNSDSr |
| 1487 | UINT64_C(510263296), // FCVTNSSDr |
| 1488 | UINT64_C(518651904), // FCVTNSSHr |
| 1489 | UINT64_C(509607936), // FCVTNSUWDr |
| 1490 | UINT64_C(517996544), // FCVTNSUWHr |
| 1491 | UINT64_C(505413632), // FCVTNSUWSr |
| 1492 | UINT64_C(2657091584), // FCVTNSUXDr |
| 1493 | UINT64_C(2665480192), // FCVTNSUXHr |
| 1494 | UINT64_C(2652897280), // FCVTNSUXSr |
| 1495 | UINT64_C(1585031168), // FCVTNSv1f16 |
| 1496 | UINT64_C(1579264000), // FCVTNSv1i32 |
| 1497 | UINT64_C(1583458304), // FCVTNSv1i64 |
| 1498 | UINT64_C(237086720), // FCVTNSv2f32 |
| 1499 | UINT64_C(1315022848), // FCVTNSv2f64 |
| 1500 | UINT64_C(242853888), // FCVTNSv4f16 |
| 1501 | UINT64_C(1310828544), // FCVTNSv4f32 |
| 1502 | UINT64_C(1316595712), // FCVTNSv8f16 |
| 1503 | UINT64_C(1695169536), // FCVTNT_Z2Z_StoB |
| 1504 | UINT64_C(1691000832), // FCVTNT_ZPmZ_DtoS |
| 1505 | UINT64_C(1686675456), // FCVTNT_ZPmZ_StoH |
| 1506 | UINT64_C(1690476544), // FCVTNT_ZPzZ_DtoS |
| 1507 | UINT64_C(1686151168), // FCVTNT_ZPzZ_StoH |
| 1508 | UINT64_C(2666201088), // FCVTNUDHr |
| 1509 | UINT64_C(2653618176), // FCVTNUDSr |
| 1510 | UINT64_C(510328832), // FCVTNUSDr |
| 1511 | UINT64_C(518717440), // FCVTNUSHr |
| 1512 | UINT64_C(509673472), // FCVTNUUWDr |
| 1513 | UINT64_C(518062080), // FCVTNUUWHr |
| 1514 | UINT64_C(505479168), // FCVTNUUWSr |
| 1515 | UINT64_C(2657157120), // FCVTNUUXDr |
| 1516 | UINT64_C(2665545728), // FCVTNUUXHr |
| 1517 | UINT64_C(2652962816), // FCVTNUUXSr |
| 1518 | UINT64_C(2121902080), // FCVTNUv1f16 |
| 1519 | UINT64_C(2116134912), // FCVTNUv1i32 |
| 1520 | UINT64_C(2120329216), // FCVTNUv1i64 |
| 1521 | UINT64_C(773957632), // FCVTNUv2f32 |
| 1522 | UINT64_C(1851893760), // FCVTNUv2f64 |
| 1523 | UINT64_C(779724800), // FCVTNUv4f16 |
| 1524 | UINT64_C(1847699456), // FCVTNUv4f32 |
| 1525 | UINT64_C(1853466624), // FCVTNUv8f16 |
| 1526 | UINT64_C(1312879616), // FCVTN_F16v16f8 |
| 1527 | UINT64_C(239137792), // FCVTN_F16v8f8 |
| 1528 | UINT64_C(1308685312), // FCVTN_F322v16f8 |
| 1529 | UINT64_C(234943488), // FCVTN_F32v8f8 |
| 1530 | UINT64_C(1695166464), // FCVTN_Z2Z_HtoB |
| 1531 | UINT64_C(3240157216), // FCVTN_Z2Z_StoH |
| 1532 | UINT64_C(3241467936), // FCVTN_Z4Z_StoB |
| 1533 | UINT64_C(241264640), // FCVTNv2i32 |
| 1534 | UINT64_C(237070336), // FCVTNv4i16 |
| 1535 | UINT64_C(1315006464), // FCVTNv4i32 |
| 1536 | UINT64_C(1310812160), // FCVTNv8i16 |
| 1537 | UINT64_C(2666659840), // FCVTPSDHr |
| 1538 | UINT64_C(2654076928), // FCVTPSDSr |
| 1539 | UINT64_C(510787584), // FCVTPSSDr |
| 1540 | UINT64_C(519176192), // FCVTPSSHr |
| 1541 | UINT64_C(510132224), // FCVTPSUWDr |
| 1542 | UINT64_C(518520832), // FCVTPSUWHr |
| 1543 | UINT64_C(505937920), // FCVTPSUWSr |
| 1544 | UINT64_C(2657615872), // FCVTPSUXDr |
| 1545 | UINT64_C(2666004480), // FCVTPSUXHr |
| 1546 | UINT64_C(2653421568), // FCVTPSUXSr |
| 1547 | UINT64_C(1593419776), // FCVTPSv1f16 |
| 1548 | UINT64_C(1587652608), // FCVTPSv1i32 |
| 1549 | UINT64_C(1591846912), // FCVTPSv1i64 |
| 1550 | UINT64_C(245475328), // FCVTPSv2f32 |
| 1551 | UINT64_C(1323411456), // FCVTPSv2f64 |
| 1552 | UINT64_C(251242496), // FCVTPSv4f16 |
| 1553 | UINT64_C(1319217152), // FCVTPSv4f32 |
| 1554 | UINT64_C(1324984320), // FCVTPSv8f16 |
| 1555 | UINT64_C(2666725376), // FCVTPUDHr |
| 1556 | UINT64_C(2654142464), // FCVTPUDSr |
| 1557 | UINT64_C(510853120), // FCVTPUSDr |
| 1558 | UINT64_C(519241728), // FCVTPUSHr |
| 1559 | UINT64_C(510197760), // FCVTPUUWDr |
| 1560 | UINT64_C(518586368), // FCVTPUUWHr |
| 1561 | UINT64_C(506003456), // FCVTPUUWSr |
| 1562 | UINT64_C(2657681408), // FCVTPUUXDr |
| 1563 | UINT64_C(2666070016), // FCVTPUUXHr |
| 1564 | UINT64_C(2653487104), // FCVTPUUXSr |
| 1565 | UINT64_C(2130290688), // FCVTPUv1f16 |
| 1566 | UINT64_C(2124523520), // FCVTPUv1i32 |
| 1567 | UINT64_C(2128717824), // FCVTPUv1i64 |
| 1568 | UINT64_C(782346240), // FCVTPUv2f32 |
| 1569 | UINT64_C(1860282368), // FCVTPUv2f64 |
| 1570 | UINT64_C(788113408), // FCVTPUv4f16 |
| 1571 | UINT64_C(1856088064), // FCVTPUv4f32 |
| 1572 | UINT64_C(1861855232), // FCVTPUv8f16 |
| 1573 | UINT64_C(509755392), // FCVTSDr |
| 1574 | UINT64_C(518144000), // FCVTSHr |
| 1575 | UINT64_C(1678417920), // FCVTXNT_ZPmZ_DtoS |
| 1576 | UINT64_C(1677893632), // FCVTXNT_ZPzZ_StoD |
| 1577 | UINT64_C(2120312832), // FCVTXNv1i64 |
| 1578 | UINT64_C(778135552), // FCVTXNv2f32 |
| 1579 | UINT64_C(1851877376), // FCVTXNv4f32 |
| 1580 | UINT64_C(1695195136), // FCVTX_ZPmZ_DtoS |
| 1581 | UINT64_C(1679474688), // FCVTX_ZPzZ_DtoS |
| 1582 | UINT64_C(2666921984), // FCVTZSDHr |
| 1583 | UINT64_C(2654339072), // FCVTZSDSr |
| 1584 | UINT64_C(1707945984), // FCVTZSN_Z2Z_DtoS |
| 1585 | UINT64_C(1699557376), // FCVTZSN_Z2Z_HtoB |
| 1586 | UINT64_C(1703751680), // FCVTZSN_Z2Z_StoH |
| 1587 | UINT64_C(511049728), // FCVTZSSDr |
| 1588 | UINT64_C(519438336), // FCVTZSSHr |
| 1589 | UINT64_C(509116416), // FCVTZSSWDri |
| 1590 | UINT64_C(517505024), // FCVTZSSWHri |
| 1591 | UINT64_C(504922112), // FCVTZSSWSri |
| 1592 | UINT64_C(2656567296), // FCVTZSSXDri |
| 1593 | UINT64_C(2664955904), // FCVTZSSXHri |
| 1594 | UINT64_C(2652372992), // FCVTZSSXSri |
| 1595 | UINT64_C(511180800), // FCVTZSUWDr |
| 1596 | UINT64_C(519569408), // FCVTZSUWHr |
| 1597 | UINT64_C(506986496), // FCVTZSUWSr |
| 1598 | UINT64_C(2658664448), // FCVTZSUXDr |
| 1599 | UINT64_C(2667053056), // FCVTZSUXHr |
| 1600 | UINT64_C(2654470144), // FCVTZSUXSr |
| 1601 | UINT64_C(3240222720), // FCVTZS_2Z2Z_StoS |
| 1602 | UINT64_C(3241271296), // FCVTZS_4Z4Z_StoS |
| 1603 | UINT64_C(1709088768), // FCVTZS_ZPmZ_DtoD |
| 1604 | UINT64_C(1708695552), // FCVTZS_ZPmZ_DtoS |
| 1605 | UINT64_C(1700700160), // FCVTZS_ZPmZ_HtoD |
| 1606 | UINT64_C(1700438016), // FCVTZS_ZPmZ_HtoH |
| 1607 | UINT64_C(1700569088), // FCVTZS_ZPmZ_HtoS |
| 1608 | UINT64_C(1708957696), // FCVTZS_ZPmZ_StoD |
| 1609 | UINT64_C(1704763392), // FCVTZS_ZPmZ_StoS |
| 1610 | UINT64_C(1692385280), // FCVTZS_ZPzZ_DtoD |
| 1611 | UINT64_C(1692303360), // FCVTZS_ZPzZ_DtoS |
| 1612 | UINT64_C(1683996672), // FCVTZS_ZPzZ_HtoD |
| 1613 | UINT64_C(1683931136), // FCVTZS_ZPzZ_HtoH |
| 1614 | UINT64_C(1683980288), // FCVTZS_ZPzZ_HtoS |
| 1615 | UINT64_C(1692368896), // FCVTZS_ZPzZ_StoD |
| 1616 | UINT64_C(1688174592), // FCVTZS_ZPzZ_StoS |
| 1617 | UINT64_C(1598094336), // FCVTZSd |
| 1618 | UINT64_C(1594948608), // FCVTZSh |
| 1619 | UINT64_C(1595997184), // FCVTZSs |
| 1620 | UINT64_C(1593423872), // FCVTZSv1f16 |
| 1621 | UINT64_C(1587656704), // FCVTZSv1i32 |
| 1622 | UINT64_C(1591851008), // FCVTZSv1i64 |
| 1623 | UINT64_C(245479424), // FCVTZSv2f32 |
| 1624 | UINT64_C(1323415552), // FCVTZSv2f64 |
| 1625 | UINT64_C(253819904), // FCVTZSv2i32_shift |
| 1626 | UINT64_C(1329658880), // FCVTZSv2i64_shift |
| 1627 | UINT64_C(251246592), // FCVTZSv4f16 |
| 1628 | UINT64_C(1319221248), // FCVTZSv4f32 |
| 1629 | UINT64_C(252771328), // FCVTZSv4i16_shift |
| 1630 | UINT64_C(1327561728), // FCVTZSv4i32_shift |
| 1631 | UINT64_C(1324988416), // FCVTZSv8f16 |
| 1632 | UINT64_C(1326513152), // FCVTZSv8i16_shift |
| 1633 | UINT64_C(2666987520), // FCVTZUDHr |
| 1634 | UINT64_C(2654404608), // FCVTZUDSr |
| 1635 | UINT64_C(1707947008), // FCVTZUN_Z2Z_DtoS |
| 1636 | UINT64_C(1699558400), // FCVTZUN_Z2Z_HtoB |
| 1637 | UINT64_C(1703752704), // FCVTZUN_Z2Z_StoH |
| 1638 | UINT64_C(511115264), // FCVTZUSDr |
| 1639 | UINT64_C(519503872), // FCVTZUSHr |
| 1640 | UINT64_C(509181952), // FCVTZUSWDri |
| 1641 | UINT64_C(517570560), // FCVTZUSWHri |
| 1642 | UINT64_C(504987648), // FCVTZUSWSri |
| 1643 | UINT64_C(2656632832), // FCVTZUSXDri |
| 1644 | UINT64_C(2665021440), // FCVTZUSXHri |
| 1645 | UINT64_C(2652438528), // FCVTZUSXSri |
| 1646 | UINT64_C(511246336), // FCVTZUUWDr |
| 1647 | UINT64_C(519634944), // FCVTZUUWHr |
| 1648 | UINT64_C(507052032), // FCVTZUUWSr |
| 1649 | UINT64_C(2658729984), // FCVTZUUXDr |
| 1650 | UINT64_C(2667118592), // FCVTZUUXHr |
| 1651 | UINT64_C(2654535680), // FCVTZUUXSr |
| 1652 | UINT64_C(3240222752), // FCVTZU_2Z2Z_StoS |
| 1653 | UINT64_C(3241271328), // FCVTZU_4Z4Z_StoS |
| 1654 | UINT64_C(1709154304), // FCVTZU_ZPmZ_DtoD |
| 1655 | UINT64_C(1708761088), // FCVTZU_ZPmZ_DtoS |
| 1656 | UINT64_C(1700765696), // FCVTZU_ZPmZ_HtoD |
| 1657 | UINT64_C(1700503552), // FCVTZU_ZPmZ_HtoH |
| 1658 | UINT64_C(1700634624), // FCVTZU_ZPmZ_HtoS |
| 1659 | UINT64_C(1709023232), // FCVTZU_ZPmZ_StoD |
| 1660 | UINT64_C(1704828928), // FCVTZU_ZPmZ_StoS |
| 1661 | UINT64_C(1692393472), // FCVTZU_ZPzZ_DtoD |
| 1662 | UINT64_C(1692311552), // FCVTZU_ZPzZ_DtoS |
| 1663 | UINT64_C(1684004864), // FCVTZU_ZPzZ_HtoD |
| 1664 | UINT64_C(1683939328), // FCVTZU_ZPzZ_HtoH |
| 1665 | UINT64_C(1683988480), // FCVTZU_ZPzZ_HtoS |
| 1666 | UINT64_C(1692377088), // FCVTZU_ZPzZ_StoD |
| 1667 | UINT64_C(1688182784), // FCVTZU_ZPzZ_StoS |
| 1668 | UINT64_C(2134965248), // FCVTZUd |
| 1669 | UINT64_C(2131819520), // FCVTZUh |
| 1670 | UINT64_C(2132868096), // FCVTZUs |
| 1671 | UINT64_C(2130294784), // FCVTZUv1f16 |
| 1672 | UINT64_C(2124527616), // FCVTZUv1i32 |
| 1673 | UINT64_C(2128721920), // FCVTZUv1i64 |
| 1674 | UINT64_C(782350336), // FCVTZUv2f32 |
| 1675 | UINT64_C(1860286464), // FCVTZUv2f64 |
| 1676 | UINT64_C(790690816), // FCVTZUv2i32_shift |
| 1677 | UINT64_C(1866529792), // FCVTZUv2i64_shift |
| 1678 | UINT64_C(788117504), // FCVTZUv4f16 |
| 1679 | UINT64_C(1856092160), // FCVTZUv4f32 |
| 1680 | UINT64_C(789642240), // FCVTZUv4i16_shift |
| 1681 | UINT64_C(1864432640), // FCVTZUv4i32_shift |
| 1682 | UINT64_C(1861859328), // FCVTZUv8f16 |
| 1683 | UINT64_C(1863384064), // FCVTZUv8i16_shift |
| 1684 | UINT64_C(3248545792), // FCVT_2ZZ_H_S |
| 1685 | UINT64_C(3240419328), // FCVT_Z2Z_HtoB |
| 1686 | UINT64_C(3240157184), // FCVT_Z2Z_StoH |
| 1687 | UINT64_C(3241467904), // FCVT_Z4Z_StoB |
| 1688 | UINT64_C(1707646976), // FCVT_ZPmZ_DtoH |
| 1689 | UINT64_C(1707778048), // FCVT_ZPmZ_DtoS |
| 1690 | UINT64_C(1707712512), // FCVT_ZPmZ_HtoD |
| 1691 | UINT64_C(1703518208), // FCVT_ZPmZ_HtoS |
| 1692 | UINT64_C(1707843584), // FCVT_ZPmZ_StoD |
| 1693 | UINT64_C(1703452672), // FCVT_ZPmZ_StoH |
| 1694 | UINT64_C(1692041216), // FCVT_ZPzZ_DtoH |
| 1695 | UINT64_C(1692057600), // FCVT_ZPzZ_DtoS |
| 1696 | UINT64_C(1692049408), // FCVT_ZPzZ_HtoD |
| 1697 | UINT64_C(1687855104), // FCVT_ZPzZ_HtoS |
| 1698 | UINT64_C(1692065792), // FCVT_ZPzZ_StoD |
| 1699 | UINT64_C(1687846912), // FCVT_ZPzZ_StoH |
| 1700 | UINT64_C(509614080), // FDIVDrr |
| 1701 | UINT64_C(518002688), // FDIVHrr |
| 1702 | UINT64_C(1707900928), // FDIVR_ZPmZ_D |
| 1703 | UINT64_C(1699512320), // FDIVR_ZPmZ_H |
| 1704 | UINT64_C(1703706624), // FDIVR_ZPmZ_S |
| 1705 | UINT64_C(505419776), // FDIVSrr |
| 1706 | UINT64_C(1707966464), // FDIV_ZPmZ_D |
| 1707 | UINT64_C(1699577856), // FDIV_ZPmZ_H |
| 1708 | UINT64_C(1703772160), // FDIV_ZPmZ_S |
| 1709 | UINT64_C(773913600), // FDIVv2f32 |
| 1710 | UINT64_C(1851849728), // FDIVv2f64 |
| 1711 | UINT64_C(775961600), // FDIVv4f16 |
| 1712 | UINT64_C(1847655424), // FDIVv4f32 |
| 1713 | UINT64_C(1849703424), // FDIVv8f16 |
| 1714 | UINT64_C(3248492576), // FDOT_VG2_M2Z2Z_BtoH |
| 1715 | UINT64_C(3248492592), // FDOT_VG2_M2Z2Z_BtoS |
| 1716 | UINT64_C(3248492544), // FDOT_VG2_M2Z2Z_HtoS |
| 1717 | UINT64_C(3251634208), // FDOT_VG2_M2ZZI_BtoH |
| 1718 | UINT64_C(3243245624), // FDOT_VG2_M2ZZI_BtoS |
| 1719 | UINT64_C(3243249672), // FDOT_VG2_M2ZZI_HtoS |
| 1720 | UINT64_C(3240103944), // FDOT_VG2_M2ZZ_BtoH |
| 1721 | UINT64_C(3240103960), // FDOT_VG2_M2ZZ_BtoS |
| 1722 | UINT64_C(3240103936), // FDOT_VG2_M2ZZ_HtoS |
| 1723 | UINT64_C(3248558112), // FDOT_VG4_M4Z4Z_BtoH |
| 1724 | UINT64_C(3248558128), // FDOT_VG4_M4Z4Z_BtoS |
| 1725 | UINT64_C(3248558080), // FDOT_VG4_M4Z4Z_HtoS |
| 1726 | UINT64_C(3239088192), // FDOT_VG4_M4ZZI_BtoH |
| 1727 | UINT64_C(3243278344), // FDOT_VG4_M4ZZI_BtoS |
| 1728 | UINT64_C(3243282440), // FDOT_VG4_M4ZZI_HtoS |
| 1729 | UINT64_C(3241152520), // FDOT_VG4_M4ZZ_BtoH |
| 1730 | UINT64_C(3241152536), // FDOT_VG4_M4ZZ_BtoS |
| 1731 | UINT64_C(3241152512), // FDOT_VG4_M4ZZ_HtoS |
| 1732 | UINT64_C(1679836160), // FDOT_ZZZI_BtoH |
| 1733 | UINT64_C(1684030464), // FDOT_ZZZI_BtoS |
| 1734 | UINT64_C(1679835136), // FDOT_ZZZI_S |
| 1735 | UINT64_C(1679852544), // FDOT_ZZZ_BtoH |
| 1736 | UINT64_C(1684046848), // FDOT_ZZZ_BtoS |
| 1737 | UINT64_C(1679851520), // FDOT_ZZZ_S |
| 1738 | UINT64_C(251658240), // FDOTlanev2f32 |
| 1739 | UINT64_C(255852544), // FDOTlanev4f16 |
| 1740 | UINT64_C(255889408), // FDOTlanev4f16_v2f32 |
| 1741 | UINT64_C(1325400064), // FDOTlanev4f32 |
| 1742 | UINT64_C(1329594368), // FDOTlanev8f16 |
| 1743 | UINT64_C(1329631232), // FDOTlanev8f16_v4f32 |
| 1744 | UINT64_C(234945536), // FDOTv2f32 |
| 1745 | UINT64_C(239139840), // FDOTv4f16 |
| 1746 | UINT64_C(243334144), // FDOTv4f16_v2f32 |
| 1747 | UINT64_C(1308687360), // FDOTv4f32 |
| 1748 | UINT64_C(1312881664), // FDOTv8f16 |
| 1749 | UINT64_C(1317075968), // FDOTv8f16_v4f32 |
| 1750 | UINT64_C(637124608), // FDUP_ZI_D |
| 1751 | UINT64_C(628736000), // FDUP_ZI_H |
| 1752 | UINT64_C(632930304), // FDUP_ZI_S |
| 1753 | UINT64_C(81836032), // FEXPA_ZZ_D |
| 1754 | UINT64_C(73447424), // FEXPA_ZZ_H |
| 1755 | UINT64_C(77641728), // FEXPA_ZZ_S |
| 1756 | UINT64_C(622952448), // FIRSTP_XPP_B |
| 1757 | UINT64_C(635535360), // FIRSTP_XPP_D |
| 1758 | UINT64_C(627146752), // FIRSTP_XPP_H |
| 1759 | UINT64_C(631341056), // FIRSTP_XPP_S |
| 1760 | UINT64_C(511574016), // FJCVTZS |
| 1761 | UINT64_C(1696505856), // FLOGB_ZPmZ_D |
| 1762 | UINT64_C(1696243712), // FLOGB_ZPmZ_H |
| 1763 | UINT64_C(1696374784), // FLOGB_ZPmZ_S |
| 1764 | UINT64_C(1679745024), // FLOGB_ZPzZ_D |
| 1765 | UINT64_C(1679728640), // FLOGB_ZPzZ_H |
| 1766 | UINT64_C(1679736832), // FLOGB_ZPzZ_S |
| 1767 | UINT64_C(3558866960), // FLTcc |
| 1768 | UINT64_C(524288000), // FMADDDrrr |
| 1769 | UINT64_C(532676608), // FMADDHrrr |
| 1770 | UINT64_C(520093696), // FMADDSrrr |
| 1771 | UINT64_C(1709211648), // FMAD_ZPmZZ_D |
| 1772 | UINT64_C(1700823040), // FMAD_ZPmZZ_H |
| 1773 | UINT64_C(1705017344), // FMAD_ZPmZZ_S |
| 1774 | UINT64_C(509626368), // FMAXDrr |
| 1775 | UINT64_C(518014976), // FMAXHrr |
| 1776 | UINT64_C(509634560), // FMAXNMDrr |
| 1777 | UINT64_C(518023168), // FMAXNMHrr |
| 1778 | UINT64_C(1691648000), // FMAXNMP_ZPmZZ_D |
| 1779 | UINT64_C(1683259392), // FMAXNMP_ZPmZZ_H |
| 1780 | UINT64_C(1687453696), // FMAXNMP_ZPmZZ_S |
| 1781 | UINT64_C(773899264), // FMAXNMPv2f32 |
| 1782 | UINT64_C(1851835392), // FMAXNMPv2f64 |
| 1783 | UINT64_C(1580255232), // FMAXNMPv2i16p |
| 1784 | UINT64_C(2117126144), // FMAXNMPv2i32p |
| 1785 | UINT64_C(2121320448), // FMAXNMPv2i64p |
| 1786 | UINT64_C(775947264), // FMAXNMPv4f16 |
| 1787 | UINT64_C(1847641088), // FMAXNMPv4f32 |
| 1788 | UINT64_C(1849689088), // FMAXNMPv8f16 |
| 1789 | UINT64_C(1691656192), // FMAXNMQV_D |
| 1790 | UINT64_C(1683267584), // FMAXNMQV_H |
| 1791 | UINT64_C(1687461888), // FMAXNMQV_S |
| 1792 | UINT64_C(505440256), // FMAXNMSrr |
| 1793 | UINT64_C(1707352064), // FMAXNMV_VPZ_D |
| 1794 | UINT64_C(1698963456), // FMAXNMV_VPZ_H |
| 1795 | UINT64_C(1703157760), // FMAXNMV_VPZ_S |
| 1796 | UINT64_C(238077952), // FMAXNMVv4i16v |
| 1797 | UINT64_C(1848690688), // FMAXNMVv4i32v |
| 1798 | UINT64_C(1311819776), // FMAXNMVv8i16v |
| 1799 | UINT64_C(3252728096), // FMAXNM_VG2_2Z2Z_D |
| 1800 | UINT64_C(3244339488), // FMAXNM_VG2_2Z2Z_H |
| 1801 | UINT64_C(3248533792), // FMAXNM_VG2_2Z2Z_S |
| 1802 | UINT64_C(3252724000), // FMAXNM_VG2_2ZZ_D |
| 1803 | UINT64_C(3244335392), // FMAXNM_VG2_2ZZ_H |
| 1804 | UINT64_C(3248529696), // FMAXNM_VG2_2ZZ_S |
| 1805 | UINT64_C(3252730144), // FMAXNM_VG4_4Z4Z_D |
| 1806 | UINT64_C(3244341536), // FMAXNM_VG4_4Z4Z_H |
| 1807 | UINT64_C(3248535840), // FMAXNM_VG4_4Z4Z_S |
| 1808 | UINT64_C(3252726048), // FMAXNM_VG4_4ZZ_D |
| 1809 | UINT64_C(3244337440), // FMAXNM_VG4_4ZZ_H |
| 1810 | UINT64_C(3248531744), // FMAXNM_VG4_4ZZ_S |
| 1811 | UINT64_C(1708949504), // FMAXNM_ZPmI_D |
| 1812 | UINT64_C(1700560896), // FMAXNM_ZPmI_H |
| 1813 | UINT64_C(1704755200), // FMAXNM_ZPmI_S |
| 1814 | UINT64_C(1707376640), // FMAXNM_ZPmZ_D |
| 1815 | UINT64_C(1698988032), // FMAXNM_ZPmZ_H |
| 1816 | UINT64_C(1703182336), // FMAXNM_ZPmZ_S |
| 1817 | UINT64_C(237028352), // FMAXNMv2f32 |
| 1818 | UINT64_C(1314964480), // FMAXNMv2f64 |
| 1819 | UINT64_C(239076352), // FMAXNMv4f16 |
| 1820 | UINT64_C(1310770176), // FMAXNMv4f32 |
| 1821 | UINT64_C(1312818176), // FMAXNMv8f16 |
| 1822 | UINT64_C(1691779072), // FMAXP_ZPmZZ_D |
| 1823 | UINT64_C(1683390464), // FMAXP_ZPmZZ_H |
| 1824 | UINT64_C(1687584768), // FMAXP_ZPmZZ_S |
| 1825 | UINT64_C(773911552), // FMAXPv2f32 |
| 1826 | UINT64_C(1851847680), // FMAXPv2f64 |
| 1827 | UINT64_C(1580267520), // FMAXPv2i16p |
| 1828 | UINT64_C(2117138432), // FMAXPv2i32p |
| 1829 | UINT64_C(2121332736), // FMAXPv2i64p |
| 1830 | UINT64_C(775959552), // FMAXPv4f16 |
| 1831 | UINT64_C(1847653376), // FMAXPv4f32 |
| 1832 | UINT64_C(1849701376), // FMAXPv8f16 |
| 1833 | UINT64_C(1691787264), // FMAXQV_D |
| 1834 | UINT64_C(1683398656), // FMAXQV_H |
| 1835 | UINT64_C(1687592960), // FMAXQV_S |
| 1836 | UINT64_C(505432064), // FMAXSrr |
| 1837 | UINT64_C(1707483136), // FMAXV_VPZ_D |
| 1838 | UINT64_C(1699094528), // FMAXV_VPZ_H |
| 1839 | UINT64_C(1703288832), // FMAXV_VPZ_S |
| 1840 | UINT64_C(238090240), // FMAXVv4i16v |
| 1841 | UINT64_C(1848702976), // FMAXVv4i32v |
| 1842 | UINT64_C(1311832064), // FMAXVv8i16v |
| 1843 | UINT64_C(3252728064), // FMAX_VG2_2Z2Z_D |
| 1844 | UINT64_C(3244339456), // FMAX_VG2_2Z2Z_H |
| 1845 | UINT64_C(3248533760), // FMAX_VG2_2Z2Z_S |
| 1846 | UINT64_C(3252723968), // FMAX_VG2_2ZZ_D |
| 1847 | UINT64_C(3244335360), // FMAX_VG2_2ZZ_H |
| 1848 | UINT64_C(3248529664), // FMAX_VG2_2ZZ_S |
| 1849 | UINT64_C(3252730112), // FMAX_VG4_4Z4Z_D |
| 1850 | UINT64_C(3244341504), // FMAX_VG4_4Z4Z_H |
| 1851 | UINT64_C(3248535808), // FMAX_VG4_4Z4Z_S |
| 1852 | UINT64_C(3252726016), // FMAX_VG4_4ZZ_D |
| 1853 | UINT64_C(3244337408), // FMAX_VG4_4ZZ_H |
| 1854 | UINT64_C(3248531712), // FMAX_VG4_4ZZ_S |
| 1855 | UINT64_C(1709080576), // FMAX_ZPmI_D |
| 1856 | UINT64_C(1700691968), // FMAX_ZPmI_H |
| 1857 | UINT64_C(1704886272), // FMAX_ZPmI_S |
| 1858 | UINT64_C(1707507712), // FMAX_ZPmZ_D |
| 1859 | UINT64_C(1699119104), // FMAX_ZPmZ_H |
| 1860 | UINT64_C(1703313408), // FMAX_ZPmZ_S |
| 1861 | UINT64_C(237040640), // FMAXv2f32 |
| 1862 | UINT64_C(1314976768), // FMAXv2f64 |
| 1863 | UINT64_C(239088640), // FMAXv4f16 |
| 1864 | UINT64_C(1310782464), // FMAXv4f32 |
| 1865 | UINT64_C(1312830464), // FMAXv8f16 |
| 1866 | UINT64_C(509630464), // FMINDrr |
| 1867 | UINT64_C(518019072), // FMINHrr |
| 1868 | UINT64_C(509638656), // FMINNMDrr |
| 1869 | UINT64_C(518027264), // FMINNMHrr |
| 1870 | UINT64_C(1691713536), // FMINNMP_ZPmZZ_D |
| 1871 | UINT64_C(1683324928), // FMINNMP_ZPmZZ_H |
| 1872 | UINT64_C(1687519232), // FMINNMP_ZPmZZ_S |
| 1873 | UINT64_C(782287872), // FMINNMPv2f32 |
| 1874 | UINT64_C(1860224000), // FMINNMPv2f64 |
| 1875 | UINT64_C(1588643840), // FMINNMPv2i16p |
| 1876 | UINT64_C(2125514752), // FMINNMPv2i32p |
| 1877 | UINT64_C(2129709056), // FMINNMPv2i64p |
| 1878 | UINT64_C(784335872), // FMINNMPv4f16 |
| 1879 | UINT64_C(1856029696), // FMINNMPv4f32 |
| 1880 | UINT64_C(1858077696), // FMINNMPv8f16 |
| 1881 | UINT64_C(1691721728), // FMINNMQV_D |
| 1882 | UINT64_C(1683333120), // FMINNMQV_H |
| 1883 | UINT64_C(1687527424), // FMINNMQV_S |
| 1884 | UINT64_C(505444352), // FMINNMSrr |
| 1885 | UINT64_C(1707417600), // FMINNMV_VPZ_D |
| 1886 | UINT64_C(1699028992), // FMINNMV_VPZ_H |
| 1887 | UINT64_C(1703223296), // FMINNMV_VPZ_S |
| 1888 | UINT64_C(246466560), // FMINNMVv4i16v |
| 1889 | UINT64_C(1857079296), // FMINNMVv4i32v |
| 1890 | UINT64_C(1320208384), // FMINNMVv8i16v |
| 1891 | UINT64_C(3252728097), // FMINNM_VG2_2Z2Z_D |
| 1892 | UINT64_C(3244339489), // FMINNM_VG2_2Z2Z_H |
| 1893 | UINT64_C(3248533793), // FMINNM_VG2_2Z2Z_S |
| 1894 | UINT64_C(3252724001), // FMINNM_VG2_2ZZ_D |
| 1895 | UINT64_C(3244335393), // FMINNM_VG2_2ZZ_H |
| 1896 | UINT64_C(3248529697), // FMINNM_VG2_2ZZ_S |
| 1897 | UINT64_C(3252730145), // FMINNM_VG4_4Z4Z_D |
| 1898 | UINT64_C(3244341537), // FMINNM_VG4_4Z4Z_H |
| 1899 | UINT64_C(3248535841), // FMINNM_VG4_4Z4Z_S |
| 1900 | UINT64_C(3252726049), // FMINNM_VG4_4ZZ_D |
| 1901 | UINT64_C(3244337441), // FMINNM_VG4_4ZZ_H |
| 1902 | UINT64_C(3248531745), // FMINNM_VG4_4ZZ_S |
| 1903 | UINT64_C(1709015040), // FMINNM_ZPmI_D |
| 1904 | UINT64_C(1700626432), // FMINNM_ZPmI_H |
| 1905 | UINT64_C(1704820736), // FMINNM_ZPmI_S |
| 1906 | UINT64_C(1707442176), // FMINNM_ZPmZ_D |
| 1907 | UINT64_C(1699053568), // FMINNM_ZPmZ_H |
| 1908 | UINT64_C(1703247872), // FMINNM_ZPmZ_S |
| 1909 | UINT64_C(245416960), // FMINNMv2f32 |
| 1910 | UINT64_C(1323353088), // FMINNMv2f64 |
| 1911 | UINT64_C(247464960), // FMINNMv4f16 |
| 1912 | UINT64_C(1319158784), // FMINNMv4f32 |
| 1913 | UINT64_C(1321206784), // FMINNMv8f16 |
| 1914 | UINT64_C(1691844608), // FMINP_ZPmZZ_D |
| 1915 | UINT64_C(1683456000), // FMINP_ZPmZZ_H |
| 1916 | UINT64_C(1687650304), // FMINP_ZPmZZ_S |
| 1917 | UINT64_C(782300160), // FMINPv2f32 |
| 1918 | UINT64_C(1860236288), // FMINPv2f64 |
| 1919 | UINT64_C(1588656128), // FMINPv2i16p |
| 1920 | UINT64_C(2125527040), // FMINPv2i32p |
| 1921 | UINT64_C(2129721344), // FMINPv2i64p |
| 1922 | UINT64_C(784348160), // FMINPv4f16 |
| 1923 | UINT64_C(1856041984), // FMINPv4f32 |
| 1924 | UINT64_C(1858089984), // FMINPv8f16 |
| 1925 | UINT64_C(1691852800), // FMINQV_D |
| 1926 | UINT64_C(1683464192), // FMINQV_H |
| 1927 | UINT64_C(1687658496), // FMINQV_S |
| 1928 | UINT64_C(505436160), // FMINSrr |
| 1929 | UINT64_C(1707548672), // FMINV_VPZ_D |
| 1930 | UINT64_C(1699160064), // FMINV_VPZ_H |
| 1931 | UINT64_C(1703354368), // FMINV_VPZ_S |
| 1932 | UINT64_C(246478848), // FMINVv4i16v |
| 1933 | UINT64_C(1857091584), // FMINVv4i32v |
| 1934 | UINT64_C(1320220672), // FMINVv8i16v |
| 1935 | UINT64_C(3252728065), // FMIN_VG2_2Z2Z_D |
| 1936 | UINT64_C(3244339457), // FMIN_VG2_2Z2Z_H |
| 1937 | UINT64_C(3248533761), // FMIN_VG2_2Z2Z_S |
| 1938 | UINT64_C(3252723969), // FMIN_VG2_2ZZ_D |
| 1939 | UINT64_C(3244335361), // FMIN_VG2_2ZZ_H |
| 1940 | UINT64_C(3248529665), // FMIN_VG2_2ZZ_S |
| 1941 | UINT64_C(3252730113), // FMIN_VG4_4Z4Z_D |
| 1942 | UINT64_C(3244341505), // FMIN_VG4_4Z4Z_H |
| 1943 | UINT64_C(3248535809), // FMIN_VG4_4Z4Z_S |
| 1944 | UINT64_C(3252726017), // FMIN_VG4_4ZZ_D |
| 1945 | UINT64_C(3244337409), // FMIN_VG4_4ZZ_H |
| 1946 | UINT64_C(3248531713), // FMIN_VG4_4ZZ_S |
| 1947 | UINT64_C(1709146112), // FMIN_ZPmI_D |
| 1948 | UINT64_C(1700757504), // FMIN_ZPmI_H |
| 1949 | UINT64_C(1704951808), // FMIN_ZPmI_S |
| 1950 | UINT64_C(1707573248), // FMIN_ZPmZ_D |
| 1951 | UINT64_C(1699184640), // FMIN_ZPmZ_H |
| 1952 | UINT64_C(1703378944), // FMIN_ZPmZ_S |
| 1953 | UINT64_C(245429248), // FMINv2f32 |
| 1954 | UINT64_C(1323365376), // FMINv2f64 |
| 1955 | UINT64_C(247477248), // FMINv4f16 |
| 1956 | UINT64_C(1319171072), // FMINv4f32 |
| 1957 | UINT64_C(1321219072), // FMINv8f16 |
| 1958 | UINT64_C(796950528), // FMLAL2lanev4f16 |
| 1959 | UINT64_C(1870692352), // FMLAL2lanev8f16 |
| 1960 | UINT64_C(773901312), // FMLAL2v4f16 |
| 1961 | UINT64_C(1847643136), // FMLAL2v8f16 |
| 1962 | UINT64_C(1688242176), // FMLALB_ZZZ |
| 1963 | UINT64_C(1679839232), // FMLALB_ZZZI |
| 1964 | UINT64_C(1688223744), // FMLALB_ZZZI_SHH |
| 1965 | UINT64_C(1688240128), // FMLALB_ZZZ_SHH |
| 1966 | UINT64_C(264241152), // FMLALBlanev8f16 |
| 1967 | UINT64_C(247528448), // FMLALBv16i8_v8f16 |
| 1968 | UINT64_C(1679853568), // FMLALLBB_ZZZ |
| 1969 | UINT64_C(1679867904), // FMLALLBB_ZZZI |
| 1970 | UINT64_C(788561920), // FMLALLBBlanev4f32 |
| 1971 | UINT64_C(234931200), // FMLALLBBv4f32 |
| 1972 | UINT64_C(1679857664), // FMLALLBT_ZZZ |
| 1973 | UINT64_C(1684062208), // FMLALLBT_ZZZI |
| 1974 | UINT64_C(792756224), // FMLALLBTlanev4f32 |
| 1975 | UINT64_C(239125504), // FMLALLBTv4f32 |
| 1976 | UINT64_C(1679861760), // FMLALLTB_ZZZ |
| 1977 | UINT64_C(1688256512), // FMLALLTB_ZZZI |
| 1978 | UINT64_C(1862303744), // FMLALLTBlanev4f32 |
| 1979 | UINT64_C(1308673024), // FMLALLTBv4f32 |
| 1980 | UINT64_C(1679865856), // FMLALLTT_ZZZ |
| 1981 | UINT64_C(1692450816), // FMLALLTT_ZZZI |
| 1982 | UINT64_C(1866498048), // FMLALLTTlanev4f32 |
| 1983 | UINT64_C(1312867328), // FMLALLTTv4f32 |
| 1984 | UINT64_C(3242196992), // FMLALL_MZZI_BtoS |
| 1985 | UINT64_C(3241149440), // FMLALL_MZZ_BtoS |
| 1986 | UINT64_C(3248488480), // FMLALL_VG2_M2Z2Z_BtoS |
| 1987 | UINT64_C(3247439904), // FMLALL_VG2_M2ZZI_BtoS |
| 1988 | UINT64_C(3240099842), // FMLALL_VG2_M2ZZ_BtoS |
| 1989 | UINT64_C(3248554016), // FMLALL_VG4_M4Z4Z_BtoS |
| 1990 | UINT64_C(3239084096), // FMLALL_VG4_M4ZZI_BtoS |
| 1991 | UINT64_C(3241148418), // FMLALL_VG4_M4ZZ_BtoS |
| 1992 | UINT64_C(1688246272), // FMLALT_ZZZ |
| 1993 | UINT64_C(1688227840), // FMLALT_ZZZI |
| 1994 | UINT64_C(1688224768), // FMLALT_ZZZI_SHH |
| 1995 | UINT64_C(1688241152), // FMLALT_ZZZ_SHH |
| 1996 | UINT64_C(1337982976), // FMLALTlanev8f16 |
| 1997 | UINT64_C(1321270272), // FMLALTv16i8_v8f16 |
| 1998 | UINT64_C(3250585600), // FMLAL_MZZI_BtoH |
| 1999 | UINT64_C(3246395392), // FMLAL_MZZI_HtoS |
| 2000 | UINT64_C(3240102912), // FMLAL_MZZ_HtoS |
| 2001 | UINT64_C(3248490528), // FMLAL_VG2_M2Z2Z_BtoH |
| 2002 | UINT64_C(3248490496), // FMLAL_VG2_M2Z2Z_HtoS |
| 2003 | UINT64_C(3247444016), // FMLAL_VG2_M2ZZI_BtoH |
| 2004 | UINT64_C(3247443968), // FMLAL_VG2_M2ZZI_HtoS |
| 2005 | UINT64_C(3240101892), // FMLAL_VG2_M2ZZ_BtoH |
| 2006 | UINT64_C(3240101888), // FMLAL_VG2_M2ZZ_HtoS |
| 2007 | UINT64_C(3241151488), // FMLAL_VG2_MZZ_BtoH |
| 2008 | UINT64_C(3248556064), // FMLAL_VG4_M4Z4Z_BtoH |
| 2009 | UINT64_C(3248556032), // FMLAL_VG4_M4Z4Z_HtoS |
| 2010 | UINT64_C(3247476768), // FMLAL_VG4_M4ZZI_BtoH |
| 2011 | UINT64_C(3247476736), // FMLAL_VG4_M4ZZI_HtoS |
| 2012 | UINT64_C(3241150468), // FMLAL_VG4_M4ZZ_BtoH |
| 2013 | UINT64_C(3241150464), // FMLAL_VG4_M4ZZ_HtoS |
| 2014 | UINT64_C(260046848), // FMLALlanev4f16 |
| 2015 | UINT64_C(1333788672), // FMLALlanev8f16 |
| 2016 | UINT64_C(237038592), // FMLALv4f16 |
| 2017 | UINT64_C(1310780416), // FMLALv8f16 |
| 2018 | UINT64_C(3252688896), // FMLA_VG2_M2Z2Z_D |
| 2019 | UINT64_C(3248492552), // FMLA_VG2_M2Z2Z_H |
| 2020 | UINT64_C(3248494592), // FMLA_VG2_M2Z2Z_S |
| 2021 | UINT64_C(3251634176), // FMLA_VG2_M2ZZI_D |
| 2022 | UINT64_C(3239055360), // FMLA_VG2_M2ZZI_H |
| 2023 | UINT64_C(3243245568), // FMLA_VG2_M2ZZI_S |
| 2024 | UINT64_C(3244300288), // FMLA_VG2_M2ZZ_D |
| 2025 | UINT64_C(3240107008), // FMLA_VG2_M2ZZ_H |
| 2026 | UINT64_C(3240105984), // FMLA_VG2_M2ZZ_S |
| 2027 | UINT64_C(3252754432), // FMLA_VG4_M4Z4Z_D |
| 2028 | UINT64_C(3248558088), // FMLA_VG4_M4Z4Z_H |
| 2029 | UINT64_C(3248560128), // FMLA_VG4_M4Z4Z_S |
| 2030 | UINT64_C(3251666944), // FMLA_VG4_M4ZZI_D |
| 2031 | UINT64_C(3239088128), // FMLA_VG4_M4ZZI_H |
| 2032 | UINT64_C(3243278336), // FMLA_VG4_M4ZZI_S |
| 2033 | UINT64_C(3245348864), // FMLA_VG4_M4ZZ_D |
| 2034 | UINT64_C(3241155584), // FMLA_VG4_M4ZZ_H |
| 2035 | UINT64_C(3241154560), // FMLA_VG4_M4ZZ_S |
| 2036 | UINT64_C(1709178880), // FMLA_ZPmZZ_D |
| 2037 | UINT64_C(1700790272), // FMLA_ZPmZZ_H |
| 2038 | UINT64_C(1704984576), // FMLA_ZPmZZ_S |
| 2039 | UINT64_C(1692401664), // FMLA_ZZZI_D |
| 2040 | UINT64_C(1679818752), // FMLA_ZZZI_H |
| 2041 | UINT64_C(1688207360), // FMLA_ZZZI_S |
| 2042 | UINT64_C(1593839616), // FMLAv1i16_indexed |
| 2043 | UINT64_C(1602228224), // FMLAv1i32_indexed |
| 2044 | UINT64_C(1606422528), // FMLAv1i64_indexed |
| 2045 | UINT64_C(237030400), // FMLAv2f32 |
| 2046 | UINT64_C(1314966528), // FMLAv2f64 |
| 2047 | UINT64_C(260050944), // FMLAv2i32_indexed |
| 2048 | UINT64_C(1337987072), // FMLAv2i64_indexed |
| 2049 | UINT64_C(239078400), // FMLAv4f16 |
| 2050 | UINT64_C(1310772224), // FMLAv4f32 |
| 2051 | UINT64_C(251662336), // FMLAv4i16_indexed |
| 2052 | UINT64_C(1333792768), // FMLAv4i32_indexed |
| 2053 | UINT64_C(1312820224), // FMLAv8f16 |
| 2054 | UINT64_C(1325404160), // FMLAv8i16_indexed |
| 2055 | UINT64_C(1679877120), // FMLLA_ZZZ_HtoS |
| 2056 | UINT64_C(796966912), // FMLSL2lanev4f16 |
| 2057 | UINT64_C(1870708736), // FMLSL2lanev8f16 |
| 2058 | UINT64_C(782289920), // FMLSL2v4f16 |
| 2059 | UINT64_C(1856031744), // FMLSL2v8f16 |
| 2060 | UINT64_C(1688231936), // FMLSLB_ZZZI_SHH |
| 2061 | UINT64_C(1688248320), // FMLSLB_ZZZ_SHH |
| 2062 | UINT64_C(1688232960), // FMLSLT_ZZZI_SHH |
| 2063 | UINT64_C(1688249344), // FMLSLT_ZZZ_SHH |
| 2064 | UINT64_C(3246395400), // FMLSL_MZZI_HtoS |
| 2065 | UINT64_C(3240102920), // FMLSL_MZZ_HtoS |
| 2066 | UINT64_C(3248490504), // FMLSL_VG2_M2Z2Z_HtoS |
| 2067 | UINT64_C(3247443976), // FMLSL_VG2_M2ZZI_HtoS |
| 2068 | UINT64_C(3240101896), // FMLSL_VG2_M2ZZ_HtoS |
| 2069 | UINT64_C(3248556040), // FMLSL_VG4_M4Z4Z_HtoS |
| 2070 | UINT64_C(3247476744), // FMLSL_VG4_M4ZZI_HtoS |
| 2071 | UINT64_C(3241150472), // FMLSL_VG4_M4ZZ_HtoS |
| 2072 | UINT64_C(260063232), // FMLSLlanev4f16 |
| 2073 | UINT64_C(1333805056), // FMLSLlanev8f16 |
| 2074 | UINT64_C(245427200), // FMLSLv4f16 |
| 2075 | UINT64_C(1319169024), // FMLSLv8f16 |
| 2076 | UINT64_C(3252688904), // FMLS_VG2_M2Z2Z_D |
| 2077 | UINT64_C(3248492568), // FMLS_VG2_M2Z2Z_H |
| 2078 | UINT64_C(3248494600), // FMLS_VG2_M2Z2Z_S |
| 2079 | UINT64_C(3251634192), // FMLS_VG2_M2ZZI_D |
| 2080 | UINT64_C(3239055376), // FMLS_VG2_M2ZZI_H |
| 2081 | UINT64_C(3243245584), // FMLS_VG2_M2ZZI_S |
| 2082 | UINT64_C(3244300296), // FMLS_VG2_M2ZZ_D |
| 2083 | UINT64_C(3240107016), // FMLS_VG2_M2ZZ_H |
| 2084 | UINT64_C(3240105992), // FMLS_VG2_M2ZZ_S |
| 2085 | UINT64_C(3252754440), // FMLS_VG4_M4Z4Z_D |
| 2086 | UINT64_C(3248558104), // FMLS_VG4_M4Z4Z_H |
| 2087 | UINT64_C(3248560136), // FMLS_VG4_M4Z4Z_S |
| 2088 | UINT64_C(3251666960), // FMLS_VG4_M4ZZI_D |
| 2089 | UINT64_C(3239088144), // FMLS_VG4_M4ZZI_H |
| 2090 | UINT64_C(3243278352), // FMLS_VG4_M4ZZI_S |
| 2091 | UINT64_C(3245348872), // FMLS_VG4_M4ZZ_D |
| 2092 | UINT64_C(3241155592), // FMLS_VG4_M4ZZ_H |
| 2093 | UINT64_C(3241154568), // FMLS_VG4_M4ZZ_S |
| 2094 | UINT64_C(1709187072), // FMLS_ZPmZZ_D |
| 2095 | UINT64_C(1700798464), // FMLS_ZPmZZ_H |
| 2096 | UINT64_C(1704992768), // FMLS_ZPmZZ_S |
| 2097 | UINT64_C(1692402688), // FMLS_ZZZI_D |
| 2098 | UINT64_C(1679819776), // FMLS_ZZZI_H |
| 2099 | UINT64_C(1688208384), // FMLS_ZZZI_S |
| 2100 | UINT64_C(1593856000), // FMLSv1i16_indexed |
| 2101 | UINT64_C(1602244608), // FMLSv1i32_indexed |
| 2102 | UINT64_C(1606438912), // FMLSv1i64_indexed |
| 2103 | UINT64_C(245419008), // FMLSv2f32 |
| 2104 | UINT64_C(1323355136), // FMLSv2f64 |
| 2105 | UINT64_C(260067328), // FMLSv2i32_indexed |
| 2106 | UINT64_C(1338003456), // FMLSv2i64_indexed |
| 2107 | UINT64_C(247467008), // FMLSv4f16 |
| 2108 | UINT64_C(1319160832), // FMLSv4f32 |
| 2109 | UINT64_C(251678720), // FMLSv4i16_indexed |
| 2110 | UINT64_C(1333809152), // FMLSv4i32_indexed |
| 2111 | UINT64_C(1321208832), // FMLSv8f16 |
| 2112 | UINT64_C(1325420544), // FMLSv8i16_indexed |
| 2113 | UINT64_C(1684070400), // FMMLA_ZZZ_BtoH |
| 2114 | UINT64_C(1679876096), // FMMLA_ZZZ_BtoS |
| 2115 | UINT64_C(1692460032), // FMMLA_ZZZ_D |
| 2116 | UINT64_C(1688264704), // FMMLA_ZZZ_H |
| 2117 | UINT64_C(1688265728), // FMMLA_ZZZ_S |
| 2118 | UINT64_C(1853942784), // FMMLAv4f32 |
| 2119 | UINT64_C(1845554176), // FMMLAv8f16 |
| 2120 | UINT64_C(1312877568), // FMMLAv8f16_v4f32 |
| 2121 | UINT64_C(1321266176), // FMMLAv8f16_v8f16 |
| 2122 | UINT64_C(2150629896), // FMOP4A_M2Z2Z_BtoH |
| 2123 | UINT64_C(2150629888), // FMOP4A_M2Z2Z_BtoS |
| 2124 | UINT64_C(2161115656), // FMOP4A_M2Z2Z_D |
| 2125 | UINT64_C(2165309960), // FMOP4A_M2Z2Z_H |
| 2126 | UINT64_C(2167407104), // FMOP4A_M2Z2Z_HtoS |
| 2127 | UINT64_C(2148532736), // FMOP4A_M2Z2Z_S |
| 2128 | UINT64_C(2149581320), // FMOP4A_M2ZZ_BtoH |
| 2129 | UINT64_C(2149581312), // FMOP4A_M2ZZ_BtoS |
| 2130 | UINT64_C(2160067080), // FMOP4A_M2ZZ_D |
| 2131 | UINT64_C(2164261384), // FMOP4A_M2ZZ_H |
| 2132 | UINT64_C(2166358528), // FMOP4A_M2ZZ_HtoS |
| 2133 | UINT64_C(2147484160), // FMOP4A_M2ZZ_S |
| 2134 | UINT64_C(2150629384), // FMOP4A_MZ2Z_BtoH |
| 2135 | UINT64_C(2150629376), // FMOP4A_MZ2Z_BtoS |
| 2136 | UINT64_C(2161115144), // FMOP4A_MZ2Z_D |
| 2137 | UINT64_C(2165309448), // FMOP4A_MZ2Z_H |
| 2138 | UINT64_C(2167406592), // FMOP4A_MZ2Z_HtoS |
| 2139 | UINT64_C(2148532224), // FMOP4A_MZ2Z_S |
| 2140 | UINT64_C(2149580808), // FMOP4A_MZZ_BtoH |
| 2141 | UINT64_C(2149580800), // FMOP4A_MZZ_BtoS |
| 2142 | UINT64_C(2160066568), // FMOP4A_MZZ_D |
| 2143 | UINT64_C(2164260872), // FMOP4A_MZZ_H |
| 2144 | UINT64_C(2166358016), // FMOP4A_MZZ_HtoS |
| 2145 | UINT64_C(2147483648), // FMOP4A_MZZ_S |
| 2146 | UINT64_C(2161115672), // FMOP4S_M2Z2Z_D |
| 2147 | UINT64_C(2165309976), // FMOP4S_M2Z2Z_H |
| 2148 | UINT64_C(2167407120), // FMOP4S_M2Z2Z_HtoS |
| 2149 | UINT64_C(2148532752), // FMOP4S_M2Z2Z_S |
| 2150 | UINT64_C(2160067096), // FMOP4S_M2ZZ_D |
| 2151 | UINT64_C(2164261400), // FMOP4S_M2ZZ_H |
| 2152 | UINT64_C(2166358544), // FMOP4S_M2ZZ_HtoS |
| 2153 | UINT64_C(2147484176), // FMOP4S_M2ZZ_S |
| 2154 | UINT64_C(2161115160), // FMOP4S_MZ2Z_D |
| 2155 | UINT64_C(2165309464), // FMOP4S_MZ2Z_H |
| 2156 | UINT64_C(2167406608), // FMOP4S_MZ2Z_HtoS |
| 2157 | UINT64_C(2148532240), // FMOP4S_MZ2Z_S |
| 2158 | UINT64_C(2160066584), // FMOP4S_MZZ_D |
| 2159 | UINT64_C(2164260888), // FMOP4S_MZZ_H |
| 2160 | UINT64_C(2166358032), // FMOP4S_MZZ_HtoS |
| 2161 | UINT64_C(2147483664), // FMOP4S_MZZ_S |
| 2162 | UINT64_C(2174746624), // FMOPAL_MPPZZ |
| 2163 | UINT64_C(2157969416), // FMOPA_MPPZZ_BtoH |
| 2164 | UINT64_C(2157969408), // FMOPA_MPPZZ_BtoS |
| 2165 | UINT64_C(2160066560), // FMOPA_MPPZZ_D |
| 2166 | UINT64_C(2172649480), // FMOPA_MPPZZ_H |
| 2167 | UINT64_C(2155872256), // FMOPA_MPPZZ_S |
| 2168 | UINT64_C(2174746640), // FMOPSL_MPPZZ |
| 2169 | UINT64_C(2160066576), // FMOPS_MPPZZ_D |
| 2170 | UINT64_C(2172649496), // FMOPS_MPPZZ_H |
| 2171 | UINT64_C(2155872272), // FMOPS_MPPZZ_S |
| 2172 | UINT64_C(2662203392), // FMOVDXHighr |
| 2173 | UINT64_C(2657484800), // FMOVDXr |
| 2174 | UINT64_C(509612032), // FMOVDi |
| 2175 | UINT64_C(509624320), // FMOVDr |
| 2176 | UINT64_C(518389760), // FMOVHWr |
| 2177 | UINT64_C(2665873408), // FMOVHXr |
| 2178 | UINT64_C(518000640), // FMOVHi |
| 2179 | UINT64_C(518012928), // FMOVHr |
| 2180 | UINT64_C(505806848), // FMOVSWr |
| 2181 | UINT64_C(505417728), // FMOVSi |
| 2182 | UINT64_C(505430016), // FMOVSr |
| 2183 | UINT64_C(518455296), // FMOVWHr |
| 2184 | UINT64_C(505872384), // FMOVWSr |
| 2185 | UINT64_C(2662268928), // FMOVXDHighr |
| 2186 | UINT64_C(2657550336), // FMOVXDr |
| 2187 | UINT64_C(2665938944), // FMOVXHr |
| 2188 | UINT64_C(251720704), // FMOVv2f32_ns |
| 2189 | UINT64_C(1862333440), // FMOVv2f64_ns |
| 2190 | UINT64_C(251722752), // FMOVv4f16_ns |
| 2191 | UINT64_C(1325462528), // FMOVv4f32_ns |
| 2192 | UINT64_C(1325464576), // FMOVv8f16_ns |
| 2193 | UINT64_C(1709219840), // FMSB_ZPmZZ_D |
| 2194 | UINT64_C(1700831232), // FMSB_ZPmZZ_H |
| 2195 | UINT64_C(1705025536), // FMSB_ZPmZZ_S |
| 2196 | UINT64_C(524320768), // FMSUBDrrr |
| 2197 | UINT64_C(532709376), // FMSUBHrrr |
| 2198 | UINT64_C(520126464), // FMSUBSrrr |
| 2199 | UINT64_C(509609984), // FMULDrr |
| 2200 | UINT64_C(517998592), // FMULHrr |
| 2201 | UINT64_C(505415680), // FMULSrr |
| 2202 | UINT64_C(1581259776), // FMULX16 |
| 2203 | UINT64_C(1579211776), // FMULX32 |
| 2204 | UINT64_C(1583406080), // FMULX64 |
| 2205 | UINT64_C(1707769856), // FMULX_ZPmZ_D |
| 2206 | UINT64_C(1699381248), // FMULX_ZPmZ_H |
| 2207 | UINT64_C(1703575552), // FMULX_ZPmZ_S |
| 2208 | UINT64_C(2130743296), // FMULXv1i16_indexed |
| 2209 | UINT64_C(2139131904), // FMULXv1i32_indexed |
| 2210 | UINT64_C(2143326208), // FMULXv1i64_indexed |
| 2211 | UINT64_C(237034496), // FMULXv2f32 |
| 2212 | UINT64_C(1314970624), // FMULXv2f64 |
| 2213 | UINT64_C(796954624), // FMULXv2i32_indexed |
| 2214 | UINT64_C(1874890752), // FMULXv2i64_indexed |
| 2215 | UINT64_C(239082496), // FMULXv4f16 |
| 2216 | UINT64_C(1310776320), // FMULXv4f32 |
| 2217 | UINT64_C(788566016), // FMULXv4i16_indexed |
| 2218 | UINT64_C(1870696448), // FMULXv4i32_indexed |
| 2219 | UINT64_C(1312824320), // FMULXv8f16 |
| 2220 | UINT64_C(1862307840), // FMULXv8i16_indexed |
| 2221 | UINT64_C(3252741120), // FMUL_2Z2Z_D |
| 2222 | UINT64_C(3244352512), // FMUL_2Z2Z_H |
| 2223 | UINT64_C(3248546816), // FMUL_2Z2Z_S |
| 2224 | UINT64_C(3252742144), // FMUL_2ZZ_D |
| 2225 | UINT64_C(3244353536), // FMUL_2ZZ_H |
| 2226 | UINT64_C(3248547840), // FMUL_2ZZ_S |
| 2227 | UINT64_C(3252806656), // FMUL_4Z4Z_D |
| 2228 | UINT64_C(3244418048), // FMUL_4Z4Z_H |
| 2229 | UINT64_C(3248612352), // FMUL_4Z4Z_S |
| 2230 | UINT64_C(3252807680), // FMUL_4ZZ_D |
| 2231 | UINT64_C(3244419072), // FMUL_4ZZ_H |
| 2232 | UINT64_C(3248613376), // FMUL_4ZZ_S |
| 2233 | UINT64_C(1708818432), // FMUL_ZPmI_D |
| 2234 | UINT64_C(1700429824), // FMUL_ZPmI_H |
| 2235 | UINT64_C(1704624128), // FMUL_ZPmI_S |
| 2236 | UINT64_C(1707245568), // FMUL_ZPmZ_D |
| 2237 | UINT64_C(1698856960), // FMUL_ZPmZ_H |
| 2238 | UINT64_C(1703051264), // FMUL_ZPmZ_S |
| 2239 | UINT64_C(1692409856), // FMUL_ZZZI_D |
| 2240 | UINT64_C(1679826944), // FMUL_ZZZI_H |
| 2241 | UINT64_C(1688215552), // FMUL_ZZZI_S |
| 2242 | UINT64_C(1707083776), // FMUL_ZZZ_D |
| 2243 | UINT64_C(1698695168), // FMUL_ZZZ_H |
| 2244 | UINT64_C(1702889472), // FMUL_ZZZ_S |
| 2245 | UINT64_C(1593872384), // FMULv1i16_indexed |
| 2246 | UINT64_C(1602260992), // FMULv1i32_indexed |
| 2247 | UINT64_C(1606455296), // FMULv1i64_indexed |
| 2248 | UINT64_C(773905408), // FMULv2f32 |
| 2249 | UINT64_C(1851841536), // FMULv2f64 |
| 2250 | UINT64_C(260083712), // FMULv2i32_indexed |
| 2251 | UINT64_C(1338019840), // FMULv2i64_indexed |
| 2252 | UINT64_C(775953408), // FMULv4f16 |
| 2253 | UINT64_C(1847647232), // FMULv4f32 |
| 2254 | UINT64_C(251695104), // FMULv4i16_indexed |
| 2255 | UINT64_C(1333825536), // FMULv4i32_indexed |
| 2256 | UINT64_C(1849695232), // FMULv8f16 |
| 2257 | UINT64_C(1325436928), // FMULv8i16_indexed |
| 2258 | UINT64_C(509689856), // FNEGDr |
| 2259 | UINT64_C(518078464), // FNEGHr |
| 2260 | UINT64_C(505495552), // FNEGSr |
| 2261 | UINT64_C(81633280), // FNEG_ZPmZ_D |
| 2262 | UINT64_C(73244672), // FNEG_ZPmZ_H |
| 2263 | UINT64_C(77438976), // FNEG_ZPmZ_S |
| 2264 | UINT64_C(80584704), // FNEG_ZPzZ_D |
| 2265 | UINT64_C(72196096), // FNEG_ZPzZ_H |
| 2266 | UINT64_C(76390400), // FNEG_ZPzZ_S |
| 2267 | UINT64_C(782301184), // FNEGv2f32 |
| 2268 | UINT64_C(1860237312), // FNEGv2f64 |
| 2269 | UINT64_C(788068352), // FNEGv4f16 |
| 2270 | UINT64_C(1856043008), // FNEGv4f32 |
| 2271 | UINT64_C(1861810176), // FNEGv8f16 |
| 2272 | UINT64_C(526385152), // FNMADDDrrr |
| 2273 | UINT64_C(534773760), // FNMADDHrrr |
| 2274 | UINT64_C(522190848), // FNMADDSrrr |
| 2275 | UINT64_C(1709228032), // FNMAD_ZPmZZ_D |
| 2276 | UINT64_C(1700839424), // FNMAD_ZPmZZ_H |
| 2277 | UINT64_C(1705033728), // FNMAD_ZPmZZ_S |
| 2278 | UINT64_C(1709195264), // FNMLA_ZPmZZ_D |
| 2279 | UINT64_C(1700806656), // FNMLA_ZPmZZ_H |
| 2280 | UINT64_C(1705000960), // FNMLA_ZPmZZ_S |
| 2281 | UINT64_C(1709203456), // FNMLS_ZPmZZ_D |
| 2282 | UINT64_C(1700814848), // FNMLS_ZPmZZ_H |
| 2283 | UINT64_C(1705009152), // FNMLS_ZPmZZ_S |
| 2284 | UINT64_C(1709236224), // FNMSB_ZPmZZ_D |
| 2285 | UINT64_C(1700847616), // FNMSB_ZPmZZ_H |
| 2286 | UINT64_C(1705041920), // FNMSB_ZPmZZ_S |
| 2287 | UINT64_C(526417920), // FNMSUBDrrr |
| 2288 | UINT64_C(534806528), // FNMSUBHrrr |
| 2289 | UINT64_C(522223616), // FNMSUBSrrr |
| 2290 | UINT64_C(509642752), // FNMULDrr |
| 2291 | UINT64_C(518031360), // FNMULHrr |
| 2292 | UINT64_C(505448448), // FNMULSrr |
| 2293 | UINT64_C(1708011520), // FRECPE_ZZ_D |
| 2294 | UINT64_C(1699622912), // FRECPE_ZZ_H |
| 2295 | UINT64_C(1703817216), // FRECPE_ZZ_S |
| 2296 | UINT64_C(1593432064), // FRECPEv1f16 |
| 2297 | UINT64_C(1587664896), // FRECPEv1i32 |
| 2298 | UINT64_C(1591859200), // FRECPEv1i64 |
| 2299 | UINT64_C(245487616), // FRECPEv2f32 |
| 2300 | UINT64_C(1323423744), // FRECPEv2f64 |
| 2301 | UINT64_C(251254784), // FRECPEv4f16 |
| 2302 | UINT64_C(1319229440), // FRECPEv4f32 |
| 2303 | UINT64_C(1324996608), // FRECPEv8f16 |
| 2304 | UINT64_C(1581267968), // FRECPS16 |
| 2305 | UINT64_C(1579219968), // FRECPS32 |
| 2306 | UINT64_C(1583414272), // FRECPS64 |
| 2307 | UINT64_C(1707087872), // FRECPS_ZZZ_D |
| 2308 | UINT64_C(1698699264), // FRECPS_ZZZ_H |
| 2309 | UINT64_C(1702893568), // FRECPS_ZZZ_S |
| 2310 | UINT64_C(237042688), // FRECPSv2f32 |
| 2311 | UINT64_C(1314978816), // FRECPSv2f64 |
| 2312 | UINT64_C(239090688), // FRECPSv4f16 |
| 2313 | UINT64_C(1310784512), // FRECPSv4f32 |
| 2314 | UINT64_C(1312832512), // FRECPSv8f16 |
| 2315 | UINT64_C(1707909120), // FRECPX_ZPmZ_D |
| 2316 | UINT64_C(1699520512), // FRECPX_ZPmZ_H |
| 2317 | UINT64_C(1703714816), // FRECPX_ZPmZ_S |
| 2318 | UINT64_C(1692106752), // FRECPX_ZPzZ_D |
| 2319 | UINT64_C(1683718144), // FRECPX_ZPzZ_H |
| 2320 | UINT64_C(1687912448), // FRECPX_ZPzZ_S |
| 2321 | UINT64_C(1593440256), // FRECPXv1f16 |
| 2322 | UINT64_C(1587673088), // FRECPXv1i32 |
| 2323 | UINT64_C(1591867392), // FRECPXv1i64 |
| 2324 | UINT64_C(510181376), // FRINT32XDr |
| 2325 | UINT64_C(505987072), // FRINT32XSr |
| 2326 | UINT64_C(1695784960), // FRINT32X_ZPmZ_D |
| 2327 | UINT64_C(1695653888), // FRINT32X_ZPmZ_S |
| 2328 | UINT64_C(1679613952), // FRINT32X_ZPzZ_D |
| 2329 | UINT64_C(1679597568), // FRINT32X_ZPzZ_S |
| 2330 | UINT64_C(773974016), // FRINT32Xv2f32 |
| 2331 | UINT64_C(1851910144), // FRINT32Xv2f64 |
| 2332 | UINT64_C(1847715840), // FRINT32Xv4f32 |
| 2333 | UINT64_C(510148608), // FRINT32ZDr |
| 2334 | UINT64_C(505954304), // FRINT32ZSr |
| 2335 | UINT64_C(1695719424), // FRINT32Z_ZPmZ_D |
| 2336 | UINT64_C(1695588352), // FRINT32Z_ZPmZ_S |
| 2337 | UINT64_C(1679605760), // FRINT32Z_ZPzZ_D |
| 2338 | UINT64_C(1679589376), // FRINT32Z_ZPzZ_S |
| 2339 | UINT64_C(237103104), // FRINT32Zv2f32 |
| 2340 | UINT64_C(1315039232), // FRINT32Zv2f64 |
| 2341 | UINT64_C(1310844928), // FRINT32Zv4f32 |
| 2342 | UINT64_C(510246912), // FRINT64XDr |
| 2343 | UINT64_C(506052608), // FRINT64XSr |
| 2344 | UINT64_C(1696047104), // FRINT64X_ZPmZ_D |
| 2345 | UINT64_C(1695916032), // FRINT64X_ZPmZ_S |
| 2346 | UINT64_C(1679679488), // FRINT64X_ZPzZ_D |
| 2347 | UINT64_C(1679663104), // FRINT64X_ZPzZ_S |
| 2348 | UINT64_C(773978112), // FRINT64Xv2f32 |
| 2349 | UINT64_C(1851914240), // FRINT64Xv2f64 |
| 2350 | UINT64_C(1847719936), // FRINT64Xv4f32 |
| 2351 | UINT64_C(510214144), // FRINT64ZDr |
| 2352 | UINT64_C(506019840), // FRINT64ZSr |
| 2353 | UINT64_C(1695981568), // FRINT64Z_ZPmZ_D |
| 2354 | UINT64_C(1695850496), // FRINT64Z_ZPmZ_S |
| 2355 | UINT64_C(1679671296), // FRINT64Z_ZPzZ_D |
| 2356 | UINT64_C(1679654912), // FRINT64Z_ZPzZ_S |
| 2357 | UINT64_C(237107200), // FRINT64Zv2f32 |
| 2358 | UINT64_C(1315043328), // FRINT64Zv2f64 |
| 2359 | UINT64_C(1310849024), // FRINT64Zv4f32 |
| 2360 | UINT64_C(510017536), // FRINTADr |
| 2361 | UINT64_C(518406144), // FRINTAHr |
| 2362 | UINT64_C(505823232), // FRINTASr |
| 2363 | UINT64_C(3249332224), // FRINTA_2Z2Z_S |
| 2364 | UINT64_C(3250380800), // FRINTA_4Z4Z_S |
| 2365 | UINT64_C(1707384832), // FRINTA_ZPmZ_D |
| 2366 | UINT64_C(1698996224), // FRINTA_ZPmZ_H |
| 2367 | UINT64_C(1703190528), // FRINTA_ZPmZ_S |
| 2368 | UINT64_C(1691975680), // FRINTA_ZPzZ_D |
| 2369 | UINT64_C(1683587072), // FRINTA_ZPzZ_H |
| 2370 | UINT64_C(1687781376), // FRINTA_ZPzZ_S |
| 2371 | UINT64_C(773949440), // FRINTAv2f32 |
| 2372 | UINT64_C(1851885568), // FRINTAv2f64 |
| 2373 | UINT64_C(779716608), // FRINTAv4f16 |
| 2374 | UINT64_C(1847691264), // FRINTAv4f32 |
| 2375 | UINT64_C(1853458432), // FRINTAv8f16 |
| 2376 | UINT64_C(510115840), // FRINTIDr |
| 2377 | UINT64_C(518504448), // FRINTIHr |
| 2378 | UINT64_C(505921536), // FRINTISr |
| 2379 | UINT64_C(1707581440), // FRINTI_ZPmZ_D |
| 2380 | UINT64_C(1699192832), // FRINTI_ZPmZ_H |
| 2381 | UINT64_C(1703387136), // FRINTI_ZPmZ_S |
| 2382 | UINT64_C(1692000256), // FRINTI_ZPzZ_D |
| 2383 | UINT64_C(1683611648), // FRINTI_ZPzZ_H |
| 2384 | UINT64_C(1687805952), // FRINTI_ZPzZ_S |
| 2385 | UINT64_C(782342144), // FRINTIv2f32 |
| 2386 | UINT64_C(1860278272), // FRINTIv2f64 |
| 2387 | UINT64_C(788109312), // FRINTIv4f16 |
| 2388 | UINT64_C(1856083968), // FRINTIv4f32 |
| 2389 | UINT64_C(1861851136), // FRINTIv8f16 |
| 2390 | UINT64_C(509952000), // FRINTMDr |
| 2391 | UINT64_C(518340608), // FRINTMHr |
| 2392 | UINT64_C(505757696), // FRINTMSr |
| 2393 | UINT64_C(3249201152), // FRINTM_2Z2Z_S |
| 2394 | UINT64_C(3250249728), // FRINTM_4Z4Z_S |
| 2395 | UINT64_C(1707253760), // FRINTM_ZPmZ_D |
| 2396 | UINT64_C(1698865152), // FRINTM_ZPmZ_H |
| 2397 | UINT64_C(1703059456), // FRINTM_ZPmZ_S |
| 2398 | UINT64_C(1691926528), // FRINTM_ZPzZ_D |
| 2399 | UINT64_C(1683537920), // FRINTM_ZPzZ_H |
| 2400 | UINT64_C(1687732224), // FRINTM_ZPzZ_S |
| 2401 | UINT64_C(237082624), // FRINTMv2f32 |
| 2402 | UINT64_C(1315018752), // FRINTMv2f64 |
| 2403 | UINT64_C(242849792), // FRINTMv4f16 |
| 2404 | UINT64_C(1310824448), // FRINTMv4f32 |
| 2405 | UINT64_C(1316591616), // FRINTMv8f16 |
| 2406 | UINT64_C(509886464), // FRINTNDr |
| 2407 | UINT64_C(518275072), // FRINTNHr |
| 2408 | UINT64_C(505692160), // FRINTNSr |
| 2409 | UINT64_C(3249070080), // FRINTN_2Z2Z_S |
| 2410 | UINT64_C(3250118656), // FRINTN_4Z4Z_S |
| 2411 | UINT64_C(1707122688), // FRINTN_ZPmZ_D |
| 2412 | UINT64_C(1698734080), // FRINTN_ZPmZ_H |
| 2413 | UINT64_C(1702928384), // FRINTN_ZPmZ_S |
| 2414 | UINT64_C(1691910144), // FRINTN_ZPzZ_D |
| 2415 | UINT64_C(1683521536), // FRINTN_ZPzZ_H |
| 2416 | UINT64_C(1687715840), // FRINTN_ZPzZ_S |
| 2417 | UINT64_C(237078528), // FRINTNv2f32 |
| 2418 | UINT64_C(1315014656), // FRINTNv2f64 |
| 2419 | UINT64_C(242845696), // FRINTNv4f16 |
| 2420 | UINT64_C(1310820352), // FRINTNv4f32 |
| 2421 | UINT64_C(1316587520), // FRINTNv8f16 |
| 2422 | UINT64_C(509919232), // FRINTPDr |
| 2423 | UINT64_C(518307840), // FRINTPHr |
| 2424 | UINT64_C(505724928), // FRINTPSr |
| 2425 | UINT64_C(3249135616), // FRINTP_2Z2Z_S |
| 2426 | UINT64_C(3250184192), // FRINTP_4Z4Z_S |
| 2427 | UINT64_C(1707188224), // FRINTP_ZPmZ_D |
| 2428 | UINT64_C(1698799616), // FRINTP_ZPmZ_H |
| 2429 | UINT64_C(1702993920), // FRINTP_ZPmZ_S |
| 2430 | UINT64_C(1691918336), // FRINTP_ZPzZ_D |
| 2431 | UINT64_C(1683529728), // FRINTP_ZPzZ_H |
| 2432 | UINT64_C(1687724032), // FRINTP_ZPzZ_S |
| 2433 | UINT64_C(245467136), // FRINTPv2f32 |
| 2434 | UINT64_C(1323403264), // FRINTPv2f64 |
| 2435 | UINT64_C(251234304), // FRINTPv4f16 |
| 2436 | UINT64_C(1319208960), // FRINTPv4f32 |
| 2437 | UINT64_C(1324976128), // FRINTPv8f16 |
| 2438 | UINT64_C(510083072), // FRINTXDr |
| 2439 | UINT64_C(518471680), // FRINTXHr |
| 2440 | UINT64_C(505888768), // FRINTXSr |
| 2441 | UINT64_C(1707515904), // FRINTX_ZPmZ_D |
| 2442 | UINT64_C(1699127296), // FRINTX_ZPmZ_H |
| 2443 | UINT64_C(1703321600), // FRINTX_ZPmZ_S |
| 2444 | UINT64_C(1691992064), // FRINTX_ZPzZ_D |
| 2445 | UINT64_C(1683603456), // FRINTX_ZPzZ_H |
| 2446 | UINT64_C(1687797760), // FRINTX_ZPzZ_S |
| 2447 | UINT64_C(773953536), // FRINTXv2f32 |
| 2448 | UINT64_C(1851889664), // FRINTXv2f64 |
| 2449 | UINT64_C(779720704), // FRINTXv4f16 |
| 2450 | UINT64_C(1847695360), // FRINTXv4f32 |
| 2451 | UINT64_C(1853462528), // FRINTXv8f16 |
| 2452 | UINT64_C(509984768), // FRINTZDr |
| 2453 | UINT64_C(518373376), // FRINTZHr |
| 2454 | UINT64_C(505790464), // FRINTZSr |
| 2455 | UINT64_C(1707319296), // FRINTZ_ZPmZ_D |
| 2456 | UINT64_C(1698930688), // FRINTZ_ZPmZ_H |
| 2457 | UINT64_C(1703124992), // FRINTZ_ZPmZ_S |
| 2458 | UINT64_C(1691934720), // FRINTZ_ZPzZ_D |
| 2459 | UINT64_C(1683546112), // FRINTZ_ZPzZ_H |
| 2460 | UINT64_C(1687740416), // FRINTZ_ZPzZ_S |
| 2461 | UINT64_C(245471232), // FRINTZv2f32 |
| 2462 | UINT64_C(1323407360), // FRINTZv2f64 |
| 2463 | UINT64_C(251238400), // FRINTZv4f16 |
| 2464 | UINT64_C(1319213056), // FRINTZv4f32 |
| 2465 | UINT64_C(1324980224), // FRINTZv8f16 |
| 2466 | UINT64_C(1708077056), // FRSQRTE_ZZ_D |
| 2467 | UINT64_C(1699688448), // FRSQRTE_ZZ_H |
| 2468 | UINT64_C(1703882752), // FRSQRTE_ZZ_S |
| 2469 | UINT64_C(2130302976), // FRSQRTEv1f16 |
| 2470 | UINT64_C(2124535808), // FRSQRTEv1i32 |
| 2471 | UINT64_C(2128730112), // FRSQRTEv1i64 |
| 2472 | UINT64_C(782358528), // FRSQRTEv2f32 |
| 2473 | UINT64_C(1860294656), // FRSQRTEv2f64 |
| 2474 | UINT64_C(788125696), // FRSQRTEv4f16 |
| 2475 | UINT64_C(1856100352), // FRSQRTEv4f32 |
| 2476 | UINT64_C(1861867520), // FRSQRTEv8f16 |
| 2477 | UINT64_C(1589656576), // FRSQRTS16 |
| 2478 | UINT64_C(1587608576), // FRSQRTS32 |
| 2479 | UINT64_C(1591802880), // FRSQRTS64 |
| 2480 | UINT64_C(1707088896), // FRSQRTS_ZZZ_D |
| 2481 | UINT64_C(1698700288), // FRSQRTS_ZZZ_H |
| 2482 | UINT64_C(1702894592), // FRSQRTS_ZZZ_S |
| 2483 | UINT64_C(245431296), // FRSQRTSv2f32 |
| 2484 | UINT64_C(1323367424), // FRSQRTSv2f64 |
| 2485 | UINT64_C(247479296), // FRSQRTSv4f16 |
| 2486 | UINT64_C(1319173120), // FRSQRTSv4f32 |
| 2487 | UINT64_C(1321221120), // FRSQRTSv8f16 |
| 2488 | UINT64_C(3252728192), // FSCALE_2Z2Z_D |
| 2489 | UINT64_C(3244339584), // FSCALE_2Z2Z_H |
| 2490 | UINT64_C(3248533888), // FSCALE_2Z2Z_S |
| 2491 | UINT64_C(3252724096), // FSCALE_2ZZ_D |
| 2492 | UINT64_C(3244335488), // FSCALE_2ZZ_H |
| 2493 | UINT64_C(3248529792), // FSCALE_2ZZ_S |
| 2494 | UINT64_C(3252730240), // FSCALE_4Z4Z_D |
| 2495 | UINT64_C(3244341632), // FSCALE_4Z4Z_H |
| 2496 | UINT64_C(3248535936), // FSCALE_4Z4Z_S |
| 2497 | UINT64_C(3252726144), // FSCALE_4ZZ_D |
| 2498 | UINT64_C(3244337536), // FSCALE_4ZZ_H |
| 2499 | UINT64_C(3248531840), // FSCALE_4ZZ_S |
| 2500 | UINT64_C(1707704320), // FSCALE_ZPmZ_D |
| 2501 | UINT64_C(1699315712), // FSCALE_ZPmZ_H |
| 2502 | UINT64_C(1703510016), // FSCALE_ZPmZ_S |
| 2503 | UINT64_C(782302208), // FSCALEv2f32 |
| 2504 | UINT64_C(1860238336), // FSCALEv2f64 |
| 2505 | UINT64_C(784350208), // FSCALEv4f16 |
| 2506 | UINT64_C(1856044032), // FSCALEv4f32 |
| 2507 | UINT64_C(1858092032), // FSCALEv8f16 |
| 2508 | UINT64_C(509722624), // FSQRTDr |
| 2509 | UINT64_C(518111232), // FSQRTHr |
| 2510 | UINT64_C(505528320), // FSQRTSr |
| 2511 | UINT64_C(1692114944), // FSQRT_ZPZz_D |
| 2512 | UINT64_C(1683726336), // FSQRT_ZPZz_H |
| 2513 | UINT64_C(1687920640), // FSQRT_ZPZz_S |
| 2514 | UINT64_C(1707974656), // FSQRT_ZPmZ_D |
| 2515 | UINT64_C(1699586048), // FSQRT_ZPmZ_H |
| 2516 | UINT64_C(1703780352), // FSQRT_ZPmZ_S |
| 2517 | UINT64_C(782366720), // FSQRTv2f32 |
| 2518 | UINT64_C(1860302848), // FSQRTv2f64 |
| 2519 | UINT64_C(788133888), // FSQRTv4f16 |
| 2520 | UINT64_C(1856108544), // FSQRTv4f32 |
| 2521 | UINT64_C(1861875712), // FSQRTv8f16 |
| 2522 | UINT64_C(509622272), // FSUBDrr |
| 2523 | UINT64_C(518010880), // FSUBHrr |
| 2524 | UINT64_C(1708883968), // FSUBR_ZPmI_D |
| 2525 | UINT64_C(1700495360), // FSUBR_ZPmI_H |
| 2526 | UINT64_C(1704689664), // FSUBR_ZPmI_S |
| 2527 | UINT64_C(1707311104), // FSUBR_ZPmZ_D |
| 2528 | UINT64_C(1698922496), // FSUBR_ZPmZ_H |
| 2529 | UINT64_C(1703116800), // FSUBR_ZPmZ_S |
| 2530 | UINT64_C(505427968), // FSUBSrr |
| 2531 | UINT64_C(3252689928), // FSUB_VG2_M2Z_D |
| 2532 | UINT64_C(3248757768), // FSUB_VG2_M2Z_H |
| 2533 | UINT64_C(3248495624), // FSUB_VG2_M2Z_S |
| 2534 | UINT64_C(3252755464), // FSUB_VG4_M4Z_D |
| 2535 | UINT64_C(3248823304), // FSUB_VG4_M4Z_H |
| 2536 | UINT64_C(3248561160), // FSUB_VG4_M4Z_S |
| 2537 | UINT64_C(1708752896), // FSUB_ZPmI_D |
| 2538 | UINT64_C(1700364288), // FSUB_ZPmI_H |
| 2539 | UINT64_C(1704558592), // FSUB_ZPmI_S |
| 2540 | UINT64_C(1707180032), // FSUB_ZPmZ_D |
| 2541 | UINT64_C(1698791424), // FSUB_ZPmZ_H |
| 2542 | UINT64_C(1702985728), // FSUB_ZPmZ_S |
| 2543 | UINT64_C(1707082752), // FSUB_ZZZ_D |
| 2544 | UINT64_C(1698694144), // FSUB_ZZZ_H |
| 2545 | UINT64_C(1702888448), // FSUB_ZZZ_S |
| 2546 | UINT64_C(245421056), // FSUBv2f32 |
| 2547 | UINT64_C(1323357184), // FSUBv2f64 |
| 2548 | UINT64_C(247469056), // FSUBv4f16 |
| 2549 | UINT64_C(1319162880), // FSUBv4f32 |
| 2550 | UINT64_C(1321210880), // FSUBv8f16 |
| 2551 | UINT64_C(1708163072), // FTMAD_ZZI_D |
| 2552 | UINT64_C(1699774464), // FTMAD_ZZI_H |
| 2553 | UINT64_C(1703968768), // FTMAD_ZZI_S |
| 2554 | UINT64_C(2153775112), // FTMOPA_M2ZZZI_BtoH |
| 2555 | UINT64_C(2153775104), // FTMOPA_M2ZZZI_BtoS |
| 2556 | UINT64_C(2168455176), // FTMOPA_M2ZZZI_HtoH |
| 2557 | UINT64_C(2170552320), // FTMOPA_M2ZZZI_HtoS |
| 2558 | UINT64_C(2151677952), // FTMOPA_M2ZZZI_StoS |
| 2559 | UINT64_C(1707084800), // FTSMUL_ZZZ_D |
| 2560 | UINT64_C(1698696192), // FTSMUL_ZZZ_H |
| 2561 | UINT64_C(1702890496), // FTSMUL_ZZZ_S |
| 2562 | UINT64_C(81833984), // FTSSEL_ZZZ_D |
| 2563 | UINT64_C(73445376), // FTSSEL_ZZZ_H |
| 2564 | UINT64_C(77639680), // FTSSEL_ZZZ_S |
| 2565 | UINT64_C(3251636224), // FVDOTB_VG4_M2ZZI_BtoS |
| 2566 | UINT64_C(3251636240), // FVDOTT_VG4_M2ZZI_BtoS |
| 2567 | UINT64_C(3251638304), // FVDOT_VG2_M2ZZI_BtoH |
| 2568 | UINT64_C(3243245576), // FVDOT_VG2_M2ZZI_HtoS |
| 2569 | UINT64_C(3574101951), // GCSPOPCX |
| 2570 | UINT64_C(3576395552), // GCSPOPM |
| 2571 | UINT64_C(3574101983), // GCSPOPX |
| 2572 | UINT64_C(3574298368), // GCSPUSHM |
| 2573 | UINT64_C(3574101919), // GCSPUSHX |
| 2574 | UINT64_C(3574298432), // GCSSS1 |
| 2575 | UINT64_C(3576395616), // GCSSS2 |
| 2576 | UINT64_C(3642690560), // GCSSTR |
| 2577 | UINT64_C(3642694656), // GCSSTTR |
| 2578 | UINT64_C(3292577792), // GLD1B_D |
| 2579 | UINT64_C(3290480640), // GLD1B_D_IMM |
| 2580 | UINT64_C(3292545024), // GLD1B_D_SXTW |
| 2581 | UINT64_C(3288350720), // GLD1B_D_UXTW |
| 2582 | UINT64_C(2216738816), // GLD1B_S_IMM |
| 2583 | UINT64_C(2218803200), // GLD1B_S_SXTW |
| 2584 | UINT64_C(2214608896), // GLD1B_S_UXTW |
| 2585 | UINT64_C(3317743616), // GLD1D |
| 2586 | UINT64_C(3315646464), // GLD1D_IMM |
| 2587 | UINT64_C(3319840768), // GLD1D_SCALED |
| 2588 | UINT64_C(3317710848), // GLD1D_SXTW |
| 2589 | UINT64_C(3319808000), // GLD1D_SXTW_SCALED |
| 2590 | UINT64_C(3313516544), // GLD1D_UXTW |
| 2591 | UINT64_C(3315613696), // GLD1D_UXTW_SCALED |
| 2592 | UINT64_C(3300966400), // GLD1H_D |
| 2593 | UINT64_C(3298869248), // GLD1H_D_IMM |
| 2594 | UINT64_C(3303063552), // GLD1H_D_SCALED |
| 2595 | UINT64_C(3300933632), // GLD1H_D_SXTW |
| 2596 | UINT64_C(3303030784), // GLD1H_D_SXTW_SCALED |
| 2597 | UINT64_C(3296739328), // GLD1H_D_UXTW |
| 2598 | UINT64_C(3298836480), // GLD1H_D_UXTW_SCALED |
| 2599 | UINT64_C(2225127424), // GLD1H_S_IMM |
| 2600 | UINT64_C(2227191808), // GLD1H_S_SXTW |
| 2601 | UINT64_C(2229288960), // GLD1H_S_SXTW_SCALED |
| 2602 | UINT64_C(2222997504), // GLD1H_S_UXTW |
| 2603 | UINT64_C(2225094656), // GLD1H_S_UXTW_SCALED |
| 2604 | UINT64_C(3288375296), // GLD1Q |
| 2605 | UINT64_C(3292561408), // GLD1SB_D |
| 2606 | UINT64_C(3290464256), // GLD1SB_D_IMM |
| 2607 | UINT64_C(3292528640), // GLD1SB_D_SXTW |
| 2608 | UINT64_C(3288334336), // GLD1SB_D_UXTW |
| 2609 | UINT64_C(2216722432), // GLD1SB_S_IMM |
| 2610 | UINT64_C(2218786816), // GLD1SB_S_SXTW |
| 2611 | UINT64_C(2214592512), // GLD1SB_S_UXTW |
| 2612 | UINT64_C(3300950016), // GLD1SH_D |
| 2613 | UINT64_C(3298852864), // GLD1SH_D_IMM |
| 2614 | UINT64_C(3303047168), // GLD1SH_D_SCALED |
| 2615 | UINT64_C(3300917248), // GLD1SH_D_SXTW |
| 2616 | UINT64_C(3303014400), // GLD1SH_D_SXTW_SCALED |
| 2617 | UINT64_C(3296722944), // GLD1SH_D_UXTW |
| 2618 | UINT64_C(3298820096), // GLD1SH_D_UXTW_SCALED |
| 2619 | UINT64_C(2225111040), // GLD1SH_S_IMM |
| 2620 | UINT64_C(2227175424), // GLD1SH_S_SXTW |
| 2621 | UINT64_C(2229272576), // GLD1SH_S_SXTW_SCALED |
| 2622 | UINT64_C(2222981120), // GLD1SH_S_UXTW |
| 2623 | UINT64_C(2225078272), // GLD1SH_S_UXTW_SCALED |
| 2624 | UINT64_C(3309338624), // GLD1SW_D |
| 2625 | UINT64_C(3307241472), // GLD1SW_D_IMM |
| 2626 | UINT64_C(3311435776), // GLD1SW_D_SCALED |
| 2627 | UINT64_C(3309305856), // GLD1SW_D_SXTW |
| 2628 | UINT64_C(3311403008), // GLD1SW_D_SXTW_SCALED |
| 2629 | UINT64_C(3305111552), // GLD1SW_D_UXTW |
| 2630 | UINT64_C(3307208704), // GLD1SW_D_UXTW_SCALED |
| 2631 | UINT64_C(3309355008), // GLD1W_D |
| 2632 | UINT64_C(3307257856), // GLD1W_D_IMM |
| 2633 | UINT64_C(3311452160), // GLD1W_D_SCALED |
| 2634 | UINT64_C(3309322240), // GLD1W_D_SXTW |
| 2635 | UINT64_C(3311419392), // GLD1W_D_SXTW_SCALED |
| 2636 | UINT64_C(3305127936), // GLD1W_D_UXTW |
| 2637 | UINT64_C(3307225088), // GLD1W_D_UXTW_SCALED |
| 2638 | UINT64_C(2233516032), // GLD1W_IMM |
| 2639 | UINT64_C(2235580416), // GLD1W_SXTW |
| 2640 | UINT64_C(2237677568), // GLD1W_SXTW_SCALED |
| 2641 | UINT64_C(2231386112), // GLD1W_UXTW |
| 2642 | UINT64_C(2233483264), // GLD1W_UXTW_SCALED |
| 2643 | UINT64_C(3292585984), // GLDFF1B_D |
| 2644 | UINT64_C(3290488832), // GLDFF1B_D_IMM |
| 2645 | UINT64_C(3292553216), // GLDFF1B_D_SXTW |
| 2646 | UINT64_C(3288358912), // GLDFF1B_D_UXTW |
| 2647 | UINT64_C(2216747008), // GLDFF1B_S_IMM |
| 2648 | UINT64_C(2218811392), // GLDFF1B_S_SXTW |
| 2649 | UINT64_C(2214617088), // GLDFF1B_S_UXTW |
| 2650 | UINT64_C(3317751808), // GLDFF1D |
| 2651 | UINT64_C(3315654656), // GLDFF1D_IMM |
| 2652 | UINT64_C(3319848960), // GLDFF1D_SCALED |
| 2653 | UINT64_C(3317719040), // GLDFF1D_SXTW |
| 2654 | UINT64_C(3319816192), // GLDFF1D_SXTW_SCALED |
| 2655 | UINT64_C(3313524736), // GLDFF1D_UXTW |
| 2656 | UINT64_C(3315621888), // GLDFF1D_UXTW_SCALED |
| 2657 | UINT64_C(3300974592), // GLDFF1H_D |
| 2658 | UINT64_C(3298877440), // GLDFF1H_D_IMM |
| 2659 | UINT64_C(3303071744), // GLDFF1H_D_SCALED |
| 2660 | UINT64_C(3300941824), // GLDFF1H_D_SXTW |
| 2661 | UINT64_C(3303038976), // GLDFF1H_D_SXTW_SCALED |
| 2662 | UINT64_C(3296747520), // GLDFF1H_D_UXTW |
| 2663 | UINT64_C(3298844672), // GLDFF1H_D_UXTW_SCALED |
| 2664 | UINT64_C(2225135616), // GLDFF1H_S_IMM |
| 2665 | UINT64_C(2227200000), // GLDFF1H_S_SXTW |
| 2666 | UINT64_C(2229297152), // GLDFF1H_S_SXTW_SCALED |
| 2667 | UINT64_C(2223005696), // GLDFF1H_S_UXTW |
| 2668 | UINT64_C(2225102848), // GLDFF1H_S_UXTW_SCALED |
| 2669 | UINT64_C(3292569600), // GLDFF1SB_D |
| 2670 | UINT64_C(3290472448), // GLDFF1SB_D_IMM |
| 2671 | UINT64_C(3292536832), // GLDFF1SB_D_SXTW |
| 2672 | UINT64_C(3288342528), // GLDFF1SB_D_UXTW |
| 2673 | UINT64_C(2216730624), // GLDFF1SB_S_IMM |
| 2674 | UINT64_C(2218795008), // GLDFF1SB_S_SXTW |
| 2675 | UINT64_C(2214600704), // GLDFF1SB_S_UXTW |
| 2676 | UINT64_C(3300958208), // GLDFF1SH_D |
| 2677 | UINT64_C(3298861056), // GLDFF1SH_D_IMM |
| 2678 | UINT64_C(3303055360), // GLDFF1SH_D_SCALED |
| 2679 | UINT64_C(3300925440), // GLDFF1SH_D_SXTW |
| 2680 | UINT64_C(3303022592), // GLDFF1SH_D_SXTW_SCALED |
| 2681 | UINT64_C(3296731136), // GLDFF1SH_D_UXTW |
| 2682 | UINT64_C(3298828288), // GLDFF1SH_D_UXTW_SCALED |
| 2683 | UINT64_C(2225119232), // GLDFF1SH_S_IMM |
| 2684 | UINT64_C(2227183616), // GLDFF1SH_S_SXTW |
| 2685 | UINT64_C(2229280768), // GLDFF1SH_S_SXTW_SCALED |
| 2686 | UINT64_C(2222989312), // GLDFF1SH_S_UXTW |
| 2687 | UINT64_C(2225086464), // GLDFF1SH_S_UXTW_SCALED |
| 2688 | UINT64_C(3309346816), // GLDFF1SW_D |
| 2689 | UINT64_C(3307249664), // GLDFF1SW_D_IMM |
| 2690 | UINT64_C(3311443968), // GLDFF1SW_D_SCALED |
| 2691 | UINT64_C(3309314048), // GLDFF1SW_D_SXTW |
| 2692 | UINT64_C(3311411200), // GLDFF1SW_D_SXTW_SCALED |
| 2693 | UINT64_C(3305119744), // GLDFF1SW_D_UXTW |
| 2694 | UINT64_C(3307216896), // GLDFF1SW_D_UXTW_SCALED |
| 2695 | UINT64_C(3309363200), // GLDFF1W_D |
| 2696 | UINT64_C(3307266048), // GLDFF1W_D_IMM |
| 2697 | UINT64_C(3311460352), // GLDFF1W_D_SCALED |
| 2698 | UINT64_C(3309330432), // GLDFF1W_D_SXTW |
| 2699 | UINT64_C(3311427584), // GLDFF1W_D_SXTW_SCALED |
| 2700 | UINT64_C(3305136128), // GLDFF1W_D_UXTW |
| 2701 | UINT64_C(3307233280), // GLDFF1W_D_UXTW_SCALED |
| 2702 | UINT64_C(2233524224), // GLDFF1W_IMM |
| 2703 | UINT64_C(2235588608), // GLDFF1W_SXTW |
| 2704 | UINT64_C(2237685760), // GLDFF1W_SXTW_SCALED |
| 2705 | UINT64_C(2231394304), // GLDFF1W_UXTW |
| 2706 | UINT64_C(2233491456), // GLDFF1W_UXTW_SCALED |
| 2707 | UINT64_C(2596279296), // GMI |
| 2708 | UINT64_C(3573751839), // HINT |
| 2709 | UINT64_C(3573555200), // HINTE |
| 2710 | UINT64_C(1172357120), // HISTCNT_ZPzZZ_D |
| 2711 | UINT64_C(1168162816), // HISTCNT_ZPzZZ_S |
| 2712 | UINT64_C(1159766016), // HISTSEG_ZZZ |
| 2713 | UINT64_C(3560964096), // HLT |
| 2714 | UINT64_C(3556769794), // HVC |
| 2715 | UINT64_C(70311936), // INCB_XPiI |
| 2716 | UINT64_C(82894848), // INCD_XPiI |
| 2717 | UINT64_C(82886656), // INCD_ZPiI |
| 2718 | UINT64_C(74506240), // INCH_XPiI |
| 2719 | UINT64_C(74498048), // INCH_ZPiI |
| 2720 | UINT64_C(623675392), // INCP_XP_B |
| 2721 | UINT64_C(636258304), // INCP_XP_D |
| 2722 | UINT64_C(627869696), // INCP_XP_H |
| 2723 | UINT64_C(632064000), // INCP_XP_S |
| 2724 | UINT64_C(636256256), // INCP_ZP_D |
| 2725 | UINT64_C(627867648), // INCP_ZP_H |
| 2726 | UINT64_C(632061952), // INCP_ZP_S |
| 2727 | UINT64_C(78700544), // INCW_XPiI |
| 2728 | UINT64_C(78692352), // INCW_ZPiI |
| 2729 | UINT64_C(69222400), // INDEX_II_B |
| 2730 | UINT64_C(81805312), // INDEX_II_D |
| 2731 | UINT64_C(73416704), // INDEX_II_H |
| 2732 | UINT64_C(77611008), // INDEX_II_S |
| 2733 | UINT64_C(69224448), // INDEX_IR_B |
| 2734 | UINT64_C(81807360), // INDEX_IR_D |
| 2735 | UINT64_C(73418752), // INDEX_IR_H |
| 2736 | UINT64_C(77613056), // INDEX_IR_S |
| 2737 | UINT64_C(69223424), // INDEX_RI_B |
| 2738 | UINT64_C(81806336), // INDEX_RI_D |
| 2739 | UINT64_C(73417728), // INDEX_RI_H |
| 2740 | UINT64_C(77612032), // INDEX_RI_S |
| 2741 | UINT64_C(69225472), // INDEX_RR_B |
| 2742 | UINT64_C(81808384), // INDEX_RR_D |
| 2743 | UINT64_C(73419776), // INDEX_RR_H |
| 2744 | UINT64_C(77614080), // INDEX_RR_S |
| 2745 | UINT64_C(3221225472), // INSERT_MXIPZ_H_B |
| 2746 | UINT64_C(3233808384), // INSERT_MXIPZ_H_D |
| 2747 | UINT64_C(3225419776), // INSERT_MXIPZ_H_H |
| 2748 | UINT64_C(3233873920), // INSERT_MXIPZ_H_Q |
| 2749 | UINT64_C(3229614080), // INSERT_MXIPZ_H_S |
| 2750 | UINT64_C(3221258240), // INSERT_MXIPZ_V_B |
| 2751 | UINT64_C(3233841152), // INSERT_MXIPZ_V_D |
| 2752 | UINT64_C(3225452544), // INSERT_MXIPZ_V_H |
| 2753 | UINT64_C(3233906688), // INSERT_MXIPZ_V_Q |
| 2754 | UINT64_C(3229646848), // INSERT_MXIPZ_V_S |
| 2755 | UINT64_C(86259712), // INSR_ZR_B |
| 2756 | UINT64_C(98842624), // INSR_ZR_D |
| 2757 | UINT64_C(90454016), // INSR_ZR_H |
| 2758 | UINT64_C(94648320), // INSR_ZR_S |
| 2759 | UINT64_C(87308288), // INSR_ZV_B |
| 2760 | UINT64_C(99891200), // INSR_ZV_D |
| 2761 | UINT64_C(91502592), // INSR_ZV_H |
| 2762 | UINT64_C(95696896), // INSR_ZV_S |
| 2763 | UINT64_C(1308761088), // INSvi16gpr |
| 2764 | UINT64_C(1845625856), // INSvi16lane |
| 2765 | UINT64_C(1308892160), // INSvi32gpr |
| 2766 | UINT64_C(1845756928), // INSvi32lane |
| 2767 | UINT64_C(1309154304), // INSvi64gpr |
| 2768 | UINT64_C(1846019072), // INSvi64lane |
| 2769 | UINT64_C(1308695552), // INSvi8gpr |
| 2770 | UINT64_C(1845560320), // INSvi8lane |
| 2771 | UINT64_C(2596278272), // IRG |
| 2772 | UINT64_C(3573756127), // ISB |
| 2773 | UINT64_C(86024192), // LASTA_RPZ_B |
| 2774 | UINT64_C(98607104), // LASTA_RPZ_D |
| 2775 | UINT64_C(90218496), // LASTA_RPZ_H |
| 2776 | UINT64_C(94412800), // LASTA_RPZ_S |
| 2777 | UINT64_C(86147072), // LASTA_VPZ_B |
| 2778 | UINT64_C(98729984), // LASTA_VPZ_D |
| 2779 | UINT64_C(90341376), // LASTA_VPZ_H |
| 2780 | UINT64_C(94535680), // LASTA_VPZ_S |
| 2781 | UINT64_C(86089728), // LASTB_RPZ_B |
| 2782 | UINT64_C(98672640), // LASTB_RPZ_D |
| 2783 | UINT64_C(90284032), // LASTB_RPZ_H |
| 2784 | UINT64_C(94478336), // LASTB_RPZ_S |
| 2785 | UINT64_C(86212608), // LASTB_VPZ_B |
| 2786 | UINT64_C(98795520), // LASTB_VPZ_D |
| 2787 | UINT64_C(90406912), // LASTB_VPZ_H |
| 2788 | UINT64_C(94601216), // LASTB_VPZ_S |
| 2789 | UINT64_C(623017984), // LASTP_XPP_B |
| 2790 | UINT64_C(635600896), // LASTP_XPP_D |
| 2791 | UINT64_C(627212288), // LASTP_XPP_H |
| 2792 | UINT64_C(631406592), // LASTP_XPP_S |
| 2793 | UINT64_C(2751479808), // LD1B |
| 2794 | UINT64_C(2684354560), // LD1B_2Z |
| 2795 | UINT64_C(2688548864), // LD1B_2Z_IMM |
| 2796 | UINT64_C(2701131776), // LD1B_2Z_STRIDED |
| 2797 | UINT64_C(2705326080), // LD1B_2Z_STRIDED_IMM |
| 2798 | UINT64_C(2684387328), // LD1B_4Z |
| 2799 | UINT64_C(2688581632), // LD1B_4Z_IMM |
| 2800 | UINT64_C(2701164544), // LD1B_4Z_STRIDED |
| 2801 | UINT64_C(2705358848), // LD1B_4Z_STRIDED_IMM |
| 2802 | UINT64_C(2757771264), // LD1B_D |
| 2803 | UINT64_C(2757795840), // LD1B_D_IMM |
| 2804 | UINT64_C(2753576960), // LD1B_H |
| 2805 | UINT64_C(2753601536), // LD1B_H_IMM |
| 2806 | UINT64_C(2751504384), // LD1B_IMM |
| 2807 | UINT64_C(2755674112), // LD1B_S |
| 2808 | UINT64_C(2755698688), // LD1B_S_IMM |
| 2809 | UINT64_C(2782937088), // LD1D |
| 2810 | UINT64_C(2684379136), // LD1D_2Z |
| 2811 | UINT64_C(2688573440), // LD1D_2Z_IMM |
| 2812 | UINT64_C(2701156352), // LD1D_2Z_STRIDED |
| 2813 | UINT64_C(2705350656), // LD1D_2Z_STRIDED_IMM |
| 2814 | UINT64_C(2684411904), // LD1D_4Z |
| 2815 | UINT64_C(2688606208), // LD1D_4Z_IMM |
| 2816 | UINT64_C(2701189120), // LD1D_4Z_STRIDED |
| 2817 | UINT64_C(2705383424), // LD1D_4Z_STRIDED_IMM |
| 2818 | UINT64_C(2782961664), // LD1D_IMM |
| 2819 | UINT64_C(2776662016), // LD1D_Q |
| 2820 | UINT64_C(2777686016), // LD1D_Q_IMM |
| 2821 | UINT64_C(1279270912), // LD1Fourv16b |
| 2822 | UINT64_C(1287659520), // LD1Fourv16b_POST |
| 2823 | UINT64_C(205532160), // LD1Fourv1d |
| 2824 | UINT64_C(213920768), // LD1Fourv1d_POST |
| 2825 | UINT64_C(1279273984), // LD1Fourv2d |
| 2826 | UINT64_C(1287662592), // LD1Fourv2d_POST |
| 2827 | UINT64_C(205531136), // LD1Fourv2s |
| 2828 | UINT64_C(213919744), // LD1Fourv2s_POST |
| 2829 | UINT64_C(205530112), // LD1Fourv4h |
| 2830 | UINT64_C(213918720), // LD1Fourv4h_POST |
| 2831 | UINT64_C(1279272960), // LD1Fourv4s |
| 2832 | UINT64_C(1287661568), // LD1Fourv4s_POST |
| 2833 | UINT64_C(205529088), // LD1Fourv8b |
| 2834 | UINT64_C(213917696), // LD1Fourv8b_POST |
| 2835 | UINT64_C(1279271936), // LD1Fourv8h |
| 2836 | UINT64_C(1287660544), // LD1Fourv8h_POST |
| 2837 | UINT64_C(2761965568), // LD1H |
| 2838 | UINT64_C(2684362752), // LD1H_2Z |
| 2839 | UINT64_C(2688557056), // LD1H_2Z_IMM |
| 2840 | UINT64_C(2701139968), // LD1H_2Z_STRIDED |
| 2841 | UINT64_C(2705334272), // LD1H_2Z_STRIDED_IMM |
| 2842 | UINT64_C(2684395520), // LD1H_4Z |
| 2843 | UINT64_C(2688589824), // LD1H_4Z_IMM |
| 2844 | UINT64_C(2701172736), // LD1H_4Z_STRIDED |
| 2845 | UINT64_C(2705367040), // LD1H_4Z_STRIDED_IMM |
| 2846 | UINT64_C(2766159872), // LD1H_D |
| 2847 | UINT64_C(2766184448), // LD1H_D_IMM |
| 2848 | UINT64_C(2761990144), // LD1H_IMM |
| 2849 | UINT64_C(2764062720), // LD1H_S |
| 2850 | UINT64_C(2764087296), // LD1H_S_IMM |
| 2851 | UINT64_C(1279291392), // LD1Onev16b |
| 2852 | UINT64_C(1287680000), // LD1Onev16b_POST |
| 2853 | UINT64_C(205552640), // LD1Onev1d |
| 2854 | UINT64_C(213941248), // LD1Onev1d_POST |
| 2855 | UINT64_C(1279294464), // LD1Onev2d |
| 2856 | UINT64_C(1287683072), // LD1Onev2d_POST |
| 2857 | UINT64_C(205551616), // LD1Onev2s |
| 2858 | UINT64_C(213940224), // LD1Onev2s_POST |
| 2859 | UINT64_C(205550592), // LD1Onev4h |
| 2860 | UINT64_C(213939200), // LD1Onev4h_POST |
| 2861 | UINT64_C(1279293440), // LD1Onev4s |
| 2862 | UINT64_C(1287682048), // LD1Onev4s_POST |
| 2863 | UINT64_C(205549568), // LD1Onev8b |
| 2864 | UINT64_C(213938176), // LD1Onev8b_POST |
| 2865 | UINT64_C(1279292416), // LD1Onev8h |
| 2866 | UINT64_C(1287681024), // LD1Onev8h_POST |
| 2867 | UINT64_C(2218844160), // LD1RB_D_IMM |
| 2868 | UINT64_C(2218827776), // LD1RB_H_IMM |
| 2869 | UINT64_C(2218819584), // LD1RB_IMM |
| 2870 | UINT64_C(2218835968), // LD1RB_S_IMM |
| 2871 | UINT64_C(2244009984), // LD1RD_IMM |
| 2872 | UINT64_C(2227232768), // LD1RH_D_IMM |
| 2873 | UINT64_C(2227216384), // LD1RH_IMM |
| 2874 | UINT64_C(2227224576), // LD1RH_S_IMM |
| 2875 | UINT64_C(2753560576), // LD1RO_B |
| 2876 | UINT64_C(2753568768), // LD1RO_B_IMM |
| 2877 | UINT64_C(2778726400), // LD1RO_D |
| 2878 | UINT64_C(2778734592), // LD1RO_D_IMM |
| 2879 | UINT64_C(2761949184), // LD1RO_H |
| 2880 | UINT64_C(2761957376), // LD1RO_H_IMM |
| 2881 | UINT64_C(2770337792), // LD1RO_W |
| 2882 | UINT64_C(2770345984), // LD1RO_W_IMM |
| 2883 | UINT64_C(2751463424), // LD1RQ_B |
| 2884 | UINT64_C(2751471616), // LD1RQ_B_IMM |
| 2885 | UINT64_C(2776629248), // LD1RQ_D |
| 2886 | UINT64_C(2776637440), // LD1RQ_D_IMM |
| 2887 | UINT64_C(2759852032), // LD1RQ_H |
| 2888 | UINT64_C(2759860224), // LD1RQ_H_IMM |
| 2889 | UINT64_C(2768240640), // LD1RQ_W |
| 2890 | UINT64_C(2768248832), // LD1RQ_W_IMM |
| 2891 | UINT64_C(2243985408), // LD1RSB_D_IMM |
| 2892 | UINT64_C(2244001792), // LD1RSB_H_IMM |
| 2893 | UINT64_C(2243993600), // LD1RSB_S_IMM |
| 2894 | UINT64_C(2235596800), // LD1RSH_D_IMM |
| 2895 | UINT64_C(2235604992), // LD1RSH_S_IMM |
| 2896 | UINT64_C(2227208192), // LD1RSW_IMM |
| 2897 | UINT64_C(2235621376), // LD1RW_D_IMM |
| 2898 | UINT64_C(2235613184), // LD1RW_IMM |
| 2899 | UINT64_C(1296089088), // LD1Rv16b |
| 2900 | UINT64_C(1304477696), // LD1Rv16b_POST |
| 2901 | UINT64_C(222350336), // LD1Rv1d |
| 2902 | UINT64_C(230738944), // LD1Rv1d_POST |
| 2903 | UINT64_C(1296092160), // LD1Rv2d |
| 2904 | UINT64_C(1304480768), // LD1Rv2d_POST |
| 2905 | UINT64_C(222349312), // LD1Rv2s |
| 2906 | UINT64_C(230737920), // LD1Rv2s_POST |
| 2907 | UINT64_C(222348288), // LD1Rv4h |
| 2908 | UINT64_C(230736896), // LD1Rv4h_POST |
| 2909 | UINT64_C(1296091136), // LD1Rv4s |
| 2910 | UINT64_C(1304479744), // LD1Rv4s_POST |
| 2911 | UINT64_C(222347264), // LD1Rv8b |
| 2912 | UINT64_C(230735872), // LD1Rv8b_POST |
| 2913 | UINT64_C(1296090112), // LD1Rv8h |
| 2914 | UINT64_C(1304478720), // LD1Rv8h_POST |
| 2915 | UINT64_C(2776645632), // LD1SB_D |
| 2916 | UINT64_C(2776670208), // LD1SB_D_IMM |
| 2917 | UINT64_C(2780839936), // LD1SB_H |
| 2918 | UINT64_C(2780864512), // LD1SB_H_IMM |
| 2919 | UINT64_C(2778742784), // LD1SB_S |
| 2920 | UINT64_C(2778767360), // LD1SB_S_IMM |
| 2921 | UINT64_C(2768257024), // LD1SH_D |
| 2922 | UINT64_C(2768281600), // LD1SH_D_IMM |
| 2923 | UINT64_C(2770354176), // LD1SH_S |
| 2924 | UINT64_C(2770378752), // LD1SH_S_IMM |
| 2925 | UINT64_C(2759868416), // LD1SW_D |
| 2926 | UINT64_C(2759892992), // LD1SW_D_IMM |
| 2927 | UINT64_C(1279287296), // LD1Threev16b |
| 2928 | UINT64_C(1287675904), // LD1Threev16b_POST |
| 2929 | UINT64_C(205548544), // LD1Threev1d |
| 2930 | UINT64_C(213937152), // LD1Threev1d_POST |
| 2931 | UINT64_C(1279290368), // LD1Threev2d |
| 2932 | UINT64_C(1287678976), // LD1Threev2d_POST |
| 2933 | UINT64_C(205547520), // LD1Threev2s |
| 2934 | UINT64_C(213936128), // LD1Threev2s_POST |
| 2935 | UINT64_C(205546496), // LD1Threev4h |
| 2936 | UINT64_C(213935104), // LD1Threev4h_POST |
| 2937 | UINT64_C(1279289344), // LD1Threev4s |
| 2938 | UINT64_C(1287677952), // LD1Threev4s_POST |
| 2939 | UINT64_C(205545472), // LD1Threev8b |
| 2940 | UINT64_C(213934080), // LD1Threev8b_POST |
| 2941 | UINT64_C(1279288320), // LD1Threev8h |
| 2942 | UINT64_C(1287676928), // LD1Threev8h_POST |
| 2943 | UINT64_C(1279303680), // LD1Twov16b |
| 2944 | UINT64_C(1287692288), // LD1Twov16b_POST |
| 2945 | UINT64_C(205564928), // LD1Twov1d |
| 2946 | UINT64_C(213953536), // LD1Twov1d_POST |
| 2947 | UINT64_C(1279306752), // LD1Twov2d |
| 2948 | UINT64_C(1287695360), // LD1Twov2d_POST |
| 2949 | UINT64_C(205563904), // LD1Twov2s |
| 2950 | UINT64_C(213952512), // LD1Twov2s_POST |
| 2951 | UINT64_C(205562880), // LD1Twov4h |
| 2952 | UINT64_C(213951488), // LD1Twov4h_POST |
| 2953 | UINT64_C(1279305728), // LD1Twov4s |
| 2954 | UINT64_C(1287694336), // LD1Twov4s_POST |
| 2955 | UINT64_C(205561856), // LD1Twov8b |
| 2956 | UINT64_C(213950464), // LD1Twov8b_POST |
| 2957 | UINT64_C(1279304704), // LD1Twov8h |
| 2958 | UINT64_C(1287693312), // LD1Twov8h_POST |
| 2959 | UINT64_C(2772451328), // LD1W |
| 2960 | UINT64_C(2684370944), // LD1W_2Z |
| 2961 | UINT64_C(2688565248), // LD1W_2Z_IMM |
| 2962 | UINT64_C(2701148160), // LD1W_2Z_STRIDED |
| 2963 | UINT64_C(2705342464), // LD1W_2Z_STRIDED_IMM |
| 2964 | UINT64_C(2684403712), // LD1W_4Z |
| 2965 | UINT64_C(2688598016), // LD1W_4Z_IMM |
| 2966 | UINT64_C(2701180928), // LD1W_4Z_STRIDED |
| 2967 | UINT64_C(2705375232), // LD1W_4Z_STRIDED_IMM |
| 2968 | UINT64_C(2774548480), // LD1W_D |
| 2969 | UINT64_C(2774573056), // LD1W_D_IMM |
| 2970 | UINT64_C(2772475904), // LD1W_IMM |
| 2971 | UINT64_C(2768273408), // LD1W_Q |
| 2972 | UINT64_C(2769297408), // LD1W_Q_IMM |
| 2973 | UINT64_C(3758096384), // LD1_MXIPXX_H_B |
| 2974 | UINT64_C(3770679296), // LD1_MXIPXX_H_D |
| 2975 | UINT64_C(3762290688), // LD1_MXIPXX_H_H |
| 2976 | UINT64_C(3787456512), // LD1_MXIPXX_H_Q |
| 2977 | UINT64_C(3766484992), // LD1_MXIPXX_H_S |
| 2978 | UINT64_C(3758129152), // LD1_MXIPXX_V_B |
| 2979 | UINT64_C(3770712064), // LD1_MXIPXX_V_D |
| 2980 | UINT64_C(3762323456), // LD1_MXIPXX_V_H |
| 2981 | UINT64_C(3787489280), // LD1_MXIPXX_V_Q |
| 2982 | UINT64_C(3766517760), // LD1_MXIPXX_V_S |
| 2983 | UINT64_C(222314496), // LD1i16 |
| 2984 | UINT64_C(230703104), // LD1i16_POST |
| 2985 | UINT64_C(222330880), // LD1i32 |
| 2986 | UINT64_C(230719488), // LD1i32_POST |
| 2987 | UINT64_C(222331904), // LD1i64 |
| 2988 | UINT64_C(230720512), // LD1i64_POST |
| 2989 | UINT64_C(222298112), // LD1i8 |
| 2990 | UINT64_C(230686720), // LD1i8_POST |
| 2991 | UINT64_C(2753609728), // LD2B |
| 2992 | UINT64_C(2753617920), // LD2B_IMM |
| 2993 | UINT64_C(2778775552), // LD2D |
| 2994 | UINT64_C(2778783744), // LD2D_IMM |
| 2995 | UINT64_C(2761998336), // LD2H |
| 2996 | UINT64_C(2762006528), // LD2H_IMM |
| 2997 | UINT64_C(2761981952), // LD2Q |
| 2998 | UINT64_C(2760957952), // LD2Q_IMM |
| 2999 | UINT64_C(1298186240), // LD2Rv16b |
| 3000 | UINT64_C(1306574848), // LD2Rv16b_POST |
| 3001 | UINT64_C(224447488), // LD2Rv1d |
| 3002 | UINT64_C(232836096), // LD2Rv1d_POST |
| 3003 | UINT64_C(1298189312), // LD2Rv2d |
| 3004 | UINT64_C(1306577920), // LD2Rv2d_POST |
| 3005 | UINT64_C(224446464), // LD2Rv2s |
| 3006 | UINT64_C(232835072), // LD2Rv2s_POST |
| 3007 | UINT64_C(224445440), // LD2Rv4h |
| 3008 | UINT64_C(232834048), // LD2Rv4h_POST |
| 3009 | UINT64_C(1298188288), // LD2Rv4s |
| 3010 | UINT64_C(1306576896), // LD2Rv4s_POST |
| 3011 | UINT64_C(224444416), // LD2Rv8b |
| 3012 | UINT64_C(232833024), // LD2Rv8b_POST |
| 3013 | UINT64_C(1298187264), // LD2Rv8h |
| 3014 | UINT64_C(1306575872), // LD2Rv8h_POST |
| 3015 | UINT64_C(1279295488), // LD2Twov16b |
| 3016 | UINT64_C(1287684096), // LD2Twov16b_POST |
| 3017 | UINT64_C(1279298560), // LD2Twov2d |
| 3018 | UINT64_C(1287687168), // LD2Twov2d_POST |
| 3019 | UINT64_C(205555712), // LD2Twov2s |
| 3020 | UINT64_C(213944320), // LD2Twov2s_POST |
| 3021 | UINT64_C(205554688), // LD2Twov4h |
| 3022 | UINT64_C(213943296), // LD2Twov4h_POST |
| 3023 | UINT64_C(1279297536), // LD2Twov4s |
| 3024 | UINT64_C(1287686144), // LD2Twov4s_POST |
| 3025 | UINT64_C(205553664), // LD2Twov8b |
| 3026 | UINT64_C(213942272), // LD2Twov8b_POST |
| 3027 | UINT64_C(1279296512), // LD2Twov8h |
| 3028 | UINT64_C(1287685120), // LD2Twov8h_POST |
| 3029 | UINT64_C(2770386944), // LD2W |
| 3030 | UINT64_C(2770395136), // LD2W_IMM |
| 3031 | UINT64_C(224411648), // LD2i16 |
| 3032 | UINT64_C(232800256), // LD2i16_POST |
| 3033 | UINT64_C(224428032), // LD2i32 |
| 3034 | UINT64_C(232816640), // LD2i32_POST |
| 3035 | UINT64_C(224429056), // LD2i64 |
| 3036 | UINT64_C(232817664), // LD2i64_POST |
| 3037 | UINT64_C(224395264), // LD2i8 |
| 3038 | UINT64_C(232783872), // LD2i8_POST |
| 3039 | UINT64_C(2755706880), // LD3B |
| 3040 | UINT64_C(2755715072), // LD3B_IMM |
| 3041 | UINT64_C(2780872704), // LD3D |
| 3042 | UINT64_C(2780880896), // LD3D_IMM |
| 3043 | UINT64_C(2764095488), // LD3H |
| 3044 | UINT64_C(2764103680), // LD3H_IMM |
| 3045 | UINT64_C(2770370560), // LD3Q |
| 3046 | UINT64_C(2769346560), // LD3Q_IMM |
| 3047 | UINT64_C(1296097280), // LD3Rv16b |
| 3048 | UINT64_C(1304485888), // LD3Rv16b_POST |
| 3049 | UINT64_C(222358528), // LD3Rv1d |
| 3050 | UINT64_C(230747136), // LD3Rv1d_POST |
| 3051 | UINT64_C(1296100352), // LD3Rv2d |
| 3052 | UINT64_C(1304488960), // LD3Rv2d_POST |
| 3053 | UINT64_C(222357504), // LD3Rv2s |
| 3054 | UINT64_C(230746112), // LD3Rv2s_POST |
| 3055 | UINT64_C(222356480), // LD3Rv4h |
| 3056 | UINT64_C(230745088), // LD3Rv4h_POST |
| 3057 | UINT64_C(1296099328), // LD3Rv4s |
| 3058 | UINT64_C(1304487936), // LD3Rv4s_POST |
| 3059 | UINT64_C(222355456), // LD3Rv8b |
| 3060 | UINT64_C(230744064), // LD3Rv8b_POST |
| 3061 | UINT64_C(1296098304), // LD3Rv8h |
| 3062 | UINT64_C(1304486912), // LD3Rv8h_POST |
| 3063 | UINT64_C(1279279104), // LD3Threev16b |
| 3064 | UINT64_C(1287667712), // LD3Threev16b_POST |
| 3065 | UINT64_C(1279282176), // LD3Threev2d |
| 3066 | UINT64_C(1287670784), // LD3Threev2d_POST |
| 3067 | UINT64_C(205539328), // LD3Threev2s |
| 3068 | UINT64_C(213927936), // LD3Threev2s_POST |
| 3069 | UINT64_C(205538304), // LD3Threev4h |
| 3070 | UINT64_C(213926912), // LD3Threev4h_POST |
| 3071 | UINT64_C(1279281152), // LD3Threev4s |
| 3072 | UINT64_C(1287669760), // LD3Threev4s_POST |
| 3073 | UINT64_C(205537280), // LD3Threev8b |
| 3074 | UINT64_C(213925888), // LD3Threev8b_POST |
| 3075 | UINT64_C(1279280128), // LD3Threev8h |
| 3076 | UINT64_C(1287668736), // LD3Threev8h_POST |
| 3077 | UINT64_C(2772484096), // LD3W |
| 3078 | UINT64_C(2772492288), // LD3W_IMM |
| 3079 | UINT64_C(222322688), // LD3i16 |
| 3080 | UINT64_C(230711296), // LD3i16_POST |
| 3081 | UINT64_C(222339072), // LD3i32 |
| 3082 | UINT64_C(230727680), // LD3i32_POST |
| 3083 | UINT64_C(222340096), // LD3i64 |
| 3084 | UINT64_C(230728704), // LD3i64_POST |
| 3085 | UINT64_C(222306304), // LD3i8 |
| 3086 | UINT64_C(230694912), // LD3i8_POST |
| 3087 | UINT64_C(2757804032), // LD4B |
| 3088 | UINT64_C(2757812224), // LD4B_IMM |
| 3089 | UINT64_C(2782969856), // LD4D |
| 3090 | UINT64_C(2782978048), // LD4D_IMM |
| 3091 | UINT64_C(1279262720), // LD4Fourv16b |
| 3092 | UINT64_C(1287651328), // LD4Fourv16b_POST |
| 3093 | UINT64_C(1279265792), // LD4Fourv2d |
| 3094 | UINT64_C(1287654400), // LD4Fourv2d_POST |
| 3095 | UINT64_C(205522944), // LD4Fourv2s |
| 3096 | UINT64_C(213911552), // LD4Fourv2s_POST |
| 3097 | UINT64_C(205521920), // LD4Fourv4h |
| 3098 | UINT64_C(213910528), // LD4Fourv4h_POST |
| 3099 | UINT64_C(1279264768), // LD4Fourv4s |
| 3100 | UINT64_C(1287653376), // LD4Fourv4s_POST |
| 3101 | UINT64_C(205520896), // LD4Fourv8b |
| 3102 | UINT64_C(213909504), // LD4Fourv8b_POST |
| 3103 | UINT64_C(1279263744), // LD4Fourv8h |
| 3104 | UINT64_C(1287652352), // LD4Fourv8h_POST |
| 3105 | UINT64_C(2766192640), // LD4H |
| 3106 | UINT64_C(2766200832), // LD4H_IMM |
| 3107 | UINT64_C(2778759168), // LD4Q |
| 3108 | UINT64_C(2777735168), // LD4Q_IMM |
| 3109 | UINT64_C(1298194432), // LD4Rv16b |
| 3110 | UINT64_C(1306583040), // LD4Rv16b_POST |
| 3111 | UINT64_C(224455680), // LD4Rv1d |
| 3112 | UINT64_C(232844288), // LD4Rv1d_POST |
| 3113 | UINT64_C(1298197504), // LD4Rv2d |
| 3114 | UINT64_C(1306586112), // LD4Rv2d_POST |
| 3115 | UINT64_C(224454656), // LD4Rv2s |
| 3116 | UINT64_C(232843264), // LD4Rv2s_POST |
| 3117 | UINT64_C(224453632), // LD4Rv4h |
| 3118 | UINT64_C(232842240), // LD4Rv4h_POST |
| 3119 | UINT64_C(1298196480), // LD4Rv4s |
| 3120 | UINT64_C(1306585088), // LD4Rv4s_POST |
| 3121 | UINT64_C(224452608), // LD4Rv8b |
| 3122 | UINT64_C(232841216), // LD4Rv8b_POST |
| 3123 | UINT64_C(1298195456), // LD4Rv8h |
| 3124 | UINT64_C(1306584064), // LD4Rv8h_POST |
| 3125 | UINT64_C(2774581248), // LD4W |
| 3126 | UINT64_C(2774589440), // LD4W_IMM |
| 3127 | UINT64_C(224419840), // LD4i16 |
| 3128 | UINT64_C(232808448), // LD4i16_POST |
| 3129 | UINT64_C(224436224), // LD4i32 |
| 3130 | UINT64_C(232824832), // LD4i32_POST |
| 3131 | UINT64_C(224437248), // LD4i64 |
| 3132 | UINT64_C(232825856), // LD4i64_POST |
| 3133 | UINT64_C(224403456), // LD4i8 |
| 3134 | UINT64_C(232792064), // LD4i8_POST |
| 3135 | UINT64_C(4164931584), // LD64B |
| 3136 | UINT64_C(4173320192), // LDA64B |
| 3137 | UINT64_C(950009856), // LDADDAB |
| 3138 | UINT64_C(2023751680), // LDADDAH |
| 3139 | UINT64_C(954204160), // LDADDALB |
| 3140 | UINT64_C(2027945984), // LDADDALH |
| 3141 | UINT64_C(3101687808), // LDADDALW |
| 3142 | UINT64_C(4175429632), // LDADDALX |
| 3143 | UINT64_C(3097493504), // LDADDAW |
| 3144 | UINT64_C(4171235328), // LDADDAX |
| 3145 | UINT64_C(941621248), // LDADDB |
| 3146 | UINT64_C(2015363072), // LDADDH |
| 3147 | UINT64_C(945815552), // LDADDLB |
| 3148 | UINT64_C(2019557376), // LDADDLH |
| 3149 | UINT64_C(3093299200), // LDADDLW |
| 3150 | UINT64_C(4167041024), // LDADDLX |
| 3151 | UINT64_C(3089104896), // LDADDW |
| 3152 | UINT64_C(4162846720), // LDADDX |
| 3153 | UINT64_C(222397440), // LDAP1 |
| 3154 | UINT64_C(3644880896), // LDAPPi |
| 3155 | UINT64_C(952090624), // LDAPRB |
| 3156 | UINT64_C(2025832448), // LDAPRH |
| 3157 | UINT64_C(3099574272), // LDAPRW |
| 3158 | UINT64_C(2579499008), // LDAPRWpost |
| 3159 | UINT64_C(4173316096), // LDAPRX |
| 3160 | UINT64_C(3653240832), // LDAPRXpost |
| 3161 | UINT64_C(423624704), // LDAPURBi |
| 3162 | UINT64_C(1497366528), // LDAPURHi |
| 3163 | UINT64_C(432013312), // LDAPURSBWi |
| 3164 | UINT64_C(427819008), // LDAPURSBXi |
| 3165 | UINT64_C(1505755136), // LDAPURSHWi |
| 3166 | UINT64_C(1501560832), // LDAPURSHXi |
| 3167 | UINT64_C(2575302656), // LDAPURSWi |
| 3168 | UINT64_C(3644850176), // LDAPURXi |
| 3169 | UINT64_C(490735616), // LDAPURbi |
| 3170 | UINT64_C(3711961088), // LDAPURdi |
| 3171 | UINT64_C(1564477440), // LDAPURhi |
| 3172 | UINT64_C(2571108352), // LDAPURi |
| 3173 | UINT64_C(499124224), // LDAPURqi |
| 3174 | UINT64_C(2638219264), // LDAPURsi |
| 3175 | UINT64_C(3644872704), // LDAPi |
| 3176 | UINT64_C(148896768), // LDARB |
| 3177 | UINT64_C(1222638592), // LDARH |
| 3178 | UINT64_C(2296380416), // LDARW |
| 3179 | UINT64_C(3370122240), // LDARX |
| 3180 | UINT64_C(2304769024), // LDATXRW |
| 3181 | UINT64_C(3378510848), // LDATXRX |
| 3182 | UINT64_C(2290057216), // LDAXPW |
| 3183 | UINT64_C(3363799040), // LDAXPX |
| 3184 | UINT64_C(140508160), // LDAXRB |
| 3185 | UINT64_C(1214249984), // LDAXRH |
| 3186 | UINT64_C(2287991808), // LDAXRW |
| 3187 | UINT64_C(3361733632), // LDAXRX |
| 3188 | UINT64_C(1008730112), // LDBFADD |
| 3189 | UINT64_C(1017118720), // LDBFADDA |
| 3190 | UINT64_C(1021313024), // LDBFADDAL |
| 3191 | UINT64_C(1012924416), // LDBFADDL |
| 3192 | UINT64_C(1008746496), // LDBFMAX |
| 3193 | UINT64_C(1017135104), // LDBFMAXA |
| 3194 | UINT64_C(1021329408), // LDBFMAXAL |
| 3195 | UINT64_C(1012940800), // LDBFMAXL |
| 3196 | UINT64_C(1008754688), // LDBFMAXNM |
| 3197 | UINT64_C(1017143296), // LDBFMAXNMA |
| 3198 | UINT64_C(1021337600), // LDBFMAXNMAL |
| 3199 | UINT64_C(1012948992), // LDBFMAXNML |
| 3200 | UINT64_C(1008750592), // LDBFMIN |
| 3201 | UINT64_C(1017139200), // LDBFMINA |
| 3202 | UINT64_C(1021333504), // LDBFMINAL |
| 3203 | UINT64_C(1012944896), // LDBFMINL |
| 3204 | UINT64_C(1008758784), // LDBFMINNM |
| 3205 | UINT64_C(1017147392), // LDBFMINNMA |
| 3206 | UINT64_C(1021341696), // LDBFMINNMAL |
| 3207 | UINT64_C(1012953088), // LDBFMINNML |
| 3208 | UINT64_C(950013952), // LDCLRAB |
| 3209 | UINT64_C(2023755776), // LDCLRAH |
| 3210 | UINT64_C(954208256), // LDCLRALB |
| 3211 | UINT64_C(2027950080), // LDCLRALH |
| 3212 | UINT64_C(3101691904), // LDCLRALW |
| 3213 | UINT64_C(4175433728), // LDCLRALX |
| 3214 | UINT64_C(3097497600), // LDCLRAW |
| 3215 | UINT64_C(4171239424), // LDCLRAX |
| 3216 | UINT64_C(941625344), // LDCLRB |
| 3217 | UINT64_C(2015367168), // LDCLRH |
| 3218 | UINT64_C(945819648), // LDCLRLB |
| 3219 | UINT64_C(2019561472), // LDCLRLH |
| 3220 | UINT64_C(3093303296), // LDCLRLW |
| 3221 | UINT64_C(4167045120), // LDCLRLX |
| 3222 | UINT64_C(421531648), // LDCLRP |
| 3223 | UINT64_C(429920256), // LDCLRPA |
| 3224 | UINT64_C(434114560), // LDCLRPAL |
| 3225 | UINT64_C(425725952), // LDCLRPL |
| 3226 | UINT64_C(3089108992), // LDCLRW |
| 3227 | UINT64_C(4162850816), // LDCLRX |
| 3228 | UINT64_C(950018048), // LDEORAB |
| 3229 | UINT64_C(2023759872), // LDEORAH |
| 3230 | UINT64_C(954212352), // LDEORALB |
| 3231 | UINT64_C(2027954176), // LDEORALH |
| 3232 | UINT64_C(3101696000), // LDEORALW |
| 3233 | UINT64_C(4175437824), // LDEORALX |
| 3234 | UINT64_C(3097501696), // LDEORAW |
| 3235 | UINT64_C(4171243520), // LDEORAX |
| 3236 | UINT64_C(941629440), // LDEORB |
| 3237 | UINT64_C(2015371264), // LDEORH |
| 3238 | UINT64_C(945823744), // LDEORLB |
| 3239 | UINT64_C(2019565568), // LDEORLH |
| 3240 | UINT64_C(3093307392), // LDEORLW |
| 3241 | UINT64_C(4167049216), // LDEORLX |
| 3242 | UINT64_C(3089113088), // LDEORW |
| 3243 | UINT64_C(4162854912), // LDEORX |
| 3244 | UINT64_C(4238344192), // LDFADDAD |
| 3245 | UINT64_C(2090860544), // LDFADDAH |
| 3246 | UINT64_C(4242538496), // LDFADDALD |
| 3247 | UINT64_C(2095054848), // LDFADDALH |
| 3248 | UINT64_C(3168796672), // LDFADDALS |
| 3249 | UINT64_C(3164602368), // LDFADDAS |
| 3250 | UINT64_C(4229955584), // LDFADDD |
| 3251 | UINT64_C(2082471936), // LDFADDH |
| 3252 | UINT64_C(4234149888), // LDFADDLD |
| 3253 | UINT64_C(2086666240), // LDFADDLH |
| 3254 | UINT64_C(3160408064), // LDFADDLS |
| 3255 | UINT64_C(3156213760), // LDFADDS |
| 3256 | UINT64_C(2751488000), // LDFF1B |
| 3257 | UINT64_C(2757779456), // LDFF1B_D |
| 3258 | UINT64_C(2753585152), // LDFF1B_H |
| 3259 | UINT64_C(2755682304), // LDFF1B_S |
| 3260 | UINT64_C(2782945280), // LDFF1D |
| 3261 | UINT64_C(2761973760), // LDFF1H |
| 3262 | UINT64_C(2766168064), // LDFF1H_D |
| 3263 | UINT64_C(2764070912), // LDFF1H_S |
| 3264 | UINT64_C(2776653824), // LDFF1SB_D |
| 3265 | UINT64_C(2780848128), // LDFF1SB_H |
| 3266 | UINT64_C(2778750976), // LDFF1SB_S |
| 3267 | UINT64_C(2768265216), // LDFF1SH_D |
| 3268 | UINT64_C(2770362368), // LDFF1SH_S |
| 3269 | UINT64_C(2759876608), // LDFF1SW_D |
| 3270 | UINT64_C(2772459520), // LDFF1W |
| 3271 | UINT64_C(2774556672), // LDFF1W_D |
| 3272 | UINT64_C(4238360576), // LDFMAXAD |
| 3273 | UINT64_C(2090876928), // LDFMAXAH |
| 3274 | UINT64_C(4242554880), // LDFMAXALD |
| 3275 | UINT64_C(2095071232), // LDFMAXALH |
| 3276 | UINT64_C(3168813056), // LDFMAXALS |
| 3277 | UINT64_C(3164618752), // LDFMAXAS |
| 3278 | UINT64_C(4229971968), // LDFMAXD |
| 3279 | UINT64_C(2082488320), // LDFMAXH |
| 3280 | UINT64_C(4234166272), // LDFMAXLD |
| 3281 | UINT64_C(2086682624), // LDFMAXLH |
| 3282 | UINT64_C(3160424448), // LDFMAXLS |
| 3283 | UINT64_C(4238368768), // LDFMAXNMAD |
| 3284 | UINT64_C(2090885120), // LDFMAXNMAH |
| 3285 | UINT64_C(4242563072), // LDFMAXNMALD |
| 3286 | UINT64_C(2095079424), // LDFMAXNMALH |
| 3287 | UINT64_C(3168821248), // LDFMAXNMALS |
| 3288 | UINT64_C(3164626944), // LDFMAXNMAS |
| 3289 | UINT64_C(4229980160), // LDFMAXNMD |
| 3290 | UINT64_C(2082496512), // LDFMAXNMH |
| 3291 | UINT64_C(4234174464), // LDFMAXNMLD |
| 3292 | UINT64_C(2086690816), // LDFMAXNMLH |
| 3293 | UINT64_C(3160432640), // LDFMAXNMLS |
| 3294 | UINT64_C(3156238336), // LDFMAXNMS |
| 3295 | UINT64_C(3156230144), // LDFMAXS |
| 3296 | UINT64_C(4238364672), // LDFMINAD |
| 3297 | UINT64_C(2090881024), // LDFMINAH |
| 3298 | UINT64_C(4242558976), // LDFMINALD |
| 3299 | UINT64_C(2095075328), // LDFMINALH |
| 3300 | UINT64_C(3168817152), // LDFMINALS |
| 3301 | UINT64_C(3164622848), // LDFMINAS |
| 3302 | UINT64_C(4229976064), // LDFMIND |
| 3303 | UINT64_C(2082492416), // LDFMINH |
| 3304 | UINT64_C(4234170368), // LDFMINLD |
| 3305 | UINT64_C(2086686720), // LDFMINLH |
| 3306 | UINT64_C(3160428544), // LDFMINLS |
| 3307 | UINT64_C(4238372864), // LDFMINNMAD |
| 3308 | UINT64_C(2090889216), // LDFMINNMAH |
| 3309 | UINT64_C(4242567168), // LDFMINNMALD |
| 3310 | UINT64_C(2095083520), // LDFMINNMALH |
| 3311 | UINT64_C(3168825344), // LDFMINNMALS |
| 3312 | UINT64_C(3164631040), // LDFMINNMAS |
| 3313 | UINT64_C(4229984256), // LDFMINNMD |
| 3314 | UINT64_C(2082500608), // LDFMINNMH |
| 3315 | UINT64_C(4234178560), // LDFMINNMLD |
| 3316 | UINT64_C(2086694912), // LDFMINNMLH |
| 3317 | UINT64_C(3160436736), // LDFMINNMLS |
| 3318 | UINT64_C(3156242432), // LDFMINNMS |
| 3319 | UINT64_C(3156234240), // LDFMINS |
| 3320 | UINT64_C(3646947328), // LDG |
| 3321 | UINT64_C(3655335936), // LDGM |
| 3322 | UINT64_C(2571114496), // LDIAPPW |
| 3323 | UINT64_C(2571110400), // LDIAPPWpost |
| 3324 | UINT64_C(3644856320), // LDIAPPX |
| 3325 | UINT64_C(3644852224), // LDIAPPXpost |
| 3326 | UINT64_C(148864000), // LDLARB |
| 3327 | UINT64_C(1222605824), // LDLARH |
| 3328 | UINT64_C(2296347648), // LDLARW |
| 3329 | UINT64_C(3370089472), // LDLARX |
| 3330 | UINT64_C(2758844416), // LDNF1B_D_IMM |
| 3331 | UINT64_C(2754650112), // LDNF1B_H_IMM |
| 3332 | UINT64_C(2752552960), // LDNF1B_IMM |
| 3333 | UINT64_C(2756747264), // LDNF1B_S_IMM |
| 3334 | UINT64_C(2784010240), // LDNF1D_IMM |
| 3335 | UINT64_C(2767233024), // LDNF1H_D_IMM |
| 3336 | UINT64_C(2763038720), // LDNF1H_IMM |
| 3337 | UINT64_C(2765135872), // LDNF1H_S_IMM |
| 3338 | UINT64_C(2777718784), // LDNF1SB_D_IMM |
| 3339 | UINT64_C(2781913088), // LDNF1SB_H_IMM |
| 3340 | UINT64_C(2779815936), // LDNF1SB_S_IMM |
| 3341 | UINT64_C(2769330176), // LDNF1SH_D_IMM |
| 3342 | UINT64_C(2771427328), // LDNF1SH_S_IMM |
| 3343 | UINT64_C(2760941568), // LDNF1SW_D_IMM |
| 3344 | UINT64_C(2775621632), // LDNF1W_D_IMM |
| 3345 | UINT64_C(2773524480), // LDNF1W_IMM |
| 3346 | UINT64_C(1816133632), // LDNPDi |
| 3347 | UINT64_C(2889875456), // LDNPQi |
| 3348 | UINT64_C(742391808), // LDNPSi |
| 3349 | UINT64_C(675282944), // LDNPWi |
| 3350 | UINT64_C(2822766592), // LDNPXi |
| 3351 | UINT64_C(2684354561), // LDNT1B_2Z |
| 3352 | UINT64_C(2688548865), // LDNT1B_2Z_IMM |
| 3353 | UINT64_C(2701131784), // LDNT1B_2Z_STRIDED |
| 3354 | UINT64_C(2705326088), // LDNT1B_2Z_STRIDED_IMM |
| 3355 | UINT64_C(2684387329), // LDNT1B_4Z |
| 3356 | UINT64_C(2688581633), // LDNT1B_4Z_IMM |
| 3357 | UINT64_C(2701164552), // LDNT1B_4Z_STRIDED |
| 3358 | UINT64_C(2705358856), // LDNT1B_4Z_STRIDED_IMM |
| 3359 | UINT64_C(2751520768), // LDNT1B_ZRI |
| 3360 | UINT64_C(2751512576), // LDNT1B_ZRR |
| 3361 | UINT64_C(3288383488), // LDNT1B_ZZR_D |
| 3362 | UINT64_C(2214633472), // LDNT1B_ZZR_S |
| 3363 | UINT64_C(2684379137), // LDNT1D_2Z |
| 3364 | UINT64_C(2688573441), // LDNT1D_2Z_IMM |
| 3365 | UINT64_C(2701156360), // LDNT1D_2Z_STRIDED |
| 3366 | UINT64_C(2705350664), // LDNT1D_2Z_STRIDED_IMM |
| 3367 | UINT64_C(2684411905), // LDNT1D_4Z |
| 3368 | UINT64_C(2688606209), // LDNT1D_4Z_IMM |
| 3369 | UINT64_C(2701189128), // LDNT1D_4Z_STRIDED |
| 3370 | UINT64_C(2705383432), // LDNT1D_4Z_STRIDED_IMM |
| 3371 | UINT64_C(2776686592), // LDNT1D_ZRI |
| 3372 | UINT64_C(2776678400), // LDNT1D_ZRR |
| 3373 | UINT64_C(3313549312), // LDNT1D_ZZR_D |
| 3374 | UINT64_C(2684362753), // LDNT1H_2Z |
| 3375 | UINT64_C(2688557057), // LDNT1H_2Z_IMM |
| 3376 | UINT64_C(2701139976), // LDNT1H_2Z_STRIDED |
| 3377 | UINT64_C(2705334280), // LDNT1H_2Z_STRIDED_IMM |
| 3378 | UINT64_C(2684395521), // LDNT1H_4Z |
| 3379 | UINT64_C(2688589825), // LDNT1H_4Z_IMM |
| 3380 | UINT64_C(2701172744), // LDNT1H_4Z_STRIDED |
| 3381 | UINT64_C(2705367048), // LDNT1H_4Z_STRIDED_IMM |
| 3382 | UINT64_C(2759909376), // LDNT1H_ZRI |
| 3383 | UINT64_C(2759901184), // LDNT1H_ZRR |
| 3384 | UINT64_C(3296772096), // LDNT1H_ZZR_D |
| 3385 | UINT64_C(2223022080), // LDNT1H_ZZR_S |
| 3386 | UINT64_C(3288367104), // LDNT1SB_ZZR_D |
| 3387 | UINT64_C(2214625280), // LDNT1SB_ZZR_S |
| 3388 | UINT64_C(3296755712), // LDNT1SH_ZZR_D |
| 3389 | UINT64_C(2223013888), // LDNT1SH_ZZR_S |
| 3390 | UINT64_C(3305144320), // LDNT1SW_ZZR_D |
| 3391 | UINT64_C(2684370945), // LDNT1W_2Z |
| 3392 | UINT64_C(2688565249), // LDNT1W_2Z_IMM |
| 3393 | UINT64_C(2701148168), // LDNT1W_2Z_STRIDED |
| 3394 | UINT64_C(2705342472), // LDNT1W_2Z_STRIDED_IMM |
| 3395 | UINT64_C(2684403713), // LDNT1W_4Z |
| 3396 | UINT64_C(2688598017), // LDNT1W_4Z_IMM |
| 3397 | UINT64_C(2701180936), // LDNT1W_4Z_STRIDED |
| 3398 | UINT64_C(2705375240), // LDNT1W_4Z_STRIDED_IMM |
| 3399 | UINT64_C(2768297984), // LDNT1W_ZRI |
| 3400 | UINT64_C(2768289792), // LDNT1W_ZRR |
| 3401 | UINT64_C(3305160704), // LDNT1W_ZZR_D |
| 3402 | UINT64_C(2231410688), // LDNT1W_ZZR_S |
| 3403 | UINT64_C(1832910848), // LDPDi |
| 3404 | UINT64_C(1824522240), // LDPDpost |
| 3405 | UINT64_C(1841299456), // LDPDpre |
| 3406 | UINT64_C(2906652672), // LDPQi |
| 3407 | UINT64_C(2898264064), // LDPQpost |
| 3408 | UINT64_C(2915041280), // LDPQpre |
| 3409 | UINT64_C(1765801984), // LDPSWi |
| 3410 | UINT64_C(1757413376), // LDPSWpost |
| 3411 | UINT64_C(1774190592), // LDPSWpre |
| 3412 | UINT64_C(759169024), // LDPSi |
| 3413 | UINT64_C(750780416), // LDPSpost |
| 3414 | UINT64_C(767557632), // LDPSpre |
| 3415 | UINT64_C(692060160), // LDPWi |
| 3416 | UINT64_C(683671552), // LDPWpost |
| 3417 | UINT64_C(700448768), // LDPWpre |
| 3418 | UINT64_C(2839543808), // LDPXi |
| 3419 | UINT64_C(2831155200), // LDPXpost |
| 3420 | UINT64_C(2847932416), // LDPXpre |
| 3421 | UINT64_C(4162847744), // LDRAAindexed |
| 3422 | UINT64_C(4162849792), // LDRAAwriteback |
| 3423 | UINT64_C(4171236352), // LDRABindexed |
| 3424 | UINT64_C(4171238400), // LDRABwriteback |
| 3425 | UINT64_C(943719424), // LDRBBpost |
| 3426 | UINT64_C(943721472), // LDRBBpre |
| 3427 | UINT64_C(945833984), // LDRBBroW |
| 3428 | UINT64_C(945842176), // LDRBBroX |
| 3429 | UINT64_C(960495616), // LDRBBui |
| 3430 | UINT64_C(1010828288), // LDRBpost |
| 3431 | UINT64_C(1010830336), // LDRBpre |
| 3432 | UINT64_C(1012942848), // LDRBroW |
| 3433 | UINT64_C(1012951040), // LDRBroX |
| 3434 | UINT64_C(1027604480), // LDRBui |
| 3435 | UINT64_C(1543503872), // LDRDl |
| 3436 | UINT64_C(4232053760), // LDRDpost |
| 3437 | UINT64_C(4232055808), // LDRDpre |
| 3438 | UINT64_C(4234168320), // LDRDroW |
| 3439 | UINT64_C(4234176512), // LDRDroX |
| 3440 | UINT64_C(4248829952), // LDRDui |
| 3441 | UINT64_C(2017461248), // LDRHHpost |
| 3442 | UINT64_C(2017463296), // LDRHHpre |
| 3443 | UINT64_C(2019575808), // LDRHHroW |
| 3444 | UINT64_C(2019584000), // LDRHHroX |
| 3445 | UINT64_C(2034237440), // LDRHHui |
| 3446 | UINT64_C(2084570112), // LDRHpost |
| 3447 | UINT64_C(2084572160), // LDRHpre |
| 3448 | UINT64_C(2086684672), // LDRHroW |
| 3449 | UINT64_C(2086692864), // LDRHroX |
| 3450 | UINT64_C(2101346304), // LDRHui |
| 3451 | UINT64_C(2617245696), // LDRQl |
| 3452 | UINT64_C(1019216896), // LDRQpost |
| 3453 | UINT64_C(1019218944), // LDRQpre |
| 3454 | UINT64_C(1021331456), // LDRQroW |
| 3455 | UINT64_C(1021339648), // LDRQroX |
| 3456 | UINT64_C(1035993088), // LDRQui |
| 3457 | UINT64_C(952108032), // LDRSBWpost |
| 3458 | UINT64_C(952110080), // LDRSBWpre |
| 3459 | UINT64_C(954222592), // LDRSBWroW |
| 3460 | UINT64_C(954230784), // LDRSBWroX |
| 3461 | UINT64_C(968884224), // LDRSBWui |
| 3462 | UINT64_C(947913728), // LDRSBXpost |
| 3463 | UINT64_C(947915776), // LDRSBXpre |
| 3464 | UINT64_C(950028288), // LDRSBXroW |
| 3465 | UINT64_C(950036480), // LDRSBXroX |
| 3466 | UINT64_C(964689920), // LDRSBXui |
| 3467 | UINT64_C(2025849856), // LDRSHWpost |
| 3468 | UINT64_C(2025851904), // LDRSHWpre |
| 3469 | UINT64_C(2027964416), // LDRSHWroW |
| 3470 | UINT64_C(2027972608), // LDRSHWroX |
| 3471 | UINT64_C(2042626048), // LDRSHWui |
| 3472 | UINT64_C(2021655552), // LDRSHXpost |
| 3473 | UINT64_C(2021657600), // LDRSHXpre |
| 3474 | UINT64_C(2023770112), // LDRSHXroW |
| 3475 | UINT64_C(2023778304), // LDRSHXroX |
| 3476 | UINT64_C(2038431744), // LDRSHXui |
| 3477 | UINT64_C(2550136832), // LDRSWl |
| 3478 | UINT64_C(3095397376), // LDRSWpost |
| 3479 | UINT64_C(3095399424), // LDRSWpre |
| 3480 | UINT64_C(3097511936), // LDRSWroW |
| 3481 | UINT64_C(3097520128), // LDRSWroX |
| 3482 | UINT64_C(3112173568), // LDRSWui |
| 3483 | UINT64_C(469762048), // LDRSl |
| 3484 | UINT64_C(3158311936), // LDRSpost |
| 3485 | UINT64_C(3158313984), // LDRSpre |
| 3486 | UINT64_C(3160426496), // LDRSroW |
| 3487 | UINT64_C(3160434688), // LDRSroX |
| 3488 | UINT64_C(3175088128), // LDRSui |
| 3489 | UINT64_C(402653184), // LDRWl |
| 3490 | UINT64_C(3091203072), // LDRWpost |
| 3491 | UINT64_C(3091205120), // LDRWpre |
| 3492 | UINT64_C(3093317632), // LDRWroW |
| 3493 | UINT64_C(3093325824), // LDRWroX |
| 3494 | UINT64_C(3107979264), // LDRWui |
| 3495 | UINT64_C(1476395008), // LDRXl |
| 3496 | UINT64_C(4164944896), // LDRXpost |
| 3497 | UINT64_C(4164946944), // LDRXpre |
| 3498 | UINT64_C(4167059456), // LDRXroW |
| 3499 | UINT64_C(4167067648), // LDRXroX |
| 3500 | UINT64_C(4181721088), // LDRXui |
| 3501 | UINT64_C(2239758336), // LDR_PXI |
| 3502 | UINT64_C(3776937984), // LDR_TX |
| 3503 | UINT64_C(3774873600), // LDR_ZA |
| 3504 | UINT64_C(2239774720), // LDR_ZXI |
| 3505 | UINT64_C(950022144), // LDSETAB |
| 3506 | UINT64_C(2023763968), // LDSETAH |
| 3507 | UINT64_C(954216448), // LDSETALB |
| 3508 | UINT64_C(2027958272), // LDSETALH |
| 3509 | UINT64_C(3101700096), // LDSETALW |
| 3510 | UINT64_C(4175441920), // LDSETALX |
| 3511 | UINT64_C(3097505792), // LDSETAW |
| 3512 | UINT64_C(4171247616), // LDSETAX |
| 3513 | UINT64_C(941633536), // LDSETB |
| 3514 | UINT64_C(2015375360), // LDSETH |
| 3515 | UINT64_C(945827840), // LDSETLB |
| 3516 | UINT64_C(2019569664), // LDSETLH |
| 3517 | UINT64_C(3093311488), // LDSETLW |
| 3518 | UINT64_C(4167053312), // LDSETLX |
| 3519 | UINT64_C(421539840), // LDSETP |
| 3520 | UINT64_C(429928448), // LDSETPA |
| 3521 | UINT64_C(434122752), // LDSETPAL |
| 3522 | UINT64_C(425734144), // LDSETPL |
| 3523 | UINT64_C(3089117184), // LDSETW |
| 3524 | UINT64_C(4162859008), // LDSETX |
| 3525 | UINT64_C(950026240), // LDSMAXAB |
| 3526 | UINT64_C(2023768064), // LDSMAXAH |
| 3527 | UINT64_C(954220544), // LDSMAXALB |
| 3528 | UINT64_C(2027962368), // LDSMAXALH |
| 3529 | UINT64_C(3101704192), // LDSMAXALW |
| 3530 | UINT64_C(4175446016), // LDSMAXALX |
| 3531 | UINT64_C(3097509888), // LDSMAXAW |
| 3532 | UINT64_C(4171251712), // LDSMAXAX |
| 3533 | UINT64_C(941637632), // LDSMAXB |
| 3534 | UINT64_C(2015379456), // LDSMAXH |
| 3535 | UINT64_C(945831936), // LDSMAXLB |
| 3536 | UINT64_C(2019573760), // LDSMAXLH |
| 3537 | UINT64_C(3093315584), // LDSMAXLW |
| 3538 | UINT64_C(4167057408), // LDSMAXLX |
| 3539 | UINT64_C(3089121280), // LDSMAXW |
| 3540 | UINT64_C(4162863104), // LDSMAXX |
| 3541 | UINT64_C(950030336), // LDSMINAB |
| 3542 | UINT64_C(2023772160), // LDSMINAH |
| 3543 | UINT64_C(954224640), // LDSMINALB |
| 3544 | UINT64_C(2027966464), // LDSMINALH |
| 3545 | UINT64_C(3101708288), // LDSMINALW |
| 3546 | UINT64_C(4175450112), // LDSMINALX |
| 3547 | UINT64_C(3097513984), // LDSMINAW |
| 3548 | UINT64_C(4171255808), // LDSMINAX |
| 3549 | UINT64_C(941641728), // LDSMINB |
| 3550 | UINT64_C(2015383552), // LDSMINH |
| 3551 | UINT64_C(945836032), // LDSMINLB |
| 3552 | UINT64_C(2019577856), // LDSMINLH |
| 3553 | UINT64_C(3093319680), // LDSMINLW |
| 3554 | UINT64_C(4167061504), // LDSMINLX |
| 3555 | UINT64_C(3089125376), // LDSMINW |
| 3556 | UINT64_C(4162867200), // LDSMINX |
| 3557 | UINT64_C(434111488), // LDTADDALW |
| 3558 | UINT64_C(1507853312), // LDTADDALX |
| 3559 | UINT64_C(429917184), // LDTADDAW |
| 3560 | UINT64_C(1503659008), // LDTADDAX |
| 3561 | UINT64_C(425722880), // LDTADDLW |
| 3562 | UINT64_C(1499464704), // LDTADDLX |
| 3563 | UINT64_C(421528576), // LDTADDW |
| 3564 | UINT64_C(1495270400), // LDTADDX |
| 3565 | UINT64_C(434115584), // LDTCLRALW |
| 3566 | UINT64_C(1507857408), // LDTCLRALX |
| 3567 | UINT64_C(429921280), // LDTCLRAW |
| 3568 | UINT64_C(1503663104), // LDTCLRAX |
| 3569 | UINT64_C(425726976), // LDTCLRLW |
| 3570 | UINT64_C(1499468800), // LDTCLRLX |
| 3571 | UINT64_C(421532672), // LDTCLRW |
| 3572 | UINT64_C(1495274496), // LDTCLRX |
| 3573 | UINT64_C(3963617280), // LDTNPQi |
| 3574 | UINT64_C(3896508416), // LDTNPXi |
| 3575 | UINT64_C(3980394496), // LDTPQi |
| 3576 | UINT64_C(3972005888), // LDTPQpost |
| 3577 | UINT64_C(3988783104), // LDTPQpre |
| 3578 | UINT64_C(3913285632), // LDTPi |
| 3579 | UINT64_C(3904897024), // LDTPpost |
| 3580 | UINT64_C(3921674240), // LDTPpre |
| 3581 | UINT64_C(943720448), // LDTRBi |
| 3582 | UINT64_C(2017462272), // LDTRHi |
| 3583 | UINT64_C(952109056), // LDTRSBWi |
| 3584 | UINT64_C(947914752), // LDTRSBXi |
| 3585 | UINT64_C(2025850880), // LDTRSHWi |
| 3586 | UINT64_C(2021656576), // LDTRSHXi |
| 3587 | UINT64_C(3095398400), // LDTRSWi |
| 3588 | UINT64_C(3091204096), // LDTRWi |
| 3589 | UINT64_C(4164945920), // LDTRXi |
| 3590 | UINT64_C(434123776), // LDTSETALW |
| 3591 | UINT64_C(1507865600), // LDTSETALX |
| 3592 | UINT64_C(429929472), // LDTSETAW |
| 3593 | UINT64_C(1503671296), // LDTSETAX |
| 3594 | UINT64_C(425735168), // LDTSETLW |
| 3595 | UINT64_C(1499476992), // LDTSETLX |
| 3596 | UINT64_C(421540864), // LDTSETW |
| 3597 | UINT64_C(1495282688), // LDTSETX |
| 3598 | UINT64_C(2304736256), // LDTXRWr |
| 3599 | UINT64_C(3378478080), // LDTXRXr |
| 3600 | UINT64_C(950034432), // LDUMAXAB |
| 3601 | UINT64_C(2023776256), // LDUMAXAH |
| 3602 | UINT64_C(954228736), // LDUMAXALB |
| 3603 | UINT64_C(2027970560), // LDUMAXALH |
| 3604 | UINT64_C(3101712384), // LDUMAXALW |
| 3605 | UINT64_C(4175454208), // LDUMAXALX |
| 3606 | UINT64_C(3097518080), // LDUMAXAW |
| 3607 | UINT64_C(4171259904), // LDUMAXAX |
| 3608 | UINT64_C(941645824), // LDUMAXB |
| 3609 | UINT64_C(2015387648), // LDUMAXH |
| 3610 | UINT64_C(945840128), // LDUMAXLB |
| 3611 | UINT64_C(2019581952), // LDUMAXLH |
| 3612 | UINT64_C(3093323776), // LDUMAXLW |
| 3613 | UINT64_C(4167065600), // LDUMAXLX |
| 3614 | UINT64_C(3089129472), // LDUMAXW |
| 3615 | UINT64_C(4162871296), // LDUMAXX |
| 3616 | UINT64_C(950038528), // LDUMINAB |
| 3617 | UINT64_C(2023780352), // LDUMINAH |
| 3618 | UINT64_C(954232832), // LDUMINALB |
| 3619 | UINT64_C(2027974656), // LDUMINALH |
| 3620 | UINT64_C(3101716480), // LDUMINALW |
| 3621 | UINT64_C(4175458304), // LDUMINALX |
| 3622 | UINT64_C(3097522176), // LDUMINAW |
| 3623 | UINT64_C(4171264000), // LDUMINAX |
| 3624 | UINT64_C(941649920), // LDUMINB |
| 3625 | UINT64_C(2015391744), // LDUMINH |
| 3626 | UINT64_C(945844224), // LDUMINLB |
| 3627 | UINT64_C(2019586048), // LDUMINLH |
| 3628 | UINT64_C(3093327872), // LDUMINLW |
| 3629 | UINT64_C(4167069696), // LDUMINLX |
| 3630 | UINT64_C(3089133568), // LDUMINW |
| 3631 | UINT64_C(4162875392), // LDUMINX |
| 3632 | UINT64_C(943718400), // LDURBBi |
| 3633 | UINT64_C(1010827264), // LDURBi |
| 3634 | UINT64_C(4232052736), // LDURDi |
| 3635 | UINT64_C(2017460224), // LDURHHi |
| 3636 | UINT64_C(2084569088), // LDURHi |
| 3637 | UINT64_C(1019215872), // LDURQi |
| 3638 | UINT64_C(952107008), // LDURSBWi |
| 3639 | UINT64_C(947912704), // LDURSBXi |
| 3640 | UINT64_C(2025848832), // LDURSHWi |
| 3641 | UINT64_C(2021654528), // LDURSHXi |
| 3642 | UINT64_C(3095396352), // LDURSWi |
| 3643 | UINT64_C(3158310912), // LDURSi |
| 3644 | UINT64_C(3091202048), // LDURWi |
| 3645 | UINT64_C(4164943872), // LDURXi |
| 3646 | UINT64_C(2290024448), // LDXPW |
| 3647 | UINT64_C(3363766272), // LDXPX |
| 3648 | UINT64_C(140475392), // LDXRB |
| 3649 | UINT64_C(1214217216), // LDXRH |
| 3650 | UINT64_C(2287959040), // LDXRW |
| 3651 | UINT64_C(3361700864), // LDXRX |
| 3652 | UINT64_C(68648960), // LSLR_ZPmZ_B |
| 3653 | UINT64_C(81231872), // LSLR_ZPmZ_D |
| 3654 | UINT64_C(72843264), // LSLR_ZPmZ_H |
| 3655 | UINT64_C(77037568), // LSLR_ZPmZ_S |
| 3656 | UINT64_C(448798720), // LSLVWr |
| 3657 | UINT64_C(2596282368), // LSLVXr |
| 3658 | UINT64_C(68911104), // LSL_WIDE_ZPmZ_B |
| 3659 | UINT64_C(73105408), // LSL_WIDE_ZPmZ_H |
| 3660 | UINT64_C(77299712), // LSL_WIDE_ZPmZ_S |
| 3661 | UINT64_C(69241856), // LSL_WIDE_ZZZ_B |
| 3662 | UINT64_C(73436160), // LSL_WIDE_ZZZ_H |
| 3663 | UINT64_C(77630464), // LSL_WIDE_ZZZ_S |
| 3664 | UINT64_C(67338496), // LSL_ZPmI_B |
| 3665 | UINT64_C(75726848), // LSL_ZPmI_D |
| 3666 | UINT64_C(67338752), // LSL_ZPmI_H |
| 3667 | UINT64_C(71532544), // LSL_ZPmI_S |
| 3668 | UINT64_C(68386816), // LSL_ZPmZ_B |
| 3669 | UINT64_C(80969728), // LSL_ZPmZ_D |
| 3670 | UINT64_C(72581120), // LSL_ZPmZ_H |
| 3671 | UINT64_C(76775424), // LSL_ZPmZ_S |
| 3672 | UINT64_C(69770240), // LSL_ZZI_B |
| 3673 | UINT64_C(77634560), // LSL_ZZI_D |
| 3674 | UINT64_C(70294528), // LSL_ZZI_H |
| 3675 | UINT64_C(73440256), // LSL_ZZI_S |
| 3676 | UINT64_C(68517888), // LSRR_ZPmZ_B |
| 3677 | UINT64_C(81100800), // LSRR_ZPmZ_D |
| 3678 | UINT64_C(72712192), // LSRR_ZPmZ_H |
| 3679 | UINT64_C(76906496), // LSRR_ZPmZ_S |
| 3680 | UINT64_C(448799744), // LSRVWr |
| 3681 | UINT64_C(2596283392), // LSRVXr |
| 3682 | UINT64_C(68780032), // LSR_WIDE_ZPmZ_B |
| 3683 | UINT64_C(72974336), // LSR_WIDE_ZPmZ_H |
| 3684 | UINT64_C(77168640), // LSR_WIDE_ZPmZ_S |
| 3685 | UINT64_C(69239808), // LSR_WIDE_ZZZ_B |
| 3686 | UINT64_C(73434112), // LSR_WIDE_ZZZ_H |
| 3687 | UINT64_C(77628416), // LSR_WIDE_ZZZ_S |
| 3688 | UINT64_C(67207424), // LSR_ZPmI_B |
| 3689 | UINT64_C(75595776), // LSR_ZPmI_D |
| 3690 | UINT64_C(67207680), // LSR_ZPmI_H |
| 3691 | UINT64_C(71401472), // LSR_ZPmI_S |
| 3692 | UINT64_C(68255744), // LSR_ZPmZ_B |
| 3693 | UINT64_C(80838656), // LSR_ZPmZ_D |
| 3694 | UINT64_C(72450048), // LSR_ZPmZ_H |
| 3695 | UINT64_C(76644352), // LSR_ZPmZ_S |
| 3696 | UINT64_C(69768192), // LSR_ZZI_B |
| 3697 | UINT64_C(77632512), // LSR_ZZI_D |
| 3698 | UINT64_C(70292480), // LSR_ZZI_H |
| 3699 | UINT64_C(73438208), // LSR_ZZI_S |
| 3700 | UINT64_C(1317015552), // LUT2_B |
| 3701 | UINT64_C(1321205760), // LUT2_H |
| 3702 | UINT64_C(1312825344), // LUT4_B |
| 3703 | UINT64_C(1312821248), // LUT4_H |
| 3704 | UINT64_C(3230416896), // LUTI2_2ZTZI_B |
| 3705 | UINT64_C(3230420992), // LUTI2_2ZTZI_H |
| 3706 | UINT64_C(3230425088), // LUTI2_2ZTZI_S |
| 3707 | UINT64_C(3230433280), // LUTI2_4ZTZI_B |
| 3708 | UINT64_C(3230437376), // LUTI2_4ZTZI_H |
| 3709 | UINT64_C(3230441472), // LUTI2_4ZTZI_S |
| 3710 | UINT64_C(3231465472), // LUTI2_S_2ZTZI_B |
| 3711 | UINT64_C(3231469568), // LUTI2_S_2ZTZI_H |
| 3712 | UINT64_C(3231481856), // LUTI2_S_4ZTZI_B |
| 3713 | UINT64_C(3231485952), // LUTI2_S_4ZTZI_H |
| 3714 | UINT64_C(3234594816), // LUTI2_ZTZI_B |
| 3715 | UINT64_C(3234598912), // LUTI2_ZTZI_H |
| 3716 | UINT64_C(3234603008), // LUTI2_ZTZI_S |
| 3717 | UINT64_C(1159770112), // LUTI2_ZZZI_B |
| 3718 | UINT64_C(1159768064), // LUTI2_ZZZI_H |
| 3719 | UINT64_C(3230285824), // LUTI4_2ZTZI_B |
| 3720 | UINT64_C(3230289920), // LUTI4_2ZTZI_H |
| 3721 | UINT64_C(3230294016), // LUTI4_2ZTZI_S |
| 3722 | UINT64_C(3230306304), // LUTI4_4ZTZI_H |
| 3723 | UINT64_C(3230310400), // LUTI4_4ZTZI_S |
| 3724 | UINT64_C(3230334976), // LUTI4_4ZZT2Z |
| 3725 | UINT64_C(3231334400), // LUTI4_S_2ZTZI_B |
| 3726 | UINT64_C(3231338496), // LUTI4_S_2ZTZI_H |
| 3727 | UINT64_C(3231354880), // LUTI4_S_4ZTZI_H |
| 3728 | UINT64_C(3231383552), // LUTI4_S_4ZZT2Z |
| 3729 | UINT64_C(1159771136), // LUTI4_Z2ZZI |
| 3730 | UINT64_C(3234463744), // LUTI4_ZTZI_B |
| 3731 | UINT64_C(3234467840), // LUTI4_ZTZI_H |
| 3732 | UINT64_C(3234471936), // LUTI4_ZTZI_S |
| 3733 | UINT64_C(1163961344), // LUTI4_ZZZI_B |
| 3734 | UINT64_C(1159773184), // LUTI4_ZZZI_H |
| 3735 | UINT64_C(3240162304), // LUTI6_4Z2Z2ZI |
| 3736 | UINT64_C(3230269440), // LUTI6_4ZT3Z |
| 3737 | UINT64_C(3240164352), // LUTI6_S_4Z2Z2ZI |
| 3738 | UINT64_C(3231318016), // LUTI6_S_4ZT3Z |
| 3739 | UINT64_C(1159769088), // LUTI6_Z2ZZ |
| 3740 | UINT64_C(1163963392), // LUTI6_Z2ZZI_H |
| 3741 | UINT64_C(3234349056), // LUTI6_ZTZ |
| 3742 | UINT64_C(2606759936), // MADDPT |
| 3743 | UINT64_C(452984832), // MADDWrrr |
| 3744 | UINT64_C(2600468480), // MADDXrrr |
| 3745 | UINT64_C(1153488896), // MAD_CPA |
| 3746 | UINT64_C(67158016), // MAD_ZPmZZ_B |
| 3747 | UINT64_C(79740928), // MAD_ZPmZZ_D |
| 3748 | UINT64_C(71352320), // MAD_ZPmZZ_H |
| 3749 | UINT64_C(75546624), // MAD_ZPmZZ_S |
| 3750 | UINT64_C(1159757824), // MATCH_PPzZZ_B |
| 3751 | UINT64_C(1163952128), // MATCH_PPzZZ_H |
| 3752 | UINT64_C(1153486848), // MLA_CPA |
| 3753 | UINT64_C(67125248), // MLA_ZPmZZ_B |
| 3754 | UINT64_C(79708160), // MLA_ZPmZZ_D |
| 3755 | UINT64_C(71319552), // MLA_ZPmZZ_H |
| 3756 | UINT64_C(75513856), // MLA_ZPmZZ_S |
| 3757 | UINT64_C(1155532800), // MLA_ZZZI_D |
| 3758 | UINT64_C(1142949888), // MLA_ZZZI_H |
| 3759 | UINT64_C(1151338496), // MLA_ZZZI_S |
| 3760 | UINT64_C(1310757888), // MLAv16i8 |
| 3761 | UINT64_C(245404672), // MLAv2i32 |
| 3762 | UINT64_C(796917760), // MLAv2i32_indexed |
| 3763 | UINT64_C(241210368), // MLAv4i16 |
| 3764 | UINT64_C(792723456), // MLAv4i16_indexed |
| 3765 | UINT64_C(1319146496), // MLAv4i32 |
| 3766 | UINT64_C(1870659584), // MLAv4i32_indexed |
| 3767 | UINT64_C(1314952192), // MLAv8i16 |
| 3768 | UINT64_C(1866465280), // MLAv8i16_indexed |
| 3769 | UINT64_C(237016064), // MLAv8i8 |
| 3770 | UINT64_C(67133440), // MLS_ZPmZZ_B |
| 3771 | UINT64_C(79716352), // MLS_ZPmZZ_D |
| 3772 | UINT64_C(71327744), // MLS_ZPmZZ_H |
| 3773 | UINT64_C(75522048), // MLS_ZPmZZ_S |
| 3774 | UINT64_C(1155533824), // MLS_ZZZI_D |
| 3775 | UINT64_C(1142950912), // MLS_ZZZI_H |
| 3776 | UINT64_C(1151339520), // MLS_ZZZI_S |
| 3777 | UINT64_C(1847628800), // MLSv16i8 |
| 3778 | UINT64_C(782275584), // MLSv2i32 |
| 3779 | UINT64_C(796934144), // MLSv2i32_indexed |
| 3780 | UINT64_C(778081280), // MLSv4i16 |
| 3781 | UINT64_C(792739840), // MLSv4i16_indexed |
| 3782 | UINT64_C(1856017408), // MLSv4i32 |
| 3783 | UINT64_C(1870675968), // MLSv4i32_indexed |
| 3784 | UINT64_C(1851823104), // MLSv8i16 |
| 3785 | UINT64_C(1866481664), // MLSv8i16_indexed |
| 3786 | UINT64_C(773886976), // MLSv8i8 |
| 3787 | UINT64_C(499155968), // MOPSSETGE |
| 3788 | UINT64_C(499164160), // MOPSSETGEN |
| 3789 | UINT64_C(499160064), // MOPSSETGET |
| 3790 | UINT64_C(499168256), // MOPSSETGETN |
| 3791 | UINT64_C(3221619200), // MOVAZ_2ZMI_H_B |
| 3792 | UINT64_C(3234202112), // MOVAZ_2ZMI_H_D |
| 3793 | UINT64_C(3225813504), // MOVAZ_2ZMI_H_H |
| 3794 | UINT64_C(3230007808), // MOVAZ_2ZMI_H_S |
| 3795 | UINT64_C(3221651968), // MOVAZ_2ZMI_V_B |
| 3796 | UINT64_C(3234234880), // MOVAZ_2ZMI_V_D |
| 3797 | UINT64_C(3225846272), // MOVAZ_2ZMI_V_H |
| 3798 | UINT64_C(3230040576), // MOVAZ_2ZMI_V_S |
| 3799 | UINT64_C(3221620224), // MOVAZ_4ZMI_H_B |
| 3800 | UINT64_C(3234203136), // MOVAZ_4ZMI_H_D |
| 3801 | UINT64_C(3225814528), // MOVAZ_4ZMI_H_H |
| 3802 | UINT64_C(3230008832), // MOVAZ_4ZMI_H_S |
| 3803 | UINT64_C(3221652992), // MOVAZ_4ZMI_V_B |
| 3804 | UINT64_C(3234235904), // MOVAZ_4ZMI_V_D |
| 3805 | UINT64_C(3225847296), // MOVAZ_4ZMI_V_H |
| 3806 | UINT64_C(3230041600), // MOVAZ_4ZMI_V_S |
| 3807 | UINT64_C(3221621248), // MOVAZ_VG2_2ZMXI |
| 3808 | UINT64_C(3221622272), // MOVAZ_VG4_4ZMXI |
| 3809 | UINT64_C(3221357056), // MOVAZ_ZMI_H_B |
| 3810 | UINT64_C(3233939968), // MOVAZ_ZMI_H_D |
| 3811 | UINT64_C(3225551360), // MOVAZ_ZMI_H_H |
| 3812 | UINT64_C(3234005504), // MOVAZ_ZMI_H_Q |
| 3813 | UINT64_C(3229745664), // MOVAZ_ZMI_H_S |
| 3814 | UINT64_C(3221389824), // MOVAZ_ZMI_V_B |
| 3815 | UINT64_C(3233972736), // MOVAZ_ZMI_V_D |
| 3816 | UINT64_C(3225584128), // MOVAZ_ZMI_V_H |
| 3817 | UINT64_C(3234038272), // MOVAZ_ZMI_V_Q |
| 3818 | UINT64_C(3229778432), // MOVAZ_ZMI_V_S |
| 3819 | UINT64_C(3221618688), // MOVA_2ZMXI_H_B |
| 3820 | UINT64_C(3234201600), // MOVA_2ZMXI_H_D |
| 3821 | UINT64_C(3225812992), // MOVA_2ZMXI_H_H |
| 3822 | UINT64_C(3230007296), // MOVA_2ZMXI_H_S |
| 3823 | UINT64_C(3221651456), // MOVA_2ZMXI_V_B |
| 3824 | UINT64_C(3234234368), // MOVA_2ZMXI_V_D |
| 3825 | UINT64_C(3225845760), // MOVA_2ZMXI_V_H |
| 3826 | UINT64_C(3230040064), // MOVA_2ZMXI_V_S |
| 3827 | UINT64_C(3221619712), // MOVA_4ZMXI_H_B |
| 3828 | UINT64_C(3234202624), // MOVA_4ZMXI_H_D |
| 3829 | UINT64_C(3225814016), // MOVA_4ZMXI_H_H |
| 3830 | UINT64_C(3230008320), // MOVA_4ZMXI_H_S |
| 3831 | UINT64_C(3221652480), // MOVA_4ZMXI_V_B |
| 3832 | UINT64_C(3234235392), // MOVA_4ZMXI_V_D |
| 3833 | UINT64_C(3225846784), // MOVA_4ZMXI_V_H |
| 3834 | UINT64_C(3230041088), // MOVA_4ZMXI_V_S |
| 3835 | UINT64_C(3221487616), // MOVA_MXI2Z_H_B |
| 3836 | UINT64_C(3234070528), // MOVA_MXI2Z_H_D |
| 3837 | UINT64_C(3225681920), // MOVA_MXI2Z_H_H |
| 3838 | UINT64_C(3229876224), // MOVA_MXI2Z_H_S |
| 3839 | UINT64_C(3221520384), // MOVA_MXI2Z_V_B |
| 3840 | UINT64_C(3234103296), // MOVA_MXI2Z_V_D |
| 3841 | UINT64_C(3225714688), // MOVA_MXI2Z_V_H |
| 3842 | UINT64_C(3229908992), // MOVA_MXI2Z_V_S |
| 3843 | UINT64_C(3221488640), // MOVA_MXI4Z_H_B |
| 3844 | UINT64_C(3234071552), // MOVA_MXI4Z_H_D |
| 3845 | UINT64_C(3225682944), // MOVA_MXI4Z_H_H |
| 3846 | UINT64_C(3229877248), // MOVA_MXI4Z_H_S |
| 3847 | UINT64_C(3221521408), // MOVA_MXI4Z_V_B |
| 3848 | UINT64_C(3234104320), // MOVA_MXI4Z_V_D |
| 3849 | UINT64_C(3225715712), // MOVA_MXI4Z_V_H |
| 3850 | UINT64_C(3229910016), // MOVA_MXI4Z_V_S |
| 3851 | UINT64_C(3221620736), // MOVA_VG2_2ZMXI |
| 3852 | UINT64_C(3221489664), // MOVA_VG2_MXI2Z |
| 3853 | UINT64_C(3221621760), // MOVA_VG4_4ZMXI |
| 3854 | UINT64_C(3221490688), // MOVA_VG4_MXI4Z |
| 3855 | UINT64_C(788587520), // MOVID |
| 3856 | UINT64_C(1325458432), // MOVIv16b_ns |
| 3857 | UINT64_C(1862329344), // MOVIv2d_ns |
| 3858 | UINT64_C(251659264), // MOVIv2i32 |
| 3859 | UINT64_C(251708416), // MOVIv2s_msl |
| 3860 | UINT64_C(251692032), // MOVIv4i16 |
| 3861 | UINT64_C(1325401088), // MOVIv4i32 |
| 3862 | UINT64_C(1325450240), // MOVIv4s_msl |
| 3863 | UINT64_C(251716608), // MOVIv8b_ns |
| 3864 | UINT64_C(1325433856), // MOVIv8i16 |
| 3865 | UINT64_C(1920991232), // MOVKWi |
| 3866 | UINT64_C(4068474880), // MOVKXi |
| 3867 | UINT64_C(310378496), // MOVNWi |
| 3868 | UINT64_C(2457862144), // MOVNXi |
| 3869 | UINT64_C(68231168), // MOVPRFX_ZPmZ_B |
| 3870 | UINT64_C(80814080), // MOVPRFX_ZPmZ_D |
| 3871 | UINT64_C(72425472), // MOVPRFX_ZPmZ_H |
| 3872 | UINT64_C(76619776), // MOVPRFX_ZPmZ_S |
| 3873 | UINT64_C(68165632), // MOVPRFX_ZPzZ_B |
| 3874 | UINT64_C(80748544), // MOVPRFX_ZPzZ_D |
| 3875 | UINT64_C(72359936), // MOVPRFX_ZPzZ_H |
| 3876 | UINT64_C(76554240), // MOVPRFX_ZPzZ_S |
| 3877 | UINT64_C(69254144), // MOVPRFX_ZZ |
| 3878 | UINT64_C(3226338272), // MOVT_TIX |
| 3879 | UINT64_C(3226403808), // MOVT_TIZ |
| 3880 | UINT64_C(3226207200), // MOVT_XTI |
| 3881 | UINT64_C(1384120320), // MOVZWi |
| 3882 | UINT64_C(3531603968), // MOVZXi |
| 3883 | UINT64_C(3579838464), // MRRS |
| 3884 | UINT64_C(3575644160), // MRS |
| 3885 | UINT64_C(67166208), // MSB_ZPmZZ_B |
| 3886 | UINT64_C(79749120), // MSB_ZPmZZ_D |
| 3887 | UINT64_C(71360512), // MSB_ZPmZZ_H |
| 3888 | UINT64_C(75554816), // MSB_ZPmZZ_S |
| 3889 | UINT64_C(3573547008), // MSR |
| 3890 | UINT64_C(3577741312), // MSRR |
| 3891 | UINT64_C(3573563423), // MSRpstateImm1 |
| 3892 | UINT64_C(3573563423), // MSRpstateImm4 |
| 3893 | UINT64_C(3573760127), // MSRpstatesvcrImm1 |
| 3894 | UINT64_C(2606792704), // MSUBPT |
| 3895 | UINT64_C(453017600), // MSUBWrrr |
| 3896 | UINT64_C(2600501248), // MSUBXrrr |
| 3897 | UINT64_C(623951872), // MUL_ZI_B |
| 3898 | UINT64_C(636534784), // MUL_ZI_D |
| 3899 | UINT64_C(628146176), // MUL_ZI_H |
| 3900 | UINT64_C(632340480), // MUL_ZI_S |
| 3901 | UINT64_C(68157440), // MUL_ZPmZ_B |
| 3902 | UINT64_C(80740352), // MUL_ZPmZ_D |
| 3903 | UINT64_C(72351744), // MUL_ZPmZ_H |
| 3904 | UINT64_C(76546048), // MUL_ZPmZ_S |
| 3905 | UINT64_C(1155594240), // MUL_ZZZI_D |
| 3906 | UINT64_C(1143011328), // MUL_ZZZI_H |
| 3907 | UINT64_C(1151399936), // MUL_ZZZI_S |
| 3908 | UINT64_C(69230592), // MUL_ZZZ_B |
| 3909 | UINT64_C(81813504), // MUL_ZZZ_D |
| 3910 | UINT64_C(73424896), // MUL_ZZZ_H |
| 3911 | UINT64_C(77619200), // MUL_ZZZ_S |
| 3912 | UINT64_C(1310759936), // MULv16i8 |
| 3913 | UINT64_C(245406720), // MULv2i32 |
| 3914 | UINT64_C(260079616), // MULv2i32_indexed |
| 3915 | UINT64_C(241212416), // MULv4i16 |
| 3916 | UINT64_C(255885312), // MULv4i16_indexed |
| 3917 | UINT64_C(1319148544), // MULv4i32 |
| 3918 | UINT64_C(1333821440), // MULv4i32_indexed |
| 3919 | UINT64_C(1314954240), // MULv8i16 |
| 3920 | UINT64_C(1329627136), // MULv8i16_indexed |
| 3921 | UINT64_C(237018112), // MULv8i8 |
| 3922 | UINT64_C(788530176), // MVNIv2i32 |
| 3923 | UINT64_C(788579328), // MVNIv2s_msl |
| 3924 | UINT64_C(788562944), // MVNIv4i16 |
| 3925 | UINT64_C(1862272000), // MVNIv4i32 |
| 3926 | UINT64_C(1862321152), // MVNIv4s_msl |
| 3927 | UINT64_C(1862304768), // MVNIv8i16 |
| 3928 | UINT64_C(633356816), // NANDS_PPzPP |
| 3929 | UINT64_C(629162512), // NAND_PPzPP |
| 3930 | UINT64_C(81804288), // NBSL_ZZZZ |
| 3931 | UINT64_C(68657152), // NEG_ZPmZ_B |
| 3932 | UINT64_C(81240064), // NEG_ZPmZ_D |
| 3933 | UINT64_C(72851456), // NEG_ZPmZ_H |
| 3934 | UINT64_C(77045760), // NEG_ZPmZ_S |
| 3935 | UINT64_C(67608576), // NEG_ZPzZ_B |
| 3936 | UINT64_C(80191488), // NEG_ZPzZ_D |
| 3937 | UINT64_C(71802880), // NEG_ZPzZ_H |
| 3938 | UINT64_C(75997184), // NEG_ZPzZ_S |
| 3939 | UINT64_C(1847638016), // NEGv16i8 |
| 3940 | UINT64_C(2128656384), // NEGv1i64 |
| 3941 | UINT64_C(782284800), // NEGv2i32 |
| 3942 | UINT64_C(1860220928), // NEGv2i64 |
| 3943 | UINT64_C(778090496), // NEGv4i16 |
| 3944 | UINT64_C(1856026624), // NEGv4i32 |
| 3945 | UINT64_C(1851832320), // NEGv8i16 |
| 3946 | UINT64_C(773896192), // NEGv8i8 |
| 3947 | UINT64_C(1159757840), // NMATCH_PPzZZ_B |
| 3948 | UINT64_C(1163952144), // NMATCH_PPzZZ_H |
| 3949 | UINT64_C(3573751839), // NOP |
| 3950 | UINT64_C(633356800), // NORS_PPzPP |
| 3951 | UINT64_C(629162496), // NOR_PPzPP |
| 3952 | UINT64_C(69115904), // NOT_ZPmZ_B |
| 3953 | UINT64_C(81698816), // NOT_ZPmZ_D |
| 3954 | UINT64_C(73310208), // NOT_ZPmZ_H |
| 3955 | UINT64_C(77504512), // NOT_ZPmZ_S |
| 3956 | UINT64_C(68067328), // NOT_ZPzZ_B |
| 3957 | UINT64_C(80650240), // NOT_ZPzZ_D |
| 3958 | UINT64_C(72261632), // NOT_ZPzZ_H |
| 3959 | UINT64_C(76455936), // NOT_ZPzZ_S |
| 3960 | UINT64_C(1847613440), // NOTv16i8 |
| 3961 | UINT64_C(773871616), // NOTv8i8 |
| 3962 | UINT64_C(633356304), // ORNS_PPzPP |
| 3963 | UINT64_C(706740224), // ORNWrs |
| 3964 | UINT64_C(2854223872), // ORNXrs |
| 3965 | UINT64_C(629162000), // ORN_PPzPP |
| 3966 | UINT64_C(1323310080), // ORNv16i8 |
| 3967 | UINT64_C(249568256), // ORNv8i8 |
| 3968 | UINT64_C(68952064), // ORQV_VPZ_B |
| 3969 | UINT64_C(81534976), // ORQV_VPZ_D |
| 3970 | UINT64_C(73146368), // ORQV_VPZ_H |
| 3971 | UINT64_C(77340672), // ORQV_VPZ_S |
| 3972 | UINT64_C(633356288), // ORRS_PPzPP |
| 3973 | UINT64_C(838860800), // ORRWri |
| 3974 | UINT64_C(704643072), // ORRWrs |
| 3975 | UINT64_C(2986344448), // ORRXri |
| 3976 | UINT64_C(2852126720), // ORRXrs |
| 3977 | UINT64_C(629161984), // ORR_PPzPP |
| 3978 | UINT64_C(83886080), // ORR_ZI |
| 3979 | UINT64_C(68681728), // ORR_ZPmZ_B |
| 3980 | UINT64_C(81264640), // ORR_ZPmZ_D |
| 3981 | UINT64_C(72876032), // ORR_ZPmZ_H |
| 3982 | UINT64_C(77070336), // ORR_ZPmZ_S |
| 3983 | UINT64_C(73412608), // ORR_ZZZ |
| 3984 | UINT64_C(1319115776), // ORRv16i8 |
| 3985 | UINT64_C(251663360), // ORRv2i32 |
| 3986 | UINT64_C(251696128), // ORRv4i16 |
| 3987 | UINT64_C(1325405184), // ORRv4i32 |
| 3988 | UINT64_C(1325437952), // ORRv8i16 |
| 3989 | UINT64_C(245373952), // ORRv8i8 |
| 3990 | UINT64_C(68689920), // ORV_VPZ_B |
| 3991 | UINT64_C(81272832), // ORV_VPZ_D |
| 3992 | UINT64_C(72884224), // ORV_VPZ_H |
| 3993 | UINT64_C(77078528), // ORV_VPZ_S |
| 3994 | UINT64_C(3670083584), // PACDA |
| 3995 | UINT64_C(3670084608), // PACDB |
| 3996 | UINT64_C(3670092768), // PACDZA |
| 3997 | UINT64_C(3670093792), // PACDZB |
| 3998 | UINT64_C(2596286464), // PACGA |
| 3999 | UINT64_C(3670081536), // PACIA |
| 4000 | UINT64_C(3573752095), // PACIA1716 |
| 4001 | UINT64_C(3670117374), // PACIA171615 |
| 4002 | UINT64_C(3573752639), // PACIASP |
| 4003 | UINT64_C(3670123518), // PACIASPPC |
| 4004 | UINT64_C(3573752607), // PACIAZ |
| 4005 | UINT64_C(3670082560), // PACIB |
| 4006 | UINT64_C(3573752159), // PACIB1716 |
| 4007 | UINT64_C(3670118398), // PACIB171615 |
| 4008 | UINT64_C(3573752703), // PACIBSP |
| 4009 | UINT64_C(3670124542), // PACIBSPPC |
| 4010 | UINT64_C(3573752671), // PACIBZ |
| 4011 | UINT64_C(3670090720), // PACIZA |
| 4012 | UINT64_C(3670091744), // PACIZB |
| 4013 | UINT64_C(3573753087), // PACM |
| 4014 | UINT64_C(3670115326), // PACNBIASPPC |
| 4015 | UINT64_C(3670116350), // PACNBIBSPPC |
| 4016 | UINT64_C(622883856), // PEXT_2PCI_B |
| 4017 | UINT64_C(635466768), // PEXT_2PCI_D |
| 4018 | UINT64_C(627078160), // PEXT_2PCI_H |
| 4019 | UINT64_C(631272464), // PEXT_2PCI_S |
| 4020 | UINT64_C(622882832), // PEXT_PCI_B |
| 4021 | UINT64_C(635465744), // PEXT_PCI_D |
| 4022 | UINT64_C(627077136), // PEXT_PCI_H |
| 4023 | UINT64_C(631271440), // PEXT_PCI_S |
| 4024 | UINT64_C(622388224), // PFALSE |
| 4025 | UINT64_C(626573312), // PFIRST_B |
| 4026 | UINT64_C(1159789568), // PMLAL_2ZZZ_Q |
| 4027 | UINT64_C(86652928), // PMOV_PZI_B |
| 4028 | UINT64_C(94910464), // PMOV_PZI_D |
| 4029 | UINT64_C(86784000), // PMOV_PZI_H |
| 4030 | UINT64_C(90716160), // PMOV_PZI_S |
| 4031 | UINT64_C(86718464), // PMOV_ZIP_B |
| 4032 | UINT64_C(94976000), // PMOV_ZIP_D |
| 4033 | UINT64_C(86849536), // PMOV_ZIP_H |
| 4034 | UINT64_C(90781696), // PMOV_ZIP_S |
| 4035 | UINT64_C(1170237440), // PMULLB_ZZZ_D |
| 4036 | UINT64_C(1161848832), // PMULLB_ZZZ_H |
| 4037 | UINT64_C(1157654528), // PMULLB_ZZZ_Q |
| 4038 | UINT64_C(1170238464), // PMULLT_ZZZ_D |
| 4039 | UINT64_C(1161849856), // PMULLT_ZZZ_H |
| 4040 | UINT64_C(1157655552), // PMULLT_ZZZ_Q |
| 4041 | UINT64_C(1159788544), // PMULL_2ZZZ_Q |
| 4042 | UINT64_C(1310777344), // PMULLv16i8 |
| 4043 | UINT64_C(249618432), // PMULLv1i64 |
| 4044 | UINT64_C(1323360256), // PMULLv2i64 |
| 4045 | UINT64_C(237035520), // PMULLv8i8 |
| 4046 | UINT64_C(69231616), // PMUL_ZZZ_B |
| 4047 | UINT64_C(1847630848), // PMULv16i8 |
| 4048 | UINT64_C(773889024), // PMULv8i8 |
| 4049 | UINT64_C(622445568), // PNEXT_B |
| 4050 | UINT64_C(635028480), // PNEXT_D |
| 4051 | UINT64_C(626639872), // PNEXT_H |
| 4052 | UINT64_C(630834176), // PNEXT_S |
| 4053 | UINT64_C(3288391680), // PRFB_D_PZI |
| 4054 | UINT64_C(3294658560), // PRFB_D_SCALED |
| 4055 | UINT64_C(3294625792), // PRFB_D_SXTW_SCALED |
| 4056 | UINT64_C(3290431488), // PRFB_D_UXTW_SCALED |
| 4057 | UINT64_C(2243952640), // PRFB_PRI |
| 4058 | UINT64_C(2214641664), // PRFB_PRR |
| 4059 | UINT64_C(2214649856), // PRFB_S_PZI |
| 4060 | UINT64_C(2220883968), // PRFB_S_SXTW_SCALED |
| 4061 | UINT64_C(2216689664), // PRFB_S_UXTW_SCALED |
| 4062 | UINT64_C(3313557504), // PRFD_D_PZI |
| 4063 | UINT64_C(3294683136), // PRFD_D_SCALED |
| 4064 | UINT64_C(3294650368), // PRFD_D_SXTW_SCALED |
| 4065 | UINT64_C(3290456064), // PRFD_D_UXTW_SCALED |
| 4066 | UINT64_C(2243977216), // PRFD_PRI |
| 4067 | UINT64_C(2239807488), // PRFD_PRR |
| 4068 | UINT64_C(2239815680), // PRFD_S_PZI |
| 4069 | UINT64_C(2220908544), // PRFD_S_SXTW_SCALED |
| 4070 | UINT64_C(2216714240), // PRFD_S_UXTW_SCALED |
| 4071 | UINT64_C(3296780288), // PRFH_D_PZI |
| 4072 | UINT64_C(3294666752), // PRFH_D_SCALED |
| 4073 | UINT64_C(3294633984), // PRFH_D_SXTW_SCALED |
| 4074 | UINT64_C(3290439680), // PRFH_D_UXTW_SCALED |
| 4075 | UINT64_C(2243960832), // PRFH_PRI |
| 4076 | UINT64_C(2223030272), // PRFH_PRR |
| 4077 | UINT64_C(2223038464), // PRFH_S_PZI |
| 4078 | UINT64_C(2220892160), // PRFH_S_SXTW_SCALED |
| 4079 | UINT64_C(2216697856), // PRFH_S_UXTW_SCALED |
| 4080 | UINT64_C(3623878656), // PRFMl |
| 4081 | UINT64_C(4171253760), // PRFMroW |
| 4082 | UINT64_C(4171261952), // PRFMroX |
| 4083 | UINT64_C(4185915392), // PRFMui |
| 4084 | UINT64_C(4169138176), // PRFUMi |
| 4085 | UINT64_C(3305168896), // PRFW_D_PZI |
| 4086 | UINT64_C(3294674944), // PRFW_D_SCALED |
| 4087 | UINT64_C(3294642176), // PRFW_D_SXTW_SCALED |
| 4088 | UINT64_C(3290447872), // PRFW_D_UXTW_SCALED |
| 4089 | UINT64_C(2243969024), // PRFW_PRI |
| 4090 | UINT64_C(2231418880), // PRFW_PRR |
| 4091 | UINT64_C(2231427072), // PRFW_S_PZI |
| 4092 | UINT64_C(2220900352), // PRFW_S_SXTW_SCALED |
| 4093 | UINT64_C(2216706048), // PRFW_S_UXTW_SCALED |
| 4094 | UINT64_C(623132672), // PSEL_PPPRI_B |
| 4095 | UINT64_C(627064832), // PSEL_PPPRI_D |
| 4096 | UINT64_C(623394816), // PSEL_PPPRI_H |
| 4097 | UINT64_C(623919104), // PSEL_PPPRI_S |
| 4098 | UINT64_C(626049024), // PTEST_PP |
| 4099 | UINT64_C(622452736), // PTRUES_B |
| 4100 | UINT64_C(635035648), // PTRUES_D |
| 4101 | UINT64_C(626647040), // PTRUES_H |
| 4102 | UINT64_C(630841344), // PTRUES_S |
| 4103 | UINT64_C(622387200), // PTRUE_B |
| 4104 | UINT64_C(622884880), // PTRUE_C_B |
| 4105 | UINT64_C(635467792), // PTRUE_C_D |
| 4106 | UINT64_C(627079184), // PTRUE_C_H |
| 4107 | UINT64_C(631273488), // PTRUE_C_S |
| 4108 | UINT64_C(634970112), // PTRUE_D |
| 4109 | UINT64_C(626581504), // PTRUE_H |
| 4110 | UINT64_C(630775808), // PTRUE_S |
| 4111 | UINT64_C(87113728), // PUNPKHI_PP |
| 4112 | UINT64_C(87048192), // PUNPKLO_PP |
| 4113 | UINT64_C(1163945984), // RADDHNB_ZZZ_B |
| 4114 | UINT64_C(1168140288), // RADDHNB_ZZZ_H |
| 4115 | UINT64_C(1172334592), // RADDHNB_ZZZ_S |
| 4116 | UINT64_C(1163947008), // RADDHNT_ZZZ_B |
| 4117 | UINT64_C(1168141312), // RADDHNT_ZZZ_H |
| 4118 | UINT64_C(1172335616), // RADDHNT_ZZZ_S |
| 4119 | UINT64_C(782254080), // RADDHNv2i64_v2i32 |
| 4120 | UINT64_C(1855995904), // RADDHNv2i64_v4i32 |
| 4121 | UINT64_C(778059776), // RADDHNv4i32_v4i16 |
| 4122 | UINT64_C(1851801600), // RADDHNv4i32_v8i16 |
| 4123 | UINT64_C(1847607296), // RADDHNv8i16_v16i8 |
| 4124 | UINT64_C(773865472), // RADDHNv8i16_v8i8 |
| 4125 | UINT64_C(3462433792), // RAX1 |
| 4126 | UINT64_C(1159787520), // RAX1_ZZZ_D |
| 4127 | UINT64_C(1522532352), // RBITWr |
| 4128 | UINT64_C(3670016000), // RBITXr |
| 4129 | UINT64_C(86474752), // RBIT_ZPmZ_B |
| 4130 | UINT64_C(99057664), // RBIT_ZPmZ_D |
| 4131 | UINT64_C(90669056), // RBIT_ZPmZ_H |
| 4132 | UINT64_C(94863360), // RBIT_ZPmZ_S |
| 4133 | UINT64_C(86482944), // RBIT_ZPzZ_B |
| 4134 | UINT64_C(99065856), // RBIT_ZPzZ_D |
| 4135 | UINT64_C(90677248), // RBIT_ZPzZ_H |
| 4136 | UINT64_C(94871552), // RBIT_ZPzZ_S |
| 4137 | UINT64_C(1851807744), // RBITv16i8 |
| 4138 | UINT64_C(778065920), // RBITv8i8 |
| 4139 | UINT64_C(421529600), // RCWCAS |
| 4140 | UINT64_C(429918208), // RCWCASA |
| 4141 | UINT64_C(434112512), // RCWCASAL |
| 4142 | UINT64_C(425723904), // RCWCASL |
| 4143 | UINT64_C(421530624), // RCWCASP |
| 4144 | UINT64_C(429919232), // RCWCASPA |
| 4145 | UINT64_C(434113536), // RCWCASPAL |
| 4146 | UINT64_C(425724928), // RCWCASPL |
| 4147 | UINT64_C(941658112), // RCWCLR |
| 4148 | UINT64_C(950046720), // RCWCLRA |
| 4149 | UINT64_C(954241024), // RCWCLRAL |
| 4150 | UINT64_C(945852416), // RCWCLRL |
| 4151 | UINT64_C(421564416), // RCWCLRP |
| 4152 | UINT64_C(429953024), // RCWCLRPA |
| 4153 | UINT64_C(434147328), // RCWCLRPAL |
| 4154 | UINT64_C(425758720), // RCWCLRPL |
| 4155 | UINT64_C(2015399936), // RCWCLRS |
| 4156 | UINT64_C(2023788544), // RCWCLRSA |
| 4157 | UINT64_C(2027982848), // RCWCLRSAL |
| 4158 | UINT64_C(2019594240), // RCWCLRSL |
| 4159 | UINT64_C(1495306240), // RCWCLRSP |
| 4160 | UINT64_C(1503694848), // RCWCLRSPA |
| 4161 | UINT64_C(1507889152), // RCWCLRSPAL |
| 4162 | UINT64_C(1499500544), // RCWCLRSPL |
| 4163 | UINT64_C(1495271424), // RCWSCAS |
| 4164 | UINT64_C(1503660032), // RCWSCASA |
| 4165 | UINT64_C(1507854336), // RCWSCASAL |
| 4166 | UINT64_C(1499465728), // RCWSCASL |
| 4167 | UINT64_C(1495272448), // RCWSCASP |
| 4168 | UINT64_C(1503661056), // RCWSCASPA |
| 4169 | UINT64_C(1507855360), // RCWSCASPAL |
| 4170 | UINT64_C(1499466752), // RCWSCASPL |
| 4171 | UINT64_C(941666304), // RCWSET |
| 4172 | UINT64_C(950054912), // RCWSETA |
| 4173 | UINT64_C(954249216), // RCWSETAL |
| 4174 | UINT64_C(945860608), // RCWSETL |
| 4175 | UINT64_C(421572608), // RCWSETP |
| 4176 | UINT64_C(429961216), // RCWSETPA |
| 4177 | UINT64_C(434155520), // RCWSETPAL |
| 4178 | UINT64_C(425766912), // RCWSETPL |
| 4179 | UINT64_C(2015408128), // RCWSETS |
| 4180 | UINT64_C(2023796736), // RCWSETSA |
| 4181 | UINT64_C(2027991040), // RCWSETSAL |
| 4182 | UINT64_C(2019602432), // RCWSETSL |
| 4183 | UINT64_C(1495314432), // RCWSETSP |
| 4184 | UINT64_C(1503703040), // RCWSETSPA |
| 4185 | UINT64_C(1507897344), // RCWSETSPAL |
| 4186 | UINT64_C(1499508736), // RCWSETSPL |
| 4187 | UINT64_C(941662208), // RCWSWP |
| 4188 | UINT64_C(950050816), // RCWSWPA |
| 4189 | UINT64_C(954245120), // RCWSWPAL |
| 4190 | UINT64_C(945856512), // RCWSWPL |
| 4191 | UINT64_C(421568512), // RCWSWPP |
| 4192 | UINT64_C(429957120), // RCWSWPPA |
| 4193 | UINT64_C(434151424), // RCWSWPPAL |
| 4194 | UINT64_C(425762816), // RCWSWPPL |
| 4195 | UINT64_C(2015404032), // RCWSWPS |
| 4196 | UINT64_C(2023792640), // RCWSWPSA |
| 4197 | UINT64_C(2027986944), // RCWSWPSAL |
| 4198 | UINT64_C(2019598336), // RCWSWPSL |
| 4199 | UINT64_C(1495310336), // RCWSWPSP |
| 4200 | UINT64_C(1503698944), // RCWSWPSPA |
| 4201 | UINT64_C(1507893248), // RCWSWPSPAL |
| 4202 | UINT64_C(1499504640), // RCWSWPSPL |
| 4203 | UINT64_C(626585600), // RDFFRS_PPz |
| 4204 | UINT64_C(622456832), // RDFFR_P |
| 4205 | UINT64_C(622391296), // RDFFR_PPz |
| 4206 | UINT64_C(79648768), // RDSVLI_XI |
| 4207 | UINT64_C(79646720), // RDVLI_XI |
| 4208 | UINT64_C(3596550144), // RET |
| 4209 | UINT64_C(3596553215), // RETAA |
| 4210 | UINT64_C(1426063391), // RETAASPPCi |
| 4211 | UINT64_C(3596553184), // RETAASPPCr |
| 4212 | UINT64_C(3596554239), // RETAB |
| 4213 | UINT64_C(1428160543), // RETABSPPCi |
| 4214 | UINT64_C(3596554208), // RETABSPPCr |
| 4215 | UINT64_C(1522533376), // REV16Wr |
| 4216 | UINT64_C(3670017024), // REV16Xr |
| 4217 | UINT64_C(1310726144), // REV16v16i8 |
| 4218 | UINT64_C(236984320), // REV16v8i8 |
| 4219 | UINT64_C(3670018048), // REV32Xr |
| 4220 | UINT64_C(1847592960), // REV32v16i8 |
| 4221 | UINT64_C(778045440), // REV32v4i16 |
| 4222 | UINT64_C(1851787264), // REV32v8i16 |
| 4223 | UINT64_C(773851136), // REV32v8i8 |
| 4224 | UINT64_C(1310722048), // REV64v16i8 |
| 4225 | UINT64_C(245368832), // REV64v2i32 |
| 4226 | UINT64_C(241174528), // REV64v4i16 |
| 4227 | UINT64_C(1319110656), // REV64v4i32 |
| 4228 | UINT64_C(1314916352), // REV64v8i16 |
| 4229 | UINT64_C(236980224), // REV64v8i8 |
| 4230 | UINT64_C(98861056), // REVB_ZPmZ_D |
| 4231 | UINT64_C(90472448), // REVB_ZPmZ_H |
| 4232 | UINT64_C(94666752), // REVB_ZPmZ_S |
| 4233 | UINT64_C(98869248), // REVB_ZPzZ_D |
| 4234 | UINT64_C(90480640), // REVB_ZPzZ_H |
| 4235 | UINT64_C(94674944), // REVB_ZPzZ_S |
| 4236 | UINT64_C(86933504), // REVD_ZPmZ |
| 4237 | UINT64_C(86941696), // REVD_ZPzZ |
| 4238 | UINT64_C(98926592), // REVH_ZPmZ_D |
| 4239 | UINT64_C(94732288), // REVH_ZPmZ_S |
| 4240 | UINT64_C(98934784), // REVH_ZPzZ_D |
| 4241 | UINT64_C(94740480), // REVH_ZPzZ_S |
| 4242 | UINT64_C(98992128), // REVW_ZPmZ_D |
| 4243 | UINT64_C(99000320), // REVW_ZPzZ_D |
| 4244 | UINT64_C(1522534400), // REVWr |
| 4245 | UINT64_C(3670019072), // REVXr |
| 4246 | UINT64_C(87310336), // REV_PP_B |
| 4247 | UINT64_C(99893248), // REV_PP_D |
| 4248 | UINT64_C(91504640), // REV_PP_H |
| 4249 | UINT64_C(95698944), // REV_PP_S |
| 4250 | UINT64_C(87570432), // REV_ZZ_B |
| 4251 | UINT64_C(100153344), // REV_ZZ_D |
| 4252 | UINT64_C(91764736), // REV_ZZ_H |
| 4253 | UINT64_C(95959040), // REV_ZZ_S |
| 4254 | UINT64_C(3120563200), // RMIF |
| 4255 | UINT64_C(448801792), // RORVWr |
| 4256 | UINT64_C(2596285440), // RORVXr |
| 4257 | UINT64_C(4171253784), // RPRFM |
| 4258 | UINT64_C(1160255488), // RSHRNB_ZZI_B |
| 4259 | UINT64_C(1160779776), // RSHRNB_ZZI_H |
| 4260 | UINT64_C(1163925504), // RSHRNB_ZZI_S |
| 4261 | UINT64_C(1160256512), // RSHRNT_ZZI_B |
| 4262 | UINT64_C(1160780800), // RSHRNT_ZZI_H |
| 4263 | UINT64_C(1163926528), // RSHRNT_ZZI_S |
| 4264 | UINT64_C(1325960192), // RSHRNv16i8_shift |
| 4265 | UINT64_C(253791232), // RSHRNv2i32_shift |
| 4266 | UINT64_C(252742656), // RSHRNv4i16_shift |
| 4267 | UINT64_C(1327533056), // RSHRNv4i32_shift |
| 4268 | UINT64_C(1326484480), // RSHRNv8i16_shift |
| 4269 | UINT64_C(252218368), // RSHRNv8i8_shift |
| 4270 | UINT64_C(1163950080), // RSUBHNB_ZZZ_B |
| 4271 | UINT64_C(1168144384), // RSUBHNB_ZZZ_H |
| 4272 | UINT64_C(1172338688), // RSUBHNB_ZZZ_S |
| 4273 | UINT64_C(1163951104), // RSUBHNT_ZZZ_B |
| 4274 | UINT64_C(1168145408), // RSUBHNT_ZZZ_H |
| 4275 | UINT64_C(1172339712), // RSUBHNT_ZZZ_S |
| 4276 | UINT64_C(782262272), // RSUBHNv2i64_v2i32 |
| 4277 | UINT64_C(1856004096), // RSUBHNv2i64_v4i32 |
| 4278 | UINT64_C(778067968), // RSUBHNv4i32_v4i16 |
| 4279 | UINT64_C(1851809792), // RSUBHNv4i32_v8i16 |
| 4280 | UINT64_C(1847615488), // RSUBHNv8i16_v16i8 |
| 4281 | UINT64_C(773873664), // RSUBHNv8i16_v8i8 |
| 4282 | UINT64_C(1170259968), // SABALB_ZZZ_D |
| 4283 | UINT64_C(1161871360), // SABALB_ZZZ_H |
| 4284 | UINT64_C(1166065664), // SABALB_ZZZ_S |
| 4285 | UINT64_C(1170260992), // SABALT_ZZZ_D |
| 4286 | UINT64_C(1161872384), // SABALT_ZZZ_H |
| 4287 | UINT64_C(1166066688), // SABALT_ZZZ_S |
| 4288 | UINT64_C(1145099264), // SABAL_ZZZ_BtoH |
| 4289 | UINT64_C(1149293568), // SABAL_ZZZ_HtoS |
| 4290 | UINT64_C(1153487872), // SABAL_ZZZ_StoD |
| 4291 | UINT64_C(1310740480), // SABALv16i8_v8i16 |
| 4292 | UINT64_C(245387264), // SABALv2i32_v2i64 |
| 4293 | UINT64_C(241192960), // SABALv4i16_v4i32 |
| 4294 | UINT64_C(1319129088), // SABALv4i32_v2i64 |
| 4295 | UINT64_C(1314934784), // SABALv8i16_v4i32 |
| 4296 | UINT64_C(236998656), // SABALv8i8_v8i16 |
| 4297 | UINT64_C(1157691392), // SABA_ZZZ_B |
| 4298 | UINT64_C(1170274304), // SABA_ZZZ_D |
| 4299 | UINT64_C(1161885696), // SABA_ZZZ_H |
| 4300 | UINT64_C(1166080000), // SABA_ZZZ_S |
| 4301 | UINT64_C(1310751744), // SABAv16i8 |
| 4302 | UINT64_C(245398528), // SABAv2i32 |
| 4303 | UINT64_C(241204224), // SABAv4i16 |
| 4304 | UINT64_C(1319140352), // SABAv4i32 |
| 4305 | UINT64_C(1314946048), // SABAv8i16 |
| 4306 | UINT64_C(237009920), // SABAv8i8 |
| 4307 | UINT64_C(1170223104), // SABDLB_ZZZ_D |
| 4308 | UINT64_C(1161834496), // SABDLB_ZZZ_H |
| 4309 | UINT64_C(1166028800), // SABDLB_ZZZ_S |
| 4310 | UINT64_C(1170224128), // SABDLT_ZZZ_D |
| 4311 | UINT64_C(1161835520), // SABDLT_ZZZ_H |
| 4312 | UINT64_C(1166029824), // SABDLT_ZZZ_S |
| 4313 | UINT64_C(1310748672), // SABDLv16i8_v8i16 |
| 4314 | UINT64_C(245395456), // SABDLv2i32_v2i64 |
| 4315 | UINT64_C(241201152), // SABDLv4i16_v4i32 |
| 4316 | UINT64_C(1319137280), // SABDLv4i32_v2i64 |
| 4317 | UINT64_C(1314942976), // SABDLv8i16_v4i32 |
| 4318 | UINT64_C(237006848), // SABDLv8i8_v8i16 |
| 4319 | UINT64_C(67895296), // SABD_ZPmZ_B |
| 4320 | UINT64_C(80478208), // SABD_ZPmZ_D |
| 4321 | UINT64_C(72089600), // SABD_ZPmZ_H |
| 4322 | UINT64_C(76283904), // SABD_ZPmZ_S |
| 4323 | UINT64_C(1310749696), // SABDv16i8 |
| 4324 | UINT64_C(245396480), // SABDv2i32 |
| 4325 | UINT64_C(241202176), // SABDv4i16 |
| 4326 | UINT64_C(1319138304), // SABDv4i32 |
| 4327 | UINT64_C(1314944000), // SABDv8i16 |
| 4328 | UINT64_C(237007872), // SABDv8i8 |
| 4329 | UINT64_C(1153736704), // SADALP_ZPmZ_D |
| 4330 | UINT64_C(1145348096), // SADALP_ZPmZ_H |
| 4331 | UINT64_C(1149542400), // SADALP_ZPmZ_S |
| 4332 | UINT64_C(1310746624), // SADALPv16i8_v8i16 |
| 4333 | UINT64_C(245393408), // SADALPv2i32_v1i64 |
| 4334 | UINT64_C(241199104), // SADALPv4i16_v2i32 |
| 4335 | UINT64_C(1319135232), // SADALPv4i32_v2i64 |
| 4336 | UINT64_C(1314940928), // SADALPv8i16_v4i32 |
| 4337 | UINT64_C(237004800), // SADALPv8i8_v4i16 |
| 4338 | UINT64_C(1170243584), // SADDLBT_ZZZ_D |
| 4339 | UINT64_C(1161854976), // SADDLBT_ZZZ_H |
| 4340 | UINT64_C(1166049280), // SADDLBT_ZZZ_S |
| 4341 | UINT64_C(1170210816), // SADDLB_ZZZ_D |
| 4342 | UINT64_C(1161822208), // SADDLB_ZZZ_H |
| 4343 | UINT64_C(1166016512), // SADDLB_ZZZ_S |
| 4344 | UINT64_C(1310730240), // SADDLPv16i8_v8i16 |
| 4345 | UINT64_C(245377024), // SADDLPv2i32_v1i64 |
| 4346 | UINT64_C(241182720), // SADDLPv4i16_v2i32 |
| 4347 | UINT64_C(1319118848), // SADDLPv4i32_v2i64 |
| 4348 | UINT64_C(1314924544), // SADDLPv8i16_v4i32 |
| 4349 | UINT64_C(236988416), // SADDLPv8i8_v4i16 |
| 4350 | UINT64_C(1170211840), // SADDLT_ZZZ_D |
| 4351 | UINT64_C(1161823232), // SADDLT_ZZZ_H |
| 4352 | UINT64_C(1166017536), // SADDLT_ZZZ_S |
| 4353 | UINT64_C(1311782912), // SADDLVv16i8v |
| 4354 | UINT64_C(242235392), // SADDLVv4i16v |
| 4355 | UINT64_C(1320171520), // SADDLVv4i32v |
| 4356 | UINT64_C(1315977216), // SADDLVv8i16v |
| 4357 | UINT64_C(238041088), // SADDLVv8i8v |
| 4358 | UINT64_C(1310720000), // SADDLv16i8_v8i16 |
| 4359 | UINT64_C(245366784), // SADDLv2i32_v2i64 |
| 4360 | UINT64_C(241172480), // SADDLv4i16_v4i32 |
| 4361 | UINT64_C(1319108608), // SADDLv4i32_v2i64 |
| 4362 | UINT64_C(1314914304), // SADDLv8i16_v4i32 |
| 4363 | UINT64_C(236978176), // SADDLv8i8_v8i16 |
| 4364 | UINT64_C(67117056), // SADDV_VPZ_B |
| 4365 | UINT64_C(71311360), // SADDV_VPZ_H |
| 4366 | UINT64_C(75505664), // SADDV_VPZ_S |
| 4367 | UINT64_C(1170227200), // SADDWB_ZZZ_D |
| 4368 | UINT64_C(1161838592), // SADDWB_ZZZ_H |
| 4369 | UINT64_C(1166032896), // SADDWB_ZZZ_S |
| 4370 | UINT64_C(1170228224), // SADDWT_ZZZ_D |
| 4371 | UINT64_C(1161839616), // SADDWT_ZZZ_H |
| 4372 | UINT64_C(1166033920), // SADDWT_ZZZ_S |
| 4373 | UINT64_C(1310724096), // SADDWv16i8_v8i16 |
| 4374 | UINT64_C(245370880), // SADDWv2i32_v2i64 |
| 4375 | UINT64_C(241176576), // SADDWv4i16_v4i32 |
| 4376 | UINT64_C(1319112704), // SADDWv4i32_v2i64 |
| 4377 | UINT64_C(1314918400), // SADDWv8i16_v4i32 |
| 4378 | UINT64_C(236982272), // SADDWv8i8_v8i16 |
| 4379 | UINT64_C(3573756159), // SB |
| 4380 | UINT64_C(1170264064), // SBCLB_ZZZ_D |
| 4381 | UINT64_C(1166069760), // SBCLB_ZZZ_S |
| 4382 | UINT64_C(1170265088), // SBCLT_ZZZ_D |
| 4383 | UINT64_C(1166070784), // SBCLT_ZZZ_S |
| 4384 | UINT64_C(2046820352), // SBCSWr |
| 4385 | UINT64_C(4194304000), // SBCSXr |
| 4386 | UINT64_C(1509949440), // SBCWr |
| 4387 | UINT64_C(3657433088), // SBCXr |
| 4388 | UINT64_C(318767104), // SBFMWri |
| 4389 | UINT64_C(2470445056), // SBFMXri |
| 4390 | UINT64_C(3240150016), // SCLAMP_VG2_2Z2Z_B |
| 4391 | UINT64_C(3252732928), // SCLAMP_VG2_2Z2Z_D |
| 4392 | UINT64_C(3244344320), // SCLAMP_VG2_2Z2Z_H |
| 4393 | UINT64_C(3248538624), // SCLAMP_VG2_2Z2Z_S |
| 4394 | UINT64_C(3240152064), // SCLAMP_VG4_4Z4Z_B |
| 4395 | UINT64_C(3252734976), // SCLAMP_VG4_4Z4Z_D |
| 4396 | UINT64_C(3244346368), // SCLAMP_VG4_4Z4Z_H |
| 4397 | UINT64_C(3248540672), // SCLAMP_VG4_4Z4Z_S |
| 4398 | UINT64_C(1140899840), // SCLAMP_ZZZ_B |
| 4399 | UINT64_C(1153482752), // SCLAMP_ZZZ_D |
| 4400 | UINT64_C(1145094144), // SCLAMP_ZZZ_H |
| 4401 | UINT64_C(1149288448), // SCLAMP_ZZZ_S |
| 4402 | UINT64_C(511442944), // SCVTFDSr |
| 4403 | UINT64_C(2667315200), // SCVTFHDr |
| 4404 | UINT64_C(519831552), // SCVTFHSr |
| 4405 | UINT64_C(1699493888), // SCVTFLT_ZZ_BtoH |
| 4406 | UINT64_C(1703688192), // SCVTFLT_ZZ_HtoS |
| 4407 | UINT64_C(1707882496), // SCVTFLT_ZZ_StoD |
| 4408 | UINT64_C(2654732288), // SCVTFSDr |
| 4409 | UINT64_C(507674624), // SCVTFSWDri |
| 4410 | UINT64_C(516063232), // SCVTFSWHri |
| 4411 | UINT64_C(503480320), // SCVTFSWSri |
| 4412 | UINT64_C(2655125504), // SCVTFSXDri |
| 4413 | UINT64_C(2663514112), // SCVTFSXHri |
| 4414 | UINT64_C(2650931200), // SCVTFSXSri |
| 4415 | UINT64_C(509739008), // SCVTFUWDri |
| 4416 | UINT64_C(518127616), // SCVTFUWHri |
| 4417 | UINT64_C(505544704), // SCVTFUWSri |
| 4418 | UINT64_C(2657222656), // SCVTFUXDri |
| 4419 | UINT64_C(2665611264), // SCVTFUXHri |
| 4420 | UINT64_C(2653028352), // SCVTFUXSri |
| 4421 | UINT64_C(3240288256), // SCVTF_2Z2Z_StoS |
| 4422 | UINT64_C(3241336832), // SCVTF_4Z4Z_StoS |
| 4423 | UINT64_C(1708564480), // SCVTF_ZPmZ_DtoD |
| 4424 | UINT64_C(1700175872), // SCVTF_ZPmZ_DtoH |
| 4425 | UINT64_C(1708433408), // SCVTF_ZPmZ_DtoS |
| 4426 | UINT64_C(1699913728), // SCVTF_ZPmZ_HtoH |
| 4427 | UINT64_C(1708171264), // SCVTF_ZPmZ_StoD |
| 4428 | UINT64_C(1700044800), // SCVTF_ZPmZ_StoH |
| 4429 | UINT64_C(1704239104), // SCVTF_ZPmZ_StoS |
| 4430 | UINT64_C(1692254208), // SCVTF_ZPzZ_DtoD |
| 4431 | UINT64_C(1683865600), // SCVTF_ZPzZ_DtoH |
| 4432 | UINT64_C(1692237824), // SCVTF_ZPzZ_DtoS |
| 4433 | UINT64_C(1683800064), // SCVTF_ZPzZ_HtoH |
| 4434 | UINT64_C(1692172288), // SCVTF_ZPzZ_StoD |
| 4435 | UINT64_C(1683849216), // SCVTF_ZPzZ_StoH |
| 4436 | UINT64_C(1688043520), // SCVTF_ZPzZ_StoS |
| 4437 | UINT64_C(1699491840), // SCVTF_ZZ_BtoH |
| 4438 | UINT64_C(1703686144), // SCVTF_ZZ_HtoS |
| 4439 | UINT64_C(1707880448), // SCVTF_ZZ_StoD |
| 4440 | UINT64_C(1598088192), // SCVTFd |
| 4441 | UINT64_C(1594942464), // SCVTFh |
| 4442 | UINT64_C(1595991040), // SCVTFs |
| 4443 | UINT64_C(1585043456), // SCVTFv1i16 |
| 4444 | UINT64_C(1579276288), // SCVTFv1i32 |
| 4445 | UINT64_C(1583470592), // SCVTFv1i64 |
| 4446 | UINT64_C(237099008), // SCVTFv2f32 |
| 4447 | UINT64_C(1315035136), // SCVTFv2f64 |
| 4448 | UINT64_C(253813760), // SCVTFv2i32_shift |
| 4449 | UINT64_C(1329652736), // SCVTFv2i64_shift |
| 4450 | UINT64_C(242866176), // SCVTFv4f16 |
| 4451 | UINT64_C(1310840832), // SCVTFv4f32 |
| 4452 | UINT64_C(252765184), // SCVTFv4i16_shift |
| 4453 | UINT64_C(1327555584), // SCVTFv4i32_shift |
| 4454 | UINT64_C(1316608000), // SCVTFv8f16 |
| 4455 | UINT64_C(1326507008), // SCVTFv8i16_shift |
| 4456 | UINT64_C(81133568), // SDIVR_ZPmZ_D |
| 4457 | UINT64_C(76939264), // SDIVR_ZPmZ_S |
| 4458 | UINT64_C(448793600), // SDIVWr |
| 4459 | UINT64_C(2596277248), // SDIVXr |
| 4460 | UINT64_C(81002496), // SDIV_ZPmZ_D |
| 4461 | UINT64_C(76808192), // SDIV_ZPmZ_S |
| 4462 | UINT64_C(3248493568), // SDOT_VG2_M2Z2Z_BtoS |
| 4463 | UINT64_C(3252687872), // SDOT_VG2_M2Z2Z_HtoD |
| 4464 | UINT64_C(3252687880), // SDOT_VG2_M2Z2Z_HtoS |
| 4465 | UINT64_C(3243249696), // SDOT_VG2_M2ZZI_BToS |
| 4466 | UINT64_C(3243249664), // SDOT_VG2_M2ZZI_HToS |
| 4467 | UINT64_C(3251634184), // SDOT_VG2_M2ZZI_HtoD |
| 4468 | UINT64_C(3240104960), // SDOT_VG2_M2ZZ_BtoS |
| 4469 | UINT64_C(3244299264), // SDOT_VG2_M2ZZ_HtoD |
| 4470 | UINT64_C(3244299272), // SDOT_VG2_M2ZZ_HtoS |
| 4471 | UINT64_C(3248559104), // SDOT_VG4_M4Z4Z_BtoS |
| 4472 | UINT64_C(3252753408), // SDOT_VG4_M4Z4Z_HtoD |
| 4473 | UINT64_C(3252753416), // SDOT_VG4_M4Z4Z_HtoS |
| 4474 | UINT64_C(3243282464), // SDOT_VG4_M4ZZI_BToS |
| 4475 | UINT64_C(3243282432), // SDOT_VG4_M4ZZI_HToS |
| 4476 | UINT64_C(3251666952), // SDOT_VG4_M4ZZI_HtoD |
| 4477 | UINT64_C(3241153536), // SDOT_VG4_M4ZZ_BtoS |
| 4478 | UINT64_C(3245347840), // SDOT_VG4_M4ZZ_HtoD |
| 4479 | UINT64_C(3245347848), // SDOT_VG4_M4ZZ_HtoS |
| 4480 | UINT64_C(1142947840), // SDOT_ZZZI_BtoH |
| 4481 | UINT64_C(1151336448), // SDOT_ZZZI_BtoS |
| 4482 | UINT64_C(1155530752), // SDOT_ZZZI_HtoD |
| 4483 | UINT64_C(1149290496), // SDOT_ZZZI_HtoS |
| 4484 | UINT64_C(1145044992), // SDOT_ZZZ_BtoH |
| 4485 | UINT64_C(1149239296), // SDOT_ZZZ_BtoS |
| 4486 | UINT64_C(1153433600), // SDOT_ZZZ_HtoD |
| 4487 | UINT64_C(1140901888), // SDOT_ZZZ_HtoS |
| 4488 | UINT64_C(1333846016), // SDOTlanev16i8 |
| 4489 | UINT64_C(260104192), // SDOTlanev8i8 |
| 4490 | UINT64_C(1317049344), // SDOTv16i8 |
| 4491 | UINT64_C(243307520), // SDOTv8i8 |
| 4492 | UINT64_C(620773904), // SEL_PPPP |
| 4493 | UINT64_C(3240132608), // SEL_VG2_2ZC2Z2Z_B |
| 4494 | UINT64_C(3252715520), // SEL_VG2_2ZC2Z2Z_D |
| 4495 | UINT64_C(3244326912), // SEL_VG2_2ZC2Z2Z_H |
| 4496 | UINT64_C(3248521216), // SEL_VG2_2ZC2Z2Z_S |
| 4497 | UINT64_C(3240198144), // SEL_VG4_4ZC4Z4Z_B |
| 4498 | UINT64_C(3252781056), // SEL_VG4_4ZC4Z4Z_D |
| 4499 | UINT64_C(3244392448), // SEL_VG4_4ZC4Z4Z_H |
| 4500 | UINT64_C(3248586752), // SEL_VG4_4ZC4Z4Z_S |
| 4501 | UINT64_C(86032384), // SEL_ZPZZ_B |
| 4502 | UINT64_C(98615296), // SEL_ZPZZ_D |
| 4503 | UINT64_C(90226688), // SEL_ZPZZ_H |
| 4504 | UINT64_C(94420992), // SEL_ZPZZ_S |
| 4505 | UINT64_C(432047104), // SETE |
| 4506 | UINT64_C(432055296), // SETEN |
| 4507 | UINT64_C(432051200), // SETET |
| 4508 | UINT64_C(432059392), // SETETN |
| 4509 | UINT64_C(973096973), // SETF16 |
| 4510 | UINT64_C(973080589), // SETF8 |
| 4511 | UINT64_C(623677440), // SETFFR |
| 4512 | UINT64_C(499139584), // SETGM |
| 4513 | UINT64_C(499147776), // SETGMN |
| 4514 | UINT64_C(499143680), // SETGMT |
| 4515 | UINT64_C(499151872), // SETGMTN |
| 4516 | UINT64_C(501186560), // SETGOE |
| 4517 | UINT64_C(501194752), // SETGOEN |
| 4518 | UINT64_C(501190656), // SETGOET |
| 4519 | UINT64_C(501198848), // SETGOETN |
| 4520 | UINT64_C(501170176), // SETGOM |
| 4521 | UINT64_C(501178368), // SETGOMN |
| 4522 | UINT64_C(501174272), // SETGOMT |
| 4523 | UINT64_C(501182464), // SETGOMTN |
| 4524 | UINT64_C(501153792), // SETGOP |
| 4525 | UINT64_C(501161984), // SETGOPN |
| 4526 | UINT64_C(501157888), // SETGOPT |
| 4527 | UINT64_C(501166080), // SETGOPTN |
| 4528 | UINT64_C(499123200), // SETGP |
| 4529 | UINT64_C(499131392), // SETGPN |
| 4530 | UINT64_C(499127296), // SETGPT |
| 4531 | UINT64_C(499135488), // SETGPTN |
| 4532 | UINT64_C(432030720), // SETM |
| 4533 | UINT64_C(432038912), // SETMN |
| 4534 | UINT64_C(432034816), // SETMT |
| 4535 | UINT64_C(432043008), // SETMTN |
| 4536 | UINT64_C(432014336), // SETP |
| 4537 | UINT64_C(432022528), // SETPN |
| 4538 | UINT64_C(432018432), // SETPT |
| 4539 | UINT64_C(432026624), // SETPTN |
| 4540 | UINT64_C(1577058304), // SHA1Crrr |
| 4541 | UINT64_C(1579681792), // SHA1Hrr |
| 4542 | UINT64_C(1577066496), // SHA1Mrrr |
| 4543 | UINT64_C(1577062400), // SHA1Prrr |
| 4544 | UINT64_C(1577070592), // SHA1SU0rrr |
| 4545 | UINT64_C(1579685888), // SHA1SU1rr |
| 4546 | UINT64_C(1577078784), // SHA256H2rrr |
| 4547 | UINT64_C(1577074688), // SHA256Hrrr |
| 4548 | UINT64_C(1579689984), // SHA256SU0rr |
| 4549 | UINT64_C(1577082880), // SHA256SU1rrr |
| 4550 | UINT64_C(3462430720), // SHA512H |
| 4551 | UINT64_C(3462431744), // SHA512H2 |
| 4552 | UINT64_C(3468722176), // SHA512SU0 |
| 4553 | UINT64_C(3462432768), // SHA512SU1 |
| 4554 | UINT64_C(1141932032), // SHADD_ZPmZ_B |
| 4555 | UINT64_C(1154514944), // SHADD_ZPmZ_D |
| 4556 | UINT64_C(1146126336), // SHADD_ZPmZ_H |
| 4557 | UINT64_C(1150320640), // SHADD_ZPmZ_S |
| 4558 | UINT64_C(1310721024), // SHADDv16i8 |
| 4559 | UINT64_C(245367808), // SHADDv2i32 |
| 4560 | UINT64_C(241173504), // SHADDv4i16 |
| 4561 | UINT64_C(1319109632), // SHADDv4i32 |
| 4562 | UINT64_C(1314915328), // SHADDv8i16 |
| 4563 | UINT64_C(236979200), // SHADDv8i8 |
| 4564 | UINT64_C(1847670784), // SHLLv16i8 |
| 4565 | UINT64_C(782317568), // SHLLv2i32 |
| 4566 | UINT64_C(778123264), // SHLLv4i16 |
| 4567 | UINT64_C(1856059392), // SHLLv4i32 |
| 4568 | UINT64_C(1851865088), // SHLLv8i16 |
| 4569 | UINT64_C(773928960), // SHLLv8i8 |
| 4570 | UINT64_C(1598051328), // SHLd |
| 4571 | UINT64_C(1325945856), // SHLv16i8_shift |
| 4572 | UINT64_C(253776896), // SHLv2i32_shift |
| 4573 | UINT64_C(1329615872), // SHLv2i64_shift |
| 4574 | UINT64_C(252728320), // SHLv4i16_shift |
| 4575 | UINT64_C(1327518720), // SHLv4i32_shift |
| 4576 | UINT64_C(1326470144), // SHLv8i16_shift |
| 4577 | UINT64_C(252204032), // SHLv8i8_shift |
| 4578 | UINT64_C(1160253440), // SHRNB_ZZI_B |
| 4579 | UINT64_C(1160777728), // SHRNB_ZZI_H |
| 4580 | UINT64_C(1163923456), // SHRNB_ZZI_S |
| 4581 | UINT64_C(1160254464), // SHRNT_ZZI_B |
| 4582 | UINT64_C(1160778752), // SHRNT_ZZI_H |
| 4583 | UINT64_C(1163924480), // SHRNT_ZZI_S |
| 4584 | UINT64_C(1325958144), // SHRNv16i8_shift |
| 4585 | UINT64_C(253789184), // SHRNv2i32_shift |
| 4586 | UINT64_C(252740608), // SHRNv4i16_shift |
| 4587 | UINT64_C(1327531008), // SHRNv4i32_shift |
| 4588 | UINT64_C(1326482432), // SHRNv8i16_shift |
| 4589 | UINT64_C(252216320), // SHRNv8i8_shift |
| 4590 | UINT64_C(1142325248), // SHSUBR_ZPmZ_B |
| 4591 | UINT64_C(1154908160), // SHSUBR_ZPmZ_D |
| 4592 | UINT64_C(1146519552), // SHSUBR_ZPmZ_H |
| 4593 | UINT64_C(1150713856), // SHSUBR_ZPmZ_S |
| 4594 | UINT64_C(1142063104), // SHSUB_ZPmZ_B |
| 4595 | UINT64_C(1154646016), // SHSUB_ZPmZ_D |
| 4596 | UINT64_C(1146257408), // SHSUB_ZPmZ_H |
| 4597 | UINT64_C(1150451712), // SHSUB_ZPmZ_S |
| 4598 | UINT64_C(1310729216), // SHSUBv16i8 |
| 4599 | UINT64_C(245376000), // SHSUBv2i32 |
| 4600 | UINT64_C(241181696), // SHSUBv4i16 |
| 4601 | UINT64_C(1319117824), // SHSUBv4i32 |
| 4602 | UINT64_C(1314923520), // SHSUBv8i16 |
| 4603 | UINT64_C(236987392), // SHSUBv8i8 |
| 4604 | UINT64_C(1158214656), // SLI_ZZI_B |
| 4605 | UINT64_C(1166078976), // SLI_ZZI_D |
| 4606 | UINT64_C(1158738944), // SLI_ZZI_H |
| 4607 | UINT64_C(1161884672), // SLI_ZZI_S |
| 4608 | UINT64_C(2134922240), // SLId |
| 4609 | UINT64_C(1862816768), // SLIv16i8_shift |
| 4610 | UINT64_C(790647808), // SLIv2i32_shift |
| 4611 | UINT64_C(1866486784), // SLIv2i64_shift |
| 4612 | UINT64_C(789599232), // SLIv4i16_shift |
| 4613 | UINT64_C(1864389632), // SLIv4i32_shift |
| 4614 | UINT64_C(1863341056), // SLIv8i16_shift |
| 4615 | UINT64_C(789074944), // SLIv8i8_shift |
| 4616 | UINT64_C(3462447104), // SM3PARTW1 |
| 4617 | UINT64_C(3462448128), // SM3PARTW2 |
| 4618 | UINT64_C(3460300800), // SM3SS1 |
| 4619 | UINT64_C(3460333568), // SM3TT1A |
| 4620 | UINT64_C(3460334592), // SM3TT1B |
| 4621 | UINT64_C(3460335616), // SM3TT2A |
| 4622 | UINT64_C(3460336640), // SM3TT2B |
| 4623 | UINT64_C(3468723200), // SM4E |
| 4624 | UINT64_C(1159786496), // SM4EKEY_ZZZ_S |
| 4625 | UINT64_C(3462449152), // SM4ENCKEY |
| 4626 | UINT64_C(1159979008), // SM4E_ZZZ_S |
| 4627 | UINT64_C(2602565632), // SMADDLrrr |
| 4628 | UINT64_C(1142202368), // SMAXP_ZPmZ_B |
| 4629 | UINT64_C(1154785280), // SMAXP_ZPmZ_D |
| 4630 | UINT64_C(1146396672), // SMAXP_ZPmZ_H |
| 4631 | UINT64_C(1150590976), // SMAXP_ZPmZ_S |
| 4632 | UINT64_C(1310761984), // SMAXPv16i8 |
| 4633 | UINT64_C(245408768), // SMAXPv2i32 |
| 4634 | UINT64_C(241214464), // SMAXPv4i16 |
| 4635 | UINT64_C(1319150592), // SMAXPv4i32 |
| 4636 | UINT64_C(1314956288), // SMAXPv8i16 |
| 4637 | UINT64_C(237020160), // SMAXPv8i8 |
| 4638 | UINT64_C(67903488), // SMAXQV_VPZ_B |
| 4639 | UINT64_C(80486400), // SMAXQV_VPZ_D |
| 4640 | UINT64_C(72097792), // SMAXQV_VPZ_H |
| 4641 | UINT64_C(76292096), // SMAXQV_VPZ_S |
| 4642 | UINT64_C(67641344), // SMAXV_VPZ_B |
| 4643 | UINT64_C(80224256), // SMAXV_VPZ_D |
| 4644 | UINT64_C(71835648), // SMAXV_VPZ_H |
| 4645 | UINT64_C(76029952), // SMAXV_VPZ_S |
| 4646 | UINT64_C(1311811584), // SMAXVv16i8v |
| 4647 | UINT64_C(242264064), // SMAXVv4i16v |
| 4648 | UINT64_C(1320200192), // SMAXVv4i32v |
| 4649 | UINT64_C(1316005888), // SMAXVv8i16v |
| 4650 | UINT64_C(238069760), // SMAXVv8i8v |
| 4651 | UINT64_C(297795584), // SMAXWri |
| 4652 | UINT64_C(448815104), // SMAXWrr |
| 4653 | UINT64_C(2445279232), // SMAXXri |
| 4654 | UINT64_C(2596298752), // SMAXXrr |
| 4655 | UINT64_C(3240144896), // SMAX_VG2_2Z2Z_B |
| 4656 | UINT64_C(3252727808), // SMAX_VG2_2Z2Z_D |
| 4657 | UINT64_C(3244339200), // SMAX_VG2_2Z2Z_H |
| 4658 | UINT64_C(3248533504), // SMAX_VG2_2Z2Z_S |
| 4659 | UINT64_C(3240140800), // SMAX_VG2_2ZZ_B |
| 4660 | UINT64_C(3252723712), // SMAX_VG2_2ZZ_D |
| 4661 | UINT64_C(3244335104), // SMAX_VG2_2ZZ_H |
| 4662 | UINT64_C(3248529408), // SMAX_VG2_2ZZ_S |
| 4663 | UINT64_C(3240146944), // SMAX_VG4_4Z4Z_B |
| 4664 | UINT64_C(3252729856), // SMAX_VG4_4Z4Z_D |
| 4665 | UINT64_C(3244341248), // SMAX_VG4_4Z4Z_H |
| 4666 | UINT64_C(3248535552), // SMAX_VG4_4Z4Z_S |
| 4667 | UINT64_C(3240142848), // SMAX_VG4_4ZZ_B |
| 4668 | UINT64_C(3252725760), // SMAX_VG4_4ZZ_D |
| 4669 | UINT64_C(3244337152), // SMAX_VG4_4ZZ_H |
| 4670 | UINT64_C(3248531456), // SMAX_VG4_4ZZ_S |
| 4671 | UINT64_C(623427584), // SMAX_ZI_B |
| 4672 | UINT64_C(636010496), // SMAX_ZI_D |
| 4673 | UINT64_C(627621888), // SMAX_ZI_H |
| 4674 | UINT64_C(631816192), // SMAX_ZI_S |
| 4675 | UINT64_C(67633152), // SMAX_ZPmZ_B |
| 4676 | UINT64_C(80216064), // SMAX_ZPmZ_D |
| 4677 | UINT64_C(71827456), // SMAX_ZPmZ_H |
| 4678 | UINT64_C(76021760), // SMAX_ZPmZ_S |
| 4679 | UINT64_C(1310745600), // SMAXv16i8 |
| 4680 | UINT64_C(245392384), // SMAXv2i32 |
| 4681 | UINT64_C(241198080), // SMAXv4i16 |
| 4682 | UINT64_C(1319134208), // SMAXv4i32 |
| 4683 | UINT64_C(1314939904), // SMAXv8i16 |
| 4684 | UINT64_C(237003776), // SMAXv8i8 |
| 4685 | UINT64_C(3556769795), // SMC |
| 4686 | UINT64_C(1142333440), // SMINP_ZPmZ_B |
| 4687 | UINT64_C(1154916352), // SMINP_ZPmZ_D |
| 4688 | UINT64_C(1146527744), // SMINP_ZPmZ_H |
| 4689 | UINT64_C(1150722048), // SMINP_ZPmZ_S |
| 4690 | UINT64_C(1310764032), // SMINPv16i8 |
| 4691 | UINT64_C(245410816), // SMINPv2i32 |
| 4692 | UINT64_C(241216512), // SMINPv4i16 |
| 4693 | UINT64_C(1319152640), // SMINPv4i32 |
| 4694 | UINT64_C(1314958336), // SMINPv8i16 |
| 4695 | UINT64_C(237022208), // SMINPv8i8 |
| 4696 | UINT64_C(68034560), // SMINQV_VPZ_B |
| 4697 | UINT64_C(80617472), // SMINQV_VPZ_D |
| 4698 | UINT64_C(72228864), // SMINQV_VPZ_H |
| 4699 | UINT64_C(76423168), // SMINQV_VPZ_S |
| 4700 | UINT64_C(67772416), // SMINV_VPZ_B |
| 4701 | UINT64_C(80355328), // SMINV_VPZ_D |
| 4702 | UINT64_C(71966720), // SMINV_VPZ_H |
| 4703 | UINT64_C(76161024), // SMINV_VPZ_S |
| 4704 | UINT64_C(1311877120), // SMINVv16i8v |
| 4705 | UINT64_C(242329600), // SMINVv4i16v |
| 4706 | UINT64_C(1320265728), // SMINVv4i32v |
| 4707 | UINT64_C(1316071424), // SMINVv8i16v |
| 4708 | UINT64_C(238135296), // SMINVv8i8v |
| 4709 | UINT64_C(298319872), // SMINWri |
| 4710 | UINT64_C(448817152), // SMINWrr |
| 4711 | UINT64_C(2445803520), // SMINXri |
| 4712 | UINT64_C(2596300800), // SMINXrr |
| 4713 | UINT64_C(3240144928), // SMIN_VG2_2Z2Z_B |
| 4714 | UINT64_C(3252727840), // SMIN_VG2_2Z2Z_D |
| 4715 | UINT64_C(3244339232), // SMIN_VG2_2Z2Z_H |
| 4716 | UINT64_C(3248533536), // SMIN_VG2_2Z2Z_S |
| 4717 | UINT64_C(3240140832), // SMIN_VG2_2ZZ_B |
| 4718 | UINT64_C(3252723744), // SMIN_VG2_2ZZ_D |
| 4719 | UINT64_C(3244335136), // SMIN_VG2_2ZZ_H |
| 4720 | UINT64_C(3248529440), // SMIN_VG2_2ZZ_S |
| 4721 | UINT64_C(3240146976), // SMIN_VG4_4Z4Z_B |
| 4722 | UINT64_C(3252729888), // SMIN_VG4_4Z4Z_D |
| 4723 | UINT64_C(3244341280), // SMIN_VG4_4Z4Z_H |
| 4724 | UINT64_C(3248535584), // SMIN_VG4_4Z4Z_S |
| 4725 | UINT64_C(3240142880), // SMIN_VG4_4ZZ_B |
| 4726 | UINT64_C(3252725792), // SMIN_VG4_4ZZ_D |
| 4727 | UINT64_C(3244337184), // SMIN_VG4_4ZZ_H |
| 4728 | UINT64_C(3248531488), // SMIN_VG4_4ZZ_S |
| 4729 | UINT64_C(623558656), // SMIN_ZI_B |
| 4730 | UINT64_C(636141568), // SMIN_ZI_D |
| 4731 | UINT64_C(627752960), // SMIN_ZI_H |
| 4732 | UINT64_C(631947264), // SMIN_ZI_S |
| 4733 | UINT64_C(67764224), // SMIN_ZPmZ_B |
| 4734 | UINT64_C(80347136), // SMIN_ZPmZ_D |
| 4735 | UINT64_C(71958528), // SMIN_ZPmZ_H |
| 4736 | UINT64_C(76152832), // SMIN_ZPmZ_S |
| 4737 | UINT64_C(1310747648), // SMINv16i8 |
| 4738 | UINT64_C(245394432), // SMINv2i32 |
| 4739 | UINT64_C(241200128), // SMINv4i16 |
| 4740 | UINT64_C(1319136256), // SMINv4i32 |
| 4741 | UINT64_C(1314941952), // SMINv8i16 |
| 4742 | UINT64_C(237005824), // SMINv8i8 |
| 4743 | UINT64_C(1155563520), // SMLALB_ZZZI_D |
| 4744 | UINT64_C(1151369216), // SMLALB_ZZZI_S |
| 4745 | UINT64_C(1153449984), // SMLALB_ZZZ_D |
| 4746 | UINT64_C(1145061376), // SMLALB_ZZZ_H |
| 4747 | UINT64_C(1149255680), // SMLALB_ZZZ_S |
| 4748 | UINT64_C(3238002688), // SMLALL_MZZI_BtoS |
| 4749 | UINT64_C(3246391296), // SMLALL_MZZI_HtoD |
| 4750 | UINT64_C(3240100864), // SMLALL_MZZ_BtoS |
| 4751 | UINT64_C(3244295168), // SMLALL_MZZ_HtoD |
| 4752 | UINT64_C(3248488448), // SMLALL_VG2_M2Z2Z_BtoS |
| 4753 | UINT64_C(3252682752), // SMLALL_VG2_M2Z2Z_HtoD |
| 4754 | UINT64_C(3239051264), // SMLALL_VG2_M2ZZI_BtoS |
| 4755 | UINT64_C(3247439872), // SMLALL_VG2_M2ZZI_HtoD |
| 4756 | UINT64_C(3240099840), // SMLALL_VG2_M2ZZ_BtoS |
| 4757 | UINT64_C(3244294144), // SMLALL_VG2_M2ZZ_HtoD |
| 4758 | UINT64_C(3248553984), // SMLALL_VG4_M4Z4Z_BtoS |
| 4759 | UINT64_C(3252748288), // SMLALL_VG4_M4Z4Z_HtoD |
| 4760 | UINT64_C(3239084032), // SMLALL_VG4_M4ZZI_BtoS |
| 4761 | UINT64_C(3247472640), // SMLALL_VG4_M4ZZI_HtoD |
| 4762 | UINT64_C(3241148416), // SMLALL_VG4_M4ZZ_BtoS |
| 4763 | UINT64_C(3245342720), // SMLALL_VG4_M4ZZ_HtoD |
| 4764 | UINT64_C(1155564544), // SMLALT_ZZZI_D |
| 4765 | UINT64_C(1151370240), // SMLALT_ZZZI_S |
| 4766 | UINT64_C(1153451008), // SMLALT_ZZZ_D |
| 4767 | UINT64_C(1145062400), // SMLALT_ZZZ_H |
| 4768 | UINT64_C(1149256704), // SMLALT_ZZZ_S |
| 4769 | UINT64_C(3250589696), // SMLAL_MZZI_HtoS |
| 4770 | UINT64_C(3244297216), // SMLAL_MZZ_HtoS |
| 4771 | UINT64_C(3252684800), // SMLAL_VG2_M2Z2Z_HtoS |
| 4772 | UINT64_C(3251638272), // SMLAL_VG2_M2ZZI_S |
| 4773 | UINT64_C(3244296192), // SMLAL_VG2_M2ZZ_HtoS |
| 4774 | UINT64_C(3252750336), // SMLAL_VG4_M4Z4Z_HtoS |
| 4775 | UINT64_C(3251671040), // SMLAL_VG4_M4ZZI_HtoS |
| 4776 | UINT64_C(3245344768), // SMLAL_VG4_M4ZZ_HtoS |
| 4777 | UINT64_C(1310752768), // SMLALv16i8_v8i16 |
| 4778 | UINT64_C(260055040), // SMLALv2i32_indexed |
| 4779 | UINT64_C(245399552), // SMLALv2i32_v2i64 |
| 4780 | UINT64_C(255860736), // SMLALv4i16_indexed |
| 4781 | UINT64_C(241205248), // SMLALv4i16_v4i32 |
| 4782 | UINT64_C(1333796864), // SMLALv4i32_indexed |
| 4783 | UINT64_C(1319141376), // SMLALv4i32_v2i64 |
| 4784 | UINT64_C(1329602560), // SMLALv8i16_indexed |
| 4785 | UINT64_C(1314947072), // SMLALv8i16_v4i32 |
| 4786 | UINT64_C(237010944), // SMLALv8i8_v8i16 |
| 4787 | UINT64_C(1155571712), // SMLSLB_ZZZI_D |
| 4788 | UINT64_C(1151377408), // SMLSLB_ZZZI_S |
| 4789 | UINT64_C(1153454080), // SMLSLB_ZZZ_D |
| 4790 | UINT64_C(1145065472), // SMLSLB_ZZZ_H |
| 4791 | UINT64_C(1149259776), // SMLSLB_ZZZ_S |
| 4792 | UINT64_C(3238002696), // SMLSLL_MZZI_BtoS |
| 4793 | UINT64_C(3246391304), // SMLSLL_MZZI_HtoD |
| 4794 | UINT64_C(3240100872), // SMLSLL_MZZ_BtoS |
| 4795 | UINT64_C(3244295176), // SMLSLL_MZZ_HtoD |
| 4796 | UINT64_C(3248488456), // SMLSLL_VG2_M2Z2Z_BtoS |
| 4797 | UINT64_C(3252682760), // SMLSLL_VG2_M2Z2Z_HtoD |
| 4798 | UINT64_C(3239051272), // SMLSLL_VG2_M2ZZI_BtoS |
| 4799 | UINT64_C(3247439880), // SMLSLL_VG2_M2ZZI_HtoD |
| 4800 | UINT64_C(3240099848), // SMLSLL_VG2_M2ZZ_BtoS |
| 4801 | UINT64_C(3244294152), // SMLSLL_VG2_M2ZZ_HtoD |
| 4802 | UINT64_C(3248553992), // SMLSLL_VG4_M4Z4Z_BtoS |
| 4803 | UINT64_C(3252748296), // SMLSLL_VG4_M4Z4Z_HtoD |
| 4804 | UINT64_C(3239084040), // SMLSLL_VG4_M4ZZI_BtoS |
| 4805 | UINT64_C(3247472648), // SMLSLL_VG4_M4ZZI_HtoD |
| 4806 | UINT64_C(3241148424), // SMLSLL_VG4_M4ZZ_BtoS |
| 4807 | UINT64_C(3245342728), // SMLSLL_VG4_M4ZZ_HtoD |
| 4808 | UINT64_C(1155572736), // SMLSLT_ZZZI_D |
| 4809 | UINT64_C(1151378432), // SMLSLT_ZZZI_S |
| 4810 | UINT64_C(1153455104), // SMLSLT_ZZZ_D |
| 4811 | UINT64_C(1145066496), // SMLSLT_ZZZ_H |
| 4812 | UINT64_C(1149260800), // SMLSLT_ZZZ_S |
| 4813 | UINT64_C(3250589704), // SMLSL_MZZI_HtoS |
| 4814 | UINT64_C(3244297224), // SMLSL_MZZ_HtoS |
| 4815 | UINT64_C(3252684808), // SMLSL_VG2_M2Z2Z_HtoS |
| 4816 | UINT64_C(3251638280), // SMLSL_VG2_M2ZZI_S |
| 4817 | UINT64_C(3244296200), // SMLSL_VG2_M2ZZ_HtoS |
| 4818 | UINT64_C(3252750344), // SMLSL_VG4_M4Z4Z_HtoS |
| 4819 | UINT64_C(3251671048), // SMLSL_VG4_M4ZZI_HtoS |
| 4820 | UINT64_C(3245344776), // SMLSL_VG4_M4ZZ_HtoS |
| 4821 | UINT64_C(1310760960), // SMLSLv16i8_v8i16 |
| 4822 | UINT64_C(260071424), // SMLSLv2i32_indexed |
| 4823 | UINT64_C(245407744), // SMLSLv2i32_v2i64 |
| 4824 | UINT64_C(255877120), // SMLSLv4i16_indexed |
| 4825 | UINT64_C(241213440), // SMLSLv4i16_v4i32 |
| 4826 | UINT64_C(1333813248), // SMLSLv4i32_indexed |
| 4827 | UINT64_C(1319149568), // SMLSLv4i32_v2i64 |
| 4828 | UINT64_C(1329618944), // SMLSLv8i16_indexed |
| 4829 | UINT64_C(1314955264), // SMLSLv8i16_v4i32 |
| 4830 | UINT64_C(237019136), // SMLSLv8i8_v8i16 |
| 4831 | UINT64_C(1317053440), // SMMLA |
| 4832 | UINT64_C(1157666816), // SMMLA_ZZZ |
| 4833 | UINT64_C(2148565504), // SMOP4A_M2Z2Z_BToS |
| 4834 | UINT64_C(2148565512), // SMOP4A_M2Z2Z_HToS |
| 4835 | UINT64_C(2697986568), // SMOP4A_M2Z2Z_HtoD |
| 4836 | UINT64_C(2147516928), // SMOP4A_M2ZZ_BToS |
| 4837 | UINT64_C(2147516936), // SMOP4A_M2ZZ_HToS |
| 4838 | UINT64_C(2696937992), // SMOP4A_M2ZZ_HtoD |
| 4839 | UINT64_C(2148564992), // SMOP4A_MZ2Z_BToS |
| 4840 | UINT64_C(2148565000), // SMOP4A_MZ2Z_HToS |
| 4841 | UINT64_C(2697986056), // SMOP4A_MZ2Z_HtoD |
| 4842 | UINT64_C(2147516416), // SMOP4A_MZZ_BToS |
| 4843 | UINT64_C(2147516424), // SMOP4A_MZZ_HToS |
| 4844 | UINT64_C(2696937480), // SMOP4A_MZZ_HtoD |
| 4845 | UINT64_C(2148565520), // SMOP4S_M2Z2Z_BToS |
| 4846 | UINT64_C(2148565528), // SMOP4S_M2Z2Z_HToS |
| 4847 | UINT64_C(2697986584), // SMOP4S_M2Z2Z_HtoD |
| 4848 | UINT64_C(2147516944), // SMOP4S_M2ZZ_BToS |
| 4849 | UINT64_C(2147516952), // SMOP4S_M2ZZ_HToS |
| 4850 | UINT64_C(2696938008), // SMOP4S_M2ZZ_HtoD |
| 4851 | UINT64_C(2148565008), // SMOP4S_MZ2Z_BToS |
| 4852 | UINT64_C(2148565016), // SMOP4S_MZ2Z_HToS |
| 4853 | UINT64_C(2697986072), // SMOP4S_MZ2Z_HtoD |
| 4854 | UINT64_C(2147516432), // SMOP4S_MZZ_BToS |
| 4855 | UINT64_C(2147516440), // SMOP4S_MZZ_HToS |
| 4856 | UINT64_C(2696937496), // SMOP4S_MZZ_HtoD |
| 4857 | UINT64_C(2696937472), // SMOPA_MPPZZ_D |
| 4858 | UINT64_C(2692743176), // SMOPA_MPPZZ_HtoS |
| 4859 | UINT64_C(2692743168), // SMOPA_MPPZZ_S |
| 4860 | UINT64_C(2696937488), // SMOPS_MPPZZ_D |
| 4861 | UINT64_C(2692743192), // SMOPS_MPPZZ_HtoS |
| 4862 | UINT64_C(2692743184), // SMOPS_MPPZZ_S |
| 4863 | UINT64_C(235023360), // SMOVvi16to32 |
| 4864 | UINT64_C(235023360), // SMOVvi16to32_idx0 |
| 4865 | UINT64_C(1308765184), // SMOVvi16to64 |
| 4866 | UINT64_C(1308765184), // SMOVvi16to64_idx0 |
| 4867 | UINT64_C(1308896256), // SMOVvi32to64 |
| 4868 | UINT64_C(1308896256), // SMOVvi32to64_idx0 |
| 4869 | UINT64_C(234957824), // SMOVvi8to32 |
| 4870 | UINT64_C(234957824), // SMOVvi8to32_idx0 |
| 4871 | UINT64_C(1308699648), // SMOVvi8to64 |
| 4872 | UINT64_C(1308699648), // SMOVvi8to64_idx0 |
| 4873 | UINT64_C(2602598400), // SMSUBLrrr |
| 4874 | UINT64_C(68288512), // SMULH_ZPmZ_B |
| 4875 | UINT64_C(80871424), // SMULH_ZPmZ_D |
| 4876 | UINT64_C(72482816), // SMULH_ZPmZ_H |
| 4877 | UINT64_C(76677120), // SMULH_ZPmZ_S |
| 4878 | UINT64_C(69232640), // SMULH_ZZZ_B |
| 4879 | UINT64_C(81815552), // SMULH_ZZZ_D |
| 4880 | UINT64_C(73426944), // SMULH_ZZZ_H |
| 4881 | UINT64_C(77621248), // SMULH_ZZZ_S |
| 4882 | UINT64_C(2604694528), // SMULHrr |
| 4883 | UINT64_C(1155579904), // SMULLB_ZZZI_D |
| 4884 | UINT64_C(1151385600), // SMULLB_ZZZI_S |
| 4885 | UINT64_C(1170239488), // SMULLB_ZZZ_D |
| 4886 | UINT64_C(1161850880), // SMULLB_ZZZ_H |
| 4887 | UINT64_C(1166045184), // SMULLB_ZZZ_S |
| 4888 | UINT64_C(1155580928), // SMULLT_ZZZI_D |
| 4889 | UINT64_C(1151386624), // SMULLT_ZZZI_S |
| 4890 | UINT64_C(1170240512), // SMULLT_ZZZ_D |
| 4891 | UINT64_C(1161851904), // SMULLT_ZZZ_H |
| 4892 | UINT64_C(1166046208), // SMULLT_ZZZ_S |
| 4893 | UINT64_C(1310769152), // SMULLv16i8_v8i16 |
| 4894 | UINT64_C(260087808), // SMULLv2i32_indexed |
| 4895 | UINT64_C(245415936), // SMULLv2i32_v2i64 |
| 4896 | UINT64_C(255893504), // SMULLv4i16_indexed |
| 4897 | UINT64_C(241221632), // SMULLv4i16_v4i32 |
| 4898 | UINT64_C(1333829632), // SMULLv4i32_indexed |
| 4899 | UINT64_C(1319157760), // SMULLv4i32_v2i64 |
| 4900 | UINT64_C(1329635328), // SMULLv8i16_indexed |
| 4901 | UINT64_C(1314963456), // SMULLv8i16_v4i32 |
| 4902 | UINT64_C(237027328), // SMULLv8i8_v8i16 |
| 4903 | UINT64_C(86867968), // SPLICE_ZPZZ_B |
| 4904 | UINT64_C(99450880), // SPLICE_ZPZZ_D |
| 4905 | UINT64_C(91062272), // SPLICE_ZPZZ_H |
| 4906 | UINT64_C(95256576), // SPLICE_ZPZZ_S |
| 4907 | UINT64_C(86802432), // SPLICE_ZPZ_B |
| 4908 | UINT64_C(99385344), // SPLICE_ZPZ_D |
| 4909 | UINT64_C(90996736), // SPLICE_ZPZ_H |
| 4910 | UINT64_C(95191040), // SPLICE_ZPZ_S |
| 4911 | UINT64_C(1141415936), // SQABS_ZPmZ_B |
| 4912 | UINT64_C(1153998848), // SQABS_ZPmZ_D |
| 4913 | UINT64_C(1145610240), // SQABS_ZPmZ_H |
| 4914 | UINT64_C(1149804544), // SQABS_ZPmZ_S |
| 4915 | UINT64_C(1141547008), // SQABS_ZPzZ_B |
| 4916 | UINT64_C(1154129920), // SQABS_ZPzZ_D |
| 4917 | UINT64_C(1145741312), // SQABS_ZPzZ_H |
| 4918 | UINT64_C(1149935616), // SQABS_ZPzZ_S |
| 4919 | UINT64_C(1310750720), // SQABSv16i8 |
| 4920 | UINT64_C(1583380480), // SQABSv1i16 |
| 4921 | UINT64_C(1587574784), // SQABSv1i32 |
| 4922 | UINT64_C(1591769088), // SQABSv1i64 |
| 4923 | UINT64_C(1579186176), // SQABSv1i8 |
| 4924 | UINT64_C(245397504), // SQABSv2i32 |
| 4925 | UINT64_C(1323333632), // SQABSv2i64 |
| 4926 | UINT64_C(241203200), // SQABSv4i16 |
| 4927 | UINT64_C(1319139328), // SQABSv4i32 |
| 4928 | UINT64_C(1314945024), // SQABSv8i16 |
| 4929 | UINT64_C(237008896), // SQABSv8i8 |
| 4930 | UINT64_C(623165440), // SQADD_ZI_B |
| 4931 | UINT64_C(635748352), // SQADD_ZI_D |
| 4932 | UINT64_C(627359744), // SQADD_ZI_H |
| 4933 | UINT64_C(631554048), // SQADD_ZI_S |
| 4934 | UINT64_C(1142456320), // SQADD_ZPmZ_B |
| 4935 | UINT64_C(1155039232), // SQADD_ZPmZ_D |
| 4936 | UINT64_C(1146650624), // SQADD_ZPmZ_H |
| 4937 | UINT64_C(1150844928), // SQADD_ZPmZ_S |
| 4938 | UINT64_C(69210112), // SQADD_ZZZ_B |
| 4939 | UINT64_C(81793024), // SQADD_ZZZ_D |
| 4940 | UINT64_C(73404416), // SQADD_ZZZ_H |
| 4941 | UINT64_C(77598720), // SQADD_ZZZ_S |
| 4942 | UINT64_C(1310723072), // SQADDv16i8 |
| 4943 | UINT64_C(1583352832), // SQADDv1i16 |
| 4944 | UINT64_C(1587547136), // SQADDv1i32 |
| 4945 | UINT64_C(1591741440), // SQADDv1i64 |
| 4946 | UINT64_C(1579158528), // SQADDv1i8 |
| 4947 | UINT64_C(245369856), // SQADDv2i32 |
| 4948 | UINT64_C(1323305984), // SQADDv2i64 |
| 4949 | UINT64_C(241175552), // SQADDv4i16 |
| 4950 | UINT64_C(1319111680), // SQADDv4i32 |
| 4951 | UINT64_C(1314917376), // SQADDv8i16 |
| 4952 | UINT64_C(236981248), // SQADDv8i8 |
| 4953 | UINT64_C(1157748736), // SQCADD_ZZI_B |
| 4954 | UINT64_C(1170331648), // SQCADD_ZZI_D |
| 4955 | UINT64_C(1161943040), // SQCADD_ZZI_H |
| 4956 | UINT64_C(1166137344), // SQCADD_ZZI_S |
| 4957 | UINT64_C(1160855552), // SQCVTN_Z2Z_StoH |
| 4958 | UINT64_C(3249791040), // SQCVTN_Z4Z_DtoH |
| 4959 | UINT64_C(3241402432), // SQCVTN_Z4Z_StoB |
| 4960 | UINT64_C(1160859648), // SQCVTUN_Z2Z_StoH |
| 4961 | UINT64_C(3253985344), // SQCVTUN_Z4Z_DtoH |
| 4962 | UINT64_C(3245596736), // SQCVTUN_Z4Z_StoB |
| 4963 | UINT64_C(3244548096), // SQCVTU_Z2Z_StoH |
| 4964 | UINT64_C(3253985280), // SQCVTU_Z4Z_DtoH |
| 4965 | UINT64_C(3245596672), // SQCVTU_Z4Z_StoB |
| 4966 | UINT64_C(3240353792), // SQCVT_Z2Z_StoH |
| 4967 | UINT64_C(3249790976), // SQCVT_Z4Z_DtoH |
| 4968 | UINT64_C(3241402368), // SQCVT_Z4Z_StoB |
| 4969 | UINT64_C(70318080), // SQDECB_XPiI |
| 4970 | UINT64_C(69269504), // SQDECB_XPiWdI |
| 4971 | UINT64_C(82900992), // SQDECD_XPiI |
| 4972 | UINT64_C(81852416), // SQDECD_XPiWdI |
| 4973 | UINT64_C(81840128), // SQDECD_ZPiI |
| 4974 | UINT64_C(74512384), // SQDECH_XPiI |
| 4975 | UINT64_C(73463808), // SQDECH_XPiWdI |
| 4976 | UINT64_C(73451520), // SQDECH_ZPiI |
| 4977 | UINT64_C(623544320), // SQDECP_XPWd_B |
| 4978 | UINT64_C(636127232), // SQDECP_XPWd_D |
| 4979 | UINT64_C(627738624), // SQDECP_XPWd_H |
| 4980 | UINT64_C(631932928), // SQDECP_XPWd_S |
| 4981 | UINT64_C(623545344), // SQDECP_XP_B |
| 4982 | UINT64_C(636128256), // SQDECP_XP_D |
| 4983 | UINT64_C(627739648), // SQDECP_XP_H |
| 4984 | UINT64_C(631933952), // SQDECP_XP_S |
| 4985 | UINT64_C(636125184), // SQDECP_ZP_D |
| 4986 | UINT64_C(627736576), // SQDECP_ZP_H |
| 4987 | UINT64_C(631930880), // SQDECP_ZP_S |
| 4988 | UINT64_C(78706688), // SQDECW_XPiI |
| 4989 | UINT64_C(77658112), // SQDECW_XPiWdI |
| 4990 | UINT64_C(77645824), // SQDECW_ZPiI |
| 4991 | UINT64_C(1153435648), // SQDMLALBT_ZZZ_D |
| 4992 | UINT64_C(1145047040), // SQDMLALBT_ZZZ_H |
| 4993 | UINT64_C(1149241344), // SQDMLALBT_ZZZ_S |
| 4994 | UINT64_C(1155538944), // SQDMLALB_ZZZI_D |
| 4995 | UINT64_C(1151344640), // SQDMLALB_ZZZI_S |
| 4996 | UINT64_C(1153458176), // SQDMLALB_ZZZ_D |
| 4997 | UINT64_C(1145069568), // SQDMLALB_ZZZ_H |
| 4998 | UINT64_C(1149263872), // SQDMLALB_ZZZ_S |
| 4999 | UINT64_C(1155539968), // SQDMLALT_ZZZI_D |
| 5000 | UINT64_C(1151345664), // SQDMLALT_ZZZI_S |
| 5001 | UINT64_C(1153459200), // SQDMLALT_ZZZ_D |
| 5002 | UINT64_C(1145070592), // SQDMLALT_ZZZ_H |
| 5003 | UINT64_C(1149264896), // SQDMLALT_ZZZ_S |
| 5004 | UINT64_C(1583386624), // SQDMLALi16 |
| 5005 | UINT64_C(1587580928), // SQDMLALi32 |
| 5006 | UINT64_C(1598042112), // SQDMLALv1i32_indexed |
| 5007 | UINT64_C(1602236416), // SQDMLALv1i64_indexed |
| 5008 | UINT64_C(260059136), // SQDMLALv2i32_indexed |
| 5009 | UINT64_C(245403648), // SQDMLALv2i32_v2i64 |
| 5010 | UINT64_C(255864832), // SQDMLALv4i16_indexed |
| 5011 | UINT64_C(241209344), // SQDMLALv4i16_v4i32 |
| 5012 | UINT64_C(1333800960), // SQDMLALv4i32_indexed |
| 5013 | UINT64_C(1319145472), // SQDMLALv4i32_v2i64 |
| 5014 | UINT64_C(1329606656), // SQDMLALv8i16_indexed |
| 5015 | UINT64_C(1314951168), // SQDMLALv8i16_v4i32 |
| 5016 | UINT64_C(1153436672), // SQDMLSLBT_ZZZ_D |
| 5017 | UINT64_C(1145048064), // SQDMLSLBT_ZZZ_H |
| 5018 | UINT64_C(1149242368), // SQDMLSLBT_ZZZ_S |
| 5019 | UINT64_C(1155543040), // SQDMLSLB_ZZZI_D |
| 5020 | UINT64_C(1151348736), // SQDMLSLB_ZZZI_S |
| 5021 | UINT64_C(1153460224), // SQDMLSLB_ZZZ_D |
| 5022 | UINT64_C(1145071616), // SQDMLSLB_ZZZ_H |
| 5023 | UINT64_C(1149265920), // SQDMLSLB_ZZZ_S |
| 5024 | UINT64_C(1155544064), // SQDMLSLT_ZZZI_D |
| 5025 | UINT64_C(1151349760), // SQDMLSLT_ZZZI_S |
| 5026 | UINT64_C(1153461248), // SQDMLSLT_ZZZ_D |
| 5027 | UINT64_C(1145072640), // SQDMLSLT_ZZZ_H |
| 5028 | UINT64_C(1149266944), // SQDMLSLT_ZZZ_S |
| 5029 | UINT64_C(1583394816), // SQDMLSLi16 |
| 5030 | UINT64_C(1587589120), // SQDMLSLi32 |
| 5031 | UINT64_C(1598058496), // SQDMLSLv1i32_indexed |
| 5032 | UINT64_C(1602252800), // SQDMLSLv1i64_indexed |
| 5033 | UINT64_C(260075520), // SQDMLSLv2i32_indexed |
| 5034 | UINT64_C(245411840), // SQDMLSLv2i32_v2i64 |
| 5035 | UINT64_C(255881216), // SQDMLSLv4i16_indexed |
| 5036 | UINT64_C(241217536), // SQDMLSLv4i16_v4i32 |
| 5037 | UINT64_C(1333817344), // SQDMLSLv4i32_indexed |
| 5038 | UINT64_C(1319153664), // SQDMLSLv4i32_v2i64 |
| 5039 | UINT64_C(1329623040), // SQDMLSLv8i16_indexed |
| 5040 | UINT64_C(1314959360), // SQDMLSLv8i16_v4i32 |
| 5041 | UINT64_C(3240145920), // SQDMULH_VG2_2Z2Z_B |
| 5042 | UINT64_C(3252728832), // SQDMULH_VG2_2Z2Z_D |
| 5043 | UINT64_C(3244340224), // SQDMULH_VG2_2Z2Z_H |
| 5044 | UINT64_C(3248534528), // SQDMULH_VG2_2Z2Z_S |
| 5045 | UINT64_C(3240141824), // SQDMULH_VG2_2ZZ_B |
| 5046 | UINT64_C(3252724736), // SQDMULH_VG2_2ZZ_D |
| 5047 | UINT64_C(3244336128), // SQDMULH_VG2_2ZZ_H |
| 5048 | UINT64_C(3248530432), // SQDMULH_VG2_2ZZ_S |
| 5049 | UINT64_C(3240147968), // SQDMULH_VG4_4Z4Z_B |
| 5050 | UINT64_C(3252730880), // SQDMULH_VG4_4Z4Z_D |
| 5051 | UINT64_C(3244342272), // SQDMULH_VG4_4Z4Z_H |
| 5052 | UINT64_C(3248536576), // SQDMULH_VG4_4Z4Z_S |
| 5053 | UINT64_C(3240143872), // SQDMULH_VG4_4ZZ_B |
| 5054 | UINT64_C(3252726784), // SQDMULH_VG4_4ZZ_D |
| 5055 | UINT64_C(3244338176), // SQDMULH_VG4_4ZZ_H |
| 5056 | UINT64_C(3248532480), // SQDMULH_VG4_4ZZ_S |
| 5057 | UINT64_C(1155592192), // SQDMULH_ZZZI_D |
| 5058 | UINT64_C(1143009280), // SQDMULH_ZZZI_H |
| 5059 | UINT64_C(1151397888), // SQDMULH_ZZZI_S |
| 5060 | UINT64_C(69234688), // SQDMULH_ZZZ_B |
| 5061 | UINT64_C(81817600), // SQDMULH_ZZZ_D |
| 5062 | UINT64_C(73428992), // SQDMULH_ZZZ_H |
| 5063 | UINT64_C(77623296), // SQDMULH_ZZZ_S |
| 5064 | UINT64_C(1583395840), // SQDMULHv1i16 |
| 5065 | UINT64_C(1598078976), // SQDMULHv1i16_indexed |
| 5066 | UINT64_C(1587590144), // SQDMULHv1i32 |
| 5067 | UINT64_C(1602273280), // SQDMULHv1i32_indexed |
| 5068 | UINT64_C(245412864), // SQDMULHv2i32 |
| 5069 | UINT64_C(260096000), // SQDMULHv2i32_indexed |
| 5070 | UINT64_C(241218560), // SQDMULHv4i16 |
| 5071 | UINT64_C(255901696), // SQDMULHv4i16_indexed |
| 5072 | UINT64_C(1319154688), // SQDMULHv4i32 |
| 5073 | UINT64_C(1333837824), // SQDMULHv4i32_indexed |
| 5074 | UINT64_C(1314960384), // SQDMULHv8i16 |
| 5075 | UINT64_C(1329643520), // SQDMULHv8i16_indexed |
| 5076 | UINT64_C(1155588096), // SQDMULLB_ZZZI_D |
| 5077 | UINT64_C(1151393792), // SQDMULLB_ZZZI_S |
| 5078 | UINT64_C(1170235392), // SQDMULLB_ZZZ_D |
| 5079 | UINT64_C(1161846784), // SQDMULLB_ZZZ_H |
| 5080 | UINT64_C(1166041088), // SQDMULLB_ZZZ_S |
| 5081 | UINT64_C(1155589120), // SQDMULLT_ZZZI_D |
| 5082 | UINT64_C(1151394816), // SQDMULLT_ZZZI_S |
| 5083 | UINT64_C(1170236416), // SQDMULLT_ZZZ_D |
| 5084 | UINT64_C(1161847808), // SQDMULLT_ZZZ_H |
| 5085 | UINT64_C(1166042112), // SQDMULLT_ZZZ_S |
| 5086 | UINT64_C(1583403008), // SQDMULLi16 |
| 5087 | UINT64_C(1587597312), // SQDMULLi32 |
| 5088 | UINT64_C(1598074880), // SQDMULLv1i32_indexed |
| 5089 | UINT64_C(1602269184), // SQDMULLv1i64_indexed |
| 5090 | UINT64_C(260091904), // SQDMULLv2i32_indexed |
| 5091 | UINT64_C(245420032), // SQDMULLv2i32_v2i64 |
| 5092 | UINT64_C(255897600), // SQDMULLv4i16_indexed |
| 5093 | UINT64_C(241225728), // SQDMULLv4i16_v4i32 |
| 5094 | UINT64_C(1333833728), // SQDMULLv4i32_indexed |
| 5095 | UINT64_C(1319161856), // SQDMULLv4i32_v2i64 |
| 5096 | UINT64_C(1329639424), // SQDMULLv8i16_indexed |
| 5097 | UINT64_C(1314967552), // SQDMULLv8i16_v4i32 |
| 5098 | UINT64_C(70316032), // SQINCB_XPiI |
| 5099 | UINT64_C(69267456), // SQINCB_XPiWdI |
| 5100 | UINT64_C(82898944), // SQINCD_XPiI |
| 5101 | UINT64_C(81850368), // SQINCD_XPiWdI |
| 5102 | UINT64_C(81838080), // SQINCD_ZPiI |
| 5103 | UINT64_C(74510336), // SQINCH_XPiI |
| 5104 | UINT64_C(73461760), // SQINCH_XPiWdI |
| 5105 | UINT64_C(73449472), // SQINCH_ZPiI |
| 5106 | UINT64_C(623413248), // SQINCP_XPWd_B |
| 5107 | UINT64_C(635996160), // SQINCP_XPWd_D |
| 5108 | UINT64_C(627607552), // SQINCP_XPWd_H |
| 5109 | UINT64_C(631801856), // SQINCP_XPWd_S |
| 5110 | UINT64_C(623414272), // SQINCP_XP_B |
| 5111 | UINT64_C(635997184), // SQINCP_XP_D |
| 5112 | UINT64_C(627608576), // SQINCP_XP_H |
| 5113 | UINT64_C(631802880), // SQINCP_XP_S |
| 5114 | UINT64_C(635994112), // SQINCP_ZP_D |
| 5115 | UINT64_C(627605504), // SQINCP_ZP_H |
| 5116 | UINT64_C(631799808), // SQINCP_ZP_S |
| 5117 | UINT64_C(78704640), // SQINCW_XPiI |
| 5118 | UINT64_C(77656064), // SQINCW_XPiWdI |
| 5119 | UINT64_C(77643776), // SQINCW_ZPiI |
| 5120 | UINT64_C(1141481472), // SQNEG_ZPmZ_B |
| 5121 | UINT64_C(1154064384), // SQNEG_ZPmZ_D |
| 5122 | UINT64_C(1145675776), // SQNEG_ZPmZ_H |
| 5123 | UINT64_C(1149870080), // SQNEG_ZPmZ_S |
| 5124 | UINT64_C(1141612544), // SQNEG_ZPzZ_B |
| 5125 | UINT64_C(1154195456), // SQNEG_ZPzZ_D |
| 5126 | UINT64_C(1145806848), // SQNEG_ZPzZ_H |
| 5127 | UINT64_C(1150001152), // SQNEG_ZPzZ_S |
| 5128 | UINT64_C(1847621632), // SQNEGv16i8 |
| 5129 | UINT64_C(2120251392), // SQNEGv1i16 |
| 5130 | UINT64_C(2124445696), // SQNEGv1i32 |
| 5131 | UINT64_C(2128640000), // SQNEGv1i64 |
| 5132 | UINT64_C(2116057088), // SQNEGv1i8 |
| 5133 | UINT64_C(782268416), // SQNEGv2i32 |
| 5134 | UINT64_C(1860204544), // SQNEGv2i64 |
| 5135 | UINT64_C(778074112), // SQNEGv4i16 |
| 5136 | UINT64_C(1856010240), // SQNEGv4i32 |
| 5137 | UINT64_C(1851815936), // SQNEGv8i16 |
| 5138 | UINT64_C(773879808), // SQNEGv8i8 |
| 5139 | UINT64_C(1151365120), // SQRDCMLAH_ZZZI_H |
| 5140 | UINT64_C(1155559424), // SQRDCMLAH_ZZZI_S |
| 5141 | UINT64_C(1140862976), // SQRDCMLAH_ZZZ_B |
| 5142 | UINT64_C(1153445888), // SQRDCMLAH_ZZZ_D |
| 5143 | UINT64_C(1145057280), // SQRDCMLAH_ZZZ_H |
| 5144 | UINT64_C(1149251584), // SQRDCMLAH_ZZZ_S |
| 5145 | UINT64_C(1155534848), // SQRDMLAH_ZZZI_D |
| 5146 | UINT64_C(1142951936), // SQRDMLAH_ZZZI_H |
| 5147 | UINT64_C(1151340544), // SQRDMLAH_ZZZI_S |
| 5148 | UINT64_C(1140879360), // SQRDMLAH_ZZZ_B |
| 5149 | UINT64_C(1153462272), // SQRDMLAH_ZZZ_D |
| 5150 | UINT64_C(1145073664), // SQRDMLAH_ZZZ_H |
| 5151 | UINT64_C(1149267968), // SQRDMLAH_ZZZ_S |
| 5152 | UINT64_C(2118157312), // SQRDMLAHv1i16 |
| 5153 | UINT64_C(2134953984), // SQRDMLAHv1i16_indexed |
| 5154 | UINT64_C(2122351616), // SQRDMLAHv1i32 |
| 5155 | UINT64_C(2139148288), // SQRDMLAHv1i32_indexed |
| 5156 | UINT64_C(780174336), // SQRDMLAHv2i32 |
| 5157 | UINT64_C(796971008), // SQRDMLAHv2i32_indexed |
| 5158 | UINT64_C(775980032), // SQRDMLAHv4i16 |
| 5159 | UINT64_C(792776704), // SQRDMLAHv4i16_indexed |
| 5160 | UINT64_C(1853916160), // SQRDMLAHv4i32 |
| 5161 | UINT64_C(1870712832), // SQRDMLAHv4i32_indexed |
| 5162 | UINT64_C(1849721856), // SQRDMLAHv8i16 |
| 5163 | UINT64_C(1866518528), // SQRDMLAHv8i16_indexed |
| 5164 | UINT64_C(1155535872), // SQRDMLSH_ZZZI_D |
| 5165 | UINT64_C(1142952960), // SQRDMLSH_ZZZI_H |
| 5166 | UINT64_C(1151341568), // SQRDMLSH_ZZZI_S |
| 5167 | UINT64_C(1140880384), // SQRDMLSH_ZZZ_B |
| 5168 | UINT64_C(1153463296), // SQRDMLSH_ZZZ_D |
| 5169 | UINT64_C(1145074688), // SQRDMLSH_ZZZ_H |
| 5170 | UINT64_C(1149268992), // SQRDMLSH_ZZZ_S |
| 5171 | UINT64_C(2118159360), // SQRDMLSHv1i16 |
| 5172 | UINT64_C(2134962176), // SQRDMLSHv1i16_indexed |
| 5173 | UINT64_C(2122353664), // SQRDMLSHv1i32 |
| 5174 | UINT64_C(2139156480), // SQRDMLSHv1i32_indexed |
| 5175 | UINT64_C(780176384), // SQRDMLSHv2i32 |
| 5176 | UINT64_C(796979200), // SQRDMLSHv2i32_indexed |
| 5177 | UINT64_C(775982080), // SQRDMLSHv4i16 |
| 5178 | UINT64_C(792784896), // SQRDMLSHv4i16_indexed |
| 5179 | UINT64_C(1853918208), // SQRDMLSHv4i32 |
| 5180 | UINT64_C(1870721024), // SQRDMLSHv4i32_indexed |
| 5181 | UINT64_C(1849723904), // SQRDMLSHv8i16 |
| 5182 | UINT64_C(1866526720), // SQRDMLSHv8i16_indexed |
| 5183 | UINT64_C(1155593216), // SQRDMULH_ZZZI_D |
| 5184 | UINT64_C(1143010304), // SQRDMULH_ZZZI_H |
| 5185 | UINT64_C(1151398912), // SQRDMULH_ZZZI_S |
| 5186 | UINT64_C(69235712), // SQRDMULH_ZZZ_B |
| 5187 | UINT64_C(81818624), // SQRDMULH_ZZZ_D |
| 5188 | UINT64_C(73430016), // SQRDMULH_ZZZ_H |
| 5189 | UINT64_C(77624320), // SQRDMULH_ZZZ_S |
| 5190 | UINT64_C(2120266752), // SQRDMULHv1i16 |
| 5191 | UINT64_C(1598083072), // SQRDMULHv1i16_indexed |
| 5192 | UINT64_C(2124461056), // SQRDMULHv1i32 |
| 5193 | UINT64_C(1602277376), // SQRDMULHv1i32_indexed |
| 5194 | UINT64_C(782283776), // SQRDMULHv2i32 |
| 5195 | UINT64_C(260100096), // SQRDMULHv2i32_indexed |
| 5196 | UINT64_C(778089472), // SQRDMULHv4i16 |
| 5197 | UINT64_C(255905792), // SQRDMULHv4i16_indexed |
| 5198 | UINT64_C(1856025600), // SQRDMULHv4i32 |
| 5199 | UINT64_C(1333841920), // SQRDMULHv4i32_indexed |
| 5200 | UINT64_C(1851831296), // SQRDMULHv8i16 |
| 5201 | UINT64_C(1329647616), // SQRDMULHv8i16_indexed |
| 5202 | UINT64_C(1141800960), // SQRSHLR_ZPmZ_B |
| 5203 | UINT64_C(1154383872), // SQRSHLR_ZPmZ_D |
| 5204 | UINT64_C(1145995264), // SQRSHLR_ZPmZ_H |
| 5205 | UINT64_C(1150189568), // SQRSHLR_ZPmZ_S |
| 5206 | UINT64_C(1141538816), // SQRSHL_ZPmZ_B |
| 5207 | UINT64_C(1154121728), // SQRSHL_ZPmZ_D |
| 5208 | UINT64_C(1145733120), // SQRSHL_ZPmZ_H |
| 5209 | UINT64_C(1149927424), // SQRSHL_ZPmZ_S |
| 5210 | UINT64_C(1310743552), // SQRSHLv16i8 |
| 5211 | UINT64_C(1583373312), // SQRSHLv1i16 |
| 5212 | UINT64_C(1587567616), // SQRSHLv1i32 |
| 5213 | UINT64_C(1591761920), // SQRSHLv1i64 |
| 5214 | UINT64_C(1579179008), // SQRSHLv1i8 |
| 5215 | UINT64_C(245390336), // SQRSHLv2i32 |
| 5216 | UINT64_C(1323326464), // SQRSHLv2i64 |
| 5217 | UINT64_C(241196032), // SQRSHLv4i16 |
| 5218 | UINT64_C(1319132160), // SQRSHLv4i32 |
| 5219 | UINT64_C(1314937856), // SQRSHLv8i16 |
| 5220 | UINT64_C(237001728), // SQRSHLv8i8 |
| 5221 | UINT64_C(1160259584), // SQRSHRNB_ZZI_B |
| 5222 | UINT64_C(1160783872), // SQRSHRNB_ZZI_H |
| 5223 | UINT64_C(1163929600), // SQRSHRNB_ZZI_S |
| 5224 | UINT64_C(1160260608), // SQRSHRNT_ZZI_B |
| 5225 | UINT64_C(1160784896), // SQRSHRNT_ZZI_H |
| 5226 | UINT64_C(1163930624), // SQRSHRNT_ZZI_S |
| 5227 | UINT64_C(3244350464), // SQRSHRN_VG4_Z4ZI_B |
| 5228 | UINT64_C(3248544768), // SQRSHRN_VG4_Z4ZI_H |
| 5229 | UINT64_C(1168648192), // SQRSHRN_Z2ZI_HtoB |
| 5230 | UINT64_C(1169172480), // SQRSHRN_Z2ZI_StoH |
| 5231 | UINT64_C(1594399744), // SQRSHRNb |
| 5232 | UINT64_C(1594924032), // SQRSHRNh |
| 5233 | UINT64_C(1595972608), // SQRSHRNs |
| 5234 | UINT64_C(1325964288), // SQRSHRNv16i8_shift |
| 5235 | UINT64_C(253795328), // SQRSHRNv2i32_shift |
| 5236 | UINT64_C(252746752), // SQRSHRNv4i16_shift |
| 5237 | UINT64_C(1327537152), // SQRSHRNv4i32_shift |
| 5238 | UINT64_C(1326488576), // SQRSHRNv8i16_shift |
| 5239 | UINT64_C(252222464), // SQRSHRNv8i8_shift |
| 5240 | UINT64_C(1160251392), // SQRSHRUNB_ZZI_B |
| 5241 | UINT64_C(1160775680), // SQRSHRUNB_ZZI_H |
| 5242 | UINT64_C(1163921408), // SQRSHRUNB_ZZI_S |
| 5243 | UINT64_C(1160252416), // SQRSHRUNT_ZZI_B |
| 5244 | UINT64_C(1160776704), // SQRSHRUNT_ZZI_H |
| 5245 | UINT64_C(1163922432), // SQRSHRUNT_ZZI_S |
| 5246 | UINT64_C(3244350528), // SQRSHRUN_VG4_Z4ZI_B |
| 5247 | UINT64_C(3248544832), // SQRSHRUN_VG4_Z4ZI_H |
| 5248 | UINT64_C(1168640000), // SQRSHRUN_Z2ZI_HtoB |
| 5249 | UINT64_C(1169164288), // SQRSHRUN_Z2ZI_StoH |
| 5250 | UINT64_C(2131266560), // SQRSHRUNb |
| 5251 | UINT64_C(2131790848), // SQRSHRUNh |
| 5252 | UINT64_C(2132839424), // SQRSHRUNs |
| 5253 | UINT64_C(1862831104), // SQRSHRUNv16i8_shift |
| 5254 | UINT64_C(790662144), // SQRSHRUNv2i32_shift |
| 5255 | UINT64_C(789613568), // SQRSHRUNv4i16_shift |
| 5256 | UINT64_C(1864403968), // SQRSHRUNv4i32_shift |
| 5257 | UINT64_C(1863355392), // SQRSHRUNv8i16_shift |
| 5258 | UINT64_C(789089280), // SQRSHRUNv8i8_shift |
| 5259 | UINT64_C(3253785600), // SQRSHRU_VG2_Z2ZI_H |
| 5260 | UINT64_C(3244349504), // SQRSHRU_VG4_Z4ZI_B |
| 5261 | UINT64_C(3248543808), // SQRSHRU_VG4_Z4ZI_H |
| 5262 | UINT64_C(3252737024), // SQRSHR_VG2_Z2ZI_H |
| 5263 | UINT64_C(3244349440), // SQRSHR_VG4_Z4ZI_B |
| 5264 | UINT64_C(3248543744), // SQRSHR_VG4_Z4ZI_H |
| 5265 | UINT64_C(1141669888), // SQSHLR_ZPmZ_B |
| 5266 | UINT64_C(1154252800), // SQSHLR_ZPmZ_D |
| 5267 | UINT64_C(1145864192), // SQSHLR_ZPmZ_H |
| 5268 | UINT64_C(1150058496), // SQSHLR_ZPmZ_S |
| 5269 | UINT64_C(68124928), // SQSHLU_ZPmI_B |
| 5270 | UINT64_C(76513280), // SQSHLU_ZPmI_D |
| 5271 | UINT64_C(68125184), // SQSHLU_ZPmI_H |
| 5272 | UINT64_C(72318976), // SQSHLU_ZPmI_S |
| 5273 | UINT64_C(2131256320), // SQSHLUb |
| 5274 | UINT64_C(2134926336), // SQSHLUd |
| 5275 | UINT64_C(2131780608), // SQSHLUh |
| 5276 | UINT64_C(2132829184), // SQSHLUs |
| 5277 | UINT64_C(1862820864), // SQSHLUv16i8_shift |
| 5278 | UINT64_C(790651904), // SQSHLUv2i32_shift |
| 5279 | UINT64_C(1866490880), // SQSHLUv2i64_shift |
| 5280 | UINT64_C(789603328), // SQSHLUv4i16_shift |
| 5281 | UINT64_C(1864393728), // SQSHLUv4i32_shift |
| 5282 | UINT64_C(1863345152), // SQSHLUv8i16_shift |
| 5283 | UINT64_C(789079040), // SQSHLUv8i8_shift |
| 5284 | UINT64_C(67535104), // SQSHL_ZPmI_B |
| 5285 | UINT64_C(75923456), // SQSHL_ZPmI_D |
| 5286 | UINT64_C(67535360), // SQSHL_ZPmI_H |
| 5287 | UINT64_C(71729152), // SQSHL_ZPmI_S |
| 5288 | UINT64_C(1141407744), // SQSHL_ZPmZ_B |
| 5289 | UINT64_C(1153990656), // SQSHL_ZPmZ_D |
| 5290 | UINT64_C(1145602048), // SQSHL_ZPmZ_H |
| 5291 | UINT64_C(1149796352), // SQSHL_ZPmZ_S |
| 5292 | UINT64_C(1594389504), // SQSHLb |
| 5293 | UINT64_C(1598059520), // SQSHLd |
| 5294 | UINT64_C(1594913792), // SQSHLh |
| 5295 | UINT64_C(1595962368), // SQSHLs |
| 5296 | UINT64_C(1310739456), // SQSHLv16i8 |
| 5297 | UINT64_C(1325954048), // SQSHLv16i8_shift |
| 5298 | UINT64_C(1583369216), // SQSHLv1i16 |
| 5299 | UINT64_C(1587563520), // SQSHLv1i32 |
| 5300 | UINT64_C(1591757824), // SQSHLv1i64 |
| 5301 | UINT64_C(1579174912), // SQSHLv1i8 |
| 5302 | UINT64_C(245386240), // SQSHLv2i32 |
| 5303 | UINT64_C(253785088), // SQSHLv2i32_shift |
| 5304 | UINT64_C(1323322368), // SQSHLv2i64 |
| 5305 | UINT64_C(1329624064), // SQSHLv2i64_shift |
| 5306 | UINT64_C(241191936), // SQSHLv4i16 |
| 5307 | UINT64_C(252736512), // SQSHLv4i16_shift |
| 5308 | UINT64_C(1319128064), // SQSHLv4i32 |
| 5309 | UINT64_C(1327526912), // SQSHLv4i32_shift |
| 5310 | UINT64_C(1314933760), // SQSHLv8i16 |
| 5311 | UINT64_C(1326478336), // SQSHLv8i16_shift |
| 5312 | UINT64_C(236997632), // SQSHLv8i8 |
| 5313 | UINT64_C(252212224), // SQSHLv8i8_shift |
| 5314 | UINT64_C(1160257536), // SQSHRNB_ZZI_B |
| 5315 | UINT64_C(1160781824), // SQSHRNB_ZZI_H |
| 5316 | UINT64_C(1163927552), // SQSHRNB_ZZI_S |
| 5317 | UINT64_C(1160258560), // SQSHRNT_ZZI_B |
| 5318 | UINT64_C(1160782848), // SQSHRNT_ZZI_H |
| 5319 | UINT64_C(1163928576), // SQSHRNT_ZZI_S |
| 5320 | UINT64_C(1168637952), // SQSHRN_Z2ZI_HtoB |
| 5321 | UINT64_C(1169162240), // SQSHRN_Z2ZI_StoH |
| 5322 | UINT64_C(1594397696), // SQSHRNb |
| 5323 | UINT64_C(1594921984), // SQSHRNh |
| 5324 | UINT64_C(1595970560), // SQSHRNs |
| 5325 | UINT64_C(1325962240), // SQSHRNv16i8_shift |
| 5326 | UINT64_C(253793280), // SQSHRNv2i32_shift |
| 5327 | UINT64_C(252744704), // SQSHRNv4i16_shift |
| 5328 | UINT64_C(1327535104), // SQSHRNv4i32_shift |
| 5329 | UINT64_C(1326486528), // SQSHRNv8i16_shift |
| 5330 | UINT64_C(252220416), // SQSHRNv8i8_shift |
| 5331 | UINT64_C(1160249344), // SQSHRUNB_ZZI_B |
| 5332 | UINT64_C(1160773632), // SQSHRUNB_ZZI_H |
| 5333 | UINT64_C(1163919360), // SQSHRUNB_ZZI_S |
| 5334 | UINT64_C(1160250368), // SQSHRUNT_ZZI_B |
| 5335 | UINT64_C(1160774656), // SQSHRUNT_ZZI_H |
| 5336 | UINT64_C(1163920384), // SQSHRUNT_ZZI_S |
| 5337 | UINT64_C(1168646144), // SQSHRUN_Z2ZI_HtoB |
| 5338 | UINT64_C(1169170432), // SQSHRUN_Z2ZI_StoH |
| 5339 | UINT64_C(2131264512), // SQSHRUNb |
| 5340 | UINT64_C(2131788800), // SQSHRUNh |
| 5341 | UINT64_C(2132837376), // SQSHRUNs |
| 5342 | UINT64_C(1862829056), // SQSHRUNv16i8_shift |
| 5343 | UINT64_C(790660096), // SQSHRUNv2i32_shift |
| 5344 | UINT64_C(789611520), // SQSHRUNv4i16_shift |
| 5345 | UINT64_C(1864401920), // SQSHRUNv4i32_shift |
| 5346 | UINT64_C(1863353344), // SQSHRUNv8i16_shift |
| 5347 | UINT64_C(789087232), // SQSHRUNv8i8_shift |
| 5348 | UINT64_C(1142849536), // SQSUBR_ZPmZ_B |
| 5349 | UINT64_C(1155432448), // SQSUBR_ZPmZ_D |
| 5350 | UINT64_C(1147043840), // SQSUBR_ZPmZ_H |
| 5351 | UINT64_C(1151238144), // SQSUBR_ZPmZ_S |
| 5352 | UINT64_C(623296512), // SQSUB_ZI_B |
| 5353 | UINT64_C(635879424), // SQSUB_ZI_D |
| 5354 | UINT64_C(627490816), // SQSUB_ZI_H |
| 5355 | UINT64_C(631685120), // SQSUB_ZI_S |
| 5356 | UINT64_C(1142587392), // SQSUB_ZPmZ_B |
| 5357 | UINT64_C(1155170304), // SQSUB_ZPmZ_D |
| 5358 | UINT64_C(1146781696), // SQSUB_ZPmZ_H |
| 5359 | UINT64_C(1150976000), // SQSUB_ZPmZ_S |
| 5360 | UINT64_C(69212160), // SQSUB_ZZZ_B |
| 5361 | UINT64_C(81795072), // SQSUB_ZZZ_D |
| 5362 | UINT64_C(73406464), // SQSUB_ZZZ_H |
| 5363 | UINT64_C(77600768), // SQSUB_ZZZ_S |
| 5364 | UINT64_C(1310731264), // SQSUBv16i8 |
| 5365 | UINT64_C(1583361024), // SQSUBv1i16 |
| 5366 | UINT64_C(1587555328), // SQSUBv1i32 |
| 5367 | UINT64_C(1591749632), // SQSUBv1i64 |
| 5368 | UINT64_C(1579166720), // SQSUBv1i8 |
| 5369 | UINT64_C(245378048), // SQSUBv2i32 |
| 5370 | UINT64_C(1323314176), // SQSUBv2i64 |
| 5371 | UINT64_C(241183744), // SQSUBv4i16 |
| 5372 | UINT64_C(1319119872), // SQSUBv4i32 |
| 5373 | UINT64_C(1314925568), // SQSUBv8i16 |
| 5374 | UINT64_C(236989440), // SQSUBv8i8 |
| 5375 | UINT64_C(1160265728), // SQXTNB_ZZ_B |
| 5376 | UINT64_C(1160790016), // SQXTNB_ZZ_H |
| 5377 | UINT64_C(1163935744), // SQXTNB_ZZ_S |
| 5378 | UINT64_C(1160266752), // SQXTNT_ZZ_B |
| 5379 | UINT64_C(1160791040), // SQXTNT_ZZ_H |
| 5380 | UINT64_C(1163936768), // SQXTNT_ZZ_S |
| 5381 | UINT64_C(1310803968), // SQXTNv16i8 |
| 5382 | UINT64_C(1583433728), // SQXTNv1i16 |
| 5383 | UINT64_C(1587628032), // SQXTNv1i32 |
| 5384 | UINT64_C(1579239424), // SQXTNv1i8 |
| 5385 | UINT64_C(245450752), // SQXTNv2i32 |
| 5386 | UINT64_C(241256448), // SQXTNv4i16 |
| 5387 | UINT64_C(1319192576), // SQXTNv4i32 |
| 5388 | UINT64_C(1314998272), // SQXTNv8i16 |
| 5389 | UINT64_C(237062144), // SQXTNv8i8 |
| 5390 | UINT64_C(1160269824), // SQXTUNB_ZZ_B |
| 5391 | UINT64_C(1160794112), // SQXTUNB_ZZ_H |
| 5392 | UINT64_C(1163939840), // SQXTUNB_ZZ_S |
| 5393 | UINT64_C(1160270848), // SQXTUNT_ZZ_B |
| 5394 | UINT64_C(1160795136), // SQXTUNT_ZZ_H |
| 5395 | UINT64_C(1163940864), // SQXTUNT_ZZ_S |
| 5396 | UINT64_C(1847666688), // SQXTUNv16i8 |
| 5397 | UINT64_C(2120296448), // SQXTUNv1i16 |
| 5398 | UINT64_C(2124490752), // SQXTUNv1i32 |
| 5399 | UINT64_C(2116102144), // SQXTUNv1i8 |
| 5400 | UINT64_C(782313472), // SQXTUNv2i32 |
| 5401 | UINT64_C(778119168), // SQXTUNv4i16 |
| 5402 | UINT64_C(1856055296), // SQXTUNv4i32 |
| 5403 | UINT64_C(1851860992), // SQXTUNv8i16 |
| 5404 | UINT64_C(773924864), // SQXTUNv8i8 |
| 5405 | UINT64_C(1142194176), // SRHADD_ZPmZ_B |
| 5406 | UINT64_C(1154777088), // SRHADD_ZPmZ_D |
| 5407 | UINT64_C(1146388480), // SRHADD_ZPmZ_H |
| 5408 | UINT64_C(1150582784), // SRHADD_ZPmZ_S |
| 5409 | UINT64_C(1310725120), // SRHADDv16i8 |
| 5410 | UINT64_C(245371904), // SRHADDv2i32 |
| 5411 | UINT64_C(241177600), // SRHADDv4i16 |
| 5412 | UINT64_C(1319113728), // SRHADDv4i32 |
| 5413 | UINT64_C(1314919424), // SRHADDv8i16 |
| 5414 | UINT64_C(236983296), // SRHADDv8i8 |
| 5415 | UINT64_C(1158213632), // SRI_ZZI_B |
| 5416 | UINT64_C(1166077952), // SRI_ZZI_D |
| 5417 | UINT64_C(1158737920), // SRI_ZZI_H |
| 5418 | UINT64_C(1161883648), // SRI_ZZI_S |
| 5419 | UINT64_C(2134918144), // SRId |
| 5420 | UINT64_C(1862812672), // SRIv16i8_shift |
| 5421 | UINT64_C(790643712), // SRIv2i32_shift |
| 5422 | UINT64_C(1866482688), // SRIv2i64_shift |
| 5423 | UINT64_C(789595136), // SRIv4i16_shift |
| 5424 | UINT64_C(1864385536), // SRIv4i32_shift |
| 5425 | UINT64_C(1863336960), // SRIv8i16_shift |
| 5426 | UINT64_C(789070848), // SRIv8i8_shift |
| 5427 | UINT64_C(1141276672), // SRSHLR_ZPmZ_B |
| 5428 | UINT64_C(1153859584), // SRSHLR_ZPmZ_D |
| 5429 | UINT64_C(1145470976), // SRSHLR_ZPmZ_H |
| 5430 | UINT64_C(1149665280), // SRSHLR_ZPmZ_S |
| 5431 | UINT64_C(3240145440), // SRSHL_VG2_2Z2Z_B |
| 5432 | UINT64_C(3252728352), // SRSHL_VG2_2Z2Z_D |
| 5433 | UINT64_C(3244339744), // SRSHL_VG2_2Z2Z_H |
| 5434 | UINT64_C(3248534048), // SRSHL_VG2_2Z2Z_S |
| 5435 | UINT64_C(3240141344), // SRSHL_VG2_2ZZ_B |
| 5436 | UINT64_C(3252724256), // SRSHL_VG2_2ZZ_D |
| 5437 | UINT64_C(3244335648), // SRSHL_VG2_2ZZ_H |
| 5438 | UINT64_C(3248529952), // SRSHL_VG2_2ZZ_S |
| 5439 | UINT64_C(3240147488), // SRSHL_VG4_4Z4Z_B |
| 5440 | UINT64_C(3252730400), // SRSHL_VG4_4Z4Z_D |
| 5441 | UINT64_C(3244341792), // SRSHL_VG4_4Z4Z_H |
| 5442 | UINT64_C(3248536096), // SRSHL_VG4_4Z4Z_S |
| 5443 | UINT64_C(3240143392), // SRSHL_VG4_4ZZ_B |
| 5444 | UINT64_C(3252726304), // SRSHL_VG4_4ZZ_D |
| 5445 | UINT64_C(3244337696), // SRSHL_VG4_4ZZ_H |
| 5446 | UINT64_C(3248532000), // SRSHL_VG4_4ZZ_S |
| 5447 | UINT64_C(1141014528), // SRSHL_ZPmZ_B |
| 5448 | UINT64_C(1153597440), // SRSHL_ZPmZ_D |
| 5449 | UINT64_C(1145208832), // SRSHL_ZPmZ_H |
| 5450 | UINT64_C(1149403136), // SRSHL_ZPmZ_S |
| 5451 | UINT64_C(1310741504), // SRSHLv16i8 |
| 5452 | UINT64_C(1591759872), // SRSHLv1i64 |
| 5453 | UINT64_C(245388288), // SRSHLv2i32 |
| 5454 | UINT64_C(1323324416), // SRSHLv2i64 |
| 5455 | UINT64_C(241193984), // SRSHLv4i16 |
| 5456 | UINT64_C(1319130112), // SRSHLv4i32 |
| 5457 | UINT64_C(1314935808), // SRSHLv8i16 |
| 5458 | UINT64_C(236999680), // SRSHLv8i8 |
| 5459 | UINT64_C(67928320), // SRSHR_ZPmI_B |
| 5460 | UINT64_C(76316672), // SRSHR_ZPmI_D |
| 5461 | UINT64_C(67928576), // SRSHR_ZPmI_H |
| 5462 | UINT64_C(72122368), // SRSHR_ZPmI_S |
| 5463 | UINT64_C(1598039040), // SRSHRd |
| 5464 | UINT64_C(1325933568), // SRSHRv16i8_shift |
| 5465 | UINT64_C(253764608), // SRSHRv2i32_shift |
| 5466 | UINT64_C(1329603584), // SRSHRv2i64_shift |
| 5467 | UINT64_C(252716032), // SRSHRv4i16_shift |
| 5468 | UINT64_C(1327506432), // SRSHRv4i32_shift |
| 5469 | UINT64_C(1326457856), // SRSHRv8i16_shift |
| 5470 | UINT64_C(252191744), // SRSHRv8i8_shift |
| 5471 | UINT64_C(1158211584), // SRSRA_ZZI_B |
| 5472 | UINT64_C(1166075904), // SRSRA_ZZI_D |
| 5473 | UINT64_C(1158735872), // SRSRA_ZZI_H |
| 5474 | UINT64_C(1161881600), // SRSRA_ZZI_S |
| 5475 | UINT64_C(1598043136), // SRSRAd |
| 5476 | UINT64_C(1325937664), // SRSRAv16i8_shift |
| 5477 | UINT64_C(253768704), // SRSRAv2i32_shift |
| 5478 | UINT64_C(1329607680), // SRSRAv2i64_shift |
| 5479 | UINT64_C(252720128), // SRSRAv4i16_shift |
| 5480 | UINT64_C(1327510528), // SRSRAv4i32_shift |
| 5481 | UINT64_C(1326461952), // SRSRAv8i16_shift |
| 5482 | UINT64_C(252195840), // SRSRAv8i8_shift |
| 5483 | UINT64_C(1161863168), // SSHLLB_ZZI_D |
| 5484 | UINT64_C(1158193152), // SSHLLB_ZZI_H |
| 5485 | UINT64_C(1158717440), // SSHLLB_ZZI_S |
| 5486 | UINT64_C(1161864192), // SSHLLT_ZZI_D |
| 5487 | UINT64_C(1158194176), // SSHLLT_ZZI_H |
| 5488 | UINT64_C(1158718464), // SSHLLT_ZZI_S |
| 5489 | UINT64_C(1325966336), // SSHLLv16i8_shift |
| 5490 | UINT64_C(253797376), // SSHLLv2i32_shift |
| 5491 | UINT64_C(252748800), // SSHLLv4i16_shift |
| 5492 | UINT64_C(1327539200), // SSHLLv4i32_shift |
| 5493 | UINT64_C(1326490624), // SSHLLv8i16_shift |
| 5494 | UINT64_C(252224512), // SSHLLv8i8_shift |
| 5495 | UINT64_C(1310737408), // SSHLv16i8 |
| 5496 | UINT64_C(1591755776), // SSHLv1i64 |
| 5497 | UINT64_C(245384192), // SSHLv2i32 |
| 5498 | UINT64_C(1323320320), // SSHLv2i64 |
| 5499 | UINT64_C(241189888), // SSHLv4i16 |
| 5500 | UINT64_C(1319126016), // SSHLv4i32 |
| 5501 | UINT64_C(1314931712), // SSHLv8i16 |
| 5502 | UINT64_C(236995584), // SSHLv8i8 |
| 5503 | UINT64_C(1598030848), // SSHRd |
| 5504 | UINT64_C(1325925376), // SSHRv16i8_shift |
| 5505 | UINT64_C(253756416), // SSHRv2i32_shift |
| 5506 | UINT64_C(1329595392), // SSHRv2i64_shift |
| 5507 | UINT64_C(252707840), // SSHRv4i16_shift |
| 5508 | UINT64_C(1327498240), // SSHRv4i32_shift |
| 5509 | UINT64_C(1326449664), // SSHRv8i16_shift |
| 5510 | UINT64_C(252183552), // SSHRv8i8_shift |
| 5511 | UINT64_C(1158209536), // SSRA_ZZI_B |
| 5512 | UINT64_C(1166073856), // SSRA_ZZI_D |
| 5513 | UINT64_C(1158733824), // SSRA_ZZI_H |
| 5514 | UINT64_C(1161879552), // SSRA_ZZI_S |
| 5515 | UINT64_C(1598034944), // SSRAd |
| 5516 | UINT64_C(1325929472), // SSRAv16i8_shift |
| 5517 | UINT64_C(253760512), // SSRAv2i32_shift |
| 5518 | UINT64_C(1329599488), // SSRAv2i64_shift |
| 5519 | UINT64_C(252711936), // SSRAv4i16_shift |
| 5520 | UINT64_C(1327502336), // SSRAv4i32_shift |
| 5521 | UINT64_C(1326453760), // SSRAv8i16_shift |
| 5522 | UINT64_C(252187648), // SSRAv8i8_shift |
| 5523 | UINT64_C(3825246208), // SST1B_D |
| 5524 | UINT64_C(3829440512), // SST1B_D_IMM |
| 5525 | UINT64_C(3825254400), // SST1B_D_SXTW |
| 5526 | UINT64_C(3825238016), // SST1B_D_UXTW |
| 5527 | UINT64_C(3831537664), // SST1B_S_IMM |
| 5528 | UINT64_C(3829448704), // SST1B_S_SXTW |
| 5529 | UINT64_C(3829432320), // SST1B_S_UXTW |
| 5530 | UINT64_C(3850412032), // SST1D |
| 5531 | UINT64_C(3854606336), // SST1D_IMM |
| 5532 | UINT64_C(3852509184), // SST1D_SCALED |
| 5533 | UINT64_C(3850420224), // SST1D_SXTW |
| 5534 | UINT64_C(3852517376), // SST1D_SXTW_SCALED |
| 5535 | UINT64_C(3850403840), // SST1D_UXTW |
| 5536 | UINT64_C(3852500992), // SST1D_UXTW_SCALED |
| 5537 | UINT64_C(3833634816), // SST1H_D |
| 5538 | UINT64_C(3837829120), // SST1H_D_IMM |
| 5539 | UINT64_C(3835731968), // SST1H_D_SCALED |
| 5540 | UINT64_C(3833643008), // SST1H_D_SXTW |
| 5541 | UINT64_C(3835740160), // SST1H_D_SXTW_SCALED |
| 5542 | UINT64_C(3833626624), // SST1H_D_UXTW |
| 5543 | UINT64_C(3835723776), // SST1H_D_UXTW_SCALED |
| 5544 | UINT64_C(3839926272), // SST1H_S_IMM |
| 5545 | UINT64_C(3837837312), // SST1H_S_SXTW |
| 5546 | UINT64_C(3839934464), // SST1H_S_SXTW_SCALED |
| 5547 | UINT64_C(3837820928), // SST1H_S_UXTW |
| 5548 | UINT64_C(3839918080), // SST1H_S_UXTW_SCALED |
| 5549 | UINT64_C(3827310592), // SST1Q |
| 5550 | UINT64_C(3842023424), // SST1W_D |
| 5551 | UINT64_C(3846217728), // SST1W_D_IMM |
| 5552 | UINT64_C(3844120576), // SST1W_D_SCALED |
| 5553 | UINT64_C(3842031616), // SST1W_D_SXTW |
| 5554 | UINT64_C(3844128768), // SST1W_D_SXTW_SCALED |
| 5555 | UINT64_C(3842015232), // SST1W_D_UXTW |
| 5556 | UINT64_C(3844112384), // SST1W_D_UXTW_SCALED |
| 5557 | UINT64_C(3848314880), // SST1W_IMM |
| 5558 | UINT64_C(3846225920), // SST1W_SXTW |
| 5559 | UINT64_C(3848323072), // SST1W_SXTW_SCALED |
| 5560 | UINT64_C(3846209536), // SST1W_UXTW |
| 5561 | UINT64_C(3848306688), // SST1W_UXTW_SCALED |
| 5562 | UINT64_C(1170245632), // SSUBLBT_ZZZ_D |
| 5563 | UINT64_C(1161857024), // SSUBLBT_ZZZ_H |
| 5564 | UINT64_C(1166051328), // SSUBLBT_ZZZ_S |
| 5565 | UINT64_C(1170214912), // SSUBLB_ZZZ_D |
| 5566 | UINT64_C(1161826304), // SSUBLB_ZZZ_H |
| 5567 | UINT64_C(1166020608), // SSUBLB_ZZZ_S |
| 5568 | UINT64_C(1170246656), // SSUBLTB_ZZZ_D |
| 5569 | UINT64_C(1161858048), // SSUBLTB_ZZZ_H |
| 5570 | UINT64_C(1166052352), // SSUBLTB_ZZZ_S |
| 5571 | UINT64_C(1170215936), // SSUBLT_ZZZ_D |
| 5572 | UINT64_C(1161827328), // SSUBLT_ZZZ_H |
| 5573 | UINT64_C(1166021632), // SSUBLT_ZZZ_S |
| 5574 | UINT64_C(1310728192), // SSUBLv16i8_v8i16 |
| 5575 | UINT64_C(245374976), // SSUBLv2i32_v2i64 |
| 5576 | UINT64_C(241180672), // SSUBLv4i16_v4i32 |
| 5577 | UINT64_C(1319116800), // SSUBLv4i32_v2i64 |
| 5578 | UINT64_C(1314922496), // SSUBLv8i16_v4i32 |
| 5579 | UINT64_C(236986368), // SSUBLv8i8_v8i16 |
| 5580 | UINT64_C(1170231296), // SSUBWB_ZZZ_D |
| 5581 | UINT64_C(1161842688), // SSUBWB_ZZZ_H |
| 5582 | UINT64_C(1166036992), // SSUBWB_ZZZ_S |
| 5583 | UINT64_C(1170232320), // SSUBWT_ZZZ_D |
| 5584 | UINT64_C(1161843712), // SSUBWT_ZZZ_H |
| 5585 | UINT64_C(1166038016), // SSUBWT_ZZZ_S |
| 5586 | UINT64_C(1310732288), // SSUBWv16i8_v8i16 |
| 5587 | UINT64_C(245379072), // SSUBWv2i32_v2i64 |
| 5588 | UINT64_C(241184768), // SSUBWv4i16_v4i32 |
| 5589 | UINT64_C(1319120896), // SSUBWv4i32_v2i64 |
| 5590 | UINT64_C(1314926592), // SSUBWv8i16_v4i32 |
| 5591 | UINT64_C(236990464), // SSUBWv8i8_v8i16 |
| 5592 | UINT64_C(3825221632), // ST1B |
| 5593 | UINT64_C(2686451712), // ST1B_2Z |
| 5594 | UINT64_C(2690646016), // ST1B_2Z_IMM |
| 5595 | UINT64_C(2703228928), // ST1B_2Z_STRIDED |
| 5596 | UINT64_C(2707423232), // ST1B_2Z_STRIDED_IMM |
| 5597 | UINT64_C(2686484480), // ST1B_4Z |
| 5598 | UINT64_C(2690678784), // ST1B_4Z_IMM |
| 5599 | UINT64_C(2703261696), // ST1B_4Z_STRIDED |
| 5600 | UINT64_C(2707456000), // ST1B_4Z_STRIDED_IMM |
| 5601 | UINT64_C(3831513088), // ST1B_D |
| 5602 | UINT64_C(3831554048), // ST1B_D_IMM |
| 5603 | UINT64_C(3827318784), // ST1B_H |
| 5604 | UINT64_C(3827359744), // ST1B_H_IMM |
| 5605 | UINT64_C(3825262592), // ST1B_IMM |
| 5606 | UINT64_C(3829415936), // ST1B_S |
| 5607 | UINT64_C(3829456896), // ST1B_S_IMM |
| 5608 | UINT64_C(3856678912), // ST1D |
| 5609 | UINT64_C(2686476288), // ST1D_2Z |
| 5610 | UINT64_C(2690670592), // ST1D_2Z_IMM |
| 5611 | UINT64_C(2703253504), // ST1D_2Z_STRIDED |
| 5612 | UINT64_C(2707447808), // ST1D_2Z_STRIDED_IMM |
| 5613 | UINT64_C(2686509056), // ST1D_4Z |
| 5614 | UINT64_C(2690703360), // ST1D_4Z_IMM |
| 5615 | UINT64_C(2703286272), // ST1D_4Z_STRIDED |
| 5616 | UINT64_C(2707480576), // ST1D_4Z_STRIDED_IMM |
| 5617 | UINT64_C(3856719872), // ST1D_IMM |
| 5618 | UINT64_C(3854581760), // ST1D_Q |
| 5619 | UINT64_C(3854622720), // ST1D_Q_IMM |
| 5620 | UINT64_C(1275076608), // ST1Fourv16b |
| 5621 | UINT64_C(1283465216), // ST1Fourv16b_POST |
| 5622 | UINT64_C(201337856), // ST1Fourv1d |
| 5623 | UINT64_C(209726464), // ST1Fourv1d_POST |
| 5624 | UINT64_C(1275079680), // ST1Fourv2d |
| 5625 | UINT64_C(1283468288), // ST1Fourv2d_POST |
| 5626 | UINT64_C(201336832), // ST1Fourv2s |
| 5627 | UINT64_C(209725440), // ST1Fourv2s_POST |
| 5628 | UINT64_C(201335808), // ST1Fourv4h |
| 5629 | UINT64_C(209724416), // ST1Fourv4h_POST |
| 5630 | UINT64_C(1275078656), // ST1Fourv4s |
| 5631 | UINT64_C(1283467264), // ST1Fourv4s_POST |
| 5632 | UINT64_C(201334784), // ST1Fourv8b |
| 5633 | UINT64_C(209723392), // ST1Fourv8b_POST |
| 5634 | UINT64_C(1275077632), // ST1Fourv8h |
| 5635 | UINT64_C(1283466240), // ST1Fourv8h_POST |
| 5636 | UINT64_C(3835707392), // ST1H |
| 5637 | UINT64_C(2686459904), // ST1H_2Z |
| 5638 | UINT64_C(2690654208), // ST1H_2Z_IMM |
| 5639 | UINT64_C(2703237120), // ST1H_2Z_STRIDED |
| 5640 | UINT64_C(2707431424), // ST1H_2Z_STRIDED_IMM |
| 5641 | UINT64_C(2686492672), // ST1H_4Z |
| 5642 | UINT64_C(2690686976), // ST1H_4Z_IMM |
| 5643 | UINT64_C(2703269888), // ST1H_4Z_STRIDED |
| 5644 | UINT64_C(2707464192), // ST1H_4Z_STRIDED_IMM |
| 5645 | UINT64_C(3839901696), // ST1H_D |
| 5646 | UINT64_C(3839942656), // ST1H_D_IMM |
| 5647 | UINT64_C(3835748352), // ST1H_IMM |
| 5648 | UINT64_C(3837804544), // ST1H_S |
| 5649 | UINT64_C(3837845504), // ST1H_S_IMM |
| 5650 | UINT64_C(1275097088), // ST1Onev16b |
| 5651 | UINT64_C(1283485696), // ST1Onev16b_POST |
| 5652 | UINT64_C(201358336), // ST1Onev1d |
| 5653 | UINT64_C(209746944), // ST1Onev1d_POST |
| 5654 | UINT64_C(1275100160), // ST1Onev2d |
| 5655 | UINT64_C(1283488768), // ST1Onev2d_POST |
| 5656 | UINT64_C(201357312), // ST1Onev2s |
| 5657 | UINT64_C(209745920), // ST1Onev2s_POST |
| 5658 | UINT64_C(201356288), // ST1Onev4h |
| 5659 | UINT64_C(209744896), // ST1Onev4h_POST |
| 5660 | UINT64_C(1275099136), // ST1Onev4s |
| 5661 | UINT64_C(1283487744), // ST1Onev4s_POST |
| 5662 | UINT64_C(201355264), // ST1Onev8b |
| 5663 | UINT64_C(209743872), // ST1Onev8b_POST |
| 5664 | UINT64_C(1275098112), // ST1Onev8h |
| 5665 | UINT64_C(1283486720), // ST1Onev8h_POST |
| 5666 | UINT64_C(1275092992), // ST1Threev16b |
| 5667 | UINT64_C(1283481600), // ST1Threev16b_POST |
| 5668 | UINT64_C(201354240), // ST1Threev1d |
| 5669 | UINT64_C(209742848), // ST1Threev1d_POST |
| 5670 | UINT64_C(1275096064), // ST1Threev2d |
| 5671 | UINT64_C(1283484672), // ST1Threev2d_POST |
| 5672 | UINT64_C(201353216), // ST1Threev2s |
| 5673 | UINT64_C(209741824), // ST1Threev2s_POST |
| 5674 | UINT64_C(201352192), // ST1Threev4h |
| 5675 | UINT64_C(209740800), // ST1Threev4h_POST |
| 5676 | UINT64_C(1275095040), // ST1Threev4s |
| 5677 | UINT64_C(1283483648), // ST1Threev4s_POST |
| 5678 | UINT64_C(201351168), // ST1Threev8b |
| 5679 | UINT64_C(209739776), // ST1Threev8b_POST |
| 5680 | UINT64_C(1275094016), // ST1Threev8h |
| 5681 | UINT64_C(1283482624), // ST1Threev8h_POST |
| 5682 | UINT64_C(1275109376), // ST1Twov16b |
| 5683 | UINT64_C(1283497984), // ST1Twov16b_POST |
| 5684 | UINT64_C(201370624), // ST1Twov1d |
| 5685 | UINT64_C(209759232), // ST1Twov1d_POST |
| 5686 | UINT64_C(1275112448), // ST1Twov2d |
| 5687 | UINT64_C(1283501056), // ST1Twov2d_POST |
| 5688 | UINT64_C(201369600), // ST1Twov2s |
| 5689 | UINT64_C(209758208), // ST1Twov2s_POST |
| 5690 | UINT64_C(201368576), // ST1Twov4h |
| 5691 | UINT64_C(209757184), // ST1Twov4h_POST |
| 5692 | UINT64_C(1275111424), // ST1Twov4s |
| 5693 | UINT64_C(1283500032), // ST1Twov4s_POST |
| 5694 | UINT64_C(201367552), // ST1Twov8b |
| 5695 | UINT64_C(209756160), // ST1Twov8b_POST |
| 5696 | UINT64_C(1275110400), // ST1Twov8h |
| 5697 | UINT64_C(1283499008), // ST1Twov8h_POST |
| 5698 | UINT64_C(3846193152), // ST1W |
| 5699 | UINT64_C(2686468096), // ST1W_2Z |
| 5700 | UINT64_C(2690662400), // ST1W_2Z_IMM |
| 5701 | UINT64_C(2703245312), // ST1W_2Z_STRIDED |
| 5702 | UINT64_C(2707439616), // ST1W_2Z_STRIDED_IMM |
| 5703 | UINT64_C(2686500864), // ST1W_4Z |
| 5704 | UINT64_C(2690695168), // ST1W_4Z_IMM |
| 5705 | UINT64_C(2703278080), // ST1W_4Z_STRIDED |
| 5706 | UINT64_C(2707472384), // ST1W_4Z_STRIDED_IMM |
| 5707 | UINT64_C(3848290304), // ST1W_D |
| 5708 | UINT64_C(3848331264), // ST1W_D_IMM |
| 5709 | UINT64_C(3846234112), // ST1W_IMM |
| 5710 | UINT64_C(3841998848), // ST1W_Q |
| 5711 | UINT64_C(3842039808), // ST1W_Q_IMM |
| 5712 | UINT64_C(3760193536), // ST1_MXIPXX_H_B |
| 5713 | UINT64_C(3772776448), // ST1_MXIPXX_H_D |
| 5714 | UINT64_C(3764387840), // ST1_MXIPXX_H_H |
| 5715 | UINT64_C(3789553664), // ST1_MXIPXX_H_Q |
| 5716 | UINT64_C(3768582144), // ST1_MXIPXX_H_S |
| 5717 | UINT64_C(3760226304), // ST1_MXIPXX_V_B |
| 5718 | UINT64_C(3772809216), // ST1_MXIPXX_V_D |
| 5719 | UINT64_C(3764420608), // ST1_MXIPXX_V_H |
| 5720 | UINT64_C(3789586432), // ST1_MXIPXX_V_Q |
| 5721 | UINT64_C(3768614912), // ST1_MXIPXX_V_S |
| 5722 | UINT64_C(218120192), // ST1i16 |
| 5723 | UINT64_C(226508800), // ST1i16_POST |
| 5724 | UINT64_C(218136576), // ST1i32 |
| 5725 | UINT64_C(226525184), // ST1i32_POST |
| 5726 | UINT64_C(218137600), // ST1i64 |
| 5727 | UINT64_C(226526208), // ST1i64_POST |
| 5728 | UINT64_C(218103808), // ST1i8 |
| 5729 | UINT64_C(226492416), // ST1i8_POST |
| 5730 | UINT64_C(3827326976), // ST2B |
| 5731 | UINT64_C(3828408320), // ST2B_IMM |
| 5732 | UINT64_C(3852492800), // ST2D |
| 5733 | UINT64_C(3853574144), // ST2D_IMM |
| 5734 | UINT64_C(3651142656), // ST2GPostIndex |
| 5735 | UINT64_C(3651144704), // ST2GPreIndex |
| 5736 | UINT64_C(3651143680), // ST2Gi |
| 5737 | UINT64_C(3835715584), // ST2H |
| 5738 | UINT64_C(3836796928), // ST2H_IMM |
| 5739 | UINT64_C(3831496704), // ST2Q |
| 5740 | UINT64_C(3829399552), // ST2Q_IMM |
| 5741 | UINT64_C(1275101184), // ST2Twov16b |
| 5742 | UINT64_C(1283489792), // ST2Twov16b_POST |
| 5743 | UINT64_C(1275104256), // ST2Twov2d |
| 5744 | UINT64_C(1283492864), // ST2Twov2d_POST |
| 5745 | UINT64_C(201361408), // ST2Twov2s |
| 5746 | UINT64_C(209750016), // ST2Twov2s_POST |
| 5747 | UINT64_C(201360384), // ST2Twov4h |
| 5748 | UINT64_C(209748992), // ST2Twov4h_POST |
| 5749 | UINT64_C(1275103232), // ST2Twov4s |
| 5750 | UINT64_C(1283491840), // ST2Twov4s_POST |
| 5751 | UINT64_C(201359360), // ST2Twov8b |
| 5752 | UINT64_C(209747968), // ST2Twov8b_POST |
| 5753 | UINT64_C(1275102208), // ST2Twov8h |
| 5754 | UINT64_C(1283490816), // ST2Twov8h_POST |
| 5755 | UINT64_C(3844104192), // ST2W |
| 5756 | UINT64_C(3845185536), // ST2W_IMM |
| 5757 | UINT64_C(220217344), // ST2i16 |
| 5758 | UINT64_C(228605952), // ST2i16_POST |
| 5759 | UINT64_C(220233728), // ST2i32 |
| 5760 | UINT64_C(228622336), // ST2i32_POST |
| 5761 | UINT64_C(220234752), // ST2i64 |
| 5762 | UINT64_C(228623360), // ST2i64_POST |
| 5763 | UINT64_C(220200960), // ST2i8 |
| 5764 | UINT64_C(228589568), // ST2i8_POST |
| 5765 | UINT64_C(3829424128), // ST3B |
| 5766 | UINT64_C(3830505472), // ST3B_IMM |
| 5767 | UINT64_C(3854589952), // ST3D |
| 5768 | UINT64_C(3855671296), // ST3D_IMM |
| 5769 | UINT64_C(3837812736), // ST3H |
| 5770 | UINT64_C(3838894080), // ST3H_IMM |
| 5771 | UINT64_C(3835691008), // ST3Q |
| 5772 | UINT64_C(3833593856), // ST3Q_IMM |
| 5773 | UINT64_C(1275084800), // ST3Threev16b |
| 5774 | UINT64_C(1283473408), // ST3Threev16b_POST |
| 5775 | UINT64_C(1275087872), // ST3Threev2d |
| 5776 | UINT64_C(1283476480), // ST3Threev2d_POST |
| 5777 | UINT64_C(201345024), // ST3Threev2s |
| 5778 | UINT64_C(209733632), // ST3Threev2s_POST |
| 5779 | UINT64_C(201344000), // ST3Threev4h |
| 5780 | UINT64_C(209732608), // ST3Threev4h_POST |
| 5781 | UINT64_C(1275086848), // ST3Threev4s |
| 5782 | UINT64_C(1283475456), // ST3Threev4s_POST |
| 5783 | UINT64_C(201342976), // ST3Threev8b |
| 5784 | UINT64_C(209731584), // ST3Threev8b_POST |
| 5785 | UINT64_C(1275085824), // ST3Threev8h |
| 5786 | UINT64_C(1283474432), // ST3Threev8h_POST |
| 5787 | UINT64_C(3846201344), // ST3W |
| 5788 | UINT64_C(3847282688), // ST3W_IMM |
| 5789 | UINT64_C(218128384), // ST3i16 |
| 5790 | UINT64_C(226516992), // ST3i16_POST |
| 5791 | UINT64_C(218144768), // ST3i32 |
| 5792 | UINT64_C(226533376), // ST3i32_POST |
| 5793 | UINT64_C(218145792), // ST3i64 |
| 5794 | UINT64_C(226534400), // ST3i64_POST |
| 5795 | UINT64_C(218112000), // ST3i8 |
| 5796 | UINT64_C(226500608), // ST3i8_POST |
| 5797 | UINT64_C(3831521280), // ST4B |
| 5798 | UINT64_C(3832602624), // ST4B_IMM |
| 5799 | UINT64_C(3856687104), // ST4D |
| 5800 | UINT64_C(3857768448), // ST4D_IMM |
| 5801 | UINT64_C(1275068416), // ST4Fourv16b |
| 5802 | UINT64_C(1283457024), // ST4Fourv16b_POST |
| 5803 | UINT64_C(1275071488), // ST4Fourv2d |
| 5804 | UINT64_C(1283460096), // ST4Fourv2d_POST |
| 5805 | UINT64_C(201328640), // ST4Fourv2s |
| 5806 | UINT64_C(209717248), // ST4Fourv2s_POST |
| 5807 | UINT64_C(201327616), // ST4Fourv4h |
| 5808 | UINT64_C(209716224), // ST4Fourv4h_POST |
| 5809 | UINT64_C(1275070464), // ST4Fourv4s |
| 5810 | UINT64_C(1283459072), // ST4Fourv4s_POST |
| 5811 | UINT64_C(201326592), // ST4Fourv8b |
| 5812 | UINT64_C(209715200), // ST4Fourv8b_POST |
| 5813 | UINT64_C(1275069440), // ST4Fourv8h |
| 5814 | UINT64_C(1283458048), // ST4Fourv8h_POST |
| 5815 | UINT64_C(3839909888), // ST4H |
| 5816 | UINT64_C(3840991232), // ST4H_IMM |
| 5817 | UINT64_C(3839885312), // ST4Q |
| 5818 | UINT64_C(3837788160), // ST4Q_IMM |
| 5819 | UINT64_C(3848298496), // ST4W |
| 5820 | UINT64_C(3849379840), // ST4W_IMM |
| 5821 | UINT64_C(220225536), // ST4i16 |
| 5822 | UINT64_C(228614144), // ST4i16_POST |
| 5823 | UINT64_C(220241920), // ST4i32 |
| 5824 | UINT64_C(228630528), // ST4i32_POST |
| 5825 | UINT64_C(220242944), // ST4i64 |
| 5826 | UINT64_C(228631552), // ST4i64_POST |
| 5827 | UINT64_C(220209152), // ST4i8 |
| 5828 | UINT64_C(228597760), // ST4i8_POST |
| 5829 | UINT64_C(4164915200), // ST64B |
| 5830 | UINT64_C(4162891776), // ST64BV |
| 5831 | UINT64_C(4162887680), // ST64BV0 |
| 5832 | UINT64_C(1008762911), // STBFADD |
| 5833 | UINT64_C(1012957215), // STBFADDL |
| 5834 | UINT64_C(1008779295), // STBFMAX |
| 5835 | UINT64_C(1012973599), // STBFMAXL |
| 5836 | UINT64_C(1008787487), // STBFMAXNM |
| 5837 | UINT64_C(1012981791), // STBFMAXNML |
| 5838 | UINT64_C(1008783391), // STBFMIN |
| 5839 | UINT64_C(1012977695), // STBFMINL |
| 5840 | UINT64_C(1008791583), // STBFMINNM |
| 5841 | UINT64_C(1012985887), // STBFMINNML |
| 5842 | UINT64_C(4229988383), // STFADDD |
| 5843 | UINT64_C(2082504735), // STFADDH |
| 5844 | UINT64_C(4234182687), // STFADDLD |
| 5845 | UINT64_C(2086699039), // STFADDLH |
| 5846 | UINT64_C(3160440863), // STFADDLS |
| 5847 | UINT64_C(3156246559), // STFADDS |
| 5848 | UINT64_C(4230004767), // STFMAXD |
| 5849 | UINT64_C(2082521119), // STFMAXH |
| 5850 | UINT64_C(4234199071), // STFMAXLD |
| 5851 | UINT64_C(2086715423), // STFMAXLH |
| 5852 | UINT64_C(3160457247), // STFMAXLS |
| 5853 | UINT64_C(4230012959), // STFMAXNMD |
| 5854 | UINT64_C(2082529311), // STFMAXNMH |
| 5855 | UINT64_C(4234207263), // STFMAXNMLD |
| 5856 | UINT64_C(2086723615), // STFMAXNMLH |
| 5857 | UINT64_C(3160465439), // STFMAXNMLS |
| 5858 | UINT64_C(3156271135), // STFMAXNMS |
| 5859 | UINT64_C(3156262943), // STFMAXS |
| 5860 | UINT64_C(4230008863), // STFMIND |
| 5861 | UINT64_C(2082525215), // STFMINH |
| 5862 | UINT64_C(4234203167), // STFMINLD |
| 5863 | UINT64_C(2086719519), // STFMINLH |
| 5864 | UINT64_C(3160461343), // STFMINLS |
| 5865 | UINT64_C(4230017055), // STFMINNMD |
| 5866 | UINT64_C(2082533407), // STFMINNMH |
| 5867 | UINT64_C(4234211359), // STFMINNMLD |
| 5868 | UINT64_C(2086727711), // STFMINNMLH |
| 5869 | UINT64_C(3160469535), // STFMINNMLS |
| 5870 | UINT64_C(3156275231), // STFMINNMS |
| 5871 | UINT64_C(3156267039), // STFMINS |
| 5872 | UINT64_C(3651141632), // STGM |
| 5873 | UINT64_C(1761607680), // STGPi |
| 5874 | UINT64_C(3642754048), // STGPostIndex |
| 5875 | UINT64_C(1753219072), // STGPpost |
| 5876 | UINT64_C(1769996288), // STGPpre |
| 5877 | UINT64_C(3642756096), // STGPreIndex |
| 5878 | UINT64_C(3642755072), // STGi |
| 5879 | UINT64_C(2566920192), // STILPW |
| 5880 | UINT64_C(2566916096), // STILPWpre |
| 5881 | UINT64_C(3640662016), // STILPX |
| 5882 | UINT64_C(3640657920), // STILPXpre |
| 5883 | UINT64_C(218203136), // STL1 |
| 5884 | UINT64_C(4169109504), // STL64B |
| 5885 | UINT64_C(4167086080), // STL64BV |
| 5886 | UINT64_C(4167081984), // STL64BV0 |
| 5887 | UINT64_C(144669696), // STLLRB |
| 5888 | UINT64_C(1218411520), // STLLRH |
| 5889 | UINT64_C(2292153344), // STLLRW |
| 5890 | UINT64_C(3365895168), // STLLRX |
| 5891 | UINT64_C(3640678400), // STLPi |
| 5892 | UINT64_C(144702464), // STLRB |
| 5893 | UINT64_C(1218444288), // STLRH |
| 5894 | UINT64_C(2292186112), // STLRW |
| 5895 | UINT64_C(2575304704), // STLRWpre |
| 5896 | UINT64_C(3365927936), // STLRX |
| 5897 | UINT64_C(3649046528), // STLRXpre |
| 5898 | UINT64_C(2298543104), // STLTXRW |
| 5899 | UINT64_C(3372284928), // STLTXRX |
| 5900 | UINT64_C(419430400), // STLURBi |
| 5901 | UINT64_C(1493172224), // STLURHi |
| 5902 | UINT64_C(2566914048), // STLURWi |
| 5903 | UINT64_C(3640655872), // STLURXi |
| 5904 | UINT64_C(486541312), // STLURbi |
| 5905 | UINT64_C(3707766784), // STLURdi |
| 5906 | UINT64_C(1560283136), // STLURhi |
| 5907 | UINT64_C(494929920), // STLURqi |
| 5908 | UINT64_C(2634024960), // STLURsi |
| 5909 | UINT64_C(2283831296), // STLXPW |
| 5910 | UINT64_C(3357573120), // STLXPX |
| 5911 | UINT64_C(134282240), // STLXRB |
| 5912 | UINT64_C(1208024064), // STLXRH |
| 5913 | UINT64_C(2281765888), // STLXRW |
| 5914 | UINT64_C(3355507712), // STLXRX |
| 5915 | UINT64_C(2151710720), // STMOPA_M2ZZZI_BtoS |
| 5916 | UINT64_C(2151710728), // STMOPA_M2ZZZI_HtoS |
| 5917 | UINT64_C(1811939328), // STNPDi |
| 5918 | UINT64_C(2885681152), // STNPQi |
| 5919 | UINT64_C(738197504), // STNPSi |
| 5920 | UINT64_C(671088640), // STNPWi |
| 5921 | UINT64_C(2818572288), // STNPXi |
| 5922 | UINT64_C(2686451713), // STNT1B_2Z |
| 5923 | UINT64_C(2690646017), // STNT1B_2Z_IMM |
| 5924 | UINT64_C(2703228936), // STNT1B_2Z_STRIDED |
| 5925 | UINT64_C(2707423240), // STNT1B_2Z_STRIDED_IMM |
| 5926 | UINT64_C(2686484481), // STNT1B_4Z |
| 5927 | UINT64_C(2690678785), // STNT1B_4Z_IMM |
| 5928 | UINT64_C(2703261704), // STNT1B_4Z_STRIDED |
| 5929 | UINT64_C(2707456008), // STNT1B_4Z_STRIDED_IMM |
| 5930 | UINT64_C(3826311168), // STNT1B_ZRI |
| 5931 | UINT64_C(3825229824), // STNT1B_ZRR |
| 5932 | UINT64_C(3825213440), // STNT1B_ZZR_D |
| 5933 | UINT64_C(3829407744), // STNT1B_ZZR_S |
| 5934 | UINT64_C(2686476289), // STNT1D_2Z |
| 5935 | UINT64_C(2690670593), // STNT1D_2Z_IMM |
| 5936 | UINT64_C(2703253512), // STNT1D_2Z_STRIDED |
| 5937 | UINT64_C(2707447816), // STNT1D_2Z_STRIDED_IMM |
| 5938 | UINT64_C(2686509057), // STNT1D_4Z |
| 5939 | UINT64_C(2690703361), // STNT1D_4Z_IMM |
| 5940 | UINT64_C(2703286280), // STNT1D_4Z_STRIDED |
| 5941 | UINT64_C(2707480584), // STNT1D_4Z_STRIDED_IMM |
| 5942 | UINT64_C(3851476992), // STNT1D_ZRI |
| 5943 | UINT64_C(3850395648), // STNT1D_ZRR |
| 5944 | UINT64_C(3850379264), // STNT1D_ZZR_D |
| 5945 | UINT64_C(2686459905), // STNT1H_2Z |
| 5946 | UINT64_C(2690654209), // STNT1H_2Z_IMM |
| 5947 | UINT64_C(2703237128), // STNT1H_2Z_STRIDED |
| 5948 | UINT64_C(2707431432), // STNT1H_2Z_STRIDED_IMM |
| 5949 | UINT64_C(2686492673), // STNT1H_4Z |
| 5950 | UINT64_C(2690686977), // STNT1H_4Z_IMM |
| 5951 | UINT64_C(2703269896), // STNT1H_4Z_STRIDED |
| 5952 | UINT64_C(2707464200), // STNT1H_4Z_STRIDED_IMM |
| 5953 | UINT64_C(3834699776), // STNT1H_ZRI |
| 5954 | UINT64_C(3833618432), // STNT1H_ZRR |
| 5955 | UINT64_C(3833602048), // STNT1H_ZZR_D |
| 5956 | UINT64_C(3837796352), // STNT1H_ZZR_S |
| 5957 | UINT64_C(2686468097), // STNT1W_2Z |
| 5958 | UINT64_C(2690662401), // STNT1W_2Z_IMM |
| 5959 | UINT64_C(2703245320), // STNT1W_2Z_STRIDED |
| 5960 | UINT64_C(2707439624), // STNT1W_2Z_STRIDED_IMM |
| 5961 | UINT64_C(2686500865), // STNT1W_4Z |
| 5962 | UINT64_C(2690695169), // STNT1W_4Z_IMM |
| 5963 | UINT64_C(2703278088), // STNT1W_4Z_STRIDED |
| 5964 | UINT64_C(2707472392), // STNT1W_4Z_STRIDED_IMM |
| 5965 | UINT64_C(3843088384), // STNT1W_ZRI |
| 5966 | UINT64_C(3842007040), // STNT1W_ZRR |
| 5967 | UINT64_C(3841990656), // STNT1W_ZZR_D |
| 5968 | UINT64_C(3846184960), // STNT1W_ZZR_S |
| 5969 | UINT64_C(1828716544), // STPDi |
| 5970 | UINT64_C(1820327936), // STPDpost |
| 5971 | UINT64_C(1837105152), // STPDpre |
| 5972 | UINT64_C(2902458368), // STPQi |
| 5973 | UINT64_C(2894069760), // STPQpost |
| 5974 | UINT64_C(2910846976), // STPQpre |
| 5975 | UINT64_C(754974720), // STPSi |
| 5976 | UINT64_C(746586112), // STPSpost |
| 5977 | UINT64_C(763363328), // STPSpre |
| 5978 | UINT64_C(687865856), // STPWi |
| 5979 | UINT64_C(679477248), // STPWpost |
| 5980 | UINT64_C(696254464), // STPWpre |
| 5981 | UINT64_C(2835349504), // STPXi |
| 5982 | UINT64_C(2826960896), // STPXpost |
| 5983 | UINT64_C(2843738112), // STPXpre |
| 5984 | UINT64_C(939525120), // STRBBpost |
| 5985 | UINT64_C(939527168), // STRBBpre |
| 5986 | UINT64_C(941639680), // STRBBroW |
| 5987 | UINT64_C(941647872), // STRBBroX |
| 5988 | UINT64_C(956301312), // STRBBui |
| 5989 | UINT64_C(1006633984), // STRBpost |
| 5990 | UINT64_C(1006636032), // STRBpre |
| 5991 | UINT64_C(1008748544), // STRBroW |
| 5992 | UINT64_C(1008756736), // STRBroX |
| 5993 | UINT64_C(1023410176), // STRBui |
| 5994 | UINT64_C(4227859456), // STRDpost |
| 5995 | UINT64_C(4227861504), // STRDpre |
| 5996 | UINT64_C(4229974016), // STRDroW |
| 5997 | UINT64_C(4229982208), // STRDroX |
| 5998 | UINT64_C(4244635648), // STRDui |
| 5999 | UINT64_C(2013266944), // STRHHpost |
| 6000 | UINT64_C(2013268992), // STRHHpre |
| 6001 | UINT64_C(2015381504), // STRHHroW |
| 6002 | UINT64_C(2015389696), // STRHHroX |
| 6003 | UINT64_C(2030043136), // STRHHui |
| 6004 | UINT64_C(2080375808), // STRHpost |
| 6005 | UINT64_C(2080377856), // STRHpre |
| 6006 | UINT64_C(2082490368), // STRHroW |
| 6007 | UINT64_C(2082498560), // STRHroX |
| 6008 | UINT64_C(2097152000), // STRHui |
| 6009 | UINT64_C(1015022592), // STRQpost |
| 6010 | UINT64_C(1015024640), // STRQpre |
| 6011 | UINT64_C(1017137152), // STRQroW |
| 6012 | UINT64_C(1017145344), // STRQroX |
| 6013 | UINT64_C(1031798784), // STRQui |
| 6014 | UINT64_C(3154117632), // STRSpost |
| 6015 | UINT64_C(3154119680), // STRSpre |
| 6016 | UINT64_C(3156232192), // STRSroW |
| 6017 | UINT64_C(3156240384), // STRSroX |
| 6018 | UINT64_C(3170893824), // STRSui |
| 6019 | UINT64_C(3087008768), // STRWpost |
| 6020 | UINT64_C(3087010816), // STRWpre |
| 6021 | UINT64_C(3089123328), // STRWroW |
| 6022 | UINT64_C(3089131520), // STRWroX |
| 6023 | UINT64_C(3103784960), // STRWui |
| 6024 | UINT64_C(4160750592), // STRXpost |
| 6025 | UINT64_C(4160752640), // STRXpre |
| 6026 | UINT64_C(4162865152), // STRXroW |
| 6027 | UINT64_C(4162873344), // STRXroX |
| 6028 | UINT64_C(4177526784), // STRXui |
| 6029 | UINT64_C(3850371072), // STR_PXI |
| 6030 | UINT64_C(3779035136), // STR_TX |
| 6031 | UINT64_C(3776970752), // STR_ZA |
| 6032 | UINT64_C(3850387456), // STR_ZXI |
| 6033 | UINT64_C(3959422976), // STTNPQi |
| 6034 | UINT64_C(3892314112), // STTNPXi |
| 6035 | UINT64_C(3976200192), // STTPQi |
| 6036 | UINT64_C(3967811584), // STTPQpost |
| 6037 | UINT64_C(3984588800), // STTPQpre |
| 6038 | UINT64_C(3909091328), // STTPi |
| 6039 | UINT64_C(3900702720), // STTPpost |
| 6040 | UINT64_C(3917479936), // STTPpre |
| 6041 | UINT64_C(939526144), // STTRBi |
| 6042 | UINT64_C(2013267968), // STTRHi |
| 6043 | UINT64_C(3087009792), // STTRWi |
| 6044 | UINT64_C(4160751616), // STTRXi |
| 6045 | UINT64_C(2298510336), // STTXRWr |
| 6046 | UINT64_C(3372252160), // STTXRXr |
| 6047 | UINT64_C(939524096), // STURBBi |
| 6048 | UINT64_C(1006632960), // STURBi |
| 6049 | UINT64_C(4227858432), // STURDi |
| 6050 | UINT64_C(2013265920), // STURHHi |
| 6051 | UINT64_C(2080374784), // STURHi |
| 6052 | UINT64_C(1015021568), // STURQi |
| 6053 | UINT64_C(3154116608), // STURSi |
| 6054 | UINT64_C(3087007744), // STURWi |
| 6055 | UINT64_C(4160749568), // STURXi |
| 6056 | UINT64_C(2283798528), // STXPW |
| 6057 | UINT64_C(3357540352), // STXPX |
| 6058 | UINT64_C(134249472), // STXRB |
| 6059 | UINT64_C(1207991296), // STXRH |
| 6060 | UINT64_C(2281733120), // STXRW |
| 6061 | UINT64_C(3355474944), // STXRX |
| 6062 | UINT64_C(3655336960), // STZ2GPostIndex |
| 6063 | UINT64_C(3655339008), // STZ2GPreIndex |
| 6064 | UINT64_C(3655337984), // STZ2Gi |
| 6065 | UINT64_C(3642753024), // STZGM |
| 6066 | UINT64_C(3646948352), // STZGPostIndex |
| 6067 | UINT64_C(3646950400), // STZGPreIndex |
| 6068 | UINT64_C(3646949376), // STZGi |
| 6069 | UINT64_C(3514826752), // SUBG |
| 6070 | UINT64_C(1163948032), // SUBHNB_ZZZ_B |
| 6071 | UINT64_C(1168142336), // SUBHNB_ZZZ_H |
| 6072 | UINT64_C(1172336640), // SUBHNB_ZZZ_S |
| 6073 | UINT64_C(1163949056), // SUBHNT_ZZZ_B |
| 6074 | UINT64_C(1168143360), // SUBHNT_ZZZ_H |
| 6075 | UINT64_C(1172337664), // SUBHNT_ZZZ_S |
| 6076 | UINT64_C(245391360), // SUBHNv2i64_v2i32 |
| 6077 | UINT64_C(1319133184), // SUBHNv2i64_v4i32 |
| 6078 | UINT64_C(241197056), // SUBHNv4i32_v4i16 |
| 6079 | UINT64_C(1314938880), // SUBHNv4i32_v8i16 |
| 6080 | UINT64_C(1310744576), // SUBHNv8i16_v16i8 |
| 6081 | UINT64_C(237002752), // SUBHNv8i16_v8i8 |
| 6082 | UINT64_C(2596274176), // SUBP |
| 6083 | UINT64_C(3133145088), // SUBPS |
| 6084 | UINT64_C(3657441280), // SUBPT_shift |
| 6085 | UINT64_C(1141940224), // SUBP_ZPmZZ_B |
| 6086 | UINT64_C(1154523136), // SUBP_ZPmZZ_D |
| 6087 | UINT64_C(1146134528), // SUBP_ZPmZZ_H |
| 6088 | UINT64_C(1150328832), // SUBP_ZPmZZ_S |
| 6089 | UINT64_C(623099904), // SUBR_ZI_B |
| 6090 | UINT64_C(635682816), // SUBR_ZI_D |
| 6091 | UINT64_C(627294208), // SUBR_ZI_H |
| 6092 | UINT64_C(631488512), // SUBR_ZI_S |
| 6093 | UINT64_C(67305472), // SUBR_ZPmZ_B |
| 6094 | UINT64_C(79888384), // SUBR_ZPmZ_D |
| 6095 | UINT64_C(71499776), // SUBR_ZPmZ_H |
| 6096 | UINT64_C(75694080), // SUBR_ZPmZ_S |
| 6097 | UINT64_C(1895825408), // SUBSWri |
| 6098 | UINT64_C(1795162112), // SUBSWrs |
| 6099 | UINT64_C(1797259264), // SUBSWrx |
| 6100 | UINT64_C(4043309056), // SUBSXri |
| 6101 | UINT64_C(3942645760), // SUBSXrs |
| 6102 | UINT64_C(3944742912), // SUBSXrx |
| 6103 | UINT64_C(3944767488), // SUBSXrx64 |
| 6104 | UINT64_C(1358954496), // SUBWri |
| 6105 | UINT64_C(1258291200), // SUBWrs |
| 6106 | UINT64_C(1260388352), // SUBWrx |
| 6107 | UINT64_C(3506438144), // SUBXri |
| 6108 | UINT64_C(3405774848), // SUBXrs |
| 6109 | UINT64_C(3407872000), // SUBXrx |
| 6110 | UINT64_C(3407896576), // SUBXrx64 |
| 6111 | UINT64_C(3252688920), // SUB_VG2_M2Z2Z_D |
| 6112 | UINT64_C(3248494616), // SUB_VG2_M2Z2Z_S |
| 6113 | UINT64_C(3244300312), // SUB_VG2_M2ZZ_D |
| 6114 | UINT64_C(3240106008), // SUB_VG2_M2ZZ_S |
| 6115 | UINT64_C(3252689944), // SUB_VG2_M2Z_D |
| 6116 | UINT64_C(3248495640), // SUB_VG2_M2Z_S |
| 6117 | UINT64_C(3252754456), // SUB_VG4_M4Z4Z_D |
| 6118 | UINT64_C(3248560152), // SUB_VG4_M4Z4Z_S |
| 6119 | UINT64_C(3245348888), // SUB_VG4_M4ZZ_D |
| 6120 | UINT64_C(3241154584), // SUB_VG4_M4ZZ_S |
| 6121 | UINT64_C(3252755480), // SUB_VG4_M4Z_D |
| 6122 | UINT64_C(3248561176), // SUB_VG4_M4Z_S |
| 6123 | UINT64_C(622968832), // SUB_ZI_B |
| 6124 | UINT64_C(635551744), // SUB_ZI_D |
| 6125 | UINT64_C(627163136), // SUB_ZI_H |
| 6126 | UINT64_C(631357440), // SUB_ZI_S |
| 6127 | UINT64_C(67174400), // SUB_ZPmZ_B |
| 6128 | UINT64_C(80019456), // SUB_ZPmZ_CPA |
| 6129 | UINT64_C(79757312), // SUB_ZPmZ_D |
| 6130 | UINT64_C(71368704), // SUB_ZPmZ_H |
| 6131 | UINT64_C(75563008), // SUB_ZPmZ_S |
| 6132 | UINT64_C(69207040), // SUB_ZZZ_B |
| 6133 | UINT64_C(81792000), // SUB_ZZZ_CPA |
| 6134 | UINT64_C(81789952), // SUB_ZZZ_D |
| 6135 | UINT64_C(73401344), // SUB_ZZZ_H |
| 6136 | UINT64_C(77595648), // SUB_ZZZ_S |
| 6137 | UINT64_C(1847624704), // SUBv16i8 |
| 6138 | UINT64_C(2128643072), // SUBv1i64 |
| 6139 | UINT64_C(782271488), // SUBv2i32 |
| 6140 | UINT64_C(1860207616), // SUBv2i64 |
| 6141 | UINT64_C(778077184), // SUBv4i16 |
| 6142 | UINT64_C(1856013312), // SUBv4i32 |
| 6143 | UINT64_C(1851819008), // SUBv8i16 |
| 6144 | UINT64_C(773882880), // SUBv8i8 |
| 6145 | UINT64_C(3243249720), // SUDOT_VG2_M2ZZI_BToS |
| 6146 | UINT64_C(3240104984), // SUDOT_VG2_M2ZZ_BToS |
| 6147 | UINT64_C(3243282488), // SUDOT_VG4_M4ZZI_BToS |
| 6148 | UINT64_C(3241153560), // SUDOT_VG4_M4ZZ_BToS |
| 6149 | UINT64_C(1151343616), // SUDOT_ZZZI |
| 6150 | UINT64_C(1325461504), // SUDOTlanev16i8 |
| 6151 | UINT64_C(251719680), // SUDOTlanev8i8 |
| 6152 | UINT64_C(3238002708), // SUMLALL_MZZI_BtoS |
| 6153 | UINT64_C(3239051312), // SUMLALL_VG2_M2ZZI_BtoS |
| 6154 | UINT64_C(3240099860), // SUMLALL_VG2_M2ZZ_BtoS |
| 6155 | UINT64_C(3239084080), // SUMLALL_VG4_M4ZZI_BtoS |
| 6156 | UINT64_C(3241148436), // SUMLALL_VG4_M4ZZ_BtoS |
| 6157 | UINT64_C(2150662656), // SUMOP4A_M2Z2Z_BToS |
| 6158 | UINT64_C(2700083720), // SUMOP4A_M2Z2Z_HtoD |
| 6159 | UINT64_C(2149614080), // SUMOP4A_M2ZZ_BToS |
| 6160 | UINT64_C(2699035144), // SUMOP4A_M2ZZ_HtoD |
| 6161 | UINT64_C(2150662144), // SUMOP4A_MZ2Z_BToS |
| 6162 | UINT64_C(2700083208), // SUMOP4A_MZ2Z_HtoD |
| 6163 | UINT64_C(2149613568), // SUMOP4A_MZZ_BToS |
| 6164 | UINT64_C(2699034632), // SUMOP4A_MZZ_HtoD |
| 6165 | UINT64_C(2150662672), // SUMOP4S_M2Z2Z_BToS |
| 6166 | UINT64_C(2700083736), // SUMOP4S_M2Z2Z_HtoD |
| 6167 | UINT64_C(2149614096), // SUMOP4S_M2ZZ_BToS |
| 6168 | UINT64_C(2699035160), // SUMOP4S_M2ZZ_HtoD |
| 6169 | UINT64_C(2150662160), // SUMOP4S_MZ2Z_BToS |
| 6170 | UINT64_C(2700083224), // SUMOP4S_MZ2Z_HtoD |
| 6171 | UINT64_C(2149613584), // SUMOP4S_MZZ_BToS |
| 6172 | UINT64_C(2699034648), // SUMOP4S_MZZ_HtoD |
| 6173 | UINT64_C(2699034624), // SUMOPA_MPPZZ_D |
| 6174 | UINT64_C(2694840320), // SUMOPA_MPPZZ_S |
| 6175 | UINT64_C(2699034640), // SUMOPS_MPPZZ_D |
| 6176 | UINT64_C(2694840336), // SUMOPS_MPPZZ_S |
| 6177 | UINT64_C(99694592), // SUNPKHI_ZZ_D |
| 6178 | UINT64_C(91305984), // SUNPKHI_ZZ_H |
| 6179 | UINT64_C(95500288), // SUNPKHI_ZZ_S |
| 6180 | UINT64_C(99629056), // SUNPKLO_ZZ_D |
| 6181 | UINT64_C(91240448), // SUNPKLO_ZZ_H |
| 6182 | UINT64_C(95434752), // SUNPKLO_ZZ_S |
| 6183 | UINT64_C(3253067776), // SUNPK_VG2_2ZZ_D |
| 6184 | UINT64_C(3244679168), // SUNPK_VG2_2ZZ_H |
| 6185 | UINT64_C(3248873472), // SUNPK_VG2_2ZZ_S |
| 6186 | UINT64_C(3254116352), // SUNPK_VG4_4Z2Z_D |
| 6187 | UINT64_C(3245727744), // SUNPK_VG4_4Z2Z_H |
| 6188 | UINT64_C(3249922048), // SUNPK_VG4_4Z2Z_S |
| 6189 | UINT64_C(1142718464), // SUQADD_ZPmZ_B |
| 6190 | UINT64_C(1155301376), // SUQADD_ZPmZ_D |
| 6191 | UINT64_C(1146912768), // SUQADD_ZPmZ_H |
| 6192 | UINT64_C(1151107072), // SUQADD_ZPmZ_S |
| 6193 | UINT64_C(1310734336), // SUQADDv16i8 |
| 6194 | UINT64_C(1583364096), // SUQADDv1i16 |
| 6195 | UINT64_C(1587558400), // SUQADDv1i32 |
| 6196 | UINT64_C(1591752704), // SUQADDv1i64 |
| 6197 | UINT64_C(1579169792), // SUQADDv1i8 |
| 6198 | UINT64_C(245381120), // SUQADDv2i32 |
| 6199 | UINT64_C(1323317248), // SUQADDv2i64 |
| 6200 | UINT64_C(241186816), // SUQADDv4i16 |
| 6201 | UINT64_C(1319122944), // SUQADDv4i32 |
| 6202 | UINT64_C(1314928640), // SUQADDv8i16 |
| 6203 | UINT64_C(236992512), // SUQADDv8i8 |
| 6204 | UINT64_C(2153807872), // SUTMOPA_M2ZZZI_BtoS |
| 6205 | UINT64_C(3243278392), // SUVDOT_VG4_M4ZZI_BToS |
| 6206 | UINT64_C(3556769793), // SVC |
| 6207 | UINT64_C(3243245600), // SVDOT_VG2_M2ZZI_HtoS |
| 6208 | UINT64_C(3243278368), // SVDOT_VG4_M4ZZI_BtoS |
| 6209 | UINT64_C(3251669000), // SVDOT_VG4_M4ZZI_HtoD |
| 6210 | UINT64_C(950042624), // SWPAB |
| 6211 | UINT64_C(2023784448), // SWPAH |
| 6212 | UINT64_C(954236928), // SWPALB |
| 6213 | UINT64_C(2027978752), // SWPALH |
| 6214 | UINT64_C(3101720576), // SWPALW |
| 6215 | UINT64_C(4175462400), // SWPALX |
| 6216 | UINT64_C(3097526272), // SWPAW |
| 6217 | UINT64_C(4171268096), // SWPAX |
| 6218 | UINT64_C(941654016), // SWPB |
| 6219 | UINT64_C(2015395840), // SWPH |
| 6220 | UINT64_C(945848320), // SWPLB |
| 6221 | UINT64_C(2019590144), // SWPLH |
| 6222 | UINT64_C(3093331968), // SWPLW |
| 6223 | UINT64_C(4167073792), // SWPLX |
| 6224 | UINT64_C(421560320), // SWPP |
| 6225 | UINT64_C(429948928), // SWPPA |
| 6226 | UINT64_C(434143232), // SWPPAL |
| 6227 | UINT64_C(425754624), // SWPPL |
| 6228 | UINT64_C(434144256), // SWPTALW |
| 6229 | UINT64_C(1507886080), // SWPTALX |
| 6230 | UINT64_C(429949952), // SWPTAW |
| 6231 | UINT64_C(1503691776), // SWPTAX |
| 6232 | UINT64_C(425755648), // SWPTLW |
| 6233 | UINT64_C(1499497472), // SWPTLX |
| 6234 | UINT64_C(421561344), // SWPTW |
| 6235 | UINT64_C(1495303168), // SWPTX |
| 6236 | UINT64_C(3089137664), // SWPW |
| 6237 | UINT64_C(4162879488), // SWPX |
| 6238 | UINT64_C(80781312), // SXTB_ZPmZ_D |
| 6239 | UINT64_C(72392704), // SXTB_ZPmZ_H |
| 6240 | UINT64_C(76587008), // SXTB_ZPmZ_S |
| 6241 | UINT64_C(79732736), // SXTB_ZPzZ_D |
| 6242 | UINT64_C(71344128), // SXTB_ZPzZ_H |
| 6243 | UINT64_C(75538432), // SXTB_ZPzZ_S |
| 6244 | UINT64_C(80912384), // SXTH_ZPmZ_D |
| 6245 | UINT64_C(76718080), // SXTH_ZPmZ_S |
| 6246 | UINT64_C(79863808), // SXTH_ZPzZ_D |
| 6247 | UINT64_C(75669504), // SXTH_ZPzZ_S |
| 6248 | UINT64_C(81043456), // SXTW_ZPmZ_D |
| 6249 | UINT64_C(79994880), // SXTW_ZPzZ_D |
| 6250 | UINT64_C(3576168448), // SYSLxt |
| 6251 | UINT64_C(3578265600), // SYSPxt |
| 6252 | UINT64_C(3578265631), // SYSPxt_XZR |
| 6253 | UINT64_C(3574071296), // SYSxt |
| 6254 | UINT64_C(1140914176), // TBLQ_ZZZ_B |
| 6255 | UINT64_C(1153497088), // TBLQ_ZZZ_D |
| 6256 | UINT64_C(1145108480), // TBLQ_ZZZ_H |
| 6257 | UINT64_C(1149302784), // TBLQ_ZZZ_S |
| 6258 | UINT64_C(85993472), // TBL_ZZZZ_B |
| 6259 | UINT64_C(98576384), // TBL_ZZZZ_D |
| 6260 | UINT64_C(90187776), // TBL_ZZZZ_H |
| 6261 | UINT64_C(94382080), // TBL_ZZZZ_S |
| 6262 | UINT64_C(85995520), // TBL_ZZZ_B |
| 6263 | UINT64_C(98578432), // TBL_ZZZ_D |
| 6264 | UINT64_C(90189824), // TBL_ZZZ_H |
| 6265 | UINT64_C(94384128), // TBL_ZZZ_S |
| 6266 | UINT64_C(1308647424), // TBLv16i8Four |
| 6267 | UINT64_C(1308622848), // TBLv16i8One |
| 6268 | UINT64_C(1308639232), // TBLv16i8Three |
| 6269 | UINT64_C(1308631040), // TBLv16i8Two |
| 6270 | UINT64_C(234905600), // TBLv8i8Four |
| 6271 | UINT64_C(234881024), // TBLv8i8One |
| 6272 | UINT64_C(234897408), // TBLv8i8Three |
| 6273 | UINT64_C(234889216), // TBLv8i8Two |
| 6274 | UINT64_C(922746880), // TBNZW |
| 6275 | UINT64_C(3070230528), // TBNZX |
| 6276 | UINT64_C(85996544), // TBXQ_ZZZ_B |
| 6277 | UINT64_C(98579456), // TBXQ_ZZZ_D |
| 6278 | UINT64_C(90190848), // TBXQ_ZZZ_H |
| 6279 | UINT64_C(94385152), // TBXQ_ZZZ_S |
| 6280 | UINT64_C(85994496), // TBX_ZZZ_B |
| 6281 | UINT64_C(98577408), // TBX_ZZZ_D |
| 6282 | UINT64_C(90188800), // TBX_ZZZ_H |
| 6283 | UINT64_C(94383104), // TBX_ZZZ_S |
| 6284 | UINT64_C(1308651520), // TBXv16i8Four |
| 6285 | UINT64_C(1308626944), // TBXv16i8One |
| 6286 | UINT64_C(1308643328), // TBXv16i8Three |
| 6287 | UINT64_C(1308635136), // TBXv16i8Two |
| 6288 | UINT64_C(234909696), // TBXv8i8Four |
| 6289 | UINT64_C(234885120), // TBXv8i8One |
| 6290 | UINT64_C(234901504), // TBXv8i8Three |
| 6291 | UINT64_C(234893312), // TBXv8i8Two |
| 6292 | UINT64_C(905969664), // TBZW |
| 6293 | UINT64_C(3053453312), // TBZX |
| 6294 | UINT64_C(3583246336), // TCHANGEBri |
| 6295 | UINT64_C(3582197760), // TCHANGEBrr |
| 6296 | UINT64_C(3582984192), // TCHANGEFri |
| 6297 | UINT64_C(3581935616), // TCHANGEFrr |
| 6298 | UINT64_C(3571449856), // TENTER |
| 6299 | UINT64_C(3607036896), // TEXIT |
| 6300 | UINT64_C(1979712096), // TFLTNZ |
| 6301 | UINT64_C(1979712064), // TFLTZ |
| 6302 | UINT64_C(86003712), // TRN1_PPP_B |
| 6303 | UINT64_C(98586624), // TRN1_PPP_D |
| 6304 | UINT64_C(90198016), // TRN1_PPP_H |
| 6305 | UINT64_C(94392320), // TRN1_PPP_S |
| 6306 | UINT64_C(86011904), // TRN1_ZZZ_B |
| 6307 | UINT64_C(98594816), // TRN1_ZZZ_D |
| 6308 | UINT64_C(90206208), // TRN1_ZZZ_H |
| 6309 | UINT64_C(94377984), // TRN1_ZZZ_Q |
| 6310 | UINT64_C(94400512), // TRN1_ZZZ_S |
| 6311 | UINT64_C(1308633088), // TRN1v16i8 |
| 6312 | UINT64_C(243279872), // TRN1v2i32 |
| 6313 | UINT64_C(1321216000), // TRN1v2i64 |
| 6314 | UINT64_C(239085568), // TRN1v4i16 |
| 6315 | UINT64_C(1317021696), // TRN1v4i32 |
| 6316 | UINT64_C(1312827392), // TRN1v8i16 |
| 6317 | UINT64_C(234891264), // TRN1v8i8 |
| 6318 | UINT64_C(86004736), // TRN2_PPP_B |
| 6319 | UINT64_C(98587648), // TRN2_PPP_D |
| 6320 | UINT64_C(90199040), // TRN2_PPP_H |
| 6321 | UINT64_C(94393344), // TRN2_PPP_S |
| 6322 | UINT64_C(86012928), // TRN2_ZZZ_B |
| 6323 | UINT64_C(98595840), // TRN2_ZZZ_D |
| 6324 | UINT64_C(90207232), // TRN2_ZZZ_H |
| 6325 | UINT64_C(94379008), // TRN2_ZZZ_Q |
| 6326 | UINT64_C(94401536), // TRN2_ZZZ_S |
| 6327 | UINT64_C(1308649472), // TRN2v16i8 |
| 6328 | UINT64_C(243296256), // TRN2v2i32 |
| 6329 | UINT64_C(1321232384), // TRN2v2i64 |
| 6330 | UINT64_C(239101952), // TRN2v4i16 |
| 6331 | UINT64_C(1317038080), // TRN2v4i32 |
| 6332 | UINT64_C(1312843776), // TRN2v8i16 |
| 6333 | UINT64_C(234907648), // TRN2v8i8 |
| 6334 | UINT64_C(1170262016), // UABALB_ZZZ_D |
| 6335 | UINT64_C(1161873408), // UABALB_ZZZ_H |
| 6336 | UINT64_C(1166067712), // UABALB_ZZZ_S |
| 6337 | UINT64_C(1170263040), // UABALT_ZZZ_D |
| 6338 | UINT64_C(1161874432), // UABALT_ZZZ_H |
| 6339 | UINT64_C(1166068736), // UABALT_ZZZ_S |
| 6340 | UINT64_C(1145101312), // UABAL_ZZZ_BtoH |
| 6341 | UINT64_C(1149295616), // UABAL_ZZZ_HtoS |
| 6342 | UINT64_C(1153489920), // UABAL_ZZZ_StoD |
| 6343 | UINT64_C(1847611392), // UABALv16i8_v8i16 |
| 6344 | UINT64_C(782258176), // UABALv2i32_v2i64 |
| 6345 | UINT64_C(778063872), // UABALv4i16_v4i32 |
| 6346 | UINT64_C(1856000000), // UABALv4i32_v2i64 |
| 6347 | UINT64_C(1851805696), // UABALv8i16_v4i32 |
| 6348 | UINT64_C(773869568), // UABALv8i8_v8i16 |
| 6349 | UINT64_C(1157692416), // UABA_ZZZ_B |
| 6350 | UINT64_C(1170275328), // UABA_ZZZ_D |
| 6351 | UINT64_C(1161886720), // UABA_ZZZ_H |
| 6352 | UINT64_C(1166081024), // UABA_ZZZ_S |
| 6353 | UINT64_C(1847622656), // UABAv16i8 |
| 6354 | UINT64_C(782269440), // UABAv2i32 |
| 6355 | UINT64_C(778075136), // UABAv4i16 |
| 6356 | UINT64_C(1856011264), // UABAv4i32 |
| 6357 | UINT64_C(1851816960), // UABAv8i16 |
| 6358 | UINT64_C(773880832), // UABAv8i8 |
| 6359 | UINT64_C(1170225152), // UABDLB_ZZZ_D |
| 6360 | UINT64_C(1161836544), // UABDLB_ZZZ_H |
| 6361 | UINT64_C(1166030848), // UABDLB_ZZZ_S |
| 6362 | UINT64_C(1170226176), // UABDLT_ZZZ_D |
| 6363 | UINT64_C(1161837568), // UABDLT_ZZZ_H |
| 6364 | UINT64_C(1166031872), // UABDLT_ZZZ_S |
| 6365 | UINT64_C(1847619584), // UABDLv16i8_v8i16 |
| 6366 | UINT64_C(782266368), // UABDLv2i32_v2i64 |
| 6367 | UINT64_C(778072064), // UABDLv4i16_v4i32 |
| 6368 | UINT64_C(1856008192), // UABDLv4i32_v2i64 |
| 6369 | UINT64_C(1851813888), // UABDLv8i16_v4i32 |
| 6370 | UINT64_C(773877760), // UABDLv8i8_v8i16 |
| 6371 | UINT64_C(67960832), // UABD_ZPmZ_B |
| 6372 | UINT64_C(80543744), // UABD_ZPmZ_D |
| 6373 | UINT64_C(72155136), // UABD_ZPmZ_H |
| 6374 | UINT64_C(76349440), // UABD_ZPmZ_S |
| 6375 | UINT64_C(1847620608), // UABDv16i8 |
| 6376 | UINT64_C(782267392), // UABDv2i32 |
| 6377 | UINT64_C(778073088), // UABDv4i16 |
| 6378 | UINT64_C(1856009216), // UABDv4i32 |
| 6379 | UINT64_C(1851814912), // UABDv8i16 |
| 6380 | UINT64_C(773878784), // UABDv8i8 |
| 6381 | UINT64_C(1153802240), // UADALP_ZPmZ_D |
| 6382 | UINT64_C(1145413632), // UADALP_ZPmZ_H |
| 6383 | UINT64_C(1149607936), // UADALP_ZPmZ_S |
| 6384 | UINT64_C(1847617536), // UADALPv16i8_v8i16 |
| 6385 | UINT64_C(782264320), // UADALPv2i32_v1i64 |
| 6386 | UINT64_C(778070016), // UADALPv4i16_v2i32 |
| 6387 | UINT64_C(1856006144), // UADALPv4i32_v2i64 |
| 6388 | UINT64_C(1851811840), // UADALPv8i16_v4i32 |
| 6389 | UINT64_C(773875712), // UADALPv8i8_v4i16 |
| 6390 | UINT64_C(1170212864), // UADDLB_ZZZ_D |
| 6391 | UINT64_C(1161824256), // UADDLB_ZZZ_H |
| 6392 | UINT64_C(1166018560), // UADDLB_ZZZ_S |
| 6393 | UINT64_C(1847601152), // UADDLPv16i8_v8i16 |
| 6394 | UINT64_C(782247936), // UADDLPv2i32_v1i64 |
| 6395 | UINT64_C(778053632), // UADDLPv4i16_v2i32 |
| 6396 | UINT64_C(1855989760), // UADDLPv4i32_v2i64 |
| 6397 | UINT64_C(1851795456), // UADDLPv8i16_v4i32 |
| 6398 | UINT64_C(773859328), // UADDLPv8i8_v4i16 |
| 6399 | UINT64_C(1170213888), // UADDLT_ZZZ_D |
| 6400 | UINT64_C(1161825280), // UADDLT_ZZZ_H |
| 6401 | UINT64_C(1166019584), // UADDLT_ZZZ_S |
| 6402 | UINT64_C(1848653824), // UADDLVv16i8v |
| 6403 | UINT64_C(779106304), // UADDLVv4i16v |
| 6404 | UINT64_C(1857042432), // UADDLVv4i32v |
| 6405 | UINT64_C(1852848128), // UADDLVv8i16v |
| 6406 | UINT64_C(774912000), // UADDLVv8i8v |
| 6407 | UINT64_C(1847590912), // UADDLv16i8_v8i16 |
| 6408 | UINT64_C(782237696), // UADDLv2i32_v2i64 |
| 6409 | UINT64_C(778043392), // UADDLv4i16_v4i32 |
| 6410 | UINT64_C(1855979520), // UADDLv4i32_v2i64 |
| 6411 | UINT64_C(1851785216), // UADDLv8i16_v4i32 |
| 6412 | UINT64_C(773849088), // UADDLv8i8_v8i16 |
| 6413 | UINT64_C(67182592), // UADDV_VPZ_B |
| 6414 | UINT64_C(79765504), // UADDV_VPZ_D |
| 6415 | UINT64_C(71376896), // UADDV_VPZ_H |
| 6416 | UINT64_C(75571200), // UADDV_VPZ_S |
| 6417 | UINT64_C(1170229248), // UADDWB_ZZZ_D |
| 6418 | UINT64_C(1161840640), // UADDWB_ZZZ_H |
| 6419 | UINT64_C(1166034944), // UADDWB_ZZZ_S |
| 6420 | UINT64_C(1170230272), // UADDWT_ZZZ_D |
| 6421 | UINT64_C(1161841664), // UADDWT_ZZZ_H |
| 6422 | UINT64_C(1166035968), // UADDWT_ZZZ_S |
| 6423 | UINT64_C(1847595008), // UADDWv16i8_v8i16 |
| 6424 | UINT64_C(782241792), // UADDWv2i32_v2i64 |
| 6425 | UINT64_C(778047488), // UADDWv4i16_v4i32 |
| 6426 | UINT64_C(1855983616), // UADDWv4i32_v2i64 |
| 6427 | UINT64_C(1851789312), // UADDWv8i16_v4i32 |
| 6428 | UINT64_C(773853184), // UADDWv8i8_v8i16 |
| 6429 | UINT64_C(1392508928), // UBFMWri |
| 6430 | UINT64_C(3544186880), // UBFMXri |
| 6431 | UINT64_C(3240150017), // UCLAMP_VG2_2Z2Z_B |
| 6432 | UINT64_C(3252732929), // UCLAMP_VG2_2Z2Z_D |
| 6433 | UINT64_C(3244344321), // UCLAMP_VG2_2Z2Z_H |
| 6434 | UINT64_C(3248538625), // UCLAMP_VG2_2Z2Z_S |
| 6435 | UINT64_C(3240152065), // UCLAMP_VG4_4Z4Z_B |
| 6436 | UINT64_C(3252734977), // UCLAMP_VG4_4Z4Z_D |
| 6437 | UINT64_C(3244346369), // UCLAMP_VG4_4Z4Z_H |
| 6438 | UINT64_C(3248540673), // UCLAMP_VG4_4Z4Z_S |
| 6439 | UINT64_C(1140900864), // UCLAMP_ZZZ_B |
| 6440 | UINT64_C(1153483776), // UCLAMP_ZZZ_D |
| 6441 | UINT64_C(1145095168), // UCLAMP_ZZZ_H |
| 6442 | UINT64_C(1149289472), // UCLAMP_ZZZ_S |
| 6443 | UINT64_C(511508480), // UCVTFDSr |
| 6444 | UINT64_C(2667380736), // UCVTFHDr |
| 6445 | UINT64_C(519897088), // UCVTFHSr |
| 6446 | UINT64_C(1699494912), // UCVTFLT_ZZ_BtoH |
| 6447 | UINT64_C(1703689216), // UCVTFLT_ZZ_HtoS |
| 6448 | UINT64_C(1707883520), // UCVTFLT_ZZ_StoD |
| 6449 | UINT64_C(2654797824), // UCVTFSDr |
| 6450 | UINT64_C(507740160), // UCVTFSWDri |
| 6451 | UINT64_C(516128768), // UCVTFSWHri |
| 6452 | UINT64_C(503545856), // UCVTFSWSri |
| 6453 | UINT64_C(2655191040), // UCVTFSXDri |
| 6454 | UINT64_C(2663579648), // UCVTFSXHri |
| 6455 | UINT64_C(2650996736), // UCVTFSXSri |
| 6456 | UINT64_C(509804544), // UCVTFUWDri |
| 6457 | UINT64_C(518193152), // UCVTFUWHri |
| 6458 | UINT64_C(505610240), // UCVTFUWSri |
| 6459 | UINT64_C(2657288192), // UCVTFUXDri |
| 6460 | UINT64_C(2665676800), // UCVTFUXHri |
| 6461 | UINT64_C(2653093888), // UCVTFUXSri |
| 6462 | UINT64_C(3240288288), // UCVTF_2Z2Z_StoS |
| 6463 | UINT64_C(3241336864), // UCVTF_4Z4Z_StoS |
| 6464 | UINT64_C(1708630016), // UCVTF_ZPmZ_DtoD |
| 6465 | UINT64_C(1700241408), // UCVTF_ZPmZ_DtoH |
| 6466 | UINT64_C(1708498944), // UCVTF_ZPmZ_DtoS |
| 6467 | UINT64_C(1699979264), // UCVTF_ZPmZ_HtoH |
| 6468 | UINT64_C(1708236800), // UCVTF_ZPmZ_StoD |
| 6469 | UINT64_C(1700110336), // UCVTF_ZPmZ_StoH |
| 6470 | UINT64_C(1704304640), // UCVTF_ZPmZ_StoS |
| 6471 | UINT64_C(1692262400), // UCVTF_ZPzZ_DtoD |
| 6472 | UINT64_C(1683873792), // UCVTF_ZPzZ_DtoH |
| 6473 | UINT64_C(1692246016), // UCVTF_ZPzZ_DtoS |
| 6474 | UINT64_C(1683808256), // UCVTF_ZPzZ_HtoH |
| 6475 | UINT64_C(1692180480), // UCVTF_ZPzZ_StoD |
| 6476 | UINT64_C(1683857408), // UCVTF_ZPzZ_StoH |
| 6477 | UINT64_C(1688051712), // UCVTF_ZPzZ_StoS |
| 6478 | UINT64_C(1699492864), // UCVTF_ZZ_BtoH |
| 6479 | UINT64_C(1703687168), // UCVTF_ZZ_HtoS |
| 6480 | UINT64_C(1707881472), // UCVTF_ZZ_StoD |
| 6481 | UINT64_C(2134959104), // UCVTFd |
| 6482 | UINT64_C(2131813376), // UCVTFh |
| 6483 | UINT64_C(2132861952), // UCVTFs |
| 6484 | UINT64_C(2121914368), // UCVTFv1i16 |
| 6485 | UINT64_C(2116147200), // UCVTFv1i32 |
| 6486 | UINT64_C(2120341504), // UCVTFv1i64 |
| 6487 | UINT64_C(773969920), // UCVTFv2f32 |
| 6488 | UINT64_C(1851906048), // UCVTFv2f64 |
| 6489 | UINT64_C(790684672), // UCVTFv2i32_shift |
| 6490 | UINT64_C(1866523648), // UCVTFv2i64_shift |
| 6491 | UINT64_C(779737088), // UCVTFv4f16 |
| 6492 | UINT64_C(1847711744), // UCVTFv4f32 |
| 6493 | UINT64_C(789636096), // UCVTFv4i16_shift |
| 6494 | UINT64_C(1864426496), // UCVTFv4i32_shift |
| 6495 | UINT64_C(1853478912), // UCVTFv8f16 |
| 6496 | UINT64_C(1863377920), // UCVTFv8i16_shift |
| 6497 | UINT64_C(0), // UDF |
| 6498 | UINT64_C(81199104), // UDIVR_ZPmZ_D |
| 6499 | UINT64_C(77004800), // UDIVR_ZPmZ_S |
| 6500 | UINT64_C(448792576), // UDIVWr |
| 6501 | UINT64_C(2596276224), // UDIVXr |
| 6502 | UINT64_C(81068032), // UDIV_ZPmZ_D |
| 6503 | UINT64_C(76873728), // UDIV_ZPmZ_S |
| 6504 | UINT64_C(3248493584), // UDOT_VG2_M2Z2Z_BtoS |
| 6505 | UINT64_C(3252687888), // UDOT_VG2_M2Z2Z_HtoD |
| 6506 | UINT64_C(3252687896), // UDOT_VG2_M2Z2Z_HtoS |
| 6507 | UINT64_C(3243249712), // UDOT_VG2_M2ZZI_BToS |
| 6508 | UINT64_C(3243249680), // UDOT_VG2_M2ZZI_HToS |
| 6509 | UINT64_C(3251634200), // UDOT_VG2_M2ZZI_HtoD |
| 6510 | UINT64_C(3240104976), // UDOT_VG2_M2ZZ_BtoS |
| 6511 | UINT64_C(3244299280), // UDOT_VG2_M2ZZ_HtoD |
| 6512 | UINT64_C(3244299288), // UDOT_VG2_M2ZZ_HtoS |
| 6513 | UINT64_C(3248559120), // UDOT_VG4_M4Z4Z_BtoS |
| 6514 | UINT64_C(3252753424), // UDOT_VG4_M4Z4Z_HtoD |
| 6515 | UINT64_C(3252753432), // UDOT_VG4_M4Z4Z_HtoS |
| 6516 | UINT64_C(3243282480), // UDOT_VG4_M4ZZI_BtoS |
| 6517 | UINT64_C(3243282448), // UDOT_VG4_M4ZZI_HToS |
| 6518 | UINT64_C(3251666968), // UDOT_VG4_M4ZZI_HtoD |
| 6519 | UINT64_C(3241153552), // UDOT_VG4_M4ZZ_BtoS |
| 6520 | UINT64_C(3245347856), // UDOT_VG4_M4ZZ_HtoD |
| 6521 | UINT64_C(3245347864), // UDOT_VG4_M4ZZ_HtoS |
| 6522 | UINT64_C(1142948864), // UDOT_ZZZI_BtoH |
| 6523 | UINT64_C(1151337472), // UDOT_ZZZI_BtoS |
| 6524 | UINT64_C(1155531776), // UDOT_ZZZI_HtoD |
| 6525 | UINT64_C(1149291520), // UDOT_ZZZI_HtoS |
| 6526 | UINT64_C(1145046016), // UDOT_ZZZ_BtoH |
| 6527 | UINT64_C(1149240320), // UDOT_ZZZ_BtoS |
| 6528 | UINT64_C(1153434624), // UDOT_ZZZ_HtoD |
| 6529 | UINT64_C(1140902912), // UDOT_ZZZ_HtoS |
| 6530 | UINT64_C(1870716928), // UDOTlanev16i8 |
| 6531 | UINT64_C(796975104), // UDOTlanev8i8 |
| 6532 | UINT64_C(1853920256), // UDOTv16i8 |
| 6533 | UINT64_C(780178432), // UDOTv8i8 |
| 6534 | UINT64_C(1141997568), // UHADD_ZPmZ_B |
| 6535 | UINT64_C(1154580480), // UHADD_ZPmZ_D |
| 6536 | UINT64_C(1146191872), // UHADD_ZPmZ_H |
| 6537 | UINT64_C(1150386176), // UHADD_ZPmZ_S |
| 6538 | UINT64_C(1847591936), // UHADDv16i8 |
| 6539 | UINT64_C(782238720), // UHADDv2i32 |
| 6540 | UINT64_C(778044416), // UHADDv4i16 |
| 6541 | UINT64_C(1855980544), // UHADDv4i32 |
| 6542 | UINT64_C(1851786240), // UHADDv8i16 |
| 6543 | UINT64_C(773850112), // UHADDv8i8 |
| 6544 | UINT64_C(1142390784), // UHSUBR_ZPmZ_B |
| 6545 | UINT64_C(1154973696), // UHSUBR_ZPmZ_D |
| 6546 | UINT64_C(1146585088), // UHSUBR_ZPmZ_H |
| 6547 | UINT64_C(1150779392), // UHSUBR_ZPmZ_S |
| 6548 | UINT64_C(1142128640), // UHSUB_ZPmZ_B |
| 6549 | UINT64_C(1154711552), // UHSUB_ZPmZ_D |
| 6550 | UINT64_C(1146322944), // UHSUB_ZPmZ_H |
| 6551 | UINT64_C(1150517248), // UHSUB_ZPmZ_S |
| 6552 | UINT64_C(1847600128), // UHSUBv16i8 |
| 6553 | UINT64_C(782246912), // UHSUBv2i32 |
| 6554 | UINT64_C(778052608), // UHSUBv4i16 |
| 6555 | UINT64_C(1855988736), // UHSUBv4i32 |
| 6556 | UINT64_C(1851794432), // UHSUBv8i16 |
| 6557 | UINT64_C(773858304), // UHSUBv8i8 |
| 6558 | UINT64_C(2610954240), // UMADDLrrr |
| 6559 | UINT64_C(1142267904), // UMAXP_ZPmZ_B |
| 6560 | UINT64_C(1154850816), // UMAXP_ZPmZ_D |
| 6561 | UINT64_C(1146462208), // UMAXP_ZPmZ_H |
| 6562 | UINT64_C(1150656512), // UMAXP_ZPmZ_S |
| 6563 | UINT64_C(1847632896), // UMAXPv16i8 |
| 6564 | UINT64_C(782279680), // UMAXPv2i32 |
| 6565 | UINT64_C(778085376), // UMAXPv4i16 |
| 6566 | UINT64_C(1856021504), // UMAXPv4i32 |
| 6567 | UINT64_C(1851827200), // UMAXPv8i16 |
| 6568 | UINT64_C(773891072), // UMAXPv8i8 |
| 6569 | UINT64_C(67969024), // UMAXQV_VPZ_B |
| 6570 | UINT64_C(80551936), // UMAXQV_VPZ_D |
| 6571 | UINT64_C(72163328), // UMAXQV_VPZ_H |
| 6572 | UINT64_C(76357632), // UMAXQV_VPZ_S |
| 6573 | UINT64_C(67706880), // UMAXV_VPZ_B |
| 6574 | UINT64_C(80289792), // UMAXV_VPZ_D |
| 6575 | UINT64_C(71901184), // UMAXV_VPZ_H |
| 6576 | UINT64_C(76095488), // UMAXV_VPZ_S |
| 6577 | UINT64_C(1848682496), // UMAXVv16i8v |
| 6578 | UINT64_C(779134976), // UMAXVv4i16v |
| 6579 | UINT64_C(1857071104), // UMAXVv4i32v |
| 6580 | UINT64_C(1852876800), // UMAXVv8i16v |
| 6581 | UINT64_C(774940672), // UMAXVv8i8v |
| 6582 | UINT64_C(298057728), // UMAXWri |
| 6583 | UINT64_C(448816128), // UMAXWrr |
| 6584 | UINT64_C(2445541376), // UMAXXri |
| 6585 | UINT64_C(2596299776), // UMAXXrr |
| 6586 | UINT64_C(3240144897), // UMAX_VG2_2Z2Z_B |
| 6587 | UINT64_C(3252727809), // UMAX_VG2_2Z2Z_D |
| 6588 | UINT64_C(3244339201), // UMAX_VG2_2Z2Z_H |
| 6589 | UINT64_C(3248533505), // UMAX_VG2_2Z2Z_S |
| 6590 | UINT64_C(3240140801), // UMAX_VG2_2ZZ_B |
| 6591 | UINT64_C(3252723713), // UMAX_VG2_2ZZ_D |
| 6592 | UINT64_C(3244335105), // UMAX_VG2_2ZZ_H |
| 6593 | UINT64_C(3248529409), // UMAX_VG2_2ZZ_S |
| 6594 | UINT64_C(3240146945), // UMAX_VG4_4Z4Z_B |
| 6595 | UINT64_C(3252729857), // UMAX_VG4_4Z4Z_D |
| 6596 | UINT64_C(3244341249), // UMAX_VG4_4Z4Z_H |
| 6597 | UINT64_C(3248535553), // UMAX_VG4_4Z4Z_S |
| 6598 | UINT64_C(3240142849), // UMAX_VG4_4ZZ_B |
| 6599 | UINT64_C(3252725761), // UMAX_VG4_4ZZ_D |
| 6600 | UINT64_C(3244337153), // UMAX_VG4_4ZZ_H |
| 6601 | UINT64_C(3248531457), // UMAX_VG4_4ZZ_S |
| 6602 | UINT64_C(623493120), // UMAX_ZI_B |
| 6603 | UINT64_C(636076032), // UMAX_ZI_D |
| 6604 | UINT64_C(627687424), // UMAX_ZI_H |
| 6605 | UINT64_C(631881728), // UMAX_ZI_S |
| 6606 | UINT64_C(67698688), // UMAX_ZPmZ_B |
| 6607 | UINT64_C(80281600), // UMAX_ZPmZ_D |
| 6608 | UINT64_C(71892992), // UMAX_ZPmZ_H |
| 6609 | UINT64_C(76087296), // UMAX_ZPmZ_S |
| 6610 | UINT64_C(1847616512), // UMAXv16i8 |
| 6611 | UINT64_C(782263296), // UMAXv2i32 |
| 6612 | UINT64_C(778068992), // UMAXv4i16 |
| 6613 | UINT64_C(1856005120), // UMAXv4i32 |
| 6614 | UINT64_C(1851810816), // UMAXv8i16 |
| 6615 | UINT64_C(773874688), // UMAXv8i8 |
| 6616 | UINT64_C(1142398976), // UMINP_ZPmZ_B |
| 6617 | UINT64_C(1154981888), // UMINP_ZPmZ_D |
| 6618 | UINT64_C(1146593280), // UMINP_ZPmZ_H |
| 6619 | UINT64_C(1150787584), // UMINP_ZPmZ_S |
| 6620 | UINT64_C(1847634944), // UMINPv16i8 |
| 6621 | UINT64_C(782281728), // UMINPv2i32 |
| 6622 | UINT64_C(778087424), // UMINPv4i16 |
| 6623 | UINT64_C(1856023552), // UMINPv4i32 |
| 6624 | UINT64_C(1851829248), // UMINPv8i16 |
| 6625 | UINT64_C(773893120), // UMINPv8i8 |
| 6626 | UINT64_C(68100096), // UMINQV_VPZ_B |
| 6627 | UINT64_C(80683008), // UMINQV_VPZ_D |
| 6628 | UINT64_C(72294400), // UMINQV_VPZ_H |
| 6629 | UINT64_C(76488704), // UMINQV_VPZ_S |
| 6630 | UINT64_C(67837952), // UMINV_VPZ_B |
| 6631 | UINT64_C(80420864), // UMINV_VPZ_D |
| 6632 | UINT64_C(72032256), // UMINV_VPZ_H |
| 6633 | UINT64_C(76226560), // UMINV_VPZ_S |
| 6634 | UINT64_C(1848748032), // UMINVv16i8v |
| 6635 | UINT64_C(779200512), // UMINVv4i16v |
| 6636 | UINT64_C(1857136640), // UMINVv4i32v |
| 6637 | UINT64_C(1852942336), // UMINVv8i16v |
| 6638 | UINT64_C(775006208), // UMINVv8i8v |
| 6639 | UINT64_C(298582016), // UMINWri |
| 6640 | UINT64_C(448818176), // UMINWrr |
| 6641 | UINT64_C(2446065664), // UMINXri |
| 6642 | UINT64_C(2596301824), // UMINXrr |
| 6643 | UINT64_C(3240144929), // UMIN_VG2_2Z2Z_B |
| 6644 | UINT64_C(3252727841), // UMIN_VG2_2Z2Z_D |
| 6645 | UINT64_C(3244339233), // UMIN_VG2_2Z2Z_H |
| 6646 | UINT64_C(3248533537), // UMIN_VG2_2Z2Z_S |
| 6647 | UINT64_C(3240140833), // UMIN_VG2_2ZZ_B |
| 6648 | UINT64_C(3252723745), // UMIN_VG2_2ZZ_D |
| 6649 | UINT64_C(3244335137), // UMIN_VG2_2ZZ_H |
| 6650 | UINT64_C(3248529441), // UMIN_VG2_2ZZ_S |
| 6651 | UINT64_C(3240146977), // UMIN_VG4_4Z4Z_B |
| 6652 | UINT64_C(3252729889), // UMIN_VG4_4Z4Z_D |
| 6653 | UINT64_C(3244341281), // UMIN_VG4_4Z4Z_H |
| 6654 | UINT64_C(3248535585), // UMIN_VG4_4Z4Z_S |
| 6655 | UINT64_C(3240142881), // UMIN_VG4_4ZZ_B |
| 6656 | UINT64_C(3252725793), // UMIN_VG4_4ZZ_D |
| 6657 | UINT64_C(3244337185), // UMIN_VG4_4ZZ_H |
| 6658 | UINT64_C(3248531489), // UMIN_VG4_4ZZ_S |
| 6659 | UINT64_C(623624192), // UMIN_ZI_B |
| 6660 | UINT64_C(636207104), // UMIN_ZI_D |
| 6661 | UINT64_C(627818496), // UMIN_ZI_H |
| 6662 | UINT64_C(632012800), // UMIN_ZI_S |
| 6663 | UINT64_C(67829760), // UMIN_ZPmZ_B |
| 6664 | UINT64_C(80412672), // UMIN_ZPmZ_D |
| 6665 | UINT64_C(72024064), // UMIN_ZPmZ_H |
| 6666 | UINT64_C(76218368), // UMIN_ZPmZ_S |
| 6667 | UINT64_C(1847618560), // UMINv16i8 |
| 6668 | UINT64_C(782265344), // UMINv2i32 |
| 6669 | UINT64_C(778071040), // UMINv4i16 |
| 6670 | UINT64_C(1856007168), // UMINv4i32 |
| 6671 | UINT64_C(1851812864), // UMINv8i16 |
| 6672 | UINT64_C(773876736), // UMINv8i8 |
| 6673 | UINT64_C(1155567616), // UMLALB_ZZZI_D |
| 6674 | UINT64_C(1151373312), // UMLALB_ZZZI_S |
| 6675 | UINT64_C(1153452032), // UMLALB_ZZZ_D |
| 6676 | UINT64_C(1145063424), // UMLALB_ZZZ_H |
| 6677 | UINT64_C(1149257728), // UMLALB_ZZZ_S |
| 6678 | UINT64_C(3238002704), // UMLALL_MZZI_BtoS |
| 6679 | UINT64_C(3246391312), // UMLALL_MZZI_HtoD |
| 6680 | UINT64_C(3240100880), // UMLALL_MZZ_BtoS |
| 6681 | UINT64_C(3244295184), // UMLALL_MZZ_HtoD |
| 6682 | UINT64_C(3248488464), // UMLALL_VG2_M2Z2Z_BtoS |
| 6683 | UINT64_C(3252682768), // UMLALL_VG2_M2Z2Z_HtoD |
| 6684 | UINT64_C(3239051280), // UMLALL_VG2_M2ZZI_BtoS |
| 6685 | UINT64_C(3247439888), // UMLALL_VG2_M2ZZI_HtoD |
| 6686 | UINT64_C(3240099856), // UMLALL_VG2_M2ZZ_BtoS |
| 6687 | UINT64_C(3244294160), // UMLALL_VG2_M2ZZ_HtoD |
| 6688 | UINT64_C(3248554000), // UMLALL_VG4_M4Z4Z_BtoS |
| 6689 | UINT64_C(3252748304), // UMLALL_VG4_M4Z4Z_HtoD |
| 6690 | UINT64_C(3239084048), // UMLALL_VG4_M4ZZI_BtoS |
| 6691 | UINT64_C(3247472656), // UMLALL_VG4_M4ZZI_HtoD |
| 6692 | UINT64_C(3241148432), // UMLALL_VG4_M4ZZ_BtoS |
| 6693 | UINT64_C(3245342736), // UMLALL_VG4_M4ZZ_HtoD |
| 6694 | UINT64_C(1155568640), // UMLALT_ZZZI_D |
| 6695 | UINT64_C(1151374336), // UMLALT_ZZZI_S |
| 6696 | UINT64_C(1153453056), // UMLALT_ZZZ_D |
| 6697 | UINT64_C(1145064448), // UMLALT_ZZZ_H |
| 6698 | UINT64_C(1149258752), // UMLALT_ZZZ_S |
| 6699 | UINT64_C(3250589712), // UMLAL_MZZI_HtoS |
| 6700 | UINT64_C(3244297232), // UMLAL_MZZ_HtoS |
| 6701 | UINT64_C(3252684816), // UMLAL_VG2_M2Z2Z_HtoS |
| 6702 | UINT64_C(3251638288), // UMLAL_VG2_M2ZZI_S |
| 6703 | UINT64_C(3244296208), // UMLAL_VG2_M2ZZ_HtoS |
| 6704 | UINT64_C(3252750352), // UMLAL_VG4_M4Z4Z_HtoS |
| 6705 | UINT64_C(3251671056), // UMLAL_VG4_M4ZZI_HtoS |
| 6706 | UINT64_C(3245344784), // UMLAL_VG4_M4ZZ_HtoS |
| 6707 | UINT64_C(1847623680), // UMLALv16i8_v8i16 |
| 6708 | UINT64_C(796925952), // UMLALv2i32_indexed |
| 6709 | UINT64_C(782270464), // UMLALv2i32_v2i64 |
| 6710 | UINT64_C(792731648), // UMLALv4i16_indexed |
| 6711 | UINT64_C(778076160), // UMLALv4i16_v4i32 |
| 6712 | UINT64_C(1870667776), // UMLALv4i32_indexed |
| 6713 | UINT64_C(1856012288), // UMLALv4i32_v2i64 |
| 6714 | UINT64_C(1866473472), // UMLALv8i16_indexed |
| 6715 | UINT64_C(1851817984), // UMLALv8i16_v4i32 |
| 6716 | UINT64_C(773881856), // UMLALv8i8_v8i16 |
| 6717 | UINT64_C(1155575808), // UMLSLB_ZZZI_D |
| 6718 | UINT64_C(1151381504), // UMLSLB_ZZZI_S |
| 6719 | UINT64_C(1153456128), // UMLSLB_ZZZ_D |
| 6720 | UINT64_C(1145067520), // UMLSLB_ZZZ_H |
| 6721 | UINT64_C(1149261824), // UMLSLB_ZZZ_S |
| 6722 | UINT64_C(3238002712), // UMLSLL_MZZI_BtoS |
| 6723 | UINT64_C(3246391320), // UMLSLL_MZZI_HtoD |
| 6724 | UINT64_C(3240100888), // UMLSLL_MZZ_BtoS |
| 6725 | UINT64_C(3244295192), // UMLSLL_MZZ_HtoD |
| 6726 | UINT64_C(3248488472), // UMLSLL_VG2_M2Z2Z_BtoS |
| 6727 | UINT64_C(3252682776), // UMLSLL_VG2_M2Z2Z_HtoD |
| 6728 | UINT64_C(3239051288), // UMLSLL_VG2_M2ZZI_BtoS |
| 6729 | UINT64_C(3247439896), // UMLSLL_VG2_M2ZZI_HtoD |
| 6730 | UINT64_C(3240099864), // UMLSLL_VG2_M2ZZ_BtoS |
| 6731 | UINT64_C(3244294168), // UMLSLL_VG2_M2ZZ_HtoD |
| 6732 | UINT64_C(3248554008), // UMLSLL_VG4_M4Z4Z_BtoS |
| 6733 | UINT64_C(3252748312), // UMLSLL_VG4_M4Z4Z_HtoD |
| 6734 | UINT64_C(3239084056), // UMLSLL_VG4_M4ZZI_BtoS |
| 6735 | UINT64_C(3247472664), // UMLSLL_VG4_M4ZZI_HtoD |
| 6736 | UINT64_C(3241148440), // UMLSLL_VG4_M4ZZ_BtoS |
| 6737 | UINT64_C(3245342744), // UMLSLL_VG4_M4ZZ_HtoD |
| 6738 | UINT64_C(1155576832), // UMLSLT_ZZZI_D |
| 6739 | UINT64_C(1151382528), // UMLSLT_ZZZI_S |
| 6740 | UINT64_C(1153457152), // UMLSLT_ZZZ_D |
| 6741 | UINT64_C(1145068544), // UMLSLT_ZZZ_H |
| 6742 | UINT64_C(1149262848), // UMLSLT_ZZZ_S |
| 6743 | UINT64_C(3250589720), // UMLSL_MZZI_HtoS |
| 6744 | UINT64_C(3244297240), // UMLSL_MZZ_HtoS |
| 6745 | UINT64_C(3252684824), // UMLSL_VG2_M2Z2Z_HtoS |
| 6746 | UINT64_C(3251638296), // UMLSL_VG2_M2ZZI_S |
| 6747 | UINT64_C(3244296216), // UMLSL_VG2_M2ZZ_HtoS |
| 6748 | UINT64_C(3252750360), // UMLSL_VG4_M4Z4Z_HtoS |
| 6749 | UINT64_C(3251671064), // UMLSL_VG4_M4ZZI_HtoS |
| 6750 | UINT64_C(3245344792), // UMLSL_VG4_M4ZZ_HtoS |
| 6751 | UINT64_C(1847631872), // UMLSLv16i8_v8i16 |
| 6752 | UINT64_C(796942336), // UMLSLv2i32_indexed |
| 6753 | UINT64_C(782278656), // UMLSLv2i32_v2i64 |
| 6754 | UINT64_C(792748032), // UMLSLv4i16_indexed |
| 6755 | UINT64_C(778084352), // UMLSLv4i16_v4i32 |
| 6756 | UINT64_C(1870684160), // UMLSLv4i32_indexed |
| 6757 | UINT64_C(1856020480), // UMLSLv4i32_v2i64 |
| 6758 | UINT64_C(1866489856), // UMLSLv8i16_indexed |
| 6759 | UINT64_C(1851826176), // UMLSLv8i16_v4i32 |
| 6760 | UINT64_C(773890048), // UMLSLv8i8_v8i16 |
| 6761 | UINT64_C(1853924352), // UMMLA |
| 6762 | UINT64_C(1170249728), // UMMLA_ZZZ |
| 6763 | UINT64_C(2167439872), // UMOP4A_M2Z2Z_BToS |
| 6764 | UINT64_C(2165342728), // UMOP4A_M2Z2Z_HToS |
| 6765 | UINT64_C(2716860936), // UMOP4A_M2Z2Z_HtoD |
| 6766 | UINT64_C(2166391296), // UMOP4A_M2ZZ_BToS |
| 6767 | UINT64_C(2164294152), // UMOP4A_M2ZZ_HToS |
| 6768 | UINT64_C(2715812360), // UMOP4A_M2ZZ_HtoD |
| 6769 | UINT64_C(2167439360), // UMOP4A_MZ2Z_BToS |
| 6770 | UINT64_C(2165342216), // UMOP4A_MZ2Z_HToS |
| 6771 | UINT64_C(2716860424), // UMOP4A_MZ2Z_HtoD |
| 6772 | UINT64_C(2166390784), // UMOP4A_MZZ_BToS |
| 6773 | UINT64_C(2164293640), // UMOP4A_MZZ_HToS |
| 6774 | UINT64_C(2715811848), // UMOP4A_MZZ_HtoD |
| 6775 | UINT64_C(2167439888), // UMOP4S_M2Z2Z_BToS |
| 6776 | UINT64_C(2165342744), // UMOP4S_M2Z2Z_HToS |
| 6777 | UINT64_C(2716860952), // UMOP4S_M2Z2Z_HtoD |
| 6778 | UINT64_C(2166391312), // UMOP4S_M2ZZ_BToS |
| 6779 | UINT64_C(2164294168), // UMOP4S_M2ZZ_HToS |
| 6780 | UINT64_C(2715812376), // UMOP4S_M2ZZ_HtoD |
| 6781 | UINT64_C(2167439376), // UMOP4S_MZ2Z_BToS |
| 6782 | UINT64_C(2165342232), // UMOP4S_MZ2Z_HToS |
| 6783 | UINT64_C(2716860440), // UMOP4S_MZ2Z_HtoD |
| 6784 | UINT64_C(2166390800), // UMOP4S_MZZ_BToS |
| 6785 | UINT64_C(2164293656), // UMOP4S_MZZ_HToS |
| 6786 | UINT64_C(2715811864), // UMOP4S_MZZ_HtoD |
| 6787 | UINT64_C(2715811840), // UMOPA_MPPZZ_D |
| 6788 | UINT64_C(2709520392), // UMOPA_MPPZZ_HtoS |
| 6789 | UINT64_C(2711617536), // UMOPA_MPPZZ_S |
| 6790 | UINT64_C(2715811856), // UMOPS_MPPZZ_D |
| 6791 | UINT64_C(2709520408), // UMOPS_MPPZZ_HtoS |
| 6792 | UINT64_C(2711617552), // UMOPS_MPPZZ_S |
| 6793 | UINT64_C(235027456), // UMOVvi16 |
| 6794 | UINT64_C(235027456), // UMOVvi16_idx0 |
| 6795 | UINT64_C(235158528), // UMOVvi32 |
| 6796 | UINT64_C(235158528), // UMOVvi32_idx0 |
| 6797 | UINT64_C(1309162496), // UMOVvi64 |
| 6798 | UINT64_C(1309162496), // UMOVvi64_idx0 |
| 6799 | UINT64_C(234961920), // UMOVvi8 |
| 6800 | UINT64_C(234961920), // UMOVvi8_idx0 |
| 6801 | UINT64_C(2610987008), // UMSUBLrrr |
| 6802 | UINT64_C(68354048), // UMULH_ZPmZ_B |
| 6803 | UINT64_C(80936960), // UMULH_ZPmZ_D |
| 6804 | UINT64_C(72548352), // UMULH_ZPmZ_H |
| 6805 | UINT64_C(76742656), // UMULH_ZPmZ_S |
| 6806 | UINT64_C(69233664), // UMULH_ZZZ_B |
| 6807 | UINT64_C(81816576), // UMULH_ZZZ_D |
| 6808 | UINT64_C(73427968), // UMULH_ZZZ_H |
| 6809 | UINT64_C(77622272), // UMULH_ZZZ_S |
| 6810 | UINT64_C(2613083136), // UMULHrr |
| 6811 | UINT64_C(1155584000), // UMULLB_ZZZI_D |
| 6812 | UINT64_C(1151389696), // UMULLB_ZZZI_S |
| 6813 | UINT64_C(1170241536), // UMULLB_ZZZ_D |
| 6814 | UINT64_C(1161852928), // UMULLB_ZZZ_H |
| 6815 | UINT64_C(1166047232), // UMULLB_ZZZ_S |
| 6816 | UINT64_C(1155585024), // UMULLT_ZZZI_D |
| 6817 | UINT64_C(1151390720), // UMULLT_ZZZI_S |
| 6818 | UINT64_C(1170242560), // UMULLT_ZZZ_D |
| 6819 | UINT64_C(1161853952), // UMULLT_ZZZ_H |
| 6820 | UINT64_C(1166048256), // UMULLT_ZZZ_S |
| 6821 | UINT64_C(1847640064), // UMULLv16i8_v8i16 |
| 6822 | UINT64_C(796958720), // UMULLv2i32_indexed |
| 6823 | UINT64_C(782286848), // UMULLv2i32_v2i64 |
| 6824 | UINT64_C(792764416), // UMULLv4i16_indexed |
| 6825 | UINT64_C(778092544), // UMULLv4i16_v4i32 |
| 6826 | UINT64_C(1870700544), // UMULLv4i32_indexed |
| 6827 | UINT64_C(1856028672), // UMULLv4i32_v2i64 |
| 6828 | UINT64_C(1866506240), // UMULLv8i16_indexed |
| 6829 | UINT64_C(1851834368), // UMULLv8i16_v4i32 |
| 6830 | UINT64_C(773898240), // UMULLv8i8_v8i16 |
| 6831 | UINT64_C(623230976), // UQADD_ZI_B |
| 6832 | UINT64_C(635813888), // UQADD_ZI_D |
| 6833 | UINT64_C(627425280), // UQADD_ZI_H |
| 6834 | UINT64_C(631619584), // UQADD_ZI_S |
| 6835 | UINT64_C(1142521856), // UQADD_ZPmZ_B |
| 6836 | UINT64_C(1155104768), // UQADD_ZPmZ_D |
| 6837 | UINT64_C(1146716160), // UQADD_ZPmZ_H |
| 6838 | UINT64_C(1150910464), // UQADD_ZPmZ_S |
| 6839 | UINT64_C(69211136), // UQADD_ZZZ_B |
| 6840 | UINT64_C(81794048), // UQADD_ZZZ_D |
| 6841 | UINT64_C(73405440), // UQADD_ZZZ_H |
| 6842 | UINT64_C(77599744), // UQADD_ZZZ_S |
| 6843 | UINT64_C(1847593984), // UQADDv16i8 |
| 6844 | UINT64_C(2120223744), // UQADDv1i16 |
| 6845 | UINT64_C(2124418048), // UQADDv1i32 |
| 6846 | UINT64_C(2128612352), // UQADDv1i64 |
| 6847 | UINT64_C(2116029440), // UQADDv1i8 |
| 6848 | UINT64_C(782240768), // UQADDv2i32 |
| 6849 | UINT64_C(1860176896), // UQADDv2i64 |
| 6850 | UINT64_C(778046464), // UQADDv4i16 |
| 6851 | UINT64_C(1855982592), // UQADDv4i32 |
| 6852 | UINT64_C(1851788288), // UQADDv8i16 |
| 6853 | UINT64_C(773852160), // UQADDv8i8 |
| 6854 | UINT64_C(1160857600), // UQCVTN_Z2Z_StoH |
| 6855 | UINT64_C(3249791072), // UQCVTN_Z4Z_DtoH |
| 6856 | UINT64_C(3241402464), // UQCVTN_Z4Z_StoB |
| 6857 | UINT64_C(3240353824), // UQCVT_Z2Z_StoH |
| 6858 | UINT64_C(3249791008), // UQCVT_Z4Z_DtoH |
| 6859 | UINT64_C(3241402400), // UQCVT_Z4Z_StoB |
| 6860 | UINT64_C(69270528), // UQDECB_WPiI |
| 6861 | UINT64_C(70319104), // UQDECB_XPiI |
| 6862 | UINT64_C(81853440), // UQDECD_WPiI |
| 6863 | UINT64_C(82902016), // UQDECD_XPiI |
| 6864 | UINT64_C(81841152), // UQDECD_ZPiI |
| 6865 | UINT64_C(73464832), // UQDECH_WPiI |
| 6866 | UINT64_C(74513408), // UQDECH_XPiI |
| 6867 | UINT64_C(73452544), // UQDECH_ZPiI |
| 6868 | UINT64_C(623609856), // UQDECP_WP_B |
| 6869 | UINT64_C(636192768), // UQDECP_WP_D |
| 6870 | UINT64_C(627804160), // UQDECP_WP_H |
| 6871 | UINT64_C(631998464), // UQDECP_WP_S |
| 6872 | UINT64_C(623610880), // UQDECP_XP_B |
| 6873 | UINT64_C(636193792), // UQDECP_XP_D |
| 6874 | UINT64_C(627805184), // UQDECP_XP_H |
| 6875 | UINT64_C(631999488), // UQDECP_XP_S |
| 6876 | UINT64_C(636190720), // UQDECP_ZP_D |
| 6877 | UINT64_C(627802112), // UQDECP_ZP_H |
| 6878 | UINT64_C(631996416), // UQDECP_ZP_S |
| 6879 | UINT64_C(77659136), // UQDECW_WPiI |
| 6880 | UINT64_C(78707712), // UQDECW_XPiI |
| 6881 | UINT64_C(77646848), // UQDECW_ZPiI |
| 6882 | UINT64_C(69268480), // UQINCB_WPiI |
| 6883 | UINT64_C(70317056), // UQINCB_XPiI |
| 6884 | UINT64_C(81851392), // UQINCD_WPiI |
| 6885 | UINT64_C(82899968), // UQINCD_XPiI |
| 6886 | UINT64_C(81839104), // UQINCD_ZPiI |
| 6887 | UINT64_C(73462784), // UQINCH_WPiI |
| 6888 | UINT64_C(74511360), // UQINCH_XPiI |
| 6889 | UINT64_C(73450496), // UQINCH_ZPiI |
| 6890 | UINT64_C(623478784), // UQINCP_WP_B |
| 6891 | UINT64_C(636061696), // UQINCP_WP_D |
| 6892 | UINT64_C(627673088), // UQINCP_WP_H |
| 6893 | UINT64_C(631867392), // UQINCP_WP_S |
| 6894 | UINT64_C(623479808), // UQINCP_XP_B |
| 6895 | UINT64_C(636062720), // UQINCP_XP_D |
| 6896 | UINT64_C(627674112), // UQINCP_XP_H |
| 6897 | UINT64_C(631868416), // UQINCP_XP_S |
| 6898 | UINT64_C(636059648), // UQINCP_ZP_D |
| 6899 | UINT64_C(627671040), // UQINCP_ZP_H |
| 6900 | UINT64_C(631865344), // UQINCP_ZP_S |
| 6901 | UINT64_C(77657088), // UQINCW_WPiI |
| 6902 | UINT64_C(78705664), // UQINCW_XPiI |
| 6903 | UINT64_C(77644800), // UQINCW_ZPiI |
| 6904 | UINT64_C(1141866496), // UQRSHLR_ZPmZ_B |
| 6905 | UINT64_C(1154449408), // UQRSHLR_ZPmZ_D |
| 6906 | UINT64_C(1146060800), // UQRSHLR_ZPmZ_H |
| 6907 | UINT64_C(1150255104), // UQRSHLR_ZPmZ_S |
| 6908 | UINT64_C(1141604352), // UQRSHL_ZPmZ_B |
| 6909 | UINT64_C(1154187264), // UQRSHL_ZPmZ_D |
| 6910 | UINT64_C(1145798656), // UQRSHL_ZPmZ_H |
| 6911 | UINT64_C(1149992960), // UQRSHL_ZPmZ_S |
| 6912 | UINT64_C(1847614464), // UQRSHLv16i8 |
| 6913 | UINT64_C(2120244224), // UQRSHLv1i16 |
| 6914 | UINT64_C(2124438528), // UQRSHLv1i32 |
| 6915 | UINT64_C(2128632832), // UQRSHLv1i64 |
| 6916 | UINT64_C(2116049920), // UQRSHLv1i8 |
| 6917 | UINT64_C(782261248), // UQRSHLv2i32 |
| 6918 | UINT64_C(1860197376), // UQRSHLv2i64 |
| 6919 | UINT64_C(778066944), // UQRSHLv4i16 |
| 6920 | UINT64_C(1856003072), // UQRSHLv4i32 |
| 6921 | UINT64_C(1851808768), // UQRSHLv8i16 |
| 6922 | UINT64_C(773872640), // UQRSHLv8i8 |
| 6923 | UINT64_C(1160263680), // UQRSHRNB_ZZI_B |
| 6924 | UINT64_C(1160787968), // UQRSHRNB_ZZI_H |
| 6925 | UINT64_C(1163933696), // UQRSHRNB_ZZI_S |
| 6926 | UINT64_C(1160264704), // UQRSHRNT_ZZI_B |
| 6927 | UINT64_C(1160788992), // UQRSHRNT_ZZI_H |
| 6928 | UINT64_C(1163934720), // UQRSHRNT_ZZI_S |
| 6929 | UINT64_C(3244350496), // UQRSHRN_VG4_Z4ZI_B |
| 6930 | UINT64_C(3248544800), // UQRSHRN_VG4_Z4ZI_H |
| 6931 | UINT64_C(1168652288), // UQRSHRN_Z2ZI_HtoB |
| 6932 | UINT64_C(1169176576), // UQRSHRN_Z2ZI_StoH |
| 6933 | UINT64_C(2131270656), // UQRSHRNb |
| 6934 | UINT64_C(2131794944), // UQRSHRNh |
| 6935 | UINT64_C(2132843520), // UQRSHRNs |
| 6936 | UINT64_C(1862835200), // UQRSHRNv16i8_shift |
| 6937 | UINT64_C(790666240), // UQRSHRNv2i32_shift |
| 6938 | UINT64_C(789617664), // UQRSHRNv4i16_shift |
| 6939 | UINT64_C(1864408064), // UQRSHRNv4i32_shift |
| 6940 | UINT64_C(1863359488), // UQRSHRNv8i16_shift |
| 6941 | UINT64_C(789093376), // UQRSHRNv8i8_shift |
| 6942 | UINT64_C(3252737056), // UQRSHR_VG2_Z2ZI_H |
| 6943 | UINT64_C(3244349472), // UQRSHR_VG4_Z4ZI_B |
| 6944 | UINT64_C(3248543776), // UQRSHR_VG4_Z4ZI_H |
| 6945 | UINT64_C(1141735424), // UQSHLR_ZPmZ_B |
| 6946 | UINT64_C(1154318336), // UQSHLR_ZPmZ_D |
| 6947 | UINT64_C(1145929728), // UQSHLR_ZPmZ_H |
| 6948 | UINT64_C(1150124032), // UQSHLR_ZPmZ_S |
| 6949 | UINT64_C(67600640), // UQSHL_ZPmI_B |
| 6950 | UINT64_C(75988992), // UQSHL_ZPmI_D |
| 6951 | UINT64_C(67600896), // UQSHL_ZPmI_H |
| 6952 | UINT64_C(71794688), // UQSHL_ZPmI_S |
| 6953 | UINT64_C(1141473280), // UQSHL_ZPmZ_B |
| 6954 | UINT64_C(1154056192), // UQSHL_ZPmZ_D |
| 6955 | UINT64_C(1145667584), // UQSHL_ZPmZ_H |
| 6956 | UINT64_C(1149861888), // UQSHL_ZPmZ_S |
| 6957 | UINT64_C(2131260416), // UQSHLb |
| 6958 | UINT64_C(2134930432), // UQSHLd |
| 6959 | UINT64_C(2131784704), // UQSHLh |
| 6960 | UINT64_C(2132833280), // UQSHLs |
| 6961 | UINT64_C(1847610368), // UQSHLv16i8 |
| 6962 | UINT64_C(1862824960), // UQSHLv16i8_shift |
| 6963 | UINT64_C(2120240128), // UQSHLv1i16 |
| 6964 | UINT64_C(2124434432), // UQSHLv1i32 |
| 6965 | UINT64_C(2128628736), // UQSHLv1i64 |
| 6966 | UINT64_C(2116045824), // UQSHLv1i8 |
| 6967 | UINT64_C(782257152), // UQSHLv2i32 |
| 6968 | UINT64_C(790656000), // UQSHLv2i32_shift |
| 6969 | UINT64_C(1860193280), // UQSHLv2i64 |
| 6970 | UINT64_C(1866494976), // UQSHLv2i64_shift |
| 6971 | UINT64_C(778062848), // UQSHLv4i16 |
| 6972 | UINT64_C(789607424), // UQSHLv4i16_shift |
| 6973 | UINT64_C(1855998976), // UQSHLv4i32 |
| 6974 | UINT64_C(1864397824), // UQSHLv4i32_shift |
| 6975 | UINT64_C(1851804672), // UQSHLv8i16 |
| 6976 | UINT64_C(1863349248), // UQSHLv8i16_shift |
| 6977 | UINT64_C(773868544), // UQSHLv8i8 |
| 6978 | UINT64_C(789083136), // UQSHLv8i8_shift |
| 6979 | UINT64_C(1160261632), // UQSHRNB_ZZI_B |
| 6980 | UINT64_C(1160785920), // UQSHRNB_ZZI_H |
| 6981 | UINT64_C(1163931648), // UQSHRNB_ZZI_S |
| 6982 | UINT64_C(1160262656), // UQSHRNT_ZZI_B |
| 6983 | UINT64_C(1160786944), // UQSHRNT_ZZI_H |
| 6984 | UINT64_C(1163932672), // UQSHRNT_ZZI_S |
| 6985 | UINT64_C(1168642048), // UQSHRN_Z2ZI_HtoB |
| 6986 | UINT64_C(1169166336), // UQSHRN_Z2ZI_StoH |
| 6987 | UINT64_C(2131268608), // UQSHRNb |
| 6988 | UINT64_C(2131792896), // UQSHRNh |
| 6989 | UINT64_C(2132841472), // UQSHRNs |
| 6990 | UINT64_C(1862833152), // UQSHRNv16i8_shift |
| 6991 | UINT64_C(790664192), // UQSHRNv2i32_shift |
| 6992 | UINT64_C(789615616), // UQSHRNv4i16_shift |
| 6993 | UINT64_C(1864406016), // UQSHRNv4i32_shift |
| 6994 | UINT64_C(1863357440), // UQSHRNv8i16_shift |
| 6995 | UINT64_C(789091328), // UQSHRNv8i8_shift |
| 6996 | UINT64_C(1142915072), // UQSUBR_ZPmZ_B |
| 6997 | UINT64_C(1155497984), // UQSUBR_ZPmZ_D |
| 6998 | UINT64_C(1147109376), // UQSUBR_ZPmZ_H |
| 6999 | UINT64_C(1151303680), // UQSUBR_ZPmZ_S |
| 7000 | UINT64_C(623362048), // UQSUB_ZI_B |
| 7001 | UINT64_C(635944960), // UQSUB_ZI_D |
| 7002 | UINT64_C(627556352), // UQSUB_ZI_H |
| 7003 | UINT64_C(631750656), // UQSUB_ZI_S |
| 7004 | UINT64_C(1142652928), // UQSUB_ZPmZ_B |
| 7005 | UINT64_C(1155235840), // UQSUB_ZPmZ_D |
| 7006 | UINT64_C(1146847232), // UQSUB_ZPmZ_H |
| 7007 | UINT64_C(1151041536), // UQSUB_ZPmZ_S |
| 7008 | UINT64_C(69213184), // UQSUB_ZZZ_B |
| 7009 | UINT64_C(81796096), // UQSUB_ZZZ_D |
| 7010 | UINT64_C(73407488), // UQSUB_ZZZ_H |
| 7011 | UINT64_C(77601792), // UQSUB_ZZZ_S |
| 7012 | UINT64_C(1847602176), // UQSUBv16i8 |
| 7013 | UINT64_C(2120231936), // UQSUBv1i16 |
| 7014 | UINT64_C(2124426240), // UQSUBv1i32 |
| 7015 | UINT64_C(2128620544), // UQSUBv1i64 |
| 7016 | UINT64_C(2116037632), // UQSUBv1i8 |
| 7017 | UINT64_C(782248960), // UQSUBv2i32 |
| 7018 | UINT64_C(1860185088), // UQSUBv2i64 |
| 7019 | UINT64_C(778054656), // UQSUBv4i16 |
| 7020 | UINT64_C(1855990784), // UQSUBv4i32 |
| 7021 | UINT64_C(1851796480), // UQSUBv8i16 |
| 7022 | UINT64_C(773860352), // UQSUBv8i8 |
| 7023 | UINT64_C(1160267776), // UQXTNB_ZZ_B |
| 7024 | UINT64_C(1160792064), // UQXTNB_ZZ_H |
| 7025 | UINT64_C(1163937792), // UQXTNB_ZZ_S |
| 7026 | UINT64_C(1160268800), // UQXTNT_ZZ_B |
| 7027 | UINT64_C(1160793088), // UQXTNT_ZZ_H |
| 7028 | UINT64_C(1163938816), // UQXTNT_ZZ_S |
| 7029 | UINT64_C(1847674880), // UQXTNv16i8 |
| 7030 | UINT64_C(2120304640), // UQXTNv1i16 |
| 7031 | UINT64_C(2124498944), // UQXTNv1i32 |
| 7032 | UINT64_C(2116110336), // UQXTNv1i8 |
| 7033 | UINT64_C(782321664), // UQXTNv2i32 |
| 7034 | UINT64_C(778127360), // UQXTNv4i16 |
| 7035 | UINT64_C(1856063488), // UQXTNv4i32 |
| 7036 | UINT64_C(1851869184), // UQXTNv8i16 |
| 7037 | UINT64_C(773933056), // UQXTNv8i8 |
| 7038 | UINT64_C(1149280256), // URECPE_ZPmZ_S |
| 7039 | UINT64_C(1149411328), // URECPE_ZPzZ_S |
| 7040 | UINT64_C(245483520), // URECPEv2i32 |
| 7041 | UINT64_C(1319225344), // URECPEv4i32 |
| 7042 | UINT64_C(1142259712), // URHADD_ZPmZ_B |
| 7043 | UINT64_C(1154842624), // URHADD_ZPmZ_D |
| 7044 | UINT64_C(1146454016), // URHADD_ZPmZ_H |
| 7045 | UINT64_C(1150648320), // URHADD_ZPmZ_S |
| 7046 | UINT64_C(1847596032), // URHADDv16i8 |
| 7047 | UINT64_C(782242816), // URHADDv2i32 |
| 7048 | UINT64_C(778048512), // URHADDv4i16 |
| 7049 | UINT64_C(1855984640), // URHADDv4i32 |
| 7050 | UINT64_C(1851790336), // URHADDv8i16 |
| 7051 | UINT64_C(773854208), // URHADDv8i8 |
| 7052 | UINT64_C(1141342208), // URSHLR_ZPmZ_B |
| 7053 | UINT64_C(1153925120), // URSHLR_ZPmZ_D |
| 7054 | UINT64_C(1145536512), // URSHLR_ZPmZ_H |
| 7055 | UINT64_C(1149730816), // URSHLR_ZPmZ_S |
| 7056 | UINT64_C(3240145441), // URSHL_VG2_2Z2Z_B |
| 7057 | UINT64_C(3252728353), // URSHL_VG2_2Z2Z_D |
| 7058 | UINT64_C(3244339745), // URSHL_VG2_2Z2Z_H |
| 7059 | UINT64_C(3248534049), // URSHL_VG2_2Z2Z_S |
| 7060 | UINT64_C(3240141345), // URSHL_VG2_2ZZ_B |
| 7061 | UINT64_C(3252724257), // URSHL_VG2_2ZZ_D |
| 7062 | UINT64_C(3244335649), // URSHL_VG2_2ZZ_H |
| 7063 | UINT64_C(3248529953), // URSHL_VG2_2ZZ_S |
| 7064 | UINT64_C(3240147489), // URSHL_VG4_4Z4Z_B |
| 7065 | UINT64_C(3252730401), // URSHL_VG4_4Z4Z_D |
| 7066 | UINT64_C(3244341793), // URSHL_VG4_4Z4Z_H |
| 7067 | UINT64_C(3248536097), // URSHL_VG4_4Z4Z_S |
| 7068 | UINT64_C(3240143393), // URSHL_VG4_4ZZ_B |
| 7069 | UINT64_C(3252726305), // URSHL_VG4_4ZZ_D |
| 7070 | UINT64_C(3244337697), // URSHL_VG4_4ZZ_H |
| 7071 | UINT64_C(3248532001), // URSHL_VG4_4ZZ_S |
| 7072 | UINT64_C(1141080064), // URSHL_ZPmZ_B |
| 7073 | UINT64_C(1153662976), // URSHL_ZPmZ_D |
| 7074 | UINT64_C(1145274368), // URSHL_ZPmZ_H |
| 7075 | UINT64_C(1149468672), // URSHL_ZPmZ_S |
| 7076 | UINT64_C(1847612416), // URSHLv16i8 |
| 7077 | UINT64_C(2128630784), // URSHLv1i64 |
| 7078 | UINT64_C(782259200), // URSHLv2i32 |
| 7079 | UINT64_C(1860195328), // URSHLv2i64 |
| 7080 | UINT64_C(778064896), // URSHLv4i16 |
| 7081 | UINT64_C(1856001024), // URSHLv4i32 |
| 7082 | UINT64_C(1851806720), // URSHLv8i16 |
| 7083 | UINT64_C(773870592), // URSHLv8i8 |
| 7084 | UINT64_C(67993856), // URSHR_ZPmI_B |
| 7085 | UINT64_C(76382208), // URSHR_ZPmI_D |
| 7086 | UINT64_C(67994112), // URSHR_ZPmI_H |
| 7087 | UINT64_C(72187904), // URSHR_ZPmI_S |
| 7088 | UINT64_C(2134909952), // URSHRd |
| 7089 | UINT64_C(1862804480), // URSHRv16i8_shift |
| 7090 | UINT64_C(790635520), // URSHRv2i32_shift |
| 7091 | UINT64_C(1866474496), // URSHRv2i64_shift |
| 7092 | UINT64_C(789586944), // URSHRv4i16_shift |
| 7093 | UINT64_C(1864377344), // URSHRv4i32_shift |
| 7094 | UINT64_C(1863328768), // URSHRv8i16_shift |
| 7095 | UINT64_C(789062656), // URSHRv8i8_shift |
| 7096 | UINT64_C(1149345792), // URSQRTE_ZPmZ_S |
| 7097 | UINT64_C(1149476864), // URSQRTE_ZPzZ_S |
| 7098 | UINT64_C(782354432), // URSQRTEv2i32 |
| 7099 | UINT64_C(1856096256), // URSQRTEv4i32 |
| 7100 | UINT64_C(1158212608), // URSRA_ZZI_B |
| 7101 | UINT64_C(1166076928), // URSRA_ZZI_D |
| 7102 | UINT64_C(1158736896), // URSRA_ZZI_H |
| 7103 | UINT64_C(1161882624), // URSRA_ZZI_S |
| 7104 | UINT64_C(2134914048), // URSRAd |
| 7105 | UINT64_C(1862808576), // URSRAv16i8_shift |
| 7106 | UINT64_C(790639616), // URSRAv2i32_shift |
| 7107 | UINT64_C(1866478592), // URSRAv2i64_shift |
| 7108 | UINT64_C(789591040), // URSRAv4i16_shift |
| 7109 | UINT64_C(1864381440), // URSRAv4i32_shift |
| 7110 | UINT64_C(1863332864), // URSRAv8i16_shift |
| 7111 | UINT64_C(789066752), // URSRAv8i8_shift |
| 7112 | UINT64_C(3248493576), // USDOT_VG2_M2Z2Z_BToS |
| 7113 | UINT64_C(3243249704), // USDOT_VG2_M2ZZI_BToS |
| 7114 | UINT64_C(3240104968), // USDOT_VG2_M2ZZ_BToS |
| 7115 | UINT64_C(3248559112), // USDOT_VG4_M4Z4Z_BToS |
| 7116 | UINT64_C(3243282472), // USDOT_VG4_M4ZZI_BToS |
| 7117 | UINT64_C(3241153544), // USDOT_VG4_M4ZZ_BToS |
| 7118 | UINT64_C(1149270016), // USDOT_ZZZ |
| 7119 | UINT64_C(1151342592), // USDOT_ZZZI |
| 7120 | UINT64_C(1333850112), // USDOTlanev16i8 |
| 7121 | UINT64_C(260108288), // USDOTlanev8i8 |
| 7122 | UINT64_C(1317051392), // USDOTv16i8 |
| 7123 | UINT64_C(243309568), // USDOTv8i8 |
| 7124 | UINT64_C(1161865216), // USHLLB_ZZI_D |
| 7125 | UINT64_C(1158195200), // USHLLB_ZZI_H |
| 7126 | UINT64_C(1158719488), // USHLLB_ZZI_S |
| 7127 | UINT64_C(1161866240), // USHLLT_ZZI_D |
| 7128 | UINT64_C(1158196224), // USHLLT_ZZI_H |
| 7129 | UINT64_C(1158720512), // USHLLT_ZZI_S |
| 7130 | UINT64_C(1862837248), // USHLLv16i8_shift |
| 7131 | UINT64_C(790668288), // USHLLv2i32_shift |
| 7132 | UINT64_C(789619712), // USHLLv4i16_shift |
| 7133 | UINT64_C(1864410112), // USHLLv4i32_shift |
| 7134 | UINT64_C(1863361536), // USHLLv8i16_shift |
| 7135 | UINT64_C(789095424), // USHLLv8i8_shift |
| 7136 | UINT64_C(1847608320), // USHLv16i8 |
| 7137 | UINT64_C(2128626688), // USHLv1i64 |
| 7138 | UINT64_C(782255104), // USHLv2i32 |
| 7139 | UINT64_C(1860191232), // USHLv2i64 |
| 7140 | UINT64_C(778060800), // USHLv4i16 |
| 7141 | UINT64_C(1855996928), // USHLv4i32 |
| 7142 | UINT64_C(1851802624), // USHLv8i16 |
| 7143 | UINT64_C(773866496), // USHLv8i8 |
| 7144 | UINT64_C(2134901760), // USHRd |
| 7145 | UINT64_C(1862796288), // USHRv16i8_shift |
| 7146 | UINT64_C(790627328), // USHRv2i32_shift |
| 7147 | UINT64_C(1866466304), // USHRv2i64_shift |
| 7148 | UINT64_C(789578752), // USHRv4i16_shift |
| 7149 | UINT64_C(1864369152), // USHRv4i32_shift |
| 7150 | UINT64_C(1863320576), // USHRv8i16_shift |
| 7151 | UINT64_C(789054464), // USHRv8i8_shift |
| 7152 | UINT64_C(3238002692), // USMLALL_MZZI_BtoS |
| 7153 | UINT64_C(3240100868), // USMLALL_MZZ_BtoS |
| 7154 | UINT64_C(3248488452), // USMLALL_VG2_M2Z2Z_BtoS |
| 7155 | UINT64_C(3239051296), // USMLALL_VG2_M2ZZI_BtoS |
| 7156 | UINT64_C(3240099844), // USMLALL_VG2_M2ZZ_BtoS |
| 7157 | UINT64_C(3248553988), // USMLALL_VG4_M4Z4Z_BtoS |
| 7158 | UINT64_C(3239084064), // USMLALL_VG4_M4ZZI_BtoS |
| 7159 | UINT64_C(3241148420), // USMLALL_VG4_M4ZZ_BtoS |
| 7160 | UINT64_C(1317055488), // USMMLA |
| 7161 | UINT64_C(1166055424), // USMMLA_ZZZ |
| 7162 | UINT64_C(2165342720), // USMOP4A_M2Z2Z_BToS |
| 7163 | UINT64_C(2714763784), // USMOP4A_M2Z2Z_HtoD |
| 7164 | UINT64_C(2164294144), // USMOP4A_M2ZZ_BToS |
| 7165 | UINT64_C(2713715208), // USMOP4A_M2ZZ_HtoD |
| 7166 | UINT64_C(2165342208), // USMOP4A_MZ2Z_BToS |
| 7167 | UINT64_C(2714763272), // USMOP4A_MZ2Z_HtoD |
| 7168 | UINT64_C(2164293632), // USMOP4A_MZZ_BToS |
| 7169 | UINT64_C(2713714696), // USMOP4A_MZZ_HtoD |
| 7170 | UINT64_C(2165342736), // USMOP4S_M2Z2Z_BToS |
| 7171 | UINT64_C(2714763800), // USMOP4S_M2Z2Z_HtoD |
| 7172 | UINT64_C(2164294160), // USMOP4S_M2ZZ_BToS |
| 7173 | UINT64_C(2713715224), // USMOP4S_M2ZZ_HtoD |
| 7174 | UINT64_C(2165342224), // USMOP4S_MZ2Z_BToS |
| 7175 | UINT64_C(2714763288), // USMOP4S_MZ2Z_HtoD |
| 7176 | UINT64_C(2164293648), // USMOP4S_MZZ_BToS |
| 7177 | UINT64_C(2713714712), // USMOP4S_MZZ_HtoD |
| 7178 | UINT64_C(2713714688), // USMOPA_MPPZZ_D |
| 7179 | UINT64_C(2709520384), // USMOPA_MPPZZ_S |
| 7180 | UINT64_C(2713714704), // USMOPS_MPPZZ_D |
| 7181 | UINT64_C(2709520400), // USMOPS_MPPZZ_S |
| 7182 | UINT64_C(1142784000), // USQADD_ZPmZ_B |
| 7183 | UINT64_C(1155366912), // USQADD_ZPmZ_D |
| 7184 | UINT64_C(1146978304), // USQADD_ZPmZ_H |
| 7185 | UINT64_C(1151172608), // USQADD_ZPmZ_S |
| 7186 | UINT64_C(1847605248), // USQADDv16i8 |
| 7187 | UINT64_C(2120235008), // USQADDv1i16 |
| 7188 | UINT64_C(2124429312), // USQADDv1i32 |
| 7189 | UINT64_C(2128623616), // USQADDv1i64 |
| 7190 | UINT64_C(2116040704), // USQADDv1i8 |
| 7191 | UINT64_C(782252032), // USQADDv2i32 |
| 7192 | UINT64_C(1860188160), // USQADDv2i64 |
| 7193 | UINT64_C(778057728), // USQADDv4i16 |
| 7194 | UINT64_C(1855993856), // USQADDv4i32 |
| 7195 | UINT64_C(1851799552), // USQADDv8i16 |
| 7196 | UINT64_C(773863424), // USQADDv8i8 |
| 7197 | UINT64_C(1158210560), // USRA_ZZI_B |
| 7198 | UINT64_C(1166074880), // USRA_ZZI_D |
| 7199 | UINT64_C(1158734848), // USRA_ZZI_H |
| 7200 | UINT64_C(1161880576), // USRA_ZZI_S |
| 7201 | UINT64_C(2134905856), // USRAd |
| 7202 | UINT64_C(1862800384), // USRAv16i8_shift |
| 7203 | UINT64_C(790631424), // USRAv2i32_shift |
| 7204 | UINT64_C(1866470400), // USRAv2i64_shift |
| 7205 | UINT64_C(789582848), // USRAv4i16_shift |
| 7206 | UINT64_C(1864373248), // USRAv4i32_shift |
| 7207 | UINT64_C(1863324672), // USRAv8i16_shift |
| 7208 | UINT64_C(789058560), // USRAv8i8_shift |
| 7209 | UINT64_C(2168487936), // USTMOPA_M2ZZZI_BtoS |
| 7210 | UINT64_C(1170216960), // USUBLB_ZZZ_D |
| 7211 | UINT64_C(1161828352), // USUBLB_ZZZ_H |
| 7212 | UINT64_C(1166022656), // USUBLB_ZZZ_S |
| 7213 | UINT64_C(1170217984), // USUBLT_ZZZ_D |
| 7214 | UINT64_C(1161829376), // USUBLT_ZZZ_H |
| 7215 | UINT64_C(1166023680), // USUBLT_ZZZ_S |
| 7216 | UINT64_C(1847599104), // USUBLv16i8_v8i16 |
| 7217 | UINT64_C(782245888), // USUBLv2i32_v2i64 |
| 7218 | UINT64_C(778051584), // USUBLv4i16_v4i32 |
| 7219 | UINT64_C(1855987712), // USUBLv4i32_v2i64 |
| 7220 | UINT64_C(1851793408), // USUBLv8i16_v4i32 |
| 7221 | UINT64_C(773857280), // USUBLv8i8_v8i16 |
| 7222 | UINT64_C(1170233344), // USUBWB_ZZZ_D |
| 7223 | UINT64_C(1161844736), // USUBWB_ZZZ_H |
| 7224 | UINT64_C(1166039040), // USUBWB_ZZZ_S |
| 7225 | UINT64_C(1170234368), // USUBWT_ZZZ_D |
| 7226 | UINT64_C(1161845760), // USUBWT_ZZZ_H |
| 7227 | UINT64_C(1166040064), // USUBWT_ZZZ_S |
| 7228 | UINT64_C(1847603200), // USUBWv16i8_v8i16 |
| 7229 | UINT64_C(782249984), // USUBWv2i32_v2i64 |
| 7230 | UINT64_C(778055680), // USUBWv4i16_v4i32 |
| 7231 | UINT64_C(1855991808), // USUBWv4i32_v2i64 |
| 7232 | UINT64_C(1851797504), // USUBWv8i16_v4i32 |
| 7233 | UINT64_C(773861376), // USUBWv8i8_v8i16 |
| 7234 | UINT64_C(3243278376), // USVDOT_VG4_M4ZZI_BToS |
| 7235 | UINT64_C(2170585088), // UTMOPA_M2ZZZI_BtoS |
| 7236 | UINT64_C(2168487944), // UTMOPA_M2ZZZI_HtoS |
| 7237 | UINT64_C(99825664), // UUNPKHI_ZZ_D |
| 7238 | UINT64_C(91437056), // UUNPKHI_ZZ_H |
| 7239 | UINT64_C(95631360), // UUNPKHI_ZZ_S |
| 7240 | UINT64_C(99760128), // UUNPKLO_ZZ_D |
| 7241 | UINT64_C(91371520), // UUNPKLO_ZZ_H |
| 7242 | UINT64_C(95565824), // UUNPKLO_ZZ_S |
| 7243 | UINT64_C(3253067777), // UUNPK_VG2_2ZZ_D |
| 7244 | UINT64_C(3244679169), // UUNPK_VG2_2ZZ_H |
| 7245 | UINT64_C(3248873473), // UUNPK_VG2_2ZZ_S |
| 7246 | UINT64_C(3254116353), // UUNPK_VG4_4Z2Z_D |
| 7247 | UINT64_C(3245727745), // UUNPK_VG4_4Z2Z_H |
| 7248 | UINT64_C(3249922049), // UUNPK_VG4_4Z2Z_S |
| 7249 | UINT64_C(3243245616), // UVDOT_VG2_M2ZZI_HtoS |
| 7250 | UINT64_C(3243278384), // UVDOT_VG4_M4ZZI_BtoS |
| 7251 | UINT64_C(3251669016), // UVDOT_VG4_M4ZZI_HtoD |
| 7252 | UINT64_C(80846848), // UXTB_ZPmZ_D |
| 7253 | UINT64_C(72458240), // UXTB_ZPmZ_H |
| 7254 | UINT64_C(76652544), // UXTB_ZPmZ_S |
| 7255 | UINT64_C(79798272), // UXTB_ZPzZ_D |
| 7256 | UINT64_C(71409664), // UXTB_ZPzZ_H |
| 7257 | UINT64_C(75603968), // UXTB_ZPzZ_S |
| 7258 | UINT64_C(80977920), // UXTH_ZPmZ_D |
| 7259 | UINT64_C(76783616), // UXTH_ZPmZ_S |
| 7260 | UINT64_C(79929344), // UXTH_ZPzZ_D |
| 7261 | UINT64_C(75735040), // UXTH_ZPzZ_S |
| 7262 | UINT64_C(81108992), // UXTW_ZPmZ_D |
| 7263 | UINT64_C(80060416), // UXTW_ZPzZ_D |
| 7264 | UINT64_C(86001664), // UZP1_PPP_B |
| 7265 | UINT64_C(98584576), // UZP1_PPP_D |
| 7266 | UINT64_C(90195968), // UZP1_PPP_H |
| 7267 | UINT64_C(94390272), // UZP1_PPP_S |
| 7268 | UINT64_C(86009856), // UZP1_ZZZ_B |
| 7269 | UINT64_C(98592768), // UZP1_ZZZ_D |
| 7270 | UINT64_C(90204160), // UZP1_ZZZ_H |
| 7271 | UINT64_C(94373888), // UZP1_ZZZ_Q |
| 7272 | UINT64_C(94398464), // UZP1_ZZZ_S |
| 7273 | UINT64_C(1308628992), // UZP1v16i8 |
| 7274 | UINT64_C(243275776), // UZP1v2i32 |
| 7275 | UINT64_C(1321211904), // UZP1v2i64 |
| 7276 | UINT64_C(239081472), // UZP1v4i16 |
| 7277 | UINT64_C(1317017600), // UZP1v4i32 |
| 7278 | UINT64_C(1312823296), // UZP1v8i16 |
| 7279 | UINT64_C(234887168), // UZP1v8i8 |
| 7280 | UINT64_C(86002688), // UZP2_PPP_B |
| 7281 | UINT64_C(98585600), // UZP2_PPP_D |
| 7282 | UINT64_C(90196992), // UZP2_PPP_H |
| 7283 | UINT64_C(94391296), // UZP2_PPP_S |
| 7284 | UINT64_C(86010880), // UZP2_ZZZ_B |
| 7285 | UINT64_C(98593792), // UZP2_ZZZ_D |
| 7286 | UINT64_C(90205184), // UZP2_ZZZ_H |
| 7287 | UINT64_C(94374912), // UZP2_ZZZ_Q |
| 7288 | UINT64_C(94399488), // UZP2_ZZZ_S |
| 7289 | UINT64_C(1308645376), // UZP2v16i8 |
| 7290 | UINT64_C(243292160), // UZP2v2i32 |
| 7291 | UINT64_C(1321228288), // UZP2v2i64 |
| 7292 | UINT64_C(239097856), // UZP2v4i16 |
| 7293 | UINT64_C(1317033984), // UZP2v4i32 |
| 7294 | UINT64_C(1312839680), // UZP2v8i16 |
| 7295 | UINT64_C(234903552), // UZP2v8i8 |
| 7296 | UINT64_C(1140910080), // UZPQ1_ZZZ_B |
| 7297 | UINT64_C(1153492992), // UZPQ1_ZZZ_D |
| 7298 | UINT64_C(1145104384), // UZPQ1_ZZZ_H |
| 7299 | UINT64_C(1149298688), // UZPQ1_ZZZ_S |
| 7300 | UINT64_C(1140911104), // UZPQ2_ZZZ_B |
| 7301 | UINT64_C(1153494016), // UZPQ2_ZZZ_D |
| 7302 | UINT64_C(1145105408), // UZPQ2_ZZZ_H |
| 7303 | UINT64_C(1149299712), // UZPQ2_ZZZ_S |
| 7304 | UINT64_C(3240153089), // UZP_VG2_2ZZZ_B |
| 7305 | UINT64_C(3252736001), // UZP_VG2_2ZZZ_D |
| 7306 | UINT64_C(3244347393), // UZP_VG2_2ZZZ_H |
| 7307 | UINT64_C(3240154113), // UZP_VG2_2ZZZ_Q |
| 7308 | UINT64_C(3248541697), // UZP_VG2_2ZZZ_S |
| 7309 | UINT64_C(3241598978), // UZP_VG4_4Z4Z_B |
| 7310 | UINT64_C(3254181890), // UZP_VG4_4Z4Z_D |
| 7311 | UINT64_C(3245793282), // UZP_VG4_4Z4Z_H |
| 7312 | UINT64_C(3241664514), // UZP_VG4_4Z4Z_Q |
| 7313 | UINT64_C(3249987586), // UZP_VG4_4Z4Z_S |
| 7314 | UINT64_C(3573747712), // WFET |
| 7315 | UINT64_C(3573747744), // WFIT |
| 7316 | UINT64_C(622874640), // WHILEGE_2PXX_B |
| 7317 | UINT64_C(635457552), // WHILEGE_2PXX_D |
| 7318 | UINT64_C(627068944), // WHILEGE_2PXX_H |
| 7319 | UINT64_C(631263248), // WHILEGE_2PXX_S |
| 7320 | UINT64_C(622870544), // WHILEGE_CXX_B |
| 7321 | UINT64_C(635453456), // WHILEGE_CXX_D |
| 7322 | UINT64_C(627064848), // WHILEGE_CXX_H |
| 7323 | UINT64_C(631259152), // WHILEGE_CXX_S |
| 7324 | UINT64_C(622854144), // WHILEGE_PWW_B |
| 7325 | UINT64_C(635437056), // WHILEGE_PWW_D |
| 7326 | UINT64_C(627048448), // WHILEGE_PWW_H |
| 7327 | UINT64_C(631242752), // WHILEGE_PWW_S |
| 7328 | UINT64_C(622858240), // WHILEGE_PXX_B |
| 7329 | UINT64_C(635441152), // WHILEGE_PXX_D |
| 7330 | UINT64_C(627052544), // WHILEGE_PXX_H |
| 7331 | UINT64_C(631246848), // WHILEGE_PXX_S |
| 7332 | UINT64_C(622874641), // WHILEGT_2PXX_B |
| 7333 | UINT64_C(635457553), // WHILEGT_2PXX_D |
| 7334 | UINT64_C(627068945), // WHILEGT_2PXX_H |
| 7335 | UINT64_C(631263249), // WHILEGT_2PXX_S |
| 7336 | UINT64_C(622870552), // WHILEGT_CXX_B |
| 7337 | UINT64_C(635453464), // WHILEGT_CXX_D |
| 7338 | UINT64_C(627064856), // WHILEGT_CXX_H |
| 7339 | UINT64_C(631259160), // WHILEGT_CXX_S |
| 7340 | UINT64_C(622854160), // WHILEGT_PWW_B |
| 7341 | UINT64_C(635437072), // WHILEGT_PWW_D |
| 7342 | UINT64_C(627048464), // WHILEGT_PWW_H |
| 7343 | UINT64_C(631242768), // WHILEGT_PWW_S |
| 7344 | UINT64_C(622858256), // WHILEGT_PXX_B |
| 7345 | UINT64_C(635441168), // WHILEGT_PXX_D |
| 7346 | UINT64_C(627052560), // WHILEGT_PXX_H |
| 7347 | UINT64_C(631246864), // WHILEGT_PXX_S |
| 7348 | UINT64_C(622876689), // WHILEHI_2PXX_B |
| 7349 | UINT64_C(635459601), // WHILEHI_2PXX_D |
| 7350 | UINT64_C(627070993), // WHILEHI_2PXX_H |
| 7351 | UINT64_C(631265297), // WHILEHI_2PXX_S |
| 7352 | UINT64_C(622872600), // WHILEHI_CXX_B |
| 7353 | UINT64_C(635455512), // WHILEHI_CXX_D |
| 7354 | UINT64_C(627066904), // WHILEHI_CXX_H |
| 7355 | UINT64_C(631261208), // WHILEHI_CXX_S |
| 7356 | UINT64_C(622856208), // WHILEHI_PWW_B |
| 7357 | UINT64_C(635439120), // WHILEHI_PWW_D |
| 7358 | UINT64_C(627050512), // WHILEHI_PWW_H |
| 7359 | UINT64_C(631244816), // WHILEHI_PWW_S |
| 7360 | UINT64_C(622860304), // WHILEHI_PXX_B |
| 7361 | UINT64_C(635443216), // WHILEHI_PXX_D |
| 7362 | UINT64_C(627054608), // WHILEHI_PXX_H |
| 7363 | UINT64_C(631248912), // WHILEHI_PXX_S |
| 7364 | UINT64_C(622876688), // WHILEHS_2PXX_B |
| 7365 | UINT64_C(635459600), // WHILEHS_2PXX_D |
| 7366 | UINT64_C(627070992), // WHILEHS_2PXX_H |
| 7367 | UINT64_C(631265296), // WHILEHS_2PXX_S |
| 7368 | UINT64_C(622872592), // WHILEHS_CXX_B |
| 7369 | UINT64_C(635455504), // WHILEHS_CXX_D |
| 7370 | UINT64_C(627066896), // WHILEHS_CXX_H |
| 7371 | UINT64_C(631261200), // WHILEHS_CXX_S |
| 7372 | UINT64_C(622856192), // WHILEHS_PWW_B |
| 7373 | UINT64_C(635439104), // WHILEHS_PWW_D |
| 7374 | UINT64_C(627050496), // WHILEHS_PWW_H |
| 7375 | UINT64_C(631244800), // WHILEHS_PWW_S |
| 7376 | UINT64_C(622860288), // WHILEHS_PXX_B |
| 7377 | UINT64_C(635443200), // WHILEHS_PXX_D |
| 7378 | UINT64_C(627054592), // WHILEHS_PXX_H |
| 7379 | UINT64_C(631248896), // WHILEHS_PXX_S |
| 7380 | UINT64_C(622875665), // WHILELE_2PXX_B |
| 7381 | UINT64_C(635458577), // WHILELE_2PXX_D |
| 7382 | UINT64_C(627069969), // WHILELE_2PXX_H |
| 7383 | UINT64_C(631264273), // WHILELE_2PXX_S |
| 7384 | UINT64_C(622871576), // WHILELE_CXX_B |
| 7385 | UINT64_C(635454488), // WHILELE_CXX_D |
| 7386 | UINT64_C(627065880), // WHILELE_CXX_H |
| 7387 | UINT64_C(631260184), // WHILELE_CXX_S |
| 7388 | UINT64_C(622855184), // WHILELE_PWW_B |
| 7389 | UINT64_C(635438096), // WHILELE_PWW_D |
| 7390 | UINT64_C(627049488), // WHILELE_PWW_H |
| 7391 | UINT64_C(631243792), // WHILELE_PWW_S |
| 7392 | UINT64_C(622859280), // WHILELE_PXX_B |
| 7393 | UINT64_C(635442192), // WHILELE_PXX_D |
| 7394 | UINT64_C(627053584), // WHILELE_PXX_H |
| 7395 | UINT64_C(631247888), // WHILELE_PXX_S |
| 7396 | UINT64_C(622877712), // WHILELO_2PXX_B |
| 7397 | UINT64_C(635460624), // WHILELO_2PXX_D |
| 7398 | UINT64_C(627072016), // WHILELO_2PXX_H |
| 7399 | UINT64_C(631266320), // WHILELO_2PXX_S |
| 7400 | UINT64_C(622873616), // WHILELO_CXX_B |
| 7401 | UINT64_C(635456528), // WHILELO_CXX_D |
| 7402 | UINT64_C(627067920), // WHILELO_CXX_H |
| 7403 | UINT64_C(631262224), // WHILELO_CXX_S |
| 7404 | UINT64_C(622857216), // WHILELO_PWW_B |
| 7405 | UINT64_C(635440128), // WHILELO_PWW_D |
| 7406 | UINT64_C(627051520), // WHILELO_PWW_H |
| 7407 | UINT64_C(631245824), // WHILELO_PWW_S |
| 7408 | UINT64_C(622861312), // WHILELO_PXX_B |
| 7409 | UINT64_C(635444224), // WHILELO_PXX_D |
| 7410 | UINT64_C(627055616), // WHILELO_PXX_H |
| 7411 | UINT64_C(631249920), // WHILELO_PXX_S |
| 7412 | UINT64_C(622877713), // WHILELS_2PXX_B |
| 7413 | UINT64_C(635460625), // WHILELS_2PXX_D |
| 7414 | UINT64_C(627072017), // WHILELS_2PXX_H |
| 7415 | UINT64_C(631266321), // WHILELS_2PXX_S |
| 7416 | UINT64_C(622873624), // WHILELS_CXX_B |
| 7417 | UINT64_C(635456536), // WHILELS_CXX_D |
| 7418 | UINT64_C(627067928), // WHILELS_CXX_H |
| 7419 | UINT64_C(631262232), // WHILELS_CXX_S |
| 7420 | UINT64_C(622857232), // WHILELS_PWW_B |
| 7421 | UINT64_C(635440144), // WHILELS_PWW_D |
| 7422 | UINT64_C(627051536), // WHILELS_PWW_H |
| 7423 | UINT64_C(631245840), // WHILELS_PWW_S |
| 7424 | UINT64_C(622861328), // WHILELS_PXX_B |
| 7425 | UINT64_C(635444240), // WHILELS_PXX_D |
| 7426 | UINT64_C(627055632), // WHILELS_PXX_H |
| 7427 | UINT64_C(631249936), // WHILELS_PXX_S |
| 7428 | UINT64_C(622875664), // WHILELT_2PXX_B |
| 7429 | UINT64_C(635458576), // WHILELT_2PXX_D |
| 7430 | UINT64_C(627069968), // WHILELT_2PXX_H |
| 7431 | UINT64_C(631264272), // WHILELT_2PXX_S |
| 7432 | UINT64_C(622871568), // WHILELT_CXX_B |
| 7433 | UINT64_C(635454480), // WHILELT_CXX_D |
| 7434 | UINT64_C(627065872), // WHILELT_CXX_H |
| 7435 | UINT64_C(631260176), // WHILELT_CXX_S |
| 7436 | UINT64_C(622855168), // WHILELT_PWW_B |
| 7437 | UINT64_C(635438080), // WHILELT_PWW_D |
| 7438 | UINT64_C(627049472), // WHILELT_PWW_H |
| 7439 | UINT64_C(631243776), // WHILELT_PWW_S |
| 7440 | UINT64_C(622859264), // WHILELT_PXX_B |
| 7441 | UINT64_C(635442176), // WHILELT_PXX_D |
| 7442 | UINT64_C(627053568), // WHILELT_PXX_H |
| 7443 | UINT64_C(631247872), // WHILELT_PXX_S |
| 7444 | UINT64_C(622866448), // WHILERW_PXX_B |
| 7445 | UINT64_C(635449360), // WHILERW_PXX_D |
| 7446 | UINT64_C(627060752), // WHILERW_PXX_H |
| 7447 | UINT64_C(631255056), // WHILERW_PXX_S |
| 7448 | UINT64_C(622866432), // WHILEWR_PXX_B |
| 7449 | UINT64_C(635449344), // WHILEWR_PXX_D |
| 7450 | UINT64_C(627060736), // WHILEWR_PXX_H |
| 7451 | UINT64_C(631255040), // WHILEWR_PXX_S |
| 7452 | UINT64_C(623415296), // WRFFR |
| 7453 | UINT64_C(3573563455), // XAFLAG |
| 7454 | UINT64_C(3464495104), // XAR |
| 7455 | UINT64_C(69743616), // XAR_ZZZI_B |
| 7456 | UINT64_C(77607936), // XAR_ZZZI_D |
| 7457 | UINT64_C(70267904), // XAR_ZZZI_H |
| 7458 | UINT64_C(73413632), // XAR_ZZZI_S |
| 7459 | UINT64_C(3670099936), // XPACD |
| 7460 | UINT64_C(3670098912), // XPACI |
| 7461 | UINT64_C(3573752063), // XPACLRI |
| 7462 | UINT64_C(1310795776), // XTNv16i8 |
| 7463 | UINT64_C(245442560), // XTNv2i32 |
| 7464 | UINT64_C(241248256), // XTNv4i16 |
| 7465 | UINT64_C(1319184384), // XTNv4i32 |
| 7466 | UINT64_C(1314990080), // XTNv8i16 |
| 7467 | UINT64_C(237053952), // XTNv8i8 |
| 7468 | UINT64_C(3221749760), // ZERO_M |
| 7469 | UINT64_C(3222044672), // ZERO_MXI_2Z |
| 7470 | UINT64_C(3222175744), // ZERO_MXI_4Z |
| 7471 | UINT64_C(3222077440), // ZERO_MXI_VG2_2Z |
| 7472 | UINT64_C(3222208512), // ZERO_MXI_VG2_4Z |
| 7473 | UINT64_C(3222011904), // ZERO_MXI_VG2_Z |
| 7474 | UINT64_C(3222110208), // ZERO_MXI_VG4_2Z |
| 7475 | UINT64_C(3222241280), // ZERO_MXI_VG4_4Z |
| 7476 | UINT64_C(3222142976), // ZERO_MXI_VG4_Z |
| 7477 | UINT64_C(3225944065), // ZERO_T |
| 7478 | UINT64_C(85999616), // ZIP1_PPP_B |
| 7479 | UINT64_C(98582528), // ZIP1_PPP_D |
| 7480 | UINT64_C(90193920), // ZIP1_PPP_H |
| 7481 | UINT64_C(94388224), // ZIP1_PPP_S |
| 7482 | UINT64_C(86007808), // ZIP1_ZZZ_B |
| 7483 | UINT64_C(98590720), // ZIP1_ZZZ_D |
| 7484 | UINT64_C(90202112), // ZIP1_ZZZ_H |
| 7485 | UINT64_C(94371840), // ZIP1_ZZZ_Q |
| 7486 | UINT64_C(94396416), // ZIP1_ZZZ_S |
| 7487 | UINT64_C(1308637184), // ZIP1v16i8 |
| 7488 | UINT64_C(243283968), // ZIP1v2i32 |
| 7489 | UINT64_C(1321220096), // ZIP1v2i64 |
| 7490 | UINT64_C(239089664), // ZIP1v4i16 |
| 7491 | UINT64_C(1317025792), // ZIP1v4i32 |
| 7492 | UINT64_C(1312831488), // ZIP1v8i16 |
| 7493 | UINT64_C(234895360), // ZIP1v8i8 |
| 7494 | UINT64_C(86000640), // ZIP2_PPP_B |
| 7495 | UINT64_C(98583552), // ZIP2_PPP_D |
| 7496 | UINT64_C(90194944), // ZIP2_PPP_H |
| 7497 | UINT64_C(94389248), // ZIP2_PPP_S |
| 7498 | UINT64_C(86008832), // ZIP2_ZZZ_B |
| 7499 | UINT64_C(98591744), // ZIP2_ZZZ_D |
| 7500 | UINT64_C(90203136), // ZIP2_ZZZ_H |
| 7501 | UINT64_C(94372864), // ZIP2_ZZZ_Q |
| 7502 | UINT64_C(94397440), // ZIP2_ZZZ_S |
| 7503 | UINT64_C(1308653568), // ZIP2v16i8 |
| 7504 | UINT64_C(243300352), // ZIP2v2i32 |
| 7505 | UINT64_C(1321236480), // ZIP2v2i64 |
| 7506 | UINT64_C(239106048), // ZIP2v4i16 |
| 7507 | UINT64_C(1317042176), // ZIP2v4i32 |
| 7508 | UINT64_C(1312847872), // ZIP2v8i16 |
| 7509 | UINT64_C(234911744), // ZIP2v8i8 |
| 7510 | UINT64_C(1140908032), // ZIPQ1_ZZZ_B |
| 7511 | UINT64_C(1153490944), // ZIPQ1_ZZZ_D |
| 7512 | UINT64_C(1145102336), // ZIPQ1_ZZZ_H |
| 7513 | UINT64_C(1149296640), // ZIPQ1_ZZZ_S |
| 7514 | UINT64_C(1140909056), // ZIPQ2_ZZZ_B |
| 7515 | UINT64_C(1153491968), // ZIPQ2_ZZZ_D |
| 7516 | UINT64_C(1145103360), // ZIPQ2_ZZZ_H |
| 7517 | UINT64_C(1149297664), // ZIPQ2_ZZZ_S |
| 7518 | UINT64_C(3240153088), // ZIP_VG2_2ZZZ_B |
| 7519 | UINT64_C(3252736000), // ZIP_VG2_2ZZZ_D |
| 7520 | UINT64_C(3244347392), // ZIP_VG2_2ZZZ_H |
| 7521 | UINT64_C(3240154112), // ZIP_VG2_2ZZZ_Q |
| 7522 | UINT64_C(3248541696), // ZIP_VG2_2ZZZ_S |
| 7523 | UINT64_C(3241598976), // ZIP_VG4_4Z4Z_B |
| 7524 | UINT64_C(3254181888), // ZIP_VG4_4Z4Z_D |
| 7525 | UINT64_C(3245793280), // ZIP_VG4_4Z4Z_H |
| 7526 | UINT64_C(3241664512), // ZIP_VG4_4Z4Z_Q |
| 7527 | UINT64_C(3249987584), // ZIP_VG4_4Z4Z_S |
| 7528 | }; |
| 7529 | constexpr unsigned FirstSupportedOpcode = 1764; |
| 7530 | |
| 7531 | const unsigned opcode = MI.getOpcode(); |
| 7532 | if (opcode < FirstSupportedOpcode) |
| 7533 | reportUnsupportedInst(Inst: MI); |
| 7534 | unsigned TableIndex = opcode - FirstSupportedOpcode; |
| 7535 | uint64_t Value = InstBits[TableIndex]; |
| 7536 | uint64_t op = 0; |
| 7537 | (void)op; // suppress warning |
| 7538 | switch (opcode) { |
| 7539 | case AArch64::AUTIA1716: |
| 7540 | case AArch64::AUTIA171615: |
| 7541 | case AArch64::AUTIASP: |
| 7542 | case AArch64::AUTIAZ: |
| 7543 | case AArch64::AUTIB1716: |
| 7544 | case AArch64::AUTIB171615: |
| 7545 | case AArch64::AUTIBSP: |
| 7546 | case AArch64::AUTIBZ: |
| 7547 | case AArch64::AXFLAG: |
| 7548 | case AArch64::CFINV: |
| 7549 | case AArch64::CHKFEAT: |
| 7550 | case AArch64::DRPS: |
| 7551 | case AArch64::ERET: |
| 7552 | case AArch64::ERETAA: |
| 7553 | case AArch64::ERETAB: |
| 7554 | case AArch64::GCSPOPCX: |
| 7555 | case AArch64::GCSPOPX: |
| 7556 | case AArch64::GCSPUSHX: |
| 7557 | case AArch64::NOP: |
| 7558 | case AArch64::PACIA1716: |
| 7559 | case AArch64::PACIA171615: |
| 7560 | case AArch64::PACIASP: |
| 7561 | case AArch64::PACIASPPC: |
| 7562 | case AArch64::PACIAZ: |
| 7563 | case AArch64::PACIB1716: |
| 7564 | case AArch64::PACIB171615: |
| 7565 | case AArch64::PACIBSP: |
| 7566 | case AArch64::PACIBSPPC: |
| 7567 | case AArch64::PACIBZ: |
| 7568 | case AArch64::PACM: |
| 7569 | case AArch64::PACNBIASPPC: |
| 7570 | case AArch64::PACNBIBSPPC: |
| 7571 | case AArch64::RETAA: |
| 7572 | case AArch64::RETAB: |
| 7573 | case AArch64::SB: |
| 7574 | case AArch64::SETFFR: |
| 7575 | case AArch64::XAFLAG: |
| 7576 | case AArch64::XPACLRI: |
| 7577 | case AArch64::ZERO_T: { |
| 7578 | break; |
| 7579 | } |
| 7580 | case AArch64::DSBnXS: { |
| 7581 | // op: CRm |
| 7582 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7583 | Value |= (op & 0xc) << 8; |
| 7584 | break; |
| 7585 | } |
| 7586 | case AArch64::CLREX: |
| 7587 | case AArch64::DMB: |
| 7588 | case AArch64::DSB: |
| 7589 | case AArch64::ISB: { |
| 7590 | // op: CRm |
| 7591 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7592 | Value |= (op & 0xf) << 8; |
| 7593 | break; |
| 7594 | } |
| 7595 | case AArch64::PTRUE_C_B: |
| 7596 | case AArch64::PTRUE_C_D: |
| 7597 | case AArch64::PTRUE_C_H: |
| 7598 | case AArch64::PTRUE_C_S: { |
| 7599 | // op: PNd |
| 7600 | op = EncodePNR_p8to15(MI, OpIdx: 0, Fixups, STI); |
| 7601 | Value |= (op & 0x7); |
| 7602 | break; |
| 7603 | } |
| 7604 | case AArch64::WHILEGE_CXX_B: |
| 7605 | case AArch64::WHILEGE_CXX_D: |
| 7606 | case AArch64::WHILEGE_CXX_H: |
| 7607 | case AArch64::WHILEGE_CXX_S: |
| 7608 | case AArch64::WHILEGT_CXX_B: |
| 7609 | case AArch64::WHILEGT_CXX_D: |
| 7610 | case AArch64::WHILEGT_CXX_H: |
| 7611 | case AArch64::WHILEGT_CXX_S: |
| 7612 | case AArch64::WHILEHI_CXX_B: |
| 7613 | case AArch64::WHILEHI_CXX_D: |
| 7614 | case AArch64::WHILEHI_CXX_H: |
| 7615 | case AArch64::WHILEHI_CXX_S: |
| 7616 | case AArch64::WHILEHS_CXX_B: |
| 7617 | case AArch64::WHILEHS_CXX_D: |
| 7618 | case AArch64::WHILEHS_CXX_H: |
| 7619 | case AArch64::WHILEHS_CXX_S: |
| 7620 | case AArch64::WHILELE_CXX_B: |
| 7621 | case AArch64::WHILELE_CXX_D: |
| 7622 | case AArch64::WHILELE_CXX_H: |
| 7623 | case AArch64::WHILELE_CXX_S: |
| 7624 | case AArch64::WHILELO_CXX_B: |
| 7625 | case AArch64::WHILELO_CXX_D: |
| 7626 | case AArch64::WHILELO_CXX_H: |
| 7627 | case AArch64::WHILELO_CXX_S: |
| 7628 | case AArch64::WHILELS_CXX_B: |
| 7629 | case AArch64::WHILELS_CXX_D: |
| 7630 | case AArch64::WHILELS_CXX_H: |
| 7631 | case AArch64::WHILELS_CXX_S: |
| 7632 | case AArch64::WHILELT_CXX_B: |
| 7633 | case AArch64::WHILELT_CXX_D: |
| 7634 | case AArch64::WHILELT_CXX_H: |
| 7635 | case AArch64::WHILELT_CXX_S: { |
| 7636 | // op: PNd |
| 7637 | op = EncodePNR_p8to15(MI, OpIdx: 0, Fixups, STI); |
| 7638 | Value |= (op & 0x7); |
| 7639 | // op: Rn |
| 7640 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7641 | Value |= (op & 0x1f) << 5; |
| 7642 | // op: vl |
| 7643 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7644 | Value |= (op & 0x1) << 13; |
| 7645 | // op: Rm |
| 7646 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7647 | Value |= (op & 0x1f) << 16; |
| 7648 | break; |
| 7649 | } |
| 7650 | case AArch64::SEL_VG2_2ZC2Z2Z_B: |
| 7651 | case AArch64::SEL_VG2_2ZC2Z2Z_D: |
| 7652 | case AArch64::SEL_VG2_2ZC2Z2Z_H: |
| 7653 | case AArch64::SEL_VG2_2ZC2Z2Z_S: { |
| 7654 | // op: PNg |
| 7655 | op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI); |
| 7656 | Value |= (op & 0x7) << 10; |
| 7657 | // op: Zm |
| 7658 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 3, Fixups, STI); |
| 7659 | Value |= (op & 0xf) << 17; |
| 7660 | // op: Zn |
| 7661 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI); |
| 7662 | Value |= (op & 0xf) << 6; |
| 7663 | // op: Zd |
| 7664 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 7665 | Value |= (op & 0xf) << 1; |
| 7666 | break; |
| 7667 | } |
| 7668 | case AArch64::SEL_VG4_4ZC4Z4Z_B: |
| 7669 | case AArch64::SEL_VG4_4ZC4Z4Z_D: |
| 7670 | case AArch64::SEL_VG4_4ZC4Z4Z_H: |
| 7671 | case AArch64::SEL_VG4_4ZC4Z4Z_S: { |
| 7672 | // op: PNg |
| 7673 | op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI); |
| 7674 | Value |= (op & 0x7) << 10; |
| 7675 | // op: Zm |
| 7676 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 3, Fixups, STI); |
| 7677 | Value |= (op & 0x7) << 18; |
| 7678 | // op: Zn |
| 7679 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 2, Fixups, STI); |
| 7680 | Value |= (op & 0x7) << 7; |
| 7681 | // op: Zd |
| 7682 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 7683 | Value |= (op & 0x7) << 2; |
| 7684 | break; |
| 7685 | } |
| 7686 | case AArch64::WHILEGE_2PXX_B: |
| 7687 | case AArch64::WHILEGE_2PXX_D: |
| 7688 | case AArch64::WHILEGE_2PXX_H: |
| 7689 | case AArch64::WHILEGE_2PXX_S: |
| 7690 | case AArch64::WHILEGT_2PXX_B: |
| 7691 | case AArch64::WHILEGT_2PXX_D: |
| 7692 | case AArch64::WHILEGT_2PXX_H: |
| 7693 | case AArch64::WHILEGT_2PXX_S: |
| 7694 | case AArch64::WHILEHI_2PXX_B: |
| 7695 | case AArch64::WHILEHI_2PXX_D: |
| 7696 | case AArch64::WHILEHI_2PXX_H: |
| 7697 | case AArch64::WHILEHI_2PXX_S: |
| 7698 | case AArch64::WHILEHS_2PXX_B: |
| 7699 | case AArch64::WHILEHS_2PXX_D: |
| 7700 | case AArch64::WHILEHS_2PXX_H: |
| 7701 | case AArch64::WHILEHS_2PXX_S: |
| 7702 | case AArch64::WHILELE_2PXX_B: |
| 7703 | case AArch64::WHILELE_2PXX_D: |
| 7704 | case AArch64::WHILELE_2PXX_H: |
| 7705 | case AArch64::WHILELE_2PXX_S: |
| 7706 | case AArch64::WHILELO_2PXX_B: |
| 7707 | case AArch64::WHILELO_2PXX_D: |
| 7708 | case AArch64::WHILELO_2PXX_H: |
| 7709 | case AArch64::WHILELO_2PXX_S: |
| 7710 | case AArch64::WHILELS_2PXX_B: |
| 7711 | case AArch64::WHILELS_2PXX_D: |
| 7712 | case AArch64::WHILELS_2PXX_H: |
| 7713 | case AArch64::WHILELS_2PXX_S: |
| 7714 | case AArch64::WHILELT_2PXX_B: |
| 7715 | case AArch64::WHILELT_2PXX_D: |
| 7716 | case AArch64::WHILELT_2PXX_H: |
| 7717 | case AArch64::WHILELT_2PXX_S: { |
| 7718 | // op: Pd |
| 7719 | op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 0, Fixups, STI); |
| 7720 | Value |= (op & 0x7) << 1; |
| 7721 | // op: Rn |
| 7722 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7723 | Value |= (op & 0x1f) << 5; |
| 7724 | // op: Rm |
| 7725 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7726 | Value |= (op & 0x1f) << 16; |
| 7727 | break; |
| 7728 | } |
| 7729 | case AArch64::PFALSE: |
| 7730 | case AArch64::RDFFR_P: { |
| 7731 | // op: Pd |
| 7732 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7733 | Value |= (op & 0xf); |
| 7734 | break; |
| 7735 | } |
| 7736 | case AArch64::PEXT_2PCI_B: |
| 7737 | case AArch64::PEXT_2PCI_D: |
| 7738 | case AArch64::PEXT_2PCI_H: |
| 7739 | case AArch64::PEXT_2PCI_S: { |
| 7740 | // op: Pd |
| 7741 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7742 | Value |= (op & 0xf); |
| 7743 | // op: PNn |
| 7744 | op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI); |
| 7745 | Value |= (op & 0x7) << 5; |
| 7746 | // op: index |
| 7747 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7748 | Value |= (op & 0x1) << 8; |
| 7749 | break; |
| 7750 | } |
| 7751 | case AArch64::PEXT_PCI_B: |
| 7752 | case AArch64::PEXT_PCI_D: |
| 7753 | case AArch64::PEXT_PCI_H: |
| 7754 | case AArch64::PEXT_PCI_S: { |
| 7755 | // op: Pd |
| 7756 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7757 | Value |= (op & 0xf); |
| 7758 | // op: PNn |
| 7759 | op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI); |
| 7760 | Value |= (op & 0x7) << 5; |
| 7761 | // op: index |
| 7762 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7763 | Value |= (op & 0x3) << 8; |
| 7764 | break; |
| 7765 | } |
| 7766 | case AArch64::CMPEQ_PPzZZ_B: |
| 7767 | case AArch64::CMPEQ_PPzZZ_D: |
| 7768 | case AArch64::CMPEQ_PPzZZ_H: |
| 7769 | case AArch64::CMPEQ_PPzZZ_S: |
| 7770 | case AArch64::CMPEQ_WIDE_PPzZZ_B: |
| 7771 | case AArch64::CMPEQ_WIDE_PPzZZ_H: |
| 7772 | case AArch64::CMPEQ_WIDE_PPzZZ_S: |
| 7773 | case AArch64::CMPGE_PPzZZ_B: |
| 7774 | case AArch64::CMPGE_PPzZZ_D: |
| 7775 | case AArch64::CMPGE_PPzZZ_H: |
| 7776 | case AArch64::CMPGE_PPzZZ_S: |
| 7777 | case AArch64::CMPGE_WIDE_PPzZZ_B: |
| 7778 | case AArch64::CMPGE_WIDE_PPzZZ_H: |
| 7779 | case AArch64::CMPGE_WIDE_PPzZZ_S: |
| 7780 | case AArch64::CMPGT_PPzZZ_B: |
| 7781 | case AArch64::CMPGT_PPzZZ_D: |
| 7782 | case AArch64::CMPGT_PPzZZ_H: |
| 7783 | case AArch64::CMPGT_PPzZZ_S: |
| 7784 | case AArch64::CMPGT_WIDE_PPzZZ_B: |
| 7785 | case AArch64::CMPGT_WIDE_PPzZZ_H: |
| 7786 | case AArch64::CMPGT_WIDE_PPzZZ_S: |
| 7787 | case AArch64::CMPHI_PPzZZ_B: |
| 7788 | case AArch64::CMPHI_PPzZZ_D: |
| 7789 | case AArch64::CMPHI_PPzZZ_H: |
| 7790 | case AArch64::CMPHI_PPzZZ_S: |
| 7791 | case AArch64::CMPHI_WIDE_PPzZZ_B: |
| 7792 | case AArch64::CMPHI_WIDE_PPzZZ_H: |
| 7793 | case AArch64::CMPHI_WIDE_PPzZZ_S: |
| 7794 | case AArch64::CMPHS_PPzZZ_B: |
| 7795 | case AArch64::CMPHS_PPzZZ_D: |
| 7796 | case AArch64::CMPHS_PPzZZ_H: |
| 7797 | case AArch64::CMPHS_PPzZZ_S: |
| 7798 | case AArch64::CMPHS_WIDE_PPzZZ_B: |
| 7799 | case AArch64::CMPHS_WIDE_PPzZZ_H: |
| 7800 | case AArch64::CMPHS_WIDE_PPzZZ_S: |
| 7801 | case AArch64::CMPLE_WIDE_PPzZZ_B: |
| 7802 | case AArch64::CMPLE_WIDE_PPzZZ_H: |
| 7803 | case AArch64::CMPLE_WIDE_PPzZZ_S: |
| 7804 | case AArch64::CMPLO_WIDE_PPzZZ_B: |
| 7805 | case AArch64::CMPLO_WIDE_PPzZZ_H: |
| 7806 | case AArch64::CMPLO_WIDE_PPzZZ_S: |
| 7807 | case AArch64::CMPLS_WIDE_PPzZZ_B: |
| 7808 | case AArch64::CMPLS_WIDE_PPzZZ_H: |
| 7809 | case AArch64::CMPLS_WIDE_PPzZZ_S: |
| 7810 | case AArch64::CMPLT_WIDE_PPzZZ_B: |
| 7811 | case AArch64::CMPLT_WIDE_PPzZZ_H: |
| 7812 | case AArch64::CMPLT_WIDE_PPzZZ_S: |
| 7813 | case AArch64::CMPNE_PPzZZ_B: |
| 7814 | case AArch64::CMPNE_PPzZZ_D: |
| 7815 | case AArch64::CMPNE_PPzZZ_H: |
| 7816 | case AArch64::CMPNE_PPzZZ_S: |
| 7817 | case AArch64::CMPNE_WIDE_PPzZZ_B: |
| 7818 | case AArch64::CMPNE_WIDE_PPzZZ_H: |
| 7819 | case AArch64::CMPNE_WIDE_PPzZZ_S: |
| 7820 | case AArch64::FACGE_PPzZZ_D: |
| 7821 | case AArch64::FACGE_PPzZZ_H: |
| 7822 | case AArch64::FACGE_PPzZZ_S: |
| 7823 | case AArch64::FACGT_PPzZZ_D: |
| 7824 | case AArch64::FACGT_PPzZZ_H: |
| 7825 | case AArch64::FACGT_PPzZZ_S: |
| 7826 | case AArch64::FCMEQ_PPzZZ_D: |
| 7827 | case AArch64::FCMEQ_PPzZZ_H: |
| 7828 | case AArch64::FCMEQ_PPzZZ_S: |
| 7829 | case AArch64::FCMGE_PPzZZ_D: |
| 7830 | case AArch64::FCMGE_PPzZZ_H: |
| 7831 | case AArch64::FCMGE_PPzZZ_S: |
| 7832 | case AArch64::FCMGT_PPzZZ_D: |
| 7833 | case AArch64::FCMGT_PPzZZ_H: |
| 7834 | case AArch64::FCMGT_PPzZZ_S: |
| 7835 | case AArch64::FCMNE_PPzZZ_D: |
| 7836 | case AArch64::FCMNE_PPzZZ_H: |
| 7837 | case AArch64::FCMNE_PPzZZ_S: |
| 7838 | case AArch64::FCMUO_PPzZZ_D: |
| 7839 | case AArch64::FCMUO_PPzZZ_H: |
| 7840 | case AArch64::FCMUO_PPzZZ_S: |
| 7841 | case AArch64::MATCH_PPzZZ_B: |
| 7842 | case AArch64::MATCH_PPzZZ_H: |
| 7843 | case AArch64::NMATCH_PPzZZ_B: |
| 7844 | case AArch64::NMATCH_PPzZZ_H: { |
| 7845 | // op: Pd |
| 7846 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7847 | Value |= (op & 0xf); |
| 7848 | // op: Pg |
| 7849 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7850 | Value |= (op & 0x7) << 10; |
| 7851 | // op: Zm |
| 7852 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7853 | Value |= (op & 0x1f) << 16; |
| 7854 | // op: Zn |
| 7855 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7856 | Value |= (op & 0x1f) << 5; |
| 7857 | break; |
| 7858 | } |
| 7859 | case AArch64::FCMEQ_PPzZ0_D: |
| 7860 | case AArch64::FCMEQ_PPzZ0_H: |
| 7861 | case AArch64::FCMEQ_PPzZ0_S: |
| 7862 | case AArch64::FCMGE_PPzZ0_D: |
| 7863 | case AArch64::FCMGE_PPzZ0_H: |
| 7864 | case AArch64::FCMGE_PPzZ0_S: |
| 7865 | case AArch64::FCMGT_PPzZ0_D: |
| 7866 | case AArch64::FCMGT_PPzZ0_H: |
| 7867 | case AArch64::FCMGT_PPzZ0_S: |
| 7868 | case AArch64::FCMLE_PPzZ0_D: |
| 7869 | case AArch64::FCMLE_PPzZ0_H: |
| 7870 | case AArch64::FCMLE_PPzZ0_S: |
| 7871 | case AArch64::FCMLT_PPzZ0_D: |
| 7872 | case AArch64::FCMLT_PPzZ0_H: |
| 7873 | case AArch64::FCMLT_PPzZ0_S: |
| 7874 | case AArch64::FCMNE_PPzZ0_D: |
| 7875 | case AArch64::FCMNE_PPzZ0_H: |
| 7876 | case AArch64::FCMNE_PPzZ0_S: { |
| 7877 | // op: Pd |
| 7878 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7879 | Value |= (op & 0xf); |
| 7880 | // op: Pg |
| 7881 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7882 | Value |= (op & 0x7) << 10; |
| 7883 | // op: Zn |
| 7884 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7885 | Value |= (op & 0x1f) << 5; |
| 7886 | break; |
| 7887 | } |
| 7888 | case AArch64::CMPEQ_PPzZI_B: |
| 7889 | case AArch64::CMPEQ_PPzZI_D: |
| 7890 | case AArch64::CMPEQ_PPzZI_H: |
| 7891 | case AArch64::CMPEQ_PPzZI_S: |
| 7892 | case AArch64::CMPGE_PPzZI_B: |
| 7893 | case AArch64::CMPGE_PPzZI_D: |
| 7894 | case AArch64::CMPGE_PPzZI_H: |
| 7895 | case AArch64::CMPGE_PPzZI_S: |
| 7896 | case AArch64::CMPGT_PPzZI_B: |
| 7897 | case AArch64::CMPGT_PPzZI_D: |
| 7898 | case AArch64::CMPGT_PPzZI_H: |
| 7899 | case AArch64::CMPGT_PPzZI_S: |
| 7900 | case AArch64::CMPLE_PPzZI_B: |
| 7901 | case AArch64::CMPLE_PPzZI_D: |
| 7902 | case AArch64::CMPLE_PPzZI_H: |
| 7903 | case AArch64::CMPLE_PPzZI_S: |
| 7904 | case AArch64::CMPLT_PPzZI_B: |
| 7905 | case AArch64::CMPLT_PPzZI_D: |
| 7906 | case AArch64::CMPLT_PPzZI_H: |
| 7907 | case AArch64::CMPLT_PPzZI_S: |
| 7908 | case AArch64::CMPNE_PPzZI_B: |
| 7909 | case AArch64::CMPNE_PPzZI_D: |
| 7910 | case AArch64::CMPNE_PPzZI_H: |
| 7911 | case AArch64::CMPNE_PPzZI_S: { |
| 7912 | // op: Pd |
| 7913 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7914 | Value |= (op & 0xf); |
| 7915 | // op: Pg |
| 7916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7917 | Value |= (op & 0x7) << 10; |
| 7918 | // op: Zn |
| 7919 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7920 | Value |= (op & 0x1f) << 5; |
| 7921 | // op: imm5 |
| 7922 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7923 | Value |= (op & 0x1f) << 16; |
| 7924 | break; |
| 7925 | } |
| 7926 | case AArch64::CMPHI_PPzZI_B: |
| 7927 | case AArch64::CMPHI_PPzZI_D: |
| 7928 | case AArch64::CMPHI_PPzZI_H: |
| 7929 | case AArch64::CMPHI_PPzZI_S: |
| 7930 | case AArch64::CMPHS_PPzZI_B: |
| 7931 | case AArch64::CMPHS_PPzZI_D: |
| 7932 | case AArch64::CMPHS_PPzZI_H: |
| 7933 | case AArch64::CMPHS_PPzZI_S: |
| 7934 | case AArch64::CMPLO_PPzZI_B: |
| 7935 | case AArch64::CMPLO_PPzZI_D: |
| 7936 | case AArch64::CMPLO_PPzZI_H: |
| 7937 | case AArch64::CMPLO_PPzZI_S: |
| 7938 | case AArch64::CMPLS_PPzZI_B: |
| 7939 | case AArch64::CMPLS_PPzZI_D: |
| 7940 | case AArch64::CMPLS_PPzZI_H: |
| 7941 | case AArch64::CMPLS_PPzZI_S: { |
| 7942 | // op: Pd |
| 7943 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7944 | Value |= (op & 0xf); |
| 7945 | // op: Pg |
| 7946 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7947 | Value |= (op & 0x7) << 10; |
| 7948 | // op: Zn |
| 7949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7950 | Value |= (op & 0x1f) << 5; |
| 7951 | // op: imm7 |
| 7952 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7953 | Value |= (op & 0x7f) << 14; |
| 7954 | break; |
| 7955 | } |
| 7956 | case AArch64::ANDS_PPzPP: |
| 7957 | case AArch64::AND_PPzPP: |
| 7958 | case AArch64::BICS_PPzPP: |
| 7959 | case AArch64::BIC_PPzPP: |
| 7960 | case AArch64::BRKPAS_PPzPP: |
| 7961 | case AArch64::BRKPA_PPzPP: |
| 7962 | case AArch64::BRKPBS_PPzPP: |
| 7963 | case AArch64::BRKPB_PPzPP: |
| 7964 | case AArch64::EORS_PPzPP: |
| 7965 | case AArch64::EOR_PPzPP: |
| 7966 | case AArch64::NANDS_PPzPP: |
| 7967 | case AArch64::NAND_PPzPP: |
| 7968 | case AArch64::NORS_PPzPP: |
| 7969 | case AArch64::NOR_PPzPP: |
| 7970 | case AArch64::ORNS_PPzPP: |
| 7971 | case AArch64::ORN_PPzPP: |
| 7972 | case AArch64::ORRS_PPzPP: |
| 7973 | case AArch64::ORR_PPzPP: |
| 7974 | case AArch64::SEL_PPPP: { |
| 7975 | // op: Pd |
| 7976 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7977 | Value |= (op & 0xf); |
| 7978 | // op: Pg |
| 7979 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7980 | Value |= (op & 0xf) << 10; |
| 7981 | // op: Pm |
| 7982 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 7983 | Value |= (op & 0xf) << 16; |
| 7984 | // op: Pn |
| 7985 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 7986 | Value |= (op & 0xf) << 5; |
| 7987 | break; |
| 7988 | } |
| 7989 | case AArch64::BRKAS_PPzP: |
| 7990 | case AArch64::BRKA_PPzP: |
| 7991 | case AArch64::BRKBS_PPzP: |
| 7992 | case AArch64::BRKB_PPzP: { |
| 7993 | // op: Pd |
| 7994 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 7995 | Value |= (op & 0xf); |
| 7996 | // op: Pg |
| 7997 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 7998 | Value |= (op & 0xf) << 10; |
| 7999 | // op: Pn |
| 8000 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8001 | Value |= (op & 0xf) << 5; |
| 8002 | break; |
| 8003 | } |
| 8004 | case AArch64::RDFFRS_PPz: |
| 8005 | case AArch64::RDFFR_PPz: { |
| 8006 | // op: Pd |
| 8007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8008 | Value |= (op & 0xf); |
| 8009 | // op: Pg |
| 8010 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8011 | Value |= (op & 0xf) << 5; |
| 8012 | break; |
| 8013 | } |
| 8014 | case AArch64::BRKA_PPmP: |
| 8015 | case AArch64::BRKB_PPmP: { |
| 8016 | // op: Pd |
| 8017 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8018 | Value |= (op & 0xf); |
| 8019 | // op: Pg |
| 8020 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8021 | Value |= (op & 0xf) << 10; |
| 8022 | // op: Pn |
| 8023 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8024 | Value |= (op & 0xf) << 5; |
| 8025 | break; |
| 8026 | } |
| 8027 | case AArch64::TRN1_PPP_B: |
| 8028 | case AArch64::TRN1_PPP_D: |
| 8029 | case AArch64::TRN1_PPP_H: |
| 8030 | case AArch64::TRN1_PPP_S: |
| 8031 | case AArch64::TRN2_PPP_B: |
| 8032 | case AArch64::TRN2_PPP_D: |
| 8033 | case AArch64::TRN2_PPP_H: |
| 8034 | case AArch64::TRN2_PPP_S: |
| 8035 | case AArch64::UZP1_PPP_B: |
| 8036 | case AArch64::UZP1_PPP_D: |
| 8037 | case AArch64::UZP1_PPP_H: |
| 8038 | case AArch64::UZP1_PPP_S: |
| 8039 | case AArch64::UZP2_PPP_B: |
| 8040 | case AArch64::UZP2_PPP_D: |
| 8041 | case AArch64::UZP2_PPP_H: |
| 8042 | case AArch64::UZP2_PPP_S: |
| 8043 | case AArch64::ZIP1_PPP_B: |
| 8044 | case AArch64::ZIP1_PPP_D: |
| 8045 | case AArch64::ZIP1_PPP_H: |
| 8046 | case AArch64::ZIP1_PPP_S: |
| 8047 | case AArch64::ZIP2_PPP_B: |
| 8048 | case AArch64::ZIP2_PPP_D: |
| 8049 | case AArch64::ZIP2_PPP_H: |
| 8050 | case AArch64::ZIP2_PPP_S: { |
| 8051 | // op: Pd |
| 8052 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8053 | Value |= (op & 0xf); |
| 8054 | // op: Pm |
| 8055 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8056 | Value |= (op & 0xf) << 16; |
| 8057 | // op: Pn |
| 8058 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8059 | Value |= (op & 0xf) << 5; |
| 8060 | break; |
| 8061 | } |
| 8062 | case AArch64::PUNPKHI_PP: |
| 8063 | case AArch64::PUNPKLO_PP: |
| 8064 | case AArch64::REV_PP_B: |
| 8065 | case AArch64::REV_PP_D: |
| 8066 | case AArch64::REV_PP_H: |
| 8067 | case AArch64::REV_PP_S: { |
| 8068 | // op: Pd |
| 8069 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8070 | Value |= (op & 0xf); |
| 8071 | // op: Pn |
| 8072 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8073 | Value |= (op & 0xf) << 5; |
| 8074 | break; |
| 8075 | } |
| 8076 | case AArch64::WHILEGE_PWW_B: |
| 8077 | case AArch64::WHILEGE_PWW_D: |
| 8078 | case AArch64::WHILEGE_PWW_H: |
| 8079 | case AArch64::WHILEGE_PWW_S: |
| 8080 | case AArch64::WHILEGE_PXX_B: |
| 8081 | case AArch64::WHILEGE_PXX_D: |
| 8082 | case AArch64::WHILEGE_PXX_H: |
| 8083 | case AArch64::WHILEGE_PXX_S: |
| 8084 | case AArch64::WHILEGT_PWW_B: |
| 8085 | case AArch64::WHILEGT_PWW_D: |
| 8086 | case AArch64::WHILEGT_PWW_H: |
| 8087 | case AArch64::WHILEGT_PWW_S: |
| 8088 | case AArch64::WHILEGT_PXX_B: |
| 8089 | case AArch64::WHILEGT_PXX_D: |
| 8090 | case AArch64::WHILEGT_PXX_H: |
| 8091 | case AArch64::WHILEGT_PXX_S: |
| 8092 | case AArch64::WHILEHI_PWW_B: |
| 8093 | case AArch64::WHILEHI_PWW_D: |
| 8094 | case AArch64::WHILEHI_PWW_H: |
| 8095 | case AArch64::WHILEHI_PWW_S: |
| 8096 | case AArch64::WHILEHI_PXX_B: |
| 8097 | case AArch64::WHILEHI_PXX_D: |
| 8098 | case AArch64::WHILEHI_PXX_H: |
| 8099 | case AArch64::WHILEHI_PXX_S: |
| 8100 | case AArch64::WHILEHS_PWW_B: |
| 8101 | case AArch64::WHILEHS_PWW_D: |
| 8102 | case AArch64::WHILEHS_PWW_H: |
| 8103 | case AArch64::WHILEHS_PWW_S: |
| 8104 | case AArch64::WHILEHS_PXX_B: |
| 8105 | case AArch64::WHILEHS_PXX_D: |
| 8106 | case AArch64::WHILEHS_PXX_H: |
| 8107 | case AArch64::WHILEHS_PXX_S: |
| 8108 | case AArch64::WHILELE_PWW_B: |
| 8109 | case AArch64::WHILELE_PWW_D: |
| 8110 | case AArch64::WHILELE_PWW_H: |
| 8111 | case AArch64::WHILELE_PWW_S: |
| 8112 | case AArch64::WHILELE_PXX_B: |
| 8113 | case AArch64::WHILELE_PXX_D: |
| 8114 | case AArch64::WHILELE_PXX_H: |
| 8115 | case AArch64::WHILELE_PXX_S: |
| 8116 | case AArch64::WHILELO_PWW_B: |
| 8117 | case AArch64::WHILELO_PWW_D: |
| 8118 | case AArch64::WHILELO_PWW_H: |
| 8119 | case AArch64::WHILELO_PWW_S: |
| 8120 | case AArch64::WHILELO_PXX_B: |
| 8121 | case AArch64::WHILELO_PXX_D: |
| 8122 | case AArch64::WHILELO_PXX_H: |
| 8123 | case AArch64::WHILELO_PXX_S: |
| 8124 | case AArch64::WHILELS_PWW_B: |
| 8125 | case AArch64::WHILELS_PWW_D: |
| 8126 | case AArch64::WHILELS_PWW_H: |
| 8127 | case AArch64::WHILELS_PWW_S: |
| 8128 | case AArch64::WHILELS_PXX_B: |
| 8129 | case AArch64::WHILELS_PXX_D: |
| 8130 | case AArch64::WHILELS_PXX_H: |
| 8131 | case AArch64::WHILELS_PXX_S: |
| 8132 | case AArch64::WHILELT_PWW_B: |
| 8133 | case AArch64::WHILELT_PWW_D: |
| 8134 | case AArch64::WHILELT_PWW_H: |
| 8135 | case AArch64::WHILELT_PWW_S: |
| 8136 | case AArch64::WHILELT_PXX_B: |
| 8137 | case AArch64::WHILELT_PXX_D: |
| 8138 | case AArch64::WHILELT_PXX_H: |
| 8139 | case AArch64::WHILELT_PXX_S: |
| 8140 | case AArch64::WHILERW_PXX_B: |
| 8141 | case AArch64::WHILERW_PXX_D: |
| 8142 | case AArch64::WHILERW_PXX_H: |
| 8143 | case AArch64::WHILERW_PXX_S: |
| 8144 | case AArch64::WHILEWR_PXX_B: |
| 8145 | case AArch64::WHILEWR_PXX_D: |
| 8146 | case AArch64::WHILEWR_PXX_H: |
| 8147 | case AArch64::WHILEWR_PXX_S: { |
| 8148 | // op: Pd |
| 8149 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8150 | Value |= (op & 0xf); |
| 8151 | // op: Rm |
| 8152 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8153 | Value |= (op & 0x1f) << 16; |
| 8154 | // op: Rn |
| 8155 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8156 | Value |= (op & 0x1f) << 5; |
| 8157 | break; |
| 8158 | } |
| 8159 | case AArch64::PMOV_PZI_B: { |
| 8160 | // op: Pd |
| 8161 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8162 | Value |= (op & 0xf); |
| 8163 | // op: Zn |
| 8164 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8165 | Value |= (op & 0x1f) << 5; |
| 8166 | break; |
| 8167 | } |
| 8168 | case AArch64::PMOV_PZI_H: { |
| 8169 | // op: Pd |
| 8170 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8171 | Value |= (op & 0xf); |
| 8172 | // op: Zn |
| 8173 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8174 | Value |= (op & 0x1f) << 5; |
| 8175 | // op: index |
| 8176 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8177 | Value |= (op & 0x1) << 17; |
| 8178 | break; |
| 8179 | } |
| 8180 | case AArch64::PMOV_PZI_S: { |
| 8181 | // op: Pd |
| 8182 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8183 | Value |= (op & 0xf); |
| 8184 | // op: Zn |
| 8185 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8186 | Value |= (op & 0x1f) << 5; |
| 8187 | // op: index |
| 8188 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8189 | Value |= (op & 0x3) << 17; |
| 8190 | break; |
| 8191 | } |
| 8192 | case AArch64::PMOV_PZI_D: { |
| 8193 | // op: Pd |
| 8194 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8195 | Value |= (op & 0xf); |
| 8196 | // op: Zn |
| 8197 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8198 | Value |= (op & 0x1f) << 5; |
| 8199 | // op: index |
| 8200 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8201 | Value |= (op & 0x4) << 20; |
| 8202 | Value |= (op & 0x3) << 17; |
| 8203 | break; |
| 8204 | } |
| 8205 | case AArch64::PTRUES_B: |
| 8206 | case AArch64::PTRUES_D: |
| 8207 | case AArch64::PTRUES_H: |
| 8208 | case AArch64::PTRUES_S: |
| 8209 | case AArch64::PTRUE_B: |
| 8210 | case AArch64::PTRUE_D: |
| 8211 | case AArch64::PTRUE_H: |
| 8212 | case AArch64::PTRUE_S: { |
| 8213 | // op: Pd |
| 8214 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8215 | Value |= (op & 0xf); |
| 8216 | // op: pattern |
| 8217 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8218 | Value |= (op & 0x1f) << 5; |
| 8219 | break; |
| 8220 | } |
| 8221 | case AArch64::BRKNS_PPzP: |
| 8222 | case AArch64::BRKN_PPzP: { |
| 8223 | // op: Pdm |
| 8224 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8225 | Value |= (op & 0xf); |
| 8226 | // op: Pg |
| 8227 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8228 | Value |= (op & 0xf) << 10; |
| 8229 | // op: Pn |
| 8230 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8231 | Value |= (op & 0xf) << 5; |
| 8232 | break; |
| 8233 | } |
| 8234 | case AArch64::PFIRST_B: |
| 8235 | case AArch64::PNEXT_B: |
| 8236 | case AArch64::PNEXT_D: |
| 8237 | case AArch64::PNEXT_H: |
| 8238 | case AArch64::PNEXT_S: { |
| 8239 | // op: Pdn |
| 8240 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8241 | Value |= (op & 0xf); |
| 8242 | // op: Pg |
| 8243 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8244 | Value |= (op & 0xf) << 5; |
| 8245 | break; |
| 8246 | } |
| 8247 | case AArch64::PTEST_PP: { |
| 8248 | // op: Pg |
| 8249 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8250 | Value |= (op & 0xf) << 10; |
| 8251 | // op: Pn |
| 8252 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8253 | Value |= (op & 0xf) << 5; |
| 8254 | break; |
| 8255 | } |
| 8256 | case AArch64::LASTA_RPZ_B: |
| 8257 | case AArch64::LASTA_RPZ_D: |
| 8258 | case AArch64::LASTA_RPZ_H: |
| 8259 | case AArch64::LASTA_RPZ_S: |
| 8260 | case AArch64::LASTB_RPZ_B: |
| 8261 | case AArch64::LASTB_RPZ_D: |
| 8262 | case AArch64::LASTB_RPZ_H: |
| 8263 | case AArch64::LASTB_RPZ_S: { |
| 8264 | // op: Pg |
| 8265 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8266 | Value |= (op & 0x7) << 10; |
| 8267 | // op: Rd |
| 8268 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8269 | Value |= (op & 0x1f); |
| 8270 | // op: Zn |
| 8271 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8272 | Value |= (op & 0x1f) << 5; |
| 8273 | break; |
| 8274 | } |
| 8275 | case AArch64::CLASTA_RPZ_B: |
| 8276 | case AArch64::CLASTA_RPZ_D: |
| 8277 | case AArch64::CLASTA_RPZ_H: |
| 8278 | case AArch64::CLASTA_RPZ_S: |
| 8279 | case AArch64::CLASTB_RPZ_B: |
| 8280 | case AArch64::CLASTB_RPZ_D: |
| 8281 | case AArch64::CLASTB_RPZ_H: |
| 8282 | case AArch64::CLASTB_RPZ_S: { |
| 8283 | // op: Pg |
| 8284 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8285 | Value |= (op & 0x7) << 10; |
| 8286 | // op: Rdn |
| 8287 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8288 | Value |= (op & 0x1f); |
| 8289 | // op: Zm |
| 8290 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8291 | Value |= (op & 0x1f) << 5; |
| 8292 | break; |
| 8293 | } |
| 8294 | case AArch64::LD2B: |
| 8295 | case AArch64::LD2D: |
| 8296 | case AArch64::LD2H: |
| 8297 | case AArch64::LD2Q: |
| 8298 | case AArch64::LD2W: |
| 8299 | case AArch64::LD3B: |
| 8300 | case AArch64::LD3D: |
| 8301 | case AArch64::LD3H: |
| 8302 | case AArch64::LD3Q: |
| 8303 | case AArch64::LD3W: |
| 8304 | case AArch64::LD4B: |
| 8305 | case AArch64::LD4D: |
| 8306 | case AArch64::LD4H: |
| 8307 | case AArch64::LD4Q: |
| 8308 | case AArch64::LD4W: |
| 8309 | case AArch64::LDNT1B_ZRR: |
| 8310 | case AArch64::LDNT1D_ZRR: |
| 8311 | case AArch64::LDNT1H_ZRR: |
| 8312 | case AArch64::LDNT1W_ZRR: |
| 8313 | case AArch64::ST1B: |
| 8314 | case AArch64::ST1B_D: |
| 8315 | case AArch64::ST1B_H: |
| 8316 | case AArch64::ST1B_S: |
| 8317 | case AArch64::ST1D: |
| 8318 | case AArch64::ST1D_Q: |
| 8319 | case AArch64::ST1H: |
| 8320 | case AArch64::ST1H_D: |
| 8321 | case AArch64::ST1H_S: |
| 8322 | case AArch64::ST1W: |
| 8323 | case AArch64::ST1W_D: |
| 8324 | case AArch64::ST1W_Q: |
| 8325 | case AArch64::ST2B: |
| 8326 | case AArch64::ST2D: |
| 8327 | case AArch64::ST2H: |
| 8328 | case AArch64::ST2W: |
| 8329 | case AArch64::ST3B: |
| 8330 | case AArch64::ST3D: |
| 8331 | case AArch64::ST3H: |
| 8332 | case AArch64::ST3W: |
| 8333 | case AArch64::ST4B: |
| 8334 | case AArch64::ST4D: |
| 8335 | case AArch64::ST4H: |
| 8336 | case AArch64::ST4W: |
| 8337 | case AArch64::STNT1B_ZRR: |
| 8338 | case AArch64::STNT1D_ZRR: |
| 8339 | case AArch64::STNT1H_ZRR: |
| 8340 | case AArch64::STNT1W_ZRR: { |
| 8341 | // op: Pg |
| 8342 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8343 | Value |= (op & 0x7) << 10; |
| 8344 | // op: Rm |
| 8345 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8346 | Value |= (op & 0x1f) << 16; |
| 8347 | // op: Rn |
| 8348 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8349 | Value |= (op & 0x1f) << 5; |
| 8350 | // op: Zt |
| 8351 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8352 | Value |= (op & 0x1f); |
| 8353 | break; |
| 8354 | } |
| 8355 | case AArch64::LDNT1B_ZZR_D: |
| 8356 | case AArch64::LDNT1B_ZZR_S: |
| 8357 | case AArch64::LDNT1D_ZZR_D: |
| 8358 | case AArch64::LDNT1H_ZZR_D: |
| 8359 | case AArch64::LDNT1H_ZZR_S: |
| 8360 | case AArch64::LDNT1SB_ZZR_D: |
| 8361 | case AArch64::LDNT1SB_ZZR_S: |
| 8362 | case AArch64::LDNT1SH_ZZR_D: |
| 8363 | case AArch64::LDNT1SH_ZZR_S: |
| 8364 | case AArch64::LDNT1SW_ZZR_D: |
| 8365 | case AArch64::LDNT1W_ZZR_D: |
| 8366 | case AArch64::LDNT1W_ZZR_S: |
| 8367 | case AArch64::STNT1B_ZZR_D: |
| 8368 | case AArch64::STNT1B_ZZR_S: |
| 8369 | case AArch64::STNT1D_ZZR_D: |
| 8370 | case AArch64::STNT1H_ZZR_D: |
| 8371 | case AArch64::STNT1H_ZZR_S: |
| 8372 | case AArch64::STNT1W_ZZR_D: |
| 8373 | case AArch64::STNT1W_ZZR_S: { |
| 8374 | // op: Pg |
| 8375 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8376 | Value |= (op & 0x7) << 10; |
| 8377 | // op: Rm |
| 8378 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8379 | Value |= (op & 0x1f) << 16; |
| 8380 | // op: Zn |
| 8381 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8382 | Value |= (op & 0x1f) << 5; |
| 8383 | // op: Zt |
| 8384 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8385 | Value |= (op & 0x1f); |
| 8386 | break; |
| 8387 | } |
| 8388 | case AArch64::GLD1B_D: |
| 8389 | case AArch64::GLD1B_D_SXTW: |
| 8390 | case AArch64::GLD1B_D_UXTW: |
| 8391 | case AArch64::GLD1B_S_SXTW: |
| 8392 | case AArch64::GLD1B_S_UXTW: |
| 8393 | case AArch64::GLD1D: |
| 8394 | case AArch64::GLD1D_SCALED: |
| 8395 | case AArch64::GLD1D_SXTW: |
| 8396 | case AArch64::GLD1D_SXTW_SCALED: |
| 8397 | case AArch64::GLD1D_UXTW: |
| 8398 | case AArch64::GLD1D_UXTW_SCALED: |
| 8399 | case AArch64::GLD1H_D: |
| 8400 | case AArch64::GLD1H_D_SCALED: |
| 8401 | case AArch64::GLD1H_D_SXTW: |
| 8402 | case AArch64::GLD1H_D_SXTW_SCALED: |
| 8403 | case AArch64::GLD1H_D_UXTW: |
| 8404 | case AArch64::GLD1H_D_UXTW_SCALED: |
| 8405 | case AArch64::GLD1H_S_SXTW: |
| 8406 | case AArch64::GLD1H_S_SXTW_SCALED: |
| 8407 | case AArch64::GLD1H_S_UXTW: |
| 8408 | case AArch64::GLD1H_S_UXTW_SCALED: |
| 8409 | case AArch64::GLD1SB_D: |
| 8410 | case AArch64::GLD1SB_D_SXTW: |
| 8411 | case AArch64::GLD1SB_D_UXTW: |
| 8412 | case AArch64::GLD1SB_S_SXTW: |
| 8413 | case AArch64::GLD1SB_S_UXTW: |
| 8414 | case AArch64::GLD1SH_D: |
| 8415 | case AArch64::GLD1SH_D_SCALED: |
| 8416 | case AArch64::GLD1SH_D_SXTW: |
| 8417 | case AArch64::GLD1SH_D_SXTW_SCALED: |
| 8418 | case AArch64::GLD1SH_D_UXTW: |
| 8419 | case AArch64::GLD1SH_D_UXTW_SCALED: |
| 8420 | case AArch64::GLD1SH_S_SXTW: |
| 8421 | case AArch64::GLD1SH_S_SXTW_SCALED: |
| 8422 | case AArch64::GLD1SH_S_UXTW: |
| 8423 | case AArch64::GLD1SH_S_UXTW_SCALED: |
| 8424 | case AArch64::GLD1SW_D: |
| 8425 | case AArch64::GLD1SW_D_SCALED: |
| 8426 | case AArch64::GLD1SW_D_SXTW: |
| 8427 | case AArch64::GLD1SW_D_SXTW_SCALED: |
| 8428 | case AArch64::GLD1SW_D_UXTW: |
| 8429 | case AArch64::GLD1SW_D_UXTW_SCALED: |
| 8430 | case AArch64::GLD1W_D: |
| 8431 | case AArch64::GLD1W_D_SCALED: |
| 8432 | case AArch64::GLD1W_D_SXTW: |
| 8433 | case AArch64::GLD1W_D_SXTW_SCALED: |
| 8434 | case AArch64::GLD1W_D_UXTW: |
| 8435 | case AArch64::GLD1W_D_UXTW_SCALED: |
| 8436 | case AArch64::GLD1W_SXTW: |
| 8437 | case AArch64::GLD1W_SXTW_SCALED: |
| 8438 | case AArch64::GLD1W_UXTW: |
| 8439 | case AArch64::GLD1W_UXTW_SCALED: |
| 8440 | case AArch64::GLDFF1B_D: |
| 8441 | case AArch64::GLDFF1B_D_SXTW: |
| 8442 | case AArch64::GLDFF1B_D_UXTW: |
| 8443 | case AArch64::GLDFF1B_S_SXTW: |
| 8444 | case AArch64::GLDFF1B_S_UXTW: |
| 8445 | case AArch64::GLDFF1D: |
| 8446 | case AArch64::GLDFF1D_SCALED: |
| 8447 | case AArch64::GLDFF1D_SXTW: |
| 8448 | case AArch64::GLDFF1D_SXTW_SCALED: |
| 8449 | case AArch64::GLDFF1D_UXTW: |
| 8450 | case AArch64::GLDFF1D_UXTW_SCALED: |
| 8451 | case AArch64::GLDFF1H_D: |
| 8452 | case AArch64::GLDFF1H_D_SCALED: |
| 8453 | case AArch64::GLDFF1H_D_SXTW: |
| 8454 | case AArch64::GLDFF1H_D_SXTW_SCALED: |
| 8455 | case AArch64::GLDFF1H_D_UXTW: |
| 8456 | case AArch64::GLDFF1H_D_UXTW_SCALED: |
| 8457 | case AArch64::GLDFF1H_S_SXTW: |
| 8458 | case AArch64::GLDFF1H_S_SXTW_SCALED: |
| 8459 | case AArch64::GLDFF1H_S_UXTW: |
| 8460 | case AArch64::GLDFF1H_S_UXTW_SCALED: |
| 8461 | case AArch64::GLDFF1SB_D: |
| 8462 | case AArch64::GLDFF1SB_D_SXTW: |
| 8463 | case AArch64::GLDFF1SB_D_UXTW: |
| 8464 | case AArch64::GLDFF1SB_S_SXTW: |
| 8465 | case AArch64::GLDFF1SB_S_UXTW: |
| 8466 | case AArch64::GLDFF1SH_D: |
| 8467 | case AArch64::GLDFF1SH_D_SCALED: |
| 8468 | case AArch64::GLDFF1SH_D_SXTW: |
| 8469 | case AArch64::GLDFF1SH_D_SXTW_SCALED: |
| 8470 | case AArch64::GLDFF1SH_D_UXTW: |
| 8471 | case AArch64::GLDFF1SH_D_UXTW_SCALED: |
| 8472 | case AArch64::GLDFF1SH_S_SXTW: |
| 8473 | case AArch64::GLDFF1SH_S_SXTW_SCALED: |
| 8474 | case AArch64::GLDFF1SH_S_UXTW: |
| 8475 | case AArch64::GLDFF1SH_S_UXTW_SCALED: |
| 8476 | case AArch64::GLDFF1SW_D: |
| 8477 | case AArch64::GLDFF1SW_D_SCALED: |
| 8478 | case AArch64::GLDFF1SW_D_SXTW: |
| 8479 | case AArch64::GLDFF1SW_D_SXTW_SCALED: |
| 8480 | case AArch64::GLDFF1SW_D_UXTW: |
| 8481 | case AArch64::GLDFF1SW_D_UXTW_SCALED: |
| 8482 | case AArch64::GLDFF1W_D: |
| 8483 | case AArch64::GLDFF1W_D_SCALED: |
| 8484 | case AArch64::GLDFF1W_D_SXTW: |
| 8485 | case AArch64::GLDFF1W_D_SXTW_SCALED: |
| 8486 | case AArch64::GLDFF1W_D_UXTW: |
| 8487 | case AArch64::GLDFF1W_D_UXTW_SCALED: |
| 8488 | case AArch64::GLDFF1W_SXTW: |
| 8489 | case AArch64::GLDFF1W_SXTW_SCALED: |
| 8490 | case AArch64::GLDFF1W_UXTW: |
| 8491 | case AArch64::GLDFF1W_UXTW_SCALED: |
| 8492 | case AArch64::SST1B_D: |
| 8493 | case AArch64::SST1B_D_SXTW: |
| 8494 | case AArch64::SST1B_D_UXTW: |
| 8495 | case AArch64::SST1B_S_SXTW: |
| 8496 | case AArch64::SST1B_S_UXTW: |
| 8497 | case AArch64::SST1D: |
| 8498 | case AArch64::SST1D_SCALED: |
| 8499 | case AArch64::SST1D_SXTW: |
| 8500 | case AArch64::SST1D_SXTW_SCALED: |
| 8501 | case AArch64::SST1D_UXTW: |
| 8502 | case AArch64::SST1D_UXTW_SCALED: |
| 8503 | case AArch64::SST1H_D: |
| 8504 | case AArch64::SST1H_D_SCALED: |
| 8505 | case AArch64::SST1H_D_SXTW: |
| 8506 | case AArch64::SST1H_D_SXTW_SCALED: |
| 8507 | case AArch64::SST1H_D_UXTW: |
| 8508 | case AArch64::SST1H_D_UXTW_SCALED: |
| 8509 | case AArch64::SST1H_S_SXTW: |
| 8510 | case AArch64::SST1H_S_SXTW_SCALED: |
| 8511 | case AArch64::SST1H_S_UXTW: |
| 8512 | case AArch64::SST1H_S_UXTW_SCALED: |
| 8513 | case AArch64::SST1W_D: |
| 8514 | case AArch64::SST1W_D_SCALED: |
| 8515 | case AArch64::SST1W_D_SXTW: |
| 8516 | case AArch64::SST1W_D_SXTW_SCALED: |
| 8517 | case AArch64::SST1W_D_UXTW: |
| 8518 | case AArch64::SST1W_D_UXTW_SCALED: |
| 8519 | case AArch64::SST1W_SXTW: |
| 8520 | case AArch64::SST1W_SXTW_SCALED: |
| 8521 | case AArch64::SST1W_UXTW: |
| 8522 | case AArch64::SST1W_UXTW_SCALED: { |
| 8523 | // op: Pg |
| 8524 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8525 | Value |= (op & 0x7) << 10; |
| 8526 | // op: Rn |
| 8527 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8528 | Value |= (op & 0x1f) << 5; |
| 8529 | // op: Zm |
| 8530 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8531 | Value |= (op & 0x1f) << 16; |
| 8532 | // op: Zt |
| 8533 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8534 | Value |= (op & 0x1f); |
| 8535 | break; |
| 8536 | } |
| 8537 | case AArch64::PRFB_D_SCALED: |
| 8538 | case AArch64::PRFB_D_SXTW_SCALED: |
| 8539 | case AArch64::PRFB_D_UXTW_SCALED: |
| 8540 | case AArch64::PRFB_S_SXTW_SCALED: |
| 8541 | case AArch64::PRFB_S_UXTW_SCALED: |
| 8542 | case AArch64::PRFD_D_SCALED: |
| 8543 | case AArch64::PRFD_D_SXTW_SCALED: |
| 8544 | case AArch64::PRFD_D_UXTW_SCALED: |
| 8545 | case AArch64::PRFD_S_SXTW_SCALED: |
| 8546 | case AArch64::PRFD_S_UXTW_SCALED: |
| 8547 | case AArch64::PRFH_D_SCALED: |
| 8548 | case AArch64::PRFH_D_SXTW_SCALED: |
| 8549 | case AArch64::PRFH_D_UXTW_SCALED: |
| 8550 | case AArch64::PRFH_S_SXTW_SCALED: |
| 8551 | case AArch64::PRFH_S_UXTW_SCALED: |
| 8552 | case AArch64::PRFW_D_SCALED: |
| 8553 | case AArch64::PRFW_D_SXTW_SCALED: |
| 8554 | case AArch64::PRFW_D_UXTW_SCALED: |
| 8555 | case AArch64::PRFW_S_SXTW_SCALED: |
| 8556 | case AArch64::PRFW_S_UXTW_SCALED: { |
| 8557 | // op: Pg |
| 8558 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8559 | Value |= (op & 0x7) << 10; |
| 8560 | // op: Rn |
| 8561 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8562 | Value |= (op & 0x1f) << 5; |
| 8563 | // op: Zm |
| 8564 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8565 | Value |= (op & 0x1f) << 16; |
| 8566 | // op: prfop |
| 8567 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8568 | Value |= (op & 0xf); |
| 8569 | break; |
| 8570 | } |
| 8571 | case AArch64::LD1B_D_IMM: |
| 8572 | case AArch64::LD1B_H_IMM: |
| 8573 | case AArch64::LD1B_IMM: |
| 8574 | case AArch64::LD1B_S_IMM: |
| 8575 | case AArch64::LD1D_IMM: |
| 8576 | case AArch64::LD1H_D_IMM: |
| 8577 | case AArch64::LD1H_IMM: |
| 8578 | case AArch64::LD1H_S_IMM: |
| 8579 | case AArch64::LD1SB_D_IMM: |
| 8580 | case AArch64::LD1SB_H_IMM: |
| 8581 | case AArch64::LD1SB_S_IMM: |
| 8582 | case AArch64::LD1SH_D_IMM: |
| 8583 | case AArch64::LD1SH_S_IMM: |
| 8584 | case AArch64::LD1SW_D_IMM: |
| 8585 | case AArch64::LD1W_D_IMM: |
| 8586 | case AArch64::LD1W_IMM: |
| 8587 | case AArch64::LDNF1B_D_IMM: |
| 8588 | case AArch64::LDNF1B_H_IMM: |
| 8589 | case AArch64::LDNF1B_IMM: |
| 8590 | case AArch64::LDNF1B_S_IMM: |
| 8591 | case AArch64::LDNF1D_IMM: |
| 8592 | case AArch64::LDNF1H_D_IMM: |
| 8593 | case AArch64::LDNF1H_IMM: |
| 8594 | case AArch64::LDNF1H_S_IMM: |
| 8595 | case AArch64::LDNF1SB_D_IMM: |
| 8596 | case AArch64::LDNF1SB_H_IMM: |
| 8597 | case AArch64::LDNF1SB_S_IMM: |
| 8598 | case AArch64::LDNF1SH_D_IMM: |
| 8599 | case AArch64::LDNF1SH_S_IMM: |
| 8600 | case AArch64::LDNF1SW_D_IMM: |
| 8601 | case AArch64::LDNF1W_D_IMM: |
| 8602 | case AArch64::LDNF1W_IMM: |
| 8603 | case AArch64::ST1B_D_IMM: |
| 8604 | case AArch64::ST1B_H_IMM: |
| 8605 | case AArch64::ST1B_IMM: |
| 8606 | case AArch64::ST1B_S_IMM: |
| 8607 | case AArch64::ST1D_IMM: |
| 8608 | case AArch64::ST1D_Q_IMM: |
| 8609 | case AArch64::ST1H_D_IMM: |
| 8610 | case AArch64::ST1H_IMM: |
| 8611 | case AArch64::ST1H_S_IMM: |
| 8612 | case AArch64::ST1W_D_IMM: |
| 8613 | case AArch64::ST1W_IMM: |
| 8614 | case AArch64::ST1W_Q_IMM: |
| 8615 | case AArch64::ST2B_IMM: |
| 8616 | case AArch64::ST2D_IMM: |
| 8617 | case AArch64::ST2H_IMM: |
| 8618 | case AArch64::ST2W_IMM: |
| 8619 | case AArch64::ST3B_IMM: |
| 8620 | case AArch64::ST3D_IMM: |
| 8621 | case AArch64::ST3H_IMM: |
| 8622 | case AArch64::ST3W_IMM: |
| 8623 | case AArch64::ST4B_IMM: |
| 8624 | case AArch64::ST4D_IMM: |
| 8625 | case AArch64::ST4H_IMM: |
| 8626 | case AArch64::ST4W_IMM: |
| 8627 | case AArch64::STNT1B_ZRI: |
| 8628 | case AArch64::STNT1D_ZRI: |
| 8629 | case AArch64::STNT1H_ZRI: |
| 8630 | case AArch64::STNT1W_ZRI: { |
| 8631 | // op: Pg |
| 8632 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8633 | Value |= (op & 0x7) << 10; |
| 8634 | // op: Rn |
| 8635 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8636 | Value |= (op & 0x1f) << 5; |
| 8637 | // op: Zt |
| 8638 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8639 | Value |= (op & 0x1f); |
| 8640 | // op: imm4 |
| 8641 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8642 | Value |= (op & 0xf) << 16; |
| 8643 | break; |
| 8644 | } |
| 8645 | case AArch64::LD1RB_D_IMM: |
| 8646 | case AArch64::LD1RB_H_IMM: |
| 8647 | case AArch64::LD1RB_IMM: |
| 8648 | case AArch64::LD1RB_S_IMM: |
| 8649 | case AArch64::LD1RD_IMM: |
| 8650 | case AArch64::LD1RH_D_IMM: |
| 8651 | case AArch64::LD1RH_IMM: |
| 8652 | case AArch64::LD1RH_S_IMM: |
| 8653 | case AArch64::LD1RSB_D_IMM: |
| 8654 | case AArch64::LD1RSB_H_IMM: |
| 8655 | case AArch64::LD1RSB_S_IMM: |
| 8656 | case AArch64::LD1RSH_D_IMM: |
| 8657 | case AArch64::LD1RSH_S_IMM: |
| 8658 | case AArch64::LD1RSW_IMM: |
| 8659 | case AArch64::LD1RW_D_IMM: |
| 8660 | case AArch64::LD1RW_IMM: { |
| 8661 | // op: Pg |
| 8662 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8663 | Value |= (op & 0x7) << 10; |
| 8664 | // op: Rn |
| 8665 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8666 | Value |= (op & 0x1f) << 5; |
| 8667 | // op: Zt |
| 8668 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8669 | Value |= (op & 0x1f); |
| 8670 | // op: imm6 |
| 8671 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8672 | Value |= (op & 0x3f) << 16; |
| 8673 | break; |
| 8674 | } |
| 8675 | case AArch64::ANDV_VPZ_B: |
| 8676 | case AArch64::ANDV_VPZ_D: |
| 8677 | case AArch64::ANDV_VPZ_H: |
| 8678 | case AArch64::ANDV_VPZ_S: |
| 8679 | case AArch64::EORV_VPZ_B: |
| 8680 | case AArch64::EORV_VPZ_D: |
| 8681 | case AArch64::EORV_VPZ_H: |
| 8682 | case AArch64::EORV_VPZ_S: |
| 8683 | case AArch64::LASTA_VPZ_B: |
| 8684 | case AArch64::LASTA_VPZ_D: |
| 8685 | case AArch64::LASTA_VPZ_H: |
| 8686 | case AArch64::LASTA_VPZ_S: |
| 8687 | case AArch64::LASTB_VPZ_B: |
| 8688 | case AArch64::LASTB_VPZ_D: |
| 8689 | case AArch64::LASTB_VPZ_H: |
| 8690 | case AArch64::LASTB_VPZ_S: |
| 8691 | case AArch64::ORV_VPZ_B: |
| 8692 | case AArch64::ORV_VPZ_D: |
| 8693 | case AArch64::ORV_VPZ_H: |
| 8694 | case AArch64::ORV_VPZ_S: |
| 8695 | case AArch64::SADDV_VPZ_B: |
| 8696 | case AArch64::SADDV_VPZ_H: |
| 8697 | case AArch64::SADDV_VPZ_S: |
| 8698 | case AArch64::SMAXV_VPZ_B: |
| 8699 | case AArch64::SMAXV_VPZ_D: |
| 8700 | case AArch64::SMAXV_VPZ_H: |
| 8701 | case AArch64::SMAXV_VPZ_S: |
| 8702 | case AArch64::SMINV_VPZ_B: |
| 8703 | case AArch64::SMINV_VPZ_D: |
| 8704 | case AArch64::SMINV_VPZ_H: |
| 8705 | case AArch64::SMINV_VPZ_S: |
| 8706 | case AArch64::UADDV_VPZ_B: |
| 8707 | case AArch64::UADDV_VPZ_D: |
| 8708 | case AArch64::UADDV_VPZ_H: |
| 8709 | case AArch64::UADDV_VPZ_S: |
| 8710 | case AArch64::UMAXV_VPZ_B: |
| 8711 | case AArch64::UMAXV_VPZ_D: |
| 8712 | case AArch64::UMAXV_VPZ_H: |
| 8713 | case AArch64::UMAXV_VPZ_S: |
| 8714 | case AArch64::UMINV_VPZ_B: |
| 8715 | case AArch64::UMINV_VPZ_D: |
| 8716 | case AArch64::UMINV_VPZ_H: |
| 8717 | case AArch64::UMINV_VPZ_S: { |
| 8718 | // op: Pg |
| 8719 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8720 | Value |= (op & 0x7) << 10; |
| 8721 | // op: Vd |
| 8722 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8723 | Value |= (op & 0x1f); |
| 8724 | // op: Zn |
| 8725 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8726 | Value |= (op & 0x1f) << 5; |
| 8727 | break; |
| 8728 | } |
| 8729 | case AArch64::CLASTA_VPZ_B: |
| 8730 | case AArch64::CLASTA_VPZ_D: |
| 8731 | case AArch64::CLASTA_VPZ_H: |
| 8732 | case AArch64::CLASTA_VPZ_S: |
| 8733 | case AArch64::CLASTB_VPZ_B: |
| 8734 | case AArch64::CLASTB_VPZ_D: |
| 8735 | case AArch64::CLASTB_VPZ_H: |
| 8736 | case AArch64::CLASTB_VPZ_S: |
| 8737 | case AArch64::FADDA_VPZ_D: |
| 8738 | case AArch64::FADDA_VPZ_H: |
| 8739 | case AArch64::FADDA_VPZ_S: { |
| 8740 | // op: Pg |
| 8741 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8742 | Value |= (op & 0x7) << 10; |
| 8743 | // op: Vdn |
| 8744 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8745 | Value |= (op & 0x1f); |
| 8746 | // op: Zm |
| 8747 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8748 | Value |= (op & 0x1f) << 5; |
| 8749 | break; |
| 8750 | } |
| 8751 | case AArch64::FMAD_ZPmZZ_D: |
| 8752 | case AArch64::FMAD_ZPmZZ_H: |
| 8753 | case AArch64::FMAD_ZPmZZ_S: |
| 8754 | case AArch64::FMSB_ZPmZZ_D: |
| 8755 | case AArch64::FMSB_ZPmZZ_H: |
| 8756 | case AArch64::FMSB_ZPmZZ_S: |
| 8757 | case AArch64::FNMAD_ZPmZZ_D: |
| 8758 | case AArch64::FNMAD_ZPmZZ_H: |
| 8759 | case AArch64::FNMAD_ZPmZZ_S: |
| 8760 | case AArch64::FNMSB_ZPmZZ_D: |
| 8761 | case AArch64::FNMSB_ZPmZZ_H: |
| 8762 | case AArch64::FNMSB_ZPmZZ_S: { |
| 8763 | // op: Pg |
| 8764 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8765 | Value |= (op & 0x7) << 10; |
| 8766 | // op: Za |
| 8767 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8768 | Value |= (op & 0x1f) << 16; |
| 8769 | // op: Zdn |
| 8770 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8771 | Value |= (op & 0x1f); |
| 8772 | // op: Zm |
| 8773 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8774 | Value |= (op & 0x1f) << 5; |
| 8775 | break; |
| 8776 | } |
| 8777 | case AArch64::ABS_ZPzZ_B: |
| 8778 | case AArch64::ABS_ZPzZ_D: |
| 8779 | case AArch64::ABS_ZPzZ_H: |
| 8780 | case AArch64::ABS_ZPzZ_S: |
| 8781 | case AArch64::BFCVT_ZPzZ_StoH: |
| 8782 | case AArch64::CLS_ZPzZ_B: |
| 8783 | case AArch64::CLS_ZPzZ_D: |
| 8784 | case AArch64::CLS_ZPzZ_H: |
| 8785 | case AArch64::CLS_ZPzZ_S: |
| 8786 | case AArch64::CLZ_ZPzZ_B: |
| 8787 | case AArch64::CLZ_ZPzZ_D: |
| 8788 | case AArch64::CLZ_ZPzZ_H: |
| 8789 | case AArch64::CLZ_ZPzZ_S: |
| 8790 | case AArch64::CNOT_ZPzZ_B: |
| 8791 | case AArch64::CNOT_ZPzZ_D: |
| 8792 | case AArch64::CNOT_ZPzZ_H: |
| 8793 | case AArch64::CNOT_ZPzZ_S: |
| 8794 | case AArch64::CNT_ZPzZ_B: |
| 8795 | case AArch64::CNT_ZPzZ_D: |
| 8796 | case AArch64::CNT_ZPzZ_H: |
| 8797 | case AArch64::CNT_ZPzZ_S: |
| 8798 | case AArch64::COMPACT_ZPZ_B: |
| 8799 | case AArch64::COMPACT_ZPZ_D: |
| 8800 | case AArch64::COMPACT_ZPZ_H: |
| 8801 | case AArch64::COMPACT_ZPZ_S: |
| 8802 | case AArch64::FABS_ZPzZ_D: |
| 8803 | case AArch64::FABS_ZPzZ_H: |
| 8804 | case AArch64::FABS_ZPzZ_S: |
| 8805 | case AArch64::FCVTX_ZPzZ_DtoS: |
| 8806 | case AArch64::FCVTZS_ZPzZ_DtoD: |
| 8807 | case AArch64::FCVTZS_ZPzZ_DtoS: |
| 8808 | case AArch64::FCVTZS_ZPzZ_HtoD: |
| 8809 | case AArch64::FCVTZS_ZPzZ_HtoH: |
| 8810 | case AArch64::FCVTZS_ZPzZ_HtoS: |
| 8811 | case AArch64::FCVTZS_ZPzZ_StoD: |
| 8812 | case AArch64::FCVTZS_ZPzZ_StoS: |
| 8813 | case AArch64::FCVTZU_ZPzZ_DtoD: |
| 8814 | case AArch64::FCVTZU_ZPzZ_DtoS: |
| 8815 | case AArch64::FCVTZU_ZPzZ_HtoD: |
| 8816 | case AArch64::FCVTZU_ZPzZ_HtoH: |
| 8817 | case AArch64::FCVTZU_ZPzZ_HtoS: |
| 8818 | case AArch64::FCVTZU_ZPzZ_StoD: |
| 8819 | case AArch64::FCVTZU_ZPzZ_StoS: |
| 8820 | case AArch64::FCVT_ZPzZ_DtoH: |
| 8821 | case AArch64::FCVT_ZPzZ_DtoS: |
| 8822 | case AArch64::FCVT_ZPzZ_HtoD: |
| 8823 | case AArch64::FCVT_ZPzZ_HtoS: |
| 8824 | case AArch64::FCVT_ZPzZ_StoD: |
| 8825 | case AArch64::FCVT_ZPzZ_StoH: |
| 8826 | case AArch64::FLOGB_ZPzZ_D: |
| 8827 | case AArch64::FLOGB_ZPzZ_H: |
| 8828 | case AArch64::FLOGB_ZPzZ_S: |
| 8829 | case AArch64::FNEG_ZPzZ_D: |
| 8830 | case AArch64::FNEG_ZPzZ_H: |
| 8831 | case AArch64::FNEG_ZPzZ_S: |
| 8832 | case AArch64::FRECPX_ZPzZ_D: |
| 8833 | case AArch64::FRECPX_ZPzZ_H: |
| 8834 | case AArch64::FRECPX_ZPzZ_S: |
| 8835 | case AArch64::FRINT32X_ZPzZ_D: |
| 8836 | case AArch64::FRINT32X_ZPzZ_S: |
| 8837 | case AArch64::FRINT32Z_ZPzZ_D: |
| 8838 | case AArch64::FRINT32Z_ZPzZ_S: |
| 8839 | case AArch64::FRINT64X_ZPzZ_D: |
| 8840 | case AArch64::FRINT64X_ZPzZ_S: |
| 8841 | case AArch64::FRINT64Z_ZPzZ_D: |
| 8842 | case AArch64::FRINT64Z_ZPzZ_S: |
| 8843 | case AArch64::FRINTA_ZPzZ_D: |
| 8844 | case AArch64::FRINTA_ZPzZ_H: |
| 8845 | case AArch64::FRINTA_ZPzZ_S: |
| 8846 | case AArch64::FRINTI_ZPzZ_D: |
| 8847 | case AArch64::FRINTI_ZPzZ_H: |
| 8848 | case AArch64::FRINTI_ZPzZ_S: |
| 8849 | case AArch64::FRINTM_ZPzZ_D: |
| 8850 | case AArch64::FRINTM_ZPzZ_H: |
| 8851 | case AArch64::FRINTM_ZPzZ_S: |
| 8852 | case AArch64::FRINTN_ZPzZ_D: |
| 8853 | case AArch64::FRINTN_ZPzZ_H: |
| 8854 | case AArch64::FRINTN_ZPzZ_S: |
| 8855 | case AArch64::FRINTP_ZPzZ_D: |
| 8856 | case AArch64::FRINTP_ZPzZ_H: |
| 8857 | case AArch64::FRINTP_ZPzZ_S: |
| 8858 | case AArch64::FRINTX_ZPzZ_D: |
| 8859 | case AArch64::FRINTX_ZPzZ_H: |
| 8860 | case AArch64::FRINTX_ZPzZ_S: |
| 8861 | case AArch64::FRINTZ_ZPzZ_D: |
| 8862 | case AArch64::FRINTZ_ZPzZ_H: |
| 8863 | case AArch64::FRINTZ_ZPzZ_S: |
| 8864 | case AArch64::FSQRT_ZPZz_D: |
| 8865 | case AArch64::FSQRT_ZPZz_H: |
| 8866 | case AArch64::FSQRT_ZPZz_S: |
| 8867 | case AArch64::MOVPRFX_ZPzZ_B: |
| 8868 | case AArch64::MOVPRFX_ZPzZ_D: |
| 8869 | case AArch64::MOVPRFX_ZPzZ_H: |
| 8870 | case AArch64::MOVPRFX_ZPzZ_S: |
| 8871 | case AArch64::NEG_ZPzZ_B: |
| 8872 | case AArch64::NEG_ZPzZ_D: |
| 8873 | case AArch64::NEG_ZPzZ_H: |
| 8874 | case AArch64::NEG_ZPzZ_S: |
| 8875 | case AArch64::NOT_ZPzZ_B: |
| 8876 | case AArch64::NOT_ZPzZ_D: |
| 8877 | case AArch64::NOT_ZPzZ_H: |
| 8878 | case AArch64::NOT_ZPzZ_S: |
| 8879 | case AArch64::SCVTF_ZPzZ_DtoD: |
| 8880 | case AArch64::SCVTF_ZPzZ_DtoH: |
| 8881 | case AArch64::SCVTF_ZPzZ_DtoS: |
| 8882 | case AArch64::SCVTF_ZPzZ_HtoH: |
| 8883 | case AArch64::SCVTF_ZPzZ_StoD: |
| 8884 | case AArch64::SCVTF_ZPzZ_StoH: |
| 8885 | case AArch64::SCVTF_ZPzZ_StoS: |
| 8886 | case AArch64::SQABS_ZPzZ_B: |
| 8887 | case AArch64::SQABS_ZPzZ_D: |
| 8888 | case AArch64::SQABS_ZPzZ_H: |
| 8889 | case AArch64::SQABS_ZPzZ_S: |
| 8890 | case AArch64::SQNEG_ZPzZ_B: |
| 8891 | case AArch64::SQNEG_ZPzZ_D: |
| 8892 | case AArch64::SQNEG_ZPzZ_H: |
| 8893 | case AArch64::SQNEG_ZPzZ_S: |
| 8894 | case AArch64::SXTB_ZPzZ_D: |
| 8895 | case AArch64::SXTB_ZPzZ_H: |
| 8896 | case AArch64::SXTB_ZPzZ_S: |
| 8897 | case AArch64::SXTH_ZPzZ_D: |
| 8898 | case AArch64::SXTH_ZPzZ_S: |
| 8899 | case AArch64::SXTW_ZPzZ_D: |
| 8900 | case AArch64::UCVTF_ZPzZ_DtoD: |
| 8901 | case AArch64::UCVTF_ZPzZ_DtoH: |
| 8902 | case AArch64::UCVTF_ZPzZ_DtoS: |
| 8903 | case AArch64::UCVTF_ZPzZ_HtoH: |
| 8904 | case AArch64::UCVTF_ZPzZ_StoD: |
| 8905 | case AArch64::UCVTF_ZPzZ_StoH: |
| 8906 | case AArch64::UCVTF_ZPzZ_StoS: |
| 8907 | case AArch64::URECPE_ZPzZ_S: |
| 8908 | case AArch64::URSQRTE_ZPzZ_S: |
| 8909 | case AArch64::UXTB_ZPzZ_D: |
| 8910 | case AArch64::UXTB_ZPzZ_H: |
| 8911 | case AArch64::UXTB_ZPzZ_S: |
| 8912 | case AArch64::UXTH_ZPzZ_D: |
| 8913 | case AArch64::UXTH_ZPzZ_S: |
| 8914 | case AArch64::UXTW_ZPzZ_D: { |
| 8915 | // op: Pg |
| 8916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8917 | Value |= (op & 0x7) << 10; |
| 8918 | // op: Zd |
| 8919 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8920 | Value |= (op & 0x1f); |
| 8921 | // op: Zn |
| 8922 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 8923 | Value |= (op & 0x1f) << 5; |
| 8924 | break; |
| 8925 | } |
| 8926 | case AArch64::BFMLA_ZPmZZ: |
| 8927 | case AArch64::BFMLS_ZPmZZ: |
| 8928 | case AArch64::FMLA_ZPmZZ_D: |
| 8929 | case AArch64::FMLA_ZPmZZ_H: |
| 8930 | case AArch64::FMLA_ZPmZZ_S: |
| 8931 | case AArch64::FMLS_ZPmZZ_D: |
| 8932 | case AArch64::FMLS_ZPmZZ_H: |
| 8933 | case AArch64::FMLS_ZPmZZ_S: |
| 8934 | case AArch64::FNMLA_ZPmZZ_D: |
| 8935 | case AArch64::FNMLA_ZPmZZ_H: |
| 8936 | case AArch64::FNMLA_ZPmZZ_S: |
| 8937 | case AArch64::FNMLS_ZPmZZ_D: |
| 8938 | case AArch64::FNMLS_ZPmZZ_H: |
| 8939 | case AArch64::FNMLS_ZPmZZ_S: |
| 8940 | case AArch64::MLA_ZPmZZ_B: |
| 8941 | case AArch64::MLA_ZPmZZ_D: |
| 8942 | case AArch64::MLA_ZPmZZ_H: |
| 8943 | case AArch64::MLA_ZPmZZ_S: |
| 8944 | case AArch64::MLS_ZPmZZ_B: |
| 8945 | case AArch64::MLS_ZPmZZ_D: |
| 8946 | case AArch64::MLS_ZPmZZ_H: |
| 8947 | case AArch64::MLS_ZPmZZ_S: { |
| 8948 | // op: Pg |
| 8949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8950 | Value |= (op & 0x7) << 10; |
| 8951 | // op: Zda |
| 8952 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8953 | Value |= (op & 0x1f); |
| 8954 | // op: Zm |
| 8955 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8956 | Value |= (op & 0x1f) << 16; |
| 8957 | // op: Zn |
| 8958 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8959 | Value |= (op & 0x1f) << 5; |
| 8960 | break; |
| 8961 | } |
| 8962 | case AArch64::MAD_ZPmZZ_B: |
| 8963 | case AArch64::MAD_ZPmZZ_D: |
| 8964 | case AArch64::MAD_ZPmZZ_H: |
| 8965 | case AArch64::MAD_ZPmZZ_S: |
| 8966 | case AArch64::MSB_ZPmZZ_B: |
| 8967 | case AArch64::MSB_ZPmZZ_D: |
| 8968 | case AArch64::MSB_ZPmZZ_H: |
| 8969 | case AArch64::MSB_ZPmZZ_S: { |
| 8970 | // op: Pg |
| 8971 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 8972 | Value |= (op & 0x7) << 10; |
| 8973 | // op: Zdn |
| 8974 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 8975 | Value |= (op & 0x1f); |
| 8976 | // op: Za |
| 8977 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 8978 | Value |= (op & 0x1f) << 5; |
| 8979 | // op: Zm |
| 8980 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 8981 | Value |= (op & 0x1f) << 16; |
| 8982 | break; |
| 8983 | } |
| 8984 | case AArch64::ADD_ZPmZ_B: |
| 8985 | case AArch64::ADD_ZPmZ_CPA: |
| 8986 | case AArch64::ADD_ZPmZ_D: |
| 8987 | case AArch64::ADD_ZPmZ_H: |
| 8988 | case AArch64::ADD_ZPmZ_S: |
| 8989 | case AArch64::AND_ZPmZ_B: |
| 8990 | case AArch64::AND_ZPmZ_D: |
| 8991 | case AArch64::AND_ZPmZ_H: |
| 8992 | case AArch64::AND_ZPmZ_S: |
| 8993 | case AArch64::ASRR_ZPmZ_B: |
| 8994 | case AArch64::ASRR_ZPmZ_D: |
| 8995 | case AArch64::ASRR_ZPmZ_H: |
| 8996 | case AArch64::ASRR_ZPmZ_S: |
| 8997 | case AArch64::ASR_WIDE_ZPmZ_B: |
| 8998 | case AArch64::ASR_WIDE_ZPmZ_H: |
| 8999 | case AArch64::ASR_WIDE_ZPmZ_S: |
| 9000 | case AArch64::ASR_ZPmZ_B: |
| 9001 | case AArch64::ASR_ZPmZ_D: |
| 9002 | case AArch64::ASR_ZPmZ_H: |
| 9003 | case AArch64::ASR_ZPmZ_S: |
| 9004 | case AArch64::BFADD_ZPmZ: |
| 9005 | case AArch64::BFMAXNM_ZPmZ: |
| 9006 | case AArch64::BFMAX_ZPmZ: |
| 9007 | case AArch64::BFMINNM_ZPmZ: |
| 9008 | case AArch64::BFMIN_ZPmZ: |
| 9009 | case AArch64::BFMUL_ZPmZ: |
| 9010 | case AArch64::BFSCALE_ZPmZ: |
| 9011 | case AArch64::BFSUB_ZPmZ: |
| 9012 | case AArch64::BIC_ZPmZ_B: |
| 9013 | case AArch64::BIC_ZPmZ_D: |
| 9014 | case AArch64::BIC_ZPmZ_H: |
| 9015 | case AArch64::BIC_ZPmZ_S: |
| 9016 | case AArch64::CLASTA_ZPZ_B: |
| 9017 | case AArch64::CLASTA_ZPZ_D: |
| 9018 | case AArch64::CLASTA_ZPZ_H: |
| 9019 | case AArch64::CLASTA_ZPZ_S: |
| 9020 | case AArch64::CLASTB_ZPZ_B: |
| 9021 | case AArch64::CLASTB_ZPZ_D: |
| 9022 | case AArch64::CLASTB_ZPZ_H: |
| 9023 | case AArch64::CLASTB_ZPZ_S: |
| 9024 | case AArch64::EOR_ZPmZ_B: |
| 9025 | case AArch64::EOR_ZPmZ_D: |
| 9026 | case AArch64::EOR_ZPmZ_H: |
| 9027 | case AArch64::EOR_ZPmZ_S: |
| 9028 | case AArch64::FABD_ZPmZ_D: |
| 9029 | case AArch64::FABD_ZPmZ_H: |
| 9030 | case AArch64::FABD_ZPmZ_S: |
| 9031 | case AArch64::FADD_ZPmZ_D: |
| 9032 | case AArch64::FADD_ZPmZ_H: |
| 9033 | case AArch64::FADD_ZPmZ_S: |
| 9034 | case AArch64::FAMAX_ZPmZ_D: |
| 9035 | case AArch64::FAMAX_ZPmZ_H: |
| 9036 | case AArch64::FAMAX_ZPmZ_S: |
| 9037 | case AArch64::FAMIN_ZPmZ_D: |
| 9038 | case AArch64::FAMIN_ZPmZ_H: |
| 9039 | case AArch64::FAMIN_ZPmZ_S: |
| 9040 | case AArch64::FDIVR_ZPmZ_D: |
| 9041 | case AArch64::FDIVR_ZPmZ_H: |
| 9042 | case AArch64::FDIVR_ZPmZ_S: |
| 9043 | case AArch64::FDIV_ZPmZ_D: |
| 9044 | case AArch64::FDIV_ZPmZ_H: |
| 9045 | case AArch64::FDIV_ZPmZ_S: |
| 9046 | case AArch64::FMAXNM_ZPmZ_D: |
| 9047 | case AArch64::FMAXNM_ZPmZ_H: |
| 9048 | case AArch64::FMAXNM_ZPmZ_S: |
| 9049 | case AArch64::FMAX_ZPmZ_D: |
| 9050 | case AArch64::FMAX_ZPmZ_H: |
| 9051 | case AArch64::FMAX_ZPmZ_S: |
| 9052 | case AArch64::FMINNM_ZPmZ_D: |
| 9053 | case AArch64::FMINNM_ZPmZ_H: |
| 9054 | case AArch64::FMINNM_ZPmZ_S: |
| 9055 | case AArch64::FMIN_ZPmZ_D: |
| 9056 | case AArch64::FMIN_ZPmZ_H: |
| 9057 | case AArch64::FMIN_ZPmZ_S: |
| 9058 | case AArch64::FMULX_ZPmZ_D: |
| 9059 | case AArch64::FMULX_ZPmZ_H: |
| 9060 | case AArch64::FMULX_ZPmZ_S: |
| 9061 | case AArch64::FMUL_ZPmZ_D: |
| 9062 | case AArch64::FMUL_ZPmZ_H: |
| 9063 | case AArch64::FMUL_ZPmZ_S: |
| 9064 | case AArch64::FSCALE_ZPmZ_D: |
| 9065 | case AArch64::FSCALE_ZPmZ_H: |
| 9066 | case AArch64::FSCALE_ZPmZ_S: |
| 9067 | case AArch64::FSUBR_ZPmZ_D: |
| 9068 | case AArch64::FSUBR_ZPmZ_H: |
| 9069 | case AArch64::FSUBR_ZPmZ_S: |
| 9070 | case AArch64::FSUB_ZPmZ_D: |
| 9071 | case AArch64::FSUB_ZPmZ_H: |
| 9072 | case AArch64::FSUB_ZPmZ_S: |
| 9073 | case AArch64::LSLR_ZPmZ_B: |
| 9074 | case AArch64::LSLR_ZPmZ_D: |
| 9075 | case AArch64::LSLR_ZPmZ_H: |
| 9076 | case AArch64::LSLR_ZPmZ_S: |
| 9077 | case AArch64::LSL_WIDE_ZPmZ_B: |
| 9078 | case AArch64::LSL_WIDE_ZPmZ_H: |
| 9079 | case AArch64::LSL_WIDE_ZPmZ_S: |
| 9080 | case AArch64::LSL_ZPmZ_B: |
| 9081 | case AArch64::LSL_ZPmZ_D: |
| 9082 | case AArch64::LSL_ZPmZ_H: |
| 9083 | case AArch64::LSL_ZPmZ_S: |
| 9084 | case AArch64::LSRR_ZPmZ_B: |
| 9085 | case AArch64::LSRR_ZPmZ_D: |
| 9086 | case AArch64::LSRR_ZPmZ_H: |
| 9087 | case AArch64::LSRR_ZPmZ_S: |
| 9088 | case AArch64::LSR_WIDE_ZPmZ_B: |
| 9089 | case AArch64::LSR_WIDE_ZPmZ_H: |
| 9090 | case AArch64::LSR_WIDE_ZPmZ_S: |
| 9091 | case AArch64::LSR_ZPmZ_B: |
| 9092 | case AArch64::LSR_ZPmZ_D: |
| 9093 | case AArch64::LSR_ZPmZ_H: |
| 9094 | case AArch64::LSR_ZPmZ_S: |
| 9095 | case AArch64::MUL_ZPmZ_B: |
| 9096 | case AArch64::MUL_ZPmZ_D: |
| 9097 | case AArch64::MUL_ZPmZ_H: |
| 9098 | case AArch64::MUL_ZPmZ_S: |
| 9099 | case AArch64::ORR_ZPmZ_B: |
| 9100 | case AArch64::ORR_ZPmZ_D: |
| 9101 | case AArch64::ORR_ZPmZ_H: |
| 9102 | case AArch64::ORR_ZPmZ_S: |
| 9103 | case AArch64::SABD_ZPmZ_B: |
| 9104 | case AArch64::SABD_ZPmZ_D: |
| 9105 | case AArch64::SABD_ZPmZ_H: |
| 9106 | case AArch64::SABD_ZPmZ_S: |
| 9107 | case AArch64::SDIVR_ZPmZ_D: |
| 9108 | case AArch64::SDIVR_ZPmZ_S: |
| 9109 | case AArch64::SDIV_ZPmZ_D: |
| 9110 | case AArch64::SDIV_ZPmZ_S: |
| 9111 | case AArch64::SMAX_ZPmZ_B: |
| 9112 | case AArch64::SMAX_ZPmZ_D: |
| 9113 | case AArch64::SMAX_ZPmZ_H: |
| 9114 | case AArch64::SMAX_ZPmZ_S: |
| 9115 | case AArch64::SMIN_ZPmZ_B: |
| 9116 | case AArch64::SMIN_ZPmZ_D: |
| 9117 | case AArch64::SMIN_ZPmZ_H: |
| 9118 | case AArch64::SMIN_ZPmZ_S: |
| 9119 | case AArch64::SMULH_ZPmZ_B: |
| 9120 | case AArch64::SMULH_ZPmZ_D: |
| 9121 | case AArch64::SMULH_ZPmZ_H: |
| 9122 | case AArch64::SMULH_ZPmZ_S: |
| 9123 | case AArch64::SPLICE_ZPZ_B: |
| 9124 | case AArch64::SPLICE_ZPZ_D: |
| 9125 | case AArch64::SPLICE_ZPZ_H: |
| 9126 | case AArch64::SPLICE_ZPZ_S: |
| 9127 | case AArch64::SUBR_ZPmZ_B: |
| 9128 | case AArch64::SUBR_ZPmZ_D: |
| 9129 | case AArch64::SUBR_ZPmZ_H: |
| 9130 | case AArch64::SUBR_ZPmZ_S: |
| 9131 | case AArch64::SUB_ZPmZ_B: |
| 9132 | case AArch64::SUB_ZPmZ_CPA: |
| 9133 | case AArch64::SUB_ZPmZ_D: |
| 9134 | case AArch64::SUB_ZPmZ_H: |
| 9135 | case AArch64::SUB_ZPmZ_S: |
| 9136 | case AArch64::UABD_ZPmZ_B: |
| 9137 | case AArch64::UABD_ZPmZ_D: |
| 9138 | case AArch64::UABD_ZPmZ_H: |
| 9139 | case AArch64::UABD_ZPmZ_S: |
| 9140 | case AArch64::UDIVR_ZPmZ_D: |
| 9141 | case AArch64::UDIVR_ZPmZ_S: |
| 9142 | case AArch64::UDIV_ZPmZ_D: |
| 9143 | case AArch64::UDIV_ZPmZ_S: |
| 9144 | case AArch64::UMAX_ZPmZ_B: |
| 9145 | case AArch64::UMAX_ZPmZ_D: |
| 9146 | case AArch64::UMAX_ZPmZ_H: |
| 9147 | case AArch64::UMAX_ZPmZ_S: |
| 9148 | case AArch64::UMIN_ZPmZ_B: |
| 9149 | case AArch64::UMIN_ZPmZ_D: |
| 9150 | case AArch64::UMIN_ZPmZ_H: |
| 9151 | case AArch64::UMIN_ZPmZ_S: |
| 9152 | case AArch64::UMULH_ZPmZ_B: |
| 9153 | case AArch64::UMULH_ZPmZ_D: |
| 9154 | case AArch64::UMULH_ZPmZ_H: |
| 9155 | case AArch64::UMULH_ZPmZ_S: { |
| 9156 | // op: Pg |
| 9157 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9158 | Value |= (op & 0x7) << 10; |
| 9159 | // op: Zdn |
| 9160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9161 | Value |= (op & 0x1f); |
| 9162 | // op: Zm |
| 9163 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9164 | Value |= (op & 0x1f) << 5; |
| 9165 | break; |
| 9166 | } |
| 9167 | case AArch64::FADD_ZPmI_D: |
| 9168 | case AArch64::FADD_ZPmI_H: |
| 9169 | case AArch64::FADD_ZPmI_S: |
| 9170 | case AArch64::FMAXNM_ZPmI_D: |
| 9171 | case AArch64::FMAXNM_ZPmI_H: |
| 9172 | case AArch64::FMAXNM_ZPmI_S: |
| 9173 | case AArch64::FMAX_ZPmI_D: |
| 9174 | case AArch64::FMAX_ZPmI_H: |
| 9175 | case AArch64::FMAX_ZPmI_S: |
| 9176 | case AArch64::FMINNM_ZPmI_D: |
| 9177 | case AArch64::FMINNM_ZPmI_H: |
| 9178 | case AArch64::FMINNM_ZPmI_S: |
| 9179 | case AArch64::FMIN_ZPmI_D: |
| 9180 | case AArch64::FMIN_ZPmI_H: |
| 9181 | case AArch64::FMIN_ZPmI_S: |
| 9182 | case AArch64::FMUL_ZPmI_D: |
| 9183 | case AArch64::FMUL_ZPmI_H: |
| 9184 | case AArch64::FMUL_ZPmI_S: |
| 9185 | case AArch64::FSUBR_ZPmI_D: |
| 9186 | case AArch64::FSUBR_ZPmI_H: |
| 9187 | case AArch64::FSUBR_ZPmI_S: |
| 9188 | case AArch64::FSUB_ZPmI_D: |
| 9189 | case AArch64::FSUB_ZPmI_H: |
| 9190 | case AArch64::FSUB_ZPmI_S: { |
| 9191 | // op: Pg |
| 9192 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9193 | Value |= (op & 0x7) << 10; |
| 9194 | // op: Zdn |
| 9195 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9196 | Value |= (op & 0x1f); |
| 9197 | // op: i1 |
| 9198 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9199 | Value |= (op & 0x1) << 5; |
| 9200 | break; |
| 9201 | } |
| 9202 | case AArch64::LSL_ZPmI_H: |
| 9203 | case AArch64::SQSHLU_ZPmI_H: |
| 9204 | case AArch64::SQSHL_ZPmI_H: |
| 9205 | case AArch64::UQSHL_ZPmI_H: { |
| 9206 | // op: Pg |
| 9207 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9208 | Value |= (op & 0x7) << 10; |
| 9209 | // op: Zdn |
| 9210 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9211 | Value |= (op & 0x1f); |
| 9212 | // op: imm |
| 9213 | op = getVecShiftL16OpValue(MI, OpIdx: 3, Fixups, STI); |
| 9214 | Value |= (op & 0xf) << 5; |
| 9215 | break; |
| 9216 | } |
| 9217 | case AArch64::LSL_ZPmI_S: |
| 9218 | case AArch64::SQSHLU_ZPmI_S: |
| 9219 | case AArch64::SQSHL_ZPmI_S: |
| 9220 | case AArch64::UQSHL_ZPmI_S: { |
| 9221 | // op: Pg |
| 9222 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9223 | Value |= (op & 0x7) << 10; |
| 9224 | // op: Zdn |
| 9225 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9226 | Value |= (op & 0x1f); |
| 9227 | // op: imm |
| 9228 | op = getVecShiftL32OpValue(MI, OpIdx: 3, Fixups, STI); |
| 9229 | Value |= (op & 0x1f) << 5; |
| 9230 | break; |
| 9231 | } |
| 9232 | case AArch64::LSL_ZPmI_D: |
| 9233 | case AArch64::SQSHLU_ZPmI_D: |
| 9234 | case AArch64::SQSHL_ZPmI_D: |
| 9235 | case AArch64::UQSHL_ZPmI_D: { |
| 9236 | // op: Pg |
| 9237 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9238 | Value |= (op & 0x7) << 10; |
| 9239 | // op: Zdn |
| 9240 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9241 | Value |= (op & 0x1f); |
| 9242 | // op: imm |
| 9243 | op = getVecShiftL64OpValue(MI, OpIdx: 3, Fixups, STI); |
| 9244 | Value |= (op & 0x20) << 17; |
| 9245 | Value |= (op & 0x1f) << 5; |
| 9246 | break; |
| 9247 | } |
| 9248 | case AArch64::LSL_ZPmI_B: |
| 9249 | case AArch64::SQSHLU_ZPmI_B: |
| 9250 | case AArch64::SQSHL_ZPmI_B: |
| 9251 | case AArch64::UQSHL_ZPmI_B: { |
| 9252 | // op: Pg |
| 9253 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9254 | Value |= (op & 0x7) << 10; |
| 9255 | // op: Zdn |
| 9256 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9257 | Value |= (op & 0x1f); |
| 9258 | // op: imm |
| 9259 | op = getVecShiftL8OpValue(MI, OpIdx: 3, Fixups, STI); |
| 9260 | Value |= (op & 0x7) << 5; |
| 9261 | break; |
| 9262 | } |
| 9263 | case AArch64::ASRD_ZPmI_H: |
| 9264 | case AArch64::ASR_ZPmI_H: |
| 9265 | case AArch64::LSR_ZPmI_H: |
| 9266 | case AArch64::SRSHR_ZPmI_H: |
| 9267 | case AArch64::URSHR_ZPmI_H: { |
| 9268 | // op: Pg |
| 9269 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9270 | Value |= (op & 0x7) << 10; |
| 9271 | // op: Zdn |
| 9272 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9273 | Value |= (op & 0x1f); |
| 9274 | // op: imm |
| 9275 | op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI); |
| 9276 | Value |= (op & 0xf) << 5; |
| 9277 | break; |
| 9278 | } |
| 9279 | case AArch64::ASRD_ZPmI_S: |
| 9280 | case AArch64::ASR_ZPmI_S: |
| 9281 | case AArch64::LSR_ZPmI_S: |
| 9282 | case AArch64::SRSHR_ZPmI_S: |
| 9283 | case AArch64::URSHR_ZPmI_S: { |
| 9284 | // op: Pg |
| 9285 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9286 | Value |= (op & 0x7) << 10; |
| 9287 | // op: Zdn |
| 9288 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9289 | Value |= (op & 0x1f); |
| 9290 | // op: imm |
| 9291 | op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI); |
| 9292 | Value |= (op & 0x1f) << 5; |
| 9293 | break; |
| 9294 | } |
| 9295 | case AArch64::ASRD_ZPmI_D: |
| 9296 | case AArch64::ASR_ZPmI_D: |
| 9297 | case AArch64::LSR_ZPmI_D: |
| 9298 | case AArch64::SRSHR_ZPmI_D: |
| 9299 | case AArch64::URSHR_ZPmI_D: { |
| 9300 | // op: Pg |
| 9301 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9302 | Value |= (op & 0x7) << 10; |
| 9303 | // op: Zdn |
| 9304 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9305 | Value |= (op & 0x1f); |
| 9306 | // op: imm |
| 9307 | op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI); |
| 9308 | Value |= (op & 0x20) << 17; |
| 9309 | Value |= (op & 0x1f) << 5; |
| 9310 | break; |
| 9311 | } |
| 9312 | case AArch64::ASRD_ZPmI_B: |
| 9313 | case AArch64::ASR_ZPmI_B: |
| 9314 | case AArch64::LSR_ZPmI_B: |
| 9315 | case AArch64::SRSHR_ZPmI_B: |
| 9316 | case AArch64::URSHR_ZPmI_B: { |
| 9317 | // op: Pg |
| 9318 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9319 | Value |= (op & 0x7) << 10; |
| 9320 | // op: Zdn |
| 9321 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9322 | Value |= (op & 0x1f); |
| 9323 | // op: imm |
| 9324 | op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI); |
| 9325 | Value |= (op & 0x7) << 5; |
| 9326 | break; |
| 9327 | } |
| 9328 | case AArch64::ADDP_ZPmZ_B: |
| 9329 | case AArch64::ADDP_ZPmZ_D: |
| 9330 | case AArch64::ADDP_ZPmZ_H: |
| 9331 | case AArch64::ADDP_ZPmZ_S: |
| 9332 | case AArch64::FADDP_ZPmZZ_D: |
| 9333 | case AArch64::FADDP_ZPmZZ_H: |
| 9334 | case AArch64::FADDP_ZPmZZ_S: |
| 9335 | case AArch64::FMAXNMP_ZPmZZ_D: |
| 9336 | case AArch64::FMAXNMP_ZPmZZ_H: |
| 9337 | case AArch64::FMAXNMP_ZPmZZ_S: |
| 9338 | case AArch64::FMAXP_ZPmZZ_D: |
| 9339 | case AArch64::FMAXP_ZPmZZ_H: |
| 9340 | case AArch64::FMAXP_ZPmZZ_S: |
| 9341 | case AArch64::FMINNMP_ZPmZZ_D: |
| 9342 | case AArch64::FMINNMP_ZPmZZ_H: |
| 9343 | case AArch64::FMINNMP_ZPmZZ_S: |
| 9344 | case AArch64::FMINP_ZPmZZ_D: |
| 9345 | case AArch64::FMINP_ZPmZZ_H: |
| 9346 | case AArch64::FMINP_ZPmZZ_S: |
| 9347 | case AArch64::SHADD_ZPmZ_B: |
| 9348 | case AArch64::SHADD_ZPmZ_D: |
| 9349 | case AArch64::SHADD_ZPmZ_H: |
| 9350 | case AArch64::SHADD_ZPmZ_S: |
| 9351 | case AArch64::SHSUBR_ZPmZ_B: |
| 9352 | case AArch64::SHSUBR_ZPmZ_D: |
| 9353 | case AArch64::SHSUBR_ZPmZ_H: |
| 9354 | case AArch64::SHSUBR_ZPmZ_S: |
| 9355 | case AArch64::SHSUB_ZPmZ_B: |
| 9356 | case AArch64::SHSUB_ZPmZ_D: |
| 9357 | case AArch64::SHSUB_ZPmZ_H: |
| 9358 | case AArch64::SHSUB_ZPmZ_S: |
| 9359 | case AArch64::SMAXP_ZPmZ_B: |
| 9360 | case AArch64::SMAXP_ZPmZ_D: |
| 9361 | case AArch64::SMAXP_ZPmZ_H: |
| 9362 | case AArch64::SMAXP_ZPmZ_S: |
| 9363 | case AArch64::SMINP_ZPmZ_B: |
| 9364 | case AArch64::SMINP_ZPmZ_D: |
| 9365 | case AArch64::SMINP_ZPmZ_H: |
| 9366 | case AArch64::SMINP_ZPmZ_S: |
| 9367 | case AArch64::SQADD_ZPmZ_B: |
| 9368 | case AArch64::SQADD_ZPmZ_D: |
| 9369 | case AArch64::SQADD_ZPmZ_H: |
| 9370 | case AArch64::SQADD_ZPmZ_S: |
| 9371 | case AArch64::SQRSHLR_ZPmZ_B: |
| 9372 | case AArch64::SQRSHLR_ZPmZ_D: |
| 9373 | case AArch64::SQRSHLR_ZPmZ_H: |
| 9374 | case AArch64::SQRSHLR_ZPmZ_S: |
| 9375 | case AArch64::SQRSHL_ZPmZ_B: |
| 9376 | case AArch64::SQRSHL_ZPmZ_D: |
| 9377 | case AArch64::SQRSHL_ZPmZ_H: |
| 9378 | case AArch64::SQRSHL_ZPmZ_S: |
| 9379 | case AArch64::SQSHLR_ZPmZ_B: |
| 9380 | case AArch64::SQSHLR_ZPmZ_D: |
| 9381 | case AArch64::SQSHLR_ZPmZ_H: |
| 9382 | case AArch64::SQSHLR_ZPmZ_S: |
| 9383 | case AArch64::SQSHL_ZPmZ_B: |
| 9384 | case AArch64::SQSHL_ZPmZ_D: |
| 9385 | case AArch64::SQSHL_ZPmZ_H: |
| 9386 | case AArch64::SQSHL_ZPmZ_S: |
| 9387 | case AArch64::SQSUBR_ZPmZ_B: |
| 9388 | case AArch64::SQSUBR_ZPmZ_D: |
| 9389 | case AArch64::SQSUBR_ZPmZ_H: |
| 9390 | case AArch64::SQSUBR_ZPmZ_S: |
| 9391 | case AArch64::SQSUB_ZPmZ_B: |
| 9392 | case AArch64::SQSUB_ZPmZ_D: |
| 9393 | case AArch64::SQSUB_ZPmZ_H: |
| 9394 | case AArch64::SQSUB_ZPmZ_S: |
| 9395 | case AArch64::SRHADD_ZPmZ_B: |
| 9396 | case AArch64::SRHADD_ZPmZ_D: |
| 9397 | case AArch64::SRHADD_ZPmZ_H: |
| 9398 | case AArch64::SRHADD_ZPmZ_S: |
| 9399 | case AArch64::SRSHLR_ZPmZ_B: |
| 9400 | case AArch64::SRSHLR_ZPmZ_D: |
| 9401 | case AArch64::SRSHLR_ZPmZ_H: |
| 9402 | case AArch64::SRSHLR_ZPmZ_S: |
| 9403 | case AArch64::SRSHL_ZPmZ_B: |
| 9404 | case AArch64::SRSHL_ZPmZ_D: |
| 9405 | case AArch64::SRSHL_ZPmZ_H: |
| 9406 | case AArch64::SRSHL_ZPmZ_S: |
| 9407 | case AArch64::SUBP_ZPmZZ_B: |
| 9408 | case AArch64::SUBP_ZPmZZ_D: |
| 9409 | case AArch64::SUBP_ZPmZZ_H: |
| 9410 | case AArch64::SUBP_ZPmZZ_S: |
| 9411 | case AArch64::SUQADD_ZPmZ_B: |
| 9412 | case AArch64::SUQADD_ZPmZ_D: |
| 9413 | case AArch64::SUQADD_ZPmZ_H: |
| 9414 | case AArch64::SUQADD_ZPmZ_S: |
| 9415 | case AArch64::UHADD_ZPmZ_B: |
| 9416 | case AArch64::UHADD_ZPmZ_D: |
| 9417 | case AArch64::UHADD_ZPmZ_H: |
| 9418 | case AArch64::UHADD_ZPmZ_S: |
| 9419 | case AArch64::UHSUBR_ZPmZ_B: |
| 9420 | case AArch64::UHSUBR_ZPmZ_D: |
| 9421 | case AArch64::UHSUBR_ZPmZ_H: |
| 9422 | case AArch64::UHSUBR_ZPmZ_S: |
| 9423 | case AArch64::UHSUB_ZPmZ_B: |
| 9424 | case AArch64::UHSUB_ZPmZ_D: |
| 9425 | case AArch64::UHSUB_ZPmZ_H: |
| 9426 | case AArch64::UHSUB_ZPmZ_S: |
| 9427 | case AArch64::UMAXP_ZPmZ_B: |
| 9428 | case AArch64::UMAXP_ZPmZ_D: |
| 9429 | case AArch64::UMAXP_ZPmZ_H: |
| 9430 | case AArch64::UMAXP_ZPmZ_S: |
| 9431 | case AArch64::UMINP_ZPmZ_B: |
| 9432 | case AArch64::UMINP_ZPmZ_D: |
| 9433 | case AArch64::UMINP_ZPmZ_H: |
| 9434 | case AArch64::UMINP_ZPmZ_S: |
| 9435 | case AArch64::UQADD_ZPmZ_B: |
| 9436 | case AArch64::UQADD_ZPmZ_D: |
| 9437 | case AArch64::UQADD_ZPmZ_H: |
| 9438 | case AArch64::UQADD_ZPmZ_S: |
| 9439 | case AArch64::UQRSHLR_ZPmZ_B: |
| 9440 | case AArch64::UQRSHLR_ZPmZ_D: |
| 9441 | case AArch64::UQRSHLR_ZPmZ_H: |
| 9442 | case AArch64::UQRSHLR_ZPmZ_S: |
| 9443 | case AArch64::UQRSHL_ZPmZ_B: |
| 9444 | case AArch64::UQRSHL_ZPmZ_D: |
| 9445 | case AArch64::UQRSHL_ZPmZ_H: |
| 9446 | case AArch64::UQRSHL_ZPmZ_S: |
| 9447 | case AArch64::UQSHLR_ZPmZ_B: |
| 9448 | case AArch64::UQSHLR_ZPmZ_D: |
| 9449 | case AArch64::UQSHLR_ZPmZ_H: |
| 9450 | case AArch64::UQSHLR_ZPmZ_S: |
| 9451 | case AArch64::UQSHL_ZPmZ_B: |
| 9452 | case AArch64::UQSHL_ZPmZ_D: |
| 9453 | case AArch64::UQSHL_ZPmZ_H: |
| 9454 | case AArch64::UQSHL_ZPmZ_S: |
| 9455 | case AArch64::UQSUBR_ZPmZ_B: |
| 9456 | case AArch64::UQSUBR_ZPmZ_D: |
| 9457 | case AArch64::UQSUBR_ZPmZ_H: |
| 9458 | case AArch64::UQSUBR_ZPmZ_S: |
| 9459 | case AArch64::UQSUB_ZPmZ_B: |
| 9460 | case AArch64::UQSUB_ZPmZ_D: |
| 9461 | case AArch64::UQSUB_ZPmZ_H: |
| 9462 | case AArch64::UQSUB_ZPmZ_S: |
| 9463 | case AArch64::URHADD_ZPmZ_B: |
| 9464 | case AArch64::URHADD_ZPmZ_D: |
| 9465 | case AArch64::URHADD_ZPmZ_H: |
| 9466 | case AArch64::URHADD_ZPmZ_S: |
| 9467 | case AArch64::URSHLR_ZPmZ_B: |
| 9468 | case AArch64::URSHLR_ZPmZ_D: |
| 9469 | case AArch64::URSHLR_ZPmZ_H: |
| 9470 | case AArch64::URSHLR_ZPmZ_S: |
| 9471 | case AArch64::URSHL_ZPmZ_B: |
| 9472 | case AArch64::URSHL_ZPmZ_D: |
| 9473 | case AArch64::URSHL_ZPmZ_H: |
| 9474 | case AArch64::URSHL_ZPmZ_S: |
| 9475 | case AArch64::USQADD_ZPmZ_B: |
| 9476 | case AArch64::USQADD_ZPmZ_D: |
| 9477 | case AArch64::USQADD_ZPmZ_H: |
| 9478 | case AArch64::USQADD_ZPmZ_S: { |
| 9479 | // op: Pg |
| 9480 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9481 | Value |= (op & 0x7) << 10; |
| 9482 | // op: Zm |
| 9483 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9484 | Value |= (op & 0x1f) << 5; |
| 9485 | // op: Zdn |
| 9486 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9487 | Value |= (op & 0x1f); |
| 9488 | break; |
| 9489 | } |
| 9490 | case AArch64::EXPAND_ZPZ_B: |
| 9491 | case AArch64::EXPAND_ZPZ_D: |
| 9492 | case AArch64::EXPAND_ZPZ_H: |
| 9493 | case AArch64::EXPAND_ZPZ_S: |
| 9494 | case AArch64::SPLICE_ZPZZ_B: |
| 9495 | case AArch64::SPLICE_ZPZZ_D: |
| 9496 | case AArch64::SPLICE_ZPZZ_H: |
| 9497 | case AArch64::SPLICE_ZPZZ_S: { |
| 9498 | // op: Pg |
| 9499 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9500 | Value |= (op & 0x7) << 10; |
| 9501 | // op: Zn |
| 9502 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9503 | Value |= (op & 0x1f) << 5; |
| 9504 | // op: Zd |
| 9505 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9506 | Value |= (op & 0x1f); |
| 9507 | break; |
| 9508 | } |
| 9509 | case AArch64::GLD1B_D_IMM: |
| 9510 | case AArch64::GLD1B_S_IMM: |
| 9511 | case AArch64::GLD1D_IMM: |
| 9512 | case AArch64::GLD1H_D_IMM: |
| 9513 | case AArch64::GLD1H_S_IMM: |
| 9514 | case AArch64::GLD1SB_D_IMM: |
| 9515 | case AArch64::GLD1SB_S_IMM: |
| 9516 | case AArch64::GLD1SH_D_IMM: |
| 9517 | case AArch64::GLD1SH_S_IMM: |
| 9518 | case AArch64::GLD1SW_D_IMM: |
| 9519 | case AArch64::GLD1W_D_IMM: |
| 9520 | case AArch64::GLD1W_IMM: |
| 9521 | case AArch64::GLDFF1B_D_IMM: |
| 9522 | case AArch64::GLDFF1B_S_IMM: |
| 9523 | case AArch64::GLDFF1D_IMM: |
| 9524 | case AArch64::GLDFF1H_D_IMM: |
| 9525 | case AArch64::GLDFF1H_S_IMM: |
| 9526 | case AArch64::GLDFF1SB_D_IMM: |
| 9527 | case AArch64::GLDFF1SB_S_IMM: |
| 9528 | case AArch64::GLDFF1SH_D_IMM: |
| 9529 | case AArch64::GLDFF1SH_S_IMM: |
| 9530 | case AArch64::GLDFF1SW_D_IMM: |
| 9531 | case AArch64::GLDFF1W_D_IMM: |
| 9532 | case AArch64::GLDFF1W_IMM: { |
| 9533 | // op: Pg |
| 9534 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9535 | Value |= (op & 0x7) << 10; |
| 9536 | // op: Zn |
| 9537 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9538 | Value |= (op & 0x1f) << 5; |
| 9539 | // op: Zt |
| 9540 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9541 | Value |= (op & 0x1f); |
| 9542 | // op: imm5 |
| 9543 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9544 | Value |= (op & 0x1f) << 16; |
| 9545 | break; |
| 9546 | } |
| 9547 | case AArch64::PRFB_D_PZI: |
| 9548 | case AArch64::PRFB_S_PZI: |
| 9549 | case AArch64::PRFD_D_PZI: |
| 9550 | case AArch64::PRFD_S_PZI: |
| 9551 | case AArch64::PRFH_D_PZI: |
| 9552 | case AArch64::PRFH_S_PZI: |
| 9553 | case AArch64::PRFW_D_PZI: |
| 9554 | case AArch64::PRFW_S_PZI: { |
| 9555 | // op: Pg |
| 9556 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9557 | Value |= (op & 0x7) << 10; |
| 9558 | // op: Zn |
| 9559 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9560 | Value |= (op & 0x1f) << 5; |
| 9561 | // op: imm5 |
| 9562 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9563 | Value |= (op & 0x1f) << 16; |
| 9564 | // op: prfop |
| 9565 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9566 | Value |= (op & 0xf); |
| 9567 | break; |
| 9568 | } |
| 9569 | case AArch64::SADALP_ZPmZ_D: |
| 9570 | case AArch64::SADALP_ZPmZ_H: |
| 9571 | case AArch64::SADALP_ZPmZ_S: |
| 9572 | case AArch64::UADALP_ZPmZ_D: |
| 9573 | case AArch64::UADALP_ZPmZ_H: |
| 9574 | case AArch64::UADALP_ZPmZ_S: { |
| 9575 | // op: Pg |
| 9576 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9577 | Value |= (op & 0x7) << 10; |
| 9578 | // op: Zn |
| 9579 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9580 | Value |= (op & 0x1f) << 5; |
| 9581 | // op: Zda |
| 9582 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9583 | Value |= (op & 0x1f); |
| 9584 | break; |
| 9585 | } |
| 9586 | case AArch64::SST1B_D_IMM: |
| 9587 | case AArch64::SST1B_S_IMM: |
| 9588 | case AArch64::SST1D_IMM: |
| 9589 | case AArch64::SST1H_D_IMM: |
| 9590 | case AArch64::SST1H_S_IMM: |
| 9591 | case AArch64::SST1W_D_IMM: |
| 9592 | case AArch64::SST1W_IMM: { |
| 9593 | // op: Pg |
| 9594 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9595 | Value |= (op & 0x7) << 10; |
| 9596 | // op: imm5 |
| 9597 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9598 | Value |= (op & 0x1f) << 16; |
| 9599 | // op: Zn |
| 9600 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9601 | Value |= (op & 0x1f) << 5; |
| 9602 | // op: Zt |
| 9603 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9604 | Value |= (op & 0x1f); |
| 9605 | break; |
| 9606 | } |
| 9607 | case AArch64::CNTP_XPP_B: |
| 9608 | case AArch64::CNTP_XPP_D: |
| 9609 | case AArch64::CNTP_XPP_H: |
| 9610 | case AArch64::CNTP_XPP_S: |
| 9611 | case AArch64::FIRSTP_XPP_B: |
| 9612 | case AArch64::FIRSTP_XPP_D: |
| 9613 | case AArch64::FIRSTP_XPP_H: |
| 9614 | case AArch64::FIRSTP_XPP_S: |
| 9615 | case AArch64::LASTP_XPP_B: |
| 9616 | case AArch64::LASTP_XPP_D: |
| 9617 | case AArch64::LASTP_XPP_H: |
| 9618 | case AArch64::LASTP_XPP_S: { |
| 9619 | // op: Pg |
| 9620 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9621 | Value |= (op & 0xf) << 10; |
| 9622 | // op: Pn |
| 9623 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9624 | Value |= (op & 0xf) << 5; |
| 9625 | // op: Rd |
| 9626 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9627 | Value |= (op & 0x1f); |
| 9628 | break; |
| 9629 | } |
| 9630 | case AArch64::SEL_ZPZZ_B: |
| 9631 | case AArch64::SEL_ZPZZ_D: |
| 9632 | case AArch64::SEL_ZPZZ_H: |
| 9633 | case AArch64::SEL_ZPZZ_S: { |
| 9634 | // op: Pg |
| 9635 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9636 | Value |= (op & 0xf) << 10; |
| 9637 | // op: Zd |
| 9638 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9639 | Value |= (op & 0x1f); |
| 9640 | // op: Zm |
| 9641 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9642 | Value |= (op & 0x1f) << 16; |
| 9643 | // op: Zn |
| 9644 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9645 | Value |= (op & 0x1f) << 5; |
| 9646 | break; |
| 9647 | } |
| 9648 | case AArch64::CPY_ZPmR_B: |
| 9649 | case AArch64::CPY_ZPmR_D: |
| 9650 | case AArch64::CPY_ZPmR_H: |
| 9651 | case AArch64::CPY_ZPmR_S: { |
| 9652 | // op: Pg |
| 9653 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9654 | Value |= (op & 0x7) << 10; |
| 9655 | // op: Rn |
| 9656 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9657 | Value |= (op & 0x1f) << 5; |
| 9658 | // op: Zd |
| 9659 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9660 | Value |= (op & 0x1f); |
| 9661 | break; |
| 9662 | } |
| 9663 | case AArch64::CPY_ZPmV_B: |
| 9664 | case AArch64::CPY_ZPmV_D: |
| 9665 | case AArch64::CPY_ZPmV_H: |
| 9666 | case AArch64::CPY_ZPmV_S: { |
| 9667 | // op: Pg |
| 9668 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9669 | Value |= (op & 0x7) << 10; |
| 9670 | // op: Vn |
| 9671 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9672 | Value |= (op & 0x1f) << 5; |
| 9673 | // op: Zd |
| 9674 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9675 | Value |= (op & 0x1f); |
| 9676 | break; |
| 9677 | } |
| 9678 | case AArch64::ABS_ZPmZ_B: |
| 9679 | case AArch64::ABS_ZPmZ_D: |
| 9680 | case AArch64::ABS_ZPmZ_H: |
| 9681 | case AArch64::ABS_ZPmZ_S: |
| 9682 | case AArch64::BFCVT_ZPmZ: |
| 9683 | case AArch64::CLS_ZPmZ_B: |
| 9684 | case AArch64::CLS_ZPmZ_D: |
| 9685 | case AArch64::CLS_ZPmZ_H: |
| 9686 | case AArch64::CLS_ZPmZ_S: |
| 9687 | case AArch64::CLZ_ZPmZ_B: |
| 9688 | case AArch64::CLZ_ZPmZ_D: |
| 9689 | case AArch64::CLZ_ZPmZ_H: |
| 9690 | case AArch64::CLZ_ZPmZ_S: |
| 9691 | case AArch64::CNOT_ZPmZ_B: |
| 9692 | case AArch64::CNOT_ZPmZ_D: |
| 9693 | case AArch64::CNOT_ZPmZ_H: |
| 9694 | case AArch64::CNOT_ZPmZ_S: |
| 9695 | case AArch64::CNT_ZPmZ_B: |
| 9696 | case AArch64::CNT_ZPmZ_D: |
| 9697 | case AArch64::CNT_ZPmZ_H: |
| 9698 | case AArch64::CNT_ZPmZ_S: |
| 9699 | case AArch64::FABS_ZPmZ_D: |
| 9700 | case AArch64::FABS_ZPmZ_H: |
| 9701 | case AArch64::FABS_ZPmZ_S: |
| 9702 | case AArch64::FCVTX_ZPmZ_DtoS: |
| 9703 | case AArch64::FCVTZS_ZPmZ_DtoD: |
| 9704 | case AArch64::FCVTZS_ZPmZ_DtoS: |
| 9705 | case AArch64::FCVTZS_ZPmZ_HtoD: |
| 9706 | case AArch64::FCVTZS_ZPmZ_HtoH: |
| 9707 | case AArch64::FCVTZS_ZPmZ_HtoS: |
| 9708 | case AArch64::FCVTZS_ZPmZ_StoD: |
| 9709 | case AArch64::FCVTZS_ZPmZ_StoS: |
| 9710 | case AArch64::FCVTZU_ZPmZ_DtoD: |
| 9711 | case AArch64::FCVTZU_ZPmZ_DtoS: |
| 9712 | case AArch64::FCVTZU_ZPmZ_HtoD: |
| 9713 | case AArch64::FCVTZU_ZPmZ_HtoH: |
| 9714 | case AArch64::FCVTZU_ZPmZ_HtoS: |
| 9715 | case AArch64::FCVTZU_ZPmZ_StoD: |
| 9716 | case AArch64::FCVTZU_ZPmZ_StoS: |
| 9717 | case AArch64::FCVT_ZPmZ_DtoH: |
| 9718 | case AArch64::FCVT_ZPmZ_DtoS: |
| 9719 | case AArch64::FCVT_ZPmZ_HtoD: |
| 9720 | case AArch64::FCVT_ZPmZ_HtoS: |
| 9721 | case AArch64::FCVT_ZPmZ_StoD: |
| 9722 | case AArch64::FCVT_ZPmZ_StoH: |
| 9723 | case AArch64::FLOGB_ZPmZ_D: |
| 9724 | case AArch64::FLOGB_ZPmZ_H: |
| 9725 | case AArch64::FLOGB_ZPmZ_S: |
| 9726 | case AArch64::FNEG_ZPmZ_D: |
| 9727 | case AArch64::FNEG_ZPmZ_H: |
| 9728 | case AArch64::FNEG_ZPmZ_S: |
| 9729 | case AArch64::FRECPX_ZPmZ_D: |
| 9730 | case AArch64::FRECPX_ZPmZ_H: |
| 9731 | case AArch64::FRECPX_ZPmZ_S: |
| 9732 | case AArch64::FRINT32X_ZPmZ_D: |
| 9733 | case AArch64::FRINT32X_ZPmZ_S: |
| 9734 | case AArch64::FRINT32Z_ZPmZ_D: |
| 9735 | case AArch64::FRINT32Z_ZPmZ_S: |
| 9736 | case AArch64::FRINT64X_ZPmZ_D: |
| 9737 | case AArch64::FRINT64X_ZPmZ_S: |
| 9738 | case AArch64::FRINT64Z_ZPmZ_D: |
| 9739 | case AArch64::FRINT64Z_ZPmZ_S: |
| 9740 | case AArch64::FRINTA_ZPmZ_D: |
| 9741 | case AArch64::FRINTA_ZPmZ_H: |
| 9742 | case AArch64::FRINTA_ZPmZ_S: |
| 9743 | case AArch64::FRINTI_ZPmZ_D: |
| 9744 | case AArch64::FRINTI_ZPmZ_H: |
| 9745 | case AArch64::FRINTI_ZPmZ_S: |
| 9746 | case AArch64::FRINTM_ZPmZ_D: |
| 9747 | case AArch64::FRINTM_ZPmZ_H: |
| 9748 | case AArch64::FRINTM_ZPmZ_S: |
| 9749 | case AArch64::FRINTN_ZPmZ_D: |
| 9750 | case AArch64::FRINTN_ZPmZ_H: |
| 9751 | case AArch64::FRINTN_ZPmZ_S: |
| 9752 | case AArch64::FRINTP_ZPmZ_D: |
| 9753 | case AArch64::FRINTP_ZPmZ_H: |
| 9754 | case AArch64::FRINTP_ZPmZ_S: |
| 9755 | case AArch64::FRINTX_ZPmZ_D: |
| 9756 | case AArch64::FRINTX_ZPmZ_H: |
| 9757 | case AArch64::FRINTX_ZPmZ_S: |
| 9758 | case AArch64::FRINTZ_ZPmZ_D: |
| 9759 | case AArch64::FRINTZ_ZPmZ_H: |
| 9760 | case AArch64::FRINTZ_ZPmZ_S: |
| 9761 | case AArch64::FSQRT_ZPmZ_D: |
| 9762 | case AArch64::FSQRT_ZPmZ_H: |
| 9763 | case AArch64::FSQRT_ZPmZ_S: |
| 9764 | case AArch64::MOVPRFX_ZPmZ_B: |
| 9765 | case AArch64::MOVPRFX_ZPmZ_D: |
| 9766 | case AArch64::MOVPRFX_ZPmZ_H: |
| 9767 | case AArch64::MOVPRFX_ZPmZ_S: |
| 9768 | case AArch64::NEG_ZPmZ_B: |
| 9769 | case AArch64::NEG_ZPmZ_D: |
| 9770 | case AArch64::NEG_ZPmZ_H: |
| 9771 | case AArch64::NEG_ZPmZ_S: |
| 9772 | case AArch64::NOT_ZPmZ_B: |
| 9773 | case AArch64::NOT_ZPmZ_D: |
| 9774 | case AArch64::NOT_ZPmZ_H: |
| 9775 | case AArch64::NOT_ZPmZ_S: |
| 9776 | case AArch64::SCVTF_ZPmZ_DtoD: |
| 9777 | case AArch64::SCVTF_ZPmZ_DtoH: |
| 9778 | case AArch64::SCVTF_ZPmZ_DtoS: |
| 9779 | case AArch64::SCVTF_ZPmZ_HtoH: |
| 9780 | case AArch64::SCVTF_ZPmZ_StoD: |
| 9781 | case AArch64::SCVTF_ZPmZ_StoH: |
| 9782 | case AArch64::SCVTF_ZPmZ_StoS: |
| 9783 | case AArch64::SQABS_ZPmZ_B: |
| 9784 | case AArch64::SQABS_ZPmZ_D: |
| 9785 | case AArch64::SQABS_ZPmZ_H: |
| 9786 | case AArch64::SQABS_ZPmZ_S: |
| 9787 | case AArch64::SQNEG_ZPmZ_B: |
| 9788 | case AArch64::SQNEG_ZPmZ_D: |
| 9789 | case AArch64::SQNEG_ZPmZ_H: |
| 9790 | case AArch64::SQNEG_ZPmZ_S: |
| 9791 | case AArch64::SXTB_ZPmZ_D: |
| 9792 | case AArch64::SXTB_ZPmZ_H: |
| 9793 | case AArch64::SXTB_ZPmZ_S: |
| 9794 | case AArch64::SXTH_ZPmZ_D: |
| 9795 | case AArch64::SXTH_ZPmZ_S: |
| 9796 | case AArch64::SXTW_ZPmZ_D: |
| 9797 | case AArch64::UCVTF_ZPmZ_DtoD: |
| 9798 | case AArch64::UCVTF_ZPmZ_DtoH: |
| 9799 | case AArch64::UCVTF_ZPmZ_DtoS: |
| 9800 | case AArch64::UCVTF_ZPmZ_HtoH: |
| 9801 | case AArch64::UCVTF_ZPmZ_StoD: |
| 9802 | case AArch64::UCVTF_ZPmZ_StoH: |
| 9803 | case AArch64::UCVTF_ZPmZ_StoS: |
| 9804 | case AArch64::URECPE_ZPmZ_S: |
| 9805 | case AArch64::URSQRTE_ZPmZ_S: |
| 9806 | case AArch64::UXTB_ZPmZ_D: |
| 9807 | case AArch64::UXTB_ZPmZ_H: |
| 9808 | case AArch64::UXTB_ZPmZ_S: |
| 9809 | case AArch64::UXTH_ZPmZ_D: |
| 9810 | case AArch64::UXTH_ZPmZ_S: |
| 9811 | case AArch64::UXTW_ZPmZ_D: { |
| 9812 | // op: Pg |
| 9813 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9814 | Value |= (op & 0x7) << 10; |
| 9815 | // op: Zd |
| 9816 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9817 | Value |= (op & 0x1f); |
| 9818 | // op: Zn |
| 9819 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9820 | Value |= (op & 0x1f) << 5; |
| 9821 | break; |
| 9822 | } |
| 9823 | case AArch64::FCPY_ZPmI_D: |
| 9824 | case AArch64::FCPY_ZPmI_H: |
| 9825 | case AArch64::FCPY_ZPmI_S: { |
| 9826 | // op: Pg |
| 9827 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9828 | Value |= (op & 0xf) << 16; |
| 9829 | // op: Zd |
| 9830 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9831 | Value |= (op & 0x1f); |
| 9832 | // op: imm8 |
| 9833 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9834 | Value |= (op & 0xff) << 5; |
| 9835 | break; |
| 9836 | } |
| 9837 | case AArch64::DECP_ZP_D: |
| 9838 | case AArch64::DECP_ZP_H: |
| 9839 | case AArch64::DECP_ZP_S: |
| 9840 | case AArch64::INCP_ZP_D: |
| 9841 | case AArch64::INCP_ZP_H: |
| 9842 | case AArch64::INCP_ZP_S: |
| 9843 | case AArch64::SQDECP_ZP_D: |
| 9844 | case AArch64::SQDECP_ZP_H: |
| 9845 | case AArch64::SQDECP_ZP_S: |
| 9846 | case AArch64::SQINCP_ZP_D: |
| 9847 | case AArch64::SQINCP_ZP_H: |
| 9848 | case AArch64::SQINCP_ZP_S: |
| 9849 | case AArch64::UQDECP_ZP_D: |
| 9850 | case AArch64::UQDECP_ZP_H: |
| 9851 | case AArch64::UQDECP_ZP_S: |
| 9852 | case AArch64::UQINCP_ZP_D: |
| 9853 | case AArch64::UQINCP_ZP_H: |
| 9854 | case AArch64::UQINCP_ZP_S: { |
| 9855 | // op: Pm |
| 9856 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9857 | Value |= (op & 0xf) << 5; |
| 9858 | // op: Zdn |
| 9859 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9860 | Value |= (op & 0x1f); |
| 9861 | break; |
| 9862 | } |
| 9863 | case AArch64::ADDHA_MPPZ_S: |
| 9864 | case AArch64::ADDVA_MPPZ_S: { |
| 9865 | // op: Pm |
| 9866 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9867 | Value |= (op & 0x7) << 13; |
| 9868 | // op: Pn |
| 9869 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9870 | Value |= (op & 0x7) << 10; |
| 9871 | // op: Zn |
| 9872 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9873 | Value |= (op & 0x1f) << 5; |
| 9874 | // op: ZAda |
| 9875 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9876 | Value |= (op & 0x3); |
| 9877 | break; |
| 9878 | } |
| 9879 | case AArch64::ADDHA_MPPZ_D: |
| 9880 | case AArch64::ADDVA_MPPZ_D: { |
| 9881 | // op: Pm |
| 9882 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 9883 | Value |= (op & 0x7) << 13; |
| 9884 | // op: Pn |
| 9885 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9886 | Value |= (op & 0x7) << 10; |
| 9887 | // op: Zn |
| 9888 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 9889 | Value |= (op & 0x1f) << 5; |
| 9890 | // op: ZAda |
| 9891 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9892 | Value |= (op & 0x7); |
| 9893 | break; |
| 9894 | } |
| 9895 | case AArch64::WRFFR: { |
| 9896 | // op: Pn |
| 9897 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9898 | Value |= (op & 0xf) << 5; |
| 9899 | break; |
| 9900 | } |
| 9901 | case AArch64::LDR_PXI: |
| 9902 | case AArch64::STR_PXI: { |
| 9903 | // op: Pt |
| 9904 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9905 | Value |= (op & 0xf); |
| 9906 | // op: Rn |
| 9907 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9908 | Value |= (op & 0x1f) << 5; |
| 9909 | // op: imm9 |
| 9910 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9911 | Value |= (op & 0x1f8) << 13; |
| 9912 | Value |= (op & 0x7) << 10; |
| 9913 | break; |
| 9914 | } |
| 9915 | case AArch64::XPACD: |
| 9916 | case AArch64::XPACI: { |
| 9917 | // op: Rd |
| 9918 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9919 | Value |= (op & 0x1f); |
| 9920 | break; |
| 9921 | } |
| 9922 | case AArch64::CNTP_XCI_B: |
| 9923 | case AArch64::CNTP_XCI_D: |
| 9924 | case AArch64::CNTP_XCI_H: |
| 9925 | case AArch64::CNTP_XCI_S: { |
| 9926 | // op: Rd |
| 9927 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9928 | Value |= (op & 0x1f); |
| 9929 | // op: PNn |
| 9930 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9931 | Value |= (op & 0xf) << 5; |
| 9932 | // op: vl |
| 9933 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9934 | Value |= (op & 0x1) << 10; |
| 9935 | break; |
| 9936 | } |
| 9937 | case AArch64::ADDPL_XXI: |
| 9938 | case AArch64::ADDSPL_XXI: |
| 9939 | case AArch64::ADDSVL_XXI: |
| 9940 | case AArch64::ADDVL_XXI: { |
| 9941 | // op: Rd |
| 9942 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 9943 | Value |= (op & 0x1f); |
| 9944 | // op: Rn |
| 9945 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 9946 | Value |= (op & 0x1f) << 16; |
| 9947 | // op: imm6 |
| 9948 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 9949 | Value |= (op & 0x3f) << 5; |
| 9950 | break; |
| 9951 | } |
| 9952 | case AArch64::ABSWr: |
| 9953 | case AArch64::ABSXr: |
| 9954 | case AArch64::ABSv16i8: |
| 9955 | case AArch64::ABSv1i64: |
| 9956 | case AArch64::ABSv2i32: |
| 9957 | case AArch64::ABSv2i64: |
| 9958 | case AArch64::ABSv4i16: |
| 9959 | case AArch64::ABSv4i32: |
| 9960 | case AArch64::ABSv8i16: |
| 9961 | case AArch64::ABSv8i8: |
| 9962 | case AArch64::ADDPv2i64p: |
| 9963 | case AArch64::ADDVv16i8v: |
| 9964 | case AArch64::ADDVv4i16v: |
| 9965 | case AArch64::ADDVv4i32v: |
| 9966 | case AArch64::ADDVv8i16v: |
| 9967 | case AArch64::ADDVv8i8v: |
| 9968 | case AArch64::AESIMCrr: |
| 9969 | case AArch64::AESMCrr: |
| 9970 | case AArch64::BF1CVTL: |
| 9971 | case AArch64::BF1CVTL2: |
| 9972 | case AArch64::BF2CVTL: |
| 9973 | case AArch64::BF2CVTL2: |
| 9974 | case AArch64::BFCVT: |
| 9975 | case AArch64::BFCVTN: |
| 9976 | case AArch64::CLSWr: |
| 9977 | case AArch64::CLSXr: |
| 9978 | case AArch64::CLSv16i8: |
| 9979 | case AArch64::CLSv2i32: |
| 9980 | case AArch64::CLSv4i16: |
| 9981 | case AArch64::CLSv4i32: |
| 9982 | case AArch64::CLSv8i16: |
| 9983 | case AArch64::CLSv8i8: |
| 9984 | case AArch64::CLZWr: |
| 9985 | case AArch64::CLZXr: |
| 9986 | case AArch64::CLZv16i8: |
| 9987 | case AArch64::CLZv2i32: |
| 9988 | case AArch64::CLZv4i16: |
| 9989 | case AArch64::CLZv4i32: |
| 9990 | case AArch64::CLZv8i16: |
| 9991 | case AArch64::CLZv8i8: |
| 9992 | case AArch64::CMEQv16i8rz: |
| 9993 | case AArch64::CMEQv1i64rz: |
| 9994 | case AArch64::CMEQv2i32rz: |
| 9995 | case AArch64::CMEQv2i64rz: |
| 9996 | case AArch64::CMEQv4i16rz: |
| 9997 | case AArch64::CMEQv4i32rz: |
| 9998 | case AArch64::CMEQv8i16rz: |
| 9999 | case AArch64::CMEQv8i8rz: |
| 10000 | case AArch64::CMGEv16i8rz: |
| 10001 | case AArch64::CMGEv1i64rz: |
| 10002 | case AArch64::CMGEv2i32rz: |
| 10003 | case AArch64::CMGEv2i64rz: |
| 10004 | case AArch64::CMGEv4i16rz: |
| 10005 | case AArch64::CMGEv4i32rz: |
| 10006 | case AArch64::CMGEv8i16rz: |
| 10007 | case AArch64::CMGEv8i8rz: |
| 10008 | case AArch64::CMGTv16i8rz: |
| 10009 | case AArch64::CMGTv1i64rz: |
| 10010 | case AArch64::CMGTv2i32rz: |
| 10011 | case AArch64::CMGTv2i64rz: |
| 10012 | case AArch64::CMGTv4i16rz: |
| 10013 | case AArch64::CMGTv4i32rz: |
| 10014 | case AArch64::CMGTv8i16rz: |
| 10015 | case AArch64::CMGTv8i8rz: |
| 10016 | case AArch64::CMLEv16i8rz: |
| 10017 | case AArch64::CMLEv1i64rz: |
| 10018 | case AArch64::CMLEv2i32rz: |
| 10019 | case AArch64::CMLEv2i64rz: |
| 10020 | case AArch64::CMLEv4i16rz: |
| 10021 | case AArch64::CMLEv4i32rz: |
| 10022 | case AArch64::CMLEv8i16rz: |
| 10023 | case AArch64::CMLEv8i8rz: |
| 10024 | case AArch64::CMLTv16i8rz: |
| 10025 | case AArch64::CMLTv1i64rz: |
| 10026 | case AArch64::CMLTv2i32rz: |
| 10027 | case AArch64::CMLTv2i64rz: |
| 10028 | case AArch64::CMLTv4i16rz: |
| 10029 | case AArch64::CMLTv4i32rz: |
| 10030 | case AArch64::CMLTv8i16rz: |
| 10031 | case AArch64::CMLTv8i8rz: |
| 10032 | case AArch64::CNTWr: |
| 10033 | case AArch64::CNTXr: |
| 10034 | case AArch64::CNTv16i8: |
| 10035 | case AArch64::CNTv8i8: |
| 10036 | case AArch64::CTZWr: |
| 10037 | case AArch64::CTZXr: |
| 10038 | case AArch64::DUPv16i8gpr: |
| 10039 | case AArch64::DUPv2i32gpr: |
| 10040 | case AArch64::DUPv2i64gpr: |
| 10041 | case AArch64::DUPv4i16gpr: |
| 10042 | case AArch64::DUPv4i32gpr: |
| 10043 | case AArch64::DUPv8i16gpr: |
| 10044 | case AArch64::DUPv8i8gpr: |
| 10045 | case AArch64::F1CVTL: |
| 10046 | case AArch64::F1CVTL2: |
| 10047 | case AArch64::F2CVTL: |
| 10048 | case AArch64::F2CVTL2: |
| 10049 | case AArch64::FABSDr: |
| 10050 | case AArch64::FABSHr: |
| 10051 | case AArch64::FABSSr: |
| 10052 | case AArch64::FABSv2f32: |
| 10053 | case AArch64::FABSv2f64: |
| 10054 | case AArch64::FABSv4f16: |
| 10055 | case AArch64::FABSv4f32: |
| 10056 | case AArch64::FABSv8f16: |
| 10057 | case AArch64::FADDPv2i16p: |
| 10058 | case AArch64::FADDPv2i32p: |
| 10059 | case AArch64::FADDPv2i64p: |
| 10060 | case AArch64::FCMEQv1i16rz: |
| 10061 | case AArch64::FCMEQv1i32rz: |
| 10062 | case AArch64::FCMEQv1i64rz: |
| 10063 | case AArch64::FCMEQv2i32rz: |
| 10064 | case AArch64::FCMEQv2i64rz: |
| 10065 | case AArch64::FCMEQv4i16rz: |
| 10066 | case AArch64::FCMEQv4i32rz: |
| 10067 | case AArch64::FCMEQv8i16rz: |
| 10068 | case AArch64::FCMGEv1i16rz: |
| 10069 | case AArch64::FCMGEv1i32rz: |
| 10070 | case AArch64::FCMGEv1i64rz: |
| 10071 | case AArch64::FCMGEv2i32rz: |
| 10072 | case AArch64::FCMGEv2i64rz: |
| 10073 | case AArch64::FCMGEv4i16rz: |
| 10074 | case AArch64::FCMGEv4i32rz: |
| 10075 | case AArch64::FCMGEv8i16rz: |
| 10076 | case AArch64::FCMGTv1i16rz: |
| 10077 | case AArch64::FCMGTv1i32rz: |
| 10078 | case AArch64::FCMGTv1i64rz: |
| 10079 | case AArch64::FCMGTv2i32rz: |
| 10080 | case AArch64::FCMGTv2i64rz: |
| 10081 | case AArch64::FCMGTv4i16rz: |
| 10082 | case AArch64::FCMGTv4i32rz: |
| 10083 | case AArch64::FCMGTv8i16rz: |
| 10084 | case AArch64::FCMLEv1i16rz: |
| 10085 | case AArch64::FCMLEv1i32rz: |
| 10086 | case AArch64::FCMLEv1i64rz: |
| 10087 | case AArch64::FCMLEv2i32rz: |
| 10088 | case AArch64::FCMLEv2i64rz: |
| 10089 | case AArch64::FCMLEv4i16rz: |
| 10090 | case AArch64::FCMLEv4i32rz: |
| 10091 | case AArch64::FCMLEv8i16rz: |
| 10092 | case AArch64::FCMLTv1i16rz: |
| 10093 | case AArch64::FCMLTv1i32rz: |
| 10094 | case AArch64::FCMLTv1i64rz: |
| 10095 | case AArch64::FCMLTv2i32rz: |
| 10096 | case AArch64::FCMLTv2i64rz: |
| 10097 | case AArch64::FCMLTv4i16rz: |
| 10098 | case AArch64::FCMLTv4i32rz: |
| 10099 | case AArch64::FCMLTv8i16rz: |
| 10100 | case AArch64::FCVTASDHr: |
| 10101 | case AArch64::FCVTASDSr: |
| 10102 | case AArch64::FCVTASSDr: |
| 10103 | case AArch64::FCVTASSHr: |
| 10104 | case AArch64::FCVTASUWDr: |
| 10105 | case AArch64::FCVTASUWHr: |
| 10106 | case AArch64::FCVTASUWSr: |
| 10107 | case AArch64::FCVTASUXDr: |
| 10108 | case AArch64::FCVTASUXHr: |
| 10109 | case AArch64::FCVTASUXSr: |
| 10110 | case AArch64::FCVTASv1f16: |
| 10111 | case AArch64::FCVTASv1i32: |
| 10112 | case AArch64::FCVTASv1i64: |
| 10113 | case AArch64::FCVTASv2f32: |
| 10114 | case AArch64::FCVTASv2f64: |
| 10115 | case AArch64::FCVTASv4f16: |
| 10116 | case AArch64::FCVTASv4f32: |
| 10117 | case AArch64::FCVTASv8f16: |
| 10118 | case AArch64::FCVTAUDHr: |
| 10119 | case AArch64::FCVTAUDSr: |
| 10120 | case AArch64::FCVTAUSDr: |
| 10121 | case AArch64::FCVTAUSHr: |
| 10122 | case AArch64::FCVTAUUWDr: |
| 10123 | case AArch64::FCVTAUUWHr: |
| 10124 | case AArch64::FCVTAUUWSr: |
| 10125 | case AArch64::FCVTAUUXDr: |
| 10126 | case AArch64::FCVTAUUXHr: |
| 10127 | case AArch64::FCVTAUUXSr: |
| 10128 | case AArch64::FCVTAUv1f16: |
| 10129 | case AArch64::FCVTAUv1i32: |
| 10130 | case AArch64::FCVTAUv1i64: |
| 10131 | case AArch64::FCVTAUv2f32: |
| 10132 | case AArch64::FCVTAUv2f64: |
| 10133 | case AArch64::FCVTAUv4f16: |
| 10134 | case AArch64::FCVTAUv4f32: |
| 10135 | case AArch64::FCVTAUv8f16: |
| 10136 | case AArch64::FCVTDHr: |
| 10137 | case AArch64::FCVTDSr: |
| 10138 | case AArch64::FCVTHDr: |
| 10139 | case AArch64::FCVTHSr: |
| 10140 | case AArch64::FCVTLv2i32: |
| 10141 | case AArch64::FCVTLv4i16: |
| 10142 | case AArch64::FCVTLv4i32: |
| 10143 | case AArch64::FCVTLv8i16: |
| 10144 | case AArch64::FCVTMSDHr: |
| 10145 | case AArch64::FCVTMSDSr: |
| 10146 | case AArch64::FCVTMSSDr: |
| 10147 | case AArch64::FCVTMSSHr: |
| 10148 | case AArch64::FCVTMSUWDr: |
| 10149 | case AArch64::FCVTMSUWHr: |
| 10150 | case AArch64::FCVTMSUWSr: |
| 10151 | case AArch64::FCVTMSUXDr: |
| 10152 | case AArch64::FCVTMSUXHr: |
| 10153 | case AArch64::FCVTMSUXSr: |
| 10154 | case AArch64::FCVTMSv1f16: |
| 10155 | case AArch64::FCVTMSv1i32: |
| 10156 | case AArch64::FCVTMSv1i64: |
| 10157 | case AArch64::FCVTMSv2f32: |
| 10158 | case AArch64::FCVTMSv2f64: |
| 10159 | case AArch64::FCVTMSv4f16: |
| 10160 | case AArch64::FCVTMSv4f32: |
| 10161 | case AArch64::FCVTMSv8f16: |
| 10162 | case AArch64::FCVTMUDHr: |
| 10163 | case AArch64::FCVTMUDSr: |
| 10164 | case AArch64::FCVTMUSDr: |
| 10165 | case AArch64::FCVTMUSHr: |
| 10166 | case AArch64::FCVTMUUWDr: |
| 10167 | case AArch64::FCVTMUUWHr: |
| 10168 | case AArch64::FCVTMUUWSr: |
| 10169 | case AArch64::FCVTMUUXDr: |
| 10170 | case AArch64::FCVTMUUXHr: |
| 10171 | case AArch64::FCVTMUUXSr: |
| 10172 | case AArch64::FCVTMUv1f16: |
| 10173 | case AArch64::FCVTMUv1i32: |
| 10174 | case AArch64::FCVTMUv1i64: |
| 10175 | case AArch64::FCVTMUv2f32: |
| 10176 | case AArch64::FCVTMUv2f64: |
| 10177 | case AArch64::FCVTMUv4f16: |
| 10178 | case AArch64::FCVTMUv4f32: |
| 10179 | case AArch64::FCVTMUv8f16: |
| 10180 | case AArch64::FCVTNSDHr: |
| 10181 | case AArch64::FCVTNSDSr: |
| 10182 | case AArch64::FCVTNSSDr: |
| 10183 | case AArch64::FCVTNSSHr: |
| 10184 | case AArch64::FCVTNSUWDr: |
| 10185 | case AArch64::FCVTNSUWHr: |
| 10186 | case AArch64::FCVTNSUWSr: |
| 10187 | case AArch64::FCVTNSUXDr: |
| 10188 | case AArch64::FCVTNSUXHr: |
| 10189 | case AArch64::FCVTNSUXSr: |
| 10190 | case AArch64::FCVTNSv1f16: |
| 10191 | case AArch64::FCVTNSv1i32: |
| 10192 | case AArch64::FCVTNSv1i64: |
| 10193 | case AArch64::FCVTNSv2f32: |
| 10194 | case AArch64::FCVTNSv2f64: |
| 10195 | case AArch64::FCVTNSv4f16: |
| 10196 | case AArch64::FCVTNSv4f32: |
| 10197 | case AArch64::FCVTNSv8f16: |
| 10198 | case AArch64::FCVTNUDHr: |
| 10199 | case AArch64::FCVTNUDSr: |
| 10200 | case AArch64::FCVTNUSDr: |
| 10201 | case AArch64::FCVTNUSHr: |
| 10202 | case AArch64::FCVTNUUWDr: |
| 10203 | case AArch64::FCVTNUUWHr: |
| 10204 | case AArch64::FCVTNUUWSr: |
| 10205 | case AArch64::FCVTNUUXDr: |
| 10206 | case AArch64::FCVTNUUXHr: |
| 10207 | case AArch64::FCVTNUUXSr: |
| 10208 | case AArch64::FCVTNUv1f16: |
| 10209 | case AArch64::FCVTNUv1i32: |
| 10210 | case AArch64::FCVTNUv1i64: |
| 10211 | case AArch64::FCVTNUv2f32: |
| 10212 | case AArch64::FCVTNUv2f64: |
| 10213 | case AArch64::FCVTNUv4f16: |
| 10214 | case AArch64::FCVTNUv4f32: |
| 10215 | case AArch64::FCVTNUv8f16: |
| 10216 | case AArch64::FCVTNv2i32: |
| 10217 | case AArch64::FCVTNv4i16: |
| 10218 | case AArch64::FCVTPSDHr: |
| 10219 | case AArch64::FCVTPSDSr: |
| 10220 | case AArch64::FCVTPSSDr: |
| 10221 | case AArch64::FCVTPSSHr: |
| 10222 | case AArch64::FCVTPSUWDr: |
| 10223 | case AArch64::FCVTPSUWHr: |
| 10224 | case AArch64::FCVTPSUWSr: |
| 10225 | case AArch64::FCVTPSUXDr: |
| 10226 | case AArch64::FCVTPSUXHr: |
| 10227 | case AArch64::FCVTPSUXSr: |
| 10228 | case AArch64::FCVTPSv1f16: |
| 10229 | case AArch64::FCVTPSv1i32: |
| 10230 | case AArch64::FCVTPSv1i64: |
| 10231 | case AArch64::FCVTPSv2f32: |
| 10232 | case AArch64::FCVTPSv2f64: |
| 10233 | case AArch64::FCVTPSv4f16: |
| 10234 | case AArch64::FCVTPSv4f32: |
| 10235 | case AArch64::FCVTPSv8f16: |
| 10236 | case AArch64::FCVTPUDHr: |
| 10237 | case AArch64::FCVTPUDSr: |
| 10238 | case AArch64::FCVTPUSDr: |
| 10239 | case AArch64::FCVTPUSHr: |
| 10240 | case AArch64::FCVTPUUWDr: |
| 10241 | case AArch64::FCVTPUUWHr: |
| 10242 | case AArch64::FCVTPUUWSr: |
| 10243 | case AArch64::FCVTPUUXDr: |
| 10244 | case AArch64::FCVTPUUXHr: |
| 10245 | case AArch64::FCVTPUUXSr: |
| 10246 | case AArch64::FCVTPUv1f16: |
| 10247 | case AArch64::FCVTPUv1i32: |
| 10248 | case AArch64::FCVTPUv1i64: |
| 10249 | case AArch64::FCVTPUv2f32: |
| 10250 | case AArch64::FCVTPUv2f64: |
| 10251 | case AArch64::FCVTPUv4f16: |
| 10252 | case AArch64::FCVTPUv4f32: |
| 10253 | case AArch64::FCVTPUv8f16: |
| 10254 | case AArch64::FCVTSDr: |
| 10255 | case AArch64::FCVTSHr: |
| 10256 | case AArch64::FCVTXNv1i64: |
| 10257 | case AArch64::FCVTXNv2f32: |
| 10258 | case AArch64::FCVTZSDHr: |
| 10259 | case AArch64::FCVTZSDSr: |
| 10260 | case AArch64::FCVTZSSDr: |
| 10261 | case AArch64::FCVTZSSHr: |
| 10262 | case AArch64::FCVTZSUWDr: |
| 10263 | case AArch64::FCVTZSUWHr: |
| 10264 | case AArch64::FCVTZSUWSr: |
| 10265 | case AArch64::FCVTZSUXDr: |
| 10266 | case AArch64::FCVTZSUXHr: |
| 10267 | case AArch64::FCVTZSUXSr: |
| 10268 | case AArch64::FCVTZSv1f16: |
| 10269 | case AArch64::FCVTZSv1i32: |
| 10270 | case AArch64::FCVTZSv1i64: |
| 10271 | case AArch64::FCVTZSv2f32: |
| 10272 | case AArch64::FCVTZSv2f64: |
| 10273 | case AArch64::FCVTZSv4f16: |
| 10274 | case AArch64::FCVTZSv4f32: |
| 10275 | case AArch64::FCVTZSv8f16: |
| 10276 | case AArch64::FCVTZUDHr: |
| 10277 | case AArch64::FCVTZUDSr: |
| 10278 | case AArch64::FCVTZUSDr: |
| 10279 | case AArch64::FCVTZUSHr: |
| 10280 | case AArch64::FCVTZUUWDr: |
| 10281 | case AArch64::FCVTZUUWHr: |
| 10282 | case AArch64::FCVTZUUWSr: |
| 10283 | case AArch64::FCVTZUUXDr: |
| 10284 | case AArch64::FCVTZUUXHr: |
| 10285 | case AArch64::FCVTZUUXSr: |
| 10286 | case AArch64::FCVTZUv1f16: |
| 10287 | case AArch64::FCVTZUv1i32: |
| 10288 | case AArch64::FCVTZUv1i64: |
| 10289 | case AArch64::FCVTZUv2f32: |
| 10290 | case AArch64::FCVTZUv2f64: |
| 10291 | case AArch64::FCVTZUv4f16: |
| 10292 | case AArch64::FCVTZUv4f32: |
| 10293 | case AArch64::FCVTZUv8f16: |
| 10294 | case AArch64::FJCVTZS: |
| 10295 | case AArch64::FMAXNMPv2i16p: |
| 10296 | case AArch64::FMAXNMPv2i32p: |
| 10297 | case AArch64::FMAXNMPv2i64p: |
| 10298 | case AArch64::FMAXNMVv4i16v: |
| 10299 | case AArch64::FMAXNMVv4i32v: |
| 10300 | case AArch64::FMAXNMVv8i16v: |
| 10301 | case AArch64::FMAXPv2i16p: |
| 10302 | case AArch64::FMAXPv2i32p: |
| 10303 | case AArch64::FMAXPv2i64p: |
| 10304 | case AArch64::FMAXVv4i16v: |
| 10305 | case AArch64::FMAXVv4i32v: |
| 10306 | case AArch64::FMAXVv8i16v: |
| 10307 | case AArch64::FMINNMPv2i16p: |
| 10308 | case AArch64::FMINNMPv2i32p: |
| 10309 | case AArch64::FMINNMPv2i64p: |
| 10310 | case AArch64::FMINNMVv4i16v: |
| 10311 | case AArch64::FMINNMVv4i32v: |
| 10312 | case AArch64::FMINNMVv8i16v: |
| 10313 | case AArch64::FMINPv2i16p: |
| 10314 | case AArch64::FMINPv2i32p: |
| 10315 | case AArch64::FMINPv2i64p: |
| 10316 | case AArch64::FMINVv4i16v: |
| 10317 | case AArch64::FMINVv4i32v: |
| 10318 | case AArch64::FMINVv8i16v: |
| 10319 | case AArch64::FMOVDXHighr: |
| 10320 | case AArch64::FMOVDXr: |
| 10321 | case AArch64::FMOVDr: |
| 10322 | case AArch64::FMOVHWr: |
| 10323 | case AArch64::FMOVHXr: |
| 10324 | case AArch64::FMOVHr: |
| 10325 | case AArch64::FMOVSWr: |
| 10326 | case AArch64::FMOVSr: |
| 10327 | case AArch64::FMOVWHr: |
| 10328 | case AArch64::FMOVWSr: |
| 10329 | case AArch64::FMOVXDHighr: |
| 10330 | case AArch64::FMOVXDr: |
| 10331 | case AArch64::FMOVXHr: |
| 10332 | case AArch64::FNEGDr: |
| 10333 | case AArch64::FNEGHr: |
| 10334 | case AArch64::FNEGSr: |
| 10335 | case AArch64::FNEGv2f32: |
| 10336 | case AArch64::FNEGv2f64: |
| 10337 | case AArch64::FNEGv4f16: |
| 10338 | case AArch64::FNEGv4f32: |
| 10339 | case AArch64::FNEGv8f16: |
| 10340 | case AArch64::FRECPEv1f16: |
| 10341 | case AArch64::FRECPEv1i32: |
| 10342 | case AArch64::FRECPEv1i64: |
| 10343 | case AArch64::FRECPEv2f32: |
| 10344 | case AArch64::FRECPEv2f64: |
| 10345 | case AArch64::FRECPEv4f16: |
| 10346 | case AArch64::FRECPEv4f32: |
| 10347 | case AArch64::FRECPEv8f16: |
| 10348 | case AArch64::FRECPXv1f16: |
| 10349 | case AArch64::FRECPXv1i32: |
| 10350 | case AArch64::FRECPXv1i64: |
| 10351 | case AArch64::FRINT32XDr: |
| 10352 | case AArch64::FRINT32XSr: |
| 10353 | case AArch64::FRINT32Xv2f32: |
| 10354 | case AArch64::FRINT32Xv2f64: |
| 10355 | case AArch64::FRINT32Xv4f32: |
| 10356 | case AArch64::FRINT32ZDr: |
| 10357 | case AArch64::FRINT32ZSr: |
| 10358 | case AArch64::FRINT32Zv2f32: |
| 10359 | case AArch64::FRINT32Zv2f64: |
| 10360 | case AArch64::FRINT32Zv4f32: |
| 10361 | case AArch64::FRINT64XDr: |
| 10362 | case AArch64::FRINT64XSr: |
| 10363 | case AArch64::FRINT64Xv2f32: |
| 10364 | case AArch64::FRINT64Xv2f64: |
| 10365 | case AArch64::FRINT64Xv4f32: |
| 10366 | case AArch64::FRINT64ZDr: |
| 10367 | case AArch64::FRINT64ZSr: |
| 10368 | case AArch64::FRINT64Zv2f32: |
| 10369 | case AArch64::FRINT64Zv2f64: |
| 10370 | case AArch64::FRINT64Zv4f32: |
| 10371 | case AArch64::FRINTADr: |
| 10372 | case AArch64::FRINTAHr: |
| 10373 | case AArch64::FRINTASr: |
| 10374 | case AArch64::FRINTAv2f32: |
| 10375 | case AArch64::FRINTAv2f64: |
| 10376 | case AArch64::FRINTAv4f16: |
| 10377 | case AArch64::FRINTAv4f32: |
| 10378 | case AArch64::FRINTAv8f16: |
| 10379 | case AArch64::FRINTIDr: |
| 10380 | case AArch64::FRINTIHr: |
| 10381 | case AArch64::FRINTISr: |
| 10382 | case AArch64::FRINTIv2f32: |
| 10383 | case AArch64::FRINTIv2f64: |
| 10384 | case AArch64::FRINTIv4f16: |
| 10385 | case AArch64::FRINTIv4f32: |
| 10386 | case AArch64::FRINTIv8f16: |
| 10387 | case AArch64::FRINTMDr: |
| 10388 | case AArch64::FRINTMHr: |
| 10389 | case AArch64::FRINTMSr: |
| 10390 | case AArch64::FRINTMv2f32: |
| 10391 | case AArch64::FRINTMv2f64: |
| 10392 | case AArch64::FRINTMv4f16: |
| 10393 | case AArch64::FRINTMv4f32: |
| 10394 | case AArch64::FRINTMv8f16: |
| 10395 | case AArch64::FRINTNDr: |
| 10396 | case AArch64::FRINTNHr: |
| 10397 | case AArch64::FRINTNSr: |
| 10398 | case AArch64::FRINTNv2f32: |
| 10399 | case AArch64::FRINTNv2f64: |
| 10400 | case AArch64::FRINTNv4f16: |
| 10401 | case AArch64::FRINTNv4f32: |
| 10402 | case AArch64::FRINTNv8f16: |
| 10403 | case AArch64::FRINTPDr: |
| 10404 | case AArch64::FRINTPHr: |
| 10405 | case AArch64::FRINTPSr: |
| 10406 | case AArch64::FRINTPv2f32: |
| 10407 | case AArch64::FRINTPv2f64: |
| 10408 | case AArch64::FRINTPv4f16: |
| 10409 | case AArch64::FRINTPv4f32: |
| 10410 | case AArch64::FRINTPv8f16: |
| 10411 | case AArch64::FRINTXDr: |
| 10412 | case AArch64::FRINTXHr: |
| 10413 | case AArch64::FRINTXSr: |
| 10414 | case AArch64::FRINTXv2f32: |
| 10415 | case AArch64::FRINTXv2f64: |
| 10416 | case AArch64::FRINTXv4f16: |
| 10417 | case AArch64::FRINTXv4f32: |
| 10418 | case AArch64::FRINTXv8f16: |
| 10419 | case AArch64::FRINTZDr: |
| 10420 | case AArch64::FRINTZHr: |
| 10421 | case AArch64::FRINTZSr: |
| 10422 | case AArch64::FRINTZv2f32: |
| 10423 | case AArch64::FRINTZv2f64: |
| 10424 | case AArch64::FRINTZv4f16: |
| 10425 | case AArch64::FRINTZv4f32: |
| 10426 | case AArch64::FRINTZv8f16: |
| 10427 | case AArch64::FRSQRTEv1f16: |
| 10428 | case AArch64::FRSQRTEv1i32: |
| 10429 | case AArch64::FRSQRTEv1i64: |
| 10430 | case AArch64::FRSQRTEv2f32: |
| 10431 | case AArch64::FRSQRTEv2f64: |
| 10432 | case AArch64::FRSQRTEv4f16: |
| 10433 | case AArch64::FRSQRTEv4f32: |
| 10434 | case AArch64::FRSQRTEv8f16: |
| 10435 | case AArch64::FSQRTDr: |
| 10436 | case AArch64::FSQRTHr: |
| 10437 | case AArch64::FSQRTSr: |
| 10438 | case AArch64::FSQRTv2f32: |
| 10439 | case AArch64::FSQRTv2f64: |
| 10440 | case AArch64::FSQRTv4f16: |
| 10441 | case AArch64::FSQRTv4f32: |
| 10442 | case AArch64::FSQRTv8f16: |
| 10443 | case AArch64::NEGv16i8: |
| 10444 | case AArch64::NEGv1i64: |
| 10445 | case AArch64::NEGv2i32: |
| 10446 | case AArch64::NEGv2i64: |
| 10447 | case AArch64::NEGv4i16: |
| 10448 | case AArch64::NEGv4i32: |
| 10449 | case AArch64::NEGv8i16: |
| 10450 | case AArch64::NEGv8i8: |
| 10451 | case AArch64::NOTv16i8: |
| 10452 | case AArch64::NOTv8i8: |
| 10453 | case AArch64::RBITWr: |
| 10454 | case AArch64::RBITXr: |
| 10455 | case AArch64::RBITv16i8: |
| 10456 | case AArch64::RBITv8i8: |
| 10457 | case AArch64::REV16Wr: |
| 10458 | case AArch64::REV16Xr: |
| 10459 | case AArch64::REV16v16i8: |
| 10460 | case AArch64::REV16v8i8: |
| 10461 | case AArch64::REV32Xr: |
| 10462 | case AArch64::REV32v16i8: |
| 10463 | case AArch64::REV32v4i16: |
| 10464 | case AArch64::REV32v8i16: |
| 10465 | case AArch64::REV32v8i8: |
| 10466 | case AArch64::REV64v16i8: |
| 10467 | case AArch64::REV64v2i32: |
| 10468 | case AArch64::REV64v4i16: |
| 10469 | case AArch64::REV64v4i32: |
| 10470 | case AArch64::REV64v8i16: |
| 10471 | case AArch64::REV64v8i8: |
| 10472 | case AArch64::REVWr: |
| 10473 | case AArch64::REVXr: |
| 10474 | case AArch64::SADDLPv16i8_v8i16: |
| 10475 | case AArch64::SADDLPv2i32_v1i64: |
| 10476 | case AArch64::SADDLPv4i16_v2i32: |
| 10477 | case AArch64::SADDLPv4i32_v2i64: |
| 10478 | case AArch64::SADDLPv8i16_v4i32: |
| 10479 | case AArch64::SADDLPv8i8_v4i16: |
| 10480 | case AArch64::SADDLVv16i8v: |
| 10481 | case AArch64::SADDLVv4i16v: |
| 10482 | case AArch64::SADDLVv4i32v: |
| 10483 | case AArch64::SADDLVv8i16v: |
| 10484 | case AArch64::SADDLVv8i8v: |
| 10485 | case AArch64::SCVTFDSr: |
| 10486 | case AArch64::SCVTFHDr: |
| 10487 | case AArch64::SCVTFHSr: |
| 10488 | case AArch64::SCVTFSDr: |
| 10489 | case AArch64::SCVTFUWDri: |
| 10490 | case AArch64::SCVTFUWHri: |
| 10491 | case AArch64::SCVTFUWSri: |
| 10492 | case AArch64::SCVTFUXDri: |
| 10493 | case AArch64::SCVTFUXHri: |
| 10494 | case AArch64::SCVTFUXSri: |
| 10495 | case AArch64::SCVTFv1i16: |
| 10496 | case AArch64::SCVTFv1i32: |
| 10497 | case AArch64::SCVTFv1i64: |
| 10498 | case AArch64::SCVTFv2f32: |
| 10499 | case AArch64::SCVTFv2f64: |
| 10500 | case AArch64::SCVTFv4f16: |
| 10501 | case AArch64::SCVTFv4f32: |
| 10502 | case AArch64::SCVTFv8f16: |
| 10503 | case AArch64::SHA1Hrr: |
| 10504 | case AArch64::SHLLv16i8: |
| 10505 | case AArch64::SHLLv2i32: |
| 10506 | case AArch64::SHLLv4i16: |
| 10507 | case AArch64::SHLLv4i32: |
| 10508 | case AArch64::SHLLv8i16: |
| 10509 | case AArch64::SHLLv8i8: |
| 10510 | case AArch64::SMAXVv16i8v: |
| 10511 | case AArch64::SMAXVv4i16v: |
| 10512 | case AArch64::SMAXVv4i32v: |
| 10513 | case AArch64::SMAXVv8i16v: |
| 10514 | case AArch64::SMAXVv8i8v: |
| 10515 | case AArch64::SMINVv16i8v: |
| 10516 | case AArch64::SMINVv4i16v: |
| 10517 | case AArch64::SMINVv4i32v: |
| 10518 | case AArch64::SMINVv8i16v: |
| 10519 | case AArch64::SMINVv8i8v: |
| 10520 | case AArch64::SMOVvi16to32_idx0: |
| 10521 | case AArch64::SMOVvi16to64_idx0: |
| 10522 | case AArch64::SMOVvi32to64_idx0: |
| 10523 | case AArch64::SMOVvi8to32_idx0: |
| 10524 | case AArch64::SMOVvi8to64_idx0: |
| 10525 | case AArch64::SQABSv16i8: |
| 10526 | case AArch64::SQABSv1i16: |
| 10527 | case AArch64::SQABSv1i32: |
| 10528 | case AArch64::SQABSv1i64: |
| 10529 | case AArch64::SQABSv1i8: |
| 10530 | case AArch64::SQABSv2i32: |
| 10531 | case AArch64::SQABSv2i64: |
| 10532 | case AArch64::SQABSv4i16: |
| 10533 | case AArch64::SQABSv4i32: |
| 10534 | case AArch64::SQABSv8i16: |
| 10535 | case AArch64::SQABSv8i8: |
| 10536 | case AArch64::SQNEGv16i8: |
| 10537 | case AArch64::SQNEGv1i16: |
| 10538 | case AArch64::SQNEGv1i32: |
| 10539 | case AArch64::SQNEGv1i64: |
| 10540 | case AArch64::SQNEGv1i8: |
| 10541 | case AArch64::SQNEGv2i32: |
| 10542 | case AArch64::SQNEGv2i64: |
| 10543 | case AArch64::SQNEGv4i16: |
| 10544 | case AArch64::SQNEGv4i32: |
| 10545 | case AArch64::SQNEGv8i16: |
| 10546 | case AArch64::SQNEGv8i8: |
| 10547 | case AArch64::SQXTNv1i16: |
| 10548 | case AArch64::SQXTNv1i32: |
| 10549 | case AArch64::SQXTNv1i8: |
| 10550 | case AArch64::SQXTNv2i32: |
| 10551 | case AArch64::SQXTNv4i16: |
| 10552 | case AArch64::SQXTNv8i8: |
| 10553 | case AArch64::SQXTUNv1i16: |
| 10554 | case AArch64::SQXTUNv1i32: |
| 10555 | case AArch64::SQXTUNv1i8: |
| 10556 | case AArch64::SQXTUNv2i32: |
| 10557 | case AArch64::SQXTUNv4i16: |
| 10558 | case AArch64::SQXTUNv8i8: |
| 10559 | case AArch64::UADDLPv16i8_v8i16: |
| 10560 | case AArch64::UADDLPv2i32_v1i64: |
| 10561 | case AArch64::UADDLPv4i16_v2i32: |
| 10562 | case AArch64::UADDLPv4i32_v2i64: |
| 10563 | case AArch64::UADDLPv8i16_v4i32: |
| 10564 | case AArch64::UADDLPv8i8_v4i16: |
| 10565 | case AArch64::UADDLVv16i8v: |
| 10566 | case AArch64::UADDLVv4i16v: |
| 10567 | case AArch64::UADDLVv4i32v: |
| 10568 | case AArch64::UADDLVv8i16v: |
| 10569 | case AArch64::UADDLVv8i8v: |
| 10570 | case AArch64::UCVTFDSr: |
| 10571 | case AArch64::UCVTFHDr: |
| 10572 | case AArch64::UCVTFHSr: |
| 10573 | case AArch64::UCVTFSDr: |
| 10574 | case AArch64::UCVTFUWDri: |
| 10575 | case AArch64::UCVTFUWHri: |
| 10576 | case AArch64::UCVTFUWSri: |
| 10577 | case AArch64::UCVTFUXDri: |
| 10578 | case AArch64::UCVTFUXHri: |
| 10579 | case AArch64::UCVTFUXSri: |
| 10580 | case AArch64::UCVTFv1i16: |
| 10581 | case AArch64::UCVTFv1i32: |
| 10582 | case AArch64::UCVTFv1i64: |
| 10583 | case AArch64::UCVTFv2f32: |
| 10584 | case AArch64::UCVTFv2f64: |
| 10585 | case AArch64::UCVTFv4f16: |
| 10586 | case AArch64::UCVTFv4f32: |
| 10587 | case AArch64::UCVTFv8f16: |
| 10588 | case AArch64::UMAXVv16i8v: |
| 10589 | case AArch64::UMAXVv4i16v: |
| 10590 | case AArch64::UMAXVv4i32v: |
| 10591 | case AArch64::UMAXVv8i16v: |
| 10592 | case AArch64::UMAXVv8i8v: |
| 10593 | case AArch64::UMINVv16i8v: |
| 10594 | case AArch64::UMINVv4i16v: |
| 10595 | case AArch64::UMINVv4i32v: |
| 10596 | case AArch64::UMINVv8i16v: |
| 10597 | case AArch64::UMINVv8i8v: |
| 10598 | case AArch64::UMOVvi16_idx0: |
| 10599 | case AArch64::UMOVvi32_idx0: |
| 10600 | case AArch64::UMOVvi64_idx0: |
| 10601 | case AArch64::UMOVvi8_idx0: |
| 10602 | case AArch64::UQXTNv1i16: |
| 10603 | case AArch64::UQXTNv1i32: |
| 10604 | case AArch64::UQXTNv1i8: |
| 10605 | case AArch64::UQXTNv2i32: |
| 10606 | case AArch64::UQXTNv4i16: |
| 10607 | case AArch64::UQXTNv8i8: |
| 10608 | case AArch64::URECPEv2i32: |
| 10609 | case AArch64::URECPEv4i32: |
| 10610 | case AArch64::URSQRTEv2i32: |
| 10611 | case AArch64::URSQRTEv4i32: |
| 10612 | case AArch64::XTNv2i32: |
| 10613 | case AArch64::XTNv4i16: |
| 10614 | case AArch64::XTNv8i8: { |
| 10615 | // op: Rd |
| 10616 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 10617 | Value |= (op & 0x1f); |
| 10618 | // op: Rn |
| 10619 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 10620 | Value |= (op & 0x1f) << 5; |
| 10621 | break; |
| 10622 | } |
| 10623 | case AArch64::ADCSWr: |
| 10624 | case AArch64::ADCSXr: |
| 10625 | case AArch64::ADCWr: |
| 10626 | case AArch64::ADCXr: |
| 10627 | case AArch64::ADDHNv2i64_v2i32: |
| 10628 | case AArch64::ADDHNv4i32_v4i16: |
| 10629 | case AArch64::ADDHNv8i16_v8i8: |
| 10630 | case AArch64::ADDPv16i8: |
| 10631 | case AArch64::ADDPv2i32: |
| 10632 | case AArch64::ADDPv2i64: |
| 10633 | case AArch64::ADDPv4i16: |
| 10634 | case AArch64::ADDPv4i32: |
| 10635 | case AArch64::ADDPv8i16: |
| 10636 | case AArch64::ADDPv8i8: |
| 10637 | case AArch64::ADDv16i8: |
| 10638 | case AArch64::ADDv1i64: |
| 10639 | case AArch64::ADDv2i32: |
| 10640 | case AArch64::ADDv2i64: |
| 10641 | case AArch64::ADDv4i16: |
| 10642 | case AArch64::ADDv4i32: |
| 10643 | case AArch64::ADDv8i16: |
| 10644 | case AArch64::ADDv8i8: |
| 10645 | case AArch64::ANDv16i8: |
| 10646 | case AArch64::ANDv8i8: |
| 10647 | case AArch64::ASRVWr: |
| 10648 | case AArch64::ASRVXr: |
| 10649 | case AArch64::BICv16i8: |
| 10650 | case AArch64::BICv8i8: |
| 10651 | case AArch64::CMEQv16i8: |
| 10652 | case AArch64::CMEQv1i64: |
| 10653 | case AArch64::CMEQv2i32: |
| 10654 | case AArch64::CMEQv2i64: |
| 10655 | case AArch64::CMEQv4i16: |
| 10656 | case AArch64::CMEQv4i32: |
| 10657 | case AArch64::CMEQv8i16: |
| 10658 | case AArch64::CMEQv8i8: |
| 10659 | case AArch64::CMGEv16i8: |
| 10660 | case AArch64::CMGEv1i64: |
| 10661 | case AArch64::CMGEv2i32: |
| 10662 | case AArch64::CMGEv2i64: |
| 10663 | case AArch64::CMGEv4i16: |
| 10664 | case AArch64::CMGEv4i32: |
| 10665 | case AArch64::CMGEv8i16: |
| 10666 | case AArch64::CMGEv8i8: |
| 10667 | case AArch64::CMGTv16i8: |
| 10668 | case AArch64::CMGTv1i64: |
| 10669 | case AArch64::CMGTv2i32: |
| 10670 | case AArch64::CMGTv2i64: |
| 10671 | case AArch64::CMGTv4i16: |
| 10672 | case AArch64::CMGTv4i32: |
| 10673 | case AArch64::CMGTv8i16: |
| 10674 | case AArch64::CMGTv8i8: |
| 10675 | case AArch64::CMHIv16i8: |
| 10676 | case AArch64::CMHIv1i64: |
| 10677 | case AArch64::CMHIv2i32: |
| 10678 | case AArch64::CMHIv2i64: |
| 10679 | case AArch64::CMHIv4i16: |
| 10680 | case AArch64::CMHIv4i32: |
| 10681 | case AArch64::CMHIv8i16: |
| 10682 | case AArch64::CMHIv8i8: |
| 10683 | case AArch64::CMHSv16i8: |
| 10684 | case AArch64::CMHSv1i64: |
| 10685 | case AArch64::CMHSv2i32: |
| 10686 | case AArch64::CMHSv2i64: |
| 10687 | case AArch64::CMHSv4i16: |
| 10688 | case AArch64::CMHSv4i32: |
| 10689 | case AArch64::CMHSv8i16: |
| 10690 | case AArch64::CMHSv8i8: |
| 10691 | case AArch64::CMTSTv16i8: |
| 10692 | case AArch64::CMTSTv1i64: |
| 10693 | case AArch64::CMTSTv2i32: |
| 10694 | case AArch64::CMTSTv2i64: |
| 10695 | case AArch64::CMTSTv4i16: |
| 10696 | case AArch64::CMTSTv4i32: |
| 10697 | case AArch64::CMTSTv8i16: |
| 10698 | case AArch64::CMTSTv8i8: |
| 10699 | case AArch64::CRC32Brr: |
| 10700 | case AArch64::CRC32CBrr: |
| 10701 | case AArch64::CRC32CHrr: |
| 10702 | case AArch64::CRC32CWrr: |
| 10703 | case AArch64::CRC32CXrr: |
| 10704 | case AArch64::CRC32Hrr: |
| 10705 | case AArch64::CRC32Wrr: |
| 10706 | case AArch64::CRC32Xrr: |
| 10707 | case AArch64::EORv16i8: |
| 10708 | case AArch64::EORv8i8: |
| 10709 | case AArch64::FABD16: |
| 10710 | case AArch64::FABD32: |
| 10711 | case AArch64::FABD64: |
| 10712 | case AArch64::FABDv2f32: |
| 10713 | case AArch64::FABDv2f64: |
| 10714 | case AArch64::FABDv4f16: |
| 10715 | case AArch64::FABDv4f32: |
| 10716 | case AArch64::FABDv8f16: |
| 10717 | case AArch64::FACGE16: |
| 10718 | case AArch64::FACGE32: |
| 10719 | case AArch64::FACGE64: |
| 10720 | case AArch64::FACGEv2f32: |
| 10721 | case AArch64::FACGEv2f64: |
| 10722 | case AArch64::FACGEv4f16: |
| 10723 | case AArch64::FACGEv4f32: |
| 10724 | case AArch64::FACGEv8f16: |
| 10725 | case AArch64::FACGT16: |
| 10726 | case AArch64::FACGT32: |
| 10727 | case AArch64::FACGT64: |
| 10728 | case AArch64::FACGTv2f32: |
| 10729 | case AArch64::FACGTv2f64: |
| 10730 | case AArch64::FACGTv4f16: |
| 10731 | case AArch64::FACGTv4f32: |
| 10732 | case AArch64::FACGTv8f16: |
| 10733 | case AArch64::FADDDrr: |
| 10734 | case AArch64::FADDHrr: |
| 10735 | case AArch64::FADDPv2f32: |
| 10736 | case AArch64::FADDPv2f64: |
| 10737 | case AArch64::FADDPv4f16: |
| 10738 | case AArch64::FADDPv4f32: |
| 10739 | case AArch64::FADDPv8f16: |
| 10740 | case AArch64::FADDSrr: |
| 10741 | case AArch64::FADDv2f32: |
| 10742 | case AArch64::FADDv2f64: |
| 10743 | case AArch64::FADDv4f16: |
| 10744 | case AArch64::FADDv4f32: |
| 10745 | case AArch64::FADDv8f16: |
| 10746 | case AArch64::FAMAXv2f32: |
| 10747 | case AArch64::FAMAXv2f64: |
| 10748 | case AArch64::FAMAXv4f16: |
| 10749 | case AArch64::FAMAXv4f32: |
| 10750 | case AArch64::FAMAXv8f16: |
| 10751 | case AArch64::FAMINv2f32: |
| 10752 | case AArch64::FAMINv2f64: |
| 10753 | case AArch64::FAMINv4f16: |
| 10754 | case AArch64::FAMINv4f32: |
| 10755 | case AArch64::FAMINv8f16: |
| 10756 | case AArch64::FCMEQ16: |
| 10757 | case AArch64::FCMEQ32: |
| 10758 | case AArch64::FCMEQ64: |
| 10759 | case AArch64::FCMEQv2f32: |
| 10760 | case AArch64::FCMEQv2f64: |
| 10761 | case AArch64::FCMEQv4f16: |
| 10762 | case AArch64::FCMEQv4f32: |
| 10763 | case AArch64::FCMEQv8f16: |
| 10764 | case AArch64::FCMGE16: |
| 10765 | case AArch64::FCMGE32: |
| 10766 | case AArch64::FCMGE64: |
| 10767 | case AArch64::FCMGEv2f32: |
| 10768 | case AArch64::FCMGEv2f64: |
| 10769 | case AArch64::FCMGEv4f16: |
| 10770 | case AArch64::FCMGEv4f32: |
| 10771 | case AArch64::FCMGEv8f16: |
| 10772 | case AArch64::FCMGT16: |
| 10773 | case AArch64::FCMGT32: |
| 10774 | case AArch64::FCMGT64: |
| 10775 | case AArch64::FCMGTv2f32: |
| 10776 | case AArch64::FCMGTv2f64: |
| 10777 | case AArch64::FCMGTv4f16: |
| 10778 | case AArch64::FCMGTv4f32: |
| 10779 | case AArch64::FCMGTv8f16: |
| 10780 | case AArch64::FCVTN_F16v16f8: |
| 10781 | case AArch64::FCVTN_F16v8f8: |
| 10782 | case AArch64::FCVTN_F32v8f8: |
| 10783 | case AArch64::FDIVDrr: |
| 10784 | case AArch64::FDIVHrr: |
| 10785 | case AArch64::FDIVSrr: |
| 10786 | case AArch64::FDIVv2f32: |
| 10787 | case AArch64::FDIVv2f64: |
| 10788 | case AArch64::FDIVv4f16: |
| 10789 | case AArch64::FDIVv4f32: |
| 10790 | case AArch64::FDIVv8f16: |
| 10791 | case AArch64::FMAXDrr: |
| 10792 | case AArch64::FMAXHrr: |
| 10793 | case AArch64::FMAXNMDrr: |
| 10794 | case AArch64::FMAXNMHrr: |
| 10795 | case AArch64::FMAXNMPv2f32: |
| 10796 | case AArch64::FMAXNMPv2f64: |
| 10797 | case AArch64::FMAXNMPv4f16: |
| 10798 | case AArch64::FMAXNMPv4f32: |
| 10799 | case AArch64::FMAXNMPv8f16: |
| 10800 | case AArch64::FMAXNMSrr: |
| 10801 | case AArch64::FMAXNMv2f32: |
| 10802 | case AArch64::FMAXNMv2f64: |
| 10803 | case AArch64::FMAXNMv4f16: |
| 10804 | case AArch64::FMAXNMv4f32: |
| 10805 | case AArch64::FMAXNMv8f16: |
| 10806 | case AArch64::FMAXPv2f32: |
| 10807 | case AArch64::FMAXPv2f64: |
| 10808 | case AArch64::FMAXPv4f16: |
| 10809 | case AArch64::FMAXPv4f32: |
| 10810 | case AArch64::FMAXPv8f16: |
| 10811 | case AArch64::FMAXSrr: |
| 10812 | case AArch64::FMAXv2f32: |
| 10813 | case AArch64::FMAXv2f64: |
| 10814 | case AArch64::FMAXv4f16: |
| 10815 | case AArch64::FMAXv4f32: |
| 10816 | case AArch64::FMAXv8f16: |
| 10817 | case AArch64::FMINDrr: |
| 10818 | case AArch64::FMINHrr: |
| 10819 | case AArch64::FMINNMDrr: |
| 10820 | case AArch64::FMINNMHrr: |
| 10821 | case AArch64::FMINNMPv2f32: |
| 10822 | case AArch64::FMINNMPv2f64: |
| 10823 | case AArch64::FMINNMPv4f16: |
| 10824 | case AArch64::FMINNMPv4f32: |
| 10825 | case AArch64::FMINNMPv8f16: |
| 10826 | case AArch64::FMINNMSrr: |
| 10827 | case AArch64::FMINNMv2f32: |
| 10828 | case AArch64::FMINNMv2f64: |
| 10829 | case AArch64::FMINNMv4f16: |
| 10830 | case AArch64::FMINNMv4f32: |
| 10831 | case AArch64::FMINNMv8f16: |
| 10832 | case AArch64::FMINPv2f32: |
| 10833 | case AArch64::FMINPv2f64: |
| 10834 | case AArch64::FMINPv4f16: |
| 10835 | case AArch64::FMINPv4f32: |
| 10836 | case AArch64::FMINPv8f16: |
| 10837 | case AArch64::FMINSrr: |
| 10838 | case AArch64::FMINv2f32: |
| 10839 | case AArch64::FMINv2f64: |
| 10840 | case AArch64::FMINv4f16: |
| 10841 | case AArch64::FMINv4f32: |
| 10842 | case AArch64::FMINv8f16: |
| 10843 | case AArch64::FMULDrr: |
| 10844 | case AArch64::FMULHrr: |
| 10845 | case AArch64::FMULSrr: |
| 10846 | case AArch64::FMULX16: |
| 10847 | case AArch64::FMULX32: |
| 10848 | case AArch64::FMULX64: |
| 10849 | case AArch64::FMULXv2f32: |
| 10850 | case AArch64::FMULXv2f64: |
| 10851 | case AArch64::FMULXv4f16: |
| 10852 | case AArch64::FMULXv4f32: |
| 10853 | case AArch64::FMULXv8f16: |
| 10854 | case AArch64::FMULv2f32: |
| 10855 | case AArch64::FMULv2f64: |
| 10856 | case AArch64::FMULv4f16: |
| 10857 | case AArch64::FMULv4f32: |
| 10858 | case AArch64::FMULv8f16: |
| 10859 | case AArch64::FNMULDrr: |
| 10860 | case AArch64::FNMULHrr: |
| 10861 | case AArch64::FNMULSrr: |
| 10862 | case AArch64::FRECPS16: |
| 10863 | case AArch64::FRECPS32: |
| 10864 | case AArch64::FRECPS64: |
| 10865 | case AArch64::FRECPSv2f32: |
| 10866 | case AArch64::FRECPSv2f64: |
| 10867 | case AArch64::FRECPSv4f16: |
| 10868 | case AArch64::FRECPSv4f32: |
| 10869 | case AArch64::FRECPSv8f16: |
| 10870 | case AArch64::FRSQRTS16: |
| 10871 | case AArch64::FRSQRTS32: |
| 10872 | case AArch64::FRSQRTS64: |
| 10873 | case AArch64::FRSQRTSv2f32: |
| 10874 | case AArch64::FRSQRTSv2f64: |
| 10875 | case AArch64::FRSQRTSv4f16: |
| 10876 | case AArch64::FRSQRTSv4f32: |
| 10877 | case AArch64::FRSQRTSv8f16: |
| 10878 | case AArch64::FSCALEv2f32: |
| 10879 | case AArch64::FSCALEv2f64: |
| 10880 | case AArch64::FSCALEv4f16: |
| 10881 | case AArch64::FSCALEv4f32: |
| 10882 | case AArch64::FSCALEv8f16: |
| 10883 | case AArch64::FSUBDrr: |
| 10884 | case AArch64::FSUBHrr: |
| 10885 | case AArch64::FSUBSrr: |
| 10886 | case AArch64::FSUBv2f32: |
| 10887 | case AArch64::FSUBv2f64: |
| 10888 | case AArch64::FSUBv4f16: |
| 10889 | case AArch64::FSUBv4f32: |
| 10890 | case AArch64::FSUBv8f16: |
| 10891 | case AArch64::GMI: |
| 10892 | case AArch64::IRG: |
| 10893 | case AArch64::LSLVWr: |
| 10894 | case AArch64::LSLVXr: |
| 10895 | case AArch64::LSRVWr: |
| 10896 | case AArch64::LSRVXr: |
| 10897 | case AArch64::MULv16i8: |
| 10898 | case AArch64::MULv2i32: |
| 10899 | case AArch64::MULv4i16: |
| 10900 | case AArch64::MULv4i32: |
| 10901 | case AArch64::MULv8i16: |
| 10902 | case AArch64::MULv8i8: |
| 10903 | case AArch64::ORNv16i8: |
| 10904 | case AArch64::ORNv8i8: |
| 10905 | case AArch64::ORRv16i8: |
| 10906 | case AArch64::ORRv8i8: |
| 10907 | case AArch64::PACGA: |
| 10908 | case AArch64::PMULLv16i8: |
| 10909 | case AArch64::PMULLv1i64: |
| 10910 | case AArch64::PMULLv2i64: |
| 10911 | case AArch64::PMULLv8i8: |
| 10912 | case AArch64::PMULv16i8: |
| 10913 | case AArch64::PMULv8i8: |
| 10914 | case AArch64::RADDHNv2i64_v2i32: |
| 10915 | case AArch64::RADDHNv4i32_v4i16: |
| 10916 | case AArch64::RADDHNv8i16_v8i8: |
| 10917 | case AArch64::RORVWr: |
| 10918 | case AArch64::RORVXr: |
| 10919 | case AArch64::RSUBHNv2i64_v2i32: |
| 10920 | case AArch64::RSUBHNv4i32_v4i16: |
| 10921 | case AArch64::RSUBHNv8i16_v8i8: |
| 10922 | case AArch64::SABDLv16i8_v8i16: |
| 10923 | case AArch64::SABDLv2i32_v2i64: |
| 10924 | case AArch64::SABDLv4i16_v4i32: |
| 10925 | case AArch64::SABDLv4i32_v2i64: |
| 10926 | case AArch64::SABDLv8i16_v4i32: |
| 10927 | case AArch64::SABDLv8i8_v8i16: |
| 10928 | case AArch64::SABDv16i8: |
| 10929 | case AArch64::SABDv2i32: |
| 10930 | case AArch64::SABDv4i16: |
| 10931 | case AArch64::SABDv4i32: |
| 10932 | case AArch64::SABDv8i16: |
| 10933 | case AArch64::SABDv8i8: |
| 10934 | case AArch64::SADDLv16i8_v8i16: |
| 10935 | case AArch64::SADDLv2i32_v2i64: |
| 10936 | case AArch64::SADDLv4i16_v4i32: |
| 10937 | case AArch64::SADDLv4i32_v2i64: |
| 10938 | case AArch64::SADDLv8i16_v4i32: |
| 10939 | case AArch64::SADDLv8i8_v8i16: |
| 10940 | case AArch64::SADDWv16i8_v8i16: |
| 10941 | case AArch64::SADDWv2i32_v2i64: |
| 10942 | case AArch64::SADDWv4i16_v4i32: |
| 10943 | case AArch64::SADDWv4i32_v2i64: |
| 10944 | case AArch64::SADDWv8i16_v4i32: |
| 10945 | case AArch64::SADDWv8i8_v8i16: |
| 10946 | case AArch64::SBCSWr: |
| 10947 | case AArch64::SBCSXr: |
| 10948 | case AArch64::SBCWr: |
| 10949 | case AArch64::SBCXr: |
| 10950 | case AArch64::SDIVWr: |
| 10951 | case AArch64::SDIVXr: |
| 10952 | case AArch64::SHADDv16i8: |
| 10953 | case AArch64::SHADDv2i32: |
| 10954 | case AArch64::SHADDv4i16: |
| 10955 | case AArch64::SHADDv4i32: |
| 10956 | case AArch64::SHADDv8i16: |
| 10957 | case AArch64::SHADDv8i8: |
| 10958 | case AArch64::SHSUBv16i8: |
| 10959 | case AArch64::SHSUBv2i32: |
| 10960 | case AArch64::SHSUBv4i16: |
| 10961 | case AArch64::SHSUBv4i32: |
| 10962 | case AArch64::SHSUBv8i16: |
| 10963 | case AArch64::SHSUBv8i8: |
| 10964 | case AArch64::SMAXPv16i8: |
| 10965 | case AArch64::SMAXPv2i32: |
| 10966 | case AArch64::SMAXPv4i16: |
| 10967 | case AArch64::SMAXPv4i32: |
| 10968 | case AArch64::SMAXPv8i16: |
| 10969 | case AArch64::SMAXPv8i8: |
| 10970 | case AArch64::SMAXWrr: |
| 10971 | case AArch64::SMAXXrr: |
| 10972 | case AArch64::SMAXv16i8: |
| 10973 | case AArch64::SMAXv2i32: |
| 10974 | case AArch64::SMAXv4i16: |
| 10975 | case AArch64::SMAXv4i32: |
| 10976 | case AArch64::SMAXv8i16: |
| 10977 | case AArch64::SMAXv8i8: |
| 10978 | case AArch64::SMINPv16i8: |
| 10979 | case AArch64::SMINPv2i32: |
| 10980 | case AArch64::SMINPv4i16: |
| 10981 | case AArch64::SMINPv4i32: |
| 10982 | case AArch64::SMINPv8i16: |
| 10983 | case AArch64::SMINPv8i8: |
| 10984 | case AArch64::SMINWrr: |
| 10985 | case AArch64::SMINXrr: |
| 10986 | case AArch64::SMINv16i8: |
| 10987 | case AArch64::SMINv2i32: |
| 10988 | case AArch64::SMINv4i16: |
| 10989 | case AArch64::SMINv4i32: |
| 10990 | case AArch64::SMINv8i16: |
| 10991 | case AArch64::SMINv8i8: |
| 10992 | case AArch64::SMULLv16i8_v8i16: |
| 10993 | case AArch64::SMULLv2i32_v2i64: |
| 10994 | case AArch64::SMULLv4i16_v4i32: |
| 10995 | case AArch64::SMULLv4i32_v2i64: |
| 10996 | case AArch64::SMULLv8i16_v4i32: |
| 10997 | case AArch64::SMULLv8i8_v8i16: |
| 10998 | case AArch64::SQADDv16i8: |
| 10999 | case AArch64::SQADDv1i16: |
| 11000 | case AArch64::SQADDv1i32: |
| 11001 | case AArch64::SQADDv1i64: |
| 11002 | case AArch64::SQADDv1i8: |
| 11003 | case AArch64::SQADDv2i32: |
| 11004 | case AArch64::SQADDv2i64: |
| 11005 | case AArch64::SQADDv4i16: |
| 11006 | case AArch64::SQADDv4i32: |
| 11007 | case AArch64::SQADDv8i16: |
| 11008 | case AArch64::SQADDv8i8: |
| 11009 | case AArch64::SQDMULHv1i16: |
| 11010 | case AArch64::SQDMULHv1i32: |
| 11011 | case AArch64::SQDMULHv2i32: |
| 11012 | case AArch64::SQDMULHv4i16: |
| 11013 | case AArch64::SQDMULHv4i32: |
| 11014 | case AArch64::SQDMULHv8i16: |
| 11015 | case AArch64::SQDMULLi16: |
| 11016 | case AArch64::SQDMULLi32: |
| 11017 | case AArch64::SQDMULLv2i32_v2i64: |
| 11018 | case AArch64::SQDMULLv4i16_v4i32: |
| 11019 | case AArch64::SQDMULLv4i32_v2i64: |
| 11020 | case AArch64::SQDMULLv8i16_v4i32: |
| 11021 | case AArch64::SQRDMULHv1i16: |
| 11022 | case AArch64::SQRDMULHv1i32: |
| 11023 | case AArch64::SQRDMULHv2i32: |
| 11024 | case AArch64::SQRDMULHv4i16: |
| 11025 | case AArch64::SQRDMULHv4i32: |
| 11026 | case AArch64::SQRDMULHv8i16: |
| 11027 | case AArch64::SQRSHLv16i8: |
| 11028 | case AArch64::SQRSHLv1i16: |
| 11029 | case AArch64::SQRSHLv1i32: |
| 11030 | case AArch64::SQRSHLv1i64: |
| 11031 | case AArch64::SQRSHLv1i8: |
| 11032 | case AArch64::SQRSHLv2i32: |
| 11033 | case AArch64::SQRSHLv2i64: |
| 11034 | case AArch64::SQRSHLv4i16: |
| 11035 | case AArch64::SQRSHLv4i32: |
| 11036 | case AArch64::SQRSHLv8i16: |
| 11037 | case AArch64::SQRSHLv8i8: |
| 11038 | case AArch64::SQSHLv16i8: |
| 11039 | case AArch64::SQSHLv1i16: |
| 11040 | case AArch64::SQSHLv1i32: |
| 11041 | case AArch64::SQSHLv1i64: |
| 11042 | case AArch64::SQSHLv1i8: |
| 11043 | case AArch64::SQSHLv2i32: |
| 11044 | case AArch64::SQSHLv2i64: |
| 11045 | case AArch64::SQSHLv4i16: |
| 11046 | case AArch64::SQSHLv4i32: |
| 11047 | case AArch64::SQSHLv8i16: |
| 11048 | case AArch64::SQSHLv8i8: |
| 11049 | case AArch64::SQSUBv16i8: |
| 11050 | case AArch64::SQSUBv1i16: |
| 11051 | case AArch64::SQSUBv1i32: |
| 11052 | case AArch64::SQSUBv1i64: |
| 11053 | case AArch64::SQSUBv1i8: |
| 11054 | case AArch64::SQSUBv2i32: |
| 11055 | case AArch64::SQSUBv2i64: |
| 11056 | case AArch64::SQSUBv4i16: |
| 11057 | case AArch64::SQSUBv4i32: |
| 11058 | case AArch64::SQSUBv8i16: |
| 11059 | case AArch64::SQSUBv8i8: |
| 11060 | case AArch64::SRHADDv16i8: |
| 11061 | case AArch64::SRHADDv2i32: |
| 11062 | case AArch64::SRHADDv4i16: |
| 11063 | case AArch64::SRHADDv4i32: |
| 11064 | case AArch64::SRHADDv8i16: |
| 11065 | case AArch64::SRHADDv8i8: |
| 11066 | case AArch64::SRSHLv16i8: |
| 11067 | case AArch64::SRSHLv1i64: |
| 11068 | case AArch64::SRSHLv2i32: |
| 11069 | case AArch64::SRSHLv2i64: |
| 11070 | case AArch64::SRSHLv4i16: |
| 11071 | case AArch64::SRSHLv4i32: |
| 11072 | case AArch64::SRSHLv8i16: |
| 11073 | case AArch64::SRSHLv8i8: |
| 11074 | case AArch64::SSHLv16i8: |
| 11075 | case AArch64::SSHLv1i64: |
| 11076 | case AArch64::SSHLv2i32: |
| 11077 | case AArch64::SSHLv2i64: |
| 11078 | case AArch64::SSHLv4i16: |
| 11079 | case AArch64::SSHLv4i32: |
| 11080 | case AArch64::SSHLv8i16: |
| 11081 | case AArch64::SSHLv8i8: |
| 11082 | case AArch64::SSUBLv16i8_v8i16: |
| 11083 | case AArch64::SSUBLv2i32_v2i64: |
| 11084 | case AArch64::SSUBLv4i16_v4i32: |
| 11085 | case AArch64::SSUBLv4i32_v2i64: |
| 11086 | case AArch64::SSUBLv8i16_v4i32: |
| 11087 | case AArch64::SSUBLv8i8_v8i16: |
| 11088 | case AArch64::SSUBWv16i8_v8i16: |
| 11089 | case AArch64::SSUBWv2i32_v2i64: |
| 11090 | case AArch64::SSUBWv4i16_v4i32: |
| 11091 | case AArch64::SSUBWv4i32_v2i64: |
| 11092 | case AArch64::SSUBWv8i16_v4i32: |
| 11093 | case AArch64::SSUBWv8i8_v8i16: |
| 11094 | case AArch64::SUBHNv2i64_v2i32: |
| 11095 | case AArch64::SUBHNv4i32_v4i16: |
| 11096 | case AArch64::SUBHNv8i16_v8i8: |
| 11097 | case AArch64::SUBP: |
| 11098 | case AArch64::SUBPS: |
| 11099 | case AArch64::SUBv16i8: |
| 11100 | case AArch64::SUBv1i64: |
| 11101 | case AArch64::SUBv2i32: |
| 11102 | case AArch64::SUBv2i64: |
| 11103 | case AArch64::SUBv4i16: |
| 11104 | case AArch64::SUBv4i32: |
| 11105 | case AArch64::SUBv8i16: |
| 11106 | case AArch64::SUBv8i8: |
| 11107 | case AArch64::TRN1v16i8: |
| 11108 | case AArch64::TRN1v2i32: |
| 11109 | case AArch64::TRN1v2i64: |
| 11110 | case AArch64::TRN1v4i16: |
| 11111 | case AArch64::TRN1v4i32: |
| 11112 | case AArch64::TRN1v8i16: |
| 11113 | case AArch64::TRN1v8i8: |
| 11114 | case AArch64::TRN2v16i8: |
| 11115 | case AArch64::TRN2v2i32: |
| 11116 | case AArch64::TRN2v2i64: |
| 11117 | case AArch64::TRN2v4i16: |
| 11118 | case AArch64::TRN2v4i32: |
| 11119 | case AArch64::TRN2v8i16: |
| 11120 | case AArch64::TRN2v8i8: |
| 11121 | case AArch64::UABDLv16i8_v8i16: |
| 11122 | case AArch64::UABDLv2i32_v2i64: |
| 11123 | case AArch64::UABDLv4i16_v4i32: |
| 11124 | case AArch64::UABDLv4i32_v2i64: |
| 11125 | case AArch64::UABDLv8i16_v4i32: |
| 11126 | case AArch64::UABDLv8i8_v8i16: |
| 11127 | case AArch64::UABDv16i8: |
| 11128 | case AArch64::UABDv2i32: |
| 11129 | case AArch64::UABDv4i16: |
| 11130 | case AArch64::UABDv4i32: |
| 11131 | case AArch64::UABDv8i16: |
| 11132 | case AArch64::UABDv8i8: |
| 11133 | case AArch64::UADDLv16i8_v8i16: |
| 11134 | case AArch64::UADDLv2i32_v2i64: |
| 11135 | case AArch64::UADDLv4i16_v4i32: |
| 11136 | case AArch64::UADDLv4i32_v2i64: |
| 11137 | case AArch64::UADDLv8i16_v4i32: |
| 11138 | case AArch64::UADDLv8i8_v8i16: |
| 11139 | case AArch64::UADDWv16i8_v8i16: |
| 11140 | case AArch64::UADDWv2i32_v2i64: |
| 11141 | case AArch64::UADDWv4i16_v4i32: |
| 11142 | case AArch64::UADDWv4i32_v2i64: |
| 11143 | case AArch64::UADDWv8i16_v4i32: |
| 11144 | case AArch64::UADDWv8i8_v8i16: |
| 11145 | case AArch64::UDIVWr: |
| 11146 | case AArch64::UDIVXr: |
| 11147 | case AArch64::UHADDv16i8: |
| 11148 | case AArch64::UHADDv2i32: |
| 11149 | case AArch64::UHADDv4i16: |
| 11150 | case AArch64::UHADDv4i32: |
| 11151 | case AArch64::UHADDv8i16: |
| 11152 | case AArch64::UHADDv8i8: |
| 11153 | case AArch64::UHSUBv16i8: |
| 11154 | case AArch64::UHSUBv2i32: |
| 11155 | case AArch64::UHSUBv4i16: |
| 11156 | case AArch64::UHSUBv4i32: |
| 11157 | case AArch64::UHSUBv8i16: |
| 11158 | case AArch64::UHSUBv8i8: |
| 11159 | case AArch64::UMAXPv16i8: |
| 11160 | case AArch64::UMAXPv2i32: |
| 11161 | case AArch64::UMAXPv4i16: |
| 11162 | case AArch64::UMAXPv4i32: |
| 11163 | case AArch64::UMAXPv8i16: |
| 11164 | case AArch64::UMAXPv8i8: |
| 11165 | case AArch64::UMAXWrr: |
| 11166 | case AArch64::UMAXXrr: |
| 11167 | case AArch64::UMAXv16i8: |
| 11168 | case AArch64::UMAXv2i32: |
| 11169 | case AArch64::UMAXv4i16: |
| 11170 | case AArch64::UMAXv4i32: |
| 11171 | case AArch64::UMAXv8i16: |
| 11172 | case AArch64::UMAXv8i8: |
| 11173 | case AArch64::UMINPv16i8: |
| 11174 | case AArch64::UMINPv2i32: |
| 11175 | case AArch64::UMINPv4i16: |
| 11176 | case AArch64::UMINPv4i32: |
| 11177 | case AArch64::UMINPv8i16: |
| 11178 | case AArch64::UMINPv8i8: |
| 11179 | case AArch64::UMINWrr: |
| 11180 | case AArch64::UMINXrr: |
| 11181 | case AArch64::UMINv16i8: |
| 11182 | case AArch64::UMINv2i32: |
| 11183 | case AArch64::UMINv4i16: |
| 11184 | case AArch64::UMINv4i32: |
| 11185 | case AArch64::UMINv8i16: |
| 11186 | case AArch64::UMINv8i8: |
| 11187 | case AArch64::UMULLv16i8_v8i16: |
| 11188 | case AArch64::UMULLv2i32_v2i64: |
| 11189 | case AArch64::UMULLv4i16_v4i32: |
| 11190 | case AArch64::UMULLv4i32_v2i64: |
| 11191 | case AArch64::UMULLv8i16_v4i32: |
| 11192 | case AArch64::UMULLv8i8_v8i16: |
| 11193 | case AArch64::UQADDv16i8: |
| 11194 | case AArch64::UQADDv1i16: |
| 11195 | case AArch64::UQADDv1i32: |
| 11196 | case AArch64::UQADDv1i64: |
| 11197 | case AArch64::UQADDv1i8: |
| 11198 | case AArch64::UQADDv2i32: |
| 11199 | case AArch64::UQADDv2i64: |
| 11200 | case AArch64::UQADDv4i16: |
| 11201 | case AArch64::UQADDv4i32: |
| 11202 | case AArch64::UQADDv8i16: |
| 11203 | case AArch64::UQADDv8i8: |
| 11204 | case AArch64::UQRSHLv16i8: |
| 11205 | case AArch64::UQRSHLv1i16: |
| 11206 | case AArch64::UQRSHLv1i32: |
| 11207 | case AArch64::UQRSHLv1i64: |
| 11208 | case AArch64::UQRSHLv1i8: |
| 11209 | case AArch64::UQRSHLv2i32: |
| 11210 | case AArch64::UQRSHLv2i64: |
| 11211 | case AArch64::UQRSHLv4i16: |
| 11212 | case AArch64::UQRSHLv4i32: |
| 11213 | case AArch64::UQRSHLv8i16: |
| 11214 | case AArch64::UQRSHLv8i8: |
| 11215 | case AArch64::UQSHLv16i8: |
| 11216 | case AArch64::UQSHLv1i16: |
| 11217 | case AArch64::UQSHLv1i32: |
| 11218 | case AArch64::UQSHLv1i64: |
| 11219 | case AArch64::UQSHLv1i8: |
| 11220 | case AArch64::UQSHLv2i32: |
| 11221 | case AArch64::UQSHLv2i64: |
| 11222 | case AArch64::UQSHLv4i16: |
| 11223 | case AArch64::UQSHLv4i32: |
| 11224 | case AArch64::UQSHLv8i16: |
| 11225 | case AArch64::UQSHLv8i8: |
| 11226 | case AArch64::UQSUBv16i8: |
| 11227 | case AArch64::UQSUBv1i16: |
| 11228 | case AArch64::UQSUBv1i32: |
| 11229 | case AArch64::UQSUBv1i64: |
| 11230 | case AArch64::UQSUBv1i8: |
| 11231 | case AArch64::UQSUBv2i32: |
| 11232 | case AArch64::UQSUBv2i64: |
| 11233 | case AArch64::UQSUBv4i16: |
| 11234 | case AArch64::UQSUBv4i32: |
| 11235 | case AArch64::UQSUBv8i16: |
| 11236 | case AArch64::UQSUBv8i8: |
| 11237 | case AArch64::URHADDv16i8: |
| 11238 | case AArch64::URHADDv2i32: |
| 11239 | case AArch64::URHADDv4i16: |
| 11240 | case AArch64::URHADDv4i32: |
| 11241 | case AArch64::URHADDv8i16: |
| 11242 | case AArch64::URHADDv8i8: |
| 11243 | case AArch64::URSHLv16i8: |
| 11244 | case AArch64::URSHLv1i64: |
| 11245 | case AArch64::URSHLv2i32: |
| 11246 | case AArch64::URSHLv2i64: |
| 11247 | case AArch64::URSHLv4i16: |
| 11248 | case AArch64::URSHLv4i32: |
| 11249 | case AArch64::URSHLv8i16: |
| 11250 | case AArch64::URSHLv8i8: |
| 11251 | case AArch64::USHLv16i8: |
| 11252 | case AArch64::USHLv1i64: |
| 11253 | case AArch64::USHLv2i32: |
| 11254 | case AArch64::USHLv2i64: |
| 11255 | case AArch64::USHLv4i16: |
| 11256 | case AArch64::USHLv4i32: |
| 11257 | case AArch64::USHLv8i16: |
| 11258 | case AArch64::USHLv8i8: |
| 11259 | case AArch64::USUBLv16i8_v8i16: |
| 11260 | case AArch64::USUBLv2i32_v2i64: |
| 11261 | case AArch64::USUBLv4i16_v4i32: |
| 11262 | case AArch64::USUBLv4i32_v2i64: |
| 11263 | case AArch64::USUBLv8i16_v4i32: |
| 11264 | case AArch64::USUBLv8i8_v8i16: |
| 11265 | case AArch64::USUBWv16i8_v8i16: |
| 11266 | case AArch64::USUBWv2i32_v2i64: |
| 11267 | case AArch64::USUBWv4i16_v4i32: |
| 11268 | case AArch64::USUBWv4i32_v2i64: |
| 11269 | case AArch64::USUBWv8i16_v4i32: |
| 11270 | case AArch64::USUBWv8i8_v8i16: |
| 11271 | case AArch64::UZP1v16i8: |
| 11272 | case AArch64::UZP1v2i32: |
| 11273 | case AArch64::UZP1v2i64: |
| 11274 | case AArch64::UZP1v4i16: |
| 11275 | case AArch64::UZP1v4i32: |
| 11276 | case AArch64::UZP1v8i16: |
| 11277 | case AArch64::UZP1v8i8: |
| 11278 | case AArch64::UZP2v16i8: |
| 11279 | case AArch64::UZP2v2i32: |
| 11280 | case AArch64::UZP2v2i64: |
| 11281 | case AArch64::UZP2v4i16: |
| 11282 | case AArch64::UZP2v4i32: |
| 11283 | case AArch64::UZP2v8i16: |
| 11284 | case AArch64::UZP2v8i8: |
| 11285 | case AArch64::ZIP1v16i8: |
| 11286 | case AArch64::ZIP1v2i32: |
| 11287 | case AArch64::ZIP1v2i64: |
| 11288 | case AArch64::ZIP1v4i16: |
| 11289 | case AArch64::ZIP1v4i32: |
| 11290 | case AArch64::ZIP1v8i16: |
| 11291 | case AArch64::ZIP1v8i8: |
| 11292 | case AArch64::ZIP2v16i8: |
| 11293 | case AArch64::ZIP2v2i32: |
| 11294 | case AArch64::ZIP2v2i64: |
| 11295 | case AArch64::ZIP2v4i16: |
| 11296 | case AArch64::ZIP2v4i32: |
| 11297 | case AArch64::ZIP2v8i16: |
| 11298 | case AArch64::ZIP2v8i8: { |
| 11299 | // op: Rd |
| 11300 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11301 | Value |= (op & 0x1f); |
| 11302 | // op: Rn |
| 11303 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11304 | Value |= (op & 0x1f) << 5; |
| 11305 | // op: Rm |
| 11306 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11307 | Value |= (op & 0x1f) << 16; |
| 11308 | break; |
| 11309 | } |
| 11310 | case AArch64::FMADDDrrr: |
| 11311 | case AArch64::FMADDHrrr: |
| 11312 | case AArch64::FMADDSrrr: |
| 11313 | case AArch64::FMSUBDrrr: |
| 11314 | case AArch64::FMSUBHrrr: |
| 11315 | case AArch64::FMSUBSrrr: |
| 11316 | case AArch64::FNMADDDrrr: |
| 11317 | case AArch64::FNMADDHrrr: |
| 11318 | case AArch64::FNMADDSrrr: |
| 11319 | case AArch64::FNMSUBDrrr: |
| 11320 | case AArch64::FNMSUBHrrr: |
| 11321 | case AArch64::FNMSUBSrrr: |
| 11322 | case AArch64::MADDPT: |
| 11323 | case AArch64::MADDWrrr: |
| 11324 | case AArch64::MADDXrrr: |
| 11325 | case AArch64::MSUBPT: |
| 11326 | case AArch64::MSUBWrrr: |
| 11327 | case AArch64::MSUBXrrr: |
| 11328 | case AArch64::SMADDLrrr: |
| 11329 | case AArch64::SMSUBLrrr: |
| 11330 | case AArch64::UMADDLrrr: |
| 11331 | case AArch64::UMSUBLrrr: { |
| 11332 | // op: Rd |
| 11333 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11334 | Value |= (op & 0x1f); |
| 11335 | // op: Rn |
| 11336 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11337 | Value |= (op & 0x1f) << 5; |
| 11338 | // op: Rm |
| 11339 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11340 | Value |= (op & 0x1f) << 16; |
| 11341 | // op: Ra |
| 11342 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11343 | Value |= (op & 0x1f) << 10; |
| 11344 | break; |
| 11345 | } |
| 11346 | case AArch64::CSELWr: |
| 11347 | case AArch64::CSELXr: |
| 11348 | case AArch64::CSINCWr: |
| 11349 | case AArch64::CSINCXr: |
| 11350 | case AArch64::CSINVWr: |
| 11351 | case AArch64::CSINVXr: |
| 11352 | case AArch64::CSNEGWr: |
| 11353 | case AArch64::CSNEGXr: |
| 11354 | case AArch64::FCSELDrrr: |
| 11355 | case AArch64::FCSELHrrr: |
| 11356 | case AArch64::FCSELSrrr: { |
| 11357 | // op: Rd |
| 11358 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11359 | Value |= (op & 0x1f); |
| 11360 | // op: Rn |
| 11361 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11362 | Value |= (op & 0x1f) << 5; |
| 11363 | // op: Rm |
| 11364 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11365 | Value |= (op & 0x1f) << 16; |
| 11366 | // op: cond |
| 11367 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11368 | Value |= (op & 0xf) << 12; |
| 11369 | break; |
| 11370 | } |
| 11371 | case AArch64::ADDSXrx64: |
| 11372 | case AArch64::ADDXrx64: |
| 11373 | case AArch64::SUBSXrx64: |
| 11374 | case AArch64::SUBXrx64: { |
| 11375 | // op: Rd |
| 11376 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11377 | Value |= (op & 0x1f); |
| 11378 | // op: Rn |
| 11379 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11380 | Value |= (op & 0x1f) << 5; |
| 11381 | // op: Rm |
| 11382 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11383 | Value |= (op & 0x1f) << 16; |
| 11384 | // op: ext |
| 11385 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11386 | Value |= (op & 0x20) << 10; |
| 11387 | Value |= (op & 0x7) << 10; |
| 11388 | break; |
| 11389 | } |
| 11390 | case AArch64::ADDSWrx: |
| 11391 | case AArch64::ADDSXrx: |
| 11392 | case AArch64::ADDWrx: |
| 11393 | case AArch64::ADDXrx: |
| 11394 | case AArch64::SUBSWrx: |
| 11395 | case AArch64::SUBSXrx: |
| 11396 | case AArch64::SUBWrx: |
| 11397 | case AArch64::SUBXrx: { |
| 11398 | // op: Rd |
| 11399 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11400 | Value |= (op & 0x1f); |
| 11401 | // op: Rn |
| 11402 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11403 | Value |= (op & 0x1f) << 5; |
| 11404 | // op: Rm |
| 11405 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11406 | Value |= (op & 0x1f) << 16; |
| 11407 | // op: extend |
| 11408 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11409 | Value |= (op & 0x3f) << 10; |
| 11410 | break; |
| 11411 | } |
| 11412 | case AArch64::FMULXv1i64_indexed: |
| 11413 | case AArch64::FMULXv2i64_indexed: |
| 11414 | case AArch64::FMULv1i64_indexed: |
| 11415 | case AArch64::FMULv2i64_indexed: { |
| 11416 | // op: Rd |
| 11417 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11418 | Value |= (op & 0x1f); |
| 11419 | // op: Rn |
| 11420 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11421 | Value |= (op & 0x1f) << 5; |
| 11422 | // op: Rm |
| 11423 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11424 | Value |= (op & 0x1f) << 16; |
| 11425 | // op: idx |
| 11426 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11427 | Value |= (op & 0x1) << 11; |
| 11428 | break; |
| 11429 | } |
| 11430 | case AArch64::LUT4_B: { |
| 11431 | // op: Rd |
| 11432 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11433 | Value |= (op & 0x1f); |
| 11434 | // op: Rn |
| 11435 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11436 | Value |= (op & 0x1f) << 5; |
| 11437 | // op: Rm |
| 11438 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11439 | Value |= (op & 0x1f) << 16; |
| 11440 | // op: idx |
| 11441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11442 | Value |= (op & 0x1) << 14; |
| 11443 | break; |
| 11444 | } |
| 11445 | case AArch64::FMULXv1i32_indexed: |
| 11446 | case AArch64::FMULXv2i32_indexed: |
| 11447 | case AArch64::FMULXv4i32_indexed: |
| 11448 | case AArch64::FMULv1i32_indexed: |
| 11449 | case AArch64::FMULv2i32_indexed: |
| 11450 | case AArch64::FMULv4i32_indexed: |
| 11451 | case AArch64::MULv2i32_indexed: |
| 11452 | case AArch64::MULv4i32_indexed: |
| 11453 | case AArch64::SMULLv2i32_indexed: |
| 11454 | case AArch64::SMULLv4i32_indexed: |
| 11455 | case AArch64::SQDMULHv1i32_indexed: |
| 11456 | case AArch64::SQDMULHv2i32_indexed: |
| 11457 | case AArch64::SQDMULHv4i32_indexed: |
| 11458 | case AArch64::SQDMULLv1i64_indexed: |
| 11459 | case AArch64::SQDMULLv2i32_indexed: |
| 11460 | case AArch64::SQDMULLv4i32_indexed: |
| 11461 | case AArch64::SQRDMULHv1i32_indexed: |
| 11462 | case AArch64::SQRDMULHv2i32_indexed: |
| 11463 | case AArch64::SQRDMULHv4i32_indexed: |
| 11464 | case AArch64::UMULLv2i32_indexed: |
| 11465 | case AArch64::UMULLv4i32_indexed: { |
| 11466 | // op: Rd |
| 11467 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11468 | Value |= (op & 0x1f); |
| 11469 | // op: Rn |
| 11470 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11471 | Value |= (op & 0x1f) << 5; |
| 11472 | // op: Rm |
| 11473 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11474 | Value |= (op & 0x1f) << 16; |
| 11475 | // op: idx |
| 11476 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11477 | Value |= (op & 0x1) << 21; |
| 11478 | Value |= (op & 0x2) << 10; |
| 11479 | break; |
| 11480 | } |
| 11481 | case AArch64::LUT2_B: |
| 11482 | case AArch64::LUT4_H: { |
| 11483 | // op: Rd |
| 11484 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11485 | Value |= (op & 0x1f); |
| 11486 | // op: Rn |
| 11487 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11488 | Value |= (op & 0x1f) << 5; |
| 11489 | // op: Rm |
| 11490 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11491 | Value |= (op & 0x1f) << 16; |
| 11492 | // op: idx |
| 11493 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11494 | Value |= (op & 0x3) << 13; |
| 11495 | break; |
| 11496 | } |
| 11497 | case AArch64::LUT2_H: { |
| 11498 | // op: Rd |
| 11499 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11500 | Value |= (op & 0x1f); |
| 11501 | // op: Rn |
| 11502 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11503 | Value |= (op & 0x1f) << 5; |
| 11504 | // op: Rm |
| 11505 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11506 | Value |= (op & 0x1f) << 16; |
| 11507 | // op: idx |
| 11508 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11509 | Value |= (op & 0x7) << 12; |
| 11510 | break; |
| 11511 | } |
| 11512 | case AArch64::EXTRWrri: { |
| 11513 | // op: Rd |
| 11514 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11515 | Value |= (op & 0x1f); |
| 11516 | // op: Rn |
| 11517 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11518 | Value |= (op & 0x1f) << 5; |
| 11519 | // op: Rm |
| 11520 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11521 | Value |= (op & 0x1f) << 16; |
| 11522 | // op: imm |
| 11523 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11524 | Value |= (op & 0x1f) << 10; |
| 11525 | break; |
| 11526 | } |
| 11527 | case AArch64::EXTRXrri: { |
| 11528 | // op: Rd |
| 11529 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11530 | Value |= (op & 0x1f); |
| 11531 | // op: Rn |
| 11532 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11533 | Value |= (op & 0x1f) << 5; |
| 11534 | // op: Rm |
| 11535 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11536 | Value |= (op & 0x1f) << 16; |
| 11537 | // op: imm |
| 11538 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11539 | Value |= (op & 0x3f) << 10; |
| 11540 | break; |
| 11541 | } |
| 11542 | case AArch64::EXTv8i8: { |
| 11543 | // op: Rd |
| 11544 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11545 | Value |= (op & 0x1f); |
| 11546 | // op: Rn |
| 11547 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11548 | Value |= (op & 0x1f) << 5; |
| 11549 | // op: Rm |
| 11550 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11551 | Value |= (op & 0x1f) << 16; |
| 11552 | // op: imm |
| 11553 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11554 | Value |= (op & 0x7) << 11; |
| 11555 | break; |
| 11556 | } |
| 11557 | case AArch64::EXTv16i8: { |
| 11558 | // op: Rd |
| 11559 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11560 | Value |= (op & 0x1f); |
| 11561 | // op: Rn |
| 11562 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11563 | Value |= (op & 0x1f) << 5; |
| 11564 | // op: Rm |
| 11565 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11566 | Value |= (op & 0x1f) << 16; |
| 11567 | // op: imm |
| 11568 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11569 | Value |= (op & 0xf) << 11; |
| 11570 | break; |
| 11571 | } |
| 11572 | case AArch64::FCADDv2f32: |
| 11573 | case AArch64::FCADDv2f64: |
| 11574 | case AArch64::FCADDv4f16: |
| 11575 | case AArch64::FCADDv4f32: |
| 11576 | case AArch64::FCADDv8f16: { |
| 11577 | // op: Rd |
| 11578 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11579 | Value |= (op & 0x1f); |
| 11580 | // op: Rn |
| 11581 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11582 | Value |= (op & 0x1f) << 5; |
| 11583 | // op: Rm |
| 11584 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11585 | Value |= (op & 0x1f) << 16; |
| 11586 | // op: rot |
| 11587 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11588 | Value |= (op & 0x1) << 12; |
| 11589 | break; |
| 11590 | } |
| 11591 | case AArch64::ADDSWrs: |
| 11592 | case AArch64::ADDSXrs: |
| 11593 | case AArch64::ADDWrs: |
| 11594 | case AArch64::ADDXrs: |
| 11595 | case AArch64::ANDSWrs: |
| 11596 | case AArch64::ANDSXrs: |
| 11597 | case AArch64::ANDWrs: |
| 11598 | case AArch64::ANDXrs: |
| 11599 | case AArch64::BICSWrs: |
| 11600 | case AArch64::BICSXrs: |
| 11601 | case AArch64::BICWrs: |
| 11602 | case AArch64::BICXrs: |
| 11603 | case AArch64::EONWrs: |
| 11604 | case AArch64::EONXrs: |
| 11605 | case AArch64::EORWrs: |
| 11606 | case AArch64::EORXrs: |
| 11607 | case AArch64::ORNWrs: |
| 11608 | case AArch64::ORNXrs: |
| 11609 | case AArch64::ORRWrs: |
| 11610 | case AArch64::ORRXrs: |
| 11611 | case AArch64::SUBSWrs: |
| 11612 | case AArch64::SUBSXrs: |
| 11613 | case AArch64::SUBWrs: |
| 11614 | case AArch64::SUBXrs: { |
| 11615 | // op: Rd |
| 11616 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11617 | Value |= (op & 0x1f); |
| 11618 | // op: Rn |
| 11619 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11620 | Value |= (op & 0x1f) << 5; |
| 11621 | // op: Rm |
| 11622 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11623 | Value |= (op & 0x1f) << 16; |
| 11624 | // op: shift |
| 11625 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11626 | Value |= (op & 0xc0) << 16; |
| 11627 | Value |= (op & 0x3f) << 10; |
| 11628 | break; |
| 11629 | } |
| 11630 | case AArch64::ADDPT_shift: |
| 11631 | case AArch64::SUBPT_shift: { |
| 11632 | // op: Rd |
| 11633 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11634 | Value |= (op & 0x1f); |
| 11635 | // op: Rn |
| 11636 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11637 | Value |= (op & 0x1f) << 5; |
| 11638 | // op: Rm |
| 11639 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11640 | Value |= (op & 0x1f) << 16; |
| 11641 | // op: shift_imm |
| 11642 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11643 | Value |= (op & 0x7) << 10; |
| 11644 | break; |
| 11645 | } |
| 11646 | case AArch64::SMULHrr: |
| 11647 | case AArch64::UMULHrr: { |
| 11648 | // op: Rd |
| 11649 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11650 | Value |= (op & 0x1f); |
| 11651 | // op: Rn |
| 11652 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11653 | Value |= (op & 0x1f) << 5; |
| 11654 | // op: Rm |
| 11655 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11656 | Value |= (op & 0x1f) << 16; |
| 11657 | Value = fixMulHigh(MI, EncodedValue: Value, STI); |
| 11658 | break; |
| 11659 | } |
| 11660 | case AArch64::FMULXv1i16_indexed: |
| 11661 | case AArch64::FMULXv4i16_indexed: |
| 11662 | case AArch64::FMULXv8i16_indexed: |
| 11663 | case AArch64::FMULv1i16_indexed: |
| 11664 | case AArch64::FMULv4i16_indexed: |
| 11665 | case AArch64::FMULv8i16_indexed: |
| 11666 | case AArch64::MULv4i16_indexed: |
| 11667 | case AArch64::MULv8i16_indexed: |
| 11668 | case AArch64::SMULLv4i16_indexed: |
| 11669 | case AArch64::SMULLv8i16_indexed: |
| 11670 | case AArch64::SQDMULHv1i16_indexed: |
| 11671 | case AArch64::SQDMULHv4i16_indexed: |
| 11672 | case AArch64::SQDMULHv8i16_indexed: |
| 11673 | case AArch64::SQDMULLv1i32_indexed: |
| 11674 | case AArch64::SQDMULLv4i16_indexed: |
| 11675 | case AArch64::SQDMULLv8i16_indexed: |
| 11676 | case AArch64::SQRDMULHv1i16_indexed: |
| 11677 | case AArch64::SQRDMULHv4i16_indexed: |
| 11678 | case AArch64::SQRDMULHv8i16_indexed: |
| 11679 | case AArch64::UMULLv4i16_indexed: |
| 11680 | case AArch64::UMULLv8i16_indexed: { |
| 11681 | // op: Rd |
| 11682 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11683 | Value |= (op & 0x1f); |
| 11684 | // op: Rn |
| 11685 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11686 | Value |= (op & 0x1f) << 5; |
| 11687 | // op: Rm |
| 11688 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11689 | Value |= (op & 0xf) << 16; |
| 11690 | // op: idx |
| 11691 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 11692 | Value |= (op & 0x3) << 20; |
| 11693 | Value |= (op & 0x4) << 9; |
| 11694 | break; |
| 11695 | } |
| 11696 | case AArch64::DUPv2i64lane: |
| 11697 | case AArch64::UMOVvi64: { |
| 11698 | // op: Rd |
| 11699 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11700 | Value |= (op & 0x1f); |
| 11701 | // op: Rn |
| 11702 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11703 | Value |= (op & 0x1f) << 5; |
| 11704 | // op: idx |
| 11705 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11706 | Value |= (op & 0x1) << 20; |
| 11707 | break; |
| 11708 | } |
| 11709 | case AArch64::DUPv2i32lane: |
| 11710 | case AArch64::DUPv4i32lane: |
| 11711 | case AArch64::SMOVvi32to64: |
| 11712 | case AArch64::UMOVvi32: { |
| 11713 | // op: Rd |
| 11714 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11715 | Value |= (op & 0x1f); |
| 11716 | // op: Rn |
| 11717 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11718 | Value |= (op & 0x1f) << 5; |
| 11719 | // op: idx |
| 11720 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11721 | Value |= (op & 0x3) << 19; |
| 11722 | break; |
| 11723 | } |
| 11724 | case AArch64::DUPv4i16lane: |
| 11725 | case AArch64::DUPv8i16lane: |
| 11726 | case AArch64::SMOVvi16to32: |
| 11727 | case AArch64::SMOVvi16to64: |
| 11728 | case AArch64::UMOVvi16: { |
| 11729 | // op: Rd |
| 11730 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11731 | Value |= (op & 0x1f); |
| 11732 | // op: Rn |
| 11733 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11734 | Value |= (op & 0x1f) << 5; |
| 11735 | // op: idx |
| 11736 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11737 | Value |= (op & 0x7) << 18; |
| 11738 | break; |
| 11739 | } |
| 11740 | case AArch64::DUPv16i8lane: |
| 11741 | case AArch64::DUPv8i8lane: |
| 11742 | case AArch64::SMOVvi8to32: |
| 11743 | case AArch64::SMOVvi8to64: |
| 11744 | case AArch64::UMOVvi8: { |
| 11745 | // op: Rd |
| 11746 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11747 | Value |= (op & 0x1f); |
| 11748 | // op: Rn |
| 11749 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11750 | Value |= (op & 0x1f) << 5; |
| 11751 | // op: idx |
| 11752 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11753 | Value |= (op & 0xf) << 17; |
| 11754 | break; |
| 11755 | } |
| 11756 | case AArch64::ADDSWri: |
| 11757 | case AArch64::ADDSXri: |
| 11758 | case AArch64::ADDWri: |
| 11759 | case AArch64::ADDXri: |
| 11760 | case AArch64::SUBSWri: |
| 11761 | case AArch64::SUBSXri: |
| 11762 | case AArch64::SUBWri: |
| 11763 | case AArch64::SUBXri: { |
| 11764 | // op: Rd |
| 11765 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11766 | Value |= (op & 0x1f); |
| 11767 | // op: Rn |
| 11768 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11769 | Value |= (op & 0x1f) << 5; |
| 11770 | // op: imm |
| 11771 | op = getAddSubImmOpValue(MI, OpIdx: 2, Fixups, STI); |
| 11772 | Value |= (op & 0x3fff) << 10; |
| 11773 | break; |
| 11774 | } |
| 11775 | case AArch64::ANDSXri: |
| 11776 | case AArch64::ANDXri: |
| 11777 | case AArch64::EORXri: |
| 11778 | case AArch64::ORRXri: { |
| 11779 | // op: Rd |
| 11780 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11781 | Value |= (op & 0x1f); |
| 11782 | // op: Rn |
| 11783 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11784 | Value |= (op & 0x1f) << 5; |
| 11785 | // op: imm |
| 11786 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11787 | Value |= (op & 0x1fff) << 10; |
| 11788 | break; |
| 11789 | } |
| 11790 | case AArch64::SMAXWri: |
| 11791 | case AArch64::SMAXXri: |
| 11792 | case AArch64::SMINWri: |
| 11793 | case AArch64::SMINXri: |
| 11794 | case AArch64::UMAXWri: |
| 11795 | case AArch64::UMAXXri: |
| 11796 | case AArch64::UMINWri: |
| 11797 | case AArch64::UMINXri: { |
| 11798 | // op: Rd |
| 11799 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11800 | Value |= (op & 0x1f); |
| 11801 | // op: Rn |
| 11802 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11803 | Value |= (op & 0x1f) << 5; |
| 11804 | // op: imm |
| 11805 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11806 | Value |= (op & 0xff) << 10; |
| 11807 | break; |
| 11808 | } |
| 11809 | case AArch64::ANDSWri: |
| 11810 | case AArch64::ANDWri: |
| 11811 | case AArch64::EORWri: |
| 11812 | case AArch64::ORRWri: { |
| 11813 | // op: Rd |
| 11814 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11815 | Value |= (op & 0x1f); |
| 11816 | // op: Rn |
| 11817 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11818 | Value |= (op & 0x1f) << 5; |
| 11819 | // op: imm |
| 11820 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 11821 | Value |= (op & 0xfff) << 10; |
| 11822 | break; |
| 11823 | } |
| 11824 | case AArch64::SHLv4i16_shift: |
| 11825 | case AArch64::SHLv8i16_shift: |
| 11826 | case AArch64::SQSHLUh: |
| 11827 | case AArch64::SQSHLUv4i16_shift: |
| 11828 | case AArch64::SQSHLUv8i16_shift: |
| 11829 | case AArch64::SQSHLh: |
| 11830 | case AArch64::SQSHLv4i16_shift: |
| 11831 | case AArch64::SQSHLv8i16_shift: |
| 11832 | case AArch64::SSHLLv4i16_shift: |
| 11833 | case AArch64::SSHLLv8i16_shift: |
| 11834 | case AArch64::UQSHLh: |
| 11835 | case AArch64::UQSHLv4i16_shift: |
| 11836 | case AArch64::UQSHLv8i16_shift: |
| 11837 | case AArch64::USHLLv4i16_shift: |
| 11838 | case AArch64::USHLLv8i16_shift: { |
| 11839 | // op: Rd |
| 11840 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11841 | Value |= (op & 0x1f); |
| 11842 | // op: Rn |
| 11843 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11844 | Value |= (op & 0x1f) << 5; |
| 11845 | // op: imm |
| 11846 | op = getVecShiftL16OpValue(MI, OpIdx: 2, Fixups, STI); |
| 11847 | Value |= (op & 0xf) << 16; |
| 11848 | break; |
| 11849 | } |
| 11850 | case AArch64::SHLv2i32_shift: |
| 11851 | case AArch64::SHLv4i32_shift: |
| 11852 | case AArch64::SQSHLUs: |
| 11853 | case AArch64::SQSHLUv2i32_shift: |
| 11854 | case AArch64::SQSHLUv4i32_shift: |
| 11855 | case AArch64::SQSHLs: |
| 11856 | case AArch64::SQSHLv2i32_shift: |
| 11857 | case AArch64::SQSHLv4i32_shift: |
| 11858 | case AArch64::SSHLLv2i32_shift: |
| 11859 | case AArch64::SSHLLv4i32_shift: |
| 11860 | case AArch64::UQSHLs: |
| 11861 | case AArch64::UQSHLv2i32_shift: |
| 11862 | case AArch64::UQSHLv4i32_shift: |
| 11863 | case AArch64::USHLLv2i32_shift: |
| 11864 | case AArch64::USHLLv4i32_shift: { |
| 11865 | // op: Rd |
| 11866 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11867 | Value |= (op & 0x1f); |
| 11868 | // op: Rn |
| 11869 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11870 | Value |= (op & 0x1f) << 5; |
| 11871 | // op: imm |
| 11872 | op = getVecShiftL32OpValue(MI, OpIdx: 2, Fixups, STI); |
| 11873 | Value |= (op & 0x1f) << 16; |
| 11874 | break; |
| 11875 | } |
| 11876 | case AArch64::SHLd: |
| 11877 | case AArch64::SHLv2i64_shift: |
| 11878 | case AArch64::SQSHLUd: |
| 11879 | case AArch64::SQSHLUv2i64_shift: |
| 11880 | case AArch64::SQSHLd: |
| 11881 | case AArch64::SQSHLv2i64_shift: |
| 11882 | case AArch64::UQSHLd: |
| 11883 | case AArch64::UQSHLv2i64_shift: { |
| 11884 | // op: Rd |
| 11885 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11886 | Value |= (op & 0x1f); |
| 11887 | // op: Rn |
| 11888 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11889 | Value |= (op & 0x1f) << 5; |
| 11890 | // op: imm |
| 11891 | op = getVecShiftL64OpValue(MI, OpIdx: 2, Fixups, STI); |
| 11892 | Value |= (op & 0x3f) << 16; |
| 11893 | break; |
| 11894 | } |
| 11895 | case AArch64::SHLv16i8_shift: |
| 11896 | case AArch64::SHLv8i8_shift: |
| 11897 | case AArch64::SQSHLUb: |
| 11898 | case AArch64::SQSHLUv16i8_shift: |
| 11899 | case AArch64::SQSHLUv8i8_shift: |
| 11900 | case AArch64::SQSHLb: |
| 11901 | case AArch64::SQSHLv16i8_shift: |
| 11902 | case AArch64::SQSHLv8i8_shift: |
| 11903 | case AArch64::SSHLLv16i8_shift: |
| 11904 | case AArch64::SSHLLv8i8_shift: |
| 11905 | case AArch64::UQSHLb: |
| 11906 | case AArch64::UQSHLv16i8_shift: |
| 11907 | case AArch64::UQSHLv8i8_shift: |
| 11908 | case AArch64::USHLLv16i8_shift: |
| 11909 | case AArch64::USHLLv8i8_shift: { |
| 11910 | // op: Rd |
| 11911 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11912 | Value |= (op & 0x1f); |
| 11913 | // op: Rn |
| 11914 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11915 | Value |= (op & 0x1f) << 5; |
| 11916 | // op: imm |
| 11917 | op = getVecShiftL8OpValue(MI, OpIdx: 2, Fixups, STI); |
| 11918 | Value |= (op & 0x7) << 16; |
| 11919 | break; |
| 11920 | } |
| 11921 | case AArch64::RSHRNv8i8_shift: |
| 11922 | case AArch64::SHRNv8i8_shift: |
| 11923 | case AArch64::SQRSHRNv8i8_shift: |
| 11924 | case AArch64::SQRSHRUNv8i8_shift: |
| 11925 | case AArch64::SQSHRNv8i8_shift: |
| 11926 | case AArch64::SQSHRUNv8i8_shift: |
| 11927 | case AArch64::UQRSHRNv8i8_shift: |
| 11928 | case AArch64::UQSHRNv8i8_shift: { |
| 11929 | // op: Rd |
| 11930 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11931 | Value |= (op & 0x1f); |
| 11932 | // op: Rn |
| 11933 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11934 | Value |= (op & 0x1f) << 5; |
| 11935 | // op: imm |
| 11936 | op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI); |
| 11937 | Value |= (op & 0x7) << 16; |
| 11938 | break; |
| 11939 | } |
| 11940 | case AArch64::FCVTZSh: |
| 11941 | case AArch64::FCVTZSv4i16_shift: |
| 11942 | case AArch64::FCVTZSv8i16_shift: |
| 11943 | case AArch64::FCVTZUh: |
| 11944 | case AArch64::FCVTZUv4i16_shift: |
| 11945 | case AArch64::FCVTZUv8i16_shift: |
| 11946 | case AArch64::SCVTFh: |
| 11947 | case AArch64::SCVTFv4i16_shift: |
| 11948 | case AArch64::SCVTFv8i16_shift: |
| 11949 | case AArch64::SQRSHRNh: |
| 11950 | case AArch64::SQRSHRUNh: |
| 11951 | case AArch64::SQSHRNh: |
| 11952 | case AArch64::SQSHRUNh: |
| 11953 | case AArch64::SRSHRv4i16_shift: |
| 11954 | case AArch64::SRSHRv8i16_shift: |
| 11955 | case AArch64::SSHRv4i16_shift: |
| 11956 | case AArch64::SSHRv8i16_shift: |
| 11957 | case AArch64::UCVTFh: |
| 11958 | case AArch64::UCVTFv4i16_shift: |
| 11959 | case AArch64::UCVTFv8i16_shift: |
| 11960 | case AArch64::UQRSHRNh: |
| 11961 | case AArch64::UQSHRNh: |
| 11962 | case AArch64::URSHRv4i16_shift: |
| 11963 | case AArch64::URSHRv8i16_shift: |
| 11964 | case AArch64::USHRv4i16_shift: |
| 11965 | case AArch64::USHRv8i16_shift: { |
| 11966 | // op: Rd |
| 11967 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 11968 | Value |= (op & 0x1f); |
| 11969 | // op: Rn |
| 11970 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 11971 | Value |= (op & 0x1f) << 5; |
| 11972 | // op: imm |
| 11973 | op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI); |
| 11974 | Value |= (op & 0xf) << 16; |
| 11975 | break; |
| 11976 | } |
| 11977 | case AArch64::FCVTZSs: |
| 11978 | case AArch64::FCVTZSv2i32_shift: |
| 11979 | case AArch64::FCVTZSv4i32_shift: |
| 11980 | case AArch64::FCVTZUs: |
| 11981 | case AArch64::FCVTZUv2i32_shift: |
| 11982 | case AArch64::FCVTZUv4i32_shift: |
| 11983 | case AArch64::SCVTFs: |
| 11984 | case AArch64::SCVTFv2i32_shift: |
| 11985 | case AArch64::SCVTFv4i32_shift: |
| 11986 | case AArch64::SQRSHRNs: |
| 11987 | case AArch64::SQRSHRUNs: |
| 11988 | case AArch64::SQSHRNs: |
| 11989 | case AArch64::SQSHRUNs: |
| 11990 | case AArch64::SRSHRv2i32_shift: |
| 11991 | case AArch64::SRSHRv4i32_shift: |
| 11992 | case AArch64::SSHRv2i32_shift: |
| 11993 | case AArch64::SSHRv4i32_shift: |
| 11994 | case AArch64::UCVTFs: |
| 11995 | case AArch64::UCVTFv2i32_shift: |
| 11996 | case AArch64::UCVTFv4i32_shift: |
| 11997 | case AArch64::UQRSHRNs: |
| 11998 | case AArch64::UQSHRNs: |
| 11999 | case AArch64::URSHRv2i32_shift: |
| 12000 | case AArch64::URSHRv4i32_shift: |
| 12001 | case AArch64::USHRv2i32_shift: |
| 12002 | case AArch64::USHRv4i32_shift: { |
| 12003 | // op: Rd |
| 12004 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12005 | Value |= (op & 0x1f); |
| 12006 | // op: Rn |
| 12007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12008 | Value |= (op & 0x1f) << 5; |
| 12009 | // op: imm |
| 12010 | op = getVecShiftR32OpValue(MI, OpIdx: 2, Fixups, STI); |
| 12011 | Value |= (op & 0x1f) << 16; |
| 12012 | break; |
| 12013 | } |
| 12014 | case AArch64::RSHRNv4i16_shift: |
| 12015 | case AArch64::SHRNv4i16_shift: |
| 12016 | case AArch64::SQRSHRNv4i16_shift: |
| 12017 | case AArch64::SQRSHRUNv4i16_shift: |
| 12018 | case AArch64::SQSHRNv4i16_shift: |
| 12019 | case AArch64::SQSHRUNv4i16_shift: |
| 12020 | case AArch64::UQRSHRNv4i16_shift: |
| 12021 | case AArch64::UQSHRNv4i16_shift: { |
| 12022 | // op: Rd |
| 12023 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12024 | Value |= (op & 0x1f); |
| 12025 | // op: Rn |
| 12026 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12027 | Value |= (op & 0x1f) << 5; |
| 12028 | // op: imm |
| 12029 | op = getVecShiftR32OpValue(MI, OpIdx: 2, Fixups, STI); |
| 12030 | Value |= (op & 0xf) << 16; |
| 12031 | break; |
| 12032 | } |
| 12033 | case AArch64::RSHRNv2i32_shift: |
| 12034 | case AArch64::SHRNv2i32_shift: |
| 12035 | case AArch64::SQRSHRNv2i32_shift: |
| 12036 | case AArch64::SQRSHRUNv2i32_shift: |
| 12037 | case AArch64::SQSHRNv2i32_shift: |
| 12038 | case AArch64::SQSHRUNv2i32_shift: |
| 12039 | case AArch64::UQRSHRNv2i32_shift: |
| 12040 | case AArch64::UQSHRNv2i32_shift: { |
| 12041 | // op: Rd |
| 12042 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12043 | Value |= (op & 0x1f); |
| 12044 | // op: Rn |
| 12045 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12046 | Value |= (op & 0x1f) << 5; |
| 12047 | // op: imm |
| 12048 | op = getVecShiftR64OpValue(MI, OpIdx: 2, Fixups, STI); |
| 12049 | Value |= (op & 0x1f) << 16; |
| 12050 | break; |
| 12051 | } |
| 12052 | case AArch64::FCVTZSd: |
| 12053 | case AArch64::FCVTZSv2i64_shift: |
| 12054 | case AArch64::FCVTZUd: |
| 12055 | case AArch64::FCVTZUv2i64_shift: |
| 12056 | case AArch64::SCVTFd: |
| 12057 | case AArch64::SCVTFv2i64_shift: |
| 12058 | case AArch64::SRSHRd: |
| 12059 | case AArch64::SRSHRv2i64_shift: |
| 12060 | case AArch64::SSHRd: |
| 12061 | case AArch64::SSHRv2i64_shift: |
| 12062 | case AArch64::UCVTFd: |
| 12063 | case AArch64::UCVTFv2i64_shift: |
| 12064 | case AArch64::URSHRd: |
| 12065 | case AArch64::URSHRv2i64_shift: |
| 12066 | case AArch64::USHRd: |
| 12067 | case AArch64::USHRv2i64_shift: { |
| 12068 | // op: Rd |
| 12069 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12070 | Value |= (op & 0x1f); |
| 12071 | // op: Rn |
| 12072 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12073 | Value |= (op & 0x1f) << 5; |
| 12074 | // op: imm |
| 12075 | op = getVecShiftR64OpValue(MI, OpIdx: 2, Fixups, STI); |
| 12076 | Value |= (op & 0x3f) << 16; |
| 12077 | break; |
| 12078 | } |
| 12079 | case AArch64::SQRSHRNb: |
| 12080 | case AArch64::SQRSHRUNb: |
| 12081 | case AArch64::SQSHRNb: |
| 12082 | case AArch64::SQSHRUNb: |
| 12083 | case AArch64::SRSHRv16i8_shift: |
| 12084 | case AArch64::SRSHRv8i8_shift: |
| 12085 | case AArch64::SSHRv16i8_shift: |
| 12086 | case AArch64::SSHRv8i8_shift: |
| 12087 | case AArch64::UQRSHRNb: |
| 12088 | case AArch64::UQSHRNb: |
| 12089 | case AArch64::URSHRv16i8_shift: |
| 12090 | case AArch64::URSHRv8i8_shift: |
| 12091 | case AArch64::USHRv16i8_shift: |
| 12092 | case AArch64::USHRv8i8_shift: { |
| 12093 | // op: Rd |
| 12094 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12095 | Value |= (op & 0x1f); |
| 12096 | // op: Rn |
| 12097 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12098 | Value |= (op & 0x1f) << 5; |
| 12099 | // op: imm |
| 12100 | op = getVecShiftR8OpValue(MI, OpIdx: 2, Fixups, STI); |
| 12101 | Value |= (op & 0x7) << 16; |
| 12102 | break; |
| 12103 | } |
| 12104 | case AArch64::ADDG: |
| 12105 | case AArch64::SUBG: { |
| 12106 | // op: Rd |
| 12107 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12108 | Value |= (op & 0x1f); |
| 12109 | // op: Rn |
| 12110 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12111 | Value |= (op & 0x1f) << 5; |
| 12112 | // op: imm6 |
| 12113 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12114 | Value |= (op & 0x3f) << 16; |
| 12115 | // op: imm4 |
| 12116 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12117 | Value |= (op & 0xf) << 10; |
| 12118 | break; |
| 12119 | } |
| 12120 | case AArch64::SBFMWri: |
| 12121 | case AArch64::UBFMWri: { |
| 12122 | // op: Rd |
| 12123 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12124 | Value |= (op & 0x1f); |
| 12125 | // op: Rn |
| 12126 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12127 | Value |= (op & 0x1f) << 5; |
| 12128 | // op: immr |
| 12129 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12130 | Value |= (op & 0x1f) << 16; |
| 12131 | // op: imms |
| 12132 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12133 | Value |= (op & 0x1f) << 10; |
| 12134 | break; |
| 12135 | } |
| 12136 | case AArch64::SBFMXri: |
| 12137 | case AArch64::UBFMXri: { |
| 12138 | // op: Rd |
| 12139 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12140 | Value |= (op & 0x1f); |
| 12141 | // op: Rn |
| 12142 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12143 | Value |= (op & 0x1f) << 5; |
| 12144 | // op: immr |
| 12145 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12146 | Value |= (op & 0x3f) << 16; |
| 12147 | // op: imms |
| 12148 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12149 | Value |= (op & 0x3f) << 10; |
| 12150 | break; |
| 12151 | } |
| 12152 | case AArch64::FCVTZSSWDri: |
| 12153 | case AArch64::FCVTZSSWHri: |
| 12154 | case AArch64::FCVTZSSWSri: |
| 12155 | case AArch64::FCVTZUSWDri: |
| 12156 | case AArch64::FCVTZUSWHri: |
| 12157 | case AArch64::FCVTZUSWSri: |
| 12158 | case AArch64::SCVTFSWDri: |
| 12159 | case AArch64::SCVTFSWHri: |
| 12160 | case AArch64::SCVTFSWSri: |
| 12161 | case AArch64::UCVTFSWDri: |
| 12162 | case AArch64::UCVTFSWHri: |
| 12163 | case AArch64::UCVTFSWSri: { |
| 12164 | // op: Rd |
| 12165 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12166 | Value |= (op & 0x1f); |
| 12167 | // op: Rn |
| 12168 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12169 | Value |= (op & 0x1f) << 5; |
| 12170 | // op: scale |
| 12171 | op = getFixedPointScaleOpValue(MI, OpIdx: 2, Fixups, STI); |
| 12172 | Value |= (op & 0x1f) << 10; |
| 12173 | break; |
| 12174 | } |
| 12175 | case AArch64::FCVTZSSXDri: |
| 12176 | case AArch64::FCVTZSSXHri: |
| 12177 | case AArch64::FCVTZSSXSri: |
| 12178 | case AArch64::FCVTZUSXDri: |
| 12179 | case AArch64::FCVTZUSXHri: |
| 12180 | case AArch64::FCVTZUSXSri: |
| 12181 | case AArch64::SCVTFSXDri: |
| 12182 | case AArch64::SCVTFSXHri: |
| 12183 | case AArch64::SCVTFSXSri: |
| 12184 | case AArch64::UCVTFSXDri: |
| 12185 | case AArch64::UCVTFSXHri: |
| 12186 | case AArch64::UCVTFSXSri: { |
| 12187 | // op: Rd |
| 12188 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12189 | Value |= (op & 0x1f); |
| 12190 | // op: Rn |
| 12191 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12192 | Value |= (op & 0x1f) << 5; |
| 12193 | // op: scale |
| 12194 | op = getFixedPointScaleOpValue(MI, OpIdx: 2, Fixups, STI); |
| 12195 | Value |= (op & 0x3f) << 10; |
| 12196 | break; |
| 12197 | } |
| 12198 | case AArch64::BFMWri: { |
| 12199 | // op: Rd |
| 12200 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12201 | Value |= (op & 0x1f); |
| 12202 | // op: Rn |
| 12203 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12204 | Value |= (op & 0x1f) << 5; |
| 12205 | // op: immr |
| 12206 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12207 | Value |= (op & 0x1f) << 16; |
| 12208 | // op: imms |
| 12209 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 12210 | Value |= (op & 0x1f) << 10; |
| 12211 | break; |
| 12212 | } |
| 12213 | case AArch64::BFMXri: { |
| 12214 | // op: Rd |
| 12215 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12216 | Value |= (op & 0x1f); |
| 12217 | // op: Rn |
| 12218 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12219 | Value |= (op & 0x1f) << 5; |
| 12220 | // op: immr |
| 12221 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12222 | Value |= (op & 0x3f) << 16; |
| 12223 | // op: imms |
| 12224 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 12225 | Value |= (op & 0x3f) << 10; |
| 12226 | break; |
| 12227 | } |
| 12228 | case AArch64::FMOVDi: |
| 12229 | case AArch64::FMOVHi: |
| 12230 | case AArch64::FMOVSi: { |
| 12231 | // op: Rd |
| 12232 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12233 | Value |= (op & 0x1f); |
| 12234 | // op: imm |
| 12235 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12236 | Value |= (op & 0xff) << 13; |
| 12237 | break; |
| 12238 | } |
| 12239 | case AArch64::MOVNWi: |
| 12240 | case AArch64::MOVNXi: { |
| 12241 | // op: Rd |
| 12242 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12243 | Value |= (op & 0x1f); |
| 12244 | // op: imm |
| 12245 | op = getMoveWideImmOpValue(MI, OpIdx: 1, Fixups, STI); |
| 12246 | Value |= (op & 0xffff) << 5; |
| 12247 | // op: shift |
| 12248 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12249 | Value |= (op & 0x30) << 17; |
| 12250 | break; |
| 12251 | } |
| 12252 | case AArch64::MOVZWi: |
| 12253 | case AArch64::MOVZXi: { |
| 12254 | // op: Rd |
| 12255 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12256 | Value |= (op & 0x1f); |
| 12257 | // op: imm |
| 12258 | op = getMoveWideImmOpValue(MI, OpIdx: 1, Fixups, STI); |
| 12259 | Value |= (op & 0xffff) << 5; |
| 12260 | // op: shift |
| 12261 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12262 | Value |= (op & 0x30) << 17; |
| 12263 | Value = fixMOVZ(MI, EncodedValue: Value, STI); |
| 12264 | break; |
| 12265 | } |
| 12266 | case AArch64::MOVKWi: |
| 12267 | case AArch64::MOVKXi: { |
| 12268 | // op: Rd |
| 12269 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12270 | Value |= (op & 0x1f); |
| 12271 | // op: imm |
| 12272 | op = getMoveWideImmOpValue(MI, OpIdx: 2, Fixups, STI); |
| 12273 | Value |= (op & 0xffff) << 5; |
| 12274 | // op: shift |
| 12275 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12276 | Value |= (op & 0x30) << 17; |
| 12277 | break; |
| 12278 | } |
| 12279 | case AArch64::CNTB_XPiI: |
| 12280 | case AArch64::CNTD_XPiI: |
| 12281 | case AArch64::CNTH_XPiI: |
| 12282 | case AArch64::CNTW_XPiI: { |
| 12283 | // op: Rd |
| 12284 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12285 | Value |= (op & 0x1f); |
| 12286 | // op: imm4 |
| 12287 | op = getSVEIncDecImm(MI, OpIdx: 2, Fixups, STI); |
| 12288 | Value |= (op & 0xf) << 16; |
| 12289 | // op: pattern |
| 12290 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12291 | Value |= (op & 0x1f) << 5; |
| 12292 | break; |
| 12293 | } |
| 12294 | case AArch64::RDSVLI_XI: |
| 12295 | case AArch64::RDVLI_XI: { |
| 12296 | // op: Rd |
| 12297 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12298 | Value |= (op & 0x1f); |
| 12299 | // op: imm6 |
| 12300 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12301 | Value |= (op & 0x3f) << 5; |
| 12302 | break; |
| 12303 | } |
| 12304 | case AArch64::FMOVv2f32_ns: |
| 12305 | case AArch64::FMOVv2f64_ns: |
| 12306 | case AArch64::FMOVv4f16_ns: |
| 12307 | case AArch64::FMOVv4f32_ns: |
| 12308 | case AArch64::FMOVv8f16_ns: |
| 12309 | case AArch64::MOVID: |
| 12310 | case AArch64::MOVIv16b_ns: |
| 12311 | case AArch64::MOVIv2d_ns: |
| 12312 | case AArch64::MOVIv8b_ns: { |
| 12313 | // op: Rd |
| 12314 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12315 | Value |= (op & 0x1f); |
| 12316 | // op: imm8 |
| 12317 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12318 | Value |= (op & 0xe0) << 11; |
| 12319 | Value |= (op & 0x1f) << 5; |
| 12320 | break; |
| 12321 | } |
| 12322 | case AArch64::MOVIv2s_msl: |
| 12323 | case AArch64::MOVIv4s_msl: |
| 12324 | case AArch64::MVNIv2s_msl: |
| 12325 | case AArch64::MVNIv4s_msl: { |
| 12326 | // op: Rd |
| 12327 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12328 | Value |= (op & 0x1f); |
| 12329 | // op: imm8 |
| 12330 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12331 | Value |= (op & 0xe0) << 11; |
| 12332 | Value |= (op & 0x1f) << 5; |
| 12333 | // op: shift |
| 12334 | op = getMoveVecShifterOpValue(MI, OpIdx: 2, Fixups, STI); |
| 12335 | Value |= (op & 0x1) << 12; |
| 12336 | break; |
| 12337 | } |
| 12338 | case AArch64::MOVIv4i16: |
| 12339 | case AArch64::MOVIv8i16: |
| 12340 | case AArch64::MVNIv4i16: |
| 12341 | case AArch64::MVNIv8i16: { |
| 12342 | // op: Rd |
| 12343 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12344 | Value |= (op & 0x1f); |
| 12345 | // op: imm8 |
| 12346 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12347 | Value |= (op & 0xe0) << 11; |
| 12348 | Value |= (op & 0x1f) << 5; |
| 12349 | // op: shift |
| 12350 | op = getVecShifterOpValue(MI, OpIdx: 2, Fixups, STI); |
| 12351 | Value |= (op & 0x1) << 13; |
| 12352 | break; |
| 12353 | } |
| 12354 | case AArch64::MOVIv2i32: |
| 12355 | case AArch64::MOVIv4i32: |
| 12356 | case AArch64::MVNIv2i32: |
| 12357 | case AArch64::MVNIv4i32: { |
| 12358 | // op: Rd |
| 12359 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 12360 | Value |= (op & 0x1f); |
| 12361 | // op: imm8 |
| 12362 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12363 | Value |= (op & 0xe0) << 11; |
| 12364 | Value |= (op & 0x1f) << 5; |
| 12365 | // op: shift |
| 12366 | op = getVecShifterOpValue(MI, OpIdx: 2, Fixups, STI); |
| 12367 | Value |= (op & 0x3) << 13; |
| 12368 | break; |
| 12369 | } |
| 12370 | case AArch64::AUTDZA: |
| 12371 | case AArch64::AUTDZB: |
| 12372 | case AArch64::AUTIZA: |
| 12373 | case AArch64::AUTIZB: |
| 12374 | case AArch64::PACDZA: |
| 12375 | case AArch64::PACDZB: |
| 12376 | case AArch64::PACIZA: |
| 12377 | case AArch64::PACIZB: { |
| 12378 | // op: Rd |
| 12379 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12380 | Value |= (op & 0x1f); |
| 12381 | break; |
| 12382 | } |
| 12383 | case AArch64::AESDrr: |
| 12384 | case AArch64::AESErr: |
| 12385 | case AArch64::AUTDA: |
| 12386 | case AArch64::AUTDB: |
| 12387 | case AArch64::AUTIA: |
| 12388 | case AArch64::AUTIB: |
| 12389 | case AArch64::BFCVTN2: |
| 12390 | case AArch64::FCVTNv4i32: |
| 12391 | case AArch64::FCVTNv8i16: |
| 12392 | case AArch64::FCVTXNv4f32: |
| 12393 | case AArch64::PACDA: |
| 12394 | case AArch64::PACDB: |
| 12395 | case AArch64::PACIA: |
| 12396 | case AArch64::PACIB: |
| 12397 | case AArch64::SADALPv16i8_v8i16: |
| 12398 | case AArch64::SADALPv2i32_v1i64: |
| 12399 | case AArch64::SADALPv4i16_v2i32: |
| 12400 | case AArch64::SADALPv4i32_v2i64: |
| 12401 | case AArch64::SADALPv8i16_v4i32: |
| 12402 | case AArch64::SADALPv8i8_v4i16: |
| 12403 | case AArch64::SHA1SU1rr: |
| 12404 | case AArch64::SHA256SU0rr: |
| 12405 | case AArch64::SQXTNv16i8: |
| 12406 | case AArch64::SQXTNv4i32: |
| 12407 | case AArch64::SQXTNv8i16: |
| 12408 | case AArch64::SQXTUNv16i8: |
| 12409 | case AArch64::SQXTUNv4i32: |
| 12410 | case AArch64::SQXTUNv8i16: |
| 12411 | case AArch64::SUQADDv16i8: |
| 12412 | case AArch64::SUQADDv1i16: |
| 12413 | case AArch64::SUQADDv1i32: |
| 12414 | case AArch64::SUQADDv1i64: |
| 12415 | case AArch64::SUQADDv1i8: |
| 12416 | case AArch64::SUQADDv2i32: |
| 12417 | case AArch64::SUQADDv2i64: |
| 12418 | case AArch64::SUQADDv4i16: |
| 12419 | case AArch64::SUQADDv4i32: |
| 12420 | case AArch64::SUQADDv8i16: |
| 12421 | case AArch64::SUQADDv8i8: |
| 12422 | case AArch64::UADALPv16i8_v8i16: |
| 12423 | case AArch64::UADALPv2i32_v1i64: |
| 12424 | case AArch64::UADALPv4i16_v2i32: |
| 12425 | case AArch64::UADALPv4i32_v2i64: |
| 12426 | case AArch64::UADALPv8i16_v4i32: |
| 12427 | case AArch64::UADALPv8i8_v4i16: |
| 12428 | case AArch64::UQXTNv16i8: |
| 12429 | case AArch64::UQXTNv4i32: |
| 12430 | case AArch64::UQXTNv8i16: |
| 12431 | case AArch64::USQADDv16i8: |
| 12432 | case AArch64::USQADDv1i16: |
| 12433 | case AArch64::USQADDv1i32: |
| 12434 | case AArch64::USQADDv1i64: |
| 12435 | case AArch64::USQADDv1i8: |
| 12436 | case AArch64::USQADDv2i32: |
| 12437 | case AArch64::USQADDv2i64: |
| 12438 | case AArch64::USQADDv4i16: |
| 12439 | case AArch64::USQADDv4i32: |
| 12440 | case AArch64::USQADDv8i16: |
| 12441 | case AArch64::USQADDv8i8: |
| 12442 | case AArch64::XTNv16i8: |
| 12443 | case AArch64::XTNv4i32: |
| 12444 | case AArch64::XTNv8i16: { |
| 12445 | // op: Rd |
| 12446 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12447 | Value |= (op & 0x1f); |
| 12448 | // op: Rn |
| 12449 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12450 | Value |= (op & 0x1f) << 5; |
| 12451 | break; |
| 12452 | } |
| 12453 | case AArch64::ADDHNv2i64_v4i32: |
| 12454 | case AArch64::ADDHNv4i32_v8i16: |
| 12455 | case AArch64::ADDHNv8i16_v16i8: |
| 12456 | case AArch64::BFDOTv4bf16: |
| 12457 | case AArch64::BFDOTv8bf16: |
| 12458 | case AArch64::BFMLALB: |
| 12459 | case AArch64::BFMLALT: |
| 12460 | case AArch64::BFMMLA: |
| 12461 | case AArch64::BIFv16i8: |
| 12462 | case AArch64::BIFv8i8: |
| 12463 | case AArch64::BITv16i8: |
| 12464 | case AArch64::BITv8i8: |
| 12465 | case AArch64::BSLv16i8: |
| 12466 | case AArch64::BSLv8i8: |
| 12467 | case AArch64::FCVTN_F322v16f8: |
| 12468 | case AArch64::FDOTv2f32: |
| 12469 | case AArch64::FDOTv4f16: |
| 12470 | case AArch64::FDOTv4f16_v2f32: |
| 12471 | case AArch64::FDOTv4f32: |
| 12472 | case AArch64::FDOTv8f16: |
| 12473 | case AArch64::FDOTv8f16_v4f32: |
| 12474 | case AArch64::FMLAL2v4f16: |
| 12475 | case AArch64::FMLAL2v8f16: |
| 12476 | case AArch64::FMLALBv16i8_v8f16: |
| 12477 | case AArch64::FMLALLBBv4f32: |
| 12478 | case AArch64::FMLALLBTv4f32: |
| 12479 | case AArch64::FMLALLTBv4f32: |
| 12480 | case AArch64::FMLALLTTv4f32: |
| 12481 | case AArch64::FMLALTv16i8_v8f16: |
| 12482 | case AArch64::FMLALv4f16: |
| 12483 | case AArch64::FMLALv8f16: |
| 12484 | case AArch64::FMLAv2f32: |
| 12485 | case AArch64::FMLAv2f64: |
| 12486 | case AArch64::FMLAv4f16: |
| 12487 | case AArch64::FMLAv4f32: |
| 12488 | case AArch64::FMLAv8f16: |
| 12489 | case AArch64::FMLSL2v4f16: |
| 12490 | case AArch64::FMLSL2v8f16: |
| 12491 | case AArch64::FMLSLv4f16: |
| 12492 | case AArch64::FMLSLv8f16: |
| 12493 | case AArch64::FMLSv2f32: |
| 12494 | case AArch64::FMLSv2f64: |
| 12495 | case AArch64::FMLSv4f16: |
| 12496 | case AArch64::FMLSv4f32: |
| 12497 | case AArch64::FMLSv8f16: |
| 12498 | case AArch64::FMMLAv4f32: |
| 12499 | case AArch64::FMMLAv8f16: |
| 12500 | case AArch64::FMMLAv8f16_v4f32: |
| 12501 | case AArch64::FMMLAv8f16_v8f16: |
| 12502 | case AArch64::MLAv16i8: |
| 12503 | case AArch64::MLAv2i32: |
| 12504 | case AArch64::MLAv4i16: |
| 12505 | case AArch64::MLAv4i32: |
| 12506 | case AArch64::MLAv8i16: |
| 12507 | case AArch64::MLAv8i8: |
| 12508 | case AArch64::MLSv16i8: |
| 12509 | case AArch64::MLSv2i32: |
| 12510 | case AArch64::MLSv4i16: |
| 12511 | case AArch64::MLSv4i32: |
| 12512 | case AArch64::MLSv8i16: |
| 12513 | case AArch64::MLSv8i8: |
| 12514 | case AArch64::RADDHNv2i64_v4i32: |
| 12515 | case AArch64::RADDHNv4i32_v8i16: |
| 12516 | case AArch64::RADDHNv8i16_v16i8: |
| 12517 | case AArch64::RSUBHNv2i64_v4i32: |
| 12518 | case AArch64::RSUBHNv4i32_v8i16: |
| 12519 | case AArch64::RSUBHNv8i16_v16i8: |
| 12520 | case AArch64::SABALv16i8_v8i16: |
| 12521 | case AArch64::SABALv2i32_v2i64: |
| 12522 | case AArch64::SABALv4i16_v4i32: |
| 12523 | case AArch64::SABALv4i32_v2i64: |
| 12524 | case AArch64::SABALv8i16_v4i32: |
| 12525 | case AArch64::SABALv8i8_v8i16: |
| 12526 | case AArch64::SABAv16i8: |
| 12527 | case AArch64::SABAv2i32: |
| 12528 | case AArch64::SABAv4i16: |
| 12529 | case AArch64::SABAv4i32: |
| 12530 | case AArch64::SABAv8i16: |
| 12531 | case AArch64::SABAv8i8: |
| 12532 | case AArch64::SDOTv16i8: |
| 12533 | case AArch64::SDOTv8i8: |
| 12534 | case AArch64::SHA1Crrr: |
| 12535 | case AArch64::SHA1Mrrr: |
| 12536 | case AArch64::SHA1Prrr: |
| 12537 | case AArch64::SHA1SU0rrr: |
| 12538 | case AArch64::SHA256H2rrr: |
| 12539 | case AArch64::SHA256Hrrr: |
| 12540 | case AArch64::SHA256SU1rrr: |
| 12541 | case AArch64::SMLALv16i8_v8i16: |
| 12542 | case AArch64::SMLALv2i32_v2i64: |
| 12543 | case AArch64::SMLALv4i16_v4i32: |
| 12544 | case AArch64::SMLALv4i32_v2i64: |
| 12545 | case AArch64::SMLALv8i16_v4i32: |
| 12546 | case AArch64::SMLALv8i8_v8i16: |
| 12547 | case AArch64::SMLSLv16i8_v8i16: |
| 12548 | case AArch64::SMLSLv2i32_v2i64: |
| 12549 | case AArch64::SMLSLv4i16_v4i32: |
| 12550 | case AArch64::SMLSLv4i32_v2i64: |
| 12551 | case AArch64::SMLSLv8i16_v4i32: |
| 12552 | case AArch64::SMLSLv8i8_v8i16: |
| 12553 | case AArch64::SMMLA: |
| 12554 | case AArch64::SQDMLALi16: |
| 12555 | case AArch64::SQDMLALi32: |
| 12556 | case AArch64::SQDMLALv2i32_v2i64: |
| 12557 | case AArch64::SQDMLALv4i16_v4i32: |
| 12558 | case AArch64::SQDMLALv4i32_v2i64: |
| 12559 | case AArch64::SQDMLALv8i16_v4i32: |
| 12560 | case AArch64::SQDMLSLi16: |
| 12561 | case AArch64::SQDMLSLi32: |
| 12562 | case AArch64::SQDMLSLv2i32_v2i64: |
| 12563 | case AArch64::SQDMLSLv4i16_v4i32: |
| 12564 | case AArch64::SQDMLSLv4i32_v2i64: |
| 12565 | case AArch64::SQDMLSLv8i16_v4i32: |
| 12566 | case AArch64::SQRDMLAHv1i16: |
| 12567 | case AArch64::SQRDMLAHv1i32: |
| 12568 | case AArch64::SQRDMLAHv2i32: |
| 12569 | case AArch64::SQRDMLAHv4i16: |
| 12570 | case AArch64::SQRDMLAHv4i32: |
| 12571 | case AArch64::SQRDMLAHv8i16: |
| 12572 | case AArch64::SQRDMLSHv1i16: |
| 12573 | case AArch64::SQRDMLSHv1i32: |
| 12574 | case AArch64::SQRDMLSHv2i32: |
| 12575 | case AArch64::SQRDMLSHv4i16: |
| 12576 | case AArch64::SQRDMLSHv4i32: |
| 12577 | case AArch64::SQRDMLSHv8i16: |
| 12578 | case AArch64::SUBHNv2i64_v4i32: |
| 12579 | case AArch64::SUBHNv4i32_v8i16: |
| 12580 | case AArch64::SUBHNv8i16_v16i8: |
| 12581 | case AArch64::UABALv16i8_v8i16: |
| 12582 | case AArch64::UABALv2i32_v2i64: |
| 12583 | case AArch64::UABALv4i16_v4i32: |
| 12584 | case AArch64::UABALv4i32_v2i64: |
| 12585 | case AArch64::UABALv8i16_v4i32: |
| 12586 | case AArch64::UABALv8i8_v8i16: |
| 12587 | case AArch64::UABAv16i8: |
| 12588 | case AArch64::UABAv2i32: |
| 12589 | case AArch64::UABAv4i16: |
| 12590 | case AArch64::UABAv4i32: |
| 12591 | case AArch64::UABAv8i16: |
| 12592 | case AArch64::UABAv8i8: |
| 12593 | case AArch64::UDOTv16i8: |
| 12594 | case AArch64::UDOTv8i8: |
| 12595 | case AArch64::UMLALv16i8_v8i16: |
| 12596 | case AArch64::UMLALv2i32_v2i64: |
| 12597 | case AArch64::UMLALv4i16_v4i32: |
| 12598 | case AArch64::UMLALv4i32_v2i64: |
| 12599 | case AArch64::UMLALv8i16_v4i32: |
| 12600 | case AArch64::UMLALv8i8_v8i16: |
| 12601 | case AArch64::UMLSLv16i8_v8i16: |
| 12602 | case AArch64::UMLSLv2i32_v2i64: |
| 12603 | case AArch64::UMLSLv4i16_v4i32: |
| 12604 | case AArch64::UMLSLv4i32_v2i64: |
| 12605 | case AArch64::UMLSLv8i16_v4i32: |
| 12606 | case AArch64::UMLSLv8i8_v8i16: |
| 12607 | case AArch64::UMMLA: |
| 12608 | case AArch64::USDOTv16i8: |
| 12609 | case AArch64::USDOTv8i8: |
| 12610 | case AArch64::USMMLA: { |
| 12611 | // op: Rd |
| 12612 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12613 | Value |= (op & 0x1f); |
| 12614 | // op: Rn |
| 12615 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12616 | Value |= (op & 0x1f) << 5; |
| 12617 | // op: Rm |
| 12618 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12619 | Value |= (op & 0x1f) << 16; |
| 12620 | break; |
| 12621 | } |
| 12622 | case AArch64::FMLAv1i64_indexed: |
| 12623 | case AArch64::FMLAv2i64_indexed: |
| 12624 | case AArch64::FMLSv1i64_indexed: |
| 12625 | case AArch64::FMLSv2i64_indexed: { |
| 12626 | // op: Rd |
| 12627 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12628 | Value |= (op & 0x1f); |
| 12629 | // op: Rn |
| 12630 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12631 | Value |= (op & 0x1f) << 5; |
| 12632 | // op: Rm |
| 12633 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12634 | Value |= (op & 0x1f) << 16; |
| 12635 | // op: idx |
| 12636 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 12637 | Value |= (op & 0x1) << 11; |
| 12638 | break; |
| 12639 | } |
| 12640 | case AArch64::BF16DOTlanev4bf16: |
| 12641 | case AArch64::BF16DOTlanev8bf16: |
| 12642 | case AArch64::FDOTlanev2f32: |
| 12643 | case AArch64::FDOTlanev4f16_v2f32: |
| 12644 | case AArch64::FDOTlanev4f32: |
| 12645 | case AArch64::FDOTlanev8f16_v4f32: |
| 12646 | case AArch64::FMLAv1i32_indexed: |
| 12647 | case AArch64::FMLAv2i32_indexed: |
| 12648 | case AArch64::FMLAv4i32_indexed: |
| 12649 | case AArch64::FMLSv1i32_indexed: |
| 12650 | case AArch64::FMLSv2i32_indexed: |
| 12651 | case AArch64::FMLSv4i32_indexed: |
| 12652 | case AArch64::MLAv2i32_indexed: |
| 12653 | case AArch64::MLAv4i32_indexed: |
| 12654 | case AArch64::MLSv2i32_indexed: |
| 12655 | case AArch64::MLSv4i32_indexed: |
| 12656 | case AArch64::SDOTlanev16i8: |
| 12657 | case AArch64::SDOTlanev8i8: |
| 12658 | case AArch64::SMLALv2i32_indexed: |
| 12659 | case AArch64::SMLALv4i32_indexed: |
| 12660 | case AArch64::SMLSLv2i32_indexed: |
| 12661 | case AArch64::SMLSLv4i32_indexed: |
| 12662 | case AArch64::SQDMLALv1i64_indexed: |
| 12663 | case AArch64::SQDMLALv2i32_indexed: |
| 12664 | case AArch64::SQDMLALv4i32_indexed: |
| 12665 | case AArch64::SQDMLSLv1i64_indexed: |
| 12666 | case AArch64::SQDMLSLv2i32_indexed: |
| 12667 | case AArch64::SQDMLSLv4i32_indexed: |
| 12668 | case AArch64::SQRDMLAHv1i32_indexed: |
| 12669 | case AArch64::SQRDMLAHv2i32_indexed: |
| 12670 | case AArch64::SQRDMLAHv4i32_indexed: |
| 12671 | case AArch64::SQRDMLSHv1i32_indexed: |
| 12672 | case AArch64::SQRDMLSHv2i32_indexed: |
| 12673 | case AArch64::SQRDMLSHv4i32_indexed: |
| 12674 | case AArch64::SUDOTlanev16i8: |
| 12675 | case AArch64::SUDOTlanev8i8: |
| 12676 | case AArch64::UDOTlanev16i8: |
| 12677 | case AArch64::UDOTlanev8i8: |
| 12678 | case AArch64::UMLALv2i32_indexed: |
| 12679 | case AArch64::UMLALv4i32_indexed: |
| 12680 | case AArch64::UMLSLv2i32_indexed: |
| 12681 | case AArch64::UMLSLv4i32_indexed: |
| 12682 | case AArch64::USDOTlanev16i8: |
| 12683 | case AArch64::USDOTlanev8i8: { |
| 12684 | // op: Rd |
| 12685 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12686 | Value |= (op & 0x1f); |
| 12687 | // op: Rn |
| 12688 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12689 | Value |= (op & 0x1f) << 5; |
| 12690 | // op: Rm |
| 12691 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12692 | Value |= (op & 0x1f) << 16; |
| 12693 | // op: idx |
| 12694 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 12695 | Value |= (op & 0x1) << 21; |
| 12696 | Value |= (op & 0x2) << 10; |
| 12697 | break; |
| 12698 | } |
| 12699 | case AArch64::FCMLAv2f32: |
| 12700 | case AArch64::FCMLAv2f64: |
| 12701 | case AArch64::FCMLAv4f16: |
| 12702 | case AArch64::FCMLAv4f32: |
| 12703 | case AArch64::FCMLAv8f16: { |
| 12704 | // op: Rd |
| 12705 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12706 | Value |= (op & 0x1f); |
| 12707 | // op: Rn |
| 12708 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12709 | Value |= (op & 0x1f) << 5; |
| 12710 | // op: Rm |
| 12711 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12712 | Value |= (op & 0x1f) << 16; |
| 12713 | // op: rot |
| 12714 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 12715 | Value |= (op & 0x3) << 11; |
| 12716 | break; |
| 12717 | } |
| 12718 | case AArch64::FCMLAv4f32_indexed: { |
| 12719 | // op: Rd |
| 12720 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12721 | Value |= (op & 0x1f); |
| 12722 | // op: Rn |
| 12723 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12724 | Value |= (op & 0x1f) << 5; |
| 12725 | // op: Rm |
| 12726 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12727 | Value |= (op & 0x1f) << 16; |
| 12728 | // op: rot |
| 12729 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 12730 | Value |= (op & 0x3) << 13; |
| 12731 | // op: idx |
| 12732 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 12733 | Value |= (op & 0x1) << 11; |
| 12734 | break; |
| 12735 | } |
| 12736 | case AArch64::FCMLAv4f16_indexed: { |
| 12737 | // op: Rd |
| 12738 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12739 | Value |= (op & 0x1f); |
| 12740 | // op: Rn |
| 12741 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12742 | Value |= (op & 0x1f) << 5; |
| 12743 | // op: Rm |
| 12744 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12745 | Value |= (op & 0x1f) << 16; |
| 12746 | // op: rot |
| 12747 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 12748 | Value |= (op & 0x3) << 13; |
| 12749 | // op: idx |
| 12750 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 12751 | Value |= (op & 0x1) << 21; |
| 12752 | break; |
| 12753 | } |
| 12754 | case AArch64::FCMLAv8f16_indexed: { |
| 12755 | // op: Rd |
| 12756 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12757 | Value |= (op & 0x1f); |
| 12758 | // op: Rn |
| 12759 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12760 | Value |= (op & 0x1f) << 5; |
| 12761 | // op: Rm |
| 12762 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12763 | Value |= (op & 0x1f) << 16; |
| 12764 | // op: rot |
| 12765 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 12766 | Value |= (op & 0x3) << 13; |
| 12767 | // op: idx |
| 12768 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 12769 | Value |= (op & 0x1) << 21; |
| 12770 | Value |= (op & 0x2) << 10; |
| 12771 | break; |
| 12772 | } |
| 12773 | case AArch64::FMLALBlanev8f16: |
| 12774 | case AArch64::FMLALLBBlanev4f32: |
| 12775 | case AArch64::FMLALLBTlanev4f32: |
| 12776 | case AArch64::FMLALLTBlanev4f32: |
| 12777 | case AArch64::FMLALLTTlanev4f32: |
| 12778 | case AArch64::FMLALTlanev8f16: { |
| 12779 | // op: Rd |
| 12780 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12781 | Value |= (op & 0x1f); |
| 12782 | // op: Rn |
| 12783 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12784 | Value |= (op & 0x1f) << 5; |
| 12785 | // op: Rm |
| 12786 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12787 | Value |= (op & 0x7) << 16; |
| 12788 | // op: idx |
| 12789 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 12790 | Value |= (op & 0x7) << 19; |
| 12791 | Value |= (op & 0x8) << 8; |
| 12792 | break; |
| 12793 | } |
| 12794 | case AArch64::BFMLALBIdx: |
| 12795 | case AArch64::BFMLALTIdx: |
| 12796 | case AArch64::FDOTlanev4f16: |
| 12797 | case AArch64::FDOTlanev8f16: |
| 12798 | case AArch64::FMLAL2lanev4f16: |
| 12799 | case AArch64::FMLAL2lanev8f16: |
| 12800 | case AArch64::FMLALlanev4f16: |
| 12801 | case AArch64::FMLALlanev8f16: |
| 12802 | case AArch64::FMLAv1i16_indexed: |
| 12803 | case AArch64::FMLAv4i16_indexed: |
| 12804 | case AArch64::FMLAv8i16_indexed: |
| 12805 | case AArch64::FMLSL2lanev4f16: |
| 12806 | case AArch64::FMLSL2lanev8f16: |
| 12807 | case AArch64::FMLSLlanev4f16: |
| 12808 | case AArch64::FMLSLlanev8f16: |
| 12809 | case AArch64::FMLSv1i16_indexed: |
| 12810 | case AArch64::FMLSv4i16_indexed: |
| 12811 | case AArch64::FMLSv8i16_indexed: |
| 12812 | case AArch64::MLAv4i16_indexed: |
| 12813 | case AArch64::MLAv8i16_indexed: |
| 12814 | case AArch64::MLSv4i16_indexed: |
| 12815 | case AArch64::MLSv8i16_indexed: |
| 12816 | case AArch64::SMLALv4i16_indexed: |
| 12817 | case AArch64::SMLALv8i16_indexed: |
| 12818 | case AArch64::SMLSLv4i16_indexed: |
| 12819 | case AArch64::SMLSLv8i16_indexed: |
| 12820 | case AArch64::SQDMLALv1i32_indexed: |
| 12821 | case AArch64::SQDMLALv4i16_indexed: |
| 12822 | case AArch64::SQDMLALv8i16_indexed: |
| 12823 | case AArch64::SQDMLSLv1i32_indexed: |
| 12824 | case AArch64::SQDMLSLv4i16_indexed: |
| 12825 | case AArch64::SQDMLSLv8i16_indexed: |
| 12826 | case AArch64::SQRDMLAHv1i16_indexed: |
| 12827 | case AArch64::SQRDMLAHv4i16_indexed: |
| 12828 | case AArch64::SQRDMLAHv8i16_indexed: |
| 12829 | case AArch64::SQRDMLSHv1i16_indexed: |
| 12830 | case AArch64::SQRDMLSHv4i16_indexed: |
| 12831 | case AArch64::SQRDMLSHv8i16_indexed: |
| 12832 | case AArch64::UMLALv4i16_indexed: |
| 12833 | case AArch64::UMLALv8i16_indexed: |
| 12834 | case AArch64::UMLSLv4i16_indexed: |
| 12835 | case AArch64::UMLSLv8i16_indexed: { |
| 12836 | // op: Rd |
| 12837 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12838 | Value |= (op & 0x1f); |
| 12839 | // op: Rn |
| 12840 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12841 | Value |= (op & 0x1f) << 5; |
| 12842 | // op: Rm |
| 12843 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 12844 | Value |= (op & 0xf) << 16; |
| 12845 | // op: idx |
| 12846 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 12847 | Value |= (op & 0x3) << 20; |
| 12848 | Value |= (op & 0x4) << 9; |
| 12849 | break; |
| 12850 | } |
| 12851 | case AArch64::SLIv4i16_shift: |
| 12852 | case AArch64::SLIv8i16_shift: { |
| 12853 | // op: Rd |
| 12854 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12855 | Value |= (op & 0x1f); |
| 12856 | // op: Rn |
| 12857 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12858 | Value |= (op & 0x1f) << 5; |
| 12859 | // op: imm |
| 12860 | op = getVecShiftL16OpValue(MI, OpIdx: 3, Fixups, STI); |
| 12861 | Value |= (op & 0xf) << 16; |
| 12862 | break; |
| 12863 | } |
| 12864 | case AArch64::SLIv2i32_shift: |
| 12865 | case AArch64::SLIv4i32_shift: { |
| 12866 | // op: Rd |
| 12867 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12868 | Value |= (op & 0x1f); |
| 12869 | // op: Rn |
| 12870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12871 | Value |= (op & 0x1f) << 5; |
| 12872 | // op: imm |
| 12873 | op = getVecShiftL32OpValue(MI, OpIdx: 3, Fixups, STI); |
| 12874 | Value |= (op & 0x1f) << 16; |
| 12875 | break; |
| 12876 | } |
| 12877 | case AArch64::SLId: |
| 12878 | case AArch64::SLIv2i64_shift: { |
| 12879 | // op: Rd |
| 12880 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12881 | Value |= (op & 0x1f); |
| 12882 | // op: Rn |
| 12883 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12884 | Value |= (op & 0x1f) << 5; |
| 12885 | // op: imm |
| 12886 | op = getVecShiftL64OpValue(MI, OpIdx: 3, Fixups, STI); |
| 12887 | Value |= (op & 0x3f) << 16; |
| 12888 | break; |
| 12889 | } |
| 12890 | case AArch64::SLIv16i8_shift: |
| 12891 | case AArch64::SLIv8i8_shift: { |
| 12892 | // op: Rd |
| 12893 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12894 | Value |= (op & 0x1f); |
| 12895 | // op: Rn |
| 12896 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12897 | Value |= (op & 0x1f) << 5; |
| 12898 | // op: imm |
| 12899 | op = getVecShiftL8OpValue(MI, OpIdx: 3, Fixups, STI); |
| 12900 | Value |= (op & 0x7) << 16; |
| 12901 | break; |
| 12902 | } |
| 12903 | case AArch64::RSHRNv16i8_shift: |
| 12904 | case AArch64::SHRNv16i8_shift: |
| 12905 | case AArch64::SQRSHRNv16i8_shift: |
| 12906 | case AArch64::SQRSHRUNv16i8_shift: |
| 12907 | case AArch64::SQSHRNv16i8_shift: |
| 12908 | case AArch64::SQSHRUNv16i8_shift: |
| 12909 | case AArch64::UQRSHRNv16i8_shift: |
| 12910 | case AArch64::UQSHRNv16i8_shift: { |
| 12911 | // op: Rd |
| 12912 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12913 | Value |= (op & 0x1f); |
| 12914 | // op: Rn |
| 12915 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12916 | Value |= (op & 0x1f) << 5; |
| 12917 | // op: imm |
| 12918 | op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI); |
| 12919 | Value |= (op & 0x7) << 16; |
| 12920 | break; |
| 12921 | } |
| 12922 | case AArch64::SRIv4i16_shift: |
| 12923 | case AArch64::SRIv8i16_shift: |
| 12924 | case AArch64::SRSRAv4i16_shift: |
| 12925 | case AArch64::SRSRAv8i16_shift: |
| 12926 | case AArch64::SSRAv4i16_shift: |
| 12927 | case AArch64::SSRAv8i16_shift: |
| 12928 | case AArch64::URSRAv4i16_shift: |
| 12929 | case AArch64::URSRAv8i16_shift: |
| 12930 | case AArch64::USRAv4i16_shift: |
| 12931 | case AArch64::USRAv8i16_shift: { |
| 12932 | // op: Rd |
| 12933 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12934 | Value |= (op & 0x1f); |
| 12935 | // op: Rn |
| 12936 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12937 | Value |= (op & 0x1f) << 5; |
| 12938 | // op: imm |
| 12939 | op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI); |
| 12940 | Value |= (op & 0xf) << 16; |
| 12941 | break; |
| 12942 | } |
| 12943 | case AArch64::SRIv2i32_shift: |
| 12944 | case AArch64::SRIv4i32_shift: |
| 12945 | case AArch64::SRSRAv2i32_shift: |
| 12946 | case AArch64::SRSRAv4i32_shift: |
| 12947 | case AArch64::SSRAv2i32_shift: |
| 12948 | case AArch64::SSRAv4i32_shift: |
| 12949 | case AArch64::URSRAv2i32_shift: |
| 12950 | case AArch64::URSRAv4i32_shift: |
| 12951 | case AArch64::USRAv2i32_shift: |
| 12952 | case AArch64::USRAv4i32_shift: { |
| 12953 | // op: Rd |
| 12954 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12955 | Value |= (op & 0x1f); |
| 12956 | // op: Rn |
| 12957 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12958 | Value |= (op & 0x1f) << 5; |
| 12959 | // op: imm |
| 12960 | op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI); |
| 12961 | Value |= (op & 0x1f) << 16; |
| 12962 | break; |
| 12963 | } |
| 12964 | case AArch64::RSHRNv8i16_shift: |
| 12965 | case AArch64::SHRNv8i16_shift: |
| 12966 | case AArch64::SQRSHRNv8i16_shift: |
| 12967 | case AArch64::SQRSHRUNv8i16_shift: |
| 12968 | case AArch64::SQSHRNv8i16_shift: |
| 12969 | case AArch64::SQSHRUNv8i16_shift: |
| 12970 | case AArch64::UQRSHRNv8i16_shift: |
| 12971 | case AArch64::UQSHRNv8i16_shift: { |
| 12972 | // op: Rd |
| 12973 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12974 | Value |= (op & 0x1f); |
| 12975 | // op: Rn |
| 12976 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12977 | Value |= (op & 0x1f) << 5; |
| 12978 | // op: imm |
| 12979 | op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI); |
| 12980 | Value |= (op & 0xf) << 16; |
| 12981 | break; |
| 12982 | } |
| 12983 | case AArch64::RSHRNv4i32_shift: |
| 12984 | case AArch64::SHRNv4i32_shift: |
| 12985 | case AArch64::SQRSHRNv4i32_shift: |
| 12986 | case AArch64::SQRSHRUNv4i32_shift: |
| 12987 | case AArch64::SQSHRNv4i32_shift: |
| 12988 | case AArch64::SQSHRUNv4i32_shift: |
| 12989 | case AArch64::UQRSHRNv4i32_shift: |
| 12990 | case AArch64::UQSHRNv4i32_shift: { |
| 12991 | // op: Rd |
| 12992 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 12993 | Value |= (op & 0x1f); |
| 12994 | // op: Rn |
| 12995 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 12996 | Value |= (op & 0x1f) << 5; |
| 12997 | // op: imm |
| 12998 | op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI); |
| 12999 | Value |= (op & 0x1f) << 16; |
| 13000 | break; |
| 13001 | } |
| 13002 | case AArch64::SRId: |
| 13003 | case AArch64::SRIv2i64_shift: |
| 13004 | case AArch64::SRSRAd: |
| 13005 | case AArch64::SRSRAv2i64_shift: |
| 13006 | case AArch64::SSRAd: |
| 13007 | case AArch64::SSRAv2i64_shift: |
| 13008 | case AArch64::URSRAd: |
| 13009 | case AArch64::URSRAv2i64_shift: |
| 13010 | case AArch64::USRAd: |
| 13011 | case AArch64::USRAv2i64_shift: { |
| 13012 | // op: Rd |
| 13013 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13014 | Value |= (op & 0x1f); |
| 13015 | // op: Rn |
| 13016 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13017 | Value |= (op & 0x1f) << 5; |
| 13018 | // op: imm |
| 13019 | op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI); |
| 13020 | Value |= (op & 0x3f) << 16; |
| 13021 | break; |
| 13022 | } |
| 13023 | case AArch64::SRIv16i8_shift: |
| 13024 | case AArch64::SRIv8i8_shift: |
| 13025 | case AArch64::SRSRAv16i8_shift: |
| 13026 | case AArch64::SRSRAv8i8_shift: |
| 13027 | case AArch64::SSRAv16i8_shift: |
| 13028 | case AArch64::SSRAv8i8_shift: |
| 13029 | case AArch64::URSRAv16i8_shift: |
| 13030 | case AArch64::URSRAv8i8_shift: |
| 13031 | case AArch64::USRAv16i8_shift: |
| 13032 | case AArch64::USRAv8i8_shift: { |
| 13033 | // op: Rd |
| 13034 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13035 | Value |= (op & 0x1f); |
| 13036 | // op: Rn |
| 13037 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13038 | Value |= (op & 0x1f) << 5; |
| 13039 | // op: imm |
| 13040 | op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI); |
| 13041 | Value |= (op & 0x7) << 16; |
| 13042 | break; |
| 13043 | } |
| 13044 | case AArch64::INSvi64gpr: { |
| 13045 | // op: Rd |
| 13046 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13047 | Value |= (op & 0x1f); |
| 13048 | // op: Rn |
| 13049 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13050 | Value |= (op & 0x1f) << 5; |
| 13051 | // op: idx |
| 13052 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13053 | Value |= (op & 0x1) << 20; |
| 13054 | break; |
| 13055 | } |
| 13056 | case AArch64::INSvi64lane: { |
| 13057 | // op: Rd |
| 13058 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13059 | Value |= (op & 0x1f); |
| 13060 | // op: Rn |
| 13061 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13062 | Value |= (op & 0x1f) << 5; |
| 13063 | // op: idx |
| 13064 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13065 | Value |= (op & 0x1) << 20; |
| 13066 | // op: idx2 |
| 13067 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13068 | Value |= (op & 0x1) << 14; |
| 13069 | break; |
| 13070 | } |
| 13071 | case AArch64::INSvi32gpr: { |
| 13072 | // op: Rd |
| 13073 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13074 | Value |= (op & 0x1f); |
| 13075 | // op: Rn |
| 13076 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13077 | Value |= (op & 0x1f) << 5; |
| 13078 | // op: idx |
| 13079 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13080 | Value |= (op & 0x3) << 19; |
| 13081 | break; |
| 13082 | } |
| 13083 | case AArch64::INSvi32lane: { |
| 13084 | // op: Rd |
| 13085 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13086 | Value |= (op & 0x1f); |
| 13087 | // op: Rn |
| 13088 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13089 | Value |= (op & 0x1f) << 5; |
| 13090 | // op: idx |
| 13091 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13092 | Value |= (op & 0x3) << 19; |
| 13093 | // op: idx2 |
| 13094 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13095 | Value |= (op & 0x3) << 13; |
| 13096 | break; |
| 13097 | } |
| 13098 | case AArch64::INSvi16gpr: { |
| 13099 | // op: Rd |
| 13100 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13101 | Value |= (op & 0x1f); |
| 13102 | // op: Rn |
| 13103 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13104 | Value |= (op & 0x1f) << 5; |
| 13105 | // op: idx |
| 13106 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13107 | Value |= (op & 0x7) << 18; |
| 13108 | break; |
| 13109 | } |
| 13110 | case AArch64::INSvi16lane: { |
| 13111 | // op: Rd |
| 13112 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13113 | Value |= (op & 0x1f); |
| 13114 | // op: Rn |
| 13115 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13116 | Value |= (op & 0x1f) << 5; |
| 13117 | // op: idx |
| 13118 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13119 | Value |= (op & 0x7) << 18; |
| 13120 | // op: idx2 |
| 13121 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13122 | Value |= (op & 0x7) << 12; |
| 13123 | break; |
| 13124 | } |
| 13125 | case AArch64::INSvi8gpr: { |
| 13126 | // op: Rd |
| 13127 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13128 | Value |= (op & 0x1f); |
| 13129 | // op: Rn |
| 13130 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13131 | Value |= (op & 0x1f) << 5; |
| 13132 | // op: idx |
| 13133 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13134 | Value |= (op & 0xf) << 17; |
| 13135 | break; |
| 13136 | } |
| 13137 | case AArch64::INSvi8lane: { |
| 13138 | // op: Rd |
| 13139 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13140 | Value |= (op & 0x1f); |
| 13141 | // op: Rn |
| 13142 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13143 | Value |= (op & 0x1f) << 5; |
| 13144 | // op: idx |
| 13145 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13146 | Value |= (op & 0xf) << 17; |
| 13147 | // op: idx2 |
| 13148 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13149 | Value |= (op & 0xf) << 11; |
| 13150 | break; |
| 13151 | } |
| 13152 | case AArch64::BICv4i16: |
| 13153 | case AArch64::BICv8i16: |
| 13154 | case AArch64::ORRv4i16: |
| 13155 | case AArch64::ORRv8i16: { |
| 13156 | // op: Rd |
| 13157 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13158 | Value |= (op & 0x1f); |
| 13159 | // op: imm8 |
| 13160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13161 | Value |= (op & 0xe0) << 11; |
| 13162 | Value |= (op & 0x1f) << 5; |
| 13163 | // op: shift |
| 13164 | op = getVecShifterOpValue(MI, OpIdx: 3, Fixups, STI); |
| 13165 | Value |= (op & 0x1) << 13; |
| 13166 | break; |
| 13167 | } |
| 13168 | case AArch64::BICv2i32: |
| 13169 | case AArch64::BICv4i32: |
| 13170 | case AArch64::ORRv2i32: |
| 13171 | case AArch64::ORRv4i32: { |
| 13172 | // op: Rd |
| 13173 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13174 | Value |= (op & 0x1f); |
| 13175 | // op: imm8 |
| 13176 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13177 | Value |= (op & 0xe0) << 11; |
| 13178 | Value |= (op & 0x1f) << 5; |
| 13179 | // op: shift |
| 13180 | op = getVecShifterOpValue(MI, OpIdx: 3, Fixups, STI); |
| 13181 | Value |= (op & 0x3) << 13; |
| 13182 | break; |
| 13183 | } |
| 13184 | case AArch64::SETGOE: |
| 13185 | case AArch64::SETGOEN: |
| 13186 | case AArch64::SETGOET: |
| 13187 | case AArch64::SETGOETN: |
| 13188 | case AArch64::SETGOM: |
| 13189 | case AArch64::SETGOMN: |
| 13190 | case AArch64::SETGOMT: |
| 13191 | case AArch64::SETGOMTN: |
| 13192 | case AArch64::SETGOP: |
| 13193 | case AArch64::SETGOPN: |
| 13194 | case AArch64::SETGOPT: |
| 13195 | case AArch64::SETGOPTN: { |
| 13196 | // op: Rd |
| 13197 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13198 | Value |= (op & 0x1f); |
| 13199 | // op: Rn |
| 13200 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13201 | Value |= (op & 0x1f) << 5; |
| 13202 | break; |
| 13203 | } |
| 13204 | case AArch64::MOPSSETGE: |
| 13205 | case AArch64::MOPSSETGEN: |
| 13206 | case AArch64::MOPSSETGET: |
| 13207 | case AArch64::MOPSSETGETN: |
| 13208 | case AArch64::SETE: |
| 13209 | case AArch64::SETEN: |
| 13210 | case AArch64::SETET: |
| 13211 | case AArch64::SETETN: |
| 13212 | case AArch64::SETGM: |
| 13213 | case AArch64::SETGMN: |
| 13214 | case AArch64::SETGMT: |
| 13215 | case AArch64::SETGMTN: |
| 13216 | case AArch64::SETGP: |
| 13217 | case AArch64::SETGPN: |
| 13218 | case AArch64::SETGPT: |
| 13219 | case AArch64::SETGPTN: |
| 13220 | case AArch64::SETM: |
| 13221 | case AArch64::SETMN: |
| 13222 | case AArch64::SETMT: |
| 13223 | case AArch64::SETMTN: |
| 13224 | case AArch64::SETP: |
| 13225 | case AArch64::SETPN: |
| 13226 | case AArch64::SETPT: |
| 13227 | case AArch64::SETPTN: { |
| 13228 | // op: Rd |
| 13229 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13230 | Value |= (op & 0x1f); |
| 13231 | // op: Rn |
| 13232 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13233 | Value |= (op & 0x1f) << 5; |
| 13234 | // op: Rm |
| 13235 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13236 | Value |= (op & 0x1f) << 16; |
| 13237 | break; |
| 13238 | } |
| 13239 | case AArch64::CPYE: |
| 13240 | case AArch64::CPYEN: |
| 13241 | case AArch64::CPYERN: |
| 13242 | case AArch64::CPYERT: |
| 13243 | case AArch64::CPYERTN: |
| 13244 | case AArch64::CPYERTRN: |
| 13245 | case AArch64::CPYERTWN: |
| 13246 | case AArch64::CPYET: |
| 13247 | case AArch64::CPYETN: |
| 13248 | case AArch64::CPYETRN: |
| 13249 | case AArch64::CPYETWN: |
| 13250 | case AArch64::CPYEWN: |
| 13251 | case AArch64::CPYEWT: |
| 13252 | case AArch64::CPYEWTN: |
| 13253 | case AArch64::CPYEWTRN: |
| 13254 | case AArch64::CPYEWTWN: |
| 13255 | case AArch64::CPYFE: |
| 13256 | case AArch64::CPYFEN: |
| 13257 | case AArch64::CPYFERN: |
| 13258 | case AArch64::CPYFERT: |
| 13259 | case AArch64::CPYFERTN: |
| 13260 | case AArch64::CPYFERTRN: |
| 13261 | case AArch64::CPYFERTWN: |
| 13262 | case AArch64::CPYFET: |
| 13263 | case AArch64::CPYFETN: |
| 13264 | case AArch64::CPYFETRN: |
| 13265 | case AArch64::CPYFETWN: |
| 13266 | case AArch64::CPYFEWN: |
| 13267 | case AArch64::CPYFEWT: |
| 13268 | case AArch64::CPYFEWTN: |
| 13269 | case AArch64::CPYFEWTRN: |
| 13270 | case AArch64::CPYFEWTWN: |
| 13271 | case AArch64::CPYFM: |
| 13272 | case AArch64::CPYFMN: |
| 13273 | case AArch64::CPYFMRN: |
| 13274 | case AArch64::CPYFMRT: |
| 13275 | case AArch64::CPYFMRTN: |
| 13276 | case AArch64::CPYFMRTRN: |
| 13277 | case AArch64::CPYFMRTWN: |
| 13278 | case AArch64::CPYFMT: |
| 13279 | case AArch64::CPYFMTN: |
| 13280 | case AArch64::CPYFMTRN: |
| 13281 | case AArch64::CPYFMTWN: |
| 13282 | case AArch64::CPYFMWN: |
| 13283 | case AArch64::CPYFMWT: |
| 13284 | case AArch64::CPYFMWTN: |
| 13285 | case AArch64::CPYFMWTRN: |
| 13286 | case AArch64::CPYFMWTWN: |
| 13287 | case AArch64::CPYFP: |
| 13288 | case AArch64::CPYFPN: |
| 13289 | case AArch64::CPYFPRN: |
| 13290 | case AArch64::CPYFPRT: |
| 13291 | case AArch64::CPYFPRTN: |
| 13292 | case AArch64::CPYFPRTRN: |
| 13293 | case AArch64::CPYFPRTWN: |
| 13294 | case AArch64::CPYFPT: |
| 13295 | case AArch64::CPYFPTN: |
| 13296 | case AArch64::CPYFPTRN: |
| 13297 | case AArch64::CPYFPTWN: |
| 13298 | case AArch64::CPYFPWN: |
| 13299 | case AArch64::CPYFPWT: |
| 13300 | case AArch64::CPYFPWTN: |
| 13301 | case AArch64::CPYFPWTRN: |
| 13302 | case AArch64::CPYFPWTWN: |
| 13303 | case AArch64::CPYM: |
| 13304 | case AArch64::CPYMN: |
| 13305 | case AArch64::CPYMRN: |
| 13306 | case AArch64::CPYMRT: |
| 13307 | case AArch64::CPYMRTN: |
| 13308 | case AArch64::CPYMRTRN: |
| 13309 | case AArch64::CPYMRTWN: |
| 13310 | case AArch64::CPYMT: |
| 13311 | case AArch64::CPYMTN: |
| 13312 | case AArch64::CPYMTRN: |
| 13313 | case AArch64::CPYMTWN: |
| 13314 | case AArch64::CPYMWN: |
| 13315 | case AArch64::CPYMWT: |
| 13316 | case AArch64::CPYMWTN: |
| 13317 | case AArch64::CPYMWTRN: |
| 13318 | case AArch64::CPYMWTWN: |
| 13319 | case AArch64::CPYP: |
| 13320 | case AArch64::CPYPN: |
| 13321 | case AArch64::CPYPRN: |
| 13322 | case AArch64::CPYPRT: |
| 13323 | case AArch64::CPYPRTN: |
| 13324 | case AArch64::CPYPRTRN: |
| 13325 | case AArch64::CPYPRTWN: |
| 13326 | case AArch64::CPYPT: |
| 13327 | case AArch64::CPYPTN: |
| 13328 | case AArch64::CPYPTRN: |
| 13329 | case AArch64::CPYPTWN: |
| 13330 | case AArch64::CPYPWN: |
| 13331 | case AArch64::CPYPWT: |
| 13332 | case AArch64::CPYPWTN: |
| 13333 | case AArch64::CPYPWTRN: |
| 13334 | case AArch64::CPYPWTWN: { |
| 13335 | // op: Rd |
| 13336 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13337 | Value |= (op & 0x1f); |
| 13338 | // op: Rs |
| 13339 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13340 | Value |= (op & 0x1f) << 16; |
| 13341 | // op: Rn |
| 13342 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13343 | Value |= (op & 0x1f) << 5; |
| 13344 | break; |
| 13345 | } |
| 13346 | case AArch64::DECP_XP_B: |
| 13347 | case AArch64::DECP_XP_D: |
| 13348 | case AArch64::DECP_XP_H: |
| 13349 | case AArch64::DECP_XP_S: |
| 13350 | case AArch64::INCP_XP_B: |
| 13351 | case AArch64::INCP_XP_D: |
| 13352 | case AArch64::INCP_XP_H: |
| 13353 | case AArch64::INCP_XP_S: |
| 13354 | case AArch64::SQDECP_XPWd_B: |
| 13355 | case AArch64::SQDECP_XPWd_D: |
| 13356 | case AArch64::SQDECP_XPWd_H: |
| 13357 | case AArch64::SQDECP_XPWd_S: |
| 13358 | case AArch64::SQDECP_XP_B: |
| 13359 | case AArch64::SQDECP_XP_D: |
| 13360 | case AArch64::SQDECP_XP_H: |
| 13361 | case AArch64::SQDECP_XP_S: |
| 13362 | case AArch64::SQINCP_XPWd_B: |
| 13363 | case AArch64::SQINCP_XPWd_D: |
| 13364 | case AArch64::SQINCP_XPWd_H: |
| 13365 | case AArch64::SQINCP_XPWd_S: |
| 13366 | case AArch64::SQINCP_XP_B: |
| 13367 | case AArch64::SQINCP_XP_D: |
| 13368 | case AArch64::SQINCP_XP_H: |
| 13369 | case AArch64::SQINCP_XP_S: |
| 13370 | case AArch64::UQDECP_WP_B: |
| 13371 | case AArch64::UQDECP_WP_D: |
| 13372 | case AArch64::UQDECP_WP_H: |
| 13373 | case AArch64::UQDECP_WP_S: |
| 13374 | case AArch64::UQDECP_XP_B: |
| 13375 | case AArch64::UQDECP_XP_D: |
| 13376 | case AArch64::UQDECP_XP_H: |
| 13377 | case AArch64::UQDECP_XP_S: |
| 13378 | case AArch64::UQINCP_WP_B: |
| 13379 | case AArch64::UQINCP_WP_D: |
| 13380 | case AArch64::UQINCP_WP_H: |
| 13381 | case AArch64::UQINCP_WP_S: |
| 13382 | case AArch64::UQINCP_XP_B: |
| 13383 | case AArch64::UQINCP_XP_D: |
| 13384 | case AArch64::UQINCP_XP_H: |
| 13385 | case AArch64::UQINCP_XP_S: { |
| 13386 | // op: Rdn |
| 13387 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13388 | Value |= (op & 0x1f); |
| 13389 | // op: Pg |
| 13390 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13391 | Value |= (op & 0xf) << 5; |
| 13392 | break; |
| 13393 | } |
| 13394 | case AArch64::DECB_XPiI: |
| 13395 | case AArch64::DECD_XPiI: |
| 13396 | case AArch64::DECH_XPiI: |
| 13397 | case AArch64::DECW_XPiI: |
| 13398 | case AArch64::INCB_XPiI: |
| 13399 | case AArch64::INCD_XPiI: |
| 13400 | case AArch64::INCH_XPiI: |
| 13401 | case AArch64::INCW_XPiI: |
| 13402 | case AArch64::SQDECB_XPiI: |
| 13403 | case AArch64::SQDECB_XPiWdI: |
| 13404 | case AArch64::SQDECD_XPiI: |
| 13405 | case AArch64::SQDECD_XPiWdI: |
| 13406 | case AArch64::SQDECH_XPiI: |
| 13407 | case AArch64::SQDECH_XPiWdI: |
| 13408 | case AArch64::SQDECW_XPiI: |
| 13409 | case AArch64::SQDECW_XPiWdI: |
| 13410 | case AArch64::SQINCB_XPiI: |
| 13411 | case AArch64::SQINCB_XPiWdI: |
| 13412 | case AArch64::SQINCD_XPiI: |
| 13413 | case AArch64::SQINCD_XPiWdI: |
| 13414 | case AArch64::SQINCH_XPiI: |
| 13415 | case AArch64::SQINCH_XPiWdI: |
| 13416 | case AArch64::SQINCW_XPiI: |
| 13417 | case AArch64::SQINCW_XPiWdI: |
| 13418 | case AArch64::UQDECB_WPiI: |
| 13419 | case AArch64::UQDECB_XPiI: |
| 13420 | case AArch64::UQDECD_WPiI: |
| 13421 | case AArch64::UQDECD_XPiI: |
| 13422 | case AArch64::UQDECH_WPiI: |
| 13423 | case AArch64::UQDECH_XPiI: |
| 13424 | case AArch64::UQDECW_WPiI: |
| 13425 | case AArch64::UQDECW_XPiI: |
| 13426 | case AArch64::UQINCB_WPiI: |
| 13427 | case AArch64::UQINCB_XPiI: |
| 13428 | case AArch64::UQINCD_WPiI: |
| 13429 | case AArch64::UQINCD_XPiI: |
| 13430 | case AArch64::UQINCH_WPiI: |
| 13431 | case AArch64::UQINCH_XPiI: |
| 13432 | case AArch64::UQINCW_WPiI: |
| 13433 | case AArch64::UQINCW_XPiI: { |
| 13434 | // op: Rdn |
| 13435 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13436 | Value |= (op & 0x1f); |
| 13437 | // op: pattern |
| 13438 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13439 | Value |= (op & 0x1f) << 5; |
| 13440 | // op: imm4 |
| 13441 | op = getSVEIncDecImm(MI, OpIdx: 3, Fixups, STI); |
| 13442 | Value |= (op & 0xf) << 16; |
| 13443 | break; |
| 13444 | } |
| 13445 | case AArch64::RETAASPPCr: |
| 13446 | case AArch64::RETABSPPCr: { |
| 13447 | // op: Rm |
| 13448 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13449 | Value |= (op & 0x1f); |
| 13450 | break; |
| 13451 | } |
| 13452 | case AArch64::CTERMEQ_WW: |
| 13453 | case AArch64::CTERMEQ_XX: |
| 13454 | case AArch64::CTERMNE_WW: |
| 13455 | case AArch64::CTERMNE_XX: |
| 13456 | case AArch64::FCMPDrr: |
| 13457 | case AArch64::FCMPEDrr: |
| 13458 | case AArch64::FCMPEHrr: |
| 13459 | case AArch64::FCMPESrr: |
| 13460 | case AArch64::FCMPHrr: |
| 13461 | case AArch64::FCMPSrr: { |
| 13462 | // op: Rm |
| 13463 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13464 | Value |= (op & 0x1f) << 16; |
| 13465 | // op: Rn |
| 13466 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13467 | Value |= (op & 0x1f) << 5; |
| 13468 | break; |
| 13469 | } |
| 13470 | case AArch64::CBBEQWrr: |
| 13471 | case AArch64::CBBGEWrr: |
| 13472 | case AArch64::CBBGTWrr: |
| 13473 | case AArch64::CBBHIWrr: |
| 13474 | case AArch64::CBBHSWrr: |
| 13475 | case AArch64::CBBNEWrr: |
| 13476 | case AArch64::CBEQWrr: |
| 13477 | case AArch64::CBEQXrr: |
| 13478 | case AArch64::CBGEWrr: |
| 13479 | case AArch64::CBGEXrr: |
| 13480 | case AArch64::CBGTWrr: |
| 13481 | case AArch64::CBGTXrr: |
| 13482 | case AArch64::CBHEQWrr: |
| 13483 | case AArch64::CBHGEWrr: |
| 13484 | case AArch64::CBHGTWrr: |
| 13485 | case AArch64::CBHHIWrr: |
| 13486 | case AArch64::CBHHSWrr: |
| 13487 | case AArch64::CBHIWrr: |
| 13488 | case AArch64::CBHIXrr: |
| 13489 | case AArch64::CBHNEWrr: |
| 13490 | case AArch64::CBHSWrr: |
| 13491 | case AArch64::CBHSXrr: |
| 13492 | case AArch64::CBNEWrr: |
| 13493 | case AArch64::CBNEXrr: { |
| 13494 | // op: Rm |
| 13495 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13496 | Value |= (op & 0x1f) << 16; |
| 13497 | // op: Rt |
| 13498 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13499 | Value |= (op & 0x1f); |
| 13500 | // op: target |
| 13501 | op = getCondCompBranchTargetOpValue(MI, OpIdx: 2, Fixups, STI); |
| 13502 | Value |= (op & 0x1ff) << 5; |
| 13503 | break; |
| 13504 | } |
| 13505 | case AArch64::INDEX_IR_B: |
| 13506 | case AArch64::INDEX_IR_D: |
| 13507 | case AArch64::INDEX_IR_H: |
| 13508 | case AArch64::INDEX_IR_S: { |
| 13509 | // op: Rm |
| 13510 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13511 | Value |= (op & 0x1f) << 16; |
| 13512 | // op: Zd |
| 13513 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13514 | Value |= (op & 0x1f); |
| 13515 | // op: imm5 |
| 13516 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13517 | Value |= (op & 0x1f) << 5; |
| 13518 | break; |
| 13519 | } |
| 13520 | case AArch64::INSR_ZR_B: |
| 13521 | case AArch64::INSR_ZR_D: |
| 13522 | case AArch64::INSR_ZR_H: |
| 13523 | case AArch64::INSR_ZR_S: { |
| 13524 | // op: Rm |
| 13525 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13526 | Value |= (op & 0x1f) << 5; |
| 13527 | // op: Zdn |
| 13528 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13529 | Value |= (op & 0x1f); |
| 13530 | break; |
| 13531 | } |
| 13532 | case AArch64::LD1B_2Z_STRIDED: |
| 13533 | case AArch64::LD1D_2Z_STRIDED: |
| 13534 | case AArch64::LD1H_2Z_STRIDED: |
| 13535 | case AArch64::LD1W_2Z_STRIDED: |
| 13536 | case AArch64::LDNT1B_2Z_STRIDED: |
| 13537 | case AArch64::LDNT1D_2Z_STRIDED: |
| 13538 | case AArch64::LDNT1H_2Z_STRIDED: |
| 13539 | case AArch64::LDNT1W_2Z_STRIDED: |
| 13540 | case AArch64::ST1B_2Z_STRIDED: |
| 13541 | case AArch64::ST1D_2Z_STRIDED: |
| 13542 | case AArch64::ST1H_2Z_STRIDED: |
| 13543 | case AArch64::ST1W_2Z_STRIDED: |
| 13544 | case AArch64::STNT1B_2Z_STRIDED: |
| 13545 | case AArch64::STNT1D_2Z_STRIDED: |
| 13546 | case AArch64::STNT1H_2Z_STRIDED: |
| 13547 | case AArch64::STNT1W_2Z_STRIDED: { |
| 13548 | // op: Rm |
| 13549 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13550 | Value |= (op & 0x1f) << 16; |
| 13551 | // op: PNg |
| 13552 | op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI); |
| 13553 | Value |= (op & 0x7) << 10; |
| 13554 | // op: Rn |
| 13555 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13556 | Value |= (op & 0x1f) << 5; |
| 13557 | // op: Zt |
| 13558 | op = EncodeZPR2StridedRegisterClass(MI, OpIdx: 0, Fixups, STI); |
| 13559 | Value |= (op & 0x8) << 1; |
| 13560 | Value |= (op & 0x7); |
| 13561 | break; |
| 13562 | } |
| 13563 | case AArch64::LD1B_4Z_STRIDED: |
| 13564 | case AArch64::LD1D_4Z_STRIDED: |
| 13565 | case AArch64::LD1H_4Z_STRIDED: |
| 13566 | case AArch64::LD1W_4Z_STRIDED: |
| 13567 | case AArch64::LDNT1B_4Z_STRIDED: |
| 13568 | case AArch64::LDNT1D_4Z_STRIDED: |
| 13569 | case AArch64::LDNT1H_4Z_STRIDED: |
| 13570 | case AArch64::LDNT1W_4Z_STRIDED: |
| 13571 | case AArch64::ST1B_4Z_STRIDED: |
| 13572 | case AArch64::ST1D_4Z_STRIDED: |
| 13573 | case AArch64::ST1H_4Z_STRIDED: |
| 13574 | case AArch64::ST1W_4Z_STRIDED: |
| 13575 | case AArch64::STNT1B_4Z_STRIDED: |
| 13576 | case AArch64::STNT1D_4Z_STRIDED: |
| 13577 | case AArch64::STNT1H_4Z_STRIDED: |
| 13578 | case AArch64::STNT1W_4Z_STRIDED: { |
| 13579 | // op: Rm |
| 13580 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13581 | Value |= (op & 0x1f) << 16; |
| 13582 | // op: PNg |
| 13583 | op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI); |
| 13584 | Value |= (op & 0x7) << 10; |
| 13585 | // op: Rn |
| 13586 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13587 | Value |= (op & 0x1f) << 5; |
| 13588 | // op: Zt |
| 13589 | op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI); |
| 13590 | Value |= (op & 0x4) << 2; |
| 13591 | Value |= (op & 0x3); |
| 13592 | break; |
| 13593 | } |
| 13594 | case AArch64::PRFB_PRR: |
| 13595 | case AArch64::PRFD_PRR: |
| 13596 | case AArch64::PRFH_PRR: |
| 13597 | case AArch64::PRFW_PRR: { |
| 13598 | // op: Rm |
| 13599 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13600 | Value |= (op & 0x1f) << 16; |
| 13601 | // op: Rn |
| 13602 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13603 | Value |= (op & 0x1f) << 5; |
| 13604 | // op: Pg |
| 13605 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13606 | Value |= (op & 0x7) << 10; |
| 13607 | // op: prfop |
| 13608 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13609 | Value |= (op & 0xf); |
| 13610 | break; |
| 13611 | } |
| 13612 | case AArch64::LD1_MXIPXX_H_H: |
| 13613 | case AArch64::LD1_MXIPXX_V_H: |
| 13614 | case AArch64::ST1_MXIPXX_H_H: |
| 13615 | case AArch64::ST1_MXIPXX_V_H: { |
| 13616 | // op: Rm |
| 13617 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13618 | Value |= (op & 0x1f) << 16; |
| 13619 | // op: Rv |
| 13620 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI); |
| 13621 | Value |= (op & 0x3) << 13; |
| 13622 | // op: Pg |
| 13623 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13624 | Value |= (op & 0x7) << 10; |
| 13625 | // op: Rn |
| 13626 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13627 | Value |= (op & 0x1f) << 5; |
| 13628 | // op: ZAt |
| 13629 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13630 | Value |= (op & 0x1) << 3; |
| 13631 | // op: imm |
| 13632 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13633 | Value |= (op & 0x7); |
| 13634 | break; |
| 13635 | } |
| 13636 | case AArch64::LD1_MXIPXX_H_S: |
| 13637 | case AArch64::LD1_MXIPXX_V_S: |
| 13638 | case AArch64::ST1_MXIPXX_H_S: |
| 13639 | case AArch64::ST1_MXIPXX_V_S: { |
| 13640 | // op: Rm |
| 13641 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13642 | Value |= (op & 0x1f) << 16; |
| 13643 | // op: Rv |
| 13644 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI); |
| 13645 | Value |= (op & 0x3) << 13; |
| 13646 | // op: Pg |
| 13647 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13648 | Value |= (op & 0x7) << 10; |
| 13649 | // op: Rn |
| 13650 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13651 | Value |= (op & 0x1f) << 5; |
| 13652 | // op: ZAt |
| 13653 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13654 | Value |= (op & 0x3) << 2; |
| 13655 | // op: imm |
| 13656 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13657 | Value |= (op & 0x3); |
| 13658 | break; |
| 13659 | } |
| 13660 | case AArch64::LD1_MXIPXX_H_D: |
| 13661 | case AArch64::LD1_MXIPXX_V_D: |
| 13662 | case AArch64::ST1_MXIPXX_H_D: |
| 13663 | case AArch64::ST1_MXIPXX_V_D: { |
| 13664 | // op: Rm |
| 13665 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13666 | Value |= (op & 0x1f) << 16; |
| 13667 | // op: Rv |
| 13668 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI); |
| 13669 | Value |= (op & 0x3) << 13; |
| 13670 | // op: Pg |
| 13671 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13672 | Value |= (op & 0x7) << 10; |
| 13673 | // op: Rn |
| 13674 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13675 | Value |= (op & 0x1f) << 5; |
| 13676 | // op: ZAt |
| 13677 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13678 | Value |= (op & 0x7) << 1; |
| 13679 | // op: imm |
| 13680 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13681 | Value |= (op & 0x1); |
| 13682 | break; |
| 13683 | } |
| 13684 | case AArch64::LD1_MXIPXX_H_Q: |
| 13685 | case AArch64::LD1_MXIPXX_V_Q: |
| 13686 | case AArch64::ST1_MXIPXX_H_Q: |
| 13687 | case AArch64::ST1_MXIPXX_V_Q: { |
| 13688 | // op: Rm |
| 13689 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13690 | Value |= (op & 0x1f) << 16; |
| 13691 | // op: Rv |
| 13692 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI); |
| 13693 | Value |= (op & 0x3) << 13; |
| 13694 | // op: Pg |
| 13695 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13696 | Value |= (op & 0x7) << 10; |
| 13697 | // op: Rn |
| 13698 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13699 | Value |= (op & 0x1f) << 5; |
| 13700 | // op: ZAt |
| 13701 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13702 | Value |= (op & 0xf); |
| 13703 | break; |
| 13704 | } |
| 13705 | case AArch64::LD1_MXIPXX_H_B: |
| 13706 | case AArch64::LD1_MXIPXX_V_B: |
| 13707 | case AArch64::ST1_MXIPXX_H_B: |
| 13708 | case AArch64::ST1_MXIPXX_V_B: { |
| 13709 | // op: Rm |
| 13710 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 13711 | Value |= (op & 0x1f) << 16; |
| 13712 | // op: Rv |
| 13713 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI); |
| 13714 | Value |= (op & 0x3) << 13; |
| 13715 | // op: Pg |
| 13716 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13717 | Value |= (op & 0x7) << 10; |
| 13718 | // op: Rn |
| 13719 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 13720 | Value |= (op & 0x1f) << 5; |
| 13721 | // op: imm |
| 13722 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13723 | Value |= (op & 0xf); |
| 13724 | break; |
| 13725 | } |
| 13726 | case AArch64::AUTIASPPCr: |
| 13727 | case AArch64::AUTIBSPPCr: |
| 13728 | case AArch64::BLR: |
| 13729 | case AArch64::BLRAAZ: |
| 13730 | case AArch64::BLRABZ: |
| 13731 | case AArch64::BR: |
| 13732 | case AArch64::BRAAZ: |
| 13733 | case AArch64::BRABZ: |
| 13734 | case AArch64::RET: |
| 13735 | case AArch64::SETF16: |
| 13736 | case AArch64::SETF8: { |
| 13737 | // op: Rn |
| 13738 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13739 | Value |= (op & 0x1f) << 5; |
| 13740 | break; |
| 13741 | } |
| 13742 | case AArch64::CCMNWr: |
| 13743 | case AArch64::CCMNXr: |
| 13744 | case AArch64::CCMPWr: |
| 13745 | case AArch64::CCMPXr: |
| 13746 | case AArch64::FCCMPDrr: |
| 13747 | case AArch64::FCCMPEDrr: |
| 13748 | case AArch64::FCCMPEHrr: |
| 13749 | case AArch64::FCCMPESrr: |
| 13750 | case AArch64::FCCMPHrr: |
| 13751 | case AArch64::FCCMPSrr: { |
| 13752 | // op: Rn |
| 13753 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13754 | Value |= (op & 0x1f) << 5; |
| 13755 | // op: Rm |
| 13756 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13757 | Value |= (op & 0x1f) << 16; |
| 13758 | // op: nzcv |
| 13759 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13760 | Value |= (op & 0xf); |
| 13761 | // op: cond |
| 13762 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13763 | Value |= (op & 0xf) << 12; |
| 13764 | break; |
| 13765 | } |
| 13766 | case AArch64::BLRAA: |
| 13767 | case AArch64::BLRAB: |
| 13768 | case AArch64::BRAA: |
| 13769 | case AArch64::BRAB: { |
| 13770 | // op: Rn |
| 13771 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13772 | Value |= (op & 0x1f) << 5; |
| 13773 | // op: Rm |
| 13774 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13775 | Value |= (op & 0x1f); |
| 13776 | break; |
| 13777 | } |
| 13778 | case AArch64::CCMNWi: |
| 13779 | case AArch64::CCMNXi: |
| 13780 | case AArch64::CCMPWi: |
| 13781 | case AArch64::CCMPXi: { |
| 13782 | // op: Rn |
| 13783 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13784 | Value |= (op & 0x1f) << 5; |
| 13785 | // op: imm |
| 13786 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13787 | Value |= (op & 0x1f) << 16; |
| 13788 | // op: nzcv |
| 13789 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13790 | Value |= (op & 0xf); |
| 13791 | // op: cond |
| 13792 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13793 | Value |= (op & 0xf) << 12; |
| 13794 | break; |
| 13795 | } |
| 13796 | case AArch64::RMIF: { |
| 13797 | // op: Rn |
| 13798 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13799 | Value |= (op & 0x1f) << 5; |
| 13800 | // op: imm |
| 13801 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13802 | Value |= (op & 0x3f) << 15; |
| 13803 | // op: mask |
| 13804 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13805 | Value |= (op & 0xf); |
| 13806 | break; |
| 13807 | } |
| 13808 | case AArch64::FCMPDri: |
| 13809 | case AArch64::FCMPEDri: |
| 13810 | case AArch64::FCMPEHri: |
| 13811 | case AArch64::FCMPESri: |
| 13812 | case AArch64::FCMPHri: |
| 13813 | case AArch64::FCMPSri: { |
| 13814 | // op: Rn |
| 13815 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13816 | Value |= (op & 0x1f) << 5; |
| 13817 | Value = fixOneOperandFPComparison(MI, EncodedValue: Value, STI); |
| 13818 | break; |
| 13819 | } |
| 13820 | case AArch64::LDR_TX: |
| 13821 | case AArch64::STR_TX: { |
| 13822 | // op: Rn |
| 13823 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13824 | Value |= (op & 0x1f) << 5; |
| 13825 | break; |
| 13826 | } |
| 13827 | case AArch64::LDAPRB: |
| 13828 | case AArch64::LDAPRH: |
| 13829 | case AArch64::LDAPRW: |
| 13830 | case AArch64::LDAPRX: |
| 13831 | case AArch64::LDGM: |
| 13832 | case AArch64::STGM: |
| 13833 | case AArch64::STZGM: { |
| 13834 | // op: Rn |
| 13835 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13836 | Value |= (op & 0x1f) << 5; |
| 13837 | // op: Rt |
| 13838 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13839 | Value |= (op & 0x1f); |
| 13840 | break; |
| 13841 | } |
| 13842 | case AArch64::ST2Gi: |
| 13843 | case AArch64::STGi: |
| 13844 | case AArch64::STZ2Gi: |
| 13845 | case AArch64::STZGi: { |
| 13846 | // op: Rn |
| 13847 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13848 | Value |= (op & 0x1f) << 5; |
| 13849 | // op: Rt |
| 13850 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13851 | Value |= (op & 0x1f); |
| 13852 | // op: offset |
| 13853 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13854 | Value |= (op & 0x1ff) << 12; |
| 13855 | break; |
| 13856 | } |
| 13857 | case AArch64::DUP_ZR_B: |
| 13858 | case AArch64::DUP_ZR_D: |
| 13859 | case AArch64::DUP_ZR_H: |
| 13860 | case AArch64::DUP_ZR_S: { |
| 13861 | // op: Rn |
| 13862 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13863 | Value |= (op & 0x1f) << 5; |
| 13864 | // op: Zd |
| 13865 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13866 | Value |= (op & 0x1f); |
| 13867 | break; |
| 13868 | } |
| 13869 | case AArch64::INDEX_RI_B: |
| 13870 | case AArch64::INDEX_RI_D: |
| 13871 | case AArch64::INDEX_RI_H: |
| 13872 | case AArch64::INDEX_RI_S: { |
| 13873 | // op: Rn |
| 13874 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13875 | Value |= (op & 0x1f) << 5; |
| 13876 | // op: Zd |
| 13877 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13878 | Value |= (op & 0x1f); |
| 13879 | // op: imm5 |
| 13880 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13881 | Value |= (op & 0x1f) << 16; |
| 13882 | break; |
| 13883 | } |
| 13884 | case AArch64::LDR_ZXI: |
| 13885 | case AArch64::STR_ZXI: { |
| 13886 | // op: Rn |
| 13887 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13888 | Value |= (op & 0x1f) << 5; |
| 13889 | // op: Zt |
| 13890 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13891 | Value |= (op & 0x1f); |
| 13892 | // op: imm9 |
| 13893 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13894 | Value |= (op & 0x1f8) << 13; |
| 13895 | Value |= (op & 0x7) << 10; |
| 13896 | break; |
| 13897 | } |
| 13898 | case AArch64::PRFB_PRI: |
| 13899 | case AArch64::PRFD_PRI: |
| 13900 | case AArch64::PRFH_PRI: |
| 13901 | case AArch64::PRFW_PRI: { |
| 13902 | // op: Rn |
| 13903 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13904 | Value |= (op & 0x1f) << 5; |
| 13905 | // op: Pg |
| 13906 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13907 | Value |= (op & 0x7) << 10; |
| 13908 | // op: imm6 |
| 13909 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13910 | Value |= (op & 0x3f) << 16; |
| 13911 | // op: prfop |
| 13912 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13913 | Value |= (op & 0xf); |
| 13914 | break; |
| 13915 | } |
| 13916 | case AArch64::LDG: |
| 13917 | case AArch64::ST2GPostIndex: |
| 13918 | case AArch64::ST2GPreIndex: |
| 13919 | case AArch64::STGPostIndex: |
| 13920 | case AArch64::STGPreIndex: |
| 13921 | case AArch64::STZ2GPostIndex: |
| 13922 | case AArch64::STZ2GPreIndex: |
| 13923 | case AArch64::STZGPostIndex: |
| 13924 | case AArch64::STZGPreIndex: { |
| 13925 | // op: Rn |
| 13926 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 13927 | Value |= (op & 0x1f) << 5; |
| 13928 | // op: Rt |
| 13929 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 13930 | Value |= (op & 0x1f); |
| 13931 | // op: offset |
| 13932 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13933 | Value |= (op & 0x1ff) << 12; |
| 13934 | break; |
| 13935 | } |
| 13936 | case AArch64::MOVA_MXI2Z_H_H: |
| 13937 | case AArch64::MOVA_MXI2Z_V_H: { |
| 13938 | // op: Rs |
| 13939 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 13940 | Value |= (op & 0x3) << 13; |
| 13941 | // op: Zn |
| 13942 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 13943 | Value |= (op & 0xf) << 6; |
| 13944 | // op: ZAd |
| 13945 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13946 | Value |= (op & 0x1) << 2; |
| 13947 | // op: imm |
| 13948 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13949 | Value |= (op & 0x3); |
| 13950 | break; |
| 13951 | } |
| 13952 | case AArch64::MOVA_MXI2Z_H_S: |
| 13953 | case AArch64::MOVA_MXI2Z_V_S: { |
| 13954 | // op: Rs |
| 13955 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 13956 | Value |= (op & 0x3) << 13; |
| 13957 | // op: Zn |
| 13958 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 13959 | Value |= (op & 0xf) << 6; |
| 13960 | // op: ZAd |
| 13961 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13962 | Value |= (op & 0x3) << 1; |
| 13963 | // op: imm |
| 13964 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13965 | Value |= (op & 0x1); |
| 13966 | break; |
| 13967 | } |
| 13968 | case AArch64::MOVA_MXI2Z_H_D: |
| 13969 | case AArch64::MOVA_MXI2Z_V_D: { |
| 13970 | // op: Rs |
| 13971 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 13972 | Value |= (op & 0x3) << 13; |
| 13973 | // op: Zn |
| 13974 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 13975 | Value |= (op & 0xf) << 6; |
| 13976 | // op: ZAd |
| 13977 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 13978 | Value |= (op & 0x7); |
| 13979 | break; |
| 13980 | } |
| 13981 | case AArch64::MOVA_MXI2Z_H_B: |
| 13982 | case AArch64::MOVA_MXI2Z_V_B: { |
| 13983 | // op: Rs |
| 13984 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 13985 | Value |= (op & 0x3) << 13; |
| 13986 | // op: Zn |
| 13987 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 13988 | Value |= (op & 0xf) << 6; |
| 13989 | // op: imm |
| 13990 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 13991 | Value |= (op & 0x7); |
| 13992 | break; |
| 13993 | } |
| 13994 | case AArch64::MOVA_MXI4Z_H_H: |
| 13995 | case AArch64::MOVA_MXI4Z_V_H: { |
| 13996 | // op: Rs |
| 13997 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 13998 | Value |= (op & 0x3) << 13; |
| 13999 | // op: Zn |
| 14000 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 14001 | Value |= (op & 0x7) << 7; |
| 14002 | // op: ZAd |
| 14003 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14004 | Value |= (op & 0x1) << 1; |
| 14005 | // op: imm |
| 14006 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14007 | Value |= (op & 0x1); |
| 14008 | break; |
| 14009 | } |
| 14010 | case AArch64::MOVA_MXI4Z_H_S: |
| 14011 | case AArch64::MOVA_MXI4Z_V_S: { |
| 14012 | // op: Rs |
| 14013 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 14014 | Value |= (op & 0x3) << 13; |
| 14015 | // op: Zn |
| 14016 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 14017 | Value |= (op & 0x7) << 7; |
| 14018 | // op: ZAd |
| 14019 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14020 | Value |= (op & 0x3); |
| 14021 | break; |
| 14022 | } |
| 14023 | case AArch64::MOVA_MXI4Z_H_D: |
| 14024 | case AArch64::MOVA_MXI4Z_V_D: { |
| 14025 | // op: Rs |
| 14026 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 14027 | Value |= (op & 0x3) << 13; |
| 14028 | // op: Zn |
| 14029 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 14030 | Value |= (op & 0x7) << 7; |
| 14031 | // op: ZAd |
| 14032 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14033 | Value |= (op & 0x7); |
| 14034 | break; |
| 14035 | } |
| 14036 | case AArch64::MOVA_MXI4Z_H_B: |
| 14037 | case AArch64::MOVA_MXI4Z_V_B: { |
| 14038 | // op: Rs |
| 14039 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 14040 | Value |= (op & 0x3) << 13; |
| 14041 | // op: Zn |
| 14042 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 14043 | Value |= (op & 0x7) << 7; |
| 14044 | // op: imm |
| 14045 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14046 | Value |= (op & 0x3); |
| 14047 | break; |
| 14048 | } |
| 14049 | case AArch64::MOVAZ_ZMI_H_H: |
| 14050 | case AArch64::MOVAZ_ZMI_V_H: { |
| 14051 | // op: Rs |
| 14052 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 14053 | Value |= (op & 0x3) << 13; |
| 14054 | // op: Zd |
| 14055 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14056 | Value |= (op & 0x1f); |
| 14057 | // op: ZAn |
| 14058 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14059 | Value |= (op & 0x1) << 8; |
| 14060 | // op: imm |
| 14061 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 14062 | Value |= (op & 0x7) << 5; |
| 14063 | break; |
| 14064 | } |
| 14065 | case AArch64::MOVAZ_ZMI_H_S: |
| 14066 | case AArch64::MOVAZ_ZMI_V_S: { |
| 14067 | // op: Rs |
| 14068 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 14069 | Value |= (op & 0x3) << 13; |
| 14070 | // op: Zd |
| 14071 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14072 | Value |= (op & 0x1f); |
| 14073 | // op: ZAn |
| 14074 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14075 | Value |= (op & 0x3) << 7; |
| 14076 | // op: imm |
| 14077 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 14078 | Value |= (op & 0x3) << 5; |
| 14079 | break; |
| 14080 | } |
| 14081 | case AArch64::MOVAZ_ZMI_H_D: |
| 14082 | case AArch64::MOVAZ_ZMI_V_D: { |
| 14083 | // op: Rs |
| 14084 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 14085 | Value |= (op & 0x3) << 13; |
| 14086 | // op: Zd |
| 14087 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14088 | Value |= (op & 0x1f); |
| 14089 | // op: ZAn |
| 14090 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14091 | Value |= (op & 0x7) << 6; |
| 14092 | // op: imm |
| 14093 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 14094 | Value |= (op & 0x1) << 5; |
| 14095 | break; |
| 14096 | } |
| 14097 | case AArch64::MOVAZ_ZMI_H_Q: |
| 14098 | case AArch64::MOVAZ_ZMI_V_Q: { |
| 14099 | // op: Rs |
| 14100 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 14101 | Value |= (op & 0x3) << 13; |
| 14102 | // op: Zd |
| 14103 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14104 | Value |= (op & 0x1f); |
| 14105 | // op: ZAn |
| 14106 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14107 | Value |= (op & 0xf) << 5; |
| 14108 | break; |
| 14109 | } |
| 14110 | case AArch64::MOVAZ_ZMI_H_B: |
| 14111 | case AArch64::MOVAZ_ZMI_V_B: { |
| 14112 | // op: Rs |
| 14113 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 14114 | Value |= (op & 0x3) << 13; |
| 14115 | // op: Zd |
| 14116 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14117 | Value |= (op & 0x1f); |
| 14118 | // op: imm |
| 14119 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 14120 | Value |= (op & 0xf) << 5; |
| 14121 | break; |
| 14122 | } |
| 14123 | case AArch64::MOVA_VG2_2ZMXI: { |
| 14124 | // op: Rs |
| 14125 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 14126 | Value |= (op & 0x3) << 13; |
| 14127 | // op: imm |
| 14128 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14129 | Value |= (op & 0x7) << 5; |
| 14130 | // op: Zd |
| 14131 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 14132 | Value |= (op & 0xf) << 1; |
| 14133 | break; |
| 14134 | } |
| 14135 | case AArch64::MOVA_VG4_4ZMXI: { |
| 14136 | // op: Rs |
| 14137 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 14138 | Value |= (op & 0x3) << 13; |
| 14139 | // op: imm |
| 14140 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14141 | Value |= (op & 0x7) << 5; |
| 14142 | // op: Zd |
| 14143 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 14144 | Value |= (op & 0x7) << 2; |
| 14145 | break; |
| 14146 | } |
| 14147 | case AArch64::MOVA_VG2_MXI2Z: { |
| 14148 | // op: Rs |
| 14149 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 14150 | Value |= (op & 0x3) << 13; |
| 14151 | // op: imm |
| 14152 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14153 | Value |= (op & 0x7); |
| 14154 | // op: Zn |
| 14155 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 14156 | Value |= (op & 0xf) << 6; |
| 14157 | break; |
| 14158 | } |
| 14159 | case AArch64::MOVA_VG4_MXI4Z: { |
| 14160 | // op: Rs |
| 14161 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 14162 | Value |= (op & 0x3) << 13; |
| 14163 | // op: imm |
| 14164 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14165 | Value |= (op & 0x7); |
| 14166 | // op: Zn |
| 14167 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 14168 | Value |= (op & 0x7) << 7; |
| 14169 | break; |
| 14170 | } |
| 14171 | case AArch64::MOVAZ_VG2_2ZMXI: { |
| 14172 | // op: Rs |
| 14173 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 3, Fixups, STI); |
| 14174 | Value |= (op & 0x3) << 13; |
| 14175 | // op: imm |
| 14176 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 14177 | Value |= (op & 0x7) << 5; |
| 14178 | // op: Zd |
| 14179 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 14180 | Value |= (op & 0xf) << 1; |
| 14181 | break; |
| 14182 | } |
| 14183 | case AArch64::MOVAZ_VG4_4ZMXI: { |
| 14184 | // op: Rs |
| 14185 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 3, Fixups, STI); |
| 14186 | Value |= (op & 0x3) << 13; |
| 14187 | // op: imm |
| 14188 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 14189 | Value |= (op & 0x7) << 5; |
| 14190 | // op: Zd |
| 14191 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 14192 | Value |= (op & 0x7) << 2; |
| 14193 | break; |
| 14194 | } |
| 14195 | case AArch64::STBFADD: |
| 14196 | case AArch64::STBFADDL: |
| 14197 | case AArch64::STBFMAX: |
| 14198 | case AArch64::STBFMAXL: |
| 14199 | case AArch64::STBFMAXNM: |
| 14200 | case AArch64::STBFMAXNML: |
| 14201 | case AArch64::STBFMIN: |
| 14202 | case AArch64::STBFMINL: |
| 14203 | case AArch64::STBFMINNM: |
| 14204 | case AArch64::STBFMINNML: |
| 14205 | case AArch64::STFADDD: |
| 14206 | case AArch64::STFADDH: |
| 14207 | case AArch64::STFADDLD: |
| 14208 | case AArch64::STFADDLH: |
| 14209 | case AArch64::STFADDLS: |
| 14210 | case AArch64::STFADDS: |
| 14211 | case AArch64::STFMAXD: |
| 14212 | case AArch64::STFMAXH: |
| 14213 | case AArch64::STFMAXLD: |
| 14214 | case AArch64::STFMAXLH: |
| 14215 | case AArch64::STFMAXLS: |
| 14216 | case AArch64::STFMAXNMD: |
| 14217 | case AArch64::STFMAXNMH: |
| 14218 | case AArch64::STFMAXNMLD: |
| 14219 | case AArch64::STFMAXNMLH: |
| 14220 | case AArch64::STFMAXNMLS: |
| 14221 | case AArch64::STFMAXNMS: |
| 14222 | case AArch64::STFMAXS: |
| 14223 | case AArch64::STFMIND: |
| 14224 | case AArch64::STFMINH: |
| 14225 | case AArch64::STFMINLD: |
| 14226 | case AArch64::STFMINLH: |
| 14227 | case AArch64::STFMINLS: |
| 14228 | case AArch64::STFMINNMD: |
| 14229 | case AArch64::STFMINNMH: |
| 14230 | case AArch64::STFMINNMLD: |
| 14231 | case AArch64::STFMINNMLH: |
| 14232 | case AArch64::STFMINNMLS: |
| 14233 | case AArch64::STFMINNMS: |
| 14234 | case AArch64::STFMINS: { |
| 14235 | // op: Rs |
| 14236 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14237 | Value |= (op & 0x1f) << 16; |
| 14238 | // op: Rn |
| 14239 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14240 | Value |= (op & 0x1f) << 5; |
| 14241 | break; |
| 14242 | } |
| 14243 | case AArch64::LDADDAB: |
| 14244 | case AArch64::LDADDAH: |
| 14245 | case AArch64::LDADDALB: |
| 14246 | case AArch64::LDADDALH: |
| 14247 | case AArch64::LDADDALW: |
| 14248 | case AArch64::LDADDALX: |
| 14249 | case AArch64::LDADDAW: |
| 14250 | case AArch64::LDADDAX: |
| 14251 | case AArch64::LDADDB: |
| 14252 | case AArch64::LDADDH: |
| 14253 | case AArch64::LDADDLB: |
| 14254 | case AArch64::LDADDLH: |
| 14255 | case AArch64::LDADDLW: |
| 14256 | case AArch64::LDADDLX: |
| 14257 | case AArch64::LDADDW: |
| 14258 | case AArch64::LDADDX: |
| 14259 | case AArch64::LDCLRAB: |
| 14260 | case AArch64::LDCLRAH: |
| 14261 | case AArch64::LDCLRALB: |
| 14262 | case AArch64::LDCLRALH: |
| 14263 | case AArch64::LDCLRALW: |
| 14264 | case AArch64::LDCLRALX: |
| 14265 | case AArch64::LDCLRAW: |
| 14266 | case AArch64::LDCLRAX: |
| 14267 | case AArch64::LDCLRB: |
| 14268 | case AArch64::LDCLRH: |
| 14269 | case AArch64::LDCLRLB: |
| 14270 | case AArch64::LDCLRLH: |
| 14271 | case AArch64::LDCLRLW: |
| 14272 | case AArch64::LDCLRLX: |
| 14273 | case AArch64::LDCLRW: |
| 14274 | case AArch64::LDCLRX: |
| 14275 | case AArch64::LDEORAB: |
| 14276 | case AArch64::LDEORAH: |
| 14277 | case AArch64::LDEORALB: |
| 14278 | case AArch64::LDEORALH: |
| 14279 | case AArch64::LDEORALW: |
| 14280 | case AArch64::LDEORALX: |
| 14281 | case AArch64::LDEORAW: |
| 14282 | case AArch64::LDEORAX: |
| 14283 | case AArch64::LDEORB: |
| 14284 | case AArch64::LDEORH: |
| 14285 | case AArch64::LDEORLB: |
| 14286 | case AArch64::LDEORLH: |
| 14287 | case AArch64::LDEORLW: |
| 14288 | case AArch64::LDEORLX: |
| 14289 | case AArch64::LDEORW: |
| 14290 | case AArch64::LDEORX: |
| 14291 | case AArch64::LDSETAB: |
| 14292 | case AArch64::LDSETAH: |
| 14293 | case AArch64::LDSETALB: |
| 14294 | case AArch64::LDSETALH: |
| 14295 | case AArch64::LDSETALW: |
| 14296 | case AArch64::LDSETALX: |
| 14297 | case AArch64::LDSETAW: |
| 14298 | case AArch64::LDSETAX: |
| 14299 | case AArch64::LDSETB: |
| 14300 | case AArch64::LDSETH: |
| 14301 | case AArch64::LDSETLB: |
| 14302 | case AArch64::LDSETLH: |
| 14303 | case AArch64::LDSETLW: |
| 14304 | case AArch64::LDSETLX: |
| 14305 | case AArch64::LDSETW: |
| 14306 | case AArch64::LDSETX: |
| 14307 | case AArch64::LDSMAXAB: |
| 14308 | case AArch64::LDSMAXAH: |
| 14309 | case AArch64::LDSMAXALB: |
| 14310 | case AArch64::LDSMAXALH: |
| 14311 | case AArch64::LDSMAXALW: |
| 14312 | case AArch64::LDSMAXALX: |
| 14313 | case AArch64::LDSMAXAW: |
| 14314 | case AArch64::LDSMAXAX: |
| 14315 | case AArch64::LDSMAXB: |
| 14316 | case AArch64::LDSMAXH: |
| 14317 | case AArch64::LDSMAXLB: |
| 14318 | case AArch64::LDSMAXLH: |
| 14319 | case AArch64::LDSMAXLW: |
| 14320 | case AArch64::LDSMAXLX: |
| 14321 | case AArch64::LDSMAXW: |
| 14322 | case AArch64::LDSMAXX: |
| 14323 | case AArch64::LDSMINAB: |
| 14324 | case AArch64::LDSMINAH: |
| 14325 | case AArch64::LDSMINALB: |
| 14326 | case AArch64::LDSMINALH: |
| 14327 | case AArch64::LDSMINALW: |
| 14328 | case AArch64::LDSMINALX: |
| 14329 | case AArch64::LDSMINAW: |
| 14330 | case AArch64::LDSMINAX: |
| 14331 | case AArch64::LDSMINB: |
| 14332 | case AArch64::LDSMINH: |
| 14333 | case AArch64::LDSMINLB: |
| 14334 | case AArch64::LDSMINLH: |
| 14335 | case AArch64::LDSMINLW: |
| 14336 | case AArch64::LDSMINLX: |
| 14337 | case AArch64::LDSMINW: |
| 14338 | case AArch64::LDSMINX: |
| 14339 | case AArch64::LDTADDALW: |
| 14340 | case AArch64::LDTADDALX: |
| 14341 | case AArch64::LDTADDAW: |
| 14342 | case AArch64::LDTADDAX: |
| 14343 | case AArch64::LDTADDLW: |
| 14344 | case AArch64::LDTADDLX: |
| 14345 | case AArch64::LDTADDW: |
| 14346 | case AArch64::LDTADDX: |
| 14347 | case AArch64::LDTCLRALW: |
| 14348 | case AArch64::LDTCLRALX: |
| 14349 | case AArch64::LDTCLRAW: |
| 14350 | case AArch64::LDTCLRAX: |
| 14351 | case AArch64::LDTCLRLW: |
| 14352 | case AArch64::LDTCLRLX: |
| 14353 | case AArch64::LDTCLRW: |
| 14354 | case AArch64::LDTCLRX: |
| 14355 | case AArch64::LDTSETALW: |
| 14356 | case AArch64::LDTSETALX: |
| 14357 | case AArch64::LDTSETAW: |
| 14358 | case AArch64::LDTSETAX: |
| 14359 | case AArch64::LDTSETLW: |
| 14360 | case AArch64::LDTSETLX: |
| 14361 | case AArch64::LDTSETW: |
| 14362 | case AArch64::LDTSETX: |
| 14363 | case AArch64::LDUMAXAB: |
| 14364 | case AArch64::LDUMAXAH: |
| 14365 | case AArch64::LDUMAXALB: |
| 14366 | case AArch64::LDUMAXALH: |
| 14367 | case AArch64::LDUMAXALW: |
| 14368 | case AArch64::LDUMAXALX: |
| 14369 | case AArch64::LDUMAXAW: |
| 14370 | case AArch64::LDUMAXAX: |
| 14371 | case AArch64::LDUMAXB: |
| 14372 | case AArch64::LDUMAXH: |
| 14373 | case AArch64::LDUMAXLB: |
| 14374 | case AArch64::LDUMAXLH: |
| 14375 | case AArch64::LDUMAXLW: |
| 14376 | case AArch64::LDUMAXLX: |
| 14377 | case AArch64::LDUMAXW: |
| 14378 | case AArch64::LDUMAXX: |
| 14379 | case AArch64::LDUMINAB: |
| 14380 | case AArch64::LDUMINAH: |
| 14381 | case AArch64::LDUMINALB: |
| 14382 | case AArch64::LDUMINALH: |
| 14383 | case AArch64::LDUMINALW: |
| 14384 | case AArch64::LDUMINALX: |
| 14385 | case AArch64::LDUMINAW: |
| 14386 | case AArch64::LDUMINAX: |
| 14387 | case AArch64::LDUMINB: |
| 14388 | case AArch64::LDUMINH: |
| 14389 | case AArch64::LDUMINLB: |
| 14390 | case AArch64::LDUMINLH: |
| 14391 | case AArch64::LDUMINLW: |
| 14392 | case AArch64::LDUMINLX: |
| 14393 | case AArch64::LDUMINW: |
| 14394 | case AArch64::LDUMINX: |
| 14395 | case AArch64::RCWCLR: |
| 14396 | case AArch64::RCWCLRA: |
| 14397 | case AArch64::RCWCLRAL: |
| 14398 | case AArch64::RCWCLRL: |
| 14399 | case AArch64::RCWCLRS: |
| 14400 | case AArch64::RCWCLRSA: |
| 14401 | case AArch64::RCWCLRSAL: |
| 14402 | case AArch64::RCWCLRSL: |
| 14403 | case AArch64::RCWSET: |
| 14404 | case AArch64::RCWSETA: |
| 14405 | case AArch64::RCWSETAL: |
| 14406 | case AArch64::RCWSETL: |
| 14407 | case AArch64::RCWSETS: |
| 14408 | case AArch64::RCWSETSA: |
| 14409 | case AArch64::RCWSETSAL: |
| 14410 | case AArch64::RCWSETSL: |
| 14411 | case AArch64::RCWSWP: |
| 14412 | case AArch64::RCWSWPA: |
| 14413 | case AArch64::RCWSWPAL: |
| 14414 | case AArch64::RCWSWPL: |
| 14415 | case AArch64::RCWSWPS: |
| 14416 | case AArch64::RCWSWPSA: |
| 14417 | case AArch64::RCWSWPSAL: |
| 14418 | case AArch64::RCWSWPSL: |
| 14419 | case AArch64::SWPAB: |
| 14420 | case AArch64::SWPAH: |
| 14421 | case AArch64::SWPALB: |
| 14422 | case AArch64::SWPALH: |
| 14423 | case AArch64::SWPALW: |
| 14424 | case AArch64::SWPALX: |
| 14425 | case AArch64::SWPAW: |
| 14426 | case AArch64::SWPAX: |
| 14427 | case AArch64::SWPB: |
| 14428 | case AArch64::SWPH: |
| 14429 | case AArch64::SWPLB: |
| 14430 | case AArch64::SWPLH: |
| 14431 | case AArch64::SWPLW: |
| 14432 | case AArch64::SWPLX: |
| 14433 | case AArch64::SWPTALW: |
| 14434 | case AArch64::SWPTALX: |
| 14435 | case AArch64::SWPTAW: |
| 14436 | case AArch64::SWPTAX: |
| 14437 | case AArch64::SWPTLW: |
| 14438 | case AArch64::SWPTLX: |
| 14439 | case AArch64::SWPTW: |
| 14440 | case AArch64::SWPTX: |
| 14441 | case AArch64::SWPW: |
| 14442 | case AArch64::SWPX: { |
| 14443 | // op: Rs |
| 14444 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14445 | Value |= (op & 0x1f) << 16; |
| 14446 | // op: Rn |
| 14447 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14448 | Value |= (op & 0x1f) << 5; |
| 14449 | // op: Rt |
| 14450 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14451 | Value |= (op & 0x1f); |
| 14452 | break; |
| 14453 | } |
| 14454 | case AArch64::CASAB: |
| 14455 | case AArch64::CASAH: |
| 14456 | case AArch64::CASALB: |
| 14457 | case AArch64::CASALH: |
| 14458 | case AArch64::CASALTX: |
| 14459 | case AArch64::CASALW: |
| 14460 | case AArch64::CASALX: |
| 14461 | case AArch64::CASATX: |
| 14462 | case AArch64::CASAW: |
| 14463 | case AArch64::CASAX: |
| 14464 | case AArch64::CASB: |
| 14465 | case AArch64::CASH: |
| 14466 | case AArch64::CASLB: |
| 14467 | case AArch64::CASLH: |
| 14468 | case AArch64::CASLTX: |
| 14469 | case AArch64::CASLW: |
| 14470 | case AArch64::CASLX: |
| 14471 | case AArch64::CASPALTX: |
| 14472 | case AArch64::CASPALW: |
| 14473 | case AArch64::CASPALX: |
| 14474 | case AArch64::CASPATX: |
| 14475 | case AArch64::CASPAW: |
| 14476 | case AArch64::CASPAX: |
| 14477 | case AArch64::CASPLTX: |
| 14478 | case AArch64::CASPLW: |
| 14479 | case AArch64::CASPLX: |
| 14480 | case AArch64::CASPTX: |
| 14481 | case AArch64::CASPW: |
| 14482 | case AArch64::CASPX: |
| 14483 | case AArch64::CASTX: |
| 14484 | case AArch64::CASW: |
| 14485 | case AArch64::CASX: |
| 14486 | case AArch64::RCWCAS: |
| 14487 | case AArch64::RCWCASA: |
| 14488 | case AArch64::RCWCASAL: |
| 14489 | case AArch64::RCWCASL: |
| 14490 | case AArch64::RCWCASP: |
| 14491 | case AArch64::RCWCASPA: |
| 14492 | case AArch64::RCWCASPAL: |
| 14493 | case AArch64::RCWCASPL: |
| 14494 | case AArch64::RCWSCAS: |
| 14495 | case AArch64::RCWSCASA: |
| 14496 | case AArch64::RCWSCASAL: |
| 14497 | case AArch64::RCWSCASL: |
| 14498 | case AArch64::RCWSCASP: |
| 14499 | case AArch64::RCWSCASPA: |
| 14500 | case AArch64::RCWSCASPAL: |
| 14501 | case AArch64::RCWSCASPL: { |
| 14502 | // op: Rs |
| 14503 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14504 | Value |= (op & 0x1f) << 16; |
| 14505 | // op: Rn |
| 14506 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14507 | Value |= (op & 0x1f) << 5; |
| 14508 | // op: Rt |
| 14509 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14510 | Value |= (op & 0x1f); |
| 14511 | break; |
| 14512 | } |
| 14513 | case AArch64::GCSPOPM: |
| 14514 | case AArch64::GCSPUSHM: |
| 14515 | case AArch64::GCSSS1: |
| 14516 | case AArch64::GCSSS2: |
| 14517 | case AArch64::WFET: |
| 14518 | case AArch64::WFIT: { |
| 14519 | // op: Rt |
| 14520 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14521 | Value |= (op & 0x1f); |
| 14522 | break; |
| 14523 | } |
| 14524 | case AArch64::GCSSTR: |
| 14525 | case AArch64::GCSSTTR: |
| 14526 | case AArch64::LD64B: |
| 14527 | case AArch64::LDA64B: |
| 14528 | case AArch64::ST64B: |
| 14529 | case AArch64::STL64B: { |
| 14530 | // op: Rt |
| 14531 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14532 | Value |= (op & 0x1f); |
| 14533 | // op: Rn |
| 14534 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14535 | Value |= (op & 0x1f) << 5; |
| 14536 | break; |
| 14537 | } |
| 14538 | case AArch64::LDRBBroW: |
| 14539 | case AArch64::LDRBBroX: |
| 14540 | case AArch64::LDRBroW: |
| 14541 | case AArch64::LDRBroX: |
| 14542 | case AArch64::LDRDroW: |
| 14543 | case AArch64::LDRDroX: |
| 14544 | case AArch64::LDRHHroW: |
| 14545 | case AArch64::LDRHHroX: |
| 14546 | case AArch64::LDRHroW: |
| 14547 | case AArch64::LDRHroX: |
| 14548 | case AArch64::LDRQroW: |
| 14549 | case AArch64::LDRQroX: |
| 14550 | case AArch64::LDRSBWroW: |
| 14551 | case AArch64::LDRSBWroX: |
| 14552 | case AArch64::LDRSBXroW: |
| 14553 | case AArch64::LDRSBXroX: |
| 14554 | case AArch64::LDRSHWroW: |
| 14555 | case AArch64::LDRSHWroX: |
| 14556 | case AArch64::LDRSHXroW: |
| 14557 | case AArch64::LDRSHXroX: |
| 14558 | case AArch64::LDRSWroW: |
| 14559 | case AArch64::LDRSWroX: |
| 14560 | case AArch64::LDRSroW: |
| 14561 | case AArch64::LDRSroX: |
| 14562 | case AArch64::LDRWroW: |
| 14563 | case AArch64::LDRWroX: |
| 14564 | case AArch64::LDRXroW: |
| 14565 | case AArch64::LDRXroX: |
| 14566 | case AArch64::PRFMroW: |
| 14567 | case AArch64::PRFMroX: |
| 14568 | case AArch64::STRBBroW: |
| 14569 | case AArch64::STRBBroX: |
| 14570 | case AArch64::STRBroW: |
| 14571 | case AArch64::STRBroX: |
| 14572 | case AArch64::STRDroW: |
| 14573 | case AArch64::STRDroX: |
| 14574 | case AArch64::STRHHroW: |
| 14575 | case AArch64::STRHHroX: |
| 14576 | case AArch64::STRHroW: |
| 14577 | case AArch64::STRHroX: |
| 14578 | case AArch64::STRQroW: |
| 14579 | case AArch64::STRQroX: |
| 14580 | case AArch64::STRSroW: |
| 14581 | case AArch64::STRSroX: |
| 14582 | case AArch64::STRWroW: |
| 14583 | case AArch64::STRWroX: |
| 14584 | case AArch64::STRXroW: |
| 14585 | case AArch64::STRXroX: { |
| 14586 | // op: Rt |
| 14587 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14588 | Value |= (op & 0x1f); |
| 14589 | // op: Rn |
| 14590 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14591 | Value |= (op & 0x1f) << 5; |
| 14592 | // op: Rm |
| 14593 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14594 | Value |= (op & 0x1f) << 16; |
| 14595 | // op: extend |
| 14596 | op = getMemExtendOpValue(MI, OpIdx: 3, Fixups, STI); |
| 14597 | Value |= (op & 0x2) << 14; |
| 14598 | Value |= (op & 0x1) << 12; |
| 14599 | break; |
| 14600 | } |
| 14601 | case AArch64::LDRQui: |
| 14602 | case AArch64::STRQui: { |
| 14603 | // op: Rt |
| 14604 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14605 | Value |= (op & 0x1f); |
| 14606 | // op: Rn |
| 14607 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14608 | Value |= (op & 0x1f) << 5; |
| 14609 | // op: offset |
| 14610 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale16>(MI, OpIdx: 2, Fixups, STI); |
| 14611 | Value |= (op & 0xfff) << 10; |
| 14612 | break; |
| 14613 | } |
| 14614 | case AArch64::LDRBBui: |
| 14615 | case AArch64::LDRBui: |
| 14616 | case AArch64::LDRSBWui: |
| 14617 | case AArch64::LDRSBXui: |
| 14618 | case AArch64::STRBBui: |
| 14619 | case AArch64::STRBui: { |
| 14620 | // op: Rt |
| 14621 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14622 | Value |= (op & 0x1f); |
| 14623 | // op: Rn |
| 14624 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14625 | Value |= (op & 0x1f) << 5; |
| 14626 | // op: offset |
| 14627 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale1>(MI, OpIdx: 2, Fixups, STI); |
| 14628 | Value |= (op & 0xfff) << 10; |
| 14629 | break; |
| 14630 | } |
| 14631 | case AArch64::LDRHHui: |
| 14632 | case AArch64::LDRHui: |
| 14633 | case AArch64::LDRSHWui: |
| 14634 | case AArch64::LDRSHXui: |
| 14635 | case AArch64::STRHHui: |
| 14636 | case AArch64::STRHui: { |
| 14637 | // op: Rt |
| 14638 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14639 | Value |= (op & 0x1f); |
| 14640 | // op: Rn |
| 14641 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14642 | Value |= (op & 0x1f) << 5; |
| 14643 | // op: offset |
| 14644 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale2>(MI, OpIdx: 2, Fixups, STI); |
| 14645 | Value |= (op & 0xfff) << 10; |
| 14646 | break; |
| 14647 | } |
| 14648 | case AArch64::LDRSWui: |
| 14649 | case AArch64::LDRSui: |
| 14650 | case AArch64::LDRWui: |
| 14651 | case AArch64::STRSui: |
| 14652 | case AArch64::STRWui: { |
| 14653 | // op: Rt |
| 14654 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14655 | Value |= (op & 0x1f); |
| 14656 | // op: Rn |
| 14657 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14658 | Value |= (op & 0x1f) << 5; |
| 14659 | // op: offset |
| 14660 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale4>(MI, OpIdx: 2, Fixups, STI); |
| 14661 | Value |= (op & 0xfff) << 10; |
| 14662 | break; |
| 14663 | } |
| 14664 | case AArch64::LDRDui: |
| 14665 | case AArch64::LDRXui: |
| 14666 | case AArch64::PRFMui: |
| 14667 | case AArch64::STRDui: |
| 14668 | case AArch64::STRXui: { |
| 14669 | // op: Rt |
| 14670 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14671 | Value |= (op & 0x1f); |
| 14672 | // op: Rn |
| 14673 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14674 | Value |= (op & 0x1f) << 5; |
| 14675 | // op: offset |
| 14676 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale8>(MI, OpIdx: 2, Fixups, STI); |
| 14677 | Value |= (op & 0xfff) << 10; |
| 14678 | break; |
| 14679 | } |
| 14680 | case AArch64::LDAPURBi: |
| 14681 | case AArch64::LDAPURHi: |
| 14682 | case AArch64::LDAPURSBWi: |
| 14683 | case AArch64::LDAPURSBXi: |
| 14684 | case AArch64::LDAPURSHWi: |
| 14685 | case AArch64::LDAPURSHXi: |
| 14686 | case AArch64::LDAPURSWi: |
| 14687 | case AArch64::LDAPURXi: |
| 14688 | case AArch64::LDAPURi: |
| 14689 | case AArch64::LDTRBi: |
| 14690 | case AArch64::LDTRHi: |
| 14691 | case AArch64::LDTRSBWi: |
| 14692 | case AArch64::LDTRSBXi: |
| 14693 | case AArch64::LDTRSHWi: |
| 14694 | case AArch64::LDTRSHXi: |
| 14695 | case AArch64::LDTRSWi: |
| 14696 | case AArch64::LDTRWi: |
| 14697 | case AArch64::LDTRXi: |
| 14698 | case AArch64::LDURBBi: |
| 14699 | case AArch64::LDURBi: |
| 14700 | case AArch64::LDURDi: |
| 14701 | case AArch64::LDURHHi: |
| 14702 | case AArch64::LDURHi: |
| 14703 | case AArch64::LDURQi: |
| 14704 | case AArch64::LDURSBWi: |
| 14705 | case AArch64::LDURSBXi: |
| 14706 | case AArch64::LDURSHWi: |
| 14707 | case AArch64::LDURSHXi: |
| 14708 | case AArch64::LDURSWi: |
| 14709 | case AArch64::LDURSi: |
| 14710 | case AArch64::LDURWi: |
| 14711 | case AArch64::LDURXi: |
| 14712 | case AArch64::PRFUMi: |
| 14713 | case AArch64::STLURBi: |
| 14714 | case AArch64::STLURHi: |
| 14715 | case AArch64::STLURWi: |
| 14716 | case AArch64::STLURXi: |
| 14717 | case AArch64::STTRBi: |
| 14718 | case AArch64::STTRHi: |
| 14719 | case AArch64::STTRWi: |
| 14720 | case AArch64::STTRXi: |
| 14721 | case AArch64::STURBBi: |
| 14722 | case AArch64::STURBi: |
| 14723 | case AArch64::STURDi: |
| 14724 | case AArch64::STURHHi: |
| 14725 | case AArch64::STURHi: |
| 14726 | case AArch64::STURQi: |
| 14727 | case AArch64::STURSi: |
| 14728 | case AArch64::STURWi: |
| 14729 | case AArch64::STURXi: { |
| 14730 | // op: Rt |
| 14731 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14732 | Value |= (op & 0x1f); |
| 14733 | // op: Rn |
| 14734 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14735 | Value |= (op & 0x1f) << 5; |
| 14736 | // op: offset |
| 14737 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14738 | Value |= (op & 0x1ff) << 12; |
| 14739 | break; |
| 14740 | } |
| 14741 | case AArch64::LDAPURbi: |
| 14742 | case AArch64::LDAPURdi: |
| 14743 | case AArch64::LDAPURhi: |
| 14744 | case AArch64::LDAPURqi: |
| 14745 | case AArch64::LDAPURsi: |
| 14746 | case AArch64::STLURbi: |
| 14747 | case AArch64::STLURdi: |
| 14748 | case AArch64::STLURhi: |
| 14749 | case AArch64::STLURqi: |
| 14750 | case AArch64::STLURsi: { |
| 14751 | // op: Rt |
| 14752 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14753 | Value |= (op & 0x1f); |
| 14754 | // op: Rn |
| 14755 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14756 | Value |= (op & 0x1f) << 5; |
| 14757 | // op: simm |
| 14758 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14759 | Value |= (op & 0x1ff) << 12; |
| 14760 | break; |
| 14761 | } |
| 14762 | case AArch64::LDARB: |
| 14763 | case AArch64::LDARH: |
| 14764 | case AArch64::LDARW: |
| 14765 | case AArch64::LDARX: |
| 14766 | case AArch64::LDATXRW: |
| 14767 | case AArch64::LDATXRX: |
| 14768 | case AArch64::LDAXRB: |
| 14769 | case AArch64::LDAXRH: |
| 14770 | case AArch64::LDAXRW: |
| 14771 | case AArch64::LDAXRX: |
| 14772 | case AArch64::LDLARB: |
| 14773 | case AArch64::LDLARH: |
| 14774 | case AArch64::LDLARW: |
| 14775 | case AArch64::LDLARX: |
| 14776 | case AArch64::LDTXRWr: |
| 14777 | case AArch64::LDTXRXr: |
| 14778 | case AArch64::LDXRB: |
| 14779 | case AArch64::LDXRH: |
| 14780 | case AArch64::LDXRW: |
| 14781 | case AArch64::LDXRX: |
| 14782 | case AArch64::STLLRB: |
| 14783 | case AArch64::STLLRH: |
| 14784 | case AArch64::STLLRW: |
| 14785 | case AArch64::STLLRX: |
| 14786 | case AArch64::STLRB: |
| 14787 | case AArch64::STLRH: |
| 14788 | case AArch64::STLRW: |
| 14789 | case AArch64::STLRX: { |
| 14790 | // op: Rt |
| 14791 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14792 | Value |= (op & 0x1f); |
| 14793 | // op: Rn |
| 14794 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14795 | Value |= (op & 0x1f) << 5; |
| 14796 | Value = fixLoadStoreExclusive<0,0>(MI, EncodedValue: Value, STI); |
| 14797 | break; |
| 14798 | } |
| 14799 | case AArch64::LDIAPPW: |
| 14800 | case AArch64::LDIAPPX: |
| 14801 | case AArch64::STILPW: |
| 14802 | case AArch64::STILPX: { |
| 14803 | // op: Rt |
| 14804 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14805 | Value |= (op & 0x1f); |
| 14806 | // op: Rn |
| 14807 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14808 | Value |= (op & 0x1f) << 5; |
| 14809 | // op: Rt2 |
| 14810 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14811 | Value |= (op & 0x1f) << 16; |
| 14812 | break; |
| 14813 | } |
| 14814 | case AArch64::LDBFADD: |
| 14815 | case AArch64::LDBFADDA: |
| 14816 | case AArch64::LDBFADDAL: |
| 14817 | case AArch64::LDBFADDL: |
| 14818 | case AArch64::LDBFMAX: |
| 14819 | case AArch64::LDBFMAXA: |
| 14820 | case AArch64::LDBFMAXAL: |
| 14821 | case AArch64::LDBFMAXL: |
| 14822 | case AArch64::LDBFMAXNM: |
| 14823 | case AArch64::LDBFMAXNMA: |
| 14824 | case AArch64::LDBFMAXNMAL: |
| 14825 | case AArch64::LDBFMAXNML: |
| 14826 | case AArch64::LDBFMIN: |
| 14827 | case AArch64::LDBFMINA: |
| 14828 | case AArch64::LDBFMINAL: |
| 14829 | case AArch64::LDBFMINL: |
| 14830 | case AArch64::LDBFMINNM: |
| 14831 | case AArch64::LDBFMINNMA: |
| 14832 | case AArch64::LDBFMINNMAL: |
| 14833 | case AArch64::LDBFMINNML: |
| 14834 | case AArch64::LDFADDAD: |
| 14835 | case AArch64::LDFADDAH: |
| 14836 | case AArch64::LDFADDALD: |
| 14837 | case AArch64::LDFADDALH: |
| 14838 | case AArch64::LDFADDALS: |
| 14839 | case AArch64::LDFADDAS: |
| 14840 | case AArch64::LDFADDD: |
| 14841 | case AArch64::LDFADDH: |
| 14842 | case AArch64::LDFADDLD: |
| 14843 | case AArch64::LDFADDLH: |
| 14844 | case AArch64::LDFADDLS: |
| 14845 | case AArch64::LDFADDS: |
| 14846 | case AArch64::LDFMAXAD: |
| 14847 | case AArch64::LDFMAXAH: |
| 14848 | case AArch64::LDFMAXALD: |
| 14849 | case AArch64::LDFMAXALH: |
| 14850 | case AArch64::LDFMAXALS: |
| 14851 | case AArch64::LDFMAXAS: |
| 14852 | case AArch64::LDFMAXD: |
| 14853 | case AArch64::LDFMAXH: |
| 14854 | case AArch64::LDFMAXLD: |
| 14855 | case AArch64::LDFMAXLH: |
| 14856 | case AArch64::LDFMAXLS: |
| 14857 | case AArch64::LDFMAXNMAD: |
| 14858 | case AArch64::LDFMAXNMAH: |
| 14859 | case AArch64::LDFMAXNMALD: |
| 14860 | case AArch64::LDFMAXNMALH: |
| 14861 | case AArch64::LDFMAXNMALS: |
| 14862 | case AArch64::LDFMAXNMAS: |
| 14863 | case AArch64::LDFMAXNMD: |
| 14864 | case AArch64::LDFMAXNMH: |
| 14865 | case AArch64::LDFMAXNMLD: |
| 14866 | case AArch64::LDFMAXNMLH: |
| 14867 | case AArch64::LDFMAXNMLS: |
| 14868 | case AArch64::LDFMAXNMS: |
| 14869 | case AArch64::LDFMAXS: |
| 14870 | case AArch64::LDFMINAD: |
| 14871 | case AArch64::LDFMINAH: |
| 14872 | case AArch64::LDFMINALD: |
| 14873 | case AArch64::LDFMINALH: |
| 14874 | case AArch64::LDFMINALS: |
| 14875 | case AArch64::LDFMINAS: |
| 14876 | case AArch64::LDFMIND: |
| 14877 | case AArch64::LDFMINH: |
| 14878 | case AArch64::LDFMINLD: |
| 14879 | case AArch64::LDFMINLH: |
| 14880 | case AArch64::LDFMINLS: |
| 14881 | case AArch64::LDFMINNMAD: |
| 14882 | case AArch64::LDFMINNMAH: |
| 14883 | case AArch64::LDFMINNMALD: |
| 14884 | case AArch64::LDFMINNMALH: |
| 14885 | case AArch64::LDFMINNMALS: |
| 14886 | case AArch64::LDFMINNMAS: |
| 14887 | case AArch64::LDFMINNMD: |
| 14888 | case AArch64::LDFMINNMH: |
| 14889 | case AArch64::LDFMINNMLD: |
| 14890 | case AArch64::LDFMINNMLH: |
| 14891 | case AArch64::LDFMINNMLS: |
| 14892 | case AArch64::LDFMINNMS: |
| 14893 | case AArch64::LDFMINS: { |
| 14894 | // op: Rt |
| 14895 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14896 | Value |= (op & 0x1f); |
| 14897 | // op: Rs |
| 14898 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14899 | Value |= (op & 0x1f) << 16; |
| 14900 | // op: Rn |
| 14901 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14902 | Value |= (op & 0x1f) << 5; |
| 14903 | break; |
| 14904 | } |
| 14905 | case AArch64::LDNPDi: |
| 14906 | case AArch64::LDNPQi: |
| 14907 | case AArch64::LDNPSi: |
| 14908 | case AArch64::LDNPWi: |
| 14909 | case AArch64::LDNPXi: |
| 14910 | case AArch64::LDPDi: |
| 14911 | case AArch64::LDPQi: |
| 14912 | case AArch64::LDPSWi: |
| 14913 | case AArch64::LDPSi: |
| 14914 | case AArch64::LDPWi: |
| 14915 | case AArch64::LDPXi: |
| 14916 | case AArch64::LDTNPQi: |
| 14917 | case AArch64::LDTNPXi: |
| 14918 | case AArch64::LDTPQi: |
| 14919 | case AArch64::LDTPi: |
| 14920 | case AArch64::STGPi: |
| 14921 | case AArch64::STNPDi: |
| 14922 | case AArch64::STNPQi: |
| 14923 | case AArch64::STNPSi: |
| 14924 | case AArch64::STNPWi: |
| 14925 | case AArch64::STNPXi: |
| 14926 | case AArch64::STPDi: |
| 14927 | case AArch64::STPQi: |
| 14928 | case AArch64::STPSi: |
| 14929 | case AArch64::STPWi: |
| 14930 | case AArch64::STPXi: |
| 14931 | case AArch64::STTNPQi: |
| 14932 | case AArch64::STTNPXi: |
| 14933 | case AArch64::STTPQi: |
| 14934 | case AArch64::STTPi: { |
| 14935 | // op: Rt |
| 14936 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14937 | Value |= (op & 0x1f); |
| 14938 | // op: Rt2 |
| 14939 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14940 | Value |= (op & 0x1f) << 10; |
| 14941 | // op: Rn |
| 14942 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14943 | Value |= (op & 0x1f) << 5; |
| 14944 | // op: offset |
| 14945 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 14946 | Value |= (op & 0x7f) << 15; |
| 14947 | break; |
| 14948 | } |
| 14949 | case AArch64::LDAXPW: |
| 14950 | case AArch64::LDAXPX: |
| 14951 | case AArch64::LDXPW: |
| 14952 | case AArch64::LDXPX: { |
| 14953 | // op: Rt |
| 14954 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14955 | Value |= (op & 0x1f); |
| 14956 | // op: Rt2 |
| 14957 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14958 | Value |= (op & 0x1f) << 10; |
| 14959 | // op: Rn |
| 14960 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14961 | Value |= (op & 0x1f) << 5; |
| 14962 | Value = fixLoadStoreExclusive<0,1>(MI, EncodedValue: Value, STI); |
| 14963 | break; |
| 14964 | } |
| 14965 | case AArch64::LDAPPi: |
| 14966 | case AArch64::LDAPi: |
| 14967 | case AArch64::STLPi: { |
| 14968 | // op: Rt |
| 14969 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14970 | Value |= (op & 0x1f); |
| 14971 | // op: Rt2 |
| 14972 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14973 | Value |= (op & 0x1f) << 16; |
| 14974 | // op: Rn |
| 14975 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 14976 | Value |= (op & 0x1f) << 5; |
| 14977 | break; |
| 14978 | } |
| 14979 | case AArch64::TBNZW: |
| 14980 | case AArch64::TBNZX: |
| 14981 | case AArch64::TBZW: |
| 14982 | case AArch64::TBZX: { |
| 14983 | // op: Rt |
| 14984 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 14985 | Value |= (op & 0x1f); |
| 14986 | // op: bit_off |
| 14987 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 14988 | Value |= (op & 0x1f) << 19; |
| 14989 | // op: target |
| 14990 | op = getTestBranchTargetOpValue(MI, OpIdx: 2, Fixups, STI); |
| 14991 | Value |= (op & 0x3fff) << 5; |
| 14992 | break; |
| 14993 | } |
| 14994 | case AArch64::CBEQWri: |
| 14995 | case AArch64::CBEQXri: |
| 14996 | case AArch64::CBGTWri: |
| 14997 | case AArch64::CBGTXri: |
| 14998 | case AArch64::CBHIWri: |
| 14999 | case AArch64::CBHIXri: |
| 15000 | case AArch64::CBLOWri: |
| 15001 | case AArch64::CBLOXri: |
| 15002 | case AArch64::CBLTWri: |
| 15003 | case AArch64::CBLTXri: |
| 15004 | case AArch64::CBNEWri: |
| 15005 | case AArch64::CBNEXri: { |
| 15006 | // op: Rt |
| 15007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15008 | Value |= (op & 0x1f); |
| 15009 | // op: imm |
| 15010 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15011 | Value |= (op & 0x3f) << 15; |
| 15012 | // op: target |
| 15013 | op = getCondCompBranchTargetOpValue(MI, OpIdx: 2, Fixups, STI); |
| 15014 | Value |= (op & 0x1ff) << 5; |
| 15015 | break; |
| 15016 | } |
| 15017 | case AArch64::LDRDl: |
| 15018 | case AArch64::LDRQl: |
| 15019 | case AArch64::LDRSWl: |
| 15020 | case AArch64::LDRSl: |
| 15021 | case AArch64::LDRWl: |
| 15022 | case AArch64::LDRXl: |
| 15023 | case AArch64::PRFMl: { |
| 15024 | // op: Rt |
| 15025 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15026 | Value |= (op & 0x1f); |
| 15027 | // op: label |
| 15028 | op = getLoadLiteralOpValue(MI, OpIdx: 1, Fixups, STI); |
| 15029 | Value |= (op & 0x7ffff) << 5; |
| 15030 | break; |
| 15031 | } |
| 15032 | case AArch64::SYSLxt: { |
| 15033 | // op: Rt |
| 15034 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15035 | Value |= (op & 0x1f); |
| 15036 | // op: op1 |
| 15037 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15038 | Value |= (op & 0x7) << 16; |
| 15039 | // op: Cn |
| 15040 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15041 | Value |= (op & 0xf) << 12; |
| 15042 | // op: Cm |
| 15043 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15044 | Value |= (op & 0xf) << 8; |
| 15045 | // op: op2 |
| 15046 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15047 | Value |= (op & 0x7) << 5; |
| 15048 | break; |
| 15049 | } |
| 15050 | case AArch64::MRRS: |
| 15051 | case AArch64::MRS: { |
| 15052 | // op: Rt |
| 15053 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15054 | Value |= (op & 0x1f); |
| 15055 | // op: systemreg |
| 15056 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15057 | Value |= (op & 0xffff) << 5; |
| 15058 | break; |
| 15059 | } |
| 15060 | case AArch64::CBNZW: |
| 15061 | case AArch64::CBNZX: |
| 15062 | case AArch64::CBZW: |
| 15063 | case AArch64::CBZX: { |
| 15064 | // op: Rt |
| 15065 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15066 | Value |= (op & 0x1f); |
| 15067 | // op: target |
| 15068 | op = getCondBranchTargetOpValue(MI, OpIdx: 1, Fixups, STI); |
| 15069 | Value |= (op & 0x7ffff) << 5; |
| 15070 | break; |
| 15071 | } |
| 15072 | case AArch64::RPRFM: { |
| 15073 | // op: Rt |
| 15074 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15075 | Value |= (op & 0x20) << 10; |
| 15076 | Value |= (op & 0x18) << 9; |
| 15077 | Value |= (op & 0x7); |
| 15078 | // op: Rn |
| 15079 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15080 | Value |= (op & 0x1f) << 5; |
| 15081 | // op: Rm |
| 15082 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15083 | Value |= (op & 0x1f) << 16; |
| 15084 | break; |
| 15085 | } |
| 15086 | case AArch64::LDAPRWpost: |
| 15087 | case AArch64::LDAPRXpost: |
| 15088 | case AArch64::STLRWpre: |
| 15089 | case AArch64::STLRXpre: { |
| 15090 | // op: Rt |
| 15091 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15092 | Value |= (op & 0x1f); |
| 15093 | // op: Rn |
| 15094 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15095 | Value |= (op & 0x1f) << 5; |
| 15096 | break; |
| 15097 | } |
| 15098 | case AArch64::ST64BV: |
| 15099 | case AArch64::ST64BV0: |
| 15100 | case AArch64::STL64BV: |
| 15101 | case AArch64::STL64BV0: { |
| 15102 | // op: Rt |
| 15103 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15104 | Value |= (op & 0x1f); |
| 15105 | // op: Rn |
| 15106 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15107 | Value |= (op & 0x1f) << 5; |
| 15108 | // op: Rs |
| 15109 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15110 | Value |= (op & 0x1f) << 16; |
| 15111 | break; |
| 15112 | } |
| 15113 | case AArch64::STTXRWr: |
| 15114 | case AArch64::STTXRXr: { |
| 15115 | // op: Rt |
| 15116 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15117 | Value |= (op & 0x1f); |
| 15118 | // op: Rn |
| 15119 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15120 | Value |= (op & 0x1f) << 5; |
| 15121 | // op: Ws |
| 15122 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15123 | Value |= (op & 0x1f) << 16; |
| 15124 | Value = fixLoadStoreExclusive<1,0>(MI, EncodedValue: Value, STI); |
| 15125 | break; |
| 15126 | } |
| 15127 | case AArch64::LDRBBpost: |
| 15128 | case AArch64::LDRBBpre: |
| 15129 | case AArch64::LDRBpost: |
| 15130 | case AArch64::LDRBpre: |
| 15131 | case AArch64::LDRDpost: |
| 15132 | case AArch64::LDRDpre: |
| 15133 | case AArch64::LDRHHpost: |
| 15134 | case AArch64::LDRHHpre: |
| 15135 | case AArch64::LDRHpost: |
| 15136 | case AArch64::LDRHpre: |
| 15137 | case AArch64::LDRQpost: |
| 15138 | case AArch64::LDRQpre: |
| 15139 | case AArch64::LDRSBWpost: |
| 15140 | case AArch64::LDRSBWpre: |
| 15141 | case AArch64::LDRSBXpost: |
| 15142 | case AArch64::LDRSBXpre: |
| 15143 | case AArch64::LDRSHWpost: |
| 15144 | case AArch64::LDRSHWpre: |
| 15145 | case AArch64::LDRSHXpost: |
| 15146 | case AArch64::LDRSHXpre: |
| 15147 | case AArch64::LDRSWpost: |
| 15148 | case AArch64::LDRSWpre: |
| 15149 | case AArch64::LDRSpost: |
| 15150 | case AArch64::LDRSpre: |
| 15151 | case AArch64::LDRWpost: |
| 15152 | case AArch64::LDRWpre: |
| 15153 | case AArch64::LDRXpost: |
| 15154 | case AArch64::LDRXpre: |
| 15155 | case AArch64::STRBBpost: |
| 15156 | case AArch64::STRBBpre: |
| 15157 | case AArch64::STRBpost: |
| 15158 | case AArch64::STRBpre: |
| 15159 | case AArch64::STRDpost: |
| 15160 | case AArch64::STRDpre: |
| 15161 | case AArch64::STRHHpost: |
| 15162 | case AArch64::STRHHpre: |
| 15163 | case AArch64::STRHpost: |
| 15164 | case AArch64::STRHpre: |
| 15165 | case AArch64::STRQpost: |
| 15166 | case AArch64::STRQpre: |
| 15167 | case AArch64::STRSpost: |
| 15168 | case AArch64::STRSpre: |
| 15169 | case AArch64::STRWpost: |
| 15170 | case AArch64::STRWpre: |
| 15171 | case AArch64::STRXpost: |
| 15172 | case AArch64::STRXpre: { |
| 15173 | // op: Rt |
| 15174 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15175 | Value |= (op & 0x1f); |
| 15176 | // op: Rn |
| 15177 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15178 | Value |= (op & 0x1f) << 5; |
| 15179 | // op: offset |
| 15180 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15181 | Value |= (op & 0x1ff) << 12; |
| 15182 | break; |
| 15183 | } |
| 15184 | case AArch64::LDIAPPWpost: |
| 15185 | case AArch64::LDIAPPXpost: |
| 15186 | case AArch64::STILPWpre: |
| 15187 | case AArch64::STILPXpre: { |
| 15188 | // op: Rt |
| 15189 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15190 | Value |= (op & 0x1f); |
| 15191 | // op: Rn |
| 15192 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15193 | Value |= (op & 0x1f) << 5; |
| 15194 | // op: Rt2 |
| 15195 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15196 | Value |= (op & 0x1f) << 16; |
| 15197 | break; |
| 15198 | } |
| 15199 | case AArch64::LDPDpost: |
| 15200 | case AArch64::LDPDpre: |
| 15201 | case AArch64::LDPQpost: |
| 15202 | case AArch64::LDPQpre: |
| 15203 | case AArch64::LDPSWpost: |
| 15204 | case AArch64::LDPSWpre: |
| 15205 | case AArch64::LDPSpost: |
| 15206 | case AArch64::LDPSpre: |
| 15207 | case AArch64::LDPWpost: |
| 15208 | case AArch64::LDPWpre: |
| 15209 | case AArch64::LDPXpost: |
| 15210 | case AArch64::LDPXpre: |
| 15211 | case AArch64::LDTPQpost: |
| 15212 | case AArch64::LDTPQpre: |
| 15213 | case AArch64::LDTPpost: |
| 15214 | case AArch64::LDTPpre: |
| 15215 | case AArch64::STGPpost: |
| 15216 | case AArch64::STGPpre: |
| 15217 | case AArch64::STPDpost: |
| 15218 | case AArch64::STPDpre: |
| 15219 | case AArch64::STPQpost: |
| 15220 | case AArch64::STPQpre: |
| 15221 | case AArch64::STPSpost: |
| 15222 | case AArch64::STPSpre: |
| 15223 | case AArch64::STPWpost: |
| 15224 | case AArch64::STPWpre: |
| 15225 | case AArch64::STPXpost: |
| 15226 | case AArch64::STPXpre: |
| 15227 | case AArch64::STTPQpost: |
| 15228 | case AArch64::STTPQpre: |
| 15229 | case AArch64::STTPpost: |
| 15230 | case AArch64::STTPpre: { |
| 15231 | // op: Rt |
| 15232 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15233 | Value |= (op & 0x1f); |
| 15234 | // op: Rt2 |
| 15235 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15236 | Value |= (op & 0x1f) << 10; |
| 15237 | // op: Rn |
| 15238 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15239 | Value |= (op & 0x1f) << 5; |
| 15240 | // op: offset |
| 15241 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15242 | Value |= (op & 0x7f) << 15; |
| 15243 | break; |
| 15244 | } |
| 15245 | case AArch64::MSR: |
| 15246 | case AArch64::MSRR: { |
| 15247 | // op: Rt |
| 15248 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15249 | Value |= (op & 0x1f); |
| 15250 | // op: systemreg |
| 15251 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15252 | Value |= (op & 0xffff) << 5; |
| 15253 | break; |
| 15254 | } |
| 15255 | case AArch64::LDCLRP: |
| 15256 | case AArch64::LDCLRPA: |
| 15257 | case AArch64::LDCLRPAL: |
| 15258 | case AArch64::LDCLRPL: |
| 15259 | case AArch64::LDSETP: |
| 15260 | case AArch64::LDSETPA: |
| 15261 | case AArch64::LDSETPAL: |
| 15262 | case AArch64::LDSETPL: |
| 15263 | case AArch64::SWPP: |
| 15264 | case AArch64::SWPPA: |
| 15265 | case AArch64::SWPPAL: |
| 15266 | case AArch64::SWPPL: { |
| 15267 | // op: Rt |
| 15268 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15269 | Value |= (op & 0x1f); |
| 15270 | // op: Rt2 |
| 15271 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15272 | Value |= (op & 0x1f) << 16; |
| 15273 | // op: Rn |
| 15274 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15275 | Value |= (op & 0x1f) << 5; |
| 15276 | break; |
| 15277 | } |
| 15278 | case AArch64::SYSPxt: |
| 15279 | case AArch64::SYSxt: { |
| 15280 | // op: Rt |
| 15281 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15282 | Value |= (op & 0x1f); |
| 15283 | // op: op1 |
| 15284 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15285 | Value |= (op & 0x7) << 16; |
| 15286 | // op: Cn |
| 15287 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15288 | Value |= (op & 0xf) << 12; |
| 15289 | // op: Cm |
| 15290 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15291 | Value |= (op & 0xf) << 8; |
| 15292 | // op: op2 |
| 15293 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15294 | Value |= (op & 0x7) << 5; |
| 15295 | break; |
| 15296 | } |
| 15297 | case AArch64::RCWCLRP: |
| 15298 | case AArch64::RCWCLRPA: |
| 15299 | case AArch64::RCWCLRPAL: |
| 15300 | case AArch64::RCWCLRPL: |
| 15301 | case AArch64::RCWCLRSP: |
| 15302 | case AArch64::RCWCLRSPA: |
| 15303 | case AArch64::RCWCLRSPAL: |
| 15304 | case AArch64::RCWCLRSPL: |
| 15305 | case AArch64::RCWSETP: |
| 15306 | case AArch64::RCWSETPA: |
| 15307 | case AArch64::RCWSETPAL: |
| 15308 | case AArch64::RCWSETPL: |
| 15309 | case AArch64::RCWSETSP: |
| 15310 | case AArch64::RCWSETSPA: |
| 15311 | case AArch64::RCWSETSPAL: |
| 15312 | case AArch64::RCWSETSPL: |
| 15313 | case AArch64::RCWSWPP: |
| 15314 | case AArch64::RCWSWPPA: |
| 15315 | case AArch64::RCWSWPPAL: |
| 15316 | case AArch64::RCWSWPPL: |
| 15317 | case AArch64::RCWSWPSP: |
| 15318 | case AArch64::RCWSWPSPA: |
| 15319 | case AArch64::RCWSWPSPAL: |
| 15320 | case AArch64::RCWSWPSPL: { |
| 15321 | // op: Rt2 |
| 15322 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15323 | Value |= (op & 0x1f) << 16; |
| 15324 | // op: Rn |
| 15325 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15326 | Value |= (op & 0x1f) << 5; |
| 15327 | // op: Rt |
| 15328 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15329 | Value |= (op & 0x1f); |
| 15330 | break; |
| 15331 | } |
| 15332 | case AArch64::LDR_ZA: |
| 15333 | case AArch64::STR_ZA: { |
| 15334 | // op: Rv |
| 15335 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 1, Fixups, STI); |
| 15336 | Value |= (op & 0x3) << 13; |
| 15337 | // op: Rn |
| 15338 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15339 | Value |= (op & 0x1f) << 5; |
| 15340 | // op: imm4 |
| 15341 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15342 | Value |= (op & 0xf); |
| 15343 | break; |
| 15344 | } |
| 15345 | case AArch64::INSERT_MXIPZ_H_H: |
| 15346 | case AArch64::INSERT_MXIPZ_V_H: { |
| 15347 | // op: Rv |
| 15348 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 15349 | Value |= (op & 0x3) << 13; |
| 15350 | // op: Pg |
| 15351 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15352 | Value |= (op & 0x7) << 10; |
| 15353 | // op: Zn |
| 15354 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 15355 | Value |= (op & 0x1f) << 5; |
| 15356 | // op: ZAd |
| 15357 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15358 | Value |= (op & 0x1) << 3; |
| 15359 | // op: imm |
| 15360 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15361 | Value |= (op & 0x7); |
| 15362 | break; |
| 15363 | } |
| 15364 | case AArch64::INSERT_MXIPZ_H_S: |
| 15365 | case AArch64::INSERT_MXIPZ_V_S: { |
| 15366 | // op: Rv |
| 15367 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 15368 | Value |= (op & 0x3) << 13; |
| 15369 | // op: Pg |
| 15370 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15371 | Value |= (op & 0x7) << 10; |
| 15372 | // op: Zn |
| 15373 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 15374 | Value |= (op & 0x1f) << 5; |
| 15375 | // op: ZAd |
| 15376 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15377 | Value |= (op & 0x3) << 2; |
| 15378 | // op: imm |
| 15379 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15380 | Value |= (op & 0x3); |
| 15381 | break; |
| 15382 | } |
| 15383 | case AArch64::INSERT_MXIPZ_H_D: |
| 15384 | case AArch64::INSERT_MXIPZ_V_D: { |
| 15385 | // op: Rv |
| 15386 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 15387 | Value |= (op & 0x3) << 13; |
| 15388 | // op: Pg |
| 15389 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15390 | Value |= (op & 0x7) << 10; |
| 15391 | // op: Zn |
| 15392 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 15393 | Value |= (op & 0x1f) << 5; |
| 15394 | // op: ZAd |
| 15395 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15396 | Value |= (op & 0x7) << 1; |
| 15397 | // op: imm |
| 15398 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15399 | Value |= (op & 0x1); |
| 15400 | break; |
| 15401 | } |
| 15402 | case AArch64::INSERT_MXIPZ_H_Q: |
| 15403 | case AArch64::INSERT_MXIPZ_V_Q: { |
| 15404 | // op: Rv |
| 15405 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 15406 | Value |= (op & 0x3) << 13; |
| 15407 | // op: Pg |
| 15408 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15409 | Value |= (op & 0x7) << 10; |
| 15410 | // op: Zn |
| 15411 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 15412 | Value |= (op & 0x1f) << 5; |
| 15413 | // op: ZAd |
| 15414 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15415 | Value |= (op & 0xf); |
| 15416 | break; |
| 15417 | } |
| 15418 | case AArch64::INSERT_MXIPZ_H_B: |
| 15419 | case AArch64::INSERT_MXIPZ_V_B: { |
| 15420 | // op: Rv |
| 15421 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 15422 | Value |= (op & 0x3) << 13; |
| 15423 | // op: Pg |
| 15424 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15425 | Value |= (op & 0x7) << 10; |
| 15426 | // op: Zn |
| 15427 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 15428 | Value |= (op & 0x1f) << 5; |
| 15429 | // op: imm |
| 15430 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15431 | Value |= (op & 0xf); |
| 15432 | break; |
| 15433 | } |
| 15434 | case AArch64::PSEL_PPPRI_D: { |
| 15435 | // op: Rv |
| 15436 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 15437 | Value |= (op & 0x3) << 16; |
| 15438 | // op: Pn |
| 15439 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15440 | Value |= (op & 0xf) << 10; |
| 15441 | // op: Pm |
| 15442 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15443 | Value |= (op & 0xf) << 5; |
| 15444 | // op: Pd |
| 15445 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15446 | Value |= (op & 0xf); |
| 15447 | // op: imm |
| 15448 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15449 | Value |= (op & 0x1) << 23; |
| 15450 | break; |
| 15451 | } |
| 15452 | case AArch64::PSEL_PPPRI_S: { |
| 15453 | // op: Rv |
| 15454 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 15455 | Value |= (op & 0x3) << 16; |
| 15456 | // op: Pn |
| 15457 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15458 | Value |= (op & 0xf) << 10; |
| 15459 | // op: Pm |
| 15460 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15461 | Value |= (op & 0xf) << 5; |
| 15462 | // op: Pd |
| 15463 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15464 | Value |= (op & 0xf); |
| 15465 | // op: imm |
| 15466 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15467 | Value |= (op & 0x3) << 22; |
| 15468 | break; |
| 15469 | } |
| 15470 | case AArch64::PSEL_PPPRI_H: { |
| 15471 | // op: Rv |
| 15472 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 15473 | Value |= (op & 0x3) << 16; |
| 15474 | // op: Pn |
| 15475 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15476 | Value |= (op & 0xf) << 10; |
| 15477 | // op: Pm |
| 15478 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15479 | Value |= (op & 0xf) << 5; |
| 15480 | // op: Pd |
| 15481 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15482 | Value |= (op & 0xf); |
| 15483 | // op: imm |
| 15484 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15485 | Value |= (op & 0x6) << 21; |
| 15486 | Value |= (op & 0x1) << 20; |
| 15487 | break; |
| 15488 | } |
| 15489 | case AArch64::PSEL_PPPRI_B: { |
| 15490 | // op: Rv |
| 15491 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 15492 | Value |= (op & 0x3) << 16; |
| 15493 | // op: Pn |
| 15494 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15495 | Value |= (op & 0xf) << 10; |
| 15496 | // op: Pm |
| 15497 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15498 | Value |= (op & 0xf) << 5; |
| 15499 | // op: Pd |
| 15500 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15501 | Value |= (op & 0xf); |
| 15502 | // op: imm |
| 15503 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15504 | Value |= (op & 0xc) << 20; |
| 15505 | Value |= (op & 0x3) << 19; |
| 15506 | break; |
| 15507 | } |
| 15508 | case AArch64::EXTRACT_ZPMXI_H_H: |
| 15509 | case AArch64::EXTRACT_ZPMXI_V_H: { |
| 15510 | // op: Rv |
| 15511 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI); |
| 15512 | Value |= (op & 0x3) << 13; |
| 15513 | // op: Pg |
| 15514 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15515 | Value |= (op & 0x7) << 10; |
| 15516 | // op: Zd |
| 15517 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15518 | Value |= (op & 0x1f); |
| 15519 | // op: ZAn |
| 15520 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15521 | Value |= (op & 0x1) << 8; |
| 15522 | // op: imm |
| 15523 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 15524 | Value |= (op & 0x7) << 5; |
| 15525 | break; |
| 15526 | } |
| 15527 | case AArch64::EXTRACT_ZPMXI_H_S: |
| 15528 | case AArch64::EXTRACT_ZPMXI_V_S: { |
| 15529 | // op: Rv |
| 15530 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI); |
| 15531 | Value |= (op & 0x3) << 13; |
| 15532 | // op: Pg |
| 15533 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15534 | Value |= (op & 0x7) << 10; |
| 15535 | // op: Zd |
| 15536 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15537 | Value |= (op & 0x1f); |
| 15538 | // op: ZAn |
| 15539 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15540 | Value |= (op & 0x3) << 7; |
| 15541 | // op: imm |
| 15542 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 15543 | Value |= (op & 0x3) << 5; |
| 15544 | break; |
| 15545 | } |
| 15546 | case AArch64::EXTRACT_ZPMXI_H_D: |
| 15547 | case AArch64::EXTRACT_ZPMXI_V_D: { |
| 15548 | // op: Rv |
| 15549 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI); |
| 15550 | Value |= (op & 0x3) << 13; |
| 15551 | // op: Pg |
| 15552 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15553 | Value |= (op & 0x7) << 10; |
| 15554 | // op: Zd |
| 15555 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15556 | Value |= (op & 0x1f); |
| 15557 | // op: ZAn |
| 15558 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15559 | Value |= (op & 0x7) << 6; |
| 15560 | // op: imm |
| 15561 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 15562 | Value |= (op & 0x1) << 5; |
| 15563 | break; |
| 15564 | } |
| 15565 | case AArch64::EXTRACT_ZPMXI_H_Q: |
| 15566 | case AArch64::EXTRACT_ZPMXI_V_Q: { |
| 15567 | // op: Rv |
| 15568 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI); |
| 15569 | Value |= (op & 0x3) << 13; |
| 15570 | // op: Pg |
| 15571 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15572 | Value |= (op & 0x7) << 10; |
| 15573 | // op: Zd |
| 15574 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15575 | Value |= (op & 0x1f); |
| 15576 | // op: ZAn |
| 15577 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15578 | Value |= (op & 0xf) << 5; |
| 15579 | break; |
| 15580 | } |
| 15581 | case AArch64::EXTRACT_ZPMXI_H_B: |
| 15582 | case AArch64::EXTRACT_ZPMXI_V_B: { |
| 15583 | // op: Rv |
| 15584 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 4, Fixups, STI); |
| 15585 | Value |= (op & 0x3) << 13; |
| 15586 | // op: Pg |
| 15587 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15588 | Value |= (op & 0x7) << 10; |
| 15589 | // op: Zd |
| 15590 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15591 | Value |= (op & 0x1f); |
| 15592 | // op: imm |
| 15593 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 15594 | Value |= (op & 0xf) << 5; |
| 15595 | break; |
| 15596 | } |
| 15597 | case AArch64::BFMLAL_VG2_M2Z2Z_HtoS: |
| 15598 | case AArch64::BFMLSL_VG2_M2Z2Z_HtoS: |
| 15599 | case AArch64::FMLAL_VG2_M2Z2Z_BtoH: |
| 15600 | case AArch64::FMLAL_VG2_M2Z2Z_HtoS: |
| 15601 | case AArch64::FMLSL_VG2_M2Z2Z_HtoS: |
| 15602 | case AArch64::SMLAL_VG2_M2Z2Z_HtoS: |
| 15603 | case AArch64::SMLSL_VG2_M2Z2Z_HtoS: |
| 15604 | case AArch64::UMLAL_VG2_M2Z2Z_HtoS: |
| 15605 | case AArch64::UMLSL_VG2_M2Z2Z_HtoS: { |
| 15606 | // op: Rv |
| 15607 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 15608 | Value |= (op & 0x3) << 13; |
| 15609 | // op: Zm |
| 15610 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 5, Fixups, STI); |
| 15611 | Value |= (op & 0xf) << 17; |
| 15612 | // op: Zn |
| 15613 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 15614 | Value |= (op & 0xf) << 6; |
| 15615 | // op: imm |
| 15616 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15617 | Value |= (op & 0x3); |
| 15618 | break; |
| 15619 | } |
| 15620 | case AArch64::BFMLAL_VG4_M4Z4Z_HtoS: |
| 15621 | case AArch64::BFMLSL_VG4_M4Z4Z_HtoS: |
| 15622 | case AArch64::FMLAL_VG4_M4Z4Z_BtoH: |
| 15623 | case AArch64::FMLAL_VG4_M4Z4Z_HtoS: |
| 15624 | case AArch64::FMLSL_VG4_M4Z4Z_HtoS: |
| 15625 | case AArch64::SMLAL_VG4_M4Z4Z_HtoS: |
| 15626 | case AArch64::SMLSL_VG4_M4Z4Z_HtoS: |
| 15627 | case AArch64::UMLAL_VG4_M4Z4Z_HtoS: |
| 15628 | case AArch64::UMLSL_VG4_M4Z4Z_HtoS: { |
| 15629 | // op: Rv |
| 15630 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 15631 | Value |= (op & 0x3) << 13; |
| 15632 | // op: Zm |
| 15633 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 5, Fixups, STI); |
| 15634 | Value |= (op & 0x7) << 18; |
| 15635 | // op: Zn |
| 15636 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 15637 | Value |= (op & 0x7) << 7; |
| 15638 | // op: imm |
| 15639 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15640 | Value |= (op & 0x3); |
| 15641 | break; |
| 15642 | } |
| 15643 | case AArch64::BFMLAL_VG2_M2ZZ_HtoS: |
| 15644 | case AArch64::BFMLAL_VG4_M4ZZ_HtoS: |
| 15645 | case AArch64::BFMLSL_VG2_M2ZZ_HtoS: |
| 15646 | case AArch64::BFMLSL_VG4_M4ZZ_HtoS: |
| 15647 | case AArch64::FMLAL_VG2_M2ZZ_BtoH: |
| 15648 | case AArch64::FMLAL_VG2_M2ZZ_HtoS: |
| 15649 | case AArch64::FMLAL_VG4_M4ZZ_BtoH: |
| 15650 | case AArch64::FMLAL_VG4_M4ZZ_HtoS: |
| 15651 | case AArch64::FMLSL_VG2_M2ZZ_HtoS: |
| 15652 | case AArch64::FMLSL_VG4_M4ZZ_HtoS: |
| 15653 | case AArch64::SMLAL_VG2_M2ZZ_HtoS: |
| 15654 | case AArch64::SMLAL_VG4_M4ZZ_HtoS: |
| 15655 | case AArch64::SMLSL_VG2_M2ZZ_HtoS: |
| 15656 | case AArch64::SMLSL_VG4_M4ZZ_HtoS: |
| 15657 | case AArch64::UMLAL_VG2_M2ZZ_HtoS: |
| 15658 | case AArch64::UMLAL_VG4_M4ZZ_HtoS: |
| 15659 | case AArch64::UMLSL_VG2_M2ZZ_HtoS: |
| 15660 | case AArch64::UMLSL_VG4_M4ZZ_HtoS: { |
| 15661 | // op: Rv |
| 15662 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 15663 | Value |= (op & 0x3) << 13; |
| 15664 | // op: Zm |
| 15665 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 15666 | Value |= (op & 0xf) << 16; |
| 15667 | // op: Zn |
| 15668 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15669 | Value |= (op & 0x1f) << 5; |
| 15670 | // op: imm |
| 15671 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15672 | Value |= (op & 0x3); |
| 15673 | break; |
| 15674 | } |
| 15675 | case AArch64::BFMLAL_MZZ_HtoS: |
| 15676 | case AArch64::BFMLSL_MZZ_HtoS: |
| 15677 | case AArch64::FMLAL_MZZ_HtoS: |
| 15678 | case AArch64::FMLAL_VG2_MZZ_BtoH: |
| 15679 | case AArch64::FMLSL_MZZ_HtoS: |
| 15680 | case AArch64::SMLAL_MZZ_HtoS: |
| 15681 | case AArch64::SMLSL_MZZ_HtoS: |
| 15682 | case AArch64::UMLAL_MZZ_HtoS: |
| 15683 | case AArch64::UMLSL_MZZ_HtoS: { |
| 15684 | // op: Rv |
| 15685 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 15686 | Value |= (op & 0x3) << 13; |
| 15687 | // op: Zm |
| 15688 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 15689 | Value |= (op & 0xf) << 16; |
| 15690 | // op: Zn |
| 15691 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15692 | Value |= (op & 0x1f) << 5; |
| 15693 | // op: imm |
| 15694 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15695 | Value |= (op & 0x7); |
| 15696 | break; |
| 15697 | } |
| 15698 | case AArch64::ZERO_MXI_VG2_4Z: |
| 15699 | case AArch64::ZERO_MXI_VG4_4Z: { |
| 15700 | // op: Rv |
| 15701 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 15702 | Value |= (op & 0x3) << 13; |
| 15703 | // op: imm |
| 15704 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15705 | Value |= (op & 0x1); |
| 15706 | break; |
| 15707 | } |
| 15708 | case AArch64::ZERO_MXI_4Z: |
| 15709 | case AArch64::ZERO_MXI_VG2_2Z: |
| 15710 | case AArch64::ZERO_MXI_VG4_2Z: { |
| 15711 | // op: Rv |
| 15712 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 15713 | Value |= (op & 0x3) << 13; |
| 15714 | // op: imm |
| 15715 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15716 | Value |= (op & 0x3); |
| 15717 | break; |
| 15718 | } |
| 15719 | case AArch64::ZERO_MXI_2Z: |
| 15720 | case AArch64::ZERO_MXI_VG2_Z: |
| 15721 | case AArch64::ZERO_MXI_VG4_Z: { |
| 15722 | // op: Rv |
| 15723 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 15724 | Value |= (op & 0x3) << 13; |
| 15725 | // op: imm |
| 15726 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15727 | Value |= (op & 0x7); |
| 15728 | break; |
| 15729 | } |
| 15730 | case AArch64::ADD_VG2_M2Z_D: |
| 15731 | case AArch64::ADD_VG2_M2Z_S: |
| 15732 | case AArch64::BFADD_VG2_M2Z_H: |
| 15733 | case AArch64::BFSUB_VG2_M2Z_H: |
| 15734 | case AArch64::FADD_VG2_M2Z_D: |
| 15735 | case AArch64::FADD_VG2_M2Z_H: |
| 15736 | case AArch64::FADD_VG2_M2Z_S: |
| 15737 | case AArch64::FSUB_VG2_M2Z_D: |
| 15738 | case AArch64::FSUB_VG2_M2Z_H: |
| 15739 | case AArch64::FSUB_VG2_M2Z_S: |
| 15740 | case AArch64::SUB_VG2_M2Z_D: |
| 15741 | case AArch64::SUB_VG2_M2Z_S: { |
| 15742 | // op: Rv |
| 15743 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 15744 | Value |= (op & 0x3) << 13; |
| 15745 | // op: imm3 |
| 15746 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15747 | Value |= (op & 0x7); |
| 15748 | // op: Zm |
| 15749 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 15750 | Value |= (op & 0xf) << 6; |
| 15751 | break; |
| 15752 | } |
| 15753 | case AArch64::ADD_VG4_M4Z_D: |
| 15754 | case AArch64::ADD_VG4_M4Z_S: |
| 15755 | case AArch64::BFADD_VG4_M4Z_H: |
| 15756 | case AArch64::BFSUB_VG4_M4Z_H: |
| 15757 | case AArch64::FADD_VG4_M4Z_D: |
| 15758 | case AArch64::FADD_VG4_M4Z_H: |
| 15759 | case AArch64::FADD_VG4_M4Z_S: |
| 15760 | case AArch64::FSUB_VG4_M4Z_D: |
| 15761 | case AArch64::FSUB_VG4_M4Z_H: |
| 15762 | case AArch64::FSUB_VG4_M4Z_S: |
| 15763 | case AArch64::SUB_VG4_M4Z_D: |
| 15764 | case AArch64::SUB_VG4_M4Z_S: { |
| 15765 | // op: Rv |
| 15766 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 15767 | Value |= (op & 0x3) << 13; |
| 15768 | // op: imm3 |
| 15769 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15770 | Value |= (op & 0x7); |
| 15771 | // op: Zm |
| 15772 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 15773 | Value |= (op & 0x7) << 7; |
| 15774 | break; |
| 15775 | } |
| 15776 | case AArch64::RAX1: |
| 15777 | case AArch64::SM4ENCKEY: |
| 15778 | case AArch64::TBLv16i8Four: |
| 15779 | case AArch64::TBLv16i8One: |
| 15780 | case AArch64::TBLv16i8Three: |
| 15781 | case AArch64::TBLv16i8Two: |
| 15782 | case AArch64::TBLv8i8Four: |
| 15783 | case AArch64::TBLv8i8One: |
| 15784 | case AArch64::TBLv8i8Three: |
| 15785 | case AArch64::TBLv8i8Two: { |
| 15786 | // op: Vd |
| 15787 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15788 | Value |= (op & 0x1f); |
| 15789 | // op: Vn |
| 15790 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15791 | Value |= (op & 0x1f) << 5; |
| 15792 | // op: Vm |
| 15793 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15794 | Value |= (op & 0x1f) << 16; |
| 15795 | break; |
| 15796 | } |
| 15797 | case AArch64::BCAX: |
| 15798 | case AArch64::EOR3: |
| 15799 | case AArch64::SM3SS1: { |
| 15800 | // op: Vd |
| 15801 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15802 | Value |= (op & 0x1f); |
| 15803 | // op: Vn |
| 15804 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15805 | Value |= (op & 0x1f) << 5; |
| 15806 | // op: Vm |
| 15807 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15808 | Value |= (op & 0x1f) << 16; |
| 15809 | // op: Va |
| 15810 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15811 | Value |= (op & 0x1f) << 10; |
| 15812 | break; |
| 15813 | } |
| 15814 | case AArch64::XAR: { |
| 15815 | // op: Vd |
| 15816 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15817 | Value |= (op & 0x1f); |
| 15818 | // op: Vn |
| 15819 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15820 | Value |= (op & 0x1f) << 5; |
| 15821 | // op: imm |
| 15822 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15823 | Value |= (op & 0x3f) << 10; |
| 15824 | // op: Vm |
| 15825 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15826 | Value |= (op & 0x1f) << 16; |
| 15827 | break; |
| 15828 | } |
| 15829 | case AArch64::ADDQV_VPZ_B: |
| 15830 | case AArch64::ADDQV_VPZ_D: |
| 15831 | case AArch64::ADDQV_VPZ_H: |
| 15832 | case AArch64::ADDQV_VPZ_S: |
| 15833 | case AArch64::ANDQV_VPZ_B: |
| 15834 | case AArch64::ANDQV_VPZ_D: |
| 15835 | case AArch64::ANDQV_VPZ_H: |
| 15836 | case AArch64::ANDQV_VPZ_S: |
| 15837 | case AArch64::EORQV_VPZ_B: |
| 15838 | case AArch64::EORQV_VPZ_D: |
| 15839 | case AArch64::EORQV_VPZ_H: |
| 15840 | case AArch64::EORQV_VPZ_S: |
| 15841 | case AArch64::FADDQV_D: |
| 15842 | case AArch64::FADDQV_H: |
| 15843 | case AArch64::FADDQV_S: |
| 15844 | case AArch64::FMAXNMQV_D: |
| 15845 | case AArch64::FMAXNMQV_H: |
| 15846 | case AArch64::FMAXNMQV_S: |
| 15847 | case AArch64::FMAXQV_D: |
| 15848 | case AArch64::FMAXQV_H: |
| 15849 | case AArch64::FMAXQV_S: |
| 15850 | case AArch64::FMINNMQV_D: |
| 15851 | case AArch64::FMINNMQV_H: |
| 15852 | case AArch64::FMINNMQV_S: |
| 15853 | case AArch64::FMINQV_D: |
| 15854 | case AArch64::FMINQV_H: |
| 15855 | case AArch64::FMINQV_S: |
| 15856 | case AArch64::ORQV_VPZ_B: |
| 15857 | case AArch64::ORQV_VPZ_D: |
| 15858 | case AArch64::ORQV_VPZ_H: |
| 15859 | case AArch64::ORQV_VPZ_S: |
| 15860 | case AArch64::SMAXQV_VPZ_B: |
| 15861 | case AArch64::SMAXQV_VPZ_D: |
| 15862 | case AArch64::SMAXQV_VPZ_H: |
| 15863 | case AArch64::SMAXQV_VPZ_S: |
| 15864 | case AArch64::SMINQV_VPZ_B: |
| 15865 | case AArch64::SMINQV_VPZ_D: |
| 15866 | case AArch64::SMINQV_VPZ_H: |
| 15867 | case AArch64::SMINQV_VPZ_S: |
| 15868 | case AArch64::UMAXQV_VPZ_B: |
| 15869 | case AArch64::UMAXQV_VPZ_D: |
| 15870 | case AArch64::UMAXQV_VPZ_H: |
| 15871 | case AArch64::UMAXQV_VPZ_S: |
| 15872 | case AArch64::UMINQV_VPZ_B: |
| 15873 | case AArch64::UMINQV_VPZ_D: |
| 15874 | case AArch64::UMINQV_VPZ_H: |
| 15875 | case AArch64::UMINQV_VPZ_S: { |
| 15876 | // op: Vd |
| 15877 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15878 | Value |= (op & 0x1f); |
| 15879 | // op: Zn |
| 15880 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15881 | Value |= (op & 0x1f) << 5; |
| 15882 | // op: Pg |
| 15883 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15884 | Value |= (op & 0x7) << 10; |
| 15885 | break; |
| 15886 | } |
| 15887 | case AArch64::SHA512SU0: |
| 15888 | case AArch64::SM4E: { |
| 15889 | // op: Vd |
| 15890 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15891 | Value |= (op & 0x1f); |
| 15892 | // op: Vn |
| 15893 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15894 | Value |= (op & 0x1f) << 5; |
| 15895 | break; |
| 15896 | } |
| 15897 | case AArch64::SHA512H: |
| 15898 | case AArch64::SHA512H2: |
| 15899 | case AArch64::SHA512SU1: |
| 15900 | case AArch64::SM3PARTW1: |
| 15901 | case AArch64::SM3PARTW2: |
| 15902 | case AArch64::TBXv16i8Four: |
| 15903 | case AArch64::TBXv16i8One: |
| 15904 | case AArch64::TBXv16i8Three: |
| 15905 | case AArch64::TBXv16i8Two: |
| 15906 | case AArch64::TBXv8i8Four: |
| 15907 | case AArch64::TBXv8i8One: |
| 15908 | case AArch64::TBXv8i8Three: |
| 15909 | case AArch64::TBXv8i8Two: { |
| 15910 | // op: Vd |
| 15911 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15912 | Value |= (op & 0x1f); |
| 15913 | // op: Vn |
| 15914 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15915 | Value |= (op & 0x1f) << 5; |
| 15916 | // op: Vm |
| 15917 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15918 | Value |= (op & 0x1f) << 16; |
| 15919 | break; |
| 15920 | } |
| 15921 | case AArch64::SM3TT1A: |
| 15922 | case AArch64::SM3TT1B: |
| 15923 | case AArch64::SM3TT2A: |
| 15924 | case AArch64::SM3TT2B: { |
| 15925 | // op: Vd |
| 15926 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 15927 | Value |= (op & 0x1f); |
| 15928 | // op: Vn |
| 15929 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15930 | Value |= (op & 0x1f) << 5; |
| 15931 | // op: imm |
| 15932 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 15933 | Value |= (op & 0x3) << 12; |
| 15934 | // op: Vm |
| 15935 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 15936 | Value |= (op & 0x1f) << 16; |
| 15937 | break; |
| 15938 | } |
| 15939 | case AArch64::INSR_ZV_B: |
| 15940 | case AArch64::INSR_ZV_D: |
| 15941 | case AArch64::INSR_ZV_H: |
| 15942 | case AArch64::INSR_ZV_S: { |
| 15943 | // op: Vm |
| 15944 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 15945 | Value |= (op & 0x1f) << 5; |
| 15946 | // op: Zdn |
| 15947 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 15948 | Value |= (op & 0x1f); |
| 15949 | break; |
| 15950 | } |
| 15951 | case AArch64::LD1Fourv16b: |
| 15952 | case AArch64::LD1Fourv1d: |
| 15953 | case AArch64::LD1Fourv2d: |
| 15954 | case AArch64::LD1Fourv2s: |
| 15955 | case AArch64::LD1Fourv4h: |
| 15956 | case AArch64::LD1Fourv4s: |
| 15957 | case AArch64::LD1Fourv8b: |
| 15958 | case AArch64::LD1Fourv8h: |
| 15959 | case AArch64::LD1Onev16b: |
| 15960 | case AArch64::LD1Onev1d: |
| 15961 | case AArch64::LD1Onev2d: |
| 15962 | case AArch64::LD1Onev2s: |
| 15963 | case AArch64::LD1Onev4h: |
| 15964 | case AArch64::LD1Onev4s: |
| 15965 | case AArch64::LD1Onev8b: |
| 15966 | case AArch64::LD1Onev8h: |
| 15967 | case AArch64::LD1Rv16b: |
| 15968 | case AArch64::LD1Rv1d: |
| 15969 | case AArch64::LD1Rv2d: |
| 15970 | case AArch64::LD1Rv2s: |
| 15971 | case AArch64::LD1Rv4h: |
| 15972 | case AArch64::LD1Rv4s: |
| 15973 | case AArch64::LD1Rv8b: |
| 15974 | case AArch64::LD1Rv8h: |
| 15975 | case AArch64::LD1Threev16b: |
| 15976 | case AArch64::LD1Threev1d: |
| 15977 | case AArch64::LD1Threev2d: |
| 15978 | case AArch64::LD1Threev2s: |
| 15979 | case AArch64::LD1Threev4h: |
| 15980 | case AArch64::LD1Threev4s: |
| 15981 | case AArch64::LD1Threev8b: |
| 15982 | case AArch64::LD1Threev8h: |
| 15983 | case AArch64::LD1Twov16b: |
| 15984 | case AArch64::LD1Twov1d: |
| 15985 | case AArch64::LD1Twov2d: |
| 15986 | case AArch64::LD1Twov2s: |
| 15987 | case AArch64::LD1Twov4h: |
| 15988 | case AArch64::LD1Twov4s: |
| 15989 | case AArch64::LD1Twov8b: |
| 15990 | case AArch64::LD1Twov8h: |
| 15991 | case AArch64::LD2Rv16b: |
| 15992 | case AArch64::LD2Rv1d: |
| 15993 | case AArch64::LD2Rv2d: |
| 15994 | case AArch64::LD2Rv2s: |
| 15995 | case AArch64::LD2Rv4h: |
| 15996 | case AArch64::LD2Rv4s: |
| 15997 | case AArch64::LD2Rv8b: |
| 15998 | case AArch64::LD2Rv8h: |
| 15999 | case AArch64::LD2Twov16b: |
| 16000 | case AArch64::LD2Twov2d: |
| 16001 | case AArch64::LD2Twov2s: |
| 16002 | case AArch64::LD2Twov4h: |
| 16003 | case AArch64::LD2Twov4s: |
| 16004 | case AArch64::LD2Twov8b: |
| 16005 | case AArch64::LD2Twov8h: |
| 16006 | case AArch64::LD3Rv16b: |
| 16007 | case AArch64::LD3Rv1d: |
| 16008 | case AArch64::LD3Rv2d: |
| 16009 | case AArch64::LD3Rv2s: |
| 16010 | case AArch64::LD3Rv4h: |
| 16011 | case AArch64::LD3Rv4s: |
| 16012 | case AArch64::LD3Rv8b: |
| 16013 | case AArch64::LD3Rv8h: |
| 16014 | case AArch64::LD3Threev16b: |
| 16015 | case AArch64::LD3Threev2d: |
| 16016 | case AArch64::LD3Threev2s: |
| 16017 | case AArch64::LD3Threev4h: |
| 16018 | case AArch64::LD3Threev4s: |
| 16019 | case AArch64::LD3Threev8b: |
| 16020 | case AArch64::LD3Threev8h: |
| 16021 | case AArch64::LD4Fourv16b: |
| 16022 | case AArch64::LD4Fourv2d: |
| 16023 | case AArch64::LD4Fourv2s: |
| 16024 | case AArch64::LD4Fourv4h: |
| 16025 | case AArch64::LD4Fourv4s: |
| 16026 | case AArch64::LD4Fourv8b: |
| 16027 | case AArch64::LD4Fourv8h: |
| 16028 | case AArch64::LD4Rv16b: |
| 16029 | case AArch64::LD4Rv1d: |
| 16030 | case AArch64::LD4Rv2d: |
| 16031 | case AArch64::LD4Rv2s: |
| 16032 | case AArch64::LD4Rv4h: |
| 16033 | case AArch64::LD4Rv4s: |
| 16034 | case AArch64::LD4Rv8b: |
| 16035 | case AArch64::LD4Rv8h: |
| 16036 | case AArch64::ST1Fourv16b: |
| 16037 | case AArch64::ST1Fourv1d: |
| 16038 | case AArch64::ST1Fourv2d: |
| 16039 | case AArch64::ST1Fourv2s: |
| 16040 | case AArch64::ST1Fourv4h: |
| 16041 | case AArch64::ST1Fourv4s: |
| 16042 | case AArch64::ST1Fourv8b: |
| 16043 | case AArch64::ST1Fourv8h: |
| 16044 | case AArch64::ST1Onev16b: |
| 16045 | case AArch64::ST1Onev1d: |
| 16046 | case AArch64::ST1Onev2d: |
| 16047 | case AArch64::ST1Onev2s: |
| 16048 | case AArch64::ST1Onev4h: |
| 16049 | case AArch64::ST1Onev4s: |
| 16050 | case AArch64::ST1Onev8b: |
| 16051 | case AArch64::ST1Onev8h: |
| 16052 | case AArch64::ST1Threev16b: |
| 16053 | case AArch64::ST1Threev1d: |
| 16054 | case AArch64::ST1Threev2d: |
| 16055 | case AArch64::ST1Threev2s: |
| 16056 | case AArch64::ST1Threev4h: |
| 16057 | case AArch64::ST1Threev4s: |
| 16058 | case AArch64::ST1Threev8b: |
| 16059 | case AArch64::ST1Threev8h: |
| 16060 | case AArch64::ST1Twov16b: |
| 16061 | case AArch64::ST1Twov1d: |
| 16062 | case AArch64::ST1Twov2d: |
| 16063 | case AArch64::ST1Twov2s: |
| 16064 | case AArch64::ST1Twov4h: |
| 16065 | case AArch64::ST1Twov4s: |
| 16066 | case AArch64::ST1Twov8b: |
| 16067 | case AArch64::ST1Twov8h: |
| 16068 | case AArch64::ST2Twov16b: |
| 16069 | case AArch64::ST2Twov2d: |
| 16070 | case AArch64::ST2Twov2s: |
| 16071 | case AArch64::ST2Twov4h: |
| 16072 | case AArch64::ST2Twov4s: |
| 16073 | case AArch64::ST2Twov8b: |
| 16074 | case AArch64::ST2Twov8h: |
| 16075 | case AArch64::ST3Threev16b: |
| 16076 | case AArch64::ST3Threev2d: |
| 16077 | case AArch64::ST3Threev2s: |
| 16078 | case AArch64::ST3Threev4h: |
| 16079 | case AArch64::ST3Threev4s: |
| 16080 | case AArch64::ST3Threev8b: |
| 16081 | case AArch64::ST3Threev8h: |
| 16082 | case AArch64::ST4Fourv16b: |
| 16083 | case AArch64::ST4Fourv2d: |
| 16084 | case AArch64::ST4Fourv2s: |
| 16085 | case AArch64::ST4Fourv4h: |
| 16086 | case AArch64::ST4Fourv4s: |
| 16087 | case AArch64::ST4Fourv8b: |
| 16088 | case AArch64::ST4Fourv8h: { |
| 16089 | // op: Vt |
| 16090 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16091 | Value |= (op & 0x1f); |
| 16092 | // op: Rn |
| 16093 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16094 | Value |= (op & 0x1f) << 5; |
| 16095 | break; |
| 16096 | } |
| 16097 | case AArch64::STL1: { |
| 16098 | // op: Vt |
| 16099 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16100 | Value |= (op & 0x1f); |
| 16101 | // op: Rn |
| 16102 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16103 | Value |= (op & 0x1f) << 5; |
| 16104 | // op: Q |
| 16105 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16106 | Value |= (op & 0x1) << 30; |
| 16107 | break; |
| 16108 | } |
| 16109 | case AArch64::ST1i64: |
| 16110 | case AArch64::ST2i64: |
| 16111 | case AArch64::ST3i64: |
| 16112 | case AArch64::ST4i64: { |
| 16113 | // op: Vt |
| 16114 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16115 | Value |= (op & 0x1f); |
| 16116 | // op: Rn |
| 16117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16118 | Value |= (op & 0x1f) << 5; |
| 16119 | // op: idx |
| 16120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16121 | Value |= (op & 0x1) << 30; |
| 16122 | break; |
| 16123 | } |
| 16124 | case AArch64::ST1i32: |
| 16125 | case AArch64::ST2i32: |
| 16126 | case AArch64::ST3i32: |
| 16127 | case AArch64::ST4i32: { |
| 16128 | // op: Vt |
| 16129 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16130 | Value |= (op & 0x1f); |
| 16131 | // op: Rn |
| 16132 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16133 | Value |= (op & 0x1f) << 5; |
| 16134 | // op: idx |
| 16135 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16136 | Value |= (op & 0x2) << 29; |
| 16137 | Value |= (op & 0x1) << 12; |
| 16138 | break; |
| 16139 | } |
| 16140 | case AArch64::ST1i16: |
| 16141 | case AArch64::ST2i16: |
| 16142 | case AArch64::ST3i16: |
| 16143 | case AArch64::ST4i16: { |
| 16144 | // op: Vt |
| 16145 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16146 | Value |= (op & 0x1f); |
| 16147 | // op: Rn |
| 16148 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16149 | Value |= (op & 0x1f) << 5; |
| 16150 | // op: idx |
| 16151 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16152 | Value |= (op & 0x4) << 28; |
| 16153 | Value |= (op & 0x3) << 11; |
| 16154 | break; |
| 16155 | } |
| 16156 | case AArch64::ST1i8: |
| 16157 | case AArch64::ST2i8: |
| 16158 | case AArch64::ST3i8: |
| 16159 | case AArch64::ST4i8: { |
| 16160 | // op: Vt |
| 16161 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16162 | Value |= (op & 0x1f); |
| 16163 | // op: Rn |
| 16164 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16165 | Value |= (op & 0x1f) << 5; |
| 16166 | // op: idx |
| 16167 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16168 | Value |= (op & 0x8) << 27; |
| 16169 | Value |= (op & 0x7) << 10; |
| 16170 | break; |
| 16171 | } |
| 16172 | case AArch64::LD1Fourv16b_POST: |
| 16173 | case AArch64::LD1Fourv1d_POST: |
| 16174 | case AArch64::LD1Fourv2d_POST: |
| 16175 | case AArch64::LD1Fourv2s_POST: |
| 16176 | case AArch64::LD1Fourv4h_POST: |
| 16177 | case AArch64::LD1Fourv4s_POST: |
| 16178 | case AArch64::LD1Fourv8b_POST: |
| 16179 | case AArch64::LD1Fourv8h_POST: |
| 16180 | case AArch64::LD1Onev16b_POST: |
| 16181 | case AArch64::LD1Onev1d_POST: |
| 16182 | case AArch64::LD1Onev2d_POST: |
| 16183 | case AArch64::LD1Onev2s_POST: |
| 16184 | case AArch64::LD1Onev4h_POST: |
| 16185 | case AArch64::LD1Onev4s_POST: |
| 16186 | case AArch64::LD1Onev8b_POST: |
| 16187 | case AArch64::LD1Onev8h_POST: |
| 16188 | case AArch64::LD1Rv16b_POST: |
| 16189 | case AArch64::LD1Rv1d_POST: |
| 16190 | case AArch64::LD1Rv2d_POST: |
| 16191 | case AArch64::LD1Rv2s_POST: |
| 16192 | case AArch64::LD1Rv4h_POST: |
| 16193 | case AArch64::LD1Rv4s_POST: |
| 16194 | case AArch64::LD1Rv8b_POST: |
| 16195 | case AArch64::LD1Rv8h_POST: |
| 16196 | case AArch64::LD1Threev16b_POST: |
| 16197 | case AArch64::LD1Threev1d_POST: |
| 16198 | case AArch64::LD1Threev2d_POST: |
| 16199 | case AArch64::LD1Threev2s_POST: |
| 16200 | case AArch64::LD1Threev4h_POST: |
| 16201 | case AArch64::LD1Threev4s_POST: |
| 16202 | case AArch64::LD1Threev8b_POST: |
| 16203 | case AArch64::LD1Threev8h_POST: |
| 16204 | case AArch64::LD1Twov16b_POST: |
| 16205 | case AArch64::LD1Twov1d_POST: |
| 16206 | case AArch64::LD1Twov2d_POST: |
| 16207 | case AArch64::LD1Twov2s_POST: |
| 16208 | case AArch64::LD1Twov4h_POST: |
| 16209 | case AArch64::LD1Twov4s_POST: |
| 16210 | case AArch64::LD1Twov8b_POST: |
| 16211 | case AArch64::LD1Twov8h_POST: |
| 16212 | case AArch64::LD2Rv16b_POST: |
| 16213 | case AArch64::LD2Rv1d_POST: |
| 16214 | case AArch64::LD2Rv2d_POST: |
| 16215 | case AArch64::LD2Rv2s_POST: |
| 16216 | case AArch64::LD2Rv4h_POST: |
| 16217 | case AArch64::LD2Rv4s_POST: |
| 16218 | case AArch64::LD2Rv8b_POST: |
| 16219 | case AArch64::LD2Rv8h_POST: |
| 16220 | case AArch64::LD2Twov16b_POST: |
| 16221 | case AArch64::LD2Twov2d_POST: |
| 16222 | case AArch64::LD2Twov2s_POST: |
| 16223 | case AArch64::LD2Twov4h_POST: |
| 16224 | case AArch64::LD2Twov4s_POST: |
| 16225 | case AArch64::LD2Twov8b_POST: |
| 16226 | case AArch64::LD2Twov8h_POST: |
| 16227 | case AArch64::LD3Rv16b_POST: |
| 16228 | case AArch64::LD3Rv1d_POST: |
| 16229 | case AArch64::LD3Rv2d_POST: |
| 16230 | case AArch64::LD3Rv2s_POST: |
| 16231 | case AArch64::LD3Rv4h_POST: |
| 16232 | case AArch64::LD3Rv4s_POST: |
| 16233 | case AArch64::LD3Rv8b_POST: |
| 16234 | case AArch64::LD3Rv8h_POST: |
| 16235 | case AArch64::LD3Threev16b_POST: |
| 16236 | case AArch64::LD3Threev2d_POST: |
| 16237 | case AArch64::LD3Threev2s_POST: |
| 16238 | case AArch64::LD3Threev4h_POST: |
| 16239 | case AArch64::LD3Threev4s_POST: |
| 16240 | case AArch64::LD3Threev8b_POST: |
| 16241 | case AArch64::LD3Threev8h_POST: |
| 16242 | case AArch64::LD4Fourv16b_POST: |
| 16243 | case AArch64::LD4Fourv2d_POST: |
| 16244 | case AArch64::LD4Fourv2s_POST: |
| 16245 | case AArch64::LD4Fourv4h_POST: |
| 16246 | case AArch64::LD4Fourv4s_POST: |
| 16247 | case AArch64::LD4Fourv8b_POST: |
| 16248 | case AArch64::LD4Fourv8h_POST: |
| 16249 | case AArch64::LD4Rv16b_POST: |
| 16250 | case AArch64::LD4Rv1d_POST: |
| 16251 | case AArch64::LD4Rv2d_POST: |
| 16252 | case AArch64::LD4Rv2s_POST: |
| 16253 | case AArch64::LD4Rv4h_POST: |
| 16254 | case AArch64::LD4Rv4s_POST: |
| 16255 | case AArch64::LD4Rv8b_POST: |
| 16256 | case AArch64::LD4Rv8h_POST: |
| 16257 | case AArch64::ST1Fourv16b_POST: |
| 16258 | case AArch64::ST1Fourv1d_POST: |
| 16259 | case AArch64::ST1Fourv2d_POST: |
| 16260 | case AArch64::ST1Fourv2s_POST: |
| 16261 | case AArch64::ST1Fourv4h_POST: |
| 16262 | case AArch64::ST1Fourv4s_POST: |
| 16263 | case AArch64::ST1Fourv8b_POST: |
| 16264 | case AArch64::ST1Fourv8h_POST: |
| 16265 | case AArch64::ST1Onev16b_POST: |
| 16266 | case AArch64::ST1Onev1d_POST: |
| 16267 | case AArch64::ST1Onev2d_POST: |
| 16268 | case AArch64::ST1Onev2s_POST: |
| 16269 | case AArch64::ST1Onev4h_POST: |
| 16270 | case AArch64::ST1Onev4s_POST: |
| 16271 | case AArch64::ST1Onev8b_POST: |
| 16272 | case AArch64::ST1Onev8h_POST: |
| 16273 | case AArch64::ST1Threev16b_POST: |
| 16274 | case AArch64::ST1Threev1d_POST: |
| 16275 | case AArch64::ST1Threev2d_POST: |
| 16276 | case AArch64::ST1Threev2s_POST: |
| 16277 | case AArch64::ST1Threev4h_POST: |
| 16278 | case AArch64::ST1Threev4s_POST: |
| 16279 | case AArch64::ST1Threev8b_POST: |
| 16280 | case AArch64::ST1Threev8h_POST: |
| 16281 | case AArch64::ST1Twov16b_POST: |
| 16282 | case AArch64::ST1Twov1d_POST: |
| 16283 | case AArch64::ST1Twov2d_POST: |
| 16284 | case AArch64::ST1Twov2s_POST: |
| 16285 | case AArch64::ST1Twov4h_POST: |
| 16286 | case AArch64::ST1Twov4s_POST: |
| 16287 | case AArch64::ST1Twov8b_POST: |
| 16288 | case AArch64::ST1Twov8h_POST: |
| 16289 | case AArch64::ST2Twov16b_POST: |
| 16290 | case AArch64::ST2Twov2d_POST: |
| 16291 | case AArch64::ST2Twov2s_POST: |
| 16292 | case AArch64::ST2Twov4h_POST: |
| 16293 | case AArch64::ST2Twov4s_POST: |
| 16294 | case AArch64::ST2Twov8b_POST: |
| 16295 | case AArch64::ST2Twov8h_POST: |
| 16296 | case AArch64::ST3Threev16b_POST: |
| 16297 | case AArch64::ST3Threev2d_POST: |
| 16298 | case AArch64::ST3Threev2s_POST: |
| 16299 | case AArch64::ST3Threev4h_POST: |
| 16300 | case AArch64::ST3Threev4s_POST: |
| 16301 | case AArch64::ST3Threev8b_POST: |
| 16302 | case AArch64::ST3Threev8h_POST: |
| 16303 | case AArch64::ST4Fourv16b_POST: |
| 16304 | case AArch64::ST4Fourv2d_POST: |
| 16305 | case AArch64::ST4Fourv2s_POST: |
| 16306 | case AArch64::ST4Fourv4h_POST: |
| 16307 | case AArch64::ST4Fourv4s_POST: |
| 16308 | case AArch64::ST4Fourv8b_POST: |
| 16309 | case AArch64::ST4Fourv8h_POST: { |
| 16310 | // op: Vt |
| 16311 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16312 | Value |= (op & 0x1f); |
| 16313 | // op: Rn |
| 16314 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16315 | Value |= (op & 0x1f) << 5; |
| 16316 | // op: Xm |
| 16317 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16318 | Value |= (op & 0x1f) << 16; |
| 16319 | break; |
| 16320 | } |
| 16321 | case AArch64::LDAP1: { |
| 16322 | // op: Vt |
| 16323 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16324 | Value |= (op & 0x1f); |
| 16325 | // op: Rn |
| 16326 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16327 | Value |= (op & 0x1f) << 5; |
| 16328 | // op: Q |
| 16329 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16330 | Value |= (op & 0x1) << 30; |
| 16331 | break; |
| 16332 | } |
| 16333 | case AArch64::LD1i64: |
| 16334 | case AArch64::LD2i64: |
| 16335 | case AArch64::LD3i64: |
| 16336 | case AArch64::LD4i64: { |
| 16337 | // op: Vt |
| 16338 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16339 | Value |= (op & 0x1f); |
| 16340 | // op: Rn |
| 16341 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16342 | Value |= (op & 0x1f) << 5; |
| 16343 | // op: idx |
| 16344 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16345 | Value |= (op & 0x1) << 30; |
| 16346 | break; |
| 16347 | } |
| 16348 | case AArch64::ST1i64_POST: |
| 16349 | case AArch64::ST2i64_POST: |
| 16350 | case AArch64::ST3i64_POST: |
| 16351 | case AArch64::ST4i64_POST: { |
| 16352 | // op: Vt |
| 16353 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16354 | Value |= (op & 0x1f); |
| 16355 | // op: Rn |
| 16356 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16357 | Value |= (op & 0x1f) << 5; |
| 16358 | // op: idx |
| 16359 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16360 | Value |= (op & 0x1) << 30; |
| 16361 | // op: Xm |
| 16362 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 16363 | Value |= (op & 0x1f) << 16; |
| 16364 | break; |
| 16365 | } |
| 16366 | case AArch64::LD1i32: |
| 16367 | case AArch64::LD2i32: |
| 16368 | case AArch64::LD3i32: |
| 16369 | case AArch64::LD4i32: { |
| 16370 | // op: Vt |
| 16371 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16372 | Value |= (op & 0x1f); |
| 16373 | // op: Rn |
| 16374 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16375 | Value |= (op & 0x1f) << 5; |
| 16376 | // op: idx |
| 16377 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16378 | Value |= (op & 0x2) << 29; |
| 16379 | Value |= (op & 0x1) << 12; |
| 16380 | break; |
| 16381 | } |
| 16382 | case AArch64::ST1i32_POST: |
| 16383 | case AArch64::ST2i32_POST: |
| 16384 | case AArch64::ST3i32_POST: |
| 16385 | case AArch64::ST4i32_POST: { |
| 16386 | // op: Vt |
| 16387 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16388 | Value |= (op & 0x1f); |
| 16389 | // op: Rn |
| 16390 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16391 | Value |= (op & 0x1f) << 5; |
| 16392 | // op: idx |
| 16393 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16394 | Value |= (op & 0x2) << 29; |
| 16395 | Value |= (op & 0x1) << 12; |
| 16396 | // op: Xm |
| 16397 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 16398 | Value |= (op & 0x1f) << 16; |
| 16399 | break; |
| 16400 | } |
| 16401 | case AArch64::LD1i16: |
| 16402 | case AArch64::LD2i16: |
| 16403 | case AArch64::LD3i16: |
| 16404 | case AArch64::LD4i16: { |
| 16405 | // op: Vt |
| 16406 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16407 | Value |= (op & 0x1f); |
| 16408 | // op: Rn |
| 16409 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16410 | Value |= (op & 0x1f) << 5; |
| 16411 | // op: idx |
| 16412 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16413 | Value |= (op & 0x4) << 28; |
| 16414 | Value |= (op & 0x3) << 11; |
| 16415 | break; |
| 16416 | } |
| 16417 | case AArch64::ST1i16_POST: |
| 16418 | case AArch64::ST2i16_POST: |
| 16419 | case AArch64::ST3i16_POST: |
| 16420 | case AArch64::ST4i16_POST: { |
| 16421 | // op: Vt |
| 16422 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16423 | Value |= (op & 0x1f); |
| 16424 | // op: Rn |
| 16425 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16426 | Value |= (op & 0x1f) << 5; |
| 16427 | // op: idx |
| 16428 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16429 | Value |= (op & 0x4) << 28; |
| 16430 | Value |= (op & 0x3) << 11; |
| 16431 | // op: Xm |
| 16432 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 16433 | Value |= (op & 0x1f) << 16; |
| 16434 | break; |
| 16435 | } |
| 16436 | case AArch64::LD1i8: |
| 16437 | case AArch64::LD2i8: |
| 16438 | case AArch64::LD3i8: |
| 16439 | case AArch64::LD4i8: { |
| 16440 | // op: Vt |
| 16441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16442 | Value |= (op & 0x1f); |
| 16443 | // op: Rn |
| 16444 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16445 | Value |= (op & 0x1f) << 5; |
| 16446 | // op: idx |
| 16447 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16448 | Value |= (op & 0x8) << 27; |
| 16449 | Value |= (op & 0x7) << 10; |
| 16450 | break; |
| 16451 | } |
| 16452 | case AArch64::ST1i8_POST: |
| 16453 | case AArch64::ST2i8_POST: |
| 16454 | case AArch64::ST3i8_POST: |
| 16455 | case AArch64::ST4i8_POST: { |
| 16456 | // op: Vt |
| 16457 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16458 | Value |= (op & 0x1f); |
| 16459 | // op: Rn |
| 16460 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16461 | Value |= (op & 0x1f) << 5; |
| 16462 | // op: idx |
| 16463 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16464 | Value |= (op & 0x8) << 27; |
| 16465 | Value |= (op & 0x7) << 10; |
| 16466 | // op: Xm |
| 16467 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 16468 | Value |= (op & 0x1f) << 16; |
| 16469 | break; |
| 16470 | } |
| 16471 | case AArch64::LD1i64_POST: |
| 16472 | case AArch64::LD2i64_POST: |
| 16473 | case AArch64::LD3i64_POST: |
| 16474 | case AArch64::LD4i64_POST: { |
| 16475 | // op: Vt |
| 16476 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16477 | Value |= (op & 0x1f); |
| 16478 | // op: Rn |
| 16479 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 16480 | Value |= (op & 0x1f) << 5; |
| 16481 | // op: idx |
| 16482 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16483 | Value |= (op & 0x1) << 30; |
| 16484 | // op: Xm |
| 16485 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 16486 | Value |= (op & 0x1f) << 16; |
| 16487 | break; |
| 16488 | } |
| 16489 | case AArch64::LD1i32_POST: |
| 16490 | case AArch64::LD2i32_POST: |
| 16491 | case AArch64::LD3i32_POST: |
| 16492 | case AArch64::LD4i32_POST: { |
| 16493 | // op: Vt |
| 16494 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16495 | Value |= (op & 0x1f); |
| 16496 | // op: Rn |
| 16497 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 16498 | Value |= (op & 0x1f) << 5; |
| 16499 | // op: idx |
| 16500 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16501 | Value |= (op & 0x2) << 29; |
| 16502 | Value |= (op & 0x1) << 12; |
| 16503 | // op: Xm |
| 16504 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 16505 | Value |= (op & 0x1f) << 16; |
| 16506 | break; |
| 16507 | } |
| 16508 | case AArch64::LD1i16_POST: |
| 16509 | case AArch64::LD2i16_POST: |
| 16510 | case AArch64::LD3i16_POST: |
| 16511 | case AArch64::LD4i16_POST: { |
| 16512 | // op: Vt |
| 16513 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16514 | Value |= (op & 0x1f); |
| 16515 | // op: Rn |
| 16516 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 16517 | Value |= (op & 0x1f) << 5; |
| 16518 | // op: idx |
| 16519 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16520 | Value |= (op & 0x4) << 28; |
| 16521 | Value |= (op & 0x3) << 11; |
| 16522 | // op: Xm |
| 16523 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 16524 | Value |= (op & 0x1f) << 16; |
| 16525 | break; |
| 16526 | } |
| 16527 | case AArch64::LD1i8_POST: |
| 16528 | case AArch64::LD2i8_POST: |
| 16529 | case AArch64::LD3i8_POST: |
| 16530 | case AArch64::LD4i8_POST: { |
| 16531 | // op: Vt |
| 16532 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16533 | Value |= (op & 0x1f); |
| 16534 | // op: Rn |
| 16535 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 16536 | Value |= (op & 0x1f) << 5; |
| 16537 | // op: idx |
| 16538 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16539 | Value |= (op & 0x8) << 27; |
| 16540 | Value |= (op & 0x7) << 10; |
| 16541 | // op: Xm |
| 16542 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 16543 | Value |= (op & 0x1f) << 16; |
| 16544 | break; |
| 16545 | } |
| 16546 | case AArch64::STLTXRW: |
| 16547 | case AArch64::STLTXRX: |
| 16548 | case AArch64::STLXRB: |
| 16549 | case AArch64::STLXRH: |
| 16550 | case AArch64::STLXRW: |
| 16551 | case AArch64::STLXRX: |
| 16552 | case AArch64::STXRB: |
| 16553 | case AArch64::STXRH: |
| 16554 | case AArch64::STXRW: |
| 16555 | case AArch64::STXRX: { |
| 16556 | // op: Ws |
| 16557 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16558 | Value |= (op & 0x1f) << 16; |
| 16559 | // op: Rt |
| 16560 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16561 | Value |= (op & 0x1f); |
| 16562 | // op: Rn |
| 16563 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16564 | Value |= (op & 0x1f) << 5; |
| 16565 | Value = fixLoadStoreExclusive<1,0>(MI, EncodedValue: Value, STI); |
| 16566 | break; |
| 16567 | } |
| 16568 | case AArch64::STLXPW: |
| 16569 | case AArch64::STLXPX: |
| 16570 | case AArch64::STXPW: |
| 16571 | case AArch64::STXPX: { |
| 16572 | // op: Ws |
| 16573 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16574 | Value |= (op & 0x1f) << 16; |
| 16575 | // op: Rt |
| 16576 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16577 | Value |= (op & 0x1f); |
| 16578 | // op: Rt2 |
| 16579 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16580 | Value |= (op & 0x1f) << 10; |
| 16581 | // op: Rn |
| 16582 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16583 | Value |= (op & 0x1f) << 5; |
| 16584 | break; |
| 16585 | } |
| 16586 | case AArch64::TCHANGEBrr: |
| 16587 | case AArch64::TCHANGEFrr: { |
| 16588 | // op: Xd |
| 16589 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16590 | Value |= (op & 0x1f); |
| 16591 | // op: Xn |
| 16592 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16593 | Value |= (op & 0x1f) << 5; |
| 16594 | // op: nb |
| 16595 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16596 | Value |= (op & 0x1) << 17; |
| 16597 | break; |
| 16598 | } |
| 16599 | case AArch64::TCHANGEBri: |
| 16600 | case AArch64::TCHANGEFri: { |
| 16601 | // op: Xd |
| 16602 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16603 | Value |= (op & 0x1f); |
| 16604 | // op: imm |
| 16605 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16606 | Value |= (op & 0x7f) << 5; |
| 16607 | // op: nb |
| 16608 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 16609 | Value |= (op & 0x1) << 17; |
| 16610 | break; |
| 16611 | } |
| 16612 | case AArch64::ADR: |
| 16613 | case AArch64::ADRP: { |
| 16614 | // op: Xd |
| 16615 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16616 | Value |= (op & 0x1f); |
| 16617 | // op: label |
| 16618 | op = getAdrLabelOpValue(MI, OpIdx: 1, Fixups, STI); |
| 16619 | Value |= (op & 0x3) << 29; |
| 16620 | Value |= (op & 0x1ffffc) << 3; |
| 16621 | break; |
| 16622 | } |
| 16623 | case AArch64::BFMOP4A_M2Z2Z_H: |
| 16624 | case AArch64::BFMOP4S_M2Z2Z_H: |
| 16625 | case AArch64::FMOP4A_M2Z2Z_BtoH: |
| 16626 | case AArch64::FMOP4A_M2Z2Z_H: |
| 16627 | case AArch64::FMOP4S_M2Z2Z_H: { |
| 16628 | // op: ZAda |
| 16629 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16630 | Value |= (op & 0x1); |
| 16631 | // op: Zn |
| 16632 | op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 2, Fixups, STI); |
| 16633 | Value |= (op & 0x7) << 6; |
| 16634 | // op: Zm |
| 16635 | op = EncodeRegMul_MinMax<2, 16, 30>(MI, OpIdx: 3, Fixups, STI); |
| 16636 | Value |= (op & 0x7) << 17; |
| 16637 | break; |
| 16638 | } |
| 16639 | case AArch64::BFMOP4A_M2ZZ_H: |
| 16640 | case AArch64::BFMOP4S_M2ZZ_H: |
| 16641 | case AArch64::FMOP4A_M2ZZ_BtoH: |
| 16642 | case AArch64::FMOP4A_M2ZZ_H: |
| 16643 | case AArch64::FMOP4S_M2ZZ_H: { |
| 16644 | // op: ZAda |
| 16645 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16646 | Value |= (op & 0x1); |
| 16647 | // op: Zn |
| 16648 | op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 2, Fixups, STI); |
| 16649 | Value |= (op & 0x7) << 6; |
| 16650 | // op: Zm |
| 16651 | op = EncodeRegMul_MinMax<2,16, 30>(MI, OpIdx: 3, Fixups, STI); |
| 16652 | Value |= (op & 0x7) << 17; |
| 16653 | break; |
| 16654 | } |
| 16655 | case AArch64::BFTMOPA_M2ZZZI_HtoH: |
| 16656 | case AArch64::FTMOPA_M2ZZZI_BtoH: |
| 16657 | case AArch64::FTMOPA_M2ZZZI_HtoH: { |
| 16658 | // op: ZAda |
| 16659 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16660 | Value |= (op & 0x1); |
| 16661 | // op: Zn |
| 16662 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI); |
| 16663 | Value |= (op & 0xf) << 6; |
| 16664 | // op: Zm |
| 16665 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16666 | Value |= (op & 0x1f) << 16; |
| 16667 | // op: Zk |
| 16668 | op = EncodeZK(MI, OpIdx: 4, Fixups, STI); |
| 16669 | Value |= (op & 0x7) << 10; |
| 16670 | // op: imm |
| 16671 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 16672 | Value |= (op & 0x3) << 4; |
| 16673 | break; |
| 16674 | } |
| 16675 | case AArch64::BFMOP4A_MZ2Z_H: |
| 16676 | case AArch64::BFMOP4S_MZ2Z_H: |
| 16677 | case AArch64::FMOP4A_MZ2Z_BtoH: |
| 16678 | case AArch64::FMOP4A_MZ2Z_H: |
| 16679 | case AArch64::FMOP4S_MZ2Z_H: { |
| 16680 | // op: ZAda |
| 16681 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16682 | Value |= (op & 0x1); |
| 16683 | // op: Zn |
| 16684 | op = EncodeRegMul_MinMax<2,0, 14>(MI, OpIdx: 2, Fixups, STI); |
| 16685 | Value |= (op & 0x7) << 6; |
| 16686 | // op: Zm |
| 16687 | op = EncodeRegMul_MinMax<2, 16, 30>(MI, OpIdx: 3, Fixups, STI); |
| 16688 | Value |= (op & 0x7) << 17; |
| 16689 | break; |
| 16690 | } |
| 16691 | case AArch64::BFMOP4A_MZZ_H: |
| 16692 | case AArch64::BFMOP4S_MZZ_H: |
| 16693 | case AArch64::FMOP4A_MZZ_BtoH: |
| 16694 | case AArch64::FMOP4A_MZZ_H: |
| 16695 | case AArch64::FMOP4S_MZZ_H: { |
| 16696 | // op: ZAda |
| 16697 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16698 | Value |= (op & 0x1); |
| 16699 | // op: Zn |
| 16700 | op = EncodeRegMul_MinMax<2,0, 14>(MI, OpIdx: 2, Fixups, STI); |
| 16701 | Value |= (op & 0x7) << 6; |
| 16702 | // op: Zm |
| 16703 | op = EncodeRegMul_MinMax<2,16, 30>(MI, OpIdx: 3, Fixups, STI); |
| 16704 | Value |= (op & 0x7) << 17; |
| 16705 | break; |
| 16706 | } |
| 16707 | case AArch64::BFMOP4A_M2Z2Z_S: |
| 16708 | case AArch64::BFMOP4S_M2Z2Z_S: |
| 16709 | case AArch64::FMOP4A_M2Z2Z_BtoS: |
| 16710 | case AArch64::FMOP4A_M2Z2Z_HtoS: |
| 16711 | case AArch64::FMOP4A_M2Z2Z_S: |
| 16712 | case AArch64::FMOP4S_M2Z2Z_HtoS: |
| 16713 | case AArch64::FMOP4S_M2Z2Z_S: |
| 16714 | case AArch64::SMOP4A_M2Z2Z_BToS: |
| 16715 | case AArch64::SMOP4A_M2Z2Z_HToS: |
| 16716 | case AArch64::SMOP4S_M2Z2Z_BToS: |
| 16717 | case AArch64::SMOP4S_M2Z2Z_HToS: |
| 16718 | case AArch64::SUMOP4A_M2Z2Z_BToS: |
| 16719 | case AArch64::SUMOP4S_M2Z2Z_BToS: |
| 16720 | case AArch64::UMOP4A_M2Z2Z_BToS: |
| 16721 | case AArch64::UMOP4A_M2Z2Z_HToS: |
| 16722 | case AArch64::UMOP4S_M2Z2Z_BToS: |
| 16723 | case AArch64::UMOP4S_M2Z2Z_HToS: |
| 16724 | case AArch64::USMOP4A_M2Z2Z_BToS: |
| 16725 | case AArch64::USMOP4S_M2Z2Z_BToS: { |
| 16726 | // op: ZAda |
| 16727 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16728 | Value |= (op & 0x3); |
| 16729 | // op: Zn |
| 16730 | op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 2, Fixups, STI); |
| 16731 | Value |= (op & 0x7) << 6; |
| 16732 | // op: Zm |
| 16733 | op = EncodeRegMul_MinMax<2, 16, 30>(MI, OpIdx: 3, Fixups, STI); |
| 16734 | Value |= (op & 0x7) << 17; |
| 16735 | break; |
| 16736 | } |
| 16737 | case AArch64::BFMOP4A_M2ZZ_S: |
| 16738 | case AArch64::BFMOP4S_M2ZZ_S: |
| 16739 | case AArch64::FMOP4A_M2ZZ_BtoS: |
| 16740 | case AArch64::FMOP4A_M2ZZ_HtoS: |
| 16741 | case AArch64::FMOP4A_M2ZZ_S: |
| 16742 | case AArch64::FMOP4S_M2ZZ_HtoS: |
| 16743 | case AArch64::FMOP4S_M2ZZ_S: |
| 16744 | case AArch64::SMOP4A_M2ZZ_BToS: |
| 16745 | case AArch64::SMOP4A_M2ZZ_HToS: |
| 16746 | case AArch64::SMOP4S_M2ZZ_BToS: |
| 16747 | case AArch64::SMOP4S_M2ZZ_HToS: |
| 16748 | case AArch64::SUMOP4A_M2ZZ_BToS: |
| 16749 | case AArch64::SUMOP4S_M2ZZ_BToS: |
| 16750 | case AArch64::UMOP4A_M2ZZ_BToS: |
| 16751 | case AArch64::UMOP4A_M2ZZ_HToS: |
| 16752 | case AArch64::UMOP4S_M2ZZ_BToS: |
| 16753 | case AArch64::UMOP4S_M2ZZ_HToS: |
| 16754 | case AArch64::USMOP4A_M2ZZ_BToS: |
| 16755 | case AArch64::USMOP4S_M2ZZ_BToS: { |
| 16756 | // op: ZAda |
| 16757 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16758 | Value |= (op & 0x3); |
| 16759 | // op: Zn |
| 16760 | op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 2, Fixups, STI); |
| 16761 | Value |= (op & 0x7) << 6; |
| 16762 | // op: Zm |
| 16763 | op = EncodeRegMul_MinMax<2,16, 30>(MI, OpIdx: 3, Fixups, STI); |
| 16764 | Value |= (op & 0x7) << 17; |
| 16765 | break; |
| 16766 | } |
| 16767 | case AArch64::BFTMOPA_M2ZZZI_HtoS: |
| 16768 | case AArch64::FTMOPA_M2ZZZI_BtoS: |
| 16769 | case AArch64::FTMOPA_M2ZZZI_HtoS: |
| 16770 | case AArch64::FTMOPA_M2ZZZI_StoS: |
| 16771 | case AArch64::STMOPA_M2ZZZI_BtoS: |
| 16772 | case AArch64::STMOPA_M2ZZZI_HtoS: |
| 16773 | case AArch64::SUTMOPA_M2ZZZI_BtoS: |
| 16774 | case AArch64::USTMOPA_M2ZZZI_BtoS: |
| 16775 | case AArch64::UTMOPA_M2ZZZI_BtoS: |
| 16776 | case AArch64::UTMOPA_M2ZZZI_HtoS: { |
| 16777 | // op: ZAda |
| 16778 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16779 | Value |= (op & 0x3); |
| 16780 | // op: Zn |
| 16781 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI); |
| 16782 | Value |= (op & 0xf) << 6; |
| 16783 | // op: Zm |
| 16784 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16785 | Value |= (op & 0x1f) << 16; |
| 16786 | // op: Zk |
| 16787 | op = EncodeZK(MI, OpIdx: 4, Fixups, STI); |
| 16788 | Value |= (op & 0x7) << 10; |
| 16789 | // op: imm |
| 16790 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 16791 | Value |= (op & 0x3) << 4; |
| 16792 | break; |
| 16793 | } |
| 16794 | case AArch64::BFMOP4A_MZ2Z_S: |
| 16795 | case AArch64::BFMOP4S_MZ2Z_S: |
| 16796 | case AArch64::FMOP4A_MZ2Z_BtoS: |
| 16797 | case AArch64::FMOP4A_MZ2Z_HtoS: |
| 16798 | case AArch64::FMOP4A_MZ2Z_S: |
| 16799 | case AArch64::FMOP4S_MZ2Z_HtoS: |
| 16800 | case AArch64::FMOP4S_MZ2Z_S: |
| 16801 | case AArch64::SMOP4A_MZ2Z_BToS: |
| 16802 | case AArch64::SMOP4A_MZ2Z_HToS: |
| 16803 | case AArch64::SMOP4S_MZ2Z_BToS: |
| 16804 | case AArch64::SMOP4S_MZ2Z_HToS: |
| 16805 | case AArch64::SUMOP4A_MZ2Z_BToS: |
| 16806 | case AArch64::SUMOP4S_MZ2Z_BToS: |
| 16807 | case AArch64::UMOP4A_MZ2Z_BToS: |
| 16808 | case AArch64::UMOP4A_MZ2Z_HToS: |
| 16809 | case AArch64::UMOP4S_MZ2Z_BToS: |
| 16810 | case AArch64::UMOP4S_MZ2Z_HToS: |
| 16811 | case AArch64::USMOP4A_MZ2Z_BToS: |
| 16812 | case AArch64::USMOP4S_MZ2Z_BToS: { |
| 16813 | // op: ZAda |
| 16814 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16815 | Value |= (op & 0x3); |
| 16816 | // op: Zn |
| 16817 | op = EncodeRegMul_MinMax<2,0, 14>(MI, OpIdx: 2, Fixups, STI); |
| 16818 | Value |= (op & 0x7) << 6; |
| 16819 | // op: Zm |
| 16820 | op = EncodeRegMul_MinMax<2, 16, 30>(MI, OpIdx: 3, Fixups, STI); |
| 16821 | Value |= (op & 0x7) << 17; |
| 16822 | break; |
| 16823 | } |
| 16824 | case AArch64::BFMOP4A_MZZ_S: |
| 16825 | case AArch64::BFMOP4S_MZZ_S: |
| 16826 | case AArch64::FMOP4A_MZZ_BtoS: |
| 16827 | case AArch64::FMOP4A_MZZ_HtoS: |
| 16828 | case AArch64::FMOP4A_MZZ_S: |
| 16829 | case AArch64::FMOP4S_MZZ_HtoS: |
| 16830 | case AArch64::FMOP4S_MZZ_S: |
| 16831 | case AArch64::SMOP4A_MZZ_BToS: |
| 16832 | case AArch64::SMOP4A_MZZ_HToS: |
| 16833 | case AArch64::SMOP4S_MZZ_BToS: |
| 16834 | case AArch64::SMOP4S_MZZ_HToS: |
| 16835 | case AArch64::SUMOP4A_MZZ_BToS: |
| 16836 | case AArch64::SUMOP4S_MZZ_BToS: |
| 16837 | case AArch64::UMOP4A_MZZ_BToS: |
| 16838 | case AArch64::UMOP4A_MZZ_HToS: |
| 16839 | case AArch64::UMOP4S_MZZ_BToS: |
| 16840 | case AArch64::UMOP4S_MZZ_HToS: |
| 16841 | case AArch64::USMOP4A_MZZ_BToS: |
| 16842 | case AArch64::USMOP4S_MZZ_BToS: { |
| 16843 | // op: ZAda |
| 16844 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16845 | Value |= (op & 0x3); |
| 16846 | // op: Zn |
| 16847 | op = EncodeRegMul_MinMax<2,0, 14>(MI, OpIdx: 2, Fixups, STI); |
| 16848 | Value |= (op & 0x7) << 6; |
| 16849 | // op: Zm |
| 16850 | op = EncodeRegMul_MinMax<2,16, 30>(MI, OpIdx: 3, Fixups, STI); |
| 16851 | Value |= (op & 0x7) << 17; |
| 16852 | break; |
| 16853 | } |
| 16854 | case AArch64::FMOP4A_M2Z2Z_D: |
| 16855 | case AArch64::FMOP4S_M2Z2Z_D: |
| 16856 | case AArch64::SMOP4A_M2Z2Z_HtoD: |
| 16857 | case AArch64::SMOP4S_M2Z2Z_HtoD: |
| 16858 | case AArch64::SUMOP4A_M2Z2Z_HtoD: |
| 16859 | case AArch64::SUMOP4S_M2Z2Z_HtoD: |
| 16860 | case AArch64::UMOP4A_M2Z2Z_HtoD: |
| 16861 | case AArch64::UMOP4S_M2Z2Z_HtoD: |
| 16862 | case AArch64::USMOP4A_M2Z2Z_HtoD: |
| 16863 | case AArch64::USMOP4S_M2Z2Z_HtoD: { |
| 16864 | // op: ZAda |
| 16865 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16866 | Value |= (op & 0x7); |
| 16867 | // op: Zn |
| 16868 | op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 2, Fixups, STI); |
| 16869 | Value |= (op & 0x7) << 6; |
| 16870 | // op: Zm |
| 16871 | op = EncodeRegMul_MinMax<2, 16, 30>(MI, OpIdx: 3, Fixups, STI); |
| 16872 | Value |= (op & 0x7) << 17; |
| 16873 | break; |
| 16874 | } |
| 16875 | case AArch64::FMOP4A_M2ZZ_D: |
| 16876 | case AArch64::FMOP4S_M2ZZ_D: |
| 16877 | case AArch64::SMOP4A_M2ZZ_HtoD: |
| 16878 | case AArch64::SMOP4S_M2ZZ_HtoD: |
| 16879 | case AArch64::SUMOP4A_M2ZZ_HtoD: |
| 16880 | case AArch64::SUMOP4S_M2ZZ_HtoD: |
| 16881 | case AArch64::UMOP4A_M2ZZ_HtoD: |
| 16882 | case AArch64::UMOP4S_M2ZZ_HtoD: |
| 16883 | case AArch64::USMOP4A_M2ZZ_HtoD: |
| 16884 | case AArch64::USMOP4S_M2ZZ_HtoD: { |
| 16885 | // op: ZAda |
| 16886 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16887 | Value |= (op & 0x7); |
| 16888 | // op: Zn |
| 16889 | op = EncodeRegMul_MinMax<2, 0, 14>(MI, OpIdx: 2, Fixups, STI); |
| 16890 | Value |= (op & 0x7) << 6; |
| 16891 | // op: Zm |
| 16892 | op = EncodeRegMul_MinMax<2,16, 30>(MI, OpIdx: 3, Fixups, STI); |
| 16893 | Value |= (op & 0x7) << 17; |
| 16894 | break; |
| 16895 | } |
| 16896 | case AArch64::FMOP4A_MZ2Z_D: |
| 16897 | case AArch64::FMOP4S_MZ2Z_D: |
| 16898 | case AArch64::SMOP4A_MZ2Z_HtoD: |
| 16899 | case AArch64::SMOP4S_MZ2Z_HtoD: |
| 16900 | case AArch64::SUMOP4A_MZ2Z_HtoD: |
| 16901 | case AArch64::SUMOP4S_MZ2Z_HtoD: |
| 16902 | case AArch64::UMOP4A_MZ2Z_HtoD: |
| 16903 | case AArch64::UMOP4S_MZ2Z_HtoD: |
| 16904 | case AArch64::USMOP4A_MZ2Z_HtoD: |
| 16905 | case AArch64::USMOP4S_MZ2Z_HtoD: { |
| 16906 | // op: ZAda |
| 16907 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16908 | Value |= (op & 0x7); |
| 16909 | // op: Zn |
| 16910 | op = EncodeRegMul_MinMax<2,0, 14>(MI, OpIdx: 2, Fixups, STI); |
| 16911 | Value |= (op & 0x7) << 6; |
| 16912 | // op: Zm |
| 16913 | op = EncodeRegMul_MinMax<2, 16, 30>(MI, OpIdx: 3, Fixups, STI); |
| 16914 | Value |= (op & 0x7) << 17; |
| 16915 | break; |
| 16916 | } |
| 16917 | case AArch64::FMOP4A_MZZ_D: |
| 16918 | case AArch64::FMOP4S_MZZ_D: |
| 16919 | case AArch64::SMOP4A_MZZ_HtoD: |
| 16920 | case AArch64::SMOP4S_MZZ_HtoD: |
| 16921 | case AArch64::SUMOP4A_MZZ_HtoD: |
| 16922 | case AArch64::SUMOP4S_MZZ_HtoD: |
| 16923 | case AArch64::UMOP4A_MZZ_HtoD: |
| 16924 | case AArch64::UMOP4S_MZZ_HtoD: |
| 16925 | case AArch64::USMOP4A_MZZ_HtoD: |
| 16926 | case AArch64::USMOP4S_MZZ_HtoD: { |
| 16927 | // op: ZAda |
| 16928 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 16929 | Value |= (op & 0x7); |
| 16930 | // op: Zn |
| 16931 | op = EncodeRegMul_MinMax<2,0, 14>(MI, OpIdx: 2, Fixups, STI); |
| 16932 | Value |= (op & 0x7) << 6; |
| 16933 | // op: Zm |
| 16934 | op = EncodeRegMul_MinMax<2,16, 30>(MI, OpIdx: 3, Fixups, STI); |
| 16935 | Value |= (op & 0x7) << 17; |
| 16936 | break; |
| 16937 | } |
| 16938 | case AArch64::MOVA_2ZMXI_H_H: |
| 16939 | case AArch64::MOVA_2ZMXI_V_H: { |
| 16940 | // op: Zd |
| 16941 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 16942 | Value |= (op & 0xf) << 1; |
| 16943 | // op: Rs |
| 16944 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 16945 | Value |= (op & 0x3) << 13; |
| 16946 | // op: ZAn |
| 16947 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16948 | Value |= (op & 0x1) << 7; |
| 16949 | // op: imm |
| 16950 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16951 | Value |= (op & 0x3) << 5; |
| 16952 | break; |
| 16953 | } |
| 16954 | case AArch64::MOVA_2ZMXI_H_S: |
| 16955 | case AArch64::MOVA_2ZMXI_V_S: { |
| 16956 | // op: Zd |
| 16957 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 16958 | Value |= (op & 0xf) << 1; |
| 16959 | // op: Rs |
| 16960 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 16961 | Value |= (op & 0x3) << 13; |
| 16962 | // op: ZAn |
| 16963 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16964 | Value |= (op & 0x3) << 6; |
| 16965 | // op: imm |
| 16966 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16967 | Value |= (op & 0x1) << 5; |
| 16968 | break; |
| 16969 | } |
| 16970 | case AArch64::MOVA_2ZMXI_H_D: |
| 16971 | case AArch64::MOVA_2ZMXI_V_D: { |
| 16972 | // op: Zd |
| 16973 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 16974 | Value |= (op & 0xf) << 1; |
| 16975 | // op: Rs |
| 16976 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 16977 | Value |= (op & 0x3) << 13; |
| 16978 | // op: ZAn |
| 16979 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 16980 | Value |= (op & 0x7) << 5; |
| 16981 | break; |
| 16982 | } |
| 16983 | case AArch64::MOVA_2ZMXI_H_B: |
| 16984 | case AArch64::MOVA_2ZMXI_V_B: { |
| 16985 | // op: Zd |
| 16986 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 16987 | Value |= (op & 0xf) << 1; |
| 16988 | // op: Rs |
| 16989 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 16990 | Value |= (op & 0x3) << 13; |
| 16991 | // op: imm |
| 16992 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 16993 | Value |= (op & 0x7) << 5; |
| 16994 | break; |
| 16995 | } |
| 16996 | case AArch64::MOVAZ_2ZMI_H_H: |
| 16997 | case AArch64::MOVAZ_2ZMI_V_H: { |
| 16998 | // op: Zd |
| 16999 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 17000 | Value |= (op & 0xf) << 1; |
| 17001 | // op: Rs |
| 17002 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 17003 | Value |= (op & 0x3) << 13; |
| 17004 | // op: ZAn |
| 17005 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17006 | Value |= (op & 0x1) << 7; |
| 17007 | // op: imm |
| 17008 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 17009 | Value |= (op & 0x3) << 5; |
| 17010 | break; |
| 17011 | } |
| 17012 | case AArch64::MOVAZ_2ZMI_H_S: |
| 17013 | case AArch64::MOVAZ_2ZMI_V_S: { |
| 17014 | // op: Zd |
| 17015 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 17016 | Value |= (op & 0xf) << 1; |
| 17017 | // op: Rs |
| 17018 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 17019 | Value |= (op & 0x3) << 13; |
| 17020 | // op: ZAn |
| 17021 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17022 | Value |= (op & 0x3) << 6; |
| 17023 | // op: imm |
| 17024 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 17025 | Value |= (op & 0x1) << 5; |
| 17026 | break; |
| 17027 | } |
| 17028 | case AArch64::MOVAZ_2ZMI_H_D: |
| 17029 | case AArch64::MOVAZ_2ZMI_V_D: { |
| 17030 | // op: Zd |
| 17031 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 17032 | Value |= (op & 0xf) << 1; |
| 17033 | // op: Rs |
| 17034 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 17035 | Value |= (op & 0x3) << 13; |
| 17036 | // op: ZAn |
| 17037 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17038 | Value |= (op & 0x7) << 5; |
| 17039 | break; |
| 17040 | } |
| 17041 | case AArch64::MOVAZ_2ZMI_H_B: |
| 17042 | case AArch64::MOVAZ_2ZMI_V_B: { |
| 17043 | // op: Zd |
| 17044 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 17045 | Value |= (op & 0xf) << 1; |
| 17046 | // op: Rs |
| 17047 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 17048 | Value |= (op & 0x3) << 13; |
| 17049 | // op: imm |
| 17050 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 17051 | Value |= (op & 0x7) << 5; |
| 17052 | break; |
| 17053 | } |
| 17054 | case AArch64::UZP_VG2_2ZZZ_B: |
| 17055 | case AArch64::UZP_VG2_2ZZZ_D: |
| 17056 | case AArch64::UZP_VG2_2ZZZ_H: |
| 17057 | case AArch64::UZP_VG2_2ZZZ_Q: |
| 17058 | case AArch64::UZP_VG2_2ZZZ_S: |
| 17059 | case AArch64::ZIP_VG2_2ZZZ_B: |
| 17060 | case AArch64::ZIP_VG2_2ZZZ_D: |
| 17061 | case AArch64::ZIP_VG2_2ZZZ_H: |
| 17062 | case AArch64::ZIP_VG2_2ZZZ_Q: |
| 17063 | case AArch64::ZIP_VG2_2ZZZ_S: { |
| 17064 | // op: Zd |
| 17065 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 17066 | Value |= (op & 0xf) << 1; |
| 17067 | // op: Zm |
| 17068 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17069 | Value |= (op & 0x1f) << 16; |
| 17070 | // op: Zn |
| 17071 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17072 | Value |= (op & 0x1f) << 5; |
| 17073 | break; |
| 17074 | } |
| 17075 | case AArch64::BFMUL_2Z2Z: |
| 17076 | case AArch64::FMUL_2Z2Z_D: |
| 17077 | case AArch64::FMUL_2Z2Z_H: |
| 17078 | case AArch64::FMUL_2Z2Z_S: { |
| 17079 | // op: Zd |
| 17080 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 17081 | Value |= (op & 0xf) << 1; |
| 17082 | // op: Zn |
| 17083 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI); |
| 17084 | Value |= (op & 0xf) << 6; |
| 17085 | // op: Zm |
| 17086 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI); |
| 17087 | Value |= (op & 0xf) << 17; |
| 17088 | break; |
| 17089 | } |
| 17090 | case AArch64::BFMUL_2ZZ: |
| 17091 | case AArch64::FMUL_2ZZ_D: |
| 17092 | case AArch64::FMUL_2ZZ_H: |
| 17093 | case AArch64::FMUL_2ZZ_S: { |
| 17094 | // op: Zd |
| 17095 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 17096 | Value |= (op & 0xf) << 1; |
| 17097 | // op: Zn |
| 17098 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI); |
| 17099 | Value |= (op & 0xf) << 6; |
| 17100 | // op: Zm |
| 17101 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17102 | Value |= (op & 0xf) << 17; |
| 17103 | break; |
| 17104 | } |
| 17105 | case AArch64::MOVA_4ZMXI_H_H: |
| 17106 | case AArch64::MOVA_4ZMXI_V_H: { |
| 17107 | // op: Zd |
| 17108 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 17109 | Value |= (op & 0x7) << 2; |
| 17110 | // op: Rs |
| 17111 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 17112 | Value |= (op & 0x3) << 13; |
| 17113 | // op: ZAn |
| 17114 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17115 | Value |= (op & 0x1) << 6; |
| 17116 | // op: imm |
| 17117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17118 | Value |= (op & 0x1) << 5; |
| 17119 | break; |
| 17120 | } |
| 17121 | case AArch64::MOVA_4ZMXI_H_S: |
| 17122 | case AArch64::MOVA_4ZMXI_V_S: { |
| 17123 | // op: Zd |
| 17124 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 17125 | Value |= (op & 0x7) << 2; |
| 17126 | // op: Rs |
| 17127 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 17128 | Value |= (op & 0x3) << 13; |
| 17129 | // op: ZAn |
| 17130 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17131 | Value |= (op & 0x3) << 5; |
| 17132 | break; |
| 17133 | } |
| 17134 | case AArch64::MOVA_4ZMXI_H_D: |
| 17135 | case AArch64::MOVA_4ZMXI_V_D: { |
| 17136 | // op: Zd |
| 17137 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 17138 | Value |= (op & 0x7) << 2; |
| 17139 | // op: Rs |
| 17140 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 17141 | Value |= (op & 0x3) << 13; |
| 17142 | // op: ZAn |
| 17143 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17144 | Value |= (op & 0x7) << 5; |
| 17145 | break; |
| 17146 | } |
| 17147 | case AArch64::MOVA_4ZMXI_H_B: |
| 17148 | case AArch64::MOVA_4ZMXI_V_B: { |
| 17149 | // op: Zd |
| 17150 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 17151 | Value |= (op & 0x7) << 2; |
| 17152 | // op: Rs |
| 17153 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 2, Fixups, STI); |
| 17154 | Value |= (op & 0x3) << 13; |
| 17155 | // op: imm |
| 17156 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17157 | Value |= (op & 0x3) << 5; |
| 17158 | break; |
| 17159 | } |
| 17160 | case AArch64::MOVAZ_4ZMI_H_H: |
| 17161 | case AArch64::MOVAZ_4ZMI_V_H: { |
| 17162 | // op: Zd |
| 17163 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 17164 | Value |= (op & 0x7) << 2; |
| 17165 | // op: Rs |
| 17166 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 17167 | Value |= (op & 0x3) << 13; |
| 17168 | // op: ZAn |
| 17169 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17170 | Value |= (op & 0x1) << 6; |
| 17171 | // op: imm |
| 17172 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 17173 | Value |= (op & 0x1) << 5; |
| 17174 | break; |
| 17175 | } |
| 17176 | case AArch64::MOVAZ_4ZMI_H_S: |
| 17177 | case AArch64::MOVAZ_4ZMI_V_S: { |
| 17178 | // op: Zd |
| 17179 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 17180 | Value |= (op & 0x7) << 2; |
| 17181 | // op: Rs |
| 17182 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 17183 | Value |= (op & 0x3) << 13; |
| 17184 | // op: ZAn |
| 17185 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17186 | Value |= (op & 0x3) << 5; |
| 17187 | break; |
| 17188 | } |
| 17189 | case AArch64::MOVAZ_4ZMI_H_D: |
| 17190 | case AArch64::MOVAZ_4ZMI_V_D: { |
| 17191 | // op: Zd |
| 17192 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 17193 | Value |= (op & 0x7) << 2; |
| 17194 | // op: Rs |
| 17195 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 17196 | Value |= (op & 0x3) << 13; |
| 17197 | // op: ZAn |
| 17198 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17199 | Value |= (op & 0x7) << 5; |
| 17200 | break; |
| 17201 | } |
| 17202 | case AArch64::MOVAZ_4ZMI_H_B: |
| 17203 | case AArch64::MOVAZ_4ZMI_V_B: { |
| 17204 | // op: Zd |
| 17205 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 17206 | Value |= (op & 0x7) << 2; |
| 17207 | // op: Rs |
| 17208 | op = encodeMatrixIndexGPR32<AArch64::W12>(MI, OpIdx: 3, Fixups, STI); |
| 17209 | Value |= (op & 0x3) << 13; |
| 17210 | // op: imm |
| 17211 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 17212 | Value |= (op & 0x3) << 5; |
| 17213 | break; |
| 17214 | } |
| 17215 | case AArch64::LUTI6_4ZT3Z: { |
| 17216 | // op: Zd |
| 17217 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 17218 | Value |= (op & 0x7) << 2; |
| 17219 | // op: Zn |
| 17220 | op = EncodeRegMul_MinMax<1, 0, 7>(MI, OpIdx: 2, Fixups, STI); |
| 17221 | Value |= (op & 0x7) << 7; |
| 17222 | break; |
| 17223 | } |
| 17224 | case AArch64::BFMUL_4Z4Z: |
| 17225 | case AArch64::FMUL_4Z4Z_D: |
| 17226 | case AArch64::FMUL_4Z4Z_H: |
| 17227 | case AArch64::FMUL_4Z4Z_S: { |
| 17228 | // op: Zd |
| 17229 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 17230 | Value |= (op & 0x7) << 2; |
| 17231 | // op: Zn |
| 17232 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 1, Fixups, STI); |
| 17233 | Value |= (op & 0x7) << 7; |
| 17234 | // op: Zm |
| 17235 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 2, Fixups, STI); |
| 17236 | Value |= (op & 0x7) << 18; |
| 17237 | break; |
| 17238 | } |
| 17239 | case AArch64::BFMUL_4ZZ: |
| 17240 | case AArch64::FMUL_4ZZ_D: |
| 17241 | case AArch64::FMUL_4ZZ_H: |
| 17242 | case AArch64::FMUL_4ZZ_S: { |
| 17243 | // op: Zd |
| 17244 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 17245 | Value |= (op & 0x7) << 2; |
| 17246 | // op: Zn |
| 17247 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 1, Fixups, STI); |
| 17248 | Value |= (op & 0x7) << 7; |
| 17249 | // op: Zm |
| 17250 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17251 | Value |= (op & 0xf) << 17; |
| 17252 | break; |
| 17253 | } |
| 17254 | case AArch64::LUTI6_4Z2Z2ZI: { |
| 17255 | // op: Zd |
| 17256 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 17257 | Value |= (op & 0x7) << 2; |
| 17258 | // op: Zn |
| 17259 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17260 | Value |= (op & 0x1f) << 5; |
| 17261 | // op: Zm |
| 17262 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17263 | Value |= (op & 0x1f) << 16; |
| 17264 | // op: i1 |
| 17265 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17266 | Value |= (op & 0x1) << 22; |
| 17267 | break; |
| 17268 | } |
| 17269 | case AArch64::LUTI6_S_4ZT3Z: { |
| 17270 | // op: Zd |
| 17271 | op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI); |
| 17272 | Value |= (op & 0x4) << 2; |
| 17273 | Value |= (op & 0x3); |
| 17274 | // op: Zn |
| 17275 | op = EncodeRegMul_MinMax<1, 0, 7>(MI, OpIdx: 2, Fixups, STI); |
| 17276 | Value |= (op & 0x7) << 7; |
| 17277 | break; |
| 17278 | } |
| 17279 | case AArch64::LUTI6_S_4Z2Z2ZI: { |
| 17280 | // op: Zd |
| 17281 | op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI); |
| 17282 | Value |= (op & 0x4) << 2; |
| 17283 | Value |= (op & 0x3); |
| 17284 | // op: Zn |
| 17285 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17286 | Value |= (op & 0x1f) << 5; |
| 17287 | // op: Zm |
| 17288 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17289 | Value |= (op & 0x1f) << 16; |
| 17290 | // op: i1 |
| 17291 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17292 | Value |= (op & 0x1) << 22; |
| 17293 | break; |
| 17294 | } |
| 17295 | case AArch64::RBIT_ZPzZ_B: |
| 17296 | case AArch64::RBIT_ZPzZ_D: |
| 17297 | case AArch64::RBIT_ZPzZ_H: |
| 17298 | case AArch64::RBIT_ZPzZ_S: |
| 17299 | case AArch64::REVB_ZPzZ_D: |
| 17300 | case AArch64::REVB_ZPzZ_H: |
| 17301 | case AArch64::REVB_ZPzZ_S: |
| 17302 | case AArch64::REVD_ZPzZ: |
| 17303 | case AArch64::REVH_ZPzZ_D: |
| 17304 | case AArch64::REVH_ZPzZ_S: |
| 17305 | case AArch64::REVW_ZPzZ_D: { |
| 17306 | // op: Zd |
| 17307 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17308 | Value |= (op & 0x1f); |
| 17309 | // op: Pg |
| 17310 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17311 | Value |= (op & 0x7) << 10; |
| 17312 | // op: Zn |
| 17313 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17314 | Value |= (op & 0x1f) << 5; |
| 17315 | break; |
| 17316 | } |
| 17317 | case AArch64::CPY_ZPzI_B: |
| 17318 | case AArch64::CPY_ZPzI_D: |
| 17319 | case AArch64::CPY_ZPzI_H: |
| 17320 | case AArch64::CPY_ZPzI_S: { |
| 17321 | // op: Zd |
| 17322 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17323 | Value |= (op & 0x1f); |
| 17324 | // op: Pg |
| 17325 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17326 | Value |= (op & 0xf) << 16; |
| 17327 | // op: imm |
| 17328 | op = getImm8OptLsl(MI, OpIdx: 2, Fixups, STI); |
| 17329 | Value |= (op & 0x1ff) << 5; |
| 17330 | break; |
| 17331 | } |
| 17332 | case AArch64::RBIT_ZPmZ_B: |
| 17333 | case AArch64::RBIT_ZPmZ_D: |
| 17334 | case AArch64::RBIT_ZPmZ_H: |
| 17335 | case AArch64::RBIT_ZPmZ_S: |
| 17336 | case AArch64::REVB_ZPmZ_D: |
| 17337 | case AArch64::REVB_ZPmZ_H: |
| 17338 | case AArch64::REVB_ZPmZ_S: |
| 17339 | case AArch64::REVD_ZPmZ: |
| 17340 | case AArch64::REVH_ZPmZ_D: |
| 17341 | case AArch64::REVH_ZPmZ_S: |
| 17342 | case AArch64::REVW_ZPmZ_D: { |
| 17343 | // op: Zd |
| 17344 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17345 | Value |= (op & 0x1f); |
| 17346 | // op: Pg |
| 17347 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17348 | Value |= (op & 0x7) << 10; |
| 17349 | // op: Zn |
| 17350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17351 | Value |= (op & 0x1f) << 5; |
| 17352 | break; |
| 17353 | } |
| 17354 | case AArch64::CPY_ZPmI_B: |
| 17355 | case AArch64::CPY_ZPmI_D: |
| 17356 | case AArch64::CPY_ZPmI_H: |
| 17357 | case AArch64::CPY_ZPmI_S: { |
| 17358 | // op: Zd |
| 17359 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17360 | Value |= (op & 0x1f); |
| 17361 | // op: Pg |
| 17362 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17363 | Value |= (op & 0xf) << 16; |
| 17364 | // op: imm |
| 17365 | op = getImm8OptLsl(MI, OpIdx: 3, Fixups, STI); |
| 17366 | Value |= (op & 0x1ff) << 5; |
| 17367 | break; |
| 17368 | } |
| 17369 | case AArch64::PMOV_ZIP_B: { |
| 17370 | // op: Zd |
| 17371 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17372 | Value |= (op & 0x1f); |
| 17373 | // op: Pn |
| 17374 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17375 | Value |= (op & 0xf) << 5; |
| 17376 | break; |
| 17377 | } |
| 17378 | case AArch64::PMOV_ZIP_H: { |
| 17379 | // op: Zd |
| 17380 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17381 | Value |= (op & 0x1f); |
| 17382 | // op: Pn |
| 17383 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17384 | Value |= (op & 0xf) << 5; |
| 17385 | // op: index |
| 17386 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17387 | Value |= (op & 0x1) << 17; |
| 17388 | break; |
| 17389 | } |
| 17390 | case AArch64::PMOV_ZIP_S: { |
| 17391 | // op: Zd |
| 17392 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17393 | Value |= (op & 0x1f); |
| 17394 | // op: Pn |
| 17395 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17396 | Value |= (op & 0xf) << 5; |
| 17397 | // op: index |
| 17398 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17399 | Value |= (op & 0x3) << 17; |
| 17400 | break; |
| 17401 | } |
| 17402 | case AArch64::PMOV_ZIP_D: { |
| 17403 | // op: Zd |
| 17404 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17405 | Value |= (op & 0x1f); |
| 17406 | // op: Pn |
| 17407 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17408 | Value |= (op & 0xf) << 5; |
| 17409 | // op: index |
| 17410 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17411 | Value |= (op & 0x4) << 20; |
| 17412 | Value |= (op & 0x3) << 17; |
| 17413 | break; |
| 17414 | } |
| 17415 | case AArch64::INDEX_RR_B: |
| 17416 | case AArch64::INDEX_RR_D: |
| 17417 | case AArch64::INDEX_RR_H: |
| 17418 | case AArch64::INDEX_RR_S: { |
| 17419 | // op: Zd |
| 17420 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17421 | Value |= (op & 0x1f); |
| 17422 | // op: Rm |
| 17423 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17424 | Value |= (op & 0x1f) << 16; |
| 17425 | // op: Rn |
| 17426 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17427 | Value |= (op & 0x1f) << 5; |
| 17428 | break; |
| 17429 | } |
| 17430 | case AArch64::ADDQP_ZZZ_B: |
| 17431 | case AArch64::ADDQP_ZZZ_D: |
| 17432 | case AArch64::ADDQP_ZZZ_H: |
| 17433 | case AArch64::ADDQP_ZZZ_S: |
| 17434 | case AArch64::ADDSUBP_ZZZ_B: |
| 17435 | case AArch64::ADDSUBP_ZZZ_D: |
| 17436 | case AArch64::ADDSUBP_ZZZ_H: |
| 17437 | case AArch64::ADDSUBP_ZZZ_S: |
| 17438 | case AArch64::ADD_ZZZ_B: |
| 17439 | case AArch64::ADD_ZZZ_CPA: |
| 17440 | case AArch64::ADD_ZZZ_D: |
| 17441 | case AArch64::ADD_ZZZ_H: |
| 17442 | case AArch64::ADD_ZZZ_S: |
| 17443 | case AArch64::AND_ZZZ: |
| 17444 | case AArch64::ASR_WIDE_ZZZ_B: |
| 17445 | case AArch64::ASR_WIDE_ZZZ_H: |
| 17446 | case AArch64::ASR_WIDE_ZZZ_S: |
| 17447 | case AArch64::BFADD_ZZZ: |
| 17448 | case AArch64::BFMUL_ZZZ: |
| 17449 | case AArch64::BFSUB_ZZZ: |
| 17450 | case AArch64::BIC_ZZZ: |
| 17451 | case AArch64::EOR_ZZZ: |
| 17452 | case AArch64::FADD_ZZZ_D: |
| 17453 | case AArch64::FADD_ZZZ_H: |
| 17454 | case AArch64::FADD_ZZZ_S: |
| 17455 | case AArch64::FMUL_ZZZ_D: |
| 17456 | case AArch64::FMUL_ZZZ_H: |
| 17457 | case AArch64::FMUL_ZZZ_S: |
| 17458 | case AArch64::FRECPS_ZZZ_D: |
| 17459 | case AArch64::FRECPS_ZZZ_H: |
| 17460 | case AArch64::FRECPS_ZZZ_S: |
| 17461 | case AArch64::FRSQRTS_ZZZ_D: |
| 17462 | case AArch64::FRSQRTS_ZZZ_H: |
| 17463 | case AArch64::FRSQRTS_ZZZ_S: |
| 17464 | case AArch64::FSUB_ZZZ_D: |
| 17465 | case AArch64::FSUB_ZZZ_H: |
| 17466 | case AArch64::FSUB_ZZZ_S: |
| 17467 | case AArch64::FTSMUL_ZZZ_D: |
| 17468 | case AArch64::FTSMUL_ZZZ_H: |
| 17469 | case AArch64::FTSMUL_ZZZ_S: |
| 17470 | case AArch64::FTSSEL_ZZZ_D: |
| 17471 | case AArch64::FTSSEL_ZZZ_H: |
| 17472 | case AArch64::FTSSEL_ZZZ_S: |
| 17473 | case AArch64::LSL_WIDE_ZZZ_B: |
| 17474 | case AArch64::LSL_WIDE_ZZZ_H: |
| 17475 | case AArch64::LSL_WIDE_ZZZ_S: |
| 17476 | case AArch64::LSR_WIDE_ZZZ_B: |
| 17477 | case AArch64::LSR_WIDE_ZZZ_H: |
| 17478 | case AArch64::LSR_WIDE_ZZZ_S: |
| 17479 | case AArch64::MUL_ZZZ_B: |
| 17480 | case AArch64::MUL_ZZZ_D: |
| 17481 | case AArch64::MUL_ZZZ_H: |
| 17482 | case AArch64::MUL_ZZZ_S: |
| 17483 | case AArch64::ORR_ZZZ: |
| 17484 | case AArch64::PMUL_ZZZ_B: |
| 17485 | case AArch64::SMULH_ZZZ_B: |
| 17486 | case AArch64::SMULH_ZZZ_D: |
| 17487 | case AArch64::SMULH_ZZZ_H: |
| 17488 | case AArch64::SMULH_ZZZ_S: |
| 17489 | case AArch64::SQADD_ZZZ_B: |
| 17490 | case AArch64::SQADD_ZZZ_D: |
| 17491 | case AArch64::SQADD_ZZZ_H: |
| 17492 | case AArch64::SQADD_ZZZ_S: |
| 17493 | case AArch64::SQDMULH_ZZZ_B: |
| 17494 | case AArch64::SQDMULH_ZZZ_D: |
| 17495 | case AArch64::SQDMULH_ZZZ_H: |
| 17496 | case AArch64::SQDMULH_ZZZ_S: |
| 17497 | case AArch64::SQRDMULH_ZZZ_B: |
| 17498 | case AArch64::SQRDMULH_ZZZ_D: |
| 17499 | case AArch64::SQRDMULH_ZZZ_H: |
| 17500 | case AArch64::SQRDMULH_ZZZ_S: |
| 17501 | case AArch64::SQSUB_ZZZ_B: |
| 17502 | case AArch64::SQSUB_ZZZ_D: |
| 17503 | case AArch64::SQSUB_ZZZ_H: |
| 17504 | case AArch64::SQSUB_ZZZ_S: |
| 17505 | case AArch64::SUB_ZZZ_B: |
| 17506 | case AArch64::SUB_ZZZ_CPA: |
| 17507 | case AArch64::SUB_ZZZ_D: |
| 17508 | case AArch64::SUB_ZZZ_H: |
| 17509 | case AArch64::SUB_ZZZ_S: |
| 17510 | case AArch64::TBL_ZZZZ_B: |
| 17511 | case AArch64::TBL_ZZZZ_D: |
| 17512 | case AArch64::TBL_ZZZZ_H: |
| 17513 | case AArch64::TBL_ZZZZ_S: |
| 17514 | case AArch64::TBL_ZZZ_B: |
| 17515 | case AArch64::TBL_ZZZ_D: |
| 17516 | case AArch64::TBL_ZZZ_H: |
| 17517 | case AArch64::TBL_ZZZ_S: |
| 17518 | case AArch64::TRN1_ZZZ_B: |
| 17519 | case AArch64::TRN1_ZZZ_D: |
| 17520 | case AArch64::TRN1_ZZZ_H: |
| 17521 | case AArch64::TRN1_ZZZ_Q: |
| 17522 | case AArch64::TRN1_ZZZ_S: |
| 17523 | case AArch64::TRN2_ZZZ_B: |
| 17524 | case AArch64::TRN2_ZZZ_D: |
| 17525 | case AArch64::TRN2_ZZZ_H: |
| 17526 | case AArch64::TRN2_ZZZ_Q: |
| 17527 | case AArch64::TRN2_ZZZ_S: |
| 17528 | case AArch64::UMULH_ZZZ_B: |
| 17529 | case AArch64::UMULH_ZZZ_D: |
| 17530 | case AArch64::UMULH_ZZZ_H: |
| 17531 | case AArch64::UMULH_ZZZ_S: |
| 17532 | case AArch64::UQADD_ZZZ_B: |
| 17533 | case AArch64::UQADD_ZZZ_D: |
| 17534 | case AArch64::UQADD_ZZZ_H: |
| 17535 | case AArch64::UQADD_ZZZ_S: |
| 17536 | case AArch64::UQSUB_ZZZ_B: |
| 17537 | case AArch64::UQSUB_ZZZ_D: |
| 17538 | case AArch64::UQSUB_ZZZ_H: |
| 17539 | case AArch64::UQSUB_ZZZ_S: |
| 17540 | case AArch64::UZP1_ZZZ_B: |
| 17541 | case AArch64::UZP1_ZZZ_D: |
| 17542 | case AArch64::UZP1_ZZZ_H: |
| 17543 | case AArch64::UZP1_ZZZ_Q: |
| 17544 | case AArch64::UZP1_ZZZ_S: |
| 17545 | case AArch64::UZP2_ZZZ_B: |
| 17546 | case AArch64::UZP2_ZZZ_D: |
| 17547 | case AArch64::UZP2_ZZZ_H: |
| 17548 | case AArch64::UZP2_ZZZ_Q: |
| 17549 | case AArch64::UZP2_ZZZ_S: |
| 17550 | case AArch64::ZIP1_ZZZ_B: |
| 17551 | case AArch64::ZIP1_ZZZ_D: |
| 17552 | case AArch64::ZIP1_ZZZ_H: |
| 17553 | case AArch64::ZIP1_ZZZ_Q: |
| 17554 | case AArch64::ZIP1_ZZZ_S: |
| 17555 | case AArch64::ZIP2_ZZZ_B: |
| 17556 | case AArch64::ZIP2_ZZZ_D: |
| 17557 | case AArch64::ZIP2_ZZZ_H: |
| 17558 | case AArch64::ZIP2_ZZZ_Q: |
| 17559 | case AArch64::ZIP2_ZZZ_S: { |
| 17560 | // op: Zd |
| 17561 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17562 | Value |= (op & 0x1f); |
| 17563 | // op: Zm |
| 17564 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17565 | Value |= (op & 0x1f) << 16; |
| 17566 | // op: Zn |
| 17567 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17568 | Value |= (op & 0x1f) << 5; |
| 17569 | break; |
| 17570 | } |
| 17571 | case AArch64::TBXQ_ZZZ_B: |
| 17572 | case AArch64::TBXQ_ZZZ_D: |
| 17573 | case AArch64::TBXQ_ZZZ_H: |
| 17574 | case AArch64::TBXQ_ZZZ_S: |
| 17575 | case AArch64::TBX_ZZZ_B: |
| 17576 | case AArch64::TBX_ZZZ_D: |
| 17577 | case AArch64::TBX_ZZZ_H: |
| 17578 | case AArch64::TBX_ZZZ_S: { |
| 17579 | // op: Zd |
| 17580 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17581 | Value |= (op & 0x1f); |
| 17582 | // op: Zm |
| 17583 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17584 | Value |= (op & 0x1f) << 16; |
| 17585 | // op: Zn |
| 17586 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17587 | Value |= (op & 0x1f) << 5; |
| 17588 | break; |
| 17589 | } |
| 17590 | case AArch64::BFCVTN_Z2Z_HtoB: |
| 17591 | case AArch64::FCVTNB_Z2Z_StoB: |
| 17592 | case AArch64::FCVTN_Z2Z_HtoB: |
| 17593 | case AArch64::FCVTZSN_Z2Z_DtoS: |
| 17594 | case AArch64::FCVTZSN_Z2Z_HtoB: |
| 17595 | case AArch64::FCVTZSN_Z2Z_StoH: |
| 17596 | case AArch64::FCVTZUN_Z2Z_DtoS: |
| 17597 | case AArch64::FCVTZUN_Z2Z_HtoB: |
| 17598 | case AArch64::FCVTZUN_Z2Z_StoH: |
| 17599 | case AArch64::SQCVTN_Z2Z_StoH: |
| 17600 | case AArch64::SQCVTUN_Z2Z_StoH: |
| 17601 | case AArch64::UQCVTN_Z2Z_StoH: { |
| 17602 | // op: Zd |
| 17603 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17604 | Value |= (op & 0x1f); |
| 17605 | // op: Zn |
| 17606 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI); |
| 17607 | Value |= (op & 0xf) << 6; |
| 17608 | break; |
| 17609 | } |
| 17610 | case AArch64::SQRSHRN_Z2ZI_StoH: |
| 17611 | case AArch64::SQRSHRUN_Z2ZI_StoH: |
| 17612 | case AArch64::SQSHRN_Z2ZI_StoH: |
| 17613 | case AArch64::SQSHRUN_Z2ZI_StoH: |
| 17614 | case AArch64::UQRSHRN_Z2ZI_StoH: |
| 17615 | case AArch64::UQSHRN_Z2ZI_StoH: { |
| 17616 | // op: Zd |
| 17617 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17618 | Value |= (op & 0x1f); |
| 17619 | // op: Zn |
| 17620 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI); |
| 17621 | Value |= (op & 0xf) << 6; |
| 17622 | // op: imm |
| 17623 | op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI); |
| 17624 | Value |= (op & 0xf) << 16; |
| 17625 | break; |
| 17626 | } |
| 17627 | case AArch64::SQRSHRN_Z2ZI_HtoB: |
| 17628 | case AArch64::SQRSHRUN_Z2ZI_HtoB: |
| 17629 | case AArch64::SQSHRN_Z2ZI_HtoB: |
| 17630 | case AArch64::SQSHRUN_Z2ZI_HtoB: |
| 17631 | case AArch64::UQRSHRN_Z2ZI_HtoB: |
| 17632 | case AArch64::UQSHRN_Z2ZI_HtoB: { |
| 17633 | // op: Zd |
| 17634 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17635 | Value |= (op & 0x1f); |
| 17636 | // op: Zn |
| 17637 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI); |
| 17638 | Value |= (op & 0xf) << 6; |
| 17639 | // op: imm |
| 17640 | op = getVecShiftR8OpValue(MI, OpIdx: 2, Fixups, STI); |
| 17641 | Value |= (op & 0x7) << 16; |
| 17642 | break; |
| 17643 | } |
| 17644 | case AArch64::FCVTNT_Z2Z_StoB: { |
| 17645 | // op: Zd |
| 17646 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17647 | Value |= (op & 0x1f); |
| 17648 | // op: Zn |
| 17649 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI); |
| 17650 | Value |= (op & 0xf) << 6; |
| 17651 | break; |
| 17652 | } |
| 17653 | case AArch64::BF1CVTLT_ZZ_BtoH: |
| 17654 | case AArch64::BF1CVT_ZZ_BtoH: |
| 17655 | case AArch64::BF2CVTLT_ZZ_BtoH: |
| 17656 | case AArch64::BF2CVT_ZZ_BtoH: |
| 17657 | case AArch64::F1CVTLT_ZZ_BtoH: |
| 17658 | case AArch64::F1CVT_ZZ_BtoH: |
| 17659 | case AArch64::F2CVTLT_ZZ_BtoH: |
| 17660 | case AArch64::F2CVT_ZZ_BtoH: |
| 17661 | case AArch64::FEXPA_ZZ_D: |
| 17662 | case AArch64::FEXPA_ZZ_H: |
| 17663 | case AArch64::FEXPA_ZZ_S: |
| 17664 | case AArch64::FRECPE_ZZ_D: |
| 17665 | case AArch64::FRECPE_ZZ_H: |
| 17666 | case AArch64::FRECPE_ZZ_S: |
| 17667 | case AArch64::FRSQRTE_ZZ_D: |
| 17668 | case AArch64::FRSQRTE_ZZ_H: |
| 17669 | case AArch64::FRSQRTE_ZZ_S: |
| 17670 | case AArch64::MOVPRFX_ZZ: |
| 17671 | case AArch64::REV_ZZ_B: |
| 17672 | case AArch64::REV_ZZ_D: |
| 17673 | case AArch64::REV_ZZ_H: |
| 17674 | case AArch64::REV_ZZ_S: |
| 17675 | case AArch64::SCVTFLT_ZZ_BtoH: |
| 17676 | case AArch64::SCVTFLT_ZZ_HtoS: |
| 17677 | case AArch64::SCVTFLT_ZZ_StoD: |
| 17678 | case AArch64::SCVTF_ZZ_BtoH: |
| 17679 | case AArch64::SCVTF_ZZ_HtoS: |
| 17680 | case AArch64::SCVTF_ZZ_StoD: |
| 17681 | case AArch64::SQXTNB_ZZ_B: |
| 17682 | case AArch64::SQXTNB_ZZ_H: |
| 17683 | case AArch64::SQXTNB_ZZ_S: |
| 17684 | case AArch64::SQXTUNB_ZZ_B: |
| 17685 | case AArch64::SQXTUNB_ZZ_H: |
| 17686 | case AArch64::SQXTUNB_ZZ_S: |
| 17687 | case AArch64::SUNPKHI_ZZ_D: |
| 17688 | case AArch64::SUNPKHI_ZZ_H: |
| 17689 | case AArch64::SUNPKHI_ZZ_S: |
| 17690 | case AArch64::SUNPKLO_ZZ_D: |
| 17691 | case AArch64::SUNPKLO_ZZ_H: |
| 17692 | case AArch64::SUNPKLO_ZZ_S: |
| 17693 | case AArch64::UCVTFLT_ZZ_BtoH: |
| 17694 | case AArch64::UCVTFLT_ZZ_HtoS: |
| 17695 | case AArch64::UCVTFLT_ZZ_StoD: |
| 17696 | case AArch64::UCVTF_ZZ_BtoH: |
| 17697 | case AArch64::UCVTF_ZZ_HtoS: |
| 17698 | case AArch64::UCVTF_ZZ_StoD: |
| 17699 | case AArch64::UQXTNB_ZZ_B: |
| 17700 | case AArch64::UQXTNB_ZZ_H: |
| 17701 | case AArch64::UQXTNB_ZZ_S: |
| 17702 | case AArch64::UUNPKHI_ZZ_D: |
| 17703 | case AArch64::UUNPKHI_ZZ_H: |
| 17704 | case AArch64::UUNPKHI_ZZ_S: |
| 17705 | case AArch64::UUNPKLO_ZZ_D: |
| 17706 | case AArch64::UUNPKLO_ZZ_H: |
| 17707 | case AArch64::UUNPKLO_ZZ_S: { |
| 17708 | // op: Zd |
| 17709 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17710 | Value |= (op & 0x1f); |
| 17711 | // op: Zn |
| 17712 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17713 | Value |= (op & 0x1f) << 5; |
| 17714 | break; |
| 17715 | } |
| 17716 | case AArch64::ADDHNB_ZZZ_B: |
| 17717 | case AArch64::ADDHNB_ZZZ_H: |
| 17718 | case AArch64::ADDHNB_ZZZ_S: |
| 17719 | case AArch64::ADR_LSL_ZZZ_D_0: |
| 17720 | case AArch64::ADR_LSL_ZZZ_D_1: |
| 17721 | case AArch64::ADR_LSL_ZZZ_D_2: |
| 17722 | case AArch64::ADR_LSL_ZZZ_D_3: |
| 17723 | case AArch64::ADR_LSL_ZZZ_S_0: |
| 17724 | case AArch64::ADR_LSL_ZZZ_S_1: |
| 17725 | case AArch64::ADR_LSL_ZZZ_S_2: |
| 17726 | case AArch64::ADR_LSL_ZZZ_S_3: |
| 17727 | case AArch64::ADR_SXTW_ZZZ_D_0: |
| 17728 | case AArch64::ADR_SXTW_ZZZ_D_1: |
| 17729 | case AArch64::ADR_SXTW_ZZZ_D_2: |
| 17730 | case AArch64::ADR_SXTW_ZZZ_D_3: |
| 17731 | case AArch64::ADR_UXTW_ZZZ_D_0: |
| 17732 | case AArch64::ADR_UXTW_ZZZ_D_1: |
| 17733 | case AArch64::ADR_UXTW_ZZZ_D_2: |
| 17734 | case AArch64::ADR_UXTW_ZZZ_D_3: |
| 17735 | case AArch64::BDEP_ZZZ_B: |
| 17736 | case AArch64::BDEP_ZZZ_D: |
| 17737 | case AArch64::BDEP_ZZZ_H: |
| 17738 | case AArch64::BDEP_ZZZ_S: |
| 17739 | case AArch64::BEXT_ZZZ_B: |
| 17740 | case AArch64::BEXT_ZZZ_D: |
| 17741 | case AArch64::BEXT_ZZZ_H: |
| 17742 | case AArch64::BEXT_ZZZ_S: |
| 17743 | case AArch64::BGRP_ZZZ_B: |
| 17744 | case AArch64::BGRP_ZZZ_D: |
| 17745 | case AArch64::BGRP_ZZZ_H: |
| 17746 | case AArch64::BGRP_ZZZ_S: |
| 17747 | case AArch64::HISTSEG_ZZZ: |
| 17748 | case AArch64::LUTI6_Z2ZZ: |
| 17749 | case AArch64::PMULLB_ZZZ_D: |
| 17750 | case AArch64::PMULLB_ZZZ_H: |
| 17751 | case AArch64::PMULLB_ZZZ_Q: |
| 17752 | case AArch64::PMULLT_ZZZ_D: |
| 17753 | case AArch64::PMULLT_ZZZ_H: |
| 17754 | case AArch64::PMULLT_ZZZ_Q: |
| 17755 | case AArch64::RADDHNB_ZZZ_B: |
| 17756 | case AArch64::RADDHNB_ZZZ_H: |
| 17757 | case AArch64::RADDHNB_ZZZ_S: |
| 17758 | case AArch64::RAX1_ZZZ_D: |
| 17759 | case AArch64::RSUBHNB_ZZZ_B: |
| 17760 | case AArch64::RSUBHNB_ZZZ_H: |
| 17761 | case AArch64::RSUBHNB_ZZZ_S: |
| 17762 | case AArch64::SABDLB_ZZZ_D: |
| 17763 | case AArch64::SABDLB_ZZZ_H: |
| 17764 | case AArch64::SABDLB_ZZZ_S: |
| 17765 | case AArch64::SABDLT_ZZZ_D: |
| 17766 | case AArch64::SABDLT_ZZZ_H: |
| 17767 | case AArch64::SABDLT_ZZZ_S: |
| 17768 | case AArch64::SADDLBT_ZZZ_D: |
| 17769 | case AArch64::SADDLBT_ZZZ_H: |
| 17770 | case AArch64::SADDLBT_ZZZ_S: |
| 17771 | case AArch64::SADDLB_ZZZ_D: |
| 17772 | case AArch64::SADDLB_ZZZ_H: |
| 17773 | case AArch64::SADDLB_ZZZ_S: |
| 17774 | case AArch64::SADDLT_ZZZ_D: |
| 17775 | case AArch64::SADDLT_ZZZ_H: |
| 17776 | case AArch64::SADDLT_ZZZ_S: |
| 17777 | case AArch64::SADDWB_ZZZ_D: |
| 17778 | case AArch64::SADDWB_ZZZ_H: |
| 17779 | case AArch64::SADDWB_ZZZ_S: |
| 17780 | case AArch64::SADDWT_ZZZ_D: |
| 17781 | case AArch64::SADDWT_ZZZ_H: |
| 17782 | case AArch64::SADDWT_ZZZ_S: |
| 17783 | case AArch64::SM4EKEY_ZZZ_S: |
| 17784 | case AArch64::SMULLB_ZZZ_D: |
| 17785 | case AArch64::SMULLB_ZZZ_H: |
| 17786 | case AArch64::SMULLB_ZZZ_S: |
| 17787 | case AArch64::SMULLT_ZZZ_D: |
| 17788 | case AArch64::SMULLT_ZZZ_H: |
| 17789 | case AArch64::SMULLT_ZZZ_S: |
| 17790 | case AArch64::SQDMULLB_ZZZ_D: |
| 17791 | case AArch64::SQDMULLB_ZZZ_H: |
| 17792 | case AArch64::SQDMULLB_ZZZ_S: |
| 17793 | case AArch64::SQDMULLT_ZZZ_D: |
| 17794 | case AArch64::SQDMULLT_ZZZ_H: |
| 17795 | case AArch64::SQDMULLT_ZZZ_S: |
| 17796 | case AArch64::SSUBLBT_ZZZ_D: |
| 17797 | case AArch64::SSUBLBT_ZZZ_H: |
| 17798 | case AArch64::SSUBLBT_ZZZ_S: |
| 17799 | case AArch64::SSUBLB_ZZZ_D: |
| 17800 | case AArch64::SSUBLB_ZZZ_H: |
| 17801 | case AArch64::SSUBLB_ZZZ_S: |
| 17802 | case AArch64::SSUBLTB_ZZZ_D: |
| 17803 | case AArch64::SSUBLTB_ZZZ_H: |
| 17804 | case AArch64::SSUBLTB_ZZZ_S: |
| 17805 | case AArch64::SSUBLT_ZZZ_D: |
| 17806 | case AArch64::SSUBLT_ZZZ_H: |
| 17807 | case AArch64::SSUBLT_ZZZ_S: |
| 17808 | case AArch64::SSUBWB_ZZZ_D: |
| 17809 | case AArch64::SSUBWB_ZZZ_H: |
| 17810 | case AArch64::SSUBWB_ZZZ_S: |
| 17811 | case AArch64::SSUBWT_ZZZ_D: |
| 17812 | case AArch64::SSUBWT_ZZZ_H: |
| 17813 | case AArch64::SSUBWT_ZZZ_S: |
| 17814 | case AArch64::SUBHNB_ZZZ_B: |
| 17815 | case AArch64::SUBHNB_ZZZ_H: |
| 17816 | case AArch64::SUBHNB_ZZZ_S: |
| 17817 | case AArch64::TBLQ_ZZZ_B: |
| 17818 | case AArch64::TBLQ_ZZZ_D: |
| 17819 | case AArch64::TBLQ_ZZZ_H: |
| 17820 | case AArch64::TBLQ_ZZZ_S: |
| 17821 | case AArch64::UABDLB_ZZZ_D: |
| 17822 | case AArch64::UABDLB_ZZZ_H: |
| 17823 | case AArch64::UABDLB_ZZZ_S: |
| 17824 | case AArch64::UABDLT_ZZZ_D: |
| 17825 | case AArch64::UABDLT_ZZZ_H: |
| 17826 | case AArch64::UABDLT_ZZZ_S: |
| 17827 | case AArch64::UADDLB_ZZZ_D: |
| 17828 | case AArch64::UADDLB_ZZZ_H: |
| 17829 | case AArch64::UADDLB_ZZZ_S: |
| 17830 | case AArch64::UADDLT_ZZZ_D: |
| 17831 | case AArch64::UADDLT_ZZZ_H: |
| 17832 | case AArch64::UADDLT_ZZZ_S: |
| 17833 | case AArch64::UADDWB_ZZZ_D: |
| 17834 | case AArch64::UADDWB_ZZZ_H: |
| 17835 | case AArch64::UADDWB_ZZZ_S: |
| 17836 | case AArch64::UADDWT_ZZZ_D: |
| 17837 | case AArch64::UADDWT_ZZZ_H: |
| 17838 | case AArch64::UADDWT_ZZZ_S: |
| 17839 | case AArch64::UMULLB_ZZZ_D: |
| 17840 | case AArch64::UMULLB_ZZZ_H: |
| 17841 | case AArch64::UMULLB_ZZZ_S: |
| 17842 | case AArch64::UMULLT_ZZZ_D: |
| 17843 | case AArch64::UMULLT_ZZZ_H: |
| 17844 | case AArch64::UMULLT_ZZZ_S: |
| 17845 | case AArch64::USUBLB_ZZZ_D: |
| 17846 | case AArch64::USUBLB_ZZZ_H: |
| 17847 | case AArch64::USUBLB_ZZZ_S: |
| 17848 | case AArch64::USUBLT_ZZZ_D: |
| 17849 | case AArch64::USUBLT_ZZZ_H: |
| 17850 | case AArch64::USUBLT_ZZZ_S: |
| 17851 | case AArch64::USUBWB_ZZZ_D: |
| 17852 | case AArch64::USUBWB_ZZZ_H: |
| 17853 | case AArch64::USUBWB_ZZZ_S: |
| 17854 | case AArch64::USUBWT_ZZZ_D: |
| 17855 | case AArch64::USUBWT_ZZZ_H: |
| 17856 | case AArch64::USUBWT_ZZZ_S: |
| 17857 | case AArch64::UZPQ1_ZZZ_B: |
| 17858 | case AArch64::UZPQ1_ZZZ_D: |
| 17859 | case AArch64::UZPQ1_ZZZ_H: |
| 17860 | case AArch64::UZPQ1_ZZZ_S: |
| 17861 | case AArch64::UZPQ2_ZZZ_B: |
| 17862 | case AArch64::UZPQ2_ZZZ_D: |
| 17863 | case AArch64::UZPQ2_ZZZ_H: |
| 17864 | case AArch64::UZPQ2_ZZZ_S: |
| 17865 | case AArch64::ZIPQ1_ZZZ_B: |
| 17866 | case AArch64::ZIPQ1_ZZZ_D: |
| 17867 | case AArch64::ZIPQ1_ZZZ_H: |
| 17868 | case AArch64::ZIPQ1_ZZZ_S: |
| 17869 | case AArch64::ZIPQ2_ZZZ_B: |
| 17870 | case AArch64::ZIPQ2_ZZZ_D: |
| 17871 | case AArch64::ZIPQ2_ZZZ_H: |
| 17872 | case AArch64::ZIPQ2_ZZZ_S: { |
| 17873 | // op: Zd |
| 17874 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17875 | Value |= (op & 0x1f); |
| 17876 | // op: Zn |
| 17877 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17878 | Value |= (op & 0x1f) << 5; |
| 17879 | // op: Zm |
| 17880 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17881 | Value |= (op & 0x1f) << 16; |
| 17882 | break; |
| 17883 | } |
| 17884 | case AArch64::LUTI4_ZZZI_B: |
| 17885 | case AArch64::LUTI6_Z2ZZI_H: { |
| 17886 | // op: Zd |
| 17887 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17888 | Value |= (op & 0x1f); |
| 17889 | // op: Zn |
| 17890 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17891 | Value |= (op & 0x1f) << 5; |
| 17892 | // op: Zm |
| 17893 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17894 | Value |= (op & 0x1f) << 16; |
| 17895 | // op: idx |
| 17896 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17897 | Value |= (op & 0x1) << 23; |
| 17898 | break; |
| 17899 | } |
| 17900 | case AArch64::LUTI2_ZZZI_B: |
| 17901 | case AArch64::LUTI4_Z2ZZI: |
| 17902 | case AArch64::LUTI4_ZZZI_H: { |
| 17903 | // op: Zd |
| 17904 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17905 | Value |= (op & 0x1f); |
| 17906 | // op: Zn |
| 17907 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17908 | Value |= (op & 0x1f) << 5; |
| 17909 | // op: Zm |
| 17910 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17911 | Value |= (op & 0x1f) << 16; |
| 17912 | // op: idx |
| 17913 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17914 | Value |= (op & 0x3) << 22; |
| 17915 | break; |
| 17916 | } |
| 17917 | case AArch64::LUTI2_ZZZI_H: { |
| 17918 | // op: Zd |
| 17919 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17920 | Value |= (op & 0x1f); |
| 17921 | // op: Zn |
| 17922 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17923 | Value |= (op & 0x1f) << 5; |
| 17924 | // op: Zm |
| 17925 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17926 | Value |= (op & 0x1f) << 16; |
| 17927 | // op: idx |
| 17928 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17929 | Value |= (op & 0x6) << 21; |
| 17930 | Value |= (op & 0x1) << 12; |
| 17931 | break; |
| 17932 | } |
| 17933 | case AArch64::FMUL_ZZZI_S: |
| 17934 | case AArch64::MUL_ZZZI_S: |
| 17935 | case AArch64::SQDMULH_ZZZI_S: |
| 17936 | case AArch64::SQRDMULH_ZZZI_S: { |
| 17937 | // op: Zd |
| 17938 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17939 | Value |= (op & 0x1f); |
| 17940 | // op: Zn |
| 17941 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17942 | Value |= (op & 0x1f) << 5; |
| 17943 | // op: Zm |
| 17944 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17945 | Value |= (op & 0x7) << 16; |
| 17946 | // op: iop |
| 17947 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17948 | Value |= (op & 0x3) << 19; |
| 17949 | break; |
| 17950 | } |
| 17951 | case AArch64::BFMUL_ZZZI: |
| 17952 | case AArch64::FMUL_ZZZI_H: |
| 17953 | case AArch64::MUL_ZZZI_H: |
| 17954 | case AArch64::SQDMULH_ZZZI_H: |
| 17955 | case AArch64::SQRDMULH_ZZZI_H: { |
| 17956 | // op: Zd |
| 17957 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17958 | Value |= (op & 0x1f); |
| 17959 | // op: Zn |
| 17960 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17961 | Value |= (op & 0x1f) << 5; |
| 17962 | // op: Zm |
| 17963 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17964 | Value |= (op & 0x7) << 16; |
| 17965 | // op: iop |
| 17966 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17967 | Value |= (op & 0x4) << 20; |
| 17968 | Value |= (op & 0x3) << 19; |
| 17969 | break; |
| 17970 | } |
| 17971 | case AArch64::SMULLB_ZZZI_S: |
| 17972 | case AArch64::SMULLT_ZZZI_S: |
| 17973 | case AArch64::SQDMULLB_ZZZI_S: |
| 17974 | case AArch64::SQDMULLT_ZZZI_S: |
| 17975 | case AArch64::UMULLB_ZZZI_S: |
| 17976 | case AArch64::UMULLT_ZZZI_S: { |
| 17977 | // op: Zd |
| 17978 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17979 | Value |= (op & 0x1f); |
| 17980 | // op: Zn |
| 17981 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 17982 | Value |= (op & 0x1f) << 5; |
| 17983 | // op: Zm |
| 17984 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 17985 | Value |= (op & 0x7) << 16; |
| 17986 | // op: iop |
| 17987 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 17988 | Value |= (op & 0x6) << 18; |
| 17989 | Value |= (op & 0x1) << 11; |
| 17990 | break; |
| 17991 | } |
| 17992 | case AArch64::FMUL_ZZZI_D: |
| 17993 | case AArch64::MUL_ZZZI_D: |
| 17994 | case AArch64::SQDMULH_ZZZI_D: |
| 17995 | case AArch64::SQRDMULH_ZZZI_D: { |
| 17996 | // op: Zd |
| 17997 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 17998 | Value |= (op & 0x1f); |
| 17999 | // op: Zn |
| 18000 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18001 | Value |= (op & 0x1f) << 5; |
| 18002 | // op: Zm |
| 18003 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18004 | Value |= (op & 0xf) << 16; |
| 18005 | // op: iop |
| 18006 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18007 | Value |= (op & 0x1) << 20; |
| 18008 | break; |
| 18009 | } |
| 18010 | case AArch64::SMULLB_ZZZI_D: |
| 18011 | case AArch64::SMULLT_ZZZI_D: |
| 18012 | case AArch64::SQDMULLB_ZZZI_D: |
| 18013 | case AArch64::SQDMULLT_ZZZI_D: |
| 18014 | case AArch64::UMULLB_ZZZI_D: |
| 18015 | case AArch64::UMULLT_ZZZI_D: { |
| 18016 | // op: Zd |
| 18017 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18018 | Value |= (op & 0x1f); |
| 18019 | // op: Zn |
| 18020 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18021 | Value |= (op & 0x1f) << 5; |
| 18022 | // op: Zm |
| 18023 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18024 | Value |= (op & 0xf) << 16; |
| 18025 | // op: iop |
| 18026 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18027 | Value |= (op & 0x2) << 19; |
| 18028 | Value |= (op & 0x1) << 11; |
| 18029 | break; |
| 18030 | } |
| 18031 | case AArch64::DUP_ZZI_H: { |
| 18032 | // op: Zd |
| 18033 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18034 | Value |= (op & 0x1f); |
| 18035 | // op: Zn |
| 18036 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18037 | Value |= (op & 0x1f) << 5; |
| 18038 | // op: idx |
| 18039 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18040 | Value |= (op & 0x18) << 19; |
| 18041 | Value |= (op & 0x7) << 18; |
| 18042 | break; |
| 18043 | } |
| 18044 | case AArch64::DUP_ZZI_Q: { |
| 18045 | // op: Zd |
| 18046 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18047 | Value |= (op & 0x1f); |
| 18048 | // op: Zn |
| 18049 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18050 | Value |= (op & 0x1f) << 5; |
| 18051 | // op: idx |
| 18052 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18053 | Value |= (op & 0x3) << 22; |
| 18054 | break; |
| 18055 | } |
| 18056 | case AArch64::DUP_ZZI_B: { |
| 18057 | // op: Zd |
| 18058 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18059 | Value |= (op & 0x1f); |
| 18060 | // op: Zn |
| 18061 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18062 | Value |= (op & 0x1f) << 5; |
| 18063 | // op: idx |
| 18064 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18065 | Value |= (op & 0x30) << 18; |
| 18066 | Value |= (op & 0xf) << 17; |
| 18067 | break; |
| 18068 | } |
| 18069 | case AArch64::DUP_ZZI_D: { |
| 18070 | // op: Zd |
| 18071 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18072 | Value |= (op & 0x1f); |
| 18073 | // op: Zn |
| 18074 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18075 | Value |= (op & 0x1f) << 5; |
| 18076 | // op: idx |
| 18077 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18078 | Value |= (op & 0x6) << 21; |
| 18079 | Value |= (op & 0x1) << 20; |
| 18080 | break; |
| 18081 | } |
| 18082 | case AArch64::DUP_ZZI_S: { |
| 18083 | // op: Zd |
| 18084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18085 | Value |= (op & 0x1f); |
| 18086 | // op: Zn |
| 18087 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18088 | Value |= (op & 0x1f) << 5; |
| 18089 | // op: idx |
| 18090 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18091 | Value |= (op & 0xc) << 20; |
| 18092 | Value |= (op & 0x3) << 19; |
| 18093 | break; |
| 18094 | } |
| 18095 | case AArch64::LSL_ZZI_H: |
| 18096 | case AArch64::SSHLLB_ZZI_S: |
| 18097 | case AArch64::SSHLLT_ZZI_S: |
| 18098 | case AArch64::USHLLB_ZZI_S: |
| 18099 | case AArch64::USHLLT_ZZI_S: { |
| 18100 | // op: Zd |
| 18101 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18102 | Value |= (op & 0x1f); |
| 18103 | // op: Zn |
| 18104 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18105 | Value |= (op & 0x1f) << 5; |
| 18106 | // op: imm |
| 18107 | op = getVecShiftL16OpValue(MI, OpIdx: 2, Fixups, STI); |
| 18108 | Value |= (op & 0xf) << 16; |
| 18109 | break; |
| 18110 | } |
| 18111 | case AArch64::LSL_ZZI_S: |
| 18112 | case AArch64::SSHLLB_ZZI_D: |
| 18113 | case AArch64::SSHLLT_ZZI_D: |
| 18114 | case AArch64::USHLLB_ZZI_D: |
| 18115 | case AArch64::USHLLT_ZZI_D: { |
| 18116 | // op: Zd |
| 18117 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18118 | Value |= (op & 0x1f); |
| 18119 | // op: Zn |
| 18120 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18121 | Value |= (op & 0x1f) << 5; |
| 18122 | // op: imm |
| 18123 | op = getVecShiftL32OpValue(MI, OpIdx: 2, Fixups, STI); |
| 18124 | Value |= (op & 0x1f) << 16; |
| 18125 | break; |
| 18126 | } |
| 18127 | case AArch64::LSL_ZZI_D: { |
| 18128 | // op: Zd |
| 18129 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18130 | Value |= (op & 0x1f); |
| 18131 | // op: Zn |
| 18132 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18133 | Value |= (op & 0x1f) << 5; |
| 18134 | // op: imm |
| 18135 | op = getVecShiftL64OpValue(MI, OpIdx: 2, Fixups, STI); |
| 18136 | Value |= (op & 0x20) << 17; |
| 18137 | Value |= (op & 0x1f) << 16; |
| 18138 | break; |
| 18139 | } |
| 18140 | case AArch64::LSL_ZZI_B: |
| 18141 | case AArch64::SSHLLB_ZZI_H: |
| 18142 | case AArch64::SSHLLT_ZZI_H: |
| 18143 | case AArch64::USHLLB_ZZI_H: |
| 18144 | case AArch64::USHLLT_ZZI_H: { |
| 18145 | // op: Zd |
| 18146 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18147 | Value |= (op & 0x1f); |
| 18148 | // op: Zn |
| 18149 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18150 | Value |= (op & 0x1f) << 5; |
| 18151 | // op: imm |
| 18152 | op = getVecShiftL8OpValue(MI, OpIdx: 2, Fixups, STI); |
| 18153 | Value |= (op & 0x7) << 16; |
| 18154 | break; |
| 18155 | } |
| 18156 | case AArch64::ASR_ZZI_H: |
| 18157 | case AArch64::LSR_ZZI_H: |
| 18158 | case AArch64::RSHRNB_ZZI_H: |
| 18159 | case AArch64::SHRNB_ZZI_H: |
| 18160 | case AArch64::SQRSHRNB_ZZI_H: |
| 18161 | case AArch64::SQRSHRUNB_ZZI_H: |
| 18162 | case AArch64::SQSHRNB_ZZI_H: |
| 18163 | case AArch64::SQSHRUNB_ZZI_H: |
| 18164 | case AArch64::UQRSHRNB_ZZI_H: |
| 18165 | case AArch64::UQSHRNB_ZZI_H: { |
| 18166 | // op: Zd |
| 18167 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18168 | Value |= (op & 0x1f); |
| 18169 | // op: Zn |
| 18170 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18171 | Value |= (op & 0x1f) << 5; |
| 18172 | // op: imm |
| 18173 | op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI); |
| 18174 | Value |= (op & 0xf) << 16; |
| 18175 | break; |
| 18176 | } |
| 18177 | case AArch64::ASR_ZZI_S: |
| 18178 | case AArch64::LSR_ZZI_S: |
| 18179 | case AArch64::RSHRNB_ZZI_S: |
| 18180 | case AArch64::SHRNB_ZZI_S: |
| 18181 | case AArch64::SQRSHRNB_ZZI_S: |
| 18182 | case AArch64::SQRSHRUNB_ZZI_S: |
| 18183 | case AArch64::SQSHRNB_ZZI_S: |
| 18184 | case AArch64::SQSHRUNB_ZZI_S: |
| 18185 | case AArch64::UQRSHRNB_ZZI_S: |
| 18186 | case AArch64::UQSHRNB_ZZI_S: { |
| 18187 | // op: Zd |
| 18188 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18189 | Value |= (op & 0x1f); |
| 18190 | // op: Zn |
| 18191 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18192 | Value |= (op & 0x1f) << 5; |
| 18193 | // op: imm |
| 18194 | op = getVecShiftR32OpValue(MI, OpIdx: 2, Fixups, STI); |
| 18195 | Value |= (op & 0x1f) << 16; |
| 18196 | break; |
| 18197 | } |
| 18198 | case AArch64::ASR_ZZI_D: |
| 18199 | case AArch64::LSR_ZZI_D: { |
| 18200 | // op: Zd |
| 18201 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18202 | Value |= (op & 0x1f); |
| 18203 | // op: Zn |
| 18204 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18205 | Value |= (op & 0x1f) << 5; |
| 18206 | // op: imm |
| 18207 | op = getVecShiftR64OpValue(MI, OpIdx: 2, Fixups, STI); |
| 18208 | Value |= (op & 0x20) << 17; |
| 18209 | Value |= (op & 0x1f) << 16; |
| 18210 | break; |
| 18211 | } |
| 18212 | case AArch64::ASR_ZZI_B: |
| 18213 | case AArch64::LSR_ZZI_B: |
| 18214 | case AArch64::RSHRNB_ZZI_B: |
| 18215 | case AArch64::SHRNB_ZZI_B: |
| 18216 | case AArch64::SQRSHRNB_ZZI_B: |
| 18217 | case AArch64::SQRSHRUNB_ZZI_B: |
| 18218 | case AArch64::SQSHRNB_ZZI_B: |
| 18219 | case AArch64::SQSHRUNB_ZZI_B: |
| 18220 | case AArch64::UQRSHRNB_ZZI_B: |
| 18221 | case AArch64::UQSHRNB_ZZI_B: { |
| 18222 | // op: Zd |
| 18223 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18224 | Value |= (op & 0x1f); |
| 18225 | // op: Zn |
| 18226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18227 | Value |= (op & 0x1f) << 5; |
| 18228 | // op: imm |
| 18229 | op = getVecShiftR8OpValue(MI, OpIdx: 2, Fixups, STI); |
| 18230 | Value |= (op & 0x7) << 16; |
| 18231 | break; |
| 18232 | } |
| 18233 | case AArch64::EXT_ZZI_B: { |
| 18234 | // op: Zd |
| 18235 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18236 | Value |= (op & 0x1f); |
| 18237 | // op: Zn |
| 18238 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18239 | Value |= (op & 0x1f) << 5; |
| 18240 | // op: imm8 |
| 18241 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18242 | Value |= (op & 0xf8) << 13; |
| 18243 | Value |= (op & 0x7) << 10; |
| 18244 | break; |
| 18245 | } |
| 18246 | case AArch64::DUPQ_ZZI_D: { |
| 18247 | // op: Zd |
| 18248 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18249 | Value |= (op & 0x1f); |
| 18250 | // op: Zn |
| 18251 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18252 | Value |= (op & 0x1f) << 5; |
| 18253 | // op: index |
| 18254 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18255 | Value |= (op & 0x1) << 20; |
| 18256 | break; |
| 18257 | } |
| 18258 | case AArch64::DUPQ_ZZI_S: { |
| 18259 | // op: Zd |
| 18260 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18261 | Value |= (op & 0x1f); |
| 18262 | // op: Zn |
| 18263 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18264 | Value |= (op & 0x1f) << 5; |
| 18265 | // op: index |
| 18266 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18267 | Value |= (op & 0x3) << 19; |
| 18268 | break; |
| 18269 | } |
| 18270 | case AArch64::DUPQ_ZZI_H: { |
| 18271 | // op: Zd |
| 18272 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18273 | Value |= (op & 0x1f); |
| 18274 | // op: Zn |
| 18275 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18276 | Value |= (op & 0x1f) << 5; |
| 18277 | // op: index |
| 18278 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18279 | Value |= (op & 0x7) << 18; |
| 18280 | break; |
| 18281 | } |
| 18282 | case AArch64::DUPQ_ZZI_B: { |
| 18283 | // op: Zd |
| 18284 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18285 | Value |= (op & 0x1f); |
| 18286 | // op: Zn |
| 18287 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18288 | Value |= (op & 0x1f) << 5; |
| 18289 | // op: index |
| 18290 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18291 | Value |= (op & 0xf) << 17; |
| 18292 | break; |
| 18293 | } |
| 18294 | case AArch64::LUTI6_ZTZ: |
| 18295 | case AArch64::SQXTNT_ZZ_B: |
| 18296 | case AArch64::SQXTNT_ZZ_H: |
| 18297 | case AArch64::SQXTNT_ZZ_S: |
| 18298 | case AArch64::SQXTUNT_ZZ_B: |
| 18299 | case AArch64::SQXTUNT_ZZ_H: |
| 18300 | case AArch64::SQXTUNT_ZZ_S: |
| 18301 | case AArch64::UQXTNT_ZZ_B: |
| 18302 | case AArch64::UQXTNT_ZZ_H: |
| 18303 | case AArch64::UQXTNT_ZZ_S: { |
| 18304 | // op: Zd |
| 18305 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18306 | Value |= (op & 0x1f); |
| 18307 | // op: Zn |
| 18308 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18309 | Value |= (op & 0x1f) << 5; |
| 18310 | break; |
| 18311 | } |
| 18312 | case AArch64::FCVTLT_ZPzZ_HtoS: |
| 18313 | case AArch64::FCVTLT_ZPzZ_StoD: { |
| 18314 | // op: Zd |
| 18315 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18316 | Value |= (op & 0x1f); |
| 18317 | // op: Zn |
| 18318 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18319 | Value |= (op & 0x1f) << 5; |
| 18320 | // op: Pg |
| 18321 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18322 | Value |= (op & 0x7) << 10; |
| 18323 | break; |
| 18324 | } |
| 18325 | case AArch64::HISTCNT_ZPzZZ_D: |
| 18326 | case AArch64::HISTCNT_ZPzZZ_S: { |
| 18327 | // op: Zd |
| 18328 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18329 | Value |= (op & 0x1f); |
| 18330 | // op: Zn |
| 18331 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18332 | Value |= (op & 0x1f) << 5; |
| 18333 | // op: Pg |
| 18334 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18335 | Value |= (op & 0x7) << 10; |
| 18336 | // op: Zm |
| 18337 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18338 | Value |= (op & 0x1f) << 16; |
| 18339 | break; |
| 18340 | } |
| 18341 | case AArch64::ADDHNT_ZZZ_B: |
| 18342 | case AArch64::ADDHNT_ZZZ_H: |
| 18343 | case AArch64::ADDHNT_ZZZ_S: |
| 18344 | case AArch64::EORBT_ZZZ_B: |
| 18345 | case AArch64::EORBT_ZZZ_D: |
| 18346 | case AArch64::EORBT_ZZZ_H: |
| 18347 | case AArch64::EORBT_ZZZ_S: |
| 18348 | case AArch64::EORTB_ZZZ_B: |
| 18349 | case AArch64::EORTB_ZZZ_D: |
| 18350 | case AArch64::EORTB_ZZZ_H: |
| 18351 | case AArch64::EORTB_ZZZ_S: |
| 18352 | case AArch64::RADDHNT_ZZZ_B: |
| 18353 | case AArch64::RADDHNT_ZZZ_H: |
| 18354 | case AArch64::RADDHNT_ZZZ_S: |
| 18355 | case AArch64::RSUBHNT_ZZZ_B: |
| 18356 | case AArch64::RSUBHNT_ZZZ_H: |
| 18357 | case AArch64::RSUBHNT_ZZZ_S: |
| 18358 | case AArch64::SUBHNT_ZZZ_B: |
| 18359 | case AArch64::SUBHNT_ZZZ_H: |
| 18360 | case AArch64::SUBHNT_ZZZ_S: { |
| 18361 | // op: Zd |
| 18362 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18363 | Value |= (op & 0x1f); |
| 18364 | // op: Zn |
| 18365 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18366 | Value |= (op & 0x1f) << 5; |
| 18367 | // op: Zm |
| 18368 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18369 | Value |= (op & 0x1f) << 16; |
| 18370 | break; |
| 18371 | } |
| 18372 | case AArch64::SLI_ZZI_H: { |
| 18373 | // op: Zd |
| 18374 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18375 | Value |= (op & 0x1f); |
| 18376 | // op: Zn |
| 18377 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18378 | Value |= (op & 0x1f) << 5; |
| 18379 | // op: imm |
| 18380 | op = getVecShiftL16OpValue(MI, OpIdx: 3, Fixups, STI); |
| 18381 | Value |= (op & 0xf) << 16; |
| 18382 | break; |
| 18383 | } |
| 18384 | case AArch64::SLI_ZZI_S: { |
| 18385 | // op: Zd |
| 18386 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18387 | Value |= (op & 0x1f); |
| 18388 | // op: Zn |
| 18389 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18390 | Value |= (op & 0x1f) << 5; |
| 18391 | // op: imm |
| 18392 | op = getVecShiftL32OpValue(MI, OpIdx: 3, Fixups, STI); |
| 18393 | Value |= (op & 0x1f) << 16; |
| 18394 | break; |
| 18395 | } |
| 18396 | case AArch64::SLI_ZZI_D: { |
| 18397 | // op: Zd |
| 18398 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18399 | Value |= (op & 0x1f); |
| 18400 | // op: Zn |
| 18401 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18402 | Value |= (op & 0x1f) << 5; |
| 18403 | // op: imm |
| 18404 | op = getVecShiftL64OpValue(MI, OpIdx: 3, Fixups, STI); |
| 18405 | Value |= (op & 0x20) << 17; |
| 18406 | Value |= (op & 0x1f) << 16; |
| 18407 | break; |
| 18408 | } |
| 18409 | case AArch64::SLI_ZZI_B: { |
| 18410 | // op: Zd |
| 18411 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18412 | Value |= (op & 0x1f); |
| 18413 | // op: Zn |
| 18414 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18415 | Value |= (op & 0x1f) << 5; |
| 18416 | // op: imm |
| 18417 | op = getVecShiftL8OpValue(MI, OpIdx: 3, Fixups, STI); |
| 18418 | Value |= (op & 0x7) << 16; |
| 18419 | break; |
| 18420 | } |
| 18421 | case AArch64::RSHRNT_ZZI_H: |
| 18422 | case AArch64::SHRNT_ZZI_H: |
| 18423 | case AArch64::SQRSHRNT_ZZI_H: |
| 18424 | case AArch64::SQRSHRUNT_ZZI_H: |
| 18425 | case AArch64::SQSHRNT_ZZI_H: |
| 18426 | case AArch64::SQSHRUNT_ZZI_H: |
| 18427 | case AArch64::SRI_ZZI_H: |
| 18428 | case AArch64::UQRSHRNT_ZZI_H: |
| 18429 | case AArch64::UQSHRNT_ZZI_H: { |
| 18430 | // op: Zd |
| 18431 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18432 | Value |= (op & 0x1f); |
| 18433 | // op: Zn |
| 18434 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18435 | Value |= (op & 0x1f) << 5; |
| 18436 | // op: imm |
| 18437 | op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI); |
| 18438 | Value |= (op & 0xf) << 16; |
| 18439 | break; |
| 18440 | } |
| 18441 | case AArch64::RSHRNT_ZZI_S: |
| 18442 | case AArch64::SHRNT_ZZI_S: |
| 18443 | case AArch64::SQRSHRNT_ZZI_S: |
| 18444 | case AArch64::SQRSHRUNT_ZZI_S: |
| 18445 | case AArch64::SQSHRNT_ZZI_S: |
| 18446 | case AArch64::SQSHRUNT_ZZI_S: |
| 18447 | case AArch64::SRI_ZZI_S: |
| 18448 | case AArch64::UQRSHRNT_ZZI_S: |
| 18449 | case AArch64::UQSHRNT_ZZI_S: { |
| 18450 | // op: Zd |
| 18451 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18452 | Value |= (op & 0x1f); |
| 18453 | // op: Zn |
| 18454 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18455 | Value |= (op & 0x1f) << 5; |
| 18456 | // op: imm |
| 18457 | op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI); |
| 18458 | Value |= (op & 0x1f) << 16; |
| 18459 | break; |
| 18460 | } |
| 18461 | case AArch64::SRI_ZZI_D: { |
| 18462 | // op: Zd |
| 18463 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18464 | Value |= (op & 0x1f); |
| 18465 | // op: Zn |
| 18466 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18467 | Value |= (op & 0x1f) << 5; |
| 18468 | // op: imm |
| 18469 | op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI); |
| 18470 | Value |= (op & 0x20) << 17; |
| 18471 | Value |= (op & 0x1f) << 16; |
| 18472 | break; |
| 18473 | } |
| 18474 | case AArch64::RSHRNT_ZZI_B: |
| 18475 | case AArch64::SHRNT_ZZI_B: |
| 18476 | case AArch64::SQRSHRNT_ZZI_B: |
| 18477 | case AArch64::SQRSHRUNT_ZZI_B: |
| 18478 | case AArch64::SQSHRNT_ZZI_B: |
| 18479 | case AArch64::SQSHRUNT_ZZI_B: |
| 18480 | case AArch64::SRI_ZZI_B: |
| 18481 | case AArch64::UQRSHRNT_ZZI_B: |
| 18482 | case AArch64::UQSHRNT_ZZI_B: { |
| 18483 | // op: Zd |
| 18484 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18485 | Value |= (op & 0x1f); |
| 18486 | // op: Zn |
| 18487 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18488 | Value |= (op & 0x1f) << 5; |
| 18489 | // op: imm |
| 18490 | op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI); |
| 18491 | Value |= (op & 0x7) << 16; |
| 18492 | break; |
| 18493 | } |
| 18494 | case AArch64::BFCVTNT_ZPmZ: |
| 18495 | case AArch64::BFCVTNT_ZPzZ_StoH: |
| 18496 | case AArch64::FCVTLT_ZPmZ_HtoS: |
| 18497 | case AArch64::FCVTLT_ZPmZ_StoD: |
| 18498 | case AArch64::FCVTNT_ZPmZ_DtoS: |
| 18499 | case AArch64::FCVTNT_ZPmZ_StoH: |
| 18500 | case AArch64::FCVTNT_ZPzZ_DtoS: |
| 18501 | case AArch64::FCVTNT_ZPzZ_StoH: |
| 18502 | case AArch64::FCVTXNT_ZPmZ_DtoS: |
| 18503 | case AArch64::FCVTXNT_ZPzZ_StoD: { |
| 18504 | // op: Zd |
| 18505 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18506 | Value |= (op & 0x1f); |
| 18507 | // op: Zn |
| 18508 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18509 | Value |= (op & 0x1f) << 5; |
| 18510 | // op: Pg |
| 18511 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18512 | Value |= (op & 0x7) << 10; |
| 18513 | break; |
| 18514 | } |
| 18515 | case AArch64::DUP_ZI_B: |
| 18516 | case AArch64::DUP_ZI_D: |
| 18517 | case AArch64::DUP_ZI_H: |
| 18518 | case AArch64::DUP_ZI_S: { |
| 18519 | // op: Zd |
| 18520 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18521 | Value |= (op & 0x1f); |
| 18522 | // op: imm |
| 18523 | op = getImm8OptLsl(MI, OpIdx: 1, Fixups, STI); |
| 18524 | Value |= (op & 0x1ff) << 5; |
| 18525 | break; |
| 18526 | } |
| 18527 | case AArch64::INDEX_II_B: |
| 18528 | case AArch64::INDEX_II_D: |
| 18529 | case AArch64::INDEX_II_H: |
| 18530 | case AArch64::INDEX_II_S: { |
| 18531 | // op: Zd |
| 18532 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18533 | Value |= (op & 0x1f); |
| 18534 | // op: imm5 |
| 18535 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18536 | Value |= (op & 0x1f) << 5; |
| 18537 | // op: imm5b |
| 18538 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18539 | Value |= (op & 0x1f) << 16; |
| 18540 | break; |
| 18541 | } |
| 18542 | case AArch64::FDUP_ZI_D: |
| 18543 | case AArch64::FDUP_ZI_H: |
| 18544 | case AArch64::FDUP_ZI_S: { |
| 18545 | // op: Zd |
| 18546 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18547 | Value |= (op & 0x1f); |
| 18548 | // op: imm8 |
| 18549 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18550 | Value |= (op & 0xff) << 5; |
| 18551 | break; |
| 18552 | } |
| 18553 | case AArch64::DUPM_ZI: { |
| 18554 | // op: Zd |
| 18555 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18556 | Value |= (op & 0x1f); |
| 18557 | // op: imms |
| 18558 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18559 | Value |= (op & 0x1fff) << 5; |
| 18560 | break; |
| 18561 | } |
| 18562 | case AArch64::FCMLA_ZPmZZ_D: |
| 18563 | case AArch64::FCMLA_ZPmZZ_H: |
| 18564 | case AArch64::FCMLA_ZPmZZ_S: { |
| 18565 | // op: Zda |
| 18566 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18567 | Value |= (op & 0x1f); |
| 18568 | // op: Pg |
| 18569 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 18570 | Value |= (op & 0x7) << 10; |
| 18571 | // op: Zn |
| 18572 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18573 | Value |= (op & 0x1f) << 5; |
| 18574 | // op: Zm |
| 18575 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 18576 | Value |= (op & 0x1f) << 16; |
| 18577 | // op: imm |
| 18578 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 18579 | Value |= (op & 0x3) << 13; |
| 18580 | break; |
| 18581 | } |
| 18582 | case AArch64::ADCLB_ZZZ_D: |
| 18583 | case AArch64::ADCLB_ZZZ_S: |
| 18584 | case AArch64::ADCLT_ZZZ_D: |
| 18585 | case AArch64::ADCLT_ZZZ_S: |
| 18586 | case AArch64::BFDOT_ZZZ: |
| 18587 | case AArch64::BFMLALB_ZZZ: |
| 18588 | case AArch64::BFMLALT_ZZZ: |
| 18589 | case AArch64::BFMLSLB_ZZZ_S: |
| 18590 | case AArch64::BFMLSLT_ZZZ_S: |
| 18591 | case AArch64::BFMMLA_ZZZ_H: |
| 18592 | case AArch64::BFMMLA_ZZZ_HtoS: |
| 18593 | case AArch64::FDOT_ZZZ_BtoH: |
| 18594 | case AArch64::FDOT_ZZZ_BtoS: |
| 18595 | case AArch64::FDOT_ZZZ_S: |
| 18596 | case AArch64::FMLALB_ZZZ: |
| 18597 | case AArch64::FMLALB_ZZZ_SHH: |
| 18598 | case AArch64::FMLALLBB_ZZZ: |
| 18599 | case AArch64::FMLALLBT_ZZZ: |
| 18600 | case AArch64::FMLALLTB_ZZZ: |
| 18601 | case AArch64::FMLALLTT_ZZZ: |
| 18602 | case AArch64::FMLALT_ZZZ: |
| 18603 | case AArch64::FMLALT_ZZZ_SHH: |
| 18604 | case AArch64::FMLLA_ZZZ_HtoS: |
| 18605 | case AArch64::FMLSLB_ZZZ_SHH: |
| 18606 | case AArch64::FMLSLT_ZZZ_SHH: |
| 18607 | case AArch64::FMMLA_ZZZ_BtoH: |
| 18608 | case AArch64::FMMLA_ZZZ_BtoS: |
| 18609 | case AArch64::FMMLA_ZZZ_D: |
| 18610 | case AArch64::FMMLA_ZZZ_H: |
| 18611 | case AArch64::FMMLA_ZZZ_S: |
| 18612 | case AArch64::MLA_CPA: |
| 18613 | case AArch64::SABALB_ZZZ_D: |
| 18614 | case AArch64::SABALB_ZZZ_H: |
| 18615 | case AArch64::SABALB_ZZZ_S: |
| 18616 | case AArch64::SABALT_ZZZ_D: |
| 18617 | case AArch64::SABALT_ZZZ_H: |
| 18618 | case AArch64::SABALT_ZZZ_S: |
| 18619 | case AArch64::SABAL_ZZZ_BtoH: |
| 18620 | case AArch64::SABAL_ZZZ_HtoS: |
| 18621 | case AArch64::SABAL_ZZZ_StoD: |
| 18622 | case AArch64::SABA_ZZZ_B: |
| 18623 | case AArch64::SABA_ZZZ_D: |
| 18624 | case AArch64::SABA_ZZZ_H: |
| 18625 | case AArch64::SABA_ZZZ_S: |
| 18626 | case AArch64::SBCLB_ZZZ_D: |
| 18627 | case AArch64::SBCLB_ZZZ_S: |
| 18628 | case AArch64::SBCLT_ZZZ_D: |
| 18629 | case AArch64::SBCLT_ZZZ_S: |
| 18630 | case AArch64::SDOT_ZZZ_BtoH: |
| 18631 | case AArch64::SDOT_ZZZ_BtoS: |
| 18632 | case AArch64::SDOT_ZZZ_HtoD: |
| 18633 | case AArch64::SDOT_ZZZ_HtoS: |
| 18634 | case AArch64::SMLALB_ZZZ_D: |
| 18635 | case AArch64::SMLALB_ZZZ_H: |
| 18636 | case AArch64::SMLALB_ZZZ_S: |
| 18637 | case AArch64::SMLALT_ZZZ_D: |
| 18638 | case AArch64::SMLALT_ZZZ_H: |
| 18639 | case AArch64::SMLALT_ZZZ_S: |
| 18640 | case AArch64::SMLSLB_ZZZ_D: |
| 18641 | case AArch64::SMLSLB_ZZZ_H: |
| 18642 | case AArch64::SMLSLB_ZZZ_S: |
| 18643 | case AArch64::SMLSLT_ZZZ_D: |
| 18644 | case AArch64::SMLSLT_ZZZ_H: |
| 18645 | case AArch64::SMLSLT_ZZZ_S: |
| 18646 | case AArch64::SMMLA_ZZZ: |
| 18647 | case AArch64::SQDMLALBT_ZZZ_D: |
| 18648 | case AArch64::SQDMLALBT_ZZZ_H: |
| 18649 | case AArch64::SQDMLALBT_ZZZ_S: |
| 18650 | case AArch64::SQDMLALB_ZZZ_D: |
| 18651 | case AArch64::SQDMLALB_ZZZ_H: |
| 18652 | case AArch64::SQDMLALB_ZZZ_S: |
| 18653 | case AArch64::SQDMLALT_ZZZ_D: |
| 18654 | case AArch64::SQDMLALT_ZZZ_H: |
| 18655 | case AArch64::SQDMLALT_ZZZ_S: |
| 18656 | case AArch64::SQDMLSLBT_ZZZ_D: |
| 18657 | case AArch64::SQDMLSLBT_ZZZ_H: |
| 18658 | case AArch64::SQDMLSLBT_ZZZ_S: |
| 18659 | case AArch64::SQDMLSLB_ZZZ_D: |
| 18660 | case AArch64::SQDMLSLB_ZZZ_H: |
| 18661 | case AArch64::SQDMLSLB_ZZZ_S: |
| 18662 | case AArch64::SQDMLSLT_ZZZ_D: |
| 18663 | case AArch64::SQDMLSLT_ZZZ_H: |
| 18664 | case AArch64::SQDMLSLT_ZZZ_S: |
| 18665 | case AArch64::SQRDMLAH_ZZZ_B: |
| 18666 | case AArch64::SQRDMLAH_ZZZ_D: |
| 18667 | case AArch64::SQRDMLAH_ZZZ_H: |
| 18668 | case AArch64::SQRDMLAH_ZZZ_S: |
| 18669 | case AArch64::SQRDMLSH_ZZZ_B: |
| 18670 | case AArch64::SQRDMLSH_ZZZ_D: |
| 18671 | case AArch64::SQRDMLSH_ZZZ_H: |
| 18672 | case AArch64::SQRDMLSH_ZZZ_S: |
| 18673 | case AArch64::UABALB_ZZZ_D: |
| 18674 | case AArch64::UABALB_ZZZ_H: |
| 18675 | case AArch64::UABALB_ZZZ_S: |
| 18676 | case AArch64::UABALT_ZZZ_D: |
| 18677 | case AArch64::UABALT_ZZZ_H: |
| 18678 | case AArch64::UABALT_ZZZ_S: |
| 18679 | case AArch64::UABAL_ZZZ_BtoH: |
| 18680 | case AArch64::UABAL_ZZZ_HtoS: |
| 18681 | case AArch64::UABAL_ZZZ_StoD: |
| 18682 | case AArch64::UABA_ZZZ_B: |
| 18683 | case AArch64::UABA_ZZZ_D: |
| 18684 | case AArch64::UABA_ZZZ_H: |
| 18685 | case AArch64::UABA_ZZZ_S: |
| 18686 | case AArch64::UDOT_ZZZ_BtoH: |
| 18687 | case AArch64::UDOT_ZZZ_BtoS: |
| 18688 | case AArch64::UDOT_ZZZ_HtoD: |
| 18689 | case AArch64::UDOT_ZZZ_HtoS: |
| 18690 | case AArch64::UMLALB_ZZZ_D: |
| 18691 | case AArch64::UMLALB_ZZZ_H: |
| 18692 | case AArch64::UMLALB_ZZZ_S: |
| 18693 | case AArch64::UMLALT_ZZZ_D: |
| 18694 | case AArch64::UMLALT_ZZZ_H: |
| 18695 | case AArch64::UMLALT_ZZZ_S: |
| 18696 | case AArch64::UMLSLB_ZZZ_D: |
| 18697 | case AArch64::UMLSLB_ZZZ_H: |
| 18698 | case AArch64::UMLSLB_ZZZ_S: |
| 18699 | case AArch64::UMLSLT_ZZZ_D: |
| 18700 | case AArch64::UMLSLT_ZZZ_H: |
| 18701 | case AArch64::UMLSLT_ZZZ_S: |
| 18702 | case AArch64::UMMLA_ZZZ: |
| 18703 | case AArch64::USDOT_ZZZ: |
| 18704 | case AArch64::USMMLA_ZZZ: { |
| 18705 | // op: Zda |
| 18706 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18707 | Value |= (op & 0x1f); |
| 18708 | // op: Zn |
| 18709 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18710 | Value |= (op & 0x1f) << 5; |
| 18711 | // op: Zm |
| 18712 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18713 | Value |= (op & 0x1f) << 16; |
| 18714 | break; |
| 18715 | } |
| 18716 | case AArch64::CDOT_ZZZ_D: |
| 18717 | case AArch64::CDOT_ZZZ_S: |
| 18718 | case AArch64::CMLA_ZZZ_B: |
| 18719 | case AArch64::CMLA_ZZZ_D: |
| 18720 | case AArch64::CMLA_ZZZ_H: |
| 18721 | case AArch64::CMLA_ZZZ_S: |
| 18722 | case AArch64::SQRDCMLAH_ZZZ_B: |
| 18723 | case AArch64::SQRDCMLAH_ZZZ_D: |
| 18724 | case AArch64::SQRDCMLAH_ZZZ_H: |
| 18725 | case AArch64::SQRDCMLAH_ZZZ_S: { |
| 18726 | // op: Zda |
| 18727 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18728 | Value |= (op & 0x1f); |
| 18729 | // op: Zn |
| 18730 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18731 | Value |= (op & 0x1f) << 5; |
| 18732 | // op: Zm |
| 18733 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18734 | Value |= (op & 0x1f) << 16; |
| 18735 | // op: rot |
| 18736 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 18737 | Value |= (op & 0x3) << 10; |
| 18738 | break; |
| 18739 | } |
| 18740 | case AArch64::SDOT_ZZZI_HtoS: |
| 18741 | case AArch64::UDOT_ZZZI_HtoS: { |
| 18742 | // op: Zda |
| 18743 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18744 | Value |= (op & 0x1f); |
| 18745 | // op: Zn |
| 18746 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18747 | Value |= (op & 0x1f) << 5; |
| 18748 | // op: Zm |
| 18749 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18750 | Value |= (op & 0x7) << 16; |
| 18751 | // op: i2 |
| 18752 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 18753 | Value |= (op & 0x3) << 19; |
| 18754 | break; |
| 18755 | } |
| 18756 | case AArch64::SUDOT_ZZZI: |
| 18757 | case AArch64::USDOT_ZZZI: { |
| 18758 | // op: Zda |
| 18759 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18760 | Value |= (op & 0x1f); |
| 18761 | // op: Zn |
| 18762 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18763 | Value |= (op & 0x1f) << 5; |
| 18764 | // op: Zm |
| 18765 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18766 | Value |= (op & 0x7) << 16; |
| 18767 | // op: idx |
| 18768 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 18769 | Value |= (op & 0x3) << 19; |
| 18770 | break; |
| 18771 | } |
| 18772 | case AArch64::FMLALB_ZZZI: |
| 18773 | case AArch64::FMLALLBB_ZZZI: |
| 18774 | case AArch64::FMLALLBT_ZZZI: |
| 18775 | case AArch64::FMLALLTB_ZZZI: |
| 18776 | case AArch64::FMLALLTT_ZZZI: |
| 18777 | case AArch64::FMLALT_ZZZI: { |
| 18778 | // op: Zda |
| 18779 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18780 | Value |= (op & 0x1f); |
| 18781 | // op: Zn |
| 18782 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18783 | Value |= (op & 0x1f) << 5; |
| 18784 | // op: Zm |
| 18785 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18786 | Value |= (op & 0x7) << 16; |
| 18787 | // op: imm4 |
| 18788 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 18789 | Value |= (op & 0xc) << 17; |
| 18790 | Value |= (op & 0x3) << 10; |
| 18791 | break; |
| 18792 | } |
| 18793 | case AArch64::BFDOT_ZZI: |
| 18794 | case AArch64::FDOT_ZZZI_BtoS: |
| 18795 | case AArch64::FDOT_ZZZI_S: |
| 18796 | case AArch64::FMLA_ZZZI_S: |
| 18797 | case AArch64::FMLS_ZZZI_S: |
| 18798 | case AArch64::MLA_ZZZI_S: |
| 18799 | case AArch64::MLS_ZZZI_S: |
| 18800 | case AArch64::SQRDMLAH_ZZZI_S: |
| 18801 | case AArch64::SQRDMLSH_ZZZI_S: { |
| 18802 | // op: Zda |
| 18803 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18804 | Value |= (op & 0x1f); |
| 18805 | // op: Zn |
| 18806 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18807 | Value |= (op & 0x1f) << 5; |
| 18808 | // op: Zm |
| 18809 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18810 | Value |= (op & 0x7) << 16; |
| 18811 | // op: iop |
| 18812 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 18813 | Value |= (op & 0x3) << 19; |
| 18814 | break; |
| 18815 | } |
| 18816 | case AArch64::BFMLA_ZZZI: |
| 18817 | case AArch64::BFMLS_ZZZI: |
| 18818 | case AArch64::FMLA_ZZZI_H: |
| 18819 | case AArch64::FMLS_ZZZI_H: |
| 18820 | case AArch64::MLA_ZZZI_H: |
| 18821 | case AArch64::MLS_ZZZI_H: |
| 18822 | case AArch64::SQRDMLAH_ZZZI_H: |
| 18823 | case AArch64::SQRDMLSH_ZZZI_H: { |
| 18824 | // op: Zda |
| 18825 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18826 | Value |= (op & 0x1f); |
| 18827 | // op: Zn |
| 18828 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18829 | Value |= (op & 0x1f) << 5; |
| 18830 | // op: Zm |
| 18831 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18832 | Value |= (op & 0x7) << 16; |
| 18833 | // op: iop |
| 18834 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 18835 | Value |= (op & 0x4) << 20; |
| 18836 | Value |= (op & 0x3) << 19; |
| 18837 | break; |
| 18838 | } |
| 18839 | case AArch64::BFMLALB_ZZZI: |
| 18840 | case AArch64::BFMLALT_ZZZI: |
| 18841 | case AArch64::BFMLSLB_ZZZI_S: |
| 18842 | case AArch64::BFMLSLT_ZZZI_S: |
| 18843 | case AArch64::FDOT_ZZZI_BtoH: |
| 18844 | case AArch64::FMLALB_ZZZI_SHH: |
| 18845 | case AArch64::FMLALT_ZZZI_SHH: |
| 18846 | case AArch64::FMLSLB_ZZZI_SHH: |
| 18847 | case AArch64::FMLSLT_ZZZI_SHH: |
| 18848 | case AArch64::SMLALB_ZZZI_S: |
| 18849 | case AArch64::SMLALT_ZZZI_S: |
| 18850 | case AArch64::SMLSLB_ZZZI_S: |
| 18851 | case AArch64::SMLSLT_ZZZI_S: |
| 18852 | case AArch64::SQDMLALB_ZZZI_S: |
| 18853 | case AArch64::SQDMLALT_ZZZI_S: |
| 18854 | case AArch64::SQDMLSLB_ZZZI_S: |
| 18855 | case AArch64::SQDMLSLT_ZZZI_S: |
| 18856 | case AArch64::UMLALB_ZZZI_S: |
| 18857 | case AArch64::UMLALT_ZZZI_S: |
| 18858 | case AArch64::UMLSLB_ZZZI_S: |
| 18859 | case AArch64::UMLSLT_ZZZI_S: { |
| 18860 | // op: Zda |
| 18861 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18862 | Value |= (op & 0x1f); |
| 18863 | // op: Zn |
| 18864 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18865 | Value |= (op & 0x1f) << 5; |
| 18866 | // op: Zm |
| 18867 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18868 | Value |= (op & 0x7) << 16; |
| 18869 | // op: iop |
| 18870 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 18871 | Value |= (op & 0x6) << 18; |
| 18872 | Value |= (op & 0x1) << 11; |
| 18873 | break; |
| 18874 | } |
| 18875 | case AArch64::FMLA_ZZZI_D: |
| 18876 | case AArch64::FMLS_ZZZI_D: |
| 18877 | case AArch64::MLA_ZZZI_D: |
| 18878 | case AArch64::MLS_ZZZI_D: |
| 18879 | case AArch64::SQRDMLAH_ZZZI_D: |
| 18880 | case AArch64::SQRDMLSH_ZZZI_D: { |
| 18881 | // op: Zda |
| 18882 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18883 | Value |= (op & 0x1f); |
| 18884 | // op: Zn |
| 18885 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18886 | Value |= (op & 0x1f) << 5; |
| 18887 | // op: Zm |
| 18888 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18889 | Value |= (op & 0xf) << 16; |
| 18890 | // op: iop |
| 18891 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 18892 | Value |= (op & 0x1) << 20; |
| 18893 | break; |
| 18894 | } |
| 18895 | case AArch64::SMLALB_ZZZI_D: |
| 18896 | case AArch64::SMLALT_ZZZI_D: |
| 18897 | case AArch64::SMLSLB_ZZZI_D: |
| 18898 | case AArch64::SMLSLT_ZZZI_D: |
| 18899 | case AArch64::SQDMLALB_ZZZI_D: |
| 18900 | case AArch64::SQDMLALT_ZZZI_D: |
| 18901 | case AArch64::SQDMLSLB_ZZZI_D: |
| 18902 | case AArch64::SQDMLSLT_ZZZI_D: |
| 18903 | case AArch64::UMLALB_ZZZI_D: |
| 18904 | case AArch64::UMLALT_ZZZI_D: |
| 18905 | case AArch64::UMLSLB_ZZZI_D: |
| 18906 | case AArch64::UMLSLT_ZZZI_D: { |
| 18907 | // op: Zda |
| 18908 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18909 | Value |= (op & 0x1f); |
| 18910 | // op: Zn |
| 18911 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18912 | Value |= (op & 0x1f) << 5; |
| 18913 | // op: Zm |
| 18914 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18915 | Value |= (op & 0xf) << 16; |
| 18916 | // op: iop |
| 18917 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 18918 | Value |= (op & 0x2) << 19; |
| 18919 | Value |= (op & 0x1) << 11; |
| 18920 | break; |
| 18921 | } |
| 18922 | case AArch64::FCMLA_ZZZI_H: { |
| 18923 | // op: Zda |
| 18924 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18925 | Value |= (op & 0x1f); |
| 18926 | // op: Zn |
| 18927 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18928 | Value |= (op & 0x1f) << 5; |
| 18929 | // op: imm |
| 18930 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 18931 | Value |= (op & 0x3) << 10; |
| 18932 | // op: Zm |
| 18933 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18934 | Value |= (op & 0x7) << 16; |
| 18935 | // op: iop |
| 18936 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 18937 | Value |= (op & 0x3) << 19; |
| 18938 | break; |
| 18939 | } |
| 18940 | case AArch64::FCMLA_ZZZI_S: { |
| 18941 | // op: Zda |
| 18942 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18943 | Value |= (op & 0x1f); |
| 18944 | // op: Zn |
| 18945 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18946 | Value |= (op & 0x1f) << 5; |
| 18947 | // op: imm |
| 18948 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 18949 | Value |= (op & 0x3) << 10; |
| 18950 | // op: Zm |
| 18951 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 18952 | Value |= (op & 0xf) << 16; |
| 18953 | // op: iop |
| 18954 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 18955 | Value |= (op & 0x1) << 20; |
| 18956 | break; |
| 18957 | } |
| 18958 | case AArch64::SRSRA_ZZI_H: |
| 18959 | case AArch64::SSRA_ZZI_H: |
| 18960 | case AArch64::URSRA_ZZI_H: |
| 18961 | case AArch64::USRA_ZZI_H: { |
| 18962 | // op: Zda |
| 18963 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18964 | Value |= (op & 0x1f); |
| 18965 | // op: Zn |
| 18966 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18967 | Value |= (op & 0x1f) << 5; |
| 18968 | // op: imm |
| 18969 | op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI); |
| 18970 | Value |= (op & 0xf) << 16; |
| 18971 | break; |
| 18972 | } |
| 18973 | case AArch64::SRSRA_ZZI_S: |
| 18974 | case AArch64::SSRA_ZZI_S: |
| 18975 | case AArch64::URSRA_ZZI_S: |
| 18976 | case AArch64::USRA_ZZI_S: { |
| 18977 | // op: Zda |
| 18978 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18979 | Value |= (op & 0x1f); |
| 18980 | // op: Zn |
| 18981 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18982 | Value |= (op & 0x1f) << 5; |
| 18983 | // op: imm |
| 18984 | op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI); |
| 18985 | Value |= (op & 0x1f) << 16; |
| 18986 | break; |
| 18987 | } |
| 18988 | case AArch64::SRSRA_ZZI_D: |
| 18989 | case AArch64::SSRA_ZZI_D: |
| 18990 | case AArch64::URSRA_ZZI_D: |
| 18991 | case AArch64::USRA_ZZI_D: { |
| 18992 | // op: Zda |
| 18993 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 18994 | Value |= (op & 0x1f); |
| 18995 | // op: Zn |
| 18996 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 18997 | Value |= (op & 0x1f) << 5; |
| 18998 | // op: imm |
| 18999 | op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI); |
| 19000 | Value |= (op & 0x20) << 17; |
| 19001 | Value |= (op & 0x1f) << 16; |
| 19002 | break; |
| 19003 | } |
| 19004 | case AArch64::SRSRA_ZZI_B: |
| 19005 | case AArch64::SSRA_ZZI_B: |
| 19006 | case AArch64::URSRA_ZZI_B: |
| 19007 | case AArch64::USRA_ZZI_B: { |
| 19008 | // op: Zda |
| 19009 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19010 | Value |= (op & 0x1f); |
| 19011 | // op: Zn |
| 19012 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19013 | Value |= (op & 0x1f) << 5; |
| 19014 | // op: imm |
| 19015 | op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI); |
| 19016 | Value |= (op & 0x7) << 16; |
| 19017 | break; |
| 19018 | } |
| 19019 | case AArch64::SDOT_ZZZI_HtoD: |
| 19020 | case AArch64::UDOT_ZZZI_HtoD: { |
| 19021 | // op: Zda |
| 19022 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19023 | Value |= (op & 0x1f); |
| 19024 | // op: Zn |
| 19025 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19026 | Value |= (op & 0x1f) << 5; |
| 19027 | // op: iop |
| 19028 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 19029 | Value |= (op & 0x1) << 20; |
| 19030 | // op: Zm |
| 19031 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19032 | Value |= (op & 0xf) << 16; |
| 19033 | break; |
| 19034 | } |
| 19035 | case AArch64::SDOT_ZZZI_BtoS: |
| 19036 | case AArch64::UDOT_ZZZI_BtoS: { |
| 19037 | // op: Zda |
| 19038 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19039 | Value |= (op & 0x1f); |
| 19040 | // op: Zn |
| 19041 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19042 | Value |= (op & 0x1f) << 5; |
| 19043 | // op: iop |
| 19044 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 19045 | Value |= (op & 0x3) << 19; |
| 19046 | // op: Zm |
| 19047 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19048 | Value |= (op & 0x7) << 16; |
| 19049 | break; |
| 19050 | } |
| 19051 | case AArch64::SDOT_ZZZI_BtoH: |
| 19052 | case AArch64::UDOT_ZZZI_BtoH: { |
| 19053 | // op: Zda |
| 19054 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19055 | Value |= (op & 0x1f); |
| 19056 | // op: Zn |
| 19057 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19058 | Value |= (op & 0x1f) << 5; |
| 19059 | // op: iop |
| 19060 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 19061 | Value |= (op & 0x4) << 20; |
| 19062 | Value |= (op & 0x3) << 19; |
| 19063 | // op: Zm |
| 19064 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19065 | Value |= (op & 0x7) << 16; |
| 19066 | break; |
| 19067 | } |
| 19068 | case AArch64::CDOT_ZZZI_D: |
| 19069 | case AArch64::CMLA_ZZZI_S: |
| 19070 | case AArch64::SQRDCMLAH_ZZZI_S: { |
| 19071 | // op: Zda |
| 19072 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19073 | Value |= (op & 0x1f); |
| 19074 | // op: Zn |
| 19075 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19076 | Value |= (op & 0x1f) << 5; |
| 19077 | // op: rot |
| 19078 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 19079 | Value |= (op & 0x3) << 10; |
| 19080 | // op: iop |
| 19081 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 19082 | Value |= (op & 0x1) << 20; |
| 19083 | // op: Zm |
| 19084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19085 | Value |= (op & 0xf) << 16; |
| 19086 | break; |
| 19087 | } |
| 19088 | case AArch64::CDOT_ZZZI_S: |
| 19089 | case AArch64::CMLA_ZZZI_H: |
| 19090 | case AArch64::SQRDCMLAH_ZZZI_H: { |
| 19091 | // op: Zda |
| 19092 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19093 | Value |= (op & 0x1f); |
| 19094 | // op: Zn |
| 19095 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19096 | Value |= (op & 0x1f) << 5; |
| 19097 | // op: rot |
| 19098 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 19099 | Value |= (op & 0x3) << 10; |
| 19100 | // op: iop |
| 19101 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 19102 | Value |= (op & 0x3) << 19; |
| 19103 | // op: Zm |
| 19104 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19105 | Value |= (op & 0x7) << 16; |
| 19106 | break; |
| 19107 | } |
| 19108 | case AArch64::AESIMC_ZZ_B: |
| 19109 | case AArch64::AESMC_ZZ_B: { |
| 19110 | // op: Zdn |
| 19111 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19112 | Value |= (op & 0x1f); |
| 19113 | break; |
| 19114 | } |
| 19115 | case AArch64::BCAX_ZZZZ: |
| 19116 | case AArch64::BSL1N_ZZZZ: |
| 19117 | case AArch64::BSL2N_ZZZZ: |
| 19118 | case AArch64::BSL_ZZZZ: |
| 19119 | case AArch64::EOR3_ZZZZ: |
| 19120 | case AArch64::NBSL_ZZZZ: { |
| 19121 | // op: Zdn |
| 19122 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19123 | Value |= (op & 0x1f); |
| 19124 | // op: Zk |
| 19125 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19126 | Value |= (op & 0x1f) << 5; |
| 19127 | // op: Zm |
| 19128 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19129 | Value |= (op & 0x1f) << 16; |
| 19130 | break; |
| 19131 | } |
| 19132 | case AArch64::MAD_CPA: { |
| 19133 | // op: Zdn |
| 19134 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19135 | Value |= (op & 0x1f); |
| 19136 | // op: Zm |
| 19137 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19138 | Value |= (op & 0x1f) << 16; |
| 19139 | // op: Za |
| 19140 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19141 | Value |= (op & 0x1f) << 5; |
| 19142 | break; |
| 19143 | } |
| 19144 | case AArch64::AESD_ZZZ_B: |
| 19145 | case AArch64::AESE_ZZZ_B: |
| 19146 | case AArch64::SM4E_ZZZ_S: { |
| 19147 | // op: Zdn |
| 19148 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19149 | Value |= (op & 0x1f); |
| 19150 | // op: Zm |
| 19151 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19152 | Value |= (op & 0x1f) << 5; |
| 19153 | break; |
| 19154 | } |
| 19155 | case AArch64::XAR_ZZZI_H: { |
| 19156 | // op: Zdn |
| 19157 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19158 | Value |= (op & 0x1f); |
| 19159 | // op: Zm |
| 19160 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19161 | Value |= (op & 0x1f) << 5; |
| 19162 | // op: imm |
| 19163 | op = getVecShiftR16OpValue(MI, OpIdx: 3, Fixups, STI); |
| 19164 | Value |= (op & 0xf) << 16; |
| 19165 | break; |
| 19166 | } |
| 19167 | case AArch64::XAR_ZZZI_S: { |
| 19168 | // op: Zdn |
| 19169 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19170 | Value |= (op & 0x1f); |
| 19171 | // op: Zm |
| 19172 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19173 | Value |= (op & 0x1f) << 5; |
| 19174 | // op: imm |
| 19175 | op = getVecShiftR32OpValue(MI, OpIdx: 3, Fixups, STI); |
| 19176 | Value |= (op & 0x1f) << 16; |
| 19177 | break; |
| 19178 | } |
| 19179 | case AArch64::XAR_ZZZI_D: { |
| 19180 | // op: Zdn |
| 19181 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19182 | Value |= (op & 0x1f); |
| 19183 | // op: Zm |
| 19184 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19185 | Value |= (op & 0x1f) << 5; |
| 19186 | // op: imm |
| 19187 | op = getVecShiftR64OpValue(MI, OpIdx: 3, Fixups, STI); |
| 19188 | Value |= (op & 0x20) << 17; |
| 19189 | Value |= (op & 0x1f) << 16; |
| 19190 | break; |
| 19191 | } |
| 19192 | case AArch64::XAR_ZZZI_B: { |
| 19193 | // op: Zdn |
| 19194 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19195 | Value |= (op & 0x1f); |
| 19196 | // op: Zm |
| 19197 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19198 | Value |= (op & 0x1f) << 5; |
| 19199 | // op: imm |
| 19200 | op = getVecShiftR8OpValue(MI, OpIdx: 3, Fixups, STI); |
| 19201 | Value |= (op & 0x7) << 16; |
| 19202 | break; |
| 19203 | } |
| 19204 | case AArch64::FTMAD_ZZI_D: |
| 19205 | case AArch64::FTMAD_ZZI_H: |
| 19206 | case AArch64::FTMAD_ZZI_S: { |
| 19207 | // op: Zdn |
| 19208 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19209 | Value |= (op & 0x1f); |
| 19210 | // op: Zm |
| 19211 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19212 | Value |= (op & 0x1f) << 5; |
| 19213 | // op: imm3 |
| 19214 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19215 | Value |= (op & 0x7) << 16; |
| 19216 | break; |
| 19217 | } |
| 19218 | case AArch64::EXTQ_ZZI: { |
| 19219 | // op: Zdn |
| 19220 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19221 | Value |= (op & 0x1f); |
| 19222 | // op: Zm |
| 19223 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19224 | Value |= (op & 0x1f) << 5; |
| 19225 | // op: imm4 |
| 19226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19227 | Value |= (op & 0xf) << 16; |
| 19228 | break; |
| 19229 | } |
| 19230 | case AArch64::EXT_ZZI: { |
| 19231 | // op: Zdn |
| 19232 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19233 | Value |= (op & 0x1f); |
| 19234 | // op: Zm |
| 19235 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19236 | Value |= (op & 0x1f) << 5; |
| 19237 | // op: imm8 |
| 19238 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19239 | Value |= (op & 0xf8) << 13; |
| 19240 | Value |= (op & 0x7) << 10; |
| 19241 | break; |
| 19242 | } |
| 19243 | case AArch64::CADD_ZZI_B: |
| 19244 | case AArch64::CADD_ZZI_D: |
| 19245 | case AArch64::CADD_ZZI_H: |
| 19246 | case AArch64::CADD_ZZI_S: |
| 19247 | case AArch64::SQCADD_ZZI_B: |
| 19248 | case AArch64::SQCADD_ZZI_D: |
| 19249 | case AArch64::SQCADD_ZZI_H: |
| 19250 | case AArch64::SQCADD_ZZI_S: { |
| 19251 | // op: Zdn |
| 19252 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19253 | Value |= (op & 0x1f); |
| 19254 | // op: Zm |
| 19255 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19256 | Value |= (op & 0x1f) << 5; |
| 19257 | // op: rot |
| 19258 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19259 | Value |= (op & 0x1) << 10; |
| 19260 | break; |
| 19261 | } |
| 19262 | case AArch64::FCADD_ZPmZ_D: |
| 19263 | case AArch64::FCADD_ZPmZ_H: |
| 19264 | case AArch64::FCADD_ZPmZ_S: { |
| 19265 | // op: Zdn |
| 19266 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19267 | Value |= (op & 0x1f); |
| 19268 | // op: Zm |
| 19269 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19270 | Value |= (op & 0x1f) << 5; |
| 19271 | // op: Pg |
| 19272 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 19273 | Value |= (op & 0x7) << 10; |
| 19274 | // op: imm |
| 19275 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 19276 | Value |= (op & 0x1) << 16; |
| 19277 | break; |
| 19278 | } |
| 19279 | case AArch64::ADD_ZI_B: |
| 19280 | case AArch64::ADD_ZI_D: |
| 19281 | case AArch64::ADD_ZI_H: |
| 19282 | case AArch64::ADD_ZI_S: |
| 19283 | case AArch64::SQADD_ZI_B: |
| 19284 | case AArch64::SQADD_ZI_D: |
| 19285 | case AArch64::SQADD_ZI_H: |
| 19286 | case AArch64::SQADD_ZI_S: |
| 19287 | case AArch64::SQSUB_ZI_B: |
| 19288 | case AArch64::SQSUB_ZI_D: |
| 19289 | case AArch64::SQSUB_ZI_H: |
| 19290 | case AArch64::SQSUB_ZI_S: |
| 19291 | case AArch64::SUBR_ZI_B: |
| 19292 | case AArch64::SUBR_ZI_D: |
| 19293 | case AArch64::SUBR_ZI_H: |
| 19294 | case AArch64::SUBR_ZI_S: |
| 19295 | case AArch64::SUB_ZI_B: |
| 19296 | case AArch64::SUB_ZI_D: |
| 19297 | case AArch64::SUB_ZI_H: |
| 19298 | case AArch64::SUB_ZI_S: |
| 19299 | case AArch64::UQADD_ZI_B: |
| 19300 | case AArch64::UQADD_ZI_D: |
| 19301 | case AArch64::UQADD_ZI_H: |
| 19302 | case AArch64::UQADD_ZI_S: |
| 19303 | case AArch64::UQSUB_ZI_B: |
| 19304 | case AArch64::UQSUB_ZI_D: |
| 19305 | case AArch64::UQSUB_ZI_H: |
| 19306 | case AArch64::UQSUB_ZI_S: { |
| 19307 | // op: Zdn |
| 19308 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19309 | Value |= (op & 0x1f); |
| 19310 | // op: imm |
| 19311 | op = getImm8OptLsl(MI, OpIdx: 2, Fixups, STI); |
| 19312 | Value |= (op & 0x1ff) << 5; |
| 19313 | break; |
| 19314 | } |
| 19315 | case AArch64::MUL_ZI_B: |
| 19316 | case AArch64::MUL_ZI_D: |
| 19317 | case AArch64::MUL_ZI_H: |
| 19318 | case AArch64::MUL_ZI_S: |
| 19319 | case AArch64::SMAX_ZI_B: |
| 19320 | case AArch64::SMAX_ZI_D: |
| 19321 | case AArch64::SMAX_ZI_H: |
| 19322 | case AArch64::SMAX_ZI_S: |
| 19323 | case AArch64::SMIN_ZI_B: |
| 19324 | case AArch64::SMIN_ZI_D: |
| 19325 | case AArch64::SMIN_ZI_H: |
| 19326 | case AArch64::SMIN_ZI_S: |
| 19327 | case AArch64::UMAX_ZI_B: |
| 19328 | case AArch64::UMAX_ZI_D: |
| 19329 | case AArch64::UMAX_ZI_H: |
| 19330 | case AArch64::UMAX_ZI_S: |
| 19331 | case AArch64::UMIN_ZI_B: |
| 19332 | case AArch64::UMIN_ZI_D: |
| 19333 | case AArch64::UMIN_ZI_H: |
| 19334 | case AArch64::UMIN_ZI_S: { |
| 19335 | // op: Zdn |
| 19336 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19337 | Value |= (op & 0x1f); |
| 19338 | // op: imm |
| 19339 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19340 | Value |= (op & 0xff) << 5; |
| 19341 | break; |
| 19342 | } |
| 19343 | case AArch64::AND_ZI: |
| 19344 | case AArch64::EOR_ZI: |
| 19345 | case AArch64::ORR_ZI: { |
| 19346 | // op: Zdn |
| 19347 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19348 | Value |= (op & 0x1f); |
| 19349 | // op: imms13 |
| 19350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19351 | Value |= (op & 0x1fff) << 5; |
| 19352 | break; |
| 19353 | } |
| 19354 | case AArch64::DECD_ZPiI: |
| 19355 | case AArch64::DECH_ZPiI: |
| 19356 | case AArch64::DECW_ZPiI: |
| 19357 | case AArch64::INCD_ZPiI: |
| 19358 | case AArch64::INCH_ZPiI: |
| 19359 | case AArch64::INCW_ZPiI: |
| 19360 | case AArch64::SQDECD_ZPiI: |
| 19361 | case AArch64::SQDECH_ZPiI: |
| 19362 | case AArch64::SQDECW_ZPiI: |
| 19363 | case AArch64::SQINCD_ZPiI: |
| 19364 | case AArch64::SQINCH_ZPiI: |
| 19365 | case AArch64::SQINCW_ZPiI: |
| 19366 | case AArch64::UQDECD_ZPiI: |
| 19367 | case AArch64::UQDECH_ZPiI: |
| 19368 | case AArch64::UQDECW_ZPiI: |
| 19369 | case AArch64::UQINCD_ZPiI: |
| 19370 | case AArch64::UQINCH_ZPiI: |
| 19371 | case AArch64::UQINCW_ZPiI: { |
| 19372 | // op: Zdn |
| 19373 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19374 | Value |= (op & 0x1f); |
| 19375 | // op: pattern |
| 19376 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19377 | Value |= (op & 0x1f) << 5; |
| 19378 | // op: imm4 |
| 19379 | op = getSVEIncDecImm(MI, OpIdx: 3, Fixups, STI); |
| 19380 | Value |= (op & 0xf) << 16; |
| 19381 | break; |
| 19382 | } |
| 19383 | case AArch64::BFMAXNM_VG2_2Z2Z_H: |
| 19384 | case AArch64::BFMAX_VG2_2Z2Z_H: |
| 19385 | case AArch64::BFMINNM_VG2_2Z2Z_H: |
| 19386 | case AArch64::BFMIN_VG2_2Z2Z_H: |
| 19387 | case AArch64::BFSCALE_2Z2Z: |
| 19388 | case AArch64::FAMAX_2Z2Z_D: |
| 19389 | case AArch64::FAMAX_2Z2Z_H: |
| 19390 | case AArch64::FAMAX_2Z2Z_S: |
| 19391 | case AArch64::FAMIN_2Z2Z_D: |
| 19392 | case AArch64::FAMIN_2Z2Z_H: |
| 19393 | case AArch64::FAMIN_2Z2Z_S: |
| 19394 | case AArch64::FMAXNM_VG2_2Z2Z_D: |
| 19395 | case AArch64::FMAXNM_VG2_2Z2Z_H: |
| 19396 | case AArch64::FMAXNM_VG2_2Z2Z_S: |
| 19397 | case AArch64::FMAX_VG2_2Z2Z_D: |
| 19398 | case AArch64::FMAX_VG2_2Z2Z_H: |
| 19399 | case AArch64::FMAX_VG2_2Z2Z_S: |
| 19400 | case AArch64::FMINNM_VG2_2Z2Z_D: |
| 19401 | case AArch64::FMINNM_VG2_2Z2Z_H: |
| 19402 | case AArch64::FMINNM_VG2_2Z2Z_S: |
| 19403 | case AArch64::FMIN_VG2_2Z2Z_D: |
| 19404 | case AArch64::FMIN_VG2_2Z2Z_H: |
| 19405 | case AArch64::FMIN_VG2_2Z2Z_S: |
| 19406 | case AArch64::FSCALE_2Z2Z_D: |
| 19407 | case AArch64::FSCALE_2Z2Z_H: |
| 19408 | case AArch64::FSCALE_2Z2Z_S: |
| 19409 | case AArch64::SMAX_VG2_2Z2Z_B: |
| 19410 | case AArch64::SMAX_VG2_2Z2Z_D: |
| 19411 | case AArch64::SMAX_VG2_2Z2Z_H: |
| 19412 | case AArch64::SMAX_VG2_2Z2Z_S: |
| 19413 | case AArch64::SMIN_VG2_2Z2Z_B: |
| 19414 | case AArch64::SMIN_VG2_2Z2Z_D: |
| 19415 | case AArch64::SMIN_VG2_2Z2Z_H: |
| 19416 | case AArch64::SMIN_VG2_2Z2Z_S: |
| 19417 | case AArch64::SQDMULH_VG2_2Z2Z_B: |
| 19418 | case AArch64::SQDMULH_VG2_2Z2Z_D: |
| 19419 | case AArch64::SQDMULH_VG2_2Z2Z_H: |
| 19420 | case AArch64::SQDMULH_VG2_2Z2Z_S: |
| 19421 | case AArch64::SRSHL_VG2_2Z2Z_B: |
| 19422 | case AArch64::SRSHL_VG2_2Z2Z_D: |
| 19423 | case AArch64::SRSHL_VG2_2Z2Z_H: |
| 19424 | case AArch64::SRSHL_VG2_2Z2Z_S: |
| 19425 | case AArch64::UMAX_VG2_2Z2Z_B: |
| 19426 | case AArch64::UMAX_VG2_2Z2Z_D: |
| 19427 | case AArch64::UMAX_VG2_2Z2Z_H: |
| 19428 | case AArch64::UMAX_VG2_2Z2Z_S: |
| 19429 | case AArch64::UMIN_VG2_2Z2Z_B: |
| 19430 | case AArch64::UMIN_VG2_2Z2Z_D: |
| 19431 | case AArch64::UMIN_VG2_2Z2Z_H: |
| 19432 | case AArch64::UMIN_VG2_2Z2Z_S: |
| 19433 | case AArch64::URSHL_VG2_2Z2Z_B: |
| 19434 | case AArch64::URSHL_VG2_2Z2Z_D: |
| 19435 | case AArch64::URSHL_VG2_2Z2Z_H: |
| 19436 | case AArch64::URSHL_VG2_2Z2Z_S: { |
| 19437 | // op: Zm |
| 19438 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI); |
| 19439 | Value |= (op & 0xf) << 17; |
| 19440 | // op: Zdn |
| 19441 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 19442 | Value |= (op & 0xf) << 1; |
| 19443 | break; |
| 19444 | } |
| 19445 | case AArch64::FMLALL_VG2_M2Z2Z_BtoS: |
| 19446 | case AArch64::SMLALL_VG2_M2Z2Z_BtoS: |
| 19447 | case AArch64::SMLALL_VG2_M2Z2Z_HtoD: |
| 19448 | case AArch64::SMLSLL_VG2_M2Z2Z_BtoS: |
| 19449 | case AArch64::SMLSLL_VG2_M2Z2Z_HtoD: |
| 19450 | case AArch64::UMLALL_VG2_M2Z2Z_BtoS: |
| 19451 | case AArch64::UMLALL_VG2_M2Z2Z_HtoD: |
| 19452 | case AArch64::UMLSLL_VG2_M2Z2Z_BtoS: |
| 19453 | case AArch64::UMLSLL_VG2_M2Z2Z_HtoD: |
| 19454 | case AArch64::USMLALL_VG2_M2Z2Z_BtoS: { |
| 19455 | // op: Zm |
| 19456 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 5, Fixups, STI); |
| 19457 | Value |= (op & 0xf) << 17; |
| 19458 | // op: Rv |
| 19459 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 19460 | Value |= (op & 0x3) << 13; |
| 19461 | // op: Zn |
| 19462 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 19463 | Value |= (op & 0xf) << 6; |
| 19464 | // op: imm |
| 19465 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19466 | Value |= (op & 0x1); |
| 19467 | break; |
| 19468 | } |
| 19469 | case AArch64::ADD_VG2_M2Z2Z_D: |
| 19470 | case AArch64::ADD_VG2_M2Z2Z_S: |
| 19471 | case AArch64::BFDOT_VG2_M2Z2Z_HtoS: |
| 19472 | case AArch64::BFMLA_VG2_M2Z2Z: |
| 19473 | case AArch64::BFMLS_VG2_M2Z2Z: |
| 19474 | case AArch64::FDOT_VG2_M2Z2Z_BtoH: |
| 19475 | case AArch64::FDOT_VG2_M2Z2Z_BtoS: |
| 19476 | case AArch64::FDOT_VG2_M2Z2Z_HtoS: |
| 19477 | case AArch64::FMLA_VG2_M2Z2Z_D: |
| 19478 | case AArch64::FMLA_VG2_M2Z2Z_H: |
| 19479 | case AArch64::FMLA_VG2_M2Z2Z_S: |
| 19480 | case AArch64::FMLS_VG2_M2Z2Z_D: |
| 19481 | case AArch64::FMLS_VG2_M2Z2Z_H: |
| 19482 | case AArch64::FMLS_VG2_M2Z2Z_S: |
| 19483 | case AArch64::SDOT_VG2_M2Z2Z_BtoS: |
| 19484 | case AArch64::SDOT_VG2_M2Z2Z_HtoD: |
| 19485 | case AArch64::SDOT_VG2_M2Z2Z_HtoS: |
| 19486 | case AArch64::SUB_VG2_M2Z2Z_D: |
| 19487 | case AArch64::SUB_VG2_M2Z2Z_S: |
| 19488 | case AArch64::UDOT_VG2_M2Z2Z_BtoS: |
| 19489 | case AArch64::UDOT_VG2_M2Z2Z_HtoD: |
| 19490 | case AArch64::UDOT_VG2_M2Z2Z_HtoS: |
| 19491 | case AArch64::USDOT_VG2_M2Z2Z_BToS: { |
| 19492 | // op: Zm |
| 19493 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 5, Fixups, STI); |
| 19494 | Value |= (op & 0xf) << 17; |
| 19495 | // op: Zn |
| 19496 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 19497 | Value |= (op & 0xf) << 6; |
| 19498 | // op: Rv |
| 19499 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 19500 | Value |= (op & 0x3) << 13; |
| 19501 | // op: imm3 |
| 19502 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19503 | Value |= (op & 0x7); |
| 19504 | break; |
| 19505 | } |
| 19506 | case AArch64::BFMAXNM_VG4_4Z2Z_H: |
| 19507 | case AArch64::BFMAX_VG4_4Z2Z_H: |
| 19508 | case AArch64::BFMINNM_VG4_4Z2Z_H: |
| 19509 | case AArch64::BFMIN_VG4_4Z2Z_H: |
| 19510 | case AArch64::BFSCALE_4Z4Z: |
| 19511 | case AArch64::FAMAX_4Z4Z_D: |
| 19512 | case AArch64::FAMAX_4Z4Z_H: |
| 19513 | case AArch64::FAMAX_4Z4Z_S: |
| 19514 | case AArch64::FAMIN_4Z4Z_D: |
| 19515 | case AArch64::FAMIN_4Z4Z_H: |
| 19516 | case AArch64::FAMIN_4Z4Z_S: |
| 19517 | case AArch64::FMAXNM_VG4_4Z4Z_D: |
| 19518 | case AArch64::FMAXNM_VG4_4Z4Z_H: |
| 19519 | case AArch64::FMAXNM_VG4_4Z4Z_S: |
| 19520 | case AArch64::FMAX_VG4_4Z4Z_D: |
| 19521 | case AArch64::FMAX_VG4_4Z4Z_H: |
| 19522 | case AArch64::FMAX_VG4_4Z4Z_S: |
| 19523 | case AArch64::FMINNM_VG4_4Z4Z_D: |
| 19524 | case AArch64::FMINNM_VG4_4Z4Z_H: |
| 19525 | case AArch64::FMINNM_VG4_4Z4Z_S: |
| 19526 | case AArch64::FMIN_VG4_4Z4Z_D: |
| 19527 | case AArch64::FMIN_VG4_4Z4Z_H: |
| 19528 | case AArch64::FMIN_VG4_4Z4Z_S: |
| 19529 | case AArch64::FSCALE_4Z4Z_D: |
| 19530 | case AArch64::FSCALE_4Z4Z_H: |
| 19531 | case AArch64::FSCALE_4Z4Z_S: |
| 19532 | case AArch64::SMAX_VG4_4Z4Z_B: |
| 19533 | case AArch64::SMAX_VG4_4Z4Z_D: |
| 19534 | case AArch64::SMAX_VG4_4Z4Z_H: |
| 19535 | case AArch64::SMAX_VG4_4Z4Z_S: |
| 19536 | case AArch64::SMIN_VG4_4Z4Z_B: |
| 19537 | case AArch64::SMIN_VG4_4Z4Z_D: |
| 19538 | case AArch64::SMIN_VG4_4Z4Z_H: |
| 19539 | case AArch64::SMIN_VG4_4Z4Z_S: |
| 19540 | case AArch64::SQDMULH_VG4_4Z4Z_B: |
| 19541 | case AArch64::SQDMULH_VG4_4Z4Z_D: |
| 19542 | case AArch64::SQDMULH_VG4_4Z4Z_H: |
| 19543 | case AArch64::SQDMULH_VG4_4Z4Z_S: |
| 19544 | case AArch64::SRSHL_VG4_4Z4Z_B: |
| 19545 | case AArch64::SRSHL_VG4_4Z4Z_D: |
| 19546 | case AArch64::SRSHL_VG4_4Z4Z_H: |
| 19547 | case AArch64::SRSHL_VG4_4Z4Z_S: |
| 19548 | case AArch64::UMAX_VG4_4Z4Z_B: |
| 19549 | case AArch64::UMAX_VG4_4Z4Z_D: |
| 19550 | case AArch64::UMAX_VG4_4Z4Z_H: |
| 19551 | case AArch64::UMAX_VG4_4Z4Z_S: |
| 19552 | case AArch64::UMIN_VG4_4Z4Z_B: |
| 19553 | case AArch64::UMIN_VG4_4Z4Z_D: |
| 19554 | case AArch64::UMIN_VG4_4Z4Z_H: |
| 19555 | case AArch64::UMIN_VG4_4Z4Z_S: |
| 19556 | case AArch64::URSHL_VG4_4Z4Z_B: |
| 19557 | case AArch64::URSHL_VG4_4Z4Z_D: |
| 19558 | case AArch64::URSHL_VG4_4Z4Z_H: |
| 19559 | case AArch64::URSHL_VG4_4Z4Z_S: { |
| 19560 | // op: Zm |
| 19561 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 2, Fixups, STI); |
| 19562 | Value |= (op & 0x7) << 18; |
| 19563 | // op: Zdn |
| 19564 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 19565 | Value |= (op & 0x7) << 2; |
| 19566 | break; |
| 19567 | } |
| 19568 | case AArch64::FMLALL_VG4_M4Z4Z_BtoS: |
| 19569 | case AArch64::SMLALL_VG4_M4Z4Z_BtoS: |
| 19570 | case AArch64::SMLALL_VG4_M4Z4Z_HtoD: |
| 19571 | case AArch64::SMLSLL_VG4_M4Z4Z_BtoS: |
| 19572 | case AArch64::SMLSLL_VG4_M4Z4Z_HtoD: |
| 19573 | case AArch64::UMLALL_VG4_M4Z4Z_BtoS: |
| 19574 | case AArch64::UMLALL_VG4_M4Z4Z_HtoD: |
| 19575 | case AArch64::UMLSLL_VG4_M4Z4Z_BtoS: |
| 19576 | case AArch64::UMLSLL_VG4_M4Z4Z_HtoD: |
| 19577 | case AArch64::USMLALL_VG4_M4Z4Z_BtoS: { |
| 19578 | // op: Zm |
| 19579 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 5, Fixups, STI); |
| 19580 | Value |= (op & 0x7) << 18; |
| 19581 | // op: Rv |
| 19582 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 19583 | Value |= (op & 0x3) << 13; |
| 19584 | // op: Zn |
| 19585 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 19586 | Value |= (op & 0x7) << 7; |
| 19587 | // op: imm |
| 19588 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19589 | Value |= (op & 0x1); |
| 19590 | break; |
| 19591 | } |
| 19592 | case AArch64::ADD_VG4_M4Z4Z_D: |
| 19593 | case AArch64::ADD_VG4_M4Z4Z_S: |
| 19594 | case AArch64::BFDOT_VG4_M4Z4Z_HtoS: |
| 19595 | case AArch64::BFMLA_VG4_M4Z4Z: |
| 19596 | case AArch64::BFMLS_VG4_M4Z4Z: |
| 19597 | case AArch64::FDOT_VG4_M4Z4Z_BtoH: |
| 19598 | case AArch64::FDOT_VG4_M4Z4Z_BtoS: |
| 19599 | case AArch64::FDOT_VG4_M4Z4Z_HtoS: |
| 19600 | case AArch64::FMLA_VG4_M4Z4Z_D: |
| 19601 | case AArch64::FMLA_VG4_M4Z4Z_H: |
| 19602 | case AArch64::FMLA_VG4_M4Z4Z_S: |
| 19603 | case AArch64::FMLS_VG4_M4Z4Z_D: |
| 19604 | case AArch64::FMLS_VG4_M4Z4Z_H: |
| 19605 | case AArch64::FMLS_VG4_M4Z4Z_S: |
| 19606 | case AArch64::SDOT_VG4_M4Z4Z_BtoS: |
| 19607 | case AArch64::SDOT_VG4_M4Z4Z_HtoD: |
| 19608 | case AArch64::SDOT_VG4_M4Z4Z_HtoS: |
| 19609 | case AArch64::SUB_VG4_M4Z4Z_D: |
| 19610 | case AArch64::SUB_VG4_M4Z4Z_S: |
| 19611 | case AArch64::UDOT_VG4_M4Z4Z_BtoS: |
| 19612 | case AArch64::UDOT_VG4_M4Z4Z_HtoD: |
| 19613 | case AArch64::UDOT_VG4_M4Z4Z_HtoS: |
| 19614 | case AArch64::USDOT_VG4_M4Z4Z_BToS: { |
| 19615 | // op: Zm |
| 19616 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 5, Fixups, STI); |
| 19617 | Value |= (op & 0x7) << 18; |
| 19618 | // op: Zn |
| 19619 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 19620 | Value |= (op & 0x7) << 7; |
| 19621 | // op: Rv |
| 19622 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 19623 | Value |= (op & 0x3) << 13; |
| 19624 | // op: imm3 |
| 19625 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19626 | Value |= (op & 0x7); |
| 19627 | break; |
| 19628 | } |
| 19629 | case AArch64::PMULL_2ZZZ_Q: { |
| 19630 | // op: Zm |
| 19631 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19632 | Value |= (op & 0x1f) << 16; |
| 19633 | // op: Zn |
| 19634 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 19635 | Value |= (op & 0x1f) << 5; |
| 19636 | // op: Zd |
| 19637 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 19638 | Value |= (op & 0xf) << 1; |
| 19639 | break; |
| 19640 | } |
| 19641 | case AArch64::AESDIMC_2ZZI_B: |
| 19642 | case AArch64::AESD_2ZZI_B: |
| 19643 | case AArch64::AESEMC_2ZZI_B: |
| 19644 | case AArch64::AESE_2ZZI_B: { |
| 19645 | // op: Zm |
| 19646 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19647 | Value |= (op & 0x1f) << 5; |
| 19648 | // op: Zdn |
| 19649 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 19650 | Value |= (op & 0xf) << 1; |
| 19651 | // op: imm2 |
| 19652 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19653 | Value |= (op & 0x3) << 19; |
| 19654 | break; |
| 19655 | } |
| 19656 | case AArch64::AESDIMC_4ZZI_B: |
| 19657 | case AArch64::AESD_4ZZI_B: |
| 19658 | case AArch64::AESEMC_4ZZI_B: |
| 19659 | case AArch64::AESE_4ZZI_B: { |
| 19660 | // op: Zm |
| 19661 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19662 | Value |= (op & 0x1f) << 5; |
| 19663 | // op: Zdn |
| 19664 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 19665 | Value |= (op & 0x7) << 2; |
| 19666 | // op: imm2 |
| 19667 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19668 | Value |= (op & 0x3) << 19; |
| 19669 | break; |
| 19670 | } |
| 19671 | case AArch64::ADD_VG2_2ZZ_B: |
| 19672 | case AArch64::ADD_VG2_2ZZ_D: |
| 19673 | case AArch64::ADD_VG2_2ZZ_H: |
| 19674 | case AArch64::ADD_VG2_2ZZ_S: |
| 19675 | case AArch64::BFMAXNM_VG2_2ZZ_H: |
| 19676 | case AArch64::BFMAX_VG2_2ZZ_H: |
| 19677 | case AArch64::BFMINNM_VG2_2ZZ_H: |
| 19678 | case AArch64::BFMIN_VG2_2ZZ_H: |
| 19679 | case AArch64::BFSCALE_2ZZ: |
| 19680 | case AArch64::FMAXNM_VG2_2ZZ_D: |
| 19681 | case AArch64::FMAXNM_VG2_2ZZ_H: |
| 19682 | case AArch64::FMAXNM_VG2_2ZZ_S: |
| 19683 | case AArch64::FMAX_VG2_2ZZ_D: |
| 19684 | case AArch64::FMAX_VG2_2ZZ_H: |
| 19685 | case AArch64::FMAX_VG2_2ZZ_S: |
| 19686 | case AArch64::FMINNM_VG2_2ZZ_D: |
| 19687 | case AArch64::FMINNM_VG2_2ZZ_H: |
| 19688 | case AArch64::FMINNM_VG2_2ZZ_S: |
| 19689 | case AArch64::FMIN_VG2_2ZZ_D: |
| 19690 | case AArch64::FMIN_VG2_2ZZ_H: |
| 19691 | case AArch64::FMIN_VG2_2ZZ_S: |
| 19692 | case AArch64::FSCALE_2ZZ_D: |
| 19693 | case AArch64::FSCALE_2ZZ_H: |
| 19694 | case AArch64::FSCALE_2ZZ_S: |
| 19695 | case AArch64::SMAX_VG2_2ZZ_B: |
| 19696 | case AArch64::SMAX_VG2_2ZZ_D: |
| 19697 | case AArch64::SMAX_VG2_2ZZ_H: |
| 19698 | case AArch64::SMAX_VG2_2ZZ_S: |
| 19699 | case AArch64::SMIN_VG2_2ZZ_B: |
| 19700 | case AArch64::SMIN_VG2_2ZZ_D: |
| 19701 | case AArch64::SMIN_VG2_2ZZ_H: |
| 19702 | case AArch64::SMIN_VG2_2ZZ_S: |
| 19703 | case AArch64::SQDMULH_VG2_2ZZ_B: |
| 19704 | case AArch64::SQDMULH_VG2_2ZZ_D: |
| 19705 | case AArch64::SQDMULH_VG2_2ZZ_H: |
| 19706 | case AArch64::SQDMULH_VG2_2ZZ_S: |
| 19707 | case AArch64::SRSHL_VG2_2ZZ_B: |
| 19708 | case AArch64::SRSHL_VG2_2ZZ_D: |
| 19709 | case AArch64::SRSHL_VG2_2ZZ_H: |
| 19710 | case AArch64::SRSHL_VG2_2ZZ_S: |
| 19711 | case AArch64::UMAX_VG2_2ZZ_B: |
| 19712 | case AArch64::UMAX_VG2_2ZZ_D: |
| 19713 | case AArch64::UMAX_VG2_2ZZ_H: |
| 19714 | case AArch64::UMAX_VG2_2ZZ_S: |
| 19715 | case AArch64::UMIN_VG2_2ZZ_B: |
| 19716 | case AArch64::UMIN_VG2_2ZZ_D: |
| 19717 | case AArch64::UMIN_VG2_2ZZ_H: |
| 19718 | case AArch64::UMIN_VG2_2ZZ_S: |
| 19719 | case AArch64::URSHL_VG2_2ZZ_B: |
| 19720 | case AArch64::URSHL_VG2_2ZZ_D: |
| 19721 | case AArch64::URSHL_VG2_2ZZ_H: |
| 19722 | case AArch64::URSHL_VG2_2ZZ_S: { |
| 19723 | // op: Zm |
| 19724 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19725 | Value |= (op & 0xf) << 16; |
| 19726 | // op: Zdn |
| 19727 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 19728 | Value |= (op & 0xf) << 1; |
| 19729 | break; |
| 19730 | } |
| 19731 | case AArch64::ADD_VG4_4ZZ_B: |
| 19732 | case AArch64::ADD_VG4_4ZZ_D: |
| 19733 | case AArch64::ADD_VG4_4ZZ_H: |
| 19734 | case AArch64::ADD_VG4_4ZZ_S: |
| 19735 | case AArch64::BFMAXNM_VG4_4ZZ_H: |
| 19736 | case AArch64::BFMAX_VG4_4ZZ_H: |
| 19737 | case AArch64::BFMINNM_VG4_4ZZ_H: |
| 19738 | case AArch64::BFMIN_VG4_4ZZ_H: |
| 19739 | case AArch64::BFSCALE_4ZZ: |
| 19740 | case AArch64::FMAXNM_VG4_4ZZ_D: |
| 19741 | case AArch64::FMAXNM_VG4_4ZZ_H: |
| 19742 | case AArch64::FMAXNM_VG4_4ZZ_S: |
| 19743 | case AArch64::FMAX_VG4_4ZZ_D: |
| 19744 | case AArch64::FMAX_VG4_4ZZ_H: |
| 19745 | case AArch64::FMAX_VG4_4ZZ_S: |
| 19746 | case AArch64::FMINNM_VG4_4ZZ_D: |
| 19747 | case AArch64::FMINNM_VG4_4ZZ_H: |
| 19748 | case AArch64::FMINNM_VG4_4ZZ_S: |
| 19749 | case AArch64::FMIN_VG4_4ZZ_D: |
| 19750 | case AArch64::FMIN_VG4_4ZZ_H: |
| 19751 | case AArch64::FMIN_VG4_4ZZ_S: |
| 19752 | case AArch64::FSCALE_4ZZ_D: |
| 19753 | case AArch64::FSCALE_4ZZ_H: |
| 19754 | case AArch64::FSCALE_4ZZ_S: |
| 19755 | case AArch64::SMAX_VG4_4ZZ_B: |
| 19756 | case AArch64::SMAX_VG4_4ZZ_D: |
| 19757 | case AArch64::SMAX_VG4_4ZZ_H: |
| 19758 | case AArch64::SMAX_VG4_4ZZ_S: |
| 19759 | case AArch64::SMIN_VG4_4ZZ_B: |
| 19760 | case AArch64::SMIN_VG4_4ZZ_D: |
| 19761 | case AArch64::SMIN_VG4_4ZZ_H: |
| 19762 | case AArch64::SMIN_VG4_4ZZ_S: |
| 19763 | case AArch64::SQDMULH_VG4_4ZZ_B: |
| 19764 | case AArch64::SQDMULH_VG4_4ZZ_D: |
| 19765 | case AArch64::SQDMULH_VG4_4ZZ_H: |
| 19766 | case AArch64::SQDMULH_VG4_4ZZ_S: |
| 19767 | case AArch64::SRSHL_VG4_4ZZ_B: |
| 19768 | case AArch64::SRSHL_VG4_4ZZ_D: |
| 19769 | case AArch64::SRSHL_VG4_4ZZ_H: |
| 19770 | case AArch64::SRSHL_VG4_4ZZ_S: |
| 19771 | case AArch64::UMAX_VG4_4ZZ_B: |
| 19772 | case AArch64::UMAX_VG4_4ZZ_D: |
| 19773 | case AArch64::UMAX_VG4_4ZZ_H: |
| 19774 | case AArch64::UMAX_VG4_4ZZ_S: |
| 19775 | case AArch64::UMIN_VG4_4ZZ_B: |
| 19776 | case AArch64::UMIN_VG4_4ZZ_D: |
| 19777 | case AArch64::UMIN_VG4_4ZZ_H: |
| 19778 | case AArch64::UMIN_VG4_4ZZ_S: |
| 19779 | case AArch64::URSHL_VG4_4ZZ_B: |
| 19780 | case AArch64::URSHL_VG4_4ZZ_D: |
| 19781 | case AArch64::URSHL_VG4_4ZZ_H: |
| 19782 | case AArch64::URSHL_VG4_4ZZ_S: { |
| 19783 | // op: Zm |
| 19784 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19785 | Value |= (op & 0xf) << 16; |
| 19786 | // op: Zdn |
| 19787 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 19788 | Value |= (op & 0x7) << 2; |
| 19789 | break; |
| 19790 | } |
| 19791 | case AArch64::BFCLAMP_VG2_2ZZZ_H: |
| 19792 | case AArch64::FCLAMP_VG2_2Z2Z_D: |
| 19793 | case AArch64::FCLAMP_VG2_2Z2Z_H: |
| 19794 | case AArch64::FCLAMP_VG2_2Z2Z_S: |
| 19795 | case AArch64::SCLAMP_VG2_2Z2Z_B: |
| 19796 | case AArch64::SCLAMP_VG2_2Z2Z_D: |
| 19797 | case AArch64::SCLAMP_VG2_2Z2Z_H: |
| 19798 | case AArch64::SCLAMP_VG2_2Z2Z_S: |
| 19799 | case AArch64::UCLAMP_VG2_2Z2Z_B: |
| 19800 | case AArch64::UCLAMP_VG2_2Z2Z_D: |
| 19801 | case AArch64::UCLAMP_VG2_2Z2Z_H: |
| 19802 | case AArch64::UCLAMP_VG2_2Z2Z_S: { |
| 19803 | // op: Zm |
| 19804 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19805 | Value |= (op & 0x1f) << 16; |
| 19806 | // op: Zn |
| 19807 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19808 | Value |= (op & 0x1f) << 5; |
| 19809 | // op: Zd |
| 19810 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 19811 | Value |= (op & 0xf) << 1; |
| 19812 | break; |
| 19813 | } |
| 19814 | case AArch64::BFCLAMP_VG4_4ZZZ_H: |
| 19815 | case AArch64::FCLAMP_VG4_4Z4Z_D: |
| 19816 | case AArch64::FCLAMP_VG4_4Z4Z_H: |
| 19817 | case AArch64::FCLAMP_VG4_4Z4Z_S: |
| 19818 | case AArch64::SCLAMP_VG4_4Z4Z_B: |
| 19819 | case AArch64::SCLAMP_VG4_4Z4Z_D: |
| 19820 | case AArch64::SCLAMP_VG4_4Z4Z_H: |
| 19821 | case AArch64::SCLAMP_VG4_4Z4Z_S: |
| 19822 | case AArch64::UCLAMP_VG4_4Z4Z_B: |
| 19823 | case AArch64::UCLAMP_VG4_4Z4Z_D: |
| 19824 | case AArch64::UCLAMP_VG4_4Z4Z_H: |
| 19825 | case AArch64::UCLAMP_VG4_4Z4Z_S: { |
| 19826 | // op: Zm |
| 19827 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19828 | Value |= (op & 0x1f) << 16; |
| 19829 | // op: Zn |
| 19830 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19831 | Value |= (op & 0x1f) << 5; |
| 19832 | // op: Zd |
| 19833 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 19834 | Value |= (op & 0x7) << 2; |
| 19835 | break; |
| 19836 | } |
| 19837 | case AArch64::BFCLAMP_ZZZ: |
| 19838 | case AArch64::FCLAMP_ZZZ_D: |
| 19839 | case AArch64::FCLAMP_ZZZ_H: |
| 19840 | case AArch64::FCLAMP_ZZZ_S: |
| 19841 | case AArch64::SCLAMP_ZZZ_B: |
| 19842 | case AArch64::SCLAMP_ZZZ_D: |
| 19843 | case AArch64::SCLAMP_ZZZ_H: |
| 19844 | case AArch64::SCLAMP_ZZZ_S: |
| 19845 | case AArch64::UCLAMP_ZZZ_B: |
| 19846 | case AArch64::UCLAMP_ZZZ_D: |
| 19847 | case AArch64::UCLAMP_ZZZ_H: |
| 19848 | case AArch64::UCLAMP_ZZZ_S: { |
| 19849 | // op: Zm |
| 19850 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19851 | Value |= (op & 0x1f) << 16; |
| 19852 | // op: Zn |
| 19853 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19854 | Value |= (op & 0x1f) << 5; |
| 19855 | // op: Zd |
| 19856 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19857 | Value |= (op & 0x1f); |
| 19858 | break; |
| 19859 | } |
| 19860 | case AArch64::PMLAL_2ZZZ_Q: { |
| 19861 | // op: Zm |
| 19862 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19863 | Value |= (op & 0x1f) << 16; |
| 19864 | // op: Zn |
| 19865 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19866 | Value |= (op & 0x1f) << 5; |
| 19867 | // op: Zda |
| 19868 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 19869 | Value |= (op & 0xf) << 1; |
| 19870 | break; |
| 19871 | } |
| 19872 | case AArch64::BFMOPA_MPPZZ_H: |
| 19873 | case AArch64::BFMOPS_MPPZZ_H: |
| 19874 | case AArch64::FMOPA_MPPZZ_BtoH: |
| 19875 | case AArch64::FMOPA_MPPZZ_H: |
| 19876 | case AArch64::FMOPS_MPPZZ_H: { |
| 19877 | // op: Zm |
| 19878 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 19879 | Value |= (op & 0x1f) << 16; |
| 19880 | // op: Pm |
| 19881 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19882 | Value |= (op & 0x7) << 13; |
| 19883 | // op: Pn |
| 19884 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19885 | Value |= (op & 0x7) << 10; |
| 19886 | // op: Zn |
| 19887 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 19888 | Value |= (op & 0x1f) << 5; |
| 19889 | // op: ZAda |
| 19890 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19891 | Value |= (op & 0x1); |
| 19892 | break; |
| 19893 | } |
| 19894 | case AArch64::BFMOPA_MPPZZ: |
| 19895 | case AArch64::BFMOPS_MPPZZ: |
| 19896 | case AArch64::BMOPA_MPPZZ_S: |
| 19897 | case AArch64::BMOPS_MPPZZ_S: |
| 19898 | case AArch64::FMOPAL_MPPZZ: |
| 19899 | case AArch64::FMOPA_MPPZZ_BtoS: |
| 19900 | case AArch64::FMOPA_MPPZZ_S: |
| 19901 | case AArch64::FMOPSL_MPPZZ: |
| 19902 | case AArch64::FMOPS_MPPZZ_S: |
| 19903 | case AArch64::SMOPA_MPPZZ_HtoS: |
| 19904 | case AArch64::SMOPA_MPPZZ_S: |
| 19905 | case AArch64::SMOPS_MPPZZ_HtoS: |
| 19906 | case AArch64::SMOPS_MPPZZ_S: |
| 19907 | case AArch64::SUMOPA_MPPZZ_S: |
| 19908 | case AArch64::SUMOPS_MPPZZ_S: |
| 19909 | case AArch64::UMOPA_MPPZZ_HtoS: |
| 19910 | case AArch64::UMOPA_MPPZZ_S: |
| 19911 | case AArch64::UMOPS_MPPZZ_HtoS: |
| 19912 | case AArch64::UMOPS_MPPZZ_S: |
| 19913 | case AArch64::USMOPA_MPPZZ_S: |
| 19914 | case AArch64::USMOPS_MPPZZ_S: { |
| 19915 | // op: Zm |
| 19916 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 19917 | Value |= (op & 0x1f) << 16; |
| 19918 | // op: Pm |
| 19919 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19920 | Value |= (op & 0x7) << 13; |
| 19921 | // op: Pn |
| 19922 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19923 | Value |= (op & 0x7) << 10; |
| 19924 | // op: Zn |
| 19925 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 19926 | Value |= (op & 0x1f) << 5; |
| 19927 | // op: ZAda |
| 19928 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19929 | Value |= (op & 0x3); |
| 19930 | break; |
| 19931 | } |
| 19932 | case AArch64::FMOPA_MPPZZ_D: |
| 19933 | case AArch64::FMOPS_MPPZZ_D: |
| 19934 | case AArch64::SMOPA_MPPZZ_D: |
| 19935 | case AArch64::SMOPS_MPPZZ_D: |
| 19936 | case AArch64::SUMOPA_MPPZZ_D: |
| 19937 | case AArch64::SUMOPS_MPPZZ_D: |
| 19938 | case AArch64::UMOPA_MPPZZ_D: |
| 19939 | case AArch64::UMOPS_MPPZZ_D: |
| 19940 | case AArch64::USMOPA_MPPZZ_D: |
| 19941 | case AArch64::USMOPS_MPPZZ_D: { |
| 19942 | // op: Zm |
| 19943 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 19944 | Value |= (op & 0x1f) << 16; |
| 19945 | // op: Pm |
| 19946 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19947 | Value |= (op & 0x7) << 13; |
| 19948 | // op: Pn |
| 19949 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 19950 | Value |= (op & 0x7) << 10; |
| 19951 | // op: Zn |
| 19952 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 19953 | Value |= (op & 0x1f) << 5; |
| 19954 | // op: ZAda |
| 19955 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 19956 | Value |= (op & 0x7); |
| 19957 | break; |
| 19958 | } |
| 19959 | case AArch64::FVDOTB_VG4_M2ZZI_BtoS: |
| 19960 | case AArch64::FVDOTT_VG4_M2ZZI_BtoS: { |
| 19961 | // op: Zm |
| 19962 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 19963 | Value |= (op & 0xf) << 16; |
| 19964 | // op: Rv |
| 19965 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 19966 | Value |= (op & 0x3) << 13; |
| 19967 | // op: Zn |
| 19968 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 19969 | Value |= (op & 0xf) << 6; |
| 19970 | // op: imm3 |
| 19971 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 19972 | Value |= (op & 0x7); |
| 19973 | // op: i |
| 19974 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 19975 | Value |= (op & 0x2) << 9; |
| 19976 | Value |= (op & 0x1) << 3; |
| 19977 | break; |
| 19978 | } |
| 19979 | case AArch64::BFDOT_VG2_M2ZZI_HtoS: |
| 19980 | case AArch64::BFVDOT_VG2_M2ZZI_HtoS: |
| 19981 | case AArch64::FDOT_VG2_M2ZZI_BtoS: |
| 19982 | case AArch64::FDOT_VG2_M2ZZI_HtoS: |
| 19983 | case AArch64::FMLA_VG2_M2ZZI_S: |
| 19984 | case AArch64::FMLS_VG2_M2ZZI_S: |
| 19985 | case AArch64::FVDOT_VG2_M2ZZI_HtoS: |
| 19986 | case AArch64::SDOT_VG2_M2ZZI_BToS: |
| 19987 | case AArch64::SDOT_VG2_M2ZZI_HToS: |
| 19988 | case AArch64::SUDOT_VG2_M2ZZI_BToS: |
| 19989 | case AArch64::SVDOT_VG2_M2ZZI_HtoS: |
| 19990 | case AArch64::UDOT_VG2_M2ZZI_BToS: |
| 19991 | case AArch64::UDOT_VG2_M2ZZI_HToS: |
| 19992 | case AArch64::USDOT_VG2_M2ZZI_BToS: |
| 19993 | case AArch64::UVDOT_VG2_M2ZZI_HtoS: { |
| 19994 | // op: Zm |
| 19995 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 19996 | Value |= (op & 0xf) << 16; |
| 19997 | // op: Rv |
| 19998 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 19999 | Value |= (op & 0x3) << 13; |
| 20000 | // op: Zn |
| 20001 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 20002 | Value |= (op & 0xf) << 6; |
| 20003 | // op: imm3 |
| 20004 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20005 | Value |= (op & 0x7); |
| 20006 | // op: i |
| 20007 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20008 | Value |= (op & 0x3) << 10; |
| 20009 | break; |
| 20010 | } |
| 20011 | case AArch64::BFMLA_VG2_M2ZZI: |
| 20012 | case AArch64::BFMLS_VG2_M2ZZI: |
| 20013 | case AArch64::FDOT_VG2_M2ZZI_BtoH: |
| 20014 | case AArch64::FMLA_VG2_M2ZZI_H: |
| 20015 | case AArch64::FMLS_VG2_M2ZZI_H: |
| 20016 | case AArch64::FVDOT_VG2_M2ZZI_BtoH: { |
| 20017 | // op: Zm |
| 20018 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20019 | Value |= (op & 0xf) << 16; |
| 20020 | // op: Rv |
| 20021 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20022 | Value |= (op & 0x3) << 13; |
| 20023 | // op: Zn |
| 20024 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 20025 | Value |= (op & 0xf) << 6; |
| 20026 | // op: imm3 |
| 20027 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20028 | Value |= (op & 0x7); |
| 20029 | // op: i |
| 20030 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20031 | Value |= (op & 0x6) << 9; |
| 20032 | Value |= (op & 0x1) << 3; |
| 20033 | break; |
| 20034 | } |
| 20035 | case AArch64::BFDOT_VG4_M4ZZI_HtoS: |
| 20036 | case AArch64::FDOT_VG4_M4ZZI_BtoS: |
| 20037 | case AArch64::FDOT_VG4_M4ZZI_HtoS: |
| 20038 | case AArch64::FMLA_VG4_M4ZZI_S: |
| 20039 | case AArch64::FMLS_VG4_M4ZZI_S: |
| 20040 | case AArch64::SDOT_VG4_M4ZZI_BToS: |
| 20041 | case AArch64::SDOT_VG4_M4ZZI_HToS: |
| 20042 | case AArch64::SUDOT_VG4_M4ZZI_BToS: |
| 20043 | case AArch64::SUVDOT_VG4_M4ZZI_BToS: |
| 20044 | case AArch64::SVDOT_VG4_M4ZZI_BtoS: |
| 20045 | case AArch64::UDOT_VG4_M4ZZI_BtoS: |
| 20046 | case AArch64::UDOT_VG4_M4ZZI_HToS: |
| 20047 | case AArch64::USDOT_VG4_M4ZZI_BToS: |
| 20048 | case AArch64::USVDOT_VG4_M4ZZI_BToS: |
| 20049 | case AArch64::UVDOT_VG4_M4ZZI_BtoS: { |
| 20050 | // op: Zm |
| 20051 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20052 | Value |= (op & 0xf) << 16; |
| 20053 | // op: Rv |
| 20054 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20055 | Value |= (op & 0x3) << 13; |
| 20056 | // op: Zn |
| 20057 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 20058 | Value |= (op & 0x7) << 7; |
| 20059 | // op: imm3 |
| 20060 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20061 | Value |= (op & 0x7); |
| 20062 | // op: i |
| 20063 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20064 | Value |= (op & 0x3) << 10; |
| 20065 | break; |
| 20066 | } |
| 20067 | case AArch64::BFMLA_VG4_M4ZZI: |
| 20068 | case AArch64::BFMLS_VG4_M4ZZI: |
| 20069 | case AArch64::FDOT_VG4_M4ZZI_BtoH: |
| 20070 | case AArch64::FMLA_VG4_M4ZZI_H: |
| 20071 | case AArch64::FMLS_VG4_M4ZZI_H: { |
| 20072 | // op: Zm |
| 20073 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20074 | Value |= (op & 0xf) << 16; |
| 20075 | // op: Rv |
| 20076 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20077 | Value |= (op & 0x3) << 13; |
| 20078 | // op: Zn |
| 20079 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 20080 | Value |= (op & 0x7) << 7; |
| 20081 | // op: imm3 |
| 20082 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20083 | Value |= (op & 0x7); |
| 20084 | // op: i |
| 20085 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20086 | Value |= (op & 0x6) << 9; |
| 20087 | Value |= (op & 0x1) << 3; |
| 20088 | break; |
| 20089 | } |
| 20090 | case AArch64::FMLALL_VG2_M2ZZ_BtoS: |
| 20091 | case AArch64::FMLALL_VG4_M4ZZ_BtoS: |
| 20092 | case AArch64::SMLALL_VG2_M2ZZ_BtoS: |
| 20093 | case AArch64::SMLALL_VG2_M2ZZ_HtoD: |
| 20094 | case AArch64::SMLALL_VG4_M4ZZ_BtoS: |
| 20095 | case AArch64::SMLALL_VG4_M4ZZ_HtoD: |
| 20096 | case AArch64::SMLSLL_VG2_M2ZZ_BtoS: |
| 20097 | case AArch64::SMLSLL_VG2_M2ZZ_HtoD: |
| 20098 | case AArch64::SMLSLL_VG4_M4ZZ_BtoS: |
| 20099 | case AArch64::SMLSLL_VG4_M4ZZ_HtoD: |
| 20100 | case AArch64::SUMLALL_VG2_M2ZZ_BtoS: |
| 20101 | case AArch64::SUMLALL_VG4_M4ZZ_BtoS: |
| 20102 | case AArch64::UMLALL_VG2_M2ZZ_BtoS: |
| 20103 | case AArch64::UMLALL_VG2_M2ZZ_HtoD: |
| 20104 | case AArch64::UMLALL_VG4_M4ZZ_BtoS: |
| 20105 | case AArch64::UMLALL_VG4_M4ZZ_HtoD: |
| 20106 | case AArch64::UMLSLL_VG2_M2ZZ_BtoS: |
| 20107 | case AArch64::UMLSLL_VG2_M2ZZ_HtoD: |
| 20108 | case AArch64::UMLSLL_VG4_M4ZZ_BtoS: |
| 20109 | case AArch64::UMLSLL_VG4_M4ZZ_HtoD: |
| 20110 | case AArch64::USMLALL_VG2_M2ZZ_BtoS: |
| 20111 | case AArch64::USMLALL_VG4_M4ZZ_BtoS: { |
| 20112 | // op: Zm |
| 20113 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20114 | Value |= (op & 0xf) << 16; |
| 20115 | // op: Rv |
| 20116 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20117 | Value |= (op & 0x3) << 13; |
| 20118 | // op: Zn |
| 20119 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 20120 | Value |= (op & 0x1f) << 5; |
| 20121 | // op: imm |
| 20122 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20123 | Value |= (op & 0x1); |
| 20124 | break; |
| 20125 | } |
| 20126 | case AArch64::FMLALL_MZZ_BtoS: |
| 20127 | case AArch64::SMLALL_MZZ_BtoS: |
| 20128 | case AArch64::SMLALL_MZZ_HtoD: |
| 20129 | case AArch64::SMLSLL_MZZ_BtoS: |
| 20130 | case AArch64::SMLSLL_MZZ_HtoD: |
| 20131 | case AArch64::UMLALL_MZZ_BtoS: |
| 20132 | case AArch64::UMLALL_MZZ_HtoD: |
| 20133 | case AArch64::UMLSLL_MZZ_BtoS: |
| 20134 | case AArch64::UMLSLL_MZZ_HtoD: |
| 20135 | case AArch64::USMLALL_MZZ_BtoS: { |
| 20136 | // op: Zm |
| 20137 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20138 | Value |= (op & 0xf) << 16; |
| 20139 | // op: Rv |
| 20140 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20141 | Value |= (op & 0x3) << 13; |
| 20142 | // op: Zn |
| 20143 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 20144 | Value |= (op & 0x1f) << 5; |
| 20145 | // op: imm |
| 20146 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20147 | Value |= (op & 0x3); |
| 20148 | break; |
| 20149 | } |
| 20150 | case AArch64::SMLALL_MZZI_HtoD: |
| 20151 | case AArch64::SMLSLL_MZZI_HtoD: |
| 20152 | case AArch64::UMLALL_MZZI_HtoD: |
| 20153 | case AArch64::UMLSLL_MZZI_HtoD: { |
| 20154 | // op: Zm |
| 20155 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20156 | Value |= (op & 0xf) << 16; |
| 20157 | // op: Rv |
| 20158 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20159 | Value |= (op & 0x3) << 13; |
| 20160 | // op: i |
| 20161 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20162 | Value |= (op & 0x4) << 13; |
| 20163 | Value |= (op & 0x3) << 10; |
| 20164 | // op: Zn |
| 20165 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 20166 | Value |= (op & 0x1f) << 5; |
| 20167 | // op: imm2 |
| 20168 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20169 | Value |= (op & 0x3); |
| 20170 | break; |
| 20171 | } |
| 20172 | case AArch64::SMLALL_VG2_M2ZZI_HtoD: |
| 20173 | case AArch64::SMLSLL_VG2_M2ZZI_HtoD: |
| 20174 | case AArch64::UMLALL_VG2_M2ZZI_HtoD: |
| 20175 | case AArch64::UMLSLL_VG2_M2ZZI_HtoD: { |
| 20176 | // op: Zm |
| 20177 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20178 | Value |= (op & 0xf) << 16; |
| 20179 | // op: Rv |
| 20180 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20181 | Value |= (op & 0x3) << 13; |
| 20182 | // op: i |
| 20183 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20184 | Value |= (op & 0x4) << 8; |
| 20185 | Value |= (op & 0x3) << 1; |
| 20186 | // op: imm |
| 20187 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20188 | Value |= (op & 0x1); |
| 20189 | // op: Zn |
| 20190 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 20191 | Value |= (op & 0xf) << 6; |
| 20192 | break; |
| 20193 | } |
| 20194 | case AArch64::SMLALL_VG4_M4ZZI_HtoD: |
| 20195 | case AArch64::SMLSLL_VG4_M4ZZI_HtoD: |
| 20196 | case AArch64::UMLALL_VG4_M4ZZI_HtoD: |
| 20197 | case AArch64::UMLSLL_VG4_M4ZZI_HtoD: { |
| 20198 | // op: Zm |
| 20199 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20200 | Value |= (op & 0xf) << 16; |
| 20201 | // op: Rv |
| 20202 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20203 | Value |= (op & 0x3) << 13; |
| 20204 | // op: i |
| 20205 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20206 | Value |= (op & 0x4) << 8; |
| 20207 | Value |= (op & 0x3) << 1; |
| 20208 | // op: imm |
| 20209 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20210 | Value |= (op & 0x1); |
| 20211 | // op: Zn |
| 20212 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 20213 | Value |= (op & 0x7) << 7; |
| 20214 | break; |
| 20215 | } |
| 20216 | case AArch64::FMLAL_MZZI_BtoH: { |
| 20217 | // op: Zm |
| 20218 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20219 | Value |= (op & 0xf) << 16; |
| 20220 | // op: Rv |
| 20221 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20222 | Value |= (op & 0x3) << 13; |
| 20223 | // op: i |
| 20224 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20225 | Value |= (op & 0x8) << 12; |
| 20226 | Value |= (op & 0x6) << 9; |
| 20227 | Value |= (op & 0x1) << 3; |
| 20228 | // op: Zn |
| 20229 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 20230 | Value |= (op & 0x1f) << 5; |
| 20231 | // op: imm3 |
| 20232 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20233 | Value |= (op & 0x7); |
| 20234 | break; |
| 20235 | } |
| 20236 | case AArch64::FMLALL_MZZI_BtoS: |
| 20237 | case AArch64::SMLALL_MZZI_BtoS: |
| 20238 | case AArch64::SMLSLL_MZZI_BtoS: |
| 20239 | case AArch64::SUMLALL_MZZI_BtoS: |
| 20240 | case AArch64::UMLALL_MZZI_BtoS: |
| 20241 | case AArch64::UMLSLL_MZZI_BtoS: |
| 20242 | case AArch64::USMLALL_MZZI_BtoS: { |
| 20243 | // op: Zm |
| 20244 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20245 | Value |= (op & 0xf) << 16; |
| 20246 | // op: Rv |
| 20247 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20248 | Value |= (op & 0x3) << 13; |
| 20249 | // op: i |
| 20250 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20251 | Value |= (op & 0x8) << 12; |
| 20252 | Value |= (op & 0x7) << 10; |
| 20253 | // op: Zn |
| 20254 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 20255 | Value |= (op & 0x1f) << 5; |
| 20256 | // op: imm2 |
| 20257 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20258 | Value |= (op & 0x3); |
| 20259 | break; |
| 20260 | } |
| 20261 | case AArch64::FMLALL_VG2_M2ZZI_BtoS: |
| 20262 | case AArch64::SMLALL_VG2_M2ZZI_BtoS: |
| 20263 | case AArch64::SMLSLL_VG2_M2ZZI_BtoS: |
| 20264 | case AArch64::SUMLALL_VG2_M2ZZI_BtoS: |
| 20265 | case AArch64::UMLALL_VG2_M2ZZI_BtoS: |
| 20266 | case AArch64::UMLSLL_VG2_M2ZZI_BtoS: |
| 20267 | case AArch64::USMLALL_VG2_M2ZZI_BtoS: { |
| 20268 | // op: Zm |
| 20269 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20270 | Value |= (op & 0xf) << 16; |
| 20271 | // op: Rv |
| 20272 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20273 | Value |= (op & 0x3) << 13; |
| 20274 | // op: i |
| 20275 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20276 | Value |= (op & 0xc) << 8; |
| 20277 | Value |= (op & 0x3) << 1; |
| 20278 | // op: imm |
| 20279 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20280 | Value |= (op & 0x1); |
| 20281 | // op: Zn |
| 20282 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 20283 | Value |= (op & 0xf) << 6; |
| 20284 | break; |
| 20285 | } |
| 20286 | case AArch64::FMLALL_VG4_M4ZZI_BtoS: |
| 20287 | case AArch64::SMLALL_VG4_M4ZZI_BtoS: |
| 20288 | case AArch64::SMLSLL_VG4_M4ZZI_BtoS: |
| 20289 | case AArch64::SUMLALL_VG4_M4ZZI_BtoS: |
| 20290 | case AArch64::UMLALL_VG4_M4ZZI_BtoS: |
| 20291 | case AArch64::UMLSLL_VG4_M4ZZI_BtoS: |
| 20292 | case AArch64::USMLALL_VG4_M4ZZI_BtoS: { |
| 20293 | // op: Zm |
| 20294 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20295 | Value |= (op & 0xf) << 16; |
| 20296 | // op: Rv |
| 20297 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20298 | Value |= (op & 0x3) << 13; |
| 20299 | // op: i |
| 20300 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20301 | Value |= (op & 0xc) << 8; |
| 20302 | Value |= (op & 0x3) << 1; |
| 20303 | // op: imm |
| 20304 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20305 | Value |= (op & 0x1); |
| 20306 | // op: Zn |
| 20307 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 20308 | Value |= (op & 0x7) << 7; |
| 20309 | break; |
| 20310 | } |
| 20311 | case AArch64::FMLAL_VG2_M2ZZI_BtoH: { |
| 20312 | // op: Zm |
| 20313 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20314 | Value |= (op & 0xf) << 16; |
| 20315 | // op: Rv |
| 20316 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20317 | Value |= (op & 0x3) << 13; |
| 20318 | // op: i |
| 20319 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20320 | Value |= (op & 0xc) << 8; |
| 20321 | Value |= (op & 0x3) << 2; |
| 20322 | // op: imm2 |
| 20323 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20324 | Value |= (op & 0x3); |
| 20325 | // op: Zn |
| 20326 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 20327 | Value |= (op & 0xf) << 6; |
| 20328 | break; |
| 20329 | } |
| 20330 | case AArch64::FMLAL_VG4_M4ZZI_BtoH: { |
| 20331 | // op: Zm |
| 20332 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20333 | Value |= (op & 0xf) << 16; |
| 20334 | // op: Rv |
| 20335 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20336 | Value |= (op & 0x3) << 13; |
| 20337 | // op: i |
| 20338 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20339 | Value |= (op & 0xc) << 8; |
| 20340 | Value |= (op & 0x3) << 2; |
| 20341 | // op: imm2 |
| 20342 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20343 | Value |= (op & 0x3); |
| 20344 | // op: Zn |
| 20345 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 20346 | Value |= (op & 0x7) << 7; |
| 20347 | break; |
| 20348 | } |
| 20349 | case AArch64::FMLA_VG2_M2ZZI_D: |
| 20350 | case AArch64::FMLS_VG2_M2ZZI_D: |
| 20351 | case AArch64::SDOT_VG2_M2ZZI_HtoD: |
| 20352 | case AArch64::UDOT_VG2_M2ZZI_HtoD: { |
| 20353 | // op: Zm |
| 20354 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20355 | Value |= (op & 0xf) << 16; |
| 20356 | // op: Rv |
| 20357 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20358 | Value |= (op & 0x3) << 13; |
| 20359 | // op: i1 |
| 20360 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20361 | Value |= (op & 0x1) << 10; |
| 20362 | // op: Zn |
| 20363 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 20364 | Value |= (op & 0xf) << 6; |
| 20365 | // op: imm3 |
| 20366 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20367 | Value |= (op & 0x7); |
| 20368 | break; |
| 20369 | } |
| 20370 | case AArch64::FMLA_VG4_M4ZZI_D: |
| 20371 | case AArch64::FMLS_VG4_M4ZZI_D: |
| 20372 | case AArch64::SDOT_VG4_M4ZZI_HtoD: |
| 20373 | case AArch64::SVDOT_VG4_M4ZZI_HtoD: |
| 20374 | case AArch64::UDOT_VG4_M4ZZI_HtoD: |
| 20375 | case AArch64::UVDOT_VG4_M4ZZI_HtoD: { |
| 20376 | // op: Zm |
| 20377 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20378 | Value |= (op & 0xf) << 16; |
| 20379 | // op: Rv |
| 20380 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20381 | Value |= (op & 0x3) << 13; |
| 20382 | // op: i1 |
| 20383 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20384 | Value |= (op & 0x1) << 10; |
| 20385 | // op: Zn |
| 20386 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 20387 | Value |= (op & 0x7) << 7; |
| 20388 | // op: imm3 |
| 20389 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20390 | Value |= (op & 0x7); |
| 20391 | break; |
| 20392 | } |
| 20393 | case AArch64::BFMLAL_MZZI_HtoS: |
| 20394 | case AArch64::BFMLSL_MZZI_HtoS: |
| 20395 | case AArch64::FMLAL_MZZI_HtoS: |
| 20396 | case AArch64::FMLSL_MZZI_HtoS: |
| 20397 | case AArch64::SMLAL_MZZI_HtoS: |
| 20398 | case AArch64::SMLSL_MZZI_HtoS: |
| 20399 | case AArch64::UMLAL_MZZI_HtoS: |
| 20400 | case AArch64::UMLSL_MZZI_HtoS: { |
| 20401 | // op: Zm |
| 20402 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20403 | Value |= (op & 0xf) << 16; |
| 20404 | // op: Rv |
| 20405 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20406 | Value |= (op & 0x3) << 13; |
| 20407 | // op: i3 |
| 20408 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20409 | Value |= (op & 0x4) << 13; |
| 20410 | Value |= (op & 0x3) << 10; |
| 20411 | // op: Zn |
| 20412 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 20413 | Value |= (op & 0x1f) << 5; |
| 20414 | // op: imm |
| 20415 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20416 | Value |= (op & 0x7); |
| 20417 | break; |
| 20418 | } |
| 20419 | case AArch64::BFMLAL_VG2_M2ZZI_HtoS: |
| 20420 | case AArch64::BFMLSL_VG2_M2ZZI_HtoS: |
| 20421 | case AArch64::FMLAL_VG2_M2ZZI_HtoS: |
| 20422 | case AArch64::FMLSL_VG2_M2ZZI_HtoS: |
| 20423 | case AArch64::SMLAL_VG2_M2ZZI_S: |
| 20424 | case AArch64::SMLSL_VG2_M2ZZI_S: |
| 20425 | case AArch64::UMLAL_VG2_M2ZZI_S: |
| 20426 | case AArch64::UMLSL_VG2_M2ZZI_S: { |
| 20427 | // op: Zm |
| 20428 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20429 | Value |= (op & 0xf) << 16; |
| 20430 | // op: Rv |
| 20431 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20432 | Value |= (op & 0x3) << 13; |
| 20433 | // op: i3 |
| 20434 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20435 | Value |= (op & 0x6) << 9; |
| 20436 | Value |= (op & 0x1) << 2; |
| 20437 | // op: Zn |
| 20438 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 4, Fixups, STI); |
| 20439 | Value |= (op & 0xf) << 6; |
| 20440 | // op: imm |
| 20441 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20442 | Value |= (op & 0x3); |
| 20443 | break; |
| 20444 | } |
| 20445 | case AArch64::BFMLAL_VG4_M4ZZI_HtoS: |
| 20446 | case AArch64::BFMLSL_VG4_M4ZZI_HtoS: |
| 20447 | case AArch64::FMLAL_VG4_M4ZZI_HtoS: |
| 20448 | case AArch64::FMLSL_VG4_M4ZZI_HtoS: |
| 20449 | case AArch64::SMLAL_VG4_M4ZZI_HtoS: |
| 20450 | case AArch64::SMLSL_VG4_M4ZZI_HtoS: |
| 20451 | case AArch64::UMLAL_VG4_M4ZZI_HtoS: |
| 20452 | case AArch64::UMLSL_VG4_M4ZZI_HtoS: { |
| 20453 | // op: Zm |
| 20454 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20455 | Value |= (op & 0xf) << 16; |
| 20456 | // op: Rv |
| 20457 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20458 | Value |= (op & 0x3) << 13; |
| 20459 | // op: i3 |
| 20460 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 6), Fixups, STI); |
| 20461 | Value |= (op & 0x6) << 9; |
| 20462 | Value |= (op & 0x1) << 2; |
| 20463 | // op: Zn |
| 20464 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 4, Fixups, STI); |
| 20465 | Value |= (op & 0x7) << 7; |
| 20466 | // op: imm |
| 20467 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20468 | Value |= (op & 0x3); |
| 20469 | break; |
| 20470 | } |
| 20471 | case AArch64::ADD_VG2_M2ZZ_D: |
| 20472 | case AArch64::ADD_VG2_M2ZZ_S: |
| 20473 | case AArch64::ADD_VG4_M4ZZ_D: |
| 20474 | case AArch64::ADD_VG4_M4ZZ_S: |
| 20475 | case AArch64::BFDOT_VG2_M2ZZ_HtoS: |
| 20476 | case AArch64::BFDOT_VG4_M4ZZ_HtoS: |
| 20477 | case AArch64::BFMLA_VG2_M2ZZ: |
| 20478 | case AArch64::BFMLA_VG4_M4ZZ: |
| 20479 | case AArch64::BFMLS_VG2_M2ZZ: |
| 20480 | case AArch64::BFMLS_VG4_M4ZZ: |
| 20481 | case AArch64::FDOT_VG2_M2ZZ_BtoH: |
| 20482 | case AArch64::FDOT_VG2_M2ZZ_BtoS: |
| 20483 | case AArch64::FDOT_VG2_M2ZZ_HtoS: |
| 20484 | case AArch64::FDOT_VG4_M4ZZ_BtoH: |
| 20485 | case AArch64::FDOT_VG4_M4ZZ_BtoS: |
| 20486 | case AArch64::FDOT_VG4_M4ZZ_HtoS: |
| 20487 | case AArch64::FMLA_VG2_M2ZZ_D: |
| 20488 | case AArch64::FMLA_VG2_M2ZZ_H: |
| 20489 | case AArch64::FMLA_VG2_M2ZZ_S: |
| 20490 | case AArch64::FMLA_VG4_M4ZZ_D: |
| 20491 | case AArch64::FMLA_VG4_M4ZZ_H: |
| 20492 | case AArch64::FMLA_VG4_M4ZZ_S: |
| 20493 | case AArch64::FMLS_VG2_M2ZZ_D: |
| 20494 | case AArch64::FMLS_VG2_M2ZZ_H: |
| 20495 | case AArch64::FMLS_VG2_M2ZZ_S: |
| 20496 | case AArch64::FMLS_VG4_M4ZZ_D: |
| 20497 | case AArch64::FMLS_VG4_M4ZZ_H: |
| 20498 | case AArch64::FMLS_VG4_M4ZZ_S: |
| 20499 | case AArch64::SDOT_VG2_M2ZZ_BtoS: |
| 20500 | case AArch64::SDOT_VG2_M2ZZ_HtoD: |
| 20501 | case AArch64::SDOT_VG2_M2ZZ_HtoS: |
| 20502 | case AArch64::SDOT_VG4_M4ZZ_BtoS: |
| 20503 | case AArch64::SDOT_VG4_M4ZZ_HtoD: |
| 20504 | case AArch64::SDOT_VG4_M4ZZ_HtoS: |
| 20505 | case AArch64::SUB_VG2_M2ZZ_D: |
| 20506 | case AArch64::SUB_VG2_M2ZZ_S: |
| 20507 | case AArch64::SUB_VG4_M4ZZ_D: |
| 20508 | case AArch64::SUB_VG4_M4ZZ_S: |
| 20509 | case AArch64::SUDOT_VG2_M2ZZ_BToS: |
| 20510 | case AArch64::SUDOT_VG4_M4ZZ_BToS: |
| 20511 | case AArch64::UDOT_VG2_M2ZZ_BtoS: |
| 20512 | case AArch64::UDOT_VG2_M2ZZ_HtoD: |
| 20513 | case AArch64::UDOT_VG2_M2ZZ_HtoS: |
| 20514 | case AArch64::UDOT_VG4_M4ZZ_BtoS: |
| 20515 | case AArch64::UDOT_VG4_M4ZZ_HtoD: |
| 20516 | case AArch64::UDOT_VG4_M4ZZ_HtoS: |
| 20517 | case AArch64::USDOT_VG2_M2ZZ_BToS: |
| 20518 | case AArch64::USDOT_VG4_M4ZZ_BToS: { |
| 20519 | // op: Zm |
| 20520 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 5), Fixups, STI); |
| 20521 | Value |= (op & 0xf) << 16; |
| 20522 | // op: Zn |
| 20523 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 4), Fixups, STI); |
| 20524 | Value |= (op & 0x1f) << 5; |
| 20525 | // op: Rv |
| 20526 | op = encodeMatrixIndexGPR32<AArch64::W8>(MI, OpIdx: 2, Fixups, STI); |
| 20527 | Value |= (op & 0x3) << 13; |
| 20528 | // op: imm3 |
| 20529 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20530 | Value |= (op & 0x7); |
| 20531 | break; |
| 20532 | } |
| 20533 | case AArch64::FCVTZS_2Z2Z_StoS: |
| 20534 | case AArch64::FCVTZU_2Z2Z_StoS: |
| 20535 | case AArch64::FRINTA_2Z2Z_S: |
| 20536 | case AArch64::FRINTM_2Z2Z_S: |
| 20537 | case AArch64::FRINTN_2Z2Z_S: |
| 20538 | case AArch64::FRINTP_2Z2Z_S: |
| 20539 | case AArch64::SCVTF_2Z2Z_StoS: |
| 20540 | case AArch64::UCVTF_2Z2Z_StoS: { |
| 20541 | // op: Zn |
| 20542 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI); |
| 20543 | Value |= (op & 0xf) << 6; |
| 20544 | // op: Zd |
| 20545 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 20546 | Value |= (op & 0xf) << 1; |
| 20547 | break; |
| 20548 | } |
| 20549 | case AArch64::SUNPK_VG4_4Z2Z_D: |
| 20550 | case AArch64::SUNPK_VG4_4Z2Z_H: |
| 20551 | case AArch64::SUNPK_VG4_4Z2Z_S: |
| 20552 | case AArch64::UUNPK_VG4_4Z2Z_D: |
| 20553 | case AArch64::UUNPK_VG4_4Z2Z_H: |
| 20554 | case AArch64::UUNPK_VG4_4Z2Z_S: { |
| 20555 | // op: Zn |
| 20556 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI); |
| 20557 | Value |= (op & 0xf) << 6; |
| 20558 | // op: Zd |
| 20559 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 20560 | Value |= (op & 0x7) << 2; |
| 20561 | break; |
| 20562 | } |
| 20563 | case AArch64::BFCVTN_Z2Z_StoH: |
| 20564 | case AArch64::BFCVT_Z2Z_HtoB: |
| 20565 | case AArch64::BFCVT_Z2Z_StoH: |
| 20566 | case AArch64::FCVTN_Z2Z_StoH: |
| 20567 | case AArch64::FCVT_Z2Z_HtoB: |
| 20568 | case AArch64::FCVT_Z2Z_StoH: |
| 20569 | case AArch64::SQCVTU_Z2Z_StoH: |
| 20570 | case AArch64::SQCVT_Z2Z_StoH: |
| 20571 | case AArch64::UQCVT_Z2Z_StoH: { |
| 20572 | // op: Zn |
| 20573 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI); |
| 20574 | Value |= (op & 0xf) << 6; |
| 20575 | // op: Zd |
| 20576 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 20577 | Value |= (op & 0x1f); |
| 20578 | break; |
| 20579 | } |
| 20580 | case AArch64::LUTI4_4ZZT2Z: { |
| 20581 | // op: Zn |
| 20582 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI); |
| 20583 | Value |= (op & 0xf) << 6; |
| 20584 | // op: Zd |
| 20585 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 20586 | Value |= (op & 0x7) << 2; |
| 20587 | break; |
| 20588 | } |
| 20589 | case AArch64::LUTI4_S_4ZZT2Z: { |
| 20590 | // op: Zn |
| 20591 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 2, Fixups, STI); |
| 20592 | Value |= (op & 0xf) << 6; |
| 20593 | // op: Zd |
| 20594 | op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI); |
| 20595 | Value |= (op & 0x4) << 2; |
| 20596 | Value |= (op & 0x3); |
| 20597 | break; |
| 20598 | } |
| 20599 | case AArch64::FCVTZS_4Z4Z_StoS: |
| 20600 | case AArch64::FCVTZU_4Z4Z_StoS: |
| 20601 | case AArch64::FRINTA_4Z4Z_S: |
| 20602 | case AArch64::FRINTM_4Z4Z_S: |
| 20603 | case AArch64::FRINTN_4Z4Z_S: |
| 20604 | case AArch64::FRINTP_4Z4Z_S: |
| 20605 | case AArch64::SCVTF_4Z4Z_StoS: |
| 20606 | case AArch64::UCVTF_4Z4Z_StoS: |
| 20607 | case AArch64::UZP_VG4_4Z4Z_B: |
| 20608 | case AArch64::UZP_VG4_4Z4Z_D: |
| 20609 | case AArch64::UZP_VG4_4Z4Z_H: |
| 20610 | case AArch64::UZP_VG4_4Z4Z_Q: |
| 20611 | case AArch64::UZP_VG4_4Z4Z_S: |
| 20612 | case AArch64::ZIP_VG4_4Z4Z_B: |
| 20613 | case AArch64::ZIP_VG4_4Z4Z_D: |
| 20614 | case AArch64::ZIP_VG4_4Z4Z_H: |
| 20615 | case AArch64::ZIP_VG4_4Z4Z_Q: |
| 20616 | case AArch64::ZIP_VG4_4Z4Z_S: { |
| 20617 | // op: Zn |
| 20618 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 1, Fixups, STI); |
| 20619 | Value |= (op & 0x7) << 7; |
| 20620 | // op: Zd |
| 20621 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 20622 | Value |= (op & 0x7) << 2; |
| 20623 | break; |
| 20624 | } |
| 20625 | case AArch64::FCVTN_Z4Z_StoB: |
| 20626 | case AArch64::FCVT_Z4Z_StoB: |
| 20627 | case AArch64::SQCVTN_Z4Z_DtoH: |
| 20628 | case AArch64::SQCVTN_Z4Z_StoB: |
| 20629 | case AArch64::SQCVTUN_Z4Z_DtoH: |
| 20630 | case AArch64::SQCVTUN_Z4Z_StoB: |
| 20631 | case AArch64::SQCVTU_Z4Z_DtoH: |
| 20632 | case AArch64::SQCVTU_Z4Z_StoB: |
| 20633 | case AArch64::SQCVT_Z4Z_DtoH: |
| 20634 | case AArch64::SQCVT_Z4Z_StoB: |
| 20635 | case AArch64::UQCVTN_Z4Z_DtoH: |
| 20636 | case AArch64::UQCVTN_Z4Z_StoB: |
| 20637 | case AArch64::UQCVT_Z4Z_DtoH: |
| 20638 | case AArch64::UQCVT_Z4Z_StoB: { |
| 20639 | // op: Zn |
| 20640 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 1, Fixups, STI); |
| 20641 | Value |= (op & 0x7) << 7; |
| 20642 | // op: Zd |
| 20643 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 20644 | Value |= (op & 0x1f); |
| 20645 | break; |
| 20646 | } |
| 20647 | case AArch64::SQRSHRN_VG4_Z4ZI_B: |
| 20648 | case AArch64::SQRSHRUN_VG4_Z4ZI_B: |
| 20649 | case AArch64::SQRSHRU_VG4_Z4ZI_B: |
| 20650 | case AArch64::SQRSHR_VG4_Z4ZI_B: |
| 20651 | case AArch64::UQRSHRN_VG4_Z4ZI_B: |
| 20652 | case AArch64::UQRSHR_VG4_Z4ZI_B: { |
| 20653 | // op: Zn |
| 20654 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 1, Fixups, STI); |
| 20655 | Value |= (op & 0x7) << 7; |
| 20656 | // op: Zd |
| 20657 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 20658 | Value |= (op & 0x1f); |
| 20659 | // op: imm |
| 20660 | op = getVecShiftR32OpValue(MI, OpIdx: 2, Fixups, STI); |
| 20661 | Value |= (op & 0x1f) << 16; |
| 20662 | break; |
| 20663 | } |
| 20664 | case AArch64::SQRSHRN_VG4_Z4ZI_H: |
| 20665 | case AArch64::SQRSHRUN_VG4_Z4ZI_H: |
| 20666 | case AArch64::SQRSHRU_VG4_Z4ZI_H: |
| 20667 | case AArch64::SQRSHR_VG4_Z4ZI_H: |
| 20668 | case AArch64::UQRSHRN_VG4_Z4ZI_H: |
| 20669 | case AArch64::UQRSHR_VG4_Z4ZI_H: { |
| 20670 | // op: Zn |
| 20671 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 1, Fixups, STI); |
| 20672 | Value |= (op & 0x7) << 7; |
| 20673 | // op: Zd |
| 20674 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 20675 | Value |= (op & 0x1f); |
| 20676 | // op: imm |
| 20677 | op = getVecShiftR64OpValue(MI, OpIdx: 2, Fixups, STI); |
| 20678 | Value |= (op & 0x20) << 17; |
| 20679 | Value |= (op & 0x1f) << 16; |
| 20680 | break; |
| 20681 | } |
| 20682 | case AArch64::BF1CVTL_2ZZ_BtoH: |
| 20683 | case AArch64::BF1CVT_2ZZ_BtoH: |
| 20684 | case AArch64::BF2CVTL_2ZZ_BtoH: |
| 20685 | case AArch64::BF2CVT_2ZZ_BtoH: |
| 20686 | case AArch64::F1CVTL_2ZZ_BtoH: |
| 20687 | case AArch64::F1CVT_2ZZ_BtoH: |
| 20688 | case AArch64::F2CVTL_2ZZ_BtoH: |
| 20689 | case AArch64::F2CVT_2ZZ_BtoH: |
| 20690 | case AArch64::FCVTL_2ZZ_H_S: |
| 20691 | case AArch64::FCVT_2ZZ_H_S: |
| 20692 | case AArch64::SUNPK_VG2_2ZZ_D: |
| 20693 | case AArch64::SUNPK_VG2_2ZZ_H: |
| 20694 | case AArch64::SUNPK_VG2_2ZZ_S: |
| 20695 | case AArch64::UUNPK_VG2_2ZZ_D: |
| 20696 | case AArch64::UUNPK_VG2_2ZZ_H: |
| 20697 | case AArch64::UUNPK_VG2_2ZZ_S: { |
| 20698 | // op: Zn |
| 20699 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 20700 | Value |= (op & 0x1f) << 5; |
| 20701 | // op: Zd |
| 20702 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 20703 | Value |= (op & 0xf) << 1; |
| 20704 | break; |
| 20705 | } |
| 20706 | case AArch64::FADDV_VPZ_D: |
| 20707 | case AArch64::FADDV_VPZ_H: |
| 20708 | case AArch64::FADDV_VPZ_S: |
| 20709 | case AArch64::FMAXNMV_VPZ_D: |
| 20710 | case AArch64::FMAXNMV_VPZ_H: |
| 20711 | case AArch64::FMAXNMV_VPZ_S: |
| 20712 | case AArch64::FMAXV_VPZ_D: |
| 20713 | case AArch64::FMAXV_VPZ_H: |
| 20714 | case AArch64::FMAXV_VPZ_S: |
| 20715 | case AArch64::FMINNMV_VPZ_D: |
| 20716 | case AArch64::FMINNMV_VPZ_H: |
| 20717 | case AArch64::FMINNMV_VPZ_S: |
| 20718 | case AArch64::FMINV_VPZ_D: |
| 20719 | case AArch64::FMINV_VPZ_H: |
| 20720 | case AArch64::FMINV_VPZ_S: { |
| 20721 | // op: Zn |
| 20722 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20723 | Value |= (op & 0x1f) << 5; |
| 20724 | // op: Vd |
| 20725 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 20726 | Value |= (op & 0x1f); |
| 20727 | // op: Pg |
| 20728 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 20729 | Value |= (op & 0x7) << 10; |
| 20730 | break; |
| 20731 | } |
| 20732 | case AArch64::LUTI4_2ZTZI_B: |
| 20733 | case AArch64::LUTI4_2ZTZI_H: |
| 20734 | case AArch64::LUTI4_2ZTZI_S: { |
| 20735 | // op: Zn |
| 20736 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20737 | Value |= (op & 0x1f) << 5; |
| 20738 | // op: Zd |
| 20739 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 20740 | Value |= (op & 0xf) << 1; |
| 20741 | // op: i |
| 20742 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20743 | Value |= (op & 0x3) << 15; |
| 20744 | break; |
| 20745 | } |
| 20746 | case AArch64::LUTI2_2ZTZI_B: |
| 20747 | case AArch64::LUTI2_2ZTZI_H: |
| 20748 | case AArch64::LUTI2_2ZTZI_S: { |
| 20749 | // op: Zn |
| 20750 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20751 | Value |= (op & 0x1f) << 5; |
| 20752 | // op: Zd |
| 20753 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 20754 | Value |= (op & 0xf) << 1; |
| 20755 | // op: i |
| 20756 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20757 | Value |= (op & 0x7) << 15; |
| 20758 | break; |
| 20759 | } |
| 20760 | case AArch64::LUTI4_4ZTZI_H: |
| 20761 | case AArch64::LUTI4_4ZTZI_S: { |
| 20762 | // op: Zn |
| 20763 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20764 | Value |= (op & 0x1f) << 5; |
| 20765 | // op: Zd |
| 20766 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 20767 | Value |= (op & 0x7) << 2; |
| 20768 | // op: i |
| 20769 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20770 | Value |= (op & 0x1) << 16; |
| 20771 | break; |
| 20772 | } |
| 20773 | case AArch64::LUTI2_4ZTZI_B: |
| 20774 | case AArch64::LUTI2_4ZTZI_H: |
| 20775 | case AArch64::LUTI2_4ZTZI_S: { |
| 20776 | // op: Zn |
| 20777 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20778 | Value |= (op & 0x1f) << 5; |
| 20779 | // op: Zd |
| 20780 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 20781 | Value |= (op & 0x7) << 2; |
| 20782 | // op: i |
| 20783 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20784 | Value |= (op & 0x3) << 16; |
| 20785 | break; |
| 20786 | } |
| 20787 | case AArch64::LUTI4_S_2ZTZI_B: |
| 20788 | case AArch64::LUTI4_S_2ZTZI_H: { |
| 20789 | // op: Zn |
| 20790 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20791 | Value |= (op & 0x1f) << 5; |
| 20792 | // op: Zd |
| 20793 | op = EncodeZPR2StridedRegisterClass(MI, OpIdx: 0, Fixups, STI); |
| 20794 | Value |= (op & 0x8) << 1; |
| 20795 | Value |= (op & 0x7); |
| 20796 | // op: i |
| 20797 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20798 | Value |= (op & 0x3) << 15; |
| 20799 | break; |
| 20800 | } |
| 20801 | case AArch64::LUTI2_S_2ZTZI_B: |
| 20802 | case AArch64::LUTI2_S_2ZTZI_H: { |
| 20803 | // op: Zn |
| 20804 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20805 | Value |= (op & 0x1f) << 5; |
| 20806 | // op: Zd |
| 20807 | op = EncodeZPR2StridedRegisterClass(MI, OpIdx: 0, Fixups, STI); |
| 20808 | Value |= (op & 0x8) << 1; |
| 20809 | Value |= (op & 0x7); |
| 20810 | // op: i |
| 20811 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20812 | Value |= (op & 0x7) << 15; |
| 20813 | break; |
| 20814 | } |
| 20815 | case AArch64::LUTI4_S_4ZTZI_H: { |
| 20816 | // op: Zn |
| 20817 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20818 | Value |= (op & 0x1f) << 5; |
| 20819 | // op: Zd |
| 20820 | op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI); |
| 20821 | Value |= (op & 0x4) << 2; |
| 20822 | Value |= (op & 0x3); |
| 20823 | // op: i |
| 20824 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20825 | Value |= (op & 0x1) << 16; |
| 20826 | break; |
| 20827 | } |
| 20828 | case AArch64::LUTI2_S_4ZTZI_B: |
| 20829 | case AArch64::LUTI2_S_4ZTZI_H: { |
| 20830 | // op: Zn |
| 20831 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20832 | Value |= (op & 0x1f) << 5; |
| 20833 | // op: Zd |
| 20834 | op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI); |
| 20835 | Value |= (op & 0x4) << 2; |
| 20836 | Value |= (op & 0x3); |
| 20837 | // op: i |
| 20838 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20839 | Value |= (op & 0x3) << 16; |
| 20840 | break; |
| 20841 | } |
| 20842 | case AArch64::LUTI4_ZTZI_B: |
| 20843 | case AArch64::LUTI4_ZTZI_H: |
| 20844 | case AArch64::LUTI4_ZTZI_S: { |
| 20845 | // op: Zn |
| 20846 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20847 | Value |= (op & 0x1f) << 5; |
| 20848 | // op: Zd |
| 20849 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 20850 | Value |= (op & 0x1f); |
| 20851 | // op: i |
| 20852 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20853 | Value |= (op & 0x7) << 14; |
| 20854 | break; |
| 20855 | } |
| 20856 | case AArch64::LUTI2_ZTZI_B: |
| 20857 | case AArch64::LUTI2_ZTZI_H: |
| 20858 | case AArch64::LUTI2_ZTZI_S: { |
| 20859 | // op: Zn |
| 20860 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20861 | Value |= (op & 0x1f) << 5; |
| 20862 | // op: Zd |
| 20863 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 20864 | Value |= (op & 0x1f); |
| 20865 | // op: i |
| 20866 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20867 | Value |= (op & 0xf) << 14; |
| 20868 | break; |
| 20869 | } |
| 20870 | case AArch64::LD1B_2Z: |
| 20871 | case AArch64::LD1D_2Z: |
| 20872 | case AArch64::LD1H_2Z: |
| 20873 | case AArch64::LD1W_2Z: |
| 20874 | case AArch64::LDNT1B_2Z: |
| 20875 | case AArch64::LDNT1D_2Z: |
| 20876 | case AArch64::LDNT1H_2Z: |
| 20877 | case AArch64::LDNT1W_2Z: |
| 20878 | case AArch64::ST1B_2Z: |
| 20879 | case AArch64::ST1D_2Z: |
| 20880 | case AArch64::ST1H_2Z: |
| 20881 | case AArch64::ST1W_2Z: |
| 20882 | case AArch64::STNT1B_2Z: |
| 20883 | case AArch64::STNT1D_2Z: |
| 20884 | case AArch64::STNT1H_2Z: |
| 20885 | case AArch64::STNT1W_2Z: { |
| 20886 | // op: Zt |
| 20887 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 20888 | Value |= (op & 0xf) << 1; |
| 20889 | // op: Rm |
| 20890 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20891 | Value |= (op & 0x1f) << 16; |
| 20892 | // op: Rn |
| 20893 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20894 | Value |= (op & 0x1f) << 5; |
| 20895 | // op: PNg |
| 20896 | op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI); |
| 20897 | Value |= (op & 0x7) << 10; |
| 20898 | break; |
| 20899 | } |
| 20900 | case AArch64::LD1B_2Z_IMM: |
| 20901 | case AArch64::LD1D_2Z_IMM: |
| 20902 | case AArch64::LD1H_2Z_IMM: |
| 20903 | case AArch64::LD1W_2Z_IMM: |
| 20904 | case AArch64::LDNT1B_2Z_IMM: |
| 20905 | case AArch64::LDNT1D_2Z_IMM: |
| 20906 | case AArch64::LDNT1H_2Z_IMM: |
| 20907 | case AArch64::LDNT1W_2Z_IMM: |
| 20908 | case AArch64::ST1B_2Z_IMM: |
| 20909 | case AArch64::ST1D_2Z_IMM: |
| 20910 | case AArch64::ST1H_2Z_IMM: |
| 20911 | case AArch64::ST1W_2Z_IMM: |
| 20912 | case AArch64::STNT1B_2Z_IMM: |
| 20913 | case AArch64::STNT1D_2Z_IMM: |
| 20914 | case AArch64::STNT1H_2Z_IMM: |
| 20915 | case AArch64::STNT1W_2Z_IMM: { |
| 20916 | // op: Zt |
| 20917 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 0, Fixups, STI); |
| 20918 | Value |= (op & 0xf) << 1; |
| 20919 | // op: Rn |
| 20920 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20921 | Value |= (op & 0x1f) << 5; |
| 20922 | // op: PNg |
| 20923 | op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI); |
| 20924 | Value |= (op & 0x7) << 10; |
| 20925 | // op: imm4 |
| 20926 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20927 | Value |= (op & 0xf) << 16; |
| 20928 | break; |
| 20929 | } |
| 20930 | case AArch64::LD1B_4Z: |
| 20931 | case AArch64::LD1D_4Z: |
| 20932 | case AArch64::LD1H_4Z: |
| 20933 | case AArch64::LD1W_4Z: |
| 20934 | case AArch64::LDNT1B_4Z: |
| 20935 | case AArch64::LDNT1D_4Z: |
| 20936 | case AArch64::LDNT1H_4Z: |
| 20937 | case AArch64::LDNT1W_4Z: |
| 20938 | case AArch64::ST1B_4Z: |
| 20939 | case AArch64::ST1D_4Z: |
| 20940 | case AArch64::ST1H_4Z: |
| 20941 | case AArch64::ST1W_4Z: |
| 20942 | case AArch64::STNT1B_4Z: |
| 20943 | case AArch64::STNT1D_4Z: |
| 20944 | case AArch64::STNT1H_4Z: |
| 20945 | case AArch64::STNT1W_4Z: { |
| 20946 | // op: Zt |
| 20947 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 20948 | Value |= (op & 0x7) << 2; |
| 20949 | // op: Rm |
| 20950 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20951 | Value |= (op & 0x1f) << 16; |
| 20952 | // op: Rn |
| 20953 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20954 | Value |= (op & 0x1f) << 5; |
| 20955 | // op: PNg |
| 20956 | op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI); |
| 20957 | Value |= (op & 0x7) << 10; |
| 20958 | break; |
| 20959 | } |
| 20960 | case AArch64::LD1B_4Z_IMM: |
| 20961 | case AArch64::LD1D_4Z_IMM: |
| 20962 | case AArch64::LD1H_4Z_IMM: |
| 20963 | case AArch64::LD1W_4Z_IMM: |
| 20964 | case AArch64::LDNT1B_4Z_IMM: |
| 20965 | case AArch64::LDNT1D_4Z_IMM: |
| 20966 | case AArch64::LDNT1H_4Z_IMM: |
| 20967 | case AArch64::LDNT1W_4Z_IMM: |
| 20968 | case AArch64::ST1B_4Z_IMM: |
| 20969 | case AArch64::ST1D_4Z_IMM: |
| 20970 | case AArch64::ST1H_4Z_IMM: |
| 20971 | case AArch64::ST1W_4Z_IMM: |
| 20972 | case AArch64::STNT1B_4Z_IMM: |
| 20973 | case AArch64::STNT1D_4Z_IMM: |
| 20974 | case AArch64::STNT1H_4Z_IMM: |
| 20975 | case AArch64::STNT1W_4Z_IMM: { |
| 20976 | // op: Zt |
| 20977 | op = EncodeRegMul_MinMax<4, 0, 28>(MI, OpIdx: 0, Fixups, STI); |
| 20978 | Value |= (op & 0x7) << 2; |
| 20979 | // op: Rn |
| 20980 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 20981 | Value |= (op & 0x1f) << 5; |
| 20982 | // op: PNg |
| 20983 | op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI); |
| 20984 | Value |= (op & 0x7) << 10; |
| 20985 | // op: imm4 |
| 20986 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 20987 | Value |= (op & 0xf) << 16; |
| 20988 | break; |
| 20989 | } |
| 20990 | case AArch64::LD1B: |
| 20991 | case AArch64::LD1B_D: |
| 20992 | case AArch64::LD1B_H: |
| 20993 | case AArch64::LD1B_S: |
| 20994 | case AArch64::LD1D: |
| 20995 | case AArch64::LD1H: |
| 20996 | case AArch64::LD1H_D: |
| 20997 | case AArch64::LD1H_S: |
| 20998 | case AArch64::LD1SB_D: |
| 20999 | case AArch64::LD1SB_H: |
| 21000 | case AArch64::LD1SB_S: |
| 21001 | case AArch64::LD1SH_D: |
| 21002 | case AArch64::LD1SH_S: |
| 21003 | case AArch64::LD1SW_D: |
| 21004 | case AArch64::LD1W: |
| 21005 | case AArch64::LD1W_D: |
| 21006 | case AArch64::LDFF1B: |
| 21007 | case AArch64::LDFF1B_D: |
| 21008 | case AArch64::LDFF1B_H: |
| 21009 | case AArch64::LDFF1B_S: |
| 21010 | case AArch64::LDFF1D: |
| 21011 | case AArch64::LDFF1H: |
| 21012 | case AArch64::LDFF1H_D: |
| 21013 | case AArch64::LDFF1H_S: |
| 21014 | case AArch64::LDFF1SB_D: |
| 21015 | case AArch64::LDFF1SB_H: |
| 21016 | case AArch64::LDFF1SB_S: |
| 21017 | case AArch64::LDFF1SH_D: |
| 21018 | case AArch64::LDFF1SH_S: |
| 21019 | case AArch64::LDFF1SW_D: |
| 21020 | case AArch64::LDFF1W: |
| 21021 | case AArch64::LDFF1W_D: { |
| 21022 | // op: Zt |
| 21023 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21024 | Value |= (op & 0x1f); |
| 21025 | // op: Pg |
| 21026 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21027 | Value |= (op & 0x7) << 10; |
| 21028 | // op: Rm |
| 21029 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 21030 | Value |= (op & 0x1f) << 16; |
| 21031 | // op: Rn |
| 21032 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21033 | Value |= (op & 0x1f) << 5; |
| 21034 | break; |
| 21035 | } |
| 21036 | case AArch64::LD1RO_B: |
| 21037 | case AArch64::LD1RO_D: |
| 21038 | case AArch64::LD1RO_H: |
| 21039 | case AArch64::LD1RO_W: |
| 21040 | case AArch64::LD1RQ_B: |
| 21041 | case AArch64::LD1RQ_D: |
| 21042 | case AArch64::LD1RQ_H: |
| 21043 | case AArch64::LD1RQ_W: { |
| 21044 | // op: Zt |
| 21045 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21046 | Value |= (op & 0x1f); |
| 21047 | // op: Pg |
| 21048 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21049 | Value |= (op & 0x7) << 10; |
| 21050 | // op: Rn |
| 21051 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21052 | Value |= (op & 0x1f) << 5; |
| 21053 | // op: Rm |
| 21054 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 21055 | Value |= (op & 0x1f) << 16; |
| 21056 | break; |
| 21057 | } |
| 21058 | case AArch64::LD2B_IMM: |
| 21059 | case AArch64::LD2D_IMM: |
| 21060 | case AArch64::LD2H_IMM: |
| 21061 | case AArch64::LD2Q_IMM: |
| 21062 | case AArch64::LD2W_IMM: |
| 21063 | case AArch64::LD3B_IMM: |
| 21064 | case AArch64::LD3D_IMM: |
| 21065 | case AArch64::LD3H_IMM: |
| 21066 | case AArch64::LD3Q_IMM: |
| 21067 | case AArch64::LD3W_IMM: |
| 21068 | case AArch64::LD4B_IMM: |
| 21069 | case AArch64::LD4D_IMM: |
| 21070 | case AArch64::LD4H_IMM: |
| 21071 | case AArch64::LD4Q_IMM: |
| 21072 | case AArch64::LD4W_IMM: |
| 21073 | case AArch64::LDNT1B_ZRI: |
| 21074 | case AArch64::LDNT1D_ZRI: |
| 21075 | case AArch64::LDNT1H_ZRI: |
| 21076 | case AArch64::LDNT1W_ZRI: { |
| 21077 | // op: Zt |
| 21078 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21079 | Value |= (op & 0x1f); |
| 21080 | // op: Pg |
| 21081 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21082 | Value |= (op & 0x7) << 10; |
| 21083 | // op: Rn |
| 21084 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21085 | Value |= (op & 0x1f) << 5; |
| 21086 | // op: imm4 |
| 21087 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 21088 | Value |= (op & 0xf) << 16; |
| 21089 | break; |
| 21090 | } |
| 21091 | case AArch64::LD1D_Q: |
| 21092 | case AArch64::LD1W_Q: |
| 21093 | case AArch64::ST2Q: |
| 21094 | case AArch64::ST3Q: |
| 21095 | case AArch64::ST4Q: { |
| 21096 | // op: Zt |
| 21097 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21098 | Value |= (op & 0x1f); |
| 21099 | // op: Rn |
| 21100 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21101 | Value |= (op & 0x1f) << 5; |
| 21102 | // op: Pg |
| 21103 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21104 | Value |= (op & 0x7) << 10; |
| 21105 | // op: Rm |
| 21106 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 21107 | Value |= (op & 0x1f) << 16; |
| 21108 | break; |
| 21109 | } |
| 21110 | case AArch64::LD1D_Q_IMM: |
| 21111 | case AArch64::LD1RO_B_IMM: |
| 21112 | case AArch64::LD1RO_D_IMM: |
| 21113 | case AArch64::LD1RO_H_IMM: |
| 21114 | case AArch64::LD1RO_W_IMM: |
| 21115 | case AArch64::LD1RQ_B_IMM: |
| 21116 | case AArch64::LD1RQ_D_IMM: |
| 21117 | case AArch64::LD1RQ_H_IMM: |
| 21118 | case AArch64::LD1RQ_W_IMM: |
| 21119 | case AArch64::LD1W_Q_IMM: |
| 21120 | case AArch64::ST2Q_IMM: |
| 21121 | case AArch64::ST3Q_IMM: |
| 21122 | case AArch64::ST4Q_IMM: { |
| 21123 | // op: Zt |
| 21124 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21125 | Value |= (op & 0x1f); |
| 21126 | // op: Rn |
| 21127 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21128 | Value |= (op & 0x1f) << 5; |
| 21129 | // op: Pg |
| 21130 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21131 | Value |= (op & 0x7) << 10; |
| 21132 | // op: imm4 |
| 21133 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 21134 | Value |= (op & 0xf) << 16; |
| 21135 | break; |
| 21136 | } |
| 21137 | case AArch64::GLD1Q: |
| 21138 | case AArch64::SST1Q: { |
| 21139 | // op: Zt |
| 21140 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21141 | Value |= (op & 0x1f); |
| 21142 | // op: Zn |
| 21143 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21144 | Value |= (op & 0x1f) << 5; |
| 21145 | // op: Pg |
| 21146 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21147 | Value |= (op & 0x7) << 10; |
| 21148 | // op: Rm |
| 21149 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 21150 | Value |= (op & 0x1f) << 16; |
| 21151 | break; |
| 21152 | } |
| 21153 | case AArch64::MOVT_TIZ: { |
| 21154 | // op: Zt |
| 21155 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21156 | Value |= (op & 0x1f); |
| 21157 | // op: off2 |
| 21158 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21159 | Value |= (op & 0x3) << 12; |
| 21160 | break; |
| 21161 | } |
| 21162 | case AArch64::B: |
| 21163 | case AArch64::BL: { |
| 21164 | // op: addr |
| 21165 | op = getBranchTargetOpValue(MI, OpIdx: 0, Fixups, STI); |
| 21166 | Value |= (op & 0x3ffffff); |
| 21167 | break; |
| 21168 | } |
| 21169 | case AArch64::FLTcc: { |
| 21170 | // op: cond |
| 21171 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21172 | Value |= (op & 0xf); |
| 21173 | // op: imm |
| 21174 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21175 | Value |= (op & 0xffff) << 5; |
| 21176 | break; |
| 21177 | } |
| 21178 | case AArch64::BCcc: |
| 21179 | case AArch64::Bcc: { |
| 21180 | // op: cond |
| 21181 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21182 | Value |= (op & 0xf); |
| 21183 | // op: target |
| 21184 | op = getCondBranchTargetOpValue(MI, OpIdx: 1, Fixups, STI); |
| 21185 | Value |= (op & 0x7ffff) << 5; |
| 21186 | break; |
| 21187 | } |
| 21188 | case AArch64::DUPi64: { |
| 21189 | // op: dst |
| 21190 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21191 | Value |= (op & 0x1f); |
| 21192 | // op: src |
| 21193 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21194 | Value |= (op & 0x1f) << 5; |
| 21195 | // op: idx |
| 21196 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21197 | Value |= (op & 0x1) << 20; |
| 21198 | break; |
| 21199 | } |
| 21200 | case AArch64::DUPi32: { |
| 21201 | // op: dst |
| 21202 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21203 | Value |= (op & 0x1f); |
| 21204 | // op: src |
| 21205 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21206 | Value |= (op & 0x1f) << 5; |
| 21207 | // op: idx |
| 21208 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21209 | Value |= (op & 0x3) << 19; |
| 21210 | break; |
| 21211 | } |
| 21212 | case AArch64::DUPi16: { |
| 21213 | // op: dst |
| 21214 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21215 | Value |= (op & 0x1f); |
| 21216 | // op: src |
| 21217 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21218 | Value |= (op & 0x1f) << 5; |
| 21219 | // op: idx |
| 21220 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21221 | Value |= (op & 0x7) << 18; |
| 21222 | break; |
| 21223 | } |
| 21224 | case AArch64::DUPi8: { |
| 21225 | // op: dst |
| 21226 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21227 | Value |= (op & 0x1f); |
| 21228 | // op: src |
| 21229 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21230 | Value |= (op & 0x1f) << 5; |
| 21231 | // op: idx |
| 21232 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21233 | Value |= (op & 0xf) << 17; |
| 21234 | break; |
| 21235 | } |
| 21236 | case AArch64::ZERO_M: { |
| 21237 | // op: imm |
| 21238 | op = EncodeMatrixTileListRegisterClass(MI, OpIdx: 0, Fixups, STI); |
| 21239 | Value |= (op & 0xff); |
| 21240 | break; |
| 21241 | } |
| 21242 | case AArch64::HINT: { |
| 21243 | // op: imm |
| 21244 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21245 | Value |= (op & 0x7f) << 5; |
| 21246 | break; |
| 21247 | } |
| 21248 | case AArch64::TENTER: { |
| 21249 | // op: imm |
| 21250 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21251 | Value |= (op & 0x7f) << 5; |
| 21252 | // op: nb |
| 21253 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21254 | Value |= (op & 0x1) << 17; |
| 21255 | break; |
| 21256 | } |
| 21257 | case AArch64::BRK: |
| 21258 | case AArch64::DCPS1: |
| 21259 | case AArch64::DCPS2: |
| 21260 | case AArch64::DCPS3: |
| 21261 | case AArch64::HLT: |
| 21262 | case AArch64::HVC: |
| 21263 | case AArch64::SMC: |
| 21264 | case AArch64::SVC: { |
| 21265 | // op: imm |
| 21266 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21267 | Value |= (op & 0xffff) << 5; |
| 21268 | break; |
| 21269 | } |
| 21270 | case AArch64::UDF: { |
| 21271 | // op: imm |
| 21272 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21273 | Value |= (op & 0xffff); |
| 21274 | break; |
| 21275 | } |
| 21276 | case AArch64::HINTE: { |
| 21277 | // op: imm16 |
| 21278 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21279 | Value |= (op & 0x8000) << 6; |
| 21280 | Value |= (op & 0x7000) << 4; |
| 21281 | Value |= (op & 0xfff); |
| 21282 | break; |
| 21283 | } |
| 21284 | case AArch64::MOVT_TIX: { |
| 21285 | // op: imm3 |
| 21286 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21287 | Value |= (op & 0x7) << 12; |
| 21288 | // op: Rt |
| 21289 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21290 | Value |= (op & 0x1f); |
| 21291 | break; |
| 21292 | } |
| 21293 | case AArch64::MOVT_XTI: { |
| 21294 | // op: imm3 |
| 21295 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21296 | Value |= (op & 0x7) << 12; |
| 21297 | // op: Rt |
| 21298 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21299 | Value |= (op & 0x1f); |
| 21300 | break; |
| 21301 | } |
| 21302 | case AArch64::LD1B_2Z_STRIDED_IMM: |
| 21303 | case AArch64::LD1D_2Z_STRIDED_IMM: |
| 21304 | case AArch64::LD1H_2Z_STRIDED_IMM: |
| 21305 | case AArch64::LD1W_2Z_STRIDED_IMM: |
| 21306 | case AArch64::LDNT1B_2Z_STRIDED_IMM: |
| 21307 | case AArch64::LDNT1D_2Z_STRIDED_IMM: |
| 21308 | case AArch64::LDNT1H_2Z_STRIDED_IMM: |
| 21309 | case AArch64::LDNT1W_2Z_STRIDED_IMM: |
| 21310 | case AArch64::ST1B_2Z_STRIDED_IMM: |
| 21311 | case AArch64::ST1D_2Z_STRIDED_IMM: |
| 21312 | case AArch64::ST1H_2Z_STRIDED_IMM: |
| 21313 | case AArch64::ST1W_2Z_STRIDED_IMM: |
| 21314 | case AArch64::STNT1B_2Z_STRIDED_IMM: |
| 21315 | case AArch64::STNT1D_2Z_STRIDED_IMM: |
| 21316 | case AArch64::STNT1H_2Z_STRIDED_IMM: |
| 21317 | case AArch64::STNT1W_2Z_STRIDED_IMM: { |
| 21318 | // op: imm4 |
| 21319 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 21320 | Value |= (op & 0xf) << 16; |
| 21321 | // op: PNg |
| 21322 | op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI); |
| 21323 | Value |= (op & 0x7) << 10; |
| 21324 | // op: Rn |
| 21325 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21326 | Value |= (op & 0x1f) << 5; |
| 21327 | // op: Zt |
| 21328 | op = EncodeZPR2StridedRegisterClass(MI, OpIdx: 0, Fixups, STI); |
| 21329 | Value |= (op & 0x8) << 1; |
| 21330 | Value |= (op & 0x7); |
| 21331 | break; |
| 21332 | } |
| 21333 | case AArch64::LD1B_4Z_STRIDED_IMM: |
| 21334 | case AArch64::LD1D_4Z_STRIDED_IMM: |
| 21335 | case AArch64::LD1H_4Z_STRIDED_IMM: |
| 21336 | case AArch64::LD1W_4Z_STRIDED_IMM: |
| 21337 | case AArch64::LDNT1B_4Z_STRIDED_IMM: |
| 21338 | case AArch64::LDNT1D_4Z_STRIDED_IMM: |
| 21339 | case AArch64::LDNT1H_4Z_STRIDED_IMM: |
| 21340 | case AArch64::LDNT1W_4Z_STRIDED_IMM: |
| 21341 | case AArch64::ST1B_4Z_STRIDED_IMM: |
| 21342 | case AArch64::ST1D_4Z_STRIDED_IMM: |
| 21343 | case AArch64::ST1H_4Z_STRIDED_IMM: |
| 21344 | case AArch64::ST1W_4Z_STRIDED_IMM: |
| 21345 | case AArch64::STNT1B_4Z_STRIDED_IMM: |
| 21346 | case AArch64::STNT1D_4Z_STRIDED_IMM: |
| 21347 | case AArch64::STNT1H_4Z_STRIDED_IMM: |
| 21348 | case AArch64::STNT1W_4Z_STRIDED_IMM: { |
| 21349 | // op: imm4 |
| 21350 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 21351 | Value |= (op & 0xf) << 16; |
| 21352 | // op: PNg |
| 21353 | op = EncodePNR_p8to15(MI, OpIdx: 1, Fixups, STI); |
| 21354 | Value |= (op & 0x7) << 10; |
| 21355 | // op: Rn |
| 21356 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21357 | Value |= (op & 0x1f) << 5; |
| 21358 | // op: Zt |
| 21359 | op = EncodeZPR4StridedRegisterClass(MI, OpIdx: 0, Fixups, STI); |
| 21360 | Value |= (op & 0x4) << 2; |
| 21361 | Value |= (op & 0x3); |
| 21362 | break; |
| 21363 | } |
| 21364 | case AArch64::SQRSHRU_VG2_Z2ZI_H: |
| 21365 | case AArch64::SQRSHR_VG2_Z2ZI_H: |
| 21366 | case AArch64::UQRSHR_VG2_Z2ZI_H: { |
| 21367 | // op: imm4 |
| 21368 | op = getVecShiftR16OpValue(MI, OpIdx: 2, Fixups, STI); |
| 21369 | Value |= (op & 0xf) << 16; |
| 21370 | // op: Zn |
| 21371 | op = EncodeRegMul_MinMax<2, 0, 30>(MI, OpIdx: 1, Fixups, STI); |
| 21372 | Value |= (op & 0xf) << 6; |
| 21373 | // op: Zd |
| 21374 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21375 | Value |= (op & 0x1f); |
| 21376 | break; |
| 21377 | } |
| 21378 | case AArch64::AUTIASPPCi: |
| 21379 | case AArch64::AUTIBSPPCi: |
| 21380 | case AArch64::RETAASPPCi: |
| 21381 | case AArch64::RETABSPPCi: { |
| 21382 | // op: label |
| 21383 | op = getPAuthPCRelOpValue(MI, OpIdx: 0, Fixups, STI); |
| 21384 | Value |= (op & 0xffff) << 5; |
| 21385 | break; |
| 21386 | } |
| 21387 | case AArch64::TEXIT: { |
| 21388 | // op: nb |
| 21389 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21390 | Value |= (op & 0x1) << 10; |
| 21391 | break; |
| 21392 | } |
| 21393 | case AArch64::LDRAAindexed: |
| 21394 | case AArch64::LDRABindexed: { |
| 21395 | // op: offset |
| 21396 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21397 | Value |= (op & 0x200) << 13; |
| 21398 | Value |= (op & 0x1ff) << 12; |
| 21399 | // op: Rn |
| 21400 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21401 | Value |= (op & 0x1f) << 5; |
| 21402 | // op: Rt |
| 21403 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21404 | Value |= (op & 0x1f); |
| 21405 | break; |
| 21406 | } |
| 21407 | case AArch64::LDRAAwriteback: |
| 21408 | case AArch64::LDRABwriteback: { |
| 21409 | // op: offset |
| 21410 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 21411 | Value |= (op & 0x200) << 13; |
| 21412 | Value |= (op & 0x1ff) << 12; |
| 21413 | // op: Rn |
| 21414 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21415 | Value |= (op & 0x1f) << 5; |
| 21416 | // op: Rt |
| 21417 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21418 | Value |= (op & 0x1f); |
| 21419 | break; |
| 21420 | } |
| 21421 | case AArch64::SYSPxt_XZR: { |
| 21422 | // op: op1 |
| 21423 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21424 | Value |= (op & 0x7) << 16; |
| 21425 | // op: Cn |
| 21426 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21427 | Value |= (op & 0xf) << 12; |
| 21428 | // op: Cm |
| 21429 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21430 | Value |= (op & 0xf) << 8; |
| 21431 | // op: op2 |
| 21432 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 3), Fixups, STI); |
| 21433 | Value |= (op & 0x7) << 5; |
| 21434 | break; |
| 21435 | } |
| 21436 | case AArch64::MSRpstateImm1: { |
| 21437 | // op: pstatefield |
| 21438 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21439 | Value |= (op & 0x38) << 13; |
| 21440 | Value |= (op & 0x1c0) << 3; |
| 21441 | Value |= (op & 0x7) << 5; |
| 21442 | // op: imm |
| 21443 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21444 | Value |= (op & 0x1) << 8; |
| 21445 | break; |
| 21446 | } |
| 21447 | case AArch64::MSRpstateImm4: { |
| 21448 | // op: pstatefield |
| 21449 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21450 | Value |= (op & 0x38) << 13; |
| 21451 | Value |= (op & 0x7) << 5; |
| 21452 | // op: imm |
| 21453 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21454 | Value |= (op & 0xf) << 8; |
| 21455 | break; |
| 21456 | } |
| 21457 | case AArch64::MSRpstatesvcrImm1: { |
| 21458 | // op: pstatefield |
| 21459 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21460 | Value |= (op & 0x7) << 9; |
| 21461 | // op: imm |
| 21462 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21463 | Value |= (op & 0x1) << 8; |
| 21464 | break; |
| 21465 | } |
| 21466 | case AArch64::CFLTEQWr: |
| 21467 | case AArch64::CFLTEQXr: |
| 21468 | case AArch64::CFLTGEWr: |
| 21469 | case AArch64::CFLTGEXr: |
| 21470 | case AArch64::CFLTGTWr: |
| 21471 | case AArch64::CFLTGTXr: |
| 21472 | case AArch64::CFLTHIWr: |
| 21473 | case AArch64::CFLTHIXr: |
| 21474 | case AArch64::CFLTHSWr: |
| 21475 | case AArch64::CFLTHSXr: |
| 21476 | case AArch64::CFLTNEWr: |
| 21477 | case AArch64::CFLTNEXr: { |
| 21478 | // op: reason |
| 21479 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21480 | Value |= (op & 0x3) << 10; |
| 21481 | // op: Rt |
| 21482 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21483 | Value |= (op & 0x1f); |
| 21484 | // op: Rm |
| 21485 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21486 | Value |= (op & 0x1f) << 16; |
| 21487 | break; |
| 21488 | } |
| 21489 | case AArch64::TFLTNZ: |
| 21490 | case AArch64::TFLTZ: { |
| 21491 | // op: reason |
| 21492 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21493 | Value |= (op & 0x3) << 10; |
| 21494 | // op: Rt |
| 21495 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21496 | Value |= (op & 0x1f); |
| 21497 | // op: bit_off |
| 21498 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21499 | Value |= (op & 0x20) << 26; |
| 21500 | Value |= (op & 0x1f) << 19; |
| 21501 | break; |
| 21502 | } |
| 21503 | case AArch64::CFLTEQWi: |
| 21504 | case AArch64::CFLTEQXi: |
| 21505 | case AArch64::CFLTGTWi: |
| 21506 | case AArch64::CFLTGTXi: |
| 21507 | case AArch64::CFLTHIWi: |
| 21508 | case AArch64::CFLTHIXi: |
| 21509 | case AArch64::CFLTLOWi: |
| 21510 | case AArch64::CFLTLOXi: |
| 21511 | case AArch64::CFLTLTWi: |
| 21512 | case AArch64::CFLTLTXi: |
| 21513 | case AArch64::CFLTNEWi: |
| 21514 | case AArch64::CFLTNEXi: { |
| 21515 | // op: reason |
| 21516 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 0), Fixups, STI); |
| 21517 | Value |= (op & 0x3) << 10; |
| 21518 | // op: Rt |
| 21519 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 1), Fixups, STI); |
| 21520 | Value |= (op & 0x1f); |
| 21521 | // op: imm |
| 21522 | op = getMachineOpValue(MI, MO: MI.getOperand(i: 2), Fixups, STI); |
| 21523 | Value |= (op & 0x1f0) << 12; |
| 21524 | Value |= (op & 0xf) << 5; |
| 21525 | break; |
| 21526 | } |
| 21527 | default: |
| 21528 | reportUnsupportedInst(Inst: MI); |
| 21529 | } |
| 21530 | return Value; |
| 21531 | } |
| 21532 | |
| 21533 | #ifdef GET_OPERAND_BIT_OFFSET |
| 21534 | #undef GET_OPERAND_BIT_OFFSET |
| 21535 | |
| 21536 | uint32_t AArch64MCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
| 21537 | unsigned OpNum, |
| 21538 | const MCSubtargetInfo &STI) const { |
| 21539 | switch (MI.getOpcode()) { |
| 21540 | case AArch64::AUTIA1716: |
| 21541 | case AArch64::AUTIA171615: |
| 21542 | case AArch64::AUTIASP: |
| 21543 | case AArch64::AUTIAZ: |
| 21544 | case AArch64::AUTIB1716: |
| 21545 | case AArch64::AUTIB171615: |
| 21546 | case AArch64::AUTIBSP: |
| 21547 | case AArch64::AUTIBZ: |
| 21548 | case AArch64::AXFLAG: |
| 21549 | case AArch64::CFINV: |
| 21550 | case AArch64::CHKFEAT: |
| 21551 | case AArch64::DRPS: |
| 21552 | case AArch64::ERET: |
| 21553 | case AArch64::ERETAA: |
| 21554 | case AArch64::ERETAB: |
| 21555 | case AArch64::GCSPOPCX: |
| 21556 | case AArch64::GCSPOPX: |
| 21557 | case AArch64::GCSPUSHX: |
| 21558 | case AArch64::NOP: |
| 21559 | case AArch64::PACIA1716: |
| 21560 | case AArch64::PACIA171615: |
| 21561 | case AArch64::PACIASP: |
| 21562 | case AArch64::PACIASPPC: |
| 21563 | case AArch64::PACIAZ: |
| 21564 | case AArch64::PACIB1716: |
| 21565 | case AArch64::PACIB171615: |
| 21566 | case AArch64::PACIBSP: |
| 21567 | case AArch64::PACIBSPPC: |
| 21568 | case AArch64::PACIBZ: |
| 21569 | case AArch64::PACM: |
| 21570 | case AArch64::PACNBIASPPC: |
| 21571 | case AArch64::PACNBIBSPPC: |
| 21572 | case AArch64::RETAA: |
| 21573 | case AArch64::RETAB: |
| 21574 | case AArch64::SB: |
| 21575 | case AArch64::SETFFR: |
| 21576 | case AArch64::XAFLAG: |
| 21577 | case AArch64::XPACLRI: |
| 21578 | case AArch64::ZERO_T: { |
| 21579 | break; |
| 21580 | } |
| 21581 | case AArch64::DSBnXS: { |
| 21582 | switch (OpNum) { |
| 21583 | case 0: |
| 21584 | // op: CRm |
| 21585 | return 10; |
| 21586 | } |
| 21587 | break; |
| 21588 | } |
| 21589 | case AArch64::CLREX: |
| 21590 | case AArch64::DMB: |
| 21591 | case AArch64::DSB: |
| 21592 | case AArch64::ISB: { |
| 21593 | switch (OpNum) { |
| 21594 | case 0: |
| 21595 | // op: CRm |
| 21596 | return 8; |
| 21597 | } |
| 21598 | break; |
| 21599 | } |
| 21600 | case AArch64::WHILEGE_CXX_B: |
| 21601 | case AArch64::WHILEGE_CXX_D: |
| 21602 | case AArch64::WHILEGE_CXX_H: |
| 21603 | case AArch64::WHILEGE_CXX_S: |
| 21604 | case AArch64::WHILEGT_CXX_B: |
| 21605 | case AArch64::WHILEGT_CXX_D: |
| 21606 | case AArch64::WHILEGT_CXX_H: |
| 21607 | case AArch64::WHILEGT_CXX_S: |
| 21608 | case AArch64::WHILEHI_CXX_B: |
| 21609 | case AArch64::WHILEHI_CXX_D: |
| 21610 | case AArch64::WHILEHI_CXX_H: |
| 21611 | case AArch64::WHILEHI_CXX_S: |
| 21612 | case AArch64::WHILEHS_CXX_B: |
| 21613 | case AArch64::WHILEHS_CXX_D: |
| 21614 | case AArch64::WHILEHS_CXX_H: |
| 21615 | case AArch64::WHILEHS_CXX_S: |
| 21616 | case AArch64::WHILELE_CXX_B: |
| 21617 | case AArch64::WHILELE_CXX_D: |
| 21618 | case AArch64::WHILELE_CXX_H: |
| 21619 | case AArch64::WHILELE_CXX_S: |
| 21620 | case AArch64::WHILELO_CXX_B: |
| 21621 | case AArch64::WHILELO_CXX_D: |
| 21622 | case AArch64::WHILELO_CXX_H: |
| 21623 | case AArch64::WHILELO_CXX_S: |
| 21624 | case AArch64::WHILELS_CXX_B: |
| 21625 | case AArch64::WHILELS_CXX_D: |
| 21626 | case AArch64::WHILELS_CXX_H: |
| 21627 | case AArch64::WHILELS_CXX_S: |
| 21628 | case AArch64::WHILELT_CXX_B: |
| 21629 | case AArch64::WHILELT_CXX_D: |
| 21630 | case AArch64::WHILELT_CXX_H: |
| 21631 | case AArch64::WHILELT_CXX_S: { |
| 21632 | switch (OpNum) { |
| 21633 | case 0: |
| 21634 | // op: PNd |
| 21635 | return 0; |
| 21636 | case 1: |
| 21637 | // op: Rn |
| 21638 | return 5; |
| 21639 | case 3: |
| 21640 | // op: vl |
| 21641 | return 13; |
| 21642 | case 2: |
| 21643 | // op: Rm |
| 21644 | return 16; |
| 21645 | } |
| 21646 | break; |
| 21647 | } |
| 21648 | case AArch64::PTRUE_C_B: |
| 21649 | case AArch64::PTRUE_C_D: |
| 21650 | case AArch64::PTRUE_C_H: |
| 21651 | case AArch64::PTRUE_C_S: { |
| 21652 | switch (OpNum) { |
| 21653 | case 0: |
| 21654 | // op: PNd |
| 21655 | return 0; |
| 21656 | } |
| 21657 | break; |
| 21658 | } |
| 21659 | case AArch64::PEXT_2PCI_B: |
| 21660 | case AArch64::PEXT_2PCI_D: |
| 21661 | case AArch64::PEXT_2PCI_H: |
| 21662 | case AArch64::PEXT_2PCI_S: |
| 21663 | case AArch64::PEXT_PCI_B: |
| 21664 | case AArch64::PEXT_PCI_D: |
| 21665 | case AArch64::PEXT_PCI_H: |
| 21666 | case AArch64::PEXT_PCI_S: { |
| 21667 | switch (OpNum) { |
| 21668 | case 0: |
| 21669 | // op: Pd |
| 21670 | return 0; |
| 21671 | case 1: |
| 21672 | // op: PNn |
| 21673 | return 5; |
| 21674 | case 2: |
| 21675 | // op: index |
| 21676 | return 8; |
| 21677 | } |
| 21678 | break; |
| 21679 | } |
| 21680 | case AArch64::BRKAS_PPzP: |
| 21681 | case AArch64::BRKA_PPzP: |
| 21682 | case AArch64::BRKBS_PPzP: |
| 21683 | case AArch64::BRKB_PPzP: { |
| 21684 | switch (OpNum) { |
| 21685 | case 0: |
| 21686 | // op: Pd |
| 21687 | return 0; |
| 21688 | case 1: |
| 21689 | // op: Pg |
| 21690 | return 10; |
| 21691 | case 2: |
| 21692 | // op: Pn |
| 21693 | return 5; |
| 21694 | } |
| 21695 | break; |
| 21696 | } |
| 21697 | case AArch64::CMPEQ_PPzZI_B: |
| 21698 | case AArch64::CMPEQ_PPzZI_D: |
| 21699 | case AArch64::CMPEQ_PPzZI_H: |
| 21700 | case AArch64::CMPEQ_PPzZI_S: |
| 21701 | case AArch64::CMPGE_PPzZI_B: |
| 21702 | case AArch64::CMPGE_PPzZI_D: |
| 21703 | case AArch64::CMPGE_PPzZI_H: |
| 21704 | case AArch64::CMPGE_PPzZI_S: |
| 21705 | case AArch64::CMPGT_PPzZI_B: |
| 21706 | case AArch64::CMPGT_PPzZI_D: |
| 21707 | case AArch64::CMPGT_PPzZI_H: |
| 21708 | case AArch64::CMPGT_PPzZI_S: |
| 21709 | case AArch64::CMPLE_PPzZI_B: |
| 21710 | case AArch64::CMPLE_PPzZI_D: |
| 21711 | case AArch64::CMPLE_PPzZI_H: |
| 21712 | case AArch64::CMPLE_PPzZI_S: |
| 21713 | case AArch64::CMPLT_PPzZI_B: |
| 21714 | case AArch64::CMPLT_PPzZI_D: |
| 21715 | case AArch64::CMPLT_PPzZI_H: |
| 21716 | case AArch64::CMPLT_PPzZI_S: |
| 21717 | case AArch64::CMPNE_PPzZI_B: |
| 21718 | case AArch64::CMPNE_PPzZI_D: |
| 21719 | case AArch64::CMPNE_PPzZI_H: |
| 21720 | case AArch64::CMPNE_PPzZI_S: { |
| 21721 | switch (OpNum) { |
| 21722 | case 0: |
| 21723 | // op: Pd |
| 21724 | return 0; |
| 21725 | case 1: |
| 21726 | // op: Pg |
| 21727 | return 10; |
| 21728 | case 2: |
| 21729 | // op: Zn |
| 21730 | return 5; |
| 21731 | case 3: |
| 21732 | // op: imm5 |
| 21733 | return 16; |
| 21734 | } |
| 21735 | break; |
| 21736 | } |
| 21737 | case AArch64::CMPHI_PPzZI_B: |
| 21738 | case AArch64::CMPHI_PPzZI_D: |
| 21739 | case AArch64::CMPHI_PPzZI_H: |
| 21740 | case AArch64::CMPHI_PPzZI_S: |
| 21741 | case AArch64::CMPHS_PPzZI_B: |
| 21742 | case AArch64::CMPHS_PPzZI_D: |
| 21743 | case AArch64::CMPHS_PPzZI_H: |
| 21744 | case AArch64::CMPHS_PPzZI_S: |
| 21745 | case AArch64::CMPLO_PPzZI_B: |
| 21746 | case AArch64::CMPLO_PPzZI_D: |
| 21747 | case AArch64::CMPLO_PPzZI_H: |
| 21748 | case AArch64::CMPLO_PPzZI_S: |
| 21749 | case AArch64::CMPLS_PPzZI_B: |
| 21750 | case AArch64::CMPLS_PPzZI_D: |
| 21751 | case AArch64::CMPLS_PPzZI_H: |
| 21752 | case AArch64::CMPLS_PPzZI_S: { |
| 21753 | switch (OpNum) { |
| 21754 | case 0: |
| 21755 | // op: Pd |
| 21756 | return 0; |
| 21757 | case 1: |
| 21758 | // op: Pg |
| 21759 | return 10; |
| 21760 | case 2: |
| 21761 | // op: Zn |
| 21762 | return 5; |
| 21763 | case 3: |
| 21764 | // op: imm7 |
| 21765 | return 14; |
| 21766 | } |
| 21767 | break; |
| 21768 | } |
| 21769 | case AArch64::FCMEQ_PPzZ0_D: |
| 21770 | case AArch64::FCMEQ_PPzZ0_H: |
| 21771 | case AArch64::FCMEQ_PPzZ0_S: |
| 21772 | case AArch64::FCMGE_PPzZ0_D: |
| 21773 | case AArch64::FCMGE_PPzZ0_H: |
| 21774 | case AArch64::FCMGE_PPzZ0_S: |
| 21775 | case AArch64::FCMGT_PPzZ0_D: |
| 21776 | case AArch64::FCMGT_PPzZ0_H: |
| 21777 | case AArch64::FCMGT_PPzZ0_S: |
| 21778 | case AArch64::FCMLE_PPzZ0_D: |
| 21779 | case AArch64::FCMLE_PPzZ0_H: |
| 21780 | case AArch64::FCMLE_PPzZ0_S: |
| 21781 | case AArch64::FCMLT_PPzZ0_D: |
| 21782 | case AArch64::FCMLT_PPzZ0_H: |
| 21783 | case AArch64::FCMLT_PPzZ0_S: |
| 21784 | case AArch64::FCMNE_PPzZ0_D: |
| 21785 | case AArch64::FCMNE_PPzZ0_H: |
| 21786 | case AArch64::FCMNE_PPzZ0_S: { |
| 21787 | switch (OpNum) { |
| 21788 | case 0: |
| 21789 | // op: Pd |
| 21790 | return 0; |
| 21791 | case 1: |
| 21792 | // op: Pg |
| 21793 | return 10; |
| 21794 | case 2: |
| 21795 | // op: Zn |
| 21796 | return 5; |
| 21797 | } |
| 21798 | break; |
| 21799 | } |
| 21800 | case AArch64::ANDS_PPzPP: |
| 21801 | case AArch64::AND_PPzPP: |
| 21802 | case AArch64::BICS_PPzPP: |
| 21803 | case AArch64::BIC_PPzPP: |
| 21804 | case AArch64::BRKPAS_PPzPP: |
| 21805 | case AArch64::BRKPA_PPzPP: |
| 21806 | case AArch64::BRKPBS_PPzPP: |
| 21807 | case AArch64::BRKPB_PPzPP: |
| 21808 | case AArch64::EORS_PPzPP: |
| 21809 | case AArch64::EOR_PPzPP: |
| 21810 | case AArch64::NANDS_PPzPP: |
| 21811 | case AArch64::NAND_PPzPP: |
| 21812 | case AArch64::NORS_PPzPP: |
| 21813 | case AArch64::NOR_PPzPP: |
| 21814 | case AArch64::ORNS_PPzPP: |
| 21815 | case AArch64::ORN_PPzPP: |
| 21816 | case AArch64::ORRS_PPzPP: |
| 21817 | case AArch64::ORR_PPzPP: |
| 21818 | case AArch64::SEL_PPPP: { |
| 21819 | switch (OpNum) { |
| 21820 | case 0: |
| 21821 | // op: Pd |
| 21822 | return 0; |
| 21823 | case 1: |
| 21824 | // op: Pg |
| 21825 | return 10; |
| 21826 | case 3: |
| 21827 | // op: Pm |
| 21828 | return 16; |
| 21829 | case 2: |
| 21830 | // op: Pn |
| 21831 | return 5; |
| 21832 | } |
| 21833 | break; |
| 21834 | } |
| 21835 | case AArch64::CMPEQ_PPzZZ_B: |
| 21836 | case AArch64::CMPEQ_PPzZZ_D: |
| 21837 | case AArch64::CMPEQ_PPzZZ_H: |
| 21838 | case AArch64::CMPEQ_PPzZZ_S: |
| 21839 | case AArch64::CMPEQ_WIDE_PPzZZ_B: |
| 21840 | case AArch64::CMPEQ_WIDE_PPzZZ_H: |
| 21841 | case AArch64::CMPEQ_WIDE_PPzZZ_S: |
| 21842 | case AArch64::CMPGE_PPzZZ_B: |
| 21843 | case AArch64::CMPGE_PPzZZ_D: |
| 21844 | case AArch64::CMPGE_PPzZZ_H: |
| 21845 | case AArch64::CMPGE_PPzZZ_S: |
| 21846 | case AArch64::CMPGE_WIDE_PPzZZ_B: |
| 21847 | case AArch64::CMPGE_WIDE_PPzZZ_H: |
| 21848 | case AArch64::CMPGE_WIDE_PPzZZ_S: |
| 21849 | case AArch64::CMPGT_PPzZZ_B: |
| 21850 | case AArch64::CMPGT_PPzZZ_D: |
| 21851 | case AArch64::CMPGT_PPzZZ_H: |
| 21852 | case AArch64::CMPGT_PPzZZ_S: |
| 21853 | case AArch64::CMPGT_WIDE_PPzZZ_B: |
| 21854 | case AArch64::CMPGT_WIDE_PPzZZ_H: |
| 21855 | case AArch64::CMPGT_WIDE_PPzZZ_S: |
| 21856 | case AArch64::CMPHI_PPzZZ_B: |
| 21857 | case AArch64::CMPHI_PPzZZ_D: |
| 21858 | case AArch64::CMPHI_PPzZZ_H: |
| 21859 | case AArch64::CMPHI_PPzZZ_S: |
| 21860 | case AArch64::CMPHI_WIDE_PPzZZ_B: |
| 21861 | case AArch64::CMPHI_WIDE_PPzZZ_H: |
| 21862 | case AArch64::CMPHI_WIDE_PPzZZ_S: |
| 21863 | case AArch64::CMPHS_PPzZZ_B: |
| 21864 | case AArch64::CMPHS_PPzZZ_D: |
| 21865 | case AArch64::CMPHS_PPzZZ_H: |
| 21866 | case AArch64::CMPHS_PPzZZ_S: |
| 21867 | case AArch64::CMPHS_WIDE_PPzZZ_B: |
| 21868 | case AArch64::CMPHS_WIDE_PPzZZ_H: |
| 21869 | case AArch64::CMPHS_WIDE_PPzZZ_S: |
| 21870 | case AArch64::CMPLE_WIDE_PPzZZ_B: |
| 21871 | case AArch64::CMPLE_WIDE_PPzZZ_H: |
| 21872 | case AArch64::CMPLE_WIDE_PPzZZ_S: |
| 21873 | case AArch64::CMPLO_WIDE_PPzZZ_B: |
| 21874 | case AArch64::CMPLO_WIDE_PPzZZ_H: |
| 21875 | case AArch64::CMPLO_WIDE_PPzZZ_S: |
| 21876 | case AArch64::CMPLS_WIDE_PPzZZ_B: |
| 21877 | case AArch64::CMPLS_WIDE_PPzZZ_H: |
| 21878 | case AArch64::CMPLS_WIDE_PPzZZ_S: |
| 21879 | case AArch64::CMPLT_WIDE_PPzZZ_B: |
| 21880 | case AArch64::CMPLT_WIDE_PPzZZ_H: |
| 21881 | case AArch64::CMPLT_WIDE_PPzZZ_S: |
| 21882 | case AArch64::CMPNE_PPzZZ_B: |
| 21883 | case AArch64::CMPNE_PPzZZ_D: |
| 21884 | case AArch64::CMPNE_PPzZZ_H: |
| 21885 | case AArch64::CMPNE_PPzZZ_S: |
| 21886 | case AArch64::CMPNE_WIDE_PPzZZ_B: |
| 21887 | case AArch64::CMPNE_WIDE_PPzZZ_H: |
| 21888 | case AArch64::CMPNE_WIDE_PPzZZ_S: |
| 21889 | case AArch64::FACGE_PPzZZ_D: |
| 21890 | case AArch64::FACGE_PPzZZ_H: |
| 21891 | case AArch64::FACGE_PPzZZ_S: |
| 21892 | case AArch64::FACGT_PPzZZ_D: |
| 21893 | case AArch64::FACGT_PPzZZ_H: |
| 21894 | case AArch64::FACGT_PPzZZ_S: |
| 21895 | case AArch64::FCMEQ_PPzZZ_D: |
| 21896 | case AArch64::FCMEQ_PPzZZ_H: |
| 21897 | case AArch64::FCMEQ_PPzZZ_S: |
| 21898 | case AArch64::FCMGE_PPzZZ_D: |
| 21899 | case AArch64::FCMGE_PPzZZ_H: |
| 21900 | case AArch64::FCMGE_PPzZZ_S: |
| 21901 | case AArch64::FCMGT_PPzZZ_D: |
| 21902 | case AArch64::FCMGT_PPzZZ_H: |
| 21903 | case AArch64::FCMGT_PPzZZ_S: |
| 21904 | case AArch64::FCMNE_PPzZZ_D: |
| 21905 | case AArch64::FCMNE_PPzZZ_H: |
| 21906 | case AArch64::FCMNE_PPzZZ_S: |
| 21907 | case AArch64::FCMUO_PPzZZ_D: |
| 21908 | case AArch64::FCMUO_PPzZZ_H: |
| 21909 | case AArch64::FCMUO_PPzZZ_S: |
| 21910 | case AArch64::MATCH_PPzZZ_B: |
| 21911 | case AArch64::MATCH_PPzZZ_H: |
| 21912 | case AArch64::NMATCH_PPzZZ_B: |
| 21913 | case AArch64::NMATCH_PPzZZ_H: { |
| 21914 | switch (OpNum) { |
| 21915 | case 0: |
| 21916 | // op: Pd |
| 21917 | return 0; |
| 21918 | case 1: |
| 21919 | // op: Pg |
| 21920 | return 10; |
| 21921 | case 3: |
| 21922 | // op: Zm |
| 21923 | return 16; |
| 21924 | case 2: |
| 21925 | // op: Zn |
| 21926 | return 5; |
| 21927 | } |
| 21928 | break; |
| 21929 | } |
| 21930 | case AArch64::RDFFRS_PPz: |
| 21931 | case AArch64::RDFFR_PPz: { |
| 21932 | switch (OpNum) { |
| 21933 | case 0: |
| 21934 | // op: Pd |
| 21935 | return 0; |
| 21936 | case 1: |
| 21937 | // op: Pg |
| 21938 | return 5; |
| 21939 | } |
| 21940 | break; |
| 21941 | } |
| 21942 | case AArch64::PUNPKHI_PP: |
| 21943 | case AArch64::PUNPKLO_PP: |
| 21944 | case AArch64::REV_PP_B: |
| 21945 | case AArch64::REV_PP_D: |
| 21946 | case AArch64::REV_PP_H: |
| 21947 | case AArch64::REV_PP_S: { |
| 21948 | switch (OpNum) { |
| 21949 | case 0: |
| 21950 | // op: Pd |
| 21951 | return 0; |
| 21952 | case 1: |
| 21953 | // op: Pn |
| 21954 | return 5; |
| 21955 | } |
| 21956 | break; |
| 21957 | } |
| 21958 | case AArch64::PMOV_PZI_D: |
| 21959 | case AArch64::PMOV_PZI_H: |
| 21960 | case AArch64::PMOV_PZI_S: { |
| 21961 | switch (OpNum) { |
| 21962 | case 0: |
| 21963 | // op: Pd |
| 21964 | return 0; |
| 21965 | case 1: |
| 21966 | // op: Zn |
| 21967 | return 5; |
| 21968 | case 2: |
| 21969 | // op: index |
| 21970 | return 17; |
| 21971 | } |
| 21972 | break; |
| 21973 | } |
| 21974 | case AArch64::PMOV_PZI_B: { |
| 21975 | switch (OpNum) { |
| 21976 | case 0: |
| 21977 | // op: Pd |
| 21978 | return 0; |
| 21979 | case 1: |
| 21980 | // op: Zn |
| 21981 | return 5; |
| 21982 | } |
| 21983 | break; |
| 21984 | } |
| 21985 | case AArch64::PTRUES_B: |
| 21986 | case AArch64::PTRUES_D: |
| 21987 | case AArch64::PTRUES_H: |
| 21988 | case AArch64::PTRUES_S: |
| 21989 | case AArch64::PTRUE_B: |
| 21990 | case AArch64::PTRUE_D: |
| 21991 | case AArch64::PTRUE_H: |
| 21992 | case AArch64::PTRUE_S: { |
| 21993 | switch (OpNum) { |
| 21994 | case 0: |
| 21995 | // op: Pd |
| 21996 | return 0; |
| 21997 | case 1: |
| 21998 | // op: pattern |
| 21999 | return 5; |
| 22000 | } |
| 22001 | break; |
| 22002 | } |
| 22003 | case AArch64::BRKA_PPmP: |
| 22004 | case AArch64::BRKB_PPmP: { |
| 22005 | switch (OpNum) { |
| 22006 | case 0: |
| 22007 | // op: Pd |
| 22008 | return 0; |
| 22009 | case 2: |
| 22010 | // op: Pg |
| 22011 | return 10; |
| 22012 | case 3: |
| 22013 | // op: Pn |
| 22014 | return 5; |
| 22015 | } |
| 22016 | break; |
| 22017 | } |
| 22018 | case AArch64::TRN1_PPP_B: |
| 22019 | case AArch64::TRN1_PPP_D: |
| 22020 | case AArch64::TRN1_PPP_H: |
| 22021 | case AArch64::TRN1_PPP_S: |
| 22022 | case AArch64::TRN2_PPP_B: |
| 22023 | case AArch64::TRN2_PPP_D: |
| 22024 | case AArch64::TRN2_PPP_H: |
| 22025 | case AArch64::TRN2_PPP_S: |
| 22026 | case AArch64::UZP1_PPP_B: |
| 22027 | case AArch64::UZP1_PPP_D: |
| 22028 | case AArch64::UZP1_PPP_H: |
| 22029 | case AArch64::UZP1_PPP_S: |
| 22030 | case AArch64::UZP2_PPP_B: |
| 22031 | case AArch64::UZP2_PPP_D: |
| 22032 | case AArch64::UZP2_PPP_H: |
| 22033 | case AArch64::UZP2_PPP_S: |
| 22034 | case AArch64::ZIP1_PPP_B: |
| 22035 | case AArch64::ZIP1_PPP_D: |
| 22036 | case AArch64::ZIP1_PPP_H: |
| 22037 | case AArch64::ZIP1_PPP_S: |
| 22038 | case AArch64::ZIP2_PPP_B: |
| 22039 | case AArch64::ZIP2_PPP_D: |
| 22040 | case AArch64::ZIP2_PPP_H: |
| 22041 | case AArch64::ZIP2_PPP_S: { |
| 22042 | switch (OpNum) { |
| 22043 | case 0: |
| 22044 | // op: Pd |
| 22045 | return 0; |
| 22046 | case 2: |
| 22047 | // op: Pm |
| 22048 | return 16; |
| 22049 | case 1: |
| 22050 | // op: Pn |
| 22051 | return 5; |
| 22052 | } |
| 22053 | break; |
| 22054 | } |
| 22055 | case AArch64::WHILEGE_PWW_B: |
| 22056 | case AArch64::WHILEGE_PWW_D: |
| 22057 | case AArch64::WHILEGE_PWW_H: |
| 22058 | case AArch64::WHILEGE_PWW_S: |
| 22059 | case AArch64::WHILEGE_PXX_B: |
| 22060 | case AArch64::WHILEGE_PXX_D: |
| 22061 | case AArch64::WHILEGE_PXX_H: |
| 22062 | case AArch64::WHILEGE_PXX_S: |
| 22063 | case AArch64::WHILEGT_PWW_B: |
| 22064 | case AArch64::WHILEGT_PWW_D: |
| 22065 | case AArch64::WHILEGT_PWW_H: |
| 22066 | case AArch64::WHILEGT_PWW_S: |
| 22067 | case AArch64::WHILEGT_PXX_B: |
| 22068 | case AArch64::WHILEGT_PXX_D: |
| 22069 | case AArch64::WHILEGT_PXX_H: |
| 22070 | case AArch64::WHILEGT_PXX_S: |
| 22071 | case AArch64::WHILEHI_PWW_B: |
| 22072 | case AArch64::WHILEHI_PWW_D: |
| 22073 | case AArch64::WHILEHI_PWW_H: |
| 22074 | case AArch64::WHILEHI_PWW_S: |
| 22075 | case AArch64::WHILEHI_PXX_B: |
| 22076 | case AArch64::WHILEHI_PXX_D: |
| 22077 | case AArch64::WHILEHI_PXX_H: |
| 22078 | case AArch64::WHILEHI_PXX_S: |
| 22079 | case AArch64::WHILEHS_PWW_B: |
| 22080 | case AArch64::WHILEHS_PWW_D: |
| 22081 | case AArch64::WHILEHS_PWW_H: |
| 22082 | case AArch64::WHILEHS_PWW_S: |
| 22083 | case AArch64::WHILEHS_PXX_B: |
| 22084 | case AArch64::WHILEHS_PXX_D: |
| 22085 | case AArch64::WHILEHS_PXX_H: |
| 22086 | case AArch64::WHILEHS_PXX_S: |
| 22087 | case AArch64::WHILELE_PWW_B: |
| 22088 | case AArch64::WHILELE_PWW_D: |
| 22089 | case AArch64::WHILELE_PWW_H: |
| 22090 | case AArch64::WHILELE_PWW_S: |
| 22091 | case AArch64::WHILELE_PXX_B: |
| 22092 | case AArch64::WHILELE_PXX_D: |
| 22093 | case AArch64::WHILELE_PXX_H: |
| 22094 | case AArch64::WHILELE_PXX_S: |
| 22095 | case AArch64::WHILELO_PWW_B: |
| 22096 | case AArch64::WHILELO_PWW_D: |
| 22097 | case AArch64::WHILELO_PWW_H: |
| 22098 | case AArch64::WHILELO_PWW_S: |
| 22099 | case AArch64::WHILELO_PXX_B: |
| 22100 | case AArch64::WHILELO_PXX_D: |
| 22101 | case AArch64::WHILELO_PXX_H: |
| 22102 | case AArch64::WHILELO_PXX_S: |
| 22103 | case AArch64::WHILELS_PWW_B: |
| 22104 | case AArch64::WHILELS_PWW_D: |
| 22105 | case AArch64::WHILELS_PWW_H: |
| 22106 | case AArch64::WHILELS_PWW_S: |
| 22107 | case AArch64::WHILELS_PXX_B: |
| 22108 | case AArch64::WHILELS_PXX_D: |
| 22109 | case AArch64::WHILELS_PXX_H: |
| 22110 | case AArch64::WHILELS_PXX_S: |
| 22111 | case AArch64::WHILELT_PWW_B: |
| 22112 | case AArch64::WHILELT_PWW_D: |
| 22113 | case AArch64::WHILELT_PWW_H: |
| 22114 | case AArch64::WHILELT_PWW_S: |
| 22115 | case AArch64::WHILELT_PXX_B: |
| 22116 | case AArch64::WHILELT_PXX_D: |
| 22117 | case AArch64::WHILELT_PXX_H: |
| 22118 | case AArch64::WHILELT_PXX_S: |
| 22119 | case AArch64::WHILERW_PXX_B: |
| 22120 | case AArch64::WHILERW_PXX_D: |
| 22121 | case AArch64::WHILERW_PXX_H: |
| 22122 | case AArch64::WHILERW_PXX_S: |
| 22123 | case AArch64::WHILEWR_PXX_B: |
| 22124 | case AArch64::WHILEWR_PXX_D: |
| 22125 | case AArch64::WHILEWR_PXX_H: |
| 22126 | case AArch64::WHILEWR_PXX_S: { |
| 22127 | switch (OpNum) { |
| 22128 | case 0: |
| 22129 | // op: Pd |
| 22130 | return 0; |
| 22131 | case 2: |
| 22132 | // op: Rm |
| 22133 | return 16; |
| 22134 | case 1: |
| 22135 | // op: Rn |
| 22136 | return 5; |
| 22137 | } |
| 22138 | break; |
| 22139 | } |
| 22140 | case AArch64::PFALSE: |
| 22141 | case AArch64::RDFFR_P: { |
| 22142 | switch (OpNum) { |
| 22143 | case 0: |
| 22144 | // op: Pd |
| 22145 | return 0; |
| 22146 | } |
| 22147 | break; |
| 22148 | } |
| 22149 | case AArch64::WHILEGE_2PXX_B: |
| 22150 | case AArch64::WHILEGE_2PXX_D: |
| 22151 | case AArch64::WHILEGE_2PXX_H: |
| 22152 | case AArch64::WHILEGE_2PXX_S: |
| 22153 | case AArch64::WHILEGT_2PXX_B: |
| 22154 | case AArch64::WHILEGT_2PXX_D: |
| 22155 | case AArch64::WHILEGT_2PXX_H: |
| 22156 | case AArch64::WHILEGT_2PXX_S: |
| 22157 | case AArch64::WHILEHI_2PXX_B: |
| 22158 | case AArch64::WHILEHI_2PXX_D: |
| 22159 | case AArch64::WHILEHI_2PXX_H: |
| 22160 | case AArch64::WHILEHI_2PXX_S: |
| 22161 | case AArch64::WHILEHS_2PXX_B: |
| 22162 | case AArch64::WHILEHS_2PXX_D: |
| 22163 | case AArch64::WHILEHS_2PXX_H: |
| 22164 | case AArch64::WHILEHS_2PXX_S: |
| 22165 | case AArch64::WHILELE_2PXX_B: |
| 22166 | case AArch64::WHILELE_2PXX_D: |
| 22167 | case AArch64::WHILELE_2PXX_H: |
| 22168 | case AArch64::WHILELE_2PXX_S: |
| 22169 | case AArch64::WHILELO_2PXX_B: |
| 22170 | case AArch64::WHILELO_2PXX_D: |
| 22171 | case AArch64::WHILELO_2PXX_H: |
| 22172 | case AArch64::WHILELO_2PXX_S: |
| 22173 | case AArch64::WHILELS_2PXX_B: |
| 22174 | case AArch64::WHILELS_2PXX_D: |
| 22175 | case AArch64::WHILELS_2PXX_H: |
| 22176 | case AArch64::WHILELS_2PXX_S: |
| 22177 | case AArch64::WHILELT_2PXX_B: |
| 22178 | case AArch64::WHILELT_2PXX_D: |
| 22179 | case AArch64::WHILELT_2PXX_H: |
| 22180 | case AArch64::WHILELT_2PXX_S: { |
| 22181 | switch (OpNum) { |
| 22182 | case 0: |
| 22183 | // op: Pd |
| 22184 | return 1; |
| 22185 | case 1: |
| 22186 | // op: Rn |
| 22187 | return 5; |
| 22188 | case 2: |
| 22189 | // op: Rm |
| 22190 | return 16; |
| 22191 | } |
| 22192 | break; |
| 22193 | } |
| 22194 | case AArch64::BRKNS_PPzP: |
| 22195 | case AArch64::BRKN_PPzP: { |
| 22196 | switch (OpNum) { |
| 22197 | case 0: |
| 22198 | // op: Pdm |
| 22199 | return 0; |
| 22200 | case 1: |
| 22201 | // op: Pg |
| 22202 | return 10; |
| 22203 | case 2: |
| 22204 | // op: Pn |
| 22205 | return 5; |
| 22206 | } |
| 22207 | break; |
| 22208 | } |
| 22209 | case AArch64::PFIRST_B: |
| 22210 | case AArch64::PNEXT_B: |
| 22211 | case AArch64::PNEXT_D: |
| 22212 | case AArch64::PNEXT_H: |
| 22213 | case AArch64::PNEXT_S: { |
| 22214 | switch (OpNum) { |
| 22215 | case 0: |
| 22216 | // op: Pdn |
| 22217 | return 0; |
| 22218 | case 1: |
| 22219 | // op: Pg |
| 22220 | return 5; |
| 22221 | } |
| 22222 | break; |
| 22223 | } |
| 22224 | case AArch64::PTEST_PP: { |
| 22225 | switch (OpNum) { |
| 22226 | case 0: |
| 22227 | // op: Pg |
| 22228 | return 10; |
| 22229 | case 1: |
| 22230 | // op: Pn |
| 22231 | return 5; |
| 22232 | } |
| 22233 | break; |
| 22234 | } |
| 22235 | case AArch64::WRFFR: { |
| 22236 | switch (OpNum) { |
| 22237 | case 0: |
| 22238 | // op: Pn |
| 22239 | return 5; |
| 22240 | } |
| 22241 | break; |
| 22242 | } |
| 22243 | case AArch64::LDR_PXI: |
| 22244 | case AArch64::STR_PXI: { |
| 22245 | switch (OpNum) { |
| 22246 | case 0: |
| 22247 | // op: Pt |
| 22248 | return 0; |
| 22249 | case 1: |
| 22250 | // op: Rn |
| 22251 | return 5; |
| 22252 | case 2: |
| 22253 | // op: imm9 |
| 22254 | return 10; |
| 22255 | } |
| 22256 | break; |
| 22257 | } |
| 22258 | case AArch64::CNTP_XCI_B: |
| 22259 | case AArch64::CNTP_XCI_D: |
| 22260 | case AArch64::CNTP_XCI_H: |
| 22261 | case AArch64::CNTP_XCI_S: { |
| 22262 | switch (OpNum) { |
| 22263 | case 0: |
| 22264 | // op: Rd |
| 22265 | return 0; |
| 22266 | case 1: |
| 22267 | // op: PNn |
| 22268 | return 5; |
| 22269 | case 2: |
| 22270 | // op: vl |
| 22271 | return 10; |
| 22272 | } |
| 22273 | break; |
| 22274 | } |
| 22275 | case AArch64::ADDPL_XXI: |
| 22276 | case AArch64::ADDSPL_XXI: |
| 22277 | case AArch64::ADDSVL_XXI: |
| 22278 | case AArch64::ADDVL_XXI: { |
| 22279 | switch (OpNum) { |
| 22280 | case 0: |
| 22281 | // op: Rd |
| 22282 | return 0; |
| 22283 | case 1: |
| 22284 | // op: Rn |
| 22285 | return 16; |
| 22286 | case 2: |
| 22287 | // op: imm6 |
| 22288 | return 5; |
| 22289 | } |
| 22290 | break; |
| 22291 | } |
| 22292 | case AArch64::FMADDDrrr: |
| 22293 | case AArch64::FMADDHrrr: |
| 22294 | case AArch64::FMADDSrrr: |
| 22295 | case AArch64::FMSUBDrrr: |
| 22296 | case AArch64::FMSUBHrrr: |
| 22297 | case AArch64::FMSUBSrrr: |
| 22298 | case AArch64::FNMADDDrrr: |
| 22299 | case AArch64::FNMADDHrrr: |
| 22300 | case AArch64::FNMADDSrrr: |
| 22301 | case AArch64::FNMSUBDrrr: |
| 22302 | case AArch64::FNMSUBHrrr: |
| 22303 | case AArch64::FNMSUBSrrr: |
| 22304 | case AArch64::MADDPT: |
| 22305 | case AArch64::MADDWrrr: |
| 22306 | case AArch64::MADDXrrr: |
| 22307 | case AArch64::MSUBPT: |
| 22308 | case AArch64::MSUBWrrr: |
| 22309 | case AArch64::MSUBXrrr: |
| 22310 | case AArch64::SMADDLrrr: |
| 22311 | case AArch64::SMSUBLrrr: |
| 22312 | case AArch64::UMADDLrrr: |
| 22313 | case AArch64::UMSUBLrrr: { |
| 22314 | switch (OpNum) { |
| 22315 | case 0: |
| 22316 | // op: Rd |
| 22317 | return 0; |
| 22318 | case 1: |
| 22319 | // op: Rn |
| 22320 | return 5; |
| 22321 | case 2: |
| 22322 | // op: Rm |
| 22323 | return 16; |
| 22324 | case 3: |
| 22325 | // op: Ra |
| 22326 | return 10; |
| 22327 | } |
| 22328 | break; |
| 22329 | } |
| 22330 | case AArch64::CSELWr: |
| 22331 | case AArch64::CSELXr: |
| 22332 | case AArch64::CSINCWr: |
| 22333 | case AArch64::CSINCXr: |
| 22334 | case AArch64::CSINVWr: |
| 22335 | case AArch64::CSINVXr: |
| 22336 | case AArch64::CSNEGWr: |
| 22337 | case AArch64::CSNEGXr: |
| 22338 | case AArch64::FCSELDrrr: |
| 22339 | case AArch64::FCSELHrrr: |
| 22340 | case AArch64::FCSELSrrr: { |
| 22341 | switch (OpNum) { |
| 22342 | case 0: |
| 22343 | // op: Rd |
| 22344 | return 0; |
| 22345 | case 1: |
| 22346 | // op: Rn |
| 22347 | return 5; |
| 22348 | case 2: |
| 22349 | // op: Rm |
| 22350 | return 16; |
| 22351 | case 3: |
| 22352 | // op: cond |
| 22353 | return 12; |
| 22354 | } |
| 22355 | break; |
| 22356 | } |
| 22357 | case AArch64::ADDSXrx64: |
| 22358 | case AArch64::ADDXrx64: |
| 22359 | case AArch64::SUBSXrx64: |
| 22360 | case AArch64::SUBXrx64: { |
| 22361 | switch (OpNum) { |
| 22362 | case 0: |
| 22363 | // op: Rd |
| 22364 | return 0; |
| 22365 | case 1: |
| 22366 | // op: Rn |
| 22367 | return 5; |
| 22368 | case 2: |
| 22369 | // op: Rm |
| 22370 | return 16; |
| 22371 | case 3: |
| 22372 | // op: ext |
| 22373 | return 10; |
| 22374 | } |
| 22375 | break; |
| 22376 | } |
| 22377 | case AArch64::ADDSWrx: |
| 22378 | case AArch64::ADDSXrx: |
| 22379 | case AArch64::ADDWrx: |
| 22380 | case AArch64::ADDXrx: |
| 22381 | case AArch64::SUBSWrx: |
| 22382 | case AArch64::SUBSXrx: |
| 22383 | case AArch64::SUBWrx: |
| 22384 | case AArch64::SUBXrx: { |
| 22385 | switch (OpNum) { |
| 22386 | case 0: |
| 22387 | // op: Rd |
| 22388 | return 0; |
| 22389 | case 1: |
| 22390 | // op: Rn |
| 22391 | return 5; |
| 22392 | case 2: |
| 22393 | // op: Rm |
| 22394 | return 16; |
| 22395 | case 3: |
| 22396 | // op: extend |
| 22397 | return 10; |
| 22398 | } |
| 22399 | break; |
| 22400 | } |
| 22401 | case AArch64::FMULXv1i16_indexed: |
| 22402 | case AArch64::FMULXv1i32_indexed: |
| 22403 | case AArch64::FMULXv1i64_indexed: |
| 22404 | case AArch64::FMULXv2i32_indexed: |
| 22405 | case AArch64::FMULXv2i64_indexed: |
| 22406 | case AArch64::FMULXv4i16_indexed: |
| 22407 | case AArch64::FMULXv4i32_indexed: |
| 22408 | case AArch64::FMULXv8i16_indexed: |
| 22409 | case AArch64::FMULv1i16_indexed: |
| 22410 | case AArch64::FMULv1i32_indexed: |
| 22411 | case AArch64::FMULv1i64_indexed: |
| 22412 | case AArch64::FMULv2i32_indexed: |
| 22413 | case AArch64::FMULv2i64_indexed: |
| 22414 | case AArch64::FMULv4i16_indexed: |
| 22415 | case AArch64::FMULv4i32_indexed: |
| 22416 | case AArch64::FMULv8i16_indexed: |
| 22417 | case AArch64::MULv2i32_indexed: |
| 22418 | case AArch64::MULv4i16_indexed: |
| 22419 | case AArch64::MULv4i32_indexed: |
| 22420 | case AArch64::MULv8i16_indexed: |
| 22421 | case AArch64::SMULLv2i32_indexed: |
| 22422 | case AArch64::SMULLv4i16_indexed: |
| 22423 | case AArch64::SMULLv4i32_indexed: |
| 22424 | case AArch64::SMULLv8i16_indexed: |
| 22425 | case AArch64::SQDMULHv1i16_indexed: |
| 22426 | case AArch64::SQDMULHv1i32_indexed: |
| 22427 | case AArch64::SQDMULHv2i32_indexed: |
| 22428 | case AArch64::SQDMULHv4i16_indexed: |
| 22429 | case AArch64::SQDMULHv4i32_indexed: |
| 22430 | case AArch64::SQDMULHv8i16_indexed: |
| 22431 | case AArch64::SQDMULLv1i32_indexed: |
| 22432 | case AArch64::SQDMULLv1i64_indexed: |
| 22433 | case AArch64::SQDMULLv2i32_indexed: |
| 22434 | case AArch64::SQDMULLv4i16_indexed: |
| 22435 | case AArch64::SQDMULLv4i32_indexed: |
| 22436 | case AArch64::SQDMULLv8i16_indexed: |
| 22437 | case AArch64::SQRDMULHv1i16_indexed: |
| 22438 | case AArch64::SQRDMULHv1i32_indexed: |
| 22439 | case AArch64::SQRDMULHv2i32_indexed: |
| 22440 | case AArch64::SQRDMULHv4i16_indexed: |
| 22441 | case AArch64::SQRDMULHv4i32_indexed: |
| 22442 | case AArch64::SQRDMULHv8i16_indexed: |
| 22443 | case AArch64::UMULLv2i32_indexed: |
| 22444 | case AArch64::UMULLv4i16_indexed: |
| 22445 | case AArch64::UMULLv4i32_indexed: |
| 22446 | case AArch64::UMULLv8i16_indexed: { |
| 22447 | switch (OpNum) { |
| 22448 | case 0: |
| 22449 | // op: Rd |
| 22450 | return 0; |
| 22451 | case 1: |
| 22452 | // op: Rn |
| 22453 | return 5; |
| 22454 | case 2: |
| 22455 | // op: Rm |
| 22456 | return 16; |
| 22457 | case 3: |
| 22458 | // op: idx |
| 22459 | return 11; |
| 22460 | } |
| 22461 | break; |
| 22462 | } |
| 22463 | case AArch64::LUT2_H: { |
| 22464 | switch (OpNum) { |
| 22465 | case 0: |
| 22466 | // op: Rd |
| 22467 | return 0; |
| 22468 | case 1: |
| 22469 | // op: Rn |
| 22470 | return 5; |
| 22471 | case 2: |
| 22472 | // op: Rm |
| 22473 | return 16; |
| 22474 | case 3: |
| 22475 | // op: idx |
| 22476 | return 12; |
| 22477 | } |
| 22478 | break; |
| 22479 | } |
| 22480 | case AArch64::LUT2_B: |
| 22481 | case AArch64::LUT4_H: { |
| 22482 | switch (OpNum) { |
| 22483 | case 0: |
| 22484 | // op: Rd |
| 22485 | return 0; |
| 22486 | case 1: |
| 22487 | // op: Rn |
| 22488 | return 5; |
| 22489 | case 2: |
| 22490 | // op: Rm |
| 22491 | return 16; |
| 22492 | case 3: |
| 22493 | // op: idx |
| 22494 | return 13; |
| 22495 | } |
| 22496 | break; |
| 22497 | } |
| 22498 | case AArch64::LUT4_B: { |
| 22499 | switch (OpNum) { |
| 22500 | case 0: |
| 22501 | // op: Rd |
| 22502 | return 0; |
| 22503 | case 1: |
| 22504 | // op: Rn |
| 22505 | return 5; |
| 22506 | case 2: |
| 22507 | // op: Rm |
| 22508 | return 16; |
| 22509 | case 3: |
| 22510 | // op: idx |
| 22511 | return 14; |
| 22512 | } |
| 22513 | break; |
| 22514 | } |
| 22515 | case AArch64::EXTRWrri: |
| 22516 | case AArch64::EXTRXrri: { |
| 22517 | switch (OpNum) { |
| 22518 | case 0: |
| 22519 | // op: Rd |
| 22520 | return 0; |
| 22521 | case 1: |
| 22522 | // op: Rn |
| 22523 | return 5; |
| 22524 | case 2: |
| 22525 | // op: Rm |
| 22526 | return 16; |
| 22527 | case 3: |
| 22528 | // op: imm |
| 22529 | return 10; |
| 22530 | } |
| 22531 | break; |
| 22532 | } |
| 22533 | case AArch64::EXTv16i8: |
| 22534 | case AArch64::EXTv8i8: { |
| 22535 | switch (OpNum) { |
| 22536 | case 0: |
| 22537 | // op: Rd |
| 22538 | return 0; |
| 22539 | case 1: |
| 22540 | // op: Rn |
| 22541 | return 5; |
| 22542 | case 2: |
| 22543 | // op: Rm |
| 22544 | return 16; |
| 22545 | case 3: |
| 22546 | // op: imm |
| 22547 | return 11; |
| 22548 | } |
| 22549 | break; |
| 22550 | } |
| 22551 | case AArch64::FCADDv2f32: |
| 22552 | case AArch64::FCADDv2f64: |
| 22553 | case AArch64::FCADDv4f16: |
| 22554 | case AArch64::FCADDv4f32: |
| 22555 | case AArch64::FCADDv8f16: { |
| 22556 | switch (OpNum) { |
| 22557 | case 0: |
| 22558 | // op: Rd |
| 22559 | return 0; |
| 22560 | case 1: |
| 22561 | // op: Rn |
| 22562 | return 5; |
| 22563 | case 2: |
| 22564 | // op: Rm |
| 22565 | return 16; |
| 22566 | case 3: |
| 22567 | // op: rot |
| 22568 | return 12; |
| 22569 | } |
| 22570 | break; |
| 22571 | } |
| 22572 | case AArch64::ADDSWrs: |
| 22573 | case AArch64::ADDSXrs: |
| 22574 | case AArch64::ADDWrs: |
| 22575 | case AArch64::ADDXrs: |
| 22576 | case AArch64::ANDSWrs: |
| 22577 | case AArch64::ANDSXrs: |
| 22578 | case AArch64::ANDWrs: |
| 22579 | case AArch64::ANDXrs: |
| 22580 | case AArch64::BICSWrs: |
| 22581 | case AArch64::BICSXrs: |
| 22582 | case AArch64::BICWrs: |
| 22583 | case AArch64::BICXrs: |
| 22584 | case AArch64::EONWrs: |
| 22585 | case AArch64::EONXrs: |
| 22586 | case AArch64::EORWrs: |
| 22587 | case AArch64::EORXrs: |
| 22588 | case AArch64::ORNWrs: |
| 22589 | case AArch64::ORNXrs: |
| 22590 | case AArch64::ORRWrs: |
| 22591 | case AArch64::ORRXrs: |
| 22592 | case AArch64::SUBSWrs: |
| 22593 | case AArch64::SUBSXrs: |
| 22594 | case AArch64::SUBWrs: |
| 22595 | case AArch64::SUBXrs: { |
| 22596 | switch (OpNum) { |
| 22597 | case 0: |
| 22598 | // op: Rd |
| 22599 | return 0; |
| 22600 | case 1: |
| 22601 | // op: Rn |
| 22602 | return 5; |
| 22603 | case 2: |
| 22604 | // op: Rm |
| 22605 | return 16; |
| 22606 | case 3: |
| 22607 | // op: shift |
| 22608 | return 10; |
| 22609 | } |
| 22610 | break; |
| 22611 | } |
| 22612 | case AArch64::ADDPT_shift: |
| 22613 | case AArch64::SUBPT_shift: { |
| 22614 | switch (OpNum) { |
| 22615 | case 0: |
| 22616 | // op: Rd |
| 22617 | return 0; |
| 22618 | case 1: |
| 22619 | // op: Rn |
| 22620 | return 5; |
| 22621 | case 2: |
| 22622 | // op: Rm |
| 22623 | return 16; |
| 22624 | case 3: |
| 22625 | // op: shift_imm |
| 22626 | return 10; |
| 22627 | } |
| 22628 | break; |
| 22629 | } |
| 22630 | case AArch64::ADCSWr: |
| 22631 | case AArch64::ADCSXr: |
| 22632 | case AArch64::ADCWr: |
| 22633 | case AArch64::ADCXr: |
| 22634 | case AArch64::ADDHNv2i64_v2i32: |
| 22635 | case AArch64::ADDHNv4i32_v4i16: |
| 22636 | case AArch64::ADDHNv8i16_v8i8: |
| 22637 | case AArch64::ADDPv16i8: |
| 22638 | case AArch64::ADDPv2i32: |
| 22639 | case AArch64::ADDPv2i64: |
| 22640 | case AArch64::ADDPv4i16: |
| 22641 | case AArch64::ADDPv4i32: |
| 22642 | case AArch64::ADDPv8i16: |
| 22643 | case AArch64::ADDPv8i8: |
| 22644 | case AArch64::ADDv16i8: |
| 22645 | case AArch64::ADDv1i64: |
| 22646 | case AArch64::ADDv2i32: |
| 22647 | case AArch64::ADDv2i64: |
| 22648 | case AArch64::ADDv4i16: |
| 22649 | case AArch64::ADDv4i32: |
| 22650 | case AArch64::ADDv8i16: |
| 22651 | case AArch64::ADDv8i8: |
| 22652 | case AArch64::ANDv16i8: |
| 22653 | case AArch64::ANDv8i8: |
| 22654 | case AArch64::ASRVWr: |
| 22655 | case AArch64::ASRVXr: |
| 22656 | case AArch64::BICv16i8: |
| 22657 | case AArch64::BICv8i8: |
| 22658 | case AArch64::CMEQv16i8: |
| 22659 | case AArch64::CMEQv1i64: |
| 22660 | case AArch64::CMEQv2i32: |
| 22661 | case AArch64::CMEQv2i64: |
| 22662 | case AArch64::CMEQv4i16: |
| 22663 | case AArch64::CMEQv4i32: |
| 22664 | case AArch64::CMEQv8i16: |
| 22665 | case AArch64::CMEQv8i8: |
| 22666 | case AArch64::CMGEv16i8: |
| 22667 | case AArch64::CMGEv1i64: |
| 22668 | case AArch64::CMGEv2i32: |
| 22669 | case AArch64::CMGEv2i64: |
| 22670 | case AArch64::CMGEv4i16: |
| 22671 | case AArch64::CMGEv4i32: |
| 22672 | case AArch64::CMGEv8i16: |
| 22673 | case AArch64::CMGEv8i8: |
| 22674 | case AArch64::CMGTv16i8: |
| 22675 | case AArch64::CMGTv1i64: |
| 22676 | case AArch64::CMGTv2i32: |
| 22677 | case AArch64::CMGTv2i64: |
| 22678 | case AArch64::CMGTv4i16: |
| 22679 | case AArch64::CMGTv4i32: |
| 22680 | case AArch64::CMGTv8i16: |
| 22681 | case AArch64::CMGTv8i8: |
| 22682 | case AArch64::CMHIv16i8: |
| 22683 | case AArch64::CMHIv1i64: |
| 22684 | case AArch64::CMHIv2i32: |
| 22685 | case AArch64::CMHIv2i64: |
| 22686 | case AArch64::CMHIv4i16: |
| 22687 | case AArch64::CMHIv4i32: |
| 22688 | case AArch64::CMHIv8i16: |
| 22689 | case AArch64::CMHIv8i8: |
| 22690 | case AArch64::CMHSv16i8: |
| 22691 | case AArch64::CMHSv1i64: |
| 22692 | case AArch64::CMHSv2i32: |
| 22693 | case AArch64::CMHSv2i64: |
| 22694 | case AArch64::CMHSv4i16: |
| 22695 | case AArch64::CMHSv4i32: |
| 22696 | case AArch64::CMHSv8i16: |
| 22697 | case AArch64::CMHSv8i8: |
| 22698 | case AArch64::CMTSTv16i8: |
| 22699 | case AArch64::CMTSTv1i64: |
| 22700 | case AArch64::CMTSTv2i32: |
| 22701 | case AArch64::CMTSTv2i64: |
| 22702 | case AArch64::CMTSTv4i16: |
| 22703 | case AArch64::CMTSTv4i32: |
| 22704 | case AArch64::CMTSTv8i16: |
| 22705 | case AArch64::CMTSTv8i8: |
| 22706 | case AArch64::CRC32Brr: |
| 22707 | case AArch64::CRC32CBrr: |
| 22708 | case AArch64::CRC32CHrr: |
| 22709 | case AArch64::CRC32CWrr: |
| 22710 | case AArch64::CRC32CXrr: |
| 22711 | case AArch64::CRC32Hrr: |
| 22712 | case AArch64::CRC32Wrr: |
| 22713 | case AArch64::CRC32Xrr: |
| 22714 | case AArch64::EORv16i8: |
| 22715 | case AArch64::EORv8i8: |
| 22716 | case AArch64::FABD16: |
| 22717 | case AArch64::FABD32: |
| 22718 | case AArch64::FABD64: |
| 22719 | case AArch64::FABDv2f32: |
| 22720 | case AArch64::FABDv2f64: |
| 22721 | case AArch64::FABDv4f16: |
| 22722 | case AArch64::FABDv4f32: |
| 22723 | case AArch64::FABDv8f16: |
| 22724 | case AArch64::FACGE16: |
| 22725 | case AArch64::FACGE32: |
| 22726 | case AArch64::FACGE64: |
| 22727 | case AArch64::FACGEv2f32: |
| 22728 | case AArch64::FACGEv2f64: |
| 22729 | case AArch64::FACGEv4f16: |
| 22730 | case AArch64::FACGEv4f32: |
| 22731 | case AArch64::FACGEv8f16: |
| 22732 | case AArch64::FACGT16: |
| 22733 | case AArch64::FACGT32: |
| 22734 | case AArch64::FACGT64: |
| 22735 | case AArch64::FACGTv2f32: |
| 22736 | case AArch64::FACGTv2f64: |
| 22737 | case AArch64::FACGTv4f16: |
| 22738 | case AArch64::FACGTv4f32: |
| 22739 | case AArch64::FACGTv8f16: |
| 22740 | case AArch64::FADDDrr: |
| 22741 | case AArch64::FADDHrr: |
| 22742 | case AArch64::FADDPv2f32: |
| 22743 | case AArch64::FADDPv2f64: |
| 22744 | case AArch64::FADDPv4f16: |
| 22745 | case AArch64::FADDPv4f32: |
| 22746 | case AArch64::FADDPv8f16: |
| 22747 | case AArch64::FADDSrr: |
| 22748 | case AArch64::FADDv2f32: |
| 22749 | case AArch64::FADDv2f64: |
| 22750 | case AArch64::FADDv4f16: |
| 22751 | case AArch64::FADDv4f32: |
| 22752 | case AArch64::FADDv8f16: |
| 22753 | case AArch64::FAMAXv2f32: |
| 22754 | case AArch64::FAMAXv2f64: |
| 22755 | case AArch64::FAMAXv4f16: |
| 22756 | case AArch64::FAMAXv4f32: |
| 22757 | case AArch64::FAMAXv8f16: |
| 22758 | case AArch64::FAMINv2f32: |
| 22759 | case AArch64::FAMINv2f64: |
| 22760 | case AArch64::FAMINv4f16: |
| 22761 | case AArch64::FAMINv4f32: |
| 22762 | case AArch64::FAMINv8f16: |
| 22763 | case AArch64::FCMEQ16: |
| 22764 | case AArch64::FCMEQ32: |
| 22765 | case AArch64::FCMEQ64: |
| 22766 | case AArch64::FCMEQv2f32: |
| 22767 | case AArch64::FCMEQv2f64: |
| 22768 | case AArch64::FCMEQv4f16: |
| 22769 | case AArch64::FCMEQv4f32: |
| 22770 | case AArch64::FCMEQv8f16: |
| 22771 | case AArch64::FCMGE16: |
| 22772 | case AArch64::FCMGE32: |
| 22773 | case AArch64::FCMGE64: |
| 22774 | case AArch64::FCMGEv2f32: |
| 22775 | case AArch64::FCMGEv2f64: |
| 22776 | case AArch64::FCMGEv4f16: |
| 22777 | case AArch64::FCMGEv4f32: |
| 22778 | case AArch64::FCMGEv8f16: |
| 22779 | case AArch64::FCMGT16: |
| 22780 | case AArch64::FCMGT32: |
| 22781 | case AArch64::FCMGT64: |
| 22782 | case AArch64::FCMGTv2f32: |
| 22783 | case AArch64::FCMGTv2f64: |
| 22784 | case AArch64::FCMGTv4f16: |
| 22785 | case AArch64::FCMGTv4f32: |
| 22786 | case AArch64::FCMGTv8f16: |
| 22787 | case AArch64::FCVTN_F16v16f8: |
| 22788 | case AArch64::FCVTN_F16v8f8: |
| 22789 | case AArch64::FCVTN_F32v8f8: |
| 22790 | case AArch64::FDIVDrr: |
| 22791 | case AArch64::FDIVHrr: |
| 22792 | case AArch64::FDIVSrr: |
| 22793 | case AArch64::FDIVv2f32: |
| 22794 | case AArch64::FDIVv2f64: |
| 22795 | case AArch64::FDIVv4f16: |
| 22796 | case AArch64::FDIVv4f32: |
| 22797 | case AArch64::FDIVv8f16: |
| 22798 | case AArch64::FMAXDrr: |
| 22799 | case AArch64::FMAXHrr: |
| 22800 | case AArch64::FMAXNMDrr: |
| 22801 | case AArch64::FMAXNMHrr: |
| 22802 | case AArch64::FMAXNMPv2f32: |
| 22803 | case AArch64::FMAXNMPv2f64: |
| 22804 | case AArch64::FMAXNMPv4f16: |
| 22805 | case AArch64::FMAXNMPv4f32: |
| 22806 | case AArch64::FMAXNMPv8f16: |
| 22807 | case AArch64::FMAXNMSrr: |
| 22808 | case AArch64::FMAXNMv2f32: |
| 22809 | case AArch64::FMAXNMv2f64: |
| 22810 | case AArch64::FMAXNMv4f16: |
| 22811 | case AArch64::FMAXNMv4f32: |
| 22812 | case AArch64::FMAXNMv8f16: |
| 22813 | case AArch64::FMAXPv2f32: |
| 22814 | case AArch64::FMAXPv2f64: |
| 22815 | case AArch64::FMAXPv4f16: |
| 22816 | case AArch64::FMAXPv4f32: |
| 22817 | case AArch64::FMAXPv8f16: |
| 22818 | case AArch64::FMAXSrr: |
| 22819 | case AArch64::FMAXv2f32: |
| 22820 | case AArch64::FMAXv2f64: |
| 22821 | case AArch64::FMAXv4f16: |
| 22822 | case AArch64::FMAXv4f32: |
| 22823 | case AArch64::FMAXv8f16: |
| 22824 | case AArch64::FMINDrr: |
| 22825 | case AArch64::FMINHrr: |
| 22826 | case AArch64::FMINNMDrr: |
| 22827 | case AArch64::FMINNMHrr: |
| 22828 | case AArch64::FMINNMPv2f32: |
| 22829 | case AArch64::FMINNMPv2f64: |
| 22830 | case AArch64::FMINNMPv4f16: |
| 22831 | case AArch64::FMINNMPv4f32: |
| 22832 | case AArch64::FMINNMPv8f16: |
| 22833 | case AArch64::FMINNMSrr: |
| 22834 | case AArch64::FMINNMv2f32: |
| 22835 | case AArch64::FMINNMv2f64: |
| 22836 | case AArch64::FMINNMv4f16: |
| 22837 | case AArch64::FMINNMv4f32: |
| 22838 | case AArch64::FMINNMv8f16: |
| 22839 | case AArch64::FMINPv2f32: |
| 22840 | case AArch64::FMINPv2f64: |
| 22841 | case AArch64::FMINPv4f16: |
| 22842 | case AArch64::FMINPv4f32: |
| 22843 | case AArch64::FMINPv8f16: |
| 22844 | case AArch64::FMINSrr: |
| 22845 | case AArch64::FMINv2f32: |
| 22846 | case AArch64::FMINv2f64: |
| 22847 | case AArch64::FMINv4f16: |
| 22848 | case AArch64::FMINv4f32: |
| 22849 | case AArch64::FMINv8f16: |
| 22850 | case AArch64::FMULDrr: |
| 22851 | case AArch64::FMULHrr: |
| 22852 | case AArch64::FMULSrr: |
| 22853 | case AArch64::FMULX16: |
| 22854 | case AArch64::FMULX32: |
| 22855 | case AArch64::FMULX64: |
| 22856 | case AArch64::FMULXv2f32: |
| 22857 | case AArch64::FMULXv2f64: |
| 22858 | case AArch64::FMULXv4f16: |
| 22859 | case AArch64::FMULXv4f32: |
| 22860 | case AArch64::FMULXv8f16: |
| 22861 | case AArch64::FMULv2f32: |
| 22862 | case AArch64::FMULv2f64: |
| 22863 | case AArch64::FMULv4f16: |
| 22864 | case AArch64::FMULv4f32: |
| 22865 | case AArch64::FMULv8f16: |
| 22866 | case AArch64::FNMULDrr: |
| 22867 | case AArch64::FNMULHrr: |
| 22868 | case AArch64::FNMULSrr: |
| 22869 | case AArch64::FRECPS16: |
| 22870 | case AArch64::FRECPS32: |
| 22871 | case AArch64::FRECPS64: |
| 22872 | case AArch64::FRECPSv2f32: |
| 22873 | case AArch64::FRECPSv2f64: |
| 22874 | case AArch64::FRECPSv4f16: |
| 22875 | case AArch64::FRECPSv4f32: |
| 22876 | case AArch64::FRECPSv8f16: |
| 22877 | case AArch64::FRSQRTS16: |
| 22878 | case AArch64::FRSQRTS32: |
| 22879 | case AArch64::FRSQRTS64: |
| 22880 | case AArch64::FRSQRTSv2f32: |
| 22881 | case AArch64::FRSQRTSv2f64: |
| 22882 | case AArch64::FRSQRTSv4f16: |
| 22883 | case AArch64::FRSQRTSv4f32: |
| 22884 | case AArch64::FRSQRTSv8f16: |
| 22885 | case AArch64::FSCALEv2f32: |
| 22886 | case AArch64::FSCALEv2f64: |
| 22887 | case AArch64::FSCALEv4f16: |
| 22888 | case AArch64::FSCALEv4f32: |
| 22889 | case AArch64::FSCALEv8f16: |
| 22890 | case AArch64::FSUBDrr: |
| 22891 | case AArch64::FSUBHrr: |
| 22892 | case AArch64::FSUBSrr: |
| 22893 | case AArch64::FSUBv2f32: |
| 22894 | case AArch64::FSUBv2f64: |
| 22895 | case AArch64::FSUBv4f16: |
| 22896 | case AArch64::FSUBv4f32: |
| 22897 | case AArch64::FSUBv8f16: |
| 22898 | case AArch64::GMI: |
| 22899 | case AArch64::IRG: |
| 22900 | case AArch64::LSLVWr: |
| 22901 | case AArch64::LSLVXr: |
| 22902 | case AArch64::LSRVWr: |
| 22903 | case AArch64::LSRVXr: |
| 22904 | case AArch64::MULv16i8: |
| 22905 | case AArch64::MULv2i32: |
| 22906 | case AArch64::MULv4i16: |
| 22907 | case AArch64::MULv4i32: |
| 22908 | case AArch64::MULv8i16: |
| 22909 | case AArch64::MULv8i8: |
| 22910 | case AArch64::ORNv16i8: |
| 22911 | case AArch64::ORNv8i8: |
| 22912 | case AArch64::ORRv16i8: |
| 22913 | case AArch64::ORRv8i8: |
| 22914 | case AArch64::PACGA: |
| 22915 | case AArch64::PMULLv16i8: |
| 22916 | case AArch64::PMULLv1i64: |
| 22917 | case AArch64::PMULLv2i64: |
| 22918 | case AArch64::PMULLv8i8: |
| 22919 | case AArch64::PMULv16i8: |
| 22920 | case AArch64::PMULv8i8: |
| 22921 | case AArch64::RADDHNv2i64_v2i32: |
| 22922 | case AArch64::RADDHNv4i32_v4i16: |
| 22923 | case AArch64::RADDHNv8i16_v8i8: |
| 22924 | case AArch64::RORVWr: |
| 22925 | case AArch64::RORVXr: |
| 22926 | case AArch64::RSUBHNv2i64_v2i32: |
| 22927 | case AArch64::RSUBHNv4i32_v4i16: |
| 22928 | case AArch64::RSUBHNv8i16_v8i8: |
| 22929 | case AArch64::SABDLv16i8_v8i16: |
| 22930 | case AArch64::SABDLv2i32_v2i64: |
| 22931 | case AArch64::SABDLv4i16_v4i32: |
| 22932 | case AArch64::SABDLv4i32_v2i64: |
| 22933 | case AArch64::SABDLv8i16_v4i32: |
| 22934 | case AArch64::SABDLv8i8_v8i16: |
| 22935 | case AArch64::SABDv16i8: |
| 22936 | case AArch64::SABDv2i32: |
| 22937 | case AArch64::SABDv4i16: |
| 22938 | case AArch64::SABDv4i32: |
| 22939 | case AArch64::SABDv8i16: |
| 22940 | case AArch64::SABDv8i8: |
| 22941 | case AArch64::SADDLv16i8_v8i16: |
| 22942 | case AArch64::SADDLv2i32_v2i64: |
| 22943 | case AArch64::SADDLv4i16_v4i32: |
| 22944 | case AArch64::SADDLv4i32_v2i64: |
| 22945 | case AArch64::SADDLv8i16_v4i32: |
| 22946 | case AArch64::SADDLv8i8_v8i16: |
| 22947 | case AArch64::SADDWv16i8_v8i16: |
| 22948 | case AArch64::SADDWv2i32_v2i64: |
| 22949 | case AArch64::SADDWv4i16_v4i32: |
| 22950 | case AArch64::SADDWv4i32_v2i64: |
| 22951 | case AArch64::SADDWv8i16_v4i32: |
| 22952 | case AArch64::SADDWv8i8_v8i16: |
| 22953 | case AArch64::SBCSWr: |
| 22954 | case AArch64::SBCSXr: |
| 22955 | case AArch64::SBCWr: |
| 22956 | case AArch64::SBCXr: |
| 22957 | case AArch64::SDIVWr: |
| 22958 | case AArch64::SDIVXr: |
| 22959 | case AArch64::SHADDv16i8: |
| 22960 | case AArch64::SHADDv2i32: |
| 22961 | case AArch64::SHADDv4i16: |
| 22962 | case AArch64::SHADDv4i32: |
| 22963 | case AArch64::SHADDv8i16: |
| 22964 | case AArch64::SHADDv8i8: |
| 22965 | case AArch64::SHSUBv16i8: |
| 22966 | case AArch64::SHSUBv2i32: |
| 22967 | case AArch64::SHSUBv4i16: |
| 22968 | case AArch64::SHSUBv4i32: |
| 22969 | case AArch64::SHSUBv8i16: |
| 22970 | case AArch64::SHSUBv8i8: |
| 22971 | case AArch64::SMAXPv16i8: |
| 22972 | case AArch64::SMAXPv2i32: |
| 22973 | case AArch64::SMAXPv4i16: |
| 22974 | case AArch64::SMAXPv4i32: |
| 22975 | case AArch64::SMAXPv8i16: |
| 22976 | case AArch64::SMAXPv8i8: |
| 22977 | case AArch64::SMAXWrr: |
| 22978 | case AArch64::SMAXXrr: |
| 22979 | case AArch64::SMAXv16i8: |
| 22980 | case AArch64::SMAXv2i32: |
| 22981 | case AArch64::SMAXv4i16: |
| 22982 | case AArch64::SMAXv4i32: |
| 22983 | case AArch64::SMAXv8i16: |
| 22984 | case AArch64::SMAXv8i8: |
| 22985 | case AArch64::SMINPv16i8: |
| 22986 | case AArch64::SMINPv2i32: |
| 22987 | case AArch64::SMINPv4i16: |
| 22988 | case AArch64::SMINPv4i32: |
| 22989 | case AArch64::SMINPv8i16: |
| 22990 | case AArch64::SMINPv8i8: |
| 22991 | case AArch64::SMINWrr: |
| 22992 | case AArch64::SMINXrr: |
| 22993 | case AArch64::SMINv16i8: |
| 22994 | case AArch64::SMINv2i32: |
| 22995 | case AArch64::SMINv4i16: |
| 22996 | case AArch64::SMINv4i32: |
| 22997 | case AArch64::SMINv8i16: |
| 22998 | case AArch64::SMINv8i8: |
| 22999 | case AArch64::SMULHrr: |
| 23000 | case AArch64::SMULLv16i8_v8i16: |
| 23001 | case AArch64::SMULLv2i32_v2i64: |
| 23002 | case AArch64::SMULLv4i16_v4i32: |
| 23003 | case AArch64::SMULLv4i32_v2i64: |
| 23004 | case AArch64::SMULLv8i16_v4i32: |
| 23005 | case AArch64::SMULLv8i8_v8i16: |
| 23006 | case AArch64::SQADDv16i8: |
| 23007 | case AArch64::SQADDv1i16: |
| 23008 | case AArch64::SQADDv1i32: |
| 23009 | case AArch64::SQADDv1i64: |
| 23010 | case AArch64::SQADDv1i8: |
| 23011 | case AArch64::SQADDv2i32: |
| 23012 | case AArch64::SQADDv2i64: |
| 23013 | case AArch64::SQADDv4i16: |
| 23014 | case AArch64::SQADDv4i32: |
| 23015 | case AArch64::SQADDv8i16: |
| 23016 | case AArch64::SQADDv8i8: |
| 23017 | case AArch64::SQDMULHv1i16: |
| 23018 | case AArch64::SQDMULHv1i32: |
| 23019 | case AArch64::SQDMULHv2i32: |
| 23020 | case AArch64::SQDMULHv4i16: |
| 23021 | case AArch64::SQDMULHv4i32: |
| 23022 | case AArch64::SQDMULHv8i16: |
| 23023 | case AArch64::SQDMULLi16: |
| 23024 | case AArch64::SQDMULLi32: |
| 23025 | case AArch64::SQDMULLv2i32_v2i64: |
| 23026 | case AArch64::SQDMULLv4i16_v4i32: |
| 23027 | case AArch64::SQDMULLv4i32_v2i64: |
| 23028 | case AArch64::SQDMULLv8i16_v4i32: |
| 23029 | case AArch64::SQRDMULHv1i16: |
| 23030 | case AArch64::SQRDMULHv1i32: |
| 23031 | case AArch64::SQRDMULHv2i32: |
| 23032 | case AArch64::SQRDMULHv4i16: |
| 23033 | case AArch64::SQRDMULHv4i32: |
| 23034 | case AArch64::SQRDMULHv8i16: |
| 23035 | case AArch64::SQRSHLv16i8: |
| 23036 | case AArch64::SQRSHLv1i16: |
| 23037 | case AArch64::SQRSHLv1i32: |
| 23038 | case AArch64::SQRSHLv1i64: |
| 23039 | case AArch64::SQRSHLv1i8: |
| 23040 | case AArch64::SQRSHLv2i32: |
| 23041 | case AArch64::SQRSHLv2i64: |
| 23042 | case AArch64::SQRSHLv4i16: |
| 23043 | case AArch64::SQRSHLv4i32: |
| 23044 | case AArch64::SQRSHLv8i16: |
| 23045 | case AArch64::SQRSHLv8i8: |
| 23046 | case AArch64::SQSHLv16i8: |
| 23047 | case AArch64::SQSHLv1i16: |
| 23048 | case AArch64::SQSHLv1i32: |
| 23049 | case AArch64::SQSHLv1i64: |
| 23050 | case AArch64::SQSHLv1i8: |
| 23051 | case AArch64::SQSHLv2i32: |
| 23052 | case AArch64::SQSHLv2i64: |
| 23053 | case AArch64::SQSHLv4i16: |
| 23054 | case AArch64::SQSHLv4i32: |
| 23055 | case AArch64::SQSHLv8i16: |
| 23056 | case AArch64::SQSHLv8i8: |
| 23057 | case AArch64::SQSUBv16i8: |
| 23058 | case AArch64::SQSUBv1i16: |
| 23059 | case AArch64::SQSUBv1i32: |
| 23060 | case AArch64::SQSUBv1i64: |
| 23061 | case AArch64::SQSUBv1i8: |
| 23062 | case AArch64::SQSUBv2i32: |
| 23063 | case AArch64::SQSUBv2i64: |
| 23064 | case AArch64::SQSUBv4i16: |
| 23065 | case AArch64::SQSUBv4i32: |
| 23066 | case AArch64::SQSUBv8i16: |
| 23067 | case AArch64::SQSUBv8i8: |
| 23068 | case AArch64::SRHADDv16i8: |
| 23069 | case AArch64::SRHADDv2i32: |
| 23070 | case AArch64::SRHADDv4i16: |
| 23071 | case AArch64::SRHADDv4i32: |
| 23072 | case AArch64::SRHADDv8i16: |
| 23073 | case AArch64::SRHADDv8i8: |
| 23074 | case AArch64::SRSHLv16i8: |
| 23075 | case AArch64::SRSHLv1i64: |
| 23076 | case AArch64::SRSHLv2i32: |
| 23077 | case AArch64::SRSHLv2i64: |
| 23078 | case AArch64::SRSHLv4i16: |
| 23079 | case AArch64::SRSHLv4i32: |
| 23080 | case AArch64::SRSHLv8i16: |
| 23081 | case AArch64::SRSHLv8i8: |
| 23082 | case AArch64::SSHLv16i8: |
| 23083 | case AArch64::SSHLv1i64: |
| 23084 | case AArch64::SSHLv2i32: |
| 23085 | case AArch64::SSHLv2i64: |
| 23086 | case AArch64::SSHLv4i16: |
| 23087 | case AArch64::SSHLv4i32: |
| 23088 | case AArch64::SSHLv8i16: |
| 23089 | case AArch64::SSHLv8i8: |
| 23090 | case AArch64::SSUBLv16i8_v8i16: |
| 23091 | case AArch64::SSUBLv2i32_v2i64: |
| 23092 | case AArch64::SSUBLv4i16_v4i32: |
| 23093 | case AArch64::SSUBLv4i32_v2i64: |
| 23094 | case AArch64::SSUBLv8i16_v4i32: |
| 23095 | case AArch64::SSUBLv8i8_v8i16: |
| 23096 | case AArch64::SSUBWv16i8_v8i16: |
| 23097 | case AArch64::SSUBWv2i32_v2i64: |
| 23098 | case AArch64::SSUBWv4i16_v4i32: |
| 23099 | case AArch64::SSUBWv4i32_v2i64: |
| 23100 | case AArch64::SSUBWv8i16_v4i32: |
| 23101 | case AArch64::SSUBWv8i8_v8i16: |
| 23102 | case AArch64::SUBHNv2i64_v2i32: |
| 23103 | case AArch64::SUBHNv4i32_v4i16: |
| 23104 | case AArch64::SUBHNv8i16_v8i8: |
| 23105 | case AArch64::SUBP: |
| 23106 | case AArch64::SUBPS: |
| 23107 | case AArch64::SUBv16i8: |
| 23108 | case AArch64::SUBv1i64: |
| 23109 | case AArch64::SUBv2i32: |
| 23110 | case AArch64::SUBv2i64: |
| 23111 | case AArch64::SUBv4i16: |
| 23112 | case AArch64::SUBv4i32: |
| 23113 | case AArch64::SUBv8i16: |
| 23114 | case AArch64::SUBv8i8: |
| 23115 | case AArch64::TRN1v16i8: |
| 23116 | case AArch64::TRN1v2i32: |
| 23117 | case AArch64::TRN1v2i64: |
| 23118 | case AArch64::TRN1v4i16: |
| 23119 | case AArch64::TRN1v4i32: |
| 23120 | case AArch64::TRN1v8i16: |
| 23121 | case AArch64::TRN1v8i8: |
| 23122 | case AArch64::TRN2v16i8: |
| 23123 | case AArch64::TRN2v2i32: |
| 23124 | case AArch64::TRN2v2i64: |
| 23125 | case AArch64::TRN2v4i16: |
| 23126 | case AArch64::TRN2v4i32: |
| 23127 | case AArch64::TRN2v8i16: |
| 23128 | case AArch64::TRN2v8i8: |
| 23129 | case AArch64::UABDLv16i8_v8i16: |
| 23130 | case AArch64::UABDLv2i32_v2i64: |
| 23131 | case AArch64::UABDLv4i16_v4i32: |
| 23132 | case AArch64::UABDLv4i32_v2i64: |
| 23133 | case AArch64::UABDLv8i16_v4i32: |
| 23134 | case AArch64::UABDLv8i8_v8i16: |
| 23135 | case AArch64::UABDv16i8: |
| 23136 | case AArch64::UABDv2i32: |
| 23137 | case AArch64::UABDv4i16: |
| 23138 | case AArch64::UABDv4i32: |
| 23139 | case AArch64::UABDv8i16: |
| 23140 | case AArch64::UABDv8i8: |
| 23141 | case AArch64::UADDLv16i8_v8i16: |
| 23142 | case AArch64::UADDLv2i32_v2i64: |
| 23143 | case AArch64::UADDLv4i16_v4i32: |
| 23144 | case AArch64::UADDLv4i32_v2i64: |
| 23145 | case AArch64::UADDLv8i16_v4i32: |
| 23146 | case AArch64::UADDLv8i8_v8i16: |
| 23147 | case AArch64::UADDWv16i8_v8i16: |
| 23148 | case AArch64::UADDWv2i32_v2i64: |
| 23149 | case AArch64::UADDWv4i16_v4i32: |
| 23150 | case AArch64::UADDWv4i32_v2i64: |
| 23151 | case AArch64::UADDWv8i16_v4i32: |
| 23152 | case AArch64::UADDWv8i8_v8i16: |
| 23153 | case AArch64::UDIVWr: |
| 23154 | case AArch64::UDIVXr: |
| 23155 | case AArch64::UHADDv16i8: |
| 23156 | case AArch64::UHADDv2i32: |
| 23157 | case AArch64::UHADDv4i16: |
| 23158 | case AArch64::UHADDv4i32: |
| 23159 | case AArch64::UHADDv8i16: |
| 23160 | case AArch64::UHADDv8i8: |
| 23161 | case AArch64::UHSUBv16i8: |
| 23162 | case AArch64::UHSUBv2i32: |
| 23163 | case AArch64::UHSUBv4i16: |
| 23164 | case AArch64::UHSUBv4i32: |
| 23165 | case AArch64::UHSUBv8i16: |
| 23166 | case AArch64::UHSUBv8i8: |
| 23167 | case AArch64::UMAXPv16i8: |
| 23168 | case AArch64::UMAXPv2i32: |
| 23169 | case AArch64::UMAXPv4i16: |
| 23170 | case AArch64::UMAXPv4i32: |
| 23171 | case AArch64::UMAXPv8i16: |
| 23172 | case AArch64::UMAXPv8i8: |
| 23173 | case AArch64::UMAXWrr: |
| 23174 | case AArch64::UMAXXrr: |
| 23175 | case AArch64::UMAXv16i8: |
| 23176 | case AArch64::UMAXv2i32: |
| 23177 | case AArch64::UMAXv4i16: |
| 23178 | case AArch64::UMAXv4i32: |
| 23179 | case AArch64::UMAXv8i16: |
| 23180 | case AArch64::UMAXv8i8: |
| 23181 | case AArch64::UMINPv16i8: |
| 23182 | case AArch64::UMINPv2i32: |
| 23183 | case AArch64::UMINPv4i16: |
| 23184 | case AArch64::UMINPv4i32: |
| 23185 | case AArch64::UMINPv8i16: |
| 23186 | case AArch64::UMINPv8i8: |
| 23187 | case AArch64::UMINWrr: |
| 23188 | case AArch64::UMINXrr: |
| 23189 | case AArch64::UMINv16i8: |
| 23190 | case AArch64::UMINv2i32: |
| 23191 | case AArch64::UMINv4i16: |
| 23192 | case AArch64::UMINv4i32: |
| 23193 | case AArch64::UMINv8i16: |
| 23194 | case AArch64::UMINv8i8: |
| 23195 | case AArch64::UMULHrr: |
| 23196 | case AArch64::UMULLv16i8_v8i16: |
| 23197 | case AArch64::UMULLv2i32_v2i64: |
| 23198 | case AArch64::UMULLv4i16_v4i32: |
| 23199 | case AArch64::UMULLv4i32_v2i64: |
| 23200 | case AArch64::UMULLv8i16_v4i32: |
| 23201 | case AArch64::UMULLv8i8_v8i16: |
| 23202 | case AArch64::UQADDv16i8: |
| 23203 | case AArch64::UQADDv1i16: |
| 23204 | case AArch64::UQADDv1i32: |
| 23205 | case AArch64::UQADDv1i64: |
| 23206 | case AArch64::UQADDv1i8: |
| 23207 | case AArch64::UQADDv2i32: |
| 23208 | case AArch64::UQADDv2i64: |
| 23209 | case AArch64::UQADDv4i16: |
| 23210 | case AArch64::UQADDv4i32: |
| 23211 | case AArch64::UQADDv8i16: |
| 23212 | case AArch64::UQADDv8i8: |
| 23213 | case AArch64::UQRSHLv16i8: |
| 23214 | case AArch64::UQRSHLv1i16: |
| 23215 | case AArch64::UQRSHLv1i32: |
| 23216 | case AArch64::UQRSHLv1i64: |
| 23217 | case AArch64::UQRSHLv1i8: |
| 23218 | case AArch64::UQRSHLv2i32: |
| 23219 | case AArch64::UQRSHLv2i64: |
| 23220 | case AArch64::UQRSHLv4i16: |
| 23221 | case AArch64::UQRSHLv4i32: |
| 23222 | case AArch64::UQRSHLv8i16: |
| 23223 | case AArch64::UQRSHLv8i8: |
| 23224 | case AArch64::UQSHLv16i8: |
| 23225 | case AArch64::UQSHLv1i16: |
| 23226 | case AArch64::UQSHLv1i32: |
| 23227 | case AArch64::UQSHLv1i64: |
| 23228 | case AArch64::UQSHLv1i8: |
| 23229 | case AArch64::UQSHLv2i32: |
| 23230 | case AArch64::UQSHLv2i64: |
| 23231 | case AArch64::UQSHLv4i16: |
| 23232 | case AArch64::UQSHLv4i32: |
| 23233 | case AArch64::UQSHLv8i16: |
| 23234 | case AArch64::UQSHLv8i8: |
| 23235 | case AArch64::UQSUBv16i8: |
| 23236 | case AArch64::UQSUBv1i16: |
| 23237 | case AArch64::UQSUBv1i32: |
| 23238 | case AArch64::UQSUBv1i64: |
| 23239 | case AArch64::UQSUBv1i8: |
| 23240 | case AArch64::UQSUBv2i32: |
| 23241 | case AArch64::UQSUBv2i64: |
| 23242 | case AArch64::UQSUBv4i16: |
| 23243 | case AArch64::UQSUBv4i32: |
| 23244 | case AArch64::UQSUBv8i16: |
| 23245 | case AArch64::UQSUBv8i8: |
| 23246 | case AArch64::URHADDv16i8: |
| 23247 | case AArch64::URHADDv2i32: |
| 23248 | case AArch64::URHADDv4i16: |
| 23249 | case AArch64::URHADDv4i32: |
| 23250 | case AArch64::URHADDv8i16: |
| 23251 | case AArch64::URHADDv8i8: |
| 23252 | case AArch64::URSHLv16i8: |
| 23253 | case AArch64::URSHLv1i64: |
| 23254 | case AArch64::URSHLv2i32: |
| 23255 | case AArch64::URSHLv2i64: |
| 23256 | case AArch64::URSHLv4i16: |
| 23257 | case AArch64::URSHLv4i32: |
| 23258 | case AArch64::URSHLv8i16: |
| 23259 | case AArch64::URSHLv8i8: |
| 23260 | case AArch64::USHLv16i8: |
| 23261 | case AArch64::USHLv1i64: |
| 23262 | case AArch64::USHLv2i32: |
| 23263 | case AArch64::USHLv2i64: |
| 23264 | case AArch64::USHLv4i16: |
| 23265 | case AArch64::USHLv4i32: |
| 23266 | case AArch64::USHLv8i16: |
| 23267 | case AArch64::USHLv8i8: |
| 23268 | case AArch64::USUBLv16i8_v8i16: |
| 23269 | case AArch64::USUBLv2i32_v2i64: |
| 23270 | case AArch64::USUBLv4i16_v4i32: |
| 23271 | case AArch64::USUBLv4i32_v2i64: |
| 23272 | case AArch64::USUBLv8i16_v4i32: |
| 23273 | case AArch64::USUBLv8i8_v8i16: |
| 23274 | case AArch64::USUBWv16i8_v8i16: |
| 23275 | case AArch64::USUBWv2i32_v2i64: |
| 23276 | case AArch64::USUBWv4i16_v4i32: |
| 23277 | case AArch64::USUBWv4i32_v2i64: |
| 23278 | case AArch64::USUBWv8i16_v4i32: |
| 23279 | case AArch64::USUBWv8i8_v8i16: |
| 23280 | case AArch64::UZP1v16i8: |
| 23281 | case AArch64::UZP1v2i32: |
| 23282 | case AArch64::UZP1v2i64: |
| 23283 | case AArch64::UZP1v4i16: |
| 23284 | case AArch64::UZP1v4i32: |
| 23285 | case AArch64::UZP1v8i16: |
| 23286 | case AArch64::UZP1v8i8: |
| 23287 | case AArch64::UZP2v16i8: |
| 23288 | case AArch64::UZP2v2i32: |
| 23289 | case AArch64::UZP2v2i64: |
| 23290 | case AArch64::UZP2v4i16: |
| 23291 | case AArch64::UZP2v4i32: |
| 23292 | case AArch64::UZP2v8i16: |
| 23293 | case AArch64::UZP2v8i8: |
| 23294 | case AArch64::ZIP1v16i8: |
| 23295 | case AArch64::ZIP1v2i32: |
| 23296 | case AArch64::ZIP1v2i64: |
| 23297 | case AArch64::ZIP1v4i16: |
| 23298 | case AArch64::ZIP1v4i32: |
| 23299 | case AArch64::ZIP1v8i16: |
| 23300 | case AArch64::ZIP1v8i8: |
| 23301 | case AArch64::ZIP2v16i8: |
| 23302 | case AArch64::ZIP2v2i32: |
| 23303 | case AArch64::ZIP2v2i64: |
| 23304 | case AArch64::ZIP2v4i16: |
| 23305 | case AArch64::ZIP2v4i32: |
| 23306 | case AArch64::ZIP2v8i16: |
| 23307 | case AArch64::ZIP2v8i8: { |
| 23308 | switch (OpNum) { |
| 23309 | case 0: |
| 23310 | // op: Rd |
| 23311 | return 0; |
| 23312 | case 1: |
| 23313 | // op: Rn |
| 23314 | return 5; |
| 23315 | case 2: |
| 23316 | // op: Rm |
| 23317 | return 16; |
| 23318 | } |
| 23319 | break; |
| 23320 | } |
| 23321 | case AArch64::DUPv16i8lane: |
| 23322 | case AArch64::DUPv8i8lane: |
| 23323 | case AArch64::SMOVvi8to32: |
| 23324 | case AArch64::SMOVvi8to64: |
| 23325 | case AArch64::UMOVvi8: { |
| 23326 | switch (OpNum) { |
| 23327 | case 0: |
| 23328 | // op: Rd |
| 23329 | return 0; |
| 23330 | case 1: |
| 23331 | // op: Rn |
| 23332 | return 5; |
| 23333 | case 2: |
| 23334 | // op: idx |
| 23335 | return 17; |
| 23336 | } |
| 23337 | break; |
| 23338 | } |
| 23339 | case AArch64::DUPv4i16lane: |
| 23340 | case AArch64::DUPv8i16lane: |
| 23341 | case AArch64::SMOVvi16to32: |
| 23342 | case AArch64::SMOVvi16to64: |
| 23343 | case AArch64::UMOVvi16: { |
| 23344 | switch (OpNum) { |
| 23345 | case 0: |
| 23346 | // op: Rd |
| 23347 | return 0; |
| 23348 | case 1: |
| 23349 | // op: Rn |
| 23350 | return 5; |
| 23351 | case 2: |
| 23352 | // op: idx |
| 23353 | return 18; |
| 23354 | } |
| 23355 | break; |
| 23356 | } |
| 23357 | case AArch64::DUPv2i32lane: |
| 23358 | case AArch64::DUPv4i32lane: |
| 23359 | case AArch64::SMOVvi32to64: |
| 23360 | case AArch64::UMOVvi32: { |
| 23361 | switch (OpNum) { |
| 23362 | case 0: |
| 23363 | // op: Rd |
| 23364 | return 0; |
| 23365 | case 1: |
| 23366 | // op: Rn |
| 23367 | return 5; |
| 23368 | case 2: |
| 23369 | // op: idx |
| 23370 | return 19; |
| 23371 | } |
| 23372 | break; |
| 23373 | } |
| 23374 | case AArch64::DUPv2i64lane: |
| 23375 | case AArch64::UMOVvi64: { |
| 23376 | switch (OpNum) { |
| 23377 | case 0: |
| 23378 | // op: Rd |
| 23379 | return 0; |
| 23380 | case 1: |
| 23381 | // op: Rn |
| 23382 | return 5; |
| 23383 | case 2: |
| 23384 | // op: idx |
| 23385 | return 20; |
| 23386 | } |
| 23387 | break; |
| 23388 | } |
| 23389 | case AArch64::ADDSWri: |
| 23390 | case AArch64::ADDSXri: |
| 23391 | case AArch64::ADDWri: |
| 23392 | case AArch64::ADDXri: |
| 23393 | case AArch64::ANDSWri: |
| 23394 | case AArch64::ANDSXri: |
| 23395 | case AArch64::ANDWri: |
| 23396 | case AArch64::ANDXri: |
| 23397 | case AArch64::EORWri: |
| 23398 | case AArch64::EORXri: |
| 23399 | case AArch64::ORRWri: |
| 23400 | case AArch64::ORRXri: |
| 23401 | case AArch64::SMAXWri: |
| 23402 | case AArch64::SMAXXri: |
| 23403 | case AArch64::SMINWri: |
| 23404 | case AArch64::SMINXri: |
| 23405 | case AArch64::SUBSWri: |
| 23406 | case AArch64::SUBSXri: |
| 23407 | case AArch64::SUBWri: |
| 23408 | case AArch64::SUBXri: |
| 23409 | case AArch64::UMAXWri: |
| 23410 | case AArch64::UMAXXri: |
| 23411 | case AArch64::UMINWri: |
| 23412 | case AArch64::UMINXri: { |
| 23413 | switch (OpNum) { |
| 23414 | case 0: |
| 23415 | // op: Rd |
| 23416 | return 0; |
| 23417 | case 1: |
| 23418 | // op: Rn |
| 23419 | return 5; |
| 23420 | case 2: |
| 23421 | // op: imm |
| 23422 | return 10; |
| 23423 | } |
| 23424 | break; |
| 23425 | } |
| 23426 | case AArch64::FCVTZSd: |
| 23427 | case AArch64::FCVTZSh: |
| 23428 | case AArch64::FCVTZSs: |
| 23429 | case AArch64::FCVTZSv2i32_shift: |
| 23430 | case AArch64::FCVTZSv2i64_shift: |
| 23431 | case AArch64::FCVTZSv4i16_shift: |
| 23432 | case AArch64::FCVTZSv4i32_shift: |
| 23433 | case AArch64::FCVTZSv8i16_shift: |
| 23434 | case AArch64::FCVTZUd: |
| 23435 | case AArch64::FCVTZUh: |
| 23436 | case AArch64::FCVTZUs: |
| 23437 | case AArch64::FCVTZUv2i32_shift: |
| 23438 | case AArch64::FCVTZUv2i64_shift: |
| 23439 | case AArch64::FCVTZUv4i16_shift: |
| 23440 | case AArch64::FCVTZUv4i32_shift: |
| 23441 | case AArch64::FCVTZUv8i16_shift: |
| 23442 | case AArch64::RSHRNv2i32_shift: |
| 23443 | case AArch64::RSHRNv4i16_shift: |
| 23444 | case AArch64::RSHRNv8i8_shift: |
| 23445 | case AArch64::SCVTFd: |
| 23446 | case AArch64::SCVTFh: |
| 23447 | case AArch64::SCVTFs: |
| 23448 | case AArch64::SCVTFv2i32_shift: |
| 23449 | case AArch64::SCVTFv2i64_shift: |
| 23450 | case AArch64::SCVTFv4i16_shift: |
| 23451 | case AArch64::SCVTFv4i32_shift: |
| 23452 | case AArch64::SCVTFv8i16_shift: |
| 23453 | case AArch64::SHLd: |
| 23454 | case AArch64::SHLv16i8_shift: |
| 23455 | case AArch64::SHLv2i32_shift: |
| 23456 | case AArch64::SHLv2i64_shift: |
| 23457 | case AArch64::SHLv4i16_shift: |
| 23458 | case AArch64::SHLv4i32_shift: |
| 23459 | case AArch64::SHLv8i16_shift: |
| 23460 | case AArch64::SHLv8i8_shift: |
| 23461 | case AArch64::SHRNv2i32_shift: |
| 23462 | case AArch64::SHRNv4i16_shift: |
| 23463 | case AArch64::SHRNv8i8_shift: |
| 23464 | case AArch64::SQRSHRNb: |
| 23465 | case AArch64::SQRSHRNh: |
| 23466 | case AArch64::SQRSHRNs: |
| 23467 | case AArch64::SQRSHRNv2i32_shift: |
| 23468 | case AArch64::SQRSHRNv4i16_shift: |
| 23469 | case AArch64::SQRSHRNv8i8_shift: |
| 23470 | case AArch64::SQRSHRUNb: |
| 23471 | case AArch64::SQRSHRUNh: |
| 23472 | case AArch64::SQRSHRUNs: |
| 23473 | case AArch64::SQRSHRUNv2i32_shift: |
| 23474 | case AArch64::SQRSHRUNv4i16_shift: |
| 23475 | case AArch64::SQRSHRUNv8i8_shift: |
| 23476 | case AArch64::SQSHLUb: |
| 23477 | case AArch64::SQSHLUd: |
| 23478 | case AArch64::SQSHLUh: |
| 23479 | case AArch64::SQSHLUs: |
| 23480 | case AArch64::SQSHLUv16i8_shift: |
| 23481 | case AArch64::SQSHLUv2i32_shift: |
| 23482 | case AArch64::SQSHLUv2i64_shift: |
| 23483 | case AArch64::SQSHLUv4i16_shift: |
| 23484 | case AArch64::SQSHLUv4i32_shift: |
| 23485 | case AArch64::SQSHLUv8i16_shift: |
| 23486 | case AArch64::SQSHLUv8i8_shift: |
| 23487 | case AArch64::SQSHLb: |
| 23488 | case AArch64::SQSHLd: |
| 23489 | case AArch64::SQSHLh: |
| 23490 | case AArch64::SQSHLs: |
| 23491 | case AArch64::SQSHLv16i8_shift: |
| 23492 | case AArch64::SQSHLv2i32_shift: |
| 23493 | case AArch64::SQSHLv2i64_shift: |
| 23494 | case AArch64::SQSHLv4i16_shift: |
| 23495 | case AArch64::SQSHLv4i32_shift: |
| 23496 | case AArch64::SQSHLv8i16_shift: |
| 23497 | case AArch64::SQSHLv8i8_shift: |
| 23498 | case AArch64::SQSHRNb: |
| 23499 | case AArch64::SQSHRNh: |
| 23500 | case AArch64::SQSHRNs: |
| 23501 | case AArch64::SQSHRNv2i32_shift: |
| 23502 | case AArch64::SQSHRNv4i16_shift: |
| 23503 | case AArch64::SQSHRNv8i8_shift: |
| 23504 | case AArch64::SQSHRUNb: |
| 23505 | case AArch64::SQSHRUNh: |
| 23506 | case AArch64::SQSHRUNs: |
| 23507 | case AArch64::SQSHRUNv2i32_shift: |
| 23508 | case AArch64::SQSHRUNv4i16_shift: |
| 23509 | case AArch64::SQSHRUNv8i8_shift: |
| 23510 | case AArch64::SRSHRd: |
| 23511 | case AArch64::SRSHRv16i8_shift: |
| 23512 | case AArch64::SRSHRv2i32_shift: |
| 23513 | case AArch64::SRSHRv2i64_shift: |
| 23514 | case AArch64::SRSHRv4i16_shift: |
| 23515 | case AArch64::SRSHRv4i32_shift: |
| 23516 | case AArch64::SRSHRv8i16_shift: |
| 23517 | case AArch64::SRSHRv8i8_shift: |
| 23518 | case AArch64::SSHLLv16i8_shift: |
| 23519 | case AArch64::SSHLLv2i32_shift: |
| 23520 | case AArch64::SSHLLv4i16_shift: |
| 23521 | case AArch64::SSHLLv4i32_shift: |
| 23522 | case AArch64::SSHLLv8i16_shift: |
| 23523 | case AArch64::SSHLLv8i8_shift: |
| 23524 | case AArch64::SSHRd: |
| 23525 | case AArch64::SSHRv16i8_shift: |
| 23526 | case AArch64::SSHRv2i32_shift: |
| 23527 | case AArch64::SSHRv2i64_shift: |
| 23528 | case AArch64::SSHRv4i16_shift: |
| 23529 | case AArch64::SSHRv4i32_shift: |
| 23530 | case AArch64::SSHRv8i16_shift: |
| 23531 | case AArch64::SSHRv8i8_shift: |
| 23532 | case AArch64::UCVTFd: |
| 23533 | case AArch64::UCVTFh: |
| 23534 | case AArch64::UCVTFs: |
| 23535 | case AArch64::UCVTFv2i32_shift: |
| 23536 | case AArch64::UCVTFv2i64_shift: |
| 23537 | case AArch64::UCVTFv4i16_shift: |
| 23538 | case AArch64::UCVTFv4i32_shift: |
| 23539 | case AArch64::UCVTFv8i16_shift: |
| 23540 | case AArch64::UQRSHRNb: |
| 23541 | case AArch64::UQRSHRNh: |
| 23542 | case AArch64::UQRSHRNs: |
| 23543 | case AArch64::UQRSHRNv2i32_shift: |
| 23544 | case AArch64::UQRSHRNv4i16_shift: |
| 23545 | case AArch64::UQRSHRNv8i8_shift: |
| 23546 | case AArch64::UQSHLb: |
| 23547 | case AArch64::UQSHLd: |
| 23548 | case AArch64::UQSHLh: |
| 23549 | case AArch64::UQSHLs: |
| 23550 | case AArch64::UQSHLv16i8_shift: |
| 23551 | case AArch64::UQSHLv2i32_shift: |
| 23552 | case AArch64::UQSHLv2i64_shift: |
| 23553 | case AArch64::UQSHLv4i16_shift: |
| 23554 | case AArch64::UQSHLv4i32_shift: |
| 23555 | case AArch64::UQSHLv8i16_shift: |
| 23556 | case AArch64::UQSHLv8i8_shift: |
| 23557 | case AArch64::UQSHRNb: |
| 23558 | case AArch64::UQSHRNh: |
| 23559 | case AArch64::UQSHRNs: |
| 23560 | case AArch64::UQSHRNv2i32_shift: |
| 23561 | case AArch64::UQSHRNv4i16_shift: |
| 23562 | case AArch64::UQSHRNv8i8_shift: |
| 23563 | case AArch64::URSHRd: |
| 23564 | case AArch64::URSHRv16i8_shift: |
| 23565 | case AArch64::URSHRv2i32_shift: |
| 23566 | case AArch64::URSHRv2i64_shift: |
| 23567 | case AArch64::URSHRv4i16_shift: |
| 23568 | case AArch64::URSHRv4i32_shift: |
| 23569 | case AArch64::URSHRv8i16_shift: |
| 23570 | case AArch64::URSHRv8i8_shift: |
| 23571 | case AArch64::USHLLv16i8_shift: |
| 23572 | case AArch64::USHLLv2i32_shift: |
| 23573 | case AArch64::USHLLv4i16_shift: |
| 23574 | case AArch64::USHLLv4i32_shift: |
| 23575 | case AArch64::USHLLv8i16_shift: |
| 23576 | case AArch64::USHLLv8i8_shift: |
| 23577 | case AArch64::USHRd: |
| 23578 | case AArch64::USHRv16i8_shift: |
| 23579 | case AArch64::USHRv2i32_shift: |
| 23580 | case AArch64::USHRv2i64_shift: |
| 23581 | case AArch64::USHRv4i16_shift: |
| 23582 | case AArch64::USHRv4i32_shift: |
| 23583 | case AArch64::USHRv8i16_shift: |
| 23584 | case AArch64::USHRv8i8_shift: { |
| 23585 | switch (OpNum) { |
| 23586 | case 0: |
| 23587 | // op: Rd |
| 23588 | return 0; |
| 23589 | case 1: |
| 23590 | // op: Rn |
| 23591 | return 5; |
| 23592 | case 2: |
| 23593 | // op: imm |
| 23594 | return 16; |
| 23595 | } |
| 23596 | break; |
| 23597 | } |
| 23598 | case AArch64::ADDG: |
| 23599 | case AArch64::SUBG: { |
| 23600 | switch (OpNum) { |
| 23601 | case 0: |
| 23602 | // op: Rd |
| 23603 | return 0; |
| 23604 | case 1: |
| 23605 | // op: Rn |
| 23606 | return 5; |
| 23607 | case 2: |
| 23608 | // op: imm6 |
| 23609 | return 16; |
| 23610 | case 3: |
| 23611 | // op: imm4 |
| 23612 | return 10; |
| 23613 | } |
| 23614 | break; |
| 23615 | } |
| 23616 | case AArch64::SBFMWri: |
| 23617 | case AArch64::SBFMXri: |
| 23618 | case AArch64::UBFMWri: |
| 23619 | case AArch64::UBFMXri: { |
| 23620 | switch (OpNum) { |
| 23621 | case 0: |
| 23622 | // op: Rd |
| 23623 | return 0; |
| 23624 | case 1: |
| 23625 | // op: Rn |
| 23626 | return 5; |
| 23627 | case 2: |
| 23628 | // op: immr |
| 23629 | return 16; |
| 23630 | case 3: |
| 23631 | // op: imms |
| 23632 | return 10; |
| 23633 | } |
| 23634 | break; |
| 23635 | } |
| 23636 | case AArch64::FCVTZSSWDri: |
| 23637 | case AArch64::FCVTZSSWHri: |
| 23638 | case AArch64::FCVTZSSWSri: |
| 23639 | case AArch64::FCVTZSSXDri: |
| 23640 | case AArch64::FCVTZSSXHri: |
| 23641 | case AArch64::FCVTZSSXSri: |
| 23642 | case AArch64::FCVTZUSWDri: |
| 23643 | case AArch64::FCVTZUSWHri: |
| 23644 | case AArch64::FCVTZUSWSri: |
| 23645 | case AArch64::FCVTZUSXDri: |
| 23646 | case AArch64::FCVTZUSXHri: |
| 23647 | case AArch64::FCVTZUSXSri: |
| 23648 | case AArch64::SCVTFSWDri: |
| 23649 | case AArch64::SCVTFSWHri: |
| 23650 | case AArch64::SCVTFSWSri: |
| 23651 | case AArch64::SCVTFSXDri: |
| 23652 | case AArch64::SCVTFSXHri: |
| 23653 | case AArch64::SCVTFSXSri: |
| 23654 | case AArch64::UCVTFSWDri: |
| 23655 | case AArch64::UCVTFSWHri: |
| 23656 | case AArch64::UCVTFSWSri: |
| 23657 | case AArch64::UCVTFSXDri: |
| 23658 | case AArch64::UCVTFSXHri: |
| 23659 | case AArch64::UCVTFSXSri: { |
| 23660 | switch (OpNum) { |
| 23661 | case 0: |
| 23662 | // op: Rd |
| 23663 | return 0; |
| 23664 | case 1: |
| 23665 | // op: Rn |
| 23666 | return 5; |
| 23667 | case 2: |
| 23668 | // op: scale |
| 23669 | return 10; |
| 23670 | } |
| 23671 | break; |
| 23672 | } |
| 23673 | case AArch64::ABSWr: |
| 23674 | case AArch64::ABSXr: |
| 23675 | case AArch64::ABSv16i8: |
| 23676 | case AArch64::ABSv1i64: |
| 23677 | case AArch64::ABSv2i32: |
| 23678 | case AArch64::ABSv2i64: |
| 23679 | case AArch64::ABSv4i16: |
| 23680 | case AArch64::ABSv4i32: |
| 23681 | case AArch64::ABSv8i16: |
| 23682 | case AArch64::ABSv8i8: |
| 23683 | case AArch64::ADDPv2i64p: |
| 23684 | case AArch64::ADDVv16i8v: |
| 23685 | case AArch64::ADDVv4i16v: |
| 23686 | case AArch64::ADDVv4i32v: |
| 23687 | case AArch64::ADDVv8i16v: |
| 23688 | case AArch64::ADDVv8i8v: |
| 23689 | case AArch64::AESIMCrr: |
| 23690 | case AArch64::AESMCrr: |
| 23691 | case AArch64::BF1CVTL: |
| 23692 | case AArch64::BF1CVTL2: |
| 23693 | case AArch64::BF2CVTL: |
| 23694 | case AArch64::BF2CVTL2: |
| 23695 | case AArch64::BFCVT: |
| 23696 | case AArch64::BFCVTN: |
| 23697 | case AArch64::CLSWr: |
| 23698 | case AArch64::CLSXr: |
| 23699 | case AArch64::CLSv16i8: |
| 23700 | case AArch64::CLSv2i32: |
| 23701 | case AArch64::CLSv4i16: |
| 23702 | case AArch64::CLSv4i32: |
| 23703 | case AArch64::CLSv8i16: |
| 23704 | case AArch64::CLSv8i8: |
| 23705 | case AArch64::CLZWr: |
| 23706 | case AArch64::CLZXr: |
| 23707 | case AArch64::CLZv16i8: |
| 23708 | case AArch64::CLZv2i32: |
| 23709 | case AArch64::CLZv4i16: |
| 23710 | case AArch64::CLZv4i32: |
| 23711 | case AArch64::CLZv8i16: |
| 23712 | case AArch64::CLZv8i8: |
| 23713 | case AArch64::CMEQv16i8rz: |
| 23714 | case AArch64::CMEQv1i64rz: |
| 23715 | case AArch64::CMEQv2i32rz: |
| 23716 | case AArch64::CMEQv2i64rz: |
| 23717 | case AArch64::CMEQv4i16rz: |
| 23718 | case AArch64::CMEQv4i32rz: |
| 23719 | case AArch64::CMEQv8i16rz: |
| 23720 | case AArch64::CMEQv8i8rz: |
| 23721 | case AArch64::CMGEv16i8rz: |
| 23722 | case AArch64::CMGEv1i64rz: |
| 23723 | case AArch64::CMGEv2i32rz: |
| 23724 | case AArch64::CMGEv2i64rz: |
| 23725 | case AArch64::CMGEv4i16rz: |
| 23726 | case AArch64::CMGEv4i32rz: |
| 23727 | case AArch64::CMGEv8i16rz: |
| 23728 | case AArch64::CMGEv8i8rz: |
| 23729 | case AArch64::CMGTv16i8rz: |
| 23730 | case AArch64::CMGTv1i64rz: |
| 23731 | case AArch64::CMGTv2i32rz: |
| 23732 | case AArch64::CMGTv2i64rz: |
| 23733 | case AArch64::CMGTv4i16rz: |
| 23734 | case AArch64::CMGTv4i32rz: |
| 23735 | case AArch64::CMGTv8i16rz: |
| 23736 | case AArch64::CMGTv8i8rz: |
| 23737 | case AArch64::CMLEv16i8rz: |
| 23738 | case AArch64::CMLEv1i64rz: |
| 23739 | case AArch64::CMLEv2i32rz: |
| 23740 | case AArch64::CMLEv2i64rz: |
| 23741 | case AArch64::CMLEv4i16rz: |
| 23742 | case AArch64::CMLEv4i32rz: |
| 23743 | case AArch64::CMLEv8i16rz: |
| 23744 | case AArch64::CMLEv8i8rz: |
| 23745 | case AArch64::CMLTv16i8rz: |
| 23746 | case AArch64::CMLTv1i64rz: |
| 23747 | case AArch64::CMLTv2i32rz: |
| 23748 | case AArch64::CMLTv2i64rz: |
| 23749 | case AArch64::CMLTv4i16rz: |
| 23750 | case AArch64::CMLTv4i32rz: |
| 23751 | case AArch64::CMLTv8i16rz: |
| 23752 | case AArch64::CMLTv8i8rz: |
| 23753 | case AArch64::CNTWr: |
| 23754 | case AArch64::CNTXr: |
| 23755 | case AArch64::CNTv16i8: |
| 23756 | case AArch64::CNTv8i8: |
| 23757 | case AArch64::CTZWr: |
| 23758 | case AArch64::CTZXr: |
| 23759 | case AArch64::DUPv16i8gpr: |
| 23760 | case AArch64::DUPv2i32gpr: |
| 23761 | case AArch64::DUPv2i64gpr: |
| 23762 | case AArch64::DUPv4i16gpr: |
| 23763 | case AArch64::DUPv4i32gpr: |
| 23764 | case AArch64::DUPv8i16gpr: |
| 23765 | case AArch64::DUPv8i8gpr: |
| 23766 | case AArch64::F1CVTL: |
| 23767 | case AArch64::F1CVTL2: |
| 23768 | case AArch64::F2CVTL: |
| 23769 | case AArch64::F2CVTL2: |
| 23770 | case AArch64::FABSDr: |
| 23771 | case AArch64::FABSHr: |
| 23772 | case AArch64::FABSSr: |
| 23773 | case AArch64::FABSv2f32: |
| 23774 | case AArch64::FABSv2f64: |
| 23775 | case AArch64::FABSv4f16: |
| 23776 | case AArch64::FABSv4f32: |
| 23777 | case AArch64::FABSv8f16: |
| 23778 | case AArch64::FADDPv2i16p: |
| 23779 | case AArch64::FADDPv2i32p: |
| 23780 | case AArch64::FADDPv2i64p: |
| 23781 | case AArch64::FCMEQv1i16rz: |
| 23782 | case AArch64::FCMEQv1i32rz: |
| 23783 | case AArch64::FCMEQv1i64rz: |
| 23784 | case AArch64::FCMEQv2i32rz: |
| 23785 | case AArch64::FCMEQv2i64rz: |
| 23786 | case AArch64::FCMEQv4i16rz: |
| 23787 | case AArch64::FCMEQv4i32rz: |
| 23788 | case AArch64::FCMEQv8i16rz: |
| 23789 | case AArch64::FCMGEv1i16rz: |
| 23790 | case AArch64::FCMGEv1i32rz: |
| 23791 | case AArch64::FCMGEv1i64rz: |
| 23792 | case AArch64::FCMGEv2i32rz: |
| 23793 | case AArch64::FCMGEv2i64rz: |
| 23794 | case AArch64::FCMGEv4i16rz: |
| 23795 | case AArch64::FCMGEv4i32rz: |
| 23796 | case AArch64::FCMGEv8i16rz: |
| 23797 | case AArch64::FCMGTv1i16rz: |
| 23798 | case AArch64::FCMGTv1i32rz: |
| 23799 | case AArch64::FCMGTv1i64rz: |
| 23800 | case AArch64::FCMGTv2i32rz: |
| 23801 | case AArch64::FCMGTv2i64rz: |
| 23802 | case AArch64::FCMGTv4i16rz: |
| 23803 | case AArch64::FCMGTv4i32rz: |
| 23804 | case AArch64::FCMGTv8i16rz: |
| 23805 | case AArch64::FCMLEv1i16rz: |
| 23806 | case AArch64::FCMLEv1i32rz: |
| 23807 | case AArch64::FCMLEv1i64rz: |
| 23808 | case AArch64::FCMLEv2i32rz: |
| 23809 | case AArch64::FCMLEv2i64rz: |
| 23810 | case AArch64::FCMLEv4i16rz: |
| 23811 | case AArch64::FCMLEv4i32rz: |
| 23812 | case AArch64::FCMLEv8i16rz: |
| 23813 | case AArch64::FCMLTv1i16rz: |
| 23814 | case AArch64::FCMLTv1i32rz: |
| 23815 | case AArch64::FCMLTv1i64rz: |
| 23816 | case AArch64::FCMLTv2i32rz: |
| 23817 | case AArch64::FCMLTv2i64rz: |
| 23818 | case AArch64::FCMLTv4i16rz: |
| 23819 | case AArch64::FCMLTv4i32rz: |
| 23820 | case AArch64::FCMLTv8i16rz: |
| 23821 | case AArch64::FCVTASDHr: |
| 23822 | case AArch64::FCVTASDSr: |
| 23823 | case AArch64::FCVTASSDr: |
| 23824 | case AArch64::FCVTASSHr: |
| 23825 | case AArch64::FCVTASUWDr: |
| 23826 | case AArch64::FCVTASUWHr: |
| 23827 | case AArch64::FCVTASUWSr: |
| 23828 | case AArch64::FCVTASUXDr: |
| 23829 | case AArch64::FCVTASUXHr: |
| 23830 | case AArch64::FCVTASUXSr: |
| 23831 | case AArch64::FCVTASv1f16: |
| 23832 | case AArch64::FCVTASv1i32: |
| 23833 | case AArch64::FCVTASv1i64: |
| 23834 | case AArch64::FCVTASv2f32: |
| 23835 | case AArch64::FCVTASv2f64: |
| 23836 | case AArch64::FCVTASv4f16: |
| 23837 | case AArch64::FCVTASv4f32: |
| 23838 | case AArch64::FCVTASv8f16: |
| 23839 | case AArch64::FCVTAUDHr: |
| 23840 | case AArch64::FCVTAUDSr: |
| 23841 | case AArch64::FCVTAUSDr: |
| 23842 | case AArch64::FCVTAUSHr: |
| 23843 | case AArch64::FCVTAUUWDr: |
| 23844 | case AArch64::FCVTAUUWHr: |
| 23845 | case AArch64::FCVTAUUWSr: |
| 23846 | case AArch64::FCVTAUUXDr: |
| 23847 | case AArch64::FCVTAUUXHr: |
| 23848 | case AArch64::FCVTAUUXSr: |
| 23849 | case AArch64::FCVTAUv1f16: |
| 23850 | case AArch64::FCVTAUv1i32: |
| 23851 | case AArch64::FCVTAUv1i64: |
| 23852 | case AArch64::FCVTAUv2f32: |
| 23853 | case AArch64::FCVTAUv2f64: |
| 23854 | case AArch64::FCVTAUv4f16: |
| 23855 | case AArch64::FCVTAUv4f32: |
| 23856 | case AArch64::FCVTAUv8f16: |
| 23857 | case AArch64::FCVTDHr: |
| 23858 | case AArch64::FCVTDSr: |
| 23859 | case AArch64::FCVTHDr: |
| 23860 | case AArch64::FCVTHSr: |
| 23861 | case AArch64::FCVTLv2i32: |
| 23862 | case AArch64::FCVTLv4i16: |
| 23863 | case AArch64::FCVTLv4i32: |
| 23864 | case AArch64::FCVTLv8i16: |
| 23865 | case AArch64::FCVTMSDHr: |
| 23866 | case AArch64::FCVTMSDSr: |
| 23867 | case AArch64::FCVTMSSDr: |
| 23868 | case AArch64::FCVTMSSHr: |
| 23869 | case AArch64::FCVTMSUWDr: |
| 23870 | case AArch64::FCVTMSUWHr: |
| 23871 | case AArch64::FCVTMSUWSr: |
| 23872 | case AArch64::FCVTMSUXDr: |
| 23873 | case AArch64::FCVTMSUXHr: |
| 23874 | case AArch64::FCVTMSUXSr: |
| 23875 | case AArch64::FCVTMSv1f16: |
| 23876 | case AArch64::FCVTMSv1i32: |
| 23877 | case AArch64::FCVTMSv1i64: |
| 23878 | case AArch64::FCVTMSv2f32: |
| 23879 | case AArch64::FCVTMSv2f64: |
| 23880 | case AArch64::FCVTMSv4f16: |
| 23881 | case AArch64::FCVTMSv4f32: |
| 23882 | case AArch64::FCVTMSv8f16: |
| 23883 | case AArch64::FCVTMUDHr: |
| 23884 | case AArch64::FCVTMUDSr: |
| 23885 | case AArch64::FCVTMUSDr: |
| 23886 | case AArch64::FCVTMUSHr: |
| 23887 | case AArch64::FCVTMUUWDr: |
| 23888 | case AArch64::FCVTMUUWHr: |
| 23889 | case AArch64::FCVTMUUWSr: |
| 23890 | case AArch64::FCVTMUUXDr: |
| 23891 | case AArch64::FCVTMUUXHr: |
| 23892 | case AArch64::FCVTMUUXSr: |
| 23893 | case AArch64::FCVTMUv1f16: |
| 23894 | case AArch64::FCVTMUv1i32: |
| 23895 | case AArch64::FCVTMUv1i64: |
| 23896 | case AArch64::FCVTMUv2f32: |
| 23897 | case AArch64::FCVTMUv2f64: |
| 23898 | case AArch64::FCVTMUv4f16: |
| 23899 | case AArch64::FCVTMUv4f32: |
| 23900 | case AArch64::FCVTMUv8f16: |
| 23901 | case AArch64::FCVTNSDHr: |
| 23902 | case AArch64::FCVTNSDSr: |
| 23903 | case AArch64::FCVTNSSDr: |
| 23904 | case AArch64::FCVTNSSHr: |
| 23905 | case AArch64::FCVTNSUWDr: |
| 23906 | case AArch64::FCVTNSUWHr: |
| 23907 | case AArch64::FCVTNSUWSr: |
| 23908 | case AArch64::FCVTNSUXDr: |
| 23909 | case AArch64::FCVTNSUXHr: |
| 23910 | case AArch64::FCVTNSUXSr: |
| 23911 | case AArch64::FCVTNSv1f16: |
| 23912 | case AArch64::FCVTNSv1i32: |
| 23913 | case AArch64::FCVTNSv1i64: |
| 23914 | case AArch64::FCVTNSv2f32: |
| 23915 | case AArch64::FCVTNSv2f64: |
| 23916 | case AArch64::FCVTNSv4f16: |
| 23917 | case AArch64::FCVTNSv4f32: |
| 23918 | case AArch64::FCVTNSv8f16: |
| 23919 | case AArch64::FCVTNUDHr: |
| 23920 | case AArch64::FCVTNUDSr: |
| 23921 | case AArch64::FCVTNUSDr: |
| 23922 | case AArch64::FCVTNUSHr: |
| 23923 | case AArch64::FCVTNUUWDr: |
| 23924 | case AArch64::FCVTNUUWHr: |
| 23925 | case AArch64::FCVTNUUWSr: |
| 23926 | case AArch64::FCVTNUUXDr: |
| 23927 | case AArch64::FCVTNUUXHr: |
| 23928 | case AArch64::FCVTNUUXSr: |
| 23929 | case AArch64::FCVTNUv1f16: |
| 23930 | case AArch64::FCVTNUv1i32: |
| 23931 | case AArch64::FCVTNUv1i64: |
| 23932 | case AArch64::FCVTNUv2f32: |
| 23933 | case AArch64::FCVTNUv2f64: |
| 23934 | case AArch64::FCVTNUv4f16: |
| 23935 | case AArch64::FCVTNUv4f32: |
| 23936 | case AArch64::FCVTNUv8f16: |
| 23937 | case AArch64::FCVTNv2i32: |
| 23938 | case AArch64::FCVTNv4i16: |
| 23939 | case AArch64::FCVTPSDHr: |
| 23940 | case AArch64::FCVTPSDSr: |
| 23941 | case AArch64::FCVTPSSDr: |
| 23942 | case AArch64::FCVTPSSHr: |
| 23943 | case AArch64::FCVTPSUWDr: |
| 23944 | case AArch64::FCVTPSUWHr: |
| 23945 | case AArch64::FCVTPSUWSr: |
| 23946 | case AArch64::FCVTPSUXDr: |
| 23947 | case AArch64::FCVTPSUXHr: |
| 23948 | case AArch64::FCVTPSUXSr: |
| 23949 | case AArch64::FCVTPSv1f16: |
| 23950 | case AArch64::FCVTPSv1i32: |
| 23951 | case AArch64::FCVTPSv1i64: |
| 23952 | case AArch64::FCVTPSv2f32: |
| 23953 | case AArch64::FCVTPSv2f64: |
| 23954 | case AArch64::FCVTPSv4f16: |
| 23955 | case AArch64::FCVTPSv4f32: |
| 23956 | case AArch64::FCVTPSv8f16: |
| 23957 | case AArch64::FCVTPUDHr: |
| 23958 | case AArch64::FCVTPUDSr: |
| 23959 | case AArch64::FCVTPUSDr: |
| 23960 | case AArch64::FCVTPUSHr: |
| 23961 | case AArch64::FCVTPUUWDr: |
| 23962 | case AArch64::FCVTPUUWHr: |
| 23963 | case AArch64::FCVTPUUWSr: |
| 23964 | case AArch64::FCVTPUUXDr: |
| 23965 | case AArch64::FCVTPUUXHr: |
| 23966 | case AArch64::FCVTPUUXSr: |
| 23967 | case AArch64::FCVTPUv1f16: |
| 23968 | case AArch64::FCVTPUv1i32: |
| 23969 | case AArch64::FCVTPUv1i64: |
| 23970 | case AArch64::FCVTPUv2f32: |
| 23971 | case AArch64::FCVTPUv2f64: |
| 23972 | case AArch64::FCVTPUv4f16: |
| 23973 | case AArch64::FCVTPUv4f32: |
| 23974 | case AArch64::FCVTPUv8f16: |
| 23975 | case AArch64::FCVTSDr: |
| 23976 | case AArch64::FCVTSHr: |
| 23977 | case AArch64::FCVTXNv1i64: |
| 23978 | case AArch64::FCVTXNv2f32: |
| 23979 | case AArch64::FCVTZSDHr: |
| 23980 | case AArch64::FCVTZSDSr: |
| 23981 | case AArch64::FCVTZSSDr: |
| 23982 | case AArch64::FCVTZSSHr: |
| 23983 | case AArch64::FCVTZSUWDr: |
| 23984 | case AArch64::FCVTZSUWHr: |
| 23985 | case AArch64::FCVTZSUWSr: |
| 23986 | case AArch64::FCVTZSUXDr: |
| 23987 | case AArch64::FCVTZSUXHr: |
| 23988 | case AArch64::FCVTZSUXSr: |
| 23989 | case AArch64::FCVTZSv1f16: |
| 23990 | case AArch64::FCVTZSv1i32: |
| 23991 | case AArch64::FCVTZSv1i64: |
| 23992 | case AArch64::FCVTZSv2f32: |
| 23993 | case AArch64::FCVTZSv2f64: |
| 23994 | case AArch64::FCVTZSv4f16: |
| 23995 | case AArch64::FCVTZSv4f32: |
| 23996 | case AArch64::FCVTZSv8f16: |
| 23997 | case AArch64::FCVTZUDHr: |
| 23998 | case AArch64::FCVTZUDSr: |
| 23999 | case AArch64::FCVTZUSDr: |
| 24000 | case AArch64::FCVTZUSHr: |
| 24001 | case AArch64::FCVTZUUWDr: |
| 24002 | case AArch64::FCVTZUUWHr: |
| 24003 | case AArch64::FCVTZUUWSr: |
| 24004 | case AArch64::FCVTZUUXDr: |
| 24005 | case AArch64::FCVTZUUXHr: |
| 24006 | case AArch64::FCVTZUUXSr: |
| 24007 | case AArch64::FCVTZUv1f16: |
| 24008 | case AArch64::FCVTZUv1i32: |
| 24009 | case AArch64::FCVTZUv1i64: |
| 24010 | case AArch64::FCVTZUv2f32: |
| 24011 | case AArch64::FCVTZUv2f64: |
| 24012 | case AArch64::FCVTZUv4f16: |
| 24013 | case AArch64::FCVTZUv4f32: |
| 24014 | case AArch64::FCVTZUv8f16: |
| 24015 | case AArch64::FJCVTZS: |
| 24016 | case AArch64::FMAXNMPv2i16p: |
| 24017 | case AArch64::FMAXNMPv2i32p: |
| 24018 | case AArch64::FMAXNMPv2i64p: |
| 24019 | case AArch64::FMAXNMVv4i16v: |
| 24020 | case AArch64::FMAXNMVv4i32v: |
| 24021 | case AArch64::FMAXNMVv8i16v: |
| 24022 | case AArch64::FMAXPv2i16p: |
| 24023 | case AArch64::FMAXPv2i32p: |
| 24024 | case AArch64::FMAXPv2i64p: |
| 24025 | case AArch64::FMAXVv4i16v: |
| 24026 | case AArch64::FMAXVv4i32v: |
| 24027 | case AArch64::FMAXVv8i16v: |
| 24028 | case AArch64::FMINNMPv2i16p: |
| 24029 | case AArch64::FMINNMPv2i32p: |
| 24030 | case AArch64::FMINNMPv2i64p: |
| 24031 | case AArch64::FMINNMVv4i16v: |
| 24032 | case AArch64::FMINNMVv4i32v: |
| 24033 | case AArch64::FMINNMVv8i16v: |
| 24034 | case AArch64::FMINPv2i16p: |
| 24035 | case AArch64::FMINPv2i32p: |
| 24036 | case AArch64::FMINPv2i64p: |
| 24037 | case AArch64::FMINVv4i16v: |
| 24038 | case AArch64::FMINVv4i32v: |
| 24039 | case AArch64::FMINVv8i16v: |
| 24040 | case AArch64::FMOVDXHighr: |
| 24041 | case AArch64::FMOVDXr: |
| 24042 | case AArch64::FMOVDr: |
| 24043 | case AArch64::FMOVHWr: |
| 24044 | case AArch64::FMOVHXr: |
| 24045 | case AArch64::FMOVHr: |
| 24046 | case AArch64::FMOVSWr: |
| 24047 | case AArch64::FMOVSr: |
| 24048 | case AArch64::FMOVWHr: |
| 24049 | case AArch64::FMOVWSr: |
| 24050 | case AArch64::FMOVXDHighr: |
| 24051 | case AArch64::FMOVXDr: |
| 24052 | case AArch64::FMOVXHr: |
| 24053 | case AArch64::FNEGDr: |
| 24054 | case AArch64::FNEGHr: |
| 24055 | case AArch64::FNEGSr: |
| 24056 | case AArch64::FNEGv2f32: |
| 24057 | case AArch64::FNEGv2f64: |
| 24058 | case AArch64::FNEGv4f16: |
| 24059 | case AArch64::FNEGv4f32: |
| 24060 | case AArch64::FNEGv8f16: |
| 24061 | case AArch64::FRECPEv1f16: |
| 24062 | case AArch64::FRECPEv1i32: |
| 24063 | case AArch64::FRECPEv1i64: |
| 24064 | case AArch64::FRECPEv2f32: |
| 24065 | case AArch64::FRECPEv2f64: |
| 24066 | case AArch64::FRECPEv4f16: |
| 24067 | case AArch64::FRECPEv4f32: |
| 24068 | case AArch64::FRECPEv8f16: |
| 24069 | case AArch64::FRECPXv1f16: |
| 24070 | case AArch64::FRECPXv1i32: |
| 24071 | case AArch64::FRECPXv1i64: |
| 24072 | case AArch64::FRINT32XDr: |
| 24073 | case AArch64::FRINT32XSr: |
| 24074 | case AArch64::FRINT32Xv2f32: |
| 24075 | case AArch64::FRINT32Xv2f64: |
| 24076 | case AArch64::FRINT32Xv4f32: |
| 24077 | case AArch64::FRINT32ZDr: |
| 24078 | case AArch64::FRINT32ZSr: |
| 24079 | case AArch64::FRINT32Zv2f32: |
| 24080 | case AArch64::FRINT32Zv2f64: |
| 24081 | case AArch64::FRINT32Zv4f32: |
| 24082 | case AArch64::FRINT64XDr: |
| 24083 | case AArch64::FRINT64XSr: |
| 24084 | case AArch64::FRINT64Xv2f32: |
| 24085 | case AArch64::FRINT64Xv2f64: |
| 24086 | case AArch64::FRINT64Xv4f32: |
| 24087 | case AArch64::FRINT64ZDr: |
| 24088 | case AArch64::FRINT64ZSr: |
| 24089 | case AArch64::FRINT64Zv2f32: |
| 24090 | case AArch64::FRINT64Zv2f64: |
| 24091 | case AArch64::FRINT64Zv4f32: |
| 24092 | case AArch64::FRINTADr: |
| 24093 | case AArch64::FRINTAHr: |
| 24094 | case AArch64::FRINTASr: |
| 24095 | case AArch64::FRINTAv2f32: |
| 24096 | case AArch64::FRINTAv2f64: |
| 24097 | case AArch64::FRINTAv4f16: |
| 24098 | case AArch64::FRINTAv4f32: |
| 24099 | case AArch64::FRINTAv8f16: |
| 24100 | case AArch64::FRINTIDr: |
| 24101 | case AArch64::FRINTIHr: |
| 24102 | case AArch64::FRINTISr: |
| 24103 | case AArch64::FRINTIv2f32: |
| 24104 | case AArch64::FRINTIv2f64: |
| 24105 | case AArch64::FRINTIv4f16: |
| 24106 | case AArch64::FRINTIv4f32: |
| 24107 | case AArch64::FRINTIv8f16: |
| 24108 | case AArch64::FRINTMDr: |
| 24109 | case AArch64::FRINTMHr: |
| 24110 | case AArch64::FRINTMSr: |
| 24111 | case AArch64::FRINTMv2f32: |
| 24112 | case AArch64::FRINTMv2f64: |
| 24113 | case AArch64::FRINTMv4f16: |
| 24114 | case AArch64::FRINTMv4f32: |
| 24115 | case AArch64::FRINTMv8f16: |
| 24116 | case AArch64::FRINTNDr: |
| 24117 | case AArch64::FRINTNHr: |
| 24118 | case AArch64::FRINTNSr: |
| 24119 | case AArch64::FRINTNv2f32: |
| 24120 | case AArch64::FRINTNv2f64: |
| 24121 | case AArch64::FRINTNv4f16: |
| 24122 | case AArch64::FRINTNv4f32: |
| 24123 | case AArch64::FRINTNv8f16: |
| 24124 | case AArch64::FRINTPDr: |
| 24125 | case AArch64::FRINTPHr: |
| 24126 | case AArch64::FRINTPSr: |
| 24127 | case AArch64::FRINTPv2f32: |
| 24128 | case AArch64::FRINTPv2f64: |
| 24129 | case AArch64::FRINTPv4f16: |
| 24130 | case AArch64::FRINTPv4f32: |
| 24131 | case AArch64::FRINTPv8f16: |
| 24132 | case AArch64::FRINTXDr: |
| 24133 | case AArch64::FRINTXHr: |
| 24134 | case AArch64::FRINTXSr: |
| 24135 | case AArch64::FRINTXv2f32: |
| 24136 | case AArch64::FRINTXv2f64: |
| 24137 | case AArch64::FRINTXv4f16: |
| 24138 | case AArch64::FRINTXv4f32: |
| 24139 | case AArch64::FRINTXv8f16: |
| 24140 | case AArch64::FRINTZDr: |
| 24141 | case AArch64::FRINTZHr: |
| 24142 | case AArch64::FRINTZSr: |
| 24143 | case AArch64::FRINTZv2f32: |
| 24144 | case AArch64::FRINTZv2f64: |
| 24145 | case AArch64::FRINTZv4f16: |
| 24146 | case AArch64::FRINTZv4f32: |
| 24147 | case AArch64::FRINTZv8f16: |
| 24148 | case AArch64::FRSQRTEv1f16: |
| 24149 | case AArch64::FRSQRTEv1i32: |
| 24150 | case AArch64::FRSQRTEv1i64: |
| 24151 | case AArch64::FRSQRTEv2f32: |
| 24152 | case AArch64::FRSQRTEv2f64: |
| 24153 | case AArch64::FRSQRTEv4f16: |
| 24154 | case AArch64::FRSQRTEv4f32: |
| 24155 | case AArch64::FRSQRTEv8f16: |
| 24156 | case AArch64::FSQRTDr: |
| 24157 | case AArch64::FSQRTHr: |
| 24158 | case AArch64::FSQRTSr: |
| 24159 | case AArch64::FSQRTv2f32: |
| 24160 | case AArch64::FSQRTv2f64: |
| 24161 | case AArch64::FSQRTv4f16: |
| 24162 | case AArch64::FSQRTv4f32: |
| 24163 | case AArch64::FSQRTv8f16: |
| 24164 | case AArch64::NEGv16i8: |
| 24165 | case AArch64::NEGv1i64: |
| 24166 | case AArch64::NEGv2i32: |
| 24167 | case AArch64::NEGv2i64: |
| 24168 | case AArch64::NEGv4i16: |
| 24169 | case AArch64::NEGv4i32: |
| 24170 | case AArch64::NEGv8i16: |
| 24171 | case AArch64::NEGv8i8: |
| 24172 | case AArch64::NOTv16i8: |
| 24173 | case AArch64::NOTv8i8: |
| 24174 | case AArch64::RBITWr: |
| 24175 | case AArch64::RBITXr: |
| 24176 | case AArch64::RBITv16i8: |
| 24177 | case AArch64::RBITv8i8: |
| 24178 | case AArch64::REV16Wr: |
| 24179 | case AArch64::REV16Xr: |
| 24180 | case AArch64::REV16v16i8: |
| 24181 | case AArch64::REV16v8i8: |
| 24182 | case AArch64::REV32Xr: |
| 24183 | case AArch64::REV32v16i8: |
| 24184 | case AArch64::REV32v4i16: |
| 24185 | case AArch64::REV32v8i16: |
| 24186 | case AArch64::REV32v8i8: |
| 24187 | case AArch64::REV64v16i8: |
| 24188 | case AArch64::REV64v2i32: |
| 24189 | case AArch64::REV64v4i16: |
| 24190 | case AArch64::REV64v4i32: |
| 24191 | case AArch64::REV64v8i16: |
| 24192 | case AArch64::REV64v8i8: |
| 24193 | case AArch64::REVWr: |
| 24194 | case AArch64::REVXr: |
| 24195 | case AArch64::SADDLPv16i8_v8i16: |
| 24196 | case AArch64::SADDLPv2i32_v1i64: |
| 24197 | case AArch64::SADDLPv4i16_v2i32: |
| 24198 | case AArch64::SADDLPv4i32_v2i64: |
| 24199 | case AArch64::SADDLPv8i16_v4i32: |
| 24200 | case AArch64::SADDLPv8i8_v4i16: |
| 24201 | case AArch64::SADDLVv16i8v: |
| 24202 | case AArch64::SADDLVv4i16v: |
| 24203 | case AArch64::SADDLVv4i32v: |
| 24204 | case AArch64::SADDLVv8i16v: |
| 24205 | case AArch64::SADDLVv8i8v: |
| 24206 | case AArch64::SCVTFDSr: |
| 24207 | case AArch64::SCVTFHDr: |
| 24208 | case AArch64::SCVTFHSr: |
| 24209 | case AArch64::SCVTFSDr: |
| 24210 | case AArch64::SCVTFUWDri: |
| 24211 | case AArch64::SCVTFUWHri: |
| 24212 | case AArch64::SCVTFUWSri: |
| 24213 | case AArch64::SCVTFUXDri: |
| 24214 | case AArch64::SCVTFUXHri: |
| 24215 | case AArch64::SCVTFUXSri: |
| 24216 | case AArch64::SCVTFv1i16: |
| 24217 | case AArch64::SCVTFv1i32: |
| 24218 | case AArch64::SCVTFv1i64: |
| 24219 | case AArch64::SCVTFv2f32: |
| 24220 | case AArch64::SCVTFv2f64: |
| 24221 | case AArch64::SCVTFv4f16: |
| 24222 | case AArch64::SCVTFv4f32: |
| 24223 | case AArch64::SCVTFv8f16: |
| 24224 | case AArch64::SHA1Hrr: |
| 24225 | case AArch64::SHLLv16i8: |
| 24226 | case AArch64::SHLLv2i32: |
| 24227 | case AArch64::SHLLv4i16: |
| 24228 | case AArch64::SHLLv4i32: |
| 24229 | case AArch64::SHLLv8i16: |
| 24230 | case AArch64::SHLLv8i8: |
| 24231 | case AArch64::SMAXVv16i8v: |
| 24232 | case AArch64::SMAXVv4i16v: |
| 24233 | case AArch64::SMAXVv4i32v: |
| 24234 | case AArch64::SMAXVv8i16v: |
| 24235 | case AArch64::SMAXVv8i8v: |
| 24236 | case AArch64::SMINVv16i8v: |
| 24237 | case AArch64::SMINVv4i16v: |
| 24238 | case AArch64::SMINVv4i32v: |
| 24239 | case AArch64::SMINVv8i16v: |
| 24240 | case AArch64::SMINVv8i8v: |
| 24241 | case AArch64::SMOVvi16to32_idx0: |
| 24242 | case AArch64::SMOVvi16to64_idx0: |
| 24243 | case AArch64::SMOVvi32to64_idx0: |
| 24244 | case AArch64::SMOVvi8to32_idx0: |
| 24245 | case AArch64::SMOVvi8to64_idx0: |
| 24246 | case AArch64::SQABSv16i8: |
| 24247 | case AArch64::SQABSv1i16: |
| 24248 | case AArch64::SQABSv1i32: |
| 24249 | case AArch64::SQABSv1i64: |
| 24250 | case AArch64::SQABSv1i8: |
| 24251 | case AArch64::SQABSv2i32: |
| 24252 | case AArch64::SQABSv2i64: |
| 24253 | case AArch64::SQABSv4i16: |
| 24254 | case AArch64::SQABSv4i32: |
| 24255 | case AArch64::SQABSv8i16: |
| 24256 | case AArch64::SQABSv8i8: |
| 24257 | case AArch64::SQNEGv16i8: |
| 24258 | case AArch64::SQNEGv1i16: |
| 24259 | case AArch64::SQNEGv1i32: |
| 24260 | case AArch64::SQNEGv1i64: |
| 24261 | case AArch64::SQNEGv1i8: |
| 24262 | case AArch64::SQNEGv2i32: |
| 24263 | case AArch64::SQNEGv2i64: |
| 24264 | case AArch64::SQNEGv4i16: |
| 24265 | case AArch64::SQNEGv4i32: |
| 24266 | case AArch64::SQNEGv8i16: |
| 24267 | case AArch64::SQNEGv8i8: |
| 24268 | case AArch64::SQXTNv1i16: |
| 24269 | case AArch64::SQXTNv1i32: |
| 24270 | case AArch64::SQXTNv1i8: |
| 24271 | case AArch64::SQXTNv2i32: |
| 24272 | case AArch64::SQXTNv4i16: |
| 24273 | case AArch64::SQXTNv8i8: |
| 24274 | case AArch64::SQXTUNv1i16: |
| 24275 | case AArch64::SQXTUNv1i32: |
| 24276 | case AArch64::SQXTUNv1i8: |
| 24277 | case AArch64::SQXTUNv2i32: |
| 24278 | case AArch64::SQXTUNv4i16: |
| 24279 | case AArch64::SQXTUNv8i8: |
| 24280 | case AArch64::UADDLPv16i8_v8i16: |
| 24281 | case AArch64::UADDLPv2i32_v1i64: |
| 24282 | case AArch64::UADDLPv4i16_v2i32: |
| 24283 | case AArch64::UADDLPv4i32_v2i64: |
| 24284 | case AArch64::UADDLPv8i16_v4i32: |
| 24285 | case AArch64::UADDLPv8i8_v4i16: |
| 24286 | case AArch64::UADDLVv16i8v: |
| 24287 | case AArch64::UADDLVv4i16v: |
| 24288 | case AArch64::UADDLVv4i32v: |
| 24289 | case AArch64::UADDLVv8i16v: |
| 24290 | case AArch64::UADDLVv8i8v: |
| 24291 | case AArch64::UCVTFDSr: |
| 24292 | case AArch64::UCVTFHDr: |
| 24293 | case AArch64::UCVTFHSr: |
| 24294 | case AArch64::UCVTFSDr: |
| 24295 | case AArch64::UCVTFUWDri: |
| 24296 | case AArch64::UCVTFUWHri: |
| 24297 | case AArch64::UCVTFUWSri: |
| 24298 | case AArch64::UCVTFUXDri: |
| 24299 | case AArch64::UCVTFUXHri: |
| 24300 | case AArch64::UCVTFUXSri: |
| 24301 | case AArch64::UCVTFv1i16: |
| 24302 | case AArch64::UCVTFv1i32: |
| 24303 | case AArch64::UCVTFv1i64: |
| 24304 | case AArch64::UCVTFv2f32: |
| 24305 | case AArch64::UCVTFv2f64: |
| 24306 | case AArch64::UCVTFv4f16: |
| 24307 | case AArch64::UCVTFv4f32: |
| 24308 | case AArch64::UCVTFv8f16: |
| 24309 | case AArch64::UMAXVv16i8v: |
| 24310 | case AArch64::UMAXVv4i16v: |
| 24311 | case AArch64::UMAXVv4i32v: |
| 24312 | case AArch64::UMAXVv8i16v: |
| 24313 | case AArch64::UMAXVv8i8v: |
| 24314 | case AArch64::UMINVv16i8v: |
| 24315 | case AArch64::UMINVv4i16v: |
| 24316 | case AArch64::UMINVv4i32v: |
| 24317 | case AArch64::UMINVv8i16v: |
| 24318 | case AArch64::UMINVv8i8v: |
| 24319 | case AArch64::UMOVvi16_idx0: |
| 24320 | case AArch64::UMOVvi32_idx0: |
| 24321 | case AArch64::UMOVvi64_idx0: |
| 24322 | case AArch64::UMOVvi8_idx0: |
| 24323 | case AArch64::UQXTNv1i16: |
| 24324 | case AArch64::UQXTNv1i32: |
| 24325 | case AArch64::UQXTNv1i8: |
| 24326 | case AArch64::UQXTNv2i32: |
| 24327 | case AArch64::UQXTNv4i16: |
| 24328 | case AArch64::UQXTNv8i8: |
| 24329 | case AArch64::URECPEv2i32: |
| 24330 | case AArch64::URECPEv4i32: |
| 24331 | case AArch64::URSQRTEv2i32: |
| 24332 | case AArch64::URSQRTEv4i32: |
| 24333 | case AArch64::XTNv2i32: |
| 24334 | case AArch64::XTNv4i16: |
| 24335 | case AArch64::XTNv8i8: { |
| 24336 | switch (OpNum) { |
| 24337 | case 0: |
| 24338 | // op: Rd |
| 24339 | return 0; |
| 24340 | case 1: |
| 24341 | // op: Rn |
| 24342 | return 5; |
| 24343 | } |
| 24344 | break; |
| 24345 | } |
| 24346 | case AArch64::FMOVDi: |
| 24347 | case AArch64::FMOVHi: |
| 24348 | case AArch64::FMOVSi: { |
| 24349 | switch (OpNum) { |
| 24350 | case 0: |
| 24351 | // op: Rd |
| 24352 | return 0; |
| 24353 | case 1: |
| 24354 | // op: imm |
| 24355 | return 13; |
| 24356 | } |
| 24357 | break; |
| 24358 | } |
| 24359 | case AArch64::MOVNWi: |
| 24360 | case AArch64::MOVNXi: |
| 24361 | case AArch64::MOVZWi: |
| 24362 | case AArch64::MOVZXi: { |
| 24363 | switch (OpNum) { |
| 24364 | case 0: |
| 24365 | // op: Rd |
| 24366 | return 0; |
| 24367 | case 1: |
| 24368 | // op: imm |
| 24369 | return 5; |
| 24370 | case 2: |
| 24371 | // op: shift |
| 24372 | return 21; |
| 24373 | } |
| 24374 | break; |
| 24375 | } |
| 24376 | case AArch64::RDSVLI_XI: |
| 24377 | case AArch64::RDVLI_XI: { |
| 24378 | switch (OpNum) { |
| 24379 | case 0: |
| 24380 | // op: Rd |
| 24381 | return 0; |
| 24382 | case 1: |
| 24383 | // op: imm6 |
| 24384 | return 5; |
| 24385 | } |
| 24386 | break; |
| 24387 | } |
| 24388 | case AArch64::MOVIv2s_msl: |
| 24389 | case AArch64::MOVIv4s_msl: |
| 24390 | case AArch64::MVNIv2s_msl: |
| 24391 | case AArch64::MVNIv4s_msl: { |
| 24392 | switch (OpNum) { |
| 24393 | case 0: |
| 24394 | // op: Rd |
| 24395 | return 0; |
| 24396 | case 1: |
| 24397 | // op: imm8 |
| 24398 | return 5; |
| 24399 | case 2: |
| 24400 | // op: shift |
| 24401 | return 12; |
| 24402 | } |
| 24403 | break; |
| 24404 | } |
| 24405 | case AArch64::MOVIv2i32: |
| 24406 | case AArch64::MOVIv4i16: |
| 24407 | case AArch64::MOVIv4i32: |
| 24408 | case AArch64::MOVIv8i16: |
| 24409 | case AArch64::MVNIv2i32: |
| 24410 | case AArch64::MVNIv4i16: |
| 24411 | case AArch64::MVNIv4i32: |
| 24412 | case AArch64::MVNIv8i16: { |
| 24413 | switch (OpNum) { |
| 24414 | case 0: |
| 24415 | // op: Rd |
| 24416 | return 0; |
| 24417 | case 1: |
| 24418 | // op: imm8 |
| 24419 | return 5; |
| 24420 | case 2: |
| 24421 | // op: shift |
| 24422 | return 13; |
| 24423 | } |
| 24424 | break; |
| 24425 | } |
| 24426 | case AArch64::FMOVv2f32_ns: |
| 24427 | case AArch64::FMOVv2f64_ns: |
| 24428 | case AArch64::FMOVv4f16_ns: |
| 24429 | case AArch64::FMOVv4f32_ns: |
| 24430 | case AArch64::FMOVv8f16_ns: |
| 24431 | case AArch64::MOVID: |
| 24432 | case AArch64::MOVIv16b_ns: |
| 24433 | case AArch64::MOVIv2d_ns: |
| 24434 | case AArch64::MOVIv8b_ns: { |
| 24435 | switch (OpNum) { |
| 24436 | case 0: |
| 24437 | // op: Rd |
| 24438 | return 0; |
| 24439 | case 1: |
| 24440 | // op: imm8 |
| 24441 | return 5; |
| 24442 | } |
| 24443 | break; |
| 24444 | } |
| 24445 | case AArch64::BFMWri: |
| 24446 | case AArch64::BFMXri: { |
| 24447 | switch (OpNum) { |
| 24448 | case 0: |
| 24449 | // op: Rd |
| 24450 | return 0; |
| 24451 | case 2: |
| 24452 | // op: Rn |
| 24453 | return 5; |
| 24454 | case 3: |
| 24455 | // op: immr |
| 24456 | return 16; |
| 24457 | case 4: |
| 24458 | // op: imms |
| 24459 | return 10; |
| 24460 | } |
| 24461 | break; |
| 24462 | } |
| 24463 | case AArch64::MOVKWi: |
| 24464 | case AArch64::MOVKXi: { |
| 24465 | switch (OpNum) { |
| 24466 | case 0: |
| 24467 | // op: Rd |
| 24468 | return 0; |
| 24469 | case 2: |
| 24470 | // op: imm |
| 24471 | return 5; |
| 24472 | case 3: |
| 24473 | // op: shift |
| 24474 | return 21; |
| 24475 | } |
| 24476 | break; |
| 24477 | } |
| 24478 | case AArch64::CNTB_XPiI: |
| 24479 | case AArch64::CNTD_XPiI: |
| 24480 | case AArch64::CNTH_XPiI: |
| 24481 | case AArch64::CNTW_XPiI: { |
| 24482 | switch (OpNum) { |
| 24483 | case 0: |
| 24484 | // op: Rd |
| 24485 | return 0; |
| 24486 | case 2: |
| 24487 | // op: imm4 |
| 24488 | return 16; |
| 24489 | case 1: |
| 24490 | // op: pattern |
| 24491 | return 5; |
| 24492 | } |
| 24493 | break; |
| 24494 | } |
| 24495 | case AArch64::XPACD: |
| 24496 | case AArch64::XPACI: { |
| 24497 | switch (OpNum) { |
| 24498 | case 0: |
| 24499 | // op: Rd |
| 24500 | return 0; |
| 24501 | } |
| 24502 | break; |
| 24503 | } |
| 24504 | case AArch64::DECP_XP_B: |
| 24505 | case AArch64::DECP_XP_D: |
| 24506 | case AArch64::DECP_XP_H: |
| 24507 | case AArch64::DECP_XP_S: |
| 24508 | case AArch64::INCP_XP_B: |
| 24509 | case AArch64::INCP_XP_D: |
| 24510 | case AArch64::INCP_XP_H: |
| 24511 | case AArch64::INCP_XP_S: |
| 24512 | case AArch64::SQDECP_XPWd_B: |
| 24513 | case AArch64::SQDECP_XPWd_D: |
| 24514 | case AArch64::SQDECP_XPWd_H: |
| 24515 | case AArch64::SQDECP_XPWd_S: |
| 24516 | case AArch64::SQDECP_XP_B: |
| 24517 | case AArch64::SQDECP_XP_D: |
| 24518 | case AArch64::SQDECP_XP_H: |
| 24519 | case AArch64::SQDECP_XP_S: |
| 24520 | case AArch64::SQINCP_XPWd_B: |
| 24521 | case AArch64::SQINCP_XPWd_D: |
| 24522 | case AArch64::SQINCP_XPWd_H: |
| 24523 | case AArch64::SQINCP_XPWd_S: |
| 24524 | case AArch64::SQINCP_XP_B: |
| 24525 | case AArch64::SQINCP_XP_D: |
| 24526 | case AArch64::SQINCP_XP_H: |
| 24527 | case AArch64::SQINCP_XP_S: |
| 24528 | case AArch64::UQDECP_WP_B: |
| 24529 | case AArch64::UQDECP_WP_D: |
| 24530 | case AArch64::UQDECP_WP_H: |
| 24531 | case AArch64::UQDECP_WP_S: |
| 24532 | case AArch64::UQDECP_XP_B: |
| 24533 | case AArch64::UQDECP_XP_D: |
| 24534 | case AArch64::UQDECP_XP_H: |
| 24535 | case AArch64::UQDECP_XP_S: |
| 24536 | case AArch64::UQINCP_WP_B: |
| 24537 | case AArch64::UQINCP_WP_D: |
| 24538 | case AArch64::UQINCP_WP_H: |
| 24539 | case AArch64::UQINCP_WP_S: |
| 24540 | case AArch64::UQINCP_XP_B: |
| 24541 | case AArch64::UQINCP_XP_D: |
| 24542 | case AArch64::UQINCP_XP_H: |
| 24543 | case AArch64::UQINCP_XP_S: { |
| 24544 | switch (OpNum) { |
| 24545 | case 0: |
| 24546 | // op: Rdn |
| 24547 | return 0; |
| 24548 | case 1: |
| 24549 | // op: Pg |
| 24550 | return 5; |
| 24551 | } |
| 24552 | break; |
| 24553 | } |
| 24554 | case AArch64::DECB_XPiI: |
| 24555 | case AArch64::DECD_XPiI: |
| 24556 | case AArch64::DECH_XPiI: |
| 24557 | case AArch64::DECW_XPiI: |
| 24558 | case AArch64::INCB_XPiI: |
| 24559 | case AArch64::INCD_XPiI: |
| 24560 | case AArch64::INCH_XPiI: |
| 24561 | case AArch64::INCW_XPiI: |
| 24562 | case AArch64::SQDECB_XPiI: |
| 24563 | case AArch64::SQDECB_XPiWdI: |
| 24564 | case AArch64::SQDECD_XPiI: |
| 24565 | case AArch64::SQDECD_XPiWdI: |
| 24566 | case AArch64::SQDECH_XPiI: |
| 24567 | case AArch64::SQDECH_XPiWdI: |
| 24568 | case AArch64::SQDECW_XPiI: |
| 24569 | case AArch64::SQDECW_XPiWdI: |
| 24570 | case AArch64::SQINCB_XPiI: |
| 24571 | case AArch64::SQINCB_XPiWdI: |
| 24572 | case AArch64::SQINCD_XPiI: |
| 24573 | case AArch64::SQINCD_XPiWdI: |
| 24574 | case AArch64::SQINCH_XPiI: |
| 24575 | case AArch64::SQINCH_XPiWdI: |
| 24576 | case AArch64::SQINCW_XPiI: |
| 24577 | case AArch64::SQINCW_XPiWdI: |
| 24578 | case AArch64::UQDECB_WPiI: |
| 24579 | case AArch64::UQDECB_XPiI: |
| 24580 | case AArch64::UQDECD_WPiI: |
| 24581 | case AArch64::UQDECD_XPiI: |
| 24582 | case AArch64::UQDECH_WPiI: |
| 24583 | case AArch64::UQDECH_XPiI: |
| 24584 | case AArch64::UQDECW_WPiI: |
| 24585 | case AArch64::UQDECW_XPiI: |
| 24586 | case AArch64::UQINCB_WPiI: |
| 24587 | case AArch64::UQINCB_XPiI: |
| 24588 | case AArch64::UQINCD_WPiI: |
| 24589 | case AArch64::UQINCD_XPiI: |
| 24590 | case AArch64::UQINCH_WPiI: |
| 24591 | case AArch64::UQINCH_XPiI: |
| 24592 | case AArch64::UQINCW_WPiI: |
| 24593 | case AArch64::UQINCW_XPiI: { |
| 24594 | switch (OpNum) { |
| 24595 | case 0: |
| 24596 | // op: Rdn |
| 24597 | return 0; |
| 24598 | case 2: |
| 24599 | // op: pattern |
| 24600 | return 5; |
| 24601 | case 3: |
| 24602 | // op: imm4 |
| 24603 | return 16; |
| 24604 | } |
| 24605 | break; |
| 24606 | } |
| 24607 | case AArch64::RETAASPPCr: |
| 24608 | case AArch64::RETABSPPCr: { |
| 24609 | switch (OpNum) { |
| 24610 | case 0: |
| 24611 | // op: Rm |
| 24612 | return 0; |
| 24613 | } |
| 24614 | break; |
| 24615 | } |
| 24616 | case AArch64::BLRAA: |
| 24617 | case AArch64::BLRAB: |
| 24618 | case AArch64::BRAA: |
| 24619 | case AArch64::BRAB: { |
| 24620 | switch (OpNum) { |
| 24621 | case 0: |
| 24622 | // op: Rn |
| 24623 | return 5; |
| 24624 | case 1: |
| 24625 | // op: Rm |
| 24626 | return 0; |
| 24627 | } |
| 24628 | break; |
| 24629 | } |
| 24630 | case AArch64::CCMNWr: |
| 24631 | case AArch64::CCMNXr: |
| 24632 | case AArch64::CCMPWr: |
| 24633 | case AArch64::CCMPXr: |
| 24634 | case AArch64::FCCMPDrr: |
| 24635 | case AArch64::FCCMPEDrr: |
| 24636 | case AArch64::FCCMPEHrr: |
| 24637 | case AArch64::FCCMPESrr: |
| 24638 | case AArch64::FCCMPHrr: |
| 24639 | case AArch64::FCCMPSrr: { |
| 24640 | switch (OpNum) { |
| 24641 | case 0: |
| 24642 | // op: Rn |
| 24643 | return 5; |
| 24644 | case 1: |
| 24645 | // op: Rm |
| 24646 | return 16; |
| 24647 | case 2: |
| 24648 | // op: nzcv |
| 24649 | return 0; |
| 24650 | case 3: |
| 24651 | // op: cond |
| 24652 | return 12; |
| 24653 | } |
| 24654 | break; |
| 24655 | } |
| 24656 | case AArch64::RMIF: { |
| 24657 | switch (OpNum) { |
| 24658 | case 0: |
| 24659 | // op: Rn |
| 24660 | return 5; |
| 24661 | case 1: |
| 24662 | // op: imm |
| 24663 | return 15; |
| 24664 | case 2: |
| 24665 | // op: mask |
| 24666 | return 0; |
| 24667 | } |
| 24668 | break; |
| 24669 | } |
| 24670 | case AArch64::CCMNWi: |
| 24671 | case AArch64::CCMNXi: |
| 24672 | case AArch64::CCMPWi: |
| 24673 | case AArch64::CCMPXi: { |
| 24674 | switch (OpNum) { |
| 24675 | case 0: |
| 24676 | // op: Rn |
| 24677 | return 5; |
| 24678 | case 1: |
| 24679 | // op: imm |
| 24680 | return 16; |
| 24681 | case 2: |
| 24682 | // op: nzcv |
| 24683 | return 0; |
| 24684 | case 3: |
| 24685 | // op: cond |
| 24686 | return 12; |
| 24687 | } |
| 24688 | break; |
| 24689 | } |
| 24690 | case AArch64::AUTIASPPCr: |
| 24691 | case AArch64::AUTIBSPPCr: |
| 24692 | case AArch64::BLR: |
| 24693 | case AArch64::BLRAAZ: |
| 24694 | case AArch64::BLRABZ: |
| 24695 | case AArch64::BR: |
| 24696 | case AArch64::BRAAZ: |
| 24697 | case AArch64::BRABZ: |
| 24698 | case AArch64::FCMPDri: |
| 24699 | case AArch64::FCMPEDri: |
| 24700 | case AArch64::FCMPEHri: |
| 24701 | case AArch64::FCMPESri: |
| 24702 | case AArch64::FCMPHri: |
| 24703 | case AArch64::FCMPSri: |
| 24704 | case AArch64::RET: |
| 24705 | case AArch64::SETF16: |
| 24706 | case AArch64::SETF8: { |
| 24707 | switch (OpNum) { |
| 24708 | case 0: |
| 24709 | // op: Rn |
| 24710 | return 5; |
| 24711 | } |
| 24712 | break; |
| 24713 | } |
| 24714 | case AArch64::STBFADD: |
| 24715 | case AArch64::STBFADDL: |
| 24716 | case AArch64::STBFMAX: |
| 24717 | case AArch64::STBFMAXL: |
| 24718 | case AArch64::STBFMAXNM: |
| 24719 | case AArch64::STBFMAXNML: |
| 24720 | case AArch64::STBFMIN: |
| 24721 | case AArch64::STBFMINL: |
| 24722 | case AArch64::STBFMINNM: |
| 24723 | case AArch64::STBFMINNML: |
| 24724 | case AArch64::STFADDD: |
| 24725 | case AArch64::STFADDH: |
| 24726 | case AArch64::STFADDLD: |
| 24727 | case AArch64::STFADDLH: |
| 24728 | case AArch64::STFADDLS: |
| 24729 | case AArch64::STFADDS: |
| 24730 | case AArch64::STFMAXD: |
| 24731 | case AArch64::STFMAXH: |
| 24732 | case AArch64::STFMAXLD: |
| 24733 | case AArch64::STFMAXLH: |
| 24734 | case AArch64::STFMAXLS: |
| 24735 | case AArch64::STFMAXNMD: |
| 24736 | case AArch64::STFMAXNMH: |
| 24737 | case AArch64::STFMAXNMLD: |
| 24738 | case AArch64::STFMAXNMLH: |
| 24739 | case AArch64::STFMAXNMLS: |
| 24740 | case AArch64::STFMAXNMS: |
| 24741 | case AArch64::STFMAXS: |
| 24742 | case AArch64::STFMIND: |
| 24743 | case AArch64::STFMINH: |
| 24744 | case AArch64::STFMINLD: |
| 24745 | case AArch64::STFMINLH: |
| 24746 | case AArch64::STFMINLS: |
| 24747 | case AArch64::STFMINNMD: |
| 24748 | case AArch64::STFMINNMH: |
| 24749 | case AArch64::STFMINNMLD: |
| 24750 | case AArch64::STFMINNMLH: |
| 24751 | case AArch64::STFMINNMLS: |
| 24752 | case AArch64::STFMINNMS: |
| 24753 | case AArch64::STFMINS: { |
| 24754 | switch (OpNum) { |
| 24755 | case 0: |
| 24756 | // op: Rs |
| 24757 | return 16; |
| 24758 | case 1: |
| 24759 | // op: Rn |
| 24760 | return 5; |
| 24761 | } |
| 24762 | break; |
| 24763 | } |
| 24764 | case AArch64::LDRBBroW: |
| 24765 | case AArch64::LDRBBroX: |
| 24766 | case AArch64::LDRBroW: |
| 24767 | case AArch64::LDRBroX: |
| 24768 | case AArch64::LDRDroW: |
| 24769 | case AArch64::LDRDroX: |
| 24770 | case AArch64::LDRHHroW: |
| 24771 | case AArch64::LDRHHroX: |
| 24772 | case AArch64::LDRHroW: |
| 24773 | case AArch64::LDRHroX: |
| 24774 | case AArch64::LDRQroW: |
| 24775 | case AArch64::LDRQroX: |
| 24776 | case AArch64::LDRSBWroW: |
| 24777 | case AArch64::LDRSBWroX: |
| 24778 | case AArch64::LDRSBXroW: |
| 24779 | case AArch64::LDRSBXroX: |
| 24780 | case AArch64::LDRSHWroW: |
| 24781 | case AArch64::LDRSHWroX: |
| 24782 | case AArch64::LDRSHXroW: |
| 24783 | case AArch64::LDRSHXroX: |
| 24784 | case AArch64::LDRSWroW: |
| 24785 | case AArch64::LDRSWroX: |
| 24786 | case AArch64::LDRSroW: |
| 24787 | case AArch64::LDRSroX: |
| 24788 | case AArch64::LDRWroW: |
| 24789 | case AArch64::LDRWroX: |
| 24790 | case AArch64::LDRXroW: |
| 24791 | case AArch64::LDRXroX: |
| 24792 | case AArch64::PRFMroW: |
| 24793 | case AArch64::PRFMroX: |
| 24794 | case AArch64::STRBBroW: |
| 24795 | case AArch64::STRBBroX: |
| 24796 | case AArch64::STRBroW: |
| 24797 | case AArch64::STRBroX: |
| 24798 | case AArch64::STRDroW: |
| 24799 | case AArch64::STRDroX: |
| 24800 | case AArch64::STRHHroW: |
| 24801 | case AArch64::STRHHroX: |
| 24802 | case AArch64::STRHroW: |
| 24803 | case AArch64::STRHroX: |
| 24804 | case AArch64::STRQroW: |
| 24805 | case AArch64::STRQroX: |
| 24806 | case AArch64::STRSroW: |
| 24807 | case AArch64::STRSroX: |
| 24808 | case AArch64::STRWroW: |
| 24809 | case AArch64::STRWroX: |
| 24810 | case AArch64::STRXroW: |
| 24811 | case AArch64::STRXroX: { |
| 24812 | switch (OpNum) { |
| 24813 | case 0: |
| 24814 | // op: Rt |
| 24815 | return 0; |
| 24816 | case 1: |
| 24817 | // op: Rn |
| 24818 | return 5; |
| 24819 | case 2: |
| 24820 | // op: Rm |
| 24821 | return 16; |
| 24822 | case 3: |
| 24823 | // op: extend |
| 24824 | return 12; |
| 24825 | } |
| 24826 | break; |
| 24827 | } |
| 24828 | case AArch64::LDRBBui: |
| 24829 | case AArch64::LDRBui: |
| 24830 | case AArch64::LDRDui: |
| 24831 | case AArch64::LDRHHui: |
| 24832 | case AArch64::LDRHui: |
| 24833 | case AArch64::LDRQui: |
| 24834 | case AArch64::LDRSBWui: |
| 24835 | case AArch64::LDRSBXui: |
| 24836 | case AArch64::LDRSHWui: |
| 24837 | case AArch64::LDRSHXui: |
| 24838 | case AArch64::LDRSWui: |
| 24839 | case AArch64::LDRSui: |
| 24840 | case AArch64::LDRWui: |
| 24841 | case AArch64::LDRXui: |
| 24842 | case AArch64::PRFMui: |
| 24843 | case AArch64::STRBBui: |
| 24844 | case AArch64::STRBui: |
| 24845 | case AArch64::STRDui: |
| 24846 | case AArch64::STRHHui: |
| 24847 | case AArch64::STRHui: |
| 24848 | case AArch64::STRQui: |
| 24849 | case AArch64::STRSui: |
| 24850 | case AArch64::STRWui: |
| 24851 | case AArch64::STRXui: { |
| 24852 | switch (OpNum) { |
| 24853 | case 0: |
| 24854 | // op: Rt |
| 24855 | return 0; |
| 24856 | case 1: |
| 24857 | // op: Rn |
| 24858 | return 5; |
| 24859 | case 2: |
| 24860 | // op: offset |
| 24861 | return 10; |
| 24862 | } |
| 24863 | break; |
| 24864 | } |
| 24865 | case AArch64::LDAPURBi: |
| 24866 | case AArch64::LDAPURHi: |
| 24867 | case AArch64::LDAPURSBWi: |
| 24868 | case AArch64::LDAPURSBXi: |
| 24869 | case AArch64::LDAPURSHWi: |
| 24870 | case AArch64::LDAPURSHXi: |
| 24871 | case AArch64::LDAPURSWi: |
| 24872 | case AArch64::LDAPURXi: |
| 24873 | case AArch64::LDAPURi: |
| 24874 | case AArch64::LDTRBi: |
| 24875 | case AArch64::LDTRHi: |
| 24876 | case AArch64::LDTRSBWi: |
| 24877 | case AArch64::LDTRSBXi: |
| 24878 | case AArch64::LDTRSHWi: |
| 24879 | case AArch64::LDTRSHXi: |
| 24880 | case AArch64::LDTRSWi: |
| 24881 | case AArch64::LDTRWi: |
| 24882 | case AArch64::LDTRXi: |
| 24883 | case AArch64::LDURBBi: |
| 24884 | case AArch64::LDURBi: |
| 24885 | case AArch64::LDURDi: |
| 24886 | case AArch64::LDURHHi: |
| 24887 | case AArch64::LDURHi: |
| 24888 | case AArch64::LDURQi: |
| 24889 | case AArch64::LDURSBWi: |
| 24890 | case AArch64::LDURSBXi: |
| 24891 | case AArch64::LDURSHWi: |
| 24892 | case AArch64::LDURSHXi: |
| 24893 | case AArch64::LDURSWi: |
| 24894 | case AArch64::LDURSi: |
| 24895 | case AArch64::LDURWi: |
| 24896 | case AArch64::LDURXi: |
| 24897 | case AArch64::PRFUMi: |
| 24898 | case AArch64::STLURBi: |
| 24899 | case AArch64::STLURHi: |
| 24900 | case AArch64::STLURWi: |
| 24901 | case AArch64::STLURXi: |
| 24902 | case AArch64::STTRBi: |
| 24903 | case AArch64::STTRHi: |
| 24904 | case AArch64::STTRWi: |
| 24905 | case AArch64::STTRXi: |
| 24906 | case AArch64::STURBBi: |
| 24907 | case AArch64::STURBi: |
| 24908 | case AArch64::STURDi: |
| 24909 | case AArch64::STURHHi: |
| 24910 | case AArch64::STURHi: |
| 24911 | case AArch64::STURQi: |
| 24912 | case AArch64::STURSi: |
| 24913 | case AArch64::STURWi: |
| 24914 | case AArch64::STURXi: { |
| 24915 | switch (OpNum) { |
| 24916 | case 0: |
| 24917 | // op: Rt |
| 24918 | return 0; |
| 24919 | case 1: |
| 24920 | // op: Rn |
| 24921 | return 5; |
| 24922 | case 2: |
| 24923 | // op: offset |
| 24924 | return 12; |
| 24925 | } |
| 24926 | break; |
| 24927 | } |
| 24928 | case AArch64::LDAPURbi: |
| 24929 | case AArch64::LDAPURdi: |
| 24930 | case AArch64::LDAPURhi: |
| 24931 | case AArch64::LDAPURqi: |
| 24932 | case AArch64::LDAPURsi: |
| 24933 | case AArch64::STLURbi: |
| 24934 | case AArch64::STLURdi: |
| 24935 | case AArch64::STLURhi: |
| 24936 | case AArch64::STLURqi: |
| 24937 | case AArch64::STLURsi: { |
| 24938 | switch (OpNum) { |
| 24939 | case 0: |
| 24940 | // op: Rt |
| 24941 | return 0; |
| 24942 | case 1: |
| 24943 | // op: Rn |
| 24944 | return 5; |
| 24945 | case 2: |
| 24946 | // op: simm |
| 24947 | return 12; |
| 24948 | } |
| 24949 | break; |
| 24950 | } |
| 24951 | case AArch64::GCSSTR: |
| 24952 | case AArch64::GCSSTTR: |
| 24953 | case AArch64::LD64B: |
| 24954 | case AArch64::LDA64B: |
| 24955 | case AArch64::LDARB: |
| 24956 | case AArch64::LDARH: |
| 24957 | case AArch64::LDARW: |
| 24958 | case AArch64::LDARX: |
| 24959 | case AArch64::LDATXRW: |
| 24960 | case AArch64::LDATXRX: |
| 24961 | case AArch64::LDAXRB: |
| 24962 | case AArch64::LDAXRH: |
| 24963 | case AArch64::LDAXRW: |
| 24964 | case AArch64::LDAXRX: |
| 24965 | case AArch64::LDLARB: |
| 24966 | case AArch64::LDLARH: |
| 24967 | case AArch64::LDLARW: |
| 24968 | case AArch64::LDLARX: |
| 24969 | case AArch64::LDTXRWr: |
| 24970 | case AArch64::LDTXRXr: |
| 24971 | case AArch64::LDXRB: |
| 24972 | case AArch64::LDXRH: |
| 24973 | case AArch64::LDXRW: |
| 24974 | case AArch64::LDXRX: |
| 24975 | case AArch64::ST64B: |
| 24976 | case AArch64::STL64B: |
| 24977 | case AArch64::STLLRB: |
| 24978 | case AArch64::STLLRH: |
| 24979 | case AArch64::STLLRW: |
| 24980 | case AArch64::STLLRX: |
| 24981 | case AArch64::STLRB: |
| 24982 | case AArch64::STLRH: |
| 24983 | case AArch64::STLRW: |
| 24984 | case AArch64::STLRX: { |
| 24985 | switch (OpNum) { |
| 24986 | case 0: |
| 24987 | // op: Rt |
| 24988 | return 0; |
| 24989 | case 1: |
| 24990 | // op: Rn |
| 24991 | return 5; |
| 24992 | } |
| 24993 | break; |
| 24994 | } |
| 24995 | case AArch64::LDBFADD: |
| 24996 | case AArch64::LDBFADDA: |
| 24997 | case AArch64::LDBFADDAL: |
| 24998 | case AArch64::LDBFADDL: |
| 24999 | case AArch64::LDBFMAX: |
| 25000 | case AArch64::LDBFMAXA: |
| 25001 | case AArch64::LDBFMAXAL: |
| 25002 | case AArch64::LDBFMAXL: |
| 25003 | case AArch64::LDBFMAXNM: |
| 25004 | case AArch64::LDBFMAXNMA: |
| 25005 | case AArch64::LDBFMAXNMAL: |
| 25006 | case AArch64::LDBFMAXNML: |
| 25007 | case AArch64::LDBFMIN: |
| 25008 | case AArch64::LDBFMINA: |
| 25009 | case AArch64::LDBFMINAL: |
| 25010 | case AArch64::LDBFMINL: |
| 25011 | case AArch64::LDBFMINNM: |
| 25012 | case AArch64::LDBFMINNMA: |
| 25013 | case AArch64::LDBFMINNMAL: |
| 25014 | case AArch64::LDBFMINNML: |
| 25015 | case AArch64::LDFADDAD: |
| 25016 | case AArch64::LDFADDAH: |
| 25017 | case AArch64::LDFADDALD: |
| 25018 | case AArch64::LDFADDALH: |
| 25019 | case AArch64::LDFADDALS: |
| 25020 | case AArch64::LDFADDAS: |
| 25021 | case AArch64::LDFADDD: |
| 25022 | case AArch64::LDFADDH: |
| 25023 | case AArch64::LDFADDLD: |
| 25024 | case AArch64::LDFADDLH: |
| 25025 | case AArch64::LDFADDLS: |
| 25026 | case AArch64::LDFADDS: |
| 25027 | case AArch64::LDFMAXAD: |
| 25028 | case AArch64::LDFMAXAH: |
| 25029 | case AArch64::LDFMAXALD: |
| 25030 | case AArch64::LDFMAXALH: |
| 25031 | case AArch64::LDFMAXALS: |
| 25032 | case AArch64::LDFMAXAS: |
| 25033 | case AArch64::LDFMAXD: |
| 25034 | case AArch64::LDFMAXH: |
| 25035 | case AArch64::LDFMAXLD: |
| 25036 | case AArch64::LDFMAXLH: |
| 25037 | case AArch64::LDFMAXLS: |
| 25038 | case AArch64::LDFMAXNMAD: |
| 25039 | case AArch64::LDFMAXNMAH: |
| 25040 | case AArch64::LDFMAXNMALD: |
| 25041 | case AArch64::LDFMAXNMALH: |
| 25042 | case AArch64::LDFMAXNMALS: |
| 25043 | case AArch64::LDFMAXNMAS: |
| 25044 | case AArch64::LDFMAXNMD: |
| 25045 | case AArch64::LDFMAXNMH: |
| 25046 | case AArch64::LDFMAXNMLD: |
| 25047 | case AArch64::LDFMAXNMLH: |
| 25048 | case AArch64::LDFMAXNMLS: |
| 25049 | case AArch64::LDFMAXNMS: |
| 25050 | case AArch64::LDFMAXS: |
| 25051 | case AArch64::LDFMINAD: |
| 25052 | case AArch64::LDFMINAH: |
| 25053 | case AArch64::LDFMINALD: |
| 25054 | case AArch64::LDFMINALH: |
| 25055 | case AArch64::LDFMINALS: |
| 25056 | case AArch64::LDFMINAS: |
| 25057 | case AArch64::LDFMIND: |
| 25058 | case AArch64::LDFMINH: |
| 25059 | case AArch64::LDFMINLD: |
| 25060 | case AArch64::LDFMINLH: |
| 25061 | case AArch64::LDFMINLS: |
| 25062 | case AArch64::LDFMINNMAD: |
| 25063 | case AArch64::LDFMINNMAH: |
| 25064 | case AArch64::LDFMINNMALD: |
| 25065 | case AArch64::LDFMINNMALH: |
| 25066 | case AArch64::LDFMINNMALS: |
| 25067 | case AArch64::LDFMINNMAS: |
| 25068 | case AArch64::LDFMINNMD: |
| 25069 | case AArch64::LDFMINNMH: |
| 25070 | case AArch64::LDFMINNMLD: |
| 25071 | case AArch64::LDFMINNMLH: |
| 25072 | case AArch64::LDFMINNMLS: |
| 25073 | case AArch64::LDFMINNMS: |
| 25074 | case AArch64::LDFMINS: { |
| 25075 | switch (OpNum) { |
| 25076 | case 0: |
| 25077 | // op: Rt |
| 25078 | return 0; |
| 25079 | case 1: |
| 25080 | // op: Rs |
| 25081 | return 16; |
| 25082 | case 2: |
| 25083 | // op: Rn |
| 25084 | return 5; |
| 25085 | } |
| 25086 | break; |
| 25087 | } |
| 25088 | case AArch64::LDNPDi: |
| 25089 | case AArch64::LDNPQi: |
| 25090 | case AArch64::LDNPSi: |
| 25091 | case AArch64::LDNPWi: |
| 25092 | case AArch64::LDNPXi: |
| 25093 | case AArch64::LDPDi: |
| 25094 | case AArch64::LDPQi: |
| 25095 | case AArch64::LDPSWi: |
| 25096 | case AArch64::LDPSi: |
| 25097 | case AArch64::LDPWi: |
| 25098 | case AArch64::LDPXi: |
| 25099 | case AArch64::LDTNPQi: |
| 25100 | case AArch64::LDTNPXi: |
| 25101 | case AArch64::LDTPQi: |
| 25102 | case AArch64::LDTPi: |
| 25103 | case AArch64::STGPi: |
| 25104 | case AArch64::STNPDi: |
| 25105 | case AArch64::STNPQi: |
| 25106 | case AArch64::STNPSi: |
| 25107 | case AArch64::STNPWi: |
| 25108 | case AArch64::STNPXi: |
| 25109 | case AArch64::STPDi: |
| 25110 | case AArch64::STPQi: |
| 25111 | case AArch64::STPSi: |
| 25112 | case AArch64::STPWi: |
| 25113 | case AArch64::STPXi: |
| 25114 | case AArch64::STTNPQi: |
| 25115 | case AArch64::STTNPXi: |
| 25116 | case AArch64::STTPQi: |
| 25117 | case AArch64::STTPi: { |
| 25118 | switch (OpNum) { |
| 25119 | case 0: |
| 25120 | // op: Rt |
| 25121 | return 0; |
| 25122 | case 1: |
| 25123 | // op: Rt2 |
| 25124 | return 10; |
| 25125 | case 2: |
| 25126 | // op: Rn |
| 25127 | return 5; |
| 25128 | case 3: |
| 25129 | // op: offset |
| 25130 | return 15; |
| 25131 | } |
| 25132 | break; |
| 25133 | } |
| 25134 | case AArch64::LDAXPW: |
| 25135 | case AArch64::LDAXPX: |
| 25136 | case AArch64::LDXPW: |
| 25137 | case AArch64::LDXPX: { |
| 25138 | switch (OpNum) { |
| 25139 | case 0: |
| 25140 | // op: Rt |
| 25141 | return 0; |
| 25142 | case 1: |
| 25143 | // op: Rt2 |
| 25144 | return 10; |
| 25145 | case 2: |
| 25146 | // op: Rn |
| 25147 | return 5; |
| 25148 | } |
| 25149 | break; |
| 25150 | } |
| 25151 | case AArch64::LDAPPi: |
| 25152 | case AArch64::LDAPi: |
| 25153 | case AArch64::STLPi: { |
| 25154 | switch (OpNum) { |
| 25155 | case 0: |
| 25156 | // op: Rt |
| 25157 | return 0; |
| 25158 | case 1: |
| 25159 | // op: Rt2 |
| 25160 | return 16; |
| 25161 | case 2: |
| 25162 | // op: Rn |
| 25163 | return 5; |
| 25164 | } |
| 25165 | break; |
| 25166 | } |
| 25167 | case AArch64::TBNZW: |
| 25168 | case AArch64::TBNZX: |
| 25169 | case AArch64::TBZW: |
| 25170 | case AArch64::TBZX: { |
| 25171 | switch (OpNum) { |
| 25172 | case 0: |
| 25173 | // op: Rt |
| 25174 | return 0; |
| 25175 | case 1: |
| 25176 | // op: bit_off |
| 25177 | return 19; |
| 25178 | case 2: |
| 25179 | // op: target |
| 25180 | return 5; |
| 25181 | } |
| 25182 | break; |
| 25183 | } |
| 25184 | case AArch64::CBEQWri: |
| 25185 | case AArch64::CBEQXri: |
| 25186 | case AArch64::CBGTWri: |
| 25187 | case AArch64::CBGTXri: |
| 25188 | case AArch64::CBHIWri: |
| 25189 | case AArch64::CBHIXri: |
| 25190 | case AArch64::CBLOWri: |
| 25191 | case AArch64::CBLOXri: |
| 25192 | case AArch64::CBLTWri: |
| 25193 | case AArch64::CBLTXri: |
| 25194 | case AArch64::CBNEWri: |
| 25195 | case AArch64::CBNEXri: { |
| 25196 | switch (OpNum) { |
| 25197 | case 0: |
| 25198 | // op: Rt |
| 25199 | return 0; |
| 25200 | case 1: |
| 25201 | // op: imm |
| 25202 | return 15; |
| 25203 | case 2: |
| 25204 | // op: target |
| 25205 | return 5; |
| 25206 | } |
| 25207 | break; |
| 25208 | } |
| 25209 | case AArch64::LDRDl: |
| 25210 | case AArch64::LDRQl: |
| 25211 | case AArch64::LDRSWl: |
| 25212 | case AArch64::LDRSl: |
| 25213 | case AArch64::LDRWl: |
| 25214 | case AArch64::LDRXl: |
| 25215 | case AArch64::PRFMl: { |
| 25216 | switch (OpNum) { |
| 25217 | case 0: |
| 25218 | // op: Rt |
| 25219 | return 0; |
| 25220 | case 1: |
| 25221 | // op: label |
| 25222 | return 5; |
| 25223 | } |
| 25224 | break; |
| 25225 | } |
| 25226 | case AArch64::SYSLxt: { |
| 25227 | switch (OpNum) { |
| 25228 | case 0: |
| 25229 | // op: Rt |
| 25230 | return 0; |
| 25231 | case 1: |
| 25232 | // op: op1 |
| 25233 | return 16; |
| 25234 | case 2: |
| 25235 | // op: Cn |
| 25236 | return 12; |
| 25237 | case 3: |
| 25238 | // op: Cm |
| 25239 | return 8; |
| 25240 | case 4: |
| 25241 | // op: op2 |
| 25242 | return 5; |
| 25243 | } |
| 25244 | break; |
| 25245 | } |
| 25246 | case AArch64::MRRS: |
| 25247 | case AArch64::MRS: { |
| 25248 | switch (OpNum) { |
| 25249 | case 0: |
| 25250 | // op: Rt |
| 25251 | return 0; |
| 25252 | case 1: |
| 25253 | // op: systemreg |
| 25254 | return 5; |
| 25255 | } |
| 25256 | break; |
| 25257 | } |
| 25258 | case AArch64::CBNZW: |
| 25259 | case AArch64::CBNZX: |
| 25260 | case AArch64::CBZW: |
| 25261 | case AArch64::CBZX: { |
| 25262 | switch (OpNum) { |
| 25263 | case 0: |
| 25264 | // op: Rt |
| 25265 | return 0; |
| 25266 | case 1: |
| 25267 | // op: target |
| 25268 | return 5; |
| 25269 | } |
| 25270 | break; |
| 25271 | } |
| 25272 | case AArch64::RPRFM: { |
| 25273 | switch (OpNum) { |
| 25274 | case 0: |
| 25275 | // op: Rt |
| 25276 | return 0; |
| 25277 | case 2: |
| 25278 | // op: Rn |
| 25279 | return 5; |
| 25280 | case 1: |
| 25281 | // op: Rm |
| 25282 | return 16; |
| 25283 | } |
| 25284 | break; |
| 25285 | } |
| 25286 | case AArch64::LDIAPPW: |
| 25287 | case AArch64::LDIAPPX: |
| 25288 | case AArch64::STILPW: |
| 25289 | case AArch64::STILPX: { |
| 25290 | switch (OpNum) { |
| 25291 | case 0: |
| 25292 | // op: Rt |
| 25293 | return 0; |
| 25294 | case 2: |
| 25295 | // op: Rn |
| 25296 | return 5; |
| 25297 | case 1: |
| 25298 | // op: Rt2 |
| 25299 | return 16; |
| 25300 | } |
| 25301 | break; |
| 25302 | } |
| 25303 | case AArch64::GCSPOPM: |
| 25304 | case AArch64::GCSPUSHM: |
| 25305 | case AArch64::GCSSS1: |
| 25306 | case AArch64::GCSSS2: |
| 25307 | case AArch64::WFET: |
| 25308 | case AArch64::WFIT: { |
| 25309 | switch (OpNum) { |
| 25310 | case 0: |
| 25311 | // op: Rt |
| 25312 | return 0; |
| 25313 | } |
| 25314 | break; |
| 25315 | } |
| 25316 | case AArch64::BCAX: |
| 25317 | case AArch64::EOR3: |
| 25318 | case AArch64::SM3SS1: { |
| 25319 | switch (OpNum) { |
| 25320 | case 0: |
| 25321 | // op: Vd |
| 25322 | return 0; |
| 25323 | case 1: |
| 25324 | // op: Vn |
| 25325 | return 5; |
| 25326 | case 2: |
| 25327 | // op: Vm |
| 25328 | return 16; |
| 25329 | case 3: |
| 25330 | // op: Va |
| 25331 | return 10; |
| 25332 | } |
| 25333 | break; |
| 25334 | } |
| 25335 | case AArch64::RAX1: |
| 25336 | case AArch64::SM4ENCKEY: |
| 25337 | case AArch64::TBLv16i8Four: |
| 25338 | case AArch64::TBLv16i8One: |
| 25339 | case AArch64::TBLv16i8Three: |
| 25340 | case AArch64::TBLv16i8Two: |
| 25341 | case AArch64::TBLv8i8Four: |
| 25342 | case AArch64::TBLv8i8One: |
| 25343 | case AArch64::TBLv8i8Three: |
| 25344 | case AArch64::TBLv8i8Two: { |
| 25345 | switch (OpNum) { |
| 25346 | case 0: |
| 25347 | // op: Vd |
| 25348 | return 0; |
| 25349 | case 1: |
| 25350 | // op: Vn |
| 25351 | return 5; |
| 25352 | case 2: |
| 25353 | // op: Vm |
| 25354 | return 16; |
| 25355 | } |
| 25356 | break; |
| 25357 | } |
| 25358 | case AArch64::XAR: { |
| 25359 | switch (OpNum) { |
| 25360 | case 0: |
| 25361 | // op: Vd |
| 25362 | return 0; |
| 25363 | case 1: |
| 25364 | // op: Vn |
| 25365 | return 5; |
| 25366 | case 3: |
| 25367 | // op: imm |
| 25368 | return 10; |
| 25369 | case 2: |
| 25370 | // op: Vm |
| 25371 | return 16; |
| 25372 | } |
| 25373 | break; |
| 25374 | } |
| 25375 | case AArch64::ADDQV_VPZ_B: |
| 25376 | case AArch64::ADDQV_VPZ_D: |
| 25377 | case AArch64::ADDQV_VPZ_H: |
| 25378 | case AArch64::ADDQV_VPZ_S: |
| 25379 | case AArch64::ANDQV_VPZ_B: |
| 25380 | case AArch64::ANDQV_VPZ_D: |
| 25381 | case AArch64::ANDQV_VPZ_H: |
| 25382 | case AArch64::ANDQV_VPZ_S: |
| 25383 | case AArch64::EORQV_VPZ_B: |
| 25384 | case AArch64::EORQV_VPZ_D: |
| 25385 | case AArch64::EORQV_VPZ_H: |
| 25386 | case AArch64::EORQV_VPZ_S: |
| 25387 | case AArch64::FADDQV_D: |
| 25388 | case AArch64::FADDQV_H: |
| 25389 | case AArch64::FADDQV_S: |
| 25390 | case AArch64::FMAXNMQV_D: |
| 25391 | case AArch64::FMAXNMQV_H: |
| 25392 | case AArch64::FMAXNMQV_S: |
| 25393 | case AArch64::FMAXQV_D: |
| 25394 | case AArch64::FMAXQV_H: |
| 25395 | case AArch64::FMAXQV_S: |
| 25396 | case AArch64::FMINNMQV_D: |
| 25397 | case AArch64::FMINNMQV_H: |
| 25398 | case AArch64::FMINNMQV_S: |
| 25399 | case AArch64::FMINQV_D: |
| 25400 | case AArch64::FMINQV_H: |
| 25401 | case AArch64::FMINQV_S: |
| 25402 | case AArch64::ORQV_VPZ_B: |
| 25403 | case AArch64::ORQV_VPZ_D: |
| 25404 | case AArch64::ORQV_VPZ_H: |
| 25405 | case AArch64::ORQV_VPZ_S: |
| 25406 | case AArch64::SMAXQV_VPZ_B: |
| 25407 | case AArch64::SMAXQV_VPZ_D: |
| 25408 | case AArch64::SMAXQV_VPZ_H: |
| 25409 | case AArch64::SMAXQV_VPZ_S: |
| 25410 | case AArch64::SMINQV_VPZ_B: |
| 25411 | case AArch64::SMINQV_VPZ_D: |
| 25412 | case AArch64::SMINQV_VPZ_H: |
| 25413 | case AArch64::SMINQV_VPZ_S: |
| 25414 | case AArch64::UMAXQV_VPZ_B: |
| 25415 | case AArch64::UMAXQV_VPZ_D: |
| 25416 | case AArch64::UMAXQV_VPZ_H: |
| 25417 | case AArch64::UMAXQV_VPZ_S: |
| 25418 | case AArch64::UMINQV_VPZ_B: |
| 25419 | case AArch64::UMINQV_VPZ_D: |
| 25420 | case AArch64::UMINQV_VPZ_H: |
| 25421 | case AArch64::UMINQV_VPZ_S: { |
| 25422 | switch (OpNum) { |
| 25423 | case 0: |
| 25424 | // op: Vd |
| 25425 | return 0; |
| 25426 | case 2: |
| 25427 | // op: Zn |
| 25428 | return 5; |
| 25429 | case 1: |
| 25430 | // op: Pg |
| 25431 | return 10; |
| 25432 | } |
| 25433 | break; |
| 25434 | } |
| 25435 | case AArch64::LD1Fourv16b: |
| 25436 | case AArch64::LD1Fourv1d: |
| 25437 | case AArch64::LD1Fourv2d: |
| 25438 | case AArch64::LD1Fourv2s: |
| 25439 | case AArch64::LD1Fourv4h: |
| 25440 | case AArch64::LD1Fourv4s: |
| 25441 | case AArch64::LD1Fourv8b: |
| 25442 | case AArch64::LD1Fourv8h: |
| 25443 | case AArch64::LD1Onev16b: |
| 25444 | case AArch64::LD1Onev1d: |
| 25445 | case AArch64::LD1Onev2d: |
| 25446 | case AArch64::LD1Onev2s: |
| 25447 | case AArch64::LD1Onev4h: |
| 25448 | case AArch64::LD1Onev4s: |
| 25449 | case AArch64::LD1Onev8b: |
| 25450 | case AArch64::LD1Onev8h: |
| 25451 | case AArch64::LD1Rv16b: |
| 25452 | case AArch64::LD1Rv1d: |
| 25453 | case AArch64::LD1Rv2d: |
| 25454 | case AArch64::LD1Rv2s: |
| 25455 | case AArch64::LD1Rv4h: |
| 25456 | case AArch64::LD1Rv4s: |
| 25457 | case AArch64::LD1Rv8b: |
| 25458 | case AArch64::LD1Rv8h: |
| 25459 | case AArch64::LD1Threev16b: |
| 25460 | case AArch64::LD1Threev1d: |
| 25461 | case AArch64::LD1Threev2d: |
| 25462 | case AArch64::LD1Threev2s: |
| 25463 | case AArch64::LD1Threev4h: |
| 25464 | case AArch64::LD1Threev4s: |
| 25465 | case AArch64::LD1Threev8b: |
| 25466 | case AArch64::LD1Threev8h: |
| 25467 | case AArch64::LD1Twov16b: |
| 25468 | case AArch64::LD1Twov1d: |
| 25469 | case AArch64::LD1Twov2d: |
| 25470 | case AArch64::LD1Twov2s: |
| 25471 | case AArch64::LD1Twov4h: |
| 25472 | case AArch64::LD1Twov4s: |
| 25473 | case AArch64::LD1Twov8b: |
| 25474 | case AArch64::LD1Twov8h: |
| 25475 | case AArch64::LD2Rv16b: |
| 25476 | case AArch64::LD2Rv1d: |
| 25477 | case AArch64::LD2Rv2d: |
| 25478 | case AArch64::LD2Rv2s: |
| 25479 | case AArch64::LD2Rv4h: |
| 25480 | case AArch64::LD2Rv4s: |
| 25481 | case AArch64::LD2Rv8b: |
| 25482 | case AArch64::LD2Rv8h: |
| 25483 | case AArch64::LD2Twov16b: |
| 25484 | case AArch64::LD2Twov2d: |
| 25485 | case AArch64::LD2Twov2s: |
| 25486 | case AArch64::LD2Twov4h: |
| 25487 | case AArch64::LD2Twov4s: |
| 25488 | case AArch64::LD2Twov8b: |
| 25489 | case AArch64::LD2Twov8h: |
| 25490 | case AArch64::LD3Rv16b: |
| 25491 | case AArch64::LD3Rv1d: |
| 25492 | case AArch64::LD3Rv2d: |
| 25493 | case AArch64::LD3Rv2s: |
| 25494 | case AArch64::LD3Rv4h: |
| 25495 | case AArch64::LD3Rv4s: |
| 25496 | case AArch64::LD3Rv8b: |
| 25497 | case AArch64::LD3Rv8h: |
| 25498 | case AArch64::LD3Threev16b: |
| 25499 | case AArch64::LD3Threev2d: |
| 25500 | case AArch64::LD3Threev2s: |
| 25501 | case AArch64::LD3Threev4h: |
| 25502 | case AArch64::LD3Threev4s: |
| 25503 | case AArch64::LD3Threev8b: |
| 25504 | case AArch64::LD3Threev8h: |
| 25505 | case AArch64::LD4Fourv16b: |
| 25506 | case AArch64::LD4Fourv2d: |
| 25507 | case AArch64::LD4Fourv2s: |
| 25508 | case AArch64::LD4Fourv4h: |
| 25509 | case AArch64::LD4Fourv4s: |
| 25510 | case AArch64::LD4Fourv8b: |
| 25511 | case AArch64::LD4Fourv8h: |
| 25512 | case AArch64::LD4Rv16b: |
| 25513 | case AArch64::LD4Rv1d: |
| 25514 | case AArch64::LD4Rv2d: |
| 25515 | case AArch64::LD4Rv2s: |
| 25516 | case AArch64::LD4Rv4h: |
| 25517 | case AArch64::LD4Rv4s: |
| 25518 | case AArch64::LD4Rv8b: |
| 25519 | case AArch64::LD4Rv8h: |
| 25520 | case AArch64::ST1Fourv16b: |
| 25521 | case AArch64::ST1Fourv1d: |
| 25522 | case AArch64::ST1Fourv2d: |
| 25523 | case AArch64::ST1Fourv2s: |
| 25524 | case AArch64::ST1Fourv4h: |
| 25525 | case AArch64::ST1Fourv4s: |
| 25526 | case AArch64::ST1Fourv8b: |
| 25527 | case AArch64::ST1Fourv8h: |
| 25528 | case AArch64::ST1Onev16b: |
| 25529 | case AArch64::ST1Onev1d: |
| 25530 | case AArch64::ST1Onev2d: |
| 25531 | case AArch64::ST1Onev2s: |
| 25532 | case AArch64::ST1Onev4h: |
| 25533 | case AArch64::ST1Onev4s: |
| 25534 | case AArch64::ST1Onev8b: |
| 25535 | case AArch64::ST1Onev8h: |
| 25536 | case AArch64::ST1Threev16b: |
| 25537 | case AArch64::ST1Threev1d: |
| 25538 | case AArch64::ST1Threev2d: |
| 25539 | case AArch64::ST1Threev2s: |
| 25540 | case AArch64::ST1Threev4h: |
| 25541 | case AArch64::ST1Threev4s: |
| 25542 | case AArch64::ST1Threev8b: |
| 25543 | case AArch64::ST1Threev8h: |
| 25544 | case AArch64::ST1Twov16b: |
| 25545 | case AArch64::ST1Twov1d: |
| 25546 | case AArch64::ST1Twov2d: |
| 25547 | case AArch64::ST1Twov2s: |
| 25548 | case AArch64::ST1Twov4h: |
| 25549 | case AArch64::ST1Twov4s: |
| 25550 | case AArch64::ST1Twov8b: |
| 25551 | case AArch64::ST1Twov8h: |
| 25552 | case AArch64::ST2Twov16b: |
| 25553 | case AArch64::ST2Twov2d: |
| 25554 | case AArch64::ST2Twov2s: |
| 25555 | case AArch64::ST2Twov4h: |
| 25556 | case AArch64::ST2Twov4s: |
| 25557 | case AArch64::ST2Twov8b: |
| 25558 | case AArch64::ST2Twov8h: |
| 25559 | case AArch64::ST3Threev16b: |
| 25560 | case AArch64::ST3Threev2d: |
| 25561 | case AArch64::ST3Threev2s: |
| 25562 | case AArch64::ST3Threev4h: |
| 25563 | case AArch64::ST3Threev4s: |
| 25564 | case AArch64::ST3Threev8b: |
| 25565 | case AArch64::ST3Threev8h: |
| 25566 | case AArch64::ST4Fourv16b: |
| 25567 | case AArch64::ST4Fourv2d: |
| 25568 | case AArch64::ST4Fourv2s: |
| 25569 | case AArch64::ST4Fourv4h: |
| 25570 | case AArch64::ST4Fourv4s: |
| 25571 | case AArch64::ST4Fourv8b: |
| 25572 | case AArch64::ST4Fourv8h: { |
| 25573 | switch (OpNum) { |
| 25574 | case 0: |
| 25575 | // op: Vt |
| 25576 | return 0; |
| 25577 | case 1: |
| 25578 | // op: Rn |
| 25579 | return 5; |
| 25580 | } |
| 25581 | break; |
| 25582 | } |
| 25583 | case AArch64::STL1: { |
| 25584 | switch (OpNum) { |
| 25585 | case 0: |
| 25586 | // op: Vt |
| 25587 | return 0; |
| 25588 | case 2: |
| 25589 | // op: Rn |
| 25590 | return 5; |
| 25591 | case 1: |
| 25592 | // op: Q |
| 25593 | return 30; |
| 25594 | } |
| 25595 | break; |
| 25596 | } |
| 25597 | case AArch64::ST1i8: |
| 25598 | case AArch64::ST2i8: |
| 25599 | case AArch64::ST3i8: |
| 25600 | case AArch64::ST4i8: { |
| 25601 | switch (OpNum) { |
| 25602 | case 0: |
| 25603 | // op: Vt |
| 25604 | return 0; |
| 25605 | case 2: |
| 25606 | // op: Rn |
| 25607 | return 5; |
| 25608 | case 1: |
| 25609 | // op: idx |
| 25610 | return 10; |
| 25611 | } |
| 25612 | break; |
| 25613 | } |
| 25614 | case AArch64::ST1i16: |
| 25615 | case AArch64::ST2i16: |
| 25616 | case AArch64::ST3i16: |
| 25617 | case AArch64::ST4i16: { |
| 25618 | switch (OpNum) { |
| 25619 | case 0: |
| 25620 | // op: Vt |
| 25621 | return 0; |
| 25622 | case 2: |
| 25623 | // op: Rn |
| 25624 | return 5; |
| 25625 | case 1: |
| 25626 | // op: idx |
| 25627 | return 11; |
| 25628 | } |
| 25629 | break; |
| 25630 | } |
| 25631 | case AArch64::ST1i32: |
| 25632 | case AArch64::ST2i32: |
| 25633 | case AArch64::ST3i32: |
| 25634 | case AArch64::ST4i32: { |
| 25635 | switch (OpNum) { |
| 25636 | case 0: |
| 25637 | // op: Vt |
| 25638 | return 0; |
| 25639 | case 2: |
| 25640 | // op: Rn |
| 25641 | return 5; |
| 25642 | case 1: |
| 25643 | // op: idx |
| 25644 | return 12; |
| 25645 | } |
| 25646 | break; |
| 25647 | } |
| 25648 | case AArch64::ST1i64: |
| 25649 | case AArch64::ST2i64: |
| 25650 | case AArch64::ST3i64: |
| 25651 | case AArch64::ST4i64: { |
| 25652 | switch (OpNum) { |
| 25653 | case 0: |
| 25654 | // op: Vt |
| 25655 | return 0; |
| 25656 | case 2: |
| 25657 | // op: Rn |
| 25658 | return 5; |
| 25659 | case 1: |
| 25660 | // op: idx |
| 25661 | return 30; |
| 25662 | } |
| 25663 | break; |
| 25664 | } |
| 25665 | case AArch64::STLTXRW: |
| 25666 | case AArch64::STLTXRX: |
| 25667 | case AArch64::STLXRB: |
| 25668 | case AArch64::STLXRH: |
| 25669 | case AArch64::STLXRW: |
| 25670 | case AArch64::STLXRX: |
| 25671 | case AArch64::STXRB: |
| 25672 | case AArch64::STXRH: |
| 25673 | case AArch64::STXRW: |
| 25674 | case AArch64::STXRX: { |
| 25675 | switch (OpNum) { |
| 25676 | case 0: |
| 25677 | // op: Ws |
| 25678 | return 16; |
| 25679 | case 1: |
| 25680 | // op: Rt |
| 25681 | return 0; |
| 25682 | case 2: |
| 25683 | // op: Rn |
| 25684 | return 5; |
| 25685 | } |
| 25686 | break; |
| 25687 | } |
| 25688 | case AArch64::STLXPW: |
| 25689 | case AArch64::STLXPX: |
| 25690 | case AArch64::STXPW: |
| 25691 | case AArch64::STXPX: { |
| 25692 | switch (OpNum) { |
| 25693 | case 0: |
| 25694 | // op: Ws |
| 25695 | return 16; |
| 25696 | case 1: |
| 25697 | // op: Rt |
| 25698 | return 0; |
| 25699 | case 2: |
| 25700 | // op: Rt2 |
| 25701 | return 10; |
| 25702 | case 3: |
| 25703 | // op: Rn |
| 25704 | return 5; |
| 25705 | } |
| 25706 | break; |
| 25707 | } |
| 25708 | case AArch64::TCHANGEBrr: |
| 25709 | case AArch64::TCHANGEFrr: { |
| 25710 | switch (OpNum) { |
| 25711 | case 0: |
| 25712 | // op: Xd |
| 25713 | return 0; |
| 25714 | case 1: |
| 25715 | // op: Xn |
| 25716 | return 5; |
| 25717 | case 2: |
| 25718 | // op: nb |
| 25719 | return 17; |
| 25720 | } |
| 25721 | break; |
| 25722 | } |
| 25723 | case AArch64::TCHANGEBri: |
| 25724 | case AArch64::TCHANGEFri: { |
| 25725 | switch (OpNum) { |
| 25726 | case 0: |
| 25727 | // op: Xd |
| 25728 | return 0; |
| 25729 | case 1: |
| 25730 | // op: imm |
| 25731 | return 5; |
| 25732 | case 2: |
| 25733 | // op: nb |
| 25734 | return 17; |
| 25735 | } |
| 25736 | break; |
| 25737 | } |
| 25738 | case AArch64::ADR: |
| 25739 | case AArch64::ADRP: { |
| 25740 | switch (OpNum) { |
| 25741 | case 0: |
| 25742 | // op: Xd |
| 25743 | return 0; |
| 25744 | case 1: |
| 25745 | // op: label |
| 25746 | return 5; |
| 25747 | } |
| 25748 | break; |
| 25749 | } |
| 25750 | case AArch64::BFTMOPA_M2ZZZI_HtoH: |
| 25751 | case AArch64::BFTMOPA_M2ZZZI_HtoS: |
| 25752 | case AArch64::FTMOPA_M2ZZZI_BtoH: |
| 25753 | case AArch64::FTMOPA_M2ZZZI_BtoS: |
| 25754 | case AArch64::FTMOPA_M2ZZZI_HtoH: |
| 25755 | case AArch64::FTMOPA_M2ZZZI_HtoS: |
| 25756 | case AArch64::FTMOPA_M2ZZZI_StoS: |
| 25757 | case AArch64::STMOPA_M2ZZZI_BtoS: |
| 25758 | case AArch64::STMOPA_M2ZZZI_HtoS: |
| 25759 | case AArch64::SUTMOPA_M2ZZZI_BtoS: |
| 25760 | case AArch64::USTMOPA_M2ZZZI_BtoS: |
| 25761 | case AArch64::UTMOPA_M2ZZZI_BtoS: |
| 25762 | case AArch64::UTMOPA_M2ZZZI_HtoS: { |
| 25763 | switch (OpNum) { |
| 25764 | case 0: |
| 25765 | // op: ZAda |
| 25766 | return 0; |
| 25767 | case 2: |
| 25768 | // op: Zn |
| 25769 | return 6; |
| 25770 | case 3: |
| 25771 | // op: Zm |
| 25772 | return 16; |
| 25773 | case 4: |
| 25774 | // op: Zk |
| 25775 | return 10; |
| 25776 | case 5: |
| 25777 | // op: imm |
| 25778 | return 4; |
| 25779 | } |
| 25780 | break; |
| 25781 | } |
| 25782 | case AArch64::BFMOP4A_M2Z2Z_H: |
| 25783 | case AArch64::BFMOP4A_M2Z2Z_S: |
| 25784 | case AArch64::BFMOP4A_M2ZZ_H: |
| 25785 | case AArch64::BFMOP4A_M2ZZ_S: |
| 25786 | case AArch64::BFMOP4A_MZ2Z_H: |
| 25787 | case AArch64::BFMOP4A_MZ2Z_S: |
| 25788 | case AArch64::BFMOP4A_MZZ_H: |
| 25789 | case AArch64::BFMOP4A_MZZ_S: |
| 25790 | case AArch64::BFMOP4S_M2Z2Z_H: |
| 25791 | case AArch64::BFMOP4S_M2Z2Z_S: |
| 25792 | case AArch64::BFMOP4S_M2ZZ_H: |
| 25793 | case AArch64::BFMOP4S_M2ZZ_S: |
| 25794 | case AArch64::BFMOP4S_MZ2Z_H: |
| 25795 | case AArch64::BFMOP4S_MZ2Z_S: |
| 25796 | case AArch64::BFMOP4S_MZZ_H: |
| 25797 | case AArch64::BFMOP4S_MZZ_S: |
| 25798 | case AArch64::FMOP4A_M2Z2Z_BtoH: |
| 25799 | case AArch64::FMOP4A_M2Z2Z_BtoS: |
| 25800 | case AArch64::FMOP4A_M2Z2Z_D: |
| 25801 | case AArch64::FMOP4A_M2Z2Z_H: |
| 25802 | case AArch64::FMOP4A_M2Z2Z_HtoS: |
| 25803 | case AArch64::FMOP4A_M2Z2Z_S: |
| 25804 | case AArch64::FMOP4A_M2ZZ_BtoH: |
| 25805 | case AArch64::FMOP4A_M2ZZ_BtoS: |
| 25806 | case AArch64::FMOP4A_M2ZZ_D: |
| 25807 | case AArch64::FMOP4A_M2ZZ_H: |
| 25808 | case AArch64::FMOP4A_M2ZZ_HtoS: |
| 25809 | case AArch64::FMOP4A_M2ZZ_S: |
| 25810 | case AArch64::FMOP4A_MZ2Z_BtoH: |
| 25811 | case AArch64::FMOP4A_MZ2Z_BtoS: |
| 25812 | case AArch64::FMOP4A_MZ2Z_D: |
| 25813 | case AArch64::FMOP4A_MZ2Z_H: |
| 25814 | case AArch64::FMOP4A_MZ2Z_HtoS: |
| 25815 | case AArch64::FMOP4A_MZ2Z_S: |
| 25816 | case AArch64::FMOP4A_MZZ_BtoH: |
| 25817 | case AArch64::FMOP4A_MZZ_BtoS: |
| 25818 | case AArch64::FMOP4A_MZZ_D: |
| 25819 | case AArch64::FMOP4A_MZZ_H: |
| 25820 | case AArch64::FMOP4A_MZZ_HtoS: |
| 25821 | case AArch64::FMOP4A_MZZ_S: |
| 25822 | case AArch64::FMOP4S_M2Z2Z_D: |
| 25823 | case AArch64::FMOP4S_M2Z2Z_H: |
| 25824 | case AArch64::FMOP4S_M2Z2Z_HtoS: |
| 25825 | case AArch64::FMOP4S_M2Z2Z_S: |
| 25826 | case AArch64::FMOP4S_M2ZZ_D: |
| 25827 | case AArch64::FMOP4S_M2ZZ_H: |
| 25828 | case AArch64::FMOP4S_M2ZZ_HtoS: |
| 25829 | case AArch64::FMOP4S_M2ZZ_S: |
| 25830 | case AArch64::FMOP4S_MZ2Z_D: |
| 25831 | case AArch64::FMOP4S_MZ2Z_H: |
| 25832 | case AArch64::FMOP4S_MZ2Z_HtoS: |
| 25833 | case AArch64::FMOP4S_MZ2Z_S: |
| 25834 | case AArch64::FMOP4S_MZZ_D: |
| 25835 | case AArch64::FMOP4S_MZZ_H: |
| 25836 | case AArch64::FMOP4S_MZZ_HtoS: |
| 25837 | case AArch64::FMOP4S_MZZ_S: |
| 25838 | case AArch64::SMOP4A_M2Z2Z_BToS: |
| 25839 | case AArch64::SMOP4A_M2Z2Z_HToS: |
| 25840 | case AArch64::SMOP4A_M2Z2Z_HtoD: |
| 25841 | case AArch64::SMOP4A_M2ZZ_BToS: |
| 25842 | case AArch64::SMOP4A_M2ZZ_HToS: |
| 25843 | case AArch64::SMOP4A_M2ZZ_HtoD: |
| 25844 | case AArch64::SMOP4A_MZ2Z_BToS: |
| 25845 | case AArch64::SMOP4A_MZ2Z_HToS: |
| 25846 | case AArch64::SMOP4A_MZ2Z_HtoD: |
| 25847 | case AArch64::SMOP4A_MZZ_BToS: |
| 25848 | case AArch64::SMOP4A_MZZ_HToS: |
| 25849 | case AArch64::SMOP4A_MZZ_HtoD: |
| 25850 | case AArch64::SMOP4S_M2Z2Z_BToS: |
| 25851 | case AArch64::SMOP4S_M2Z2Z_HToS: |
| 25852 | case AArch64::SMOP4S_M2Z2Z_HtoD: |
| 25853 | case AArch64::SMOP4S_M2ZZ_BToS: |
| 25854 | case AArch64::SMOP4S_M2ZZ_HToS: |
| 25855 | case AArch64::SMOP4S_M2ZZ_HtoD: |
| 25856 | case AArch64::SMOP4S_MZ2Z_BToS: |
| 25857 | case AArch64::SMOP4S_MZ2Z_HToS: |
| 25858 | case AArch64::SMOP4S_MZ2Z_HtoD: |
| 25859 | case AArch64::SMOP4S_MZZ_BToS: |
| 25860 | case AArch64::SMOP4S_MZZ_HToS: |
| 25861 | case AArch64::SMOP4S_MZZ_HtoD: |
| 25862 | case AArch64::SUMOP4A_M2Z2Z_BToS: |
| 25863 | case AArch64::SUMOP4A_M2Z2Z_HtoD: |
| 25864 | case AArch64::SUMOP4A_M2ZZ_BToS: |
| 25865 | case AArch64::SUMOP4A_M2ZZ_HtoD: |
| 25866 | case AArch64::SUMOP4A_MZ2Z_BToS: |
| 25867 | case AArch64::SUMOP4A_MZ2Z_HtoD: |
| 25868 | case AArch64::SUMOP4A_MZZ_BToS: |
| 25869 | case AArch64::SUMOP4A_MZZ_HtoD: |
| 25870 | case AArch64::SUMOP4S_M2Z2Z_BToS: |
| 25871 | case AArch64::SUMOP4S_M2Z2Z_HtoD: |
| 25872 | case AArch64::SUMOP4S_M2ZZ_BToS: |
| 25873 | case AArch64::SUMOP4S_M2ZZ_HtoD: |
| 25874 | case AArch64::SUMOP4S_MZ2Z_BToS: |
| 25875 | case AArch64::SUMOP4S_MZ2Z_HtoD: |
| 25876 | case AArch64::SUMOP4S_MZZ_BToS: |
| 25877 | case AArch64::SUMOP4S_MZZ_HtoD: |
| 25878 | case AArch64::UMOP4A_M2Z2Z_BToS: |
| 25879 | case AArch64::UMOP4A_M2Z2Z_HToS: |
| 25880 | case AArch64::UMOP4A_M2Z2Z_HtoD: |
| 25881 | case AArch64::UMOP4A_M2ZZ_BToS: |
| 25882 | case AArch64::UMOP4A_M2ZZ_HToS: |
| 25883 | case AArch64::UMOP4A_M2ZZ_HtoD: |
| 25884 | case AArch64::UMOP4A_MZ2Z_BToS: |
| 25885 | case AArch64::UMOP4A_MZ2Z_HToS: |
| 25886 | case AArch64::UMOP4A_MZ2Z_HtoD: |
| 25887 | case AArch64::UMOP4A_MZZ_BToS: |
| 25888 | case AArch64::UMOP4A_MZZ_HToS: |
| 25889 | case AArch64::UMOP4A_MZZ_HtoD: |
| 25890 | case AArch64::UMOP4S_M2Z2Z_BToS: |
| 25891 | case AArch64::UMOP4S_M2Z2Z_HToS: |
| 25892 | case AArch64::UMOP4S_M2Z2Z_HtoD: |
| 25893 | case AArch64::UMOP4S_M2ZZ_BToS: |
| 25894 | case AArch64::UMOP4S_M2ZZ_HToS: |
| 25895 | case AArch64::UMOP4S_M2ZZ_HtoD: |
| 25896 | case AArch64::UMOP4S_MZ2Z_BToS: |
| 25897 | case AArch64::UMOP4S_MZ2Z_HToS: |
| 25898 | case AArch64::UMOP4S_MZ2Z_HtoD: |
| 25899 | case AArch64::UMOP4S_MZZ_BToS: |
| 25900 | case AArch64::UMOP4S_MZZ_HToS: |
| 25901 | case AArch64::UMOP4S_MZZ_HtoD: |
| 25902 | case AArch64::USMOP4A_M2Z2Z_BToS: |
| 25903 | case AArch64::USMOP4A_M2Z2Z_HtoD: |
| 25904 | case AArch64::USMOP4A_M2ZZ_BToS: |
| 25905 | case AArch64::USMOP4A_M2ZZ_HtoD: |
| 25906 | case AArch64::USMOP4A_MZ2Z_BToS: |
| 25907 | case AArch64::USMOP4A_MZ2Z_HtoD: |
| 25908 | case AArch64::USMOP4A_MZZ_BToS: |
| 25909 | case AArch64::USMOP4A_MZZ_HtoD: |
| 25910 | case AArch64::USMOP4S_M2Z2Z_BToS: |
| 25911 | case AArch64::USMOP4S_M2Z2Z_HtoD: |
| 25912 | case AArch64::USMOP4S_M2ZZ_BToS: |
| 25913 | case AArch64::USMOP4S_M2ZZ_HtoD: |
| 25914 | case AArch64::USMOP4S_MZ2Z_BToS: |
| 25915 | case AArch64::USMOP4S_MZ2Z_HtoD: |
| 25916 | case AArch64::USMOP4S_MZZ_BToS: |
| 25917 | case AArch64::USMOP4S_MZZ_HtoD: { |
| 25918 | switch (OpNum) { |
| 25919 | case 0: |
| 25920 | // op: ZAda |
| 25921 | return 0; |
| 25922 | case 2: |
| 25923 | // op: Zn |
| 25924 | return 6; |
| 25925 | case 3: |
| 25926 | // op: Zm |
| 25927 | return 17; |
| 25928 | } |
| 25929 | break; |
| 25930 | } |
| 25931 | case AArch64::RBIT_ZPzZ_B: |
| 25932 | case AArch64::RBIT_ZPzZ_D: |
| 25933 | case AArch64::RBIT_ZPzZ_H: |
| 25934 | case AArch64::RBIT_ZPzZ_S: |
| 25935 | case AArch64::REVB_ZPzZ_D: |
| 25936 | case AArch64::REVB_ZPzZ_H: |
| 25937 | case AArch64::REVB_ZPzZ_S: |
| 25938 | case AArch64::REVD_ZPzZ: |
| 25939 | case AArch64::REVH_ZPzZ_D: |
| 25940 | case AArch64::REVH_ZPzZ_S: |
| 25941 | case AArch64::REVW_ZPzZ_D: { |
| 25942 | switch (OpNum) { |
| 25943 | case 0: |
| 25944 | // op: Zd |
| 25945 | return 0; |
| 25946 | case 1: |
| 25947 | // op: Pg |
| 25948 | return 10; |
| 25949 | case 2: |
| 25950 | // op: Zn |
| 25951 | return 5; |
| 25952 | } |
| 25953 | break; |
| 25954 | } |
| 25955 | case AArch64::CPY_ZPzI_B: |
| 25956 | case AArch64::CPY_ZPzI_D: |
| 25957 | case AArch64::CPY_ZPzI_H: |
| 25958 | case AArch64::CPY_ZPzI_S: { |
| 25959 | switch (OpNum) { |
| 25960 | case 0: |
| 25961 | // op: Zd |
| 25962 | return 0; |
| 25963 | case 1: |
| 25964 | // op: Pg |
| 25965 | return 16; |
| 25966 | case 2: |
| 25967 | // op: imm |
| 25968 | return 5; |
| 25969 | } |
| 25970 | break; |
| 25971 | } |
| 25972 | case AArch64::LUTI6_S_4Z2Z2ZI: { |
| 25973 | switch (OpNum) { |
| 25974 | case 0: |
| 25975 | // op: Zd |
| 25976 | return 0; |
| 25977 | case 1: |
| 25978 | // op: Zn |
| 25979 | return 5; |
| 25980 | case 2: |
| 25981 | // op: Zm |
| 25982 | return 16; |
| 25983 | case 3: |
| 25984 | // op: i1 |
| 25985 | return 22; |
| 25986 | } |
| 25987 | break; |
| 25988 | } |
| 25989 | case AArch64::LUTI2_ZZZI_H: { |
| 25990 | switch (OpNum) { |
| 25991 | case 0: |
| 25992 | // op: Zd |
| 25993 | return 0; |
| 25994 | case 1: |
| 25995 | // op: Zn |
| 25996 | return 5; |
| 25997 | case 2: |
| 25998 | // op: Zm |
| 25999 | return 16; |
| 26000 | case 3: |
| 26001 | // op: idx |
| 26002 | return 12; |
| 26003 | } |
| 26004 | break; |
| 26005 | } |
| 26006 | case AArch64::LUTI2_ZZZI_B: |
| 26007 | case AArch64::LUTI4_Z2ZZI: |
| 26008 | case AArch64::LUTI4_ZZZI_H: { |
| 26009 | switch (OpNum) { |
| 26010 | case 0: |
| 26011 | // op: Zd |
| 26012 | return 0; |
| 26013 | case 1: |
| 26014 | // op: Zn |
| 26015 | return 5; |
| 26016 | case 2: |
| 26017 | // op: Zm |
| 26018 | return 16; |
| 26019 | case 3: |
| 26020 | // op: idx |
| 26021 | return 22; |
| 26022 | } |
| 26023 | break; |
| 26024 | } |
| 26025 | case AArch64::LUTI4_ZZZI_B: |
| 26026 | case AArch64::LUTI6_Z2ZZI_H: { |
| 26027 | switch (OpNum) { |
| 26028 | case 0: |
| 26029 | // op: Zd |
| 26030 | return 0; |
| 26031 | case 1: |
| 26032 | // op: Zn |
| 26033 | return 5; |
| 26034 | case 2: |
| 26035 | // op: Zm |
| 26036 | return 16; |
| 26037 | case 3: |
| 26038 | // op: idx |
| 26039 | return 23; |
| 26040 | } |
| 26041 | break; |
| 26042 | } |
| 26043 | case AArch64::SMULLB_ZZZI_D: |
| 26044 | case AArch64::SMULLB_ZZZI_S: |
| 26045 | case AArch64::SMULLT_ZZZI_D: |
| 26046 | case AArch64::SMULLT_ZZZI_S: |
| 26047 | case AArch64::SQDMULLB_ZZZI_D: |
| 26048 | case AArch64::SQDMULLB_ZZZI_S: |
| 26049 | case AArch64::SQDMULLT_ZZZI_D: |
| 26050 | case AArch64::SQDMULLT_ZZZI_S: |
| 26051 | case AArch64::UMULLB_ZZZI_D: |
| 26052 | case AArch64::UMULLB_ZZZI_S: |
| 26053 | case AArch64::UMULLT_ZZZI_D: |
| 26054 | case AArch64::UMULLT_ZZZI_S: { |
| 26055 | switch (OpNum) { |
| 26056 | case 0: |
| 26057 | // op: Zd |
| 26058 | return 0; |
| 26059 | case 1: |
| 26060 | // op: Zn |
| 26061 | return 5; |
| 26062 | case 2: |
| 26063 | // op: Zm |
| 26064 | return 16; |
| 26065 | case 3: |
| 26066 | // op: iop |
| 26067 | return 11; |
| 26068 | } |
| 26069 | break; |
| 26070 | } |
| 26071 | case AArch64::BFMUL_ZZZI: |
| 26072 | case AArch64::FMUL_ZZZI_H: |
| 26073 | case AArch64::FMUL_ZZZI_S: |
| 26074 | case AArch64::MUL_ZZZI_H: |
| 26075 | case AArch64::MUL_ZZZI_S: |
| 26076 | case AArch64::SQDMULH_ZZZI_H: |
| 26077 | case AArch64::SQDMULH_ZZZI_S: |
| 26078 | case AArch64::SQRDMULH_ZZZI_H: |
| 26079 | case AArch64::SQRDMULH_ZZZI_S: { |
| 26080 | switch (OpNum) { |
| 26081 | case 0: |
| 26082 | // op: Zd |
| 26083 | return 0; |
| 26084 | case 1: |
| 26085 | // op: Zn |
| 26086 | return 5; |
| 26087 | case 2: |
| 26088 | // op: Zm |
| 26089 | return 16; |
| 26090 | case 3: |
| 26091 | // op: iop |
| 26092 | return 19; |
| 26093 | } |
| 26094 | break; |
| 26095 | } |
| 26096 | case AArch64::FMUL_ZZZI_D: |
| 26097 | case AArch64::MUL_ZZZI_D: |
| 26098 | case AArch64::SQDMULH_ZZZI_D: |
| 26099 | case AArch64::SQRDMULH_ZZZI_D: { |
| 26100 | switch (OpNum) { |
| 26101 | case 0: |
| 26102 | // op: Zd |
| 26103 | return 0; |
| 26104 | case 1: |
| 26105 | // op: Zn |
| 26106 | return 5; |
| 26107 | case 2: |
| 26108 | // op: Zm |
| 26109 | return 16; |
| 26110 | case 3: |
| 26111 | // op: iop |
| 26112 | return 20; |
| 26113 | } |
| 26114 | break; |
| 26115 | } |
| 26116 | case AArch64::ADDHNB_ZZZ_B: |
| 26117 | case AArch64::ADDHNB_ZZZ_H: |
| 26118 | case AArch64::ADDHNB_ZZZ_S: |
| 26119 | case AArch64::ADR_LSL_ZZZ_D_0: |
| 26120 | case AArch64::ADR_LSL_ZZZ_D_1: |
| 26121 | case AArch64::ADR_LSL_ZZZ_D_2: |
| 26122 | case AArch64::ADR_LSL_ZZZ_D_3: |
| 26123 | case AArch64::ADR_LSL_ZZZ_S_0: |
| 26124 | case AArch64::ADR_LSL_ZZZ_S_1: |
| 26125 | case AArch64::ADR_LSL_ZZZ_S_2: |
| 26126 | case AArch64::ADR_LSL_ZZZ_S_3: |
| 26127 | case AArch64::ADR_SXTW_ZZZ_D_0: |
| 26128 | case AArch64::ADR_SXTW_ZZZ_D_1: |
| 26129 | case AArch64::ADR_SXTW_ZZZ_D_2: |
| 26130 | case AArch64::ADR_SXTW_ZZZ_D_3: |
| 26131 | case AArch64::ADR_UXTW_ZZZ_D_0: |
| 26132 | case AArch64::ADR_UXTW_ZZZ_D_1: |
| 26133 | case AArch64::ADR_UXTW_ZZZ_D_2: |
| 26134 | case AArch64::ADR_UXTW_ZZZ_D_3: |
| 26135 | case AArch64::BDEP_ZZZ_B: |
| 26136 | case AArch64::BDEP_ZZZ_D: |
| 26137 | case AArch64::BDEP_ZZZ_H: |
| 26138 | case AArch64::BDEP_ZZZ_S: |
| 26139 | case AArch64::BEXT_ZZZ_B: |
| 26140 | case AArch64::BEXT_ZZZ_D: |
| 26141 | case AArch64::BEXT_ZZZ_H: |
| 26142 | case AArch64::BEXT_ZZZ_S: |
| 26143 | case AArch64::BGRP_ZZZ_B: |
| 26144 | case AArch64::BGRP_ZZZ_D: |
| 26145 | case AArch64::BGRP_ZZZ_H: |
| 26146 | case AArch64::BGRP_ZZZ_S: |
| 26147 | case AArch64::HISTSEG_ZZZ: |
| 26148 | case AArch64::LUTI6_Z2ZZ: |
| 26149 | case AArch64::PMULLB_ZZZ_D: |
| 26150 | case AArch64::PMULLB_ZZZ_H: |
| 26151 | case AArch64::PMULLB_ZZZ_Q: |
| 26152 | case AArch64::PMULLT_ZZZ_D: |
| 26153 | case AArch64::PMULLT_ZZZ_H: |
| 26154 | case AArch64::PMULLT_ZZZ_Q: |
| 26155 | case AArch64::RADDHNB_ZZZ_B: |
| 26156 | case AArch64::RADDHNB_ZZZ_H: |
| 26157 | case AArch64::RADDHNB_ZZZ_S: |
| 26158 | case AArch64::RAX1_ZZZ_D: |
| 26159 | case AArch64::RSUBHNB_ZZZ_B: |
| 26160 | case AArch64::RSUBHNB_ZZZ_H: |
| 26161 | case AArch64::RSUBHNB_ZZZ_S: |
| 26162 | case AArch64::SABDLB_ZZZ_D: |
| 26163 | case AArch64::SABDLB_ZZZ_H: |
| 26164 | case AArch64::SABDLB_ZZZ_S: |
| 26165 | case AArch64::SABDLT_ZZZ_D: |
| 26166 | case AArch64::SABDLT_ZZZ_H: |
| 26167 | case AArch64::SABDLT_ZZZ_S: |
| 26168 | case AArch64::SADDLBT_ZZZ_D: |
| 26169 | case AArch64::SADDLBT_ZZZ_H: |
| 26170 | case AArch64::SADDLBT_ZZZ_S: |
| 26171 | case AArch64::SADDLB_ZZZ_D: |
| 26172 | case AArch64::SADDLB_ZZZ_H: |
| 26173 | case AArch64::SADDLB_ZZZ_S: |
| 26174 | case AArch64::SADDLT_ZZZ_D: |
| 26175 | case AArch64::SADDLT_ZZZ_H: |
| 26176 | case AArch64::SADDLT_ZZZ_S: |
| 26177 | case AArch64::SADDWB_ZZZ_D: |
| 26178 | case AArch64::SADDWB_ZZZ_H: |
| 26179 | case AArch64::SADDWB_ZZZ_S: |
| 26180 | case AArch64::SADDWT_ZZZ_D: |
| 26181 | case AArch64::SADDWT_ZZZ_H: |
| 26182 | case AArch64::SADDWT_ZZZ_S: |
| 26183 | case AArch64::SM4EKEY_ZZZ_S: |
| 26184 | case AArch64::SMULLB_ZZZ_D: |
| 26185 | case AArch64::SMULLB_ZZZ_H: |
| 26186 | case AArch64::SMULLB_ZZZ_S: |
| 26187 | case AArch64::SMULLT_ZZZ_D: |
| 26188 | case AArch64::SMULLT_ZZZ_H: |
| 26189 | case AArch64::SMULLT_ZZZ_S: |
| 26190 | case AArch64::SQDMULLB_ZZZ_D: |
| 26191 | case AArch64::SQDMULLB_ZZZ_H: |
| 26192 | case AArch64::SQDMULLB_ZZZ_S: |
| 26193 | case AArch64::SQDMULLT_ZZZ_D: |
| 26194 | case AArch64::SQDMULLT_ZZZ_H: |
| 26195 | case AArch64::SQDMULLT_ZZZ_S: |
| 26196 | case AArch64::SSUBLBT_ZZZ_D: |
| 26197 | case AArch64::SSUBLBT_ZZZ_H: |
| 26198 | case AArch64::SSUBLBT_ZZZ_S: |
| 26199 | case AArch64::SSUBLB_ZZZ_D: |
| 26200 | case AArch64::SSUBLB_ZZZ_H: |
| 26201 | case AArch64::SSUBLB_ZZZ_S: |
| 26202 | case AArch64::SSUBLTB_ZZZ_D: |
| 26203 | case AArch64::SSUBLTB_ZZZ_H: |
| 26204 | case AArch64::SSUBLTB_ZZZ_S: |
| 26205 | case AArch64::SSUBLT_ZZZ_D: |
| 26206 | case AArch64::SSUBLT_ZZZ_H: |
| 26207 | case AArch64::SSUBLT_ZZZ_S: |
| 26208 | case AArch64::SSUBWB_ZZZ_D: |
| 26209 | case AArch64::SSUBWB_ZZZ_H: |
| 26210 | case AArch64::SSUBWB_ZZZ_S: |
| 26211 | case AArch64::SSUBWT_ZZZ_D: |
| 26212 | case AArch64::SSUBWT_ZZZ_H: |
| 26213 | case AArch64::SSUBWT_ZZZ_S: |
| 26214 | case AArch64::SUBHNB_ZZZ_B: |
| 26215 | case AArch64::SUBHNB_ZZZ_H: |
| 26216 | case AArch64::SUBHNB_ZZZ_S: |
| 26217 | case AArch64::TBLQ_ZZZ_B: |
| 26218 | case AArch64::TBLQ_ZZZ_D: |
| 26219 | case AArch64::TBLQ_ZZZ_H: |
| 26220 | case AArch64::TBLQ_ZZZ_S: |
| 26221 | case AArch64::UABDLB_ZZZ_D: |
| 26222 | case AArch64::UABDLB_ZZZ_H: |
| 26223 | case AArch64::UABDLB_ZZZ_S: |
| 26224 | case AArch64::UABDLT_ZZZ_D: |
| 26225 | case AArch64::UABDLT_ZZZ_H: |
| 26226 | case AArch64::UABDLT_ZZZ_S: |
| 26227 | case AArch64::UADDLB_ZZZ_D: |
| 26228 | case AArch64::UADDLB_ZZZ_H: |
| 26229 | case AArch64::UADDLB_ZZZ_S: |
| 26230 | case AArch64::UADDLT_ZZZ_D: |
| 26231 | case AArch64::UADDLT_ZZZ_H: |
| 26232 | case AArch64::UADDLT_ZZZ_S: |
| 26233 | case AArch64::UADDWB_ZZZ_D: |
| 26234 | case AArch64::UADDWB_ZZZ_H: |
| 26235 | case AArch64::UADDWB_ZZZ_S: |
| 26236 | case AArch64::UADDWT_ZZZ_D: |
| 26237 | case AArch64::UADDWT_ZZZ_H: |
| 26238 | case AArch64::UADDWT_ZZZ_S: |
| 26239 | case AArch64::UMULLB_ZZZ_D: |
| 26240 | case AArch64::UMULLB_ZZZ_H: |
| 26241 | case AArch64::UMULLB_ZZZ_S: |
| 26242 | case AArch64::UMULLT_ZZZ_D: |
| 26243 | case AArch64::UMULLT_ZZZ_H: |
| 26244 | case AArch64::UMULLT_ZZZ_S: |
| 26245 | case AArch64::USUBLB_ZZZ_D: |
| 26246 | case AArch64::USUBLB_ZZZ_H: |
| 26247 | case AArch64::USUBLB_ZZZ_S: |
| 26248 | case AArch64::USUBLT_ZZZ_D: |
| 26249 | case AArch64::USUBLT_ZZZ_H: |
| 26250 | case AArch64::USUBLT_ZZZ_S: |
| 26251 | case AArch64::USUBWB_ZZZ_D: |
| 26252 | case AArch64::USUBWB_ZZZ_H: |
| 26253 | case AArch64::USUBWB_ZZZ_S: |
| 26254 | case AArch64::USUBWT_ZZZ_D: |
| 26255 | case AArch64::USUBWT_ZZZ_H: |
| 26256 | case AArch64::USUBWT_ZZZ_S: |
| 26257 | case AArch64::UZPQ1_ZZZ_B: |
| 26258 | case AArch64::UZPQ1_ZZZ_D: |
| 26259 | case AArch64::UZPQ1_ZZZ_H: |
| 26260 | case AArch64::UZPQ1_ZZZ_S: |
| 26261 | case AArch64::UZPQ2_ZZZ_B: |
| 26262 | case AArch64::UZPQ2_ZZZ_D: |
| 26263 | case AArch64::UZPQ2_ZZZ_H: |
| 26264 | case AArch64::UZPQ2_ZZZ_S: |
| 26265 | case AArch64::ZIPQ1_ZZZ_B: |
| 26266 | case AArch64::ZIPQ1_ZZZ_D: |
| 26267 | case AArch64::ZIPQ1_ZZZ_H: |
| 26268 | case AArch64::ZIPQ1_ZZZ_S: |
| 26269 | case AArch64::ZIPQ2_ZZZ_B: |
| 26270 | case AArch64::ZIPQ2_ZZZ_D: |
| 26271 | case AArch64::ZIPQ2_ZZZ_H: |
| 26272 | case AArch64::ZIPQ2_ZZZ_S: { |
| 26273 | switch (OpNum) { |
| 26274 | case 0: |
| 26275 | // op: Zd |
| 26276 | return 0; |
| 26277 | case 1: |
| 26278 | // op: Zn |
| 26279 | return 5; |
| 26280 | case 2: |
| 26281 | // op: Zm |
| 26282 | return 16; |
| 26283 | } |
| 26284 | break; |
| 26285 | } |
| 26286 | case AArch64::DUP_ZZI_B: { |
| 26287 | switch (OpNum) { |
| 26288 | case 0: |
| 26289 | // op: Zd |
| 26290 | return 0; |
| 26291 | case 1: |
| 26292 | // op: Zn |
| 26293 | return 5; |
| 26294 | case 2: |
| 26295 | // op: idx |
| 26296 | return 17; |
| 26297 | } |
| 26298 | break; |
| 26299 | } |
| 26300 | case AArch64::DUP_ZZI_H: { |
| 26301 | switch (OpNum) { |
| 26302 | case 0: |
| 26303 | // op: Zd |
| 26304 | return 0; |
| 26305 | case 1: |
| 26306 | // op: Zn |
| 26307 | return 5; |
| 26308 | case 2: |
| 26309 | // op: idx |
| 26310 | return 18; |
| 26311 | } |
| 26312 | break; |
| 26313 | } |
| 26314 | case AArch64::DUP_ZZI_S: { |
| 26315 | switch (OpNum) { |
| 26316 | case 0: |
| 26317 | // op: Zd |
| 26318 | return 0; |
| 26319 | case 1: |
| 26320 | // op: Zn |
| 26321 | return 5; |
| 26322 | case 2: |
| 26323 | // op: idx |
| 26324 | return 19; |
| 26325 | } |
| 26326 | break; |
| 26327 | } |
| 26328 | case AArch64::DUP_ZZI_D: { |
| 26329 | switch (OpNum) { |
| 26330 | case 0: |
| 26331 | // op: Zd |
| 26332 | return 0; |
| 26333 | case 1: |
| 26334 | // op: Zn |
| 26335 | return 5; |
| 26336 | case 2: |
| 26337 | // op: idx |
| 26338 | return 20; |
| 26339 | } |
| 26340 | break; |
| 26341 | } |
| 26342 | case AArch64::DUP_ZZI_Q: { |
| 26343 | switch (OpNum) { |
| 26344 | case 0: |
| 26345 | // op: Zd |
| 26346 | return 0; |
| 26347 | case 1: |
| 26348 | // op: Zn |
| 26349 | return 5; |
| 26350 | case 2: |
| 26351 | // op: idx |
| 26352 | return 22; |
| 26353 | } |
| 26354 | break; |
| 26355 | } |
| 26356 | case AArch64::ASR_ZZI_B: |
| 26357 | case AArch64::ASR_ZZI_D: |
| 26358 | case AArch64::ASR_ZZI_H: |
| 26359 | case AArch64::ASR_ZZI_S: |
| 26360 | case AArch64::LSL_ZZI_B: |
| 26361 | case AArch64::LSL_ZZI_D: |
| 26362 | case AArch64::LSL_ZZI_H: |
| 26363 | case AArch64::LSL_ZZI_S: |
| 26364 | case AArch64::LSR_ZZI_B: |
| 26365 | case AArch64::LSR_ZZI_D: |
| 26366 | case AArch64::LSR_ZZI_H: |
| 26367 | case AArch64::LSR_ZZI_S: |
| 26368 | case AArch64::RSHRNB_ZZI_B: |
| 26369 | case AArch64::RSHRNB_ZZI_H: |
| 26370 | case AArch64::RSHRNB_ZZI_S: |
| 26371 | case AArch64::SHRNB_ZZI_B: |
| 26372 | case AArch64::SHRNB_ZZI_H: |
| 26373 | case AArch64::SHRNB_ZZI_S: |
| 26374 | case AArch64::SQRSHRNB_ZZI_B: |
| 26375 | case AArch64::SQRSHRNB_ZZI_H: |
| 26376 | case AArch64::SQRSHRNB_ZZI_S: |
| 26377 | case AArch64::SQRSHRUNB_ZZI_B: |
| 26378 | case AArch64::SQRSHRUNB_ZZI_H: |
| 26379 | case AArch64::SQRSHRUNB_ZZI_S: |
| 26380 | case AArch64::SQSHRNB_ZZI_B: |
| 26381 | case AArch64::SQSHRNB_ZZI_H: |
| 26382 | case AArch64::SQSHRNB_ZZI_S: |
| 26383 | case AArch64::SQSHRUNB_ZZI_B: |
| 26384 | case AArch64::SQSHRUNB_ZZI_H: |
| 26385 | case AArch64::SQSHRUNB_ZZI_S: |
| 26386 | case AArch64::SSHLLB_ZZI_D: |
| 26387 | case AArch64::SSHLLB_ZZI_H: |
| 26388 | case AArch64::SSHLLB_ZZI_S: |
| 26389 | case AArch64::SSHLLT_ZZI_D: |
| 26390 | case AArch64::SSHLLT_ZZI_H: |
| 26391 | case AArch64::SSHLLT_ZZI_S: |
| 26392 | case AArch64::UQRSHRNB_ZZI_B: |
| 26393 | case AArch64::UQRSHRNB_ZZI_H: |
| 26394 | case AArch64::UQRSHRNB_ZZI_S: |
| 26395 | case AArch64::UQSHRNB_ZZI_B: |
| 26396 | case AArch64::UQSHRNB_ZZI_H: |
| 26397 | case AArch64::UQSHRNB_ZZI_S: |
| 26398 | case AArch64::USHLLB_ZZI_D: |
| 26399 | case AArch64::USHLLB_ZZI_H: |
| 26400 | case AArch64::USHLLB_ZZI_S: |
| 26401 | case AArch64::USHLLT_ZZI_D: |
| 26402 | case AArch64::USHLLT_ZZI_H: |
| 26403 | case AArch64::USHLLT_ZZI_S: { |
| 26404 | switch (OpNum) { |
| 26405 | case 0: |
| 26406 | // op: Zd |
| 26407 | return 0; |
| 26408 | case 1: |
| 26409 | // op: Zn |
| 26410 | return 5; |
| 26411 | case 2: |
| 26412 | // op: imm |
| 26413 | return 16; |
| 26414 | } |
| 26415 | break; |
| 26416 | } |
| 26417 | case AArch64::EXT_ZZI_B: { |
| 26418 | switch (OpNum) { |
| 26419 | case 0: |
| 26420 | // op: Zd |
| 26421 | return 0; |
| 26422 | case 1: |
| 26423 | // op: Zn |
| 26424 | return 5; |
| 26425 | case 2: |
| 26426 | // op: imm8 |
| 26427 | return 10; |
| 26428 | } |
| 26429 | break; |
| 26430 | } |
| 26431 | case AArch64::DUPQ_ZZI_B: { |
| 26432 | switch (OpNum) { |
| 26433 | case 0: |
| 26434 | // op: Zd |
| 26435 | return 0; |
| 26436 | case 1: |
| 26437 | // op: Zn |
| 26438 | return 5; |
| 26439 | case 2: |
| 26440 | // op: index |
| 26441 | return 17; |
| 26442 | } |
| 26443 | break; |
| 26444 | } |
| 26445 | case AArch64::DUPQ_ZZI_H: { |
| 26446 | switch (OpNum) { |
| 26447 | case 0: |
| 26448 | // op: Zd |
| 26449 | return 0; |
| 26450 | case 1: |
| 26451 | // op: Zn |
| 26452 | return 5; |
| 26453 | case 2: |
| 26454 | // op: index |
| 26455 | return 18; |
| 26456 | } |
| 26457 | break; |
| 26458 | } |
| 26459 | case AArch64::DUPQ_ZZI_S: { |
| 26460 | switch (OpNum) { |
| 26461 | case 0: |
| 26462 | // op: Zd |
| 26463 | return 0; |
| 26464 | case 1: |
| 26465 | // op: Zn |
| 26466 | return 5; |
| 26467 | case 2: |
| 26468 | // op: index |
| 26469 | return 19; |
| 26470 | } |
| 26471 | break; |
| 26472 | } |
| 26473 | case AArch64::DUPQ_ZZI_D: { |
| 26474 | switch (OpNum) { |
| 26475 | case 0: |
| 26476 | // op: Zd |
| 26477 | return 0; |
| 26478 | case 1: |
| 26479 | // op: Zn |
| 26480 | return 5; |
| 26481 | case 2: |
| 26482 | // op: index |
| 26483 | return 20; |
| 26484 | } |
| 26485 | break; |
| 26486 | } |
| 26487 | case AArch64::BF1CVTLT_ZZ_BtoH: |
| 26488 | case AArch64::BF1CVT_ZZ_BtoH: |
| 26489 | case AArch64::BF2CVTLT_ZZ_BtoH: |
| 26490 | case AArch64::BF2CVT_ZZ_BtoH: |
| 26491 | case AArch64::F1CVTLT_ZZ_BtoH: |
| 26492 | case AArch64::F1CVT_ZZ_BtoH: |
| 26493 | case AArch64::F2CVTLT_ZZ_BtoH: |
| 26494 | case AArch64::F2CVT_ZZ_BtoH: |
| 26495 | case AArch64::FEXPA_ZZ_D: |
| 26496 | case AArch64::FEXPA_ZZ_H: |
| 26497 | case AArch64::FEXPA_ZZ_S: |
| 26498 | case AArch64::FRECPE_ZZ_D: |
| 26499 | case AArch64::FRECPE_ZZ_H: |
| 26500 | case AArch64::FRECPE_ZZ_S: |
| 26501 | case AArch64::FRSQRTE_ZZ_D: |
| 26502 | case AArch64::FRSQRTE_ZZ_H: |
| 26503 | case AArch64::FRSQRTE_ZZ_S: |
| 26504 | case AArch64::MOVPRFX_ZZ: |
| 26505 | case AArch64::REV_ZZ_B: |
| 26506 | case AArch64::REV_ZZ_D: |
| 26507 | case AArch64::REV_ZZ_H: |
| 26508 | case AArch64::REV_ZZ_S: |
| 26509 | case AArch64::SCVTFLT_ZZ_BtoH: |
| 26510 | case AArch64::SCVTFLT_ZZ_HtoS: |
| 26511 | case AArch64::SCVTFLT_ZZ_StoD: |
| 26512 | case AArch64::SCVTF_ZZ_BtoH: |
| 26513 | case AArch64::SCVTF_ZZ_HtoS: |
| 26514 | case AArch64::SCVTF_ZZ_StoD: |
| 26515 | case AArch64::SQXTNB_ZZ_B: |
| 26516 | case AArch64::SQXTNB_ZZ_H: |
| 26517 | case AArch64::SQXTNB_ZZ_S: |
| 26518 | case AArch64::SQXTUNB_ZZ_B: |
| 26519 | case AArch64::SQXTUNB_ZZ_H: |
| 26520 | case AArch64::SQXTUNB_ZZ_S: |
| 26521 | case AArch64::SUNPKHI_ZZ_D: |
| 26522 | case AArch64::SUNPKHI_ZZ_H: |
| 26523 | case AArch64::SUNPKHI_ZZ_S: |
| 26524 | case AArch64::SUNPKLO_ZZ_D: |
| 26525 | case AArch64::SUNPKLO_ZZ_H: |
| 26526 | case AArch64::SUNPKLO_ZZ_S: |
| 26527 | case AArch64::UCVTFLT_ZZ_BtoH: |
| 26528 | case AArch64::UCVTFLT_ZZ_HtoS: |
| 26529 | case AArch64::UCVTFLT_ZZ_StoD: |
| 26530 | case AArch64::UCVTF_ZZ_BtoH: |
| 26531 | case AArch64::UCVTF_ZZ_HtoS: |
| 26532 | case AArch64::UCVTF_ZZ_StoD: |
| 26533 | case AArch64::UQXTNB_ZZ_B: |
| 26534 | case AArch64::UQXTNB_ZZ_H: |
| 26535 | case AArch64::UQXTNB_ZZ_S: |
| 26536 | case AArch64::UUNPKHI_ZZ_D: |
| 26537 | case AArch64::UUNPKHI_ZZ_H: |
| 26538 | case AArch64::UUNPKHI_ZZ_S: |
| 26539 | case AArch64::UUNPKLO_ZZ_D: |
| 26540 | case AArch64::UUNPKLO_ZZ_H: |
| 26541 | case AArch64::UUNPKLO_ZZ_S: { |
| 26542 | switch (OpNum) { |
| 26543 | case 0: |
| 26544 | // op: Zd |
| 26545 | return 0; |
| 26546 | case 1: |
| 26547 | // op: Zn |
| 26548 | return 5; |
| 26549 | } |
| 26550 | break; |
| 26551 | } |
| 26552 | case AArch64::SQRSHRN_Z2ZI_HtoB: |
| 26553 | case AArch64::SQRSHRN_Z2ZI_StoH: |
| 26554 | case AArch64::SQRSHRUN_Z2ZI_HtoB: |
| 26555 | case AArch64::SQRSHRUN_Z2ZI_StoH: |
| 26556 | case AArch64::SQSHRN_Z2ZI_HtoB: |
| 26557 | case AArch64::SQSHRN_Z2ZI_StoH: |
| 26558 | case AArch64::SQSHRUN_Z2ZI_HtoB: |
| 26559 | case AArch64::SQSHRUN_Z2ZI_StoH: |
| 26560 | case AArch64::UQRSHRN_Z2ZI_HtoB: |
| 26561 | case AArch64::UQRSHRN_Z2ZI_StoH: |
| 26562 | case AArch64::UQSHRN_Z2ZI_HtoB: |
| 26563 | case AArch64::UQSHRN_Z2ZI_StoH: { |
| 26564 | switch (OpNum) { |
| 26565 | case 0: |
| 26566 | // op: Zd |
| 26567 | return 0; |
| 26568 | case 1: |
| 26569 | // op: Zn |
| 26570 | return 6; |
| 26571 | case 2: |
| 26572 | // op: imm |
| 26573 | return 16; |
| 26574 | } |
| 26575 | break; |
| 26576 | } |
| 26577 | case AArch64::BFCVTN_Z2Z_HtoB: |
| 26578 | case AArch64::FCVTNB_Z2Z_StoB: |
| 26579 | case AArch64::FCVTN_Z2Z_HtoB: |
| 26580 | case AArch64::FCVTZSN_Z2Z_DtoS: |
| 26581 | case AArch64::FCVTZSN_Z2Z_HtoB: |
| 26582 | case AArch64::FCVTZSN_Z2Z_StoH: |
| 26583 | case AArch64::FCVTZUN_Z2Z_DtoS: |
| 26584 | case AArch64::FCVTZUN_Z2Z_HtoB: |
| 26585 | case AArch64::FCVTZUN_Z2Z_StoH: |
| 26586 | case AArch64::SQCVTN_Z2Z_StoH: |
| 26587 | case AArch64::SQCVTUN_Z2Z_StoH: |
| 26588 | case AArch64::UQCVTN_Z2Z_StoH: { |
| 26589 | switch (OpNum) { |
| 26590 | case 0: |
| 26591 | // op: Zd |
| 26592 | return 0; |
| 26593 | case 1: |
| 26594 | // op: Zn |
| 26595 | return 6; |
| 26596 | } |
| 26597 | break; |
| 26598 | } |
| 26599 | case AArch64::DUP_ZI_B: |
| 26600 | case AArch64::DUP_ZI_D: |
| 26601 | case AArch64::DUP_ZI_H: |
| 26602 | case AArch64::DUP_ZI_S: { |
| 26603 | switch (OpNum) { |
| 26604 | case 0: |
| 26605 | // op: Zd |
| 26606 | return 0; |
| 26607 | case 1: |
| 26608 | // op: imm |
| 26609 | return 5; |
| 26610 | } |
| 26611 | break; |
| 26612 | } |
| 26613 | case AArch64::INDEX_II_B: |
| 26614 | case AArch64::INDEX_II_D: |
| 26615 | case AArch64::INDEX_II_H: |
| 26616 | case AArch64::INDEX_II_S: { |
| 26617 | switch (OpNum) { |
| 26618 | case 0: |
| 26619 | // op: Zd |
| 26620 | return 0; |
| 26621 | case 1: |
| 26622 | // op: imm5 |
| 26623 | return 5; |
| 26624 | case 2: |
| 26625 | // op: imm5b |
| 26626 | return 16; |
| 26627 | } |
| 26628 | break; |
| 26629 | } |
| 26630 | case AArch64::FDUP_ZI_D: |
| 26631 | case AArch64::FDUP_ZI_H: |
| 26632 | case AArch64::FDUP_ZI_S: { |
| 26633 | switch (OpNum) { |
| 26634 | case 0: |
| 26635 | // op: Zd |
| 26636 | return 0; |
| 26637 | case 1: |
| 26638 | // op: imm8 |
| 26639 | return 5; |
| 26640 | } |
| 26641 | break; |
| 26642 | } |
| 26643 | case AArch64::DUPM_ZI: { |
| 26644 | switch (OpNum) { |
| 26645 | case 0: |
| 26646 | // op: Zd |
| 26647 | return 0; |
| 26648 | case 1: |
| 26649 | // op: imms |
| 26650 | return 5; |
| 26651 | } |
| 26652 | break; |
| 26653 | } |
| 26654 | case AArch64::RBIT_ZPmZ_B: |
| 26655 | case AArch64::RBIT_ZPmZ_D: |
| 26656 | case AArch64::RBIT_ZPmZ_H: |
| 26657 | case AArch64::RBIT_ZPmZ_S: |
| 26658 | case AArch64::REVB_ZPmZ_D: |
| 26659 | case AArch64::REVB_ZPmZ_H: |
| 26660 | case AArch64::REVB_ZPmZ_S: |
| 26661 | case AArch64::REVD_ZPmZ: |
| 26662 | case AArch64::REVH_ZPmZ_D: |
| 26663 | case AArch64::REVH_ZPmZ_S: |
| 26664 | case AArch64::REVW_ZPmZ_D: { |
| 26665 | switch (OpNum) { |
| 26666 | case 0: |
| 26667 | // op: Zd |
| 26668 | return 0; |
| 26669 | case 2: |
| 26670 | // op: Pg |
| 26671 | return 10; |
| 26672 | case 3: |
| 26673 | // op: Zn |
| 26674 | return 5; |
| 26675 | } |
| 26676 | break; |
| 26677 | } |
| 26678 | case AArch64::CPY_ZPmI_B: |
| 26679 | case AArch64::CPY_ZPmI_D: |
| 26680 | case AArch64::CPY_ZPmI_H: |
| 26681 | case AArch64::CPY_ZPmI_S: { |
| 26682 | switch (OpNum) { |
| 26683 | case 0: |
| 26684 | // op: Zd |
| 26685 | return 0; |
| 26686 | case 2: |
| 26687 | // op: Pg |
| 26688 | return 16; |
| 26689 | case 3: |
| 26690 | // op: imm |
| 26691 | return 5; |
| 26692 | } |
| 26693 | break; |
| 26694 | } |
| 26695 | case AArch64::INDEX_RR_B: |
| 26696 | case AArch64::INDEX_RR_D: |
| 26697 | case AArch64::INDEX_RR_H: |
| 26698 | case AArch64::INDEX_RR_S: { |
| 26699 | switch (OpNum) { |
| 26700 | case 0: |
| 26701 | // op: Zd |
| 26702 | return 0; |
| 26703 | case 2: |
| 26704 | // op: Rm |
| 26705 | return 16; |
| 26706 | case 1: |
| 26707 | // op: Rn |
| 26708 | return 5; |
| 26709 | } |
| 26710 | break; |
| 26711 | } |
| 26712 | case AArch64::ADDQP_ZZZ_B: |
| 26713 | case AArch64::ADDQP_ZZZ_D: |
| 26714 | case AArch64::ADDQP_ZZZ_H: |
| 26715 | case AArch64::ADDQP_ZZZ_S: |
| 26716 | case AArch64::ADDSUBP_ZZZ_B: |
| 26717 | case AArch64::ADDSUBP_ZZZ_D: |
| 26718 | case AArch64::ADDSUBP_ZZZ_H: |
| 26719 | case AArch64::ADDSUBP_ZZZ_S: |
| 26720 | case AArch64::ADD_ZZZ_B: |
| 26721 | case AArch64::ADD_ZZZ_CPA: |
| 26722 | case AArch64::ADD_ZZZ_D: |
| 26723 | case AArch64::ADD_ZZZ_H: |
| 26724 | case AArch64::ADD_ZZZ_S: |
| 26725 | case AArch64::AND_ZZZ: |
| 26726 | case AArch64::ASR_WIDE_ZZZ_B: |
| 26727 | case AArch64::ASR_WIDE_ZZZ_H: |
| 26728 | case AArch64::ASR_WIDE_ZZZ_S: |
| 26729 | case AArch64::BFADD_ZZZ: |
| 26730 | case AArch64::BFMUL_ZZZ: |
| 26731 | case AArch64::BFSUB_ZZZ: |
| 26732 | case AArch64::BIC_ZZZ: |
| 26733 | case AArch64::EOR_ZZZ: |
| 26734 | case AArch64::FADD_ZZZ_D: |
| 26735 | case AArch64::FADD_ZZZ_H: |
| 26736 | case AArch64::FADD_ZZZ_S: |
| 26737 | case AArch64::FMUL_ZZZ_D: |
| 26738 | case AArch64::FMUL_ZZZ_H: |
| 26739 | case AArch64::FMUL_ZZZ_S: |
| 26740 | case AArch64::FRECPS_ZZZ_D: |
| 26741 | case AArch64::FRECPS_ZZZ_H: |
| 26742 | case AArch64::FRECPS_ZZZ_S: |
| 26743 | case AArch64::FRSQRTS_ZZZ_D: |
| 26744 | case AArch64::FRSQRTS_ZZZ_H: |
| 26745 | case AArch64::FRSQRTS_ZZZ_S: |
| 26746 | case AArch64::FSUB_ZZZ_D: |
| 26747 | case AArch64::FSUB_ZZZ_H: |
| 26748 | case AArch64::FSUB_ZZZ_S: |
| 26749 | case AArch64::FTSMUL_ZZZ_D: |
| 26750 | case AArch64::FTSMUL_ZZZ_H: |
| 26751 | case AArch64::FTSMUL_ZZZ_S: |
| 26752 | case AArch64::FTSSEL_ZZZ_D: |
| 26753 | case AArch64::FTSSEL_ZZZ_H: |
| 26754 | case AArch64::FTSSEL_ZZZ_S: |
| 26755 | case AArch64::LSL_WIDE_ZZZ_B: |
| 26756 | case AArch64::LSL_WIDE_ZZZ_H: |
| 26757 | case AArch64::LSL_WIDE_ZZZ_S: |
| 26758 | case AArch64::LSR_WIDE_ZZZ_B: |
| 26759 | case AArch64::LSR_WIDE_ZZZ_H: |
| 26760 | case AArch64::LSR_WIDE_ZZZ_S: |
| 26761 | case AArch64::MUL_ZZZ_B: |
| 26762 | case AArch64::MUL_ZZZ_D: |
| 26763 | case AArch64::MUL_ZZZ_H: |
| 26764 | case AArch64::MUL_ZZZ_S: |
| 26765 | case AArch64::ORR_ZZZ: |
| 26766 | case AArch64::PMUL_ZZZ_B: |
| 26767 | case AArch64::SMULH_ZZZ_B: |
| 26768 | case AArch64::SMULH_ZZZ_D: |
| 26769 | case AArch64::SMULH_ZZZ_H: |
| 26770 | case AArch64::SMULH_ZZZ_S: |
| 26771 | case AArch64::SQADD_ZZZ_B: |
| 26772 | case AArch64::SQADD_ZZZ_D: |
| 26773 | case AArch64::SQADD_ZZZ_H: |
| 26774 | case AArch64::SQADD_ZZZ_S: |
| 26775 | case AArch64::SQDMULH_ZZZ_B: |
| 26776 | case AArch64::SQDMULH_ZZZ_D: |
| 26777 | case AArch64::SQDMULH_ZZZ_H: |
| 26778 | case AArch64::SQDMULH_ZZZ_S: |
| 26779 | case AArch64::SQRDMULH_ZZZ_B: |
| 26780 | case AArch64::SQRDMULH_ZZZ_D: |
| 26781 | case AArch64::SQRDMULH_ZZZ_H: |
| 26782 | case AArch64::SQRDMULH_ZZZ_S: |
| 26783 | case AArch64::SQSUB_ZZZ_B: |
| 26784 | case AArch64::SQSUB_ZZZ_D: |
| 26785 | case AArch64::SQSUB_ZZZ_H: |
| 26786 | case AArch64::SQSUB_ZZZ_S: |
| 26787 | case AArch64::SUB_ZZZ_B: |
| 26788 | case AArch64::SUB_ZZZ_CPA: |
| 26789 | case AArch64::SUB_ZZZ_D: |
| 26790 | case AArch64::SUB_ZZZ_H: |
| 26791 | case AArch64::SUB_ZZZ_S: |
| 26792 | case AArch64::TBL_ZZZZ_B: |
| 26793 | case AArch64::TBL_ZZZZ_D: |
| 26794 | case AArch64::TBL_ZZZZ_H: |
| 26795 | case AArch64::TBL_ZZZZ_S: |
| 26796 | case AArch64::TBL_ZZZ_B: |
| 26797 | case AArch64::TBL_ZZZ_D: |
| 26798 | case AArch64::TBL_ZZZ_H: |
| 26799 | case AArch64::TBL_ZZZ_S: |
| 26800 | case AArch64::TRN1_ZZZ_B: |
| 26801 | case AArch64::TRN1_ZZZ_D: |
| 26802 | case AArch64::TRN1_ZZZ_H: |
| 26803 | case AArch64::TRN1_ZZZ_Q: |
| 26804 | case AArch64::TRN1_ZZZ_S: |
| 26805 | case AArch64::TRN2_ZZZ_B: |
| 26806 | case AArch64::TRN2_ZZZ_D: |
| 26807 | case AArch64::TRN2_ZZZ_H: |
| 26808 | case AArch64::TRN2_ZZZ_Q: |
| 26809 | case AArch64::TRN2_ZZZ_S: |
| 26810 | case AArch64::UMULH_ZZZ_B: |
| 26811 | case AArch64::UMULH_ZZZ_D: |
| 26812 | case AArch64::UMULH_ZZZ_H: |
| 26813 | case AArch64::UMULH_ZZZ_S: |
| 26814 | case AArch64::UQADD_ZZZ_B: |
| 26815 | case AArch64::UQADD_ZZZ_D: |
| 26816 | case AArch64::UQADD_ZZZ_H: |
| 26817 | case AArch64::UQADD_ZZZ_S: |
| 26818 | case AArch64::UQSUB_ZZZ_B: |
| 26819 | case AArch64::UQSUB_ZZZ_D: |
| 26820 | case AArch64::UQSUB_ZZZ_H: |
| 26821 | case AArch64::UQSUB_ZZZ_S: |
| 26822 | case AArch64::UZP1_ZZZ_B: |
| 26823 | case AArch64::UZP1_ZZZ_D: |
| 26824 | case AArch64::UZP1_ZZZ_H: |
| 26825 | case AArch64::UZP1_ZZZ_Q: |
| 26826 | case AArch64::UZP1_ZZZ_S: |
| 26827 | case AArch64::UZP2_ZZZ_B: |
| 26828 | case AArch64::UZP2_ZZZ_D: |
| 26829 | case AArch64::UZP2_ZZZ_H: |
| 26830 | case AArch64::UZP2_ZZZ_Q: |
| 26831 | case AArch64::UZP2_ZZZ_S: |
| 26832 | case AArch64::ZIP1_ZZZ_B: |
| 26833 | case AArch64::ZIP1_ZZZ_D: |
| 26834 | case AArch64::ZIP1_ZZZ_H: |
| 26835 | case AArch64::ZIP1_ZZZ_Q: |
| 26836 | case AArch64::ZIP1_ZZZ_S: |
| 26837 | case AArch64::ZIP2_ZZZ_B: |
| 26838 | case AArch64::ZIP2_ZZZ_D: |
| 26839 | case AArch64::ZIP2_ZZZ_H: |
| 26840 | case AArch64::ZIP2_ZZZ_Q: |
| 26841 | case AArch64::ZIP2_ZZZ_S: { |
| 26842 | switch (OpNum) { |
| 26843 | case 0: |
| 26844 | // op: Zd |
| 26845 | return 0; |
| 26846 | case 2: |
| 26847 | // op: Zm |
| 26848 | return 16; |
| 26849 | case 1: |
| 26850 | // op: Zn |
| 26851 | return 5; |
| 26852 | } |
| 26853 | break; |
| 26854 | } |
| 26855 | case AArch64::HISTCNT_ZPzZZ_D: |
| 26856 | case AArch64::HISTCNT_ZPzZZ_S: { |
| 26857 | switch (OpNum) { |
| 26858 | case 0: |
| 26859 | // op: Zd |
| 26860 | return 0; |
| 26861 | case 2: |
| 26862 | // op: Zn |
| 26863 | return 5; |
| 26864 | case 1: |
| 26865 | // op: Pg |
| 26866 | return 10; |
| 26867 | case 3: |
| 26868 | // op: Zm |
| 26869 | return 16; |
| 26870 | } |
| 26871 | break; |
| 26872 | } |
| 26873 | case AArch64::FCVTLT_ZPzZ_HtoS: |
| 26874 | case AArch64::FCVTLT_ZPzZ_StoD: { |
| 26875 | switch (OpNum) { |
| 26876 | case 0: |
| 26877 | // op: Zd |
| 26878 | return 0; |
| 26879 | case 2: |
| 26880 | // op: Zn |
| 26881 | return 5; |
| 26882 | case 1: |
| 26883 | // op: Pg |
| 26884 | return 10; |
| 26885 | } |
| 26886 | break; |
| 26887 | } |
| 26888 | case AArch64::ADDHNT_ZZZ_B: |
| 26889 | case AArch64::ADDHNT_ZZZ_H: |
| 26890 | case AArch64::ADDHNT_ZZZ_S: |
| 26891 | case AArch64::EORBT_ZZZ_B: |
| 26892 | case AArch64::EORBT_ZZZ_D: |
| 26893 | case AArch64::EORBT_ZZZ_H: |
| 26894 | case AArch64::EORBT_ZZZ_S: |
| 26895 | case AArch64::EORTB_ZZZ_B: |
| 26896 | case AArch64::EORTB_ZZZ_D: |
| 26897 | case AArch64::EORTB_ZZZ_H: |
| 26898 | case AArch64::EORTB_ZZZ_S: |
| 26899 | case AArch64::RADDHNT_ZZZ_B: |
| 26900 | case AArch64::RADDHNT_ZZZ_H: |
| 26901 | case AArch64::RADDHNT_ZZZ_S: |
| 26902 | case AArch64::RSUBHNT_ZZZ_B: |
| 26903 | case AArch64::RSUBHNT_ZZZ_H: |
| 26904 | case AArch64::RSUBHNT_ZZZ_S: |
| 26905 | case AArch64::SUBHNT_ZZZ_B: |
| 26906 | case AArch64::SUBHNT_ZZZ_H: |
| 26907 | case AArch64::SUBHNT_ZZZ_S: { |
| 26908 | switch (OpNum) { |
| 26909 | case 0: |
| 26910 | // op: Zd |
| 26911 | return 0; |
| 26912 | case 2: |
| 26913 | // op: Zn |
| 26914 | return 5; |
| 26915 | case 3: |
| 26916 | // op: Zm |
| 26917 | return 16; |
| 26918 | } |
| 26919 | break; |
| 26920 | } |
| 26921 | case AArch64::RSHRNT_ZZI_B: |
| 26922 | case AArch64::RSHRNT_ZZI_H: |
| 26923 | case AArch64::RSHRNT_ZZI_S: |
| 26924 | case AArch64::SHRNT_ZZI_B: |
| 26925 | case AArch64::SHRNT_ZZI_H: |
| 26926 | case AArch64::SHRNT_ZZI_S: |
| 26927 | case AArch64::SLI_ZZI_B: |
| 26928 | case AArch64::SLI_ZZI_D: |
| 26929 | case AArch64::SLI_ZZI_H: |
| 26930 | case AArch64::SLI_ZZI_S: |
| 26931 | case AArch64::SQRSHRNT_ZZI_B: |
| 26932 | case AArch64::SQRSHRNT_ZZI_H: |
| 26933 | case AArch64::SQRSHRNT_ZZI_S: |
| 26934 | case AArch64::SQRSHRUNT_ZZI_B: |
| 26935 | case AArch64::SQRSHRUNT_ZZI_H: |
| 26936 | case AArch64::SQRSHRUNT_ZZI_S: |
| 26937 | case AArch64::SQSHRNT_ZZI_B: |
| 26938 | case AArch64::SQSHRNT_ZZI_H: |
| 26939 | case AArch64::SQSHRNT_ZZI_S: |
| 26940 | case AArch64::SQSHRUNT_ZZI_B: |
| 26941 | case AArch64::SQSHRUNT_ZZI_H: |
| 26942 | case AArch64::SQSHRUNT_ZZI_S: |
| 26943 | case AArch64::SRI_ZZI_B: |
| 26944 | case AArch64::SRI_ZZI_D: |
| 26945 | case AArch64::SRI_ZZI_H: |
| 26946 | case AArch64::SRI_ZZI_S: |
| 26947 | case AArch64::UQRSHRNT_ZZI_B: |
| 26948 | case AArch64::UQRSHRNT_ZZI_H: |
| 26949 | case AArch64::UQRSHRNT_ZZI_S: |
| 26950 | case AArch64::UQSHRNT_ZZI_B: |
| 26951 | case AArch64::UQSHRNT_ZZI_H: |
| 26952 | case AArch64::UQSHRNT_ZZI_S: { |
| 26953 | switch (OpNum) { |
| 26954 | case 0: |
| 26955 | // op: Zd |
| 26956 | return 0; |
| 26957 | case 2: |
| 26958 | // op: Zn |
| 26959 | return 5; |
| 26960 | case 3: |
| 26961 | // op: imm |
| 26962 | return 16; |
| 26963 | } |
| 26964 | break; |
| 26965 | } |
| 26966 | case AArch64::LUTI6_ZTZ: |
| 26967 | case AArch64::SQXTNT_ZZ_B: |
| 26968 | case AArch64::SQXTNT_ZZ_H: |
| 26969 | case AArch64::SQXTNT_ZZ_S: |
| 26970 | case AArch64::SQXTUNT_ZZ_B: |
| 26971 | case AArch64::SQXTUNT_ZZ_H: |
| 26972 | case AArch64::SQXTUNT_ZZ_S: |
| 26973 | case AArch64::UQXTNT_ZZ_B: |
| 26974 | case AArch64::UQXTNT_ZZ_H: |
| 26975 | case AArch64::UQXTNT_ZZ_S: { |
| 26976 | switch (OpNum) { |
| 26977 | case 0: |
| 26978 | // op: Zd |
| 26979 | return 0; |
| 26980 | case 2: |
| 26981 | // op: Zn |
| 26982 | return 5; |
| 26983 | } |
| 26984 | break; |
| 26985 | } |
| 26986 | case AArch64::FCVTNT_Z2Z_StoB: { |
| 26987 | switch (OpNum) { |
| 26988 | case 0: |
| 26989 | // op: Zd |
| 26990 | return 0; |
| 26991 | case 2: |
| 26992 | // op: Zn |
| 26993 | return 6; |
| 26994 | } |
| 26995 | break; |
| 26996 | } |
| 26997 | case AArch64::LUTI6_S_4ZT3Z: { |
| 26998 | switch (OpNum) { |
| 26999 | case 0: |
| 27000 | // op: Zd |
| 27001 | return 0; |
| 27002 | case 2: |
| 27003 | // op: Zn |
| 27004 | return 7; |
| 27005 | } |
| 27006 | break; |
| 27007 | } |
| 27008 | case AArch64::PMOV_ZIP_D: |
| 27009 | case AArch64::PMOV_ZIP_H: |
| 27010 | case AArch64::PMOV_ZIP_S: { |
| 27011 | switch (OpNum) { |
| 27012 | case 0: |
| 27013 | // op: Zd |
| 27014 | return 0; |
| 27015 | case 3: |
| 27016 | // op: Pn |
| 27017 | return 5; |
| 27018 | case 2: |
| 27019 | // op: index |
| 27020 | return 17; |
| 27021 | } |
| 27022 | break; |
| 27023 | } |
| 27024 | case AArch64::PMOV_ZIP_B: { |
| 27025 | switch (OpNum) { |
| 27026 | case 0: |
| 27027 | // op: Zd |
| 27028 | return 0; |
| 27029 | case 3: |
| 27030 | // op: Pn |
| 27031 | return 5; |
| 27032 | } |
| 27033 | break; |
| 27034 | } |
| 27035 | case AArch64::TBXQ_ZZZ_B: |
| 27036 | case AArch64::TBXQ_ZZZ_D: |
| 27037 | case AArch64::TBXQ_ZZZ_H: |
| 27038 | case AArch64::TBXQ_ZZZ_S: |
| 27039 | case AArch64::TBX_ZZZ_B: |
| 27040 | case AArch64::TBX_ZZZ_D: |
| 27041 | case AArch64::TBX_ZZZ_H: |
| 27042 | case AArch64::TBX_ZZZ_S: { |
| 27043 | switch (OpNum) { |
| 27044 | case 0: |
| 27045 | // op: Zd |
| 27046 | return 0; |
| 27047 | case 3: |
| 27048 | // op: Zm |
| 27049 | return 16; |
| 27050 | case 2: |
| 27051 | // op: Zn |
| 27052 | return 5; |
| 27053 | } |
| 27054 | break; |
| 27055 | } |
| 27056 | case AArch64::BFCVTNT_ZPmZ: |
| 27057 | case AArch64::BFCVTNT_ZPzZ_StoH: |
| 27058 | case AArch64::FCVTLT_ZPmZ_HtoS: |
| 27059 | case AArch64::FCVTLT_ZPmZ_StoD: |
| 27060 | case AArch64::FCVTNT_ZPmZ_DtoS: |
| 27061 | case AArch64::FCVTNT_ZPmZ_StoH: |
| 27062 | case AArch64::FCVTNT_ZPzZ_DtoS: |
| 27063 | case AArch64::FCVTNT_ZPzZ_StoH: |
| 27064 | case AArch64::FCVTXNT_ZPmZ_DtoS: |
| 27065 | case AArch64::FCVTXNT_ZPzZ_StoD: { |
| 27066 | switch (OpNum) { |
| 27067 | case 0: |
| 27068 | // op: Zd |
| 27069 | return 0; |
| 27070 | case 3: |
| 27071 | // op: Zn |
| 27072 | return 5; |
| 27073 | case 2: |
| 27074 | // op: Pg |
| 27075 | return 10; |
| 27076 | } |
| 27077 | break; |
| 27078 | } |
| 27079 | case AArch64::BFMUL_2Z2Z: |
| 27080 | case AArch64::BFMUL_2ZZ: |
| 27081 | case AArch64::FMUL_2Z2Z_D: |
| 27082 | case AArch64::FMUL_2Z2Z_H: |
| 27083 | case AArch64::FMUL_2Z2Z_S: |
| 27084 | case AArch64::FMUL_2ZZ_D: |
| 27085 | case AArch64::FMUL_2ZZ_H: |
| 27086 | case AArch64::FMUL_2ZZ_S: { |
| 27087 | switch (OpNum) { |
| 27088 | case 0: |
| 27089 | // op: Zd |
| 27090 | return 1; |
| 27091 | case 1: |
| 27092 | // op: Zn |
| 27093 | return 6; |
| 27094 | case 2: |
| 27095 | // op: Zm |
| 27096 | return 17; |
| 27097 | } |
| 27098 | break; |
| 27099 | } |
| 27100 | case AArch64::MOVA_2ZMXI_H_D: |
| 27101 | case AArch64::MOVA_2ZMXI_V_D: { |
| 27102 | switch (OpNum) { |
| 27103 | case 0: |
| 27104 | // op: Zd |
| 27105 | return 1; |
| 27106 | case 2: |
| 27107 | // op: Rs |
| 27108 | return 13; |
| 27109 | case 1: |
| 27110 | // op: ZAn |
| 27111 | return 5; |
| 27112 | } |
| 27113 | break; |
| 27114 | } |
| 27115 | case AArch64::MOVA_2ZMXI_H_S: |
| 27116 | case AArch64::MOVA_2ZMXI_V_S: { |
| 27117 | switch (OpNum) { |
| 27118 | case 0: |
| 27119 | // op: Zd |
| 27120 | return 1; |
| 27121 | case 2: |
| 27122 | // op: Rs |
| 27123 | return 13; |
| 27124 | case 1: |
| 27125 | // op: ZAn |
| 27126 | return 6; |
| 27127 | case 3: |
| 27128 | // op: imm |
| 27129 | return 5; |
| 27130 | } |
| 27131 | break; |
| 27132 | } |
| 27133 | case AArch64::MOVA_2ZMXI_H_H: |
| 27134 | case AArch64::MOVA_2ZMXI_V_H: { |
| 27135 | switch (OpNum) { |
| 27136 | case 0: |
| 27137 | // op: Zd |
| 27138 | return 1; |
| 27139 | case 2: |
| 27140 | // op: Rs |
| 27141 | return 13; |
| 27142 | case 1: |
| 27143 | // op: ZAn |
| 27144 | return 7; |
| 27145 | case 3: |
| 27146 | // op: imm |
| 27147 | return 5; |
| 27148 | } |
| 27149 | break; |
| 27150 | } |
| 27151 | case AArch64::MOVA_2ZMXI_H_B: |
| 27152 | case AArch64::MOVA_2ZMXI_V_B: { |
| 27153 | switch (OpNum) { |
| 27154 | case 0: |
| 27155 | // op: Zd |
| 27156 | return 1; |
| 27157 | case 2: |
| 27158 | // op: Rs |
| 27159 | return 13; |
| 27160 | case 3: |
| 27161 | // op: imm |
| 27162 | return 5; |
| 27163 | } |
| 27164 | break; |
| 27165 | } |
| 27166 | case AArch64::UZP_VG2_2ZZZ_B: |
| 27167 | case AArch64::UZP_VG2_2ZZZ_D: |
| 27168 | case AArch64::UZP_VG2_2ZZZ_H: |
| 27169 | case AArch64::UZP_VG2_2ZZZ_Q: |
| 27170 | case AArch64::UZP_VG2_2ZZZ_S: |
| 27171 | case AArch64::ZIP_VG2_2ZZZ_B: |
| 27172 | case AArch64::ZIP_VG2_2ZZZ_D: |
| 27173 | case AArch64::ZIP_VG2_2ZZZ_H: |
| 27174 | case AArch64::ZIP_VG2_2ZZZ_Q: |
| 27175 | case AArch64::ZIP_VG2_2ZZZ_S: { |
| 27176 | switch (OpNum) { |
| 27177 | case 0: |
| 27178 | // op: Zd |
| 27179 | return 1; |
| 27180 | case 2: |
| 27181 | // op: Zm |
| 27182 | return 16; |
| 27183 | case 1: |
| 27184 | // op: Zn |
| 27185 | return 5; |
| 27186 | } |
| 27187 | break; |
| 27188 | } |
| 27189 | case AArch64::MOVAZ_2ZMI_H_D: |
| 27190 | case AArch64::MOVAZ_2ZMI_V_D: { |
| 27191 | switch (OpNum) { |
| 27192 | case 0: |
| 27193 | // op: Zd |
| 27194 | return 1; |
| 27195 | case 3: |
| 27196 | // op: Rs |
| 27197 | return 13; |
| 27198 | case 2: |
| 27199 | // op: ZAn |
| 27200 | return 5; |
| 27201 | } |
| 27202 | break; |
| 27203 | } |
| 27204 | case AArch64::MOVAZ_2ZMI_H_S: |
| 27205 | case AArch64::MOVAZ_2ZMI_V_S: { |
| 27206 | switch (OpNum) { |
| 27207 | case 0: |
| 27208 | // op: Zd |
| 27209 | return 1; |
| 27210 | case 3: |
| 27211 | // op: Rs |
| 27212 | return 13; |
| 27213 | case 2: |
| 27214 | // op: ZAn |
| 27215 | return 6; |
| 27216 | case 4: |
| 27217 | // op: imm |
| 27218 | return 5; |
| 27219 | } |
| 27220 | break; |
| 27221 | } |
| 27222 | case AArch64::MOVAZ_2ZMI_H_H: |
| 27223 | case AArch64::MOVAZ_2ZMI_V_H: { |
| 27224 | switch (OpNum) { |
| 27225 | case 0: |
| 27226 | // op: Zd |
| 27227 | return 1; |
| 27228 | case 3: |
| 27229 | // op: Rs |
| 27230 | return 13; |
| 27231 | case 2: |
| 27232 | // op: ZAn |
| 27233 | return 7; |
| 27234 | case 4: |
| 27235 | // op: imm |
| 27236 | return 5; |
| 27237 | } |
| 27238 | break; |
| 27239 | } |
| 27240 | case AArch64::MOVAZ_2ZMI_H_B: |
| 27241 | case AArch64::MOVAZ_2ZMI_V_B: { |
| 27242 | switch (OpNum) { |
| 27243 | case 0: |
| 27244 | // op: Zd |
| 27245 | return 1; |
| 27246 | case 3: |
| 27247 | // op: Rs |
| 27248 | return 13; |
| 27249 | case 4: |
| 27250 | // op: imm |
| 27251 | return 5; |
| 27252 | } |
| 27253 | break; |
| 27254 | } |
| 27255 | case AArch64::LUTI6_4Z2Z2ZI: { |
| 27256 | switch (OpNum) { |
| 27257 | case 0: |
| 27258 | // op: Zd |
| 27259 | return 2; |
| 27260 | case 1: |
| 27261 | // op: Zn |
| 27262 | return 5; |
| 27263 | case 2: |
| 27264 | // op: Zm |
| 27265 | return 16; |
| 27266 | case 3: |
| 27267 | // op: i1 |
| 27268 | return 22; |
| 27269 | } |
| 27270 | break; |
| 27271 | } |
| 27272 | case AArch64::BFMUL_4ZZ: |
| 27273 | case AArch64::FMUL_4ZZ_D: |
| 27274 | case AArch64::FMUL_4ZZ_H: |
| 27275 | case AArch64::FMUL_4ZZ_S: { |
| 27276 | switch (OpNum) { |
| 27277 | case 0: |
| 27278 | // op: Zd |
| 27279 | return 2; |
| 27280 | case 1: |
| 27281 | // op: Zn |
| 27282 | return 7; |
| 27283 | case 2: |
| 27284 | // op: Zm |
| 27285 | return 17; |
| 27286 | } |
| 27287 | break; |
| 27288 | } |
| 27289 | case AArch64::BFMUL_4Z4Z: |
| 27290 | case AArch64::FMUL_4Z4Z_D: |
| 27291 | case AArch64::FMUL_4Z4Z_H: |
| 27292 | case AArch64::FMUL_4Z4Z_S: { |
| 27293 | switch (OpNum) { |
| 27294 | case 0: |
| 27295 | // op: Zd |
| 27296 | return 2; |
| 27297 | case 1: |
| 27298 | // op: Zn |
| 27299 | return 7; |
| 27300 | case 2: |
| 27301 | // op: Zm |
| 27302 | return 18; |
| 27303 | } |
| 27304 | break; |
| 27305 | } |
| 27306 | case AArch64::MOVA_4ZMXI_H_D: |
| 27307 | case AArch64::MOVA_4ZMXI_H_S: |
| 27308 | case AArch64::MOVA_4ZMXI_V_D: |
| 27309 | case AArch64::MOVA_4ZMXI_V_S: { |
| 27310 | switch (OpNum) { |
| 27311 | case 0: |
| 27312 | // op: Zd |
| 27313 | return 2; |
| 27314 | case 2: |
| 27315 | // op: Rs |
| 27316 | return 13; |
| 27317 | case 1: |
| 27318 | // op: ZAn |
| 27319 | return 5; |
| 27320 | } |
| 27321 | break; |
| 27322 | } |
| 27323 | case AArch64::MOVA_4ZMXI_H_H: |
| 27324 | case AArch64::MOVA_4ZMXI_V_H: { |
| 27325 | switch (OpNum) { |
| 27326 | case 0: |
| 27327 | // op: Zd |
| 27328 | return 2; |
| 27329 | case 2: |
| 27330 | // op: Rs |
| 27331 | return 13; |
| 27332 | case 1: |
| 27333 | // op: ZAn |
| 27334 | return 6; |
| 27335 | case 3: |
| 27336 | // op: imm |
| 27337 | return 5; |
| 27338 | } |
| 27339 | break; |
| 27340 | } |
| 27341 | case AArch64::MOVA_4ZMXI_H_B: |
| 27342 | case AArch64::MOVA_4ZMXI_V_B: { |
| 27343 | switch (OpNum) { |
| 27344 | case 0: |
| 27345 | // op: Zd |
| 27346 | return 2; |
| 27347 | case 2: |
| 27348 | // op: Rs |
| 27349 | return 13; |
| 27350 | case 3: |
| 27351 | // op: imm |
| 27352 | return 5; |
| 27353 | } |
| 27354 | break; |
| 27355 | } |
| 27356 | case AArch64::LUTI6_4ZT3Z: { |
| 27357 | switch (OpNum) { |
| 27358 | case 0: |
| 27359 | // op: Zd |
| 27360 | return 2; |
| 27361 | case 2: |
| 27362 | // op: Zn |
| 27363 | return 7; |
| 27364 | } |
| 27365 | break; |
| 27366 | } |
| 27367 | case AArch64::MOVAZ_4ZMI_H_D: |
| 27368 | case AArch64::MOVAZ_4ZMI_H_S: |
| 27369 | case AArch64::MOVAZ_4ZMI_V_D: |
| 27370 | case AArch64::MOVAZ_4ZMI_V_S: { |
| 27371 | switch (OpNum) { |
| 27372 | case 0: |
| 27373 | // op: Zd |
| 27374 | return 2; |
| 27375 | case 3: |
| 27376 | // op: Rs |
| 27377 | return 13; |
| 27378 | case 2: |
| 27379 | // op: ZAn |
| 27380 | return 5; |
| 27381 | } |
| 27382 | break; |
| 27383 | } |
| 27384 | case AArch64::MOVAZ_4ZMI_H_H: |
| 27385 | case AArch64::MOVAZ_4ZMI_V_H: { |
| 27386 | switch (OpNum) { |
| 27387 | case 0: |
| 27388 | // op: Zd |
| 27389 | return 2; |
| 27390 | case 3: |
| 27391 | // op: Rs |
| 27392 | return 13; |
| 27393 | case 2: |
| 27394 | // op: ZAn |
| 27395 | return 6; |
| 27396 | case 4: |
| 27397 | // op: imm |
| 27398 | return 5; |
| 27399 | } |
| 27400 | break; |
| 27401 | } |
| 27402 | case AArch64::MOVAZ_4ZMI_H_B: |
| 27403 | case AArch64::MOVAZ_4ZMI_V_B: { |
| 27404 | switch (OpNum) { |
| 27405 | case 0: |
| 27406 | // op: Zd |
| 27407 | return 2; |
| 27408 | case 3: |
| 27409 | // op: Rs |
| 27410 | return 13; |
| 27411 | case 4: |
| 27412 | // op: imm |
| 27413 | return 5; |
| 27414 | } |
| 27415 | break; |
| 27416 | } |
| 27417 | case AArch64::FCMLA_ZPmZZ_D: |
| 27418 | case AArch64::FCMLA_ZPmZZ_H: |
| 27419 | case AArch64::FCMLA_ZPmZZ_S: { |
| 27420 | switch (OpNum) { |
| 27421 | case 0: |
| 27422 | // op: Zda |
| 27423 | return 0; |
| 27424 | case 1: |
| 27425 | // op: Pg |
| 27426 | return 10; |
| 27427 | case 3: |
| 27428 | // op: Zn |
| 27429 | return 5; |
| 27430 | case 4: |
| 27431 | // op: Zm |
| 27432 | return 16; |
| 27433 | case 5: |
| 27434 | // op: imm |
| 27435 | return 13; |
| 27436 | } |
| 27437 | break; |
| 27438 | } |
| 27439 | case AArch64::SDOT_ZZZI_HtoS: |
| 27440 | case AArch64::UDOT_ZZZI_HtoS: { |
| 27441 | switch (OpNum) { |
| 27442 | case 0: |
| 27443 | // op: Zda |
| 27444 | return 0; |
| 27445 | case 2: |
| 27446 | // op: Zn |
| 27447 | return 5; |
| 27448 | case 3: |
| 27449 | // op: Zm |
| 27450 | return 16; |
| 27451 | case 4: |
| 27452 | // op: i2 |
| 27453 | return 19; |
| 27454 | } |
| 27455 | break; |
| 27456 | } |
| 27457 | case AArch64::SUDOT_ZZZI: |
| 27458 | case AArch64::USDOT_ZZZI: { |
| 27459 | switch (OpNum) { |
| 27460 | case 0: |
| 27461 | // op: Zda |
| 27462 | return 0; |
| 27463 | case 2: |
| 27464 | // op: Zn |
| 27465 | return 5; |
| 27466 | case 3: |
| 27467 | // op: Zm |
| 27468 | return 16; |
| 27469 | case 4: |
| 27470 | // op: idx |
| 27471 | return 19; |
| 27472 | } |
| 27473 | break; |
| 27474 | } |
| 27475 | case AArch64::FMLALB_ZZZI: |
| 27476 | case AArch64::FMLALLBB_ZZZI: |
| 27477 | case AArch64::FMLALLBT_ZZZI: |
| 27478 | case AArch64::FMLALLTB_ZZZI: |
| 27479 | case AArch64::FMLALLTT_ZZZI: |
| 27480 | case AArch64::FMLALT_ZZZI: { |
| 27481 | switch (OpNum) { |
| 27482 | case 0: |
| 27483 | // op: Zda |
| 27484 | return 0; |
| 27485 | case 2: |
| 27486 | // op: Zn |
| 27487 | return 5; |
| 27488 | case 3: |
| 27489 | // op: Zm |
| 27490 | return 16; |
| 27491 | case 4: |
| 27492 | // op: imm4 |
| 27493 | return 10; |
| 27494 | } |
| 27495 | break; |
| 27496 | } |
| 27497 | case AArch64::BFMLALB_ZZZI: |
| 27498 | case AArch64::BFMLALT_ZZZI: |
| 27499 | case AArch64::BFMLSLB_ZZZI_S: |
| 27500 | case AArch64::BFMLSLT_ZZZI_S: |
| 27501 | case AArch64::FDOT_ZZZI_BtoH: |
| 27502 | case AArch64::FMLALB_ZZZI_SHH: |
| 27503 | case AArch64::FMLALT_ZZZI_SHH: |
| 27504 | case AArch64::FMLSLB_ZZZI_SHH: |
| 27505 | case AArch64::FMLSLT_ZZZI_SHH: |
| 27506 | case AArch64::SMLALB_ZZZI_D: |
| 27507 | case AArch64::SMLALB_ZZZI_S: |
| 27508 | case AArch64::SMLALT_ZZZI_D: |
| 27509 | case AArch64::SMLALT_ZZZI_S: |
| 27510 | case AArch64::SMLSLB_ZZZI_D: |
| 27511 | case AArch64::SMLSLB_ZZZI_S: |
| 27512 | case AArch64::SMLSLT_ZZZI_D: |
| 27513 | case AArch64::SMLSLT_ZZZI_S: |
| 27514 | case AArch64::SQDMLALB_ZZZI_D: |
| 27515 | case AArch64::SQDMLALB_ZZZI_S: |
| 27516 | case AArch64::SQDMLALT_ZZZI_D: |
| 27517 | case AArch64::SQDMLALT_ZZZI_S: |
| 27518 | case AArch64::SQDMLSLB_ZZZI_D: |
| 27519 | case AArch64::SQDMLSLB_ZZZI_S: |
| 27520 | case AArch64::SQDMLSLT_ZZZI_D: |
| 27521 | case AArch64::SQDMLSLT_ZZZI_S: |
| 27522 | case AArch64::UMLALB_ZZZI_D: |
| 27523 | case AArch64::UMLALB_ZZZI_S: |
| 27524 | case AArch64::UMLALT_ZZZI_D: |
| 27525 | case AArch64::UMLALT_ZZZI_S: |
| 27526 | case AArch64::UMLSLB_ZZZI_D: |
| 27527 | case AArch64::UMLSLB_ZZZI_S: |
| 27528 | case AArch64::UMLSLT_ZZZI_D: |
| 27529 | case AArch64::UMLSLT_ZZZI_S: { |
| 27530 | switch (OpNum) { |
| 27531 | case 0: |
| 27532 | // op: Zda |
| 27533 | return 0; |
| 27534 | case 2: |
| 27535 | // op: Zn |
| 27536 | return 5; |
| 27537 | case 3: |
| 27538 | // op: Zm |
| 27539 | return 16; |
| 27540 | case 4: |
| 27541 | // op: iop |
| 27542 | return 11; |
| 27543 | } |
| 27544 | break; |
| 27545 | } |
| 27546 | case AArch64::BFDOT_ZZI: |
| 27547 | case AArch64::BFMLA_ZZZI: |
| 27548 | case AArch64::BFMLS_ZZZI: |
| 27549 | case AArch64::FDOT_ZZZI_BtoS: |
| 27550 | case AArch64::FDOT_ZZZI_S: |
| 27551 | case AArch64::FMLA_ZZZI_H: |
| 27552 | case AArch64::FMLA_ZZZI_S: |
| 27553 | case AArch64::FMLS_ZZZI_H: |
| 27554 | case AArch64::FMLS_ZZZI_S: |
| 27555 | case AArch64::MLA_ZZZI_H: |
| 27556 | case AArch64::MLA_ZZZI_S: |
| 27557 | case AArch64::MLS_ZZZI_H: |
| 27558 | case AArch64::MLS_ZZZI_S: |
| 27559 | case AArch64::SQRDMLAH_ZZZI_H: |
| 27560 | case AArch64::SQRDMLAH_ZZZI_S: |
| 27561 | case AArch64::SQRDMLSH_ZZZI_H: |
| 27562 | case AArch64::SQRDMLSH_ZZZI_S: { |
| 27563 | switch (OpNum) { |
| 27564 | case 0: |
| 27565 | // op: Zda |
| 27566 | return 0; |
| 27567 | case 2: |
| 27568 | // op: Zn |
| 27569 | return 5; |
| 27570 | case 3: |
| 27571 | // op: Zm |
| 27572 | return 16; |
| 27573 | case 4: |
| 27574 | // op: iop |
| 27575 | return 19; |
| 27576 | } |
| 27577 | break; |
| 27578 | } |
| 27579 | case AArch64::FMLA_ZZZI_D: |
| 27580 | case AArch64::FMLS_ZZZI_D: |
| 27581 | case AArch64::MLA_ZZZI_D: |
| 27582 | case AArch64::MLS_ZZZI_D: |
| 27583 | case AArch64::SQRDMLAH_ZZZI_D: |
| 27584 | case AArch64::SQRDMLSH_ZZZI_D: { |
| 27585 | switch (OpNum) { |
| 27586 | case 0: |
| 27587 | // op: Zda |
| 27588 | return 0; |
| 27589 | case 2: |
| 27590 | // op: Zn |
| 27591 | return 5; |
| 27592 | case 3: |
| 27593 | // op: Zm |
| 27594 | return 16; |
| 27595 | case 4: |
| 27596 | // op: iop |
| 27597 | return 20; |
| 27598 | } |
| 27599 | break; |
| 27600 | } |
| 27601 | case AArch64::CDOT_ZZZ_D: |
| 27602 | case AArch64::CDOT_ZZZ_S: |
| 27603 | case AArch64::CMLA_ZZZ_B: |
| 27604 | case AArch64::CMLA_ZZZ_D: |
| 27605 | case AArch64::CMLA_ZZZ_H: |
| 27606 | case AArch64::CMLA_ZZZ_S: |
| 27607 | case AArch64::SQRDCMLAH_ZZZ_B: |
| 27608 | case AArch64::SQRDCMLAH_ZZZ_D: |
| 27609 | case AArch64::SQRDCMLAH_ZZZ_H: |
| 27610 | case AArch64::SQRDCMLAH_ZZZ_S: { |
| 27611 | switch (OpNum) { |
| 27612 | case 0: |
| 27613 | // op: Zda |
| 27614 | return 0; |
| 27615 | case 2: |
| 27616 | // op: Zn |
| 27617 | return 5; |
| 27618 | case 3: |
| 27619 | // op: Zm |
| 27620 | return 16; |
| 27621 | case 4: |
| 27622 | // op: rot |
| 27623 | return 10; |
| 27624 | } |
| 27625 | break; |
| 27626 | } |
| 27627 | case AArch64::ADCLB_ZZZ_D: |
| 27628 | case AArch64::ADCLB_ZZZ_S: |
| 27629 | case AArch64::ADCLT_ZZZ_D: |
| 27630 | case AArch64::ADCLT_ZZZ_S: |
| 27631 | case AArch64::BFDOT_ZZZ: |
| 27632 | case AArch64::BFMLALB_ZZZ: |
| 27633 | case AArch64::BFMLALT_ZZZ: |
| 27634 | case AArch64::BFMLSLB_ZZZ_S: |
| 27635 | case AArch64::BFMLSLT_ZZZ_S: |
| 27636 | case AArch64::BFMMLA_ZZZ_H: |
| 27637 | case AArch64::BFMMLA_ZZZ_HtoS: |
| 27638 | case AArch64::FDOT_ZZZ_BtoH: |
| 27639 | case AArch64::FDOT_ZZZ_BtoS: |
| 27640 | case AArch64::FDOT_ZZZ_S: |
| 27641 | case AArch64::FMLALB_ZZZ: |
| 27642 | case AArch64::FMLALB_ZZZ_SHH: |
| 27643 | case AArch64::FMLALLBB_ZZZ: |
| 27644 | case AArch64::FMLALLBT_ZZZ: |
| 27645 | case AArch64::FMLALLTB_ZZZ: |
| 27646 | case AArch64::FMLALLTT_ZZZ: |
| 27647 | case AArch64::FMLALT_ZZZ: |
| 27648 | case AArch64::FMLALT_ZZZ_SHH: |
| 27649 | case AArch64::FMLLA_ZZZ_HtoS: |
| 27650 | case AArch64::FMLSLB_ZZZ_SHH: |
| 27651 | case AArch64::FMLSLT_ZZZ_SHH: |
| 27652 | case AArch64::FMMLA_ZZZ_BtoH: |
| 27653 | case AArch64::FMMLA_ZZZ_BtoS: |
| 27654 | case AArch64::FMMLA_ZZZ_D: |
| 27655 | case AArch64::FMMLA_ZZZ_H: |
| 27656 | case AArch64::FMMLA_ZZZ_S: |
| 27657 | case AArch64::MLA_CPA: |
| 27658 | case AArch64::SABALB_ZZZ_D: |
| 27659 | case AArch64::SABALB_ZZZ_H: |
| 27660 | case AArch64::SABALB_ZZZ_S: |
| 27661 | case AArch64::SABALT_ZZZ_D: |
| 27662 | case AArch64::SABALT_ZZZ_H: |
| 27663 | case AArch64::SABALT_ZZZ_S: |
| 27664 | case AArch64::SABAL_ZZZ_BtoH: |
| 27665 | case AArch64::SABAL_ZZZ_HtoS: |
| 27666 | case AArch64::SABAL_ZZZ_StoD: |
| 27667 | case AArch64::SABA_ZZZ_B: |
| 27668 | case AArch64::SABA_ZZZ_D: |
| 27669 | case AArch64::SABA_ZZZ_H: |
| 27670 | case AArch64::SABA_ZZZ_S: |
| 27671 | case AArch64::SBCLB_ZZZ_D: |
| 27672 | case AArch64::SBCLB_ZZZ_S: |
| 27673 | case AArch64::SBCLT_ZZZ_D: |
| 27674 | case AArch64::SBCLT_ZZZ_S: |
| 27675 | case AArch64::SDOT_ZZZ_BtoH: |
| 27676 | case AArch64::SDOT_ZZZ_BtoS: |
| 27677 | case AArch64::SDOT_ZZZ_HtoD: |
| 27678 | case AArch64::SDOT_ZZZ_HtoS: |
| 27679 | case AArch64::SMLALB_ZZZ_D: |
| 27680 | case AArch64::SMLALB_ZZZ_H: |
| 27681 | case AArch64::SMLALB_ZZZ_S: |
| 27682 | case AArch64::SMLALT_ZZZ_D: |
| 27683 | case AArch64::SMLALT_ZZZ_H: |
| 27684 | case AArch64::SMLALT_ZZZ_S: |
| 27685 | case AArch64::SMLSLB_ZZZ_D: |
| 27686 | case AArch64::SMLSLB_ZZZ_H: |
| 27687 | case AArch64::SMLSLB_ZZZ_S: |
| 27688 | case AArch64::SMLSLT_ZZZ_D: |
| 27689 | case AArch64::SMLSLT_ZZZ_H: |
| 27690 | case AArch64::SMLSLT_ZZZ_S: |
| 27691 | case AArch64::SMMLA_ZZZ: |
| 27692 | case AArch64::SQDMLALBT_ZZZ_D: |
| 27693 | case AArch64::SQDMLALBT_ZZZ_H: |
| 27694 | case AArch64::SQDMLALBT_ZZZ_S: |
| 27695 | case AArch64::SQDMLALB_ZZZ_D: |
| 27696 | case AArch64::SQDMLALB_ZZZ_H: |
| 27697 | case AArch64::SQDMLALB_ZZZ_S: |
| 27698 | case AArch64::SQDMLALT_ZZZ_D: |
| 27699 | case AArch64::SQDMLALT_ZZZ_H: |
| 27700 | case AArch64::SQDMLALT_ZZZ_S: |
| 27701 | case AArch64::SQDMLSLBT_ZZZ_D: |
| 27702 | case AArch64::SQDMLSLBT_ZZZ_H: |
| 27703 | case AArch64::SQDMLSLBT_ZZZ_S: |
| 27704 | case AArch64::SQDMLSLB_ZZZ_D: |
| 27705 | case AArch64::SQDMLSLB_ZZZ_H: |
| 27706 | case AArch64::SQDMLSLB_ZZZ_S: |
| 27707 | case AArch64::SQDMLSLT_ZZZ_D: |
| 27708 | case AArch64::SQDMLSLT_ZZZ_H: |
| 27709 | case AArch64::SQDMLSLT_ZZZ_S: |
| 27710 | case AArch64::SQRDMLAH_ZZZ_B: |
| 27711 | case AArch64::SQRDMLAH_ZZZ_D: |
| 27712 | case AArch64::SQRDMLAH_ZZZ_H: |
| 27713 | case AArch64::SQRDMLAH_ZZZ_S: |
| 27714 | case AArch64::SQRDMLSH_ZZZ_B: |
| 27715 | case AArch64::SQRDMLSH_ZZZ_D: |
| 27716 | case AArch64::SQRDMLSH_ZZZ_H: |
| 27717 | case AArch64::SQRDMLSH_ZZZ_S: |
| 27718 | case AArch64::UABALB_ZZZ_D: |
| 27719 | case AArch64::UABALB_ZZZ_H: |
| 27720 | case AArch64::UABALB_ZZZ_S: |
| 27721 | case AArch64::UABALT_ZZZ_D: |
| 27722 | case AArch64::UABALT_ZZZ_H: |
| 27723 | case AArch64::UABALT_ZZZ_S: |
| 27724 | case AArch64::UABAL_ZZZ_BtoH: |
| 27725 | case AArch64::UABAL_ZZZ_HtoS: |
| 27726 | case AArch64::UABAL_ZZZ_StoD: |
| 27727 | case AArch64::UABA_ZZZ_B: |
| 27728 | case AArch64::UABA_ZZZ_D: |
| 27729 | case AArch64::UABA_ZZZ_H: |
| 27730 | case AArch64::UABA_ZZZ_S: |
| 27731 | case AArch64::UDOT_ZZZ_BtoH: |
| 27732 | case AArch64::UDOT_ZZZ_BtoS: |
| 27733 | case AArch64::UDOT_ZZZ_HtoD: |
| 27734 | case AArch64::UDOT_ZZZ_HtoS: |
| 27735 | case AArch64::UMLALB_ZZZ_D: |
| 27736 | case AArch64::UMLALB_ZZZ_H: |
| 27737 | case AArch64::UMLALB_ZZZ_S: |
| 27738 | case AArch64::UMLALT_ZZZ_D: |
| 27739 | case AArch64::UMLALT_ZZZ_H: |
| 27740 | case AArch64::UMLALT_ZZZ_S: |
| 27741 | case AArch64::UMLSLB_ZZZ_D: |
| 27742 | case AArch64::UMLSLB_ZZZ_H: |
| 27743 | case AArch64::UMLSLB_ZZZ_S: |
| 27744 | case AArch64::UMLSLT_ZZZ_D: |
| 27745 | case AArch64::UMLSLT_ZZZ_H: |
| 27746 | case AArch64::UMLSLT_ZZZ_S: |
| 27747 | case AArch64::UMMLA_ZZZ: |
| 27748 | case AArch64::USDOT_ZZZ: |
| 27749 | case AArch64::USMMLA_ZZZ: { |
| 27750 | switch (OpNum) { |
| 27751 | case 0: |
| 27752 | // op: Zda |
| 27753 | return 0; |
| 27754 | case 2: |
| 27755 | // op: Zn |
| 27756 | return 5; |
| 27757 | case 3: |
| 27758 | // op: Zm |
| 27759 | return 16; |
| 27760 | } |
| 27761 | break; |
| 27762 | } |
| 27763 | case AArch64::SRSRA_ZZI_B: |
| 27764 | case AArch64::SRSRA_ZZI_D: |
| 27765 | case AArch64::SRSRA_ZZI_H: |
| 27766 | case AArch64::SRSRA_ZZI_S: |
| 27767 | case AArch64::SSRA_ZZI_B: |
| 27768 | case AArch64::SSRA_ZZI_D: |
| 27769 | case AArch64::SSRA_ZZI_H: |
| 27770 | case AArch64::SSRA_ZZI_S: |
| 27771 | case AArch64::URSRA_ZZI_B: |
| 27772 | case AArch64::URSRA_ZZI_D: |
| 27773 | case AArch64::URSRA_ZZI_H: |
| 27774 | case AArch64::URSRA_ZZI_S: |
| 27775 | case AArch64::USRA_ZZI_B: |
| 27776 | case AArch64::USRA_ZZI_D: |
| 27777 | case AArch64::USRA_ZZI_H: |
| 27778 | case AArch64::USRA_ZZI_S: { |
| 27779 | switch (OpNum) { |
| 27780 | case 0: |
| 27781 | // op: Zda |
| 27782 | return 0; |
| 27783 | case 2: |
| 27784 | // op: Zn |
| 27785 | return 5; |
| 27786 | case 3: |
| 27787 | // op: imm |
| 27788 | return 16; |
| 27789 | } |
| 27790 | break; |
| 27791 | } |
| 27792 | case AArch64::SDOT_ZZZI_BtoH: |
| 27793 | case AArch64::SDOT_ZZZI_BtoS: |
| 27794 | case AArch64::UDOT_ZZZI_BtoH: |
| 27795 | case AArch64::UDOT_ZZZI_BtoS: { |
| 27796 | switch (OpNum) { |
| 27797 | case 0: |
| 27798 | // op: Zda |
| 27799 | return 0; |
| 27800 | case 2: |
| 27801 | // op: Zn |
| 27802 | return 5; |
| 27803 | case 4: |
| 27804 | // op: iop |
| 27805 | return 19; |
| 27806 | case 3: |
| 27807 | // op: Zm |
| 27808 | return 16; |
| 27809 | } |
| 27810 | break; |
| 27811 | } |
| 27812 | case AArch64::SDOT_ZZZI_HtoD: |
| 27813 | case AArch64::UDOT_ZZZI_HtoD: { |
| 27814 | switch (OpNum) { |
| 27815 | case 0: |
| 27816 | // op: Zda |
| 27817 | return 0; |
| 27818 | case 2: |
| 27819 | // op: Zn |
| 27820 | return 5; |
| 27821 | case 4: |
| 27822 | // op: iop |
| 27823 | return 20; |
| 27824 | case 3: |
| 27825 | // op: Zm |
| 27826 | return 16; |
| 27827 | } |
| 27828 | break; |
| 27829 | } |
| 27830 | case AArch64::FCMLA_ZZZI_H: { |
| 27831 | switch (OpNum) { |
| 27832 | case 0: |
| 27833 | // op: Zda |
| 27834 | return 0; |
| 27835 | case 2: |
| 27836 | // op: Zn |
| 27837 | return 5; |
| 27838 | case 5: |
| 27839 | // op: imm |
| 27840 | return 10; |
| 27841 | case 3: |
| 27842 | // op: Zm |
| 27843 | return 16; |
| 27844 | case 4: |
| 27845 | // op: iop |
| 27846 | return 19; |
| 27847 | } |
| 27848 | break; |
| 27849 | } |
| 27850 | case AArch64::FCMLA_ZZZI_S: { |
| 27851 | switch (OpNum) { |
| 27852 | case 0: |
| 27853 | // op: Zda |
| 27854 | return 0; |
| 27855 | case 2: |
| 27856 | // op: Zn |
| 27857 | return 5; |
| 27858 | case 5: |
| 27859 | // op: imm |
| 27860 | return 10; |
| 27861 | case 3: |
| 27862 | // op: Zm |
| 27863 | return 16; |
| 27864 | case 4: |
| 27865 | // op: iop |
| 27866 | return 20; |
| 27867 | } |
| 27868 | break; |
| 27869 | } |
| 27870 | case AArch64::CDOT_ZZZI_S: |
| 27871 | case AArch64::CMLA_ZZZI_H: |
| 27872 | case AArch64::SQRDCMLAH_ZZZI_H: { |
| 27873 | switch (OpNum) { |
| 27874 | case 0: |
| 27875 | // op: Zda |
| 27876 | return 0; |
| 27877 | case 2: |
| 27878 | // op: Zn |
| 27879 | return 5; |
| 27880 | case 5: |
| 27881 | // op: rot |
| 27882 | return 10; |
| 27883 | case 4: |
| 27884 | // op: iop |
| 27885 | return 19; |
| 27886 | case 3: |
| 27887 | // op: Zm |
| 27888 | return 16; |
| 27889 | } |
| 27890 | break; |
| 27891 | } |
| 27892 | case AArch64::CDOT_ZZZI_D: |
| 27893 | case AArch64::CMLA_ZZZI_S: |
| 27894 | case AArch64::SQRDCMLAH_ZZZI_S: { |
| 27895 | switch (OpNum) { |
| 27896 | case 0: |
| 27897 | // op: Zda |
| 27898 | return 0; |
| 27899 | case 2: |
| 27900 | // op: Zn |
| 27901 | return 5; |
| 27902 | case 5: |
| 27903 | // op: rot |
| 27904 | return 10; |
| 27905 | case 4: |
| 27906 | // op: iop |
| 27907 | return 20; |
| 27908 | case 3: |
| 27909 | // op: Zm |
| 27910 | return 16; |
| 27911 | } |
| 27912 | break; |
| 27913 | } |
| 27914 | case AArch64::MAD_CPA: { |
| 27915 | switch (OpNum) { |
| 27916 | case 0: |
| 27917 | // op: Zdn |
| 27918 | return 0; |
| 27919 | case 2: |
| 27920 | // op: Zm |
| 27921 | return 16; |
| 27922 | case 3: |
| 27923 | // op: Za |
| 27924 | return 5; |
| 27925 | } |
| 27926 | break; |
| 27927 | } |
| 27928 | case AArch64::XAR_ZZZI_B: |
| 27929 | case AArch64::XAR_ZZZI_D: |
| 27930 | case AArch64::XAR_ZZZI_H: |
| 27931 | case AArch64::XAR_ZZZI_S: { |
| 27932 | switch (OpNum) { |
| 27933 | case 0: |
| 27934 | // op: Zdn |
| 27935 | return 0; |
| 27936 | case 2: |
| 27937 | // op: Zm |
| 27938 | return 5; |
| 27939 | case 3: |
| 27940 | // op: imm |
| 27941 | return 16; |
| 27942 | } |
| 27943 | break; |
| 27944 | } |
| 27945 | case AArch64::FTMAD_ZZI_D: |
| 27946 | case AArch64::FTMAD_ZZI_H: |
| 27947 | case AArch64::FTMAD_ZZI_S: { |
| 27948 | switch (OpNum) { |
| 27949 | case 0: |
| 27950 | // op: Zdn |
| 27951 | return 0; |
| 27952 | case 2: |
| 27953 | // op: Zm |
| 27954 | return 5; |
| 27955 | case 3: |
| 27956 | // op: imm3 |
| 27957 | return 16; |
| 27958 | } |
| 27959 | break; |
| 27960 | } |
| 27961 | case AArch64::EXTQ_ZZI: { |
| 27962 | switch (OpNum) { |
| 27963 | case 0: |
| 27964 | // op: Zdn |
| 27965 | return 0; |
| 27966 | case 2: |
| 27967 | // op: Zm |
| 27968 | return 5; |
| 27969 | case 3: |
| 27970 | // op: imm4 |
| 27971 | return 16; |
| 27972 | } |
| 27973 | break; |
| 27974 | } |
| 27975 | case AArch64::EXT_ZZI: { |
| 27976 | switch (OpNum) { |
| 27977 | case 0: |
| 27978 | // op: Zdn |
| 27979 | return 0; |
| 27980 | case 2: |
| 27981 | // op: Zm |
| 27982 | return 5; |
| 27983 | case 3: |
| 27984 | // op: imm8 |
| 27985 | return 10; |
| 27986 | } |
| 27987 | break; |
| 27988 | } |
| 27989 | case AArch64::CADD_ZZI_B: |
| 27990 | case AArch64::CADD_ZZI_D: |
| 27991 | case AArch64::CADD_ZZI_H: |
| 27992 | case AArch64::CADD_ZZI_S: |
| 27993 | case AArch64::SQCADD_ZZI_B: |
| 27994 | case AArch64::SQCADD_ZZI_D: |
| 27995 | case AArch64::SQCADD_ZZI_H: |
| 27996 | case AArch64::SQCADD_ZZI_S: { |
| 27997 | switch (OpNum) { |
| 27998 | case 0: |
| 27999 | // op: Zdn |
| 28000 | return 0; |
| 28001 | case 2: |
| 28002 | // op: Zm |
| 28003 | return 5; |
| 28004 | case 3: |
| 28005 | // op: rot |
| 28006 | return 10; |
| 28007 | } |
| 28008 | break; |
| 28009 | } |
| 28010 | case AArch64::AESD_ZZZ_B: |
| 28011 | case AArch64::AESE_ZZZ_B: |
| 28012 | case AArch64::SM4E_ZZZ_S: { |
| 28013 | switch (OpNum) { |
| 28014 | case 0: |
| 28015 | // op: Zdn |
| 28016 | return 0; |
| 28017 | case 2: |
| 28018 | // op: Zm |
| 28019 | return 5; |
| 28020 | } |
| 28021 | break; |
| 28022 | } |
| 28023 | case AArch64::ADD_ZI_B: |
| 28024 | case AArch64::ADD_ZI_D: |
| 28025 | case AArch64::ADD_ZI_H: |
| 28026 | case AArch64::ADD_ZI_S: |
| 28027 | case AArch64::MUL_ZI_B: |
| 28028 | case AArch64::MUL_ZI_D: |
| 28029 | case AArch64::MUL_ZI_H: |
| 28030 | case AArch64::MUL_ZI_S: |
| 28031 | case AArch64::SMAX_ZI_B: |
| 28032 | case AArch64::SMAX_ZI_D: |
| 28033 | case AArch64::SMAX_ZI_H: |
| 28034 | case AArch64::SMAX_ZI_S: |
| 28035 | case AArch64::SMIN_ZI_B: |
| 28036 | case AArch64::SMIN_ZI_D: |
| 28037 | case AArch64::SMIN_ZI_H: |
| 28038 | case AArch64::SMIN_ZI_S: |
| 28039 | case AArch64::SQADD_ZI_B: |
| 28040 | case AArch64::SQADD_ZI_D: |
| 28041 | case AArch64::SQADD_ZI_H: |
| 28042 | case AArch64::SQADD_ZI_S: |
| 28043 | case AArch64::SQSUB_ZI_B: |
| 28044 | case AArch64::SQSUB_ZI_D: |
| 28045 | case AArch64::SQSUB_ZI_H: |
| 28046 | case AArch64::SQSUB_ZI_S: |
| 28047 | case AArch64::SUBR_ZI_B: |
| 28048 | case AArch64::SUBR_ZI_D: |
| 28049 | case AArch64::SUBR_ZI_H: |
| 28050 | case AArch64::SUBR_ZI_S: |
| 28051 | case AArch64::SUB_ZI_B: |
| 28052 | case AArch64::SUB_ZI_D: |
| 28053 | case AArch64::SUB_ZI_H: |
| 28054 | case AArch64::SUB_ZI_S: |
| 28055 | case AArch64::UMAX_ZI_B: |
| 28056 | case AArch64::UMAX_ZI_D: |
| 28057 | case AArch64::UMAX_ZI_H: |
| 28058 | case AArch64::UMAX_ZI_S: |
| 28059 | case AArch64::UMIN_ZI_B: |
| 28060 | case AArch64::UMIN_ZI_D: |
| 28061 | case AArch64::UMIN_ZI_H: |
| 28062 | case AArch64::UMIN_ZI_S: |
| 28063 | case AArch64::UQADD_ZI_B: |
| 28064 | case AArch64::UQADD_ZI_D: |
| 28065 | case AArch64::UQADD_ZI_H: |
| 28066 | case AArch64::UQADD_ZI_S: |
| 28067 | case AArch64::UQSUB_ZI_B: |
| 28068 | case AArch64::UQSUB_ZI_D: |
| 28069 | case AArch64::UQSUB_ZI_H: |
| 28070 | case AArch64::UQSUB_ZI_S: { |
| 28071 | switch (OpNum) { |
| 28072 | case 0: |
| 28073 | // op: Zdn |
| 28074 | return 0; |
| 28075 | case 2: |
| 28076 | // op: imm |
| 28077 | return 5; |
| 28078 | } |
| 28079 | break; |
| 28080 | } |
| 28081 | case AArch64::AND_ZI: |
| 28082 | case AArch64::EOR_ZI: |
| 28083 | case AArch64::ORR_ZI: { |
| 28084 | switch (OpNum) { |
| 28085 | case 0: |
| 28086 | // op: Zdn |
| 28087 | return 0; |
| 28088 | case 2: |
| 28089 | // op: imms13 |
| 28090 | return 5; |
| 28091 | } |
| 28092 | break; |
| 28093 | } |
| 28094 | case AArch64::DECD_ZPiI: |
| 28095 | case AArch64::DECH_ZPiI: |
| 28096 | case AArch64::DECW_ZPiI: |
| 28097 | case AArch64::INCD_ZPiI: |
| 28098 | case AArch64::INCH_ZPiI: |
| 28099 | case AArch64::INCW_ZPiI: |
| 28100 | case AArch64::SQDECD_ZPiI: |
| 28101 | case AArch64::SQDECH_ZPiI: |
| 28102 | case AArch64::SQDECW_ZPiI: |
| 28103 | case AArch64::SQINCD_ZPiI: |
| 28104 | case AArch64::SQINCH_ZPiI: |
| 28105 | case AArch64::SQINCW_ZPiI: |
| 28106 | case AArch64::UQDECD_ZPiI: |
| 28107 | case AArch64::UQDECH_ZPiI: |
| 28108 | case AArch64::UQDECW_ZPiI: |
| 28109 | case AArch64::UQINCD_ZPiI: |
| 28110 | case AArch64::UQINCH_ZPiI: |
| 28111 | case AArch64::UQINCW_ZPiI: { |
| 28112 | switch (OpNum) { |
| 28113 | case 0: |
| 28114 | // op: Zdn |
| 28115 | return 0; |
| 28116 | case 2: |
| 28117 | // op: pattern |
| 28118 | return 5; |
| 28119 | case 3: |
| 28120 | // op: imm4 |
| 28121 | return 16; |
| 28122 | } |
| 28123 | break; |
| 28124 | } |
| 28125 | case AArch64::BCAX_ZZZZ: |
| 28126 | case AArch64::BSL1N_ZZZZ: |
| 28127 | case AArch64::BSL2N_ZZZZ: |
| 28128 | case AArch64::BSL_ZZZZ: |
| 28129 | case AArch64::EOR3_ZZZZ: |
| 28130 | case AArch64::NBSL_ZZZZ: { |
| 28131 | switch (OpNum) { |
| 28132 | case 0: |
| 28133 | // op: Zdn |
| 28134 | return 0; |
| 28135 | case 3: |
| 28136 | // op: Zk |
| 28137 | return 5; |
| 28138 | case 2: |
| 28139 | // op: Zm |
| 28140 | return 16; |
| 28141 | } |
| 28142 | break; |
| 28143 | } |
| 28144 | case AArch64::FCADD_ZPmZ_D: |
| 28145 | case AArch64::FCADD_ZPmZ_H: |
| 28146 | case AArch64::FCADD_ZPmZ_S: { |
| 28147 | switch (OpNum) { |
| 28148 | case 0: |
| 28149 | // op: Zdn |
| 28150 | return 0; |
| 28151 | case 3: |
| 28152 | // op: Zm |
| 28153 | return 5; |
| 28154 | case 1: |
| 28155 | // op: Pg |
| 28156 | return 10; |
| 28157 | case 4: |
| 28158 | // op: imm |
| 28159 | return 16; |
| 28160 | } |
| 28161 | break; |
| 28162 | } |
| 28163 | case AArch64::AESIMC_ZZ_B: |
| 28164 | case AArch64::AESMC_ZZ_B: { |
| 28165 | switch (OpNum) { |
| 28166 | case 0: |
| 28167 | // op: Zdn |
| 28168 | return 0; |
| 28169 | } |
| 28170 | break; |
| 28171 | } |
| 28172 | case AArch64::LD1RO_B: |
| 28173 | case AArch64::LD1RO_D: |
| 28174 | case AArch64::LD1RO_H: |
| 28175 | case AArch64::LD1RO_W: |
| 28176 | case AArch64::LD1RQ_B: |
| 28177 | case AArch64::LD1RQ_D: |
| 28178 | case AArch64::LD1RQ_H: |
| 28179 | case AArch64::LD1RQ_W: { |
| 28180 | switch (OpNum) { |
| 28181 | case 0: |
| 28182 | // op: Zt |
| 28183 | return 0; |
| 28184 | case 1: |
| 28185 | // op: Pg |
| 28186 | return 10; |
| 28187 | case 2: |
| 28188 | // op: Rn |
| 28189 | return 5; |
| 28190 | case 3: |
| 28191 | // op: Rm |
| 28192 | return 16; |
| 28193 | } |
| 28194 | break; |
| 28195 | } |
| 28196 | case AArch64::LD2B_IMM: |
| 28197 | case AArch64::LD2D_IMM: |
| 28198 | case AArch64::LD2H_IMM: |
| 28199 | case AArch64::LD2Q_IMM: |
| 28200 | case AArch64::LD2W_IMM: |
| 28201 | case AArch64::LD3B_IMM: |
| 28202 | case AArch64::LD3D_IMM: |
| 28203 | case AArch64::LD3H_IMM: |
| 28204 | case AArch64::LD3Q_IMM: |
| 28205 | case AArch64::LD3W_IMM: |
| 28206 | case AArch64::LD4B_IMM: |
| 28207 | case AArch64::LD4D_IMM: |
| 28208 | case AArch64::LD4H_IMM: |
| 28209 | case AArch64::LD4Q_IMM: |
| 28210 | case AArch64::LD4W_IMM: |
| 28211 | case AArch64::LDNT1B_ZRI: |
| 28212 | case AArch64::LDNT1D_ZRI: |
| 28213 | case AArch64::LDNT1H_ZRI: |
| 28214 | case AArch64::LDNT1W_ZRI: { |
| 28215 | switch (OpNum) { |
| 28216 | case 0: |
| 28217 | // op: Zt |
| 28218 | return 0; |
| 28219 | case 1: |
| 28220 | // op: Pg |
| 28221 | return 10; |
| 28222 | case 2: |
| 28223 | // op: Rn |
| 28224 | return 5; |
| 28225 | case 3: |
| 28226 | // op: imm4 |
| 28227 | return 16; |
| 28228 | } |
| 28229 | break; |
| 28230 | } |
| 28231 | case AArch64::LD1B: |
| 28232 | case AArch64::LD1B_D: |
| 28233 | case AArch64::LD1B_H: |
| 28234 | case AArch64::LD1B_S: |
| 28235 | case AArch64::LD1D: |
| 28236 | case AArch64::LD1H: |
| 28237 | case AArch64::LD1H_D: |
| 28238 | case AArch64::LD1H_S: |
| 28239 | case AArch64::LD1SB_D: |
| 28240 | case AArch64::LD1SB_H: |
| 28241 | case AArch64::LD1SB_S: |
| 28242 | case AArch64::LD1SH_D: |
| 28243 | case AArch64::LD1SH_S: |
| 28244 | case AArch64::LD1SW_D: |
| 28245 | case AArch64::LD1W: |
| 28246 | case AArch64::LD1W_D: |
| 28247 | case AArch64::LDFF1B: |
| 28248 | case AArch64::LDFF1B_D: |
| 28249 | case AArch64::LDFF1B_H: |
| 28250 | case AArch64::LDFF1B_S: |
| 28251 | case AArch64::LDFF1D: |
| 28252 | case AArch64::LDFF1H: |
| 28253 | case AArch64::LDFF1H_D: |
| 28254 | case AArch64::LDFF1H_S: |
| 28255 | case AArch64::LDFF1SB_D: |
| 28256 | case AArch64::LDFF1SB_H: |
| 28257 | case AArch64::LDFF1SB_S: |
| 28258 | case AArch64::LDFF1SH_D: |
| 28259 | case AArch64::LDFF1SH_S: |
| 28260 | case AArch64::LDFF1SW_D: |
| 28261 | case AArch64::LDFF1W: |
| 28262 | case AArch64::LDFF1W_D: { |
| 28263 | switch (OpNum) { |
| 28264 | case 0: |
| 28265 | // op: Zt |
| 28266 | return 0; |
| 28267 | case 1: |
| 28268 | // op: Pg |
| 28269 | return 10; |
| 28270 | case 3: |
| 28271 | // op: Rm |
| 28272 | return 16; |
| 28273 | case 2: |
| 28274 | // op: Rn |
| 28275 | return 5; |
| 28276 | } |
| 28277 | break; |
| 28278 | } |
| 28279 | case AArch64::LD1D_Q: |
| 28280 | case AArch64::LD1W_Q: |
| 28281 | case AArch64::ST2Q: |
| 28282 | case AArch64::ST3Q: |
| 28283 | case AArch64::ST4Q: { |
| 28284 | switch (OpNum) { |
| 28285 | case 0: |
| 28286 | // op: Zt |
| 28287 | return 0; |
| 28288 | case 2: |
| 28289 | // op: Rn |
| 28290 | return 5; |
| 28291 | case 1: |
| 28292 | // op: Pg |
| 28293 | return 10; |
| 28294 | case 3: |
| 28295 | // op: Rm |
| 28296 | return 16; |
| 28297 | } |
| 28298 | break; |
| 28299 | } |
| 28300 | case AArch64::LD1D_Q_IMM: |
| 28301 | case AArch64::LD1RO_B_IMM: |
| 28302 | case AArch64::LD1RO_D_IMM: |
| 28303 | case AArch64::LD1RO_H_IMM: |
| 28304 | case AArch64::LD1RO_W_IMM: |
| 28305 | case AArch64::LD1RQ_B_IMM: |
| 28306 | case AArch64::LD1RQ_D_IMM: |
| 28307 | case AArch64::LD1RQ_H_IMM: |
| 28308 | case AArch64::LD1RQ_W_IMM: |
| 28309 | case AArch64::LD1W_Q_IMM: |
| 28310 | case AArch64::ST2Q_IMM: |
| 28311 | case AArch64::ST3Q_IMM: |
| 28312 | case AArch64::ST4Q_IMM: { |
| 28313 | switch (OpNum) { |
| 28314 | case 0: |
| 28315 | // op: Zt |
| 28316 | return 0; |
| 28317 | case 2: |
| 28318 | // op: Rn |
| 28319 | return 5; |
| 28320 | case 1: |
| 28321 | // op: Pg |
| 28322 | return 10; |
| 28323 | case 3: |
| 28324 | // op: imm4 |
| 28325 | return 16; |
| 28326 | } |
| 28327 | break; |
| 28328 | } |
| 28329 | case AArch64::GLD1Q: |
| 28330 | case AArch64::SST1Q: { |
| 28331 | switch (OpNum) { |
| 28332 | case 0: |
| 28333 | // op: Zt |
| 28334 | return 0; |
| 28335 | case 2: |
| 28336 | // op: Zn |
| 28337 | return 5; |
| 28338 | case 1: |
| 28339 | // op: Pg |
| 28340 | return 10; |
| 28341 | case 3: |
| 28342 | // op: Rm |
| 28343 | return 16; |
| 28344 | } |
| 28345 | break; |
| 28346 | } |
| 28347 | case AArch64::LD1B_2Z_IMM: |
| 28348 | case AArch64::LD1D_2Z_IMM: |
| 28349 | case AArch64::LD1H_2Z_IMM: |
| 28350 | case AArch64::LD1W_2Z_IMM: |
| 28351 | case AArch64::LDNT1B_2Z_IMM: |
| 28352 | case AArch64::LDNT1D_2Z_IMM: |
| 28353 | case AArch64::LDNT1H_2Z_IMM: |
| 28354 | case AArch64::LDNT1W_2Z_IMM: |
| 28355 | case AArch64::ST1B_2Z_IMM: |
| 28356 | case AArch64::ST1D_2Z_IMM: |
| 28357 | case AArch64::ST1H_2Z_IMM: |
| 28358 | case AArch64::ST1W_2Z_IMM: |
| 28359 | case AArch64::STNT1B_2Z_IMM: |
| 28360 | case AArch64::STNT1D_2Z_IMM: |
| 28361 | case AArch64::STNT1H_2Z_IMM: |
| 28362 | case AArch64::STNT1W_2Z_IMM: { |
| 28363 | switch (OpNum) { |
| 28364 | case 0: |
| 28365 | // op: Zt |
| 28366 | return 1; |
| 28367 | case 2: |
| 28368 | // op: Rn |
| 28369 | return 5; |
| 28370 | case 1: |
| 28371 | // op: PNg |
| 28372 | return 10; |
| 28373 | case 3: |
| 28374 | // op: imm4 |
| 28375 | return 16; |
| 28376 | } |
| 28377 | break; |
| 28378 | } |
| 28379 | case AArch64::LD1B_2Z: |
| 28380 | case AArch64::LD1D_2Z: |
| 28381 | case AArch64::LD1H_2Z: |
| 28382 | case AArch64::LD1W_2Z: |
| 28383 | case AArch64::LDNT1B_2Z: |
| 28384 | case AArch64::LDNT1D_2Z: |
| 28385 | case AArch64::LDNT1H_2Z: |
| 28386 | case AArch64::LDNT1W_2Z: |
| 28387 | case AArch64::ST1B_2Z: |
| 28388 | case AArch64::ST1D_2Z: |
| 28389 | case AArch64::ST1H_2Z: |
| 28390 | case AArch64::ST1W_2Z: |
| 28391 | case AArch64::STNT1B_2Z: |
| 28392 | case AArch64::STNT1D_2Z: |
| 28393 | case AArch64::STNT1H_2Z: |
| 28394 | case AArch64::STNT1W_2Z: { |
| 28395 | switch (OpNum) { |
| 28396 | case 0: |
| 28397 | // op: Zt |
| 28398 | return 1; |
| 28399 | case 3: |
| 28400 | // op: Rm |
| 28401 | return 16; |
| 28402 | case 2: |
| 28403 | // op: Rn |
| 28404 | return 5; |
| 28405 | case 1: |
| 28406 | // op: PNg |
| 28407 | return 10; |
| 28408 | } |
| 28409 | break; |
| 28410 | } |
| 28411 | case AArch64::LD1B_4Z_IMM: |
| 28412 | case AArch64::LD1D_4Z_IMM: |
| 28413 | case AArch64::LD1H_4Z_IMM: |
| 28414 | case AArch64::LD1W_4Z_IMM: |
| 28415 | case AArch64::LDNT1B_4Z_IMM: |
| 28416 | case AArch64::LDNT1D_4Z_IMM: |
| 28417 | case AArch64::LDNT1H_4Z_IMM: |
| 28418 | case AArch64::LDNT1W_4Z_IMM: |
| 28419 | case AArch64::ST1B_4Z_IMM: |
| 28420 | case AArch64::ST1D_4Z_IMM: |
| 28421 | case AArch64::ST1H_4Z_IMM: |
| 28422 | case AArch64::ST1W_4Z_IMM: |
| 28423 | case AArch64::STNT1B_4Z_IMM: |
| 28424 | case AArch64::STNT1D_4Z_IMM: |
| 28425 | case AArch64::STNT1H_4Z_IMM: |
| 28426 | case AArch64::STNT1W_4Z_IMM: { |
| 28427 | switch (OpNum) { |
| 28428 | case 0: |
| 28429 | // op: Zt |
| 28430 | return 2; |
| 28431 | case 2: |
| 28432 | // op: Rn |
| 28433 | return 5; |
| 28434 | case 1: |
| 28435 | // op: PNg |
| 28436 | return 10; |
| 28437 | case 3: |
| 28438 | // op: imm4 |
| 28439 | return 16; |
| 28440 | } |
| 28441 | break; |
| 28442 | } |
| 28443 | case AArch64::LD1B_4Z: |
| 28444 | case AArch64::LD1D_4Z: |
| 28445 | case AArch64::LD1H_4Z: |
| 28446 | case AArch64::LD1W_4Z: |
| 28447 | case AArch64::LDNT1B_4Z: |
| 28448 | case AArch64::LDNT1D_4Z: |
| 28449 | case AArch64::LDNT1H_4Z: |
| 28450 | case AArch64::LDNT1W_4Z: |
| 28451 | case AArch64::ST1B_4Z: |
| 28452 | case AArch64::ST1D_4Z: |
| 28453 | case AArch64::ST1H_4Z: |
| 28454 | case AArch64::ST1W_4Z: |
| 28455 | case AArch64::STNT1B_4Z: |
| 28456 | case AArch64::STNT1D_4Z: |
| 28457 | case AArch64::STNT1H_4Z: |
| 28458 | case AArch64::STNT1W_4Z: { |
| 28459 | switch (OpNum) { |
| 28460 | case 0: |
| 28461 | // op: Zt |
| 28462 | return 2; |
| 28463 | case 3: |
| 28464 | // op: Rm |
| 28465 | return 16; |
| 28466 | case 2: |
| 28467 | // op: Rn |
| 28468 | return 5; |
| 28469 | case 1: |
| 28470 | // op: PNg |
| 28471 | return 10; |
| 28472 | } |
| 28473 | break; |
| 28474 | } |
| 28475 | case AArch64::B: |
| 28476 | case AArch64::BL: { |
| 28477 | switch (OpNum) { |
| 28478 | case 0: |
| 28479 | // op: addr |
| 28480 | return 0; |
| 28481 | } |
| 28482 | break; |
| 28483 | } |
| 28484 | case AArch64::FLTcc: { |
| 28485 | switch (OpNum) { |
| 28486 | case 0: |
| 28487 | // op: cond |
| 28488 | return 0; |
| 28489 | case 1: |
| 28490 | // op: imm |
| 28491 | return 5; |
| 28492 | } |
| 28493 | break; |
| 28494 | } |
| 28495 | case AArch64::BCcc: |
| 28496 | case AArch64::Bcc: { |
| 28497 | switch (OpNum) { |
| 28498 | case 0: |
| 28499 | // op: cond |
| 28500 | return 0; |
| 28501 | case 1: |
| 28502 | // op: target |
| 28503 | return 5; |
| 28504 | } |
| 28505 | break; |
| 28506 | } |
| 28507 | case AArch64::DUPi8: { |
| 28508 | switch (OpNum) { |
| 28509 | case 0: |
| 28510 | // op: dst |
| 28511 | return 0; |
| 28512 | case 1: |
| 28513 | // op: src |
| 28514 | return 5; |
| 28515 | case 2: |
| 28516 | // op: idx |
| 28517 | return 17; |
| 28518 | } |
| 28519 | break; |
| 28520 | } |
| 28521 | case AArch64::DUPi16: { |
| 28522 | switch (OpNum) { |
| 28523 | case 0: |
| 28524 | // op: dst |
| 28525 | return 0; |
| 28526 | case 1: |
| 28527 | // op: src |
| 28528 | return 5; |
| 28529 | case 2: |
| 28530 | // op: idx |
| 28531 | return 18; |
| 28532 | } |
| 28533 | break; |
| 28534 | } |
| 28535 | case AArch64::DUPi32: { |
| 28536 | switch (OpNum) { |
| 28537 | case 0: |
| 28538 | // op: dst |
| 28539 | return 0; |
| 28540 | case 1: |
| 28541 | // op: src |
| 28542 | return 5; |
| 28543 | case 2: |
| 28544 | // op: idx |
| 28545 | return 19; |
| 28546 | } |
| 28547 | break; |
| 28548 | } |
| 28549 | case AArch64::DUPi64: { |
| 28550 | switch (OpNum) { |
| 28551 | case 0: |
| 28552 | // op: dst |
| 28553 | return 0; |
| 28554 | case 1: |
| 28555 | // op: src |
| 28556 | return 5; |
| 28557 | case 2: |
| 28558 | // op: idx |
| 28559 | return 20; |
| 28560 | } |
| 28561 | break; |
| 28562 | } |
| 28563 | case AArch64::UDF: |
| 28564 | case AArch64::ZERO_M: { |
| 28565 | switch (OpNum) { |
| 28566 | case 0: |
| 28567 | // op: imm |
| 28568 | return 0; |
| 28569 | } |
| 28570 | break; |
| 28571 | } |
| 28572 | case AArch64::TENTER: { |
| 28573 | switch (OpNum) { |
| 28574 | case 0: |
| 28575 | // op: imm |
| 28576 | return 5; |
| 28577 | case 1: |
| 28578 | // op: nb |
| 28579 | return 17; |
| 28580 | } |
| 28581 | break; |
| 28582 | } |
| 28583 | case AArch64::BRK: |
| 28584 | case AArch64::DCPS1: |
| 28585 | case AArch64::DCPS2: |
| 28586 | case AArch64::DCPS3: |
| 28587 | case AArch64::HINT: |
| 28588 | case AArch64::HLT: |
| 28589 | case AArch64::HVC: |
| 28590 | case AArch64::SMC: |
| 28591 | case AArch64::SVC: { |
| 28592 | switch (OpNum) { |
| 28593 | case 0: |
| 28594 | // op: imm |
| 28595 | return 5; |
| 28596 | } |
| 28597 | break; |
| 28598 | } |
| 28599 | case AArch64::HINTE: { |
| 28600 | switch (OpNum) { |
| 28601 | case 0: |
| 28602 | // op: imm16 |
| 28603 | return 0; |
| 28604 | } |
| 28605 | break; |
| 28606 | } |
| 28607 | case AArch64::AUTIASPPCi: |
| 28608 | case AArch64::AUTIBSPPCi: |
| 28609 | case AArch64::RETAASPPCi: |
| 28610 | case AArch64::RETABSPPCi: { |
| 28611 | switch (OpNum) { |
| 28612 | case 0: |
| 28613 | // op: label |
| 28614 | return 5; |
| 28615 | } |
| 28616 | break; |
| 28617 | } |
| 28618 | case AArch64::TEXIT: { |
| 28619 | switch (OpNum) { |
| 28620 | case 0: |
| 28621 | // op: nb |
| 28622 | return 10; |
| 28623 | } |
| 28624 | break; |
| 28625 | } |
| 28626 | case AArch64::SYSPxt_XZR: { |
| 28627 | switch (OpNum) { |
| 28628 | case 0: |
| 28629 | // op: op1 |
| 28630 | return 16; |
| 28631 | case 1: |
| 28632 | // op: Cn |
| 28633 | return 12; |
| 28634 | case 2: |
| 28635 | // op: Cm |
| 28636 | return 8; |
| 28637 | case 3: |
| 28638 | // op: op2 |
| 28639 | return 5; |
| 28640 | } |
| 28641 | break; |
| 28642 | } |
| 28643 | case AArch64::MSRpstateImm1: |
| 28644 | case AArch64::MSRpstateImm4: { |
| 28645 | switch (OpNum) { |
| 28646 | case 0: |
| 28647 | // op: pstatefield |
| 28648 | return 5; |
| 28649 | case 1: |
| 28650 | // op: imm |
| 28651 | return 8; |
| 28652 | } |
| 28653 | break; |
| 28654 | } |
| 28655 | case AArch64::MSRpstatesvcrImm1: { |
| 28656 | switch (OpNum) { |
| 28657 | case 0: |
| 28658 | // op: pstatefield |
| 28659 | return 9; |
| 28660 | case 1: |
| 28661 | // op: imm |
| 28662 | return 8; |
| 28663 | } |
| 28664 | break; |
| 28665 | } |
| 28666 | case AArch64::CFLTEQWr: |
| 28667 | case AArch64::CFLTEQXr: |
| 28668 | case AArch64::CFLTGEWr: |
| 28669 | case AArch64::CFLTGEXr: |
| 28670 | case AArch64::CFLTGTWr: |
| 28671 | case AArch64::CFLTGTXr: |
| 28672 | case AArch64::CFLTHIWr: |
| 28673 | case AArch64::CFLTHIXr: |
| 28674 | case AArch64::CFLTHSWr: |
| 28675 | case AArch64::CFLTHSXr: |
| 28676 | case AArch64::CFLTNEWr: |
| 28677 | case AArch64::CFLTNEXr: { |
| 28678 | switch (OpNum) { |
| 28679 | case 0: |
| 28680 | // op: reason |
| 28681 | return 10; |
| 28682 | case 1: |
| 28683 | // op: Rt |
| 28684 | return 0; |
| 28685 | case 2: |
| 28686 | // op: Rm |
| 28687 | return 16; |
| 28688 | } |
| 28689 | break; |
| 28690 | } |
| 28691 | case AArch64::TFLTNZ: |
| 28692 | case AArch64::TFLTZ: { |
| 28693 | switch (OpNum) { |
| 28694 | case 0: |
| 28695 | // op: reason |
| 28696 | return 10; |
| 28697 | case 1: |
| 28698 | // op: Rt |
| 28699 | return 0; |
| 28700 | case 2: |
| 28701 | // op: bit_off |
| 28702 | return 19; |
| 28703 | } |
| 28704 | break; |
| 28705 | } |
| 28706 | case AArch64::CFLTEQWi: |
| 28707 | case AArch64::CFLTEQXi: |
| 28708 | case AArch64::CFLTGTWi: |
| 28709 | case AArch64::CFLTGTXi: |
| 28710 | case AArch64::CFLTHIWi: |
| 28711 | case AArch64::CFLTHIXi: |
| 28712 | case AArch64::CFLTLOWi: |
| 28713 | case AArch64::CFLTLOXi: |
| 28714 | case AArch64::CFLTLTWi: |
| 28715 | case AArch64::CFLTLTXi: |
| 28716 | case AArch64::CFLTNEWi: |
| 28717 | case AArch64::CFLTNEXi: { |
| 28718 | switch (OpNum) { |
| 28719 | case 0: |
| 28720 | // op: reason |
| 28721 | return 10; |
| 28722 | case 1: |
| 28723 | // op: Rt |
| 28724 | return 0; |
| 28725 | case 2: |
| 28726 | // op: imm |
| 28727 | return 5; |
| 28728 | } |
| 28729 | break; |
| 28730 | } |
| 28731 | case AArch64::SEL_VG2_2ZC2Z2Z_B: |
| 28732 | case AArch64::SEL_VG2_2ZC2Z2Z_D: |
| 28733 | case AArch64::SEL_VG2_2ZC2Z2Z_H: |
| 28734 | case AArch64::SEL_VG2_2ZC2Z2Z_S: { |
| 28735 | switch (OpNum) { |
| 28736 | case 1: |
| 28737 | // op: PNg |
| 28738 | return 10; |
| 28739 | case 3: |
| 28740 | // op: Zm |
| 28741 | return 17; |
| 28742 | case 2: |
| 28743 | // op: Zn |
| 28744 | return 6; |
| 28745 | case 0: |
| 28746 | // op: Zd |
| 28747 | return 1; |
| 28748 | } |
| 28749 | break; |
| 28750 | } |
| 28751 | case AArch64::SEL_VG4_4ZC4Z4Z_B: |
| 28752 | case AArch64::SEL_VG4_4ZC4Z4Z_D: |
| 28753 | case AArch64::SEL_VG4_4ZC4Z4Z_H: |
| 28754 | case AArch64::SEL_VG4_4ZC4Z4Z_S: { |
| 28755 | switch (OpNum) { |
| 28756 | case 1: |
| 28757 | // op: PNg |
| 28758 | return 10; |
| 28759 | case 3: |
| 28760 | // op: Zm |
| 28761 | return 18; |
| 28762 | case 2: |
| 28763 | // op: Zn |
| 28764 | return 7; |
| 28765 | case 0: |
| 28766 | // op: Zd |
| 28767 | return 2; |
| 28768 | } |
| 28769 | break; |
| 28770 | } |
| 28771 | case AArch64::LASTA_RPZ_B: |
| 28772 | case AArch64::LASTA_RPZ_D: |
| 28773 | case AArch64::LASTA_RPZ_H: |
| 28774 | case AArch64::LASTA_RPZ_S: |
| 28775 | case AArch64::LASTB_RPZ_B: |
| 28776 | case AArch64::LASTB_RPZ_D: |
| 28777 | case AArch64::LASTB_RPZ_H: |
| 28778 | case AArch64::LASTB_RPZ_S: { |
| 28779 | switch (OpNum) { |
| 28780 | case 1: |
| 28781 | // op: Pg |
| 28782 | return 10; |
| 28783 | case 0: |
| 28784 | // op: Rd |
| 28785 | return 0; |
| 28786 | case 2: |
| 28787 | // op: Zn |
| 28788 | return 5; |
| 28789 | } |
| 28790 | break; |
| 28791 | } |
| 28792 | case AArch64::CLASTA_RPZ_B: |
| 28793 | case AArch64::CLASTA_RPZ_D: |
| 28794 | case AArch64::CLASTA_RPZ_H: |
| 28795 | case AArch64::CLASTA_RPZ_S: |
| 28796 | case AArch64::CLASTB_RPZ_B: |
| 28797 | case AArch64::CLASTB_RPZ_D: |
| 28798 | case AArch64::CLASTB_RPZ_H: |
| 28799 | case AArch64::CLASTB_RPZ_S: { |
| 28800 | switch (OpNum) { |
| 28801 | case 1: |
| 28802 | // op: Pg |
| 28803 | return 10; |
| 28804 | case 0: |
| 28805 | // op: Rdn |
| 28806 | return 0; |
| 28807 | case 3: |
| 28808 | // op: Zm |
| 28809 | return 5; |
| 28810 | } |
| 28811 | break; |
| 28812 | } |
| 28813 | case AArch64::ANDV_VPZ_B: |
| 28814 | case AArch64::ANDV_VPZ_D: |
| 28815 | case AArch64::ANDV_VPZ_H: |
| 28816 | case AArch64::ANDV_VPZ_S: |
| 28817 | case AArch64::EORV_VPZ_B: |
| 28818 | case AArch64::EORV_VPZ_D: |
| 28819 | case AArch64::EORV_VPZ_H: |
| 28820 | case AArch64::EORV_VPZ_S: |
| 28821 | case AArch64::LASTA_VPZ_B: |
| 28822 | case AArch64::LASTA_VPZ_D: |
| 28823 | case AArch64::LASTA_VPZ_H: |
| 28824 | case AArch64::LASTA_VPZ_S: |
| 28825 | case AArch64::LASTB_VPZ_B: |
| 28826 | case AArch64::LASTB_VPZ_D: |
| 28827 | case AArch64::LASTB_VPZ_H: |
| 28828 | case AArch64::LASTB_VPZ_S: |
| 28829 | case AArch64::ORV_VPZ_B: |
| 28830 | case AArch64::ORV_VPZ_D: |
| 28831 | case AArch64::ORV_VPZ_H: |
| 28832 | case AArch64::ORV_VPZ_S: |
| 28833 | case AArch64::SADDV_VPZ_B: |
| 28834 | case AArch64::SADDV_VPZ_H: |
| 28835 | case AArch64::SADDV_VPZ_S: |
| 28836 | case AArch64::SMAXV_VPZ_B: |
| 28837 | case AArch64::SMAXV_VPZ_D: |
| 28838 | case AArch64::SMAXV_VPZ_H: |
| 28839 | case AArch64::SMAXV_VPZ_S: |
| 28840 | case AArch64::SMINV_VPZ_B: |
| 28841 | case AArch64::SMINV_VPZ_D: |
| 28842 | case AArch64::SMINV_VPZ_H: |
| 28843 | case AArch64::SMINV_VPZ_S: |
| 28844 | case AArch64::UADDV_VPZ_B: |
| 28845 | case AArch64::UADDV_VPZ_D: |
| 28846 | case AArch64::UADDV_VPZ_H: |
| 28847 | case AArch64::UADDV_VPZ_S: |
| 28848 | case AArch64::UMAXV_VPZ_B: |
| 28849 | case AArch64::UMAXV_VPZ_D: |
| 28850 | case AArch64::UMAXV_VPZ_H: |
| 28851 | case AArch64::UMAXV_VPZ_S: |
| 28852 | case AArch64::UMINV_VPZ_B: |
| 28853 | case AArch64::UMINV_VPZ_D: |
| 28854 | case AArch64::UMINV_VPZ_H: |
| 28855 | case AArch64::UMINV_VPZ_S: { |
| 28856 | switch (OpNum) { |
| 28857 | case 1: |
| 28858 | // op: Pg |
| 28859 | return 10; |
| 28860 | case 0: |
| 28861 | // op: Vd |
| 28862 | return 0; |
| 28863 | case 2: |
| 28864 | // op: Zn |
| 28865 | return 5; |
| 28866 | } |
| 28867 | break; |
| 28868 | } |
| 28869 | case AArch64::CLASTA_VPZ_B: |
| 28870 | case AArch64::CLASTA_VPZ_D: |
| 28871 | case AArch64::CLASTA_VPZ_H: |
| 28872 | case AArch64::CLASTA_VPZ_S: |
| 28873 | case AArch64::CLASTB_VPZ_B: |
| 28874 | case AArch64::CLASTB_VPZ_D: |
| 28875 | case AArch64::CLASTB_VPZ_H: |
| 28876 | case AArch64::CLASTB_VPZ_S: |
| 28877 | case AArch64::FADDA_VPZ_D: |
| 28878 | case AArch64::FADDA_VPZ_H: |
| 28879 | case AArch64::FADDA_VPZ_S: { |
| 28880 | switch (OpNum) { |
| 28881 | case 1: |
| 28882 | // op: Pg |
| 28883 | return 10; |
| 28884 | case 0: |
| 28885 | // op: Vdn |
| 28886 | return 0; |
| 28887 | case 3: |
| 28888 | // op: Zm |
| 28889 | return 5; |
| 28890 | } |
| 28891 | break; |
| 28892 | } |
| 28893 | case AArch64::ABS_ZPzZ_B: |
| 28894 | case AArch64::ABS_ZPzZ_D: |
| 28895 | case AArch64::ABS_ZPzZ_H: |
| 28896 | case AArch64::ABS_ZPzZ_S: |
| 28897 | case AArch64::BFCVT_ZPzZ_StoH: |
| 28898 | case AArch64::CLS_ZPzZ_B: |
| 28899 | case AArch64::CLS_ZPzZ_D: |
| 28900 | case AArch64::CLS_ZPzZ_H: |
| 28901 | case AArch64::CLS_ZPzZ_S: |
| 28902 | case AArch64::CLZ_ZPzZ_B: |
| 28903 | case AArch64::CLZ_ZPzZ_D: |
| 28904 | case AArch64::CLZ_ZPzZ_H: |
| 28905 | case AArch64::CLZ_ZPzZ_S: |
| 28906 | case AArch64::CNOT_ZPzZ_B: |
| 28907 | case AArch64::CNOT_ZPzZ_D: |
| 28908 | case AArch64::CNOT_ZPzZ_H: |
| 28909 | case AArch64::CNOT_ZPzZ_S: |
| 28910 | case AArch64::CNT_ZPzZ_B: |
| 28911 | case AArch64::CNT_ZPzZ_D: |
| 28912 | case AArch64::CNT_ZPzZ_H: |
| 28913 | case AArch64::CNT_ZPzZ_S: |
| 28914 | case AArch64::COMPACT_ZPZ_B: |
| 28915 | case AArch64::COMPACT_ZPZ_D: |
| 28916 | case AArch64::COMPACT_ZPZ_H: |
| 28917 | case AArch64::COMPACT_ZPZ_S: |
| 28918 | case AArch64::FABS_ZPzZ_D: |
| 28919 | case AArch64::FABS_ZPzZ_H: |
| 28920 | case AArch64::FABS_ZPzZ_S: |
| 28921 | case AArch64::FCVTX_ZPzZ_DtoS: |
| 28922 | case AArch64::FCVTZS_ZPzZ_DtoD: |
| 28923 | case AArch64::FCVTZS_ZPzZ_DtoS: |
| 28924 | case AArch64::FCVTZS_ZPzZ_HtoD: |
| 28925 | case AArch64::FCVTZS_ZPzZ_HtoH: |
| 28926 | case AArch64::FCVTZS_ZPzZ_HtoS: |
| 28927 | case AArch64::FCVTZS_ZPzZ_StoD: |
| 28928 | case AArch64::FCVTZS_ZPzZ_StoS: |
| 28929 | case AArch64::FCVTZU_ZPzZ_DtoD: |
| 28930 | case AArch64::FCVTZU_ZPzZ_DtoS: |
| 28931 | case AArch64::FCVTZU_ZPzZ_HtoD: |
| 28932 | case AArch64::FCVTZU_ZPzZ_HtoH: |
| 28933 | case AArch64::FCVTZU_ZPzZ_HtoS: |
| 28934 | case AArch64::FCVTZU_ZPzZ_StoD: |
| 28935 | case AArch64::FCVTZU_ZPzZ_StoS: |
| 28936 | case AArch64::FCVT_ZPzZ_DtoH: |
| 28937 | case AArch64::FCVT_ZPzZ_DtoS: |
| 28938 | case AArch64::FCVT_ZPzZ_HtoD: |
| 28939 | case AArch64::FCVT_ZPzZ_HtoS: |
| 28940 | case AArch64::FCVT_ZPzZ_StoD: |
| 28941 | case AArch64::FCVT_ZPzZ_StoH: |
| 28942 | case AArch64::FLOGB_ZPzZ_D: |
| 28943 | case AArch64::FLOGB_ZPzZ_H: |
| 28944 | case AArch64::FLOGB_ZPzZ_S: |
| 28945 | case AArch64::FNEG_ZPzZ_D: |
| 28946 | case AArch64::FNEG_ZPzZ_H: |
| 28947 | case AArch64::FNEG_ZPzZ_S: |
| 28948 | case AArch64::FRECPX_ZPzZ_D: |
| 28949 | case AArch64::FRECPX_ZPzZ_H: |
| 28950 | case AArch64::FRECPX_ZPzZ_S: |
| 28951 | case AArch64::FRINT32X_ZPzZ_D: |
| 28952 | case AArch64::FRINT32X_ZPzZ_S: |
| 28953 | case AArch64::FRINT32Z_ZPzZ_D: |
| 28954 | case AArch64::FRINT32Z_ZPzZ_S: |
| 28955 | case AArch64::FRINT64X_ZPzZ_D: |
| 28956 | case AArch64::FRINT64X_ZPzZ_S: |
| 28957 | case AArch64::FRINT64Z_ZPzZ_D: |
| 28958 | case AArch64::FRINT64Z_ZPzZ_S: |
| 28959 | case AArch64::FRINTA_ZPzZ_D: |
| 28960 | case AArch64::FRINTA_ZPzZ_H: |
| 28961 | case AArch64::FRINTA_ZPzZ_S: |
| 28962 | case AArch64::FRINTI_ZPzZ_D: |
| 28963 | case AArch64::FRINTI_ZPzZ_H: |
| 28964 | case AArch64::FRINTI_ZPzZ_S: |
| 28965 | case AArch64::FRINTM_ZPzZ_D: |
| 28966 | case AArch64::FRINTM_ZPzZ_H: |
| 28967 | case AArch64::FRINTM_ZPzZ_S: |
| 28968 | case AArch64::FRINTN_ZPzZ_D: |
| 28969 | case AArch64::FRINTN_ZPzZ_H: |
| 28970 | case AArch64::FRINTN_ZPzZ_S: |
| 28971 | case AArch64::FRINTP_ZPzZ_D: |
| 28972 | case AArch64::FRINTP_ZPzZ_H: |
| 28973 | case AArch64::FRINTP_ZPzZ_S: |
| 28974 | case AArch64::FRINTX_ZPzZ_D: |
| 28975 | case AArch64::FRINTX_ZPzZ_H: |
| 28976 | case AArch64::FRINTX_ZPzZ_S: |
| 28977 | case AArch64::FRINTZ_ZPzZ_D: |
| 28978 | case AArch64::FRINTZ_ZPzZ_H: |
| 28979 | case AArch64::FRINTZ_ZPzZ_S: |
| 28980 | case AArch64::FSQRT_ZPZz_D: |
| 28981 | case AArch64::FSQRT_ZPZz_H: |
| 28982 | case AArch64::FSQRT_ZPZz_S: |
| 28983 | case AArch64::MOVPRFX_ZPzZ_B: |
| 28984 | case AArch64::MOVPRFX_ZPzZ_D: |
| 28985 | case AArch64::MOVPRFX_ZPzZ_H: |
| 28986 | case AArch64::MOVPRFX_ZPzZ_S: |
| 28987 | case AArch64::NEG_ZPzZ_B: |
| 28988 | case AArch64::NEG_ZPzZ_D: |
| 28989 | case AArch64::NEG_ZPzZ_H: |
| 28990 | case AArch64::NEG_ZPzZ_S: |
| 28991 | case AArch64::NOT_ZPzZ_B: |
| 28992 | case AArch64::NOT_ZPzZ_D: |
| 28993 | case AArch64::NOT_ZPzZ_H: |
| 28994 | case AArch64::NOT_ZPzZ_S: |
| 28995 | case AArch64::SCVTF_ZPzZ_DtoD: |
| 28996 | case AArch64::SCVTF_ZPzZ_DtoH: |
| 28997 | case AArch64::SCVTF_ZPzZ_DtoS: |
| 28998 | case AArch64::SCVTF_ZPzZ_HtoH: |
| 28999 | case AArch64::SCVTF_ZPzZ_StoD: |
| 29000 | case AArch64::SCVTF_ZPzZ_StoH: |
| 29001 | case AArch64::SCVTF_ZPzZ_StoS: |
| 29002 | case AArch64::SQABS_ZPzZ_B: |
| 29003 | case AArch64::SQABS_ZPzZ_D: |
| 29004 | case AArch64::SQABS_ZPzZ_H: |
| 29005 | case AArch64::SQABS_ZPzZ_S: |
| 29006 | case AArch64::SQNEG_ZPzZ_B: |
| 29007 | case AArch64::SQNEG_ZPzZ_D: |
| 29008 | case AArch64::SQNEG_ZPzZ_H: |
| 29009 | case AArch64::SQNEG_ZPzZ_S: |
| 29010 | case AArch64::SXTB_ZPzZ_D: |
| 29011 | case AArch64::SXTB_ZPzZ_H: |
| 29012 | case AArch64::SXTB_ZPzZ_S: |
| 29013 | case AArch64::SXTH_ZPzZ_D: |
| 29014 | case AArch64::SXTH_ZPzZ_S: |
| 29015 | case AArch64::SXTW_ZPzZ_D: |
| 29016 | case AArch64::UCVTF_ZPzZ_DtoD: |
| 29017 | case AArch64::UCVTF_ZPzZ_DtoH: |
| 29018 | case AArch64::UCVTF_ZPzZ_DtoS: |
| 29019 | case AArch64::UCVTF_ZPzZ_HtoH: |
| 29020 | case AArch64::UCVTF_ZPzZ_StoD: |
| 29021 | case AArch64::UCVTF_ZPzZ_StoH: |
| 29022 | case AArch64::UCVTF_ZPzZ_StoS: |
| 29023 | case AArch64::URECPE_ZPzZ_S: |
| 29024 | case AArch64::URSQRTE_ZPzZ_S: |
| 29025 | case AArch64::UXTB_ZPzZ_D: |
| 29026 | case AArch64::UXTB_ZPzZ_H: |
| 29027 | case AArch64::UXTB_ZPzZ_S: |
| 29028 | case AArch64::UXTH_ZPzZ_D: |
| 29029 | case AArch64::UXTH_ZPzZ_S: |
| 29030 | case AArch64::UXTW_ZPzZ_D: { |
| 29031 | switch (OpNum) { |
| 29032 | case 1: |
| 29033 | // op: Pg |
| 29034 | return 10; |
| 29035 | case 0: |
| 29036 | // op: Zd |
| 29037 | return 0; |
| 29038 | case 2: |
| 29039 | // op: Zn |
| 29040 | return 5; |
| 29041 | } |
| 29042 | break; |
| 29043 | } |
| 29044 | case AArch64::SEL_ZPZZ_B: |
| 29045 | case AArch64::SEL_ZPZZ_D: |
| 29046 | case AArch64::SEL_ZPZZ_H: |
| 29047 | case AArch64::SEL_ZPZZ_S: { |
| 29048 | switch (OpNum) { |
| 29049 | case 1: |
| 29050 | // op: Pg |
| 29051 | return 10; |
| 29052 | case 0: |
| 29053 | // op: Zd |
| 29054 | return 0; |
| 29055 | case 3: |
| 29056 | // op: Zm |
| 29057 | return 16; |
| 29058 | case 2: |
| 29059 | // op: Zn |
| 29060 | return 5; |
| 29061 | } |
| 29062 | break; |
| 29063 | } |
| 29064 | case AArch64::BFMLA_ZPmZZ: |
| 29065 | case AArch64::BFMLS_ZPmZZ: |
| 29066 | case AArch64::FMLA_ZPmZZ_D: |
| 29067 | case AArch64::FMLA_ZPmZZ_H: |
| 29068 | case AArch64::FMLA_ZPmZZ_S: |
| 29069 | case AArch64::FMLS_ZPmZZ_D: |
| 29070 | case AArch64::FMLS_ZPmZZ_H: |
| 29071 | case AArch64::FMLS_ZPmZZ_S: |
| 29072 | case AArch64::FNMLA_ZPmZZ_D: |
| 29073 | case AArch64::FNMLA_ZPmZZ_H: |
| 29074 | case AArch64::FNMLA_ZPmZZ_S: |
| 29075 | case AArch64::FNMLS_ZPmZZ_D: |
| 29076 | case AArch64::FNMLS_ZPmZZ_H: |
| 29077 | case AArch64::FNMLS_ZPmZZ_S: |
| 29078 | case AArch64::MLA_ZPmZZ_B: |
| 29079 | case AArch64::MLA_ZPmZZ_D: |
| 29080 | case AArch64::MLA_ZPmZZ_H: |
| 29081 | case AArch64::MLA_ZPmZZ_S: |
| 29082 | case AArch64::MLS_ZPmZZ_B: |
| 29083 | case AArch64::MLS_ZPmZZ_D: |
| 29084 | case AArch64::MLS_ZPmZZ_H: |
| 29085 | case AArch64::MLS_ZPmZZ_S: { |
| 29086 | switch (OpNum) { |
| 29087 | case 1: |
| 29088 | // op: Pg |
| 29089 | return 10; |
| 29090 | case 0: |
| 29091 | // op: Zda |
| 29092 | return 0; |
| 29093 | case 4: |
| 29094 | // op: Zm |
| 29095 | return 16; |
| 29096 | case 3: |
| 29097 | // op: Zn |
| 29098 | return 5; |
| 29099 | } |
| 29100 | break; |
| 29101 | } |
| 29102 | case AArch64::ADD_ZPmZ_B: |
| 29103 | case AArch64::ADD_ZPmZ_CPA: |
| 29104 | case AArch64::ADD_ZPmZ_D: |
| 29105 | case AArch64::ADD_ZPmZ_H: |
| 29106 | case AArch64::ADD_ZPmZ_S: |
| 29107 | case AArch64::AND_ZPmZ_B: |
| 29108 | case AArch64::AND_ZPmZ_D: |
| 29109 | case AArch64::AND_ZPmZ_H: |
| 29110 | case AArch64::AND_ZPmZ_S: |
| 29111 | case AArch64::ASRR_ZPmZ_B: |
| 29112 | case AArch64::ASRR_ZPmZ_D: |
| 29113 | case AArch64::ASRR_ZPmZ_H: |
| 29114 | case AArch64::ASRR_ZPmZ_S: |
| 29115 | case AArch64::ASR_WIDE_ZPmZ_B: |
| 29116 | case AArch64::ASR_WIDE_ZPmZ_H: |
| 29117 | case AArch64::ASR_WIDE_ZPmZ_S: |
| 29118 | case AArch64::ASR_ZPmZ_B: |
| 29119 | case AArch64::ASR_ZPmZ_D: |
| 29120 | case AArch64::ASR_ZPmZ_H: |
| 29121 | case AArch64::ASR_ZPmZ_S: |
| 29122 | case AArch64::BFADD_ZPmZ: |
| 29123 | case AArch64::BFMAXNM_ZPmZ: |
| 29124 | case AArch64::BFMAX_ZPmZ: |
| 29125 | case AArch64::BFMINNM_ZPmZ: |
| 29126 | case AArch64::BFMIN_ZPmZ: |
| 29127 | case AArch64::BFMUL_ZPmZ: |
| 29128 | case AArch64::BFSCALE_ZPmZ: |
| 29129 | case AArch64::BFSUB_ZPmZ: |
| 29130 | case AArch64::BIC_ZPmZ_B: |
| 29131 | case AArch64::BIC_ZPmZ_D: |
| 29132 | case AArch64::BIC_ZPmZ_H: |
| 29133 | case AArch64::BIC_ZPmZ_S: |
| 29134 | case AArch64::CLASTA_ZPZ_B: |
| 29135 | case AArch64::CLASTA_ZPZ_D: |
| 29136 | case AArch64::CLASTA_ZPZ_H: |
| 29137 | case AArch64::CLASTA_ZPZ_S: |
| 29138 | case AArch64::CLASTB_ZPZ_B: |
| 29139 | case AArch64::CLASTB_ZPZ_D: |
| 29140 | case AArch64::CLASTB_ZPZ_H: |
| 29141 | case AArch64::CLASTB_ZPZ_S: |
| 29142 | case AArch64::EOR_ZPmZ_B: |
| 29143 | case AArch64::EOR_ZPmZ_D: |
| 29144 | case AArch64::EOR_ZPmZ_H: |
| 29145 | case AArch64::EOR_ZPmZ_S: |
| 29146 | case AArch64::FABD_ZPmZ_D: |
| 29147 | case AArch64::FABD_ZPmZ_H: |
| 29148 | case AArch64::FABD_ZPmZ_S: |
| 29149 | case AArch64::FADD_ZPmZ_D: |
| 29150 | case AArch64::FADD_ZPmZ_H: |
| 29151 | case AArch64::FADD_ZPmZ_S: |
| 29152 | case AArch64::FAMAX_ZPmZ_D: |
| 29153 | case AArch64::FAMAX_ZPmZ_H: |
| 29154 | case AArch64::FAMAX_ZPmZ_S: |
| 29155 | case AArch64::FAMIN_ZPmZ_D: |
| 29156 | case AArch64::FAMIN_ZPmZ_H: |
| 29157 | case AArch64::FAMIN_ZPmZ_S: |
| 29158 | case AArch64::FDIVR_ZPmZ_D: |
| 29159 | case AArch64::FDIVR_ZPmZ_H: |
| 29160 | case AArch64::FDIVR_ZPmZ_S: |
| 29161 | case AArch64::FDIV_ZPmZ_D: |
| 29162 | case AArch64::FDIV_ZPmZ_H: |
| 29163 | case AArch64::FDIV_ZPmZ_S: |
| 29164 | case AArch64::FMAXNM_ZPmZ_D: |
| 29165 | case AArch64::FMAXNM_ZPmZ_H: |
| 29166 | case AArch64::FMAXNM_ZPmZ_S: |
| 29167 | case AArch64::FMAX_ZPmZ_D: |
| 29168 | case AArch64::FMAX_ZPmZ_H: |
| 29169 | case AArch64::FMAX_ZPmZ_S: |
| 29170 | case AArch64::FMINNM_ZPmZ_D: |
| 29171 | case AArch64::FMINNM_ZPmZ_H: |
| 29172 | case AArch64::FMINNM_ZPmZ_S: |
| 29173 | case AArch64::FMIN_ZPmZ_D: |
| 29174 | case AArch64::FMIN_ZPmZ_H: |
| 29175 | case AArch64::FMIN_ZPmZ_S: |
| 29176 | case AArch64::FMULX_ZPmZ_D: |
| 29177 | case AArch64::FMULX_ZPmZ_H: |
| 29178 | case AArch64::FMULX_ZPmZ_S: |
| 29179 | case AArch64::FMUL_ZPmZ_D: |
| 29180 | case AArch64::FMUL_ZPmZ_H: |
| 29181 | case AArch64::FMUL_ZPmZ_S: |
| 29182 | case AArch64::FSCALE_ZPmZ_D: |
| 29183 | case AArch64::FSCALE_ZPmZ_H: |
| 29184 | case AArch64::FSCALE_ZPmZ_S: |
| 29185 | case AArch64::FSUBR_ZPmZ_D: |
| 29186 | case AArch64::FSUBR_ZPmZ_H: |
| 29187 | case AArch64::FSUBR_ZPmZ_S: |
| 29188 | case AArch64::FSUB_ZPmZ_D: |
| 29189 | case AArch64::FSUB_ZPmZ_H: |
| 29190 | case AArch64::FSUB_ZPmZ_S: |
| 29191 | case AArch64::LSLR_ZPmZ_B: |
| 29192 | case AArch64::LSLR_ZPmZ_D: |
| 29193 | case AArch64::LSLR_ZPmZ_H: |
| 29194 | case AArch64::LSLR_ZPmZ_S: |
| 29195 | case AArch64::LSL_WIDE_ZPmZ_B: |
| 29196 | case AArch64::LSL_WIDE_ZPmZ_H: |
| 29197 | case AArch64::LSL_WIDE_ZPmZ_S: |
| 29198 | case AArch64::LSL_ZPmZ_B: |
| 29199 | case AArch64::LSL_ZPmZ_D: |
| 29200 | case AArch64::LSL_ZPmZ_H: |
| 29201 | case AArch64::LSL_ZPmZ_S: |
| 29202 | case AArch64::LSRR_ZPmZ_B: |
| 29203 | case AArch64::LSRR_ZPmZ_D: |
| 29204 | case AArch64::LSRR_ZPmZ_H: |
| 29205 | case AArch64::LSRR_ZPmZ_S: |
| 29206 | case AArch64::LSR_WIDE_ZPmZ_B: |
| 29207 | case AArch64::LSR_WIDE_ZPmZ_H: |
| 29208 | case AArch64::LSR_WIDE_ZPmZ_S: |
| 29209 | case AArch64::LSR_ZPmZ_B: |
| 29210 | case AArch64::LSR_ZPmZ_D: |
| 29211 | case AArch64::LSR_ZPmZ_H: |
| 29212 | case AArch64::LSR_ZPmZ_S: |
| 29213 | case AArch64::MUL_ZPmZ_B: |
| 29214 | case AArch64::MUL_ZPmZ_D: |
| 29215 | case AArch64::MUL_ZPmZ_H: |
| 29216 | case AArch64::MUL_ZPmZ_S: |
| 29217 | case AArch64::ORR_ZPmZ_B: |
| 29218 | case AArch64::ORR_ZPmZ_D: |
| 29219 | case AArch64::ORR_ZPmZ_H: |
| 29220 | case AArch64::ORR_ZPmZ_S: |
| 29221 | case AArch64::SABD_ZPmZ_B: |
| 29222 | case AArch64::SABD_ZPmZ_D: |
| 29223 | case AArch64::SABD_ZPmZ_H: |
| 29224 | case AArch64::SABD_ZPmZ_S: |
| 29225 | case AArch64::SDIVR_ZPmZ_D: |
| 29226 | case AArch64::SDIVR_ZPmZ_S: |
| 29227 | case AArch64::SDIV_ZPmZ_D: |
| 29228 | case AArch64::SDIV_ZPmZ_S: |
| 29229 | case AArch64::SMAX_ZPmZ_B: |
| 29230 | case AArch64::SMAX_ZPmZ_D: |
| 29231 | case AArch64::SMAX_ZPmZ_H: |
| 29232 | case AArch64::SMAX_ZPmZ_S: |
| 29233 | case AArch64::SMIN_ZPmZ_B: |
| 29234 | case AArch64::SMIN_ZPmZ_D: |
| 29235 | case AArch64::SMIN_ZPmZ_H: |
| 29236 | case AArch64::SMIN_ZPmZ_S: |
| 29237 | case AArch64::SMULH_ZPmZ_B: |
| 29238 | case AArch64::SMULH_ZPmZ_D: |
| 29239 | case AArch64::SMULH_ZPmZ_H: |
| 29240 | case AArch64::SMULH_ZPmZ_S: |
| 29241 | case AArch64::SPLICE_ZPZ_B: |
| 29242 | case AArch64::SPLICE_ZPZ_D: |
| 29243 | case AArch64::SPLICE_ZPZ_H: |
| 29244 | case AArch64::SPLICE_ZPZ_S: |
| 29245 | case AArch64::SUBR_ZPmZ_B: |
| 29246 | case AArch64::SUBR_ZPmZ_D: |
| 29247 | case AArch64::SUBR_ZPmZ_H: |
| 29248 | case AArch64::SUBR_ZPmZ_S: |
| 29249 | case AArch64::SUB_ZPmZ_B: |
| 29250 | case AArch64::SUB_ZPmZ_CPA: |
| 29251 | case AArch64::SUB_ZPmZ_D: |
| 29252 | case AArch64::SUB_ZPmZ_H: |
| 29253 | case AArch64::SUB_ZPmZ_S: |
| 29254 | case AArch64::UABD_ZPmZ_B: |
| 29255 | case AArch64::UABD_ZPmZ_D: |
| 29256 | case AArch64::UABD_ZPmZ_H: |
| 29257 | case AArch64::UABD_ZPmZ_S: |
| 29258 | case AArch64::UDIVR_ZPmZ_D: |
| 29259 | case AArch64::UDIVR_ZPmZ_S: |
| 29260 | case AArch64::UDIV_ZPmZ_D: |
| 29261 | case AArch64::UDIV_ZPmZ_S: |
| 29262 | case AArch64::UMAX_ZPmZ_B: |
| 29263 | case AArch64::UMAX_ZPmZ_D: |
| 29264 | case AArch64::UMAX_ZPmZ_H: |
| 29265 | case AArch64::UMAX_ZPmZ_S: |
| 29266 | case AArch64::UMIN_ZPmZ_B: |
| 29267 | case AArch64::UMIN_ZPmZ_D: |
| 29268 | case AArch64::UMIN_ZPmZ_H: |
| 29269 | case AArch64::UMIN_ZPmZ_S: |
| 29270 | case AArch64::UMULH_ZPmZ_B: |
| 29271 | case AArch64::UMULH_ZPmZ_D: |
| 29272 | case AArch64::UMULH_ZPmZ_H: |
| 29273 | case AArch64::UMULH_ZPmZ_S: { |
| 29274 | switch (OpNum) { |
| 29275 | case 1: |
| 29276 | // op: Pg |
| 29277 | return 10; |
| 29278 | case 0: |
| 29279 | // op: Zdn |
| 29280 | return 0; |
| 29281 | case 3: |
| 29282 | // op: Zm |
| 29283 | return 5; |
| 29284 | } |
| 29285 | break; |
| 29286 | } |
| 29287 | case AArch64::FADD_ZPmI_D: |
| 29288 | case AArch64::FADD_ZPmI_H: |
| 29289 | case AArch64::FADD_ZPmI_S: |
| 29290 | case AArch64::FMAXNM_ZPmI_D: |
| 29291 | case AArch64::FMAXNM_ZPmI_H: |
| 29292 | case AArch64::FMAXNM_ZPmI_S: |
| 29293 | case AArch64::FMAX_ZPmI_D: |
| 29294 | case AArch64::FMAX_ZPmI_H: |
| 29295 | case AArch64::FMAX_ZPmI_S: |
| 29296 | case AArch64::FMINNM_ZPmI_D: |
| 29297 | case AArch64::FMINNM_ZPmI_H: |
| 29298 | case AArch64::FMINNM_ZPmI_S: |
| 29299 | case AArch64::FMIN_ZPmI_D: |
| 29300 | case AArch64::FMIN_ZPmI_H: |
| 29301 | case AArch64::FMIN_ZPmI_S: |
| 29302 | case AArch64::FMUL_ZPmI_D: |
| 29303 | case AArch64::FMUL_ZPmI_H: |
| 29304 | case AArch64::FMUL_ZPmI_S: |
| 29305 | case AArch64::FSUBR_ZPmI_D: |
| 29306 | case AArch64::FSUBR_ZPmI_H: |
| 29307 | case AArch64::FSUBR_ZPmI_S: |
| 29308 | case AArch64::FSUB_ZPmI_D: |
| 29309 | case AArch64::FSUB_ZPmI_H: |
| 29310 | case AArch64::FSUB_ZPmI_S: { |
| 29311 | switch (OpNum) { |
| 29312 | case 1: |
| 29313 | // op: Pg |
| 29314 | return 10; |
| 29315 | case 0: |
| 29316 | // op: Zdn |
| 29317 | return 0; |
| 29318 | case 3: |
| 29319 | // op: i1 |
| 29320 | return 5; |
| 29321 | } |
| 29322 | break; |
| 29323 | } |
| 29324 | case AArch64::ASRD_ZPmI_B: |
| 29325 | case AArch64::ASRD_ZPmI_D: |
| 29326 | case AArch64::ASRD_ZPmI_H: |
| 29327 | case AArch64::ASRD_ZPmI_S: |
| 29328 | case AArch64::ASR_ZPmI_B: |
| 29329 | case AArch64::ASR_ZPmI_D: |
| 29330 | case AArch64::ASR_ZPmI_H: |
| 29331 | case AArch64::ASR_ZPmI_S: |
| 29332 | case AArch64::LSL_ZPmI_B: |
| 29333 | case AArch64::LSL_ZPmI_D: |
| 29334 | case AArch64::LSL_ZPmI_H: |
| 29335 | case AArch64::LSL_ZPmI_S: |
| 29336 | case AArch64::LSR_ZPmI_B: |
| 29337 | case AArch64::LSR_ZPmI_D: |
| 29338 | case AArch64::LSR_ZPmI_H: |
| 29339 | case AArch64::LSR_ZPmI_S: |
| 29340 | case AArch64::SQSHLU_ZPmI_B: |
| 29341 | case AArch64::SQSHLU_ZPmI_D: |
| 29342 | case AArch64::SQSHLU_ZPmI_H: |
| 29343 | case AArch64::SQSHLU_ZPmI_S: |
| 29344 | case AArch64::SQSHL_ZPmI_B: |
| 29345 | case AArch64::SQSHL_ZPmI_D: |
| 29346 | case AArch64::SQSHL_ZPmI_H: |
| 29347 | case AArch64::SQSHL_ZPmI_S: |
| 29348 | case AArch64::SRSHR_ZPmI_B: |
| 29349 | case AArch64::SRSHR_ZPmI_D: |
| 29350 | case AArch64::SRSHR_ZPmI_H: |
| 29351 | case AArch64::SRSHR_ZPmI_S: |
| 29352 | case AArch64::UQSHL_ZPmI_B: |
| 29353 | case AArch64::UQSHL_ZPmI_D: |
| 29354 | case AArch64::UQSHL_ZPmI_H: |
| 29355 | case AArch64::UQSHL_ZPmI_S: |
| 29356 | case AArch64::URSHR_ZPmI_B: |
| 29357 | case AArch64::URSHR_ZPmI_D: |
| 29358 | case AArch64::URSHR_ZPmI_H: |
| 29359 | case AArch64::URSHR_ZPmI_S: { |
| 29360 | switch (OpNum) { |
| 29361 | case 1: |
| 29362 | // op: Pg |
| 29363 | return 10; |
| 29364 | case 0: |
| 29365 | // op: Zdn |
| 29366 | return 0; |
| 29367 | case 3: |
| 29368 | // op: imm |
| 29369 | return 5; |
| 29370 | } |
| 29371 | break; |
| 29372 | } |
| 29373 | case AArch64::MAD_ZPmZZ_B: |
| 29374 | case AArch64::MAD_ZPmZZ_D: |
| 29375 | case AArch64::MAD_ZPmZZ_H: |
| 29376 | case AArch64::MAD_ZPmZZ_S: |
| 29377 | case AArch64::MSB_ZPmZZ_B: |
| 29378 | case AArch64::MSB_ZPmZZ_D: |
| 29379 | case AArch64::MSB_ZPmZZ_H: |
| 29380 | case AArch64::MSB_ZPmZZ_S: { |
| 29381 | switch (OpNum) { |
| 29382 | case 1: |
| 29383 | // op: Pg |
| 29384 | return 10; |
| 29385 | case 0: |
| 29386 | // op: Zdn |
| 29387 | return 0; |
| 29388 | case 4: |
| 29389 | // op: Za |
| 29390 | return 5; |
| 29391 | case 3: |
| 29392 | // op: Zm |
| 29393 | return 16; |
| 29394 | } |
| 29395 | break; |
| 29396 | } |
| 29397 | case AArch64::CNTP_XPP_B: |
| 29398 | case AArch64::CNTP_XPP_D: |
| 29399 | case AArch64::CNTP_XPP_H: |
| 29400 | case AArch64::CNTP_XPP_S: |
| 29401 | case AArch64::FIRSTP_XPP_B: |
| 29402 | case AArch64::FIRSTP_XPP_D: |
| 29403 | case AArch64::FIRSTP_XPP_H: |
| 29404 | case AArch64::FIRSTP_XPP_S: |
| 29405 | case AArch64::LASTP_XPP_B: |
| 29406 | case AArch64::LASTP_XPP_D: |
| 29407 | case AArch64::LASTP_XPP_H: |
| 29408 | case AArch64::LASTP_XPP_S: { |
| 29409 | switch (OpNum) { |
| 29410 | case 1: |
| 29411 | // op: Pg |
| 29412 | return 10; |
| 29413 | case 2: |
| 29414 | // op: Pn |
| 29415 | return 5; |
| 29416 | case 0: |
| 29417 | // op: Rd |
| 29418 | return 0; |
| 29419 | } |
| 29420 | break; |
| 29421 | } |
| 29422 | case AArch64::LD1B_D_IMM: |
| 29423 | case AArch64::LD1B_H_IMM: |
| 29424 | case AArch64::LD1B_IMM: |
| 29425 | case AArch64::LD1B_S_IMM: |
| 29426 | case AArch64::LD1D_IMM: |
| 29427 | case AArch64::LD1H_D_IMM: |
| 29428 | case AArch64::LD1H_IMM: |
| 29429 | case AArch64::LD1H_S_IMM: |
| 29430 | case AArch64::LD1SB_D_IMM: |
| 29431 | case AArch64::LD1SB_H_IMM: |
| 29432 | case AArch64::LD1SB_S_IMM: |
| 29433 | case AArch64::LD1SH_D_IMM: |
| 29434 | case AArch64::LD1SH_S_IMM: |
| 29435 | case AArch64::LD1SW_D_IMM: |
| 29436 | case AArch64::LD1W_D_IMM: |
| 29437 | case AArch64::LD1W_IMM: |
| 29438 | case AArch64::LDNF1B_D_IMM: |
| 29439 | case AArch64::LDNF1B_H_IMM: |
| 29440 | case AArch64::LDNF1B_IMM: |
| 29441 | case AArch64::LDNF1B_S_IMM: |
| 29442 | case AArch64::LDNF1D_IMM: |
| 29443 | case AArch64::LDNF1H_D_IMM: |
| 29444 | case AArch64::LDNF1H_IMM: |
| 29445 | case AArch64::LDNF1H_S_IMM: |
| 29446 | case AArch64::LDNF1SB_D_IMM: |
| 29447 | case AArch64::LDNF1SB_H_IMM: |
| 29448 | case AArch64::LDNF1SB_S_IMM: |
| 29449 | case AArch64::LDNF1SH_D_IMM: |
| 29450 | case AArch64::LDNF1SH_S_IMM: |
| 29451 | case AArch64::LDNF1SW_D_IMM: |
| 29452 | case AArch64::LDNF1W_D_IMM: |
| 29453 | case AArch64::LDNF1W_IMM: |
| 29454 | case AArch64::ST1B_D_IMM: |
| 29455 | case AArch64::ST1B_H_IMM: |
| 29456 | case AArch64::ST1B_IMM: |
| 29457 | case AArch64::ST1B_S_IMM: |
| 29458 | case AArch64::ST1D_IMM: |
| 29459 | case AArch64::ST1D_Q_IMM: |
| 29460 | case AArch64::ST1H_D_IMM: |
| 29461 | case AArch64::ST1H_IMM: |
| 29462 | case AArch64::ST1H_S_IMM: |
| 29463 | case AArch64::ST1W_D_IMM: |
| 29464 | case AArch64::ST1W_IMM: |
| 29465 | case AArch64::ST1W_Q_IMM: |
| 29466 | case AArch64::ST2B_IMM: |
| 29467 | case AArch64::ST2D_IMM: |
| 29468 | case AArch64::ST2H_IMM: |
| 29469 | case AArch64::ST2W_IMM: |
| 29470 | case AArch64::ST3B_IMM: |
| 29471 | case AArch64::ST3D_IMM: |
| 29472 | case AArch64::ST3H_IMM: |
| 29473 | case AArch64::ST3W_IMM: |
| 29474 | case AArch64::ST4B_IMM: |
| 29475 | case AArch64::ST4D_IMM: |
| 29476 | case AArch64::ST4H_IMM: |
| 29477 | case AArch64::ST4W_IMM: |
| 29478 | case AArch64::STNT1B_ZRI: |
| 29479 | case AArch64::STNT1D_ZRI: |
| 29480 | case AArch64::STNT1H_ZRI: |
| 29481 | case AArch64::STNT1W_ZRI: { |
| 29482 | switch (OpNum) { |
| 29483 | case 1: |
| 29484 | // op: Pg |
| 29485 | return 10; |
| 29486 | case 2: |
| 29487 | // op: Rn |
| 29488 | return 5; |
| 29489 | case 0: |
| 29490 | // op: Zt |
| 29491 | return 0; |
| 29492 | case 3: |
| 29493 | // op: imm4 |
| 29494 | return 16; |
| 29495 | } |
| 29496 | break; |
| 29497 | } |
| 29498 | case AArch64::LD1RB_D_IMM: |
| 29499 | case AArch64::LD1RB_H_IMM: |
| 29500 | case AArch64::LD1RB_IMM: |
| 29501 | case AArch64::LD1RB_S_IMM: |
| 29502 | case AArch64::LD1RD_IMM: |
| 29503 | case AArch64::LD1RH_D_IMM: |
| 29504 | case AArch64::LD1RH_IMM: |
| 29505 | case AArch64::LD1RH_S_IMM: |
| 29506 | case AArch64::LD1RSB_D_IMM: |
| 29507 | case AArch64::LD1RSB_H_IMM: |
| 29508 | case AArch64::LD1RSB_S_IMM: |
| 29509 | case AArch64::LD1RSH_D_IMM: |
| 29510 | case AArch64::LD1RSH_S_IMM: |
| 29511 | case AArch64::LD1RSW_IMM: |
| 29512 | case AArch64::LD1RW_D_IMM: |
| 29513 | case AArch64::LD1RW_IMM: { |
| 29514 | switch (OpNum) { |
| 29515 | case 1: |
| 29516 | // op: Pg |
| 29517 | return 10; |
| 29518 | case 2: |
| 29519 | // op: Rn |
| 29520 | return 5; |
| 29521 | case 0: |
| 29522 | // op: Zt |
| 29523 | return 0; |
| 29524 | case 3: |
| 29525 | // op: imm6 |
| 29526 | return 16; |
| 29527 | } |
| 29528 | break; |
| 29529 | } |
| 29530 | case AArch64::GLD1B_D: |
| 29531 | case AArch64::GLD1B_D_SXTW: |
| 29532 | case AArch64::GLD1B_D_UXTW: |
| 29533 | case AArch64::GLD1B_S_SXTW: |
| 29534 | case AArch64::GLD1B_S_UXTW: |
| 29535 | case AArch64::GLD1D: |
| 29536 | case AArch64::GLD1D_SCALED: |
| 29537 | case AArch64::GLD1D_SXTW: |
| 29538 | case AArch64::GLD1D_SXTW_SCALED: |
| 29539 | case AArch64::GLD1D_UXTW: |
| 29540 | case AArch64::GLD1D_UXTW_SCALED: |
| 29541 | case AArch64::GLD1H_D: |
| 29542 | case AArch64::GLD1H_D_SCALED: |
| 29543 | case AArch64::GLD1H_D_SXTW: |
| 29544 | case AArch64::GLD1H_D_SXTW_SCALED: |
| 29545 | case AArch64::GLD1H_D_UXTW: |
| 29546 | case AArch64::GLD1H_D_UXTW_SCALED: |
| 29547 | case AArch64::GLD1H_S_SXTW: |
| 29548 | case AArch64::GLD1H_S_SXTW_SCALED: |
| 29549 | case AArch64::GLD1H_S_UXTW: |
| 29550 | case AArch64::GLD1H_S_UXTW_SCALED: |
| 29551 | case AArch64::GLD1SB_D: |
| 29552 | case AArch64::GLD1SB_D_SXTW: |
| 29553 | case AArch64::GLD1SB_D_UXTW: |
| 29554 | case AArch64::GLD1SB_S_SXTW: |
| 29555 | case AArch64::GLD1SB_S_UXTW: |
| 29556 | case AArch64::GLD1SH_D: |
| 29557 | case AArch64::GLD1SH_D_SCALED: |
| 29558 | case AArch64::GLD1SH_D_SXTW: |
| 29559 | case AArch64::GLD1SH_D_SXTW_SCALED: |
| 29560 | case AArch64::GLD1SH_D_UXTW: |
| 29561 | case AArch64::GLD1SH_D_UXTW_SCALED: |
| 29562 | case AArch64::GLD1SH_S_SXTW: |
| 29563 | case AArch64::GLD1SH_S_SXTW_SCALED: |
| 29564 | case AArch64::GLD1SH_S_UXTW: |
| 29565 | case AArch64::GLD1SH_S_UXTW_SCALED: |
| 29566 | case AArch64::GLD1SW_D: |
| 29567 | case AArch64::GLD1SW_D_SCALED: |
| 29568 | case AArch64::GLD1SW_D_SXTW: |
| 29569 | case AArch64::GLD1SW_D_SXTW_SCALED: |
| 29570 | case AArch64::GLD1SW_D_UXTW: |
| 29571 | case AArch64::GLD1SW_D_UXTW_SCALED: |
| 29572 | case AArch64::GLD1W_D: |
| 29573 | case AArch64::GLD1W_D_SCALED: |
| 29574 | case AArch64::GLD1W_D_SXTW: |
| 29575 | case AArch64::GLD1W_D_SXTW_SCALED: |
| 29576 | case AArch64::GLD1W_D_UXTW: |
| 29577 | case AArch64::GLD1W_D_UXTW_SCALED: |
| 29578 | case AArch64::GLD1W_SXTW: |
| 29579 | case AArch64::GLD1W_SXTW_SCALED: |
| 29580 | case AArch64::GLD1W_UXTW: |
| 29581 | case AArch64::GLD1W_UXTW_SCALED: |
| 29582 | case AArch64::GLDFF1B_D: |
| 29583 | case AArch64::GLDFF1B_D_SXTW: |
| 29584 | case AArch64::GLDFF1B_D_UXTW: |
| 29585 | case AArch64::GLDFF1B_S_SXTW: |
| 29586 | case AArch64::GLDFF1B_S_UXTW: |
| 29587 | case AArch64::GLDFF1D: |
| 29588 | case AArch64::GLDFF1D_SCALED: |
| 29589 | case AArch64::GLDFF1D_SXTW: |
| 29590 | case AArch64::GLDFF1D_SXTW_SCALED: |
| 29591 | case AArch64::GLDFF1D_UXTW: |
| 29592 | case AArch64::GLDFF1D_UXTW_SCALED: |
| 29593 | case AArch64::GLDFF1H_D: |
| 29594 | case AArch64::GLDFF1H_D_SCALED: |
| 29595 | case AArch64::GLDFF1H_D_SXTW: |
| 29596 | case AArch64::GLDFF1H_D_SXTW_SCALED: |
| 29597 | case AArch64::GLDFF1H_D_UXTW: |
| 29598 | case AArch64::GLDFF1H_D_UXTW_SCALED: |
| 29599 | case AArch64::GLDFF1H_S_SXTW: |
| 29600 | case AArch64::GLDFF1H_S_SXTW_SCALED: |
| 29601 | case AArch64::GLDFF1H_S_UXTW: |
| 29602 | case AArch64::GLDFF1H_S_UXTW_SCALED: |
| 29603 | case AArch64::GLDFF1SB_D: |
| 29604 | case AArch64::GLDFF1SB_D_SXTW: |
| 29605 | case AArch64::GLDFF1SB_D_UXTW: |
| 29606 | case AArch64::GLDFF1SB_S_SXTW: |
| 29607 | case AArch64::GLDFF1SB_S_UXTW: |
| 29608 | case AArch64::GLDFF1SH_D: |
| 29609 | case AArch64::GLDFF1SH_D_SCALED: |
| 29610 | case AArch64::GLDFF1SH_D_SXTW: |
| 29611 | case AArch64::GLDFF1SH_D_SXTW_SCALED: |
| 29612 | case AArch64::GLDFF1SH_D_UXTW: |
| 29613 | case AArch64::GLDFF1SH_D_UXTW_SCALED: |
| 29614 | case AArch64::GLDFF1SH_S_SXTW: |
| 29615 | case AArch64::GLDFF1SH_S_SXTW_SCALED: |
| 29616 | case AArch64::GLDFF1SH_S_UXTW: |
| 29617 | case AArch64::GLDFF1SH_S_UXTW_SCALED: |
| 29618 | case AArch64::GLDFF1SW_D: |
| 29619 | case AArch64::GLDFF1SW_D_SCALED: |
| 29620 | case AArch64::GLDFF1SW_D_SXTW: |
| 29621 | case AArch64::GLDFF1SW_D_SXTW_SCALED: |
| 29622 | case AArch64::GLDFF1SW_D_UXTW: |
| 29623 | case AArch64::GLDFF1SW_D_UXTW_SCALED: |
| 29624 | case AArch64::GLDFF1W_D: |
| 29625 | case AArch64::GLDFF1W_D_SCALED: |
| 29626 | case AArch64::GLDFF1W_D_SXTW: |
| 29627 | case AArch64::GLDFF1W_D_SXTW_SCALED: |
| 29628 | case AArch64::GLDFF1W_D_UXTW: |
| 29629 | case AArch64::GLDFF1W_D_UXTW_SCALED: |
| 29630 | case AArch64::GLDFF1W_SXTW: |
| 29631 | case AArch64::GLDFF1W_SXTW_SCALED: |
| 29632 | case AArch64::GLDFF1W_UXTW: |
| 29633 | case AArch64::GLDFF1W_UXTW_SCALED: |
| 29634 | case AArch64::SST1B_D: |
| 29635 | case AArch64::SST1B_D_SXTW: |
| 29636 | case AArch64::SST1B_D_UXTW: |
| 29637 | case AArch64::SST1B_S_SXTW: |
| 29638 | case AArch64::SST1B_S_UXTW: |
| 29639 | case AArch64::SST1D: |
| 29640 | case AArch64::SST1D_SCALED: |
| 29641 | case AArch64::SST1D_SXTW: |
| 29642 | case AArch64::SST1D_SXTW_SCALED: |
| 29643 | case AArch64::SST1D_UXTW: |
| 29644 | case AArch64::SST1D_UXTW_SCALED: |
| 29645 | case AArch64::SST1H_D: |
| 29646 | case AArch64::SST1H_D_SCALED: |
| 29647 | case AArch64::SST1H_D_SXTW: |
| 29648 | case AArch64::SST1H_D_SXTW_SCALED: |
| 29649 | case AArch64::SST1H_D_UXTW: |
| 29650 | case AArch64::SST1H_D_UXTW_SCALED: |
| 29651 | case AArch64::SST1H_S_SXTW: |
| 29652 | case AArch64::SST1H_S_SXTW_SCALED: |
| 29653 | case AArch64::SST1H_S_UXTW: |
| 29654 | case AArch64::SST1H_S_UXTW_SCALED: |
| 29655 | case AArch64::SST1W_D: |
| 29656 | case AArch64::SST1W_D_SCALED: |
| 29657 | case AArch64::SST1W_D_SXTW: |
| 29658 | case AArch64::SST1W_D_SXTW_SCALED: |
| 29659 | case AArch64::SST1W_D_UXTW: |
| 29660 | case AArch64::SST1W_D_UXTW_SCALED: |
| 29661 | case AArch64::SST1W_SXTW: |
| 29662 | case AArch64::SST1W_SXTW_SCALED: |
| 29663 | case AArch64::SST1W_UXTW: |
| 29664 | case AArch64::SST1W_UXTW_SCALED: { |
| 29665 | switch (OpNum) { |
| 29666 | case 1: |
| 29667 | // op: Pg |
| 29668 | return 10; |
| 29669 | case 2: |
| 29670 | // op: Rn |
| 29671 | return 5; |
| 29672 | case 3: |
| 29673 | // op: Zm |
| 29674 | return 16; |
| 29675 | case 0: |
| 29676 | // op: Zt |
| 29677 | return 0; |
| 29678 | } |
| 29679 | break; |
| 29680 | } |
| 29681 | case AArch64::PRFB_D_SCALED: |
| 29682 | case AArch64::PRFB_D_SXTW_SCALED: |
| 29683 | case AArch64::PRFB_D_UXTW_SCALED: |
| 29684 | case AArch64::PRFB_S_SXTW_SCALED: |
| 29685 | case AArch64::PRFB_S_UXTW_SCALED: |
| 29686 | case AArch64::PRFD_D_SCALED: |
| 29687 | case AArch64::PRFD_D_SXTW_SCALED: |
| 29688 | case AArch64::PRFD_D_UXTW_SCALED: |
| 29689 | case AArch64::PRFD_S_SXTW_SCALED: |
| 29690 | case AArch64::PRFD_S_UXTW_SCALED: |
| 29691 | case AArch64::PRFH_D_SCALED: |
| 29692 | case AArch64::PRFH_D_SXTW_SCALED: |
| 29693 | case AArch64::PRFH_D_UXTW_SCALED: |
| 29694 | case AArch64::PRFH_S_SXTW_SCALED: |
| 29695 | case AArch64::PRFH_S_UXTW_SCALED: |
| 29696 | case AArch64::PRFW_D_SCALED: |
| 29697 | case AArch64::PRFW_D_SXTW_SCALED: |
| 29698 | case AArch64::PRFW_D_UXTW_SCALED: |
| 29699 | case AArch64::PRFW_S_SXTW_SCALED: |
| 29700 | case AArch64::PRFW_S_UXTW_SCALED: { |
| 29701 | switch (OpNum) { |
| 29702 | case 1: |
| 29703 | // op: Pg |
| 29704 | return 10; |
| 29705 | case 2: |
| 29706 | // op: Rn |
| 29707 | return 5; |
| 29708 | case 3: |
| 29709 | // op: Zm |
| 29710 | return 16; |
| 29711 | case 0: |
| 29712 | // op: prfop |
| 29713 | return 0; |
| 29714 | } |
| 29715 | break; |
| 29716 | } |
| 29717 | case AArch64::EXPAND_ZPZ_B: |
| 29718 | case AArch64::EXPAND_ZPZ_D: |
| 29719 | case AArch64::EXPAND_ZPZ_H: |
| 29720 | case AArch64::EXPAND_ZPZ_S: |
| 29721 | case AArch64::SPLICE_ZPZZ_B: |
| 29722 | case AArch64::SPLICE_ZPZZ_D: |
| 29723 | case AArch64::SPLICE_ZPZZ_H: |
| 29724 | case AArch64::SPLICE_ZPZZ_S: { |
| 29725 | switch (OpNum) { |
| 29726 | case 1: |
| 29727 | // op: Pg |
| 29728 | return 10; |
| 29729 | case 2: |
| 29730 | // op: Zn |
| 29731 | return 5; |
| 29732 | case 0: |
| 29733 | // op: Zd |
| 29734 | return 0; |
| 29735 | } |
| 29736 | break; |
| 29737 | } |
| 29738 | case AArch64::GLD1B_D_IMM: |
| 29739 | case AArch64::GLD1B_S_IMM: |
| 29740 | case AArch64::GLD1D_IMM: |
| 29741 | case AArch64::GLD1H_D_IMM: |
| 29742 | case AArch64::GLD1H_S_IMM: |
| 29743 | case AArch64::GLD1SB_D_IMM: |
| 29744 | case AArch64::GLD1SB_S_IMM: |
| 29745 | case AArch64::GLD1SH_D_IMM: |
| 29746 | case AArch64::GLD1SH_S_IMM: |
| 29747 | case AArch64::GLD1SW_D_IMM: |
| 29748 | case AArch64::GLD1W_D_IMM: |
| 29749 | case AArch64::GLD1W_IMM: |
| 29750 | case AArch64::GLDFF1B_D_IMM: |
| 29751 | case AArch64::GLDFF1B_S_IMM: |
| 29752 | case AArch64::GLDFF1D_IMM: |
| 29753 | case AArch64::GLDFF1H_D_IMM: |
| 29754 | case AArch64::GLDFF1H_S_IMM: |
| 29755 | case AArch64::GLDFF1SB_D_IMM: |
| 29756 | case AArch64::GLDFF1SB_S_IMM: |
| 29757 | case AArch64::GLDFF1SH_D_IMM: |
| 29758 | case AArch64::GLDFF1SH_S_IMM: |
| 29759 | case AArch64::GLDFF1SW_D_IMM: |
| 29760 | case AArch64::GLDFF1W_D_IMM: |
| 29761 | case AArch64::GLDFF1W_IMM: { |
| 29762 | switch (OpNum) { |
| 29763 | case 1: |
| 29764 | // op: Pg |
| 29765 | return 10; |
| 29766 | case 2: |
| 29767 | // op: Zn |
| 29768 | return 5; |
| 29769 | case 0: |
| 29770 | // op: Zt |
| 29771 | return 0; |
| 29772 | case 3: |
| 29773 | // op: imm5 |
| 29774 | return 16; |
| 29775 | } |
| 29776 | break; |
| 29777 | } |
| 29778 | case AArch64::PRFB_D_PZI: |
| 29779 | case AArch64::PRFB_S_PZI: |
| 29780 | case AArch64::PRFD_D_PZI: |
| 29781 | case AArch64::PRFD_S_PZI: |
| 29782 | case AArch64::PRFH_D_PZI: |
| 29783 | case AArch64::PRFH_S_PZI: |
| 29784 | case AArch64::PRFW_D_PZI: |
| 29785 | case AArch64::PRFW_S_PZI: { |
| 29786 | switch (OpNum) { |
| 29787 | case 1: |
| 29788 | // op: Pg |
| 29789 | return 10; |
| 29790 | case 2: |
| 29791 | // op: Zn |
| 29792 | return 5; |
| 29793 | case 3: |
| 29794 | // op: imm5 |
| 29795 | return 16; |
| 29796 | case 0: |
| 29797 | // op: prfop |
| 29798 | return 0; |
| 29799 | } |
| 29800 | break; |
| 29801 | } |
| 29802 | case AArch64::LD2B: |
| 29803 | case AArch64::LD2D: |
| 29804 | case AArch64::LD2H: |
| 29805 | case AArch64::LD2Q: |
| 29806 | case AArch64::LD2W: |
| 29807 | case AArch64::LD3B: |
| 29808 | case AArch64::LD3D: |
| 29809 | case AArch64::LD3H: |
| 29810 | case AArch64::LD3Q: |
| 29811 | case AArch64::LD3W: |
| 29812 | case AArch64::LD4B: |
| 29813 | case AArch64::LD4D: |
| 29814 | case AArch64::LD4H: |
| 29815 | case AArch64::LD4Q: |
| 29816 | case AArch64::LD4W: |
| 29817 | case AArch64::LDNT1B_ZRR: |
| 29818 | case AArch64::LDNT1D_ZRR: |
| 29819 | case AArch64::LDNT1H_ZRR: |
| 29820 | case AArch64::LDNT1W_ZRR: |
| 29821 | case AArch64::ST1B: |
| 29822 | case AArch64::ST1B_D: |
| 29823 | case AArch64::ST1B_H: |
| 29824 | case AArch64::ST1B_S: |
| 29825 | case AArch64::ST1D: |
| 29826 | case AArch64::ST1D_Q: |
| 29827 | case AArch64::ST1H: |
| 29828 | case AArch64::ST1H_D: |
| 29829 | case AArch64::ST1H_S: |
| 29830 | case AArch64::ST1W: |
| 29831 | case AArch64::ST1W_D: |
| 29832 | case AArch64::ST1W_Q: |
| 29833 | case AArch64::ST2B: |
| 29834 | case AArch64::ST2D: |
| 29835 | case AArch64::ST2H: |
| 29836 | case AArch64::ST2W: |
| 29837 | case AArch64::ST3B: |
| 29838 | case AArch64::ST3D: |
| 29839 | case AArch64::ST3H: |
| 29840 | case AArch64::ST3W: |
| 29841 | case AArch64::ST4B: |
| 29842 | case AArch64::ST4D: |
| 29843 | case AArch64::ST4H: |
| 29844 | case AArch64::ST4W: |
| 29845 | case AArch64::STNT1B_ZRR: |
| 29846 | case AArch64::STNT1D_ZRR: |
| 29847 | case AArch64::STNT1H_ZRR: |
| 29848 | case AArch64::STNT1W_ZRR: { |
| 29849 | switch (OpNum) { |
| 29850 | case 1: |
| 29851 | // op: Pg |
| 29852 | return 10; |
| 29853 | case 3: |
| 29854 | // op: Rm |
| 29855 | return 16; |
| 29856 | case 2: |
| 29857 | // op: Rn |
| 29858 | return 5; |
| 29859 | case 0: |
| 29860 | // op: Zt |
| 29861 | return 0; |
| 29862 | } |
| 29863 | break; |
| 29864 | } |
| 29865 | case AArch64::LDNT1B_ZZR_D: |
| 29866 | case AArch64::LDNT1B_ZZR_S: |
| 29867 | case AArch64::LDNT1D_ZZR_D: |
| 29868 | case AArch64::LDNT1H_ZZR_D: |
| 29869 | case AArch64::LDNT1H_ZZR_S: |
| 29870 | case AArch64::LDNT1SB_ZZR_D: |
| 29871 | case AArch64::LDNT1SB_ZZR_S: |
| 29872 | case AArch64::LDNT1SH_ZZR_D: |
| 29873 | case AArch64::LDNT1SH_ZZR_S: |
| 29874 | case AArch64::LDNT1SW_ZZR_D: |
| 29875 | case AArch64::LDNT1W_ZZR_D: |
| 29876 | case AArch64::LDNT1W_ZZR_S: |
| 29877 | case AArch64::STNT1B_ZZR_D: |
| 29878 | case AArch64::STNT1B_ZZR_S: |
| 29879 | case AArch64::STNT1D_ZZR_D: |
| 29880 | case AArch64::STNT1H_ZZR_D: |
| 29881 | case AArch64::STNT1H_ZZR_S: |
| 29882 | case AArch64::STNT1W_ZZR_D: |
| 29883 | case AArch64::STNT1W_ZZR_S: { |
| 29884 | switch (OpNum) { |
| 29885 | case 1: |
| 29886 | // op: Pg |
| 29887 | return 10; |
| 29888 | case 3: |
| 29889 | // op: Rm |
| 29890 | return 16; |
| 29891 | case 2: |
| 29892 | // op: Zn |
| 29893 | return 5; |
| 29894 | case 0: |
| 29895 | // op: Zt |
| 29896 | return 0; |
| 29897 | } |
| 29898 | break; |
| 29899 | } |
| 29900 | case AArch64::ADDP_ZPmZ_B: |
| 29901 | case AArch64::ADDP_ZPmZ_D: |
| 29902 | case AArch64::ADDP_ZPmZ_H: |
| 29903 | case AArch64::ADDP_ZPmZ_S: |
| 29904 | case AArch64::FADDP_ZPmZZ_D: |
| 29905 | case AArch64::FADDP_ZPmZZ_H: |
| 29906 | case AArch64::FADDP_ZPmZZ_S: |
| 29907 | case AArch64::FMAXNMP_ZPmZZ_D: |
| 29908 | case AArch64::FMAXNMP_ZPmZZ_H: |
| 29909 | case AArch64::FMAXNMP_ZPmZZ_S: |
| 29910 | case AArch64::FMAXP_ZPmZZ_D: |
| 29911 | case AArch64::FMAXP_ZPmZZ_H: |
| 29912 | case AArch64::FMAXP_ZPmZZ_S: |
| 29913 | case AArch64::FMINNMP_ZPmZZ_D: |
| 29914 | case AArch64::FMINNMP_ZPmZZ_H: |
| 29915 | case AArch64::FMINNMP_ZPmZZ_S: |
| 29916 | case AArch64::FMINP_ZPmZZ_D: |
| 29917 | case AArch64::FMINP_ZPmZZ_H: |
| 29918 | case AArch64::FMINP_ZPmZZ_S: |
| 29919 | case AArch64::SHADD_ZPmZ_B: |
| 29920 | case AArch64::SHADD_ZPmZ_D: |
| 29921 | case AArch64::SHADD_ZPmZ_H: |
| 29922 | case AArch64::SHADD_ZPmZ_S: |
| 29923 | case AArch64::SHSUBR_ZPmZ_B: |
| 29924 | case AArch64::SHSUBR_ZPmZ_D: |
| 29925 | case AArch64::SHSUBR_ZPmZ_H: |
| 29926 | case AArch64::SHSUBR_ZPmZ_S: |
| 29927 | case AArch64::SHSUB_ZPmZ_B: |
| 29928 | case AArch64::SHSUB_ZPmZ_D: |
| 29929 | case AArch64::SHSUB_ZPmZ_H: |
| 29930 | case AArch64::SHSUB_ZPmZ_S: |
| 29931 | case AArch64::SMAXP_ZPmZ_B: |
| 29932 | case AArch64::SMAXP_ZPmZ_D: |
| 29933 | case AArch64::SMAXP_ZPmZ_H: |
| 29934 | case AArch64::SMAXP_ZPmZ_S: |
| 29935 | case AArch64::SMINP_ZPmZ_B: |
| 29936 | case AArch64::SMINP_ZPmZ_D: |
| 29937 | case AArch64::SMINP_ZPmZ_H: |
| 29938 | case AArch64::SMINP_ZPmZ_S: |
| 29939 | case AArch64::SQADD_ZPmZ_B: |
| 29940 | case AArch64::SQADD_ZPmZ_D: |
| 29941 | case AArch64::SQADD_ZPmZ_H: |
| 29942 | case AArch64::SQADD_ZPmZ_S: |
| 29943 | case AArch64::SQRSHLR_ZPmZ_B: |
| 29944 | case AArch64::SQRSHLR_ZPmZ_D: |
| 29945 | case AArch64::SQRSHLR_ZPmZ_H: |
| 29946 | case AArch64::SQRSHLR_ZPmZ_S: |
| 29947 | case AArch64::SQRSHL_ZPmZ_B: |
| 29948 | case AArch64::SQRSHL_ZPmZ_D: |
| 29949 | case AArch64::SQRSHL_ZPmZ_H: |
| 29950 | case AArch64::SQRSHL_ZPmZ_S: |
| 29951 | case AArch64::SQSHLR_ZPmZ_B: |
| 29952 | case AArch64::SQSHLR_ZPmZ_D: |
| 29953 | case AArch64::SQSHLR_ZPmZ_H: |
| 29954 | case AArch64::SQSHLR_ZPmZ_S: |
| 29955 | case AArch64::SQSHL_ZPmZ_B: |
| 29956 | case AArch64::SQSHL_ZPmZ_D: |
| 29957 | case AArch64::SQSHL_ZPmZ_H: |
| 29958 | case AArch64::SQSHL_ZPmZ_S: |
| 29959 | case AArch64::SQSUBR_ZPmZ_B: |
| 29960 | case AArch64::SQSUBR_ZPmZ_D: |
| 29961 | case AArch64::SQSUBR_ZPmZ_H: |
| 29962 | case AArch64::SQSUBR_ZPmZ_S: |
| 29963 | case AArch64::SQSUB_ZPmZ_B: |
| 29964 | case AArch64::SQSUB_ZPmZ_D: |
| 29965 | case AArch64::SQSUB_ZPmZ_H: |
| 29966 | case AArch64::SQSUB_ZPmZ_S: |
| 29967 | case AArch64::SRHADD_ZPmZ_B: |
| 29968 | case AArch64::SRHADD_ZPmZ_D: |
| 29969 | case AArch64::SRHADD_ZPmZ_H: |
| 29970 | case AArch64::SRHADD_ZPmZ_S: |
| 29971 | case AArch64::SRSHLR_ZPmZ_B: |
| 29972 | case AArch64::SRSHLR_ZPmZ_D: |
| 29973 | case AArch64::SRSHLR_ZPmZ_H: |
| 29974 | case AArch64::SRSHLR_ZPmZ_S: |
| 29975 | case AArch64::SRSHL_ZPmZ_B: |
| 29976 | case AArch64::SRSHL_ZPmZ_D: |
| 29977 | case AArch64::SRSHL_ZPmZ_H: |
| 29978 | case AArch64::SRSHL_ZPmZ_S: |
| 29979 | case AArch64::SUBP_ZPmZZ_B: |
| 29980 | case AArch64::SUBP_ZPmZZ_D: |
| 29981 | case AArch64::SUBP_ZPmZZ_H: |
| 29982 | case AArch64::SUBP_ZPmZZ_S: |
| 29983 | case AArch64::SUQADD_ZPmZ_B: |
| 29984 | case AArch64::SUQADD_ZPmZ_D: |
| 29985 | case AArch64::SUQADD_ZPmZ_H: |
| 29986 | case AArch64::SUQADD_ZPmZ_S: |
| 29987 | case AArch64::UHADD_ZPmZ_B: |
| 29988 | case AArch64::UHADD_ZPmZ_D: |
| 29989 | case AArch64::UHADD_ZPmZ_H: |
| 29990 | case AArch64::UHADD_ZPmZ_S: |
| 29991 | case AArch64::UHSUBR_ZPmZ_B: |
| 29992 | case AArch64::UHSUBR_ZPmZ_D: |
| 29993 | case AArch64::UHSUBR_ZPmZ_H: |
| 29994 | case AArch64::UHSUBR_ZPmZ_S: |
| 29995 | case AArch64::UHSUB_ZPmZ_B: |
| 29996 | case AArch64::UHSUB_ZPmZ_D: |
| 29997 | case AArch64::UHSUB_ZPmZ_H: |
| 29998 | case AArch64::UHSUB_ZPmZ_S: |
| 29999 | case AArch64::UMAXP_ZPmZ_B: |
| 30000 | case AArch64::UMAXP_ZPmZ_D: |
| 30001 | case AArch64::UMAXP_ZPmZ_H: |
| 30002 | case AArch64::UMAXP_ZPmZ_S: |
| 30003 | case AArch64::UMINP_ZPmZ_B: |
| 30004 | case AArch64::UMINP_ZPmZ_D: |
| 30005 | case AArch64::UMINP_ZPmZ_H: |
| 30006 | case AArch64::UMINP_ZPmZ_S: |
| 30007 | case AArch64::UQADD_ZPmZ_B: |
| 30008 | case AArch64::UQADD_ZPmZ_D: |
| 30009 | case AArch64::UQADD_ZPmZ_H: |
| 30010 | case AArch64::UQADD_ZPmZ_S: |
| 30011 | case AArch64::UQRSHLR_ZPmZ_B: |
| 30012 | case AArch64::UQRSHLR_ZPmZ_D: |
| 30013 | case AArch64::UQRSHLR_ZPmZ_H: |
| 30014 | case AArch64::UQRSHLR_ZPmZ_S: |
| 30015 | case AArch64::UQRSHL_ZPmZ_B: |
| 30016 | case AArch64::UQRSHL_ZPmZ_D: |
| 30017 | case AArch64::UQRSHL_ZPmZ_H: |
| 30018 | case AArch64::UQRSHL_ZPmZ_S: |
| 30019 | case AArch64::UQSHLR_ZPmZ_B: |
| 30020 | case AArch64::UQSHLR_ZPmZ_D: |
| 30021 | case AArch64::UQSHLR_ZPmZ_H: |
| 30022 | case AArch64::UQSHLR_ZPmZ_S: |
| 30023 | case AArch64::UQSHL_ZPmZ_B: |
| 30024 | case AArch64::UQSHL_ZPmZ_D: |
| 30025 | case AArch64::UQSHL_ZPmZ_H: |
| 30026 | case AArch64::UQSHL_ZPmZ_S: |
| 30027 | case AArch64::UQSUBR_ZPmZ_B: |
| 30028 | case AArch64::UQSUBR_ZPmZ_D: |
| 30029 | case AArch64::UQSUBR_ZPmZ_H: |
| 30030 | case AArch64::UQSUBR_ZPmZ_S: |
| 30031 | case AArch64::UQSUB_ZPmZ_B: |
| 30032 | case AArch64::UQSUB_ZPmZ_D: |
| 30033 | case AArch64::UQSUB_ZPmZ_H: |
| 30034 | case AArch64::UQSUB_ZPmZ_S: |
| 30035 | case AArch64::URHADD_ZPmZ_B: |
| 30036 | case AArch64::URHADD_ZPmZ_D: |
| 30037 | case AArch64::URHADD_ZPmZ_H: |
| 30038 | case AArch64::URHADD_ZPmZ_S: |
| 30039 | case AArch64::URSHLR_ZPmZ_B: |
| 30040 | case AArch64::URSHLR_ZPmZ_D: |
| 30041 | case AArch64::URSHLR_ZPmZ_H: |
| 30042 | case AArch64::URSHLR_ZPmZ_S: |
| 30043 | case AArch64::URSHL_ZPmZ_B: |
| 30044 | case AArch64::URSHL_ZPmZ_D: |
| 30045 | case AArch64::URSHL_ZPmZ_H: |
| 30046 | case AArch64::URSHL_ZPmZ_S: |
| 30047 | case AArch64::USQADD_ZPmZ_B: |
| 30048 | case AArch64::USQADD_ZPmZ_D: |
| 30049 | case AArch64::USQADD_ZPmZ_H: |
| 30050 | case AArch64::USQADD_ZPmZ_S: { |
| 30051 | switch (OpNum) { |
| 30052 | case 1: |
| 30053 | // op: Pg |
| 30054 | return 10; |
| 30055 | case 3: |
| 30056 | // op: Zm |
| 30057 | return 5; |
| 30058 | case 0: |
| 30059 | // op: Zdn |
| 30060 | return 0; |
| 30061 | } |
| 30062 | break; |
| 30063 | } |
| 30064 | case AArch64::SADALP_ZPmZ_D: |
| 30065 | case AArch64::SADALP_ZPmZ_H: |
| 30066 | case AArch64::SADALP_ZPmZ_S: |
| 30067 | case AArch64::UADALP_ZPmZ_D: |
| 30068 | case AArch64::UADALP_ZPmZ_H: |
| 30069 | case AArch64::UADALP_ZPmZ_S: { |
| 30070 | switch (OpNum) { |
| 30071 | case 1: |
| 30072 | // op: Pg |
| 30073 | return 10; |
| 30074 | case 3: |
| 30075 | // op: Zn |
| 30076 | return 5; |
| 30077 | case 0: |
| 30078 | // op: Zda |
| 30079 | return 0; |
| 30080 | } |
| 30081 | break; |
| 30082 | } |
| 30083 | case AArch64::SST1B_D_IMM: |
| 30084 | case AArch64::SST1B_S_IMM: |
| 30085 | case AArch64::SST1D_IMM: |
| 30086 | case AArch64::SST1H_D_IMM: |
| 30087 | case AArch64::SST1H_S_IMM: |
| 30088 | case AArch64::SST1W_D_IMM: |
| 30089 | case AArch64::SST1W_IMM: { |
| 30090 | switch (OpNum) { |
| 30091 | case 1: |
| 30092 | // op: Pg |
| 30093 | return 10; |
| 30094 | case 3: |
| 30095 | // op: imm5 |
| 30096 | return 16; |
| 30097 | case 2: |
| 30098 | // op: Zn |
| 30099 | return 5; |
| 30100 | case 0: |
| 30101 | // op: Zt |
| 30102 | return 0; |
| 30103 | } |
| 30104 | break; |
| 30105 | } |
| 30106 | case AArch64::FMAD_ZPmZZ_D: |
| 30107 | case AArch64::FMAD_ZPmZZ_H: |
| 30108 | case AArch64::FMAD_ZPmZZ_S: |
| 30109 | case AArch64::FMSB_ZPmZZ_D: |
| 30110 | case AArch64::FMSB_ZPmZZ_H: |
| 30111 | case AArch64::FMSB_ZPmZZ_S: |
| 30112 | case AArch64::FNMAD_ZPmZZ_D: |
| 30113 | case AArch64::FNMAD_ZPmZZ_H: |
| 30114 | case AArch64::FNMAD_ZPmZZ_S: |
| 30115 | case AArch64::FNMSB_ZPmZZ_D: |
| 30116 | case AArch64::FNMSB_ZPmZZ_H: |
| 30117 | case AArch64::FNMSB_ZPmZZ_S: { |
| 30118 | switch (OpNum) { |
| 30119 | case 1: |
| 30120 | // op: Pg |
| 30121 | return 10; |
| 30122 | case 4: |
| 30123 | // op: Za |
| 30124 | return 16; |
| 30125 | case 0: |
| 30126 | // op: Zdn |
| 30127 | return 0; |
| 30128 | case 3: |
| 30129 | // op: Zm |
| 30130 | return 5; |
| 30131 | } |
| 30132 | break; |
| 30133 | } |
| 30134 | case AArch64::BF16DOTlanev4bf16: |
| 30135 | case AArch64::BF16DOTlanev8bf16: |
| 30136 | case AArch64::BFMLALBIdx: |
| 30137 | case AArch64::BFMLALTIdx: |
| 30138 | case AArch64::FDOTlanev2f32: |
| 30139 | case AArch64::FDOTlanev4f16: |
| 30140 | case AArch64::FDOTlanev4f16_v2f32: |
| 30141 | case AArch64::FDOTlanev4f32: |
| 30142 | case AArch64::FDOTlanev8f16: |
| 30143 | case AArch64::FDOTlanev8f16_v4f32: |
| 30144 | case AArch64::FMLAL2lanev4f16: |
| 30145 | case AArch64::FMLAL2lanev8f16: |
| 30146 | case AArch64::FMLALBlanev8f16: |
| 30147 | case AArch64::FMLALLBBlanev4f32: |
| 30148 | case AArch64::FMLALLBTlanev4f32: |
| 30149 | case AArch64::FMLALLTBlanev4f32: |
| 30150 | case AArch64::FMLALLTTlanev4f32: |
| 30151 | case AArch64::FMLALTlanev8f16: |
| 30152 | case AArch64::FMLALlanev4f16: |
| 30153 | case AArch64::FMLALlanev8f16: |
| 30154 | case AArch64::FMLAv1i16_indexed: |
| 30155 | case AArch64::FMLAv1i32_indexed: |
| 30156 | case AArch64::FMLAv1i64_indexed: |
| 30157 | case AArch64::FMLAv2i32_indexed: |
| 30158 | case AArch64::FMLAv2i64_indexed: |
| 30159 | case AArch64::FMLAv4i16_indexed: |
| 30160 | case AArch64::FMLAv4i32_indexed: |
| 30161 | case AArch64::FMLAv8i16_indexed: |
| 30162 | case AArch64::FMLSL2lanev4f16: |
| 30163 | case AArch64::FMLSL2lanev8f16: |
| 30164 | case AArch64::FMLSLlanev4f16: |
| 30165 | case AArch64::FMLSLlanev8f16: |
| 30166 | case AArch64::FMLSv1i16_indexed: |
| 30167 | case AArch64::FMLSv1i32_indexed: |
| 30168 | case AArch64::FMLSv1i64_indexed: |
| 30169 | case AArch64::FMLSv2i32_indexed: |
| 30170 | case AArch64::FMLSv2i64_indexed: |
| 30171 | case AArch64::FMLSv4i16_indexed: |
| 30172 | case AArch64::FMLSv4i32_indexed: |
| 30173 | case AArch64::FMLSv8i16_indexed: |
| 30174 | case AArch64::MLAv2i32_indexed: |
| 30175 | case AArch64::MLAv4i16_indexed: |
| 30176 | case AArch64::MLAv4i32_indexed: |
| 30177 | case AArch64::MLAv8i16_indexed: |
| 30178 | case AArch64::MLSv2i32_indexed: |
| 30179 | case AArch64::MLSv4i16_indexed: |
| 30180 | case AArch64::MLSv4i32_indexed: |
| 30181 | case AArch64::MLSv8i16_indexed: |
| 30182 | case AArch64::SDOTlanev16i8: |
| 30183 | case AArch64::SDOTlanev8i8: |
| 30184 | case AArch64::SMLALv2i32_indexed: |
| 30185 | case AArch64::SMLALv4i16_indexed: |
| 30186 | case AArch64::SMLALv4i32_indexed: |
| 30187 | case AArch64::SMLALv8i16_indexed: |
| 30188 | case AArch64::SMLSLv2i32_indexed: |
| 30189 | case AArch64::SMLSLv4i16_indexed: |
| 30190 | case AArch64::SMLSLv4i32_indexed: |
| 30191 | case AArch64::SMLSLv8i16_indexed: |
| 30192 | case AArch64::SQDMLALv1i32_indexed: |
| 30193 | case AArch64::SQDMLALv1i64_indexed: |
| 30194 | case AArch64::SQDMLALv2i32_indexed: |
| 30195 | case AArch64::SQDMLALv4i16_indexed: |
| 30196 | case AArch64::SQDMLALv4i32_indexed: |
| 30197 | case AArch64::SQDMLALv8i16_indexed: |
| 30198 | case AArch64::SQDMLSLv1i32_indexed: |
| 30199 | case AArch64::SQDMLSLv1i64_indexed: |
| 30200 | case AArch64::SQDMLSLv2i32_indexed: |
| 30201 | case AArch64::SQDMLSLv4i16_indexed: |
| 30202 | case AArch64::SQDMLSLv4i32_indexed: |
| 30203 | case AArch64::SQDMLSLv8i16_indexed: |
| 30204 | case AArch64::SQRDMLAHv1i16_indexed: |
| 30205 | case AArch64::SQRDMLAHv1i32_indexed: |
| 30206 | case AArch64::SQRDMLAHv2i32_indexed: |
| 30207 | case AArch64::SQRDMLAHv4i16_indexed: |
| 30208 | case AArch64::SQRDMLAHv4i32_indexed: |
| 30209 | case AArch64::SQRDMLAHv8i16_indexed: |
| 30210 | case AArch64::SQRDMLSHv1i16_indexed: |
| 30211 | case AArch64::SQRDMLSHv1i32_indexed: |
| 30212 | case AArch64::SQRDMLSHv2i32_indexed: |
| 30213 | case AArch64::SQRDMLSHv4i16_indexed: |
| 30214 | case AArch64::SQRDMLSHv4i32_indexed: |
| 30215 | case AArch64::SQRDMLSHv8i16_indexed: |
| 30216 | case AArch64::SUDOTlanev16i8: |
| 30217 | case AArch64::SUDOTlanev8i8: |
| 30218 | case AArch64::UDOTlanev16i8: |
| 30219 | case AArch64::UDOTlanev8i8: |
| 30220 | case AArch64::UMLALv2i32_indexed: |
| 30221 | case AArch64::UMLALv4i16_indexed: |
| 30222 | case AArch64::UMLALv4i32_indexed: |
| 30223 | case AArch64::UMLALv8i16_indexed: |
| 30224 | case AArch64::UMLSLv2i32_indexed: |
| 30225 | case AArch64::UMLSLv4i16_indexed: |
| 30226 | case AArch64::UMLSLv4i32_indexed: |
| 30227 | case AArch64::UMLSLv8i16_indexed: |
| 30228 | case AArch64::USDOTlanev16i8: |
| 30229 | case AArch64::USDOTlanev8i8: { |
| 30230 | switch (OpNum) { |
| 30231 | case 1: |
| 30232 | // op: Rd |
| 30233 | return 0; |
| 30234 | case 2: |
| 30235 | // op: Rn |
| 30236 | return 5; |
| 30237 | case 3: |
| 30238 | // op: Rm |
| 30239 | return 16; |
| 30240 | case 4: |
| 30241 | // op: idx |
| 30242 | return 11; |
| 30243 | } |
| 30244 | break; |
| 30245 | } |
| 30246 | case AArch64::FCMLAv2f32: |
| 30247 | case AArch64::FCMLAv2f64: |
| 30248 | case AArch64::FCMLAv4f16: |
| 30249 | case AArch64::FCMLAv4f32: |
| 30250 | case AArch64::FCMLAv8f16: { |
| 30251 | switch (OpNum) { |
| 30252 | case 1: |
| 30253 | // op: Rd |
| 30254 | return 0; |
| 30255 | case 2: |
| 30256 | // op: Rn |
| 30257 | return 5; |
| 30258 | case 3: |
| 30259 | // op: Rm |
| 30260 | return 16; |
| 30261 | case 4: |
| 30262 | // op: rot |
| 30263 | return 11; |
| 30264 | } |
| 30265 | break; |
| 30266 | } |
| 30267 | case AArch64::FCMLAv4f32_indexed: |
| 30268 | case AArch64::FCMLAv8f16_indexed: { |
| 30269 | switch (OpNum) { |
| 30270 | case 1: |
| 30271 | // op: Rd |
| 30272 | return 0; |
| 30273 | case 2: |
| 30274 | // op: Rn |
| 30275 | return 5; |
| 30276 | case 3: |
| 30277 | // op: Rm |
| 30278 | return 16; |
| 30279 | case 5: |
| 30280 | // op: rot |
| 30281 | return 13; |
| 30282 | case 4: |
| 30283 | // op: idx |
| 30284 | return 11; |
| 30285 | } |
| 30286 | break; |
| 30287 | } |
| 30288 | case AArch64::FCMLAv4f16_indexed: { |
| 30289 | switch (OpNum) { |
| 30290 | case 1: |
| 30291 | // op: Rd |
| 30292 | return 0; |
| 30293 | case 2: |
| 30294 | // op: Rn |
| 30295 | return 5; |
| 30296 | case 3: |
| 30297 | // op: Rm |
| 30298 | return 16; |
| 30299 | case 5: |
| 30300 | // op: rot |
| 30301 | return 13; |
| 30302 | case 4: |
| 30303 | // op: idx |
| 30304 | return 21; |
| 30305 | } |
| 30306 | break; |
| 30307 | } |
| 30308 | case AArch64::ADDHNv2i64_v4i32: |
| 30309 | case AArch64::ADDHNv4i32_v8i16: |
| 30310 | case AArch64::ADDHNv8i16_v16i8: |
| 30311 | case AArch64::BFDOTv4bf16: |
| 30312 | case AArch64::BFDOTv8bf16: |
| 30313 | case AArch64::BFMLALB: |
| 30314 | case AArch64::BFMLALT: |
| 30315 | case AArch64::BFMMLA: |
| 30316 | case AArch64::BIFv16i8: |
| 30317 | case AArch64::BIFv8i8: |
| 30318 | case AArch64::BITv16i8: |
| 30319 | case AArch64::BITv8i8: |
| 30320 | case AArch64::BSLv16i8: |
| 30321 | case AArch64::BSLv8i8: |
| 30322 | case AArch64::FCVTN_F322v16f8: |
| 30323 | case AArch64::FDOTv2f32: |
| 30324 | case AArch64::FDOTv4f16: |
| 30325 | case AArch64::FDOTv4f16_v2f32: |
| 30326 | case AArch64::FDOTv4f32: |
| 30327 | case AArch64::FDOTv8f16: |
| 30328 | case AArch64::FDOTv8f16_v4f32: |
| 30329 | case AArch64::FMLAL2v4f16: |
| 30330 | case AArch64::FMLAL2v8f16: |
| 30331 | case AArch64::FMLALBv16i8_v8f16: |
| 30332 | case AArch64::FMLALLBBv4f32: |
| 30333 | case AArch64::FMLALLBTv4f32: |
| 30334 | case AArch64::FMLALLTBv4f32: |
| 30335 | case AArch64::FMLALLTTv4f32: |
| 30336 | case AArch64::FMLALTv16i8_v8f16: |
| 30337 | case AArch64::FMLALv4f16: |
| 30338 | case AArch64::FMLALv8f16: |
| 30339 | case AArch64::FMLAv2f32: |
| 30340 | case AArch64::FMLAv2f64: |
| 30341 | case AArch64::FMLAv4f16: |
| 30342 | case AArch64::FMLAv4f32: |
| 30343 | case AArch64::FMLAv8f16: |
| 30344 | case AArch64::FMLSL2v4f16: |
| 30345 | case AArch64::FMLSL2v8f16: |
| 30346 | case AArch64::FMLSLv4f16: |
| 30347 | case AArch64::FMLSLv8f16: |
| 30348 | case AArch64::FMLSv2f32: |
| 30349 | case AArch64::FMLSv2f64: |
| 30350 | case AArch64::FMLSv4f16: |
| 30351 | case AArch64::FMLSv4f32: |
| 30352 | case AArch64::FMLSv8f16: |
| 30353 | case AArch64::FMMLAv4f32: |
| 30354 | case AArch64::FMMLAv8f16: |
| 30355 | case AArch64::FMMLAv8f16_v4f32: |
| 30356 | case AArch64::FMMLAv8f16_v8f16: |
| 30357 | case AArch64::MLAv16i8: |
| 30358 | case AArch64::MLAv2i32: |
| 30359 | case AArch64::MLAv4i16: |
| 30360 | case AArch64::MLAv4i32: |
| 30361 | case AArch64::MLAv8i16: |
| 30362 | case AArch64::MLAv8i8: |
| 30363 | case AArch64::MLSv16i8: |
| 30364 | case AArch64::MLSv2i32: |
| 30365 | case AArch64::MLSv4i16: |
| 30366 | case AArch64::MLSv4i32: |
| 30367 | case AArch64::MLSv8i16: |
| 30368 | case AArch64::MLSv8i8: |
| 30369 | case AArch64::RADDHNv2i64_v4i32: |
| 30370 | case AArch64::RADDHNv4i32_v8i16: |
| 30371 | case AArch64::RADDHNv8i16_v16i8: |
| 30372 | case AArch64::RSUBHNv2i64_v4i32: |
| 30373 | case AArch64::RSUBHNv4i32_v8i16: |
| 30374 | case AArch64::RSUBHNv8i16_v16i8: |
| 30375 | case AArch64::SABALv16i8_v8i16: |
| 30376 | case AArch64::SABALv2i32_v2i64: |
| 30377 | case AArch64::SABALv4i16_v4i32: |
| 30378 | case AArch64::SABALv4i32_v2i64: |
| 30379 | case AArch64::SABALv8i16_v4i32: |
| 30380 | case AArch64::SABALv8i8_v8i16: |
| 30381 | case AArch64::SABAv16i8: |
| 30382 | case AArch64::SABAv2i32: |
| 30383 | case AArch64::SABAv4i16: |
| 30384 | case AArch64::SABAv4i32: |
| 30385 | case AArch64::SABAv8i16: |
| 30386 | case AArch64::SABAv8i8: |
| 30387 | case AArch64::SDOTv16i8: |
| 30388 | case AArch64::SDOTv8i8: |
| 30389 | case AArch64::SHA1Crrr: |
| 30390 | case AArch64::SHA1Mrrr: |
| 30391 | case AArch64::SHA1Prrr: |
| 30392 | case AArch64::SHA1SU0rrr: |
| 30393 | case AArch64::SHA256H2rrr: |
| 30394 | case AArch64::SHA256Hrrr: |
| 30395 | case AArch64::SHA256SU1rrr: |
| 30396 | case AArch64::SMLALv16i8_v8i16: |
| 30397 | case AArch64::SMLALv2i32_v2i64: |
| 30398 | case AArch64::SMLALv4i16_v4i32: |
| 30399 | case AArch64::SMLALv4i32_v2i64: |
| 30400 | case AArch64::SMLALv8i16_v4i32: |
| 30401 | case AArch64::SMLALv8i8_v8i16: |
| 30402 | case AArch64::SMLSLv16i8_v8i16: |
| 30403 | case AArch64::SMLSLv2i32_v2i64: |
| 30404 | case AArch64::SMLSLv4i16_v4i32: |
| 30405 | case AArch64::SMLSLv4i32_v2i64: |
| 30406 | case AArch64::SMLSLv8i16_v4i32: |
| 30407 | case AArch64::SMLSLv8i8_v8i16: |
| 30408 | case AArch64::SMMLA: |
| 30409 | case AArch64::SQDMLALi16: |
| 30410 | case AArch64::SQDMLALi32: |
| 30411 | case AArch64::SQDMLALv2i32_v2i64: |
| 30412 | case AArch64::SQDMLALv4i16_v4i32: |
| 30413 | case AArch64::SQDMLALv4i32_v2i64: |
| 30414 | case AArch64::SQDMLALv8i16_v4i32: |
| 30415 | case AArch64::SQDMLSLi16: |
| 30416 | case AArch64::SQDMLSLi32: |
| 30417 | case AArch64::SQDMLSLv2i32_v2i64: |
| 30418 | case AArch64::SQDMLSLv4i16_v4i32: |
| 30419 | case AArch64::SQDMLSLv4i32_v2i64: |
| 30420 | case AArch64::SQDMLSLv8i16_v4i32: |
| 30421 | case AArch64::SQRDMLAHv1i16: |
| 30422 | case AArch64::SQRDMLAHv1i32: |
| 30423 | case AArch64::SQRDMLAHv2i32: |
| 30424 | case AArch64::SQRDMLAHv4i16: |
| 30425 | case AArch64::SQRDMLAHv4i32: |
| 30426 | case AArch64::SQRDMLAHv8i16: |
| 30427 | case AArch64::SQRDMLSHv1i16: |
| 30428 | case AArch64::SQRDMLSHv1i32: |
| 30429 | case AArch64::SQRDMLSHv2i32: |
| 30430 | case AArch64::SQRDMLSHv4i16: |
| 30431 | case AArch64::SQRDMLSHv4i32: |
| 30432 | case AArch64::SQRDMLSHv8i16: |
| 30433 | case AArch64::SUBHNv2i64_v4i32: |
| 30434 | case AArch64::SUBHNv4i32_v8i16: |
| 30435 | case AArch64::SUBHNv8i16_v16i8: |
| 30436 | case AArch64::UABALv16i8_v8i16: |
| 30437 | case AArch64::UABALv2i32_v2i64: |
| 30438 | case AArch64::UABALv4i16_v4i32: |
| 30439 | case AArch64::UABALv4i32_v2i64: |
| 30440 | case AArch64::UABALv8i16_v4i32: |
| 30441 | case AArch64::UABALv8i8_v8i16: |
| 30442 | case AArch64::UABAv16i8: |
| 30443 | case AArch64::UABAv2i32: |
| 30444 | case AArch64::UABAv4i16: |
| 30445 | case AArch64::UABAv4i32: |
| 30446 | case AArch64::UABAv8i16: |
| 30447 | case AArch64::UABAv8i8: |
| 30448 | case AArch64::UDOTv16i8: |
| 30449 | case AArch64::UDOTv8i8: |
| 30450 | case AArch64::UMLALv16i8_v8i16: |
| 30451 | case AArch64::UMLALv2i32_v2i64: |
| 30452 | case AArch64::UMLALv4i16_v4i32: |
| 30453 | case AArch64::UMLALv4i32_v2i64: |
| 30454 | case AArch64::UMLALv8i16_v4i32: |
| 30455 | case AArch64::UMLALv8i8_v8i16: |
| 30456 | case AArch64::UMLSLv16i8_v8i16: |
| 30457 | case AArch64::UMLSLv2i32_v2i64: |
| 30458 | case AArch64::UMLSLv4i16_v4i32: |
| 30459 | case AArch64::UMLSLv4i32_v2i64: |
| 30460 | case AArch64::UMLSLv8i16_v4i32: |
| 30461 | case AArch64::UMLSLv8i8_v8i16: |
| 30462 | case AArch64::UMMLA: |
| 30463 | case AArch64::USDOTv16i8: |
| 30464 | case AArch64::USDOTv8i8: |
| 30465 | case AArch64::USMMLA: { |
| 30466 | switch (OpNum) { |
| 30467 | case 1: |
| 30468 | // op: Rd |
| 30469 | return 0; |
| 30470 | case 2: |
| 30471 | // op: Rn |
| 30472 | return 5; |
| 30473 | case 3: |
| 30474 | // op: Rm |
| 30475 | return 16; |
| 30476 | } |
| 30477 | break; |
| 30478 | } |
| 30479 | case AArch64::RSHRNv16i8_shift: |
| 30480 | case AArch64::RSHRNv4i32_shift: |
| 30481 | case AArch64::RSHRNv8i16_shift: |
| 30482 | case AArch64::SHRNv16i8_shift: |
| 30483 | case AArch64::SHRNv4i32_shift: |
| 30484 | case AArch64::SHRNv8i16_shift: |
| 30485 | case AArch64::SLId: |
| 30486 | case AArch64::SLIv16i8_shift: |
| 30487 | case AArch64::SLIv2i32_shift: |
| 30488 | case AArch64::SLIv2i64_shift: |
| 30489 | case AArch64::SLIv4i16_shift: |
| 30490 | case AArch64::SLIv4i32_shift: |
| 30491 | case AArch64::SLIv8i16_shift: |
| 30492 | case AArch64::SLIv8i8_shift: |
| 30493 | case AArch64::SQRSHRNv16i8_shift: |
| 30494 | case AArch64::SQRSHRNv4i32_shift: |
| 30495 | case AArch64::SQRSHRNv8i16_shift: |
| 30496 | case AArch64::SQRSHRUNv16i8_shift: |
| 30497 | case AArch64::SQRSHRUNv4i32_shift: |
| 30498 | case AArch64::SQRSHRUNv8i16_shift: |
| 30499 | case AArch64::SQSHRNv16i8_shift: |
| 30500 | case AArch64::SQSHRNv4i32_shift: |
| 30501 | case AArch64::SQSHRNv8i16_shift: |
| 30502 | case AArch64::SQSHRUNv16i8_shift: |
| 30503 | case AArch64::SQSHRUNv4i32_shift: |
| 30504 | case AArch64::SQSHRUNv8i16_shift: |
| 30505 | case AArch64::SRId: |
| 30506 | case AArch64::SRIv16i8_shift: |
| 30507 | case AArch64::SRIv2i32_shift: |
| 30508 | case AArch64::SRIv2i64_shift: |
| 30509 | case AArch64::SRIv4i16_shift: |
| 30510 | case AArch64::SRIv4i32_shift: |
| 30511 | case AArch64::SRIv8i16_shift: |
| 30512 | case AArch64::SRIv8i8_shift: |
| 30513 | case AArch64::SRSRAd: |
| 30514 | case AArch64::SRSRAv16i8_shift: |
| 30515 | case AArch64::SRSRAv2i32_shift: |
| 30516 | case AArch64::SRSRAv2i64_shift: |
| 30517 | case AArch64::SRSRAv4i16_shift: |
| 30518 | case AArch64::SRSRAv4i32_shift: |
| 30519 | case AArch64::SRSRAv8i16_shift: |
| 30520 | case AArch64::SRSRAv8i8_shift: |
| 30521 | case AArch64::SSRAd: |
| 30522 | case AArch64::SSRAv16i8_shift: |
| 30523 | case AArch64::SSRAv2i32_shift: |
| 30524 | case AArch64::SSRAv2i64_shift: |
| 30525 | case AArch64::SSRAv4i16_shift: |
| 30526 | case AArch64::SSRAv4i32_shift: |
| 30527 | case AArch64::SSRAv8i16_shift: |
| 30528 | case AArch64::SSRAv8i8_shift: |
| 30529 | case AArch64::UQRSHRNv16i8_shift: |
| 30530 | case AArch64::UQRSHRNv4i32_shift: |
| 30531 | case AArch64::UQRSHRNv8i16_shift: |
| 30532 | case AArch64::UQSHRNv16i8_shift: |
| 30533 | case AArch64::UQSHRNv4i32_shift: |
| 30534 | case AArch64::UQSHRNv8i16_shift: |
| 30535 | case AArch64::URSRAd: |
| 30536 | case AArch64::URSRAv16i8_shift: |
| 30537 | case AArch64::URSRAv2i32_shift: |
| 30538 | case AArch64::URSRAv2i64_shift: |
| 30539 | case AArch64::URSRAv4i16_shift: |
| 30540 | case AArch64::URSRAv4i32_shift: |
| 30541 | case AArch64::URSRAv8i16_shift: |
| 30542 | case AArch64::URSRAv8i8_shift: |
| 30543 | case AArch64::USRAd: |
| 30544 | case AArch64::USRAv16i8_shift: |
| 30545 | case AArch64::USRAv2i32_shift: |
| 30546 | case AArch64::USRAv2i64_shift: |
| 30547 | case AArch64::USRAv4i16_shift: |
| 30548 | case AArch64::USRAv4i32_shift: |
| 30549 | case AArch64::USRAv8i16_shift: |
| 30550 | case AArch64::USRAv8i8_shift: { |
| 30551 | switch (OpNum) { |
| 30552 | case 1: |
| 30553 | // op: Rd |
| 30554 | return 0; |
| 30555 | case 2: |
| 30556 | // op: Rn |
| 30557 | return 5; |
| 30558 | case 3: |
| 30559 | // op: imm |
| 30560 | return 16; |
| 30561 | } |
| 30562 | break; |
| 30563 | } |
| 30564 | case AArch64::AESDrr: |
| 30565 | case AArch64::AESErr: |
| 30566 | case AArch64::AUTDA: |
| 30567 | case AArch64::AUTDB: |
| 30568 | case AArch64::AUTIA: |
| 30569 | case AArch64::AUTIB: |
| 30570 | case AArch64::BFCVTN2: |
| 30571 | case AArch64::FCVTNv4i32: |
| 30572 | case AArch64::FCVTNv8i16: |
| 30573 | case AArch64::FCVTXNv4f32: |
| 30574 | case AArch64::PACDA: |
| 30575 | case AArch64::PACDB: |
| 30576 | case AArch64::PACIA: |
| 30577 | case AArch64::PACIB: |
| 30578 | case AArch64::SADALPv16i8_v8i16: |
| 30579 | case AArch64::SADALPv2i32_v1i64: |
| 30580 | case AArch64::SADALPv4i16_v2i32: |
| 30581 | case AArch64::SADALPv4i32_v2i64: |
| 30582 | case AArch64::SADALPv8i16_v4i32: |
| 30583 | case AArch64::SADALPv8i8_v4i16: |
| 30584 | case AArch64::SHA1SU1rr: |
| 30585 | case AArch64::SHA256SU0rr: |
| 30586 | case AArch64::SQXTNv16i8: |
| 30587 | case AArch64::SQXTNv4i32: |
| 30588 | case AArch64::SQXTNv8i16: |
| 30589 | case AArch64::SQXTUNv16i8: |
| 30590 | case AArch64::SQXTUNv4i32: |
| 30591 | case AArch64::SQXTUNv8i16: |
| 30592 | case AArch64::SUQADDv16i8: |
| 30593 | case AArch64::SUQADDv1i16: |
| 30594 | case AArch64::SUQADDv1i32: |
| 30595 | case AArch64::SUQADDv1i64: |
| 30596 | case AArch64::SUQADDv1i8: |
| 30597 | case AArch64::SUQADDv2i32: |
| 30598 | case AArch64::SUQADDv2i64: |
| 30599 | case AArch64::SUQADDv4i16: |
| 30600 | case AArch64::SUQADDv4i32: |
| 30601 | case AArch64::SUQADDv8i16: |
| 30602 | case AArch64::SUQADDv8i8: |
| 30603 | case AArch64::UADALPv16i8_v8i16: |
| 30604 | case AArch64::UADALPv2i32_v1i64: |
| 30605 | case AArch64::UADALPv4i16_v2i32: |
| 30606 | case AArch64::UADALPv4i32_v2i64: |
| 30607 | case AArch64::UADALPv8i16_v4i32: |
| 30608 | case AArch64::UADALPv8i8_v4i16: |
| 30609 | case AArch64::UQXTNv16i8: |
| 30610 | case AArch64::UQXTNv4i32: |
| 30611 | case AArch64::UQXTNv8i16: |
| 30612 | case AArch64::USQADDv16i8: |
| 30613 | case AArch64::USQADDv1i16: |
| 30614 | case AArch64::USQADDv1i32: |
| 30615 | case AArch64::USQADDv1i64: |
| 30616 | case AArch64::USQADDv1i8: |
| 30617 | case AArch64::USQADDv2i32: |
| 30618 | case AArch64::USQADDv2i64: |
| 30619 | case AArch64::USQADDv4i16: |
| 30620 | case AArch64::USQADDv4i32: |
| 30621 | case AArch64::USQADDv8i16: |
| 30622 | case AArch64::USQADDv8i8: |
| 30623 | case AArch64::XTNv16i8: |
| 30624 | case AArch64::XTNv4i32: |
| 30625 | case AArch64::XTNv8i16: { |
| 30626 | switch (OpNum) { |
| 30627 | case 1: |
| 30628 | // op: Rd |
| 30629 | return 0; |
| 30630 | case 2: |
| 30631 | // op: Rn |
| 30632 | return 5; |
| 30633 | } |
| 30634 | break; |
| 30635 | } |
| 30636 | case AArch64::BICv2i32: |
| 30637 | case AArch64::BICv4i16: |
| 30638 | case AArch64::BICv4i32: |
| 30639 | case AArch64::BICv8i16: |
| 30640 | case AArch64::ORRv2i32: |
| 30641 | case AArch64::ORRv4i16: |
| 30642 | case AArch64::ORRv4i32: |
| 30643 | case AArch64::ORRv8i16: { |
| 30644 | switch (OpNum) { |
| 30645 | case 1: |
| 30646 | // op: Rd |
| 30647 | return 0; |
| 30648 | case 2: |
| 30649 | // op: imm8 |
| 30650 | return 5; |
| 30651 | case 3: |
| 30652 | // op: shift |
| 30653 | return 13; |
| 30654 | } |
| 30655 | break; |
| 30656 | } |
| 30657 | case AArch64::INSvi8lane: { |
| 30658 | switch (OpNum) { |
| 30659 | case 1: |
| 30660 | // op: Rd |
| 30661 | return 0; |
| 30662 | case 3: |
| 30663 | // op: Rn |
| 30664 | return 5; |
| 30665 | case 2: |
| 30666 | // op: idx |
| 30667 | return 17; |
| 30668 | case 4: |
| 30669 | // op: idx2 |
| 30670 | return 11; |
| 30671 | } |
| 30672 | break; |
| 30673 | } |
| 30674 | case AArch64::INSvi8gpr: { |
| 30675 | switch (OpNum) { |
| 30676 | case 1: |
| 30677 | // op: Rd |
| 30678 | return 0; |
| 30679 | case 3: |
| 30680 | // op: Rn |
| 30681 | return 5; |
| 30682 | case 2: |
| 30683 | // op: idx |
| 30684 | return 17; |
| 30685 | } |
| 30686 | break; |
| 30687 | } |
| 30688 | case AArch64::INSvi16lane: { |
| 30689 | switch (OpNum) { |
| 30690 | case 1: |
| 30691 | // op: Rd |
| 30692 | return 0; |
| 30693 | case 3: |
| 30694 | // op: Rn |
| 30695 | return 5; |
| 30696 | case 2: |
| 30697 | // op: idx |
| 30698 | return 18; |
| 30699 | case 4: |
| 30700 | // op: idx2 |
| 30701 | return 12; |
| 30702 | } |
| 30703 | break; |
| 30704 | } |
| 30705 | case AArch64::INSvi16gpr: { |
| 30706 | switch (OpNum) { |
| 30707 | case 1: |
| 30708 | // op: Rd |
| 30709 | return 0; |
| 30710 | case 3: |
| 30711 | // op: Rn |
| 30712 | return 5; |
| 30713 | case 2: |
| 30714 | // op: idx |
| 30715 | return 18; |
| 30716 | } |
| 30717 | break; |
| 30718 | } |
| 30719 | case AArch64::INSvi32lane: { |
| 30720 | switch (OpNum) { |
| 30721 | case 1: |
| 30722 | // op: Rd |
| 30723 | return 0; |
| 30724 | case 3: |
| 30725 | // op: Rn |
| 30726 | return 5; |
| 30727 | case 2: |
| 30728 | // op: idx |
| 30729 | return 19; |
| 30730 | case 4: |
| 30731 | // op: idx2 |
| 30732 | return 13; |
| 30733 | } |
| 30734 | break; |
| 30735 | } |
| 30736 | case AArch64::INSvi32gpr: { |
| 30737 | switch (OpNum) { |
| 30738 | case 1: |
| 30739 | // op: Rd |
| 30740 | return 0; |
| 30741 | case 3: |
| 30742 | // op: Rn |
| 30743 | return 5; |
| 30744 | case 2: |
| 30745 | // op: idx |
| 30746 | return 19; |
| 30747 | } |
| 30748 | break; |
| 30749 | } |
| 30750 | case AArch64::INSvi64lane: { |
| 30751 | switch (OpNum) { |
| 30752 | case 1: |
| 30753 | // op: Rd |
| 30754 | return 0; |
| 30755 | case 3: |
| 30756 | // op: Rn |
| 30757 | return 5; |
| 30758 | case 2: |
| 30759 | // op: idx |
| 30760 | return 20; |
| 30761 | case 4: |
| 30762 | // op: idx2 |
| 30763 | return 14; |
| 30764 | } |
| 30765 | break; |
| 30766 | } |
| 30767 | case AArch64::INSvi64gpr: { |
| 30768 | switch (OpNum) { |
| 30769 | case 1: |
| 30770 | // op: Rd |
| 30771 | return 0; |
| 30772 | case 3: |
| 30773 | // op: Rn |
| 30774 | return 5; |
| 30775 | case 2: |
| 30776 | // op: idx |
| 30777 | return 20; |
| 30778 | } |
| 30779 | break; |
| 30780 | } |
| 30781 | case AArch64::AUTDZA: |
| 30782 | case AArch64::AUTDZB: |
| 30783 | case AArch64::AUTIZA: |
| 30784 | case AArch64::AUTIZB: |
| 30785 | case AArch64::PACDZA: |
| 30786 | case AArch64::PACDZB: |
| 30787 | case AArch64::PACIZA: |
| 30788 | case AArch64::PACIZB: { |
| 30789 | switch (OpNum) { |
| 30790 | case 1: |
| 30791 | // op: Rd |
| 30792 | return 0; |
| 30793 | } |
| 30794 | break; |
| 30795 | } |
| 30796 | case AArch64::CTERMEQ_WW: |
| 30797 | case AArch64::CTERMEQ_XX: |
| 30798 | case AArch64::CTERMNE_WW: |
| 30799 | case AArch64::CTERMNE_XX: |
| 30800 | case AArch64::FCMPDrr: |
| 30801 | case AArch64::FCMPEDrr: |
| 30802 | case AArch64::FCMPEHrr: |
| 30803 | case AArch64::FCMPESrr: |
| 30804 | case AArch64::FCMPHrr: |
| 30805 | case AArch64::FCMPSrr: { |
| 30806 | switch (OpNum) { |
| 30807 | case 1: |
| 30808 | // op: Rm |
| 30809 | return 16; |
| 30810 | case 0: |
| 30811 | // op: Rn |
| 30812 | return 5; |
| 30813 | } |
| 30814 | break; |
| 30815 | } |
| 30816 | case AArch64::CBBEQWrr: |
| 30817 | case AArch64::CBBGEWrr: |
| 30818 | case AArch64::CBBGTWrr: |
| 30819 | case AArch64::CBBHIWrr: |
| 30820 | case AArch64::CBBHSWrr: |
| 30821 | case AArch64::CBBNEWrr: |
| 30822 | case AArch64::CBEQWrr: |
| 30823 | case AArch64::CBEQXrr: |
| 30824 | case AArch64::CBGEWrr: |
| 30825 | case AArch64::CBGEXrr: |
| 30826 | case AArch64::CBGTWrr: |
| 30827 | case AArch64::CBGTXrr: |
| 30828 | case AArch64::CBHEQWrr: |
| 30829 | case AArch64::CBHGEWrr: |
| 30830 | case AArch64::CBHGTWrr: |
| 30831 | case AArch64::CBHHIWrr: |
| 30832 | case AArch64::CBHHSWrr: |
| 30833 | case AArch64::CBHIWrr: |
| 30834 | case AArch64::CBHIXrr: |
| 30835 | case AArch64::CBHNEWrr: |
| 30836 | case AArch64::CBHSWrr: |
| 30837 | case AArch64::CBHSXrr: |
| 30838 | case AArch64::CBNEWrr: |
| 30839 | case AArch64::CBNEXrr: { |
| 30840 | switch (OpNum) { |
| 30841 | case 1: |
| 30842 | // op: Rm |
| 30843 | return 16; |
| 30844 | case 0: |
| 30845 | // op: Rt |
| 30846 | return 0; |
| 30847 | case 2: |
| 30848 | // op: target |
| 30849 | return 5; |
| 30850 | } |
| 30851 | break; |
| 30852 | } |
| 30853 | case AArch64::ST2Gi: |
| 30854 | case AArch64::STGi: |
| 30855 | case AArch64::STZ2Gi: |
| 30856 | case AArch64::STZGi: { |
| 30857 | switch (OpNum) { |
| 30858 | case 1: |
| 30859 | // op: Rn |
| 30860 | return 5; |
| 30861 | case 0: |
| 30862 | // op: Rt |
| 30863 | return 0; |
| 30864 | case 2: |
| 30865 | // op: offset |
| 30866 | return 12; |
| 30867 | } |
| 30868 | break; |
| 30869 | } |
| 30870 | case AArch64::LDAPRB: |
| 30871 | case AArch64::LDAPRH: |
| 30872 | case AArch64::LDAPRW: |
| 30873 | case AArch64::LDAPRX: |
| 30874 | case AArch64::LDGM: |
| 30875 | case AArch64::STGM: |
| 30876 | case AArch64::STZGM: { |
| 30877 | switch (OpNum) { |
| 30878 | case 1: |
| 30879 | // op: Rn |
| 30880 | return 5; |
| 30881 | case 0: |
| 30882 | // op: Rt |
| 30883 | return 0; |
| 30884 | } |
| 30885 | break; |
| 30886 | } |
| 30887 | case AArch64::INDEX_RI_B: |
| 30888 | case AArch64::INDEX_RI_D: |
| 30889 | case AArch64::INDEX_RI_H: |
| 30890 | case AArch64::INDEX_RI_S: { |
| 30891 | switch (OpNum) { |
| 30892 | case 1: |
| 30893 | // op: Rn |
| 30894 | return 5; |
| 30895 | case 0: |
| 30896 | // op: Zd |
| 30897 | return 0; |
| 30898 | case 2: |
| 30899 | // op: imm5 |
| 30900 | return 16; |
| 30901 | } |
| 30902 | break; |
| 30903 | } |
| 30904 | case AArch64::DUP_ZR_B: |
| 30905 | case AArch64::DUP_ZR_D: |
| 30906 | case AArch64::DUP_ZR_H: |
| 30907 | case AArch64::DUP_ZR_S: { |
| 30908 | switch (OpNum) { |
| 30909 | case 1: |
| 30910 | // op: Rn |
| 30911 | return 5; |
| 30912 | case 0: |
| 30913 | // op: Zd |
| 30914 | return 0; |
| 30915 | } |
| 30916 | break; |
| 30917 | } |
| 30918 | case AArch64::LDR_ZXI: |
| 30919 | case AArch64::STR_ZXI: { |
| 30920 | switch (OpNum) { |
| 30921 | case 1: |
| 30922 | // op: Rn |
| 30923 | return 5; |
| 30924 | case 0: |
| 30925 | // op: Zt |
| 30926 | return 0; |
| 30927 | case 2: |
| 30928 | // op: imm9 |
| 30929 | return 10; |
| 30930 | } |
| 30931 | break; |
| 30932 | } |
| 30933 | case AArch64::LDR_TX: |
| 30934 | case AArch64::STR_TX: { |
| 30935 | switch (OpNum) { |
| 30936 | case 1: |
| 30937 | // op: Rn |
| 30938 | return 5; |
| 30939 | } |
| 30940 | break; |
| 30941 | } |
| 30942 | case AArch64::LDADDAB: |
| 30943 | case AArch64::LDADDAH: |
| 30944 | case AArch64::LDADDALB: |
| 30945 | case AArch64::LDADDALH: |
| 30946 | case AArch64::LDADDALW: |
| 30947 | case AArch64::LDADDALX: |
| 30948 | case AArch64::LDADDAW: |
| 30949 | case AArch64::LDADDAX: |
| 30950 | case AArch64::LDADDB: |
| 30951 | case AArch64::LDADDH: |
| 30952 | case AArch64::LDADDLB: |
| 30953 | case AArch64::LDADDLH: |
| 30954 | case AArch64::LDADDLW: |
| 30955 | case AArch64::LDADDLX: |
| 30956 | case AArch64::LDADDW: |
| 30957 | case AArch64::LDADDX: |
| 30958 | case AArch64::LDCLRAB: |
| 30959 | case AArch64::LDCLRAH: |
| 30960 | case AArch64::LDCLRALB: |
| 30961 | case AArch64::LDCLRALH: |
| 30962 | case AArch64::LDCLRALW: |
| 30963 | case AArch64::LDCLRALX: |
| 30964 | case AArch64::LDCLRAW: |
| 30965 | case AArch64::LDCLRAX: |
| 30966 | case AArch64::LDCLRB: |
| 30967 | case AArch64::LDCLRH: |
| 30968 | case AArch64::LDCLRLB: |
| 30969 | case AArch64::LDCLRLH: |
| 30970 | case AArch64::LDCLRLW: |
| 30971 | case AArch64::LDCLRLX: |
| 30972 | case AArch64::LDCLRW: |
| 30973 | case AArch64::LDCLRX: |
| 30974 | case AArch64::LDEORAB: |
| 30975 | case AArch64::LDEORAH: |
| 30976 | case AArch64::LDEORALB: |
| 30977 | case AArch64::LDEORALH: |
| 30978 | case AArch64::LDEORALW: |
| 30979 | case AArch64::LDEORALX: |
| 30980 | case AArch64::LDEORAW: |
| 30981 | case AArch64::LDEORAX: |
| 30982 | case AArch64::LDEORB: |
| 30983 | case AArch64::LDEORH: |
| 30984 | case AArch64::LDEORLB: |
| 30985 | case AArch64::LDEORLH: |
| 30986 | case AArch64::LDEORLW: |
| 30987 | case AArch64::LDEORLX: |
| 30988 | case AArch64::LDEORW: |
| 30989 | case AArch64::LDEORX: |
| 30990 | case AArch64::LDSETAB: |
| 30991 | case AArch64::LDSETAH: |
| 30992 | case AArch64::LDSETALB: |
| 30993 | case AArch64::LDSETALH: |
| 30994 | case AArch64::LDSETALW: |
| 30995 | case AArch64::LDSETALX: |
| 30996 | case AArch64::LDSETAW: |
| 30997 | case AArch64::LDSETAX: |
| 30998 | case AArch64::LDSETB: |
| 30999 | case AArch64::LDSETH: |
| 31000 | case AArch64::LDSETLB: |
| 31001 | case AArch64::LDSETLH: |
| 31002 | case AArch64::LDSETLW: |
| 31003 | case AArch64::LDSETLX: |
| 31004 | case AArch64::LDSETW: |
| 31005 | case AArch64::LDSETX: |
| 31006 | case AArch64::LDSMAXAB: |
| 31007 | case AArch64::LDSMAXAH: |
| 31008 | case AArch64::LDSMAXALB: |
| 31009 | case AArch64::LDSMAXALH: |
| 31010 | case AArch64::LDSMAXALW: |
| 31011 | case AArch64::LDSMAXALX: |
| 31012 | case AArch64::LDSMAXAW: |
| 31013 | case AArch64::LDSMAXAX: |
| 31014 | case AArch64::LDSMAXB: |
| 31015 | case AArch64::LDSMAXH: |
| 31016 | case AArch64::LDSMAXLB: |
| 31017 | case AArch64::LDSMAXLH: |
| 31018 | case AArch64::LDSMAXLW: |
| 31019 | case AArch64::LDSMAXLX: |
| 31020 | case AArch64::LDSMAXW: |
| 31021 | case AArch64::LDSMAXX: |
| 31022 | case AArch64::LDSMINAB: |
| 31023 | case AArch64::LDSMINAH: |
| 31024 | case AArch64::LDSMINALB: |
| 31025 | case AArch64::LDSMINALH: |
| 31026 | case AArch64::LDSMINALW: |
| 31027 | case AArch64::LDSMINALX: |
| 31028 | case AArch64::LDSMINAW: |
| 31029 | case AArch64::LDSMINAX: |
| 31030 | case AArch64::LDSMINB: |
| 31031 | case AArch64::LDSMINH: |
| 31032 | case AArch64::LDSMINLB: |
| 31033 | case AArch64::LDSMINLH: |
| 31034 | case AArch64::LDSMINLW: |
| 31035 | case AArch64::LDSMINLX: |
| 31036 | case AArch64::LDSMINW: |
| 31037 | case AArch64::LDSMINX: |
| 31038 | case AArch64::LDTADDALW: |
| 31039 | case AArch64::LDTADDALX: |
| 31040 | case AArch64::LDTADDAW: |
| 31041 | case AArch64::LDTADDAX: |
| 31042 | case AArch64::LDTADDLW: |
| 31043 | case AArch64::LDTADDLX: |
| 31044 | case AArch64::LDTADDW: |
| 31045 | case AArch64::LDTADDX: |
| 31046 | case AArch64::LDTCLRALW: |
| 31047 | case AArch64::LDTCLRALX: |
| 31048 | case AArch64::LDTCLRAW: |
| 31049 | case AArch64::LDTCLRAX: |
| 31050 | case AArch64::LDTCLRLW: |
| 31051 | case AArch64::LDTCLRLX: |
| 31052 | case AArch64::LDTCLRW: |
| 31053 | case AArch64::LDTCLRX: |
| 31054 | case AArch64::LDTSETALW: |
| 31055 | case AArch64::LDTSETALX: |
| 31056 | case AArch64::LDTSETAW: |
| 31057 | case AArch64::LDTSETAX: |
| 31058 | case AArch64::LDTSETLW: |
| 31059 | case AArch64::LDTSETLX: |
| 31060 | case AArch64::LDTSETW: |
| 31061 | case AArch64::LDTSETX: |
| 31062 | case AArch64::LDUMAXAB: |
| 31063 | case AArch64::LDUMAXAH: |
| 31064 | case AArch64::LDUMAXALB: |
| 31065 | case AArch64::LDUMAXALH: |
| 31066 | case AArch64::LDUMAXALW: |
| 31067 | case AArch64::LDUMAXALX: |
| 31068 | case AArch64::LDUMAXAW: |
| 31069 | case AArch64::LDUMAXAX: |
| 31070 | case AArch64::LDUMAXB: |
| 31071 | case AArch64::LDUMAXH: |
| 31072 | case AArch64::LDUMAXLB: |
| 31073 | case AArch64::LDUMAXLH: |
| 31074 | case AArch64::LDUMAXLW: |
| 31075 | case AArch64::LDUMAXLX: |
| 31076 | case AArch64::LDUMAXW: |
| 31077 | case AArch64::LDUMAXX: |
| 31078 | case AArch64::LDUMINAB: |
| 31079 | case AArch64::LDUMINAH: |
| 31080 | case AArch64::LDUMINALB: |
| 31081 | case AArch64::LDUMINALH: |
| 31082 | case AArch64::LDUMINALW: |
| 31083 | case AArch64::LDUMINALX: |
| 31084 | case AArch64::LDUMINAW: |
| 31085 | case AArch64::LDUMINAX: |
| 31086 | case AArch64::LDUMINB: |
| 31087 | case AArch64::LDUMINH: |
| 31088 | case AArch64::LDUMINLB: |
| 31089 | case AArch64::LDUMINLH: |
| 31090 | case AArch64::LDUMINLW: |
| 31091 | case AArch64::LDUMINLX: |
| 31092 | case AArch64::LDUMINW: |
| 31093 | case AArch64::LDUMINX: |
| 31094 | case AArch64::RCWCLR: |
| 31095 | case AArch64::RCWCLRA: |
| 31096 | case AArch64::RCWCLRAL: |
| 31097 | case AArch64::RCWCLRL: |
| 31098 | case AArch64::RCWCLRS: |
| 31099 | case AArch64::RCWCLRSA: |
| 31100 | case AArch64::RCWCLRSAL: |
| 31101 | case AArch64::RCWCLRSL: |
| 31102 | case AArch64::RCWSET: |
| 31103 | case AArch64::RCWSETA: |
| 31104 | case AArch64::RCWSETAL: |
| 31105 | case AArch64::RCWSETL: |
| 31106 | case AArch64::RCWSETS: |
| 31107 | case AArch64::RCWSETSA: |
| 31108 | case AArch64::RCWSETSAL: |
| 31109 | case AArch64::RCWSETSL: |
| 31110 | case AArch64::RCWSWP: |
| 31111 | case AArch64::RCWSWPA: |
| 31112 | case AArch64::RCWSWPAL: |
| 31113 | case AArch64::RCWSWPL: |
| 31114 | case AArch64::RCWSWPS: |
| 31115 | case AArch64::RCWSWPSA: |
| 31116 | case AArch64::RCWSWPSAL: |
| 31117 | case AArch64::RCWSWPSL: |
| 31118 | case AArch64::SWPAB: |
| 31119 | case AArch64::SWPAH: |
| 31120 | case AArch64::SWPALB: |
| 31121 | case AArch64::SWPALH: |
| 31122 | case AArch64::SWPALW: |
| 31123 | case AArch64::SWPALX: |
| 31124 | case AArch64::SWPAW: |
| 31125 | case AArch64::SWPAX: |
| 31126 | case AArch64::SWPB: |
| 31127 | case AArch64::SWPH: |
| 31128 | case AArch64::SWPLB: |
| 31129 | case AArch64::SWPLH: |
| 31130 | case AArch64::SWPLW: |
| 31131 | case AArch64::SWPLX: |
| 31132 | case AArch64::SWPTALW: |
| 31133 | case AArch64::SWPTALX: |
| 31134 | case AArch64::SWPTAW: |
| 31135 | case AArch64::SWPTAX: |
| 31136 | case AArch64::SWPTLW: |
| 31137 | case AArch64::SWPTLX: |
| 31138 | case AArch64::SWPTW: |
| 31139 | case AArch64::SWPTX: |
| 31140 | case AArch64::SWPW: |
| 31141 | case AArch64::SWPX: { |
| 31142 | switch (OpNum) { |
| 31143 | case 1: |
| 31144 | // op: Rs |
| 31145 | return 16; |
| 31146 | case 2: |
| 31147 | // op: Rn |
| 31148 | return 5; |
| 31149 | case 0: |
| 31150 | // op: Rt |
| 31151 | return 0; |
| 31152 | } |
| 31153 | break; |
| 31154 | } |
| 31155 | case AArch64::CASAB: |
| 31156 | case AArch64::CASAH: |
| 31157 | case AArch64::CASALB: |
| 31158 | case AArch64::CASALH: |
| 31159 | case AArch64::CASALTX: |
| 31160 | case AArch64::CASALW: |
| 31161 | case AArch64::CASALX: |
| 31162 | case AArch64::CASATX: |
| 31163 | case AArch64::CASAW: |
| 31164 | case AArch64::CASAX: |
| 31165 | case AArch64::CASB: |
| 31166 | case AArch64::CASH: |
| 31167 | case AArch64::CASLB: |
| 31168 | case AArch64::CASLH: |
| 31169 | case AArch64::CASLTX: |
| 31170 | case AArch64::CASLW: |
| 31171 | case AArch64::CASLX: |
| 31172 | case AArch64::CASPALTX: |
| 31173 | case AArch64::CASPALW: |
| 31174 | case AArch64::CASPALX: |
| 31175 | case AArch64::CASPATX: |
| 31176 | case AArch64::CASPAW: |
| 31177 | case AArch64::CASPAX: |
| 31178 | case AArch64::CASPLTX: |
| 31179 | case AArch64::CASPLW: |
| 31180 | case AArch64::CASPLX: |
| 31181 | case AArch64::CASPTX: |
| 31182 | case AArch64::CASPW: |
| 31183 | case AArch64::CASPX: |
| 31184 | case AArch64::CASTX: |
| 31185 | case AArch64::CASW: |
| 31186 | case AArch64::CASX: |
| 31187 | case AArch64::RCWCAS: |
| 31188 | case AArch64::RCWCASA: |
| 31189 | case AArch64::RCWCASAL: |
| 31190 | case AArch64::RCWCASL: |
| 31191 | case AArch64::RCWCASP: |
| 31192 | case AArch64::RCWCASPA: |
| 31193 | case AArch64::RCWCASPAL: |
| 31194 | case AArch64::RCWCASPL: |
| 31195 | case AArch64::RCWSCAS: |
| 31196 | case AArch64::RCWSCASA: |
| 31197 | case AArch64::RCWSCASAL: |
| 31198 | case AArch64::RCWSCASL: |
| 31199 | case AArch64::RCWSCASP: |
| 31200 | case AArch64::RCWSCASPA: |
| 31201 | case AArch64::RCWSCASPAL: |
| 31202 | case AArch64::RCWSCASPL: { |
| 31203 | switch (OpNum) { |
| 31204 | case 1: |
| 31205 | // op: Rs |
| 31206 | return 16; |
| 31207 | case 3: |
| 31208 | // op: Rn |
| 31209 | return 5; |
| 31210 | case 2: |
| 31211 | // op: Rt |
| 31212 | return 0; |
| 31213 | } |
| 31214 | break; |
| 31215 | } |
| 31216 | case AArch64::MSR: |
| 31217 | case AArch64::MSRR: { |
| 31218 | switch (OpNum) { |
| 31219 | case 1: |
| 31220 | // op: Rt |
| 31221 | return 0; |
| 31222 | case 0: |
| 31223 | // op: systemreg |
| 31224 | return 5; |
| 31225 | } |
| 31226 | break; |
| 31227 | } |
| 31228 | case AArch64::ST64BV: |
| 31229 | case AArch64::ST64BV0: |
| 31230 | case AArch64::STL64BV: |
| 31231 | case AArch64::STL64BV0: { |
| 31232 | switch (OpNum) { |
| 31233 | case 1: |
| 31234 | // op: Rt |
| 31235 | return 0; |
| 31236 | case 2: |
| 31237 | // op: Rn |
| 31238 | return 5; |
| 31239 | case 0: |
| 31240 | // op: Rs |
| 31241 | return 16; |
| 31242 | } |
| 31243 | break; |
| 31244 | } |
| 31245 | case AArch64::STTXRWr: |
| 31246 | case AArch64::STTXRXr: { |
| 31247 | switch (OpNum) { |
| 31248 | case 1: |
| 31249 | // op: Rt |
| 31250 | return 0; |
| 31251 | case 2: |
| 31252 | // op: Rn |
| 31253 | return 5; |
| 31254 | case 0: |
| 31255 | // op: Ws |
| 31256 | return 16; |
| 31257 | } |
| 31258 | break; |
| 31259 | } |
| 31260 | case AArch64::LDRBBpost: |
| 31261 | case AArch64::LDRBBpre: |
| 31262 | case AArch64::LDRBpost: |
| 31263 | case AArch64::LDRBpre: |
| 31264 | case AArch64::LDRDpost: |
| 31265 | case AArch64::LDRDpre: |
| 31266 | case AArch64::LDRHHpost: |
| 31267 | case AArch64::LDRHHpre: |
| 31268 | case AArch64::LDRHpost: |
| 31269 | case AArch64::LDRHpre: |
| 31270 | case AArch64::LDRQpost: |
| 31271 | case AArch64::LDRQpre: |
| 31272 | case AArch64::LDRSBWpost: |
| 31273 | case AArch64::LDRSBWpre: |
| 31274 | case AArch64::LDRSBXpost: |
| 31275 | case AArch64::LDRSBXpre: |
| 31276 | case AArch64::LDRSHWpost: |
| 31277 | case AArch64::LDRSHWpre: |
| 31278 | case AArch64::LDRSHXpost: |
| 31279 | case AArch64::LDRSHXpre: |
| 31280 | case AArch64::LDRSWpost: |
| 31281 | case AArch64::LDRSWpre: |
| 31282 | case AArch64::LDRSpost: |
| 31283 | case AArch64::LDRSpre: |
| 31284 | case AArch64::LDRWpost: |
| 31285 | case AArch64::LDRWpre: |
| 31286 | case AArch64::LDRXpost: |
| 31287 | case AArch64::LDRXpre: |
| 31288 | case AArch64::STRBBpost: |
| 31289 | case AArch64::STRBBpre: |
| 31290 | case AArch64::STRBpost: |
| 31291 | case AArch64::STRBpre: |
| 31292 | case AArch64::STRDpost: |
| 31293 | case AArch64::STRDpre: |
| 31294 | case AArch64::STRHHpost: |
| 31295 | case AArch64::STRHHpre: |
| 31296 | case AArch64::STRHpost: |
| 31297 | case AArch64::STRHpre: |
| 31298 | case AArch64::STRQpost: |
| 31299 | case AArch64::STRQpre: |
| 31300 | case AArch64::STRSpost: |
| 31301 | case AArch64::STRSpre: |
| 31302 | case AArch64::STRWpost: |
| 31303 | case AArch64::STRWpre: |
| 31304 | case AArch64::STRXpost: |
| 31305 | case AArch64::STRXpre: { |
| 31306 | switch (OpNum) { |
| 31307 | case 1: |
| 31308 | // op: Rt |
| 31309 | return 0; |
| 31310 | case 2: |
| 31311 | // op: Rn |
| 31312 | return 5; |
| 31313 | case 3: |
| 31314 | // op: offset |
| 31315 | return 12; |
| 31316 | } |
| 31317 | break; |
| 31318 | } |
| 31319 | case AArch64::LDAPRWpost: |
| 31320 | case AArch64::LDAPRXpost: |
| 31321 | case AArch64::STLRWpre: |
| 31322 | case AArch64::STLRXpre: { |
| 31323 | switch (OpNum) { |
| 31324 | case 1: |
| 31325 | // op: Rt |
| 31326 | return 0; |
| 31327 | case 2: |
| 31328 | // op: Rn |
| 31329 | return 5; |
| 31330 | } |
| 31331 | break; |
| 31332 | } |
| 31333 | case AArch64::LDPDpost: |
| 31334 | case AArch64::LDPDpre: |
| 31335 | case AArch64::LDPQpost: |
| 31336 | case AArch64::LDPQpre: |
| 31337 | case AArch64::LDPSWpost: |
| 31338 | case AArch64::LDPSWpre: |
| 31339 | case AArch64::LDPSpost: |
| 31340 | case AArch64::LDPSpre: |
| 31341 | case AArch64::LDPWpost: |
| 31342 | case AArch64::LDPWpre: |
| 31343 | case AArch64::LDPXpost: |
| 31344 | case AArch64::LDPXpre: |
| 31345 | case AArch64::LDTPQpost: |
| 31346 | case AArch64::LDTPQpre: |
| 31347 | case AArch64::LDTPpost: |
| 31348 | case AArch64::LDTPpre: |
| 31349 | case AArch64::STGPpost: |
| 31350 | case AArch64::STGPpre: |
| 31351 | case AArch64::STPDpost: |
| 31352 | case AArch64::STPDpre: |
| 31353 | case AArch64::STPQpost: |
| 31354 | case AArch64::STPQpre: |
| 31355 | case AArch64::STPSpost: |
| 31356 | case AArch64::STPSpre: |
| 31357 | case AArch64::STPWpost: |
| 31358 | case AArch64::STPWpre: |
| 31359 | case AArch64::STPXpost: |
| 31360 | case AArch64::STPXpre: |
| 31361 | case AArch64::STTPQpost: |
| 31362 | case AArch64::STTPQpre: |
| 31363 | case AArch64::STTPpost: |
| 31364 | case AArch64::STTPpre: { |
| 31365 | switch (OpNum) { |
| 31366 | case 1: |
| 31367 | // op: Rt |
| 31368 | return 0; |
| 31369 | case 2: |
| 31370 | // op: Rt2 |
| 31371 | return 10; |
| 31372 | case 3: |
| 31373 | // op: Rn |
| 31374 | return 5; |
| 31375 | case 4: |
| 31376 | // op: offset |
| 31377 | return 15; |
| 31378 | } |
| 31379 | break; |
| 31380 | } |
| 31381 | case AArch64::LDIAPPWpost: |
| 31382 | case AArch64::LDIAPPXpost: |
| 31383 | case AArch64::STILPWpre: |
| 31384 | case AArch64::STILPXpre: { |
| 31385 | switch (OpNum) { |
| 31386 | case 1: |
| 31387 | // op: Rt |
| 31388 | return 0; |
| 31389 | case 3: |
| 31390 | // op: Rn |
| 31391 | return 5; |
| 31392 | case 2: |
| 31393 | // op: Rt2 |
| 31394 | return 16; |
| 31395 | } |
| 31396 | break; |
| 31397 | } |
| 31398 | case AArch64::LDR_ZA: |
| 31399 | case AArch64::STR_ZA: { |
| 31400 | switch (OpNum) { |
| 31401 | case 1: |
| 31402 | // op: Rv |
| 31403 | return 13; |
| 31404 | case 3: |
| 31405 | // op: Rn |
| 31406 | return 5; |
| 31407 | case 2: |
| 31408 | // op: imm4 |
| 31409 | return 0; |
| 31410 | } |
| 31411 | break; |
| 31412 | } |
| 31413 | case AArch64::SHA512H: |
| 31414 | case AArch64::SHA512H2: |
| 31415 | case AArch64::SHA512SU1: |
| 31416 | case AArch64::SM3PARTW1: |
| 31417 | case AArch64::SM3PARTW2: |
| 31418 | case AArch64::TBXv16i8Four: |
| 31419 | case AArch64::TBXv16i8One: |
| 31420 | case AArch64::TBXv16i8Three: |
| 31421 | case AArch64::TBXv16i8Two: |
| 31422 | case AArch64::TBXv8i8Four: |
| 31423 | case AArch64::TBXv8i8One: |
| 31424 | case AArch64::TBXv8i8Three: |
| 31425 | case AArch64::TBXv8i8Two: { |
| 31426 | switch (OpNum) { |
| 31427 | case 1: |
| 31428 | // op: Vd |
| 31429 | return 0; |
| 31430 | case 2: |
| 31431 | // op: Vn |
| 31432 | return 5; |
| 31433 | case 3: |
| 31434 | // op: Vm |
| 31435 | return 16; |
| 31436 | } |
| 31437 | break; |
| 31438 | } |
| 31439 | case AArch64::SM3TT1A: |
| 31440 | case AArch64::SM3TT1B: |
| 31441 | case AArch64::SM3TT2A: |
| 31442 | case AArch64::SM3TT2B: { |
| 31443 | switch (OpNum) { |
| 31444 | case 1: |
| 31445 | // op: Vd |
| 31446 | return 0; |
| 31447 | case 2: |
| 31448 | // op: Vn |
| 31449 | return 5; |
| 31450 | case 4: |
| 31451 | // op: imm |
| 31452 | return 12; |
| 31453 | case 3: |
| 31454 | // op: Vm |
| 31455 | return 16; |
| 31456 | } |
| 31457 | break; |
| 31458 | } |
| 31459 | case AArch64::SHA512SU0: |
| 31460 | case AArch64::SM4E: { |
| 31461 | switch (OpNum) { |
| 31462 | case 1: |
| 31463 | // op: Vd |
| 31464 | return 0; |
| 31465 | case 2: |
| 31466 | // op: Vn |
| 31467 | return 5; |
| 31468 | } |
| 31469 | break; |
| 31470 | } |
| 31471 | case AArch64::LD1Fourv16b_POST: |
| 31472 | case AArch64::LD1Fourv1d_POST: |
| 31473 | case AArch64::LD1Fourv2d_POST: |
| 31474 | case AArch64::LD1Fourv2s_POST: |
| 31475 | case AArch64::LD1Fourv4h_POST: |
| 31476 | case AArch64::LD1Fourv4s_POST: |
| 31477 | case AArch64::LD1Fourv8b_POST: |
| 31478 | case AArch64::LD1Fourv8h_POST: |
| 31479 | case AArch64::LD1Onev16b_POST: |
| 31480 | case AArch64::LD1Onev1d_POST: |
| 31481 | case AArch64::LD1Onev2d_POST: |
| 31482 | case AArch64::LD1Onev2s_POST: |
| 31483 | case AArch64::LD1Onev4h_POST: |
| 31484 | case AArch64::LD1Onev4s_POST: |
| 31485 | case AArch64::LD1Onev8b_POST: |
| 31486 | case AArch64::LD1Onev8h_POST: |
| 31487 | case AArch64::LD1Rv16b_POST: |
| 31488 | case AArch64::LD1Rv1d_POST: |
| 31489 | case AArch64::LD1Rv2d_POST: |
| 31490 | case AArch64::LD1Rv2s_POST: |
| 31491 | case AArch64::LD1Rv4h_POST: |
| 31492 | case AArch64::LD1Rv4s_POST: |
| 31493 | case AArch64::LD1Rv8b_POST: |
| 31494 | case AArch64::LD1Rv8h_POST: |
| 31495 | case AArch64::LD1Threev16b_POST: |
| 31496 | case AArch64::LD1Threev1d_POST: |
| 31497 | case AArch64::LD1Threev2d_POST: |
| 31498 | case AArch64::LD1Threev2s_POST: |
| 31499 | case AArch64::LD1Threev4h_POST: |
| 31500 | case AArch64::LD1Threev4s_POST: |
| 31501 | case AArch64::LD1Threev8b_POST: |
| 31502 | case AArch64::LD1Threev8h_POST: |
| 31503 | case AArch64::LD1Twov16b_POST: |
| 31504 | case AArch64::LD1Twov1d_POST: |
| 31505 | case AArch64::LD1Twov2d_POST: |
| 31506 | case AArch64::LD1Twov2s_POST: |
| 31507 | case AArch64::LD1Twov4h_POST: |
| 31508 | case AArch64::LD1Twov4s_POST: |
| 31509 | case AArch64::LD1Twov8b_POST: |
| 31510 | case AArch64::LD1Twov8h_POST: |
| 31511 | case AArch64::LD2Rv16b_POST: |
| 31512 | case AArch64::LD2Rv1d_POST: |
| 31513 | case AArch64::LD2Rv2d_POST: |
| 31514 | case AArch64::LD2Rv2s_POST: |
| 31515 | case AArch64::LD2Rv4h_POST: |
| 31516 | case AArch64::LD2Rv4s_POST: |
| 31517 | case AArch64::LD2Rv8b_POST: |
| 31518 | case AArch64::LD2Rv8h_POST: |
| 31519 | case AArch64::LD2Twov16b_POST: |
| 31520 | case AArch64::LD2Twov2d_POST: |
| 31521 | case AArch64::LD2Twov2s_POST: |
| 31522 | case AArch64::LD2Twov4h_POST: |
| 31523 | case AArch64::LD2Twov4s_POST: |
| 31524 | case AArch64::LD2Twov8b_POST: |
| 31525 | case AArch64::LD2Twov8h_POST: |
| 31526 | case AArch64::LD3Rv16b_POST: |
| 31527 | case AArch64::LD3Rv1d_POST: |
| 31528 | case AArch64::LD3Rv2d_POST: |
| 31529 | case AArch64::LD3Rv2s_POST: |
| 31530 | case AArch64::LD3Rv4h_POST: |
| 31531 | case AArch64::LD3Rv4s_POST: |
| 31532 | case AArch64::LD3Rv8b_POST: |
| 31533 | case AArch64::LD3Rv8h_POST: |
| 31534 | case AArch64::LD3Threev16b_POST: |
| 31535 | case AArch64::LD3Threev2d_POST: |
| 31536 | case AArch64::LD3Threev2s_POST: |
| 31537 | case AArch64::LD3Threev4h_POST: |
| 31538 | case AArch64::LD3Threev4s_POST: |
| 31539 | case AArch64::LD3Threev8b_POST: |
| 31540 | case AArch64::LD3Threev8h_POST: |
| 31541 | case AArch64::LD4Fourv16b_POST: |
| 31542 | case AArch64::LD4Fourv2d_POST: |
| 31543 | case AArch64::LD4Fourv2s_POST: |
| 31544 | case AArch64::LD4Fourv4h_POST: |
| 31545 | case AArch64::LD4Fourv4s_POST: |
| 31546 | case AArch64::LD4Fourv8b_POST: |
| 31547 | case AArch64::LD4Fourv8h_POST: |
| 31548 | case AArch64::LD4Rv16b_POST: |
| 31549 | case AArch64::LD4Rv1d_POST: |
| 31550 | case AArch64::LD4Rv2d_POST: |
| 31551 | case AArch64::LD4Rv2s_POST: |
| 31552 | case AArch64::LD4Rv4h_POST: |
| 31553 | case AArch64::LD4Rv4s_POST: |
| 31554 | case AArch64::LD4Rv8b_POST: |
| 31555 | case AArch64::LD4Rv8h_POST: |
| 31556 | case AArch64::ST1Fourv16b_POST: |
| 31557 | case AArch64::ST1Fourv1d_POST: |
| 31558 | case AArch64::ST1Fourv2d_POST: |
| 31559 | case AArch64::ST1Fourv2s_POST: |
| 31560 | case AArch64::ST1Fourv4h_POST: |
| 31561 | case AArch64::ST1Fourv4s_POST: |
| 31562 | case AArch64::ST1Fourv8b_POST: |
| 31563 | case AArch64::ST1Fourv8h_POST: |
| 31564 | case AArch64::ST1Onev16b_POST: |
| 31565 | case AArch64::ST1Onev1d_POST: |
| 31566 | case AArch64::ST1Onev2d_POST: |
| 31567 | case AArch64::ST1Onev2s_POST: |
| 31568 | case AArch64::ST1Onev4h_POST: |
| 31569 | case AArch64::ST1Onev4s_POST: |
| 31570 | case AArch64::ST1Onev8b_POST: |
| 31571 | case AArch64::ST1Onev8h_POST: |
| 31572 | case AArch64::ST1Threev16b_POST: |
| 31573 | case AArch64::ST1Threev1d_POST: |
| 31574 | case AArch64::ST1Threev2d_POST: |
| 31575 | case AArch64::ST1Threev2s_POST: |
| 31576 | case AArch64::ST1Threev4h_POST: |
| 31577 | case AArch64::ST1Threev4s_POST: |
| 31578 | case AArch64::ST1Threev8b_POST: |
| 31579 | case AArch64::ST1Threev8h_POST: |
| 31580 | case AArch64::ST1Twov16b_POST: |
| 31581 | case AArch64::ST1Twov1d_POST: |
| 31582 | case AArch64::ST1Twov2d_POST: |
| 31583 | case AArch64::ST1Twov2s_POST: |
| 31584 | case AArch64::ST1Twov4h_POST: |
| 31585 | case AArch64::ST1Twov4s_POST: |
| 31586 | case AArch64::ST1Twov8b_POST: |
| 31587 | case AArch64::ST1Twov8h_POST: |
| 31588 | case AArch64::ST2Twov16b_POST: |
| 31589 | case AArch64::ST2Twov2d_POST: |
| 31590 | case AArch64::ST2Twov2s_POST: |
| 31591 | case AArch64::ST2Twov4h_POST: |
| 31592 | case AArch64::ST2Twov4s_POST: |
| 31593 | case AArch64::ST2Twov8b_POST: |
| 31594 | case AArch64::ST2Twov8h_POST: |
| 31595 | case AArch64::ST3Threev16b_POST: |
| 31596 | case AArch64::ST3Threev2d_POST: |
| 31597 | case AArch64::ST3Threev2s_POST: |
| 31598 | case AArch64::ST3Threev4h_POST: |
| 31599 | case AArch64::ST3Threev4s_POST: |
| 31600 | case AArch64::ST3Threev8b_POST: |
| 31601 | case AArch64::ST3Threev8h_POST: |
| 31602 | case AArch64::ST4Fourv16b_POST: |
| 31603 | case AArch64::ST4Fourv2d_POST: |
| 31604 | case AArch64::ST4Fourv2s_POST: |
| 31605 | case AArch64::ST4Fourv4h_POST: |
| 31606 | case AArch64::ST4Fourv4s_POST: |
| 31607 | case AArch64::ST4Fourv8b_POST: |
| 31608 | case AArch64::ST4Fourv8h_POST: { |
| 31609 | switch (OpNum) { |
| 31610 | case 1: |
| 31611 | // op: Vt |
| 31612 | return 0; |
| 31613 | case 2: |
| 31614 | // op: Rn |
| 31615 | return 5; |
| 31616 | case 3: |
| 31617 | // op: Xm |
| 31618 | return 16; |
| 31619 | } |
| 31620 | break; |
| 31621 | } |
| 31622 | case AArch64::LDAP1: { |
| 31623 | switch (OpNum) { |
| 31624 | case 1: |
| 31625 | // op: Vt |
| 31626 | return 0; |
| 31627 | case 3: |
| 31628 | // op: Rn |
| 31629 | return 5; |
| 31630 | case 2: |
| 31631 | // op: Q |
| 31632 | return 30; |
| 31633 | } |
| 31634 | break; |
| 31635 | } |
| 31636 | case AArch64::ST1i8_POST: |
| 31637 | case AArch64::ST2i8_POST: |
| 31638 | case AArch64::ST3i8_POST: |
| 31639 | case AArch64::ST4i8_POST: { |
| 31640 | switch (OpNum) { |
| 31641 | case 1: |
| 31642 | // op: Vt |
| 31643 | return 0; |
| 31644 | case 3: |
| 31645 | // op: Rn |
| 31646 | return 5; |
| 31647 | case 2: |
| 31648 | // op: idx |
| 31649 | return 10; |
| 31650 | case 4: |
| 31651 | // op: Xm |
| 31652 | return 16; |
| 31653 | } |
| 31654 | break; |
| 31655 | } |
| 31656 | case AArch64::LD1i8: |
| 31657 | case AArch64::LD2i8: |
| 31658 | case AArch64::LD3i8: |
| 31659 | case AArch64::LD4i8: { |
| 31660 | switch (OpNum) { |
| 31661 | case 1: |
| 31662 | // op: Vt |
| 31663 | return 0; |
| 31664 | case 3: |
| 31665 | // op: Rn |
| 31666 | return 5; |
| 31667 | case 2: |
| 31668 | // op: idx |
| 31669 | return 10; |
| 31670 | } |
| 31671 | break; |
| 31672 | } |
| 31673 | case AArch64::ST1i16_POST: |
| 31674 | case AArch64::ST2i16_POST: |
| 31675 | case AArch64::ST3i16_POST: |
| 31676 | case AArch64::ST4i16_POST: { |
| 31677 | switch (OpNum) { |
| 31678 | case 1: |
| 31679 | // op: Vt |
| 31680 | return 0; |
| 31681 | case 3: |
| 31682 | // op: Rn |
| 31683 | return 5; |
| 31684 | case 2: |
| 31685 | // op: idx |
| 31686 | return 11; |
| 31687 | case 4: |
| 31688 | // op: Xm |
| 31689 | return 16; |
| 31690 | } |
| 31691 | break; |
| 31692 | } |
| 31693 | case AArch64::LD1i16: |
| 31694 | case AArch64::LD2i16: |
| 31695 | case AArch64::LD3i16: |
| 31696 | case AArch64::LD4i16: { |
| 31697 | switch (OpNum) { |
| 31698 | case 1: |
| 31699 | // op: Vt |
| 31700 | return 0; |
| 31701 | case 3: |
| 31702 | // op: Rn |
| 31703 | return 5; |
| 31704 | case 2: |
| 31705 | // op: idx |
| 31706 | return 11; |
| 31707 | } |
| 31708 | break; |
| 31709 | } |
| 31710 | case AArch64::ST1i32_POST: |
| 31711 | case AArch64::ST2i32_POST: |
| 31712 | case AArch64::ST3i32_POST: |
| 31713 | case AArch64::ST4i32_POST: { |
| 31714 | switch (OpNum) { |
| 31715 | case 1: |
| 31716 | // op: Vt |
| 31717 | return 0; |
| 31718 | case 3: |
| 31719 | // op: Rn |
| 31720 | return 5; |
| 31721 | case 2: |
| 31722 | // op: idx |
| 31723 | return 12; |
| 31724 | case 4: |
| 31725 | // op: Xm |
| 31726 | return 16; |
| 31727 | } |
| 31728 | break; |
| 31729 | } |
| 31730 | case AArch64::LD1i32: |
| 31731 | case AArch64::LD2i32: |
| 31732 | case AArch64::LD3i32: |
| 31733 | case AArch64::LD4i32: { |
| 31734 | switch (OpNum) { |
| 31735 | case 1: |
| 31736 | // op: Vt |
| 31737 | return 0; |
| 31738 | case 3: |
| 31739 | // op: Rn |
| 31740 | return 5; |
| 31741 | case 2: |
| 31742 | // op: idx |
| 31743 | return 12; |
| 31744 | } |
| 31745 | break; |
| 31746 | } |
| 31747 | case AArch64::ST1i64_POST: |
| 31748 | case AArch64::ST2i64_POST: |
| 31749 | case AArch64::ST3i64_POST: |
| 31750 | case AArch64::ST4i64_POST: { |
| 31751 | switch (OpNum) { |
| 31752 | case 1: |
| 31753 | // op: Vt |
| 31754 | return 0; |
| 31755 | case 3: |
| 31756 | // op: Rn |
| 31757 | return 5; |
| 31758 | case 2: |
| 31759 | // op: idx |
| 31760 | return 30; |
| 31761 | case 4: |
| 31762 | // op: Xm |
| 31763 | return 16; |
| 31764 | } |
| 31765 | break; |
| 31766 | } |
| 31767 | case AArch64::LD1i64: |
| 31768 | case AArch64::LD2i64: |
| 31769 | case AArch64::LD3i64: |
| 31770 | case AArch64::LD4i64: { |
| 31771 | switch (OpNum) { |
| 31772 | case 1: |
| 31773 | // op: Vt |
| 31774 | return 0; |
| 31775 | case 3: |
| 31776 | // op: Rn |
| 31777 | return 5; |
| 31778 | case 2: |
| 31779 | // op: idx |
| 31780 | return 30; |
| 31781 | } |
| 31782 | break; |
| 31783 | } |
| 31784 | case AArch64::BF1CVTL_2ZZ_BtoH: |
| 31785 | case AArch64::BF1CVT_2ZZ_BtoH: |
| 31786 | case AArch64::BF2CVTL_2ZZ_BtoH: |
| 31787 | case AArch64::BF2CVT_2ZZ_BtoH: |
| 31788 | case AArch64::F1CVTL_2ZZ_BtoH: |
| 31789 | case AArch64::F1CVT_2ZZ_BtoH: |
| 31790 | case AArch64::F2CVTL_2ZZ_BtoH: |
| 31791 | case AArch64::F2CVT_2ZZ_BtoH: |
| 31792 | case AArch64::FCVTL_2ZZ_H_S: |
| 31793 | case AArch64::FCVT_2ZZ_H_S: |
| 31794 | case AArch64::SUNPK_VG2_2ZZ_D: |
| 31795 | case AArch64::SUNPK_VG2_2ZZ_H: |
| 31796 | case AArch64::SUNPK_VG2_2ZZ_S: |
| 31797 | case AArch64::UUNPK_VG2_2ZZ_D: |
| 31798 | case AArch64::UUNPK_VG2_2ZZ_H: |
| 31799 | case AArch64::UUNPK_VG2_2ZZ_S: { |
| 31800 | switch (OpNum) { |
| 31801 | case 1: |
| 31802 | // op: Zn |
| 31803 | return 5; |
| 31804 | case 0: |
| 31805 | // op: Zd |
| 31806 | return 1; |
| 31807 | } |
| 31808 | break; |
| 31809 | } |
| 31810 | case AArch64::BFCVTN_Z2Z_StoH: |
| 31811 | case AArch64::BFCVT_Z2Z_HtoB: |
| 31812 | case AArch64::BFCVT_Z2Z_StoH: |
| 31813 | case AArch64::FCVTN_Z2Z_StoH: |
| 31814 | case AArch64::FCVT_Z2Z_HtoB: |
| 31815 | case AArch64::FCVT_Z2Z_StoH: |
| 31816 | case AArch64::SQCVTU_Z2Z_StoH: |
| 31817 | case AArch64::SQCVT_Z2Z_StoH: |
| 31818 | case AArch64::UQCVT_Z2Z_StoH: { |
| 31819 | switch (OpNum) { |
| 31820 | case 1: |
| 31821 | // op: Zn |
| 31822 | return 6; |
| 31823 | case 0: |
| 31824 | // op: Zd |
| 31825 | return 0; |
| 31826 | } |
| 31827 | break; |
| 31828 | } |
| 31829 | case AArch64::FCVTZS_2Z2Z_StoS: |
| 31830 | case AArch64::FCVTZU_2Z2Z_StoS: |
| 31831 | case AArch64::FRINTA_2Z2Z_S: |
| 31832 | case AArch64::FRINTM_2Z2Z_S: |
| 31833 | case AArch64::FRINTN_2Z2Z_S: |
| 31834 | case AArch64::FRINTP_2Z2Z_S: |
| 31835 | case AArch64::SCVTF_2Z2Z_StoS: |
| 31836 | case AArch64::UCVTF_2Z2Z_StoS: { |
| 31837 | switch (OpNum) { |
| 31838 | case 1: |
| 31839 | // op: Zn |
| 31840 | return 6; |
| 31841 | case 0: |
| 31842 | // op: Zd |
| 31843 | return 1; |
| 31844 | } |
| 31845 | break; |
| 31846 | } |
| 31847 | case AArch64::SUNPK_VG4_4Z2Z_D: |
| 31848 | case AArch64::SUNPK_VG4_4Z2Z_H: |
| 31849 | case AArch64::SUNPK_VG4_4Z2Z_S: |
| 31850 | case AArch64::UUNPK_VG4_4Z2Z_D: |
| 31851 | case AArch64::UUNPK_VG4_4Z2Z_H: |
| 31852 | case AArch64::UUNPK_VG4_4Z2Z_S: { |
| 31853 | switch (OpNum) { |
| 31854 | case 1: |
| 31855 | // op: Zn |
| 31856 | return 6; |
| 31857 | case 0: |
| 31858 | // op: Zd |
| 31859 | return 2; |
| 31860 | } |
| 31861 | break; |
| 31862 | } |
| 31863 | case AArch64::SQRSHRN_VG4_Z4ZI_B: |
| 31864 | case AArch64::SQRSHRN_VG4_Z4ZI_H: |
| 31865 | case AArch64::SQRSHRUN_VG4_Z4ZI_B: |
| 31866 | case AArch64::SQRSHRUN_VG4_Z4ZI_H: |
| 31867 | case AArch64::SQRSHRU_VG4_Z4ZI_B: |
| 31868 | case AArch64::SQRSHRU_VG4_Z4ZI_H: |
| 31869 | case AArch64::SQRSHR_VG4_Z4ZI_B: |
| 31870 | case AArch64::SQRSHR_VG4_Z4ZI_H: |
| 31871 | case AArch64::UQRSHRN_VG4_Z4ZI_B: |
| 31872 | case AArch64::UQRSHRN_VG4_Z4ZI_H: |
| 31873 | case AArch64::UQRSHR_VG4_Z4ZI_B: |
| 31874 | case AArch64::UQRSHR_VG4_Z4ZI_H: { |
| 31875 | switch (OpNum) { |
| 31876 | case 1: |
| 31877 | // op: Zn |
| 31878 | return 7; |
| 31879 | case 0: |
| 31880 | // op: Zd |
| 31881 | return 0; |
| 31882 | case 2: |
| 31883 | // op: imm |
| 31884 | return 16; |
| 31885 | } |
| 31886 | break; |
| 31887 | } |
| 31888 | case AArch64::FCVTN_Z4Z_StoB: |
| 31889 | case AArch64::FCVT_Z4Z_StoB: |
| 31890 | case AArch64::SQCVTN_Z4Z_DtoH: |
| 31891 | case AArch64::SQCVTN_Z4Z_StoB: |
| 31892 | case AArch64::SQCVTUN_Z4Z_DtoH: |
| 31893 | case AArch64::SQCVTUN_Z4Z_StoB: |
| 31894 | case AArch64::SQCVTU_Z4Z_DtoH: |
| 31895 | case AArch64::SQCVTU_Z4Z_StoB: |
| 31896 | case AArch64::SQCVT_Z4Z_DtoH: |
| 31897 | case AArch64::SQCVT_Z4Z_StoB: |
| 31898 | case AArch64::UQCVTN_Z4Z_DtoH: |
| 31899 | case AArch64::UQCVTN_Z4Z_StoB: |
| 31900 | case AArch64::UQCVT_Z4Z_DtoH: |
| 31901 | case AArch64::UQCVT_Z4Z_StoB: { |
| 31902 | switch (OpNum) { |
| 31903 | case 1: |
| 31904 | // op: Zn |
| 31905 | return 7; |
| 31906 | case 0: |
| 31907 | // op: Zd |
| 31908 | return 0; |
| 31909 | } |
| 31910 | break; |
| 31911 | } |
| 31912 | case AArch64::FCVTZS_4Z4Z_StoS: |
| 31913 | case AArch64::FCVTZU_4Z4Z_StoS: |
| 31914 | case AArch64::FRINTA_4Z4Z_S: |
| 31915 | case AArch64::FRINTM_4Z4Z_S: |
| 31916 | case AArch64::FRINTN_4Z4Z_S: |
| 31917 | case AArch64::FRINTP_4Z4Z_S: |
| 31918 | case AArch64::SCVTF_4Z4Z_StoS: |
| 31919 | case AArch64::UCVTF_4Z4Z_StoS: |
| 31920 | case AArch64::UZP_VG4_4Z4Z_B: |
| 31921 | case AArch64::UZP_VG4_4Z4Z_D: |
| 31922 | case AArch64::UZP_VG4_4Z4Z_H: |
| 31923 | case AArch64::UZP_VG4_4Z4Z_Q: |
| 31924 | case AArch64::UZP_VG4_4Z4Z_S: |
| 31925 | case AArch64::ZIP_VG4_4Z4Z_B: |
| 31926 | case AArch64::ZIP_VG4_4Z4Z_D: |
| 31927 | case AArch64::ZIP_VG4_4Z4Z_H: |
| 31928 | case AArch64::ZIP_VG4_4Z4Z_Q: |
| 31929 | case AArch64::ZIP_VG4_4Z4Z_S: { |
| 31930 | switch (OpNum) { |
| 31931 | case 1: |
| 31932 | // op: Zn |
| 31933 | return 7; |
| 31934 | case 0: |
| 31935 | // op: Zd |
| 31936 | return 2; |
| 31937 | } |
| 31938 | break; |
| 31939 | } |
| 31940 | case AArch64::MOVT_TIX: { |
| 31941 | switch (OpNum) { |
| 31942 | case 1: |
| 31943 | // op: imm3 |
| 31944 | return 12; |
| 31945 | case 2: |
| 31946 | // op: Rt |
| 31947 | return 0; |
| 31948 | } |
| 31949 | break; |
| 31950 | } |
| 31951 | case AArch64::ABS_ZPmZ_B: |
| 31952 | case AArch64::ABS_ZPmZ_D: |
| 31953 | case AArch64::ABS_ZPmZ_H: |
| 31954 | case AArch64::ABS_ZPmZ_S: |
| 31955 | case AArch64::BFCVT_ZPmZ: |
| 31956 | case AArch64::CLS_ZPmZ_B: |
| 31957 | case AArch64::CLS_ZPmZ_D: |
| 31958 | case AArch64::CLS_ZPmZ_H: |
| 31959 | case AArch64::CLS_ZPmZ_S: |
| 31960 | case AArch64::CLZ_ZPmZ_B: |
| 31961 | case AArch64::CLZ_ZPmZ_D: |
| 31962 | case AArch64::CLZ_ZPmZ_H: |
| 31963 | case AArch64::CLZ_ZPmZ_S: |
| 31964 | case AArch64::CNOT_ZPmZ_B: |
| 31965 | case AArch64::CNOT_ZPmZ_D: |
| 31966 | case AArch64::CNOT_ZPmZ_H: |
| 31967 | case AArch64::CNOT_ZPmZ_S: |
| 31968 | case AArch64::CNT_ZPmZ_B: |
| 31969 | case AArch64::CNT_ZPmZ_D: |
| 31970 | case AArch64::CNT_ZPmZ_H: |
| 31971 | case AArch64::CNT_ZPmZ_S: |
| 31972 | case AArch64::FABS_ZPmZ_D: |
| 31973 | case AArch64::FABS_ZPmZ_H: |
| 31974 | case AArch64::FABS_ZPmZ_S: |
| 31975 | case AArch64::FCVTX_ZPmZ_DtoS: |
| 31976 | case AArch64::FCVTZS_ZPmZ_DtoD: |
| 31977 | case AArch64::FCVTZS_ZPmZ_DtoS: |
| 31978 | case AArch64::FCVTZS_ZPmZ_HtoD: |
| 31979 | case AArch64::FCVTZS_ZPmZ_HtoH: |
| 31980 | case AArch64::FCVTZS_ZPmZ_HtoS: |
| 31981 | case AArch64::FCVTZS_ZPmZ_StoD: |
| 31982 | case AArch64::FCVTZS_ZPmZ_StoS: |
| 31983 | case AArch64::FCVTZU_ZPmZ_DtoD: |
| 31984 | case AArch64::FCVTZU_ZPmZ_DtoS: |
| 31985 | case AArch64::FCVTZU_ZPmZ_HtoD: |
| 31986 | case AArch64::FCVTZU_ZPmZ_HtoH: |
| 31987 | case AArch64::FCVTZU_ZPmZ_HtoS: |
| 31988 | case AArch64::FCVTZU_ZPmZ_StoD: |
| 31989 | case AArch64::FCVTZU_ZPmZ_StoS: |
| 31990 | case AArch64::FCVT_ZPmZ_DtoH: |
| 31991 | case AArch64::FCVT_ZPmZ_DtoS: |
| 31992 | case AArch64::FCVT_ZPmZ_HtoD: |
| 31993 | case AArch64::FCVT_ZPmZ_HtoS: |
| 31994 | case AArch64::FCVT_ZPmZ_StoD: |
| 31995 | case AArch64::FCVT_ZPmZ_StoH: |
| 31996 | case AArch64::FLOGB_ZPmZ_D: |
| 31997 | case AArch64::FLOGB_ZPmZ_H: |
| 31998 | case AArch64::FLOGB_ZPmZ_S: |
| 31999 | case AArch64::FNEG_ZPmZ_D: |
| 32000 | case AArch64::FNEG_ZPmZ_H: |
| 32001 | case AArch64::FNEG_ZPmZ_S: |
| 32002 | case AArch64::FRECPX_ZPmZ_D: |
| 32003 | case AArch64::FRECPX_ZPmZ_H: |
| 32004 | case AArch64::FRECPX_ZPmZ_S: |
| 32005 | case AArch64::FRINT32X_ZPmZ_D: |
| 32006 | case AArch64::FRINT32X_ZPmZ_S: |
| 32007 | case AArch64::FRINT32Z_ZPmZ_D: |
| 32008 | case AArch64::FRINT32Z_ZPmZ_S: |
| 32009 | case AArch64::FRINT64X_ZPmZ_D: |
| 32010 | case AArch64::FRINT64X_ZPmZ_S: |
| 32011 | case AArch64::FRINT64Z_ZPmZ_D: |
| 32012 | case AArch64::FRINT64Z_ZPmZ_S: |
| 32013 | case AArch64::FRINTA_ZPmZ_D: |
| 32014 | case AArch64::FRINTA_ZPmZ_H: |
| 32015 | case AArch64::FRINTA_ZPmZ_S: |
| 32016 | case AArch64::FRINTI_ZPmZ_D: |
| 32017 | case AArch64::FRINTI_ZPmZ_H: |
| 32018 | case AArch64::FRINTI_ZPmZ_S: |
| 32019 | case AArch64::FRINTM_ZPmZ_D: |
| 32020 | case AArch64::FRINTM_ZPmZ_H: |
| 32021 | case AArch64::FRINTM_ZPmZ_S: |
| 32022 | case AArch64::FRINTN_ZPmZ_D: |
| 32023 | case AArch64::FRINTN_ZPmZ_H: |
| 32024 | case AArch64::FRINTN_ZPmZ_S: |
| 32025 | case AArch64::FRINTP_ZPmZ_D: |
| 32026 | case AArch64::FRINTP_ZPmZ_H: |
| 32027 | case AArch64::FRINTP_ZPmZ_S: |
| 32028 | case AArch64::FRINTX_ZPmZ_D: |
| 32029 | case AArch64::FRINTX_ZPmZ_H: |
| 32030 | case AArch64::FRINTX_ZPmZ_S: |
| 32031 | case AArch64::FRINTZ_ZPmZ_D: |
| 32032 | case AArch64::FRINTZ_ZPmZ_H: |
| 32033 | case AArch64::FRINTZ_ZPmZ_S: |
| 32034 | case AArch64::FSQRT_ZPmZ_D: |
| 32035 | case AArch64::FSQRT_ZPmZ_H: |
| 32036 | case AArch64::FSQRT_ZPmZ_S: |
| 32037 | case AArch64::MOVPRFX_ZPmZ_B: |
| 32038 | case AArch64::MOVPRFX_ZPmZ_D: |
| 32039 | case AArch64::MOVPRFX_ZPmZ_H: |
| 32040 | case AArch64::MOVPRFX_ZPmZ_S: |
| 32041 | case AArch64::NEG_ZPmZ_B: |
| 32042 | case AArch64::NEG_ZPmZ_D: |
| 32043 | case AArch64::NEG_ZPmZ_H: |
| 32044 | case AArch64::NEG_ZPmZ_S: |
| 32045 | case AArch64::NOT_ZPmZ_B: |
| 32046 | case AArch64::NOT_ZPmZ_D: |
| 32047 | case AArch64::NOT_ZPmZ_H: |
| 32048 | case AArch64::NOT_ZPmZ_S: |
| 32049 | case AArch64::SCVTF_ZPmZ_DtoD: |
| 32050 | case AArch64::SCVTF_ZPmZ_DtoH: |
| 32051 | case AArch64::SCVTF_ZPmZ_DtoS: |
| 32052 | case AArch64::SCVTF_ZPmZ_HtoH: |
| 32053 | case AArch64::SCVTF_ZPmZ_StoD: |
| 32054 | case AArch64::SCVTF_ZPmZ_StoH: |
| 32055 | case AArch64::SCVTF_ZPmZ_StoS: |
| 32056 | case AArch64::SQABS_ZPmZ_B: |
| 32057 | case AArch64::SQABS_ZPmZ_D: |
| 32058 | case AArch64::SQABS_ZPmZ_H: |
| 32059 | case AArch64::SQABS_ZPmZ_S: |
| 32060 | case AArch64::SQNEG_ZPmZ_B: |
| 32061 | case AArch64::SQNEG_ZPmZ_D: |
| 32062 | case AArch64::SQNEG_ZPmZ_H: |
| 32063 | case AArch64::SQNEG_ZPmZ_S: |
| 32064 | case AArch64::SXTB_ZPmZ_D: |
| 32065 | case AArch64::SXTB_ZPmZ_H: |
| 32066 | case AArch64::SXTB_ZPmZ_S: |
| 32067 | case AArch64::SXTH_ZPmZ_D: |
| 32068 | case AArch64::SXTH_ZPmZ_S: |
| 32069 | case AArch64::SXTW_ZPmZ_D: |
| 32070 | case AArch64::UCVTF_ZPmZ_DtoD: |
| 32071 | case AArch64::UCVTF_ZPmZ_DtoH: |
| 32072 | case AArch64::UCVTF_ZPmZ_DtoS: |
| 32073 | case AArch64::UCVTF_ZPmZ_HtoH: |
| 32074 | case AArch64::UCVTF_ZPmZ_StoD: |
| 32075 | case AArch64::UCVTF_ZPmZ_StoH: |
| 32076 | case AArch64::UCVTF_ZPmZ_StoS: |
| 32077 | case AArch64::URECPE_ZPmZ_S: |
| 32078 | case AArch64::URSQRTE_ZPmZ_S: |
| 32079 | case AArch64::UXTB_ZPmZ_D: |
| 32080 | case AArch64::UXTB_ZPmZ_H: |
| 32081 | case AArch64::UXTB_ZPmZ_S: |
| 32082 | case AArch64::UXTH_ZPmZ_D: |
| 32083 | case AArch64::UXTH_ZPmZ_S: |
| 32084 | case AArch64::UXTW_ZPmZ_D: { |
| 32085 | switch (OpNum) { |
| 32086 | case 2: |
| 32087 | // op: Pg |
| 32088 | return 10; |
| 32089 | case 0: |
| 32090 | // op: Zd |
| 32091 | return 0; |
| 32092 | case 3: |
| 32093 | // op: Zn |
| 32094 | return 5; |
| 32095 | } |
| 32096 | break; |
| 32097 | } |
| 32098 | case AArch64::CPY_ZPmR_B: |
| 32099 | case AArch64::CPY_ZPmR_D: |
| 32100 | case AArch64::CPY_ZPmR_H: |
| 32101 | case AArch64::CPY_ZPmR_S: { |
| 32102 | switch (OpNum) { |
| 32103 | case 2: |
| 32104 | // op: Pg |
| 32105 | return 10; |
| 32106 | case 3: |
| 32107 | // op: Rn |
| 32108 | return 5; |
| 32109 | case 0: |
| 32110 | // op: Zd |
| 32111 | return 0; |
| 32112 | } |
| 32113 | break; |
| 32114 | } |
| 32115 | case AArch64::CPY_ZPmV_B: |
| 32116 | case AArch64::CPY_ZPmV_D: |
| 32117 | case AArch64::CPY_ZPmV_H: |
| 32118 | case AArch64::CPY_ZPmV_S: { |
| 32119 | switch (OpNum) { |
| 32120 | case 2: |
| 32121 | // op: Pg |
| 32122 | return 10; |
| 32123 | case 3: |
| 32124 | // op: Vn |
| 32125 | return 5; |
| 32126 | case 0: |
| 32127 | // op: Zd |
| 32128 | return 0; |
| 32129 | } |
| 32130 | break; |
| 32131 | } |
| 32132 | case AArch64::FCPY_ZPmI_D: |
| 32133 | case AArch64::FCPY_ZPmI_H: |
| 32134 | case AArch64::FCPY_ZPmI_S: { |
| 32135 | switch (OpNum) { |
| 32136 | case 2: |
| 32137 | // op: Pg |
| 32138 | return 16; |
| 32139 | case 0: |
| 32140 | // op: Zd |
| 32141 | return 0; |
| 32142 | case 3: |
| 32143 | // op: imm8 |
| 32144 | return 5; |
| 32145 | } |
| 32146 | break; |
| 32147 | } |
| 32148 | case AArch64::DECP_ZP_D: |
| 32149 | case AArch64::DECP_ZP_H: |
| 32150 | case AArch64::DECP_ZP_S: |
| 32151 | case AArch64::INCP_ZP_D: |
| 32152 | case AArch64::INCP_ZP_H: |
| 32153 | case AArch64::INCP_ZP_S: |
| 32154 | case AArch64::SQDECP_ZP_D: |
| 32155 | case AArch64::SQDECP_ZP_H: |
| 32156 | case AArch64::SQDECP_ZP_S: |
| 32157 | case AArch64::SQINCP_ZP_D: |
| 32158 | case AArch64::SQINCP_ZP_H: |
| 32159 | case AArch64::SQINCP_ZP_S: |
| 32160 | case AArch64::UQDECP_ZP_D: |
| 32161 | case AArch64::UQDECP_ZP_H: |
| 32162 | case AArch64::UQDECP_ZP_S: |
| 32163 | case AArch64::UQINCP_ZP_D: |
| 32164 | case AArch64::UQINCP_ZP_H: |
| 32165 | case AArch64::UQINCP_ZP_S: { |
| 32166 | switch (OpNum) { |
| 32167 | case 2: |
| 32168 | // op: Pm |
| 32169 | return 5; |
| 32170 | case 0: |
| 32171 | // op: Zdn |
| 32172 | return 0; |
| 32173 | } |
| 32174 | break; |
| 32175 | } |
| 32176 | case AArch64::MOPSSETGE: |
| 32177 | case AArch64::MOPSSETGEN: |
| 32178 | case AArch64::MOPSSETGET: |
| 32179 | case AArch64::MOPSSETGETN: |
| 32180 | case AArch64::SETE: |
| 32181 | case AArch64::SETEN: |
| 32182 | case AArch64::SETET: |
| 32183 | case AArch64::SETETN: |
| 32184 | case AArch64::SETGM: |
| 32185 | case AArch64::SETGMN: |
| 32186 | case AArch64::SETGMT: |
| 32187 | case AArch64::SETGMTN: |
| 32188 | case AArch64::SETGP: |
| 32189 | case AArch64::SETGPN: |
| 32190 | case AArch64::SETGPT: |
| 32191 | case AArch64::SETGPTN: |
| 32192 | case AArch64::SETM: |
| 32193 | case AArch64::SETMN: |
| 32194 | case AArch64::SETMT: |
| 32195 | case AArch64::SETMTN: |
| 32196 | case AArch64::SETP: |
| 32197 | case AArch64::SETPN: |
| 32198 | case AArch64::SETPT: |
| 32199 | case AArch64::SETPTN: { |
| 32200 | switch (OpNum) { |
| 32201 | case 2: |
| 32202 | // op: Rd |
| 32203 | return 0; |
| 32204 | case 3: |
| 32205 | // op: Rn |
| 32206 | return 5; |
| 32207 | case 4: |
| 32208 | // op: Rm |
| 32209 | return 16; |
| 32210 | } |
| 32211 | break; |
| 32212 | } |
| 32213 | case AArch64::SETGOE: |
| 32214 | case AArch64::SETGOEN: |
| 32215 | case AArch64::SETGOET: |
| 32216 | case AArch64::SETGOETN: |
| 32217 | case AArch64::SETGOM: |
| 32218 | case AArch64::SETGOMN: |
| 32219 | case AArch64::SETGOMT: |
| 32220 | case AArch64::SETGOMTN: |
| 32221 | case AArch64::SETGOP: |
| 32222 | case AArch64::SETGOPN: |
| 32223 | case AArch64::SETGOPT: |
| 32224 | case AArch64::SETGOPTN: { |
| 32225 | switch (OpNum) { |
| 32226 | case 2: |
| 32227 | // op: Rd |
| 32228 | return 0; |
| 32229 | case 3: |
| 32230 | // op: Rn |
| 32231 | return 5; |
| 32232 | } |
| 32233 | break; |
| 32234 | } |
| 32235 | case AArch64::INDEX_IR_B: |
| 32236 | case AArch64::INDEX_IR_D: |
| 32237 | case AArch64::INDEX_IR_H: |
| 32238 | case AArch64::INDEX_IR_S: { |
| 32239 | switch (OpNum) { |
| 32240 | case 2: |
| 32241 | // op: Rm |
| 32242 | return 16; |
| 32243 | case 0: |
| 32244 | // op: Zd |
| 32245 | return 0; |
| 32246 | case 1: |
| 32247 | // op: imm5 |
| 32248 | return 5; |
| 32249 | } |
| 32250 | break; |
| 32251 | } |
| 32252 | case AArch64::INSR_ZR_B: |
| 32253 | case AArch64::INSR_ZR_D: |
| 32254 | case AArch64::INSR_ZR_H: |
| 32255 | case AArch64::INSR_ZR_S: { |
| 32256 | switch (OpNum) { |
| 32257 | case 2: |
| 32258 | // op: Rm |
| 32259 | return 5; |
| 32260 | case 0: |
| 32261 | // op: Zdn |
| 32262 | return 0; |
| 32263 | } |
| 32264 | break; |
| 32265 | } |
| 32266 | case AArch64::PRFB_PRI: |
| 32267 | case AArch64::PRFD_PRI: |
| 32268 | case AArch64::PRFH_PRI: |
| 32269 | case AArch64::PRFW_PRI: { |
| 32270 | switch (OpNum) { |
| 32271 | case 2: |
| 32272 | // op: Rn |
| 32273 | return 5; |
| 32274 | case 1: |
| 32275 | // op: Pg |
| 32276 | return 10; |
| 32277 | case 3: |
| 32278 | // op: imm6 |
| 32279 | return 16; |
| 32280 | case 0: |
| 32281 | // op: prfop |
| 32282 | return 0; |
| 32283 | } |
| 32284 | break; |
| 32285 | } |
| 32286 | case AArch64::LDG: |
| 32287 | case AArch64::ST2GPostIndex: |
| 32288 | case AArch64::ST2GPreIndex: |
| 32289 | case AArch64::STGPostIndex: |
| 32290 | case AArch64::STGPreIndex: |
| 32291 | case AArch64::STZ2GPostIndex: |
| 32292 | case AArch64::STZ2GPreIndex: |
| 32293 | case AArch64::STZGPostIndex: |
| 32294 | case AArch64::STZGPreIndex: { |
| 32295 | switch (OpNum) { |
| 32296 | case 2: |
| 32297 | // op: Rn |
| 32298 | return 5; |
| 32299 | case 1: |
| 32300 | // op: Rt |
| 32301 | return 0; |
| 32302 | case 3: |
| 32303 | // op: offset |
| 32304 | return 12; |
| 32305 | } |
| 32306 | break; |
| 32307 | } |
| 32308 | case AArch64::MOVA_VG2_MXI2Z: { |
| 32309 | switch (OpNum) { |
| 32310 | case 2: |
| 32311 | // op: Rs |
| 32312 | return 13; |
| 32313 | case 3: |
| 32314 | // op: imm |
| 32315 | return 0; |
| 32316 | case 4: |
| 32317 | // op: Zn |
| 32318 | return 6; |
| 32319 | } |
| 32320 | break; |
| 32321 | } |
| 32322 | case AArch64::MOVA_VG4_MXI4Z: { |
| 32323 | switch (OpNum) { |
| 32324 | case 2: |
| 32325 | // op: Rs |
| 32326 | return 13; |
| 32327 | case 3: |
| 32328 | // op: imm |
| 32329 | return 0; |
| 32330 | case 4: |
| 32331 | // op: Zn |
| 32332 | return 7; |
| 32333 | } |
| 32334 | break; |
| 32335 | } |
| 32336 | case AArch64::MOVA_VG2_2ZMXI: { |
| 32337 | switch (OpNum) { |
| 32338 | case 2: |
| 32339 | // op: Rs |
| 32340 | return 13; |
| 32341 | case 3: |
| 32342 | // op: imm |
| 32343 | return 5; |
| 32344 | case 0: |
| 32345 | // op: Zd |
| 32346 | return 1; |
| 32347 | } |
| 32348 | break; |
| 32349 | } |
| 32350 | case AArch64::MOVA_VG4_4ZMXI: { |
| 32351 | switch (OpNum) { |
| 32352 | case 2: |
| 32353 | // op: Rs |
| 32354 | return 13; |
| 32355 | case 3: |
| 32356 | // op: imm |
| 32357 | return 5; |
| 32358 | case 0: |
| 32359 | // op: Zd |
| 32360 | return 2; |
| 32361 | } |
| 32362 | break; |
| 32363 | } |
| 32364 | case AArch64::MOVA_MXI2Z_H_D: |
| 32365 | case AArch64::MOVA_MXI2Z_V_D: { |
| 32366 | switch (OpNum) { |
| 32367 | case 2: |
| 32368 | // op: Rs |
| 32369 | return 13; |
| 32370 | case 4: |
| 32371 | // op: Zn |
| 32372 | return 6; |
| 32373 | case 0: |
| 32374 | // op: ZAd |
| 32375 | return 0; |
| 32376 | } |
| 32377 | break; |
| 32378 | } |
| 32379 | case AArch64::MOVA_MXI2Z_H_S: |
| 32380 | case AArch64::MOVA_MXI2Z_V_S: { |
| 32381 | switch (OpNum) { |
| 32382 | case 2: |
| 32383 | // op: Rs |
| 32384 | return 13; |
| 32385 | case 4: |
| 32386 | // op: Zn |
| 32387 | return 6; |
| 32388 | case 0: |
| 32389 | // op: ZAd |
| 32390 | return 1; |
| 32391 | case 3: |
| 32392 | // op: imm |
| 32393 | return 0; |
| 32394 | } |
| 32395 | break; |
| 32396 | } |
| 32397 | case AArch64::MOVA_MXI2Z_H_H: |
| 32398 | case AArch64::MOVA_MXI2Z_V_H: { |
| 32399 | switch (OpNum) { |
| 32400 | case 2: |
| 32401 | // op: Rs |
| 32402 | return 13; |
| 32403 | case 4: |
| 32404 | // op: Zn |
| 32405 | return 6; |
| 32406 | case 0: |
| 32407 | // op: ZAd |
| 32408 | return 2; |
| 32409 | case 3: |
| 32410 | // op: imm |
| 32411 | return 0; |
| 32412 | } |
| 32413 | break; |
| 32414 | } |
| 32415 | case AArch64::MOVA_MXI2Z_H_B: |
| 32416 | case AArch64::MOVA_MXI2Z_V_B: { |
| 32417 | switch (OpNum) { |
| 32418 | case 2: |
| 32419 | // op: Rs |
| 32420 | return 13; |
| 32421 | case 4: |
| 32422 | // op: Zn |
| 32423 | return 6; |
| 32424 | case 3: |
| 32425 | // op: imm |
| 32426 | return 0; |
| 32427 | } |
| 32428 | break; |
| 32429 | } |
| 32430 | case AArch64::MOVA_MXI4Z_H_D: |
| 32431 | case AArch64::MOVA_MXI4Z_H_S: |
| 32432 | case AArch64::MOVA_MXI4Z_V_D: |
| 32433 | case AArch64::MOVA_MXI4Z_V_S: { |
| 32434 | switch (OpNum) { |
| 32435 | case 2: |
| 32436 | // op: Rs |
| 32437 | return 13; |
| 32438 | case 4: |
| 32439 | // op: Zn |
| 32440 | return 7; |
| 32441 | case 0: |
| 32442 | // op: ZAd |
| 32443 | return 0; |
| 32444 | } |
| 32445 | break; |
| 32446 | } |
| 32447 | case AArch64::MOVA_MXI4Z_H_H: |
| 32448 | case AArch64::MOVA_MXI4Z_V_H: { |
| 32449 | switch (OpNum) { |
| 32450 | case 2: |
| 32451 | // op: Rs |
| 32452 | return 13; |
| 32453 | case 4: |
| 32454 | // op: Zn |
| 32455 | return 7; |
| 32456 | case 0: |
| 32457 | // op: ZAd |
| 32458 | return 1; |
| 32459 | case 3: |
| 32460 | // op: imm |
| 32461 | return 0; |
| 32462 | } |
| 32463 | break; |
| 32464 | } |
| 32465 | case AArch64::MOVA_MXI4Z_H_B: |
| 32466 | case AArch64::MOVA_MXI4Z_V_B: { |
| 32467 | switch (OpNum) { |
| 32468 | case 2: |
| 32469 | // op: Rs |
| 32470 | return 13; |
| 32471 | case 4: |
| 32472 | // op: Zn |
| 32473 | return 7; |
| 32474 | case 3: |
| 32475 | // op: imm |
| 32476 | return 0; |
| 32477 | } |
| 32478 | break; |
| 32479 | } |
| 32480 | case AArch64::LDCLRP: |
| 32481 | case AArch64::LDCLRPA: |
| 32482 | case AArch64::LDCLRPAL: |
| 32483 | case AArch64::LDCLRPL: |
| 32484 | case AArch64::LDSETP: |
| 32485 | case AArch64::LDSETPA: |
| 32486 | case AArch64::LDSETPAL: |
| 32487 | case AArch64::LDSETPL: |
| 32488 | case AArch64::SWPP: |
| 32489 | case AArch64::SWPPA: |
| 32490 | case AArch64::SWPPAL: |
| 32491 | case AArch64::SWPPL: { |
| 32492 | switch (OpNum) { |
| 32493 | case 2: |
| 32494 | // op: Rt |
| 32495 | return 0; |
| 32496 | case 3: |
| 32497 | // op: Rt2 |
| 32498 | return 16; |
| 32499 | case 4: |
| 32500 | // op: Rn |
| 32501 | return 5; |
| 32502 | } |
| 32503 | break; |
| 32504 | } |
| 32505 | case AArch64::ZERO_MXI_2Z: |
| 32506 | case AArch64::ZERO_MXI_4Z: |
| 32507 | case AArch64::ZERO_MXI_VG2_2Z: |
| 32508 | case AArch64::ZERO_MXI_VG2_4Z: |
| 32509 | case AArch64::ZERO_MXI_VG2_Z: |
| 32510 | case AArch64::ZERO_MXI_VG4_2Z: |
| 32511 | case AArch64::ZERO_MXI_VG4_4Z: |
| 32512 | case AArch64::ZERO_MXI_VG4_Z: { |
| 32513 | switch (OpNum) { |
| 32514 | case 2: |
| 32515 | // op: Rv |
| 32516 | return 13; |
| 32517 | case 3: |
| 32518 | // op: imm |
| 32519 | return 0; |
| 32520 | } |
| 32521 | break; |
| 32522 | } |
| 32523 | case AArch64::ADD_VG2_M2Z_D: |
| 32524 | case AArch64::ADD_VG2_M2Z_S: |
| 32525 | case AArch64::BFADD_VG2_M2Z_H: |
| 32526 | case AArch64::BFSUB_VG2_M2Z_H: |
| 32527 | case AArch64::FADD_VG2_M2Z_D: |
| 32528 | case AArch64::FADD_VG2_M2Z_H: |
| 32529 | case AArch64::FADD_VG2_M2Z_S: |
| 32530 | case AArch64::FSUB_VG2_M2Z_D: |
| 32531 | case AArch64::FSUB_VG2_M2Z_H: |
| 32532 | case AArch64::FSUB_VG2_M2Z_S: |
| 32533 | case AArch64::SUB_VG2_M2Z_D: |
| 32534 | case AArch64::SUB_VG2_M2Z_S: { |
| 32535 | switch (OpNum) { |
| 32536 | case 2: |
| 32537 | // op: Rv |
| 32538 | return 13; |
| 32539 | case 3: |
| 32540 | // op: imm3 |
| 32541 | return 0; |
| 32542 | case 4: |
| 32543 | // op: Zm |
| 32544 | return 6; |
| 32545 | } |
| 32546 | break; |
| 32547 | } |
| 32548 | case AArch64::ADD_VG4_M4Z_D: |
| 32549 | case AArch64::ADD_VG4_M4Z_S: |
| 32550 | case AArch64::BFADD_VG4_M4Z_H: |
| 32551 | case AArch64::BFSUB_VG4_M4Z_H: |
| 32552 | case AArch64::FADD_VG4_M4Z_D: |
| 32553 | case AArch64::FADD_VG4_M4Z_H: |
| 32554 | case AArch64::FADD_VG4_M4Z_S: |
| 32555 | case AArch64::FSUB_VG4_M4Z_D: |
| 32556 | case AArch64::FSUB_VG4_M4Z_H: |
| 32557 | case AArch64::FSUB_VG4_M4Z_S: |
| 32558 | case AArch64::SUB_VG4_M4Z_D: |
| 32559 | case AArch64::SUB_VG4_M4Z_S: { |
| 32560 | switch (OpNum) { |
| 32561 | case 2: |
| 32562 | // op: Rv |
| 32563 | return 13; |
| 32564 | case 3: |
| 32565 | // op: imm3 |
| 32566 | return 0; |
| 32567 | case 4: |
| 32568 | // op: Zm |
| 32569 | return 7; |
| 32570 | } |
| 32571 | break; |
| 32572 | } |
| 32573 | case AArch64::INSERT_MXIPZ_H_Q: |
| 32574 | case AArch64::INSERT_MXIPZ_V_Q: { |
| 32575 | switch (OpNum) { |
| 32576 | case 2: |
| 32577 | // op: Rv |
| 32578 | return 13; |
| 32579 | case 4: |
| 32580 | // op: Pg |
| 32581 | return 10; |
| 32582 | case 5: |
| 32583 | // op: Zn |
| 32584 | return 5; |
| 32585 | case 0: |
| 32586 | // op: ZAd |
| 32587 | return 0; |
| 32588 | } |
| 32589 | break; |
| 32590 | } |
| 32591 | case AArch64::INSERT_MXIPZ_H_D: |
| 32592 | case AArch64::INSERT_MXIPZ_V_D: { |
| 32593 | switch (OpNum) { |
| 32594 | case 2: |
| 32595 | // op: Rv |
| 32596 | return 13; |
| 32597 | case 4: |
| 32598 | // op: Pg |
| 32599 | return 10; |
| 32600 | case 5: |
| 32601 | // op: Zn |
| 32602 | return 5; |
| 32603 | case 0: |
| 32604 | // op: ZAd |
| 32605 | return 1; |
| 32606 | case 3: |
| 32607 | // op: imm |
| 32608 | return 0; |
| 32609 | } |
| 32610 | break; |
| 32611 | } |
| 32612 | case AArch64::INSERT_MXIPZ_H_S: |
| 32613 | case AArch64::INSERT_MXIPZ_V_S: { |
| 32614 | switch (OpNum) { |
| 32615 | case 2: |
| 32616 | // op: Rv |
| 32617 | return 13; |
| 32618 | case 4: |
| 32619 | // op: Pg |
| 32620 | return 10; |
| 32621 | case 5: |
| 32622 | // op: Zn |
| 32623 | return 5; |
| 32624 | case 0: |
| 32625 | // op: ZAd |
| 32626 | return 2; |
| 32627 | case 3: |
| 32628 | // op: imm |
| 32629 | return 0; |
| 32630 | } |
| 32631 | break; |
| 32632 | } |
| 32633 | case AArch64::INSERT_MXIPZ_H_H: |
| 32634 | case AArch64::INSERT_MXIPZ_V_H: { |
| 32635 | switch (OpNum) { |
| 32636 | case 2: |
| 32637 | // op: Rv |
| 32638 | return 13; |
| 32639 | case 4: |
| 32640 | // op: Pg |
| 32641 | return 10; |
| 32642 | case 5: |
| 32643 | // op: Zn |
| 32644 | return 5; |
| 32645 | case 0: |
| 32646 | // op: ZAd |
| 32647 | return 3; |
| 32648 | case 3: |
| 32649 | // op: imm |
| 32650 | return 0; |
| 32651 | } |
| 32652 | break; |
| 32653 | } |
| 32654 | case AArch64::INSERT_MXIPZ_H_B: |
| 32655 | case AArch64::INSERT_MXIPZ_V_B: { |
| 32656 | switch (OpNum) { |
| 32657 | case 2: |
| 32658 | // op: Rv |
| 32659 | return 13; |
| 32660 | case 4: |
| 32661 | // op: Pg |
| 32662 | return 10; |
| 32663 | case 5: |
| 32664 | // op: Zn |
| 32665 | return 5; |
| 32666 | case 3: |
| 32667 | // op: imm |
| 32668 | return 0; |
| 32669 | } |
| 32670 | break; |
| 32671 | } |
| 32672 | case AArch64::BFMLAL_MZZ_HtoS: |
| 32673 | case AArch64::BFMLAL_VG2_M2ZZ_HtoS: |
| 32674 | case AArch64::BFMLAL_VG4_M4ZZ_HtoS: |
| 32675 | case AArch64::BFMLSL_MZZ_HtoS: |
| 32676 | case AArch64::BFMLSL_VG2_M2ZZ_HtoS: |
| 32677 | case AArch64::BFMLSL_VG4_M4ZZ_HtoS: |
| 32678 | case AArch64::FMLAL_MZZ_HtoS: |
| 32679 | case AArch64::FMLAL_VG2_M2ZZ_BtoH: |
| 32680 | case AArch64::FMLAL_VG2_M2ZZ_HtoS: |
| 32681 | case AArch64::FMLAL_VG2_MZZ_BtoH: |
| 32682 | case AArch64::FMLAL_VG4_M4ZZ_BtoH: |
| 32683 | case AArch64::FMLAL_VG4_M4ZZ_HtoS: |
| 32684 | case AArch64::FMLSL_MZZ_HtoS: |
| 32685 | case AArch64::FMLSL_VG2_M2ZZ_HtoS: |
| 32686 | case AArch64::FMLSL_VG4_M4ZZ_HtoS: |
| 32687 | case AArch64::SMLAL_MZZ_HtoS: |
| 32688 | case AArch64::SMLAL_VG2_M2ZZ_HtoS: |
| 32689 | case AArch64::SMLAL_VG4_M4ZZ_HtoS: |
| 32690 | case AArch64::SMLSL_MZZ_HtoS: |
| 32691 | case AArch64::SMLSL_VG2_M2ZZ_HtoS: |
| 32692 | case AArch64::SMLSL_VG4_M4ZZ_HtoS: |
| 32693 | case AArch64::UMLAL_MZZ_HtoS: |
| 32694 | case AArch64::UMLAL_VG2_M2ZZ_HtoS: |
| 32695 | case AArch64::UMLAL_VG4_M4ZZ_HtoS: |
| 32696 | case AArch64::UMLSL_MZZ_HtoS: |
| 32697 | case AArch64::UMLSL_VG2_M2ZZ_HtoS: |
| 32698 | case AArch64::UMLSL_VG4_M4ZZ_HtoS: { |
| 32699 | switch (OpNum) { |
| 32700 | case 2: |
| 32701 | // op: Rv |
| 32702 | return 13; |
| 32703 | case 5: |
| 32704 | // op: Zm |
| 32705 | return 16; |
| 32706 | case 4: |
| 32707 | // op: Zn |
| 32708 | return 5; |
| 32709 | case 3: |
| 32710 | // op: imm |
| 32711 | return 0; |
| 32712 | } |
| 32713 | break; |
| 32714 | } |
| 32715 | case AArch64::BFMLAL_VG2_M2Z2Z_HtoS: |
| 32716 | case AArch64::BFMLSL_VG2_M2Z2Z_HtoS: |
| 32717 | case AArch64::FMLAL_VG2_M2Z2Z_BtoH: |
| 32718 | case AArch64::FMLAL_VG2_M2Z2Z_HtoS: |
| 32719 | case AArch64::FMLSL_VG2_M2Z2Z_HtoS: |
| 32720 | case AArch64::SMLAL_VG2_M2Z2Z_HtoS: |
| 32721 | case AArch64::SMLSL_VG2_M2Z2Z_HtoS: |
| 32722 | case AArch64::UMLAL_VG2_M2Z2Z_HtoS: |
| 32723 | case AArch64::UMLSL_VG2_M2Z2Z_HtoS: { |
| 32724 | switch (OpNum) { |
| 32725 | case 2: |
| 32726 | // op: Rv |
| 32727 | return 13; |
| 32728 | case 5: |
| 32729 | // op: Zm |
| 32730 | return 17; |
| 32731 | case 4: |
| 32732 | // op: Zn |
| 32733 | return 6; |
| 32734 | case 3: |
| 32735 | // op: imm |
| 32736 | return 0; |
| 32737 | } |
| 32738 | break; |
| 32739 | } |
| 32740 | case AArch64::BFMLAL_VG4_M4Z4Z_HtoS: |
| 32741 | case AArch64::BFMLSL_VG4_M4Z4Z_HtoS: |
| 32742 | case AArch64::FMLAL_VG4_M4Z4Z_BtoH: |
| 32743 | case AArch64::FMLAL_VG4_M4Z4Z_HtoS: |
| 32744 | case AArch64::FMLSL_VG4_M4Z4Z_HtoS: |
| 32745 | case AArch64::SMLAL_VG4_M4Z4Z_HtoS: |
| 32746 | case AArch64::SMLSL_VG4_M4Z4Z_HtoS: |
| 32747 | case AArch64::UMLAL_VG4_M4Z4Z_HtoS: |
| 32748 | case AArch64::UMLSL_VG4_M4Z4Z_HtoS: { |
| 32749 | switch (OpNum) { |
| 32750 | case 2: |
| 32751 | // op: Rv |
| 32752 | return 13; |
| 32753 | case 5: |
| 32754 | // op: Zm |
| 32755 | return 18; |
| 32756 | case 4: |
| 32757 | // op: Zn |
| 32758 | return 7; |
| 32759 | case 3: |
| 32760 | // op: imm |
| 32761 | return 0; |
| 32762 | } |
| 32763 | break; |
| 32764 | } |
| 32765 | case AArch64::INSR_ZV_B: |
| 32766 | case AArch64::INSR_ZV_D: |
| 32767 | case AArch64::INSR_ZV_H: |
| 32768 | case AArch64::INSR_ZV_S: { |
| 32769 | switch (OpNum) { |
| 32770 | case 2: |
| 32771 | // op: Vm |
| 32772 | return 5; |
| 32773 | case 0: |
| 32774 | // op: Zdn |
| 32775 | return 0; |
| 32776 | } |
| 32777 | break; |
| 32778 | } |
| 32779 | case AArch64::LD1i8_POST: |
| 32780 | case AArch64::LD2i8_POST: |
| 32781 | case AArch64::LD3i8_POST: |
| 32782 | case AArch64::LD4i8_POST: { |
| 32783 | switch (OpNum) { |
| 32784 | case 2: |
| 32785 | // op: Vt |
| 32786 | return 0; |
| 32787 | case 4: |
| 32788 | // op: Rn |
| 32789 | return 5; |
| 32790 | case 3: |
| 32791 | // op: idx |
| 32792 | return 10; |
| 32793 | case 5: |
| 32794 | // op: Xm |
| 32795 | return 16; |
| 32796 | } |
| 32797 | break; |
| 32798 | } |
| 32799 | case AArch64::LD1i16_POST: |
| 32800 | case AArch64::LD2i16_POST: |
| 32801 | case AArch64::LD3i16_POST: |
| 32802 | case AArch64::LD4i16_POST: { |
| 32803 | switch (OpNum) { |
| 32804 | case 2: |
| 32805 | // op: Vt |
| 32806 | return 0; |
| 32807 | case 4: |
| 32808 | // op: Rn |
| 32809 | return 5; |
| 32810 | case 3: |
| 32811 | // op: idx |
| 32812 | return 11; |
| 32813 | case 5: |
| 32814 | // op: Xm |
| 32815 | return 16; |
| 32816 | } |
| 32817 | break; |
| 32818 | } |
| 32819 | case AArch64::LD1i32_POST: |
| 32820 | case AArch64::LD2i32_POST: |
| 32821 | case AArch64::LD3i32_POST: |
| 32822 | case AArch64::LD4i32_POST: { |
| 32823 | switch (OpNum) { |
| 32824 | case 2: |
| 32825 | // op: Vt |
| 32826 | return 0; |
| 32827 | case 4: |
| 32828 | // op: Rn |
| 32829 | return 5; |
| 32830 | case 3: |
| 32831 | // op: idx |
| 32832 | return 12; |
| 32833 | case 5: |
| 32834 | // op: Xm |
| 32835 | return 16; |
| 32836 | } |
| 32837 | break; |
| 32838 | } |
| 32839 | case AArch64::LD1i64_POST: |
| 32840 | case AArch64::LD2i64_POST: |
| 32841 | case AArch64::LD3i64_POST: |
| 32842 | case AArch64::LD4i64_POST: { |
| 32843 | switch (OpNum) { |
| 32844 | case 2: |
| 32845 | // op: Vt |
| 32846 | return 0; |
| 32847 | case 4: |
| 32848 | // op: Rn |
| 32849 | return 5; |
| 32850 | case 3: |
| 32851 | // op: idx |
| 32852 | return 30; |
| 32853 | case 5: |
| 32854 | // op: Xm |
| 32855 | return 16; |
| 32856 | } |
| 32857 | break; |
| 32858 | } |
| 32859 | case AArch64::ADD_VG2_2ZZ_B: |
| 32860 | case AArch64::ADD_VG2_2ZZ_D: |
| 32861 | case AArch64::ADD_VG2_2ZZ_H: |
| 32862 | case AArch64::ADD_VG2_2ZZ_S: |
| 32863 | case AArch64::BFMAXNM_VG2_2ZZ_H: |
| 32864 | case AArch64::BFMAX_VG2_2ZZ_H: |
| 32865 | case AArch64::BFMINNM_VG2_2ZZ_H: |
| 32866 | case AArch64::BFMIN_VG2_2ZZ_H: |
| 32867 | case AArch64::BFSCALE_2ZZ: |
| 32868 | case AArch64::FMAXNM_VG2_2ZZ_D: |
| 32869 | case AArch64::FMAXNM_VG2_2ZZ_H: |
| 32870 | case AArch64::FMAXNM_VG2_2ZZ_S: |
| 32871 | case AArch64::FMAX_VG2_2ZZ_D: |
| 32872 | case AArch64::FMAX_VG2_2ZZ_H: |
| 32873 | case AArch64::FMAX_VG2_2ZZ_S: |
| 32874 | case AArch64::FMINNM_VG2_2ZZ_D: |
| 32875 | case AArch64::FMINNM_VG2_2ZZ_H: |
| 32876 | case AArch64::FMINNM_VG2_2ZZ_S: |
| 32877 | case AArch64::FMIN_VG2_2ZZ_D: |
| 32878 | case AArch64::FMIN_VG2_2ZZ_H: |
| 32879 | case AArch64::FMIN_VG2_2ZZ_S: |
| 32880 | case AArch64::FSCALE_2ZZ_D: |
| 32881 | case AArch64::FSCALE_2ZZ_H: |
| 32882 | case AArch64::FSCALE_2ZZ_S: |
| 32883 | case AArch64::SMAX_VG2_2ZZ_B: |
| 32884 | case AArch64::SMAX_VG2_2ZZ_D: |
| 32885 | case AArch64::SMAX_VG2_2ZZ_H: |
| 32886 | case AArch64::SMAX_VG2_2ZZ_S: |
| 32887 | case AArch64::SMIN_VG2_2ZZ_B: |
| 32888 | case AArch64::SMIN_VG2_2ZZ_D: |
| 32889 | case AArch64::SMIN_VG2_2ZZ_H: |
| 32890 | case AArch64::SMIN_VG2_2ZZ_S: |
| 32891 | case AArch64::SQDMULH_VG2_2ZZ_B: |
| 32892 | case AArch64::SQDMULH_VG2_2ZZ_D: |
| 32893 | case AArch64::SQDMULH_VG2_2ZZ_H: |
| 32894 | case AArch64::SQDMULH_VG2_2ZZ_S: |
| 32895 | case AArch64::SRSHL_VG2_2ZZ_B: |
| 32896 | case AArch64::SRSHL_VG2_2ZZ_D: |
| 32897 | case AArch64::SRSHL_VG2_2ZZ_H: |
| 32898 | case AArch64::SRSHL_VG2_2ZZ_S: |
| 32899 | case AArch64::UMAX_VG2_2ZZ_B: |
| 32900 | case AArch64::UMAX_VG2_2ZZ_D: |
| 32901 | case AArch64::UMAX_VG2_2ZZ_H: |
| 32902 | case AArch64::UMAX_VG2_2ZZ_S: |
| 32903 | case AArch64::UMIN_VG2_2ZZ_B: |
| 32904 | case AArch64::UMIN_VG2_2ZZ_D: |
| 32905 | case AArch64::UMIN_VG2_2ZZ_H: |
| 32906 | case AArch64::UMIN_VG2_2ZZ_S: |
| 32907 | case AArch64::URSHL_VG2_2ZZ_B: |
| 32908 | case AArch64::URSHL_VG2_2ZZ_D: |
| 32909 | case AArch64::URSHL_VG2_2ZZ_H: |
| 32910 | case AArch64::URSHL_VG2_2ZZ_S: { |
| 32911 | switch (OpNum) { |
| 32912 | case 2: |
| 32913 | // op: Zm |
| 32914 | return 16; |
| 32915 | case 0: |
| 32916 | // op: Zdn |
| 32917 | return 1; |
| 32918 | } |
| 32919 | break; |
| 32920 | } |
| 32921 | case AArch64::ADD_VG4_4ZZ_B: |
| 32922 | case AArch64::ADD_VG4_4ZZ_D: |
| 32923 | case AArch64::ADD_VG4_4ZZ_H: |
| 32924 | case AArch64::ADD_VG4_4ZZ_S: |
| 32925 | case AArch64::BFMAXNM_VG4_4ZZ_H: |
| 32926 | case AArch64::BFMAX_VG4_4ZZ_H: |
| 32927 | case AArch64::BFMINNM_VG4_4ZZ_H: |
| 32928 | case AArch64::BFMIN_VG4_4ZZ_H: |
| 32929 | case AArch64::BFSCALE_4ZZ: |
| 32930 | case AArch64::FMAXNM_VG4_4ZZ_D: |
| 32931 | case AArch64::FMAXNM_VG4_4ZZ_H: |
| 32932 | case AArch64::FMAXNM_VG4_4ZZ_S: |
| 32933 | case AArch64::FMAX_VG4_4ZZ_D: |
| 32934 | case AArch64::FMAX_VG4_4ZZ_H: |
| 32935 | case AArch64::FMAX_VG4_4ZZ_S: |
| 32936 | case AArch64::FMINNM_VG4_4ZZ_D: |
| 32937 | case AArch64::FMINNM_VG4_4ZZ_H: |
| 32938 | case AArch64::FMINNM_VG4_4ZZ_S: |
| 32939 | case AArch64::FMIN_VG4_4ZZ_D: |
| 32940 | case AArch64::FMIN_VG4_4ZZ_H: |
| 32941 | case AArch64::FMIN_VG4_4ZZ_S: |
| 32942 | case AArch64::FSCALE_4ZZ_D: |
| 32943 | case AArch64::FSCALE_4ZZ_H: |
| 32944 | case AArch64::FSCALE_4ZZ_S: |
| 32945 | case AArch64::SMAX_VG4_4ZZ_B: |
| 32946 | case AArch64::SMAX_VG4_4ZZ_D: |
| 32947 | case AArch64::SMAX_VG4_4ZZ_H: |
| 32948 | case AArch64::SMAX_VG4_4ZZ_S: |
| 32949 | case AArch64::SMIN_VG4_4ZZ_B: |
| 32950 | case AArch64::SMIN_VG4_4ZZ_D: |
| 32951 | case AArch64::SMIN_VG4_4ZZ_H: |
| 32952 | case AArch64::SMIN_VG4_4ZZ_S: |
| 32953 | case AArch64::SQDMULH_VG4_4ZZ_B: |
| 32954 | case AArch64::SQDMULH_VG4_4ZZ_D: |
| 32955 | case AArch64::SQDMULH_VG4_4ZZ_H: |
| 32956 | case AArch64::SQDMULH_VG4_4ZZ_S: |
| 32957 | case AArch64::SRSHL_VG4_4ZZ_B: |
| 32958 | case AArch64::SRSHL_VG4_4ZZ_D: |
| 32959 | case AArch64::SRSHL_VG4_4ZZ_H: |
| 32960 | case AArch64::SRSHL_VG4_4ZZ_S: |
| 32961 | case AArch64::UMAX_VG4_4ZZ_B: |
| 32962 | case AArch64::UMAX_VG4_4ZZ_D: |
| 32963 | case AArch64::UMAX_VG4_4ZZ_H: |
| 32964 | case AArch64::UMAX_VG4_4ZZ_S: |
| 32965 | case AArch64::UMIN_VG4_4ZZ_B: |
| 32966 | case AArch64::UMIN_VG4_4ZZ_D: |
| 32967 | case AArch64::UMIN_VG4_4ZZ_H: |
| 32968 | case AArch64::UMIN_VG4_4ZZ_S: |
| 32969 | case AArch64::URSHL_VG4_4ZZ_B: |
| 32970 | case AArch64::URSHL_VG4_4ZZ_D: |
| 32971 | case AArch64::URSHL_VG4_4ZZ_H: |
| 32972 | case AArch64::URSHL_VG4_4ZZ_S: { |
| 32973 | switch (OpNum) { |
| 32974 | case 2: |
| 32975 | // op: Zm |
| 32976 | return 16; |
| 32977 | case 0: |
| 32978 | // op: Zdn |
| 32979 | return 2; |
| 32980 | } |
| 32981 | break; |
| 32982 | } |
| 32983 | case AArch64::PMULL_2ZZZ_Q: { |
| 32984 | switch (OpNum) { |
| 32985 | case 2: |
| 32986 | // op: Zm |
| 32987 | return 16; |
| 32988 | case 1: |
| 32989 | // op: Zn |
| 32990 | return 5; |
| 32991 | case 0: |
| 32992 | // op: Zd |
| 32993 | return 1; |
| 32994 | } |
| 32995 | break; |
| 32996 | } |
| 32997 | case AArch64::BFMAXNM_VG2_2Z2Z_H: |
| 32998 | case AArch64::BFMAX_VG2_2Z2Z_H: |
| 32999 | case AArch64::BFMINNM_VG2_2Z2Z_H: |
| 33000 | case AArch64::BFMIN_VG2_2Z2Z_H: |
| 33001 | case AArch64::BFSCALE_2Z2Z: |
| 33002 | case AArch64::FAMAX_2Z2Z_D: |
| 33003 | case AArch64::FAMAX_2Z2Z_H: |
| 33004 | case AArch64::FAMAX_2Z2Z_S: |
| 33005 | case AArch64::FAMIN_2Z2Z_D: |
| 33006 | case AArch64::FAMIN_2Z2Z_H: |
| 33007 | case AArch64::FAMIN_2Z2Z_S: |
| 33008 | case AArch64::FMAXNM_VG2_2Z2Z_D: |
| 33009 | case AArch64::FMAXNM_VG2_2Z2Z_H: |
| 33010 | case AArch64::FMAXNM_VG2_2Z2Z_S: |
| 33011 | case AArch64::FMAX_VG2_2Z2Z_D: |
| 33012 | case AArch64::FMAX_VG2_2Z2Z_H: |
| 33013 | case AArch64::FMAX_VG2_2Z2Z_S: |
| 33014 | case AArch64::FMINNM_VG2_2Z2Z_D: |
| 33015 | case AArch64::FMINNM_VG2_2Z2Z_H: |
| 33016 | case AArch64::FMINNM_VG2_2Z2Z_S: |
| 33017 | case AArch64::FMIN_VG2_2Z2Z_D: |
| 33018 | case AArch64::FMIN_VG2_2Z2Z_H: |
| 33019 | case AArch64::FMIN_VG2_2Z2Z_S: |
| 33020 | case AArch64::FSCALE_2Z2Z_D: |
| 33021 | case AArch64::FSCALE_2Z2Z_H: |
| 33022 | case AArch64::FSCALE_2Z2Z_S: |
| 33023 | case AArch64::SMAX_VG2_2Z2Z_B: |
| 33024 | case AArch64::SMAX_VG2_2Z2Z_D: |
| 33025 | case AArch64::SMAX_VG2_2Z2Z_H: |
| 33026 | case AArch64::SMAX_VG2_2Z2Z_S: |
| 33027 | case AArch64::SMIN_VG2_2Z2Z_B: |
| 33028 | case AArch64::SMIN_VG2_2Z2Z_D: |
| 33029 | case AArch64::SMIN_VG2_2Z2Z_H: |
| 33030 | case AArch64::SMIN_VG2_2Z2Z_S: |
| 33031 | case AArch64::SQDMULH_VG2_2Z2Z_B: |
| 33032 | case AArch64::SQDMULH_VG2_2Z2Z_D: |
| 33033 | case AArch64::SQDMULH_VG2_2Z2Z_H: |
| 33034 | case AArch64::SQDMULH_VG2_2Z2Z_S: |
| 33035 | case AArch64::SRSHL_VG2_2Z2Z_B: |
| 33036 | case AArch64::SRSHL_VG2_2Z2Z_D: |
| 33037 | case AArch64::SRSHL_VG2_2Z2Z_H: |
| 33038 | case AArch64::SRSHL_VG2_2Z2Z_S: |
| 33039 | case AArch64::UMAX_VG2_2Z2Z_B: |
| 33040 | case AArch64::UMAX_VG2_2Z2Z_D: |
| 33041 | case AArch64::UMAX_VG2_2Z2Z_H: |
| 33042 | case AArch64::UMAX_VG2_2Z2Z_S: |
| 33043 | case AArch64::UMIN_VG2_2Z2Z_B: |
| 33044 | case AArch64::UMIN_VG2_2Z2Z_D: |
| 33045 | case AArch64::UMIN_VG2_2Z2Z_H: |
| 33046 | case AArch64::UMIN_VG2_2Z2Z_S: |
| 33047 | case AArch64::URSHL_VG2_2Z2Z_B: |
| 33048 | case AArch64::URSHL_VG2_2Z2Z_D: |
| 33049 | case AArch64::URSHL_VG2_2Z2Z_H: |
| 33050 | case AArch64::URSHL_VG2_2Z2Z_S: { |
| 33051 | switch (OpNum) { |
| 33052 | case 2: |
| 33053 | // op: Zm |
| 33054 | return 17; |
| 33055 | case 0: |
| 33056 | // op: Zdn |
| 33057 | return 1; |
| 33058 | } |
| 33059 | break; |
| 33060 | } |
| 33061 | case AArch64::BFMAXNM_VG4_4Z2Z_H: |
| 33062 | case AArch64::BFMAX_VG4_4Z2Z_H: |
| 33063 | case AArch64::BFMINNM_VG4_4Z2Z_H: |
| 33064 | case AArch64::BFMIN_VG4_4Z2Z_H: |
| 33065 | case AArch64::BFSCALE_4Z4Z: |
| 33066 | case AArch64::FAMAX_4Z4Z_D: |
| 33067 | case AArch64::FAMAX_4Z4Z_H: |
| 33068 | case AArch64::FAMAX_4Z4Z_S: |
| 33069 | case AArch64::FAMIN_4Z4Z_D: |
| 33070 | case AArch64::FAMIN_4Z4Z_H: |
| 33071 | case AArch64::FAMIN_4Z4Z_S: |
| 33072 | case AArch64::FMAXNM_VG4_4Z4Z_D: |
| 33073 | case AArch64::FMAXNM_VG4_4Z4Z_H: |
| 33074 | case AArch64::FMAXNM_VG4_4Z4Z_S: |
| 33075 | case AArch64::FMAX_VG4_4Z4Z_D: |
| 33076 | case AArch64::FMAX_VG4_4Z4Z_H: |
| 33077 | case AArch64::FMAX_VG4_4Z4Z_S: |
| 33078 | case AArch64::FMINNM_VG4_4Z4Z_D: |
| 33079 | case AArch64::FMINNM_VG4_4Z4Z_H: |
| 33080 | case AArch64::FMINNM_VG4_4Z4Z_S: |
| 33081 | case AArch64::FMIN_VG4_4Z4Z_D: |
| 33082 | case AArch64::FMIN_VG4_4Z4Z_H: |
| 33083 | case AArch64::FMIN_VG4_4Z4Z_S: |
| 33084 | case AArch64::FSCALE_4Z4Z_D: |
| 33085 | case AArch64::FSCALE_4Z4Z_H: |
| 33086 | case AArch64::FSCALE_4Z4Z_S: |
| 33087 | case AArch64::SMAX_VG4_4Z4Z_B: |
| 33088 | case AArch64::SMAX_VG4_4Z4Z_D: |
| 33089 | case AArch64::SMAX_VG4_4Z4Z_H: |
| 33090 | case AArch64::SMAX_VG4_4Z4Z_S: |
| 33091 | case AArch64::SMIN_VG4_4Z4Z_B: |
| 33092 | case AArch64::SMIN_VG4_4Z4Z_D: |
| 33093 | case AArch64::SMIN_VG4_4Z4Z_H: |
| 33094 | case AArch64::SMIN_VG4_4Z4Z_S: |
| 33095 | case AArch64::SQDMULH_VG4_4Z4Z_B: |
| 33096 | case AArch64::SQDMULH_VG4_4Z4Z_D: |
| 33097 | case AArch64::SQDMULH_VG4_4Z4Z_H: |
| 33098 | case AArch64::SQDMULH_VG4_4Z4Z_S: |
| 33099 | case AArch64::SRSHL_VG4_4Z4Z_B: |
| 33100 | case AArch64::SRSHL_VG4_4Z4Z_D: |
| 33101 | case AArch64::SRSHL_VG4_4Z4Z_H: |
| 33102 | case AArch64::SRSHL_VG4_4Z4Z_S: |
| 33103 | case AArch64::UMAX_VG4_4Z4Z_B: |
| 33104 | case AArch64::UMAX_VG4_4Z4Z_D: |
| 33105 | case AArch64::UMAX_VG4_4Z4Z_H: |
| 33106 | case AArch64::UMAX_VG4_4Z4Z_S: |
| 33107 | case AArch64::UMIN_VG4_4Z4Z_B: |
| 33108 | case AArch64::UMIN_VG4_4Z4Z_D: |
| 33109 | case AArch64::UMIN_VG4_4Z4Z_H: |
| 33110 | case AArch64::UMIN_VG4_4Z4Z_S: |
| 33111 | case AArch64::URSHL_VG4_4Z4Z_B: |
| 33112 | case AArch64::URSHL_VG4_4Z4Z_D: |
| 33113 | case AArch64::URSHL_VG4_4Z4Z_H: |
| 33114 | case AArch64::URSHL_VG4_4Z4Z_S: { |
| 33115 | switch (OpNum) { |
| 33116 | case 2: |
| 33117 | // op: Zm |
| 33118 | return 18; |
| 33119 | case 0: |
| 33120 | // op: Zdn |
| 33121 | return 2; |
| 33122 | } |
| 33123 | break; |
| 33124 | } |
| 33125 | case AArch64::AESDIMC_2ZZI_B: |
| 33126 | case AArch64::AESD_2ZZI_B: |
| 33127 | case AArch64::AESEMC_2ZZI_B: |
| 33128 | case AArch64::AESE_2ZZI_B: { |
| 33129 | switch (OpNum) { |
| 33130 | case 2: |
| 33131 | // op: Zm |
| 33132 | return 5; |
| 33133 | case 0: |
| 33134 | // op: Zdn |
| 33135 | return 1; |
| 33136 | case 3: |
| 33137 | // op: imm2 |
| 33138 | return 19; |
| 33139 | } |
| 33140 | break; |
| 33141 | } |
| 33142 | case AArch64::AESDIMC_4ZZI_B: |
| 33143 | case AArch64::AESD_4ZZI_B: |
| 33144 | case AArch64::AESEMC_4ZZI_B: |
| 33145 | case AArch64::AESE_4ZZI_B: { |
| 33146 | switch (OpNum) { |
| 33147 | case 2: |
| 33148 | // op: Zm |
| 33149 | return 5; |
| 33150 | case 0: |
| 33151 | // op: Zdn |
| 33152 | return 2; |
| 33153 | case 3: |
| 33154 | // op: imm2 |
| 33155 | return 19; |
| 33156 | } |
| 33157 | break; |
| 33158 | } |
| 33159 | case AArch64::FADDV_VPZ_D: |
| 33160 | case AArch64::FADDV_VPZ_H: |
| 33161 | case AArch64::FADDV_VPZ_S: |
| 33162 | case AArch64::FMAXNMV_VPZ_D: |
| 33163 | case AArch64::FMAXNMV_VPZ_H: |
| 33164 | case AArch64::FMAXNMV_VPZ_S: |
| 33165 | case AArch64::FMAXV_VPZ_D: |
| 33166 | case AArch64::FMAXV_VPZ_H: |
| 33167 | case AArch64::FMAXV_VPZ_S: |
| 33168 | case AArch64::FMINNMV_VPZ_D: |
| 33169 | case AArch64::FMINNMV_VPZ_H: |
| 33170 | case AArch64::FMINNMV_VPZ_S: |
| 33171 | case AArch64::FMINV_VPZ_D: |
| 33172 | case AArch64::FMINV_VPZ_H: |
| 33173 | case AArch64::FMINV_VPZ_S: { |
| 33174 | switch (OpNum) { |
| 33175 | case 2: |
| 33176 | // op: Zn |
| 33177 | return 5; |
| 33178 | case 0: |
| 33179 | // op: Vd |
| 33180 | return 0; |
| 33181 | case 1: |
| 33182 | // op: Pg |
| 33183 | return 10; |
| 33184 | } |
| 33185 | break; |
| 33186 | } |
| 33187 | case AArch64::LUTI2_ZTZI_B: |
| 33188 | case AArch64::LUTI2_ZTZI_H: |
| 33189 | case AArch64::LUTI2_ZTZI_S: |
| 33190 | case AArch64::LUTI4_ZTZI_B: |
| 33191 | case AArch64::LUTI4_ZTZI_H: |
| 33192 | case AArch64::LUTI4_ZTZI_S: { |
| 33193 | switch (OpNum) { |
| 33194 | case 2: |
| 33195 | // op: Zn |
| 33196 | return 5; |
| 33197 | case 0: |
| 33198 | // op: Zd |
| 33199 | return 0; |
| 33200 | case 3: |
| 33201 | // op: i |
| 33202 | return 14; |
| 33203 | } |
| 33204 | break; |
| 33205 | } |
| 33206 | case AArch64::LUTI2_S_2ZTZI_B: |
| 33207 | case AArch64::LUTI2_S_2ZTZI_H: |
| 33208 | case AArch64::LUTI4_S_2ZTZI_B: |
| 33209 | case AArch64::LUTI4_S_2ZTZI_H: { |
| 33210 | switch (OpNum) { |
| 33211 | case 2: |
| 33212 | // op: Zn |
| 33213 | return 5; |
| 33214 | case 0: |
| 33215 | // op: Zd |
| 33216 | return 0; |
| 33217 | case 3: |
| 33218 | // op: i |
| 33219 | return 15; |
| 33220 | } |
| 33221 | break; |
| 33222 | } |
| 33223 | case AArch64::LUTI2_S_4ZTZI_B: |
| 33224 | case AArch64::LUTI2_S_4ZTZI_H: |
| 33225 | case AArch64::LUTI4_S_4ZTZI_H: { |
| 33226 | switch (OpNum) { |
| 33227 | case 2: |
| 33228 | // op: Zn |
| 33229 | return 5; |
| 33230 | case 0: |
| 33231 | // op: Zd |
| 33232 | return 0; |
| 33233 | case 3: |
| 33234 | // op: i |
| 33235 | return 16; |
| 33236 | } |
| 33237 | break; |
| 33238 | } |
| 33239 | case AArch64::LUTI2_2ZTZI_B: |
| 33240 | case AArch64::LUTI2_2ZTZI_H: |
| 33241 | case AArch64::LUTI2_2ZTZI_S: |
| 33242 | case AArch64::LUTI4_2ZTZI_B: |
| 33243 | case AArch64::LUTI4_2ZTZI_H: |
| 33244 | case AArch64::LUTI4_2ZTZI_S: { |
| 33245 | switch (OpNum) { |
| 33246 | case 2: |
| 33247 | // op: Zn |
| 33248 | return 5; |
| 33249 | case 0: |
| 33250 | // op: Zd |
| 33251 | return 1; |
| 33252 | case 3: |
| 33253 | // op: i |
| 33254 | return 15; |
| 33255 | } |
| 33256 | break; |
| 33257 | } |
| 33258 | case AArch64::LUTI2_4ZTZI_B: |
| 33259 | case AArch64::LUTI2_4ZTZI_H: |
| 33260 | case AArch64::LUTI2_4ZTZI_S: |
| 33261 | case AArch64::LUTI4_4ZTZI_H: |
| 33262 | case AArch64::LUTI4_4ZTZI_S: { |
| 33263 | switch (OpNum) { |
| 33264 | case 2: |
| 33265 | // op: Zn |
| 33266 | return 5; |
| 33267 | case 0: |
| 33268 | // op: Zd |
| 33269 | return 2; |
| 33270 | case 3: |
| 33271 | // op: i |
| 33272 | return 16; |
| 33273 | } |
| 33274 | break; |
| 33275 | } |
| 33276 | case AArch64::LUTI4_S_4ZZT2Z: { |
| 33277 | switch (OpNum) { |
| 33278 | case 2: |
| 33279 | // op: Zn |
| 33280 | return 6; |
| 33281 | case 0: |
| 33282 | // op: Zd |
| 33283 | return 0; |
| 33284 | } |
| 33285 | break; |
| 33286 | } |
| 33287 | case AArch64::LUTI4_4ZZT2Z: { |
| 33288 | switch (OpNum) { |
| 33289 | case 2: |
| 33290 | // op: Zn |
| 33291 | return 6; |
| 33292 | case 0: |
| 33293 | // op: Zd |
| 33294 | return 2; |
| 33295 | } |
| 33296 | break; |
| 33297 | } |
| 33298 | case AArch64::MOVT_TIZ: { |
| 33299 | switch (OpNum) { |
| 33300 | case 2: |
| 33301 | // op: Zt |
| 33302 | return 0; |
| 33303 | case 1: |
| 33304 | // op: off2 |
| 33305 | return 12; |
| 33306 | } |
| 33307 | break; |
| 33308 | } |
| 33309 | case AArch64::MOVT_XTI: { |
| 33310 | switch (OpNum) { |
| 33311 | case 2: |
| 33312 | // op: imm3 |
| 33313 | return 12; |
| 33314 | case 0: |
| 33315 | // op: Rt |
| 33316 | return 0; |
| 33317 | } |
| 33318 | break; |
| 33319 | } |
| 33320 | case AArch64::SQRSHRU_VG2_Z2ZI_H: |
| 33321 | case AArch64::SQRSHR_VG2_Z2ZI_H: |
| 33322 | case AArch64::UQRSHR_VG2_Z2ZI_H: { |
| 33323 | switch (OpNum) { |
| 33324 | case 2: |
| 33325 | // op: imm4 |
| 33326 | return 16; |
| 33327 | case 1: |
| 33328 | // op: Zn |
| 33329 | return 6; |
| 33330 | case 0: |
| 33331 | // op: Zd |
| 33332 | return 0; |
| 33333 | } |
| 33334 | break; |
| 33335 | } |
| 33336 | case AArch64::LDRAAindexed: |
| 33337 | case AArch64::LDRABindexed: { |
| 33338 | switch (OpNum) { |
| 33339 | case 2: |
| 33340 | // op: offset |
| 33341 | return 12; |
| 33342 | case 1: |
| 33343 | // op: Rn |
| 33344 | return 5; |
| 33345 | case 0: |
| 33346 | // op: Rt |
| 33347 | return 0; |
| 33348 | } |
| 33349 | break; |
| 33350 | } |
| 33351 | case AArch64::ADDHA_MPPZ_D: |
| 33352 | case AArch64::ADDHA_MPPZ_S: |
| 33353 | case AArch64::ADDVA_MPPZ_D: |
| 33354 | case AArch64::ADDVA_MPPZ_S: { |
| 33355 | switch (OpNum) { |
| 33356 | case 3: |
| 33357 | // op: Pm |
| 33358 | return 13; |
| 33359 | case 2: |
| 33360 | // op: Pn |
| 33361 | return 10; |
| 33362 | case 4: |
| 33363 | // op: Zn |
| 33364 | return 5; |
| 33365 | case 0: |
| 33366 | // op: ZAda |
| 33367 | return 0; |
| 33368 | } |
| 33369 | break; |
| 33370 | } |
| 33371 | case AArch64::CPYE: |
| 33372 | case AArch64::CPYEN: |
| 33373 | case AArch64::CPYERN: |
| 33374 | case AArch64::CPYERT: |
| 33375 | case AArch64::CPYERTN: |
| 33376 | case AArch64::CPYERTRN: |
| 33377 | case AArch64::CPYERTWN: |
| 33378 | case AArch64::CPYET: |
| 33379 | case AArch64::CPYETN: |
| 33380 | case AArch64::CPYETRN: |
| 33381 | case AArch64::CPYETWN: |
| 33382 | case AArch64::CPYEWN: |
| 33383 | case AArch64::CPYEWT: |
| 33384 | case AArch64::CPYEWTN: |
| 33385 | case AArch64::CPYEWTRN: |
| 33386 | case AArch64::CPYEWTWN: |
| 33387 | case AArch64::CPYFE: |
| 33388 | case AArch64::CPYFEN: |
| 33389 | case AArch64::CPYFERN: |
| 33390 | case AArch64::CPYFERT: |
| 33391 | case AArch64::CPYFERTN: |
| 33392 | case AArch64::CPYFERTRN: |
| 33393 | case AArch64::CPYFERTWN: |
| 33394 | case AArch64::CPYFET: |
| 33395 | case AArch64::CPYFETN: |
| 33396 | case AArch64::CPYFETRN: |
| 33397 | case AArch64::CPYFETWN: |
| 33398 | case AArch64::CPYFEWN: |
| 33399 | case AArch64::CPYFEWT: |
| 33400 | case AArch64::CPYFEWTN: |
| 33401 | case AArch64::CPYFEWTRN: |
| 33402 | case AArch64::CPYFEWTWN: |
| 33403 | case AArch64::CPYFM: |
| 33404 | case AArch64::CPYFMN: |
| 33405 | case AArch64::CPYFMRN: |
| 33406 | case AArch64::CPYFMRT: |
| 33407 | case AArch64::CPYFMRTN: |
| 33408 | case AArch64::CPYFMRTRN: |
| 33409 | case AArch64::CPYFMRTWN: |
| 33410 | case AArch64::CPYFMT: |
| 33411 | case AArch64::CPYFMTN: |
| 33412 | case AArch64::CPYFMTRN: |
| 33413 | case AArch64::CPYFMTWN: |
| 33414 | case AArch64::CPYFMWN: |
| 33415 | case AArch64::CPYFMWT: |
| 33416 | case AArch64::CPYFMWTN: |
| 33417 | case AArch64::CPYFMWTRN: |
| 33418 | case AArch64::CPYFMWTWN: |
| 33419 | case AArch64::CPYFP: |
| 33420 | case AArch64::CPYFPN: |
| 33421 | case AArch64::CPYFPRN: |
| 33422 | case AArch64::CPYFPRT: |
| 33423 | case AArch64::CPYFPRTN: |
| 33424 | case AArch64::CPYFPRTRN: |
| 33425 | case AArch64::CPYFPRTWN: |
| 33426 | case AArch64::CPYFPT: |
| 33427 | case AArch64::CPYFPTN: |
| 33428 | case AArch64::CPYFPTRN: |
| 33429 | case AArch64::CPYFPTWN: |
| 33430 | case AArch64::CPYFPWN: |
| 33431 | case AArch64::CPYFPWT: |
| 33432 | case AArch64::CPYFPWTN: |
| 33433 | case AArch64::CPYFPWTRN: |
| 33434 | case AArch64::CPYFPWTWN: |
| 33435 | case AArch64::CPYM: |
| 33436 | case AArch64::CPYMN: |
| 33437 | case AArch64::CPYMRN: |
| 33438 | case AArch64::CPYMRT: |
| 33439 | case AArch64::CPYMRTN: |
| 33440 | case AArch64::CPYMRTRN: |
| 33441 | case AArch64::CPYMRTWN: |
| 33442 | case AArch64::CPYMT: |
| 33443 | case AArch64::CPYMTN: |
| 33444 | case AArch64::CPYMTRN: |
| 33445 | case AArch64::CPYMTWN: |
| 33446 | case AArch64::CPYMWN: |
| 33447 | case AArch64::CPYMWT: |
| 33448 | case AArch64::CPYMWTN: |
| 33449 | case AArch64::CPYMWTRN: |
| 33450 | case AArch64::CPYMWTWN: |
| 33451 | case AArch64::CPYP: |
| 33452 | case AArch64::CPYPN: |
| 33453 | case AArch64::CPYPRN: |
| 33454 | case AArch64::CPYPRT: |
| 33455 | case AArch64::CPYPRTN: |
| 33456 | case AArch64::CPYPRTRN: |
| 33457 | case AArch64::CPYPRTWN: |
| 33458 | case AArch64::CPYPT: |
| 33459 | case AArch64::CPYPTN: |
| 33460 | case AArch64::CPYPTRN: |
| 33461 | case AArch64::CPYPTWN: |
| 33462 | case AArch64::CPYPWN: |
| 33463 | case AArch64::CPYPWT: |
| 33464 | case AArch64::CPYPWTN: |
| 33465 | case AArch64::CPYPWTRN: |
| 33466 | case AArch64::CPYPWTWN: { |
| 33467 | switch (OpNum) { |
| 33468 | case 3: |
| 33469 | // op: Rd |
| 33470 | return 0; |
| 33471 | case 4: |
| 33472 | // op: Rs |
| 33473 | return 16; |
| 33474 | case 5: |
| 33475 | // op: Rn |
| 33476 | return 5; |
| 33477 | } |
| 33478 | break; |
| 33479 | } |
| 33480 | case AArch64::LD1B_2Z_STRIDED: |
| 33481 | case AArch64::LD1B_4Z_STRIDED: |
| 33482 | case AArch64::LD1D_2Z_STRIDED: |
| 33483 | case AArch64::LD1D_4Z_STRIDED: |
| 33484 | case AArch64::LD1H_2Z_STRIDED: |
| 33485 | case AArch64::LD1H_4Z_STRIDED: |
| 33486 | case AArch64::LD1W_2Z_STRIDED: |
| 33487 | case AArch64::LD1W_4Z_STRIDED: |
| 33488 | case AArch64::LDNT1B_2Z_STRIDED: |
| 33489 | case AArch64::LDNT1B_4Z_STRIDED: |
| 33490 | case AArch64::LDNT1D_2Z_STRIDED: |
| 33491 | case AArch64::LDNT1D_4Z_STRIDED: |
| 33492 | case AArch64::LDNT1H_2Z_STRIDED: |
| 33493 | case AArch64::LDNT1H_4Z_STRIDED: |
| 33494 | case AArch64::LDNT1W_2Z_STRIDED: |
| 33495 | case AArch64::LDNT1W_4Z_STRIDED: |
| 33496 | case AArch64::ST1B_2Z_STRIDED: |
| 33497 | case AArch64::ST1B_4Z_STRIDED: |
| 33498 | case AArch64::ST1D_2Z_STRIDED: |
| 33499 | case AArch64::ST1D_4Z_STRIDED: |
| 33500 | case AArch64::ST1H_2Z_STRIDED: |
| 33501 | case AArch64::ST1H_4Z_STRIDED: |
| 33502 | case AArch64::ST1W_2Z_STRIDED: |
| 33503 | case AArch64::ST1W_4Z_STRIDED: |
| 33504 | case AArch64::STNT1B_2Z_STRIDED: |
| 33505 | case AArch64::STNT1B_4Z_STRIDED: |
| 33506 | case AArch64::STNT1D_2Z_STRIDED: |
| 33507 | case AArch64::STNT1D_4Z_STRIDED: |
| 33508 | case AArch64::STNT1H_2Z_STRIDED: |
| 33509 | case AArch64::STNT1H_4Z_STRIDED: |
| 33510 | case AArch64::STNT1W_2Z_STRIDED: |
| 33511 | case AArch64::STNT1W_4Z_STRIDED: { |
| 33512 | switch (OpNum) { |
| 33513 | case 3: |
| 33514 | // op: Rm |
| 33515 | return 16; |
| 33516 | case 1: |
| 33517 | // op: PNg |
| 33518 | return 10; |
| 33519 | case 2: |
| 33520 | // op: Rn |
| 33521 | return 5; |
| 33522 | case 0: |
| 33523 | // op: Zt |
| 33524 | return 0; |
| 33525 | } |
| 33526 | break; |
| 33527 | } |
| 33528 | case AArch64::PRFB_PRR: |
| 33529 | case AArch64::PRFD_PRR: |
| 33530 | case AArch64::PRFH_PRR: |
| 33531 | case AArch64::PRFW_PRR: { |
| 33532 | switch (OpNum) { |
| 33533 | case 3: |
| 33534 | // op: Rm |
| 33535 | return 16; |
| 33536 | case 2: |
| 33537 | // op: Rn |
| 33538 | return 5; |
| 33539 | case 1: |
| 33540 | // op: Pg |
| 33541 | return 10; |
| 33542 | case 0: |
| 33543 | // op: prfop |
| 33544 | return 0; |
| 33545 | } |
| 33546 | break; |
| 33547 | } |
| 33548 | case AArch64::MOVAZ_ZMI_H_Q: |
| 33549 | case AArch64::MOVAZ_ZMI_V_Q: { |
| 33550 | switch (OpNum) { |
| 33551 | case 3: |
| 33552 | // op: Rs |
| 33553 | return 13; |
| 33554 | case 0: |
| 33555 | // op: Zd |
| 33556 | return 0; |
| 33557 | case 1: |
| 33558 | // op: ZAn |
| 33559 | return 5; |
| 33560 | } |
| 33561 | break; |
| 33562 | } |
| 33563 | case AArch64::MOVAZ_ZMI_H_D: |
| 33564 | case AArch64::MOVAZ_ZMI_V_D: { |
| 33565 | switch (OpNum) { |
| 33566 | case 3: |
| 33567 | // op: Rs |
| 33568 | return 13; |
| 33569 | case 0: |
| 33570 | // op: Zd |
| 33571 | return 0; |
| 33572 | case 1: |
| 33573 | // op: ZAn |
| 33574 | return 6; |
| 33575 | case 4: |
| 33576 | // op: imm |
| 33577 | return 5; |
| 33578 | } |
| 33579 | break; |
| 33580 | } |
| 33581 | case AArch64::MOVAZ_ZMI_H_S: |
| 33582 | case AArch64::MOVAZ_ZMI_V_S: { |
| 33583 | switch (OpNum) { |
| 33584 | case 3: |
| 33585 | // op: Rs |
| 33586 | return 13; |
| 33587 | case 0: |
| 33588 | // op: Zd |
| 33589 | return 0; |
| 33590 | case 1: |
| 33591 | // op: ZAn |
| 33592 | return 7; |
| 33593 | case 4: |
| 33594 | // op: imm |
| 33595 | return 5; |
| 33596 | } |
| 33597 | break; |
| 33598 | } |
| 33599 | case AArch64::MOVAZ_ZMI_H_H: |
| 33600 | case AArch64::MOVAZ_ZMI_V_H: { |
| 33601 | switch (OpNum) { |
| 33602 | case 3: |
| 33603 | // op: Rs |
| 33604 | return 13; |
| 33605 | case 0: |
| 33606 | // op: Zd |
| 33607 | return 0; |
| 33608 | case 1: |
| 33609 | // op: ZAn |
| 33610 | return 8; |
| 33611 | case 4: |
| 33612 | // op: imm |
| 33613 | return 5; |
| 33614 | } |
| 33615 | break; |
| 33616 | } |
| 33617 | case AArch64::MOVAZ_ZMI_H_B: |
| 33618 | case AArch64::MOVAZ_ZMI_V_B: { |
| 33619 | switch (OpNum) { |
| 33620 | case 3: |
| 33621 | // op: Rs |
| 33622 | return 13; |
| 33623 | case 0: |
| 33624 | // op: Zd |
| 33625 | return 0; |
| 33626 | case 4: |
| 33627 | // op: imm |
| 33628 | return 5; |
| 33629 | } |
| 33630 | break; |
| 33631 | } |
| 33632 | case AArch64::MOVAZ_VG2_2ZMXI: { |
| 33633 | switch (OpNum) { |
| 33634 | case 3: |
| 33635 | // op: Rs |
| 33636 | return 13; |
| 33637 | case 4: |
| 33638 | // op: imm |
| 33639 | return 5; |
| 33640 | case 0: |
| 33641 | // op: Zd |
| 33642 | return 1; |
| 33643 | } |
| 33644 | break; |
| 33645 | } |
| 33646 | case AArch64::MOVAZ_VG4_4ZMXI: { |
| 33647 | switch (OpNum) { |
| 33648 | case 3: |
| 33649 | // op: Rs |
| 33650 | return 13; |
| 33651 | case 4: |
| 33652 | // op: imm |
| 33653 | return 5; |
| 33654 | case 0: |
| 33655 | // op: Zd |
| 33656 | return 2; |
| 33657 | } |
| 33658 | break; |
| 33659 | } |
| 33660 | case AArch64::RCWCLRP: |
| 33661 | case AArch64::RCWCLRPA: |
| 33662 | case AArch64::RCWCLRPAL: |
| 33663 | case AArch64::RCWCLRPL: |
| 33664 | case AArch64::RCWCLRSP: |
| 33665 | case AArch64::RCWCLRSPA: |
| 33666 | case AArch64::RCWCLRSPAL: |
| 33667 | case AArch64::RCWCLRSPL: |
| 33668 | case AArch64::RCWSETP: |
| 33669 | case AArch64::RCWSETPA: |
| 33670 | case AArch64::RCWSETPAL: |
| 33671 | case AArch64::RCWSETPL: |
| 33672 | case AArch64::RCWSETSP: |
| 33673 | case AArch64::RCWSETSPA: |
| 33674 | case AArch64::RCWSETSPAL: |
| 33675 | case AArch64::RCWSETSPL: |
| 33676 | case AArch64::RCWSWPP: |
| 33677 | case AArch64::RCWSWPPA: |
| 33678 | case AArch64::RCWSWPPAL: |
| 33679 | case AArch64::RCWSWPPL: |
| 33680 | case AArch64::RCWSWPSP: |
| 33681 | case AArch64::RCWSWPSPA: |
| 33682 | case AArch64::RCWSWPSPAL: |
| 33683 | case AArch64::RCWSWPSPL: { |
| 33684 | switch (OpNum) { |
| 33685 | case 3: |
| 33686 | // op: Rt2 |
| 33687 | return 16; |
| 33688 | case 4: |
| 33689 | // op: Rn |
| 33690 | return 5; |
| 33691 | case 2: |
| 33692 | // op: Rt |
| 33693 | return 0; |
| 33694 | } |
| 33695 | break; |
| 33696 | } |
| 33697 | case AArch64::PSEL_PPPRI_B: { |
| 33698 | switch (OpNum) { |
| 33699 | case 3: |
| 33700 | // op: Rv |
| 33701 | return 16; |
| 33702 | case 1: |
| 33703 | // op: Pn |
| 33704 | return 10; |
| 33705 | case 2: |
| 33706 | // op: Pm |
| 33707 | return 5; |
| 33708 | case 0: |
| 33709 | // op: Pd |
| 33710 | return 0; |
| 33711 | case 4: |
| 33712 | // op: imm |
| 33713 | return 19; |
| 33714 | } |
| 33715 | break; |
| 33716 | } |
| 33717 | case AArch64::PSEL_PPPRI_H: { |
| 33718 | switch (OpNum) { |
| 33719 | case 3: |
| 33720 | // op: Rv |
| 33721 | return 16; |
| 33722 | case 1: |
| 33723 | // op: Pn |
| 33724 | return 10; |
| 33725 | case 2: |
| 33726 | // op: Pm |
| 33727 | return 5; |
| 33728 | case 0: |
| 33729 | // op: Pd |
| 33730 | return 0; |
| 33731 | case 4: |
| 33732 | // op: imm |
| 33733 | return 20; |
| 33734 | } |
| 33735 | break; |
| 33736 | } |
| 33737 | case AArch64::PSEL_PPPRI_S: { |
| 33738 | switch (OpNum) { |
| 33739 | case 3: |
| 33740 | // op: Rv |
| 33741 | return 16; |
| 33742 | case 1: |
| 33743 | // op: Pn |
| 33744 | return 10; |
| 33745 | case 2: |
| 33746 | // op: Pm |
| 33747 | return 5; |
| 33748 | case 0: |
| 33749 | // op: Pd |
| 33750 | return 0; |
| 33751 | case 4: |
| 33752 | // op: imm |
| 33753 | return 22; |
| 33754 | } |
| 33755 | break; |
| 33756 | } |
| 33757 | case AArch64::PSEL_PPPRI_D: { |
| 33758 | switch (OpNum) { |
| 33759 | case 3: |
| 33760 | // op: Rv |
| 33761 | return 16; |
| 33762 | case 1: |
| 33763 | // op: Pn |
| 33764 | return 10; |
| 33765 | case 2: |
| 33766 | // op: Pm |
| 33767 | return 5; |
| 33768 | case 0: |
| 33769 | // op: Pd |
| 33770 | return 0; |
| 33771 | case 4: |
| 33772 | // op: imm |
| 33773 | return 23; |
| 33774 | } |
| 33775 | break; |
| 33776 | } |
| 33777 | case AArch64::BFCLAMP_ZZZ: |
| 33778 | case AArch64::FCLAMP_ZZZ_D: |
| 33779 | case AArch64::FCLAMP_ZZZ_H: |
| 33780 | case AArch64::FCLAMP_ZZZ_S: |
| 33781 | case AArch64::SCLAMP_ZZZ_B: |
| 33782 | case AArch64::SCLAMP_ZZZ_D: |
| 33783 | case AArch64::SCLAMP_ZZZ_H: |
| 33784 | case AArch64::SCLAMP_ZZZ_S: |
| 33785 | case AArch64::UCLAMP_ZZZ_B: |
| 33786 | case AArch64::UCLAMP_ZZZ_D: |
| 33787 | case AArch64::UCLAMP_ZZZ_H: |
| 33788 | case AArch64::UCLAMP_ZZZ_S: { |
| 33789 | switch (OpNum) { |
| 33790 | case 3: |
| 33791 | // op: Zm |
| 33792 | return 16; |
| 33793 | case 2: |
| 33794 | // op: Zn |
| 33795 | return 5; |
| 33796 | case 0: |
| 33797 | // op: Zd |
| 33798 | return 0; |
| 33799 | } |
| 33800 | break; |
| 33801 | } |
| 33802 | case AArch64::BFCLAMP_VG2_2ZZZ_H: |
| 33803 | case AArch64::FCLAMP_VG2_2Z2Z_D: |
| 33804 | case AArch64::FCLAMP_VG2_2Z2Z_H: |
| 33805 | case AArch64::FCLAMP_VG2_2Z2Z_S: |
| 33806 | case AArch64::SCLAMP_VG2_2Z2Z_B: |
| 33807 | case AArch64::SCLAMP_VG2_2Z2Z_D: |
| 33808 | case AArch64::SCLAMP_VG2_2Z2Z_H: |
| 33809 | case AArch64::SCLAMP_VG2_2Z2Z_S: |
| 33810 | case AArch64::UCLAMP_VG2_2Z2Z_B: |
| 33811 | case AArch64::UCLAMP_VG2_2Z2Z_D: |
| 33812 | case AArch64::UCLAMP_VG2_2Z2Z_H: |
| 33813 | case AArch64::UCLAMP_VG2_2Z2Z_S: { |
| 33814 | switch (OpNum) { |
| 33815 | case 3: |
| 33816 | // op: Zm |
| 33817 | return 16; |
| 33818 | case 2: |
| 33819 | // op: Zn |
| 33820 | return 5; |
| 33821 | case 0: |
| 33822 | // op: Zd |
| 33823 | return 1; |
| 33824 | } |
| 33825 | break; |
| 33826 | } |
| 33827 | case AArch64::BFCLAMP_VG4_4ZZZ_H: |
| 33828 | case AArch64::FCLAMP_VG4_4Z4Z_D: |
| 33829 | case AArch64::FCLAMP_VG4_4Z4Z_H: |
| 33830 | case AArch64::FCLAMP_VG4_4Z4Z_S: |
| 33831 | case AArch64::SCLAMP_VG4_4Z4Z_B: |
| 33832 | case AArch64::SCLAMP_VG4_4Z4Z_D: |
| 33833 | case AArch64::SCLAMP_VG4_4Z4Z_H: |
| 33834 | case AArch64::SCLAMP_VG4_4Z4Z_S: |
| 33835 | case AArch64::UCLAMP_VG4_4Z4Z_B: |
| 33836 | case AArch64::UCLAMP_VG4_4Z4Z_D: |
| 33837 | case AArch64::UCLAMP_VG4_4Z4Z_H: |
| 33838 | case AArch64::UCLAMP_VG4_4Z4Z_S: { |
| 33839 | switch (OpNum) { |
| 33840 | case 3: |
| 33841 | // op: Zm |
| 33842 | return 16; |
| 33843 | case 2: |
| 33844 | // op: Zn |
| 33845 | return 5; |
| 33846 | case 0: |
| 33847 | // op: Zd |
| 33848 | return 2; |
| 33849 | } |
| 33850 | break; |
| 33851 | } |
| 33852 | case AArch64::PMLAL_2ZZZ_Q: { |
| 33853 | switch (OpNum) { |
| 33854 | case 3: |
| 33855 | // op: Zm |
| 33856 | return 16; |
| 33857 | case 2: |
| 33858 | // op: Zn |
| 33859 | return 5; |
| 33860 | case 0: |
| 33861 | // op: Zda |
| 33862 | return 1; |
| 33863 | } |
| 33864 | break; |
| 33865 | } |
| 33866 | case AArch64::LD1B_2Z_STRIDED_IMM: |
| 33867 | case AArch64::LD1B_4Z_STRIDED_IMM: |
| 33868 | case AArch64::LD1D_2Z_STRIDED_IMM: |
| 33869 | case AArch64::LD1D_4Z_STRIDED_IMM: |
| 33870 | case AArch64::LD1H_2Z_STRIDED_IMM: |
| 33871 | case AArch64::LD1H_4Z_STRIDED_IMM: |
| 33872 | case AArch64::LD1W_2Z_STRIDED_IMM: |
| 33873 | case AArch64::LD1W_4Z_STRIDED_IMM: |
| 33874 | case AArch64::LDNT1B_2Z_STRIDED_IMM: |
| 33875 | case AArch64::LDNT1B_4Z_STRIDED_IMM: |
| 33876 | case AArch64::LDNT1D_2Z_STRIDED_IMM: |
| 33877 | case AArch64::LDNT1D_4Z_STRIDED_IMM: |
| 33878 | case AArch64::LDNT1H_2Z_STRIDED_IMM: |
| 33879 | case AArch64::LDNT1H_4Z_STRIDED_IMM: |
| 33880 | case AArch64::LDNT1W_2Z_STRIDED_IMM: |
| 33881 | case AArch64::LDNT1W_4Z_STRIDED_IMM: |
| 33882 | case AArch64::ST1B_2Z_STRIDED_IMM: |
| 33883 | case AArch64::ST1B_4Z_STRIDED_IMM: |
| 33884 | case AArch64::ST1D_2Z_STRIDED_IMM: |
| 33885 | case AArch64::ST1D_4Z_STRIDED_IMM: |
| 33886 | case AArch64::ST1H_2Z_STRIDED_IMM: |
| 33887 | case AArch64::ST1H_4Z_STRIDED_IMM: |
| 33888 | case AArch64::ST1W_2Z_STRIDED_IMM: |
| 33889 | case AArch64::ST1W_4Z_STRIDED_IMM: |
| 33890 | case AArch64::STNT1B_2Z_STRIDED_IMM: |
| 33891 | case AArch64::STNT1B_4Z_STRIDED_IMM: |
| 33892 | case AArch64::STNT1D_2Z_STRIDED_IMM: |
| 33893 | case AArch64::STNT1D_4Z_STRIDED_IMM: |
| 33894 | case AArch64::STNT1H_2Z_STRIDED_IMM: |
| 33895 | case AArch64::STNT1H_4Z_STRIDED_IMM: |
| 33896 | case AArch64::STNT1W_2Z_STRIDED_IMM: |
| 33897 | case AArch64::STNT1W_4Z_STRIDED_IMM: { |
| 33898 | switch (OpNum) { |
| 33899 | case 3: |
| 33900 | // op: imm4 |
| 33901 | return 16; |
| 33902 | case 1: |
| 33903 | // op: PNg |
| 33904 | return 10; |
| 33905 | case 2: |
| 33906 | // op: Rn |
| 33907 | return 5; |
| 33908 | case 0: |
| 33909 | // op: Zt |
| 33910 | return 0; |
| 33911 | } |
| 33912 | break; |
| 33913 | } |
| 33914 | case AArch64::LDRAAwriteback: |
| 33915 | case AArch64::LDRABwriteback: { |
| 33916 | switch (OpNum) { |
| 33917 | case 3: |
| 33918 | // op: offset |
| 33919 | return 12; |
| 33920 | case 2: |
| 33921 | // op: Rn |
| 33922 | return 5; |
| 33923 | case 1: |
| 33924 | // op: Rt |
| 33925 | return 0; |
| 33926 | } |
| 33927 | break; |
| 33928 | } |
| 33929 | case AArch64::SYSPxt: |
| 33930 | case AArch64::SYSxt: { |
| 33931 | switch (OpNum) { |
| 33932 | case 4: |
| 33933 | // op: Rt |
| 33934 | return 0; |
| 33935 | case 0: |
| 33936 | // op: op1 |
| 33937 | return 16; |
| 33938 | case 1: |
| 33939 | // op: Cn |
| 33940 | return 12; |
| 33941 | case 2: |
| 33942 | // op: Cm |
| 33943 | return 8; |
| 33944 | case 3: |
| 33945 | // op: op2 |
| 33946 | return 5; |
| 33947 | } |
| 33948 | break; |
| 33949 | } |
| 33950 | case AArch64::EXTRACT_ZPMXI_H_Q: |
| 33951 | case AArch64::EXTRACT_ZPMXI_V_Q: { |
| 33952 | switch (OpNum) { |
| 33953 | case 4: |
| 33954 | // op: Rv |
| 33955 | return 13; |
| 33956 | case 2: |
| 33957 | // op: Pg |
| 33958 | return 10; |
| 33959 | case 0: |
| 33960 | // op: Zd |
| 33961 | return 0; |
| 33962 | case 3: |
| 33963 | // op: ZAn |
| 33964 | return 5; |
| 33965 | } |
| 33966 | break; |
| 33967 | } |
| 33968 | case AArch64::EXTRACT_ZPMXI_H_D: |
| 33969 | case AArch64::EXTRACT_ZPMXI_V_D: { |
| 33970 | switch (OpNum) { |
| 33971 | case 4: |
| 33972 | // op: Rv |
| 33973 | return 13; |
| 33974 | case 2: |
| 33975 | // op: Pg |
| 33976 | return 10; |
| 33977 | case 0: |
| 33978 | // op: Zd |
| 33979 | return 0; |
| 33980 | case 3: |
| 33981 | // op: ZAn |
| 33982 | return 6; |
| 33983 | case 5: |
| 33984 | // op: imm |
| 33985 | return 5; |
| 33986 | } |
| 33987 | break; |
| 33988 | } |
| 33989 | case AArch64::EXTRACT_ZPMXI_H_S: |
| 33990 | case AArch64::EXTRACT_ZPMXI_V_S: { |
| 33991 | switch (OpNum) { |
| 33992 | case 4: |
| 33993 | // op: Rv |
| 33994 | return 13; |
| 33995 | case 2: |
| 33996 | // op: Pg |
| 33997 | return 10; |
| 33998 | case 0: |
| 33999 | // op: Zd |
| 34000 | return 0; |
| 34001 | case 3: |
| 34002 | // op: ZAn |
| 34003 | return 7; |
| 34004 | case 5: |
| 34005 | // op: imm |
| 34006 | return 5; |
| 34007 | } |
| 34008 | break; |
| 34009 | } |
| 34010 | case AArch64::EXTRACT_ZPMXI_H_H: |
| 34011 | case AArch64::EXTRACT_ZPMXI_V_H: { |
| 34012 | switch (OpNum) { |
| 34013 | case 4: |
| 34014 | // op: Rv |
| 34015 | return 13; |
| 34016 | case 2: |
| 34017 | // op: Pg |
| 34018 | return 10; |
| 34019 | case 0: |
| 34020 | // op: Zd |
| 34021 | return 0; |
| 34022 | case 3: |
| 34023 | // op: ZAn |
| 34024 | return 8; |
| 34025 | case 5: |
| 34026 | // op: imm |
| 34027 | return 5; |
| 34028 | } |
| 34029 | break; |
| 34030 | } |
| 34031 | case AArch64::EXTRACT_ZPMXI_H_B: |
| 34032 | case AArch64::EXTRACT_ZPMXI_V_B: { |
| 34033 | switch (OpNum) { |
| 34034 | case 4: |
| 34035 | // op: Rv |
| 34036 | return 13; |
| 34037 | case 2: |
| 34038 | // op: Pg |
| 34039 | return 10; |
| 34040 | case 0: |
| 34041 | // op: Zd |
| 34042 | return 0; |
| 34043 | case 5: |
| 34044 | // op: imm |
| 34045 | return 5; |
| 34046 | } |
| 34047 | break; |
| 34048 | } |
| 34049 | case AArch64::LD1_MXIPXX_H_Q: |
| 34050 | case AArch64::LD1_MXIPXX_V_Q: |
| 34051 | case AArch64::ST1_MXIPXX_H_Q: |
| 34052 | case AArch64::ST1_MXIPXX_V_Q: { |
| 34053 | switch (OpNum) { |
| 34054 | case 5: |
| 34055 | // op: Rm |
| 34056 | return 16; |
| 34057 | case 1: |
| 34058 | // op: Rv |
| 34059 | return 13; |
| 34060 | case 3: |
| 34061 | // op: Pg |
| 34062 | return 10; |
| 34063 | case 4: |
| 34064 | // op: Rn |
| 34065 | return 5; |
| 34066 | case 0: |
| 34067 | // op: ZAt |
| 34068 | return 0; |
| 34069 | } |
| 34070 | break; |
| 34071 | } |
| 34072 | case AArch64::LD1_MXIPXX_H_D: |
| 34073 | case AArch64::LD1_MXIPXX_V_D: |
| 34074 | case AArch64::ST1_MXIPXX_H_D: |
| 34075 | case AArch64::ST1_MXIPXX_V_D: { |
| 34076 | switch (OpNum) { |
| 34077 | case 5: |
| 34078 | // op: Rm |
| 34079 | return 16; |
| 34080 | case 1: |
| 34081 | // op: Rv |
| 34082 | return 13; |
| 34083 | case 3: |
| 34084 | // op: Pg |
| 34085 | return 10; |
| 34086 | case 4: |
| 34087 | // op: Rn |
| 34088 | return 5; |
| 34089 | case 0: |
| 34090 | // op: ZAt |
| 34091 | return 1; |
| 34092 | case 2: |
| 34093 | // op: imm |
| 34094 | return 0; |
| 34095 | } |
| 34096 | break; |
| 34097 | } |
| 34098 | case AArch64::LD1_MXIPXX_H_S: |
| 34099 | case AArch64::LD1_MXIPXX_V_S: |
| 34100 | case AArch64::ST1_MXIPXX_H_S: |
| 34101 | case AArch64::ST1_MXIPXX_V_S: { |
| 34102 | switch (OpNum) { |
| 34103 | case 5: |
| 34104 | // op: Rm |
| 34105 | return 16; |
| 34106 | case 1: |
| 34107 | // op: Rv |
| 34108 | return 13; |
| 34109 | case 3: |
| 34110 | // op: Pg |
| 34111 | return 10; |
| 34112 | case 4: |
| 34113 | // op: Rn |
| 34114 | return 5; |
| 34115 | case 0: |
| 34116 | // op: ZAt |
| 34117 | return 2; |
| 34118 | case 2: |
| 34119 | // op: imm |
| 34120 | return 0; |
| 34121 | } |
| 34122 | break; |
| 34123 | } |
| 34124 | case AArch64::LD1_MXIPXX_H_H: |
| 34125 | case AArch64::LD1_MXIPXX_V_H: |
| 34126 | case AArch64::ST1_MXIPXX_H_H: |
| 34127 | case AArch64::ST1_MXIPXX_V_H: { |
| 34128 | switch (OpNum) { |
| 34129 | case 5: |
| 34130 | // op: Rm |
| 34131 | return 16; |
| 34132 | case 1: |
| 34133 | // op: Rv |
| 34134 | return 13; |
| 34135 | case 3: |
| 34136 | // op: Pg |
| 34137 | return 10; |
| 34138 | case 4: |
| 34139 | // op: Rn |
| 34140 | return 5; |
| 34141 | case 0: |
| 34142 | // op: ZAt |
| 34143 | return 3; |
| 34144 | case 2: |
| 34145 | // op: imm |
| 34146 | return 0; |
| 34147 | } |
| 34148 | break; |
| 34149 | } |
| 34150 | case AArch64::LD1_MXIPXX_H_B: |
| 34151 | case AArch64::LD1_MXIPXX_V_B: |
| 34152 | case AArch64::ST1_MXIPXX_H_B: |
| 34153 | case AArch64::ST1_MXIPXX_V_B: { |
| 34154 | switch (OpNum) { |
| 34155 | case 5: |
| 34156 | // op: Rm |
| 34157 | return 16; |
| 34158 | case 1: |
| 34159 | // op: Rv |
| 34160 | return 13; |
| 34161 | case 3: |
| 34162 | // op: Pg |
| 34163 | return 10; |
| 34164 | case 4: |
| 34165 | // op: Rn |
| 34166 | return 5; |
| 34167 | case 2: |
| 34168 | // op: imm |
| 34169 | return 0; |
| 34170 | } |
| 34171 | break; |
| 34172 | } |
| 34173 | case AArch64::FMLALL_MZZ_BtoS: |
| 34174 | case AArch64::FMLALL_VG2_M2ZZ_BtoS: |
| 34175 | case AArch64::FMLALL_VG4_M4ZZ_BtoS: |
| 34176 | case AArch64::SMLALL_MZZ_BtoS: |
| 34177 | case AArch64::SMLALL_MZZ_HtoD: |
| 34178 | case AArch64::SMLALL_VG2_M2ZZ_BtoS: |
| 34179 | case AArch64::SMLALL_VG2_M2ZZ_HtoD: |
| 34180 | case AArch64::SMLALL_VG4_M4ZZ_BtoS: |
| 34181 | case AArch64::SMLALL_VG4_M4ZZ_HtoD: |
| 34182 | case AArch64::SMLSLL_MZZ_BtoS: |
| 34183 | case AArch64::SMLSLL_MZZ_HtoD: |
| 34184 | case AArch64::SMLSLL_VG2_M2ZZ_BtoS: |
| 34185 | case AArch64::SMLSLL_VG2_M2ZZ_HtoD: |
| 34186 | case AArch64::SMLSLL_VG4_M4ZZ_BtoS: |
| 34187 | case AArch64::SMLSLL_VG4_M4ZZ_HtoD: |
| 34188 | case AArch64::SUMLALL_VG2_M2ZZ_BtoS: |
| 34189 | case AArch64::SUMLALL_VG4_M4ZZ_BtoS: |
| 34190 | case AArch64::UMLALL_MZZ_BtoS: |
| 34191 | case AArch64::UMLALL_MZZ_HtoD: |
| 34192 | case AArch64::UMLALL_VG2_M2ZZ_BtoS: |
| 34193 | case AArch64::UMLALL_VG2_M2ZZ_HtoD: |
| 34194 | case AArch64::UMLALL_VG4_M4ZZ_BtoS: |
| 34195 | case AArch64::UMLALL_VG4_M4ZZ_HtoD: |
| 34196 | case AArch64::UMLSLL_MZZ_BtoS: |
| 34197 | case AArch64::UMLSLL_MZZ_HtoD: |
| 34198 | case AArch64::UMLSLL_VG2_M2ZZ_BtoS: |
| 34199 | case AArch64::UMLSLL_VG2_M2ZZ_HtoD: |
| 34200 | case AArch64::UMLSLL_VG4_M4ZZ_BtoS: |
| 34201 | case AArch64::UMLSLL_VG4_M4ZZ_HtoD: |
| 34202 | case AArch64::USMLALL_MZZ_BtoS: |
| 34203 | case AArch64::USMLALL_VG2_M2ZZ_BtoS: |
| 34204 | case AArch64::USMLALL_VG4_M4ZZ_BtoS: { |
| 34205 | switch (OpNum) { |
| 34206 | case 5: |
| 34207 | // op: Zm |
| 34208 | return 16; |
| 34209 | case 2: |
| 34210 | // op: Rv |
| 34211 | return 13; |
| 34212 | case 4: |
| 34213 | // op: Zn |
| 34214 | return 5; |
| 34215 | case 3: |
| 34216 | // op: imm |
| 34217 | return 0; |
| 34218 | } |
| 34219 | break; |
| 34220 | } |
| 34221 | case AArch64::BFDOT_VG2_M2ZZI_HtoS: |
| 34222 | case AArch64::BFVDOT_VG2_M2ZZI_HtoS: |
| 34223 | case AArch64::FDOT_VG2_M2ZZI_BtoS: |
| 34224 | case AArch64::FDOT_VG2_M2ZZI_HtoS: |
| 34225 | case AArch64::FMLA_VG2_M2ZZI_S: |
| 34226 | case AArch64::FMLS_VG2_M2ZZI_S: |
| 34227 | case AArch64::FVDOT_VG2_M2ZZI_HtoS: |
| 34228 | case AArch64::SDOT_VG2_M2ZZI_BToS: |
| 34229 | case AArch64::SDOT_VG2_M2ZZI_HToS: |
| 34230 | case AArch64::SUDOT_VG2_M2ZZI_BToS: |
| 34231 | case AArch64::SVDOT_VG2_M2ZZI_HtoS: |
| 34232 | case AArch64::UDOT_VG2_M2ZZI_BToS: |
| 34233 | case AArch64::UDOT_VG2_M2ZZI_HToS: |
| 34234 | case AArch64::USDOT_VG2_M2ZZI_BToS: |
| 34235 | case AArch64::UVDOT_VG2_M2ZZI_HtoS: { |
| 34236 | switch (OpNum) { |
| 34237 | case 5: |
| 34238 | // op: Zm |
| 34239 | return 16; |
| 34240 | case 2: |
| 34241 | // op: Rv |
| 34242 | return 13; |
| 34243 | case 4: |
| 34244 | // op: Zn |
| 34245 | return 6; |
| 34246 | case 3: |
| 34247 | // op: imm3 |
| 34248 | return 0; |
| 34249 | case 6: |
| 34250 | // op: i |
| 34251 | return 10; |
| 34252 | } |
| 34253 | break; |
| 34254 | } |
| 34255 | case AArch64::BFMLA_VG2_M2ZZI: |
| 34256 | case AArch64::BFMLS_VG2_M2ZZI: |
| 34257 | case AArch64::FDOT_VG2_M2ZZI_BtoH: |
| 34258 | case AArch64::FMLA_VG2_M2ZZI_H: |
| 34259 | case AArch64::FMLS_VG2_M2ZZI_H: |
| 34260 | case AArch64::FVDOTB_VG4_M2ZZI_BtoS: |
| 34261 | case AArch64::FVDOTT_VG4_M2ZZI_BtoS: |
| 34262 | case AArch64::FVDOT_VG2_M2ZZI_BtoH: { |
| 34263 | switch (OpNum) { |
| 34264 | case 5: |
| 34265 | // op: Zm |
| 34266 | return 16; |
| 34267 | case 2: |
| 34268 | // op: Rv |
| 34269 | return 13; |
| 34270 | case 4: |
| 34271 | // op: Zn |
| 34272 | return 6; |
| 34273 | case 3: |
| 34274 | // op: imm3 |
| 34275 | return 0; |
| 34276 | case 6: |
| 34277 | // op: i |
| 34278 | return 3; |
| 34279 | } |
| 34280 | break; |
| 34281 | } |
| 34282 | case AArch64::BFDOT_VG4_M4ZZI_HtoS: |
| 34283 | case AArch64::FDOT_VG4_M4ZZI_BtoS: |
| 34284 | case AArch64::FDOT_VG4_M4ZZI_HtoS: |
| 34285 | case AArch64::FMLA_VG4_M4ZZI_S: |
| 34286 | case AArch64::FMLS_VG4_M4ZZI_S: |
| 34287 | case AArch64::SDOT_VG4_M4ZZI_BToS: |
| 34288 | case AArch64::SDOT_VG4_M4ZZI_HToS: |
| 34289 | case AArch64::SUDOT_VG4_M4ZZI_BToS: |
| 34290 | case AArch64::SUVDOT_VG4_M4ZZI_BToS: |
| 34291 | case AArch64::SVDOT_VG4_M4ZZI_BtoS: |
| 34292 | case AArch64::UDOT_VG4_M4ZZI_BtoS: |
| 34293 | case AArch64::UDOT_VG4_M4ZZI_HToS: |
| 34294 | case AArch64::USDOT_VG4_M4ZZI_BToS: |
| 34295 | case AArch64::USVDOT_VG4_M4ZZI_BToS: |
| 34296 | case AArch64::UVDOT_VG4_M4ZZI_BtoS: { |
| 34297 | switch (OpNum) { |
| 34298 | case 5: |
| 34299 | // op: Zm |
| 34300 | return 16; |
| 34301 | case 2: |
| 34302 | // op: Rv |
| 34303 | return 13; |
| 34304 | case 4: |
| 34305 | // op: Zn |
| 34306 | return 7; |
| 34307 | case 3: |
| 34308 | // op: imm3 |
| 34309 | return 0; |
| 34310 | case 6: |
| 34311 | // op: i |
| 34312 | return 10; |
| 34313 | } |
| 34314 | break; |
| 34315 | } |
| 34316 | case AArch64::BFMLA_VG4_M4ZZI: |
| 34317 | case AArch64::BFMLS_VG4_M4ZZI: |
| 34318 | case AArch64::FDOT_VG4_M4ZZI_BtoH: |
| 34319 | case AArch64::FMLA_VG4_M4ZZI_H: |
| 34320 | case AArch64::FMLS_VG4_M4ZZI_H: { |
| 34321 | switch (OpNum) { |
| 34322 | case 5: |
| 34323 | // op: Zm |
| 34324 | return 16; |
| 34325 | case 2: |
| 34326 | // op: Rv |
| 34327 | return 13; |
| 34328 | case 4: |
| 34329 | // op: Zn |
| 34330 | return 7; |
| 34331 | case 3: |
| 34332 | // op: imm3 |
| 34333 | return 0; |
| 34334 | case 6: |
| 34335 | // op: i |
| 34336 | return 3; |
| 34337 | } |
| 34338 | break; |
| 34339 | } |
| 34340 | case AArch64::FMLALL_MZZI_BtoS: |
| 34341 | case AArch64::SMLALL_MZZI_BtoS: |
| 34342 | case AArch64::SMLALL_MZZI_HtoD: |
| 34343 | case AArch64::SMLSLL_MZZI_BtoS: |
| 34344 | case AArch64::SMLSLL_MZZI_HtoD: |
| 34345 | case AArch64::SUMLALL_MZZI_BtoS: |
| 34346 | case AArch64::UMLALL_MZZI_BtoS: |
| 34347 | case AArch64::UMLALL_MZZI_HtoD: |
| 34348 | case AArch64::UMLSLL_MZZI_BtoS: |
| 34349 | case AArch64::UMLSLL_MZZI_HtoD: |
| 34350 | case AArch64::USMLALL_MZZI_BtoS: { |
| 34351 | switch (OpNum) { |
| 34352 | case 5: |
| 34353 | // op: Zm |
| 34354 | return 16; |
| 34355 | case 2: |
| 34356 | // op: Rv |
| 34357 | return 13; |
| 34358 | case 6: |
| 34359 | // op: i |
| 34360 | return 10; |
| 34361 | case 4: |
| 34362 | // op: Zn |
| 34363 | return 5; |
| 34364 | case 3: |
| 34365 | // op: imm2 |
| 34366 | return 0; |
| 34367 | } |
| 34368 | break; |
| 34369 | } |
| 34370 | case AArch64::FMLALL_VG2_M2ZZI_BtoS: |
| 34371 | case AArch64::SMLALL_VG2_M2ZZI_BtoS: |
| 34372 | case AArch64::SMLALL_VG2_M2ZZI_HtoD: |
| 34373 | case AArch64::SMLSLL_VG2_M2ZZI_BtoS: |
| 34374 | case AArch64::SMLSLL_VG2_M2ZZI_HtoD: |
| 34375 | case AArch64::SUMLALL_VG2_M2ZZI_BtoS: |
| 34376 | case AArch64::UMLALL_VG2_M2ZZI_BtoS: |
| 34377 | case AArch64::UMLALL_VG2_M2ZZI_HtoD: |
| 34378 | case AArch64::UMLSLL_VG2_M2ZZI_BtoS: |
| 34379 | case AArch64::UMLSLL_VG2_M2ZZI_HtoD: |
| 34380 | case AArch64::USMLALL_VG2_M2ZZI_BtoS: { |
| 34381 | switch (OpNum) { |
| 34382 | case 5: |
| 34383 | // op: Zm |
| 34384 | return 16; |
| 34385 | case 2: |
| 34386 | // op: Rv |
| 34387 | return 13; |
| 34388 | case 6: |
| 34389 | // op: i |
| 34390 | return 1; |
| 34391 | case 3: |
| 34392 | // op: imm |
| 34393 | return 0; |
| 34394 | case 4: |
| 34395 | // op: Zn |
| 34396 | return 6; |
| 34397 | } |
| 34398 | break; |
| 34399 | } |
| 34400 | case AArch64::FMLALL_VG4_M4ZZI_BtoS: |
| 34401 | case AArch64::SMLALL_VG4_M4ZZI_BtoS: |
| 34402 | case AArch64::SMLALL_VG4_M4ZZI_HtoD: |
| 34403 | case AArch64::SMLSLL_VG4_M4ZZI_BtoS: |
| 34404 | case AArch64::SMLSLL_VG4_M4ZZI_HtoD: |
| 34405 | case AArch64::SUMLALL_VG4_M4ZZI_BtoS: |
| 34406 | case AArch64::UMLALL_VG4_M4ZZI_BtoS: |
| 34407 | case AArch64::UMLALL_VG4_M4ZZI_HtoD: |
| 34408 | case AArch64::UMLSLL_VG4_M4ZZI_BtoS: |
| 34409 | case AArch64::UMLSLL_VG4_M4ZZI_HtoD: |
| 34410 | case AArch64::USMLALL_VG4_M4ZZI_BtoS: { |
| 34411 | switch (OpNum) { |
| 34412 | case 5: |
| 34413 | // op: Zm |
| 34414 | return 16; |
| 34415 | case 2: |
| 34416 | // op: Rv |
| 34417 | return 13; |
| 34418 | case 6: |
| 34419 | // op: i |
| 34420 | return 1; |
| 34421 | case 3: |
| 34422 | // op: imm |
| 34423 | return 0; |
| 34424 | case 4: |
| 34425 | // op: Zn |
| 34426 | return 7; |
| 34427 | } |
| 34428 | break; |
| 34429 | } |
| 34430 | case AArch64::FMLAL_VG2_M2ZZI_BtoH: { |
| 34431 | switch (OpNum) { |
| 34432 | case 5: |
| 34433 | // op: Zm |
| 34434 | return 16; |
| 34435 | case 2: |
| 34436 | // op: Rv |
| 34437 | return 13; |
| 34438 | case 6: |
| 34439 | // op: i |
| 34440 | return 2; |
| 34441 | case 3: |
| 34442 | // op: imm2 |
| 34443 | return 0; |
| 34444 | case 4: |
| 34445 | // op: Zn |
| 34446 | return 6; |
| 34447 | } |
| 34448 | break; |
| 34449 | } |
| 34450 | case AArch64::FMLAL_VG4_M4ZZI_BtoH: { |
| 34451 | switch (OpNum) { |
| 34452 | case 5: |
| 34453 | // op: Zm |
| 34454 | return 16; |
| 34455 | case 2: |
| 34456 | // op: Rv |
| 34457 | return 13; |
| 34458 | case 6: |
| 34459 | // op: i |
| 34460 | return 2; |
| 34461 | case 3: |
| 34462 | // op: imm2 |
| 34463 | return 0; |
| 34464 | case 4: |
| 34465 | // op: Zn |
| 34466 | return 7; |
| 34467 | } |
| 34468 | break; |
| 34469 | } |
| 34470 | case AArch64::FMLAL_MZZI_BtoH: { |
| 34471 | switch (OpNum) { |
| 34472 | case 5: |
| 34473 | // op: Zm |
| 34474 | return 16; |
| 34475 | case 2: |
| 34476 | // op: Rv |
| 34477 | return 13; |
| 34478 | case 6: |
| 34479 | // op: i |
| 34480 | return 3; |
| 34481 | case 4: |
| 34482 | // op: Zn |
| 34483 | return 5; |
| 34484 | case 3: |
| 34485 | // op: imm3 |
| 34486 | return 0; |
| 34487 | } |
| 34488 | break; |
| 34489 | } |
| 34490 | case AArch64::FMLA_VG2_M2ZZI_D: |
| 34491 | case AArch64::FMLS_VG2_M2ZZI_D: |
| 34492 | case AArch64::SDOT_VG2_M2ZZI_HtoD: |
| 34493 | case AArch64::UDOT_VG2_M2ZZI_HtoD: { |
| 34494 | switch (OpNum) { |
| 34495 | case 5: |
| 34496 | // op: Zm |
| 34497 | return 16; |
| 34498 | case 2: |
| 34499 | // op: Rv |
| 34500 | return 13; |
| 34501 | case 6: |
| 34502 | // op: i1 |
| 34503 | return 10; |
| 34504 | case 4: |
| 34505 | // op: Zn |
| 34506 | return 6; |
| 34507 | case 3: |
| 34508 | // op: imm3 |
| 34509 | return 0; |
| 34510 | } |
| 34511 | break; |
| 34512 | } |
| 34513 | case AArch64::FMLA_VG4_M4ZZI_D: |
| 34514 | case AArch64::FMLS_VG4_M4ZZI_D: |
| 34515 | case AArch64::SDOT_VG4_M4ZZI_HtoD: |
| 34516 | case AArch64::SVDOT_VG4_M4ZZI_HtoD: |
| 34517 | case AArch64::UDOT_VG4_M4ZZI_HtoD: |
| 34518 | case AArch64::UVDOT_VG4_M4ZZI_HtoD: { |
| 34519 | switch (OpNum) { |
| 34520 | case 5: |
| 34521 | // op: Zm |
| 34522 | return 16; |
| 34523 | case 2: |
| 34524 | // op: Rv |
| 34525 | return 13; |
| 34526 | case 6: |
| 34527 | // op: i1 |
| 34528 | return 10; |
| 34529 | case 4: |
| 34530 | // op: Zn |
| 34531 | return 7; |
| 34532 | case 3: |
| 34533 | // op: imm3 |
| 34534 | return 0; |
| 34535 | } |
| 34536 | break; |
| 34537 | } |
| 34538 | case AArch64::BFMLAL_MZZI_HtoS: |
| 34539 | case AArch64::BFMLSL_MZZI_HtoS: |
| 34540 | case AArch64::FMLAL_MZZI_HtoS: |
| 34541 | case AArch64::FMLSL_MZZI_HtoS: |
| 34542 | case AArch64::SMLAL_MZZI_HtoS: |
| 34543 | case AArch64::SMLSL_MZZI_HtoS: |
| 34544 | case AArch64::UMLAL_MZZI_HtoS: |
| 34545 | case AArch64::UMLSL_MZZI_HtoS: { |
| 34546 | switch (OpNum) { |
| 34547 | case 5: |
| 34548 | // op: Zm |
| 34549 | return 16; |
| 34550 | case 2: |
| 34551 | // op: Rv |
| 34552 | return 13; |
| 34553 | case 6: |
| 34554 | // op: i3 |
| 34555 | return 10; |
| 34556 | case 4: |
| 34557 | // op: Zn |
| 34558 | return 5; |
| 34559 | case 3: |
| 34560 | // op: imm |
| 34561 | return 0; |
| 34562 | } |
| 34563 | break; |
| 34564 | } |
| 34565 | case AArch64::BFMLAL_VG2_M2ZZI_HtoS: |
| 34566 | case AArch64::BFMLSL_VG2_M2ZZI_HtoS: |
| 34567 | case AArch64::FMLAL_VG2_M2ZZI_HtoS: |
| 34568 | case AArch64::FMLSL_VG2_M2ZZI_HtoS: |
| 34569 | case AArch64::SMLAL_VG2_M2ZZI_S: |
| 34570 | case AArch64::SMLSL_VG2_M2ZZI_S: |
| 34571 | case AArch64::UMLAL_VG2_M2ZZI_S: |
| 34572 | case AArch64::UMLSL_VG2_M2ZZI_S: { |
| 34573 | switch (OpNum) { |
| 34574 | case 5: |
| 34575 | // op: Zm |
| 34576 | return 16; |
| 34577 | case 2: |
| 34578 | // op: Rv |
| 34579 | return 13; |
| 34580 | case 6: |
| 34581 | // op: i3 |
| 34582 | return 2; |
| 34583 | case 4: |
| 34584 | // op: Zn |
| 34585 | return 6; |
| 34586 | case 3: |
| 34587 | // op: imm |
| 34588 | return 0; |
| 34589 | } |
| 34590 | break; |
| 34591 | } |
| 34592 | case AArch64::BFMLAL_VG4_M4ZZI_HtoS: |
| 34593 | case AArch64::BFMLSL_VG4_M4ZZI_HtoS: |
| 34594 | case AArch64::FMLAL_VG4_M4ZZI_HtoS: |
| 34595 | case AArch64::FMLSL_VG4_M4ZZI_HtoS: |
| 34596 | case AArch64::SMLAL_VG4_M4ZZI_HtoS: |
| 34597 | case AArch64::SMLSL_VG4_M4ZZI_HtoS: |
| 34598 | case AArch64::UMLAL_VG4_M4ZZI_HtoS: |
| 34599 | case AArch64::UMLSL_VG4_M4ZZI_HtoS: { |
| 34600 | switch (OpNum) { |
| 34601 | case 5: |
| 34602 | // op: Zm |
| 34603 | return 16; |
| 34604 | case 2: |
| 34605 | // op: Rv |
| 34606 | return 13; |
| 34607 | case 6: |
| 34608 | // op: i3 |
| 34609 | return 2; |
| 34610 | case 4: |
| 34611 | // op: Zn |
| 34612 | return 7; |
| 34613 | case 3: |
| 34614 | // op: imm |
| 34615 | return 0; |
| 34616 | } |
| 34617 | break; |
| 34618 | } |
| 34619 | case AArch64::BFMOPA_MPPZZ: |
| 34620 | case AArch64::BFMOPA_MPPZZ_H: |
| 34621 | case AArch64::BFMOPS_MPPZZ: |
| 34622 | case AArch64::BFMOPS_MPPZZ_H: |
| 34623 | case AArch64::BMOPA_MPPZZ_S: |
| 34624 | case AArch64::BMOPS_MPPZZ_S: |
| 34625 | case AArch64::FMOPAL_MPPZZ: |
| 34626 | case AArch64::FMOPA_MPPZZ_BtoH: |
| 34627 | case AArch64::FMOPA_MPPZZ_BtoS: |
| 34628 | case AArch64::FMOPA_MPPZZ_D: |
| 34629 | case AArch64::FMOPA_MPPZZ_H: |
| 34630 | case AArch64::FMOPA_MPPZZ_S: |
| 34631 | case AArch64::FMOPSL_MPPZZ: |
| 34632 | case AArch64::FMOPS_MPPZZ_D: |
| 34633 | case AArch64::FMOPS_MPPZZ_H: |
| 34634 | case AArch64::FMOPS_MPPZZ_S: |
| 34635 | case AArch64::SMOPA_MPPZZ_D: |
| 34636 | case AArch64::SMOPA_MPPZZ_HtoS: |
| 34637 | case AArch64::SMOPA_MPPZZ_S: |
| 34638 | case AArch64::SMOPS_MPPZZ_D: |
| 34639 | case AArch64::SMOPS_MPPZZ_HtoS: |
| 34640 | case AArch64::SMOPS_MPPZZ_S: |
| 34641 | case AArch64::SUMOPA_MPPZZ_D: |
| 34642 | case AArch64::SUMOPA_MPPZZ_S: |
| 34643 | case AArch64::SUMOPS_MPPZZ_D: |
| 34644 | case AArch64::SUMOPS_MPPZZ_S: |
| 34645 | case AArch64::UMOPA_MPPZZ_D: |
| 34646 | case AArch64::UMOPA_MPPZZ_HtoS: |
| 34647 | case AArch64::UMOPA_MPPZZ_S: |
| 34648 | case AArch64::UMOPS_MPPZZ_D: |
| 34649 | case AArch64::UMOPS_MPPZZ_HtoS: |
| 34650 | case AArch64::UMOPS_MPPZZ_S: |
| 34651 | case AArch64::USMOPA_MPPZZ_D: |
| 34652 | case AArch64::USMOPA_MPPZZ_S: |
| 34653 | case AArch64::USMOPS_MPPZZ_D: |
| 34654 | case AArch64::USMOPS_MPPZZ_S: { |
| 34655 | switch (OpNum) { |
| 34656 | case 5: |
| 34657 | // op: Zm |
| 34658 | return 16; |
| 34659 | case 3: |
| 34660 | // op: Pm |
| 34661 | return 13; |
| 34662 | case 2: |
| 34663 | // op: Pn |
| 34664 | return 10; |
| 34665 | case 4: |
| 34666 | // op: Zn |
| 34667 | return 5; |
| 34668 | case 0: |
| 34669 | // op: ZAda |
| 34670 | return 0; |
| 34671 | } |
| 34672 | break; |
| 34673 | } |
| 34674 | case AArch64::ADD_VG2_M2ZZ_D: |
| 34675 | case AArch64::ADD_VG2_M2ZZ_S: |
| 34676 | case AArch64::ADD_VG4_M4ZZ_D: |
| 34677 | case AArch64::ADD_VG4_M4ZZ_S: |
| 34678 | case AArch64::BFDOT_VG2_M2ZZ_HtoS: |
| 34679 | case AArch64::BFDOT_VG4_M4ZZ_HtoS: |
| 34680 | case AArch64::BFMLA_VG2_M2ZZ: |
| 34681 | case AArch64::BFMLA_VG4_M4ZZ: |
| 34682 | case AArch64::BFMLS_VG2_M2ZZ: |
| 34683 | case AArch64::BFMLS_VG4_M4ZZ: |
| 34684 | case AArch64::FDOT_VG2_M2ZZ_BtoH: |
| 34685 | case AArch64::FDOT_VG2_M2ZZ_BtoS: |
| 34686 | case AArch64::FDOT_VG2_M2ZZ_HtoS: |
| 34687 | case AArch64::FDOT_VG4_M4ZZ_BtoH: |
| 34688 | case AArch64::FDOT_VG4_M4ZZ_BtoS: |
| 34689 | case AArch64::FDOT_VG4_M4ZZ_HtoS: |
| 34690 | case AArch64::FMLA_VG2_M2ZZ_D: |
| 34691 | case AArch64::FMLA_VG2_M2ZZ_H: |
| 34692 | case AArch64::FMLA_VG2_M2ZZ_S: |
| 34693 | case AArch64::FMLA_VG4_M4ZZ_D: |
| 34694 | case AArch64::FMLA_VG4_M4ZZ_H: |
| 34695 | case AArch64::FMLA_VG4_M4ZZ_S: |
| 34696 | case AArch64::FMLS_VG2_M2ZZ_D: |
| 34697 | case AArch64::FMLS_VG2_M2ZZ_H: |
| 34698 | case AArch64::FMLS_VG2_M2ZZ_S: |
| 34699 | case AArch64::FMLS_VG4_M4ZZ_D: |
| 34700 | case AArch64::FMLS_VG4_M4ZZ_H: |
| 34701 | case AArch64::FMLS_VG4_M4ZZ_S: |
| 34702 | case AArch64::SDOT_VG2_M2ZZ_BtoS: |
| 34703 | case AArch64::SDOT_VG2_M2ZZ_HtoD: |
| 34704 | case AArch64::SDOT_VG2_M2ZZ_HtoS: |
| 34705 | case AArch64::SDOT_VG4_M4ZZ_BtoS: |
| 34706 | case AArch64::SDOT_VG4_M4ZZ_HtoD: |
| 34707 | case AArch64::SDOT_VG4_M4ZZ_HtoS: |
| 34708 | case AArch64::SUB_VG2_M2ZZ_D: |
| 34709 | case AArch64::SUB_VG2_M2ZZ_S: |
| 34710 | case AArch64::SUB_VG4_M4ZZ_D: |
| 34711 | case AArch64::SUB_VG4_M4ZZ_S: |
| 34712 | case AArch64::SUDOT_VG2_M2ZZ_BToS: |
| 34713 | case AArch64::SUDOT_VG4_M4ZZ_BToS: |
| 34714 | case AArch64::UDOT_VG2_M2ZZ_BtoS: |
| 34715 | case AArch64::UDOT_VG2_M2ZZ_HtoD: |
| 34716 | case AArch64::UDOT_VG2_M2ZZ_HtoS: |
| 34717 | case AArch64::UDOT_VG4_M4ZZ_BtoS: |
| 34718 | case AArch64::UDOT_VG4_M4ZZ_HtoD: |
| 34719 | case AArch64::UDOT_VG4_M4ZZ_HtoS: |
| 34720 | case AArch64::USDOT_VG2_M2ZZ_BToS: |
| 34721 | case AArch64::USDOT_VG4_M4ZZ_BToS: { |
| 34722 | switch (OpNum) { |
| 34723 | case 5: |
| 34724 | // op: Zm |
| 34725 | return 16; |
| 34726 | case 4: |
| 34727 | // op: Zn |
| 34728 | return 5; |
| 34729 | case 2: |
| 34730 | // op: Rv |
| 34731 | return 13; |
| 34732 | case 3: |
| 34733 | // op: imm3 |
| 34734 | return 0; |
| 34735 | } |
| 34736 | break; |
| 34737 | } |
| 34738 | case AArch64::FMLALL_VG2_M2Z2Z_BtoS: |
| 34739 | case AArch64::SMLALL_VG2_M2Z2Z_BtoS: |
| 34740 | case AArch64::SMLALL_VG2_M2Z2Z_HtoD: |
| 34741 | case AArch64::SMLSLL_VG2_M2Z2Z_BtoS: |
| 34742 | case AArch64::SMLSLL_VG2_M2Z2Z_HtoD: |
| 34743 | case AArch64::UMLALL_VG2_M2Z2Z_BtoS: |
| 34744 | case AArch64::UMLALL_VG2_M2Z2Z_HtoD: |
| 34745 | case AArch64::UMLSLL_VG2_M2Z2Z_BtoS: |
| 34746 | case AArch64::UMLSLL_VG2_M2Z2Z_HtoD: |
| 34747 | case AArch64::USMLALL_VG2_M2Z2Z_BtoS: { |
| 34748 | switch (OpNum) { |
| 34749 | case 5: |
| 34750 | // op: Zm |
| 34751 | return 17; |
| 34752 | case 2: |
| 34753 | // op: Rv |
| 34754 | return 13; |
| 34755 | case 4: |
| 34756 | // op: Zn |
| 34757 | return 6; |
| 34758 | case 3: |
| 34759 | // op: imm |
| 34760 | return 0; |
| 34761 | } |
| 34762 | break; |
| 34763 | } |
| 34764 | case AArch64::ADD_VG2_M2Z2Z_D: |
| 34765 | case AArch64::ADD_VG2_M2Z2Z_S: |
| 34766 | case AArch64::BFDOT_VG2_M2Z2Z_HtoS: |
| 34767 | case AArch64::BFMLA_VG2_M2Z2Z: |
| 34768 | case AArch64::BFMLS_VG2_M2Z2Z: |
| 34769 | case AArch64::FDOT_VG2_M2Z2Z_BtoH: |
| 34770 | case AArch64::FDOT_VG2_M2Z2Z_BtoS: |
| 34771 | case AArch64::FDOT_VG2_M2Z2Z_HtoS: |
| 34772 | case AArch64::FMLA_VG2_M2Z2Z_D: |
| 34773 | case AArch64::FMLA_VG2_M2Z2Z_H: |
| 34774 | case AArch64::FMLA_VG2_M2Z2Z_S: |
| 34775 | case AArch64::FMLS_VG2_M2Z2Z_D: |
| 34776 | case AArch64::FMLS_VG2_M2Z2Z_H: |
| 34777 | case AArch64::FMLS_VG2_M2Z2Z_S: |
| 34778 | case AArch64::SDOT_VG2_M2Z2Z_BtoS: |
| 34779 | case AArch64::SDOT_VG2_M2Z2Z_HtoD: |
| 34780 | case AArch64::SDOT_VG2_M2Z2Z_HtoS: |
| 34781 | case AArch64::SUB_VG2_M2Z2Z_D: |
| 34782 | case AArch64::SUB_VG2_M2Z2Z_S: |
| 34783 | case AArch64::UDOT_VG2_M2Z2Z_BtoS: |
| 34784 | case AArch64::UDOT_VG2_M2Z2Z_HtoD: |
| 34785 | case AArch64::UDOT_VG2_M2Z2Z_HtoS: |
| 34786 | case AArch64::USDOT_VG2_M2Z2Z_BToS: { |
| 34787 | switch (OpNum) { |
| 34788 | case 5: |
| 34789 | // op: Zm |
| 34790 | return 17; |
| 34791 | case 4: |
| 34792 | // op: Zn |
| 34793 | return 6; |
| 34794 | case 2: |
| 34795 | // op: Rv |
| 34796 | return 13; |
| 34797 | case 3: |
| 34798 | // op: imm3 |
| 34799 | return 0; |
| 34800 | } |
| 34801 | break; |
| 34802 | } |
| 34803 | case AArch64::FMLALL_VG4_M4Z4Z_BtoS: |
| 34804 | case AArch64::SMLALL_VG4_M4Z4Z_BtoS: |
| 34805 | case AArch64::SMLALL_VG4_M4Z4Z_HtoD: |
| 34806 | case AArch64::SMLSLL_VG4_M4Z4Z_BtoS: |
| 34807 | case AArch64::SMLSLL_VG4_M4Z4Z_HtoD: |
| 34808 | case AArch64::UMLALL_VG4_M4Z4Z_BtoS: |
| 34809 | case AArch64::UMLALL_VG4_M4Z4Z_HtoD: |
| 34810 | case AArch64::UMLSLL_VG4_M4Z4Z_BtoS: |
| 34811 | case AArch64::UMLSLL_VG4_M4Z4Z_HtoD: |
| 34812 | case AArch64::USMLALL_VG4_M4Z4Z_BtoS: { |
| 34813 | switch (OpNum) { |
| 34814 | case 5: |
| 34815 | // op: Zm |
| 34816 | return 18; |
| 34817 | case 2: |
| 34818 | // op: Rv |
| 34819 | return 13; |
| 34820 | case 4: |
| 34821 | // op: Zn |
| 34822 | return 7; |
| 34823 | case 3: |
| 34824 | // op: imm |
| 34825 | return 0; |
| 34826 | } |
| 34827 | break; |
| 34828 | } |
| 34829 | case AArch64::ADD_VG4_M4Z4Z_D: |
| 34830 | case AArch64::ADD_VG4_M4Z4Z_S: |
| 34831 | case AArch64::BFDOT_VG4_M4Z4Z_HtoS: |
| 34832 | case AArch64::BFMLA_VG4_M4Z4Z: |
| 34833 | case AArch64::BFMLS_VG4_M4Z4Z: |
| 34834 | case AArch64::FDOT_VG4_M4Z4Z_BtoH: |
| 34835 | case AArch64::FDOT_VG4_M4Z4Z_BtoS: |
| 34836 | case AArch64::FDOT_VG4_M4Z4Z_HtoS: |
| 34837 | case AArch64::FMLA_VG4_M4Z4Z_D: |
| 34838 | case AArch64::FMLA_VG4_M4Z4Z_H: |
| 34839 | case AArch64::FMLA_VG4_M4Z4Z_S: |
| 34840 | case AArch64::FMLS_VG4_M4Z4Z_D: |
| 34841 | case AArch64::FMLS_VG4_M4Z4Z_H: |
| 34842 | case AArch64::FMLS_VG4_M4Z4Z_S: |
| 34843 | case AArch64::SDOT_VG4_M4Z4Z_BtoS: |
| 34844 | case AArch64::SDOT_VG4_M4Z4Z_HtoD: |
| 34845 | case AArch64::SDOT_VG4_M4Z4Z_HtoS: |
| 34846 | case AArch64::SUB_VG4_M4Z4Z_D: |
| 34847 | case AArch64::SUB_VG4_M4Z4Z_S: |
| 34848 | case AArch64::UDOT_VG4_M4Z4Z_BtoS: |
| 34849 | case AArch64::UDOT_VG4_M4Z4Z_HtoD: |
| 34850 | case AArch64::UDOT_VG4_M4Z4Z_HtoS: |
| 34851 | case AArch64::USDOT_VG4_M4Z4Z_BToS: { |
| 34852 | switch (OpNum) { |
| 34853 | case 5: |
| 34854 | // op: Zm |
| 34855 | return 18; |
| 34856 | case 4: |
| 34857 | // op: Zn |
| 34858 | return 7; |
| 34859 | case 2: |
| 34860 | // op: Rv |
| 34861 | return 13; |
| 34862 | case 3: |
| 34863 | // op: imm3 |
| 34864 | return 0; |
| 34865 | } |
| 34866 | break; |
| 34867 | } |
| 34868 | default: |
| 34869 | reportUnsupportedInst(MI); |
| 34870 | } |
| 34871 | reportUnsupportedOperand(MI, OpNum); |
| 34872 | } |
| 34873 | |
| 34874 | #endif // GET_OPERAND_BIT_OFFSET |
| 34875 | |
| 34876 |
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