1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11
12namespace llvm::AArch64 {
13
14enum : unsigned {
15 InvalidRegBankID = ~0u,
16 CCRegBankID = 0,
17 FPRRegBankID = 1,
18 GPRRegBankID = 2,
19 NumRegisterBanks,
20};
21
22} // namespace llvm::AArch64
23
24#endif // GET_REGBANK_DECLARATIONS
25
26#ifdef GET_TARGET_REGBANK_CLASS
27#undef GET_TARGET_REGBANK_CLASS
28
29private:
30 static const RegisterBank *RegBanks[];
31 static const unsigned Sizes[];
32
33public:
34 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
35protected:
36 AArch64GenRegisterBankInfo(unsigned HwMode = 0);
37
38
39#endif // GET_TARGET_REGBANK_CLASS
40
41#ifdef GET_TARGET_REGBANK_IMPL
42#undef GET_TARGET_REGBANK_IMPL
43
44namespace llvm {
45
46namespace AArch64 {
47
48const uint32_t CCRegBankCoverageData[] = {
49 // 0-31
50 0,
51 // 32-63
52 (1u << (AArch64::CCRRegClassID - 32)) |
53 0,
54 // 64-95
55 0,
56 // 96-127
57 0,
58 // 128-159
59 0,
60 // 160-191
61 0,
62 // 192-223
63 0,
64 // 224-255
65 0,
66 // 256-287
67 0,
68 // 288-319
69 0,
70 // 320-351
71 0,
72 // 352-383
73 0,
74 // 384-415
75 0,
76 // 416-447
77 0,
78 // 448-479
79 0,
80 // 480-511
81 0,
82 // 512-543
83 0,
84};
85const uint32_t FPRRegBankCoverageData[] = {
86 // 0-31
87 (1u << (AArch64::FPR8RegClassID - 0)) |
88 (1u << (AArch64::FPR16RegClassID - 0)) |
89 (1u << (AArch64::FPR16_loRegClassID - 0)) |
90 0,
91 // 32-63
92 (1u << (AArch64::FPR32RegClassID - 32)) |
93 (1u << (AArch64::FPR64RegClassID - 32)) |
94 (1u << (AArch64::FPR32_with_hsub_in_FPR16_loRegClassID - 32)) |
95 0,
96 // 64-95
97 (1u << (AArch64::DDRegClassID - 64)) |
98 (1u << (AArch64::FPR128RegClassID - 64)) |
99 (1u << (AArch64::FPR64_loRegClassID - 64)) |
100 (1u << (AArch64::DD_with_dsub0_in_FPR64_loRegClassID - 64)) |
101 (1u << (AArch64::DD_with_dsub1_in_FPR64_loRegClassID - 64)) |
102 (1u << (AArch64::FPR128_loRegClassID - 64)) |
103 (1u << (AArch64::DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID - 64)) |
104 (1u << (AArch64::ZPRRegClassID - 64)) |
105 (1u << (AArch64::ZPRMul2RegClassID - 64)) |
106 0,
107 // 96-127
108 (1u << (AArch64::DDDRegClassID - 96)) |
109 (1u << (AArch64::DDDDRegClassID - 96)) |
110 (1u << (AArch64::QQRegClassID - 96)) |
111 (1u << (AArch64::DDD_with_dsub0_in_FPR64_loRegClassID - 96)) |
112 (1u << (AArch64::DDD_with_dsub1_in_FPR64_loRegClassID - 96)) |
113 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_loRegClassID - 96)) |
114 (1u << (AArch64::DDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
115 (1u << (AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID - 96)) |
116 (1u << (AArch64::DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
117 (1u << (AArch64::DDDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
118 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
119 (1u << (AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
120 (1u << (AArch64::DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
121 (1u << (AArch64::DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
122 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
123 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_loRegClassID - 96)) |
124 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID - 96)) |
125 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
126 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
127 (1u << (AArch64::FPR128_0to7RegClassID - 96)) |
128 (1u << (AArch64::ZPRMul2_HiRegClassID - 96)) |
129 (1u << (AArch64::ZPRMul2_Hi_and_ZPRMul4RegClassID - 96)) |
130 (1u << (AArch64::ZPRMul4_and_ZPR_KRegClassID - 96)) |
131 (1u << (AArch64::ZPRMul2_and_ZPR_KRegClassID - 96)) |
132 (1u << (AArch64::ZPRMul2_LoRegClassID - 96)) |
133 (1u << (AArch64::ZPRMul2_Lo_and_ZPRMul4RegClassID - 96)) |
134 (1u << (AArch64::ZPRMul4_and_ZPR_3bRegClassID - 96)) |
135 (1u << (AArch64::ZPRMul2_and_ZPR_3bRegClassID - 96)) |
136 (1u << (AArch64::ZPRMul4RegClassID - 96)) |
137 (1u << (AArch64::ZPR_4bRegClassID - 96)) |
138 (1u << (AArch64::ZPR_3bRegClassID - 96)) |
139 (1u << (AArch64::ZPR_KRegClassID - 96)) |
140 0,
141 // 128-159
142 (1u << (AArch64::QQ_with_dsub1_in_FPR64_loRegClassID - 128)) |
143 (1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 128)) |
144 (1u << (AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_loRegClassID - 128)) |
145 (1u << (AArch64::QQ_with_qsub0_in_FPR128_0to7RegClassID - 128)) |
146 (1u << (AArch64::QQ_with_qsub1_in_FPR128_0to7RegClassID - 128)) |
147 0,
148 // 160-191
149 (1u << (AArch64::QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7RegClassID - 160)) |
150 0,
151 // 192-223
152 (1u << (AArch64::QQQRegClassID - 192)) |
153 (1u << (AArch64::QQQ_with_dsub1_in_FPR64_loRegClassID - 192)) |
154 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 192)) |
155 (1u << (AArch64::QQQ_with_dsub2_in_FPR64_loRegClassID - 192)) |
156 (1u << (AArch64::QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID - 192)) |
157 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_loRegClassID - 192)) |
158 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID - 192)) |
159 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_0to7RegClassID - 192)) |
160 (1u << (AArch64::QQQ_with_qsub1_in_FPR128_0to7RegClassID - 192)) |
161 (1u << (AArch64::QQQ_with_qsub2_in_FPR128_0to7RegClassID - 192)) |
162 0,
163 // 224-255
164 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7RegClassID - 224)) |
165 (1u << (AArch64::QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID - 224)) |
166 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID - 224)) |
167 0,
168 // 256-287
169 0,
170 // 288-319
171 (1u << (AArch64::QQQQRegClassID - 288)) |
172 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_loRegClassID - 288)) |
173 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID - 288)) |
174 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID - 288)) |
175 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID - 288)) |
176 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID - 288)) |
177 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_loRegClassID - 288)) |
178 (1u << (AArch64::QQQQ_with_dsub2_in_FPR64_loRegClassID - 288)) |
179 (1u << (AArch64::QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID - 288)) |
180 (1u << (AArch64::QQQQ_with_dsub3_in_FPR64_loRegClassID - 288)) |
181 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 288)) |
182 0,
183 // 320-351
184 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7RegClassID - 320)) |
185 (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_0to7RegClassID - 320)) |
186 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 320)) |
187 (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 320)) |
188 (1u << (AArch64::QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 320)) |
189 (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 320)) |
190 0,
191 // 352-383
192 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7RegClassID - 352)) |
193 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 352)) |
194 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 352)) |
195 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 352)) |
196 0,
197 // 384-415
198 0,
199 // 416-447
200 0,
201 // 448-479
202 0,
203 // 480-511
204 0,
205 // 512-543
206 0,
207};
208const uint32_t GPRRegBankCoverageData[] = {
209 // 0-31
210 0,
211 // 32-63
212 (1u << (AArch64::GPR32allRegClassID - 32)) |
213 (1u << (AArch64::GPR32RegClassID - 32)) |
214 (1u << (AArch64::GPR32spRegClassID - 32)) |
215 (1u << (AArch64::GPR32commonRegClassID - 32)) |
216 (1u << (AArch64::WSeqPairsClassRegClassID - 32)) |
217 (1u << (AArch64::GPR64allRegClassID - 32)) |
218 (1u << (AArch64::GPR64RegClassID - 32)) |
219 (1u << (AArch64::GPR64spRegClassID - 32)) |
220 (1u << (AArch64::GPR64commonRegClassID - 32)) |
221 (1u << (AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID - 32)) |
222 (1u << (AArch64::GPR64noipRegClassID - 32)) |
223 (1u << (AArch64::GPR64common_and_GPR64noipRegClassID - 32)) |
224 (1u << (AArch64::tcGPR64RegClassID - 32)) |
225 (1u << (AArch64::tcGPRnotx16RegClassID - 32)) |
226 (1u << (AArch64::tcGPRnotx16x17RegClassID - 32)) |
227 (1u << (AArch64::GPR32argRegClassID - 32)) |
228 (1u << (AArch64::WSeqPairsClass_with_sube32_in_GPR32argRegClassID - 32)) |
229 (1u << (AArch64::MatrixIndexGPR32_12_15RegClassID - 32)) |
230 (1u << (AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15RegClassID - 32)) |
231 (1u << (AArch64::MatrixIndexGPR32_8_11RegClassID - 32)) |
232 (1u << (AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11RegClassID - 32)) |
233 0,
234 // 64-95
235 (1u << (AArch64::XSeqPairsClassRegClassID - 64)) |
236 (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID - 64)) |
237 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClassID - 64)) |
238 (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPRnotx16RegClassID - 64)) |
239 (1u << (AArch64::XSeqPairsClass_with_subo64_in_tcGPRnotx16x17RegClassID - 64)) |
240 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64argRegClassID - 64)) |
241 (1u << (AArch64::GPR64argRegClassID - 64)) |
242 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID - 64)) |
243 (1u << (AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID - 64)) |
244 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID - 64)) |
245 (1u << (AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID - 64)) |
246 (1u << (AArch64::XSeqPairsClass_with_subo64_in_FIXED_REGSRegClassID - 64)) |
247 (1u << (AArch64::FIXED_REGSRegClassID - 64)) |
248 (1u << (AArch64::FIXED_REGS_with_sub_32RegClassID - 64)) |
249 (1u << (AArch64::FIXED_REGS_and_GPR64RegClassID - 64)) |
250 (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID - 64)) |
251 (1u << (AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID - 64)) |
252 (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPRx16x17RegClassID - 64)) |
253 (1u << (AArch64::tcGPRx16x17RegClassID - 64)) |
254 (1u << (AArch64::tcGPRx17RegClassID - 64)) |
255 (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClassID - 64)) |
256 0,
257 // 96-127
258 0,
259 // 128-159
260 0,
261 // 160-191
262 0,
263 // 192-223
264 0,
265 // 224-255
266 0,
267 // 256-287
268 0,
269 // 288-319
270 0,
271 // 320-351
272 0,
273 // 352-383
274 0,
275 // 384-415
276 0,
277 // 416-447
278 0,
279 // 448-479
280 0,
281 // 480-511
282 0,
283 // 512-543
284 0,
285};
286
287constexpr RegisterBank CCRegBank(/* ID */ AArch64::CCRegBankID, /* Name */ "CC", /* CoveredRegClasses */ CCRegBankCoverageData, /* NumRegClasses */ 530);
288constexpr RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 530);
289constexpr RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 530);
290
291} // namespace AArch64
292
293const RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
294 &AArch64::CCRegBank,
295 &AArch64::FPRRegBank,
296 &AArch64::GPRRegBank,
297};
298
299const unsigned AArch64GenRegisterBankInfo::Sizes[] = {
300 // Mode = 0 (Default)
301 32,
302 512,
303 128,
304};
305
306AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo(unsigned HwMode)
307 : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks, Sizes, HwMode) {
308 // Assert that RegBank indices match their ID's
309#ifndef NDEBUG
310 for (auto RB : enumerate(RegBanks))
311 assert(RB.index() == RB.value()->getID() && "Index != ID");
312#endif // NDEBUG
313}
314
315const RegisterBank &
316AArch64GenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
317 constexpr uint32_t InvalidRegBankID = uint32_t(AArch64::InvalidRegBankID) & 3;
318 static const uint32_t RegClass2RegBank[24] = {
319 (uint32_t(InvalidRegBankID) << 0) |
320 (uint32_t(InvalidRegBankID) << 2) |
321 (uint32_t(InvalidRegBankID) << 4) |
322 (uint32_t(InvalidRegBankID) << 6) |
323 (uint32_t(InvalidRegBankID) << 8) |
324 (uint32_t(InvalidRegBankID) << 10) |
325 (uint32_t(AArch64::FPRRegBankID) << 12) | // FPR8RegClassID
326 (uint32_t(AArch64::FPRRegBankID) << 14) | // FPR16RegClassID
327 (uint32_t(InvalidRegBankID) << 16) |
328 (uint32_t(AArch64::FPRRegBankID) << 18) | // FPR16_loRegClassID
329 (uint32_t(InvalidRegBankID) << 20) |
330 (uint32_t(InvalidRegBankID) << 22) |
331 (uint32_t(InvalidRegBankID) << 24) |
332 (uint32_t(InvalidRegBankID) << 26) |
333 (uint32_t(InvalidRegBankID) << 28) |
334 (uint32_t(InvalidRegBankID) << 30),
335 (uint32_t(InvalidRegBankID) << 0) |
336 (uint32_t(InvalidRegBankID) << 2) |
337 (uint32_t(InvalidRegBankID) << 4) |
338 (uint32_t(InvalidRegBankID) << 6) |
339 (uint32_t(InvalidRegBankID) << 8) |
340 (uint32_t(InvalidRegBankID) << 10) |
341 (uint32_t(InvalidRegBankID) << 12) |
342 (uint32_t(InvalidRegBankID) << 14) |
343 (uint32_t(InvalidRegBankID) << 16) |
344 (uint32_t(InvalidRegBankID) << 18) |
345 (uint32_t(InvalidRegBankID) << 20) |
346 (uint32_t(InvalidRegBankID) << 22) |
347 (uint32_t(InvalidRegBankID) << 24) |
348 (uint32_t(InvalidRegBankID) << 26) |
349 (uint32_t(InvalidRegBankID) << 28) |
350 (uint32_t(InvalidRegBankID) << 30),
351 (uint32_t(InvalidRegBankID) << 0) |
352 (uint32_t(InvalidRegBankID) << 2) |
353 (uint32_t(InvalidRegBankID) << 4) |
354 (uint32_t(InvalidRegBankID) << 6) |
355 (uint32_t(InvalidRegBankID) << 8) |
356 (uint32_t(InvalidRegBankID) << 10) |
357 (uint32_t(AArch64::GPRRegBankID) << 12) | // GPR32allRegClassID
358 (uint32_t(AArch64::FPRRegBankID) << 14) | // FPR32RegClassID
359 (uint32_t(AArch64::GPRRegBankID) << 16) | // GPR32RegClassID
360 (uint32_t(AArch64::GPRRegBankID) << 18) | // GPR32spRegClassID
361 (uint32_t(AArch64::GPRRegBankID) << 20) | // GPR32commonRegClassID
362 (uint32_t(AArch64::FPRRegBankID) << 22) | // FPR32_with_hsub_in_FPR16_loRegClassID
363 (uint32_t(AArch64::GPRRegBankID) << 24) | // GPR32argRegClassID
364 (uint32_t(AArch64::GPRRegBankID) << 26) | // MatrixIndexGPR32_12_15RegClassID
365 (uint32_t(AArch64::GPRRegBankID) << 28) | // MatrixIndexGPR32_8_11RegClassID
366 (uint32_t(AArch64::CCRegBankID) << 30), // CCRRegClassID
367 (uint32_t(InvalidRegBankID) << 0) |
368 (uint32_t(AArch64::GPRRegBankID) << 2) | // WSeqPairsClassRegClassID
369 (uint32_t(AArch64::GPRRegBankID) << 4) | // WSeqPairsClass_with_subo32_in_GPR32commonRegClassID
370 (uint32_t(AArch64::GPRRegBankID) << 6) | // WSeqPairsClass_with_sube32_in_GPR32argRegClassID
371 (uint32_t(AArch64::GPRRegBankID) << 8) | // WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15RegClassID
372 (uint32_t(AArch64::GPRRegBankID) << 10) | // WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11RegClassID
373 (uint32_t(AArch64::GPRRegBankID) << 12) | // GPR64allRegClassID
374 (uint32_t(AArch64::FPRRegBankID) << 14) | // FPR64RegClassID
375 (uint32_t(AArch64::GPRRegBankID) << 16) | // GPR64RegClassID
376 (uint32_t(AArch64::GPRRegBankID) << 18) | // GPR64spRegClassID
377 (uint32_t(AArch64::GPRRegBankID) << 20) | // GPR64commonRegClassID
378 (uint32_t(AArch64::GPRRegBankID) << 22) | // GPR64noipRegClassID
379 (uint32_t(AArch64::GPRRegBankID) << 24) | // GPR64common_and_GPR64noipRegClassID
380 (uint32_t(AArch64::GPRRegBankID) << 26) | // tcGPR64RegClassID
381 (uint32_t(AArch64::GPRRegBankID) << 28) | // tcGPRnotx16RegClassID
382 (uint32_t(AArch64::GPRRegBankID) << 30), // tcGPRnotx16x17RegClassID
383 (uint32_t(AArch64::FPRRegBankID) << 0) | // FPR64_loRegClassID
384 (uint32_t(AArch64::GPRRegBankID) << 2) | // GPR64argRegClassID
385 (uint32_t(AArch64::GPRRegBankID) << 4) | // FIXED_REGSRegClassID
386 (uint32_t(AArch64::GPRRegBankID) << 6) | // GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID
387 (uint32_t(AArch64::GPRRegBankID) << 8) | // GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID
388 (uint32_t(AArch64::GPRRegBankID) << 10) | // FIXED_REGS_with_sub_32RegClassID
389 (uint32_t(AArch64::GPRRegBankID) << 12) | // tcGPRx16x17RegClassID
390 (uint32_t(AArch64::GPRRegBankID) << 14) | // FIXED_REGS_and_GPR64RegClassID
391 (uint32_t(InvalidRegBankID) << 16) |
392 (uint32_t(AArch64::GPRRegBankID) << 18) | // tcGPRx17RegClassID
393 (uint32_t(AArch64::FPRRegBankID) << 20) | // DDRegClassID
394 (uint32_t(AArch64::FPRRegBankID) << 22) | // DD_with_dsub0_in_FPR64_loRegClassID
395 (uint32_t(AArch64::FPRRegBankID) << 24) | // DD_with_dsub1_in_FPR64_loRegClassID
396 (uint32_t(AArch64::GPRRegBankID) << 26) | // XSeqPairsClassRegClassID
397 (uint32_t(AArch64::FPRRegBankID) << 28) | // DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID
398 (uint32_t(AArch64::GPRRegBankID) << 30), // XSeqPairsClass_with_subo64_in_GPR64commonRegClassID
399 (uint32_t(AArch64::GPRRegBankID) << 0) | // XSeqPairsClass_with_subo64_in_GPR64noipRegClassID
400 (uint32_t(AArch64::GPRRegBankID) << 2) | // XSeqPairsClass_with_sube64_in_GPR64noipRegClassID
401 (uint32_t(AArch64::GPRRegBankID) << 4) | // XSeqPairsClass_with_sube64_in_tcGPR64RegClassID
402 (uint32_t(AArch64::GPRRegBankID) << 6) | // XSeqPairsClass_with_sube64_in_tcGPRnotx16RegClassID
403 (uint32_t(AArch64::GPRRegBankID) << 8) | // XSeqPairsClass_with_subo64_in_tcGPR64RegClassID
404 (uint32_t(AArch64::GPRRegBankID) << 10) | // XSeqPairsClass_with_subo64_in_tcGPRnotx16x17RegClassID
405 (uint32_t(AArch64::GPRRegBankID) << 12) | // XSeqPairsClass_with_sube64_in_GPR64argRegClassID
406 (uint32_t(AArch64::GPRRegBankID) << 14) | // XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID
407 (uint32_t(AArch64::GPRRegBankID) << 16) | // XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID
408 (uint32_t(AArch64::GPRRegBankID) << 18) | // XSeqPairsClass_with_sube64_in_tcGPRx16x17RegClassID
409 (uint32_t(AArch64::GPRRegBankID) << 20) | // XSeqPairsClass_with_subo64_in_FIXED_REGSRegClassID
410 (uint32_t(AArch64::FPRRegBankID) << 22) | // FPR128RegClassID
411 (uint32_t(AArch64::FPRRegBankID) << 24) | // ZPRRegClassID
412 (uint32_t(AArch64::FPRRegBankID) << 26) | // FPR128_loRegClassID
413 (uint32_t(InvalidRegBankID) << 28) |
414 (uint32_t(AArch64::FPRRegBankID) << 30), // ZPRMul2RegClassID
415 (uint32_t(AArch64::FPRRegBankID) << 0) | // ZPR_4bRegClassID
416 (uint32_t(AArch64::FPRRegBankID) << 2) | // FPR128_0to7RegClassID
417 (uint32_t(AArch64::FPRRegBankID) << 4) | // ZPRMul2_HiRegClassID
418 (uint32_t(AArch64::FPRRegBankID) << 6) | // ZPRMul2_LoRegClassID
419 (uint32_t(AArch64::FPRRegBankID) << 8) | // ZPRMul4RegClassID
420 (uint32_t(AArch64::FPRRegBankID) << 10) | // ZPR_3bRegClassID
421 (uint32_t(AArch64::FPRRegBankID) << 12) | // ZPR_KRegClassID
422 (uint32_t(AArch64::FPRRegBankID) << 14) | // ZPRMul2_Hi_and_ZPRMul4RegClassID
423 (uint32_t(AArch64::FPRRegBankID) << 16) | // ZPRMul2_Lo_and_ZPRMul4RegClassID
424 (uint32_t(AArch64::FPRRegBankID) << 18) | // ZPRMul2_and_ZPR_3bRegClassID
425 (uint32_t(AArch64::FPRRegBankID) << 20) | // ZPRMul2_and_ZPR_KRegClassID
426 (uint32_t(AArch64::FPRRegBankID) << 22) | // ZPRMul4_and_ZPR_3bRegClassID
427 (uint32_t(AArch64::FPRRegBankID) << 24) | // ZPRMul4_and_ZPR_KRegClassID
428 (uint32_t(AArch64::FPRRegBankID) << 26) | // DDDRegClassID
429 (uint32_t(AArch64::FPRRegBankID) << 28) | // DDD_with_dsub0_in_FPR64_loRegClassID
430 (uint32_t(AArch64::FPRRegBankID) << 30), // DDD_with_dsub1_in_FPR64_loRegClassID
431 (uint32_t(AArch64::FPRRegBankID) << 0) | // DDD_with_dsub2_in_FPR64_loRegClassID
432 (uint32_t(AArch64::FPRRegBankID) << 2) | // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID
433 (uint32_t(AArch64::FPRRegBankID) << 4) | // DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID
434 (uint32_t(AArch64::FPRRegBankID) << 6) | // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID
435 (uint32_t(AArch64::FPRRegBankID) << 8) | // DDDDRegClassID
436 (uint32_t(AArch64::FPRRegBankID) << 10) | // DDDD_with_dsub0_in_FPR64_loRegClassID
437 (uint32_t(AArch64::FPRRegBankID) << 12) | // DDDD_with_dsub1_in_FPR64_loRegClassID
438 (uint32_t(AArch64::FPRRegBankID) << 14) | // DDDD_with_dsub2_in_FPR64_loRegClassID
439 (uint32_t(AArch64::FPRRegBankID) << 16) | // DDDD_with_dsub3_in_FPR64_loRegClassID
440 (uint32_t(AArch64::FPRRegBankID) << 18) | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID
441 (uint32_t(AArch64::FPRRegBankID) << 20) | // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID
442 (uint32_t(AArch64::FPRRegBankID) << 22) | // DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID
443 (uint32_t(AArch64::FPRRegBankID) << 24) | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID
444 (uint32_t(AArch64::FPRRegBankID) << 26) | // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID
445 (uint32_t(AArch64::FPRRegBankID) << 28) | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID
446 (uint32_t(AArch64::FPRRegBankID) << 30), // QQRegClassID
447 (uint32_t(InvalidRegBankID) << 0) |
448 (uint32_t(InvalidRegBankID) << 2) |
449 (uint32_t(InvalidRegBankID) << 4) |
450 (uint32_t(AArch64::FPRRegBankID) << 6) | // QQ_with_dsub1_in_FPR64_loRegClassID
451 (uint32_t(AArch64::FPRRegBankID) << 8) | // QQ_with_qsub0_in_FPR128_loRegClassID
452 (uint32_t(InvalidRegBankID) << 10) |
453 (uint32_t(InvalidRegBankID) << 12) |
454 (uint32_t(InvalidRegBankID) << 14) |
455 (uint32_t(InvalidRegBankID) << 16) |
456 (uint32_t(InvalidRegBankID) << 18) |
457 (uint32_t(InvalidRegBankID) << 20) |
458 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_loRegClassID
459 (uint32_t(InvalidRegBankID) << 24) |
460 (uint32_t(InvalidRegBankID) << 26) |
461 (uint32_t(InvalidRegBankID) << 28) |
462 (uint32_t(InvalidRegBankID) << 30),
463 (uint32_t(InvalidRegBankID) << 0) |
464 (uint32_t(AArch64::FPRRegBankID) << 2) | // QQ_with_qsub0_in_FPR128_0to7RegClassID
465 (uint32_t(AArch64::FPRRegBankID) << 4) | // QQ_with_qsub1_in_FPR128_0to7RegClassID
466 (uint32_t(InvalidRegBankID) << 6) |
467 (uint32_t(InvalidRegBankID) << 8) |
468 (uint32_t(InvalidRegBankID) << 10) |
469 (uint32_t(InvalidRegBankID) << 12) |
470 (uint32_t(InvalidRegBankID) << 14) |
471 (uint32_t(InvalidRegBankID) << 16) |
472 (uint32_t(InvalidRegBankID) << 18) |
473 (uint32_t(InvalidRegBankID) << 20) |
474 (uint32_t(InvalidRegBankID) << 22) |
475 (uint32_t(InvalidRegBankID) << 24) |
476 (uint32_t(InvalidRegBankID) << 26) |
477 (uint32_t(InvalidRegBankID) << 28) |
478 (uint32_t(InvalidRegBankID) << 30),
479 (uint32_t(InvalidRegBankID) << 0) |
480 (uint32_t(InvalidRegBankID) << 2) |
481 (uint32_t(AArch64::FPRRegBankID) << 4) | // QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7RegClassID
482 (uint32_t(InvalidRegBankID) << 6) |
483 (uint32_t(InvalidRegBankID) << 8) |
484 (uint32_t(InvalidRegBankID) << 10) |
485 (uint32_t(InvalidRegBankID) << 12) |
486 (uint32_t(InvalidRegBankID) << 14) |
487 (uint32_t(InvalidRegBankID) << 16) |
488 (uint32_t(InvalidRegBankID) << 18) |
489 (uint32_t(InvalidRegBankID) << 20) |
490 (uint32_t(InvalidRegBankID) << 22) |
491 (uint32_t(InvalidRegBankID) << 24) |
492 (uint32_t(InvalidRegBankID) << 26) |
493 (uint32_t(InvalidRegBankID) << 28) |
494 (uint32_t(InvalidRegBankID) << 30),
495 (uint32_t(InvalidRegBankID) << 0) |
496 (uint32_t(InvalidRegBankID) << 2) |
497 (uint32_t(InvalidRegBankID) << 4) |
498 (uint32_t(InvalidRegBankID) << 6) |
499 (uint32_t(InvalidRegBankID) << 8) |
500 (uint32_t(InvalidRegBankID) << 10) |
501 (uint32_t(InvalidRegBankID) << 12) |
502 (uint32_t(InvalidRegBankID) << 14) |
503 (uint32_t(InvalidRegBankID) << 16) |
504 (uint32_t(InvalidRegBankID) << 18) |
505 (uint32_t(InvalidRegBankID) << 20) |
506 (uint32_t(InvalidRegBankID) << 22) |
507 (uint32_t(InvalidRegBankID) << 24) |
508 (uint32_t(InvalidRegBankID) << 26) |
509 (uint32_t(InvalidRegBankID) << 28) |
510 (uint32_t(InvalidRegBankID) << 30),
511 (uint32_t(InvalidRegBankID) << 0) |
512 (uint32_t(InvalidRegBankID) << 2) |
513 (uint32_t(InvalidRegBankID) << 4) |
514 (uint32_t(InvalidRegBankID) << 6) |
515 (uint32_t(InvalidRegBankID) << 8) |
516 (uint32_t(InvalidRegBankID) << 10) |
517 (uint32_t(InvalidRegBankID) << 12) |
518 (uint32_t(InvalidRegBankID) << 14) |
519 (uint32_t(InvalidRegBankID) << 16) |
520 (uint32_t(InvalidRegBankID) << 18) |
521 (uint32_t(InvalidRegBankID) << 20) |
522 (uint32_t(InvalidRegBankID) << 22) |
523 (uint32_t(InvalidRegBankID) << 24) |
524 (uint32_t(AArch64::FPRRegBankID) << 26) | // QQQRegClassID
525 (uint32_t(InvalidRegBankID) << 28) |
526 (uint32_t(AArch64::FPRRegBankID) << 30), // QQQ_with_dsub1_in_FPR64_loRegClassID
527 (uint32_t(AArch64::FPRRegBankID) << 0) | // QQQ_with_dsub2_in_FPR64_loRegClassID
528 (uint32_t(AArch64::FPRRegBankID) << 2) | // QQQ_with_qsub0_in_FPR128_loRegClassID
529 (uint32_t(InvalidRegBankID) << 4) |
530 (uint32_t(InvalidRegBankID) << 6) |
531 (uint32_t(InvalidRegBankID) << 8) |
532 (uint32_t(InvalidRegBankID) << 10) |
533 (uint32_t(InvalidRegBankID) << 12) |
534 (uint32_t(AArch64::FPRRegBankID) << 14) | // QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID
535 (uint32_t(AArch64::FPRRegBankID) << 16) | // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_loRegClassID
536 (uint32_t(InvalidRegBankID) << 18) |
537 (uint32_t(InvalidRegBankID) << 20) |
538 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID
539 (uint32_t(InvalidRegBankID) << 24) |
540 (uint32_t(AArch64::FPRRegBankID) << 26) | // QQQ_with_qsub0_in_FPR128_0to7RegClassID
541 (uint32_t(AArch64::FPRRegBankID) << 28) | // QQQ_with_qsub1_in_FPR128_0to7RegClassID
542 (uint32_t(AArch64::FPRRegBankID) << 30), // QQQ_with_qsub2_in_FPR128_0to7RegClassID
543 (uint32_t(InvalidRegBankID) << 0) |
544 (uint32_t(InvalidRegBankID) << 2) |
545 (uint32_t(InvalidRegBankID) << 4) |
546 (uint32_t(InvalidRegBankID) << 6) |
547 (uint32_t(InvalidRegBankID) << 8) |
548 (uint32_t(InvalidRegBankID) << 10) |
549 (uint32_t(InvalidRegBankID) << 12) |
550 (uint32_t(InvalidRegBankID) << 14) |
551 (uint32_t(InvalidRegBankID) << 16) |
552 (uint32_t(InvalidRegBankID) << 18) |
553 (uint32_t(InvalidRegBankID) << 20) |
554 (uint32_t(InvalidRegBankID) << 22) |
555 (uint32_t(InvalidRegBankID) << 24) |
556 (uint32_t(InvalidRegBankID) << 26) |
557 (uint32_t(InvalidRegBankID) << 28) |
558 (uint32_t(InvalidRegBankID) << 30),
559 (uint32_t(AArch64::FPRRegBankID) << 0) | // QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID
560 (uint32_t(AArch64::FPRRegBankID) << 2) | // QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7RegClassID
561 (uint32_t(InvalidRegBankID) << 4) |
562 (uint32_t(InvalidRegBankID) << 6) |
563 (uint32_t(InvalidRegBankID) << 8) |
564 (uint32_t(InvalidRegBankID) << 10) |
565 (uint32_t(InvalidRegBankID) << 12) |
566 (uint32_t(AArch64::FPRRegBankID) << 14) | // QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID
567 (uint32_t(InvalidRegBankID) << 16) |
568 (uint32_t(InvalidRegBankID) << 18) |
569 (uint32_t(InvalidRegBankID) << 20) |
570 (uint32_t(InvalidRegBankID) << 22) |
571 (uint32_t(InvalidRegBankID) << 24) |
572 (uint32_t(InvalidRegBankID) << 26) |
573 (uint32_t(InvalidRegBankID) << 28) |
574 (uint32_t(InvalidRegBankID) << 30),
575 (uint32_t(InvalidRegBankID) << 0) |
576 (uint32_t(InvalidRegBankID) << 2) |
577 (uint32_t(InvalidRegBankID) << 4) |
578 (uint32_t(InvalidRegBankID) << 6) |
579 (uint32_t(InvalidRegBankID) << 8) |
580 (uint32_t(InvalidRegBankID) << 10) |
581 (uint32_t(InvalidRegBankID) << 12) |
582 (uint32_t(InvalidRegBankID) << 14) |
583 (uint32_t(InvalidRegBankID) << 16) |
584 (uint32_t(InvalidRegBankID) << 18) |
585 (uint32_t(InvalidRegBankID) << 20) |
586 (uint32_t(InvalidRegBankID) << 22) |
587 (uint32_t(InvalidRegBankID) << 24) |
588 (uint32_t(InvalidRegBankID) << 26) |
589 (uint32_t(InvalidRegBankID) << 28) |
590 (uint32_t(InvalidRegBankID) << 30),
591 (uint32_t(InvalidRegBankID) << 0) |
592 (uint32_t(InvalidRegBankID) << 2) |
593 (uint32_t(InvalidRegBankID) << 4) |
594 (uint32_t(InvalidRegBankID) << 6) |
595 (uint32_t(InvalidRegBankID) << 8) |
596 (uint32_t(InvalidRegBankID) << 10) |
597 (uint32_t(InvalidRegBankID) << 12) |
598 (uint32_t(InvalidRegBankID) << 14) |
599 (uint32_t(InvalidRegBankID) << 16) |
600 (uint32_t(InvalidRegBankID) << 18) |
601 (uint32_t(InvalidRegBankID) << 20) |
602 (uint32_t(InvalidRegBankID) << 22) |
603 (uint32_t(InvalidRegBankID) << 24) |
604 (uint32_t(InvalidRegBankID) << 26) |
605 (uint32_t(InvalidRegBankID) << 28) |
606 (uint32_t(InvalidRegBankID) << 30),
607 (uint32_t(InvalidRegBankID) << 0) |
608 (uint32_t(InvalidRegBankID) << 2) |
609 (uint32_t(InvalidRegBankID) << 4) |
610 (uint32_t(InvalidRegBankID) << 6) |
611 (uint32_t(InvalidRegBankID) << 8) |
612 (uint32_t(InvalidRegBankID) << 10) |
613 (uint32_t(InvalidRegBankID) << 12) |
614 (uint32_t(InvalidRegBankID) << 14) |
615 (uint32_t(AArch64::FPRRegBankID) << 16) | // QQQQRegClassID
616 (uint32_t(InvalidRegBankID) << 18) |
617 (uint32_t(AArch64::FPRRegBankID) << 20) | // QQQQ_with_dsub1_in_FPR64_loRegClassID
618 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQQQ_with_dsub2_in_FPR64_loRegClassID
619 (uint32_t(AArch64::FPRRegBankID) << 24) | // QQQQ_with_dsub3_in_FPR64_loRegClassID
620 (uint32_t(AArch64::FPRRegBankID) << 26) | // QQQQ_with_qsub0_in_FPR128_loRegClassID
621 (uint32_t(InvalidRegBankID) << 28) |
622 (uint32_t(InvalidRegBankID) << 30),
623 (uint32_t(InvalidRegBankID) << 0) |
624 (uint32_t(InvalidRegBankID) << 2) |
625 (uint32_t(InvalidRegBankID) << 4) |
626 (uint32_t(InvalidRegBankID) << 6) |
627 (uint32_t(InvalidRegBankID) << 8) |
628 (uint32_t(AArch64::FPRRegBankID) << 10) | // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID
629 (uint32_t(AArch64::FPRRegBankID) << 12) | // QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID
630 (uint32_t(AArch64::FPRRegBankID) << 14) | // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_loRegClassID
631 (uint32_t(InvalidRegBankID) << 16) |
632 (uint32_t(InvalidRegBankID) << 18) |
633 (uint32_t(InvalidRegBankID) << 20) |
634 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID
635 (uint32_t(AArch64::FPRRegBankID) << 24) | // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID
636 (uint32_t(InvalidRegBankID) << 26) |
637 (uint32_t(InvalidRegBankID) << 28) |
638 (uint32_t(AArch64::FPRRegBankID) << 30), // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID
639 (uint32_t(InvalidRegBankID) << 0) |
640 (uint32_t(InvalidRegBankID) << 2) |
641 (uint32_t(InvalidRegBankID) << 4) |
642 (uint32_t(AArch64::FPRRegBankID) << 6) | // QQQQ_with_qsub0_in_FPR128_0to7RegClassID
643 (uint32_t(AArch64::FPRRegBankID) << 8) | // QQQQ_with_qsub1_in_FPR128_0to7RegClassID
644 (uint32_t(AArch64::FPRRegBankID) << 10) | // QQQQ_with_qsub2_in_FPR128_0to7RegClassID
645 (uint32_t(AArch64::FPRRegBankID) << 12) | // QQQQ_with_qsub3_in_FPR128_0to7RegClassID
646 (uint32_t(InvalidRegBankID) << 14) |
647 (uint32_t(InvalidRegBankID) << 16) |
648 (uint32_t(InvalidRegBankID) << 18) |
649 (uint32_t(InvalidRegBankID) << 20) |
650 (uint32_t(InvalidRegBankID) << 22) |
651 (uint32_t(InvalidRegBankID) << 24) |
652 (uint32_t(InvalidRegBankID) << 26) |
653 (uint32_t(InvalidRegBankID) << 28) |
654 (uint32_t(InvalidRegBankID) << 30),
655 (uint32_t(InvalidRegBankID) << 0) |
656 (uint32_t(InvalidRegBankID) << 2) |
657 (uint32_t(InvalidRegBankID) << 4) |
658 (uint32_t(InvalidRegBankID) << 6) |
659 (uint32_t(InvalidRegBankID) << 8) |
660 (uint32_t(InvalidRegBankID) << 10) |
661 (uint32_t(InvalidRegBankID) << 12) |
662 (uint32_t(InvalidRegBankID) << 14) |
663 (uint32_t(InvalidRegBankID) << 16) |
664 (uint32_t(InvalidRegBankID) << 18) |
665 (uint32_t(InvalidRegBankID) << 20) |
666 (uint32_t(InvalidRegBankID) << 22) |
667 (uint32_t(InvalidRegBankID) << 24) |
668 (uint32_t(InvalidRegBankID) << 26) |
669 (uint32_t(AArch64::FPRRegBankID) << 28) | // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID
670 (uint32_t(AArch64::FPRRegBankID) << 30), // QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID
671 (uint32_t(AArch64::FPRRegBankID) << 0) | // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7RegClassID
672 (uint32_t(InvalidRegBankID) << 2) |
673 (uint32_t(InvalidRegBankID) << 4) |
674 (uint32_t(InvalidRegBankID) << 6) |
675 (uint32_t(InvalidRegBankID) << 8) |
676 (uint32_t(InvalidRegBankID) << 10) |
677 (uint32_t(InvalidRegBankID) << 12) |
678 (uint32_t(InvalidRegBankID) << 14) |
679 (uint32_t(InvalidRegBankID) << 16) |
680 (uint32_t(AArch64::FPRRegBankID) << 18) | // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID
681 (uint32_t(AArch64::FPRRegBankID) << 20) | // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID
682 (uint32_t(InvalidRegBankID) << 22) |
683 (uint32_t(InvalidRegBankID) << 24) |
684 (uint32_t(InvalidRegBankID) << 26) |
685 (uint32_t(InvalidRegBankID) << 28) |
686 (uint32_t(InvalidRegBankID) << 30),
687 (uint32_t(InvalidRegBankID) << 0) |
688 (uint32_t(InvalidRegBankID) << 2) |
689 (uint32_t(InvalidRegBankID) << 4) |
690 (uint32_t(InvalidRegBankID) << 6) |
691 (uint32_t(InvalidRegBankID) << 8) |
692 (uint32_t(AArch64::FPRRegBankID) << 10) // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID
693 };
694 const unsigned RegClassID = RC.getID();
695 if (LLVM_LIKELY(RegClassID < 374)) {
696 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
697 if (RegBankID != InvalidRegBankID)
698 return getRegBank(RegBankID);
699 }
700 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
701}
702
703} // namespace llvm
704
705#endif // GET_TARGET_REGBANK_IMPL
706
707