1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11
12namespace llvm::AArch64 {
13
14enum : unsigned {
15 InvalidRegBankID = ~0u,
16 CCRegBankID = 0,
17 FPRRegBankID = 1,
18 GPRRegBankID = 2,
19 NumRegisterBanks,
20};
21
22} // namespace llvm::AArch64
23
24#endif // GET_REGBANK_DECLARATIONS
25
26#ifdef GET_TARGET_REGBANK_CLASS
27#undef GET_TARGET_REGBANK_CLASS
28
29private:
30 static const RegisterBank *RegBanks[];
31 static const unsigned Sizes[];
32
33public:
34 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
35protected:
36 AArch64GenRegisterBankInfo(unsigned HwMode = 0);
37
38
39#endif // GET_TARGET_REGBANK_CLASS
40
41#ifdef GET_TARGET_REGBANK_IMPL
42#undef GET_TARGET_REGBANK_IMPL
43
44namespace llvm {
45
46namespace AArch64 {
47
48const uint32_t CCRegBankCoverageData[] = {
49 // 0-31
50 0,
51 // 32-63
52 (1u << (AArch64::CCRRegClassID - 32)) |
53 0,
54 // 64-95
55 0,
56 // 96-127
57 0,
58 // 128-159
59 0,
60 // 160-191
61 0,
62 // 192-223
63 0,
64 // 224-255
65 0,
66 // 256-287
67 0,
68 // 288-319
69 0,
70 // 320-351
71 0,
72 // 352-383
73 0,
74 // 384-415
75 0,
76};
77const uint32_t FPRRegBankCoverageData[] = {
78 // 0-31
79 (1u << (AArch64::FPR8RegClassID - 0)) |
80 (1u << (AArch64::FPR16RegClassID - 0)) |
81 (1u << (AArch64::FPR32RegClassID - 0)) |
82 (1u << (AArch64::FPR16_loRegClassID - 0)) |
83 0,
84 // 32-63
85 (1u << (AArch64::FPR64RegClassID - 32)) |
86 (1u << (AArch64::DDRegClassID - 32)) |
87 (1u << (AArch64::FPR32_with_hsub_in_FPR16_loRegClassID - 32)) |
88 (1u << (AArch64::FPR64_loRegClassID - 32)) |
89 (1u << (AArch64::DD_with_dsub0_in_FPR64_loRegClassID - 32)) |
90 (1u << (AArch64::DD_with_dsub1_in_FPR64_loRegClassID - 32)) |
91 0,
92 // 64-95
93 (1u << (AArch64::FPR128RegClassID - 64)) |
94 (1u << (AArch64::DDDRegClassID - 64)) |
95 (1u << (AArch64::FPR128_loRegClassID - 64)) |
96 (1u << (AArch64::DDD_with_dsub0_in_FPR64_loRegClassID - 64)) |
97 (1u << (AArch64::DDD_with_dsub1_in_FPR64_loRegClassID - 64)) |
98 (1u << (AArch64::DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID - 64)) |
99 (1u << (AArch64::DDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
100 (1u << (AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID - 64)) |
101 (1u << (AArch64::DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
102 (1u << (AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID - 64)) |
103 (1u << (AArch64::FPR128_0to7RegClassID - 64)) |
104 (1u << (AArch64::ZPRRegClassID - 64)) |
105 (1u << (AArch64::ZPR_4bRegClassID - 64)) |
106 (1u << (AArch64::ZPRMul2_LoRegClassID - 64)) |
107 (1u << (AArch64::ZPRMul2_Lo_and_ZPR_3bRegClassID - 64)) |
108 (1u << (AArch64::ZPR_3bRegClassID - 64)) |
109 (1u << (AArch64::ZPRMul2_HiRegClassID - 64)) |
110 (1u << (AArch64::ZPRMul2_Hi_and_ZPR_KRegClassID - 64)) |
111 (1u << (AArch64::ZPR_KRegClassID - 64)) |
112 0,
113 // 96-127
114 (1u << (AArch64::DDDDRegClassID - 96)) |
115 (1u << (AArch64::QQRegClassID - 96)) |
116 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_loRegClassID - 96)) |
117 (1u << (AArch64::QQ_with_dsub1_in_FPR64_loRegClassID - 96)) |
118 (1u << (AArch64::QQ_with_qsub0_in_FPR128_loRegClassID - 96)) |
119 (1u << (AArch64::DDDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
120 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
121 (1u << (AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_loRegClassID - 96)) |
122 (1u << (AArch64::DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
123 (1u << (AArch64::DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
124 (1u << (AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
125 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_loRegClassID - 96)) |
126 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID - 96)) |
127 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID - 96)) |
128 (1u << (AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID - 96)) |
129 (1u << (AArch64::QQ_with_qsub0_in_FPR128_0to7RegClassID - 96)) |
130 (1u << (AArch64::QQ_with_qsub1_in_FPR128_0to7RegClassID - 96)) |
131 0,
132 // 128-159
133 (1u << (AArch64::QQQRegClassID - 128)) |
134 (1u << (AArch64::QQQ_with_dsub1_in_FPR64_loRegClassID - 128)) |
135 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID - 128)) |
136 (1u << (AArch64::QQQ_with_dsub2_in_FPR64_loRegClassID - 128)) |
137 (1u << (AArch64::QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7RegClassID - 128)) |
138 0,
139 // 160-191
140 (1u << (AArch64::QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID - 160)) |
141 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_loRegClassID - 160)) |
142 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID - 160)) |
143 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_0to7RegClassID - 160)) |
144 (1u << (AArch64::QQQ_with_qsub1_in_FPR128_0to7RegClassID - 160)) |
145 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7RegClassID - 160)) |
146 (1u << (AArch64::QQQ_with_qsub2_in_FPR128_0to7RegClassID - 160)) |
147 (1u << (AArch64::QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID - 160)) |
148 0,
149 // 192-223
150 (1u << (AArch64::QQQQRegClassID - 192)) |
151 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_loRegClassID - 192)) |
152 (1u << (AArch64::QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID - 192)) |
153 (1u << (AArch64::QQQQ_with_dsub2_in_FPR64_loRegClassID - 192)) |
154 (1u << (AArch64::QQQQ_with_dsub3_in_FPR64_loRegClassID - 192)) |
155 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID - 192)) |
156 0,
157 // 224-255
158 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID - 224)) |
159 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID - 224)) |
160 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID - 224)) |
161 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7RegClassID - 224)) |
162 (1u << (AArch64::QQQQ_with_qsub1_in_FPR128_0to7RegClassID - 224)) |
163 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID - 224)) |
164 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_loRegClassID - 224)) |
165 (1u << (AArch64::QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID - 224)) |
166 (1u << (AArch64::QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 224)) |
167 (1u << (AArch64::QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 224)) |
168 0,
169 // 256-287
170 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7RegClassID - 256)) |
171 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 256)) |
172 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID - 256)) |
173 (1u << (AArch64::QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 256)) |
174 (1u << (AArch64::QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 256)) |
175 0,
176 // 288-319
177 (1u << (AArch64::QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID - 288)) |
178 0,
179 // 320-351
180 0,
181 // 352-383
182 0,
183 // 384-415
184 0,
185};
186const uint32_t GPRRegBankCoverageData[] = {
187 // 0-31
188 (1u << (AArch64::GPR32allRegClassID - 0)) |
189 (1u << (AArch64::GPR32RegClassID - 0)) |
190 (1u << (AArch64::GPR32spRegClassID - 0)) |
191 0,
192 // 32-63
193 (1u << (AArch64::GPR32commonRegClassID - 32)) |
194 (1u << (AArch64::WSeqPairsClassRegClassID - 32)) |
195 (1u << (AArch64::GPR64allRegClassID - 32)) |
196 (1u << (AArch64::GPR64RegClassID - 32)) |
197 (1u << (AArch64::GPR64spRegClassID - 32)) |
198 (1u << (AArch64::GPR64commonRegClassID - 32)) |
199 (1u << (AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID - 32)) |
200 (1u << (AArch64::GPR64noipRegClassID - 32)) |
201 (1u << (AArch64::GPR64common_and_GPR64noipRegClassID - 32)) |
202 (1u << (AArch64::tcGPR64RegClassID - 32)) |
203 (1u << (AArch64::tcGPRnotx16RegClassID - 32)) |
204 (1u << (AArch64::tcGPRnotx16x17RegClassID - 32)) |
205 (1u << (AArch64::MatrixIndexGPR32_12_15RegClassID - 32)) |
206 (1u << (AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15RegClassID - 32)) |
207 (1u << (AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID - 32)) |
208 (1u << (AArch64::MatrixIndexGPR32_8_11RegClassID - 32)) |
209 (1u << (AArch64::WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11RegClassID - 32)) |
210 (1u << (AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID - 32)) |
211 (1u << (AArch64::FIXED_REGSRegClassID - 32)) |
212 (1u << (AArch64::FIXED_REGS_with_sub_32RegClassID - 32)) |
213 (1u << (AArch64::FIXED_REGS_and_GPR64RegClassID - 32)) |
214 (1u << (AArch64::tcGPRx16x17RegClassID - 32)) |
215 (1u << (AArch64::tcGPRx17RegClassID - 32)) |
216 0,
217 // 64-95
218 (1u << (AArch64::XSeqPairsClassRegClassID - 64)) |
219 (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID - 64)) |
220 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClassID - 64)) |
221 (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPRnotx16RegClassID - 64)) |
222 (1u << (AArch64::XSeqPairsClass_with_subo64_in_tcGPRnotx16x17RegClassID - 64)) |
223 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID - 64)) |
224 (1u << (AArch64::XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID - 64)) |
225 (1u << (AArch64::XSeqPairsClass_with_subo64_in_FIXED_REGSRegClassID - 64)) |
226 (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID - 64)) |
227 (1u << (AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID - 64)) |
228 (1u << (AArch64::XSeqPairsClass_with_sube64_in_tcGPRx16x17RegClassID - 64)) |
229 (1u << (AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClassID - 64)) |
230 0,
231 // 96-127
232 0,
233 // 128-159
234 0,
235 // 160-191
236 0,
237 // 192-223
238 0,
239 // 224-255
240 0,
241 // 256-287
242 0,
243 // 288-319
244 0,
245 // 320-351
246 0,
247 // 352-383
248 0,
249 // 384-415
250 0,
251};
252
253constexpr RegisterBank CCRegBank(/* ID */ AArch64::CCRegBankID, /* Name */ "CC", /* CoveredRegClasses */ CCRegBankCoverageData, /* NumRegClasses */ 403);
254constexpr RegisterBank FPRRegBank(/* ID */ AArch64::FPRRegBankID, /* Name */ "FPR", /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 403);
255constexpr RegisterBank GPRRegBank(/* ID */ AArch64::GPRRegBankID, /* Name */ "GPR", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 403);
256
257} // namespace AArch64
258
259const RegisterBank *AArch64GenRegisterBankInfo::RegBanks[] = {
260 &AArch64::CCRegBank,
261 &AArch64::FPRRegBank,
262 &AArch64::GPRRegBank,
263};
264
265const unsigned AArch64GenRegisterBankInfo::Sizes[] = {
266 // Mode = 0 (DefaultMode)
267 32,
268 512,
269 128,
270};
271
272AArch64GenRegisterBankInfo::AArch64GenRegisterBankInfo(unsigned HwMode)
273 : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks, Sizes, HwMode) {
274 // Assert that RegBank indices match their ID's
275#ifndef NDEBUG
276 for (auto RB : enumerate(RegBanks))
277 assert(RB.index() == RB.value()->getID() && "Index != ID");
278#endif // NDEBUG
279}
280
281const RegisterBank &
282AArch64GenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
283 constexpr uint32_t InvalidRegBankID = uint32_t(AArch64::InvalidRegBankID) & 3;
284 static const uint32_t RegClass2RegBank[19] = {
285 (uint32_t(InvalidRegBankID) << 0) |
286 (uint32_t(InvalidRegBankID) << 2) |
287 (uint32_t(InvalidRegBankID) << 4) |
288 (uint32_t(InvalidRegBankID) << 6) |
289 (uint32_t(InvalidRegBankID) << 8) |
290 (uint32_t(InvalidRegBankID) << 10) |
291 (uint32_t(AArch64::FPRRegBankID) << 12) | // FPR8RegClassID
292 (uint32_t(AArch64::FPRRegBankID) << 14) | // FPR16RegClassID
293 (uint32_t(InvalidRegBankID) << 16) |
294 (uint32_t(AArch64::FPRRegBankID) << 18) | // FPR16_loRegClassID
295 (uint32_t(InvalidRegBankID) << 20) |
296 (uint32_t(InvalidRegBankID) << 22) |
297 (uint32_t(InvalidRegBankID) << 24) |
298 (uint32_t(InvalidRegBankID) << 26) |
299 (uint32_t(InvalidRegBankID) << 28) |
300 (uint32_t(InvalidRegBankID) << 30),
301 (uint32_t(InvalidRegBankID) << 0) |
302 (uint32_t(InvalidRegBankID) << 2) |
303 (uint32_t(InvalidRegBankID) << 4) |
304 (uint32_t(InvalidRegBankID) << 6) |
305 (uint32_t(InvalidRegBankID) << 8) |
306 (uint32_t(InvalidRegBankID) << 10) |
307 (uint32_t(InvalidRegBankID) << 12) |
308 (uint32_t(InvalidRegBankID) << 14) |
309 (uint32_t(InvalidRegBankID) << 16) |
310 (uint32_t(InvalidRegBankID) << 18) |
311 (uint32_t(InvalidRegBankID) << 20) |
312 (uint32_t(InvalidRegBankID) << 22) |
313 (uint32_t(AArch64::GPRRegBankID) << 24) | // GPR32allRegClassID
314 (uint32_t(AArch64::FPRRegBankID) << 26) | // FPR32RegClassID
315 (uint32_t(AArch64::GPRRegBankID) << 28) | // GPR32RegClassID
316 (uint32_t(AArch64::GPRRegBankID) << 30), // GPR32spRegClassID
317 (uint32_t(AArch64::GPRRegBankID) << 0) | // GPR32commonRegClassID
318 (uint32_t(AArch64::FPRRegBankID) << 2) | // FPR32_with_hsub_in_FPR16_loRegClassID
319 (uint32_t(AArch64::GPRRegBankID) << 4) | // MatrixIndexGPR32_12_15RegClassID
320 (uint32_t(AArch64::GPRRegBankID) << 6) | // MatrixIndexGPR32_8_11RegClassID
321 (uint32_t(AArch64::CCRegBankID) << 8) | // CCRRegClassID
322 (uint32_t(InvalidRegBankID) << 10) |
323 (uint32_t(AArch64::GPRRegBankID) << 12) | // WSeqPairsClassRegClassID
324 (uint32_t(AArch64::GPRRegBankID) << 14) | // WSeqPairsClass_with_subo32_in_GPR32commonRegClassID
325 (uint32_t(AArch64::GPRRegBankID) << 16) | // WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15RegClassID
326 (uint32_t(AArch64::GPRRegBankID) << 18) | // WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_8_11RegClassID
327 (uint32_t(AArch64::GPRRegBankID) << 20) | // GPR64allRegClassID
328 (uint32_t(AArch64::FPRRegBankID) << 22) | // FPR64RegClassID
329 (uint32_t(AArch64::GPRRegBankID) << 24) | // GPR64RegClassID
330 (uint32_t(AArch64::GPRRegBankID) << 26) | // GPR64spRegClassID
331 (uint32_t(AArch64::GPRRegBankID) << 28) | // GPR64commonRegClassID
332 (uint32_t(AArch64::GPRRegBankID) << 30), // GPR64noipRegClassID
333 (uint32_t(AArch64::GPRRegBankID) << 0) | // GPR64common_and_GPR64noipRegClassID
334 (uint32_t(AArch64::GPRRegBankID) << 2) | // tcGPR64RegClassID
335 (uint32_t(AArch64::GPRRegBankID) << 4) | // tcGPRnotx16RegClassID
336 (uint32_t(AArch64::GPRRegBankID) << 6) | // tcGPRnotx16x17RegClassID
337 (uint32_t(AArch64::FPRRegBankID) << 8) | // FPR64_loRegClassID
338 (uint32_t(AArch64::GPRRegBankID) << 10) | // FIXED_REGSRegClassID
339 (uint32_t(AArch64::GPRRegBankID) << 12) | // GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID
340 (uint32_t(AArch64::GPRRegBankID) << 14) | // GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID
341 (uint32_t(AArch64::GPRRegBankID) << 16) | // FIXED_REGS_with_sub_32RegClassID
342 (uint32_t(AArch64::GPRRegBankID) << 18) | // tcGPRx16x17RegClassID
343 (uint32_t(AArch64::GPRRegBankID) << 20) | // FIXED_REGS_and_GPR64RegClassID
344 (uint32_t(InvalidRegBankID) << 22) |
345 (uint32_t(AArch64::GPRRegBankID) << 24) | // tcGPRx17RegClassID
346 (uint32_t(AArch64::FPRRegBankID) << 26) | // DDRegClassID
347 (uint32_t(AArch64::FPRRegBankID) << 28) | // DD_with_dsub0_in_FPR64_loRegClassID
348 (uint32_t(AArch64::FPRRegBankID) << 30), // DD_with_dsub1_in_FPR64_loRegClassID
349 (uint32_t(AArch64::GPRRegBankID) << 0) | // XSeqPairsClassRegClassID
350 (uint32_t(AArch64::FPRRegBankID) << 2) | // DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID
351 (uint32_t(AArch64::GPRRegBankID) << 4) | // XSeqPairsClass_with_subo64_in_GPR64commonRegClassID
352 (uint32_t(AArch64::GPRRegBankID) << 6) | // XSeqPairsClass_with_subo64_in_GPR64noipRegClassID
353 (uint32_t(AArch64::GPRRegBankID) << 8) | // XSeqPairsClass_with_sube64_in_GPR64noipRegClassID
354 (uint32_t(AArch64::GPRRegBankID) << 10) | // XSeqPairsClass_with_sube64_in_tcGPR64RegClassID
355 (uint32_t(AArch64::GPRRegBankID) << 12) | // XSeqPairsClass_with_sube64_in_tcGPRnotx16RegClassID
356 (uint32_t(AArch64::GPRRegBankID) << 14) | // XSeqPairsClass_with_subo64_in_tcGPR64RegClassID
357 (uint32_t(AArch64::GPRRegBankID) << 16) | // XSeqPairsClass_with_subo64_in_tcGPRnotx16x17RegClassID
358 (uint32_t(AArch64::GPRRegBankID) << 18) | // XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_12_15RegClassID
359 (uint32_t(AArch64::GPRRegBankID) << 20) | // XSeqPairsClass_with_sube64_in_GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID
360 (uint32_t(AArch64::GPRRegBankID) << 22) | // XSeqPairsClass_with_sube64_in_tcGPRx16x17RegClassID
361 (uint32_t(AArch64::GPRRegBankID) << 24) | // XSeqPairsClass_with_subo64_in_FIXED_REGSRegClassID
362 (uint32_t(AArch64::FPRRegBankID) << 26) | // FPR128RegClassID
363 (uint32_t(AArch64::FPRRegBankID) << 28) | // ZPRRegClassID
364 (uint32_t(AArch64::FPRRegBankID) << 30), // FPR128_loRegClassID
365 (uint32_t(InvalidRegBankID) << 0) |
366 (uint32_t(AArch64::FPRRegBankID) << 2) | // ZPR_4bRegClassID
367 (uint32_t(AArch64::FPRRegBankID) << 4) | // FPR128_0to7RegClassID
368 (uint32_t(AArch64::FPRRegBankID) << 6) | // ZPRMul2_HiRegClassID
369 (uint32_t(AArch64::FPRRegBankID) << 8) | // ZPRMul2_LoRegClassID
370 (uint32_t(AArch64::FPRRegBankID) << 10) | // ZPR_3bRegClassID
371 (uint32_t(AArch64::FPRRegBankID) << 12) | // ZPR_KRegClassID
372 (uint32_t(AArch64::FPRRegBankID) << 14) | // ZPRMul2_Hi_and_ZPR_KRegClassID
373 (uint32_t(AArch64::FPRRegBankID) << 16) | // ZPRMul2_Lo_and_ZPR_3bRegClassID
374 (uint32_t(AArch64::FPRRegBankID) << 18) | // DDDRegClassID
375 (uint32_t(AArch64::FPRRegBankID) << 20) | // DDD_with_dsub0_in_FPR64_loRegClassID
376 (uint32_t(AArch64::FPRRegBankID) << 22) | // DDD_with_dsub1_in_FPR64_loRegClassID
377 (uint32_t(AArch64::FPRRegBankID) << 24) | // DDD_with_dsub2_in_FPR64_loRegClassID
378 (uint32_t(AArch64::FPRRegBankID) << 26) | // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID
379 (uint32_t(AArch64::FPRRegBankID) << 28) | // DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID
380 (uint32_t(AArch64::FPRRegBankID) << 30), // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID
381 (uint32_t(AArch64::FPRRegBankID) << 0) | // DDDDRegClassID
382 (uint32_t(AArch64::FPRRegBankID) << 2) | // DDDD_with_dsub0_in_FPR64_loRegClassID
383 (uint32_t(AArch64::FPRRegBankID) << 4) | // DDDD_with_dsub1_in_FPR64_loRegClassID
384 (uint32_t(AArch64::FPRRegBankID) << 6) | // DDDD_with_dsub2_in_FPR64_loRegClassID
385 (uint32_t(AArch64::FPRRegBankID) << 8) | // DDDD_with_dsub3_in_FPR64_loRegClassID
386 (uint32_t(AArch64::FPRRegBankID) << 10) | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID
387 (uint32_t(AArch64::FPRRegBankID) << 12) | // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID
388 (uint32_t(AArch64::FPRRegBankID) << 14) | // DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID
389 (uint32_t(AArch64::FPRRegBankID) << 16) | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID
390 (uint32_t(AArch64::FPRRegBankID) << 18) | // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID
391 (uint32_t(AArch64::FPRRegBankID) << 20) | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID
392 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQRegClassID
393 (uint32_t(InvalidRegBankID) << 24) |
394 (uint32_t(InvalidRegBankID) << 26) |
395 (uint32_t(AArch64::FPRRegBankID) << 28) | // QQ_with_dsub1_in_FPR64_loRegClassID
396 (uint32_t(AArch64::FPRRegBankID) << 30), // QQ_with_qsub0_in_FPR128_loRegClassID
397 (uint32_t(InvalidRegBankID) << 0) |
398 (uint32_t(InvalidRegBankID) << 2) |
399 (uint32_t(InvalidRegBankID) << 4) |
400 (uint32_t(InvalidRegBankID) << 6) |
401 (uint32_t(InvalidRegBankID) << 8) |
402 (uint32_t(AArch64::FPRRegBankID) << 10) | // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_dsub1_in_FPR64_loRegClassID
403 (uint32_t(InvalidRegBankID) << 12) |
404 (uint32_t(InvalidRegBankID) << 14) |
405 (uint32_t(InvalidRegBankID) << 16) |
406 (uint32_t(InvalidRegBankID) << 18) |
407 (uint32_t(AArch64::FPRRegBankID) << 20) | // QQ_with_qsub0_in_FPR128_0to7RegClassID
408 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQ_with_qsub1_in_FPR128_0to7RegClassID
409 (uint32_t(InvalidRegBankID) << 24) |
410 (uint32_t(InvalidRegBankID) << 26) |
411 (uint32_t(InvalidRegBankID) << 28) |
412 (uint32_t(InvalidRegBankID) << 30),
413 (uint32_t(InvalidRegBankID) << 0) |
414 (uint32_t(InvalidRegBankID) << 2) |
415 (uint32_t(InvalidRegBankID) << 4) |
416 (uint32_t(InvalidRegBankID) << 6) |
417 (uint32_t(InvalidRegBankID) << 8) |
418 (uint32_t(InvalidRegBankID) << 10) |
419 (uint32_t(InvalidRegBankID) << 12) |
420 (uint32_t(AArch64::FPRRegBankID) << 14) | // QQ_with_qsub0_in_FPR128_0to7_and_QQ_with_qsub1_in_FPR128_0to7RegClassID
421 (uint32_t(InvalidRegBankID) << 16) |
422 (uint32_t(InvalidRegBankID) << 18) |
423 (uint32_t(InvalidRegBankID) << 20) |
424 (uint32_t(InvalidRegBankID) << 22) |
425 (uint32_t(InvalidRegBankID) << 24) |
426 (uint32_t(InvalidRegBankID) << 26) |
427 (uint32_t(InvalidRegBankID) << 28) |
428 (uint32_t(InvalidRegBankID) << 30),
429 (uint32_t(InvalidRegBankID) << 0) |
430 (uint32_t(InvalidRegBankID) << 2) |
431 (uint32_t(InvalidRegBankID) << 4) |
432 (uint32_t(InvalidRegBankID) << 6) |
433 (uint32_t(InvalidRegBankID) << 8) |
434 (uint32_t(InvalidRegBankID) << 10) |
435 (uint32_t(InvalidRegBankID) << 12) |
436 (uint32_t(InvalidRegBankID) << 14) |
437 (uint32_t(InvalidRegBankID) << 16) |
438 (uint32_t(InvalidRegBankID) << 18) |
439 (uint32_t(InvalidRegBankID) << 20) |
440 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQQRegClassID
441 (uint32_t(InvalidRegBankID) << 24) |
442 (uint32_t(AArch64::FPRRegBankID) << 26) | // QQQ_with_dsub1_in_FPR64_loRegClassID
443 (uint32_t(AArch64::FPRRegBankID) << 28) | // QQQ_with_dsub2_in_FPR64_loRegClassID
444 (uint32_t(AArch64::FPRRegBankID) << 30), // QQQ_with_qsub0_in_FPR128_loRegClassID
445 (uint32_t(InvalidRegBankID) << 0) |
446 (uint32_t(InvalidRegBankID) << 2) |
447 (uint32_t(InvalidRegBankID) << 4) |
448 (uint32_t(InvalidRegBankID) << 6) |
449 (uint32_t(InvalidRegBankID) << 8) |
450 (uint32_t(AArch64::FPRRegBankID) << 10) | // QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID
451 (uint32_t(AArch64::FPRRegBankID) << 12) | // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub1_in_FPR64_loRegClassID
452 (uint32_t(InvalidRegBankID) << 14) |
453 (uint32_t(InvalidRegBankID) << 16) |
454 (uint32_t(AArch64::FPRRegBankID) << 18) | // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_dsub2_in_FPR64_loRegClassID
455 (uint32_t(InvalidRegBankID) << 20) |
456 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQQ_with_qsub0_in_FPR128_0to7RegClassID
457 (uint32_t(AArch64::FPRRegBankID) << 24) | // QQQ_with_qsub1_in_FPR128_0to7RegClassID
458 (uint32_t(AArch64::FPRRegBankID) << 26) | // QQQ_with_qsub2_in_FPR128_0to7RegClassID
459 (uint32_t(InvalidRegBankID) << 28) |
460 (uint32_t(InvalidRegBankID) << 30),
461 (uint32_t(InvalidRegBankID) << 0) |
462 (uint32_t(InvalidRegBankID) << 2) |
463 (uint32_t(InvalidRegBankID) << 4) |
464 (uint32_t(InvalidRegBankID) << 6) |
465 (uint32_t(InvalidRegBankID) << 8) |
466 (uint32_t(InvalidRegBankID) << 10) |
467 (uint32_t(InvalidRegBankID) << 12) |
468 (uint32_t(InvalidRegBankID) << 14) |
469 (uint32_t(InvalidRegBankID) << 16) |
470 (uint32_t(InvalidRegBankID) << 18) |
471 (uint32_t(InvalidRegBankID) << 20) |
472 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQQ_with_dsub1_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID
473 (uint32_t(AArch64::FPRRegBankID) << 24) | // QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub1_in_FPR128_0to7RegClassID
474 (uint32_t(InvalidRegBankID) << 26) |
475 (uint32_t(InvalidRegBankID) << 28) |
476 (uint32_t(InvalidRegBankID) << 30),
477 (uint32_t(InvalidRegBankID) << 0) |
478 (uint32_t(InvalidRegBankID) << 2) |
479 (uint32_t(AArch64::FPRRegBankID) << 4) | // QQQ_with_qsub0_in_FPR128_0to7_and_QQQ_with_qsub2_in_FPR128_0to7RegClassID
480 (uint32_t(InvalidRegBankID) << 6) |
481 (uint32_t(InvalidRegBankID) << 8) |
482 (uint32_t(InvalidRegBankID) << 10) |
483 (uint32_t(InvalidRegBankID) << 12) |
484 (uint32_t(InvalidRegBankID) << 14) |
485 (uint32_t(InvalidRegBankID) << 16) |
486 (uint32_t(InvalidRegBankID) << 18) |
487 (uint32_t(InvalidRegBankID) << 20) |
488 (uint32_t(InvalidRegBankID) << 22) |
489 (uint32_t(InvalidRegBankID) << 24) |
490 (uint32_t(InvalidRegBankID) << 26) |
491 (uint32_t(InvalidRegBankID) << 28) |
492 (uint32_t(InvalidRegBankID) << 30),
493 (uint32_t(InvalidRegBankID) << 0) |
494 (uint32_t(InvalidRegBankID) << 2) |
495 (uint32_t(InvalidRegBankID) << 4) |
496 (uint32_t(InvalidRegBankID) << 6) |
497 (uint32_t(InvalidRegBankID) << 8) |
498 (uint32_t(InvalidRegBankID) << 10) |
499 (uint32_t(InvalidRegBankID) << 12) |
500 (uint32_t(InvalidRegBankID) << 14) |
501 (uint32_t(InvalidRegBankID) << 16) |
502 (uint32_t(InvalidRegBankID) << 18) |
503 (uint32_t(AArch64::FPRRegBankID) << 20) | // QQQQRegClassID
504 (uint32_t(InvalidRegBankID) << 22) |
505 (uint32_t(AArch64::FPRRegBankID) << 24) | // QQQQ_with_dsub1_in_FPR64_loRegClassID
506 (uint32_t(AArch64::FPRRegBankID) << 26) | // QQQQ_with_dsub2_in_FPR64_loRegClassID
507 (uint32_t(AArch64::FPRRegBankID) << 28) | // QQQQ_with_dsub3_in_FPR64_loRegClassID
508 (uint32_t(AArch64::FPRRegBankID) << 30), // QQQQ_with_qsub0_in_FPR128_loRegClassID
509 (uint32_t(InvalidRegBankID) << 0) |
510 (uint32_t(InvalidRegBankID) << 2) |
511 (uint32_t(InvalidRegBankID) << 4) |
512 (uint32_t(InvalidRegBankID) << 6) |
513 (uint32_t(InvalidRegBankID) << 8) |
514 (uint32_t(InvalidRegBankID) << 10) |
515 (uint32_t(InvalidRegBankID) << 12) |
516 (uint32_t(AArch64::FPRRegBankID) << 14) | // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID
517 (uint32_t(AArch64::FPRRegBankID) << 16) | // QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID
518 (uint32_t(AArch64::FPRRegBankID) << 18) | // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub1_in_FPR64_loRegClassID
519 (uint32_t(InvalidRegBankID) << 20) |
520 (uint32_t(InvalidRegBankID) << 22) |
521 (uint32_t(InvalidRegBankID) << 24) |
522 (uint32_t(AArch64::FPRRegBankID) << 26) | // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID
523 (uint32_t(AArch64::FPRRegBankID) << 28) | // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub2_in_FPR64_loRegClassID
524 (uint32_t(InvalidRegBankID) << 30),
525 (uint32_t(InvalidRegBankID) << 0) |
526 (uint32_t(AArch64::FPRRegBankID) << 2) | // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_dsub3_in_FPR64_loRegClassID
527 (uint32_t(InvalidRegBankID) << 4) |
528 (uint32_t(AArch64::FPRRegBankID) << 6) | // QQQQ_with_qsub0_in_FPR128_0to7RegClassID
529 (uint32_t(AArch64::FPRRegBankID) << 8) | // QQQQ_with_qsub1_in_FPR128_0to7RegClassID
530 (uint32_t(AArch64::FPRRegBankID) << 10) | // QQQQ_with_qsub2_in_FPR128_0to7RegClassID
531 (uint32_t(AArch64::FPRRegBankID) << 12) | // QQQQ_with_qsub3_in_FPR128_0to7RegClassID
532 (uint32_t(InvalidRegBankID) << 14) |
533 (uint32_t(InvalidRegBankID) << 16) |
534 (uint32_t(InvalidRegBankID) << 18) |
535 (uint32_t(InvalidRegBankID) << 20) |
536 (uint32_t(InvalidRegBankID) << 22) |
537 (uint32_t(InvalidRegBankID) << 24) |
538 (uint32_t(InvalidRegBankID) << 26) |
539 (uint32_t(InvalidRegBankID) << 28) |
540 (uint32_t(InvalidRegBankID) << 30),
541 (uint32_t(InvalidRegBankID) << 0) |
542 (uint32_t(InvalidRegBankID) << 2) |
543 (uint32_t(InvalidRegBankID) << 4) |
544 (uint32_t(InvalidRegBankID) << 6) |
545 (uint32_t(InvalidRegBankID) << 8) |
546 (uint32_t(InvalidRegBankID) << 10) |
547 (uint32_t(InvalidRegBankID) << 12) |
548 (uint32_t(InvalidRegBankID) << 14) |
549 (uint32_t(InvalidRegBankID) << 16) |
550 (uint32_t(InvalidRegBankID) << 18) |
551 (uint32_t(InvalidRegBankID) << 20) |
552 (uint32_t(AArch64::FPRRegBankID) << 22) | // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID
553 (uint32_t(AArch64::FPRRegBankID) << 24) | // QQQQ_with_dsub2_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID
554 (uint32_t(AArch64::FPRRegBankID) << 26) | // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub1_in_FPR128_0to7RegClassID
555 (uint32_t(InvalidRegBankID) << 28) |
556 (uint32_t(InvalidRegBankID) << 30),
557 (uint32_t(InvalidRegBankID) << 0) |
558 (uint32_t(InvalidRegBankID) << 2) |
559 (uint32_t(InvalidRegBankID) << 4) |
560 (uint32_t(InvalidRegBankID) << 6) |
561 (uint32_t(InvalidRegBankID) << 8) |
562 (uint32_t(InvalidRegBankID) << 10) |
563 (uint32_t(AArch64::FPRRegBankID) << 12) | // QQQQ_with_dsub1_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID
564 (uint32_t(AArch64::FPRRegBankID) << 14) | // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub2_in_FPR128_0to7RegClassID
565 (uint32_t(InvalidRegBankID) << 16) |
566 (uint32_t(InvalidRegBankID) << 18) |
567 (uint32_t(InvalidRegBankID) << 20) |
568 (uint32_t(InvalidRegBankID) << 22) |
569 (uint32_t(InvalidRegBankID) << 24) |
570 (uint32_t(InvalidRegBankID) << 26) |
571 (uint32_t(InvalidRegBankID) << 28) |
572 (uint32_t(InvalidRegBankID) << 30),
573 (uint32_t(InvalidRegBankID) << 0) |
574 (uint32_t(InvalidRegBankID) << 2) |
575 (uint32_t(AArch64::FPRRegBankID) << 4) // QQQQ_with_qsub0_in_FPR128_0to7_and_QQQQ_with_qsub3_in_FPR128_0to7RegClassID
576 };
577 const unsigned RegClassID = RC.getID();
578 if (LLVM_LIKELY(RegClassID < 291)) {
579 unsigned RegBankID = (RegClass2RegBank[RegClassID / 16] >> ((RegClassID % 16) * 2)) & 3;
580 if (RegBankID != InvalidRegBankID)
581 return getRegBank(RegBankID);
582 }
583 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
584}
585
586} // namespace llvm
587
588#endif // GET_TARGET_REGBANK_IMPL
589
590