1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: AArch64.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::AArch64ISD {
14
15enum GenNodeType : unsigned {
16 ABDS_PRED = ISD::BUILTIN_OP_END,
17 ABDU_PRED,
18 ABS_MERGE_PASSTHRU,
19 ADC,
20 ADCS,
21 ADDHN,
22 ADDP,
23 ADDS,
24 ADDlow,
25 ADR,
26 ADRP,
27 ANDS,
28 ANDV_PRED,
29 ASRD_MERGE_OP1,
30 ASSERT_ZEXT_BOOL,
31 AUTH_CALL,
32 AUTH_CALL_RVMARKER,
33 AUTH_TC_RETURN,
34 BIC,
35 BICi,
36 BITREVERSE_MERGE_PASSTHRU,
37 BRCOND,
38 BSP,
39 BSWAP_MERGE_PASSTHRU,
40 CALL,
41 CALL_ARM64EC_TO_X64,
42 CALL_BTI,
43 CALL_RVMARKER,
44 CB,
45 CBNZ,
46 CBZ,
47 CCMN,
48 CCMP,
49 CHECK_MATCHING_VL,
50 CLASTA_N,
51 CLASTB_N,
52 CMTST,
53 COALESCER_BARRIER,
54 COND_SMSTART,
55 COND_SMSTOP,
56 CSEL,
57 CSINC,
58 CSINV,
59 CSNEG,
60 CTLZ_MERGE_PASSTHRU,
61 CTPOP_MERGE_PASSTHRU,
62 CTTZ_ELTS,
63 CTTZ_ELTS_ZERO_POISON,
64 DUP,
65 DUPLANE128,
66 DUPLANE16,
67 DUPLANE32,
68 DUPLANE64,
69 DUPLANE8,
70 DUP_MERGE_PASSTHRU,
71 ENTRY_PSTATE_SM,
72 EORV_PRED,
73 EXT,
74 EXTR,
75 FABS_MERGE_PASSTHRU,
76 FADDA_PRED,
77 FADDV_PRED,
78 FADD_PRED,
79 FCCMP,
80 FCEIL_MERGE_PASSTHRU,
81 FCMEQ,
82 FCMGE,
83 FCMGT,
84 FCMP,
85 FCVTAS_HALF,
86 FCVTAU_HALF,
87 FCVTMS_HALF,
88 FCVTMU_HALF,
89 FCVTNS_HALF,
90 FCVTNU_HALF,
91 FCVTPS_HALF,
92 FCVTPU_HALF,
93 FCVTXN,
94 FCVTX_MERGE_PASSTHRU,
95 FCVTZS_HALF,
96 FCVTZS_MERGE_PASSTHRU,
97 FCVTZU_HALF,
98 FCVTZU_MERGE_PASSTHRU,
99 FDIV_PRED,
100 FFLOOR_MERGE_PASSTHRU,
101 FMAXNMV_PRED,
102 FMAXNM_PRED,
103 FMAXV_PRED,
104 FMAX_PRED,
105 FMA_PRED,
106 FMINNMV_PRED,
107 FMINNM_PRED,
108 FMINV_PRED,
109 FMIN_PRED,
110 FMOV,
111 FMUL_PRED,
112 FNEARBYINT_MERGE_PASSTHRU,
113 FNEG_MERGE_PASSTHRU,
114 FP_EXTEND_MERGE_PASSTHRU,
115 FP_ROUND_MERGE_PASSTHRU,
116 FRECPE,
117 FRECPS,
118 FRECPX_MERGE_PASSTHRU,
119 FRINT32_MERGE_PASSTHRU,
120 FRINT64_MERGE_PASSTHRU,
121 FRINT_MERGE_PASSTHRU,
122 FROUNDEVEN_MERGE_PASSTHRU,
123 FROUND_MERGE_PASSTHRU,
124 FRSQRTE,
125 FRSQRTS,
126 FSQRT_MERGE_PASSTHRU,
127 FSUB_PRED,
128 FTRUNC32_MERGE_PASSTHRU,
129 FTRUNC64_MERGE_PASSTHRU,
130 FTRUNC_MERGE_PASSTHRU,
131 GLD1Q_INDEX_MERGE_ZERO,
132 GLD1Q_MERGE_ZERO,
133 GLD1S_IMM_MERGE_ZERO,
134 GLD1S_MERGE_ZERO,
135 GLD1S_SCALED_MERGE_ZERO,
136 GLD1S_SXTW_MERGE_ZERO,
137 GLD1S_SXTW_SCALED_MERGE_ZERO,
138 GLD1S_UXTW_MERGE_ZERO,
139 GLD1S_UXTW_SCALED_MERGE_ZERO,
140 GLD1_IMM_MERGE_ZERO,
141 GLD1_MERGE_ZERO,
142 GLD1_SCALED_MERGE_ZERO,
143 GLD1_SXTW_MERGE_ZERO,
144 GLD1_SXTW_SCALED_MERGE_ZERO,
145 GLD1_UXTW_MERGE_ZERO,
146 GLD1_UXTW_SCALED_MERGE_ZERO,
147 GLDFF1S_IMM_MERGE_ZERO,
148 GLDFF1S_MERGE_ZERO,
149 GLDFF1S_SCALED_MERGE_ZERO,
150 GLDFF1S_SXTW_MERGE_ZERO,
151 GLDFF1S_SXTW_SCALED_MERGE_ZERO,
152 GLDFF1S_UXTW_MERGE_ZERO,
153 GLDFF1S_UXTW_SCALED_MERGE_ZERO,
154 GLDFF1_IMM_MERGE_ZERO,
155 GLDFF1_MERGE_ZERO,
156 GLDFF1_SCALED_MERGE_ZERO,
157 GLDFF1_SXTW_MERGE_ZERO,
158 GLDFF1_SXTW_SCALED_MERGE_ZERO,
159 GLDFF1_UXTW_MERGE_ZERO,
160 GLDFF1_UXTW_SCALED_MERGE_ZERO,
161 GLDNT1S_MERGE_ZERO,
162 GLDNT1_INDEX_MERGE_ZERO,
163 GLDNT1_MERGE_ZERO,
164 HADDS_PRED,
165 HADDU_PRED,
166 HVC,
167 INOUT_ZA_USE,
168 INSR,
169 LASTA,
170 LASTB,
171 LD1DUPpost,
172 LD1LANEpost,
173 LD1RO_MERGE_ZERO,
174 LD1RQ_MERGE_ZERO,
175 LD1S_MERGE_ZERO,
176 LD1_MERGE_ZERO,
177 LD1x2post,
178 LD1x3post,
179 LD1x4post,
180 LD2DUPpost,
181 LD2LANEpost,
182 LD2post,
183 LD3DUPpost,
184 LD3LANEpost,
185 LD3post,
186 LD4DUPpost,
187 LD4LANEpost,
188 LD4post,
189 LDFF1S_MERGE_ZERO,
190 LDFF1_MERGE_ZERO,
191 LDIAPP,
192 LDNF1S_MERGE_ZERO,
193 LDNF1_MERGE_ZERO,
194 LDNP,
195 LDP,
196 LOADgot,
197 LS64_BUILD,
198 LS64_EXTRACT,
199 MOVI,
200 MOVIedit,
201 MOVImsl,
202 MOVIshift,
203 MRRS,
204 MRS,
205 MSRR,
206 MULHS_PRED,
207 MULHU_PRED,
208 MUL_PRED,
209 MVNImsl,
210 MVNIshift,
211 NEG_MERGE_PASSTHRU,
212 NVCAST,
213 ORRi,
214 ORV_PRED,
215 PMULL,
216 PREFETCH,
217 PROBED_ALLOCA,
218 PTEST,
219 PTEST_ANY,
220 PTEST_FIRST,
221 PTRUE,
222 RANGE_PREFETCH,
223 RDSVL,
224 REINTERPRET_CAST,
225 REQUIRES_ZA_SAVE,
226 REQUIRES_ZT0_SAVE,
227 RESTORE_ZT,
228 RET_GLUE,
229 REV16,
230 REV32,
231 REV64,
232 REVD_MERGE_PASSTHRU,
233 REVH_MERGE_PASSTHRU,
234 REVW_MERGE_PASSTHRU,
235 RHADDS_PRED,
236 RHADDU_PRED,
237 RSHRNB_I,
238 SADDLP,
239 SADDLV,
240 SADDV,
241 SADDV_PRED,
242 SAVE_ZT,
243 SBC,
244 SBCS,
245 SDOT,
246 SETCC_MERGE_ZERO,
247 SHL_PRED,
248 SIGN_EXTEND_INREG_MERGE_PASSTHRU,
249 SINT_TO_FP_MERGE_PASSTHRU,
250 SITOF,
251 SMAXV,
252 SMAXV_PRED,
253 SMAX_PRED,
254 SME_STATE_ALLOC,
255 SME_ZA_LDR,
256 SME_ZA_STR,
257 SMINV,
258 SMINV_PRED,
259 SMIN_PRED,
260 SMSTART,
261 SMSTOP,
262 SMULL,
263 SPLICE,
264 SQABS,
265 SQADD,
266 SQDMULH,
267 SQDMULL,
268 SQNEG,
269 SQRDMLAH,
270 SQRDMLSH,
271 SQRDMULH,
272 SQRSHL,
273 SQRSHRN,
274 SQRSHRUN,
275 SQSHL,
276 SQSHLU_I,
277 SQSHL_I,
278 SQSHRN,
279 SQSHRUN,
280 SQSUB,
281 SRA_PRED,
282 SRL_PRED,
283 SRSHR_I,
284 SST1Q_INDEX_PRED,
285 SST1Q_PRED,
286 SST1_IMM_PRED,
287 SST1_PRED,
288 SST1_SCALED_PRED,
289 SST1_SXTW_PRED,
290 SST1_SXTW_SCALED_PRED,
291 SST1_UXTW_PRED,
292 SST1_UXTW_SCALED_PRED,
293 SSTNT1_INDEX_PRED,
294 SSTNT1_PRED,
295 ST1_PRED,
296 ST1x2post,
297 ST1x3post,
298 ST1x4post,
299 ST2G,
300 ST2LANEpost,
301 ST2post,
302 ST3LANEpost,
303 ST3post,
304 ST4LANEpost,
305 ST4post,
306 STG,
307 STILP,
308 STNP,
309 STP,
310 STRICT_FADD_PRED,
311 STRICT_FCEIL_MERGE_PASSTHRU,
312 STRICT_FCMP,
313 STRICT_FCMPE,
314 STRICT_FCVTX_MERGE_PASSTHRU,
315 STRICT_FCVTZS_MERGE_PASSTHRU,
316 STRICT_FCVTZU_MERGE_PASSTHRU,
317 STRICT_FDIV_PRED,
318 STRICT_FFLOOR_MERGE_PASSTHRU,
319 STRICT_FMAXNM_PRED,
320 STRICT_FMAX_PRED,
321 STRICT_FMA_PRED,
322 STRICT_FMINNM_PRED,
323 STRICT_FMIN_PRED,
324 STRICT_FMUL_PRED,
325 STRICT_FNEARBYINT_MERGE_PASSTHRU,
326 STRICT_FP_EXTEND_MERGE_PASSTHRU,
327 STRICT_FP_ROUND_MERGE_PASSTHRU,
328 STRICT_FRINT_MERGE_PASSTHRU,
329 STRICT_FROUNDEVEN_MERGE_PASSTHRU,
330 STRICT_FROUND_MERGE_PASSTHRU,
331 STRICT_FSQRT_MERGE_PASSTHRU,
332 STRICT_FSUB_PRED,
333 STRICT_FTRUNC_MERGE_PASSTHRU,
334 STRICT_SINT_TO_FP_MERGE_PASSTHRU,
335 STRICT_UINT_TO_FP_MERGE_PASSTHRU,
336 STZ2G,
337 STZG,
338 SUBS,
339 SUNPKHI,
340 SUNPKLO,
341 SUQADD,
342 SVC,
343 TBL,
344 TBNZ,
345 TBZ,
346 TC_RETURN,
347 THREAD_POINTER,
348 TLSDESC_AUTH_CALLSEQ,
349 TLSDESC_CALLSEQ,
350 TRN1,
351 TRN2,
352 UADDLP,
353 UADDLV,
354 UADDV,
355 UADDV_PRED,
356 UDOT,
357 UINT_TO_FP_MERGE_PASSTHRU,
358 UITOF,
359 UMAXV,
360 UMAXV_PRED,
361 UMAX_PRED,
362 UMINV,
363 UMINV_PRED,
364 UMIN_PRED,
365 UMULL,
366 UQADD,
367 UQRSHL,
368 UQRSHRN,
369 UQSHL,
370 UQSHL_I,
371 UQSHRN,
372 UQSUB,
373 URSHR_I,
374 URSHR_I_PRED,
375 USDOT,
376 USQADD,
377 UUNPKHI,
378 UUNPKLO,
379 UZP1,
380 UZP2,
381 VASHR,
382 VLSHR,
383 VSHL,
384 VSLI,
385 VSRI,
386 WHILEGE_PRED_COUNTER,
387 WHILEGT_PRED_COUNTER,
388 WHILEHI_PRED_COUNTER,
389 WHILEHS_PRED_COUNTER,
390 WHILELE_PRED_COUNTER,
391 WHILELO_PRED_COUNTER,
392 WHILELS_PRED_COUNTER,
393 WHILELT_PRED_COUNTER,
394 WrapperLarge,
395 ZERO_EXTEND_INREG_MERGE_PASSTHRU,
396 ZIP1,
397 ZIP2,
398};
399
400static constexpr unsigned GENERATED_OPCODE_END = ZIP2 + 1;
401
402} // namespace llvm::AArch64ISD
403
404#endif // GET_SDNODE_ENUM
405
406#ifdef GET_SDNODE_DESC
407#undef GET_SDNODE_DESC
408
409namespace llvm {
410
411
412#ifdef __GNUC__
413#pragma GCC diagnostic push
414#pragma GCC diagnostic ignored "-Woverlength-strings"
415#endif
416static constexpr char AArch64SDNodeNamesStorage[] =
417 "\0"
418 "AArch64ISD::ABDS_PRED\0"
419 "AArch64ISD::ABDU_PRED\0"
420 "AArch64ISD::ABS_MERGE_PASSTHRU\0"
421 "AArch64ISD::ADC\0"
422 "AArch64ISD::ADCS\0"
423 "AArch64ISD::ADDHN\0"
424 "AArch64ISD::ADDP\0"
425 "AArch64ISD::ADDS\0"
426 "AArch64ISD::ADDlow\0"
427 "AArch64ISD::ADR\0"
428 "AArch64ISD::ADRP\0"
429 "AArch64ISD::ANDS\0"
430 "AArch64ISD::ANDV_PRED\0"
431 "AArch64ISD::ASRD_MERGE_OP1\0"
432 "AArch64ISD::ASSERT_ZEXT_BOOL\0"
433 "AArch64ISD::AUTH_CALL\0"
434 "AArch64ISD::AUTH_CALL_RVMARKER\0"
435 "AArch64ISD::AUTH_TC_RETURN\0"
436 "AArch64ISD::BIC\0"
437 "AArch64ISD::BICi\0"
438 "AArch64ISD::BITREVERSE_MERGE_PASSTHRU\0"
439 "AArch64ISD::BRCOND\0"
440 "AArch64ISD::BSP\0"
441 "AArch64ISD::BSWAP_MERGE_PASSTHRU\0"
442 "AArch64ISD::CALL\0"
443 "AArch64ISD::CALL_ARM64EC_TO_X64\0"
444 "AArch64ISD::CALL_BTI\0"
445 "AArch64ISD::CALL_RVMARKER\0"
446 "AArch64ISD::CB\0"
447 "AArch64ISD::CBNZ\0"
448 "AArch64ISD::CBZ\0"
449 "AArch64ISD::CCMN\0"
450 "AArch64ISD::CCMP\0"
451 "AArch64ISD::CHECK_MATCHING_VL\0"
452 "AArch64ISD::CLASTA_N\0"
453 "AArch64ISD::CLASTB_N\0"
454 "AArch64ISD::CMTST\0"
455 "AArch64ISD::COALESCER_BARRIER\0"
456 "AArch64ISD::COND_SMSTART\0"
457 "AArch64ISD::COND_SMSTOP\0"
458 "AArch64ISD::CSEL\0"
459 "AArch64ISD::CSINC\0"
460 "AArch64ISD::CSINV\0"
461 "AArch64ISD::CSNEG\0"
462 "AArch64ISD::CTLZ_MERGE_PASSTHRU\0"
463 "AArch64ISD::CTPOP_MERGE_PASSTHRU\0"
464 "AArch64ISD::CTTZ_ELTS\0"
465 "AArch64ISD::CTTZ_ELTS_ZERO_POISON\0"
466 "AArch64ISD::DUP\0"
467 "AArch64ISD::DUPLANE128\0"
468 "AArch64ISD::DUPLANE16\0"
469 "AArch64ISD::DUPLANE32\0"
470 "AArch64ISD::DUPLANE64\0"
471 "AArch64ISD::DUPLANE8\0"
472 "AArch64ISD::DUP_MERGE_PASSTHRU\0"
473 "AArch64ISD::ENTRY_PSTATE_SM\0"
474 "AArch64ISD::EORV_PRED\0"
475 "AArch64ISD::EXT\0"
476 "AArch64ISD::EXTR\0"
477 "AArch64ISD::FABS_MERGE_PASSTHRU\0"
478 "AArch64ISD::FADDA_PRED\0"
479 "AArch64ISD::FADDV_PRED\0"
480 "AArch64ISD::FADD_PRED\0"
481 "AArch64ISD::FCCMP\0"
482 "AArch64ISD::FCEIL_MERGE_PASSTHRU\0"
483 "AArch64ISD::FCMEQ\0"
484 "AArch64ISD::FCMGE\0"
485 "AArch64ISD::FCMGT\0"
486 "AArch64ISD::FCMP\0"
487 "AArch64ISD::FCVTAS_HALF\0"
488 "AArch64ISD::FCVTAU_HALF\0"
489 "AArch64ISD::FCVTMS_HALF\0"
490 "AArch64ISD::FCVTMU_HALF\0"
491 "AArch64ISD::FCVTNS_HALF\0"
492 "AArch64ISD::FCVTNU_HALF\0"
493 "AArch64ISD::FCVTPS_HALF\0"
494 "AArch64ISD::FCVTPU_HALF\0"
495 "AArch64ISD::FCVTXN\0"
496 "AArch64ISD::FCVTX_MERGE_PASSTHRU\0"
497 "AArch64ISD::FCVTZS_HALF\0"
498 "AArch64ISD::FCVTZS_MERGE_PASSTHRU\0"
499 "AArch64ISD::FCVTZU_HALF\0"
500 "AArch64ISD::FCVTZU_MERGE_PASSTHRU\0"
501 "AArch64ISD::FDIV_PRED\0"
502 "AArch64ISD::FFLOOR_MERGE_PASSTHRU\0"
503 "AArch64ISD::FMAXNMV_PRED\0"
504 "AArch64ISD::FMAXNM_PRED\0"
505 "AArch64ISD::FMAXV_PRED\0"
506 "AArch64ISD::FMAX_PRED\0"
507 "AArch64ISD::FMA_PRED\0"
508 "AArch64ISD::FMINNMV_PRED\0"
509 "AArch64ISD::FMINNM_PRED\0"
510 "AArch64ISD::FMINV_PRED\0"
511 "AArch64ISD::FMIN_PRED\0"
512 "AArch64ISD::FMOV\0"
513 "AArch64ISD::FMUL_PRED\0"
514 "AArch64ISD::FNEARBYINT_MERGE_PASSTHRU\0"
515 "AArch64ISD::FNEG_MERGE_PASSTHRU\0"
516 "AArch64ISD::FP_EXTEND_MERGE_PASSTHRU\0"
517 "AArch64ISD::FP_ROUND_MERGE_PASSTHRU\0"
518 "AArch64ISD::FRECPE\0"
519 "AArch64ISD::FRECPS\0"
520 "AArch64ISD::FRECPX_MERGE_PASSTHRU\0"
521 "AArch64ISD::FRINT32_MERGE_PASSTHRU\0"
522 "AArch64ISD::FRINT64_MERGE_PASSTHRU\0"
523 "AArch64ISD::FRINT_MERGE_PASSTHRU\0"
524 "AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU\0"
525 "AArch64ISD::FROUND_MERGE_PASSTHRU\0"
526 "AArch64ISD::FRSQRTE\0"
527 "AArch64ISD::FRSQRTS\0"
528 "AArch64ISD::FSQRT_MERGE_PASSTHRU\0"
529 "AArch64ISD::FSUB_PRED\0"
530 "AArch64ISD::FTRUNC32_MERGE_PASSTHRU\0"
531 "AArch64ISD::FTRUNC64_MERGE_PASSTHRU\0"
532 "AArch64ISD::FTRUNC_MERGE_PASSTHRU\0"
533 "AArch64ISD::GLD1Q_INDEX_MERGE_ZERO\0"
534 "AArch64ISD::GLD1Q_MERGE_ZERO\0"
535 "AArch64ISD::GLD1S_IMM_MERGE_ZERO\0"
536 "AArch64ISD::GLD1S_MERGE_ZERO\0"
537 "AArch64ISD::GLD1S_SCALED_MERGE_ZERO\0"
538 "AArch64ISD::GLD1S_SXTW_MERGE_ZERO\0"
539 "AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO\0"
540 "AArch64ISD::GLD1S_UXTW_MERGE_ZERO\0"
541 "AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO\0"
542 "AArch64ISD::GLD1_IMM_MERGE_ZERO\0"
543 "AArch64ISD::GLD1_MERGE_ZERO\0"
544 "AArch64ISD::GLD1_SCALED_MERGE_ZERO\0"
545 "AArch64ISD::GLD1_SXTW_MERGE_ZERO\0"
546 "AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO\0"
547 "AArch64ISD::GLD1_UXTW_MERGE_ZERO\0"
548 "AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO\0"
549 "AArch64ISD::GLDFF1S_IMM_MERGE_ZERO\0"
550 "AArch64ISD::GLDFF1S_MERGE_ZERO\0"
551 "AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO\0"
552 "AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO\0"
553 "AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO\0"
554 "AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO\0"
555 "AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO\0"
556 "AArch64ISD::GLDFF1_IMM_MERGE_ZERO\0"
557 "AArch64ISD::GLDFF1_MERGE_ZERO\0"
558 "AArch64ISD::GLDFF1_SCALED_MERGE_ZERO\0"
559 "AArch64ISD::GLDFF1_SXTW_MERGE_ZERO\0"
560 "AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO\0"
561 "AArch64ISD::GLDFF1_UXTW_MERGE_ZERO\0"
562 "AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO\0"
563 "AArch64ISD::GLDNT1S_MERGE_ZERO\0"
564 "AArch64ISD::GLDNT1_INDEX_MERGE_ZERO\0"
565 "AArch64ISD::GLDNT1_MERGE_ZERO\0"
566 "AArch64ISD::HADDS_PRED\0"
567 "AArch64ISD::HADDU_PRED\0"
568 "AArch64ISD::HVC\0"
569 "AArch64ISD::INOUT_ZA_USE\0"
570 "AArch64ISD::INSR\0"
571 "AArch64ISD::LASTA\0"
572 "AArch64ISD::LASTB\0"
573 "AArch64ISD::LD1DUPpost\0"
574 "AArch64ISD::LD1LANEpost\0"
575 "AArch64ISD::LD1RO_MERGE_ZERO\0"
576 "AArch64ISD::LD1RQ_MERGE_ZERO\0"
577 "AArch64ISD::LD1S_MERGE_ZERO\0"
578 "AArch64ISD::LD1_MERGE_ZERO\0"
579 "AArch64ISD::LD1x2post\0"
580 "AArch64ISD::LD1x3post\0"
581 "AArch64ISD::LD1x4post\0"
582 "AArch64ISD::LD2DUPpost\0"
583 "AArch64ISD::LD2LANEpost\0"
584 "AArch64ISD::LD2post\0"
585 "AArch64ISD::LD3DUPpost\0"
586 "AArch64ISD::LD3LANEpost\0"
587 "AArch64ISD::LD3post\0"
588 "AArch64ISD::LD4DUPpost\0"
589 "AArch64ISD::LD4LANEpost\0"
590 "AArch64ISD::LD4post\0"
591 "AArch64ISD::LDFF1S_MERGE_ZERO\0"
592 "AArch64ISD::LDFF1_MERGE_ZERO\0"
593 "AArch64ISD::LDIAPP\0"
594 "AArch64ISD::LDNF1S_MERGE_ZERO\0"
595 "AArch64ISD::LDNF1_MERGE_ZERO\0"
596 "AArch64ISD::LDNP\0"
597 "AArch64ISD::LDP\0"
598 "AArch64ISD::LOADgot\0"
599 "AArch64ISD::LS64_BUILD\0"
600 "AArch64ISD::LS64_EXTRACT\0"
601 "AArch64ISD::MOVI\0"
602 "AArch64ISD::MOVIedit\0"
603 "AArch64ISD::MOVImsl\0"
604 "AArch64ISD::MOVIshift\0"
605 "AArch64ISD::MRRS\0"
606 "AArch64ISD::MRS\0"
607 "AArch64ISD::MSRR\0"
608 "AArch64ISD::MULHS_PRED\0"
609 "AArch64ISD::MULHU_PRED\0"
610 "AArch64ISD::MUL_PRED\0"
611 "AArch64ISD::MVNImsl\0"
612 "AArch64ISD::MVNIshift\0"
613 "AArch64ISD::NEG_MERGE_PASSTHRU\0"
614 "AArch64ISD::NVCAST\0"
615 "AArch64ISD::ORRi\0"
616 "AArch64ISD::ORV_PRED\0"
617 "AArch64ISD::PMULL\0"
618 "AArch64ISD::PREFETCH\0"
619 "AArch64ISD::PROBED_ALLOCA\0"
620 "AArch64ISD::PTEST\0"
621 "AArch64ISD::PTEST_ANY\0"
622 "AArch64ISD::PTEST_FIRST\0"
623 "AArch64ISD::PTRUE\0"
624 "AArch64ISD::RANGE_PREFETCH\0"
625 "AArch64ISD::RDSVL\0"
626 "AArch64ISD::REINTERPRET_CAST\0"
627 "AArch64ISD::REQUIRES_ZA_SAVE\0"
628 "AArch64ISD::REQUIRES_ZT0_SAVE\0"
629 "AArch64ISD::RESTORE_ZT\0"
630 "AArch64ISD::RET_GLUE\0"
631 "AArch64ISD::REV16\0"
632 "AArch64ISD::REV32\0"
633 "AArch64ISD::REV64\0"
634 "AArch64ISD::REVD_MERGE_PASSTHRU\0"
635 "AArch64ISD::REVH_MERGE_PASSTHRU\0"
636 "AArch64ISD::REVW_MERGE_PASSTHRU\0"
637 "AArch64ISD::RHADDS_PRED\0"
638 "AArch64ISD::RHADDU_PRED\0"
639 "AArch64ISD::RSHRNB_I\0"
640 "AArch64ISD::SADDLP\0"
641 "AArch64ISD::SADDLV\0"
642 "AArch64ISD::SADDV\0"
643 "AArch64ISD::SADDV_PRED\0"
644 "AArch64ISD::SAVE_ZT\0"
645 "AArch64ISD::SBC\0"
646 "AArch64ISD::SBCS\0"
647 "AArch64ISD::SDOT\0"
648 "AArch64ISD::SETCC_MERGE_ZERO\0"
649 "AArch64ISD::SHL_PRED\0"
650 "AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU\0"
651 "AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU\0"
652 "AArch64ISD::SITOF\0"
653 "AArch64ISD::SMAXV\0"
654 "AArch64ISD::SMAXV_PRED\0"
655 "AArch64ISD::SMAX_PRED\0"
656 "AArch64ISD::SME_STATE_ALLOC\0"
657 "AArch64ISD::SME_ZA_LDR\0"
658 "AArch64ISD::SME_ZA_STR\0"
659 "AArch64ISD::SMINV\0"
660 "AArch64ISD::SMINV_PRED\0"
661 "AArch64ISD::SMIN_PRED\0"
662 "AArch64ISD::SMSTART\0"
663 "AArch64ISD::SMSTOP\0"
664 "AArch64ISD::SMULL\0"
665 "AArch64ISD::SPLICE\0"
666 "AArch64ISD::SQABS\0"
667 "AArch64ISD::SQADD\0"
668 "AArch64ISD::SQDMULH\0"
669 "AArch64ISD::SQDMULL\0"
670 "AArch64ISD::SQNEG\0"
671 "AArch64ISD::SQRDMLAH\0"
672 "AArch64ISD::SQRDMLSH\0"
673 "AArch64ISD::SQRDMULH\0"
674 "AArch64ISD::SQRSHL\0"
675 "AArch64ISD::SQRSHRN\0"
676 "AArch64ISD::SQRSHRUN\0"
677 "AArch64ISD::SQSHL\0"
678 "AArch64ISD::SQSHLU_I\0"
679 "AArch64ISD::SQSHL_I\0"
680 "AArch64ISD::SQSHRN\0"
681 "AArch64ISD::SQSHRUN\0"
682 "AArch64ISD::SQSUB\0"
683 "AArch64ISD::SRA_PRED\0"
684 "AArch64ISD::SRL_PRED\0"
685 "AArch64ISD::SRSHR_I\0"
686 "AArch64ISD::SST1Q_INDEX_PRED\0"
687 "AArch64ISD::SST1Q_PRED\0"
688 "AArch64ISD::SST1_IMM_PRED\0"
689 "AArch64ISD::SST1_PRED\0"
690 "AArch64ISD::SST1_SCALED_PRED\0"
691 "AArch64ISD::SST1_SXTW_PRED\0"
692 "AArch64ISD::SST1_SXTW_SCALED_PRED\0"
693 "AArch64ISD::SST1_UXTW_PRED\0"
694 "AArch64ISD::SST1_UXTW_SCALED_PRED\0"
695 "AArch64ISD::SSTNT1_INDEX_PRED\0"
696 "AArch64ISD::SSTNT1_PRED\0"
697 "AArch64ISD::ST1_PRED\0"
698 "AArch64ISD::ST1x2post\0"
699 "AArch64ISD::ST1x3post\0"
700 "AArch64ISD::ST1x4post\0"
701 "AArch64ISD::ST2G\0"
702 "AArch64ISD::ST2LANEpost\0"
703 "AArch64ISD::ST2post\0"
704 "AArch64ISD::ST3LANEpost\0"
705 "AArch64ISD::ST3post\0"
706 "AArch64ISD::ST4LANEpost\0"
707 "AArch64ISD::ST4post\0"
708 "AArch64ISD::STG\0"
709 "AArch64ISD::STILP\0"
710 "AArch64ISD::STNP\0"
711 "AArch64ISD::STP\0"
712 "AArch64ISD::STRICT_FADD_PRED\0"
713 "AArch64ISD::STRICT_FCEIL_MERGE_PASSTHRU\0"
714 "AArch64ISD::STRICT_FCMP\0"
715 "AArch64ISD::STRICT_FCMPE\0"
716 "AArch64ISD::STRICT_FCVTX_MERGE_PASSTHRU\0"
717 "AArch64ISD::STRICT_FCVTZS_MERGE_PASSTHRU\0"
718 "AArch64ISD::STRICT_FCVTZU_MERGE_PASSTHRU\0"
719 "AArch64ISD::STRICT_FDIV_PRED\0"
720 "AArch64ISD::STRICT_FFLOOR_MERGE_PASSTHRU\0"
721 "AArch64ISD::STRICT_FMAXNM_PRED\0"
722 "AArch64ISD::STRICT_FMAX_PRED\0"
723 "AArch64ISD::STRICT_FMA_PRED\0"
724 "AArch64ISD::STRICT_FMINNM_PRED\0"
725 "AArch64ISD::STRICT_FMIN_PRED\0"
726 "AArch64ISD::STRICT_FMUL_PRED\0"
727 "AArch64ISD::STRICT_FNEARBYINT_MERGE_PASSTHRU\0"
728 "AArch64ISD::STRICT_FP_EXTEND_MERGE_PASSTHRU\0"
729 "AArch64ISD::STRICT_FP_ROUND_MERGE_PASSTHRU\0"
730 "AArch64ISD::STRICT_FRINT_MERGE_PASSTHRU\0"
731 "AArch64ISD::STRICT_FROUNDEVEN_MERGE_PASSTHRU\0"
732 "AArch64ISD::STRICT_FROUND_MERGE_PASSTHRU\0"
733 "AArch64ISD::STRICT_FSQRT_MERGE_PASSTHRU\0"
734 "AArch64ISD::STRICT_FSUB_PRED\0"
735 "AArch64ISD::STRICT_FTRUNC_MERGE_PASSTHRU\0"
736 "AArch64ISD::STRICT_SINT_TO_FP_MERGE_PASSTHRU\0"
737 "AArch64ISD::STRICT_UINT_TO_FP_MERGE_PASSTHRU\0"
738 "AArch64ISD::STZ2G\0"
739 "AArch64ISD::STZG\0"
740 "AArch64ISD::SUBS\0"
741 "AArch64ISD::SUNPKHI\0"
742 "AArch64ISD::SUNPKLO\0"
743 "AArch64ISD::SUQADD\0"
744 "AArch64ISD::SVC\0"
745 "AArch64ISD::TBL\0"
746 "AArch64ISD::TBNZ\0"
747 "AArch64ISD::TBZ\0"
748 "AArch64ISD::TC_RETURN\0"
749 "AArch64ISD::THREAD_POINTER\0"
750 "AArch64ISD::TLSDESC_AUTH_CALLSEQ\0"
751 "AArch64ISD::TLSDESC_CALLSEQ\0"
752 "AArch64ISD::TRN1\0"
753 "AArch64ISD::TRN2\0"
754 "AArch64ISD::UADDLP\0"
755 "AArch64ISD::UADDLV\0"
756 "AArch64ISD::UADDV\0"
757 "AArch64ISD::UADDV_PRED\0"
758 "AArch64ISD::UDOT\0"
759 "AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU\0"
760 "AArch64ISD::UITOF\0"
761 "AArch64ISD::UMAXV\0"
762 "AArch64ISD::UMAXV_PRED\0"
763 "AArch64ISD::UMAX_PRED\0"
764 "AArch64ISD::UMINV\0"
765 "AArch64ISD::UMINV_PRED\0"
766 "AArch64ISD::UMIN_PRED\0"
767 "AArch64ISD::UMULL\0"
768 "AArch64ISD::UQADD\0"
769 "AArch64ISD::UQRSHL\0"
770 "AArch64ISD::UQRSHRN\0"
771 "AArch64ISD::UQSHL\0"
772 "AArch64ISD::UQSHL_I\0"
773 "AArch64ISD::UQSHRN\0"
774 "AArch64ISD::UQSUB\0"
775 "AArch64ISD::URSHR_I\0"
776 "AArch64ISD::URSHR_I_PRED\0"
777 "AArch64ISD::USDOT\0"
778 "AArch64ISD::USQADD\0"
779 "AArch64ISD::UUNPKHI\0"
780 "AArch64ISD::UUNPKLO\0"
781 "AArch64ISD::UZP1\0"
782 "AArch64ISD::UZP2\0"
783 "AArch64ISD::VASHR\0"
784 "AArch64ISD::VLSHR\0"
785 "AArch64ISD::VSHL\0"
786 "AArch64ISD::VSLI\0"
787 "AArch64ISD::VSRI\0"
788 "AArch64ISD::WHILEGE_PRED_COUNTER\0"
789 "AArch64ISD::WHILEGT_PRED_COUNTER\0"
790 "AArch64ISD::WHILEHI_PRED_COUNTER\0"
791 "AArch64ISD::WHILEHS_PRED_COUNTER\0"
792 "AArch64ISD::WHILELE_PRED_COUNTER\0"
793 "AArch64ISD::WHILELO_PRED_COUNTER\0"
794 "AArch64ISD::WHILELS_PRED_COUNTER\0"
795 "AArch64ISD::WHILELT_PRED_COUNTER\0"
796 "AArch64ISD::WrapperLarge\0"
797 "AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU\0"
798 "AArch64ISD::ZIP1\0"
799 "AArch64ISD::ZIP2\0"
800 ;
801#ifdef __GNUC__
802#pragma GCC diagnostic pop
803#endif
804
805static constexpr llvm::StringTable
806AArch64SDNodeNames = AArch64SDNodeNamesStorage;
807
808static const VTByHwModePair AArch64VTByHwModeTable[] = {
809 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
810};
811
812static const SDTypeConstraint AArch64SDTypeConstraints[] = {
813 /* 0 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::Other},
814 /* 3 */ {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
815 /* 6 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
816 /* 12 */ {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
817 /* 16 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
818 /* 22 */ {SDTCisSameAs, 2, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
819 /* 25 */ {SDTCisSameAs, 2, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
820 /* 28 */ {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i64},
821 /* 31 */ {SDTCisSameAs, 1, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i64},
822 /* 36 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i64},
823 /* 39 */ {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i64},
824 /* 41 */ {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::v2i64},
825 /* 44 */ {SDTCisInt, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::aarch64svcount},
826 /* 50 */ {SDTCisVT, 3, 0, 0, MVT::i64}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
827 /* 54 */ {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
828 /* 60 */ {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
829 /* 62 */ {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i64}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
830 /* 66 */ {SDTCisVT, 1, 0, 0, MVT::Other}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
831 /* 68 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
832 /* 71 */ {SDTCisSameAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
833 /* 74 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
834 /* 77 */ {SDTCisOpSmallerThanOp, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
835 /* 80 */ {SDTCisVT, 2, 0, 0, MVT::Other}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
836 /* 83 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
837 /* 86 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
838 /* 89 */ {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
839 /* 91 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
840 /* 95 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
841 /* 99 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
842 /* 104 */ {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
843 /* 108 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
844 /* 112 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
845 /* 116 */ {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
846 /* 120 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
847 /* 125 */ {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisSameAs, 3, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 0, 0, 0, MVT::i1}, {SDTCisSameNumEltsAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
848 /* 132 */ {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
849 /* 134 */ {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::nxv1i1}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
850 /* 139 */ {SDTCisSameNumEltsAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 2, 0, 0, MVT::i1}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
851 /* 144 */ {SDTCisOpSmallerThanOp, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
852 /* 148 */ {SDTCisSameAs, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisSameNumEltsAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
853 /* 155 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
854 /* 158 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
855 /* 163 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
856 /* 170 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
857 /* 175 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVTSmallerThanOp, 3, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
858 /* 184 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
859 /* 191 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
860 /* 198 */ {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
861 /* 204 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
862 /* 214 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
863 /* 219 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
864 /* 221 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
865 /* 225 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
866 /* 227 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
867 /* 229 */ {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
868 /* 233 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
869 /* 236 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
870 /* 240 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
871 /* 244 */ {SDTCisPtrTy, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
872 /* 247 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
873 /* 249 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
874 /* 254 */ {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64},
875 /* 256 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
876 /* 258 */ {SDTCisSameNumEltsAs, 1, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
877 /* 262 */ {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
878 /* 264 */ {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
879};
880
881static const SDNodeDesc AArch64SDNodeDescs[] = {
882 {1, 3, 0, 0, 0, 1, 214, 5}, // ABDS_PRED
883 {1, 3, 0, 0, 0, 23, 214, 5}, // ABDU_PRED
884 {1, 3, 0, 0, 0, 45, 214, 5}, // ABS_MERGE_PASSTHRU
885 {1, 3, 0, 0, 0, 76, 229, 4}, // ADC
886 {2, 3, 0, 0, 0, 92, 249, 5}, // ADCS
887 {1, 2, 0, 0, 0, 109, 144, 4}, // ADDHN
888 {1, 2, 0, 0, 0, 127, 105, 3}, // ADDP
889 {2, 2, 0, 0, 0, 144, 250, 4}, // ADDS
890 {1, 2, 0, 0, 0, 161, 230, 3}, // ADDlow
891 {1, 1, 0, 0, 0, 180, 225, 2}, // ADR
892 {1, 1, 0, 0, 0, 196, 225, 2}, // ADRP
893 {2, 2, 0, 0, 0, 213, 250, 4}, // ANDS
894 {1, 2, 0, 0, 0, 230, 262, 2}, // ANDV_PRED
895 {1, 3, 0, 0, 0, 252, 184, 7}, // ASRD_MERGE_OP1
896 {1, 1, 0, 0, 0, 279, 71, 3}, // ASSERT_ZEXT_BOOL
897 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 308, 50, 4}, // AUTH_CALL
898 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 330, 54, 6}, // AUTH_CALL_RVMARKER
899 {0, 5, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 361, 62, 4}, // AUTH_TC_RETURN
900 {1, 2, 0, 0, 0, 388, 170, 5}, // BIC
901 {1, 3, 0, 0, 0, 404, 112, 4}, // BICi
902 {1, 3, 0, 0, 0, 421, 214, 5}, // BITREVERSE_MERGE_PASSTHRU
903 {0, 3, 0|1<<SDNPHasChain, 0, 0, 459, 0, 3}, // BRCOND
904 {1, 3, 0, 0, 0, 478, 104, 4}, // BSP
905 {1, 3, 0, 0, 0, 494, 214, 5}, // BSWAP_MERGE_PASSTHRU
906 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 527, 53, 1}, // CALL
907 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 544, 53, 1}, // CALL_ARM64EC_TO_X64
908 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 576, 53, 1}, // CALL_BTI
909 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 597, 53, 1}, // CALL_RVMARKER
910 {0, 4, 0|1<<SDNPHasChain, 0, 0, 623, 12, 4}, // CB
911 {0, 2, 0|1<<SDNPHasChain, 0, 0, 638, 66, 2}, // CBNZ
912 {0, 2, 0|1<<SDNPHasChain, 0, 0, 655, 66, 2}, // CBZ
913 {1, 5, 0, 0, 0, 671, 6, 6}, // CCMN
914 {1, 5, 0, 0, 0, 688, 6, 6}, // CCMP
915 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 705, 0, 0}, // CHECK_MATCHING_VL
916 {1, 3, 0, 0, 0, 735, 258, 4}, // CLASTA_N
917 {1, 3, 0, 0, 0, 756, 258, 4}, // CLASTB_N
918 {1, 2, 0, 0, 0, 777, 105, 3}, // CMTST
919 {1, 1, 0|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 795, 0, 0}, // COALESCER_BARRIER
920 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 825, 83, 3}, // COND_SMSTART
921 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 850, 83, 3}, // COND_SMSTOP
922 {1, 4, 0, 0, 0, 874, 240, 4}, // CSEL
923 {1, 4, 0, 0, 0, 891, 240, 4}, // CSINC
924 {1, 4, 0, 0, 0, 909, 240, 4}, // CSINV
925 {1, 4, 0, 0, 0, 927, 240, 4}, // CSNEG
926 {1, 3, 0, 0, 0, 945, 214, 5}, // CTLZ_MERGE_PASSTHRU
927 {1, 3, 0, 0, 0, 977, 214, 5}, // CTPOP_MERGE_PASSTHRU
928 {1, 2, 0, 0, 0, 1010, 86, 3}, // CTTZ_ELTS
929 {1, 2, 0, 0, 0, 1032, 86, 3}, // CTTZ_ELTS_ZERO_POISON
930 {1, 1, 0, 0, 0, 1066, 107, 1}, // DUP
931 {1, 2, 0, 0, 0, 1082, 219, 2}, // DUPLANE128
932 {1, 2, 0, 0, 0, 1105, 219, 2}, // DUPLANE16
933 {1, 2, 0, 0, 0, 1127, 219, 2}, // DUPLANE32
934 {1, 2, 0, 0, 0, 1149, 219, 2}, // DUPLANE64
935 {1, 2, 0, 0, 0, 1171, 219, 2}, // DUPLANE8
936 {1, 3, 0, 0, 0, 1192, 120, 5}, // DUP_MERGE_PASSTHRU
937 {1, 0, 0|1<<SDNPHasChain, 0, 0, 1223, 67, 1}, // ENTRY_PSTATE_SM
938 {1, 2, 0, 0, 0, 1251, 262, 2}, // EORV_PRED
939 {1, 3, 0, 0, 0, 1273, 108, 4}, // EXT
940 {1, 3, 0, 0, 0, 1289, 244, 3}, // EXTR
941 {1, 3, 0, 0, 0, 1306, 214, 5}, // FABS_MERGE_PASSTHRU
942 {1, 3, 0, 0, 0, 1338, 258, 4}, // FADDA_PRED
943 {1, 2, 0, 0, 0, 1361, 262, 2}, // FADDV_PRED
944 {1, 3, 0, 0, 0, 1384, 214, 5}, // FADD_PRED
945 {1, 5, 0, 0, 0, 1406, 16, 6}, // FCCMP
946 {1, 3, 0, 0, 0, 1424, 214, 5}, // FCEIL_MERGE_PASSTHRU
947 {1, 2, 0, 0, 0, 1457, 266, 1}, // FCMEQ
948 {1, 2, 0, 0, 0, 1475, 266, 1}, // FCMGE
949 {1, 2, 0, 0, 0, 1493, 266, 1}, // FCMGT
950 {1, 2, 0, 0, 0, 1511, 22, 3}, // FCMP
951 {1, 1, 0, 0, 0, 1528, 95, 4}, // FCVTAS_HALF
952 {1, 1, 0, 0, 0, 1552, 95, 4}, // FCVTAU_HALF
953 {1, 1, 0, 0, 0, 1576, 95, 4}, // FCVTMS_HALF
954 {1, 1, 0, 0, 0, 1600, 95, 4}, // FCVTMU_HALF
955 {1, 1, 0, 0, 0, 1624, 95, 4}, // FCVTNS_HALF
956 {1, 1, 0, 0, 0, 1648, 95, 4}, // FCVTNU_HALF
957 {1, 1, 0, 0, 0, 1672, 95, 4}, // FCVTPS_HALF
958 {1, 1, 0, 0, 0, 1696, 95, 4}, // FCVTPU_HALF
959 {1, 1, 0, 0, 0, 1720, 91, 4}, // FCVTXN
960 {1, 3, 0, 0, 0, 1739, 148, 7}, // FCVTX_MERGE_PASSTHRU
961 {1, 1, 0, 0, 0, 1772, 95, 4}, // FCVTZS_HALF
962 {1, 3, 0, 0, 0, 1796, 148, 7}, // FCVTZS_MERGE_PASSTHRU
963 {1, 1, 0, 0, 0, 1830, 95, 4}, // FCVTZU_HALF
964 {1, 3, 0, 0, 0, 1854, 148, 7}, // FCVTZU_MERGE_PASSTHRU
965 {1, 3, 0, 0, 0, 1888, 214, 5}, // FDIV_PRED
966 {1, 3, 0, 0, 0, 1910, 214, 5}, // FFLOOR_MERGE_PASSTHRU
967 {1, 2, 0, 0, 0, 1944, 262, 2}, // FMAXNMV_PRED
968 {1, 3, 0, 0, 0, 1969, 214, 5}, // FMAXNM_PRED
969 {1, 2, 0, 0, 0, 1993, 262, 2}, // FMAXV_PRED
970 {1, 3, 0, 0, 0, 2016, 214, 5}, // FMAX_PRED
971 {1, 4, 0, 0, 0, 2038, 204, 10}, // FMA_PRED
972 {1, 2, 0, 0, 0, 2059, 262, 2}, // FMINNMV_PRED
973 {1, 3, 0, 0, 0, 2084, 214, 5}, // FMINNM_PRED
974 {1, 2, 0, 0, 0, 2108, 262, 2}, // FMINV_PRED
975 {1, 3, 0, 0, 0, 2131, 214, 5}, // FMIN_PRED
976 {1, 1, 0, 0, 0, 2153, 257, 1}, // FMOV
977 {1, 3, 0, 0, 0, 2170, 214, 5}, // FMUL_PRED
978 {1, 3, 0, 0, 0, 2192, 214, 5}, // FNEARBYINT_MERGE_PASSTHRU
979 {1, 3, 0, 0, 0, 2230, 214, 5}, // FNEG_MERGE_PASSTHRU
980 {1, 3, 0, 0, 0, 2262, 148, 7}, // FP_EXTEND_MERGE_PASSTHRU
981 {1, 4, 0, 0, 0, 2299, 198, 6}, // FP_ROUND_MERGE_PASSTHRU
982 {1, 1, 0, 0, 0, 2335, 227, 2}, // FRECPE
983 {1, 2, 0, 0, 0, 2354, 233, 3}, // FRECPS
984 {1, 3, 0, 0, 0, 2373, 214, 5}, // FRECPX_MERGE_PASSTHRU
985 {1, 3, 0, 0, 0, 2407, 214, 5}, // FRINT32_MERGE_PASSTHRU
986 {1, 3, 0, 0, 0, 2442, 214, 5}, // FRINT64_MERGE_PASSTHRU
987 {1, 3, 0, 0, 0, 2477, 214, 5}, // FRINT_MERGE_PASSTHRU
988 {1, 3, 0, 0, 0, 2510, 214, 5}, // FROUNDEVEN_MERGE_PASSTHRU
989 {1, 3, 0, 0, 0, 2548, 214, 5}, // FROUND_MERGE_PASSTHRU
990 {1, 1, 0, 0, 0, 2582, 227, 2}, // FRSQRTE
991 {1, 2, 0, 0, 0, 2602, 233, 3}, // FRSQRTS
992 {1, 3, 0, 0, 0, 2622, 214, 5}, // FSQRT_MERGE_PASSTHRU
993 {1, 3, 0, 0, 0, 2655, 214, 5}, // FSUB_PRED
994 {1, 3, 0, 0, 0, 2677, 214, 5}, // FTRUNC32_MERGE_PASSTHRU
995 {1, 3, 0, 0, 0, 2713, 214, 5}, // FTRUNC64_MERGE_PASSTHRU
996 {1, 3, 0, 0, 0, 2749, 214, 5}, // FTRUNC_MERGE_PASSTHRU
997 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2783, 0, 0}, // GLD1Q_INDEX_MERGE_ZERO
998 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2818, 134, 5}, // GLD1Q_MERGE_ZERO
999 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2847, 191, 7}, // GLD1S_IMM_MERGE_ZERO
1000 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2880, 163, 7}, // GLD1S_MERGE_ZERO
1001 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2909, 163, 7}, // GLD1S_SCALED_MERGE_ZERO
1002 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2945, 163, 7}, // GLD1S_SXTW_MERGE_ZERO
1003 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2979, 163, 7}, // GLD1S_SXTW_SCALED_MERGE_ZERO
1004 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3020, 163, 7}, // GLD1S_UXTW_MERGE_ZERO
1005 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3054, 163, 7}, // GLD1S_UXTW_SCALED_MERGE_ZERO
1006 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3095, 191, 7}, // GLD1_IMM_MERGE_ZERO
1007 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3127, 163, 7}, // GLD1_MERGE_ZERO
1008 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3155, 163, 7}, // GLD1_SCALED_MERGE_ZERO
1009 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3190, 163, 7}, // GLD1_SXTW_MERGE_ZERO
1010 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3223, 163, 7}, // GLD1_SXTW_SCALED_MERGE_ZERO
1011 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3263, 163, 7}, // GLD1_UXTW_MERGE_ZERO
1012 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3296, 163, 7}, // GLD1_UXTW_SCALED_MERGE_ZERO
1013 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3336, 191, 7}, // GLDFF1S_IMM_MERGE_ZERO
1014 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3371, 163, 7}, // GLDFF1S_MERGE_ZERO
1015 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3402, 163, 7}, // GLDFF1S_SCALED_MERGE_ZERO
1016 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3440, 163, 7}, // GLDFF1S_SXTW_MERGE_ZERO
1017 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3476, 163, 7}, // GLDFF1S_SXTW_SCALED_MERGE_ZERO
1018 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3519, 163, 7}, // GLDFF1S_UXTW_MERGE_ZERO
1019 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3555, 163, 7}, // GLDFF1S_UXTW_SCALED_MERGE_ZERO
1020 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3598, 191, 7}, // GLDFF1_IMM_MERGE_ZERO
1021 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3632, 163, 7}, // GLDFF1_MERGE_ZERO
1022 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3662, 163, 7}, // GLDFF1_SCALED_MERGE_ZERO
1023 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3699, 163, 7}, // GLDFF1_SXTW_MERGE_ZERO
1024 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3734, 163, 7}, // GLDFF1_SXTW_SCALED_MERGE_ZERO
1025 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3776, 163, 7}, // GLDFF1_UXTW_MERGE_ZERO
1026 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3811, 163, 7}, // GLDFF1_UXTW_SCALED_MERGE_ZERO
1027 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3853, 191, 7}, // GLDNT1S_MERGE_ZERO
1028 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3884, 0, 0}, // GLDNT1_INDEX_MERGE_ZERO
1029 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3920, 191, 7}, // GLDNT1_MERGE_ZERO
1030 {1, 3, 0, 0, 0, 3950, 214, 5}, // HADDS_PRED
1031 {1, 3, 0, 0, 0, 3973, 214, 5}, // HADDU_PRED
1032 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3996, 67, 1}, // HVC
1033 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 4012, 0, 0}, // INOUT_ZA_USE
1034 {1, 2, 0, 0, 0, 4037, 107, 1}, // INSR
1035 {1, 2, 0, 0, 0, 4054, 262, 2}, // LASTA
1036 {1, 2, 0, 0, 0, 4072, 262, 2}, // LASTB
1037 {2, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4090, 0, 0}, // LD1DUPpost
1038 {2, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4113, 0, 0}, // LD1LANEpost
1039 {1, 2, 0|1<<SDNPHasChain, 0, 0, 4137, 158, 5}, // LD1RO_MERGE_ZERO
1040 {1, 2, 0|1<<SDNPHasChain, 0, 0, 4166, 158, 5}, // LD1RQ_MERGE_ZERO
1041 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4195, 158, 5}, // LD1S_MERGE_ZERO
1042 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4223, 158, 5}, // LD1_MERGE_ZERO
1043 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4250, 0, 0}, // LD1x2post
1044 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4272, 0, 0}, // LD1x3post
1045 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4294, 0, 0}, // LD1x4post
1046 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4316, 0, 0}, // LD2DUPpost
1047 {3, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4339, 0, 0}, // LD2LANEpost
1048 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4363, 0, 0}, // LD2post
1049 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4383, 0, 0}, // LD3DUPpost
1050 {4, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4406, 0, 0}, // LD3LANEpost
1051 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4430, 0, 0}, // LD3post
1052 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4450, 0, 0}, // LD4DUPpost
1053 {5, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4473, 0, 0}, // LD4LANEpost
1054 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4497, 0, 0}, // LD4post
1055 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4517, 158, 5}, // LDFF1S_MERGE_ZERO
1056 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4547, 158, 5}, // LDFF1_MERGE_ZERO
1057 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4576, 28, 3}, // LDIAPP
1058 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4595, 158, 5}, // LDNF1S_MERGE_ZERO
1059 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4625, 158, 5}, // LDNF1_MERGE_ZERO
1060 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4654, 41, 3}, // LDNP
1061 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4671, 28, 3}, // LDP
1062 {1, 1, 0, 0, 0, 4687, 225, 2}, // LOADgot
1063 {1, 8, 0, 0, 0, 4707, 0, 0}, // LS64_BUILD
1064 {1, 2, 0, 0, 0, 4730, 0, 0}, // LS64_EXTRACT
1065 {1, 1, 0, 0, 0, 4755, 257, 1}, // MOVI
1066 {1, 1, 0, 0, 0, 4772, 257, 1}, // MOVIedit
1067 {1, 2, 0, 0, 0, 4793, 256, 2}, // MOVImsl
1068 {1, 2, 0, 0, 0, 4813, 256, 2}, // MOVIshift
1069 {2, 1, 0|1<<SDNPHasChain, 0, 0, 4835, 39, 2}, // MRRS
1070 {2, 1, 0|1<<SDNPHasChain, 0, 0, 4852, 36, 3}, // MRS
1071 {0, 3, 0|1<<SDNPHasChain, 0, 0, 4868, 254, 2}, // MSRR
1072 {1, 3, 0, 0, 0, 4885, 214, 5}, // MULHS_PRED
1073 {1, 3, 0, 0, 0, 4908, 214, 5}, // MULHU_PRED
1074 {1, 3, 0, 0, 0, 4931, 214, 5}, // MUL_PRED
1075 {1, 2, 0, 0, 0, 4952, 256, 2}, // MVNImsl
1076 {1, 2, 0, 0, 0, 4972, 256, 2}, // MVNIshift
1077 {1, 3, 0, 0, 0, 4994, 214, 5}, // NEG_MERGE_PASSTHRU
1078 {1, 1, 0, 0, 0, 5025, 0, 0}, // NVCAST
1079 {1, 3, 0, 0, 0, 5044, 112, 4}, // ORRi
1080 {1, 2, 0, 0, 0, 5061, 262, 2}, // ORV_PRED
1081 {1, 2, 0, 0, 0, 5082, 74, 3}, // PMULL
1082 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5100, 4, 2}, // PREFETCH
1083 {0, 1, 0|1<<SDNPHasChain, 0, 0, 5121, 53, 1}, // PROBED_ALLOCA
1084 {1, 2, 0, 0, 0, 5147, 25, 3}, // PTEST
1085 {1, 2, 0, 0, 0, 5165, 25, 3}, // PTEST_ANY
1086 {1, 2, 0, 0, 0, 5187, 25, 3}, // PTEST_FIRST
1087 {1, 1, 0, 0, 0, 5211, 132, 2}, // PTRUE
1088 {0, 3, 0|1<<SDNPHasChain, 0, 0, 5229, 3, 3}, // RANGE_PREFETCH
1089 {1, 1, 0, 0, 0, 5256, 72, 2}, // RDSVL
1090 {1, 1, 0, 0, 0, 5274, 0, 0}, // REINTERPRET_CAST
1091 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 5303, 0, 0}, // REQUIRES_ZA_SAVE
1092 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 5332, 0, 0}, // REQUIRES_ZT0_SAVE
1093 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5362, 69, 2}, // RESTORE_ZT
1094 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 5385, 0, 0}, // RET_GLUE
1095 {1, 1, 0, 0, 0, 5406, 226, 1}, // REV16
1096 {1, 1, 0, 0, 0, 5424, 226, 1}, // REV32
1097 {1, 1, 0, 0, 0, 5442, 226, 1}, // REV64
1098 {1, 3, 0, 0, 0, 5460, 214, 5}, // REVD_MERGE_PASSTHRU
1099 {1, 3, 0, 0, 0, 5492, 214, 5}, // REVH_MERGE_PASSTHRU
1100 {1, 3, 0, 0, 0, 5524, 214, 5}, // REVW_MERGE_PASSTHRU
1101 {1, 3, 0, 0, 0, 5556, 214, 5}, // RHADDS_PRED
1102 {1, 3, 0, 0, 0, 5580, 214, 5}, // RHADDU_PRED
1103 {1, 2, 0, 0, 0, 5604, 155, 3}, // RSHRNB_I
1104 {1, 1, 0, 0, 0, 5625, 146, 2}, // SADDLP
1105 {1, 1, 0, 0, 0, 5644, 146, 2}, // SADDLV
1106 {1, 1, 0, 0, 0, 5663, 106, 2}, // SADDV
1107 {1, 2, 0, 0, 0, 5681, 262, 2}, // SADDV_PRED
1108 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5704, 69, 2}, // SAVE_ZT
1109 {1, 3, 0, 0, 0, 5724, 229, 4}, // SBC
1110 {2, 3, 0, 0, 0, 5740, 249, 5}, // SBCS
1111 {1, 3, 0, 0, 0, 5757, 116, 4}, // SDOT
1112 {1, 4, 0, 0, 0, 5774, 125, 7}, // SETCC_MERGE_ZERO
1113 {1, 3, 0, 0, 0, 5803, 214, 5}, // SHL_PRED
1114 {1, 4, 0, 0, 0, 5824, 175, 9}, // SIGN_EXTEND_INREG_MERGE_PASSTHRU
1115 {1, 3, 0, 0, 0, 5869, 148, 7}, // SINT_TO_FP_MERGE_PASSTHRU
1116 {1, 1, 0, 0, 0, 5907, 89, 2}, // SITOF
1117 {1, 1, 0, 0, 0, 5925, 106, 2}, // SMAXV
1118 {1, 2, 0, 0, 0, 5943, 262, 2}, // SMAXV_PRED
1119 {1, 3, 0, 0, 0, 5966, 214, 5}, // SMAX_PRED
1120 {0, 0, 0|1<<SDNPHasChain, 0, 0, 5988, 0, 0}, // SME_STATE_ALLOC
1121 {0, 3, 0|1<<SDNPHasChain, 0, 0, 6016, 68, 3}, // SME_ZA_LDR
1122 {0, 3, 0|1<<SDNPHasChain, 0, 0, 6039, 68, 3}, // SME_ZA_STR
1123 {1, 1, 0, 0, 0, 6062, 106, 2}, // SMINV
1124 {1, 2, 0, 0, 0, 6080, 262, 2}, // SMINV_PRED
1125 {1, 3, 0, 0, 0, 6103, 214, 5}, // SMIN_PRED
1126 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 6125, 67, 1}, // SMSTART
1127 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 6145, 67, 1}, // SMSTOP
1128 {1, 2, 0, 0, 0, 6164, 74, 3}, // SMULL
1129 {1, 3, 0, 0, 0, 6182, 214, 5}, // SPLICE
1130 {1, 1, 0, 0, 0, 6201, 227, 2}, // SQABS
1131 {1, 2, 0, 0, 0, 6219, 233, 3}, // SQADD
1132 {1, 2, 0, 0, 0, 6237, 266, 1}, // SQDMULH
1133 {1, 2, 0, 0, 0, 6257, 264, 3}, // SQDMULL
1134 {1, 1, 0, 0, 0, 6277, 227, 2}, // SQNEG
1135 {1, 3, 0, 0, 0, 6295, 236, 4}, // SQRDMLAH
1136 {1, 3, 0, 0, 0, 6316, 236, 4}, // SQRDMLSH
1137 {1, 2, 0, 0, 0, 6337, 233, 3}, // SQRDMULH
1138 {1, 2, 0, 0, 0, 6358, 233, 3}, // SQRSHL
1139 {1, 2, 0, 0, 0, 6377, 99, 5}, // SQRSHRN
1140 {1, 2, 0, 0, 0, 6397, 99, 5}, // SQRSHRUN
1141 {1, 2, 0, 0, 0, 6418, 233, 3}, // SQSHL
1142 {1, 2, 0, 0, 0, 6436, 247, 2}, // SQSHLU_I
1143 {1, 2, 0, 0, 0, 6457, 247, 2}, // SQSHL_I
1144 {1, 2, 0, 0, 0, 6477, 99, 5}, // SQSHRN
1145 {1, 2, 0, 0, 0, 6496, 99, 5}, // SQSHRUN
1146 {1, 2, 0, 0, 0, 6516, 233, 3}, // SQSUB
1147 {1, 3, 0, 0, 0, 6534, 214, 5}, // SRA_PRED
1148 {1, 3, 0, 0, 0, 6555, 214, 5}, // SRL_PRED
1149 {1, 2, 0, 0, 0, 6576, 247, 2}, // SRSHR_I
1150 {0, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6596, 0, 0}, // SST1Q_INDEX_PRED
1151 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6625, 134, 5}, // SST1Q_PRED
1152 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6648, 191, 7}, // SST1_IMM_PRED
1153 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6674, 163, 7}, // SST1_PRED
1154 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6696, 163, 7}, // SST1_SCALED_PRED
1155 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6725, 163, 7}, // SST1_SXTW_PRED
1156 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6752, 163, 7}, // SST1_SXTW_SCALED_PRED
1157 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6786, 163, 7}, // SST1_UXTW_PRED
1158 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6813, 163, 7}, // SST1_UXTW_SCALED_PRED
1159 {0, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6847, 0, 0}, // SSTNT1_INDEX_PRED
1160 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6877, 191, 7}, // SSTNT1_PRED
1161 {0, 4, 0|1<<SDNPHasChain, 0, 0, 6901, 139, 5}, // ST1_PRED
1162 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6922, 0, 0}, // ST1x2post
1163 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6944, 0, 0}, // ST1x3post
1164 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6966, 0, 0}, // ST1x4post
1165 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6988, 60, 2}, // ST2G
1166 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7005, 0, 0}, // ST2LANEpost
1167 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7029, 0, 0}, // ST2post
1168 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7049, 0, 0}, // ST3LANEpost
1169 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7073, 0, 0}, // ST3post
1170 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7093, 0, 0}, // ST4LANEpost
1171 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7117, 0, 0}, // ST4post
1172 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7137, 60, 2}, // STG
1173 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7153, 28, 3}, // STILP
1174 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7171, 41, 3}, // STNP
1175 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7188, 28, 3}, // STP
1176 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7204, 214, 5}, // STRICT_FADD_PRED
1177 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7233, 214, 5}, // STRICT_FCEIL_MERGE_PASSTHRU
1178 {1, 2, 0|1<<SDNPHasChain, 0|1<<SDNFIsStrictFP, 0, 7273, 22, 3}, // STRICT_FCMP
1179 {1, 2, 0|1<<SDNPHasChain, 0|1<<SDNFIsStrictFP, 0, 7297, 22, 3}, // STRICT_FCMPE
1180 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7322, 148, 7}, // STRICT_FCVTX_MERGE_PASSTHRU
1181 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7362, 148, 7}, // STRICT_FCVTZS_MERGE_PASSTHRU
1182 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7403, 148, 7}, // STRICT_FCVTZU_MERGE_PASSTHRU
1183 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7444, 214, 5}, // STRICT_FDIV_PRED
1184 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7473, 214, 5}, // STRICT_FFLOOR_MERGE_PASSTHRU
1185 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7514, 214, 5}, // STRICT_FMAXNM_PRED
1186 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7545, 214, 5}, // STRICT_FMAX_PRED
1187 {1, 4, 0|1<<SDNPHasChain, 0, 0, 7574, 204, 10}, // STRICT_FMA_PRED
1188 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7602, 214, 5}, // STRICT_FMINNM_PRED
1189 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7633, 214, 5}, // STRICT_FMIN_PRED
1190 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7662, 214, 5}, // STRICT_FMUL_PRED
1191 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7691, 214, 5}, // STRICT_FNEARBYINT_MERGE_PASSTHRU
1192 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7736, 148, 7}, // STRICT_FP_EXTEND_MERGE_PASSTHRU
1193 {1, 4, 0|1<<SDNPHasChain, 0, 0, 7780, 198, 6}, // STRICT_FP_ROUND_MERGE_PASSTHRU
1194 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7823, 214, 5}, // STRICT_FRINT_MERGE_PASSTHRU
1195 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7863, 214, 5}, // STRICT_FROUNDEVEN_MERGE_PASSTHRU
1196 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7908, 214, 5}, // STRICT_FROUND_MERGE_PASSTHRU
1197 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7949, 214, 5}, // STRICT_FSQRT_MERGE_PASSTHRU
1198 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7989, 214, 5}, // STRICT_FSUB_PRED
1199 {1, 3, 0|1<<SDNPHasChain, 0, 0, 8018, 214, 5}, // STRICT_FTRUNC_MERGE_PASSTHRU
1200 {1, 3, 0|1<<SDNPHasChain, 0, 0, 8059, 148, 7}, // STRICT_SINT_TO_FP_MERGE_PASSTHRU
1201 {1, 3, 0|1<<SDNPHasChain, 0, 0, 8104, 148, 7}, // STRICT_UINT_TO_FP_MERGE_PASSTHRU
1202 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 8149, 60, 2}, // STZ2G
1203 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 8167, 60, 2}, // STZG
1204 {2, 2, 0, 0, 0, 8184, 250, 4}, // SUBS
1205 {1, 1, 0, 0, 0, 8201, 77, 3}, // SUNPKHI
1206 {1, 1, 0, 0, 0, 8221, 77, 3}, // SUNPKLO
1207 {1, 2, 0, 0, 0, 8241, 233, 3}, // SUQADD
1208 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 8260, 67, 1}, // SVC
1209 {1, 2, 0, 0, 0, 8276, 113, 3}, // TBL
1210 {0, 3, 0|1<<SDNPHasChain, 0, 0, 8292, 80, 3}, // TBNZ
1211 {0, 3, 0|1<<SDNPHasChain, 0, 0, 8309, 80, 3}, // TBZ
1212 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 8325, 53, 1}, // TC_RETURN
1213 {1, 0, 0, 0, 0, 8347, 53, 1}, // THREAD_POINTER
1214 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 8374, 53, 1}, // TLSDESC_AUTH_CALLSEQ
1215 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 8407, 53, 1}, // TLSDESC_CALLSEQ
1216 {1, 2, 0, 0, 0, 8435, 105, 3}, // TRN1
1217 {1, 2, 0, 0, 0, 8452, 105, 3}, // TRN2
1218 {1, 1, 0, 0, 0, 8469, 146, 2}, // UADDLP
1219 {1, 1, 0, 0, 0, 8488, 146, 2}, // UADDLV
1220 {1, 1, 0, 0, 0, 8507, 106, 2}, // UADDV
1221 {1, 2, 0, 0, 0, 8525, 262, 2}, // UADDV_PRED
1222 {1, 3, 0, 0, 0, 8548, 116, 4}, // UDOT
1223 {1, 3, 0, 0, 0, 8565, 148, 7}, // UINT_TO_FP_MERGE_PASSTHRU
1224 {1, 1, 0, 0, 0, 8603, 89, 2}, // UITOF
1225 {1, 1, 0, 0, 0, 8621, 106, 2}, // UMAXV
1226 {1, 2, 0, 0, 0, 8639, 262, 2}, // UMAXV_PRED
1227 {1, 3, 0, 0, 0, 8662, 214, 5}, // UMAX_PRED
1228 {1, 1, 0, 0, 0, 8684, 106, 2}, // UMINV
1229 {1, 2, 0, 0, 0, 8702, 262, 2}, // UMINV_PRED
1230 {1, 3, 0, 0, 0, 8725, 214, 5}, // UMIN_PRED
1231 {1, 2, 0, 0, 0, 8747, 74, 3}, // UMULL
1232 {1, 2, 0, 0, 0, 8765, 233, 3}, // UQADD
1233 {1, 2, 0, 0, 0, 8783, 233, 3}, // UQRSHL
1234 {1, 2, 0, 0, 0, 8802, 99, 5}, // UQRSHRN
1235 {1, 2, 0, 0, 0, 8822, 233, 3}, // UQSHL
1236 {1, 2, 0, 0, 0, 8840, 247, 2}, // UQSHL_I
1237 {1, 2, 0, 0, 0, 8860, 99, 5}, // UQSHRN
1238 {1, 2, 0, 0, 0, 8879, 233, 3}, // UQSUB
1239 {1, 2, 0, 0, 0, 8897, 247, 2}, // URSHR_I
1240 {1, 3, 0, 0, 0, 8917, 184, 7}, // URSHR_I_PRED
1241 {1, 3, 0, 0, 0, 8942, 116, 4}, // USDOT
1242 {1, 2, 0, 0, 0, 8960, 233, 3}, // USQADD
1243 {1, 1, 0, 0, 0, 8979, 77, 3}, // UUNPKHI
1244 {1, 1, 0, 0, 0, 8999, 77, 3}, // UUNPKLO
1245 {1, 2, 0, 0, 0, 9019, 105, 3}, // UZP1
1246 {1, 2, 0, 0, 0, 9036, 105, 3}, // UZP2
1247 {1, 2, 0, 0, 0, 9053, 247, 2}, // VASHR
1248 {1, 2, 0, 0, 0, 9071, 247, 2}, // VLSHR
1249 {1, 2, 0, 0, 0, 9089, 247, 2}, // VSHL
1250 {1, 3, 0, 0, 0, 9106, 221, 4}, // VSLI
1251 {1, 3, 0, 0, 0, 9123, 221, 4}, // VSRI
1252 {2, 4, 0, 0, 0, 9140, 44, 6}, // WHILEGE_PRED_COUNTER
1253 {2, 4, 0, 0, 0, 9173, 44, 6}, // WHILEGT_PRED_COUNTER
1254 {2, 4, 0, 0, 0, 9206, 44, 6}, // WHILEHI_PRED_COUNTER
1255 {2, 4, 0, 0, 0, 9239, 44, 6}, // WHILEHS_PRED_COUNTER
1256 {2, 4, 0, 0, 0, 9272, 44, 6}, // WHILELE_PRED_COUNTER
1257 {2, 4, 0, 0, 0, 9305, 44, 6}, // WHILELO_PRED_COUNTER
1258 {2, 4, 0, 0, 0, 9338, 44, 6}, // WHILELS_PRED_COUNTER
1259 {2, 4, 0, 0, 0, 9371, 44, 6}, // WHILELT_PRED_COUNTER
1260 {1, 4, 0, 0, 0, 9404, 31, 5}, // WrapperLarge
1261 {1, 4, 0, 0, 0, 9429, 175, 9}, // ZERO_EXTEND_INREG_MERGE_PASSTHRU
1262 {1, 2, 0, 0, 0, 9474, 105, 3}, // ZIP1
1263 {1, 2, 0, 0, 0, 9491, 105, 3}, // ZIP2
1264};
1265
1266static const SDNodeInfo AArch64GenSDNodeInfo(
1267 /*NumOpcodes=*/382, AArch64SDNodeDescs, AArch64SDNodeNames,
1268 AArch64VTByHwModeTable, AArch64SDTypeConstraints);
1269
1270} // namespace llvm
1271
1272#endif // GET_SDNODE_DESC
1273
1274