1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: AArch64.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::AArch64ISD {
14
15enum GenNodeType : unsigned {
16 ABDS_PRED = ISD::BUILTIN_OP_END,
17 ABDU_PRED,
18 ABS_MERGE_PASSTHRU,
19 ADC,
20 ADCS,
21 ADDP,
22 ADDS,
23 ADDlow,
24 ADR,
25 ADRP,
26 ANDS,
27 ANDV_PRED,
28 ASRD_MERGE_OP1,
29 ASSERT_ZEXT_BOOL,
30 AUTH_CALL,
31 AUTH_CALL_RVMARKER,
32 AUTH_TC_RETURN,
33 BIC,
34 BICi,
35 BITREVERSE_MERGE_PASSTHRU,
36 BRCOND,
37 BSP,
38 BSWAP_MERGE_PASSTHRU,
39 CALL,
40 CALL_ARM64EC_TO_X64,
41 CALL_BTI,
42 CALL_RVMARKER,
43 CB,
44 CBNZ,
45 CBZ,
46 CCMN,
47 CCMP,
48 CHECK_MATCHING_VL,
49 CLASTA_N,
50 CLASTB_N,
51 COALESCER_BARRIER,
52 COND_SMSTART,
53 COND_SMSTOP,
54 CSEL,
55 CSINC,
56 CSINV,
57 CSNEG,
58 CTLZ_MERGE_PASSTHRU,
59 CTPOP_MERGE_PASSTHRU,
60 CTTZ_ELTS,
61 DUP,
62 DUPLANE128,
63 DUPLANE16,
64 DUPLANE32,
65 DUPLANE64,
66 DUPLANE8,
67 DUP_MERGE_PASSTHRU,
68 ENTRY_PSTATE_SM,
69 EORV_PRED,
70 EXT,
71 EXTR,
72 FABS_MERGE_PASSTHRU,
73 FADDA_PRED,
74 FADDV_PRED,
75 FADD_PRED,
76 FCCMP,
77 FCEIL_MERGE_PASSTHRU,
78 FCMEQ,
79 FCMGE,
80 FCMGT,
81 FCMP,
82 FCVTAS_HALF,
83 FCVTAU_HALF,
84 FCVTMS_HALF,
85 FCVTMU_HALF,
86 FCVTNS_HALF,
87 FCVTNU_HALF,
88 FCVTPS_HALF,
89 FCVTPU_HALF,
90 FCVTXN,
91 FCVTX_MERGE_PASSTHRU,
92 FCVTZS_HALF,
93 FCVTZS_MERGE_PASSTHRU,
94 FCVTZU_HALF,
95 FCVTZU_MERGE_PASSTHRU,
96 FDIV_PRED,
97 FFLOOR_MERGE_PASSTHRU,
98 FMAXNMV_PRED,
99 FMAXNM_PRED,
100 FMAXV_PRED,
101 FMAX_PRED,
102 FMA_PRED,
103 FMINNMV_PRED,
104 FMINNM_PRED,
105 FMINV_PRED,
106 FMIN_PRED,
107 FMOV,
108 FMUL_PRED,
109 FNEARBYINT_MERGE_PASSTHRU,
110 FNEG_MERGE_PASSTHRU,
111 FP_EXTEND_MERGE_PASSTHRU,
112 FP_ROUND_MERGE_PASSTHRU,
113 FRECPE,
114 FRECPS,
115 FRECPX_MERGE_PASSTHRU,
116 FRINT32_MERGE_PASSTHRU,
117 FRINT64_MERGE_PASSTHRU,
118 FRINT_MERGE_PASSTHRU,
119 FROUNDEVEN_MERGE_PASSTHRU,
120 FROUND_MERGE_PASSTHRU,
121 FRSQRTE,
122 FRSQRTS,
123 FSQRT_MERGE_PASSTHRU,
124 FSUB_PRED,
125 FTRUNC32_MERGE_PASSTHRU,
126 FTRUNC64_MERGE_PASSTHRU,
127 FTRUNC_MERGE_PASSTHRU,
128 GLD1Q_INDEX_MERGE_ZERO,
129 GLD1Q_MERGE_ZERO,
130 GLD1S_IMM_MERGE_ZERO,
131 GLD1S_MERGE_ZERO,
132 GLD1S_SCALED_MERGE_ZERO,
133 GLD1S_SXTW_MERGE_ZERO,
134 GLD1S_SXTW_SCALED_MERGE_ZERO,
135 GLD1S_UXTW_MERGE_ZERO,
136 GLD1S_UXTW_SCALED_MERGE_ZERO,
137 GLD1_IMM_MERGE_ZERO,
138 GLD1_MERGE_ZERO,
139 GLD1_SCALED_MERGE_ZERO,
140 GLD1_SXTW_MERGE_ZERO,
141 GLD1_SXTW_SCALED_MERGE_ZERO,
142 GLD1_UXTW_MERGE_ZERO,
143 GLD1_UXTW_SCALED_MERGE_ZERO,
144 GLDFF1S_IMM_MERGE_ZERO,
145 GLDFF1S_MERGE_ZERO,
146 GLDFF1S_SCALED_MERGE_ZERO,
147 GLDFF1S_SXTW_MERGE_ZERO,
148 GLDFF1S_SXTW_SCALED_MERGE_ZERO,
149 GLDFF1S_UXTW_MERGE_ZERO,
150 GLDFF1S_UXTW_SCALED_MERGE_ZERO,
151 GLDFF1_IMM_MERGE_ZERO,
152 GLDFF1_MERGE_ZERO,
153 GLDFF1_SCALED_MERGE_ZERO,
154 GLDFF1_SXTW_MERGE_ZERO,
155 GLDFF1_SXTW_SCALED_MERGE_ZERO,
156 GLDFF1_UXTW_MERGE_ZERO,
157 GLDFF1_UXTW_SCALED_MERGE_ZERO,
158 GLDNT1S_MERGE_ZERO,
159 GLDNT1_INDEX_MERGE_ZERO,
160 GLDNT1_MERGE_ZERO,
161 HADDS_PRED,
162 HADDU_PRED,
163 INOUT_ZA_USE,
164 INSR,
165 LASTA,
166 LASTB,
167 LD1DUPpost,
168 LD1LANEpost,
169 LD1RO_MERGE_ZERO,
170 LD1RQ_MERGE_ZERO,
171 LD1S_MERGE_ZERO,
172 LD1_MERGE_ZERO,
173 LD1x2post,
174 LD1x3post,
175 LD1x4post,
176 LD2DUPpost,
177 LD2LANEpost,
178 LD2post,
179 LD3DUPpost,
180 LD3LANEpost,
181 LD3post,
182 LD4DUPpost,
183 LD4LANEpost,
184 LD4post,
185 LDFF1S_MERGE_ZERO,
186 LDFF1_MERGE_ZERO,
187 LDIAPP,
188 LDNF1S_MERGE_ZERO,
189 LDNF1_MERGE_ZERO,
190 LDNP,
191 LDP,
192 LOADgot,
193 LS64_BUILD,
194 LS64_EXTRACT,
195 MOVI,
196 MOVIedit,
197 MOVImsl,
198 MOVIshift,
199 MRRS,
200 MRS,
201 MSRR,
202 MULHS_PRED,
203 MULHU_PRED,
204 MUL_PRED,
205 MVNImsl,
206 MVNIshift,
207 NEG_MERGE_PASSTHRU,
208 NVCAST,
209 ORRi,
210 ORV_PRED,
211 PMULL,
212 PREFETCH,
213 PROBED_ALLOCA,
214 PTEST,
215 PTEST_ANY,
216 PTEST_FIRST,
217 PTRUE,
218 RANGE_PREFETCH,
219 RDSVL,
220 REINTERPRET_CAST,
221 REQUIRES_ZA_SAVE,
222 REQUIRES_ZT0_SAVE,
223 RESTORE_ZT,
224 RET_GLUE,
225 REV16,
226 REV32,
227 REV64,
228 REVD_MERGE_PASSTHRU,
229 REVH_MERGE_PASSTHRU,
230 REVW_MERGE_PASSTHRU,
231 RHADDS_PRED,
232 RHADDU_PRED,
233 RSHRNB_I,
234 SADDLP,
235 SADDLV,
236 SADDV,
237 SADDV_PRED,
238 SADDWB,
239 SADDWT,
240 SAVE_ZT,
241 SBC,
242 SBCS,
243 SDOT,
244 SETCC_MERGE_ZERO,
245 SHL_PRED,
246 SIGN_EXTEND_INREG_MERGE_PASSTHRU,
247 SINT_TO_FP_MERGE_PASSTHRU,
248 SITOF,
249 SMAXV,
250 SMAXV_PRED,
251 SMAX_PRED,
252 SME_STATE_ALLOC,
253 SME_ZA_LDR,
254 SME_ZA_STR,
255 SMINV,
256 SMINV_PRED,
257 SMIN_PRED,
258 SMSTART,
259 SMSTOP,
260 SMULL,
261 SPLICE,
262 SQABS,
263 SQADD,
264 SQDMULH,
265 SQDMULL,
266 SQNEG,
267 SQRDMLAH,
268 SQRDMLSH,
269 SQRDMULH,
270 SQRSHL,
271 SQRSHRN,
272 SQRSHRUN,
273 SQSHL,
274 SQSHLU_I,
275 SQSHL_I,
276 SQSHRN,
277 SQSHRUN,
278 SQSUB,
279 SRA_PRED,
280 SRL_PRED,
281 SRSHR_I,
282 SST1Q_INDEX_PRED,
283 SST1Q_PRED,
284 SST1_IMM_PRED,
285 SST1_PRED,
286 SST1_SCALED_PRED,
287 SST1_SXTW_PRED,
288 SST1_SXTW_SCALED_PRED,
289 SST1_UXTW_PRED,
290 SST1_UXTW_SCALED_PRED,
291 SSTNT1_INDEX_PRED,
292 SSTNT1_PRED,
293 ST1_PRED,
294 ST1x2post,
295 ST1x3post,
296 ST1x4post,
297 ST2G,
298 ST2LANEpost,
299 ST2post,
300 ST3LANEpost,
301 ST3post,
302 ST4LANEpost,
303 ST4post,
304 STG,
305 STILP,
306 STNP,
307 STP,
308 STRICT_FCMP,
309 STRICT_FCMPE,
310 STZ2G,
311 STZG,
312 SUBS,
313 SUNPKHI,
314 SUNPKLO,
315 SUQADD,
316 TBL,
317 TBNZ,
318 TBZ,
319 TC_RETURN,
320 THREAD_POINTER,
321 TLSDESC_AUTH_CALLSEQ,
322 TLSDESC_CALLSEQ,
323 TRN1,
324 TRN2,
325 UADDLP,
326 UADDLV,
327 UADDV,
328 UADDV_PRED,
329 UADDWB,
330 UADDWT,
331 UDOT,
332 UINT_TO_FP_MERGE_PASSTHRU,
333 UITOF,
334 UMAXV,
335 UMAXV_PRED,
336 UMAX_PRED,
337 UMINV,
338 UMINV_PRED,
339 UMIN_PRED,
340 UMULL,
341 UQADD,
342 UQRSHL,
343 UQRSHRN,
344 UQSHL,
345 UQSHL_I,
346 UQSHRN,
347 UQSUB,
348 URSHR_I,
349 URSHR_I_PRED,
350 USDOT,
351 USQADD,
352 UUNPKHI,
353 UUNPKLO,
354 UZP1,
355 UZP2,
356 VASHR,
357 VLSHR,
358 VSHL,
359 VSLI,
360 VSRI,
361 WHILEGE_PRED_COUNTER,
362 WHILEGT_PRED_COUNTER,
363 WHILEHI_PRED_COUNTER,
364 WHILEHS_PRED_COUNTER,
365 WHILELE_PRED_COUNTER,
366 WHILELO_PRED_COUNTER,
367 WHILELS_PRED_COUNTER,
368 WHILELT_PRED_COUNTER,
369 WrapperLarge,
370 ZERO_EXTEND_INREG_MERGE_PASSTHRU,
371 ZIP1,
372 ZIP2,
373};
374
375static constexpr unsigned GENERATED_OPCODE_END = ZIP2 + 1;
376
377} // namespace llvm::AArch64ISD
378
379#endif // GET_SDNODE_ENUM
380
381#ifdef GET_SDNODE_DESC
382#undef GET_SDNODE_DESC
383
384namespace llvm {
385
386
387#ifdef __GNUC__
388#pragma GCC diagnostic push
389#pragma GCC diagnostic ignored "-Woverlength-strings"
390#endif
391static constexpr char AArch64SDNodeNamesStorage[] =
392 "\0"
393 "AArch64ISD::ABDS_PRED\0"
394 "AArch64ISD::ABDU_PRED\0"
395 "AArch64ISD::ABS_MERGE_PASSTHRU\0"
396 "AArch64ISD::ADC\0"
397 "AArch64ISD::ADCS\0"
398 "AArch64ISD::ADDP\0"
399 "AArch64ISD::ADDS\0"
400 "AArch64ISD::ADDlow\0"
401 "AArch64ISD::ADR\0"
402 "AArch64ISD::ADRP\0"
403 "AArch64ISD::ANDS\0"
404 "AArch64ISD::ANDV_PRED\0"
405 "AArch64ISD::ASRD_MERGE_OP1\0"
406 "AArch64ISD::ASSERT_ZEXT_BOOL\0"
407 "AArch64ISD::AUTH_CALL\0"
408 "AArch64ISD::AUTH_CALL_RVMARKER\0"
409 "AArch64ISD::AUTH_TC_RETURN\0"
410 "AArch64ISD::BIC\0"
411 "AArch64ISD::BICi\0"
412 "AArch64ISD::BITREVERSE_MERGE_PASSTHRU\0"
413 "AArch64ISD::BRCOND\0"
414 "AArch64ISD::BSP\0"
415 "AArch64ISD::BSWAP_MERGE_PASSTHRU\0"
416 "AArch64ISD::CALL\0"
417 "AArch64ISD::CALL_ARM64EC_TO_X64\0"
418 "AArch64ISD::CALL_BTI\0"
419 "AArch64ISD::CALL_RVMARKER\0"
420 "AArch64ISD::CB\0"
421 "AArch64ISD::CBNZ\0"
422 "AArch64ISD::CBZ\0"
423 "AArch64ISD::CCMN\0"
424 "AArch64ISD::CCMP\0"
425 "AArch64ISD::CHECK_MATCHING_VL\0"
426 "AArch64ISD::CLASTA_N\0"
427 "AArch64ISD::CLASTB_N\0"
428 "AArch64ISD::COALESCER_BARRIER\0"
429 "AArch64ISD::COND_SMSTART\0"
430 "AArch64ISD::COND_SMSTOP\0"
431 "AArch64ISD::CSEL\0"
432 "AArch64ISD::CSINC\0"
433 "AArch64ISD::CSINV\0"
434 "AArch64ISD::CSNEG\0"
435 "AArch64ISD::CTLZ_MERGE_PASSTHRU\0"
436 "AArch64ISD::CTPOP_MERGE_PASSTHRU\0"
437 "AArch64ISD::CTTZ_ELTS\0"
438 "AArch64ISD::DUP\0"
439 "AArch64ISD::DUPLANE128\0"
440 "AArch64ISD::DUPLANE16\0"
441 "AArch64ISD::DUPLANE32\0"
442 "AArch64ISD::DUPLANE64\0"
443 "AArch64ISD::DUPLANE8\0"
444 "AArch64ISD::DUP_MERGE_PASSTHRU\0"
445 "AArch64ISD::ENTRY_PSTATE_SM\0"
446 "AArch64ISD::EORV_PRED\0"
447 "AArch64ISD::EXT\0"
448 "AArch64ISD::EXTR\0"
449 "AArch64ISD::FABS_MERGE_PASSTHRU\0"
450 "AArch64ISD::FADDA_PRED\0"
451 "AArch64ISD::FADDV_PRED\0"
452 "AArch64ISD::FADD_PRED\0"
453 "AArch64ISD::FCCMP\0"
454 "AArch64ISD::FCEIL_MERGE_PASSTHRU\0"
455 "AArch64ISD::FCMEQ\0"
456 "AArch64ISD::FCMGE\0"
457 "AArch64ISD::FCMGT\0"
458 "AArch64ISD::FCMP\0"
459 "AArch64ISD::FCVTAS_HALF\0"
460 "AArch64ISD::FCVTAU_HALF\0"
461 "AArch64ISD::FCVTMS_HALF\0"
462 "AArch64ISD::FCVTMU_HALF\0"
463 "AArch64ISD::FCVTNS_HALF\0"
464 "AArch64ISD::FCVTNU_HALF\0"
465 "AArch64ISD::FCVTPS_HALF\0"
466 "AArch64ISD::FCVTPU_HALF\0"
467 "AArch64ISD::FCVTXN\0"
468 "AArch64ISD::FCVTX_MERGE_PASSTHRU\0"
469 "AArch64ISD::FCVTZS_HALF\0"
470 "AArch64ISD::FCVTZS_MERGE_PASSTHRU\0"
471 "AArch64ISD::FCVTZU_HALF\0"
472 "AArch64ISD::FCVTZU_MERGE_PASSTHRU\0"
473 "AArch64ISD::FDIV_PRED\0"
474 "AArch64ISD::FFLOOR_MERGE_PASSTHRU\0"
475 "AArch64ISD::FMAXNMV_PRED\0"
476 "AArch64ISD::FMAXNM_PRED\0"
477 "AArch64ISD::FMAXV_PRED\0"
478 "AArch64ISD::FMAX_PRED\0"
479 "AArch64ISD::FMA_PRED\0"
480 "AArch64ISD::FMINNMV_PRED\0"
481 "AArch64ISD::FMINNM_PRED\0"
482 "AArch64ISD::FMINV_PRED\0"
483 "AArch64ISD::FMIN_PRED\0"
484 "AArch64ISD::FMOV\0"
485 "AArch64ISD::FMUL_PRED\0"
486 "AArch64ISD::FNEARBYINT_MERGE_PASSTHRU\0"
487 "AArch64ISD::FNEG_MERGE_PASSTHRU\0"
488 "AArch64ISD::FP_EXTEND_MERGE_PASSTHRU\0"
489 "AArch64ISD::FP_ROUND_MERGE_PASSTHRU\0"
490 "AArch64ISD::FRECPE\0"
491 "AArch64ISD::FRECPS\0"
492 "AArch64ISD::FRECPX_MERGE_PASSTHRU\0"
493 "AArch64ISD::FRINT32_MERGE_PASSTHRU\0"
494 "AArch64ISD::FRINT64_MERGE_PASSTHRU\0"
495 "AArch64ISD::FRINT_MERGE_PASSTHRU\0"
496 "AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU\0"
497 "AArch64ISD::FROUND_MERGE_PASSTHRU\0"
498 "AArch64ISD::FRSQRTE\0"
499 "AArch64ISD::FRSQRTS\0"
500 "AArch64ISD::FSQRT_MERGE_PASSTHRU\0"
501 "AArch64ISD::FSUB_PRED\0"
502 "AArch64ISD::FTRUNC32_MERGE_PASSTHRU\0"
503 "AArch64ISD::FTRUNC64_MERGE_PASSTHRU\0"
504 "AArch64ISD::FTRUNC_MERGE_PASSTHRU\0"
505 "AArch64ISD::GLD1Q_INDEX_MERGE_ZERO\0"
506 "AArch64ISD::GLD1Q_MERGE_ZERO\0"
507 "AArch64ISD::GLD1S_IMM_MERGE_ZERO\0"
508 "AArch64ISD::GLD1S_MERGE_ZERO\0"
509 "AArch64ISD::GLD1S_SCALED_MERGE_ZERO\0"
510 "AArch64ISD::GLD1S_SXTW_MERGE_ZERO\0"
511 "AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO\0"
512 "AArch64ISD::GLD1S_UXTW_MERGE_ZERO\0"
513 "AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO\0"
514 "AArch64ISD::GLD1_IMM_MERGE_ZERO\0"
515 "AArch64ISD::GLD1_MERGE_ZERO\0"
516 "AArch64ISD::GLD1_SCALED_MERGE_ZERO\0"
517 "AArch64ISD::GLD1_SXTW_MERGE_ZERO\0"
518 "AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO\0"
519 "AArch64ISD::GLD1_UXTW_MERGE_ZERO\0"
520 "AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO\0"
521 "AArch64ISD::GLDFF1S_IMM_MERGE_ZERO\0"
522 "AArch64ISD::GLDFF1S_MERGE_ZERO\0"
523 "AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO\0"
524 "AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO\0"
525 "AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO\0"
526 "AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO\0"
527 "AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO\0"
528 "AArch64ISD::GLDFF1_IMM_MERGE_ZERO\0"
529 "AArch64ISD::GLDFF1_MERGE_ZERO\0"
530 "AArch64ISD::GLDFF1_SCALED_MERGE_ZERO\0"
531 "AArch64ISD::GLDFF1_SXTW_MERGE_ZERO\0"
532 "AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO\0"
533 "AArch64ISD::GLDFF1_UXTW_MERGE_ZERO\0"
534 "AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO\0"
535 "AArch64ISD::GLDNT1S_MERGE_ZERO\0"
536 "AArch64ISD::GLDNT1_INDEX_MERGE_ZERO\0"
537 "AArch64ISD::GLDNT1_MERGE_ZERO\0"
538 "AArch64ISD::HADDS_PRED\0"
539 "AArch64ISD::HADDU_PRED\0"
540 "AArch64ISD::INOUT_ZA_USE\0"
541 "AArch64ISD::INSR\0"
542 "AArch64ISD::LASTA\0"
543 "AArch64ISD::LASTB\0"
544 "AArch64ISD::LD1DUPpost\0"
545 "AArch64ISD::LD1LANEpost\0"
546 "AArch64ISD::LD1RO_MERGE_ZERO\0"
547 "AArch64ISD::LD1RQ_MERGE_ZERO\0"
548 "AArch64ISD::LD1S_MERGE_ZERO\0"
549 "AArch64ISD::LD1_MERGE_ZERO\0"
550 "AArch64ISD::LD1x2post\0"
551 "AArch64ISD::LD1x3post\0"
552 "AArch64ISD::LD1x4post\0"
553 "AArch64ISD::LD2DUPpost\0"
554 "AArch64ISD::LD2LANEpost\0"
555 "AArch64ISD::LD2post\0"
556 "AArch64ISD::LD3DUPpost\0"
557 "AArch64ISD::LD3LANEpost\0"
558 "AArch64ISD::LD3post\0"
559 "AArch64ISD::LD4DUPpost\0"
560 "AArch64ISD::LD4LANEpost\0"
561 "AArch64ISD::LD4post\0"
562 "AArch64ISD::LDFF1S_MERGE_ZERO\0"
563 "AArch64ISD::LDFF1_MERGE_ZERO\0"
564 "AArch64ISD::LDIAPP\0"
565 "AArch64ISD::LDNF1S_MERGE_ZERO\0"
566 "AArch64ISD::LDNF1_MERGE_ZERO\0"
567 "AArch64ISD::LDNP\0"
568 "AArch64ISD::LDP\0"
569 "AArch64ISD::LOADgot\0"
570 "AArch64ISD::LS64_BUILD\0"
571 "AArch64ISD::LS64_EXTRACT\0"
572 "AArch64ISD::MOVI\0"
573 "AArch64ISD::MOVIedit\0"
574 "AArch64ISD::MOVImsl\0"
575 "AArch64ISD::MOVIshift\0"
576 "AArch64ISD::MRRS\0"
577 "AArch64ISD::MRS\0"
578 "AArch64ISD::MSRR\0"
579 "AArch64ISD::MULHS_PRED\0"
580 "AArch64ISD::MULHU_PRED\0"
581 "AArch64ISD::MUL_PRED\0"
582 "AArch64ISD::MVNImsl\0"
583 "AArch64ISD::MVNIshift\0"
584 "AArch64ISD::NEG_MERGE_PASSTHRU\0"
585 "AArch64ISD::NVCAST\0"
586 "AArch64ISD::ORRi\0"
587 "AArch64ISD::ORV_PRED\0"
588 "AArch64ISD::PMULL\0"
589 "AArch64ISD::PREFETCH\0"
590 "AArch64ISD::PROBED_ALLOCA\0"
591 "AArch64ISD::PTEST\0"
592 "AArch64ISD::PTEST_ANY\0"
593 "AArch64ISD::PTEST_FIRST\0"
594 "AArch64ISD::PTRUE\0"
595 "AArch64ISD::RANGE_PREFETCH\0"
596 "AArch64ISD::RDSVL\0"
597 "AArch64ISD::REINTERPRET_CAST\0"
598 "AArch64ISD::REQUIRES_ZA_SAVE\0"
599 "AArch64ISD::REQUIRES_ZT0_SAVE\0"
600 "AArch64ISD::RESTORE_ZT\0"
601 "AArch64ISD::RET_GLUE\0"
602 "AArch64ISD::REV16\0"
603 "AArch64ISD::REV32\0"
604 "AArch64ISD::REV64\0"
605 "AArch64ISD::REVD_MERGE_PASSTHRU\0"
606 "AArch64ISD::REVH_MERGE_PASSTHRU\0"
607 "AArch64ISD::REVW_MERGE_PASSTHRU\0"
608 "AArch64ISD::RHADDS_PRED\0"
609 "AArch64ISD::RHADDU_PRED\0"
610 "AArch64ISD::RSHRNB_I\0"
611 "AArch64ISD::SADDLP\0"
612 "AArch64ISD::SADDLV\0"
613 "AArch64ISD::SADDV\0"
614 "AArch64ISD::SADDV_PRED\0"
615 "AArch64ISD::SADDWB\0"
616 "AArch64ISD::SADDWT\0"
617 "AArch64ISD::SAVE_ZT\0"
618 "AArch64ISD::SBC\0"
619 "AArch64ISD::SBCS\0"
620 "AArch64ISD::SDOT\0"
621 "AArch64ISD::SETCC_MERGE_ZERO\0"
622 "AArch64ISD::SHL_PRED\0"
623 "AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU\0"
624 "AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU\0"
625 "AArch64ISD::SITOF\0"
626 "AArch64ISD::SMAXV\0"
627 "AArch64ISD::SMAXV_PRED\0"
628 "AArch64ISD::SMAX_PRED\0"
629 "AArch64ISD::SME_STATE_ALLOC\0"
630 "AArch64ISD::SME_ZA_LDR\0"
631 "AArch64ISD::SME_ZA_STR\0"
632 "AArch64ISD::SMINV\0"
633 "AArch64ISD::SMINV_PRED\0"
634 "AArch64ISD::SMIN_PRED\0"
635 "AArch64ISD::SMSTART\0"
636 "AArch64ISD::SMSTOP\0"
637 "AArch64ISD::SMULL\0"
638 "AArch64ISD::SPLICE\0"
639 "AArch64ISD::SQABS\0"
640 "AArch64ISD::SQADD\0"
641 "AArch64ISD::SQDMULH\0"
642 "AArch64ISD::SQDMULL\0"
643 "AArch64ISD::SQNEG\0"
644 "AArch64ISD::SQRDMLAH\0"
645 "AArch64ISD::SQRDMLSH\0"
646 "AArch64ISD::SQRDMULH\0"
647 "AArch64ISD::SQRSHL\0"
648 "AArch64ISD::SQRSHRN\0"
649 "AArch64ISD::SQRSHRUN\0"
650 "AArch64ISD::SQSHL\0"
651 "AArch64ISD::SQSHLU_I\0"
652 "AArch64ISD::SQSHL_I\0"
653 "AArch64ISD::SQSHRN\0"
654 "AArch64ISD::SQSHRUN\0"
655 "AArch64ISD::SQSUB\0"
656 "AArch64ISD::SRA_PRED\0"
657 "AArch64ISD::SRL_PRED\0"
658 "AArch64ISD::SRSHR_I\0"
659 "AArch64ISD::SST1Q_INDEX_PRED\0"
660 "AArch64ISD::SST1Q_PRED\0"
661 "AArch64ISD::SST1_IMM_PRED\0"
662 "AArch64ISD::SST1_PRED\0"
663 "AArch64ISD::SST1_SCALED_PRED\0"
664 "AArch64ISD::SST1_SXTW_PRED\0"
665 "AArch64ISD::SST1_SXTW_SCALED_PRED\0"
666 "AArch64ISD::SST1_UXTW_PRED\0"
667 "AArch64ISD::SST1_UXTW_SCALED_PRED\0"
668 "AArch64ISD::SSTNT1_INDEX_PRED\0"
669 "AArch64ISD::SSTNT1_PRED\0"
670 "AArch64ISD::ST1_PRED\0"
671 "AArch64ISD::ST1x2post\0"
672 "AArch64ISD::ST1x3post\0"
673 "AArch64ISD::ST1x4post\0"
674 "AArch64ISD::ST2G\0"
675 "AArch64ISD::ST2LANEpost\0"
676 "AArch64ISD::ST2post\0"
677 "AArch64ISD::ST3LANEpost\0"
678 "AArch64ISD::ST3post\0"
679 "AArch64ISD::ST4LANEpost\0"
680 "AArch64ISD::ST4post\0"
681 "AArch64ISD::STG\0"
682 "AArch64ISD::STILP\0"
683 "AArch64ISD::STNP\0"
684 "AArch64ISD::STP\0"
685 "AArch64ISD::STRICT_FCMP\0"
686 "AArch64ISD::STRICT_FCMPE\0"
687 "AArch64ISD::STZ2G\0"
688 "AArch64ISD::STZG\0"
689 "AArch64ISD::SUBS\0"
690 "AArch64ISD::SUNPKHI\0"
691 "AArch64ISD::SUNPKLO\0"
692 "AArch64ISD::SUQADD\0"
693 "AArch64ISD::TBL\0"
694 "AArch64ISD::TBNZ\0"
695 "AArch64ISD::TBZ\0"
696 "AArch64ISD::TC_RETURN\0"
697 "AArch64ISD::THREAD_POINTER\0"
698 "AArch64ISD::TLSDESC_AUTH_CALLSEQ\0"
699 "AArch64ISD::TLSDESC_CALLSEQ\0"
700 "AArch64ISD::TRN1\0"
701 "AArch64ISD::TRN2\0"
702 "AArch64ISD::UADDLP\0"
703 "AArch64ISD::UADDLV\0"
704 "AArch64ISD::UADDV\0"
705 "AArch64ISD::UADDV_PRED\0"
706 "AArch64ISD::UADDWB\0"
707 "AArch64ISD::UADDWT\0"
708 "AArch64ISD::UDOT\0"
709 "AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU\0"
710 "AArch64ISD::UITOF\0"
711 "AArch64ISD::UMAXV\0"
712 "AArch64ISD::UMAXV_PRED\0"
713 "AArch64ISD::UMAX_PRED\0"
714 "AArch64ISD::UMINV\0"
715 "AArch64ISD::UMINV_PRED\0"
716 "AArch64ISD::UMIN_PRED\0"
717 "AArch64ISD::UMULL\0"
718 "AArch64ISD::UQADD\0"
719 "AArch64ISD::UQRSHL\0"
720 "AArch64ISD::UQRSHRN\0"
721 "AArch64ISD::UQSHL\0"
722 "AArch64ISD::UQSHL_I\0"
723 "AArch64ISD::UQSHRN\0"
724 "AArch64ISD::UQSUB\0"
725 "AArch64ISD::URSHR_I\0"
726 "AArch64ISD::URSHR_I_PRED\0"
727 "AArch64ISD::USDOT\0"
728 "AArch64ISD::USQADD\0"
729 "AArch64ISD::UUNPKHI\0"
730 "AArch64ISD::UUNPKLO\0"
731 "AArch64ISD::UZP1\0"
732 "AArch64ISD::UZP2\0"
733 "AArch64ISD::VASHR\0"
734 "AArch64ISD::VLSHR\0"
735 "AArch64ISD::VSHL\0"
736 "AArch64ISD::VSLI\0"
737 "AArch64ISD::VSRI\0"
738 "AArch64ISD::WHILEGE_PRED_COUNTER\0"
739 "AArch64ISD::WHILEGT_PRED_COUNTER\0"
740 "AArch64ISD::WHILEHI_PRED_COUNTER\0"
741 "AArch64ISD::WHILEHS_PRED_COUNTER\0"
742 "AArch64ISD::WHILELE_PRED_COUNTER\0"
743 "AArch64ISD::WHILELO_PRED_COUNTER\0"
744 "AArch64ISD::WHILELS_PRED_COUNTER\0"
745 "AArch64ISD::WHILELT_PRED_COUNTER\0"
746 "AArch64ISD::WrapperLarge\0"
747 "AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU\0"
748 "AArch64ISD::ZIP1\0"
749 "AArch64ISD::ZIP2\0"
750 ;
751#ifdef __GNUC__
752#pragma GCC diagnostic pop
753#endif
754
755static constexpr llvm::StringTable
756AArch64SDNodeNames = AArch64SDNodeNamesStorage;
757
758static const VTByHwModePair AArch64VTByHwModeTable[] = {
759 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
760};
761
762static const SDTypeConstraint AArch64SDTypeConstraints[] = {
763 /* 0 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::Other},
764 /* 3 */ {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
765 /* 6 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
766 /* 12 */ {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
767 /* 16 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
768 /* 22 */ {SDTCisSameAs, 2, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
769 /* 25 */ {SDTCisSameAs, 2, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
770 /* 28 */ {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i64},
771 /* 31 */ {SDTCisSameAs, 1, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i64},
772 /* 36 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i64},
773 /* 39 */ {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i64},
774 /* 41 */ {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::v2i64},
775 /* 44 */ {SDTCisInt, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::aarch64svcount},
776 /* 50 */ {SDTCisVT, 3, 0, 0, MVT::i64}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
777 /* 54 */ {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
778 /* 60 */ {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
779 /* 62 */ {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i64}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
780 /* 66 */ {SDTCisVT, 1, 0, 0, MVT::Other}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
781 /* 68 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
782 /* 71 */ {SDTCisSameAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
783 /* 74 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
784 /* 77 */ {SDTCisOpSmallerThanOp, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
785 /* 80 */ {SDTCisVT, 2, 0, 0, MVT::Other}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
786 /* 83 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
787 /* 86 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
788 /* 89 */ {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
789 /* 91 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
790 /* 95 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
791 /* 99 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
792 /* 104 */ {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
793 /* 108 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
794 /* 112 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
795 /* 116 */ {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
796 /* 120 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
797 /* 125 */ {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
798 /* 127 */ {SDTCisSameNumEltsAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 2, 0, 0, MVT::i1}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
799 /* 132 */ {SDTCisSameAs, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisSameNumEltsAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
800 /* 139 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
801 /* 142 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
802 /* 147 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
803 /* 154 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
804 /* 159 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVTSmallerThanOp, 3, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
805 /* 168 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
806 /* 175 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
807 /* 182 */ {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
808 /* 188 */ {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCVecEltisVT, 0, 0, 0, MVT::i1}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
809 /* 196 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
810 /* 206 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
811 /* 211 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
812 /* 213 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
813 /* 217 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
814 /* 219 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
815 /* 221 */ {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
816 /* 225 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
817 /* 228 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
818 /* 232 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
819 /* 236 */ {SDTCisPtrTy, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
820 /* 239 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
821 /* 241 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
822 /* 246 */ {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64},
823 /* 248 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
824 /* 250 */ {SDTCisSameNumEltsAs, 1, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
825 /* 254 */ {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
826 /* 256 */ {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
827};
828
829static const SDNodeDesc AArch64SDNodeDescs[] = {
830 {1, 3, 0, 0, 0, 1, 206, 5}, // ABDS_PRED
831 {1, 3, 0, 0, 0, 23, 206, 5}, // ABDU_PRED
832 {1, 3, 0, 0, 0, 45, 206, 5}, // ABS_MERGE_PASSTHRU
833 {1, 3, 0, 0, 0, 76, 221, 4}, // ADC
834 {2, 3, 0, 0, 0, 92, 241, 5}, // ADCS
835 {1, 2, 0, 0, 0, 109, 105, 3}, // ADDP
836 {2, 2, 0, 0, 0, 126, 242, 4}, // ADDS
837 {1, 2, 0, 0, 0, 143, 222, 3}, // ADDlow
838 {1, 1, 0, 0, 0, 162, 217, 2}, // ADR
839 {1, 1, 0, 0, 0, 178, 217, 2}, // ADRP
840 {2, 2, 0, 0, 0, 195, 242, 4}, // ANDS
841 {1, 2, 0, 0, 0, 212, 254, 2}, // ANDV_PRED
842 {1, 3, 0, 0, 0, 234, 168, 7}, // ASRD_MERGE_OP1
843 {1, 1, 0, 0, 0, 261, 71, 3}, // ASSERT_ZEXT_BOOL
844 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 290, 50, 4}, // AUTH_CALL
845 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 312, 54, 6}, // AUTH_CALL_RVMARKER
846 {0, 5, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 343, 62, 4}, // AUTH_TC_RETURN
847 {1, 2, 0, 0, 0, 370, 154, 5}, // BIC
848 {1, 3, 0, 0, 0, 386, 112, 4}, // BICi
849 {1, 3, 0, 0, 0, 403, 206, 5}, // BITREVERSE_MERGE_PASSTHRU
850 {0, 3, 0|1<<SDNPHasChain, 0, 0, 441, 0, 3}, // BRCOND
851 {1, 3, 0, 0, 0, 460, 104, 4}, // BSP
852 {1, 3, 0, 0, 0, 476, 206, 5}, // BSWAP_MERGE_PASSTHRU
853 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 509, 53, 1}, // CALL
854 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 526, 53, 1}, // CALL_ARM64EC_TO_X64
855 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 558, 53, 1}, // CALL_BTI
856 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 579, 53, 1}, // CALL_RVMARKER
857 {0, 4, 0|1<<SDNPHasChain, 0, 0, 605, 12, 4}, // CB
858 {0, 2, 0|1<<SDNPHasChain, 0, 0, 620, 66, 2}, // CBNZ
859 {0, 2, 0|1<<SDNPHasChain, 0, 0, 637, 66, 2}, // CBZ
860 {1, 5, 0, 0, 0, 653, 6, 6}, // CCMN
861 {1, 5, 0, 0, 0, 670, 6, 6}, // CCMP
862 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 687, 0, 0}, // CHECK_MATCHING_VL
863 {1, 3, 0, 0, 0, 717, 250, 4}, // CLASTA_N
864 {1, 3, 0, 0, 0, 738, 250, 4}, // CLASTB_N
865 {1, 1, 0|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 759, 0, 0}, // COALESCER_BARRIER
866 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 789, 83, 3}, // COND_SMSTART
867 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 814, 83, 3}, // COND_SMSTOP
868 {1, 4, 0, 0, 0, 838, 232, 4}, // CSEL
869 {1, 4, 0, 0, 0, 855, 232, 4}, // CSINC
870 {1, 4, 0, 0, 0, 873, 232, 4}, // CSINV
871 {1, 4, 0, 0, 0, 891, 232, 4}, // CSNEG
872 {1, 3, 0, 0, 0, 909, 206, 5}, // CTLZ_MERGE_PASSTHRU
873 {1, 3, 0, 0, 0, 941, 206, 5}, // CTPOP_MERGE_PASSTHRU
874 {1, 2, 0, 0, 0, 974, 86, 3}, // CTTZ_ELTS
875 {1, 1, 0, 0, 0, 996, 107, 1}, // DUP
876 {1, 2, 0, 0, 0, 1012, 211, 2}, // DUPLANE128
877 {1, 2, 0, 0, 0, 1035, 211, 2}, // DUPLANE16
878 {1, 2, 0, 0, 0, 1057, 211, 2}, // DUPLANE32
879 {1, 2, 0, 0, 0, 1079, 211, 2}, // DUPLANE64
880 {1, 2, 0, 0, 0, 1101, 211, 2}, // DUPLANE8
881 {1, 3, 0, 0, 0, 1122, 120, 5}, // DUP_MERGE_PASSTHRU
882 {1, 0, 0|1<<SDNPHasChain, 0, 0, 1153, 67, 1}, // ENTRY_PSTATE_SM
883 {1, 2, 0, 0, 0, 1181, 254, 2}, // EORV_PRED
884 {1, 3, 0, 0, 0, 1203, 108, 4}, // EXT
885 {1, 3, 0, 0, 0, 1219, 236, 3}, // EXTR
886 {1, 3, 0, 0, 0, 1236, 206, 5}, // FABS_MERGE_PASSTHRU
887 {1, 3, 0, 0, 0, 1268, 250, 4}, // FADDA_PRED
888 {1, 2, 0, 0, 0, 1291, 254, 2}, // FADDV_PRED
889 {1, 3, 0, 0, 0, 1314, 206, 5}, // FADD_PRED
890 {1, 5, 0, 0, 0, 1336, 16, 6}, // FCCMP
891 {1, 3, 0, 0, 0, 1354, 206, 5}, // FCEIL_MERGE_PASSTHRU
892 {1, 2, 0, 0, 0, 1387, 258, 1}, // FCMEQ
893 {1, 2, 0, 0, 0, 1405, 258, 1}, // FCMGE
894 {1, 2, 0, 0, 0, 1423, 258, 1}, // FCMGT
895 {1, 2, 0, 0, 0, 1441, 22, 3}, // FCMP
896 {1, 1, 0, 0, 0, 1458, 95, 4}, // FCVTAS_HALF
897 {1, 1, 0, 0, 0, 1482, 95, 4}, // FCVTAU_HALF
898 {1, 1, 0, 0, 0, 1506, 95, 4}, // FCVTMS_HALF
899 {1, 1, 0, 0, 0, 1530, 95, 4}, // FCVTMU_HALF
900 {1, 1, 0, 0, 0, 1554, 95, 4}, // FCVTNS_HALF
901 {1, 1, 0, 0, 0, 1578, 95, 4}, // FCVTNU_HALF
902 {1, 1, 0, 0, 0, 1602, 95, 4}, // FCVTPS_HALF
903 {1, 1, 0, 0, 0, 1626, 95, 4}, // FCVTPU_HALF
904 {1, 1, 0, 0, 0, 1650, 91, 4}, // FCVTXN
905 {1, 3, 0, 0, 0, 1669, 132, 7}, // FCVTX_MERGE_PASSTHRU
906 {1, 1, 0, 0, 0, 1702, 95, 4}, // FCVTZS_HALF
907 {1, 3, 0, 0, 0, 1726, 132, 7}, // FCVTZS_MERGE_PASSTHRU
908 {1, 1, 0, 0, 0, 1760, 95, 4}, // FCVTZU_HALF
909 {1, 3, 0, 0, 0, 1784, 132, 7}, // FCVTZU_MERGE_PASSTHRU
910 {1, 3, 0, 0, 0, 1818, 206, 5}, // FDIV_PRED
911 {1, 3, 0, 0, 0, 1840, 206, 5}, // FFLOOR_MERGE_PASSTHRU
912 {1, 2, 0, 0, 0, 1874, 254, 2}, // FMAXNMV_PRED
913 {1, 3, 0, 0, 0, 1899, 206, 5}, // FMAXNM_PRED
914 {1, 2, 0, 0, 0, 1923, 254, 2}, // FMAXV_PRED
915 {1, 3, 0, 0, 0, 1946, 206, 5}, // FMAX_PRED
916 {1, 4, 0, 0, 0, 1968, 196, 10}, // FMA_PRED
917 {1, 2, 0, 0, 0, 1989, 254, 2}, // FMINNMV_PRED
918 {1, 3, 0, 0, 0, 2014, 206, 5}, // FMINNM_PRED
919 {1, 2, 0, 0, 0, 2038, 254, 2}, // FMINV_PRED
920 {1, 3, 0, 0, 0, 2061, 206, 5}, // FMIN_PRED
921 {1, 1, 0, 0, 0, 2083, 249, 1}, // FMOV
922 {1, 3, 0, 0, 0, 2100, 206, 5}, // FMUL_PRED
923 {1, 3, 0, 0, 0, 2122, 206, 5}, // FNEARBYINT_MERGE_PASSTHRU
924 {1, 3, 0, 0, 0, 2160, 206, 5}, // FNEG_MERGE_PASSTHRU
925 {1, 3, 0, 0, 0, 2192, 132, 7}, // FP_EXTEND_MERGE_PASSTHRU
926 {1, 4, 0, 0, 0, 2229, 182, 6}, // FP_ROUND_MERGE_PASSTHRU
927 {1, 1, 0, 0, 0, 2265, 219, 2}, // FRECPE
928 {1, 2, 0, 0, 0, 2284, 225, 3}, // FRECPS
929 {1, 3, 0, 0, 0, 2303, 206, 5}, // FRECPX_MERGE_PASSTHRU
930 {1, 3, 0, 0, 0, 2337, 206, 5}, // FRINT32_MERGE_PASSTHRU
931 {1, 3, 0, 0, 0, 2372, 206, 5}, // FRINT64_MERGE_PASSTHRU
932 {1, 3, 0, 0, 0, 2407, 206, 5}, // FRINT_MERGE_PASSTHRU
933 {1, 3, 0, 0, 0, 2440, 206, 5}, // FROUNDEVEN_MERGE_PASSTHRU
934 {1, 3, 0, 0, 0, 2478, 206, 5}, // FROUND_MERGE_PASSTHRU
935 {1, 1, 0, 0, 0, 2512, 219, 2}, // FRSQRTE
936 {1, 2, 0, 0, 0, 2532, 225, 3}, // FRSQRTS
937 {1, 3, 0, 0, 0, 2552, 206, 5}, // FSQRT_MERGE_PASSTHRU
938 {1, 3, 0, 0, 0, 2585, 206, 5}, // FSUB_PRED
939 {1, 3, 0, 0, 0, 2607, 206, 5}, // FTRUNC32_MERGE_PASSTHRU
940 {1, 3, 0, 0, 0, 2643, 206, 5}, // FTRUNC64_MERGE_PASSTHRU
941 {1, 3, 0, 0, 0, 2679, 206, 5}, // FTRUNC_MERGE_PASSTHRU
942 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2713, 0, 0}, // GLD1Q_INDEX_MERGE_ZERO
943 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2748, 175, 7}, // GLD1Q_MERGE_ZERO
944 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2777, 175, 7}, // GLD1S_IMM_MERGE_ZERO
945 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2810, 147, 7}, // GLD1S_MERGE_ZERO
946 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2839, 147, 7}, // GLD1S_SCALED_MERGE_ZERO
947 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2875, 147, 7}, // GLD1S_SXTW_MERGE_ZERO
948 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2909, 147, 7}, // GLD1S_SXTW_SCALED_MERGE_ZERO
949 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2950, 147, 7}, // GLD1S_UXTW_MERGE_ZERO
950 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2984, 147, 7}, // GLD1S_UXTW_SCALED_MERGE_ZERO
951 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3025, 175, 7}, // GLD1_IMM_MERGE_ZERO
952 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3057, 147, 7}, // GLD1_MERGE_ZERO
953 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3085, 147, 7}, // GLD1_SCALED_MERGE_ZERO
954 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3120, 147, 7}, // GLD1_SXTW_MERGE_ZERO
955 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3153, 147, 7}, // GLD1_SXTW_SCALED_MERGE_ZERO
956 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3193, 147, 7}, // GLD1_UXTW_MERGE_ZERO
957 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3226, 147, 7}, // GLD1_UXTW_SCALED_MERGE_ZERO
958 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3266, 175, 7}, // GLDFF1S_IMM_MERGE_ZERO
959 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3301, 147, 7}, // GLDFF1S_MERGE_ZERO
960 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3332, 147, 7}, // GLDFF1S_SCALED_MERGE_ZERO
961 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3370, 147, 7}, // GLDFF1S_SXTW_MERGE_ZERO
962 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3406, 147, 7}, // GLDFF1S_SXTW_SCALED_MERGE_ZERO
963 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3449, 147, 7}, // GLDFF1S_UXTW_MERGE_ZERO
964 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3485, 147, 7}, // GLDFF1S_UXTW_SCALED_MERGE_ZERO
965 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3528, 175, 7}, // GLDFF1_IMM_MERGE_ZERO
966 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3562, 147, 7}, // GLDFF1_MERGE_ZERO
967 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3592, 147, 7}, // GLDFF1_SCALED_MERGE_ZERO
968 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3629, 147, 7}, // GLDFF1_SXTW_MERGE_ZERO
969 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3664, 147, 7}, // GLDFF1_SXTW_SCALED_MERGE_ZERO
970 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3706, 147, 7}, // GLDFF1_UXTW_MERGE_ZERO
971 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3741, 147, 7}, // GLDFF1_UXTW_SCALED_MERGE_ZERO
972 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3783, 175, 7}, // GLDNT1S_MERGE_ZERO
973 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3814, 0, 0}, // GLDNT1_INDEX_MERGE_ZERO
974 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3850, 175, 7}, // GLDNT1_MERGE_ZERO
975 {1, 3, 0, 0, 0, 3880, 206, 5}, // HADDS_PRED
976 {1, 3, 0, 0, 0, 3903, 206, 5}, // HADDU_PRED
977 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 3926, 0, 0}, // INOUT_ZA_USE
978 {1, 2, 0, 0, 0, 3951, 107, 1}, // INSR
979 {1, 2, 0, 0, 0, 3968, 254, 2}, // LASTA
980 {1, 2, 0, 0, 0, 3986, 254, 2}, // LASTB
981 {2, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4004, 0, 0}, // LD1DUPpost
982 {2, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4027, 0, 0}, // LD1LANEpost
983 {1, 2, 0|1<<SDNPHasChain, 0, 0, 4051, 142, 5}, // LD1RO_MERGE_ZERO
984 {1, 2, 0|1<<SDNPHasChain, 0, 0, 4080, 142, 5}, // LD1RQ_MERGE_ZERO
985 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4109, 142, 5}, // LD1S_MERGE_ZERO
986 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4137, 142, 5}, // LD1_MERGE_ZERO
987 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4164, 0, 0}, // LD1x2post
988 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4186, 0, 0}, // LD1x3post
989 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4208, 0, 0}, // LD1x4post
990 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4230, 0, 0}, // LD2DUPpost
991 {3, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4253, 0, 0}, // LD2LANEpost
992 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4277, 0, 0}, // LD2post
993 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4297, 0, 0}, // LD3DUPpost
994 {4, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4320, 0, 0}, // LD3LANEpost
995 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4344, 0, 0}, // LD3post
996 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4364, 0, 0}, // LD4DUPpost
997 {5, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4387, 0, 0}, // LD4LANEpost
998 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4411, 0, 0}, // LD4post
999 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4431, 142, 5}, // LDFF1S_MERGE_ZERO
1000 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4461, 142, 5}, // LDFF1_MERGE_ZERO
1001 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4490, 28, 3}, // LDIAPP
1002 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4509, 142, 5}, // LDNF1S_MERGE_ZERO
1003 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4539, 142, 5}, // LDNF1_MERGE_ZERO
1004 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4568, 41, 3}, // LDNP
1005 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4585, 28, 3}, // LDP
1006 {1, 1, 0, 0, 0, 4601, 217, 2}, // LOADgot
1007 {1, 8, 0, 0, 0, 4621, 0, 0}, // LS64_BUILD
1008 {1, 2, 0, 0, 0, 4644, 0, 0}, // LS64_EXTRACT
1009 {1, 1, 0, 0, 0, 4669, 249, 1}, // MOVI
1010 {1, 1, 0, 0, 0, 4686, 249, 1}, // MOVIedit
1011 {1, 2, 0, 0, 0, 4707, 248, 2}, // MOVImsl
1012 {1, 2, 0, 0, 0, 4727, 248, 2}, // MOVIshift
1013 {2, 1, 0|1<<SDNPHasChain, 0, 0, 4749, 39, 2}, // MRRS
1014 {2, 1, 0|1<<SDNPHasChain, 0, 0, 4766, 36, 3}, // MRS
1015 {0, 3, 0|1<<SDNPHasChain, 0, 0, 4782, 246, 2}, // MSRR
1016 {1, 3, 0, 0, 0, 4799, 206, 5}, // MULHS_PRED
1017 {1, 3, 0, 0, 0, 4822, 206, 5}, // MULHU_PRED
1018 {1, 3, 0, 0, 0, 4845, 206, 5}, // MUL_PRED
1019 {1, 2, 0, 0, 0, 4866, 248, 2}, // MVNImsl
1020 {1, 2, 0, 0, 0, 4886, 248, 2}, // MVNIshift
1021 {1, 3, 0, 0, 0, 4908, 206, 5}, // NEG_MERGE_PASSTHRU
1022 {1, 1, 0, 0, 0, 4939, 0, 0}, // NVCAST
1023 {1, 3, 0, 0, 0, 4958, 112, 4}, // ORRi
1024 {1, 2, 0, 0, 0, 4975, 254, 2}, // ORV_PRED
1025 {1, 2, 0, 0, 0, 4996, 74, 3}, // PMULL
1026 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5014, 4, 2}, // PREFETCH
1027 {0, 1, 0|1<<SDNPHasChain, 0, 0, 5035, 53, 1}, // PROBED_ALLOCA
1028 {1, 2, 0, 0, 0, 5061, 25, 3}, // PTEST
1029 {1, 2, 0, 0, 0, 5079, 25, 3}, // PTEST_ANY
1030 {1, 2, 0, 0, 0, 5101, 25, 3}, // PTEST_FIRST
1031 {1, 1, 0, 0, 0, 5125, 125, 2}, // PTRUE
1032 {0, 3, 0|1<<SDNPHasChain, 0, 0, 5143, 3, 3}, // RANGE_PREFETCH
1033 {1, 1, 0, 0, 0, 5170, 72, 2}, // RDSVL
1034 {1, 1, 0, 0, 0, 5188, 0, 0}, // REINTERPRET_CAST
1035 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 5217, 0, 0}, // REQUIRES_ZA_SAVE
1036 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 5246, 0, 0}, // REQUIRES_ZT0_SAVE
1037 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5276, 69, 2}, // RESTORE_ZT
1038 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 5299, 0, 0}, // RET_GLUE
1039 {1, 1, 0, 0, 0, 5320, 218, 1}, // REV16
1040 {1, 1, 0, 0, 0, 5338, 218, 1}, // REV32
1041 {1, 1, 0, 0, 0, 5356, 218, 1}, // REV64
1042 {1, 3, 0, 0, 0, 5374, 206, 5}, // REVD_MERGE_PASSTHRU
1043 {1, 3, 0, 0, 0, 5406, 206, 5}, // REVH_MERGE_PASSTHRU
1044 {1, 3, 0, 0, 0, 5438, 206, 5}, // REVW_MERGE_PASSTHRU
1045 {1, 3, 0, 0, 0, 5470, 206, 5}, // RHADDS_PRED
1046 {1, 3, 0, 0, 0, 5494, 206, 5}, // RHADDU_PRED
1047 {1, 2, 0, 0, 0, 5518, 139, 3}, // RSHRNB_I
1048 {1, 1, 0, 0, 0, 5539, 137, 2}, // SADDLP
1049 {1, 1, 0, 0, 0, 5558, 137, 2}, // SADDLV
1050 {1, 1, 0, 0, 0, 5577, 106, 2}, // SADDV
1051 {1, 2, 0, 0, 0, 5595, 254, 2}, // SADDV_PRED
1052 {1, 2, 0, 0, 0, 5618, 137, 2}, // SADDWB
1053 {1, 2, 0, 0, 0, 5637, 137, 2}, // SADDWT
1054 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5656, 69, 2}, // SAVE_ZT
1055 {1, 3, 0, 0, 0, 5676, 221, 4}, // SBC
1056 {2, 3, 0, 0, 0, 5692, 241, 5}, // SBCS
1057 {1, 3, 0, 0, 0, 5709, 116, 4}, // SDOT
1058 {1, 4, 0, 0, 0, 5726, 188, 8}, // SETCC_MERGE_ZERO
1059 {1, 3, 0, 0, 0, 5755, 206, 5}, // SHL_PRED
1060 {1, 4, 0, 0, 0, 5776, 159, 9}, // SIGN_EXTEND_INREG_MERGE_PASSTHRU
1061 {1, 3, 0, 0, 0, 5821, 132, 7}, // SINT_TO_FP_MERGE_PASSTHRU
1062 {1, 1, 0, 0, 0, 5859, 89, 2}, // SITOF
1063 {1, 1, 0, 0, 0, 5877, 106, 2}, // SMAXV
1064 {1, 2, 0, 0, 0, 5895, 254, 2}, // SMAXV_PRED
1065 {1, 3, 0, 0, 0, 5918, 206, 5}, // SMAX_PRED
1066 {0, 0, 0|1<<SDNPHasChain, 0, 0, 5940, 0, 0}, // SME_STATE_ALLOC
1067 {0, 3, 0|1<<SDNPHasChain, 0, 0, 5968, 68, 3}, // SME_ZA_LDR
1068 {0, 3, 0|1<<SDNPHasChain, 0, 0, 5991, 68, 3}, // SME_ZA_STR
1069 {1, 1, 0, 0, 0, 6014, 106, 2}, // SMINV
1070 {1, 2, 0, 0, 0, 6032, 254, 2}, // SMINV_PRED
1071 {1, 3, 0, 0, 0, 6055, 206, 5}, // SMIN_PRED
1072 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 6077, 67, 1}, // SMSTART
1073 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 6097, 67, 1}, // SMSTOP
1074 {1, 2, 0, 0, 0, 6116, 74, 3}, // SMULL
1075 {1, 3, 0, 0, 0, 6134, 206, 5}, // SPLICE
1076 {1, 1, 0, 0, 0, 6153, 219, 2}, // SQABS
1077 {1, 2, 0, 0, 0, 6171, 225, 3}, // SQADD
1078 {1, 2, 0, 0, 0, 6189, 258, 1}, // SQDMULH
1079 {1, 2, 0, 0, 0, 6209, 256, 3}, // SQDMULL
1080 {1, 1, 0, 0, 0, 6229, 219, 2}, // SQNEG
1081 {1, 3, 0, 0, 0, 6247, 228, 4}, // SQRDMLAH
1082 {1, 3, 0, 0, 0, 6268, 228, 4}, // SQRDMLSH
1083 {1, 2, 0, 0, 0, 6289, 225, 3}, // SQRDMULH
1084 {1, 2, 0, 0, 0, 6310, 225, 3}, // SQRSHL
1085 {1, 2, 0, 0, 0, 6329, 99, 5}, // SQRSHRN
1086 {1, 2, 0, 0, 0, 6349, 99, 5}, // SQRSHRUN
1087 {1, 2, 0, 0, 0, 6370, 225, 3}, // SQSHL
1088 {1, 2, 0, 0, 0, 6388, 239, 2}, // SQSHLU_I
1089 {1, 2, 0, 0, 0, 6409, 239, 2}, // SQSHL_I
1090 {1, 2, 0, 0, 0, 6429, 99, 5}, // SQSHRN
1091 {1, 2, 0, 0, 0, 6448, 99, 5}, // SQSHRUN
1092 {1, 2, 0, 0, 0, 6468, 225, 3}, // SQSUB
1093 {1, 3, 0, 0, 0, 6486, 206, 5}, // SRA_PRED
1094 {1, 3, 0, 0, 0, 6507, 206, 5}, // SRL_PRED
1095 {1, 2, 0, 0, 0, 6528, 239, 2}, // SRSHR_I
1096 {0, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6548, 0, 0}, // SST1Q_INDEX_PRED
1097 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6577, 175, 7}, // SST1Q_PRED
1098 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6600, 175, 7}, // SST1_IMM_PRED
1099 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6626, 147, 7}, // SST1_PRED
1100 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6648, 147, 7}, // SST1_SCALED_PRED
1101 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6677, 147, 7}, // SST1_SXTW_PRED
1102 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6704, 147, 7}, // SST1_SXTW_SCALED_PRED
1103 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6738, 147, 7}, // SST1_UXTW_PRED
1104 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6765, 147, 7}, // SST1_UXTW_SCALED_PRED
1105 {0, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6799, 0, 0}, // SSTNT1_INDEX_PRED
1106 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6829, 175, 7}, // SSTNT1_PRED
1107 {0, 4, 0|1<<SDNPHasChain, 0, 0, 6853, 127, 5}, // ST1_PRED
1108 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6874, 0, 0}, // ST1x2post
1109 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6896, 0, 0}, // ST1x3post
1110 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6918, 0, 0}, // ST1x4post
1111 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6940, 60, 2}, // ST2G
1112 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6957, 0, 0}, // ST2LANEpost
1113 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6981, 0, 0}, // ST2post
1114 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7001, 0, 0}, // ST3LANEpost
1115 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7025, 0, 0}, // ST3post
1116 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7045, 0, 0}, // ST4LANEpost
1117 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7069, 0, 0}, // ST4post
1118 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7089, 60, 2}, // STG
1119 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7105, 28, 3}, // STILP
1120 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7123, 41, 3}, // STNP
1121 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7140, 28, 3}, // STP
1122 {1, 2, 0|1<<SDNPHasChain, 0|1<<SDNFIsStrictFP, 0, 7156, 22, 3}, // STRICT_FCMP
1123 {1, 2, 0|1<<SDNPHasChain, 0|1<<SDNFIsStrictFP, 0, 7180, 22, 3}, // STRICT_FCMPE
1124 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7205, 60, 2}, // STZ2G
1125 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7223, 60, 2}, // STZG
1126 {2, 2, 0, 0, 0, 7240, 242, 4}, // SUBS
1127 {1, 1, 0, 0, 0, 7257, 77, 3}, // SUNPKHI
1128 {1, 1, 0, 0, 0, 7277, 77, 3}, // SUNPKLO
1129 {1, 2, 0, 0, 0, 7297, 225, 3}, // SUQADD
1130 {1, 2, 0, 0, 0, 7316, 113, 3}, // TBL
1131 {0, 3, 0|1<<SDNPHasChain, 0, 0, 7332, 80, 3}, // TBNZ
1132 {0, 3, 0|1<<SDNPHasChain, 0, 0, 7349, 80, 3}, // TBZ
1133 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 7365, 53, 1}, // TC_RETURN
1134 {1, 0, 0, 0, 0, 7387, 53, 1}, // THREAD_POINTER
1135 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 7414, 53, 1}, // TLSDESC_AUTH_CALLSEQ
1136 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 7447, 53, 1}, // TLSDESC_CALLSEQ
1137 {1, 2, 0, 0, 0, 7475, 105, 3}, // TRN1
1138 {1, 2, 0, 0, 0, 7492, 105, 3}, // TRN2
1139 {1, 1, 0, 0, 0, 7509, 137, 2}, // UADDLP
1140 {1, 1, 0, 0, 0, 7528, 137, 2}, // UADDLV
1141 {1, 1, 0, 0, 0, 7547, 106, 2}, // UADDV
1142 {1, 2, 0, 0, 0, 7565, 254, 2}, // UADDV_PRED
1143 {1, 2, 0, 0, 0, 7588, 137, 2}, // UADDWB
1144 {1, 2, 0, 0, 0, 7607, 137, 2}, // UADDWT
1145 {1, 3, 0, 0, 0, 7626, 116, 4}, // UDOT
1146 {1, 3, 0, 0, 0, 7643, 132, 7}, // UINT_TO_FP_MERGE_PASSTHRU
1147 {1, 1, 0, 0, 0, 7681, 89, 2}, // UITOF
1148 {1, 1, 0, 0, 0, 7699, 106, 2}, // UMAXV
1149 {1, 2, 0, 0, 0, 7717, 254, 2}, // UMAXV_PRED
1150 {1, 3, 0, 0, 0, 7740, 206, 5}, // UMAX_PRED
1151 {1, 1, 0, 0, 0, 7762, 106, 2}, // UMINV
1152 {1, 2, 0, 0, 0, 7780, 254, 2}, // UMINV_PRED
1153 {1, 3, 0, 0, 0, 7803, 206, 5}, // UMIN_PRED
1154 {1, 2, 0, 0, 0, 7825, 74, 3}, // UMULL
1155 {1, 2, 0, 0, 0, 7843, 225, 3}, // UQADD
1156 {1, 2, 0, 0, 0, 7861, 225, 3}, // UQRSHL
1157 {1, 2, 0, 0, 0, 7880, 99, 5}, // UQRSHRN
1158 {1, 2, 0, 0, 0, 7900, 225, 3}, // UQSHL
1159 {1, 2, 0, 0, 0, 7918, 239, 2}, // UQSHL_I
1160 {1, 2, 0, 0, 0, 7938, 99, 5}, // UQSHRN
1161 {1, 2, 0, 0, 0, 7957, 225, 3}, // UQSUB
1162 {1, 2, 0, 0, 0, 7975, 239, 2}, // URSHR_I
1163 {1, 3, 0, 0, 0, 7995, 168, 7}, // URSHR_I_PRED
1164 {1, 3, 0, 0, 0, 8020, 116, 4}, // USDOT
1165 {1, 2, 0, 0, 0, 8038, 225, 3}, // USQADD
1166 {1, 1, 0, 0, 0, 8057, 77, 3}, // UUNPKHI
1167 {1, 1, 0, 0, 0, 8077, 77, 3}, // UUNPKLO
1168 {1, 2, 0, 0, 0, 8097, 105, 3}, // UZP1
1169 {1, 2, 0, 0, 0, 8114, 105, 3}, // UZP2
1170 {1, 2, 0, 0, 0, 8131, 239, 2}, // VASHR
1171 {1, 2, 0, 0, 0, 8149, 239, 2}, // VLSHR
1172 {1, 2, 0, 0, 0, 8167, 239, 2}, // VSHL
1173 {1, 3, 0, 0, 0, 8184, 213, 4}, // VSLI
1174 {1, 3, 0, 0, 0, 8201, 213, 4}, // VSRI
1175 {2, 4, 0, 0, 0, 8218, 44, 6}, // WHILEGE_PRED_COUNTER
1176 {2, 4, 0, 0, 0, 8251, 44, 6}, // WHILEGT_PRED_COUNTER
1177 {2, 4, 0, 0, 0, 8284, 44, 6}, // WHILEHI_PRED_COUNTER
1178 {2, 4, 0, 0, 0, 8317, 44, 6}, // WHILEHS_PRED_COUNTER
1179 {2, 4, 0, 0, 0, 8350, 44, 6}, // WHILELE_PRED_COUNTER
1180 {2, 4, 0, 0, 0, 8383, 44, 6}, // WHILELO_PRED_COUNTER
1181 {2, 4, 0, 0, 0, 8416, 44, 6}, // WHILELS_PRED_COUNTER
1182 {2, 4, 0, 0, 0, 8449, 44, 6}, // WHILELT_PRED_COUNTER
1183 {1, 4, 0, 0, 0, 8482, 31, 5}, // WrapperLarge
1184 {1, 4, 0, 0, 0, 8507, 159, 9}, // ZERO_EXTEND_INREG_MERGE_PASSTHRU
1185 {1, 2, 0, 0, 0, 8552, 105, 3}, // ZIP1
1186 {1, 2, 0, 0, 0, 8569, 105, 3}, // ZIP2
1187};
1188
1189static const SDNodeInfo AArch64GenSDNodeInfo(
1190 /*NumOpcodes=*/357, AArch64SDNodeDescs, AArch64SDNodeNames,
1191 AArch64VTByHwModeTable, AArch64SDTypeConstraints);
1192
1193} // namespace llvm
1194
1195#endif // GET_SDNODE_DESC
1196
1197