1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: AArch64.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::AArch64ISD {
14
15enum GenNodeType : unsigned {
16 ABDS_PRED = ISD::BUILTIN_OP_END,
17 ABDU_PRED,
18 ABS_MERGE_PASSTHRU,
19 ADC,
20 ADCS,
21 ADDP,
22 ADDS,
23 ADDlow,
24 ADR,
25 ADRP,
26 ALLOCATE_ZA_BUFFER,
27 ALLOC_SME_SAVE_BUFFER,
28 ANDS,
29 ANDV_PRED,
30 ASRD_MERGE_OP1,
31 ASSERT_ZEXT_BOOL,
32 AUTH_CALL,
33 AUTH_CALL_RVMARKER,
34 AUTH_TC_RETURN,
35 BIC,
36 BICi,
37 BITREVERSE_MERGE_PASSTHRU,
38 BRCOND,
39 BSP,
40 BSWAP_MERGE_PASSTHRU,
41 CALL,
42 CALL_ARM64EC_TO_X64,
43 CALL_BTI,
44 CALL_RVMARKER,
45 CB,
46 CBNZ,
47 CBZ,
48 CCMN,
49 CCMP,
50 CHECK_MATCHING_VL,
51 CLASTA_N,
52 CLASTB_N,
53 COALESCER_BARRIER,
54 COND_SMSTART,
55 COND_SMSTOP,
56 CSEL,
57 CSINC,
58 CSINV,
59 CSNEG,
60 CTLZ_MERGE_PASSTHRU,
61 CTPOP_MERGE_PASSTHRU,
62 CTTZ_ELTS,
63 DUP,
64 DUPLANE128,
65 DUPLANE16,
66 DUPLANE32,
67 DUPLANE64,
68 DUPLANE8,
69 DUP_MERGE_PASSTHRU,
70 ENTRY_PSTATE_SM,
71 EORV_PRED,
72 EXT,
73 EXTR,
74 FABS_MERGE_PASSTHRU,
75 FADDA_PRED,
76 FADDV_PRED,
77 FADD_PRED,
78 FCCMP,
79 FCEIL_MERGE_PASSTHRU,
80 FCMEQ,
81 FCMGE,
82 FCMGT,
83 FCMP,
84 FCVTAS_HALF,
85 FCVTAU_HALF,
86 FCVTMS_HALF,
87 FCVTMU_HALF,
88 FCVTNS_HALF,
89 FCVTNU_HALF,
90 FCVTPS_HALF,
91 FCVTPU_HALF,
92 FCVTXN,
93 FCVTX_MERGE_PASSTHRU,
94 FCVTZS_HALF,
95 FCVTZS_MERGE_PASSTHRU,
96 FCVTZU_HALF,
97 FCVTZU_MERGE_PASSTHRU,
98 FDIV_PRED,
99 FFLOOR_MERGE_PASSTHRU,
100 FMAXNMV_PRED,
101 FMAXNM_PRED,
102 FMAXV_PRED,
103 FMAX_PRED,
104 FMA_PRED,
105 FMINNMV_PRED,
106 FMINNM_PRED,
107 FMINV_PRED,
108 FMIN_PRED,
109 FMOV,
110 FMUL_PRED,
111 FNEARBYINT_MERGE_PASSTHRU,
112 FNEG_MERGE_PASSTHRU,
113 FP_EXTEND_MERGE_PASSTHRU,
114 FP_ROUND_MERGE_PASSTHRU,
115 FRECPE,
116 FRECPS,
117 FRECPX_MERGE_PASSTHRU,
118 FRINT32_MERGE_PASSTHRU,
119 FRINT64_MERGE_PASSTHRU,
120 FRINT_MERGE_PASSTHRU,
121 FROUNDEVEN_MERGE_PASSTHRU,
122 FROUND_MERGE_PASSTHRU,
123 FRSQRTE,
124 FRSQRTS,
125 FSQRT_MERGE_PASSTHRU,
126 FSUB_PRED,
127 FTRUNC32_MERGE_PASSTHRU,
128 FTRUNC64_MERGE_PASSTHRU,
129 FTRUNC_MERGE_PASSTHRU,
130 GET_SME_SAVE_SIZE,
131 GLD1Q_INDEX_MERGE_ZERO,
132 GLD1Q_MERGE_ZERO,
133 GLD1S_IMM_MERGE_ZERO,
134 GLD1S_MERGE_ZERO,
135 GLD1S_SCALED_MERGE_ZERO,
136 GLD1S_SXTW_MERGE_ZERO,
137 GLD1S_SXTW_SCALED_MERGE_ZERO,
138 GLD1S_UXTW_MERGE_ZERO,
139 GLD1S_UXTW_SCALED_MERGE_ZERO,
140 GLD1_IMM_MERGE_ZERO,
141 GLD1_MERGE_ZERO,
142 GLD1_SCALED_MERGE_ZERO,
143 GLD1_SXTW_MERGE_ZERO,
144 GLD1_SXTW_SCALED_MERGE_ZERO,
145 GLD1_UXTW_MERGE_ZERO,
146 GLD1_UXTW_SCALED_MERGE_ZERO,
147 GLDFF1S_IMM_MERGE_ZERO,
148 GLDFF1S_MERGE_ZERO,
149 GLDFF1S_SCALED_MERGE_ZERO,
150 GLDFF1S_SXTW_MERGE_ZERO,
151 GLDFF1S_SXTW_SCALED_MERGE_ZERO,
152 GLDFF1S_UXTW_MERGE_ZERO,
153 GLDFF1S_UXTW_SCALED_MERGE_ZERO,
154 GLDFF1_IMM_MERGE_ZERO,
155 GLDFF1_MERGE_ZERO,
156 GLDFF1_SCALED_MERGE_ZERO,
157 GLDFF1_SXTW_MERGE_ZERO,
158 GLDFF1_SXTW_SCALED_MERGE_ZERO,
159 GLDFF1_UXTW_MERGE_ZERO,
160 GLDFF1_UXTW_SCALED_MERGE_ZERO,
161 GLDNT1S_MERGE_ZERO,
162 GLDNT1_INDEX_MERGE_ZERO,
163 GLDNT1_MERGE_ZERO,
164 HADDS_PRED,
165 HADDU_PRED,
166 INIT_TPIDR2OBJ,
167 INOUT_ZA_USE,
168 INSR,
169 LASTA,
170 LASTB,
171 LD1DUPpost,
172 LD1LANEpost,
173 LD1RO_MERGE_ZERO,
174 LD1RQ_MERGE_ZERO,
175 LD1S_MERGE_ZERO,
176 LD1_MERGE_ZERO,
177 LD1x2post,
178 LD1x3post,
179 LD1x4post,
180 LD2DUPpost,
181 LD2LANEpost,
182 LD2post,
183 LD3DUPpost,
184 LD3LANEpost,
185 LD3post,
186 LD4DUPpost,
187 LD4LANEpost,
188 LD4post,
189 LDFF1S_MERGE_ZERO,
190 LDFF1_MERGE_ZERO,
191 LDIAPP,
192 LDNF1S_MERGE_ZERO,
193 LDNF1_MERGE_ZERO,
194 LDNP,
195 LDP,
196 LOADgot,
197 LS64_BUILD,
198 LS64_EXTRACT,
199 MOVI,
200 MOVIedit,
201 MOVImsl,
202 MOVIshift,
203 MRRS,
204 MRS,
205 MSRR,
206 MULHS_PRED,
207 MULHU_PRED,
208 MUL_PRED,
209 MVNImsl,
210 MVNIshift,
211 NEG_MERGE_PASSTHRU,
212 NVCAST,
213 ORRi,
214 ORV_PRED,
215 PMULL,
216 PREFETCH,
217 PROBED_ALLOCA,
218 PTEST,
219 PTEST_ANY,
220 PTEST_FIRST,
221 PTRUE,
222 RANGE_PREFETCH,
223 RDSVL,
224 REINTERPRET_CAST,
225 REQUIRES_ZA_SAVE,
226 REQUIRES_ZT0_SAVE,
227 RESTORE_ZA,
228 RESTORE_ZT,
229 RET_GLUE,
230 REV16,
231 REV32,
232 REV64,
233 REVD_MERGE_PASSTHRU,
234 REVH_MERGE_PASSTHRU,
235 REVW_MERGE_PASSTHRU,
236 RHADDS_PRED,
237 RHADDU_PRED,
238 RSHRNB_I,
239 SADDLP,
240 SADDLV,
241 SADDV,
242 SADDV_PRED,
243 SADDWB,
244 SADDWT,
245 SAVE_ZT,
246 SBC,
247 SBCS,
248 SDIV_PRED,
249 SDOT,
250 SETCC_MERGE_ZERO,
251 SHL_PRED,
252 SIGN_EXTEND_INREG_MERGE_PASSTHRU,
253 SINT_TO_FP_MERGE_PASSTHRU,
254 SITOF,
255 SMAXV,
256 SMAXV_PRED,
257 SMAX_PRED,
258 SME_STATE_ALLOC,
259 SME_ZA_LDR,
260 SME_ZA_STR,
261 SMINV,
262 SMINV_PRED,
263 SMIN_PRED,
264 SMSTART,
265 SMSTOP,
266 SMULL,
267 SPLICE,
268 SQADD,
269 SQDMULH,
270 SQDMULL,
271 SQRDMLAH,
272 SQRDMLSH,
273 SQRDMULH,
274 SQRSHL,
275 SQRSHRN,
276 SQRSHRUN,
277 SQSHL,
278 SQSHLU_I,
279 SQSHL_I,
280 SQSHRN,
281 SQSHRUN,
282 SQSUB,
283 SRA_PRED,
284 SRL_PRED,
285 SRSHR_I,
286 SST1Q_INDEX_PRED,
287 SST1Q_PRED,
288 SST1_IMM_PRED,
289 SST1_PRED,
290 SST1_SCALED_PRED,
291 SST1_SXTW_PRED,
292 SST1_SXTW_SCALED_PRED,
293 SST1_UXTW_PRED,
294 SST1_UXTW_SCALED_PRED,
295 SSTNT1_INDEX_PRED,
296 SSTNT1_PRED,
297 ST1_PRED,
298 ST1x2post,
299 ST1x3post,
300 ST1x4post,
301 ST2G,
302 ST2LANEpost,
303 ST2post,
304 ST3LANEpost,
305 ST3post,
306 ST4LANEpost,
307 ST4post,
308 STG,
309 STILP,
310 STNP,
311 STP,
312 STRICT_FCMP,
313 STRICT_FCMPE,
314 STZ2G,
315 STZG,
316 SUBS,
317 SUNPKHI,
318 SUNPKLO,
319 TBL,
320 TBNZ,
321 TBZ,
322 TC_RETURN,
323 THREAD_POINTER,
324 TLSDESC_AUTH_CALLSEQ,
325 TLSDESC_CALLSEQ,
326 TRN1,
327 TRN2,
328 UADDLP,
329 UADDLV,
330 UADDV,
331 UADDV_PRED,
332 UADDWB,
333 UADDWT,
334 UDIV_PRED,
335 UDOT,
336 UINT_TO_FP_MERGE_PASSTHRU,
337 UITOF,
338 UMAXV,
339 UMAXV_PRED,
340 UMAX_PRED,
341 UMINV,
342 UMINV_PRED,
343 UMIN_PRED,
344 UMULL,
345 UQADD,
346 UQRSHL,
347 UQRSHRN,
348 UQSHL,
349 UQSHL_I,
350 UQSHRN,
351 UQSUB,
352 URSHR_I,
353 URSHR_I_PRED,
354 USDOT,
355 UUNPKHI,
356 UUNPKLO,
357 UZP1,
358 UZP2,
359 VASHR,
360 VLSHR,
361 VSHL,
362 VSLI,
363 VSRI,
364 WrapperLarge,
365 ZERO_EXTEND_INREG_MERGE_PASSTHRU,
366 ZIP1,
367 ZIP2,
368};
369
370static constexpr unsigned GENERATED_OPCODE_END = ZIP2 + 1;
371
372} // namespace llvm::AArch64ISD
373
374#endif // GET_SDNODE_ENUM
375
376#ifdef GET_SDNODE_DESC
377#undef GET_SDNODE_DESC
378
379namespace llvm {
380
381
382#ifdef __GNUC__
383#pragma GCC diagnostic push
384#pragma GCC diagnostic ignored "-Woverlength-strings"
385#endif
386static constexpr char AArch64SDNodeNamesStorage[] =
387 "\0"
388 "AArch64ISD::ABDS_PRED\0"
389 "AArch64ISD::ABDU_PRED\0"
390 "AArch64ISD::ABS_MERGE_PASSTHRU\0"
391 "AArch64ISD::ADC\0"
392 "AArch64ISD::ADCS\0"
393 "AArch64ISD::ADDP\0"
394 "AArch64ISD::ADDS\0"
395 "AArch64ISD::ADDlow\0"
396 "AArch64ISD::ADR\0"
397 "AArch64ISD::ADRP\0"
398 "AArch64ISD::ALLOCATE_ZA_BUFFER\0"
399 "AArch64ISD::ALLOC_SME_SAVE_BUFFER\0"
400 "AArch64ISD::ANDS\0"
401 "AArch64ISD::ANDV_PRED\0"
402 "AArch64ISD::ASRD_MERGE_OP1\0"
403 "AArch64ISD::ASSERT_ZEXT_BOOL\0"
404 "AArch64ISD::AUTH_CALL\0"
405 "AArch64ISD::AUTH_CALL_RVMARKER\0"
406 "AArch64ISD::AUTH_TC_RETURN\0"
407 "AArch64ISD::BIC\0"
408 "AArch64ISD::BICi\0"
409 "AArch64ISD::BITREVERSE_MERGE_PASSTHRU\0"
410 "AArch64ISD::BRCOND\0"
411 "AArch64ISD::BSP\0"
412 "AArch64ISD::BSWAP_MERGE_PASSTHRU\0"
413 "AArch64ISD::CALL\0"
414 "AArch64ISD::CALL_ARM64EC_TO_X64\0"
415 "AArch64ISD::CALL_BTI\0"
416 "AArch64ISD::CALL_RVMARKER\0"
417 "AArch64ISD::CB\0"
418 "AArch64ISD::CBNZ\0"
419 "AArch64ISD::CBZ\0"
420 "AArch64ISD::CCMN\0"
421 "AArch64ISD::CCMP\0"
422 "AArch64ISD::CHECK_MATCHING_VL\0"
423 "AArch64ISD::CLASTA_N\0"
424 "AArch64ISD::CLASTB_N\0"
425 "AArch64ISD::COALESCER_BARRIER\0"
426 "AArch64ISD::COND_SMSTART\0"
427 "AArch64ISD::COND_SMSTOP\0"
428 "AArch64ISD::CSEL\0"
429 "AArch64ISD::CSINC\0"
430 "AArch64ISD::CSINV\0"
431 "AArch64ISD::CSNEG\0"
432 "AArch64ISD::CTLZ_MERGE_PASSTHRU\0"
433 "AArch64ISD::CTPOP_MERGE_PASSTHRU\0"
434 "AArch64ISD::CTTZ_ELTS\0"
435 "AArch64ISD::DUP\0"
436 "AArch64ISD::DUPLANE128\0"
437 "AArch64ISD::DUPLANE16\0"
438 "AArch64ISD::DUPLANE32\0"
439 "AArch64ISD::DUPLANE64\0"
440 "AArch64ISD::DUPLANE8\0"
441 "AArch64ISD::DUP_MERGE_PASSTHRU\0"
442 "AArch64ISD::ENTRY_PSTATE_SM\0"
443 "AArch64ISD::EORV_PRED\0"
444 "AArch64ISD::EXT\0"
445 "AArch64ISD::EXTR\0"
446 "AArch64ISD::FABS_MERGE_PASSTHRU\0"
447 "AArch64ISD::FADDA_PRED\0"
448 "AArch64ISD::FADDV_PRED\0"
449 "AArch64ISD::FADD_PRED\0"
450 "AArch64ISD::FCCMP\0"
451 "AArch64ISD::FCEIL_MERGE_PASSTHRU\0"
452 "AArch64ISD::FCMEQ\0"
453 "AArch64ISD::FCMGE\0"
454 "AArch64ISD::FCMGT\0"
455 "AArch64ISD::FCMP\0"
456 "AArch64ISD::FCVTAS_HALF\0"
457 "AArch64ISD::FCVTAU_HALF\0"
458 "AArch64ISD::FCVTMS_HALF\0"
459 "AArch64ISD::FCVTMU_HALF\0"
460 "AArch64ISD::FCVTNS_HALF\0"
461 "AArch64ISD::FCVTNU_HALF\0"
462 "AArch64ISD::FCVTPS_HALF\0"
463 "AArch64ISD::FCVTPU_HALF\0"
464 "AArch64ISD::FCVTXN\0"
465 "AArch64ISD::FCVTX_MERGE_PASSTHRU\0"
466 "AArch64ISD::FCVTZS_HALF\0"
467 "AArch64ISD::FCVTZS_MERGE_PASSTHRU\0"
468 "AArch64ISD::FCVTZU_HALF\0"
469 "AArch64ISD::FCVTZU_MERGE_PASSTHRU\0"
470 "AArch64ISD::FDIV_PRED\0"
471 "AArch64ISD::FFLOOR_MERGE_PASSTHRU\0"
472 "AArch64ISD::FMAXNMV_PRED\0"
473 "AArch64ISD::FMAXNM_PRED\0"
474 "AArch64ISD::FMAXV_PRED\0"
475 "AArch64ISD::FMAX_PRED\0"
476 "AArch64ISD::FMA_PRED\0"
477 "AArch64ISD::FMINNMV_PRED\0"
478 "AArch64ISD::FMINNM_PRED\0"
479 "AArch64ISD::FMINV_PRED\0"
480 "AArch64ISD::FMIN_PRED\0"
481 "AArch64ISD::FMOV\0"
482 "AArch64ISD::FMUL_PRED\0"
483 "AArch64ISD::FNEARBYINT_MERGE_PASSTHRU\0"
484 "AArch64ISD::FNEG_MERGE_PASSTHRU\0"
485 "AArch64ISD::FP_EXTEND_MERGE_PASSTHRU\0"
486 "AArch64ISD::FP_ROUND_MERGE_PASSTHRU\0"
487 "AArch64ISD::FRECPE\0"
488 "AArch64ISD::FRECPS\0"
489 "AArch64ISD::FRECPX_MERGE_PASSTHRU\0"
490 "AArch64ISD::FRINT32_MERGE_PASSTHRU\0"
491 "AArch64ISD::FRINT64_MERGE_PASSTHRU\0"
492 "AArch64ISD::FRINT_MERGE_PASSTHRU\0"
493 "AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU\0"
494 "AArch64ISD::FROUND_MERGE_PASSTHRU\0"
495 "AArch64ISD::FRSQRTE\0"
496 "AArch64ISD::FRSQRTS\0"
497 "AArch64ISD::FSQRT_MERGE_PASSTHRU\0"
498 "AArch64ISD::FSUB_PRED\0"
499 "AArch64ISD::FTRUNC32_MERGE_PASSTHRU\0"
500 "AArch64ISD::FTRUNC64_MERGE_PASSTHRU\0"
501 "AArch64ISD::FTRUNC_MERGE_PASSTHRU\0"
502 "AArch64ISD::GET_SME_SAVE_SIZE\0"
503 "AArch64ISD::GLD1Q_INDEX_MERGE_ZERO\0"
504 "AArch64ISD::GLD1Q_MERGE_ZERO\0"
505 "AArch64ISD::GLD1S_IMM_MERGE_ZERO\0"
506 "AArch64ISD::GLD1S_MERGE_ZERO\0"
507 "AArch64ISD::GLD1S_SCALED_MERGE_ZERO\0"
508 "AArch64ISD::GLD1S_SXTW_MERGE_ZERO\0"
509 "AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO\0"
510 "AArch64ISD::GLD1S_UXTW_MERGE_ZERO\0"
511 "AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO\0"
512 "AArch64ISD::GLD1_IMM_MERGE_ZERO\0"
513 "AArch64ISD::GLD1_MERGE_ZERO\0"
514 "AArch64ISD::GLD1_SCALED_MERGE_ZERO\0"
515 "AArch64ISD::GLD1_SXTW_MERGE_ZERO\0"
516 "AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO\0"
517 "AArch64ISD::GLD1_UXTW_MERGE_ZERO\0"
518 "AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO\0"
519 "AArch64ISD::GLDFF1S_IMM_MERGE_ZERO\0"
520 "AArch64ISD::GLDFF1S_MERGE_ZERO\0"
521 "AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO\0"
522 "AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO\0"
523 "AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO\0"
524 "AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO\0"
525 "AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO\0"
526 "AArch64ISD::GLDFF1_IMM_MERGE_ZERO\0"
527 "AArch64ISD::GLDFF1_MERGE_ZERO\0"
528 "AArch64ISD::GLDFF1_SCALED_MERGE_ZERO\0"
529 "AArch64ISD::GLDFF1_SXTW_MERGE_ZERO\0"
530 "AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO\0"
531 "AArch64ISD::GLDFF1_UXTW_MERGE_ZERO\0"
532 "AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO\0"
533 "AArch64ISD::GLDNT1S_MERGE_ZERO\0"
534 "AArch64ISD::GLDNT1_INDEX_MERGE_ZERO\0"
535 "AArch64ISD::GLDNT1_MERGE_ZERO\0"
536 "AArch64ISD::HADDS_PRED\0"
537 "AArch64ISD::HADDU_PRED\0"
538 "AArch64ISD::INIT_TPIDR2OBJ\0"
539 "AArch64ISD::INOUT_ZA_USE\0"
540 "AArch64ISD::INSR\0"
541 "AArch64ISD::LASTA\0"
542 "AArch64ISD::LASTB\0"
543 "AArch64ISD::LD1DUPpost\0"
544 "AArch64ISD::LD1LANEpost\0"
545 "AArch64ISD::LD1RO_MERGE_ZERO\0"
546 "AArch64ISD::LD1RQ_MERGE_ZERO\0"
547 "AArch64ISD::LD1S_MERGE_ZERO\0"
548 "AArch64ISD::LD1_MERGE_ZERO\0"
549 "AArch64ISD::LD1x2post\0"
550 "AArch64ISD::LD1x3post\0"
551 "AArch64ISD::LD1x4post\0"
552 "AArch64ISD::LD2DUPpost\0"
553 "AArch64ISD::LD2LANEpost\0"
554 "AArch64ISD::LD2post\0"
555 "AArch64ISD::LD3DUPpost\0"
556 "AArch64ISD::LD3LANEpost\0"
557 "AArch64ISD::LD3post\0"
558 "AArch64ISD::LD4DUPpost\0"
559 "AArch64ISD::LD4LANEpost\0"
560 "AArch64ISD::LD4post\0"
561 "AArch64ISD::LDFF1S_MERGE_ZERO\0"
562 "AArch64ISD::LDFF1_MERGE_ZERO\0"
563 "AArch64ISD::LDIAPP\0"
564 "AArch64ISD::LDNF1S_MERGE_ZERO\0"
565 "AArch64ISD::LDNF1_MERGE_ZERO\0"
566 "AArch64ISD::LDNP\0"
567 "AArch64ISD::LDP\0"
568 "AArch64ISD::LOADgot\0"
569 "AArch64ISD::LS64_BUILD\0"
570 "AArch64ISD::LS64_EXTRACT\0"
571 "AArch64ISD::MOVI\0"
572 "AArch64ISD::MOVIedit\0"
573 "AArch64ISD::MOVImsl\0"
574 "AArch64ISD::MOVIshift\0"
575 "AArch64ISD::MRRS\0"
576 "AArch64ISD::MRS\0"
577 "AArch64ISD::MSRR\0"
578 "AArch64ISD::MULHS_PRED\0"
579 "AArch64ISD::MULHU_PRED\0"
580 "AArch64ISD::MUL_PRED\0"
581 "AArch64ISD::MVNImsl\0"
582 "AArch64ISD::MVNIshift\0"
583 "AArch64ISD::NEG_MERGE_PASSTHRU\0"
584 "AArch64ISD::NVCAST\0"
585 "AArch64ISD::ORRi\0"
586 "AArch64ISD::ORV_PRED\0"
587 "AArch64ISD::PMULL\0"
588 "AArch64ISD::PREFETCH\0"
589 "AArch64ISD::PROBED_ALLOCA\0"
590 "AArch64ISD::PTEST\0"
591 "AArch64ISD::PTEST_ANY\0"
592 "AArch64ISD::PTEST_FIRST\0"
593 "AArch64ISD::PTRUE\0"
594 "AArch64ISD::RANGE_PREFETCH\0"
595 "AArch64ISD::RDSVL\0"
596 "AArch64ISD::REINTERPRET_CAST\0"
597 "AArch64ISD::REQUIRES_ZA_SAVE\0"
598 "AArch64ISD::REQUIRES_ZT0_SAVE\0"
599 "AArch64ISD::RESTORE_ZA\0"
600 "AArch64ISD::RESTORE_ZT\0"
601 "AArch64ISD::RET_GLUE\0"
602 "AArch64ISD::REV16\0"
603 "AArch64ISD::REV32\0"
604 "AArch64ISD::REV64\0"
605 "AArch64ISD::REVD_MERGE_PASSTHRU\0"
606 "AArch64ISD::REVH_MERGE_PASSTHRU\0"
607 "AArch64ISD::REVW_MERGE_PASSTHRU\0"
608 "AArch64ISD::RHADDS_PRED\0"
609 "AArch64ISD::RHADDU_PRED\0"
610 "AArch64ISD::RSHRNB_I\0"
611 "AArch64ISD::SADDLP\0"
612 "AArch64ISD::SADDLV\0"
613 "AArch64ISD::SADDV\0"
614 "AArch64ISD::SADDV_PRED\0"
615 "AArch64ISD::SADDWB\0"
616 "AArch64ISD::SADDWT\0"
617 "AArch64ISD::SAVE_ZT\0"
618 "AArch64ISD::SBC\0"
619 "AArch64ISD::SBCS\0"
620 "AArch64ISD::SDIV_PRED\0"
621 "AArch64ISD::SDOT\0"
622 "AArch64ISD::SETCC_MERGE_ZERO\0"
623 "AArch64ISD::SHL_PRED\0"
624 "AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU\0"
625 "AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU\0"
626 "AArch64ISD::SITOF\0"
627 "AArch64ISD::SMAXV\0"
628 "AArch64ISD::SMAXV_PRED\0"
629 "AArch64ISD::SMAX_PRED\0"
630 "AArch64ISD::SME_STATE_ALLOC\0"
631 "AArch64ISD::SME_ZA_LDR\0"
632 "AArch64ISD::SME_ZA_STR\0"
633 "AArch64ISD::SMINV\0"
634 "AArch64ISD::SMINV_PRED\0"
635 "AArch64ISD::SMIN_PRED\0"
636 "AArch64ISD::SMSTART\0"
637 "AArch64ISD::SMSTOP\0"
638 "AArch64ISD::SMULL\0"
639 "AArch64ISD::SPLICE\0"
640 "AArch64ISD::SQADD\0"
641 "AArch64ISD::SQDMULH\0"
642 "AArch64ISD::SQDMULL\0"
643 "AArch64ISD::SQRDMLAH\0"
644 "AArch64ISD::SQRDMLSH\0"
645 "AArch64ISD::SQRDMULH\0"
646 "AArch64ISD::SQRSHL\0"
647 "AArch64ISD::SQRSHRN\0"
648 "AArch64ISD::SQRSHRUN\0"
649 "AArch64ISD::SQSHL\0"
650 "AArch64ISD::SQSHLU_I\0"
651 "AArch64ISD::SQSHL_I\0"
652 "AArch64ISD::SQSHRN\0"
653 "AArch64ISD::SQSHRUN\0"
654 "AArch64ISD::SQSUB\0"
655 "AArch64ISD::SRA_PRED\0"
656 "AArch64ISD::SRL_PRED\0"
657 "AArch64ISD::SRSHR_I\0"
658 "AArch64ISD::SST1Q_INDEX_PRED\0"
659 "AArch64ISD::SST1Q_PRED\0"
660 "AArch64ISD::SST1_IMM_PRED\0"
661 "AArch64ISD::SST1_PRED\0"
662 "AArch64ISD::SST1_SCALED_PRED\0"
663 "AArch64ISD::SST1_SXTW_PRED\0"
664 "AArch64ISD::SST1_SXTW_SCALED_PRED\0"
665 "AArch64ISD::SST1_UXTW_PRED\0"
666 "AArch64ISD::SST1_UXTW_SCALED_PRED\0"
667 "AArch64ISD::SSTNT1_INDEX_PRED\0"
668 "AArch64ISD::SSTNT1_PRED\0"
669 "AArch64ISD::ST1_PRED\0"
670 "AArch64ISD::ST1x2post\0"
671 "AArch64ISD::ST1x3post\0"
672 "AArch64ISD::ST1x4post\0"
673 "AArch64ISD::ST2G\0"
674 "AArch64ISD::ST2LANEpost\0"
675 "AArch64ISD::ST2post\0"
676 "AArch64ISD::ST3LANEpost\0"
677 "AArch64ISD::ST3post\0"
678 "AArch64ISD::ST4LANEpost\0"
679 "AArch64ISD::ST4post\0"
680 "AArch64ISD::STG\0"
681 "AArch64ISD::STILP\0"
682 "AArch64ISD::STNP\0"
683 "AArch64ISD::STP\0"
684 "AArch64ISD::STRICT_FCMP\0"
685 "AArch64ISD::STRICT_FCMPE\0"
686 "AArch64ISD::STZ2G\0"
687 "AArch64ISD::STZG\0"
688 "AArch64ISD::SUBS\0"
689 "AArch64ISD::SUNPKHI\0"
690 "AArch64ISD::SUNPKLO\0"
691 "AArch64ISD::TBL\0"
692 "AArch64ISD::TBNZ\0"
693 "AArch64ISD::TBZ\0"
694 "AArch64ISD::TC_RETURN\0"
695 "AArch64ISD::THREAD_POINTER\0"
696 "AArch64ISD::TLSDESC_AUTH_CALLSEQ\0"
697 "AArch64ISD::TLSDESC_CALLSEQ\0"
698 "AArch64ISD::TRN1\0"
699 "AArch64ISD::TRN2\0"
700 "AArch64ISD::UADDLP\0"
701 "AArch64ISD::UADDLV\0"
702 "AArch64ISD::UADDV\0"
703 "AArch64ISD::UADDV_PRED\0"
704 "AArch64ISD::UADDWB\0"
705 "AArch64ISD::UADDWT\0"
706 "AArch64ISD::UDIV_PRED\0"
707 "AArch64ISD::UDOT\0"
708 "AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU\0"
709 "AArch64ISD::UITOF\0"
710 "AArch64ISD::UMAXV\0"
711 "AArch64ISD::UMAXV_PRED\0"
712 "AArch64ISD::UMAX_PRED\0"
713 "AArch64ISD::UMINV\0"
714 "AArch64ISD::UMINV_PRED\0"
715 "AArch64ISD::UMIN_PRED\0"
716 "AArch64ISD::UMULL\0"
717 "AArch64ISD::UQADD\0"
718 "AArch64ISD::UQRSHL\0"
719 "AArch64ISD::UQRSHRN\0"
720 "AArch64ISD::UQSHL\0"
721 "AArch64ISD::UQSHL_I\0"
722 "AArch64ISD::UQSHRN\0"
723 "AArch64ISD::UQSUB\0"
724 "AArch64ISD::URSHR_I\0"
725 "AArch64ISD::URSHR_I_PRED\0"
726 "AArch64ISD::USDOT\0"
727 "AArch64ISD::UUNPKHI\0"
728 "AArch64ISD::UUNPKLO\0"
729 "AArch64ISD::UZP1\0"
730 "AArch64ISD::UZP2\0"
731 "AArch64ISD::VASHR\0"
732 "AArch64ISD::VLSHR\0"
733 "AArch64ISD::VSHL\0"
734 "AArch64ISD::VSLI\0"
735 "AArch64ISD::VSRI\0"
736 "AArch64ISD::WrapperLarge\0"
737 "AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU\0"
738 "AArch64ISD::ZIP1\0"
739 "AArch64ISD::ZIP2\0"
740 ;
741#ifdef __GNUC__
742#pragma GCC diagnostic pop
743#endif
744
745static constexpr llvm::StringTable
746AArch64SDNodeNames = AArch64SDNodeNamesStorage;
747
748static const VTByHwModePair AArch64VTByHwModeTable[] = {
749 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
750};
751
752static const SDTypeConstraint AArch64SDTypeConstraints[] = {
753 /* 0 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::Other},
754 /* 3 */ {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
755 /* 6 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
756 /* 12 */ {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
757 /* 16 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
758 /* 22 */ {SDTCisSameAs, 2, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
759 /* 25 */ {SDTCisSameAs, 2, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
760 /* 28 */ {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i64},
761 /* 31 */ {SDTCisSameAs, 1, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i64},
762 /* 36 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i64},
763 /* 39 */ {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i64},
764 /* 41 */ {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::v2i64},
765 /* 44 */ {SDTCisVT, 3, 0, 0, MVT::i64}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
766 /* 48 */ {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
767 /* 54 */ {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
768 /* 56 */ {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i64}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
769 /* 60 */ {SDTCisVT, 1, 0, 0, MVT::Other}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
770 /* 62 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
771 /* 65 */ {SDTCisSameAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
772 /* 68 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
773 /* 71 */ {SDTCisOpSmallerThanOp, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
774 /* 74 */ {SDTCisVT, 2, 0, 0, MVT::Other}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
775 /* 77 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
776 /* 80 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
777 /* 83 */ {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
778 /* 85 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
779 /* 89 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
780 /* 93 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
781 /* 98 */ {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
782 /* 102 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
783 /* 106 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
784 /* 110 */ {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
785 /* 114 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
786 /* 119 */ {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
787 /* 121 */ {SDTCisSameNumEltsAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 2, 0, 0, MVT::i1}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
788 /* 126 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
789 /* 129 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
790 /* 134 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
791 /* 141 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
792 /* 146 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVTSmallerThanOp, 3, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
793 /* 155 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
794 /* 161 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
795 /* 168 */ {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
796 /* 174 */ {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCVecEltisVT, 0, 0, 0, MVT::i1}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
797 /* 182 */ {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
798 /* 189 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
799 /* 199 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
800 /* 204 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
801 /* 206 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
802 /* 210 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
803 /* 212 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
804 /* 214 */ {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
805 /* 218 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
806 /* 221 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
807 /* 225 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
808 /* 229 */ {SDTCisPtrTy, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
809 /* 232 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
810 /* 234 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
811 /* 239 */ {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64},
812 /* 241 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
813 /* 243 */ {SDTCisSameNumEltsAs, 1, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
814 /* 247 */ {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
815 /* 249 */ {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
816};
817
818static const SDNodeDesc AArch64SDNodeDescs[] = {
819 {1, 3, 0, 0, 0, 1, 199, 5}, // ABDS_PRED
820 {1, 3, 0, 0, 0, 23, 199, 5}, // ABDU_PRED
821 {1, 3, 0, 0, 0, 45, 199, 5}, // ABS_MERGE_PASSTHRU
822 {1, 3, 0, 0, 0, 76, 214, 4}, // ADC
823 {2, 3, 0, 0, 0, 92, 234, 5}, // ADCS
824 {1, 2, 0, 0, 0, 109, 99, 3}, // ADDP
825 {2, 2, 0, 0, 0, 126, 235, 4}, // ADDS
826 {1, 2, 0, 0, 0, 143, 215, 3}, // ADDlow
827 {1, 1, 0, 0, 0, 162, 210, 2}, // ADR
828 {1, 1, 0, 0, 0, 178, 210, 2}, // ADRP
829 {1, 1, 0|1<<SDNPHasChain, 0, 0, 195, 66, 2}, // ALLOCATE_ZA_BUFFER
830 {1, 1, 0|1<<SDNPHasChain, 0, 0, 226, 66, 2}, // ALLOC_SME_SAVE_BUFFER
831 {2, 2, 0, 0, 0, 260, 235, 4}, // ANDS
832 {1, 2, 0, 0, 0, 277, 247, 2}, // ANDV_PRED
833 {1, 3, 0, 0, 0, 299, 155, 6}, // ASRD_MERGE_OP1
834 {1, 1, 0, 0, 0, 326, 65, 3}, // ASSERT_ZEXT_BOOL
835 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 355, 44, 4}, // AUTH_CALL
836 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 377, 48, 6}, // AUTH_CALL_RVMARKER
837 {0, 5, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 408, 56, 4}, // AUTH_TC_RETURN
838 {1, 2, 0, 0, 0, 435, 141, 5}, // BIC
839 {1, 3, 0, 0, 0, 451, 106, 4}, // BICi
840 {1, 3, 0, 0, 0, 468, 199, 5}, // BITREVERSE_MERGE_PASSTHRU
841 {0, 3, 0|1<<SDNPHasChain, 0, 0, 506, 0, 3}, // BRCOND
842 {1, 3, 0, 0, 0, 525, 98, 4}, // BSP
843 {1, 3, 0, 0, 0, 541, 199, 5}, // BSWAP_MERGE_PASSTHRU
844 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 574, 47, 1}, // CALL
845 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 591, 47, 1}, // CALL_ARM64EC_TO_X64
846 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 623, 47, 1}, // CALL_BTI
847 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 644, 47, 1}, // CALL_RVMARKER
848 {0, 4, 0|1<<SDNPHasChain, 0, 0, 670, 12, 4}, // CB
849 {0, 2, 0|1<<SDNPHasChain, 0, 0, 685, 60, 2}, // CBNZ
850 {0, 2, 0|1<<SDNPHasChain, 0, 0, 702, 60, 2}, // CBZ
851 {1, 5, 0, 0, 0, 718, 6, 6}, // CCMN
852 {1, 5, 0, 0, 0, 735, 6, 6}, // CCMP
853 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 752, 0, 0}, // CHECK_MATCHING_VL
854 {1, 3, 0, 0, 0, 782, 243, 4}, // CLASTA_N
855 {1, 3, 0, 0, 0, 803, 243, 4}, // CLASTB_N
856 {1, 1, 0|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 824, 0, 0}, // COALESCER_BARRIER
857 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 854, 77, 3}, // COND_SMSTART
858 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 879, 77, 3}, // COND_SMSTOP
859 {1, 4, 0, 0, 0, 903, 225, 4}, // CSEL
860 {1, 4, 0, 0, 0, 920, 225, 4}, // CSINC
861 {1, 4, 0, 0, 0, 938, 225, 4}, // CSINV
862 {1, 4, 0, 0, 0, 956, 225, 4}, // CSNEG
863 {1, 3, 0, 0, 0, 974, 199, 5}, // CTLZ_MERGE_PASSTHRU
864 {1, 3, 0, 0, 0, 1006, 199, 5}, // CTPOP_MERGE_PASSTHRU
865 {1, 2, 0, 0, 0, 1039, 80, 3}, // CTTZ_ELTS
866 {1, 1, 0, 0, 0, 1061, 101, 1}, // DUP
867 {1, 2, 0, 0, 0, 1077, 204, 2}, // DUPLANE128
868 {1, 2, 0, 0, 0, 1100, 204, 2}, // DUPLANE16
869 {1, 2, 0, 0, 0, 1122, 204, 2}, // DUPLANE32
870 {1, 2, 0, 0, 0, 1144, 204, 2}, // DUPLANE64
871 {1, 2, 0, 0, 0, 1166, 204, 2}, // DUPLANE8
872 {1, 3, 0, 0, 0, 1187, 114, 5}, // DUP_MERGE_PASSTHRU
873 {1, 0, 0|1<<SDNPHasChain, 0, 0, 1218, 61, 1}, // ENTRY_PSTATE_SM
874 {1, 2, 0, 0, 0, 1246, 247, 2}, // EORV_PRED
875 {1, 3, 0, 0, 0, 1268, 102, 4}, // EXT
876 {1, 3, 0, 0, 0, 1284, 229, 3}, // EXTR
877 {1, 3, 0, 0, 0, 1301, 199, 5}, // FABS_MERGE_PASSTHRU
878 {1, 3, 0, 0, 0, 1333, 243, 4}, // FADDA_PRED
879 {1, 2, 0, 0, 0, 1356, 247, 2}, // FADDV_PRED
880 {1, 3, 0, 0, 0, 1379, 199, 5}, // FADD_PRED
881 {1, 5, 0, 0, 0, 1401, 16, 6}, // FCCMP
882 {1, 3, 0, 0, 0, 1419, 199, 5}, // FCEIL_MERGE_PASSTHRU
883 {1, 2, 0, 0, 0, 1452, 251, 1}, // FCMEQ
884 {1, 2, 0, 0, 0, 1470, 251, 1}, // FCMGE
885 {1, 2, 0, 0, 0, 1488, 251, 1}, // FCMGT
886 {1, 2, 0, 0, 0, 1506, 22, 3}, // FCMP
887 {1, 1, 0, 0, 0, 1523, 89, 4}, // FCVTAS_HALF
888 {1, 1, 0, 0, 0, 1547, 89, 4}, // FCVTAU_HALF
889 {1, 1, 0, 0, 0, 1571, 89, 4}, // FCVTMS_HALF
890 {1, 1, 0, 0, 0, 1595, 89, 4}, // FCVTMU_HALF
891 {1, 1, 0, 0, 0, 1619, 89, 4}, // FCVTNS_HALF
892 {1, 1, 0, 0, 0, 1643, 89, 4}, // FCVTNU_HALF
893 {1, 1, 0, 0, 0, 1667, 89, 4}, // FCVTPS_HALF
894 {1, 1, 0, 0, 0, 1691, 89, 4}, // FCVTPU_HALF
895 {1, 1, 0, 0, 0, 1715, 85, 4}, // FCVTXN
896 {1, 3, 0, 0, 0, 1734, 182, 7}, // FCVTX_MERGE_PASSTHRU
897 {1, 1, 0, 0, 0, 1767, 89, 4}, // FCVTZS_HALF
898 {1, 3, 0, 0, 0, 1791, 182, 7}, // FCVTZS_MERGE_PASSTHRU
899 {1, 1, 0, 0, 0, 1825, 89, 4}, // FCVTZU_HALF
900 {1, 3, 0, 0, 0, 1849, 182, 7}, // FCVTZU_MERGE_PASSTHRU
901 {1, 3, 0, 0, 0, 1883, 199, 5}, // FDIV_PRED
902 {1, 3, 0, 0, 0, 1905, 199, 5}, // FFLOOR_MERGE_PASSTHRU
903 {1, 2, 0, 0, 0, 1939, 247, 2}, // FMAXNMV_PRED
904 {1, 3, 0, 0, 0, 1964, 199, 5}, // FMAXNM_PRED
905 {1, 2, 0, 0, 0, 1988, 247, 2}, // FMAXV_PRED
906 {1, 3, 0, 0, 0, 2011, 199, 5}, // FMAX_PRED
907 {1, 4, 0, 0, 0, 2033, 189, 10}, // FMA_PRED
908 {1, 2, 0, 0, 0, 2054, 247, 2}, // FMINNMV_PRED
909 {1, 3, 0, 0, 0, 2079, 199, 5}, // FMINNM_PRED
910 {1, 2, 0, 0, 0, 2103, 247, 2}, // FMINV_PRED
911 {1, 3, 0, 0, 0, 2126, 199, 5}, // FMIN_PRED
912 {1, 1, 0, 0, 0, 2148, 242, 1}, // FMOV
913 {1, 3, 0, 0, 0, 2165, 199, 5}, // FMUL_PRED
914 {1, 3, 0, 0, 0, 2187, 199, 5}, // FNEARBYINT_MERGE_PASSTHRU
915 {1, 3, 0, 0, 0, 2225, 199, 5}, // FNEG_MERGE_PASSTHRU
916 {1, 3, 0, 0, 0, 2257, 182, 7}, // FP_EXTEND_MERGE_PASSTHRU
917 {1, 4, 0, 0, 0, 2294, 168, 6}, // FP_ROUND_MERGE_PASSTHRU
918 {1, 1, 0, 0, 0, 2330, 212, 2}, // FRECPE
919 {1, 2, 0, 0, 0, 2349, 218, 3}, // FRECPS
920 {1, 3, 0, 0, 0, 2368, 199, 5}, // FRECPX_MERGE_PASSTHRU
921 {1, 3, 0, 0, 0, 2402, 199, 5}, // FRINT32_MERGE_PASSTHRU
922 {1, 3, 0, 0, 0, 2437, 199, 5}, // FRINT64_MERGE_PASSTHRU
923 {1, 3, 0, 0, 0, 2472, 199, 5}, // FRINT_MERGE_PASSTHRU
924 {1, 3, 0, 0, 0, 2505, 199, 5}, // FROUNDEVEN_MERGE_PASSTHRU
925 {1, 3, 0, 0, 0, 2543, 199, 5}, // FROUND_MERGE_PASSTHRU
926 {1, 1, 0, 0, 0, 2577, 212, 2}, // FRSQRTE
927 {1, 2, 0, 0, 0, 2597, 218, 3}, // FRSQRTS
928 {1, 3, 0, 0, 0, 2617, 199, 5}, // FSQRT_MERGE_PASSTHRU
929 {1, 3, 0, 0, 0, 2650, 199, 5}, // FSUB_PRED
930 {1, 3, 0, 0, 0, 2672, 199, 5}, // FTRUNC32_MERGE_PASSTHRU
931 {1, 3, 0, 0, 0, 2708, 199, 5}, // FTRUNC64_MERGE_PASSTHRU
932 {1, 3, 0, 0, 0, 2744, 199, 5}, // FTRUNC_MERGE_PASSTHRU
933 {1, 0, 0|1<<SDNPHasChain, 0, 0, 2778, 61, 1}, // GET_SME_SAVE_SIZE
934 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2808, 0, 0}, // GLD1Q_INDEX_MERGE_ZERO
935 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2843, 161, 7}, // GLD1Q_MERGE_ZERO
936 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2872, 161, 7}, // GLD1S_IMM_MERGE_ZERO
937 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2905, 134, 7}, // GLD1S_MERGE_ZERO
938 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2934, 134, 7}, // GLD1S_SCALED_MERGE_ZERO
939 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2970, 134, 7}, // GLD1S_SXTW_MERGE_ZERO
940 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3004, 134, 7}, // GLD1S_SXTW_SCALED_MERGE_ZERO
941 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3045, 134, 7}, // GLD1S_UXTW_MERGE_ZERO
942 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3079, 134, 7}, // GLD1S_UXTW_SCALED_MERGE_ZERO
943 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3120, 161, 7}, // GLD1_IMM_MERGE_ZERO
944 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3152, 134, 7}, // GLD1_MERGE_ZERO
945 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3180, 134, 7}, // GLD1_SCALED_MERGE_ZERO
946 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3215, 134, 7}, // GLD1_SXTW_MERGE_ZERO
947 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3248, 134, 7}, // GLD1_SXTW_SCALED_MERGE_ZERO
948 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3288, 134, 7}, // GLD1_UXTW_MERGE_ZERO
949 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3321, 134, 7}, // GLD1_UXTW_SCALED_MERGE_ZERO
950 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3361, 161, 7}, // GLDFF1S_IMM_MERGE_ZERO
951 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3396, 134, 7}, // GLDFF1S_MERGE_ZERO
952 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3427, 134, 7}, // GLDFF1S_SCALED_MERGE_ZERO
953 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3465, 134, 7}, // GLDFF1S_SXTW_MERGE_ZERO
954 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3501, 134, 7}, // GLDFF1S_SXTW_SCALED_MERGE_ZERO
955 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3544, 134, 7}, // GLDFF1S_UXTW_MERGE_ZERO
956 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3580, 134, 7}, // GLDFF1S_UXTW_SCALED_MERGE_ZERO
957 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3623, 161, 7}, // GLDFF1_IMM_MERGE_ZERO
958 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3657, 134, 7}, // GLDFF1_MERGE_ZERO
959 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3687, 134, 7}, // GLDFF1_SCALED_MERGE_ZERO
960 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3724, 134, 7}, // GLDFF1_SXTW_MERGE_ZERO
961 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3759, 134, 7}, // GLDFF1_SXTW_SCALED_MERGE_ZERO
962 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3801, 134, 7}, // GLDFF1_UXTW_MERGE_ZERO
963 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3836, 134, 7}, // GLDFF1_UXTW_SCALED_MERGE_ZERO
964 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3878, 161, 7}, // GLDNT1S_MERGE_ZERO
965 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3909, 0, 0}, // GLDNT1_INDEX_MERGE_ZERO
966 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3945, 161, 7}, // GLDNT1_MERGE_ZERO
967 {1, 3, 0, 0, 0, 3975, 199, 5}, // HADDS_PRED
968 {1, 3, 0, 0, 0, 3998, 199, 5}, // HADDU_PRED
969 {0, 2, 0|1<<SDNPHasChain, 0, 0, 4021, 66, 2}, // INIT_TPIDR2OBJ
970 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 4048, 0, 0}, // INOUT_ZA_USE
971 {1, 2, 0, 0, 0, 4073, 101, 1}, // INSR
972 {1, 2, 0, 0, 0, 4090, 247, 2}, // LASTA
973 {1, 2, 0, 0, 0, 4108, 247, 2}, // LASTB
974 {2, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4126, 0, 0}, // LD1DUPpost
975 {2, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4149, 0, 0}, // LD1LANEpost
976 {1, 2, 0|1<<SDNPHasChain, 0, 0, 4173, 129, 5}, // LD1RO_MERGE_ZERO
977 {1, 2, 0|1<<SDNPHasChain, 0, 0, 4202, 129, 5}, // LD1RQ_MERGE_ZERO
978 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4231, 129, 5}, // LD1S_MERGE_ZERO
979 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4259, 129, 5}, // LD1_MERGE_ZERO
980 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4286, 0, 0}, // LD1x2post
981 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4308, 0, 0}, // LD1x3post
982 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4330, 0, 0}, // LD1x4post
983 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4352, 0, 0}, // LD2DUPpost
984 {3, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4375, 0, 0}, // LD2LANEpost
985 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4399, 0, 0}, // LD2post
986 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4419, 0, 0}, // LD3DUPpost
987 {4, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4442, 0, 0}, // LD3LANEpost
988 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4466, 0, 0}, // LD3post
989 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4486, 0, 0}, // LD4DUPpost
990 {5, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4509, 0, 0}, // LD4LANEpost
991 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4533, 0, 0}, // LD4post
992 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4553, 129, 5}, // LDFF1S_MERGE_ZERO
993 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4583, 129, 5}, // LDFF1_MERGE_ZERO
994 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4612, 28, 3}, // LDIAPP
995 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4631, 129, 5}, // LDNF1S_MERGE_ZERO
996 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4661, 129, 5}, // LDNF1_MERGE_ZERO
997 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4690, 41, 3}, // LDNP
998 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4707, 28, 3}, // LDP
999 {1, 1, 0, 0, 0, 4723, 210, 2}, // LOADgot
1000 {1, 8, 0, 0, 0, 4743, 0, 0}, // LS64_BUILD
1001 {1, 2, 0, 0, 0, 4766, 0, 0}, // LS64_EXTRACT
1002 {1, 1, 0, 0, 0, 4791, 242, 1}, // MOVI
1003 {1, 1, 0, 0, 0, 4808, 242, 1}, // MOVIedit
1004 {1, 2, 0, 0, 0, 4829, 241, 2}, // MOVImsl
1005 {1, 2, 0, 0, 0, 4849, 241, 2}, // MOVIshift
1006 {2, 1, 0|1<<SDNPHasChain, 0, 0, 4871, 39, 2}, // MRRS
1007 {2, 1, 0|1<<SDNPHasChain, 0, 0, 4888, 36, 3}, // MRS
1008 {0, 3, 0|1<<SDNPHasChain, 0, 0, 4904, 239, 2}, // MSRR
1009 {1, 3, 0, 0, 0, 4921, 199, 5}, // MULHS_PRED
1010 {1, 3, 0, 0, 0, 4944, 199, 5}, // MULHU_PRED
1011 {1, 3, 0, 0, 0, 4967, 199, 5}, // MUL_PRED
1012 {1, 2, 0, 0, 0, 4988, 241, 2}, // MVNImsl
1013 {1, 2, 0, 0, 0, 5008, 241, 2}, // MVNIshift
1014 {1, 3, 0, 0, 0, 5030, 199, 5}, // NEG_MERGE_PASSTHRU
1015 {1, 1, 0, 0, 0, 5061, 0, 0}, // NVCAST
1016 {1, 3, 0, 0, 0, 5080, 106, 4}, // ORRi
1017 {1, 2, 0, 0, 0, 5097, 247, 2}, // ORV_PRED
1018 {1, 2, 0, 0, 0, 5118, 68, 3}, // PMULL
1019 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5136, 4, 2}, // PREFETCH
1020 {0, 1, 0|1<<SDNPHasChain, 0, 0, 5157, 47, 1}, // PROBED_ALLOCA
1021 {1, 2, 0, 0, 0, 5183, 25, 3}, // PTEST
1022 {1, 2, 0, 0, 0, 5201, 25, 3}, // PTEST_ANY
1023 {1, 2, 0, 0, 0, 5223, 25, 3}, // PTEST_FIRST
1024 {1, 1, 0, 0, 0, 5247, 119, 2}, // PTRUE
1025 {0, 3, 0|1<<SDNPHasChain, 0, 0, 5265, 3, 3}, // RANGE_PREFETCH
1026 {1, 1, 0, 0, 0, 5292, 66, 2}, // RDSVL
1027 {1, 1, 0, 0, 0, 5310, 0, 0}, // REINTERPRET_CAST
1028 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 5339, 0, 0}, // REQUIRES_ZA_SAVE
1029 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 5368, 0, 0}, // REQUIRES_ZT0_SAVE
1030 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 5398, 63, 2}, // RESTORE_ZA
1031 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5421, 63, 2}, // RESTORE_ZT
1032 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 5444, 0, 0}, // RET_GLUE
1033 {1, 1, 0, 0, 0, 5465, 211, 1}, // REV16
1034 {1, 1, 0, 0, 0, 5483, 211, 1}, // REV32
1035 {1, 1, 0, 0, 0, 5501, 211, 1}, // REV64
1036 {1, 3, 0, 0, 0, 5519, 199, 5}, // REVD_MERGE_PASSTHRU
1037 {1, 3, 0, 0, 0, 5551, 199, 5}, // REVH_MERGE_PASSTHRU
1038 {1, 3, 0, 0, 0, 5583, 199, 5}, // REVW_MERGE_PASSTHRU
1039 {1, 3, 0, 0, 0, 5615, 199, 5}, // RHADDS_PRED
1040 {1, 3, 0, 0, 0, 5639, 199, 5}, // RHADDU_PRED
1041 {1, 2, 0, 0, 0, 5663, 126, 3}, // RSHRNB_I
1042 {1, 1, 0, 0, 0, 5684, 127, 2}, // SADDLP
1043 {1, 1, 0, 0, 0, 5703, 127, 2}, // SADDLV
1044 {1, 1, 0, 0, 0, 5722, 100, 2}, // SADDV
1045 {1, 2, 0, 0, 0, 5740, 247, 2}, // SADDV_PRED
1046 {1, 2, 0, 0, 0, 5763, 127, 2}, // SADDWB
1047 {1, 2, 0, 0, 0, 5782, 127, 2}, // SADDWT
1048 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5801, 63, 2}, // SAVE_ZT
1049 {1, 3, 0, 0, 0, 5821, 214, 4}, // SBC
1050 {2, 3, 0, 0, 0, 5837, 234, 5}, // SBCS
1051 {1, 3, 0, 0, 0, 5854, 199, 5}, // SDIV_PRED
1052 {1, 3, 0, 0, 0, 5876, 110, 4}, // SDOT
1053 {1, 4, 0, 0, 0, 5893, 174, 8}, // SETCC_MERGE_ZERO
1054 {1, 3, 0, 0, 0, 5922, 199, 5}, // SHL_PRED
1055 {1, 4, 0, 0, 0, 5943, 146, 9}, // SIGN_EXTEND_INREG_MERGE_PASSTHRU
1056 {1, 3, 0, 0, 0, 5988, 182, 7}, // SINT_TO_FP_MERGE_PASSTHRU
1057 {1, 1, 0, 0, 0, 6026, 83, 2}, // SITOF
1058 {1, 1, 0, 0, 0, 6044, 100, 2}, // SMAXV
1059 {1, 2, 0, 0, 0, 6062, 247, 2}, // SMAXV_PRED
1060 {1, 3, 0, 0, 0, 6085, 199, 5}, // SMAX_PRED
1061 {0, 0, 0|1<<SDNPHasChain, 0, 0, 6107, 0, 0}, // SME_STATE_ALLOC
1062 {0, 3, 0|1<<SDNPHasChain, 0, 0, 6135, 62, 3}, // SME_ZA_LDR
1063 {0, 3, 0|1<<SDNPHasChain, 0, 0, 6158, 62, 3}, // SME_ZA_STR
1064 {1, 1, 0, 0, 0, 6181, 100, 2}, // SMINV
1065 {1, 2, 0, 0, 0, 6199, 247, 2}, // SMINV_PRED
1066 {1, 3, 0, 0, 0, 6222, 199, 5}, // SMIN_PRED
1067 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 6244, 61, 1}, // SMSTART
1068 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 6264, 61, 1}, // SMSTOP
1069 {1, 2, 0, 0, 0, 6283, 68, 3}, // SMULL
1070 {1, 3, 0, 0, 0, 6301, 199, 5}, // SPLICE
1071 {1, 2, 0, 0, 0, 6320, 218, 3}, // SQADD
1072 {1, 2, 0, 0, 0, 6338, 251, 1}, // SQDMULH
1073 {1, 2, 0, 0, 0, 6358, 249, 3}, // SQDMULL
1074 {1, 3, 0, 0, 0, 6378, 221, 4}, // SQRDMLAH
1075 {1, 3, 0, 0, 0, 6399, 221, 4}, // SQRDMLSH
1076 {1, 2, 0, 0, 0, 6420, 218, 3}, // SQRDMULH
1077 {1, 2, 0, 0, 0, 6441, 218, 3}, // SQRSHL
1078 {1, 2, 0, 0, 0, 6460, 93, 5}, // SQRSHRN
1079 {1, 2, 0, 0, 0, 6480, 93, 5}, // SQRSHRUN
1080 {1, 2, 0, 0, 0, 6501, 218, 3}, // SQSHL
1081 {1, 2, 0, 0, 0, 6519, 232, 2}, // SQSHLU_I
1082 {1, 2, 0, 0, 0, 6540, 232, 2}, // SQSHL_I
1083 {1, 2, 0, 0, 0, 6560, 93, 5}, // SQSHRN
1084 {1, 2, 0, 0, 0, 6579, 93, 5}, // SQSHRUN
1085 {1, 2, 0, 0, 0, 6599, 218, 3}, // SQSUB
1086 {1, 3, 0, 0, 0, 6617, 199, 5}, // SRA_PRED
1087 {1, 3, 0, 0, 0, 6638, 199, 5}, // SRL_PRED
1088 {1, 2, 0, 0, 0, 6659, 232, 2}, // SRSHR_I
1089 {0, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6679, 0, 0}, // SST1Q_INDEX_PRED
1090 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6708, 161, 7}, // SST1Q_PRED
1091 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6731, 161, 7}, // SST1_IMM_PRED
1092 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6757, 134, 7}, // SST1_PRED
1093 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6779, 134, 7}, // SST1_SCALED_PRED
1094 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6808, 134, 7}, // SST1_SXTW_PRED
1095 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6835, 134, 7}, // SST1_SXTW_SCALED_PRED
1096 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6869, 134, 7}, // SST1_UXTW_PRED
1097 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6896, 134, 7}, // SST1_UXTW_SCALED_PRED
1098 {0, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6930, 0, 0}, // SSTNT1_INDEX_PRED
1099 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6960, 161, 7}, // SSTNT1_PRED
1100 {0, 4, 0|1<<SDNPHasChain, 0, 0, 6984, 121, 5}, // ST1_PRED
1101 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7005, 0, 0}, // ST1x2post
1102 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7027, 0, 0}, // ST1x3post
1103 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7049, 0, 0}, // ST1x4post
1104 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7071, 54, 2}, // ST2G
1105 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7088, 0, 0}, // ST2LANEpost
1106 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7112, 0, 0}, // ST2post
1107 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7132, 0, 0}, // ST3LANEpost
1108 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7156, 0, 0}, // ST3post
1109 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7176, 0, 0}, // ST4LANEpost
1110 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7200, 0, 0}, // ST4post
1111 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7220, 54, 2}, // STG
1112 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7236, 28, 3}, // STILP
1113 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7254, 41, 3}, // STNP
1114 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7271, 28, 3}, // STP
1115 {1, 2, 0|1<<SDNPHasChain, 0|1<<SDNFIsStrictFP, 0, 7287, 22, 3}, // STRICT_FCMP
1116 {1, 2, 0|1<<SDNPHasChain, 0|1<<SDNFIsStrictFP, 0, 7311, 22, 3}, // STRICT_FCMPE
1117 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7336, 54, 2}, // STZ2G
1118 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7354, 54, 2}, // STZG
1119 {2, 2, 0, 0, 0, 7371, 235, 4}, // SUBS
1120 {1, 1, 0, 0, 0, 7388, 71, 3}, // SUNPKHI
1121 {1, 1, 0, 0, 0, 7408, 71, 3}, // SUNPKLO
1122 {1, 2, 0, 0, 0, 7428, 107, 3}, // TBL
1123 {0, 3, 0|1<<SDNPHasChain, 0, 0, 7444, 74, 3}, // TBNZ
1124 {0, 3, 0|1<<SDNPHasChain, 0, 0, 7461, 74, 3}, // TBZ
1125 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 7477, 47, 1}, // TC_RETURN
1126 {1, 0, 0, 0, 0, 7499, 47, 1}, // THREAD_POINTER
1127 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 7526, 47, 1}, // TLSDESC_AUTH_CALLSEQ
1128 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 7559, 47, 1}, // TLSDESC_CALLSEQ
1129 {1, 2, 0, 0, 0, 7587, 99, 3}, // TRN1
1130 {1, 2, 0, 0, 0, 7604, 99, 3}, // TRN2
1131 {1, 1, 0, 0, 0, 7621, 127, 2}, // UADDLP
1132 {1, 1, 0, 0, 0, 7640, 127, 2}, // UADDLV
1133 {1, 1, 0, 0, 0, 7659, 100, 2}, // UADDV
1134 {1, 2, 0, 0, 0, 7677, 247, 2}, // UADDV_PRED
1135 {1, 2, 0, 0, 0, 7700, 127, 2}, // UADDWB
1136 {1, 2, 0, 0, 0, 7719, 127, 2}, // UADDWT
1137 {1, 3, 0, 0, 0, 7738, 199, 5}, // UDIV_PRED
1138 {1, 3, 0, 0, 0, 7760, 110, 4}, // UDOT
1139 {1, 3, 0, 0, 0, 7777, 182, 7}, // UINT_TO_FP_MERGE_PASSTHRU
1140 {1, 1, 0, 0, 0, 7815, 83, 2}, // UITOF
1141 {1, 1, 0, 0, 0, 7833, 100, 2}, // UMAXV
1142 {1, 2, 0, 0, 0, 7851, 247, 2}, // UMAXV_PRED
1143 {1, 3, 0, 0, 0, 7874, 199, 5}, // UMAX_PRED
1144 {1, 1, 0, 0, 0, 7896, 100, 2}, // UMINV
1145 {1, 2, 0, 0, 0, 7914, 247, 2}, // UMINV_PRED
1146 {1, 3, 0, 0, 0, 7937, 199, 5}, // UMIN_PRED
1147 {1, 2, 0, 0, 0, 7959, 68, 3}, // UMULL
1148 {1, 2, 0, 0, 0, 7977, 218, 3}, // UQADD
1149 {1, 2, 0, 0, 0, 7995, 218, 3}, // UQRSHL
1150 {1, 2, 0, 0, 0, 8014, 93, 5}, // UQRSHRN
1151 {1, 2, 0, 0, 0, 8034, 218, 3}, // UQSHL
1152 {1, 2, 0, 0, 0, 8052, 232, 2}, // UQSHL_I
1153 {1, 2, 0, 0, 0, 8072, 93, 5}, // UQSHRN
1154 {1, 2, 0, 0, 0, 8091, 218, 3}, // UQSUB
1155 {1, 2, 0, 0, 0, 8109, 232, 2}, // URSHR_I
1156 {1, 3, 0, 0, 0, 8129, 155, 6}, // URSHR_I_PRED
1157 {1, 3, 0, 0, 0, 8154, 110, 4}, // USDOT
1158 {1, 1, 0, 0, 0, 8172, 71, 3}, // UUNPKHI
1159 {1, 1, 0, 0, 0, 8192, 71, 3}, // UUNPKLO
1160 {1, 2, 0, 0, 0, 8212, 99, 3}, // UZP1
1161 {1, 2, 0, 0, 0, 8229, 99, 3}, // UZP2
1162 {1, 2, 0, 0, 0, 8246, 232, 2}, // VASHR
1163 {1, 2, 0, 0, 0, 8264, 232, 2}, // VLSHR
1164 {1, 2, 0, 0, 0, 8282, 232, 2}, // VSHL
1165 {1, 3, 0, 0, 0, 8299, 206, 4}, // VSLI
1166 {1, 3, 0, 0, 0, 8316, 206, 4}, // VSRI
1167 {1, 4, 0, 0, 0, 8333, 31, 5}, // WrapperLarge
1168 {1, 4, 0, 0, 0, 8358, 146, 9}, // ZERO_EXTEND_INREG_MERGE_PASSTHRU
1169 {1, 2, 0, 0, 0, 8403, 99, 3}, // ZIP1
1170 {1, 2, 0, 0, 0, 8420, 99, 3}, // ZIP2
1171};
1172
1173static const SDNodeInfo AArch64GenSDNodeInfo(
1174 /*NumOpcodes=*/352, AArch64SDNodeDescs, AArch64SDNodeNames,
1175 AArch64VTByHwModeTable, AArch64SDTypeConstraints);
1176
1177} // namespace llvm
1178
1179#endif // GET_SDNODE_DESC
1180
1181