1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: AArch64.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::AArch64ISD {
14
15enum GenNodeType : unsigned {
16 ABDS_PRED = ISD::BUILTIN_OP_END,
17 ABDU_PRED,
18 ABS_MERGE_PASSTHRU,
19 ADC,
20 ADCS,
21 ADDHN,
22 ADDP,
23 ADDS,
24 ADDlow,
25 ADR,
26 ADRP,
27 ANDS,
28 ANDV_PRED,
29 ASRD_MERGE_OP1,
30 ASSERT_ZEXT_BOOL,
31 AUTH_CALL,
32 AUTH_CALL_RVMARKER,
33 AUTH_TC_RETURN,
34 BIC,
35 BICi,
36 BITREVERSE_MERGE_PASSTHRU,
37 BRCOND,
38 BSP,
39 BSWAP_MERGE_PASSTHRU,
40 CALL,
41 CALL_ARM64EC_TO_X64,
42 CALL_BTI,
43 CALL_RVMARKER,
44 CB,
45 CBNZ,
46 CBZ,
47 CCMN,
48 CCMP,
49 CHECK_MATCHING_VL,
50 CLASTA_N,
51 CLASTB_N,
52 CMTST,
53 COALESCER_BARRIER,
54 COND_SMSTART,
55 COND_SMSTOP,
56 CSEL,
57 CSINC,
58 CSINV,
59 CSNEG,
60 CTLZ_MERGE_PASSTHRU,
61 CTPOP_MERGE_PASSTHRU,
62 CTTZ_ELTS,
63 DUP,
64 DUPLANE128,
65 DUPLANE16,
66 DUPLANE32,
67 DUPLANE64,
68 DUPLANE8,
69 DUP_MERGE_PASSTHRU,
70 ENTRY_PSTATE_SM,
71 EORV_PRED,
72 EXT,
73 EXTR,
74 FABS_MERGE_PASSTHRU,
75 FADDA_PRED,
76 FADDV_PRED,
77 FADD_PRED,
78 FCCMP,
79 FCEIL_MERGE_PASSTHRU,
80 FCMEQ,
81 FCMGE,
82 FCMGT,
83 FCMP,
84 FCVTAS_HALF,
85 FCVTAU_HALF,
86 FCVTMS_HALF,
87 FCVTMU_HALF,
88 FCVTNS_HALF,
89 FCVTNU_HALF,
90 FCVTPS_HALF,
91 FCVTPU_HALF,
92 FCVTXN,
93 FCVTX_MERGE_PASSTHRU,
94 FCVTZS_HALF,
95 FCVTZS_MERGE_PASSTHRU,
96 FCVTZU_HALF,
97 FCVTZU_MERGE_PASSTHRU,
98 FDIV_PRED,
99 FFLOOR_MERGE_PASSTHRU,
100 FMAXNMV_PRED,
101 FMAXNM_PRED,
102 FMAXV_PRED,
103 FMAX_PRED,
104 FMA_PRED,
105 FMINNMV_PRED,
106 FMINNM_PRED,
107 FMINV_PRED,
108 FMIN_PRED,
109 FMOV,
110 FMUL_PRED,
111 FNEARBYINT_MERGE_PASSTHRU,
112 FNEG_MERGE_PASSTHRU,
113 FP_EXTEND_MERGE_PASSTHRU,
114 FP_ROUND_MERGE_PASSTHRU,
115 FRECPE,
116 FRECPS,
117 FRECPX_MERGE_PASSTHRU,
118 FRINT32_MERGE_PASSTHRU,
119 FRINT64_MERGE_PASSTHRU,
120 FRINT_MERGE_PASSTHRU,
121 FROUNDEVEN_MERGE_PASSTHRU,
122 FROUND_MERGE_PASSTHRU,
123 FRSQRTE,
124 FRSQRTS,
125 FSQRT_MERGE_PASSTHRU,
126 FSUB_PRED,
127 FTRUNC32_MERGE_PASSTHRU,
128 FTRUNC64_MERGE_PASSTHRU,
129 FTRUNC_MERGE_PASSTHRU,
130 GLD1Q_INDEX_MERGE_ZERO,
131 GLD1Q_MERGE_ZERO,
132 GLD1S_IMM_MERGE_ZERO,
133 GLD1S_MERGE_ZERO,
134 GLD1S_SCALED_MERGE_ZERO,
135 GLD1S_SXTW_MERGE_ZERO,
136 GLD1S_SXTW_SCALED_MERGE_ZERO,
137 GLD1S_UXTW_MERGE_ZERO,
138 GLD1S_UXTW_SCALED_MERGE_ZERO,
139 GLD1_IMM_MERGE_ZERO,
140 GLD1_MERGE_ZERO,
141 GLD1_SCALED_MERGE_ZERO,
142 GLD1_SXTW_MERGE_ZERO,
143 GLD1_SXTW_SCALED_MERGE_ZERO,
144 GLD1_UXTW_MERGE_ZERO,
145 GLD1_UXTW_SCALED_MERGE_ZERO,
146 GLDFF1S_IMM_MERGE_ZERO,
147 GLDFF1S_MERGE_ZERO,
148 GLDFF1S_SCALED_MERGE_ZERO,
149 GLDFF1S_SXTW_MERGE_ZERO,
150 GLDFF1S_SXTW_SCALED_MERGE_ZERO,
151 GLDFF1S_UXTW_MERGE_ZERO,
152 GLDFF1S_UXTW_SCALED_MERGE_ZERO,
153 GLDFF1_IMM_MERGE_ZERO,
154 GLDFF1_MERGE_ZERO,
155 GLDFF1_SCALED_MERGE_ZERO,
156 GLDFF1_SXTW_MERGE_ZERO,
157 GLDFF1_SXTW_SCALED_MERGE_ZERO,
158 GLDFF1_UXTW_MERGE_ZERO,
159 GLDFF1_UXTW_SCALED_MERGE_ZERO,
160 GLDNT1S_MERGE_ZERO,
161 GLDNT1_INDEX_MERGE_ZERO,
162 GLDNT1_MERGE_ZERO,
163 HADDS_PRED,
164 HADDU_PRED,
165 HVC,
166 INOUT_ZA_USE,
167 INSR,
168 LASTA,
169 LASTB,
170 LD1DUPpost,
171 LD1LANEpost,
172 LD1RO_MERGE_ZERO,
173 LD1RQ_MERGE_ZERO,
174 LD1S_MERGE_ZERO,
175 LD1_MERGE_ZERO,
176 LD1x2post,
177 LD1x3post,
178 LD1x4post,
179 LD2DUPpost,
180 LD2LANEpost,
181 LD2post,
182 LD3DUPpost,
183 LD3LANEpost,
184 LD3post,
185 LD4DUPpost,
186 LD4LANEpost,
187 LD4post,
188 LDFF1S_MERGE_ZERO,
189 LDFF1_MERGE_ZERO,
190 LDIAPP,
191 LDNF1S_MERGE_ZERO,
192 LDNF1_MERGE_ZERO,
193 LDNP,
194 LDP,
195 LOADgot,
196 LS64_BUILD,
197 LS64_EXTRACT,
198 MOVI,
199 MOVIedit,
200 MOVImsl,
201 MOVIshift,
202 MRRS,
203 MRS,
204 MSRR,
205 MULHS_PRED,
206 MULHU_PRED,
207 MUL_PRED,
208 MVNImsl,
209 MVNIshift,
210 NEG_MERGE_PASSTHRU,
211 NVCAST,
212 ORRi,
213 ORV_PRED,
214 PMULL,
215 PREFETCH,
216 PROBED_ALLOCA,
217 PTEST,
218 PTEST_ANY,
219 PTEST_FIRST,
220 PTRUE,
221 RANGE_PREFETCH,
222 RDSVL,
223 REINTERPRET_CAST,
224 REQUIRES_ZA_SAVE,
225 REQUIRES_ZT0_SAVE,
226 RESTORE_ZT,
227 RET_GLUE,
228 REV16,
229 REV32,
230 REV64,
231 REVD_MERGE_PASSTHRU,
232 REVH_MERGE_PASSTHRU,
233 REVW_MERGE_PASSTHRU,
234 RHADDS_PRED,
235 RHADDU_PRED,
236 RSHRNB_I,
237 SADDLP,
238 SADDLV,
239 SADDV,
240 SADDV_PRED,
241 SAVE_ZT,
242 SBC,
243 SBCS,
244 SDOT,
245 SETCC_MERGE_ZERO,
246 SHL_PRED,
247 SIGN_EXTEND_INREG_MERGE_PASSTHRU,
248 SINT_TO_FP_MERGE_PASSTHRU,
249 SITOF,
250 SMAXV,
251 SMAXV_PRED,
252 SMAX_PRED,
253 SME_STATE_ALLOC,
254 SME_ZA_LDR,
255 SME_ZA_STR,
256 SMINV,
257 SMINV_PRED,
258 SMIN_PRED,
259 SMSTART,
260 SMSTOP,
261 SMULL,
262 SPLICE,
263 SQABS,
264 SQADD,
265 SQDMULH,
266 SQDMULL,
267 SQNEG,
268 SQRDMLAH,
269 SQRDMLSH,
270 SQRDMULH,
271 SQRSHL,
272 SQRSHRN,
273 SQRSHRUN,
274 SQSHL,
275 SQSHLU_I,
276 SQSHL_I,
277 SQSHRN,
278 SQSHRUN,
279 SQSUB,
280 SRA_PRED,
281 SRL_PRED,
282 SRSHR_I,
283 SST1Q_INDEX_PRED,
284 SST1Q_PRED,
285 SST1_IMM_PRED,
286 SST1_PRED,
287 SST1_SCALED_PRED,
288 SST1_SXTW_PRED,
289 SST1_SXTW_SCALED_PRED,
290 SST1_UXTW_PRED,
291 SST1_UXTW_SCALED_PRED,
292 SSTNT1_INDEX_PRED,
293 SSTNT1_PRED,
294 ST1_PRED,
295 ST1x2post,
296 ST1x3post,
297 ST1x4post,
298 ST2G,
299 ST2LANEpost,
300 ST2post,
301 ST3LANEpost,
302 ST3post,
303 ST4LANEpost,
304 ST4post,
305 STG,
306 STILP,
307 STNP,
308 STP,
309 STRICT_FADD_PRED,
310 STRICT_FCEIL_MERGE_PASSTHRU,
311 STRICT_FCMP,
312 STRICT_FCMPE,
313 STRICT_FDIV_PRED,
314 STRICT_FFLOOR_MERGE_PASSTHRU,
315 STRICT_FMAXNM_PRED,
316 STRICT_FMAX_PRED,
317 STRICT_FMA_PRED,
318 STRICT_FMINNM_PRED,
319 STRICT_FMIN_PRED,
320 STRICT_FMUL_PRED,
321 STRICT_FNEARBYINT_MERGE_PASSTHRU,
322 STRICT_FROUNDEVEN_MERGE_PASSTHRU,
323 STRICT_FROUND_MERGE_PASSTHRU,
324 STRICT_FSQRT_MERGE_PASSTHRU,
325 STRICT_FSUB_PRED,
326 STRICT_FTRUNC_MERGE_PASSTHRU,
327 STZ2G,
328 STZG,
329 SUBS,
330 SUNPKHI,
331 SUNPKLO,
332 SUQADD,
333 SVC,
334 TBL,
335 TBNZ,
336 TBZ,
337 TC_RETURN,
338 THREAD_POINTER,
339 TLSDESC_AUTH_CALLSEQ,
340 TLSDESC_CALLSEQ,
341 TRN1,
342 TRN2,
343 UADDLP,
344 UADDLV,
345 UADDV,
346 UADDV_PRED,
347 UDOT,
348 UINT_TO_FP_MERGE_PASSTHRU,
349 UITOF,
350 UMAXV,
351 UMAXV_PRED,
352 UMAX_PRED,
353 UMINV,
354 UMINV_PRED,
355 UMIN_PRED,
356 UMULL,
357 UQADD,
358 UQRSHL,
359 UQRSHRN,
360 UQSHL,
361 UQSHL_I,
362 UQSHRN,
363 UQSUB,
364 URSHR_I,
365 URSHR_I_PRED,
366 USDOT,
367 USQADD,
368 UUNPKHI,
369 UUNPKLO,
370 UZP1,
371 UZP2,
372 VASHR,
373 VLSHR,
374 VSHL,
375 VSLI,
376 VSRI,
377 WHILEGE_PRED_COUNTER,
378 WHILEGT_PRED_COUNTER,
379 WHILEHI_PRED_COUNTER,
380 WHILEHS_PRED_COUNTER,
381 WHILELE_PRED_COUNTER,
382 WHILELO_PRED_COUNTER,
383 WHILELS_PRED_COUNTER,
384 WHILELT_PRED_COUNTER,
385 WrapperLarge,
386 ZERO_EXTEND_INREG_MERGE_PASSTHRU,
387 ZIP1,
388 ZIP2,
389};
390
391static constexpr unsigned GENERATED_OPCODE_END = ZIP2 + 1;
392
393} // namespace llvm::AArch64ISD
394
395#endif // GET_SDNODE_ENUM
396
397#ifdef GET_SDNODE_DESC
398#undef GET_SDNODE_DESC
399
400namespace llvm {
401
402
403#ifdef __GNUC__
404#pragma GCC diagnostic push
405#pragma GCC diagnostic ignored "-Woverlength-strings"
406#endif
407static constexpr char AArch64SDNodeNamesStorage[] =
408 "\0"
409 "AArch64ISD::ABDS_PRED\0"
410 "AArch64ISD::ABDU_PRED\0"
411 "AArch64ISD::ABS_MERGE_PASSTHRU\0"
412 "AArch64ISD::ADC\0"
413 "AArch64ISD::ADCS\0"
414 "AArch64ISD::ADDHN\0"
415 "AArch64ISD::ADDP\0"
416 "AArch64ISD::ADDS\0"
417 "AArch64ISD::ADDlow\0"
418 "AArch64ISD::ADR\0"
419 "AArch64ISD::ADRP\0"
420 "AArch64ISD::ANDS\0"
421 "AArch64ISD::ANDV_PRED\0"
422 "AArch64ISD::ASRD_MERGE_OP1\0"
423 "AArch64ISD::ASSERT_ZEXT_BOOL\0"
424 "AArch64ISD::AUTH_CALL\0"
425 "AArch64ISD::AUTH_CALL_RVMARKER\0"
426 "AArch64ISD::AUTH_TC_RETURN\0"
427 "AArch64ISD::BIC\0"
428 "AArch64ISD::BICi\0"
429 "AArch64ISD::BITREVERSE_MERGE_PASSTHRU\0"
430 "AArch64ISD::BRCOND\0"
431 "AArch64ISD::BSP\0"
432 "AArch64ISD::BSWAP_MERGE_PASSTHRU\0"
433 "AArch64ISD::CALL\0"
434 "AArch64ISD::CALL_ARM64EC_TO_X64\0"
435 "AArch64ISD::CALL_BTI\0"
436 "AArch64ISD::CALL_RVMARKER\0"
437 "AArch64ISD::CB\0"
438 "AArch64ISD::CBNZ\0"
439 "AArch64ISD::CBZ\0"
440 "AArch64ISD::CCMN\0"
441 "AArch64ISD::CCMP\0"
442 "AArch64ISD::CHECK_MATCHING_VL\0"
443 "AArch64ISD::CLASTA_N\0"
444 "AArch64ISD::CLASTB_N\0"
445 "AArch64ISD::CMTST\0"
446 "AArch64ISD::COALESCER_BARRIER\0"
447 "AArch64ISD::COND_SMSTART\0"
448 "AArch64ISD::COND_SMSTOP\0"
449 "AArch64ISD::CSEL\0"
450 "AArch64ISD::CSINC\0"
451 "AArch64ISD::CSINV\0"
452 "AArch64ISD::CSNEG\0"
453 "AArch64ISD::CTLZ_MERGE_PASSTHRU\0"
454 "AArch64ISD::CTPOP_MERGE_PASSTHRU\0"
455 "AArch64ISD::CTTZ_ELTS\0"
456 "AArch64ISD::DUP\0"
457 "AArch64ISD::DUPLANE128\0"
458 "AArch64ISD::DUPLANE16\0"
459 "AArch64ISD::DUPLANE32\0"
460 "AArch64ISD::DUPLANE64\0"
461 "AArch64ISD::DUPLANE8\0"
462 "AArch64ISD::DUP_MERGE_PASSTHRU\0"
463 "AArch64ISD::ENTRY_PSTATE_SM\0"
464 "AArch64ISD::EORV_PRED\0"
465 "AArch64ISD::EXT\0"
466 "AArch64ISD::EXTR\0"
467 "AArch64ISD::FABS_MERGE_PASSTHRU\0"
468 "AArch64ISD::FADDA_PRED\0"
469 "AArch64ISD::FADDV_PRED\0"
470 "AArch64ISD::FADD_PRED\0"
471 "AArch64ISD::FCCMP\0"
472 "AArch64ISD::FCEIL_MERGE_PASSTHRU\0"
473 "AArch64ISD::FCMEQ\0"
474 "AArch64ISD::FCMGE\0"
475 "AArch64ISD::FCMGT\0"
476 "AArch64ISD::FCMP\0"
477 "AArch64ISD::FCVTAS_HALF\0"
478 "AArch64ISD::FCVTAU_HALF\0"
479 "AArch64ISD::FCVTMS_HALF\0"
480 "AArch64ISD::FCVTMU_HALF\0"
481 "AArch64ISD::FCVTNS_HALF\0"
482 "AArch64ISD::FCVTNU_HALF\0"
483 "AArch64ISD::FCVTPS_HALF\0"
484 "AArch64ISD::FCVTPU_HALF\0"
485 "AArch64ISD::FCVTXN\0"
486 "AArch64ISD::FCVTX_MERGE_PASSTHRU\0"
487 "AArch64ISD::FCVTZS_HALF\0"
488 "AArch64ISD::FCVTZS_MERGE_PASSTHRU\0"
489 "AArch64ISD::FCVTZU_HALF\0"
490 "AArch64ISD::FCVTZU_MERGE_PASSTHRU\0"
491 "AArch64ISD::FDIV_PRED\0"
492 "AArch64ISD::FFLOOR_MERGE_PASSTHRU\0"
493 "AArch64ISD::FMAXNMV_PRED\0"
494 "AArch64ISD::FMAXNM_PRED\0"
495 "AArch64ISD::FMAXV_PRED\0"
496 "AArch64ISD::FMAX_PRED\0"
497 "AArch64ISD::FMA_PRED\0"
498 "AArch64ISD::FMINNMV_PRED\0"
499 "AArch64ISD::FMINNM_PRED\0"
500 "AArch64ISD::FMINV_PRED\0"
501 "AArch64ISD::FMIN_PRED\0"
502 "AArch64ISD::FMOV\0"
503 "AArch64ISD::FMUL_PRED\0"
504 "AArch64ISD::FNEARBYINT_MERGE_PASSTHRU\0"
505 "AArch64ISD::FNEG_MERGE_PASSTHRU\0"
506 "AArch64ISD::FP_EXTEND_MERGE_PASSTHRU\0"
507 "AArch64ISD::FP_ROUND_MERGE_PASSTHRU\0"
508 "AArch64ISD::FRECPE\0"
509 "AArch64ISD::FRECPS\0"
510 "AArch64ISD::FRECPX_MERGE_PASSTHRU\0"
511 "AArch64ISD::FRINT32_MERGE_PASSTHRU\0"
512 "AArch64ISD::FRINT64_MERGE_PASSTHRU\0"
513 "AArch64ISD::FRINT_MERGE_PASSTHRU\0"
514 "AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU\0"
515 "AArch64ISD::FROUND_MERGE_PASSTHRU\0"
516 "AArch64ISD::FRSQRTE\0"
517 "AArch64ISD::FRSQRTS\0"
518 "AArch64ISD::FSQRT_MERGE_PASSTHRU\0"
519 "AArch64ISD::FSUB_PRED\0"
520 "AArch64ISD::FTRUNC32_MERGE_PASSTHRU\0"
521 "AArch64ISD::FTRUNC64_MERGE_PASSTHRU\0"
522 "AArch64ISD::FTRUNC_MERGE_PASSTHRU\0"
523 "AArch64ISD::GLD1Q_INDEX_MERGE_ZERO\0"
524 "AArch64ISD::GLD1Q_MERGE_ZERO\0"
525 "AArch64ISD::GLD1S_IMM_MERGE_ZERO\0"
526 "AArch64ISD::GLD1S_MERGE_ZERO\0"
527 "AArch64ISD::GLD1S_SCALED_MERGE_ZERO\0"
528 "AArch64ISD::GLD1S_SXTW_MERGE_ZERO\0"
529 "AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO\0"
530 "AArch64ISD::GLD1S_UXTW_MERGE_ZERO\0"
531 "AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO\0"
532 "AArch64ISD::GLD1_IMM_MERGE_ZERO\0"
533 "AArch64ISD::GLD1_MERGE_ZERO\0"
534 "AArch64ISD::GLD1_SCALED_MERGE_ZERO\0"
535 "AArch64ISD::GLD1_SXTW_MERGE_ZERO\0"
536 "AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO\0"
537 "AArch64ISD::GLD1_UXTW_MERGE_ZERO\0"
538 "AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO\0"
539 "AArch64ISD::GLDFF1S_IMM_MERGE_ZERO\0"
540 "AArch64ISD::GLDFF1S_MERGE_ZERO\0"
541 "AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO\0"
542 "AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO\0"
543 "AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO\0"
544 "AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO\0"
545 "AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO\0"
546 "AArch64ISD::GLDFF1_IMM_MERGE_ZERO\0"
547 "AArch64ISD::GLDFF1_MERGE_ZERO\0"
548 "AArch64ISD::GLDFF1_SCALED_MERGE_ZERO\0"
549 "AArch64ISD::GLDFF1_SXTW_MERGE_ZERO\0"
550 "AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO\0"
551 "AArch64ISD::GLDFF1_UXTW_MERGE_ZERO\0"
552 "AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO\0"
553 "AArch64ISD::GLDNT1S_MERGE_ZERO\0"
554 "AArch64ISD::GLDNT1_INDEX_MERGE_ZERO\0"
555 "AArch64ISD::GLDNT1_MERGE_ZERO\0"
556 "AArch64ISD::HADDS_PRED\0"
557 "AArch64ISD::HADDU_PRED\0"
558 "AArch64ISD::HVC\0"
559 "AArch64ISD::INOUT_ZA_USE\0"
560 "AArch64ISD::INSR\0"
561 "AArch64ISD::LASTA\0"
562 "AArch64ISD::LASTB\0"
563 "AArch64ISD::LD1DUPpost\0"
564 "AArch64ISD::LD1LANEpost\0"
565 "AArch64ISD::LD1RO_MERGE_ZERO\0"
566 "AArch64ISD::LD1RQ_MERGE_ZERO\0"
567 "AArch64ISD::LD1S_MERGE_ZERO\0"
568 "AArch64ISD::LD1_MERGE_ZERO\0"
569 "AArch64ISD::LD1x2post\0"
570 "AArch64ISD::LD1x3post\0"
571 "AArch64ISD::LD1x4post\0"
572 "AArch64ISD::LD2DUPpost\0"
573 "AArch64ISD::LD2LANEpost\0"
574 "AArch64ISD::LD2post\0"
575 "AArch64ISD::LD3DUPpost\0"
576 "AArch64ISD::LD3LANEpost\0"
577 "AArch64ISD::LD3post\0"
578 "AArch64ISD::LD4DUPpost\0"
579 "AArch64ISD::LD4LANEpost\0"
580 "AArch64ISD::LD4post\0"
581 "AArch64ISD::LDFF1S_MERGE_ZERO\0"
582 "AArch64ISD::LDFF1_MERGE_ZERO\0"
583 "AArch64ISD::LDIAPP\0"
584 "AArch64ISD::LDNF1S_MERGE_ZERO\0"
585 "AArch64ISD::LDNF1_MERGE_ZERO\0"
586 "AArch64ISD::LDNP\0"
587 "AArch64ISD::LDP\0"
588 "AArch64ISD::LOADgot\0"
589 "AArch64ISD::LS64_BUILD\0"
590 "AArch64ISD::LS64_EXTRACT\0"
591 "AArch64ISD::MOVI\0"
592 "AArch64ISD::MOVIedit\0"
593 "AArch64ISD::MOVImsl\0"
594 "AArch64ISD::MOVIshift\0"
595 "AArch64ISD::MRRS\0"
596 "AArch64ISD::MRS\0"
597 "AArch64ISD::MSRR\0"
598 "AArch64ISD::MULHS_PRED\0"
599 "AArch64ISD::MULHU_PRED\0"
600 "AArch64ISD::MUL_PRED\0"
601 "AArch64ISD::MVNImsl\0"
602 "AArch64ISD::MVNIshift\0"
603 "AArch64ISD::NEG_MERGE_PASSTHRU\0"
604 "AArch64ISD::NVCAST\0"
605 "AArch64ISD::ORRi\0"
606 "AArch64ISD::ORV_PRED\0"
607 "AArch64ISD::PMULL\0"
608 "AArch64ISD::PREFETCH\0"
609 "AArch64ISD::PROBED_ALLOCA\0"
610 "AArch64ISD::PTEST\0"
611 "AArch64ISD::PTEST_ANY\0"
612 "AArch64ISD::PTEST_FIRST\0"
613 "AArch64ISD::PTRUE\0"
614 "AArch64ISD::RANGE_PREFETCH\0"
615 "AArch64ISD::RDSVL\0"
616 "AArch64ISD::REINTERPRET_CAST\0"
617 "AArch64ISD::REQUIRES_ZA_SAVE\0"
618 "AArch64ISD::REQUIRES_ZT0_SAVE\0"
619 "AArch64ISD::RESTORE_ZT\0"
620 "AArch64ISD::RET_GLUE\0"
621 "AArch64ISD::REV16\0"
622 "AArch64ISD::REV32\0"
623 "AArch64ISD::REV64\0"
624 "AArch64ISD::REVD_MERGE_PASSTHRU\0"
625 "AArch64ISD::REVH_MERGE_PASSTHRU\0"
626 "AArch64ISD::REVW_MERGE_PASSTHRU\0"
627 "AArch64ISD::RHADDS_PRED\0"
628 "AArch64ISD::RHADDU_PRED\0"
629 "AArch64ISD::RSHRNB_I\0"
630 "AArch64ISD::SADDLP\0"
631 "AArch64ISD::SADDLV\0"
632 "AArch64ISD::SADDV\0"
633 "AArch64ISD::SADDV_PRED\0"
634 "AArch64ISD::SAVE_ZT\0"
635 "AArch64ISD::SBC\0"
636 "AArch64ISD::SBCS\0"
637 "AArch64ISD::SDOT\0"
638 "AArch64ISD::SETCC_MERGE_ZERO\0"
639 "AArch64ISD::SHL_PRED\0"
640 "AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU\0"
641 "AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU\0"
642 "AArch64ISD::SITOF\0"
643 "AArch64ISD::SMAXV\0"
644 "AArch64ISD::SMAXV_PRED\0"
645 "AArch64ISD::SMAX_PRED\0"
646 "AArch64ISD::SME_STATE_ALLOC\0"
647 "AArch64ISD::SME_ZA_LDR\0"
648 "AArch64ISD::SME_ZA_STR\0"
649 "AArch64ISD::SMINV\0"
650 "AArch64ISD::SMINV_PRED\0"
651 "AArch64ISD::SMIN_PRED\0"
652 "AArch64ISD::SMSTART\0"
653 "AArch64ISD::SMSTOP\0"
654 "AArch64ISD::SMULL\0"
655 "AArch64ISD::SPLICE\0"
656 "AArch64ISD::SQABS\0"
657 "AArch64ISD::SQADD\0"
658 "AArch64ISD::SQDMULH\0"
659 "AArch64ISD::SQDMULL\0"
660 "AArch64ISD::SQNEG\0"
661 "AArch64ISD::SQRDMLAH\0"
662 "AArch64ISD::SQRDMLSH\0"
663 "AArch64ISD::SQRDMULH\0"
664 "AArch64ISD::SQRSHL\0"
665 "AArch64ISD::SQRSHRN\0"
666 "AArch64ISD::SQRSHRUN\0"
667 "AArch64ISD::SQSHL\0"
668 "AArch64ISD::SQSHLU_I\0"
669 "AArch64ISD::SQSHL_I\0"
670 "AArch64ISD::SQSHRN\0"
671 "AArch64ISD::SQSHRUN\0"
672 "AArch64ISD::SQSUB\0"
673 "AArch64ISD::SRA_PRED\0"
674 "AArch64ISD::SRL_PRED\0"
675 "AArch64ISD::SRSHR_I\0"
676 "AArch64ISD::SST1Q_INDEX_PRED\0"
677 "AArch64ISD::SST1Q_PRED\0"
678 "AArch64ISD::SST1_IMM_PRED\0"
679 "AArch64ISD::SST1_PRED\0"
680 "AArch64ISD::SST1_SCALED_PRED\0"
681 "AArch64ISD::SST1_SXTW_PRED\0"
682 "AArch64ISD::SST1_SXTW_SCALED_PRED\0"
683 "AArch64ISD::SST1_UXTW_PRED\0"
684 "AArch64ISD::SST1_UXTW_SCALED_PRED\0"
685 "AArch64ISD::SSTNT1_INDEX_PRED\0"
686 "AArch64ISD::SSTNT1_PRED\0"
687 "AArch64ISD::ST1_PRED\0"
688 "AArch64ISD::ST1x2post\0"
689 "AArch64ISD::ST1x3post\0"
690 "AArch64ISD::ST1x4post\0"
691 "AArch64ISD::ST2G\0"
692 "AArch64ISD::ST2LANEpost\0"
693 "AArch64ISD::ST2post\0"
694 "AArch64ISD::ST3LANEpost\0"
695 "AArch64ISD::ST3post\0"
696 "AArch64ISD::ST4LANEpost\0"
697 "AArch64ISD::ST4post\0"
698 "AArch64ISD::STG\0"
699 "AArch64ISD::STILP\0"
700 "AArch64ISD::STNP\0"
701 "AArch64ISD::STP\0"
702 "AArch64ISD::STRICT_FADD_PRED\0"
703 "AArch64ISD::STRICT_FCEIL_MERGE_PASSTHRU\0"
704 "AArch64ISD::STRICT_FCMP\0"
705 "AArch64ISD::STRICT_FCMPE\0"
706 "AArch64ISD::STRICT_FDIV_PRED\0"
707 "AArch64ISD::STRICT_FFLOOR_MERGE_PASSTHRU\0"
708 "AArch64ISD::STRICT_FMAXNM_PRED\0"
709 "AArch64ISD::STRICT_FMAX_PRED\0"
710 "AArch64ISD::STRICT_FMA_PRED\0"
711 "AArch64ISD::STRICT_FMINNM_PRED\0"
712 "AArch64ISD::STRICT_FMIN_PRED\0"
713 "AArch64ISD::STRICT_FMUL_PRED\0"
714 "AArch64ISD::STRICT_FNEARBYINT_MERGE_PASSTHRU\0"
715 "AArch64ISD::STRICT_FROUNDEVEN_MERGE_PASSTHRU\0"
716 "AArch64ISD::STRICT_FROUND_MERGE_PASSTHRU\0"
717 "AArch64ISD::STRICT_FSQRT_MERGE_PASSTHRU\0"
718 "AArch64ISD::STRICT_FSUB_PRED\0"
719 "AArch64ISD::STRICT_FTRUNC_MERGE_PASSTHRU\0"
720 "AArch64ISD::STZ2G\0"
721 "AArch64ISD::STZG\0"
722 "AArch64ISD::SUBS\0"
723 "AArch64ISD::SUNPKHI\0"
724 "AArch64ISD::SUNPKLO\0"
725 "AArch64ISD::SUQADD\0"
726 "AArch64ISD::SVC\0"
727 "AArch64ISD::TBL\0"
728 "AArch64ISD::TBNZ\0"
729 "AArch64ISD::TBZ\0"
730 "AArch64ISD::TC_RETURN\0"
731 "AArch64ISD::THREAD_POINTER\0"
732 "AArch64ISD::TLSDESC_AUTH_CALLSEQ\0"
733 "AArch64ISD::TLSDESC_CALLSEQ\0"
734 "AArch64ISD::TRN1\0"
735 "AArch64ISD::TRN2\0"
736 "AArch64ISD::UADDLP\0"
737 "AArch64ISD::UADDLV\0"
738 "AArch64ISD::UADDV\0"
739 "AArch64ISD::UADDV_PRED\0"
740 "AArch64ISD::UDOT\0"
741 "AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU\0"
742 "AArch64ISD::UITOF\0"
743 "AArch64ISD::UMAXV\0"
744 "AArch64ISD::UMAXV_PRED\0"
745 "AArch64ISD::UMAX_PRED\0"
746 "AArch64ISD::UMINV\0"
747 "AArch64ISD::UMINV_PRED\0"
748 "AArch64ISD::UMIN_PRED\0"
749 "AArch64ISD::UMULL\0"
750 "AArch64ISD::UQADD\0"
751 "AArch64ISD::UQRSHL\0"
752 "AArch64ISD::UQRSHRN\0"
753 "AArch64ISD::UQSHL\0"
754 "AArch64ISD::UQSHL_I\0"
755 "AArch64ISD::UQSHRN\0"
756 "AArch64ISD::UQSUB\0"
757 "AArch64ISD::URSHR_I\0"
758 "AArch64ISD::URSHR_I_PRED\0"
759 "AArch64ISD::USDOT\0"
760 "AArch64ISD::USQADD\0"
761 "AArch64ISD::UUNPKHI\0"
762 "AArch64ISD::UUNPKLO\0"
763 "AArch64ISD::UZP1\0"
764 "AArch64ISD::UZP2\0"
765 "AArch64ISD::VASHR\0"
766 "AArch64ISD::VLSHR\0"
767 "AArch64ISD::VSHL\0"
768 "AArch64ISD::VSLI\0"
769 "AArch64ISD::VSRI\0"
770 "AArch64ISD::WHILEGE_PRED_COUNTER\0"
771 "AArch64ISD::WHILEGT_PRED_COUNTER\0"
772 "AArch64ISD::WHILEHI_PRED_COUNTER\0"
773 "AArch64ISD::WHILEHS_PRED_COUNTER\0"
774 "AArch64ISD::WHILELE_PRED_COUNTER\0"
775 "AArch64ISD::WHILELO_PRED_COUNTER\0"
776 "AArch64ISD::WHILELS_PRED_COUNTER\0"
777 "AArch64ISD::WHILELT_PRED_COUNTER\0"
778 "AArch64ISD::WrapperLarge\0"
779 "AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU\0"
780 "AArch64ISD::ZIP1\0"
781 "AArch64ISD::ZIP2\0"
782 ;
783#ifdef __GNUC__
784#pragma GCC diagnostic pop
785#endif
786
787static constexpr llvm::StringTable
788AArch64SDNodeNames = AArch64SDNodeNamesStorage;
789
790static const VTByHwModePair AArch64VTByHwModeTable[] = {
791 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
792};
793
794static const SDTypeConstraint AArch64SDTypeConstraints[] = {
795 /* 0 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::Other},
796 /* 3 */ {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
797 /* 6 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
798 /* 12 */ {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
799 /* 16 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
800 /* 22 */ {SDTCisSameAs, 2, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
801 /* 25 */ {SDTCisSameAs, 2, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
802 /* 28 */ {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i64},
803 /* 31 */ {SDTCisSameAs, 1, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i64},
804 /* 36 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i64},
805 /* 39 */ {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i64},
806 /* 41 */ {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::v2i64},
807 /* 44 */ {SDTCisInt, 5, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::aarch64svcount},
808 /* 50 */ {SDTCisVT, 3, 0, 0, MVT::i64}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
809 /* 54 */ {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
810 /* 60 */ {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
811 /* 62 */ {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i64}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
812 /* 66 */ {SDTCisVT, 1, 0, 0, MVT::Other}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
813 /* 68 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
814 /* 71 */ {SDTCisSameAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
815 /* 74 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
816 /* 77 */ {SDTCisOpSmallerThanOp, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
817 /* 80 */ {SDTCisVT, 2, 0, 0, MVT::Other}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
818 /* 83 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
819 /* 86 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
820 /* 89 */ {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
821 /* 91 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
822 /* 95 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
823 /* 99 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
824 /* 104 */ {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
825 /* 108 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
826 /* 112 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
827 /* 116 */ {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
828 /* 120 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
829 /* 125 */ {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisSameAs, 3, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 0, 0, 0, MVT::i1}, {SDTCisSameNumEltsAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
830 /* 132 */ {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
831 /* 134 */ {SDTCisSameNumEltsAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 2, 0, 0, MVT::i1}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
832 /* 139 */ {SDTCisOpSmallerThanOp, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
833 /* 143 */ {SDTCisSameAs, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisSameNumEltsAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
834 /* 150 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
835 /* 153 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
836 /* 158 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
837 /* 165 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
838 /* 170 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVTSmallerThanOp, 3, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
839 /* 179 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
840 /* 186 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
841 /* 193 */ {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
842 /* 199 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
843 /* 209 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
844 /* 214 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
845 /* 216 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
846 /* 220 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
847 /* 222 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
848 /* 224 */ {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
849 /* 228 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
850 /* 231 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
851 /* 235 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
852 /* 239 */ {SDTCisPtrTy, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
853 /* 242 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
854 /* 244 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
855 /* 249 */ {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64},
856 /* 251 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
857 /* 253 */ {SDTCisSameNumEltsAs, 1, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
858 /* 257 */ {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
859 /* 259 */ {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
860};
861
862static const SDNodeDesc AArch64SDNodeDescs[] = {
863 {1, 3, 0, 0, 0, 1, 209, 5}, // ABDS_PRED
864 {1, 3, 0, 0, 0, 23, 209, 5}, // ABDU_PRED
865 {1, 3, 0, 0, 0, 45, 209, 5}, // ABS_MERGE_PASSTHRU
866 {1, 3, 0, 0, 0, 76, 224, 4}, // ADC
867 {2, 3, 0, 0, 0, 92, 244, 5}, // ADCS
868 {1, 2, 0, 0, 0, 109, 139, 4}, // ADDHN
869 {1, 2, 0, 0, 0, 127, 105, 3}, // ADDP
870 {2, 2, 0, 0, 0, 144, 245, 4}, // ADDS
871 {1, 2, 0, 0, 0, 161, 225, 3}, // ADDlow
872 {1, 1, 0, 0, 0, 180, 220, 2}, // ADR
873 {1, 1, 0, 0, 0, 196, 220, 2}, // ADRP
874 {2, 2, 0, 0, 0, 213, 245, 4}, // ANDS
875 {1, 2, 0, 0, 0, 230, 257, 2}, // ANDV_PRED
876 {1, 3, 0, 0, 0, 252, 179, 7}, // ASRD_MERGE_OP1
877 {1, 1, 0, 0, 0, 279, 71, 3}, // ASSERT_ZEXT_BOOL
878 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 308, 50, 4}, // AUTH_CALL
879 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 330, 54, 6}, // AUTH_CALL_RVMARKER
880 {0, 5, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 361, 62, 4}, // AUTH_TC_RETURN
881 {1, 2, 0, 0, 0, 388, 165, 5}, // BIC
882 {1, 3, 0, 0, 0, 404, 112, 4}, // BICi
883 {1, 3, 0, 0, 0, 421, 209, 5}, // BITREVERSE_MERGE_PASSTHRU
884 {0, 3, 0|1<<SDNPHasChain, 0, 0, 459, 0, 3}, // BRCOND
885 {1, 3, 0, 0, 0, 478, 104, 4}, // BSP
886 {1, 3, 0, 0, 0, 494, 209, 5}, // BSWAP_MERGE_PASSTHRU
887 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 527, 53, 1}, // CALL
888 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 544, 53, 1}, // CALL_ARM64EC_TO_X64
889 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 576, 53, 1}, // CALL_BTI
890 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 597, 53, 1}, // CALL_RVMARKER
891 {0, 4, 0|1<<SDNPHasChain, 0, 0, 623, 12, 4}, // CB
892 {0, 2, 0|1<<SDNPHasChain, 0, 0, 638, 66, 2}, // CBNZ
893 {0, 2, 0|1<<SDNPHasChain, 0, 0, 655, 66, 2}, // CBZ
894 {1, 5, 0, 0, 0, 671, 6, 6}, // CCMN
895 {1, 5, 0, 0, 0, 688, 6, 6}, // CCMP
896 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 705, 0, 0}, // CHECK_MATCHING_VL
897 {1, 3, 0, 0, 0, 735, 253, 4}, // CLASTA_N
898 {1, 3, 0, 0, 0, 756, 253, 4}, // CLASTB_N
899 {1, 2, 0, 0, 0, 777, 105, 3}, // CMTST
900 {1, 1, 0|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 795, 0, 0}, // COALESCER_BARRIER
901 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 825, 83, 3}, // COND_SMSTART
902 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 850, 83, 3}, // COND_SMSTOP
903 {1, 4, 0, 0, 0, 874, 235, 4}, // CSEL
904 {1, 4, 0, 0, 0, 891, 235, 4}, // CSINC
905 {1, 4, 0, 0, 0, 909, 235, 4}, // CSINV
906 {1, 4, 0, 0, 0, 927, 235, 4}, // CSNEG
907 {1, 3, 0, 0, 0, 945, 209, 5}, // CTLZ_MERGE_PASSTHRU
908 {1, 3, 0, 0, 0, 977, 209, 5}, // CTPOP_MERGE_PASSTHRU
909 {1, 2, 0, 0, 0, 1010, 86, 3}, // CTTZ_ELTS
910 {1, 1, 0, 0, 0, 1032, 107, 1}, // DUP
911 {1, 2, 0, 0, 0, 1048, 214, 2}, // DUPLANE128
912 {1, 2, 0, 0, 0, 1071, 214, 2}, // DUPLANE16
913 {1, 2, 0, 0, 0, 1093, 214, 2}, // DUPLANE32
914 {1, 2, 0, 0, 0, 1115, 214, 2}, // DUPLANE64
915 {1, 2, 0, 0, 0, 1137, 214, 2}, // DUPLANE8
916 {1, 3, 0, 0, 0, 1158, 120, 5}, // DUP_MERGE_PASSTHRU
917 {1, 0, 0|1<<SDNPHasChain, 0, 0, 1189, 67, 1}, // ENTRY_PSTATE_SM
918 {1, 2, 0, 0, 0, 1217, 257, 2}, // EORV_PRED
919 {1, 3, 0, 0, 0, 1239, 108, 4}, // EXT
920 {1, 3, 0, 0, 0, 1255, 239, 3}, // EXTR
921 {1, 3, 0, 0, 0, 1272, 209, 5}, // FABS_MERGE_PASSTHRU
922 {1, 3, 0, 0, 0, 1304, 253, 4}, // FADDA_PRED
923 {1, 2, 0, 0, 0, 1327, 257, 2}, // FADDV_PRED
924 {1, 3, 0, 0, 0, 1350, 209, 5}, // FADD_PRED
925 {1, 5, 0, 0, 0, 1372, 16, 6}, // FCCMP
926 {1, 3, 0, 0, 0, 1390, 209, 5}, // FCEIL_MERGE_PASSTHRU
927 {1, 2, 0, 0, 0, 1423, 261, 1}, // FCMEQ
928 {1, 2, 0, 0, 0, 1441, 261, 1}, // FCMGE
929 {1, 2, 0, 0, 0, 1459, 261, 1}, // FCMGT
930 {1, 2, 0, 0, 0, 1477, 22, 3}, // FCMP
931 {1, 1, 0, 0, 0, 1494, 95, 4}, // FCVTAS_HALF
932 {1, 1, 0, 0, 0, 1518, 95, 4}, // FCVTAU_HALF
933 {1, 1, 0, 0, 0, 1542, 95, 4}, // FCVTMS_HALF
934 {1, 1, 0, 0, 0, 1566, 95, 4}, // FCVTMU_HALF
935 {1, 1, 0, 0, 0, 1590, 95, 4}, // FCVTNS_HALF
936 {1, 1, 0, 0, 0, 1614, 95, 4}, // FCVTNU_HALF
937 {1, 1, 0, 0, 0, 1638, 95, 4}, // FCVTPS_HALF
938 {1, 1, 0, 0, 0, 1662, 95, 4}, // FCVTPU_HALF
939 {1, 1, 0, 0, 0, 1686, 91, 4}, // FCVTXN
940 {1, 3, 0, 0, 0, 1705, 143, 7}, // FCVTX_MERGE_PASSTHRU
941 {1, 1, 0, 0, 0, 1738, 95, 4}, // FCVTZS_HALF
942 {1, 3, 0, 0, 0, 1762, 143, 7}, // FCVTZS_MERGE_PASSTHRU
943 {1, 1, 0, 0, 0, 1796, 95, 4}, // FCVTZU_HALF
944 {1, 3, 0, 0, 0, 1820, 143, 7}, // FCVTZU_MERGE_PASSTHRU
945 {1, 3, 0, 0, 0, 1854, 209, 5}, // FDIV_PRED
946 {1, 3, 0, 0, 0, 1876, 209, 5}, // FFLOOR_MERGE_PASSTHRU
947 {1, 2, 0, 0, 0, 1910, 257, 2}, // FMAXNMV_PRED
948 {1, 3, 0, 0, 0, 1935, 209, 5}, // FMAXNM_PRED
949 {1, 2, 0, 0, 0, 1959, 257, 2}, // FMAXV_PRED
950 {1, 3, 0, 0, 0, 1982, 209, 5}, // FMAX_PRED
951 {1, 4, 0, 0, 0, 2004, 199, 10}, // FMA_PRED
952 {1, 2, 0, 0, 0, 2025, 257, 2}, // FMINNMV_PRED
953 {1, 3, 0, 0, 0, 2050, 209, 5}, // FMINNM_PRED
954 {1, 2, 0, 0, 0, 2074, 257, 2}, // FMINV_PRED
955 {1, 3, 0, 0, 0, 2097, 209, 5}, // FMIN_PRED
956 {1, 1, 0, 0, 0, 2119, 252, 1}, // FMOV
957 {1, 3, 0, 0, 0, 2136, 209, 5}, // FMUL_PRED
958 {1, 3, 0, 0, 0, 2158, 209, 5}, // FNEARBYINT_MERGE_PASSTHRU
959 {1, 3, 0, 0, 0, 2196, 209, 5}, // FNEG_MERGE_PASSTHRU
960 {1, 3, 0, 0, 0, 2228, 143, 7}, // FP_EXTEND_MERGE_PASSTHRU
961 {1, 4, 0, 0, 0, 2265, 193, 6}, // FP_ROUND_MERGE_PASSTHRU
962 {1, 1, 0, 0, 0, 2301, 222, 2}, // FRECPE
963 {1, 2, 0, 0, 0, 2320, 228, 3}, // FRECPS
964 {1, 3, 0, 0, 0, 2339, 209, 5}, // FRECPX_MERGE_PASSTHRU
965 {1, 3, 0, 0, 0, 2373, 209, 5}, // FRINT32_MERGE_PASSTHRU
966 {1, 3, 0, 0, 0, 2408, 209, 5}, // FRINT64_MERGE_PASSTHRU
967 {1, 3, 0, 0, 0, 2443, 209, 5}, // FRINT_MERGE_PASSTHRU
968 {1, 3, 0, 0, 0, 2476, 209, 5}, // FROUNDEVEN_MERGE_PASSTHRU
969 {1, 3, 0, 0, 0, 2514, 209, 5}, // FROUND_MERGE_PASSTHRU
970 {1, 1, 0, 0, 0, 2548, 222, 2}, // FRSQRTE
971 {1, 2, 0, 0, 0, 2568, 228, 3}, // FRSQRTS
972 {1, 3, 0, 0, 0, 2588, 209, 5}, // FSQRT_MERGE_PASSTHRU
973 {1, 3, 0, 0, 0, 2621, 209, 5}, // FSUB_PRED
974 {1, 3, 0, 0, 0, 2643, 209, 5}, // FTRUNC32_MERGE_PASSTHRU
975 {1, 3, 0, 0, 0, 2679, 209, 5}, // FTRUNC64_MERGE_PASSTHRU
976 {1, 3, 0, 0, 0, 2715, 209, 5}, // FTRUNC_MERGE_PASSTHRU
977 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2749, 0, 0}, // GLD1Q_INDEX_MERGE_ZERO
978 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2784, 186, 7}, // GLD1Q_MERGE_ZERO
979 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2813, 186, 7}, // GLD1S_IMM_MERGE_ZERO
980 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2846, 158, 7}, // GLD1S_MERGE_ZERO
981 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2875, 158, 7}, // GLD1S_SCALED_MERGE_ZERO
982 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2911, 158, 7}, // GLD1S_SXTW_MERGE_ZERO
983 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2945, 158, 7}, // GLD1S_SXTW_SCALED_MERGE_ZERO
984 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2986, 158, 7}, // GLD1S_UXTW_MERGE_ZERO
985 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3020, 158, 7}, // GLD1S_UXTW_SCALED_MERGE_ZERO
986 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3061, 186, 7}, // GLD1_IMM_MERGE_ZERO
987 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3093, 158, 7}, // GLD1_MERGE_ZERO
988 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3121, 158, 7}, // GLD1_SCALED_MERGE_ZERO
989 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3156, 158, 7}, // GLD1_SXTW_MERGE_ZERO
990 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3189, 158, 7}, // GLD1_SXTW_SCALED_MERGE_ZERO
991 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3229, 158, 7}, // GLD1_UXTW_MERGE_ZERO
992 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3262, 158, 7}, // GLD1_UXTW_SCALED_MERGE_ZERO
993 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3302, 186, 7}, // GLDFF1S_IMM_MERGE_ZERO
994 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3337, 158, 7}, // GLDFF1S_MERGE_ZERO
995 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3368, 158, 7}, // GLDFF1S_SCALED_MERGE_ZERO
996 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3406, 158, 7}, // GLDFF1S_SXTW_MERGE_ZERO
997 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3442, 158, 7}, // GLDFF1S_SXTW_SCALED_MERGE_ZERO
998 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3485, 158, 7}, // GLDFF1S_UXTW_MERGE_ZERO
999 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3521, 158, 7}, // GLDFF1S_UXTW_SCALED_MERGE_ZERO
1000 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3564, 186, 7}, // GLDFF1_IMM_MERGE_ZERO
1001 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3598, 158, 7}, // GLDFF1_MERGE_ZERO
1002 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3628, 158, 7}, // GLDFF1_SCALED_MERGE_ZERO
1003 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3665, 158, 7}, // GLDFF1_SXTW_MERGE_ZERO
1004 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3700, 158, 7}, // GLDFF1_SXTW_SCALED_MERGE_ZERO
1005 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3742, 158, 7}, // GLDFF1_UXTW_MERGE_ZERO
1006 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3777, 158, 7}, // GLDFF1_UXTW_SCALED_MERGE_ZERO
1007 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3819, 186, 7}, // GLDNT1S_MERGE_ZERO
1008 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3850, 0, 0}, // GLDNT1_INDEX_MERGE_ZERO
1009 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3886, 186, 7}, // GLDNT1_MERGE_ZERO
1010 {1, 3, 0, 0, 0, 3916, 209, 5}, // HADDS_PRED
1011 {1, 3, 0, 0, 0, 3939, 209, 5}, // HADDU_PRED
1012 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3962, 67, 1}, // HVC
1013 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 3978, 0, 0}, // INOUT_ZA_USE
1014 {1, 2, 0, 0, 0, 4003, 107, 1}, // INSR
1015 {1, 2, 0, 0, 0, 4020, 257, 2}, // LASTA
1016 {1, 2, 0, 0, 0, 4038, 257, 2}, // LASTB
1017 {2, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4056, 0, 0}, // LD1DUPpost
1018 {2, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4079, 0, 0}, // LD1LANEpost
1019 {1, 2, 0|1<<SDNPHasChain, 0, 0, 4103, 153, 5}, // LD1RO_MERGE_ZERO
1020 {1, 2, 0|1<<SDNPHasChain, 0, 0, 4132, 153, 5}, // LD1RQ_MERGE_ZERO
1021 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4161, 153, 5}, // LD1S_MERGE_ZERO
1022 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4189, 153, 5}, // LD1_MERGE_ZERO
1023 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4216, 0, 0}, // LD1x2post
1024 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4238, 0, 0}, // LD1x3post
1025 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4260, 0, 0}, // LD1x4post
1026 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4282, 0, 0}, // LD2DUPpost
1027 {3, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4305, 0, 0}, // LD2LANEpost
1028 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4329, 0, 0}, // LD2post
1029 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4349, 0, 0}, // LD3DUPpost
1030 {4, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4372, 0, 0}, // LD3LANEpost
1031 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4396, 0, 0}, // LD3post
1032 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4416, 0, 0}, // LD4DUPpost
1033 {5, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4439, 0, 0}, // LD4LANEpost
1034 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4463, 0, 0}, // LD4post
1035 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4483, 153, 5}, // LDFF1S_MERGE_ZERO
1036 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4513, 153, 5}, // LDFF1_MERGE_ZERO
1037 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4542, 28, 3}, // LDIAPP
1038 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4561, 153, 5}, // LDNF1S_MERGE_ZERO
1039 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4591, 153, 5}, // LDNF1_MERGE_ZERO
1040 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4620, 41, 3}, // LDNP
1041 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4637, 28, 3}, // LDP
1042 {1, 1, 0, 0, 0, 4653, 220, 2}, // LOADgot
1043 {1, 8, 0, 0, 0, 4673, 0, 0}, // LS64_BUILD
1044 {1, 2, 0, 0, 0, 4696, 0, 0}, // LS64_EXTRACT
1045 {1, 1, 0, 0, 0, 4721, 252, 1}, // MOVI
1046 {1, 1, 0, 0, 0, 4738, 252, 1}, // MOVIedit
1047 {1, 2, 0, 0, 0, 4759, 251, 2}, // MOVImsl
1048 {1, 2, 0, 0, 0, 4779, 251, 2}, // MOVIshift
1049 {2, 1, 0|1<<SDNPHasChain, 0, 0, 4801, 39, 2}, // MRRS
1050 {2, 1, 0|1<<SDNPHasChain, 0, 0, 4818, 36, 3}, // MRS
1051 {0, 3, 0|1<<SDNPHasChain, 0, 0, 4834, 249, 2}, // MSRR
1052 {1, 3, 0, 0, 0, 4851, 209, 5}, // MULHS_PRED
1053 {1, 3, 0, 0, 0, 4874, 209, 5}, // MULHU_PRED
1054 {1, 3, 0, 0, 0, 4897, 209, 5}, // MUL_PRED
1055 {1, 2, 0, 0, 0, 4918, 251, 2}, // MVNImsl
1056 {1, 2, 0, 0, 0, 4938, 251, 2}, // MVNIshift
1057 {1, 3, 0, 0, 0, 4960, 209, 5}, // NEG_MERGE_PASSTHRU
1058 {1, 1, 0, 0, 0, 4991, 0, 0}, // NVCAST
1059 {1, 3, 0, 0, 0, 5010, 112, 4}, // ORRi
1060 {1, 2, 0, 0, 0, 5027, 257, 2}, // ORV_PRED
1061 {1, 2, 0, 0, 0, 5048, 74, 3}, // PMULL
1062 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5066, 4, 2}, // PREFETCH
1063 {0, 1, 0|1<<SDNPHasChain, 0, 0, 5087, 53, 1}, // PROBED_ALLOCA
1064 {1, 2, 0, 0, 0, 5113, 25, 3}, // PTEST
1065 {1, 2, 0, 0, 0, 5131, 25, 3}, // PTEST_ANY
1066 {1, 2, 0, 0, 0, 5153, 25, 3}, // PTEST_FIRST
1067 {1, 1, 0, 0, 0, 5177, 132, 2}, // PTRUE
1068 {0, 3, 0|1<<SDNPHasChain, 0, 0, 5195, 3, 3}, // RANGE_PREFETCH
1069 {1, 1, 0, 0, 0, 5222, 72, 2}, // RDSVL
1070 {1, 1, 0, 0, 0, 5240, 0, 0}, // REINTERPRET_CAST
1071 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 5269, 0, 0}, // REQUIRES_ZA_SAVE
1072 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 5298, 0, 0}, // REQUIRES_ZT0_SAVE
1073 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5328, 69, 2}, // RESTORE_ZT
1074 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 5351, 0, 0}, // RET_GLUE
1075 {1, 1, 0, 0, 0, 5372, 221, 1}, // REV16
1076 {1, 1, 0, 0, 0, 5390, 221, 1}, // REV32
1077 {1, 1, 0, 0, 0, 5408, 221, 1}, // REV64
1078 {1, 3, 0, 0, 0, 5426, 209, 5}, // REVD_MERGE_PASSTHRU
1079 {1, 3, 0, 0, 0, 5458, 209, 5}, // REVH_MERGE_PASSTHRU
1080 {1, 3, 0, 0, 0, 5490, 209, 5}, // REVW_MERGE_PASSTHRU
1081 {1, 3, 0, 0, 0, 5522, 209, 5}, // RHADDS_PRED
1082 {1, 3, 0, 0, 0, 5546, 209, 5}, // RHADDU_PRED
1083 {1, 2, 0, 0, 0, 5570, 150, 3}, // RSHRNB_I
1084 {1, 1, 0, 0, 0, 5591, 141, 2}, // SADDLP
1085 {1, 1, 0, 0, 0, 5610, 141, 2}, // SADDLV
1086 {1, 1, 0, 0, 0, 5629, 106, 2}, // SADDV
1087 {1, 2, 0, 0, 0, 5647, 257, 2}, // SADDV_PRED
1088 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5670, 69, 2}, // SAVE_ZT
1089 {1, 3, 0, 0, 0, 5690, 224, 4}, // SBC
1090 {2, 3, 0, 0, 0, 5706, 244, 5}, // SBCS
1091 {1, 3, 0, 0, 0, 5723, 116, 4}, // SDOT
1092 {1, 4, 0, 0, 0, 5740, 125, 7}, // SETCC_MERGE_ZERO
1093 {1, 3, 0, 0, 0, 5769, 209, 5}, // SHL_PRED
1094 {1, 4, 0, 0, 0, 5790, 170, 9}, // SIGN_EXTEND_INREG_MERGE_PASSTHRU
1095 {1, 3, 0, 0, 0, 5835, 143, 7}, // SINT_TO_FP_MERGE_PASSTHRU
1096 {1, 1, 0, 0, 0, 5873, 89, 2}, // SITOF
1097 {1, 1, 0, 0, 0, 5891, 106, 2}, // SMAXV
1098 {1, 2, 0, 0, 0, 5909, 257, 2}, // SMAXV_PRED
1099 {1, 3, 0, 0, 0, 5932, 209, 5}, // SMAX_PRED
1100 {0, 0, 0|1<<SDNPHasChain, 0, 0, 5954, 0, 0}, // SME_STATE_ALLOC
1101 {0, 3, 0|1<<SDNPHasChain, 0, 0, 5982, 68, 3}, // SME_ZA_LDR
1102 {0, 3, 0|1<<SDNPHasChain, 0, 0, 6005, 68, 3}, // SME_ZA_STR
1103 {1, 1, 0, 0, 0, 6028, 106, 2}, // SMINV
1104 {1, 2, 0, 0, 0, 6046, 257, 2}, // SMINV_PRED
1105 {1, 3, 0, 0, 0, 6069, 209, 5}, // SMIN_PRED
1106 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 6091, 67, 1}, // SMSTART
1107 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 6111, 67, 1}, // SMSTOP
1108 {1, 2, 0, 0, 0, 6130, 74, 3}, // SMULL
1109 {1, 3, 0, 0, 0, 6148, 209, 5}, // SPLICE
1110 {1, 1, 0, 0, 0, 6167, 222, 2}, // SQABS
1111 {1, 2, 0, 0, 0, 6185, 228, 3}, // SQADD
1112 {1, 2, 0, 0, 0, 6203, 261, 1}, // SQDMULH
1113 {1, 2, 0, 0, 0, 6223, 259, 3}, // SQDMULL
1114 {1, 1, 0, 0, 0, 6243, 222, 2}, // SQNEG
1115 {1, 3, 0, 0, 0, 6261, 231, 4}, // SQRDMLAH
1116 {1, 3, 0, 0, 0, 6282, 231, 4}, // SQRDMLSH
1117 {1, 2, 0, 0, 0, 6303, 228, 3}, // SQRDMULH
1118 {1, 2, 0, 0, 0, 6324, 228, 3}, // SQRSHL
1119 {1, 2, 0, 0, 0, 6343, 99, 5}, // SQRSHRN
1120 {1, 2, 0, 0, 0, 6363, 99, 5}, // SQRSHRUN
1121 {1, 2, 0, 0, 0, 6384, 228, 3}, // SQSHL
1122 {1, 2, 0, 0, 0, 6402, 242, 2}, // SQSHLU_I
1123 {1, 2, 0, 0, 0, 6423, 242, 2}, // SQSHL_I
1124 {1, 2, 0, 0, 0, 6443, 99, 5}, // SQSHRN
1125 {1, 2, 0, 0, 0, 6462, 99, 5}, // SQSHRUN
1126 {1, 2, 0, 0, 0, 6482, 228, 3}, // SQSUB
1127 {1, 3, 0, 0, 0, 6500, 209, 5}, // SRA_PRED
1128 {1, 3, 0, 0, 0, 6521, 209, 5}, // SRL_PRED
1129 {1, 2, 0, 0, 0, 6542, 242, 2}, // SRSHR_I
1130 {0, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6562, 0, 0}, // SST1Q_INDEX_PRED
1131 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6591, 186, 7}, // SST1Q_PRED
1132 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6614, 186, 7}, // SST1_IMM_PRED
1133 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6640, 158, 7}, // SST1_PRED
1134 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6662, 158, 7}, // SST1_SCALED_PRED
1135 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6691, 158, 7}, // SST1_SXTW_PRED
1136 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6718, 158, 7}, // SST1_SXTW_SCALED_PRED
1137 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6752, 158, 7}, // SST1_UXTW_PRED
1138 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6779, 158, 7}, // SST1_UXTW_SCALED_PRED
1139 {0, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6813, 0, 0}, // SSTNT1_INDEX_PRED
1140 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6843, 186, 7}, // SSTNT1_PRED
1141 {0, 4, 0|1<<SDNPHasChain, 0, 0, 6867, 134, 5}, // ST1_PRED
1142 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6888, 0, 0}, // ST1x2post
1143 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6910, 0, 0}, // ST1x3post
1144 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6932, 0, 0}, // ST1x4post
1145 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6954, 60, 2}, // ST2G
1146 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6971, 0, 0}, // ST2LANEpost
1147 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6995, 0, 0}, // ST2post
1148 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7015, 0, 0}, // ST3LANEpost
1149 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7039, 0, 0}, // ST3post
1150 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7059, 0, 0}, // ST4LANEpost
1151 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7083, 0, 0}, // ST4post
1152 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7103, 60, 2}, // STG
1153 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7119, 28, 3}, // STILP
1154 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7137, 41, 3}, // STNP
1155 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7154, 28, 3}, // STP
1156 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7170, 209, 5}, // STRICT_FADD_PRED
1157 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7199, 209, 5}, // STRICT_FCEIL_MERGE_PASSTHRU
1158 {1, 2, 0|1<<SDNPHasChain, 0|1<<SDNFIsStrictFP, 0, 7239, 22, 3}, // STRICT_FCMP
1159 {1, 2, 0|1<<SDNPHasChain, 0|1<<SDNFIsStrictFP, 0, 7263, 22, 3}, // STRICT_FCMPE
1160 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7288, 209, 5}, // STRICT_FDIV_PRED
1161 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7317, 209, 5}, // STRICT_FFLOOR_MERGE_PASSTHRU
1162 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7358, 209, 5}, // STRICT_FMAXNM_PRED
1163 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7389, 209, 5}, // STRICT_FMAX_PRED
1164 {1, 4, 0|1<<SDNPHasChain, 0, 0, 7418, 199, 10}, // STRICT_FMA_PRED
1165 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7446, 209, 5}, // STRICT_FMINNM_PRED
1166 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7477, 209, 5}, // STRICT_FMIN_PRED
1167 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7506, 209, 5}, // STRICT_FMUL_PRED
1168 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7535, 209, 5}, // STRICT_FNEARBYINT_MERGE_PASSTHRU
1169 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7580, 209, 5}, // STRICT_FROUNDEVEN_MERGE_PASSTHRU
1170 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7625, 209, 5}, // STRICT_FROUND_MERGE_PASSTHRU
1171 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7666, 209, 5}, // STRICT_FSQRT_MERGE_PASSTHRU
1172 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7706, 209, 5}, // STRICT_FSUB_PRED
1173 {1, 3, 0|1<<SDNPHasChain, 0, 0, 7735, 209, 5}, // STRICT_FTRUNC_MERGE_PASSTHRU
1174 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7776, 60, 2}, // STZ2G
1175 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7794, 60, 2}, // STZG
1176 {2, 2, 0, 0, 0, 7811, 245, 4}, // SUBS
1177 {1, 1, 0, 0, 0, 7828, 77, 3}, // SUNPKHI
1178 {1, 1, 0, 0, 0, 7848, 77, 3}, // SUNPKLO
1179 {1, 2, 0, 0, 0, 7868, 228, 3}, // SUQADD
1180 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 7887, 67, 1}, // SVC
1181 {1, 2, 0, 0, 0, 7903, 113, 3}, // TBL
1182 {0, 3, 0|1<<SDNPHasChain, 0, 0, 7919, 80, 3}, // TBNZ
1183 {0, 3, 0|1<<SDNPHasChain, 0, 0, 7936, 80, 3}, // TBZ
1184 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 7952, 53, 1}, // TC_RETURN
1185 {1, 0, 0, 0, 0, 7974, 53, 1}, // THREAD_POINTER
1186 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 8001, 53, 1}, // TLSDESC_AUTH_CALLSEQ
1187 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 8034, 53, 1}, // TLSDESC_CALLSEQ
1188 {1, 2, 0, 0, 0, 8062, 105, 3}, // TRN1
1189 {1, 2, 0, 0, 0, 8079, 105, 3}, // TRN2
1190 {1, 1, 0, 0, 0, 8096, 141, 2}, // UADDLP
1191 {1, 1, 0, 0, 0, 8115, 141, 2}, // UADDLV
1192 {1, 1, 0, 0, 0, 8134, 106, 2}, // UADDV
1193 {1, 2, 0, 0, 0, 8152, 257, 2}, // UADDV_PRED
1194 {1, 3, 0, 0, 0, 8175, 116, 4}, // UDOT
1195 {1, 3, 0, 0, 0, 8192, 143, 7}, // UINT_TO_FP_MERGE_PASSTHRU
1196 {1, 1, 0, 0, 0, 8230, 89, 2}, // UITOF
1197 {1, 1, 0, 0, 0, 8248, 106, 2}, // UMAXV
1198 {1, 2, 0, 0, 0, 8266, 257, 2}, // UMAXV_PRED
1199 {1, 3, 0, 0, 0, 8289, 209, 5}, // UMAX_PRED
1200 {1, 1, 0, 0, 0, 8311, 106, 2}, // UMINV
1201 {1, 2, 0, 0, 0, 8329, 257, 2}, // UMINV_PRED
1202 {1, 3, 0, 0, 0, 8352, 209, 5}, // UMIN_PRED
1203 {1, 2, 0, 0, 0, 8374, 74, 3}, // UMULL
1204 {1, 2, 0, 0, 0, 8392, 228, 3}, // UQADD
1205 {1, 2, 0, 0, 0, 8410, 228, 3}, // UQRSHL
1206 {1, 2, 0, 0, 0, 8429, 99, 5}, // UQRSHRN
1207 {1, 2, 0, 0, 0, 8449, 228, 3}, // UQSHL
1208 {1, 2, 0, 0, 0, 8467, 242, 2}, // UQSHL_I
1209 {1, 2, 0, 0, 0, 8487, 99, 5}, // UQSHRN
1210 {1, 2, 0, 0, 0, 8506, 228, 3}, // UQSUB
1211 {1, 2, 0, 0, 0, 8524, 242, 2}, // URSHR_I
1212 {1, 3, 0, 0, 0, 8544, 179, 7}, // URSHR_I_PRED
1213 {1, 3, 0, 0, 0, 8569, 116, 4}, // USDOT
1214 {1, 2, 0, 0, 0, 8587, 228, 3}, // USQADD
1215 {1, 1, 0, 0, 0, 8606, 77, 3}, // UUNPKHI
1216 {1, 1, 0, 0, 0, 8626, 77, 3}, // UUNPKLO
1217 {1, 2, 0, 0, 0, 8646, 105, 3}, // UZP1
1218 {1, 2, 0, 0, 0, 8663, 105, 3}, // UZP2
1219 {1, 2, 0, 0, 0, 8680, 242, 2}, // VASHR
1220 {1, 2, 0, 0, 0, 8698, 242, 2}, // VLSHR
1221 {1, 2, 0, 0, 0, 8716, 242, 2}, // VSHL
1222 {1, 3, 0, 0, 0, 8733, 216, 4}, // VSLI
1223 {1, 3, 0, 0, 0, 8750, 216, 4}, // VSRI
1224 {2, 4, 0, 0, 0, 8767, 44, 6}, // WHILEGE_PRED_COUNTER
1225 {2, 4, 0, 0, 0, 8800, 44, 6}, // WHILEGT_PRED_COUNTER
1226 {2, 4, 0, 0, 0, 8833, 44, 6}, // WHILEHI_PRED_COUNTER
1227 {2, 4, 0, 0, 0, 8866, 44, 6}, // WHILEHS_PRED_COUNTER
1228 {2, 4, 0, 0, 0, 8899, 44, 6}, // WHILELE_PRED_COUNTER
1229 {2, 4, 0, 0, 0, 8932, 44, 6}, // WHILELO_PRED_COUNTER
1230 {2, 4, 0, 0, 0, 8965, 44, 6}, // WHILELS_PRED_COUNTER
1231 {2, 4, 0, 0, 0, 8998, 44, 6}, // WHILELT_PRED_COUNTER
1232 {1, 4, 0, 0, 0, 9031, 31, 5}, // WrapperLarge
1233 {1, 4, 0, 0, 0, 9056, 170, 9}, // ZERO_EXTEND_INREG_MERGE_PASSTHRU
1234 {1, 2, 0, 0, 0, 9101, 105, 3}, // ZIP1
1235 {1, 2, 0, 0, 0, 9118, 105, 3}, // ZIP2
1236};
1237
1238static const SDNodeInfo AArch64GenSDNodeInfo(
1239 /*NumOpcodes=*/373, AArch64SDNodeDescs, AArch64SDNodeNames,
1240 AArch64VTByHwModeTable, AArch64SDTypeConstraints);
1241
1242} // namespace llvm
1243
1244#endif // GET_SDNODE_DESC
1245
1246