1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: AArch64.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::AArch64ISD {
14
15enum GenNodeType : unsigned {
16 ABDS_PRED = ISD::BUILTIN_OP_END,
17 ABDU_PRED,
18 ABS_MERGE_PASSTHRU,
19 ADC,
20 ADCS,
21 ADDP,
22 ADDS,
23 ADDlow,
24 ADR,
25 ADRP,
26 ALLOCATE_ZA_BUFFER,
27 ALLOC_SME_SAVE_BUFFER,
28 ANDS,
29 ANDV_PRED,
30 ASRD_MERGE_OP1,
31 ASSERT_ZEXT_BOOL,
32 AUTH_CALL,
33 AUTH_CALL_RVMARKER,
34 AUTH_TC_RETURN,
35 BIC,
36 BICi,
37 BITREVERSE_MERGE_PASSTHRU,
38 BRCOND,
39 BSP,
40 BSWAP_MERGE_PASSTHRU,
41 CALL,
42 CALL_ARM64EC_TO_X64,
43 CALL_BTI,
44 CALL_RVMARKER,
45 CB,
46 CBNZ,
47 CBZ,
48 CCMN,
49 CCMP,
50 CHECK_MATCHING_VL,
51 CLASTA_N,
52 CLASTB_N,
53 COALESCER_BARRIER,
54 COND_SMSTART,
55 COND_SMSTOP,
56 CSEL,
57 CSINC,
58 CSINV,
59 CSNEG,
60 CTLZ_MERGE_PASSTHRU,
61 CTPOP_MERGE_PASSTHRU,
62 CTTZ_ELTS,
63 DUP,
64 DUPLANE128,
65 DUPLANE16,
66 DUPLANE32,
67 DUPLANE64,
68 DUPLANE8,
69 DUP_MERGE_PASSTHRU,
70 ENTRY_PSTATE_SM,
71 EORV_PRED,
72 EXT,
73 EXTR,
74 FABS_MERGE_PASSTHRU,
75 FADDA_PRED,
76 FADDV_PRED,
77 FADD_PRED,
78 FCCMP,
79 FCEIL_MERGE_PASSTHRU,
80 FCMEQ,
81 FCMGE,
82 FCMGT,
83 FCMP,
84 FCVTAS_HALF,
85 FCVTAU_HALF,
86 FCVTMS_HALF,
87 FCVTMU_HALF,
88 FCVTNS_HALF,
89 FCVTNU_HALF,
90 FCVTPS_HALF,
91 FCVTPU_HALF,
92 FCVTXN,
93 FCVTX_MERGE_PASSTHRU,
94 FCVTZS_HALF,
95 FCVTZS_MERGE_PASSTHRU,
96 FCVTZU_HALF,
97 FCVTZU_MERGE_PASSTHRU,
98 FDIV_PRED,
99 FFLOOR_MERGE_PASSTHRU,
100 FMAXNMV_PRED,
101 FMAXNM_PRED,
102 FMAXV_PRED,
103 FMAX_PRED,
104 FMA_PRED,
105 FMINNMV_PRED,
106 FMINNM_PRED,
107 FMINV_PRED,
108 FMIN_PRED,
109 FMOV,
110 FMUL_PRED,
111 FNEARBYINT_MERGE_PASSTHRU,
112 FNEG_MERGE_PASSTHRU,
113 FP_EXTEND_MERGE_PASSTHRU,
114 FP_ROUND_MERGE_PASSTHRU,
115 FRECPE,
116 FRECPS,
117 FRECPX_MERGE_PASSTHRU,
118 FRINT32_MERGE_PASSTHRU,
119 FRINT64_MERGE_PASSTHRU,
120 FRINT_MERGE_PASSTHRU,
121 FROUNDEVEN_MERGE_PASSTHRU,
122 FROUND_MERGE_PASSTHRU,
123 FRSQRTE,
124 FRSQRTS,
125 FSQRT_MERGE_PASSTHRU,
126 FSUB_PRED,
127 FTRUNC32_MERGE_PASSTHRU,
128 FTRUNC64_MERGE_PASSTHRU,
129 FTRUNC_MERGE_PASSTHRU,
130 GET_SME_SAVE_SIZE,
131 GLD1Q_INDEX_MERGE_ZERO,
132 GLD1Q_MERGE_ZERO,
133 GLD1S_IMM_MERGE_ZERO,
134 GLD1S_MERGE_ZERO,
135 GLD1S_SCALED_MERGE_ZERO,
136 GLD1S_SXTW_MERGE_ZERO,
137 GLD1S_SXTW_SCALED_MERGE_ZERO,
138 GLD1S_UXTW_MERGE_ZERO,
139 GLD1S_UXTW_SCALED_MERGE_ZERO,
140 GLD1_IMM_MERGE_ZERO,
141 GLD1_MERGE_ZERO,
142 GLD1_SCALED_MERGE_ZERO,
143 GLD1_SXTW_MERGE_ZERO,
144 GLD1_SXTW_SCALED_MERGE_ZERO,
145 GLD1_UXTW_MERGE_ZERO,
146 GLD1_UXTW_SCALED_MERGE_ZERO,
147 GLDFF1S_IMM_MERGE_ZERO,
148 GLDFF1S_MERGE_ZERO,
149 GLDFF1S_SCALED_MERGE_ZERO,
150 GLDFF1S_SXTW_MERGE_ZERO,
151 GLDFF1S_SXTW_SCALED_MERGE_ZERO,
152 GLDFF1S_UXTW_MERGE_ZERO,
153 GLDFF1S_UXTW_SCALED_MERGE_ZERO,
154 GLDFF1_IMM_MERGE_ZERO,
155 GLDFF1_MERGE_ZERO,
156 GLDFF1_SCALED_MERGE_ZERO,
157 GLDFF1_SXTW_MERGE_ZERO,
158 GLDFF1_SXTW_SCALED_MERGE_ZERO,
159 GLDFF1_UXTW_MERGE_ZERO,
160 GLDFF1_UXTW_SCALED_MERGE_ZERO,
161 GLDNT1S_MERGE_ZERO,
162 GLDNT1_INDEX_MERGE_ZERO,
163 GLDNT1_MERGE_ZERO,
164 HADDS_PRED,
165 HADDU_PRED,
166 INIT_TPIDR2OBJ,
167 INOUT_ZA_USE,
168 INSR,
169 LASTA,
170 LASTB,
171 LD1DUPpost,
172 LD1LANEpost,
173 LD1RO_MERGE_ZERO,
174 LD1RQ_MERGE_ZERO,
175 LD1S_MERGE_ZERO,
176 LD1_MERGE_ZERO,
177 LD1x2post,
178 LD1x3post,
179 LD1x4post,
180 LD2DUPpost,
181 LD2LANEpost,
182 LD2post,
183 LD3DUPpost,
184 LD3LANEpost,
185 LD3post,
186 LD4DUPpost,
187 LD4LANEpost,
188 LD4post,
189 LDFF1S_MERGE_ZERO,
190 LDFF1_MERGE_ZERO,
191 LDIAPP,
192 LDNF1S_MERGE_ZERO,
193 LDNF1_MERGE_ZERO,
194 LDNP,
195 LDP,
196 LOADgot,
197 LS64_BUILD,
198 LS64_EXTRACT,
199 MOVI,
200 MOVIedit,
201 MOVImsl,
202 MOVIshift,
203 MRRS,
204 MRS,
205 MSRR,
206 MULHS_PRED,
207 MULHU_PRED,
208 MUL_PRED,
209 MVNImsl,
210 MVNIshift,
211 NEG_MERGE_PASSTHRU,
212 NVCAST,
213 ORRi,
214 ORV_PRED,
215 PMULL,
216 PREFETCH,
217 PROBED_ALLOCA,
218 PTEST,
219 PTEST_ANY,
220 PTEST_FIRST,
221 PTRUE,
222 RANGE_PREFETCH,
223 RDSVL,
224 REINTERPRET_CAST,
225 REQUIRES_ZA_SAVE,
226 REQUIRES_ZT0_SAVE,
227 RESTORE_ZA,
228 RESTORE_ZT,
229 RET_GLUE,
230 REV16,
231 REV32,
232 REV64,
233 REVD_MERGE_PASSTHRU,
234 REVH_MERGE_PASSTHRU,
235 REVW_MERGE_PASSTHRU,
236 RHADDS_PRED,
237 RHADDU_PRED,
238 RSHRNB_I,
239 SADDLP,
240 SADDLV,
241 SADDV,
242 SADDV_PRED,
243 SADDWB,
244 SADDWT,
245 SAVE_ZT,
246 SBC,
247 SBCS,
248 SDIV_PRED,
249 SDOT,
250 SETCC_MERGE_ZERO,
251 SHL_PRED,
252 SIGN_EXTEND_INREG_MERGE_PASSTHRU,
253 SINT_TO_FP_MERGE_PASSTHRU,
254 SITOF,
255 SMAXV,
256 SMAXV_PRED,
257 SMAX_PRED,
258 SME_STATE_ALLOC,
259 SME_ZA_LDR,
260 SME_ZA_STR,
261 SMINV,
262 SMINV_PRED,
263 SMIN_PRED,
264 SMSTART,
265 SMSTOP,
266 SMULL,
267 SPLICE,
268 SQABS,
269 SQADD,
270 SQDMULH,
271 SQDMULL,
272 SQNEG,
273 SQRDMLAH,
274 SQRDMLSH,
275 SQRDMULH,
276 SQRSHL,
277 SQRSHRN,
278 SQRSHRUN,
279 SQSHL,
280 SQSHLU_I,
281 SQSHL_I,
282 SQSHRN,
283 SQSHRUN,
284 SQSUB,
285 SRA_PRED,
286 SRL_PRED,
287 SRSHR_I,
288 SST1Q_INDEX_PRED,
289 SST1Q_PRED,
290 SST1_IMM_PRED,
291 SST1_PRED,
292 SST1_SCALED_PRED,
293 SST1_SXTW_PRED,
294 SST1_SXTW_SCALED_PRED,
295 SST1_UXTW_PRED,
296 SST1_UXTW_SCALED_PRED,
297 SSTNT1_INDEX_PRED,
298 SSTNT1_PRED,
299 ST1_PRED,
300 ST1x2post,
301 ST1x3post,
302 ST1x4post,
303 ST2G,
304 ST2LANEpost,
305 ST2post,
306 ST3LANEpost,
307 ST3post,
308 ST4LANEpost,
309 ST4post,
310 STG,
311 STILP,
312 STNP,
313 STP,
314 STRICT_FCMP,
315 STRICT_FCMPE,
316 STZ2G,
317 STZG,
318 SUBS,
319 SUNPKHI,
320 SUNPKLO,
321 SUQADD,
322 TBL,
323 TBNZ,
324 TBZ,
325 TC_RETURN,
326 THREAD_POINTER,
327 TLSDESC_AUTH_CALLSEQ,
328 TLSDESC_CALLSEQ,
329 TRN1,
330 TRN2,
331 UADDLP,
332 UADDLV,
333 UADDV,
334 UADDV_PRED,
335 UADDWB,
336 UADDWT,
337 UDIV_PRED,
338 UDOT,
339 UINT_TO_FP_MERGE_PASSTHRU,
340 UITOF,
341 UMAXV,
342 UMAXV_PRED,
343 UMAX_PRED,
344 UMINV,
345 UMINV_PRED,
346 UMIN_PRED,
347 UMULL,
348 UQADD,
349 UQRSHL,
350 UQRSHRN,
351 UQSHL,
352 UQSHL_I,
353 UQSHRN,
354 UQSUB,
355 URSHR_I,
356 URSHR_I_PRED,
357 USDOT,
358 USQADD,
359 UUNPKHI,
360 UUNPKLO,
361 UZP1,
362 UZP2,
363 VASHR,
364 VLSHR,
365 VSHL,
366 VSLI,
367 VSRI,
368 WrapperLarge,
369 ZERO_EXTEND_INREG_MERGE_PASSTHRU,
370 ZIP1,
371 ZIP2,
372};
373
374static constexpr unsigned GENERATED_OPCODE_END = ZIP2 + 1;
375
376} // namespace llvm::AArch64ISD
377
378#endif // GET_SDNODE_ENUM
379
380#ifdef GET_SDNODE_DESC
381#undef GET_SDNODE_DESC
382
383namespace llvm {
384
385
386#ifdef __GNUC__
387#pragma GCC diagnostic push
388#pragma GCC diagnostic ignored "-Woverlength-strings"
389#endif
390static constexpr char AArch64SDNodeNamesStorage[] =
391 "\0"
392 "AArch64ISD::ABDS_PRED\0"
393 "AArch64ISD::ABDU_PRED\0"
394 "AArch64ISD::ABS_MERGE_PASSTHRU\0"
395 "AArch64ISD::ADC\0"
396 "AArch64ISD::ADCS\0"
397 "AArch64ISD::ADDP\0"
398 "AArch64ISD::ADDS\0"
399 "AArch64ISD::ADDlow\0"
400 "AArch64ISD::ADR\0"
401 "AArch64ISD::ADRP\0"
402 "AArch64ISD::ALLOCATE_ZA_BUFFER\0"
403 "AArch64ISD::ALLOC_SME_SAVE_BUFFER\0"
404 "AArch64ISD::ANDS\0"
405 "AArch64ISD::ANDV_PRED\0"
406 "AArch64ISD::ASRD_MERGE_OP1\0"
407 "AArch64ISD::ASSERT_ZEXT_BOOL\0"
408 "AArch64ISD::AUTH_CALL\0"
409 "AArch64ISD::AUTH_CALL_RVMARKER\0"
410 "AArch64ISD::AUTH_TC_RETURN\0"
411 "AArch64ISD::BIC\0"
412 "AArch64ISD::BICi\0"
413 "AArch64ISD::BITREVERSE_MERGE_PASSTHRU\0"
414 "AArch64ISD::BRCOND\0"
415 "AArch64ISD::BSP\0"
416 "AArch64ISD::BSWAP_MERGE_PASSTHRU\0"
417 "AArch64ISD::CALL\0"
418 "AArch64ISD::CALL_ARM64EC_TO_X64\0"
419 "AArch64ISD::CALL_BTI\0"
420 "AArch64ISD::CALL_RVMARKER\0"
421 "AArch64ISD::CB\0"
422 "AArch64ISD::CBNZ\0"
423 "AArch64ISD::CBZ\0"
424 "AArch64ISD::CCMN\0"
425 "AArch64ISD::CCMP\0"
426 "AArch64ISD::CHECK_MATCHING_VL\0"
427 "AArch64ISD::CLASTA_N\0"
428 "AArch64ISD::CLASTB_N\0"
429 "AArch64ISD::COALESCER_BARRIER\0"
430 "AArch64ISD::COND_SMSTART\0"
431 "AArch64ISD::COND_SMSTOP\0"
432 "AArch64ISD::CSEL\0"
433 "AArch64ISD::CSINC\0"
434 "AArch64ISD::CSINV\0"
435 "AArch64ISD::CSNEG\0"
436 "AArch64ISD::CTLZ_MERGE_PASSTHRU\0"
437 "AArch64ISD::CTPOP_MERGE_PASSTHRU\0"
438 "AArch64ISD::CTTZ_ELTS\0"
439 "AArch64ISD::DUP\0"
440 "AArch64ISD::DUPLANE128\0"
441 "AArch64ISD::DUPLANE16\0"
442 "AArch64ISD::DUPLANE32\0"
443 "AArch64ISD::DUPLANE64\0"
444 "AArch64ISD::DUPLANE8\0"
445 "AArch64ISD::DUP_MERGE_PASSTHRU\0"
446 "AArch64ISD::ENTRY_PSTATE_SM\0"
447 "AArch64ISD::EORV_PRED\0"
448 "AArch64ISD::EXT\0"
449 "AArch64ISD::EXTR\0"
450 "AArch64ISD::FABS_MERGE_PASSTHRU\0"
451 "AArch64ISD::FADDA_PRED\0"
452 "AArch64ISD::FADDV_PRED\0"
453 "AArch64ISD::FADD_PRED\0"
454 "AArch64ISD::FCCMP\0"
455 "AArch64ISD::FCEIL_MERGE_PASSTHRU\0"
456 "AArch64ISD::FCMEQ\0"
457 "AArch64ISD::FCMGE\0"
458 "AArch64ISD::FCMGT\0"
459 "AArch64ISD::FCMP\0"
460 "AArch64ISD::FCVTAS_HALF\0"
461 "AArch64ISD::FCVTAU_HALF\0"
462 "AArch64ISD::FCVTMS_HALF\0"
463 "AArch64ISD::FCVTMU_HALF\0"
464 "AArch64ISD::FCVTNS_HALF\0"
465 "AArch64ISD::FCVTNU_HALF\0"
466 "AArch64ISD::FCVTPS_HALF\0"
467 "AArch64ISD::FCVTPU_HALF\0"
468 "AArch64ISD::FCVTXN\0"
469 "AArch64ISD::FCVTX_MERGE_PASSTHRU\0"
470 "AArch64ISD::FCVTZS_HALF\0"
471 "AArch64ISD::FCVTZS_MERGE_PASSTHRU\0"
472 "AArch64ISD::FCVTZU_HALF\0"
473 "AArch64ISD::FCVTZU_MERGE_PASSTHRU\0"
474 "AArch64ISD::FDIV_PRED\0"
475 "AArch64ISD::FFLOOR_MERGE_PASSTHRU\0"
476 "AArch64ISD::FMAXNMV_PRED\0"
477 "AArch64ISD::FMAXNM_PRED\0"
478 "AArch64ISD::FMAXV_PRED\0"
479 "AArch64ISD::FMAX_PRED\0"
480 "AArch64ISD::FMA_PRED\0"
481 "AArch64ISD::FMINNMV_PRED\0"
482 "AArch64ISD::FMINNM_PRED\0"
483 "AArch64ISD::FMINV_PRED\0"
484 "AArch64ISD::FMIN_PRED\0"
485 "AArch64ISD::FMOV\0"
486 "AArch64ISD::FMUL_PRED\0"
487 "AArch64ISD::FNEARBYINT_MERGE_PASSTHRU\0"
488 "AArch64ISD::FNEG_MERGE_PASSTHRU\0"
489 "AArch64ISD::FP_EXTEND_MERGE_PASSTHRU\0"
490 "AArch64ISD::FP_ROUND_MERGE_PASSTHRU\0"
491 "AArch64ISD::FRECPE\0"
492 "AArch64ISD::FRECPS\0"
493 "AArch64ISD::FRECPX_MERGE_PASSTHRU\0"
494 "AArch64ISD::FRINT32_MERGE_PASSTHRU\0"
495 "AArch64ISD::FRINT64_MERGE_PASSTHRU\0"
496 "AArch64ISD::FRINT_MERGE_PASSTHRU\0"
497 "AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU\0"
498 "AArch64ISD::FROUND_MERGE_PASSTHRU\0"
499 "AArch64ISD::FRSQRTE\0"
500 "AArch64ISD::FRSQRTS\0"
501 "AArch64ISD::FSQRT_MERGE_PASSTHRU\0"
502 "AArch64ISD::FSUB_PRED\0"
503 "AArch64ISD::FTRUNC32_MERGE_PASSTHRU\0"
504 "AArch64ISD::FTRUNC64_MERGE_PASSTHRU\0"
505 "AArch64ISD::FTRUNC_MERGE_PASSTHRU\0"
506 "AArch64ISD::GET_SME_SAVE_SIZE\0"
507 "AArch64ISD::GLD1Q_INDEX_MERGE_ZERO\0"
508 "AArch64ISD::GLD1Q_MERGE_ZERO\0"
509 "AArch64ISD::GLD1S_IMM_MERGE_ZERO\0"
510 "AArch64ISD::GLD1S_MERGE_ZERO\0"
511 "AArch64ISD::GLD1S_SCALED_MERGE_ZERO\0"
512 "AArch64ISD::GLD1S_SXTW_MERGE_ZERO\0"
513 "AArch64ISD::GLD1S_SXTW_SCALED_MERGE_ZERO\0"
514 "AArch64ISD::GLD1S_UXTW_MERGE_ZERO\0"
515 "AArch64ISD::GLD1S_UXTW_SCALED_MERGE_ZERO\0"
516 "AArch64ISD::GLD1_IMM_MERGE_ZERO\0"
517 "AArch64ISD::GLD1_MERGE_ZERO\0"
518 "AArch64ISD::GLD1_SCALED_MERGE_ZERO\0"
519 "AArch64ISD::GLD1_SXTW_MERGE_ZERO\0"
520 "AArch64ISD::GLD1_SXTW_SCALED_MERGE_ZERO\0"
521 "AArch64ISD::GLD1_UXTW_MERGE_ZERO\0"
522 "AArch64ISD::GLD1_UXTW_SCALED_MERGE_ZERO\0"
523 "AArch64ISD::GLDFF1S_IMM_MERGE_ZERO\0"
524 "AArch64ISD::GLDFF1S_MERGE_ZERO\0"
525 "AArch64ISD::GLDFF1S_SCALED_MERGE_ZERO\0"
526 "AArch64ISD::GLDFF1S_SXTW_MERGE_ZERO\0"
527 "AArch64ISD::GLDFF1S_SXTW_SCALED_MERGE_ZERO\0"
528 "AArch64ISD::GLDFF1S_UXTW_MERGE_ZERO\0"
529 "AArch64ISD::GLDFF1S_UXTW_SCALED_MERGE_ZERO\0"
530 "AArch64ISD::GLDFF1_IMM_MERGE_ZERO\0"
531 "AArch64ISD::GLDFF1_MERGE_ZERO\0"
532 "AArch64ISD::GLDFF1_SCALED_MERGE_ZERO\0"
533 "AArch64ISD::GLDFF1_SXTW_MERGE_ZERO\0"
534 "AArch64ISD::GLDFF1_SXTW_SCALED_MERGE_ZERO\0"
535 "AArch64ISD::GLDFF1_UXTW_MERGE_ZERO\0"
536 "AArch64ISD::GLDFF1_UXTW_SCALED_MERGE_ZERO\0"
537 "AArch64ISD::GLDNT1S_MERGE_ZERO\0"
538 "AArch64ISD::GLDNT1_INDEX_MERGE_ZERO\0"
539 "AArch64ISD::GLDNT1_MERGE_ZERO\0"
540 "AArch64ISD::HADDS_PRED\0"
541 "AArch64ISD::HADDU_PRED\0"
542 "AArch64ISD::INIT_TPIDR2OBJ\0"
543 "AArch64ISD::INOUT_ZA_USE\0"
544 "AArch64ISD::INSR\0"
545 "AArch64ISD::LASTA\0"
546 "AArch64ISD::LASTB\0"
547 "AArch64ISD::LD1DUPpost\0"
548 "AArch64ISD::LD1LANEpost\0"
549 "AArch64ISD::LD1RO_MERGE_ZERO\0"
550 "AArch64ISD::LD1RQ_MERGE_ZERO\0"
551 "AArch64ISD::LD1S_MERGE_ZERO\0"
552 "AArch64ISD::LD1_MERGE_ZERO\0"
553 "AArch64ISD::LD1x2post\0"
554 "AArch64ISD::LD1x3post\0"
555 "AArch64ISD::LD1x4post\0"
556 "AArch64ISD::LD2DUPpost\0"
557 "AArch64ISD::LD2LANEpost\0"
558 "AArch64ISD::LD2post\0"
559 "AArch64ISD::LD3DUPpost\0"
560 "AArch64ISD::LD3LANEpost\0"
561 "AArch64ISD::LD3post\0"
562 "AArch64ISD::LD4DUPpost\0"
563 "AArch64ISD::LD4LANEpost\0"
564 "AArch64ISD::LD4post\0"
565 "AArch64ISD::LDFF1S_MERGE_ZERO\0"
566 "AArch64ISD::LDFF1_MERGE_ZERO\0"
567 "AArch64ISD::LDIAPP\0"
568 "AArch64ISD::LDNF1S_MERGE_ZERO\0"
569 "AArch64ISD::LDNF1_MERGE_ZERO\0"
570 "AArch64ISD::LDNP\0"
571 "AArch64ISD::LDP\0"
572 "AArch64ISD::LOADgot\0"
573 "AArch64ISD::LS64_BUILD\0"
574 "AArch64ISD::LS64_EXTRACT\0"
575 "AArch64ISD::MOVI\0"
576 "AArch64ISD::MOVIedit\0"
577 "AArch64ISD::MOVImsl\0"
578 "AArch64ISD::MOVIshift\0"
579 "AArch64ISD::MRRS\0"
580 "AArch64ISD::MRS\0"
581 "AArch64ISD::MSRR\0"
582 "AArch64ISD::MULHS_PRED\0"
583 "AArch64ISD::MULHU_PRED\0"
584 "AArch64ISD::MUL_PRED\0"
585 "AArch64ISD::MVNImsl\0"
586 "AArch64ISD::MVNIshift\0"
587 "AArch64ISD::NEG_MERGE_PASSTHRU\0"
588 "AArch64ISD::NVCAST\0"
589 "AArch64ISD::ORRi\0"
590 "AArch64ISD::ORV_PRED\0"
591 "AArch64ISD::PMULL\0"
592 "AArch64ISD::PREFETCH\0"
593 "AArch64ISD::PROBED_ALLOCA\0"
594 "AArch64ISD::PTEST\0"
595 "AArch64ISD::PTEST_ANY\0"
596 "AArch64ISD::PTEST_FIRST\0"
597 "AArch64ISD::PTRUE\0"
598 "AArch64ISD::RANGE_PREFETCH\0"
599 "AArch64ISD::RDSVL\0"
600 "AArch64ISD::REINTERPRET_CAST\0"
601 "AArch64ISD::REQUIRES_ZA_SAVE\0"
602 "AArch64ISD::REQUIRES_ZT0_SAVE\0"
603 "AArch64ISD::RESTORE_ZA\0"
604 "AArch64ISD::RESTORE_ZT\0"
605 "AArch64ISD::RET_GLUE\0"
606 "AArch64ISD::REV16\0"
607 "AArch64ISD::REV32\0"
608 "AArch64ISD::REV64\0"
609 "AArch64ISD::REVD_MERGE_PASSTHRU\0"
610 "AArch64ISD::REVH_MERGE_PASSTHRU\0"
611 "AArch64ISD::REVW_MERGE_PASSTHRU\0"
612 "AArch64ISD::RHADDS_PRED\0"
613 "AArch64ISD::RHADDU_PRED\0"
614 "AArch64ISD::RSHRNB_I\0"
615 "AArch64ISD::SADDLP\0"
616 "AArch64ISD::SADDLV\0"
617 "AArch64ISD::SADDV\0"
618 "AArch64ISD::SADDV_PRED\0"
619 "AArch64ISD::SADDWB\0"
620 "AArch64ISD::SADDWT\0"
621 "AArch64ISD::SAVE_ZT\0"
622 "AArch64ISD::SBC\0"
623 "AArch64ISD::SBCS\0"
624 "AArch64ISD::SDIV_PRED\0"
625 "AArch64ISD::SDOT\0"
626 "AArch64ISD::SETCC_MERGE_ZERO\0"
627 "AArch64ISD::SHL_PRED\0"
628 "AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU\0"
629 "AArch64ISD::SINT_TO_FP_MERGE_PASSTHRU\0"
630 "AArch64ISD::SITOF\0"
631 "AArch64ISD::SMAXV\0"
632 "AArch64ISD::SMAXV_PRED\0"
633 "AArch64ISD::SMAX_PRED\0"
634 "AArch64ISD::SME_STATE_ALLOC\0"
635 "AArch64ISD::SME_ZA_LDR\0"
636 "AArch64ISD::SME_ZA_STR\0"
637 "AArch64ISD::SMINV\0"
638 "AArch64ISD::SMINV_PRED\0"
639 "AArch64ISD::SMIN_PRED\0"
640 "AArch64ISD::SMSTART\0"
641 "AArch64ISD::SMSTOP\0"
642 "AArch64ISD::SMULL\0"
643 "AArch64ISD::SPLICE\0"
644 "AArch64ISD::SQABS\0"
645 "AArch64ISD::SQADD\0"
646 "AArch64ISD::SQDMULH\0"
647 "AArch64ISD::SQDMULL\0"
648 "AArch64ISD::SQNEG\0"
649 "AArch64ISD::SQRDMLAH\0"
650 "AArch64ISD::SQRDMLSH\0"
651 "AArch64ISD::SQRDMULH\0"
652 "AArch64ISD::SQRSHL\0"
653 "AArch64ISD::SQRSHRN\0"
654 "AArch64ISD::SQRSHRUN\0"
655 "AArch64ISD::SQSHL\0"
656 "AArch64ISD::SQSHLU_I\0"
657 "AArch64ISD::SQSHL_I\0"
658 "AArch64ISD::SQSHRN\0"
659 "AArch64ISD::SQSHRUN\0"
660 "AArch64ISD::SQSUB\0"
661 "AArch64ISD::SRA_PRED\0"
662 "AArch64ISD::SRL_PRED\0"
663 "AArch64ISD::SRSHR_I\0"
664 "AArch64ISD::SST1Q_INDEX_PRED\0"
665 "AArch64ISD::SST1Q_PRED\0"
666 "AArch64ISD::SST1_IMM_PRED\0"
667 "AArch64ISD::SST1_PRED\0"
668 "AArch64ISD::SST1_SCALED_PRED\0"
669 "AArch64ISD::SST1_SXTW_PRED\0"
670 "AArch64ISD::SST1_SXTW_SCALED_PRED\0"
671 "AArch64ISD::SST1_UXTW_PRED\0"
672 "AArch64ISD::SST1_UXTW_SCALED_PRED\0"
673 "AArch64ISD::SSTNT1_INDEX_PRED\0"
674 "AArch64ISD::SSTNT1_PRED\0"
675 "AArch64ISD::ST1_PRED\0"
676 "AArch64ISD::ST1x2post\0"
677 "AArch64ISD::ST1x3post\0"
678 "AArch64ISD::ST1x4post\0"
679 "AArch64ISD::ST2G\0"
680 "AArch64ISD::ST2LANEpost\0"
681 "AArch64ISD::ST2post\0"
682 "AArch64ISD::ST3LANEpost\0"
683 "AArch64ISD::ST3post\0"
684 "AArch64ISD::ST4LANEpost\0"
685 "AArch64ISD::ST4post\0"
686 "AArch64ISD::STG\0"
687 "AArch64ISD::STILP\0"
688 "AArch64ISD::STNP\0"
689 "AArch64ISD::STP\0"
690 "AArch64ISD::STRICT_FCMP\0"
691 "AArch64ISD::STRICT_FCMPE\0"
692 "AArch64ISD::STZ2G\0"
693 "AArch64ISD::STZG\0"
694 "AArch64ISD::SUBS\0"
695 "AArch64ISD::SUNPKHI\0"
696 "AArch64ISD::SUNPKLO\0"
697 "AArch64ISD::SUQADD\0"
698 "AArch64ISD::TBL\0"
699 "AArch64ISD::TBNZ\0"
700 "AArch64ISD::TBZ\0"
701 "AArch64ISD::TC_RETURN\0"
702 "AArch64ISD::THREAD_POINTER\0"
703 "AArch64ISD::TLSDESC_AUTH_CALLSEQ\0"
704 "AArch64ISD::TLSDESC_CALLSEQ\0"
705 "AArch64ISD::TRN1\0"
706 "AArch64ISD::TRN2\0"
707 "AArch64ISD::UADDLP\0"
708 "AArch64ISD::UADDLV\0"
709 "AArch64ISD::UADDV\0"
710 "AArch64ISD::UADDV_PRED\0"
711 "AArch64ISD::UADDWB\0"
712 "AArch64ISD::UADDWT\0"
713 "AArch64ISD::UDIV_PRED\0"
714 "AArch64ISD::UDOT\0"
715 "AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU\0"
716 "AArch64ISD::UITOF\0"
717 "AArch64ISD::UMAXV\0"
718 "AArch64ISD::UMAXV_PRED\0"
719 "AArch64ISD::UMAX_PRED\0"
720 "AArch64ISD::UMINV\0"
721 "AArch64ISD::UMINV_PRED\0"
722 "AArch64ISD::UMIN_PRED\0"
723 "AArch64ISD::UMULL\0"
724 "AArch64ISD::UQADD\0"
725 "AArch64ISD::UQRSHL\0"
726 "AArch64ISD::UQRSHRN\0"
727 "AArch64ISD::UQSHL\0"
728 "AArch64ISD::UQSHL_I\0"
729 "AArch64ISD::UQSHRN\0"
730 "AArch64ISD::UQSUB\0"
731 "AArch64ISD::URSHR_I\0"
732 "AArch64ISD::URSHR_I_PRED\0"
733 "AArch64ISD::USDOT\0"
734 "AArch64ISD::USQADD\0"
735 "AArch64ISD::UUNPKHI\0"
736 "AArch64ISD::UUNPKLO\0"
737 "AArch64ISD::UZP1\0"
738 "AArch64ISD::UZP2\0"
739 "AArch64ISD::VASHR\0"
740 "AArch64ISD::VLSHR\0"
741 "AArch64ISD::VSHL\0"
742 "AArch64ISD::VSLI\0"
743 "AArch64ISD::VSRI\0"
744 "AArch64ISD::WrapperLarge\0"
745 "AArch64ISD::ZERO_EXTEND_INREG_MERGE_PASSTHRU\0"
746 "AArch64ISD::ZIP1\0"
747 "AArch64ISD::ZIP2\0"
748 ;
749#ifdef __GNUC__
750#pragma GCC diagnostic pop
751#endif
752
753static constexpr llvm::StringTable
754AArch64SDNodeNames = AArch64SDNodeNamesStorage;
755
756static const VTByHwModePair AArch64VTByHwModeTable[] = {
757 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
758};
759
760static const SDTypeConstraint AArch64SDTypeConstraints[] = {
761 /* 0 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::Other},
762 /* 3 */ {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
763 /* 6 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
764 /* 12 */ {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
765 /* 16 */ {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
766 /* 22 */ {SDTCisSameAs, 2, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
767 /* 25 */ {SDTCisSameAs, 2, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
768 /* 28 */ {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i64},
769 /* 31 */ {SDTCisSameAs, 1, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i64},
770 /* 36 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i64},
771 /* 39 */ {SDTCisVT, 1, 0, 0, MVT::i64}, {SDTCisVT, 0, 0, 0, MVT::i64},
772 /* 41 */ {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::v2i64},
773 /* 44 */ {SDTCisVT, 3, 0, 0, MVT::i64}, {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
774 /* 48 */ {SDTCisVT, 5, 0, 0, MVT::i64}, {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
775 /* 54 */ {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
776 /* 56 */ {SDTCisVT, 4, 0, 0, MVT::i64}, {SDTCisVT, 3, 0, 0, MVT::i64}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
777 /* 60 */ {SDTCisVT, 1, 0, 0, MVT::Other}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
778 /* 62 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
779 /* 65 */ {SDTCisSameAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
780 /* 68 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
781 /* 71 */ {SDTCisOpSmallerThanOp, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
782 /* 74 */ {SDTCisVT, 2, 0, 0, MVT::Other}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
783 /* 77 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
784 /* 80 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
785 /* 83 */ {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
786 /* 85 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
787 /* 89 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
788 /* 93 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisOpSmallerThanOp, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
789 /* 98 */ {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
790 /* 102 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
791 /* 106 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
792 /* 110 */ {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
793 /* 114 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
794 /* 119 */ {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
795 /* 121 */ {SDTCisSameNumEltsAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 2, 0, 0, MVT::i1}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
796 /* 126 */ {SDTCisSameAs, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisSameNumEltsAs, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
797 /* 133 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
798 /* 136 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
799 /* 141 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
800 /* 148 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
801 /* 153 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVTSmallerThanOp, 3, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
802 /* 162 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
803 /* 169 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
804 /* 176 */ {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
805 /* 182 */ {SDTCisVT, 4, 0, 0, MVT::Other}, {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCVecEltisVT, 0, 0, 0, MVT::i1}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
806 /* 190 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
807 /* 200 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 2, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
808 /* 205 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
809 /* 207 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
810 /* 211 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
811 /* 213 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
812 /* 215 */ {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
813 /* 219 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
814 /* 222 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
815 /* 226 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
816 /* 230 */ {SDTCisPtrTy, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
817 /* 233 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
818 /* 235 */ {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
819 /* 240 */ {SDTCisVT, 2, 0, 0, MVT::i64}, {SDTCisVT, 1, 0, 0, MVT::i64},
820 /* 242 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
821 /* 244 */ {SDTCisSameNumEltsAs, 1, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCVecEltisVT, 1, 0, 0, MVT::i1}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
822 /* 248 */ {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
823 /* 250 */ {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
824};
825
826static const SDNodeDesc AArch64SDNodeDescs[] = {
827 {1, 3, 0, 0, 0, 1, 200, 5}, // ABDS_PRED
828 {1, 3, 0, 0, 0, 23, 200, 5}, // ABDU_PRED
829 {1, 3, 0, 0, 0, 45, 200, 5}, // ABS_MERGE_PASSTHRU
830 {1, 3, 0, 0, 0, 76, 215, 4}, // ADC
831 {2, 3, 0, 0, 0, 92, 235, 5}, // ADCS
832 {1, 2, 0, 0, 0, 109, 99, 3}, // ADDP
833 {2, 2, 0, 0, 0, 126, 236, 4}, // ADDS
834 {1, 2, 0, 0, 0, 143, 216, 3}, // ADDlow
835 {1, 1, 0, 0, 0, 162, 211, 2}, // ADR
836 {1, 1, 0, 0, 0, 178, 211, 2}, // ADRP
837 {1, 1, 0|1<<SDNPHasChain, 0, 0, 195, 66, 2}, // ALLOCATE_ZA_BUFFER
838 {1, 1, 0|1<<SDNPHasChain, 0, 0, 226, 66, 2}, // ALLOC_SME_SAVE_BUFFER
839 {2, 2, 0, 0, 0, 260, 236, 4}, // ANDS
840 {1, 2, 0, 0, 0, 277, 248, 2}, // ANDV_PRED
841 {1, 3, 0, 0, 0, 299, 162, 7}, // ASRD_MERGE_OP1
842 {1, 1, 0, 0, 0, 326, 65, 3}, // ASSERT_ZEXT_BOOL
843 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 355, 44, 4}, // AUTH_CALL
844 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 377, 48, 6}, // AUTH_CALL_RVMARKER
845 {0, 5, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 408, 56, 4}, // AUTH_TC_RETURN
846 {1, 2, 0, 0, 0, 435, 148, 5}, // BIC
847 {1, 3, 0, 0, 0, 451, 106, 4}, // BICi
848 {1, 3, 0, 0, 0, 468, 200, 5}, // BITREVERSE_MERGE_PASSTHRU
849 {0, 3, 0|1<<SDNPHasChain, 0, 0, 506, 0, 3}, // BRCOND
850 {1, 3, 0, 0, 0, 525, 98, 4}, // BSP
851 {1, 3, 0, 0, 0, 541, 200, 5}, // BSWAP_MERGE_PASSTHRU
852 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 574, 47, 1}, // CALL
853 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 591, 47, 1}, // CALL_ARM64EC_TO_X64
854 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 623, 47, 1}, // CALL_BTI
855 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 644, 47, 1}, // CALL_RVMARKER
856 {0, 4, 0|1<<SDNPHasChain, 0, 0, 670, 12, 4}, // CB
857 {0, 2, 0|1<<SDNPHasChain, 0, 0, 685, 60, 2}, // CBNZ
858 {0, 2, 0|1<<SDNPHasChain, 0, 0, 702, 60, 2}, // CBZ
859 {1, 5, 0, 0, 0, 718, 6, 6}, // CCMN
860 {1, 5, 0, 0, 0, 735, 6, 6}, // CCMP
861 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 752, 0, 0}, // CHECK_MATCHING_VL
862 {1, 3, 0, 0, 0, 782, 244, 4}, // CLASTA_N
863 {1, 3, 0, 0, 0, 803, 244, 4}, // CLASTB_N
864 {1, 1, 0|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 824, 0, 0}, // COALESCER_BARRIER
865 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 854, 77, 3}, // COND_SMSTART
866 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 879, 77, 3}, // COND_SMSTOP
867 {1, 4, 0, 0, 0, 903, 226, 4}, // CSEL
868 {1, 4, 0, 0, 0, 920, 226, 4}, // CSINC
869 {1, 4, 0, 0, 0, 938, 226, 4}, // CSINV
870 {1, 4, 0, 0, 0, 956, 226, 4}, // CSNEG
871 {1, 3, 0, 0, 0, 974, 200, 5}, // CTLZ_MERGE_PASSTHRU
872 {1, 3, 0, 0, 0, 1006, 200, 5}, // CTPOP_MERGE_PASSTHRU
873 {1, 2, 0, 0, 0, 1039, 80, 3}, // CTTZ_ELTS
874 {1, 1, 0, 0, 0, 1061, 101, 1}, // DUP
875 {1, 2, 0, 0, 0, 1077, 205, 2}, // DUPLANE128
876 {1, 2, 0, 0, 0, 1100, 205, 2}, // DUPLANE16
877 {1, 2, 0, 0, 0, 1122, 205, 2}, // DUPLANE32
878 {1, 2, 0, 0, 0, 1144, 205, 2}, // DUPLANE64
879 {1, 2, 0, 0, 0, 1166, 205, 2}, // DUPLANE8
880 {1, 3, 0, 0, 0, 1187, 114, 5}, // DUP_MERGE_PASSTHRU
881 {1, 0, 0|1<<SDNPHasChain, 0, 0, 1218, 61, 1}, // ENTRY_PSTATE_SM
882 {1, 2, 0, 0, 0, 1246, 248, 2}, // EORV_PRED
883 {1, 3, 0, 0, 0, 1268, 102, 4}, // EXT
884 {1, 3, 0, 0, 0, 1284, 230, 3}, // EXTR
885 {1, 3, 0, 0, 0, 1301, 200, 5}, // FABS_MERGE_PASSTHRU
886 {1, 3, 0, 0, 0, 1333, 244, 4}, // FADDA_PRED
887 {1, 2, 0, 0, 0, 1356, 248, 2}, // FADDV_PRED
888 {1, 3, 0, 0, 0, 1379, 200, 5}, // FADD_PRED
889 {1, 5, 0, 0, 0, 1401, 16, 6}, // FCCMP
890 {1, 3, 0, 0, 0, 1419, 200, 5}, // FCEIL_MERGE_PASSTHRU
891 {1, 2, 0, 0, 0, 1452, 252, 1}, // FCMEQ
892 {1, 2, 0, 0, 0, 1470, 252, 1}, // FCMGE
893 {1, 2, 0, 0, 0, 1488, 252, 1}, // FCMGT
894 {1, 2, 0, 0, 0, 1506, 22, 3}, // FCMP
895 {1, 1, 0, 0, 0, 1523, 89, 4}, // FCVTAS_HALF
896 {1, 1, 0, 0, 0, 1547, 89, 4}, // FCVTAU_HALF
897 {1, 1, 0, 0, 0, 1571, 89, 4}, // FCVTMS_HALF
898 {1, 1, 0, 0, 0, 1595, 89, 4}, // FCVTMU_HALF
899 {1, 1, 0, 0, 0, 1619, 89, 4}, // FCVTNS_HALF
900 {1, 1, 0, 0, 0, 1643, 89, 4}, // FCVTNU_HALF
901 {1, 1, 0, 0, 0, 1667, 89, 4}, // FCVTPS_HALF
902 {1, 1, 0, 0, 0, 1691, 89, 4}, // FCVTPU_HALF
903 {1, 1, 0, 0, 0, 1715, 85, 4}, // FCVTXN
904 {1, 3, 0, 0, 0, 1734, 126, 7}, // FCVTX_MERGE_PASSTHRU
905 {1, 1, 0, 0, 0, 1767, 89, 4}, // FCVTZS_HALF
906 {1, 3, 0, 0, 0, 1791, 126, 7}, // FCVTZS_MERGE_PASSTHRU
907 {1, 1, 0, 0, 0, 1825, 89, 4}, // FCVTZU_HALF
908 {1, 3, 0, 0, 0, 1849, 126, 7}, // FCVTZU_MERGE_PASSTHRU
909 {1, 3, 0, 0, 0, 1883, 200, 5}, // FDIV_PRED
910 {1, 3, 0, 0, 0, 1905, 200, 5}, // FFLOOR_MERGE_PASSTHRU
911 {1, 2, 0, 0, 0, 1939, 248, 2}, // FMAXNMV_PRED
912 {1, 3, 0, 0, 0, 1964, 200, 5}, // FMAXNM_PRED
913 {1, 2, 0, 0, 0, 1988, 248, 2}, // FMAXV_PRED
914 {1, 3, 0, 0, 0, 2011, 200, 5}, // FMAX_PRED
915 {1, 4, 0, 0, 0, 2033, 190, 10}, // FMA_PRED
916 {1, 2, 0, 0, 0, 2054, 248, 2}, // FMINNMV_PRED
917 {1, 3, 0, 0, 0, 2079, 200, 5}, // FMINNM_PRED
918 {1, 2, 0, 0, 0, 2103, 248, 2}, // FMINV_PRED
919 {1, 3, 0, 0, 0, 2126, 200, 5}, // FMIN_PRED
920 {1, 1, 0, 0, 0, 2148, 243, 1}, // FMOV
921 {1, 3, 0, 0, 0, 2165, 200, 5}, // FMUL_PRED
922 {1, 3, 0, 0, 0, 2187, 200, 5}, // FNEARBYINT_MERGE_PASSTHRU
923 {1, 3, 0, 0, 0, 2225, 200, 5}, // FNEG_MERGE_PASSTHRU
924 {1, 3, 0, 0, 0, 2257, 126, 7}, // FP_EXTEND_MERGE_PASSTHRU
925 {1, 4, 0, 0, 0, 2294, 176, 6}, // FP_ROUND_MERGE_PASSTHRU
926 {1, 1, 0, 0, 0, 2330, 213, 2}, // FRECPE
927 {1, 2, 0, 0, 0, 2349, 219, 3}, // FRECPS
928 {1, 3, 0, 0, 0, 2368, 200, 5}, // FRECPX_MERGE_PASSTHRU
929 {1, 3, 0, 0, 0, 2402, 200, 5}, // FRINT32_MERGE_PASSTHRU
930 {1, 3, 0, 0, 0, 2437, 200, 5}, // FRINT64_MERGE_PASSTHRU
931 {1, 3, 0, 0, 0, 2472, 200, 5}, // FRINT_MERGE_PASSTHRU
932 {1, 3, 0, 0, 0, 2505, 200, 5}, // FROUNDEVEN_MERGE_PASSTHRU
933 {1, 3, 0, 0, 0, 2543, 200, 5}, // FROUND_MERGE_PASSTHRU
934 {1, 1, 0, 0, 0, 2577, 213, 2}, // FRSQRTE
935 {1, 2, 0, 0, 0, 2597, 219, 3}, // FRSQRTS
936 {1, 3, 0, 0, 0, 2617, 200, 5}, // FSQRT_MERGE_PASSTHRU
937 {1, 3, 0, 0, 0, 2650, 200, 5}, // FSUB_PRED
938 {1, 3, 0, 0, 0, 2672, 200, 5}, // FTRUNC32_MERGE_PASSTHRU
939 {1, 3, 0, 0, 0, 2708, 200, 5}, // FTRUNC64_MERGE_PASSTHRU
940 {1, 3, 0, 0, 0, 2744, 200, 5}, // FTRUNC_MERGE_PASSTHRU
941 {1, 0, 0|1<<SDNPHasChain, 0, 0, 2778, 61, 1}, // GET_SME_SAVE_SIZE
942 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2808, 0, 0}, // GLD1Q_INDEX_MERGE_ZERO
943 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2843, 169, 7}, // GLD1Q_MERGE_ZERO
944 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2872, 169, 7}, // GLD1S_IMM_MERGE_ZERO
945 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2905, 141, 7}, // GLD1S_MERGE_ZERO
946 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2934, 141, 7}, // GLD1S_SCALED_MERGE_ZERO
947 {1, 4, 0|1<<SDNPHasChain, 0, 0, 2970, 141, 7}, // GLD1S_SXTW_MERGE_ZERO
948 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3004, 141, 7}, // GLD1S_SXTW_SCALED_MERGE_ZERO
949 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3045, 141, 7}, // GLD1S_UXTW_MERGE_ZERO
950 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3079, 141, 7}, // GLD1S_UXTW_SCALED_MERGE_ZERO
951 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3120, 169, 7}, // GLD1_IMM_MERGE_ZERO
952 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3152, 141, 7}, // GLD1_MERGE_ZERO
953 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3180, 141, 7}, // GLD1_SCALED_MERGE_ZERO
954 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3215, 141, 7}, // GLD1_SXTW_MERGE_ZERO
955 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3248, 141, 7}, // GLD1_SXTW_SCALED_MERGE_ZERO
956 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3288, 141, 7}, // GLD1_UXTW_MERGE_ZERO
957 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3321, 141, 7}, // GLD1_UXTW_SCALED_MERGE_ZERO
958 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3361, 169, 7}, // GLDFF1S_IMM_MERGE_ZERO
959 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3396, 141, 7}, // GLDFF1S_MERGE_ZERO
960 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3427, 141, 7}, // GLDFF1S_SCALED_MERGE_ZERO
961 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3465, 141, 7}, // GLDFF1S_SXTW_MERGE_ZERO
962 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3501, 141, 7}, // GLDFF1S_SXTW_SCALED_MERGE_ZERO
963 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3544, 141, 7}, // GLDFF1S_UXTW_MERGE_ZERO
964 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3580, 141, 7}, // GLDFF1S_UXTW_SCALED_MERGE_ZERO
965 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3623, 169, 7}, // GLDFF1_IMM_MERGE_ZERO
966 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3657, 141, 7}, // GLDFF1_MERGE_ZERO
967 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3687, 141, 7}, // GLDFF1_SCALED_MERGE_ZERO
968 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3724, 141, 7}, // GLDFF1_SXTW_MERGE_ZERO
969 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3759, 141, 7}, // GLDFF1_SXTW_SCALED_MERGE_ZERO
970 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3801, 141, 7}, // GLDFF1_UXTW_MERGE_ZERO
971 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3836, 141, 7}, // GLDFF1_UXTW_SCALED_MERGE_ZERO
972 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3878, 169, 7}, // GLDNT1S_MERGE_ZERO
973 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3909, 0, 0}, // GLDNT1_INDEX_MERGE_ZERO
974 {1, 4, 0|1<<SDNPHasChain, 0, 0, 3945, 169, 7}, // GLDNT1_MERGE_ZERO
975 {1, 3, 0, 0, 0, 3975, 200, 5}, // HADDS_PRED
976 {1, 3, 0, 0, 0, 3998, 200, 5}, // HADDU_PRED
977 {0, 2, 0|1<<SDNPHasChain, 0, 0, 4021, 66, 2}, // INIT_TPIDR2OBJ
978 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 4048, 0, 0}, // INOUT_ZA_USE
979 {1, 2, 0, 0, 0, 4073, 101, 1}, // INSR
980 {1, 2, 0, 0, 0, 4090, 248, 2}, // LASTA
981 {1, 2, 0, 0, 0, 4108, 248, 2}, // LASTB
982 {2, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4126, 0, 0}, // LD1DUPpost
983 {2, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4149, 0, 0}, // LD1LANEpost
984 {1, 2, 0|1<<SDNPHasChain, 0, 0, 4173, 136, 5}, // LD1RO_MERGE_ZERO
985 {1, 2, 0|1<<SDNPHasChain, 0, 0, 4202, 136, 5}, // LD1RQ_MERGE_ZERO
986 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4231, 136, 5}, // LD1S_MERGE_ZERO
987 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4259, 136, 5}, // LD1_MERGE_ZERO
988 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4286, 0, 0}, // LD1x2post
989 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4308, 0, 0}, // LD1x3post
990 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4330, 0, 0}, // LD1x4post
991 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4352, 0, 0}, // LD2DUPpost
992 {3, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4375, 0, 0}, // LD2LANEpost
993 {3, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4399, 0, 0}, // LD2post
994 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4419, 0, 0}, // LD3DUPpost
995 {4, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4442, 0, 0}, // LD3LANEpost
996 {4, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4466, 0, 0}, // LD3post
997 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4486, 0, 0}, // LD4DUPpost
998 {5, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4509, 0, 0}, // LD4LANEpost
999 {5, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4533, 0, 0}, // LD4post
1000 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4553, 136, 5}, // LDFF1S_MERGE_ZERO
1001 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4583, 136, 5}, // LDFF1_MERGE_ZERO
1002 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4612, 28, 3}, // LDIAPP
1003 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4631, 136, 5}, // LDNF1S_MERGE_ZERO
1004 {1, 3, 0|1<<SDNPHasChain, 0, 0, 4661, 136, 5}, // LDNF1_MERGE_ZERO
1005 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4690, 41, 3}, // LDNP
1006 {2, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 4707, 28, 3}, // LDP
1007 {1, 1, 0, 0, 0, 4723, 211, 2}, // LOADgot
1008 {1, 8, 0, 0, 0, 4743, 0, 0}, // LS64_BUILD
1009 {1, 2, 0, 0, 0, 4766, 0, 0}, // LS64_EXTRACT
1010 {1, 1, 0, 0, 0, 4791, 243, 1}, // MOVI
1011 {1, 1, 0, 0, 0, 4808, 243, 1}, // MOVIedit
1012 {1, 2, 0, 0, 0, 4829, 242, 2}, // MOVImsl
1013 {1, 2, 0, 0, 0, 4849, 242, 2}, // MOVIshift
1014 {2, 1, 0|1<<SDNPHasChain, 0, 0, 4871, 39, 2}, // MRRS
1015 {2, 1, 0|1<<SDNPHasChain, 0, 0, 4888, 36, 3}, // MRS
1016 {0, 3, 0|1<<SDNPHasChain, 0, 0, 4904, 240, 2}, // MSRR
1017 {1, 3, 0, 0, 0, 4921, 200, 5}, // MULHS_PRED
1018 {1, 3, 0, 0, 0, 4944, 200, 5}, // MULHU_PRED
1019 {1, 3, 0, 0, 0, 4967, 200, 5}, // MUL_PRED
1020 {1, 2, 0, 0, 0, 4988, 242, 2}, // MVNImsl
1021 {1, 2, 0, 0, 0, 5008, 242, 2}, // MVNIshift
1022 {1, 3, 0, 0, 0, 5030, 200, 5}, // NEG_MERGE_PASSTHRU
1023 {1, 1, 0, 0, 0, 5061, 0, 0}, // NVCAST
1024 {1, 3, 0, 0, 0, 5080, 106, 4}, // ORRi
1025 {1, 2, 0, 0, 0, 5097, 248, 2}, // ORV_PRED
1026 {1, 2, 0, 0, 0, 5118, 68, 3}, // PMULL
1027 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5136, 4, 2}, // PREFETCH
1028 {0, 1, 0|1<<SDNPHasChain, 0, 0, 5157, 47, 1}, // PROBED_ALLOCA
1029 {1, 2, 0, 0, 0, 5183, 25, 3}, // PTEST
1030 {1, 2, 0, 0, 0, 5201, 25, 3}, // PTEST_ANY
1031 {1, 2, 0, 0, 0, 5223, 25, 3}, // PTEST_FIRST
1032 {1, 1, 0, 0, 0, 5247, 119, 2}, // PTRUE
1033 {0, 3, 0|1<<SDNPHasChain, 0, 0, 5265, 3, 3}, // RANGE_PREFETCH
1034 {1, 1, 0, 0, 0, 5292, 66, 2}, // RDSVL
1035 {1, 1, 0, 0, 0, 5310, 0, 0}, // REINTERPRET_CAST
1036 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 5339, 0, 0}, // REQUIRES_ZA_SAVE
1037 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPInGlue, 0, 0, 5368, 0, 0}, // REQUIRES_ZT0_SAVE
1038 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 5398, 63, 2}, // RESTORE_ZA
1039 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5421, 63, 2}, // RESTORE_ZT
1040 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 5444, 0, 0}, // RET_GLUE
1041 {1, 1, 0, 0, 0, 5465, 212, 1}, // REV16
1042 {1, 1, 0, 0, 0, 5483, 212, 1}, // REV32
1043 {1, 1, 0, 0, 0, 5501, 212, 1}, // REV64
1044 {1, 3, 0, 0, 0, 5519, 200, 5}, // REVD_MERGE_PASSTHRU
1045 {1, 3, 0, 0, 0, 5551, 200, 5}, // REVH_MERGE_PASSTHRU
1046 {1, 3, 0, 0, 0, 5583, 200, 5}, // REVW_MERGE_PASSTHRU
1047 {1, 3, 0, 0, 0, 5615, 200, 5}, // RHADDS_PRED
1048 {1, 3, 0, 0, 0, 5639, 200, 5}, // RHADDU_PRED
1049 {1, 2, 0, 0, 0, 5663, 133, 3}, // RSHRNB_I
1050 {1, 1, 0, 0, 0, 5684, 131, 2}, // SADDLP
1051 {1, 1, 0, 0, 0, 5703, 131, 2}, // SADDLV
1052 {1, 1, 0, 0, 0, 5722, 100, 2}, // SADDV
1053 {1, 2, 0, 0, 0, 5740, 248, 2}, // SADDV_PRED
1054 {1, 2, 0, 0, 0, 5763, 131, 2}, // SADDWB
1055 {1, 2, 0, 0, 0, 5782, 131, 2}, // SADDWT
1056 {0, 2, 0|1<<SDNPHasChain, 0, 0, 5801, 63, 2}, // SAVE_ZT
1057 {1, 3, 0, 0, 0, 5821, 215, 4}, // SBC
1058 {2, 3, 0, 0, 0, 5837, 235, 5}, // SBCS
1059 {1, 3, 0, 0, 0, 5854, 200, 5}, // SDIV_PRED
1060 {1, 3, 0, 0, 0, 5876, 110, 4}, // SDOT
1061 {1, 4, 0, 0, 0, 5893, 182, 8}, // SETCC_MERGE_ZERO
1062 {1, 3, 0, 0, 0, 5922, 200, 5}, // SHL_PRED
1063 {1, 4, 0, 0, 0, 5943, 153, 9}, // SIGN_EXTEND_INREG_MERGE_PASSTHRU
1064 {1, 3, 0, 0, 0, 5988, 126, 7}, // SINT_TO_FP_MERGE_PASSTHRU
1065 {1, 1, 0, 0, 0, 6026, 83, 2}, // SITOF
1066 {1, 1, 0, 0, 0, 6044, 100, 2}, // SMAXV
1067 {1, 2, 0, 0, 0, 6062, 248, 2}, // SMAXV_PRED
1068 {1, 3, 0, 0, 0, 6085, 200, 5}, // SMAX_PRED
1069 {0, 0, 0|1<<SDNPHasChain, 0, 0, 6107, 0, 0}, // SME_STATE_ALLOC
1070 {0, 3, 0|1<<SDNPHasChain, 0, 0, 6135, 62, 3}, // SME_ZA_LDR
1071 {0, 3, 0|1<<SDNPHasChain, 0, 0, 6158, 62, 3}, // SME_ZA_STR
1072 {1, 1, 0, 0, 0, 6181, 100, 2}, // SMINV
1073 {1, 2, 0, 0, 0, 6199, 248, 2}, // SMINV_PRED
1074 {1, 3, 0, 0, 0, 6222, 200, 5}, // SMIN_PRED
1075 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 6244, 61, 1}, // SMSTART
1076 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 6264, 61, 1}, // SMSTOP
1077 {1, 2, 0, 0, 0, 6283, 68, 3}, // SMULL
1078 {1, 3, 0, 0, 0, 6301, 200, 5}, // SPLICE
1079 {1, 1, 0, 0, 0, 6320, 213, 2}, // SQABS
1080 {1, 2, 0, 0, 0, 6338, 219, 3}, // SQADD
1081 {1, 2, 0, 0, 0, 6356, 252, 1}, // SQDMULH
1082 {1, 2, 0, 0, 0, 6376, 250, 3}, // SQDMULL
1083 {1, 1, 0, 0, 0, 6396, 213, 2}, // SQNEG
1084 {1, 3, 0, 0, 0, 6414, 222, 4}, // SQRDMLAH
1085 {1, 3, 0, 0, 0, 6435, 222, 4}, // SQRDMLSH
1086 {1, 2, 0, 0, 0, 6456, 219, 3}, // SQRDMULH
1087 {1, 2, 0, 0, 0, 6477, 219, 3}, // SQRSHL
1088 {1, 2, 0, 0, 0, 6496, 93, 5}, // SQRSHRN
1089 {1, 2, 0, 0, 0, 6516, 93, 5}, // SQRSHRUN
1090 {1, 2, 0, 0, 0, 6537, 219, 3}, // SQSHL
1091 {1, 2, 0, 0, 0, 6555, 233, 2}, // SQSHLU_I
1092 {1, 2, 0, 0, 0, 6576, 233, 2}, // SQSHL_I
1093 {1, 2, 0, 0, 0, 6596, 93, 5}, // SQSHRN
1094 {1, 2, 0, 0, 0, 6615, 93, 5}, // SQSHRUN
1095 {1, 2, 0, 0, 0, 6635, 219, 3}, // SQSUB
1096 {1, 3, 0, 0, 0, 6653, 200, 5}, // SRA_PRED
1097 {1, 3, 0, 0, 0, 6674, 200, 5}, // SRL_PRED
1098 {1, 2, 0, 0, 0, 6695, 233, 2}, // SRSHR_I
1099 {0, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6715, 0, 0}, // SST1Q_INDEX_PRED
1100 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6744, 169, 7}, // SST1Q_PRED
1101 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6767, 169, 7}, // SST1_IMM_PRED
1102 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6793, 141, 7}, // SST1_PRED
1103 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6815, 141, 7}, // SST1_SCALED_PRED
1104 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6844, 141, 7}, // SST1_SXTW_PRED
1105 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6871, 141, 7}, // SST1_SXTW_SCALED_PRED
1106 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6905, 141, 7}, // SST1_UXTW_PRED
1107 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6932, 141, 7}, // SST1_UXTW_SCALED_PRED
1108 {0, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 6966, 0, 0}, // SSTNT1_INDEX_PRED
1109 {0, 5, 0|1<<SDNPHasChain, 0, 0, 6996, 169, 7}, // SSTNT1_PRED
1110 {0, 4, 0|1<<SDNPHasChain, 0, 0, 7020, 121, 5}, // ST1_PRED
1111 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7041, 0, 0}, // ST1x2post
1112 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7063, 0, 0}, // ST1x3post
1113 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7085, 0, 0}, // ST1x4post
1114 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7107, 54, 2}, // ST2G
1115 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7124, 0, 0}, // ST2LANEpost
1116 {1, 4, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7148, 0, 0}, // ST2post
1117 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7168, 0, 0}, // ST3LANEpost
1118 {1, 5, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7192, 0, 0}, // ST3post
1119 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7212, 0, 0}, // ST4LANEpost
1120 {1, 6, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7236, 0, 0}, // ST4post
1121 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7256, 54, 2}, // STG
1122 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7272, 28, 3}, // STILP
1123 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7290, 41, 3}, // STNP
1124 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7307, 28, 3}, // STP
1125 {1, 2, 0|1<<SDNPHasChain, 0|1<<SDNFIsStrictFP, 0, 7323, 22, 3}, // STRICT_FCMP
1126 {1, 2, 0|1<<SDNPHasChain, 0|1<<SDNFIsStrictFP, 0, 7347, 22, 3}, // STRICT_FCMPE
1127 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7372, 54, 2}, // STZ2G
1128 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 7390, 54, 2}, // STZG
1129 {2, 2, 0, 0, 0, 7407, 236, 4}, // SUBS
1130 {1, 1, 0, 0, 0, 7424, 71, 3}, // SUNPKHI
1131 {1, 1, 0, 0, 0, 7444, 71, 3}, // SUNPKLO
1132 {1, 2, 0, 0, 0, 7464, 219, 3}, // SUQADD
1133 {1, 2, 0, 0, 0, 7483, 107, 3}, // TBL
1134 {0, 3, 0|1<<SDNPHasChain, 0, 0, 7499, 74, 3}, // TBNZ
1135 {0, 3, 0|1<<SDNPHasChain, 0, 0, 7516, 74, 3}, // TBZ
1136 {0, 2, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 7532, 47, 1}, // TC_RETURN
1137 {1, 0, 0, 0, 0, 7554, 47, 1}, // THREAD_POINTER
1138 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 7581, 47, 1}, // TLSDESC_AUTH_CALLSEQ
1139 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 7614, 47, 1}, // TLSDESC_CALLSEQ
1140 {1, 2, 0, 0, 0, 7642, 99, 3}, // TRN1
1141 {1, 2, 0, 0, 0, 7659, 99, 3}, // TRN2
1142 {1, 1, 0, 0, 0, 7676, 131, 2}, // UADDLP
1143 {1, 1, 0, 0, 0, 7695, 131, 2}, // UADDLV
1144 {1, 1, 0, 0, 0, 7714, 100, 2}, // UADDV
1145 {1, 2, 0, 0, 0, 7732, 248, 2}, // UADDV_PRED
1146 {1, 2, 0, 0, 0, 7755, 131, 2}, // UADDWB
1147 {1, 2, 0, 0, 0, 7774, 131, 2}, // UADDWT
1148 {1, 3, 0, 0, 0, 7793, 200, 5}, // UDIV_PRED
1149 {1, 3, 0, 0, 0, 7815, 110, 4}, // UDOT
1150 {1, 3, 0, 0, 0, 7832, 126, 7}, // UINT_TO_FP_MERGE_PASSTHRU
1151 {1, 1, 0, 0, 0, 7870, 83, 2}, // UITOF
1152 {1, 1, 0, 0, 0, 7888, 100, 2}, // UMAXV
1153 {1, 2, 0, 0, 0, 7906, 248, 2}, // UMAXV_PRED
1154 {1, 3, 0, 0, 0, 7929, 200, 5}, // UMAX_PRED
1155 {1, 1, 0, 0, 0, 7951, 100, 2}, // UMINV
1156 {1, 2, 0, 0, 0, 7969, 248, 2}, // UMINV_PRED
1157 {1, 3, 0, 0, 0, 7992, 200, 5}, // UMIN_PRED
1158 {1, 2, 0, 0, 0, 8014, 68, 3}, // UMULL
1159 {1, 2, 0, 0, 0, 8032, 219, 3}, // UQADD
1160 {1, 2, 0, 0, 0, 8050, 219, 3}, // UQRSHL
1161 {1, 2, 0, 0, 0, 8069, 93, 5}, // UQRSHRN
1162 {1, 2, 0, 0, 0, 8089, 219, 3}, // UQSHL
1163 {1, 2, 0, 0, 0, 8107, 233, 2}, // UQSHL_I
1164 {1, 2, 0, 0, 0, 8127, 93, 5}, // UQSHRN
1165 {1, 2, 0, 0, 0, 8146, 219, 3}, // UQSUB
1166 {1, 2, 0, 0, 0, 8164, 233, 2}, // URSHR_I
1167 {1, 3, 0, 0, 0, 8184, 162, 7}, // URSHR_I_PRED
1168 {1, 3, 0, 0, 0, 8209, 110, 4}, // USDOT
1169 {1, 2, 0, 0, 0, 8227, 219, 3}, // USQADD
1170 {1, 1, 0, 0, 0, 8246, 71, 3}, // UUNPKHI
1171 {1, 1, 0, 0, 0, 8266, 71, 3}, // UUNPKLO
1172 {1, 2, 0, 0, 0, 8286, 99, 3}, // UZP1
1173 {1, 2, 0, 0, 0, 8303, 99, 3}, // UZP2
1174 {1, 2, 0, 0, 0, 8320, 233, 2}, // VASHR
1175 {1, 2, 0, 0, 0, 8338, 233, 2}, // VLSHR
1176 {1, 2, 0, 0, 0, 8356, 233, 2}, // VSHL
1177 {1, 3, 0, 0, 0, 8373, 207, 4}, // VSLI
1178 {1, 3, 0, 0, 0, 8390, 207, 4}, // VSRI
1179 {1, 4, 0, 0, 0, 8407, 31, 5}, // WrapperLarge
1180 {1, 4, 0, 0, 0, 8432, 153, 9}, // ZERO_EXTEND_INREG_MERGE_PASSTHRU
1181 {1, 2, 0, 0, 0, 8477, 99, 3}, // ZIP1
1182 {1, 2, 0, 0, 0, 8494, 99, 3}, // ZIP2
1183};
1184
1185static const SDNodeInfo AArch64GenSDNodeInfo(
1186 /*NumOpcodes=*/356, AArch64SDNodeDescs, AArch64SDNodeNames,
1187 AArch64VTByHwModeTable, AArch64SDTypeConstraints);
1188
1189} // namespace llvm
1190
1191#endif // GET_SDNODE_DESC
1192
1193