1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11
12namespace llvm::AMDGPU {
13
14enum : unsigned {
15 InvalidRegBankID = ~0u,
16 AGPRRegBankID = 0,
17 SGPRRegBankID = 1,
18 VCCRegBankID = 2,
19 VGPRRegBankID = 3,
20 NumRegisterBanks,
21};
22
23} // namespace llvm::AMDGPU
24
25#endif // GET_REGBANK_DECLARATIONS
26
27#ifdef GET_TARGET_REGBANK_CLASS
28#undef GET_TARGET_REGBANK_CLASS
29
30private:
31 static const RegisterBank *RegBanks[];
32 static const unsigned Sizes[];
33
34public:
35 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const override;
36protected:
37 AMDGPUGenRegisterBankInfo(unsigned HwMode = 0);
38
39
40#endif // GET_TARGET_REGBANK_CLASS
41
42#ifdef GET_TARGET_REGBANK_IMPL
43#undef GET_TARGET_REGBANK_IMPL
44
45namespace llvm {
46
47namespace AMDGPU {
48
49const uint32_t AGPRRegBankCoverageData[] = {
50 // 0-31
51 (1u << (AMDGPU::AGPR_LO16RegClassID - 0)) |
52 (1u << (AMDGPU::AGPR_32RegClassID - 0)) |
53 (1u << (AMDGPU::AV_32RegClassID - 0)) |
54 0,
55 // 32-63
56 (1u << (AMDGPU::AReg_64RegClassID - 32)) |
57 (1u << (AMDGPU::AReg_64_Align2RegClassID - 32)) |
58 (1u << (AMDGPU::AV_64RegClassID - 32)) |
59 (1u << (AMDGPU::AV_64_Align2RegClassID - 32)) |
60 0,
61 // 64-95
62 (1u << (AMDGPU::AReg_96RegClassID - 64)) |
63 (1u << (AMDGPU::AReg_96_Align2RegClassID - 64)) |
64 (1u << (AMDGPU::AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID - 64)) |
65 (1u << (AMDGPU::AV_96RegClassID - 64)) |
66 (1u << (AMDGPU::AV_96_Align2RegClassID - 64)) |
67 (1u << (AMDGPU::AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) |
68 0,
69 // 96-127
70 (1u << (AMDGPU::AReg_128RegClassID - 96)) |
71 (1u << (AMDGPU::AV_128RegClassID - 96)) |
72 (1u << (AMDGPU::AV_128_Align2RegClassID - 96)) |
73 (1u << (AMDGPU::AV_128_with_sub1_sub2_in_AV_64_Align2RegClassID - 96)) |
74 0,
75 // 128-159
76 (1u << (AMDGPU::AReg_128_Align2RegClassID - 128)) |
77 (1u << (AMDGPU::AReg_128_with_sub1_sub2_in_AReg_64_Align2RegClassID - 128)) |
78 (1u << (AMDGPU::AV_160RegClassID - 128)) |
79 (1u << (AMDGPU::AV_160_Align2RegClassID - 128)) |
80 (1u << (AMDGPU::AV_160_with_sub1_sub2_in_AV_64_Align2RegClassID - 128)) |
81 0,
82 // 160-191
83 (1u << (AMDGPU::AReg_160RegClassID - 160)) |
84 (1u << (AMDGPU::AReg_160_Align2RegClassID - 160)) |
85 (1u << (AMDGPU::AReg_160_with_sub1_sub2_in_AReg_64_Align2RegClassID - 160)) |
86 (1u << (AMDGPU::AV_192RegClassID - 160)) |
87 0,
88 // 192-223
89 (1u << (AMDGPU::AReg_192RegClassID - 192)) |
90 (1u << (AMDGPU::AReg_192_Align2RegClassID - 192)) |
91 (1u << (AMDGPU::AReg_192_with_sub1_sub2_in_AReg_64_Align2RegClassID - 192)) |
92 (1u << (AMDGPU::AV_192_Align2RegClassID - 192)) |
93 (1u << (AMDGPU::AV_192_with_sub1_sub2_in_AV_64_Align2RegClassID - 192)) |
94 0,
95 // 224-255
96 (1u << (AMDGPU::AReg_224RegClassID - 224)) |
97 (1u << (AMDGPU::AV_224RegClassID - 224)) |
98 (1u << (AMDGPU::AV_224_Align2RegClassID - 224)) |
99 (1u << (AMDGPU::AV_224_with_sub1_sub2_in_AV_64_Align2RegClassID - 224)) |
100 0,
101 // 256-287
102 (1u << (AMDGPU::AReg_224_Align2RegClassID - 256)) |
103 (1u << (AMDGPU::AReg_224_with_sub1_sub2_in_AReg_64_Align2RegClassID - 256)) |
104 (1u << (AMDGPU::AV_256RegClassID - 256)) |
105 (1u << (AMDGPU::AV_256_Align2RegClassID - 256)) |
106 (1u << (AMDGPU::AV_256_with_sub1_sub2_in_AV_64_Align2RegClassID - 256)) |
107 0,
108 // 288-319
109 (1u << (AMDGPU::AReg_256RegClassID - 288)) |
110 (1u << (AMDGPU::AReg_256_Align2RegClassID - 288)) |
111 (1u << (AMDGPU::AReg_256_with_sub1_sub2_in_AReg_64_Align2RegClassID - 288)) |
112 0,
113 // 320-351
114 (1u << (AMDGPU::AReg_288RegClassID - 320)) |
115 (1u << (AMDGPU::AV_288RegClassID - 320)) |
116 (1u << (AMDGPU::AV_288_Align2RegClassID - 320)) |
117 (1u << (AMDGPU::AV_288_with_sub1_sub2_in_AV_64_Align2RegClassID - 320)) |
118 0,
119 // 352-383
120 (1u << (AMDGPU::AReg_288_Align2RegClassID - 352)) |
121 (1u << (AMDGPU::AReg_288_with_sub1_sub2_in_AReg_64_Align2RegClassID - 352)) |
122 0,
123 // 384-415
124 (1u << (AMDGPU::AReg_320RegClassID - 384)) |
125 (1u << (AMDGPU::AV_320RegClassID - 384)) |
126 (1u << (AMDGPU::AV_320_Align2RegClassID - 384)) |
127 (1u << (AMDGPU::AV_320_with_sub1_sub2_in_AV_64_Align2RegClassID - 384)) |
128 0,
129 // 416-447
130 (1u << (AMDGPU::AReg_320_Align2RegClassID - 416)) |
131 (1u << (AMDGPU::AReg_320_with_sub1_sub2_in_AReg_64_Align2RegClassID - 416)) |
132 0,
133 // 448-479
134 (1u << (AMDGPU::AReg_352RegClassID - 448)) |
135 (1u << (AMDGPU::AV_352RegClassID - 448)) |
136 (1u << (AMDGPU::AV_352_Align2RegClassID - 448)) |
137 (1u << (AMDGPU::AV_352_with_sub1_sub2_in_AV_64_Align2RegClassID - 448)) |
138 0,
139 // 480-511
140 (1u << (AMDGPU::AReg_352_Align2RegClassID - 480)) |
141 (1u << (AMDGPU::AReg_352_with_sub1_sub2_in_AReg_64_Align2RegClassID - 480)) |
142 0,
143 // 512-543
144 (1u << (AMDGPU::AReg_384RegClassID - 512)) |
145 (1u << (AMDGPU::AV_384RegClassID - 512)) |
146 (1u << (AMDGPU::AV_384_Align2RegClassID - 512)) |
147 (1u << (AMDGPU::AV_384_with_sub1_sub2_in_AV_64_Align2RegClassID - 512)) |
148 0,
149 // 544-575
150 (1u << (AMDGPU::AReg_384_Align2RegClassID - 544)) |
151 (1u << (AMDGPU::AReg_384_with_sub1_sub2_in_AReg_64_Align2RegClassID - 544)) |
152 0,
153 // 576-607
154 (1u << (AMDGPU::AV_512RegClassID - 576)) |
155 (1u << (AMDGPU::AV_512_Align2RegClassID - 576)) |
156 (1u << (AMDGPU::AV_512_with_sub1_sub2_in_AV_64_Align2RegClassID - 576)) |
157 0,
158 // 608-639
159 (1u << (AMDGPU::AReg_512RegClassID - 608)) |
160 (1u << (AMDGPU::AReg_512_Align2RegClassID - 608)) |
161 0,
162 // 640-671
163 (1u << (AMDGPU::AReg_512_with_sub1_sub2_in_AReg_64_Align2RegClassID - 640)) |
164 0,
165 // 672-703
166 0,
167 // 704-735
168 (1u << (AMDGPU::AReg_1024RegClassID - 704)) |
169 0,
170 // 736-767
171 0,
172 // 768-799
173 (1u << (AMDGPU::AReg_1024_Align2RegClassID - 768)) |
174 (1u << (AMDGPU::AReg_1024_with_sub1_sub2_in_AReg_64_Align2RegClassID - 768)) |
175 0,
176 // 800-831
177 0,
178 // 832-863
179 0,
180 // 864-895
181 0,
182};
183const uint32_t SGPRRegBankCoverageData[] = {
184 // 0-31
185 (1u << (AMDGPU::SReg_LO16RegClassID - 0)) |
186 (1u << (AMDGPU::SGPR_LO16RegClassID - 0)) |
187 (1u << (AMDGPU::TTMP_LO16RegClassID - 0)) |
188 (1u << (AMDGPU::SReg_32RegClassID - 0)) |
189 (1u << (AMDGPU::SReg_32_XEXEC_HIRegClassID - 0)) |
190 (1u << (AMDGPU::SReg_32_XEXECRegClassID - 0)) |
191 (1u << (AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID - 0)) |
192 (1u << (AMDGPU::SReg_32_XM0RegClassID - 0)) |
193 (1u << (AMDGPU::VS_16RegClassID - 0)) |
194 (1u << (AMDGPU::VS_16_Lo128RegClassID - 0)) |
195 (1u << (AMDGPU::VS_16_with_hi16RegClassID - 0)) |
196 (1u << (AMDGPU::VS_32RegClassID - 0)) |
197 (1u << (AMDGPU::VS_32_with_hi16RegClassID - 0)) |
198 (1u << (AMDGPU::VS_32_Lo256RegClassID - 0)) |
199 (1u << (AMDGPU::VS_32_Lo256_with_hi16RegClassID - 0)) |
200 (1u << (AMDGPU::VS_32_Lo128RegClassID - 0)) |
201 (1u << (AMDGPU::VS_32_Lo128_with_hi16RegClassID - 0)) |
202 (1u << (AMDGPU::SRegOrLds_32RegClassID - 0)) |
203 (1u << (AMDGPU::VS_16_with_hi16_with_lo16_in_SGPR_LO16RegClassID - 0)) |
204 (1u << (AMDGPU::VS_16_with_hi16_with_lo16_in_TTMP_LO16RegClassID - 0)) |
205 0,
206 // 32-63
207 (1u << (AMDGPU::SReg_32_XM0_XEXECRegClassID - 32)) |
208 (1u << (AMDGPU::SGPR_32RegClassID - 32)) |
209 (1u << (AMDGPU::TTMP_32RegClassID - 32)) |
210 (1u << (AMDGPU::VS_64RegClassID - 32)) |
211 (1u << (AMDGPU::VS_64_with_sub1RegClassID - 32)) |
212 (1u << (AMDGPU::VS_64_Align2RegClassID - 32)) |
213 (1u << (AMDGPU::VS_64_Align2_with_sub1RegClassID - 32)) |
214 (1u << (AMDGPU::VS_64_with_sub0_in_VS_32_Lo256RegClassID - 32)) |
215 (1u << (AMDGPU::VS_64_with_sub1_and_VS_64_with_sub0_in_VS_32_Lo256RegClassID - 32)) |
216 (1u << (AMDGPU::VS_64_with_sub1_with_sub1_in_VS_32_Lo256RegClassID - 32)) |
217 (1u << (AMDGPU::VS_64_Lo256RegClassID - 32)) |
218 (1u << (AMDGPU::VS_64_with_sub0_in_VS_32_Lo128RegClassID - 32)) |
219 (1u << (AMDGPU::VS_64_Lo256_with_sub1RegClassID - 32)) |
220 (1u << (AMDGPU::VS_64_with_sub1_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID - 32)) |
221 (1u << (AMDGPU::VS_64_with_sub1_with_sub1_in_VS_32_Lo128RegClassID - 32)) |
222 (1u << (AMDGPU::VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID - 32)) |
223 (1u << (AMDGPU::VS_64_with_sub1_and_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID - 32)) |
224 0,
225 // 64-95
226 (1u << (AMDGPU::SReg_64RegClassID - 64)) |
227 (1u << (AMDGPU::SReg_64_XEXECRegClassID - 64)) |
228 (1u << (AMDGPU::SReg_64_XEXEC_XNULLRegClassID - 64)) |
229 (1u << (AMDGPU::SGPR_64RegClassID - 64)) |
230 (1u << (AMDGPU::CCR_SGPR_64RegClassID - 64)) |
231 (1u << (AMDGPU::Gfx_CCR_SGPR_64RegClassID - 64)) |
232 (1u << (AMDGPU::TTMP_64RegClassID - 64)) |
233 (1u << (AMDGPU::SReg_64_EncodableRegClassID - 64)) |
234 (1u << (AMDGPU::SReg_64_Encodable_with_sub0_in_SReg_32_XEXECRegClassID - 64)) |
235 0,
236 // 96-127
237 (1u << (AMDGPU::SReg_96RegClassID - 96)) |
238 (1u << (AMDGPU::SGPR_96RegClassID - 96)) |
239 (1u << (AMDGPU::SGPR_96_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 96)) |
240 (1u << (AMDGPU::SGPR_96_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 96)) |
241 (1u << (AMDGPU::TTMP_96RegClassID - 96)) |
242 (1u << (AMDGPU::VS_128RegClassID - 96)) |
243 (1u << (AMDGPU::VS_128_with_hi16RegClassID - 96)) |
244 (1u << (AMDGPU::VS_128_Align2RegClassID - 96)) |
245 (1u << (AMDGPU::VS_128_Align2_with_hi16RegClassID - 96)) |
246 (1u << (AMDGPU::VS_128_with_hi16_with_sub0_in_VS_32_Lo256RegClassID - 96)) |
247 (1u << (AMDGPU::VS_128_with_hi16_with_sub1_in_VS_32_Lo256RegClassID - 96)) |
248 (1u << (AMDGPU::VS_128_with_hi16_with_sub2_in_VS_32_Lo256RegClassID - 96)) |
249 (1u << (AMDGPU::VS_128_with_hi16_with_sub3_in_VS_32_Lo256RegClassID - 96)) |
250 (1u << (AMDGPU::VS_128_with_hi16_with_sub0_in_VS_32_Lo128RegClassID - 96)) |
251 (1u << (AMDGPU::VS_128_with_hi16_with_sub0_sub1_in_VS_64_Lo256RegClassID - 96)) |
252 (1u << (AMDGPU::VS_128_with_hi16_with_sub1_in_VS_32_Lo128RegClassID - 96)) |
253 (1u << (AMDGPU::VS_128_with_hi16_with_sub2_sub3_in_VS_64_Lo256RegClassID - 96)) |
254 (1u << (AMDGPU::VS_128_with_hi16_with_sub2_in_VS_32_Lo128RegClassID - 96)) |
255 (1u << (AMDGPU::VS_128_with_hi16_with_sub3_in_VS_32_Lo128RegClassID - 96)) |
256 0,
257 // 128-159
258 (1u << (AMDGPU::SReg_128RegClassID - 128)) |
259 (1u << (AMDGPU::SReg_128_XNULLRegClassID - 128)) |
260 (1u << (AMDGPU::SGPR_128RegClassID - 128)) |
261 (1u << (AMDGPU::SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 128)) |
262 (1u << (AMDGPU::SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 128)) |
263 (1u << (AMDGPU::SGPR_128_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 128)) |
264 (1u << (AMDGPU::TTMP_128RegClassID - 128)) |
265 (1u << (AMDGPU::VS_128_with_hi16_with_sub0_sub1_in_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID - 128)) |
266 (1u << (AMDGPU::VS_128_with_hi16_with_sub2_sub3_in_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID - 128)) |
267 0,
268 // 160-191
269 (1u << (AMDGPU::SReg_160RegClassID - 160)) |
270 (1u << (AMDGPU::SGPR_160RegClassID - 160)) |
271 (1u << (AMDGPU::SGPR_160_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 160)) |
272 (1u << (AMDGPU::SGPR_160_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 160)) |
273 (1u << (AMDGPU::SGPR_160_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 160)) |
274 (1u << (AMDGPU::TTMP_160RegClassID - 160)) |
275 0,
276 // 192-223
277 0,
278 // 224-255
279 (1u << (AMDGPU::SReg_192RegClassID - 224)) |
280 (1u << (AMDGPU::SGPR_192RegClassID - 224)) |
281 (1u << (AMDGPU::SGPR_192_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 224)) |
282 (1u << (AMDGPU::SGPR_192_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 224)) |
283 (1u << (AMDGPU::SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 224)) |
284 (1u << (AMDGPU::SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 224)) |
285 (1u << (AMDGPU::SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 224)) |
286 (1u << (AMDGPU::TTMP_192RegClassID - 224)) |
287 0,
288 // 256-287
289 (1u << (AMDGPU::SReg_224RegClassID - 256)) |
290 (1u << (AMDGPU::SGPR_224RegClassID - 256)) |
291 (1u << (AMDGPU::SGPR_224_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 256)) |
292 (1u << (AMDGPU::SGPR_224_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 256)) |
293 (1u << (AMDGPU::SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 256)) |
294 (1u << (AMDGPU::SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_224_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 256)) |
295 (1u << (AMDGPU::SGPR_224_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 256)) |
296 (1u << (AMDGPU::TTMP_224RegClassID - 256)) |
297 0,
298 // 288-319
299 0,
300 // 320-351
301 (1u << (AMDGPU::SReg_256RegClassID - 320)) |
302 (1u << (AMDGPU::SReg_256_XNULLRegClassID - 320)) |
303 (1u << (AMDGPU::SGPR_256RegClassID - 320)) |
304 (1u << (AMDGPU::SGPR_256_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 320)) |
305 (1u << (AMDGPU::SGPR_256_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 320)) |
306 (1u << (AMDGPU::SGPR_256_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 320)) |
307 (1u << (AMDGPU::SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 320)) |
308 (1u << (AMDGPU::SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_256_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 320)) |
309 (1u << (AMDGPU::SGPR_256_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 320)) |
310 (1u << (AMDGPU::TTMP_256RegClassID - 320)) |
311 0,
312 // 352-383
313 (1u << (AMDGPU::SReg_288RegClassID - 352)) |
314 (1u << (AMDGPU::SGPR_288RegClassID - 352)) |
315 (1u << (AMDGPU::SGPR_288_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 352)) |
316 0,
317 // 384-415
318 (1u << (AMDGPU::SGPR_288_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 384)) |
319 (1u << (AMDGPU::SGPR_288_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 384)) |
320 (1u << (AMDGPU::SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 384)) |
321 (1u << (AMDGPU::SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_288_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 384)) |
322 (1u << (AMDGPU::SGPR_288_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 384)) |
323 (1u << (AMDGPU::TTMP_288RegClassID - 384)) |
324 0,
325 // 416-447
326 (1u << (AMDGPU::SReg_320RegClassID - 416)) |
327 (1u << (AMDGPU::SGPR_320RegClassID - 416)) |
328 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 416)) |
329 (1u << (AMDGPU::SGPR_320_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 416)) |
330 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 416)) |
331 (1u << (AMDGPU::SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 416)) |
332 (1u << (AMDGPU::SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 416)) |
333 0,
334 // 448-479
335 (1u << (AMDGPU::SGPR_320_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 448)) |
336 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 448)) |
337 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 448)) |
338 (1u << (AMDGPU::SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 448)) |
339 (1u << (AMDGPU::SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 448)) |
340 (1u << (AMDGPU::TTMP_320RegClassID - 448)) |
341 0,
342 // 480-511
343 (1u << (AMDGPU::SReg_352RegClassID - 480)) |
344 (1u << (AMDGPU::SGPR_352RegClassID - 480)) |
345 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 480)) |
346 0,
347 // 512-543
348 (1u << (AMDGPU::SGPR_352_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 512)) |
349 (1u << (AMDGPU::SGPR_352_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 512)) |
350 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 512)) |
351 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 512)) |
352 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 512)) |
353 (1u << (AMDGPU::SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 512)) |
354 (1u << (AMDGPU::SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 512)) |
355 (1u << (AMDGPU::SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 512)) |
356 (1u << (AMDGPU::SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 512)) |
357 (1u << (AMDGPU::TTMP_352RegClassID - 512)) |
358 0,
359 // 544-575
360 0,
361 // 576-607
362 (1u << (AMDGPU::SReg_384RegClassID - 576)) |
363 (1u << (AMDGPU::SGPR_384RegClassID - 576)) |
364 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 576)) |
365 (1u << (AMDGPU::SGPR_384_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 576)) |
366 (1u << (AMDGPU::SGPR_384_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 576)) |
367 (1u << (AMDGPU::SGPR_384_with_sub10_sub11_in_CCR_SGPR_64RegClassID - 576)) |
368 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
369 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
370 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
371 (1u << (AMDGPU::SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
372 (1u << (AMDGPU::SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
373 (1u << (AMDGPU::SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
374 (1u << (AMDGPU::SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 576)) |
375 (1u << (AMDGPU::TTMP_384RegClassID - 576)) |
376 0,
377 // 608-639
378 0,
379 // 640-671
380 (1u << (AMDGPU::SReg_512RegClassID - 640)) |
381 (1u << (AMDGPU::SGPR_512RegClassID - 640)) |
382 0,
383 // 672-703
384 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 672)) |
385 (1u << (AMDGPU::SGPR_512_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 672)) |
386 (1u << (AMDGPU::SGPR_512_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 672)) |
387 (1u << (AMDGPU::SGPR_512_with_sub10_sub11_in_CCR_SGPR_64RegClassID - 672)) |
388 (1u << (AMDGPU::SGPR_512_with_sub14_sub15_in_CCR_SGPR_64RegClassID - 672)) |
389 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 672)) |
390 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 672)) |
391 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 672)) |
392 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 672)) |
393 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 672)) |
394 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 672)) |
395 (1u << (AMDGPU::SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 672)) |
396 (1u << (AMDGPU::SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 672)) |
397 (1u << (AMDGPU::SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 672)) |
398 (1u << (AMDGPU::SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 672)) |
399 (1u << (AMDGPU::SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 672)) |
400 (1u << (AMDGPU::SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 672)) |
401 (1u << (AMDGPU::SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 672)) |
402 (1u << (AMDGPU::TTMP_512RegClassID - 672)) |
403 0,
404 // 704-735
405 0,
406 // 736-767
407 0,
408 // 768-799
409 0,
410 // 800-831
411 (1u << (AMDGPU::SReg_1024RegClassID - 800)) |
412 (1u << (AMDGPU::SGPR_1024RegClassID - 800)) |
413 0,
414 // 832-863
415 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClassID - 832)) |
416 (1u << (AMDGPU::SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64RegClassID - 832)) |
417 (1u << (AMDGPU::SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64RegClassID - 832)) |
418 (1u << (AMDGPU::SGPR_1024_with_sub10_sub11_in_CCR_SGPR_64RegClassID - 832)) |
419 (1u << (AMDGPU::SGPR_1024_with_sub14_sub15_in_CCR_SGPR_64RegClassID - 832)) |
420 (1u << (AMDGPU::SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
421 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
422 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
423 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
424 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
425 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
426 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
427 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
428 (1u << (AMDGPU::SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
429 (1u << (AMDGPU::SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
430 (1u << (AMDGPU::SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
431 (1u << (AMDGPU::SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
432 (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
433 (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
434 (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
435 (1u << (AMDGPU::SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
436 (1u << (AMDGPU::SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
437 (1u << (AMDGPU::SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
438 (1u << (AMDGPU::SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
439 (1u << (AMDGPU::SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
440 (1u << (AMDGPU::SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
441 (1u << (AMDGPU::SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
442 (1u << (AMDGPU::SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
443 (1u << (AMDGPU::SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
444 (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
445 (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
446 (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 832)) |
447 0,
448 // 864-895
449 (1u << (AMDGPU::SGPR_1024_with_sub18_sub19_in_CCR_SGPR_64RegClassID - 864)) |
450 (1u << (AMDGPU::SGPR_1024_with_sub22_sub23_in_CCR_SGPR_64RegClassID - 864)) |
451 (1u << (AMDGPU::SGPR_1024_with_sub26_sub27_in_CCR_SGPR_64RegClassID - 864)) |
452 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
453 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
454 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
455 (1u << (AMDGPU::SGPR_1024_with_sub10_sub11_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
456 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
457 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
458 (1u << (AMDGPU::SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
459 (1u << (AMDGPU::SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
460 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
461 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
462 (1u << (AMDGPU::SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
463 (1u << (AMDGPU::SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
464 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
465 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
466 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
467 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
468 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
469 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
470 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
471 (1u << (AMDGPU::SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
472 (1u << (AMDGPU::SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
473 (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
474 (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
475 (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
476 (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
477 (1u << (AMDGPU::SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
478 (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
479 (1u << (AMDGPU::SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
480 (1u << (AMDGPU::SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID - 864)) |
481 0,
482};
483const uint32_t VCCRegBankCoverageData[] = {
484 // 0-31
485 (1u << (AMDGPU::SReg_32RegClassID - 0)) |
486 (1u << (AMDGPU::SReg_LO16RegClassID - 0)) |
487 (1u << (AMDGPU::SReg_32_XEXEC_HIRegClassID - 0)) |
488 (1u << (AMDGPU::SReg_32_XEXECRegClassID - 0)) |
489 (1u << (AMDGPU::SGPR_LO16RegClassID - 0)) |
490 (1u << (AMDGPU::TTMP_LO16RegClassID - 0)) |
491 (1u << (AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID - 0)) |
492 (1u << (AMDGPU::SReg_32_XM0RegClassID - 0)) |
493 (1u << (AMDGPU::VS_16RegClassID - 0)) |
494 (1u << (AMDGPU::VS_16_Lo128RegClassID - 0)) |
495 (1u << (AMDGPU::VS_16_with_hi16RegClassID - 0)) |
496 (1u << (AMDGPU::VS_32RegClassID - 0)) |
497 (1u << (AMDGPU::VS_32_with_hi16RegClassID - 0)) |
498 (1u << (AMDGPU::VS_32_Lo256RegClassID - 0)) |
499 (1u << (AMDGPU::VS_32_Lo256_with_hi16RegClassID - 0)) |
500 (1u << (AMDGPU::VS_32_Lo128RegClassID - 0)) |
501 (1u << (AMDGPU::VS_32_Lo128_with_hi16RegClassID - 0)) |
502 (1u << (AMDGPU::SRegOrLds_32RegClassID - 0)) |
503 (1u << (AMDGPU::VS_16_with_hi16_with_lo16_in_SGPR_LO16RegClassID - 0)) |
504 (1u << (AMDGPU::VS_16_with_hi16_with_lo16_in_TTMP_LO16RegClassID - 0)) |
505 0,
506 // 32-63
507 (1u << (AMDGPU::SReg_32_XM0_XEXECRegClassID - 32)) |
508 (1u << (AMDGPU::SGPR_32RegClassID - 32)) |
509 (1u << (AMDGPU::TTMP_32RegClassID - 32)) |
510 0,
511 // 64-95
512 (1u << (AMDGPU::SReg_64RegClassID - 64)) |
513 (1u << (AMDGPU::SReg_64_XEXECRegClassID - 64)) |
514 (1u << (AMDGPU::SReg_64_XEXEC_XNULLRegClassID - 64)) |
515 (1u << (AMDGPU::SGPR_64RegClassID - 64)) |
516 (1u << (AMDGPU::CCR_SGPR_64RegClassID - 64)) |
517 (1u << (AMDGPU::Gfx_CCR_SGPR_64RegClassID - 64)) |
518 (1u << (AMDGPU::TTMP_64RegClassID - 64)) |
519 0,
520 // 96-127
521 0,
522 // 128-159
523 0,
524 // 160-191
525 0,
526 // 192-223
527 0,
528 // 224-255
529 0,
530 // 256-287
531 0,
532 // 288-319
533 0,
534 // 320-351
535 0,
536 // 352-383
537 0,
538 // 384-415
539 0,
540 // 416-447
541 0,
542 // 448-479
543 0,
544 // 480-511
545 0,
546 // 512-543
547 0,
548 // 544-575
549 0,
550 // 576-607
551 0,
552 // 608-639
553 0,
554 // 640-671
555 0,
556 // 672-703
557 0,
558 // 704-735
559 0,
560 // 736-767
561 0,
562 // 768-799
563 0,
564 // 800-831
565 0,
566 // 832-863
567 0,
568 // 864-895
569 0,
570};
571const uint32_t VGPRRegBankCoverageData[] = {
572 // 0-31
573 (1u << (AMDGPU::VGPR_16_Lo128RegClassID - 0)) |
574 (1u << (AMDGPU::VGPR_16RegClassID - 0)) |
575 (1u << (AMDGPU::VGPR_32RegClassID - 0)) |
576 (1u << (AMDGPU::VS_16RegClassID - 0)) |
577 (1u << (AMDGPU::VGPR_32_Lo256RegClassID - 0)) |
578 (1u << (AMDGPU::VS_16_Lo128RegClassID - 0)) |
579 (1u << (AMDGPU::AV_32RegClassID - 0)) |
580 (1u << (AMDGPU::VS_32RegClassID - 0)) |
581 (1u << (AMDGPU::VS_32_with_hi16RegClassID - 0)) |
582 (1u << (AMDGPU::VRegOrLds_32RegClassID - 0)) |
583 (1u << (AMDGPU::VS_32_Lo256RegClassID - 0)) |
584 (1u << (AMDGPU::VS_32_Lo256_with_hi16RegClassID - 0)) |
585 (1u << (AMDGPU::VRegOrLds_32_and_VS_32_Lo256RegClassID - 0)) |
586 (1u << (AMDGPU::VS_32_Lo128RegClassID - 0)) |
587 (1u << (AMDGPU::VS_32_Lo128_with_hi16RegClassID - 0)) |
588 0,
589 // 32-63
590 (1u << (AMDGPU::VGPR_32_Lo128RegClassID - 32)) |
591 (1u << (AMDGPU::VReg_64RegClassID - 32)) |
592 (1u << (AMDGPU::VReg_64_Align2RegClassID - 32)) |
593 (1u << (AMDGPU::VReg_64_Lo256_Align2RegClassID - 32)) |
594 (1u << (AMDGPU::VRegOrLds_32_and_VS_32_Lo128RegClassID - 32)) |
595 (1u << (AMDGPU::AV_64_with_sub0_in_VGPR_32_Lo256RegClassID - 32)) |
596 (1u << (AMDGPU::AV_64_with_sub1_in_VGPR_32_Lo256RegClassID - 32)) |
597 (1u << (AMDGPU::AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 32)) |
598 (1u << (AMDGPU::AV_64_with_sub1_in_VGPR_32_Lo128RegClassID - 32)) |
599 (1u << (AMDGPU::AV_64RegClassID - 32)) |
600 (1u << (AMDGPU::VS_64RegClassID - 32)) |
601 (1u << (AMDGPU::VS_64_with_sub1RegClassID - 32)) |
602 (1u << (AMDGPU::AV_64_Align2RegClassID - 32)) |
603 (1u << (AMDGPU::VS_64_Align2RegClassID - 32)) |
604 (1u << (AMDGPU::VS_64_Align2_with_sub1RegClassID - 32)) |
605 (1u << (AMDGPU::VS_64_with_sub0_in_VS_32_Lo256RegClassID - 32)) |
606 (1u << (AMDGPU::VS_64_with_sub1_and_VS_64_with_sub0_in_VS_32_Lo256RegClassID - 32)) |
607 (1u << (AMDGPU::VS_64_with_sub1_with_sub1_in_VS_32_Lo256RegClassID - 32)) |
608 (1u << (AMDGPU::VS_64_Lo256RegClassID - 32)) |
609 (1u << (AMDGPU::VS_64_Lo256_with_sub1RegClassID - 32)) |
610 (1u << (AMDGPU::VS_64_with_sub0_in_VS_32_Lo128RegClassID - 32)) |
611 (1u << (AMDGPU::VS_64_with_sub1_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID - 32)) |
612 (1u << (AMDGPU::VS_64_with_sub1_with_sub1_in_VS_32_Lo128RegClassID - 32)) |
613 (1u << (AMDGPU::VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID - 32)) |
614 (1u << (AMDGPU::VS_64_with_sub1_and_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID - 32)) |
615 0,
616 // 64-95
617 (1u << (AMDGPU::AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 64)) |
618 (1u << (AMDGPU::VReg_96RegClassID - 64)) |
619 (1u << (AMDGPU::AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID - 64)) |
620 (1u << (AMDGPU::AV_96_with_sub0_in_VGPR_32_Lo256_and_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) |
621 (1u << (AMDGPU::AV_96_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID - 64)) |
622 (1u << (AMDGPU::AV_96_with_hi16_in_VGPR_16_Lo128_and_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) |
623 (1u << (AMDGPU::VReg_96_Align2RegClassID - 64)) |
624 (1u << (AMDGPU::AV_96_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID - 64)) |
625 (1u << (AMDGPU::VReg_96_Lo256_Align2RegClassID - 64)) |
626 (1u << (AMDGPU::AV_96_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 64)) |
627 (1u << (AMDGPU::AV_96_with_sub0_in_VGPR_32_Lo256RegClassID - 64)) |
628 (1u << (AMDGPU::AV_96_with_sub1_in_VGPR_32_Lo256RegClassID - 64)) |
629 (1u << (AMDGPU::AV_96_with_sub2_in_VGPR_32_Lo256RegClassID - 64)) |
630 (1u << (AMDGPU::AV_96_with_hi16_in_VGPR_16_Lo128RegClassID - 64)) |
631 (1u << (AMDGPU::AV_96_with_sub1_in_VGPR_32_Lo128RegClassID - 64)) |
632 (1u << (AMDGPU::AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 64)) |
633 (1u << (AMDGPU::AV_96RegClassID - 64)) |
634 (1u << (AMDGPU::AV_96_Align2RegClassID - 64)) |
635 (1u << (AMDGPU::AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID - 64)) |
636 0,
637 // 96-127
638 (1u << (AMDGPU::AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 96)) |
639 (1u << (AMDGPU::AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 96)) |
640 (1u << (AMDGPU::VReg_128RegClassID - 96)) |
641 (1u << (AMDGPU::VReg_128_Align2RegClassID - 96)) |
642 (1u << (AMDGPU::AV_128_with_sub1_sub2_in_VReg_64_Align2RegClassID - 96)) |
643 (1u << (AMDGPU::AV_128_with_sub0_in_VGPR_32_Lo256RegClassID - 96)) |
644 (1u << (AMDGPU::AV_128_with_sub1_in_VGPR_32_Lo256RegClassID - 96)) |
645 (1u << (AMDGPU::AV_128_with_sub2_in_VGPR_32_Lo256RegClassID - 96)) |
646 (1u << (AMDGPU::AV_128_with_sub3_in_VGPR_32_Lo256RegClassID - 96)) |
647 (1u << (AMDGPU::AV_128RegClassID - 96)) |
648 (1u << (AMDGPU::VS_128RegClassID - 96)) |
649 (1u << (AMDGPU::VS_128_with_hi16RegClassID - 96)) |
650 (1u << (AMDGPU::AV_128_Align2RegClassID - 96)) |
651 (1u << (AMDGPU::AV_128_with_sub1_sub2_in_AV_64_Align2RegClassID - 96)) |
652 (1u << (AMDGPU::VS_128_Align2RegClassID - 96)) |
653 (1u << (AMDGPU::VS_128_Align2_with_hi16RegClassID - 96)) |
654 (1u << (AMDGPU::VS_128_with_hi16_with_sub0_in_VS_32_Lo256RegClassID - 96)) |
655 (1u << (AMDGPU::VS_128_with_hi16_with_sub1_in_VS_32_Lo256RegClassID - 96)) |
656 (1u << (AMDGPU::VS_128_with_hi16_with_sub2_in_VS_32_Lo256RegClassID - 96)) |
657 (1u << (AMDGPU::VS_128_with_hi16_with_sub0_sub1_in_VS_64_Lo256RegClassID - 96)) |
658 (1u << (AMDGPU::VS_128_with_hi16_with_sub3_in_VS_32_Lo256RegClassID - 96)) |
659 (1u << (AMDGPU::VS_128_with_hi16_with_sub2_sub3_in_VS_64_Lo256RegClassID - 96)) |
660 (1u << (AMDGPU::VS_128_with_hi16_with_sub0_in_VS_32_Lo128RegClassID - 96)) |
661 (1u << (AMDGPU::VS_128_with_hi16_with_sub1_in_VS_32_Lo128RegClassID - 96)) |
662 (1u << (AMDGPU::VS_128_with_hi16_with_sub2_in_VS_32_Lo128RegClassID - 96)) |
663 (1u << (AMDGPU::VS_128_with_hi16_with_sub3_in_VS_32_Lo128RegClassID - 96)) |
664 0,
665 // 128-159
666 (1u << (AMDGPU::AV_128_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID - 128)) |
667 (1u << (AMDGPU::VReg_128_Lo256_Align2RegClassID - 128)) |
668 (1u << (AMDGPU::AV_128_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 128)) |
669 (1u << (AMDGPU::AV_128_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 128)) |
670 (1u << (AMDGPU::AV_128_with_sub0_in_VGPR_32_Lo256_and_AV_128_with_sub1_sub2_in_AV_64_Align2RegClassID - 128)) |
671 (1u << (AMDGPU::AV_128_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID - 128)) |
672 (1u << (AMDGPU::AV_128_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID - 128)) |
673 (1u << (AMDGPU::AV_128_with_hi16_in_VGPR_16_Lo128_and_AV_128_with_sub1_sub2_in_AV_64_Align2RegClassID - 128)) |
674 (1u << (AMDGPU::AV_128_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 128)) |
675 (1u << (AMDGPU::AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 128)) |
676 (1u << (AMDGPU::AV_128_with_hi16_in_VGPR_16_Lo128RegClassID - 128)) |
677 (1u << (AMDGPU::AV_128_with_sub1_in_VGPR_32_Lo128RegClassID - 128)) |
678 (1u << (AMDGPU::AV_128_with_sub2_in_VGPR_32_Lo128RegClassID - 128)) |
679 (1u << (AMDGPU::AV_128_with_sub3_in_VGPR_32_Lo128RegClassID - 128)) |
680 (1u << (AMDGPU::VReg_160RegClassID - 128)) |
681 (1u << (AMDGPU::AV_160_with_sub1_sub2_in_VReg_64_Align2RegClassID - 128)) |
682 (1u << (AMDGPU::VS_128_with_hi16_with_sub0_sub1_in_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID - 128)) |
683 (1u << (AMDGPU::VS_128_with_hi16_with_sub2_sub3_in_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID - 128)) |
684 (1u << (AMDGPU::VReg_160_Align2RegClassID - 128)) |
685 (1u << (AMDGPU::AV_160RegClassID - 128)) |
686 (1u << (AMDGPU::AV_160_Align2RegClassID - 128)) |
687 (1u << (AMDGPU::AV_160_with_sub1_sub2_in_AV_64_Align2RegClassID - 128)) |
688 0,
689 // 160-191
690 (1u << (AMDGPU::AV_160_with_sub0_in_VGPR_32_Lo256_and_AV_160_with_sub1_sub2_in_AV_64_Align2RegClassID - 160)) |
691 (1u << (AMDGPU::AV_160_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID - 160)) |
692 (1u << (AMDGPU::AV_160_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID - 160)) |
693 (1u << (AMDGPU::AV_160_with_hi16_in_VGPR_16_Lo128_and_AV_160_with_sub1_sub2_in_AV_64_Align2RegClassID - 160)) |
694 (1u << (AMDGPU::AV_160_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 160)) |
695 (1u << (AMDGPU::AV_160_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 160)) |
696 (1u << (AMDGPU::AV_160_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID - 160)) |
697 (1u << (AMDGPU::AV_160_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID - 160)) |
698 (1u << (AMDGPU::VReg_160_Lo256_Align2RegClassID - 160)) |
699 (1u << (AMDGPU::AV_160_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 160)) |
700 (1u << (AMDGPU::AV_160_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 160)) |
701 (1u << (AMDGPU::AV_160_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 160)) |
702 (1u << (AMDGPU::AV_160_with_sub0_in_VGPR_32_Lo256RegClassID - 160)) |
703 (1u << (AMDGPU::AV_160_with_sub1_in_VGPR_32_Lo256RegClassID - 160)) |
704 (1u << (AMDGPU::AV_160_with_sub2_in_VGPR_32_Lo256RegClassID - 160)) |
705 (1u << (AMDGPU::AV_160_with_sub3_in_VGPR_32_Lo256RegClassID - 160)) |
706 (1u << (AMDGPU::AV_160_with_sub4_in_VGPR_32_Lo256RegClassID - 160)) |
707 (1u << (AMDGPU::AV_160_with_hi16_in_VGPR_16_Lo128RegClassID - 160)) |
708 (1u << (AMDGPU::AV_160_with_sub1_in_VGPR_32_Lo128RegClassID - 160)) |
709 (1u << (AMDGPU::AV_160_with_sub2_in_VGPR_32_Lo128RegClassID - 160)) |
710 (1u << (AMDGPU::AV_160_with_sub3_in_VGPR_32_Lo128RegClassID - 160)) |
711 (1u << (AMDGPU::AV_160_with_sub4_in_VGPR_32_Lo128RegClassID - 160)) |
712 (1u << (AMDGPU::AV_192RegClassID - 160)) |
713 0,
714 // 192-223
715 (1u << (AMDGPU::VReg_192RegClassID - 192)) |
716 (1u << (AMDGPU::VReg_192_Align2RegClassID - 192)) |
717 (1u << (AMDGPU::AV_192_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID - 192)) |
718 (1u << (AMDGPU::AV_192_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID - 192)) |
719 (1u << (AMDGPU::VReg_192_Lo256_Align2RegClassID - 192)) |
720 (1u << (AMDGPU::AV_192_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 192)) |
721 (1u << (AMDGPU::AV_192_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 192)) |
722 (1u << (AMDGPU::AV_192_with_sub1_sub2_in_VReg_64_Align2RegClassID - 192)) |
723 (1u << (AMDGPU::AV_192_with_sub0_in_VGPR_32_Lo256_and_AV_192_with_sub1_sub2_in_AV_64_Align2RegClassID - 192)) |
724 (1u << (AMDGPU::AV_192_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID - 192)) |
725 (1u << (AMDGPU::AV_192_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID - 192)) |
726 (1u << (AMDGPU::AV_192_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID - 192)) |
727 (1u << (AMDGPU::AV_192_with_hi16_in_VGPR_16_Lo128_and_AV_192_with_sub1_sub2_in_AV_64_Align2RegClassID - 192)) |
728 (1u << (AMDGPU::AV_192_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 192)) |
729 (1u << (AMDGPU::AV_192_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 192)) |
730 (1u << (AMDGPU::AV_192_with_sub0_in_VGPR_32_Lo256RegClassID - 192)) |
731 (1u << (AMDGPU::AV_192_with_sub1_in_VGPR_32_Lo256RegClassID - 192)) |
732 (1u << (AMDGPU::AV_192_with_sub2_in_VGPR_32_Lo256RegClassID - 192)) |
733 (1u << (AMDGPU::AV_192_with_sub3_in_VGPR_32_Lo256RegClassID - 192)) |
734 (1u << (AMDGPU::AV_192_with_sub4_in_VGPR_32_Lo256RegClassID - 192)) |
735 (1u << (AMDGPU::AV_192_with_sub5_in_VGPR_32_Lo256RegClassID - 192)) |
736 (1u << (AMDGPU::AV_192_with_hi16_in_VGPR_16_Lo128RegClassID - 192)) |
737 (1u << (AMDGPU::AV_192_with_sub1_in_VGPR_32_Lo128RegClassID - 192)) |
738 (1u << (AMDGPU::AV_192_with_sub2_in_VGPR_32_Lo128RegClassID - 192)) |
739 (1u << (AMDGPU::AV_192_with_sub3_in_VGPR_32_Lo128RegClassID - 192)) |
740 (1u << (AMDGPU::AV_192_with_sub4_in_VGPR_32_Lo128RegClassID - 192)) |
741 (1u << (AMDGPU::AV_192_with_sub5_in_VGPR_32_Lo128RegClassID - 192)) |
742 (1u << (AMDGPU::AV_192_Align2RegClassID - 192)) |
743 (1u << (AMDGPU::AV_192_with_sub1_sub2_in_AV_64_Align2RegClassID - 192)) |
744 0,
745 // 224-255
746 (1u << (AMDGPU::AV_192_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 224)) |
747 (1u << (AMDGPU::AV_192_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 224)) |
748 (1u << (AMDGPU::VReg_224RegClassID - 224)) |
749 (1u << (AMDGPU::AV_224_with_sub1_sub2_in_VReg_64_Align2RegClassID - 224)) |
750 (1u << (AMDGPU::AV_224_with_sub0_in_VGPR_32_Lo256_and_AV_224_with_sub1_sub2_in_AV_64_Align2RegClassID - 224)) |
751 (1u << (AMDGPU::AV_224_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID - 224)) |
752 (1u << (AMDGPU::AV_224_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID - 224)) |
753 (1u << (AMDGPU::VReg_224_Align2RegClassID - 224)) |
754 (1u << (AMDGPU::AV_224_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID - 224)) |
755 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID - 224)) |
756 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID - 224)) |
757 (1u << (AMDGPU::AV_224_with_sub0_in_VGPR_32_Lo256RegClassID - 224)) |
758 (1u << (AMDGPU::AV_224_with_sub1_in_VGPR_32_Lo256RegClassID - 224)) |
759 (1u << (AMDGPU::AV_224_with_sub2_in_VGPR_32_Lo256RegClassID - 224)) |
760 (1u << (AMDGPU::AV_224_with_sub3_in_VGPR_32_Lo256RegClassID - 224)) |
761 (1u << (AMDGPU::AV_224_with_sub4_in_VGPR_32_Lo256RegClassID - 224)) |
762 (1u << (AMDGPU::AV_224_with_sub5_in_VGPR_32_Lo256RegClassID - 224)) |
763 (1u << (AMDGPU::AV_224_with_sub6_in_VGPR_32_Lo256RegClassID - 224)) |
764 (1u << (AMDGPU::AV_224_with_hi16_in_VGPR_16_Lo128RegClassID - 224)) |
765 (1u << (AMDGPU::AV_224_with_sub1_in_VGPR_32_Lo128RegClassID - 224)) |
766 (1u << (AMDGPU::AV_224RegClassID - 224)) |
767 (1u << (AMDGPU::AV_224_Align2RegClassID - 224)) |
768 (1u << (AMDGPU::AV_224_with_sub1_sub2_in_AV_64_Align2RegClassID - 224)) |
769 0,
770 // 256-287
771 (1u << (AMDGPU::AV_224_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID - 256)) |
772 (1u << (AMDGPU::AV_224_with_hi16_in_VGPR_16_Lo128_and_AV_224_with_sub1_sub2_in_AV_64_Align2RegClassID - 256)) |
773 (1u << (AMDGPU::AV_224_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 256)) |
774 (1u << (AMDGPU::AV_224_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) |
775 (1u << (AMDGPU::AV_224_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) |
776 (1u << (AMDGPU::VReg_224_Lo256_Align2RegClassID - 256)) |
777 (1u << (AMDGPU::AV_224_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 256)) |
778 (1u << (AMDGPU::AV_224_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) |
779 (1u << (AMDGPU::AV_224_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) |
780 (1u << (AMDGPU::AV_224_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) |
781 (1u << (AMDGPU::AV_224_with_sub2_in_VGPR_32_Lo128RegClassID - 256)) |
782 (1u << (AMDGPU::AV_224_with_sub3_in_VGPR_32_Lo128RegClassID - 256)) |
783 (1u << (AMDGPU::AV_224_with_sub4_in_VGPR_32_Lo128RegClassID - 256)) |
784 (1u << (AMDGPU::AV_224_with_sub5_in_VGPR_32_Lo128RegClassID - 256)) |
785 (1u << (AMDGPU::AV_224_with_sub6_in_VGPR_32_Lo128RegClassID - 256)) |
786 (1u << (AMDGPU::VReg_256RegClassID - 256)) |
787 (1u << (AMDGPU::VReg_256_Align2RegClassID - 256)) |
788 (1u << (AMDGPU::AV_256_with_sub1_sub2_in_VReg_64_Align2RegClassID - 256)) |
789 (1u << (AMDGPU::AV_256_with_sub0_in_VGPR_32_Lo256RegClassID - 256)) |
790 (1u << (AMDGPU::AV_256RegClassID - 256)) |
791 (1u << (AMDGPU::AV_256_Align2RegClassID - 256)) |
792 (1u << (AMDGPU::AV_256_with_sub1_sub2_in_AV_64_Align2RegClassID - 256)) |
793 0,
794 // 288-319
795 (1u << (AMDGPU::AV_256_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID - 288)) |
796 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID - 288)) |
797 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID - 288)) |
798 (1u << (AMDGPU::VReg_256_Lo256_Align2RegClassID - 288)) |
799 (1u << (AMDGPU::AV_256_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 288)) |
800 (1u << (AMDGPU::AV_256_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 288)) |
801 (1u << (AMDGPU::AV_256_with_sub0_in_VGPR_32_Lo256_and_AV_256_with_sub1_sub2_in_AV_64_Align2RegClassID - 288)) |
802 (1u << (AMDGPU::AV_256_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID - 288)) |
803 (1u << (AMDGPU::AV_256_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID - 288)) |
804 (1u << (AMDGPU::AV_256_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID - 288)) |
805 (1u << (AMDGPU::AV_256_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID - 288)) |
806 (1u << (AMDGPU::AV_256_with_hi16_in_VGPR_16_Lo128_and_AV_256_with_sub1_sub2_in_AV_64_Align2RegClassID - 288)) |
807 (1u << (AMDGPU::AV_256_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 288)) |
808 (1u << (AMDGPU::AV_256_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 288)) |
809 (1u << (AMDGPU::AV_256_with_sub1_in_VGPR_32_Lo256RegClassID - 288)) |
810 (1u << (AMDGPU::AV_256_with_sub2_in_VGPR_32_Lo256RegClassID - 288)) |
811 (1u << (AMDGPU::AV_256_with_sub3_in_VGPR_32_Lo256RegClassID - 288)) |
812 (1u << (AMDGPU::AV_256_with_sub4_in_VGPR_32_Lo256RegClassID - 288)) |
813 (1u << (AMDGPU::AV_256_with_sub5_in_VGPR_32_Lo256RegClassID - 288)) |
814 (1u << (AMDGPU::AV_256_with_sub6_in_VGPR_32_Lo256RegClassID - 288)) |
815 (1u << (AMDGPU::AV_256_with_sub7_in_VGPR_32_Lo256RegClassID - 288)) |
816 (1u << (AMDGPU::AV_256_with_hi16_in_VGPR_16_Lo128RegClassID - 288)) |
817 (1u << (AMDGPU::AV_256_with_sub1_in_VGPR_32_Lo128RegClassID - 288)) |
818 (1u << (AMDGPU::AV_256_with_sub2_in_VGPR_32_Lo128RegClassID - 288)) |
819 (1u << (AMDGPU::AV_256_with_sub3_in_VGPR_32_Lo128RegClassID - 288)) |
820 (1u << (AMDGPU::AV_256_with_sub4_in_VGPR_32_Lo128RegClassID - 288)) |
821 (1u << (AMDGPU::AV_256_with_sub5_in_VGPR_32_Lo128RegClassID - 288)) |
822 (1u << (AMDGPU::AV_256_with_sub6_in_VGPR_32_Lo128RegClassID - 288)) |
823 (1u << (AMDGPU::AV_256_with_sub7_in_VGPR_32_Lo128RegClassID - 288)) |
824 0,
825 // 320-351
826 (1u << (AMDGPU::AV_256_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) |
827 (1u << (AMDGPU::AV_256_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) |
828 (1u << (AMDGPU::AV_256_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) |
829 (1u << (AMDGPU::AV_256_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 320)) |
830 (1u << (AMDGPU::VReg_288RegClassID - 320)) |
831 (1u << (AMDGPU::AV_288_with_sub1_sub2_in_VReg_64_Align2RegClassID - 320)) |
832 (1u << (AMDGPU::AV_288_with_sub0_in_VGPR_32_Lo256_and_AV_288_with_sub1_sub2_in_AV_64_Align2RegClassID - 320)) |
833 (1u << (AMDGPU::VReg_288_Align2RegClassID - 320)) |
834 (1u << (AMDGPU::AV_288_with_sub0_in_VGPR_32_Lo256RegClassID - 320)) |
835 (1u << (AMDGPU::AV_288_with_sub1_in_VGPR_32_Lo256RegClassID - 320)) |
836 (1u << (AMDGPU::AV_288_with_sub2_in_VGPR_32_Lo256RegClassID - 320)) |
837 (1u << (AMDGPU::AV_288_with_sub3_in_VGPR_32_Lo256RegClassID - 320)) |
838 (1u << (AMDGPU::AV_288_with_sub4_in_VGPR_32_Lo256RegClassID - 320)) |
839 (1u << (AMDGPU::AV_288_with_sub5_in_VGPR_32_Lo256RegClassID - 320)) |
840 (1u << (AMDGPU::AV_288_with_sub6_in_VGPR_32_Lo256RegClassID - 320)) |
841 (1u << (AMDGPU::AV_288_with_sub7_in_VGPR_32_Lo256RegClassID - 320)) |
842 (1u << (AMDGPU::AV_288_with_sub8_in_VGPR_32_Lo256RegClassID - 320)) |
843 (1u << (AMDGPU::AV_288_with_hi16_in_VGPR_16_Lo128RegClassID - 320)) |
844 (1u << (AMDGPU::AV_288RegClassID - 320)) |
845 (1u << (AMDGPU::AV_288_Align2RegClassID - 320)) |
846 (1u << (AMDGPU::AV_288_with_sub1_sub2_in_AV_64_Align2RegClassID - 320)) |
847 0,
848 // 352-383
849 (1u << (AMDGPU::AV_288_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID - 352)) |
850 (1u << (AMDGPU::AV_288_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID - 352)) |
851 (1u << (AMDGPU::AV_288_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID - 352)) |
852 (1u << (AMDGPU::AV_288_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID - 352)) |
853 (1u << (AMDGPU::AV_288_with_hi16_in_VGPR_16_Lo128_and_AV_288_with_sub1_sub2_in_AV_64_Align2RegClassID - 352)) |
854 (1u << (AMDGPU::AV_288_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 352)) |
855 (1u << (AMDGPU::AV_288_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 352)) |
856 (1u << (AMDGPU::AV_288_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 352)) |
857 (1u << (AMDGPU::AV_288_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 352)) |
858 (1u << (AMDGPU::AV_288_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID - 352)) |
859 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID - 352)) |
860 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID - 352)) |
861 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClassID - 352)) |
862 (1u << (AMDGPU::VReg_288_Lo256_Align2RegClassID - 352)) |
863 (1u << (AMDGPU::AV_288_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 352)) |
864 (1u << (AMDGPU::AV_288_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 352)) |
865 (1u << (AMDGPU::AV_288_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 352)) |
866 (1u << (AMDGPU::AV_288_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 352)) |
867 (1u << (AMDGPU::AV_288_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 352)) |
868 (1u << (AMDGPU::AV_288_with_sub1_in_VGPR_32_Lo128RegClassID - 352)) |
869 (1u << (AMDGPU::AV_288_with_sub2_in_VGPR_32_Lo128RegClassID - 352)) |
870 (1u << (AMDGPU::AV_288_with_sub3_in_VGPR_32_Lo128RegClassID - 352)) |
871 (1u << (AMDGPU::AV_288_with_sub4_in_VGPR_32_Lo128RegClassID - 352)) |
872 (1u << (AMDGPU::AV_288_with_sub5_in_VGPR_32_Lo128RegClassID - 352)) |
873 (1u << (AMDGPU::AV_288_with_sub6_in_VGPR_32_Lo128RegClassID - 352)) |
874 (1u << (AMDGPU::AV_288_with_sub7_in_VGPR_32_Lo128RegClassID - 352)) |
875 (1u << (AMDGPU::AV_288_with_sub8_in_VGPR_32_Lo128RegClassID - 352)) |
876 0,
877 // 384-415
878 (1u << (AMDGPU::VReg_320RegClassID - 384)) |
879 (1u << (AMDGPU::VReg_320_Align2RegClassID - 384)) |
880 (1u << (AMDGPU::AV_320_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID - 384)) |
881 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID - 384)) |
882 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID - 384)) |
883 (1u << (AMDGPU::AV_320_with_sub1_sub2_in_VReg_64_Align2RegClassID - 384)) |
884 (1u << (AMDGPU::AV_320_with_sub0_in_VGPR_32_Lo256_and_AV_320_with_sub1_sub2_in_AV_64_Align2RegClassID - 384)) |
885 (1u << (AMDGPU::AV_320_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID - 384)) |
886 (1u << (AMDGPU::AV_320_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID - 384)) |
887 (1u << (AMDGPU::AV_320_with_sub0_in_VGPR_32_Lo256RegClassID - 384)) |
888 (1u << (AMDGPU::AV_320_with_sub1_in_VGPR_32_Lo256RegClassID - 384)) |
889 (1u << (AMDGPU::AV_320_with_sub2_in_VGPR_32_Lo256RegClassID - 384)) |
890 (1u << (AMDGPU::AV_320_with_sub3_in_VGPR_32_Lo256RegClassID - 384)) |
891 (1u << (AMDGPU::AV_320_with_sub4_in_VGPR_32_Lo256RegClassID - 384)) |
892 (1u << (AMDGPU::AV_320_with_sub5_in_VGPR_32_Lo256RegClassID - 384)) |
893 (1u << (AMDGPU::AV_320_with_sub6_in_VGPR_32_Lo256RegClassID - 384)) |
894 (1u << (AMDGPU::AV_320_with_sub7_in_VGPR_32_Lo256RegClassID - 384)) |
895 (1u << (AMDGPU::AV_320_with_sub8_in_VGPR_32_Lo256RegClassID - 384)) |
896 (1u << (AMDGPU::AV_320_with_sub9_in_VGPR_32_Lo256RegClassID - 384)) |
897 (1u << (AMDGPU::AV_320_with_hi16_in_VGPR_16_Lo128RegClassID - 384)) |
898 (1u << (AMDGPU::AV_320_with_sub1_in_VGPR_32_Lo128RegClassID - 384)) |
899 (1u << (AMDGPU::AV_320_with_sub2_in_VGPR_32_Lo128RegClassID - 384)) |
900 (1u << (AMDGPU::AV_320RegClassID - 384)) |
901 (1u << (AMDGPU::AV_320_Align2RegClassID - 384)) |
902 (1u << (AMDGPU::AV_320_with_sub1_sub2_in_AV_64_Align2RegClassID - 384)) |
903 0,
904 // 416-447
905 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClassID - 416)) |
906 (1u << (AMDGPU::VReg_320_Lo256_Align2RegClassID - 416)) |
907 (1u << (AMDGPU::AV_320_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 416)) |
908 (1u << (AMDGPU::AV_320_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) |
909 (1u << (AMDGPU::AV_320_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) |
910 (1u << (AMDGPU::AV_320_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) |
911 (1u << (AMDGPU::AV_320_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) |
912 (1u << (AMDGPU::AV_320_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID - 416)) |
913 (1u << (AMDGPU::AV_320_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID - 416)) |
914 (1u << (AMDGPU::AV_320_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClassID - 416)) |
915 (1u << (AMDGPU::AV_320_with_hi16_in_VGPR_16_Lo128_and_AV_320_with_sub1_sub2_in_AV_64_Align2RegClassID - 416)) |
916 (1u << (AMDGPU::AV_320_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 416)) |
917 (1u << (AMDGPU::AV_320_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) |
918 (1u << (AMDGPU::AV_320_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) |
919 (1u << (AMDGPU::AV_320_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) |
920 (1u << (AMDGPU::AV_320_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 416)) |
921 (1u << (AMDGPU::AV_320_with_sub3_in_VGPR_32_Lo128RegClassID - 416)) |
922 (1u << (AMDGPU::AV_320_with_sub4_in_VGPR_32_Lo128RegClassID - 416)) |
923 (1u << (AMDGPU::AV_320_with_sub5_in_VGPR_32_Lo128RegClassID - 416)) |
924 (1u << (AMDGPU::AV_320_with_sub6_in_VGPR_32_Lo128RegClassID - 416)) |
925 (1u << (AMDGPU::AV_320_with_sub7_in_VGPR_32_Lo128RegClassID - 416)) |
926 (1u << (AMDGPU::AV_320_with_sub8_in_VGPR_32_Lo128RegClassID - 416)) |
927 (1u << (AMDGPU::AV_320_with_sub9_in_VGPR_32_Lo128RegClassID - 416)) |
928 0,
929 // 448-479
930 (1u << (AMDGPU::VReg_352RegClassID - 448)) |
931 (1u << (AMDGPU::AV_352_with_sub1_sub2_in_VReg_64_Align2RegClassID - 448)) |
932 (1u << (AMDGPU::AV_352_with_sub0_in_VGPR_32_Lo256_and_AV_352_with_sub1_sub2_in_AV_64_Align2RegClassID - 448)) |
933 (1u << (AMDGPU::AV_352_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID - 448)) |
934 (1u << (AMDGPU::AV_352_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID - 448)) |
935 (1u << (AMDGPU::VReg_352_Align2RegClassID - 448)) |
936 (1u << (AMDGPU::AV_352_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID - 448)) |
937 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID - 448)) |
938 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID - 448)) |
939 (1u << (AMDGPU::AV_352_with_sub0_in_VGPR_32_Lo256RegClassID - 448)) |
940 (1u << (AMDGPU::AV_352_with_sub1_in_VGPR_32_Lo256RegClassID - 448)) |
941 (1u << (AMDGPU::AV_352_with_sub2_in_VGPR_32_Lo256RegClassID - 448)) |
942 (1u << (AMDGPU::AV_352_with_sub3_in_VGPR_32_Lo256RegClassID - 448)) |
943 (1u << (AMDGPU::AV_352_with_sub4_in_VGPR_32_Lo256RegClassID - 448)) |
944 (1u << (AMDGPU::AV_352_with_sub5_in_VGPR_32_Lo256RegClassID - 448)) |
945 (1u << (AMDGPU::AV_352_with_sub6_in_VGPR_32_Lo256RegClassID - 448)) |
946 (1u << (AMDGPU::AV_352_with_sub7_in_VGPR_32_Lo256RegClassID - 448)) |
947 (1u << (AMDGPU::AV_352_with_sub8_in_VGPR_32_Lo256RegClassID - 448)) |
948 (1u << (AMDGPU::AV_352_with_sub9_in_VGPR_32_Lo256RegClassID - 448)) |
949 (1u << (AMDGPU::AV_352_with_sub10_in_VGPR_32_Lo256RegClassID - 448)) |
950 (1u << (AMDGPU::AV_352_with_hi16_in_VGPR_16_Lo128RegClassID - 448)) |
951 (1u << (AMDGPU::AV_352_with_sub1_in_VGPR_32_Lo128RegClassID - 448)) |
952 (1u << (AMDGPU::AV_352RegClassID - 448)) |
953 (1u << (AMDGPU::AV_352_Align2RegClassID - 448)) |
954 (1u << (AMDGPU::AV_352_with_sub1_sub2_in_AV_64_Align2RegClassID - 448)) |
955 0,
956 // 480-511
957 (1u << (AMDGPU::AV_352_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID - 480)) |
958 (1u << (AMDGPU::AV_352_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID - 480)) |
959 (1u << (AMDGPU::AV_352_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClassID - 480)) |
960 (1u << (AMDGPU::AV_352_with_hi16_in_VGPR_16_Lo128_and_AV_352_with_sub1_sub2_in_AV_64_Align2RegClassID - 480)) |
961 (1u << (AMDGPU::AV_352_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 480)) |
962 (1u << (AMDGPU::AV_352_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 480)) |
963 (1u << (AMDGPU::AV_352_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 480)) |
964 (1u << (AMDGPU::AV_352_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 480)) |
965 (1u << (AMDGPU::AV_352_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 480)) |
966 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClassID - 480)) |
967 (1u << (AMDGPU::AV_352_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClassID - 480)) |
968 (1u << (AMDGPU::VReg_352_Lo256_Align2RegClassID - 480)) |
969 (1u << (AMDGPU::AV_352_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 480)) |
970 (1u << (AMDGPU::AV_352_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 480)) |
971 (1u << (AMDGPU::AV_352_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 480)) |
972 (1u << (AMDGPU::AV_352_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 480)) |
973 (1u << (AMDGPU::AV_352_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 480)) |
974 (1u << (AMDGPU::AV_352_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 480)) |
975 (1u << (AMDGPU::AV_352_with_sub2_in_VGPR_32_Lo128RegClassID - 480)) |
976 (1u << (AMDGPU::AV_352_with_sub3_in_VGPR_32_Lo128RegClassID - 480)) |
977 (1u << (AMDGPU::AV_352_with_sub4_in_VGPR_32_Lo128RegClassID - 480)) |
978 (1u << (AMDGPU::AV_352_with_sub5_in_VGPR_32_Lo128RegClassID - 480)) |
979 (1u << (AMDGPU::AV_352_with_sub6_in_VGPR_32_Lo128RegClassID - 480)) |
980 (1u << (AMDGPU::AV_352_with_sub7_in_VGPR_32_Lo128RegClassID - 480)) |
981 (1u << (AMDGPU::AV_352_with_sub8_in_VGPR_32_Lo128RegClassID - 480)) |
982 (1u << (AMDGPU::AV_352_with_sub9_in_VGPR_32_Lo128RegClassID - 480)) |
983 (1u << (AMDGPU::AV_352_with_sub10_in_VGPR_32_Lo128RegClassID - 480)) |
984 0,
985 // 512-543
986 (1u << (AMDGPU::VReg_384RegClassID - 512)) |
987 (1u << (AMDGPU::VReg_384_Align2RegClassID - 512)) |
988 (1u << (AMDGPU::AV_384_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID - 512)) |
989 (1u << (AMDGPU::AV_384_with_sub1_sub2_in_VReg_64_Align2RegClassID - 512)) |
990 (1u << (AMDGPU::AV_384_with_sub0_in_VGPR_32_Lo256_and_AV_384_with_sub1_sub2_in_AV_64_Align2RegClassID - 512)) |
991 (1u << (AMDGPU::AV_384_with_sub0_in_VGPR_32_Lo256RegClassID - 512)) |
992 (1u << (AMDGPU::AV_384_with_sub1_in_VGPR_32_Lo256RegClassID - 512)) |
993 (1u << (AMDGPU::AV_384_with_sub2_in_VGPR_32_Lo256RegClassID - 512)) |
994 (1u << (AMDGPU::AV_384_with_sub3_in_VGPR_32_Lo256RegClassID - 512)) |
995 (1u << (AMDGPU::AV_384_with_sub4_in_VGPR_32_Lo256RegClassID - 512)) |
996 (1u << (AMDGPU::AV_384_with_sub5_in_VGPR_32_Lo256RegClassID - 512)) |
997 (1u << (AMDGPU::AV_384_with_sub6_in_VGPR_32_Lo256RegClassID - 512)) |
998 (1u << (AMDGPU::AV_384_with_sub7_in_VGPR_32_Lo256RegClassID - 512)) |
999 (1u << (AMDGPU::AV_384_with_sub8_in_VGPR_32_Lo256RegClassID - 512)) |
1000 (1u << (AMDGPU::AV_384_with_sub9_in_VGPR_32_Lo256RegClassID - 512)) |
1001 (1u << (AMDGPU::AV_384_with_sub10_in_VGPR_32_Lo256RegClassID - 512)) |
1002 (1u << (AMDGPU::AV_384_with_sub11_in_VGPR_32_Lo256RegClassID - 512)) |
1003 (1u << (AMDGPU::AV_384_with_hi16_in_VGPR_16_Lo128RegClassID - 512)) |
1004 (1u << (AMDGPU::AV_384RegClassID - 512)) |
1005 (1u << (AMDGPU::AV_384_Align2RegClassID - 512)) |
1006 (1u << (AMDGPU::AV_384_with_sub1_sub2_in_AV_64_Align2RegClassID - 512)) |
1007 0,
1008 // 544-575
1009 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID - 544)) |
1010 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID - 544)) |
1011 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClassID - 544)) |
1012 (1u << (AMDGPU::AV_384_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClassID - 544)) |
1013 (1u << (AMDGPU::VReg_384_Lo256_Align2RegClassID - 544)) |
1014 (1u << (AMDGPU::AV_384_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 544)) |
1015 (1u << (AMDGPU::AV_384_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 544)) |
1016 (1u << (AMDGPU::AV_384_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 544)) |
1017 (1u << (AMDGPU::AV_384_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 544)) |
1018 (1u << (AMDGPU::AV_384_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID - 544)) |
1019 (1u << (AMDGPU::AV_384_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID - 544)) |
1020 (1u << (AMDGPU::AV_384_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID - 544)) |
1021 (1u << (AMDGPU::AV_384_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID - 544)) |
1022 (1u << (AMDGPU::AV_384_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClassID - 544)) |
1023 (1u << (AMDGPU::AV_384_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_352_Lo256_Align2RegClassID - 544)) |
1024 (1u << (AMDGPU::AV_384_with_hi16_in_VGPR_16_Lo128_and_AV_384_with_sub1_sub2_in_AV_64_Align2RegClassID - 544)) |
1025 (1u << (AMDGPU::AV_384_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 544)) |
1026 (1u << (AMDGPU::AV_384_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 544)) |
1027 (1u << (AMDGPU::AV_384_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 544)) |
1028 (1u << (AMDGPU::AV_384_with_sub1_in_VGPR_32_Lo128RegClassID - 544)) |
1029 (1u << (AMDGPU::AV_384_with_sub2_in_VGPR_32_Lo128RegClassID - 544)) |
1030 (1u << (AMDGPU::AV_384_with_sub3_in_VGPR_32_Lo128RegClassID - 544)) |
1031 (1u << (AMDGPU::AV_384_with_sub4_in_VGPR_32_Lo128RegClassID - 544)) |
1032 (1u << (AMDGPU::AV_384_with_sub5_in_VGPR_32_Lo128RegClassID - 544)) |
1033 (1u << (AMDGPU::AV_384_with_sub6_in_VGPR_32_Lo128RegClassID - 544)) |
1034 (1u << (AMDGPU::AV_384_with_sub7_in_VGPR_32_Lo128RegClassID - 544)) |
1035 (1u << (AMDGPU::AV_384_with_sub8_in_VGPR_32_Lo128RegClassID - 544)) |
1036 (1u << (AMDGPU::AV_384_with_sub9_in_VGPR_32_Lo128RegClassID - 544)) |
1037 (1u << (AMDGPU::AV_384_with_sub10_in_VGPR_32_Lo128RegClassID - 544)) |
1038 (1u << (AMDGPU::AV_384_with_sub11_in_VGPR_32_Lo128RegClassID - 544)) |
1039 0,
1040 // 576-607
1041 (1u << (AMDGPU::AV_384_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 576)) |
1042 (1u << (AMDGPU::AV_384_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 576)) |
1043 (1u << (AMDGPU::AV_384_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 576)) |
1044 (1u << (AMDGPU::AV_384_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 576)) |
1045 (1u << (AMDGPU::AV_384_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 576)) |
1046 (1u << (AMDGPU::VReg_512RegClassID - 576)) |
1047 (1u << (AMDGPU::VReg_512_Align2RegClassID - 576)) |
1048 (1u << (AMDGPU::AV_512_with_sub1_sub2_in_VReg_64_Align2RegClassID - 576)) |
1049 (1u << (AMDGPU::AV_512_with_sub0_in_VGPR_32_Lo256RegClassID - 576)) |
1050 (1u << (AMDGPU::AV_512_with_sub1_in_VGPR_32_Lo256RegClassID - 576)) |
1051 (1u << (AMDGPU::AV_512_with_sub2_in_VGPR_32_Lo256RegClassID - 576)) |
1052 (1u << (AMDGPU::AV_512_with_sub3_in_VGPR_32_Lo256RegClassID - 576)) |
1053 (1u << (AMDGPU::AV_512_with_sub4_in_VGPR_32_Lo256RegClassID - 576)) |
1054 (1u << (AMDGPU::AV_512_with_sub5_in_VGPR_32_Lo256RegClassID - 576)) |
1055 (1u << (AMDGPU::AV_512_with_sub6_in_VGPR_32_Lo256RegClassID - 576)) |
1056 (1u << (AMDGPU::AV_512RegClassID - 576)) |
1057 (1u << (AMDGPU::AV_512_Align2RegClassID - 576)) |
1058 (1u << (AMDGPU::AV_512_with_sub1_sub2_in_AV_64_Align2RegClassID - 576)) |
1059 0,
1060 // 608-639
1061 (1u << (AMDGPU::AV_512_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID - 608)) |
1062 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID - 608)) |
1063 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID - 608)) |
1064 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClassID - 608)) |
1065 (1u << (AMDGPU::AV_512_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClassID - 608)) |
1066 (1u << (AMDGPU::AV_512_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_384_Lo256_Align2RegClassID - 608)) |
1067 (1u << (AMDGPU::AV_512_with_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_in_VReg_352_Lo256_Align2RegClassID - 608)) |
1068 (1u << (AMDGPU::AV_512_with_sub0_in_VGPR_32_Lo256_and_AV_512_with_sub1_sub2_in_AV_64_Align2RegClassID - 608)) |
1069 (1u << (AMDGPU::AV_512_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID - 608)) |
1070 (1u << (AMDGPU::AV_512_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID - 608)) |
1071 (1u << (AMDGPU::AV_512_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID - 608)) |
1072 (1u << (AMDGPU::AV_512_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID - 608)) |
1073 (1u << (AMDGPU::AV_512_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClassID - 608)) |
1074 (1u << (AMDGPU::AV_512_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_352_Lo256_Align2RegClassID - 608)) |
1075 (1u << (AMDGPU::AV_512_with_sub7_in_VGPR_32_Lo256RegClassID - 608)) |
1076 (1u << (AMDGPU::AV_512_with_sub8_in_VGPR_32_Lo256RegClassID - 608)) |
1077 (1u << (AMDGPU::AV_512_with_sub9_in_VGPR_32_Lo256RegClassID - 608)) |
1078 (1u << (AMDGPU::AV_512_with_sub10_in_VGPR_32_Lo256RegClassID - 608)) |
1079 (1u << (AMDGPU::AV_512_with_sub11_in_VGPR_32_Lo256RegClassID - 608)) |
1080 (1u << (AMDGPU::AV_512_with_sub12_in_VGPR_32_Lo256RegClassID - 608)) |
1081 (1u << (AMDGPU::AV_512_with_sub13_in_VGPR_32_Lo256RegClassID - 608)) |
1082 (1u << (AMDGPU::AV_512_with_sub14_in_VGPR_32_Lo256RegClassID - 608)) |
1083 (1u << (AMDGPU::AV_512_with_sub15_in_VGPR_32_Lo256RegClassID - 608)) |
1084 (1u << (AMDGPU::AV_512_with_hi16_in_VGPR_16_Lo128RegClassID - 608)) |
1085 (1u << (AMDGPU::AV_512_with_sub1_in_VGPR_32_Lo128RegClassID - 608)) |
1086 (1u << (AMDGPU::AV_512_with_sub2_in_VGPR_32_Lo128RegClassID - 608)) |
1087 (1u << (AMDGPU::AV_512_with_sub3_in_VGPR_32_Lo128RegClassID - 608)) |
1088 (1u << (AMDGPU::AV_512_with_sub4_in_VGPR_32_Lo128RegClassID - 608)) |
1089 (1u << (AMDGPU::AV_512_with_sub5_in_VGPR_32_Lo128RegClassID - 608)) |
1090 (1u << (AMDGPU::AV_512_with_sub6_in_VGPR_32_Lo128RegClassID - 608)) |
1091 0,
1092 // 640-671
1093 (1u << (AMDGPU::VReg_512_Lo256_Align2RegClassID - 640)) |
1094 (1u << (AMDGPU::AV_512_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 640)) |
1095 (1u << (AMDGPU::AV_512_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1096 (1u << (AMDGPU::AV_512_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1097 (1u << (AMDGPU::AV_512_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1098 (1u << (AMDGPU::AV_512_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1099 (1u << (AMDGPU::AV_512_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1100 (1u << (AMDGPU::AV_512_with_sub10_sub11_sub12_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1101 (1u << (AMDGPU::AV_512_with_sub12_sub13_sub14_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1102 (1u << (AMDGPU::AV_512_with_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_VReg_352_Lo256_Align2RegClassID - 640)) |
1103 (1u << (AMDGPU::AV_512_with_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_VReg_352_Lo256_Align2RegClassID - 640)) |
1104 (1u << (AMDGPU::AV_512_with_hi16_in_VGPR_16_Lo128_and_AV_512_with_sub1_sub2_in_AV_64_Align2RegClassID - 640)) |
1105 (1u << (AMDGPU::AV_512_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 640)) |
1106 (1u << (AMDGPU::AV_512_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1107 (1u << (AMDGPU::AV_512_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1108 (1u << (AMDGPU::AV_512_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1109 (1u << (AMDGPU::AV_512_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1110 (1u << (AMDGPU::AV_512_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1111 (1u << (AMDGPU::AV_512_with_sub11_sub12_sub13_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1112 (1u << (AMDGPU::AV_512_with_sub13_sub14_sub15_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 640)) |
1113 (1u << (AMDGPU::AV_512_with_sub7_in_VGPR_32_Lo128RegClassID - 640)) |
1114 (1u << (AMDGPU::AV_512_with_sub8_in_VGPR_32_Lo128RegClassID - 640)) |
1115 (1u << (AMDGPU::AV_512_with_sub9_in_VGPR_32_Lo128RegClassID - 640)) |
1116 (1u << (AMDGPU::AV_512_with_sub10_in_VGPR_32_Lo128RegClassID - 640)) |
1117 (1u << (AMDGPU::AV_512_with_sub11_in_VGPR_32_Lo128RegClassID - 640)) |
1118 (1u << (AMDGPU::AV_512_with_sub12_in_VGPR_32_Lo128RegClassID - 640)) |
1119 (1u << (AMDGPU::AV_512_with_sub13_in_VGPR_32_Lo128RegClassID - 640)) |
1120 (1u << (AMDGPU::AV_512_with_sub14_in_VGPR_32_Lo128RegClassID - 640)) |
1121 (1u << (AMDGPU::AV_512_with_sub15_in_VGPR_32_Lo128RegClassID - 640)) |
1122 0,
1123 // 672-703
1124 (1u << (AMDGPU::VReg_1024RegClassID - 672)) |
1125 (1u << (AMDGPU::VReg_1024_Align2RegClassID - 672)) |
1126 (1u << (AMDGPU::AV_1024_with_sub1_sub2_in_VReg_64_Align2RegClassID - 672)) |
1127 (1u << (AMDGPU::AV_1024_with_sub0_in_VGPR_32_Lo256RegClassID - 672)) |
1128 (1u << (AMDGPU::AV_1024_with_sub1_in_VGPR_32_Lo256RegClassID - 672)) |
1129 (1u << (AMDGPU::AV_1024_with_sub2_in_VGPR_32_Lo256RegClassID - 672)) |
1130 (1u << (AMDGPU::AV_1024_with_sub3_in_VGPR_32_Lo256RegClassID - 672)) |
1131 (1u << (AMDGPU::AV_1024_with_sub4_in_VGPR_32_Lo256RegClassID - 672)) |
1132 (1u << (AMDGPU::AV_1024_with_sub5_in_VGPR_32_Lo256RegClassID - 672)) |
1133 (1u << (AMDGPU::AV_1024_with_sub6_in_VGPR_32_Lo256RegClassID - 672)) |
1134 0,
1135 // 704-735
1136 (1u << (AMDGPU::AV_1024_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID - 704)) |
1137 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID - 704)) |
1138 (1u << (AMDGPU::AV_1024_with_sub0_in_VGPR_32_Lo256_and_AV_1024_with_sub1_sub2_in_AV_64_Align2RegClassID - 704)) |
1139 (1u << (AMDGPU::AV_1024_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID - 704)) |
1140 (1u << (AMDGPU::AV_1024_with_sub7_in_VGPR_32_Lo256RegClassID - 704)) |
1141 (1u << (AMDGPU::AV_1024_with_sub8_in_VGPR_32_Lo256RegClassID - 704)) |
1142 (1u << (AMDGPU::AV_1024_with_sub9_in_VGPR_32_Lo256RegClassID - 704)) |
1143 (1u << (AMDGPU::AV_1024_with_sub10_in_VGPR_32_Lo256RegClassID - 704)) |
1144 (1u << (AMDGPU::AV_1024_with_sub11_in_VGPR_32_Lo256RegClassID - 704)) |
1145 (1u << (AMDGPU::AV_1024_with_sub12_in_VGPR_32_Lo256RegClassID - 704)) |
1146 (1u << (AMDGPU::AV_1024_with_sub13_in_VGPR_32_Lo256RegClassID - 704)) |
1147 (1u << (AMDGPU::AV_1024_with_sub14_in_VGPR_32_Lo256RegClassID - 704)) |
1148 (1u << (AMDGPU::AV_1024_with_sub15_in_VGPR_32_Lo256RegClassID - 704)) |
1149 (1u << (AMDGPU::AV_1024_with_sub16_in_VGPR_32_Lo256RegClassID - 704)) |
1150 (1u << (AMDGPU::AV_1024_with_sub17_in_VGPR_32_Lo256RegClassID - 704)) |
1151 (1u << (AMDGPU::AV_1024_with_sub18_in_VGPR_32_Lo256RegClassID - 704)) |
1152 (1u << (AMDGPU::AV_1024_with_sub19_in_VGPR_32_Lo256RegClassID - 704)) |
1153 (1u << (AMDGPU::AV_1024_with_sub20_in_VGPR_32_Lo256RegClassID - 704)) |
1154 (1u << (AMDGPU::AV_1024_with_sub21_in_VGPR_32_Lo256RegClassID - 704)) |
1155 (1u << (AMDGPU::AV_1024_with_sub22_in_VGPR_32_Lo256RegClassID - 704)) |
1156 (1u << (AMDGPU::AV_1024_with_sub23_in_VGPR_32_Lo256RegClassID - 704)) |
1157 (1u << (AMDGPU::AV_1024_with_sub24_in_VGPR_32_Lo256RegClassID - 704)) |
1158 (1u << (AMDGPU::AV_1024_with_sub25_in_VGPR_32_Lo256RegClassID - 704)) |
1159 (1u << (AMDGPU::AV_1024_with_sub26_in_VGPR_32_Lo256RegClassID - 704)) |
1160 (1u << (AMDGPU::AV_1024_with_sub27_in_VGPR_32_Lo256RegClassID - 704)) |
1161 (1u << (AMDGPU::AV_1024_with_sub28_in_VGPR_32_Lo256RegClassID - 704)) |
1162 (1u << (AMDGPU::AV_1024_with_sub29_in_VGPR_32_Lo256RegClassID - 704)) |
1163 (1u << (AMDGPU::AV_1024_with_sub30_in_VGPR_32_Lo256RegClassID - 704)) |
1164 (1u << (AMDGPU::AV_1024_with_sub31_in_VGPR_32_Lo256RegClassID - 704)) |
1165 (1u << (AMDGPU::AV_1024_with_hi16_in_VGPR_16_Lo128RegClassID - 704)) |
1166 (1u << (AMDGPU::AV_1024_with_sub1_in_VGPR_32_Lo128RegClassID - 704)) |
1167 0,
1168 // 736-767
1169 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID - 736)) |
1170 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClassID - 736)) |
1171 (1u << (AMDGPU::AV_1024_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClassID - 736)) |
1172 (1u << (AMDGPU::AV_1024_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_384_Lo256_Align2RegClassID - 736)) |
1173 (1u << (AMDGPU::AV_1024_with_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_in_VReg_352_Lo256_Align2RegClassID - 736)) |
1174 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_VReg_512_Lo256_Align2RegClassID - 736)) |
1175 (1u << (AMDGPU::AV_1024_with_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_in_VReg_352_Lo256_Align2RegClassID - 736)) |
1176 (1u << (AMDGPU::AV_1024_with_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_in_VReg_352_Lo256_Align2RegClassID - 736)) |
1177 (1u << (AMDGPU::AV_1024_with_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_in_VReg_352_Lo256_Align2RegClassID - 736)) |
1178 (1u << (AMDGPU::AV_1024_with_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_in_VReg_352_Lo256_Align2RegClassID - 736)) |
1179 (1u << (AMDGPU::AV_1024_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID - 736)) |
1180 (1u << (AMDGPU::AV_1024_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID - 736)) |
1181 (1u << (AMDGPU::AV_1024_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID - 736)) |
1182 (1u << (AMDGPU::AV_1024_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClassID - 736)) |
1183 (1u << (AMDGPU::AV_1024_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_352_Lo256_Align2RegClassID - 736)) |
1184 (1u << (AMDGPU::AV_1024_with_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_VReg_352_Lo256_Align2RegClassID - 736)) |
1185 (1u << (AMDGPU::AV_1024_with_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_VReg_352_Lo256_Align2RegClassID - 736)) |
1186 (1u << (AMDGPU::AV_1024_with_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_in_VReg_352_Lo256_Align2RegClassID - 736)) |
1187 (1u << (AMDGPU::AV_1024_with_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_in_VReg_352_Lo256_Align2RegClassID - 736)) |
1188 (1u << (AMDGPU::AV_1024_with_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_in_VReg_352_Lo256_Align2RegClassID - 736)) |
1189 (1u << (AMDGPU::AV_1024_with_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_in_VReg_352_Lo256_Align2RegClassID - 736)) |
1190 (1u << (AMDGPU::AV_1024_with_sub2_in_VGPR_32_Lo128RegClassID - 736)) |
1191 (1u << (AMDGPU::AV_1024_with_sub3_in_VGPR_32_Lo128RegClassID - 736)) |
1192 (1u << (AMDGPU::AV_1024_with_sub4_in_VGPR_32_Lo128RegClassID - 736)) |
1193 (1u << (AMDGPU::AV_1024_with_sub5_in_VGPR_32_Lo128RegClassID - 736)) |
1194 (1u << (AMDGPU::AV_1024_with_sub6_in_VGPR_32_Lo128RegClassID - 736)) |
1195 (1u << (AMDGPU::AV_1024_with_sub7_in_VGPR_32_Lo128RegClassID - 736)) |
1196 (1u << (AMDGPU::AV_1024_with_sub8_in_VGPR_32_Lo128RegClassID - 736)) |
1197 (1u << (AMDGPU::AV_1024_with_sub9_in_VGPR_32_Lo128RegClassID - 736)) |
1198 (1u << (AMDGPU::AV_1024_with_sub10_in_VGPR_32_Lo128RegClassID - 736)) |
1199 (1u << (AMDGPU::AV_1024_with_sub11_in_VGPR_32_Lo128RegClassID - 736)) |
1200 (1u << (AMDGPU::AV_1024_with_sub12_in_VGPR_32_Lo128RegClassID - 736)) |
1201 0,
1202 // 768-799
1203 (1u << (AMDGPU::AV_1024_with_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_in_VReg_352_Lo256_Align2RegClassID - 768)) |
1204 (1u << (AMDGPU::AV_1024_with_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_in_VReg_352_Lo256_Align2RegClassID - 768)) |
1205 (1u << (AMDGPU::AV_1024_with_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_in_VReg_352_Lo256_Align2RegClassID - 768)) |
1206 (1u << (AMDGPU::VReg_1024_Lo256_Align2RegClassID - 768)) |
1207 (1u << (AMDGPU::AV_1024_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 768)) |
1208 (1u << (AMDGPU::AV_1024_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 768)) |
1209 (1u << (AMDGPU::AV_1024_with_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_in_VReg_352_Lo256_Align2RegClassID - 768)) |
1210 (1u << (AMDGPU::AV_1024_with_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_in_VReg_352_Lo256_Align2RegClassID - 768)) |
1211 (1u << (AMDGPU::AV_1024_with_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_in_VReg_352_Lo256_Align2RegClassID - 768)) |
1212 (1u << (AMDGPU::AV_1024_with_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16_in_VReg_352_Lo256_Align2RegClassID - 768)) |
1213 (1u << (AMDGPU::AV_1024_with_hi16_in_VGPR_16_Lo128_and_AV_1024_with_sub1_sub2_in_AV_64_Align2RegClassID - 768)) |
1214 (1u << (AMDGPU::AV_1024_with_sub13_in_VGPR_32_Lo128RegClassID - 768)) |
1215 (1u << (AMDGPU::AV_1024_with_sub14_in_VGPR_32_Lo128RegClassID - 768)) |
1216 (1u << (AMDGPU::AV_1024_with_sub15_in_VGPR_32_Lo128RegClassID - 768)) |
1217 (1u << (AMDGPU::AV_1024_with_sub16_in_VGPR_32_Lo128RegClassID - 768)) |
1218 (1u << (AMDGPU::AV_1024_with_sub17_in_VGPR_32_Lo128RegClassID - 768)) |
1219 (1u << (AMDGPU::AV_1024_with_sub18_in_VGPR_32_Lo128RegClassID - 768)) |
1220 (1u << (AMDGPU::AV_1024_with_sub19_in_VGPR_32_Lo128RegClassID - 768)) |
1221 (1u << (AMDGPU::AV_1024_with_sub20_in_VGPR_32_Lo128RegClassID - 768)) |
1222 (1u << (AMDGPU::AV_1024_with_sub21_in_VGPR_32_Lo128RegClassID - 768)) |
1223 (1u << (AMDGPU::AV_1024_with_sub22_in_VGPR_32_Lo128RegClassID - 768)) |
1224 (1u << (AMDGPU::AV_1024_with_sub23_in_VGPR_32_Lo128RegClassID - 768)) |
1225 (1u << (AMDGPU::AV_1024_with_sub24_in_VGPR_32_Lo128RegClassID - 768)) |
1226 (1u << (AMDGPU::AV_1024_with_sub25_in_VGPR_32_Lo128RegClassID - 768)) |
1227 (1u << (AMDGPU::AV_1024_with_sub26_in_VGPR_32_Lo128RegClassID - 768)) |
1228 (1u << (AMDGPU::AV_1024_with_sub27_in_VGPR_32_Lo128RegClassID - 768)) |
1229 (1u << (AMDGPU::AV_1024_with_sub28_in_VGPR_32_Lo128RegClassID - 768)) |
1230 (1u << (AMDGPU::AV_1024_with_sub29_in_VGPR_32_Lo128RegClassID - 768)) |
1231 (1u << (AMDGPU::AV_1024_with_sub30_in_VGPR_32_Lo128RegClassID - 768)) |
1232 (1u << (AMDGPU::AV_1024_with_sub31_in_VGPR_32_Lo128RegClassID - 768)) |
1233 0,
1234 // 800-831
1235 (1u << (AMDGPU::AV_1024_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1236 (1u << (AMDGPU::AV_1024_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1237 (1u << (AMDGPU::AV_1024_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1238 (1u << (AMDGPU::AV_1024_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1239 (1u << (AMDGPU::AV_1024_with_sub10_sub11_sub12_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1240 (1u << (AMDGPU::AV_1024_with_sub12_sub13_sub14_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1241 (1u << (AMDGPU::AV_1024_with_sub14_sub15_sub16_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1242 (1u << (AMDGPU::AV_1024_with_sub16_sub17_sub18_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1243 (1u << (AMDGPU::AV_1024_with_sub18_sub19_sub20_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1244 (1u << (AMDGPU::AV_1024_with_sub20_sub21_sub22_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1245 (1u << (AMDGPU::AV_1024_with_sub22_sub23_sub24_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1246 (1u << (AMDGPU::AV_1024_with_sub24_sub25_sub26_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1247 (1u << (AMDGPU::AV_1024_with_sub26_sub27_sub28_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1248 (1u << (AMDGPU::AV_1024_with_sub28_sub29_sub30_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1249 (1u << (AMDGPU::AV_1024_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID - 800)) |
1250 (1u << (AMDGPU::AV_1024_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1251 (1u << (AMDGPU::AV_1024_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1252 (1u << (AMDGPU::AV_1024_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1253 (1u << (AMDGPU::AV_1024_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1254 (1u << (AMDGPU::AV_1024_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1255 (1u << (AMDGPU::AV_1024_with_sub11_sub12_sub13_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1256 (1u << (AMDGPU::AV_1024_with_sub13_sub14_sub15_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1257 (1u << (AMDGPU::AV_1024_with_sub15_sub16_sub17_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1258 (1u << (AMDGPU::AV_1024_with_sub17_sub18_sub19_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1259 (1u << (AMDGPU::AV_1024_with_sub19_sub20_sub21_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1260 (1u << (AMDGPU::AV_1024_with_sub21_sub22_sub23_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1261 (1u << (AMDGPU::AV_1024_with_sub23_sub24_sub25_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1262 (1u << (AMDGPU::AV_1024_with_sub25_sub26_sub27_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1263 (1u << (AMDGPU::AV_1024_with_sub27_sub28_sub29_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1264 (1u << (AMDGPU::AV_1024_with_sub29_sub30_sub31_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID - 800)) |
1265 0,
1266 // 832-863
1267 0,
1268 // 864-895
1269 0,
1270};
1271
1272constexpr RegisterBank AGPRRegBank(/* ID */ AMDGPU::AGPRRegBankID, /* Name */ "AGPR", /* CoveredRegClasses */ AGPRRegBankCoverageData, /* NumRegClasses */ 896);
1273constexpr RegisterBank SGPRRegBank(/* ID */ AMDGPU::SGPRRegBankID, /* Name */ "SGPR", /* CoveredRegClasses */ SGPRRegBankCoverageData, /* NumRegClasses */ 896);
1274constexpr RegisterBank VCCRegBank(/* ID */ AMDGPU::VCCRegBankID, /* Name */ "VCC", /* CoveredRegClasses */ VCCRegBankCoverageData, /* NumRegClasses */ 896);
1275constexpr RegisterBank VGPRRegBank(/* ID */ AMDGPU::VGPRRegBankID, /* Name */ "VGPR", /* CoveredRegClasses */ VGPRRegBankCoverageData, /* NumRegClasses */ 896);
1276
1277} // namespace AMDGPU
1278
1279const RegisterBank *AMDGPUGenRegisterBankInfo::RegBanks[] = {
1280 &AMDGPU::AGPRRegBank,
1281 &AMDGPU::SGPRRegBank,
1282 &AMDGPU::VCCRegBank,
1283 &AMDGPU::VGPRRegBank,
1284};
1285
1286const unsigned AMDGPUGenRegisterBankInfo::Sizes[] = {
1287 // Mode = 0 (Default)
1288 1024,
1289 1024,
1290 64,
1291 1024,
1292 // Mode = 1 (AVAlign2LoadStoreMode)
1293 1024,
1294 1024,
1295 64,
1296 1024,
1297 // Mode = 2 (AlignedVGPRNoAGPRMode_Wave32)
1298 1024,
1299 1024,
1300 64,
1301 1024,
1302 // Mode = 3 (AlignedVGPRNoAGPRMode_Wave64)
1303 1024,
1304 1024,
1305 64,
1306 1024,
1307 // Mode = 4 (anonymous_14566)
1308 1024,
1309 1024,
1310 64,
1311 1024,
1312};
1313
1314AMDGPUGenRegisterBankInfo::AMDGPUGenRegisterBankInfo(unsigned HwMode)
1315 : RegisterBankInfo(RegBanks, AMDGPU::NumRegisterBanks, Sizes, HwMode) {
1316 // Assert that RegBank indices match their ID's
1317#ifndef NDEBUG
1318 for (auto RB : enumerate(RegBanks))
1319 assert(RB.index() == RB.value()->getID() && "Index != ID");
1320#endif // NDEBUG
1321}
1322
1323const RegisterBank &
1324AMDGPUGenRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const {
1325 constexpr uint32_t InvalidRegBankID = uint32_t(AMDGPU::InvalidRegBankID) & 15;
1326 static const uint32_t RegClass2RegBank[112] = {
1327 (uint32_t(InvalidRegBankID) << 0) |
1328 (uint32_t(InvalidRegBankID) << 4) |
1329 (uint32_t(InvalidRegBankID) << 8) | // VS_16RegClassID
1330 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // VGPR_16RegClassID
1331 (uint32_t(InvalidRegBankID) << 16) | // VS_16_Lo128RegClassID
1332 (uint32_t(AMDGPU::AGPRRegBankID) << 20) | // AGPR_LO16RegClassID
1333 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // VGPR_16_Lo128RegClassID
1334 (uint32_t(InvalidRegBankID) << 28), // SReg_LO16RegClassID
1335 (uint32_t(InvalidRegBankID) << 0) | // VS_16_with_hi16RegClassID
1336 (uint32_t(InvalidRegBankID) << 4) |
1337 (uint32_t(InvalidRegBankID) << 8) | // SGPR_LO16RegClassID
1338 (uint32_t(InvalidRegBankID) << 12) | // VS_16_with_hi16_with_lo16_in_SGPR_LO16RegClassID
1339 (uint32_t(InvalidRegBankID) << 16) | // TTMP_LO16RegClassID
1340 (uint32_t(InvalidRegBankID) << 20) | // VS_16_with_hi16_with_lo16_in_TTMP_LO16RegClassID
1341 (uint32_t(InvalidRegBankID) << 24) | // AV_32RegClassID
1342 (uint32_t(InvalidRegBankID) << 28), // VS_32RegClassID
1343 (uint32_t(InvalidRegBankID) << 0) | // VS_32_with_hi16RegClassID
1344 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // VRegOrLds_32RegClassID
1345 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // VGPR_32RegClassID
1346 (uint32_t(InvalidRegBankID) << 12) | // VS_32_Lo256RegClassID
1347 (uint32_t(InvalidRegBankID) << 16) | // VS_32_Lo256_with_hi16RegClassID
1348 (uint32_t(InvalidRegBankID) << 20) | // VS_32_Lo128RegClassID
1349 (uint32_t(InvalidRegBankID) << 24) | // VS_32_Lo128_with_hi16RegClassID
1350 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VRegOrLds_32_and_VS_32_Lo256RegClassID
1351 (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AGPR_32RegClassID
1352 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // VGPR_32_Lo256RegClassID
1353 (uint32_t(InvalidRegBankID) << 8) | // SRegOrLds_32RegClassID
1354 (uint32_t(InvalidRegBankID) << 12) | // SReg_32RegClassID
1355 (uint32_t(InvalidRegBankID) << 16) | // SReg_32_XEXEC_HIRegClassID
1356 (uint32_t(InvalidRegBankID) << 20) | // SReg_32_XM0RegClassID
1357 (uint32_t(InvalidRegBankID) << 24) | // SReg_32_XEXECRegClassID
1358 (uint32_t(InvalidRegBankID) << 28), // SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID
1359 (uint32_t(InvalidRegBankID) << 0) | // SReg_32_XM0_XEXECRegClassID
1360 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // VRegOrLds_32_and_VS_32_Lo128RegClassID
1361 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // VGPR_32_Lo128RegClassID
1362 (uint32_t(InvalidRegBankID) << 12) | // SGPR_32RegClassID
1363 (uint32_t(InvalidRegBankID) << 16) | // TTMP_32RegClassID
1364 (uint32_t(InvalidRegBankID) << 20) |
1365 (uint32_t(InvalidRegBankID) << 24) |
1366 (uint32_t(InvalidRegBankID) << 28), // AV_64RegClassID
1367 (uint32_t(InvalidRegBankID) << 0) | // VS_64RegClassID
1368 (uint32_t(InvalidRegBankID) << 4) | // VS_64_with_sub1RegClassID
1369 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // VReg_64RegClassID
1370 (uint32_t(InvalidRegBankID) << 12) | // AV_64_Align2RegClassID
1371 (uint32_t(InvalidRegBankID) << 16) | // VS_64_Align2RegClassID
1372 (uint32_t(InvalidRegBankID) << 20) | // VS_64_Align2_with_sub1RegClassID
1373 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // VReg_64_Align2RegClassID
1374 (uint32_t(InvalidRegBankID) << 28), // VS_64_with_sub0_in_VS_32_Lo256RegClassID
1375 (uint32_t(InvalidRegBankID) << 0) | // VS_64_with_sub1_and_VS_64_with_sub0_in_VS_32_Lo256RegClassID
1376 (uint32_t(InvalidRegBankID) << 4) | // VS_64_with_sub1_with_sub1_in_VS_32_Lo256RegClassID
1377 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_64_with_sub0_in_VGPR_32_Lo256RegClassID
1378 (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_64RegClassID
1379 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_64_with_sub1_in_VGPR_32_Lo256RegClassID
1380 (uint32_t(InvalidRegBankID) << 20) | // VS_64_Lo256RegClassID
1381 (uint32_t(InvalidRegBankID) << 24) | // VS_64_with_sub0_in_VS_32_Lo128RegClassID
1382 (uint32_t(InvalidRegBankID) << 28), // VS_64_Lo256_with_sub1RegClassID
1383 (uint32_t(InvalidRegBankID) << 0) | // VS_64_with_sub1_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID
1384 (uint32_t(InvalidRegBankID) << 4) | // VS_64_with_sub1_with_sub1_in_VS_32_Lo128RegClassID
1385 (uint32_t(InvalidRegBankID) << 8) | // VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID
1386 (uint32_t(InvalidRegBankID) << 12) | // VS_64_with_sub1_and_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID
1387 (uint32_t(AMDGPU::AGPRRegBankID) << 16) | // AReg_64_Align2RegClassID
1388 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1389 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // VReg_64_Lo256_Align2RegClassID
1390 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_64_with_sub1_in_VGPR_32_Lo128RegClassID
1391 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SReg_64_EncodableRegClassID
1392 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SReg_64_Encodable_with_sub0_in_SReg_32_XEXECRegClassID
1393 (uint32_t(InvalidRegBankID) << 8) | // SReg_64RegClassID
1394 (uint32_t(InvalidRegBankID) << 12) | // SReg_64_XEXECRegClassID
1395 (uint32_t(InvalidRegBankID) << 16) | // SReg_64_XEXEC_XNULLRegClassID
1396 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1397 (uint32_t(InvalidRegBankID) << 24) | // SGPR_64RegClassID
1398 (uint32_t(InvalidRegBankID) << 28), // CCR_SGPR_64RegClassID
1399 (uint32_t(InvalidRegBankID) << 0) | // Gfx_CCR_SGPR_64RegClassID
1400 (uint32_t(InvalidRegBankID) << 4) | // TTMP_64RegClassID
1401 (uint32_t(InvalidRegBankID) << 8) |
1402 (uint32_t(InvalidRegBankID) << 12) | // AV_96RegClassID
1403 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // VReg_96RegClassID
1404 (uint32_t(InvalidRegBankID) << 20) | // AV_96_Align2RegClassID
1405 (uint32_t(InvalidRegBankID) << 24) | // AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID
1406 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_96_with_sub1_sub2_in_VReg_64_Align2RegClassID
1407 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // VReg_96_Align2RegClassID
1408 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_96_with_sub0_in_VGPR_32_Lo256RegClassID
1409 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_96_with_sub1_in_VGPR_32_Lo256RegClassID
1410 (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_96RegClassID
1411 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_96_with_sub2_in_VGPR_32_Lo256RegClassID
1412 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_96_with_hi16_in_VGPR_16_Lo128RegClassID
1413 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_96_with_sub0_in_VGPR_32_Lo256_and_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID
1414 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_96_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID
1415 (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AReg_96_Align2RegClassID
1416 (uint32_t(AMDGPU::AGPRRegBankID) << 4) | // AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClassID
1417 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_96_with_sub1_in_VGPR_32_Lo128RegClassID
1418 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_96_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID
1419 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // VReg_96_Lo256_Align2RegClassID
1420 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1421 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_96_with_hi16_in_VGPR_16_Lo128_and_AV_96_with_sub1_sub2_in_AV_64_Align2RegClassID
1422 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_96_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1423 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1424 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1425 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SReg_96RegClassID
1426 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_96RegClassID
1427 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_96_with_sub0_sub1_in_CCR_SGPR_64RegClassID
1428 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_96_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID
1429 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // TTMP_96RegClassID
1430 (uint32_t(InvalidRegBankID) << 28), // AV_128RegClassID
1431 (uint32_t(InvalidRegBankID) << 0) | // VS_128RegClassID
1432 (uint32_t(InvalidRegBankID) << 4) | // VS_128_with_hi16RegClassID
1433 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // VReg_128RegClassID
1434 (uint32_t(InvalidRegBankID) << 12) | // AV_128_Align2RegClassID
1435 (uint32_t(InvalidRegBankID) << 16) | // AV_128_with_sub1_sub2_in_AV_64_Align2RegClassID
1436 (uint32_t(InvalidRegBankID) << 20) | // VS_128_Align2RegClassID
1437 (uint32_t(InvalidRegBankID) << 24) | // VS_128_Align2_with_hi16RegClassID
1438 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_128_Align2RegClassID
1439 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_128_with_sub1_sub2_in_VReg_64_Align2RegClassID
1440 (uint32_t(InvalidRegBankID) << 4) | // VS_128_with_hi16_with_sub0_in_VS_32_Lo256RegClassID
1441 (uint32_t(InvalidRegBankID) << 8) | // VS_128_with_hi16_with_sub1_in_VS_32_Lo256RegClassID
1442 (uint32_t(InvalidRegBankID) << 12) | // VS_128_with_hi16_with_sub2_in_VS_32_Lo256RegClassID
1443 (uint32_t(InvalidRegBankID) << 16) | // VS_128_with_hi16_with_sub3_in_VS_32_Lo256RegClassID
1444 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_128_with_sub0_in_VGPR_32_Lo256RegClassID
1445 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_128_with_sub1_in_VGPR_32_Lo256RegClassID
1446 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_128_with_sub2_in_VGPR_32_Lo256RegClassID
1447 (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AReg_128RegClassID
1448 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_128_with_sub3_in_VGPR_32_Lo256RegClassID
1449 (uint32_t(InvalidRegBankID) << 8) | // VS_128_with_hi16_with_sub0_in_VS_32_Lo128RegClassID
1450 (uint32_t(InvalidRegBankID) << 12) | // VS_128_with_hi16_with_sub0_sub1_in_VS_64_Lo256RegClassID
1451 (uint32_t(InvalidRegBankID) << 16) | // VS_128_with_hi16_with_sub1_in_VS_32_Lo128RegClassID
1452 (uint32_t(InvalidRegBankID) << 20) | // VS_128_with_hi16_with_sub2_sub3_in_VS_64_Lo256RegClassID
1453 (uint32_t(InvalidRegBankID) << 24) | // VS_128_with_hi16_with_sub2_in_VS_32_Lo128RegClassID
1454 (uint32_t(InvalidRegBankID) << 28), // VS_128_with_hi16_with_sub3_in_VS_32_Lo128RegClassID
1455 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_128_with_hi16_in_VGPR_16_Lo128RegClassID
1456 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_128_with_sub0_in_VGPR_32_Lo256_and_AV_128_with_sub1_sub2_in_AV_64_Align2RegClassID
1457 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_128_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID
1458 (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_128_Align2RegClassID
1459 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_128_with_sub1_in_VGPR_32_Lo128RegClassID
1460 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_128_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID
1461 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // VReg_128_Lo256_Align2RegClassID
1462 (uint32_t(AMDGPU::AGPRRegBankID) << 28), // AReg_128_with_sub1_sub2_in_AReg_64_Align2RegClassID
1463 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_128_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID
1464 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_128_with_sub2_in_VGPR_32_Lo128RegClassID
1465 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_128_with_sub3_in_VGPR_32_Lo128RegClassID
1466 (uint32_t(InvalidRegBankID) << 12) | // VS_128_with_hi16_with_sub0_sub1_in_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID
1467 (uint32_t(InvalidRegBankID) << 16) | // VS_128_with_hi16_with_sub2_sub3_in_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClassID
1468 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_128_with_hi16_in_VGPR_16_Lo128_and_AV_128_with_sub1_sub2_in_AV_64_Align2RegClassID
1469 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_128_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1470 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_128_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1471 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_128_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1472 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1473 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SReg_128RegClassID
1474 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SReg_128_XNULLRegClassID
1475 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_128RegClassID
1476 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClassID
1477 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_128_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID
1478 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClassID
1479 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // TTMP_128RegClassID
1480 (uint32_t(InvalidRegBankID) << 4) |
1481 (uint32_t(InvalidRegBankID) << 8) | // AV_160RegClassID
1482 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // VReg_160RegClassID
1483 (uint32_t(InvalidRegBankID) << 16) | // AV_160_Align2RegClassID
1484 (uint32_t(InvalidRegBankID) << 20) | // AV_160_with_sub1_sub2_in_AV_64_Align2RegClassID
1485 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_160_with_sub1_sub2_in_VReg_64_Align2RegClassID
1486 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_160_Align2RegClassID
1487 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_160_with_sub0_in_VGPR_32_Lo256RegClassID
1488 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_160_with_sub1_in_VGPR_32_Lo256RegClassID
1489 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_160_with_sub2_in_VGPR_32_Lo256RegClassID
1490 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_160_with_sub3_in_VGPR_32_Lo256RegClassID
1491 (uint32_t(AMDGPU::AGPRRegBankID) << 16) | // AReg_160RegClassID
1492 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_160_with_sub4_in_VGPR_32_Lo256RegClassID
1493 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_160_with_hi16_in_VGPR_16_Lo128RegClassID
1494 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_160_with_sub0_in_VGPR_32_Lo256_and_AV_160_with_sub1_sub2_in_AV_64_Align2RegClassID
1495 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_160_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID
1496 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_160_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID
1497 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_160_with_sub1_in_VGPR_32_Lo128RegClassID
1498 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_160_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID
1499 (uint32_t(AMDGPU::AGPRRegBankID) << 16) | // AReg_160_Align2RegClassID
1500 (uint32_t(AMDGPU::AGPRRegBankID) << 20) | // AReg_160_with_sub1_sub2_in_AReg_64_Align2RegClassID
1501 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_160_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID
1502 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_160_with_sub2_in_VGPR_32_Lo128RegClassID
1503 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // VReg_160_Lo256_Align2RegClassID
1504 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_160_with_sub3_in_VGPR_32_Lo128RegClassID
1505 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_160_with_sub4_in_VGPR_32_Lo128RegClassID
1506 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_160_with_hi16_in_VGPR_16_Lo128_and_AV_160_with_sub1_sub2_in_AV_64_Align2RegClassID
1507 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_160_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1508 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_160_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1509 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_160_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1510 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_160_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1511 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_160_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1512 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SReg_160RegClassID
1513 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_160RegClassID
1514 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_160_with_sub0_sub1_in_CCR_SGPR_64RegClassID
1515 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_160_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID
1516 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_160_with_sub2_sub3_in_CCR_SGPR_64RegClassID
1517 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // TTMP_160RegClassID
1518 (uint32_t(InvalidRegBankID) << 28), // AV_192RegClassID
1519 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // VReg_192RegClassID
1520 (uint32_t(InvalidRegBankID) << 4) | // AV_192_Align2RegClassID
1521 (uint32_t(InvalidRegBankID) << 8) | // AV_192_with_sub1_sub2_in_AV_64_Align2RegClassID
1522 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // VReg_192_Align2RegClassID
1523 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_192_with_sub1_sub2_in_VReg_64_Align2RegClassID
1524 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_192_with_sub0_in_VGPR_32_Lo256RegClassID
1525 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_192_with_sub1_in_VGPR_32_Lo256RegClassID
1526 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_192_with_sub2_in_VGPR_32_Lo256RegClassID
1527 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_192_with_sub3_in_VGPR_32_Lo256RegClassID
1528 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_192_with_sub4_in_VGPR_32_Lo256RegClassID
1529 (uint32_t(AMDGPU::AGPRRegBankID) << 8) | // AReg_192RegClassID
1530 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_192_with_sub5_in_VGPR_32_Lo256RegClassID
1531 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_192_with_hi16_in_VGPR_16_Lo128RegClassID
1532 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_192_with_sub0_in_VGPR_32_Lo256_and_AV_192_with_sub1_sub2_in_AV_64_Align2RegClassID
1533 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_192_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID
1534 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_192_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID
1535 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_192_with_sub1_in_VGPR_32_Lo128RegClassID
1536 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_192_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID
1537 (uint32_t(AMDGPU::AGPRRegBankID) << 8) | // AReg_192_Align2RegClassID
1538 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_192_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID
1539 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_192_with_sub2_in_VGPR_32_Lo128RegClassID
1540 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // VReg_192_Lo256_Align2RegClassID
1541 (uint32_t(AMDGPU::AGPRRegBankID) << 24) | // AReg_192_with_sub1_sub2_in_AReg_64_Align2RegClassID
1542 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_192_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID
1543 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_192_with_sub3_in_VGPR_32_Lo128RegClassID
1544 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_192_with_sub4_in_VGPR_32_Lo128RegClassID
1545 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_192_with_sub5_in_VGPR_32_Lo128RegClassID
1546 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_192_with_hi16_in_VGPR_16_Lo128_and_AV_192_with_sub1_sub2_in_AV_64_Align2RegClassID
1547 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_192_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1548 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_192_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1549 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_192_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1550 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_192_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1551 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_192_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1552 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_192_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1553 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SReg_192RegClassID
1554 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_192RegClassID
1555 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_192_with_sub0_sub1_in_CCR_SGPR_64RegClassID
1556 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID
1557 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_192_with_sub2_sub3_in_CCR_SGPR_64RegClassID
1558 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1559 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1560 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // TTMP_192RegClassID
1561 (uint32_t(InvalidRegBankID) << 8) | // AV_224RegClassID
1562 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // VReg_224RegClassID
1563 (uint32_t(InvalidRegBankID) << 16) | // AV_224_Align2RegClassID
1564 (uint32_t(InvalidRegBankID) << 20) | // AV_224_with_sub1_sub2_in_AV_64_Align2RegClassID
1565 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_224_with_sub1_sub2_in_VReg_64_Align2RegClassID
1566 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_224_Align2RegClassID
1567 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_224_with_sub0_in_VGPR_32_Lo256RegClassID
1568 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_224_with_sub1_in_VGPR_32_Lo256RegClassID
1569 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_224_with_sub2_in_VGPR_32_Lo256RegClassID
1570 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_224_with_sub3_in_VGPR_32_Lo256RegClassID
1571 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_224_with_sub4_in_VGPR_32_Lo256RegClassID
1572 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_224_with_sub5_in_VGPR_32_Lo256RegClassID
1573 (uint32_t(AMDGPU::AGPRRegBankID) << 24) | // AReg_224RegClassID
1574 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_224_with_sub6_in_VGPR_32_Lo256RegClassID
1575 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_224_with_hi16_in_VGPR_16_Lo128RegClassID
1576 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_224_with_sub0_in_VGPR_32_Lo256_and_AV_224_with_sub1_sub2_in_AV_64_Align2RegClassID
1577 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_224_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID
1578 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_224_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID
1579 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_224_with_sub1_in_VGPR_32_Lo128RegClassID
1580 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_224_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID
1581 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_224_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID
1582 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_224_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID
1583 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_224_with_sub2_in_VGPR_32_Lo128RegClassID
1584 (uint32_t(AMDGPU::AGPRRegBankID) << 4) | // AReg_224_Align2RegClassID
1585 (uint32_t(AMDGPU::AGPRRegBankID) << 8) | // AReg_224_with_sub1_sub2_in_AReg_64_Align2RegClassID
1586 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_224_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID
1587 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_224_with_sub3_in_VGPR_32_Lo128RegClassID
1588 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // VReg_224_Lo256_Align2RegClassID
1589 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_224_with_sub4_in_VGPR_32_Lo128RegClassID
1590 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_224_with_sub5_in_VGPR_32_Lo128RegClassID
1591 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_224_with_sub6_in_VGPR_32_Lo128RegClassID
1592 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_224_with_hi16_in_VGPR_16_Lo128_and_AV_224_with_sub1_sub2_in_AV_64_Align2RegClassID
1593 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_224_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1594 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_224_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1595 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_224_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1596 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_224_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1597 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_224_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1598 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_224_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1599 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_224_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1600 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SReg_224RegClassID
1601 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_224RegClassID
1602 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_224_with_sub0_sub1_in_CCR_SGPR_64RegClassID
1603 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID
1604 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_224_with_sub2_sub3_in_CCR_SGPR_64RegClassID
1605 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_224_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1606 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_224_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1607 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // TTMP_224RegClassID
1608 (uint32_t(InvalidRegBankID) << 4) | // AV_256RegClassID
1609 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // VReg_256RegClassID
1610 (uint32_t(InvalidRegBankID) << 12) | // AV_256_Align2RegClassID
1611 (uint32_t(InvalidRegBankID) << 16) | // AV_256_with_sub1_sub2_in_AV_64_Align2RegClassID
1612 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // VReg_256_Align2RegClassID
1613 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_256_with_sub1_sub2_in_VReg_64_Align2RegClassID
1614 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_256_with_sub0_in_VGPR_32_Lo256RegClassID
1615 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_256_with_sub1_in_VGPR_32_Lo256RegClassID
1616 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_256_with_sub2_in_VGPR_32_Lo256RegClassID
1617 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_256_with_sub3_in_VGPR_32_Lo256RegClassID
1618 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_256_with_sub4_in_VGPR_32_Lo256RegClassID
1619 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_256_with_sub5_in_VGPR_32_Lo256RegClassID
1620 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_256_with_sub6_in_VGPR_32_Lo256RegClassID
1621 (uint32_t(AMDGPU::AGPRRegBankID) << 24) | // AReg_256RegClassID
1622 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_256_with_sub7_in_VGPR_32_Lo256RegClassID
1623 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_256_with_hi16_in_VGPR_16_Lo128RegClassID
1624 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_256_with_sub0_in_VGPR_32_Lo256_and_AV_256_with_sub1_sub2_in_AV_64_Align2RegClassID
1625 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_256_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID
1626 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_256_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID
1627 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_256_with_sub1_in_VGPR_32_Lo128RegClassID
1628 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_256_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID
1629 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_256_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID
1630 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_256_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID
1631 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_256_with_sub2_in_VGPR_32_Lo128RegClassID
1632 (uint32_t(AMDGPU::AGPRRegBankID) << 4) | // AReg_256_Align2RegClassID
1633 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_256_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID
1634 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_256_with_sub3_in_VGPR_32_Lo128RegClassID
1635 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // VReg_256_Lo256_Align2RegClassID
1636 (uint32_t(AMDGPU::AGPRRegBankID) << 20) | // AReg_256_with_sub1_sub2_in_AReg_64_Align2RegClassID
1637 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_256_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID
1638 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_256_with_sub4_in_VGPR_32_Lo128RegClassID
1639 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_256_with_sub5_in_VGPR_32_Lo128RegClassID
1640 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_256_with_sub6_in_VGPR_32_Lo128RegClassID
1641 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_256_with_sub7_in_VGPR_32_Lo128RegClassID
1642 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_256_with_hi16_in_VGPR_16_Lo128_and_AV_256_with_sub1_sub2_in_AV_64_Align2RegClassID
1643 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_256_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1644 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_256_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1645 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_256_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1646 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_256_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1647 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_256_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1648 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_256_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1649 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_256_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1650 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_256_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1651 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SReg_256RegClassID
1652 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SReg_256_XNULLRegClassID
1653 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_256RegClassID
1654 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_256_with_sub0_sub1_in_CCR_SGPR_64RegClassID
1655 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID
1656 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_256_with_sub2_sub3_in_CCR_SGPR_64RegClassID
1657 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_256_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1658 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_256_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1659 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_256_with_sub6_sub7_in_CCR_SGPR_64RegClassID
1660 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // TTMP_256RegClassID
1661 (uint32_t(InvalidRegBankID) << 24) | // AV_288RegClassID
1662 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_288RegClassID
1663 (uint32_t(InvalidRegBankID) << 0) | // AV_288_Align2RegClassID
1664 (uint32_t(InvalidRegBankID) << 4) | // AV_288_with_sub1_sub2_in_AV_64_Align2RegClassID
1665 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_288_with_sub1_sub2_in_VReg_64_Align2RegClassID
1666 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // VReg_288_Align2RegClassID
1667 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_288_with_sub0_in_VGPR_32_Lo256RegClassID
1668 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_288_with_sub1_in_VGPR_32_Lo256RegClassID
1669 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_288_with_sub2_in_VGPR_32_Lo256RegClassID
1670 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_288_with_sub3_in_VGPR_32_Lo256RegClassID
1671 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_288_with_sub4_in_VGPR_32_Lo256RegClassID
1672 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_288_with_sub5_in_VGPR_32_Lo256RegClassID
1673 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_288_with_sub6_in_VGPR_32_Lo256RegClassID
1674 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_288_with_sub7_in_VGPR_32_Lo256RegClassID
1675 (uint32_t(AMDGPU::AGPRRegBankID) << 16) | // AReg_288RegClassID
1676 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_288_with_sub8_in_VGPR_32_Lo256RegClassID
1677 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_288_with_hi16_in_VGPR_16_Lo128RegClassID
1678 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_288_with_sub0_in_VGPR_32_Lo256_and_AV_288_with_sub1_sub2_in_AV_64_Align2RegClassID
1679 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_288_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID
1680 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_288_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID
1681 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_288_with_sub1_in_VGPR_32_Lo128RegClassID
1682 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_288_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID
1683 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID
1684 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_288_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID
1685 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_288_with_sub2_in_VGPR_32_Lo128RegClassID
1686 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClassID
1687 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_288_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID
1688 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_288_with_sub3_in_VGPR_32_Lo128RegClassID
1689 (uint32_t(AMDGPU::AGPRRegBankID) << 8) | // AReg_288_Align2RegClassID
1690 (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_288_with_sub1_sub2_in_AReg_64_Align2RegClassID
1691 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_288_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID
1692 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_288_with_sub4_in_VGPR_32_Lo128RegClassID
1693 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // VReg_288_Lo256_Align2RegClassID
1694 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_288_with_sub5_in_VGPR_32_Lo128RegClassID
1695 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_288_with_sub6_in_VGPR_32_Lo128RegClassID
1696 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_288_with_sub7_in_VGPR_32_Lo128RegClassID
1697 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_288_with_sub8_in_VGPR_32_Lo128RegClassID
1698 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_288_with_hi16_in_VGPR_16_Lo128_and_AV_288_with_sub1_sub2_in_AV_64_Align2RegClassID
1699 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_288_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1700 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_288_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1701 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_288_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1702 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_288_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1703 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_288_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1704 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_288_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1705 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_288_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1706 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_288_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1707 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_288_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1708 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SReg_288RegClassID
1709 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_288RegClassID
1710 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_288_with_sub0_sub1_in_CCR_SGPR_64RegClassID
1711 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID
1712 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_288_with_sub2_sub3_in_CCR_SGPR_64RegClassID
1713 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_288_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1714 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_288_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1715 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_288_with_sub6_sub7_in_CCR_SGPR_64RegClassID
1716 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // TTMP_288RegClassID
1717 (uint32_t(InvalidRegBankID) << 24) | // AV_320RegClassID
1718 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_320RegClassID
1719 (uint32_t(InvalidRegBankID) << 0) | // AV_320_Align2RegClassID
1720 (uint32_t(InvalidRegBankID) << 4) | // AV_320_with_sub1_sub2_in_AV_64_Align2RegClassID
1721 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // VReg_320_Align2RegClassID
1722 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_320_with_sub1_sub2_in_VReg_64_Align2RegClassID
1723 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_320_with_sub0_in_VGPR_32_Lo256RegClassID
1724 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_320_with_sub1_in_VGPR_32_Lo256RegClassID
1725 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_320_with_sub2_in_VGPR_32_Lo256RegClassID
1726 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_320_with_sub3_in_VGPR_32_Lo256RegClassID
1727 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_320_with_sub4_in_VGPR_32_Lo256RegClassID
1728 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_320_with_sub5_in_VGPR_32_Lo256RegClassID
1729 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_320_with_sub6_in_VGPR_32_Lo256RegClassID
1730 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_320_with_sub7_in_VGPR_32_Lo256RegClassID
1731 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_320_with_sub8_in_VGPR_32_Lo256RegClassID
1732 (uint32_t(AMDGPU::AGPRRegBankID) << 20) | // AReg_320RegClassID
1733 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_320_with_sub9_in_VGPR_32_Lo256RegClassID
1734 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_320_with_hi16_in_VGPR_16_Lo128RegClassID
1735 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_320_with_sub0_in_VGPR_32_Lo256_and_AV_320_with_sub1_sub2_in_AV_64_Align2RegClassID
1736 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_320_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID
1737 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_320_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID
1738 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_320_with_sub1_in_VGPR_32_Lo128RegClassID
1739 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_320_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID
1740 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID
1741 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_320_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID
1742 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_320_with_sub2_in_VGPR_32_Lo128RegClassID
1743 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClassID
1744 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_320_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID
1745 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_320_with_sub3_in_VGPR_32_Lo128RegClassID
1746 (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_320_Align2RegClassID
1747 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_320_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID
1748 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_320_with_sub4_in_VGPR_32_Lo128RegClassID
1749 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // VReg_320_Lo256_Align2RegClassID
1750 (uint32_t(AMDGPU::AGPRRegBankID) << 28), // AReg_320_with_sub1_sub2_in_AReg_64_Align2RegClassID
1751 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_320_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClassID
1752 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_320_with_sub5_in_VGPR_32_Lo128RegClassID
1753 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_320_with_sub6_in_VGPR_32_Lo128RegClassID
1754 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_320_with_sub7_in_VGPR_32_Lo128RegClassID
1755 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_320_with_sub8_in_VGPR_32_Lo128RegClassID
1756 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_320_with_sub9_in_VGPR_32_Lo128RegClassID
1757 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_320_with_hi16_in_VGPR_16_Lo128_and_AV_320_with_sub1_sub2_in_AV_64_Align2RegClassID
1758 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_320_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1759 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_320_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1760 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_320_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1761 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_320_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1762 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_320_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1763 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_320_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1764 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_320_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1765 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_320_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1766 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_320_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1767 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_320_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1768 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SReg_320RegClassID
1769 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_320RegClassID
1770 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_320_with_sub0_sub1_in_CCR_SGPR_64RegClassID
1771 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID
1772 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_320_with_sub2_sub3_in_CCR_SGPR_64RegClassID
1773 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1774 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
1775 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1776 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
1777 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_320_with_sub6_sub7_in_CCR_SGPR_64RegClassID
1778 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
1779 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // TTMP_320RegClassID
1780 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_320_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
1781 (uint32_t(InvalidRegBankID) << 24) | // AV_352RegClassID
1782 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_352RegClassID
1783 (uint32_t(InvalidRegBankID) << 0) | // AV_352_Align2RegClassID
1784 (uint32_t(InvalidRegBankID) << 4) | // AV_352_with_sub1_sub2_in_AV_64_Align2RegClassID
1785 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_352_with_sub1_sub2_in_VReg_64_Align2RegClassID
1786 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // VReg_352_Align2RegClassID
1787 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_352_with_sub0_in_VGPR_32_Lo256RegClassID
1788 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_352_with_sub1_in_VGPR_32_Lo256RegClassID
1789 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_352_with_sub2_in_VGPR_32_Lo256RegClassID
1790 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_352_with_sub3_in_VGPR_32_Lo256RegClassID
1791 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_352_with_sub4_in_VGPR_32_Lo256RegClassID
1792 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_352_with_sub5_in_VGPR_32_Lo256RegClassID
1793 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_352_with_sub6_in_VGPR_32_Lo256RegClassID
1794 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_352_with_sub7_in_VGPR_32_Lo256RegClassID
1795 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_352_with_sub8_in_VGPR_32_Lo256RegClassID
1796 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_352_with_sub9_in_VGPR_32_Lo256RegClassID
1797 (uint32_t(AMDGPU::AGPRRegBankID) << 24) | // AReg_352RegClassID
1798 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_352_with_sub10_in_VGPR_32_Lo256RegClassID
1799 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_352_with_hi16_in_VGPR_16_Lo128RegClassID
1800 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_352_with_sub0_in_VGPR_32_Lo256_and_AV_352_with_sub1_sub2_in_AV_64_Align2RegClassID
1801 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_352_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID
1802 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_352_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID
1803 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_352_with_sub1_in_VGPR_32_Lo128RegClassID
1804 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_352_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID
1805 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID
1806 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_352_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID
1807 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_352_with_sub2_in_VGPR_32_Lo128RegClassID
1808 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClassID
1809 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_352_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID
1810 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_352_with_sub3_in_VGPR_32_Lo128RegClassID
1811 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_352_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClassID
1812 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_352_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID
1813 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_352_with_sub4_in_VGPR_32_Lo128RegClassID
1814 (uint32_t(AMDGPU::AGPRRegBankID) << 28), // AReg_352_Align2RegClassID
1815 (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AReg_352_with_sub1_sub2_in_AReg_64_Align2RegClassID
1816 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_352_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClassID
1817 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_352_with_sub5_in_VGPR_32_Lo128RegClassID
1818 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // VReg_352_Lo256_Align2RegClassID
1819 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_352_with_sub6_in_VGPR_32_Lo128RegClassID
1820 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_352_with_sub7_in_VGPR_32_Lo128RegClassID
1821 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_352_with_sub8_in_VGPR_32_Lo128RegClassID
1822 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_352_with_sub9_in_VGPR_32_Lo128RegClassID
1823 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_352_with_sub10_in_VGPR_32_Lo128RegClassID
1824 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_352_with_hi16_in_VGPR_16_Lo128_and_AV_352_with_sub1_sub2_in_AV_64_Align2RegClassID
1825 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_352_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1826 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_352_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1827 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_352_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1828 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_352_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1829 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_352_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1830 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_352_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1831 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_352_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1832 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_352_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1833 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_352_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1834 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_352_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1835 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_352_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1836 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SReg_352RegClassID
1837 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_352RegClassID
1838 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_352_with_sub0_sub1_in_CCR_SGPR_64RegClassID
1839 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID
1840 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_352_with_sub2_sub3_in_CCR_SGPR_64RegClassID
1841 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1842 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
1843 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1844 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
1845 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_352_with_sub6_sub7_in_CCR_SGPR_64RegClassID
1846 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
1847 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // TTMP_352RegClassID
1848 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_352_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
1849 (uint32_t(InvalidRegBankID) << 8) | // AV_384RegClassID
1850 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // VReg_384RegClassID
1851 (uint32_t(InvalidRegBankID) << 16) | // AV_384_Align2RegClassID
1852 (uint32_t(InvalidRegBankID) << 20) | // AV_384_with_sub1_sub2_in_AV_64_Align2RegClassID
1853 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // VReg_384_Align2RegClassID
1854 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_384_with_sub1_sub2_in_VReg_64_Align2RegClassID
1855 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_384_with_sub0_in_VGPR_32_Lo256RegClassID
1856 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_384_with_sub1_in_VGPR_32_Lo256RegClassID
1857 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_384_with_sub2_in_VGPR_32_Lo256RegClassID
1858 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_384_with_sub3_in_VGPR_32_Lo256RegClassID
1859 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_384_with_sub4_in_VGPR_32_Lo256RegClassID
1860 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_384_with_sub5_in_VGPR_32_Lo256RegClassID
1861 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_384_with_sub6_in_VGPR_32_Lo256RegClassID
1862 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_384_with_sub7_in_VGPR_32_Lo256RegClassID
1863 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_384_with_sub8_in_VGPR_32_Lo256RegClassID
1864 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_384_with_sub9_in_VGPR_32_Lo256RegClassID
1865 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_384_with_sub10_in_VGPR_32_Lo256RegClassID
1866 (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_384RegClassID
1867 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_384_with_sub11_in_VGPR_32_Lo256RegClassID
1868 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_384_with_hi16_in_VGPR_16_Lo128RegClassID
1869 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_384_with_sub0_in_VGPR_32_Lo256_and_AV_384_with_sub1_sub2_in_AV_64_Align2RegClassID
1870 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_384_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID
1871 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_384_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID
1872 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_384_with_sub1_in_VGPR_32_Lo128RegClassID
1873 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_384_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID
1874 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID
1875 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_384_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID
1876 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_384_with_sub2_in_VGPR_32_Lo128RegClassID
1877 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClassID
1878 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_384_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID
1879 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_384_with_sub3_in_VGPR_32_Lo128RegClassID
1880 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_384_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClassID
1881 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_384_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID
1882 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_384_with_sub4_in_VGPR_32_Lo128RegClassID
1883 (uint32_t(AMDGPU::AGPRRegBankID) << 16) | // AReg_384_Align2RegClassID
1884 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_384_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClassID
1885 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_384_with_sub5_in_VGPR_32_Lo128RegClassID
1886 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_384_Lo256_Align2RegClassID
1887 (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AReg_384_with_sub1_sub2_in_AReg_64_Align2RegClassID
1888 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_384_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_352_Lo256_Align2RegClassID
1889 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_384_with_sub6_in_VGPR_32_Lo128RegClassID
1890 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_384_with_sub7_in_VGPR_32_Lo128RegClassID
1891 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_384_with_sub8_in_VGPR_32_Lo128RegClassID
1892 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_384_with_sub9_in_VGPR_32_Lo128RegClassID
1893 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_384_with_sub10_in_VGPR_32_Lo128RegClassID
1894 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_384_with_sub11_in_VGPR_32_Lo128RegClassID
1895 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_384_with_hi16_in_VGPR_16_Lo128_and_AV_384_with_sub1_sub2_in_AV_64_Align2RegClassID
1896 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_384_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1897 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_384_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1898 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_384_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1899 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_384_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1900 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_384_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1901 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_384_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1902 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_384_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1903 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_384_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1904 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_384_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1905 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_384_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1906 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_384_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1907 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_384_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1908 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SReg_384RegClassID
1909 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_384RegClassID
1910 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_384_with_sub0_sub1_in_CCR_SGPR_64RegClassID
1911 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID
1912 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_384_with_sub2_sub3_in_CCR_SGPR_64RegClassID
1913 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1914 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
1915 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
1916 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
1917 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_384_with_sub6_sub7_in_CCR_SGPR_64RegClassID
1918 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
1919 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_384_with_sub10_sub11_in_CCR_SGPR_64RegClassID
1920 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // TTMP_384RegClassID
1921 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
1922 (uint32_t(InvalidRegBankID) << 12) | // AV_512RegClassID
1923 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // VReg_512RegClassID
1924 (uint32_t(InvalidRegBankID) << 20) | // AV_512_Align2RegClassID
1925 (uint32_t(InvalidRegBankID) << 24) | // AV_512_with_sub1_sub2_in_AV_64_Align2RegClassID
1926 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_512_Align2RegClassID
1927 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_512_with_sub1_sub2_in_VReg_64_Align2RegClassID
1928 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_sub0_in_VGPR_32_Lo256RegClassID
1929 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_512_with_sub1_in_VGPR_32_Lo256RegClassID
1930 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_512_with_sub2_in_VGPR_32_Lo256RegClassID
1931 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub3_in_VGPR_32_Lo256RegClassID
1932 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_sub4_in_VGPR_32_Lo256RegClassID
1933 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_512_with_sub5_in_VGPR_32_Lo256RegClassID
1934 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_512_with_sub6_in_VGPR_32_Lo256RegClassID
1935 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_512_with_sub7_in_VGPR_32_Lo256RegClassID
1936 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_sub8_in_VGPR_32_Lo256RegClassID
1937 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_512_with_sub9_in_VGPR_32_Lo256RegClassID
1938 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_512_with_sub10_in_VGPR_32_Lo256RegClassID
1939 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub11_in_VGPR_32_Lo256RegClassID
1940 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_sub12_in_VGPR_32_Lo256RegClassID
1941 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_512_with_sub13_in_VGPR_32_Lo256RegClassID
1942 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_512_with_sub14_in_VGPR_32_Lo256RegClassID
1943 (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AReg_512RegClassID
1944 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_sub15_in_VGPR_32_Lo256RegClassID
1945 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_512_with_hi16_in_VGPR_16_Lo128RegClassID
1946 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_512_with_sub0_in_VGPR_32_Lo256_and_AV_512_with_sub1_sub2_in_AV_64_Align2RegClassID
1947 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID
1948 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID
1949 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_512_with_sub1_in_VGPR_32_Lo128RegClassID
1950 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_512_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID
1951 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID
1952 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID
1953 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_512_with_sub2_in_VGPR_32_Lo128RegClassID
1954 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClassID
1955 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID
1956 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_sub3_in_VGPR_32_Lo128RegClassID
1957 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_512_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClassID
1958 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_512_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID
1959 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_512_with_sub4_in_VGPR_32_Lo128RegClassID
1960 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_384_Lo256_Align2RegClassID
1961 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_512_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClassID
1962 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_512_with_sub5_in_VGPR_32_Lo128RegClassID
1963 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_352_Lo256_Align2RegClassID
1964 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_in_VReg_352_Lo256_Align2RegClassID
1965 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_512_with_sub6_in_VGPR_32_Lo128RegClassID
1966 (uint32_t(AMDGPU::AGPRRegBankID) << 28), // AReg_512_Align2RegClassID
1967 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_512_with_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_VReg_352_Lo256_Align2RegClassID
1968 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_sub7_in_VGPR_32_Lo128RegClassID
1969 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // VReg_512_Lo256_Align2RegClassID
1970 (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_512_with_sub1_sub2_in_AReg_64_Align2RegClassID
1971 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_VReg_352_Lo256_Align2RegClassID
1972 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_sub8_in_VGPR_32_Lo128RegClassID
1973 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_512_with_sub9_in_VGPR_32_Lo128RegClassID
1974 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_512_with_sub10_in_VGPR_32_Lo128RegClassID
1975 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_512_with_sub11_in_VGPR_32_Lo128RegClassID
1976 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_sub12_in_VGPR_32_Lo128RegClassID
1977 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_512_with_sub13_in_VGPR_32_Lo128RegClassID
1978 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_512_with_sub14_in_VGPR_32_Lo128RegClassID
1979 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub15_in_VGPR_32_Lo128RegClassID
1980 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_hi16_in_VGPR_16_Lo128_and_AV_512_with_sub1_sub2_in_AV_64_Align2RegClassID
1981 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_512_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1982 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_512_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1983 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_512_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
1984 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1985 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_512_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1986 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_512_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1987 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1988 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1989 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_512_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1990 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_512_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1991 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_512_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1992 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_512_with_sub10_sub11_sub12_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1993 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_512_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1994 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_512_with_sub11_sub12_sub13_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1995 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_512_with_sub12_sub13_sub14_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1996 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_512_with_sub13_sub14_sub15_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
1997 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SReg_512RegClassID
1998 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_512RegClassID
1999 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_512_with_sub0_sub1_in_CCR_SGPR_64RegClassID
2000 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID
2001 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2002 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_512_with_sub2_sub3_in_CCR_SGPR_64RegClassID
2003 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
2004 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2005 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
2006 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2007 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_512_with_sub6_sub7_in_CCR_SGPR_64RegClassID
2008 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2009 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2010 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_512_with_sub10_sub11_in_CCR_SGPR_64RegClassID
2011 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2012 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2013 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_512_with_sub14_sub15_in_CCR_SGPR_64RegClassID
2014 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2015 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2016 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2017 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // TTMP_512RegClassID
2018 (uint32_t(InvalidRegBankID) << 12) |
2019 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // VReg_1024RegClassID
2020 (uint32_t(InvalidRegBankID) << 20) |
2021 (uint32_t(InvalidRegBankID) << 24) |
2022 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // VReg_1024_Align2RegClassID
2023 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub1_sub2_in_VReg_64_Align2RegClassID
2024 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub0_in_VGPR_32_Lo256RegClassID
2025 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub1_in_VGPR_32_Lo256RegClassID
2026 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub2_in_VGPR_32_Lo256RegClassID
2027 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub3_in_VGPR_32_Lo256RegClassID
2028 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub4_in_VGPR_32_Lo256RegClassID
2029 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub5_in_VGPR_32_Lo256RegClassID
2030 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub6_in_VGPR_32_Lo256RegClassID
2031 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub7_in_VGPR_32_Lo256RegClassID
2032 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub8_in_VGPR_32_Lo256RegClassID
2033 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub9_in_VGPR_32_Lo256RegClassID
2034 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub10_in_VGPR_32_Lo256RegClassID
2035 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub11_in_VGPR_32_Lo256RegClassID
2036 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub12_in_VGPR_32_Lo256RegClassID
2037 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub13_in_VGPR_32_Lo256RegClassID
2038 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub14_in_VGPR_32_Lo256RegClassID
2039 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub15_in_VGPR_32_Lo256RegClassID
2040 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub16_in_VGPR_32_Lo256RegClassID
2041 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub17_in_VGPR_32_Lo256RegClassID
2042 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub18_in_VGPR_32_Lo256RegClassID
2043 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub19_in_VGPR_32_Lo256RegClassID
2044 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub20_in_VGPR_32_Lo256RegClassID
2045 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub21_in_VGPR_32_Lo256RegClassID
2046 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub22_in_VGPR_32_Lo256RegClassID
2047 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub23_in_VGPR_32_Lo256RegClassID
2048 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub24_in_VGPR_32_Lo256RegClassID
2049 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub25_in_VGPR_32_Lo256RegClassID
2050 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub26_in_VGPR_32_Lo256RegClassID
2051 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub27_in_VGPR_32_Lo256RegClassID
2052 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub28_in_VGPR_32_Lo256RegClassID
2053 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub29_in_VGPR_32_Lo256RegClassID
2054 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub30_in_VGPR_32_Lo256RegClassID
2055 (uint32_t(AMDGPU::AGPRRegBankID) << 0) | // AReg_1024RegClassID
2056 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub31_in_VGPR_32_Lo256RegClassID
2057 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_hi16_in_VGPR_16_Lo128RegClassID
2058 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub0_in_VGPR_32_Lo256_and_AV_1024_with_sub1_sub2_in_AV_64_Align2RegClassID
2059 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClassID
2060 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClassID
2061 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub1_in_VGPR_32_Lo128RegClassID
2062 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClassID
2063 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClassID
2064 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClassID
2065 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub2_in_VGPR_32_Lo128RegClassID
2066 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClassID
2067 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClassID
2068 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub3_in_VGPR_32_Lo128RegClassID
2069 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClassID
2070 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClassID
2071 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub4_in_VGPR_32_Lo128RegClassID
2072 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_384_Lo256_Align2RegClassID
2073 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClassID
2074 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub5_in_VGPR_32_Lo128RegClassID
2075 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_352_Lo256_Align2RegClassID
2076 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_in_VReg_352_Lo256_Align2RegClassID
2077 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub6_in_VGPR_32_Lo128RegClassID
2078 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_VReg_512_Lo256_Align2RegClassID
2079 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_VReg_352_Lo256_Align2RegClassID
2080 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub7_in_VGPR_32_Lo128RegClassID
2081 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_VReg_352_Lo256_Align2RegClassID
2082 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_in_VReg_352_Lo256_Align2RegClassID
2083 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub8_in_VGPR_32_Lo128RegClassID
2084 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_in_VReg_352_Lo256_Align2RegClassID
2085 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_in_VReg_352_Lo256_Align2RegClassID
2086 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub9_in_VGPR_32_Lo128RegClassID
2087 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub10_in_VGPR_32_Lo128RegClassID
2088 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_in_VReg_352_Lo256_Align2RegClassID
2089 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_in_VReg_352_Lo256_Align2RegClassID
2090 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub11_in_VGPR_32_Lo128RegClassID
2091 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_in_VReg_352_Lo256_Align2RegClassID
2092 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_in_VReg_352_Lo256_Align2RegClassID
2093 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub12_in_VGPR_32_Lo128RegClassID
2094 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_in_VReg_352_Lo256_Align2RegClassID
2095 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_in_VReg_352_Lo256_Align2RegClassID
2096 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub13_in_VGPR_32_Lo128RegClassID
2097 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_in_VReg_352_Lo256_Align2RegClassID
2098 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_in_VReg_352_Lo256_Align2RegClassID
2099 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub14_in_VGPR_32_Lo128RegClassID
2100 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_in_VReg_352_Lo256_Align2RegClassID
2101 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_in_VReg_352_Lo256_Align2RegClassID
2102 (uint32_t(AMDGPU::AGPRRegBankID) << 28), // AReg_1024_Align2RegClassID
2103 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub15_in_VGPR_32_Lo128RegClassID
2104 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_in_VReg_352_Lo256_Align2RegClassID
2105 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // VReg_1024_Lo256_Align2RegClassID
2106 (uint32_t(AMDGPU::AGPRRegBankID) << 12) | // AReg_1024_with_sub1_sub2_in_AReg_64_Align2RegClassID
2107 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub16_in_VGPR_32_Lo128RegClassID
2108 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16_in_VReg_352_Lo256_Align2RegClassID
2109 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub17_in_VGPR_32_Lo128RegClassID
2110 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub18_in_VGPR_32_Lo128RegClassID
2111 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub19_in_VGPR_32_Lo128RegClassID
2112 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub20_in_VGPR_32_Lo128RegClassID
2113 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub21_in_VGPR_32_Lo128RegClassID
2114 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub22_in_VGPR_32_Lo128RegClassID
2115 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub23_in_VGPR_32_Lo128RegClassID
2116 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub24_in_VGPR_32_Lo128RegClassID
2117 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub25_in_VGPR_32_Lo128RegClassID
2118 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub26_in_VGPR_32_Lo128RegClassID
2119 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub27_in_VGPR_32_Lo128RegClassID
2120 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub28_in_VGPR_32_Lo128RegClassID
2121 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub29_in_VGPR_32_Lo128RegClassID
2122 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub30_in_VGPR_32_Lo128RegClassID
2123 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub31_in_VGPR_32_Lo128RegClassID
2124 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_hi16_in_VGPR_16_Lo128_and_AV_1024_with_sub1_sub2_in_AV_64_Align2RegClassID
2125 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
2126 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2127 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClassID
2128 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2129 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2130 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2131 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2132 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2133 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2134 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2135 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2136 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub10_sub11_sub12_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2137 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2138 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub11_sub12_sub13_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2139 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub12_sub13_sub14_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2140 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub13_sub14_sub15_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2141 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub14_sub15_sub16_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2142 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub15_sub16_sub17_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2143 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub16_sub17_sub18_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2144 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub17_sub18_sub19_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2145 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub18_sub19_sub20_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2146 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub19_sub20_sub21_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2147 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub20_sub21_sub22_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2148 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub21_sub22_sub23_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2149 (uint32_t(AMDGPU::VGPRRegBankID) << 24) | // AV_1024_with_sub22_sub23_sub24_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2150 (uint32_t(AMDGPU::VGPRRegBankID) << 28), // AV_1024_with_sub23_sub24_sub25_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2151 (uint32_t(AMDGPU::VGPRRegBankID) << 0) | // AV_1024_with_sub24_sub25_sub26_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2152 (uint32_t(AMDGPU::VGPRRegBankID) << 4) | // AV_1024_with_sub25_sub26_sub27_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2153 (uint32_t(AMDGPU::VGPRRegBankID) << 8) | // AV_1024_with_sub26_sub27_sub28_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2154 (uint32_t(AMDGPU::VGPRRegBankID) << 12) | // AV_1024_with_sub27_sub28_sub29_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2155 (uint32_t(AMDGPU::VGPRRegBankID) << 16) | // AV_1024_with_sub28_sub29_sub30_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2156 (uint32_t(AMDGPU::VGPRRegBankID) << 20) | // AV_1024_with_sub29_sub30_sub31_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClassID
2157 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024RegClassID
2158 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SReg_1024RegClassID
2159 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClassID
2160 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClassID
2161 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2162 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID
2163 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID
2164 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID
2165 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID
2166 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64RegClassID
2167 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
2168 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2169 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID
2170 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClassID
2171 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID
2172 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID
2173 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID
2174 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID
2175 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2176 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64RegClassID
2177 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2178 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID
2179 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2180 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub10_sub11_in_CCR_SGPR_64RegClassID
2181 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID
2182 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID
2183 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID
2184 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID
2185 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2186 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID
2187 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID
2188 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2189 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID
2190 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub14_sub15_in_CCR_SGPR_64RegClassID
2191 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID
2192 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID
2193 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID
2194 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID
2195 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID
2196 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID
2197 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClassID
2198 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub10_sub11_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID
2199 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID
2200 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub18_sub19_in_CCR_SGPR_64RegClassID
2201 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID
2202 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID
2203 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID
2204 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID
2205 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2206 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2207 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2208 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2209 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClassID
2210 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClassID
2211 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub22_sub23_in_CCR_SGPR_64RegClassID
2212 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID
2213 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID
2214 (uint32_t(AMDGPU::SGPRRegBankID) << 28), // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2215 (uint32_t(AMDGPU::SGPRRegBankID) << 0) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2216 (uint32_t(AMDGPU::SGPRRegBankID) << 4) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2217 (uint32_t(AMDGPU::SGPRRegBankID) << 8) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2218 (uint32_t(AMDGPU::SGPRRegBankID) << 12) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2219 (uint32_t(AMDGPU::SGPRRegBankID) << 16) | // SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClassID
2220 (uint32_t(AMDGPU::SGPRRegBankID) << 20) | // SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClassID
2221 (uint32_t(AMDGPU::SGPRRegBankID) << 24) | // SGPR_1024_with_sub26_sub27_in_CCR_SGPR_64RegClassID
2222 (uint32_t(AMDGPU::SGPRRegBankID) << 28) // SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClassID
2223 };
2224 const unsigned RegClassID = RC.getID();
2225 if (LLVM_LIKELY(RegClassID < 896)) {
2226 unsigned RegBankID = (RegClass2RegBank[RegClassID / 8] >> ((RegClassID % 8) * 4)) & 15;
2227 if (RegBankID != InvalidRegBankID)
2228 return getRegBank(RegBankID);
2229 }
2230 llvm_unreachable(llvm::Twine("Target needs to handle register class ID 0x").concat(llvm::Twine::utohexstr(RegClassID)).str().c_str());
2231}
2232
2233} // namespace llvm
2234
2235#endif // GET_TARGET_REGBANK_IMPL
2236
2237