| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Register Information Header Fragment *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #include "llvm/CodeGen/TargetRegisterInfo.h" |
| 10 | |
| 11 | namespace llvm { |
| 12 | |
| 13 | class AMDGPUFrameLowering; |
| 14 | |
| 15 | struct AMDGPUGenRegisterInfo : public TargetRegisterInfo { |
| 16 | explicit AMDGPUGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, |
| 17 | unsigned PC = 0, unsigned HwMode = 0); |
| 18 | unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; |
| 19 | unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override; |
| 20 | LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
| 21 | LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
| 22 | const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override; |
| 23 | const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override; |
| 24 | const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; |
| 25 | unsigned getRegUnitWeight(MCRegUnit RegUnit) const override; |
| 26 | unsigned getNumRegPressureSets() const override; |
| 27 | const char *getRegPressureSetName(unsigned Idx) const override; |
| 28 | unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; |
| 29 | const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; |
| 30 | const int *getRegUnitPressureSets(MCRegUnit RegUnit) const override; |
| 31 | ArrayRef<const char *> getRegMaskNames() const override; |
| 32 | ArrayRef<const uint32_t *> getRegMasks() const override; |
| 33 | bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override; |
| 34 | bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override; |
| 35 | bool isFixedRegister(const MachineFunction &, MCRegister) const override; |
| 36 | bool isArgumentRegister(const MachineFunction &, MCRegister) const override; |
| 37 | bool isConstantPhysReg(MCRegister PhysReg) const override final; |
| 38 | /// Devirtualized TargetFrameLowering. |
| 39 | static const AMDGPUFrameLowering *getFrameLowering( |
| 40 | const MachineFunction &MF); |
| 41 | const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) const override; |
| 42 | }; |
| 43 | |
| 44 | namespace AMDGPU { // Register classes |
| 45 | extern const TargetRegisterClass SCC_CLASSRegClass; |
| 46 | extern const TargetRegisterClass VReg_1RegClass; |
| 47 | extern const TargetRegisterClass VS_16RegClass; |
| 48 | extern const TargetRegisterClass VGPR_16RegClass; |
| 49 | extern const TargetRegisterClass VS_16_Lo128RegClass; |
| 50 | extern const TargetRegisterClass AGPR_LO16RegClass; |
| 51 | extern const TargetRegisterClass VGPR_16_Lo128RegClass; |
| 52 | extern const TargetRegisterClass SReg_LO16RegClass; |
| 53 | extern const TargetRegisterClass VS_16_with_hi16RegClass; |
| 54 | extern const TargetRegisterClass SGPR_HI16RegClass; |
| 55 | extern const TargetRegisterClass SGPR_LO16RegClass; |
| 56 | extern const TargetRegisterClass VS_16_with_hi16_with_lo16_in_SGPR_LO16RegClass; |
| 57 | extern const TargetRegisterClass TTMP_LO16RegClass; |
| 58 | extern const TargetRegisterClass VS_16_with_hi16_with_lo16_in_TTMP_LO16RegClass; |
| 59 | extern const TargetRegisterClass AV_32RegClass; |
| 60 | extern const TargetRegisterClass VS_32RegClass; |
| 61 | extern const TargetRegisterClass VS_32_with_hi16RegClass; |
| 62 | extern const TargetRegisterClass VRegOrLds_32RegClass; |
| 63 | extern const TargetRegisterClass VGPR_32RegClass; |
| 64 | extern const TargetRegisterClass VS_32_Lo256RegClass; |
| 65 | extern const TargetRegisterClass VS_32_Lo256_with_hi16RegClass; |
| 66 | extern const TargetRegisterClass VS_32_Lo128RegClass; |
| 67 | extern const TargetRegisterClass VS_32_Lo128_with_hi16RegClass; |
| 68 | extern const TargetRegisterClass VRegOrLds_32_and_VS_32_Lo256RegClass; |
| 69 | extern const TargetRegisterClass AGPR_32RegClass; |
| 70 | extern const TargetRegisterClass VGPR_32_Lo256RegClass; |
| 71 | extern const TargetRegisterClass SRegOrLds_32RegClass; |
| 72 | extern const TargetRegisterClass SReg_32RegClass; |
| 73 | extern const TargetRegisterClass SReg_32_XEXEC_HIRegClass; |
| 74 | extern const TargetRegisterClass SReg_32_XM0RegClass; |
| 75 | extern const TargetRegisterClass SReg_32_XEXECRegClass; |
| 76 | extern const TargetRegisterClass SReg_32_XEXEC_HI_and_SReg_32_XM0RegClass; |
| 77 | extern const TargetRegisterClass SReg_32_XM0_XEXECRegClass; |
| 78 | extern const TargetRegisterClass VRegOrLds_32_and_VS_32_Lo128RegClass; |
| 79 | extern const TargetRegisterClass VGPR_32_Lo128RegClass; |
| 80 | extern const TargetRegisterClass SGPR_32RegClass; |
| 81 | extern const TargetRegisterClass TTMP_32RegClass; |
| 82 | extern const TargetRegisterClass Pseudo_SReg_32RegClass; |
| 83 | extern const TargetRegisterClass SRegOrLds_32_and_VRegOrLds_32RegClass; |
| 84 | extern const TargetRegisterClass AV_64RegClass; |
| 85 | extern const TargetRegisterClass VS_64RegClass; |
| 86 | extern const TargetRegisterClass VS_64_with_sub1RegClass; |
| 87 | extern const TargetRegisterClass VReg_64RegClass; |
| 88 | extern const TargetRegisterClass AV_64_Align2RegClass; |
| 89 | extern const TargetRegisterClass VS_64_Align2RegClass; |
| 90 | extern const TargetRegisterClass VS_64_Align2_with_sub1RegClass; |
| 91 | extern const TargetRegisterClass VReg_64_Align2RegClass; |
| 92 | extern const TargetRegisterClass VS_64_with_sub0_in_VS_32_Lo256RegClass; |
| 93 | extern const TargetRegisterClass VS_64_with_sub1_and_VS_64_with_sub0_in_VS_32_Lo256RegClass; |
| 94 | extern const TargetRegisterClass VS_64_with_sub1_with_sub1_in_VS_32_Lo256RegClass; |
| 95 | extern const TargetRegisterClass AV_64_with_sub0_in_VGPR_32_Lo256RegClass; |
| 96 | extern const TargetRegisterClass AReg_64RegClass; |
| 97 | extern const TargetRegisterClass AV_64_with_sub1_in_VGPR_32_Lo256RegClass; |
| 98 | extern const TargetRegisterClass VS_64_Lo256RegClass; |
| 99 | extern const TargetRegisterClass VS_64_with_sub0_in_VS_32_Lo128RegClass; |
| 100 | extern const TargetRegisterClass VS_64_Lo256_with_sub1RegClass; |
| 101 | extern const TargetRegisterClass VS_64_with_sub1_and_VS_64_with_sub0_in_VS_32_Lo128RegClass; |
| 102 | extern const TargetRegisterClass VS_64_with_sub1_with_sub1_in_VS_32_Lo128RegClass; |
| 103 | extern const TargetRegisterClass VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClass; |
| 104 | extern const TargetRegisterClass VS_64_with_sub1_and_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClass; |
| 105 | extern const TargetRegisterClass AReg_64_Align2RegClass; |
| 106 | extern const TargetRegisterClass AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 107 | extern const TargetRegisterClass VReg_64_Lo256_Align2RegClass; |
| 108 | extern const TargetRegisterClass AV_64_with_sub1_in_VGPR_32_Lo128RegClass; |
| 109 | extern const TargetRegisterClass SReg_64_EncodableRegClass; |
| 110 | extern const TargetRegisterClass SReg_64_Encodable_with_sub0_in_SReg_32_XEXECRegClass; |
| 111 | extern const TargetRegisterClass SReg_64RegClass; |
| 112 | extern const TargetRegisterClass SReg_64_XEXECRegClass; |
| 113 | extern const TargetRegisterClass SReg_64_XEXEC_XNULLRegClass; |
| 114 | extern const TargetRegisterClass AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 115 | extern const TargetRegisterClass SGPR_64RegClass; |
| 116 | extern const TargetRegisterClass CCR_SGPR_64RegClass; |
| 117 | extern const TargetRegisterClass Gfx_CCR_SGPR_64RegClass; |
| 118 | extern const TargetRegisterClass TTMP_64RegClass; |
| 119 | extern const TargetRegisterClass APERTURE_ClassRegClass; |
| 120 | extern const TargetRegisterClass AV_96RegClass; |
| 121 | extern const TargetRegisterClass VReg_96RegClass; |
| 122 | extern const TargetRegisterClass AV_96_Align2RegClass; |
| 123 | extern const TargetRegisterClass AV_96_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 124 | extern const TargetRegisterClass AV_96_with_sub1_sub2_in_VReg_64_Align2RegClass; |
| 125 | extern const TargetRegisterClass VReg_96_Align2RegClass; |
| 126 | extern const TargetRegisterClass AV_96_with_sub0_in_VGPR_32_Lo256RegClass; |
| 127 | extern const TargetRegisterClass AV_96_with_sub1_in_VGPR_32_Lo256RegClass; |
| 128 | extern const TargetRegisterClass AReg_96RegClass; |
| 129 | extern const TargetRegisterClass AV_96_with_sub2_in_VGPR_32_Lo256RegClass; |
| 130 | extern const TargetRegisterClass AV_96_with_hi16_in_VGPR_16_Lo128RegClass; |
| 131 | extern const TargetRegisterClass AV_96_with_sub0_in_VGPR_32_Lo256_and_AV_96_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 132 | extern const TargetRegisterClass AV_96_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass; |
| 133 | extern const TargetRegisterClass AReg_96_Align2RegClass; |
| 134 | extern const TargetRegisterClass AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClass; |
| 135 | extern const TargetRegisterClass AV_96_with_sub1_in_VGPR_32_Lo128RegClass; |
| 136 | extern const TargetRegisterClass AV_96_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass; |
| 137 | extern const TargetRegisterClass VReg_96_Lo256_Align2RegClass; |
| 138 | extern const TargetRegisterClass AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 139 | extern const TargetRegisterClass AV_96_with_hi16_in_VGPR_16_Lo128_and_AV_96_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 140 | extern const TargetRegisterClass AV_96_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 141 | extern const TargetRegisterClass AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 142 | extern const TargetRegisterClass AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 143 | extern const TargetRegisterClass SReg_96RegClass; |
| 144 | extern const TargetRegisterClass SGPR_96RegClass; |
| 145 | extern const TargetRegisterClass SGPR_96_with_sub0_sub1_in_CCR_SGPR_64RegClass; |
| 146 | extern const TargetRegisterClass SGPR_96_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass; |
| 147 | extern const TargetRegisterClass TTMP_96RegClass; |
| 148 | extern const TargetRegisterClass AV_128RegClass; |
| 149 | extern const TargetRegisterClass VS_128RegClass; |
| 150 | extern const TargetRegisterClass VS_128_with_hi16RegClass; |
| 151 | extern const TargetRegisterClass VReg_128RegClass; |
| 152 | extern const TargetRegisterClass AV_128_Align2RegClass; |
| 153 | extern const TargetRegisterClass AV_128_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 154 | extern const TargetRegisterClass VS_128_Align2RegClass; |
| 155 | extern const TargetRegisterClass VS_128_Align2_with_hi16RegClass; |
| 156 | extern const TargetRegisterClass VReg_128_Align2RegClass; |
| 157 | extern const TargetRegisterClass AV_128_with_sub1_sub2_in_VReg_64_Align2RegClass; |
| 158 | extern const TargetRegisterClass VS_128_with_hi16_with_sub0_in_VS_32_Lo256RegClass; |
| 159 | extern const TargetRegisterClass VS_128_with_hi16_with_sub1_in_VS_32_Lo256RegClass; |
| 160 | extern const TargetRegisterClass VS_128_with_hi16_with_sub2_in_VS_32_Lo256RegClass; |
| 161 | extern const TargetRegisterClass VS_128_with_hi16_with_sub3_in_VS_32_Lo256RegClass; |
| 162 | extern const TargetRegisterClass AV_128_with_sub0_in_VGPR_32_Lo256RegClass; |
| 163 | extern const TargetRegisterClass AV_128_with_sub1_in_VGPR_32_Lo256RegClass; |
| 164 | extern const TargetRegisterClass AV_128_with_sub2_in_VGPR_32_Lo256RegClass; |
| 165 | extern const TargetRegisterClass AReg_128RegClass; |
| 166 | extern const TargetRegisterClass AV_128_with_sub3_in_VGPR_32_Lo256RegClass; |
| 167 | extern const TargetRegisterClass VS_128_with_hi16_with_sub0_in_VS_32_Lo128RegClass; |
| 168 | extern const TargetRegisterClass VS_128_with_hi16_with_sub0_sub1_in_VS_64_Lo256RegClass; |
| 169 | extern const TargetRegisterClass VS_128_with_hi16_with_sub1_in_VS_32_Lo128RegClass; |
| 170 | extern const TargetRegisterClass VS_128_with_hi16_with_sub2_sub3_in_VS_64_Lo256RegClass; |
| 171 | extern const TargetRegisterClass VS_128_with_hi16_with_sub2_in_VS_32_Lo128RegClass; |
| 172 | extern const TargetRegisterClass VS_128_with_hi16_with_sub3_in_VS_32_Lo128RegClass; |
| 173 | extern const TargetRegisterClass AV_128_with_hi16_in_VGPR_16_Lo128RegClass; |
| 174 | extern const TargetRegisterClass AV_128_with_sub0_in_VGPR_32_Lo256_and_AV_128_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 175 | extern const TargetRegisterClass AV_128_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass; |
| 176 | extern const TargetRegisterClass AReg_128_Align2RegClass; |
| 177 | extern const TargetRegisterClass AV_128_with_sub1_in_VGPR_32_Lo128RegClass; |
| 178 | extern const TargetRegisterClass AV_128_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass; |
| 179 | extern const TargetRegisterClass VReg_128_Lo256_Align2RegClass; |
| 180 | extern const TargetRegisterClass AReg_128_with_sub1_sub2_in_AReg_64_Align2RegClass; |
| 181 | extern const TargetRegisterClass AV_128_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass; |
| 182 | extern const TargetRegisterClass AV_128_with_sub2_in_VGPR_32_Lo128RegClass; |
| 183 | extern const TargetRegisterClass AV_128_with_sub3_in_VGPR_32_Lo128RegClass; |
| 184 | extern const TargetRegisterClass VS_128_with_hi16_with_sub0_sub1_in_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClass; |
| 185 | extern const TargetRegisterClass VS_128_with_hi16_with_sub2_sub3_in_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClass; |
| 186 | extern const TargetRegisterClass AV_128_with_hi16_in_VGPR_16_Lo128_and_AV_128_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 187 | extern const TargetRegisterClass AV_128_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 188 | extern const TargetRegisterClass AV_128_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 189 | extern const TargetRegisterClass AV_128_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 190 | extern const TargetRegisterClass AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 191 | extern const TargetRegisterClass SReg_128RegClass; |
| 192 | extern const TargetRegisterClass SReg_128_XNULLRegClass; |
| 193 | extern const TargetRegisterClass SGPR_128RegClass; |
| 194 | extern const TargetRegisterClass SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass; |
| 195 | extern const TargetRegisterClass SGPR_128_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass; |
| 196 | extern const TargetRegisterClass SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClass; |
| 197 | extern const TargetRegisterClass TTMP_128RegClass; |
| 198 | extern const TargetRegisterClass Pseudo_SReg_128RegClass; |
| 199 | extern const TargetRegisterClass AV_160RegClass; |
| 200 | extern const TargetRegisterClass VReg_160RegClass; |
| 201 | extern const TargetRegisterClass AV_160_Align2RegClass; |
| 202 | extern const TargetRegisterClass AV_160_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 203 | extern const TargetRegisterClass AV_160_with_sub1_sub2_in_VReg_64_Align2RegClass; |
| 204 | extern const TargetRegisterClass VReg_160_Align2RegClass; |
| 205 | extern const TargetRegisterClass AV_160_with_sub0_in_VGPR_32_Lo256RegClass; |
| 206 | extern const TargetRegisterClass AV_160_with_sub1_in_VGPR_32_Lo256RegClass; |
| 207 | extern const TargetRegisterClass AV_160_with_sub2_in_VGPR_32_Lo256RegClass; |
| 208 | extern const TargetRegisterClass AV_160_with_sub3_in_VGPR_32_Lo256RegClass; |
| 209 | extern const TargetRegisterClass AReg_160RegClass; |
| 210 | extern const TargetRegisterClass AV_160_with_sub4_in_VGPR_32_Lo256RegClass; |
| 211 | extern const TargetRegisterClass AV_160_with_hi16_in_VGPR_16_Lo128RegClass; |
| 212 | extern const TargetRegisterClass AV_160_with_sub0_in_VGPR_32_Lo256_and_AV_160_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 213 | extern const TargetRegisterClass AV_160_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass; |
| 214 | extern const TargetRegisterClass AV_160_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass; |
| 215 | extern const TargetRegisterClass AV_160_with_sub1_in_VGPR_32_Lo128RegClass; |
| 216 | extern const TargetRegisterClass AV_160_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass; |
| 217 | extern const TargetRegisterClass AReg_160_Align2RegClass; |
| 218 | extern const TargetRegisterClass AReg_160_with_sub1_sub2_in_AReg_64_Align2RegClass; |
| 219 | extern const TargetRegisterClass AV_160_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass; |
| 220 | extern const TargetRegisterClass AV_160_with_sub2_in_VGPR_32_Lo128RegClass; |
| 221 | extern const TargetRegisterClass VReg_160_Lo256_Align2RegClass; |
| 222 | extern const TargetRegisterClass AV_160_with_sub3_in_VGPR_32_Lo128RegClass; |
| 223 | extern const TargetRegisterClass AV_160_with_sub4_in_VGPR_32_Lo128RegClass; |
| 224 | extern const TargetRegisterClass AV_160_with_hi16_in_VGPR_16_Lo128_and_AV_160_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 225 | extern const TargetRegisterClass AV_160_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 226 | extern const TargetRegisterClass AV_160_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 227 | extern const TargetRegisterClass AV_160_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 228 | extern const TargetRegisterClass AV_160_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 229 | extern const TargetRegisterClass AV_160_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 230 | extern const TargetRegisterClass SReg_160RegClass; |
| 231 | extern const TargetRegisterClass SGPR_160RegClass; |
| 232 | extern const TargetRegisterClass SGPR_160_with_sub0_sub1_in_CCR_SGPR_64RegClass; |
| 233 | extern const TargetRegisterClass SGPR_160_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass; |
| 234 | extern const TargetRegisterClass SGPR_160_with_sub2_sub3_in_CCR_SGPR_64RegClass; |
| 235 | extern const TargetRegisterClass TTMP_160RegClass; |
| 236 | extern const TargetRegisterClass AV_192RegClass; |
| 237 | extern const TargetRegisterClass VReg_192RegClass; |
| 238 | extern const TargetRegisterClass AV_192_Align2RegClass; |
| 239 | extern const TargetRegisterClass AV_192_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 240 | extern const TargetRegisterClass VReg_192_Align2RegClass; |
| 241 | extern const TargetRegisterClass AV_192_with_sub1_sub2_in_VReg_64_Align2RegClass; |
| 242 | extern const TargetRegisterClass AV_192_with_sub0_in_VGPR_32_Lo256RegClass; |
| 243 | extern const TargetRegisterClass AV_192_with_sub1_in_VGPR_32_Lo256RegClass; |
| 244 | extern const TargetRegisterClass AV_192_with_sub2_in_VGPR_32_Lo256RegClass; |
| 245 | extern const TargetRegisterClass AV_192_with_sub3_in_VGPR_32_Lo256RegClass; |
| 246 | extern const TargetRegisterClass AV_192_with_sub4_in_VGPR_32_Lo256RegClass; |
| 247 | extern const TargetRegisterClass AReg_192RegClass; |
| 248 | extern const TargetRegisterClass AV_192_with_sub5_in_VGPR_32_Lo256RegClass; |
| 249 | extern const TargetRegisterClass AV_192_with_hi16_in_VGPR_16_Lo128RegClass; |
| 250 | extern const TargetRegisterClass AV_192_with_sub0_in_VGPR_32_Lo256_and_AV_192_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 251 | extern const TargetRegisterClass AV_192_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass; |
| 252 | extern const TargetRegisterClass AV_192_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass; |
| 253 | extern const TargetRegisterClass AV_192_with_sub1_in_VGPR_32_Lo128RegClass; |
| 254 | extern const TargetRegisterClass AV_192_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass; |
| 255 | extern const TargetRegisterClass AReg_192_Align2RegClass; |
| 256 | extern const TargetRegisterClass AV_192_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass; |
| 257 | extern const TargetRegisterClass AV_192_with_sub2_in_VGPR_32_Lo128RegClass; |
| 258 | extern const TargetRegisterClass VReg_192_Lo256_Align2RegClass; |
| 259 | extern const TargetRegisterClass AReg_192_with_sub1_sub2_in_AReg_64_Align2RegClass; |
| 260 | extern const TargetRegisterClass AV_192_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass; |
| 261 | extern const TargetRegisterClass AV_192_with_sub3_in_VGPR_32_Lo128RegClass; |
| 262 | extern const TargetRegisterClass AV_192_with_sub4_in_VGPR_32_Lo128RegClass; |
| 263 | extern const TargetRegisterClass AV_192_with_sub5_in_VGPR_32_Lo128RegClass; |
| 264 | extern const TargetRegisterClass AV_192_with_hi16_in_VGPR_16_Lo128_and_AV_192_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 265 | extern const TargetRegisterClass AV_192_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 266 | extern const TargetRegisterClass AV_192_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 267 | extern const TargetRegisterClass AV_192_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 268 | extern const TargetRegisterClass AV_192_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 269 | extern const TargetRegisterClass AV_192_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 270 | extern const TargetRegisterClass AV_192_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 271 | extern const TargetRegisterClass SReg_192RegClass; |
| 272 | extern const TargetRegisterClass SGPR_192RegClass; |
| 273 | extern const TargetRegisterClass SGPR_192_with_sub0_sub1_in_CCR_SGPR_64RegClass; |
| 274 | extern const TargetRegisterClass SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass; |
| 275 | extern const TargetRegisterClass SGPR_192_with_sub2_sub3_in_CCR_SGPR_64RegClass; |
| 276 | extern const TargetRegisterClass SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 277 | extern const TargetRegisterClass SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 278 | extern const TargetRegisterClass TTMP_192RegClass; |
| 279 | extern const TargetRegisterClass AV_224RegClass; |
| 280 | extern const TargetRegisterClass VReg_224RegClass; |
| 281 | extern const TargetRegisterClass AV_224_Align2RegClass; |
| 282 | extern const TargetRegisterClass AV_224_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 283 | extern const TargetRegisterClass AV_224_with_sub1_sub2_in_VReg_64_Align2RegClass; |
| 284 | extern const TargetRegisterClass VReg_224_Align2RegClass; |
| 285 | extern const TargetRegisterClass AV_224_with_sub0_in_VGPR_32_Lo256RegClass; |
| 286 | extern const TargetRegisterClass AV_224_with_sub1_in_VGPR_32_Lo256RegClass; |
| 287 | extern const TargetRegisterClass AV_224_with_sub2_in_VGPR_32_Lo256RegClass; |
| 288 | extern const TargetRegisterClass AV_224_with_sub3_in_VGPR_32_Lo256RegClass; |
| 289 | extern const TargetRegisterClass AV_224_with_sub4_in_VGPR_32_Lo256RegClass; |
| 290 | extern const TargetRegisterClass AV_224_with_sub5_in_VGPR_32_Lo256RegClass; |
| 291 | extern const TargetRegisterClass AReg_224RegClass; |
| 292 | extern const TargetRegisterClass AV_224_with_sub6_in_VGPR_32_Lo256RegClass; |
| 293 | extern const TargetRegisterClass AV_224_with_hi16_in_VGPR_16_Lo128RegClass; |
| 294 | extern const TargetRegisterClass AV_224_with_sub0_in_VGPR_32_Lo256_and_AV_224_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 295 | extern const TargetRegisterClass AV_224_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass; |
| 296 | extern const TargetRegisterClass AV_224_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass; |
| 297 | extern const TargetRegisterClass AV_224_with_sub1_in_VGPR_32_Lo128RegClass; |
| 298 | extern const TargetRegisterClass AV_224_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass; |
| 299 | extern const TargetRegisterClass AV_224_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass; |
| 300 | extern const TargetRegisterClass AV_224_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass; |
| 301 | extern const TargetRegisterClass AV_224_with_sub2_in_VGPR_32_Lo128RegClass; |
| 302 | extern const TargetRegisterClass AReg_224_Align2RegClass; |
| 303 | extern const TargetRegisterClass AReg_224_with_sub1_sub2_in_AReg_64_Align2RegClass; |
| 304 | extern const TargetRegisterClass AV_224_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass; |
| 305 | extern const TargetRegisterClass AV_224_with_sub3_in_VGPR_32_Lo128RegClass; |
| 306 | extern const TargetRegisterClass VReg_224_Lo256_Align2RegClass; |
| 307 | extern const TargetRegisterClass AV_224_with_sub4_in_VGPR_32_Lo128RegClass; |
| 308 | extern const TargetRegisterClass AV_224_with_sub5_in_VGPR_32_Lo128RegClass; |
| 309 | extern const TargetRegisterClass AV_224_with_sub6_in_VGPR_32_Lo128RegClass; |
| 310 | extern const TargetRegisterClass AV_224_with_hi16_in_VGPR_16_Lo128_and_AV_224_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 311 | extern const TargetRegisterClass AV_224_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 312 | extern const TargetRegisterClass AV_224_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 313 | extern const TargetRegisterClass AV_224_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 314 | extern const TargetRegisterClass AV_224_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 315 | extern const TargetRegisterClass AV_224_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 316 | extern const TargetRegisterClass AV_224_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 317 | extern const TargetRegisterClass AV_224_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 318 | extern const TargetRegisterClass SReg_224RegClass; |
| 319 | extern const TargetRegisterClass SGPR_224RegClass; |
| 320 | extern const TargetRegisterClass SGPR_224_with_sub0_sub1_in_CCR_SGPR_64RegClass; |
| 321 | extern const TargetRegisterClass SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass; |
| 322 | extern const TargetRegisterClass SGPR_224_with_sub2_sub3_in_CCR_SGPR_64RegClass; |
| 323 | extern const TargetRegisterClass SGPR_224_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 324 | extern const TargetRegisterClass SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_224_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 325 | extern const TargetRegisterClass TTMP_224RegClass; |
| 326 | extern const TargetRegisterClass AV_256RegClass; |
| 327 | extern const TargetRegisterClass VReg_256RegClass; |
| 328 | extern const TargetRegisterClass AV_256_Align2RegClass; |
| 329 | extern const TargetRegisterClass AV_256_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 330 | extern const TargetRegisterClass VReg_256_Align2RegClass; |
| 331 | extern const TargetRegisterClass AV_256_with_sub1_sub2_in_VReg_64_Align2RegClass; |
| 332 | extern const TargetRegisterClass AV_256_with_sub0_in_VGPR_32_Lo256RegClass; |
| 333 | extern const TargetRegisterClass AV_256_with_sub1_in_VGPR_32_Lo256RegClass; |
| 334 | extern const TargetRegisterClass AV_256_with_sub2_in_VGPR_32_Lo256RegClass; |
| 335 | extern const TargetRegisterClass AV_256_with_sub3_in_VGPR_32_Lo256RegClass; |
| 336 | extern const TargetRegisterClass AV_256_with_sub4_in_VGPR_32_Lo256RegClass; |
| 337 | extern const TargetRegisterClass AV_256_with_sub5_in_VGPR_32_Lo256RegClass; |
| 338 | extern const TargetRegisterClass AV_256_with_sub6_in_VGPR_32_Lo256RegClass; |
| 339 | extern const TargetRegisterClass AReg_256RegClass; |
| 340 | extern const TargetRegisterClass AV_256_with_sub7_in_VGPR_32_Lo256RegClass; |
| 341 | extern const TargetRegisterClass AV_256_with_hi16_in_VGPR_16_Lo128RegClass; |
| 342 | extern const TargetRegisterClass AV_256_with_sub0_in_VGPR_32_Lo256_and_AV_256_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 343 | extern const TargetRegisterClass AV_256_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass; |
| 344 | extern const TargetRegisterClass AV_256_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass; |
| 345 | extern const TargetRegisterClass AV_256_with_sub1_in_VGPR_32_Lo128RegClass; |
| 346 | extern const TargetRegisterClass AV_256_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass; |
| 347 | extern const TargetRegisterClass AV_256_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass; |
| 348 | extern const TargetRegisterClass AV_256_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass; |
| 349 | extern const TargetRegisterClass AV_256_with_sub2_in_VGPR_32_Lo128RegClass; |
| 350 | extern const TargetRegisterClass AReg_256_Align2RegClass; |
| 351 | extern const TargetRegisterClass AV_256_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass; |
| 352 | extern const TargetRegisterClass AV_256_with_sub3_in_VGPR_32_Lo128RegClass; |
| 353 | extern const TargetRegisterClass VReg_256_Lo256_Align2RegClass; |
| 354 | extern const TargetRegisterClass AReg_256_with_sub1_sub2_in_AReg_64_Align2RegClass; |
| 355 | extern const TargetRegisterClass AV_256_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass; |
| 356 | extern const TargetRegisterClass AV_256_with_sub4_in_VGPR_32_Lo128RegClass; |
| 357 | extern const TargetRegisterClass AV_256_with_sub5_in_VGPR_32_Lo128RegClass; |
| 358 | extern const TargetRegisterClass AV_256_with_sub6_in_VGPR_32_Lo128RegClass; |
| 359 | extern const TargetRegisterClass AV_256_with_sub7_in_VGPR_32_Lo128RegClass; |
| 360 | extern const TargetRegisterClass AV_256_with_hi16_in_VGPR_16_Lo128_and_AV_256_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 361 | extern const TargetRegisterClass AV_256_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 362 | extern const TargetRegisterClass AV_256_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 363 | extern const TargetRegisterClass AV_256_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 364 | extern const TargetRegisterClass AV_256_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 365 | extern const TargetRegisterClass AV_256_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 366 | extern const TargetRegisterClass AV_256_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 367 | extern const TargetRegisterClass AV_256_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 368 | extern const TargetRegisterClass AV_256_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 369 | extern const TargetRegisterClass SReg_256RegClass; |
| 370 | extern const TargetRegisterClass SReg_256_XNULLRegClass; |
| 371 | extern const TargetRegisterClass SGPR_256RegClass; |
| 372 | extern const TargetRegisterClass SGPR_256_with_sub0_sub1_in_CCR_SGPR_64RegClass; |
| 373 | extern const TargetRegisterClass SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass; |
| 374 | extern const TargetRegisterClass SGPR_256_with_sub2_sub3_in_CCR_SGPR_64RegClass; |
| 375 | extern const TargetRegisterClass SGPR_256_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 376 | extern const TargetRegisterClass SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_256_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 377 | extern const TargetRegisterClass SGPR_256_with_sub6_sub7_in_CCR_SGPR_64RegClass; |
| 378 | extern const TargetRegisterClass TTMP_256RegClass; |
| 379 | extern const TargetRegisterClass AV_288RegClass; |
| 380 | extern const TargetRegisterClass VReg_288RegClass; |
| 381 | extern const TargetRegisterClass AV_288_Align2RegClass; |
| 382 | extern const TargetRegisterClass AV_288_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 383 | extern const TargetRegisterClass AV_288_with_sub1_sub2_in_VReg_64_Align2RegClass; |
| 384 | extern const TargetRegisterClass VReg_288_Align2RegClass; |
| 385 | extern const TargetRegisterClass AV_288_with_sub0_in_VGPR_32_Lo256RegClass; |
| 386 | extern const TargetRegisterClass AV_288_with_sub1_in_VGPR_32_Lo256RegClass; |
| 387 | extern const TargetRegisterClass AV_288_with_sub2_in_VGPR_32_Lo256RegClass; |
| 388 | extern const TargetRegisterClass AV_288_with_sub3_in_VGPR_32_Lo256RegClass; |
| 389 | extern const TargetRegisterClass AV_288_with_sub4_in_VGPR_32_Lo256RegClass; |
| 390 | extern const TargetRegisterClass AV_288_with_sub5_in_VGPR_32_Lo256RegClass; |
| 391 | extern const TargetRegisterClass AV_288_with_sub6_in_VGPR_32_Lo256RegClass; |
| 392 | extern const TargetRegisterClass AV_288_with_sub7_in_VGPR_32_Lo256RegClass; |
| 393 | extern const TargetRegisterClass AReg_288RegClass; |
| 394 | extern const TargetRegisterClass AV_288_with_sub8_in_VGPR_32_Lo256RegClass; |
| 395 | extern const TargetRegisterClass AV_288_with_hi16_in_VGPR_16_Lo128RegClass; |
| 396 | extern const TargetRegisterClass AV_288_with_sub0_in_VGPR_32_Lo256_and_AV_288_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 397 | extern const TargetRegisterClass AV_288_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass; |
| 398 | extern const TargetRegisterClass AV_288_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass; |
| 399 | extern const TargetRegisterClass AV_288_with_sub1_in_VGPR_32_Lo128RegClass; |
| 400 | extern const TargetRegisterClass AV_288_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass; |
| 401 | extern const TargetRegisterClass AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass; |
| 402 | extern const TargetRegisterClass AV_288_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass; |
| 403 | extern const TargetRegisterClass AV_288_with_sub2_in_VGPR_32_Lo128RegClass; |
| 404 | extern const TargetRegisterClass AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClass; |
| 405 | extern const TargetRegisterClass AV_288_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass; |
| 406 | extern const TargetRegisterClass AV_288_with_sub3_in_VGPR_32_Lo128RegClass; |
| 407 | extern const TargetRegisterClass AReg_288_Align2RegClass; |
| 408 | extern const TargetRegisterClass AReg_288_with_sub1_sub2_in_AReg_64_Align2RegClass; |
| 409 | extern const TargetRegisterClass AV_288_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass; |
| 410 | extern const TargetRegisterClass AV_288_with_sub4_in_VGPR_32_Lo128RegClass; |
| 411 | extern const TargetRegisterClass VReg_288_Lo256_Align2RegClass; |
| 412 | extern const TargetRegisterClass AV_288_with_sub5_in_VGPR_32_Lo128RegClass; |
| 413 | extern const TargetRegisterClass AV_288_with_sub6_in_VGPR_32_Lo128RegClass; |
| 414 | extern const TargetRegisterClass AV_288_with_sub7_in_VGPR_32_Lo128RegClass; |
| 415 | extern const TargetRegisterClass AV_288_with_sub8_in_VGPR_32_Lo128RegClass; |
| 416 | extern const TargetRegisterClass AV_288_with_hi16_in_VGPR_16_Lo128_and_AV_288_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 417 | extern const TargetRegisterClass AV_288_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 418 | extern const TargetRegisterClass AV_288_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 419 | extern const TargetRegisterClass AV_288_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 420 | extern const TargetRegisterClass AV_288_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 421 | extern const TargetRegisterClass AV_288_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 422 | extern const TargetRegisterClass AV_288_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 423 | extern const TargetRegisterClass AV_288_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 424 | extern const TargetRegisterClass AV_288_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 425 | extern const TargetRegisterClass AV_288_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 426 | extern const TargetRegisterClass SReg_288RegClass; |
| 427 | extern const TargetRegisterClass SGPR_288RegClass; |
| 428 | extern const TargetRegisterClass SGPR_288_with_sub0_sub1_in_CCR_SGPR_64RegClass; |
| 429 | extern const TargetRegisterClass SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass; |
| 430 | extern const TargetRegisterClass SGPR_288_with_sub2_sub3_in_CCR_SGPR_64RegClass; |
| 431 | extern const TargetRegisterClass SGPR_288_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 432 | extern const TargetRegisterClass SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_288_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 433 | extern const TargetRegisterClass SGPR_288_with_sub6_sub7_in_CCR_SGPR_64RegClass; |
| 434 | extern const TargetRegisterClass TTMP_288RegClass; |
| 435 | extern const TargetRegisterClass AV_320RegClass; |
| 436 | extern const TargetRegisterClass VReg_320RegClass; |
| 437 | extern const TargetRegisterClass AV_320_Align2RegClass; |
| 438 | extern const TargetRegisterClass AV_320_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 439 | extern const TargetRegisterClass VReg_320_Align2RegClass; |
| 440 | extern const TargetRegisterClass AV_320_with_sub1_sub2_in_VReg_64_Align2RegClass; |
| 441 | extern const TargetRegisterClass AV_320_with_sub0_in_VGPR_32_Lo256RegClass; |
| 442 | extern const TargetRegisterClass AV_320_with_sub1_in_VGPR_32_Lo256RegClass; |
| 443 | extern const TargetRegisterClass AV_320_with_sub2_in_VGPR_32_Lo256RegClass; |
| 444 | extern const TargetRegisterClass AV_320_with_sub3_in_VGPR_32_Lo256RegClass; |
| 445 | extern const TargetRegisterClass AV_320_with_sub4_in_VGPR_32_Lo256RegClass; |
| 446 | extern const TargetRegisterClass AV_320_with_sub5_in_VGPR_32_Lo256RegClass; |
| 447 | extern const TargetRegisterClass AV_320_with_sub6_in_VGPR_32_Lo256RegClass; |
| 448 | extern const TargetRegisterClass AV_320_with_sub7_in_VGPR_32_Lo256RegClass; |
| 449 | extern const TargetRegisterClass AV_320_with_sub8_in_VGPR_32_Lo256RegClass; |
| 450 | extern const TargetRegisterClass AReg_320RegClass; |
| 451 | extern const TargetRegisterClass AV_320_with_sub9_in_VGPR_32_Lo256RegClass; |
| 452 | extern const TargetRegisterClass AV_320_with_hi16_in_VGPR_16_Lo128RegClass; |
| 453 | extern const TargetRegisterClass AV_320_with_sub0_in_VGPR_32_Lo256_and_AV_320_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 454 | extern const TargetRegisterClass AV_320_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass; |
| 455 | extern const TargetRegisterClass AV_320_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass; |
| 456 | extern const TargetRegisterClass AV_320_with_sub1_in_VGPR_32_Lo128RegClass; |
| 457 | extern const TargetRegisterClass AV_320_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass; |
| 458 | extern const TargetRegisterClass AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass; |
| 459 | extern const TargetRegisterClass AV_320_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass; |
| 460 | extern const TargetRegisterClass AV_320_with_sub2_in_VGPR_32_Lo128RegClass; |
| 461 | extern const TargetRegisterClass AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClass; |
| 462 | extern const TargetRegisterClass AV_320_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass; |
| 463 | extern const TargetRegisterClass AV_320_with_sub3_in_VGPR_32_Lo128RegClass; |
| 464 | extern const TargetRegisterClass AReg_320_Align2RegClass; |
| 465 | extern const TargetRegisterClass AV_320_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass; |
| 466 | extern const TargetRegisterClass AV_320_with_sub4_in_VGPR_32_Lo128RegClass; |
| 467 | extern const TargetRegisterClass VReg_320_Lo256_Align2RegClass; |
| 468 | extern const TargetRegisterClass AReg_320_with_sub1_sub2_in_AReg_64_Align2RegClass; |
| 469 | extern const TargetRegisterClass AV_320_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClass; |
| 470 | extern const TargetRegisterClass AV_320_with_sub5_in_VGPR_32_Lo128RegClass; |
| 471 | extern const TargetRegisterClass AV_320_with_sub6_in_VGPR_32_Lo128RegClass; |
| 472 | extern const TargetRegisterClass AV_320_with_sub7_in_VGPR_32_Lo128RegClass; |
| 473 | extern const TargetRegisterClass AV_320_with_sub8_in_VGPR_32_Lo128RegClass; |
| 474 | extern const TargetRegisterClass AV_320_with_sub9_in_VGPR_32_Lo128RegClass; |
| 475 | extern const TargetRegisterClass AV_320_with_hi16_in_VGPR_16_Lo128_and_AV_320_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 476 | extern const TargetRegisterClass AV_320_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 477 | extern const TargetRegisterClass AV_320_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 478 | extern const TargetRegisterClass AV_320_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 479 | extern const TargetRegisterClass AV_320_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 480 | extern const TargetRegisterClass AV_320_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 481 | extern const TargetRegisterClass AV_320_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 482 | extern const TargetRegisterClass AV_320_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 483 | extern const TargetRegisterClass AV_320_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 484 | extern const TargetRegisterClass AV_320_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 485 | extern const TargetRegisterClass AV_320_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 486 | extern const TargetRegisterClass SReg_320RegClass; |
| 487 | extern const TargetRegisterClass SGPR_320RegClass; |
| 488 | extern const TargetRegisterClass SGPR_320_with_sub0_sub1_in_CCR_SGPR_64RegClass; |
| 489 | extern const TargetRegisterClass SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass; |
| 490 | extern const TargetRegisterClass SGPR_320_with_sub2_sub3_in_CCR_SGPR_64RegClass; |
| 491 | extern const TargetRegisterClass SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 492 | extern const TargetRegisterClass SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 493 | extern const TargetRegisterClass SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 494 | extern const TargetRegisterClass SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 495 | extern const TargetRegisterClass SGPR_320_with_sub6_sub7_in_CCR_SGPR_64RegClass; |
| 496 | extern const TargetRegisterClass SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 497 | extern const TargetRegisterClass TTMP_320RegClass; |
| 498 | extern const TargetRegisterClass SGPR_320_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 499 | extern const TargetRegisterClass AV_352RegClass; |
| 500 | extern const TargetRegisterClass VReg_352RegClass; |
| 501 | extern const TargetRegisterClass AV_352_Align2RegClass; |
| 502 | extern const TargetRegisterClass AV_352_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 503 | extern const TargetRegisterClass AV_352_with_sub1_sub2_in_VReg_64_Align2RegClass; |
| 504 | extern const TargetRegisterClass VReg_352_Align2RegClass; |
| 505 | extern const TargetRegisterClass AV_352_with_sub0_in_VGPR_32_Lo256RegClass; |
| 506 | extern const TargetRegisterClass AV_352_with_sub1_in_VGPR_32_Lo256RegClass; |
| 507 | extern const TargetRegisterClass AV_352_with_sub2_in_VGPR_32_Lo256RegClass; |
| 508 | extern const TargetRegisterClass AV_352_with_sub3_in_VGPR_32_Lo256RegClass; |
| 509 | extern const TargetRegisterClass AV_352_with_sub4_in_VGPR_32_Lo256RegClass; |
| 510 | extern const TargetRegisterClass AV_352_with_sub5_in_VGPR_32_Lo256RegClass; |
| 511 | extern const TargetRegisterClass AV_352_with_sub6_in_VGPR_32_Lo256RegClass; |
| 512 | extern const TargetRegisterClass AV_352_with_sub7_in_VGPR_32_Lo256RegClass; |
| 513 | extern const TargetRegisterClass AV_352_with_sub8_in_VGPR_32_Lo256RegClass; |
| 514 | extern const TargetRegisterClass AV_352_with_sub9_in_VGPR_32_Lo256RegClass; |
| 515 | extern const TargetRegisterClass AReg_352RegClass; |
| 516 | extern const TargetRegisterClass AV_352_with_sub10_in_VGPR_32_Lo256RegClass; |
| 517 | extern const TargetRegisterClass AV_352_with_hi16_in_VGPR_16_Lo128RegClass; |
| 518 | extern const TargetRegisterClass AV_352_with_sub0_in_VGPR_32_Lo256_and_AV_352_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 519 | extern const TargetRegisterClass AV_352_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass; |
| 520 | extern const TargetRegisterClass AV_352_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass; |
| 521 | extern const TargetRegisterClass AV_352_with_sub1_in_VGPR_32_Lo128RegClass; |
| 522 | extern const TargetRegisterClass AV_352_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass; |
| 523 | extern const TargetRegisterClass AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass; |
| 524 | extern const TargetRegisterClass AV_352_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass; |
| 525 | extern const TargetRegisterClass AV_352_with_sub2_in_VGPR_32_Lo128RegClass; |
| 526 | extern const TargetRegisterClass AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClass; |
| 527 | extern const TargetRegisterClass AV_352_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass; |
| 528 | extern const TargetRegisterClass AV_352_with_sub3_in_VGPR_32_Lo128RegClass; |
| 529 | extern const TargetRegisterClass AV_352_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClass; |
| 530 | extern const TargetRegisterClass AV_352_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass; |
| 531 | extern const TargetRegisterClass AV_352_with_sub4_in_VGPR_32_Lo128RegClass; |
| 532 | extern const TargetRegisterClass AReg_352_Align2RegClass; |
| 533 | extern const TargetRegisterClass AReg_352_with_sub1_sub2_in_AReg_64_Align2RegClass; |
| 534 | extern const TargetRegisterClass AV_352_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClass; |
| 535 | extern const TargetRegisterClass AV_352_with_sub5_in_VGPR_32_Lo128RegClass; |
| 536 | extern const TargetRegisterClass VReg_352_Lo256_Align2RegClass; |
| 537 | extern const TargetRegisterClass AV_352_with_sub6_in_VGPR_32_Lo128RegClass; |
| 538 | extern const TargetRegisterClass AV_352_with_sub7_in_VGPR_32_Lo128RegClass; |
| 539 | extern const TargetRegisterClass AV_352_with_sub8_in_VGPR_32_Lo128RegClass; |
| 540 | extern const TargetRegisterClass AV_352_with_sub9_in_VGPR_32_Lo128RegClass; |
| 541 | extern const TargetRegisterClass AV_352_with_sub10_in_VGPR_32_Lo128RegClass; |
| 542 | extern const TargetRegisterClass AV_352_with_hi16_in_VGPR_16_Lo128_and_AV_352_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 543 | extern const TargetRegisterClass AV_352_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 544 | extern const TargetRegisterClass AV_352_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 545 | extern const TargetRegisterClass AV_352_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 546 | extern const TargetRegisterClass AV_352_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 547 | extern const TargetRegisterClass AV_352_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 548 | extern const TargetRegisterClass AV_352_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 549 | extern const TargetRegisterClass AV_352_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 550 | extern const TargetRegisterClass AV_352_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 551 | extern const TargetRegisterClass AV_352_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 552 | extern const TargetRegisterClass AV_352_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 553 | extern const TargetRegisterClass AV_352_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 554 | extern const TargetRegisterClass SReg_352RegClass; |
| 555 | extern const TargetRegisterClass SGPR_352RegClass; |
| 556 | extern const TargetRegisterClass SGPR_352_with_sub0_sub1_in_CCR_SGPR_64RegClass; |
| 557 | extern const TargetRegisterClass SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass; |
| 558 | extern const TargetRegisterClass SGPR_352_with_sub2_sub3_in_CCR_SGPR_64RegClass; |
| 559 | extern const TargetRegisterClass SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 560 | extern const TargetRegisterClass SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 561 | extern const TargetRegisterClass SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 562 | extern const TargetRegisterClass SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 563 | extern const TargetRegisterClass SGPR_352_with_sub6_sub7_in_CCR_SGPR_64RegClass; |
| 564 | extern const TargetRegisterClass SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 565 | extern const TargetRegisterClass TTMP_352RegClass; |
| 566 | extern const TargetRegisterClass SGPR_352_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 567 | extern const TargetRegisterClass AV_384RegClass; |
| 568 | extern const TargetRegisterClass VReg_384RegClass; |
| 569 | extern const TargetRegisterClass AV_384_Align2RegClass; |
| 570 | extern const TargetRegisterClass AV_384_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 571 | extern const TargetRegisterClass VReg_384_Align2RegClass; |
| 572 | extern const TargetRegisterClass AV_384_with_sub1_sub2_in_VReg_64_Align2RegClass; |
| 573 | extern const TargetRegisterClass AV_384_with_sub0_in_VGPR_32_Lo256RegClass; |
| 574 | extern const TargetRegisterClass AV_384_with_sub1_in_VGPR_32_Lo256RegClass; |
| 575 | extern const TargetRegisterClass AV_384_with_sub2_in_VGPR_32_Lo256RegClass; |
| 576 | extern const TargetRegisterClass AV_384_with_sub3_in_VGPR_32_Lo256RegClass; |
| 577 | extern const TargetRegisterClass AV_384_with_sub4_in_VGPR_32_Lo256RegClass; |
| 578 | extern const TargetRegisterClass AV_384_with_sub5_in_VGPR_32_Lo256RegClass; |
| 579 | extern const TargetRegisterClass AV_384_with_sub6_in_VGPR_32_Lo256RegClass; |
| 580 | extern const TargetRegisterClass AV_384_with_sub7_in_VGPR_32_Lo256RegClass; |
| 581 | extern const TargetRegisterClass AV_384_with_sub8_in_VGPR_32_Lo256RegClass; |
| 582 | extern const TargetRegisterClass AV_384_with_sub9_in_VGPR_32_Lo256RegClass; |
| 583 | extern const TargetRegisterClass AV_384_with_sub10_in_VGPR_32_Lo256RegClass; |
| 584 | extern const TargetRegisterClass AReg_384RegClass; |
| 585 | extern const TargetRegisterClass AV_384_with_sub11_in_VGPR_32_Lo256RegClass; |
| 586 | extern const TargetRegisterClass AV_384_with_hi16_in_VGPR_16_Lo128RegClass; |
| 587 | extern const TargetRegisterClass AV_384_with_sub0_in_VGPR_32_Lo256_and_AV_384_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 588 | extern const TargetRegisterClass AV_384_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass; |
| 589 | extern const TargetRegisterClass AV_384_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass; |
| 590 | extern const TargetRegisterClass AV_384_with_sub1_in_VGPR_32_Lo128RegClass; |
| 591 | extern const TargetRegisterClass AV_384_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass; |
| 592 | extern const TargetRegisterClass AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass; |
| 593 | extern const TargetRegisterClass AV_384_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass; |
| 594 | extern const TargetRegisterClass AV_384_with_sub2_in_VGPR_32_Lo128RegClass; |
| 595 | extern const TargetRegisterClass AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClass; |
| 596 | extern const TargetRegisterClass AV_384_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass; |
| 597 | extern const TargetRegisterClass AV_384_with_sub3_in_VGPR_32_Lo128RegClass; |
| 598 | extern const TargetRegisterClass AV_384_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClass; |
| 599 | extern const TargetRegisterClass AV_384_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass; |
| 600 | extern const TargetRegisterClass AV_384_with_sub4_in_VGPR_32_Lo128RegClass; |
| 601 | extern const TargetRegisterClass AReg_384_Align2RegClass; |
| 602 | extern const TargetRegisterClass AV_384_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClass; |
| 603 | extern const TargetRegisterClass AV_384_with_sub5_in_VGPR_32_Lo128RegClass; |
| 604 | extern const TargetRegisterClass VReg_384_Lo256_Align2RegClass; |
| 605 | extern const TargetRegisterClass AReg_384_with_sub1_sub2_in_AReg_64_Align2RegClass; |
| 606 | extern const TargetRegisterClass AV_384_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 607 | extern const TargetRegisterClass AV_384_with_sub6_in_VGPR_32_Lo128RegClass; |
| 608 | extern const TargetRegisterClass AV_384_with_sub7_in_VGPR_32_Lo128RegClass; |
| 609 | extern const TargetRegisterClass AV_384_with_sub8_in_VGPR_32_Lo128RegClass; |
| 610 | extern const TargetRegisterClass AV_384_with_sub9_in_VGPR_32_Lo128RegClass; |
| 611 | extern const TargetRegisterClass AV_384_with_sub10_in_VGPR_32_Lo128RegClass; |
| 612 | extern const TargetRegisterClass AV_384_with_sub11_in_VGPR_32_Lo128RegClass; |
| 613 | extern const TargetRegisterClass AV_384_with_hi16_in_VGPR_16_Lo128_and_AV_384_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 614 | extern const TargetRegisterClass AV_384_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 615 | extern const TargetRegisterClass AV_384_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 616 | extern const TargetRegisterClass AV_384_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 617 | extern const TargetRegisterClass AV_384_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 618 | extern const TargetRegisterClass AV_384_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 619 | extern const TargetRegisterClass AV_384_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 620 | extern const TargetRegisterClass AV_384_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 621 | extern const TargetRegisterClass AV_384_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 622 | extern const TargetRegisterClass AV_384_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 623 | extern const TargetRegisterClass AV_384_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 624 | extern const TargetRegisterClass AV_384_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 625 | extern const TargetRegisterClass AV_384_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 626 | extern const TargetRegisterClass SReg_384RegClass; |
| 627 | extern const TargetRegisterClass SGPR_384RegClass; |
| 628 | extern const TargetRegisterClass SGPR_384_with_sub0_sub1_in_CCR_SGPR_64RegClass; |
| 629 | extern const TargetRegisterClass SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass; |
| 630 | extern const TargetRegisterClass SGPR_384_with_sub2_sub3_in_CCR_SGPR_64RegClass; |
| 631 | extern const TargetRegisterClass SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 632 | extern const TargetRegisterClass SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 633 | extern const TargetRegisterClass SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 634 | extern const TargetRegisterClass SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 635 | extern const TargetRegisterClass SGPR_384_with_sub6_sub7_in_CCR_SGPR_64RegClass; |
| 636 | extern const TargetRegisterClass SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 637 | extern const TargetRegisterClass SGPR_384_with_sub10_sub11_in_CCR_SGPR_64RegClass; |
| 638 | extern const TargetRegisterClass TTMP_384RegClass; |
| 639 | extern const TargetRegisterClass SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 640 | extern const TargetRegisterClass AV_512RegClass; |
| 641 | extern const TargetRegisterClass VReg_512RegClass; |
| 642 | extern const TargetRegisterClass AV_512_Align2RegClass; |
| 643 | extern const TargetRegisterClass AV_512_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 644 | extern const TargetRegisterClass VReg_512_Align2RegClass; |
| 645 | extern const TargetRegisterClass AV_512_with_sub1_sub2_in_VReg_64_Align2RegClass; |
| 646 | extern const TargetRegisterClass AV_512_with_sub0_in_VGPR_32_Lo256RegClass; |
| 647 | extern const TargetRegisterClass AV_512_with_sub1_in_VGPR_32_Lo256RegClass; |
| 648 | extern const TargetRegisterClass AV_512_with_sub2_in_VGPR_32_Lo256RegClass; |
| 649 | extern const TargetRegisterClass AV_512_with_sub3_in_VGPR_32_Lo256RegClass; |
| 650 | extern const TargetRegisterClass AV_512_with_sub4_in_VGPR_32_Lo256RegClass; |
| 651 | extern const TargetRegisterClass AV_512_with_sub5_in_VGPR_32_Lo256RegClass; |
| 652 | extern const TargetRegisterClass AV_512_with_sub6_in_VGPR_32_Lo256RegClass; |
| 653 | extern const TargetRegisterClass AV_512_with_sub7_in_VGPR_32_Lo256RegClass; |
| 654 | extern const TargetRegisterClass AV_512_with_sub8_in_VGPR_32_Lo256RegClass; |
| 655 | extern const TargetRegisterClass AV_512_with_sub9_in_VGPR_32_Lo256RegClass; |
| 656 | extern const TargetRegisterClass AV_512_with_sub10_in_VGPR_32_Lo256RegClass; |
| 657 | extern const TargetRegisterClass AV_512_with_sub11_in_VGPR_32_Lo256RegClass; |
| 658 | extern const TargetRegisterClass AV_512_with_sub12_in_VGPR_32_Lo256RegClass; |
| 659 | extern const TargetRegisterClass AV_512_with_sub13_in_VGPR_32_Lo256RegClass; |
| 660 | extern const TargetRegisterClass AV_512_with_sub14_in_VGPR_32_Lo256RegClass; |
| 661 | extern const TargetRegisterClass AReg_512RegClass; |
| 662 | extern const TargetRegisterClass AV_512_with_sub15_in_VGPR_32_Lo256RegClass; |
| 663 | extern const TargetRegisterClass AV_512_with_hi16_in_VGPR_16_Lo128RegClass; |
| 664 | extern const TargetRegisterClass AV_512_with_sub0_in_VGPR_32_Lo256_and_AV_512_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 665 | extern const TargetRegisterClass AV_512_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass; |
| 666 | extern const TargetRegisterClass AV_512_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass; |
| 667 | extern const TargetRegisterClass AV_512_with_sub1_in_VGPR_32_Lo128RegClass; |
| 668 | extern const TargetRegisterClass AV_512_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass; |
| 669 | extern const TargetRegisterClass AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass; |
| 670 | extern const TargetRegisterClass AV_512_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass; |
| 671 | extern const TargetRegisterClass AV_512_with_sub2_in_VGPR_32_Lo128RegClass; |
| 672 | extern const TargetRegisterClass AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClass; |
| 673 | extern const TargetRegisterClass AV_512_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass; |
| 674 | extern const TargetRegisterClass AV_512_with_sub3_in_VGPR_32_Lo128RegClass; |
| 675 | extern const TargetRegisterClass AV_512_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClass; |
| 676 | extern const TargetRegisterClass AV_512_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass; |
| 677 | extern const TargetRegisterClass AV_512_with_sub4_in_VGPR_32_Lo128RegClass; |
| 678 | extern const TargetRegisterClass AV_512_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_384_Lo256_Align2RegClass; |
| 679 | extern const TargetRegisterClass AV_512_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClass; |
| 680 | extern const TargetRegisterClass AV_512_with_sub5_in_VGPR_32_Lo128RegClass; |
| 681 | extern const TargetRegisterClass AV_512_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 682 | extern const TargetRegisterClass AV_512_with_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 683 | extern const TargetRegisterClass AV_512_with_sub6_in_VGPR_32_Lo128RegClass; |
| 684 | extern const TargetRegisterClass AReg_512_Align2RegClass; |
| 685 | extern const TargetRegisterClass AV_512_with_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 686 | extern const TargetRegisterClass AV_512_with_sub7_in_VGPR_32_Lo128RegClass; |
| 687 | extern const TargetRegisterClass VReg_512_Lo256_Align2RegClass; |
| 688 | extern const TargetRegisterClass AReg_512_with_sub1_sub2_in_AReg_64_Align2RegClass; |
| 689 | extern const TargetRegisterClass AV_512_with_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 690 | extern const TargetRegisterClass AV_512_with_sub8_in_VGPR_32_Lo128RegClass; |
| 691 | extern const TargetRegisterClass AV_512_with_sub9_in_VGPR_32_Lo128RegClass; |
| 692 | extern const TargetRegisterClass AV_512_with_sub10_in_VGPR_32_Lo128RegClass; |
| 693 | extern const TargetRegisterClass AV_512_with_sub11_in_VGPR_32_Lo128RegClass; |
| 694 | extern const TargetRegisterClass AV_512_with_sub12_in_VGPR_32_Lo128RegClass; |
| 695 | extern const TargetRegisterClass AV_512_with_sub13_in_VGPR_32_Lo128RegClass; |
| 696 | extern const TargetRegisterClass AV_512_with_sub14_in_VGPR_32_Lo128RegClass; |
| 697 | extern const TargetRegisterClass AV_512_with_sub15_in_VGPR_32_Lo128RegClass; |
| 698 | extern const TargetRegisterClass AV_512_with_hi16_in_VGPR_16_Lo128_and_AV_512_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 699 | extern const TargetRegisterClass AV_512_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 700 | extern const TargetRegisterClass AV_512_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 701 | extern const TargetRegisterClass AV_512_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 702 | extern const TargetRegisterClass AV_512_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 703 | extern const TargetRegisterClass AV_512_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 704 | extern const TargetRegisterClass AV_512_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 705 | extern const TargetRegisterClass AV_512_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 706 | extern const TargetRegisterClass AV_512_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 707 | extern const TargetRegisterClass AV_512_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 708 | extern const TargetRegisterClass AV_512_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 709 | extern const TargetRegisterClass AV_512_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 710 | extern const TargetRegisterClass AV_512_with_sub10_sub11_sub12_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 711 | extern const TargetRegisterClass AV_512_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 712 | extern const TargetRegisterClass AV_512_with_sub11_sub12_sub13_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 713 | extern const TargetRegisterClass AV_512_with_sub12_sub13_sub14_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 714 | extern const TargetRegisterClass AV_512_with_sub13_sub14_sub15_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 715 | extern const TargetRegisterClass SReg_512RegClass; |
| 716 | extern const TargetRegisterClass SGPR_512RegClass; |
| 717 | extern const TargetRegisterClass SGPR_512_with_sub0_sub1_in_CCR_SGPR_64RegClass; |
| 718 | extern const TargetRegisterClass SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass; |
| 719 | extern const TargetRegisterClass SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 720 | extern const TargetRegisterClass SGPR_512_with_sub2_sub3_in_CCR_SGPR_64RegClass; |
| 721 | extern const TargetRegisterClass SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 722 | extern const TargetRegisterClass SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 723 | extern const TargetRegisterClass SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 724 | extern const TargetRegisterClass SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 725 | extern const TargetRegisterClass SGPR_512_with_sub6_sub7_in_CCR_SGPR_64RegClass; |
| 726 | extern const TargetRegisterClass SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 727 | extern const TargetRegisterClass SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 728 | extern const TargetRegisterClass SGPR_512_with_sub10_sub11_in_CCR_SGPR_64RegClass; |
| 729 | extern const TargetRegisterClass SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 730 | extern const TargetRegisterClass SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 731 | extern const TargetRegisterClass SGPR_512_with_sub14_sub15_in_CCR_SGPR_64RegClass; |
| 732 | extern const TargetRegisterClass SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 733 | extern const TargetRegisterClass SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 734 | extern const TargetRegisterClass SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 735 | extern const TargetRegisterClass TTMP_512RegClass; |
| 736 | extern const TargetRegisterClass AV_1024RegClass; |
| 737 | extern const TargetRegisterClass VReg_1024RegClass; |
| 738 | extern const TargetRegisterClass AV_1024_Align2RegClass; |
| 739 | extern const TargetRegisterClass AV_1024_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 740 | extern const TargetRegisterClass VReg_1024_Align2RegClass; |
| 741 | extern const TargetRegisterClass AV_1024_with_sub1_sub2_in_VReg_64_Align2RegClass; |
| 742 | extern const TargetRegisterClass AV_1024_with_sub0_in_VGPR_32_Lo256RegClass; |
| 743 | extern const TargetRegisterClass AV_1024_with_sub1_in_VGPR_32_Lo256RegClass; |
| 744 | extern const TargetRegisterClass AV_1024_with_sub2_in_VGPR_32_Lo256RegClass; |
| 745 | extern const TargetRegisterClass AV_1024_with_sub3_in_VGPR_32_Lo256RegClass; |
| 746 | extern const TargetRegisterClass AV_1024_with_sub4_in_VGPR_32_Lo256RegClass; |
| 747 | extern const TargetRegisterClass AV_1024_with_sub5_in_VGPR_32_Lo256RegClass; |
| 748 | extern const TargetRegisterClass AV_1024_with_sub6_in_VGPR_32_Lo256RegClass; |
| 749 | extern const TargetRegisterClass AV_1024_with_sub7_in_VGPR_32_Lo256RegClass; |
| 750 | extern const TargetRegisterClass AV_1024_with_sub8_in_VGPR_32_Lo256RegClass; |
| 751 | extern const TargetRegisterClass AV_1024_with_sub9_in_VGPR_32_Lo256RegClass; |
| 752 | extern const TargetRegisterClass AV_1024_with_sub10_in_VGPR_32_Lo256RegClass; |
| 753 | extern const TargetRegisterClass AV_1024_with_sub11_in_VGPR_32_Lo256RegClass; |
| 754 | extern const TargetRegisterClass AV_1024_with_sub12_in_VGPR_32_Lo256RegClass; |
| 755 | extern const TargetRegisterClass AV_1024_with_sub13_in_VGPR_32_Lo256RegClass; |
| 756 | extern const TargetRegisterClass AV_1024_with_sub14_in_VGPR_32_Lo256RegClass; |
| 757 | extern const TargetRegisterClass AV_1024_with_sub15_in_VGPR_32_Lo256RegClass; |
| 758 | extern const TargetRegisterClass AV_1024_with_sub16_in_VGPR_32_Lo256RegClass; |
| 759 | extern const TargetRegisterClass AV_1024_with_sub17_in_VGPR_32_Lo256RegClass; |
| 760 | extern const TargetRegisterClass AV_1024_with_sub18_in_VGPR_32_Lo256RegClass; |
| 761 | extern const TargetRegisterClass AV_1024_with_sub19_in_VGPR_32_Lo256RegClass; |
| 762 | extern const TargetRegisterClass AV_1024_with_sub20_in_VGPR_32_Lo256RegClass; |
| 763 | extern const TargetRegisterClass AV_1024_with_sub21_in_VGPR_32_Lo256RegClass; |
| 764 | extern const TargetRegisterClass AV_1024_with_sub22_in_VGPR_32_Lo256RegClass; |
| 765 | extern const TargetRegisterClass AV_1024_with_sub23_in_VGPR_32_Lo256RegClass; |
| 766 | extern const TargetRegisterClass AV_1024_with_sub24_in_VGPR_32_Lo256RegClass; |
| 767 | extern const TargetRegisterClass AV_1024_with_sub25_in_VGPR_32_Lo256RegClass; |
| 768 | extern const TargetRegisterClass AV_1024_with_sub26_in_VGPR_32_Lo256RegClass; |
| 769 | extern const TargetRegisterClass AV_1024_with_sub27_in_VGPR_32_Lo256RegClass; |
| 770 | extern const TargetRegisterClass AV_1024_with_sub28_in_VGPR_32_Lo256RegClass; |
| 771 | extern const TargetRegisterClass AV_1024_with_sub29_in_VGPR_32_Lo256RegClass; |
| 772 | extern const TargetRegisterClass AV_1024_with_sub30_in_VGPR_32_Lo256RegClass; |
| 773 | extern const TargetRegisterClass AReg_1024RegClass; |
| 774 | extern const TargetRegisterClass AV_1024_with_sub31_in_VGPR_32_Lo256RegClass; |
| 775 | extern const TargetRegisterClass AV_1024_with_hi16_in_VGPR_16_Lo128RegClass; |
| 776 | extern const TargetRegisterClass AV_1024_with_sub0_in_VGPR_32_Lo256_and_AV_1024_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 777 | extern const TargetRegisterClass AV_1024_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass; |
| 778 | extern const TargetRegisterClass AV_1024_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass; |
| 779 | extern const TargetRegisterClass AV_1024_with_sub1_in_VGPR_32_Lo128RegClass; |
| 780 | extern const TargetRegisterClass AV_1024_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass; |
| 781 | extern const TargetRegisterClass AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass; |
| 782 | extern const TargetRegisterClass AV_1024_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass; |
| 783 | extern const TargetRegisterClass AV_1024_with_sub2_in_VGPR_32_Lo128RegClass; |
| 784 | extern const TargetRegisterClass AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClass; |
| 785 | extern const TargetRegisterClass AV_1024_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass; |
| 786 | extern const TargetRegisterClass AV_1024_with_sub3_in_VGPR_32_Lo128RegClass; |
| 787 | extern const TargetRegisterClass AV_1024_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClass; |
| 788 | extern const TargetRegisterClass AV_1024_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass; |
| 789 | extern const TargetRegisterClass AV_1024_with_sub4_in_VGPR_32_Lo128RegClass; |
| 790 | extern const TargetRegisterClass AV_1024_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_384_Lo256_Align2RegClass; |
| 791 | extern const TargetRegisterClass AV_1024_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClass; |
| 792 | extern const TargetRegisterClass AV_1024_with_sub5_in_VGPR_32_Lo128RegClass; |
| 793 | extern const TargetRegisterClass AV_1024_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 794 | extern const TargetRegisterClass AV_1024_with_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 795 | extern const TargetRegisterClass AV_1024_with_sub6_in_VGPR_32_Lo128RegClass; |
| 796 | extern const TargetRegisterClass AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_VReg_512_Lo256_Align2RegClass; |
| 797 | extern const TargetRegisterClass AV_1024_with_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 798 | extern const TargetRegisterClass AV_1024_with_sub7_in_VGPR_32_Lo128RegClass; |
| 799 | extern const TargetRegisterClass AV_1024_with_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 800 | extern const TargetRegisterClass AV_1024_with_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 801 | extern const TargetRegisterClass AV_1024_with_sub8_in_VGPR_32_Lo128RegClass; |
| 802 | extern const TargetRegisterClass AV_1024_with_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 803 | extern const TargetRegisterClass AV_1024_with_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 804 | extern const TargetRegisterClass AV_1024_with_sub9_in_VGPR_32_Lo128RegClass; |
| 805 | extern const TargetRegisterClass AV_1024_with_sub10_in_VGPR_32_Lo128RegClass; |
| 806 | extern const TargetRegisterClass AV_1024_with_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 807 | extern const TargetRegisterClass AV_1024_with_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 808 | extern const TargetRegisterClass AV_1024_with_sub11_in_VGPR_32_Lo128RegClass; |
| 809 | extern const TargetRegisterClass AV_1024_with_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 810 | extern const TargetRegisterClass AV_1024_with_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 811 | extern const TargetRegisterClass AV_1024_with_sub12_in_VGPR_32_Lo128RegClass; |
| 812 | extern const TargetRegisterClass AV_1024_with_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 813 | extern const TargetRegisterClass AV_1024_with_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 814 | extern const TargetRegisterClass AV_1024_with_sub13_in_VGPR_32_Lo128RegClass; |
| 815 | extern const TargetRegisterClass AV_1024_with_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 816 | extern const TargetRegisterClass AV_1024_with_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 817 | extern const TargetRegisterClass AV_1024_with_sub14_in_VGPR_32_Lo128RegClass; |
| 818 | extern const TargetRegisterClass AV_1024_with_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 819 | extern const TargetRegisterClass AV_1024_with_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 820 | extern const TargetRegisterClass AReg_1024_Align2RegClass; |
| 821 | extern const TargetRegisterClass AV_1024_with_sub15_in_VGPR_32_Lo128RegClass; |
| 822 | extern const TargetRegisterClass AV_1024_with_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 823 | extern const TargetRegisterClass VReg_1024_Lo256_Align2RegClass; |
| 824 | extern const TargetRegisterClass AReg_1024_with_sub1_sub2_in_AReg_64_Align2RegClass; |
| 825 | extern const TargetRegisterClass AV_1024_with_sub16_in_VGPR_32_Lo128RegClass; |
| 826 | extern const TargetRegisterClass AV_1024_with_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16_in_VReg_352_Lo256_Align2RegClass; |
| 827 | extern const TargetRegisterClass AV_1024_with_sub17_in_VGPR_32_Lo128RegClass; |
| 828 | extern const TargetRegisterClass AV_1024_with_sub18_in_VGPR_32_Lo128RegClass; |
| 829 | extern const TargetRegisterClass AV_1024_with_sub19_in_VGPR_32_Lo128RegClass; |
| 830 | extern const TargetRegisterClass AV_1024_with_sub20_in_VGPR_32_Lo128RegClass; |
| 831 | extern const TargetRegisterClass AV_1024_with_sub21_in_VGPR_32_Lo128RegClass; |
| 832 | extern const TargetRegisterClass AV_1024_with_sub22_in_VGPR_32_Lo128RegClass; |
| 833 | extern const TargetRegisterClass AV_1024_with_sub23_in_VGPR_32_Lo128RegClass; |
| 834 | extern const TargetRegisterClass AV_1024_with_sub24_in_VGPR_32_Lo128RegClass; |
| 835 | extern const TargetRegisterClass AV_1024_with_sub25_in_VGPR_32_Lo128RegClass; |
| 836 | extern const TargetRegisterClass AV_1024_with_sub26_in_VGPR_32_Lo128RegClass; |
| 837 | extern const TargetRegisterClass AV_1024_with_sub27_in_VGPR_32_Lo128RegClass; |
| 838 | extern const TargetRegisterClass AV_1024_with_sub28_in_VGPR_32_Lo128RegClass; |
| 839 | extern const TargetRegisterClass AV_1024_with_sub29_in_VGPR_32_Lo128RegClass; |
| 840 | extern const TargetRegisterClass AV_1024_with_sub30_in_VGPR_32_Lo128RegClass; |
| 841 | extern const TargetRegisterClass AV_1024_with_sub31_in_VGPR_32_Lo128RegClass; |
| 842 | extern const TargetRegisterClass AV_1024_with_hi16_in_VGPR_16_Lo128_and_AV_1024_with_sub1_sub2_in_AV_64_Align2RegClass; |
| 843 | extern const TargetRegisterClass AV_1024_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 844 | extern const TargetRegisterClass AV_1024_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 845 | extern const TargetRegisterClass AV_1024_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass; |
| 846 | extern const TargetRegisterClass AV_1024_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 847 | extern const TargetRegisterClass AV_1024_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 848 | extern const TargetRegisterClass AV_1024_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 849 | extern const TargetRegisterClass AV_1024_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 850 | extern const TargetRegisterClass AV_1024_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 851 | extern const TargetRegisterClass AV_1024_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 852 | extern const TargetRegisterClass AV_1024_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 853 | extern const TargetRegisterClass AV_1024_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 854 | extern const TargetRegisterClass AV_1024_with_sub10_sub11_sub12_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 855 | extern const TargetRegisterClass AV_1024_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 856 | extern const TargetRegisterClass AV_1024_with_sub11_sub12_sub13_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 857 | extern const TargetRegisterClass AV_1024_with_sub12_sub13_sub14_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 858 | extern const TargetRegisterClass AV_1024_with_sub13_sub14_sub15_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 859 | extern const TargetRegisterClass AV_1024_with_sub14_sub15_sub16_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 860 | extern const TargetRegisterClass AV_1024_with_sub15_sub16_sub17_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 861 | extern const TargetRegisterClass AV_1024_with_sub16_sub17_sub18_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 862 | extern const TargetRegisterClass AV_1024_with_sub17_sub18_sub19_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 863 | extern const TargetRegisterClass AV_1024_with_sub18_sub19_sub20_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 864 | extern const TargetRegisterClass AV_1024_with_sub19_sub20_sub21_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 865 | extern const TargetRegisterClass AV_1024_with_sub20_sub21_sub22_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 866 | extern const TargetRegisterClass AV_1024_with_sub21_sub22_sub23_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 867 | extern const TargetRegisterClass AV_1024_with_sub22_sub23_sub24_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 868 | extern const TargetRegisterClass AV_1024_with_sub23_sub24_sub25_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 869 | extern const TargetRegisterClass AV_1024_with_sub24_sub25_sub26_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 870 | extern const TargetRegisterClass AV_1024_with_sub25_sub26_sub27_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 871 | extern const TargetRegisterClass AV_1024_with_sub26_sub27_sub28_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 872 | extern const TargetRegisterClass AV_1024_with_sub27_sub28_sub29_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 873 | extern const TargetRegisterClass AV_1024_with_sub28_sub29_sub30_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 874 | extern const TargetRegisterClass AV_1024_with_sub29_sub30_sub31_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass; |
| 875 | extern const TargetRegisterClass SGPR_1024RegClass; |
| 876 | extern const TargetRegisterClass SReg_1024RegClass; |
| 877 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClass; |
| 878 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass; |
| 879 | extern const TargetRegisterClass SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 880 | extern const TargetRegisterClass SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClass; |
| 881 | extern const TargetRegisterClass SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass; |
| 882 | extern const TargetRegisterClass SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass; |
| 883 | extern const TargetRegisterClass SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass; |
| 884 | extern const TargetRegisterClass SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64RegClass; |
| 885 | extern const TargetRegisterClass SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 886 | extern const TargetRegisterClass SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 887 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass; |
| 888 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass; |
| 889 | extern const TargetRegisterClass SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClass; |
| 890 | extern const TargetRegisterClass SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass; |
| 891 | extern const TargetRegisterClass SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass; |
| 892 | extern const TargetRegisterClass SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass; |
| 893 | extern const TargetRegisterClass SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 894 | extern const TargetRegisterClass SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64RegClass; |
| 895 | extern const TargetRegisterClass SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 896 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass; |
| 897 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 898 | extern const TargetRegisterClass SGPR_1024_with_sub10_sub11_in_CCR_SGPR_64RegClass; |
| 899 | extern const TargetRegisterClass SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass; |
| 900 | extern const TargetRegisterClass SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass; |
| 901 | extern const TargetRegisterClass SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass; |
| 902 | extern const TargetRegisterClass SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass; |
| 903 | extern const TargetRegisterClass SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 904 | extern const TargetRegisterClass SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClass; |
| 905 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass; |
| 906 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 907 | extern const TargetRegisterClass SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass; |
| 908 | extern const TargetRegisterClass SGPR_1024_with_sub14_sub15_in_CCR_SGPR_64RegClass; |
| 909 | extern const TargetRegisterClass SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass; |
| 910 | extern const TargetRegisterClass SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass; |
| 911 | extern const TargetRegisterClass SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClass; |
| 912 | extern const TargetRegisterClass SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass; |
| 913 | extern const TargetRegisterClass SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass; |
| 914 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClass; |
| 915 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClass; |
| 916 | extern const TargetRegisterClass SGPR_1024_with_sub10_sub11_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass; |
| 917 | extern const TargetRegisterClass SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass; |
| 918 | extern const TargetRegisterClass SGPR_1024_with_sub18_sub19_in_CCR_SGPR_64RegClass; |
| 919 | extern const TargetRegisterClass SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass; |
| 920 | extern const TargetRegisterClass SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass; |
| 921 | extern const TargetRegisterClass SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass; |
| 922 | extern const TargetRegisterClass SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass; |
| 923 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 924 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 925 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 926 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 927 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass; |
| 928 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass; |
| 929 | extern const TargetRegisterClass SGPR_1024_with_sub22_sub23_in_CCR_SGPR_64RegClass; |
| 930 | extern const TargetRegisterClass SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass; |
| 931 | extern const TargetRegisterClass SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass; |
| 932 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 933 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 934 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 935 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 936 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 937 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass; |
| 938 | extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass; |
| 939 | extern const TargetRegisterClass SGPR_1024_with_sub26_sub27_in_CCR_SGPR_64RegClass; |
| 940 | extern const TargetRegisterClass SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass; |
| 941 | } // end namespace AMDGPU |
| 942 | |
| 943 | } // end namespace llvm |
| 944 | |
| 945 |
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