| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Register Information Header Fragment *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #include "llvm/CodeGen/TargetRegisterInfo.h" |
| 10 | |
| 11 | namespace llvm { |
| 12 | |
| 13 | class AMDGPUFrameLowering; |
| 14 | |
| 15 | extern const MCRegisterClassStorage<889, 161388, 1500754, 432208, 767, 13651> AMDGPUMCRegisterClassStorage; |
| 16 | |
| 17 | struct AMDGPUGenRegisterInfo : public TargetRegisterInfo { |
| 18 | explicit AMDGPUGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, |
| 19 | unsigned PC = 0, unsigned HwMode = 0); |
| 20 | unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; |
| 21 | unsigned reverseComposeSubRegIndicesImpl(unsigned, unsigned) const override; |
| 22 | LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
| 23 | LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
| 24 | const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override; |
| 25 | const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override; |
| 26 | const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; |
| 27 | unsigned getRegUnitWeight(MCRegUnit RegUnit) const override; |
| 28 | unsigned getNumRegPressureSets() const override; |
| 29 | const char *getRegPressureSetName(unsigned Idx) const override; |
| 30 | unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; |
| 31 | const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; |
| 32 | const int *getRegUnitPressureSets(MCRegUnit RegUnit) const override; |
| 33 | ArrayRef<const char *> getRegMaskNames() const override; |
| 34 | ArrayRef<const uint32_t *> getRegMasks() const override; |
| 35 | bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override; |
| 36 | bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const override; |
| 37 | bool isFixedRegister(const MachineFunction &, MCRegister) const override; |
| 38 | bool isArgumentRegister(const MachineFunction &, MCRegister) const override; |
| 39 | bool isConstantPhysReg(MCRegister PhysReg) const override final; |
| 40 | /// Devirtualized TargetFrameLowering. |
| 41 | static const AMDGPUFrameLowering *getFrameLowering( |
| 42 | const MachineFunction &MF); |
| 43 | const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) const override; |
| 44 | const TargetRegisterClass *getMinimalPhysRegClass(MCRegister Reg) const override; |
| 45 | }; |
| 46 | |
| 47 | namespace AMDGPU { |
| 48 | |
| 49 | // Register classes |
| 50 | static constexpr const TargetRegisterClass &SCC_CLASSRegClass = AMDGPUMCRegisterClassStorage.Classes[0]; |
| 51 | static constexpr const TargetRegisterClass &VReg_1RegClass = AMDGPUMCRegisterClassStorage.Classes[1]; |
| 52 | static constexpr const TargetRegisterClass &VS_16RegClass = AMDGPUMCRegisterClassStorage.Classes[2]; |
| 53 | static constexpr const TargetRegisterClass &VGPR_16RegClass = AMDGPUMCRegisterClassStorage.Classes[3]; |
| 54 | static constexpr const TargetRegisterClass &VS_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[4]; |
| 55 | static constexpr const TargetRegisterClass &AGPR_LO16RegClass = AMDGPUMCRegisterClassStorage.Classes[5]; |
| 56 | static constexpr const TargetRegisterClass &VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[6]; |
| 57 | static constexpr const TargetRegisterClass &SReg_LO16RegClass = AMDGPUMCRegisterClassStorage.Classes[7]; |
| 58 | static constexpr const TargetRegisterClass &VS_16_with_hi16RegClass = AMDGPUMCRegisterClassStorage.Classes[8]; |
| 59 | static constexpr const TargetRegisterClass &SGPR_LO16RegClass = AMDGPUMCRegisterClassStorage.Classes[9]; |
| 60 | static constexpr const TargetRegisterClass &VS_16_with_hi16_with_lo16_in_SGPR_LO16RegClass = AMDGPUMCRegisterClassStorage.Classes[10]; |
| 61 | static constexpr const TargetRegisterClass &TTMP_LO16RegClass = AMDGPUMCRegisterClassStorage.Classes[11]; |
| 62 | static constexpr const TargetRegisterClass &VS_16_with_hi16_with_lo16_in_TTMP_LO16RegClass = AMDGPUMCRegisterClassStorage.Classes[12]; |
| 63 | static constexpr const TargetRegisterClass &AV_32RegClass = AMDGPUMCRegisterClassStorage.Classes[13]; |
| 64 | static constexpr const TargetRegisterClass &VS_32RegClass = AMDGPUMCRegisterClassStorage.Classes[14]; |
| 65 | static constexpr const TargetRegisterClass &VRegOrLds_32RegClass = AMDGPUMCRegisterClassStorage.Classes[15]; |
| 66 | static constexpr const TargetRegisterClass &VGPR_32RegClass = AMDGPUMCRegisterClassStorage.Classes[16]; |
| 67 | static constexpr const TargetRegisterClass &VS_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[17]; |
| 68 | static constexpr const TargetRegisterClass &VS_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[18]; |
| 69 | static constexpr const TargetRegisterClass &AGPR_32RegClass = AMDGPUMCRegisterClassStorage.Classes[19]; |
| 70 | static constexpr const TargetRegisterClass &VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[20]; |
| 71 | static constexpr const TargetRegisterClass &SRegOrLds_32RegClass = AMDGPUMCRegisterClassStorage.Classes[21]; |
| 72 | static constexpr const TargetRegisterClass &SReg_32RegClass = AMDGPUMCRegisterClassStorage.Classes[22]; |
| 73 | static constexpr const TargetRegisterClass &SReg_32_XEXEC_HIRegClass = AMDGPUMCRegisterClassStorage.Classes[23]; |
| 74 | static constexpr const TargetRegisterClass &SReg_32_XM0RegClass = AMDGPUMCRegisterClassStorage.Classes[24]; |
| 75 | static constexpr const TargetRegisterClass &SReg_32_XEXECRegClass = AMDGPUMCRegisterClassStorage.Classes[25]; |
| 76 | static constexpr const TargetRegisterClass &SReg_32_XEXEC_HI_and_SReg_32_XM0RegClass = AMDGPUMCRegisterClassStorage.Classes[26]; |
| 77 | static constexpr const TargetRegisterClass &SReg_32_XM0_XEXECRegClass = AMDGPUMCRegisterClassStorage.Classes[27]; |
| 78 | static constexpr const TargetRegisterClass &VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[28]; |
| 79 | static constexpr const TargetRegisterClass &SGPR_32RegClass = AMDGPUMCRegisterClassStorage.Classes[29]; |
| 80 | static constexpr const TargetRegisterClass &TTMP_32RegClass = AMDGPUMCRegisterClassStorage.Classes[30]; |
| 81 | static constexpr const TargetRegisterClass &Pseudo_SReg_32RegClass = AMDGPUMCRegisterClassStorage.Classes[31]; |
| 82 | static constexpr const TargetRegisterClass &AV_64RegClass = AMDGPUMCRegisterClassStorage.Classes[32]; |
| 83 | static constexpr const TargetRegisterClass &VS_64RegClass = AMDGPUMCRegisterClassStorage.Classes[33]; |
| 84 | static constexpr const TargetRegisterClass &VS_64_with_sub1RegClass = AMDGPUMCRegisterClassStorage.Classes[34]; |
| 85 | static constexpr const TargetRegisterClass &VReg_64RegClass = AMDGPUMCRegisterClassStorage.Classes[35]; |
| 86 | static constexpr const TargetRegisterClass &AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[36]; |
| 87 | static constexpr const TargetRegisterClass &VS_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[37]; |
| 88 | static constexpr const TargetRegisterClass &VS_64_Align2_with_sub1RegClass = AMDGPUMCRegisterClassStorage.Classes[38]; |
| 89 | static constexpr const TargetRegisterClass &VReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[39]; |
| 90 | static constexpr const TargetRegisterClass &VS_64_with_sub0_in_VS_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[40]; |
| 91 | static constexpr const TargetRegisterClass &VS_64_with_sub1_and_VS_64_with_sub0_in_VS_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[41]; |
| 92 | static constexpr const TargetRegisterClass &VS_64_with_sub1_with_sub1_in_VS_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[42]; |
| 93 | static constexpr const TargetRegisterClass &AV_64_with_sub0_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[43]; |
| 94 | static constexpr const TargetRegisterClass &AReg_64RegClass = AMDGPUMCRegisterClassStorage.Classes[44]; |
| 95 | static constexpr const TargetRegisterClass &AV_64_with_sub1_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[45]; |
| 96 | static constexpr const TargetRegisterClass &VS_64_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[46]; |
| 97 | static constexpr const TargetRegisterClass &VS_64_with_sub0_in_VS_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[47]; |
| 98 | static constexpr const TargetRegisterClass &VS_64_Lo256_with_sub1RegClass = AMDGPUMCRegisterClassStorage.Classes[48]; |
| 99 | static constexpr const TargetRegisterClass &VS_64_with_sub1_and_VS_64_with_sub0_in_VS_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[49]; |
| 100 | static constexpr const TargetRegisterClass &VS_64_with_sub1_with_sub1_in_VS_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[50]; |
| 101 | static constexpr const TargetRegisterClass &VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[51]; |
| 102 | static constexpr const TargetRegisterClass &VS_64_with_sub1_and_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[52]; |
| 103 | static constexpr const TargetRegisterClass &AReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[53]; |
| 104 | static constexpr const TargetRegisterClass &AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[54]; |
| 105 | static constexpr const TargetRegisterClass &VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[55]; |
| 106 | static constexpr const TargetRegisterClass &AV_64_with_sub1_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[56]; |
| 107 | static constexpr const TargetRegisterClass &SReg_64_EncodableRegClass = AMDGPUMCRegisterClassStorage.Classes[57]; |
| 108 | static constexpr const TargetRegisterClass &SReg_64_Encodable_with_sub0_in_SReg_32_XEXECRegClass = AMDGPUMCRegisterClassStorage.Classes[58]; |
| 109 | static constexpr const TargetRegisterClass &SReg_64RegClass = AMDGPUMCRegisterClassStorage.Classes[59]; |
| 110 | static constexpr const TargetRegisterClass &SReg_64_XEXECRegClass = AMDGPUMCRegisterClassStorage.Classes[60]; |
| 111 | static constexpr const TargetRegisterClass &SReg_64_XEXEC_XNULLRegClass = AMDGPUMCRegisterClassStorage.Classes[61]; |
| 112 | static constexpr const TargetRegisterClass &AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[62]; |
| 113 | static constexpr const TargetRegisterClass &SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[63]; |
| 114 | static constexpr const TargetRegisterClass &CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[64]; |
| 115 | static constexpr const TargetRegisterClass &Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[65]; |
| 116 | static constexpr const TargetRegisterClass &TTMP_64RegClass = AMDGPUMCRegisterClassStorage.Classes[66]; |
| 117 | static constexpr const TargetRegisterClass &APERTURE_ClassRegClass = AMDGPUMCRegisterClassStorage.Classes[67]; |
| 118 | static constexpr const TargetRegisterClass &AV_96RegClass = AMDGPUMCRegisterClassStorage.Classes[68]; |
| 119 | static constexpr const TargetRegisterClass &VReg_96RegClass = AMDGPUMCRegisterClassStorage.Classes[69]; |
| 120 | static constexpr const TargetRegisterClass &AV_96_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[70]; |
| 121 | static constexpr const TargetRegisterClass &AV_96_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[71]; |
| 122 | static constexpr const TargetRegisterClass &AV_96_with_sub1_sub2_in_VReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[72]; |
| 123 | static constexpr const TargetRegisterClass &VReg_96_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[73]; |
| 124 | static constexpr const TargetRegisterClass &AV_96_with_sub0_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[74]; |
| 125 | static constexpr const TargetRegisterClass &AV_96_with_sub1_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[75]; |
| 126 | static constexpr const TargetRegisterClass &AReg_96RegClass = AMDGPUMCRegisterClassStorage.Classes[76]; |
| 127 | static constexpr const TargetRegisterClass &AV_96_with_sub2_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[77]; |
| 128 | static constexpr const TargetRegisterClass &AV_96_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[78]; |
| 129 | static constexpr const TargetRegisterClass &AV_96_with_sub0_in_VGPR_32_Lo256_and_AV_96_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[79]; |
| 130 | static constexpr const TargetRegisterClass &AV_96_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[80]; |
| 131 | static constexpr const TargetRegisterClass &AReg_96_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[81]; |
| 132 | static constexpr const TargetRegisterClass &AReg_96_with_sub1_sub2_in_AReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[82]; |
| 133 | static constexpr const TargetRegisterClass &AV_96_with_sub1_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[83]; |
| 134 | static constexpr const TargetRegisterClass &AV_96_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[84]; |
| 135 | static constexpr const TargetRegisterClass &VReg_96_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[85]; |
| 136 | static constexpr const TargetRegisterClass &AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[86]; |
| 137 | static constexpr const TargetRegisterClass &AV_96_with_hi16_in_VGPR_16_Lo128_and_AV_96_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[87]; |
| 138 | static constexpr const TargetRegisterClass &AV_96_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[88]; |
| 139 | static constexpr const TargetRegisterClass &AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[89]; |
| 140 | static constexpr const TargetRegisterClass &AV_96_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[90]; |
| 141 | static constexpr const TargetRegisterClass &SReg_96RegClass = AMDGPUMCRegisterClassStorage.Classes[91]; |
| 142 | static constexpr const TargetRegisterClass &SGPR_96RegClass = AMDGPUMCRegisterClassStorage.Classes[92]; |
| 143 | static constexpr const TargetRegisterClass &SGPR_96_with_sub0_sub1_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[93]; |
| 144 | static constexpr const TargetRegisterClass &SGPR_96_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[94]; |
| 145 | static constexpr const TargetRegisterClass &TTMP_96RegClass = AMDGPUMCRegisterClassStorage.Classes[95]; |
| 146 | static constexpr const TargetRegisterClass &AV_128RegClass = AMDGPUMCRegisterClassStorage.Classes[96]; |
| 147 | static constexpr const TargetRegisterClass &VS_128RegClass = AMDGPUMCRegisterClassStorage.Classes[97]; |
| 148 | static constexpr const TargetRegisterClass &VS_128_with_hi16RegClass = AMDGPUMCRegisterClassStorage.Classes[98]; |
| 149 | static constexpr const TargetRegisterClass &VReg_128RegClass = AMDGPUMCRegisterClassStorage.Classes[99]; |
| 150 | static constexpr const TargetRegisterClass &AV_128_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[100]; |
| 151 | static constexpr const TargetRegisterClass &AV_128_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[101]; |
| 152 | static constexpr const TargetRegisterClass &VS_128_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[102]; |
| 153 | static constexpr const TargetRegisterClass &VS_128_Align2_with_hi16RegClass = AMDGPUMCRegisterClassStorage.Classes[103]; |
| 154 | static constexpr const TargetRegisterClass &VReg_128_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[104]; |
| 155 | static constexpr const TargetRegisterClass &AV_128_with_sub1_sub2_in_VReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[105]; |
| 156 | static constexpr const TargetRegisterClass &VS_128_with_hi16_with_sub0_in_VS_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[106]; |
| 157 | static constexpr const TargetRegisterClass &VS_128_with_hi16_with_sub1_in_VS_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[107]; |
| 158 | static constexpr const TargetRegisterClass &VS_128_with_hi16_with_sub2_in_VS_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[108]; |
| 159 | static constexpr const TargetRegisterClass &VS_128_with_hi16_with_sub3_in_VS_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[109]; |
| 160 | static constexpr const TargetRegisterClass &AV_128_with_sub0_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[110]; |
| 161 | static constexpr const TargetRegisterClass &AV_128_with_sub1_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[111]; |
| 162 | static constexpr const TargetRegisterClass &AV_128_with_sub2_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[112]; |
| 163 | static constexpr const TargetRegisterClass &AReg_128RegClass = AMDGPUMCRegisterClassStorage.Classes[113]; |
| 164 | static constexpr const TargetRegisterClass &AV_128_with_sub3_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[114]; |
| 165 | static constexpr const TargetRegisterClass &VS_128_with_hi16_with_sub0_in_VS_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[115]; |
| 166 | static constexpr const TargetRegisterClass &VS_128_with_hi16_with_sub0_sub1_in_VS_64_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[116]; |
| 167 | static constexpr const TargetRegisterClass &VS_128_with_hi16_with_sub1_in_VS_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[117]; |
| 168 | static constexpr const TargetRegisterClass &VS_128_with_hi16_with_sub2_sub3_in_VS_64_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[118]; |
| 169 | static constexpr const TargetRegisterClass &VS_128_with_hi16_with_sub2_in_VS_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[119]; |
| 170 | static constexpr const TargetRegisterClass &VS_128_with_hi16_with_sub3_in_VS_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[120]; |
| 171 | static constexpr const TargetRegisterClass &AV_128_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[121]; |
| 172 | static constexpr const TargetRegisterClass &AV_128_with_sub0_in_VGPR_32_Lo256_and_AV_128_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[122]; |
| 173 | static constexpr const TargetRegisterClass &AV_128_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[123]; |
| 174 | static constexpr const TargetRegisterClass &AReg_128_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[124]; |
| 175 | static constexpr const TargetRegisterClass &AV_128_with_sub1_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[125]; |
| 176 | static constexpr const TargetRegisterClass &AV_128_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[126]; |
| 177 | static constexpr const TargetRegisterClass &VReg_128_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[127]; |
| 178 | static constexpr const TargetRegisterClass &AReg_128_with_sub1_sub2_in_AReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[128]; |
| 179 | static constexpr const TargetRegisterClass &AV_128_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[129]; |
| 180 | static constexpr const TargetRegisterClass &AV_128_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[130]; |
| 181 | static constexpr const TargetRegisterClass &AV_128_with_sub3_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[131]; |
| 182 | static constexpr const TargetRegisterClass &VS_128_with_hi16_with_sub0_sub1_in_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[132]; |
| 183 | static constexpr const TargetRegisterClass &VS_128_with_hi16_with_sub2_sub3_in_VS_64_Align2_and_VS_64_with_sub0_in_VS_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[133]; |
| 184 | static constexpr const TargetRegisterClass &AV_128_with_hi16_in_VGPR_16_Lo128_and_AV_128_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[134]; |
| 185 | static constexpr const TargetRegisterClass &AV_128_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[135]; |
| 186 | static constexpr const TargetRegisterClass &AV_128_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[136]; |
| 187 | static constexpr const TargetRegisterClass &AV_128_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[137]; |
| 188 | static constexpr const TargetRegisterClass &AV_128_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[138]; |
| 189 | static constexpr const TargetRegisterClass &SReg_128RegClass = AMDGPUMCRegisterClassStorage.Classes[139]; |
| 190 | static constexpr const TargetRegisterClass &SReg_128_XNULLRegClass = AMDGPUMCRegisterClassStorage.Classes[140]; |
| 191 | static constexpr const TargetRegisterClass &SGPR_128RegClass = AMDGPUMCRegisterClassStorage.Classes[141]; |
| 192 | static constexpr const TargetRegisterClass &SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[142]; |
| 193 | static constexpr const TargetRegisterClass &SGPR_128_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[143]; |
| 194 | static constexpr const TargetRegisterClass &SGPR_128_with_sub2_sub3_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[144]; |
| 195 | static constexpr const TargetRegisterClass &TTMP_128RegClass = AMDGPUMCRegisterClassStorage.Classes[145]; |
| 196 | static constexpr const TargetRegisterClass &Pseudo_SReg_128RegClass = AMDGPUMCRegisterClassStorage.Classes[146]; |
| 197 | static constexpr const TargetRegisterClass &AV_160RegClass = AMDGPUMCRegisterClassStorage.Classes[147]; |
| 198 | static constexpr const TargetRegisterClass &VReg_160RegClass = AMDGPUMCRegisterClassStorage.Classes[148]; |
| 199 | static constexpr const TargetRegisterClass &AV_160_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[149]; |
| 200 | static constexpr const TargetRegisterClass &AV_160_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[150]; |
| 201 | static constexpr const TargetRegisterClass &AV_160_with_sub1_sub2_in_VReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[151]; |
| 202 | static constexpr const TargetRegisterClass &VReg_160_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[152]; |
| 203 | static constexpr const TargetRegisterClass &AV_160_with_sub0_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[153]; |
| 204 | static constexpr const TargetRegisterClass &AV_160_with_sub1_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[154]; |
| 205 | static constexpr const TargetRegisterClass &AV_160_with_sub2_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[155]; |
| 206 | static constexpr const TargetRegisterClass &AV_160_with_sub3_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[156]; |
| 207 | static constexpr const TargetRegisterClass &AReg_160RegClass = AMDGPUMCRegisterClassStorage.Classes[157]; |
| 208 | static constexpr const TargetRegisterClass &AV_160_with_sub4_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[158]; |
| 209 | static constexpr const TargetRegisterClass &AV_160_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[159]; |
| 210 | static constexpr const TargetRegisterClass &AV_160_with_sub0_in_VGPR_32_Lo256_and_AV_160_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[160]; |
| 211 | static constexpr const TargetRegisterClass &AV_160_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[161]; |
| 212 | static constexpr const TargetRegisterClass &AV_160_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[162]; |
| 213 | static constexpr const TargetRegisterClass &AV_160_with_sub1_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[163]; |
| 214 | static constexpr const TargetRegisterClass &AV_160_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[164]; |
| 215 | static constexpr const TargetRegisterClass &AReg_160_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[165]; |
| 216 | static constexpr const TargetRegisterClass &AReg_160_with_sub1_sub2_in_AReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[166]; |
| 217 | static constexpr const TargetRegisterClass &AV_160_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[167]; |
| 218 | static constexpr const TargetRegisterClass &AV_160_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[168]; |
| 219 | static constexpr const TargetRegisterClass &VReg_160_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[169]; |
| 220 | static constexpr const TargetRegisterClass &AV_160_with_sub3_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[170]; |
| 221 | static constexpr const TargetRegisterClass &AV_160_with_sub4_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[171]; |
| 222 | static constexpr const TargetRegisterClass &AV_160_with_hi16_in_VGPR_16_Lo128_and_AV_160_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[172]; |
| 223 | static constexpr const TargetRegisterClass &AV_160_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[173]; |
| 224 | static constexpr const TargetRegisterClass &AV_160_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[174]; |
| 225 | static constexpr const TargetRegisterClass &AV_160_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[175]; |
| 226 | static constexpr const TargetRegisterClass &AV_160_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[176]; |
| 227 | static constexpr const TargetRegisterClass &AV_160_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[177]; |
| 228 | static constexpr const TargetRegisterClass &SReg_160RegClass = AMDGPUMCRegisterClassStorage.Classes[178]; |
| 229 | static constexpr const TargetRegisterClass &SGPR_160RegClass = AMDGPUMCRegisterClassStorage.Classes[179]; |
| 230 | static constexpr const TargetRegisterClass &SGPR_160_with_sub0_sub1_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[180]; |
| 231 | static constexpr const TargetRegisterClass &SGPR_160_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[181]; |
| 232 | static constexpr const TargetRegisterClass &SGPR_160_with_sub2_sub3_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[182]; |
| 233 | static constexpr const TargetRegisterClass &TTMP_160RegClass = AMDGPUMCRegisterClassStorage.Classes[183]; |
| 234 | static constexpr const TargetRegisterClass &AV_192RegClass = AMDGPUMCRegisterClassStorage.Classes[184]; |
| 235 | static constexpr const TargetRegisterClass &VReg_192RegClass = AMDGPUMCRegisterClassStorage.Classes[185]; |
| 236 | static constexpr const TargetRegisterClass &AV_192_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[186]; |
| 237 | static constexpr const TargetRegisterClass &AV_192_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[187]; |
| 238 | static constexpr const TargetRegisterClass &VReg_192_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[188]; |
| 239 | static constexpr const TargetRegisterClass &AV_192_with_sub1_sub2_in_VReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[189]; |
| 240 | static constexpr const TargetRegisterClass &AV_192_with_sub0_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[190]; |
| 241 | static constexpr const TargetRegisterClass &AV_192_with_sub1_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[191]; |
| 242 | static constexpr const TargetRegisterClass &AV_192_with_sub2_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[192]; |
| 243 | static constexpr const TargetRegisterClass &AV_192_with_sub3_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[193]; |
| 244 | static constexpr const TargetRegisterClass &AV_192_with_sub4_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[194]; |
| 245 | static constexpr const TargetRegisterClass &AReg_192RegClass = AMDGPUMCRegisterClassStorage.Classes[195]; |
| 246 | static constexpr const TargetRegisterClass &AV_192_with_sub5_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[196]; |
| 247 | static constexpr const TargetRegisterClass &AV_192_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[197]; |
| 248 | static constexpr const TargetRegisterClass &AV_192_with_sub0_in_VGPR_32_Lo256_and_AV_192_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[198]; |
| 249 | static constexpr const TargetRegisterClass &AV_192_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[199]; |
| 250 | static constexpr const TargetRegisterClass &AV_192_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[200]; |
| 251 | static constexpr const TargetRegisterClass &AV_192_with_sub1_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[201]; |
| 252 | static constexpr const TargetRegisterClass &AV_192_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[202]; |
| 253 | static constexpr const TargetRegisterClass &AReg_192_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[203]; |
| 254 | static constexpr const TargetRegisterClass &AV_192_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[204]; |
| 255 | static constexpr const TargetRegisterClass &AV_192_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[205]; |
| 256 | static constexpr const TargetRegisterClass &VReg_192_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[206]; |
| 257 | static constexpr const TargetRegisterClass &AReg_192_with_sub1_sub2_in_AReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[207]; |
| 258 | static constexpr const TargetRegisterClass &AV_192_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[208]; |
| 259 | static constexpr const TargetRegisterClass &AV_192_with_sub3_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[209]; |
| 260 | static constexpr const TargetRegisterClass &AV_192_with_sub4_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[210]; |
| 261 | static constexpr const TargetRegisterClass &AV_192_with_sub5_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[211]; |
| 262 | static constexpr const TargetRegisterClass &AV_192_with_hi16_in_VGPR_16_Lo128_and_AV_192_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[212]; |
| 263 | static constexpr const TargetRegisterClass &AV_192_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[213]; |
| 264 | static constexpr const TargetRegisterClass &AV_192_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[214]; |
| 265 | static constexpr const TargetRegisterClass &AV_192_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[215]; |
| 266 | static constexpr const TargetRegisterClass &AV_192_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[216]; |
| 267 | static constexpr const TargetRegisterClass &AV_192_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[217]; |
| 268 | static constexpr const TargetRegisterClass &AV_192_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[218]; |
| 269 | static constexpr const TargetRegisterClass &SReg_192RegClass = AMDGPUMCRegisterClassStorage.Classes[219]; |
| 270 | static constexpr const TargetRegisterClass &SGPR_192RegClass = AMDGPUMCRegisterClassStorage.Classes[220]; |
| 271 | static constexpr const TargetRegisterClass &SGPR_192_with_sub0_sub1_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[221]; |
| 272 | static constexpr const TargetRegisterClass &SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[222]; |
| 273 | static constexpr const TargetRegisterClass &SGPR_192_with_sub2_sub3_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[223]; |
| 274 | static constexpr const TargetRegisterClass &SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[224]; |
| 275 | static constexpr const TargetRegisterClass &SGPR_192_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_192_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[225]; |
| 276 | static constexpr const TargetRegisterClass &TTMP_192RegClass = AMDGPUMCRegisterClassStorage.Classes[226]; |
| 277 | static constexpr const TargetRegisterClass &AV_224RegClass = AMDGPUMCRegisterClassStorage.Classes[227]; |
| 278 | static constexpr const TargetRegisterClass &VReg_224RegClass = AMDGPUMCRegisterClassStorage.Classes[228]; |
| 279 | static constexpr const TargetRegisterClass &AV_224_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[229]; |
| 280 | static constexpr const TargetRegisterClass &AV_224_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[230]; |
| 281 | static constexpr const TargetRegisterClass &AV_224_with_sub1_sub2_in_VReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[231]; |
| 282 | static constexpr const TargetRegisterClass &VReg_224_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[232]; |
| 283 | static constexpr const TargetRegisterClass &AV_224_with_sub0_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[233]; |
| 284 | static constexpr const TargetRegisterClass &AV_224_with_sub1_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[234]; |
| 285 | static constexpr const TargetRegisterClass &AV_224_with_sub2_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[235]; |
| 286 | static constexpr const TargetRegisterClass &AV_224_with_sub3_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[236]; |
| 287 | static constexpr const TargetRegisterClass &AV_224_with_sub4_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[237]; |
| 288 | static constexpr const TargetRegisterClass &AV_224_with_sub5_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[238]; |
| 289 | static constexpr const TargetRegisterClass &AReg_224RegClass = AMDGPUMCRegisterClassStorage.Classes[239]; |
| 290 | static constexpr const TargetRegisterClass &AV_224_with_sub6_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[240]; |
| 291 | static constexpr const TargetRegisterClass &AV_224_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[241]; |
| 292 | static constexpr const TargetRegisterClass &AV_224_with_sub0_in_VGPR_32_Lo256_and_AV_224_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[242]; |
| 293 | static constexpr const TargetRegisterClass &AV_224_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[243]; |
| 294 | static constexpr const TargetRegisterClass &AV_224_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[244]; |
| 295 | static constexpr const TargetRegisterClass &AV_224_with_sub1_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[245]; |
| 296 | static constexpr const TargetRegisterClass &AV_224_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[246]; |
| 297 | static constexpr const TargetRegisterClass &AV_224_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[247]; |
| 298 | static constexpr const TargetRegisterClass &AV_224_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[248]; |
| 299 | static constexpr const TargetRegisterClass &AV_224_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[249]; |
| 300 | static constexpr const TargetRegisterClass &AReg_224_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[250]; |
| 301 | static constexpr const TargetRegisterClass &AReg_224_with_sub1_sub2_in_AReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[251]; |
| 302 | static constexpr const TargetRegisterClass &AV_224_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[252]; |
| 303 | static constexpr const TargetRegisterClass &AV_224_with_sub3_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[253]; |
| 304 | static constexpr const TargetRegisterClass &VReg_224_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[254]; |
| 305 | static constexpr const TargetRegisterClass &AV_224_with_sub4_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[255]; |
| 306 | static constexpr const TargetRegisterClass &AV_224_with_sub5_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[256]; |
| 307 | static constexpr const TargetRegisterClass &AV_224_with_sub6_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[257]; |
| 308 | static constexpr const TargetRegisterClass &AV_224_with_hi16_in_VGPR_16_Lo128_and_AV_224_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[258]; |
| 309 | static constexpr const TargetRegisterClass &AV_224_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[259]; |
| 310 | static constexpr const TargetRegisterClass &AV_224_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[260]; |
| 311 | static constexpr const TargetRegisterClass &AV_224_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[261]; |
| 312 | static constexpr const TargetRegisterClass &AV_224_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[262]; |
| 313 | static constexpr const TargetRegisterClass &AV_224_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[263]; |
| 314 | static constexpr const TargetRegisterClass &AV_224_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[264]; |
| 315 | static constexpr const TargetRegisterClass &AV_224_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[265]; |
| 316 | static constexpr const TargetRegisterClass &SReg_224RegClass = AMDGPUMCRegisterClassStorage.Classes[266]; |
| 317 | static constexpr const TargetRegisterClass &SGPR_224RegClass = AMDGPUMCRegisterClassStorage.Classes[267]; |
| 318 | static constexpr const TargetRegisterClass &SGPR_224_with_sub0_sub1_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[268]; |
| 319 | static constexpr const TargetRegisterClass &SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[269]; |
| 320 | static constexpr const TargetRegisterClass &SGPR_224_with_sub2_sub3_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[270]; |
| 321 | static constexpr const TargetRegisterClass &SGPR_224_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[271]; |
| 322 | static constexpr const TargetRegisterClass &SGPR_224_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_224_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[272]; |
| 323 | static constexpr const TargetRegisterClass &TTMP_224RegClass = AMDGPUMCRegisterClassStorage.Classes[273]; |
| 324 | static constexpr const TargetRegisterClass &AV_256RegClass = AMDGPUMCRegisterClassStorage.Classes[274]; |
| 325 | static constexpr const TargetRegisterClass &VReg_256RegClass = AMDGPUMCRegisterClassStorage.Classes[275]; |
| 326 | static constexpr const TargetRegisterClass &AV_256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[276]; |
| 327 | static constexpr const TargetRegisterClass &AV_256_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[277]; |
| 328 | static constexpr const TargetRegisterClass &VReg_256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[278]; |
| 329 | static constexpr const TargetRegisterClass &AV_256_with_sub1_sub2_in_VReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[279]; |
| 330 | static constexpr const TargetRegisterClass &AV_256_with_sub0_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[280]; |
| 331 | static constexpr const TargetRegisterClass &AV_256_with_sub1_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[281]; |
| 332 | static constexpr const TargetRegisterClass &AV_256_with_sub2_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[282]; |
| 333 | static constexpr const TargetRegisterClass &AV_256_with_sub3_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[283]; |
| 334 | static constexpr const TargetRegisterClass &AV_256_with_sub4_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[284]; |
| 335 | static constexpr const TargetRegisterClass &AV_256_with_sub5_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[285]; |
| 336 | static constexpr const TargetRegisterClass &AV_256_with_sub6_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[286]; |
| 337 | static constexpr const TargetRegisterClass &AReg_256RegClass = AMDGPUMCRegisterClassStorage.Classes[287]; |
| 338 | static constexpr const TargetRegisterClass &AV_256_with_sub7_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[288]; |
| 339 | static constexpr const TargetRegisterClass &AV_256_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[289]; |
| 340 | static constexpr const TargetRegisterClass &AV_256_with_sub0_in_VGPR_32_Lo256_and_AV_256_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[290]; |
| 341 | static constexpr const TargetRegisterClass &AV_256_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[291]; |
| 342 | static constexpr const TargetRegisterClass &AV_256_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[292]; |
| 343 | static constexpr const TargetRegisterClass &AV_256_with_sub1_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[293]; |
| 344 | static constexpr const TargetRegisterClass &AV_256_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[294]; |
| 345 | static constexpr const TargetRegisterClass &AV_256_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[295]; |
| 346 | static constexpr const TargetRegisterClass &AV_256_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[296]; |
| 347 | static constexpr const TargetRegisterClass &AV_256_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[297]; |
| 348 | static constexpr const TargetRegisterClass &AReg_256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[298]; |
| 349 | static constexpr const TargetRegisterClass &AV_256_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[299]; |
| 350 | static constexpr const TargetRegisterClass &AV_256_with_sub3_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[300]; |
| 351 | static constexpr const TargetRegisterClass &VReg_256_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[301]; |
| 352 | static constexpr const TargetRegisterClass &AReg_256_with_sub1_sub2_in_AReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[302]; |
| 353 | static constexpr const TargetRegisterClass &AV_256_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[303]; |
| 354 | static constexpr const TargetRegisterClass &AV_256_with_sub4_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[304]; |
| 355 | static constexpr const TargetRegisterClass &AV_256_with_sub5_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[305]; |
| 356 | static constexpr const TargetRegisterClass &AV_256_with_sub6_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[306]; |
| 357 | static constexpr const TargetRegisterClass &AV_256_with_sub7_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[307]; |
| 358 | static constexpr const TargetRegisterClass &AV_256_with_hi16_in_VGPR_16_Lo128_and_AV_256_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[308]; |
| 359 | static constexpr const TargetRegisterClass &AV_256_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[309]; |
| 360 | static constexpr const TargetRegisterClass &AV_256_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[310]; |
| 361 | static constexpr const TargetRegisterClass &AV_256_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[311]; |
| 362 | static constexpr const TargetRegisterClass &AV_256_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[312]; |
| 363 | static constexpr const TargetRegisterClass &AV_256_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[313]; |
| 364 | static constexpr const TargetRegisterClass &AV_256_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[314]; |
| 365 | static constexpr const TargetRegisterClass &AV_256_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[315]; |
| 366 | static constexpr const TargetRegisterClass &AV_256_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[316]; |
| 367 | static constexpr const TargetRegisterClass &SReg_256RegClass = AMDGPUMCRegisterClassStorage.Classes[317]; |
| 368 | static constexpr const TargetRegisterClass &SReg_256_XNULLRegClass = AMDGPUMCRegisterClassStorage.Classes[318]; |
| 369 | static constexpr const TargetRegisterClass &SGPR_256RegClass = AMDGPUMCRegisterClassStorage.Classes[319]; |
| 370 | static constexpr const TargetRegisterClass &SGPR_256_with_sub0_sub1_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[320]; |
| 371 | static constexpr const TargetRegisterClass &SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[321]; |
| 372 | static constexpr const TargetRegisterClass &SGPR_256_with_sub2_sub3_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[322]; |
| 373 | static constexpr const TargetRegisterClass &SGPR_256_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[323]; |
| 374 | static constexpr const TargetRegisterClass &SGPR_256_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_256_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[324]; |
| 375 | static constexpr const TargetRegisterClass &SGPR_256_with_sub6_sub7_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[325]; |
| 376 | static constexpr const TargetRegisterClass &TTMP_256RegClass = AMDGPUMCRegisterClassStorage.Classes[326]; |
| 377 | static constexpr const TargetRegisterClass &AV_288RegClass = AMDGPUMCRegisterClassStorage.Classes[327]; |
| 378 | static constexpr const TargetRegisterClass &VReg_288RegClass = AMDGPUMCRegisterClassStorage.Classes[328]; |
| 379 | static constexpr const TargetRegisterClass &AV_288_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[329]; |
| 380 | static constexpr const TargetRegisterClass &AV_288_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[330]; |
| 381 | static constexpr const TargetRegisterClass &AV_288_with_sub1_sub2_in_VReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[331]; |
| 382 | static constexpr const TargetRegisterClass &VReg_288_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[332]; |
| 383 | static constexpr const TargetRegisterClass &AV_288_with_sub0_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[333]; |
| 384 | static constexpr const TargetRegisterClass &AV_288_with_sub1_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[334]; |
| 385 | static constexpr const TargetRegisterClass &AV_288_with_sub2_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[335]; |
| 386 | static constexpr const TargetRegisterClass &AV_288_with_sub3_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[336]; |
| 387 | static constexpr const TargetRegisterClass &AV_288_with_sub4_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[337]; |
| 388 | static constexpr const TargetRegisterClass &AV_288_with_sub5_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[338]; |
| 389 | static constexpr const TargetRegisterClass &AV_288_with_sub6_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[339]; |
| 390 | static constexpr const TargetRegisterClass &AV_288_with_sub7_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[340]; |
| 391 | static constexpr const TargetRegisterClass &AReg_288RegClass = AMDGPUMCRegisterClassStorage.Classes[341]; |
| 392 | static constexpr const TargetRegisterClass &AV_288_with_sub8_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[342]; |
| 393 | static constexpr const TargetRegisterClass &AV_288_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[343]; |
| 394 | static constexpr const TargetRegisterClass &AV_288_with_sub0_in_VGPR_32_Lo256_and_AV_288_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[344]; |
| 395 | static constexpr const TargetRegisterClass &AV_288_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[345]; |
| 396 | static constexpr const TargetRegisterClass &AV_288_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[346]; |
| 397 | static constexpr const TargetRegisterClass &AV_288_with_sub1_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[347]; |
| 398 | static constexpr const TargetRegisterClass &AV_288_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[348]; |
| 399 | static constexpr const TargetRegisterClass &AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[349]; |
| 400 | static constexpr const TargetRegisterClass &AV_288_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[350]; |
| 401 | static constexpr const TargetRegisterClass &AV_288_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[351]; |
| 402 | static constexpr const TargetRegisterClass &AV_288_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[352]; |
| 403 | static constexpr const TargetRegisterClass &AV_288_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[353]; |
| 404 | static constexpr const TargetRegisterClass &AV_288_with_sub3_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[354]; |
| 405 | static constexpr const TargetRegisterClass &AReg_288_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[355]; |
| 406 | static constexpr const TargetRegisterClass &AReg_288_with_sub1_sub2_in_AReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[356]; |
| 407 | static constexpr const TargetRegisterClass &AV_288_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[357]; |
| 408 | static constexpr const TargetRegisterClass &AV_288_with_sub4_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[358]; |
| 409 | static constexpr const TargetRegisterClass &VReg_288_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[359]; |
| 410 | static constexpr const TargetRegisterClass &AV_288_with_sub5_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[360]; |
| 411 | static constexpr const TargetRegisterClass &AV_288_with_sub6_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[361]; |
| 412 | static constexpr const TargetRegisterClass &AV_288_with_sub7_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[362]; |
| 413 | static constexpr const TargetRegisterClass &AV_288_with_sub8_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[363]; |
| 414 | static constexpr const TargetRegisterClass &AV_288_with_hi16_in_VGPR_16_Lo128_and_AV_288_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[364]; |
| 415 | static constexpr const TargetRegisterClass &AV_288_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[365]; |
| 416 | static constexpr const TargetRegisterClass &AV_288_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[366]; |
| 417 | static constexpr const TargetRegisterClass &AV_288_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[367]; |
| 418 | static constexpr const TargetRegisterClass &AV_288_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[368]; |
| 419 | static constexpr const TargetRegisterClass &AV_288_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[369]; |
| 420 | static constexpr const TargetRegisterClass &AV_288_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[370]; |
| 421 | static constexpr const TargetRegisterClass &AV_288_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[371]; |
| 422 | static constexpr const TargetRegisterClass &AV_288_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[372]; |
| 423 | static constexpr const TargetRegisterClass &AV_288_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[373]; |
| 424 | static constexpr const TargetRegisterClass &SReg_288RegClass = AMDGPUMCRegisterClassStorage.Classes[374]; |
| 425 | static constexpr const TargetRegisterClass &SGPR_288RegClass = AMDGPUMCRegisterClassStorage.Classes[375]; |
| 426 | static constexpr const TargetRegisterClass &SGPR_288_with_sub0_sub1_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[376]; |
| 427 | static constexpr const TargetRegisterClass &SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[377]; |
| 428 | static constexpr const TargetRegisterClass &SGPR_288_with_sub2_sub3_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[378]; |
| 429 | static constexpr const TargetRegisterClass &SGPR_288_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[379]; |
| 430 | static constexpr const TargetRegisterClass &SGPR_288_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_288_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[380]; |
| 431 | static constexpr const TargetRegisterClass &SGPR_288_with_sub6_sub7_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[381]; |
| 432 | static constexpr const TargetRegisterClass &TTMP_288RegClass = AMDGPUMCRegisterClassStorage.Classes[382]; |
| 433 | static constexpr const TargetRegisterClass &AV_320RegClass = AMDGPUMCRegisterClassStorage.Classes[383]; |
| 434 | static constexpr const TargetRegisterClass &VReg_320RegClass = AMDGPUMCRegisterClassStorage.Classes[384]; |
| 435 | static constexpr const TargetRegisterClass &AV_320_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[385]; |
| 436 | static constexpr const TargetRegisterClass &AV_320_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[386]; |
| 437 | static constexpr const TargetRegisterClass &VReg_320_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[387]; |
| 438 | static constexpr const TargetRegisterClass &AV_320_with_sub1_sub2_in_VReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[388]; |
| 439 | static constexpr const TargetRegisterClass &AV_320_with_sub0_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[389]; |
| 440 | static constexpr const TargetRegisterClass &AV_320_with_sub1_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[390]; |
| 441 | static constexpr const TargetRegisterClass &AV_320_with_sub2_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[391]; |
| 442 | static constexpr const TargetRegisterClass &AV_320_with_sub3_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[392]; |
| 443 | static constexpr const TargetRegisterClass &AV_320_with_sub4_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[393]; |
| 444 | static constexpr const TargetRegisterClass &AV_320_with_sub5_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[394]; |
| 445 | static constexpr const TargetRegisterClass &AV_320_with_sub6_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[395]; |
| 446 | static constexpr const TargetRegisterClass &AV_320_with_sub7_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[396]; |
| 447 | static constexpr const TargetRegisterClass &AV_320_with_sub8_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[397]; |
| 448 | static constexpr const TargetRegisterClass &AReg_320RegClass = AMDGPUMCRegisterClassStorage.Classes[398]; |
| 449 | static constexpr const TargetRegisterClass &AV_320_with_sub9_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[399]; |
| 450 | static constexpr const TargetRegisterClass &AV_320_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[400]; |
| 451 | static constexpr const TargetRegisterClass &AV_320_with_sub0_in_VGPR_32_Lo256_and_AV_320_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[401]; |
| 452 | static constexpr const TargetRegisterClass &AV_320_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[402]; |
| 453 | static constexpr const TargetRegisterClass &AV_320_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[403]; |
| 454 | static constexpr const TargetRegisterClass &AV_320_with_sub1_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[404]; |
| 455 | static constexpr const TargetRegisterClass &AV_320_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[405]; |
| 456 | static constexpr const TargetRegisterClass &AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[406]; |
| 457 | static constexpr const TargetRegisterClass &AV_320_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[407]; |
| 458 | static constexpr const TargetRegisterClass &AV_320_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[408]; |
| 459 | static constexpr const TargetRegisterClass &AV_320_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[409]; |
| 460 | static constexpr const TargetRegisterClass &AV_320_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[410]; |
| 461 | static constexpr const TargetRegisterClass &AV_320_with_sub3_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[411]; |
| 462 | static constexpr const TargetRegisterClass &AReg_320_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[412]; |
| 463 | static constexpr const TargetRegisterClass &AV_320_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[413]; |
| 464 | static constexpr const TargetRegisterClass &AV_320_with_sub4_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[414]; |
| 465 | static constexpr const TargetRegisterClass &VReg_320_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[415]; |
| 466 | static constexpr const TargetRegisterClass &AReg_320_with_sub1_sub2_in_AReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[416]; |
| 467 | static constexpr const TargetRegisterClass &AV_320_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[417]; |
| 468 | static constexpr const TargetRegisterClass &AV_320_with_sub5_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[418]; |
| 469 | static constexpr const TargetRegisterClass &AV_320_with_sub6_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[419]; |
| 470 | static constexpr const TargetRegisterClass &AV_320_with_sub7_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[420]; |
| 471 | static constexpr const TargetRegisterClass &AV_320_with_sub8_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[421]; |
| 472 | static constexpr const TargetRegisterClass &AV_320_with_sub9_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[422]; |
| 473 | static constexpr const TargetRegisterClass &AV_320_with_hi16_in_VGPR_16_Lo128_and_AV_320_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[423]; |
| 474 | static constexpr const TargetRegisterClass &AV_320_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[424]; |
| 475 | static constexpr const TargetRegisterClass &AV_320_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[425]; |
| 476 | static constexpr const TargetRegisterClass &AV_320_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[426]; |
| 477 | static constexpr const TargetRegisterClass &AV_320_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[427]; |
| 478 | static constexpr const TargetRegisterClass &AV_320_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[428]; |
| 479 | static constexpr const TargetRegisterClass &AV_320_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[429]; |
| 480 | static constexpr const TargetRegisterClass &AV_320_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[430]; |
| 481 | static constexpr const TargetRegisterClass &AV_320_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[431]; |
| 482 | static constexpr const TargetRegisterClass &AV_320_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[432]; |
| 483 | static constexpr const TargetRegisterClass &AV_320_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[433]; |
| 484 | static constexpr const TargetRegisterClass &SReg_320RegClass = AMDGPUMCRegisterClassStorage.Classes[434]; |
| 485 | static constexpr const TargetRegisterClass &SGPR_320RegClass = AMDGPUMCRegisterClassStorage.Classes[435]; |
| 486 | static constexpr const TargetRegisterClass &SGPR_320_with_sub0_sub1_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[436]; |
| 487 | static constexpr const TargetRegisterClass &SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[437]; |
| 488 | static constexpr const TargetRegisterClass &SGPR_320_with_sub2_sub3_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[438]; |
| 489 | static constexpr const TargetRegisterClass &SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[439]; |
| 490 | static constexpr const TargetRegisterClass &SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[440]; |
| 491 | static constexpr const TargetRegisterClass &SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[441]; |
| 492 | static constexpr const TargetRegisterClass &SGPR_320_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[442]; |
| 493 | static constexpr const TargetRegisterClass &SGPR_320_with_sub6_sub7_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[443]; |
| 494 | static constexpr const TargetRegisterClass &SGPR_320_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[444]; |
| 495 | static constexpr const TargetRegisterClass &TTMP_320RegClass = AMDGPUMCRegisterClassStorage.Classes[445]; |
| 496 | static constexpr const TargetRegisterClass &SGPR_320_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_320_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[446]; |
| 497 | static constexpr const TargetRegisterClass &AV_352RegClass = AMDGPUMCRegisterClassStorage.Classes[447]; |
| 498 | static constexpr const TargetRegisterClass &VReg_352RegClass = AMDGPUMCRegisterClassStorage.Classes[448]; |
| 499 | static constexpr const TargetRegisterClass &AV_352_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[449]; |
| 500 | static constexpr const TargetRegisterClass &AV_352_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[450]; |
| 501 | static constexpr const TargetRegisterClass &AV_352_with_sub1_sub2_in_VReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[451]; |
| 502 | static constexpr const TargetRegisterClass &VReg_352_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[452]; |
| 503 | static constexpr const TargetRegisterClass &AV_352_with_sub0_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[453]; |
| 504 | static constexpr const TargetRegisterClass &AV_352_with_sub1_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[454]; |
| 505 | static constexpr const TargetRegisterClass &AV_352_with_sub2_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[455]; |
| 506 | static constexpr const TargetRegisterClass &AV_352_with_sub3_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[456]; |
| 507 | static constexpr const TargetRegisterClass &AV_352_with_sub4_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[457]; |
| 508 | static constexpr const TargetRegisterClass &AV_352_with_sub5_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[458]; |
| 509 | static constexpr const TargetRegisterClass &AV_352_with_sub6_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[459]; |
| 510 | static constexpr const TargetRegisterClass &AV_352_with_sub7_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[460]; |
| 511 | static constexpr const TargetRegisterClass &AV_352_with_sub8_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[461]; |
| 512 | static constexpr const TargetRegisterClass &AV_352_with_sub9_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[462]; |
| 513 | static constexpr const TargetRegisterClass &AReg_352RegClass = AMDGPUMCRegisterClassStorage.Classes[463]; |
| 514 | static constexpr const TargetRegisterClass &AV_352_with_sub10_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[464]; |
| 515 | static constexpr const TargetRegisterClass &AV_352_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[465]; |
| 516 | static constexpr const TargetRegisterClass &AV_352_with_sub0_in_VGPR_32_Lo256_and_AV_352_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[466]; |
| 517 | static constexpr const TargetRegisterClass &AV_352_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[467]; |
| 518 | static constexpr const TargetRegisterClass &AV_352_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[468]; |
| 519 | static constexpr const TargetRegisterClass &AV_352_with_sub1_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[469]; |
| 520 | static constexpr const TargetRegisterClass &AV_352_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[470]; |
| 521 | static constexpr const TargetRegisterClass &AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[471]; |
| 522 | static constexpr const TargetRegisterClass &AV_352_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[472]; |
| 523 | static constexpr const TargetRegisterClass &AV_352_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[473]; |
| 524 | static constexpr const TargetRegisterClass &AV_352_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[474]; |
| 525 | static constexpr const TargetRegisterClass &AV_352_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[475]; |
| 526 | static constexpr const TargetRegisterClass &AV_352_with_sub3_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[476]; |
| 527 | static constexpr const TargetRegisterClass &AV_352_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[477]; |
| 528 | static constexpr const TargetRegisterClass &AV_352_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[478]; |
| 529 | static constexpr const TargetRegisterClass &AV_352_with_sub4_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[479]; |
| 530 | static constexpr const TargetRegisterClass &AReg_352_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[480]; |
| 531 | static constexpr const TargetRegisterClass &AReg_352_with_sub1_sub2_in_AReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[481]; |
| 532 | static constexpr const TargetRegisterClass &AV_352_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[482]; |
| 533 | static constexpr const TargetRegisterClass &AV_352_with_sub5_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[483]; |
| 534 | static constexpr const TargetRegisterClass &VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[484]; |
| 535 | static constexpr const TargetRegisterClass &AV_352_with_sub6_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[485]; |
| 536 | static constexpr const TargetRegisterClass &AV_352_with_sub7_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[486]; |
| 537 | static constexpr const TargetRegisterClass &AV_352_with_sub8_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[487]; |
| 538 | static constexpr const TargetRegisterClass &AV_352_with_sub9_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[488]; |
| 539 | static constexpr const TargetRegisterClass &AV_352_with_sub10_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[489]; |
| 540 | static constexpr const TargetRegisterClass &AV_352_with_hi16_in_VGPR_16_Lo128_and_AV_352_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[490]; |
| 541 | static constexpr const TargetRegisterClass &AV_352_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[491]; |
| 542 | static constexpr const TargetRegisterClass &AV_352_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[492]; |
| 543 | static constexpr const TargetRegisterClass &AV_352_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[493]; |
| 544 | static constexpr const TargetRegisterClass &AV_352_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[494]; |
| 545 | static constexpr const TargetRegisterClass &AV_352_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[495]; |
| 546 | static constexpr const TargetRegisterClass &AV_352_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[496]; |
| 547 | static constexpr const TargetRegisterClass &AV_352_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[497]; |
| 548 | static constexpr const TargetRegisterClass &AV_352_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[498]; |
| 549 | static constexpr const TargetRegisterClass &AV_352_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[499]; |
| 550 | static constexpr const TargetRegisterClass &AV_352_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[500]; |
| 551 | static constexpr const TargetRegisterClass &AV_352_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[501]; |
| 552 | static constexpr const TargetRegisterClass &SReg_352RegClass = AMDGPUMCRegisterClassStorage.Classes[502]; |
| 553 | static constexpr const TargetRegisterClass &SGPR_352RegClass = AMDGPUMCRegisterClassStorage.Classes[503]; |
| 554 | static constexpr const TargetRegisterClass &SGPR_352_with_sub0_sub1_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[504]; |
| 555 | static constexpr const TargetRegisterClass &SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[505]; |
| 556 | static constexpr const TargetRegisterClass &SGPR_352_with_sub2_sub3_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[506]; |
| 557 | static constexpr const TargetRegisterClass &SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[507]; |
| 558 | static constexpr const TargetRegisterClass &SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[508]; |
| 559 | static constexpr const TargetRegisterClass &SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[509]; |
| 560 | static constexpr const TargetRegisterClass &SGPR_352_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[510]; |
| 561 | static constexpr const TargetRegisterClass &SGPR_352_with_sub6_sub7_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[511]; |
| 562 | static constexpr const TargetRegisterClass &SGPR_352_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[512]; |
| 563 | static constexpr const TargetRegisterClass &TTMP_352RegClass = AMDGPUMCRegisterClassStorage.Classes[513]; |
| 564 | static constexpr const TargetRegisterClass &SGPR_352_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_352_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[514]; |
| 565 | static constexpr const TargetRegisterClass &AV_384RegClass = AMDGPUMCRegisterClassStorage.Classes[515]; |
| 566 | static constexpr const TargetRegisterClass &VReg_384RegClass = AMDGPUMCRegisterClassStorage.Classes[516]; |
| 567 | static constexpr const TargetRegisterClass &AV_384_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[517]; |
| 568 | static constexpr const TargetRegisterClass &AV_384_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[518]; |
| 569 | static constexpr const TargetRegisterClass &VReg_384_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[519]; |
| 570 | static constexpr const TargetRegisterClass &AV_384_with_sub1_sub2_in_VReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[520]; |
| 571 | static constexpr const TargetRegisterClass &AV_384_with_sub0_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[521]; |
| 572 | static constexpr const TargetRegisterClass &AV_384_with_sub1_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[522]; |
| 573 | static constexpr const TargetRegisterClass &AV_384_with_sub2_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[523]; |
| 574 | static constexpr const TargetRegisterClass &AV_384_with_sub3_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[524]; |
| 575 | static constexpr const TargetRegisterClass &AV_384_with_sub4_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[525]; |
| 576 | static constexpr const TargetRegisterClass &AV_384_with_sub5_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[526]; |
| 577 | static constexpr const TargetRegisterClass &AV_384_with_sub6_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[527]; |
| 578 | static constexpr const TargetRegisterClass &AV_384_with_sub7_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[528]; |
| 579 | static constexpr const TargetRegisterClass &AV_384_with_sub8_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[529]; |
| 580 | static constexpr const TargetRegisterClass &AV_384_with_sub9_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[530]; |
| 581 | static constexpr const TargetRegisterClass &AV_384_with_sub10_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[531]; |
| 582 | static constexpr const TargetRegisterClass &AReg_384RegClass = AMDGPUMCRegisterClassStorage.Classes[532]; |
| 583 | static constexpr const TargetRegisterClass &AV_384_with_sub11_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[533]; |
| 584 | static constexpr const TargetRegisterClass &AV_384_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[534]; |
| 585 | static constexpr const TargetRegisterClass &AV_384_with_sub0_in_VGPR_32_Lo256_and_AV_384_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[535]; |
| 586 | static constexpr const TargetRegisterClass &AV_384_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[536]; |
| 587 | static constexpr const TargetRegisterClass &AV_384_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[537]; |
| 588 | static constexpr const TargetRegisterClass &AV_384_with_sub1_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[538]; |
| 589 | static constexpr const TargetRegisterClass &AV_384_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[539]; |
| 590 | static constexpr const TargetRegisterClass &AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[540]; |
| 591 | static constexpr const TargetRegisterClass &AV_384_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[541]; |
| 592 | static constexpr const TargetRegisterClass &AV_384_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[542]; |
| 593 | static constexpr const TargetRegisterClass &AV_384_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[543]; |
| 594 | static constexpr const TargetRegisterClass &AV_384_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[544]; |
| 595 | static constexpr const TargetRegisterClass &AV_384_with_sub3_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[545]; |
| 596 | static constexpr const TargetRegisterClass &AV_384_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[546]; |
| 597 | static constexpr const TargetRegisterClass &AV_384_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[547]; |
| 598 | static constexpr const TargetRegisterClass &AV_384_with_sub4_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[548]; |
| 599 | static constexpr const TargetRegisterClass &AReg_384_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[549]; |
| 600 | static constexpr const TargetRegisterClass &AV_384_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[550]; |
| 601 | static constexpr const TargetRegisterClass &AV_384_with_sub5_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[551]; |
| 602 | static constexpr const TargetRegisterClass &VReg_384_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[552]; |
| 603 | static constexpr const TargetRegisterClass &AReg_384_with_sub1_sub2_in_AReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[553]; |
| 604 | static constexpr const TargetRegisterClass &AV_384_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[554]; |
| 605 | static constexpr const TargetRegisterClass &AV_384_with_sub6_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[555]; |
| 606 | static constexpr const TargetRegisterClass &AV_384_with_sub7_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[556]; |
| 607 | static constexpr const TargetRegisterClass &AV_384_with_sub8_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[557]; |
| 608 | static constexpr const TargetRegisterClass &AV_384_with_sub9_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[558]; |
| 609 | static constexpr const TargetRegisterClass &AV_384_with_sub10_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[559]; |
| 610 | static constexpr const TargetRegisterClass &AV_384_with_sub11_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[560]; |
| 611 | static constexpr const TargetRegisterClass &AV_384_with_hi16_in_VGPR_16_Lo128_and_AV_384_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[561]; |
| 612 | static constexpr const TargetRegisterClass &AV_384_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[562]; |
| 613 | static constexpr const TargetRegisterClass &AV_384_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[563]; |
| 614 | static constexpr const TargetRegisterClass &AV_384_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[564]; |
| 615 | static constexpr const TargetRegisterClass &AV_384_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[565]; |
| 616 | static constexpr const TargetRegisterClass &AV_384_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[566]; |
| 617 | static constexpr const TargetRegisterClass &AV_384_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[567]; |
| 618 | static constexpr const TargetRegisterClass &AV_384_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[568]; |
| 619 | static constexpr const TargetRegisterClass &AV_384_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[569]; |
| 620 | static constexpr const TargetRegisterClass &AV_384_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[570]; |
| 621 | static constexpr const TargetRegisterClass &AV_384_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[571]; |
| 622 | static constexpr const TargetRegisterClass &AV_384_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[572]; |
| 623 | static constexpr const TargetRegisterClass &AV_384_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[573]; |
| 624 | static constexpr const TargetRegisterClass &SReg_384RegClass = AMDGPUMCRegisterClassStorage.Classes[574]; |
| 625 | static constexpr const TargetRegisterClass &SGPR_384RegClass = AMDGPUMCRegisterClassStorage.Classes[575]; |
| 626 | static constexpr const TargetRegisterClass &SGPR_384_with_sub0_sub1_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[576]; |
| 627 | static constexpr const TargetRegisterClass &SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[577]; |
| 628 | static constexpr const TargetRegisterClass &SGPR_384_with_sub2_sub3_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[578]; |
| 629 | static constexpr const TargetRegisterClass &SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[579]; |
| 630 | static constexpr const TargetRegisterClass &SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[580]; |
| 631 | static constexpr const TargetRegisterClass &SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[581]; |
| 632 | static constexpr const TargetRegisterClass &SGPR_384_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[582]; |
| 633 | static constexpr const TargetRegisterClass &SGPR_384_with_sub6_sub7_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[583]; |
| 634 | static constexpr const TargetRegisterClass &SGPR_384_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[584]; |
| 635 | static constexpr const TargetRegisterClass &SGPR_384_with_sub10_sub11_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[585]; |
| 636 | static constexpr const TargetRegisterClass &TTMP_384RegClass = AMDGPUMCRegisterClassStorage.Classes[586]; |
| 637 | static constexpr const TargetRegisterClass &SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[587]; |
| 638 | static constexpr const TargetRegisterClass &AV_512RegClass = AMDGPUMCRegisterClassStorage.Classes[588]; |
| 639 | static constexpr const TargetRegisterClass &VReg_512RegClass = AMDGPUMCRegisterClassStorage.Classes[589]; |
| 640 | static constexpr const TargetRegisterClass &AV_512_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[590]; |
| 641 | static constexpr const TargetRegisterClass &AV_512_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[591]; |
| 642 | static constexpr const TargetRegisterClass &VReg_512_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[592]; |
| 643 | static constexpr const TargetRegisterClass &AV_512_with_sub1_sub2_in_VReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[593]; |
| 644 | static constexpr const TargetRegisterClass &AV_512_with_sub0_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[594]; |
| 645 | static constexpr const TargetRegisterClass &AV_512_with_sub1_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[595]; |
| 646 | static constexpr const TargetRegisterClass &AV_512_with_sub2_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[596]; |
| 647 | static constexpr const TargetRegisterClass &AV_512_with_sub3_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[597]; |
| 648 | static constexpr const TargetRegisterClass &AV_512_with_sub4_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[598]; |
| 649 | static constexpr const TargetRegisterClass &AV_512_with_sub5_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[599]; |
| 650 | static constexpr const TargetRegisterClass &AV_512_with_sub6_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[600]; |
| 651 | static constexpr const TargetRegisterClass &AV_512_with_sub7_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[601]; |
| 652 | static constexpr const TargetRegisterClass &AV_512_with_sub8_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[602]; |
| 653 | static constexpr const TargetRegisterClass &AV_512_with_sub9_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[603]; |
| 654 | static constexpr const TargetRegisterClass &AV_512_with_sub10_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[604]; |
| 655 | static constexpr const TargetRegisterClass &AV_512_with_sub11_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[605]; |
| 656 | static constexpr const TargetRegisterClass &AV_512_with_sub12_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[606]; |
| 657 | static constexpr const TargetRegisterClass &AV_512_with_sub13_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[607]; |
| 658 | static constexpr const TargetRegisterClass &AV_512_with_sub14_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[608]; |
| 659 | static constexpr const TargetRegisterClass &AReg_512RegClass = AMDGPUMCRegisterClassStorage.Classes[609]; |
| 660 | static constexpr const TargetRegisterClass &AV_512_with_sub15_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[610]; |
| 661 | static constexpr const TargetRegisterClass &AV_512_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[611]; |
| 662 | static constexpr const TargetRegisterClass &AV_512_with_sub0_in_VGPR_32_Lo256_and_AV_512_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[612]; |
| 663 | static constexpr const TargetRegisterClass &AV_512_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[613]; |
| 664 | static constexpr const TargetRegisterClass &AV_512_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[614]; |
| 665 | static constexpr const TargetRegisterClass &AV_512_with_sub1_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[615]; |
| 666 | static constexpr const TargetRegisterClass &AV_512_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[616]; |
| 667 | static constexpr const TargetRegisterClass &AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[617]; |
| 668 | static constexpr const TargetRegisterClass &AV_512_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[618]; |
| 669 | static constexpr const TargetRegisterClass &AV_512_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[619]; |
| 670 | static constexpr const TargetRegisterClass &AV_512_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[620]; |
| 671 | static constexpr const TargetRegisterClass &AV_512_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[621]; |
| 672 | static constexpr const TargetRegisterClass &AV_512_with_sub3_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[622]; |
| 673 | static constexpr const TargetRegisterClass &AV_512_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[623]; |
| 674 | static constexpr const TargetRegisterClass &AV_512_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[624]; |
| 675 | static constexpr const TargetRegisterClass &AV_512_with_sub4_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[625]; |
| 676 | static constexpr const TargetRegisterClass &AV_512_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_384_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[626]; |
| 677 | static constexpr const TargetRegisterClass &AV_512_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[627]; |
| 678 | static constexpr const TargetRegisterClass &AV_512_with_sub5_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[628]; |
| 679 | static constexpr const TargetRegisterClass &AV_512_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[629]; |
| 680 | static constexpr const TargetRegisterClass &AV_512_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_VReg_320_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[630]; |
| 681 | static constexpr const TargetRegisterClass &AV_512_with_sub6_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[631]; |
| 682 | static constexpr const TargetRegisterClass &AReg_512_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[632]; |
| 683 | static constexpr const TargetRegisterClass &AV_512_with_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_VReg_288_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[633]; |
| 684 | static constexpr const TargetRegisterClass &AV_512_with_sub7_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[634]; |
| 685 | static constexpr const TargetRegisterClass &VReg_512_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[635]; |
| 686 | static constexpr const TargetRegisterClass &AReg_512_with_sub1_sub2_in_AReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[636]; |
| 687 | static constexpr const TargetRegisterClass &AV_512_with_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[637]; |
| 688 | static constexpr const TargetRegisterClass &AV_512_with_sub8_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[638]; |
| 689 | static constexpr const TargetRegisterClass &AV_512_with_sub9_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[639]; |
| 690 | static constexpr const TargetRegisterClass &AV_512_with_sub10_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[640]; |
| 691 | static constexpr const TargetRegisterClass &AV_512_with_sub11_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[641]; |
| 692 | static constexpr const TargetRegisterClass &AV_512_with_sub12_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[642]; |
| 693 | static constexpr const TargetRegisterClass &AV_512_with_sub13_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[643]; |
| 694 | static constexpr const TargetRegisterClass &AV_512_with_sub14_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[644]; |
| 695 | static constexpr const TargetRegisterClass &AV_512_with_sub15_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[645]; |
| 696 | static constexpr const TargetRegisterClass &AV_512_with_hi16_in_VGPR_16_Lo128_and_AV_512_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[646]; |
| 697 | static constexpr const TargetRegisterClass &AV_512_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[647]; |
| 698 | static constexpr const TargetRegisterClass &AV_512_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[648]; |
| 699 | static constexpr const TargetRegisterClass &AV_512_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[649]; |
| 700 | static constexpr const TargetRegisterClass &AV_512_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[650]; |
| 701 | static constexpr const TargetRegisterClass &AV_512_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[651]; |
| 702 | static constexpr const TargetRegisterClass &AV_512_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[652]; |
| 703 | static constexpr const TargetRegisterClass &AV_512_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[653]; |
| 704 | static constexpr const TargetRegisterClass &AV_512_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[654]; |
| 705 | static constexpr const TargetRegisterClass &AV_512_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[655]; |
| 706 | static constexpr const TargetRegisterClass &AV_512_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[656]; |
| 707 | static constexpr const TargetRegisterClass &AV_512_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[657]; |
| 708 | static constexpr const TargetRegisterClass &AV_512_with_sub10_sub11_sub12_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[658]; |
| 709 | static constexpr const TargetRegisterClass &AV_512_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[659]; |
| 710 | static constexpr const TargetRegisterClass &AV_512_with_sub11_sub12_sub13_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[660]; |
| 711 | static constexpr const TargetRegisterClass &AV_512_with_sub12_sub13_sub14_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[661]; |
| 712 | static constexpr const TargetRegisterClass &AV_512_with_sub13_sub14_sub15_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[662]; |
| 713 | static constexpr const TargetRegisterClass &SReg_512RegClass = AMDGPUMCRegisterClassStorage.Classes[663]; |
| 714 | static constexpr const TargetRegisterClass &SGPR_512RegClass = AMDGPUMCRegisterClassStorage.Classes[664]; |
| 715 | static constexpr const TargetRegisterClass &SGPR_512_with_sub0_sub1_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[665]; |
| 716 | static constexpr const TargetRegisterClass &SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[666]; |
| 717 | static constexpr const TargetRegisterClass &SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[667]; |
| 718 | static constexpr const TargetRegisterClass &SGPR_512_with_sub2_sub3_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[668]; |
| 719 | static constexpr const TargetRegisterClass &SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[669]; |
| 720 | static constexpr const TargetRegisterClass &SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[670]; |
| 721 | static constexpr const TargetRegisterClass &SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[671]; |
| 722 | static constexpr const TargetRegisterClass &SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[672]; |
| 723 | static constexpr const TargetRegisterClass &SGPR_512_with_sub6_sub7_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[673]; |
| 724 | static constexpr const TargetRegisterClass &SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[674]; |
| 725 | static constexpr const TargetRegisterClass &SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[675]; |
| 726 | static constexpr const TargetRegisterClass &SGPR_512_with_sub10_sub11_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[676]; |
| 727 | static constexpr const TargetRegisterClass &SGPR_512_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[677]; |
| 728 | static constexpr const TargetRegisterClass &SGPR_512_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[678]; |
| 729 | static constexpr const TargetRegisterClass &SGPR_512_with_sub14_sub15_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[679]; |
| 730 | static constexpr const TargetRegisterClass &SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[680]; |
| 731 | static constexpr const TargetRegisterClass &SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[681]; |
| 732 | static constexpr const TargetRegisterClass &SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[682]; |
| 733 | static constexpr const TargetRegisterClass &TTMP_512RegClass = AMDGPUMCRegisterClassStorage.Classes[683]; |
| 734 | static constexpr const TargetRegisterClass &AV_1024RegClass = AMDGPUMCRegisterClassStorage.Classes[684]; |
| 735 | static constexpr const TargetRegisterClass &VReg_1024RegClass = AMDGPUMCRegisterClassStorage.Classes[685]; |
| 736 | static constexpr const TargetRegisterClass &AV_1024_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[686]; |
| 737 | static constexpr const TargetRegisterClass &AV_1024_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[687]; |
| 738 | static constexpr const TargetRegisterClass &VReg_1024_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[688]; |
| 739 | static constexpr const TargetRegisterClass &AV_1024_with_sub1_sub2_in_VReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[689]; |
| 740 | static constexpr const TargetRegisterClass &AV_1024_with_sub0_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[690]; |
| 741 | static constexpr const TargetRegisterClass &AV_1024_with_sub1_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[691]; |
| 742 | static constexpr const TargetRegisterClass &AV_1024_with_sub2_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[692]; |
| 743 | static constexpr const TargetRegisterClass &AV_1024_with_sub3_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[693]; |
| 744 | static constexpr const TargetRegisterClass &AV_1024_with_sub4_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[694]; |
| 745 | static constexpr const TargetRegisterClass &AV_1024_with_sub5_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[695]; |
| 746 | static constexpr const TargetRegisterClass &AV_1024_with_sub6_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[696]; |
| 747 | static constexpr const TargetRegisterClass &AV_1024_with_sub7_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[697]; |
| 748 | static constexpr const TargetRegisterClass &AV_1024_with_sub8_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[698]; |
| 749 | static constexpr const TargetRegisterClass &AV_1024_with_sub9_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[699]; |
| 750 | static constexpr const TargetRegisterClass &AV_1024_with_sub10_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[700]; |
| 751 | static constexpr const TargetRegisterClass &AV_1024_with_sub11_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[701]; |
| 752 | static constexpr const TargetRegisterClass &AV_1024_with_sub12_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[702]; |
| 753 | static constexpr const TargetRegisterClass &AV_1024_with_sub13_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[703]; |
| 754 | static constexpr const TargetRegisterClass &AV_1024_with_sub14_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[704]; |
| 755 | static constexpr const TargetRegisterClass &AV_1024_with_sub15_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[705]; |
| 756 | static constexpr const TargetRegisterClass &AV_1024_with_sub16_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[706]; |
| 757 | static constexpr const TargetRegisterClass &AV_1024_with_sub17_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[707]; |
| 758 | static constexpr const TargetRegisterClass &AV_1024_with_sub18_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[708]; |
| 759 | static constexpr const TargetRegisterClass &AV_1024_with_sub19_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[709]; |
| 760 | static constexpr const TargetRegisterClass &AV_1024_with_sub20_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[710]; |
| 761 | static constexpr const TargetRegisterClass &AV_1024_with_sub21_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[711]; |
| 762 | static constexpr const TargetRegisterClass &AV_1024_with_sub22_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[712]; |
| 763 | static constexpr const TargetRegisterClass &AV_1024_with_sub23_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[713]; |
| 764 | static constexpr const TargetRegisterClass &AV_1024_with_sub24_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[714]; |
| 765 | static constexpr const TargetRegisterClass &AV_1024_with_sub25_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[715]; |
| 766 | static constexpr const TargetRegisterClass &AV_1024_with_sub26_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[716]; |
| 767 | static constexpr const TargetRegisterClass &AV_1024_with_sub27_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[717]; |
| 768 | static constexpr const TargetRegisterClass &AV_1024_with_sub28_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[718]; |
| 769 | static constexpr const TargetRegisterClass &AV_1024_with_sub29_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[719]; |
| 770 | static constexpr const TargetRegisterClass &AV_1024_with_sub30_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[720]; |
| 771 | static constexpr const TargetRegisterClass &AReg_1024RegClass = AMDGPUMCRegisterClassStorage.Classes[721]; |
| 772 | static constexpr const TargetRegisterClass &AV_1024_with_sub31_in_VGPR_32_Lo256RegClass = AMDGPUMCRegisterClassStorage.Classes[722]; |
| 773 | static constexpr const TargetRegisterClass &AV_1024_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[723]; |
| 774 | static constexpr const TargetRegisterClass &AV_1024_with_sub0_in_VGPR_32_Lo256_and_AV_1024_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[724]; |
| 775 | static constexpr const TargetRegisterClass &AV_1024_with_sub0_sub1_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[725]; |
| 776 | static constexpr const TargetRegisterClass &AV_1024_with_sub0_sub1_sub2_sub3_in_VReg_128_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[726]; |
| 777 | static constexpr const TargetRegisterClass &AV_1024_with_sub1_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[727]; |
| 778 | static constexpr const TargetRegisterClass &AV_1024_with_sub1_sub2_in_VReg_64_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[728]; |
| 779 | static constexpr const TargetRegisterClass &AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_in_VReg_192_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[729]; |
| 780 | static constexpr const TargetRegisterClass &AV_1024_with_sub1_sub2_sub3_in_VReg_96_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[730]; |
| 781 | static constexpr const TargetRegisterClass &AV_1024_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[731]; |
| 782 | static constexpr const TargetRegisterClass &AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_in_VReg_256_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[732]; |
| 783 | static constexpr const TargetRegisterClass &AV_1024_with_sub1_sub2_sub3_sub4_sub5_in_VReg_160_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[733]; |
| 784 | static constexpr const TargetRegisterClass &AV_1024_with_sub3_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[734]; |
| 785 | static constexpr const TargetRegisterClass &AV_1024_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_320_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[735]; |
| 786 | static constexpr const TargetRegisterClass &AV_1024_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_in_VReg_224_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[736]; |
| 787 | static constexpr const TargetRegisterClass &AV_1024_with_sub4_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[737]; |
| 788 | static constexpr const TargetRegisterClass &AV_1024_with_lo16_hi16_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_384_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[738]; |
| 789 | static constexpr const TargetRegisterClass &AV_1024_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_in_VReg_288_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[739]; |
| 790 | static constexpr const TargetRegisterClass &AV_1024_with_sub5_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[740]; |
| 791 | static constexpr const TargetRegisterClass &AV_1024_with_sub1_lo16_sub1_hi16_sub2_lo16_sub2_hi16_sub3_lo16_sub3_hi16_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[741]; |
| 792 | static constexpr const TargetRegisterClass &AV_1024_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_VReg_320_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[742]; |
| 793 | static constexpr const TargetRegisterClass &AV_1024_with_sub6_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[743]; |
| 794 | static constexpr const TargetRegisterClass &AV_1024_with_sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_in_VReg_512_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[744]; |
| 795 | static constexpr const TargetRegisterClass &AV_1024_with_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_in_VReg_288_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[745]; |
| 796 | static constexpr const TargetRegisterClass &AV_1024_with_sub7_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[746]; |
| 797 | static constexpr const TargetRegisterClass &AV_1024_with_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[747]; |
| 798 | static constexpr const TargetRegisterClass &AV_1024_with_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[748]; |
| 799 | static constexpr const TargetRegisterClass &AV_1024_with_sub8_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[749]; |
| 800 | static constexpr const TargetRegisterClass &AV_1024_with_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[750]; |
| 801 | static constexpr const TargetRegisterClass &AV_1024_with_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[751]; |
| 802 | static constexpr const TargetRegisterClass &AV_1024_with_sub9_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[752]; |
| 803 | static constexpr const TargetRegisterClass &AV_1024_with_sub10_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[753]; |
| 804 | static constexpr const TargetRegisterClass &AV_1024_with_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[754]; |
| 805 | static constexpr const TargetRegisterClass &AV_1024_with_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[755]; |
| 806 | static constexpr const TargetRegisterClass &AV_1024_with_sub11_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[756]; |
| 807 | static constexpr const TargetRegisterClass &AV_1024_with_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[757]; |
| 808 | static constexpr const TargetRegisterClass &AV_1024_with_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[758]; |
| 809 | static constexpr const TargetRegisterClass &AV_1024_with_sub12_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[759]; |
| 810 | static constexpr const TargetRegisterClass &AV_1024_with_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[760]; |
| 811 | static constexpr const TargetRegisterClass &AV_1024_with_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[761]; |
| 812 | static constexpr const TargetRegisterClass &AV_1024_with_sub13_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[762]; |
| 813 | static constexpr const TargetRegisterClass &AV_1024_with_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[763]; |
| 814 | static constexpr const TargetRegisterClass &AV_1024_with_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[764]; |
| 815 | static constexpr const TargetRegisterClass &AV_1024_with_sub14_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[765]; |
| 816 | static constexpr const TargetRegisterClass &AV_1024_with_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[766]; |
| 817 | static constexpr const TargetRegisterClass &AV_1024_with_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[767]; |
| 818 | static constexpr const TargetRegisterClass &AReg_1024_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[768]; |
| 819 | static constexpr const TargetRegisterClass &AV_1024_with_sub15_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[769]; |
| 820 | static constexpr const TargetRegisterClass &AV_1024_with_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[770]; |
| 821 | static constexpr const TargetRegisterClass &VReg_1024_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[771]; |
| 822 | static constexpr const TargetRegisterClass &AReg_1024_with_sub1_sub2_in_AReg_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[772]; |
| 823 | static constexpr const TargetRegisterClass &AV_1024_with_sub16_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[773]; |
| 824 | static constexpr const TargetRegisterClass &AV_1024_with_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16_in_VReg_352_Lo256_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[774]; |
| 825 | static constexpr const TargetRegisterClass &AV_1024_with_sub17_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[775]; |
| 826 | static constexpr const TargetRegisterClass &AV_1024_with_sub18_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[776]; |
| 827 | static constexpr const TargetRegisterClass &AV_1024_with_sub19_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[777]; |
| 828 | static constexpr const TargetRegisterClass &AV_1024_with_sub20_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[778]; |
| 829 | static constexpr const TargetRegisterClass &AV_1024_with_sub21_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[779]; |
| 830 | static constexpr const TargetRegisterClass &AV_1024_with_sub22_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[780]; |
| 831 | static constexpr const TargetRegisterClass &AV_1024_with_sub23_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[781]; |
| 832 | static constexpr const TargetRegisterClass &AV_1024_with_sub24_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[782]; |
| 833 | static constexpr const TargetRegisterClass &AV_1024_with_sub25_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[783]; |
| 834 | static constexpr const TargetRegisterClass &AV_1024_with_sub26_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[784]; |
| 835 | static constexpr const TargetRegisterClass &AV_1024_with_sub27_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[785]; |
| 836 | static constexpr const TargetRegisterClass &AV_1024_with_sub28_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[786]; |
| 837 | static constexpr const TargetRegisterClass &AV_1024_with_sub29_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[787]; |
| 838 | static constexpr const TargetRegisterClass &AV_1024_with_sub30_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[788]; |
| 839 | static constexpr const TargetRegisterClass &AV_1024_with_sub31_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[789]; |
| 840 | static constexpr const TargetRegisterClass &AV_1024_with_hi16_in_VGPR_16_Lo128_and_AV_1024_with_sub1_sub2_in_AV_64_Align2RegClass = AMDGPUMCRegisterClassStorage.Classes[790]; |
| 841 | static constexpr const TargetRegisterClass &AV_1024_with_sub0_sub1_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[791]; |
| 842 | static constexpr const TargetRegisterClass &AV_1024_with_sub0_sub1_sub2_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[792]; |
| 843 | static constexpr const TargetRegisterClass &AV_1024_with_sub1_sub2_in_AV_64_Align2_and_AV_64_with_hi16_in_VGPR_16_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[793]; |
| 844 | static constexpr const TargetRegisterClass &AV_1024_with_sub1_sub2_sub3_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[794]; |
| 845 | static constexpr const TargetRegisterClass &AV_1024_with_sub2_sub3_sub4_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[795]; |
| 846 | static constexpr const TargetRegisterClass &AV_1024_with_sub3_sub4_sub5_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[796]; |
| 847 | static constexpr const TargetRegisterClass &AV_1024_with_sub4_sub5_sub6_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[797]; |
| 848 | static constexpr const TargetRegisterClass &AV_1024_with_sub5_sub6_sub7_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[798]; |
| 849 | static constexpr const TargetRegisterClass &AV_1024_with_sub6_sub7_sub8_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[799]; |
| 850 | static constexpr const TargetRegisterClass &AV_1024_with_sub7_sub8_sub9_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[800]; |
| 851 | static constexpr const TargetRegisterClass &AV_1024_with_sub8_sub9_sub10_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[801]; |
| 852 | static constexpr const TargetRegisterClass &AV_1024_with_sub10_sub11_sub12_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[802]; |
| 853 | static constexpr const TargetRegisterClass &AV_1024_with_sub9_sub10_sub11_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[803]; |
| 854 | static constexpr const TargetRegisterClass &AV_1024_with_sub11_sub12_sub13_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[804]; |
| 855 | static constexpr const TargetRegisterClass &AV_1024_with_sub12_sub13_sub14_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[805]; |
| 856 | static constexpr const TargetRegisterClass &AV_1024_with_sub13_sub14_sub15_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[806]; |
| 857 | static constexpr const TargetRegisterClass &AV_1024_with_sub14_sub15_sub16_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[807]; |
| 858 | static constexpr const TargetRegisterClass &AV_1024_with_sub15_sub16_sub17_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[808]; |
| 859 | static constexpr const TargetRegisterClass &AV_1024_with_sub16_sub17_sub18_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[809]; |
| 860 | static constexpr const TargetRegisterClass &AV_1024_with_sub17_sub18_sub19_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[810]; |
| 861 | static constexpr const TargetRegisterClass &AV_1024_with_sub18_sub19_sub20_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[811]; |
| 862 | static constexpr const TargetRegisterClass &AV_1024_with_sub19_sub20_sub21_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[812]; |
| 863 | static constexpr const TargetRegisterClass &AV_1024_with_sub20_sub21_sub22_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[813]; |
| 864 | static constexpr const TargetRegisterClass &AV_1024_with_sub21_sub22_sub23_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[814]; |
| 865 | static constexpr const TargetRegisterClass &AV_1024_with_sub22_sub23_sub24_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[815]; |
| 866 | static constexpr const TargetRegisterClass &AV_1024_with_sub23_sub24_sub25_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[816]; |
| 867 | static constexpr const TargetRegisterClass &AV_1024_with_sub24_sub25_sub26_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[817]; |
| 868 | static constexpr const TargetRegisterClass &AV_1024_with_sub25_sub26_sub27_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[818]; |
| 869 | static constexpr const TargetRegisterClass &AV_1024_with_sub26_sub27_sub28_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[819]; |
| 870 | static constexpr const TargetRegisterClass &AV_1024_with_sub27_sub28_sub29_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[820]; |
| 871 | static constexpr const TargetRegisterClass &AV_1024_with_sub28_sub29_sub30_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[821]; |
| 872 | static constexpr const TargetRegisterClass &AV_1024_with_sub29_sub30_sub31_in_AV_96_Align2_and_AV_96_with_sub2_in_VGPR_32_Lo128RegClass = AMDGPUMCRegisterClassStorage.Classes[822]; |
| 873 | static constexpr const TargetRegisterClass &SGPR_1024RegClass = AMDGPUMCRegisterClassStorage.Classes[823]; |
| 874 | static constexpr const TargetRegisterClass &SReg_1024RegClass = AMDGPUMCRegisterClassStorage.Classes[824]; |
| 875 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[825]; |
| 876 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[826]; |
| 877 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[827]; |
| 878 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[828]; |
| 879 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[829]; |
| 880 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[830]; |
| 881 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[831]; |
| 882 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[832]; |
| 883 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[833]; |
| 884 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[834]; |
| 885 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[835]; |
| 886 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[836]; |
| 887 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[837]; |
| 888 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[838]; |
| 889 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[839]; |
| 890 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[840]; |
| 891 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[841]; |
| 892 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[842]; |
| 893 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[843]; |
| 894 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[844]; |
| 895 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[845]; |
| 896 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub10_sub11_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[846]; |
| 897 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[847]; |
| 898 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[848]; |
| 899 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[849]; |
| 900 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[850]; |
| 901 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[851]; |
| 902 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[852]; |
| 903 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[853]; |
| 904 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[854]; |
| 905 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[855]; |
| 906 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub14_sub15_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[856]; |
| 907 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[857]; |
| 908 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[858]; |
| 909 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[859]; |
| 910 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[860]; |
| 911 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[861]; |
| 912 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[862]; |
| 913 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub16_sub17_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[863]; |
| 914 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub10_sub11_in_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[864]; |
| 915 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[865]; |
| 916 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub18_sub19_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[866]; |
| 917 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub2_sub3_in_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[867]; |
| 918 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[868]; |
| 919 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub6_sub7_in_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[869]; |
| 920 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[870]; |
| 921 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[871]; |
| 922 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[872]; |
| 923 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[873]; |
| 924 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[874]; |
| 925 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_in_SGPR_512_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_512_with_sub12_sub13_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[875]; |
| 926 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub20_sub21_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[876]; |
| 927 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub22_sub23_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[877]; |
| 928 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[878]; |
| 929 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[879]; |
| 930 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_1024_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[880]; |
| 931 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[881]; |
| 932 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[882]; |
| 933 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[883]; |
| 934 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub4_lo16_sub4_hi16_sub5_lo16_sub5_hi16_sub6_lo16_sub6_hi16_sub7_lo16_sub7_hi16_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[884]; |
| 935 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64_with_sub8_lo16_sub8_hi16_sub9_lo16_sub9_hi16_sub10_lo16_sub10_hi16_sub11_lo16_sub11_hi16_sub12_lo16_sub12_hi16_sub13_lo16_sub13_hi16_sub14_lo16_sub14_hi16_sub15_lo16_sub15_hi16_sub16_lo16_sub16_hi16_sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_in_SGPR_384_with_sub0_sub1_in_CCR_SGPR_64_and_SGPR_384_with_sub8_sub9_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[885]; |
| 936 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub0_sub1_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub24_sub25_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[886]; |
| 937 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub26_sub27_in_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[887]; |
| 938 | static constexpr const TargetRegisterClass &SGPR_1024_with_sub4_sub5_in_Gfx_CCR_SGPR_64_and_SGPR_1024_with_sub28_sub29_in_Gfx_CCR_SGPR_64RegClass = AMDGPUMCRegisterClassStorage.Classes[888]; |
| 939 | |
| 940 | } // namespace AMDGPU |
| 941 | |
| 942 | } // namespace llvm |
| 943 |
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