1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: AMDGPU.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::AMDGPUISD {
14
15enum GenNodeType : unsigned {
16 ATOMIC_CMP_SWAP = ISD::BUILTIN_OP_END,
17 BFE_I32,
18 BFE_U32,
19 BFI,
20 BORROW,
21 BRANCH_COND,
22 BUFFER_ATOMIC_ADD,
23 BUFFER_ATOMIC_AND,
24 BUFFER_ATOMIC_CMPSWAP,
25 BUFFER_ATOMIC_COND_SUB_U32,
26 BUFFER_ATOMIC_CSUB,
27 BUFFER_ATOMIC_DEC,
28 BUFFER_ATOMIC_FADD,
29 BUFFER_ATOMIC_FMAX,
30 BUFFER_ATOMIC_FMIN,
31 BUFFER_ATOMIC_INC,
32 BUFFER_ATOMIC_OR,
33 BUFFER_ATOMIC_SMAX,
34 BUFFER_ATOMIC_SMIN,
35 BUFFER_ATOMIC_SUB,
36 BUFFER_ATOMIC_SWAP,
37 BUFFER_ATOMIC_UMAX,
38 BUFFER_ATOMIC_UMIN,
39 BUFFER_ATOMIC_XOR,
40 BUFFER_LOAD,
41 BUFFER_LOAD_BYTE,
42 BUFFER_LOAD_BYTE_TFE,
43 BUFFER_LOAD_FORMAT,
44 BUFFER_LOAD_FORMAT_D16,
45 BUFFER_LOAD_FORMAT_TFE,
46 BUFFER_LOAD_SHORT,
47 BUFFER_LOAD_SHORT_TFE,
48 BUFFER_LOAD_TFE,
49 BUFFER_LOAD_UBYTE,
50 BUFFER_LOAD_UBYTE_TFE,
51 BUFFER_LOAD_USHORT,
52 BUFFER_LOAD_USHORT_TFE,
53 BUFFER_STORE,
54 BUFFER_STORE_BYTE,
55 BUFFER_STORE_FORMAT,
56 BUFFER_STORE_FORMAT_D16,
57 BUFFER_STORE_SHORT,
58 CALL,
59 CARRY,
60 CLAMP,
61 CONST_DATA_PTR,
62 COS_HW,
63 CVT_F32_FP8_E5M3,
64 CVT_F32_UBYTE0,
65 CVT_F32_UBYTE1,
66 CVT_F32_UBYTE2,
67 CVT_F32_UBYTE3,
68 CVT_PKNORM_I16_F32,
69 CVT_PKNORM_U16_F32,
70 CVT_PKRTZ_F16_F32,
71 CVT_PK_BF8_F16,
72 CVT_PK_BF8_F32,
73 CVT_PK_F16_BF8,
74 CVT_PK_F16_FP8,
75 CVT_PK_F32_BF8,
76 CVT_PK_F32_FP8,
77 CVT_PK_FP8_F16,
78 CVT_PK_FP8_F32,
79 CVT_PK_FP8_F32_E5M3,
80 CVT_PK_I16_I32,
81 CVT_PK_U16_U32,
82 DENORM_MODE,
83 DIV_FIXUP,
84 DIV_FMAS,
85 DIV_SCALE,
86 DS_ORDERED_COUNT,
87 DWORDADDR,
88 ELSE,
89 ENDPGM,
90 ENDPGM_TRAP,
91 EXP,
92 FDOT2,
93 FFBH_U32,
94 FFBL_B32,
95 FLAT_LOAD_MONITOR,
96 FMAD_FTZ,
97 FMAX3,
98 FMAXIMUM3,
99 FMAX_LEGACY,
100 FMA_W_CHAIN,
101 FMED3,
102 FMIN3,
103 FMINIMUM3,
104 FMIN_LEGACY,
105 FMUL_LEGACY,
106 FMUL_W_CHAIN,
107 FP_CLASS,
108 FP_TO_FP16,
109 FRACT,
110 GLOBAL_LOAD_MONITOR,
111 IF,
112 LDS,
113 LOAD_D16_HI,
114 LOAD_D16_HI_I8,
115 LOAD_D16_HI_U8,
116 LOAD_D16_LO,
117 LOAD_D16_LO_I8,
118 LOAD_D16_LO_U8,
119 LOG,
120 LOOP,
121 MAD_I24,
122 MAD_U24,
123 MULHI_I24,
124 MULHI_U24,
125 MUL_I24,
126 MUL_U24,
127 PC_ADD_REL_OFFSET,
128 PC_ADD_REL_OFFSET64,
129 PERM,
130 RCP,
131 RCP_IFLAG,
132 RCP_LEGACY,
133 REGISTER_LOAD,
134 REGISTER_STORE,
135 RETURN_TO_EPILOG,
136 RET_GLUE,
137 RSQ,
138 RSQ_CLAMP,
139 SBUFFER_LOAD,
140 SBUFFER_LOAD_BYTE,
141 SBUFFER_LOAD_SHORT,
142 SBUFFER_LOAD_UBYTE,
143 SBUFFER_LOAD_USHORT,
144 SBUFFER_PREFETCH_DATA,
145 SETCC,
146 SIMULATED_TRAP,
147 SIN_HW,
148 SMAX3,
149 SMED3,
150 SMIN3,
151 STORE_MSKOR,
152 TBUFFER_LOAD_FORMAT,
153 TBUFFER_LOAD_FORMAT_D16,
154 TBUFFER_STORE_FORMAT,
155 TBUFFER_STORE_FORMAT_D16,
156 TC_RETURN,
157 TC_RETURN_CHAIN,
158 TC_RETURN_CHAIN_DVGPR,
159 TC_RETURN_GFX,
160 TC_RETURN_GFX_WholeWave,
161 TRAP,
162 UMAX3,
163 UMED3,
164 UMIN3,
165 URECIP,
166 WHOLE_WAVE_RETURN,
167 WHOLE_WAVE_SETUP,
168};
169
170static constexpr unsigned GENERATED_OPCODE_END = WHOLE_WAVE_SETUP + 1;
171
172} // namespace llvm::AMDGPUISD
173
174#endif // GET_SDNODE_ENUM
175
176#ifdef GET_SDNODE_DESC
177#undef GET_SDNODE_DESC
178
179namespace llvm {
180
181
182#ifdef __GNUC__
183#pragma GCC diagnostic push
184#pragma GCC diagnostic ignored "-Woverlength-strings"
185#endif
186static constexpr char AMDGPUSDNodeNamesStorage[] =
187 "\0"
188 "AMDGPUISD::ATOMIC_CMP_SWAP\0"
189 "AMDGPUISD::BFE_I32\0"
190 "AMDGPUISD::BFE_U32\0"
191 "AMDGPUISD::BFI\0"
192 "AMDGPUISD::BORROW\0"
193 "AMDGPUISD::BRANCH_COND\0"
194 "AMDGPUISD::BUFFER_ATOMIC_ADD\0"
195 "AMDGPUISD::BUFFER_ATOMIC_AND\0"
196 "AMDGPUISD::BUFFER_ATOMIC_CMPSWAP\0"
197 "AMDGPUISD::BUFFER_ATOMIC_COND_SUB_U32\0"
198 "AMDGPUISD::BUFFER_ATOMIC_CSUB\0"
199 "AMDGPUISD::BUFFER_ATOMIC_DEC\0"
200 "AMDGPUISD::BUFFER_ATOMIC_FADD\0"
201 "AMDGPUISD::BUFFER_ATOMIC_FMAX\0"
202 "AMDGPUISD::BUFFER_ATOMIC_FMIN\0"
203 "AMDGPUISD::BUFFER_ATOMIC_INC\0"
204 "AMDGPUISD::BUFFER_ATOMIC_OR\0"
205 "AMDGPUISD::BUFFER_ATOMIC_SMAX\0"
206 "AMDGPUISD::BUFFER_ATOMIC_SMIN\0"
207 "AMDGPUISD::BUFFER_ATOMIC_SUB\0"
208 "AMDGPUISD::BUFFER_ATOMIC_SWAP\0"
209 "AMDGPUISD::BUFFER_ATOMIC_UMAX\0"
210 "AMDGPUISD::BUFFER_ATOMIC_UMIN\0"
211 "AMDGPUISD::BUFFER_ATOMIC_XOR\0"
212 "AMDGPUISD::BUFFER_LOAD\0"
213 "AMDGPUISD::BUFFER_LOAD_BYTE\0"
214 "AMDGPUISD::BUFFER_LOAD_BYTE_TFE\0"
215 "AMDGPUISD::BUFFER_LOAD_FORMAT\0"
216 "AMDGPUISD::BUFFER_LOAD_FORMAT_D16\0"
217 "AMDGPUISD::BUFFER_LOAD_FORMAT_TFE\0"
218 "AMDGPUISD::BUFFER_LOAD_SHORT\0"
219 "AMDGPUISD::BUFFER_LOAD_SHORT_TFE\0"
220 "AMDGPUISD::BUFFER_LOAD_TFE\0"
221 "AMDGPUISD::BUFFER_LOAD_UBYTE\0"
222 "AMDGPUISD::BUFFER_LOAD_UBYTE_TFE\0"
223 "AMDGPUISD::BUFFER_LOAD_USHORT\0"
224 "AMDGPUISD::BUFFER_LOAD_USHORT_TFE\0"
225 "AMDGPUISD::BUFFER_STORE\0"
226 "AMDGPUISD::BUFFER_STORE_BYTE\0"
227 "AMDGPUISD::BUFFER_STORE_FORMAT\0"
228 "AMDGPUISD::BUFFER_STORE_FORMAT_D16\0"
229 "AMDGPUISD::BUFFER_STORE_SHORT\0"
230 "AMDGPUISD::CALL\0"
231 "AMDGPUISD::CARRY\0"
232 "AMDGPUISD::CLAMP\0"
233 "AMDGPUISD::CONST_DATA_PTR\0"
234 "AMDGPUISD::COS_HW\0"
235 "AMDGPUISD::CVT_F32_FP8_E5M3\0"
236 "AMDGPUISD::CVT_F32_UBYTE0\0"
237 "AMDGPUISD::CVT_F32_UBYTE1\0"
238 "AMDGPUISD::CVT_F32_UBYTE2\0"
239 "AMDGPUISD::CVT_F32_UBYTE3\0"
240 "AMDGPUISD::CVT_PKNORM_I16_F32\0"
241 "AMDGPUISD::CVT_PKNORM_U16_F32\0"
242 "AMDGPUISD::CVT_PKRTZ_F16_F32\0"
243 "AMDGPUISD::CVT_PK_BF8_F16\0"
244 "AMDGPUISD::CVT_PK_BF8_F32\0"
245 "AMDGPUISD::CVT_PK_F16_BF8\0"
246 "AMDGPUISD::CVT_PK_F16_FP8\0"
247 "AMDGPUISD::CVT_PK_F32_BF8\0"
248 "AMDGPUISD::CVT_PK_F32_FP8\0"
249 "AMDGPUISD::CVT_PK_FP8_F16\0"
250 "AMDGPUISD::CVT_PK_FP8_F32\0"
251 "AMDGPUISD::CVT_PK_FP8_F32_E5M3\0"
252 "AMDGPUISD::CVT_PK_I16_I32\0"
253 "AMDGPUISD::CVT_PK_U16_U32\0"
254 "AMDGPUISD::DENORM_MODE\0"
255 "AMDGPUISD::DIV_FIXUP\0"
256 "AMDGPUISD::DIV_FMAS\0"
257 "AMDGPUISD::DIV_SCALE\0"
258 "AMDGPUISD::DS_ORDERED_COUNT\0"
259 "AMDGPUISD::DWORDADDR\0"
260 "AMDGPUISD::ELSE\0"
261 "AMDGPUISD::ENDPGM\0"
262 "AMDGPUISD::ENDPGM_TRAP\0"
263 "AMDGPUISD::EXP\0"
264 "AMDGPUISD::FDOT2\0"
265 "AMDGPUISD::FFBH_U32\0"
266 "AMDGPUISD::FFBL_B32\0"
267 "AMDGPUISD::FLAT_LOAD_MONITOR\0"
268 "AMDGPUISD::FMAD_FTZ\0"
269 "AMDGPUISD::FMAX3\0"
270 "AMDGPUISD::FMAXIMUM3\0"
271 "AMDGPUISD::FMAX_LEGACY\0"
272 "AMDGPUISD::FMA_W_CHAIN\0"
273 "AMDGPUISD::FMED3\0"
274 "AMDGPUISD::FMIN3\0"
275 "AMDGPUISD::FMINIMUM3\0"
276 "AMDGPUISD::FMIN_LEGACY\0"
277 "AMDGPUISD::FMUL_LEGACY\0"
278 "AMDGPUISD::FMUL_W_CHAIN\0"
279 "AMDGPUISD::FP_CLASS\0"
280 "AMDGPUISD::FP_TO_FP16\0"
281 "AMDGPUISD::FRACT\0"
282 "AMDGPUISD::GLOBAL_LOAD_MONITOR\0"
283 "AMDGPUISD::IF\0"
284 "AMDGPUISD::LDS\0"
285 "AMDGPUISD::LOAD_D16_HI\0"
286 "AMDGPUISD::LOAD_D16_HI_I8\0"
287 "AMDGPUISD::LOAD_D16_HI_U8\0"
288 "AMDGPUISD::LOAD_D16_LO\0"
289 "AMDGPUISD::LOAD_D16_LO_I8\0"
290 "AMDGPUISD::LOAD_D16_LO_U8\0"
291 "AMDGPUISD::LOG\0"
292 "AMDGPUISD::LOOP\0"
293 "AMDGPUISD::MAD_I24\0"
294 "AMDGPUISD::MAD_U24\0"
295 "AMDGPUISD::MULHI_I24\0"
296 "AMDGPUISD::MULHI_U24\0"
297 "AMDGPUISD::MUL_I24\0"
298 "AMDGPUISD::MUL_U24\0"
299 "AMDGPUISD::PC_ADD_REL_OFFSET\0"
300 "AMDGPUISD::PC_ADD_REL_OFFSET64\0"
301 "AMDGPUISD::PERM\0"
302 "AMDGPUISD::RCP\0"
303 "AMDGPUISD::RCP_IFLAG\0"
304 "AMDGPUISD::RCP_LEGACY\0"
305 "AMDGPUISD::REGISTER_LOAD\0"
306 "AMDGPUISD::REGISTER_STORE\0"
307 "AMDGPUISD::RETURN_TO_EPILOG\0"
308 "AMDGPUISD::RET_GLUE\0"
309 "AMDGPUISD::RSQ\0"
310 "AMDGPUISD::RSQ_CLAMP\0"
311 "AMDGPUISD::SBUFFER_LOAD\0"
312 "AMDGPUISD::SBUFFER_LOAD_BYTE\0"
313 "AMDGPUISD::SBUFFER_LOAD_SHORT\0"
314 "AMDGPUISD::SBUFFER_LOAD_UBYTE\0"
315 "AMDGPUISD::SBUFFER_LOAD_USHORT\0"
316 "AMDGPUISD::SBUFFER_PREFETCH_DATA\0"
317 "AMDGPUISD::SETCC\0"
318 "AMDGPUISD::SIMULATED_TRAP\0"
319 "AMDGPUISD::SIN_HW\0"
320 "AMDGPUISD::SMAX3\0"
321 "AMDGPUISD::SMED3\0"
322 "AMDGPUISD::SMIN3\0"
323 "AMDGPUISD::STORE_MSKOR\0"
324 "AMDGPUISD::TBUFFER_LOAD_FORMAT\0"
325 "AMDGPUISD::TBUFFER_LOAD_FORMAT_D16\0"
326 "AMDGPUISD::TBUFFER_STORE_FORMAT\0"
327 "AMDGPUISD::TBUFFER_STORE_FORMAT_D16\0"
328 "AMDGPUISD::TC_RETURN\0"
329 "AMDGPUISD::TC_RETURN_CHAIN\0"
330 "AMDGPUISD::TC_RETURN_CHAIN_DVGPR\0"
331 "AMDGPUISD::TC_RETURN_GFX\0"
332 "AMDGPUISD::TC_RETURN_GFX_WholeWave\0"
333 "AMDGPUISD::TRAP\0"
334 "AMDGPUISD::UMAX3\0"
335 "AMDGPUISD::UMED3\0"
336 "AMDGPUISD::UMIN3\0"
337 "AMDGPUISD::URECIP\0"
338 "AMDGPUISD::WHOLE_WAVE_RETURN\0"
339 "AMDGPUISD::WHOLE_WAVE_SETUP\0"
340 ;
341#ifdef __GNUC__
342#pragma GCC diagnostic pop
343#endif
344
345static constexpr llvm::StringTable
346AMDGPUSDNodeNames = AMDGPUSDNodeNamesStorage;
347
348static const VTByHwModePair AMDGPUVTByHwModeTable[] = {
349 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
350};
351
352static const SDTypeConstraint AMDGPUSDTypeConstraints[] = {
353 /* 0 */ {SDTCisVT, 0, 0, 0, MVT::Other},
354 /* 1 */ {SDTCisVT, 1, 0, 0, MVT::Other}, {SDTCisVT, 0, 0, 0, MVT::i1},
355 /* 3 */ {SDTCisVT, 2, 0, 0, MVT::Other}, {SDTCisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 0, 0, 0, MVT::i1},
356 /* 6 */ {SDTCisVT, 1, 0, 0, MVT::v2f16}, {SDTCisVT, 0, 0, 0, MVT::i16},
357 /* 8 */ {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
358 /* 10 */ {SDTCisVT, 2, 0, 0, MVT::i16}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
359 /* 13 */ {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::i32},
360 /* 18 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::f32},
361 /* 21 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::v4i32},
362 /* 24 */ {SDTCisVT, 1, 0, 0, MVT::i16}, {SDTCisVT, 0, 0, 0, MVT::v2f16},
363 /* 26 */ {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::v2f32},
364 /* 28 */ {SDTCisVT, 0, 0, 0, MVT::iPTR}, {SDTCisVT, 0, 0, 0, MVT::iPTR},
365 /* 30 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::iPTR},
366 /* 33 */ {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
367 /* 34 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
368 /* 37 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
369 /* 40 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
370 /* 43 */ {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
371 /* 46 */ {SDTCisInt, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
372 /* 51 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
373 /* 56 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
374 /* 59 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
375 /* 61 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
376 /* 63 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
377 /* 67 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
378 /* 70 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
379 /* 74 */ {SDTCisInt, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
380 /* 79 */ {SDTCisVT, 7, 0, 0, MVT::i1}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::v4i32},
381 /* 86 */ {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::v4i32},
382 /* 94 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
383 /* 96 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
384 /* 98 */ {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
385 /* 100 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
386 /* 102 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
387 /* 104 */ {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::v4i32},
388 /* 111 */ {SDTCisVT, 9, 0, 0, MVT::i1}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::v4i32},
389};
390
391static const SDNodeDesc AMDGPUSDNodeDescs[] = {
392 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1, 98, 2}, // ATOMIC_CMP_SWAP
393 {1, 3, 0, 0, 0, 28, 63, 4}, // BFE_I32
394 {1, 3, 0, 0, 0, 47, 63, 4}, // BFE_U32
395 {1, 3, 0, 0, 0, 66, 63, 4}, // BFI
396 {1, 2, 0, 0, 0, 81, 64, 3}, // BORROW
397 {0, 2, 0|1<<SDNPHasChain, 0, 0, 99, 0, 1}, // BRANCH_COND
398 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 122, 104, 7}, // BUFFER_ATOMIC_ADD
399 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 151, 104, 7}, // BUFFER_ATOMIC_AND
400 {1, 9, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 180, 111, 7}, // BUFFER_ATOMIC_CMPSWAP
401 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 213, 104, 7}, // BUFFER_ATOMIC_COND_SUB_U32
402 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 251, 104, 7}, // BUFFER_ATOMIC_CSUB
403 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 281, 104, 7}, // BUFFER_ATOMIC_DEC
404 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 310, 104, 7}, // BUFFER_ATOMIC_FADD
405 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 340, 104, 7}, // BUFFER_ATOMIC_FMAX
406 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 370, 104, 7}, // BUFFER_ATOMIC_FMIN
407 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 400, 104, 7}, // BUFFER_ATOMIC_INC
408 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 429, 104, 7}, // BUFFER_ATOMIC_OR
409 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 457, 104, 7}, // BUFFER_ATOMIC_SMAX
410 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 487, 104, 7}, // BUFFER_ATOMIC_SMIN
411 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 517, 104, 7}, // BUFFER_ATOMIC_SUB
412 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 546, 104, 7}, // BUFFER_ATOMIC_SWAP
413 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 576, 104, 7}, // BUFFER_ATOMIC_UMAX
414 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 606, 104, 7}, // BUFFER_ATOMIC_UMIN
415 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 636, 104, 7}, // BUFFER_ATOMIC_XOR
416 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 665, 79, 7}, // BUFFER_LOAD
417 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 688, 79, 7}, // BUFFER_LOAD_BYTE
418 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 716, 79, 7}, // BUFFER_LOAD_BYTE_TFE
419 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 748, 79, 7}, // BUFFER_LOAD_FORMAT
420 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 778, 79, 7}, // BUFFER_LOAD_FORMAT_D16
421 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 812, 79, 7}, // BUFFER_LOAD_FORMAT_TFE
422 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 846, 79, 7}, // BUFFER_LOAD_SHORT
423 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 875, 79, 7}, // BUFFER_LOAD_SHORT_TFE
424 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 908, 79, 7}, // BUFFER_LOAD_TFE
425 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 935, 79, 7}, // BUFFER_LOAD_UBYTE
426 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 964, 79, 7}, // BUFFER_LOAD_UBYTE_TFE
427 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 997, 79, 7}, // BUFFER_LOAD_USHORT
428 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1027, 79, 7}, // BUFFER_LOAD_USHORT_TFE
429 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1061, 79, 7}, // BUFFER_STORE
430 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1085, 79, 7}, // BUFFER_STORE_BYTE
431 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1114, 79, 7}, // BUFFER_STORE_FORMAT
432 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1145, 79, 7}, // BUFFER_STORE_FORMAT_D16
433 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1180, 79, 7}, // BUFFER_STORE_SHORT
434 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 1210, 33, 1}, // CALL
435 {1, 2, 0, 0, 0, 1226, 64, 3}, // CARRY
436 {1, 1, 0, 0, 0, 1243, 61, 2}, // CLAMP
437 {1, 1, 0, 0, 0, 1260, 28, 2}, // CONST_DATA_PTR
438 {1, 1, 0, 0, 0, 1286, 61, 2}, // COS_HW
439 {1, 2, 0, 0, 0, 1304, 18, 3}, // CVT_F32_FP8_E5M3
440 {1, 1, 0, 0, 0, 1332, 56, 3}, // CVT_F32_UBYTE0
441 {1, 1, 0, 0, 0, 1358, 56, 3}, // CVT_F32_UBYTE1
442 {1, 1, 0, 0, 0, 1384, 56, 3}, // CVT_F32_UBYTE2
443 {1, 1, 0, 0, 0, 1410, 56, 3}, // CVT_F32_UBYTE3
444 {1, 2, 0, 0, 0, 1436, 102, 2}, // CVT_PKNORM_I16_F32
445 {1, 2, 0, 0, 0, 1466, 102, 2}, // CVT_PKNORM_U16_F32
446 {1, 2, 0, 0, 0, 1496, 102, 2}, // CVT_PKRTZ_F16_F32
447 {1, 1, 0, 0, 0, 1525, 6, 2}, // CVT_PK_BF8_F16
448 {1, 4, 0, 0, 0, 1551, 13, 5}, // CVT_PK_BF8_F32
449 {1, 1, 0, 0, 0, 1577, 24, 2}, // CVT_PK_F16_BF8
450 {1, 1, 0, 0, 0, 1603, 24, 2}, // CVT_PK_F16_FP8
451 {1, 1, 0, 0, 0, 1629, 26, 2}, // CVT_PK_F32_BF8
452 {1, 1, 0, 0, 0, 1655, 26, 2}, // CVT_PK_F32_FP8
453 {1, 1, 0, 0, 0, 1681, 6, 2}, // CVT_PK_FP8_F16
454 {1, 4, 0, 0, 0, 1707, 13, 5}, // CVT_PK_FP8_F32
455 {1, 4, 0, 0, 0, 1733, 13, 5}, // CVT_PK_FP8_F32_E5M3
456 {1, 2, 0, 0, 0, 1764, 100, 2}, // CVT_PK_I16_I32
457 {1, 2, 0, 0, 0, 1790, 100, 2}, // CVT_PK_U16_U32
458 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 1816, 36, 1}, // DENORM_MODE
459 {1, 3, 0, 0, 0, 1839, 70, 4}, // DIV_FIXUP
460 {1, 4, 0|1<<SDNPOptInGlue, 0, 0, 1860, 46, 5}, // DIV_FMAS
461 {2, 3, 0, 0, 0, 1880, 51, 5}, // DIV_SCALE
462 {1, 2, 0|1<<SDNPHasChain|1<<SDNPInGlue|1<<SDNPMemOperand, 0, 0, 1901, 10, 3}, // DS_ORDERED_COUNT
463 {1, 1, 0, 0, 0, 1929, 59, 2}, // DWORDADDR
464 {1, 2, 0|1<<SDNPHasChain, 0, 0, 1950, 3, 3}, // ELSE
465 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue, 0, 0, 1966, 0, 0}, // ENDPGM
466 {0, 0, 0|1<<SDNPHasChain, 0, 0, 1984, 0, 0}, // ENDPGM_TRAP
467 {1, 1, 0, 0, 0, 2007, 61, 2}, // EXP
468 {1, 4, 0, 0, 0, 2022, 74, 5}, // FDOT2
469 {1, 1, 0, 0, 0, 2039, 34, 3}, // FFBH_U32
470 {1, 1, 0, 0, 0, 2059, 34, 3}, // FFBL_B32
471 {1, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2079, 95, 1}, // FLAT_LOAD_MONITOR
472 {1, 3, 0, 0, 0, 2108, 70, 4}, // FMAD_FTZ
473 {1, 3, 0, 0, 0, 2128, 70, 4}, // FMAX3
474 {1, 3, 0, 0, 0, 2145, 70, 4}, // FMAXIMUM3
475 {1, 2, 0, 0, 0, 2166, 67, 3}, // FMAX_LEGACY
476 {1, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 2189, 70, 4}, // FMA_W_CHAIN
477 {1, 3, 0, 0, 0, 2212, 70, 4}, // FMED3
478 {1, 3, 0, 0, 0, 2229, 70, 4}, // FMIN3
479 {1, 3, 0, 0, 0, 2246, 70, 4}, // FMINIMUM3
480 {1, 2, 0, 0, 0, 2267, 67, 3}, // FMIN_LEGACY
481 {1, 2, 0, 0, 0, 2290, 67, 3}, // FMUL_LEGACY
482 {1, 2, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 2313, 67, 3}, // FMUL_W_CHAIN
483 {1, 2, 0, 0, 0, 2337, 40, 3}, // FP_CLASS
484 {1, 1, 0, 0, 0, 2357, 37, 3}, // FP_TO_FP16
485 {1, 1, 0, 0, 0, 2379, 61, 2}, // FRACT
486 {1, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2396, 95, 1}, // GLOBAL_LOAD_MONITOR
487 {1, 2, 0|1<<SDNPHasChain, 0, 0, 2427, 3, 3}, // IF
488 {1, 1, 0, 0, 0, 2441, 8, 2}, // LDS
489 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2456, 94, 2}, // LOAD_D16_HI
490 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2479, 94, 2}, // LOAD_D16_HI_I8
491 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2505, 94, 2}, // LOAD_D16_HI_U8
492 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2531, 94, 2}, // LOAD_D16_LO
493 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2554, 94, 2}, // LOAD_D16_LO_I8
494 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2580, 94, 2}, // LOAD_D16_LO_U8
495 {1, 1, 0, 0, 0, 2606, 61, 2}, // LOG
496 {0, 2, 0|1<<SDNPHasChain, 0, 0, 2621, 1, 2}, // LOOP
497 {1, 3, 0, 0, 0, 2637, 63, 4}, // MAD_I24
498 {1, 3, 0, 0, 0, 2656, 63, 4}, // MAD_U24
499 {1, 2, 0, 0, 0, 2675, 64, 3}, // MULHI_I24
500 {1, 2, 0, 0, 0, 2696, 64, 3}, // MULHI_U24
501 {1, 2, 0, 0, 0, 2717, 0, 0}, // MUL_I24
502 {1, 2, 0, 0, 0, 2736, 0, 0}, // MUL_U24
503 {1, 2, 0, 0, 0, 2755, 30, 3}, // PC_ADD_REL_OFFSET
504 {1, 1, 0, 0, 0, 2784, 31, 2}, // PC_ADD_REL_OFFSET64
505 {1, 3, 0, 0, 0, 2815, 63, 4}, // PERM
506 {1, 1, 0, 0, 0, 2831, 61, 2}, // RCP
507 {1, 1, 0, 0, 0, 2846, 61, 2}, // RCP_IFLAG
508 {1, 1, 0, 0, 0, 2867, 61, 2}, // RCP_LEGACY
509 {1, 2, 0|1<<SDNPHasChain, 0, 0, 2889, 96, 2}, // REGISTER_LOAD
510 {0, 3, 0|1<<SDNPHasChain, 0, 0, 2914, 96, 2}, // REGISTER_STORE
511 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 2940, 0, 0}, // RETURN_TO_EPILOG
512 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 2968, 0, 0}, // RET_GLUE
513 {1, 1, 0, 0, 0, 2988, 61, 2}, // RSQ
514 {1, 1, 0, 0, 0, 3003, 61, 2}, // RSQ_CLAMP
515 {1, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3024, 83, 3}, // SBUFFER_LOAD
516 {1, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3048, 83, 3}, // SBUFFER_LOAD_BYTE
517 {1, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3077, 83, 3}, // SBUFFER_LOAD_SHORT
518 {1, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3107, 83, 3}, // SBUFFER_LOAD_UBYTE
519 {1, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3137, 83, 3}, // SBUFFER_LOAD_USHORT
520 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3168, 21, 3}, // SBUFFER_PREFETCH_DATA
521 {1, 3, 0, 0, 0, 3201, 43, 3}, // SETCC
522 {0, 0, 0|1<<SDNPHasChain, 0, 0, 3218, 0, 0}, // SIMULATED_TRAP
523 {1, 1, 0, 0, 0, 3244, 61, 2}, // SIN_HW
524 {1, 3, 0, 0, 0, 3262, 63, 4}, // SMAX3
525 {1, 3, 0, 0, 0, 3279, 63, 4}, // SMED3
526 {1, 3, 0, 0, 0, 3296, 63, 4}, // SMIN3
527 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3313, 0, 0}, // STORE_MSKOR
528 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3336, 86, 8}, // TBUFFER_LOAD_FORMAT
529 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3367, 86, 8}, // TBUFFER_LOAD_FORMAT_D16
530 {0, 9, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3402, 86, 8}, // TBUFFER_STORE_FORMAT
531 {0, 9, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3434, 86, 8}, // TBUFFER_STORE_FORMAT_D16
532 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3470, 33, 1}, // TC_RETURN
533 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3491, 33, 1}, // TC_RETURN_CHAIN
534 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3518, 33, 1}, // TC_RETURN_CHAIN_DVGPR
535 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3551, 33, 1}, // TC_RETURN_GFX
536 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3576, 33, 1}, // TC_RETURN_GFX_WholeWave
537 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3611, 7, 1}, // TRAP
538 {1, 3, 0, 0, 0, 3627, 63, 4}, // UMAX3
539 {1, 3, 0, 0, 0, 3644, 63, 4}, // UMED3
540 {1, 3, 0, 0, 0, 3661, 63, 4}, // UMIN3
541 {1, 1, 0, 0, 0, 3678, 59, 2}, // URECIP
542 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3696, 0, 0}, // WHOLE_WAVE_RETURN
543 {1, 0, 0|1<<SDNPHasChain, 0, 0, 3725, 36, 1}, // WHOLE_WAVE_SETUP
544};
545
546static const SDNodeInfo AMDGPUGenSDNodeInfo(
547 /*NumOpcodes=*/152, AMDGPUSDNodeDescs, AMDGPUSDNodeNames,
548 AMDGPUVTByHwModeTable, AMDGPUSDTypeConstraints);
549
550} // namespace llvm
551
552#endif // GET_SDNODE_DESC
553
554