1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: AMDGPU.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::AMDGPUISD {
14
15enum GenNodeType : unsigned {
16 ATOMIC_CMP_SWAP = ISD::BUILTIN_OP_END,
17 BFE_I32,
18 BFE_U32,
19 BFI,
20 BORROW,
21 BRANCH_COND,
22 BUFFER_ATOMIC_ADD,
23 BUFFER_ATOMIC_AND,
24 BUFFER_ATOMIC_CMPSWAP,
25 BUFFER_ATOMIC_COND_SUB_U32,
26 BUFFER_ATOMIC_CSUB,
27 BUFFER_ATOMIC_DEC,
28 BUFFER_ATOMIC_FADD,
29 BUFFER_ATOMIC_FMAX,
30 BUFFER_ATOMIC_FMIN,
31 BUFFER_ATOMIC_INC,
32 BUFFER_ATOMIC_OR,
33 BUFFER_ATOMIC_SMAX,
34 BUFFER_ATOMIC_SMIN,
35 BUFFER_ATOMIC_SUB,
36 BUFFER_ATOMIC_SWAP,
37 BUFFER_ATOMIC_UMAX,
38 BUFFER_ATOMIC_UMIN,
39 BUFFER_ATOMIC_XOR,
40 BUFFER_LOAD,
41 BUFFER_LOAD_BYTE,
42 BUFFER_LOAD_BYTE_TFE,
43 BUFFER_LOAD_FORMAT,
44 BUFFER_LOAD_FORMAT_D16,
45 BUFFER_LOAD_FORMAT_D16_TFE,
46 BUFFER_LOAD_FORMAT_TFE,
47 BUFFER_LOAD_SHORT,
48 BUFFER_LOAD_SHORT_TFE,
49 BUFFER_LOAD_TFE,
50 BUFFER_LOAD_UBYTE,
51 BUFFER_LOAD_UBYTE_TFE,
52 BUFFER_LOAD_USHORT,
53 BUFFER_LOAD_USHORT_TFE,
54 BUFFER_STORE,
55 BUFFER_STORE_BYTE,
56 BUFFER_STORE_FORMAT,
57 BUFFER_STORE_FORMAT_D16,
58 BUFFER_STORE_SHORT,
59 CALL,
60 CARRY,
61 CLAMP,
62 CONST_DATA_PTR,
63 COS_HW,
64 CVT_F32_FP8_E5M3,
65 CVT_F32_UBYTE0,
66 CVT_F32_UBYTE1,
67 CVT_F32_UBYTE2,
68 CVT_F32_UBYTE3,
69 CVT_PKNORM_I16_F32,
70 CVT_PKNORM_U16_F32,
71 CVT_PKRTZ_F16_F32,
72 CVT_PK_BF8_F16,
73 CVT_PK_BF8_F32,
74 CVT_PK_F16_BF8,
75 CVT_PK_F16_FP8,
76 CVT_PK_F32_BF8,
77 CVT_PK_F32_FP8,
78 CVT_PK_FP8_F16,
79 CVT_PK_FP8_F32,
80 CVT_PK_FP8_F32_E5M3,
81 CVT_PK_I16_I32,
82 CVT_PK_U16_U32,
83 DENORM_MODE,
84 DIV_FIXUP,
85 DIV_FMAS,
86 DIV_SCALE,
87 DS_ORDERED_COUNT,
88 DWORDADDR,
89 ELSE,
90 ENDPGM,
91 ENDPGM_TRAP,
92 EXP,
93 FDOT2,
94 FFBH_U32,
95 FFBL_B32,
96 FLAT_LOAD_MONITOR,
97 FMAD_FTZ,
98 FMAX3,
99 FMAXIMUM3,
100 FMAX_LEGACY,
101 FMA_W_CHAIN,
102 FMED3,
103 FMIN3,
104 FMINIMUM3,
105 FMIN_LEGACY,
106 FMUL_LEGACY,
107 FMUL_W_CHAIN,
108 FP_CLASS,
109 FP_TO_FP16,
110 FRACT,
111 GLOBAL_LOAD_MONITOR,
112 IF,
113 LDS,
114 LOAD_D16_HI,
115 LOAD_D16_HI_I8,
116 LOAD_D16_HI_U8,
117 LOAD_D16_LO,
118 LOAD_D16_LO_I8,
119 LOAD_D16_LO_U8,
120 LOG,
121 LOOP,
122 MAD_I24,
123 MAD_U24,
124 MULHI_I24,
125 MULHI_U24,
126 MUL_I24,
127 MUL_U24,
128 PC_ADD_REL_OFFSET,
129 PC_ADD_REL_OFFSET64,
130 PERM,
131 RCP,
132 RCP_IFLAG,
133 RCP_LEGACY,
134 REGISTER_LOAD,
135 REGISTER_STORE,
136 RETURN_TO_EPILOG,
137 RET_GLUE,
138 RSQ,
139 RSQ_CLAMP,
140 SBUFFER_LOAD,
141 SBUFFER_LOAD_BYTE,
142 SBUFFER_LOAD_SHORT,
143 SBUFFER_LOAD_UBYTE,
144 SBUFFER_LOAD_USHORT,
145 SBUFFER_PREFETCH_DATA,
146 SETCC,
147 SIMULATED_TRAP,
148 SIN_HW,
149 SMAX3,
150 SMED3,
151 SMIN3,
152 STORE_MSKOR,
153 TBUFFER_LOAD_FORMAT,
154 TBUFFER_LOAD_FORMAT_D16,
155 TBUFFER_STORE_FORMAT,
156 TBUFFER_STORE_FORMAT_D16,
157 TC_RETURN,
158 TC_RETURN_CHAIN,
159 TC_RETURN_CHAIN_DVGPR,
160 TC_RETURN_GFX,
161 TC_RETURN_GFX_WholeWave,
162 TRAP,
163 UMAX3,
164 UMED3,
165 UMIN3,
166 URECIP,
167 WHOLE_WAVE_RETURN,
168 WHOLE_WAVE_SETUP,
169};
170
171static constexpr unsigned GENERATED_OPCODE_END = WHOLE_WAVE_SETUP + 1;
172
173} // namespace llvm::AMDGPUISD
174
175#endif // GET_SDNODE_ENUM
176
177#ifdef GET_SDNODE_DESC
178#undef GET_SDNODE_DESC
179
180namespace llvm {
181
182
183#ifdef __GNUC__
184#pragma GCC diagnostic push
185#pragma GCC diagnostic ignored "-Woverlength-strings"
186#endif
187static constexpr char AMDGPUSDNodeNamesStorage[] =
188 "\0"
189 "AMDGPUISD::ATOMIC_CMP_SWAP\0"
190 "AMDGPUISD::BFE_I32\0"
191 "AMDGPUISD::BFE_U32\0"
192 "AMDGPUISD::BFI\0"
193 "AMDGPUISD::BORROW\0"
194 "AMDGPUISD::BRANCH_COND\0"
195 "AMDGPUISD::BUFFER_ATOMIC_ADD\0"
196 "AMDGPUISD::BUFFER_ATOMIC_AND\0"
197 "AMDGPUISD::BUFFER_ATOMIC_CMPSWAP\0"
198 "AMDGPUISD::BUFFER_ATOMIC_COND_SUB_U32\0"
199 "AMDGPUISD::BUFFER_ATOMIC_CSUB\0"
200 "AMDGPUISD::BUFFER_ATOMIC_DEC\0"
201 "AMDGPUISD::BUFFER_ATOMIC_FADD\0"
202 "AMDGPUISD::BUFFER_ATOMIC_FMAX\0"
203 "AMDGPUISD::BUFFER_ATOMIC_FMIN\0"
204 "AMDGPUISD::BUFFER_ATOMIC_INC\0"
205 "AMDGPUISD::BUFFER_ATOMIC_OR\0"
206 "AMDGPUISD::BUFFER_ATOMIC_SMAX\0"
207 "AMDGPUISD::BUFFER_ATOMIC_SMIN\0"
208 "AMDGPUISD::BUFFER_ATOMIC_SUB\0"
209 "AMDGPUISD::BUFFER_ATOMIC_SWAP\0"
210 "AMDGPUISD::BUFFER_ATOMIC_UMAX\0"
211 "AMDGPUISD::BUFFER_ATOMIC_UMIN\0"
212 "AMDGPUISD::BUFFER_ATOMIC_XOR\0"
213 "AMDGPUISD::BUFFER_LOAD\0"
214 "AMDGPUISD::BUFFER_LOAD_BYTE\0"
215 "AMDGPUISD::BUFFER_LOAD_BYTE_TFE\0"
216 "AMDGPUISD::BUFFER_LOAD_FORMAT\0"
217 "AMDGPUISD::BUFFER_LOAD_FORMAT_D16\0"
218 "AMDGPUISD::BUFFER_LOAD_FORMAT_D16_TFE\0"
219 "AMDGPUISD::BUFFER_LOAD_FORMAT_TFE\0"
220 "AMDGPUISD::BUFFER_LOAD_SHORT\0"
221 "AMDGPUISD::BUFFER_LOAD_SHORT_TFE\0"
222 "AMDGPUISD::BUFFER_LOAD_TFE\0"
223 "AMDGPUISD::BUFFER_LOAD_UBYTE\0"
224 "AMDGPUISD::BUFFER_LOAD_UBYTE_TFE\0"
225 "AMDGPUISD::BUFFER_LOAD_USHORT\0"
226 "AMDGPUISD::BUFFER_LOAD_USHORT_TFE\0"
227 "AMDGPUISD::BUFFER_STORE\0"
228 "AMDGPUISD::BUFFER_STORE_BYTE\0"
229 "AMDGPUISD::BUFFER_STORE_FORMAT\0"
230 "AMDGPUISD::BUFFER_STORE_FORMAT_D16\0"
231 "AMDGPUISD::BUFFER_STORE_SHORT\0"
232 "AMDGPUISD::CALL\0"
233 "AMDGPUISD::CARRY\0"
234 "AMDGPUISD::CLAMP\0"
235 "AMDGPUISD::CONST_DATA_PTR\0"
236 "AMDGPUISD::COS_HW\0"
237 "AMDGPUISD::CVT_F32_FP8_E5M3\0"
238 "AMDGPUISD::CVT_F32_UBYTE0\0"
239 "AMDGPUISD::CVT_F32_UBYTE1\0"
240 "AMDGPUISD::CVT_F32_UBYTE2\0"
241 "AMDGPUISD::CVT_F32_UBYTE3\0"
242 "AMDGPUISD::CVT_PKNORM_I16_F32\0"
243 "AMDGPUISD::CVT_PKNORM_U16_F32\0"
244 "AMDGPUISD::CVT_PKRTZ_F16_F32\0"
245 "AMDGPUISD::CVT_PK_BF8_F16\0"
246 "AMDGPUISD::CVT_PK_BF8_F32\0"
247 "AMDGPUISD::CVT_PK_F16_BF8\0"
248 "AMDGPUISD::CVT_PK_F16_FP8\0"
249 "AMDGPUISD::CVT_PK_F32_BF8\0"
250 "AMDGPUISD::CVT_PK_F32_FP8\0"
251 "AMDGPUISD::CVT_PK_FP8_F16\0"
252 "AMDGPUISD::CVT_PK_FP8_F32\0"
253 "AMDGPUISD::CVT_PK_FP8_F32_E5M3\0"
254 "AMDGPUISD::CVT_PK_I16_I32\0"
255 "AMDGPUISD::CVT_PK_U16_U32\0"
256 "AMDGPUISD::DENORM_MODE\0"
257 "AMDGPUISD::DIV_FIXUP\0"
258 "AMDGPUISD::DIV_FMAS\0"
259 "AMDGPUISD::DIV_SCALE\0"
260 "AMDGPUISD::DS_ORDERED_COUNT\0"
261 "AMDGPUISD::DWORDADDR\0"
262 "AMDGPUISD::ELSE\0"
263 "AMDGPUISD::ENDPGM\0"
264 "AMDGPUISD::ENDPGM_TRAP\0"
265 "AMDGPUISD::EXP\0"
266 "AMDGPUISD::FDOT2\0"
267 "AMDGPUISD::FFBH_U32\0"
268 "AMDGPUISD::FFBL_B32\0"
269 "AMDGPUISD::FLAT_LOAD_MONITOR\0"
270 "AMDGPUISD::FMAD_FTZ\0"
271 "AMDGPUISD::FMAX3\0"
272 "AMDGPUISD::FMAXIMUM3\0"
273 "AMDGPUISD::FMAX_LEGACY\0"
274 "AMDGPUISD::FMA_W_CHAIN\0"
275 "AMDGPUISD::FMED3\0"
276 "AMDGPUISD::FMIN3\0"
277 "AMDGPUISD::FMINIMUM3\0"
278 "AMDGPUISD::FMIN_LEGACY\0"
279 "AMDGPUISD::FMUL_LEGACY\0"
280 "AMDGPUISD::FMUL_W_CHAIN\0"
281 "AMDGPUISD::FP_CLASS\0"
282 "AMDGPUISD::FP_TO_FP16\0"
283 "AMDGPUISD::FRACT\0"
284 "AMDGPUISD::GLOBAL_LOAD_MONITOR\0"
285 "AMDGPUISD::IF\0"
286 "AMDGPUISD::LDS\0"
287 "AMDGPUISD::LOAD_D16_HI\0"
288 "AMDGPUISD::LOAD_D16_HI_I8\0"
289 "AMDGPUISD::LOAD_D16_HI_U8\0"
290 "AMDGPUISD::LOAD_D16_LO\0"
291 "AMDGPUISD::LOAD_D16_LO_I8\0"
292 "AMDGPUISD::LOAD_D16_LO_U8\0"
293 "AMDGPUISD::LOG\0"
294 "AMDGPUISD::LOOP\0"
295 "AMDGPUISD::MAD_I24\0"
296 "AMDGPUISD::MAD_U24\0"
297 "AMDGPUISD::MULHI_I24\0"
298 "AMDGPUISD::MULHI_U24\0"
299 "AMDGPUISD::MUL_I24\0"
300 "AMDGPUISD::MUL_U24\0"
301 "AMDGPUISD::PC_ADD_REL_OFFSET\0"
302 "AMDGPUISD::PC_ADD_REL_OFFSET64\0"
303 "AMDGPUISD::PERM\0"
304 "AMDGPUISD::RCP\0"
305 "AMDGPUISD::RCP_IFLAG\0"
306 "AMDGPUISD::RCP_LEGACY\0"
307 "AMDGPUISD::REGISTER_LOAD\0"
308 "AMDGPUISD::REGISTER_STORE\0"
309 "AMDGPUISD::RETURN_TO_EPILOG\0"
310 "AMDGPUISD::RET_GLUE\0"
311 "AMDGPUISD::RSQ\0"
312 "AMDGPUISD::RSQ_CLAMP\0"
313 "AMDGPUISD::SBUFFER_LOAD\0"
314 "AMDGPUISD::SBUFFER_LOAD_BYTE\0"
315 "AMDGPUISD::SBUFFER_LOAD_SHORT\0"
316 "AMDGPUISD::SBUFFER_LOAD_UBYTE\0"
317 "AMDGPUISD::SBUFFER_LOAD_USHORT\0"
318 "AMDGPUISD::SBUFFER_PREFETCH_DATA\0"
319 "AMDGPUISD::SETCC\0"
320 "AMDGPUISD::SIMULATED_TRAP\0"
321 "AMDGPUISD::SIN_HW\0"
322 "AMDGPUISD::SMAX3\0"
323 "AMDGPUISD::SMED3\0"
324 "AMDGPUISD::SMIN3\0"
325 "AMDGPUISD::STORE_MSKOR\0"
326 "AMDGPUISD::TBUFFER_LOAD_FORMAT\0"
327 "AMDGPUISD::TBUFFER_LOAD_FORMAT_D16\0"
328 "AMDGPUISD::TBUFFER_STORE_FORMAT\0"
329 "AMDGPUISD::TBUFFER_STORE_FORMAT_D16\0"
330 "AMDGPUISD::TC_RETURN\0"
331 "AMDGPUISD::TC_RETURN_CHAIN\0"
332 "AMDGPUISD::TC_RETURN_CHAIN_DVGPR\0"
333 "AMDGPUISD::TC_RETURN_GFX\0"
334 "AMDGPUISD::TC_RETURN_GFX_WholeWave\0"
335 "AMDGPUISD::TRAP\0"
336 "AMDGPUISD::UMAX3\0"
337 "AMDGPUISD::UMED3\0"
338 "AMDGPUISD::UMIN3\0"
339 "AMDGPUISD::URECIP\0"
340 "AMDGPUISD::WHOLE_WAVE_RETURN\0"
341 "AMDGPUISD::WHOLE_WAVE_SETUP\0"
342 ;
343#ifdef __GNUC__
344#pragma GCC diagnostic pop
345#endif
346
347static constexpr llvm::StringTable
348AMDGPUSDNodeNames = AMDGPUSDNodeNamesStorage;
349
350static const VTByHwModePair AMDGPUVTByHwModeTable[] = {
351 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
352};
353
354static const SDTypeConstraint AMDGPUSDTypeConstraints[] = {
355 /* 0 */ {SDTCisVT, 0, 0, 0, MVT::Other},
356 /* 1 */ {SDTCisVT, 1, 0, 0, MVT::Other}, {SDTCisVT, 0, 0, 0, MVT::i1},
357 /* 3 */ {SDTCisVT, 2, 0, 0, MVT::Other}, {SDTCisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 0, 0, 0, MVT::i1},
358 /* 6 */ {SDTCisVT, 1, 0, 0, MVT::v2f16}, {SDTCisVT, 0, 0, 0, MVT::i16},
359 /* 8 */ {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::i32},
360 /* 10 */ {SDTCisVT, 2, 0, 0, MVT::i16}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
361 /* 13 */ {SDTCisVT, 4, 0, 0, MVT::i1}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::f32}, {SDTCisVT, 1, 0, 0, MVT::f32}, {SDTCisVT, 0, 0, 0, MVT::i32},
362 /* 18 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::f32},
363 /* 21 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::v4i32},
364 /* 24 */ {SDTCisVT, 1, 0, 0, MVT::i16}, {SDTCisVT, 0, 0, 0, MVT::v2f16},
365 /* 26 */ {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::v2f32},
366 /* 28 */ {SDTCisVT, 0, 0, 0, MVT::iPTR}, {SDTCisVT, 0, 0, 0, MVT::iPTR},
367 /* 30 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::iPTR},
368 /* 33 */ {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
369 /* 34 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
370 /* 37 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
371 /* 40 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
372 /* 43 */ {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
373 /* 46 */ {SDTCisInt, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
374 /* 51 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
375 /* 56 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
376 /* 59 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
377 /* 61 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
378 /* 63 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
379 /* 67 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
380 /* 70 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
381 /* 74 */ {SDTCisInt, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
382 /* 79 */ {SDTCisVT, 7, 0, 0, MVT::i1}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::v4i32},
383 /* 86 */ {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::v4i32},
384 /* 94 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
385 /* 96 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
386 /* 98 */ {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
387 /* 100 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
388 /* 102 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
389 /* 104 */ {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::v4i32},
390 /* 111 */ {SDTCisVT, 9, 0, 0, MVT::i1}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::v4i32},
391};
392
393static const SDNodeDesc AMDGPUSDNodeDescs[] = {
394 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1, 98, 2}, // ATOMIC_CMP_SWAP
395 {1, 3, 0, 0, 0, 28, 63, 4}, // BFE_I32
396 {1, 3, 0, 0, 0, 47, 63, 4}, // BFE_U32
397 {1, 3, 0, 0, 0, 66, 63, 4}, // BFI
398 {1, 2, 0, 0, 0, 81, 64, 3}, // BORROW
399 {0, 2, 0|1<<SDNPHasChain, 0, 0, 99, 0, 1}, // BRANCH_COND
400 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 122, 104, 7}, // BUFFER_ATOMIC_ADD
401 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 151, 104, 7}, // BUFFER_ATOMIC_AND
402 {1, 9, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 180, 111, 7}, // BUFFER_ATOMIC_CMPSWAP
403 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 213, 104, 7}, // BUFFER_ATOMIC_COND_SUB_U32
404 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 251, 104, 7}, // BUFFER_ATOMIC_CSUB
405 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 281, 104, 7}, // BUFFER_ATOMIC_DEC
406 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 310, 104, 7}, // BUFFER_ATOMIC_FADD
407 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 340, 104, 7}, // BUFFER_ATOMIC_FMAX
408 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 370, 104, 7}, // BUFFER_ATOMIC_FMIN
409 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 400, 104, 7}, // BUFFER_ATOMIC_INC
410 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 429, 104, 7}, // BUFFER_ATOMIC_OR
411 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 457, 104, 7}, // BUFFER_ATOMIC_SMAX
412 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 487, 104, 7}, // BUFFER_ATOMIC_SMIN
413 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 517, 104, 7}, // BUFFER_ATOMIC_SUB
414 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 546, 104, 7}, // BUFFER_ATOMIC_SWAP
415 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 576, 104, 7}, // BUFFER_ATOMIC_UMAX
416 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 606, 104, 7}, // BUFFER_ATOMIC_UMIN
417 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 636, 104, 7}, // BUFFER_ATOMIC_XOR
418 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 665, 79, 7}, // BUFFER_LOAD
419 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 688, 79, 7}, // BUFFER_LOAD_BYTE
420 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 716, 79, 7}, // BUFFER_LOAD_BYTE_TFE
421 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 748, 79, 7}, // BUFFER_LOAD_FORMAT
422 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 778, 79, 7}, // BUFFER_LOAD_FORMAT_D16
423 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 812, 79, 7}, // BUFFER_LOAD_FORMAT_D16_TFE
424 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 850, 79, 7}, // BUFFER_LOAD_FORMAT_TFE
425 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 884, 79, 7}, // BUFFER_LOAD_SHORT
426 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 913, 79, 7}, // BUFFER_LOAD_SHORT_TFE
427 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 946, 79, 7}, // BUFFER_LOAD_TFE
428 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 973, 79, 7}, // BUFFER_LOAD_UBYTE
429 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1002, 79, 7}, // BUFFER_LOAD_UBYTE_TFE
430 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1035, 79, 7}, // BUFFER_LOAD_USHORT
431 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1065, 79, 7}, // BUFFER_LOAD_USHORT_TFE
432 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1099, 79, 7}, // BUFFER_STORE
433 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1123, 79, 7}, // BUFFER_STORE_BYTE
434 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1152, 79, 7}, // BUFFER_STORE_FORMAT
435 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1183, 79, 7}, // BUFFER_STORE_FORMAT_D16
436 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1218, 79, 7}, // BUFFER_STORE_SHORT
437 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 1248, 33, 1}, // CALL
438 {1, 2, 0, 0, 0, 1264, 64, 3}, // CARRY
439 {1, 1, 0, 0, 0, 1281, 61, 2}, // CLAMP
440 {1, 1, 0, 0, 0, 1298, 28, 2}, // CONST_DATA_PTR
441 {1, 1, 0, 0, 0, 1324, 61, 2}, // COS_HW
442 {1, 2, 0, 0, 0, 1342, 18, 3}, // CVT_F32_FP8_E5M3
443 {1, 1, 0, 0, 0, 1370, 56, 3}, // CVT_F32_UBYTE0
444 {1, 1, 0, 0, 0, 1396, 56, 3}, // CVT_F32_UBYTE1
445 {1, 1, 0, 0, 0, 1422, 56, 3}, // CVT_F32_UBYTE2
446 {1, 1, 0, 0, 0, 1448, 56, 3}, // CVT_F32_UBYTE3
447 {1, 2, 0, 0, 0, 1474, 102, 2}, // CVT_PKNORM_I16_F32
448 {1, 2, 0, 0, 0, 1504, 102, 2}, // CVT_PKNORM_U16_F32
449 {1, 2, 0, 0, 0, 1534, 102, 2}, // CVT_PKRTZ_F16_F32
450 {1, 1, 0, 0, 0, 1563, 6, 2}, // CVT_PK_BF8_F16
451 {1, 4, 0, 0, 0, 1589, 13, 5}, // CVT_PK_BF8_F32
452 {1, 1, 0, 0, 0, 1615, 24, 2}, // CVT_PK_F16_BF8
453 {1, 1, 0, 0, 0, 1641, 24, 2}, // CVT_PK_F16_FP8
454 {1, 1, 0, 0, 0, 1667, 26, 2}, // CVT_PK_F32_BF8
455 {1, 1, 0, 0, 0, 1693, 26, 2}, // CVT_PK_F32_FP8
456 {1, 1, 0, 0, 0, 1719, 6, 2}, // CVT_PK_FP8_F16
457 {1, 4, 0, 0, 0, 1745, 13, 5}, // CVT_PK_FP8_F32
458 {1, 4, 0, 0, 0, 1771, 13, 5}, // CVT_PK_FP8_F32_E5M3
459 {1, 2, 0, 0, 0, 1802, 100, 2}, // CVT_PK_I16_I32
460 {1, 2, 0, 0, 0, 1828, 100, 2}, // CVT_PK_U16_U32
461 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 1854, 36, 1}, // DENORM_MODE
462 {1, 3, 0, 0, 0, 1877, 70, 4}, // DIV_FIXUP
463 {1, 4, 0|1<<SDNPOptInGlue, 0, 0, 1898, 46, 5}, // DIV_FMAS
464 {2, 3, 0, 0, 0, 1918, 51, 5}, // DIV_SCALE
465 {1, 2, 0|1<<SDNPHasChain|1<<SDNPInGlue|1<<SDNPMemOperand, 0, 0, 1939, 10, 3}, // DS_ORDERED_COUNT
466 {1, 1, 0, 0, 0, 1967, 59, 2}, // DWORDADDR
467 {1, 2, 0|1<<SDNPHasChain, 0, 0, 1988, 3, 3}, // ELSE
468 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue, 0, 0, 2004, 0, 0}, // ENDPGM
469 {0, 0, 0|1<<SDNPHasChain, 0, 0, 2022, 0, 0}, // ENDPGM_TRAP
470 {1, 1, 0, 0, 0, 2045, 61, 2}, // EXP
471 {1, 4, 0, 0, 0, 2060, 74, 5}, // FDOT2
472 {1, 1, 0, 0, 0, 2077, 34, 3}, // FFBH_U32
473 {1, 1, 0, 0, 0, 2097, 34, 3}, // FFBL_B32
474 {1, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2117, 95, 1}, // FLAT_LOAD_MONITOR
475 {1, 3, 0, 0, 0, 2146, 70, 4}, // FMAD_FTZ
476 {1, 3, 0, 0, 0, 2166, 70, 4}, // FMAX3
477 {1, 3, 0, 0, 0, 2183, 70, 4}, // FMAXIMUM3
478 {1, 2, 0, 0, 0, 2204, 67, 3}, // FMAX_LEGACY
479 {1, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 2227, 70, 4}, // FMA_W_CHAIN
480 {1, 3, 0, 0, 0, 2250, 70, 4}, // FMED3
481 {1, 3, 0, 0, 0, 2267, 70, 4}, // FMIN3
482 {1, 3, 0, 0, 0, 2284, 70, 4}, // FMINIMUM3
483 {1, 2, 0, 0, 0, 2305, 67, 3}, // FMIN_LEGACY
484 {1, 2, 0, 0, 0, 2328, 67, 3}, // FMUL_LEGACY
485 {1, 2, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 2351, 67, 3}, // FMUL_W_CHAIN
486 {1, 2, 0, 0, 0, 2375, 40, 3}, // FP_CLASS
487 {1, 1, 0, 0, 0, 2395, 37, 3}, // FP_TO_FP16
488 {1, 1, 0, 0, 0, 2417, 61, 2}, // FRACT
489 {1, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2434, 95, 1}, // GLOBAL_LOAD_MONITOR
490 {1, 2, 0|1<<SDNPHasChain, 0, 0, 2465, 3, 3}, // IF
491 {1, 1, 0, 0, 0, 2479, 8, 2}, // LDS
492 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2494, 94, 2}, // LOAD_D16_HI
493 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2517, 94, 2}, // LOAD_D16_HI_I8
494 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2543, 94, 2}, // LOAD_D16_HI_U8
495 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2569, 94, 2}, // LOAD_D16_LO
496 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2592, 94, 2}, // LOAD_D16_LO_I8
497 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2618, 94, 2}, // LOAD_D16_LO_U8
498 {1, 1, 0, 0, 0, 2644, 61, 2}, // LOG
499 {0, 2, 0|1<<SDNPHasChain, 0, 0, 2659, 1, 2}, // LOOP
500 {1, 3, 0, 0, 0, 2675, 63, 4}, // MAD_I24
501 {1, 3, 0, 0, 0, 2694, 63, 4}, // MAD_U24
502 {1, 2, 0, 0, 0, 2713, 64, 3}, // MULHI_I24
503 {1, 2, 0, 0, 0, 2734, 64, 3}, // MULHI_U24
504 {1, 2, 0, 0, 0, 2755, 0, 0}, // MUL_I24
505 {1, 2, 0, 0, 0, 2774, 0, 0}, // MUL_U24
506 {1, 2, 0, 0, 0, 2793, 30, 3}, // PC_ADD_REL_OFFSET
507 {1, 1, 0, 0, 0, 2822, 31, 2}, // PC_ADD_REL_OFFSET64
508 {1, 3, 0, 0, 0, 2853, 63, 4}, // PERM
509 {1, 1, 0, 0, 0, 2869, 61, 2}, // RCP
510 {1, 1, 0, 0, 0, 2884, 61, 2}, // RCP_IFLAG
511 {1, 1, 0, 0, 0, 2905, 61, 2}, // RCP_LEGACY
512 {1, 2, 0|1<<SDNPHasChain, 0, 0, 2927, 96, 2}, // REGISTER_LOAD
513 {0, 3, 0|1<<SDNPHasChain, 0, 0, 2952, 96, 2}, // REGISTER_STORE
514 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 2978, 0, 0}, // RETURN_TO_EPILOG
515 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3006, 0, 0}, // RET_GLUE
516 {1, 1, 0, 0, 0, 3026, 61, 2}, // RSQ
517 {1, 1, 0, 0, 0, 3041, 61, 2}, // RSQ_CLAMP
518 {1, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3062, 83, 3}, // SBUFFER_LOAD
519 {1, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3086, 83, 3}, // SBUFFER_LOAD_BYTE
520 {1, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3115, 83, 3}, // SBUFFER_LOAD_SHORT
521 {1, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3145, 83, 3}, // SBUFFER_LOAD_UBYTE
522 {1, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3175, 83, 3}, // SBUFFER_LOAD_USHORT
523 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3206, 21, 3}, // SBUFFER_PREFETCH_DATA
524 {1, 3, 0, 0, 0, 3239, 43, 3}, // SETCC
525 {0, 0, 0|1<<SDNPHasChain, 0, 0, 3256, 0, 0}, // SIMULATED_TRAP
526 {1, 1, 0, 0, 0, 3282, 61, 2}, // SIN_HW
527 {1, 3, 0, 0, 0, 3300, 63, 4}, // SMAX3
528 {1, 3, 0, 0, 0, 3317, 63, 4}, // SMED3
529 {1, 3, 0, 0, 0, 3334, 63, 4}, // SMIN3
530 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3351, 0, 0}, // STORE_MSKOR
531 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3374, 86, 8}, // TBUFFER_LOAD_FORMAT
532 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3405, 86, 8}, // TBUFFER_LOAD_FORMAT_D16
533 {0, 9, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3440, 86, 8}, // TBUFFER_STORE_FORMAT
534 {0, 9, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3472, 86, 8}, // TBUFFER_STORE_FORMAT_D16
535 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3508, 33, 1}, // TC_RETURN
536 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3529, 33, 1}, // TC_RETURN_CHAIN
537 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3556, 33, 1}, // TC_RETURN_CHAIN_DVGPR
538 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3589, 33, 1}, // TC_RETURN_GFX
539 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3614, 33, 1}, // TC_RETURN_GFX_WholeWave
540 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3649, 7, 1}, // TRAP
541 {1, 3, 0, 0, 0, 3665, 63, 4}, // UMAX3
542 {1, 3, 0, 0, 0, 3682, 63, 4}, // UMED3
543 {1, 3, 0, 0, 0, 3699, 63, 4}, // UMIN3
544 {1, 1, 0, 0, 0, 3716, 59, 2}, // URECIP
545 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3734, 0, 0}, // WHOLE_WAVE_RETURN
546 {1, 0, 0|1<<SDNPHasChain, 0, 0, 3763, 36, 1}, // WHOLE_WAVE_SETUP
547};
548
549static const SDNodeInfo AMDGPUGenSDNodeInfo(
550 /*NumOpcodes=*/153, AMDGPUSDNodeDescs, AMDGPUSDNodeNames,
551 AMDGPUVTByHwModeTable, AMDGPUSDTypeConstraints);
552
553} // namespace llvm
554
555#endif // GET_SDNODE_DESC
556
557