1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target SDNode descriptions *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* From: AMDGPU.td *|
7|* *|
8\*===----------------------------------------------------------------------===*/
9
10#ifdef GET_SDNODE_ENUM
11#undef GET_SDNODE_ENUM
12
13namespace llvm::AMDGPUISD {
14
15enum GenNodeType : unsigned {
16 ATOMIC_CMP_SWAP = ISD::BUILTIN_OP_END,
17 BFE_I32,
18 BFE_U32,
19 BFI,
20 BFM,
21 BORROW,
22 BRANCH_COND,
23 BUFFER_ATOMIC_ADD,
24 BUFFER_ATOMIC_AND,
25 BUFFER_ATOMIC_CMPSWAP,
26 BUFFER_ATOMIC_COND_SUB_U32,
27 BUFFER_ATOMIC_CSUB,
28 BUFFER_ATOMIC_DEC,
29 BUFFER_ATOMIC_FADD,
30 BUFFER_ATOMIC_FMAX,
31 BUFFER_ATOMIC_FMIN,
32 BUFFER_ATOMIC_INC,
33 BUFFER_ATOMIC_OR,
34 BUFFER_ATOMIC_SMAX,
35 BUFFER_ATOMIC_SMIN,
36 BUFFER_ATOMIC_SUB,
37 BUFFER_ATOMIC_SWAP,
38 BUFFER_ATOMIC_UMAX,
39 BUFFER_ATOMIC_UMIN,
40 BUFFER_ATOMIC_XOR,
41 BUFFER_LOAD,
42 BUFFER_LOAD_BYTE,
43 BUFFER_LOAD_BYTE_TFE,
44 BUFFER_LOAD_FORMAT,
45 BUFFER_LOAD_FORMAT_D16,
46 BUFFER_LOAD_FORMAT_TFE,
47 BUFFER_LOAD_SHORT,
48 BUFFER_LOAD_SHORT_TFE,
49 BUFFER_LOAD_TFE,
50 BUFFER_LOAD_UBYTE,
51 BUFFER_LOAD_UBYTE_TFE,
52 BUFFER_LOAD_USHORT,
53 BUFFER_LOAD_USHORT_TFE,
54 BUFFER_STORE,
55 BUFFER_STORE_BYTE,
56 BUFFER_STORE_FORMAT,
57 BUFFER_STORE_FORMAT_D16,
58 BUFFER_STORE_SHORT,
59 CALL,
60 CARRY,
61 CLAMP,
62 CONST_DATA_PTR,
63 COS_HW,
64 CVT_F32_UBYTE0,
65 CVT_F32_UBYTE1,
66 CVT_F32_UBYTE2,
67 CVT_F32_UBYTE3,
68 CVT_PKNORM_I16_F32,
69 CVT_PKNORM_U16_F32,
70 CVT_PKRTZ_F16_F32,
71 CVT_PK_I16_I32,
72 CVT_PK_U16_U32,
73 DENORM_MODE,
74 DIV_FIXUP,
75 DIV_FMAS,
76 DIV_SCALE,
77 DS_ORDERED_COUNT,
78 DWORDADDR,
79 ELSE,
80 ENDPGM,
81 ENDPGM_TRAP,
82 EXP,
83 FDOT2,
84 FFBH_U32,
85 FFBL_B32,
86 FLAT_LOAD_MONITOR,
87 FMAD_FTZ,
88 FMAX3,
89 FMAXIMUM3,
90 FMAX_LEGACY,
91 FMA_W_CHAIN,
92 FMED3,
93 FMIN3,
94 FMINIMUM3,
95 FMIN_LEGACY,
96 FMUL_LEGACY,
97 FMUL_W_CHAIN,
98 FP_CLASS,
99 FP_TO_FP16,
100 FRACT,
101 GLOBAL_LOAD_MONITOR,
102 IF,
103 LDS,
104 LOAD_D16_HI,
105 LOAD_D16_HI_I8,
106 LOAD_D16_HI_U8,
107 LOAD_D16_LO,
108 LOAD_D16_LO_I8,
109 LOAD_D16_LO_U8,
110 LOG,
111 LOOP,
112 MAD_I24,
113 MAD_U24,
114 MULHI_I24,
115 MULHI_U24,
116 MUL_I24,
117 MUL_U24,
118 PC_ADD_REL_OFFSET,
119 PC_ADD_REL_OFFSET64,
120 PERM,
121 RCP,
122 RCP_IFLAG,
123 RCP_LEGACY,
124 REGISTER_LOAD,
125 REGISTER_STORE,
126 RETURN_TO_EPILOG,
127 RET_GLUE,
128 RSQ,
129 RSQ_CLAMP,
130 SBUFFER_LOAD,
131 SBUFFER_LOAD_BYTE,
132 SBUFFER_LOAD_SHORT,
133 SBUFFER_LOAD_UBYTE,
134 SBUFFER_LOAD_USHORT,
135 SBUFFER_PREFETCH_DATA,
136 SETCC,
137 SIMULATED_TRAP,
138 SIN_HW,
139 SMAX3,
140 SMED3,
141 SMIN3,
142 STORE_MSKOR,
143 TBUFFER_LOAD_FORMAT,
144 TBUFFER_LOAD_FORMAT_D16,
145 TBUFFER_STORE_FORMAT,
146 TBUFFER_STORE_FORMAT_D16,
147 TC_RETURN,
148 TC_RETURN_CHAIN,
149 TC_RETURN_CHAIN_DVGPR,
150 TC_RETURN_GFX,
151 TC_RETURN_GFX_WholeWave,
152 TRAP,
153 UMAX3,
154 UMED3,
155 UMIN3,
156 URECIP,
157 WHOLE_WAVE_RETURN,
158 WHOLE_WAVE_SETUP,
159};
160
161static constexpr unsigned GENERATED_OPCODE_END = WHOLE_WAVE_SETUP + 1;
162
163} // namespace llvm::AMDGPUISD
164
165#endif // GET_SDNODE_ENUM
166
167#ifdef GET_SDNODE_DESC
168#undef GET_SDNODE_DESC
169
170namespace llvm {
171
172
173#ifdef __GNUC__
174#pragma GCC diagnostic push
175#pragma GCC diagnostic ignored "-Woverlength-strings"
176#endif
177static constexpr char AMDGPUSDNodeNamesStorage[] =
178 "\0"
179 "AMDGPUISD::ATOMIC_CMP_SWAP\0"
180 "AMDGPUISD::BFE_I32\0"
181 "AMDGPUISD::BFE_U32\0"
182 "AMDGPUISD::BFI\0"
183 "AMDGPUISD::BFM\0"
184 "AMDGPUISD::BORROW\0"
185 "AMDGPUISD::BRANCH_COND\0"
186 "AMDGPUISD::BUFFER_ATOMIC_ADD\0"
187 "AMDGPUISD::BUFFER_ATOMIC_AND\0"
188 "AMDGPUISD::BUFFER_ATOMIC_CMPSWAP\0"
189 "AMDGPUISD::BUFFER_ATOMIC_COND_SUB_U32\0"
190 "AMDGPUISD::BUFFER_ATOMIC_CSUB\0"
191 "AMDGPUISD::BUFFER_ATOMIC_DEC\0"
192 "AMDGPUISD::BUFFER_ATOMIC_FADD\0"
193 "AMDGPUISD::BUFFER_ATOMIC_FMAX\0"
194 "AMDGPUISD::BUFFER_ATOMIC_FMIN\0"
195 "AMDGPUISD::BUFFER_ATOMIC_INC\0"
196 "AMDGPUISD::BUFFER_ATOMIC_OR\0"
197 "AMDGPUISD::BUFFER_ATOMIC_SMAX\0"
198 "AMDGPUISD::BUFFER_ATOMIC_SMIN\0"
199 "AMDGPUISD::BUFFER_ATOMIC_SUB\0"
200 "AMDGPUISD::BUFFER_ATOMIC_SWAP\0"
201 "AMDGPUISD::BUFFER_ATOMIC_UMAX\0"
202 "AMDGPUISD::BUFFER_ATOMIC_UMIN\0"
203 "AMDGPUISD::BUFFER_ATOMIC_XOR\0"
204 "AMDGPUISD::BUFFER_LOAD\0"
205 "AMDGPUISD::BUFFER_LOAD_BYTE\0"
206 "AMDGPUISD::BUFFER_LOAD_BYTE_TFE\0"
207 "AMDGPUISD::BUFFER_LOAD_FORMAT\0"
208 "AMDGPUISD::BUFFER_LOAD_FORMAT_D16\0"
209 "AMDGPUISD::BUFFER_LOAD_FORMAT_TFE\0"
210 "AMDGPUISD::BUFFER_LOAD_SHORT\0"
211 "AMDGPUISD::BUFFER_LOAD_SHORT_TFE\0"
212 "AMDGPUISD::BUFFER_LOAD_TFE\0"
213 "AMDGPUISD::BUFFER_LOAD_UBYTE\0"
214 "AMDGPUISD::BUFFER_LOAD_UBYTE_TFE\0"
215 "AMDGPUISD::BUFFER_LOAD_USHORT\0"
216 "AMDGPUISD::BUFFER_LOAD_USHORT_TFE\0"
217 "AMDGPUISD::BUFFER_STORE\0"
218 "AMDGPUISD::BUFFER_STORE_BYTE\0"
219 "AMDGPUISD::BUFFER_STORE_FORMAT\0"
220 "AMDGPUISD::BUFFER_STORE_FORMAT_D16\0"
221 "AMDGPUISD::BUFFER_STORE_SHORT\0"
222 "AMDGPUISD::CALL\0"
223 "AMDGPUISD::CARRY\0"
224 "AMDGPUISD::CLAMP\0"
225 "AMDGPUISD::CONST_DATA_PTR\0"
226 "AMDGPUISD::COS_HW\0"
227 "AMDGPUISD::CVT_F32_UBYTE0\0"
228 "AMDGPUISD::CVT_F32_UBYTE1\0"
229 "AMDGPUISD::CVT_F32_UBYTE2\0"
230 "AMDGPUISD::CVT_F32_UBYTE3\0"
231 "AMDGPUISD::CVT_PKNORM_I16_F32\0"
232 "AMDGPUISD::CVT_PKNORM_U16_F32\0"
233 "AMDGPUISD::CVT_PKRTZ_F16_F32\0"
234 "AMDGPUISD::CVT_PK_I16_I32\0"
235 "AMDGPUISD::CVT_PK_U16_U32\0"
236 "AMDGPUISD::DENORM_MODE\0"
237 "AMDGPUISD::DIV_FIXUP\0"
238 "AMDGPUISD::DIV_FMAS\0"
239 "AMDGPUISD::DIV_SCALE\0"
240 "AMDGPUISD::DS_ORDERED_COUNT\0"
241 "AMDGPUISD::DWORDADDR\0"
242 "AMDGPUISD::ELSE\0"
243 "AMDGPUISD::ENDPGM\0"
244 "AMDGPUISD::ENDPGM_TRAP\0"
245 "AMDGPUISD::EXP\0"
246 "AMDGPUISD::FDOT2\0"
247 "AMDGPUISD::FFBH_U32\0"
248 "AMDGPUISD::FFBL_B32\0"
249 "AMDGPUISD::FLAT_LOAD_MONITOR\0"
250 "AMDGPUISD::FMAD_FTZ\0"
251 "AMDGPUISD::FMAX3\0"
252 "AMDGPUISD::FMAXIMUM3\0"
253 "AMDGPUISD::FMAX_LEGACY\0"
254 "AMDGPUISD::FMA_W_CHAIN\0"
255 "AMDGPUISD::FMED3\0"
256 "AMDGPUISD::FMIN3\0"
257 "AMDGPUISD::FMINIMUM3\0"
258 "AMDGPUISD::FMIN_LEGACY\0"
259 "AMDGPUISD::FMUL_LEGACY\0"
260 "AMDGPUISD::FMUL_W_CHAIN\0"
261 "AMDGPUISD::FP_CLASS\0"
262 "AMDGPUISD::FP_TO_FP16\0"
263 "AMDGPUISD::FRACT\0"
264 "AMDGPUISD::GLOBAL_LOAD_MONITOR\0"
265 "AMDGPUISD::IF\0"
266 "AMDGPUISD::LDS\0"
267 "AMDGPUISD::LOAD_D16_HI\0"
268 "AMDGPUISD::LOAD_D16_HI_I8\0"
269 "AMDGPUISD::LOAD_D16_HI_U8\0"
270 "AMDGPUISD::LOAD_D16_LO\0"
271 "AMDGPUISD::LOAD_D16_LO_I8\0"
272 "AMDGPUISD::LOAD_D16_LO_U8\0"
273 "AMDGPUISD::LOG\0"
274 "AMDGPUISD::LOOP\0"
275 "AMDGPUISD::MAD_I24\0"
276 "AMDGPUISD::MAD_U24\0"
277 "AMDGPUISD::MULHI_I24\0"
278 "AMDGPUISD::MULHI_U24\0"
279 "AMDGPUISD::MUL_I24\0"
280 "AMDGPUISD::MUL_U24\0"
281 "AMDGPUISD::PC_ADD_REL_OFFSET\0"
282 "AMDGPUISD::PC_ADD_REL_OFFSET64\0"
283 "AMDGPUISD::PERM\0"
284 "AMDGPUISD::RCP\0"
285 "AMDGPUISD::RCP_IFLAG\0"
286 "AMDGPUISD::RCP_LEGACY\0"
287 "AMDGPUISD::REGISTER_LOAD\0"
288 "AMDGPUISD::REGISTER_STORE\0"
289 "AMDGPUISD::RETURN_TO_EPILOG\0"
290 "AMDGPUISD::RET_GLUE\0"
291 "AMDGPUISD::RSQ\0"
292 "AMDGPUISD::RSQ_CLAMP\0"
293 "AMDGPUISD::SBUFFER_LOAD\0"
294 "AMDGPUISD::SBUFFER_LOAD_BYTE\0"
295 "AMDGPUISD::SBUFFER_LOAD_SHORT\0"
296 "AMDGPUISD::SBUFFER_LOAD_UBYTE\0"
297 "AMDGPUISD::SBUFFER_LOAD_USHORT\0"
298 "AMDGPUISD::SBUFFER_PREFETCH_DATA\0"
299 "AMDGPUISD::SETCC\0"
300 "AMDGPUISD::SIMULATED_TRAP\0"
301 "AMDGPUISD::SIN_HW\0"
302 "AMDGPUISD::SMAX3\0"
303 "AMDGPUISD::SMED3\0"
304 "AMDGPUISD::SMIN3\0"
305 "AMDGPUISD::STORE_MSKOR\0"
306 "AMDGPUISD::TBUFFER_LOAD_FORMAT\0"
307 "AMDGPUISD::TBUFFER_LOAD_FORMAT_D16\0"
308 "AMDGPUISD::TBUFFER_STORE_FORMAT\0"
309 "AMDGPUISD::TBUFFER_STORE_FORMAT_D16\0"
310 "AMDGPUISD::TC_RETURN\0"
311 "AMDGPUISD::TC_RETURN_CHAIN\0"
312 "AMDGPUISD::TC_RETURN_CHAIN_DVGPR\0"
313 "AMDGPUISD::TC_RETURN_GFX\0"
314 "AMDGPUISD::TC_RETURN_GFX_WholeWave\0"
315 "AMDGPUISD::TRAP\0"
316 "AMDGPUISD::UMAX3\0"
317 "AMDGPUISD::UMED3\0"
318 "AMDGPUISD::UMIN3\0"
319 "AMDGPUISD::URECIP\0"
320 "AMDGPUISD::WHOLE_WAVE_RETURN\0"
321 "AMDGPUISD::WHOLE_WAVE_SETUP\0"
322 ;
323#ifdef __GNUC__
324#pragma GCC diagnostic pop
325#endif
326
327static constexpr llvm::StringTable
328AMDGPUSDNodeNames = AMDGPUSDNodeNamesStorage;
329
330static const VTByHwModePair AMDGPUVTByHwModeTable[] = {
331 /* dummy */ {0, MVT::INVALID_SIMPLE_VALUE_TYPE}
332};
333
334static const SDTypeConstraint AMDGPUSDTypeConstraints[] = {
335 /* 0 */ {SDTCisVT, 0, 0, 0, MVT::Other},
336 /* 1 */ {SDTCisVT, 1, 0, 0, MVT::Other}, {SDTCisVT, 0, 0, 0, MVT::i1},
337 /* 3 */ {SDTCisVT, 2, 0, 0, MVT::Other}, {SDTCisVT, 1, 0, 0, MVT::i1}, {SDTCisVT, 0, 0, 0, MVT::i1},
338 /* 6 */ {SDTCisVT, 0, 0, 0, MVT::i16},
339 /* 7 */ {SDTCisVT, 2, 0, 0, MVT::i16}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::i32},
340 /* 10 */ {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::i32}, {SDTCisVT, 0, 0, 0, MVT::v4i32},
341 /* 13 */ {SDTCisVT, 0, 0, 0, MVT::iPTR}, {SDTCisVT, 0, 0, 0, MVT::iPTR},
342 /* 15 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVT, 0, 0, 0, MVT::iPTR},
343 /* 18 */ {SDTCisPtrTy, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
344 /* 19 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
345 /* 22 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
346 /* 25 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
347 /* 28 */ {SDTCisVT, 3, 0, 0, MVT::Other}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
348 /* 31 */ {SDTCisInt, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
349 /* 36 */ {SDTCisSameAs, 0, 4, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
350 /* 41 */ {SDTCisSameNumEltsAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
351 /* 44 */ {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
352 /* 46 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
353 /* 48 */ {SDTCisInt, 3, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
354 /* 52 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
355 /* 55 */ {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 1, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
356 /* 59 */ {SDTCisInt, 4, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisVec, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 0, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisSameAs, 0, 3, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
357 /* 64 */ {SDTCisVT, 7, 0, 0, MVT::i1}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::v4i32},
358 /* 71 */ {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::i32}, {SDTCisVT, 1, 0, 0, MVT::v4i32},
359 /* 79 */ {SDTCisSameAs, 0, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
360 /* 81 */ {SDTCisInt, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
361 /* 83 */ {SDTCisVec, 2, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisPtrTy, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
362 /* 85 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisInt, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
363 /* 87 */ {SDTCisSameAs, 1, 2, 0, MVT::INVALID_SIMPLE_VALUE_TYPE}, {SDTCisFP, 1, 0, 0, MVT::INVALID_SIMPLE_VALUE_TYPE},
364 /* 89 */ {SDTCisVT, 8, 0, 0, MVT::i1}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::i32}, {SDTCisVT, 2, 0, 0, MVT::v4i32},
365 /* 96 */ {SDTCisVT, 9, 0, 0, MVT::i1}, {SDTCisVT, 8, 0, 0, MVT::i32}, {SDTCisVT, 7, 0, 0, MVT::i32}, {SDTCisVT, 6, 0, 0, MVT::i32}, {SDTCisVT, 5, 0, 0, MVT::i32}, {SDTCisVT, 4, 0, 0, MVT::i32}, {SDTCisVT, 3, 0, 0, MVT::v4i32},
366};
367
368static const SDNodeDesc AMDGPUSDNodeDescs[] = {
369 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1, 83, 2}, // ATOMIC_CMP_SWAP
370 {1, 3, 0, 0, 0, 28, 48, 4}, // BFE_I32
371 {1, 3, 0, 0, 0, 47, 48, 4}, // BFE_U32
372 {1, 3, 0, 0, 0, 66, 48, 4}, // BFI
373 {1, 2, 0, 0, 0, 81, 49, 3}, // BFM
374 {1, 2, 0, 0, 0, 96, 49, 3}, // BORROW
375 {0, 2, 0|1<<SDNPHasChain, 0, 0, 114, 0, 1}, // BRANCH_COND
376 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 137, 89, 7}, // BUFFER_ATOMIC_ADD
377 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 166, 89, 7}, // BUFFER_ATOMIC_AND
378 {1, 9, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 195, 96, 7}, // BUFFER_ATOMIC_CMPSWAP
379 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 228, 89, 7}, // BUFFER_ATOMIC_COND_SUB_U32
380 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 266, 89, 7}, // BUFFER_ATOMIC_CSUB
381 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 296, 89, 7}, // BUFFER_ATOMIC_DEC
382 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 325, 89, 7}, // BUFFER_ATOMIC_FADD
383 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 355, 89, 7}, // BUFFER_ATOMIC_FMAX
384 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 385, 89, 7}, // BUFFER_ATOMIC_FMIN
385 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 415, 89, 7}, // BUFFER_ATOMIC_INC
386 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 444, 89, 7}, // BUFFER_ATOMIC_OR
387 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 472, 89, 7}, // BUFFER_ATOMIC_SMAX
388 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 502, 89, 7}, // BUFFER_ATOMIC_SMIN
389 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 532, 89, 7}, // BUFFER_ATOMIC_SUB
390 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 561, 89, 7}, // BUFFER_ATOMIC_SWAP
391 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 591, 89, 7}, // BUFFER_ATOMIC_UMAX
392 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 621, 89, 7}, // BUFFER_ATOMIC_UMIN
393 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 651, 89, 7}, // BUFFER_ATOMIC_XOR
394 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 680, 64, 7}, // BUFFER_LOAD
395 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 703, 64, 7}, // BUFFER_LOAD_BYTE
396 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 731, 64, 7}, // BUFFER_LOAD_BYTE_TFE
397 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 763, 64, 7}, // BUFFER_LOAD_FORMAT
398 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 793, 64, 7}, // BUFFER_LOAD_FORMAT_D16
399 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 827, 64, 7}, // BUFFER_LOAD_FORMAT_TFE
400 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 861, 64, 7}, // BUFFER_LOAD_SHORT
401 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 890, 64, 7}, // BUFFER_LOAD_SHORT_TFE
402 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 923, 64, 7}, // BUFFER_LOAD_TFE
403 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 950, 64, 7}, // BUFFER_LOAD_UBYTE
404 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 979, 64, 7}, // BUFFER_LOAD_UBYTE_TFE
405 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1012, 64, 7}, // BUFFER_LOAD_USHORT
406 {1, 7, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1042, 64, 7}, // BUFFER_LOAD_USHORT_TFE
407 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1076, 64, 7}, // BUFFER_STORE
408 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1100, 64, 7}, // BUFFER_STORE_BYTE
409 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1129, 64, 7}, // BUFFER_STORE_FORMAT
410 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1160, 64, 7}, // BUFFER_STORE_FORMAT_D16
411 {0, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1195, 64, 7}, // BUFFER_STORE_SHORT
412 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 1225, 18, 1}, // CALL
413 {1, 2, 0, 0, 0, 1241, 49, 3}, // CARRY
414 {1, 1, 0, 0, 0, 1258, 46, 2}, // CLAMP
415 {1, 1, 0, 0, 0, 1275, 13, 2}, // CONST_DATA_PTR
416 {1, 1, 0, 0, 0, 1301, 46, 2}, // COS_HW
417 {1, 1, 0, 0, 0, 1319, 41, 3}, // CVT_F32_UBYTE0
418 {1, 1, 0, 0, 0, 1345, 41, 3}, // CVT_F32_UBYTE1
419 {1, 1, 0, 0, 0, 1371, 41, 3}, // CVT_F32_UBYTE2
420 {1, 1, 0, 0, 0, 1397, 41, 3}, // CVT_F32_UBYTE3
421 {1, 2, 0, 0, 0, 1423, 87, 2}, // CVT_PKNORM_I16_F32
422 {1, 2, 0, 0, 0, 1453, 87, 2}, // CVT_PKNORM_U16_F32
423 {1, 2, 0, 0, 0, 1483, 87, 2}, // CVT_PKRTZ_F16_F32
424 {1, 2, 0, 0, 0, 1512, 85, 2}, // CVT_PK_I16_I32
425 {1, 2, 0, 0, 0, 1538, 85, 2}, // CVT_PK_U16_U32
426 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 1564, 21, 1}, // DENORM_MODE
427 {1, 3, 0, 0, 0, 1587, 55, 4}, // DIV_FIXUP
428 {1, 4, 0|1<<SDNPOptInGlue, 0, 0, 1608, 31, 5}, // DIV_FMAS
429 {2, 3, 0, 0, 0, 1628, 36, 5}, // DIV_SCALE
430 {1, 2, 0|1<<SDNPHasChain|1<<SDNPInGlue|1<<SDNPMemOperand, 0, 0, 1649, 7, 3}, // DS_ORDERED_COUNT
431 {1, 1, 0, 0, 0, 1677, 44, 2}, // DWORDADDR
432 {1, 2, 0|1<<SDNPHasChain, 0, 0, 1698, 3, 3}, // ELSE
433 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue, 0, 0, 1714, 0, 0}, // ENDPGM
434 {0, 0, 0|1<<SDNPHasChain, 0, 0, 1732, 0, 0}, // ENDPGM_TRAP
435 {1, 1, 0, 0, 0, 1755, 46, 2}, // EXP
436 {1, 4, 0, 0, 0, 1770, 59, 5}, // FDOT2
437 {1, 1, 0, 0, 0, 1787, 19, 3}, // FFBH_U32
438 {1, 1, 0, 0, 0, 1807, 19, 3}, // FFBL_B32
439 {1, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 1827, 80, 1}, // FLAT_LOAD_MONITOR
440 {1, 3, 0, 0, 0, 1856, 55, 4}, // FMAD_FTZ
441 {1, 3, 0, 0, 0, 1876, 55, 4}, // FMAX3
442 {1, 3, 0, 0, 0, 1893, 55, 4}, // FMAXIMUM3
443 {1, 2, 0, 0, 0, 1914, 52, 3}, // FMAX_LEGACY
444 {1, 3, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 1937, 55, 4}, // FMA_W_CHAIN
445 {1, 3, 0, 0, 0, 1960, 55, 4}, // FMED3
446 {1, 3, 0, 0, 0, 1977, 55, 4}, // FMIN3
447 {1, 3, 0, 0, 0, 1994, 55, 4}, // FMINIMUM3
448 {1, 2, 0, 0, 0, 2015, 52, 3}, // FMIN_LEGACY
449 {1, 2, 0, 0, 0, 2038, 52, 3}, // FMUL_LEGACY
450 {1, 2, 0|1<<SDNPHasChain|1<<SDNPOutGlue|1<<SDNPOptInGlue, 0, 0, 2061, 52, 3}, // FMUL_W_CHAIN
451 {1, 2, 0, 0, 0, 2085, 25, 3}, // FP_CLASS
452 {1, 1, 0, 0, 0, 2105, 22, 3}, // FP_TO_FP16
453 {1, 1, 0, 0, 0, 2127, 46, 2}, // FRACT
454 {1, 1, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2144, 80, 1}, // GLOBAL_LOAD_MONITOR
455 {1, 2, 0|1<<SDNPHasChain, 0, 0, 2175, 3, 3}, // IF
456 {1, 1, 0, 0, 0, 2189, 16, 2}, // LDS
457 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2204, 79, 2}, // LOAD_D16_HI
458 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2227, 79, 2}, // LOAD_D16_HI_I8
459 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2253, 79, 2}, // LOAD_D16_HI_U8
460 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2279, 79, 2}, // LOAD_D16_LO
461 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2302, 79, 2}, // LOAD_D16_LO_I8
462 {1, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2328, 79, 2}, // LOAD_D16_LO_U8
463 {1, 1, 0, 0, 0, 2354, 46, 2}, // LOG
464 {0, 2, 0|1<<SDNPHasChain, 0, 0, 2369, 1, 2}, // LOOP
465 {1, 3, 0, 0, 0, 2385, 48, 4}, // MAD_I24
466 {1, 3, 0, 0, 0, 2404, 48, 4}, // MAD_U24
467 {1, 2, 0, 0, 0, 2423, 49, 3}, // MULHI_I24
468 {1, 2, 0, 0, 0, 2444, 49, 3}, // MULHI_U24
469 {1, 2, 0, 0, 0, 2465, 0, 0}, // MUL_I24
470 {1, 2, 0, 0, 0, 2484, 0, 0}, // MUL_U24
471 {1, 2, 0, 0, 0, 2503, 15, 3}, // PC_ADD_REL_OFFSET
472 {1, 1, 0, 0, 0, 2532, 16, 2}, // PC_ADD_REL_OFFSET64
473 {1, 3, 0, 0, 0, 2563, 48, 4}, // PERM
474 {1, 1, 0, 0, 0, 2579, 46, 2}, // RCP
475 {1, 1, 0, 0, 0, 2594, 46, 2}, // RCP_IFLAG
476 {1, 1, 0, 0, 0, 2615, 46, 2}, // RCP_LEGACY
477 {1, 2, 0|1<<SDNPHasChain, 0, 0, 2637, 81, 2}, // REGISTER_LOAD
478 {0, 3, 0|1<<SDNPHasChain, 0, 0, 2662, 81, 2}, // REGISTER_STORE
479 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 2688, 0, 0}, // RETURN_TO_EPILOG
480 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 2716, 0, 0}, // RET_GLUE
481 {1, 1, 0, 0, 0, 2736, 46, 2}, // RSQ
482 {1, 1, 0, 0, 0, 2751, 46, 2}, // RSQ_CLAMP
483 {1, 3, 0|1<<SDNPMemOperand, 0, 0, 2772, 68, 3}, // SBUFFER_LOAD
484 {1, 3, 0|1<<SDNPMemOperand, 0, 0, 2796, 68, 3}, // SBUFFER_LOAD_BYTE
485 {1, 3, 0|1<<SDNPMemOperand, 0, 0, 2825, 68, 3}, // SBUFFER_LOAD_SHORT
486 {1, 3, 0|1<<SDNPMemOperand, 0, 0, 2855, 68, 3}, // SBUFFER_LOAD_UBYTE
487 {1, 3, 0|1<<SDNPMemOperand, 0, 0, 2885, 68, 3}, // SBUFFER_LOAD_USHORT
488 {0, 3, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 2916, 10, 3}, // SBUFFER_PREFETCH_DATA
489 {1, 3, 0, 0, 0, 2949, 28, 3}, // SETCC
490 {0, 0, 0|1<<SDNPHasChain, 0, 0, 2966, 0, 0}, // SIMULATED_TRAP
491 {1, 1, 0, 0, 0, 2992, 46, 2}, // SIN_HW
492 {1, 3, 0, 0, 0, 3010, 48, 4}, // SMAX3
493 {1, 3, 0, 0, 0, 3027, 48, 4}, // SMED3
494 {1, 3, 0, 0, 0, 3044, 48, 4}, // SMIN3
495 {0, 2, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3061, 0, 0}, // STORE_MSKOR
496 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3084, 71, 8}, // TBUFFER_LOAD_FORMAT
497 {1, 8, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3115, 71, 8}, // TBUFFER_LOAD_FORMAT_D16
498 {0, 9, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3150, 71, 8}, // TBUFFER_STORE_FORMAT
499 {0, 9, 0|1<<SDNPHasChain|1<<SDNPMemOperand, 0, 0, 3182, 71, 8}, // TBUFFER_STORE_FORMAT_D16
500 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3218, 18, 1}, // TC_RETURN
501 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3239, 18, 1}, // TC_RETURN_CHAIN
502 {0, -1, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3266, 18, 1}, // TC_RETURN_CHAIN_DVGPR
503 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3299, 18, 1}, // TC_RETURN_GFX
504 {0, 3, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3324, 18, 1}, // TC_RETURN_GFX_WholeWave
505 {0, 1, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3359, 6, 1}, // TRAP
506 {1, 3, 0, 0, 0, 3375, 48, 4}, // UMAX3
507 {1, 3, 0, 0, 0, 3392, 48, 4}, // UMED3
508 {1, 3, 0, 0, 0, 3409, 48, 4}, // UMIN3
509 {1, 1, 0, 0, 0, 3426, 44, 2}, // URECIP
510 {0, 0, 0|1<<SDNPHasChain|1<<SDNPOptInGlue|1<<SDNPVariadic, 0, 0, 3444, 0, 0}, // WHOLE_WAVE_RETURN
511 {1, 0, 0|1<<SDNPHasChain, 0, 0, 3473, 21, 1}, // WHOLE_WAVE_SETUP
512};
513
514static const SDNodeInfo AMDGPUGenSDNodeInfo(
515 /*NumOpcodes=*/143, AMDGPUSDNodeDescs, AMDGPUSDNodeNames,
516 AMDGPUVTByHwModeTable, AMDGPUSDTypeConstraints);
517
518} // namespace llvm
519
520#endif // GET_SDNODE_DESC
521
522