| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 | |* *| |
| 3 | |* Subtarget Enumeration Source Fragment *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_SUBTARGETINFO_ENUM |
| 10 | #undef GET_SUBTARGETINFO_ENUM |
| 11 | |
| 12 | namespace llvm { |
| 13 | |
| 14 | namespace AMDGPU { |
| 15 | |
| 16 | enum { |
| 17 | Feature16BitInsts = 0, |
| 18 | Feature32BitNumRecordsBufferResource = 1, |
| 19 | Feature45BitNumRecordsBufferResource = 2, |
| 20 | Feature64BitLiterals = 3, |
| 21 | Feature1024AddressableVGPRs = 4, |
| 22 | Feature1536VGPRs = 5, |
| 23 | FeatureA16 = 6, |
| 24 | FeatureAddMinMaxInsts = 7, |
| 25 | FeatureAddNoCarryInsts = 8, |
| 26 | FeatureAddSubU64Insts = 9, |
| 27 | FeatureAddressableLocalMemorySize32768 = 10, |
| 28 | FeatureAddressableLocalMemorySize65536 = 11, |
| 29 | FeatureAddressableLocalMemorySize163840 = 12, |
| 30 | FeatureAddressableLocalMemorySize196608 = 13, |
| 31 | FeatureAddressableLocalMemorySize327680 = 14, |
| 32 | FeatureAgentScopeFineGrainedRemoteMemoryAtomics = 15, |
| 33 | FeatureApertureRegs = 16, |
| 34 | FeatureArchitectedFlatScratch = 17, |
| 35 | FeatureArchitectedSGPRs = 18, |
| 36 | FeatureAshrPkInsts = 19, |
| 37 | FeatureAssemblerPermissiveWavesize = 20, |
| 38 | FeatureAsyncLoadToLDSInsts = 21, |
| 39 | FeatureAsyncStoreFromLDSInsts = 22, |
| 40 | FeatureAsynccnt = 23, |
| 41 | FeatureAtomicBufferGlobalPkAddF16Insts = 24, |
| 42 | FeatureAtomicBufferGlobalPkAddF16NoRtnInsts = 25, |
| 43 | FeatureAtomicBufferPkAddBF16Inst = 26, |
| 44 | FeatureAtomicCSubNoRtnInsts = 27, |
| 45 | FeatureAtomicDsPkAdd16Insts = 28, |
| 46 | FeatureAtomicFMinFMaxF32FlatInsts = 29, |
| 47 | FeatureAtomicFMinFMaxF32GlobalInsts = 30, |
| 48 | FeatureAtomicFMinFMaxF64FlatInsts = 31, |
| 49 | FeatureAtomicFMinFMaxF64GlobalInsts = 32, |
| 50 | FeatureAtomicFaddNoRtnInsts = 33, |
| 51 | FeatureAtomicFaddRtnInsts = 34, |
| 52 | FeatureAtomicFlatPkAdd16Insts = 35, |
| 53 | FeatureAtomicGlobalPkAddBF16Inst = 36, |
| 54 | FeatureAutoWaitcntBeforeBarrier = 37, |
| 55 | FeatureBF8ConversionScaleInsts = 38, |
| 56 | FeatureBF16ConversionInsts = 39, |
| 57 | FeatureBF16InlineConstFromUpperFP32 = 40, |
| 58 | FeatureBF16PackedInsts = 41, |
| 59 | FeatureBF16TransInsts = 42, |
| 60 | FeatureBVHDualAndBVH8Insts = 43, |
| 61 | FeatureBVHRayTracingInsts = 44, |
| 62 | FeatureBackOffBarrier = 45, |
| 63 | FeatureBitOp3Insts = 46, |
| 64 | FeatureCIInsts = 47, |
| 65 | FeatureClusters = 48, |
| 66 | FeatureCuMode = 49, |
| 67 | FeatureCubeInsts = 50, |
| 68 | FeatureCvtFP8ByteSel = 51, |
| 69 | FeatureCvtFP8SDWASrcSel = 52, |
| 70 | FeatureCvtFP8VOP1Bug = 53, |
| 71 | FeatureCvtNormInsts = 54, |
| 72 | FeatureCvtPkF16F32Inst = 55, |
| 73 | FeatureCvtPkNormVOP2Insts = 56, |
| 74 | FeatureCvtPkNormVOP3Insts = 57, |
| 75 | FeatureCvtSrPkBF16F32Inst = 58, |
| 76 | FeatureD16Writes32BitVgpr = 59, |
| 77 | FeatureDLInsts = 60, |
| 78 | FeatureDPALU_DPP = 61, |
| 79 | FeatureDPP = 62, |
| 80 | FeatureDPP8 = 63, |
| 81 | FeatureDPPBroadcasts = 64, |
| 82 | FeatureDPPSrc1SGPR = 65, |
| 83 | FeatureDPPWavefrontShifts = 66, |
| 84 | FeatureDX10ClampAndIEEEMode = 67, |
| 85 | FeatureDataCacheLineSize128 = 68, |
| 86 | FeatureDefaultComponentBroadcast = 69, |
| 87 | FeatureDefaultComponentZero = 70, |
| 88 | FeatureDot1Insts = 71, |
| 89 | FeatureDot2Insts = 72, |
| 90 | FeatureDot3Insts = 73, |
| 91 | FeatureDot4Insts = 74, |
| 92 | FeatureDot5Insts = 75, |
| 93 | FeatureDot6Insts = 76, |
| 94 | FeatureDot7Insts = 77, |
| 95 | FeatureDot8Insts = 78, |
| 96 | FeatureDot9Insts = 79, |
| 97 | FeatureDot10Insts = 80, |
| 98 | FeatureDot11Insts = 81, |
| 99 | FeatureDot12Insts = 82, |
| 100 | FeatureDot13Insts = 83, |
| 101 | FeatureDsSrc2Insts = 84, |
| 102 | FeatureDumpCodeLower = 85, |
| 103 | FeatureEmulatedSystemScopeAtomics = 86, |
| 104 | FeatureEnableDS128 = 87, |
| 105 | FeatureEnableFlatScratch = 88, |
| 106 | FeatureEnableLoadStoreOpt = 89, |
| 107 | FeatureEnablePRTStrictNull = 90, |
| 108 | FeatureEnableSIScheduler = 91, |
| 109 | FeatureEnableUnsafeDSOffsetFolding = 92, |
| 110 | FeatureExtendedImageInsts = 93, |
| 111 | FeatureF16BF16ToFP6BF6ConversionScaleInsts = 94, |
| 112 | FeatureF16FP8ConversionInsts = 95, |
| 113 | FeatureF32ToF16BF16ConversionSRInsts = 96, |
| 114 | FeatureF32ToFP6BF6ConversionScaleInsts = 97, |
| 115 | FeatureFMA = 98, |
| 116 | FeatureFP4ConversionScaleInsts = 99, |
| 117 | FeatureFP6BF6ConversionScaleInsts = 100, |
| 118 | FeatureFP8ConversionInsts = 101, |
| 119 | FeatureFP8ConversionScaleInsts = 102, |
| 120 | FeatureFP8E5M3Insts = 103, |
| 121 | FeatureFP8F16ConversionInsts = 104, |
| 122 | FeatureFP8Insts = 105, |
| 123 | FeatureFP64 = 106, |
| 124 | FeatureFastDenormalF32 = 107, |
| 125 | FeatureFastFMAF32 = 108, |
| 126 | FeatureFlatAddressSpace = 109, |
| 127 | FeatureFlatAtomicFaddF32Inst = 110, |
| 128 | FeatureFlatBufferGlobalAtomicFaddF64Inst = 111, |
| 129 | FeatureFlatGVSMode = 112, |
| 130 | FeatureFlatGlobalInsts = 113, |
| 131 | FeatureFlatInstOffsets = 114, |
| 132 | FeatureFlatOffsetBits12 = 115, |
| 133 | FeatureFlatOffsetBits24 = 116, |
| 134 | FeatureFlatScratchInsts = 117, |
| 135 | FeatureFlatSegmentOffsetBug = 118, |
| 136 | FeatureFlatSignedOffset = 119, |
| 137 | FeatureFmaLegacy32Insts = 120, |
| 138 | FeatureFmaMixBF16Insts = 121, |
| 139 | FeatureFmaMixInsts = 122, |
| 140 | FeatureFmacF64Inst = 123, |
| 141 | FeatureFormattedMUBUFInsts = 124, |
| 142 | FeatureFullRate64Ops = 125, |
| 143 | FeatureG16 = 126, |
| 144 | FeatureGCN3Encoding = 127, |
| 145 | FeatureGDS = 128, |
| 146 | FeatureGFX7GFX8GFX9Insts = 129, |
| 147 | FeatureGFX8Insts = 130, |
| 148 | FeatureGFX9 = 131, |
| 149 | FeatureGFX9Insts = 132, |
| 150 | FeatureGFX10 = 133, |
| 151 | FeatureGFX10Insts = 134, |
| 152 | FeatureGFX10_3Insts = 135, |
| 153 | FeatureGFX10_BEncoding = 136, |
| 154 | FeatureGFX11 = 137, |
| 155 | FeatureGFX11Insts = 138, |
| 156 | FeatureGFX11_7Insts = 139, |
| 157 | FeatureGFX12 = 140, |
| 158 | FeatureGFX12Insts = 141, |
| 159 | FeatureGFX13 = 142, |
| 160 | FeatureGFX13Insts = 143, |
| 161 | FeatureGFX90AInsts = 144, |
| 162 | FeatureGFX125xLowestRateWMMA = 145, |
| 163 | FeatureGFX940Insts = 146, |
| 164 | FeatureGFX950Insts = 147, |
| 165 | FeatureGFX1250Insts = 148, |
| 166 | FeatureGFX1250_STRICT = 149, |
| 167 | FeatureGFX1251GEMMInsts = 150, |
| 168 | FeatureGWS = 151, |
| 169 | FeatureGetWaveIdInst = 152, |
| 170 | FeatureGloballyAddressableScratch = 153, |
| 171 | FeatureHalfAddressablePhysicalLocalMemory = 154, |
| 172 | FeatureHalfRate64Ops = 155, |
| 173 | FeatureIEEEMinimumMaximumInsts = 156, |
| 174 | FeatureImageGather4D16Bug = 157, |
| 175 | FeatureImageInsts = 158, |
| 176 | FeatureImageStoreD16Bug = 159, |
| 177 | FeatureInstCacheLineSize64 = 160, |
| 178 | FeatureInstCacheLineSize128 = 161, |
| 179 | FeatureInstFwdPrefetchBug = 162, |
| 180 | FeatureIntClamp = 163, |
| 181 | FeatureInv2PiInlineImm = 164, |
| 182 | FeatureKernargPreload = 165, |
| 183 | FeatureLDSBankCount16 = 166, |
| 184 | FeatureLDSBankCount32 = 167, |
| 185 | FeatureLDSMisalignedBug = 168, |
| 186 | FeatureLdsAtomicAddF64 = 169, |
| 187 | FeatureLdsBarrierArriveAtomic = 170, |
| 188 | FeatureLdsBranchVmemWARHazard = 171, |
| 189 | FeatureLerpInst = 172, |
| 190 | FeatureLshlAddU64Inst = 173, |
| 191 | FeatureMADIntraFwdBug = 174, |
| 192 | FeatureMAIInsts = 175, |
| 193 | FeatureMFMAInlineLiteralBug = 176, |
| 194 | FeatureMIMG_R128 = 177, |
| 195 | FeatureMSAALoadDstSelBug = 178, |
| 196 | FeatureMSAALoadInsts = 179, |
| 197 | FeatureMTBUFInsts = 180, |
| 198 | FeatureMadMacF32Insts = 181, |
| 199 | FeatureMadMixInsts = 182, |
| 200 | FeatureMadNC64_32Insts = 183, |
| 201 | FeatureMadU32Inst = 184, |
| 202 | FeatureMaxHardClauseLength32 = 185, |
| 203 | FeatureMaxHardClauseLength63 = 186, |
| 204 | FeatureMaxPrivateElementSize4 = 187, |
| 205 | FeatureMaxPrivateElementSize8 = 188, |
| 206 | FeatureMaxPrivateElementSize16 = 189, |
| 207 | FeatureMaxWavesPerEU8 = 190, |
| 208 | FeatureMaxWavesPerEU10 = 191, |
| 209 | FeatureMaxWavesPerEU16 = 192, |
| 210 | FeatureMaxWavesPerEU20 = 193, |
| 211 | FeatureMcastLoadInsts = 194, |
| 212 | FeatureMemoryAtomicFAddF32DenormalSupport = 195, |
| 213 | FeatureMin3Max3PKF16 = 196, |
| 214 | FeatureMinMaxI64Insts = 197, |
| 215 | FeatureMinimum3Maximum3F16 = 198, |
| 216 | FeatureMinimum3Maximum3F32 = 199, |
| 217 | FeatureMinimum3Maximum3PKF16 = 200, |
| 218 | FeatureMovrel = 201, |
| 219 | FeatureMqsadInsts = 202, |
| 220 | FeatureMqsadPkInsts = 203, |
| 221 | FeatureMsadInsts = 204, |
| 222 | FeatureNSAClauseBug = 205, |
| 223 | FeatureNSAEncoding = 206, |
| 224 | FeatureNSAtoVMEMBug = 207, |
| 225 | FeatureNeedsAligned2addrDS = 208, |
| 226 | FeatureNeedsTDMDrain = 209, |
| 227 | FeatureNegativeScratchOffsetBug = 210, |
| 228 | FeatureNegativeUnalignedScratchOffsetBug = 211, |
| 229 | FeatureNoDataDepHazard = 212, |
| 230 | FeatureNoF16PseudoScalarTransInlineConstants = 213, |
| 231 | FeatureNoSdstCMPX = 214, |
| 232 | FeatureOCPFP8ConversionInsts = 215, |
| 233 | FeatureOffset3fBug = 216, |
| 234 | FeaturePackedFP32Ops = 217, |
| 235 | FeaturePackedFP32SingleSGPROps = 218, |
| 236 | FeaturePackedFP64SingleSGPROps = 219, |
| 237 | FeaturePackedTID = 220, |
| 238 | FeaturePackedU64SingleSGPROps = 221, |
| 239 | FeaturePartialNSAEncoding = 222, |
| 240 | FeaturePermlane16Insts = 223, |
| 241 | FeaturePermlane16Swap = 224, |
| 242 | FeaturePermlane32Swap = 225, |
| 243 | FeaturePkAddMinMaxInsts = 226, |
| 244 | FeaturePkFmacF16Inst = 227, |
| 245 | FeaturePointSampleAccel = 228, |
| 246 | FeaturePopsExitingWaveID = 229, |
| 247 | FeaturePreciseMemory = 230, |
| 248 | FeaturePrivEnabledTrap2NopBug = 231, |
| 249 | FeaturePrngInst = 232, |
| 250 | FeaturePseudoScalarTrans = 233, |
| 251 | FeatureQsadInsts = 234, |
| 252 | FeatureR128A16 = 235, |
| 253 | FeatureRealTrue16Insts = 236, |
| 254 | FeatureRequiredExportPriority = 237, |
| 255 | FeatureRequiresAlignedVGPRs = 238, |
| 256 | FeatureRequiresCOV6 = 239, |
| 257 | FeatureRequiresInitialUnclausedVmem = 240, |
| 258 | FeatureRestrictedSOffset = 241, |
| 259 | FeatureSALUFloatInsts = 242, |
| 260 | FeatureSALUMinimumMaximumInsts = 243, |
| 261 | FeatureSBarrierLeaveImm = 244, |
| 262 | FeatureSDWA = 245, |
| 263 | FeatureSDWAMac = 246, |
| 264 | FeatureSDWAOmod = 247, |
| 265 | FeatureSDWAOutModsVOPC = 248, |
| 266 | FeatureSDWAScalar = 249, |
| 267 | FeatureSDWASdst = 250, |
| 268 | FeatureSGPRInitBug = 251, |
| 269 | FeatureSMEMtoVectorWriteHazard = 252, |
| 270 | FeatureSMemRealTime = 253, |
| 271 | FeatureSMemTimeInst = 254, |
| 272 | FeatureSRAMECC = 255, |
| 273 | FeatureSWMMACGfx1200Insts = 256, |
| 274 | FeatureSWMMACGfx1250Insts = 257, |
| 275 | FeatureSWakeupBarrier = 258, |
| 276 | FeatureSWakeupImm = 259, |
| 277 | FeatureSadInsts = 260, |
| 278 | FeatureSafeCUPrefetch = 261, |
| 279 | FeatureSafeSmemPrefetch = 262, |
| 280 | FeatureScalarAtomics = 263, |
| 281 | FeatureScalarDwordx3Loads = 264, |
| 282 | FeatureScalarFlatScratchInsts = 265, |
| 283 | FeatureScalarStores = 266, |
| 284 | FeatureSeaIslands = 267, |
| 285 | FeatureSetPrioIncWgInst = 268, |
| 286 | FeatureSetregVGPRMSBFixup = 269, |
| 287 | FeatureShaderCyclesHiLoRegisters = 270, |
| 288 | FeatureShaderCyclesRegister = 271, |
| 289 | FeatureSmemPrefetchInsts = 272, |
| 290 | FeatureSouthernIslands = 273, |
| 291 | FeatureSupportsSRAMECC = 274, |
| 292 | FeatureSupportsWGP = 275, |
| 293 | FeatureSupportsWave32 = 276, |
| 294 | FeatureSupportsWave64 = 277, |
| 295 | FeatureSupportsXNACK = 278, |
| 296 | FeatureTanhInsts = 279, |
| 297 | FeatureTensorCvtLutInsts = 280, |
| 298 | FeatureTgSplitSupport = 281, |
| 299 | FeatureTransCoexecutionHazard = 282, |
| 300 | FeatureTransposeLoadF4F6Insts = 283, |
| 301 | FeatureTrapHandler = 284, |
| 302 | FeatureTrigReducedRange = 285, |
| 303 | FeatureTrue16BitInsts = 286, |
| 304 | FeatureUnalignedAccessMode = 287, |
| 305 | FeatureUnalignedBufferAccess = 288, |
| 306 | FeatureUnalignedDSAccess = 289, |
| 307 | FeatureUnalignedScratchAccess = 290, |
| 308 | FeatureUnpackedD16VMem = 291, |
| 309 | FeatureUseAddPC64Inst = 292, |
| 310 | FeatureUseBlockVGPROpsForCSR = 293, |
| 311 | FeatureUseFlatForGlobal = 294, |
| 312 | FeatureUserSGPRInit16Bug = 295, |
| 313 | FeatureVALUTransUseHazard = 296, |
| 314 | FeatureVGPRIndexMode = 297, |
| 315 | FeatureVMEMtoScalarWriteHazard = 298, |
| 316 | FeatureVMemToLDSLoad = 299, |
| 317 | FeatureVMovB64Inst = 300, |
| 318 | FeatureVMulU64Inst = 301, |
| 319 | FeatureVOP3Literal = 302, |
| 320 | FeatureVOP3PInsts = 303, |
| 321 | FeatureVOP3PX2IncrementsVaVdstTwice = 304, |
| 322 | FeatureVOPDInsts = 305, |
| 323 | FeatureVcmpxExecWARHazard = 306, |
| 324 | FeatureVcmpxPermlaneHazard = 307, |
| 325 | FeatureVmemPrefInsts = 308, |
| 326 | FeatureVmemWriteVgprInOrder = 309, |
| 327 | FeatureVolcanicIslands = 310, |
| 328 | FeatureVscnt = 311, |
| 329 | FeatureWMMA128bInsts = 312, |
| 330 | FeatureWMMA256bInsts = 313, |
| 331 | FeatureWMMACoexecutionHazards = 314, |
| 332 | FeatureWMMAN16Insts = 315, |
| 333 | FeatureWaitXcnt = 316, |
| 334 | FeatureWaitsBeforeSystemScopeStores = 317, |
| 335 | FeatureWavefrontSize16 = 318, |
| 336 | FeatureWavefrontSize32 = 319, |
| 337 | FeatureWavefrontSize64 = 320, |
| 338 | FeatureXF32Insts = 321, |
| 339 | FeatureXNACK = 322, |
| 340 | FeatureXNACKOnOffModes = 323, |
| 341 | NumSubtargetFeatures = 324 |
| 342 | }; |
| 343 | |
| 344 | } // namespace AMDGPU |
| 345 | |
| 346 | } // namespace llvm |
| 347 | |
| 348 | #endif // GET_SUBTARGETINFO_ENUM |
| 349 | |
| 350 | #ifdef GET_SUBTARGETINFO_MACRO |
| 351 | |
| 352 | GET_SUBTARGETINFO_MACRO(DumpCode, false, dumpCode) |
| 353 | GET_SUBTARGETINFO_MACRO(EnableCuMode, false, enableCuMode) |
| 354 | GET_SUBTARGETINFO_MACRO(EnableDS128, false, enableDS128) |
| 355 | GET_SUBTARGETINFO_MACRO(EnableFlatScratch, false, enableFlatScratch) |
| 356 | GET_SUBTARGETINFO_MACRO(EnableLoadStoreOpt, false, enableLoadStoreOpt) |
| 357 | GET_SUBTARGETINFO_MACRO(EnablePRTStrictNull, false, enablePRTStrictNull) |
| 358 | GET_SUBTARGETINFO_MACRO(EnablePreciseMemory, false, enablePreciseMemory) |
| 359 | GET_SUBTARGETINFO_MACRO(EnableRealTrue16Insts, false, enableRealTrue16Insts) |
| 360 | GET_SUBTARGETINFO_MACRO(EnableSIScheduler, false, enableSIScheduler) |
| 361 | GET_SUBTARGETINFO_MACRO(EnableSRAMECC, false, enableSRAMECC) |
| 362 | GET_SUBTARGETINFO_MACRO(EnableUnsafeDSOffsetFolding, false, enableUnsafeDSOffsetFolding) |
| 363 | GET_SUBTARGETINFO_MACRO(EnableXNACK, false, enableXNACK) |
| 364 | GET_SUBTARGETINFO_MACRO(Has1024AddressableVGPRs, false, has1024AddressableVGPRs) |
| 365 | GET_SUBTARGETINFO_MACRO(Has1536VGPRs, false, has1536VGPRs) |
| 366 | GET_SUBTARGETINFO_MACRO(Has16BitInsts, false, has16BitInsts) |
| 367 | GET_SUBTARGETINFO_MACRO(Has64BitLiterals, false, has64BitLiterals) |
| 368 | GET_SUBTARGETINFO_MACRO(HasA16, false, hasA16) |
| 369 | GET_SUBTARGETINFO_MACRO(HasAddMinMaxInsts, false, hasAddMinMaxInsts) |
| 370 | GET_SUBTARGETINFO_MACRO(HasAddNoCarryInsts, false, hasAddNoCarryInsts) |
| 371 | GET_SUBTARGETINFO_MACRO(HasAddSubU64Insts, false, hasAddSubU64Insts) |
| 372 | GET_SUBTARGETINFO_MACRO(HasAgentScopeFineGrainedRemoteMemoryAtomics, false, hasAgentScopeFineGrainedRemoteMemoryAtomics) |
| 373 | GET_SUBTARGETINFO_MACRO(HasApertureRegs, false, hasApertureRegs) |
| 374 | GET_SUBTARGETINFO_MACRO(HasArchitectedFlatScratch, false, hasArchitectedFlatScratch) |
| 375 | GET_SUBTARGETINFO_MACRO(HasArchitectedSGPRs, false, hasArchitectedSGPRs) |
| 376 | GET_SUBTARGETINFO_MACRO(HasAshrPkInsts, false, hasAshrPkInsts) |
| 377 | GET_SUBTARGETINFO_MACRO(HasAssemblerPermissiveWavesize, false, hasAssemblerPermissiveWavesize) |
| 378 | GET_SUBTARGETINFO_MACRO(HasAsyncLoadToLDSInsts, false, hasAsyncLoadToLDSInsts) |
| 379 | GET_SUBTARGETINFO_MACRO(HasAsyncStoreFromLDSInsts, false, hasAsyncStoreFromLDSInsts) |
| 380 | GET_SUBTARGETINFO_MACRO(HasAsynccnt, false, hasAsynccnt) |
| 381 | GET_SUBTARGETINFO_MACRO(HasAtomicBufferGlobalPkAddF16Insts, false, hasAtomicBufferGlobalPkAddF16Insts) |
| 382 | GET_SUBTARGETINFO_MACRO(HasAtomicBufferGlobalPkAddF16NoRtnInsts, false, hasAtomicBufferGlobalPkAddF16NoRtnInsts) |
| 383 | GET_SUBTARGETINFO_MACRO(HasAtomicBufferPkAddBF16Inst, false, hasAtomicBufferPkAddBF16Inst) |
| 384 | GET_SUBTARGETINFO_MACRO(HasAtomicCSubNoRtnInsts, false, hasAtomicCSubNoRtnInsts) |
| 385 | GET_SUBTARGETINFO_MACRO(HasAtomicDsPkAdd16Insts, false, hasAtomicDsPkAdd16Insts) |
| 386 | GET_SUBTARGETINFO_MACRO(HasAtomicFMinFMaxF32FlatInsts, false, hasAtomicFMinFMaxF32FlatInsts) |
| 387 | GET_SUBTARGETINFO_MACRO(HasAtomicFMinFMaxF32GlobalInsts, false, hasAtomicFMinFMaxF32GlobalInsts) |
| 388 | GET_SUBTARGETINFO_MACRO(HasAtomicFMinFMaxF64FlatInsts, false, hasAtomicFMinFMaxF64FlatInsts) |
| 389 | GET_SUBTARGETINFO_MACRO(HasAtomicFMinFMaxF64GlobalInsts, false, hasAtomicFMinFMaxF64GlobalInsts) |
| 390 | GET_SUBTARGETINFO_MACRO(HasAtomicFaddNoRtnInsts, false, hasAtomicFaddNoRtnInsts) |
| 391 | GET_SUBTARGETINFO_MACRO(HasAtomicFaddRtnInsts, false, hasAtomicFaddRtnInsts) |
| 392 | GET_SUBTARGETINFO_MACRO(HasAtomicFlatPkAdd16Insts, false, hasAtomicFlatPkAdd16Insts) |
| 393 | GET_SUBTARGETINFO_MACRO(HasAtomicGlobalPkAddBF16Inst, false, hasAtomicGlobalPkAddBF16Inst) |
| 394 | GET_SUBTARGETINFO_MACRO(HasAutoWaitcntBeforeBarrier, false, hasAutoWaitcntBeforeBarrier) |
| 395 | GET_SUBTARGETINFO_MACRO(HasBF16ConversionInsts, false, hasBF16ConversionInsts) |
| 396 | GET_SUBTARGETINFO_MACRO(HasBF16InlineConstFromUpperFP32, false, hasBF16InlineConstFromUpperFP32) |
| 397 | GET_SUBTARGETINFO_MACRO(HasBF16PackedInsts, false, hasBF16PackedInsts) |
| 398 | GET_SUBTARGETINFO_MACRO(HasBF16TransInsts, false, hasBF16TransInsts) |
| 399 | GET_SUBTARGETINFO_MACRO(HasBF8ConversionScaleInsts, false, hasBF8ConversionScaleInsts) |
| 400 | GET_SUBTARGETINFO_MACRO(HasBVHDualAndBVH8Insts, false, hasBVHDualAndBVH8Insts) |
| 401 | GET_SUBTARGETINFO_MACRO(HasBVHRayTracingInsts, false, hasBVHRayTracingInsts) |
| 402 | GET_SUBTARGETINFO_MACRO(HasBackOffBarrier, false, hasBackOffBarrier) |
| 403 | GET_SUBTARGETINFO_MACRO(HasBitOp3Insts, false, hasBitOp3Insts) |
| 404 | GET_SUBTARGETINFO_MACRO(HasCIInsts, false, hasCIInsts) |
| 405 | GET_SUBTARGETINFO_MACRO(HasClusters, false, hasClusters) |
| 406 | GET_SUBTARGETINFO_MACRO(HasCubeInsts, false, hasCubeInsts) |
| 407 | GET_SUBTARGETINFO_MACRO(HasCvtFP8ByteSel, false, hasCvtFP8ByteSel) |
| 408 | GET_SUBTARGETINFO_MACRO(HasCvtFP8SDWASrcSel, false, hasCvtFP8SDWASrcSel) |
| 409 | GET_SUBTARGETINFO_MACRO(HasCvtFP8VOP1Bug, false, hasCvtFP8VOP1Bug) |
| 410 | GET_SUBTARGETINFO_MACRO(HasCvtNormInsts, false, hasCvtNormInsts) |
| 411 | GET_SUBTARGETINFO_MACRO(HasCvtPkF16F32Inst, false, hasCvtPkF16F32Inst) |
| 412 | GET_SUBTARGETINFO_MACRO(HasCvtPkNormVOP2Insts, false, hasCvtPkNormVOP2Insts) |
| 413 | GET_SUBTARGETINFO_MACRO(HasCvtPkNormVOP3Insts, false, hasCvtPkNormVOP3Insts) |
| 414 | GET_SUBTARGETINFO_MACRO(HasCvtSrPkBF16F32Inst, false, hasCvtSrPkBF16F32Inst) |
| 415 | GET_SUBTARGETINFO_MACRO(HasD16Writes32BitVgpr, false, hasD16Writes32BitVgpr) |
| 416 | GET_SUBTARGETINFO_MACRO(HasDLInsts, false, hasDLInsts) |
| 417 | GET_SUBTARGETINFO_MACRO(HasDPALU_DPP, false, hasDPALU_DPP) |
| 418 | GET_SUBTARGETINFO_MACRO(HasDPP, false, hasDPP) |
| 419 | GET_SUBTARGETINFO_MACRO(HasDPP8, false, hasDPP8) |
| 420 | GET_SUBTARGETINFO_MACRO(HasDPPBroadcasts, false, hasDPPBroadcasts) |
| 421 | GET_SUBTARGETINFO_MACRO(HasDPPSrc1SGPR, false, hasDPPSrc1SGPR) |
| 422 | GET_SUBTARGETINFO_MACRO(HasDPPWavefrontShifts, false, hasDPPWavefrontShifts) |
| 423 | GET_SUBTARGETINFO_MACRO(HasDX10ClampAndIEEEMode, false, hasDX10ClampAndIEEEMode) |
| 424 | GET_SUBTARGETINFO_MACRO(HasDefaultComponentBroadcast, false, hasDefaultComponentBroadcast) |
| 425 | GET_SUBTARGETINFO_MACRO(HasDefaultComponentZero, false, hasDefaultComponentZero) |
| 426 | GET_SUBTARGETINFO_MACRO(HasDot10Insts, false, hasDot10Insts) |
| 427 | GET_SUBTARGETINFO_MACRO(HasDot11Insts, false, hasDot11Insts) |
| 428 | GET_SUBTARGETINFO_MACRO(HasDot12Insts, false, hasDot12Insts) |
| 429 | GET_SUBTARGETINFO_MACRO(HasDot13Insts, false, hasDot13Insts) |
| 430 | GET_SUBTARGETINFO_MACRO(HasDot1Insts, false, hasDot1Insts) |
| 431 | GET_SUBTARGETINFO_MACRO(HasDot2Insts, false, hasDot2Insts) |
| 432 | GET_SUBTARGETINFO_MACRO(HasDot3Insts, false, hasDot3Insts) |
| 433 | GET_SUBTARGETINFO_MACRO(HasDot4Insts, false, hasDot4Insts) |
| 434 | GET_SUBTARGETINFO_MACRO(HasDot5Insts, false, hasDot5Insts) |
| 435 | GET_SUBTARGETINFO_MACRO(HasDot6Insts, false, hasDot6Insts) |
| 436 | GET_SUBTARGETINFO_MACRO(HasDot7Insts, false, hasDot7Insts) |
| 437 | GET_SUBTARGETINFO_MACRO(HasDot8Insts, false, hasDot8Insts) |
| 438 | GET_SUBTARGETINFO_MACRO(HasDot9Insts, false, hasDot9Insts) |
| 439 | GET_SUBTARGETINFO_MACRO(HasDsSrc2Insts, false, hasDsSrc2Insts) |
| 440 | GET_SUBTARGETINFO_MACRO(HasEmulatedSystemScopeAtomics, false, hasEmulatedSystemScopeAtomics) |
| 441 | GET_SUBTARGETINFO_MACRO(HasExtendedImageInsts, false, hasExtendedImageInsts) |
| 442 | GET_SUBTARGETINFO_MACRO(HasF16BF16ToFP6BF6ConversionScaleInsts, false, hasF16BF16ToFP6BF6ConversionScaleInsts) |
| 443 | GET_SUBTARGETINFO_MACRO(HasF16FP8ConversionInsts, false, hasF16FP8ConversionInsts) |
| 444 | GET_SUBTARGETINFO_MACRO(HasF32ToF16BF16ConversionSRInsts, false, hasF32ToF16BF16ConversionSRInsts) |
| 445 | GET_SUBTARGETINFO_MACRO(HasF32ToFP6BF6ConversionScaleInsts, false, hasF32ToFP6BF6ConversionScaleInsts) |
| 446 | GET_SUBTARGETINFO_MACRO(HasFMA, false, hasFMA) |
| 447 | GET_SUBTARGETINFO_MACRO(HasFP4ConversionScaleInsts, false, hasFP4ConversionScaleInsts) |
| 448 | GET_SUBTARGETINFO_MACRO(HasFP64, false, hasFP64) |
| 449 | GET_SUBTARGETINFO_MACRO(HasFP6BF6ConversionScaleInsts, false, hasFP6BF6ConversionScaleInsts) |
| 450 | GET_SUBTARGETINFO_MACRO(HasFP8ConversionInsts, false, hasFP8ConversionInsts) |
| 451 | GET_SUBTARGETINFO_MACRO(HasFP8ConversionScaleInsts, false, hasFP8ConversionScaleInsts) |
| 452 | GET_SUBTARGETINFO_MACRO(HasFP8E5M3Insts, false, hasFP8E5M3Insts) |
| 453 | GET_SUBTARGETINFO_MACRO(HasFP8F16ConversionInsts, false, hasFP8F16ConversionInsts) |
| 454 | GET_SUBTARGETINFO_MACRO(HasFP8Insts, false, hasFP8Insts) |
| 455 | GET_SUBTARGETINFO_MACRO(HasFastDenormalF32, false, hasFastDenormalF32) |
| 456 | GET_SUBTARGETINFO_MACRO(HasFastFMAF32, false, hasFastFMAF32) |
| 457 | GET_SUBTARGETINFO_MACRO(HasFlatAddressSpace, false, hasFlatAddressSpace) |
| 458 | GET_SUBTARGETINFO_MACRO(HasFlatAtomicFaddF32Inst, false, hasFlatAtomicFaddF32Inst) |
| 459 | GET_SUBTARGETINFO_MACRO(HasFlatBufferGlobalAtomicFaddF64Inst, false, hasFlatBufferGlobalAtomicFaddF64Inst) |
| 460 | GET_SUBTARGETINFO_MACRO(HasFlatGVSMode, false, hasFlatGVSMode) |
| 461 | GET_SUBTARGETINFO_MACRO(HasFlatGlobalInsts, false, hasFlatGlobalInsts) |
| 462 | GET_SUBTARGETINFO_MACRO(HasFlatInstOffsets, false, hasFlatInstOffsets) |
| 463 | GET_SUBTARGETINFO_MACRO(HasFlatScratchInsts, false, hasFlatScratchInsts) |
| 464 | GET_SUBTARGETINFO_MACRO(HasFlatSegmentOffsetBug, false, hasFlatSegmentOffsetBug) |
| 465 | GET_SUBTARGETINFO_MACRO(HasFlatSignedOffset, false, hasFlatSignedOffset) |
| 466 | GET_SUBTARGETINFO_MACRO(HasFmaLegacy32Insts, false, hasFmaLegacy32Insts) |
| 467 | GET_SUBTARGETINFO_MACRO(HasFmaMixBF16Insts, false, hasFmaMixBF16Insts) |
| 468 | GET_SUBTARGETINFO_MACRO(HasFmaMixInsts, false, hasFmaMixInsts) |
| 469 | GET_SUBTARGETINFO_MACRO(HasFmacF64Inst, false, hasFmacF64Inst) |
| 470 | GET_SUBTARGETINFO_MACRO(HasFormattedMUBUFInsts, false, hasFormattedMUBUFInsts) |
| 471 | GET_SUBTARGETINFO_MACRO(HasFullRate64Ops, false, hasFullRate64Ops) |
| 472 | GET_SUBTARGETINFO_MACRO(HasG16, false, hasG16) |
| 473 | GET_SUBTARGETINFO_MACRO(HasGCN3Encoding, false, hasGCN3Encoding) |
| 474 | GET_SUBTARGETINFO_MACRO(HasGDS, false, hasGDS) |
| 475 | GET_SUBTARGETINFO_MACRO(HasGFX10Insts, false, hasGFX10Insts) |
| 476 | GET_SUBTARGETINFO_MACRO(HasGFX10_3Insts, false, hasGFX10_3Insts) |
| 477 | GET_SUBTARGETINFO_MACRO(HasGFX10_BEncoding, false, hasGFX10_BEncoding) |
| 478 | GET_SUBTARGETINFO_MACRO(HasGFX11Insts, false, hasGFX11Insts) |
| 479 | GET_SUBTARGETINFO_MACRO(HasGFX11_7Insts, false, hasGFX11_7Insts) |
| 480 | GET_SUBTARGETINFO_MACRO(HasGFX1250Insts, false, hasGFX1250Insts) |
| 481 | GET_SUBTARGETINFO_MACRO(HasGFX1250_STRICT, false, hasGFX1250_STRICT) |
| 482 | GET_SUBTARGETINFO_MACRO(HasGFX1251GEMMInsts, false, hasGFX1251GEMMInsts) |
| 483 | GET_SUBTARGETINFO_MACRO(HasGFX125xLowestRateWMMA, false, hasGFX125xLowestRateWMMA) |
| 484 | GET_SUBTARGETINFO_MACRO(HasGFX12Insts, false, hasGFX12Insts) |
| 485 | GET_SUBTARGETINFO_MACRO(HasGFX13Insts, false, hasGFX13Insts) |
| 486 | GET_SUBTARGETINFO_MACRO(HasGFX7GFX8GFX9Insts, false, hasGFX7GFX8GFX9Insts) |
| 487 | GET_SUBTARGETINFO_MACRO(HasGFX8Insts, false, hasGFX8Insts) |
| 488 | GET_SUBTARGETINFO_MACRO(HasGFX90AInsts, false, hasGFX90AInsts) |
| 489 | GET_SUBTARGETINFO_MACRO(HasGFX940Insts, false, hasGFX940Insts) |
| 490 | GET_SUBTARGETINFO_MACRO(HasGFX950Insts, false, hasGFX950Insts) |
| 491 | GET_SUBTARGETINFO_MACRO(HasGFX9Insts, false, hasGFX9Insts) |
| 492 | GET_SUBTARGETINFO_MACRO(HasGWS, false, hasGWS) |
| 493 | GET_SUBTARGETINFO_MACRO(HasGetWaveIdInst, false, hasGetWaveIdInst) |
| 494 | GET_SUBTARGETINFO_MACRO(HasGloballyAddressableScratch, false, hasGloballyAddressableScratch) |
| 495 | GET_SUBTARGETINFO_MACRO(HasHalfAddressablePhysicalLocalMemory, false, hasHalfAddressablePhysicalLocalMemory) |
| 496 | GET_SUBTARGETINFO_MACRO(HasHalfRate64Ops, false, hasHalfRate64Ops) |
| 497 | GET_SUBTARGETINFO_MACRO(HasIEEEMinimumMaximumInsts, false, hasIEEEMinimumMaximumInsts) |
| 498 | GET_SUBTARGETINFO_MACRO(HasImageGather4D16Bug, false, hasImageGather4D16Bug) |
| 499 | GET_SUBTARGETINFO_MACRO(HasImageInsts, false, hasImageInsts) |
| 500 | GET_SUBTARGETINFO_MACRO(HasImageStoreD16Bug, false, hasImageStoreD16Bug) |
| 501 | GET_SUBTARGETINFO_MACRO(HasInstFwdPrefetchBug, false, hasInstFwdPrefetchBug) |
| 502 | GET_SUBTARGETINFO_MACRO(HasIntClamp, false, hasIntClamp) |
| 503 | GET_SUBTARGETINFO_MACRO(HasInv2PiInlineImm, false, hasInv2PiInlineImm) |
| 504 | GET_SUBTARGETINFO_MACRO(HasKernargPreload, false, hasKernargPreload) |
| 505 | GET_SUBTARGETINFO_MACRO(HasLDSMisalignedBug, false, hasLDSMisalignedBug) |
| 506 | GET_SUBTARGETINFO_MACRO(HasLdsAtomicAddF64, false, hasLdsAtomicAddF64) |
| 507 | GET_SUBTARGETINFO_MACRO(HasLdsBarrierArriveAtomic, false, hasLdsBarrierArriveAtomic) |
| 508 | GET_SUBTARGETINFO_MACRO(HasLdsBranchVmemWARHazard, false, hasLdsBranchVmemWARHazard) |
| 509 | GET_SUBTARGETINFO_MACRO(HasLerpInst, false, hasLerpInst) |
| 510 | GET_SUBTARGETINFO_MACRO(HasLshlAddU64Inst, false, hasLshlAddU64Inst) |
| 511 | GET_SUBTARGETINFO_MACRO(HasMADIntraFwdBug, false, hasMADIntraFwdBug) |
| 512 | GET_SUBTARGETINFO_MACRO(HasMAIInsts, false, hasMAIInsts) |
| 513 | GET_SUBTARGETINFO_MACRO(HasMFMAInlineLiteralBug, false, hasMFMAInlineLiteralBug) |
| 514 | GET_SUBTARGETINFO_MACRO(HasMIMG_R128, false, hasMIMG_R128) |
| 515 | GET_SUBTARGETINFO_MACRO(HasMSAALoadDstSelBug, false, hasMSAALoadDstSelBug) |
| 516 | GET_SUBTARGETINFO_MACRO(HasMSAALoadInsts, false, hasMSAALoadInsts) |
| 517 | GET_SUBTARGETINFO_MACRO(HasMTBUFInsts, false, hasMTBUFInsts) |
| 518 | GET_SUBTARGETINFO_MACRO(HasMadMacF32Insts, false, hasMadMacF32Insts) |
| 519 | GET_SUBTARGETINFO_MACRO(HasMadMixInsts, false, hasMadMixInsts) |
| 520 | GET_SUBTARGETINFO_MACRO(HasMadNC64_32Insts, false, hasMadNC64_32Insts) |
| 521 | GET_SUBTARGETINFO_MACRO(HasMadU32Inst, false, hasMadU32Inst) |
| 522 | GET_SUBTARGETINFO_MACRO(HasMcastLoadInsts, false, hasMcastLoadInsts) |
| 523 | GET_SUBTARGETINFO_MACRO(HasMemoryAtomicFaddF32DenormalSupport, false, hasMemoryAtomicFaddF32DenormalSupport) |
| 524 | GET_SUBTARGETINFO_MACRO(HasMin3Max3PKF16, false, hasMin3Max3PKF16) |
| 525 | GET_SUBTARGETINFO_MACRO(HasMinMaxI64Insts, false, hasMinMaxI64Insts) |
| 526 | GET_SUBTARGETINFO_MACRO(HasMinimum3Maximum3F16, false, hasMinimum3Maximum3F16) |
| 527 | GET_SUBTARGETINFO_MACRO(HasMinimum3Maximum3F32, false, hasMinimum3Maximum3F32) |
| 528 | GET_SUBTARGETINFO_MACRO(HasMinimum3Maximum3PKF16, false, hasMinimum3Maximum3PKF16) |
| 529 | GET_SUBTARGETINFO_MACRO(HasMovrel, false, hasMovrel) |
| 530 | GET_SUBTARGETINFO_MACRO(HasMqsadInsts, false, hasMqsadInsts) |
| 531 | GET_SUBTARGETINFO_MACRO(HasMqsadPkInsts, false, hasMqsadPkInsts) |
| 532 | GET_SUBTARGETINFO_MACRO(HasMsadInsts, false, hasMsadInsts) |
| 533 | GET_SUBTARGETINFO_MACRO(HasNSAClauseBug, false, hasNSAClauseBug) |
| 534 | GET_SUBTARGETINFO_MACRO(HasNSAEncoding, false, hasNSAEncoding) |
| 535 | GET_SUBTARGETINFO_MACRO(HasNSAtoVMEMBug, false, hasNSAtoVMEMBug) |
| 536 | GET_SUBTARGETINFO_MACRO(HasNeedsAligned2addrDS, false, hasNeedsAligned2addrDS) |
| 537 | GET_SUBTARGETINFO_MACRO(HasNeedsTDMDrain, false, hasNeedsTDMDrain) |
| 538 | GET_SUBTARGETINFO_MACRO(HasNegativeScratchOffsetBug, false, hasNegativeScratchOffsetBug) |
| 539 | GET_SUBTARGETINFO_MACRO(HasNegativeUnalignedScratchOffsetBug, false, hasNegativeUnalignedScratchOffsetBug) |
| 540 | GET_SUBTARGETINFO_MACRO(HasNoDataDepHazard, false, hasNoDataDepHazard) |
| 541 | GET_SUBTARGETINFO_MACRO(HasNoF16PseudoScalarTransInlineConstants, false, hasNoF16PseudoScalarTransInlineConstants) |
| 542 | GET_SUBTARGETINFO_MACRO(HasNoSdstCMPX, false, hasNoSdstCMPX) |
| 543 | GET_SUBTARGETINFO_MACRO(HasOCPFP8ConversionInsts, false, hasOCPFP8ConversionInsts) |
| 544 | GET_SUBTARGETINFO_MACRO(HasOffset3fBug, false, hasOffset3fBug) |
| 545 | GET_SUBTARGETINFO_MACRO(HasPackedFP32Ops, false, hasPackedFP32Ops) |
| 546 | GET_SUBTARGETINFO_MACRO(HasPackedFP32SingleSGPROps, false, hasPackedFP32SingleSGPROps) |
| 547 | GET_SUBTARGETINFO_MACRO(HasPackedFP64SingleSGPROps, false, hasPackedFP64SingleSGPROps) |
| 548 | GET_SUBTARGETINFO_MACRO(HasPackedTID, false, hasPackedTID) |
| 549 | GET_SUBTARGETINFO_MACRO(HasPackedU64SingleSGPROps, false, hasPackedU64SingleSGPROps) |
| 550 | GET_SUBTARGETINFO_MACRO(HasPartialNSAEncoding, false, hasPartialNSAEncoding) |
| 551 | GET_SUBTARGETINFO_MACRO(HasPermlane16Insts, false, hasPermlane16Insts) |
| 552 | GET_SUBTARGETINFO_MACRO(HasPermlane16Swap, false, hasPermlane16Swap) |
| 553 | GET_SUBTARGETINFO_MACRO(HasPermlane32Swap, false, hasPermlane32Swap) |
| 554 | GET_SUBTARGETINFO_MACRO(HasPkAddMinMaxInsts, false, hasPkAddMinMaxInsts) |
| 555 | GET_SUBTARGETINFO_MACRO(HasPkFmacF16Inst, false, hasPkFmacF16Inst) |
| 556 | GET_SUBTARGETINFO_MACRO(HasPointSampleAccel, false, hasPointSampleAccel) |
| 557 | GET_SUBTARGETINFO_MACRO(HasPopsExitingWaveID, false, hasPopsExitingWaveID) |
| 558 | GET_SUBTARGETINFO_MACRO(HasPrivEnabledTrap2NopBug, false, hasPrivEnabledTrap2NopBug) |
| 559 | GET_SUBTARGETINFO_MACRO(HasPrngInst, false, hasPrngInst) |
| 560 | GET_SUBTARGETINFO_MACRO(HasPseudoScalarTrans, false, hasPseudoScalarTrans) |
| 561 | GET_SUBTARGETINFO_MACRO(HasQsadInsts, false, hasQsadInsts) |
| 562 | GET_SUBTARGETINFO_MACRO(HasR128A16, false, hasR128A16) |
| 563 | GET_SUBTARGETINFO_MACRO(HasRequiredExportPriority, false, hasRequiredExportPriority) |
| 564 | GET_SUBTARGETINFO_MACRO(HasRequiresInitialUnclausedVmem, false, hasRequiresInitialUnclausedVmem) |
| 565 | GET_SUBTARGETINFO_MACRO(HasRestrictedSOffset, false, hasRestrictedSOffset) |
| 566 | GET_SUBTARGETINFO_MACRO(HasSALUFloatInsts, false, hasSALUFloatInsts) |
| 567 | GET_SUBTARGETINFO_MACRO(HasSALUMinimumMaximumInsts, false, hasSALUMinimumMaximumInsts) |
| 568 | GET_SUBTARGETINFO_MACRO(HasSBarrierLeaveImm, false, hasSBarrierLeaveImm) |
| 569 | GET_SUBTARGETINFO_MACRO(HasSDWA, false, hasSDWA) |
| 570 | GET_SUBTARGETINFO_MACRO(HasSDWAMac, false, hasSDWAMac) |
| 571 | GET_SUBTARGETINFO_MACRO(HasSDWAOmod, false, hasSDWAOmod) |
| 572 | GET_SUBTARGETINFO_MACRO(HasSDWAOutModsVOPC, false, hasSDWAOutModsVOPC) |
| 573 | GET_SUBTARGETINFO_MACRO(HasSDWAScalar, false, hasSDWAScalar) |
| 574 | GET_SUBTARGETINFO_MACRO(HasSDWASdst, false, hasSDWASdst) |
| 575 | GET_SUBTARGETINFO_MACRO(HasSGPRInitBug, false, hasSGPRInitBug) |
| 576 | GET_SUBTARGETINFO_MACRO(HasSMEMtoVectorWriteHazard, false, hasSMEMtoVectorWriteHazard) |
| 577 | GET_SUBTARGETINFO_MACRO(HasSMemRealTime, false, hasSMemRealTime) |
| 578 | GET_SUBTARGETINFO_MACRO(HasSMemTimeInst, false, hasSMemTimeInst) |
| 579 | GET_SUBTARGETINFO_MACRO(HasSWMMACGfx1200Insts, false, hasSWMMACGfx1200Insts) |
| 580 | GET_SUBTARGETINFO_MACRO(HasSWMMACGfx1250Insts, false, hasSWMMACGfx1250Insts) |
| 581 | GET_SUBTARGETINFO_MACRO(HasSWakeupBarrier, false, hasSWakeupBarrier) |
| 582 | GET_SUBTARGETINFO_MACRO(HasSWakeupImm, false, hasSWakeupImm) |
| 583 | GET_SUBTARGETINFO_MACRO(HasSadInsts, false, hasSadInsts) |
| 584 | GET_SUBTARGETINFO_MACRO(HasSafeCUPrefetch, false, hasSafeCUPrefetch) |
| 585 | GET_SUBTARGETINFO_MACRO(HasSafeSmemPrefetch, false, hasSafeSmemPrefetch) |
| 586 | GET_SUBTARGETINFO_MACRO(HasScalarAtomics, false, hasScalarAtomics) |
| 587 | GET_SUBTARGETINFO_MACRO(HasScalarDwordx3Loads, false, hasScalarDwordx3Loads) |
| 588 | GET_SUBTARGETINFO_MACRO(HasScalarFlatScratchInsts, false, hasScalarFlatScratchInsts) |
| 589 | GET_SUBTARGETINFO_MACRO(HasScalarStores, false, hasScalarStores) |
| 590 | GET_SUBTARGETINFO_MACRO(HasSetPrioIncWgInst, false, hasSetPrioIncWgInst) |
| 591 | GET_SUBTARGETINFO_MACRO(HasSetregVGPRMSBFixup, false, hasSetregVGPRMSBFixup) |
| 592 | GET_SUBTARGETINFO_MACRO(HasShaderCyclesHiLoRegisters, false, hasShaderCyclesHiLoRegisters) |
| 593 | GET_SUBTARGETINFO_MACRO(HasShaderCyclesRegister, false, hasShaderCyclesRegister) |
| 594 | GET_SUBTARGETINFO_MACRO(HasSmemPrefetchInsts, false, hasSmemPrefetchInsts) |
| 595 | GET_SUBTARGETINFO_MACRO(HasSupportsWGP, false, hasSupportsWGP) |
| 596 | GET_SUBTARGETINFO_MACRO(HasTanhInsts, false, hasTanhInsts) |
| 597 | GET_SUBTARGETINFO_MACRO(HasTensorCvtLutInsts, false, hasTensorCvtLutInsts) |
| 598 | GET_SUBTARGETINFO_MACRO(HasTgSplitSupport, false, hasTgSplitSupport) |
| 599 | GET_SUBTARGETINFO_MACRO(HasTransCoexecutionHazard, false, hasTransCoexecutionHazard) |
| 600 | GET_SUBTARGETINFO_MACRO(HasTransposeLoadF4F6Insts, false, hasTransposeLoadF4F6Insts) |
| 601 | GET_SUBTARGETINFO_MACRO(HasTrapHandler, false, hasTrapHandler) |
| 602 | GET_SUBTARGETINFO_MACRO(HasTrigReducedRange, false, hasTrigReducedRange) |
| 603 | GET_SUBTARGETINFO_MACRO(HasTrue16BitInsts, false, hasTrue16BitInsts) |
| 604 | GET_SUBTARGETINFO_MACRO(HasUnalignedAccessMode, false, hasUnalignedAccessMode) |
| 605 | GET_SUBTARGETINFO_MACRO(HasUnalignedBufferAccess, false, hasUnalignedBufferAccess) |
| 606 | GET_SUBTARGETINFO_MACRO(HasUnalignedDSAccess, false, hasUnalignedDSAccess) |
| 607 | GET_SUBTARGETINFO_MACRO(HasUnalignedScratchAccess, false, hasUnalignedScratchAccess) |
| 608 | GET_SUBTARGETINFO_MACRO(HasUnpackedD16VMem, false, hasUnpackedD16VMem) |
| 609 | GET_SUBTARGETINFO_MACRO(HasUserSGPRInit16Bug, false, hasUserSGPRInit16Bug) |
| 610 | GET_SUBTARGETINFO_MACRO(HasVALUTransUseHazard, false, hasVALUTransUseHazard) |
| 611 | GET_SUBTARGETINFO_MACRO(HasVGPRIndexMode, false, hasVGPRIndexMode) |
| 612 | GET_SUBTARGETINFO_MACRO(HasVMEMtoScalarWriteHazard, false, hasVMEMtoScalarWriteHazard) |
| 613 | GET_SUBTARGETINFO_MACRO(HasVMemToLDSLoad, false, hasVMemToLDSLoad) |
| 614 | GET_SUBTARGETINFO_MACRO(HasVMovB64Inst, false, hasVMovB64Inst) |
| 615 | GET_SUBTARGETINFO_MACRO(HasVMulU64Inst, false, hasVMulU64Inst) |
| 616 | GET_SUBTARGETINFO_MACRO(HasVOP3Literal, false, hasVOP3Literal) |
| 617 | GET_SUBTARGETINFO_MACRO(HasVOP3PInsts, false, hasVOP3PInsts) |
| 618 | GET_SUBTARGETINFO_MACRO(HasVOP3PX2IncrementsVaVdstTwice, false, hasVOP3PX2IncrementsVaVdstTwice) |
| 619 | GET_SUBTARGETINFO_MACRO(HasVOPDInsts, false, hasVOPDInsts) |
| 620 | GET_SUBTARGETINFO_MACRO(HasVcmpxExecWARHazard, false, hasVcmpxExecWARHazard) |
| 621 | GET_SUBTARGETINFO_MACRO(HasVcmpxPermlaneHazard, false, hasVcmpxPermlaneHazard) |
| 622 | GET_SUBTARGETINFO_MACRO(HasVmemPrefInsts, false, hasVmemPrefInsts) |
| 623 | GET_SUBTARGETINFO_MACRO(HasVmemWriteVgprInOrder, false, hasVmemWriteVgprInOrder) |
| 624 | GET_SUBTARGETINFO_MACRO(HasVscnt, false, hasVscnt) |
| 625 | GET_SUBTARGETINFO_MACRO(HasWMMA128bInsts, false, hasWMMA128bInsts) |
| 626 | GET_SUBTARGETINFO_MACRO(HasWMMA256bInsts, false, hasWMMA256bInsts) |
| 627 | GET_SUBTARGETINFO_MACRO(HasWMMACoexecutionHazards, false, hasWMMACoexecutionHazards) |
| 628 | GET_SUBTARGETINFO_MACRO(HasWMMAN16Insts, false, hasWMMAN16Insts) |
| 629 | GET_SUBTARGETINFO_MACRO(HasWaitXcnt, false, hasWaitXcnt) |
| 630 | GET_SUBTARGETINFO_MACRO(HasXF32Insts, false, hasXF32Insts) |
| 631 | GET_SUBTARGETINFO_MACRO(HasXNACKOnOffModes, false, hasXNACKOnOffModes) |
| 632 | GET_SUBTARGETINFO_MACRO(RequiresAlignVGPR, false, requiresAlignVGPR) |
| 633 | GET_SUBTARGETINFO_MACRO(RequiresCOV6, false, requiresCOV6) |
| 634 | GET_SUBTARGETINFO_MACRO(RequiresWaitsBeforeSystemScopeStores, false, requiresWaitsBeforeSystemScopeStores) |
| 635 | GET_SUBTARGETINFO_MACRO(SupportsSRAMECC, false, supportsSRAMECC) |
| 636 | GET_SUBTARGETINFO_MACRO(SupportsWave32, false, supportsWave32) |
| 637 | GET_SUBTARGETINFO_MACRO(SupportsWave64, false, supportsWave64) |
| 638 | GET_SUBTARGETINFO_MACRO(SupportsXNACK, false, supportsXNACK) |
| 639 | GET_SUBTARGETINFO_MACRO(UseAddPC64Inst, false, useAddPC64Inst) |
| 640 | GET_SUBTARGETINFO_MACRO(UseBlockVGPROpsForCSR, false, useBlockVGPROpsForCSR) |
| 641 | GET_SUBTARGETINFO_MACRO(UseFlatForGlobal, false, useFlatForGlobal) |
| 642 | |
| 643 | #undef GET_SUBTARGETINFO_MACRO |
| 644 | #endif // GET_SUBTARGETINFO_MACRO |
| 645 | |
| 646 | #ifdef GET_SUBTARGETINFO_MC_DESC |
| 647 | #undef GET_SUBTARGETINFO_MC_DESC |
| 648 | |
| 649 | namespace llvm { |
| 650 | |
| 651 | // Sorted (by key) array of values for CPU features. |
| 652 | extern const llvm::SubtargetFeatureKVStorage< 324, 20809> AMDGPUFeatureKVStorage = { |
| 653 | { |
| 654 | { sizeof(SubtargetFeatureKV) * 324 + 1, sizeof(SubtargetFeatureKV) * 324 + 24, AMDGPU::Feature1024AddressableVGPRs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 655 | { sizeof(SubtargetFeatureKV) * 323 + 51, sizeof(SubtargetFeatureKV) * 323 + 71, AMDGPU::Feature1536VGPRs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 656 | { sizeof(SubtargetFeatureKV) * 322 + 104, sizeof(SubtargetFeatureKV) * 322 + 117, AMDGPU::Feature16BitInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 657 | { sizeof(SubtargetFeatureKV) * 321 + 142, sizeof(SubtargetFeatureKV) * 321 + 177, AMDGPU::Feature32BitNumRecordsBufferResource, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 658 | { sizeof(SubtargetFeatureKV) * 320 + 225, sizeof(SubtargetFeatureKV) * 320 + 260, AMDGPU::Feature45BitNumRecordsBufferResource, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 659 | { sizeof(SubtargetFeatureKV) * 319 + 308, sizeof(SubtargetFeatureKV) * 319 + 324, AMDGPU::Feature64BitLiterals, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 660 | { sizeof(SubtargetFeatureKV) * 318 + 379, sizeof(SubtargetFeatureKV) * 318 + 383, AMDGPU::FeatureA16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 661 | { sizeof(SubtargetFeatureKV) * 317 + 457, sizeof(SubtargetFeatureKV) * 317 + 475, AMDGPU::FeatureAddMinMaxInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 662 | { sizeof(SubtargetFeatureKV) * 316 + 516, sizeof(SubtargetFeatureKV) * 316 + 535, AMDGPU::FeatureAddNoCarryInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 663 | { sizeof(SubtargetFeatureKV) * 315 + 584, sizeof(SubtargetFeatureKV) * 315 + 602, AMDGPU::FeatureAddSubU64Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 664 | { sizeof(SubtargetFeatureKV) * 314 + 643, sizeof(SubtargetFeatureKV) * 314 + 676, AMDGPU::FeatureAddressableLocalMemorySize163840, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 665 | { sizeof(SubtargetFeatureKV) * 313 + 710, sizeof(SubtargetFeatureKV) * 313 + 676, AMDGPU::FeatureAddressableLocalMemorySize196608, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 666 | { sizeof(SubtargetFeatureKV) * 312 + 743, sizeof(SubtargetFeatureKV) * 312 + 676, AMDGPU::FeatureAddressableLocalMemorySize32768, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 667 | { sizeof(SubtargetFeatureKV) * 311 + 775, sizeof(SubtargetFeatureKV) * 311 + 676, AMDGPU::FeatureAddressableLocalMemorySize327680, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 668 | { sizeof(SubtargetFeatureKV) * 310 + 808, sizeof(SubtargetFeatureKV) * 310 + 676, AMDGPU::FeatureAddressableLocalMemorySize65536, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 669 | { sizeof(SubtargetFeatureKV) * 309 + 840, sizeof(SubtargetFeatureKV) * 309 + 887, AMDGPU::FeatureAgentScopeFineGrainedRemoteMemoryAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 670 | { sizeof(SubtargetFeatureKV) * 308 + 1092, sizeof(SubtargetFeatureKV) * 308 + 1106, AMDGPU::FeatureApertureRegs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 671 | { sizeof(SubtargetFeatureKV) * 307 + 1150, sizeof(SubtargetFeatureKV) * 307 + 1175, AMDGPU::FeatureArchitectedFlatScratch, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 672 | { sizeof(SubtargetFeatureKV) * 306 + 1248, sizeof(SubtargetFeatureKV) * 306 + 1266, AMDGPU::FeatureArchitectedSGPRs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 673 | { sizeof(SubtargetFeatureKV) * 305 + 1295, sizeof(SubtargetFeatureKV) * 305 + 1309, AMDGPU::FeatureAshrPkInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 674 | { sizeof(SubtargetFeatureKV) * 304 + 1348, sizeof(SubtargetFeatureKV) * 304 + 1378, AMDGPU::FeatureAssemblerPermissiveWavesize, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 675 | { sizeof(SubtargetFeatureKV) * 303 + 1435, sizeof(SubtargetFeatureKV) * 303 + 1459, AMDGPU::FeatureAsyncLoadToLDSInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 676 | { sizeof(SubtargetFeatureKV) * 302 + 1501, sizeof(SubtargetFeatureKV) * 302 + 1528, AMDGPU::FeatureAsyncStoreFromLDSInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 677 | { sizeof(SubtargetFeatureKV) * 301 + 1573, sizeof(SubtargetFeatureKV) * 301 + 1582, AMDGPU::FeatureAsynccnt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 678 | { sizeof(SubtargetFeatureKV) * 300 + 1612, sizeof(SubtargetFeatureKV) * 300 + 1650, AMDGPU::FeatureAtomicBufferGlobalPkAddF16Insts, { { { 0x0ULL, 0x2000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 679 | { sizeof(SubtargetFeatureKV) * 299 + 1752, sizeof(SubtargetFeatureKV) * 299 + 1797, AMDGPU::FeatureAtomicBufferGlobalPkAddF16NoRtnInsts, { { { 0x0ULL, 0x2000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 680 | { sizeof(SubtargetFeatureKV) * 298 + 1901, sizeof(SubtargetFeatureKV) * 298 + 1932, AMDGPU::FeatureAtomicBufferPkAddBF16Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 681 | { sizeof(SubtargetFeatureKV) * 297 + 1974, sizeof(SubtargetFeatureKV) * 297 + 1999, AMDGPU::FeatureAtomicCSubNoRtnInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 682 | { sizeof(SubtargetFeatureKV) * 296 + 2091, sizeof(SubtargetFeatureKV) * 296 + 2117, AMDGPU::FeatureAtomicDsPkAdd16Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 683 | { sizeof(SubtargetFeatureKV) * 295 + 2203, sizeof(SubtargetFeatureKV) * 295 + 2228, AMDGPU::FeatureAtomicFaddNoRtnInsts, { { { 0x0ULL, 0x2000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 684 | { sizeof(SubtargetFeatureKV) * 294 + 2326, sizeof(SubtargetFeatureKV) * 294 + 2348, AMDGPU::FeatureAtomicFaddRtnInsts, { { { 0x0ULL, 0x2000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 685 | { sizeof(SubtargetFeatureKV) * 293 + 2440, sizeof(SubtargetFeatureKV) * 293 + 2468, AMDGPU::FeatureAtomicFlatPkAdd16Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 686 | { sizeof(SubtargetFeatureKV) * 292 + 2536, sizeof(SubtargetFeatureKV) * 292 + 2562, AMDGPU::FeatureAtomicFMinFMaxF32FlatInsts, { { { 0x0ULL, 0x200000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 687 | { sizeof(SubtargetFeatureKV) * 291 + 2625, sizeof(SubtargetFeatureKV) * 291 + 2651, AMDGPU::FeatureAtomicFMinFMaxF64FlatInsts, { { { 0x0ULL, 0x200000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 688 | { sizeof(SubtargetFeatureKV) * 290 + 2715, sizeof(SubtargetFeatureKV) * 290 + 2743, AMDGPU::FeatureAtomicFMinFMaxF32GlobalInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 689 | { sizeof(SubtargetFeatureKV) * 289 + 2808, sizeof(SubtargetFeatureKV) * 289 + 2743, AMDGPU::FeatureAtomicFMinFMaxF64GlobalInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 690 | { sizeof(SubtargetFeatureKV) * 288 + 2836, sizeof(SubtargetFeatureKV) * 288 + 2867, AMDGPU::FeatureAtomicGlobalPkAddBF16Inst, { { { 0x0ULL, 0x2000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 691 | { sizeof(SubtargetFeatureKV) * 287 + 2909, sizeof(SubtargetFeatureKV) * 287 + 2937, AMDGPU::FeatureAutoWaitcntBeforeBarrier, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 692 | { sizeof(SubtargetFeatureKV) * 286 + 2991, sizeof(SubtargetFeatureKV) * 286 + 3008, AMDGPU::FeatureBackOffBarrier, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 693 | { sizeof(SubtargetFeatureKV) * 285 + 3071, sizeof(SubtargetFeatureKV) * 285 + 3086, AMDGPU::FeatureBF16ConversionInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 694 | { sizeof(SubtargetFeatureKV) * 284 + 3119, sizeof(SubtargetFeatureKV) * 284 + 3140, AMDGPU::FeatureBF16InlineConstFromUpperFP32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 695 | { sizeof(SubtargetFeatureKV) * 283 + 3213, sizeof(SubtargetFeatureKV) * 283 + 3227, AMDGPU::FeatureBF16PackedInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 696 | { sizeof(SubtargetFeatureKV) * 282 + 3282, sizeof(SubtargetFeatureKV) * 282 + 3299, AMDGPU::FeatureBF16TransInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 697 | { sizeof(SubtargetFeatureKV) * 281 + 3336, sizeof(SubtargetFeatureKV) * 281 + 3356, AMDGPU::FeatureBF8ConversionScaleInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 698 | { sizeof(SubtargetFeatureKV) * 280 + 3394, sizeof(SubtargetFeatureKV) * 280 + 3407, AMDGPU::FeatureBitOp3Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 699 | { sizeof(SubtargetFeatureKV) * 279 + 3450, sizeof(SubtargetFeatureKV) * 279 + 3465, AMDGPU::FeatureUseBlockVGPROpsForCSR, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 700 | { sizeof(SubtargetFeatureKV) * 278 + 3518, sizeof(SubtargetFeatureKV) * 278 + 3539, AMDGPU::FeatureBVHDualAndBVH8Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 701 | { sizeof(SubtargetFeatureKV) * 277 + 3614, sizeof(SubtargetFeatureKV) * 277 + 3636, AMDGPU::FeatureBVHRayTracingInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 702 | { sizeof(SubtargetFeatureKV) * 276 + 3669, sizeof(SubtargetFeatureKV) * 276 + 3678, AMDGPU::FeatureCIInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 703 | { sizeof(SubtargetFeatureKV) * 275 + 3710, sizeof(SubtargetFeatureKV) * 275 + 3719, AMDGPU::FeatureClusters, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 704 | { sizeof(SubtargetFeatureKV) * 274 + 3754, sizeof(SubtargetFeatureKV) * 274 + 3765, AMDGPU::FeatureCubeInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 705 | { sizeof(SubtargetFeatureKV) * 273 + 3790, sizeof(SubtargetFeatureKV) * 273 + 3797, AMDGPU::FeatureCuMode, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 706 | { sizeof(SubtargetFeatureKV) * 272 + 3832, sizeof(SubtargetFeatureKV) * 272 + 3849, AMDGPU::FeatureCvtFP8ByteSel, { { { 0x0ULL, 0x2000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 707 | { sizeof(SubtargetFeatureKV) * 271 + 3913, sizeof(SubtargetFeatureKV) * 271 + 3934, AMDGPU::FeatureCvtFP8SDWASrcSel, { { { 0x0ULL, 0x2000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 708 | { sizeof(SubtargetFeatureKV) * 270 + 4013, sizeof(SubtargetFeatureKV) * 270 + 4030, AMDGPU::FeatureCvtFP8VOP1Bug, { { { 0x0ULL, 0x2000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 709 | { sizeof(SubtargetFeatureKV) * 269 + 4083, sizeof(SubtargetFeatureKV) * 269 + 4098, AMDGPU::FeatureCvtNormInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 710 | { sizeof(SubtargetFeatureKV) * 268 + 4127, sizeof(SubtargetFeatureKV) * 268 + 4147, AMDGPU::FeatureCvtPkF16F32Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 711 | { sizeof(SubtargetFeatureKV) * 267 + 4178, sizeof(SubtargetFeatureKV) * 267 + 4200, AMDGPU::FeatureCvtPkNormVOP2Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 712 | { sizeof(SubtargetFeatureKV) * 266 + 4273, sizeof(SubtargetFeatureKV) * 266 + 4200, AMDGPU::FeatureCvtPkNormVOP3Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 713 | { sizeof(SubtargetFeatureKV) * 265 + 4295, sizeof(SubtargetFeatureKV) * 265 + 4319, AMDGPU::FeatureCvtSrPkBF16F32Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 714 | { sizeof(SubtargetFeatureKV) * 264 + 4354, sizeof(SubtargetFeatureKV) * 264 + 4371, AMDGPU::FeatureD16Writes32BitVgpr, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 715 | { sizeof(SubtargetFeatureKV) * 263 + 4430, sizeof(SubtargetFeatureKV) * 263 + 4451, AMDGPU::FeatureDataCacheLineSize128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 716 | { sizeof(SubtargetFeatureKV) * 262 + 4489, sizeof(SubtargetFeatureKV) * 262 + 4517, AMDGPU::FeatureDefaultComponentBroadcast, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 717 | { sizeof(SubtargetFeatureKV) * 261 + 4599, sizeof(SubtargetFeatureKV) * 261 + 4622, AMDGPU::FeatureDefaultComponentZero, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 718 | { sizeof(SubtargetFeatureKV) * 260 + 4704, sizeof(SubtargetFeatureKV) * 260 + 4713, AMDGPU::FeatureDLInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 719 | { sizeof(SubtargetFeatureKV) * 259 + 4756, sizeof(SubtargetFeatureKV) * 259 + 4767, AMDGPU::FeatureDot1Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 720 | { sizeof(SubtargetFeatureKV) * 258 + 4816, sizeof(SubtargetFeatureKV) * 258 + 4828, AMDGPU::FeatureDot10Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 721 | { sizeof(SubtargetFeatureKV) * 257 + 4859, sizeof(SubtargetFeatureKV) * 257 + 4871, AMDGPU::FeatureDot11Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 722 | { sizeof(SubtargetFeatureKV) * 256 + 4967, sizeof(SubtargetFeatureKV) * 256 + 4979, AMDGPU::FeatureDot12Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 723 | { sizeof(SubtargetFeatureKV) * 255 + 5012, sizeof(SubtargetFeatureKV) * 255 + 5024, AMDGPU::FeatureDot13Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 724 | { sizeof(SubtargetFeatureKV) * 254 + 5058, sizeof(SubtargetFeatureKV) * 254 + 5069, AMDGPU::FeatureDot2Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 725 | { sizeof(SubtargetFeatureKV) * 253 + 5117, sizeof(SubtargetFeatureKV) * 253 + 5128, AMDGPU::FeatureDot3Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 726 | { sizeof(SubtargetFeatureKV) * 252 + 5159, sizeof(SubtargetFeatureKV) * 252 + 5170, AMDGPU::FeatureDot4Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 727 | { sizeof(SubtargetFeatureKV) * 251 + 5202, sizeof(SubtargetFeatureKV) * 251 + 5213, AMDGPU::FeatureDot5Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 728 | { sizeof(SubtargetFeatureKV) * 250 + 5245, sizeof(SubtargetFeatureKV) * 250 + 5256, AMDGPU::FeatureDot6Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 729 | { sizeof(SubtargetFeatureKV) * 249 + 5287, sizeof(SubtargetFeatureKV) * 249 + 5298, AMDGPU::FeatureDot7Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 730 | { sizeof(SubtargetFeatureKV) * 248 + 5344, sizeof(SubtargetFeatureKV) * 248 + 5355, AMDGPU::FeatureDot8Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 731 | { sizeof(SubtargetFeatureKV) * 247 + 5403, sizeof(SubtargetFeatureKV) * 247 + 5414, AMDGPU::FeatureDot9Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 732 | { sizeof(SubtargetFeatureKV) * 246 + 5464, sizeof(SubtargetFeatureKV) * 246 + 5468, AMDGPU::FeatureDPP, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 733 | { sizeof(SubtargetFeatureKV) * 245 + 5517, sizeof(SubtargetFeatureKV) * 245 + 5527, AMDGPU::FeatureDPALU_DPP, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 734 | { sizeof(SubtargetFeatureKV) * 244 + 5586, sizeof(SubtargetFeatureKV) * 244 + 5600, AMDGPU::FeatureDPPBroadcasts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 735 | { sizeof(SubtargetFeatureKV) * 243 + 5636, sizeof(SubtargetFeatureKV) * 243 + 5650, AMDGPU::FeatureDPPSrc1SGPR, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 736 | { sizeof(SubtargetFeatureKV) * 242 + 5692, sizeof(SubtargetFeatureKV) * 242 + 5713, AMDGPU::FeatureDPPWavefrontShifts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 737 | { sizeof(SubtargetFeatureKV) * 241 + 5761, sizeof(SubtargetFeatureKV) * 241 + 5766, AMDGPU::FeatureDPP8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 738 | { sizeof(SubtargetFeatureKV) * 240 + 5816, sizeof(SubtargetFeatureKV) * 240 + 5830, AMDGPU::FeatureDsSrc2Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 739 | { sizeof(SubtargetFeatureKV) * 239 + 5857, sizeof(SubtargetFeatureKV) * 239 + 5866, AMDGPU::FeatureDumpCodeLower, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 740 | { sizeof(SubtargetFeatureKV) * 238 + 5904, sizeof(SubtargetFeatureKV) * 238 + 5929, AMDGPU::FeatureDX10ClampAndIEEEMode, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 741 | { sizeof(SubtargetFeatureKV) * 237 + 5988, sizeof(SubtargetFeatureKV) * 237 + 6018, AMDGPU::FeatureEmulatedSystemScopeAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 742 | { sizeof(SubtargetFeatureKV) * 236 + 6112, sizeof(SubtargetFeatureKV) * 236 + 6125, AMDGPU::FeatureEnableDS128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 743 | { sizeof(SubtargetFeatureKV) * 235 + 6150, sizeof(SubtargetFeatureKV) * 235 + 6170, AMDGPU::FeatureEnableFlatScratch, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 744 | { sizeof(SubtargetFeatureKV) * 234 + 6227, sizeof(SubtargetFeatureKV) * 234 + 6250, AMDGPU::FeatureEnablePRTStrictNull, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 745 | { sizeof(SubtargetFeatureKV) * 233 + 6312, sizeof(SubtargetFeatureKV) * 233 + 6333, AMDGPU::FeatureExtendedImageInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 746 | { sizeof(SubtargetFeatureKV) * 232 + 6383, sizeof(SubtargetFeatureKV) * 232 + 6408, AMDGPU::FeatureF16FP8ConversionInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 747 | { sizeof(SubtargetFeatureKV) * 231 + 6455, sizeof(SubtargetFeatureKV) * 231 + 6489, AMDGPU::FeatureF16BF16ToFP6BF6ConversionScaleInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 748 | { sizeof(SubtargetFeatureKV) * 230 + 6541, sizeof(SubtargetFeatureKV) * 230 + 6569, AMDGPU::FeatureF32ToF16BF16ConversionSRInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 749 | { sizeof(SubtargetFeatureKV) * 229 + 6618, sizeof(SubtargetFeatureKV) * 229 + 6648, AMDGPU::FeatureF32ToFP6BF6ConversionScaleInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 750 | { sizeof(SubtargetFeatureKV) * 228 + 6696, sizeof(SubtargetFeatureKV) * 228 + 6714, AMDGPU::FeatureFastDenormalF32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 751 | { sizeof(SubtargetFeatureKV) * 227 + 6785, sizeof(SubtargetFeatureKV) * 227 + 6795, AMDGPU::FeatureFastFMAF32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 752 | { sizeof(SubtargetFeatureKV) * 226 + 6845, sizeof(SubtargetFeatureKV) * 226 + 6864, AMDGPU::FeatureFlatAddressSpace, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 753 | { sizeof(SubtargetFeatureKV) * 225 + 6891, sizeof(SubtargetFeatureKV) * 225 + 6917, AMDGPU::FeatureFlatAtomicFaddF32Inst, { { { 0x0ULL, 0x200000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 754 | { sizeof(SubtargetFeatureKV) * 224 + 6953, sizeof(SubtargetFeatureKV) * 224 + 6986, AMDGPU::FeatureFlatBufferGlobalAtomicFaddF64Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 755 | { sizeof(SubtargetFeatureKV) * 223 + 7048, sizeof(SubtargetFeatureKV) * 223 + 7064, AMDGPU::FeatureUseFlatForGlobal, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 756 | { sizeof(SubtargetFeatureKV) * 222 + 7110, sizeof(SubtargetFeatureKV) * 222 + 7128, AMDGPU::FeatureFlatGlobalInsts, { { { 0x0ULL, 0x200000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 757 | { sizeof(SubtargetFeatureKV) * 221 + 7167, sizeof(SubtargetFeatureKV) * 221 + 7181, AMDGPU::FeatureFlatGVSMode, { { { 0x0ULL, 0x200000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 758 | { sizeof(SubtargetFeatureKV) * 220 + 7231, sizeof(SubtargetFeatureKV) * 220 + 7249, AMDGPU::FeatureFlatInstOffsets, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 759 | { sizeof(SubtargetFeatureKV) * 219 + 7305, sizeof(SubtargetFeatureKV) * 219 + 7325, AMDGPU::FeatureFlatOffsetBits12, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 760 | { sizeof(SubtargetFeatureKV) * 218 + 7365, sizeof(SubtargetFeatureKV) * 218 + 7325, AMDGPU::FeatureFlatOffsetBits24, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 761 | { sizeof(SubtargetFeatureKV) * 217 + 7385, sizeof(SubtargetFeatureKV) * 217 + 7404, AMDGPU::FeatureFlatScratchInsts, { { { 0x0ULL, 0x200000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 762 | { sizeof(SubtargetFeatureKV) * 216 + 7444, sizeof(SubtargetFeatureKV) * 216 + 7468, AMDGPU::FeatureFlatSegmentOffsetBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 763 | { sizeof(SubtargetFeatureKV) * 215 + 7551, sizeof(SubtargetFeatureKV) * 215 + 7570, AMDGPU::FeatureFlatSignedOffset, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 764 | { sizeof(SubtargetFeatureKV) * 214 + 7626, sizeof(SubtargetFeatureKV) * 214 + 7645, AMDGPU::FeatureFmaLegacy32Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 765 | { sizeof(SubtargetFeatureKV) * 213 + 7690, sizeof(SubtargetFeatureKV) * 213 + 7709, AMDGPU::FeatureFmaMixBF16Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 766 | { sizeof(SubtargetFeatureKV) * 212 + 7781, sizeof(SubtargetFeatureKV) * 212 + 7795, AMDGPU::FeatureFmaMixInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 767 | { sizeof(SubtargetFeatureKV) * 211 + 7860, sizeof(SubtargetFeatureKV) * 211 + 7873, AMDGPU::FeatureFmacF64Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 768 | { sizeof(SubtargetFeatureKV) * 210 + 7900, sizeof(SubtargetFeatureKV) * 210 + 7905, AMDGPU::FeatureFMA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 769 | { sizeof(SubtargetFeatureKV) * 209 + 7969, sizeof(SubtargetFeatureKV) * 209 + 7991, AMDGPU::FeatureFormattedMUBUFInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 770 | { sizeof(SubtargetFeatureKV) * 208 + 8041, sizeof(SubtargetFeatureKV) * 208 + 8061, AMDGPU::FeatureFP4ConversionScaleInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 771 | { sizeof(SubtargetFeatureKV) * 207 + 8099, sizeof(SubtargetFeatureKV) * 207 + 8104, AMDGPU::FeatureFP64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 772 | { sizeof(SubtargetFeatureKV) * 206 + 8139, sizeof(SubtargetFeatureKV) * 206 + 8162, AMDGPU::FeatureFP6BF6ConversionScaleInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 773 | { sizeof(SubtargetFeatureKV) * 205 + 8208, sizeof(SubtargetFeatureKV) * 205 + 8229, AMDGPU::FeatureFP8ConversionInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 774 | { sizeof(SubtargetFeatureKV) * 204 + 8269, sizeof(SubtargetFeatureKV) * 204 + 8289, AMDGPU::FeatureFP8ConversionScaleInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 775 | { sizeof(SubtargetFeatureKV) * 203 + 8327, sizeof(SubtargetFeatureKV) * 203 + 8352, AMDGPU::FeatureFP8F16ConversionInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 776 | { sizeof(SubtargetFeatureKV) * 202 + 8399, sizeof(SubtargetFeatureKV) * 202 + 8409, AMDGPU::FeatureFP8Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 777 | { sizeof(SubtargetFeatureKV) * 201 + 8438, sizeof(SubtargetFeatureKV) * 201 + 8452, AMDGPU::FeatureFP8E5M3Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 778 | { sizeof(SubtargetFeatureKV) * 200 + 8480, sizeof(SubtargetFeatureKV) * 200 + 8497, AMDGPU::FeatureFullRate64Ops, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 779 | { sizeof(SubtargetFeatureKV) * 199 + 8534, sizeof(SubtargetFeatureKV) * 199 + 8538, AMDGPU::FeatureG16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 780 | { sizeof(SubtargetFeatureKV) * 198 + 8585, sizeof(SubtargetFeatureKV) * 198 + 8599, AMDGPU::FeatureGCN3Encoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 781 | { sizeof(SubtargetFeatureKV) * 197 + 8622, sizeof(SubtargetFeatureKV) * 197 + 8626, AMDGPU::FeatureGDS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 782 | { sizeof(SubtargetFeatureKV) * 196 + 8648, sizeof(SubtargetFeatureKV) * 196 + 8665, AMDGPU::FeatureGetWaveIdInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 783 | { sizeof(SubtargetFeatureKV) * 195 + 8707, sizeof(SubtargetFeatureKV) * 195 + 8713, AMDGPU::FeatureGFX10, { { { 0xc3448001e0010943ULL, 0x542e3c0020000048ULL, 0x412101944800055ULL, 0x66a0040880501e00ULL, 0xa0c80700380010ULL, 0x0ULL, 0x0ULL, } } } }, |
| 784 | { sizeof(SubtargetFeatureKV) * 194 + 8734, sizeof(SubtargetFeatureKV) * 194 + 8748, AMDGPU::FeatureGFX10_3Insts, { { { 0x0ULL, 0x100000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 785 | { sizeof(SubtargetFeatureKV) * 193 + 8784, sizeof(SubtargetFeatureKV) * 193 + 8796, AMDGPU::FeatureGFX10Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 786 | { sizeof(SubtargetFeatureKV) * 192 + 8831, sizeof(SubtargetFeatureKV) * 192 + 8848, AMDGPU::FeatureGFX10_BEncoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 787 | { sizeof(SubtargetFeatureKV) * 191 + 8872, sizeof(SubtargetFeatureKV) * 191 + 8878, AMDGPU::FeatureGFX11, { { { 0xc344900060010943ULL, 0x54263c0020000040ULL, 0x21a101a048005d5ULL, 0x40880501e01ULL, 0xa2c00740380010ULL, 0x0ULL, 0x0ULL, } } } }, |
| 788 | { sizeof(SubtargetFeatureKV) * 190 + 8899, sizeof(SubtargetFeatureKV) * 190 + 8913, AMDGPU::FeatureGFX11_7Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 789 | { sizeof(SubtargetFeatureKV) * 189 + 8949, sizeof(SubtargetFeatureKV) * 189 + 8961, AMDGPU::FeatureGFX11Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 790 | { sizeof(SubtargetFeatureKV) * 188 + 8996, sizeof(SubtargetFeatureKV) * 188 + 9002, AMDGPU::FeatureGFX12, { { { 0xc000800060018143ULL, 0x44b63c0000000020ULL, 0x202001a100025d4ULL, 0x80008805002c1ULL, 0x82c00740100000ULL, 0x0ULL, 0x0ULL, } } } }, |
| 791 | { sizeof(SubtargetFeatureKV) * 187 + 9023, sizeof(SubtargetFeatureKV) * 187 + 9035, AMDGPU::FeatureGFX12Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 792 | { sizeof(SubtargetFeatureKV) * 186 + 9070, sizeof(SubtargetFeatureKV) * 186 + 9084, AMDGPU::FeatureGFX1250Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 793 | { sizeof(SubtargetFeatureKV) * 185 + 9121, sizeof(SubtargetFeatureKV) * 185 + 9136, AMDGPU::FeatureGFX1250_STRICT, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 794 | { sizeof(SubtargetFeatureKV) * 184 + 9156, sizeof(SubtargetFeatureKV) * 184 + 9175, AMDGPU::FeatureGFX1251GEMMInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 795 | { sizeof(SubtargetFeatureKV) * 183 + 9217, sizeof(SubtargetFeatureKV) * 183 + 9242, AMDGPU::FeatureGFX125xLowestRateWMMA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 796 | { sizeof(SubtargetFeatureKV) * 182 + 9321, sizeof(SubtargetFeatureKV) * 182 + 9327, AMDGPU::FeatureGFX13, { { { 0xc000800060018145ULL, 0x54b63c0020000020ULL, 0x21a001a5000a5d4ULL, 0x80008805002c1ULL, 0x82c00740380000ULL, 0x0ULL, 0x0ULL, } } } }, |
| 797 | { sizeof(SubtargetFeatureKV) * 181 + 9348, sizeof(SubtargetFeatureKV) * 181 + 9360, AMDGPU::FeatureGFX13Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x10000000000000ULL, 0x8ULL, 0x0ULL, 0x0ULL, } } } }, |
| 798 | { sizeof(SubtargetFeatureKV) * 180 + 9395, sizeof(SubtargetFeatureKV) * 180 + 9416, AMDGPU::FeatureGFX7GFX8GFX9Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 799 | { sizeof(SubtargetFeatureKV) * 179 + 9456, sizeof(SubtargetFeatureKV) * 179 + 9467, AMDGPU::FeatureGFX8Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 800 | { sizeof(SubtargetFeatureKV) * 178 + 9501, sizeof(SubtargetFeatureKV) * 178 + 9506, AMDGPU::FeatureGFX9, { { { 0x4340800000010143ULL, 0x90263c000000004dULL, 0x10101900800016ULL, 0x66a00c0000041c00ULL, 0x208a0700200690ULL, 0x9ULL, 0x0ULL, } } } }, |
| 801 | { sizeof(SubtargetFeatureKV) * 177 + 9526, sizeof(SubtargetFeatureKV) * 177 + 9537, AMDGPU::FeatureGFX9Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 802 | { sizeof(SubtargetFeatureKV) * 176 + 9571, sizeof(SubtargetFeatureKV) * 176 + 9584, AMDGPU::FeatureGFX90AInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 803 | { sizeof(SubtargetFeatureKV) * 175 + 9620, sizeof(SubtargetFeatureKV) * 175 + 9633, AMDGPU::FeatureGFX940Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 804 | { sizeof(SubtargetFeatureKV) * 174 + 9669, sizeof(SubtargetFeatureKV) * 174 + 9682, AMDGPU::FeatureGFX950Insts, { { { 0x80004000080000ULL, 0x5940000000ULL, 0x0ULL, 0x300000180ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 805 | { sizeof(SubtargetFeatureKV) * 173 + 9718, sizeof(SubtargetFeatureKV) * 173 + 9747, AMDGPU::FeatureGloballyAddressableScratch, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 806 | { sizeof(SubtargetFeatureKV) * 172 + 9818, sizeof(SubtargetFeatureKV) * 172 + 9822, AMDGPU::FeatureGWS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 807 | { sizeof(SubtargetFeatureKV) * 171 + 9843, sizeof(SubtargetFeatureKV) * 171 + 9882, AMDGPU::FeatureHalfAddressablePhysicalLocalMemory, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 808 | { sizeof(SubtargetFeatureKV) * 170 + 9943, sizeof(SubtargetFeatureKV) * 170 + 9960, AMDGPU::FeatureHalfRate64Ops, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 809 | { sizeof(SubtargetFeatureKV) * 169 + 10016, sizeof(SubtargetFeatureKV) * 169 + 10043, AMDGPU::FeatureIEEEMinimumMaximumInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 810 | { sizeof(SubtargetFeatureKV) * 168 + 10159, sizeof(SubtargetFeatureKV) * 168 + 10181, AMDGPU::FeatureImageGather4D16Bug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 811 | { sizeof(SubtargetFeatureKV) * 167 + 10212, sizeof(SubtargetFeatureKV) * 167 + 10224, AMDGPU::FeatureImageInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 812 | { sizeof(SubtargetFeatureKV) * 166 + 10251, sizeof(SubtargetFeatureKV) * 166 + 10271, AMDGPU::FeatureImageStoreD16Bug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 813 | { sizeof(SubtargetFeatureKV) * 165 + 10300, sizeof(SubtargetFeatureKV) * 165 + 10322, AMDGPU::FeatureInstFwdPrefetchBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 814 | { sizeof(SubtargetFeatureKV) * 164 + 10372, sizeof(SubtargetFeatureKV) * 164 + 10393, AMDGPU::FeatureInstCacheLineSize128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 815 | { sizeof(SubtargetFeatureKV) * 163 + 10431, sizeof(SubtargetFeatureKV) * 163 + 10393, AMDGPU::FeatureInstCacheLineSize64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 816 | { sizeof(SubtargetFeatureKV) * 162 + 10451, sizeof(SubtargetFeatureKV) * 162 + 10467, AMDGPU::FeatureIntClamp, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 817 | { sizeof(SubtargetFeatureKV) * 161 + 10505, sizeof(SubtargetFeatureKV) * 161 + 10524, AMDGPU::FeatureInv2PiInlineImm, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 818 | { sizeof(SubtargetFeatureKV) * 160 + 10561, sizeof(SubtargetFeatureKV) * 160 + 10577, AMDGPU::FeatureKernargPreload, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 819 | { sizeof(SubtargetFeatureKV) * 159 + 10641, sizeof(SubtargetFeatureKV) * 159 + 10660, AMDGPU::FeatureLdsAtomicAddF64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 820 | { sizeof(SubtargetFeatureKV) * 158 + 10707, sizeof(SubtargetFeatureKV) * 158 + 10733, AMDGPU::FeatureLdsBarrierArriveAtomic, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 821 | { sizeof(SubtargetFeatureKV) * 157 + 10776, sizeof(SubtargetFeatureKV) * 157 + 10803, AMDGPU::FeatureLdsBranchVmemWARHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 822 | { sizeof(SubtargetFeatureKV) * 156 + 10860, sizeof(SubtargetFeatureKV) * 156 + 10879, AMDGPU::FeatureLDSMisalignedBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 823 | { sizeof(SubtargetFeatureKV) * 155 + 10973, sizeof(SubtargetFeatureKV) * 155 + 10988, AMDGPU::FeatureLDSBankCount16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 824 | { sizeof(SubtargetFeatureKV) * 154 + 11030, sizeof(SubtargetFeatureKV) * 154 + 10988, AMDGPU::FeatureLDSBankCount32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 825 | { sizeof(SubtargetFeatureKV) * 153 + 11045, sizeof(SubtargetFeatureKV) * 153 + 11055, AMDGPU::FeatureLerpInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 826 | { sizeof(SubtargetFeatureKV) * 152 + 11081, sizeof(SubtargetFeatureKV) * 152 + 11096, AMDGPU::FeatureEnableLoadStoreOpt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 827 | { sizeof(SubtargetFeatureKV) * 151 + 11132, sizeof(SubtargetFeatureKV) * 151 + 11150, AMDGPU::FeatureLshlAddU64Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 828 | { sizeof(SubtargetFeatureKV) * 150 + 11181, sizeof(SubtargetFeatureKV) * 150 + 11199, AMDGPU::FeatureMADIntraFwdBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 829 | { sizeof(SubtargetFeatureKV) * 149 + 11244, sizeof(SubtargetFeatureKV) * 149 + 11262, AMDGPU::FeatureMadMacF32Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 830 | { sizeof(SubtargetFeatureKV) * 148 + 11323, sizeof(SubtargetFeatureKV) * 148 + 11337, AMDGPU::FeatureMadMixInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 831 | { sizeof(SubtargetFeatureKV) * 147 + 11402, sizeof(SubtargetFeatureKV) * 147 + 11421, AMDGPU::FeatureMadNC64_32Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 832 | { sizeof(SubtargetFeatureKV) * 146 + 11465, sizeof(SubtargetFeatureKV) * 146 + 11478, AMDGPU::FeatureMadU32Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 833 | { sizeof(SubtargetFeatureKV) * 145 + 11504, sizeof(SubtargetFeatureKV) * 145 + 11514, AMDGPU::FeatureMAIInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 834 | { sizeof(SubtargetFeatureKV) * 144 + 11535, sizeof(SubtargetFeatureKV) * 144 + 11561, AMDGPU::FeatureMaxHardClauseLength32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 835 | { sizeof(SubtargetFeatureKV) * 143 + 11622, sizeof(SubtargetFeatureKV) * 143 + 11648, AMDGPU::FeatureMaxHardClauseLength63, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 836 | { sizeof(SubtargetFeatureKV) * 142 + 11709, sizeof(SubtargetFeatureKV) * 142 + 11737, AMDGPU::FeatureMaxPrivateElementSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 837 | { sizeof(SubtargetFeatureKV) * 141 + 11775, sizeof(SubtargetFeatureKV) * 141 + 11802, AMDGPU::FeatureMaxPrivateElementSize4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 838 | { sizeof(SubtargetFeatureKV) * 140 + 11839, sizeof(SubtargetFeatureKV) * 140 + 11866, AMDGPU::FeatureMaxPrivateElementSize8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 839 | { sizeof(SubtargetFeatureKV) * 139 + 11903, sizeof(SubtargetFeatureKV) * 139 + 11923, AMDGPU::FeatureMaxWavesPerEU10, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 840 | { sizeof(SubtargetFeatureKV) * 138 + 11975, sizeof(SubtargetFeatureKV) * 138 + 11923, AMDGPU::FeatureMaxWavesPerEU16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 841 | { sizeof(SubtargetFeatureKV) * 137 + 11995, sizeof(SubtargetFeatureKV) * 137 + 11923, AMDGPU::FeatureMaxWavesPerEU20, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 842 | { sizeof(SubtargetFeatureKV) * 136 + 12015, sizeof(SubtargetFeatureKV) * 136 + 11923, AMDGPU::FeatureMaxWavesPerEU8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 843 | { sizeof(SubtargetFeatureKV) * 135 + 12034, sizeof(SubtargetFeatureKV) * 135 + 12051, AMDGPU::FeatureMcastLoadInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 844 | { sizeof(SubtargetFeatureKV) * 134 + 12083, sizeof(SubtargetFeatureKV) * 134 + 12123, AMDGPU::FeatureMemoryAtomicFAddF32DenormalSupport, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 845 | { sizeof(SubtargetFeatureKV) * 133 + 12191, sizeof(SubtargetFeatureKV) * 133 + 12215, AMDGPU::FeatureMFMAInlineLiteralBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 846 | { sizeof(SubtargetFeatureKV) * 132 + 12254, sizeof(SubtargetFeatureKV) * 132 + 12264, AMDGPU::FeatureMIMG_R128, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 847 | { sizeof(SubtargetFeatureKV) * 131 + 12298, sizeof(SubtargetFeatureKV) * 131 + 12316, AMDGPU::FeatureMinMaxI64Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 848 | { sizeof(SubtargetFeatureKV) * 130 + 12353, sizeof(SubtargetFeatureKV) * 130 + 12369, AMDGPU::FeatureMin3Max3PKF16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 849 | { sizeof(SubtargetFeatureKV) * 129 + 12426, sizeof(SubtargetFeatureKV) * 129 + 12448, AMDGPU::FeatureMinimum3Maximum3F16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 850 | { sizeof(SubtargetFeatureKV) * 128 + 12499, sizeof(SubtargetFeatureKV) * 128 + 12521, AMDGPU::FeatureMinimum3Maximum3F32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 851 | { sizeof(SubtargetFeatureKV) * 127 + 12572, sizeof(SubtargetFeatureKV) * 127 + 12596, AMDGPU::FeatureMinimum3Maximum3PKF16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 852 | { sizeof(SubtargetFeatureKV) * 126 + 12653, sizeof(SubtargetFeatureKV) * 126 + 12660, AMDGPU::FeatureMovrel, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 853 | { sizeof(SubtargetFeatureKV) * 125 + 12691, sizeof(SubtargetFeatureKV) * 125 + 12703, AMDGPU::FeatureMqsadInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 854 | { sizeof(SubtargetFeatureKV) * 124 + 12734, sizeof(SubtargetFeatureKV) * 124 + 12749, AMDGPU::FeatureMqsadPkInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 855 | { sizeof(SubtargetFeatureKV) * 123 + 12783, sizeof(SubtargetFeatureKV) * 123 + 12805, AMDGPU::FeatureMSAALoadDstSelBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 856 | { sizeof(SubtargetFeatureKV) * 122 + 12841, sizeof(SubtargetFeatureKV) * 122 + 12857, AMDGPU::FeatureMSAALoadInsts, { { { 0x0ULL, 0x0ULL, 0x40000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 857 | { sizeof(SubtargetFeatureKV) * 121 + 12890, sizeof(SubtargetFeatureKV) * 121 + 12901, AMDGPU::FeatureMsadInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 858 | { sizeof(SubtargetFeatureKV) * 120 + 12927, sizeof(SubtargetFeatureKV) * 120 + 12939, AMDGPU::FeatureMTBUFInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 859 | { sizeof(SubtargetFeatureKV) * 119 + 12977, sizeof(SubtargetFeatureKV) * 119 + 13001, AMDGPU::FeatureNeedsAligned2addrDS, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 860 | { sizeof(SubtargetFeatureKV) * 118 + 13060, sizeof(SubtargetFeatureKV) * 118 + 13076, AMDGPU::FeatureNeedsTDMDrain, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 861 | { sizeof(SubtargetFeatureKV) * 117 + 13107, sizeof(SubtargetFeatureKV) * 117 + 13135, AMDGPU::FeatureNegativeScratchOffsetBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 862 | { sizeof(SubtargetFeatureKV) * 116 + 13225, sizeof(SubtargetFeatureKV) * 116 + 13263, AMDGPU::FeatureNegativeUnalignedScratchOffsetBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 863 | { sizeof(SubtargetFeatureKV) * 115 + 13389, sizeof(SubtargetFeatureKV) * 115 + 13408, AMDGPU::FeatureNoDataDepHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 864 | { sizeof(SubtargetFeatureKV) * 114 + 13436, sizeof(SubtargetFeatureKV) * 114 + 13480, AMDGPU::FeatureNoF16PseudoScalarTransInlineConstants, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 865 | { sizeof(SubtargetFeatureKV) * 113 + 13553, sizeof(SubtargetFeatureKV) * 113 + 13566, AMDGPU::FeatureNoSdstCMPX, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 866 | { sizeof(SubtargetFeatureKV) * 112 + 13617, sizeof(SubtargetFeatureKV) * 112 + 13632, AMDGPU::FeatureNSAClauseBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 867 | { sizeof(SubtargetFeatureKV) * 111 + 13695, sizeof(SubtargetFeatureKV) * 111 + 13708, AMDGPU::FeatureNSAEncoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 868 | { sizeof(SubtargetFeatureKV) * 110 + 13752, sizeof(SubtargetFeatureKV) * 110 + 13768, AMDGPU::FeatureNSAtoVMEMBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 869 | { sizeof(SubtargetFeatureKV) * 109 + 13833, sizeof(SubtargetFeatureKV) * 109 + 13858, AMDGPU::FeatureOCPFP8ConversionInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 870 | { sizeof(SubtargetFeatureKV) * 108 + 13909, sizeof(SubtargetFeatureKV) * 108 + 13923, AMDGPU::FeatureOffset3fBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 871 | { sizeof(SubtargetFeatureKV) * 107 + 13956, sizeof(SubtargetFeatureKV) * 107 + 13972, AMDGPU::FeaturePackedFP32Ops, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 872 | { sizeof(SubtargetFeatureKV) * 106 + 14005, sizeof(SubtargetFeatureKV) * 106 + 14033, AMDGPU::FeaturePackedFP32SingleSGPROps, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 873 | { sizeof(SubtargetFeatureKV) * 105 + 14116, sizeof(SubtargetFeatureKV) * 105 + 14144, AMDGPU::FeaturePackedFP64SingleSGPROps, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 874 | { sizeof(SubtargetFeatureKV) * 104 + 14227, sizeof(SubtargetFeatureKV) * 104 + 14238, AMDGPU::FeaturePackedTID, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 875 | { sizeof(SubtargetFeatureKV) * 103 + 14287, sizeof(SubtargetFeatureKV) * 103 + 14314, AMDGPU::FeaturePackedU64SingleSGPROps, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 876 | { sizeof(SubtargetFeatureKV) * 102 + 14399, sizeof(SubtargetFeatureKV) * 102 + 14420, AMDGPU::FeaturePartialNSAEncoding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 877 | { sizeof(SubtargetFeatureKV) * 101 + 14472, sizeof(SubtargetFeatureKV) * 101 + 14489, AMDGPU::FeaturePermlane16Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 878 | { sizeof(SubtargetFeatureKV) * 100 + 14541, sizeof(SubtargetFeatureKV) * 100 + 14557, AMDGPU::FeaturePermlane16Swap, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 879 | { sizeof(SubtargetFeatureKV) * 99 + 14596, sizeof(SubtargetFeatureKV) * 99 + 14612, AMDGPU::FeaturePermlane32Swap, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 880 | { sizeof(SubtargetFeatureKV) * 98 + 14651, sizeof(SubtargetFeatureKV) * 98 + 14672, AMDGPU::FeaturePkAddMinMaxInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 881 | { sizeof(SubtargetFeatureKV) * 97 + 14716, sizeof(SubtargetFeatureKV) * 97 + 14733, AMDGPU::FeaturePkFmacF16Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 882 | { sizeof(SubtargetFeatureKV) * 96 + 14763, sizeof(SubtargetFeatureKV) * 96 + 14782, AMDGPU::FeaturePointSampleAccel, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 883 | { sizeof(SubtargetFeatureKV) * 95 + 14820, sizeof(SubtargetFeatureKV) * 95 + 14841, AMDGPU::FeaturePopsExitingWaveID, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 884 | { sizeof(SubtargetFeatureKV) * 94 + 14884, sizeof(SubtargetFeatureKV) * 94 + 14899, AMDGPU::FeaturePreciseMemory, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 885 | { sizeof(SubtargetFeatureKV) * 93 + 14926, sizeof(SubtargetFeatureKV) * 93 + 14953, AMDGPU::FeaturePrivEnabledTrap2NopBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 886 | { sizeof(SubtargetFeatureKV) * 92 + 15021, sizeof(SubtargetFeatureKV) * 92 + 15031, AMDGPU::FeaturePrngInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 887 | { sizeof(SubtargetFeatureKV) * 91 + 15058, sizeof(SubtargetFeatureKV) * 91 + 15078, AMDGPU::FeaturePseudoScalarTrans, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 888 | { sizeof(SubtargetFeatureKV) * 90 + 15124, sizeof(SubtargetFeatureKV) * 90 + 15135, AMDGPU::FeatureQsadInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 889 | { sizeof(SubtargetFeatureKV) * 89 + 15160, sizeof(SubtargetFeatureKV) * 89 + 15169, AMDGPU::FeatureR128A16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 890 | { sizeof(SubtargetFeatureKV) * 88 + 15286, sizeof(SubtargetFeatureKV) * 88 + 15298, AMDGPU::FeatureRealTrue16Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 891 | { sizeof(SubtargetFeatureKV) * 87 + 15324, sizeof(SubtargetFeatureKV) * 87 + 15349, AMDGPU::FeatureRequiredExportPriority, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 892 | { sizeof(SubtargetFeatureKV) * 86 + 15407, sizeof(SubtargetFeatureKV) * 86 + 15421, AMDGPU::FeatureRequiresCOV6, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 893 | { sizeof(SubtargetFeatureKV) * 85 + 15452, sizeof(SubtargetFeatureKV) * 85 + 15483, AMDGPU::FeatureRequiresInitialUnclausedVmem, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 894 | { sizeof(SubtargetFeatureKV) * 84 + 15551, sizeof(SubtargetFeatureKV) * 84 + 15570, AMDGPU::FeatureRestrictedSOffset, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 895 | { sizeof(SubtargetFeatureKV) * 83 + 15620, sizeof(SubtargetFeatureKV) * 83 + 15640, AMDGPU::FeatureSBarrierLeaveImm, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 896 | { sizeof(SubtargetFeatureKV) * 82 + 15683, sizeof(SubtargetFeatureKV) * 82 + 15697, AMDGPU::FeatureSMemRealTime, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 897 | { sizeof(SubtargetFeatureKV) * 81 + 15727, sizeof(SubtargetFeatureKV) * 81 + 15742, AMDGPU::FeatureSMemTimeInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 898 | { sizeof(SubtargetFeatureKV) * 80 + 15768, sizeof(SubtargetFeatureKV) * 80 + 15790, AMDGPU::FeatureSWakeupBarrier, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 899 | { sizeof(SubtargetFeatureKV) * 79 + 15824, sizeof(SubtargetFeatureKV) * 79 + 15837, AMDGPU::FeatureSWakeupImm, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 900 | { sizeof(SubtargetFeatureKV) * 78 + 15873, sizeof(SubtargetFeatureKV) * 78 + 15883, AMDGPU::FeatureSadInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 901 | { sizeof(SubtargetFeatureKV) * 77 + 15907, sizeof(SubtargetFeatureKV) * 77 + 15924, AMDGPU::FeatureSafeCUPrefetch, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 902 | { sizeof(SubtargetFeatureKV) * 76 + 15980, sizeof(SubtargetFeatureKV) * 76 + 15999, AMDGPU::FeatureSafeSmemPrefetch, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 903 | { sizeof(SubtargetFeatureKV) * 75 + 16046, sizeof(SubtargetFeatureKV) * 75 + 16057, AMDGPU::FeatureSALUFloatInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 904 | { sizeof(SubtargetFeatureKV) * 74 + 16094, sizeof(SubtargetFeatureKV) * 74 + 16121, AMDGPU::FeatureSALUMinimumMaximumInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 905 | { sizeof(SubtargetFeatureKV) * 73 + 16164, sizeof(SubtargetFeatureKV) * 73 + 16179, AMDGPU::FeatureScalarAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 906 | { sizeof(SubtargetFeatureKV) * 72 + 16217, sizeof(SubtargetFeatureKV) * 72 + 16238, AMDGPU::FeatureScalarDwordx3Loads, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 907 | { sizeof(SubtargetFeatureKV) * 71 + 16274, sizeof(SubtargetFeatureKV) * 71 + 16300, AMDGPU::FeatureScalarFlatScratchInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 908 | { sizeof(SubtargetFeatureKV) * 70 + 16342, sizeof(SubtargetFeatureKV) * 70 + 16356, AMDGPU::FeatureScalarStores, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 909 | { sizeof(SubtargetFeatureKV) * 69 + 16393, sizeof(SubtargetFeatureKV) * 69 + 16398, AMDGPU::FeatureSDWA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 910 | { sizeof(SubtargetFeatureKV) * 68 + 16444, sizeof(SubtargetFeatureKV) * 68 + 16453, AMDGPU::FeatureSDWAMac, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 911 | { sizeof(SubtargetFeatureKV) * 67 + 16518, sizeof(SubtargetFeatureKV) * 67 + 16528, AMDGPU::FeatureSDWAOmod, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 912 | { sizeof(SubtargetFeatureKV) * 66 + 16584, sizeof(SubtargetFeatureKV) * 66 + 16603, AMDGPU::FeatureSDWAOutModsVOPC, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 913 | { sizeof(SubtargetFeatureKV) * 65 + 16669, sizeof(SubtargetFeatureKV) * 65 + 16681, AMDGPU::FeatureSDWAScalar, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 914 | { sizeof(SubtargetFeatureKV) * 64 + 16748, sizeof(SubtargetFeatureKV) * 64 + 16758, AMDGPU::FeatureSDWASdst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 915 | { sizeof(SubtargetFeatureKV) * 63 + 16829, sizeof(SubtargetFeatureKV) * 63 + 16841, AMDGPU::FeatureSeaIslands, { { { 0x1048001e0000802ULL, 0x1000240020100048ULL, 0x8032100140800003ULL, 0x4000040000001e00ULL, 0x20000120200010ULL, 0x1ULL, 0x0ULL, } } } }, |
| 916 | { sizeof(SubtargetFeatureKV) * 62 + 16868, sizeof(SubtargetFeatureKV) * 62 + 16888, AMDGPU::FeatureSetPrioIncWgInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 917 | { sizeof(SubtargetFeatureKV) * 61 + 16922, sizeof(SubtargetFeatureKV) * 61 + 16944, AMDGPU::FeatureSetregVGPRMSBFixup, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 918 | { sizeof(SubtargetFeatureKV) * 60 + 17000, sizeof(SubtargetFeatureKV) * 60 + 17014, AMDGPU::FeatureSGPRInitBug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 919 | { sizeof(SubtargetFeatureKV) * 59 + 17080, sizeof(SubtargetFeatureKV) * 59 + 17110, AMDGPU::FeatureShaderCyclesHiLoRegisters, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 920 | { sizeof(SubtargetFeatureKV) * 58 + 17153, sizeof(SubtargetFeatureKV) * 58 + 17176, AMDGPU::FeatureShaderCyclesRegister, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 921 | { sizeof(SubtargetFeatureKV) * 57 + 17212, sizeof(SubtargetFeatureKV) * 57 + 17225, AMDGPU::FeatureEnableSIScheduler, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 922 | { sizeof(SubtargetFeatureKV) * 56 + 17253, sizeof(SubtargetFeatureKV) * 56 + 17273, AMDGPU::FeatureSmemPrefetchInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 923 | { sizeof(SubtargetFeatureKV) * 55 + 17374, sizeof(SubtargetFeatureKV) * 55 + 17402, AMDGPU::FeatureSMEMtoVectorWriteHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 924 | { sizeof(SubtargetFeatureKV) * 54 + 17445, sizeof(SubtargetFeatureKV) * 54 + 17462, AMDGPU::FeatureSouthernIslands, { { { 0x104000140000402ULL, 0x1000040020100048ULL, 0x8032108140800001ULL, 0x4000000000001a00ULL, 0x20000020200010ULL, 0x1ULL, 0x0ULL, } } } }, |
| 925 | { sizeof(SubtargetFeatureKV) * 53 + 17494, sizeof(SubtargetFeatureKV) * 53 + 17502, AMDGPU::FeatureSRAMECC, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 926 | { sizeof(SubtargetFeatureKV) * 52 + 17517, sizeof(SubtargetFeatureKV) * 52 + 17533, AMDGPU::FeatureSupportsSRAMECC, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 927 | { sizeof(SubtargetFeatureKV) * 51 + 17559, sizeof(SubtargetFeatureKV) * 51 + 17575, AMDGPU::FeatureSupportsWave32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 928 | { sizeof(SubtargetFeatureKV) * 50 + 17605, sizeof(SubtargetFeatureKV) * 50 + 17621, AMDGPU::FeatureSupportsWave64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 929 | { sizeof(SubtargetFeatureKV) * 49 + 17651, sizeof(SubtargetFeatureKV) * 49 + 17664, AMDGPU::FeatureSupportsWGP, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 930 | { sizeof(SubtargetFeatureKV) * 48 + 17691, sizeof(SubtargetFeatureKV) * 48 + 17712, AMDGPU::FeatureSWMMACGfx1200Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 931 | { sizeof(SubtargetFeatureKV) * 47 + 17744, sizeof(SubtargetFeatureKV) * 47 + 17765, AMDGPU::FeatureSWMMACGfx1250Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 932 | { sizeof(SubtargetFeatureKV) * 46 + 17797, sizeof(SubtargetFeatureKV) * 46 + 17808, AMDGPU::FeatureTanhInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 933 | { sizeof(SubtargetFeatureKV) * 45 + 17840, sizeof(SubtargetFeatureKV) * 45 + 17861, AMDGPU::FeatureTensorCvtLutInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 934 | { sizeof(SubtargetFeatureKV) * 44 + 17891, sizeof(SubtargetFeatureKV) * 44 + 17907, AMDGPU::FeatureTgSplitSupport, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 935 | { sizeof(SubtargetFeatureKV) * 43 + 17961, sizeof(SubtargetFeatureKV) * 43 + 17986, AMDGPU::FeatureTransCoexecutionHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 936 | { sizeof(SubtargetFeatureKV) * 42 + 18044, sizeof(SubtargetFeatureKV) * 42 + 18070, AMDGPU::FeatureTransposeLoadF4F6Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 937 | { sizeof(SubtargetFeatureKV) * 41 + 18127, sizeof(SubtargetFeatureKV) * 41 + 18140, AMDGPU::FeatureTrapHandler, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 938 | { sizeof(SubtargetFeatureKV) * 40 + 18161, sizeof(SubtargetFeatureKV) * 40 + 18180, AMDGPU::FeatureTrigReducedRange, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 939 | { sizeof(SubtargetFeatureKV) * 39 + 18236, sizeof(SubtargetFeatureKV) * 39 + 18243, AMDGPU::FeatureTrue16BitInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 940 | { sizeof(SubtargetFeatureKV) * 38 + 18276, sizeof(SubtargetFeatureKV) * 38 + 18298, AMDGPU::FeatureUnalignedAccessMode, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 941 | { sizeof(SubtargetFeatureKV) * 37 + 18385, sizeof(SubtargetFeatureKV) * 37 + 18409, AMDGPU::FeatureUnalignedBufferAccess, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 942 | { sizeof(SubtargetFeatureKV) * 36 + 18461, sizeof(SubtargetFeatureKV) * 36 + 18481, AMDGPU::FeatureUnalignedDSAccess, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 943 | { sizeof(SubtargetFeatureKV) * 35 + 18543, sizeof(SubtargetFeatureKV) * 35 + 18568, AMDGPU::FeatureUnalignedScratchAccess, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 944 | { sizeof(SubtargetFeatureKV) * 34 + 18611, sizeof(SubtargetFeatureKV) * 34 + 18629, AMDGPU::FeatureUnpackedD16VMem, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 945 | { sizeof(SubtargetFeatureKV) * 33 + 18664, sizeof(SubtargetFeatureKV) * 33 + 18689, AMDGPU::FeatureEnableUnsafeDSOffsetFolding, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 946 | { sizeof(SubtargetFeatureKV) * 32 + 18740, sizeof(SubtargetFeatureKV) * 32 + 18758, AMDGPU::FeatureUseAddPC64Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 947 | { sizeof(SubtargetFeatureKV) * 31 + 18788, sizeof(SubtargetFeatureKV) * 31 + 18809, AMDGPU::FeatureUserSGPRInit16Bug, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 948 | { sizeof(SubtargetFeatureKV) * 30 + 18867, sizeof(SubtargetFeatureKV) * 30 + 18882, AMDGPU::FeatureVMovB64Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 949 | { sizeof(SubtargetFeatureKV) * 29 + 18908, sizeof(SubtargetFeatureKV) * 29 + 18923, AMDGPU::FeatureVMulU64Inst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 950 | { sizeof(SubtargetFeatureKV) * 28 + 18950, sizeof(SubtargetFeatureKV) * 28 + 18972, AMDGPU::FeatureVALUTransUseHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 951 | { sizeof(SubtargetFeatureKV) * 27 + 19047, sizeof(SubtargetFeatureKV) * 27 + 19069, AMDGPU::FeatureVcmpxExecWARHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 952 | { sizeof(SubtargetFeatureKV) * 26 + 19115, sizeof(SubtargetFeatureKV) * 26 + 19137, AMDGPU::FeatureVcmpxPermlaneHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 953 | { sizeof(SubtargetFeatureKV) * 25 + 19155, sizeof(SubtargetFeatureKV) * 25 + 19167, AMDGPU::FeatureRequiresAlignedVGPRs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 954 | { sizeof(SubtargetFeatureKV) * 24 + 19219, sizeof(SubtargetFeatureKV) * 24 + 19235, AMDGPU::FeatureVGPRIndexMode, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 955 | { sizeof(SubtargetFeatureKV) * 23 + 19267, sizeof(SubtargetFeatureKV) * 23 + 19283, AMDGPU::FeatureVmemPrefInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 956 | { sizeof(SubtargetFeatureKV) * 22 + 19339, sizeof(SubtargetFeatureKV) * 22 + 19362, AMDGPU::FeatureVMemToLDSLoad, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 957 | { sizeof(SubtargetFeatureKV) * 21 + 19519, sizeof(SubtargetFeatureKV) * 21 + 19547, AMDGPU::FeatureVMEMtoScalarWriteHazard, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 958 | { sizeof(SubtargetFeatureKV) * 20 + 19646, sizeof(SubtargetFeatureKV) * 20 + 19671, AMDGPU::FeatureVmemWriteVgprInOrder, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 959 | { sizeof(SubtargetFeatureKV) * 19 + 19734, sizeof(SubtargetFeatureKV) * 19 + 19751, AMDGPU::FeatureVolcanicIslands, { { { 0x4104800000000803ULL, 0x90002c002010004dULL, 0x8032101940800007ULL, 0x6160040000001e00ULL, 0x20020120200410ULL, 0x1ULL, 0x0ULL, } } } }, |
| 960 | { sizeof(SubtargetFeatureKV) * 18 + 19783, sizeof(SubtargetFeatureKV) * 18 + 19796, AMDGPU::FeatureVOP3Literal, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 961 | { sizeof(SubtargetFeatureKV) * 17 + 19824, sizeof(SubtargetFeatureKV) * 17 + 19830, AMDGPU::FeatureVOP3PInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 962 | { sizeof(SubtargetFeatureKV) * 16 + 19860, sizeof(SubtargetFeatureKV) * 16 + 19893, AMDGPU::FeatureVOP3PX2IncrementsVaVdstTwice, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 963 | { sizeof(SubtargetFeatureKV) * 15 + 19957, sizeof(SubtargetFeatureKV) * 15 + 19962, AMDGPU::FeatureVOPDInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 964 | { sizeof(SubtargetFeatureKV) * 14 + 20002, sizeof(SubtargetFeatureKV) * 14 + 20008, AMDGPU::FeatureVscnt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 965 | { sizeof(SubtargetFeatureKV) * 13 + 20041, sizeof(SubtargetFeatureKV) * 13 + 20051, AMDGPU::FeatureWaitXcnt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 966 | { sizeof(SubtargetFeatureKV) * 12 + 20079, sizeof(SubtargetFeatureKV) * 12 + 20112, AMDGPU::FeatureWaitsBeforeSystemScopeStores, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 967 | { sizeof(SubtargetFeatureKV) * 11 + 20183, sizeof(SubtargetFeatureKV) * 11 + 20199, AMDGPU::FeatureWavefrontSize16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 968 | { sizeof(SubtargetFeatureKV) * 10 + 20235, sizeof(SubtargetFeatureKV) * 10 + 20199, AMDGPU::FeatureWavefrontSize32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 969 | { sizeof(SubtargetFeatureKV) * 9 + 20251, sizeof(SubtargetFeatureKV) * 9 + 20199, AMDGPU::FeatureWavefrontSize64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 970 | { sizeof(SubtargetFeatureKV) * 8 + 20267, sizeof(SubtargetFeatureKV) * 8 + 20283, AMDGPU::FeatureWMMA128bInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 971 | { sizeof(SubtargetFeatureKV) * 7 + 20356, sizeof(SubtargetFeatureKV) * 7 + 20372, AMDGPU::FeatureWMMA256bInsts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 972 | { sizeof(SubtargetFeatureKV) * 6 + 20438, sizeof(SubtargetFeatureKV) * 6 + 20463, AMDGPU::FeatureWMMACoexecutionHazards, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 973 | { sizeof(SubtargetFeatureKV) * 5 + 20526, sizeof(SubtargetFeatureKV) * 5 + 20541, AMDGPU::FeatureWMMAN16Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 974 | { sizeof(SubtargetFeatureKV) * 4 + 20575, sizeof(SubtargetFeatureKV) * 4 + 20586, AMDGPU::FeatureXF32Insts, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 975 | { sizeof(SubtargetFeatureKV) * 3 + 20689, sizeof(SubtargetFeatureKV) * 3 + 20695, AMDGPU::FeatureXNACK, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x400000ULL, 0x0ULL, 0x0ULL, } } } }, |
| 976 | { sizeof(SubtargetFeatureKV) * 2 + 20716, sizeof(SubtargetFeatureKV) * 2 + 20735, AMDGPU::FeatureXNACKOnOffModes, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x400000ULL, 0x0ULL, 0x0ULL, } } } }, |
| 977 | { sizeof(SubtargetFeatureKV) * 1 + 20770, sizeof(SubtargetFeatureKV) * 1 + 20784, AMDGPU::FeatureSupportsXNACK, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } }, |
| 978 | }, |
| 979 | "\000" "1024-addressable-vgprs\000Has 1024 addressable VGPRs\000" "1536-" |
| 980 | "physical-vgprs\000Has 1536 physical VGPRs per SIMD\000" "16-bit-insts\000" |
| 981 | "Has i16/f16 instructions\000" "32-bit-num-records-buffer-resource\000Th" |
| 982 | "e buffer resource (V#) has 32-bit num_records\000" "45-bit-num-records-" |
| 983 | "buffer-resource\000The buffer resource (V#) has 45-bit num_records\000" "" |
| 984 | "64-bit-literals\000Can use 64-bit literals with single DWORD instructio" |
| 985 | "ns\000a16\000Support A16 for 16-bit coordinates/gradients/lod/clamp/mip" |
| 986 | " image operands\000add-min-max-insts\000Has v_add_{min|max}_{i|u}32 ins" |
| 987 | "tructions\000add-no-carry-insts\000Have VALU add/sub instructions witho" |
| 988 | "ut carry out\000add-sub-u64-insts\000Has v_add_u64 and v_sub_u64 instru" |
| 989 | "ctions\000addressablelocalmemorysize163840\000The size of local memory " |
| 990 | "in bytes\000addressablelocalmemorysize196608\000addressablelocalmemorys" |
| 991 | "ize32768\000addressablelocalmemorysize327680\000addressablelocalmemorys" |
| 992 | "ize65536\000agent-scope-fine-grained-remote-memory-atomics\000Agent (de" |
| 993 | "vice) scoped atomic operations, excluding those directly supported by P" |
| 994 | "CIe (i.e. integer atomic add, exchange, and compare-and-swap), are func" |
| 995 | "tional for allocations in host or peer device memory.\000aperture-regs\000" |
| 996 | "Has Memory Aperture Base and Size Registers\000architected-flat-scratch" |
| 997 | "\000Flat Scratch register is a readonly SPI initialized architected reg" |
| 998 | "ister\000architected-sgprs\000Enable the architected SGPRs\000ashr-pk-i" |
| 999 | "nsts\000Has Arithmetic Shift Pack instructions\000assembler-permissive-" |
| 1000 | "wavesize\000Allow parsing wave32 and wave64 variants of instructions\000" |
| 1001 | "async-load-to-lds-insts\000Has global async load to LDS instructions\000" |
| 1002 | "async-store-from-lds-insts\000Has global async store from LDS instructi" |
| 1003 | "ons\000asynccnt\000Has separate asynccnt counter\000atomic-buffer-globa" |
| 1004 | "l-pk-add-f16-insts\000Has buffer_atomic_pk_add_f16 and global_atomic_pk" |
| 1005 | "_add_f16 instructions that can return original value\000atomic-buffer-g" |
| 1006 | "lobal-pk-add-f16-no-rtn-insts\000Has buffer_atomic_pk_add_f16 and globa" |
| 1007 | "l_atomic_pk_add_f16 instructions that don't return original value\000at" |
| 1008 | "omic-buffer-pk-add-bf16-inst\000Has buffer_atomic_pk_add_bf16 instructi" |
| 1009 | "on\000atomic-csub-no-rtn-insts\000Has buffer_atomic_csub and global_ato" |
| 1010 | "mic_csub instructions that don't return original value\000atomic-ds-pk-" |
| 1011 | "add-16-insts\000Has ds_pk_add_bf16, ds_pk_add_f16, ds_pk_add_rtn_bf16, " |
| 1012 | "ds_pk_add_rtn_f16 instructions\000atomic-fadd-no-rtn-insts\000Has buffe" |
| 1013 | "r_atomic_add_f32 and global_atomic_add_f32 instructions that don't retu" |
| 1014 | "rn original value\000atomic-fadd-rtn-insts\000Has buffer_atomic_add_f32" |
| 1015 | " and global_atomic_add_f32 instructions that return original value\000a" |
| 1016 | "tomic-flat-pk-add-16-insts\000Has flat_atomic_pk_add_f16 and flat_atomi" |
| 1017 | "c_pk_add_bf16 instructions\000atomic-fmin-fmax-flat-f32\000Has flat mem" |
| 1018 | "ory instructions for atomicrmw fmin/fmax for float\000atomic-fmin-fmax-" |
| 1019 | "flat-f64\000Has flat memory instructions for atomicrmw fmin/fmax for do" |
| 1020 | "uble\000atomic-fmin-fmax-global-f32\000Has global/buffer instructions f" |
| 1021 | "or atomicrmw fmin/fmax for float\000atomic-fmin-fmax-global-f64\000atom" |
| 1022 | "ic-global-pk-add-bf16-inst\000Has global_atomic_pk_add_bf16 instruction" |
| 1023 | "\000auto-waitcnt-before-barrier\000Hardware automatically inserts waitc" |
| 1024 | "nt before barrier\000back-off-barrier\000Hardware supports backing off " |
| 1025 | "s_barrier if an exception occurs\000bf16-cvt-insts\000Has bf16 conversi" |
| 1026 | "on instructions\000bf16-from-upper-fp32\000bf16 inline constants are ac" |
| 1027 | "tually selected from upper 16-bits of a fp32\000bf16-pk-insts\000Has bf" |
| 1028 | "16 packed instructions (fma, add, mul, max, min)\000bf16-trans-insts\000" |
| 1029 | "Has bf16 transcendental instructions\000bf8-cvt-scale-insts\000Has bf8 " |
| 1030 | "conversion scale instructions\000bitop3-insts\000Has v_bitop3_b32/v_bit" |
| 1031 | "op3_b16 instructions\000block-vgpr-csr\000Use block load/store for VGPR" |
| 1032 | " callee saved registers\000bvh-dual-bvh-8-insts\000Has image_bvh_dual_i" |
| 1033 | "ntersect_ray and image_bvh8_intersect_ray instructions\000bvh-ray-traci" |
| 1034 | "ng-insts\000Has BVH ray tracing instructions\000ci-insts\000Additional " |
| 1035 | "instructions for CI+\000clusters\000Has clusters of workgroups support\000" |
| 1036 | "cube-insts\000Has v_cube* instructions\000cumode\000Enable CU wavefront" |
| 1037 | " execution mode\000cvt-fp8-byte-sel\000FP8/BF8 conversions take the byt" |
| 1038 | "e index from a byte_sel operand\000cvt-fp8-sdwa-src-sel\000FP8/BF8 conv" |
| 1039 | "ersions take the byte index from the SDWA src0_sel or op_sel field\000c" |
| 1040 | "vt-fp8-vop1-bug\000FP8/BF8 VOP1 form of conversion to F32 is unreliable" |
| 1041 | "\000cvt-norm-insts\000Has v_cvt_norm* instructions\000cvt-pk-f16-f32-in" |
| 1042 | "st\000Has cvt_pk_f16_f32 instruction\000cvt-pknorm-vop2-insts\000Has v_" |
| 1043 | "cvt_pk_norm_*f32 instructions/Has v_cvt_pk_norm_*_f16 instructions\000c" |
| 1044 | "vt-pknorm-vop3-insts\000cvt-sr-pk-bf16-f32-inst\000Has cvt_sr_pk_bf16_f" |
| 1045 | "32 instruction\000d16-write-vgpr32\000D16 instructions potentially have" |
| 1046 | " 32-bit data dependencies\000datacachelinesize128\000Data (VMEM) cache " |
| 1047 | "line size in bytes.\000default-component-broadcast\000BUFFER/IMAGE stor" |
| 1048 | "e instructions set unspecified components to x component (GFX12)\000def" |
| 1049 | "ault-component-zero\000BUFFER/IMAGE store instructions set unspecified " |
| 1050 | "components to zero (before GFX12)\000dl-insts\000Has v_fmac_f32 and v_x" |
| 1051 | "nor_b32 instructions\000dot1-insts\000Has v_dot4_i32_i8 and v_dot8_i32_" |
| 1052 | "i4 instructions\000dot10-insts\000Has v_dot2_f32_f16 instruction\000dot" |
| 1053 | "11-insts\000Has v_dot4_f32_fp8_fp8, v_dot4_f32_fp8_bf8, v_dot4_f32_bf8_" |
| 1054 | "fp8, v_dot4_f32_bf8_bf8 instructions\000dot12-insts\000Has v_dot2_f32_b" |
| 1055 | "f16 instructions\000dot13-insts\000Has v_dot2c_f32_bf16 instructions\000" |
| 1056 | "dot2-insts\000Has v_dot2_i32_i16, v_dot2_u32_u16 instructions\000dot3-i" |
| 1057 | "nsts\000Has v_dot8c_i32_i4 instruction\000dot4-insts\000Has v_dot2c_i32" |
| 1058 | "_i16 instruction\000dot5-insts\000Has v_dot2c_f32_f16 instruction\000do" |
| 1059 | "t6-insts\000Has v_dot4c_i32_i8 instruction\000dot7-insts\000Has v_dot4_" |
| 1060 | "u32_u8, v_dot8_u32_u4 instructions\000dot8-insts\000Has v_dot4_i32_iu8," |
| 1061 | " v_dot8_i32_iu4 instructions\000dot9-insts\000Has v_dot2_f16_f16, v_dot" |
| 1062 | "2_bf16_bf16 instructions\000dpp\000Support DPP (Data Parallel Primitive" |
| 1063 | "s) extension\000dpp-64bit\000Support DPP (Data Parallel Primitives) ext" |
| 1064 | "ension in DP ALU\000dpp-row-bcast\000Support DPP row_bcast15/row_bcast3" |
| 1065 | "1\000dpp-src1-sgpr\000Support SGPR for Src1 of DPP instructions\000dpp-" |
| 1066 | "wavefront-shifts\000Support DPP wave_shl/wave_rol/wave_shr/wave_ror\000" |
| 1067 | "dpp8\000Support DPP8 (Data Parallel Primitives) extension\000ds-src2-in" |
| 1068 | "sts\000Has ds_*_src2 instructions\000dumpcode\000Dump MachineInstrs in " |
| 1069 | "the CodeEmitter\000dx10-clamp-and-ieee-mode\000Target has DX10_CLAMP an" |
| 1070 | "d IEEE_MODE kernel descriptor bits\000emulated-system-scope-atomics\000" |
| 1071 | "System scope atomics unsupported by the PCI-e are emulated in HW via CA" |
| 1072 | "S loop and functional.\000enable-ds128\000Use ds_{read|write}_b128\000e" |
| 1073 | "nable-flat-scratch\000Use scratch_* flat memory instructions to access " |
| 1074 | "scratch\000enable-prt-strict-null\000Enable zeroing of result registers" |
| 1075 | " for sparse texture fetches\000extended-image-insts\000Support mips != " |
| 1076 | "0, lod != 0, gather4, and get_lod\000f16-fp8-conversion-insts\000Has f1" |
| 1077 | "6 conversion to fp8 and bf8 instructions\000f16bf16-to-fp6bf6-cvt-scale" |
| 1078 | "-insts\000Has f16bf16 to fp6bf6 conversion scale instructions\000f32-to" |
| 1079 | "-f16bf16-cvt-sr-insts\000Has f32 to f16bf16 conversion scale instructio" |
| 1080 | "ns\000f32-to-fp6bf6-cvt-scale-insts\000Has f32 to fp6bf6 conversion sca" |
| 1081 | "le instructions\000fast-denormal-f32\000Enabling denormals does not cau" |
| 1082 | "se f32 instructions to run at f64 rates\000fast-fmaf\000Assuming f32 fm" |
| 1083 | "a is at least as fast as mul + add\000flat-address-space\000Support fla" |
| 1084 | "t address space\000flat-atomic-fadd-f32-inst\000Has flat_atomic_add_f32" |
| 1085 | " instruction\000flat-buffer-global-fadd-f64-inst\000Has flat, buffer, a" |
| 1086 | "nd global instructions for f64 atomic fadd\000flat-for-global\000Force " |
| 1087 | "to generate flat instruction for global\000flat-global-insts\000Have gl" |
| 1088 | "obal_* flat memory instructions\000flat-gvs-mode\000Have GVS addressing" |
| 1089 | " mode with flat_* instructions\000flat-inst-offsets\000Flat instruction" |
| 1090 | "s have immediate offset addressing mode\000flat-offset-bits-12\000Numbe" |
| 1091 | "r of bits for flat offset encoding\000flat-offset-bits-24\000flat-scrat" |
| 1092 | "ch-insts\000Have scratch_* flat memory instructions\000flat-segment-off" |
| 1093 | "set-bug\000GFX10 bug where inst_offset is ignored when flat instruction" |
| 1094 | "s access global memory\000flat-signed-offset\000Immediate offset of FLA" |
| 1095 | "T instructions are always signed\000fma-legacy32-insts\000Has single-pr" |
| 1096 | "ecision legacy FMA instructions\000fma-mix-bf16-insts\000Has v_fma_mix_" |
| 1097 | "f32_bf16, v_fma_mixlo_bf16, v_fma_mixhi_bf16 instructions\000fma-mix-in" |
| 1098 | "sts\000Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions" |
| 1099 | "\000fmacf64-inst\000Has v_fmac_f64 instruction\000fmaf\000Enable single" |
| 1100 | " precision FMA (not as fast as mul+add, but fused)\000formatted-mubuf-i" |
| 1101 | "nsts\000Has formatted memory untyped buffer instructions.\000fp4-cvt-sc" |
| 1102 | "ale-insts\000Has fp4 conversion scale instructions\000fp64\000Enable do" |
| 1103 | "uble precision operations\000fp6bf6-cvt-scale-insts\000Has fp6 and bf6 " |
| 1104 | "conversion scale instructions\000fp8-conversion-insts\000Has fp8 and bf" |
| 1105 | "8 conversion instructions\000fp8-cvt-scale-insts\000Has fp8 conversion " |
| 1106 | "scale instructions\000fp8-f16-conversion-insts\000Has fp8 and bf8 conve" |
| 1107 | "rsion to f16 instructions\000fp8-insts\000Has fp8 and bf8 instructions\000" |
| 1108 | "fp8e5m3-insts\000Has fp8 e5m3 format support\000full-rate-64-ops\000Mos" |
| 1109 | "t fp64 instructions are full rate\000g16\000Support G16 for 16-bit grad" |
| 1110 | "ient image operands\000gcn3-encoding\000Encoding format for VI\000gds\000" |
| 1111 | "Has Global Data Share\000get-wave-id-inst\000Has s_get_waveid_in_workgr" |
| 1112 | "oup instruction\000gfx10\000GFX10 GPU generation\000gfx10-3-insts\000Ad" |
| 1113 | "ditional instructions for GFX10.3\000gfx10-insts\000Additional instruct" |
| 1114 | "ions for GFX10+\000gfx10_b-encoding\000Encoding format GFX10_B\000gfx11" |
| 1115 | "\000GFX11 GPU generation\000gfx11-7-insts\000Additional instructions fo" |
| 1116 | "r GFX11.7\000gfx11-insts\000Additional instructions for GFX11+\000gfx12" |
| 1117 | "\000GFX12 GPU generation\000gfx12-insts\000Additional instructions for " |
| 1118 | "GFX12+\000gfx1250-insts\000Additional instructions for GFX1250+\000gfx1" |
| 1119 | "250-strict\000gfx1250 strict mode\000gfx1251-gemm-insts\000Has addition" |
| 1120 | "al gfx1251 DGEMM instructions\000gfx125x-lowest-rate-wmma\000Has the lo" |
| 1121 | "west rate wmma in the gfx125x family, mainly for the gfx12-5-generic\000" |
| 1122 | "gfx13\000GFX13 GPU generation\000gfx13-insts\000Additional instructions" |
| 1123 | " for GFX13+\000gfx7-gfx8-gfx9-insts\000Instructions shared in GFX7, GFX" |
| 1124 | "8, GFX9\000gfx8-insts\000Additional instructions for GFX8+\000gfx9\000G" |
| 1125 | "FX9 GPU generation\000gfx9-insts\000Additional instructions for GFX9+\000" |
| 1126 | "gfx90a-insts\000Additional instructions for GFX90A+\000gfx940-insts\000" |
| 1127 | "Additional instructions for GFX940+\000gfx950-insts\000Additional instr" |
| 1128 | "uctions for GFX950+\000globally-addressable-scratch\000FLAT instruction" |
| 1129 | "s can access scratch memory for any thread in any wave\000gws\000Has Gl" |
| 1130 | "obal Wave Sync\000half-addressable-physical-local-memory\000A work-grou" |
| 1131 | "p can address only half of the physical LDS block\000half-rate-64-ops\000" |
| 1132 | "Most fp64 instructions are half rate instead of quarter\000ieee-minimum" |
| 1133 | "-maximum-insts\000Has v_minimum/maximum_f16/f32/f64, v_minimummaximum/m" |
| 1134 | "aximumminimum_f16/f32 andv_pk_minimum/maximum_f16 instructions\000image" |
| 1135 | "-gather4-d16-bug\000Image Gather4 D16 hardware bug\000image-insts\000Su" |
| 1136 | "pport image instructions\000image-store-d16-bug\000Image Store D16 hard" |
| 1137 | "ware bug\000inst-fwd-prefetch-bug\000S_INST_PREFETCH instruction causes" |
| 1138 | " shader to hang\000instcachelinesize128\000Instruction cache line size " |
| 1139 | "in bytes.\000instcachelinesize64\000int-clamp-insts\000Support clamp fo" |
| 1140 | "r integer destination\000inv-2pi-inline-imm\000Has 1 / (2 * pi) as inli" |
| 1141 | "ne immediate\000kernarg-preload\000Hardware supports preloading of kern" |
| 1142 | "el arguments in user SGPRs.\000lds-atomic-add-f64\000Has ds_add_f64 and" |
| 1143 | " ds_add_rtn_f64 instructions\000lds-barrier-arrive-atomic\000Has LDS ba" |
| 1144 | "rrier-arrive atomic instructions\000lds-branch-vmem-war-hazard\000Switc" |
| 1145 | "hing between LDS and VMEM-tex not waiting VM_VSRC=0\000lds-misaligned-b" |
| 1146 | "ug\000Some GFX10 bug with multi-dword LDS and flat access that is not n" |
| 1147 | "aturally aligned in WGP mode\000ldsbankcount16\000The number of LDS ban" |
| 1148 | "ks per compute unit.\000ldsbankcount32\000lerp-inst\000Has v_lerp_u8 in" |
| 1149 | "struction\000load-store-opt\000Enable SI load/store optimizer pass\000l" |
| 1150 | "shl-add-u64-inst\000Has v_lshl_add_u64 instruction\000mad-intra-fwd-bug" |
| 1151 | "\000MAD_U64/I64 intra instruction forwarding bug\000mad-mac-f32-insts\000" |
| 1152 | "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions\000mad-mix" |
| 1153 | "-insts\000Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructi" |
| 1154 | "ons\000mad-nc-64-32-insts\000Has v_mad_nc_{u64_u32|i64_i32} instruction" |
| 1155 | "s\000mad-u32-inst\000Has v_mad_u32 instruction\000mai-insts\000Has mAI " |
| 1156 | "instructions\000max-hard-clause-length-32\000Maximum number of instruct" |
| 1157 | "ions in an explicit S_CLAUSE is 32\000max-hard-clause-length-63\000Maxi" |
| 1158 | "mum number of instructions in an explicit S_CLAUSE is 63\000max-private" |
| 1159 | "-element-size-16\000Maximum private access size may be 16\000max-privat" |
| 1160 | "e-element-size-4\000Maximum private access size may be 4\000max-private" |
| 1161 | "-element-size-8\000Maximum private access size may be 8\000max-waves-pe" |
| 1162 | "r-eu-10\000Maximum number of waves an execution unit can hold.\000max-w" |
| 1163 | "aves-per-eu-16\000max-waves-per-eu-20\000max-waves-per-eu-8\000mcast-lo" |
| 1164 | "ad-insts\000Has multicast load instructions\000memory-atomic-fadd-f32-d" |
| 1165 | "enormal-support\000global/flat/buffer atomic fadd for float supports de" |
| 1166 | "normal handling\000mfma-inline-literal-bug\000MFMA cannot use inline li" |
| 1167 | "teral as SrcC\000mimg-r128\000Support 128-bit texture resources\000min-" |
| 1168 | "max-i64-insts\000Has v_{min|max}_{i|u}64 instructions\000min3-max3-pkf1" |
| 1169 | "6\000Has v_pk_min3_num_f16 and v_pk_max3_num_f16 instructions\000minimu" |
| 1170 | "m3-maximum3-f16\000Has v_minimum3_f16 and v_maximum3_f16 instructions\000" |
| 1171 | "minimum3-maximum3-f32\000Has v_minimum3_f32 and v_maximum3_f32 instruct" |
| 1172 | "ions\000minimum3-maximum3-pkf16\000Has v_pk_minimum3_f16 and v_pk_maxim" |
| 1173 | "um3_f16 instructions\000movrel\000Has v_movrel*_b32 instructions\000mqs" |
| 1174 | "ad-insts\000Has v_mqsad_u32_u8 instruction\000mqsad-pk-insts\000Has v_m" |
| 1175 | "qsad_pk_u16_u8 instruction\000msaa-load-dst-sel-bug\000MSAA loads not h" |
| 1176 | "onoring dst_sel bug\000msaa-load-insts\000Has image_msaa_load instructi" |
| 1177 | "ons\000msad-insts\000Has v_msad_u8 instruction\000mtbuf-insts\000Has me" |
| 1178 | "mory typed buffer instructions.\000needs-aligned-2addr-lds\000Needs 2ad" |
| 1179 | "dr LDS instructions to be aligned to payload size\000needs-tdm-drain\000" |
| 1180 | "Needs to keep tensor count low\000negative-scratch-offset-bug\000Negati" |
| 1181 | "ve immediate offsets in scratch instructions with an SGPR offset page f" |
| 1182 | "ault on GFX9\000negative-unaligned-scratch-offset-bug\000Scratch instru" |
| 1183 | "ctions with a VGPR offset and a negative immediate offset thatis not a " |
| 1184 | "multiple of 4 read wrong memory on GFX10\000no-data-dep-hazard\000Does " |
| 1185 | "not need SW waitstates\000no-f16-pseudo-scalar-trans-inline-constants\000" |
| 1186 | "Inline constants are not supported for F16 pseudo scalar transcendental" |
| 1187 | "s\000no-sdst-cmpx\000V_CMPX does not write VCC/SGPR in addition to EXEC" |
| 1188 | "\000nsa-clause-bug\000MIMG-NSA in a hard clause has unpredictable resul" |
| 1189 | "ts on GFX10.1\000nsa-encoding\000Support NSA encoding for image instruc" |
| 1190 | "tions\000nsa-to-vmem-bug\000MIMG-NSA followed by VMEM fail if EXEC_LO o" |
| 1191 | "r EXEC_HI equals zero\000ocp-fp8-conversion-insts\000Has OCP fp8 (E4M3F" |
| 1192 | "N, E5M2) conversion instructions\000offset-3f-bug\000Branch offset of 3" |
| 1193 | "f hardware bug\000packed-fp32-ops\000Support packed fp32 instructions\000" |
| 1194 | "packed-fp32-single-sgpr-ops\000Support packed fp32 instructions with SG" |
| 1195 | "PR operands propagating low to high 32 bit\000packed-fp64-single-sgpr-o" |
| 1196 | "ps\000Support packed fp64 instructions with SGPR operands propagating l" |
| 1197 | "ow to high 64 bit\000packed-tid\000Workitem IDs are packed into v0 at k" |
| 1198 | "ernel launch\000packed-u64-single-sgpr-ops\000Support packed uint64 ins" |
| 1199 | "tructions with SGPR operands propagating low to high 64 bit\000partial-" |
| 1200 | "nsa-encoding\000Support partial NSA encoding for image instructions\000" |
| 1201 | "permlane16-insts\000Has v_permlane16_b32/v_permlanex16_b32 instructions" |
| 1202 | "\000permlane16-swap\000Has v_permlane16_swap_b32 instructions\000permla" |
| 1203 | "ne32-swap\000Has v_permlane32_swap_b32 instructions\000pk-add-min-max-i" |
| 1204 | "nsts\000Has v_pk_add_{min|max}_{i|u}16 instructions\000pk-fmac-f16-inst" |
| 1205 | "\000Has v_pk_fmac_f16 instruction\000point-sample-accel\000Has point sa" |
| 1206 | "mple acceleration feature\000pops-exiting-wave-id\000Has POPS_EXITING_W" |
| 1207 | "AVE_ID hardware register\000precise-memory\000Enable precise memory mod" |
| 1208 | "e\000priv-enabled-trap2-nop-bug\000Hardware that runs with PRIV=1 inter" |
| 1209 | "preting 's_trap 2' as a nop bug\000prng-inst\000Has v_prng_b32 instruct" |
| 1210 | "ion\000pseudo-scalar-trans\000Has Pseudo Scalar Transcendental instruct" |
| 1211 | "ions\000qsad-insts\000Has v_qsad* instructions\000r128-a16\000Support g" |
| 1212 | "fx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image oper" |
| 1213 | "ands, where a16 is aliased with r128\000real-true16\000Use true 16-bit " |
| 1214 | "registers\000required-export-priority\000Export priority must be explic" |
| 1215 | "itly manipulated on GFX11.5\000requires-cov6\000Target Requires Code Ob" |
| 1216 | "ject V6\000requires-initial-unclause-vmem\000Hardware entrypoints requi" |
| 1217 | "re first VMEM instruction to be unclaused\000restricted-soffset\000Has " |
| 1218 | "restricted SOffset (immediate not supported).\000s-barrier-leave-imm\000" |
| 1219 | "s_barrier_leave takes an immediate operand\000s-memrealtime\000Has s_me" |
| 1220 | "mrealtime instruction\000s-memtime-inst\000Has s_memtime instruction\000" |
| 1221 | "s-wakeup-barrier-inst\000Has s_wakeup_barrier instruction.\000s-wakeup-" |
| 1222 | "imm\000s_wakeup takes an immediate operand\000sad-insts\000Has v_sad* i" |
| 1223 | "nstructions\000safe-cu-prefetch\000VMEM CU scope prefetches do not fail" |
| 1224 | " on illegal address\000safe-smem-prefetch\000SMEM prefetches do not fai" |
| 1225 | "l on illegal address\000salu-float\000Has SALU floating point instructi" |
| 1226 | "ons\000salu-minimum-maximum-insts\000Has s_minimum/maximum_f16/f32 inst" |
| 1227 | "ructions\000scalar-atomics\000Has atomic scalar memory instructions\000" |
| 1228 | "scalar-dwordx3-loads\000Has 96-bit scalar load instructions\000scalar-f" |
| 1229 | "lat-scratch-insts\000Have s_scratch_* flat memory instructions\000scala" |
| 1230 | "r-stores\000Has store scalar memory instructions\000sdwa\000Support SDW" |
| 1231 | "A (Sub-DWORD Addressing) extension\000sdwa-mav\000Support v_mac_f32/f16" |
| 1232 | " with SDWA (Sub-DWORD Addressing) extension\000sdwa-omod\000Support OMo" |
| 1233 | "d with SDWA (Sub-DWORD Addressing) extension\000sdwa-out-mods-vopc\000S" |
| 1234 | "upport clamp for VOPC with SDWA (Sub-DWORD Addressing) extension\000sdw" |
| 1235 | "a-scalar\000Support scalar register with SDWA (Sub-DWORD Addressing) ex" |
| 1236 | "tension\000sdwa-sdst\000Support scalar dst for VOPC with SDWA (Sub-DWOR" |
| 1237 | "D Addressing) extension\000sea-islands\000SEA_ISLANDS GPU generation\000" |
| 1238 | "setprio-inc-wg-inst\000Has s_setprio_inc_wg instruction.\000setreg-vgpr" |
| 1239 | "-msb-fixup\000S_SETREG to MODE clobbers VGPR MSB bits, requires fixup\000" |
| 1240 | "sgpr-init-bug\000VI SGPR initialization bug requiring a fixed SGPR allo" |
| 1241 | "cation size\000shader-cycles-hi-lo-registers\000Has SHADER_CYCLES_HI/LO" |
| 1242 | " hardware registers\000shader-cycles-register\000Has SHADER_CYCLES hard" |
| 1243 | "ware register\000si-scheduler\000Enable SI Machine Scheduler\000smem-pr" |
| 1244 | "efetch-insts\000Has s_prefetch_inst, s_prefetch_inst_pc_rel, s_prefetch" |
| 1245 | "_data and s_prefetch_data_pc_rel instructions\000smem-to-vector-write-h" |
| 1246 | "azard\000s_load_dword followed by v_cmp page faults\000southern-islands" |
| 1247 | "\000SOUTHERN_ISLANDS GPU generation\000sramecc\000Enable SRAMECC\000sra" |
| 1248 | "mecc-support\000Hardware supports SRAMECC\000supports-wave32\000Hardwar" |
| 1249 | "e supports wave32 mode\000supports-wave64\000Hardware supports wave64 m" |
| 1250 | "ode\000supports-wgp\000Hardware supports WGP mode\000swmmac-gfx1200-ins" |
| 1251 | "ts\000Has GFX1200 SWMMAC instructions\000swmmac-gfx1250-insts\000Has GF" |
| 1252 | "X1250 SWMMAC instructions\000tanh-insts\000Has v_tanh_f32/f16 instructi" |
| 1253 | "ons\000tensor-cvt-lut-insts\000Has v_perm_pk16* instructions\000tgsplit" |
| 1254 | "-support\000Hardware support for threadgroup split execution mode\000tr" |
| 1255 | "ans-coexecution-hazard\000Hazard when TRANS co-executes with other VALU" |
| 1256 | " instruction\000transpose-load-f4f6-insts\000Has ds_load_tr4/tr6 and gl" |
| 1257 | "obal_load_tr4/tr6 instructions\000trap-handler\000Trap handler support\000" |
| 1258 | "trig-reduced-range\000Requires use of fract on arguments to trig instru" |
| 1259 | "ctions\000true16\000True 16-bit operand instructions\000unaligned-acces" |
| 1260 | "s-mode\000Enable unaligned global, local and region loads and stores if" |
| 1261 | " the hardware supports it\000unaligned-buffer-access\000Hardware suppor" |
| 1262 | "ts unaligned global loads and stores\000unaligned-ds-access\000Hardware" |
| 1263 | " supports unaligned local and region loads and stores\000unaligned-scra" |
| 1264 | "tch-access\000Support unaligned scratch loads and stores\000unpacked-d1" |
| 1265 | "6-vmem\000Has unpacked d16 vmem instructions\000unsafe-ds-offset-foldin" |
| 1266 | "g\000Force using DS instruction immediate offsets on SI\000use-add-pc64" |
| 1267 | "-inst\000Use s_add_pc_i64 instruction.\000user-sgpr-init16-bug\000Bug r" |
| 1268 | "equiring at least 16 user+system SGPRs to be enabled\000v-mov-b64-inst\000" |
| 1269 | "Has v_mov_b64 instruction\000v-mul-u64-inst\000Has v_mul_u64 instructio" |
| 1270 | "n.\000valu-trans-use-hazard\000Hazard when TRANS instructions are close" |
| 1271 | "ly followed by a use of the result\000vcmpx-exec-war-hazard\000V_CMPX W" |
| 1272 | "AR hazard on EXEC (V_CMPX issue ONLY)\000vcmpx-permlane-hazard\000TODO:" |
| 1273 | " describe me\000vgpr-align2\000VGPR and AGPR tuple operands require eve" |
| 1274 | "n alignment\000vgpr-index-mode\000Has VGPR mode register indexing\000vm" |
| 1275 | "em-pref-insts\000Has flat_prefect_b8 and global_prefetch_b8 instruction" |
| 1276 | "s\000vmem-to-lds-load-insts\000The platform has memory to lds instructi" |
| 1277 | "ons (global_load w/lds bit set, buffer_loadw/lds bit set or global_load" |
| 1278 | "_lds. This does not include scratch_load_lds.\000vmem-to-scalar-write-h" |
| 1279 | "azard\000VMEM instruction followed by scalar writing to EXEC mask, M0 o" |
| 1280 | "r SGPR leads to incorrect execution.\000vmem-write-vgpr-in-order\000VME" |
| 1281 | "M instructions of the same type write VGPR results in order\000volcanic" |
| 1282 | "-islands\000VOLCANIC_ISLANDS GPU generation\000vop3-literal\000Can use " |
| 1283 | "one literal in VOP3\000vop3p\000Has VOP3P packed instructions\000vop3px" |
| 1284 | "2-increments-va-vdst-twice\000VOP3PX2 encoded instructions increment th" |
| 1285 | "e VaVdst counter twice\000vopd\000Has VOPD dual issue wave32 instructio" |
| 1286 | "ns\000vscnt\000Has separate store vscnt counter\000wait-xcnt\000Has s_w" |
| 1287 | "ait_xcnt instruction\000waits-before-system-scope-stores\000Target requ" |
| 1288 | "ires waits for loads and atomics before system scope stores\000wavefron" |
| 1289 | "tsize16\000The number of threads per wavefront\000wavefrontsize32\000wa" |
| 1290 | "vefrontsize64\000wmma-128b-insts\000Has WMMA instructions where A and B" |
| 1291 | " matrices do not have duplicated data\000wmma-256b-insts\000Has WMMA in" |
| 1292 | "structions where A and B matrices have duplicated data\000wmma-coexecut" |
| 1293 | "ion-hazards\000Hazards when WMMA co-executes with other WMMA/VALU instr" |
| 1294 | "uction\000wmma-n16-insts\000Has WMMA instructions with N = 16\000xf32-i" |
| 1295 | "nsts\000Has instructions that support xf32 format, such as v_mfma_f32_1" |
| 1296 | "6x16x8_xf32 and v_mfma_f32_32x32x4_xf32\000xnack\000Enable XNACK suppor" |
| 1297 | "t\000xnack-on-off-modes\000Target supports XNACK on/off modes\000xnack-" |
| 1298 | "support\000Hardware supports XNACK\000" }; |
| 1299 | |
| 1300 | #ifdef DBGFIELD |
| 1301 | #error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro" |
| 1302 | #endif |
| 1303 | #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) |
| 1304 | #define DBGFIELD(x) x, |
| 1305 | #define DBGVAL_OR_NULLPTR(x) x |
| 1306 | #else |
| 1307 | #define DBGFIELD(x) |
| 1308 | #define DBGVAL_OR_NULLPTR(x) nullptr |
| 1309 | #endif |
| 1310 | |
| 1311 | // =============================================================== |
| 1312 | // Data tables for the new per-operand machine model. |
| 1313 | |
| 1314 | static_assert(3 <= UINT8_MAX, "NumWriteProcResEntries does not fit in uint8_t" ); |
| 1315 | static_assert(3 <= UINT8_MAX, "NumWriteLatencyEntries does not fit in uint8_t" ); |
| 1316 | |
| 1317 | // {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle} |
| 1318 | extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[] = { |
| 1319 | { 0, 0, 0 }, // Invalid |
| 1320 | { 4, 1, 0}, // #1 |
| 1321 | { 5, 1, 0}, // #2 |
| 1322 | { 4, 1, 0}, // #3 |
| 1323 | { 7, 1, 0}, // #4 |
| 1324 | { 4, 2, 0}, // #5 |
| 1325 | { 7, 2, 0}, // #6 |
| 1326 | { 4, 1, 0}, // #7 |
| 1327 | { 8, 1, 0}, // #8 |
| 1328 | { 3, 1, 0}, // #9 |
| 1329 | { 4, 2, 0}, // #10 |
| 1330 | { 8, 1, 0}, // #11 |
| 1331 | { 3, 1, 0}, // #12 |
| 1332 | { 4, 1, 0}, // #13 |
| 1333 | { 3, 2, 0}, // #14 |
| 1334 | { 4, 2, 0}, // #15 |
| 1335 | { 2, 1, 0}, // #16 |
| 1336 | { 4, 1, 0}, // #17 |
| 1337 | { 1, 1, 0}, // #18 |
| 1338 | { 4, 2, 0}, // #19 |
| 1339 | { 5, 1, 0}, // #20 |
| 1340 | { 7, 1, 0}, // #21 |
| 1341 | { 4, 1, 0}, // #22 |
| 1342 | { 6, 1, 0}, // #23 |
| 1343 | { 4, 1, 0}, // #24 |
| 1344 | { 5, 1, 0}, // #25 |
| 1345 | { 7, 1, 0}, // #26 |
| 1346 | { 4, 1, 0}, // #27 |
| 1347 | { 7, 2, 0}, // #28 |
| 1348 | { 4, 1, 0}, // #29 |
| 1349 | { 6, 1, 0}, // #30 |
| 1350 | { 7, 1, 0}, // #31 |
| 1351 | { 4, 3, 0}, // #32 |
| 1352 | { 8, 3, 0}, // #33 |
| 1353 | { 9, 16, 0}, // #34 |
| 1354 | { 9, 32, 0}, // #35 |
| 1355 | { 4, 2, 0}, // #36 |
| 1356 | { 6, 2, 0}, // #37 |
| 1357 | { 3, 1, 0}, // #38 |
| 1358 | { 4, 2, 0}, // #39 |
| 1359 | { 7, 1, 0}, // #40 |
| 1360 | { 4, 2, 0}, // #41 |
| 1361 | { 5, 1, 0}, // #42 |
| 1362 | { 6, 1, 0}, // #43 |
| 1363 | { 4, 1, 0}, // #44 |
| 1364 | { 5, 1, 0}, // #45 |
| 1365 | { 6, 1, 0}, // #46 |
| 1366 | { 4, 1, 0}, // #47 |
| 1367 | { 6, 2, 0}, // #48 |
| 1368 | { 4, 3, 0}, // #49 |
| 1369 | { 7, 3, 0}, // #50 |
| 1370 | { 9, 4, 0}, // #51 |
| 1371 | { 9, 8, 0}, // #52 |
| 1372 | { 5, 2, 0}, // #53 |
| 1373 | { 3, 1, 0}, // #54 |
| 1374 | { 6, 1, 0}, // #55 |
| 1375 | { 6, 3, 0}, // #56 |
| 1376 | { 7, 8, 0}, // #57 |
| 1377 | { 7, 16, 0}, // #58 |
| 1378 | { 5, 4, 0}, // #59 |
| 1379 | { 5, 8, 0}, // #60 |
| 1380 | { 7, 4, 0}, // #61 |
| 1381 | { 5, 16, 0} // #62 |
| 1382 | }; // AMDGPUWriteProcResTable |
| 1383 | |
| 1384 | // {Cycles, WriteResourceID} |
| 1385 | extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[] = { |
| 1386 | { 0, 0}, // Invalid |
| 1387 | { 2, 0}, // #1 WriteSALU_WriteDoubleAdd_Write64Bit_Write2PassMAI |
| 1388 | { 5, 0}, // #2 Write32Bit_WriteFloatCvt_WriteFloatFMA_Write64Bit_WriteDoubleAdd_WriteLDS_WriteSMEM |
| 1389 | { 5, 0}, // #3 Write32Bit_WriteVALUDummy_Write64Bit_WriteLDS |
| 1390 | { 5, 0}, // #4 Write32Bit |
| 1391 | {320, 0}, // #5 WriteVMEM |
| 1392 | {320, 0}, // #6 WriteVMEM |
| 1393 | {20, 0}, // #7 WriteLDS_WriteSMEM |
| 1394 | {20, 0}, // #8 WriteLDS |
| 1395 | {20, 0}, // #9 WriteLDS |
| 1396 | {16, 0}, // #10 WriteExport_Write4PassWMMA_WriteXDL4PassWMMA_WriteFloatFMA_WriteDouble_WriteTrans64_Write16PassMAI_Write16PassDGEMM |
| 1397 | {32, 0}, // #11 WriteBranch_WriteXDL8PassWMMA |
| 1398 | {2000, 0}, // #12 WriteBarrier |
| 1399 | { 2, 0}, // #13 WriteSALU |
| 1400 | { 6, 0}, // #14 Write64Bit_WriteQuarterRate32_WriteDoubleCvt |
| 1401 | { 5, 0}, // #15 Write32Bit_WriteFloatFMA |
| 1402 | { 2, 0}, // #16 WriteSALU_WriteSALUDummy |
| 1403 | {22, 0}, // #17 WriteDoubleAdd_WriteDoubleCvt |
| 1404 | {10, 0}, // #18 WriteTrans32 |
| 1405 | {22, 0}, // #19 WriteDouble |
| 1406 | { 2, 0}, // #20 WriteSALUDummy |
| 1407 | { 8, 0}, // #21 WriteIntMul_WriteQuarterRate32_WriteTrans32_WritePseudoScalarTrans_WriteXDL2PassWMMA_WriteBranch_WriteDoubleAdd_Write8PassMAI_Write8PassDGEMM |
| 1408 | { 2, 0}, // #22 WriteSALUDummy |
| 1409 | {24, 0}, // #23 WriteTrans64 |
| 1410 | { 6, 0}, // #24 Write64Bit |
| 1411 | { 6, 0}, // #25 Write64Bit |
| 1412 | {320, 0}, // #26 WriteVMEM |
| 1413 | {320, 0}, // #27 WriteVMEM |
| 1414 | {320, 0}, // #28 WriteVMEM |
| 1415 | {22, 0}, // #29 WriteDoubleAdd |
| 1416 | { 5, 0}, // #30 Write32Bit |
| 1417 | { 4, 0}, // #31 WriteSFPU_WriteXDL1PassWMMA_WriteExport_WriteTrans32_WriteFloatCvt_WriteDoubleCvt_WriteIntMul_WriteQuarterRate32_WriteTrans64_Write4PassDGEMM_Write4PassMAI |
| 1418 | {38, 0}, // #32 WriteDoubleAdd_WriteDoubleCvt_WriteTrans64 |
| 1419 | {38, 0}, // #33 WriteDouble |
| 1420 | { 2, 0}, // #34 WriteSALUDummy |
| 1421 | {40, 0}, // #35 WriteTrans64 |
| 1422 | {38, 0}, // #36 WriteDoubleAdd |
| 1423 | { 5, 0}, // #37 Write32Bit |
| 1424 | {37, 0}, // #38 WriteDoubleAdd_WriteDoubleCvt |
| 1425 | {37, 0}, // #39 WriteDouble |
| 1426 | { 2, 0}, // #40 WriteSALUDummy |
| 1427 | {37, 0}, // #41 WriteDoubleAdd |
| 1428 | { 5, 0}, // #42 Write32Bit |
| 1429 | { 9, 0}, // #43 WriteTrans32 |
| 1430 | { 6, 0}, // #44 WriteDouble |
| 1431 | { 2, 0}, // #45 WriteSALUDummy |
| 1432 | { 7, 0}, // #46 WriteTrans64 |
| 1433 | { 1, 0}, // #47 WriteSALU_Write32Bit_WriteFloatFMA_WriteDoubleAdd_Write64Bit_WriteDoubleCvt_WriteIntMul |
| 1434 | { 1, 0}, // #48 Write32Bit_WriteSALU_WriteSALUDummy_WriteVALUDummy_Write64Bit |
| 1435 | { 1, 0}, // #49 Write32Bit |
| 1436 | {80, 0}, // #50 WriteVMEM |
| 1437 | {80, 0}, // #51 WriteVMEM |
| 1438 | { 5, 0}, // #52 WriteLDS |
| 1439 | {500, 0}, // #53 WriteBarrier |
| 1440 | { 1, 0}, // #54 WriteSALU |
| 1441 | { 2, 0}, // #55 Write64Bit |
| 1442 | { 4, 0}, // #56 WriteDouble_WriteIntMul |
| 1443 | { 1, 0}, // #57 WriteSALUDummy |
| 1444 | { 2, 0}, // #58 Write64Bit |
| 1445 | { 2, 0}, // #59 Write64Bit |
| 1446 | {80, 0}, // #60 WriteVMEM |
| 1447 | {80, 0}, // #61 WriteVMEM |
| 1448 | {80, 0}, // #62 WriteVMEM |
| 1449 | { 2, 0}, // #63 WriteDoubleAdd |
| 1450 | { 1, 0}, // #64 Write32Bit |
| 1451 | {16, 0}, // #65 WriteFloatFMA_WriteDouble |
| 1452 | { 1, 0}, // #66 WriteSALUDummy |
| 1453 | { 8, 0}, // #67 WriteDoubleAdd |
| 1454 | { 1, 0} // #68 Write32Bit |
| 1455 | }; // AMDGPUWriteLatencyTable |
| 1456 | |
| 1457 | // {UseIdx, WriteResourceID, Cycles} |
| 1458 | extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[] = { |
| 1459 | {0, 0, 0}, // Invalid |
| 1460 | {0, 0, -4}, // #1 |
| 1461 | {0, 0, -2} // #2 |
| 1462 | }; // AMDGPUReadAdvanceTable |
| 1463 | |
| 1464 | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, ReadAdvanceIdx, WriteProcResIdx, WriteLatencyIdx, NumReadAdvanceEntries, NumWriteProcResEntries, NumWriteLatencyEntries} |
| 1465 | static const llvm::MCSchedClassDesc GFX10SpeedModelSchedClasses[] = { |
| 1466 | {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
| 1467 | {DBGFIELD(/*NullALU_WriteSALU*/ 19) 1, false, false, true, 0, 1, 1, 0, 2, 1}, // #1 |
| 1468 | {DBGFIELD(/*NullALU_Write32Bit*/ 37) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #2 |
| 1469 | {DBGFIELD(/*NullALU_Write32Bit_Write32Bit*/ 56) 2, false, false, true, 0, 5, 3, 0, 2, 2}, // #3 |
| 1470 | {DBGFIELD(/*NullALU_WriteVMEM*/ 86) 1, false, false, true, 0, 7, 5, 0, 2, 1}, // #4 |
| 1471 | {DBGFIELD(/*NullALU_WriteVMEM_WriteLDS*/ 104) 2, false, false, true, 0, 9, 6, 0, 3, 2}, // #5 |
| 1472 | {DBGFIELD(/*NullALU_WriteLDS*/ 131) 1, false, false, true, 0, 12, 7, 0, 2, 1}, // #6 |
| 1473 | {DBGFIELD(/*NullALU_WriteLDS_WriteLDS*/ 148) 2, false, false, true, 0, 14, 8, 0, 2, 2}, // #7 |
| 1474 | {DBGFIELD(/*NullALU_WriteExport*/ 174) 1, false, false, true, 0, 16, 10, 0, 2, 1}, // #8 |
| 1475 | {DBGFIELD(/*WriteBranch*/ 194) 1, false, false, true, 0, 18, 11, 0, 1, 1}, // #9 |
| 1476 | {DBGFIELD(/*NullALU*/ 206) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #10 |
| 1477 | {DBGFIELD(/*NullALU_WriteBranch*/ 214) 1, false, false, true, 0, 18, 11, 0, 1, 1}, // #11 |
| 1478 | {DBGFIELD(/*NullALU_WriteSFPU*/ 234) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #12 |
| 1479 | {DBGFIELD(/*NullALU_WriteSMEM*/ 252) 1, false, false, true, 0, 12, 7, 0, 2, 1}, // #13 |
| 1480 | {DBGFIELD(/*NullALU_WriteBarrier*/ 270) 1, false, false, true, 0, 18, 12, 0, 1, 1}, // #14 |
| 1481 | {DBGFIELD(/*NullALU_WriteSALU_Write64Bit*/ 291) 2, false, false, true, 0, 19, 13, 0, 3, 2}, // #15 |
| 1482 | {DBGFIELD(/*NullALU_Write32Bit_WriteSALU*/ 320) 2, false, false, true, 0, 19, 15, 0, 3, 2}, // #16 |
| 1483 | {DBGFIELD(/*NullALU_WriteDoubleAdd*/ 349) 1, false, false, true, 0, 3, 17, 0, 2, 1}, // #17 |
| 1484 | {DBGFIELD(/*NullALU_Write64Bit*/ 372) 1, false, false, true, 0, 3, 14, 0, 2, 1}, // #18 |
| 1485 | {DBGFIELD(/*NullALU_WriteTrans32*/ 391) 1, false, false, true, 0, 22, 18, 0, 2, 1}, // #19 |
| 1486 | {DBGFIELD(/*NullALU_WriteFloatCvt*/ 412) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #20 |
| 1487 | {DBGFIELD(/*NullALU_WriteDoubleCvt*/ 434) 1, false, false, true, 0, 3, 17, 0, 2, 1}, // #21 |
| 1488 | {DBGFIELD(/*NullALU_WriteFloatFMA*/ 457) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #22 |
| 1489 | {DBGFIELD(/*NullALU_WriteDouble*/ 479) 1, false, false, true, 0, 3, 17, 0, 2, 1}, // #23 |
| 1490 | {DBGFIELD(/*NullALU_WriteFloatFMA_WriteSALUDummy*/ 499) 1, false, false, true, 0, 24, 15, 0, 3, 2}, // #24 |
| 1491 | {DBGFIELD(/*NullALU_WriteDouble_WriteSALUDummy*/ 536) 1, false, false, true, 0, 24, 19, 0, 3, 2}, // #25 |
| 1492 | {DBGFIELD(/*NullALU_WriteIntMul_WriteSALUDummy*/ 571) 1, false, false, true, 0, 24, 21, 0, 3, 2}, // #26 |
| 1493 | {DBGFIELD(/*NullALU_WriteIntMul*/ 606) 1, false, false, true, 0, 3, 21, 0, 2, 1}, // #27 |
| 1494 | {DBGFIELD(/*NullALU_WriteQuarterRate32*/ 626) 1, false, false, true, 0, 3, 21, 0, 2, 1}, // #28 |
| 1495 | {DBGFIELD(/*NullALU_Write32Bit_WriteVALUDummy*/ 653) 1, false, false, true, 0, 27, 2, 0, 2, 2}, // #29 |
| 1496 | {DBGFIELD(/*NullALU_WriteTrans64*/ 687) 1, false, false, true, 0, 29, 23, 0, 3, 1}, // #30 |
| 1497 | {DBGFIELD(/*NullALU_Write64Bit_Write64Bit*/ 708) 2, false, false, true, 0, 5, 24, 0, 2, 2}, // #31 |
| 1498 | {DBGFIELD(/*NullALU_WritePseudoScalarTrans*/ 738) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
| 1499 | {DBGFIELD(/*NullALU_WriteVMEM_WriteVMEM_WriteVMEM*/ 769) 3, false, false, true, 0, 32, 26, 0, 2, 3}, // #33 |
| 1500 | {DBGFIELD(/*NullALU_WriteDoubleAdd_Write32Bit*/ 807) 2, false, false, true, 0, 5, 29, 0, 2, 2}, // #34 |
| 1501 | {DBGFIELD(/*COPY*/ 841) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #35 |
| 1502 | {DBGFIELD(/*V_ACCVGPR_WRITE_B32_e64*/ 846) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #36 |
| 1503 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 870) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #37 |
| 1504 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 1996) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #38 |
| 1505 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 7379) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #39 |
| 1506 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 14259) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #40 |
| 1507 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 15206) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #41 |
| 1508 | {DBGFIELD(/*V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd*/ 20331) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #42 |
| 1509 | {DBGFIELD(/*V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi*/ 20460) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #43 |
| 1510 | {DBGFIELD(/*V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd*/ 21054) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #44 |
| 1511 | {DBGFIELD(/*V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi*/ 22045) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #45 |
| 1512 | {DBGFIELD(/*V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd*/ 23391) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #46 |
| 1513 | {DBGFIELD(/*V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 23589) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #47 |
| 1514 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd*/ 24372) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #48 |
| 1515 | {DBGFIELD(/*V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi*/ 25890) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #49 |
| 1516 | {DBGFIELD(/*V_SMFMAC_F32_16X16X128_BF8_BF8_e64_V_SMFMAC_F32_16X16X128_BF8_FP8_e64_V_SMFMAC_F32_16X16X128_FP8_BF8_e64_V_SMFMAC_F32_16X16X128_FP8_FP8_e64_V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_F16_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X128_I8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_F16_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X128_I8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940*/ 27751) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #50 |
| 1517 | {DBGFIELD(/*V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_F16_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_F32_32X32X64_BF8_BF8_e64_V_SMFMAC_F32_32X32X64_BF8_FP8_e64_V_SMFMAC_F32_32X32X64_FP8_BF8_e64_V_SMFMAC_F32_32X32X64_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_I32_32X32X64_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_F16_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940_V_SMFMAC_I32_32X32X64_I8_gfx940*/ 28707) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #51 |
| 1518 | {DBGFIELD(/*V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 29653) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #52 |
| 1519 | {DBGFIELD(/*V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd*/ 29782) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #53 |
| 1520 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 29980) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #54 |
| 1521 | {DBGFIELD(/*V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 31537) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #55 |
| 1522 | {DBGFIELD(/*V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd*/ 33310) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #56 |
| 1523 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_threeaddr*/ 35956) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #57 |
| 1524 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_twoaddr_V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250*/ 35993) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #58 |
| 1525 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr*/ 36071) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #59 |
| 1526 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250*/ 36407) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #60 |
| 1527 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X16_F16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_V_WMMA_F32_16X16X16_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 37111) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #61 |
| 1528 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X16_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X16_F16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X16_BF16_w32_threeaddr_V_WMMA_F32_16X16X16_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 38981) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #62 |
| 1529 | {DBGFIELD(/*V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 39334) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #63 |
| 1530 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr*/ 40806) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #64 |
| 1531 | {DBGFIELD(/*V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250*/ 41150) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #65 |
| 1532 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_w32_threeaddr_V_WMMA_I32_16X16X16_IU8_w32_threeaddr_V_WMMA_I32_16X16X32_IU4_w32_threeaddr_V_WMMA_I32_16X16X64_IU8_w32_threeaddr*/ 42066) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #66 |
| 1533 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr*/ 42218) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #67 |
| 1534 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250*/ 43640) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #68 |
| 1535 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr*/ 46448) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #69 |
| 1536 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr_V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250_V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250*/ 46576) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #70 |
| 1537 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 46828) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #71 |
| 1538 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 47548) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #72 |
| 1539 | {DBGFIELD(/*V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12*/ 48921) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #73 |
| 1540 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 49481) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #74 |
| 1541 | {DBGFIELD(/*V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12*/ 49679) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #75 |
| 1542 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_threeaddr_w32_V_WMMA_I32_16X16X16_IU4_threeaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_threeaddr_V_WMMA_I32_16X16X16_IU8_threeaddr_w32_V_WMMA_I32_16X16X16_IU8_threeaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_threeaddr_V_WMMA_I32_16X16X32_IU4_w64_threeaddr*/ 50741) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #76 |
| 1543 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_threeaddr*/ 51007) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #77 |
| 1544 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_twoaddr_V_WMMA_F64_16X16X4_F64_w32_twoaddr_gfx1250*/ 51044) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #78 |
| 1545 | {DBGFIELD(/*Write32Bit*/ 51122) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #79 |
| 1546 | {DBGFIELD(/*Write64Bit*/ 51133) 1, false, false, true, 0, 3, 14, 0, 2, 1}, // #80 |
| 1547 | {DBGFIELD(/*WriteSALU*/ 51144) 1, false, false, true, 0, 1, 1, 0, 2, 1}, // #81 |
| 1548 | {DBGFIELD(/*Write64Bit_MIVGPRRead*/ 51154) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #82 |
| 1549 | {DBGFIELD(/*Write64Bit_ReadDefault*/ 51176) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #83 |
| 1550 | {DBGFIELD(/*Write16PassMAI_MIMFMARead*/ 51199) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #84 |
| 1551 | {DBGFIELD(/*Write8PassMAI_MIMFMARead*/ 51225) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #85 |
| 1552 | {DBGFIELD(/*Write4PassMAI_MIMFMARead*/ 51250) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #86 |
| 1553 | {DBGFIELD(/*WriteXDL2PassWMMA*/ 51275) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #87 |
| 1554 | {DBGFIELD(/*WriteXDL1PassWMMA*/ 51293) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #88 |
| 1555 | {DBGFIELD(/*WriteXDL4PassWMMA*/ 51311) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #89 |
| 1556 | {DBGFIELD(/*WriteXDL8PassWMMA*/ 51329) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #90 |
| 1557 | }; // GFX10SpeedModelSchedClasses |
| 1558 | |
| 1559 | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, ReadAdvanceIdx, WriteProcResIdx, WriteLatencyIdx, NumReadAdvanceEntries, NumWriteProcResEntries, NumWriteLatencyEntries} |
| 1560 | static const llvm::MCSchedClassDesc GFX11SpeedModelSchedClasses[] = { |
| 1561 | {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
| 1562 | {DBGFIELD(/*NullALU_WriteSALU*/ 19) 1, false, false, true, 0, 1, 1, 0, 2, 1}, // #1 |
| 1563 | {DBGFIELD(/*NullALU_Write32Bit*/ 37) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #2 |
| 1564 | {DBGFIELD(/*NullALU_Write32Bit_Write32Bit*/ 56) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #3 |
| 1565 | {DBGFIELD(/*NullALU_WriteVMEM*/ 86) 1, false, false, true, 0, 7, 5, 0, 2, 1}, // #4 |
| 1566 | {DBGFIELD(/*NullALU_WriteVMEM_WriteLDS*/ 104) 2, false, false, true, 0, 9, 6, 0, 3, 2}, // #5 |
| 1567 | {DBGFIELD(/*NullALU_WriteLDS*/ 131) 1, false, false, true, 0, 12, 7, 0, 2, 1}, // #6 |
| 1568 | {DBGFIELD(/*NullALU_WriteLDS_WriteLDS*/ 148) 2, false, false, true, 0, 14, 7, 0, 2, 2}, // #7 |
| 1569 | {DBGFIELD(/*NullALU_WriteExport*/ 174) 1, false, false, true, 0, 16, 10, 0, 2, 1}, // #8 |
| 1570 | {DBGFIELD(/*WriteBranch*/ 194) 1, false, false, true, 0, 18, 11, 0, 1, 1}, // #9 |
| 1571 | {DBGFIELD(/*NullALU*/ 206) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #10 |
| 1572 | {DBGFIELD(/*NullALU_WriteBranch*/ 214) 1, false, false, true, 0, 18, 11, 0, 1, 1}, // #11 |
| 1573 | {DBGFIELD(/*NullALU_WriteSFPU*/ 234) 1, false, false, true, 0, 1, 31, 0, 2, 1}, // #12 |
| 1574 | {DBGFIELD(/*NullALU_WriteSMEM*/ 252) 1, false, false, true, 0, 12, 7, 0, 2, 1}, // #13 |
| 1575 | {DBGFIELD(/*NullALU_WriteBarrier*/ 270) 1, false, false, true, 0, 18, 12, 0, 1, 1}, // #14 |
| 1576 | {DBGFIELD(/*NullALU_WriteSALU_Write64Bit*/ 291) 2, false, false, true, 0, 19, 13, 0, 3, 2}, // #15 |
| 1577 | {DBGFIELD(/*NullALU_Write32Bit_WriteSALU*/ 320) 2, false, false, true, 0, 19, 15, 0, 3, 2}, // #16 |
| 1578 | {DBGFIELD(/*NullALU_WriteDoubleAdd*/ 349) 1, false, false, true, 0, 3, 32, 0, 2, 1}, // #17 |
| 1579 | {DBGFIELD(/*NullALU_Write64Bit*/ 372) 1, false, false, true, 0, 3, 14, 0, 2, 1}, // #18 |
| 1580 | {DBGFIELD(/*NullALU_WriteTrans32*/ 391) 1, false, false, true, 0, 22, 18, 0, 2, 1}, // #19 |
| 1581 | {DBGFIELD(/*NullALU_WriteFloatCvt*/ 412) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #20 |
| 1582 | {DBGFIELD(/*NullALU_WriteDoubleCvt*/ 434) 1, false, false, true, 0, 3, 32, 0, 2, 1}, // #21 |
| 1583 | {DBGFIELD(/*NullALU_WriteFloatFMA*/ 457) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #22 |
| 1584 | {DBGFIELD(/*NullALU_WriteDouble*/ 479) 1, false, false, true, 0, 3, 32, 0, 2, 1}, // #23 |
| 1585 | {DBGFIELD(/*NullALU_WriteFloatFMA_WriteSALUDummy*/ 499) 1, false, false, true, 0, 24, 15, 0, 3, 2}, // #24 |
| 1586 | {DBGFIELD(/*NullALU_WriteDouble_WriteSALUDummy*/ 536) 1, false, false, true, 0, 24, 33, 0, 3, 2}, // #25 |
| 1587 | {DBGFIELD(/*NullALU_WriteIntMul_WriteSALUDummy*/ 571) 1, false, false, true, 0, 24, 21, 0, 3, 2}, // #26 |
| 1588 | {DBGFIELD(/*NullALU_WriteIntMul*/ 606) 1, false, false, true, 0, 3, 21, 0, 2, 1}, // #27 |
| 1589 | {DBGFIELD(/*NullALU_WriteQuarterRate32*/ 626) 1, false, false, true, 0, 3, 21, 0, 2, 1}, // #28 |
| 1590 | {DBGFIELD(/*NullALU_Write32Bit_WriteVALUDummy*/ 653) 1, false, false, true, 0, 27, 2, 0, 2, 2}, // #29 |
| 1591 | {DBGFIELD(/*NullALU_WriteTrans64*/ 687) 1, false, false, true, 0, 29, 35, 0, 3, 1}, // #30 |
| 1592 | {DBGFIELD(/*NullALU_Write64Bit_Write64Bit*/ 708) 2, false, false, true, 0, 5, 24, 0, 2, 2}, // #31 |
| 1593 | {DBGFIELD(/*NullALU_WritePseudoScalarTrans*/ 738) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
| 1594 | {DBGFIELD(/*NullALU_WriteVMEM_WriteVMEM_WriteVMEM*/ 769) 3, false, false, true, 0, 32, 26, 0, 2, 3}, // #33 |
| 1595 | {DBGFIELD(/*NullALU_WriteDoubleAdd_Write32Bit*/ 807) 2, false, false, true, 0, 5, 36, 0, 2, 2}, // #34 |
| 1596 | {DBGFIELD(/*COPY*/ 841) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #35 |
| 1597 | {DBGFIELD(/*V_ACCVGPR_WRITE_B32_e64*/ 846) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #36 |
| 1598 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 870) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #37 |
| 1599 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 1996) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #38 |
| 1600 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 7379) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #39 |
| 1601 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 14259) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #40 |
| 1602 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 15206) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #41 |
| 1603 | {DBGFIELD(/*V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd*/ 20331) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #42 |
| 1604 | {DBGFIELD(/*V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi*/ 20460) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #43 |
| 1605 | {DBGFIELD(/*V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd*/ 21054) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #44 |
| 1606 | {DBGFIELD(/*V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi*/ 22045) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #45 |
| 1607 | {DBGFIELD(/*V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd*/ 23391) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #46 |
| 1608 | {DBGFIELD(/*V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 23589) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #47 |
| 1609 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd*/ 24372) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #48 |
| 1610 | {DBGFIELD(/*V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi*/ 25890) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #49 |
| 1611 | {DBGFIELD(/*V_SMFMAC_F32_16X16X128_BF8_BF8_e64_V_SMFMAC_F32_16X16X128_BF8_FP8_e64_V_SMFMAC_F32_16X16X128_FP8_BF8_e64_V_SMFMAC_F32_16X16X128_FP8_FP8_e64_V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_F16_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X128_I8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_F16_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X128_I8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940*/ 27751) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #50 |
| 1612 | {DBGFIELD(/*V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_F16_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_F32_32X32X64_BF8_BF8_e64_V_SMFMAC_F32_32X32X64_BF8_FP8_e64_V_SMFMAC_F32_32X32X64_FP8_BF8_e64_V_SMFMAC_F32_32X32X64_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_I32_32X32X64_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_F16_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940_V_SMFMAC_I32_32X32X64_I8_gfx940*/ 28707) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #51 |
| 1613 | {DBGFIELD(/*V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 29653) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #52 |
| 1614 | {DBGFIELD(/*V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd*/ 29782) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #53 |
| 1615 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 29980) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #54 |
| 1616 | {DBGFIELD(/*V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 31537) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #55 |
| 1617 | {DBGFIELD(/*V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd*/ 33310) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #56 |
| 1618 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_threeaddr*/ 35956) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #57 |
| 1619 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_twoaddr_V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250*/ 35993) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #58 |
| 1620 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr*/ 36071) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #59 |
| 1621 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250*/ 36407) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #60 |
| 1622 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X16_F16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_V_WMMA_F32_16X16X16_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 37111) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #61 |
| 1623 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X16_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X16_F16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X16_BF16_w32_threeaddr_V_WMMA_F32_16X16X16_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 38981) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #62 |
| 1624 | {DBGFIELD(/*V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 39334) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #63 |
| 1625 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr*/ 40806) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #64 |
| 1626 | {DBGFIELD(/*V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250*/ 41150) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #65 |
| 1627 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_w32_threeaddr_V_WMMA_I32_16X16X16_IU8_w32_threeaddr_V_WMMA_I32_16X16X32_IU4_w32_threeaddr_V_WMMA_I32_16X16X64_IU8_w32_threeaddr*/ 42066) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #66 |
| 1628 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr*/ 42218) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #67 |
| 1629 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250*/ 43640) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #68 |
| 1630 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr*/ 46448) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #69 |
| 1631 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr_V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250_V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250*/ 46576) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #70 |
| 1632 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 46828) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #71 |
| 1633 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 47548) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #72 |
| 1634 | {DBGFIELD(/*V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12*/ 48921) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #73 |
| 1635 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 49481) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #74 |
| 1636 | {DBGFIELD(/*V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12*/ 49679) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #75 |
| 1637 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_threeaddr_w32_V_WMMA_I32_16X16X16_IU4_threeaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_threeaddr_V_WMMA_I32_16X16X16_IU8_threeaddr_w32_V_WMMA_I32_16X16X16_IU8_threeaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_threeaddr_V_WMMA_I32_16X16X32_IU4_w64_threeaddr*/ 50741) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #76 |
| 1638 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_threeaddr*/ 51007) 2, false, false, true, 0, 5, 2, 0, 2, 2}, // #77 |
| 1639 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_twoaddr_V_WMMA_F64_16X16X4_F64_w32_twoaddr_gfx1250*/ 51044) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #78 |
| 1640 | {DBGFIELD(/*Write32Bit*/ 51122) 1, false, false, true, 0, 3, 2, 0, 2, 1}, // #79 |
| 1641 | {DBGFIELD(/*Write64Bit*/ 51133) 1, false, false, true, 0, 3, 14, 0, 2, 1}, // #80 |
| 1642 | {DBGFIELD(/*WriteSALU*/ 51144) 1, false, false, true, 0, 1, 1, 0, 2, 1}, // #81 |
| 1643 | {DBGFIELD(/*Write64Bit_MIVGPRRead*/ 51154) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #82 |
| 1644 | {DBGFIELD(/*Write64Bit_ReadDefault*/ 51176) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #83 |
| 1645 | {DBGFIELD(/*Write16PassMAI_MIMFMARead*/ 51199) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #84 |
| 1646 | {DBGFIELD(/*Write8PassMAI_MIMFMARead*/ 51225) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #85 |
| 1647 | {DBGFIELD(/*Write4PassMAI_MIMFMARead*/ 51250) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #86 |
| 1648 | {DBGFIELD(/*WriteXDL2PassWMMA*/ 51275) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #87 |
| 1649 | {DBGFIELD(/*WriteXDL1PassWMMA*/ 51293) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #88 |
| 1650 | {DBGFIELD(/*WriteXDL4PassWMMA*/ 51311) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #89 |
| 1651 | {DBGFIELD(/*WriteXDL8PassWMMA*/ 51329) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #90 |
| 1652 | }; // GFX11SpeedModelSchedClasses |
| 1653 | |
| 1654 | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, ReadAdvanceIdx, WriteProcResIdx, WriteLatencyIdx, NumReadAdvanceEntries, NumWriteProcResEntries, NumWriteLatencyEntries} |
| 1655 | static const llvm::MCSchedClassDesc GFX125xGenericSpeedModelSchedClasses[] = { |
| 1656 | {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
| 1657 | {DBGFIELD(/*NullALU_WriteSALU*/ 19) 1, false, false, false, 0, 1, 1, 0, 2, 1}, // #1 |
| 1658 | {DBGFIELD(/*NullALU_Write32Bit*/ 37) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #2 |
| 1659 | {DBGFIELD(/*NullALU_Write32Bit_Write32Bit*/ 56) 2, false, false, false, 0, 5, 2, 0, 2, 2}, // #3 |
| 1660 | {DBGFIELD(/*NullALU_WriteVMEM*/ 86) 1, false, false, false, 0, 7, 5, 0, 2, 1}, // #4 |
| 1661 | {DBGFIELD(/*NullALU_WriteVMEM_WriteLDS*/ 104) 2, false, false, false, 0, 9, 6, 0, 3, 2}, // #5 |
| 1662 | {DBGFIELD(/*NullALU_WriteLDS*/ 131) 1, false, false, false, 0, 12, 7, 0, 2, 1}, // #6 |
| 1663 | {DBGFIELD(/*NullALU_WriteLDS_WriteLDS*/ 148) 2, false, false, false, 0, 14, 7, 0, 2, 2}, // #7 |
| 1664 | {DBGFIELD(/*NullALU_WriteExport*/ 174) 1, false, false, false, 0, 16, 10, 0, 2, 1}, // #8 |
| 1665 | {DBGFIELD(/*WriteBranch*/ 194) 1, false, false, false, 0, 18, 11, 0, 1, 1}, // #9 |
| 1666 | {DBGFIELD(/*NullALU*/ 206) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #10 |
| 1667 | {DBGFIELD(/*NullALU_WriteBranch*/ 214) 1, false, false, false, 0, 18, 11, 0, 1, 1}, // #11 |
| 1668 | {DBGFIELD(/*NullALU_WriteSFPU*/ 234) 1, false, false, false, 0, 1, 31, 0, 2, 1}, // #12 |
| 1669 | {DBGFIELD(/*NullALU_WriteSMEM*/ 252) 1, false, false, false, 0, 12, 7, 0, 2, 1}, // #13 |
| 1670 | {DBGFIELD(/*NullALU_WriteBarrier*/ 270) 1, false, false, false, 0, 18, 12, 0, 1, 1}, // #14 |
| 1671 | {DBGFIELD(/*NullALU_WriteSALU_Write64Bit*/ 291) 2, false, false, false, 0, 19, 13, 0, 3, 2}, // #15 |
| 1672 | {DBGFIELD(/*NullALU_Write32Bit_WriteSALU*/ 320) 2, false, false, false, 0, 19, 15, 0, 3, 2}, // #16 |
| 1673 | {DBGFIELD(/*NullALU_WriteDoubleAdd*/ 349) 1, false, false, false, 0, 3, 38, 0, 2, 1}, // #17 |
| 1674 | {DBGFIELD(/*NullALU_Write64Bit*/ 372) 1, false, false, false, 0, 3, 14, 0, 2, 1}, // #18 |
| 1675 | {DBGFIELD(/*NullALU_WriteTrans32*/ 391) 1, false, false, false, 0, 22, 21, 0, 2, 1}, // #19 |
| 1676 | {DBGFIELD(/*NullALU_WriteFloatCvt*/ 412) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #20 |
| 1677 | {DBGFIELD(/*NullALU_WriteDoubleCvt*/ 434) 1, false, false, false, 0, 3, 38, 0, 2, 1}, // #21 |
| 1678 | {DBGFIELD(/*NullALU_WriteFloatFMA*/ 457) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #22 |
| 1679 | {DBGFIELD(/*NullALU_WriteDouble*/ 479) 1, false, false, false, 0, 3, 38, 0, 2, 1}, // #23 |
| 1680 | {DBGFIELD(/*NullALU_WriteFloatFMA_WriteSALUDummy*/ 499) 1, false, false, false, 0, 24, 15, 0, 3, 2}, // #24 |
| 1681 | {DBGFIELD(/*NullALU_WriteDouble_WriteSALUDummy*/ 536) 1, false, false, false, 0, 24, 39, 0, 3, 2}, // #25 |
| 1682 | {DBGFIELD(/*NullALU_WriteIntMul_WriteSALUDummy*/ 571) 1, false, false, false, 0, 24, 21, 0, 3, 2}, // #26 |
| 1683 | {DBGFIELD(/*NullALU_WriteIntMul*/ 606) 1, false, false, false, 0, 3, 21, 0, 2, 1}, // #27 |
| 1684 | {DBGFIELD(/*NullALU_WriteQuarterRate32*/ 626) 1, false, false, false, 0, 3, 14, 0, 2, 1}, // #28 |
| 1685 | {DBGFIELD(/*NullALU_Write32Bit_WriteVALUDummy*/ 653) 1, false, false, false, 0, 27, 2, 0, 2, 2}, // #29 |
| 1686 | {DBGFIELD(/*NullALU_WriteTrans64*/ 687) 1, false, false, false, 0, 29, 32, 0, 3, 1}, // #30 |
| 1687 | {DBGFIELD(/*NullALU_Write64Bit_Write64Bit*/ 708) 2, false, false, false, 0, 5, 24, 0, 2, 2}, // #31 |
| 1688 | {DBGFIELD(/*NullALU_WritePseudoScalarTrans*/ 738) 1, false, false, false, 0, 3, 21, 0, 2, 1}, // #32 |
| 1689 | {DBGFIELD(/*NullALU_WriteVMEM_WriteVMEM_WriteVMEM*/ 769) 3, false, false, false, 0, 32, 26, 0, 2, 3}, // #33 |
| 1690 | {DBGFIELD(/*NullALU_WriteDoubleAdd_Write32Bit*/ 807) 2, false, false, false, 0, 5, 41, 0, 2, 2}, // #34 |
| 1691 | {DBGFIELD(/*COPY*/ 841) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #35 |
| 1692 | {DBGFIELD(/*V_ACCVGPR_WRITE_B32_e64*/ 846) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #36 |
| 1693 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 870) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #37 |
| 1694 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 1996) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #38 |
| 1695 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 7379) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #39 |
| 1696 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 14259) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #40 |
| 1697 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 15206) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #41 |
| 1698 | {DBGFIELD(/*V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd*/ 20331) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #42 |
| 1699 | {DBGFIELD(/*V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi*/ 20460) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #43 |
| 1700 | {DBGFIELD(/*V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd*/ 21054) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #44 |
| 1701 | {DBGFIELD(/*V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi*/ 22045) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #45 |
| 1702 | {DBGFIELD(/*V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd*/ 23391) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #46 |
| 1703 | {DBGFIELD(/*V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 23589) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #47 |
| 1704 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd*/ 24372) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #48 |
| 1705 | {DBGFIELD(/*V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi*/ 25890) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #49 |
| 1706 | {DBGFIELD(/*V_SMFMAC_F32_16X16X128_BF8_BF8_e64_V_SMFMAC_F32_16X16X128_BF8_FP8_e64_V_SMFMAC_F32_16X16X128_FP8_BF8_e64_V_SMFMAC_F32_16X16X128_FP8_FP8_e64_V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_F16_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X128_I8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_F16_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X128_I8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940*/ 27751) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #50 |
| 1707 | {DBGFIELD(/*V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_F16_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_F32_32X32X64_BF8_BF8_e64_V_SMFMAC_F32_32X32X64_BF8_FP8_e64_V_SMFMAC_F32_32X32X64_FP8_BF8_e64_V_SMFMAC_F32_32X32X64_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_I32_32X32X64_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_F16_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940_V_SMFMAC_I32_32X32X64_I8_gfx940*/ 28707) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #51 |
| 1708 | {DBGFIELD(/*V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 29653) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #52 |
| 1709 | {DBGFIELD(/*V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd*/ 29782) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #53 |
| 1710 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 29980) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #54 |
| 1711 | {DBGFIELD(/*V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 31537) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #55 |
| 1712 | {DBGFIELD(/*V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd*/ 33310) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #56 |
| 1713 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_threeaddr*/ 35956) 1, false, false, false, 0, 4, 10, 0, 1, 1}, // #57 |
| 1714 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_twoaddr_V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250*/ 35993) 1, false, false, false, 0, 4, 10, 0, 1, 1}, // #58 |
| 1715 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr*/ 36071) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #59 |
| 1716 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250*/ 36407) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #60 |
| 1717 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X16_F16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_V_WMMA_F32_16X16X16_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 37111) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #61 |
| 1718 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X16_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X16_F16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X16_BF16_w32_threeaddr_V_WMMA_F32_16X16X16_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 38981) 2, false, false, false, 0, 5, 2, 0, 2, 2}, // #62 |
| 1719 | {DBGFIELD(/*V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 39334) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #63 |
| 1720 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr*/ 40806) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #64 |
| 1721 | {DBGFIELD(/*V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250*/ 41150) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #65 |
| 1722 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_w32_threeaddr_V_WMMA_I32_16X16X16_IU8_w32_threeaddr_V_WMMA_I32_16X16X32_IU4_w32_threeaddr_V_WMMA_I32_16X16X64_IU8_w32_threeaddr*/ 42066) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #66 |
| 1723 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr*/ 42218) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #67 |
| 1724 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250*/ 43640) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #68 |
| 1725 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr*/ 46448) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #69 |
| 1726 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr_V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250_V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250*/ 46576) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #70 |
| 1727 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 46828) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #71 |
| 1728 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 47548) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #72 |
| 1729 | {DBGFIELD(/*V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12*/ 48921) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #73 |
| 1730 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 49481) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #74 |
| 1731 | {DBGFIELD(/*V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12*/ 49679) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #75 |
| 1732 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_threeaddr_w32_V_WMMA_I32_16X16X16_IU4_threeaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_threeaddr_V_WMMA_I32_16X16X16_IU8_threeaddr_w32_V_WMMA_I32_16X16X16_IU8_threeaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_threeaddr_V_WMMA_I32_16X16X32_IU4_w64_threeaddr*/ 50741) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #76 |
| 1733 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_threeaddr*/ 51007) 2, false, false, false, 0, 5, 2, 0, 2, 2}, // #77 |
| 1734 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_twoaddr_V_WMMA_F64_16X16X4_F64_w32_twoaddr_gfx1250*/ 51044) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #78 |
| 1735 | {DBGFIELD(/*Write32Bit*/ 51122) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #79 |
| 1736 | {DBGFIELD(/*Write64Bit*/ 51133) 1, false, false, false, 0, 3, 14, 0, 2, 1}, // #80 |
| 1737 | {DBGFIELD(/*WriteSALU*/ 51144) 1, false, false, false, 0, 1, 1, 0, 2, 1}, // #81 |
| 1738 | {DBGFIELD(/*Write64Bit_MIVGPRRead*/ 51154) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #82 |
| 1739 | {DBGFIELD(/*Write64Bit_ReadDefault*/ 51176) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #83 |
| 1740 | {DBGFIELD(/*Write16PassMAI_MIMFMARead*/ 51199) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #84 |
| 1741 | {DBGFIELD(/*Write8PassMAI_MIMFMARead*/ 51225) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #85 |
| 1742 | {DBGFIELD(/*Write4PassMAI_MIMFMARead*/ 51250) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #86 |
| 1743 | {DBGFIELD(/*WriteXDL2PassWMMA*/ 51275) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #87 |
| 1744 | {DBGFIELD(/*WriteXDL1PassWMMA*/ 51293) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #88 |
| 1745 | {DBGFIELD(/*WriteXDL4PassWMMA*/ 51311) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #89 |
| 1746 | {DBGFIELD(/*WriteXDL8PassWMMA*/ 51329) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #90 |
| 1747 | }; // GFX125xGenericSpeedModelSchedClasses |
| 1748 | |
| 1749 | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, ReadAdvanceIdx, WriteProcResIdx, WriteLatencyIdx, NumReadAdvanceEntries, NumWriteProcResEntries, NumWriteLatencyEntries} |
| 1750 | static const llvm::MCSchedClassDesc GFX12SpeedModelSchedClasses[] = { |
| 1751 | {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
| 1752 | {DBGFIELD(/*NullALU_WriteSALU*/ 19) 1, false, false, false, 0, 1, 1, 0, 2, 1}, // #1 |
| 1753 | {DBGFIELD(/*NullALU_Write32Bit*/ 37) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #2 |
| 1754 | {DBGFIELD(/*NullALU_Write32Bit_Write32Bit*/ 56) 2, false, false, false, 0, 36, 2, 0, 2, 2}, // #3 |
| 1755 | {DBGFIELD(/*NullALU_WriteVMEM*/ 86) 1, false, false, false, 0, 3, 5, 0, 2, 1}, // #4 |
| 1756 | {DBGFIELD(/*NullALU_WriteVMEM_WriteLDS*/ 104) 2, false, false, false, 0, 38, 6, 0, 3, 2}, // #5 |
| 1757 | {DBGFIELD(/*NullALU_WriteLDS*/ 131) 1, false, false, false, 0, 12, 7, 0, 2, 1}, // #6 |
| 1758 | {DBGFIELD(/*NullALU_WriteLDS_WriteLDS*/ 148) 2, false, false, false, 0, 14, 7, 0, 2, 2}, // #7 |
| 1759 | {DBGFIELD(/*NullALU_WriteExport*/ 174) 1, false, false, false, 0, 16, 10, 0, 2, 1}, // #8 |
| 1760 | {DBGFIELD(/*WriteBranch*/ 194) 1, false, false, false, 0, 18, 11, 0, 1, 1}, // #9 |
| 1761 | {DBGFIELD(/*NullALU*/ 206) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #10 |
| 1762 | {DBGFIELD(/*NullALU_WriteBranch*/ 214) 1, false, false, false, 0, 18, 11, 0, 1, 1}, // #11 |
| 1763 | {DBGFIELD(/*NullALU_WriteSFPU*/ 234) 1, false, false, false, 0, 1, 31, 0, 2, 1}, // #12 |
| 1764 | {DBGFIELD(/*NullALU_WriteSMEM*/ 252) 1, false, false, false, 0, 12, 7, 0, 2, 1}, // #13 |
| 1765 | {DBGFIELD(/*NullALU_WriteBarrier*/ 270) 1, false, false, false, 0, 18, 12, 0, 1, 1}, // #14 |
| 1766 | {DBGFIELD(/*NullALU_WriteSALU_Write64Bit*/ 291) 2, false, false, false, 0, 41, 13, 0, 3, 2}, // #15 |
| 1767 | {DBGFIELD(/*NullALU_Write32Bit_WriteSALU*/ 320) 2, false, false, false, 0, 41, 15, 0, 3, 2}, // #16 |
| 1768 | {DBGFIELD(/*NullALU_WriteDoubleAdd*/ 349) 1, false, false, false, 0, 22, 32, 0, 2, 1}, // #17 |
| 1769 | {DBGFIELD(/*NullALU_Write64Bit*/ 372) 1, false, false, false, 0, 22, 14, 0, 2, 1}, // #18 |
| 1770 | {DBGFIELD(/*NullALU_WriteTrans32*/ 391) 1, false, false, false, 0, 22, 43, 0, 2, 1}, // #19 |
| 1771 | {DBGFIELD(/*NullALU_WriteFloatCvt*/ 412) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #20 |
| 1772 | {DBGFIELD(/*NullALU_WriteDoubleCvt*/ 434) 1, false, false, false, 0, 22, 32, 0, 2, 1}, // #21 |
| 1773 | {DBGFIELD(/*NullALU_WriteFloatFMA*/ 457) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #22 |
| 1774 | {DBGFIELD(/*NullALU_WriteDouble*/ 479) 1, false, false, false, 0, 22, 32, 0, 2, 1}, // #23 |
| 1775 | {DBGFIELD(/*NullALU_WriteFloatFMA_WriteSALUDummy*/ 499) 1, false, false, false, 0, 44, 15, 0, 3, 2}, // #24 |
| 1776 | {DBGFIELD(/*NullALU_WriteDouble_WriteSALUDummy*/ 536) 1, false, false, false, 0, 44, 33, 0, 3, 2}, // #25 |
| 1777 | {DBGFIELD(/*NullALU_WriteIntMul_WriteSALUDummy*/ 571) 1, false, false, false, 0, 44, 21, 0, 3, 2}, // #26 |
| 1778 | {DBGFIELD(/*NullALU_WriteIntMul*/ 606) 1, false, false, false, 0, 22, 21, 0, 2, 1}, // #27 |
| 1779 | {DBGFIELD(/*NullALU_WriteQuarterRate32*/ 626) 1, false, false, false, 0, 22, 14, 0, 2, 1}, // #28 |
| 1780 | {DBGFIELD(/*NullALU_Write32Bit_WriteVALUDummy*/ 653) 1, false, false, false, 0, 47, 2, 0, 2, 2}, // #29 |
| 1781 | {DBGFIELD(/*NullALU_WriteTrans64*/ 687) 1, false, false, false, 0, 22, 35, 0, 2, 1}, // #30 |
| 1782 | {DBGFIELD(/*NullALU_Write64Bit_Write64Bit*/ 708) 2, false, false, false, 0, 36, 24, 0, 2, 2}, // #31 |
| 1783 | {DBGFIELD(/*NullALU_WritePseudoScalarTrans*/ 738) 1, false, false, false, 0, 22, 21, 0, 2, 1}, // #32 |
| 1784 | {DBGFIELD(/*NullALU_WriteVMEM_WriteVMEM_WriteVMEM*/ 769) 3, false, false, false, 0, 49, 26, 0, 2, 3}, // #33 |
| 1785 | {DBGFIELD(/*NullALU_WriteDoubleAdd_Write32Bit*/ 807) 2, false, false, false, 0, 36, 36, 0, 2, 2}, // #34 |
| 1786 | {DBGFIELD(/*COPY*/ 841) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #35 |
| 1787 | {DBGFIELD(/*V_ACCVGPR_WRITE_B32_e64*/ 846) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #36 |
| 1788 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 870) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #37 |
| 1789 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 1996) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #38 |
| 1790 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 7379) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #39 |
| 1791 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 14259) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #40 |
| 1792 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 15206) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #41 |
| 1793 | {DBGFIELD(/*V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd*/ 20331) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #42 |
| 1794 | {DBGFIELD(/*V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi*/ 20460) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #43 |
| 1795 | {DBGFIELD(/*V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd*/ 21054) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #44 |
| 1796 | {DBGFIELD(/*V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi*/ 22045) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #45 |
| 1797 | {DBGFIELD(/*V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd*/ 23391) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #46 |
| 1798 | {DBGFIELD(/*V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 23589) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #47 |
| 1799 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd*/ 24372) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #48 |
| 1800 | {DBGFIELD(/*V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi*/ 25890) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #49 |
| 1801 | {DBGFIELD(/*V_SMFMAC_F32_16X16X128_BF8_BF8_e64_V_SMFMAC_F32_16X16X128_BF8_FP8_e64_V_SMFMAC_F32_16X16X128_FP8_BF8_e64_V_SMFMAC_F32_16X16X128_FP8_FP8_e64_V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_F16_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X128_I8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_F16_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X128_I8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940*/ 27751) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #50 |
| 1802 | {DBGFIELD(/*V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_F16_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_F32_32X32X64_BF8_BF8_e64_V_SMFMAC_F32_32X32X64_BF8_FP8_e64_V_SMFMAC_F32_32X32X64_FP8_BF8_e64_V_SMFMAC_F32_32X32X64_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_I32_32X32X64_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_F16_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940_V_SMFMAC_I32_32X32X64_I8_gfx940*/ 28707) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #51 |
| 1803 | {DBGFIELD(/*V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 29653) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #52 |
| 1804 | {DBGFIELD(/*V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd*/ 29782) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #53 |
| 1805 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 29980) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #54 |
| 1806 | {DBGFIELD(/*V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 31537) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #55 |
| 1807 | {DBGFIELD(/*V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd*/ 33310) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #56 |
| 1808 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_threeaddr*/ 35956) 2, false, false, false, 0, 36, 2, 0, 2, 2}, // #57 |
| 1809 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_twoaddr_V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250*/ 35993) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #58 |
| 1810 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr*/ 36071) 2, false, false, false, 0, 36, 2, 0, 2, 2}, // #59 |
| 1811 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250*/ 36407) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #60 |
| 1812 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X16_F16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_V_WMMA_F32_16X16X16_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 37111) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #61 |
| 1813 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X16_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X16_F16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X16_BF16_w32_threeaddr_V_WMMA_F32_16X16X16_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 38981) 2, false, false, false, 0, 36, 2, 0, 2, 2}, // #62 |
| 1814 | {DBGFIELD(/*V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 39334) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #63 |
| 1815 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr*/ 40806) 2, false, false, false, 0, 36, 2, 0, 2, 2}, // #64 |
| 1816 | {DBGFIELD(/*V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250*/ 41150) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #65 |
| 1817 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_w32_threeaddr_V_WMMA_I32_16X16X16_IU8_w32_threeaddr_V_WMMA_I32_16X16X32_IU4_w32_threeaddr_V_WMMA_I32_16X16X64_IU8_w32_threeaddr*/ 42066) 2, false, false, false, 0, 36, 2, 0, 2, 2}, // #66 |
| 1818 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr*/ 42218) 2, false, false, false, 0, 36, 2, 0, 2, 2}, // #67 |
| 1819 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250*/ 43640) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #68 |
| 1820 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr*/ 46448) 2, false, false, false, 0, 36, 2, 0, 2, 2}, // #69 |
| 1821 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr_V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250_V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250*/ 46576) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #70 |
| 1822 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 46828) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #71 |
| 1823 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 47548) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #72 |
| 1824 | {DBGFIELD(/*V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12*/ 48921) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #73 |
| 1825 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 49481) 2, false, false, false, 0, 36, 2, 0, 2, 2}, // #74 |
| 1826 | {DBGFIELD(/*V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12*/ 49679) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #75 |
| 1827 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_threeaddr_w32_V_WMMA_I32_16X16X16_IU4_threeaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_threeaddr_V_WMMA_I32_16X16X16_IU8_threeaddr_w32_V_WMMA_I32_16X16X16_IU8_threeaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_threeaddr_V_WMMA_I32_16X16X32_IU4_w64_threeaddr*/ 50741) 2, false, false, false, 0, 36, 2, 0, 2, 2}, // #76 |
| 1828 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_threeaddr*/ 51007) 2, false, false, false, 0, 36, 2, 0, 2, 2}, // #77 |
| 1829 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_twoaddr_V_WMMA_F64_16X16X4_F64_w32_twoaddr_gfx1250*/ 51044) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #78 |
| 1830 | {DBGFIELD(/*Write32Bit*/ 51122) 1, false, false, false, 0, 22, 2, 0, 2, 1}, // #79 |
| 1831 | {DBGFIELD(/*Write64Bit*/ 51133) 1, false, false, false, 0, 22, 14, 0, 2, 1}, // #80 |
| 1832 | {DBGFIELD(/*WriteSALU*/ 51144) 1, false, false, false, 0, 1, 1, 0, 2, 1}, // #81 |
| 1833 | {DBGFIELD(/*Write64Bit_MIVGPRRead*/ 51154) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #82 |
| 1834 | {DBGFIELD(/*Write64Bit_ReadDefault*/ 51176) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #83 |
| 1835 | {DBGFIELD(/*Write16PassMAI_MIMFMARead*/ 51199) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #84 |
| 1836 | {DBGFIELD(/*Write8PassMAI_MIMFMARead*/ 51225) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #85 |
| 1837 | {DBGFIELD(/*Write4PassMAI_MIMFMARead*/ 51250) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #86 |
| 1838 | {DBGFIELD(/*WriteXDL2PassWMMA*/ 51275) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #87 |
| 1839 | {DBGFIELD(/*WriteXDL1PassWMMA*/ 51293) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #88 |
| 1840 | {DBGFIELD(/*WriteXDL4PassWMMA*/ 51311) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #89 |
| 1841 | {DBGFIELD(/*WriteXDL8PassWMMA*/ 51329) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #90 |
| 1842 | }; // GFX12SpeedModelSchedClasses |
| 1843 | |
| 1844 | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, ReadAdvanceIdx, WriteProcResIdx, WriteLatencyIdx, NumReadAdvanceEntries, NumWriteProcResEntries, NumWriteLatencyEntries} |
| 1845 | static const llvm::MCSchedClassDesc GFX1250SpeedModelSchedClasses[] = { |
| 1846 | {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
| 1847 | {DBGFIELD(/*NullALU_WriteSALU*/ 19) 1, false, false, false, 0, 1, 1, 0, 2, 1}, // #1 |
| 1848 | {DBGFIELD(/*NullALU_Write32Bit*/ 37) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #2 |
| 1849 | {DBGFIELD(/*NullALU_Write32Bit_Write32Bit*/ 56) 2, false, false, false, 0, 5, 2, 0, 2, 2}, // #3 |
| 1850 | {DBGFIELD(/*NullALU_WriteVMEM*/ 86) 1, false, false, false, 0, 7, 5, 0, 2, 1}, // #4 |
| 1851 | {DBGFIELD(/*NullALU_WriteVMEM_WriteLDS*/ 104) 2, false, false, false, 0, 9, 6, 0, 3, 2}, // #5 |
| 1852 | {DBGFIELD(/*NullALU_WriteLDS*/ 131) 1, false, false, false, 0, 12, 7, 0, 2, 1}, // #6 |
| 1853 | {DBGFIELD(/*NullALU_WriteLDS_WriteLDS*/ 148) 2, false, false, false, 0, 14, 7, 0, 2, 2}, // #7 |
| 1854 | {DBGFIELD(/*NullALU_WriteExport*/ 174) 1, false, false, false, 0, 16, 10, 0, 2, 1}, // #8 |
| 1855 | {DBGFIELD(/*WriteBranch*/ 194) 1, false, false, false, 0, 18, 11, 0, 1, 1}, // #9 |
| 1856 | {DBGFIELD(/*NullALU*/ 206) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #10 |
| 1857 | {DBGFIELD(/*NullALU_WriteBranch*/ 214) 1, false, false, false, 0, 18, 11, 0, 1, 1}, // #11 |
| 1858 | {DBGFIELD(/*NullALU_WriteSFPU*/ 234) 1, false, false, false, 0, 1, 31, 0, 2, 1}, // #12 |
| 1859 | {DBGFIELD(/*NullALU_WriteSMEM*/ 252) 1, false, false, false, 0, 12, 7, 0, 2, 1}, // #13 |
| 1860 | {DBGFIELD(/*NullALU_WriteBarrier*/ 270) 1, false, false, false, 0, 18, 12, 0, 1, 1}, // #14 |
| 1861 | {DBGFIELD(/*NullALU_WriteSALU_Write64Bit*/ 291) 2, false, false, false, 0, 19, 13, 0, 3, 2}, // #15 |
| 1862 | {DBGFIELD(/*NullALU_Write32Bit_WriteSALU*/ 320) 2, false, false, false, 0, 19, 15, 0, 3, 2}, // #16 |
| 1863 | {DBGFIELD(/*NullALU_WriteDoubleAdd*/ 349) 1, false, false, false, 0, 3, 38, 0, 2, 1}, // #17 |
| 1864 | {DBGFIELD(/*NullALU_Write64Bit*/ 372) 1, false, false, false, 0, 3, 14, 0, 2, 1}, // #18 |
| 1865 | {DBGFIELD(/*NullALU_WriteTrans32*/ 391) 1, false, false, false, 0, 22, 21, 0, 2, 1}, // #19 |
| 1866 | {DBGFIELD(/*NullALU_WriteFloatCvt*/ 412) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #20 |
| 1867 | {DBGFIELD(/*NullALU_WriteDoubleCvt*/ 434) 1, false, false, false, 0, 3, 38, 0, 2, 1}, // #21 |
| 1868 | {DBGFIELD(/*NullALU_WriteFloatFMA*/ 457) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #22 |
| 1869 | {DBGFIELD(/*NullALU_WriteDouble*/ 479) 1, false, false, false, 0, 3, 38, 0, 2, 1}, // #23 |
| 1870 | {DBGFIELD(/*NullALU_WriteFloatFMA_WriteSALUDummy*/ 499) 1, false, false, false, 0, 24, 15, 0, 3, 2}, // #24 |
| 1871 | {DBGFIELD(/*NullALU_WriteDouble_WriteSALUDummy*/ 536) 1, false, false, false, 0, 24, 39, 0, 3, 2}, // #25 |
| 1872 | {DBGFIELD(/*NullALU_WriteIntMul_WriteSALUDummy*/ 571) 1, false, false, false, 0, 24, 21, 0, 3, 2}, // #26 |
| 1873 | {DBGFIELD(/*NullALU_WriteIntMul*/ 606) 1, false, false, false, 0, 3, 21, 0, 2, 1}, // #27 |
| 1874 | {DBGFIELD(/*NullALU_WriteQuarterRate32*/ 626) 1, false, false, false, 0, 3, 14, 0, 2, 1}, // #28 |
| 1875 | {DBGFIELD(/*NullALU_Write32Bit_WriteVALUDummy*/ 653) 1, false, false, false, 0, 27, 2, 0, 2, 2}, // #29 |
| 1876 | {DBGFIELD(/*NullALU_WriteTrans64*/ 687) 1, false, false, false, 0, 29, 32, 0, 3, 1}, // #30 |
| 1877 | {DBGFIELD(/*NullALU_Write64Bit_Write64Bit*/ 708) 2, false, false, false, 0, 5, 24, 0, 2, 2}, // #31 |
| 1878 | {DBGFIELD(/*NullALU_WritePseudoScalarTrans*/ 738) 1, false, false, false, 0, 3, 21, 0, 2, 1}, // #32 |
| 1879 | {DBGFIELD(/*NullALU_WriteVMEM_WriteVMEM_WriteVMEM*/ 769) 3, false, false, false, 0, 32, 26, 0, 2, 3}, // #33 |
| 1880 | {DBGFIELD(/*NullALU_WriteDoubleAdd_Write32Bit*/ 807) 2, false, false, false, 0, 5, 41, 0, 2, 2}, // #34 |
| 1881 | {DBGFIELD(/*COPY*/ 841) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #35 |
| 1882 | {DBGFIELD(/*V_ACCVGPR_WRITE_B32_e64*/ 846) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #36 |
| 1883 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 870) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #37 |
| 1884 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 1996) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #38 |
| 1885 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 7379) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #39 |
| 1886 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 14259) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #40 |
| 1887 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 15206) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #41 |
| 1888 | {DBGFIELD(/*V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd*/ 20331) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #42 |
| 1889 | {DBGFIELD(/*V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi*/ 20460) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #43 |
| 1890 | {DBGFIELD(/*V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd*/ 21054) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #44 |
| 1891 | {DBGFIELD(/*V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi*/ 22045) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #45 |
| 1892 | {DBGFIELD(/*V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd*/ 23391) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #46 |
| 1893 | {DBGFIELD(/*V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 23589) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #47 |
| 1894 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd*/ 24372) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #48 |
| 1895 | {DBGFIELD(/*V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi*/ 25890) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #49 |
| 1896 | {DBGFIELD(/*V_SMFMAC_F32_16X16X128_BF8_BF8_e64_V_SMFMAC_F32_16X16X128_BF8_FP8_e64_V_SMFMAC_F32_16X16X128_FP8_BF8_e64_V_SMFMAC_F32_16X16X128_FP8_FP8_e64_V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_F16_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X128_I8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_F16_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X128_I8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940*/ 27751) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #50 |
| 1897 | {DBGFIELD(/*V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_F16_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_F32_32X32X64_BF8_BF8_e64_V_SMFMAC_F32_32X32X64_BF8_FP8_e64_V_SMFMAC_F32_32X32X64_FP8_BF8_e64_V_SMFMAC_F32_32X32X64_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_I32_32X32X64_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_F16_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940_V_SMFMAC_I32_32X32X64_I8_gfx940*/ 28707) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #51 |
| 1898 | {DBGFIELD(/*V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 29653) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #52 |
| 1899 | {DBGFIELD(/*V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd*/ 29782) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #53 |
| 1900 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 29980) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #54 |
| 1901 | {DBGFIELD(/*V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 31537) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #55 |
| 1902 | {DBGFIELD(/*V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd*/ 33310) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #56 |
| 1903 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_threeaddr*/ 35956) 1, false, false, false, 0, 4, 10, 0, 1, 1}, // #57 |
| 1904 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_twoaddr_V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250*/ 35993) 1, false, false, false, 0, 4, 10, 0, 1, 1}, // #58 |
| 1905 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr*/ 36071) 1, false, false, false, 0, 51, 31, 0, 1, 1}, // #59 |
| 1906 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250*/ 36407) 1, false, false, false, 0, 51, 31, 0, 1, 1}, // #60 |
| 1907 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X16_F16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_V_WMMA_F32_16X16X16_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 37111) 1, false, false, false, 0, 52, 21, 0, 1, 1}, // #61 |
| 1908 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X16_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X16_F16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X16_BF16_w32_threeaddr_V_WMMA_F32_16X16X16_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 38981) 1, false, false, false, 0, 52, 21, 0, 1, 1}, // #62 |
| 1909 | {DBGFIELD(/*V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 39334) 1, false, false, false, 0, 52, 21, 0, 1, 1}, // #63 |
| 1910 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr*/ 40806) 1, false, false, false, 0, 52, 21, 0, 1, 1}, // #64 |
| 1911 | {DBGFIELD(/*V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250*/ 41150) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #65 |
| 1912 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_w32_threeaddr_V_WMMA_I32_16X16X16_IU8_w32_threeaddr_V_WMMA_I32_16X16X32_IU4_w32_threeaddr_V_WMMA_I32_16X16X64_IU8_w32_threeaddr*/ 42066) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #66 |
| 1913 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr*/ 42218) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #67 |
| 1914 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250*/ 43640) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #68 |
| 1915 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr*/ 46448) 1, false, false, false, 0, 52, 21, 0, 1, 1}, // #69 |
| 1916 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr_V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250_V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250*/ 46576) 1, false, false, false, 0, 52, 21, 0, 1, 1}, // #70 |
| 1917 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 46828) 1, false, false, false, 0, 52, 21, 0, 1, 1}, // #71 |
| 1918 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 47548) 1, false, false, false, 0, 52, 21, 0, 1, 1}, // #72 |
| 1919 | {DBGFIELD(/*V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12*/ 48921) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #73 |
| 1920 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 49481) 1, false, false, false, 0, 52, 21, 0, 1, 1}, // #74 |
| 1921 | {DBGFIELD(/*V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12*/ 49679) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #75 |
| 1922 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_threeaddr_w32_V_WMMA_I32_16X16X16_IU4_threeaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_threeaddr_V_WMMA_I32_16X16X16_IU8_threeaddr_w32_V_WMMA_I32_16X16X16_IU8_threeaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_threeaddr_V_WMMA_I32_16X16X32_IU4_w64_threeaddr*/ 50741) 2, false, false, false, 0, 5, 2, 0, 2, 2}, // #76 |
| 1923 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_threeaddr*/ 51007) 2, false, false, false, 0, 5, 2, 0, 2, 2}, // #77 |
| 1924 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_twoaddr_V_WMMA_F64_16X16X4_F64_w32_twoaddr_gfx1250*/ 51044) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #78 |
| 1925 | {DBGFIELD(/*Write32Bit*/ 51122) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #79 |
| 1926 | {DBGFIELD(/*Write64Bit*/ 51133) 1, false, false, false, 0, 3, 14, 0, 2, 1}, // #80 |
| 1927 | {DBGFIELD(/*WriteSALU*/ 51144) 1, false, false, false, 0, 1, 1, 0, 2, 1}, // #81 |
| 1928 | {DBGFIELD(/*Write64Bit_MIVGPRRead*/ 51154) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #82 |
| 1929 | {DBGFIELD(/*Write64Bit_ReadDefault*/ 51176) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #83 |
| 1930 | {DBGFIELD(/*Write16PassMAI_MIMFMARead*/ 51199) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #84 |
| 1931 | {DBGFIELD(/*Write8PassMAI_MIMFMARead*/ 51225) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #85 |
| 1932 | {DBGFIELD(/*Write4PassMAI_MIMFMARead*/ 51250) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #86 |
| 1933 | {DBGFIELD(/*WriteXDL2PassWMMA*/ 51275) 1, false, false, false, 0, 52, 21, 0, 1, 1}, // #87 |
| 1934 | {DBGFIELD(/*WriteXDL1PassWMMA*/ 51293) 1, false, false, false, 0, 51, 31, 0, 1, 1}, // #88 |
| 1935 | {DBGFIELD(/*WriteXDL4PassWMMA*/ 51311) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #89 |
| 1936 | {DBGFIELD(/*WriteXDL8PassWMMA*/ 51329) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #90 |
| 1937 | }; // GFX1250SpeedModelSchedClasses |
| 1938 | |
| 1939 | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, ReadAdvanceIdx, WriteProcResIdx, WriteLatencyIdx, NumReadAdvanceEntries, NumWriteProcResEntries, NumWriteLatencyEntries} |
| 1940 | static const llvm::MCSchedClassDesc GFX1251SpeedModelSchedClasses[] = { |
| 1941 | {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
| 1942 | {DBGFIELD(/*NullALU_WriteSALU*/ 19) 1, false, false, false, 0, 1, 1, 0, 2, 1}, // #1 |
| 1943 | {DBGFIELD(/*NullALU_Write32Bit*/ 37) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #2 |
| 1944 | {DBGFIELD(/*NullALU_Write32Bit_Write32Bit*/ 56) 2, false, false, false, 0, 5, 2, 0, 2, 2}, // #3 |
| 1945 | {DBGFIELD(/*NullALU_WriteVMEM*/ 86) 1, false, false, false, 0, 7, 5, 0, 2, 1}, // #4 |
| 1946 | {DBGFIELD(/*NullALU_WriteVMEM_WriteLDS*/ 104) 2, false, false, false, 0, 9, 6, 0, 3, 2}, // #5 |
| 1947 | {DBGFIELD(/*NullALU_WriteLDS*/ 131) 1, false, false, false, 0, 12, 7, 0, 2, 1}, // #6 |
| 1948 | {DBGFIELD(/*NullALU_WriteLDS_WriteLDS*/ 148) 2, false, false, false, 0, 14, 7, 0, 2, 2}, // #7 |
| 1949 | {DBGFIELD(/*NullALU_WriteExport*/ 174) 1, false, false, false, 0, 16, 10, 0, 2, 1}, // #8 |
| 1950 | {DBGFIELD(/*WriteBranch*/ 194) 1, false, false, false, 0, 18, 11, 0, 1, 1}, // #9 |
| 1951 | {DBGFIELD(/*NullALU*/ 206) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #10 |
| 1952 | {DBGFIELD(/*NullALU_WriteBranch*/ 214) 1, false, false, false, 0, 18, 11, 0, 1, 1}, // #11 |
| 1953 | {DBGFIELD(/*NullALU_WriteSFPU*/ 234) 1, false, false, false, 0, 1, 31, 0, 2, 1}, // #12 |
| 1954 | {DBGFIELD(/*NullALU_WriteSMEM*/ 252) 1, false, false, false, 0, 12, 7, 0, 2, 1}, // #13 |
| 1955 | {DBGFIELD(/*NullALU_WriteBarrier*/ 270) 1, false, false, false, 0, 18, 12, 0, 1, 1}, // #14 |
| 1956 | {DBGFIELD(/*NullALU_WriteSALU_Write64Bit*/ 291) 2, false, false, false, 0, 19, 1, 0, 3, 2}, // #15 |
| 1957 | {DBGFIELD(/*NullALU_Write32Bit_WriteSALU*/ 320) 2, false, false, false, 0, 19, 15, 0, 3, 2}, // #16 |
| 1958 | {DBGFIELD(/*NullALU_WriteDoubleAdd*/ 349) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #17 |
| 1959 | {DBGFIELD(/*NullALU_Write64Bit*/ 372) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #18 |
| 1960 | {DBGFIELD(/*NullALU_WriteTrans32*/ 391) 1, false, false, false, 0, 22, 21, 0, 2, 1}, // #19 |
| 1961 | {DBGFIELD(/*NullALU_WriteFloatCvt*/ 412) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #20 |
| 1962 | {DBGFIELD(/*NullALU_WriteDoubleCvt*/ 434) 1, false, false, false, 0, 3, 14, 0, 2, 1}, // #21 |
| 1963 | {DBGFIELD(/*NullALU_WriteFloatFMA*/ 457) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #22 |
| 1964 | {DBGFIELD(/*NullALU_WriteDouble*/ 479) 1, false, false, false, 0, 3, 14, 0, 2, 1}, // #23 |
| 1965 | {DBGFIELD(/*NullALU_WriteFloatFMA_WriteSALUDummy*/ 499) 1, false, false, false, 0, 24, 15, 0, 3, 2}, // #24 |
| 1966 | {DBGFIELD(/*NullALU_WriteDouble_WriteSALUDummy*/ 536) 1, false, false, false, 0, 24, 44, 0, 3, 2}, // #25 |
| 1967 | {DBGFIELD(/*NullALU_WriteIntMul_WriteSALUDummy*/ 571) 1, false, false, false, 0, 24, 21, 0, 3, 2}, // #26 |
| 1968 | {DBGFIELD(/*NullALU_WriteIntMul*/ 606) 1, false, false, false, 0, 3, 21, 0, 2, 1}, // #27 |
| 1969 | {DBGFIELD(/*NullALU_WriteQuarterRate32*/ 626) 1, false, false, false, 0, 3, 14, 0, 2, 1}, // #28 |
| 1970 | {DBGFIELD(/*NullALU_Write32Bit_WriteVALUDummy*/ 653) 1, false, false, false, 0, 27, 2, 0, 2, 2}, // #29 |
| 1971 | {DBGFIELD(/*NullALU_WriteTrans64*/ 687) 1, false, false, false, 0, 29, 46, 0, 3, 1}, // #30 |
| 1972 | {DBGFIELD(/*NullALU_Write64Bit_Write64Bit*/ 708) 2, false, false, false, 0, 5, 2, 0, 2, 2}, // #31 |
| 1973 | {DBGFIELD(/*NullALU_WritePseudoScalarTrans*/ 738) 1, false, false, false, 0, 3, 21, 0, 2, 1}, // #32 |
| 1974 | {DBGFIELD(/*NullALU_WriteVMEM_WriteVMEM_WriteVMEM*/ 769) 3, false, false, false, 0, 32, 26, 0, 2, 3}, // #33 |
| 1975 | {DBGFIELD(/*NullALU_WriteDoubleAdd_Write32Bit*/ 807) 2, false, false, false, 0, 5, 2, 0, 2, 2}, // #34 |
| 1976 | {DBGFIELD(/*COPY*/ 841) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #35 |
| 1977 | {DBGFIELD(/*V_ACCVGPR_WRITE_B32_e64*/ 846) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #36 |
| 1978 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 870) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #37 |
| 1979 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 1996) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #38 |
| 1980 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 7379) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #39 |
| 1981 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 14259) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #40 |
| 1982 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 15206) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #41 |
| 1983 | {DBGFIELD(/*V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd*/ 20331) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #42 |
| 1984 | {DBGFIELD(/*V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi*/ 20460) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #43 |
| 1985 | {DBGFIELD(/*V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd*/ 21054) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #44 |
| 1986 | {DBGFIELD(/*V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi*/ 22045) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #45 |
| 1987 | {DBGFIELD(/*V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd*/ 23391) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #46 |
| 1988 | {DBGFIELD(/*V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 23589) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #47 |
| 1989 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd*/ 24372) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #48 |
| 1990 | {DBGFIELD(/*V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi*/ 25890) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #49 |
| 1991 | {DBGFIELD(/*V_SMFMAC_F32_16X16X128_BF8_BF8_e64_V_SMFMAC_F32_16X16X128_BF8_FP8_e64_V_SMFMAC_F32_16X16X128_FP8_BF8_e64_V_SMFMAC_F32_16X16X128_FP8_FP8_e64_V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_F16_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X128_I8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_F16_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X128_I8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940*/ 27751) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #50 |
| 1992 | {DBGFIELD(/*V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_F16_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_F32_32X32X64_BF8_BF8_e64_V_SMFMAC_F32_32X32X64_BF8_FP8_e64_V_SMFMAC_F32_32X32X64_FP8_BF8_e64_V_SMFMAC_F32_32X32X64_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_I32_32X32X64_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_F16_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940_V_SMFMAC_I32_32X32X64_I8_gfx940*/ 28707) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #51 |
| 1993 | {DBGFIELD(/*V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 29653) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #52 |
| 1994 | {DBGFIELD(/*V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd*/ 29782) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #53 |
| 1995 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 29980) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #54 |
| 1996 | {DBGFIELD(/*V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 31537) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #55 |
| 1997 | {DBGFIELD(/*V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd*/ 33310) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #56 |
| 1998 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_threeaddr*/ 35956) 1, false, false, false, 0, 4, 10, 0, 1, 1}, // #57 |
| 1999 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_twoaddr_V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250*/ 35993) 1, false, false, false, 0, 4, 10, 0, 1, 1}, // #58 |
| 2000 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr*/ 36071) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #59 |
| 2001 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250*/ 36407) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #60 |
| 2002 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X16_F16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_V_WMMA_F32_16X16X16_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 37111) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #61 |
| 2003 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X16_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X16_F16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X16_BF16_w32_threeaddr_V_WMMA_F32_16X16X16_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 38981) 2, false, false, false, 0, 5, 2, 0, 2, 2}, // #62 |
| 2004 | {DBGFIELD(/*V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 39334) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #63 |
| 2005 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr*/ 40806) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #64 |
| 2006 | {DBGFIELD(/*V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250*/ 41150) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #65 |
| 2007 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_w32_threeaddr_V_WMMA_I32_16X16X16_IU8_w32_threeaddr_V_WMMA_I32_16X16X32_IU4_w32_threeaddr_V_WMMA_I32_16X16X64_IU8_w32_threeaddr*/ 42066) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #66 |
| 2008 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr*/ 42218) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #67 |
| 2009 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250*/ 43640) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #68 |
| 2010 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr*/ 46448) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #69 |
| 2011 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr_V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250_V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250*/ 46576) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #70 |
| 2012 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 46828) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #71 |
| 2013 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 47548) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #72 |
| 2014 | {DBGFIELD(/*V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12*/ 48921) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #73 |
| 2015 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 49481) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #74 |
| 2016 | {DBGFIELD(/*V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12*/ 49679) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #75 |
| 2017 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_threeaddr_w32_V_WMMA_I32_16X16X16_IU4_threeaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_threeaddr_V_WMMA_I32_16X16X16_IU8_threeaddr_w32_V_WMMA_I32_16X16X16_IU8_threeaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_threeaddr_V_WMMA_I32_16X16X32_IU4_w64_threeaddr*/ 50741) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #76 |
| 2018 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_threeaddr*/ 51007) 1, false, false, false, 0, 4, 10, 0, 1, 1}, // #77 |
| 2019 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_twoaddr_V_WMMA_F64_16X16X4_F64_w32_twoaddr_gfx1250*/ 51044) 1, false, false, false, 0, 4, 10, 0, 1, 1}, // #78 |
| 2020 | {DBGFIELD(/*Write32Bit*/ 51122) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #79 |
| 2021 | {DBGFIELD(/*Write64Bit*/ 51133) 1, false, false, false, 0, 3, 2, 0, 2, 1}, // #80 |
| 2022 | {DBGFIELD(/*WriteSALU*/ 51144) 1, false, false, false, 0, 1, 1, 0, 2, 1}, // #81 |
| 2023 | {DBGFIELD(/*Write64Bit_MIVGPRRead*/ 51154) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #82 |
| 2024 | {DBGFIELD(/*Write64Bit_ReadDefault*/ 51176) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #83 |
| 2025 | {DBGFIELD(/*Write16PassMAI_MIMFMARead*/ 51199) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #84 |
| 2026 | {DBGFIELD(/*Write8PassMAI_MIMFMARead*/ 51225) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #85 |
| 2027 | {DBGFIELD(/*Write4PassMAI_MIMFMARead*/ 51250) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #86 |
| 2028 | {DBGFIELD(/*WriteXDL2PassWMMA*/ 51275) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #87 |
| 2029 | {DBGFIELD(/*WriteXDL1PassWMMA*/ 51293) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #88 |
| 2030 | {DBGFIELD(/*WriteXDL4PassWMMA*/ 51311) 1, false, false, false, 0, 34, 10, 0, 1, 1}, // #89 |
| 2031 | {DBGFIELD(/*WriteXDL8PassWMMA*/ 51329) 1, false, false, false, 0, 35, 11, 0, 1, 1}, // #90 |
| 2032 | }; // GFX1251SpeedModelSchedClasses |
| 2033 | |
| 2034 | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, ReadAdvanceIdx, WriteProcResIdx, WriteLatencyIdx, NumReadAdvanceEntries, NumWriteProcResEntries, NumWriteLatencyEntries} |
| 2035 | static const llvm::MCSchedClassDesc SIFullSpeedModelSchedClasses[] = { |
| 2036 | {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
| 2037 | {DBGFIELD(/*NullALU_WriteSALU*/ 19) 1, false, false, true, 0, 1, 47, 0, 1, 1}, // #1 |
| 2038 | {DBGFIELD(/*NullALU_Write32Bit*/ 37) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #2 |
| 2039 | {DBGFIELD(/*NullALU_Write32Bit_Write32Bit*/ 56) 2, false, false, true, 0, 53, 48, 0, 1, 2}, // #3 |
| 2040 | {DBGFIELD(/*NullALU_WriteVMEM*/ 86) 1, false, false, true, 0, 23, 50, 0, 1, 1}, // #4 |
| 2041 | {DBGFIELD(/*NullALU_WriteVMEM_WriteLDS*/ 104) 2, false, false, true, 0, 54, 51, 0, 2, 2}, // #5 |
| 2042 | {DBGFIELD(/*NullALU_WriteLDS*/ 131) 1, false, false, true, 0, 9, 2, 0, 1, 1}, // #6 |
| 2043 | {DBGFIELD(/*NullALU_WriteLDS_WriteLDS*/ 148) 2, false, false, true, 0, 14, 2, 0, 1, 2}, // #7 |
| 2044 | {DBGFIELD(/*NullALU_WriteExport*/ 174) 1, false, false, true, 0, 16, 31, 0, 1, 1}, // #8 |
| 2045 | {DBGFIELD(/*WriteBranch*/ 194) 1, false, false, true, 0, 18, 21, 0, 1, 1}, // #9 |
| 2046 | {DBGFIELD(/*NullALU*/ 206) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #10 |
| 2047 | {DBGFIELD(/*NullALU_WriteBranch*/ 214) 1, false, false, true, 0, 18, 21, 0, 1, 1}, // #11 |
| 2048 | {DBGFIELD(/*NullALU_WriteSFPU*/ 234) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #12 |
| 2049 | {DBGFIELD(/*NullALU_WriteSMEM*/ 252) 1, false, false, true, 0, 9, 2, 0, 1, 1}, // #13 |
| 2050 | {DBGFIELD(/*NullALU_WriteBarrier*/ 270) 1, false, false, true, 0, 18, 53, 0, 1, 1}, // #14 |
| 2051 | {DBGFIELD(/*NullALU_WriteSALU_Write64Bit*/ 291) 2, false, false, true, 0, 1, 54, 0, 2, 2}, // #15 |
| 2052 | {DBGFIELD(/*NullALU_Write32Bit_WriteSALU*/ 320) 2, false, false, true, 0, 1, 47, 0, 2, 2}, // #16 |
| 2053 | {DBGFIELD(/*NullALU_WriteDoubleAdd*/ 349) 1, false, false, true, 0, 2, 1, 0, 1, 1}, // #17 |
| 2054 | {DBGFIELD(/*NullALU_Write64Bit*/ 372) 1, false, false, true, 0, 2, 1, 0, 1, 1}, // #18 |
| 2055 | {DBGFIELD(/*NullALU_WriteTrans32*/ 391) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #19 |
| 2056 | {DBGFIELD(/*NullALU_WriteFloatCvt*/ 412) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #20 |
| 2057 | {DBGFIELD(/*NullALU_WriteDoubleCvt*/ 434) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #21 |
| 2058 | {DBGFIELD(/*NullALU_WriteFloatFMA*/ 457) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #22 |
| 2059 | {DBGFIELD(/*NullALU_WriteDouble*/ 479) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #23 |
| 2060 | {DBGFIELD(/*NullALU_WriteFloatFMA_WriteSALUDummy*/ 499) 1, false, false, true, 0, 1, 47, 0, 2, 2}, // #24 |
| 2061 | {DBGFIELD(/*NullALU_WriteDouble_WriteSALUDummy*/ 536) 1, false, false, true, 0, 1, 56, 0, 2, 2}, // #25 |
| 2062 | {DBGFIELD(/*NullALU_WriteIntMul_WriteSALUDummy*/ 571) 1, false, false, true, 0, 1, 56, 0, 2, 2}, // #26 |
| 2063 | {DBGFIELD(/*NullALU_WriteIntMul*/ 606) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #27 |
| 2064 | {DBGFIELD(/*NullALU_WriteQuarterRate32*/ 626) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #28 |
| 2065 | {DBGFIELD(/*NullALU_Write32Bit_WriteVALUDummy*/ 653) 1, false, false, true, 0, 53, 47, 0, 1, 2}, // #29 |
| 2066 | {DBGFIELD(/*NullALU_WriteTrans64*/ 687) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #30 |
| 2067 | {DBGFIELD(/*NullALU_Write64Bit_Write64Bit*/ 708) 2, false, false, true, 0, 53, 58, 0, 1, 2}, // #31 |
| 2068 | {DBGFIELD(/*NullALU_WritePseudoScalarTrans*/ 738) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
| 2069 | {DBGFIELD(/*NullALU_WriteVMEM_WriteVMEM_WriteVMEM*/ 769) 3, false, false, true, 0, 56, 60, 0, 1, 3}, // #33 |
| 2070 | {DBGFIELD(/*NullALU_WriteDoubleAdd_Write32Bit*/ 807) 2, false, false, true, 0, 53, 63, 0, 1, 2}, // #34 |
| 2071 | {DBGFIELD(/*COPY*/ 841) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #35 |
| 2072 | {DBGFIELD(/*V_ACCVGPR_WRITE_B32_e64*/ 846) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #36 |
| 2073 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 870) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #37 |
| 2074 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 1996) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #38 |
| 2075 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 7379) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #39 |
| 2076 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 14259) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #40 |
| 2077 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 15206) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #41 |
| 2078 | {DBGFIELD(/*V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd*/ 20331) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #42 |
| 2079 | {DBGFIELD(/*V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi*/ 20460) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #43 |
| 2080 | {DBGFIELD(/*V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd*/ 21054) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #44 |
| 2081 | {DBGFIELD(/*V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi*/ 22045) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #45 |
| 2082 | {DBGFIELD(/*V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd*/ 23391) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #46 |
| 2083 | {DBGFIELD(/*V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 23589) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #47 |
| 2084 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd*/ 24372) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #48 |
| 2085 | {DBGFIELD(/*V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi*/ 25890) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #49 |
| 2086 | {DBGFIELD(/*V_SMFMAC_F32_16X16X128_BF8_BF8_e64_V_SMFMAC_F32_16X16X128_BF8_FP8_e64_V_SMFMAC_F32_16X16X128_FP8_BF8_e64_V_SMFMAC_F32_16X16X128_FP8_FP8_e64_V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_F16_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X128_I8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_F16_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X128_I8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940*/ 27751) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #50 |
| 2087 | {DBGFIELD(/*V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_F16_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_F32_32X32X64_BF8_BF8_e64_V_SMFMAC_F32_32X32X64_BF8_FP8_e64_V_SMFMAC_F32_32X32X64_FP8_BF8_e64_V_SMFMAC_F32_32X32X64_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_I32_32X32X64_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_F16_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940_V_SMFMAC_I32_32X32X64_I8_gfx940*/ 28707) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #51 |
| 2088 | {DBGFIELD(/*V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 29653) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #52 |
| 2089 | {DBGFIELD(/*V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd*/ 29782) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #53 |
| 2090 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 29980) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #54 |
| 2091 | {DBGFIELD(/*V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 31537) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #55 |
| 2092 | {DBGFIELD(/*V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd*/ 33310) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #56 |
| 2093 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_threeaddr*/ 35956) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #57 |
| 2094 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_twoaddr_V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250*/ 35993) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #58 |
| 2095 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr*/ 36071) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #59 |
| 2096 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250*/ 36407) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #60 |
| 2097 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X16_F16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_V_WMMA_F32_16X16X16_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 37111) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #61 |
| 2098 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X16_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X16_F16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X16_BF16_w32_threeaddr_V_WMMA_F32_16X16X16_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 38981) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #62 |
| 2099 | {DBGFIELD(/*V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 39334) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #63 |
| 2100 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr*/ 40806) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #64 |
| 2101 | {DBGFIELD(/*V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250*/ 41150) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #65 |
| 2102 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_w32_threeaddr_V_WMMA_I32_16X16X16_IU8_w32_threeaddr_V_WMMA_I32_16X16X32_IU4_w32_threeaddr_V_WMMA_I32_16X16X64_IU8_w32_threeaddr*/ 42066) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #66 |
| 2103 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr*/ 42218) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #67 |
| 2104 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250*/ 43640) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #68 |
| 2105 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr*/ 46448) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #69 |
| 2106 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr_V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250_V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250*/ 46576) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #70 |
| 2107 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 46828) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #71 |
| 2108 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 47548) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #72 |
| 2109 | {DBGFIELD(/*V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12*/ 48921) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #73 |
| 2110 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 49481) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #74 |
| 2111 | {DBGFIELD(/*V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12*/ 49679) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #75 |
| 2112 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_threeaddr_w32_V_WMMA_I32_16X16X16_IU4_threeaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_threeaddr_V_WMMA_I32_16X16X16_IU8_threeaddr_w32_V_WMMA_I32_16X16X16_IU8_threeaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_threeaddr_V_WMMA_I32_16X16X32_IU4_w64_threeaddr*/ 50741) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #76 |
| 2113 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_threeaddr*/ 51007) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #77 |
| 2114 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_twoaddr_V_WMMA_F64_16X16X4_F64_w32_twoaddr_gfx1250*/ 51044) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #78 |
| 2115 | {DBGFIELD(/*Write32Bit*/ 51122) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #79 |
| 2116 | {DBGFIELD(/*Write64Bit*/ 51133) 1, false, false, true, 0, 2, 1, 0, 1, 1}, // #80 |
| 2117 | {DBGFIELD(/*WriteSALU*/ 51144) 1, false, false, true, 0, 1, 47, 0, 1, 1}, // #81 |
| 2118 | {DBGFIELD(/*Write64Bit_MIVGPRRead*/ 51154) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #82 |
| 2119 | {DBGFIELD(/*Write64Bit_ReadDefault*/ 51176) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #83 |
| 2120 | {DBGFIELD(/*Write16PassMAI_MIMFMARead*/ 51199) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #84 |
| 2121 | {DBGFIELD(/*Write8PassMAI_MIMFMARead*/ 51225) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #85 |
| 2122 | {DBGFIELD(/*Write4PassMAI_MIMFMARead*/ 51250) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #86 |
| 2123 | {DBGFIELD(/*WriteXDL2PassWMMA*/ 51275) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #87 |
| 2124 | {DBGFIELD(/*WriteXDL1PassWMMA*/ 51293) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #88 |
| 2125 | {DBGFIELD(/*WriteXDL4PassWMMA*/ 51311) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #89 |
| 2126 | {DBGFIELD(/*WriteXDL8PassWMMA*/ 51329) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #90 |
| 2127 | }; // SIFullSpeedModelSchedClasses |
| 2128 | |
| 2129 | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, ReadAdvanceIdx, WriteProcResIdx, WriteLatencyIdx, NumReadAdvanceEntries, NumWriteProcResEntries, NumWriteLatencyEntries} |
| 2130 | static const llvm::MCSchedClassDesc SIQuarterSpeedModelSchedClasses[] = { |
| 2131 | {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
| 2132 | {DBGFIELD(/*NullALU_WriteSALU*/ 19) 1, false, false, true, 0, 1, 47, 0, 1, 1}, // #1 |
| 2133 | {DBGFIELD(/*NullALU_Write32Bit*/ 37) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #2 |
| 2134 | {DBGFIELD(/*NullALU_Write32Bit_Write32Bit*/ 56) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #3 |
| 2135 | {DBGFIELD(/*NullALU_WriteVMEM*/ 86) 1, false, false, true, 0, 23, 50, 0, 1, 1}, // #4 |
| 2136 | {DBGFIELD(/*NullALU_WriteVMEM_WriteLDS*/ 104) 2, false, false, true, 0, 54, 51, 0, 2, 2}, // #5 |
| 2137 | {DBGFIELD(/*NullALU_WriteLDS*/ 131) 1, false, false, true, 0, 9, 2, 0, 1, 1}, // #6 |
| 2138 | {DBGFIELD(/*NullALU_WriteLDS_WriteLDS*/ 148) 2, false, false, true, 0, 14, 2, 0, 1, 2}, // #7 |
| 2139 | {DBGFIELD(/*NullALU_WriteExport*/ 174) 1, false, false, true, 0, 16, 31, 0, 1, 1}, // #8 |
| 2140 | {DBGFIELD(/*WriteBranch*/ 194) 1, false, false, true, 0, 18, 21, 0, 1, 1}, // #9 |
| 2141 | {DBGFIELD(/*NullALU*/ 206) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #10 |
| 2142 | {DBGFIELD(/*NullALU_WriteBranch*/ 214) 1, false, false, true, 0, 18, 21, 0, 1, 1}, // #11 |
| 2143 | {DBGFIELD(/*NullALU_WriteSFPU*/ 234) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #12 |
| 2144 | {DBGFIELD(/*NullALU_WriteSMEM*/ 252) 1, false, false, true, 0, 9, 2, 0, 1, 1}, // #13 |
| 2145 | {DBGFIELD(/*NullALU_WriteBarrier*/ 270) 1, false, false, true, 0, 18, 53, 0, 1, 1}, // #14 |
| 2146 | {DBGFIELD(/*NullALU_WriteSALU_Write64Bit*/ 291) 2, false, false, true, 0, 1, 54, 0, 2, 2}, // #15 |
| 2147 | {DBGFIELD(/*NullALU_Write32Bit_WriteSALU*/ 320) 2, false, false, true, 0, 1, 47, 0, 2, 2}, // #16 |
| 2148 | {DBGFIELD(/*NullALU_WriteDoubleAdd*/ 349) 1, false, false, true, 0, 2, 21, 0, 1, 1}, // #17 |
| 2149 | {DBGFIELD(/*NullALU_Write64Bit*/ 372) 1, false, false, true, 0, 2, 1, 0, 1, 1}, // #18 |
| 2150 | {DBGFIELD(/*NullALU_WriteTrans32*/ 391) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #19 |
| 2151 | {DBGFIELD(/*NullALU_WriteFloatCvt*/ 412) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #20 |
| 2152 | {DBGFIELD(/*NullALU_WriteDoubleCvt*/ 434) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #21 |
| 2153 | {DBGFIELD(/*NullALU_WriteFloatFMA*/ 457) 1, false, false, true, 0, 2, 10, 0, 1, 1}, // #22 |
| 2154 | {DBGFIELD(/*NullALU_WriteDouble*/ 479) 1, false, false, true, 0, 2, 10, 0, 1, 1}, // #23 |
| 2155 | {DBGFIELD(/*NullALU_WriteFloatFMA_WriteSALUDummy*/ 499) 1, false, false, true, 0, 1, 65, 0, 2, 2}, // #24 |
| 2156 | {DBGFIELD(/*NullALU_WriteDouble_WriteSALUDummy*/ 536) 1, false, false, true, 0, 1, 65, 0, 2, 2}, // #25 |
| 2157 | {DBGFIELD(/*NullALU_WriteIntMul_WriteSALUDummy*/ 571) 1, false, false, true, 0, 1, 56, 0, 2, 2}, // #26 |
| 2158 | {DBGFIELD(/*NullALU_WriteIntMul*/ 606) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #27 |
| 2159 | {DBGFIELD(/*NullALU_WriteQuarterRate32*/ 626) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #28 |
| 2160 | {DBGFIELD(/*NullALU_Write32Bit_WriteVALUDummy*/ 653) 1, false, false, true, 0, 53, 47, 0, 1, 2}, // #29 |
| 2161 | {DBGFIELD(/*NullALU_WriteTrans64*/ 687) 1, false, false, true, 0, 2, 10, 0, 1, 1}, // #30 |
| 2162 | {DBGFIELD(/*NullALU_Write64Bit_Write64Bit*/ 708) 2, false, false, true, 0, 53, 58, 0, 1, 2}, // #31 |
| 2163 | {DBGFIELD(/*NullALU_WritePseudoScalarTrans*/ 738) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
| 2164 | {DBGFIELD(/*NullALU_WriteVMEM_WriteVMEM_WriteVMEM*/ 769) 3, false, false, true, 0, 56, 60, 0, 1, 3}, // #33 |
| 2165 | {DBGFIELD(/*NullALU_WriteDoubleAdd_Write32Bit*/ 807) 2, false, false, true, 0, 53, 67, 0, 1, 2}, // #34 |
| 2166 | {DBGFIELD(/*COPY*/ 841) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #35 |
| 2167 | {DBGFIELD(/*V_ACCVGPR_WRITE_B32_e64*/ 846) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #36 |
| 2168 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 870) 1, false, false, true, 1, 6, 1, 1, 1, 1}, // #37 |
| 2169 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 1996) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #38 |
| 2170 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 7379) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #39 |
| 2171 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 14259) 1, false, false, true, 1, 6, 1, 1, 1, 1}, // #40 |
| 2172 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 15206) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #41 |
| 2173 | {DBGFIELD(/*V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd*/ 20331) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #42 |
| 2174 | {DBGFIELD(/*V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi*/ 20460) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #43 |
| 2175 | {DBGFIELD(/*V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd*/ 21054) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #44 |
| 2176 | {DBGFIELD(/*V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi*/ 22045) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #45 |
| 2177 | {DBGFIELD(/*V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd*/ 23391) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #46 |
| 2178 | {DBGFIELD(/*V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 23589) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #47 |
| 2179 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd*/ 24372) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #48 |
| 2180 | {DBGFIELD(/*V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi*/ 25890) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #49 |
| 2181 | {DBGFIELD(/*V_SMFMAC_F32_16X16X128_BF8_BF8_e64_V_SMFMAC_F32_16X16X128_BF8_FP8_e64_V_SMFMAC_F32_16X16X128_FP8_BF8_e64_V_SMFMAC_F32_16X16X128_FP8_FP8_e64_V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_F16_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X128_I8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_F16_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X128_I8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940*/ 27751) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #50 |
| 2182 | {DBGFIELD(/*V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_F16_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_F32_32X32X64_BF8_BF8_e64_V_SMFMAC_F32_32X32X64_BF8_FP8_e64_V_SMFMAC_F32_32X32X64_FP8_BF8_e64_V_SMFMAC_F32_32X32X64_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_I32_32X32X64_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_F16_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940_V_SMFMAC_I32_32X32X64_I8_gfx940*/ 28707) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #51 |
| 2183 | {DBGFIELD(/*V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 29653) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #52 |
| 2184 | {DBGFIELD(/*V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd*/ 29782) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #53 |
| 2185 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 29980) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #54 |
| 2186 | {DBGFIELD(/*V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 31537) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #55 |
| 2187 | {DBGFIELD(/*V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd*/ 33310) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #56 |
| 2188 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_threeaddr*/ 35956) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #57 |
| 2189 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_twoaddr_V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250*/ 35993) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #58 |
| 2190 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr*/ 36071) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #59 |
| 2191 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250*/ 36407) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #60 |
| 2192 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X16_F16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_V_WMMA_F32_16X16X16_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 37111) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #61 |
| 2193 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X16_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X16_F16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X16_BF16_w32_threeaddr_V_WMMA_F32_16X16X16_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 38981) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #62 |
| 2194 | {DBGFIELD(/*V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 39334) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #63 |
| 2195 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr*/ 40806) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #64 |
| 2196 | {DBGFIELD(/*V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250*/ 41150) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #65 |
| 2197 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_w32_threeaddr_V_WMMA_I32_16X16X16_IU8_w32_threeaddr_V_WMMA_I32_16X16X32_IU4_w32_threeaddr_V_WMMA_I32_16X16X64_IU8_w32_threeaddr*/ 42066) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #66 |
| 2198 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr*/ 42218) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #67 |
| 2199 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250*/ 43640) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #68 |
| 2200 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr*/ 46448) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #69 |
| 2201 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr_V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250_V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250*/ 46576) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #70 |
| 2202 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 46828) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #71 |
| 2203 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 47548) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #72 |
| 2204 | {DBGFIELD(/*V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12*/ 48921) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #73 |
| 2205 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 49481) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #74 |
| 2206 | {DBGFIELD(/*V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12*/ 49679) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #75 |
| 2207 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_threeaddr_w32_V_WMMA_I32_16X16X16_IU4_threeaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_threeaddr_V_WMMA_I32_16X16X16_IU8_threeaddr_w32_V_WMMA_I32_16X16X16_IU8_threeaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_threeaddr_V_WMMA_I32_16X16X32_IU4_w64_threeaddr*/ 50741) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #76 |
| 2208 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_threeaddr*/ 51007) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #77 |
| 2209 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_twoaddr_V_WMMA_F64_16X16X4_F64_w32_twoaddr_gfx1250*/ 51044) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #78 |
| 2210 | {DBGFIELD(/*Write32Bit*/ 51122) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #79 |
| 2211 | {DBGFIELD(/*Write64Bit*/ 51133) 1, false, false, true, 0, 2, 1, 0, 1, 1}, // #80 |
| 2212 | {DBGFIELD(/*WriteSALU*/ 51144) 1, false, false, true, 0, 1, 47, 0, 1, 1}, // #81 |
| 2213 | {DBGFIELD(/*Write64Bit_MIVGPRRead*/ 51154) 1, false, false, true, 2, 2, 1, 1, 1, 1}, // #82 |
| 2214 | {DBGFIELD(/*Write64Bit_ReadDefault*/ 51176) 1, false, false, true, 0, 2, 1, 0, 1, 1}, // #83 |
| 2215 | {DBGFIELD(/*Write16PassMAI_MIMFMARead*/ 51199) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #84 |
| 2216 | {DBGFIELD(/*Write8PassMAI_MIMFMARead*/ 51225) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #85 |
| 2217 | {DBGFIELD(/*Write4PassMAI_MIMFMARead*/ 51250) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #86 |
| 2218 | {DBGFIELD(/*WriteXDL2PassWMMA*/ 51275) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #87 |
| 2219 | {DBGFIELD(/*WriteXDL1PassWMMA*/ 51293) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #88 |
| 2220 | {DBGFIELD(/*WriteXDL4PassWMMA*/ 51311) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #89 |
| 2221 | {DBGFIELD(/*WriteXDL8PassWMMA*/ 51329) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #90 |
| 2222 | }; // SIQuarterSpeedModelSchedClasses |
| 2223 | |
| 2224 | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, ReadAdvanceIdx, WriteProcResIdx, WriteLatencyIdx, NumReadAdvanceEntries, NumWriteProcResEntries, NumWriteLatencyEntries} |
| 2225 | static const llvm::MCSchedClassDesc SIDPGFX942FullSpeedModelSchedClasses[] = { |
| 2226 | {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
| 2227 | {DBGFIELD(/*NullALU_WriteSALU*/ 19) 1, false, false, true, 0, 1, 47, 0, 1, 1}, // #1 |
| 2228 | {DBGFIELD(/*NullALU_Write32Bit*/ 37) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #2 |
| 2229 | {DBGFIELD(/*NullALU_Write32Bit_Write32Bit*/ 56) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #3 |
| 2230 | {DBGFIELD(/*NullALU_WriteVMEM*/ 86) 1, false, false, true, 0, 23, 50, 0, 1, 1}, // #4 |
| 2231 | {DBGFIELD(/*NullALU_WriteVMEM_WriteLDS*/ 104) 2, false, false, true, 0, 54, 51, 0, 2, 2}, // #5 |
| 2232 | {DBGFIELD(/*NullALU_WriteLDS*/ 131) 1, false, false, true, 0, 9, 2, 0, 1, 1}, // #6 |
| 2233 | {DBGFIELD(/*NullALU_WriteLDS_WriteLDS*/ 148) 2, false, false, true, 0, 14, 2, 0, 1, 2}, // #7 |
| 2234 | {DBGFIELD(/*NullALU_WriteExport*/ 174) 1, false, false, true, 0, 16, 31, 0, 1, 1}, // #8 |
| 2235 | {DBGFIELD(/*WriteBranch*/ 194) 1, false, false, true, 0, 18, 21, 0, 1, 1}, // #9 |
| 2236 | {DBGFIELD(/*NullALU*/ 206) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #10 |
| 2237 | {DBGFIELD(/*NullALU_WriteBranch*/ 214) 1, false, false, true, 0, 18, 21, 0, 1, 1}, // #11 |
| 2238 | {DBGFIELD(/*NullALU_WriteSFPU*/ 234) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #12 |
| 2239 | {DBGFIELD(/*NullALU_WriteSMEM*/ 252) 1, false, false, true, 0, 9, 2, 0, 1, 1}, // #13 |
| 2240 | {DBGFIELD(/*NullALU_WriteBarrier*/ 270) 1, false, false, true, 0, 18, 53, 0, 1, 1}, // #14 |
| 2241 | {DBGFIELD(/*NullALU_WriteSALU_Write64Bit*/ 291) 2, false, false, true, 0, 1, 47, 0, 2, 2}, // #15 |
| 2242 | {DBGFIELD(/*NullALU_Write32Bit_WriteSALU*/ 320) 2, false, false, true, 0, 1, 47, 0, 2, 2}, // #16 |
| 2243 | {DBGFIELD(/*NullALU_WriteDoubleAdd*/ 349) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #17 |
| 2244 | {DBGFIELD(/*NullALU_Write64Bit*/ 372) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #18 |
| 2245 | {DBGFIELD(/*NullALU_WriteTrans32*/ 391) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #19 |
| 2246 | {DBGFIELD(/*NullALU_WriteFloatCvt*/ 412) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #20 |
| 2247 | {DBGFIELD(/*NullALU_WriteDoubleCvt*/ 434) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #21 |
| 2248 | {DBGFIELD(/*NullALU_WriteFloatFMA*/ 457) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #22 |
| 2249 | {DBGFIELD(/*NullALU_WriteDouble*/ 479) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #23 |
| 2250 | {DBGFIELD(/*NullALU_WriteFloatFMA_WriteSALUDummy*/ 499) 1, false, false, true, 0, 1, 47, 0, 2, 2}, // #24 |
| 2251 | {DBGFIELD(/*NullALU_WriteDouble_WriteSALUDummy*/ 536) 1, false, false, true, 0, 1, 47, 0, 2, 2}, // #25 |
| 2252 | {DBGFIELD(/*NullALU_WriteIntMul_WriteSALUDummy*/ 571) 1, false, false, true, 0, 1, 47, 0, 2, 2}, // #26 |
| 2253 | {DBGFIELD(/*NullALU_WriteIntMul*/ 606) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #27 |
| 2254 | {DBGFIELD(/*NullALU_WriteQuarterRate32*/ 626) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #28 |
| 2255 | {DBGFIELD(/*NullALU_Write32Bit_WriteVALUDummy*/ 653) 1, false, false, true, 0, 53, 47, 0, 1, 2}, // #29 |
| 2256 | {DBGFIELD(/*NullALU_WriteTrans64*/ 687) 1, false, false, false, 0, 2, 31, 0, 1, 1}, // #30 |
| 2257 | {DBGFIELD(/*NullALU_Write64Bit_Write64Bit*/ 708) 2, false, false, false, 0, 53, 47, 0, 1, 2}, // #31 |
| 2258 | {DBGFIELD(/*NullALU_WritePseudoScalarTrans*/ 738) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
| 2259 | {DBGFIELD(/*NullALU_WriteVMEM_WriteVMEM_WriteVMEM*/ 769) 3, false, false, true, 0, 56, 60, 0, 1, 3}, // #33 |
| 2260 | {DBGFIELD(/*NullALU_WriteDoubleAdd_Write32Bit*/ 807) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #34 |
| 2261 | {DBGFIELD(/*COPY*/ 841) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #35 |
| 2262 | {DBGFIELD(/*V_ACCVGPR_WRITE_B32_e64*/ 846) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #36 |
| 2263 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 870) 1, false, false, true, 1, 59, 31, 1, 1, 1}, // #37 |
| 2264 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 1996) 1, false, false, true, 1, 60, 21, 1, 1, 1}, // #38 |
| 2265 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 7379) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #39 |
| 2266 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 14259) 1, false, false, true, 1, 6, 1, 1, 1, 1}, // #40 |
| 2267 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 15206) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #41 |
| 2268 | {DBGFIELD(/*V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd*/ 20331) 1, false, false, true, 1, 61, 31, 1, 1, 1}, // #42 |
| 2269 | {DBGFIELD(/*V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi*/ 20460) 1, false, false, true, 1, 61, 31, 1, 1, 1}, // #43 |
| 2270 | {DBGFIELD(/*V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd*/ 21054) 1, false, false, true, 1, 61, 31, 1, 1, 1}, // #44 |
| 2271 | {DBGFIELD(/*V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi*/ 22045) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #45 |
| 2272 | {DBGFIELD(/*V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd*/ 23391) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #46 |
| 2273 | {DBGFIELD(/*V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 23589) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #47 |
| 2274 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd*/ 24372) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #48 |
| 2275 | {DBGFIELD(/*V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi*/ 25890) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #49 |
| 2276 | {DBGFIELD(/*V_SMFMAC_F32_16X16X128_BF8_BF8_e64_V_SMFMAC_F32_16X16X128_BF8_FP8_e64_V_SMFMAC_F32_16X16X128_FP8_BF8_e64_V_SMFMAC_F32_16X16X128_FP8_FP8_e64_V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_F16_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X128_I8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_F16_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X128_I8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940*/ 27751) 1, false, false, true, 1, 61, 31, 1, 1, 1}, // #50 |
| 2277 | {DBGFIELD(/*V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_F16_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_F32_32X32X64_BF8_BF8_e64_V_SMFMAC_F32_32X32X64_BF8_FP8_e64_V_SMFMAC_F32_32X32X64_FP8_BF8_e64_V_SMFMAC_F32_32X32X64_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_I32_32X32X64_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_F16_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940_V_SMFMAC_I32_32X32X64_I8_gfx940*/ 28707) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #51 |
| 2278 | {DBGFIELD(/*V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 29653) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #52 |
| 2279 | {DBGFIELD(/*V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd*/ 29782) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #53 |
| 2280 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 29980) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #54 |
| 2281 | {DBGFIELD(/*V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 31537) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #55 |
| 2282 | {DBGFIELD(/*V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd*/ 33310) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #56 |
| 2283 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_threeaddr*/ 35956) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #57 |
| 2284 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_twoaddr_V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250*/ 35993) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #58 |
| 2285 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr*/ 36071) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #59 |
| 2286 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250*/ 36407) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #60 |
| 2287 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X16_F16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_V_WMMA_F32_16X16X16_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 37111) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #61 |
| 2288 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X16_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X16_F16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X16_BF16_w32_threeaddr_V_WMMA_F32_16X16X16_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 38981) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #62 |
| 2289 | {DBGFIELD(/*V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 39334) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #63 |
| 2290 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr*/ 40806) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #64 |
| 2291 | {DBGFIELD(/*V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250*/ 41150) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #65 |
| 2292 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_w32_threeaddr_V_WMMA_I32_16X16X16_IU8_w32_threeaddr_V_WMMA_I32_16X16X32_IU4_w32_threeaddr_V_WMMA_I32_16X16X64_IU8_w32_threeaddr*/ 42066) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #66 |
| 2293 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr*/ 42218) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #67 |
| 2294 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250*/ 43640) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #68 |
| 2295 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr*/ 46448) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #69 |
| 2296 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr_V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250_V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250*/ 46576) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #70 |
| 2297 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 46828) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #71 |
| 2298 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 47548) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #72 |
| 2299 | {DBGFIELD(/*V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12*/ 48921) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #73 |
| 2300 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 49481) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #74 |
| 2301 | {DBGFIELD(/*V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12*/ 49679) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #75 |
| 2302 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_threeaddr_w32_V_WMMA_I32_16X16X16_IU4_threeaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_threeaddr_V_WMMA_I32_16X16X16_IU8_threeaddr_w32_V_WMMA_I32_16X16X16_IU8_threeaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_threeaddr_V_WMMA_I32_16X16X32_IU4_w64_threeaddr*/ 50741) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #76 |
| 2303 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_threeaddr*/ 51007) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #77 |
| 2304 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_twoaddr_V_WMMA_F64_16X16X4_F64_w32_twoaddr_gfx1250*/ 51044) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #78 |
| 2305 | {DBGFIELD(/*Write32Bit*/ 51122) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #79 |
| 2306 | {DBGFIELD(/*Write64Bit*/ 51133) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #80 |
| 2307 | {DBGFIELD(/*WriteSALU*/ 51144) 1, false, false, true, 0, 1, 47, 0, 1, 1}, // #81 |
| 2308 | {DBGFIELD(/*Write64Bit_MIVGPRRead*/ 51154) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #82 |
| 2309 | {DBGFIELD(/*Write64Bit_ReadDefault*/ 51176) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #83 |
| 2310 | {DBGFIELD(/*Write16PassMAI_MIMFMARead*/ 51199) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #84 |
| 2311 | {DBGFIELD(/*Write8PassMAI_MIMFMARead*/ 51225) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #85 |
| 2312 | {DBGFIELD(/*Write4PassMAI_MIMFMARead*/ 51250) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #86 |
| 2313 | {DBGFIELD(/*WriteXDL2PassWMMA*/ 51275) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #87 |
| 2314 | {DBGFIELD(/*WriteXDL1PassWMMA*/ 51293) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #88 |
| 2315 | {DBGFIELD(/*WriteXDL4PassWMMA*/ 51311) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #89 |
| 2316 | {DBGFIELD(/*WriteXDL8PassWMMA*/ 51329) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #90 |
| 2317 | }; // SIDPGFX942FullSpeedModelSchedClasses |
| 2318 | |
| 2319 | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, ReadAdvanceIdx, WriteProcResIdx, WriteLatencyIdx, NumReadAdvanceEntries, NumWriteProcResEntries, NumWriteLatencyEntries} |
| 2320 | static const llvm::MCSchedClassDesc SIDPFullSpeedModelSchedClasses[] = { |
| 2321 | {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
| 2322 | {DBGFIELD(/*NullALU_WriteSALU*/ 19) 1, false, false, true, 0, 1, 47, 0, 1, 1}, // #1 |
| 2323 | {DBGFIELD(/*NullALU_Write32Bit*/ 37) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #2 |
| 2324 | {DBGFIELD(/*NullALU_Write32Bit_Write32Bit*/ 56) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #3 |
| 2325 | {DBGFIELD(/*NullALU_WriteVMEM*/ 86) 1, false, false, true, 0, 23, 50, 0, 1, 1}, // #4 |
| 2326 | {DBGFIELD(/*NullALU_WriteVMEM_WriteLDS*/ 104) 2, false, false, true, 0, 54, 51, 0, 2, 2}, // #5 |
| 2327 | {DBGFIELD(/*NullALU_WriteLDS*/ 131) 1, false, false, true, 0, 9, 2, 0, 1, 1}, // #6 |
| 2328 | {DBGFIELD(/*NullALU_WriteLDS_WriteLDS*/ 148) 2, false, false, true, 0, 14, 2, 0, 1, 2}, // #7 |
| 2329 | {DBGFIELD(/*NullALU_WriteExport*/ 174) 1, false, false, true, 0, 16, 31, 0, 1, 1}, // #8 |
| 2330 | {DBGFIELD(/*WriteBranch*/ 194) 1, false, false, true, 0, 18, 21, 0, 1, 1}, // #9 |
| 2331 | {DBGFIELD(/*NullALU*/ 206) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #10 |
| 2332 | {DBGFIELD(/*NullALU_WriteBranch*/ 214) 1, false, false, true, 0, 18, 21, 0, 1, 1}, // #11 |
| 2333 | {DBGFIELD(/*NullALU_WriteSFPU*/ 234) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #12 |
| 2334 | {DBGFIELD(/*NullALU_WriteSMEM*/ 252) 1, false, false, true, 0, 9, 2, 0, 1, 1}, // #13 |
| 2335 | {DBGFIELD(/*NullALU_WriteBarrier*/ 270) 1, false, false, true, 0, 18, 53, 0, 1, 1}, // #14 |
| 2336 | {DBGFIELD(/*NullALU_WriteSALU_Write64Bit*/ 291) 2, false, false, true, 0, 1, 47, 0, 2, 2}, // #15 |
| 2337 | {DBGFIELD(/*NullALU_Write32Bit_WriteSALU*/ 320) 2, false, false, true, 0, 1, 47, 0, 2, 2}, // #16 |
| 2338 | {DBGFIELD(/*NullALU_WriteDoubleAdd*/ 349) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #17 |
| 2339 | {DBGFIELD(/*NullALU_Write64Bit*/ 372) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #18 |
| 2340 | {DBGFIELD(/*NullALU_WriteTrans32*/ 391) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #19 |
| 2341 | {DBGFIELD(/*NullALU_WriteFloatCvt*/ 412) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #20 |
| 2342 | {DBGFIELD(/*NullALU_WriteDoubleCvt*/ 434) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #21 |
| 2343 | {DBGFIELD(/*NullALU_WriteFloatFMA*/ 457) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #22 |
| 2344 | {DBGFIELD(/*NullALU_WriteDouble*/ 479) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #23 |
| 2345 | {DBGFIELD(/*NullALU_WriteFloatFMA_WriteSALUDummy*/ 499) 1, false, false, true, 0, 1, 47, 0, 2, 2}, // #24 |
| 2346 | {DBGFIELD(/*NullALU_WriteDouble_WriteSALUDummy*/ 536) 1, false, false, true, 0, 1, 47, 0, 2, 2}, // #25 |
| 2347 | {DBGFIELD(/*NullALU_WriteIntMul_WriteSALUDummy*/ 571) 1, false, false, true, 0, 1, 47, 0, 2, 2}, // #26 |
| 2348 | {DBGFIELD(/*NullALU_WriteIntMul*/ 606) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #27 |
| 2349 | {DBGFIELD(/*NullALU_WriteQuarterRate32*/ 626) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #28 |
| 2350 | {DBGFIELD(/*NullALU_Write32Bit_WriteVALUDummy*/ 653) 1, false, false, true, 0, 53, 47, 0, 1, 2}, // #29 |
| 2351 | {DBGFIELD(/*NullALU_WriteTrans64*/ 687) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #30 |
| 2352 | {DBGFIELD(/*NullALU_Write64Bit_Write64Bit*/ 708) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #31 |
| 2353 | {DBGFIELD(/*NullALU_WritePseudoScalarTrans*/ 738) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
| 2354 | {DBGFIELD(/*NullALU_WriteVMEM_WriteVMEM_WriteVMEM*/ 769) 3, false, false, true, 0, 56, 60, 0, 1, 3}, // #33 |
| 2355 | {DBGFIELD(/*NullALU_WriteDoubleAdd_Write32Bit*/ 807) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #34 |
| 2356 | {DBGFIELD(/*COPY*/ 841) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #35 |
| 2357 | {DBGFIELD(/*V_ACCVGPR_WRITE_B32_e64*/ 846) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #36 |
| 2358 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 870) 1, false, false, true, 1, 59, 31, 1, 1, 1}, // #37 |
| 2359 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 1996) 1, false, false, true, 1, 60, 21, 1, 1, 1}, // #38 |
| 2360 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 7379) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #39 |
| 2361 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 14259) 1, false, false, true, 1, 6, 1, 1, 1, 1}, // #40 |
| 2362 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 15206) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #41 |
| 2363 | {DBGFIELD(/*V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd*/ 20331) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #42 |
| 2364 | {DBGFIELD(/*V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi*/ 20460) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #43 |
| 2365 | {DBGFIELD(/*V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd*/ 21054) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #44 |
| 2366 | {DBGFIELD(/*V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi*/ 22045) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #45 |
| 2367 | {DBGFIELD(/*V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd*/ 23391) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #46 |
| 2368 | {DBGFIELD(/*V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 23589) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #47 |
| 2369 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd*/ 24372) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #48 |
| 2370 | {DBGFIELD(/*V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi*/ 25890) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #49 |
| 2371 | {DBGFIELD(/*V_SMFMAC_F32_16X16X128_BF8_BF8_e64_V_SMFMAC_F32_16X16X128_BF8_FP8_e64_V_SMFMAC_F32_16X16X128_FP8_BF8_e64_V_SMFMAC_F32_16X16X128_FP8_FP8_e64_V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_F16_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X128_I8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_F16_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X128_I8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940*/ 27751) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #50 |
| 2372 | {DBGFIELD(/*V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_F16_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_F32_32X32X64_BF8_BF8_e64_V_SMFMAC_F32_32X32X64_BF8_FP8_e64_V_SMFMAC_F32_32X32X64_FP8_BF8_e64_V_SMFMAC_F32_32X32X64_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_I32_32X32X64_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_F16_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940_V_SMFMAC_I32_32X32X64_I8_gfx940*/ 28707) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #51 |
| 2373 | {DBGFIELD(/*V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 29653) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #52 |
| 2374 | {DBGFIELD(/*V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd*/ 29782) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #53 |
| 2375 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 29980) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #54 |
| 2376 | {DBGFIELD(/*V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 31537) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #55 |
| 2377 | {DBGFIELD(/*V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd*/ 33310) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #56 |
| 2378 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_threeaddr*/ 35956) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #57 |
| 2379 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_twoaddr_V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250*/ 35993) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #58 |
| 2380 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr*/ 36071) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #59 |
| 2381 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250*/ 36407) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #60 |
| 2382 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X16_F16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_V_WMMA_F32_16X16X16_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 37111) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #61 |
| 2383 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X16_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X16_F16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X16_BF16_w32_threeaddr_V_WMMA_F32_16X16X16_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 38981) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #62 |
| 2384 | {DBGFIELD(/*V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 39334) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #63 |
| 2385 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr*/ 40806) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #64 |
| 2386 | {DBGFIELD(/*V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250*/ 41150) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #65 |
| 2387 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_w32_threeaddr_V_WMMA_I32_16X16X16_IU8_w32_threeaddr_V_WMMA_I32_16X16X32_IU4_w32_threeaddr_V_WMMA_I32_16X16X64_IU8_w32_threeaddr*/ 42066) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #66 |
| 2388 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr*/ 42218) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #67 |
| 2389 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250*/ 43640) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #68 |
| 2390 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr*/ 46448) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #69 |
| 2391 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr_V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250_V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250*/ 46576) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #70 |
| 2392 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 46828) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #71 |
| 2393 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 47548) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #72 |
| 2394 | {DBGFIELD(/*V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12*/ 48921) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #73 |
| 2395 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 49481) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #74 |
| 2396 | {DBGFIELD(/*V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12*/ 49679) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #75 |
| 2397 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_threeaddr_w32_V_WMMA_I32_16X16X16_IU4_threeaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_threeaddr_V_WMMA_I32_16X16X16_IU8_threeaddr_w32_V_WMMA_I32_16X16X16_IU8_threeaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_threeaddr_V_WMMA_I32_16X16X32_IU4_w64_threeaddr*/ 50741) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #76 |
| 2398 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_threeaddr*/ 51007) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #77 |
| 2399 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_twoaddr_V_WMMA_F64_16X16X4_F64_w32_twoaddr_gfx1250*/ 51044) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #78 |
| 2400 | {DBGFIELD(/*Write32Bit*/ 51122) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #79 |
| 2401 | {DBGFIELD(/*Write64Bit*/ 51133) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #80 |
| 2402 | {DBGFIELD(/*WriteSALU*/ 51144) 1, false, false, true, 0, 1, 47, 0, 1, 1}, // #81 |
| 2403 | {DBGFIELD(/*Write64Bit_MIVGPRRead*/ 51154) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #82 |
| 2404 | {DBGFIELD(/*Write64Bit_ReadDefault*/ 51176) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #83 |
| 2405 | {DBGFIELD(/*Write16PassMAI_MIMFMARead*/ 51199) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #84 |
| 2406 | {DBGFIELD(/*Write8PassMAI_MIMFMARead*/ 51225) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #85 |
| 2407 | {DBGFIELD(/*Write4PassMAI_MIMFMARead*/ 51250) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #86 |
| 2408 | {DBGFIELD(/*WriteXDL2PassWMMA*/ 51275) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #87 |
| 2409 | {DBGFIELD(/*WriteXDL1PassWMMA*/ 51293) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #88 |
| 2410 | {DBGFIELD(/*WriteXDL4PassWMMA*/ 51311) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #89 |
| 2411 | {DBGFIELD(/*WriteXDL8PassWMMA*/ 51329) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #90 |
| 2412 | }; // SIDPFullSpeedModelSchedClasses |
| 2413 | |
| 2414 | // {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, ReadAdvanceIdx, WriteProcResIdx, WriteLatencyIdx, NumReadAdvanceEntries, NumWriteProcResEntries, NumWriteLatencyEntries} |
| 2415 | static const llvm::MCSchedClassDesc SIDPGFX950FullSpeedModelSchedClasses[] = { |
| 2416 | {DBGFIELD(1) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, |
| 2417 | {DBGFIELD(/*NullALU_WriteSALU*/ 19) 1, false, false, true, 0, 1, 47, 0, 1, 1}, // #1 |
| 2418 | {DBGFIELD(/*NullALU_Write32Bit*/ 37) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #2 |
| 2419 | {DBGFIELD(/*NullALU_Write32Bit_Write32Bit*/ 56) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #3 |
| 2420 | {DBGFIELD(/*NullALU_WriteVMEM*/ 86) 1, false, false, true, 0, 23, 50, 0, 1, 1}, // #4 |
| 2421 | {DBGFIELD(/*NullALU_WriteVMEM_WriteLDS*/ 104) 2, false, false, true, 0, 54, 51, 0, 2, 2}, // #5 |
| 2422 | {DBGFIELD(/*NullALU_WriteLDS*/ 131) 1, false, false, true, 0, 9, 2, 0, 1, 1}, // #6 |
| 2423 | {DBGFIELD(/*NullALU_WriteLDS_WriteLDS*/ 148) 2, false, false, true, 0, 14, 2, 0, 1, 2}, // #7 |
| 2424 | {DBGFIELD(/*NullALU_WriteExport*/ 174) 1, false, false, true, 0, 16, 31, 0, 1, 1}, // #8 |
| 2425 | {DBGFIELD(/*WriteBranch*/ 194) 1, false, false, true, 0, 18, 21, 0, 1, 1}, // #9 |
| 2426 | {DBGFIELD(/*NullALU*/ 206) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #10 |
| 2427 | {DBGFIELD(/*NullALU_WriteBranch*/ 214) 1, false, false, true, 0, 18, 21, 0, 1, 1}, // #11 |
| 2428 | {DBGFIELD(/*NullALU_WriteSFPU*/ 234) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #12 |
| 2429 | {DBGFIELD(/*NullALU_WriteSMEM*/ 252) 1, false, false, true, 0, 9, 2, 0, 1, 1}, // #13 |
| 2430 | {DBGFIELD(/*NullALU_WriteBarrier*/ 270) 1, false, false, true, 0, 18, 53, 0, 1, 1}, // #14 |
| 2431 | {DBGFIELD(/*NullALU_WriteSALU_Write64Bit*/ 291) 2, false, false, true, 0, 1, 47, 0, 2, 2}, // #15 |
| 2432 | {DBGFIELD(/*NullALU_Write32Bit_WriteSALU*/ 320) 2, false, false, true, 0, 1, 47, 0, 2, 2}, // #16 |
| 2433 | {DBGFIELD(/*NullALU_WriteDoubleAdd*/ 349) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #17 |
| 2434 | {DBGFIELD(/*NullALU_Write64Bit*/ 372) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #18 |
| 2435 | {DBGFIELD(/*NullALU_WriteTrans32*/ 391) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #19 |
| 2436 | {DBGFIELD(/*NullALU_WriteFloatCvt*/ 412) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #20 |
| 2437 | {DBGFIELD(/*NullALU_WriteDoubleCvt*/ 434) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #21 |
| 2438 | {DBGFIELD(/*NullALU_WriteFloatFMA*/ 457) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #22 |
| 2439 | {DBGFIELD(/*NullALU_WriteDouble*/ 479) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #23 |
| 2440 | {DBGFIELD(/*NullALU_WriteFloatFMA_WriteSALUDummy*/ 499) 1, false, false, true, 0, 1, 47, 0, 2, 2}, // #24 |
| 2441 | {DBGFIELD(/*NullALU_WriteDouble_WriteSALUDummy*/ 536) 1, false, false, true, 0, 1, 47, 0, 2, 2}, // #25 |
| 2442 | {DBGFIELD(/*NullALU_WriteIntMul_WriteSALUDummy*/ 571) 1, false, false, true, 0, 1, 47, 0, 2, 2}, // #26 |
| 2443 | {DBGFIELD(/*NullALU_WriteIntMul*/ 606) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #27 |
| 2444 | {DBGFIELD(/*NullALU_WriteQuarterRate32*/ 626) 1, false, false, true, 0, 2, 31, 0, 1, 1}, // #28 |
| 2445 | {DBGFIELD(/*NullALU_Write32Bit_WriteVALUDummy*/ 653) 1, false, false, true, 0, 53, 47, 0, 1, 2}, // #29 |
| 2446 | {DBGFIELD(/*NullALU_WriteTrans64*/ 687) 1, false, false, false, 0, 2, 31, 0, 1, 1}, // #30 |
| 2447 | {DBGFIELD(/*NullALU_Write64Bit_Write64Bit*/ 708) 2, false, false, false, 0, 53, 47, 0, 1, 2}, // #31 |
| 2448 | {DBGFIELD(/*NullALU_WritePseudoScalarTrans*/ 738) 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #32 |
| 2449 | {DBGFIELD(/*NullALU_WriteVMEM_WriteVMEM_WriteVMEM*/ 769) 3, false, false, true, 0, 56, 60, 0, 1, 3}, // #33 |
| 2450 | {DBGFIELD(/*NullALU_WriteDoubleAdd_Write32Bit*/ 807) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #34 |
| 2451 | {DBGFIELD(/*COPY*/ 841) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #35 |
| 2452 | {DBGFIELD(/*V_ACCVGPR_WRITE_B32_e64*/ 846) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #36 |
| 2453 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 870) 1, false, false, true, 1, 59, 31, 1, 1, 1}, // #37 |
| 2454 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 1996) 1, false, false, true, 1, 62, 10, 1, 1, 1}, // #38 |
| 2455 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 7379) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #39 |
| 2456 | {DBGFIELD(/*V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi*/ 14259) 1, false, false, true, 1, 6, 1, 1, 1, 1}, // #40 |
| 2457 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 15206) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #41 |
| 2458 | {DBGFIELD(/*V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd*/ 20331) 1, false, false, true, 1, 61, 31, 1, 1, 1}, // #42 |
| 2459 | {DBGFIELD(/*V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi*/ 20460) 1, false, false, true, 1, 61, 31, 1, 1, 1}, // #43 |
| 2460 | {DBGFIELD(/*V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd*/ 21054) 1, false, false, true, 1, 61, 31, 1, 1, 1}, // #44 |
| 2461 | {DBGFIELD(/*V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi*/ 22045) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #45 |
| 2462 | {DBGFIELD(/*V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd*/ 23391) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #46 |
| 2463 | {DBGFIELD(/*V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi*/ 23589) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #47 |
| 2464 | {DBGFIELD(/*V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd*/ 24372) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #48 |
| 2465 | {DBGFIELD(/*V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi*/ 25890) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #49 |
| 2466 | {DBGFIELD(/*V_SMFMAC_F32_16X16X128_BF8_BF8_e64_V_SMFMAC_F32_16X16X128_BF8_FP8_e64_V_SMFMAC_F32_16X16X128_FP8_BF8_e64_V_SMFMAC_F32_16X16X128_FP8_FP8_e64_V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_F16_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X128_I8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_F16_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X128_I8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940*/ 27751) 1, false, false, true, 1, 61, 31, 1, 1, 1}, // #50 |
| 2467 | {DBGFIELD(/*V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_F16_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_F32_32X32X64_BF8_BF8_e64_V_SMFMAC_F32_32X32X64_BF8_FP8_e64_V_SMFMAC_F32_32X32X64_FP8_BF8_e64_V_SMFMAC_F32_32X32X64_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_I32_32X32X64_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_F16_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940_V_SMFMAC_I32_32X32X64_I8_gfx940*/ 28707) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #51 |
| 2468 | {DBGFIELD(/*V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd*/ 29653) 1, false, false, true, 1, 61, 31, 1, 1, 1}, // #52 |
| 2469 | {DBGFIELD(/*V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd*/ 29782) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #53 |
| 2470 | {DBGFIELD(/*V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 29980) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #54 |
| 2471 | {DBGFIELD(/*V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd*/ 31537) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #55 |
| 2472 | {DBGFIELD(/*V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd*/ 33310) 8190, false, false, false, 0, 0, 0, 0, 0, 0}, // #56 |
| 2473 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_threeaddr*/ 35956) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #57 |
| 2474 | {DBGFIELD(/*V_WMMA_F32_16X16X4_F32_w32_twoaddr_V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250*/ 35993) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #58 |
| 2475 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr*/ 36071) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #59 |
| 2476 | {DBGFIELD(/*V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250*/ 36407) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #60 |
| 2477 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X16_F16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_V_WMMA_F32_16X16X16_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 37111) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #61 |
| 2478 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X16_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X16_F16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X16_BF16_w32_threeaddr_V_WMMA_F32_16X16X16_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 38981) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #62 |
| 2479 | {DBGFIELD(/*V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 39334) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #63 |
| 2480 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr*/ 40806) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #64 |
| 2481 | {DBGFIELD(/*V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250*/ 41150) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #65 |
| 2482 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_w32_threeaddr_V_WMMA_I32_16X16X16_IU8_w32_threeaddr_V_WMMA_I32_16X16X32_IU4_w32_threeaddr_V_WMMA_I32_16X16X64_IU8_w32_threeaddr*/ 42066) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #66 |
| 2483 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr*/ 42218) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #67 |
| 2484 | {DBGFIELD(/*V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250*/ 43640) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #68 |
| 2485 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr*/ 46448) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #69 |
| 2486 | {DBGFIELD(/*V_WMMA_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr_V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250_V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250*/ 46576) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #70 |
| 2487 | {DBGFIELD(/*V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250*/ 46828) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #71 |
| 2488 | {DBGFIELD(/*V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250*/ 47548) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #72 |
| 2489 | {DBGFIELD(/*V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12*/ 48921) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #73 |
| 2490 | {DBGFIELD(/*V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr*/ 49481) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #74 |
| 2491 | {DBGFIELD(/*V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12*/ 49679) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #75 |
| 2492 | {DBGFIELD(/*V_WMMA_I32_16X16X16_IU4_threeaddr_w32_V_WMMA_I32_16X16X16_IU4_threeaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_threeaddr_V_WMMA_I32_16X16X16_IU8_threeaddr_w32_V_WMMA_I32_16X16X16_IU8_threeaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_threeaddr_V_WMMA_I32_16X16X32_IU4_w64_threeaddr*/ 50741) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #76 |
| 2493 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_threeaddr*/ 51007) 2, false, false, true, 0, 53, 47, 0, 1, 2}, // #77 |
| 2494 | {DBGFIELD(/*V_WMMA_F64_16X16X4_F64_w32_twoaddr_V_WMMA_F64_16X16X4_F64_w32_twoaddr_gfx1250*/ 51044) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #78 |
| 2495 | {DBGFIELD(/*Write32Bit*/ 51122) 1, false, false, true, 0, 2, 47, 0, 1, 1}, // #79 |
| 2496 | {DBGFIELD(/*Write64Bit*/ 51133) 1, false, false, false, 0, 2, 47, 0, 1, 1}, // #80 |
| 2497 | {DBGFIELD(/*WriteSALU*/ 51144) 1, false, false, true, 0, 1, 47, 0, 1, 1}, // #81 |
| 2498 | {DBGFIELD(/*Write64Bit_MIVGPRRead*/ 51154) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #82 |
| 2499 | {DBGFIELD(/*Write64Bit_ReadDefault*/ 51176) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #83 |
| 2500 | {DBGFIELD(/*Write16PassMAI_MIMFMARead*/ 51199) 1, false, false, true, 1, 58, 10, 1, 1, 1}, // #84 |
| 2501 | {DBGFIELD(/*Write8PassMAI_MIMFMARead*/ 51225) 1, false, false, true, 1, 57, 21, 1, 1, 1}, // #85 |
| 2502 | {DBGFIELD(/*Write4PassMAI_MIMFMARead*/ 51250) 1, false, false, true, 1, 61, 31, 1, 1, 1}, // #86 |
| 2503 | {DBGFIELD(/*WriteXDL2PassWMMA*/ 51275) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #87 |
| 2504 | {DBGFIELD(/*WriteXDL1PassWMMA*/ 51293) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #88 |
| 2505 | {DBGFIELD(/*WriteXDL4PassWMMA*/ 51311) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #89 |
| 2506 | {DBGFIELD(/*WriteXDL8PassWMMA*/ 51329) 0, false, false, false, 0, 0, 0, 0, 0, 0}, // #90 |
| 2507 | }; // SIDPGFX950FullSpeedModelSchedClasses |
| 2508 | |
| 2509 | #ifdef __GNUC__ |
| 2510 | #pragma GCC diagnostic push |
| 2511 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 2512 | #endif |
| 2513 | static constexpr char AMDGPUSchedClassNamesStorage[] = |
| 2514 | "\0" |
| 2515 | "InvalidSchedClass\0" |
| 2516 | "NullALU_WriteSALU\0" |
| 2517 | "NullALU_Write32Bit\0" |
| 2518 | "NullALU_Write32Bit_Write32Bit\0" |
| 2519 | "NullALU_WriteVMEM\0" |
| 2520 | "NullALU_WriteVMEM_WriteLDS\0" |
| 2521 | "NullALU_WriteLDS\0" |
| 2522 | "NullALU_WriteLDS_WriteLDS\0" |
| 2523 | "NullALU_WriteExport\0" |
| 2524 | "WriteBranch\0" |
| 2525 | "NullALU\0" |
| 2526 | "NullALU_WriteBranch\0" |
| 2527 | "NullALU_WriteSFPU\0" |
| 2528 | "NullALU_WriteSMEM\0" |
| 2529 | "NullALU_WriteBarrier\0" |
| 2530 | "NullALU_WriteSALU_Write64Bit\0" |
| 2531 | "NullALU_Write32Bit_WriteSALU\0" |
| 2532 | "NullALU_WriteDoubleAdd\0" |
| 2533 | "NullALU_Write64Bit\0" |
| 2534 | "NullALU_WriteTrans32\0" |
| 2535 | "NullALU_WriteFloatCvt\0" |
| 2536 | "NullALU_WriteDoubleCvt\0" |
| 2537 | "NullALU_WriteFloatFMA\0" |
| 2538 | "NullALU_WriteDouble\0" |
| 2539 | "NullALU_WriteFloatFMA_WriteSALUDummy\0" |
| 2540 | "NullALU_WriteDouble_WriteSALUDummy\0" |
| 2541 | "NullALU_WriteIntMul_WriteSALUDummy\0" |
| 2542 | "NullALU_WriteIntMul\0" |
| 2543 | "NullALU_WriteQuarterRate32\0" |
| 2544 | "NullALU_Write32Bit_WriteVALUDummy\0" |
| 2545 | "NullALU_WriteTrans64\0" |
| 2546 | "NullALU_Write64Bit_Write64Bit\0" |
| 2547 | "NullALU_WritePseudoScalarTrans\0" |
| 2548 | "NullALU_WriteVMEM_WriteVMEM_WriteVMEM\0" |
| 2549 | "NullALU_WriteDoubleAdd_Write32Bit\0" |
| 2550 | "COPY\0" |
| 2551 | "V_ACCVGPR_WRITE_B32_e64\0" |
| 2552 | "V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_F64_4X4X4F64_e64_V_MFMA_F64_4X4X4F64_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_F64_4X4X4F64_gfx90a_acd_V_MFMA_F64_4X4X4F64_gfx90a_vcd_V_MFMA_F64_4X4X4F64_gfx940_acd_V_MFMA_F64_4X4X4F64_gfx940_vcd_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi\0" |
| 2553 | "V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F64_16X16X4F64_e64_V_MFMA_F64_16X16X4F64_mac_e64_V_MFMA_F64_16X16X4F64_mac_vgprcd_e64_V_MFMA_F64_16X16X4F64_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_F64_16X16X4F64_gfx90a_acd_V_MFMA_F64_16X16X4F64_gfx90a_vcd_V_MFMA_F64_16X16X4F64_gfx940_acd_V_MFMA_F64_16X16X4F64_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd\0" |
| 2554 | "V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi\0" |
| 2555 | "V_MFMA_F32_4X4X1F32_e64_V_MFMA_F32_4X4X1F32_vgprcd_e64_V_MFMA_F32_4X4X2BF16_e64_V_MFMA_F32_4X4X2BF16_vgprcd_e64_V_MFMA_F32_4X4X4BF16_1K_e64_V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64_V_MFMA_F32_4X4X4F16_e64_V_MFMA_F32_4X4X4F16_vgprcd_e64_V_MFMA_I32_4X4X4I8_e64_V_MFMA_I32_4X4X4I8_vgprcd_e64_V_MFMA_F32_4X4X1F32_gfx90a_acd_V_MFMA_F32_4X4X1F32_gfx90a_vcd_V_MFMA_F32_4X4X1F32_gfx940_acd_V_MFMA_F32_4X4X1F32_gfx940_vcd_V_MFMA_F32_4X4X1F32_vi_V_MFMA_F32_4X4X2BF16_gfx90a_acd_V_MFMA_F32_4X4X2BF16_gfx90a_vcd_V_MFMA_F32_4X4X2BF16_vi_V_MFMA_F32_4X4X4BF16_1K_gfx90a_acd_V_MFMA_F32_4X4X4BF16_1K_gfx90a_vcd_V_MFMA_F32_4X4X4BF16_1K_gfx940_acd_V_MFMA_F32_4X4X4BF16_1K_gfx940_vcd_V_MFMA_F32_4X4X4F16_gfx90a_acd_V_MFMA_F32_4X4X4F16_gfx90a_vcd_V_MFMA_F32_4X4X4F16_gfx940_acd_V_MFMA_F32_4X4X4F16_gfx940_vcd_V_MFMA_F32_4X4X4F16_vi_V_MFMA_I32_4X4X4I8_gfx90a_acd_V_MFMA_I32_4X4X4I8_gfx90a_vcd_V_MFMA_I32_4X4X4I8_gfx940_acd_V_MFMA_I32_4X4X4I8_gfx940_vcd_V_MFMA_I32_4X4X4I8_vi\0" |
| 2556 | "V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X2BF16_e64_V_MFMA_F32_16X16X2BF16_mac_e64_V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64_V_MFMA_F32_16X16X2BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_F32_16X16X8BF16_e64_V_MFMA_F32_16X16X8BF16_vgprcd_e64_V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X2BF16_gfx90a_acd_V_MFMA_F32_16X16X2BF16_gfx90a_vcd_V_MFMA_F32_16X16X2BF16_vi_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_F32_16X16X8BF16_gfx90a_acd_V_MFMA_F32_16X16X8BF16_gfx90a_vcd_V_MFMA_F32_16X16X8BF16_vi_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd\0" |
| 2557 | "V_MFMA_F32_16X16X8XF32_e64_V_MFMA_F32_16X16X8XF32_vgprcd_e64_V_MFMA_F32_16X16X8XF32_gfx940_acd_V_MFMA_F32_16X16X8XF32_gfx940_vcd\0" |
| 2558 | "V_MFMA_F32_16X16X16BF16_1K_e64_V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X16F16_e64_V_MFMA_F32_16X16X16F16_vgprcd_e64_V_MFMA_I32_16X16X16I8_e64_V_MFMA_I32_16X16X16I8_vgprcd_e64_V_MFMA_F32_16X16X16BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X16BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X16BF16_1K_gfx940_acd_V_MFMA_F32_16X16X16BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X16F16_gfx90a_acd_V_MFMA_F32_16X16X16F16_gfx90a_vcd_V_MFMA_F32_16X16X16F16_gfx940_acd_V_MFMA_F32_16X16X16F16_gfx940_vcd_V_MFMA_F32_16X16X16F16_vi_V_MFMA_I32_16X16X16I8_gfx90a_acd_V_MFMA_I32_16X16X16I8_gfx90a_vcd_V_MFMA_I32_16X16X16I8_vi\0" |
| 2559 | "V_MFMA_F32_16X16X32_BF16_e64_V_MFMA_F32_16X16X32_BF16_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_BF8_e64_V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_BF8_FP8_e64_V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64_V_MFMA_F32_16X16X32_F16_e64_V_MFMA_F32_16X16X32_F16_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_BF8_e64_V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64_V_MFMA_F32_16X16X32_FP8_FP8_e64_V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64_V_MFMA_I32_16X16X32I8_e64_V_MFMA_I32_16X16X32I8_vgprcd_e64_V_MFMA_F32_16X16X32_BF16_gfx940_acd_V_MFMA_F32_16X16X32_BF16_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_BF8_FP8_gfx940_vcd_V_MFMA_F32_16X16X32_F16_gfx940_acd_V_MFMA_F32_16X16X32_F16_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_BF8_gfx940_vcd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_acd_V_MFMA_F32_16X16X32_FP8_FP8_gfx940_vcd_V_MFMA_I32_16X16X32I8_gfx940_acd_V_MFMA_I32_16X16X32I8_gfx940_vcd\0" |
| 2560 | "V_MFMA_F32_16X16X1F32_e64_V_MFMA_F32_16X16X1F32_mac_e64_V_MFMA_F32_16X16X1F32_mac_vgprcd_e64_V_MFMA_F32_16X16X1F32_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_e64_V_MFMA_F32_16X16X4BF16_1K_mac_e64_V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_16X16X4BF16_1K_vgprcd_e64_V_MFMA_F32_16X16X4F16_e64_V_MFMA_F32_16X16X4F16_mac_e64_V_MFMA_F32_16X16X4F16_mac_vgprcd_e64_V_MFMA_F32_16X16X4F16_vgprcd_e64_V_MFMA_F32_16X16X4F32_e64_V_MFMA_F32_16X16X4F32_vgprcd_e64_V_MFMA_I32_16X16X4I8_e64_V_MFMA_I32_16X16X4I8_mac_e64_V_MFMA_I32_16X16X4I8_mac_vgprcd_e64_V_MFMA_I32_16X16X4I8_vgprcd_e64_V_MFMA_F32_16X16X1F32_gfx90a_acd_V_MFMA_F32_16X16X1F32_gfx90a_vcd_V_MFMA_F32_16X16X1F32_gfx940_acd_V_MFMA_F32_16X16X1F32_gfx940_vcd_V_MFMA_F32_16X16X1F32_vi_V_MFMA_F32_16X16X4BF16_1K_gfx90a_acd_V_MFMA_F32_16X16X4BF16_1K_gfx90a_vcd_V_MFMA_F32_16X16X4BF16_1K_gfx940_acd_V_MFMA_F32_16X16X4BF16_1K_gfx940_vcd_V_MFMA_F32_16X16X4F16_gfx90a_acd_V_MFMA_F32_16X16X4F16_gfx90a_vcd_V_MFMA_F32_16X16X4F16_gfx940_acd_V_MFMA_F32_16X16X4F16_gfx940_vcd_V_MFMA_F32_16X16X4F16_vi_V_MFMA_F32_16X16X4F32_gfx90a_acd_V_MFMA_F32_16X16X4F32_gfx90a_vcd_V_MFMA_F32_16X16X4F32_gfx940_acd_V_MFMA_F32_16X16X4F32_gfx940_vcd_V_MFMA_F32_16X16X4F32_vi_V_MFMA_I32_16X16X4I8_gfx90a_acd_V_MFMA_I32_16X16X4I8_gfx90a_vcd_V_MFMA_I32_16X16X4I8_gfx940_acd_V_MFMA_I32_16X16X4I8_gfx940_vcd_V_MFMA_I32_16X16X4I8_vi\0" |
| 2561 | "V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd\0" |
| 2562 | "V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi\0" |
| 2563 | "V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd\0" |
| 2564 | "V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi\0" |
| 2565 | "V_SMFMAC_F32_16X16X128_BF8_BF8_e64_V_SMFMAC_F32_16X16X128_BF8_FP8_e64_V_SMFMAC_F32_16X16X128_FP8_BF8_e64_V_SMFMAC_F32_16X16X128_FP8_FP8_e64_V_SMFMAC_F32_16X16X32_BF16_e64_V_SMFMAC_F32_16X16X32_F16_e64_V_SMFMAC_F32_16X16X64_BF16_e64_V_SMFMAC_F32_16X16X64_BF8_BF8_e64_V_SMFMAC_F32_16X16X64_BF8_FP8_e64_V_SMFMAC_F32_16X16X64_F16_e64_V_SMFMAC_F32_16X16X64_FP8_BF8_e64_V_SMFMAC_F32_16X16X64_FP8_FP8_e64_V_SMFMAC_I32_16X16X128_I8_e64_V_SMFMAC_I32_16X16X64_I8_e64_V_SMFMAC_F32_16X16X128_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X128_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X128_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X128_FP8_FP8_gfx940_V_SMFMAC_F32_16X16X32_BF16_gfx940_V_SMFMAC_F32_16X16X32_F16_gfx940_V_SMFMAC_F32_16X16X64_BF16_gfx940_V_SMFMAC_F32_16X16X64_BF8_BF8_gfx940_V_SMFMAC_F32_16X16X64_BF8_FP8_gfx940_V_SMFMAC_F32_16X16X64_F16_gfx940_V_SMFMAC_F32_16X16X64_FP8_BF8_gfx940_V_SMFMAC_F32_16X16X64_FP8_FP8_gfx940_V_SMFMAC_I32_16X16X128_I8_gfx940_V_SMFMAC_I32_16X16X64_I8_gfx940\0" |
| 2566 | "V_SMFMAC_F32_32X32X16_BF16_e64_V_SMFMAC_F32_32X32X16_F16_e64_V_SMFMAC_F32_32X32X32_BF16_e64_V_SMFMAC_F32_32X32X32_BF8_BF8_e64_V_SMFMAC_F32_32X32X32_BF8_FP8_e64_V_SMFMAC_F32_32X32X32_F16_e64_V_SMFMAC_F32_32X32X32_FP8_BF8_e64_V_SMFMAC_F32_32X32X32_FP8_FP8_e64_V_SMFMAC_F32_32X32X64_BF8_BF8_e64_V_SMFMAC_F32_32X32X64_BF8_FP8_e64_V_SMFMAC_F32_32X32X64_FP8_BF8_e64_V_SMFMAC_F32_32X32X64_FP8_FP8_e64_V_SMFMAC_I32_32X32X32_I8_e64_V_SMFMAC_I32_32X32X64_I8_e64_V_SMFMAC_F32_32X32X16_BF16_gfx940_V_SMFMAC_F32_32X32X16_F16_gfx940_V_SMFMAC_F32_32X32X32_BF16_gfx940_V_SMFMAC_F32_32X32X32_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X32_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X32_F16_gfx940_V_SMFMAC_F32_32X32X32_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X32_FP8_FP8_gfx940_V_SMFMAC_F32_32X32X64_BF8_BF8_gfx940_V_SMFMAC_F32_32X32X64_BF8_FP8_gfx940_V_SMFMAC_F32_32X32X64_FP8_BF8_gfx940_V_SMFMAC_F32_32X32X64_FP8_FP8_gfx940_V_SMFMAC_I32_32X32X32_I8_gfx940_V_SMFMAC_I32_32X32X64_I8_gfx940\0" |
| 2567 | "V_MFMA_I32_16X16X64_I8_e64_V_MFMA_I32_16X16X64_I8_vgprcd_e64_V_MFMA_I32_16X16X64_I8_gfx940_acd_V_MFMA_I32_16X16X64_I8_gfx940_vcd\0" |
| 2568 | "V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd\0" |
| 2569 | "V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd\0" |
| 2570 | "V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd\0" |
| 2571 | "V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd\0" |
| 2572 | "V_WMMA_F32_16X16X4_F32_w32_threeaddr\0" |
| 2573 | "V_WMMA_F32_16X16X4_F32_w32_twoaddr_V_WMMA_F32_16X16X4_F32_w32_twoaddr_gfx1250\0" |
| 2574 | "V_WMMA_F16_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_threeaddr\0" |
| 2575 | "V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X64_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X64_FP8_FP8_w32_twoaddr_gfx1250\0" |
| 2576 | "V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X16_F16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_V_WMMA_F32_16X16X16_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_BF16_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F16_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_BF16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx1170_V_WMMA_F32_16X16X16_F16_w32_twoaddr_gfx12_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250\0" |
| 2577 | "V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X16_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X16_F16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X16_BF16_w32_threeaddr_V_WMMA_F32_16X16X16_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr\0" |
| 2578 | "V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_SWMMAC_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250\0" |
| 2579 | "V_WMMA_F16_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_threeaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_threeaddr\0" |
| 2580 | "V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_V_SWMMAC_I32_16X16X128_IU8_w32_twoaddr_gfx1250_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w32_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w32_twoaddr_gfx12_V_WMMA_I32_16X16X64_IU8_w32_twoaddr_gfx1250\0" |
| 2581 | "V_WMMA_I32_16X16X16_IU4_w32_threeaddr_V_WMMA_I32_16X16X16_IU8_w32_threeaddr_V_WMMA_I32_16X16X32_IU4_w32_threeaddr_V_WMMA_I32_16X16X64_IU8_w32_threeaddr\0" |
| 2582 | "V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr\0" |
| 2583 | "V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250\0" |
| 2584 | "V_WMMA_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_threeaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_threeaddr\0" |
| 2585 | "V_WMMA_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE16_F32_32X16X128_F4_w32_twoaddr_V_WMMA_SCALE_F32_32X16X128_F4_w32_twoaddr_V_WMMA_F32_32X16X128_F4_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_32X16X128_F4_w32_gfx1250_V_WMMA_SCALE_F32_32X16X128_F4_w32_gfx1250\0" |
| 2586 | "V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_V_WMMA_F16_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X128_FP8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_BF8_FP8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_BF8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_FP8_FP8_w32_twoaddr_gfx1250\0" |
| 2587 | "V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_V_WMMA_F16_16X16X32_F16_w32_twoaddr_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_V_WMMA_F32_16X16X32_F16_w32_twoaddr_V_SWMMAC_BF16F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_BF16_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F16_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F16_16X16X64_F16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_F16_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X64_BF16_w32_twoaddr_gfx1250_V_SWMMAC_F32_16X16X64_F16_w32_twoaddr_gfx1250_V_WMMA_BF16F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_BF16_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F16_16X16X32_F16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_BF16_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X32_F16_w32_twoaddr_gfx1250\0" |
| 2588 | "V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr_gfx12_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx1170_V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr_gfx12\0" |
| 2589 | "V_WMMA_BF16F32_16X16X32_BF16_w32_threeaddr_V_WMMA_BF16_16X16X32_BF16_w32_threeaddr_V_WMMA_F16_16X16X32_F16_w32_threeaddr_V_WMMA_F32_16X16X32_BF16_w32_threeaddr_V_WMMA_F32_16X16X32_F16_w32_threeaddr\0" |
| 2590 | "V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr_gfx12_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx1170_V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU4_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU4_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU4_w64_twoaddr_gfx12_V_WMMA_I32_16X16X16_IU8_twoaddr_w32_gfx11_V_WMMA_I32_16X16X16_IU8_twoaddr_w64_gfx11_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X16_IU8_w64_twoaddr_gfx12_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx1170_V_WMMA_I32_16X16X32_IU4_w64_twoaddr_gfx12\0" |
| 2591 | "V_WMMA_I32_16X16X16_IU4_threeaddr_w32_V_WMMA_I32_16X16X16_IU4_threeaddr_w64_V_WMMA_I32_16X16X16_IU4_w64_threeaddr_V_WMMA_I32_16X16X16_IU8_threeaddr_w32_V_WMMA_I32_16X16X16_IU8_threeaddr_w64_V_WMMA_I32_16X16X16_IU8_w64_threeaddr_V_WMMA_I32_16X16X32_IU4_w64_threeaddr\0" |
| 2592 | "V_WMMA_F64_16X16X4_F64_w32_threeaddr\0" |
| 2593 | "V_WMMA_F64_16X16X4_F64_w32_twoaddr_V_WMMA_F64_16X16X4_F64_w32_twoaddr_gfx1250\0" |
| 2594 | "Write32Bit\0" |
| 2595 | "Write64Bit\0" |
| 2596 | "WriteSALU\0" |
| 2597 | "Write64Bit_MIVGPRRead\0" |
| 2598 | "Write64Bit_ReadDefault\0" |
| 2599 | "Write16PassMAI_MIMFMARead\0" |
| 2600 | "Write8PassMAI_MIMFMARead\0" |
| 2601 | "Write4PassMAI_MIMFMARead\0" |
| 2602 | "WriteXDL2PassWMMA\0" |
| 2603 | "WriteXDL1PassWMMA\0" |
| 2604 | "WriteXDL4PassWMMA\0" |
| 2605 | "WriteXDL8PassWMMA\0" |
| 2606 | ; |
| 2607 | #ifdef __GNUC__ |
| 2608 | #pragma GCC diagnostic pop |
| 2609 | #endif |
| 2610 | |
| 2611 | static constexpr llvm::StringTable |
| 2612 | AMDGPUSchedClassNames = AMDGPUSchedClassNamesStorage; |
| 2613 | |
| 2614 | static const unsigned GFX10SpeedModelProcResourceSubUnits[] = { |
| 2615 | 0, // Invalid |
| 2616 | }; |
| 2617 | |
| 2618 | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
| 2619 | static const llvm::MCProcResourceDesc GFX10SpeedModelProcResources[] = { |
| 2620 | {"InvalidUnit" , 0, 0, 0, 0}, |
| 2621 | {"HWBranch" , 1, 0, 1, nullptr}, // #1 |
| 2622 | {"HWExport" , 1, 0, 1, nullptr}, // #2 |
| 2623 | {"HWLGKM" , 1, 0, 1, nullptr}, // #3 |
| 2624 | {"HWRC" , 1, 0, 1, nullptr}, // #4 |
| 2625 | {"HWSALU" , 1, 0, 1, nullptr}, // #5 |
| 2626 | {"HWTransVALU" , 1, 0, 1, nullptr}, // #6 |
| 2627 | {"HWVALU" , 1, 0, 1, nullptr}, // #7 |
| 2628 | {"HWVMEM" , 1, 0, 1, nullptr}, // #8 |
| 2629 | }; |
| 2630 | |
| 2631 | static const unsigned GFX11SpeedModelProcResourceSubUnits[] = { |
| 2632 | 0, // Invalid |
| 2633 | }; |
| 2634 | |
| 2635 | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
| 2636 | static const llvm::MCProcResourceDesc GFX11SpeedModelProcResources[] = { |
| 2637 | {"InvalidUnit" , 0, 0, 0, 0}, |
| 2638 | {"HWBranch" , 1, 0, 1, nullptr}, // #1 |
| 2639 | {"HWExport" , 1, 0, 1, nullptr}, // #2 |
| 2640 | {"HWLGKM" , 1, 0, 1, nullptr}, // #3 |
| 2641 | {"HWRC" , 1, 0, 1, nullptr}, // #4 |
| 2642 | {"HWSALU" , 1, 0, 1, nullptr}, // #5 |
| 2643 | {"HWTransVALU" , 1, 0, 1, nullptr}, // #6 |
| 2644 | {"HWVALU" , 1, 0, 1, nullptr}, // #7 |
| 2645 | {"HWVMEM" , 1, 0, 1, nullptr}, // #8 |
| 2646 | }; |
| 2647 | |
| 2648 | static const unsigned GFX125xGenericSpeedModelProcResourceSubUnits[] = { |
| 2649 | 0, // Invalid |
| 2650 | }; |
| 2651 | |
| 2652 | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
| 2653 | static const llvm::MCProcResourceDesc GFX125xGenericSpeedModelProcResources[] = { |
| 2654 | {"InvalidUnit" , 0, 0, 0, 0}, |
| 2655 | {"HWBranch" , 1, 0, 1, nullptr}, // #1 |
| 2656 | {"HWExport" , 1, 0, 1, nullptr}, // #2 |
| 2657 | {"HWLGKM" , 1, 0, 1, nullptr}, // #3 |
| 2658 | {"HWRC" , 1, 0, 1, nullptr}, // #4 |
| 2659 | {"HWSALU" , 1, 0, 1, nullptr}, // #5 |
| 2660 | {"HWTransVALU" , 1, 0, 1, nullptr}, // #6 |
| 2661 | {"HWVALU" , 1, 0, 1, nullptr}, // #7 |
| 2662 | {"HWVMEM" , 1, 0, 1, nullptr}, // #8 |
| 2663 | {"HWXDL" , 1, 0, 0, nullptr}, // #9 |
| 2664 | }; |
| 2665 | |
| 2666 | static const unsigned GFX12SpeedModelProcResourceSubUnits[] = { |
| 2667 | 0, // Invalid |
| 2668 | }; |
| 2669 | |
| 2670 | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
| 2671 | static const llvm::MCProcResourceDesc GFX12SpeedModelProcResources[] = { |
| 2672 | {"InvalidUnit" , 0, 0, 0, 0}, |
| 2673 | {"HWBranch" , 1, 0, 1, nullptr}, // #1 |
| 2674 | {"HWExport" , 1, 0, 1, nullptr}, // #2 |
| 2675 | {"HWLGKM" , 1, 0, 1, nullptr}, // #3 |
| 2676 | {"HWRC" , 1, 0, 1, nullptr}, // #4 |
| 2677 | {"HWSALU" , 1, 0, 1, nullptr}, // #5 |
| 2678 | {"HWVALU" , 1, 0, 1, nullptr}, // #6 |
| 2679 | {"HWVMEM" , 1, 0, 1, nullptr}, // #7 |
| 2680 | }; |
| 2681 | |
| 2682 | static const unsigned GFX1250SpeedModelProcResourceSubUnits[] = { |
| 2683 | 0, // Invalid |
| 2684 | }; |
| 2685 | |
| 2686 | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
| 2687 | static const llvm::MCProcResourceDesc GFX1250SpeedModelProcResources[] = { |
| 2688 | {"InvalidUnit" , 0, 0, 0, 0}, |
| 2689 | {"HWBranch" , 1, 0, 1, nullptr}, // #1 |
| 2690 | {"HWExport" , 1, 0, 1, nullptr}, // #2 |
| 2691 | {"HWLGKM" , 1, 0, 1, nullptr}, // #3 |
| 2692 | {"HWRC" , 1, 0, 1, nullptr}, // #4 |
| 2693 | {"HWSALU" , 1, 0, 1, nullptr}, // #5 |
| 2694 | {"HWTransVALU" , 1, 0, 1, nullptr}, // #6 |
| 2695 | {"HWVALU" , 1, 0, 1, nullptr}, // #7 |
| 2696 | {"HWVMEM" , 1, 0, 1, nullptr}, // #8 |
| 2697 | {"HWXDL" , 1, 0, 0, nullptr}, // #9 |
| 2698 | }; |
| 2699 | |
| 2700 | static const unsigned GFX1251SpeedModelProcResourceSubUnits[] = { |
| 2701 | 0, // Invalid |
| 2702 | }; |
| 2703 | |
| 2704 | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
| 2705 | static const llvm::MCProcResourceDesc GFX1251SpeedModelProcResources[] = { |
| 2706 | {"InvalidUnit" , 0, 0, 0, 0}, |
| 2707 | {"HWBranch" , 1, 0, 1, nullptr}, // #1 |
| 2708 | {"HWExport" , 1, 0, 1, nullptr}, // #2 |
| 2709 | {"HWLGKM" , 1, 0, 1, nullptr}, // #3 |
| 2710 | {"HWRC" , 1, 0, 1, nullptr}, // #4 |
| 2711 | {"HWSALU" , 1, 0, 1, nullptr}, // #5 |
| 2712 | {"HWTransVALU" , 1, 0, 1, nullptr}, // #6 |
| 2713 | {"HWVALU" , 1, 0, 1, nullptr}, // #7 |
| 2714 | {"HWVMEM" , 1, 0, 1, nullptr}, // #8 |
| 2715 | {"HWXDL" , 1, 0, 0, nullptr}, // #9 |
| 2716 | }; |
| 2717 | |
| 2718 | static const unsigned SIFullSpeedModelProcResourceSubUnits[] = { |
| 2719 | 0, // Invalid |
| 2720 | }; |
| 2721 | |
| 2722 | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
| 2723 | static const llvm::MCProcResourceDesc SIFullSpeedModelProcResources[] = { |
| 2724 | {"InvalidUnit" , 0, 0, 0, 0}, |
| 2725 | {"HWBranch" , 1, 0, 1, nullptr}, // #1 |
| 2726 | {"HWExport" , 1, 0, 1, nullptr}, // #2 |
| 2727 | {"HWLGKM" , 1, 0, 1, nullptr}, // #3 |
| 2728 | {"HWSALU" , 1, 0, 1, nullptr}, // #4 |
| 2729 | {"HWVALU" , 1, 0, 1, nullptr}, // #5 |
| 2730 | {"HWVMEM" , 1, 0, 1, nullptr}, // #6 |
| 2731 | {"HWXDL" , 1, 0, 0, nullptr}, // #7 |
| 2732 | }; |
| 2733 | |
| 2734 | static const unsigned SIQuarterSpeedModelProcResourceSubUnits[] = { |
| 2735 | 0, // Invalid |
| 2736 | }; |
| 2737 | |
| 2738 | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
| 2739 | static const llvm::MCProcResourceDesc SIQuarterSpeedModelProcResources[] = { |
| 2740 | {"InvalidUnit" , 0, 0, 0, 0}, |
| 2741 | {"HWBranch" , 1, 0, 1, nullptr}, // #1 |
| 2742 | {"HWExport" , 1, 0, 1, nullptr}, // #2 |
| 2743 | {"HWLGKM" , 1, 0, 1, nullptr}, // #3 |
| 2744 | {"HWSALU" , 1, 0, 1, nullptr}, // #4 |
| 2745 | {"HWVALU" , 1, 0, 1, nullptr}, // #5 |
| 2746 | {"HWVMEM" , 1, 0, 1, nullptr}, // #6 |
| 2747 | {"HWXDL" , 1, 0, 0, nullptr}, // #7 |
| 2748 | }; |
| 2749 | |
| 2750 | static const unsigned SIDPGFX942FullSpeedModelProcResourceSubUnits[] = { |
| 2751 | 0, // Invalid |
| 2752 | }; |
| 2753 | |
| 2754 | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
| 2755 | static const llvm::MCProcResourceDesc SIDPGFX942FullSpeedModelProcResources[] = { |
| 2756 | {"InvalidUnit" , 0, 0, 0, 0}, |
| 2757 | {"HWBranch" , 1, 0, 1, nullptr}, // #1 |
| 2758 | {"HWExport" , 1, 0, 1, nullptr}, // #2 |
| 2759 | {"HWLGKM" , 1, 0, 1, nullptr}, // #3 |
| 2760 | {"HWSALU" , 1, 0, 1, nullptr}, // #4 |
| 2761 | {"HWVALU" , 1, 0, 1, nullptr}, // #5 |
| 2762 | {"HWVMEM" , 1, 0, 1, nullptr}, // #6 |
| 2763 | {"HWXDL" , 1, 0, 0, nullptr}, // #7 |
| 2764 | }; |
| 2765 | |
| 2766 | static const unsigned SIDPFullSpeedModelProcResourceSubUnits[] = { |
| 2767 | 0, // Invalid |
| 2768 | }; |
| 2769 | |
| 2770 | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
| 2771 | static const llvm::MCProcResourceDesc SIDPFullSpeedModelProcResources[] = { |
| 2772 | {"InvalidUnit" , 0, 0, 0, 0}, |
| 2773 | {"HWBranch" , 1, 0, 1, nullptr}, // #1 |
| 2774 | {"HWExport" , 1, 0, 1, nullptr}, // #2 |
| 2775 | {"HWLGKM" , 1, 0, 1, nullptr}, // #3 |
| 2776 | {"HWSALU" , 1, 0, 1, nullptr}, // #4 |
| 2777 | {"HWVALU" , 1, 0, 1, nullptr}, // #5 |
| 2778 | {"HWVMEM" , 1, 0, 1, nullptr}, // #6 |
| 2779 | {"HWXDL" , 1, 0, 0, nullptr}, // #7 |
| 2780 | }; |
| 2781 | |
| 2782 | static const unsigned SIDPGFX950FullSpeedModelProcResourceSubUnits[] = { |
| 2783 | 0, // Invalid |
| 2784 | }; |
| 2785 | |
| 2786 | // {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin} |
| 2787 | static const llvm::MCProcResourceDesc SIDPGFX950FullSpeedModelProcResources[] = { |
| 2788 | {"InvalidUnit" , 0, 0, 0, 0}, |
| 2789 | {"HWBranch" , 1, 0, 1, nullptr}, // #1 |
| 2790 | {"HWExport" , 1, 0, 1, nullptr}, // #2 |
| 2791 | {"HWLGKM" , 1, 0, 1, nullptr}, // #3 |
| 2792 | {"HWSALU" , 1, 0, 1, nullptr}, // #4 |
| 2793 | {"HWVALU" , 1, 0, 1, nullptr}, // #5 |
| 2794 | {"HWVMEM" , 1, 0, 1, nullptr}, // #6 |
| 2795 | {"HWXDL" , 1, 0, 0, nullptr}, // #7 |
| 2796 | }; |
| 2797 | |
| 2798 | extern const llvm::MCSchedModel AMDGPUSchedModels[] = { |
| 2799 | { // NoSchedModel |
| 2800 | MCSchedModel::DefaultIssueWidth, |
| 2801 | MCSchedModel::DefaultMicroOpBufferSize, |
| 2802 | MCSchedModel::DefaultLoopMicroOpBufferSize, |
| 2803 | MCSchedModel::DefaultLoadLatency, |
| 2804 | MCSchedModel::DefaultHighLatency, |
| 2805 | MCSchedModel::DefaultMispredictPenalty, |
| 2806 | false, // PostRAScheduler |
| 2807 | false, // CompleteModel |
| 2808 | false, // EnableIntervals |
| 2809 | 0, // Processor ID |
| 2810 | nullptr, nullptr, 0, 0, // No instruction-level machine model. |
| 2811 | DBGVAL_OR_NULLPTR(&AMDGPUSchedClassNames), // SchedClassNames |
| 2812 | nullptr, // No Itinerary |
| 2813 | nullptr // No extra processor descriptor |
| 2814 | }, |
| 2815 | { // GFX10SpeedModel |
| 2816 | 1, // IssueWidth |
| 2817 | 1, // MicroOpBufferSize |
| 2818 | MCSchedModel::DefaultLoopMicroOpBufferSize, |
| 2819 | MCSchedModel::DefaultLoadLatency, |
| 2820 | MCSchedModel::DefaultHighLatency, |
| 2821 | 20, // MispredictPenalty |
| 2822 | true, // PostRAScheduler |
| 2823 | true, // CompleteModel |
| 2824 | false, // EnableIntervals |
| 2825 | 1, // Processor ID |
| 2826 | GFX10SpeedModelProcResources, |
| 2827 | GFX10SpeedModelSchedClasses, |
| 2828 | 9, |
| 2829 | 91, |
| 2830 | DBGVAL_OR_NULLPTR(&AMDGPUSchedClassNames), // SchedClassNames |
| 2831 | nullptr, // No Itinerary |
| 2832 | nullptr // No extra processor descriptor |
| 2833 | }, |
| 2834 | { // GFX11SpeedModel |
| 2835 | 1, // IssueWidth |
| 2836 | 1, // MicroOpBufferSize |
| 2837 | MCSchedModel::DefaultLoopMicroOpBufferSize, |
| 2838 | MCSchedModel::DefaultLoadLatency, |
| 2839 | MCSchedModel::DefaultHighLatency, |
| 2840 | 20, // MispredictPenalty |
| 2841 | true, // PostRAScheduler |
| 2842 | true, // CompleteModel |
| 2843 | false, // EnableIntervals |
| 2844 | 2, // Processor ID |
| 2845 | GFX11SpeedModelProcResources, |
| 2846 | GFX11SpeedModelSchedClasses, |
| 2847 | 9, |
| 2848 | 91, |
| 2849 | DBGVAL_OR_NULLPTR(&AMDGPUSchedClassNames), // SchedClassNames |
| 2850 | nullptr, // No Itinerary |
| 2851 | nullptr // No extra processor descriptor |
| 2852 | }, |
| 2853 | { // GFX125xGenericSpeedModel |
| 2854 | 1, // IssueWidth |
| 2855 | 1, // MicroOpBufferSize |
| 2856 | MCSchedModel::DefaultLoopMicroOpBufferSize, |
| 2857 | MCSchedModel::DefaultLoadLatency, |
| 2858 | MCSchedModel::DefaultHighLatency, |
| 2859 | 20, // MispredictPenalty |
| 2860 | true, // PostRAScheduler |
| 2861 | true, // CompleteModel |
| 2862 | false, // EnableIntervals |
| 2863 | 3, // Processor ID |
| 2864 | GFX125xGenericSpeedModelProcResources, |
| 2865 | GFX125xGenericSpeedModelSchedClasses, |
| 2866 | 10, |
| 2867 | 91, |
| 2868 | DBGVAL_OR_NULLPTR(&AMDGPUSchedClassNames), // SchedClassNames |
| 2869 | nullptr, // No Itinerary |
| 2870 | nullptr // No extra processor descriptor |
| 2871 | }, |
| 2872 | { // GFX12SpeedModel |
| 2873 | 1, // IssueWidth |
| 2874 | 1, // MicroOpBufferSize |
| 2875 | MCSchedModel::DefaultLoopMicroOpBufferSize, |
| 2876 | MCSchedModel::DefaultLoadLatency, |
| 2877 | MCSchedModel::DefaultHighLatency, |
| 2878 | 20, // MispredictPenalty |
| 2879 | true, // PostRAScheduler |
| 2880 | true, // CompleteModel |
| 2881 | false, // EnableIntervals |
| 2882 | 4, // Processor ID |
| 2883 | GFX12SpeedModelProcResources, |
| 2884 | GFX12SpeedModelSchedClasses, |
| 2885 | 8, |
| 2886 | 91, |
| 2887 | DBGVAL_OR_NULLPTR(&AMDGPUSchedClassNames), // SchedClassNames |
| 2888 | nullptr, // No Itinerary |
| 2889 | nullptr // No extra processor descriptor |
| 2890 | }, |
| 2891 | { // GFX1250SpeedModel |
| 2892 | 1, // IssueWidth |
| 2893 | 1, // MicroOpBufferSize |
| 2894 | MCSchedModel::DefaultLoopMicroOpBufferSize, |
| 2895 | MCSchedModel::DefaultLoadLatency, |
| 2896 | MCSchedModel::DefaultHighLatency, |
| 2897 | 20, // MispredictPenalty |
| 2898 | true, // PostRAScheduler |
| 2899 | true, // CompleteModel |
| 2900 | false, // EnableIntervals |
| 2901 | 5, // Processor ID |
| 2902 | GFX1250SpeedModelProcResources, |
| 2903 | GFX1250SpeedModelSchedClasses, |
| 2904 | 10, |
| 2905 | 91, |
| 2906 | DBGVAL_OR_NULLPTR(&AMDGPUSchedClassNames), // SchedClassNames |
| 2907 | nullptr, // No Itinerary |
| 2908 | nullptr // No extra processor descriptor |
| 2909 | }, |
| 2910 | { // GFX1251SpeedModel |
| 2911 | 1, // IssueWidth |
| 2912 | 1, // MicroOpBufferSize |
| 2913 | MCSchedModel::DefaultLoopMicroOpBufferSize, |
| 2914 | MCSchedModel::DefaultLoadLatency, |
| 2915 | MCSchedModel::DefaultHighLatency, |
| 2916 | 20, // MispredictPenalty |
| 2917 | true, // PostRAScheduler |
| 2918 | true, // CompleteModel |
| 2919 | false, // EnableIntervals |
| 2920 | 6, // Processor ID |
| 2921 | GFX1251SpeedModelProcResources, |
| 2922 | GFX1251SpeedModelSchedClasses, |
| 2923 | 10, |
| 2924 | 91, |
| 2925 | DBGVAL_OR_NULLPTR(&AMDGPUSchedClassNames), // SchedClassNames |
| 2926 | nullptr, // No Itinerary |
| 2927 | nullptr // No extra processor descriptor |
| 2928 | }, |
| 2929 | { // SIFullSpeedModel |
| 2930 | 1, // IssueWidth |
| 2931 | 1, // MicroOpBufferSize |
| 2932 | MCSchedModel::DefaultLoopMicroOpBufferSize, |
| 2933 | MCSchedModel::DefaultLoadLatency, |
| 2934 | MCSchedModel::DefaultHighLatency, |
| 2935 | 20, // MispredictPenalty |
| 2936 | true, // PostRAScheduler |
| 2937 | true, // CompleteModel |
| 2938 | false, // EnableIntervals |
| 2939 | 7, // Processor ID |
| 2940 | SIFullSpeedModelProcResources, |
| 2941 | SIFullSpeedModelSchedClasses, |
| 2942 | 8, |
| 2943 | 91, |
| 2944 | DBGVAL_OR_NULLPTR(&AMDGPUSchedClassNames), // SchedClassNames |
| 2945 | nullptr, // No Itinerary |
| 2946 | nullptr // No extra processor descriptor |
| 2947 | }, |
| 2948 | { // SIQuarterSpeedModel |
| 2949 | 1, // IssueWidth |
| 2950 | 1, // MicroOpBufferSize |
| 2951 | MCSchedModel::DefaultLoopMicroOpBufferSize, |
| 2952 | MCSchedModel::DefaultLoadLatency, |
| 2953 | MCSchedModel::DefaultHighLatency, |
| 2954 | 20, // MispredictPenalty |
| 2955 | true, // PostRAScheduler |
| 2956 | true, // CompleteModel |
| 2957 | false, // EnableIntervals |
| 2958 | 8, // Processor ID |
| 2959 | SIQuarterSpeedModelProcResources, |
| 2960 | SIQuarterSpeedModelSchedClasses, |
| 2961 | 8, |
| 2962 | 91, |
| 2963 | DBGVAL_OR_NULLPTR(&AMDGPUSchedClassNames), // SchedClassNames |
| 2964 | nullptr, // No Itinerary |
| 2965 | nullptr // No extra processor descriptor |
| 2966 | }, |
| 2967 | { // SIDPGFX942FullSpeedModel |
| 2968 | 1, // IssueWidth |
| 2969 | 1, // MicroOpBufferSize |
| 2970 | MCSchedModel::DefaultLoopMicroOpBufferSize, |
| 2971 | MCSchedModel::DefaultLoadLatency, |
| 2972 | MCSchedModel::DefaultHighLatency, |
| 2973 | 20, // MispredictPenalty |
| 2974 | true, // PostRAScheduler |
| 2975 | true, // CompleteModel |
| 2976 | false, // EnableIntervals |
| 2977 | 9, // Processor ID |
| 2978 | SIDPGFX942FullSpeedModelProcResources, |
| 2979 | SIDPGFX942FullSpeedModelSchedClasses, |
| 2980 | 8, |
| 2981 | 91, |
| 2982 | DBGVAL_OR_NULLPTR(&AMDGPUSchedClassNames), // SchedClassNames |
| 2983 | nullptr, // No Itinerary |
| 2984 | nullptr // No extra processor descriptor |
| 2985 | }, |
| 2986 | { // SIDPFullSpeedModel |
| 2987 | 1, // IssueWidth |
| 2988 | 1, // MicroOpBufferSize |
| 2989 | MCSchedModel::DefaultLoopMicroOpBufferSize, |
| 2990 | MCSchedModel::DefaultLoadLatency, |
| 2991 | MCSchedModel::DefaultHighLatency, |
| 2992 | 20, // MispredictPenalty |
| 2993 | true, // PostRAScheduler |
| 2994 | true, // CompleteModel |
| 2995 | false, // EnableIntervals |
| 2996 | 10, // Processor ID |
| 2997 | SIDPFullSpeedModelProcResources, |
| 2998 | SIDPFullSpeedModelSchedClasses, |
| 2999 | 8, |
| 3000 | 91, |
| 3001 | DBGVAL_OR_NULLPTR(&AMDGPUSchedClassNames), // SchedClassNames |
| 3002 | nullptr, // No Itinerary |
| 3003 | nullptr // No extra processor descriptor |
| 3004 | }, |
| 3005 | { // SIDPGFX950FullSpeedModel |
| 3006 | 1, // IssueWidth |
| 3007 | 1, // MicroOpBufferSize |
| 3008 | MCSchedModel::DefaultLoopMicroOpBufferSize, |
| 3009 | MCSchedModel::DefaultLoadLatency, |
| 3010 | MCSchedModel::DefaultHighLatency, |
| 3011 | 20, // MispredictPenalty |
| 3012 | true, // PostRAScheduler |
| 3013 | true, // CompleteModel |
| 3014 | false, // EnableIntervals |
| 3015 | 11, // Processor ID |
| 3016 | SIDPGFX950FullSpeedModelProcResources, |
| 3017 | SIDPGFX950FullSpeedModelSchedClasses, |
| 3018 | 8, |
| 3019 | 91, |
| 3020 | DBGVAL_OR_NULLPTR(&AMDGPUSchedClassNames), // SchedClassNames |
| 3021 | nullptr, // No Itinerary |
| 3022 | nullptr // No extra processor descriptor |
| 3023 | }, |
| 3024 | }; |
| 3025 | |
| 3026 | #undef DBGFIELD |
| 3027 | |
| 3028 | #undef DBGVAL_OR_NULLPTR |
| 3029 | |
| 3030 | static constexpr size_t AMDGPUCPUAliasArraySize = sizeof(std::array<SubtargetSubTypeAliasKV, 18>); |
| 3031 | // Sorted (by key) array of values for CPU subtype. |
| 3032 | extern const llvm::SubtargetSubTypeKVStorage< 64, 18, 698> AMDGPUSubTypeKVStorage = { |
| 3033 | { |
| 3034 | { sizeof(SubtargetSubTypeKV) * 64 + AMDGPUCPUAliasArraySize + 22, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 }, |
| 3035 | { sizeof(SubtargetSubTypeKV) * 63 + AMDGPUCPUAliasArraySize + 30, { { { 0x0ULL, 0x200000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 0 }, |
| 3036 | { sizeof(SubtargetSubTypeKV) * 62 + AMDGPUCPUAliasArraySize + 42, { { { 0x1000200000000000ULL, 0x40000000100000ULL, 0x20098401000020ULL, 0x100080200108fc02ULL, 0xc040000000680ULL, 0x8ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 }, |
| 3037 | { sizeof(SubtargetSubTypeKV) * 61 + AMDGPUCPUAliasArraySize + 58, { { { 0x1000300000000000ULL, 0x13980ULL, 0x80080000001a0ULL, 0x802000005c01ULL, 0x8000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 }, |
| 3038 | { sizeof(SubtargetSubTypeKV) * 60 + AMDGPUCPUAliasArraySize + 74, { { { 0x1000200000000000ULL, 0x40000000100000ULL, 0x20098401000020ULL, 0x100000200108fc02ULL, 0xc040000000680ULL, 0x8ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 }, |
| 3039 | { sizeof(SubtargetSubTypeKV) * 59 + AMDGPUCPUAliasArraySize + 82, { { { 0x1000200000000000ULL, 0x40000000113980ULL, 0x20098401000020ULL, 0x100000200108fc02ULL, 0xc040000000680ULL, 0x8ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 }, |
| 3040 | { sizeof(SubtargetSubTypeKV) * 58 + AMDGPUCPUAliasArraySize + 90, { { { 0x1000200000000000ULL, 0x40000000113980ULL, 0x20098401000020ULL, 0x100000200108fc02ULL, 0xc040000000680ULL, 0x8ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 }, |
| 3041 | { sizeof(SubtargetSubTypeKV) * 57 + AMDGPUCPUAliasArraySize + 98, { { { 0x1000300000000000ULL, 0x40000000100000ULL, 0x28098401000020ULL, 0x100000200108fc02ULL, 0xc040000000680ULL, 0x8ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 }, |
| 3042 | { sizeof(SubtargetSubTypeKV) * 56 + AMDGPUCPUAliasArraySize + 106, { { { 0x1000300000000000ULL, 0x13980ULL, 0x80080000001a0ULL, 0x2000005c01ULL, 0x8000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 }, |
| 3043 | { sizeof(SubtargetSubTypeKV) * 55 + AMDGPUCPUAliasArraySize + 114, { { { 0x1000300000000000ULL, 0x13980ULL, 0x80080000001a0ULL, 0x2000005c01ULL, 0x8000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 }, |
| 3044 | { sizeof(SubtargetSubTypeKV) * 54 + AMDGPUCPUAliasArraySize + 122, { { { 0x1000300000000000ULL, 0x13980ULL, 0x80080000001a0ULL, 0x2000005c01ULL, 0x8000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 }, |
| 3045 | { sizeof(SubtargetSubTypeKV) * 53 + AMDGPUCPUAliasArraySize + 130, { { { 0x1000300000000000ULL, 0x13980ULL, 0x80080000001a0ULL, 0x2000005c01ULL, 0x8000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 }, |
| 3046 | { sizeof(SubtargetSubTypeKV) * 52 + AMDGPUCPUAliasArraySize + 138, { { { 0x1000300000000000ULL, 0x13980ULL, 0x80080000001a0ULL, 0x2000005c01ULL, 0x8000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 }, |
| 3047 | { sizeof(SubtargetSubTypeKV) * 51 + AMDGPUCPUAliasArraySize + 146, { { { 0x1000300000000000ULL, 0x13980ULL, 0x80080000001a0ULL, 0x2000005c01ULL, 0x8000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 }, |
| 3048 | { sizeof(SubtargetSubTypeKV) * 50 + AMDGPUCPUAliasArraySize + 154, { { { 0x1000300000000000ULL, 0x13980ULL, 0x80080000001a0ULL, 0x2000005c01ULL, 0x8000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 1 }, |
| 3049 | { sizeof(SubtargetSubTypeKV) * 49 + AMDGPUCPUAliasArraySize + 162, { { { 0x1808200600020000ULL, 0x40200007e002ULL, 0x8050000a00ULL, 0x4900050a05cc8ULL, 0x108000000008001ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3050 | { sizeof(SubtargetSubTypeKV) * 48 + AMDGPUCPUAliasArraySize + 178, { { { 0x1800200600020000ULL, 0x40000005e808ULL, 0x4408040000200ULL, 0xb08050005c08ULL, 0x208018000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3051 | { sizeof(SubtargetSubTypeKV) * 47 + AMDGPUCPUAliasArraySize + 192, { { { 0x1800200600020020ULL, 0x40000005e808ULL, 0x4408040000200ULL, 0x108050005c08ULL, 0x208018000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3052 | { sizeof(SubtargetSubTypeKV) * 46 + AMDGPUCPUAliasArraySize + 200, { { { 0x1800200600020020ULL, 0x40000005e808ULL, 0x4408040000200ULL, 0x108050005c08ULL, 0x208010000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3053 | { sizeof(SubtargetSubTypeKV) * 45 + AMDGPUCPUAliasArraySize + 208, { { { 0x1800200600020000ULL, 0x40000005e808ULL, 0x4408040000200ULL, 0x108050005c08ULL, 0x208018000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3054 | { sizeof(SubtargetSubTypeKV) * 44 + AMDGPUCPUAliasArraySize + 216, { { { 0x1800200600020000ULL, 0x40000005e808ULL, 0x4408040000200ULL, 0x108050005c08ULL, 0x208010000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3055 | { sizeof(SubtargetSubTypeKV) * 43 + AMDGPUCPUAliasArraySize + 224, { { { 0x1800200600020000ULL, 0x40000005e80aULL, 0x8040000200ULL, 0x4301050005c08ULL, 0x208000000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3056 | { sizeof(SubtargetSubTypeKV) * 42 + AMDGPUCPUAliasArraySize + 232, { { { 0x1800200600020020ULL, 0x40000005e80aULL, 0x8040000200ULL, 0x4301050005c08ULL, 0x208000000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3057 | { sizeof(SubtargetSubTypeKV) * 41 + AMDGPUCPUAliasArraySize + 240, { { { 0x1800200600020000ULL, 0x40000005e80aULL, 0x8040000200ULL, 0x4301050005c08ULL, 0x208000000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3058 | { sizeof(SubtargetSubTypeKV) * 40 + AMDGPUCPUAliasArraySize + 248, { { { 0x1800200600020000ULL, 0x40000005e80aULL, 0x8040000200ULL, 0x4300050005c08ULL, 0x208000000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3059 | { sizeof(SubtargetSubTypeKV) * 39 + AMDGPUCPUAliasArraySize + 256, { { { 0x1800200600020000ULL, 0x40000005e80aULL, 0x8040000200ULL, 0x4300050005c08ULL, 0x208000000008000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3060 | { sizeof(SubtargetSubTypeKV) * 38 + AMDGPUCPUAliasArraySize + 264, { { { 0x1808200600020000ULL, 0x40200007e002ULL, 0x8050000a00ULL, 0x4100050a05cc8ULL, 0x108000000008001ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3061 | { sizeof(SubtargetSubTypeKV) * 37 + AMDGPUCPUAliasArraySize + 272, { { { 0x1808200600020000ULL, 0x40200007e002ULL, 0x8050000a00ULL, 0x4100050a05cc8ULL, 0x108000000008001ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3062 | { sizeof(SubtargetSubTypeKV) * 36 + AMDGPUCPUAliasArraySize + 280, { { { 0x1808200600020000ULL, 0x40200007e002ULL, 0x8050000a00ULL, 0x4100050a05cc8ULL, 0x108000000008001ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 2 }, |
| 3063 | { sizeof(SubtargetSubTypeKV) * 35 + AMDGPUCPUAliasArraySize + 288, { { { 0x1c8b679f95ee429cULL, 0xa01c1a080406012ULL, 0x58026a002121000ULL, 0x7d30514a2013cULL, 0x941830000dc57104ULL, 0x4ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 3 }, |
| 3064 | { sizeof(SubtargetSubTypeKV) * 34 + AMDGPUCPUAliasArraySize + 304, { { { 0x1b4c381e15060820ULL, 0x100040202007e012ULL, 0x218108054001000ULL, 0x6960050a05c08ULL, 0x2108000000294111ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 4 }, |
| 3065 | { sizeof(SubtargetSubTypeKV) * 33 + AMDGPUCPUAliasArraySize + 318, { { { 0x1b4c381e15060820ULL, 0x100040202007e012ULL, 0x218108054001000ULL, 0x6160050a05c08ULL, 0x2108000000294111ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 4 }, |
| 3066 | { sizeof(SubtargetSubTypeKV) * 32 + AMDGPUCPUAliasArraySize + 326, { { { 0x1b4c381e15060820ULL, 0x100040202007e012ULL, 0x218108054001000ULL, 0x6160050a05c08ULL, 0x2108000000294111ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 4 }, |
| 3067 | { sizeof(SubtargetSubTypeKV) * 31 + AMDGPUCPUAliasArraySize + 334, { { { 0x1fcf679f95ee429cULL, 0xa01c1a080406012ULL, 0x58036a002101000ULL, 0x7570514a21d3cULL, 0x9c1930000d857117ULL, 0x4ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 5 }, |
| 3068 | { sizeof(SubtargetSubTypeKV) * 30 + AMDGPUCPUAliasArraySize + 342, { { { 0x1fcf679f95ee429cULL, 0xa01c1a080406012ULL, 0x58036a002301000ULL, 0x7570514a31d3cULL, 0x941930000d857117ULL, 0x4ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 5 }, |
| 3069 | { sizeof(SubtargetSubTypeKV) * 29 + AMDGPUCPUAliasArraySize + 357, { { { 0x3fcf679f95ee429cULL, 0x2a01c1a080406012ULL, 0x58036a002521000ULL, 0x757053ca21d3cULL, 0x9c1930100d855117ULL, 0x4ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 6 }, |
| 3070 | { sizeof(SubtargetSubTypeKV) * 28 + AMDGPUCPUAliasArraySize + 365, { { { 0x17cd479f952e2028ULL, 0xa014122c0006002ULL, 0x108012104000ULL, 0x6870150805c00ULL, 0x8000001818114ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 4 }, |
| 3071 | { sizeof(SubtargetSubTypeKV) * 27 + AMDGPUCPUAliasArraySize + 379, { { { 0x17cd479f952e2028ULL, 0xa014122c0006002ULL, 0x108012104000ULL, 0x6070150805c00ULL, 0x8000001818114ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 4 }, |
| 3072 | { sizeof(SubtargetSubTypeKV) * 26 + AMDGPUCPUAliasArraySize + 387, { { { 0x0ULL, 0x100000000000ULL, 0x8008000000ULL, 0x0ULL, 0x20000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 7 }, |
| 3073 | { sizeof(SubtargetSubTypeKV) * 25 + AMDGPUCPUAliasArraySize + 394, { { { 0x0ULL, 0x0ULL, 0x8000000000ULL, 0x0ULL, 0x20000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3074 | { sizeof(SubtargetSubTypeKV) * 24 + AMDGPUCPUAliasArraySize + 401, { { { 0x0ULL, 0x0ULL, 0x8000000000ULL, 0x0ULL, 0x20000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3075 | { sizeof(SubtargetSubTypeKV) * 23 + AMDGPUCPUAliasArraySize + 408, { { { 0x0ULL, 0x0ULL, 0x8000000000ULL, 0x0ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3076 | { sizeof(SubtargetSubTypeKV) * 22 + AMDGPUCPUAliasArraySize + 415, { { { 0x0ULL, 0x100000000000ULL, 0x8008000000ULL, 0x0ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 7 }, |
| 3077 | { sizeof(SubtargetSubTypeKV) * 21 + AMDGPUCPUAliasArraySize + 422, { { { 0x0ULL, 0x100000000000ULL, 0x4000000000ULL, 0x0ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3078 | { sizeof(SubtargetSubTypeKV) * 20 + AMDGPUCPUAliasArraySize + 429, { { { 0x0ULL, 0x0ULL, 0x4000000000ULL, 0x0ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3079 | { sizeof(SubtargetSubTypeKV) * 19 + AMDGPUCPUAliasArraySize + 436, { { { 0x0ULL, 0x0ULL, 0x8000000000ULL, 0x0ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3080 | { sizeof(SubtargetSubTypeKV) * 18 + AMDGPUCPUAliasArraySize + 443, { { { 0x0ULL, 0x0ULL, 0x4000000000ULL, 0x0ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3081 | { sizeof(SubtargetSubTypeKV) * 17 + AMDGPUCPUAliasArraySize + 450, { { { 0x0ULL, 0x100000000000ULL, 0x8008000000ULL, 0x0ULL, 0x40000800000000ULL, 0x8ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3082 | { sizeof(SubtargetSubTypeKV) * 16 + AMDGPUCPUAliasArraySize + 457, { { { 0x0ULL, 0x0ULL, 0x8000000000ULL, 0x800000000000000ULL, 0x40000800000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3083 | { sizeof(SubtargetSubTypeKV) * 15 + AMDGPUCPUAliasArraySize + 464, { { { 0x0ULL, 0x0ULL, 0x8000000000ULL, 0x0ULL, 0x40000800000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3084 | { sizeof(SubtargetSubTypeKV) * 14 + AMDGPUCPUAliasArraySize + 471, { { { 0x0ULL, 0x0ULL, 0x8000000000ULL, 0x800000000000000ULL, 0x40000800000000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3085 | { sizeof(SubtargetSubTypeKV) * 13 + AMDGPUCPUAliasArraySize + 478, { { { 0x0ULL, 0x0ULL, 0x40a0000000ULL, 0x0ULL, 0x40000000000000ULL, 0x8ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3086 | { sizeof(SubtargetSubTypeKV) * 12 + AMDGPUCPUAliasArraySize + 485, { { { 0x3000201f91028800ULL, 0x2c00c00000013f80ULL, 0x4000a2a000050008ULL, 0xc00812000008ULL, 0x100002040000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 9 }, |
| 3087 | { sizeof(SubtargetSubTypeKV) * 11 + AMDGPUCPUAliasArraySize + 500, { { { 0x4000000000800ULL, 0x20100000ULL, 0x8020008060000009ULL, 0x802000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3088 | { sizeof(SubtargetSubTypeKV) * 10 + AMDGPUCPUAliasArraySize + 513, { { { 0x4000000000800ULL, 0x20100000ULL, 0x8060008060000009ULL, 0x2000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3089 | { sizeof(SubtargetSubTypeKV) * 9 + AMDGPUCPUAliasArraySize + 520, { { { 0x4000000000800ULL, 0x20100000ULL, 0x8060008060000009ULL, 0x2000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3090 | { sizeof(SubtargetSubTypeKV) * 8 + AMDGPUCPUAliasArraySize + 527, { { { 0x4000000000800ULL, 0x400000020100000ULL, 0x8020008060000009ULL, 0x2000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3091 | { sizeof(SubtargetSubTypeKV) * 7 + AMDGPUCPUAliasArraySize + 534, { { { 0x1004000000000800ULL, 0x400000020112180ULL, 0x8020008068000009ULL, 0x2000000000ULL, 0x40000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3092 | { sizeof(SubtargetSubTypeKV) * 6 + AMDGPUCPUAliasArraySize + 541, { { { 0x1004000202000800ULL, 0x400000020113f80ULL, 0x8021808068000009ULL, 0x800000000ULL, 0x40000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3093 | { sizeof(SubtargetSubTypeKV) * 5 + AMDGPUCPUAliasArraySize + 548, { { { 0x4000000000800ULL, 0x20100000ULL, 0x8060008060000009ULL, 0x2000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3094 | { sizeof(SubtargetSubTypeKV) * 4 + AMDGPUCPUAliasArraySize + 555, { { { 0x3004200781000800ULL, 0x2c00800000013f80ULL, 0x402082a040010008ULL, 0x400812000000ULL, 0x2040000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 10 }, |
| 3095 | { sizeof(SubtargetSubTypeKV) * 3 + AMDGPUCPUAliasArraySize + 562, { { { 0x4000000000800ULL, 0x20100000ULL, 0x8060008060000009ULL, 0x2000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 8 }, |
| 3096 | { sizeof(SubtargetSubTypeKV) * 2 + AMDGPUCPUAliasArraySize + 569, { { { 0x3030201f91028800ULL, 0x2c00c22000013f80ULL, 0x4000a2a000050008ULL, 0x400812000008ULL, 0x100002040000ULL, 0x2ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 9 }, |
| 3097 | { sizeof(SubtargetSubTypeKV) * 1 + AMDGPUCPUAliasArraySize + 576, { { { 0x301060df95029000ULL, 0x2c00c278000d3f80ULL, 0x4000a2a0000d0008ULL, 0x410812800008ULL, 0x100002040000ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, 11 }, |
| 3098 | }, |
| 3099 | { { |
| 3100 | { sizeof(SubtargetSubTypeAliasKV) * 18 + 1, 45 }, |
| 3101 | { sizeof(SubtargetSubTypeAliasKV) * 17 + 9, 47 }, |
| 3102 | { sizeof(SubtargetSubTypeAliasKV) * 16 + 17, 49 }, |
| 3103 | { sizeof(SubtargetSubTypeAliasKV) * 15 + 583, 40 }, |
| 3104 | { sizeof(SubtargetSubTypeAliasKV) * 14 + 590, 42 }, |
| 3105 | { sizeof(SubtargetSubTypeAliasKV) * 13 + 597, 48 }, |
| 3106 | { sizeof(SubtargetSubTypeAliasKV) * 12 + 605, 44 }, |
| 3107 | { sizeof(SubtargetSubTypeAliasKV) * 11 + 612, 41 }, |
| 3108 | { sizeof(SubtargetSubTypeAliasKV) * 10 + 619, 44 }, |
| 3109 | { sizeof(SubtargetSubTypeAliasKV) * 9 + 627, 40 }, |
| 3110 | { sizeof(SubtargetSubTypeAliasKV) * 8 + 633, 39 }, |
| 3111 | { sizeof(SubtargetSubTypeAliasKV) * 7 + 642, 49 }, |
| 3112 | { sizeof(SubtargetSubTypeAliasKV) * 6 + 652, 49 }, |
| 3113 | { sizeof(SubtargetSubTypeAliasKV) * 5 + 662, 51 }, |
| 3114 | { sizeof(SubtargetSubTypeAliasKV) * 4 + 669, 38 }, |
| 3115 | { sizeof(SubtargetSubTypeAliasKV) * 3 + 676, 48 }, |
| 3116 | { sizeof(SubtargetSubTypeAliasKV) * 2 + 682, 50 }, |
| 3117 | { sizeof(SubtargetSubTypeAliasKV) * 1 + 691, 39 }, |
| 3118 | } }, |
| 3119 | "\000bonaire\000carrizo\000fiji\000generic\000generic-hsa\000gfx10-1-gen" |
| 3120 | "eric\000gfx10-3-generic\000gfx1010\000gfx1011\000gfx1012\000gfx1013\000" |
| 3121 | "gfx1030\000gfx1031\000gfx1032\000gfx1033\000gfx1034\000gfx1035\000gfx10" |
| 3122 | "36\000gfx11-7-generic\000gfx11-generic\000gfx1100\000gfx1101\000gfx1102" |
| 3123 | "\000gfx1103\000gfx1150\000gfx1151\000gfx1152\000gfx1153\000gfx1154\000g" |
| 3124 | "fx1170\000gfx1171\000gfx1172\000gfx12-5-generic\000gfx12-generic\000gfx" |
| 3125 | "1200\000gfx1201\000gfx1250\000gfx1250-strict\000gfx1251\000gfx13-generi" |
| 3126 | "c\000gfx1310\000gfx600\000gfx601\000gfx602\000gfx700\000gfx701\000gfx70" |
| 3127 | "2\000gfx703\000gfx704\000gfx705\000gfx801\000gfx802\000gfx803\000gfx805" |
| 3128 | "\000gfx810\000gfx9-4-generic\000gfx9-generic\000gfx900\000gfx902\000gfx" |
| 3129 | "904\000gfx906\000gfx908\000gfx909\000gfx90a\000gfx90c\000gfx942\000gfx9" |
| 3130 | "50\000hainan\000hawaii\000iceland\000kabini\000kaveri\000mullins\000ola" |
| 3131 | "nd\000pitcairn\000polaris10\000polaris11\000stoney\000tahiti\000tonga\000" |
| 3132 | "tongapro\000verde\000" }; |
| 3133 | |
| 3134 | namespace AMDGPU_MC { |
| 3135 | |
| 3136 | unsigned resolveVariantSchedClassImpl(unsigned SchedClass, |
| 3137 | const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID) { |
| 3138 | switch (SchedClass) { |
| 3139 | case 35: // COPY |
| 3140 | if (CPUID == 1) { // GFX10SpeedModel |
| 3141 | return 81; // WriteSALU |
| 3142 | } |
| 3143 | if (CPUID == 2) { // GFX11SpeedModel |
| 3144 | return 81; // WriteSALU |
| 3145 | } |
| 3146 | if (CPUID == 3) { // GFX125xGenericSpeedModel |
| 3147 | return 81; // WriteSALU |
| 3148 | } |
| 3149 | if (CPUID == 4) { // GFX12SpeedModel |
| 3150 | return 81; // WriteSALU |
| 3151 | } |
| 3152 | if (CPUID == 5) { // GFX1250SpeedModel |
| 3153 | return 81; // WriteSALU |
| 3154 | } |
| 3155 | if (CPUID == 6) { // GFX1251SpeedModel |
| 3156 | return 81; // WriteSALU |
| 3157 | } |
| 3158 | if (CPUID == 7) { // SIFullSpeedModel |
| 3159 | return 81; // WriteSALU |
| 3160 | } |
| 3161 | if (CPUID == 8) { // SIQuarterSpeedModel |
| 3162 | return 81; // WriteSALU |
| 3163 | } |
| 3164 | if (CPUID == 9) { // SIDPGFX942FullSpeedModel |
| 3165 | return 81; // WriteSALU |
| 3166 | } |
| 3167 | if (CPUID == 10) { // SIDPFullSpeedModel |
| 3168 | return 81; // WriteSALU |
| 3169 | } |
| 3170 | if (CPUID == 11) { // SIDPGFX950FullSpeedModel |
| 3171 | return 81; // WriteSALU |
| 3172 | } |
| 3173 | break; |
| 3174 | case 36: // V_ACCVGPR_WRITE_B32_e64 |
| 3175 | if (CPUID == 8) { // SIQuarterSpeedModel |
| 3176 | return 83; // Write64Bit_ReadDefault |
| 3177 | } |
| 3178 | break; |
| 3179 | case 39: // V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi |
| 3180 | if (CPUID == 11) { // SIDPGFX950FullSpeedModel |
| 3181 | return 85; // Write8PassMAI_MIMFMARead |
| 3182 | } |
| 3183 | break; |
| 3184 | case 54: // V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd |
| 3185 | if (CPUID == 11) { // SIDPGFX950FullSpeedModel |
| 3186 | return 86; // Write4PassMAI_MIMFMARead |
| 3187 | } |
| 3188 | break; |
| 3189 | case 55: // V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd |
| 3190 | if (CPUID == 11) { // SIDPGFX950FullSpeedModel |
| 3191 | return 86; // Write4PassMAI_MIMFMARead |
| 3192 | } |
| 3193 | break; |
| 3194 | case 56: // V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd |
| 3195 | if (CPUID == 11) { // SIDPGFX950FullSpeedModel |
| 3196 | return 85; // Write8PassMAI_MIMFMARead |
| 3197 | } |
| 3198 | break; |
| 3199 | case 67: // V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr |
| 3200 | if (CPUID == 3) { // GFX125xGenericSpeedModel |
| 3201 | return 90; // WriteXDL8PassWMMA |
| 3202 | } |
| 3203 | if (CPUID == 5) { // GFX1250SpeedModel |
| 3204 | return 88; // WriteXDL1PassWMMA |
| 3205 | } |
| 3206 | if (CPUID == 6) { // GFX1251SpeedModel |
| 3207 | return 90; // WriteXDL8PassWMMA |
| 3208 | } |
| 3209 | break; |
| 3210 | case 68: // V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250 |
| 3211 | if (CPUID == 3) { // GFX125xGenericSpeedModel |
| 3212 | return 90; // WriteXDL8PassWMMA |
| 3213 | } |
| 3214 | if (CPUID == 5) { // GFX1250SpeedModel |
| 3215 | return 88; // WriteXDL1PassWMMA |
| 3216 | } |
| 3217 | if (CPUID == 6) { // GFX1251SpeedModel |
| 3218 | return 90; // WriteXDL8PassWMMA |
| 3219 | } |
| 3220 | break; |
| 3221 | }; |
| 3222 | // Don't know how to resolve this scheduling class. |
| 3223 | return 0; |
| 3224 | } |
| 3225 | |
| 3226 | } // namespace AMDGPU_MC |
| 3227 | struct AMDGPUGenMCSubtargetInfo : public MCSubtargetInfo { |
| 3228 | AMDGPUGenMCSubtargetInfo(const Triple &TT, |
| 3229 | StringRef CPU, StringRef TuneCPU, StringRef FS, |
| 3230 | StringTable PN, |
| 3231 | ArrayRef<SubtargetFeatureKV> PF, |
| 3232 | ArrayRef<SubtargetSubTypeKV> PD, |
| 3233 | ArrayRef<SubtargetSubTypeAliasKV> PA, |
| 3234 | const MCSchedModel *PSM, |
| 3235 | const MCWriteProcResEntry *WPR, |
| 3236 | const MCWriteLatencyEntry *WL, |
| 3237 | const MCReadAdvanceEntry *RA, const InstrStage *IS, |
| 3238 | const unsigned *OC, const unsigned *FP) : |
| 3239 | MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PA, PSM, |
| 3240 | WPR, WL, RA, IS, OC, FP) { } |
| 3241 | |
| 3242 | unsigned resolveVariantSchedClass(unsigned SchedClass, |
| 3243 | const MCInst *MI, const MCInstrInfo *MCII, |
| 3244 | unsigned CPUID) const final { |
| 3245 | return AMDGPU_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID); |
| 3246 | } |
| 3247 | unsigned getHwModeSet() const final; |
| 3248 | unsigned getHwMode(enum HwModeType type = HwMode_Default) const final; |
| 3249 | }; |
| 3250 | unsigned AMDGPUGenMCSubtargetInfo::getHwModeSet() const { |
| 3251 | [[maybe_unused]] const FeatureBitset &FB = getFeatureBits(); |
| 3252 | // Collect HwModes and store them as a bit set. |
| 3253 | unsigned Modes = 0; |
| 3254 | if (FB[AMDGPU::FeatureMAIInsts] && FB[AMDGPU::FeatureRequiresAlignedVGPRs]) Modes |= (1 << 0); |
| 3255 | if (!(FB[AMDGPU::FeatureMAIInsts]) && FB[AMDGPU::FeatureRequiresAlignedVGPRs] && FB[AMDGPU::FeatureWavefrontSize32]) Modes |= (1 << 1); |
| 3256 | if (!(FB[AMDGPU::FeatureMAIInsts]) && FB[AMDGPU::FeatureRequiresAlignedVGPRs] && FB[AMDGPU::FeatureWavefrontSize64]) Modes |= (1 << 2); |
| 3257 | if ((FB[AMDGPU::FeatureWavefrontSize32] || FB[AMDGPU::FeatureAssemblerPermissiveWavesize]) && !(FB[AMDGPU::FeatureRequiresAlignedVGPRs])) Modes |= (1 << 3); |
| 3258 | return Modes; |
| 3259 | } |
| 3260 | unsigned AMDGPUGenMCSubtargetInfo::getHwMode(enum HwModeType type) const { |
| 3261 | unsigned Modes = getHwModeSet(); |
| 3262 | |
| 3263 | if (!Modes) |
| 3264 | return Modes; |
| 3265 | |
| 3266 | switch (type) { |
| 3267 | case HwMode_Default: |
| 3268 | return llvm::countr_zero(Modes) + 1; |
| 3269 | case HwMode_ValueType: |
| 3270 | Modes &= 15; |
| 3271 | if (!Modes) |
| 3272 | return Modes; |
| 3273 | if (!llvm::has_single_bit<unsigned>(Modes)) |
| 3274 | llvm_unreachable("Two or more HwModes for ValueType were found!" ); |
| 3275 | return llvm::countr_zero(Modes) + 1; |
| 3276 | case HwMode_RegInfo: |
| 3277 | Modes &= 15; |
| 3278 | if (!Modes) |
| 3279 | return Modes; |
| 3280 | if (!llvm::has_single_bit<unsigned>(Modes)) |
| 3281 | llvm_unreachable("Two or more HwModes for RegInfo were found!" ); |
| 3282 | return llvm::countr_zero(Modes) + 1; |
| 3283 | case HwMode_EncodingInfo: |
| 3284 | // No HwMode for EncodingInfo. |
| 3285 | return 0; |
| 3286 | } |
| 3287 | llvm_unreachable("unexpected HwModeType" ); |
| 3288 | return 0; // should not get here |
| 3289 | } |
| 3290 | |
| 3291 | static inline MCSubtargetInfo *createAMDGPUMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) { |
| 3292 | return new AMDGPUGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(AMDGPUSubTypeKVStorage.Strings), AMDGPUFeatureKVStorage.Features, AMDGPUSubTypeKVStorage.SubTypes, ArrayRef(AMDGPUSubTypeKVStorage.Aliases).take_front(18), AMDGPUSchedModels, |
| 3293 | AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, |
| 3294 | nullptr, nullptr, nullptr); |
| 3295 | } |
| 3296 | |
| 3297 | |
| 3298 | } // namespace llvm |
| 3299 | |
| 3300 | #endif // GET_SUBTARGETINFO_MC_DESC |
| 3301 | |
| 3302 | #ifdef GET_SUBTARGETINFO_TARGET_DESC |
| 3303 | #undef GET_SUBTARGETINFO_TARGET_DESC |
| 3304 | |
| 3305 | #include "llvm/ADT/BitmaskEnum.h" |
| 3306 | #include "llvm/Support/Debug.h" |
| 3307 | #include "llvm/Support/raw_ostream.h" |
| 3308 | |
| 3309 | // ParseSubtargetFeatures - Parses features string setting specified |
| 3310 | // subtarget options. |
| 3311 | void llvm::AMDGPUSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) { |
| 3312 | LLVM_DEBUG(dbgs() << "\nFeatures:" << FS); |
| 3313 | LLVM_DEBUG(dbgs() << "\nCPU:" << CPU); |
| 3314 | LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n" ); |
| 3315 | InitMCProcessorInfo(CPU, TuneCPU, FS); |
| 3316 | const FeatureBitset &Bits = getFeatureBits(); |
| 3317 | if (Bits[AMDGPU::Feature16BitInsts]) Has16BitInsts = true; |
| 3318 | if (Bits[AMDGPU::Feature32BitNumRecordsBufferResource] && BufferResourceNumRecordsWidth < 32) BufferResourceNumRecordsWidth = 32; |
| 3319 | if (Bits[AMDGPU::Feature45BitNumRecordsBufferResource] && BufferResourceNumRecordsWidth < 45) BufferResourceNumRecordsWidth = 45; |
| 3320 | if (Bits[AMDGPU::Feature64BitLiterals]) Has64BitLiterals = true; |
| 3321 | if (Bits[AMDGPU::Feature1024AddressableVGPRs]) Has1024AddressableVGPRs = true; |
| 3322 | if (Bits[AMDGPU::Feature1536VGPRs]) Has1536VGPRs = true; |
| 3323 | if (Bits[AMDGPU::FeatureA16]) HasA16 = true; |
| 3324 | if (Bits[AMDGPU::FeatureAddMinMaxInsts]) HasAddMinMaxInsts = true; |
| 3325 | if (Bits[AMDGPU::FeatureAddNoCarryInsts]) HasAddNoCarryInsts = true; |
| 3326 | if (Bits[AMDGPU::FeatureAddSubU64Insts]) HasAddSubU64Insts = true; |
| 3327 | if (Bits[AMDGPU::FeatureAddressableLocalMemorySize32768] && AddressableLocalMemorySize < 32768) AddressableLocalMemorySize = 32768; |
| 3328 | if (Bits[AMDGPU::FeatureAddressableLocalMemorySize65536] && AddressableLocalMemorySize < 65536) AddressableLocalMemorySize = 65536; |
| 3329 | if (Bits[AMDGPU::FeatureAddressableLocalMemorySize163840] && AddressableLocalMemorySize < 163840) AddressableLocalMemorySize = 163840; |
| 3330 | if (Bits[AMDGPU::FeatureAddressableLocalMemorySize196608] && AddressableLocalMemorySize < 196608) AddressableLocalMemorySize = 196608; |
| 3331 | if (Bits[AMDGPU::FeatureAddressableLocalMemorySize327680] && AddressableLocalMemorySize < 327680) AddressableLocalMemorySize = 327680; |
| 3332 | if (Bits[AMDGPU::FeatureAgentScopeFineGrainedRemoteMemoryAtomics]) HasAgentScopeFineGrainedRemoteMemoryAtomics = true; |
| 3333 | if (Bits[AMDGPU::FeatureApertureRegs]) HasApertureRegs = true; |
| 3334 | if (Bits[AMDGPU::FeatureArchitectedFlatScratch]) HasArchitectedFlatScratch = true; |
| 3335 | if (Bits[AMDGPU::FeatureArchitectedSGPRs]) HasArchitectedSGPRs = true; |
| 3336 | if (Bits[AMDGPU::FeatureAshrPkInsts]) HasAshrPkInsts = true; |
| 3337 | if (Bits[AMDGPU::FeatureAssemblerPermissiveWavesize]) HasAssemblerPermissiveWavesize = true; |
| 3338 | if (Bits[AMDGPU::FeatureAsyncLoadToLDSInsts]) HasAsyncLoadToLDSInsts = true; |
| 3339 | if (Bits[AMDGPU::FeatureAsyncStoreFromLDSInsts]) HasAsyncStoreFromLDSInsts = true; |
| 3340 | if (Bits[AMDGPU::FeatureAsynccnt]) HasAsynccnt = true; |
| 3341 | if (Bits[AMDGPU::FeatureAtomicBufferGlobalPkAddF16Insts]) HasAtomicBufferGlobalPkAddF16Insts = true; |
| 3342 | if (Bits[AMDGPU::FeatureAtomicBufferGlobalPkAddF16NoRtnInsts]) HasAtomicBufferGlobalPkAddF16NoRtnInsts = true; |
| 3343 | if (Bits[AMDGPU::FeatureAtomicBufferPkAddBF16Inst]) HasAtomicBufferPkAddBF16Inst = true; |
| 3344 | if (Bits[AMDGPU::FeatureAtomicCSubNoRtnInsts]) HasAtomicCSubNoRtnInsts = true; |
| 3345 | if (Bits[AMDGPU::FeatureAtomicDsPkAdd16Insts]) HasAtomicDsPkAdd16Insts = true; |
| 3346 | if (Bits[AMDGPU::FeatureAtomicFMinFMaxF32FlatInsts]) HasAtomicFMinFMaxF32FlatInsts = true; |
| 3347 | if (Bits[AMDGPU::FeatureAtomicFMinFMaxF32GlobalInsts]) HasAtomicFMinFMaxF32GlobalInsts = true; |
| 3348 | if (Bits[AMDGPU::FeatureAtomicFMinFMaxF64FlatInsts]) HasAtomicFMinFMaxF64FlatInsts = true; |
| 3349 | if (Bits[AMDGPU::FeatureAtomicFMinFMaxF64GlobalInsts]) HasAtomicFMinFMaxF64GlobalInsts = true; |
| 3350 | if (Bits[AMDGPU::FeatureAtomicFaddNoRtnInsts]) HasAtomicFaddNoRtnInsts = true; |
| 3351 | if (Bits[AMDGPU::FeatureAtomicFaddRtnInsts]) HasAtomicFaddRtnInsts = true; |
| 3352 | if (Bits[AMDGPU::FeatureAtomicFlatPkAdd16Insts]) HasAtomicFlatPkAdd16Insts = true; |
| 3353 | if (Bits[AMDGPU::FeatureAtomicGlobalPkAddBF16Inst]) HasAtomicGlobalPkAddBF16Inst = true; |
| 3354 | if (Bits[AMDGPU::FeatureAutoWaitcntBeforeBarrier]) HasAutoWaitcntBeforeBarrier = true; |
| 3355 | if (Bits[AMDGPU::FeatureBF8ConversionScaleInsts]) HasBF8ConversionScaleInsts = true; |
| 3356 | if (Bits[AMDGPU::FeatureBF16ConversionInsts]) HasBF16ConversionInsts = true; |
| 3357 | if (Bits[AMDGPU::FeatureBF16InlineConstFromUpperFP32]) HasBF16InlineConstFromUpperFP32 = true; |
| 3358 | if (Bits[AMDGPU::FeatureBF16PackedInsts]) HasBF16PackedInsts = true; |
| 3359 | if (Bits[AMDGPU::FeatureBF16TransInsts]) HasBF16TransInsts = true; |
| 3360 | if (Bits[AMDGPU::FeatureBVHDualAndBVH8Insts]) HasBVHDualAndBVH8Insts = true; |
| 3361 | if (Bits[AMDGPU::FeatureBVHRayTracingInsts]) HasBVHRayTracingInsts = true; |
| 3362 | if (Bits[AMDGPU::FeatureBackOffBarrier]) HasBackOffBarrier = true; |
| 3363 | if (Bits[AMDGPU::FeatureBitOp3Insts]) HasBitOp3Insts = true; |
| 3364 | if (Bits[AMDGPU::FeatureCIInsts]) HasCIInsts = true; |
| 3365 | if (Bits[AMDGPU::FeatureClusters]) HasClusters = true; |
| 3366 | if (Bits[AMDGPU::FeatureCuMode]) EnableCuMode = true; |
| 3367 | if (Bits[AMDGPU::FeatureCubeInsts]) HasCubeInsts = true; |
| 3368 | if (Bits[AMDGPU::FeatureCvtFP8ByteSel]) HasCvtFP8ByteSel = true; |
| 3369 | if (Bits[AMDGPU::FeatureCvtFP8SDWASrcSel]) HasCvtFP8SDWASrcSel = true; |
| 3370 | if (Bits[AMDGPU::FeatureCvtFP8VOP1Bug]) HasCvtFP8VOP1Bug = true; |
| 3371 | if (Bits[AMDGPU::FeatureCvtNormInsts]) HasCvtNormInsts = true; |
| 3372 | if (Bits[AMDGPU::FeatureCvtPkF16F32Inst]) HasCvtPkF16F32Inst = true; |
| 3373 | if (Bits[AMDGPU::FeatureCvtPkNormVOP2Insts]) HasCvtPkNormVOP2Insts = true; |
| 3374 | if (Bits[AMDGPU::FeatureCvtPkNormVOP3Insts]) HasCvtPkNormVOP3Insts = true; |
| 3375 | if (Bits[AMDGPU::FeatureCvtSrPkBF16F32Inst]) HasCvtSrPkBF16F32Inst = true; |
| 3376 | if (Bits[AMDGPU::FeatureD16Writes32BitVgpr]) HasD16Writes32BitVgpr = true; |
| 3377 | if (Bits[AMDGPU::FeatureDLInsts]) HasDLInsts = true; |
| 3378 | if (Bits[AMDGPU::FeatureDPALU_DPP]) HasDPALU_DPP = true; |
| 3379 | if (Bits[AMDGPU::FeatureDPP]) HasDPP = true; |
| 3380 | if (Bits[AMDGPU::FeatureDPP8]) HasDPP8 = true; |
| 3381 | if (Bits[AMDGPU::FeatureDPPBroadcasts]) HasDPPBroadcasts = true; |
| 3382 | if (Bits[AMDGPU::FeatureDPPSrc1SGPR]) HasDPPSrc1SGPR = true; |
| 3383 | if (Bits[AMDGPU::FeatureDPPWavefrontShifts]) HasDPPWavefrontShifts = true; |
| 3384 | if (Bits[AMDGPU::FeatureDX10ClampAndIEEEMode]) HasDX10ClampAndIEEEMode = true; |
| 3385 | if (Bits[AMDGPU::FeatureDataCacheLineSize128] && DataCacheLineSize < 128) DataCacheLineSize = 128; |
| 3386 | if (Bits[AMDGPU::FeatureDefaultComponentBroadcast]) HasDefaultComponentBroadcast = true; |
| 3387 | if (Bits[AMDGPU::FeatureDefaultComponentZero]) HasDefaultComponentZero = true; |
| 3388 | if (Bits[AMDGPU::FeatureDot1Insts]) HasDot1Insts = true; |
| 3389 | if (Bits[AMDGPU::FeatureDot2Insts]) HasDot2Insts = true; |
| 3390 | if (Bits[AMDGPU::FeatureDot3Insts]) HasDot3Insts = true; |
| 3391 | if (Bits[AMDGPU::FeatureDot4Insts]) HasDot4Insts = true; |
| 3392 | if (Bits[AMDGPU::FeatureDot5Insts]) HasDot5Insts = true; |
| 3393 | if (Bits[AMDGPU::FeatureDot6Insts]) HasDot6Insts = true; |
| 3394 | if (Bits[AMDGPU::FeatureDot7Insts]) HasDot7Insts = true; |
| 3395 | if (Bits[AMDGPU::FeatureDot8Insts]) HasDot8Insts = true; |
| 3396 | if (Bits[AMDGPU::FeatureDot9Insts]) HasDot9Insts = true; |
| 3397 | if (Bits[AMDGPU::FeatureDot10Insts]) HasDot10Insts = true; |
| 3398 | if (Bits[AMDGPU::FeatureDot11Insts]) HasDot11Insts = true; |
| 3399 | if (Bits[AMDGPU::FeatureDot12Insts]) HasDot12Insts = true; |
| 3400 | if (Bits[AMDGPU::FeatureDot13Insts]) HasDot13Insts = true; |
| 3401 | if (Bits[AMDGPU::FeatureDsSrc2Insts]) HasDsSrc2Insts = true; |
| 3402 | if (Bits[AMDGPU::FeatureDumpCodeLower]) DumpCode = true; |
| 3403 | if (Bits[AMDGPU::FeatureEmulatedSystemScopeAtomics]) HasEmulatedSystemScopeAtomics = true; |
| 3404 | if (Bits[AMDGPU::FeatureEnableDS128]) EnableDS128 = true; |
| 3405 | if (Bits[AMDGPU::FeatureEnableFlatScratch]) EnableFlatScratch = true; |
| 3406 | if (Bits[AMDGPU::FeatureEnableLoadStoreOpt]) EnableLoadStoreOpt = true; |
| 3407 | if (Bits[AMDGPU::FeatureEnablePRTStrictNull]) EnablePRTStrictNull = true; |
| 3408 | if (Bits[AMDGPU::FeatureEnableSIScheduler]) EnableSIScheduler = true; |
| 3409 | if (Bits[AMDGPU::FeatureEnableUnsafeDSOffsetFolding]) EnableUnsafeDSOffsetFolding = true; |
| 3410 | if (Bits[AMDGPU::FeatureExtendedImageInsts]) HasExtendedImageInsts = true; |
| 3411 | if (Bits[AMDGPU::FeatureF16BF16ToFP6BF6ConversionScaleInsts]) HasF16BF16ToFP6BF6ConversionScaleInsts = true; |
| 3412 | if (Bits[AMDGPU::FeatureF16FP8ConversionInsts]) HasF16FP8ConversionInsts = true; |
| 3413 | if (Bits[AMDGPU::FeatureF32ToF16BF16ConversionSRInsts]) HasF32ToF16BF16ConversionSRInsts = true; |
| 3414 | if (Bits[AMDGPU::FeatureF32ToFP6BF6ConversionScaleInsts]) HasF32ToFP6BF6ConversionScaleInsts = true; |
| 3415 | if (Bits[AMDGPU::FeatureFMA]) HasFMA = true; |
| 3416 | if (Bits[AMDGPU::FeatureFP4ConversionScaleInsts]) HasFP4ConversionScaleInsts = true; |
| 3417 | if (Bits[AMDGPU::FeatureFP6BF6ConversionScaleInsts]) HasFP6BF6ConversionScaleInsts = true; |
| 3418 | if (Bits[AMDGPU::FeatureFP8ConversionInsts]) HasFP8ConversionInsts = true; |
| 3419 | if (Bits[AMDGPU::FeatureFP8ConversionScaleInsts]) HasFP8ConversionScaleInsts = true; |
| 3420 | if (Bits[AMDGPU::FeatureFP8E5M3Insts]) HasFP8E5M3Insts = true; |
| 3421 | if (Bits[AMDGPU::FeatureFP8F16ConversionInsts]) HasFP8F16ConversionInsts = true; |
| 3422 | if (Bits[AMDGPU::FeatureFP8Insts]) HasFP8Insts = true; |
| 3423 | if (Bits[AMDGPU::FeatureFP64]) HasFP64 = true; |
| 3424 | if (Bits[AMDGPU::FeatureFastDenormalF32]) HasFastDenormalF32 = true; |
| 3425 | if (Bits[AMDGPU::FeatureFastFMAF32]) HasFastFMAF32 = true; |
| 3426 | if (Bits[AMDGPU::FeatureFlatAddressSpace]) HasFlatAddressSpace = true; |
| 3427 | if (Bits[AMDGPU::FeatureFlatAtomicFaddF32Inst]) HasFlatAtomicFaddF32Inst = true; |
| 3428 | if (Bits[AMDGPU::FeatureFlatBufferGlobalAtomicFaddF64Inst]) HasFlatBufferGlobalAtomicFaddF64Inst = true; |
| 3429 | if (Bits[AMDGPU::FeatureFlatGVSMode]) HasFlatGVSMode = true; |
| 3430 | if (Bits[AMDGPU::FeatureFlatGlobalInsts]) HasFlatGlobalInsts = true; |
| 3431 | if (Bits[AMDGPU::FeatureFlatInstOffsets]) HasFlatInstOffsets = true; |
| 3432 | if (Bits[AMDGPU::FeatureFlatOffsetBits12] && FlatOffsetBitWidth < 12) FlatOffsetBitWidth = 12; |
| 3433 | if (Bits[AMDGPU::FeatureFlatOffsetBits24] && FlatOffsetBitWidth < 24) FlatOffsetBitWidth = 24; |
| 3434 | if (Bits[AMDGPU::FeatureFlatScratchInsts]) HasFlatScratchInsts = true; |
| 3435 | if (Bits[AMDGPU::FeatureFlatSegmentOffsetBug]) HasFlatSegmentOffsetBug = true; |
| 3436 | if (Bits[AMDGPU::FeatureFlatSignedOffset]) HasFlatSignedOffset = true; |
| 3437 | if (Bits[AMDGPU::FeatureFmaLegacy32Insts]) HasFmaLegacy32Insts = true; |
| 3438 | if (Bits[AMDGPU::FeatureFmaMixBF16Insts]) HasFmaMixBF16Insts = true; |
| 3439 | if (Bits[AMDGPU::FeatureFmaMixInsts]) HasFmaMixInsts = true; |
| 3440 | if (Bits[AMDGPU::FeatureFmacF64Inst]) HasFmacF64Inst = true; |
| 3441 | if (Bits[AMDGPU::FeatureFormattedMUBUFInsts]) HasFormattedMUBUFInsts = true; |
| 3442 | if (Bits[AMDGPU::FeatureFullRate64Ops]) HasFullRate64Ops = true; |
| 3443 | if (Bits[AMDGPU::FeatureG16]) HasG16 = true; |
| 3444 | if (Bits[AMDGPU::FeatureGCN3Encoding]) HasGCN3Encoding = true; |
| 3445 | if (Bits[AMDGPU::FeatureGDS]) HasGDS = true; |
| 3446 | if (Bits[AMDGPU::FeatureGFX7GFX8GFX9Insts]) HasGFX7GFX8GFX9Insts = true; |
| 3447 | if (Bits[AMDGPU::FeatureGFX8Insts]) HasGFX8Insts = true; |
| 3448 | if (Bits[AMDGPU::FeatureGFX9] && Gen < GCNSubtarget::GFX9) Gen = GCNSubtarget::GFX9; |
| 3449 | if (Bits[AMDGPU::FeatureGFX9Insts]) HasGFX9Insts = true; |
| 3450 | if (Bits[AMDGPU::FeatureGFX10] && Gen < GCNSubtarget::GFX10) Gen = GCNSubtarget::GFX10; |
| 3451 | if (Bits[AMDGPU::FeatureGFX10Insts]) HasGFX10Insts = true; |
| 3452 | if (Bits[AMDGPU::FeatureGFX10_3Insts]) HasGFX10_3Insts = true; |
| 3453 | if (Bits[AMDGPU::FeatureGFX10_BEncoding]) HasGFX10_BEncoding = true; |
| 3454 | if (Bits[AMDGPU::FeatureGFX11] && Gen < GCNSubtarget::GFX11) Gen = GCNSubtarget::GFX11; |
| 3455 | if (Bits[AMDGPU::FeatureGFX11Insts]) HasGFX11Insts = true; |
| 3456 | if (Bits[AMDGPU::FeatureGFX11_7Insts]) HasGFX11_7Insts = true; |
| 3457 | if (Bits[AMDGPU::FeatureGFX12] && Gen < GCNSubtarget::GFX12) Gen = GCNSubtarget::GFX12; |
| 3458 | if (Bits[AMDGPU::FeatureGFX12Insts]) HasGFX12Insts = true; |
| 3459 | if (Bits[AMDGPU::FeatureGFX13] && Gen < GCNSubtarget::GFX13) Gen = GCNSubtarget::GFX13; |
| 3460 | if (Bits[AMDGPU::FeatureGFX13Insts]) HasGFX13Insts = true; |
| 3461 | if (Bits[AMDGPU::FeatureGFX90AInsts]) HasGFX90AInsts = true; |
| 3462 | if (Bits[AMDGPU::FeatureGFX125xLowestRateWMMA]) HasGFX125xLowestRateWMMA = true; |
| 3463 | if (Bits[AMDGPU::FeatureGFX940Insts]) HasGFX940Insts = true; |
| 3464 | if (Bits[AMDGPU::FeatureGFX950Insts]) HasGFX950Insts = true; |
| 3465 | if (Bits[AMDGPU::FeatureGFX1250Insts]) HasGFX1250Insts = true; |
| 3466 | if (Bits[AMDGPU::FeatureGFX1250_STRICT]) HasGFX1250_STRICT = true; |
| 3467 | if (Bits[AMDGPU::FeatureGFX1251GEMMInsts]) HasGFX1251GEMMInsts = true; |
| 3468 | if (Bits[AMDGPU::FeatureGWS]) HasGWS = true; |
| 3469 | if (Bits[AMDGPU::FeatureGetWaveIdInst]) HasGetWaveIdInst = true; |
| 3470 | if (Bits[AMDGPU::FeatureGloballyAddressableScratch]) HasGloballyAddressableScratch = true; |
| 3471 | if (Bits[AMDGPU::FeatureHalfAddressablePhysicalLocalMemory]) HasHalfAddressablePhysicalLocalMemory = true; |
| 3472 | if (Bits[AMDGPU::FeatureHalfRate64Ops]) HasHalfRate64Ops = true; |
| 3473 | if (Bits[AMDGPU::FeatureIEEEMinimumMaximumInsts]) HasIEEEMinimumMaximumInsts = true; |
| 3474 | if (Bits[AMDGPU::FeatureImageGather4D16Bug]) HasImageGather4D16Bug = true; |
| 3475 | if (Bits[AMDGPU::FeatureImageInsts]) HasImageInsts = true; |
| 3476 | if (Bits[AMDGPU::FeatureImageStoreD16Bug]) HasImageStoreD16Bug = true; |
| 3477 | if (Bits[AMDGPU::FeatureInstCacheLineSize64] && InstCacheLineSize < 64) InstCacheLineSize = 64; |
| 3478 | if (Bits[AMDGPU::FeatureInstCacheLineSize128] && InstCacheLineSize < 128) InstCacheLineSize = 128; |
| 3479 | if (Bits[AMDGPU::FeatureInstFwdPrefetchBug]) HasInstFwdPrefetchBug = true; |
| 3480 | if (Bits[AMDGPU::FeatureIntClamp]) HasIntClamp = true; |
| 3481 | if (Bits[AMDGPU::FeatureInv2PiInlineImm]) HasInv2PiInlineImm = true; |
| 3482 | if (Bits[AMDGPU::FeatureKernargPreload]) HasKernargPreload = true; |
| 3483 | if (Bits[AMDGPU::FeatureLDSBankCount16] && LDSBankCount < 16) LDSBankCount = 16; |
| 3484 | if (Bits[AMDGPU::FeatureLDSBankCount32] && LDSBankCount < 32) LDSBankCount = 32; |
| 3485 | if (Bits[AMDGPU::FeatureLDSMisalignedBug]) HasLDSMisalignedBug = true; |
| 3486 | if (Bits[AMDGPU::FeatureLdsAtomicAddF64]) HasLdsAtomicAddF64 = true; |
| 3487 | if (Bits[AMDGPU::FeatureLdsBarrierArriveAtomic]) HasLdsBarrierArriveAtomic = true; |
| 3488 | if (Bits[AMDGPU::FeatureLdsBranchVmemWARHazard]) HasLdsBranchVmemWARHazard = true; |
| 3489 | if (Bits[AMDGPU::FeatureLerpInst]) HasLerpInst = true; |
| 3490 | if (Bits[AMDGPU::FeatureLshlAddU64Inst]) HasLshlAddU64Inst = true; |
| 3491 | if (Bits[AMDGPU::FeatureMADIntraFwdBug]) HasMADIntraFwdBug = true; |
| 3492 | if (Bits[AMDGPU::FeatureMAIInsts]) HasMAIInsts = true; |
| 3493 | if (Bits[AMDGPU::FeatureMFMAInlineLiteralBug]) HasMFMAInlineLiteralBug = true; |
| 3494 | if (Bits[AMDGPU::FeatureMIMG_R128]) HasMIMG_R128 = true; |
| 3495 | if (Bits[AMDGPU::FeatureMSAALoadDstSelBug]) HasMSAALoadDstSelBug = true; |
| 3496 | if (Bits[AMDGPU::FeatureMSAALoadInsts]) HasMSAALoadInsts = true; |
| 3497 | if (Bits[AMDGPU::FeatureMTBUFInsts]) HasMTBUFInsts = true; |
| 3498 | if (Bits[AMDGPU::FeatureMadMacF32Insts]) HasMadMacF32Insts = true; |
| 3499 | if (Bits[AMDGPU::FeatureMadMixInsts]) HasMadMixInsts = true; |
| 3500 | if (Bits[AMDGPU::FeatureMadNC64_32Insts]) HasMadNC64_32Insts = true; |
| 3501 | if (Bits[AMDGPU::FeatureMadU32Inst]) HasMadU32Inst = true; |
| 3502 | if (Bits[AMDGPU::FeatureMaxHardClauseLength32] && MaxHardClauseLength < 32) MaxHardClauseLength = 32; |
| 3503 | if (Bits[AMDGPU::FeatureMaxHardClauseLength63] && MaxHardClauseLength < 63) MaxHardClauseLength = 63; |
| 3504 | if (Bits[AMDGPU::FeatureMaxPrivateElementSize4] && MaxPrivateElementSize < 4) MaxPrivateElementSize = 4; |
| 3505 | if (Bits[AMDGPU::FeatureMaxPrivateElementSize8] && MaxPrivateElementSize < 8) MaxPrivateElementSize = 8; |
| 3506 | if (Bits[AMDGPU::FeatureMaxPrivateElementSize16] && MaxPrivateElementSize < 16) MaxPrivateElementSize = 16; |
| 3507 | if (Bits[AMDGPU::FeatureMaxWavesPerEU8] && MaxWavesPerEU < 8) MaxWavesPerEU = 8; |
| 3508 | if (Bits[AMDGPU::FeatureMaxWavesPerEU10] && MaxWavesPerEU < 10) MaxWavesPerEU = 10; |
| 3509 | if (Bits[AMDGPU::FeatureMaxWavesPerEU16] && MaxWavesPerEU < 16) MaxWavesPerEU = 16; |
| 3510 | if (Bits[AMDGPU::FeatureMaxWavesPerEU20] && MaxWavesPerEU < 20) MaxWavesPerEU = 20; |
| 3511 | if (Bits[AMDGPU::FeatureMcastLoadInsts]) HasMcastLoadInsts = true; |
| 3512 | if (Bits[AMDGPU::FeatureMemoryAtomicFAddF32DenormalSupport]) HasMemoryAtomicFaddF32DenormalSupport = true; |
| 3513 | if (Bits[AMDGPU::FeatureMin3Max3PKF16]) HasMin3Max3PKF16 = true; |
| 3514 | if (Bits[AMDGPU::FeatureMinMaxI64Insts]) HasMinMaxI64Insts = true; |
| 3515 | if (Bits[AMDGPU::FeatureMinimum3Maximum3F16]) HasMinimum3Maximum3F16 = true; |
| 3516 | if (Bits[AMDGPU::FeatureMinimum3Maximum3F32]) HasMinimum3Maximum3F32 = true; |
| 3517 | if (Bits[AMDGPU::FeatureMinimum3Maximum3PKF16]) HasMinimum3Maximum3PKF16 = true; |
| 3518 | if (Bits[AMDGPU::FeatureMovrel]) HasMovrel = true; |
| 3519 | if (Bits[AMDGPU::FeatureMqsadInsts]) HasMqsadInsts = true; |
| 3520 | if (Bits[AMDGPU::FeatureMqsadPkInsts]) HasMqsadPkInsts = true; |
| 3521 | if (Bits[AMDGPU::FeatureMsadInsts]) HasMsadInsts = true; |
| 3522 | if (Bits[AMDGPU::FeatureNSAClauseBug]) HasNSAClauseBug = true; |
| 3523 | if (Bits[AMDGPU::FeatureNSAEncoding]) HasNSAEncoding = true; |
| 3524 | if (Bits[AMDGPU::FeatureNSAtoVMEMBug]) HasNSAtoVMEMBug = true; |
| 3525 | if (Bits[AMDGPU::FeatureNeedsAligned2addrDS]) HasNeedsAligned2addrDS = true; |
| 3526 | if (Bits[AMDGPU::FeatureNeedsTDMDrain]) HasNeedsTDMDrain = true; |
| 3527 | if (Bits[AMDGPU::FeatureNegativeScratchOffsetBug]) HasNegativeScratchOffsetBug = true; |
| 3528 | if (Bits[AMDGPU::FeatureNegativeUnalignedScratchOffsetBug]) HasNegativeUnalignedScratchOffsetBug = true; |
| 3529 | if (Bits[AMDGPU::FeatureNoDataDepHazard]) HasNoDataDepHazard = true; |
| 3530 | if (Bits[AMDGPU::FeatureNoF16PseudoScalarTransInlineConstants]) HasNoF16PseudoScalarTransInlineConstants = true; |
| 3531 | if (Bits[AMDGPU::FeatureNoSdstCMPX]) HasNoSdstCMPX = true; |
| 3532 | if (Bits[AMDGPU::FeatureOCPFP8ConversionInsts]) HasOCPFP8ConversionInsts = true; |
| 3533 | if (Bits[AMDGPU::FeatureOffset3fBug]) HasOffset3fBug = true; |
| 3534 | if (Bits[AMDGPU::FeaturePackedFP32Ops]) HasPackedFP32Ops = true; |
| 3535 | if (Bits[AMDGPU::FeaturePackedFP32SingleSGPROps]) HasPackedFP32SingleSGPROps = true; |
| 3536 | if (Bits[AMDGPU::FeaturePackedFP64SingleSGPROps]) HasPackedFP64SingleSGPROps = true; |
| 3537 | if (Bits[AMDGPU::FeaturePackedTID]) HasPackedTID = true; |
| 3538 | if (Bits[AMDGPU::FeaturePackedU64SingleSGPROps]) HasPackedU64SingleSGPROps = true; |
| 3539 | if (Bits[AMDGPU::FeaturePartialNSAEncoding]) HasPartialNSAEncoding = true; |
| 3540 | if (Bits[AMDGPU::FeaturePermlane16Insts]) HasPermlane16Insts = true; |
| 3541 | if (Bits[AMDGPU::FeaturePermlane16Swap]) HasPermlane16Swap = true; |
| 3542 | if (Bits[AMDGPU::FeaturePermlane32Swap]) HasPermlane32Swap = true; |
| 3543 | if (Bits[AMDGPU::FeaturePkAddMinMaxInsts]) HasPkAddMinMaxInsts = true; |
| 3544 | if (Bits[AMDGPU::FeaturePkFmacF16Inst]) HasPkFmacF16Inst = true; |
| 3545 | if (Bits[AMDGPU::FeaturePointSampleAccel]) HasPointSampleAccel = true; |
| 3546 | if (Bits[AMDGPU::FeaturePopsExitingWaveID]) HasPopsExitingWaveID = true; |
| 3547 | if (Bits[AMDGPU::FeaturePreciseMemory]) EnablePreciseMemory = true; |
| 3548 | if (Bits[AMDGPU::FeaturePrivEnabledTrap2NopBug]) HasPrivEnabledTrap2NopBug = true; |
| 3549 | if (Bits[AMDGPU::FeaturePrngInst]) HasPrngInst = true; |
| 3550 | if (Bits[AMDGPU::FeaturePseudoScalarTrans]) HasPseudoScalarTrans = true; |
| 3551 | if (Bits[AMDGPU::FeatureQsadInsts]) HasQsadInsts = true; |
| 3552 | if (Bits[AMDGPU::FeatureR128A16]) HasR128A16 = true; |
| 3553 | if (Bits[AMDGPU::FeatureRealTrue16Insts]) EnableRealTrue16Insts = true; |
| 3554 | if (Bits[AMDGPU::FeatureRequiredExportPriority]) HasRequiredExportPriority = true; |
| 3555 | if (Bits[AMDGPU::FeatureRequiresAlignedVGPRs]) RequiresAlignVGPR = true; |
| 3556 | if (Bits[AMDGPU::FeatureRequiresCOV6]) RequiresCOV6 = true; |
| 3557 | if (Bits[AMDGPU::FeatureRequiresInitialUnclausedVmem]) HasRequiresInitialUnclausedVmem = true; |
| 3558 | if (Bits[AMDGPU::FeatureRestrictedSOffset]) HasRestrictedSOffset = true; |
| 3559 | if (Bits[AMDGPU::FeatureSALUFloatInsts]) HasSALUFloatInsts = true; |
| 3560 | if (Bits[AMDGPU::FeatureSALUMinimumMaximumInsts]) HasSALUMinimumMaximumInsts = true; |
| 3561 | if (Bits[AMDGPU::FeatureSBarrierLeaveImm]) HasSBarrierLeaveImm = true; |
| 3562 | if (Bits[AMDGPU::FeatureSDWA]) HasSDWA = true; |
| 3563 | if (Bits[AMDGPU::FeatureSDWAMac]) HasSDWAMac = true; |
| 3564 | if (Bits[AMDGPU::FeatureSDWAOmod]) HasSDWAOmod = true; |
| 3565 | if (Bits[AMDGPU::FeatureSDWAOutModsVOPC]) HasSDWAOutModsVOPC = true; |
| 3566 | if (Bits[AMDGPU::FeatureSDWAScalar]) HasSDWAScalar = true; |
| 3567 | if (Bits[AMDGPU::FeatureSDWASdst]) HasSDWASdst = true; |
| 3568 | if (Bits[AMDGPU::FeatureSGPRInitBug]) HasSGPRInitBug = true; |
| 3569 | if (Bits[AMDGPU::FeatureSMEMtoVectorWriteHazard]) HasSMEMtoVectorWriteHazard = true; |
| 3570 | if (Bits[AMDGPU::FeatureSMemRealTime]) HasSMemRealTime = true; |
| 3571 | if (Bits[AMDGPU::FeatureSMemTimeInst]) HasSMemTimeInst = true; |
| 3572 | if (Bits[AMDGPU::FeatureSRAMECC]) EnableSRAMECC = true; |
| 3573 | if (Bits[AMDGPU::FeatureSWMMACGfx1200Insts]) HasSWMMACGfx1200Insts = true; |
| 3574 | if (Bits[AMDGPU::FeatureSWMMACGfx1250Insts]) HasSWMMACGfx1250Insts = true; |
| 3575 | if (Bits[AMDGPU::FeatureSWakeupBarrier]) HasSWakeupBarrier = true; |
| 3576 | if (Bits[AMDGPU::FeatureSWakeupImm]) HasSWakeupImm = true; |
| 3577 | if (Bits[AMDGPU::FeatureSadInsts]) HasSadInsts = true; |
| 3578 | if (Bits[AMDGPU::FeatureSafeCUPrefetch]) HasSafeCUPrefetch = true; |
| 3579 | if (Bits[AMDGPU::FeatureSafeSmemPrefetch]) HasSafeSmemPrefetch = true; |
| 3580 | if (Bits[AMDGPU::FeatureScalarAtomics]) HasScalarAtomics = true; |
| 3581 | if (Bits[AMDGPU::FeatureScalarDwordx3Loads]) HasScalarDwordx3Loads = true; |
| 3582 | if (Bits[AMDGPU::FeatureScalarFlatScratchInsts]) HasScalarFlatScratchInsts = true; |
| 3583 | if (Bits[AMDGPU::FeatureScalarStores]) HasScalarStores = true; |
| 3584 | if (Bits[AMDGPU::FeatureSeaIslands] && Gen < GCNSubtarget::SEA_ISLANDS) Gen = GCNSubtarget::SEA_ISLANDS; |
| 3585 | if (Bits[AMDGPU::FeatureSetPrioIncWgInst]) HasSetPrioIncWgInst = true; |
| 3586 | if (Bits[AMDGPU::FeatureSetregVGPRMSBFixup]) HasSetregVGPRMSBFixup = true; |
| 3587 | if (Bits[AMDGPU::FeatureShaderCyclesHiLoRegisters]) HasShaderCyclesHiLoRegisters = true; |
| 3588 | if (Bits[AMDGPU::FeatureShaderCyclesRegister]) HasShaderCyclesRegister = true; |
| 3589 | if (Bits[AMDGPU::FeatureSmemPrefetchInsts]) HasSmemPrefetchInsts = true; |
| 3590 | if (Bits[AMDGPU::FeatureSouthernIslands] && Gen < GCNSubtarget::SOUTHERN_ISLANDS) Gen = GCNSubtarget::SOUTHERN_ISLANDS; |
| 3591 | if (Bits[AMDGPU::FeatureSupportsSRAMECC]) SupportsSRAMECC = true; |
| 3592 | if (Bits[AMDGPU::FeatureSupportsWGP]) HasSupportsWGP = true; |
| 3593 | if (Bits[AMDGPU::FeatureSupportsWave32]) SupportsWave32 = true; |
| 3594 | if (Bits[AMDGPU::FeatureSupportsWave64]) SupportsWave64 = true; |
| 3595 | if (Bits[AMDGPU::FeatureSupportsXNACK]) SupportsXNACK = true; |
| 3596 | if (Bits[AMDGPU::FeatureTanhInsts]) HasTanhInsts = true; |
| 3597 | if (Bits[AMDGPU::FeatureTensorCvtLutInsts]) HasTensorCvtLutInsts = true; |
| 3598 | if (Bits[AMDGPU::FeatureTgSplitSupport]) HasTgSplitSupport = true; |
| 3599 | if (Bits[AMDGPU::FeatureTransCoexecutionHazard]) HasTransCoexecutionHazard = true; |
| 3600 | if (Bits[AMDGPU::FeatureTransposeLoadF4F6Insts]) HasTransposeLoadF4F6Insts = true; |
| 3601 | if (Bits[AMDGPU::FeatureTrapHandler]) HasTrapHandler = true; |
| 3602 | if (Bits[AMDGPU::FeatureTrigReducedRange]) HasTrigReducedRange = true; |
| 3603 | if (Bits[AMDGPU::FeatureTrue16BitInsts]) HasTrue16BitInsts = true; |
| 3604 | if (Bits[AMDGPU::FeatureUnalignedAccessMode]) HasUnalignedAccessMode = true; |
| 3605 | if (Bits[AMDGPU::FeatureUnalignedBufferAccess]) HasUnalignedBufferAccess = true; |
| 3606 | if (Bits[AMDGPU::FeatureUnalignedDSAccess]) HasUnalignedDSAccess = true; |
| 3607 | if (Bits[AMDGPU::FeatureUnalignedScratchAccess]) HasUnalignedScratchAccess = true; |
| 3608 | if (Bits[AMDGPU::FeatureUnpackedD16VMem]) HasUnpackedD16VMem = true; |
| 3609 | if (Bits[AMDGPU::FeatureUseAddPC64Inst]) UseAddPC64Inst = true; |
| 3610 | if (Bits[AMDGPU::FeatureUseBlockVGPROpsForCSR]) UseBlockVGPROpsForCSR = true; |
| 3611 | if (Bits[AMDGPU::FeatureUseFlatForGlobal]) UseFlatForGlobal = true; |
| 3612 | if (Bits[AMDGPU::FeatureUserSGPRInit16Bug]) HasUserSGPRInit16Bug = true; |
| 3613 | if (Bits[AMDGPU::FeatureVALUTransUseHazard]) HasVALUTransUseHazard = true; |
| 3614 | if (Bits[AMDGPU::FeatureVGPRIndexMode]) HasVGPRIndexMode = true; |
| 3615 | if (Bits[AMDGPU::FeatureVMEMtoScalarWriteHazard]) HasVMEMtoScalarWriteHazard = true; |
| 3616 | if (Bits[AMDGPU::FeatureVMemToLDSLoad]) HasVMemToLDSLoad = true; |
| 3617 | if (Bits[AMDGPU::FeatureVMovB64Inst]) HasVMovB64Inst = true; |
| 3618 | if (Bits[AMDGPU::FeatureVMulU64Inst]) HasVMulU64Inst = true; |
| 3619 | if (Bits[AMDGPU::FeatureVOP3Literal]) HasVOP3Literal = true; |
| 3620 | if (Bits[AMDGPU::FeatureVOP3PInsts]) HasVOP3PInsts = true; |
| 3621 | if (Bits[AMDGPU::FeatureVOP3PX2IncrementsVaVdstTwice]) HasVOP3PX2IncrementsVaVdstTwice = true; |
| 3622 | if (Bits[AMDGPU::FeatureVOPDInsts]) HasVOPDInsts = true; |
| 3623 | if (Bits[AMDGPU::FeatureVcmpxExecWARHazard]) HasVcmpxExecWARHazard = true; |
| 3624 | if (Bits[AMDGPU::FeatureVcmpxPermlaneHazard]) HasVcmpxPermlaneHazard = true; |
| 3625 | if (Bits[AMDGPU::FeatureVmemPrefInsts]) HasVmemPrefInsts = true; |
| 3626 | if (Bits[AMDGPU::FeatureVmemWriteVgprInOrder]) HasVmemWriteVgprInOrder = true; |
| 3627 | if (Bits[AMDGPU::FeatureVolcanicIslands] && Gen < GCNSubtarget::VOLCANIC_ISLANDS) Gen = GCNSubtarget::VOLCANIC_ISLANDS; |
| 3628 | if (Bits[AMDGPU::FeatureVscnt]) HasVscnt = true; |
| 3629 | if (Bits[AMDGPU::FeatureWMMA128bInsts]) HasWMMA128bInsts = true; |
| 3630 | if (Bits[AMDGPU::FeatureWMMA256bInsts]) HasWMMA256bInsts = true; |
| 3631 | if (Bits[AMDGPU::FeatureWMMACoexecutionHazards]) HasWMMACoexecutionHazards = true; |
| 3632 | if (Bits[AMDGPU::FeatureWMMAN16Insts]) HasWMMAN16Insts = true; |
| 3633 | if (Bits[AMDGPU::FeatureWaitXcnt]) HasWaitXcnt = true; |
| 3634 | if (Bits[AMDGPU::FeatureWaitsBeforeSystemScopeStores]) RequiresWaitsBeforeSystemScopeStores = true; |
| 3635 | if (Bits[AMDGPU::FeatureWavefrontSize16] && WavefrontSizeLog2 < 4) WavefrontSizeLog2 = 4; |
| 3636 | if (Bits[AMDGPU::FeatureWavefrontSize32] && WavefrontSizeLog2 < 5) WavefrontSizeLog2 = 5; |
| 3637 | if (Bits[AMDGPU::FeatureWavefrontSize64] && WavefrontSizeLog2 < 6) WavefrontSizeLog2 = 6; |
| 3638 | if (Bits[AMDGPU::FeatureXF32Insts]) HasXF32Insts = true; |
| 3639 | if (Bits[AMDGPU::FeatureXNACK]) EnableXNACK = true; |
| 3640 | if (Bits[AMDGPU::FeatureXNACKOnOffModes]) HasXNACKOnOffModes = true; |
| 3641 | } |
| 3642 | |
| 3643 | #endif // GET_SUBTARGETINFO_TARGET_DESC |
| 3644 | |
| 3645 | #ifdef GET_SUBTARGETINFO_HEADER |
| 3646 | #undef GET_SUBTARGETINFO_HEADER |
| 3647 | |
| 3648 | namespace llvm { |
| 3649 | |
| 3650 | class DFAPacketizer; |
| 3651 | namespace AMDGPU_MC { |
| 3652 | |
| 3653 | unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, const MCSubtargetInfo &STI, unsigned CPUID); |
| 3654 | |
| 3655 | } // namespace AMDGPU_MC |
| 3656 | struct AMDGPUGenSubtargetInfo : public TargetSubtargetInfo { |
| 3657 | explicit AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS); |
| 3658 | public: |
| 3659 | unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const final; |
| 3660 | unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const final; |
| 3661 | DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const; |
| 3662 | enum class AMDGPUHwModeBits : unsigned { |
| 3663 | DefaultMode = 0, |
| 3664 | AVAlign2LoadStoreMode = (1 << 0), |
| 3665 | AlignedVGPRNoAGPRMode_Wave32 = (1 << 1), |
| 3666 | AlignedVGPRNoAGPRMode_Wave64 = (1 << 2), |
| 3667 | anonymous_14248 = (1 << 3), |
| 3668 | |
| 3669 | LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/anonymous_14248), |
| 3670 | }; |
| 3671 | unsigned getHwModeSet() const final; |
| 3672 | unsigned getHwMode(enum HwModeType type = HwMode_Default) const final; |
| 3673 | const FeatureBitset &getInlineIgnoreFeatures() const override; |
| 3674 | const FeatureBitset &getInlineInverseFeatures() const override; |
| 3675 | const FeatureBitset &getInlineMustMatchFeatures() const override; |
| 3676 | }; |
| 3677 | |
| 3678 | } // namespace llvm |
| 3679 | |
| 3680 | #endif // GET_SUBTARGETINFO_HEADER |
| 3681 | |
| 3682 | #ifdef GET_SUBTARGETINFO_CTOR |
| 3683 | #undef GET_SUBTARGETINFO_CTOR |
| 3684 | |
| 3685 | #include "llvm/CodeGen/TargetSchedule.h" |
| 3686 | |
| 3687 | namespace llvm { |
| 3688 | |
| 3689 | extern const llvm::StringRef AMDGPUNames[]; |
| 3690 | extern const llvm::SubtargetFeatureKVStorage<324, 20809> AMDGPUFeatureKVStorage; |
| 3691 | extern const llvm::SubtargetSubTypeKVStorage<64, 18, 698> AMDGPUSubTypeKVStorage; |
| 3692 | extern const llvm::MCSchedModel AMDGPUSchedModels[]; |
| 3693 | extern const llvm::MCWriteProcResEntry AMDGPUWriteProcResTable[]; |
| 3694 | extern const llvm::MCWriteLatencyEntry AMDGPUWriteLatencyTable[]; |
| 3695 | extern const llvm::MCReadAdvanceEntry AMDGPUReadAdvanceTable[]; |
| 3696 | AMDGPUGenSubtargetInfo::AMDGPUGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) |
| 3697 | : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, StringTable(AMDGPUSubTypeKVStorage.Strings), ArrayRef(AMDGPUFeatureKVStorage.Features), ArrayRef(AMDGPUSubTypeKVStorage.SubTypes), ArrayRef(AMDGPUSubTypeKVStorage.Aliases).take_front(18), AMDGPUSchedModels, |
| 3698 | AMDGPUWriteProcResTable, AMDGPUWriteLatencyTable, AMDGPUReadAdvanceTable, |
| 3699 | nullptr, nullptr, nullptr) {} |
| 3700 | |
| 3701 | unsigned AMDGPUGenSubtargetInfo |
| 3702 | ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const { |
| 3703 | |
| 3704 | const SIInstrInfo *TII = |
| 3705 | static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo()); |
| 3706 | (void)TII; |
| 3707 | |
| 3708 | switch (SchedClass) { |
| 3709 | case 35: // COPY |
| 3710 | if (SchedModel->getProcessorID() == 1) { // GFX10SpeedModel |
| 3711 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
| 3712 | return 79; // Write32Bit |
| 3713 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
| 3714 | return 80; // Write64Bit |
| 3715 | return 81; // WriteSALU |
| 3716 | } |
| 3717 | if (SchedModel->getProcessorID() == 2) { // GFX11SpeedModel |
| 3718 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
| 3719 | return 79; // Write32Bit |
| 3720 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
| 3721 | return 80; // Write64Bit |
| 3722 | return 81; // WriteSALU |
| 3723 | } |
| 3724 | if (SchedModel->getProcessorID() == 3) { // GFX125xGenericSpeedModel |
| 3725 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
| 3726 | return 79; // Write32Bit |
| 3727 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
| 3728 | return 80; // Write64Bit |
| 3729 | return 81; // WriteSALU |
| 3730 | } |
| 3731 | if (SchedModel->getProcessorID() == 4) { // GFX12SpeedModel |
| 3732 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
| 3733 | return 79; // Write32Bit |
| 3734 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
| 3735 | return 80; // Write64Bit |
| 3736 | return 81; // WriteSALU |
| 3737 | } |
| 3738 | if (SchedModel->getProcessorID() == 5) { // GFX1250SpeedModel |
| 3739 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
| 3740 | return 79; // Write32Bit |
| 3741 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
| 3742 | return 80; // Write64Bit |
| 3743 | return 81; // WriteSALU |
| 3744 | } |
| 3745 | if (SchedModel->getProcessorID() == 6) { // GFX1251SpeedModel |
| 3746 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
| 3747 | return 79; // Write32Bit |
| 3748 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
| 3749 | return 80; // Write64Bit |
| 3750 | return 81; // WriteSALU |
| 3751 | } |
| 3752 | if (SchedModel->getProcessorID() == 7) { // SIFullSpeedModel |
| 3753 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
| 3754 | return 79; // Write32Bit |
| 3755 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
| 3756 | return 80; // Write64Bit |
| 3757 | return 81; // WriteSALU |
| 3758 | } |
| 3759 | if (SchedModel->getProcessorID() == 8) { // SIQuarterSpeedModel |
| 3760 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
| 3761 | return 79; // Write32Bit |
| 3762 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
| 3763 | return 80; // Write64Bit |
| 3764 | return 81; // WriteSALU |
| 3765 | } |
| 3766 | if (SchedModel->getProcessorID() == 9) { // SIDPGFX942FullSpeedModel |
| 3767 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
| 3768 | return 79; // Write32Bit |
| 3769 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
| 3770 | return 80; // Write64Bit |
| 3771 | return 81; // WriteSALU |
| 3772 | } |
| 3773 | if (SchedModel->getProcessorID() == 10) { // SIDPFullSpeedModel |
| 3774 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
| 3775 | return 79; // Write32Bit |
| 3776 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
| 3777 | return 80; // Write64Bit |
| 3778 | return 81; // WriteSALU |
| 3779 | } |
| 3780 | if (SchedModel->getProcessorID() == 11) { // SIDPGFX950FullSpeedModel |
| 3781 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32) |
| 3782 | return 79; // Write32Bit |
| 3783 | if (TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32) |
| 3784 | return 80; // Write64Bit |
| 3785 | return 81; // WriteSALU |
| 3786 | } |
| 3787 | break; |
| 3788 | case 36: // V_ACCVGPR_WRITE_B32_e64 |
| 3789 | if (SchedModel->getProcessorID() == 8) { // SIQuarterSpeedModel |
| 3790 | if (TII->hasVGPRUses(*MI)) |
| 3791 | return 82; // Write64Bit_MIVGPRRead |
| 3792 | return 83; // Write64Bit_ReadDefault |
| 3793 | } |
| 3794 | break; |
| 3795 | case 39: // V_MFMA_F32_32X32X16_BF16_e64_V_MFMA_F32_32X32X16_BF16_mac_e64_V_MFMA_F32_32X32X16_BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_e64_V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_e64_V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_BF8_FP8_vgprcd_e64_V_MFMA_F32_32X32X16_F16_e64_V_MFMA_F32_32X32X16_F16_mac_e64_V_MFMA_F32_32X32X16_F16_mac_vgprcd_e64_V_MFMA_F32_32X32X16_F16_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_e64_V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_BF8_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_e64_V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64_V_MFMA_F32_32X32X16_FP8_FP8_vgprcd_e64_V_MFMA_F32_32X32X1F32_e64_V_MFMA_F32_32X32X1F32_mac_e64_V_MFMA_F32_32X32X1F32_mac_vgprcd_e64_V_MFMA_F32_32X32X1F32_vgprcd_e64_V_MFMA_F32_32X32X2BF16_e64_V_MFMA_F32_32X32X2BF16_mac_e64_V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X2BF16_vgprcd_e64_V_MFMA_F32_32X32X2F32_e64_V_MFMA_F32_32X32X2F32_mac_e64_V_MFMA_F32_32X32X2F32_mac_vgprcd_e64_V_MFMA_F32_32X32X2F32_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_e64_V_MFMA_F32_32X32X4BF16_1K_mac_e64_V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X4BF16_e64_V_MFMA_F32_32X32X4BF16_mac_e64_V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64_V_MFMA_F32_32X32X4BF16_vgprcd_e64_V_MFMA_F32_32X32X4F16_e64_V_MFMA_F32_32X32X4F16_mac_e64_V_MFMA_F32_32X32X4F16_mac_vgprcd_e64_V_MFMA_F32_32X32X4F16_vgprcd_e64_V_MFMA_F32_32X32X4XF32_e64_V_MFMA_F32_32X32X4XF32_mac_e64_V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64_V_MFMA_F32_32X32X4XF32_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_e64_V_MFMA_F32_32X32X8BF16_1K_mac_e64_V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64_V_MFMA_F32_32X32X8BF16_1K_vgprcd_e64_V_MFMA_F32_32X32X8F16_e64_V_MFMA_F32_32X32X8F16_mac_e64_V_MFMA_F32_32X32X8F16_mac_vgprcd_e64_V_MFMA_F32_32X32X8F16_vgprcd_e64_V_MFMA_I32_32X32X16I8_e64_V_MFMA_I32_32X32X16I8_mac_e64_V_MFMA_I32_32X32X16I8_mac_vgprcd_e64_V_MFMA_I32_32X32X16I8_vgprcd_e64_V_MFMA_I32_32X32X32_I8_e64_V_MFMA_I32_32X32X32_I8_mac_e64_V_MFMA_I32_32X32X32_I8_mac_vgprcd_e64_V_MFMA_I32_32X32X32_I8_vgprcd_e64_V_MFMA_I32_32X32X4I8_e64_V_MFMA_I32_32X32X4I8_mac_e64_V_MFMA_I32_32X32X4I8_mac_vgprcd_e64_V_MFMA_I32_32X32X4I8_vgprcd_e64_V_MFMA_I32_32X32X8I8_e64_V_MFMA_I32_32X32X8I8_mac_e64_V_MFMA_I32_32X32X8I8_mac_vgprcd_e64_V_MFMA_I32_32X32X8I8_vgprcd_e64_V_MFMA_F32_32X32X16_BF16_gfx940_acd_V_MFMA_F32_32X32X16_BF16_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_BF8_FP8_gfx940_vcd_V_MFMA_F32_32X32X16_F16_gfx940_acd_V_MFMA_F32_32X32X16_F16_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_BF8_gfx940_vcd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_acd_V_MFMA_F32_32X32X16_FP8_FP8_gfx940_vcd_V_MFMA_F32_32X32X1F32_gfx90a_acd_V_MFMA_F32_32X32X1F32_gfx90a_vcd_V_MFMA_F32_32X32X1F32_gfx940_acd_V_MFMA_F32_32X32X1F32_gfx940_vcd_V_MFMA_F32_32X32X1F32_vi_V_MFMA_F32_32X32X2BF16_gfx90a_acd_V_MFMA_F32_32X32X2BF16_gfx90a_vcd_V_MFMA_F32_32X32X2BF16_vi_V_MFMA_F32_32X32X2F32_gfx90a_acd_V_MFMA_F32_32X32X2F32_gfx90a_vcd_V_MFMA_F32_32X32X2F32_gfx940_acd_V_MFMA_F32_32X32X2F32_gfx940_vcd_V_MFMA_F32_32X32X2F32_vi_V_MFMA_F32_32X32X4BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X4BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_1K_gfx940_acd_V_MFMA_F32_32X32X4BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X4BF16_gfx90a_acd_V_MFMA_F32_32X32X4BF16_gfx90a_vcd_V_MFMA_F32_32X32X4BF16_vi_V_MFMA_F32_32X32X4F16_gfx90a_acd_V_MFMA_F32_32X32X4F16_gfx90a_vcd_V_MFMA_F32_32X32X4F16_gfx940_acd_V_MFMA_F32_32X32X4F16_gfx940_vcd_V_MFMA_F32_32X32X4F16_vi_V_MFMA_F32_32X32X4XF32_gfx940_acd_V_MFMA_F32_32X32X4XF32_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_acd_V_MFMA_F32_32X32X8BF16_1K_gfx90a_vcd_V_MFMA_F32_32X32X8BF16_1K_gfx940_acd_V_MFMA_F32_32X32X8BF16_1K_gfx940_vcd_V_MFMA_F32_32X32X8F16_gfx90a_acd_V_MFMA_F32_32X32X8F16_gfx90a_vcd_V_MFMA_F32_32X32X8F16_gfx940_acd_V_MFMA_F32_32X32X8F16_gfx940_vcd_V_MFMA_F32_32X32X8F16_vi_V_MFMA_I32_32X32X16I8_gfx940_acd_V_MFMA_I32_32X32X16I8_gfx940_vcd_V_MFMA_I32_32X32X32_I8_gfx940_acd_V_MFMA_I32_32X32X32_I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_gfx90a_acd_V_MFMA_I32_32X32X4I8_gfx90a_vcd_V_MFMA_I32_32X32X4I8_gfx940_acd_V_MFMA_I32_32X32X4I8_gfx940_vcd_V_MFMA_I32_32X32X4I8_vi_V_MFMA_I32_32X32X8I8_gfx90a_acd_V_MFMA_I32_32X32X8I8_gfx90a_vcd_V_MFMA_I32_32X32X8I8_vi |
| 3796 | if (SchedModel->getProcessorID() == 11) { // SIDPGFX950FullSpeedModel |
| 3797 | if ( |
| 3798 | TII->getNamedOperand(*MI, AMDGPU::OpName::cbsz)->getImm() <= AMDGPU::MFMAScaleFormats::FP8_E5M2 || |
| 3799 | TII->getNamedOperand(*MI, AMDGPU::OpName::blgp)->getImm() <= AMDGPU::MFMAScaleFormats::FP8_E5M2 |
| 3800 | ) |
| 3801 | return 84; // Write16PassMAI_MIMFMARead |
| 3802 | return 85; // Write8PassMAI_MIMFMARead |
| 3803 | } |
| 3804 | break; |
| 3805 | case 54: // V_MFMA_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd |
| 3806 | if (SchedModel->getProcessorID() == 11) { // SIDPGFX950FullSpeedModel |
| 3807 | if ( |
| 3808 | TII->getNamedOperand(*MI, AMDGPU::OpName::cbsz)->getImm() <= AMDGPU::MFMAScaleFormats::FP8_E5M2 || |
| 3809 | TII->getNamedOperand(*MI, AMDGPU::OpName::blgp)->getImm() <= AMDGPU::MFMAScaleFormats::FP8_E5M2 |
| 3810 | ) |
| 3811 | return 85; // Write8PassMAI_MIMFMARead |
| 3812 | return 86; // Write4PassMAI_MIMFMARead |
| 3813 | } |
| 3814 | break; |
| 3815 | case 55: // V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_gfx940_vcd |
| 3816 | if (SchedModel->getProcessorID() == 11) { // SIDPGFX950FullSpeedModel |
| 3817 | if ( |
| 3818 | TII->getNamedOperand(*MI, AMDGPU::OpName::cbsz)->getImm() <= AMDGPU::MFMAScaleFormats::FP8_E5M2 || |
| 3819 | TII->getNamedOperand(*MI, AMDGPU::OpName::blgp)->getImm() <= AMDGPU::MFMAScaleFormats::FP8_E5M2 |
| 3820 | ) |
| 3821 | return 85; // Write8PassMAI_MIMFMARead |
| 3822 | return 86; // Write4PassMAI_MIMFMARead |
| 3823 | } |
| 3824 | break; |
| 3825 | case 56: // V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_mac_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_vgprcd_e64_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f4_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f6_f8_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f4_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f6_gfx940_vcd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_acd_V_MFMA_SCALE_F32_32X32X64_F8F6F4_f8_f8_gfx940_vcd |
| 3826 | if (SchedModel->getProcessorID() == 11) { // SIDPGFX950FullSpeedModel |
| 3827 | if ( |
| 3828 | TII->getNamedOperand(*MI, AMDGPU::OpName::cbsz)->getImm() <= AMDGPU::MFMAScaleFormats::FP8_E5M2 || |
| 3829 | TII->getNamedOperand(*MI, AMDGPU::OpName::blgp)->getImm() <= AMDGPU::MFMAScaleFormats::FP8_E5M2 |
| 3830 | ) |
| 3831 | return 84; // Write16PassMAI_MIMFMARead |
| 3832 | return 85; // Write8PassMAI_MIMFMARead |
| 3833 | } |
| 3834 | break; |
| 3835 | case 67: // V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_threeaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr |
| 3836 | if (SchedModel->getProcessorID() == 3) { // GFX125xGenericSpeedModel |
| 3837 | if ( |
| 3838 | TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_a_fmt)->getImm() == AMDGPU::WMMA::MATRIX_FMT_FP4 && |
| 3839 | TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_b_fmt)->getImm() <= AMDGPU::WMMA::MATRIX_FMT_FP4 |
| 3840 | ) |
| 3841 | return 89; // WriteXDL4PassWMMA |
| 3842 | return 90; // WriteXDL8PassWMMA |
| 3843 | } |
| 3844 | if (SchedModel->getProcessorID() == 5) { // GFX1250SpeedModel |
| 3845 | if ( |
| 3846 | TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_a_fmt)->getImm() != AMDGPU::WMMA::MATRIX_FMT_FP4 || |
| 3847 | TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_b_fmt)->getImm() != AMDGPU::WMMA::MATRIX_FMT_FP4 |
| 3848 | ) |
| 3849 | return 87; // WriteXDL2PassWMMA |
| 3850 | return 88; // WriteXDL1PassWMMA |
| 3851 | } |
| 3852 | if (SchedModel->getProcessorID() == 6) { // GFX1251SpeedModel |
| 3853 | if ( |
| 3854 | TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_a_fmt)->getImm() == AMDGPU::WMMA::MATRIX_FMT_FP4 && |
| 3855 | TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_b_fmt)->getImm() <= AMDGPU::WMMA::MATRIX_FMT_FP4 |
| 3856 | ) |
| 3857 | return 89; // WriteXDL4PassWMMA |
| 3858 | return 90; // WriteXDL8PassWMMA |
| 3859 | } |
| 3860 | break; |
| 3861 | case 68: // V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_V_WMMA_F32_16X16X128_F8F6F4_f4_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f4_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f6_f8_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f4_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f6_w32_twoaddr_gfx1250_V_WMMA_F32_16X16X128_F8F6F4_f8_f8_w32_twoaddr_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE16_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f4_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f6_f8_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f4_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f6_w32_gfx1250_V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_gfx1250 |
| 3862 | if (SchedModel->getProcessorID() == 3) { // GFX125xGenericSpeedModel |
| 3863 | if ( |
| 3864 | TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_a_fmt)->getImm() == AMDGPU::WMMA::MATRIX_FMT_FP4 && |
| 3865 | TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_b_fmt)->getImm() <= AMDGPU::WMMA::MATRIX_FMT_FP4 |
| 3866 | ) |
| 3867 | return 89; // WriteXDL4PassWMMA |
| 3868 | return 90; // WriteXDL8PassWMMA |
| 3869 | } |
| 3870 | if (SchedModel->getProcessorID() == 5) { // GFX1250SpeedModel |
| 3871 | if ( |
| 3872 | TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_a_fmt)->getImm() != AMDGPU::WMMA::MATRIX_FMT_FP4 || |
| 3873 | TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_b_fmt)->getImm() != AMDGPU::WMMA::MATRIX_FMT_FP4 |
| 3874 | ) |
| 3875 | return 87; // WriteXDL2PassWMMA |
| 3876 | return 88; // WriteXDL1PassWMMA |
| 3877 | } |
| 3878 | if (SchedModel->getProcessorID() == 6) { // GFX1251SpeedModel |
| 3879 | if ( |
| 3880 | TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_a_fmt)->getImm() == AMDGPU::WMMA::MATRIX_FMT_FP4 && |
| 3881 | TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_b_fmt)->getImm() <= AMDGPU::WMMA::MATRIX_FMT_FP4 |
| 3882 | ) |
| 3883 | return 89; // WriteXDL4PassWMMA |
| 3884 | return 90; // WriteXDL8PassWMMA |
| 3885 | } |
| 3886 | break; |
| 3887 | }; |
| 3888 | report_fatal_error("Expected a variant SchedClass" ); |
| 3889 | } // AMDGPUGenSubtargetInfo::resolveSchedClass |
| 3890 | |
| 3891 | unsigned AMDGPUGenSubtargetInfo |
| 3892 | ::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const { |
| 3893 | return AMDGPU_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID); |
| 3894 | } // AMDGPUGenSubtargetInfo::resolveVariantSchedClass |
| 3895 | |
| 3896 | unsigned AMDGPUGenSubtargetInfo::getHwModeSet() const { |
| 3897 | [[maybe_unused]] const auto *Subtarget = |
| 3898 | static_cast<const AMDGPUSubtarget *>(this); |
| 3899 | // Collect HwModes and store them as a bit set. |
| 3900 | unsigned Modes = 0; |
| 3901 | if ((Subtarget->hasMAIInsts()) && (Subtarget->needsAlignedVGPRs())) Modes |= (1 << 0); |
| 3902 | if ((!Subtarget->hasMAIInsts()) && (Subtarget->needsAlignedVGPRs()) && (Subtarget->isWave32())) Modes |= (1 << 1); |
| 3903 | if ((!Subtarget->hasMAIInsts()) && (Subtarget->needsAlignedVGPRs()) && (Subtarget->isWave64())) Modes |= (1 << 2); |
| 3904 | if ((Subtarget->isWave32()) && (!Subtarget->needsAlignedVGPRs())) Modes |= (1 << 3); |
| 3905 | return Modes; |
| 3906 | } |
| 3907 | unsigned AMDGPUGenSubtargetInfo::getHwMode(enum HwModeType type) const { |
| 3908 | unsigned Modes = getHwModeSet(); |
| 3909 | |
| 3910 | if (!Modes) |
| 3911 | return Modes; |
| 3912 | |
| 3913 | switch (type) { |
| 3914 | case HwMode_Default: |
| 3915 | return llvm::countr_zero(Modes) + 1; |
| 3916 | case HwMode_ValueType: |
| 3917 | Modes &= 15; |
| 3918 | if (!Modes) |
| 3919 | return Modes; |
| 3920 | if (!llvm::has_single_bit<unsigned>(Modes)) |
| 3921 | llvm_unreachable("Two or more HwModes for ValueType were found!" ); |
| 3922 | return llvm::countr_zero(Modes) + 1; |
| 3923 | case HwMode_RegInfo: |
| 3924 | Modes &= 15; |
| 3925 | if (!Modes) |
| 3926 | return Modes; |
| 3927 | if (!llvm::has_single_bit<unsigned>(Modes)) |
| 3928 | llvm_unreachable("Two or more HwModes for RegInfo were found!" ); |
| 3929 | return llvm::countr_zero(Modes) + 1; |
| 3930 | case HwMode_EncodingInfo: |
| 3931 | // No HwMode for EncodingInfo. |
| 3932 | return 0; |
| 3933 | } |
| 3934 | llvm_unreachable("unexpected HwModeType" ); |
| 3935 | return 0; // should not get here |
| 3936 | } |
| 3937 | const FeatureBitset &AMDGPUGenSubtargetInfo::getInlineIgnoreFeatures() const { |
| 3938 | static constexpr FeatureBitset Features = { |
| 3939 | AMDGPU::FeatureEnableLoadStoreOpt, |
| 3940 | AMDGPU::FeatureEnableSIScheduler, |
| 3941 | AMDGPU::FeatureEnableUnsafeDSOffsetFolding, |
| 3942 | AMDGPU::FeatureXNACK, |
| 3943 | AMDGPU::FeatureAutoWaitcntBeforeBarrier, |
| 3944 | AMDGPU::FeatureFastFMAF32, |
| 3945 | AMDGPU::FeatureHalfRate64Ops, |
| 3946 | AMDGPU::FeatureSGPRInitBug, |
| 3947 | AMDGPU::FeatureSupportsWGP, |
| 3948 | AMDGPU::FeatureTrapHandler, |
| 3949 | AMDGPU::FeatureUnalignedAccessMode, |
| 3950 | AMDGPU::FeatureUnalignedScratchAccess, |
| 3951 | AMDGPU::FeatureXNACKOnOffModes, |
| 3952 | AMDGPU::FeatureSupportsSRAMECC, |
| 3953 | AMDGPU::FeatureSupportsWave32, |
| 3954 | AMDGPU::FeatureSupportsWave64, |
| 3955 | AMDGPU::FeatureSupportsXNACK, |
| 3956 | AMDGPU::FeatureUseFlatForGlobal, |
| 3957 | }; |
| 3958 | return Features; |
| 3959 | } |
| 3960 | |
| 3961 | const FeatureBitset &AMDGPUGenSubtargetInfo::getInlineInverseFeatures() const { |
| 3962 | static constexpr FeatureBitset Features = { |
| 3963 | }; |
| 3964 | return Features; |
| 3965 | } |
| 3966 | |
| 3967 | const FeatureBitset &AMDGPUGenSubtargetInfo::getInlineMustMatchFeatures() const { |
| 3968 | static constexpr FeatureBitset Features = { |
| 3969 | }; |
| 3970 | return Features; |
| 3971 | } |
| 3972 | |
| 3973 | |
| 3974 | } // namespace llvm |
| 3975 | |
| 3976 | #endif // GET_SUBTARGETINFO_CTOR |
| 3977 | |
| 3978 | #ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS |
| 3979 | #undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS |
| 3980 | |
| 3981 | |
| 3982 | #endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS |
| 3983 | |
| 3984 | #ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS |
| 3985 | #undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS |
| 3986 | |
| 3987 | |
| 3988 | #endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS |
| 3989 | |
| 3990 | |